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20.1
Arria 10 SoC Hardware Manager
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alt_fpga_manager.h
1
/******************************************************************************
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*
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* Copyright 2015 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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/*
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* $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/soc_a10/alt_fpga_manager.h#1 $
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*/
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#ifndef __ALT_FPGA_MANAGER_H__
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#define __ALT_FPGA_MANAGER_H__
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#include "hwlib.h"
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#include "alt_dma.h"
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43
#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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70
#ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
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#define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
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#endif
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typedef
enum
ALT_FPGA_CFG_MODE_e
79
{
84
ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC
,
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90
ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC
,
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ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_DC
,
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102
ALT_FPGA_CFG_MODE_PP16_FAST_AES_DC
,
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ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC
,
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114
ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC
,
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ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_DC
,
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ALT_FPGA_CFG_MODE_PP32_FAST_AES_DC
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}
ALT_FPGA_CFG_MODE_t
;
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137
ALT_STATUS_CODE
alt_fpga_init
(
void
);
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145
ALT_STATUS_CODE
alt_fpga_uninit
(
void
);
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161
ALT_STATUS_CODE
alt_fpga_control_enable
(
ALT_FPGA_CFG_MODE_t
mode
);
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171
ALT_STATUS_CODE
alt_fpga_control_disable
(
void
);
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bool
alt_fpga_control_is_enabled
(
void
);
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198
ALT_STATUS_CODE
alt_fpga_reset_assert
(
void
);
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214
ALT_STATUS_CODE
alt_fpga_reset_deassert
(
void
);
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220
typedef
enum
ALT_FPGA_STATUS_e
221
{
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ALT_FPGA_STATUS_F2S_CRC_ERROR
= 1 << 0,
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ALT_FPGA_STATUS_F2S_EARLY_USERMODE
= 1 << 1,
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ALT_FPGA_STATUS_F2S_USERMODE
= 1 << 2,
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ALT_FPGA_STATUS_F2S_INITDONE_OE
= 1 << 3,
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ALT_FPGA_STATUS_F2S_NSTATUS_PIN
= 1 << 4,
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ALT_FPGA_STATUS_F2S_NSTATUS_OE
= 1 << 5,
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ALT_FPGA_STATUS_F2S_CONDONE_PIN
= 1 << 6,
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ALT_FPGA_STATUS_F2S_CONDONE_OE
= 1 << 7,
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270
ALT_FPGA_STATUS_F2S_CVP_CONF_DONE
= 1 << 8,
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ALT_FPGA_STATUS_F2S_PR_READY
= 1 << 9,
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ALT_FPGA_STATUS_F2S_PR_DONE
= 1 << 10,
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285
ALT_FPGA_STATUS_F2S_PR_ERROR
= 1 << 11,
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ALT_FPGA_STATUS_F2S_NCONFIG_PIN
= 1 << 12,
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ALT_FPGA_STATUS_F2S_NCEO_OE
= 1 << 13,
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ALT_FPGA_STATUS_F2S_MSEL0
= 1 << 16,
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ALT_FPGA_STATUS_F2S_MSEL1
= 1 << 17,
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ALT_FPGA_STATUS_F2S_MSEL2
= 1 << 18,
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ALT_FPGA_STATUS_IMGCFG_FIFOEMPTY
= 1 << 24,
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ALT_FPGA_STATUS_IMGCFG_FIFOFULL
= 1 << 25,
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ALT_FPGA_STATUS_JTAGM
= 1 << 28,
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ALT_FPGA_STATUS_EMR
= 1 << 29
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}
ALT_FPGA_STATUS_t
;
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uint32_t
alt_fpga_status_get
(
void
);
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typedef
int32_t (*
alt_fpga_istream_t
)(
void
* buf,
size_t
len,
void
* user_data);
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ALT_STATUS_CODE
alt_fpga_configure
(
const
void
* buf,
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size_t
len);
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ALT_STATUS_CODE
alt_fpga_configure_list
(
const
void
** buf_list,
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const
size_t
* len_list,
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size_t
list_count);
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#if ALT_FPGA_ENABLE_DMA_SUPPORT
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ALT_STATUS_CODE alt_fpga_configure_dma(
const
void
* buf,
477
size_t
len,
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ALT_DMA_CHANNEL_t
dma_channel);
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ALT_STATUS_CODE alt_fpga_configure_list_dma(
const
void
** buf_list,
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const
size_t
* len_list,
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size_t
list_count,
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ALT_DMA_CHANNEL_t
dma_channel);
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#endif
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ALT_STATUS_CODE
alt_fpga_istream_configure
(
alt_fpga_istream_t
cfg_stream,
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void
* user_data);
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#if ALT_FPGA_ENABLE_DMA_SUPPORT
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ALT_STATUS_CODE alt_fpga_istream_configure_dma(
alt_fpga_istream_t
cfg_stream,
581
void
* user_data,
582
ALT_DMA_CHANNEL_t
dma_channel);
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#endif
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ALT_STATUS_CODE
alt_fpga_int_enable
(uint32_t mask);
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ALT_STATUS_CODE
alt_fpga_int_disable
(uint32_t mask);
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uint32_t
alt_fpga_int_get
(
void
);
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ALT_STATUS_CODE
alt_fpga_int_clear
(uint32_t mask);
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typedef
enum
ALT_FPGA_GPI_e
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{
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ALT_FPGA_GPI_0
= (int32_t)(1UL << 0),
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ALT_FPGA_GPI_1
= (int32_t)(1UL << 1),
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ALT_FPGA_GPI_2
= (int32_t)(1UL << 2),
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ALT_FPGA_GPI_3
= (int32_t)(1UL << 3),
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ALT_FPGA_GPI_4
= (int32_t)(1UL << 4),
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ALT_FPGA_GPI_5
= (int32_t)(1UL << 5),
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ALT_FPGA_GPI_6
= (int32_t)(1UL << 6),
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ALT_FPGA_GPI_7
= (int32_t)(1UL << 7),
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ALT_FPGA_GPI_8
= (int32_t)(1UL << 8),
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ALT_FPGA_GPI_9
= (int32_t)(1UL << 9),
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ALT_FPGA_GPI_10
= (int32_t)(1UL << 10),
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ALT_FPGA_GPI_11
= (int32_t)(1UL << 11),
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ALT_FPGA_GPI_12
= (int32_t)(1UL << 12),
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ALT_FPGA_GPI_13
= (int32_t)(1UL << 13),
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ALT_FPGA_GPI_14
= (int32_t)(1UL << 14),
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ALT_FPGA_GPI_15
= (int32_t)(1UL << 15),
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ALT_FPGA_GPI_16
= (int32_t)(1UL << 16),
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ALT_FPGA_GPI_17
= (int32_t)(1UL << 17),
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ALT_FPGA_GPI_18
= (int32_t)(1UL << 18),
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ALT_FPGA_GPI_19
= (int32_t)(1UL << 19),
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ALT_FPGA_GPI_20
= (int32_t)(1UL << 20),
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ALT_FPGA_GPI_21
= (int32_t)(1UL << 21),
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ALT_FPGA_GPI_22
= (int32_t)(1UL << 22),
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ALT_FPGA_GPI_23
= (int32_t)(1UL << 23),
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ALT_FPGA_GPI_24
= (int32_t)(1UL << 24),
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769
ALT_FPGA_GPI_25
= (int32_t)(1UL << 25),
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772
ALT_FPGA_GPI_26
= (int32_t)(1UL << 26),
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ALT_FPGA_GPI_27
= (int32_t)(1UL << 27),
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ALT_FPGA_GPI_28
= (int32_t)(1UL << 28),
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ALT_FPGA_GPI_29
= (int32_t)(1UL << 29),
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ALT_FPGA_GPI_30
= (int32_t)(1UL << 30),
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ALT_FPGA_GPI_31
= (int32_t)(1UL << 31)
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}
ALT_FPGA_GPI_t
;
790
808
uint32_t
alt_fpga_gpi_read
(uint32_t mask);
809
814
typedef
enum
ALT_FPGA_GPO_e
815
{
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ALT_FPGA_GPO_0
= (int32_t)(1UL << 0),
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820
ALT_FPGA_GPO_1
= (int32_t)(1UL << 1),
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823
ALT_FPGA_GPO_2
= (int32_t)(1UL << 2),
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826
ALT_FPGA_GPO_3
= (int32_t)(1UL << 3),
827
829
ALT_FPGA_GPO_4
= (int32_t)(1UL << 4),
830
832
ALT_FPGA_GPO_5
= (int32_t)(1UL << 5),
833
835
ALT_FPGA_GPO_6
= (int32_t)(1UL << 6),
836
838
ALT_FPGA_GPO_7
= (int32_t)(1UL << 7),
839
841
ALT_FPGA_GPO_8
= (int32_t)(1UL << 8),
842
844
ALT_FPGA_GPO_9
= (int32_t)(1UL << 9),
845
847
ALT_FPGA_GPO_10
= (int32_t)(1UL << 10),
848
850
ALT_FPGA_GPO_11
= (int32_t)(1UL << 11),
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853
ALT_FPGA_GPO_12
= (int32_t)(1UL << 12),
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856
ALT_FPGA_GPO_13
= (int32_t)(1UL << 13),
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859
ALT_FPGA_GPO_14
= (int32_t)(1UL << 14),
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862
ALT_FPGA_GPO_15
= (int32_t)(1UL << 15),
863
865
ALT_FPGA_GPO_16
= (int32_t)(1UL << 16),
866
868
ALT_FPGA_GPO_17
= (int32_t)(1UL << 17),
869
871
ALT_FPGA_GPO_18
= (int32_t)(1UL << 18),
872
874
ALT_FPGA_GPO_19
= (int32_t)(1UL << 19),
875
877
ALT_FPGA_GPO_20
= (int32_t)(1UL << 20),
878
880
ALT_FPGA_GPO_21
= (int32_t)(1UL << 21),
881
883
ALT_FPGA_GPO_22
= (int32_t)(1UL << 22),
884
886
ALT_FPGA_GPO_23
= (int32_t)(1UL << 23),
887
889
ALT_FPGA_GPO_24
= (int32_t)(1UL << 24),
890
892
ALT_FPGA_GPO_25
= (int32_t)(1UL << 25),
893
895
ALT_FPGA_GPO_26
= (int32_t)(1UL << 26),
896
898
ALT_FPGA_GPO_27
= (int32_t)(1UL << 27),
899
901
ALT_FPGA_GPO_28
= (int32_t)(1UL << 28),
902
904
ALT_FPGA_GPO_29
= (int32_t)(1UL << 29),
905
907
ALT_FPGA_GPO_30
= (int32_t)(1UL << 30),
908
910
ALT_FPGA_GPO_31
= (int32_t)(1UL << 31)
911
912
}
ALT_FPGA_GPO_t
;
913
938
ALT_STATUS_CODE
alt_fpga_gpo_write
(uint32_t mask, uint32_t value);
939
948
#ifdef __cplusplus
949
}
950
#endif
/* __cplusplus */
951
952
#endif
/* __ALT_FPGA_MANAGER_H__ */
include
soc_a10
alt_fpga_manager.h
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