35 #ifndef __ALT_SOCAL_SDMMC_H__
36 #define __ALT_SOCAL_SDMMC_H__
120 #define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
126 #define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
129 #define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
131 #define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
133 #define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
135 #define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
137 #define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
139 #define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
141 #define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
143 #define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
170 #define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
176 #define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
179 #define ALT_SDMMC_CTL_FIFO_RST_LSB 1
181 #define ALT_SDMMC_CTL_FIFO_RST_MSB 1
183 #define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
185 #define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
187 #define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
189 #define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
191 #define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
193 #define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
221 #define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
227 #define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
230 #define ALT_SDMMC_CTL_DMA_RST_LSB 2
232 #define ALT_SDMMC_CTL_DMA_RST_MSB 2
234 #define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
236 #define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
238 #define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
240 #define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
242 #define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
244 #define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
274 #define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
280 #define ALT_SDMMC_CTL_INT_EN_E_END 0x1
283 #define ALT_SDMMC_CTL_INT_EN_LSB 4
285 #define ALT_SDMMC_CTL_INT_EN_MSB 4
287 #define ALT_SDMMC_CTL_INT_EN_WIDTH 1
289 #define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
291 #define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
293 #define ALT_SDMMC_CTL_INT_EN_RESET 0x0
295 #define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
297 #define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
312 #define ALT_SDMMC_CTL_DMA_EN_LSB 5
314 #define ALT_SDMMC_CTL_DMA_EN_MSB 5
316 #define ALT_SDMMC_CTL_DMA_EN_WIDTH 1
318 #define ALT_SDMMC_CTL_DMA_EN_SET_MSK 0x00000020
320 #define ALT_SDMMC_CTL_DMA_EN_CLR_MSK 0xffffffdf
322 #define ALT_SDMMC_CTL_DMA_EN_RESET 0x0
324 #define ALT_SDMMC_CTL_DMA_EN_GET(value) (((value) & 0x00000020) >> 5)
326 #define ALT_SDMMC_CTL_DMA_EN_SET(value) (((value) << 5) & 0x00000020)
352 #define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
358 #define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
361 #define ALT_SDMMC_CTL_RD_WAIT_LSB 6
363 #define ALT_SDMMC_CTL_RD_WAIT_MSB 6
365 #define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
367 #define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
369 #define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
371 #define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
373 #define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
375 #define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
407 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
413 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
416 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
418 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
420 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
422 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
424 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
426 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
428 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
430 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
460 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
466 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
469 #define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
471 #define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
473 #define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
475 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
477 #define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
479 #define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
481 #define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
483 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
509 #define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
515 #define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
518 #define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
520 #define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
522 #define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
524 #define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
526 #define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
528 #define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
530 #define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
532 #define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
558 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
564 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
567 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
569 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
571 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
573 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
575 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
577 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
579 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
581 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
605 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
611 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
614 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
616 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
618 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
620 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
622 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
624 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
626 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
628 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
641 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_LSB 16
643 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_MSB 19
645 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_WIDTH 4
647 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET_MSK 0x000f0000
649 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff
651 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_RESET 0x0
653 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16)
655 #define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000)
668 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_LSB 20
670 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_MSB 23
672 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_WIDTH 4
674 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET_MSK 0x00f00000
676 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff
678 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_RESET 0x0
680 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20)
682 #define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000)
702 #define ALT_SDMMC_CTL_EN_OD_PULLUP_LSB 24
704 #define ALT_SDMMC_CTL_EN_OD_PULLUP_MSB 24
706 #define ALT_SDMMC_CTL_EN_OD_PULLUP_WIDTH 1
708 #define ALT_SDMMC_CTL_EN_OD_PULLUP_SET_MSK 0x01000000
710 #define ALT_SDMMC_CTL_EN_OD_PULLUP_CLR_MSK 0xfeffffff
712 #define ALT_SDMMC_CTL_EN_OD_PULLUP_RESET 0x0
714 #define ALT_SDMMC_CTL_EN_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24)
716 #define ALT_SDMMC_CTL_EN_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000)
743 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
749 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
752 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
754 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
756 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
758 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
760 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
762 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
764 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
766 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
779 struct ALT_SDMMC_CTL_s
781 uint32_t controller_reset : 1;
782 uint32_t fifo_reset : 1;
783 uint32_t dma_reset : 1;
785 uint32_t int_enable : 1;
786 uint32_t dma_enable : 1;
787 uint32_t read_wait : 1;
788 uint32_t send_irq_response : 1;
789 uint32_t abort_read_data : 1;
790 uint32_t send_ccsd : 1;
791 uint32_t send_auto_stop_ccsd : 1;
792 uint32_t ceata_device_interrupt_status : 1;
794 uint32_t card_voltage_a : 4;
795 uint32_t card_voltage_b : 4;
796 uint32_t enable_od_pullup : 1;
797 uint32_t use_internal_dmac : 1;
802 typedef volatile struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t;
806 #define ALT_SDMMC_CTL_RESET 0x00000000
808 #define ALT_SDMMC_CTL_OFST 0x0
852 #define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
858 #define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
861 #define ALT_SDMMC_PWREN_POWER_EN_LSB 0
863 #define ALT_SDMMC_PWREN_POWER_EN_MSB 0
865 #define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
867 #define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
869 #define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
871 #define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
873 #define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
875 #define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
888 struct ALT_SDMMC_PWREN_s
890 uint32_t power_enable : 1;
895 typedef volatile struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
899 #define ALT_SDMMC_PWREN_RESET 0x00000000
901 #define ALT_SDMMC_PWREN_OFST 0x4
929 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
931 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
933 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
935 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
937 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
939 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
941 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
943 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
957 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_LSB 8
959 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_MSB 15
961 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_WIDTH 8
963 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET_MSK 0x0000ff00
965 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_CLR_MSK 0xffff00ff
967 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_RESET 0x0
969 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_GET(value) (((value) & 0x0000ff00) >> 8)
971 #define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET(value) (((value) << 8) & 0x0000ff00)
985 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_LSB 16
987 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_MSB 23
989 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_WIDTH 8
991 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET_MSK 0x00ff0000
993 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_CLR_MSK 0xff00ffff
995 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_RESET 0x0
997 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_GET(value) (((value) & 0x00ff0000) >> 16)
999 #define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET(value) (((value) << 16) & 0x00ff0000)
1013 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_LSB 24
1015 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_MSB 31
1017 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_WIDTH 8
1019 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET_MSK 0xff000000
1021 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_CLR_MSK 0x00ffffff
1023 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_RESET 0x0
1025 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_GET(value) (((value) & 0xff000000) >> 24)
1027 #define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET(value) (((value) << 24) & 0xff000000)
1029 #ifndef __ASSEMBLY__
1040 struct ALT_SDMMC_CLKDIV_s
1042 uint32_t clk_divider0 : 8;
1043 const uint32_t clk_divider1 : 8;
1044 const uint32_t clk_divider2 : 8;
1045 const uint32_t clk_divider3 : 8;
1049 typedef volatile struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
1053 #define ALT_SDMMC_CLKDIV_RESET 0x00000000
1055 #define ALT_SDMMC_CLKDIV_OFST 0x8
1102 #define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
1105 #define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
1107 #define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 31
1109 #define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 32
1111 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0xffffffff
1113 #define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0x00000000
1115 #define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
1117 #define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0xffffffff) >> 0)
1119 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0xffffffff)
1121 #ifndef __ASSEMBLY__
1132 struct ALT_SDMMC_CLKSRC_s
1134 const uint32_t clk_source : 32;
1138 typedef volatile struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
1142 #define ALT_SDMMC_CLKSRC_RESET 0x00000000
1144 #define ALT_SDMMC_CLKSRC_OFST 0xc
1189 #define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
1195 #define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
1198 #define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
1200 #define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
1202 #define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
1204 #define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
1206 #define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
1208 #define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
1210 #define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
1212 #define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
1243 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
1249 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
1252 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
1254 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
1256 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
1258 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
1260 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
1262 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
1264 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
1266 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
1268 #ifndef __ASSEMBLY__
1279 struct ALT_SDMMC_CLKENA_s
1281 uint32_t cclk_enable : 1;
1283 uint32_t cclk_low_power : 1;
1288 typedef volatile struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
1292 #define ALT_SDMMC_CLKENA_RESET 0x00000000
1294 #define ALT_SDMMC_CLKENA_OFST 0x10
1320 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1322 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1324 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1326 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1328 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1330 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1332 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1334 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1353 #define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1355 #define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1357 #define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1359 #define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1361 #define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1363 #define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1365 #define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1367 #define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1369 #ifndef __ASSEMBLY__
1380 struct ALT_SDMMC_TMOUT_s
1382 uint32_t response_timeout : 8;
1383 uint32_t data_timeout : 24;
1387 typedef volatile struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
1391 #define ALT_SDMMC_TMOUT_RESET 0xffffff40
1393 #define ALT_SDMMC_TMOUT_OFST 0x14
1438 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1444 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1447 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1449 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1451 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1453 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1455 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1457 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1459 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1461 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1489 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1495 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1498 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1500 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1502 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1504 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1506 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1508 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1510 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1512 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1514 #ifndef __ASSEMBLY__
1525 struct ALT_SDMMC_CTYPE_s
1527 uint32_t card_width2 : 1;
1529 uint32_t card_width1 : 1;
1534 typedef volatile struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
1538 #define ALT_SDMMC_CTYPE_RESET 0x00000000
1540 #define ALT_SDMMC_CTYPE_OFST 0x18
1564 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1566 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1568 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1570 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1572 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1574 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1576 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1578 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1580 #ifndef __ASSEMBLY__
1591 struct ALT_SDMMC_BLKSIZ_s
1593 uint32_t block_size : 16;
1598 typedef volatile struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
1602 #define ALT_SDMMC_BLKSIZ_RESET 0x00000200
1604 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
1632 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1634 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1636 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1638 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1640 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1642 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1644 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1646 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1648 #ifndef __ASSEMBLY__
1659 struct ALT_SDMMC_BYTCNT_s
1661 uint32_t byte_count : 32;
1665 typedef volatile struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
1669 #define ALT_SDMMC_BYTCNT_RESET 0x00000200
1671 #define ALT_SDMMC_BYTCNT_OFST 0x20
1722 #define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1728 #define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1731 #define ALT_SDMMC_INTMSK_CD_LSB 0
1733 #define ALT_SDMMC_INTMSK_CD_MSB 0
1735 #define ALT_SDMMC_INTMSK_CD_WIDTH 1
1737 #define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1739 #define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1741 #define ALT_SDMMC_INTMSK_CD_RESET 0x0
1743 #define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1745 #define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1768 #define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1774 #define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1777 #define ALT_SDMMC_INTMSK_RE_LSB 1
1779 #define ALT_SDMMC_INTMSK_RE_MSB 1
1781 #define ALT_SDMMC_INTMSK_RE_WIDTH 1
1783 #define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1785 #define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1787 #define ALT_SDMMC_INTMSK_RE_RESET 0x0
1789 #define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1791 #define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1814 #define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1820 #define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1823 #define ALT_SDMMC_INTMSK_CMD_LSB 2
1825 #define ALT_SDMMC_INTMSK_CMD_MSB 2
1827 #define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1829 #define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1831 #define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1833 #define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1835 #define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1837 #define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1860 #define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1866 #define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1869 #define ALT_SDMMC_INTMSK_DTO_LSB 3
1871 #define ALT_SDMMC_INTMSK_DTO_MSB 3
1873 #define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1875 #define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1877 #define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1879 #define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1881 #define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1883 #define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1906 #define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1912 #define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1915 #define ALT_SDMMC_INTMSK_TXDR_LSB 4
1917 #define ALT_SDMMC_INTMSK_TXDR_MSB 4
1919 #define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1921 #define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1923 #define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1925 #define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1927 #define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1929 #define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1952 #define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1958 #define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1961 #define ALT_SDMMC_INTMSK_RXDR_LSB 5
1963 #define ALT_SDMMC_INTMSK_RXDR_MSB 5
1965 #define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1967 #define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1969 #define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1971 #define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1973 #define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1975 #define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1998 #define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
2004 #define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
2007 #define ALT_SDMMC_INTMSK_RCRC_LSB 6
2009 #define ALT_SDMMC_INTMSK_RCRC_MSB 6
2011 #define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
2013 #define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
2015 #define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
2017 #define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
2019 #define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
2021 #define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
2044 #define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
2050 #define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
2053 #define ALT_SDMMC_INTMSK_DCRC_LSB 7
2055 #define ALT_SDMMC_INTMSK_DCRC_MSB 7
2057 #define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
2059 #define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
2061 #define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
2063 #define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
2065 #define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
2067 #define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
2090 #define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
2096 #define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
2099 #define ALT_SDMMC_INTMSK_RTO_LSB 8
2101 #define ALT_SDMMC_INTMSK_RTO_MSB 8
2103 #define ALT_SDMMC_INTMSK_RTO_WIDTH 1
2105 #define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
2107 #define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
2109 #define ALT_SDMMC_INTMSK_RTO_RESET 0x0
2111 #define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
2113 #define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
2136 #define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
2142 #define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
2145 #define ALT_SDMMC_INTMSK_DRT_LSB 9
2147 #define ALT_SDMMC_INTMSK_DRT_MSB 9
2149 #define ALT_SDMMC_INTMSK_DRT_WIDTH 1
2151 #define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
2153 #define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
2155 #define ALT_SDMMC_INTMSK_DRT_RESET 0x0
2157 #define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
2159 #define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
2182 #define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
2188 #define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
2191 #define ALT_SDMMC_INTMSK_HTO_LSB 10
2193 #define ALT_SDMMC_INTMSK_HTO_MSB 10
2195 #define ALT_SDMMC_INTMSK_HTO_WIDTH 1
2197 #define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
2199 #define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
2201 #define ALT_SDMMC_INTMSK_HTO_RESET 0x0
2203 #define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
2205 #define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
2228 #define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
2234 #define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
2237 #define ALT_SDMMC_INTMSK_FRUN_LSB 11
2239 #define ALT_SDMMC_INTMSK_FRUN_MSB 11
2241 #define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
2243 #define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
2245 #define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
2247 #define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
2249 #define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
2251 #define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
2274 #define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
2280 #define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
2283 #define ALT_SDMMC_INTMSK_HLE_LSB 12
2285 #define ALT_SDMMC_INTMSK_HLE_MSB 12
2287 #define ALT_SDMMC_INTMSK_HLE_WIDTH 1
2289 #define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
2291 #define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
2293 #define ALT_SDMMC_INTMSK_HLE_RESET 0x0
2295 #define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
2297 #define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
2320 #define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2326 #define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2329 #define ALT_SDMMC_INTMSK_SBE_LSB 13
2331 #define ALT_SDMMC_INTMSK_SBE_MSB 13
2333 #define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2335 #define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2337 #define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2339 #define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2341 #define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2343 #define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2366 #define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2372 #define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2375 #define ALT_SDMMC_INTMSK_ACD_LSB 14
2377 #define ALT_SDMMC_INTMSK_ACD_MSB 14
2379 #define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2381 #define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2383 #define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2385 #define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2387 #define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2389 #define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2412 #define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2418 #define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2421 #define ALT_SDMMC_INTMSK_EBE_LSB 15
2423 #define ALT_SDMMC_INTMSK_EBE_MSB 15
2425 #define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2427 #define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2429 #define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2431 #define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2433 #define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2435 #define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2463 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2469 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2472 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2474 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 31
2476 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 16
2478 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0xffff0000
2480 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0x0000ffff
2482 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2484 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0xffff0000) >> 16)
2486 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0xffff0000)
2488 #ifndef __ASSEMBLY__
2499 struct ALT_SDMMC_INTMSK_s
2517 uint32_t sdio_int_mask : 16;
2521 typedef volatile struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t;
2525 #define ALT_SDMMC_INTMSK_RESET 0x00000000
2527 #define ALT_SDMMC_INTMSK_OFST 0x24
2550 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2552 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2554 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2556 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2558 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2560 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2562 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2564 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2566 #ifndef __ASSEMBLY__
2577 struct ALT_SDMMC_CMDARG_s
2579 uint32_t cmd_arg : 32;
2583 typedef volatile struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
2587 #define ALT_SDMMC_CMDARG_RESET 0x00000000
2589 #define ALT_SDMMC_CMDARG_OFST 0x28
2634 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2636 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2638 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2640 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2642 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2644 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2646 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2648 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2672 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x0
2678 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x1
2681 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2683 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2685 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2687 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2689 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2691 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2693 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2695 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2719 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2725 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2728 #define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2730 #define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2732 #define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2734 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2736 #define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2738 #define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2740 #define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2742 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2769 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2775 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2778 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2780 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2782 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2784 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2786 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2788 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2790 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2792 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2816 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2822 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2825 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2827 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2829 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2831 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2833 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2835 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2837 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2839 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2865 #define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2871 #define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2874 #define ALT_SDMMC_CMD_RD_WR_LSB 10
2876 #define ALT_SDMMC_CMD_RD_WR_MSB 10
2878 #define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2880 #define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2882 #define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2884 #define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2886 #define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2888 #define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2914 #define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2920 #define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2923 #define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2925 #define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2927 #define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2929 #define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2931 #define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2933 #define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2935 #define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2937 #define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2976 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2982 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2985 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2987 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2989 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2991 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2993 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2995 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2997 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2999 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
3031 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
3037 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
3040 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
3042 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
3044 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
3046 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
3048 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
3050 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
3052 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
3054 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
3094 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
3100 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
3103 #define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
3105 #define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
3107 #define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
3109 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
3111 #define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
3113 #define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
3115 #define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
3117 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
3150 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
3156 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
3159 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
3161 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
3163 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
3165 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
3167 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
3169 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
3171 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
3173 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
3194 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
3196 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
3198 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
3200 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
3202 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
3204 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
3206 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
3208 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
3246 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
3252 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
3255 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
3257 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
3259 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
3261 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
3263 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
3265 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
3267 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
3269 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
3305 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
3311 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
3314 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
3316 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
3318 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
3320 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
3322 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
3324 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
3326 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
3328 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
3368 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
3375 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
3378 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
3380 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
3382 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
3384 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
3386 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
3388 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
3390 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
3392 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
3418 #define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3424 #define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3427 #define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3429 #define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3431 #define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3433 #define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3435 #define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3437 #define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3439 #define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3441 #define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3466 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3472 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3475 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3477 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3479 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3481 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3483 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3485 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3487 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3489 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3512 #define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3518 #define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3521 #define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3523 #define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3525 #define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3527 #define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3529 #define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3531 #define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3533 #define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3535 #define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3561 #define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3567 #define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3570 #define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3572 #define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3574 #define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3576 #define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3578 #define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3580 #define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3582 #define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3584 #define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3610 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3616 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3619 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3621 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3623 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3625 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3627 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3629 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3631 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3633 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3661 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3667 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3670 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3672 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3674 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3676 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3678 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3680 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3682 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3684 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3714 #define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3720 #define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3723 #define ALT_SDMMC_CMD_START_CMD_LSB 31
3725 #define ALT_SDMMC_CMD_START_CMD_MSB 31
3727 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3729 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3731 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3733 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3735 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3737 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3739 #ifndef __ASSEMBLY__
3750 struct ALT_SDMMC_CMD_s
3752 uint32_t cmd_index : 6;
3753 uint32_t response_expect : 1;
3754 uint32_t response_length : 1;
3755 uint32_t check_response_crc : 1;
3756 uint32_t data_expected : 1;
3757 uint32_t read_write : 1;
3758 uint32_t transfer_mode : 1;
3759 uint32_t send_auto_stop : 1;
3760 uint32_t wait_prvdata_complete : 1;
3761 uint32_t stop_abort_cmd : 1;
3762 uint32_t send_initialization : 1;
3763 uint32_t card_number : 5;
3764 uint32_t update_clock_registers_only : 1;
3765 uint32_t read_ceata_device : 1;
3766 uint32_t ccs_expected : 1;
3767 uint32_t enable_boot : 1;
3768 uint32_t expect_boot_ack : 1;
3769 uint32_t disable_boot : 1;
3770 uint32_t boot_mode : 1;
3771 uint32_t volt_switch : 1;
3772 uint32_t use_hold_reg : 1;
3774 uint32_t start_cmd : 1;
3778 typedef volatile struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
3782 #define ALT_SDMMC_CMD_RESET 0x20000000
3784 #define ALT_SDMMC_CMD_OFST 0x2c
3807 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3809 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3811 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3813 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3815 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3817 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3819 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3821 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3823 #ifndef __ASSEMBLY__
3834 struct ALT_SDMMC_RESP0_s
3836 const uint32_t response0 : 32;
3840 typedef volatile struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
3844 #define ALT_SDMMC_RESP0_RESET 0x00000000
3846 #define ALT_SDMMC_RESP0_OFST 0x30
3874 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3876 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3878 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3880 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3882 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3884 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3886 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3888 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3890 #ifndef __ASSEMBLY__
3901 struct ALT_SDMMC_RESP1_s
3903 const uint32_t response1 : 32;
3907 typedef volatile struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
3911 #define ALT_SDMMC_RESP1_RESET 0x00000000
3913 #define ALT_SDMMC_RESP1_OFST 0x34
3936 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3938 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3940 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3942 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3944 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3946 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3948 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3950 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3952 #ifndef __ASSEMBLY__
3963 struct ALT_SDMMC_RESP2_s
3965 const uint32_t response2 : 32;
3969 typedef volatile struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
3973 #define ALT_SDMMC_RESP2_RESET 0x00000000
3975 #define ALT_SDMMC_RESP2_OFST 0x38
3998 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
4000 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
4002 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
4004 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
4006 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
4008 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
4010 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
4012 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
4014 #ifndef __ASSEMBLY__
4025 struct ALT_SDMMC_RESP3_s
4027 const uint32_t response3 : 32;
4031 typedef volatile struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
4035 #define ALT_SDMMC_RESP3_RESET 0x00000000
4037 #define ALT_SDMMC_RESP3_OFST 0x3c
4087 #define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
4093 #define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
4096 #define ALT_SDMMC_MINTSTS_CD_LSB 0
4098 #define ALT_SDMMC_MINTSTS_CD_MSB 0
4100 #define ALT_SDMMC_MINTSTS_CD_WIDTH 1
4102 #define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
4104 #define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
4106 #define ALT_SDMMC_MINTSTS_CD_RESET 0x0
4108 #define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4110 #define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4132 #define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
4138 #define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
4141 #define ALT_SDMMC_MINTSTS_RESP_LSB 1
4143 #define ALT_SDMMC_MINTSTS_RESP_MSB 1
4145 #define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
4147 #define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
4149 #define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
4151 #define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
4153 #define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
4155 #define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
4177 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
4183 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
4186 #define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
4188 #define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
4190 #define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
4192 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
4194 #define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
4196 #define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
4198 #define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
4200 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
4222 #define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
4228 #define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
4231 #define ALT_SDMMC_MINTSTS_DT_LSB 3
4233 #define ALT_SDMMC_MINTSTS_DT_MSB 3
4235 #define ALT_SDMMC_MINTSTS_DT_WIDTH 1
4237 #define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
4239 #define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
4241 #define ALT_SDMMC_MINTSTS_DT_RESET 0x0
4243 #define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
4245 #define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
4267 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
4273 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
4276 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
4278 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
4280 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
4282 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
4284 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
4286 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
4288 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
4290 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
4312 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
4318 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
4321 #define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
4323 #define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
4325 #define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
4327 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
4329 #define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
4331 #define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
4333 #define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
4335 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
4357 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
4363 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
4366 #define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
4368 #define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
4370 #define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
4372 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
4374 #define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
4376 #define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
4378 #define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
4380 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
4402 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
4408 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
4411 #define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
4413 #define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
4415 #define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
4417 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
4419 #define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
4421 #define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
4423 #define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
4425 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
4447 #define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4453 #define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4456 #define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4458 #define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4460 #define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4462 #define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4464 #define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4466 #define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4468 #define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4470 #define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4492 #define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4498 #define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4501 #define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4503 #define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4505 #define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4507 #define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4509 #define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4511 #define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4513 #define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4515 #define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4537 #define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4543 #define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4546 #define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4548 #define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4550 #define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4552 #define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4554 #define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4556 #define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4558 #define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4560 #define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4582 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4588 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4591 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4593 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4595 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4597 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4599 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4601 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4603 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4605 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4627 #define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4633 #define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4636 #define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4638 #define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4640 #define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4642 #define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4644 #define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4646 #define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4648 #define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4650 #define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4672 #define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4678 #define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4681 #define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4683 #define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4685 #define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4687 #define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4689 #define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4691 #define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4693 #define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4695 #define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4717 #define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4723 #define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4726 #define ALT_SDMMC_MINTSTS_ACD_LSB 14
4728 #define ALT_SDMMC_MINTSTS_ACD_MSB 14
4730 #define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4732 #define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4734 #define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4736 #define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4738 #define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4740 #define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4762 #define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4768 #define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4771 #define ALT_SDMMC_MINTSTS_EBE_LSB 15
4773 #define ALT_SDMMC_MINTSTS_EBE_MSB 15
4775 #define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4777 #define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4779 #define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4781 #define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4783 #define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4785 #define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4816 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4822 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4825 #define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4827 #define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 31
4829 #define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 16
4831 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0xffff0000
4833 #define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
4835 #define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4837 #define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
4839 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
4841 #ifndef __ASSEMBLY__
4852 struct ALT_SDMMC_MINTSTS_s
4854 const uint32_t cd : 1;
4855 const uint32_t resp : 1;
4856 const uint32_t cmd_done : 1;
4857 const uint32_t dt : 1;
4858 const uint32_t dttxfifodr : 1;
4859 const uint32_t rxfifodr : 1;
4860 const uint32_t respcrcerr : 1;
4861 const uint32_t datacrcerr : 1;
4862 const uint32_t respto : 1;
4863 const uint32_t datardto : 1;
4864 const uint32_t dshto : 1;
4865 const uint32_t fifoovunerr : 1;
4866 const uint32_t hlwerr : 1;
4867 const uint32_t strerr : 1;
4868 const uint32_t acd : 1;
4869 const uint32_t ebe : 1;
4870 const uint32_t sdio_interrupt : 16;
4874 typedef volatile struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
4878 #define ALT_SDMMC_MINTSTS_RESET 0x00000000
4880 #define ALT_SDMMC_MINTSTS_OFST 0x40
4931 #define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4937 #define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4940 #define ALT_SDMMC_RINTSTS_CD_LSB 0
4942 #define ALT_SDMMC_RINTSTS_CD_MSB 0
4944 #define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4946 #define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4948 #define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4950 #define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4952 #define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4954 #define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4977 #define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4983 #define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4986 #define ALT_SDMMC_RINTSTS_RE_LSB 1
4988 #define ALT_SDMMC_RINTSTS_RE_MSB 1
4990 #define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4992 #define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4994 #define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4996 #define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4998 #define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
5000 #define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
5023 #define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
5029 #define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
5032 #define ALT_SDMMC_RINTSTS_CMD_LSB 2
5034 #define ALT_SDMMC_RINTSTS_CMD_MSB 2
5036 #define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
5038 #define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
5040 #define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
5042 #define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
5044 #define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
5046 #define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
5069 #define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
5075 #define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
5078 #define ALT_SDMMC_RINTSTS_DTO_LSB 3
5080 #define ALT_SDMMC_RINTSTS_DTO_MSB 3
5082 #define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
5084 #define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
5086 #define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
5088 #define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
5090 #define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
5092 #define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
5115 #define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
5121 #define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
5124 #define ALT_SDMMC_RINTSTS_TXDR_LSB 4
5126 #define ALT_SDMMC_RINTSTS_TXDR_MSB 4
5128 #define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
5130 #define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
5132 #define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
5134 #define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
5136 #define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
5138 #define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
5161 #define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
5167 #define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
5170 #define ALT_SDMMC_RINTSTS_RXDR_LSB 5
5172 #define ALT_SDMMC_RINTSTS_RXDR_MSB 5
5174 #define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
5176 #define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
5178 #define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
5180 #define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
5182 #define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
5184 #define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
5207 #define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
5213 #define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
5216 #define ALT_SDMMC_RINTSTS_RCRC_LSB 6
5218 #define ALT_SDMMC_RINTSTS_RCRC_MSB 6
5220 #define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
5222 #define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
5224 #define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
5226 #define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
5228 #define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
5230 #define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
5253 #define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
5259 #define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
5262 #define ALT_SDMMC_RINTSTS_DCRC_LSB 7
5264 #define ALT_SDMMC_RINTSTS_DCRC_MSB 7
5266 #define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
5268 #define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
5270 #define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
5272 #define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
5274 #define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
5276 #define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
5300 #define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
5306 #define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
5309 #define ALT_SDMMC_RINTSTS_BAR_LSB 8
5311 #define ALT_SDMMC_RINTSTS_BAR_MSB 8
5313 #define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
5315 #define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
5317 #define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
5319 #define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
5321 #define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
5323 #define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
5347 #define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
5353 #define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
5356 #define ALT_SDMMC_RINTSTS_BDS_LSB 9
5358 #define ALT_SDMMC_RINTSTS_BDS_MSB 9
5360 #define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
5362 #define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
5364 #define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
5366 #define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
5368 #define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
5370 #define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
5395 #define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
5401 #define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
5404 #define ALT_SDMMC_RINTSTS_HTO_LSB 10
5406 #define ALT_SDMMC_RINTSTS_HTO_MSB 10
5408 #define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
5410 #define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
5412 #define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
5414 #define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
5416 #define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
5418 #define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
5441 #define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5447 #define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5450 #define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5452 #define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5454 #define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5456 #define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5458 #define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5460 #define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5462 #define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5464 #define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5487 #define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5493 #define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5496 #define ALT_SDMMC_RINTSTS_HLE_LSB 12
5498 #define ALT_SDMMC_RINTSTS_HLE_MSB 12
5500 #define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5502 #define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5504 #define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5506 #define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5508 #define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5510 #define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5533 #define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5539 #define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5542 #define ALT_SDMMC_RINTSTS_SBE_LSB 13
5544 #define ALT_SDMMC_RINTSTS_SBE_MSB 13
5546 #define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5548 #define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5550 #define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5552 #define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5554 #define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5556 #define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5579 #define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5585 #define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5588 #define ALT_SDMMC_RINTSTS_ACD_LSB 14
5590 #define ALT_SDMMC_RINTSTS_ACD_MSB 14
5592 #define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5594 #define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5596 #define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5598 #define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5600 #define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5602 #define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5625 #define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5631 #define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5634 #define ALT_SDMMC_RINTSTS_EBE_LSB 15
5636 #define ALT_SDMMC_RINTSTS_EBE_MSB 15
5638 #define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5640 #define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5642 #define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5644 #define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5646 #define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5648 #define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5680 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5686 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5689 #define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5691 #define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 31
5693 #define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 16
5695 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0xffff0000
5697 #define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
5699 #define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5701 #define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
5703 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
5705 #ifndef __ASSEMBLY__
5716 struct ALT_SDMMC_RINTSTS_s
5734 uint32_t sdio_interrupt : 16;
5738 typedef volatile struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
5742 #define ALT_SDMMC_RINTSTS_RESET 0x00000000
5744 #define ALT_SDMMC_RINTSTS_OFST 0x44
5792 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5798 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5801 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5803 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5805 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5807 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5809 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5811 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5813 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5815 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5840 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5846 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5849 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5851 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5853 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5855 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5857 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5859 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5861 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5863 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5885 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5891 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5894 #define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5896 #define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5898 #define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5900 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5902 #define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5904 #define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5906 #define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5908 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5930 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x0
5936 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x1
5939 #define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5941 #define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5943 #define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5945 #define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5947 #define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5949 #define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5951 #define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5953 #define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
6036 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
6042 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
6048 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
6054 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
6060 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
6066 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
6072 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
6078 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
6084 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
6090 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
6096 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
6102 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
6108 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
6114 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
6120 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
6126 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
6129 #define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
6131 #define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
6133 #define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
6135 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
6137 #define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
6139 #define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
6141 #define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
6143 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
6169 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
6175 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
6178 #define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
6180 #define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
6182 #define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
6184 #define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
6186 #define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
6188 #define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
6190 #define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
6192 #define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
6218 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
6224 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
6227 #define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
6229 #define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
6231 #define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
6233 #define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
6235 #define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
6237 #define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
6239 #define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
6241 #define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
6263 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
6269 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
6272 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
6274 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
6276 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
6278 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
6280 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
6282 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
6284 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
6286 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
6297 #define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
6299 #define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
6301 #define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
6303 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
6305 #define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
6307 #define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
6309 #define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
6311 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
6322 #define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
6324 #define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
6326 #define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
6328 #define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
6330 #define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
6332 #define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
6334 #define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
6336 #define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
6349 #define ALT_SDMMC_STAT_DMA_ACK_LSB 30
6351 #define ALT_SDMMC_STAT_DMA_ACK_MSB 30
6353 #define ALT_SDMMC_STAT_DMA_ACK_WIDTH 1
6355 #define ALT_SDMMC_STAT_DMA_ACK_SET_MSK 0x40000000
6357 #define ALT_SDMMC_STAT_DMA_ACK_CLR_MSK 0xbfffffff
6359 #define ALT_SDMMC_STAT_DMA_ACK_RESET 0x0
6361 #define ALT_SDMMC_STAT_DMA_ACK_GET(value) (((value) & 0x40000000) >> 30)
6363 #define ALT_SDMMC_STAT_DMA_ACK_SET(value) (((value) << 30) & 0x40000000)
6376 #define ALT_SDMMC_STAT_DMA_REQ_LSB 31
6378 #define ALT_SDMMC_STAT_DMA_REQ_MSB 31
6380 #define ALT_SDMMC_STAT_DMA_REQ_WIDTH 1
6382 #define ALT_SDMMC_STAT_DMA_REQ_SET_MSK 0x80000000
6384 #define ALT_SDMMC_STAT_DMA_REQ_CLR_MSK 0x7fffffff
6386 #define ALT_SDMMC_STAT_DMA_REQ_RESET 0x0
6388 #define ALT_SDMMC_STAT_DMA_REQ_GET(value) (((value) & 0x80000000) >> 31)
6390 #define ALT_SDMMC_STAT_DMA_REQ_SET(value) (((value) << 31) & 0x80000000)
6392 #ifndef __ASSEMBLY__
6403 struct ALT_SDMMC_STAT_s
6405 const uint32_t fifo_rx_watermark : 1;
6406 const uint32_t fifo_tx_watermark : 1;
6407 const uint32_t fifo_empty : 1;
6408 const uint32_t fifo_full : 1;
6409 const uint32_t command_fsm_states : 4;
6410 const uint32_t data_3_status : 1;
6411 const uint32_t data_busy : 1;
6412 const uint32_t data_state_mc_busy : 1;
6413 const uint32_t response_index : 6;
6414 const uint32_t fifo_count : 13;
6415 const uint32_t dma_ack : 1;
6416 const uint32_t dma_req : 1;
6420 typedef volatile struct ALT_SDMMC_STAT_s ALT_SDMMC_STAT_t;
6424 #define ALT_SDMMC_STAT_RESET 0x00000106
6426 #define ALT_SDMMC_STAT_OFST 0x48
6472 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
6474 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
6476 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
6478 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
6480 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
6482 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
6484 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
6486 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
6525 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
6527 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
6529 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
6531 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
6533 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
6535 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
6537 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
6539 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
6626 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
6632 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
6638 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6644 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6650 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6656 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6662 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6665 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6667 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6669 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6671 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6673 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6675 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6677 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6679 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6681 #ifndef __ASSEMBLY__
6692 struct ALT_SDMMC_FIFOTH_s
6694 uint32_t tx_wmark : 12;
6696 uint32_t rx_wmark : 12;
6697 uint32_t dw_dma_multiple_transaction_size : 3;
6702 typedef volatile struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
6706 #define ALT_SDMMC_FIFOTH_RESET 0x03ff0000
6708 #define ALT_SDMMC_FIFOTH_OFST 0x4c
6744 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6750 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6753 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6755 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6757 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6759 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6761 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6763 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6765 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6767 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6769 #ifndef __ASSEMBLY__
6780 struct ALT_SDMMC_CDETECT_s
6782 const uint32_t card_detect_n : 1;
6787 typedef volatile struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
6791 #define ALT_SDMMC_CDETECT_RESET 0x00000001
6793 #define ALT_SDMMC_CDETECT_OFST 0x50
6830 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6836 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6839 #define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6841 #define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6843 #define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6845 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6847 #define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6849 #define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6851 #define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6853 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6855 #ifndef __ASSEMBLY__
6866 struct ALT_SDMMC_WRTPRT_s
6868 const uint32_t write_protect : 1;
6873 typedef volatile struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
6877 #define ALT_SDMMC_WRTPRT_RESET 0x00000001
6879 #define ALT_SDMMC_WRTPRT_OFST 0x54
6905 #define ALT_SDMMC_GPIO_GPI_LSB 0
6907 #define ALT_SDMMC_GPIO_GPI_MSB 7
6909 #define ALT_SDMMC_GPIO_GPI_WIDTH 8
6911 #define ALT_SDMMC_GPIO_GPI_SET_MSK 0x000000ff
6913 #define ALT_SDMMC_GPIO_GPI_CLR_MSK 0xffffff00
6915 #define ALT_SDMMC_GPIO_GPI_RESET 0x0
6917 #define ALT_SDMMC_GPIO_GPI_GET(value) (((value) & 0x000000ff) >> 0)
6919 #define ALT_SDMMC_GPIO_GPI_SET(value) (((value) << 0) & 0x000000ff)
6931 #define ALT_SDMMC_GPIO_GPO_LSB 8
6933 #define ALT_SDMMC_GPIO_GPO_MSB 23
6935 #define ALT_SDMMC_GPIO_GPO_WIDTH 16
6937 #define ALT_SDMMC_GPIO_GPO_SET_MSK 0x00ffff00
6939 #define ALT_SDMMC_GPIO_GPO_CLR_MSK 0xff0000ff
6941 #define ALT_SDMMC_GPIO_GPO_RESET 0x0
6943 #define ALT_SDMMC_GPIO_GPO_GET(value) (((value) & 0x00ffff00) >> 8)
6945 #define ALT_SDMMC_GPIO_GPO_SET(value) (((value) << 8) & 0x00ffff00)
6947 #ifndef __ASSEMBLY__
6958 struct ALT_SDMMC_GPIO_s
6960 const uint32_t gpi : 8;
6966 typedef volatile struct ALT_SDMMC_GPIO_s ALT_SDMMC_GPIO_t;
6970 #define ALT_SDMMC_GPIO_RESET 0x00000000
6972 #define ALT_SDMMC_GPIO_OFST 0x58
7004 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
7006 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
7008 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
7010 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
7012 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
7014 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
7016 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7018 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7020 #ifndef __ASSEMBLY__
7031 struct ALT_SDMMC_TCBCNT_s
7033 const uint32_t trans_card_byte_count : 32;
7037 typedef volatile struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
7041 #define ALT_SDMMC_TCBCNT_RESET 0x00000000
7043 #define ALT_SDMMC_TCBCNT_OFST 0x5c
7075 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
7077 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
7079 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
7081 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
7083 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
7085 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
7087 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7089 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7091 #ifndef __ASSEMBLY__
7102 struct ALT_SDMMC_TBBCNT_s
7104 const uint32_t trans_fifo_byte_count : 32;
7108 typedef volatile struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
7112 #define ALT_SDMMC_TBBCNT_RESET 0x00000000
7114 #define ALT_SDMMC_TBBCNT_OFST 0x60
7140 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
7142 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
7144 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
7146 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
7148 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
7150 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
7152 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
7154 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
7156 #ifndef __ASSEMBLY__
7167 struct ALT_SDMMC_DEBNCE_s
7169 uint32_t debounce_count : 24;
7174 typedef volatile struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
7178 #define ALT_SDMMC_DEBNCE_RESET 0x00ffffff
7180 #define ALT_SDMMC_DEBNCE_OFST 0x64
7206 #define ALT_SDMMC_USRID_USR_ID_LSB 0
7208 #define ALT_SDMMC_USRID_USR_ID_MSB 31
7210 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
7212 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
7214 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
7216 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
7218 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
7220 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
7222 #ifndef __ASSEMBLY__
7233 struct ALT_SDMMC_USRID_s
7235 uint32_t usr_id : 32;
7239 typedef volatile struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
7243 #define ALT_SDMMC_USRID_RESET 0x07967797
7245 #define ALT_SDMMC_USRID_OFST 0x68
7269 #define ALT_SDMMC_VERID_VER_ID_LSB 0
7271 #define ALT_SDMMC_VERID_VER_ID_MSB 31
7273 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
7275 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
7277 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
7279 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342270a
7281 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
7283 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
7285 #ifndef __ASSEMBLY__
7296 struct ALT_SDMMC_VERID_s
7298 const uint32_t ver_id : 32;
7302 typedef volatile struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
7306 #define ALT_SDMMC_VERID_RESET 0x5342270a
7308 #define ALT_SDMMC_VERID_OFST 0x6c
7354 #define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
7357 #define ALT_SDMMC_HCON_CT_LSB 0
7359 #define ALT_SDMMC_HCON_CT_MSB 0
7361 #define ALT_SDMMC_HCON_CT_WIDTH 1
7363 #define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
7365 #define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
7367 #define ALT_SDMMC_HCON_CT_RESET 0x1
7369 #define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
7371 #define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
7392 #define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
7395 #define ALT_SDMMC_HCON_NC_LSB 1
7397 #define ALT_SDMMC_HCON_NC_MSB 5
7399 #define ALT_SDMMC_HCON_NC_WIDTH 5
7401 #define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
7403 #define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
7405 #define ALT_SDMMC_HCON_NC_RESET 0x0
7407 #define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
7409 #define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
7430 #define ALT_SDMMC_HCON_HBUS_E_APB 0x0
7433 #define ALT_SDMMC_HCON_HBUS_LSB 6
7435 #define ALT_SDMMC_HCON_HBUS_MSB 6
7437 #define ALT_SDMMC_HCON_HBUS_WIDTH 1
7439 #define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
7441 #define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
7443 #define ALT_SDMMC_HCON_HBUS_RESET 0x0
7445 #define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
7447 #define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
7468 #define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
7471 #define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
7473 #define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
7475 #define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
7477 #define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
7479 #define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
7481 #define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
7483 #define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
7485 #define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
7506 #define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
7509 #define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
7511 #define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
7513 #define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
7515 #define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
7517 #define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
7519 #define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
7521 #define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
7523 #define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
7545 #define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
7548 #define ALT_SDMMC_HCON_DMAINTF_LSB 16
7550 #define ALT_SDMMC_HCON_DMAINTF_MSB 17
7552 #define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
7554 #define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
7556 #define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
7558 #define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
7560 #define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
7562 #define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
7584 #define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
7587 #define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
7589 #define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
7591 #define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
7593 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
7595 #define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
7597 #define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
7599 #define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
7601 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
7622 #define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
7625 #define ALT_SDMMC_HCON_RIOS_LSB 21
7627 #define ALT_SDMMC_HCON_RIOS_MSB 21
7629 #define ALT_SDMMC_HCON_RIOS_WIDTH 1
7631 #define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
7633 #define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
7635 #define ALT_SDMMC_HCON_RIOS_RESET 0x0
7637 #define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
7639 #define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
7660 #define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
7663 #define ALT_SDMMC_HCON_IHR_LSB 22
7665 #define ALT_SDMMC_HCON_IHR_MSB 22
7667 #define ALT_SDMMC_HCON_IHR_WIDTH 1
7669 #define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
7671 #define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
7673 #define ALT_SDMMC_HCON_IHR_RESET 0x1
7675 #define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
7677 #define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
7698 #define ALT_SDMMC_HCON_SCFP_E_SET 0x1
7701 #define ALT_SDMMC_HCON_SCFP_LSB 23
7703 #define ALT_SDMMC_HCON_SCFP_MSB 23
7705 #define ALT_SDMMC_HCON_SCFP_WIDTH 1
7707 #define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
7709 #define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
7711 #define ALT_SDMMC_HCON_SCFP_RESET 0x1
7713 #define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
7715 #define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
7736 #define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
7739 #define ALT_SDMMC_HCON_NCD_LSB 24
7741 #define ALT_SDMMC_HCON_NCD_MSB 25
7743 #define ALT_SDMMC_HCON_NCD_WIDTH 2
7745 #define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
7747 #define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
7749 #define ALT_SDMMC_HCON_NCD_RESET 0x0
7751 #define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
7753 #define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
7774 #define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
7777 #define ALT_SDMMC_HCON_ARO_LSB 26
7779 #define ALT_SDMMC_HCON_ARO_MSB 26
7781 #define ALT_SDMMC_HCON_ARO_WIDTH 1
7783 #define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7785 #define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7787 #define ALT_SDMMC_HCON_ARO_RESET 0x0
7789 #define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7791 #define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7806 #define ALT_SDMMC_HCON_AC_LSB 27
7808 #define ALT_SDMMC_HCON_AC_MSB 27
7810 #define ALT_SDMMC_HCON_AC_WIDTH 1
7812 #define ALT_SDMMC_HCON_AC_SET_MSK 0x08000000
7814 #define ALT_SDMMC_HCON_AC_CLR_MSK 0xf7ffffff
7816 #define ALT_SDMMC_HCON_AC_RESET 0x0
7818 #define ALT_SDMMC_HCON_AC_GET(value) (((value) & 0x08000000) >> 27)
7820 #define ALT_SDMMC_HCON_AC_SET(value) (((value) << 27) & 0x08000000)
7822 #ifndef __ASSEMBLY__
7833 struct ALT_SDMMC_HCON_s
7835 const uint32_t ct : 1;
7836 const uint32_t nc : 5;
7837 const uint32_t hbus : 1;
7838 const uint32_t hdatawidth : 3;
7839 const uint32_t haddrwidth : 6;
7840 const uint32_t dmaintf : 2;
7841 const uint32_t dmadatawidth : 3;
7842 const uint32_t rios : 1;
7843 const uint32_t ihr : 1;
7844 const uint32_t scfp : 1;
7845 const uint32_t ncd : 2;
7846 const uint32_t aro : 1;
7847 const uint32_t ac : 1;
7852 typedef volatile struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
7856 #define ALT_SDMMC_HCON_RESET 0x00c43081
7858 #define ALT_SDMMC_HCON_OFST 0x70
7909 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7915 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7918 #define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7920 #define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 15
7922 #define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 16
7924 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x0000ffff
7926 #define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xffff0000
7928 #define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7930 #define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
7932 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
7962 #define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7968 #define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7971 #define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7973 #define ALT_SDMMC_UHS_REG_DDR_REG_MSB 31
7975 #define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 16
7977 #define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0xffff0000
7979 #define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0x0000ffff
7981 #define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7983 #define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0xffff0000) >> 16)
7985 #define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0xffff0000)
7987 #ifndef __ASSEMBLY__
7998 struct ALT_SDMMC_UHS_REG_s
8000 uint32_t volt_reg : 16;
8001 uint32_t ddr_reg : 16;
8005 typedef volatile struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
8009 #define ALT_SDMMC_UHS_REG_RESET 0x00000000
8011 #define ALT_SDMMC_UHS_REG_OFST 0x74
8059 #define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
8065 #define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
8068 #define ALT_SDMMC_RST_N_CARD_RST_LSB 0
8070 #define ALT_SDMMC_RST_N_CARD_RST_MSB 0
8072 #define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
8074 #define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
8076 #define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
8078 #define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
8080 #define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
8082 #define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
8084 #ifndef __ASSEMBLY__
8095 struct ALT_SDMMC_RST_N_s
8097 uint32_t card_reset : 1;
8102 typedef volatile struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
8106 #define ALT_SDMMC_RST_N_RESET 0x00000001
8108 #define ALT_SDMMC_RST_N_OFST 0x78
8149 #define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
8155 #define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
8158 #define ALT_SDMMC_BMOD_SWR_LSB 0
8160 #define ALT_SDMMC_BMOD_SWR_MSB 0
8162 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
8164 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
8166 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
8168 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
8170 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
8172 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
8200 #define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
8206 #define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
8209 #define ALT_SDMMC_BMOD_FB_LSB 1
8211 #define ALT_SDMMC_BMOD_FB_MSB 1
8213 #define ALT_SDMMC_BMOD_FB_WIDTH 1
8215 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
8217 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
8219 #define ALT_SDMMC_BMOD_FB_RESET 0x0
8221 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
8223 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
8238 #define ALT_SDMMC_BMOD_DSL_LSB 2
8240 #define ALT_SDMMC_BMOD_DSL_MSB 6
8242 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
8244 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
8246 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
8248 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
8250 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
8252 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
8276 #define ALT_SDMMC_BMOD_DE_E_DISD 0x0
8282 #define ALT_SDMMC_BMOD_DE_E_END 0x1
8285 #define ALT_SDMMC_BMOD_DE_LSB 7
8287 #define ALT_SDMMC_BMOD_DE_MSB 7
8289 #define ALT_SDMMC_BMOD_DE_WIDTH 1
8291 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
8293 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
8295 #define ALT_SDMMC_BMOD_DE_RESET 0x0
8297 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
8299 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
8355 #define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
8361 #define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
8367 #define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
8373 #define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
8379 #define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
8385 #define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
8391 #define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
8397 #define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
8400 #define ALT_SDMMC_BMOD_PBL_LSB 8
8402 #define ALT_SDMMC_BMOD_PBL_MSB 10
8404 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
8406 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
8408 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
8410 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
8412 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
8414 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
8416 #ifndef __ASSEMBLY__
8427 struct ALT_SDMMC_BMOD_s
8433 const uint32_t pbl : 3;
8438 typedef volatile struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
8442 #define ALT_SDMMC_BMOD_RESET 0x00000000
8444 #define ALT_SDMMC_BMOD_OFST 0x80
8473 #define ALT_SDMMC_PLDMND_PD_LSB 0
8475 #define ALT_SDMMC_PLDMND_PD_MSB 31
8477 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
8479 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
8481 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
8483 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
8485 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
8487 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
8489 #ifndef __ASSEMBLY__
8500 struct ALT_SDMMC_PLDMND_s
8506 typedef volatile struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
8510 #define ALT_SDMMC_PLDMND_RESET 0x00000000
8512 #define ALT_SDMMC_PLDMND_OFST 0x84
8538 #define ALT_SDMMC_DBADDR_SDL_LSB 0
8540 #define ALT_SDMMC_DBADDR_SDL_MSB 31
8542 #define ALT_SDMMC_DBADDR_SDL_WIDTH 32
8544 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xffffffff
8546 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000000
8548 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
8550 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xffffffff) >> 0)
8552 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 0) & 0xffffffff)
8554 #ifndef __ASSEMBLY__
8565 struct ALT_SDMMC_DBADDR_s
8571 typedef volatile struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
8575 #define ALT_SDMMC_DBADDR_RESET 0x00000000
8577 #define ALT_SDMMC_DBADDR_OFST 0x88
8623 #define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
8629 #define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
8632 #define ALT_SDMMC_IDSTS_TI_LSB 0
8634 #define ALT_SDMMC_IDSTS_TI_MSB 0
8636 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
8638 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
8640 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
8642 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
8644 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
8646 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
8669 #define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
8675 #define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
8678 #define ALT_SDMMC_IDSTS_RI_LSB 1
8680 #define ALT_SDMMC_IDSTS_RI_MSB 1
8682 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
8684 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
8686 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
8688 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
8690 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
8692 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
8716 #define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
8722 #define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
8725 #define ALT_SDMMC_IDSTS_FBE_LSB 2
8727 #define ALT_SDMMC_IDSTS_FBE_MSB 2
8729 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
8731 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
8733 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
8735 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
8737 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
8739 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
8764 #define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
8770 #define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
8773 #define ALT_SDMMC_IDSTS_DU_LSB 4
8775 #define ALT_SDMMC_IDSTS_DU_MSB 4
8777 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
8779 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
8781 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
8783 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
8785 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
8787 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
8834 #define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
8840 #define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
8843 #define ALT_SDMMC_IDSTS_CES_LSB 5
8845 #define ALT_SDMMC_IDSTS_CES_MSB 5
8847 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
8849 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
8851 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
8853 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
8855 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
8857 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
8890 #define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
8896 #define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
8899 #define ALT_SDMMC_IDSTS_NIS_LSB 8
8901 #define ALT_SDMMC_IDSTS_NIS_MSB 8
8903 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8905 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8907 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8909 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8911 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8913 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8946 #define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8952 #define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8955 #define ALT_SDMMC_IDSTS_AIS_LSB 9
8957 #define ALT_SDMMC_IDSTS_AIS_MSB 9
8959 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8961 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8963 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8965 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8967 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8969 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
9003 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
9009 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
9012 #define ALT_SDMMC_IDSTS_EB_LSB 10
9014 #define ALT_SDMMC_IDSTS_EB_MSB 12
9016 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
9018 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
9020 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
9022 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
9024 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
9026 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
9075 #define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
9081 #define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
9087 #define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
9093 #define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
9099 #define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
9105 #define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
9111 #define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
9117 #define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
9123 #define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
9126 #define ALT_SDMMC_IDSTS_FSM_LSB 13
9128 #define ALT_SDMMC_IDSTS_FSM_MSB 16
9130 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
9132 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
9134 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
9136 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
9138 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
9140 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
9142 #ifndef __ASSEMBLY__
9153 struct ALT_SDMMC_IDSTS_s
9164 const uint32_t eb : 3;
9165 const uint32_t fsm : 4;
9170 typedef volatile struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
9174 #define ALT_SDMMC_IDSTS_RESET 0x00000000
9176 #define ALT_SDMMC_IDSTS_OFST 0x8c
9220 #define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
9226 #define ALT_SDMMC_IDINTEN_TI_E_END 0x1
9229 #define ALT_SDMMC_IDINTEN_TI_LSB 0
9231 #define ALT_SDMMC_IDINTEN_TI_MSB 0
9233 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
9235 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
9237 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
9239 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
9241 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
9243 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
9266 #define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
9272 #define ALT_SDMMC_IDINTEN_RI_E_END 0x1
9275 #define ALT_SDMMC_IDINTEN_RI_LSB 1
9277 #define ALT_SDMMC_IDINTEN_RI_MSB 1
9279 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
9281 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
9283 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
9285 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
9287 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
9289 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
9313 #define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
9319 #define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
9322 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
9324 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
9326 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
9328 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
9330 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
9332 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
9334 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
9336 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
9359 #define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
9365 #define ALT_SDMMC_IDINTEN_DU_E_END 0x1
9368 #define ALT_SDMMC_IDINTEN_DU_LSB 4
9370 #define ALT_SDMMC_IDINTEN_DU_MSB 4
9372 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
9374 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
9376 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
9378 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
9380 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
9382 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
9405 #define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
9411 #define ALT_SDMMC_IDINTEN_CES_E_END 0x1
9414 #define ALT_SDMMC_IDINTEN_CES_LSB 5
9416 #define ALT_SDMMC_IDINTEN_CES_MSB 5
9418 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
9420 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
9422 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
9424 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
9426 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
9428 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
9455 #define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
9461 #define ALT_SDMMC_IDINTEN_NI_E_END 0x1
9464 #define ALT_SDMMC_IDINTEN_NI_LSB 8
9466 #define ALT_SDMMC_IDINTEN_NI_MSB 8
9468 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
9470 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
9472 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
9474 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
9476 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
9478 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
9505 #define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
9511 #define ALT_SDMMC_IDINTEN_AI_E_END 0x1
9514 #define ALT_SDMMC_IDINTEN_AI_LSB 9
9516 #define ALT_SDMMC_IDINTEN_AI_MSB 9
9518 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
9520 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
9522 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
9524 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
9526 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
9528 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
9530 #ifndef __ASSEMBLY__
9541 struct ALT_SDMMC_IDINTEN_s
9556 typedef volatile struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
9560 #define ALT_SDMMC_IDINTEN_RESET 0x00000000
9562 #define ALT_SDMMC_IDINTEN_OFST 0x90
9587 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
9589 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
9591 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
9593 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
9595 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
9597 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
9599 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
9601 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
9603 #ifndef __ASSEMBLY__
9614 struct ALT_SDMMC_DSCADDR_s
9616 const uint32_t hda : 32;
9620 typedef volatile struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
9624 #define ALT_SDMMC_DSCADDR_RESET 0x00000000
9626 #define ALT_SDMMC_DSCADDR_OFST 0x94
9651 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
9653 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
9655 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
9657 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
9659 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
9661 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
9663 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
9665 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
9667 #ifndef __ASSEMBLY__
9678 struct ALT_SDMMC_BUFADDR_s
9680 const uint32_t hba : 32;
9684 typedef volatile struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
9688 #define ALT_SDMMC_BUFADDR_RESET 0x00000000
9690 #define ALT_SDMMC_BUFADDR_OFST 0x98
9736 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
9742 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
9745 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
9747 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
9749 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
9751 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
9753 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
9755 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
9757 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
9759 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
9781 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_LSB 1
9783 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_MSB 1
9785 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_WIDTH 1
9787 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET_MSK 0x00000002
9789 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_CLR_MSK 0xfffffffd
9791 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_RESET 0x0
9793 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_GET(value) (((value) & 0x00000002) >> 1)
9795 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET(value) (((value) << 1) & 0x00000002)
9818 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
9820 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 28
9822 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 13
9824 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x1fff0000
9826 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xe000ffff
9828 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
9830 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x1fff0000) >> 16)
9832 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x1fff0000)
9834 #ifndef __ASSEMBLY__
9845 struct ALT_SDMMC_CARDTHRCTL_s
9847 uint32_t cardrdthren : 1;
9848 uint32_t busy_clr_int_en : 1;
9850 uint32_t cardrdthreshold : 13;
9855 typedef volatile struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
9859 #define ALT_SDMMC_CARDTHRCTL_RESET 0x00000000
9861 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
9902 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
9908 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
9911 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
9913 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
9915 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
9917 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
9919 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
9921 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
9923 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
9925 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
9927 #ifndef __ASSEMBLY__
9938 struct ALT_SDMMC_BACK_END_POWER_R_s
9940 uint32_t back_end_power : 16;
9945 typedef volatile struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
9949 #define ALT_SDMMC_BACK_END_POWER_R_RESET 0x00000000
9951 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
9988 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_LSB 0
9990 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_MSB 15
9992 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_WIDTH 16
9994 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET_MSK 0x0000ffff
9996 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_CLR_MSK 0xffff0000
9998 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_RESET 0x0
10000 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
10002 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
10015 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_LSB 16
10017 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_MSB 22
10019 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_WIDTH 7
10021 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET_MSK 0x007f0000
10023 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_CLR_MSK 0xff80ffff
10025 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_RESET 0x0
10027 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_GET(value) (((value) & 0x007f0000) >> 16)
10029 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET(value) (((value) << 16) & 0x007f0000)
10042 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_LSB 23
10044 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_MSB 29
10046 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_WIDTH 7
10048 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET_MSK 0x3f800000
10050 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_CLR_MSK 0xc07fffff
10052 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_RESET 0x0
10054 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_GET(value) (((value) & 0x3f800000) >> 23)
10056 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET(value) (((value) << 23) & 0x3f800000)
10068 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_LSB 30
10070 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_MSB 31
10072 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_WIDTH 2
10074 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET_MSK 0xc0000000
10076 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_CLR_MSK 0x3fffffff
10078 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_RESET 0x0
10080 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_GET(value) (((value) & 0xc0000000) >> 30)
10082 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET(value) (((value) << 30) & 0xc0000000)
10084 #ifndef __ASSEMBLY__
10095 struct ALT_SDMMC_UHS_REG_EXT_s
10097 uint32_t mmc_volt_reg : 16;
10098 uint32_t clk_smpl_phase_ctrl : 7;
10099 uint32_t clk_drv_phase_ctrl : 7;
10100 uint32_t ext_clk_mux_ctrl : 2;
10104 typedef volatile struct ALT_SDMMC_UHS_REG_EXT_s ALT_SDMMC_UHS_REG_EXT_t;
10108 #define ALT_SDMMC_UHS_REG_EXT_RESET 0x00000000
10110 #define ALT_SDMMC_UHS_REG_EXT_OFST 0x108
10145 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_LSB 0
10147 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_MSB 0
10149 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_WIDTH 1
10151 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET_MSK 0x00000001
10153 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_CLR_MSK 0xfffffffe
10155 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_RESET 0x0
10157 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_GET(value) (((value) & 0x00000001) >> 0)
10159 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET(value) (((value) << 0) & 0x00000001)
10161 #ifndef __ASSEMBLY__
10172 struct ALT_SDMMC_EMMC_DDR_REG_s
10174 uint32_t half_start_bit : 1;
10179 typedef volatile struct ALT_SDMMC_EMMC_DDR_REG_s ALT_SDMMC_EMMC_DDR_REG_t;
10183 #define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000
10185 #define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c
10220 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_LSB 0
10222 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_MSB 1
10224 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_WIDTH 2
10226 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET_MSK 0x00000003
10228 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_CLR_MSK 0xfffffffc
10230 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_RESET 0x0
10232 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_GET(value) (((value) & 0x00000003) >> 0)
10234 #define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET(value) (((value) << 0) & 0x00000003)
10236 #ifndef __ASSEMBLY__
10247 struct ALT_SDMMC_EN_SHIFT_s
10249 uint32_t enable_shift_card : 2;
10254 typedef volatile struct ALT_SDMMC_EN_SHIFT_s ALT_SDMMC_EN_SHIFT_t;
10258 #define ALT_SDMMC_EN_SHIFT_RESET 0x00000000
10260 #define ALT_SDMMC_EN_SHIFT_OFST 0x110
10285 #define ALT_SDMMC_DATA_VALUE_LSB 0
10287 #define ALT_SDMMC_DATA_VALUE_MSB 31
10289 #define ALT_SDMMC_DATA_VALUE_WIDTH 32
10291 #define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
10293 #define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
10295 #define ALT_SDMMC_DATA_VALUE_RESET 0x0
10297 #define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
10299 #define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
10301 #ifndef __ASSEMBLY__
10312 struct ALT_SDMMC_DATA_s
10314 uint32_t value : 32;
10318 typedef volatile struct ALT_SDMMC_DATA_s ALT_SDMMC_DATA_t;
10322 #define ALT_SDMMC_DATA_RESET 0x00000000
10324 #define ALT_SDMMC_DATA_OFST 0x200
10326 #ifndef __ASSEMBLY__
10339 ALT_SDMMC_CTL_t ctrl;
10340 ALT_SDMMC_PWREN_t pwren;
10341 ALT_SDMMC_CLKDIV_t clkdiv;
10342 ALT_SDMMC_CLKSRC_t clksrc;
10343 ALT_SDMMC_CLKENA_t clkena;
10344 ALT_SDMMC_TMOUT_t tmout;
10345 ALT_SDMMC_CTYPE_t ctype;
10346 ALT_SDMMC_BLKSIZ_t blksiz;
10347 ALT_SDMMC_BYTCNT_t bytcnt;
10348 ALT_SDMMC_INTMSK_t intmask;
10349 ALT_SDMMC_CMDARG_t cmdarg;
10350 ALT_SDMMC_CMD_t cmd;
10351 ALT_SDMMC_RESP0_t resp0;
10352 ALT_SDMMC_RESP1_t resp1;
10353 ALT_SDMMC_RESP2_t resp2;
10354 ALT_SDMMC_RESP3_t resp3;
10355 ALT_SDMMC_MINTSTS_t mintsts;
10356 ALT_SDMMC_RINTSTS_t rintsts;
10357 ALT_SDMMC_STAT_t status;
10358 ALT_SDMMC_FIFOTH_t fifoth;
10359 ALT_SDMMC_CDETECT_t cdetect;
10360 ALT_SDMMC_WRTPRT_t wrtprt;
10361 ALT_SDMMC_GPIO_t gpio;
10362 ALT_SDMMC_TCBCNT_t tcbcnt;
10363 ALT_SDMMC_TBBCNT_t tbbcnt;
10364 ALT_SDMMC_DEBNCE_t debnce;
10365 ALT_SDMMC_USRID_t usrid;
10366 ALT_SDMMC_VERID_t verid;
10367 ALT_SDMMC_HCON_t hcon;
10368 ALT_SDMMC_UHS_REG_t uhs_reg;
10369 ALT_SDMMC_RST_N_t rst_n;
10370 volatile uint32_t _pad_0x7c_0x7f;
10371 ALT_SDMMC_BMOD_t bmod;
10372 ALT_SDMMC_PLDMND_t pldmnd;
10373 ALT_SDMMC_DBADDR_t dbaddr;
10374 ALT_SDMMC_IDSTS_t idsts;
10375 ALT_SDMMC_IDINTEN_t idinten;
10376 ALT_SDMMC_DSCADDR_t dscaddr;
10377 ALT_SDMMC_BUFADDR_t bufaddr;
10378 volatile uint32_t _pad_0x9c_0xff[25];
10379 ALT_SDMMC_CARDTHRCTL_t cardthrctl;
10380 ALT_SDMMC_BACK_END_POWER_R_t back_end_power_r;
10381 ALT_SDMMC_UHS_REG_EXT_t uhs_reg_ext;
10382 ALT_SDMMC_EMMC_DDR_REG_t emmc_ddr_reg;
10383 ALT_SDMMC_EN_SHIFT_t enable_shift;
10384 volatile uint32_t _pad_0x114_0x1ff[59];
10385 ALT_SDMMC_DATA_t data;
10386 volatile uint32_t _pad_0x204_0x400[127];
10390 typedef volatile struct ALT_SDMMC_s ALT_SDMMC_t;
10392 struct ALT_SDMMC_raw_s
10394 volatile uint32_t ctrl;
10395 volatile uint32_t pwren;
10396 volatile uint32_t clkdiv;
10397 volatile uint32_t clksrc;
10398 volatile uint32_t clkena;
10399 volatile uint32_t tmout;
10400 volatile uint32_t ctype;
10401 volatile uint32_t blksiz;
10402 volatile uint32_t bytcnt;
10403 volatile uint32_t intmask;
10404 volatile uint32_t cmdarg;
10405 volatile uint32_t cmd;
10406 volatile uint32_t resp0;
10407 volatile uint32_t resp1;
10408 volatile uint32_t resp2;
10409 volatile uint32_t resp3;
10410 volatile uint32_t mintsts;
10411 volatile uint32_t rintsts;
10412 volatile uint32_t status;
10413 volatile uint32_t fifoth;
10414 volatile uint32_t cdetect;
10415 volatile uint32_t wrtprt;
10416 volatile uint32_t gpio;
10417 volatile uint32_t tcbcnt;
10418 volatile uint32_t tbbcnt;
10419 volatile uint32_t debnce;
10420 volatile uint32_t usrid;
10421 volatile uint32_t verid;
10422 volatile uint32_t hcon;
10423 volatile uint32_t uhs_reg;
10424 volatile uint32_t rst_n;
10425 uint32_t _pad_0x7c_0x7f;
10426 volatile uint32_t bmod;
10427 volatile uint32_t pldmnd;
10428 volatile uint32_t dbaddr;
10429 volatile uint32_t idsts;
10430 volatile uint32_t idinten;
10431 volatile uint32_t dscaddr;
10432 volatile uint32_t bufaddr;
10433 uint32_t _pad_0x9c_0xff[25];
10434 volatile uint32_t cardthrctl;
10435 volatile uint32_t back_end_power_r;
10436 volatile uint32_t uhs_reg_ext;
10437 volatile uint32_t emmc_ddr_reg;
10438 volatile uint32_t enable_shift;
10439 uint32_t _pad_0x114_0x1ff[59];
10440 volatile uint32_t data;
10441 uint32_t _pad_0x204_0x400[127];
10445 typedef volatile struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;