Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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FPGA Manager

Description

This module defines the FPGA Manager API for accessing, configuring, and controlling the FPGA fabric and the FPGA/HPS interface. This API is specific to Arria 10 SoC FPGA devices.

Members

 FPGA Full Configuration
 

Macros

#define ALT_FPGA_ENABLE_DMA_SUPPORT   (0)
 

Typedefs

typedef enum ALT_FPGA_CFG_MODE_e ALT_FPGA_CFG_MODE_t
 
typedef enum ALT_FPGA_STATUS_e ALT_FPGA_STATUS_t
 
typedef int32_t(* alt_fpga_istream_t )(void *buf, size_t len, void *user_data)
 

ENUMS

enum  ALT_FPGA_CFG_MODE_e {
  ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC, ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC, ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_DC, ALT_FPGA_CFG_MODE_PP16_FAST_AES_DC,
  ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC, ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC, ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_DC, ALT_FPGA_CFG_MODE_PP32_FAST_AES_DC,
  ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC = 0x0, ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC = 0x1, ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC = 0x2, ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC = 0x4,
  ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC = 0x5, ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC = 0x6, ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC = 0x8, ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC = 0x9,
  ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC = 0xa, ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC = 0xc, ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC = 0xd, ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC = 0xe,
  ALT_FPGA_CFG_MODE_UNKNOWN = 0x20
}
 
enum  ALT_FPGA_STATUS_e {
  ALT_FPGA_STATUS_F2S_CRC_ERROR = 1 << 0, ALT_FPGA_STATUS_F2S_EARLY_USERMODE = 1 << 1, ALT_FPGA_STATUS_F2S_USERMODE = 1 << 2, ALT_FPGA_STATUS_F2S_INITDONE_OE = 1 << 3,
  ALT_FPGA_STATUS_F2S_NSTATUS_PIN = 1 << 4, ALT_FPGA_STATUS_F2S_NSTATUS_OE = 1 << 5, ALT_FPGA_STATUS_F2S_CONDONE_PIN = 1 << 6, ALT_FPGA_STATUS_F2S_CONDONE_OE = 1 << 7,
  ALT_FPGA_STATUS_F2S_CVP_CONF_DONE = 1 << 8, ALT_FPGA_STATUS_F2S_PR_READY = 1 << 9, ALT_FPGA_STATUS_F2S_PR_DONE = 1 << 10, ALT_FPGA_STATUS_F2S_PR_ERROR = 1 << 11,
  ALT_FPGA_STATUS_F2S_NCONFIG_PIN = 1 << 12, ALT_FPGA_STATUS_F2S_NCEO_OE = 1 << 13, ALT_FPGA_STATUS_F2S_MSEL0 = 1 << 16, ALT_FPGA_STATUS_F2S_MSEL1 = 1 << 17,
  ALT_FPGA_STATUS_F2S_MSEL2 = 1 << 18, ALT_FPGA_STATUS_IMGCFG_FIFOEMPTY = 1 << 24, ALT_FPGA_STATUS_IMGCFG_FIFOFULL = 1 << 25, ALT_FPGA_STATUS_JTAGM = 1 << 28,
  ALT_FPGA_STATUS_EMR = 1 << 29
}
 

Functions

ALT_STATUS_CODE alt_fpga_init (void)
 
ALT_STATUS_CODE alt_fpga_uninit (void)
 
ALT_STATUS_CODE alt_fpga_control_enable (ALT_FPGA_CFG_MODE_t mode)
 
ALT_STATUS_CODE alt_fpga_control_disable (void)
 
bool alt_fpga_control_is_enabled (void)
 
ALT_STATUS_CODE alt_fpga_reset_assert (void)
 
ALT_STATUS_CODE alt_fpga_reset_deassert (void)
 
uint32_t alt_fpga_status_get (void)
 

Macro Definitions

#define ALT_FPGA_ENABLE_DMA_SUPPORT   (0)

This preprocessor definition determines if DMA support for FPGA programming is enabled or not. Enabling DMA support enables the following API:

  • alt_fpga_configure_dma()
  • alt_fpga_configure_list_dma()
  • alt_fpga_istream_configure_dma()

Please note that DMA support for Arria 10 SoC is not yet mature and may not be functional or tested.

To enable DMA support, define ALT_FPGA_ENABLE_DMA_SUPPORT=1 in the Makefile.

Typedef Documentation

This type definition enumerates the available modes for configuring the FPGA.

This type definition enumerates the status conditions for the FPGA Control Block (CB).

typedef int32_t(* alt_fpga_istream_t)(void *buf, size_t len, void *user_data)

Type definition for the callback function prototype used by the FPGA Manager to read configuration bitstream data from a user defined input source stream.

The purpose of this callback function declaration is to provide a prototype for a user defined method of sequentially reading FPGA configuration bitstream data from an arbitrary input source. Example input sources include a file resident on a file system, a network stream socket, or a fixed address block in flash memory. The only requirement on the input source is that it is capable of supplying consecutive blocks of data of the requested size from the FPGA configuration bitstream as demanded by the FPGA Manager.

During FPGA configuration, the FPGA Manager periodically calls the user defined callback function to fetch the next buf_len consecutive configuration data bytes from the user defined input stream. The callback function fills the FPGA Manager supplied buffer buf with up to the next buf_len bytes of configuration bitsteam data as read from the input source stream. The callback function returns the number of configuration bytes read into buf or 0 upon reaching the end of the configuration bitstream data.

If an error occurs on the configuration bitstream input source, then the callback function should return an error code value less than 0.

Parameters
bufA pointer to a buffer to fill with FPGA configuration bitstream data bytes.
lenThe length of the input buffer buf in bytes. The number of FPGA configuration bitstream data bytes copied into buf should not exceed buf_len.
user_dataA 32-bit data word for passing user defined data. The content of this parameter is user defined. The FPGA Manager merely forwards the user_data value when it invokes the callback.
Return values
>0The number of bytes returned in buf.
=0The end of the input stream has been reached.
<0An error occurred on the input stream.

Enumeration Type Documentation

This type definition enumerates the available modes for configuring the FPGA.

Enumerator:
ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC 

16-bit Passive Parallel with Fast power on reset delay; No Design Security; No Data Compression.

ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC 

16-bit Passive Parallel with Fast power on reset delay; With Design Security; No Data Compression.

ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_DC 

16-bit Passive Parallel with Fast power on reset delay; No design security; With Data Compression.

ALT_FPGA_CFG_MODE_PP16_FAST_AES_DC 

16-bit Passive Parallel with Fast power on reset delay; With design security; With Data Compression.

ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC 

32-bit Passive Parallel with Fast power on reset delay; No Design Security; No Data Compression.

ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC 

32-bit Passive Parallel with Fast power on reset delay; With design security; No Data Comression.

ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_DC 

32-bit Passive Parallel with Fast power on reset delay; No design security; With Data Compression. This is the default configuration.

ALT_FPGA_CFG_MODE_PP32_FAST_AES_DC 

32-bit Passive Parallel with Fast power on reset delay; With design security; With Data Compression.

ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC 

16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC 

16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC 

16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC 

16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC 

16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC 

16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC 

32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC 

32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC 

32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC 

32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC 

32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC 

32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_UNKNOWN 

Unknown FPGA Configuration Mode.

This type definition enumerates the status conditions for the FPGA Control Block (CB).

Enumerator:
ALT_FPGA_STATUS_F2S_CRC_ERROR 

CRC Error detected while in usermode.

ALT_FPGA_STATUS_F2S_EARLY_USERMODE 

Early usermode signal from CSS. This can be used by software to determine status when HPS is configured the shared IOs via sending the POF to the CSS.

ALT_FPGA_STATUS_F2S_USERMODE 

Usermode status. Asserted only when the FPGA has finally entered usermode.

ALT_FPGA_STATUS_F2S_INITDONE_OE 

Driven enable of initdone signal.

ALT_FPGA_STATUS_F2S_NSTATUS_PIN 

Sampled pin value of nstatus signal. This can be overridden by an external device.

ALT_FPGA_STATUS_F2S_NSTATUS_OE 

Driven enable of nstatus signal.

ALT_FPGA_STATUS_F2S_CONDONE_PIN 

Sampled pin value of condone signal. This can be overridden by an external devices.

ALT_FPGA_STATUS_F2S_CONDONE_OE 

Driven enable of condone signal from CSS.

ALT_FPGA_STATUS_F2S_CVP_CONF_DONE 

Configuration via PCIe (CVP) done indicator.

ALT_FPGA_STATUS_F2S_PR_READY 

Partial Reconfiguration (PR) ready.

ALT_FPGA_STATUS_F2S_PR_DONE 

Partial Reconfiguration (PR) done.

ALT_FPGA_STATUS_F2S_PR_ERROR 

Partial Reconfiguration (PR) error.

ALT_FPGA_STATUS_F2S_NCONFIG_PIN 

Sampled pin value of nconfig signal.

ALT_FPGA_STATUS_F2S_NCEO_OE 

Chip select output driven from CSS block.

ALT_FPGA_STATUS_F2S_MSEL0 

Sampled pin value of MSEL[0].

ALT_FPGA_STATUS_F2S_MSEL1 

Sampled pin value of MSEL[1].

ALT_FPGA_STATUS_F2S_MSEL2 

Sampled pin value of MSEL[2].

ALT_FPGA_STATUS_IMGCFG_FIFOEMPTY 

FIFO Empty status of the FPGA image configuration FIFO.

ALT_FPGA_STATUS_IMGCFG_FIFOFULL 

FIFO Full status of the FPGA image configuration FIFO.

ALT_FPGA_STATUS_JTAGM 

JTAG Master Session Status.

ALT_FPGA_STATUS_EMR 

EMR valid bit.

Function Documentation

ALT_STATUS_CODE alt_fpga_init ( void  )

Initializes the FPGA manager. This should be the first API called when using the FPGA manager API.

Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_fpga_uninit ( void  )

Uninitializes the FPGA manager

Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_fpga_control_enable ( ALT_FPGA_CFG_MODE_t  mode)

Instructs the CPU core to acquire control of the FPGA control block. Control is required before asserting reset or FPGA configuration is possible.

Parameters
modeFPGA programming mode for the subsequent images.
Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORError acquiring control of the FPGA control block. This is likely due to another device on the system controlling the FPGA control block or a repeat call to this API without first being released.
ALT_STATUS_CODE alt_fpga_control_disable ( void  )

Instructs the CPU core to release control of the FPGA control block. This API should be called after all FPGA related operations are completed. This will allow another device on the system to configure the FPGA.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORFailure status.
bool alt_fpga_control_is_enabled ( void  )

Returns true if the HPS currently has control of the FPGA control block and false otherwise.

Return values
trueHPS has control of the FPGA control block.
falseHPS does not have control of the FPGA control block.
ALT_STATUS_CODE alt_fpga_reset_assert ( void  )

Assert and hold the FPGA in reset.

This function asserts and holds the FPGA in reset. Any FPGA configuration is cleared. The FPGA must be reconfigured to resume operation.

The FPGA is reset by the assertion of the nCONFIG signal. The signal remains asserted until alt_fgpa_reset_deassert() is called.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_FPGA_PWR_OFFFPGA is not powered on.
ALT_E_FPGA_NO_SOC_CTRLSoC software is not in control of the FPGA. Use alt_fpga_control_enable() to gain control.
ALT_STATUS_CODE alt_fpga_reset_deassert ( void  )

Deassert and release the FPGA from reset.

This function deasserts the FPGA from reset. The FPGA must be reconfigured to resume operation.

The FPGA is reset by the deassertion of the nCONFIG signal.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_FPGA_PWR_OFFFPGA is not powered on.
ALT_E_FPGA_NO_SOC_CTRLSoC software is not in control of the FPGA. Use alt_fpga_control_enable() to gain control.
uint32_t alt_fpga_status_get ( void  )

Gets the current status conditions that are active.

Return values
Maskof logically OR'ed ALT_FPGA_STATUS_t values that are active.