35 #ifndef __ALTERA_ALT_CLKMGR_H__
36 #define __ALTERA_ALT_CLKMGR_H__
85 #define ALT_CLKMGR_CTL_SAFEMOD_LSB 0
87 #define ALT_CLKMGR_CTL_SAFEMOD_MSB 0
89 #define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1
91 #define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001
93 #define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe
95 #define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1
97 #define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0)
99 #define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001)
113 #define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2
115 #define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2
117 #define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1
119 #define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004
121 #define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb
123 #define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1
125 #define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2)
127 #define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004)
140 struct ALT_CLKMGR_CTL_s
142 uint32_t safemode : 1;
144 uint32_t ensfmdwr : 1;
149 typedef volatile struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t;
153 #define ALT_CLKMGR_CTL_OFST 0x0
186 #define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0
188 #define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0
190 #define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1
192 #define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001
194 #define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe
196 #define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1
198 #define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0)
200 #define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001)
219 #define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1
221 #define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1
223 #define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1
225 #define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002
227 #define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd
229 #define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1
231 #define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1)
233 #define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002)
261 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0
267 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1
270 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2
272 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2
274 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1
276 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004
278 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb
280 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0
282 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2)
284 #define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004)
303 #define ALT_CLKMGR_BYPASS_PERPLL_LSB 3
305 #define ALT_CLKMGR_BYPASS_PERPLL_MSB 3
307 #define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1
309 #define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008
311 #define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7
313 #define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1
315 #define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3)
317 #define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008)
345 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0
351 #define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1
354 #define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4
356 #define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4
358 #define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1
360 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010
362 #define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef
364 #define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0
366 #define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4)
368 #define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010)
381 struct ALT_CLKMGR_BYPASS_s
383 uint32_t mainpll : 1;
385 uint32_t sdrpllsrc : 1;
387 uint32_t perpllsrc : 1;
392 typedef volatile struct ALT_CLKMGR_BYPASS_s ALT_CLKMGR_BYPASS_t;
396 #define ALT_CLKMGR_BYPASS_OFST 0x4
431 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0
433 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0
435 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1
437 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001
439 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
441 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0
443 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
445 #define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
458 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1
460 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1
462 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1
464 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002
466 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd
468 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0
470 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
472 #define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
484 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2
486 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2
488 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1
490 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004
492 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
494 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0
496 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
498 #define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
510 #define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3
512 #define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3
514 #define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1
516 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008
518 #define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7
520 #define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0
522 #define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
524 #define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
536 #define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4
538 #define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4
540 #define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1
542 #define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010
544 #define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef
546 #define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0
548 #define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
550 #define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
562 #define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5
564 #define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5
566 #define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1
568 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020
570 #define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf
572 #define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0
574 #define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
576 #define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
588 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6
590 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6
592 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1
594 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040
596 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf
598 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0
600 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6)
602 #define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040)
614 #define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7
616 #define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7
618 #define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1
620 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080
622 #define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f
624 #define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0
626 #define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7)
628 #define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080)
640 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8
642 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8
644 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1
646 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100
648 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff
650 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0
652 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
654 #define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
667 struct ALT_CLKMGR_INTER_s
669 uint32_t mainpllachieved : 1;
670 uint32_t perpllachieved : 1;
671 uint32_t sdrpllachieved : 1;
672 uint32_t mainplllost : 1;
673 uint32_t perplllost : 1;
674 uint32_t sdrplllost : 1;
675 const uint32_t mainplllocked : 1;
676 const uint32_t perplllocked : 1;
677 const uint32_t sdrplllocked : 1;
682 typedef volatile struct ALT_CLKMGR_INTER_s ALT_CLKMGR_INTER_t;
686 #define ALT_CLKMGR_INTER_OFST 0x8
719 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
721 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
723 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
725 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
727 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
729 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
731 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
733 #define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
746 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
748 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
750 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
752 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
754 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
756 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
758 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
760 #define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
773 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2
775 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2
777 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1
779 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004
781 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
783 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0
785 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
787 #define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
800 #define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3
802 #define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3
804 #define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
806 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008
808 #define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7
810 #define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
812 #define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
814 #define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
827 #define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4
829 #define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4
831 #define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
833 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010
835 #define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef
837 #define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
839 #define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
841 #define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
854 #define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5
856 #define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5
858 #define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1
860 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020
862 #define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf
864 #define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0
866 #define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
868 #define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
881 struct ALT_CLKMGR_INTREN_s
883 uint32_t mainpllachieved : 1;
884 uint32_t perpllachieved : 1;
885 uint32_t sdrpllachieved : 1;
886 uint32_t mainplllost : 1;
887 uint32_t perplllost : 1;
888 uint32_t sdrplllost : 1;
893 typedef volatile struct ALT_CLKMGR_INTREN_s ALT_CLKMGR_INTREN_t;
897 #define ALT_CLKMGR_INTREN_OFST 0xc
929 #define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0
931 #define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0
933 #define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1
935 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001
937 #define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe
939 #define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1
941 #define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0)
943 #define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001)
962 #define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1
964 #define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1
966 #define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1
968 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002
970 #define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd
972 #define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1
974 #define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1)
976 #define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002)
989 struct ALT_CLKMGR_DBCTL_s
991 uint32_t stayosc1 : 1;
992 uint32_t ensfmdwr : 1;
997 typedef volatile struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t;
1001 #define ALT_CLKMGR_DBCTL_OFST 0x10
1044 #define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
1050 #define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
1053 #define ALT_CLKMGR_STAT_BUSY_LSB 0
1055 #define ALT_CLKMGR_STAT_BUSY_MSB 0
1057 #define ALT_CLKMGR_STAT_BUSY_WIDTH 1
1059 #define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1061 #define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1063 #define ALT_CLKMGR_STAT_BUSY_RESET 0x0
1065 #define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1067 #define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1069 #ifndef __ASSEMBLY__
1080 struct ALT_CLKMGR_STAT_s
1082 const uint32_t busy : 1;
1087 typedef volatile struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t;
1091 #define ALT_CLKMGR_STAT_OFST 0x14
1133 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0
1135 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0
1137 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1
1139 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001
1141 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
1143 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1
1145 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
1147 #define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
1158 #define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1
1160 #define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1
1162 #define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1
1164 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002
1166 #define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd
1168 #define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0
1170 #define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
1172 #define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
1183 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2
1185 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2
1187 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1
1189 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004
1191 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
1193 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1
1195 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
1197 #define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
1211 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3
1213 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15
1215 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13
1217 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8
1219 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007
1221 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1
1223 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
1225 #define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
1239 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16
1241 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21
1243 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6
1245 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000
1247 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
1249 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1
1251 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
1253 #define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
1271 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24
1273 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24
1275 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1
1277 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
1279 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
1281 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0
1283 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
1285 #define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
1312 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25
1314 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30
1316 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6
1318 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000
1320 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
1322 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0
1324 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
1326 #define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
1349 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31
1351 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31
1353 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1
1355 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
1357 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
1359 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1
1361 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
1363 #define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
1365 #ifndef __ASSEMBLY__
1376 struct ALT_CLKMGR_MAINPLL_VCO_s
1378 uint32_t bgpwrdn : 1;
1381 uint32_t numer : 13;
1384 uint32_t outresetall : 1;
1385 uint32_t outreset : 6;
1386 uint32_t regextsel : 1;
1390 typedef volatile struct ALT_CLKMGR_MAINPLL_VCO_s ALT_CLKMGR_MAINPLL_VCO_t;
1394 #define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0
1429 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0
1431 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0
1433 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1
1435 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001
1437 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
1439 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0
1441 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
1443 #define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
1454 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1
1456 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12
1458 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12
1460 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe
1462 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001
1464 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1
1466 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
1468 #define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
1479 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13
1481 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13
1483 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1
1485 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000
1487 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
1489 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0
1491 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
1493 #define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
1504 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14
1506 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14
1508 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1
1510 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000
1512 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff
1514 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1
1516 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
1518 #define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
1520 #ifndef __ASSEMBLY__
1531 struct ALT_CLKMGR_MAINPLL_MISC_s
1533 uint32_t bwadjen : 1;
1534 uint32_t bwadj : 12;
1535 uint32_t fasten : 1;
1541 typedef volatile struct ALT_CLKMGR_MAINPLL_MISC_s ALT_CLKMGR_MAINPLL_MISC_t;
1545 #define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4
1572 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
1574 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8
1576 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9
1578 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff
1580 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00
1582 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
1584 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1586 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1588 #ifndef __ASSEMBLY__
1599 struct ALT_CLKMGR_MAINPLL_MPUCLK_s
1606 typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t;
1610 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8
1637 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0
1639 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8
1641 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9
1643 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff
1645 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00
1647 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0
1649 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1651 #define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1653 #ifndef __ASSEMBLY__
1664 struct ALT_CLKMGR_MAINPLL_MAINCLK_s
1671 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINCLK_s ALT_CLKMGR_MAINPLL_MAINCLK_t;
1675 #define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc
1702 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0
1704 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8
1706 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9
1708 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff
1710 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00
1712 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0
1714 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1716 #define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1718 #ifndef __ASSEMBLY__
1729 struct ALT_CLKMGR_MAINPLL_DBGATCLK_s
1736 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGATCLK_s ALT_CLKMGR_MAINPLL_DBGATCLK_t;
1740 #define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10
1767 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0
1769 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8
1771 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9
1773 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff
1775 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00
1777 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3
1779 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1781 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1783 #ifndef __ASSEMBLY__
1794 struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s
1801 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINQSPICLK_s ALT_CLKMGR_MAINPLL_MAINQSPICLK_t;
1805 #define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14
1832 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0
1834 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8
1836 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9
1838 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
1840 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
1842 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3
1844 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1846 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1848 #ifndef __ASSEMBLY__
1859 struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s
1866 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t;
1870 #define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18
1899 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0
1901 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8
1903 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9
1905 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff
1907 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00
1909 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf
1911 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1913 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1915 #ifndef __ASSEMBLY__
1926 struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s
1933 typedef volatile struct ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t;
1937 #define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c
1976 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0
1978 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0
1980 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1
1982 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001
1984 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe
1986 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1
1988 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0)
1990 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001)
2001 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1
2003 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1
2005 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1
2007 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002
2009 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd
2011 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1
2013 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1)
2015 #define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002)
2026 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2
2028 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2
2030 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1
2032 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004
2034 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb
2036 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1
2038 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2)
2040 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004)
2051 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3
2053 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3
2055 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1
2057 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008
2059 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7
2061 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1
2063 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3)
2065 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008)
2076 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4
2078 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4
2080 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1
2082 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010
2084 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef
2086 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1
2088 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4)
2090 #define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010)
2101 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5
2103 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5
2105 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1
2107 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020
2109 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf
2111 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1
2113 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5)
2115 #define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020)
2126 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6
2128 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6
2130 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1
2132 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040
2134 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf
2136 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1
2138 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6)
2140 #define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040)
2151 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7
2153 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7
2155 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1
2157 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080
2159 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f
2161 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1
2163 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7)
2165 #define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080)
2176 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8
2178 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8
2180 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1
2182 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100
2184 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff
2186 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1
2188 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8)
2190 #define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100)
2203 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9
2205 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9
2207 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1
2209 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200
2211 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff
2213 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1
2215 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9)
2217 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200)
2219 #ifndef __ASSEMBLY__
2230 struct ALT_CLKMGR_MAINPLL_EN_s
2232 uint32_t l4mainclk : 1;
2233 uint32_t l3mpclk : 1;
2234 uint32_t l4mpclk : 1;
2235 uint32_t l4spclk : 1;
2236 uint32_t dbgatclk : 1;
2237 uint32_t dbgclk : 1;
2238 uint32_t dbgtraceclk : 1;
2239 uint32_t dbgtimerclk : 1;
2240 uint32_t cfgclk : 1;
2241 uint32_t s2fuser0clk : 1;
2246 typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t;
2250 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x20
2292 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0
2298 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1
2301 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0
2303 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1
2305 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2
2307 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003
2309 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc
2311 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0
2313 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0)
2315 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003)
2338 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0
2344 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1
2347 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2
2349 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3
2351 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2
2353 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c
2355 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3
2357 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0
2359 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2)
2361 #define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c)
2390 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0
2396 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1
2402 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2
2408 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3
2414 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4
2420 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5
2426 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6
2432 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7
2435 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4
2437 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6
2439 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3
2441 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070
2443 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f
2445 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0
2447 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4)
2449 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070)
2478 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0
2484 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1
2490 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2
2496 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3
2502 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4
2508 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5
2514 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6
2520 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7
2523 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7
2525 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9
2527 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3
2529 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380
2531 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f
2533 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0
2535 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7)
2537 #define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380)
2539 #ifndef __ASSEMBLY__
2550 struct ALT_CLKMGR_MAINPLL_MAINDIV_s
2552 uint32_t l3mpclk : 2;
2553 uint32_t l3spclk : 2;
2554 uint32_t l4mpclk : 3;
2555 uint32_t l4spclk : 3;
2560 typedef volatile struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t;
2564 #define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24
2605 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0
2611 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1
2617 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2
2620 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0
2622 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1
2624 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2
2626 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003
2628 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc
2630 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0
2632 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0)
2634 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003)
2657 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1
2663 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2
2666 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2
2668 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3
2670 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2
2672 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c
2674 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3
2676 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1
2678 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2)
2680 #define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c)
2682 #ifndef __ASSEMBLY__
2693 struct ALT_CLKMGR_MAINPLL_DBGDIV_s
2695 uint32_t dbgatclk : 2;
2696 uint32_t dbgclk : 2;
2701 typedef volatile struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t;
2705 #define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28
2750 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0
2756 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1
2762 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2
2768 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3
2774 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4
2780 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5
2786 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6
2792 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7
2795 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0
2797 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2
2799 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3
2801 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007
2803 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8
2805 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0
2807 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0)
2809 #define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007)
2811 #ifndef __ASSEMBLY__
2822 struct ALT_CLKMGR_MAINPLL_TRACEDIV_s
2824 uint32_t traceclk : 3;
2829 typedef volatile struct ALT_CLKMGR_MAINPLL_TRACEDIV_s ALT_CLKMGR_MAINPLL_TRACEDIV_t;
2833 #define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c
2871 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0
2877 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1
2880 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0
2882 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0
2884 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1
2886 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001
2888 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe
2890 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0
2892 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0)
2894 #define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001)
2916 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0
2922 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1
2925 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1
2927 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1
2929 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1
2931 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002
2933 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd
2935 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0
2937 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1)
2939 #define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002)
2941 #ifndef __ASSEMBLY__
2952 struct ALT_CLKMGR_MAINPLL_L4SRC_s
2960 typedef volatile struct ALT_CLKMGR_MAINPLL_L4SRC_s ALT_CLKMGR_MAINPLL_L4SRC_t;
2964 #define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30
3011 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0
3017 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
3020 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0
3022 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5
3024 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6
3026 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
3028 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
3030 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0
3032 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
3034 #define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
3036 #ifndef __ASSEMBLY__
3047 struct ALT_CLKMGR_MAINPLL_STAT_s
3049 const uint32_t outresetack : 6;
3054 typedef volatile struct ALT_CLKMGR_MAINPLL_STAT_s ALT_CLKMGR_MAINPLL_STAT_t;
3058 #define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34
3060 #ifndef __ASSEMBLY__
3071 struct ALT_CLKMGR_MAINPLL_s
3073 ALT_CLKMGR_MAINPLL_VCO_t vco;
3074 ALT_CLKMGR_MAINPLL_MISC_t misc;
3075 ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk;
3076 ALT_CLKMGR_MAINPLL_MAINCLK_t mainclk;
3077 ALT_CLKMGR_MAINPLL_DBGATCLK_t dbgatclk;
3078 ALT_CLKMGR_MAINPLL_MAINQSPICLK_t mainqspiclk;
3079 ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t mainnandsdmmcclk;
3080 ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t cfgs2fuser0clk;
3081 ALT_CLKMGR_MAINPLL_EN_t en;
3082 ALT_CLKMGR_MAINPLL_MAINDIV_t maindiv;
3083 ALT_CLKMGR_MAINPLL_DBGDIV_t dbgdiv;
3084 ALT_CLKMGR_MAINPLL_TRACEDIV_t tracediv;
3085 ALT_CLKMGR_MAINPLL_L4SRC_t l4src;
3086 ALT_CLKMGR_MAINPLL_STAT_t stat;
3087 volatile uint32_t _pad_0x38_0x40[2];
3091 typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t;
3093 struct ALT_CLKMGR_MAINPLL_raw_s
3095 volatile uint32_t vco;
3096 volatile uint32_t misc;
3097 volatile uint32_t mpuclk;
3098 volatile uint32_t mainclk;
3099 volatile uint32_t dbgatclk;
3100 volatile uint32_t mainqspiclk;
3101 volatile uint32_t mainnandsdmmcclk;
3102 volatile uint32_t cfgs2fuser0clk;
3103 volatile uint32_t en;
3104 volatile uint32_t maindiv;
3105 volatile uint32_t dbgdiv;
3106 volatile uint32_t tracediv;
3107 volatile uint32_t l4src;
3108 volatile uint32_t stat;
3109 uint32_t _pad_0x38_0x40[2];
3113 typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t;
3157 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0
3159 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0
3161 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1
3163 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001
3165 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
3167 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1
3169 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
3171 #define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
3182 #define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1
3184 #define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1
3186 #define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1
3188 #define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002
3190 #define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd
3192 #define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0
3194 #define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
3196 #define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
3207 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2
3209 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2
3211 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1
3213 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004
3215 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
3217 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1
3219 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
3221 #define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
3235 #define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3
3237 #define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15
3239 #define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13
3241 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8
3243 #define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007
3245 #define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1
3247 #define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
3249 #define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
3263 #define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16
3265 #define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21
3267 #define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6
3269 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000
3271 #define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
3273 #define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1
3275 #define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
3277 #define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
3302 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0
3308 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1
3314 #define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2
3317 #define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22
3319 #define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23
3321 #define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2
3323 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000
3325 #define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff
3327 #define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0
3329 #define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22)
3331 #define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000)
3349 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24
3351 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24
3353 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1
3355 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
3357 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
3359 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0
3361 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
3363 #define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
3390 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25
3392 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30
3394 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6
3396 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000
3398 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
3400 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0
3402 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
3404 #define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
3427 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31
3429 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31
3431 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1
3433 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
3435 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
3437 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1
3439 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
3441 #define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
3443 #ifndef __ASSEMBLY__
3454 struct ALT_CLKMGR_PERPLL_VCO_s
3456 uint32_t bgpwrdn : 1;
3459 uint32_t numer : 13;
3462 uint32_t outresetall : 1;
3463 uint32_t outreset : 6;
3464 uint32_t regextsel : 1;
3468 typedef volatile struct ALT_CLKMGR_PERPLL_VCO_s ALT_CLKMGR_PERPLL_VCO_t;
3472 #define ALT_CLKMGR_PERPLL_VCO_OFST 0x0
3507 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0
3509 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0
3511 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1
3513 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001
3515 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
3517 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0
3519 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
3521 #define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
3532 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1
3534 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12
3536 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12
3538 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe
3540 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001
3542 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1
3544 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
3546 #define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
3557 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13
3559 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13
3561 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1
3563 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000
3565 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
3567 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0
3569 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
3571 #define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
3582 #define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14
3584 #define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14
3586 #define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1
3588 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000
3590 #define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff
3592 #define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1
3594 #define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
3596 #define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
3598 #ifndef __ASSEMBLY__
3609 struct ALT_CLKMGR_PERPLL_MISC_s
3611 uint32_t bwadjen : 1;
3612 uint32_t bwadj : 12;
3613 uint32_t fasten : 1;
3619 typedef volatile struct ALT_CLKMGR_PERPLL_MISC_s ALT_CLKMGR_PERPLL_MISC_t;
3623 #define ALT_CLKMGR_PERPLL_MISC_OFST 0x4
3650 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0
3652 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8
3654 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9
3656 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff
3658 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00
3660 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1
3662 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3664 #define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3666 #ifndef __ASSEMBLY__
3677 struct ALT_CLKMGR_PERPLL_EMAC0CLK_s
3684 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC0CLK_s ALT_CLKMGR_PERPLL_EMAC0CLK_t;
3688 #define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8
3715 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0
3717 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8
3719 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9
3721 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff
3723 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00
3725 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1
3727 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3729 #define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3731 #ifndef __ASSEMBLY__
3742 struct ALT_CLKMGR_PERPLL_EMAC1CLK_s
3749 typedef volatile struct ALT_CLKMGR_PERPLL_EMAC1CLK_s ALT_CLKMGR_PERPLL_EMAC1CLK_t;
3753 #define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc
3780 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0
3782 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8
3784 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9
3786 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff
3788 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00
3790 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1
3792 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3794 #define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3796 #ifndef __ASSEMBLY__
3807 struct ALT_CLKMGR_PERPLL_PERQSPICLK_s
3814 typedef volatile struct ALT_CLKMGR_PERPLL_PERQSPICLK_s ALT_CLKMGR_PERPLL_PERQSPICLK_t;
3818 #define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10
3845 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0
3847 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8
3849 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9
3851 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
3853 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
3855 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1
3857 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3859 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3861 #ifndef __ASSEMBLY__
3872 struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s
3879 typedef volatile struct ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t;
3883 #define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14
3910 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0
3912 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8
3914 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9
3916 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff
3918 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00
3920 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1
3922 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3924 #define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3926 #ifndef __ASSEMBLY__
3937 struct ALT_CLKMGR_PERPLL_PERBASECLK_s
3944 typedef volatile struct ALT_CLKMGR_PERPLL_PERBASECLK_s ALT_CLKMGR_PERPLL_PERBASECLK_t;
3948 #define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18
3977 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0
3979 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8
3981 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9
3983 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff
3985 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00
3987 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1
3989 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3991 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3993 #ifndef __ASSEMBLY__
4004 struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s
4011 typedef volatile struct ALT_CLKMGR_PERPLL_S2FUSER1CLK_s ALT_CLKMGR_PERPLL_S2FUSER1CLK_t;
4015 #define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c
4057 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0
4059 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0
4061 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1
4063 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001
4065 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe
4067 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1
4069 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0)
4071 #define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001)
4082 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1
4084 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1
4086 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1
4088 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002
4090 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd
4092 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1
4094 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1)
4096 #define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002)
4107 #define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2
4109 #define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2
4111 #define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1
4113 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004
4115 #define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb
4117 #define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1
4119 #define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2)
4121 #define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004)
4132 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3
4134 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3
4136 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1
4138 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008
4140 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7
4142 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1
4144 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3)
4146 #define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008)
4157 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4
4159 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4
4161 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1
4163 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010
4165 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef
4167 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1
4169 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4)
4171 #define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010)
4182 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5
4184 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5
4186 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1
4188 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020
4190 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf
4192 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1
4194 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5)
4196 #define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020)
4207 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6
4209 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6
4211 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1
4213 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040
4215 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf
4217 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1
4219 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6)
4221 #define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040)
4234 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7
4236 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7
4238 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1
4240 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080
4242 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f
4244 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1
4246 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7)
4248 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080)
4259 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8
4261 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8
4263 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1
4265 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100
4267 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff
4269 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1
4271 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8)
4273 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100)
4289 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9
4291 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9
4293 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1
4295 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200
4297 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff
4299 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1
4301 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9)
4303 #define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200)
4319 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10
4321 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10
4323 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1
4325 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400
4327 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff
4329 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1
4331 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10)
4333 #define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400)
4344 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11
4346 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11
4348 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1
4350 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800
4352 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff
4354 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1
4356 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11)
4358 #define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800)
4360 #ifndef __ASSEMBLY__
4371 struct ALT_CLKMGR_PERPLL_EN_s
4373 uint32_t emac0clk : 1;
4374 uint32_t emac1clk : 1;
4375 uint32_t usbclk : 1;
4376 uint32_t spimclk : 1;
4377 uint32_t can0clk : 1;
4378 uint32_t can1clk : 1;
4379 uint32_t gpioclk : 1;
4380 uint32_t s2fuser1clk : 1;
4381 uint32_t sdmmcclk : 1;
4382 uint32_t nandxclk : 1;
4383 uint32_t nandclk : 1;
4384 uint32_t qspiclk : 1;
4389 typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
4393 #define ALT_CLKMGR_PERPLL_EN_OFST 0x20
4441 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0
4447 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1
4453 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2
4459 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3
4465 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4
4471 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5
4477 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6
4483 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7
4486 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0
4488 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2
4490 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3
4492 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007
4494 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8
4496 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0
4498 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0)
4500 #define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007)
4529 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0
4535 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1
4541 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2
4547 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3
4553 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4
4559 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5
4565 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6
4571 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7
4574 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3
4576 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5
4578 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3
4580 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038
4582 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7
4584 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0
4586 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3)
4588 #define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038)
4617 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0
4623 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1
4629 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2
4635 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3
4641 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4
4647 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5
4653 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6
4659 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7
4662 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6
4664 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8
4666 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3
4668 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0
4670 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f
4672 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0
4674 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6)
4676 #define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0)
4705 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0
4711 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1
4717 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2
4723 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3
4729 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4
4735 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5
4741 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6
4747 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7
4750 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9
4752 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11
4754 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3
4756 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00
4758 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff
4760 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0
4762 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9)
4764 #define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00)
4766 #ifndef __ASSEMBLY__
4777 struct ALT_CLKMGR_PERPLL_DIV_s
4779 uint32_t usbclk : 3;
4780 uint32_t spimclk : 3;
4781 uint32_t can0clk : 3;
4782 uint32_t can1clk : 3;
4787 typedef volatile struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t;
4791 #define ALT_CLKMGR_PERPLL_DIV_OFST 0x24
4819 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
4821 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23
4823 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24
4825 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff
4827 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000
4829 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
4831 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0)
4833 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff)
4835 #ifndef __ASSEMBLY__
4846 struct ALT_CLKMGR_PERPLL_GPIODIV_s
4848 uint32_t gpiodbclk : 24;
4853 typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
4857 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28
4899 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0
4905 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1
4911 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2
4914 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0
4916 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1
4918 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2
4920 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003
4922 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc
4924 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1
4926 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0)
4928 #define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003)
4953 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0
4959 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1
4965 #define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2
4968 #define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2
4970 #define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3
4972 #define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2
4974 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c
4976 #define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3
4978 #define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1
4980 #define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2)
4982 #define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c)
5007 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0
5013 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1
5019 #define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2
5022 #define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4
5024 #define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5
5026 #define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2
5028 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030
5030 #define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf
5032 #define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1
5034 #define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4)
5036 #define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030)
5038 #ifndef __ASSEMBLY__
5049 struct ALT_CLKMGR_PERPLL_SRC_s
5058 typedef volatile struct ALT_CLKMGR_PERPLL_SRC_s ALT_CLKMGR_PERPLL_SRC_t;
5062 #define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c
5109 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0
5115 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
5118 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0
5120 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5
5122 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6
5124 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
5126 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
5128 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0
5130 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
5132 #define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
5134 #ifndef __ASSEMBLY__
5145 struct ALT_CLKMGR_PERPLL_STAT_s
5147 const uint32_t outresetack : 6;
5152 typedef volatile struct ALT_CLKMGR_PERPLL_STAT_s ALT_CLKMGR_PERPLL_STAT_t;
5156 #define ALT_CLKMGR_PERPLL_STAT_OFST 0x30
5158 #ifndef __ASSEMBLY__
5169 struct ALT_CLKMGR_PERPLL_s
5171 ALT_CLKMGR_PERPLL_VCO_t vco;
5172 ALT_CLKMGR_PERPLL_MISC_t misc;
5173 ALT_CLKMGR_PERPLL_EMAC0CLK_t emac0clk;
5174 ALT_CLKMGR_PERPLL_EMAC1CLK_t emac1clk;
5175 ALT_CLKMGR_PERPLL_PERQSPICLK_t perqspiclk;
5176 ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t pernandsdmmcclk;
5177 ALT_CLKMGR_PERPLL_PERBASECLK_t perbaseclk;
5178 ALT_CLKMGR_PERPLL_S2FUSER1CLK_t s2fuser1clk;
5179 ALT_CLKMGR_PERPLL_EN_t en;
5180 ALT_CLKMGR_PERPLL_DIV_t div;
5181 ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv;
5182 ALT_CLKMGR_PERPLL_SRC_t src;
5183 ALT_CLKMGR_PERPLL_STAT_t stat;
5184 volatile uint32_t _pad_0x34_0x40[3];
5188 typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
5190 struct ALT_CLKMGR_PERPLL_raw_s
5192 volatile uint32_t vco;
5193 volatile uint32_t misc;
5194 volatile uint32_t emac0clk;
5195 volatile uint32_t emac1clk;
5196 volatile uint32_t perqspiclk;
5197 volatile uint32_t pernandsdmmcclk;
5198 volatile uint32_t perbaseclk;
5199 volatile uint32_t s2fuser1clk;
5200 volatile uint32_t en;
5201 volatile uint32_t div;
5202 volatile uint32_t gpiodiv;
5203 volatile uint32_t src;
5204 volatile uint32_t stat;
5205 uint32_t _pad_0x34_0x40[3];
5209 typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;
5253 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0
5255 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0
5257 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1
5259 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001
5261 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
5263 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1
5265 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5267 #define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5278 #define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1
5280 #define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1
5282 #define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1
5284 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002
5286 #define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd
5288 #define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0
5290 #define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
5292 #define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
5303 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2
5305 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2
5307 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1
5309 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004
5311 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
5313 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1
5315 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
5317 #define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
5331 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3
5333 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15
5335 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13
5337 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8
5339 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007
5341 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1
5343 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
5345 #define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
5359 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16
5361 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21
5363 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6
5365 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000
5367 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
5369 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1
5371 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
5373 #define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
5399 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0
5405 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1
5411 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2
5414 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22
5416 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23
5418 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2
5420 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000
5422 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff
5424 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0
5426 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22)
5428 #define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000)
5446 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24
5448 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24
5450 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1
5452 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
5454 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
5456 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0
5458 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
5460 #define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
5487 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25
5489 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30
5491 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6
5493 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000
5495 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
5497 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0
5499 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
5501 #define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
5524 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31
5526 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31
5528 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1
5530 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
5532 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
5534 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1
5536 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
5538 #define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
5540 #ifndef __ASSEMBLY__
5551 struct ALT_CLKMGR_SDRPLL_VCO_s
5553 uint32_t bgpwrdn : 1;
5556 uint32_t numer : 13;
5559 uint32_t outresetall : 1;
5560 uint32_t outreset : 6;
5561 uint32_t regextsel : 1;
5565 typedef volatile struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t;
5569 #define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0
5604 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0
5606 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0
5608 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1
5610 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001
5612 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe
5614 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0
5616 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
5618 #define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
5629 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1
5631 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12
5633 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12
5635 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe
5637 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001
5639 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1
5641 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
5643 #define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
5654 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13
5656 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13
5658 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1
5660 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000
5662 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff
5664 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0
5666 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
5668 #define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000)
5679 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14
5681 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14
5683 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1
5685 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000
5687 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff
5689 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1
5691 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14)
5693 #define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000)
5695 #ifndef __ASSEMBLY__
5706 struct ALT_CLKMGR_SDRPLL_CTL_s
5708 uint32_t bwadjen : 1;
5709 uint32_t bwadj : 12;
5710 uint32_t fasten : 1;
5716 typedef volatile struct ALT_CLKMGR_SDRPLL_CTL_s ALT_CLKMGR_SDRPLL_CTL_t;
5720 #define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4
5748 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0
5750 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8
5752 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9
5754 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff
5756 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00
5758 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1
5760 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5762 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5781 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9
5783 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20
5785 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12
5787 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00
5789 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff
5791 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0
5793 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5795 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5797 #ifndef __ASSEMBLY__
5808 struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s
5811 uint32_t phase : 12;
5816 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQSCLK_s ALT_CLKMGR_SDRPLL_DDRDQSCLK_t;
5820 #define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8
5848 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0
5850 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8
5852 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9
5854 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff
5856 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00
5858 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1
5860 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5862 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5881 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9
5883 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20
5885 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12
5887 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00
5889 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff
5891 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0
5893 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5895 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5897 #ifndef __ASSEMBLY__
5908 struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s
5911 uint32_t phase : 12;
5916 typedef volatile struct ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t;
5920 #define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc
5948 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0
5950 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8
5952 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9
5954 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff
5956 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00
5958 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1
5960 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5962 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5981 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9
5983 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20
5985 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12
5987 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00
5989 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff
5991 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0
5993 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5995 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5997 #ifndef __ASSEMBLY__
6008 struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s
6011 uint32_t phase : 12;
6016 typedef volatile struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t;
6020 #define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10
6050 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0
6052 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8
6054 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9
6056 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff
6058 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00
6060 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1
6062 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6064 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6083 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9
6085 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20
6087 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12
6089 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00
6091 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff
6093 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0
6095 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
6097 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
6099 #ifndef __ASSEMBLY__
6110 struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s
6113 uint32_t phase : 12;
6118 typedef volatile struct ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t;
6122 #define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14
6156 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0
6158 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0
6160 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1
6162 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001
6164 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe
6166 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1
6168 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0)
6170 #define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001)
6181 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1
6183 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1
6185 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1
6187 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002
6189 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd
6191 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1
6193 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1)
6195 #define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002)
6206 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2
6208 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2
6210 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1
6212 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004
6214 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb
6216 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1
6218 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2)
6220 #define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004)
6233 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3
6235 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3
6237 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1
6239 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008
6241 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7
6243 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1
6245 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3)
6247 #define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008)
6249 #ifndef __ASSEMBLY__
6260 struct ALT_CLKMGR_SDRPLL_EN_s
6262 uint32_t ddrdqsclk : 1;
6263 uint32_t ddr2xdqsclk : 1;
6264 uint32_t ddrdqclk : 1;
6265 uint32_t s2fuser2clk : 1;
6270 typedef volatile struct ALT_CLKMGR_SDRPLL_EN_s ALT_CLKMGR_SDRPLL_EN_t;
6274 #define ALT_CLKMGR_SDRPLL_EN_OFST 0x18
6321 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0
6327 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
6330 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0
6332 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5
6334 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6
6336 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
6338 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
6340 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0
6342 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
6344 #define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
6346 #ifndef __ASSEMBLY__
6357 struct ALT_CLKMGR_SDRPLL_STAT_s
6359 const uint32_t outresetack : 6;
6364 typedef volatile struct ALT_CLKMGR_SDRPLL_STAT_s ALT_CLKMGR_SDRPLL_STAT_t;
6368 #define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c
6370 #ifndef __ASSEMBLY__
6381 struct ALT_CLKMGR_SDRPLL_s
6383 ALT_CLKMGR_SDRPLL_VCO_t vco;
6384 ALT_CLKMGR_SDRPLL_CTL_t ctrl;
6385 ALT_CLKMGR_SDRPLL_DDRDQSCLK_t ddrdqsclk;
6386 ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t ddr2xdqsclk;
6387 ALT_CLKMGR_SDRPLL_DDRDQCLK_t ddrdqclk;
6388 ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t s2fuser2clk;
6389 ALT_CLKMGR_SDRPLL_EN_t en;
6390 ALT_CLKMGR_SDRPLL_STAT_t stat;
6394 typedef volatile struct ALT_CLKMGR_SDRPLL_s ALT_CLKMGR_SDRPLL_t;
6396 struct ALT_CLKMGR_SDRPLL_raw_s
6398 volatile uint32_t vco;
6399 volatile uint32_t ctrl;
6400 volatile uint32_t ddrdqsclk;
6401 volatile uint32_t ddr2xdqsclk;
6402 volatile uint32_t ddrdqclk;
6403 volatile uint32_t s2fuser2clk;
6404 volatile uint32_t en;
6405 volatile uint32_t stat;
6409 typedef volatile struct ALT_CLKMGR_SDRPLL_raw_s ALT_CLKMGR_SDRPLL_raw_t;
6445 #define ALT_CLKMGR_MISC_MPUCLK_CNT_LSB 0
6447 #define ALT_CLKMGR_MISC_MPUCLK_CNT_MSB 8
6449 #define ALT_CLKMGR_MISC_MPUCLK_CNT_WIDTH 9
6451 #define ALT_CLKMGR_MISC_MPUCLK_CNT_SET_MSK 0x000001ff
6453 #define ALT_CLKMGR_MISC_MPUCLK_CNT_CLR_MSK 0xfffffe00
6455 #define ALT_CLKMGR_MISC_MPUCLK_CNT_RESET 0x1
6457 #define ALT_CLKMGR_MISC_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6459 #define ALT_CLKMGR_MISC_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6461 #ifndef __ASSEMBLY__
6472 struct ALT_CLKMGR_MISC_MPUCLK_s
6479 typedef volatile struct ALT_CLKMGR_MISC_MPUCLK_s ALT_CLKMGR_MISC_MPUCLK_t;
6483 #define ALT_CLKMGR_MISC_MPUCLK_OFST 0x0
6510 #define ALT_CLKMGR_MISC_MAINCLK_CNT_LSB 0
6512 #define ALT_CLKMGR_MISC_MAINCLK_CNT_MSB 8
6514 #define ALT_CLKMGR_MISC_MAINCLK_CNT_WIDTH 9
6516 #define ALT_CLKMGR_MISC_MAINCLK_CNT_SET_MSK 0x000001ff
6518 #define ALT_CLKMGR_MISC_MAINCLK_CNT_CLR_MSK 0xfffffe00
6520 #define ALT_CLKMGR_MISC_MAINCLK_CNT_RESET 0x3
6522 #define ALT_CLKMGR_MISC_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6524 #define ALT_CLKMGR_MISC_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6526 #ifndef __ASSEMBLY__
6537 struct ALT_CLKMGR_MISC_MAINCLK_s
6544 typedef volatile struct ALT_CLKMGR_MISC_MAINCLK_s ALT_CLKMGR_MISC_MAINCLK_t;
6548 #define ALT_CLKMGR_MISC_MAINCLK_OFST 0x4
6575 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_LSB 0
6577 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_MSB 8
6579 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_WIDTH 9
6581 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET_MSK 0x000001ff
6583 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_CLR_MSK 0xfffffe00
6585 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_RESET 0x3
6587 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6589 #define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6591 #ifndef __ASSEMBLY__
6602 struct ALT_CLKMGR_MISC_DBGATCLK_s
6609 typedef volatile struct ALT_CLKMGR_MISC_DBGATCLK_s ALT_CLKMGR_MISC_DBGATCLK_t;
6613 #define ALT_CLKMGR_MISC_DBGATCLK_OFST 0x8
6615 #ifndef __ASSEMBLY__
6626 struct ALT_CLKMGR_MISCGRP_s
6628 ALT_CLKMGR_MISC_MPUCLK_t mpuclk;
6629 ALT_CLKMGR_MISC_MAINCLK_t mainclk;
6630 ALT_CLKMGR_MISC_DBGATCLK_t dbgatclk;
6631 volatile uint32_t _pad_0xc_0x20[5];
6635 typedef volatile struct ALT_CLKMGR_MISCGRP_s ALT_CLKMGR_MISCGRP_t;
6637 struct ALT_CLKMGR_MISCGRP_raw_s
6639 volatile uint32_t mpuclk;
6640 volatile uint32_t mainclk;
6641 volatile uint32_t dbgatclk;
6642 uint32_t _pad_0xc_0x20[5];
6646 typedef volatile struct ALT_CLKMGR_MISCGRP_raw_s ALT_CLKMGR_MISCGRP_raw_t;
6650 #ifndef __ASSEMBLY__
6663 ALT_CLKMGR_CTL_t ctrl;
6664 ALT_CLKMGR_BYPASS_t bypass;
6665 ALT_CLKMGR_INTER_t inter;
6666 ALT_CLKMGR_INTREN_t intren;
6667 ALT_CLKMGR_DBCTL_t dbctrl;
6668 ALT_CLKMGR_STAT_t stat;
6669 volatile uint32_t _pad_0x18_0x3f[10];
6670 ALT_CLKMGR_MAINPLL_t mainpllgrp;
6671 ALT_CLKMGR_PERPLL_t perpllgrp;
6672 ALT_CLKMGR_SDRPLL_t sdrpllgrp;
6673 ALT_CLKMGR_MISCGRP_t miscgrp;
6674 volatile uint32_t _pad_0x100_0x200[64];
6678 typedef volatile struct ALT_CLKMGR_s ALT_CLKMGR_t;
6680 struct ALT_CLKMGR_raw_s
6682 volatile uint32_t ctrl;
6683 volatile uint32_t bypass;
6684 volatile uint32_t inter;
6685 volatile uint32_t intren;
6686 volatile uint32_t dbctrl;
6687 volatile uint32_t stat;
6688 uint32_t _pad_0x18_0x3f[10];
6689 ALT_CLKMGR_MAINPLL_raw_t mainpllgrp;
6690 ALT_CLKMGR_PERPLL_raw_t perpllgrp;
6691 ALT_CLKMGR_SDRPLL_raw_t sdrpllgrp;
6692 ALT_CLKMGR_MISCGRP_raw_t miscgrp;
6693 uint32_t _pad_0x100_0x200[64];
6697 typedef volatile struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t;