Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_clkmgr.h
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32 
33 /* Altera - ALT_CLKMGR_CLKMGR */
34 
35 #ifndef __ALT_SOCAL_CLKMGR_H__
36 #define __ALT_SOCAL_CLKMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_CLKMGR_CLKMGR
50  *
51  */
52 /*
53  * Register : Control Register - ctrl
54  *
55  * Contains fields that control the entire Clock Manager.
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:-----------------------------
61  * [0] | RW | 0x1 | Boot Mode
62  * [7:1] | ??? | 0x1 | *UNDEFINED*
63  * [8] | RW | 0x0 | SW Control Boot Clock Enable
64  * [9] | RW | 0x0 | SW Control Boot Clock Select
65  * [31:10] | ??? | 0x0 | *UNDEFINED*
66  *
67  */
68 /*
69  * Field : Boot Mode - bootmode
70  *
71  * When set the Clock Manager is in Boot Mode.
72  *
73  * In Boot Mode Clock Manager register settings defining clock behavior are ignored
74  * and clocks are set to their Boot Mode settings. All clocks will be bypassed and
75  * external HW managed counters and dividers will be set to divide by 1.
76  *
77  * This bit should only be cleared when clocks have been correctly configured.
78  *
79  * This field is set on a cold reset and optionally on a warm reset. SW may set
80  * this bit to force the clocks into Boot Mode. SW exits Boot Mode by clearing
81  * this bit.
82  *
83  * Field Access Macros:
84  *
85  */
86 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field. */
87 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_LSB 0
88 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field. */
89 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_MSB 0
90 /* The width in bits of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field. */
91 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_WIDTH 1
92 /* The mask used to set the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value. */
93 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001
94 /* The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value. */
95 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_CLR_MSK 0xfffffffe
96 /* The reset value of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field. */
97 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_RESET 0x1
98 /* Extracts the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD field value from a register. */
99 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_GET(value) (((value) & 0x00000001) >> 0)
100 /* Produces a ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value suitable for setting the register. */
101 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET(value) (((value) << 0) & 0x00000001)
102 
103 /*
104  * Field : SW Control Boot Clock Enable - swctrlbtclken
105  *
106  * If set, then Software will take control of the boot_clk mux select. If set,
107  * then swctrlbtclksel will determine the mux setting. If not set, the security
108  * features will determine the fuse settings.
109  *
110  * This bit is cleared on a cold reset. Warm reset has no affect on this bit.
111  *
112  * Field Access Macros:
113  *
114  */
115 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field. */
116 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_LSB 8
117 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field. */
118 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_MSB 8
119 /* The width in bits of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field. */
120 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_WIDTH 1
121 /* The mask used to set the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value. */
122 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET_MSK 0x00000100
123 /* The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value. */
124 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_CLR_MSK 0xfffffeff
125 /* The reset value of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field. */
126 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_RESET 0x0
127 /* Extracts the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN field value from a register. */
128 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_GET(value) (((value) & 0x00000100) >> 8)
129 /* Produces a ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value suitable for setting the register. */
130 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET(value) (((value) << 8) & 0x00000100)
131 
132 /*
133  * Field : SW Control Boot Clock Select - swctrlbtclksel
134  *
135  * This bit is only used if swctrlbtclken is set.
136  *
137  * If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2. If 0,
138  * boot_clk source will be from the external oscillator (EOSC1).
139  *
140  * This bit is cleared on a cold reset. Warm reset has no affect on this bit.
141  *
142  * Field Access Macros:
143  *
144  */
145 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field. */
146 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_LSB 9
147 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field. */
148 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_MSB 9
149 /* The width in bits of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field. */
150 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_WIDTH 1
151 /* The mask used to set the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value. */
152 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET_MSK 0x00000200
153 /* The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value. */
154 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_CLR_MSK 0xfffffdff
155 /* The reset value of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field. */
156 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_RESET 0x0
157 /* Extracts the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL field value from a register. */
158 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_GET(value) (((value) & 0x00000200) >> 9)
159 /* Produces a ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value suitable for setting the register. */
160 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET(value) (((value) << 9) & 0x00000200)
161 
162 #ifndef __ASSEMBLY__
163 /*
164  * WARNING: The C register and register group struct declarations are provided for
165  * convenience and illustrative purposes. They should, however, be used with
166  * caution as the C language standard provides no guarantees about the alignment or
167  * atomicity of device memory accesses. The recommended practice for writing
168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
169  * alt_write_word() functions.
170  *
171  * The struct declaration for register ALT_CLKMGR_CLKMGR_CTL.
172  */
173 struct ALT_CLKMGR_CLKMGR_CTL_s
174 {
175  uint32_t bootmode : 1; /* Boot Mode */
176  uint32_t : 7; /* *UNDEFINED* */
177  uint32_t swctrlbtclken : 1; /* SW Control Boot Clock Enable */
178  uint32_t swctrlbtclksel : 1; /* SW Control Boot Clock Select */
179  uint32_t : 22; /* *UNDEFINED* */
180 };
181 
182 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_CTL. */
183 typedef volatile struct ALT_CLKMGR_CLKMGR_CTL_s ALT_CLKMGR_CLKMGR_CTL_t;
184 #endif /* __ASSEMBLY__ */
185 
186 /* The reset value of the ALT_CLKMGR_CLKMGR_CTL register. */
187 #define ALT_CLKMGR_CLKMGR_CTL_RESET 0x00000003
188 /* The byte offset of the ALT_CLKMGR_CLKMGR_CTL register from the beginning of the component. */
189 #define ALT_CLKMGR_CLKMGR_CTL_OFST 0x0
190 
191 /*
192  * Register : Interrupt Status Register - intr
193  *
194  * Contains interrupt fields for Clock Manager
195  *
196  * Register Layout
197  *
198  * Bits | Access | Reset | Description
199  * :--------|:-------|:------|:-----------------------------
200  * [0] | RW | 0x0 | Main PLL Achieved Lock
201  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock
202  * [2] | RW | 0x0 | Main PLL Lost Lock
203  * [3] | RW | 0x0 | Peripheral PLL Lost Lock
204  * [7:4] | ??? | 0x0 | *UNDEFINED*
205  * [8] | RW | 0x0 | Main PLL RF Slip
206  * [9] | RW | 0x0 | Peripheral PLL RF Slip
207  * [10] | RW | 0x0 | Main PLL FB Slip
208  * [11] | RW | 0x0 | Peripheral PLL FB Slip
209  * [31:12] | ??? | 0x0 | *UNDEFINED*
210  *
211  */
212 /*
213  * Field : Main PLL Achieved Lock - mainpllachieved
214  *
215  * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
216  * If 0, the Main PLL has not achieved lock since this bit was cleared.
217  *
218  * Field Access Macros:
219  *
220  */
221 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field. */
222 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_LSB 0
223 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field. */
224 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_MSB 0
225 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field. */
226 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_WIDTH 1
227 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field value. */
228 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001
229 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field value. */
230 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
231 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field. */
232 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_RESET 0x0
233 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED field value from a register. */
234 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
235 /* Produces a ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED register field value suitable for setting the register. */
236 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
237 
238 /*
239  * Field : Peripheral PLL Achieved Lock - perpllachieved
240  *
241  * If 1, the Peripheral PLL has achieved lock at least once since this bit was
242  * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
243  * cleared.
244  *
245  * Field Access Macros:
246  *
247  */
248 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field. */
249 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_LSB 1
250 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field. */
251 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_MSB 1
252 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field. */
253 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_WIDTH 1
254 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field value. */
255 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002
256 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field value. */
257 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
258 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field. */
259 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_RESET 0x0
260 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED field value from a register. */
261 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
262 /* Produces a ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED register field value suitable for setting the register. */
263 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
264 
265 /*
266  * Field : Main PLL Lost Lock - mainplllost
267  *
268  * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
269  * the Main PLL has not lost lock since this bit was cleared.
270  *
271  * Field Access Macros:
272  *
273  */
274 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field. */
275 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_LSB 2
276 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field. */
277 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_MSB 2
278 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field. */
279 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_WIDTH 1
280 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field value. */
281 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004
282 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field value. */
283 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_CLR_MSK 0xfffffffb
284 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field. */
285 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_RESET 0x0
286 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST field value from a register. */
287 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
288 /* Produces a ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST register field value suitable for setting the register. */
289 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
290 
291 /*
292  * Field : Peripheral PLL Lost Lock - perplllost
293  *
294  * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
295  * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
296  *
297  * Field Access Macros:
298  *
299  */
300 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field. */
301 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_LSB 3
302 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field. */
303 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_MSB 3
304 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field. */
305 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_WIDTH 1
306 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field value. */
307 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008
308 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field value. */
309 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_CLR_MSK 0xfffffff7
310 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field. */
311 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_RESET 0x0
312 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST field value from a register. */
313 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
314 /* Produces a ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST register field value suitable for setting the register. */
315 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
316 
317 /*
318  * Field : Main PLL RF Slip - mainpllrfslip
319  *
320  * If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).
321  * This does not mean the PLL has lost lock, but the quality of the clock has
322  * degraded.
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field. */
328 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_LSB 8
329 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field. */
330 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_MSB 8
331 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field. */
332 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_WIDTH 1
333 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field value. */
334 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100
335 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field value. */
336 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
337 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field. */
338 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_RESET 0x0
339 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP field value from a register. */
340 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
341 /* Produces a ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP register field value suitable for setting the register. */
342 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
343 
344 /*
345  * Field : Peripheral PLL RF Slip - perpllrfslip
346  *
347  * If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too
348  * high). This does not mean the PLL has lost lock, but the quality of the clock
349  * has degraded.
350  *
351  * Field Access Macros:
352  *
353  */
354 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field. */
355 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_LSB 9
356 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field. */
357 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_MSB 9
358 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field. */
359 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_WIDTH 1
360 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field value. */
361 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200
362 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field value. */
363 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
364 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field. */
365 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_RESET 0x0
366 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP field value from a register. */
367 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
368 /* Produces a ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP register field value suitable for setting the register. */
369 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
370 
371 /*
372  * Field : Main PLL FB Slip - mainpllfbslip
373  *
374  * If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low). This
375  * does not mean the PLL has lost lock, but the quality of the clock has degraded.
376  *
377  * Field Access Macros:
378  *
379  */
380 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field. */
381 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_LSB 10
382 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field. */
383 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_MSB 10
384 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field. */
385 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_WIDTH 1
386 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field value. */
387 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400
388 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field value. */
389 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
390 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field. */
391 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_RESET 0x0
392 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP field value from a register. */
393 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
394 /* Produces a ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP register field value suitable for setting the register. */
395 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
396 
397 /*
398  * Field : Peripheral PLL FB Slip - perpllfbslip
399  *
400  * If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).
401  * This does not mean the PLL has lost lock, but the quality of the clock has
402  * degraded.
403  *
404  * Field Access Macros:
405  *
406  */
407 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field. */
408 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_LSB 11
409 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field. */
410 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_MSB 11
411 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field. */
412 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_WIDTH 1
413 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field value. */
414 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800
415 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field value. */
416 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
417 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field. */
418 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_RESET 0x0
419 /* Extracts the ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP field value from a register. */
420 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
421 /* Produces a ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP register field value suitable for setting the register. */
422 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
423 
424 #ifndef __ASSEMBLY__
425 /*
426  * WARNING: The C register and register group struct declarations are provided for
427  * convenience and illustrative purposes. They should, however, be used with
428  * caution as the C language standard provides no guarantees about the alignment or
429  * atomicity of device memory accesses. The recommended practice for writing
430  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
431  * alt_write_word() functions.
432  *
433  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTR.
434  */
435 struct ALT_CLKMGR_CLKMGR_INTR_s
436 {
437  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */
438  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */
439  uint32_t mainplllost : 1; /* Main PLL Lost Lock */
440  uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */
441  uint32_t : 4; /* *UNDEFINED* */
442  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip */
443  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip */
444  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip */
445  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip */
446  uint32_t : 20; /* *UNDEFINED* */
447 };
448 
449 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTR. */
450 typedef volatile struct ALT_CLKMGR_CLKMGR_INTR_s ALT_CLKMGR_CLKMGR_INTR_t;
451 #endif /* __ASSEMBLY__ */
452 
453 /* The reset value of the ALT_CLKMGR_CLKMGR_INTR register. */
454 #define ALT_CLKMGR_CLKMGR_INTR_RESET 0x00000000
455 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTR register from the beginning of the component. */
456 #define ALT_CLKMGR_CLKMGR_INTR_OFST 0x4
457 
458 /*
459  * Register : Interrupt Status Register Set - intrs
460  *
461  * Contains fields that indicate the PLL lock status.
462  *
463  * Register Layout
464  *
465  * Bits | Access | Reset | Description
466  * :--------|:-------|:------|:-----------------------------
467  * [0] | RW | 0x0 | Main PLL Achieved Lock
468  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock
469  * [2] | RW | 0x0 | Main PLL Lost Lock
470  * [3] | RW | 0x0 | Peripheral PLL Lost Lock
471  * [7:4] | ??? | 0x0 | *UNDEFINED*
472  * [8] | RW | 0x0 | Main PLL RF Slip
473  * [9] | RW | 0x0 | Peripheral PLL RF Slip
474  * [10] | RW | 0x0 | Main PLL FB Slip
475  * [11] | RW | 0x0 | Peripheral PLL FB Slip
476  * [31:12] | ??? | 0x0 | *UNDEFINED*
477  *
478  */
479 /*
480  * Field : Main PLL Achieved Lock - mainpllachieved
481  *
482  * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
483  * If 0, the Main PLL has not achieved lock since this bit was cleared.
484  *
485  * Field Access Macros:
486  *
487  */
488 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field. */
489 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_LSB 0
490 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field. */
491 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_MSB 0
492 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field. */
493 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_WIDTH 1
494 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field value. */
495 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_SET_MSK 0x00000001
496 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field value. */
497 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
498 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field. */
499 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_RESET 0x0
500 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED field value from a register. */
501 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
502 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED register field value suitable for setting the register. */
503 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
504 
505 /*
506  * Field : Peripheral PLL Achieved Lock - perpllachieved
507  *
508  * If 1, the Peripheral PLL has achieved lock at least once since this bit was
509  * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
510  * cleared.
511  *
512  * Field Access Macros:
513  *
514  */
515 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field. */
516 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_LSB 1
517 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field. */
518 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_MSB 1
519 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field. */
520 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_WIDTH 1
521 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field value. */
522 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_SET_MSK 0x00000002
523 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field value. */
524 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_CLR_MSK 0xfffffffd
525 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field. */
526 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_RESET 0x0
527 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED field value from a register. */
528 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
529 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED register field value suitable for setting the register. */
530 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
531 
532 /*
533  * Field : Main PLL Lost Lock - mainplllost
534  *
535  * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
536  * the Main PLL has not lost lock since this bit was cleared.
537  *
538  * Field Access Macros:
539  *
540  */
541 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field. */
542 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_LSB 2
543 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field. */
544 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_MSB 2
545 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field. */
546 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_WIDTH 1
547 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field value. */
548 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_SET_MSK 0x00000004
549 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field value. */
550 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_CLR_MSK 0xfffffffb
551 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field. */
552 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_RESET 0x0
553 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST field value from a register. */
554 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
555 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST register field value suitable for setting the register. */
556 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
557 
558 /*
559  * Field : Peripheral PLL Lost Lock - perplllost
560  *
561  * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
562  * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
563  *
564  * Field Access Macros:
565  *
566  */
567 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field. */
568 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_LSB 3
569 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field. */
570 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_MSB 3
571 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field. */
572 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_WIDTH 1
573 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field value. */
574 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_SET_MSK 0x00000008
575 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field value. */
576 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_CLR_MSK 0xfffffff7
577 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field. */
578 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_RESET 0x0
579 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST field value from a register. */
580 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
581 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST register field value suitable for setting the register. */
582 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
583 
584 /*
585  * Field : Main PLL RF Slip - mainpllrfslip
586  *
587  * If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).
588  * This does not mean the PLL has lost lock, but the quality of the clock has
589  * degraded.
590  *
591  * Field Access Macros:
592  *
593  */
594 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field. */
595 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_LSB 8
596 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field. */
597 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_MSB 8
598 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field. */
599 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_WIDTH 1
600 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field value. */
601 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_SET_MSK 0x00000100
602 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field value. */
603 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
604 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field. */
605 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_RESET 0x0
606 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP field value from a register. */
607 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
608 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP register field value suitable for setting the register. */
609 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
610 
611 /*
612  * Field : Peripheral PLL RF Slip - perpllrfslip
613  *
614  * If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too
615  * high). This does not mean the PLL has lost lock, but the quality of the clock
616  * has degraded.
617  *
618  * Field Access Macros:
619  *
620  */
621 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field. */
622 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_LSB 9
623 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field. */
624 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_MSB 9
625 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field. */
626 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_WIDTH 1
627 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field value. */
628 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_SET_MSK 0x00000200
629 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field value. */
630 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_CLR_MSK 0xfffffdff
631 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field. */
632 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_RESET 0x0
633 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP field value from a register. */
634 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
635 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP register field value suitable for setting the register. */
636 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
637 
638 /*
639  * Field : Main PLL FB Slip - mainpllfbslip
640  *
641  * If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low). This
642  * does not mean the PLL has lost lock, but the quality of the clock has degraded.
643  *
644  * Field Access Macros:
645  *
646  */
647 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field. */
648 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_LSB 10
649 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field. */
650 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_MSB 10
651 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field. */
652 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_WIDTH 1
653 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field value. */
654 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_SET_MSK 0x00000400
655 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field value. */
656 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
657 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field. */
658 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_RESET 0x0
659 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP field value from a register. */
660 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
661 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP register field value suitable for setting the register. */
662 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
663 
664 /*
665  * Field : Peripheral PLL FB Slip - perpllfbslip
666  *
667  * If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).
668  * This does not mean the PLL has lost lock, but the quality of the clock has
669  * degraded.
670  *
671  * Field Access Macros:
672  *
673  */
674 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field. */
675 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_LSB 11
676 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field. */
677 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_MSB 11
678 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field. */
679 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_WIDTH 1
680 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field value. */
681 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_SET_MSK 0x00000800
682 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field value. */
683 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
684 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field. */
685 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_RESET 0x0
686 /* Extracts the ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP field value from a register. */
687 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
688 /* Produces a ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP register field value suitable for setting the register. */
689 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
690 
691 #ifndef __ASSEMBLY__
692 /*
693  * WARNING: The C register and register group struct declarations are provided for
694  * convenience and illustrative purposes. They should, however, be used with
695  * caution as the C language standard provides no guarantees about the alignment or
696  * atomicity of device memory accesses. The recommended practice for writing
697  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
698  * alt_write_word() functions.
699  *
700  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTRS.
701  */
702 struct ALT_CLKMGR_CLKMGR_INTRS_s
703 {
704  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */
705  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */
706  uint32_t mainplllost : 1; /* Main PLL Lost Lock */
707  uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */
708  uint32_t : 4; /* *UNDEFINED* */
709  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip */
710  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip */
711  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip */
712  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip */
713  uint32_t : 20; /* *UNDEFINED* */
714 };
715 
716 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTRS. */
717 typedef volatile struct ALT_CLKMGR_CLKMGR_INTRS_s ALT_CLKMGR_CLKMGR_INTRS_t;
718 #endif /* __ASSEMBLY__ */
719 
720 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRS register. */
721 #define ALT_CLKMGR_CLKMGR_INTRS_RESET 0x00000000
722 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTRS register from the beginning of the component. */
723 #define ALT_CLKMGR_CLKMGR_INTRS_OFST 0x8
724 
725 /*
726  * Register : Interrupt Status Register Reset - intrr
727  *
728  * Contains fields that indicate the PLL lock status.
729  *
730  * Register Layout
731  *
732  * Bits | Access | Reset | Description
733  * :--------|:-------|:------|:-----------------------------
734  * [0] | RW | 0x0 | Main PLL Achieved Lock
735  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock
736  * [2] | RW | 0x0 | Main PLL Lost Lock
737  * [3] | RW | 0x0 | Peripheral PLL Lost Lock
738  * [7:4] | ??? | 0x0 | *UNDEFINED*
739  * [8] | RW | 0x0 | Main PLL RF Slip
740  * [9] | RW | 0x0 | Peripheral PLL RF Slip
741  * [10] | RW | 0x0 | Main PLL FB Slip
742  * [11] | RW | 0x0 | Peripheral PLL FB Slip
743  * [31:12] | ??? | 0x0 | *UNDEFINED*
744  *
745  */
746 /*
747  * Field : Main PLL Achieved Lock - mainpllachieved
748  *
749  * If 1, the Main PLL has achieved lock at least once since this bit was cleared.
750  * If 0, the Main PLL has not achieved lock since this bit was cleared.
751  *
752  * Field Access Macros:
753  *
754  */
755 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field. */
756 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_LSB 0
757 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field. */
758 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_MSB 0
759 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field. */
760 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_WIDTH 1
761 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field value. */
762 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_SET_MSK 0x00000001
763 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field value. */
764 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
765 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field. */
766 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_RESET 0x0
767 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED field value from a register. */
768 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
769 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED register field value suitable for setting the register. */
770 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
771 
772 /*
773  * Field : Peripheral PLL Achieved Lock - perpllachieved
774  *
775  * If 1, the Peripheral PLL has achieved lock at least once since this bit was
776  * cleared. If 0, the Peripheral PLL has not achieved lock since this bit was
777  * cleared.
778  *
779  * Field Access Macros:
780  *
781  */
782 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field. */
783 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_LSB 1
784 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field. */
785 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_MSB 1
786 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field. */
787 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_WIDTH 1
788 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field value. */
789 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_SET_MSK 0x00000002
790 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field value. */
791 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
792 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field. */
793 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_RESET 0x0
794 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED field value from a register. */
795 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
796 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED register field value suitable for setting the register. */
797 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
798 
799 /*
800  * Field : Main PLL Lost Lock - mainplllost
801  *
802  * If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0,
803  * the Main PLL has not lost lock since this bit was cleared.
804  *
805  * Field Access Macros:
806  *
807  */
808 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field. */
809 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_LSB 2
810 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field. */
811 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_MSB 2
812 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field. */
813 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_WIDTH 1
814 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field value. */
815 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_SET_MSK 0x00000004
816 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field value. */
817 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_CLR_MSK 0xfffffffb
818 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field. */
819 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_RESET 0x0
820 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST field value from a register. */
821 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
822 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST register field value suitable for setting the register. */
823 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
824 
825 /*
826  * Field : Peripheral PLL Lost Lock - perplllost
827  *
828  * If 1, the Peripheral PLL has lost lock at least once since this bit was cleared.
829  * If 0, the Peripheral PLL has not lost lock since this bit was cleared.
830  *
831  * Field Access Macros:
832  *
833  */
834 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field. */
835 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_LSB 3
836 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field. */
837 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_MSB 3
838 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field. */
839 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_WIDTH 1
840 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field value. */
841 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_SET_MSK 0x00000008
842 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field value. */
843 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_CLR_MSK 0xfffffff7
844 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field. */
845 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_RESET 0x0
846 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST field value from a register. */
847 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
848 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST register field value suitable for setting the register. */
849 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
850 
851 /*
852  * Field : Main PLL RF Slip - mainpllrfslip
853  *
854  * If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).
855  * This does not mean the PLL has lost lock, but the quality of the clock has
856  * degraded.
857  *
858  * Field Access Macros:
859  *
860  */
861 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field. */
862 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_LSB 8
863 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field. */
864 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_MSB 8
865 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field. */
866 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_WIDTH 1
867 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field value. */
868 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_SET_MSK 0x00000100
869 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field value. */
870 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
871 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field. */
872 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_RESET 0x0
873 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP field value from a register. */
874 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
875 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP register field value suitable for setting the register. */
876 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
877 
878 /*
879  * Field : Peripheral PLL RF Slip - perpllrfslip
880  *
881  * If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too
882  * high). This does not mean the PLL has lost lock, but the quality of the clock
883  * has degraded.
884  *
885  * Field Access Macros:
886  *
887  */
888 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field. */
889 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_LSB 9
890 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field. */
891 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_MSB 9
892 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field. */
893 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_WIDTH 1
894 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field value. */
895 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_SET_MSK 0x00000200
896 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field value. */
897 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
898 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field. */
899 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_RESET 0x0
900 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP field value from a register. */
901 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
902 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP register field value suitable for setting the register. */
903 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
904 
905 /*
906  * Field : Main PLL FB Slip - mainpllfbslip
907  *
908  * If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low). This
909  * does not mean the PLL has lost lock, but the quality of the clock has degraded.
910  *
911  * Field Access Macros:
912  *
913  */
914 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field. */
915 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_LSB 10
916 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field. */
917 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_MSB 10
918 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field. */
919 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_WIDTH 1
920 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field value. */
921 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_SET_MSK 0x00000400
922 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field value. */
923 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
924 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field. */
925 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_RESET 0x0
926 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP field value from a register. */
927 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
928 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP register field value suitable for setting the register. */
929 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
930 
931 /*
932  * Field : Peripheral PLL FB Slip - perpllfbslip
933  *
934  * If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).
935  * This does not mean the PLL has lost lock, but the quality of the clock has
936  * degraded.
937  *
938  * Field Access Macros:
939  *
940  */
941 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field. */
942 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_LSB 11
943 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field. */
944 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_MSB 11
945 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field. */
946 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_WIDTH 1
947 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field value. */
948 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_SET_MSK 0x00000800
949 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field value. */
950 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
951 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field. */
952 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_RESET 0x0
953 /* Extracts the ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP field value from a register. */
954 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
955 /* Produces a ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP register field value suitable for setting the register. */
956 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
957 
958 #ifndef __ASSEMBLY__
959 /*
960  * WARNING: The C register and register group struct declarations are provided for
961  * convenience and illustrative purposes. They should, however, be used with
962  * caution as the C language standard provides no guarantees about the alignment or
963  * atomicity of device memory accesses. The recommended practice for writing
964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
965  * alt_write_word() functions.
966  *
967  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTRR.
968  */
969 struct ALT_CLKMGR_CLKMGR_INTRR_s
970 {
971  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock */
972  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock */
973  uint32_t mainplllost : 1; /* Main PLL Lost Lock */
974  uint32_t perplllost : 1; /* Peripheral PLL Lost Lock */
975  uint32_t : 4; /* *UNDEFINED* */
976  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip */
977  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip */
978  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip */
979  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip */
980  uint32_t : 20; /* *UNDEFINED* */
981 };
982 
983 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTRR. */
984 typedef volatile struct ALT_CLKMGR_CLKMGR_INTRR_s ALT_CLKMGR_CLKMGR_INTRR_t;
985 #endif /* __ASSEMBLY__ */
986 
987 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRR register. */
988 #define ALT_CLKMGR_CLKMGR_INTRR_RESET 0x00000000
989 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTRR register from the beginning of the component. */
990 #define ALT_CLKMGR_CLKMGR_INTRR_OFST 0xc
991 
992 /*
993  * Register : Interrupt Enable Register - intren
994  *
995  * Contain fields that enable the interrupt
996  *
997  * Register Layout
998  *
999  * Bits | Access | Reset | Description
1000  * :--------|:-------|:------|:----------------------------------------------
1001  * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1002  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1003  * [2] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1004  * [3] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1005  * [7:4] | ??? | 0x0 | *UNDEFINED*
1006  * [8] | RW | 0x0 | Main PLL RF Slip Interrupt Enable
1007  * [9] | RW | 0x0 | Peripheral PLL RF Slip Interrupt Enable
1008  * [10] | RW | 0x0 | Main PLL FB Slip Interrupt Enable
1009  * [11] | RW | 0x0 | Peripheral PLL FB Slip Interrupt Enable
1010  * [31:12] | ??? | 0x0 | *UNDEFINED*
1011  *
1012  */
1013 /*
1014  * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
1015  *
1016  * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
1017  * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into
1018  * the Clock Manager interrupt output.
1019  *
1020  * Field Access Macros:
1021  *
1022  */
1023 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
1024 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
1025 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
1026 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
1027 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
1028 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
1029 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
1030 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
1031 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field value. */
1032 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1033 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field. */
1034 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
1035 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED field value from a register. */
1036 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1037 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED register field value suitable for setting the register. */
1038 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1039 
1040 /*
1041  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
1042  *
1043  * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
1044  * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is
1045  * not ORed into the Clock Manager interrupt output.
1046  *
1047  * Field Access Macros:
1048  *
1049  */
1050 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field. */
1051 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
1052 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field. */
1053 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
1054 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field. */
1055 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
1056 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
1057 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
1058 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field value. */
1059 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1060 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field. */
1061 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
1062 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED field value from a register. */
1063 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1064 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED register field value suitable for setting the register. */
1065 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1066 
1067 /*
1068  * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
1069  *
1070  * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
1071  * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the
1072  * Clock Manager interrupt output.
1073  *
1074  * Field Access Macros:
1075  *
1076  */
1077 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field. */
1078 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_LSB 2
1079 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field. */
1080 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_MSB 2
1081 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field. */
1082 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
1083 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field value. */
1084 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000004
1085 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field value. */
1086 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffffb
1087 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field. */
1088 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
1089 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST field value from a register. */
1090 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1091 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST register field value suitable for setting the register. */
1092 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1093 
1094 /*
1095  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
1096  *
1097  * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
1098  * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed
1099  * into the Clock Manager interrupt output.
1100  *
1101  * Field Access Macros:
1102  *
1103  */
1104 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field. */
1105 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_LSB 3
1106 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field. */
1107 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_MSB 3
1108 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field. */
1109 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
1110 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field value. */
1111 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000008
1112 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field value. */
1113 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xfffffff7
1114 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field. */
1115 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
1116 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST field value from a register. */
1117 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1118 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST register field value suitable for setting the register. */
1119 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1120 
1121 /*
1122  * Field : Main PLL RF Slip Interrupt Enable - mainpllrfslip
1123  *
1124  * When set to 1,the Main PLL reference cycle slipped bit is ORed into the Clock
1125  * Manager interrupt output. When set to 0, the Main PLL reference cylce slipped
1126  * bit is Ored into the Clock Manager interrupt output.
1127  *
1128  * Field Access Macros:
1129  *
1130  */
1131 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field. */
1132 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_LSB 8
1133 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field. */
1134 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_MSB 8
1135 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field. */
1136 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_WIDTH 1
1137 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field value. */
1138 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_SET_MSK 0x00000100
1139 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field value. */
1140 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1141 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field. */
1142 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_RESET 0x0
1143 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP field value from a register. */
1144 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1145 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP register field value suitable for setting the register. */
1146 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1147 
1148 /*
1149  * Field : Peripheral PLL RF Slip Interrupt Enable - perpllrfslip
1150  *
1151  * When set to 1,the Peripheral PLL reference cycle slipped bit is ORed into the
1152  * Clock Manager interrupt output. When set to 0, the Peripheral PLL reference
1153  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1154  *
1155  * Field Access Macros:
1156  *
1157  */
1158 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field. */
1159 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_LSB 9
1160 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field. */
1161 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_MSB 9
1162 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field. */
1163 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_WIDTH 1
1164 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field value. */
1165 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_SET_MSK 0x00000200
1166 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field value. */
1167 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1168 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field. */
1169 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_RESET 0x0
1170 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP field value from a register. */
1171 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1172 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP register field value suitable for setting the register. */
1173 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1174 
1175 /*
1176  * Field : Main PLL FB Slip Interrupt Enable - mainpllfbslip
1177  *
1178  * When set to 1,the Main PLL feedback cycle slipped bit is ORed into the Clock
1179  * Manager interrupt output. When set to 0, the Main PLL feedback cylce slipped
1180  * bit is Ored into the Clock Manager interrupt output.
1181  *
1182  * Field Access Macros:
1183  *
1184  */
1185 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field. */
1186 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_LSB 10
1187 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field. */
1188 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_MSB 10
1189 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field. */
1190 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_WIDTH 1
1191 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field value. */
1192 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_SET_MSK 0x00000400
1193 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field value. */
1194 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1195 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field. */
1196 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_RESET 0x0
1197 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP field value from a register. */
1198 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1199 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP register field value suitable for setting the register. */
1200 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1201 
1202 /*
1203  * Field : Peripheral PLL FB Slip Interrupt Enable - perpllfbslip
1204  *
1205  * When set to 1,the Peripheral PLL feedback cycle slipped bit is ORed into the
1206  * Clock Manager interrupt output. When set to 0, the Peripheral PLL feedback
1207  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1208  *
1209  * Field Access Macros:
1210  *
1211  */
1212 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field. */
1213 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_LSB 11
1214 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field. */
1215 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_MSB 11
1216 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field. */
1217 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_WIDTH 1
1218 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field value. */
1219 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_SET_MSK 0x00000800
1220 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field value. */
1221 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1222 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field. */
1223 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_RESET 0x0
1224 /* Extracts the ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP field value from a register. */
1225 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1226 /* Produces a ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP register field value suitable for setting the register. */
1227 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1228 
1229 #ifndef __ASSEMBLY__
1230 /*
1231  * WARNING: The C register and register group struct declarations are provided for
1232  * convenience and illustrative purposes. They should, however, be used with
1233  * caution as the C language standard provides no guarantees about the alignment or
1234  * atomicity of device memory accesses. The recommended practice for writing
1235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1236  * alt_write_word() functions.
1237  *
1238  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTREN.
1239  */
1240 struct ALT_CLKMGR_CLKMGR_INTREN_s
1241 {
1242  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */
1243  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1244  uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */
1245  uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1246  uint32_t : 4; /* *UNDEFINED* */
1247  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip Interrupt Enable */
1248  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip Interrupt Enable */
1249  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip Interrupt Enable */
1250  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip Interrupt Enable */
1251  uint32_t : 20; /* *UNDEFINED* */
1252 };
1253 
1254 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTREN. */
1255 typedef volatile struct ALT_CLKMGR_CLKMGR_INTREN_s ALT_CLKMGR_CLKMGR_INTREN_t;
1256 #endif /* __ASSEMBLY__ */
1257 
1258 /* The reset value of the ALT_CLKMGR_CLKMGR_INTREN register. */
1259 #define ALT_CLKMGR_CLKMGR_INTREN_RESET 0x00000000
1260 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTREN register from the beginning of the component. */
1261 #define ALT_CLKMGR_CLKMGR_INTREN_OFST 0x10
1262 
1263 /*
1264  * Register : Interrupt Enable Register Set - intrens
1265  *
1266  * Contain fields that enable the interrupt
1267  *
1268  * Register Layout
1269  *
1270  * Bits | Access | Reset | Description
1271  * :--------|:-------|:------|:----------------------------------------------
1272  * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1273  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1274  * [2] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1275  * [3] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1276  * [7:4] | ??? | 0x0 | *UNDEFINED*
1277  * [8] | RW | 0x0 | Main PLL RF Slip Interrupt Enable
1278  * [9] | RW | 0x0 | Peripheral PLL RF Slip Interrupt Enable
1279  * [10] | RW | 0x0 | Main PLL FB Slip Interrupt Enable
1280  * [11] | RW | 0x0 | Peripheral PLL FB Slip Interrupt Enable
1281  * [31:12] | ??? | 0x0 | *UNDEFINED*
1282  *
1283  */
1284 /*
1285  * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
1286  *
1287  * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
1288  * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into
1289  * the Clock Manager interrupt output.
1290  *
1291  * Field Access Macros:
1292  *
1293  */
1294 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field. */
1295 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_LSB 0
1296 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field. */
1297 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_MSB 0
1298 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field. */
1299 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_WIDTH 1
1300 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field value. */
1301 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_SET_MSK 0x00000001
1302 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field value. */
1303 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1304 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field. */
1305 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_RESET 0x0
1306 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED field value from a register. */
1307 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1308 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED register field value suitable for setting the register. */
1309 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1310 
1311 /*
1312  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
1313  *
1314  * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
1315  * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is
1316  * not ORed into the Clock Manager interrupt output.
1317  *
1318  * Field Access Macros:
1319  *
1320  */
1321 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field. */
1322 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_LSB 1
1323 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field. */
1324 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_MSB 1
1325 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field. */
1326 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_WIDTH 1
1327 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field value. */
1328 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_SET_MSK 0x00000002
1329 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field value. */
1330 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1331 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field. */
1332 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_RESET 0x0
1333 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED field value from a register. */
1334 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1335 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED register field value suitable for setting the register. */
1336 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1337 
1338 /*
1339  * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
1340  *
1341  * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
1342  * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the
1343  * Clock Manager interrupt output.
1344  *
1345  * Field Access Macros:
1346  *
1347  */
1348 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field. */
1349 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_LSB 2
1350 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field. */
1351 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_MSB 2
1352 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field. */
1353 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_WIDTH 1
1354 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field value. */
1355 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_SET_MSK 0x00000004
1356 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field value. */
1357 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_CLR_MSK 0xfffffffb
1358 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field. */
1359 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_RESET 0x0
1360 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST field value from a register. */
1361 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1362 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST register field value suitable for setting the register. */
1363 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1364 
1365 /*
1366  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
1367  *
1368  * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
1369  * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed
1370  * into the Clock Manager interrupt output.
1371  *
1372  * Field Access Macros:
1373  *
1374  */
1375 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field. */
1376 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_LSB 3
1377 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field. */
1378 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_MSB 3
1379 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field. */
1380 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_WIDTH 1
1381 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field value. */
1382 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_SET_MSK 0x00000008
1383 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field value. */
1384 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_CLR_MSK 0xfffffff7
1385 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field. */
1386 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_RESET 0x0
1387 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST field value from a register. */
1388 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1389 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST register field value suitable for setting the register. */
1390 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1391 
1392 /*
1393  * Field : Main PLL RF Slip Interrupt Enable - mainpllrfslip
1394  *
1395  * When set to 1,the Main PLL reference cycle slipped bit is ORed into the Clock
1396  * Manager interrupt output. When set to 0, the Main PLL reference cylce slipped
1397  * bit is Ored into the Clock Manager interrupt output.
1398  *
1399  * Field Access Macros:
1400  *
1401  */
1402 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field. */
1403 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_LSB 8
1404 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field. */
1405 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_MSB 8
1406 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field. */
1407 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_WIDTH 1
1408 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field value. */
1409 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_SET_MSK 0x00000100
1410 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field value. */
1411 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1412 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field. */
1413 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_RESET 0x0
1414 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP field value from a register. */
1415 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1416 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP register field value suitable for setting the register. */
1417 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1418 
1419 /*
1420  * Field : Peripheral PLL RF Slip Interrupt Enable - perpllrfslip
1421  *
1422  * When set to 1,the Peripheral PLL reference cycle slipped bit is ORed into the
1423  * Clock Manager interrupt output. When set to 0, the Peripheral PLL reference
1424  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1425  *
1426  * Field Access Macros:
1427  *
1428  */
1429 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field. */
1430 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_LSB 9
1431 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field. */
1432 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_MSB 9
1433 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field. */
1434 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_WIDTH 1
1435 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field value. */
1436 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_SET_MSK 0x00000200
1437 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field value. */
1438 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1439 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field. */
1440 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_RESET 0x0
1441 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP field value from a register. */
1442 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1443 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP register field value suitable for setting the register. */
1444 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1445 
1446 /*
1447  * Field : Main PLL FB Slip Interrupt Enable - mainpllfbslip
1448  *
1449  * When set to 1,the Main PLL feedback cycle slipped bit is ORed into the Clock
1450  * Manager interrupt output. When set to 0, the Main PLL feedback cylce slipped
1451  * bit is Ored into the Clock Manager interrupt output.
1452  *
1453  * Field Access Macros:
1454  *
1455  */
1456 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field. */
1457 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_LSB 10
1458 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field. */
1459 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_MSB 10
1460 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field. */
1461 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_WIDTH 1
1462 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field value. */
1463 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_SET_MSK 0x00000400
1464 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field value. */
1465 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1466 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field. */
1467 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_RESET 0x0
1468 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP field value from a register. */
1469 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1470 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP register field value suitable for setting the register. */
1471 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1472 
1473 /*
1474  * Field : Peripheral PLL FB Slip Interrupt Enable - perpllfbslip
1475  *
1476  * When set to 1,the Peripheral PLL feedback cycle slipped bit is ORed into the
1477  * Clock Manager interrupt output. When set to 0, the Peripheral PLL feedback
1478  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1479  *
1480  * Field Access Macros:
1481  *
1482  */
1483 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field. */
1484 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_LSB 11
1485 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field. */
1486 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_MSB 11
1487 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field. */
1488 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_WIDTH 1
1489 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field value. */
1490 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_SET_MSK 0x00000800
1491 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field value. */
1492 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1493 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field. */
1494 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_RESET 0x0
1495 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP field value from a register. */
1496 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1497 /* Produces a ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP register field value suitable for setting the register. */
1498 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1499 
1500 #ifndef __ASSEMBLY__
1501 /*
1502  * WARNING: The C register and register group struct declarations are provided for
1503  * convenience and illustrative purposes. They should, however, be used with
1504  * caution as the C language standard provides no guarantees about the alignment or
1505  * atomicity of device memory accesses. The recommended practice for writing
1506  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1507  * alt_write_word() functions.
1508  *
1509  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTRENS.
1510  */
1511 struct ALT_CLKMGR_CLKMGR_INTRENS_s
1512 {
1513  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */
1514  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1515  uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */
1516  uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1517  uint32_t : 4; /* *UNDEFINED* */
1518  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip Interrupt Enable */
1519  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip Interrupt Enable */
1520  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip Interrupt Enable */
1521  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip Interrupt Enable */
1522  uint32_t : 20; /* *UNDEFINED* */
1523 };
1524 
1525 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTRENS. */
1526 typedef volatile struct ALT_CLKMGR_CLKMGR_INTRENS_s ALT_CLKMGR_CLKMGR_INTRENS_t;
1527 #endif /* __ASSEMBLY__ */
1528 
1529 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENS register. */
1530 #define ALT_CLKMGR_CLKMGR_INTRENS_RESET 0x00000000
1531 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTRENS register from the beginning of the component. */
1532 #define ALT_CLKMGR_CLKMGR_INTRENS_OFST 0x14
1533 
1534 /*
1535  * Register : Interrupt Enable Register Reset - intrenr
1536  *
1537  * Contain fields that enable the interrupt
1538  *
1539  * Register Layout
1540  *
1541  * Bits | Access | Reset | Description
1542  * :--------|:-------|:------|:----------------------------------------------
1543  * [0] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1544  * [1] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1545  * [2] | RW | 0x0 | Main PLL Achieved Lock Interrupt Enable
1546  * [3] | RW | 0x0 | Peripheral PLL Achieved Lock Interrupt Enable
1547  * [7:4] | ??? | 0x0 | *UNDEFINED*
1548  * [8] | RW | 0x0 | Main PLL RF Slip Interrupt Enable
1549  * [9] | RW | 0x0 | Peripheral PLL RF Slip Interrupt Enable
1550  * [10] | RW | 0x0 | Main PLL FB Slip Interrupt Enable
1551  * [11] | RW | 0x0 | Peripheral PLL FB Slip Interrupt Enable
1552  * [31:12] | ??? | 0x0 | *UNDEFINED*
1553  *
1554  */
1555 /*
1556  * Field : Main PLL Achieved Lock Interrupt Enable - mainpllachieved
1557  *
1558  * When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager
1559  * interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into
1560  * the Clock Manager interrupt output.
1561  *
1562  * Field Access Macros:
1563  *
1564  */
1565 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field. */
1566 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_LSB 0
1567 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field. */
1568 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_MSB 0
1569 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field. */
1570 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_WIDTH 1
1571 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field value. */
1572 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_SET_MSK 0x00000001
1573 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field value. */
1574 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1575 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field. */
1576 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_RESET 0x0
1577 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED field value from a register. */
1578 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1579 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED register field value suitable for setting the register. */
1580 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1581 
1582 /*
1583  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perpllachieved
1584  *
1585  * When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock
1586  * Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is
1587  * not ORed into the Clock Manager interrupt output.
1588  *
1589  * Field Access Macros:
1590  *
1591  */
1592 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field. */
1593 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_LSB 1
1594 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field. */
1595 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_MSB 1
1596 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field. */
1597 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_WIDTH 1
1598 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field value. */
1599 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_SET_MSK 0x00000002
1600 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field value. */
1601 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1602 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field. */
1603 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_RESET 0x0
1604 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED field value from a register. */
1605 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1606 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED register field value suitable for setting the register. */
1607 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1608 
1609 /*
1610  * Field : Main PLL Achieved Lock Interrupt Enable - mainplllost
1611  *
1612  * When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager
1613  * interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the
1614  * Clock Manager interrupt output.
1615  *
1616  * Field Access Macros:
1617  *
1618  */
1619 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field. */
1620 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_LSB 2
1621 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field. */
1622 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_MSB 2
1623 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field. */
1624 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_WIDTH 1
1625 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field value. */
1626 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_SET_MSK 0x00000004
1627 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field value. */
1628 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_CLR_MSK 0xfffffffb
1629 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field. */
1630 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_RESET 0x0
1631 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST field value from a register. */
1632 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1633 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST register field value suitable for setting the register. */
1634 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1635 
1636 /*
1637  * Field : Peripheral PLL Achieved Lock Interrupt Enable - perplllost
1638  *
1639  * When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager
1640  * interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed
1641  * into the Clock Manager interrupt output.
1642  *
1643  * Field Access Macros:
1644  *
1645  */
1646 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field. */
1647 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_LSB 3
1648 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field. */
1649 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_MSB 3
1650 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field. */
1651 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_WIDTH 1
1652 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field value. */
1653 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_SET_MSK 0x00000008
1654 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field value. */
1655 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_CLR_MSK 0xfffffff7
1656 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field. */
1657 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_RESET 0x0
1658 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST field value from a register. */
1659 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1660 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST register field value suitable for setting the register. */
1661 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1662 
1663 /*
1664  * Field : Main PLL RF Slip Interrupt Enable - mainpllrfslip
1665  *
1666  * When set to 1,the Main PLL reference cycle slipped bit is ORed into the Clock
1667  * Manager interrupt output. When set to 0, the Main PLL reference cylce slipped
1668  * bit is Ored into the Clock Manager interrupt output.
1669  *
1670  * Field Access Macros:
1671  *
1672  */
1673 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field. */
1674 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_LSB 8
1675 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field. */
1676 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_MSB 8
1677 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field. */
1678 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_WIDTH 1
1679 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field value. */
1680 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_SET_MSK 0x00000100
1681 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field value. */
1682 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1683 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field. */
1684 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_RESET 0x0
1685 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP field value from a register. */
1686 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1687 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP register field value suitable for setting the register. */
1688 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1689 
1690 /*
1691  * Field : Peripheral PLL RF Slip Interrupt Enable - perpllrfslip
1692  *
1693  * When set to 1,the Peripheral PLL reference cycle slipped bit is ORed into the
1694  * Clock Manager interrupt output. When set to 0, the Peripheral PLL reference
1695  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1696  *
1697  * Field Access Macros:
1698  *
1699  */
1700 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field. */
1701 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_LSB 9
1702 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field. */
1703 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_MSB 9
1704 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field. */
1705 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_WIDTH 1
1706 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field value. */
1707 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_SET_MSK 0x00000200
1708 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field value. */
1709 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1710 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field. */
1711 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_RESET 0x0
1712 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP field value from a register. */
1713 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1714 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP register field value suitable for setting the register. */
1715 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1716 
1717 /*
1718  * Field : Main PLL FB Slip Interrupt Enable - mainpllfbslip
1719  *
1720  * When set to 1,the Main PLL feedback cycle slipped bit is ORed into the Clock
1721  * Manager interrupt output. When set to 0, the Main PLL feedback cylce slipped
1722  * bit is Ored into the Clock Manager interrupt output.
1723  *
1724  * Field Access Macros:
1725  *
1726  */
1727 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field. */
1728 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_LSB 10
1729 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field. */
1730 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_MSB 10
1731 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field. */
1732 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_WIDTH 1
1733 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field value. */
1734 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_SET_MSK 0x00000400
1735 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field value. */
1736 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1737 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field. */
1738 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_RESET 0x0
1739 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP field value from a register. */
1740 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1741 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP register field value suitable for setting the register. */
1742 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1743 
1744 /*
1745  * Field : Peripheral PLL FB Slip Interrupt Enable - perpllfbslip
1746  *
1747  * When set to 1,the Peripheral PLL feedback cycle slipped bit is ORed into the
1748  * Clock Manager interrupt output. When set to 0, the Peripheral PLL feedback
1749  * cylce slipped bit is Ored into the Clock Manager interrupt output.
1750  *
1751  * Field Access Macros:
1752  *
1753  */
1754 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field. */
1755 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_LSB 11
1756 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field. */
1757 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_MSB 11
1758 /* The width in bits of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field. */
1759 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_WIDTH 1
1760 /* The mask used to set the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field value. */
1761 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_SET_MSK 0x00000800
1762 /* The mask used to clear the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field value. */
1763 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1764 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field. */
1765 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_RESET 0x0
1766 /* Extracts the ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP field value from a register. */
1767 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1768 /* Produces a ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP register field value suitable for setting the register. */
1769 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1770 
1771 #ifndef __ASSEMBLY__
1772 /*
1773  * WARNING: The C register and register group struct declarations are provided for
1774  * convenience and illustrative purposes. They should, however, be used with
1775  * caution as the C language standard provides no guarantees about the alignment or
1776  * atomicity of device memory accesses. The recommended practice for writing
1777  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1778  * alt_write_word() functions.
1779  *
1780  * The struct declaration for register ALT_CLKMGR_CLKMGR_INTRENR.
1781  */
1782 struct ALT_CLKMGR_CLKMGR_INTRENR_s
1783 {
1784  uint32_t mainpllachieved : 1; /* Main PLL Achieved Lock Interrupt Enable */
1785  uint32_t perpllachieved : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1786  uint32_t mainplllost : 1; /* Main PLL Achieved Lock Interrupt Enable */
1787  uint32_t perplllost : 1; /* Peripheral PLL Achieved Lock Interrupt Enable */
1788  uint32_t : 4; /* *UNDEFINED* */
1789  uint32_t mainpllrfslip : 1; /* Main PLL RF Slip Interrupt Enable */
1790  uint32_t perpllrfslip : 1; /* Peripheral PLL RF Slip Interrupt Enable */
1791  uint32_t mainpllfbslip : 1; /* Main PLL FB Slip Interrupt Enable */
1792  uint32_t perpllfbslip : 1; /* Peripheral PLL FB Slip Interrupt Enable */
1793  uint32_t : 20; /* *UNDEFINED* */
1794 };
1795 
1796 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_INTRENR. */
1797 typedef volatile struct ALT_CLKMGR_CLKMGR_INTRENR_s ALT_CLKMGR_CLKMGR_INTRENR_t;
1798 #endif /* __ASSEMBLY__ */
1799 
1800 /* The reset value of the ALT_CLKMGR_CLKMGR_INTRENR register. */
1801 #define ALT_CLKMGR_CLKMGR_INTRENR_RESET 0x00000000
1802 /* The byte offset of the ALT_CLKMGR_CLKMGR_INTRENR register from the beginning of the component. */
1803 #define ALT_CLKMGR_CLKMGR_INTRENR_OFST 0x18
1804 
1805 /*
1806  * Register : Status Register - stat
1807  *
1808  * Provides status for Clock Manager including PLL lock and HW Managed Clock State
1809  * Machine busy.
1810  *
1811  * Register Layout
1812  *
1813  * Bits | Access | Reset | Description
1814  * :--------|:-------|:------|:-----------------------------------
1815  * [0] | R | 0x0 | HW Managed Clocks BUSY
1816  * [7:1] | ??? | 0x0 | *UNDEFINED*
1817  * [8] | R | 0x0 | Main PLL Current Lock Status
1818  * [9] | R | 0x0 | Peripheral PLL Current Lock Status
1819  * [15:10] | ??? | 0x0 | *UNDEFINED*
1820  * [16] | R | 0x1 | Boot Mode Status
1821  * [17] | R | 0x0 | Boot Clock Source Status
1822  * [31:18] | ??? | 0x0 | *UNDEFINED*
1823  *
1824  */
1825 /*
1826  * Field : HW Managed Clocks BUSY - busy
1827  *
1828  * This read only bit indicates that the Hardware Managed clock's state machine is
1829  * active. If the state machine is active, then the clocks are in transition.
1830  * Software should poll this bit after changing the source of internal clocks when
1831  * changing the state of CTRL.BOOTMODE, MAINPLLGRP.BYPASS.MPU or
1832  * MAINPLLGRP.BYPASS.NOC register bits. Immediately following writes to any of
1833  * these registers, SW should wait 0.5 usecs and then poll this BUSY bit until it
1834  * is IDLE before proceeding with any other register writes in the Clock Manager.
1835  *
1836  * The reset value of this bit is applied on a cold reset; warm reset has no affect
1837  * on this bit.
1838  *
1839  * Field Enumeration Values:
1840  *
1841  * Enum | Value | Description
1842  * :-----------------------------------|:------|:---------------------
1843  * ALT_CLKMGR_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable
1844  * ALT_CLKMGR_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition
1845  *
1846  * Field Access Macros:
1847  *
1848  */
1849 /*
1850  * Enumerated value for register field ALT_CLKMGR_CLKMGR_STAT_BUSY
1851  *
1852  * Clocks stable
1853  */
1854 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_E_IDLE 0x0
1855 /*
1856  * Enumerated value for register field ALT_CLKMGR_CLKMGR_STAT_BUSY
1857  *
1858  * Clocks in transition
1859  */
1860 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_E_BUSY 0x1
1861 
1862 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_STAT_BUSY register field. */
1863 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_LSB 0
1864 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_STAT_BUSY register field. */
1865 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_MSB 0
1866 /* The width in bits of the ALT_CLKMGR_CLKMGR_STAT_BUSY register field. */
1867 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_WIDTH 1
1868 /* The mask used to set the ALT_CLKMGR_CLKMGR_STAT_BUSY register field value. */
1869 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1870 /* The mask used to clear the ALT_CLKMGR_CLKMGR_STAT_BUSY register field value. */
1871 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1872 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT_BUSY register field. */
1873 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_RESET 0x0
1874 /* Extracts the ALT_CLKMGR_CLKMGR_STAT_BUSY field value from a register. */
1875 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1876 /* Produces a ALT_CLKMGR_CLKMGR_STAT_BUSY register field value suitable for setting the register. */
1877 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1878 
1879 /*
1880  * Field : Main PLL Current Lock Status - mainplllocked
1881  *
1882  * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not
1883  * locked.
1884  *
1885  * Field Access Macros:
1886  *
1887  */
1888 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field. */
1889 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_LSB 8
1890 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field. */
1891 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_MSB 8
1892 /* The width in bits of the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field. */
1893 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_WIDTH 1
1894 /* The mask used to set the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field value. */
1895 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100
1896 /* The mask used to clear the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field value. */
1897 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_CLR_MSK 0xfffffeff
1898 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field. */
1899 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_RESET 0x0
1900 /* Extracts the ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED field value from a register. */
1901 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
1902 /* Produces a ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED register field value suitable for setting the register. */
1903 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
1904 
1905 /*
1906  * Field : Peripheral PLL Current Lock Status - perplllocked
1907  *
1908  * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is
1909  * currently not locked.
1910  *
1911  * Field Access Macros:
1912  *
1913  */
1914 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field. */
1915 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_LSB 9
1916 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field. */
1917 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_MSB 9
1918 /* The width in bits of the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field. */
1919 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_WIDTH 1
1920 /* The mask used to set the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field value. */
1921 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200
1922 /* The mask used to clear the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field value. */
1923 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_CLR_MSK 0xfffffdff
1924 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field. */
1925 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_RESET 0x0
1926 /* Extracts the ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED field value from a register. */
1927 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_GET(value) (((value) & 0x00000200) >> 9)
1928 /* Produces a ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED register field value suitable for setting the register. */
1929 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET(value) (((value) << 9) & 0x00000200)
1930 
1931 /*
1932  * Field : Boot Mode Status - bootmode
1933  *
1934  * If 1, the clocks are currently in Boot Mode. If 0, the clocks are not in Boot
1935  * Mode.
1936  *
1937  * This is a read only status. For SW to exit Boot Mode, SW must clear the RW bit
1938  * CTRL.BOOTMODE.
1939  *
1940  * Field Access Macros:
1941  *
1942  */
1943 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field. */
1944 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_LSB 16
1945 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field. */
1946 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_MSB 16
1947 /* The width in bits of the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field. */
1948 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_WIDTH 1
1949 /* The mask used to set the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field value. */
1950 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_SET_MSK 0x00010000
1951 /* The mask used to clear the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field value. */
1952 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_CLR_MSK 0xfffeffff
1953 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field. */
1954 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_RESET 0x1
1955 /* Extracts the ALT_CLKMGR_CLKMGR_STAT_BOOTMOD field value from a register. */
1956 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_GET(value) (((value) & 0x00010000) >> 16)
1957 /* Produces a ALT_CLKMGR_CLKMGR_STAT_BOOTMOD register field value suitable for setting the register. */
1958 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_SET(value) (((value) << 16) & 0x00010000)
1959 
1960 /*
1961  * Field : Boot Clock Source Status - bootclksrc
1962  *
1963  * If 1, the source of boot_clk is cb_intosc_hs_div2_clk. . If 0, the boot_clk
1964  * source is the external oscillator (EOSC1).
1965  *
1966  * This is a read only status.
1967  *
1968  * Field Access Macros:
1969  *
1970  */
1971 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field. */
1972 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_LSB 17
1973 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field. */
1974 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_MSB 17
1975 /* The width in bits of the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field. */
1976 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_WIDTH 1
1977 /* The mask used to set the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field value. */
1978 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000
1979 /* The mask used to clear the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field value. */
1980 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_CLR_MSK 0xfffdffff
1981 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field. */
1982 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_RESET 0x0
1983 /* Extracts the ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC field value from a register. */
1984 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_GET(value) (((value) & 0x00020000) >> 17)
1985 /* Produces a ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC register field value suitable for setting the register. */
1986 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET(value) (((value) << 17) & 0x00020000)
1987 
1988 #ifndef __ASSEMBLY__
1989 /*
1990  * WARNING: The C register and register group struct declarations are provided for
1991  * convenience and illustrative purposes. They should, however, be used with
1992  * caution as the C language standard provides no guarantees about the alignment or
1993  * atomicity of device memory accesses. The recommended practice for writing
1994  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1995  * alt_write_word() functions.
1996  *
1997  * The struct declaration for register ALT_CLKMGR_CLKMGR_STAT.
1998  */
1999 struct ALT_CLKMGR_CLKMGR_STAT_s
2000 {
2001  const uint32_t busy : 1; /* HW Managed Clocks BUSY */
2002  uint32_t : 7; /* *UNDEFINED* */
2003  const uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */
2004  const uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */
2005  uint32_t : 6; /* *UNDEFINED* */
2006  const uint32_t bootmode : 1; /* Boot Mode Status */
2007  const uint32_t bootclksrc : 1; /* Boot Clock Source Status */
2008  uint32_t : 14; /* *UNDEFINED* */
2009 };
2010 
2011 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_STAT. */
2012 typedef volatile struct ALT_CLKMGR_CLKMGR_STAT_s ALT_CLKMGR_CLKMGR_STAT_t;
2013 #endif /* __ASSEMBLY__ */
2014 
2015 /* The reset value of the ALT_CLKMGR_CLKMGR_STAT register. */
2016 #define ALT_CLKMGR_CLKMGR_STAT_RESET 0x00010000
2017 /* The byte offset of the ALT_CLKMGR_CLKMGR_STAT register from the beginning of the component. */
2018 #define ALT_CLKMGR_CLKMGR_STAT_OFST 0x1c
2019 
2020 /*
2021  * Register : Test IO Control Register - testioctrl
2022  *
2023  * Contains fields setting the IO output select for Test Clock and Debug outputs.
2024  * The dedicated IO outputs includes two outputs for the Main PLL clock outputs
2025  * (PLL_CLK0 and PLL_CLK1), two outputs for the Peripheral PLL clock outputs
2026  * (PLL_CLK2 and PLL_CLK3), and one output for miscelaneous debug for the Main and
2027  * Peripheral PLL (PLL_CLK4).
2028  *
2029  * The Test Clock and Debug outputs will only propigate to the dedicated IO based
2030  * on the IO pinmux configuration. If Test Clocks are selected in the pinmux, then
2031  * the selects in this register determine which PLL clocks and PLL debug signals
2032  * will propigate to the IOs.
2033  *
2034  * Register Layout
2035  *
2036  * Bits | Access | Reset | Description
2037  * :--------|:-------|:------|:------------------------
2038  * [3:0] | RW | 0x8 | Main Clock Select
2039  * [7:4] | ??? | 0x0 | *UNDEFINED*
2040  * [11:8] | RW | 0x8 | Peripheral Clock Select
2041  * [15:12] | ??? | 0x0 | *UNDEFINED*
2042  * [20:16] | RW | 0x10 | Debug Clock Select
2043  * [31:21] | ??? | 0x0 | *UNDEFINED*
2044  *
2045  */
2046 /*
2047  * Field : Main Clock Select - mainclksel
2048  *
2049  * Selects the source of PLL_CLK0 and PLL_CLK1 dedicated IO outputs if selected.
2050  * All of the CLKOUT# counter outputs are from the Main PLL.
2051  *
2052  * The following table determines the PLL counter output select:
2053  *
2054  * sel PLL_CLK0 PLL_CLK1
2055  *
2056  * 0000 CLKOUT0 CLKOUT8
2057  *
2058  * 0001 CLKOUT1 CLKOUT9
2059  *
2060  * 0010 CLKOUT2 CLKOUT10
2061  *
2062  * 0011 CLKOUT3 CLKOUT11
2063  *
2064  * 0100 CLKOUT4 CLKOUT13
2065  *
2066  * 0101 CLKOUT5 CLKOUT14
2067  *
2068  * 0110 CLKOUT6 CLKOUT15
2069  *
2070  * 0111 CLKOUT7 CLKOUT16
2071  *
2072  * 1xxx VSS VSS
2073  *
2074  * Field Access Macros:
2075  *
2076  */
2077 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field. */
2078 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_LSB 0
2079 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field. */
2080 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_MSB 3
2081 /* The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field. */
2082 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_WIDTH 4
2083 /* The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value. */
2084 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET_MSK 0x0000000f
2085 /* The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value. */
2086 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_CLR_MSK 0xfffffff0
2087 /* The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field. */
2088 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_RESET 0x8
2089 /* Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL field value from a register. */
2090 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_GET(value) (((value) & 0x0000000f) >> 0)
2091 /* Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value suitable for setting the register. */
2092 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET(value) (((value) << 0) & 0x0000000f)
2093 
2094 /*
2095  * Field : Peripheral Clock Select - periclksel
2096  *
2097  * Selects the source of PLL_CLK2 and PLL_CLK3 dedicated IO outputs if selected.
2098  * All of the CLKOUT# counter outputs are from the Peripheral PLL.
2099  *
2100  * The following table determines the PLL counter output select:
2101  *
2102  * sel PLL_CLK2 PLL_CLK3
2103  *
2104  * 0000 CLKOUT0 CLKOUT8
2105  *
2106  * 0001 CLKOUT1 CLKOUT9
2107  *
2108  * 0010 CLKOUT2 CLKOUT10
2109  *
2110  * 0011 CLKOUT3 CLKOUT11
2111  *
2112  * 0100 CLKOUT4 CLKOUT13
2113  *
2114  * 0101 CLKOUT5 CLKOUT14
2115  *
2116  * 0110 CLKOUT6 CLKOUT15
2117  *
2118  * 0111 CLKOUT7 CLKOUT16
2119  *
2120  * 1xxx VSS VSS
2121  *
2122  * Field Access Macros:
2123  *
2124  */
2125 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field. */
2126 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_LSB 8
2127 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field. */
2128 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_MSB 11
2129 /* The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field. */
2130 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_WIDTH 4
2131 /* The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value. */
2132 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET_MSK 0x00000f00
2133 /* The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value. */
2134 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_CLR_MSK 0xfffff0ff
2135 /* The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field. */
2136 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_RESET 0x8
2137 /* Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL field value from a register. */
2138 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_GET(value) (((value) & 0x00000f00) >> 8)
2139 /* Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value suitable for setting the register. */
2140 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET(value) (((value) << 8) & 0x00000f00)
2141 
2142 /*
2143  * Field : Debug Clock Select - debugclksel
2144  *
2145  * Selects the source of PLL_CLK4 for miscellaneous PLL signals.
2146  *
2147  * Bit[3] (p below) determines if from the debug output is from the Main or
2148  * Peripheral PLL. If 0, the the output is from the Main PLL and if 1, the output
2149  * is from the Peripheral PLL.
2150  *
2151  * The following table determines the PLL debug output select:
2152  *
2153  * sel PLL_CLK4
2154  *
2155  * 0p000 OUTRESETACK0
2156  *
2157  * 0p001 OUTRESETACK3
2158  *
2159  * 0p010 OUTRESETACK7
2160  *
2161  * 0p011 PLLRESET
2162  *
2163  * 0p100 OUTRESETACK15
2164  *
2165  * 0p101 FBSLIP
2166  *
2167  * 0p110 RFSLIP
2168  *
2169  * 0p111 LOCK
2170  *
2171  * 1xxxx VSS
2172  *
2173  * Field Access Macros:
2174  *
2175  */
2176 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field. */
2177 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_LSB 16
2178 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field. */
2179 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_MSB 20
2180 /* The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field. */
2181 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_WIDTH 5
2182 /* The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value. */
2183 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET_MSK 0x001f0000
2184 /* The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value. */
2185 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_CLR_MSK 0xffe0ffff
2186 /* The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field. */
2187 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_RESET 0x10
2188 /* Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL field value from a register. */
2189 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_GET(value) (((value) & 0x001f0000) >> 16)
2190 /* Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value suitable for setting the register. */
2191 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET(value) (((value) << 16) & 0x001f0000)
2192 
2193 #ifndef __ASSEMBLY__
2194 /*
2195  * WARNING: The C register and register group struct declarations are provided for
2196  * convenience and illustrative purposes. They should, however, be used with
2197  * caution as the C language standard provides no guarantees about the alignment or
2198  * atomicity of device memory accesses. The recommended practice for writing
2199  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2200  * alt_write_word() functions.
2201  *
2202  * The struct declaration for register ALT_CLKMGR_CLKMGR_TESTIOCTL.
2203  */
2204 struct ALT_CLKMGR_CLKMGR_TESTIOCTL_s
2205 {
2206  uint32_t mainclksel : 4; /* Main Clock Select */
2207  uint32_t : 4; /* *UNDEFINED* */
2208  uint32_t periclksel : 4; /* Peripheral Clock Select */
2209  uint32_t : 4; /* *UNDEFINED* */
2210  uint32_t debugclksel : 5; /* Debug Clock Select */
2211  uint32_t : 11; /* *UNDEFINED* */
2212 };
2213 
2214 /* The typedef declaration for register ALT_CLKMGR_CLKMGR_TESTIOCTL. */
2215 typedef volatile struct ALT_CLKMGR_CLKMGR_TESTIOCTL_s ALT_CLKMGR_CLKMGR_TESTIOCTL_t;
2216 #endif /* __ASSEMBLY__ */
2217 
2218 /* The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL register. */
2219 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_RESET 0x00100808
2220 /* The byte offset of the ALT_CLKMGR_CLKMGR_TESTIOCTL register from the beginning of the component. */
2221 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_OFST 0x20
2222 
2223 #ifndef __ASSEMBLY__
2224 /*
2225  * WARNING: The C register and register group struct declarations are provided for
2226  * convenience and illustrative purposes. They should, however, be used with
2227  * caution as the C language standard provides no guarantees about the alignment or
2228  * atomicity of device memory accesses. The recommended practice for writing
2229  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2230  * alt_write_word() functions.
2231  *
2232  * The struct declaration for register group ALT_CLKMGR_CLKMGR.
2233  */
2234 struct ALT_CLKMGR_CLKMGR_s
2235 {
2236  ALT_CLKMGR_CLKMGR_CTL_t ctrl; /* ALT_CLKMGR_CLKMGR_CTL */
2237  ALT_CLKMGR_CLKMGR_INTR_t intr; /* ALT_CLKMGR_CLKMGR_INTR */
2238  ALT_CLKMGR_CLKMGR_INTRS_t intrs; /* ALT_CLKMGR_CLKMGR_INTRS */
2239  ALT_CLKMGR_CLKMGR_INTRR_t intrr; /* ALT_CLKMGR_CLKMGR_INTRR */
2240  ALT_CLKMGR_CLKMGR_INTREN_t intren; /* ALT_CLKMGR_CLKMGR_INTREN */
2241  ALT_CLKMGR_CLKMGR_INTRENS_t intrens; /* ALT_CLKMGR_CLKMGR_INTRENS */
2242  ALT_CLKMGR_CLKMGR_INTRENR_t intrenr; /* ALT_CLKMGR_CLKMGR_INTRENR */
2243  ALT_CLKMGR_CLKMGR_STAT_t stat; /* ALT_CLKMGR_CLKMGR_STAT */
2244  ALT_CLKMGR_CLKMGR_TESTIOCTL_t testioctrl; /* ALT_CLKMGR_CLKMGR_TESTIOCTL */
2245  volatile uint32_t _pad_0x24_0x40[7]; /* *UNDEFINED* */
2246 };
2247 
2248 /* The typedef declaration for register group ALT_CLKMGR_CLKMGR. */
2249 typedef volatile struct ALT_CLKMGR_CLKMGR_s ALT_CLKMGR_CLKMGR_t;
2250 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_CLKMGR. */
2251 struct ALT_CLKMGR_CLKMGR_raw_s
2252 {
2253  volatile uint32_t ctrl; /* ALT_CLKMGR_CLKMGR_CTL */
2254  volatile uint32_t intr; /* ALT_CLKMGR_CLKMGR_INTR */
2255  volatile uint32_t intrs; /* ALT_CLKMGR_CLKMGR_INTRS */
2256  volatile uint32_t intrr; /* ALT_CLKMGR_CLKMGR_INTRR */
2257  volatile uint32_t intren; /* ALT_CLKMGR_CLKMGR_INTREN */
2258  volatile uint32_t intrens; /* ALT_CLKMGR_CLKMGR_INTRENS */
2259  volatile uint32_t intrenr; /* ALT_CLKMGR_CLKMGR_INTRENR */
2260  volatile uint32_t stat; /* ALT_CLKMGR_CLKMGR_STAT */
2261  volatile uint32_t testioctrl; /* ALT_CLKMGR_CLKMGR_TESTIOCTL */
2262  uint32_t _pad_0x24_0x40[7]; /* *UNDEFINED* */
2263 };
2264 
2265 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_CLKMGR. */
2266 typedef volatile struct ALT_CLKMGR_CLKMGR_raw_s ALT_CLKMGR_CLKMGR_raw_t;
2267 #endif /* __ASSEMBLY__ */
2268 
2269 
2270 /*
2271  * Component : ALT_CLKMGR_MAINPLL
2272  *
2273  */
2274 /*
2275  * Register : Main PLL VCO Control Register 0 - vco0
2276  *
2277  * Register Layout
2278  *
2279  * Bits | Access | Reset | Description
2280  * :--------|:-------|:------|:--------------------------------
2281  * [0] | RW | 0x1 | BG PWRDN
2282  * [1] | RW | 0x1 | Power down
2283  * [2] | RW | 0x0 | Enable
2284  * [3] | RW | 0x0 | All Output Counter Reset
2285  * [4] | RW | 0x0 | External Regulator Input Select
2286  * [5] | RW | 0x0 | Fast Locking Enable
2287  * [6] | RW | 0x1 | Saturation Enable
2288  * [7] | ??? | 0x0 | *UNDEFINED*
2289  * [9:8] | RW | 0x0 | Clock Source
2290  * [15:10] | ??? | 0x0 | *UNDEFINED*
2291  * [27:16] | RW | 0x1 | Loop Bandwidth Adjust
2292  * [28] | RW | 0x0 | Loop Bandwidth Adjust Enabled
2293  * [31:29] | ??? | 0x0 | *UNDEFINED*
2294  *
2295  */
2296 /*
2297  * Field : BG PWRDN - bgpwrdn
2298  *
2299  * If '1', powers down bandgap. If '0', bandgap is not power down.
2300  *
2301  * Field Access Macros:
2302  *
2303  */
2304 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field. */
2305 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_LSB 0
2306 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field. */
2307 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_MSB 0
2308 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field. */
2309 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_WIDTH 1
2310 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value. */
2311 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
2312 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value. */
2313 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe
2314 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field. */
2315 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_RESET 0x1
2316 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN field value from a register. */
2317 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
2318 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value suitable for setting the register. */
2319 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
2320 
2321 /*
2322  * Field : Power down - pwrdn
2323  *
2324  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
2325  *
2326  * Field Access Macros:
2327  *
2328  */
2329 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field. */
2330 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_LSB 1
2331 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field. */
2332 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_MSB 1
2333 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field. */
2334 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_WIDTH 1
2335 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value. */
2336 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002
2337 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value. */
2338 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd
2339 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field. */
2340 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_RESET 0x1
2341 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_PWRDN field value from a register. */
2342 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_GET(value) (((value) & 0x00000002) >> 1)
2343 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value suitable for setting the register. */
2344 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET(value) (((value) << 1) & 0x00000002)
2345 
2346 /*
2347  * Field : Enable - en
2348  *
2349  * If '1', VCO is enabled. If '0', VCO is in reset.
2350  *
2351  * Field Access Macros:
2352  *
2353  */
2354 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_EN register field. */
2355 #define ALT_CLKMGR_MAINPLL_VCO0_EN_LSB 2
2356 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_EN register field. */
2357 #define ALT_CLKMGR_MAINPLL_VCO0_EN_MSB 2
2358 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_EN register field. */
2359 #define ALT_CLKMGR_MAINPLL_VCO0_EN_WIDTH 1
2360 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_EN register field value. */
2361 #define ALT_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004
2362 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_EN register field value. */
2363 #define ALT_CLKMGR_MAINPLL_VCO0_EN_CLR_MSK 0xfffffffb
2364 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_EN register field. */
2365 #define ALT_CLKMGR_MAINPLL_VCO0_EN_RESET 0x0
2366 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_EN field value from a register. */
2367 #define ALT_CLKMGR_MAINPLL_VCO0_EN_GET(value) (((value) & 0x00000004) >> 2)
2368 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_EN register field value suitable for setting the register. */
2369 #define ALT_CLKMGR_MAINPLL_VCO0_EN_SET(value) (((value) << 2) & 0x00000004)
2370 
2371 /*
2372  * Field : All Output Counter Reset - outresetall
2373  *
2374  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
2375  * software for correct clock operation.
2376  *
2377  * If '1', Reset phase multiplexer and all output counter state. So that after the
2378  * assertion all the clocks output are start from rising edge align.
2379  *
2380  * If '0', phase multiplexer and output counter state not reset and no change to
2381  * the phase of the clock outputs.
2382  *
2383  * Field Access Macros:
2384  *
2385  */
2386 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field. */
2387 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_LSB 3
2388 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field. */
2389 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_MSB 3
2390 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field. */
2391 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_WIDTH 1
2392 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value. */
2393 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
2394 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value. */
2395 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7
2396 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field. */
2397 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_RESET 0x0
2398 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL field value from a register. */
2399 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_GET(value) (((value) & 0x00000008) >> 3)
2400 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value suitable for setting the register. */
2401 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET(value) (((value) << 3) & 0x00000008)
2402 
2403 /*
2404  * Field : External Regulator Input Select - regextsel
2405  *
2406  * If set to '1', the external regulator is selected for the PLL.
2407  *
2408  * If set to '0', the internal regulator is slected.
2409  *
2410  * It is strongly recommended to select the external regulator while the PLL is not
2411  * enabled (in reset), and then disable the external regulater once the PLL
2412  * becomes enabled. Software should simulateously update the 'Enable' bit and the
2413  * 'External Regulator Input Select' in the same write access to the VCO register.
2414  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
2415  * set, and vice versa.
2416  *
2417  * The reset value of this bit is applied on a cold reset; warm reset has no affect
2418  * on this bit.
2419  *
2420  * Field Access Macros:
2421  *
2422  */
2423 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field. */
2424 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_LSB 4
2425 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field. */
2426 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_MSB 4
2427 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field. */
2428 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_WIDTH 1
2429 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value. */
2430 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
2431 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value. */
2432 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef
2433 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field. */
2434 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_RESET 0x0
2435 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL field value from a register. */
2436 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_GET(value) (((value) & 0x00000010) >> 4)
2437 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value suitable for setting the register. */
2438 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET(value) (((value) << 4) & 0x00000010)
2439 
2440 /*
2441  * Field : Fast Locking Enable - fasten
2442  *
2443  * Enables fast locking circuit.
2444  *
2445  * Field Access Macros:
2446  *
2447  */
2448 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field. */
2449 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_LSB 5
2450 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field. */
2451 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_MSB 5
2452 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field. */
2453 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_WIDTH 1
2454 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value. */
2455 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET_MSK 0x00000020
2456 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value. */
2457 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf
2458 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field. */
2459 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_RESET 0x0
2460 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_FASTEN field value from a register. */
2461 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_GET(value) (((value) & 0x00000020) >> 5)
2462 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value suitable for setting the register. */
2463 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET(value) (((value) << 5) & 0x00000020)
2464 
2465 /*
2466  * Field : Saturation Enable - saten
2467  *
2468  * Enables saturation behavior.
2469  *
2470  * Field Access Macros:
2471  *
2472  */
2473 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field. */
2474 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_LSB 6
2475 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field. */
2476 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_MSB 6
2477 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field. */
2478 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_WIDTH 1
2479 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value. */
2480 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET_MSK 0x00000040
2481 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value. */
2482 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_CLR_MSK 0xffffffbf
2483 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field. */
2484 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_RESET 0x1
2485 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_SATEN field value from a register. */
2486 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_GET(value) (((value) & 0x00000040) >> 6)
2487 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value suitable for setting the register. */
2488 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET(value) (((value) << 6) & 0x00000040)
2489 
2490 /*
2491  * Field : Clock Source - psrc
2492  *
2493  * Controls the VCO input clock source.
2494  *
2495  * Field Enumeration Values:
2496  *
2497  * Enum | Value | Description
2498  * :--------------------------------------|:------|:--------------
2499  * ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_EOSC1 | 0x0 | eosc1_clk
2500  * ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC | 0x1 | cb_intosc_clk
2501  * ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_F2S | 0x2 | f2s_free_clk
2502  *
2503  * Field Access Macros:
2504  *
2505  */
2506 /*
2507  * Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
2508  *
2509  * eosc1_clk
2510  */
2511 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_EOSC1 0x0
2512 /*
2513  * Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
2514  *
2515  * cb_intosc_clk
2516  */
2517 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
2518 /*
2519  * Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
2520  *
2521  * f2s_free_clk
2522  */
2523 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_F2S 0x2
2524 
2525 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field. */
2526 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
2527 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field. */
2528 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_MSB 9
2529 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field. */
2530 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_WIDTH 2
2531 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value. */
2532 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET_MSK 0x00000300
2533 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value. */
2534 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_CLR_MSK 0xfffffcff
2535 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field. */
2536 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_RESET 0x0
2537 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_PSRC field value from a register. */
2538 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_GET(value) (((value) & 0x00000300) >> 8)
2539 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value suitable for setting the register. */
2540 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET(value) (((value) << 8) & 0x00000300)
2541 
2542 /*
2543  * Field : Loop Bandwidth Adjust - bwadj
2544  *
2545  * Provides Loop Bandwidth Adjust value.
2546  *
2547  * Field Access Macros:
2548  *
2549  */
2550 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field. */
2551 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_LSB 16
2552 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field. */
2553 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_MSB 27
2554 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field. */
2555 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_WIDTH 12
2556 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value. */
2557 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET_MSK 0x0fff0000
2558 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value. */
2559 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff
2560 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field. */
2561 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_RESET 0x1
2562 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_BWADJ field value from a register. */
2563 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_GET(value) (((value) & 0x0fff0000) >> 16)
2564 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value suitable for setting the register. */
2565 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET(value) (((value) << 16) & 0x0fff0000)
2566 
2567 /*
2568  * Field : Loop Bandwidth Adjust Enabled - bwadjen
2569  *
2570  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
2571  * Adjust field.
2572  *
2573  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
2574  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
2575  * (12:1) of the M field in the VCO register.
2576  *
2577  * Field Access Macros:
2578  *
2579  */
2580 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field. */
2581 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_LSB 28
2582 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field. */
2583 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_MSB 28
2584 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field. */
2585 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_WIDTH 1
2586 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value. */
2587 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET_MSK 0x10000000
2588 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value. */
2589 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff
2590 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field. */
2591 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_RESET 0x0
2592 /* Extracts the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN field value from a register. */
2593 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_GET(value) (((value) & 0x10000000) >> 28)
2594 /* Produces a ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value suitable for setting the register. */
2595 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET(value) (((value) << 28) & 0x10000000)
2596 
2597 #ifndef __ASSEMBLY__
2598 /*
2599  * WARNING: The C register and register group struct declarations are provided for
2600  * convenience and illustrative purposes. They should, however, be used with
2601  * caution as the C language standard provides no guarantees about the alignment or
2602  * atomicity of device memory accesses. The recommended practice for writing
2603  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2604  * alt_write_word() functions.
2605  *
2606  * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO0.
2607  */
2608 struct ALT_CLKMGR_MAINPLL_VCO0_s
2609 {
2610  uint32_t bgpwrdn : 1; /* BG PWRDN */
2611  uint32_t pwrdn : 1; /* Power down */
2612  uint32_t en : 1; /* Enable */
2613  uint32_t outresetall : 1; /* All Output Counter Reset */
2614  uint32_t regextsel : 1; /* External Regulator Input Select */
2615  uint32_t fasten : 1; /* Fast Locking Enable */
2616  uint32_t saten : 1; /* Saturation Enable */
2617  uint32_t : 1; /* *UNDEFINED* */
2618  uint32_t psrc : 2; /* Clock Source */
2619  uint32_t : 6; /* *UNDEFINED* */
2620  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
2621  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
2622  uint32_t : 3; /* *UNDEFINED* */
2623 };
2624 
2625 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO0. */
2626 typedef volatile struct ALT_CLKMGR_MAINPLL_VCO0_s ALT_CLKMGR_MAINPLL_VCO0_t;
2627 #endif /* __ASSEMBLY__ */
2628 
2629 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO0 register. */
2630 #define ALT_CLKMGR_MAINPLL_VCO0_RESET 0x00010043
2631 /* The byte offset of the ALT_CLKMGR_MAINPLL_VCO0 register from the beginning of the component. */
2632 #define ALT_CLKMGR_MAINPLL_VCO0_OFST 0x0
2633 
2634 /*
2635  * Register : Main PLL VCO Control Register 1 - vco1
2636  *
2637  * Contains settings that control the Main PLL VCO. The VCO1 register contains the
2638  * numerator and denominator counter settings.
2639  *
2640  * Register Layout
2641  *
2642  * Bits | Access | Reset | Description
2643  * :--------|:-------|:------|:----------------
2644  * [12:0] | RW | 0x1 | Numerator (M)
2645  * [15:13] | ??? | 0x0 | *UNDEFINED*
2646  * [21:16] | RW | 0x1 | Denominator (N)
2647  * [31:22] | ??? | 0x0 | *UNDEFINED*
2648  *
2649  */
2650 /*
2651  * Field : Numerator (M) - numer
2652  *
2653  * Numerator in VCO output frequency equation. For incremental frequency change, if
2654  * the new value lead to less than 20% of the frequency change, this value can be
2655  * changed without resetting the PLL. The Numerator and Denominator can not be
2656  * changed at the same time for incremental frequency changed.
2657  *
2658  * Field Access Macros:
2659  *
2660  */
2661 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field. */
2662 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_LSB 0
2663 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field. */
2664 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_MSB 12
2665 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field. */
2666 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_WIDTH 13
2667 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field value. */
2668 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_SET_MSK 0x00001fff
2669 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field value. */
2670 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_CLR_MSK 0xffffe000
2671 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO1_NUMER register field. */
2672 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_RESET 0x1
2673 /* Extracts the ALT_CLKMGR_MAINPLL_VCO1_NUMER field value from a register. */
2674 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_GET(value) (((value) & 0x00001fff) >> 0)
2675 /* Produces a ALT_CLKMGR_MAINPLL_VCO1_NUMER register field value suitable for setting the register. */
2676 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_SET(value) (((value) << 0) & 0x00001fff)
2677 
2678 /*
2679  * Field : Denominator (N) - denom
2680  *
2681  * Denominator in VCO output frequency equation. For incremental frequency change,
2682  * if the new value lead to less than 20% of the frequency change, this value can
2683  * be changed without resetting the PLL. The Numerator and Denominator can not be
2684  * changed at the same time for incremental frequency changed.
2685  *
2686  * Field Access Macros:
2687  *
2688  */
2689 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field. */
2690 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
2691 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field. */
2692 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_MSB 21
2693 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field. */
2694 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_WIDTH 6
2695 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field value. */
2696 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_SET_MSK 0x003f0000
2697 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field value. */
2698 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_CLR_MSK 0xffc0ffff
2699 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO1_DENOM register field. */
2700 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_RESET 0x1
2701 /* Extracts the ALT_CLKMGR_MAINPLL_VCO1_DENOM field value from a register. */
2702 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
2703 /* Produces a ALT_CLKMGR_MAINPLL_VCO1_DENOM register field value suitable for setting the register. */
2704 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_SET(value) (((value) << 16) & 0x003f0000)
2705 
2706 #ifndef __ASSEMBLY__
2707 /*
2708  * WARNING: The C register and register group struct declarations are provided for
2709  * convenience and illustrative purposes. They should, however, be used with
2710  * caution as the C language standard provides no guarantees about the alignment or
2711  * atomicity of device memory accesses. The recommended practice for writing
2712  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2713  * alt_write_word() functions.
2714  *
2715  * The struct declaration for register ALT_CLKMGR_MAINPLL_VCO1.
2716  */
2717 struct ALT_CLKMGR_MAINPLL_VCO1_s
2718 {
2719  uint32_t numer : 13; /* Numerator (M) */
2720  uint32_t : 3; /* *UNDEFINED* */
2721  uint32_t denom : 6; /* Denominator (N) */
2722  uint32_t : 10; /* *UNDEFINED* */
2723 };
2724 
2725 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO1. */
2726 typedef volatile struct ALT_CLKMGR_MAINPLL_VCO1_s ALT_CLKMGR_MAINPLL_VCO1_t;
2727 #endif /* __ASSEMBLY__ */
2728 
2729 /* The reset value of the ALT_CLKMGR_MAINPLL_VCO1 register. */
2730 #define ALT_CLKMGR_MAINPLL_VCO1_RESET 0x00010001
2731 /* The byte offset of the ALT_CLKMGR_MAINPLL_VCO1 register from the beginning of the component. */
2732 #define ALT_CLKMGR_MAINPLL_VCO1_OFST 0x4
2733 
2734 /*
2735  * Register : Enable Register - en
2736  *
2737  * Contains fields that control clock enables for Main Clocks.
2738  *
2739  * 1: The clock is enabled.
2740  *
2741  * 0: The clock is disabled.
2742  *
2743  * Register Layout
2744  *
2745  * Bits | Access | Reset | Description
2746  * :-------|:-------|:------|:-----------------------
2747  * [0] | RW | 0x1 | MPU Clock Group Enable
2748  * [1] | RW | 0x1 | l4_main_clk Enable
2749  * [2] | RW | 0x1 | l4_mp_clk Enable
2750  * [3] | RW | 0x1 | l4_sp_clk Enable
2751  * [4] | RW | 0x1 | Debug Group Enable
2752  * [5] | RW | 0x1 | Debug Timer Enable
2753  * [6] | RW | 0x1 | s2f_user0_clk Enable
2754  * [7] | RW | 0x1 | hmc_pll_ref_clk Enable
2755  * [31:8] | ??? | 0x0 | *UNDEFINED*
2756  *
2757  */
2758 /*
2759  * Field : MPU Clock Group Enable - mpuclken
2760  *
2761  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
2762  *
2763  * Field Access Macros:
2764  *
2765  */
2766 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
2767 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_LSB 0
2768 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
2769 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_MSB 0
2770 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
2771 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_WIDTH 1
2772 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value. */
2773 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET_MSK 0x00000001
2774 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value. */
2775 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_CLR_MSK 0xfffffffe
2776 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
2777 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_RESET 0x1
2778 /* Extracts the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN field value from a register. */
2779 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
2780 /* Produces a ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value suitable for setting the register. */
2781 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
2782 
2783 /*
2784  * Field : l4_main_clk Enable - l4mainclken
2785  *
2786  * Enables clock l4_main_clk output
2787  *
2788  * Field Access Macros:
2789  *
2790  */
2791 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
2792 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_LSB 1
2793 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
2794 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_MSB 1
2795 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
2796 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_WIDTH 1
2797 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value. */
2798 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET_MSK 0x00000002
2799 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value. */
2800 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_CLR_MSK 0xfffffffd
2801 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
2802 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_RESET 0x1
2803 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN field value from a register. */
2804 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
2805 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value suitable for setting the register. */
2806 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
2807 
2808 /*
2809  * Field : l4_mp_clk Enable - l4mpclken
2810  *
2811  * Enables clock l4_mp_clk output
2812  *
2813  * Field Access Macros:
2814  *
2815  */
2816 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
2817 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_LSB 2
2818 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
2819 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_MSB 2
2820 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
2821 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_WIDTH 1
2822 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value. */
2823 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET_MSK 0x00000004
2824 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value. */
2825 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_CLR_MSK 0xfffffffb
2826 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
2827 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_RESET 0x1
2828 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN field value from a register. */
2829 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
2830 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value suitable for setting the register. */
2831 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
2832 
2833 /*
2834  * Field : l4_sp_clk Enable - l4spclken
2835  *
2836  * Enables clock l4_sp_clk output
2837  *
2838  * Field Access Macros:
2839  *
2840  */
2841 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
2842 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_LSB 3
2843 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
2844 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_MSB 3
2845 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
2846 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_WIDTH 1
2847 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value. */
2848 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET_MSK 0x00000008
2849 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value. */
2850 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_CLR_MSK 0xfffffff7
2851 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
2852 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_RESET 0x1
2853 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN field value from a register. */
2854 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
2855 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value suitable for setting the register. */
2856 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
2857 
2858 /*
2859  * Field : Debug Group Enable - csclken
2860  *
2861  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk, and cs_trace_clk)
2862  *
2863  * Field Access Macros:
2864  *
2865  */
2866 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
2867 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_LSB 4
2868 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
2869 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_MSB 4
2870 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
2871 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_WIDTH 1
2872 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value. */
2873 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET_MSK 0x00000010
2874 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value. */
2875 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_CLR_MSK 0xffffffef
2876 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
2877 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_RESET 0x1
2878 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CSCLKEN field value from a register. */
2879 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
2880 /* Produces a ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value suitable for setting the register. */
2881 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
2882 
2883 /*
2884  * Field : Debug Timer Enable - cstimerclken
2885  *
2886  * Enables Debug Timer Clock output (cs_timer_clk)
2887  *
2888  * Field Access Macros:
2889  *
2890  */
2891 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field. */
2892 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_LSB 5
2893 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field. */
2894 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_MSB 5
2895 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field. */
2896 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_WIDTH 1
2897 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field value. */
2898 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_SET_MSK 0x00000020
2899 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field value. */
2900 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_CLR_MSK 0xffffffdf
2901 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field. */
2902 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_RESET 0x1
2903 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN field value from a register. */
2904 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
2905 /* Produces a ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN register field value suitable for setting the register. */
2906 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
2907 
2908 /*
2909  * Field : s2f_user0_clk Enable - s2fuser0clken
2910  *
2911  * Enables clock s2f_user0_clk output
2912  *
2913  * Field Access Macros:
2914  *
2915  */
2916 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
2917 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_LSB 6
2918 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
2919 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_MSB 6
2920 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
2921 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_WIDTH 1
2922 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value. */
2923 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040
2924 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value. */
2925 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
2926 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
2927 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_RESET 0x1
2928 /* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN field value from a register. */
2929 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
2930 /* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value suitable for setting the register. */
2931 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
2932 
2933 /*
2934  * Field : hmc_pll_ref_clk Enable - hmcpllrefclken
2935  *
2936  * Enables clock hmc_pll_ref_clk output
2937  *
2938  * Field Access Macros:
2939  *
2940  */
2941 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field. */
2942 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_LSB 7
2943 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field. */
2944 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_MSB 7
2945 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field. */
2946 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_WIDTH 1
2947 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field value. */
2948 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080
2949 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field value. */
2950 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
2951 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field. */
2952 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_RESET 0x1
2953 /* Extracts the ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN field value from a register. */
2954 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
2955 /* Produces a ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN register field value suitable for setting the register. */
2956 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
2957 
2958 #ifndef __ASSEMBLY__
2959 /*
2960  * WARNING: The C register and register group struct declarations are provided for
2961  * convenience and illustrative purposes. They should, however, be used with
2962  * caution as the C language standard provides no guarantees about the alignment or
2963  * atomicity of device memory accesses. The recommended practice for writing
2964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2965  * alt_write_word() functions.
2966  *
2967  * The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
2968  */
2969 struct ALT_CLKMGR_MAINPLL_EN_s
2970 {
2971  uint32_t mpuclken : 1; /* MPU Clock Group Enable */
2972  uint32_t l4mainclken : 1; /* l4_main_clk Enable */
2973  uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
2974  uint32_t l4spclken : 1; /* l4_sp_clk Enable */
2975  uint32_t csclken : 1; /* Debug Group Enable */
2976  uint32_t cstimerclken : 1; /* Debug Timer Enable */
2977  uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
2978  uint32_t hmcpllrefclken : 1; /* hmc_pll_ref_clk Enable */
2979  uint32_t : 24; /* *UNDEFINED* */
2980 };
2981 
2982 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */
2983 typedef volatile struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t;
2984 #endif /* __ASSEMBLY__ */
2985 
2986 /* The reset value of the ALT_CLKMGR_MAINPLL_EN register. */
2987 #define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
2988 /* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */
2989 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x8
2990 
2991 /*
2992  * Register : Enable Set Register - ens
2993  *
2994  * Write One to Set correspondng fields in the Enable Register.
2995  *
2996  * Register Layout
2997  *
2998  * Bits | Access | Reset | Description
2999  * :-------|:-------|:------|:-----------------------
3000  * [0] | RW | 0x1 | MPU Clock Group Enable
3001  * [1] | RW | 0x1 | l4_main_clk Enable
3002  * [2] | RW | 0x1 | l4_mp_clk Enable
3003  * [3] | RW | 0x1 | l4_sp_clk Enable
3004  * [4] | RW | 0x1 | Debug Group Enable
3005  * [5] | RW | 0x1 | Debug Timer Enable
3006  * [6] | RW | 0x1 | s2f_user0_clk Enable
3007  * [7] | RW | 0x1 | hmc_pll_ref_clk Enable
3008  * [31:8] | ??? | 0x0 | *UNDEFINED*
3009  *
3010  */
3011 /*
3012  * Field : MPU Clock Group Enable - mpuclken
3013  *
3014  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
3015  *
3016  * Field Access Macros:
3017  *
3018  */
3019 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
3020 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_LSB 0
3021 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
3022 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_MSB 0
3023 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
3024 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_WIDTH 1
3025 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value. */
3026 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET_MSK 0x00000001
3027 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value. */
3028 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_CLR_MSK 0xfffffffe
3029 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
3030 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_RESET 0x1
3031 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN field value from a register. */
3032 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
3033 /* Produces a ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value suitable for setting the register. */
3034 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
3035 
3036 /*
3037  * Field : l4_main_clk Enable - l4mainclken
3038  *
3039  * Enables clock l4_main_clk output
3040  *
3041  * Field Access Macros:
3042  *
3043  */
3044 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
3045 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_LSB 1
3046 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
3047 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_MSB 1
3048 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
3049 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_WIDTH 1
3050 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value. */
3051 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET_MSK 0x00000002
3052 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value. */
3053 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_CLR_MSK 0xfffffffd
3054 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
3055 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_RESET 0x1
3056 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN field value from a register. */
3057 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
3058 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value suitable for setting the register. */
3059 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
3060 
3061 /*
3062  * Field : l4_mp_clk Enable - l4mpclken
3063  *
3064  * Enables clock l4_mp_clk output
3065  *
3066  * Field Access Macros:
3067  *
3068  */
3069 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
3070 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_LSB 2
3071 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
3072 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_MSB 2
3073 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
3074 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_WIDTH 1
3075 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value. */
3076 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET_MSK 0x00000004
3077 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value. */
3078 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_CLR_MSK 0xfffffffb
3079 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
3080 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_RESET 0x1
3081 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN field value from a register. */
3082 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
3083 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value suitable for setting the register. */
3084 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
3085 
3086 /*
3087  * Field : l4_sp_clk Enable - l4spclken
3088  *
3089  * Enables clock l4_sp_clk output
3090  *
3091  * Field Access Macros:
3092  *
3093  */
3094 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
3095 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_LSB 3
3096 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
3097 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_MSB 3
3098 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
3099 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_WIDTH 1
3100 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value. */
3101 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET_MSK 0x00000008
3102 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value. */
3103 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_CLR_MSK 0xfffffff7
3104 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
3105 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_RESET 0x1
3106 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN field value from a register. */
3107 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
3108 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value suitable for setting the register. */
3109 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
3110 
3111 /*
3112  * Field : Debug Group Enable - csclken
3113  *
3114  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)
3115  *
3116  * Field Access Macros:
3117  *
3118  */
3119 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
3120 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_LSB 4
3121 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
3122 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_MSB 4
3123 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
3124 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_WIDTH 1
3125 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value. */
3126 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET_MSK 0x00000010
3127 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value. */
3128 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_CLR_MSK 0xffffffef
3129 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
3130 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_RESET 0x1
3131 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN field value from a register. */
3132 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
3133 /* Produces a ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value suitable for setting the register. */
3134 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
3135 
3136 /*
3137  * Field : Debug Timer Enable - cstimerclken
3138  *
3139  * Enables Debug Timer Clock output (cs_timer_clk)
3140  *
3141  * Field Access Macros:
3142  *
3143  */
3144 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field. */
3145 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_LSB 5
3146 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field. */
3147 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_MSB 5
3148 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field. */
3149 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_WIDTH 1
3150 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field value. */
3151 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_SET_MSK 0x00000020
3152 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field value. */
3153 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_CLR_MSK 0xffffffdf
3154 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field. */
3155 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_RESET 0x1
3156 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN field value from a register. */
3157 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
3158 /* Produces a ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN register field value suitable for setting the register. */
3159 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
3160 
3161 /*
3162  * Field : s2f_user0_clk Enable - s2fuser0clken
3163  *
3164  * Enables clock s2f_user0_clk output
3165  *
3166  * Field Access Macros:
3167  *
3168  */
3169 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
3170 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_LSB 6
3171 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
3172 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_MSB 6
3173 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
3174 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_WIDTH 1
3175 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value. */
3176 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET_MSK 0x00000040
3177 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value. */
3178 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
3179 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
3180 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_RESET 0x1
3181 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN field value from a register. */
3182 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
3183 /* Produces a ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value suitable for setting the register. */
3184 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
3185 
3186 /*
3187  * Field : hmc_pll_ref_clk Enable - hmcpllrefclken
3188  *
3189  * Enables clock hmc_pll_ref_clk output
3190  *
3191  * Field Access Macros:
3192  *
3193  */
3194 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field. */
3195 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_LSB 7
3196 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field. */
3197 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_MSB 7
3198 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field. */
3199 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_WIDTH 1
3200 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field value. */
3201 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_SET_MSK 0x00000080
3202 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field value. */
3203 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
3204 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field. */
3205 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_RESET 0x1
3206 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN field value from a register. */
3207 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
3208 /* Produces a ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN register field value suitable for setting the register. */
3209 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
3210 
3211 #ifndef __ASSEMBLY__
3212 /*
3213  * WARNING: The C register and register group struct declarations are provided for
3214  * convenience and illustrative purposes. They should, however, be used with
3215  * caution as the C language standard provides no guarantees about the alignment or
3216  * atomicity of device memory accesses. The recommended practice for writing
3217  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3218  * alt_write_word() functions.
3219  *
3220  * The struct declaration for register ALT_CLKMGR_MAINPLL_ENS.
3221  */
3222 struct ALT_CLKMGR_MAINPLL_ENS_s
3223 {
3224  uint32_t mpuclken : 1; /* MPU Clock Group Enable */
3225  uint32_t l4mainclken : 1; /* l4_main_clk Enable */
3226  uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
3227  uint32_t l4spclken : 1; /* l4_sp_clk Enable */
3228  uint32_t csclken : 1; /* Debug Group Enable */
3229  uint32_t cstimerclken : 1; /* Debug Timer Enable */
3230  uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
3231  uint32_t hmcpllrefclken : 1; /* hmc_pll_ref_clk Enable */
3232  uint32_t : 24; /* *UNDEFINED* */
3233 };
3234 
3235 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_ENS. */
3236 typedef volatile struct ALT_CLKMGR_MAINPLL_ENS_s ALT_CLKMGR_MAINPLL_ENS_t;
3237 #endif /* __ASSEMBLY__ */
3238 
3239 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS register. */
3240 #define ALT_CLKMGR_MAINPLL_ENS_RESET 0x000000ff
3241 /* The byte offset of the ALT_CLKMGR_MAINPLL_ENS register from the beginning of the component. */
3242 #define ALT_CLKMGR_MAINPLL_ENS_OFST 0xc
3243 
3244 /*
3245  * Register : Enable Reset Register - enr
3246  *
3247  * Write One to Clear corresponding fields in Enable Register.
3248  *
3249  * Register Layout
3250  *
3251  * Bits | Access | Reset | Description
3252  * :-------|:-------|:------|:-----------------------
3253  * [0] | RW | 0x1 | MPU Clock Group Enable
3254  * [1] | RW | 0x1 | l4_main_clk Enable
3255  * [2] | RW | 0x1 | l4_mp_clk Enable
3256  * [3] | RW | 0x1 | l4_sp_clk Enable
3257  * [4] | RW | 0x1 | Debug Group Enable
3258  * [5] | RW | 0x1 | Debug Timer Enable
3259  * [6] | RW | 0x1 | s2f_user0_clk Enable
3260  * [7] | RW | 0x1 | hmc_pll_ref_clk Enable
3261  * [31:8] | ??? | 0x0 | *UNDEFINED*
3262  *
3263  */
3264 /*
3265  * Field : MPU Clock Group Enable - mpuclken
3266  *
3267  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
3268  *
3269  * Field Access Macros:
3270  *
3271  */
3272 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
3273 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_LSB 0
3274 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
3275 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_MSB 0
3276 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
3277 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_WIDTH 1
3278 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value. */
3279 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET_MSK 0x00000001
3280 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value. */
3281 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_CLR_MSK 0xfffffffe
3282 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
3283 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_RESET 0x1
3284 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN field value from a register. */
3285 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
3286 /* Produces a ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value suitable for setting the register. */
3287 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
3288 
3289 /*
3290  * Field : l4_main_clk Enable - l4mainclken
3291  *
3292  * Enables clock l4_main_clk output
3293  *
3294  * Field Access Macros:
3295  *
3296  */
3297 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
3298 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_LSB 1
3299 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
3300 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_MSB 1
3301 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
3302 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_WIDTH 1
3303 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value. */
3304 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET_MSK 0x00000002
3305 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value. */
3306 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_CLR_MSK 0xfffffffd
3307 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
3308 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_RESET 0x1
3309 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN field value from a register. */
3310 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
3311 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value suitable for setting the register. */
3312 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
3313 
3314 /*
3315  * Field : l4_mp_clk Enable - l4mpclken
3316  *
3317  * Enables clock l4_mp_clk output
3318  *
3319  * Field Access Macros:
3320  *
3321  */
3322 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
3323 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_LSB 2
3324 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
3325 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_MSB 2
3326 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
3327 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_WIDTH 1
3328 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value. */
3329 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET_MSK 0x00000004
3330 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value. */
3331 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_CLR_MSK 0xfffffffb
3332 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
3333 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_RESET 0x1
3334 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN field value from a register. */
3335 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
3336 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value suitable for setting the register. */
3337 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
3338 
3339 /*
3340  * Field : l4_sp_clk Enable - l4spclken
3341  *
3342  * Enables clock l4_sp_clk output
3343  *
3344  * Field Access Macros:
3345  *
3346  */
3347 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
3348 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_LSB 3
3349 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
3350 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_MSB 3
3351 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
3352 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_WIDTH 1
3353 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value. */
3354 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET_MSK 0x00000008
3355 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value. */
3356 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_CLR_MSK 0xfffffff7
3357 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
3358 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_RESET 0x1
3359 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN field value from a register. */
3360 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
3361 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value suitable for setting the register. */
3362 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
3363 
3364 /*
3365  * Field : Debug Group Enable - csclken
3366  *
3367  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)
3368  *
3369  * Field Access Macros:
3370  *
3371  */
3372 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
3373 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_LSB 4
3374 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
3375 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_MSB 4
3376 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
3377 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_WIDTH 1
3378 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value. */
3379 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET_MSK 0x00000010
3380 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value. */
3381 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_CLR_MSK 0xffffffef
3382 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
3383 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_RESET 0x1
3384 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN field value from a register. */
3385 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
3386 /* Produces a ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value suitable for setting the register. */
3387 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
3388 
3389 /*
3390  * Field : Debug Timer Enable - cstimerclken
3391  *
3392  * Enables Debug Timer Clock output (cs_timer_clk)
3393  *
3394  * Field Access Macros:
3395  *
3396  */
3397 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field. */
3398 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_LSB 5
3399 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field. */
3400 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_MSB 5
3401 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field. */
3402 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_WIDTH 1
3403 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value. */
3404 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET_MSK 0x00000020
3405 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value. */
3406 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_CLR_MSK 0xffffffdf
3407 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field. */
3408 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_RESET 0x1
3409 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN field value from a register. */
3410 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
3411 /* Produces a ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value suitable for setting the register. */
3412 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
3413 
3414 /*
3415  * Field : s2f_user0_clk Enable - s2fuser0clken
3416  *
3417  * Enables clock s2f_user0_clk output
3418  *
3419  * Field Access Macros:
3420  *
3421  */
3422 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
3423 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_LSB 6
3424 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
3425 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_MSB 6
3426 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
3427 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_WIDTH 1
3428 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value. */
3429 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET_MSK 0x00000040
3430 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value. */
3431 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
3432 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
3433 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_RESET 0x1
3434 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN field value from a register. */
3435 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
3436 /* Produces a ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value suitable for setting the register. */
3437 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
3438 
3439 /*
3440  * Field : hmc_pll_ref_clk Enable - hmcpllrefclken
3441  *
3442  * Enables clock hmc_pll_ref_clk output
3443  *
3444  * Field Access Macros:
3445  *
3446  */
3447 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field. */
3448 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_LSB 7
3449 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field. */
3450 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_MSB 7
3451 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field. */
3452 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_WIDTH 1
3453 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value. */
3454 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET_MSK 0x00000080
3455 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value. */
3456 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
3457 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field. */
3458 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_RESET 0x1
3459 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN field value from a register. */
3460 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
3461 /* Produces a ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value suitable for setting the register. */
3462 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
3463 
3464 #ifndef __ASSEMBLY__
3465 /*
3466  * WARNING: The C register and register group struct declarations are provided for
3467  * convenience and illustrative purposes. They should, however, be used with
3468  * caution as the C language standard provides no guarantees about the alignment or
3469  * atomicity of device memory accesses. The recommended practice for writing
3470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3471  * alt_write_word() functions.
3472  *
3473  * The struct declaration for register ALT_CLKMGR_MAINPLL_ENR.
3474  */
3475 struct ALT_CLKMGR_MAINPLL_ENR_s
3476 {
3477  uint32_t mpuclken : 1; /* MPU Clock Group Enable */
3478  uint32_t l4mainclken : 1; /* l4_main_clk Enable */
3479  uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
3480  uint32_t l4spclken : 1; /* l4_sp_clk Enable */
3481  uint32_t csclken : 1; /* Debug Group Enable */
3482  uint32_t cstimerclken : 1; /* Debug Timer Enable */
3483  uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
3484  uint32_t hmcpllrefclken : 1; /* hmc_pll_ref_clk Enable */
3485  uint32_t : 24; /* *UNDEFINED* */
3486 };
3487 
3488 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_ENR. */
3489 typedef volatile struct ALT_CLKMGR_MAINPLL_ENR_s ALT_CLKMGR_MAINPLL_ENR_t;
3490 #endif /* __ASSEMBLY__ */
3491 
3492 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR register. */
3493 #define ALT_CLKMGR_MAINPLL_ENR_RESET 0x000000ff
3494 /* The byte offset of the ALT_CLKMGR_MAINPLL_ENR register from the beginning of the component. */
3495 #define ALT_CLKMGR_MAINPLL_ENR_OFST 0x10
3496 
3497 /*
3498  * Register : Bypass Register - bypass
3499  *
3500  * Contains fields that control bypass for clocks derived from the Main PLL.
3501  *
3502  * 1: The clock is bypassed to boot_clk.
3503  *
3504  * 0: The clock is derived from the 5:1 active mux.
3505  *
3506  * Register Layout
3507  *
3508  * Bits | Access | Reset | Description
3509  * :-------|:-------|:------|:-------------------------
3510  * [0] | RW | 0x1 | MPU Bypass
3511  * [1] | RW | 0x1 | NOC Bypass
3512  * [2] | RW | 0x1 | S2F User0 Bypass
3513  * [3] | RW | 0x1 | HMC PLL Reference Bypass
3514  * [4] | RW | 0x1 | PLL RFEN Clock Bypass
3515  * [5] | RW | 0x1 | PLL FBEN Clock Bypass
3516  * [31:6] | ??? | 0x0 | *UNDEFINED*
3517  *
3518  */
3519 /*
3520  * Field : MPU Bypass - mpu
3521  *
3522  * If set, the MPU clock group will be bypassed to the boot_clk.
3523  *
3524  * Field Access Macros:
3525  *
3526  */
3527 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
3528 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_LSB 0
3529 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
3530 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_MSB 0
3531 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
3532 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_WIDTH 1
3533 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value. */
3534 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET_MSK 0x00000001
3535 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value. */
3536 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_CLR_MSK 0xfffffffe
3537 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
3538 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_RESET 0x1
3539 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_MPU field value from a register. */
3540 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3541 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value suitable for setting the register. */
3542 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET(value) (((value) << 0) & 0x00000001)
3543 
3544 /*
3545  * Field : NOC Bypass - noc
3546  *
3547  * If set, the NOC clock group will be bypassed to boot_clk.
3548  *
3549  * Field Access Macros:
3550  *
3551  */
3552 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
3553 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_LSB 1
3554 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
3555 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_MSB 1
3556 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
3557 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_WIDTH 1
3558 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value. */
3559 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET_MSK 0x00000002
3560 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value. */
3561 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_CLR_MSK 0xfffffffd
3562 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
3563 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_RESET 0x1
3564 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_NOC field value from a register. */
3565 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_GET(value) (((value) & 0x00000002) >> 1)
3566 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value suitable for setting the register. */
3567 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET(value) (((value) << 1) & 0x00000002)
3568 
3569 /*
3570  * Field : S2F User0 Bypass - s2fuser0
3571  *
3572  * If set, the s2f_user0_clk will be bypassed to the boot_clk.
3573  *
3574  * Field Access Macros:
3575  *
3576  */
3577 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
3578 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_LSB 2
3579 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
3580 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_MSB 2
3581 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
3582 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_WIDTH 1
3583 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value. */
3584 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET_MSK 0x00000004
3585 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value. */
3586 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_CLR_MSK 0xfffffffb
3587 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
3588 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_RESET 0x1
3589 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 field value from a register. */
3590 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
3591 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value suitable for setting the register. */
3592 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
3593 
3594 /*
3595  * Field : HMC PLL Reference Bypass - hmcpllref
3596  *
3597  * If set, the hmc_pll_ref_clk will be bypassed to the boot_clk.
3598  *
3599  * Field Access Macros:
3600  *
3601  */
3602 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field. */
3603 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_LSB 3
3604 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field. */
3605 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_MSB 3
3606 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field. */
3607 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_WIDTH 1
3608 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field value. */
3609 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_SET_MSK 0x00000008
3610 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field value. */
3611 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_CLR_MSK 0xfffffff7
3612 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field. */
3613 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_RESET 0x1
3614 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF field value from a register. */
3615 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
3616 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF register field value suitable for setting the register. */
3617 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
3618 
3619 /*
3620  * Field : PLL RFEN Clock Bypass - rfen
3621  *
3622  * If set, the pll_main_rfen_clk will be bypassed to the boot_clk. The
3623  * pll_main_rfen_clk is used to synchronously update the Denominator to the Main
3624  * PLL.
3625  *
3626  * Field Access Macros:
3627  *
3628  */
3629 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field. */
3630 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_LSB 4
3631 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field. */
3632 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_MSB 4
3633 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field. */
3634 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_WIDTH 1
3635 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field value. */
3636 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_SET_MSK 0x00000010
3637 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field value. */
3638 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_CLR_MSK 0xffffffef
3639 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field. */
3640 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_RESET 0x1
3641 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_RFEN field value from a register. */
3642 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_GET(value) (((value) & 0x00000010) >> 4)
3643 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_RFEN register field value suitable for setting the register. */
3644 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_SET(value) (((value) << 4) & 0x00000010)
3645 
3646 /*
3647  * Field : PLL FBEN Clock Bypass - fben
3648  *
3649  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
3650  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
3651  *
3652  * Field Access Macros:
3653  *
3654  */
3655 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field. */
3656 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_LSB 5
3657 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field. */
3658 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_MSB 5
3659 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field. */
3660 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_WIDTH 1
3661 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field value. */
3662 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_SET_MSK 0x00000020
3663 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field value. */
3664 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_CLR_MSK 0xffffffdf
3665 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field. */
3666 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_RESET 0x1
3667 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_FBEN field value from a register. */
3668 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_GET(value) (((value) & 0x00000020) >> 5)
3669 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_FBEN register field value suitable for setting the register. */
3670 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_SET(value) (((value) << 5) & 0x00000020)
3671 
3672 #ifndef __ASSEMBLY__
3673 /*
3674  * WARNING: The C register and register group struct declarations are provided for
3675  * convenience and illustrative purposes. They should, however, be used with
3676  * caution as the C language standard provides no guarantees about the alignment or
3677  * atomicity of device memory accesses. The recommended practice for writing
3678  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3679  * alt_write_word() functions.
3680  *
3681  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASS.
3682  */
3683 struct ALT_CLKMGR_MAINPLL_BYPASS_s
3684 {
3685  uint32_t mpu : 1; /* MPU Bypass */
3686  uint32_t noc : 1; /* NOC Bypass */
3687  uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
3688  uint32_t hmcpllref : 1; /* HMC PLL Reference Bypass */
3689  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
3690  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
3691  uint32_t : 26; /* *UNDEFINED* */
3692 };
3693 
3694 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASS. */
3695 typedef volatile struct ALT_CLKMGR_MAINPLL_BYPASS_s ALT_CLKMGR_MAINPLL_BYPASS_t;
3696 #endif /* __ASSEMBLY__ */
3697 
3698 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS register. */
3699 #define ALT_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
3700 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASS register from the beginning of the component. */
3701 #define ALT_CLKMGR_MAINPLL_BYPASS_OFST 0x14
3702 
3703 /*
3704  * Register : Bypass Set Register - bypasss
3705  *
3706  * Write One to Set corresponding fields in Bypass Register.
3707  *
3708  * Register Layout
3709  *
3710  * Bits | Access | Reset | Description
3711  * :-------|:-------|:------|:-------------------------
3712  * [0] | RW | 0x1 | MPU Bypass
3713  * [1] | RW | 0x1 | NOC Bypass
3714  * [2] | RW | 0x1 | S2F User0 Bypass
3715  * [3] | RW | 0x1 | HMC PLL Reference Bypass
3716  * [4] | RW | 0x1 | PLL RFEN Clock Bypass
3717  * [5] | RW | 0x1 | PLL FBEN Clock Bypass
3718  * [31:6] | ??? | 0x0 | *UNDEFINED*
3719  *
3720  */
3721 /*
3722  * Field : MPU Bypass - mpu
3723  *
3724  * If set, the MPU clock group will be bypassed to the input clock reference of the
3725  * Main PLL.
3726  *
3727  * Field Access Macros:
3728  *
3729  */
3730 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
3731 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_LSB 0
3732 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
3733 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_MSB 0
3734 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
3735 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_WIDTH 1
3736 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value. */
3737 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET_MSK 0x00000001
3738 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value. */
3739 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_CLR_MSK 0xfffffffe
3740 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
3741 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_RESET 0x1
3742 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_MPU field value from a register. */
3743 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3744 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value suitable for setting the register. */
3745 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET(value) (((value) << 0) & 0x00000001)
3746 
3747 /*
3748  * Field : NOC Bypass - noc
3749  *
3750  * If set, the NOC clock group will be bypassed to the input clock reference of the
3751  * Main PLL.
3752  *
3753  * Field Access Macros:
3754  *
3755  */
3756 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
3757 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_LSB 1
3758 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
3759 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_MSB 1
3760 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
3761 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_WIDTH 1
3762 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value. */
3763 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET_MSK 0x00000002
3764 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value. */
3765 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_CLR_MSK 0xfffffffd
3766 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
3767 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_RESET 0x1
3768 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_NOC field value from a register. */
3769 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_GET(value) (((value) & 0x00000002) >> 1)
3770 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value suitable for setting the register. */
3771 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET(value) (((value) << 1) & 0x00000002)
3772 
3773 /*
3774  * Field : S2F User0 Bypass - s2fuser0
3775  *
3776  * If set, the s2f_user0_clk will be bypassed to the input clock reference of the
3777  * Main PLL.
3778  *
3779  * Field Access Macros:
3780  *
3781  */
3782 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
3783 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_LSB 2
3784 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
3785 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_MSB 2
3786 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
3787 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_WIDTH 1
3788 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value. */
3789 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET_MSK 0x00000004
3790 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value. */
3791 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_CLR_MSK 0xfffffffb
3792 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
3793 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_RESET 0x1
3794 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 field value from a register. */
3795 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
3796 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value suitable for setting the register. */
3797 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
3798 
3799 /*
3800  * Field : HMC PLL Reference Bypass - hmcpllref
3801  *
3802  * If set, the hmc_pll_ref_clk will be bypassed to the boot_clk.
3803  *
3804  * Field Access Macros:
3805  *
3806  */
3807 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field. */
3808 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_LSB 3
3809 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field. */
3810 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_MSB 3
3811 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field. */
3812 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_WIDTH 1
3813 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field value. */
3814 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_SET_MSK 0x00000008
3815 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field value. */
3816 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_CLR_MSK 0xfffffff7
3817 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field. */
3818 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_RESET 0x1
3819 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF field value from a register. */
3820 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
3821 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF register field value suitable for setting the register. */
3822 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
3823 
3824 /*
3825  * Field : PLL RFEN Clock Bypass - rfen
3826  *
3827  * If set, the pll_main_rfen_clk will be bypassed to the boot_clk. The
3828  * pll_main_rfen_clk is used to synchronously update the Denominator to the Main
3829  * PLL.
3830  *
3831  * Field Access Macros:
3832  *
3833  */
3834 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field. */
3835 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_LSB 4
3836 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field. */
3837 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_MSB 4
3838 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field. */
3839 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_WIDTH 1
3840 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field value. */
3841 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_SET_MSK 0x00000010
3842 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field value. */
3843 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_CLR_MSK 0xffffffef
3844 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field. */
3845 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_RESET 0x1
3846 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_RFEN field value from a register. */
3847 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_GET(value) (((value) & 0x00000010) >> 4)
3848 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_RFEN register field value suitable for setting the register. */
3849 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_SET(value) (((value) << 4) & 0x00000010)
3850 
3851 /*
3852  * Field : PLL FBEN Clock Bypass - fben
3853  *
3854  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
3855  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
3856  *
3857  * Field Access Macros:
3858  *
3859  */
3860 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field. */
3861 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_LSB 5
3862 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field. */
3863 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_MSB 5
3864 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field. */
3865 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_WIDTH 1
3866 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field value. */
3867 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_SET_MSK 0x00000020
3868 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field value. */
3869 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_CLR_MSK 0xffffffdf
3870 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field. */
3871 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_RESET 0x1
3872 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_FBEN field value from a register. */
3873 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_GET(value) (((value) & 0x00000020) >> 5)
3874 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_FBEN register field value suitable for setting the register. */
3875 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_SET(value) (((value) << 5) & 0x00000020)
3876 
3877 #ifndef __ASSEMBLY__
3878 /*
3879  * WARNING: The C register and register group struct declarations are provided for
3880  * convenience and illustrative purposes. They should, however, be used with
3881  * caution as the C language standard provides no guarantees about the alignment or
3882  * atomicity of device memory accesses. The recommended practice for writing
3883  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3884  * alt_write_word() functions.
3885  *
3886  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASSS.
3887  */
3888 struct ALT_CLKMGR_MAINPLL_BYPASSS_s
3889 {
3890  uint32_t mpu : 1; /* MPU Bypass */
3891  uint32_t noc : 1; /* NOC Bypass */
3892  uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
3893  uint32_t hmcpllref : 1; /* HMC PLL Reference Bypass */
3894  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
3895  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
3896  uint32_t : 26; /* *UNDEFINED* */
3897 };
3898 
3899 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASSS. */
3900 typedef volatile struct ALT_CLKMGR_MAINPLL_BYPASSS_s ALT_CLKMGR_MAINPLL_BYPASSS_t;
3901 #endif /* __ASSEMBLY__ */
3902 
3903 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS register. */
3904 #define ALT_CLKMGR_MAINPLL_BYPASSS_RESET 0x0000003f
3905 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASSS register from the beginning of the component. */
3906 #define ALT_CLKMGR_MAINPLL_BYPASSS_OFST 0x18
3907 
3908 /*
3909  * Register : Bypass Reset Register - bypassr
3910  *
3911  * Write One to Clear corresponding fields in Bypass Register.
3912  *
3913  * Register Layout
3914  *
3915  * Bits | Access | Reset | Description
3916  * :-------|:-------|:------|:-------------------------
3917  * [0] | RW | 0x1 | MPU Bypass
3918  * [1] | RW | 0x1 | NOC Bypass
3919  * [2] | RW | 0x1 | S2F User0 Bypass
3920  * [3] | RW | 0x1 | HMC PLL Reference Bypass
3921  * [4] | RW | 0x1 | PLL RFEN Clock Bypass
3922  * [5] | RW | 0x1 | PLL FBEN Clock Bypass
3923  * [31:6] | ??? | 0x0 | *UNDEFINED*
3924  *
3925  */
3926 /*
3927  * Field : MPU Bypass - mpu
3928  *
3929  * If set, the MPU clock group will be bypassed to the input clock reference of the
3930  * Main PLL.
3931  *
3932  * Field Access Macros:
3933  *
3934  */
3935 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
3936 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_LSB 0
3937 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
3938 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_MSB 0
3939 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
3940 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_WIDTH 1
3941 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value. */
3942 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET_MSK 0x00000001
3943 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value. */
3944 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_CLR_MSK 0xfffffffe
3945 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
3946 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_RESET 0x1
3947 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_MPU field value from a register. */
3948 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_GET(value) (((value) & 0x00000001) >> 0)
3949 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value suitable for setting the register. */
3950 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET(value) (((value) << 0) & 0x00000001)
3951 
3952 /*
3953  * Field : NOC Bypass - noc
3954  *
3955  * If set, the NOC clock group will be bypassed to the input clock reference of the
3956  * Main PLL.
3957  *
3958  * Field Access Macros:
3959  *
3960  */
3961 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
3962 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_LSB 1
3963 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
3964 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_MSB 1
3965 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
3966 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_WIDTH 1
3967 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value. */
3968 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET_MSK 0x00000002
3969 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value. */
3970 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_CLR_MSK 0xfffffffd
3971 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
3972 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_RESET 0x1
3973 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_NOC field value from a register. */
3974 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_GET(value) (((value) & 0x00000002) >> 1)
3975 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value suitable for setting the register. */
3976 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET(value) (((value) << 1) & 0x00000002)
3977 
3978 /*
3979  * Field : S2F User0 Bypass - s2fuser0
3980  *
3981  * If set, the s2f_user0_clk will be bypassed to the input clock reference of the
3982  * Main PLL.
3983  *
3984  * Field Access Macros:
3985  *
3986  */
3987 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
3988 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_LSB 2
3989 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
3990 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_MSB 2
3991 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
3992 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_WIDTH 1
3993 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value. */
3994 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET_MSK 0x00000004
3995 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value. */
3996 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_CLR_MSK 0xfffffffb
3997 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
3998 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_RESET 0x1
3999 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 field value from a register. */
4000 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
4001 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value suitable for setting the register. */
4002 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
4003 
4004 /*
4005  * Field : HMC PLL Reference Bypass - hmcpllref
4006  *
4007  * If set, the hmc_pll_ref_clk will be bypassed to the boot_clk.
4008  *
4009  * Field Access Macros:
4010  *
4011  */
4012 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field. */
4013 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_LSB 3
4014 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field. */
4015 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_MSB 3
4016 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field. */
4017 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_WIDTH 1
4018 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value. */
4019 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET_MSK 0x00000008
4020 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value. */
4021 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_CLR_MSK 0xfffffff7
4022 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field. */
4023 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_RESET 0x1
4024 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF field value from a register. */
4025 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
4026 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value suitable for setting the register. */
4027 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
4028 
4029 /*
4030  * Field : PLL RFEN Clock Bypass - rfen
4031  *
4032  * If set, the pll_main_rfen_clk will be bypassed to the boot_clk. The
4033  * pll_main_rfen_clk is used to synchronously update the Denominator to the Main
4034  * PLL.
4035  *
4036  * Field Access Macros:
4037  *
4038  */
4039 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field. */
4040 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_LSB 4
4041 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field. */
4042 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_MSB 4
4043 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field. */
4044 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_WIDTH 1
4045 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value. */
4046 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET_MSK 0x00000010
4047 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value. */
4048 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_CLR_MSK 0xffffffef
4049 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field. */
4050 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_RESET 0x1
4051 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN field value from a register. */
4052 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_GET(value) (((value) & 0x00000010) >> 4)
4053 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value suitable for setting the register. */
4054 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET(value) (((value) << 4) & 0x00000010)
4055 
4056 /*
4057  * Field : PLL FBEN Clock Bypass - fben
4058  *
4059  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
4060  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
4061  *
4062  * Field Access Macros:
4063  *
4064  */
4065 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field. */
4066 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_LSB 5
4067 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field. */
4068 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_MSB 5
4069 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field. */
4070 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_WIDTH 1
4071 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value. */
4072 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET_MSK 0x00000020
4073 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value. */
4074 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_CLR_MSK 0xffffffdf
4075 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field. */
4076 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_RESET 0x1
4077 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN field value from a register. */
4078 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_GET(value) (((value) & 0x00000020) >> 5)
4079 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value suitable for setting the register. */
4080 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET(value) (((value) << 5) & 0x00000020)
4081 
4082 #ifndef __ASSEMBLY__
4083 /*
4084  * WARNING: The C register and register group struct declarations are provided for
4085  * convenience and illustrative purposes. They should, however, be used with
4086  * caution as the C language standard provides no guarantees about the alignment or
4087  * atomicity of device memory accesses. The recommended practice for writing
4088  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4089  * alt_write_word() functions.
4090  *
4091  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASSR.
4092  */
4093 struct ALT_CLKMGR_MAINPLL_BYPASSR_s
4094 {
4095  uint32_t mpu : 1; /* MPU Bypass */
4096  uint32_t noc : 1; /* NOC Bypass */
4097  uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
4098  uint32_t hmcpllref : 1; /* HMC PLL Reference Bypass */
4099  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
4100  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
4101  uint32_t : 26; /* *UNDEFINED* */
4102 };
4103 
4104 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASSR. */
4105 typedef volatile struct ALT_CLKMGR_MAINPLL_BYPASSR_s ALT_CLKMGR_MAINPLL_BYPASSR_t;
4106 #endif /* __ASSEMBLY__ */
4107 
4108 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR register. */
4109 #define ALT_CLKMGR_MAINPLL_BYPASSR_RESET 0x0000003f
4110 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASSR register from the beginning of the component. */
4111 #define ALT_CLKMGR_MAINPLL_BYPASSR_OFST 0x1c
4112 
4113 /*
4114  * Register : Main PLL Control Register for MPU Clock Group. - mpuclk
4115  *
4116  * Contains settings that control clock mpu_clk generated from the Main PLL VCO
4117  * clock.
4118  *
4119  * Register Layout
4120  *
4121  * Bits | Access | Reset | Description
4122  * :--------|:-------|:------|:------------------------------
4123  * [10:0] | RW | 0x0 | Counter
4124  * [15:11] | ??? | 0x0 | *UNDEFINED*
4125  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4126  * [31:19] | ??? | 0x0 | *UNDEFINED*
4127  *
4128  */
4129 /*
4130  * Field : Counter - cnt
4131  *
4132  * Divides the VCO/2 frequency by the value+1 in this field.
4133  *
4134  * Field Access Macros:
4135  *
4136  */
4137 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
4138 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
4139 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
4140 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 10
4141 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
4142 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 11
4143 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
4144 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000007ff
4145 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
4146 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffff800
4147 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
4148 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
4149 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */
4150 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4151 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */
4152 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4153 
4154 /*
4155  * Field : src
4156  *
4157  * Selects the source for the active 5:1 clock selection when the PLL is not
4158  * bypassed.
4159  *
4160  * Field Enumeration Values:
4161  *
4162  * Enum | Value | Description
4163  * :---------------------------------------|:------|:------------
4164  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_MAIN | 0x0 |
4165  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_PERI | 0x1 |
4166  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_OSC1 | 0x2 |
4167  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_INTOSC | 0x3 |
4168  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_FPGA | 0x4 |
4169  *
4170  * Field Access Macros:
4171  *
4172  */
4173 /*
4174  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4175  *
4176  */
4177 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_MAIN 0x0
4178 /*
4179  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4180  *
4181  */
4182 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_PERI 0x1
4183 /*
4184  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4185  *
4186  */
4187 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_OSC1 0x2
4188 /*
4189  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4190  *
4191  */
4192 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_INTOSC 0x3
4193 /*
4194  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
4195  *
4196  */
4197 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_FPGA 0x4
4198 
4199 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
4200 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
4201 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
4202 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_MSB 18
4203 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
4204 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_WIDTH 3
4205 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value. */
4206 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET_MSK 0x00070000
4207 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value. */
4208 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_CLR_MSK 0xfff8ffff
4209 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
4210 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_RESET 0x0
4211 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_SRC field value from a register. */
4212 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4213 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value suitable for setting the register. */
4214 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4215 
4216 #ifndef __ASSEMBLY__
4217 /*
4218  * WARNING: The C register and register group struct declarations are provided for
4219  * convenience and illustrative purposes. They should, however, be used with
4220  * caution as the C language standard provides no guarantees about the alignment or
4221  * atomicity of device memory accesses. The recommended practice for writing
4222  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4223  * alt_write_word() functions.
4224  *
4225  * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK.
4226  */
4227 struct ALT_CLKMGR_MAINPLL_MPUCLK_s
4228 {
4229  uint32_t cnt : 11; /* Counter */
4230  uint32_t : 5; /* *UNDEFINED* */
4231  uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_MPUCLK_SRC */
4232  uint32_t : 13; /* *UNDEFINED* */
4233 };
4234 
4235 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */
4236 typedef volatile struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t;
4237 #endif /* __ASSEMBLY__ */
4238 
4239 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK register. */
4240 #define ALT_CLKMGR_MAINPLL_MPUCLK_RESET 0x00000000
4241 /* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */
4242 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x20
4243 
4244 /*
4245  * Register : Main PLL Control Register for NOC Clock Group. - nocclk
4246  *
4247  * Contains settings that control clock main_clk generated from the Main PLL VCO
4248  * clock.
4249  *
4250  * Register Layout
4251  *
4252  * Bits | Access | Reset | Description
4253  * :--------|:-------|:------|:------------------------------
4254  * [10:0] | RW | 0x0 | Counter
4255  * [15:11] | ??? | 0x0 | *UNDEFINED*
4256  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4257  * [31:19] | ??? | 0x0 | *UNDEFINED*
4258  *
4259  */
4260 /*
4261  * Field : Counter - cnt
4262  *
4263  * Divides the VCO frequency by the value+1 in this field.
4264  *
4265  * Field Access Macros:
4266  *
4267  */
4268 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
4269 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_LSB 0
4270 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
4271 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_MSB 10
4272 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
4273 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_WIDTH 11
4274 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value. */
4275 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET_MSK 0x000007ff
4276 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value. */
4277 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_CLR_MSK 0xfffff800
4278 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
4279 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_RESET 0x0
4280 /* Extracts the ALT_CLKMGR_MAINPLL_NOCCLK_CNT field value from a register. */
4281 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4282 /* Produces a ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value suitable for setting the register. */
4283 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4284 
4285 /*
4286  * Field : src
4287  *
4288  * Selects the source for the active 5:1 clock selection when the PLL is not
4289  * bypassed.
4290  *
4291  * Field Enumeration Values:
4292  *
4293  * Enum | Value | Description
4294  * :---------------------------------------|:------|:------------
4295  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_MAIN | 0x0 |
4296  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_PERI | 0x1 |
4297  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_OSC1 | 0x2 |
4298  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_INTOSC | 0x3 |
4299  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_FPGA | 0x4 |
4300  *
4301  * Field Access Macros:
4302  *
4303  */
4304 /*
4305  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4306  *
4307  */
4308 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_MAIN 0x0
4309 /*
4310  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4311  *
4312  */
4313 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_PERI 0x1
4314 /*
4315  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4316  *
4317  */
4318 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_OSC1 0x2
4319 /*
4320  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4321  *
4322  */
4323 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_INTOSC 0x3
4324 /*
4325  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
4326  *
4327  */
4328 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_FPGA 0x4
4329 
4330 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
4331 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
4332 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
4333 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_MSB 18
4334 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
4335 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_WIDTH 3
4336 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value. */
4337 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET_MSK 0x00070000
4338 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value. */
4339 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_CLR_MSK 0xfff8ffff
4340 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
4341 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_RESET 0x0
4342 /* Extracts the ALT_CLKMGR_MAINPLL_NOCCLK_SRC field value from a register. */
4343 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4344 /* Produces a ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value suitable for setting the register. */
4345 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4346 
4347 #ifndef __ASSEMBLY__
4348 /*
4349  * WARNING: The C register and register group struct declarations are provided for
4350  * convenience and illustrative purposes. They should, however, be used with
4351  * caution as the C language standard provides no guarantees about the alignment or
4352  * atomicity of device memory accesses. The recommended practice for writing
4353  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4354  * alt_write_word() functions.
4355  *
4356  * The struct declaration for register ALT_CLKMGR_MAINPLL_NOCCLK.
4357  */
4358 struct ALT_CLKMGR_MAINPLL_NOCCLK_s
4359 {
4360  uint32_t cnt : 11; /* Counter */
4361  uint32_t : 5; /* *UNDEFINED* */
4362  uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_NOCCLK_SRC */
4363  uint32_t : 13; /* *UNDEFINED* */
4364 };
4365 
4366 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_NOCCLK. */
4367 typedef volatile struct ALT_CLKMGR_MAINPLL_NOCCLK_s ALT_CLKMGR_MAINPLL_NOCCLK_t;
4368 #endif /* __ASSEMBLY__ */
4369 
4370 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK register. */
4371 #define ALT_CLKMGR_MAINPLL_NOCCLK_RESET 0x00000000
4372 /* The byte offset of the ALT_CLKMGR_MAINPLL_NOCCLK register from the beginning of the component. */
4373 #define ALT_CLKMGR_MAINPLL_NOCCLK_OFST 0x24
4374 
4375 /*
4376  * Register : Main PLL Control Register for Counter 2 Clock - cntr2clk
4377  *
4378  * Contains settings that control Couner 2 clock generated from the Main PLL VCO
4379  * clock.
4380  *
4381  * Register Layout
4382  *
4383  * Bits | Access | Reset | Description
4384  * :--------|:-------|:------|:------------
4385  * [10:0] | RW | 0x0 | Counter
4386  * [31:11] | ??? | 0x0 | *UNDEFINED*
4387  *
4388  */
4389 /*
4390  * Field : Counter - cnt
4391  *
4392  * Divides the VCO frequency by the value+1 in this field.
4393  *
4394  * Field Access Macros:
4395  *
4396  */
4397 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
4398 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_LSB 0
4399 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
4400 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_MSB 10
4401 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
4402 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_WIDTH 11
4403 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value. */
4404 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
4405 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value. */
4406 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
4407 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
4408 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_RESET 0x0
4409 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT field value from a register. */
4410 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4411 /* Produces a ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value suitable for setting the register. */
4412 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4413 
4414 #ifndef __ASSEMBLY__
4415 /*
4416  * WARNING: The C register and register group struct declarations are provided for
4417  * convenience and illustrative purposes. They should, however, be used with
4418  * caution as the C language standard provides no guarantees about the alignment or
4419  * atomicity of device memory accesses. The recommended practice for writing
4420  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4421  * alt_write_word() functions.
4422  *
4423  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR2CLK.
4424  */
4425 struct ALT_CLKMGR_MAINPLL_CNTR2CLK_s
4426 {
4427  uint32_t cnt : 11; /* Counter */
4428  uint32_t : 21; /* *UNDEFINED* */
4429 };
4430 
4431 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR2CLK. */
4432 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR2CLK_s ALT_CLKMGR_MAINPLL_CNTR2CLK_t;
4433 #endif /* __ASSEMBLY__ */
4434 
4435 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR2CLK register. */
4436 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_RESET 0x00000000
4437 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR2CLK register from the beginning of the component. */
4438 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_OFST 0x28
4439 
4440 /*
4441  * Register : Main PLL Control Register for Counter 3 Clock - cntr3clk
4442  *
4443  * Contains settings that control Couner 3 clock generated from the Main PLL VCO
4444  * clock.
4445  *
4446  * Register Layout
4447  *
4448  * Bits | Access | Reset | Description
4449  * :--------|:-------|:------|:------------
4450  * [10:0] | RW | 0x0 | Counter
4451  * [31:11] | ??? | 0x0 | *UNDEFINED*
4452  *
4453  */
4454 /*
4455  * Field : Counter - cnt
4456  *
4457  * Divides the VCO frequency by the value+1 in this field.
4458  *
4459  * Field Access Macros:
4460  *
4461  */
4462 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
4463 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_LSB 0
4464 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
4465 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_MSB 10
4466 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
4467 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_WIDTH 11
4468 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value. */
4469 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
4470 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value. */
4471 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
4472 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
4473 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_RESET 0x0
4474 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT field value from a register. */
4475 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4476 /* Produces a ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value suitable for setting the register. */
4477 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4478 
4479 #ifndef __ASSEMBLY__
4480 /*
4481  * WARNING: The C register and register group struct declarations are provided for
4482  * convenience and illustrative purposes. They should, however, be used with
4483  * caution as the C language standard provides no guarantees about the alignment or
4484  * atomicity of device memory accesses. The recommended practice for writing
4485  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4486  * alt_write_word() functions.
4487  *
4488  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR3CLK.
4489  */
4490 struct ALT_CLKMGR_MAINPLL_CNTR3CLK_s
4491 {
4492  uint32_t cnt : 11; /* Counter */
4493  uint32_t : 21; /* *UNDEFINED* */
4494 };
4495 
4496 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR3CLK. */
4497 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR3CLK_s ALT_CLKMGR_MAINPLL_CNTR3CLK_t;
4498 #endif /* __ASSEMBLY__ */
4499 
4500 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR3CLK register. */
4501 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_RESET 0x00000000
4502 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR3CLK register from the beginning of the component. */
4503 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_OFST 0x2c
4504 
4505 /*
4506  * Register : Main PLL Control Register for Counter 4 Clock - cntr4clk
4507  *
4508  * Contains settings that control Couner 4 clock generated from the Main PLL VCO
4509  * clock.
4510  *
4511  * Register Layout
4512  *
4513  * Bits | Access | Reset | Description
4514  * :--------|:-------|:------|:------------
4515  * [10:0] | RW | 0x0 | Counter
4516  * [31:11] | ??? | 0x0 | *UNDEFINED*
4517  *
4518  */
4519 /*
4520  * Field : Counter - cnt
4521  *
4522  * Divides the VCO frequency by the value+1 in this field.
4523  *
4524  * Field Access Macros:
4525  *
4526  */
4527 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
4528 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_LSB 0
4529 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
4530 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_MSB 10
4531 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
4532 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_WIDTH 11
4533 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value. */
4534 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
4535 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value. */
4536 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
4537 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
4538 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_RESET 0x0
4539 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT field value from a register. */
4540 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4541 /* Produces a ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value suitable for setting the register. */
4542 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4543 
4544 #ifndef __ASSEMBLY__
4545 /*
4546  * WARNING: The C register and register group struct declarations are provided for
4547  * convenience and illustrative purposes. They should, however, be used with
4548  * caution as the C language standard provides no guarantees about the alignment or
4549  * atomicity of device memory accesses. The recommended practice for writing
4550  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4551  * alt_write_word() functions.
4552  *
4553  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR4CLK.
4554  */
4555 struct ALT_CLKMGR_MAINPLL_CNTR4CLK_s
4556 {
4557  uint32_t cnt : 11; /* Counter */
4558  uint32_t : 21; /* *UNDEFINED* */
4559 };
4560 
4561 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR4CLK. */
4562 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR4CLK_s ALT_CLKMGR_MAINPLL_CNTR4CLK_t;
4563 #endif /* __ASSEMBLY__ */
4564 
4565 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR4CLK register. */
4566 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_RESET 0x00000000
4567 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR4CLK register from the beginning of the component. */
4568 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_OFST 0x30
4569 
4570 /*
4571  * Register : Main PLL Control Register for Counter 5 Clock - cntr5clk
4572  *
4573  * Contains settings that control Couner 5 clock generated from the Main PLL VCO
4574  * clock.
4575  *
4576  * Register Layout
4577  *
4578  * Bits | Access | Reset | Description
4579  * :--------|:-------|:------|:------------
4580  * [10:0] | RW | 0x0 | Counter
4581  * [31:11] | ??? | 0x0 | *UNDEFINED*
4582  *
4583  */
4584 /*
4585  * Field : Counter - cnt
4586  *
4587  * Divides the VCO frequency by the value+1 in this field.
4588  *
4589  * Field Access Macros:
4590  *
4591  */
4592 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
4593 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_LSB 0
4594 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
4595 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_MSB 10
4596 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
4597 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_WIDTH 11
4598 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value. */
4599 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
4600 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value. */
4601 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
4602 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
4603 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_RESET 0x0
4604 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT field value from a register. */
4605 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4606 /* Produces a ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value suitable for setting the register. */
4607 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4608 
4609 #ifndef __ASSEMBLY__
4610 /*
4611  * WARNING: The C register and register group struct declarations are provided for
4612  * convenience and illustrative purposes. They should, however, be used with
4613  * caution as the C language standard provides no guarantees about the alignment or
4614  * atomicity of device memory accesses. The recommended practice for writing
4615  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4616  * alt_write_word() functions.
4617  *
4618  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR5CLK.
4619  */
4620 struct ALT_CLKMGR_MAINPLL_CNTR5CLK_s
4621 {
4622  uint32_t cnt : 11; /* Counter */
4623  uint32_t : 21; /* *UNDEFINED* */
4624 };
4625 
4626 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR5CLK. */
4627 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR5CLK_s ALT_CLKMGR_MAINPLL_CNTR5CLK_t;
4628 #endif /* __ASSEMBLY__ */
4629 
4630 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR5CLK register. */
4631 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_RESET 0x00000000
4632 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR5CLK register from the beginning of the component. */
4633 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_OFST 0x34
4634 
4635 /*
4636  * Register : Main PLL Control Register for Counter 6 Clock - cntr6clk
4637  *
4638  * Contains settings that control Couner 6 clock generated from the Main PLL VCO
4639  * clock.
4640  *
4641  * Register Layout
4642  *
4643  * Bits | Access | Reset | Description
4644  * :--------|:-------|:------|:------------
4645  * [10:0] | RW | 0x0 | Counter
4646  * [31:11] | ??? | 0x0 | *UNDEFINED*
4647  *
4648  */
4649 /*
4650  * Field : Counter - cnt
4651  *
4652  * Divides the VCO frequency by the value+1 in this field.
4653  *
4654  * Field Access Macros:
4655  *
4656  */
4657 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
4658 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_LSB 0
4659 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
4660 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_MSB 10
4661 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
4662 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_WIDTH 11
4663 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value. */
4664 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
4665 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value. */
4666 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
4667 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
4668 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_RESET 0x0
4669 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT field value from a register. */
4670 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4671 /* Produces a ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value suitable for setting the register. */
4672 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4673 
4674 #ifndef __ASSEMBLY__
4675 /*
4676  * WARNING: The C register and register group struct declarations are provided for
4677  * convenience and illustrative purposes. They should, however, be used with
4678  * caution as the C language standard provides no guarantees about the alignment or
4679  * atomicity of device memory accesses. The recommended practice for writing
4680  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4681  * alt_write_word() functions.
4682  *
4683  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR6CLK.
4684  */
4685 struct ALT_CLKMGR_MAINPLL_CNTR6CLK_s
4686 {
4687  uint32_t cnt : 11; /* Counter */
4688  uint32_t : 21; /* *UNDEFINED* */
4689 };
4690 
4691 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR6CLK. */
4692 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR6CLK_s ALT_CLKMGR_MAINPLL_CNTR6CLK_t;
4693 #endif /* __ASSEMBLY__ */
4694 
4695 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR6CLK register. */
4696 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_RESET 0x00000000
4697 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR6CLK register from the beginning of the component. */
4698 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_OFST 0x38
4699 
4700 /*
4701  * Register : Main PLL Control Register for Counter 7 Clock - cntr7clk
4702  *
4703  * Contains settings that control Couner 7 clock generated from the Main PLL VCO
4704  * clock.
4705  *
4706  * Register Layout
4707  *
4708  * Bits | Access | Reset | Description
4709  * :--------|:-------|:------|:--------------------------------
4710  * [10:0] | RW | 0x0 | Counter
4711  * [15:11] | ??? | 0x0 | *UNDEFINED*
4712  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4713  * [31:19] | ??? | 0x0 | *UNDEFINED*
4714  *
4715  */
4716 /*
4717  * Field : Counter - cnt
4718  *
4719  * Divides the VCO frequency by the value+1 in this field.
4720  *
4721  * Field Access Macros:
4722  *
4723  */
4724 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
4725 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_LSB 0
4726 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
4727 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_MSB 10
4728 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
4729 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_WIDTH 11
4730 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value. */
4731 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
4732 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value. */
4733 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
4734 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
4735 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_RESET 0x0
4736 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT field value from a register. */
4737 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4738 /* Produces a ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value suitable for setting the register. */
4739 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4740 
4741 /*
4742  * Field : src
4743  *
4744  * Selects the source for the active 5:1 clock selection when the PLL is not
4745  * bypassed.
4746  *
4747  * Field Enumeration Values:
4748  *
4749  * Enum | Value | Description
4750  * :-----------------------------------------|:------|:------------
4751  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_MAIN | 0x0 |
4752  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_PERI | 0x1 |
4753  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_OSC1 | 0x2 |
4754  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_INTOSC | 0x3 |
4755  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_FPGA | 0x4 |
4756  *
4757  * Field Access Macros:
4758  *
4759  */
4760 /*
4761  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4762  *
4763  */
4764 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_MAIN 0x0
4765 /*
4766  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4767  *
4768  */
4769 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_PERI 0x1
4770 /*
4771  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4772  *
4773  */
4774 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_OSC1 0x2
4775 /*
4776  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4777  *
4778  */
4779 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_INTOSC 0x3
4780 /*
4781  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
4782  *
4783  */
4784 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_FPGA 0x4
4785 
4786 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
4787 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
4788 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
4789 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_MSB 18
4790 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
4791 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_WIDTH 3
4792 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value. */
4793 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET_MSK 0x00070000
4794 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value. */
4795 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_CLR_MSK 0xfff8ffff
4796 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
4797 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_RESET 0x0
4798 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC field value from a register. */
4799 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4800 /* Produces a ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value suitable for setting the register. */
4801 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4802 
4803 #ifndef __ASSEMBLY__
4804 /*
4805  * WARNING: The C register and register group struct declarations are provided for
4806  * convenience and illustrative purposes. They should, however, be used with
4807  * caution as the C language standard provides no guarantees about the alignment or
4808  * atomicity of device memory accesses. The recommended practice for writing
4809  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4810  * alt_write_word() functions.
4811  *
4812  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR7CLK.
4813  */
4814 struct ALT_CLKMGR_MAINPLL_CNTR7CLK_s
4815 {
4816  uint32_t cnt : 11; /* Counter */
4817  uint32_t : 5; /* *UNDEFINED* */
4818  uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC */
4819  uint32_t : 13; /* *UNDEFINED* */
4820 };
4821 
4822 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR7CLK. */
4823 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR7CLK_s ALT_CLKMGR_MAINPLL_CNTR7CLK_t;
4824 #endif /* __ASSEMBLY__ */
4825 
4826 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK register. */
4827 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_RESET 0x00000000
4828 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR7CLK register from the beginning of the component. */
4829 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_OFST 0x3c
4830 
4831 /*
4832  * Register : Main PLL Control Register for Counter 8 Clock - cntr8clk
4833  *
4834  * Contains settings that control Couner 8 clock generated from the Main PLL VCO
4835  * clock.
4836  *
4837  * Register Layout
4838  *
4839  * Bits | Access | Reset | Description
4840  * :--------|:-------|:------|:------------
4841  * [10:0] | RW | 0x0 | Counter
4842  * [31:11] | ??? | 0x0 | *UNDEFINED*
4843  *
4844  */
4845 /*
4846  * Field : Counter - cnt
4847  *
4848  * Divides the VCO frequency by the value+1 in this field.
4849  *
4850  * Field Access Macros:
4851  *
4852  */
4853 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
4854 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_LSB 0
4855 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
4856 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_MSB 10
4857 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
4858 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_WIDTH 11
4859 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value. */
4860 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
4861 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value. */
4862 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
4863 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
4864 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_RESET 0x0
4865 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT field value from a register. */
4866 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4867 /* Produces a ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value suitable for setting the register. */
4868 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4869 
4870 #ifndef __ASSEMBLY__
4871 /*
4872  * WARNING: The C register and register group struct declarations are provided for
4873  * convenience and illustrative purposes. They should, however, be used with
4874  * caution as the C language standard provides no guarantees about the alignment or
4875  * atomicity of device memory accesses. The recommended practice for writing
4876  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4877  * alt_write_word() functions.
4878  *
4879  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR8CLK.
4880  */
4881 struct ALT_CLKMGR_MAINPLL_CNTR8CLK_s
4882 {
4883  uint32_t cnt : 11; /* Counter */
4884  uint32_t : 21; /* *UNDEFINED* */
4885 };
4886 
4887 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR8CLK. */
4888 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR8CLK_s ALT_CLKMGR_MAINPLL_CNTR8CLK_t;
4889 #endif /* __ASSEMBLY__ */
4890 
4891 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR8CLK register. */
4892 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_RESET 0x00000000
4893 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR8CLK register from the beginning of the component. */
4894 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_OFST 0x40
4895 
4896 /*
4897  * Register : Main PLL Control Register for Counter 9 Clock - cntr9clk
4898  *
4899  * Contains settings that control Couner 9 clock generated from the Main PLL VCO
4900  * clock.
4901  *
4902  * Register Layout
4903  *
4904  * Bits | Access | Reset | Description
4905  * :--------|:-------|:------|:--------------------------------
4906  * [10:0] | RW | 0x0 | Counter
4907  * [15:11] | ??? | 0x0 | *UNDEFINED*
4908  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4909  * [31:19] | ??? | 0x0 | *UNDEFINED*
4910  *
4911  */
4912 /*
4913  * Field : Counter - cnt
4914  *
4915  * Divides the VCO frequency by the value+1 in this field.
4916  *
4917  * Field Access Macros:
4918  *
4919  */
4920 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
4921 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_LSB 0
4922 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
4923 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_MSB 10
4924 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
4925 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_WIDTH 11
4926 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value. */
4927 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
4928 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value. */
4929 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
4930 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
4931 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_RESET 0x0
4932 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT field value from a register. */
4933 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4934 /* Produces a ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value suitable for setting the register. */
4935 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4936 
4937 /*
4938  * Field : src
4939  *
4940  * Selects the source for the active 5:1 clock selection when the PLL is not
4941  * bypassed.
4942  *
4943  * Field Enumeration Values:
4944  *
4945  * Enum | Value | Description
4946  * :-----------------------------------------|:------|:------------
4947  * ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_MAIN | 0x0 |
4948  * ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_PERI | 0x1 |
4949  * ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_OSC1 | 0x2 |
4950  * ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_INTOSC | 0x3 |
4951  * ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_FPGA | 0x4 |
4952  *
4953  * Field Access Macros:
4954  *
4955  */
4956 /*
4957  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4958  *
4959  */
4960 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_MAIN 0x0
4961 /*
4962  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4963  *
4964  */
4965 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_PERI 0x1
4966 /*
4967  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4968  *
4969  */
4970 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_OSC1 0x2
4971 /*
4972  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4973  *
4974  */
4975 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_INTOSC 0x3
4976 /*
4977  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC
4978  *
4979  */
4980 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_FPGA 0x4
4981 
4982 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field. */
4983 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
4984 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field. */
4985 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_MSB 18
4986 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field. */
4987 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_WIDTH 3
4988 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field value. */
4989 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_SET_MSK 0x00070000
4990 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field value. */
4991 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_CLR_MSK 0xfff8ffff
4992 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field. */
4993 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_RESET 0x0
4994 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC field value from a register. */
4995 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4996 /* Produces a ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC register field value suitable for setting the register. */
4997 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4998 
4999 #ifndef __ASSEMBLY__
5000 /*
5001  * WARNING: The C register and register group struct declarations are provided for
5002  * convenience and illustrative purposes. They should, however, be used with
5003  * caution as the C language standard provides no guarantees about the alignment or
5004  * atomicity of device memory accesses. The recommended practice for writing
5005  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5006  * alt_write_word() functions.
5007  *
5008  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR9CLK.
5009  */
5010 struct ALT_CLKMGR_MAINPLL_CNTR9CLK_s
5011 {
5012  uint32_t cnt : 11; /* Counter */
5013  uint32_t : 5; /* *UNDEFINED* */
5014  uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC */
5015  uint32_t : 13; /* *UNDEFINED* */
5016 };
5017 
5018 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR9CLK. */
5019 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR9CLK_s ALT_CLKMGR_MAINPLL_CNTR9CLK_t;
5020 #endif /* __ASSEMBLY__ */
5021 
5022 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR9CLK register. */
5023 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_RESET 0x00000000
5024 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR9CLK register from the beginning of the component. */
5025 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_OFST 0x44
5026 
5027 /*
5028  * Register : Main PLL Control Register for Counter 15 Clock - cntr15clk
5029  *
5030  * Contains settings that control Couner 15 clock generated from the Main PLL VCO
5031  * clock.
5032  *
5033  * Register Layout
5034  *
5035  * Bits | Access | Reset | Description
5036  * :--------|:-------|:------|:------------
5037  * [10:0] | RW | 0x0 | Counter
5038  * [31:11] | ??? | 0x0 | *UNDEFINED*
5039  *
5040  */
5041 /*
5042  * Field : Counter - cnt
5043  *
5044  * Divides the VCO frequency by the value+1 in this field.
5045  *
5046  * Field Access Macros:
5047  *
5048  */
5049 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field. */
5050 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_LSB 0
5051 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field. */
5052 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_MSB 10
5053 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field. */
5054 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_WIDTH 11
5055 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field value. */
5056 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_SET_MSK 0x000007ff
5057 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field value. */
5058 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_CLR_MSK 0xfffff800
5059 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field. */
5060 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_RESET 0x0
5061 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT field value from a register. */
5062 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
5063 /* Produces a ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT register field value suitable for setting the register. */
5064 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
5065 
5066 #ifndef __ASSEMBLY__
5067 /*
5068  * WARNING: The C register and register group struct declarations are provided for
5069  * convenience and illustrative purposes. They should, however, be used with
5070  * caution as the C language standard provides no guarantees about the alignment or
5071  * atomicity of device memory accesses. The recommended practice for writing
5072  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5073  * alt_write_word() functions.
5074  *
5075  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR15CLK.
5076  */
5077 struct ALT_CLKMGR_MAINPLL_CNTR15CLK_s
5078 {
5079  uint32_t cnt : 11; /* Counter */
5080  uint32_t : 21; /* *UNDEFINED* */
5081 };
5082 
5083 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR15CLK. */
5084 typedef volatile struct ALT_CLKMGR_MAINPLL_CNTR15CLK_s ALT_CLKMGR_MAINPLL_CNTR15CLK_t;
5085 #endif /* __ASSEMBLY__ */
5086 
5087 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR15CLK register. */
5088 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_RESET 0x00000000
5089 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR15CLK register from the beginning of the component. */
5090 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_OFST 0x5c
5091 
5092 /*
5093  * Register : Main PLL Output Counter Reset Register - outrst
5094  *
5095  * Contains settings to assert individual Outreset for all Main PLL Counters.
5096  *
5097  * Register Layout
5098  *
5099  * Bits | Access | Reset | Description
5100  * :--------|:-------|:------|:---------------------
5101  * [15:0] | RW | 0x0 | Output Counter Reset
5102  * [31:16] | ??? | 0x0 | *UNDEFINED*
5103  *
5104  */
5105 /*
5106  * Field : Output Counter Reset - outreset
5107  *
5108  * Resets the individual PLL output counter.
5109  *
5110  * For software to change the PLL output counter without producing glitches on the
5111  * respective clock, SW must set the Output Counter Reset Register 'Output Counter
5112  * Reset' bit. Software then polls the respective Output Counter Reset Acknowledge
5113  * bit in the Output Counter Reset Ack Status Register. Software then writes the
5114  * appropriate counter register, and then clears the respective Output Counter
5115  * Reset bit.
5116  *
5117  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
5118  *
5119  * If set to '1', reset output divider, no clock output from counter.
5120  *
5121  * If set to '0', counter is not reset.
5122  *
5123  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5124  * on this bit.
5125  *
5126  * Field Access Macros:
5127  *
5128  */
5129 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field. */
5130 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_LSB 0
5131 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field. */
5132 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_MSB 15
5133 /* The width in bits of the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field. */
5134 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_WIDTH 16
5135 /* The mask used to set the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field value. */
5136 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_SET_MSK 0x0000ffff
5137 /* The mask used to clear the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field value. */
5138 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_CLR_MSK 0xffff0000
5139 /* The reset value of the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field. */
5140 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_RESET 0x0
5141 /* Extracts the ALT_CLKMGR_MAINPLL_OUTRST_OUTRST field value from a register. */
5142 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_GET(value) (((value) & 0x0000ffff) >> 0)
5143 /* Produces a ALT_CLKMGR_MAINPLL_OUTRST_OUTRST register field value suitable for setting the register. */
5144 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_SET(value) (((value) << 0) & 0x0000ffff)
5145 
5146 #ifndef __ASSEMBLY__
5147 /*
5148  * WARNING: The C register and register group struct declarations are provided for
5149  * convenience and illustrative purposes. They should, however, be used with
5150  * caution as the C language standard provides no guarantees about the alignment or
5151  * atomicity of device memory accesses. The recommended practice for writing
5152  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5153  * alt_write_word() functions.
5154  *
5155  * The struct declaration for register ALT_CLKMGR_MAINPLL_OUTRST.
5156  */
5157 struct ALT_CLKMGR_MAINPLL_OUTRST_s
5158 {
5159  uint32_t outreset : 16; /* Output Counter Reset */
5160  uint32_t : 16; /* *UNDEFINED* */
5161 };
5162 
5163 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_OUTRST. */
5164 typedef volatile struct ALT_CLKMGR_MAINPLL_OUTRST_s ALT_CLKMGR_MAINPLL_OUTRST_t;
5165 #endif /* __ASSEMBLY__ */
5166 
5167 /* The reset value of the ALT_CLKMGR_MAINPLL_OUTRST register. */
5168 #define ALT_CLKMGR_MAINPLL_OUTRST_RESET 0x00000000
5169 /* The byte offset of the ALT_CLKMGR_MAINPLL_OUTRST register from the beginning of the component. */
5170 #define ALT_CLKMGR_MAINPLL_OUTRST_OFST 0x60
5171 
5172 /*
5173  * Register : Main PLL Output Counter Reset Ack Status Register - outrststat
5174  *
5175  * Contains Output Clock Counter Reset acknowledge status.
5176  *
5177  * Register Layout
5178  *
5179  * Bits | Access | Reset | Description
5180  * :--------|:-------|:------|:---------------------------------
5181  * [15:0] | R | 0x0 | Output Counter Reset Acknowledge
5182  * [31:16] | ??? | 0x0 | *UNDEFINED*
5183  *
5184  */
5185 /*
5186  * Field : Output Counter Reset Acknowledge - outresetack
5187  *
5188  * These read only bits per PLL output indicate that the PLL has received the
5189  * Output Reset Counter request and has gracefully stopped the respective PLL
5190  * output clock.
5191  *
5192  * For software to change the PLL output counter without producing glitches on the
5193  * respective clock, SW must set the Output Counter Reset Register 'Output Counter
5194  * Reset' bit. Software then polls the respective Output Counter Reset Acknowledge
5195  * bit in the Output Counter Reset Ack Status Register. Software then writes the
5196  * appropriate counter register, and then clears the respective Output Counter
5197  * Reset bit.
5198  *
5199  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5200  * on this bit.
5201  *
5202  * Field Enumeration Values:
5203  *
5204  * Enum | Value | Description
5205  * :--------------------------------------------------|:------|:-------------------------------------
5206  * ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE | 0x0 | Idle
5207  * ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
5208  *
5209  * Field Access Macros:
5210  *
5211  */
5212 /*
5213  * Enumerated value for register field ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK
5214  *
5215  * Idle
5216  */
5217 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE 0x0
5218 /*
5219  * Enumerated value for register field ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK
5220  *
5221  * Output Counter Acknowledge received.
5222  */
5223 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD 0x1
5224 
5225 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field. */
5226 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_LSB 0
5227 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field. */
5228 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_MSB 15
5229 /* The width in bits of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field. */
5230 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_WIDTH 16
5231 /* The mask used to set the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field value. */
5232 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_SET_MSK 0x0000ffff
5233 /* The mask used to clear the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field value. */
5234 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_CLR_MSK 0xffff0000
5235 /* The reset value of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field. */
5236 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_RESET 0x0
5237 /* Extracts the ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK field value from a register. */
5238 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_GET(value) (((value) & 0x0000ffff) >> 0)
5239 /* Produces a ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK register field value suitable for setting the register. */
5240 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000ffff)
5241 
5242 #ifndef __ASSEMBLY__
5243 /*
5244  * WARNING: The C register and register group struct declarations are provided for
5245  * convenience and illustrative purposes. They should, however, be used with
5246  * caution as the C language standard provides no guarantees about the alignment or
5247  * atomicity of device memory accesses. The recommended practice for writing
5248  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5249  * alt_write_word() functions.
5250  *
5251  * The struct declaration for register ALT_CLKMGR_MAINPLL_OUTRSTSTAT.
5252  */
5253 struct ALT_CLKMGR_MAINPLL_OUTRSTSTAT_s
5254 {
5255  const uint32_t outresetack : 16; /* Output Counter Reset Acknowledge */
5256  uint32_t : 16; /* *UNDEFINED* */
5257 };
5258 
5259 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_OUTRSTSTAT. */
5260 typedef volatile struct ALT_CLKMGR_MAINPLL_OUTRSTSTAT_s ALT_CLKMGR_MAINPLL_OUTRSTSTAT_t;
5261 #endif /* __ASSEMBLY__ */
5262 
5263 /* The reset value of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT register. */
5264 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_RESET 0x00000000
5265 /* The byte offset of the ALT_CLKMGR_MAINPLL_OUTRSTSTAT register from the beginning of the component. */
5266 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OFST 0x64
5267 
5268 /*
5269  * Register : NoC Divide Register - nocdiv
5270  *
5271  * Contains fields that control clock dividers for NoC Clocks.
5272  *
5273  * Register Layout
5274  *
5275  * Bits | Access | Reset | Description
5276  * :--------|:-------|:------|:----------------------------------------
5277  * [1:0] | RW | 0x0 | L4 Main Clock Divider
5278  * [7:2] | ??? | 0x0 | *UNDEFINED*
5279  * [9:8] | RW | 0x1 | L4 MP Clock Divider
5280  * [15:10] | ??? | 0x0 | *UNDEFINED*
5281  * [17:16] | RW | 0x2 | L4 SP Clock Divider
5282  * [23:18] | ??? | 0x0 | *UNDEFINED*
5283  * [25:24] | RW | 0x0 | CoreSight Trace Clock Divider
5284  * [27:26] | RW | 0x2 | CoreSight Trace Interface Clock Divider
5285  * [28] | RW | 0x1 | CoreSight Debug Clock Divider
5286  * [31:29] | ??? | 0x0 | *UNDEFINED*
5287  *
5288  */
5289 /*
5290  * Field : L4 Main Clock Divider - l4mainclk
5291  *
5292  * The external l4_main_clk divider is specified in this field.
5293  *
5294  * Field Enumeration Values:
5295  *
5296  * Enum | Value | Description
5297  * :-------------------------------------------|:------|:------------
5298  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 | 0x0 | Divide By 1
5299  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 | 0x1 | Divide By 2
5300  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 | 0x2 | Divide By 4
5301  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 | 0x3 | Divide By 8
5302  *
5303  * Field Access Macros:
5304  *
5305  */
5306 /*
5307  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
5308  *
5309  * Divide By 1
5310  */
5311 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 0x0
5312 /*
5313  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
5314  *
5315  * Divide By 2
5316  */
5317 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 0x1
5318 /*
5319  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
5320  *
5321  * Divide By 4
5322  */
5323 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 0x2
5324 /*
5325  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
5326  *
5327  * Divide By 8
5328  */
5329 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 0x3
5330 
5331 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
5332 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
5333 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
5334 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_MSB 1
5335 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
5336 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_WIDTH 2
5337 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value. */
5338 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET_MSK 0x00000003
5339 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value. */
5340 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_CLR_MSK 0xfffffffc
5341 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
5342 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_RESET 0x0
5343 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK field value from a register. */
5344 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_GET(value) (((value) & 0x00000003) >> 0)
5345 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value suitable for setting the register. */
5346 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET(value) (((value) << 0) & 0x00000003)
5347 
5348 /*
5349  * Field : L4 MP Clock Divider - l4mpclk
5350  *
5351  * The external l4_mp_clk divider is specified in this field.
5352  *
5353  * Field Enumeration Values:
5354  *
5355  * Enum | Value | Description
5356  * :-----------------------------------------|:------|:------------
5357  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1
5358  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2
5359  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4
5360  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8
5361  *
5362  * Field Access Macros:
5363  *
5364  */
5365 /*
5366  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
5367  *
5368  * Divide By 1
5369  */
5370 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 0x0
5371 /*
5372  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
5373  *
5374  * Divide By 2
5375  */
5376 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 0x1
5377 /*
5378  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
5379  *
5380  * Divide By 4
5381  */
5382 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 0x2
5383 /*
5384  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
5385  *
5386  * Divide By 8
5387  */
5388 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 0x3
5389 
5390 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
5391 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
5392 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
5393 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_MSB 9
5394 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
5395 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_WIDTH 2
5396 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value. */
5397 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET_MSK 0x00000300
5398 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value. */
5399 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_CLR_MSK 0xfffffcff
5400 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
5401 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_RESET 0x1
5402 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK field value from a register. */
5403 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_GET(value) (((value) & 0x00000300) >> 8)
5404 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value suitable for setting the register. */
5405 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET(value) (((value) << 8) & 0x00000300)
5406 
5407 /*
5408  * Field : L4 SP Clock Divider - l4spclk
5409  *
5410  * The external l4_sp_clk divider is specified in this field.
5411  *
5412  * Field Enumeration Values:
5413  *
5414  * Enum | Value | Description
5415  * :-----------------------------------------|:------|:------------
5416  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1
5417  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2
5418  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4
5419  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8
5420  *
5421  * Field Access Macros:
5422  *
5423  */
5424 /*
5425  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
5426  *
5427  * Divide By 1
5428  */
5429 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 0x0
5430 /*
5431  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
5432  *
5433  * Divide By 2
5434  */
5435 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 0x1
5436 /*
5437  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
5438  *
5439  * Divide By 4
5440  */
5441 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 0x2
5442 /*
5443  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
5444  *
5445  * Divide By 8
5446  */
5447 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 0x3
5448 
5449 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
5450 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
5451 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
5452 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_MSB 17
5453 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
5454 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_WIDTH 2
5455 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value. */
5456 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET_MSK 0x00030000
5457 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value. */
5458 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_CLR_MSK 0xfffcffff
5459 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
5460 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_RESET 0x2
5461 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK field value from a register. */
5462 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_GET(value) (((value) & 0x00030000) >> 16)
5463 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value suitable for setting the register. */
5464 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET(value) (((value) << 16) & 0x00030000)
5465 
5466 /*
5467  * Field : CoreSight Trace Clock Divider - csatclk
5468  *
5469  * The external cs_at_clk divider is specified in this field.
5470  *
5471  * Field Enumeration Values:
5472  *
5473  * Enum | Value | Description
5474  * :-----------------------------------------|:------|:------------
5475  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 | 0x0 | Divide By 1
5476  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 | 0x1 | Divide By 2
5477  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 | 0x2 | Divide By 4
5478  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 | 0x3 | Divide By 8
5479  *
5480  * Field Access Macros:
5481  *
5482  */
5483 /*
5484  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
5485  *
5486  * Divide By 1
5487  */
5488 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 0x0
5489 /*
5490  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
5491  *
5492  * Divide By 2
5493  */
5494 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 0x1
5495 /*
5496  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
5497  *
5498  * Divide By 4
5499  */
5500 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 0x2
5501 /*
5502  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
5503  *
5504  * Divide By 8
5505  */
5506 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 0x3
5507 
5508 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
5509 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
5510 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
5511 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_MSB 25
5512 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
5513 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_WIDTH 2
5514 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value. */
5515 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET_MSK 0x03000000
5516 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value. */
5517 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_CLR_MSK 0xfcffffff
5518 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
5519 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_RESET 0x0
5520 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK field value from a register. */
5521 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_GET(value) (((value) & 0x03000000) >> 24)
5522 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value suitable for setting the register. */
5523 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET(value) (((value) << 24) & 0x03000000)
5524 
5525 /*
5526  * Field : CoreSight Trace Interface Clock Divider - cstraceclk
5527  *
5528  * The external cs_trace_clk divider is specified in this field. The cs_trace_clk
5529  * is used by the actual trace interface to the debugger. This divider is cascaded
5530  * after the cs_at_clk external divider.
5531  *
5532  * Field Enumeration Values:
5533  *
5534  * Enum | Value | Description
5535  * :--------------------------------------------|:------|:------------
5536  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 | 0x0 | Divide By 1
5537  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 | 0x1 | Divide By 2
5538  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 | 0x2 | Divide By 4
5539  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 | 0x3 | Divide By 8
5540  *
5541  * Field Access Macros:
5542  *
5543  */
5544 /*
5545  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
5546  *
5547  * Divide By 1
5548  */
5549 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 0x0
5550 /*
5551  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
5552  *
5553  * Divide By 2
5554  */
5555 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 0x1
5556 /*
5557  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
5558  *
5559  * Divide By 4
5560  */
5561 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 0x2
5562 /*
5563  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
5564  *
5565  * Divide By 8
5566  */
5567 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 0x3
5568 
5569 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
5570 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
5571 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
5572 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_MSB 27
5573 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
5574 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_WIDTH 2
5575 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value. */
5576 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET_MSK 0x0c000000
5577 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value. */
5578 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_CLR_MSK 0xf3ffffff
5579 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
5580 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_RESET 0x2
5581 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK field value from a register. */
5582 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_GET(value) (((value) & 0x0c000000) >> 26)
5583 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value suitable for setting the register. */
5584 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET(value) (((value) << 26) & 0x0c000000)
5585 
5586 /*
5587  * Field : CoreSight Debug Clock Divider - cspdbgclk
5588  *
5589  * The external cs_pdbg_clk divider is specified in this field. This divider is
5590  * cascaded after the cs_at_clk external divider.
5591  *
5592  * Field Enumeration Values:
5593  *
5594  * Enum | Value | Description
5595  * :-------------------------------------------|:------|:------------
5596  * ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 | 0x0 | Divide By 1
5597  * ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 | 0x1 | Divide By 4
5598  *
5599  * Field Access Macros:
5600  *
5601  */
5602 /*
5603  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
5604  *
5605  * Divide By 1
5606  */
5607 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 0x0
5608 /*
5609  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
5610  *
5611  * Divide By 4
5612  */
5613 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 0x1
5614 
5615 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
5616 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
5617 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
5618 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_MSB 28
5619 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
5620 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_WIDTH 1
5621 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value. */
5622 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET_MSK 0x10000000
5623 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value. */
5624 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_CLR_MSK 0xefffffff
5625 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
5626 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_RESET 0x1
5627 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK field value from a register. */
5628 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_GET(value) (((value) & 0x10000000) >> 28)
5629 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value suitable for setting the register. */
5630 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET(value) (((value) << 28) & 0x10000000)
5631 
5632 #ifndef __ASSEMBLY__
5633 /*
5634  * WARNING: The C register and register group struct declarations are provided for
5635  * convenience and illustrative purposes. They should, however, be used with
5636  * caution as the C language standard provides no guarantees about the alignment or
5637  * atomicity of device memory accesses. The recommended practice for writing
5638  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5639  * alt_write_word() functions.
5640  *
5641  * The struct declaration for register ALT_CLKMGR_MAINPLL_NOCDIV.
5642  */
5643 struct ALT_CLKMGR_MAINPLL_NOCDIV_s
5644 {
5645  uint32_t l4mainclk : 2; /* L4 Main Clock Divider */
5646  uint32_t : 6; /* *UNDEFINED* */
5647  uint32_t l4mpclk : 2; /* L4 MP Clock Divider */
5648  uint32_t : 6; /* *UNDEFINED* */
5649  uint32_t l4spclk : 2; /* L4 SP Clock Divider */
5650  uint32_t : 6; /* *UNDEFINED* */
5651  uint32_t csatclk : 2; /* CoreSight Trace Clock Divider */
5652  uint32_t cstraceclk : 2; /* CoreSight Trace Interface Clock Divider */
5653  uint32_t cspdbgclk : 1; /* CoreSight Debug Clock Divider */
5654  uint32_t : 3; /* *UNDEFINED* */
5655 };
5656 
5657 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_NOCDIV. */
5658 typedef volatile struct ALT_CLKMGR_MAINPLL_NOCDIV_s ALT_CLKMGR_MAINPLL_NOCDIV_t;
5659 #endif /* __ASSEMBLY__ */
5660 
5661 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV register. */
5662 #define ALT_CLKMGR_MAINPLL_NOCDIV_RESET 0x18020100
5663 /* The byte offset of the ALT_CLKMGR_MAINPLL_NOCDIV register from the beginning of the component. */
5664 #define ALT_CLKMGR_MAINPLL_NOCDIV_OFST 0x68
5665 
5666 #ifndef __ASSEMBLY__
5667 /*
5668  * WARNING: The C register and register group struct declarations are provided for
5669  * convenience and illustrative purposes. They should, however, be used with
5670  * caution as the C language standard provides no guarantees about the alignment or
5671  * atomicity of device memory accesses. The recommended practice for writing
5672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5673  * alt_write_word() functions.
5674  *
5675  * The struct declaration for register group ALT_CLKMGR_MAINPLL.
5676  */
5677 struct ALT_CLKMGR_MAINPLL_s
5678 {
5679  ALT_CLKMGR_MAINPLL_VCO0_t vco0; /* ALT_CLKMGR_MAINPLL_VCO0 */
5680  ALT_CLKMGR_MAINPLL_VCO1_t vco1; /* ALT_CLKMGR_MAINPLL_VCO1 */
5681  ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */
5682  ALT_CLKMGR_MAINPLL_ENS_t ens; /* ALT_CLKMGR_MAINPLL_ENS */
5683  ALT_CLKMGR_MAINPLL_ENR_t enr; /* ALT_CLKMGR_MAINPLL_ENR */
5684  ALT_CLKMGR_MAINPLL_BYPASS_t bypass; /* ALT_CLKMGR_MAINPLL_BYPASS */
5685  ALT_CLKMGR_MAINPLL_BYPASSS_t bypasss; /* ALT_CLKMGR_MAINPLL_BYPASSS */
5686  ALT_CLKMGR_MAINPLL_BYPASSR_t bypassr; /* ALT_CLKMGR_MAINPLL_BYPASSR */
5687  ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
5688  ALT_CLKMGR_MAINPLL_NOCCLK_t nocclk; /* ALT_CLKMGR_MAINPLL_NOCCLK */
5689  ALT_CLKMGR_MAINPLL_CNTR2CLK_t cntr2clk; /* ALT_CLKMGR_MAINPLL_CNTR2CLK */
5690  ALT_CLKMGR_MAINPLL_CNTR3CLK_t cntr3clk; /* ALT_CLKMGR_MAINPLL_CNTR3CLK */
5691  ALT_CLKMGR_MAINPLL_CNTR4CLK_t cntr4clk; /* ALT_CLKMGR_MAINPLL_CNTR4CLK */
5692  ALT_CLKMGR_MAINPLL_CNTR5CLK_t cntr5clk; /* ALT_CLKMGR_MAINPLL_CNTR5CLK */
5693  ALT_CLKMGR_MAINPLL_CNTR6CLK_t cntr6clk; /* ALT_CLKMGR_MAINPLL_CNTR6CLK */
5694  ALT_CLKMGR_MAINPLL_CNTR7CLK_t cntr7clk; /* ALT_CLKMGR_MAINPLL_CNTR7CLK */
5695  ALT_CLKMGR_MAINPLL_CNTR8CLK_t cntr8clk; /* ALT_CLKMGR_MAINPLL_CNTR8CLK */
5696  ALT_CLKMGR_MAINPLL_CNTR9CLK_t cntr9clk; /* ALT_CLKMGR_MAINPLL_CNTR9CLK */
5697  volatile uint32_t _pad_0x48_0x5b[5]; /* *UNDEFINED* */
5698  ALT_CLKMGR_MAINPLL_CNTR15CLK_t cntr15clk; /* ALT_CLKMGR_MAINPLL_CNTR15CLK */
5699  ALT_CLKMGR_MAINPLL_OUTRST_t outrst; /* ALT_CLKMGR_MAINPLL_OUTRST */
5700  ALT_CLKMGR_MAINPLL_OUTRSTSTAT_t outrststat; /* ALT_CLKMGR_MAINPLL_OUTRSTSTAT */
5701  ALT_CLKMGR_MAINPLL_NOCDIV_t nocdiv; /* ALT_CLKMGR_MAINPLL_NOCDIV */
5702  volatile uint32_t _pad_0x6c_0x80[5]; /* *UNDEFINED* */
5703 };
5704 
5705 /* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */
5706 typedef volatile struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t;
5707 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
5708 struct ALT_CLKMGR_MAINPLL_raw_s
5709 {
5710  volatile uint32_t vco0; /* ALT_CLKMGR_MAINPLL_VCO0 */
5711  volatile uint32_t vco1; /* ALT_CLKMGR_MAINPLL_VCO1 */
5712  volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */
5713  volatile uint32_t ens; /* ALT_CLKMGR_MAINPLL_ENS */
5714  volatile uint32_t enr; /* ALT_CLKMGR_MAINPLL_ENR */
5715  volatile uint32_t bypass; /* ALT_CLKMGR_MAINPLL_BYPASS */
5716  volatile uint32_t bypasss; /* ALT_CLKMGR_MAINPLL_BYPASSS */
5717  volatile uint32_t bypassr; /* ALT_CLKMGR_MAINPLL_BYPASSR */
5718  volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
5719  volatile uint32_t nocclk; /* ALT_CLKMGR_MAINPLL_NOCCLK */
5720  volatile uint32_t cntr2clk; /* ALT_CLKMGR_MAINPLL_CNTR2CLK */
5721  volatile uint32_t cntr3clk; /* ALT_CLKMGR_MAINPLL_CNTR3CLK */
5722  volatile uint32_t cntr4clk; /* ALT_CLKMGR_MAINPLL_CNTR4CLK */
5723  volatile uint32_t cntr5clk; /* ALT_CLKMGR_MAINPLL_CNTR5CLK */
5724  volatile uint32_t cntr6clk; /* ALT_CLKMGR_MAINPLL_CNTR6CLK */
5725  volatile uint32_t cntr7clk; /* ALT_CLKMGR_MAINPLL_CNTR7CLK */
5726  volatile uint32_t cntr8clk; /* ALT_CLKMGR_MAINPLL_CNTR8CLK */
5727  volatile uint32_t cntr9clk; /* ALT_CLKMGR_MAINPLL_CNTR9CLK */
5728  uint32_t _pad_0x48_0x5b[5]; /* *UNDEFINED* */
5729  volatile uint32_t cntr15clk; /* ALT_CLKMGR_MAINPLL_CNTR15CLK */
5730  volatile uint32_t outrst; /* ALT_CLKMGR_MAINPLL_OUTRST */
5731  volatile uint32_t outrststat; /* ALT_CLKMGR_MAINPLL_OUTRSTSTAT */
5732  volatile uint32_t nocdiv; /* ALT_CLKMGR_MAINPLL_NOCDIV */
5733  uint32_t _pad_0x6c_0x80[5]; /* *UNDEFINED* */
5734 };
5735 
5736 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
5737 typedef volatile struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t;
5738 #endif /* __ASSEMBLY__ */
5739 
5740 
5741 /*
5742  * Component : ALT_CLKMGR_PERPLL
5743  *
5744  */
5745 /*
5746  * Register : Peripheral PLL VCO Control Register 0 - vco0
5747  *
5748  * Contains settings that control the Peripheral PLL VCO. VCO0 register contains
5749  * signals required for PLL reset and power down.
5750  *
5751  * Register Layout
5752  *
5753  * Bits | Access | Reset | Description
5754  * :--------|:-------|:------|:--------------------------------
5755  * [0] | RW | 0x1 | BG PWRDN
5756  * [1] | RW | 0x1 | Power down
5757  * [2] | RW | 0x0 | Enable
5758  * [3] | RW | 0x0 | All Output Counter Reset
5759  * [4] | RW | 0x0 | External Regulator Input Select
5760  * [5] | RW | 0x0 | Fast Locking Enable
5761  * [6] | RW | 0x1 | Saturation Enable
5762  * [7] | ??? | 0x0 | *UNDEFINED*
5763  * [9:8] | RW | 0x0 | Clock Source
5764  * [15:10] | ??? | 0x0 | *UNDEFINED*
5765  * [27:16] | RW | 0x1 | Loop Bandwidth Adjust
5766  * [28] | RW | 0x0 | Loop Bandwidth Adjust Enabled
5767  * [31:29] | ??? | 0x0 | *UNDEFINED*
5768  *
5769  */
5770 /*
5771  * Field : BG PWRDN - bgpwrdn
5772  *
5773  * If '1', powers down bandgap. If '0', bandgap is not power down.
5774  *
5775  * Field Access Macros:
5776  *
5777  */
5778 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field. */
5779 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_LSB 0
5780 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field. */
5781 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_MSB 0
5782 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field. */
5783 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_WIDTH 1
5784 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field value. */
5785 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
5786 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field value. */
5787 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe
5788 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field. */
5789 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_RESET 0x1
5790 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_BGPWRDN field value from a register. */
5791 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5792 /* Produces a ALT_CLKMGR_PERPLL_VCO0_BGPWRDN register field value suitable for setting the register. */
5793 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5794 
5795 /*
5796  * Field : Power down - pwrdn
5797  *
5798  * If '1', power down analog circuitry. If '0', analog circuitry not powered down.
5799  *
5800  * Field Access Macros:
5801  *
5802  */
5803 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field. */
5804 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_LSB 1
5805 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field. */
5806 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_MSB 1
5807 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field. */
5808 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_WIDTH 1
5809 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field value. */
5810 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002
5811 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field value. */
5812 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd
5813 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_PWRDN register field. */
5814 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_RESET 0x1
5815 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_PWRDN field value from a register. */
5816 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_GET(value) (((value) & 0x00000002) >> 1)
5817 /* Produces a ALT_CLKMGR_PERPLL_VCO0_PWRDN register field value suitable for setting the register. */
5818 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_SET(value) (((value) << 1) & 0x00000002)
5819 
5820 /*
5821  * Field : Enable - en
5822  *
5823  * If '1', VCO is enabled. If '0', VCO is in reset.
5824  *
5825  * Field Access Macros:
5826  *
5827  */
5828 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_EN register field. */
5829 #define ALT_CLKMGR_PERPLL_VCO0_EN_LSB 2
5830 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_EN register field. */
5831 #define ALT_CLKMGR_PERPLL_VCO0_EN_MSB 2
5832 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_EN register field. */
5833 #define ALT_CLKMGR_PERPLL_VCO0_EN_WIDTH 1
5834 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_EN register field value. */
5835 #define ALT_CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004
5836 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_EN register field value. */
5837 #define ALT_CLKMGR_PERPLL_VCO0_EN_CLR_MSK 0xfffffffb
5838 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_EN register field. */
5839 #define ALT_CLKMGR_PERPLL_VCO0_EN_RESET 0x0
5840 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_EN field value from a register. */
5841 #define ALT_CLKMGR_PERPLL_VCO0_EN_GET(value) (((value) & 0x00000004) >> 2)
5842 /* Produces a ALT_CLKMGR_PERPLL_VCO0_EN register field value suitable for setting the register. */
5843 #define ALT_CLKMGR_PERPLL_VCO0_EN_SET(value) (((value) << 2) & 0x00000004)
5844 
5845 /*
5846  * Field : All Output Counter Reset - outresetall
5847  *
5848  * Before releasing Bypass, All Output Counter Reset must be set and cleared by
5849  * software for correct clock operation.
5850  *
5851  * If '1', Reset phase multiplexer and all output counter state. So that after the
5852  * assertion all the clocks output are start from rising edge align.
5853  *
5854  * If '0', phase multiplexer and output counter state not reset and no change to
5855  * the phase of the clock outputs.
5856  *
5857  * Field Access Macros:
5858  *
5859  */
5860 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field. */
5861 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_LSB 3
5862 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field. */
5863 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_MSB 3
5864 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field. */
5865 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_WIDTH 1
5866 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field value. */
5867 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
5868 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field value. */
5869 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7
5870 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field. */
5871 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_RESET 0x0
5872 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL field value from a register. */
5873 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_GET(value) (((value) & 0x00000008) >> 3)
5874 /* Produces a ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL register field value suitable for setting the register. */
5875 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET(value) (((value) << 3) & 0x00000008)
5876 
5877 /*
5878  * Field : External Regulator Input Select - regextsel
5879  *
5880  * If set to '1', the external regulator is selected for the PLL.
5881  *
5882  * If set to '0', the internal regulator is slected.
5883  *
5884  * It is strongly recommended to select the external regulator while the PLL is not
5885  * enabled (in reset), and then disable the external regulater once the PLL
5886  * becomes enabled. Software should simulateously update the 'Enable' bit and the
5887  * 'External Regulator Input Select' in the same write access to the VCO register.
5888  * When the 'Enable' bit is clear, the 'External Regulator Input Select' should be
5889  * set, and vice versa.
5890  *
5891  * The reset value of this bit is applied on a cold reset; warm reset has no affect
5892  * on this bit.
5893  *
5894  * Field Access Macros:
5895  *
5896  */
5897 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field. */
5898 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_LSB 4
5899 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field. */
5900 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_MSB 4
5901 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field. */
5902 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_WIDTH 1
5903 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field value. */
5904 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
5905 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field value. */
5906 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef
5907 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field. */
5908 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_RESET 0x0
5909 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL field value from a register. */
5910 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_GET(value) (((value) & 0x00000010) >> 4)
5911 /* Produces a ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL register field value suitable for setting the register. */
5912 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET(value) (((value) << 4) & 0x00000010)
5913 
5914 /*
5915  * Field : Fast Locking Enable - fasten
5916  *
5917  * Enables fast locking circuit.
5918  *
5919  * Field Access Macros:
5920  *
5921  */
5922 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field. */
5923 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_LSB 5
5924 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field. */
5925 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_MSB 5
5926 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field. */
5927 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_WIDTH 1
5928 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field value. */
5929 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_SET_MSK 0x00000020
5930 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field value. */
5931 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf
5932 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_FASTEN register field. */
5933 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_RESET 0x0
5934 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_FASTEN field value from a register. */
5935 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_GET(value) (((value) & 0x00000020) >> 5)
5936 /* Produces a ALT_CLKMGR_PERPLL_VCO0_FASTEN register field value suitable for setting the register. */
5937 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_SET(value) (((value) << 5) & 0x00000020)
5938 
5939 /*
5940  * Field : Saturation Enable - saten
5941  *
5942  * Enables saturation behavior.
5943  *
5944  * Field Access Macros:
5945  *
5946  */
5947 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_SATEN register field. */
5948 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_LSB 6
5949 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_SATEN register field. */
5950 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_MSB 6
5951 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_SATEN register field. */
5952 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_WIDTH 1
5953 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_SATEN register field value. */
5954 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_SET_MSK 0x00000040
5955 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_SATEN register field value. */
5956 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_CLR_MSK 0xffffffbf
5957 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_SATEN register field. */
5958 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_RESET 0x1
5959 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_SATEN field value from a register. */
5960 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_GET(value) (((value) & 0x00000040) >> 6)
5961 /* Produces a ALT_CLKMGR_PERPLL_VCO0_SATEN register field value suitable for setting the register. */
5962 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_SET(value) (((value) << 6) & 0x00000040)
5963 
5964 /*
5965  * Field : Clock Source - psrc
5966  *
5967  * Controls the VCO input clock source.
5968  *
5969  * Field Enumeration Values:
5970  *
5971  * Enum | Value | Description
5972  * :-------------------------------------|:------|:-----------------
5973  * ALT_CLKMGR_PERPLL_VCO0_PSRC_E_EOSC1 | 0x0 | eosc1_clk
5974  * ALT_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC | 0x1 | cb_intosc_clk
5975  * ALT_CLKMGR_PERPLL_VCO0_PSRC_E_F2S | 0x2 | f2s_free_clk
5976  * ALT_CLKMGR_PERPLL_VCO0_PSRC_E_MAIN | 0x3 | main_count15_clk
5977  *
5978  * Field Access Macros:
5979  *
5980  */
5981 /*
5982  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO0_PSRC
5983  *
5984  * eosc1_clk
5985  */
5986 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_EOSC1 0x0
5987 /*
5988  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO0_PSRC
5989  *
5990  * cb_intosc_clk
5991  */
5992 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
5993 /*
5994  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO0_PSRC
5995  *
5996  * f2s_free_clk
5997  */
5998 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_F2S 0x2
5999 /*
6000  * Enumerated value for register field ALT_CLKMGR_PERPLL_VCO0_PSRC
6001  *
6002  * main_count15_clk
6003  */
6004 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_MAIN 0x3
6005 
6006 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_PSRC register field. */
6007 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_LSB 8
6008 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_PSRC register field. */
6009 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_MSB 9
6010 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_PSRC register field. */
6011 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_WIDTH 2
6012 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_PSRC register field value. */
6013 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_SET_MSK 0x00000300
6014 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_PSRC register field value. */
6015 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_CLR_MSK 0xfffffcff
6016 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_PSRC register field. */
6017 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_RESET 0x0
6018 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_PSRC field value from a register. */
6019 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_GET(value) (((value) & 0x00000300) >> 8)
6020 /* Produces a ALT_CLKMGR_PERPLL_VCO0_PSRC register field value suitable for setting the register. */
6021 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_SET(value) (((value) << 8) & 0x00000300)
6022 
6023 /*
6024  * Field : Loop Bandwidth Adjust - bwadj
6025  *
6026  * Provides Loop Bandwidth Adjust value.
6027  *
6028  * Field Access Macros:
6029  *
6030  */
6031 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field. */
6032 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_LSB 16
6033 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field. */
6034 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_MSB 27
6035 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field. */
6036 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_WIDTH 12
6037 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field value. */
6038 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_SET_MSK 0x0fff0000
6039 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field value. */
6040 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff
6041 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_BWADJ register field. */
6042 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_RESET 0x1
6043 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_BWADJ field value from a register. */
6044 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_GET(value) (((value) & 0x0fff0000) >> 16)
6045 /* Produces a ALT_CLKMGR_PERPLL_VCO0_BWADJ register field value suitable for setting the register. */
6046 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_SET(value) (((value) << 16) & 0x0fff0000)
6047 
6048 /*
6049  * Field : Loop Bandwidth Adjust Enabled - bwadjen
6050  *
6051  * If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth
6052  * Adjust field.
6053  *
6054  * If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2
6055  * value of the VCO Control Register. The M divided by 2 is the upper 12 bits
6056  * (12:1) of the M field in the VCO register.
6057  *
6058  * Field Access Macros:
6059  *
6060  */
6061 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field. */
6062 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_LSB 28
6063 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field. */
6064 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_MSB 28
6065 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field. */
6066 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_WIDTH 1
6067 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field value. */
6068 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_SET_MSK 0x10000000
6069 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field value. */
6070 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff
6071 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field. */
6072 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_RESET 0x0
6073 /* Extracts the ALT_CLKMGR_PERPLL_VCO0_BWADJEN field value from a register. */
6074 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_GET(value) (((value) & 0x10000000) >> 28)
6075 /* Produces a ALT_CLKMGR_PERPLL_VCO0_BWADJEN register field value suitable for setting the register. */
6076 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_SET(value) (((value) << 28) & 0x10000000)
6077 
6078 #ifndef __ASSEMBLY__
6079 /*
6080  * WARNING: The C register and register group struct declarations are provided for
6081  * convenience and illustrative purposes. They should, however, be used with
6082  * caution as the C language standard provides no guarantees about the alignment or
6083  * atomicity of device memory accesses. The recommended practice for writing
6084  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6085  * alt_write_word() functions.
6086  *
6087  * The struct declaration for register ALT_CLKMGR_PERPLL_VCO0.
6088  */
6089 struct ALT_CLKMGR_PERPLL_VCO0_s
6090 {
6091  uint32_t bgpwrdn : 1; /* BG PWRDN */
6092  uint32_t pwrdn : 1; /* Power down */
6093  uint32_t en : 1; /* Enable */
6094  uint32_t outresetall : 1; /* All Output Counter Reset */
6095  uint32_t regextsel : 1; /* External Regulator Input Select */
6096  uint32_t fasten : 1; /* Fast Locking Enable */
6097  uint32_t saten : 1; /* Saturation Enable */
6098  uint32_t : 1; /* *UNDEFINED* */
6099  uint32_t psrc : 2; /* Clock Source */
6100  uint32_t : 6; /* *UNDEFINED* */
6101  uint32_t bwadj : 12; /* Loop Bandwidth Adjust */
6102  uint32_t bwadjen : 1; /* Loop Bandwidth Adjust Enabled */
6103  uint32_t : 3; /* *UNDEFINED* */
6104 };
6105 
6106 /* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO0. */
6107 typedef volatile struct ALT_CLKMGR_PERPLL_VCO0_s ALT_CLKMGR_PERPLL_VCO0_t;
6108 #endif /* __ASSEMBLY__ */
6109 
6110 /* The reset value of the ALT_CLKMGR_PERPLL_VCO0 register. */
6111 #define ALT_CLKMGR_PERPLL_VCO0_RESET 0x00010043
6112 /* The byte offset of the ALT_CLKMGR_PERPLL_VCO0 register from the beginning of the component. */
6113 #define ALT_CLKMGR_PERPLL_VCO0_OFST 0x0
6114 
6115 /*
6116  * Register : Main PLL VCO Control Register - vco1
6117  *
6118  * Contains settings that control the Peripheral PLL VCO. The VCO1 register
6119  * contains the numerator and denominator counter settings.
6120  *
6121  * Register Layout
6122  *
6123  * Bits | Access | Reset | Description
6124  * :--------|:-------|:------|:----------------
6125  * [12:0] | RW | 0x1 | Numerator (M)
6126  * [15:13] | ??? | 0x0 | *UNDEFINED*
6127  * [21:16] | RW | 0x1 | Denominator (N)
6128  * [31:22] | ??? | 0x0 | *UNDEFINED*
6129  *
6130  */
6131 /*
6132  * Field : Numerator (M) - numer
6133  *
6134  * Numerator in VCO output frequency equation. For incremental frequency change, if
6135  * the new value lead to less than 20% of the frequency change, this value can be
6136  * changed without resetting the PLL. The Numerator and Denominator can not be
6137  * changed at the same time for incremental frequency changed.
6138  *
6139  * Field Access Macros:
6140  *
6141  */
6142 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO1_NUMER register field. */
6143 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_LSB 0
6144 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO1_NUMER register field. */
6145 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_MSB 12
6146 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO1_NUMER register field. */
6147 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_WIDTH 13
6148 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO1_NUMER register field value. */
6149 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_SET_MSK 0x00001fff
6150 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO1_NUMER register field value. */
6151 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_CLR_MSK 0xffffe000
6152 /* The reset value of the ALT_CLKMGR_PERPLL_VCO1_NUMER register field. */
6153 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_RESET 0x1
6154 /* Extracts the ALT_CLKMGR_PERPLL_VCO1_NUMER field value from a register. */
6155 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_GET(value) (((value) & 0x00001fff) >> 0)
6156 /* Produces a ALT_CLKMGR_PERPLL_VCO1_NUMER register field value suitable for setting the register. */
6157 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_SET(value) (((value) << 0) & 0x00001fff)
6158 
6159 /*
6160  * Field : Denominator (N) - denom
6161  *
6162  * Denominator in VCO output frequency equation. For incremental frequency change,
6163  * if the new value lead to less than 20% of the frequency change, this value can
6164  * be changed without resetting the PLL. The Numerator and Denominator can not be
6165  * changed at the same time for incremental frequency changed.
6166  *
6167  * Field Access Macros:
6168  *
6169  */
6170 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCO1_DENOM register field. */
6171 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_LSB 16
6172 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCO1_DENOM register field. */
6173 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_MSB 21
6174 /* The width in bits of the ALT_CLKMGR_PERPLL_VCO1_DENOM register field. */
6175 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_WIDTH 6
6176 /* The mask used to set the ALT_CLKMGR_PERPLL_VCO1_DENOM register field value. */
6177 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_SET_MSK 0x003f0000
6178 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCO1_DENOM register field value. */
6179 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_CLR_MSK 0xffc0ffff
6180 /* The reset value of the ALT_CLKMGR_PERPLL_VCO1_DENOM register field. */
6181 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_RESET 0x1
6182 /* Extracts the ALT_CLKMGR_PERPLL_VCO1_DENOM field value from a register. */
6183 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
6184 /* Produces a ALT_CLKMGR_PERPLL_VCO1_DENOM register field value suitable for setting the register. */
6185 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_SET(value) (((value) << 16) & 0x003f0000)
6186 
6187 #ifndef __ASSEMBLY__
6188 /*
6189  * WARNING: The C register and register group struct declarations are provided for
6190  * convenience and illustrative purposes. They should, however, be used with
6191  * caution as the C language standard provides no guarantees about the alignment or
6192  * atomicity of device memory accesses. The recommended practice for writing
6193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6194  * alt_write_word() functions.
6195  *
6196  * The struct declaration for register ALT_CLKMGR_PERPLL_VCO1.
6197  */
6198 struct ALT_CLKMGR_PERPLL_VCO1_s
6199 {
6200  uint32_t numer : 13; /* Numerator (M) */
6201  uint32_t : 3; /* *UNDEFINED* */
6202  uint32_t denom : 6; /* Denominator (N) */
6203  uint32_t : 10; /* *UNDEFINED* */
6204 };
6205 
6206 /* The typedef declaration for register ALT_CLKMGR_PERPLL_VCO1. */
6207 typedef volatile struct ALT_CLKMGR_PERPLL_VCO1_s ALT_CLKMGR_PERPLL_VCO1_t;
6208 #endif /* __ASSEMBLY__ */
6209 
6210 /* The reset value of the ALT_CLKMGR_PERPLL_VCO1 register. */
6211 #define ALT_CLKMGR_PERPLL_VCO1_RESET 0x00010001
6212 /* The byte offset of the ALT_CLKMGR_PERPLL_VCO1 register from the beginning of the component. */
6213 #define ALT_CLKMGR_PERPLL_VCO1_OFST 0x4
6214 
6215 /*
6216  * Register : Enable Register - en
6217  *
6218  * Contains fields that control clock enables for clocks derived from the
6219  * Peripheral PLL.
6220  *
6221  * 1: The clock is enabled.
6222  *
6223  * 0: The clock is disabled.
6224  *
6225  * Register Layout
6226  *
6227  * Bits | Access | Reset | Description
6228  * :--------|:-------|:------|:---------------------
6229  * [0] | RW | 0x1 | emac0_clk Enable
6230  * [1] | RW | 0x1 | emac1_clk_clk Enable
6231  * [2] | RW | 0x1 | emac2_clk Enable
6232  * [3] | RW | 0x1 | emac_ptp_clk Enable
6233  * [4] | RW | 0x1 | gpio_db_clk Enable
6234  * [5] | RW | 0x1 | SDMMC Clock Enable
6235  * [6] | RW | 0x1 | s2f_user1_clk Enable
6236  * [7] | ??? | 0x0 | *UNDEFINED*
6237  * [8] | RW | 0x1 | USB Clock Enable
6238  * [9] | RW | 0x1 | SPIM Clock Enable
6239  * [10] | RW | 0x1 | NAND Clock Enable
6240  * [11] | RW | 0x1 | QSPI Clock Enable
6241  * [31:12] | ??? | 0x0 | *UNDEFINED*
6242  *
6243  */
6244 /*
6245  * Field : emac0_clk Enable - emac0en
6246  *
6247  * Enables clock emac0_clk output
6248  *
6249  * Field Access Macros:
6250  *
6251  */
6252 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
6253 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_LSB 0
6254 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
6255 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_MSB 0
6256 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
6257 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_WIDTH 1
6258 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value. */
6259 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET_MSK 0x00000001
6260 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value. */
6261 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_CLR_MSK 0xfffffffe
6262 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
6263 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_RESET 0x1
6264 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0EN field value from a register. */
6265 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6266 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value suitable for setting the register. */
6267 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6268 
6269 /*
6270  * Field : emac1_clk_clk Enable - emac1en
6271  *
6272  * Enables clock emac1_clk output
6273  *
6274  * Field Access Macros:
6275  *
6276  */
6277 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
6278 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_LSB 1
6279 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
6280 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_MSB 1
6281 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
6282 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_WIDTH 1
6283 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value. */
6284 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET_MSK 0x00000002
6285 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value. */
6286 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_CLR_MSK 0xfffffffd
6287 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
6288 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_RESET 0x1
6289 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1EN field value from a register. */
6290 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6291 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value suitable for setting the register. */
6292 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6293 
6294 /*
6295  * Field : emac2_clk Enable - emac2en
6296  *
6297  * Enables clock emac2_clk output
6298  *
6299  * Field Access Macros:
6300  *
6301  */
6302 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
6303 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_LSB 2
6304 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
6305 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_MSB 2
6306 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
6307 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_WIDTH 1
6308 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value. */
6309 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET_MSK 0x00000004
6310 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value. */
6311 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_CLR_MSK 0xfffffffb
6312 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
6313 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_RESET 0x1
6314 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC2EN field value from a register. */
6315 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6316 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value suitable for setting the register. */
6317 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
6318 
6319 /*
6320  * Field : emac_ptp_clk Enable - emacptpen
6321  *
6322  * Enables clock emac_ptp_clk output
6323  *
6324  * Field Access Macros:
6325  *
6326  */
6327 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
6328 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_LSB 3
6329 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
6330 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_MSB 3
6331 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
6332 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_WIDTH 1
6333 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value. */
6334 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET_MSK 0x00000008
6335 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value. */
6336 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_CLR_MSK 0xfffffff7
6337 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
6338 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_RESET 0x1
6339 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMACPTPEN field value from a register. */
6340 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
6341 /* Produces a ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value suitable for setting the register. */
6342 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
6343 
6344 /*
6345  * Field : gpio_db_clk Enable - gpiodben
6346  *
6347  * Enables clock gpio_db_clk output
6348  *
6349  * Field Access Macros:
6350  *
6351  */
6352 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
6353 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_LSB 4
6354 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
6355 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_MSB 4
6356 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
6357 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_WIDTH 1
6358 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value. */
6359 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET_MSK 0x00000010
6360 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value. */
6361 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_CLR_MSK 0xffffffef
6362 /* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
6363 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_RESET 0x1
6364 /* Extracts the ALT_CLKMGR_PERPLL_EN_GPIODBEN field value from a register. */
6365 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
6366 /* Produces a ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value suitable for setting the register. */
6367 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
6368 
6369 /*
6370  * Field : SDMMC Clock Enable - sdmmcclken
6371  *
6372  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
6373  * to the SDMMC directly.
6374  *
6375  * Field Access Macros:
6376  *
6377  */
6378 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
6379 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_LSB 5
6380 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
6381 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_MSB 5
6382 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
6383 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_WIDTH 1
6384 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value. */
6385 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET_MSK 0x00000020
6386 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value. */
6387 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_CLR_MSK 0xffffffdf
6388 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
6389 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_RESET 0x1
6390 /* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN field value from a register. */
6391 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
6392 /* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value suitable for setting the register. */
6393 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
6394 
6395 /*
6396  * Field : s2f_user1_clk Enable - s2fuser1clken
6397  *
6398  * Enables clock s2f_user1_clk output
6399  *
6400  * Field Access Macros:
6401  *
6402  */
6403 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
6404 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_LSB 6
6405 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
6406 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_MSB 6
6407 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
6408 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_WIDTH 1
6409 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value. */
6410 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET_MSK 0x00000040
6411 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value. */
6412 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
6413 /* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
6414 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_RESET 0x1
6415 /* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN field value from a register. */
6416 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
6417 /* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value suitable for setting the register. */
6418 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
6419 
6420 /*
6421  * Field : USB Clock Enable - usbclken
6422  *
6423  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
6424  * the USB directly.
6425  *
6426  * Field Access Macros:
6427  *
6428  */
6429 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
6430 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_LSB 8
6431 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
6432 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_MSB 8
6433 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
6434 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_WIDTH 1
6435 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value. */
6436 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET_MSK 0x00000100
6437 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value. */
6438 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_CLR_MSK 0xfffffeff
6439 /* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
6440 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_RESET 0x1
6441 /* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLKEN field value from a register. */
6442 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
6443 /* Produces a ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value suitable for setting the register. */
6444 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
6445 
6446 /*
6447  * Field : SPIM Clock Enable - spimclken
6448  *
6449  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
6450  * Manger to the SPIM directly.
6451  *
6452  * Field Access Macros:
6453  *
6454  */
6455 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
6456 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_LSB 9
6457 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
6458 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_MSB 9
6459 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
6460 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_WIDTH 1
6461 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value. */
6462 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET_MSK 0x00000200
6463 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value. */
6464 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_CLR_MSK 0xfffffdff
6465 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
6466 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_RESET 0x1
6467 /* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN field value from a register. */
6468 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
6469 /* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value suitable for setting the register. */
6470 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
6471 
6472 /*
6473  * Field : NAND Clock Enable - nandclken
6474  *
6475  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
6476  * the NAND directly.
6477  *
6478  * Field Access Macros:
6479  *
6480  */
6481 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
6482 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_LSB 10
6483 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
6484 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_MSB 10
6485 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
6486 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_WIDTH 1
6487 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value. */
6488 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET_MSK 0x00000400
6489 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value. */
6490 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_CLR_MSK 0xfffffbff
6491 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
6492 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_RESET 0x1
6493 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLKEN field value from a register. */
6494 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
6495 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value suitable for setting the register. */
6496 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
6497 
6498 /*
6499  * Field : QSPI Clock Enable - qspiclken
6500  *
6501  * Enables QSPI peripheral clock. This enable goes outside of the Clock Manger to
6502  * the QSPI directly.
6503  *
6504  * Field Access Macros:
6505  *
6506  */
6507 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field. */
6508 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_LSB 11
6509 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field. */
6510 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_MSB 11
6511 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field. */
6512 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_WIDTH 1
6513 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field value. */
6514 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_SET_MSK 0x00000800
6515 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field value. */
6516 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_CLR_MSK 0xfffff7ff
6517 /* The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field. */
6518 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_RESET 0x1
6519 /* Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLKEN field value from a register. */
6520 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
6521 /* Produces a ALT_CLKMGR_PERPLL_EN_QSPICLKEN register field value suitable for setting the register. */
6522 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
6523 
6524 #ifndef __ASSEMBLY__
6525 /*
6526  * WARNING: The C register and register group struct declarations are provided for
6527  * convenience and illustrative purposes. They should, however, be used with
6528  * caution as the C language standard provides no guarantees about the alignment or
6529  * atomicity of device memory accesses. The recommended practice for writing
6530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6531  * alt_write_word() functions.
6532  *
6533  * The struct declaration for register ALT_CLKMGR_PERPLL_EN.
6534  */
6535 struct ALT_CLKMGR_PERPLL_EN_s
6536 {
6537  uint32_t emac0en : 1; /* emac0_clk Enable */
6538  uint32_t emac1en : 1; /* emac1_clk_clk Enable */
6539  uint32_t emac2en : 1; /* emac2_clk Enable */
6540  uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
6541  uint32_t gpiodben : 1; /* gpio_db_clk Enable */
6542  uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
6543  uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
6544  uint32_t : 1; /* *UNDEFINED* */
6545  uint32_t usbclken : 1; /* USB Clock Enable */
6546  uint32_t spimclken : 1; /* SPIM Clock Enable */
6547  uint32_t nandclken : 1; /* NAND Clock Enable */
6548  uint32_t qspiclken : 1; /* QSPI Clock Enable */
6549  uint32_t : 20; /* *UNDEFINED* */
6550 };
6551 
6552 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */
6553 typedef volatile struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
6554 #endif /* __ASSEMBLY__ */
6555 
6556 /* The reset value of the ALT_CLKMGR_PERPLL_EN register. */
6557 #define ALT_CLKMGR_PERPLL_EN_RESET 0x00000f7f
6558 /* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */
6559 #define ALT_CLKMGR_PERPLL_EN_OFST 0x8
6560 
6561 /*
6562  * Register : Enable Set Register - ens
6563  *
6564  * Write One to Set corresonding fields in Enable Register.
6565  *
6566  * Register Layout
6567  *
6568  * Bits | Access | Reset | Description
6569  * :--------|:-------|:------|:---------------------
6570  * [0] | RW | 0x1 | emac0_clk Enable
6571  * [1] | RW | 0x1 | emac1_clk_clk Enable
6572  * [2] | RW | 0x1 | emac2_clk Enable
6573  * [3] | RW | 0x1 | emac_ptp_clk Enable
6574  * [4] | RW | 0x1 | gpio_db_clk Enable
6575  * [5] | RW | 0x1 | SDMMC Clock Enable
6576  * [6] | RW | 0x1 | s2f_user1_clk Enable
6577  * [7] | ??? | 0x0 | *UNDEFINED*
6578  * [8] | RW | 0x1 | USB Clock Enable
6579  * [9] | RW | 0x1 | SPIM Clock Enable
6580  * [10] | RW | 0x1 | NAND Clock Enable
6581  * [11] | RW | 0x1 | QSPI Clock Enable
6582  * [31:12] | ??? | 0x0 | *UNDEFINED*
6583  *
6584  */
6585 /*
6586  * Field : emac0_clk Enable - emac0en
6587  *
6588  * Enables clock emac0_clk output
6589  *
6590  * Field Access Macros:
6591  *
6592  */
6593 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
6594 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0
6595 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
6596 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0
6597 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
6598 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1
6599 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value. */
6600 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001
6601 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value. */
6602 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe
6603 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
6604 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1
6605 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC0EN field value from a register. */
6606 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6607 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value suitable for setting the register. */
6608 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6609 
6610 /*
6611  * Field : emac1_clk_clk Enable - emac1en
6612  *
6613  * Enables clock emac1_clk output
6614  *
6615  * Field Access Macros:
6616  *
6617  */
6618 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
6619 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1
6620 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
6621 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1
6622 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
6623 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1
6624 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value. */
6625 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002
6626 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value. */
6627 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd
6628 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
6629 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1
6630 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC1EN field value from a register. */
6631 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6632 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value suitable for setting the register. */
6633 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6634 
6635 /*
6636  * Field : emac2_clk Enable - emac2en
6637  *
6638  * Enables clock emac2_clk output
6639  *
6640  * Field Access Macros:
6641  *
6642  */
6643 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
6644 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2
6645 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
6646 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2
6647 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
6648 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1
6649 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value. */
6650 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004
6651 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value. */
6652 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb
6653 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
6654 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1
6655 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC2EN field value from a register. */
6656 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6657 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value suitable for setting the register. */
6658 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
6659 
6660 /*
6661  * Field : emac_ptp_clk Enable - emacptpen
6662  *
6663  * Enables clock emac_ptp_clk output
6664  *
6665  * Field Access Macros:
6666  *
6667  */
6668 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
6669 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3
6670 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
6671 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3
6672 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
6673 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1
6674 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value. */
6675 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008
6676 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value. */
6677 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7
6678 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
6679 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1
6680 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN field value from a register. */
6681 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
6682 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value suitable for setting the register. */
6683 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
6684 
6685 /*
6686  * Field : gpio_db_clk Enable - gpiodben
6687  *
6688  * Enables clock gpio_db_clk output
6689  *
6690  * Field Access Macros:
6691  *
6692  */
6693 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
6694 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4
6695 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
6696 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4
6697 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
6698 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1
6699 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value. */
6700 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010
6701 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value. */
6702 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef
6703 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
6704 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1
6705 /* Extracts the ALT_CLKMGR_PERPLL_ENS_GPIODBEN field value from a register. */
6706 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
6707 /* Produces a ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value suitable for setting the register. */
6708 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
6709 
6710 /*
6711  * Field : SDMMC Clock Enable - sdmmcclken
6712  *
6713  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
6714  * to the SDMMC directly.
6715  *
6716  * Field Access Macros:
6717  *
6718  */
6719 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
6720 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5
6721 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
6722 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5
6723 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
6724 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1
6725 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value. */
6726 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020
6727 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value. */
6728 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf
6729 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
6730 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1
6731 /* Extracts the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN field value from a register. */
6732 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
6733 /* Produces a ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value suitable for setting the register. */
6734 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
6735 
6736 /*
6737  * Field : s2f_user1_clk Enable - s2fuser1clken
6738  *
6739  * Enables clock s2f_user1_clk output
6740  *
6741  * Field Access Macros:
6742  *
6743  */
6744 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
6745 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6
6746 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
6747 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6
6748 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
6749 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1
6750 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value. */
6751 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040
6752 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value. */
6753 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
6754 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
6755 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1
6756 /* Extracts the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN field value from a register. */
6757 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
6758 /* Produces a ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value suitable for setting the register. */
6759 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
6760 
6761 /*
6762  * Field : USB Clock Enable - usbclken
6763  *
6764  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
6765  * the USB directly.
6766  *
6767  * Field Access Macros:
6768  *
6769  */
6770 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
6771 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8
6772 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
6773 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8
6774 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
6775 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1
6776 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value. */
6777 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100
6778 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value. */
6779 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff
6780 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
6781 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1
6782 /* Extracts the ALT_CLKMGR_PERPLL_ENS_USBCLKEN field value from a register. */
6783 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
6784 /* Produces a ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value suitable for setting the register. */
6785 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
6786 
6787 /*
6788  * Field : SPIM Clock Enable - spimclken
6789  *
6790  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
6791  * Manger to the SPIM directly.
6792  *
6793  * Field Access Macros:
6794  *
6795  */
6796 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
6797 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9
6798 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
6799 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9
6800 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
6801 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1
6802 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value. */
6803 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200
6804 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value. */
6805 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff
6806 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
6807 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1
6808 /* Extracts the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN field value from a register. */
6809 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
6810 /* Produces a ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value suitable for setting the register. */
6811 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
6812 
6813 /*
6814  * Field : NAND Clock Enable - nandclken
6815  *
6816  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
6817  * the NAND directly.
6818  *
6819  * Field Access Macros:
6820  *
6821  */
6822 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
6823 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10
6824 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
6825 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10
6826 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
6827 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1
6828 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value. */
6829 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400
6830 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value. */
6831 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff
6832 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
6833 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1
6834 /* Extracts the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN field value from a register. */
6835 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
6836 /* Produces a ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value suitable for setting the register. */
6837 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
6838 
6839 /*
6840  * Field : QSPI Clock Enable - qspiclken
6841  *
6842  * Enables QSPI peripheral clock. This enable goes outside of the Clock Manger to
6843  * the QSPI directly.
6844  *
6845  * Field Access Macros:
6846  *
6847  */
6848 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field. */
6849 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_LSB 11
6850 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field. */
6851 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_MSB 11
6852 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field. */
6853 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_WIDTH 1
6854 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value. */
6855 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET_MSK 0x00000800
6856 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value. */
6857 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_CLR_MSK 0xfffff7ff
6858 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field. */
6859 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_RESET 0x1
6860 /* Extracts the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN field value from a register. */
6861 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
6862 /* Produces a ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value suitable for setting the register. */
6863 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
6864 
6865 #ifndef __ASSEMBLY__
6866 /*
6867  * WARNING: The C register and register group struct declarations are provided for
6868  * convenience and illustrative purposes. They should, however, be used with
6869  * caution as the C language standard provides no guarantees about the alignment or
6870  * atomicity of device memory accesses. The recommended practice for writing
6871  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6872  * alt_write_word() functions.
6873  *
6874  * The struct declaration for register ALT_CLKMGR_PERPLL_ENS.
6875  */
6876 struct ALT_CLKMGR_PERPLL_ENS_s
6877 {
6878  uint32_t emac0en : 1; /* emac0_clk Enable */
6879  uint32_t emac1en : 1; /* emac1_clk_clk Enable */
6880  uint32_t emac2en : 1; /* emac2_clk Enable */
6881  uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
6882  uint32_t gpiodben : 1; /* gpio_db_clk Enable */
6883  uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
6884  uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
6885  uint32_t : 1; /* *UNDEFINED* */
6886  uint32_t usbclken : 1; /* USB Clock Enable */
6887  uint32_t spimclken : 1; /* SPIM Clock Enable */
6888  uint32_t nandclken : 1; /* NAND Clock Enable */
6889  uint32_t qspiclken : 1; /* QSPI Clock Enable */
6890  uint32_t : 20; /* *UNDEFINED* */
6891 };
6892 
6893 /* The typedef declaration for register ALT_CLKMGR_PERPLL_ENS. */
6894 typedef volatile struct ALT_CLKMGR_PERPLL_ENS_s ALT_CLKMGR_PERPLL_ENS_t;
6895 #endif /* __ASSEMBLY__ */
6896 
6897 /* The reset value of the ALT_CLKMGR_PERPLL_ENS register. */
6898 #define ALT_CLKMGR_PERPLL_ENS_RESET 0x00000f7f
6899 /* The byte offset of the ALT_CLKMGR_PERPLL_ENS register from the beginning of the component. */
6900 #define ALT_CLKMGR_PERPLL_ENS_OFST 0xc
6901 
6902 /*
6903  * Register : Enable Reset Register - enr
6904  *
6905  * Write One to Clear corresponding fields in Enable Register.
6906  *
6907  * Register Layout
6908  *
6909  * Bits | Access | Reset | Description
6910  * :--------|:-------|:------|:---------------------
6911  * [0] | RW | 0x1 | emac0_clk Enable
6912  * [1] | RW | 0x1 | emac1_clk_clk Enable
6913  * [2] | RW | 0x1 | emac2_clk Enable
6914  * [3] | RW | 0x1 | emac_ptp_clk Enable
6915  * [4] | RW | 0x1 | gpio_db_clk Enable
6916  * [5] | RW | 0x1 | SDMMC Clock Enable
6917  * [6] | RW | 0x1 | s2f_user1_clk Enable
6918  * [7] | ??? | 0x0 | *UNDEFINED*
6919  * [8] | RW | 0x1 | USB Clock Enable
6920  * [9] | RW | 0x1 | SPIM Clock Enable
6921  * [10] | RW | 0x1 | NAND Clock Enable
6922  * [11] | RW | 0x1 | QSPI Clock Enable
6923  * [31:12] | ??? | 0x0 | *UNDEFINED*
6924  *
6925  */
6926 /*
6927  * Field : emac0_clk Enable - emac0en
6928  *
6929  * Enables clock emac0_clk output
6930  *
6931  * Field Access Macros:
6932  *
6933  */
6934 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
6935 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_LSB 0
6936 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
6937 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_MSB 0
6938 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
6939 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_WIDTH 1
6940 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value. */
6941 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET_MSK 0x00000001
6942 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value. */
6943 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_CLR_MSK 0xfffffffe
6944 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
6945 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_RESET 0x1
6946 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC0EN field value from a register. */
6947 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6948 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value suitable for setting the register. */
6949 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6950 
6951 /*
6952  * Field : emac1_clk_clk Enable - emac1en
6953  *
6954  * Enables clock emac1_clk output
6955  *
6956  * Field Access Macros:
6957  *
6958  */
6959 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
6960 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_LSB 1
6961 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
6962 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_MSB 1
6963 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
6964 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_WIDTH 1
6965 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value. */
6966 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET_MSK 0x00000002
6967 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value. */
6968 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_CLR_MSK 0xfffffffd
6969 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
6970 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_RESET 0x1
6971 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC1EN field value from a register. */
6972 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6973 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value suitable for setting the register. */
6974 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6975 
6976 /*
6977  * Field : emac2_clk Enable - emac2en
6978  *
6979  * Enables clock emac2_clk output
6980  *
6981  * Field Access Macros:
6982  *
6983  */
6984 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
6985 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_LSB 2
6986 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
6987 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_MSB 2
6988 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
6989 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_WIDTH 1
6990 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value. */
6991 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET_MSK 0x00000004
6992 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value. */
6993 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_CLR_MSK 0xfffffffb
6994 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
6995 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_RESET 0x1
6996 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC2EN field value from a register. */
6997 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6998 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value suitable for setting the register. */
6999 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
7000 
7001 /*
7002  * Field : emac_ptp_clk Enable - emacptpen
7003  *
7004  * Enables clock emac_ptp_clk output
7005  *
7006  * Field Access Macros:
7007  *
7008  */
7009 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
7010 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_LSB 3
7011 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
7012 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_MSB 3
7013 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
7014 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_WIDTH 1
7015 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value. */
7016 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET_MSK 0x00000008
7017 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value. */
7018 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_CLR_MSK 0xfffffff7
7019 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
7020 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_RESET 0x1
7021 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN field value from a register. */
7022 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
7023 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value suitable for setting the register. */
7024 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
7025 
7026 /*
7027  * Field : gpio_db_clk Enable - gpiodben
7028  *
7029  * Enables clock gpio_db_clk output
7030  *
7031  * Field Access Macros:
7032  *
7033  */
7034 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
7035 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_LSB 4
7036 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
7037 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_MSB 4
7038 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
7039 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_WIDTH 1
7040 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value. */
7041 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET_MSK 0x00000010
7042 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value. */
7043 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_CLR_MSK 0xffffffef
7044 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
7045 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_RESET 0x1
7046 /* Extracts the ALT_CLKMGR_PERPLL_ENR_GPIODBEN field value from a register. */
7047 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
7048 /* Produces a ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value suitable for setting the register. */
7049 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
7050 
7051 /*
7052  * Field : SDMMC Clock Enable - sdmmcclken
7053  *
7054  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
7055  * to the SDMMC directly.
7056  *
7057  * Field Access Macros:
7058  *
7059  */
7060 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
7061 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_LSB 5
7062 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
7063 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_MSB 5
7064 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
7065 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_WIDTH 1
7066 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value. */
7067 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET_MSK 0x00000020
7068 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value. */
7069 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_CLR_MSK 0xffffffdf
7070 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
7071 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_RESET 0x1
7072 /* Extracts the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN field value from a register. */
7073 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
7074 /* Produces a ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value suitable for setting the register. */
7075 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
7076 
7077 /*
7078  * Field : s2f_user1_clk Enable - s2fuser1clken
7079  *
7080  * Enables clock s2f_user1_clk output
7081  *
7082  * Field Access Macros:
7083  *
7084  */
7085 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
7086 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_LSB 6
7087 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
7088 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_MSB 6
7089 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
7090 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_WIDTH 1
7091 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value. */
7092 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET_MSK 0x00000040
7093 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value. */
7094 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
7095 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
7096 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_RESET 0x1
7097 /* Extracts the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN field value from a register. */
7098 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
7099 /* Produces a ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value suitable for setting the register. */
7100 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
7101 
7102 /*
7103  * Field : USB Clock Enable - usbclken
7104  *
7105  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
7106  * the USB directly.
7107  *
7108  * Field Access Macros:
7109  *
7110  */
7111 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
7112 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_LSB 8
7113 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
7114 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_MSB 8
7115 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
7116 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_WIDTH 1
7117 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value. */
7118 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET_MSK 0x00000100
7119 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value. */
7120 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_CLR_MSK 0xfffffeff
7121 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
7122 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_RESET 0x1
7123 /* Extracts the ALT_CLKMGR_PERPLL_ENR_USBCLKEN field value from a register. */
7124 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
7125 /* Produces a ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value suitable for setting the register. */
7126 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
7127 
7128 /*
7129  * Field : SPIM Clock Enable - spimclken
7130  *
7131  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
7132  * Manger to the SPIM directly.
7133  *
7134  * Field Access Macros:
7135  *
7136  */
7137 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
7138 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_LSB 9
7139 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
7140 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_MSB 9
7141 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
7142 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_WIDTH 1
7143 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value. */
7144 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET_MSK 0x00000200
7145 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value. */
7146 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_CLR_MSK 0xfffffdff
7147 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
7148 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_RESET 0x1
7149 /* Extracts the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN field value from a register. */
7150 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
7151 /* Produces a ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value suitable for setting the register. */
7152 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
7153 
7154 /*
7155  * Field : NAND Clock Enable - nandclken
7156  *
7157  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
7158  * the NAND directly.
7159  *
7160  * Field Access Macros:
7161  *
7162  */
7163 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
7164 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_LSB 10
7165 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
7166 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_MSB 10
7167 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
7168 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_WIDTH 1
7169 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value. */
7170 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET_MSK 0x00000400
7171 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value. */
7172 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_CLR_MSK 0xfffffbff
7173 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
7174 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_RESET 0x1
7175 /* Extracts the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN field value from a register. */
7176 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
7177 /* Produces a ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value suitable for setting the register. */
7178 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
7179 
7180 /*
7181  * Field : QSPI Clock Enable - qspiclken
7182  *
7183  * Enables QSPI peripheral clock. This enable goes outside of the Clock Manger to
7184  * the QSPI directly.
7185  *
7186  * Field Access Macros:
7187  *
7188  */
7189 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field. */
7190 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_LSB 11
7191 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field. */
7192 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_MSB 11
7193 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field. */
7194 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_WIDTH 1
7195 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field value. */
7196 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_SET_MSK 0x00000800
7197 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field value. */
7198 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_CLR_MSK 0xfffff7ff
7199 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field. */
7200 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_RESET 0x1
7201 /* Extracts the ALT_CLKMGR_PERPLL_ENR_QSPICLKEN field value from a register. */
7202 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
7203 /* Produces a ALT_CLKMGR_PERPLL_ENR_QSPICLKEN register field value suitable for setting the register. */
7204 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
7205 
7206 #ifndef __ASSEMBLY__
7207 /*
7208  * WARNING: The C register and register group struct declarations are provided for
7209  * convenience and illustrative purposes. They should, however, be used with
7210  * caution as the C language standard provides no guarantees about the alignment or
7211  * atomicity of device memory accesses. The recommended practice for writing
7212  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7213  * alt_write_word() functions.
7214  *
7215  * The struct declaration for register ALT_CLKMGR_PERPLL_ENR.
7216  */
7217 struct ALT_CLKMGR_PERPLL_ENR_s
7218 {
7219  uint32_t emac0en : 1; /* emac0_clk Enable */
7220  uint32_t emac1en : 1; /* emac1_clk_clk Enable */
7221  uint32_t emac2en : 1; /* emac2_clk Enable */
7222  uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
7223  uint32_t gpiodben : 1; /* gpio_db_clk Enable */
7224  uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
7225  uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
7226  uint32_t : 1; /* *UNDEFINED* */
7227  uint32_t usbclken : 1; /* USB Clock Enable */
7228  uint32_t spimclken : 1; /* SPIM Clock Enable */
7229  uint32_t nandclken : 1; /* NAND Clock Enable */
7230  uint32_t qspiclken : 1; /* QSPI Clock Enable */
7231  uint32_t : 20; /* *UNDEFINED* */
7232 };
7233 
7234 /* The typedef declaration for register ALT_CLKMGR_PERPLL_ENR. */
7235 typedef volatile struct ALT_CLKMGR_PERPLL_ENR_s ALT_CLKMGR_PERPLL_ENR_t;
7236 #endif /* __ASSEMBLY__ */
7237 
7238 /* The reset value of the ALT_CLKMGR_PERPLL_ENR register. */
7239 #define ALT_CLKMGR_PERPLL_ENR_RESET 0x00000f7f
7240 /* The byte offset of the ALT_CLKMGR_PERPLL_ENR register from the beginning of the component. */
7241 #define ALT_CLKMGR_PERPLL_ENR_OFST 0x10
7242 
7243 /*
7244  * Register : Bypass Register - bypass
7245  *
7246  * Contains fields that control bypass for clocks derived from the Peripheral PLL.
7247  *
7248  * 1: The clock is bypassed.
7249  *
7250  * 0: The clock is derived from the 5:1 active mux.
7251  *
7252  * Register Layout
7253  *
7254  * Bits | Access | Reset | Description
7255  * :-------|:-------|:------|:----------------------
7256  * [0] | RW | 0x1 | EMACA Bypass
7257  * [1] | RW | 0x1 | EMACB Bypass
7258  * [2] | RW | 0x1 | EMAC PTP Bypass
7259  * [3] | RW | 0x1 | GPIO Debounce Bypass
7260  * [4] | RW | 0x1 | SDMMC Bypass
7261  * [5] | RW | 0x1 | S2F User1 Bypass
7262  * [6] | RW | 0x1 | PLL RFEN Clock Bypass
7263  * [7] | RW | 0x1 | PLL FBEN Clock Bypass
7264  * [31:8] | ??? | 0x0 | *UNDEFINED*
7265  *
7266  */
7267 /*
7268  * Field : EMACA Bypass - emaca
7269  *
7270  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
7271  * Main PLL.
7272  *
7273  * Field Access Macros:
7274  *
7275  */
7276 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
7277 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_LSB 0
7278 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
7279 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_MSB 0
7280 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
7281 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_WIDTH 1
7282 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value. */
7283 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET_MSK 0x00000001
7284 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value. */
7285 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_CLR_MSK 0xfffffffe
7286 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
7287 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_RESET 0x1
7288 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACA field value from a register. */
7289 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7290 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value suitable for setting the register. */
7291 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET(value) (((value) << 0) & 0x00000001)
7292 
7293 /*
7294  * Field : EMACB Bypass - emacb
7295  *
7296  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
7297  * Main PLL.
7298  *
7299  * Field Access Macros:
7300  *
7301  */
7302 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
7303 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_LSB 1
7304 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
7305 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_MSB 1
7306 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
7307 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_WIDTH 1
7308 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value. */
7309 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET_MSK 0x00000002
7310 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value. */
7311 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_CLR_MSK 0xfffffffd
7312 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
7313 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_RESET 0x1
7314 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACB field value from a register. */
7315 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7316 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value suitable for setting the register. */
7317 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET(value) (((value) << 1) & 0x00000002)
7318 
7319 /*
7320  * Field : EMAC PTP Bypass - emacptp
7321  *
7322  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
7323  * Peripheral PLL.
7324  *
7325  * Field Access Macros:
7326  *
7327  */
7328 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
7329 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_LSB 2
7330 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
7331 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_MSB 2
7332 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
7333 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_WIDTH 1
7334 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value. */
7335 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET_MSK 0x00000004
7336 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value. */
7337 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_CLR_MSK 0xfffffffb
7338 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
7339 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_RESET 0x1
7340 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP field value from a register. */
7341 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7342 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value suitable for setting the register. */
7343 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7344 
7345 /*
7346  * Field : GPIO Debounce Bypass - gpiodb
7347  *
7348  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
7349  * Peripheral PLL.
7350  *
7351  * Field Access Macros:
7352  *
7353  */
7354 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
7355 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_LSB 3
7356 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
7357 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_MSB 3
7358 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
7359 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_WIDTH 1
7360 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value. */
7361 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET_MSK 0x00000008
7362 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value. */
7363 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_CLR_MSK 0xfffffff7
7364 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
7365 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_RESET 0x1
7366 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_GPIODB field value from a register. */
7367 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7368 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value suitable for setting the register. */
7369 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7370 
7371 /*
7372  * Field : SDMMC Bypass - sdmmc
7373  *
7374  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
7375  * Peripheral PLL.
7376  *
7377  * Field Access Macros:
7378  *
7379  */
7380 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
7381 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_LSB 4
7382 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
7383 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_MSB 4
7384 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
7385 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_WIDTH 1
7386 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value. */
7387 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET_MSK 0x00000010
7388 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value. */
7389 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_CLR_MSK 0xffffffef
7390 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
7391 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_RESET 0x1
7392 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_SDMMC field value from a register. */
7393 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7394 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value suitable for setting the register. */
7395 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7396 
7397 /*
7398  * Field : S2F User1 Bypass - s2fuser1
7399  *
7400  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
7401  * Peripheral PLL.
7402  *
7403  * Field Access Macros:
7404  *
7405  */
7406 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
7407 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_LSB 5
7408 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
7409 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_MSB 5
7410 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
7411 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_WIDTH 1
7412 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value. */
7413 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET_MSK 0x00000020
7414 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value. */
7415 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_CLR_MSK 0xffffffdf
7416 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
7417 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_RESET 0x1
7418 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 field value from a register. */
7419 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7420 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value suitable for setting the register. */
7421 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7422 
7423 /*
7424  * Field : PLL RFEN Clock Bypass - rfen
7425  *
7426  * If set, the pll_peri_rfen_clk will be bypassed to the boot_clk. The
7427  * pll_peri_rfen_clk is used to synchronously update the Denominator to the
7428  * Peripheral PLL.
7429  *
7430  * Field Access Macros:
7431  *
7432  */
7433 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field. */
7434 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_LSB 6
7435 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field. */
7436 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_MSB 6
7437 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field. */
7438 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_WIDTH 1
7439 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field value. */
7440 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_SET_MSK 0x00000040
7441 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field value. */
7442 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_CLR_MSK 0xffffffbf
7443 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_RFEN register field. */
7444 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_RESET 0x1
7445 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_RFEN field value from a register. */
7446 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7447 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_RFEN register field value suitable for setting the register. */
7448 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_SET(value) (((value) << 6) & 0x00000040)
7449 
7450 /*
7451  * Field : PLL FBEN Clock Bypass - fben
7452  *
7453  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
7454  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
7455  *
7456  * Field Access Macros:
7457  *
7458  */
7459 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field. */
7460 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_LSB 7
7461 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field. */
7462 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_MSB 7
7463 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field. */
7464 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_WIDTH 1
7465 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field value. */
7466 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_SET_MSK 0x00000080
7467 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field value. */
7468 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_CLR_MSK 0xffffff7f
7469 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_FBEN register field. */
7470 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_RESET 0x1
7471 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_FBEN field value from a register. */
7472 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7473 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_FBEN register field value suitable for setting the register. */
7474 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_SET(value) (((value) << 7) & 0x00000080)
7475 
7476 #ifndef __ASSEMBLY__
7477 /*
7478  * WARNING: The C register and register group struct declarations are provided for
7479  * convenience and illustrative purposes. They should, however, be used with
7480  * caution as the C language standard provides no guarantees about the alignment or
7481  * atomicity of device memory accesses. The recommended practice for writing
7482  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7483  * alt_write_word() functions.
7484  *
7485  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASS.
7486  */
7487 struct ALT_CLKMGR_PERPLL_BYPASS_s
7488 {
7489  uint32_t emaca : 1; /* EMACA Bypass */
7490  uint32_t emacb : 1; /* EMACB Bypass */
7491  uint32_t emacptp : 1; /* EMAC PTP Bypass */
7492  uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
7493  uint32_t sdmmc : 1; /* SDMMC Bypass */
7494  uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
7495  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
7496  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
7497  uint32_t : 24; /* *UNDEFINED* */
7498 };
7499 
7500 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASS. */
7501 typedef volatile struct ALT_CLKMGR_PERPLL_BYPASS_s ALT_CLKMGR_PERPLL_BYPASS_t;
7502 #endif /* __ASSEMBLY__ */
7503 
7504 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS register. */
7505 #define ALT_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
7506 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASS register from the beginning of the component. */
7507 #define ALT_CLKMGR_PERPLL_BYPASS_OFST 0x14
7508 
7509 /*
7510  * Register : Bypass Set Register - bypasss
7511  *
7512  * Write One to Set corresponding fields in Bypass Register.
7513  *
7514  * Register Layout
7515  *
7516  * Bits | Access | Reset | Description
7517  * :-------|:-------|:------|:----------------------
7518  * [0] | RW | 0x1 | EMACA Bypass
7519  * [1] | RW | 0x1 | EMACB Bypass
7520  * [2] | RW | 0x1 | EMAC PTP Bypass
7521  * [3] | RW | 0x1 | GPIO Debounce Bypass
7522  * [4] | RW | 0x1 | SDMMC Bypass
7523  * [5] | RW | 0x1 | S2F User1 Bypass
7524  * [6] | RW | 0x1 | PLL RFEN Clock Bypass
7525  * [7] | RW | 0x1 | PLL FBEN Clock Bypass
7526  * [31:8] | ??? | 0x0 | *UNDEFINED*
7527  *
7528  */
7529 /*
7530  * Field : EMACA Bypass - emaca
7531  *
7532  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
7533  * Periphal PLL.
7534  *
7535  * Field Access Macros:
7536  *
7537  */
7538 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
7539 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_LSB 0
7540 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
7541 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_MSB 0
7542 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
7543 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_WIDTH 1
7544 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value. */
7545 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET_MSK 0x00000001
7546 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value. */
7547 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_CLR_MSK 0xfffffffe
7548 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
7549 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_RESET 0x1
7550 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACA field value from a register. */
7551 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7552 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value suitable for setting the register. */
7553 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET(value) (((value) << 0) & 0x00000001)
7554 
7555 /*
7556  * Field : EMACB Bypass - emacb
7557  *
7558  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
7559  * Main PLL.
7560  *
7561  * Field Access Macros:
7562  *
7563  */
7564 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
7565 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_LSB 1
7566 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
7567 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_MSB 1
7568 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
7569 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_WIDTH 1
7570 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value. */
7571 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET_MSK 0x00000002
7572 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value. */
7573 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_CLR_MSK 0xfffffffd
7574 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
7575 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_RESET 0x1
7576 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACB field value from a register. */
7577 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7578 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value suitable for setting the register. */
7579 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET(value) (((value) << 1) & 0x00000002)
7580 
7581 /*
7582  * Field : EMAC PTP Bypass - emacptp
7583  *
7584  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
7585  * Peripheral PLL.
7586  *
7587  * Field Access Macros:
7588  *
7589  */
7590 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
7591 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_LSB 2
7592 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
7593 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_MSB 2
7594 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
7595 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_WIDTH 1
7596 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value. */
7597 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET_MSK 0x00000004
7598 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value. */
7599 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_CLR_MSK 0xfffffffb
7600 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
7601 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_RESET 0x1
7602 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP field value from a register. */
7603 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7604 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value suitable for setting the register. */
7605 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7606 
7607 /*
7608  * Field : GPIO Debounce Bypass - gpiodb
7609  *
7610  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
7611  * Peripheral PLL.
7612  *
7613  * Field Access Macros:
7614  *
7615  */
7616 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
7617 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_LSB 3
7618 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
7619 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_MSB 3
7620 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
7621 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_WIDTH 1
7622 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value. */
7623 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET_MSK 0x00000008
7624 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value. */
7625 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_CLR_MSK 0xfffffff7
7626 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
7627 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_RESET 0x1
7628 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB field value from a register. */
7629 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7630 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value suitable for setting the register. */
7631 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7632 
7633 /*
7634  * Field : SDMMC Bypass - sdmmc
7635  *
7636  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
7637  * Peripheral PLL.
7638  *
7639  * Field Access Macros:
7640  *
7641  */
7642 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
7643 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_LSB 4
7644 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
7645 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_MSB 4
7646 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
7647 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_WIDTH 1
7648 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value. */
7649 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET_MSK 0x00000010
7650 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value. */
7651 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_CLR_MSK 0xffffffef
7652 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
7653 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_RESET 0x1
7654 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC field value from a register. */
7655 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7656 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value suitable for setting the register. */
7657 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7658 
7659 /*
7660  * Field : S2F User1 Bypass - s2fuser1
7661  *
7662  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
7663  * Peripheral PLL.
7664  *
7665  * Field Access Macros:
7666  *
7667  */
7668 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
7669 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_LSB 5
7670 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
7671 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_MSB 5
7672 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
7673 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_WIDTH 1
7674 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value. */
7675 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET_MSK 0x00000020
7676 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value. */
7677 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_CLR_MSK 0xffffffdf
7678 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
7679 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_RESET 0x1
7680 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 field value from a register. */
7681 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7682 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value suitable for setting the register. */
7683 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7684 
7685 /*
7686  * Field : PLL RFEN Clock Bypass - rfen
7687  *
7688  * If set, the pll_peri_rfen_clk will be bypassed to the boot_clk. The
7689  * pll_peri_rfen_clk is used to synchronously update the Denominator to the
7690  * Peripheral PLL.
7691  *
7692  * Field Access Macros:
7693  *
7694  */
7695 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field. */
7696 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_LSB 6
7697 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field. */
7698 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_MSB 6
7699 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field. */
7700 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_WIDTH 1
7701 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field value. */
7702 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_SET_MSK 0x00000040
7703 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field value. */
7704 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_CLR_MSK 0xffffffbf
7705 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field. */
7706 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_RESET 0x1
7707 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_RFEN field value from a register. */
7708 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7709 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_RFEN register field value suitable for setting the register. */
7710 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_SET(value) (((value) << 6) & 0x00000040)
7711 
7712 /*
7713  * Field : PLL FBEN Clock Bypass - fben
7714  *
7715  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
7716  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
7717  *
7718  * Field Access Macros:
7719  *
7720  */
7721 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field. */
7722 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_LSB 7
7723 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field. */
7724 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_MSB 7
7725 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field. */
7726 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_WIDTH 1
7727 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field value. */
7728 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_SET_MSK 0x00000080
7729 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field value. */
7730 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_CLR_MSK 0xffffff7f
7731 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field. */
7732 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_RESET 0x1
7733 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_FBEN field value from a register. */
7734 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7735 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_FBEN register field value suitable for setting the register. */
7736 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_SET(value) (((value) << 7) & 0x00000080)
7737 
7738 #ifndef __ASSEMBLY__
7739 /*
7740  * WARNING: The C register and register group struct declarations are provided for
7741  * convenience and illustrative purposes. They should, however, be used with
7742  * caution as the C language standard provides no guarantees about the alignment or
7743  * atomicity of device memory accesses. The recommended practice for writing
7744  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7745  * alt_write_word() functions.
7746  *
7747  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASSS.
7748  */
7749 struct ALT_CLKMGR_PERPLL_BYPASSS_s
7750 {
7751  uint32_t emaca : 1; /* EMACA Bypass */
7752  uint32_t emacb : 1; /* EMACB Bypass */
7753  uint32_t emacptp : 1; /* EMAC PTP Bypass */
7754  uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
7755  uint32_t sdmmc : 1; /* SDMMC Bypass */
7756  uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
7757  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
7758  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
7759  uint32_t : 24; /* *UNDEFINED* */
7760 };
7761 
7762 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASSS. */
7763 typedef volatile struct ALT_CLKMGR_PERPLL_BYPASSS_s ALT_CLKMGR_PERPLL_BYPASSS_t;
7764 #endif /* __ASSEMBLY__ */
7765 
7766 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS register. */
7767 #define ALT_CLKMGR_PERPLL_BYPASSS_RESET 0x000000ff
7768 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASSS register from the beginning of the component. */
7769 #define ALT_CLKMGR_PERPLL_BYPASSS_OFST 0x18
7770 
7771 /*
7772  * Register : Bypass Reset Register - bypassr
7773  *
7774  * Write One to Clear corresponding fields in Bypass Register.
7775  *
7776  * Register Layout
7777  *
7778  * Bits | Access | Reset | Description
7779  * :-------|:-------|:------|:----------------------
7780  * [0] | RW | 0x1 | EMACA Bypass
7781  * [1] | RW | 0x1 | EMACB Bypass
7782  * [2] | RW | 0x1 | EMAC PTP Bypass
7783  * [3] | RW | 0x1 | GPIO Debounce Bypass
7784  * [4] | RW | 0x1 | SDMMC Bypass
7785  * [5] | RW | 0x1 | S2F User1 Bypass
7786  * [6] | RW | 0x1 | PLL RFEN Clock Bypass
7787  * [7] | RW | 0x1 | PLL FBEN Clock Bypass
7788  * [31:8] | ??? | 0x0 | *UNDEFINED*
7789  *
7790  */
7791 /*
7792  * Field : EMACA Bypass - emaca
7793  *
7794  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
7795  * Periphal PLL.
7796  *
7797  * Field Access Macros:
7798  *
7799  */
7800 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
7801 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_LSB 0
7802 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
7803 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_MSB 0
7804 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
7805 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_WIDTH 1
7806 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value. */
7807 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET_MSK 0x00000001
7808 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value. */
7809 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_CLR_MSK 0xfffffffe
7810 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
7811 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_RESET 0x1
7812 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACA field value from a register. */
7813 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7814 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value suitable for setting the register. */
7815 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET(value) (((value) << 0) & 0x00000001)
7816 
7817 /*
7818  * Field : EMACB Bypass - emacb
7819  *
7820  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
7821  * Main PLL.
7822  *
7823  * Field Access Macros:
7824  *
7825  */
7826 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
7827 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_LSB 1
7828 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
7829 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_MSB 1
7830 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
7831 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_WIDTH 1
7832 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value. */
7833 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET_MSK 0x00000002
7834 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value. */
7835 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_CLR_MSK 0xfffffffd
7836 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
7837 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_RESET 0x1
7838 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACB field value from a register. */
7839 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7840 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value suitable for setting the register. */
7841 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET(value) (((value) << 1) & 0x00000002)
7842 
7843 /*
7844  * Field : EMAC PTP Bypass - emacptp
7845  *
7846  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
7847  * Peripheral PLL.
7848  *
7849  * Field Access Macros:
7850  *
7851  */
7852 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
7853 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_LSB 2
7854 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
7855 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_MSB 2
7856 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
7857 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_WIDTH 1
7858 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value. */
7859 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET_MSK 0x00000004
7860 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value. */
7861 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_CLR_MSK 0xfffffffb
7862 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
7863 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_RESET 0x1
7864 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP field value from a register. */
7865 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7866 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value suitable for setting the register. */
7867 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7868 
7869 /*
7870  * Field : GPIO Debounce Bypass - gpiodb
7871  *
7872  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
7873  * Peripheral PLL.
7874  *
7875  * Field Access Macros:
7876  *
7877  */
7878 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
7879 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_LSB 3
7880 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
7881 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_MSB 3
7882 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
7883 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_WIDTH 1
7884 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value. */
7885 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET_MSK 0x00000008
7886 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value. */
7887 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_CLR_MSK 0xfffffff7
7888 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
7889 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_RESET 0x1
7890 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB field value from a register. */
7891 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7892 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value suitable for setting the register. */
7893 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7894 
7895 /*
7896  * Field : SDMMC Bypass - sdmmc
7897  *
7898  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
7899  * Peripheral PLL.
7900  *
7901  * Field Access Macros:
7902  *
7903  */
7904 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
7905 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_LSB 4
7906 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
7907 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_MSB 4
7908 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
7909 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_WIDTH 1
7910 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value. */
7911 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET_MSK 0x00000010
7912 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value. */
7913 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_CLR_MSK 0xffffffef
7914 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
7915 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_RESET 0x1
7916 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC field value from a register. */
7917 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7918 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value suitable for setting the register. */
7919 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7920 
7921 /*
7922  * Field : S2F User1 Bypass - s2fuser1
7923  *
7924  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
7925  * Peripheral PLL.
7926  *
7927  * Field Access Macros:
7928  *
7929  */
7930 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
7931 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_LSB 5
7932 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
7933 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_MSB 5
7934 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
7935 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_WIDTH 1
7936 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value. */
7937 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET_MSK 0x00000020
7938 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value. */
7939 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_CLR_MSK 0xffffffdf
7940 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
7941 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_RESET 0x1
7942 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 field value from a register. */
7943 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7944 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value suitable for setting the register. */
7945 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7946 
7947 /*
7948  * Field : PLL RFEN Clock Bypass - rfen
7949  *
7950  * If set, the pll_peri_rfen_clk will be bypassed to the boot_clk. The
7951  * pll_peri_rfen_clk is used to synchronously update the Denominator to the
7952  * Peripheral PLL.
7953  *
7954  * Field Access Macros:
7955  *
7956  */
7957 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field. */
7958 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_LSB 6
7959 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field. */
7960 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_MSB 6
7961 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field. */
7962 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_WIDTH 1
7963 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field value. */
7964 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_SET_MSK 0x00000040
7965 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field value. */
7966 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_CLR_MSK 0xffffffbf
7967 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field. */
7968 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_RESET 0x1
7969 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_RFEN field value from a register. */
7970 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7971 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_RFEN register field value suitable for setting the register. */
7972 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_SET(value) (((value) << 6) & 0x00000040)
7973 
7974 /*
7975  * Field : PLL FBEN Clock Bypass - fben
7976  *
7977  * If set, the pll_main_fben_clk will be bypassed to the boot_clk. The
7978  * pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
7979  *
7980  * Field Access Macros:
7981  *
7982  */
7983 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field. */
7984 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_LSB 7
7985 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field. */
7986 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_MSB 7
7987 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field. */
7988 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_WIDTH 1
7989 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field value. */
7990 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_SET_MSK 0x00000080
7991 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field value. */
7992 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_CLR_MSK 0xffffff7f
7993 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field. */
7994 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_RESET 0x1
7995 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_FBEN field value from a register. */
7996 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7997 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_FBEN register field value suitable for setting the register. */
7998 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_SET(value) (((value) << 7) & 0x00000080)
7999 
8000 #ifndef __ASSEMBLY__
8001 /*
8002  * WARNING: The C register and register group struct declarations are provided for
8003  * convenience and illustrative purposes. They should, however, be used with
8004  * caution as the C language standard provides no guarantees about the alignment or
8005  * atomicity of device memory accesses. The recommended practice for writing
8006  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8007  * alt_write_word() functions.
8008  *
8009  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASSR.
8010  */
8011 struct ALT_CLKMGR_PERPLL_BYPASSR_s
8012 {
8013  uint32_t emaca : 1; /* EMACA Bypass */
8014  uint32_t emacb : 1; /* EMACB Bypass */
8015  uint32_t emacptp : 1; /* EMAC PTP Bypass */
8016  uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
8017  uint32_t sdmmc : 1; /* SDMMC Bypass */
8018  uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
8019  uint32_t rfen : 1; /* PLL RFEN Clock Bypass */
8020  uint32_t fben : 1; /* PLL FBEN Clock Bypass */
8021  uint32_t : 24; /* *UNDEFINED* */
8022 };
8023 
8024 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASSR. */
8025 typedef volatile struct ALT_CLKMGR_PERPLL_BYPASSR_s ALT_CLKMGR_PERPLL_BYPASSR_t;
8026 #endif /* __ASSEMBLY__ */
8027 
8028 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR register. */
8029 #define ALT_CLKMGR_PERPLL_BYPASSR_RESET 0x000000ff
8030 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASSR register from the beginning of the component. */
8031 #define ALT_CLKMGR_PERPLL_BYPASSR_OFST 0x1c
8032 
8033 /*
8034  * Register : Peripheral PLL Control Register for Counter 2 Clock - cntr2clk
8035  *
8036  * Contains settings that control Couner 2 clock generated from the Peripheral PLL
8037  * VCO clock.
8038  *
8039  * Register Layout
8040  *
8041  * Bits | Access | Reset | Description
8042  * :--------|:-------|:------|:-------------------------------
8043  * [10:0] | RW | 0x0 | Counter
8044  * [15:11] | ??? | 0x0 | *UNDEFINED*
8045  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8046  * [31:19] | ??? | 0x0 | *UNDEFINED*
8047  *
8048  */
8049 /*
8050  * Field : Counter - cnt
8051  *
8052  * Divides the VCO frequency by the value+1 in this field.
8053  *
8054  * Field Access Macros:
8055  *
8056  */
8057 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
8058 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_LSB 0
8059 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
8060 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_MSB 10
8061 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
8062 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_WIDTH 11
8063 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value. */
8064 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
8065 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value. */
8066 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
8067 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
8068 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_RESET 0x0
8069 /* Extracts the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT field value from a register. */
8070 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8071 /* Produces a ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value suitable for setting the register. */
8072 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8073 
8074 /*
8075  * Field : src
8076  *
8077  * Selects the source for the active 5:1 clock selection when the PLL is not
8078  * bypassed.
8079  *
8080  * Field Enumeration Values:
8081  *
8082  * Enum | Value | Description
8083  * :----------------------------------------|:------|:------------
8084  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN | 0x0 |
8085  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI | 0x1 |
8086  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 | 0x2 |
8087  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC | 0x3 |
8088  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA | 0x4 |
8089  *
8090  * Field Access Macros:
8091  *
8092  */
8093 /*
8094  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8095  *
8096  */
8097 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN 0x0
8098 /*
8099  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8100  *
8101  */
8102 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI 0x1
8103 /*
8104  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8105  *
8106  */
8107 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 0x2
8108 /*
8109  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8110  *
8111  */
8112 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC 0x3
8113 /*
8114  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
8115  *
8116  */
8117 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA 0x4
8118 
8119 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
8120 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
8121 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
8122 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_MSB 18
8123 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
8124 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_WIDTH 3
8125 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value. */
8126 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET_MSK 0x00070000
8127 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value. */
8128 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_CLR_MSK 0xfff8ffff
8129 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
8130 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_RESET 0x0
8131 /* Extracts the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC field value from a register. */
8132 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8133 /* Produces a ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value suitable for setting the register. */
8134 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8135 
8136 #ifndef __ASSEMBLY__
8137 /*
8138  * WARNING: The C register and register group struct declarations are provided for
8139  * convenience and illustrative purposes. They should, however, be used with
8140  * caution as the C language standard provides no guarantees about the alignment or
8141  * atomicity of device memory accesses. The recommended practice for writing
8142  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8143  * alt_write_word() functions.
8144  *
8145  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR2CLK.
8146  */
8147 struct ALT_CLKMGR_PERPLL_CNTR2CLK_s
8148 {
8149  uint32_t cnt : 11; /* Counter */
8150  uint32_t : 5; /* *UNDEFINED* */
8151  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR2CLK_SRC */
8152  uint32_t : 13; /* *UNDEFINED* */
8153 };
8154 
8155 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR2CLK. */
8156 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR2CLK_s ALT_CLKMGR_PERPLL_CNTR2CLK_t;
8157 #endif /* __ASSEMBLY__ */
8158 
8159 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK register. */
8160 #define ALT_CLKMGR_PERPLL_CNTR2CLK_RESET 0x00000000
8161 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR2CLK register from the beginning of the component. */
8162 #define ALT_CLKMGR_PERPLL_CNTR2CLK_OFST 0x28
8163 
8164 /*
8165  * Register : Peripheral PLL Control Register for Counter 3 Clock - cntr3clk
8166  *
8167  * Contains settings that control Counter 3 clock generated from the Peripheral PLL
8168  * VCO clock.
8169  *
8170  * Register Layout
8171  *
8172  * Bits | Access | Reset | Description
8173  * :--------|:-------|:------|:-------------------------------
8174  * [10:0] | RW | 0x0 | Counter
8175  * [15:11] | ??? | 0x0 | *UNDEFINED*
8176  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8177  * [31:19] | ??? | 0x0 | *UNDEFINED*
8178  *
8179  */
8180 /*
8181  * Field : Counter - cnt
8182  *
8183  * Divides the VCO frequency by the value+1 in this field.
8184  *
8185  * Field Access Macros:
8186  *
8187  */
8188 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
8189 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_LSB 0
8190 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
8191 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_MSB 10
8192 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
8193 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_WIDTH 11
8194 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value. */
8195 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
8196 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value. */
8197 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
8198 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
8199 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_RESET 0x0
8200 /* Extracts the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT field value from a register. */
8201 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8202 /* Produces a ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value suitable for setting the register. */
8203 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8204 
8205 /*
8206  * Field : src
8207  *
8208  * Selects the source for the active 5:1 clock selection when the PLL is not
8209  * bypassed.
8210  *
8211  * Field Enumeration Values:
8212  *
8213  * Enum | Value | Description
8214  * :----------------------------------------|:------|:------------
8215  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN | 0x0 |
8216  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI | 0x1 |
8217  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 | 0x2 |
8218  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC | 0x3 |
8219  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA | 0x4 |
8220  *
8221  * Field Access Macros:
8222  *
8223  */
8224 /*
8225  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8226  *
8227  */
8228 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN 0x0
8229 /*
8230  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8231  *
8232  */
8233 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI 0x1
8234 /*
8235  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8236  *
8237  */
8238 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 0x2
8239 /*
8240  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8241  *
8242  */
8243 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC 0x3
8244 /*
8245  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
8246  *
8247  */
8248 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA 0x4
8249 
8250 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
8251 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
8252 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
8253 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_MSB 18
8254 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
8255 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_WIDTH 3
8256 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value. */
8257 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET_MSK 0x00070000
8258 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value. */
8259 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_CLR_MSK 0xfff8ffff
8260 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
8261 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_RESET 0x0
8262 /* Extracts the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC field value from a register. */
8263 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8264 /* Produces a ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value suitable for setting the register. */
8265 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8266 
8267 #ifndef __ASSEMBLY__
8268 /*
8269  * WARNING: The C register and register group struct declarations are provided for
8270  * convenience and illustrative purposes. They should, however, be used with
8271  * caution as the C language standard provides no guarantees about the alignment or
8272  * atomicity of device memory accesses. The recommended practice for writing
8273  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8274  * alt_write_word() functions.
8275  *
8276  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR3CLK.
8277  */
8278 struct ALT_CLKMGR_PERPLL_CNTR3CLK_s
8279 {
8280  uint32_t cnt : 11; /* Counter */
8281  uint32_t : 5; /* *UNDEFINED* */
8282  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR3CLK_SRC */
8283  uint32_t : 13; /* *UNDEFINED* */
8284 };
8285 
8286 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR3CLK. */
8287 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR3CLK_s ALT_CLKMGR_PERPLL_CNTR3CLK_t;
8288 #endif /* __ASSEMBLY__ */
8289 
8290 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK register. */
8291 #define ALT_CLKMGR_PERPLL_CNTR3CLK_RESET 0x00000000
8292 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR3CLK register from the beginning of the component. */
8293 #define ALT_CLKMGR_PERPLL_CNTR3CLK_OFST 0x2c
8294 
8295 /*
8296  * Register : Peripheral PLL Control Register for Counter 4 Clock - cntr4clk
8297  *
8298  * Contains settings that control Couner 4 clock generated from the Peripheral PLL
8299  * VCO clock.
8300  *
8301  * Register Layout
8302  *
8303  * Bits | Access | Reset | Description
8304  * :--------|:-------|:------|:-------------------------------
8305  * [10:0] | RW | 0x0 | Counter
8306  * [15:11] | ??? | 0x0 | *UNDEFINED*
8307  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8308  * [31:19] | ??? | 0x0 | *UNDEFINED*
8309  *
8310  */
8311 /*
8312  * Field : Counter - cnt
8313  *
8314  * Divides the VCO frequency by the value+1 in this field.
8315  *
8316  * Field Access Macros:
8317  *
8318  */
8319 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
8320 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_LSB 0
8321 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
8322 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_MSB 10
8323 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
8324 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_WIDTH 11
8325 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value. */
8326 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
8327 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value. */
8328 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
8329 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
8330 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_RESET 0x0
8331 /* Extracts the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT field value from a register. */
8332 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8333 /* Produces a ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value suitable for setting the register. */
8334 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8335 
8336 /*
8337  * Field : src
8338  *
8339  * Selects the source for the active 5:1 clock selection when the PLL is not
8340  * bypassed.
8341  *
8342  * Field Enumeration Values:
8343  *
8344  * Enum | Value | Description
8345  * :----------------------------------------|:------|:------------
8346  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN | 0x0 |
8347  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI | 0x1 |
8348  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 | 0x2 |
8349  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC | 0x3 |
8350  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA | 0x4 |
8351  *
8352  * Field Access Macros:
8353  *
8354  */
8355 /*
8356  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8357  *
8358  */
8359 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN 0x0
8360 /*
8361  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8362  *
8363  */
8364 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI 0x1
8365 /*
8366  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8367  *
8368  */
8369 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 0x2
8370 /*
8371  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8372  *
8373  */
8374 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC 0x3
8375 /*
8376  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
8377  *
8378  */
8379 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA 0x4
8380 
8381 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
8382 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
8383 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
8384 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_MSB 18
8385 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
8386 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_WIDTH 3
8387 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value. */
8388 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET_MSK 0x00070000
8389 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value. */
8390 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_CLR_MSK 0xfff8ffff
8391 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
8392 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_RESET 0x0
8393 /* Extracts the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC field value from a register. */
8394 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8395 /* Produces a ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value suitable for setting the register. */
8396 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8397 
8398 #ifndef __ASSEMBLY__
8399 /*
8400  * WARNING: The C register and register group struct declarations are provided for
8401  * convenience and illustrative purposes. They should, however, be used with
8402  * caution as the C language standard provides no guarantees about the alignment or
8403  * atomicity of device memory accesses. The recommended practice for writing
8404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8405  * alt_write_word() functions.
8406  *
8407  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR4CLK.
8408  */
8409 struct ALT_CLKMGR_PERPLL_CNTR4CLK_s
8410 {
8411  uint32_t cnt : 11; /* Counter */
8412  uint32_t : 5; /* *UNDEFINED* */
8413  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR4CLK_SRC */
8414  uint32_t : 13; /* *UNDEFINED* */
8415 };
8416 
8417 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR4CLK. */
8418 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR4CLK_s ALT_CLKMGR_PERPLL_CNTR4CLK_t;
8419 #endif /* __ASSEMBLY__ */
8420 
8421 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK register. */
8422 #define ALT_CLKMGR_PERPLL_CNTR4CLK_RESET 0x00000000
8423 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR4CLK register from the beginning of the component. */
8424 #define ALT_CLKMGR_PERPLL_CNTR4CLK_OFST 0x30
8425 
8426 /*
8427  * Register : Peripheral PLL Control Register for Counter 5 Clock - cntr5clk
8428  *
8429  * Contains settings that control Couner 5 clock generated from the Peripheral PLL
8430  * VCO clock.
8431  *
8432  * Register Layout
8433  *
8434  * Bits | Access | Reset | Description
8435  * :--------|:-------|:------|:-------------------------------
8436  * [10:0] | RW | 0x0 | Counter
8437  * [15:11] | ??? | 0x0 | *UNDEFINED*
8438  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8439  * [31:19] | ??? | 0x0 | *UNDEFINED*
8440  *
8441  */
8442 /*
8443  * Field : Counter - cnt
8444  *
8445  * Divides the VCO frequency by the value+1 in this field.
8446  *
8447  * Field Access Macros:
8448  *
8449  */
8450 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
8451 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0
8452 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
8453 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10
8454 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
8455 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11
8456 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value. */
8457 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
8458 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value. */
8459 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
8460 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
8461 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x0
8462 /* Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT field value from a register. */
8463 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8464 /* Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value suitable for setting the register. */
8465 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8466 
8467 /*
8468  * Field : src
8469  *
8470  * Selects the source for the active 5:1 clock selection when the PLL is not
8471  * bypassed.
8472  *
8473  * Field Enumeration Values:
8474  *
8475  * Enum | Value | Description
8476  * :----------------------------------------|:------|:------------
8477  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN | 0x0 |
8478  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI | 0x1 |
8479  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 | 0x2 |
8480  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC | 0x3 |
8481  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA | 0x4 |
8482  *
8483  * Field Access Macros:
8484  *
8485  */
8486 /*
8487  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8488  *
8489  */
8490 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN 0x0
8491 /*
8492  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8493  *
8494  */
8495 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI 0x1
8496 /*
8497  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8498  *
8499  */
8500 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 0x2
8501 /*
8502  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8503  *
8504  */
8505 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC 0x3
8506 /*
8507  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
8508  *
8509  */
8510 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA 0x4
8511 
8512 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
8513 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
8514 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
8515 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_MSB 18
8516 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
8517 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_WIDTH 3
8518 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value. */
8519 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET_MSK 0x00070000
8520 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value. */
8521 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_CLR_MSK 0xfff8ffff
8522 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
8523 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_RESET 0x0
8524 /* Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC field value from a register. */
8525 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8526 /* Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value suitable for setting the register. */
8527 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8528 
8529 #ifndef __ASSEMBLY__
8530 /*
8531  * WARNING: The C register and register group struct declarations are provided for
8532  * convenience and illustrative purposes. They should, however, be used with
8533  * caution as the C language standard provides no guarantees about the alignment or
8534  * atomicity of device memory accesses. The recommended practice for writing
8535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8536  * alt_write_word() functions.
8537  *
8538  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK.
8539  */
8540 struct ALT_CLKMGR_PERPLL_CNTR5CLK_s
8541 {
8542  uint32_t cnt : 11; /* Counter */
8543  uint32_t : 5; /* *UNDEFINED* */
8544  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR5CLK_SRC */
8545  uint32_t : 13; /* *UNDEFINED* */
8546 };
8547 
8548 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK. */
8549 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR5CLK_s ALT_CLKMGR_PERPLL_CNTR5CLK_t;
8550 #endif /* __ASSEMBLY__ */
8551 
8552 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK register. */
8553 #define ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000000
8554 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR5CLK register from the beginning of the component. */
8555 #define ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x34
8556 
8557 /*
8558  * Register : Peripheral PLL Control Register for Counter 6 Clock - cntr6clk
8559  *
8560  * Contains settings that control Couner 6 clock generated from the Peripheral PLL
8561  * VCO clock.
8562  *
8563  * Register Layout
8564  *
8565  * Bits | Access | Reset | Description
8566  * :--------|:-------|:------|:-------------------------------
8567  * [10:0] | RW | 0x0 | Counter
8568  * [15:11] | ??? | 0x0 | *UNDEFINED*
8569  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8570  * [31:19] | ??? | 0x0 | *UNDEFINED*
8571  *
8572  */
8573 /*
8574  * Field : Counter - cnt
8575  *
8576  * Divides the VCO frequency by the value+1 in this field.
8577  *
8578  * Field Access Macros:
8579  *
8580  */
8581 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
8582 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_LSB 0
8583 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
8584 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_MSB 10
8585 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
8586 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_WIDTH 11
8587 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value. */
8588 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
8589 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value. */
8590 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
8591 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
8592 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_RESET 0x0
8593 /* Extracts the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT field value from a register. */
8594 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8595 /* Produces a ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value suitable for setting the register. */
8596 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8597 
8598 /*
8599  * Field : src
8600  *
8601  * Selects the source for the active 5:1 clock selection when the PLL is not
8602  * bypassed.
8603  *
8604  * Field Enumeration Values:
8605  *
8606  * Enum | Value | Description
8607  * :----------------------------------------|:------|:------------
8608  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN | 0x0 |
8609  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI | 0x1 |
8610  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 | 0x2 |
8611  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC | 0x3 |
8612  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA | 0x4 |
8613  *
8614  * Field Access Macros:
8615  *
8616  */
8617 /*
8618  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8619  *
8620  */
8621 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN 0x0
8622 /*
8623  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8624  *
8625  */
8626 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI 0x1
8627 /*
8628  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8629  *
8630  */
8631 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 0x2
8632 /*
8633  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8634  *
8635  */
8636 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC 0x3
8637 /*
8638  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
8639  *
8640  */
8641 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA 0x4
8642 
8643 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
8644 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
8645 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
8646 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_MSB 18
8647 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
8648 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_WIDTH 3
8649 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value. */
8650 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET_MSK 0x00070000
8651 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value. */
8652 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_CLR_MSK 0xfff8ffff
8653 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
8654 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_RESET 0x0
8655 /* Extracts the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC field value from a register. */
8656 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8657 /* Produces a ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value suitable for setting the register. */
8658 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8659 
8660 #ifndef __ASSEMBLY__
8661 /*
8662  * WARNING: The C register and register group struct declarations are provided for
8663  * convenience and illustrative purposes. They should, however, be used with
8664  * caution as the C language standard provides no guarantees about the alignment or
8665  * atomicity of device memory accesses. The recommended practice for writing
8666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8667  * alt_write_word() functions.
8668  *
8669  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR6CLK.
8670  */
8671 struct ALT_CLKMGR_PERPLL_CNTR6CLK_s
8672 {
8673  uint32_t cnt : 11; /* Counter */
8674  uint32_t : 5; /* *UNDEFINED* */
8675  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR6CLK_SRC */
8676  uint32_t : 13; /* *UNDEFINED* */
8677 };
8678 
8679 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR6CLK. */
8680 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR6CLK_s ALT_CLKMGR_PERPLL_CNTR6CLK_t;
8681 #endif /* __ASSEMBLY__ */
8682 
8683 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK register. */
8684 #define ALT_CLKMGR_PERPLL_CNTR6CLK_RESET 0x00000000
8685 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR6CLK register from the beginning of the component. */
8686 #define ALT_CLKMGR_PERPLL_CNTR6CLK_OFST 0x38
8687 
8688 /*
8689  * Register : Peripheral PLL Control Register for Counter 7 Clock - cntr7clk
8690  *
8691  * Contains settings that control Couner 7 clock generated from the Peripheral PLL
8692  * VCO clock.
8693  *
8694  * Register Layout
8695  *
8696  * Bits | Access | Reset | Description
8697  * :--------|:-------|:------|:------------
8698  * [10:0] | RW | 0x0 | Counter
8699  * [31:11] | ??? | 0x0 | *UNDEFINED*
8700  *
8701  */
8702 /*
8703  * Field : Counter - cnt
8704  *
8705  * Divides the VCO frequency by the value+1 in this field.
8706  *
8707  * Field Access Macros:
8708  *
8709  */
8710 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
8711 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_LSB 0
8712 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
8713 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_MSB 10
8714 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
8715 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_WIDTH 11
8716 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value. */
8717 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
8718 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value. */
8719 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
8720 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
8721 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_RESET 0x0
8722 /* Extracts the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT field value from a register. */
8723 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8724 /* Produces a ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value suitable for setting the register. */
8725 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8726 
8727 #ifndef __ASSEMBLY__
8728 /*
8729  * WARNING: The C register and register group struct declarations are provided for
8730  * convenience and illustrative purposes. They should, however, be used with
8731  * caution as the C language standard provides no guarantees about the alignment or
8732  * atomicity of device memory accesses. The recommended practice for writing
8733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8734  * alt_write_word() functions.
8735  *
8736  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR7CLK.
8737  */
8738 struct ALT_CLKMGR_PERPLL_CNTR7CLK_s
8739 {
8740  uint32_t cnt : 11; /* Counter */
8741  uint32_t : 21; /* *UNDEFINED* */
8742 };
8743 
8744 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR7CLK. */
8745 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR7CLK_s ALT_CLKMGR_PERPLL_CNTR7CLK_t;
8746 #endif /* __ASSEMBLY__ */
8747 
8748 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR7CLK register. */
8749 #define ALT_CLKMGR_PERPLL_CNTR7CLK_RESET 0x00000000
8750 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR7CLK register from the beginning of the component. */
8751 #define ALT_CLKMGR_PERPLL_CNTR7CLK_OFST 0x3c
8752 
8753 /*
8754  * Register : Peripheral PLL Control Register for Counter 8 Clock - cntr8clk
8755  *
8756  * Contains settings that control Couner 8 clock generated from the Peripheral PLL
8757  * VCO clock.
8758  *
8759  * Register Layout
8760  *
8761  * Bits | Access | Reset | Description
8762  * :--------|:-------|:------|:-------------------------------
8763  * [10:0] | RW | 0x0 | Counter
8764  * [15:11] | ??? | 0x0 | *UNDEFINED*
8765  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8766  * [31:19] | ??? | 0x0 | *UNDEFINED*
8767  *
8768  */
8769 /*
8770  * Field : Counter - cnt
8771  *
8772  * Divides the VCO frequency by the value+1 in this field.
8773  *
8774  * Field Access Macros:
8775  *
8776  */
8777 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
8778 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_LSB 0
8779 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
8780 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_MSB 10
8781 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
8782 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_WIDTH 11
8783 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value. */
8784 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
8785 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value. */
8786 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
8787 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
8788 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_RESET 0x0
8789 /* Extracts the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT field value from a register. */
8790 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8791 /* Produces a ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value suitable for setting the register. */
8792 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8793 
8794 /*
8795  * Field : src
8796  *
8797  * Selects the source for the active 5:1 clock selection when the PLL is not
8798  * bypassed.
8799  *
8800  * Field Enumeration Values:
8801  *
8802  * Enum | Value | Description
8803  * :----------------------------------------|:------|:------------
8804  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN | 0x0 |
8805  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI | 0x1 |
8806  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 | 0x2 |
8807  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC | 0x3 |
8808  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA | 0x4 |
8809  *
8810  * Field Access Macros:
8811  *
8812  */
8813 /*
8814  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8815  *
8816  */
8817 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN 0x0
8818 /*
8819  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8820  *
8821  */
8822 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI 0x1
8823 /*
8824  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8825  *
8826  */
8827 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 0x2
8828 /*
8829  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8830  *
8831  */
8832 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC 0x3
8833 /*
8834  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
8835  *
8836  */
8837 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA 0x4
8838 
8839 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
8840 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
8841 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
8842 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_MSB 18
8843 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
8844 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_WIDTH 3
8845 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value. */
8846 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET_MSK 0x00070000
8847 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value. */
8848 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_CLR_MSK 0xfff8ffff
8849 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
8850 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_RESET 0x0
8851 /* Extracts the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC field value from a register. */
8852 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8853 /* Produces a ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value suitable for setting the register. */
8854 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8855 
8856 #ifndef __ASSEMBLY__
8857 /*
8858  * WARNING: The C register and register group struct declarations are provided for
8859  * convenience and illustrative purposes. They should, however, be used with
8860  * caution as the C language standard provides no guarantees about the alignment or
8861  * atomicity of device memory accesses. The recommended practice for writing
8862  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8863  * alt_write_word() functions.
8864  *
8865  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR8CLK.
8866  */
8867 struct ALT_CLKMGR_PERPLL_CNTR8CLK_s
8868 {
8869  uint32_t cnt : 11; /* Counter */
8870  uint32_t : 5; /* *UNDEFINED* */
8871  uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR8CLK_SRC */
8872  uint32_t : 13; /* *UNDEFINED* */
8873 };
8874 
8875 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR8CLK. */
8876 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR8CLK_s ALT_CLKMGR_PERPLL_CNTR8CLK_t;
8877 #endif /* __ASSEMBLY__ */
8878 
8879 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK register. */
8880 #define ALT_CLKMGR_PERPLL_CNTR8CLK_RESET 0x00000000
8881 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR8CLK register from the beginning of the component. */
8882 #define ALT_CLKMGR_PERPLL_CNTR8CLK_OFST 0x40
8883 
8884 /*
8885  * Register : Peripheral PLL Control Register for Counter 9 Clock - cntr9clk
8886  *
8887  * Contains settings that control Couner 9 clock generated from the Peripheral PLL
8888  * VCO clock.
8889  *
8890  * Register Layout
8891  *
8892  * Bits | Access | Reset | Description
8893  * :--------|:-------|:------|:------------
8894  * [10:0] | RW | 0x0 | Counter
8895  * [31:11] | ??? | 0x0 | *UNDEFINED*
8896  *
8897  */
8898 /*
8899  * Field : Counter - cnt
8900  *
8901  * Divides the VCO frequency by the value+1 in this field.
8902  *
8903  * Field Access Macros:
8904  *
8905  */
8906 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
8907 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_LSB 0
8908 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
8909 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_MSB 10
8910 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
8911 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_WIDTH 11
8912 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value. */
8913 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
8914 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value. */
8915 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
8916 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
8917 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_RESET 0x0
8918 /* Extracts the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT field value from a register. */
8919 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8920 /* Produces a ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value suitable for setting the register. */
8921 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8922 
8923 #ifndef __ASSEMBLY__
8924 /*
8925  * WARNING: The C register and register group struct declarations are provided for
8926  * convenience and illustrative purposes. They should, however, be used with
8927  * caution as the C language standard provides no guarantees about the alignment or
8928  * atomicity of device memory accesses. The recommended practice for writing
8929  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8930  * alt_write_word() functions.
8931  *
8932  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR9CLK.
8933  */
8934 struct ALT_CLKMGR_PERPLL_CNTR9CLK_s
8935 {
8936  uint32_t cnt : 11; /* Counter */
8937  uint32_t : 21; /* *UNDEFINED* */
8938 };
8939 
8940 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR9CLK. */
8941 typedef volatile struct ALT_CLKMGR_PERPLL_CNTR9CLK_s ALT_CLKMGR_PERPLL_CNTR9CLK_t;
8942 #endif /* __ASSEMBLY__ */
8943 
8944 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR9CLK register. */
8945 #define ALT_CLKMGR_PERPLL_CNTR9CLK_RESET 0x00000000
8946 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR9CLK register from the beginning of the component. */
8947 #define ALT_CLKMGR_PERPLL_CNTR9CLK_OFST 0x44
8948 
8949 /*
8950  * Register : Peripheral PLL Output Counter Reset Register - outrst
8951  *
8952  * Contains settings to assert individual Outreset for all Peripheral PLL Counters.
8953  *
8954  * Register Layout
8955  *
8956  * Bits | Access | Reset | Description
8957  * :--------|:-------|:------|:---------------------
8958  * [15:0] | RW | 0x0 | Output Counter Reset
8959  * [31:16] | ??? | 0x0 | *UNDEFINED*
8960  *
8961  */
8962 /*
8963  * Field : Output Counter Reset - outreset
8964  *
8965  * Resets the individual PLL output counter.
8966  *
8967  * For software to change the PLL output counter without producing glitches on the
8968  * respective clock, SW must set the Output Counter Reset Register 'Output Counter
8969  * Reset' bit. Software then polls the respective Output Counter Reset Acknowledge
8970  * bit in the Output Counter Reset Ack Status Register. Software then writes the
8971  * appropriate counter register, and then clears the respective Output Counter
8972  * Reset bit.
8973  *
8974  * LSB 'outreset[0]' corresponds to PLL output clock C0, etc.
8975  *
8976  * If set to '1', reset output divider, no clock output from counter.
8977  *
8978  * If set to '0', counter is not reset.
8979  *
8980  * The reset value of this bit is applied on a cold reset; warm reset has no affect
8981  * on this bit.
8982  *
8983  * Field Access Macros:
8984  *
8985  */
8986 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field. */
8987 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_LSB 0
8988 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field. */
8989 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_MSB 15
8990 /* The width in bits of the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field. */
8991 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_WIDTH 16
8992 /* The mask used to set the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field value. */
8993 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_SET_MSK 0x0000ffff
8994 /* The mask used to clear the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field value. */
8995 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_CLR_MSK 0xffff0000
8996 /* The reset value of the ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field. */
8997 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_RESET 0x0
8998 /* Extracts the ALT_CLKMGR_PERPLL_OUTRST_OUTRST field value from a register. */
8999 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_GET(value) (((value) & 0x0000ffff) >> 0)
9000 /* Produces a ALT_CLKMGR_PERPLL_OUTRST_OUTRST register field value suitable for setting the register. */
9001 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_SET(value) (((value) << 0) & 0x0000ffff)
9002 
9003 #ifndef __ASSEMBLY__
9004 /*
9005  * WARNING: The C register and register group struct declarations are provided for
9006  * convenience and illustrative purposes. They should, however, be used with
9007  * caution as the C language standard provides no guarantees about the alignment or
9008  * atomicity of device memory accesses. The recommended practice for writing
9009  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9010  * alt_write_word() functions.
9011  *
9012  * The struct declaration for register ALT_CLKMGR_PERPLL_OUTRST.
9013  */
9014 struct ALT_CLKMGR_PERPLL_OUTRST_s
9015 {
9016  uint32_t outreset : 16; /* Output Counter Reset */
9017  uint32_t : 16; /* *UNDEFINED* */
9018 };
9019 
9020 /* The typedef declaration for register ALT_CLKMGR_PERPLL_OUTRST. */
9021 typedef volatile struct ALT_CLKMGR_PERPLL_OUTRST_s ALT_CLKMGR_PERPLL_OUTRST_t;
9022 #endif /* __ASSEMBLY__ */
9023 
9024 /* The reset value of the ALT_CLKMGR_PERPLL_OUTRST register. */
9025 #define ALT_CLKMGR_PERPLL_OUTRST_RESET 0x00000000
9026 /* The byte offset of the ALT_CLKMGR_PERPLL_OUTRST register from the beginning of the component. */
9027 #define ALT_CLKMGR_PERPLL_OUTRST_OFST 0x60
9028 
9029 /*
9030  * Register : Peripheral PLL Output Counter Reset Ack Status Register - outrststat
9031  *
9032  * Contains Output Clock Counter Reset acknowledge status.
9033  *
9034  * Register Layout
9035  *
9036  * Bits | Access | Reset | Description
9037  * :--------|:-------|:------|:---------------------------------
9038  * [15:0] | R | 0x0 | Output Counter Reset Acknowledge
9039  * [31:16] | ??? | 0x0 | *UNDEFINED*
9040  *
9041  */
9042 /*
9043  * Field : Output Counter Reset Acknowledge - outresetack
9044  *
9045  * These read only bits per PLL output indicate that the PLL has received the
9046  * Output Reset Counter request and has gracefully stopped the respective PLL
9047  * output clock.
9048  *
9049  * For software to change the PLL output counter without producing glitches on the
9050  * respective clock, SW must set the Output Counter Reset Register 'Output Counter
9051  * Reset' bit. Software then polls the respective Output Counter Reset Acknowledge
9052  * bit in the Output Counter Reset Ack Status Register. Software then writes the
9053  * appropriate counter register, and then clears the respective Output Counter
9054  * Reset bit.
9055  *
9056  * The reset value of this bit is applied on a cold reset; warm reset has no affect
9057  * on this bit.
9058  *
9059  * Field Enumeration Values:
9060  *
9061  * Enum | Value | Description
9062  * :-------------------------------------------------|:------|:-------------------------------------
9063  * ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE | 0x0 | Idle
9064  * ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD | 0x1 | Output Counter Acknowledge received.
9065  *
9066  * Field Access Macros:
9067  *
9068  */
9069 /*
9070  * Enumerated value for register field ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK
9071  *
9072  * Idle
9073  */
9074 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE 0x0
9075 /*
9076  * Enumerated value for register field ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK
9077  *
9078  * Output Counter Acknowledge received.
9079  */
9080 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD 0x1
9081 
9082 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field. */
9083 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_LSB 0
9084 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field. */
9085 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_MSB 15
9086 /* The width in bits of the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field. */
9087 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_WIDTH 16
9088 /* The mask used to set the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field value. */
9089 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_SET_MSK 0x0000ffff
9090 /* The mask used to clear the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field value. */
9091 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_CLR_MSK 0xffff0000
9092 /* The reset value of the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field. */
9093 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_RESET 0x0
9094 /* Extracts the ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK field value from a register. */
9095 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_GET(value) (((value) & 0x0000ffff) >> 0)
9096 /* Produces a ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK register field value suitable for setting the register. */
9097 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000ffff)
9098 
9099 #ifndef __ASSEMBLY__
9100 /*
9101  * WARNING: The C register and register group struct declarations are provided for
9102  * convenience and illustrative purposes. They should, however, be used with
9103  * caution as the C language standard provides no guarantees about the alignment or
9104  * atomicity of device memory accesses. The recommended practice for writing
9105  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9106  * alt_write_word() functions.
9107  *
9108  * The struct declaration for register ALT_CLKMGR_PERPLL_OUTRSTSTAT.
9109  */
9110 struct ALT_CLKMGR_PERPLL_OUTRSTSTAT_s
9111 {
9112  const uint32_t outresetack : 16; /* Output Counter Reset Acknowledge */
9113  uint32_t : 16; /* *UNDEFINED* */
9114 };
9115 
9116 /* The typedef declaration for register ALT_CLKMGR_PERPLL_OUTRSTSTAT. */
9117 typedef volatile struct ALT_CLKMGR_PERPLL_OUTRSTSTAT_s ALT_CLKMGR_PERPLL_OUTRSTSTAT_t;
9118 #endif /* __ASSEMBLY__ */
9119 
9120 /* The reset value of the ALT_CLKMGR_PERPLL_OUTRSTSTAT register. */
9121 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_RESET 0x00000000
9122 /* The byte offset of the ALT_CLKMGR_PERPLL_OUTRSTSTAT register from the beginning of the component. */
9123 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OFST 0x64
9124 
9125 /*
9126  * Register : Main Divide Register - emacctl
9127  *
9128  * Contains fields that control clock dividers for main clocks derived from the
9129  * Main PLL
9130  *
9131  * Register Layout
9132  *
9133  * Bits | Access | Reset | Description
9134  * :--------|:-------|:------|:-------------------
9135  * [25:0] | ??? | 0x0 | *UNDEFINED*
9136  * [26] | RW | 0x0 | EMAC0 clock select
9137  * [27] | RW | 0x0 | EMAC1 clock select
9138  * [28] | RW | 0x0 | EMAC2 clock select
9139  * [31:29] | ??? | 0x0 | *UNDEFINED*
9140  *
9141  */
9142 /*
9143  * Field : EMAC0 clock select - emac0sel
9144  *
9145  * Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk.
9146  *
9147  * Field Enumeration Values:
9148  *
9149  * Enum | Value | Description
9150  * :-------------------------------------------|:------|:------------
9151  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA | 0x0 | EMAC A
9152  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB | 0x1 | EMAC B
9153  *
9154  * Field Access Macros:
9155  *
9156  */
9157 /*
9158  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
9159  *
9160  * EMAC A
9161  */
9162 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0
9163 /*
9164  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
9165  *
9166  * EMAC B
9167  */
9168 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1
9169 
9170 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
9171 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
9172 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
9173 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26
9174 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
9175 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1
9176 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value. */
9177 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000
9178 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value. */
9179 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff
9180 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
9181 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0
9182 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL field value from a register. */
9183 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET(value) (((value) & 0x04000000) >> 26)
9184 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value suitable for setting the register. */
9185 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET(value) (((value) << 26) & 0x04000000)
9186 
9187 /*
9188  * Field : EMAC1 clock select - emac1sel
9189  *
9190  * Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk.
9191  *
9192  * Field Enumeration Values:
9193  *
9194  * Enum | Value | Description
9195  * :-------------------------------------------|:------|:------------
9196  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA | 0x0 | EMAC A
9197  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB | 0x1 | EMAC B
9198  *
9199  * Field Access Macros:
9200  *
9201  */
9202 /*
9203  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
9204  *
9205  * EMAC A
9206  */
9207 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0
9208 /*
9209  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
9210  *
9211  * EMAC B
9212  */
9213 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1
9214 
9215 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
9216 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
9217 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
9218 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27
9219 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
9220 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1
9221 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value. */
9222 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000
9223 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value. */
9224 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff
9225 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
9226 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0
9227 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL field value from a register. */
9228 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET(value) (((value) & 0x08000000) >> 27)
9229 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value suitable for setting the register. */
9230 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET(value) (((value) << 27) & 0x08000000)
9231 
9232 /*
9233  * Field : EMAC2 clock select - emac2sel
9234  *
9235  * Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk.
9236  *
9237  * Field Enumeration Values:
9238  *
9239  * Enum | Value | Description
9240  * :-------------------------------------------|:------|:------------
9241  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA | 0x0 | EMAC A
9242  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB | 0x1 | EMAC B
9243  *
9244  * Field Access Macros:
9245  *
9246  */
9247 /*
9248  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
9249  *
9250  * EMAC A
9251  */
9252 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0
9253 /*
9254  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
9255  *
9256  * EMAC B
9257  */
9258 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1
9259 
9260 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
9261 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
9262 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
9263 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28
9264 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
9265 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1
9266 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value. */
9267 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000
9268 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value. */
9269 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff
9270 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
9271 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0
9272 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL field value from a register. */
9273 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET(value) (((value) & 0x10000000) >> 28)
9274 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value suitable for setting the register. */
9275 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET(value) (((value) << 28) & 0x10000000)
9276 
9277 #ifndef __ASSEMBLY__
9278 /*
9279  * WARNING: The C register and register group struct declarations are provided for
9280  * convenience and illustrative purposes. They should, however, be used with
9281  * caution as the C language standard provides no guarantees about the alignment or
9282  * atomicity of device memory accesses. The recommended practice for writing
9283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9284  * alt_write_word() functions.
9285  *
9286  * The struct declaration for register ALT_CLKMGR_PERPLL_EMACCTL.
9287  */
9288 struct ALT_CLKMGR_PERPLL_EMACCTL_s
9289 {
9290  uint32_t : 26; /* *UNDEFINED* */
9291  uint32_t emac0sel : 1; /* EMAC0 clock select */
9292  uint32_t emac1sel : 1; /* EMAC1 clock select */
9293  uint32_t emac2sel : 1; /* EMAC2 clock select */
9294  uint32_t : 3; /* *UNDEFINED* */
9295 };
9296 
9297 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMACCTL. */
9298 typedef volatile struct ALT_CLKMGR_PERPLL_EMACCTL_s ALT_CLKMGR_PERPLL_EMACCTL_t;
9299 #endif /* __ASSEMBLY__ */
9300 
9301 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL register. */
9302 #define ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000
9303 /* The byte offset of the ALT_CLKMGR_PERPLL_EMACCTL register from the beginning of the component. */
9304 #define ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x68
9305 
9306 /*
9307  * Register : GPIO Divide Register - gpiodiv
9308  *
9309  * Contains a field that controls the clock divider for the GPIO De-bounce clock.
9310  *
9311  * Register Layout
9312  *
9313  * Bits | Access | Reset | Description
9314  * :--------|:-------|:------|:-----------------------------
9315  * [15:0] | RW | 0x1 | GPIO De-bounce Clock Divider
9316  * [31:16] | ??? | 0x0 | *UNDEFINED*
9317  *
9318  */
9319 /*
9320  * Field : GPIO De-bounce Clock Divider - gpiodbclk
9321  *
9322  * The gpio_db_clk is divided down from the periph_base_clk by the value plus one
9323  * specified in this field. The value 0 (divide by 1) is illegal. A value of 1
9324  * indicates divide by 2, 2 divide by 3, etc.
9325  *
9326  * Field Access Macros:
9327  *
9328  */
9329 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
9330 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
9331 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
9332 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 15
9333 /* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
9334 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 16
9335 /* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
9336 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x0000ffff
9337 /* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
9338 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xffff0000
9339 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
9340 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
9341 /* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */
9342 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x0000ffff) >> 0)
9343 /* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */
9344 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x0000ffff)
9345 
9346 #ifndef __ASSEMBLY__
9347 /*
9348  * WARNING: The C register and register group struct declarations are provided for
9349  * convenience and illustrative purposes. They should, however, be used with
9350  * caution as the C language standard provides no guarantees about the alignment or
9351  * atomicity of device memory accesses. The recommended practice for writing
9352  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9353  * alt_write_word() functions.
9354  *
9355  * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.
9356  */
9357 struct ALT_CLKMGR_PERPLL_GPIODIV_s
9358 {
9359  uint32_t gpiodbclk : 16; /* GPIO De-bounce Clock Divider */
9360  uint32_t : 16; /* *UNDEFINED* */
9361 };
9362 
9363 /* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */
9364 typedef volatile struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
9365 #endif /* __ASSEMBLY__ */
9366 
9367 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV register. */
9368 #define ALT_CLKMGR_PERPLL_GPIODIV_RESET 0x00000001
9369 /* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */
9370 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x6c
9371 
9372 #ifndef __ASSEMBLY__
9373 /*
9374  * WARNING: The C register and register group struct declarations are provided for
9375  * convenience and illustrative purposes. They should, however, be used with
9376  * caution as the C language standard provides no guarantees about the alignment or
9377  * atomicity of device memory accesses. The recommended practice for writing
9378  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9379  * alt_write_word() functions.
9380  *
9381  * The struct declaration for register group ALT_CLKMGR_PERPLL.
9382  */
9383 struct ALT_CLKMGR_PERPLL_s
9384 {
9385  ALT_CLKMGR_PERPLL_VCO0_t vco0; /* ALT_CLKMGR_PERPLL_VCO0 */
9386  ALT_CLKMGR_PERPLL_VCO1_t vco1; /* ALT_CLKMGR_PERPLL_VCO1 */
9387  ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */
9388  ALT_CLKMGR_PERPLL_ENS_t ens; /* ALT_CLKMGR_PERPLL_ENS */
9389  ALT_CLKMGR_PERPLL_ENR_t enr; /* ALT_CLKMGR_PERPLL_ENR */
9390  ALT_CLKMGR_PERPLL_BYPASS_t bypass; /* ALT_CLKMGR_PERPLL_BYPASS */
9391  ALT_CLKMGR_PERPLL_BYPASSS_t bypasss; /* ALT_CLKMGR_PERPLL_BYPASSS */
9392  ALT_CLKMGR_PERPLL_BYPASSR_t bypassr; /* ALT_CLKMGR_PERPLL_BYPASSR */
9393  volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
9394  ALT_CLKMGR_PERPLL_CNTR2CLK_t cntr2clk; /* ALT_CLKMGR_PERPLL_CNTR2CLK */
9395  ALT_CLKMGR_PERPLL_CNTR3CLK_t cntr3clk; /* ALT_CLKMGR_PERPLL_CNTR3CLK */
9396  ALT_CLKMGR_PERPLL_CNTR4CLK_t cntr4clk; /* ALT_CLKMGR_PERPLL_CNTR4CLK */
9397  ALT_CLKMGR_PERPLL_CNTR5CLK_t cntr5clk; /* ALT_CLKMGR_PERPLL_CNTR5CLK */
9398  ALT_CLKMGR_PERPLL_CNTR6CLK_t cntr6clk; /* ALT_CLKMGR_PERPLL_CNTR6CLK */
9399  ALT_CLKMGR_PERPLL_CNTR7CLK_t cntr7clk; /* ALT_CLKMGR_PERPLL_CNTR7CLK */
9400  ALT_CLKMGR_PERPLL_CNTR8CLK_t cntr8clk; /* ALT_CLKMGR_PERPLL_CNTR8CLK */
9401  ALT_CLKMGR_PERPLL_CNTR9CLK_t cntr9clk; /* ALT_CLKMGR_PERPLL_CNTR9CLK */
9402  volatile uint32_t _pad_0x48_0x5f[6]; /* *UNDEFINED* */
9403  ALT_CLKMGR_PERPLL_OUTRST_t outrst; /* ALT_CLKMGR_PERPLL_OUTRST */
9404  ALT_CLKMGR_PERPLL_OUTRSTSTAT_t outrststat; /* ALT_CLKMGR_PERPLL_OUTRSTSTAT */
9405  ALT_CLKMGR_PERPLL_EMACCTL_t emacctl; /* ALT_CLKMGR_PERPLL_EMACCTL */
9406  ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
9407  volatile uint32_t _pad_0x70_0x80[4]; /* *UNDEFINED* */
9408 };
9409 
9410 /* The typedef declaration for register group ALT_CLKMGR_PERPLL. */
9411 typedef volatile struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
9412 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
9413 struct ALT_CLKMGR_PERPLL_raw_s
9414 {
9415  volatile uint32_t vco0; /* ALT_CLKMGR_PERPLL_VCO0 */
9416  volatile uint32_t vco1; /* ALT_CLKMGR_PERPLL_VCO1 */
9417  volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */
9418  volatile uint32_t ens; /* ALT_CLKMGR_PERPLL_ENS */
9419  volatile uint32_t enr; /* ALT_CLKMGR_PERPLL_ENR */
9420  volatile uint32_t bypass; /* ALT_CLKMGR_PERPLL_BYPASS */
9421  volatile uint32_t bypasss; /* ALT_CLKMGR_PERPLL_BYPASSS */
9422  volatile uint32_t bypassr; /* ALT_CLKMGR_PERPLL_BYPASSR */
9423  uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
9424  volatile uint32_t cntr2clk; /* ALT_CLKMGR_PERPLL_CNTR2CLK */
9425  volatile uint32_t cntr3clk; /* ALT_CLKMGR_PERPLL_CNTR3CLK */
9426  volatile uint32_t cntr4clk; /* ALT_CLKMGR_PERPLL_CNTR4CLK */
9427  volatile uint32_t cntr5clk; /* ALT_CLKMGR_PERPLL_CNTR5CLK */
9428  volatile uint32_t cntr6clk; /* ALT_CLKMGR_PERPLL_CNTR6CLK */
9429  volatile uint32_t cntr7clk; /* ALT_CLKMGR_PERPLL_CNTR7CLK */
9430  volatile uint32_t cntr8clk; /* ALT_CLKMGR_PERPLL_CNTR8CLK */
9431  volatile uint32_t cntr9clk; /* ALT_CLKMGR_PERPLL_CNTR9CLK */
9432  uint32_t _pad_0x48_0x5f[6]; /* *UNDEFINED* */
9433  volatile uint32_t outrst; /* ALT_CLKMGR_PERPLL_OUTRST */
9434  volatile uint32_t outrststat; /* ALT_CLKMGR_PERPLL_OUTRSTSTAT */
9435  volatile uint32_t emacctl; /* ALT_CLKMGR_PERPLL_EMACCTL */
9436  volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
9437  uint32_t _pad_0x70_0x80[4]; /* *UNDEFINED* */
9438 };
9439 
9440 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
9441 typedef volatile struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;
9442 #endif /* __ASSEMBLY__ */
9443 
9444 
9445 /*
9446  * Component : ALT_CLKMGR_ALTERA
9447  *
9448  */
9449 /*
9450  * Register : NOC Internal PLL Counters - nocclk
9451  *
9452  * Contains settings that control clock main_clk generated from the Main PLL VCO
9453  * clock.
9454  *
9455  * Register Layout
9456  *
9457  * Bits | Access | Reset | Description
9458  * :--------|:-------|:------|:--------------------------------
9459  * [10:0] | RW | 0x3 | Main PLL Internal Counter
9460  * [15:11] | ??? | 0x0 | *UNDEFINED*
9461  * [26:16] | RW | 0x3 | Peripheral PLL Internal Counter
9462  * [31:27] | ??? | 0x0 | *UNDEFINED*
9463  *
9464  */
9465 /*
9466  * Field : Main PLL Internal Counter - maincnt
9467  *
9468  * Divides the VCO frequency by the value+1 in this field. Divides the VCO
9469  * frequency by the value+1 in this field. This field loads the internal counter
9470  * in the NOC PLL for the NOC Clock Group.
9471  *
9472  * Field Access Macros:
9473  *
9474  */
9475 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_NOCCLK_MAINCNT register field. */
9476 #define ALT_CLKMGR_NOCCLK_MAINCNT_LSB 0
9477 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_NOCCLK_MAINCNT register field. */
9478 #define ALT_CLKMGR_NOCCLK_MAINCNT_MSB 10
9479 /* The width in bits of the ALT_CLKMGR_NOCCLK_MAINCNT register field. */
9480 #define ALT_CLKMGR_NOCCLK_MAINCNT_WIDTH 11
9481 /* The mask used to set the ALT_CLKMGR_NOCCLK_MAINCNT register field value. */
9482 #define ALT_CLKMGR_NOCCLK_MAINCNT_SET_MSK 0x000007ff
9483 /* The mask used to clear the ALT_CLKMGR_NOCCLK_MAINCNT register field value. */
9484 #define ALT_CLKMGR_NOCCLK_MAINCNT_CLR_MSK 0xfffff800
9485 /* The reset value of the ALT_CLKMGR_NOCCLK_MAINCNT register field. */
9486 #define ALT_CLKMGR_NOCCLK_MAINCNT_RESET 0x3
9487 /* Extracts the ALT_CLKMGR_NOCCLK_MAINCNT field value from a register. */
9488 #define ALT_CLKMGR_NOCCLK_MAINCNT_GET(value) (((value) & 0x000007ff) >> 0)
9489 /* Produces a ALT_CLKMGR_NOCCLK_MAINCNT register field value suitable for setting the register. */
9490 #define ALT_CLKMGR_NOCCLK_MAINCNT_SET(value) (((value) << 0) & 0x000007ff)
9491 
9492 /*
9493  * Field : Peripheral PLL Internal Counter - pericnt
9494  *
9495  * Divides the VCO frequency by the value+1 in this field. Divides the VCO
9496  * frequency by the value+1 in this field. This field loads the internal counter
9497  * in the NOC PLL for the NOC Clock Group.
9498  *
9499  * Field Access Macros:
9500  *
9501  */
9502 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_NOCCLK_PERICNT register field. */
9503 #define ALT_CLKMGR_NOCCLK_PERICNT_LSB 16
9504 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_NOCCLK_PERICNT register field. */
9505 #define ALT_CLKMGR_NOCCLK_PERICNT_MSB 26
9506 /* The width in bits of the ALT_CLKMGR_NOCCLK_PERICNT register field. */
9507 #define ALT_CLKMGR_NOCCLK_PERICNT_WIDTH 11
9508 /* The mask used to set the ALT_CLKMGR_NOCCLK_PERICNT register field value. */
9509 #define ALT_CLKMGR_NOCCLK_PERICNT_SET_MSK 0x07ff0000
9510 /* The mask used to clear the ALT_CLKMGR_NOCCLK_PERICNT register field value. */
9511 #define ALT_CLKMGR_NOCCLK_PERICNT_CLR_MSK 0xf800ffff
9512 /* The reset value of the ALT_CLKMGR_NOCCLK_PERICNT register field. */
9513 #define ALT_CLKMGR_NOCCLK_PERICNT_RESET 0x3
9514 /* Extracts the ALT_CLKMGR_NOCCLK_PERICNT field value from a register. */
9515 #define ALT_CLKMGR_NOCCLK_PERICNT_GET(value) (((value) & 0x07ff0000) >> 16)
9516 /* Produces a ALT_CLKMGR_NOCCLK_PERICNT register field value suitable for setting the register. */
9517 #define ALT_CLKMGR_NOCCLK_PERICNT_SET(value) (((value) << 16) & 0x07ff0000)
9518 
9519 #ifndef __ASSEMBLY__
9520 /*
9521  * WARNING: The C register and register group struct declarations are provided for
9522  * convenience and illustrative purposes. They should, however, be used with
9523  * caution as the C language standard provides no guarantees about the alignment or
9524  * atomicity of device memory accesses. The recommended practice for writing
9525  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9526  * alt_write_word() functions.
9527  *
9528  * The struct declaration for register ALT_CLKMGR_NOCCLK.
9529  */
9530 struct ALT_CLKMGR_NOCCLK_s
9531 {
9532  uint32_t maincnt : 11; /* Main PLL Internal Counter */
9533  uint32_t : 5; /* *UNDEFINED* */
9534  uint32_t pericnt : 11; /* Peripheral PLL Internal Counter */
9535  uint32_t : 5; /* *UNDEFINED* */
9536 };
9537 
9538 /* The typedef declaration for register ALT_CLKMGR_NOCCLK. */
9539 typedef volatile struct ALT_CLKMGR_NOCCLK_s ALT_CLKMGR_NOCCLK_t;
9540 #endif /* __ASSEMBLY__ */
9541 
9542 /* The reset value of the ALT_CLKMGR_NOCCLK register. */
9543 #define ALT_CLKMGR_NOCCLK_RESET 0x00030003
9544 /* The byte offset of the ALT_CLKMGR_NOCCLK register from the beginning of the component. */
9545 #define ALT_CLKMGR_NOCCLK_OFST 0x4
9546 
9547 #ifndef __ASSEMBLY__
9548 /*
9549  * WARNING: The C register and register group struct declarations are provided for
9550  * convenience and illustrative purposes. They should, however, be used with
9551  * caution as the C language standard provides no guarantees about the alignment or
9552  * atomicity of device memory accesses. The recommended practice for writing
9553  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9554  * alt_write_word() functions.
9555  *
9556  * The struct declaration for register group ALT_CLKMGR_ALTERA.
9557  */
9558 struct ALT_CLKMGR_ALTERA_s
9559 {
9560  volatile uint32_t _pad_0x0_0x3; /* *UNDEFINED* */
9561  ALT_CLKMGR_NOCCLK_t nocclk; /* ALT_CLKMGR_NOCCLK */
9562  volatile uint32_t _pad_0x8_0x40[14]; /* *UNDEFINED* */
9563 };
9564 
9565 /* The typedef declaration for register group ALT_CLKMGR_ALTERA. */
9566 typedef volatile struct ALT_CLKMGR_ALTERA_s ALT_CLKMGR_ALTERA_t;
9567 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_ALTERA. */
9568 struct ALT_CLKMGR_ALTERA_raw_s
9569 {
9570  uint32_t _pad_0x0_0x3; /* *UNDEFINED* */
9571  volatile uint32_t nocclk; /* ALT_CLKMGR_NOCCLK */
9572  uint32_t _pad_0x8_0x40[14]; /* *UNDEFINED* */
9573 };
9574 
9575 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_ALTERA. */
9576 typedef volatile struct ALT_CLKMGR_ALTERA_raw_s ALT_CLKMGR_ALTERA_raw_t;
9577 #endif /* __ASSEMBLY__ */
9578 
9579 
9580 #ifdef __cplusplus
9581 }
9582 #endif /* __cplusplus */
9583 #endif /* __ALT_SOCAL_CLKMGR_H__ */
9584