Hardware Libraries  20.1
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alt_spis.h
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32 
33 /* Altera - ALT_SPIS */
34 
35 #ifndef __ALT_SOCAL_SPIS_H__
36 #define __ALT_SOCAL_SPIS_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_SPIS
50  *
51  */
52 /*
53  * Register : ctrlr0
54  *
55  * Control Register 0:
56  *
57  * This register controls the serial data transfer. It is impossible to
58  *
59  * write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
60  *
61  * is enabled and disabled by writing to the SSIENR register.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :--------|:-------|:------|:----------------------
67  * [3:0] | RW | 0x7 | ALT_SPIS_CTLR0_DFS
68  * [5:4] | RW | 0x0 | ALT_SPIS_CTLR0_FRF
69  * [6] | RW | 0x0 | ALT_SPIS_CTLR0_SCPH
70  * [7] | RW | 0x0 | ALT_SPIS_CTLR0_SCPOL
71  * [9:8] | RW | 0x0 | ALT_SPIS_CTLR0_TMOD
72  * [10] | RW | 0x0 | ALT_SPIS_CTLR0_SLV_OE
73  * [11] | RW | 0x0 | ALT_SPIS_CTLR0_SRL
74  * [15:12] | RW | 0x0 | ALT_SPIS_CTLR0_CFS
75  * [31:16] | ??? | 0x0 | *UNDEFINED*
76  *
77  */
78 /*
79  * Field : dfs
80  *
81  * Data Frame Size.
82  *
83  * Selects the data frame length. When the data frame size is programmed
84  *
85  * to be less than 16 bits, the receive data are automatically
86  *
87  * right-justified by the receive logic, with the upper bits of the receive
88  *
89  * FIFO zero-padded. You must right-justify transmit data before writing
90  *
91  * into the transmit FIFO. The transmit logic ignores the upper unused
92  *
93  * bits when transmitting the data
94  *
95  * Field Enumeration Values:
96  *
97  * Enum | Value | Description
98  * :--------------------------------|:------|:----------------------------
99  * ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer
100  * ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer
101  * ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer
102  * ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer
103  * ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer
104  * ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer
105  * ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer
106  * ALT_SPIS_CTLR0_DFS_E_WIDTH11BIT | 0xa | 11-bit serial data transfer
107  * ALT_SPIS_CTLR0_DFS_E_WIDTH12BIT | 0xb | 12-bit serial data transfer
108  * ALT_SPIS_CTLR0_DFS_E_WIDTH13BIT | 0xc | 13-bit serial data transfer
109  * ALT_SPIS_CTLR0_DFS_E_WIDTH14BIT | 0xd | 14-bit serial data transfer
110  * ALT_SPIS_CTLR0_DFS_E_WIDTH15BIT | 0xe | 15-bit serial data transfer
111  * ALT_SPIS_CTLR0_DFS_E_WIDTH16BIT | 0xf | 16-bit serial data transfer
112  *
113  * Field Access Macros:
114  *
115  */
116 /*
117  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
118  *
119  * 4-bit serial data transfer
120  */
121 #define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
122 /*
123  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
124  *
125  * 5-bit serial data transfer
126  */
127 #define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
128 /*
129  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
130  *
131  * 6-bit serial data transfer
132  */
133 #define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
134 /*
135  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
136  *
137  * 7-bit serial data transfer
138  */
139 #define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
140 /*
141  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
142  *
143  * 8-bit serial data transfer
144  */
145 #define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
146 /*
147  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
148  *
149  * 9-bit serial data transfer
150  */
151 #define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
152 /*
153  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
154  *
155  * 10-bit serial data transfer
156  */
157 #define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
158 /*
159  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
160  *
161  * 11-bit serial data transfer
162  */
163 #define ALT_SPIS_CTLR0_DFS_E_WIDTH11BIT 0xa
164 /*
165  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
166  *
167  * 12-bit serial data transfer
168  */
169 #define ALT_SPIS_CTLR0_DFS_E_WIDTH12BIT 0xb
170 /*
171  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
172  *
173  * 13-bit serial data transfer
174  */
175 #define ALT_SPIS_CTLR0_DFS_E_WIDTH13BIT 0xc
176 /*
177  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
178  *
179  * 14-bit serial data transfer
180  */
181 #define ALT_SPIS_CTLR0_DFS_E_WIDTH14BIT 0xd
182 /*
183  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
184  *
185  * 15-bit serial data transfer
186  */
187 #define ALT_SPIS_CTLR0_DFS_E_WIDTH15BIT 0xe
188 /*
189  * Enumerated value for register field ALT_SPIS_CTLR0_DFS
190  *
191  * 16-bit serial data transfer
192  */
193 #define ALT_SPIS_CTLR0_DFS_E_WIDTH16BIT 0xf
194 
195 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_DFS register field. */
196 #define ALT_SPIS_CTLR0_DFS_LSB 0
197 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_DFS register field. */
198 #define ALT_SPIS_CTLR0_DFS_MSB 3
199 /* The width in bits of the ALT_SPIS_CTLR0_DFS register field. */
200 #define ALT_SPIS_CTLR0_DFS_WIDTH 4
201 /* The mask used to set the ALT_SPIS_CTLR0_DFS register field value. */
202 #define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
203 /* The mask used to clear the ALT_SPIS_CTLR0_DFS register field value. */
204 #define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
205 /* The reset value of the ALT_SPIS_CTLR0_DFS register field. */
206 #define ALT_SPIS_CTLR0_DFS_RESET 0x7
207 /* Extracts the ALT_SPIS_CTLR0_DFS field value from a register. */
208 #define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
209 /* Produces a ALT_SPIS_CTLR0_DFS register field value suitable for setting the register. */
210 #define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
211 
212 /*
213  * Field : frf
214  *
215  * Frame Format.
216  *
217  * Selects which serial protocol transfers the data.
218  *
219  * 00 - Motorola SPI
220  *
221  * 01 - Texas Instruments SSP
222  *
223  * 10 - National Semiconductors Microwire
224  *
225  * 11 - Reserved
226  *
227  * Field Enumeration Values:
228  *
229  * Enum | Value | Description
230  * :----------------------------|:------|:------------------------
231  * ALT_SPIS_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI
232  * ALT_SPIS_CTLR0_FRF_E_TISSP | 0x1 | Texas instruments SSP
233  * ALT_SPIS_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire
234  *
235  * Field Access Macros:
236  *
237  */
238 /*
239  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
240  *
241  * Motorola SPI
242  */
243 #define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
244 /*
245  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
246  *
247  * Texas instruments SSP
248  */
249 #define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
250 /*
251  * Enumerated value for register field ALT_SPIS_CTLR0_FRF
252  *
253  * National Semi Microwire
254  */
255 #define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
256 
257 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_FRF register field. */
258 #define ALT_SPIS_CTLR0_FRF_LSB 4
259 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_FRF register field. */
260 #define ALT_SPIS_CTLR0_FRF_MSB 5
261 /* The width in bits of the ALT_SPIS_CTLR0_FRF register field. */
262 #define ALT_SPIS_CTLR0_FRF_WIDTH 2
263 /* The mask used to set the ALT_SPIS_CTLR0_FRF register field value. */
264 #define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
265 /* The mask used to clear the ALT_SPIS_CTLR0_FRF register field value. */
266 #define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
267 /* The reset value of the ALT_SPIS_CTLR0_FRF register field. */
268 #define ALT_SPIS_CTLR0_FRF_RESET 0x0
269 /* Extracts the ALT_SPIS_CTLR0_FRF field value from a register. */
270 #define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
271 /* Produces a ALT_SPIS_CTLR0_FRF register field value suitable for setting the register. */
272 #define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
273 
274 /*
275  * Field : scph
276  *
277  * Serial Clock Phase.
278  *
279  * Valid when the frame format (FRF) is set to Motorola SPI. The serial
280  *
281  * clock phase selects the relationship of the serial clock with the slave
282  *
283  * select signal. When SCPH = 0, data are captured on the first edge of
284  *
285  * the serial clock. When SCPH = 1, the serial clock starts toggling one
286  *
287  * cycle after the slave select line is activated, and data are captured
288  *
289  * on the second edge of the serial clock.
290  *
291  * 0: Serial clock toggles in middle of first data bit
292  *
293  * 1: Serial clock toggles at start of first data bit
294  *
295  * Field Enumeration Values:
296  *
297  * Enum | Value | Description
298  * :--------------------------------|:------|:---------------------------------------
299  * ALT_SPIS_CTLR0_SCPH_E_INACTLOW | 0x0 | Inactive state of serial clock is low
300  * ALT_SPIS_CTLR0_SCPH_E_INACTHIGH | 0x1 | Inactive state of serial clock is high
301  *
302  * Field Access Macros:
303  *
304  */
305 /*
306  * Enumerated value for register field ALT_SPIS_CTLR0_SCPH
307  *
308  * Inactive state of serial clock is low
309  */
310 #define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
311 /*
312  * Enumerated value for register field ALT_SPIS_CTLR0_SCPH
313  *
314  * Inactive state of serial clock is high
315  */
316 #define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
317 
318 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPH register field. */
319 #define ALT_SPIS_CTLR0_SCPH_LSB 6
320 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPH register field. */
321 #define ALT_SPIS_CTLR0_SCPH_MSB 6
322 /* The width in bits of the ALT_SPIS_CTLR0_SCPH register field. */
323 #define ALT_SPIS_CTLR0_SCPH_WIDTH 1
324 /* The mask used to set the ALT_SPIS_CTLR0_SCPH register field value. */
325 #define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
326 /* The mask used to clear the ALT_SPIS_CTLR0_SCPH register field value. */
327 #define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
328 /* The reset value of the ALT_SPIS_CTLR0_SCPH register field. */
329 #define ALT_SPIS_CTLR0_SCPH_RESET 0x0
330 /* Extracts the ALT_SPIS_CTLR0_SCPH field value from a register. */
331 #define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
332 /* Produces a ALT_SPIS_CTLR0_SCPH register field value suitable for setting the register. */
333 #define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
334 
335 /*
336  * Field : scpol
337  *
338  * Serial Clock Polarity.
339  *
340  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select
341  *
342  * the polarity of the inactive serial clock, which is held inactive when
343  *
344  * the DW_apb_ssi master is not actively transferring data on the serial bus.
345  *
346  * 0 - Inactive state of serial clock is low
347  *
348  * 1 - Inactive state of serial clock is high
349  *
350  * Field Enumeration Values:
351  *
352  * Enum | Value | Description
353  * :--------------------------------|:------|:-------------------------------------------------
354  * ALT_SPIS_CTLR0_SCPOL_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit
355  * ALT_SPIS_CTLR0_SCPOL_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit
356  *
357  * Field Access Macros:
358  *
359  */
360 /*
361  * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL
362  *
363  * Serial clock toggles in middle of first data bit
364  */
365 #define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
366 /*
367  * Enumerated value for register field ALT_SPIS_CTLR0_SCPOL
368  *
369  * Serial clock toggles at start of first data bit
370  */
371 #define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
372 
373 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */
374 #define ALT_SPIS_CTLR0_SCPOL_LSB 7
375 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPOL register field. */
376 #define ALT_SPIS_CTLR0_SCPOL_MSB 7
377 /* The width in bits of the ALT_SPIS_CTLR0_SCPOL register field. */
378 #define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
379 /* The mask used to set the ALT_SPIS_CTLR0_SCPOL register field value. */
380 #define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
381 /* The mask used to clear the ALT_SPIS_CTLR0_SCPOL register field value. */
382 #define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
383 /* The reset value of the ALT_SPIS_CTLR0_SCPOL register field. */
384 #define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
385 /* Extracts the ALT_SPIS_CTLR0_SCPOL field value from a register. */
386 #define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
387 /* Produces a ALT_SPIS_CTLR0_SCPOL register field value suitable for setting the register. */
388 #define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
389 
390 /*
391  * Field : tmod
392  *
393  * Transfer Mode.
394  *
395  * Selects the mode of transfer for serial communication. This field does
396  *
397  * not affect the transfer duplicity. Only indicates whether the receive or
398  *
399  * transmit data are valid. In transmit-only mode, data received from the
400  *
401  * external device is not valid and is not stored in the receive FIFO memory;
402  *
403  * it is overwritten on the next transfer. In receive-only mode, transmitted
404  *
405  * data are not valid. After the first write to the transmit FIFO, the same
406  *
407  * word is retransmitted for the duration of the transfer. In
408  *
409  * transmit-and-receive mode, both transmit and receive data are valid.
410  *
411  * The transfer continues until the transmit FIFO is empty. Data received
412  *
413  * from the external device are stored into the receive FIFO memory, where
414  *
415  * it can be accessed by the host processor.
416  *
417  * 00 - Transmit & Receive
418  *
419  * 01 - Transmit Only
420  *
421  * 10 - Receive Only
422  *
423  * 11 - Reserved
424  *
425  * Field Enumeration Values:
426  *
427  * Enum | Value | Description
428  * :-----------------------------|:------|:-----------------------
429  * ALT_SPIS_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive
430  * ALT_SPIS_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only
431  * ALT_SPIS_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only
432  *
433  * Field Access Macros:
434  *
435  */
436 /*
437  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
438  *
439  * Transmit & and Receive
440  */
441 #define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
442 /*
443  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
444  *
445  * Transmit Only
446  */
447 #define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
448 /*
449  * Enumerated value for register field ALT_SPIS_CTLR0_TMOD
450  *
451  * Receive Only
452  */
453 #define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
454 
455 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_TMOD register field. */
456 #define ALT_SPIS_CTLR0_TMOD_LSB 8
457 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_TMOD register field. */
458 #define ALT_SPIS_CTLR0_TMOD_MSB 9
459 /* The width in bits of the ALT_SPIS_CTLR0_TMOD register field. */
460 #define ALT_SPIS_CTLR0_TMOD_WIDTH 2
461 /* The mask used to set the ALT_SPIS_CTLR0_TMOD register field value. */
462 #define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
463 /* The mask used to clear the ALT_SPIS_CTLR0_TMOD register field value. */
464 #define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
465 /* The reset value of the ALT_SPIS_CTLR0_TMOD register field. */
466 #define ALT_SPIS_CTLR0_TMOD_RESET 0x0
467 /* Extracts the ALT_SPIS_CTLR0_TMOD field value from a register. */
468 #define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
469 /* Produces a ALT_SPIS_CTLR0_TMOD register field value suitable for setting the register. */
470 #define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
471 
472 /*
473  * Field : slv_oe
474  *
475  * Slave Output Enable.
476  *
477  * Relevant only when the DW_apb_ssi is configured as a serial-slave
478  *
479  * device. When configured as a serial master, this bit field has no
480  *
481  * functionality. This bit enables or disables the setting of the
482  *
483  * ssi_oe_n output from the DW_apb_ssi serial slave. When SLV_OE = 1,
484  *
485  * the ssi_oe_n output can never be active. When the ssi_oe_n output
486  *
487  * controls the tri-state buffer on the txd output from the slave, a
488  *
489  * high impedance state is always present on the slave txd output when
490  *
491  * SLV_OE = 1. This is useful when the master transmits in broadcast
492  *
493  * mode (master transmits data to all slave devices). Only one slave
494  *
495  * may respond with data on the master rxd line. This bit is
496  *
497  * enabled after reset and must be disabled by software (when broadcast
498  *
499  * mode is used), if you do not want this device to respond with data.
500  *
501  * 0 - Slave txd is enabled
502  *
503  * 1 - Slave txd is disabled
504  *
505  * Field Enumeration Values:
506  *
507  * Enum | Value | Description
508  * :-----------------------------|:------|:----------------------
509  * ALT_SPIS_CTLR0_SLV_OE_E_END | 0x0 | Slave txd is enabled
510  * ALT_SPIS_CTLR0_SLV_OE_E_DISD | 0x1 | Slave txd is disabled
511  *
512  * Field Access Macros:
513  *
514  */
515 /*
516  * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE
517  *
518  * Slave txd is enabled
519  */
520 #define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
521 /*
522  * Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE
523  *
524  * Slave txd is disabled
525  */
526 #define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
527 
528 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */
529 #define ALT_SPIS_CTLR0_SLV_OE_LSB 10
530 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SLV_OE register field. */
531 #define ALT_SPIS_CTLR0_SLV_OE_MSB 10
532 /* The width in bits of the ALT_SPIS_CTLR0_SLV_OE register field. */
533 #define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
534 /* The mask used to set the ALT_SPIS_CTLR0_SLV_OE register field value. */
535 #define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
536 /* The mask used to clear the ALT_SPIS_CTLR0_SLV_OE register field value. */
537 #define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
538 /* The reset value of the ALT_SPIS_CTLR0_SLV_OE register field. */
539 #define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
540 /* Extracts the ALT_SPIS_CTLR0_SLV_OE field value from a register. */
541 #define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
542 /* Produces a ALT_SPIS_CTLR0_SLV_OE register field value suitable for setting the register. */
543 #define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
544 
545 /*
546  * Field : srl
547  *
548  * Shift Register Loop. Used for testing purposes only. When internally
549  *
550  * active, connects the transmit shift register output to the receive
551  *
552  * shift register input.
553  *
554  * 0 - Normal Mode Operation
555  *
556  * 1 - Test Mode Operation
557  *
558  * Field Enumeration Values:
559  *
560  * Enum | Value | Description
561  * :-----------------------------|:------|:----------------------
562  * ALT_SPIS_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation
563  * ALT_SPIS_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation
564  *
565  * Field Access Macros:
566  *
567  */
568 /*
569  * Enumerated value for register field ALT_SPIS_CTLR0_SRL
570  *
571  * Normal Mode Operation
572  */
573 #define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
574 /*
575  * Enumerated value for register field ALT_SPIS_CTLR0_SRL
576  *
577  * Test Mode Operation
578  */
579 #define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
580 
581 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SRL register field. */
582 #define ALT_SPIS_CTLR0_SRL_LSB 11
583 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SRL register field. */
584 #define ALT_SPIS_CTLR0_SRL_MSB 11
585 /* The width in bits of the ALT_SPIS_CTLR0_SRL register field. */
586 #define ALT_SPIS_CTLR0_SRL_WIDTH 1
587 /* The mask used to set the ALT_SPIS_CTLR0_SRL register field value. */
588 #define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
589 /* The mask used to clear the ALT_SPIS_CTLR0_SRL register field value. */
590 #define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
591 /* The reset value of the ALT_SPIS_CTLR0_SRL register field. */
592 #define ALT_SPIS_CTLR0_SRL_RESET 0x0
593 /* Extracts the ALT_SPIS_CTLR0_SRL field value from a register. */
594 #define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
595 /* Produces a ALT_SPIS_CTLR0_SRL register field value suitable for setting the register. */
596 #define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
597 
598 /*
599  * Field : cfs
600  *
601  * Control Frame Size. Selects the length of the control word for the
602  *
603  * Microwire frame format
604  *
605  * Field Enumeration Values:
606  *
607  * Enum | Value | Description
608  * :-------------------------------|:------|:--------------------
609  * ALT_SPIS_CTLR0_CFS_E_SIZE1BIT | 0x0 | 1-bit control word
610  * ALT_SPIS_CTLR0_CFS_E_SIZE2BIT | 0x1 | 2-bit control word
611  * ALT_SPIS_CTLR0_CFS_E_SIZE3BIT | 0x2 | 3-bit control word
612  * ALT_SPIS_CTLR0_CFS_E_SIZE4BIT | 0x3 | 4-bit control word
613  * ALT_SPIS_CTLR0_CFS_E_SIZE5BIT | 0x4 | 5-bit control word
614  * ALT_SPIS_CTLR0_CFS_E_SIZE6BIT | 0x5 | 6-bit control word
615  * ALT_SPIS_CTLR0_CFS_E_SIZE7BIT | 0x6 | 7-bit control word
616  * ALT_SPIS_CTLR0_CFS_E_SIZE8BIT | 0x7 | 8-bit control word
617  * ALT_SPIS_CTLR0_CFS_E_SIZE9BIT | 0x8 | 9-bit control word
618  * ALT_SPIS_CTLR0_CFS_E_SIZE10BIT | 0x9 | 10-bit control word
619  * ALT_SPIS_CTLR0_CFS_E_SIZE11BIT | 0xa | 11-bit control word
620  * ALT_SPIS_CTLR0_CFS_E_SIZE12BIT | 0xb | 12-bit control word
621  * ALT_SPIS_CTLR0_CFS_E_SIZE13BIT | 0xc | 13-bit control word
622  * ALT_SPIS_CTLR0_CFS_E_SIZE14BIT | 0xd | 14-bit control word
623  * ALT_SPIS_CTLR0_CFS_E_SIZE15BIT | 0xe | 15-bit control word
624  * ALT_SPIS_CTLR0_CFS_E_SIZE16BIT | 0xf | 16-bit control word
625  *
626  * Field Access Macros:
627  *
628  */
629 /*
630  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
631  *
632  * 1-bit control word
633  */
634 #define ALT_SPIS_CTLR0_CFS_E_SIZE1BIT 0x0
635 /*
636  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
637  *
638  * 2-bit control word
639  */
640 #define ALT_SPIS_CTLR0_CFS_E_SIZE2BIT 0x1
641 /*
642  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
643  *
644  * 3-bit control word
645  */
646 #define ALT_SPIS_CTLR0_CFS_E_SIZE3BIT 0x2
647 /*
648  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
649  *
650  * 4-bit control word
651  */
652 #define ALT_SPIS_CTLR0_CFS_E_SIZE4BIT 0x3
653 /*
654  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
655  *
656  * 5-bit control word
657  */
658 #define ALT_SPIS_CTLR0_CFS_E_SIZE5BIT 0x4
659 /*
660  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
661  *
662  * 6-bit control word
663  */
664 #define ALT_SPIS_CTLR0_CFS_E_SIZE6BIT 0x5
665 /*
666  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
667  *
668  * 7-bit control word
669  */
670 #define ALT_SPIS_CTLR0_CFS_E_SIZE7BIT 0x6
671 /*
672  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
673  *
674  * 8-bit control word
675  */
676 #define ALT_SPIS_CTLR0_CFS_E_SIZE8BIT 0x7
677 /*
678  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
679  *
680  * 9-bit control word
681  */
682 #define ALT_SPIS_CTLR0_CFS_E_SIZE9BIT 0x8
683 /*
684  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
685  *
686  * 10-bit control word
687  */
688 #define ALT_SPIS_CTLR0_CFS_E_SIZE10BIT 0x9
689 /*
690  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
691  *
692  * 11-bit control word
693  */
694 #define ALT_SPIS_CTLR0_CFS_E_SIZE11BIT 0xa
695 /*
696  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
697  *
698  * 12-bit control word
699  */
700 #define ALT_SPIS_CTLR0_CFS_E_SIZE12BIT 0xb
701 /*
702  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
703  *
704  * 13-bit control word
705  */
706 #define ALT_SPIS_CTLR0_CFS_E_SIZE13BIT 0xc
707 /*
708  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
709  *
710  * 14-bit control word
711  */
712 #define ALT_SPIS_CTLR0_CFS_E_SIZE14BIT 0xd
713 /*
714  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
715  *
716  * 15-bit control word
717  */
718 #define ALT_SPIS_CTLR0_CFS_E_SIZE15BIT 0xe
719 /*
720  * Enumerated value for register field ALT_SPIS_CTLR0_CFS
721  *
722  * 16-bit control word
723  */
724 #define ALT_SPIS_CTLR0_CFS_E_SIZE16BIT 0xf
725 
726 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_CFS register field. */
727 #define ALT_SPIS_CTLR0_CFS_LSB 12
728 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_CFS register field. */
729 #define ALT_SPIS_CTLR0_CFS_MSB 15
730 /* The width in bits of the ALT_SPIS_CTLR0_CFS register field. */
731 #define ALT_SPIS_CTLR0_CFS_WIDTH 4
732 /* The mask used to set the ALT_SPIS_CTLR0_CFS register field value. */
733 #define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
734 /* The mask used to clear the ALT_SPIS_CTLR0_CFS register field value. */
735 #define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
736 /* The reset value of the ALT_SPIS_CTLR0_CFS register field. */
737 #define ALT_SPIS_CTLR0_CFS_RESET 0x0
738 /* Extracts the ALT_SPIS_CTLR0_CFS field value from a register. */
739 #define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
740 /* Produces a ALT_SPIS_CTLR0_CFS register field value suitable for setting the register. */
741 #define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
742 
743 #ifndef __ASSEMBLY__
744 /*
745  * WARNING: The C register and register group struct declarations are provided for
746  * convenience and illustrative purposes. They should, however, be used with
747  * caution as the C language standard provides no guarantees about the alignment or
748  * atomicity of device memory accesses. The recommended practice for writing
749  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
750  * alt_write_word() functions.
751  *
752  * The struct declaration for register ALT_SPIS_CTLR0.
753  */
754 struct ALT_SPIS_CTLR0_s
755 {
756  uint32_t dfs : 4; /* ALT_SPIS_CTLR0_DFS */
757  uint32_t frf : 2; /* ALT_SPIS_CTLR0_FRF */
758  uint32_t scph : 1; /* ALT_SPIS_CTLR0_SCPH */
759  uint32_t scpol : 1; /* ALT_SPIS_CTLR0_SCPOL */
760  uint32_t tmod : 2; /* ALT_SPIS_CTLR0_TMOD */
761  uint32_t slv_oe : 1; /* ALT_SPIS_CTLR0_SLV_OE */
762  uint32_t srl : 1; /* ALT_SPIS_CTLR0_SRL */
763  uint32_t cfs : 4; /* ALT_SPIS_CTLR0_CFS */
764  uint32_t : 16; /* *UNDEFINED* */
765 };
766 
767 /* The typedef declaration for register ALT_SPIS_CTLR0. */
768 typedef volatile struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t;
769 #endif /* __ASSEMBLY__ */
770 
771 /* The reset value of the ALT_SPIS_CTLR0 register. */
772 #define ALT_SPIS_CTLR0_RESET 0x00000007
773 /* The byte offset of the ALT_SPIS_CTLR0 register from the beginning of the component. */
774 #define ALT_SPIS_CTLR0_OFST 0x0
775 /* The address of the ALT_SPIS_CTLR0 register. */
776 #define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
777 
778 /*
779  * Register : spienr
780  *
781  * SSI Enable Register
782  *
783  * Register Layout
784  *
785  * Bits | Access | Reset | Description
786  * :-------|:-------|:------|:-----------------------
787  * [0] | RW | 0x0 | ALT_SPIS_SPIENR_SPI_EN
788  * [31:1] | ??? | 0x0 | *UNDEFINED*
789  *
790  */
791 /*
792  * Field : spi_en
793  *
794  * SSI Enable. Enables and disables all DW_apb_ssi operations. When
795  *
796  * disabled, all serial transfers are halted immediately. Transmit and
797  *
798  * receive FIFO buffers are cleared when the device is disabled. It is
799  *
800  * impossible to program some of the DW_apb_ssi control registers when
801  *
802  * enabled. When disabled, the ssi_sleep output is set (after delay) to
803  *
804  * inform the system that it is safe to remove the ssi_clk, thus saving
805  *
806  * power consumption in the system.
807  *
808  * Field Enumeration Values:
809  *
810  * Enum | Value | Description
811  * :------------------------------|:------|:------------------------------------
812  * ALT_SPIS_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations
813  * ALT_SPIS_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations
814  *
815  * Field Access Macros:
816  *
817  */
818 /*
819  * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN
820  *
821  * Disables serial transfer operations
822  */
823 #define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
824 /*
825  * Enumerated value for register field ALT_SPIS_SPIENR_SPI_EN
826  *
827  * Enables serial transfer operations
828  */
829 #define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
830 
831 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */
832 #define ALT_SPIS_SPIENR_SPI_EN_LSB 0
833 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SPIENR_SPI_EN register field. */
834 #define ALT_SPIS_SPIENR_SPI_EN_MSB 0
835 /* The width in bits of the ALT_SPIS_SPIENR_SPI_EN register field. */
836 #define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
837 /* The mask used to set the ALT_SPIS_SPIENR_SPI_EN register field value. */
838 #define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
839 /* The mask used to clear the ALT_SPIS_SPIENR_SPI_EN register field value. */
840 #define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
841 /* The reset value of the ALT_SPIS_SPIENR_SPI_EN register field. */
842 #define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
843 /* Extracts the ALT_SPIS_SPIENR_SPI_EN field value from a register. */
844 #define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
845 /* Produces a ALT_SPIS_SPIENR_SPI_EN register field value suitable for setting the register. */
846 #define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
847 
848 #ifndef __ASSEMBLY__
849 /*
850  * WARNING: The C register and register group struct declarations are provided for
851  * convenience and illustrative purposes. They should, however, be used with
852  * caution as the C language standard provides no guarantees about the alignment or
853  * atomicity of device memory accesses. The recommended practice for writing
854  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
855  * alt_write_word() functions.
856  *
857  * The struct declaration for register ALT_SPIS_SPIENR.
858  */
859 struct ALT_SPIS_SPIENR_s
860 {
861  uint32_t spi_en : 1; /* ALT_SPIS_SPIENR_SPI_EN */
862  uint32_t : 31; /* *UNDEFINED* */
863 };
864 
865 /* The typedef declaration for register ALT_SPIS_SPIENR. */
866 typedef volatile struct ALT_SPIS_SPIENR_s ALT_SPIS_SPIENR_t;
867 #endif /* __ASSEMBLY__ */
868 
869 /* The reset value of the ALT_SPIS_SPIENR register. */
870 #define ALT_SPIS_SPIENR_RESET 0x00000000
871 /* The byte offset of the ALT_SPIS_SPIENR register from the beginning of the component. */
872 #define ALT_SPIS_SPIENR_OFST 0x8
873 /* The address of the ALT_SPIS_SPIENR register. */
874 #define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
875 
876 /*
877  * Register : mwcr
878  *
879  * Microwire Control Register.
880  *
881  * This register controls the direction of the data word for the half-duplex
882  *
883  * Microwire serial protocol. It is impossible to write to this register
884  *
885  * when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
886  *
887  * writing to the SSIENR register.
888  *
889  * Register Layout
890  *
891  * Bits | Access | Reset | Description
892  * :-------|:-------|:------|:--------------------
893  * [0] | RW | 0x0 | ALT_SPIS_MWCR_MWMOD
894  * [1] | RW | 0x0 | ALT_SPIS_MWCR_MDD
895  * [31:2] | ??? | 0x0 | *UNDEFINED*
896  *
897  */
898 /*
899  * Field : mwmod
900  *
901  * Microwire Transfer Mode.
902  *
903  * Defines whether the Microwire transfer is sequential or non-sequential.
904  *
905  * When sequential mode is used, only one control word is needed to
906  *
907  * transmit or receive a block of data words. When non-sequential mode is
908  *
909  * used, there must be a control word for each data word that is
910  *
911  * transmitted or received.
912  *
913  * 0: non-sequential transfer
914  *
915  * 1: sequential transfer
916  *
917  * Field Enumeration Values:
918  *
919  * Enum | Value | Description
920  * :-----------------------------|:------|:------------------------
921  * ALT_SPIS_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer
922  * ALT_SPIS_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer
923  *
924  * Field Access Macros:
925  *
926  */
927 /*
928  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
929  *
930  * non-sequential transfer
931  */
932 #define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
933 /*
934  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
935  *
936  * sequential transfer
937  */
938 #define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
939 
940 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
941 #define ALT_SPIS_MWCR_MWMOD_LSB 0
942 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
943 #define ALT_SPIS_MWCR_MWMOD_MSB 0
944 /* The width in bits of the ALT_SPIS_MWCR_MWMOD register field. */
945 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
946 /* The mask used to set the ALT_SPIS_MWCR_MWMOD register field value. */
947 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
948 /* The mask used to clear the ALT_SPIS_MWCR_MWMOD register field value. */
949 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
950 /* The reset value of the ALT_SPIS_MWCR_MWMOD register field. */
951 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
952 /* Extracts the ALT_SPIS_MWCR_MWMOD field value from a register. */
953 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
954 /* Produces a ALT_SPIS_MWCR_MWMOD register field value suitable for setting the register. */
955 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
956 
957 /*
958  * Field : mdd
959  *
960  * Microwire Control.
961  *
962  * Defines the direction of the data word when the Microwire serial protocol
963  *
964  * is used. When this bit is set to 0, the data word is received by the
965  *
966  * DW_apb_ssi MacroCell from the external serial device. When this bit is
967  *
968  * set to 1, the data word is transmitted from the DW_apb_ssi MacroCell to
969  *
970  * the external serial device.
971  *
972  * Field Enumeration Values:
973  *
974  * Enum | Value | Description
975  * :--------------------------|:------|:-------------------------
976  * ALT_SPIS_MWCR_MDD_E_RXMOD | 0x0 | SPI Slave receives data
977  * ALT_SPIS_MWCR_MDD_E_TXMOD | 0x1 | SPI Slave transmits data
978  *
979  * Field Access Macros:
980  *
981  */
982 /*
983  * Enumerated value for register field ALT_SPIS_MWCR_MDD
984  *
985  * SPI Slave receives data
986  */
987 #define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
988 /*
989  * Enumerated value for register field ALT_SPIS_MWCR_MDD
990  *
991  * SPI Slave transmits data
992  */
993 #define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
994 
995 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MDD register field. */
996 #define ALT_SPIS_MWCR_MDD_LSB 1
997 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MDD register field. */
998 #define ALT_SPIS_MWCR_MDD_MSB 1
999 /* The width in bits of the ALT_SPIS_MWCR_MDD register field. */
1000 #define ALT_SPIS_MWCR_MDD_WIDTH 1
1001 /* The mask used to set the ALT_SPIS_MWCR_MDD register field value. */
1002 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
1003 /* The mask used to clear the ALT_SPIS_MWCR_MDD register field value. */
1004 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
1005 /* The reset value of the ALT_SPIS_MWCR_MDD register field. */
1006 #define ALT_SPIS_MWCR_MDD_RESET 0x0
1007 /* Extracts the ALT_SPIS_MWCR_MDD field value from a register. */
1008 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1009 /* Produces a ALT_SPIS_MWCR_MDD register field value suitable for setting the register. */
1010 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1011 
1012 #ifndef __ASSEMBLY__
1013 /*
1014  * WARNING: The C register and register group struct declarations are provided for
1015  * convenience and illustrative purposes. They should, however, be used with
1016  * caution as the C language standard provides no guarantees about the alignment or
1017  * atomicity of device memory accesses. The recommended practice for writing
1018  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1019  * alt_write_word() functions.
1020  *
1021  * The struct declaration for register ALT_SPIS_MWCR.
1022  */
1023 struct ALT_SPIS_MWCR_s
1024 {
1025  uint32_t mwmod : 1; /* ALT_SPIS_MWCR_MWMOD */
1026  uint32_t mdd : 1; /* ALT_SPIS_MWCR_MDD */
1027  uint32_t : 30; /* *UNDEFINED* */
1028 };
1029 
1030 /* The typedef declaration for register ALT_SPIS_MWCR. */
1031 typedef volatile struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
1032 #endif /* __ASSEMBLY__ */
1033 
1034 /* The reset value of the ALT_SPIS_MWCR register. */
1035 #define ALT_SPIS_MWCR_RESET 0x00000000
1036 /* The byte offset of the ALT_SPIS_MWCR register from the beginning of the component. */
1037 #define ALT_SPIS_MWCR_OFST 0xc
1038 /* The address of the ALT_SPIS_MWCR register. */
1039 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
1040 
1041 /*
1042  * Register : txftlr
1043  *
1044  * Transmit FIFO Threshold Level.
1045  *
1046  * This register controls the threshold value for the transmit FIFO memory.
1047  *
1048  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1049  *
1050  * Register Layout
1051  *
1052  * Bits | Access | Reset | Description
1053  * :-------|:-------|:------|:--------------------
1054  * [7:0] | RW | 0x0 | ALT_SPIS_TXFTLR_TFT
1055  * [31:8] | ??? | 0x0 | *UNDEFINED*
1056  *
1057  */
1058 /*
1059  * Field : tft
1060  *
1061  * Transmit FIFO Threshold.
1062  *
1063  * Controls the level of entries (or below) at which the transmit FIFO controller
1064  *
1065  * triggers an interrupt. The FIFO depth is configurable in the range 2-256;
1066  *
1067  * this register is sized to the number of address bits needed to access the
1068  *
1069  * FIFO. If you attempt to set this value greater than or equal to the depth
1070  *
1071  * of the FIFO, this field is not written and retains its current value. When
1072  *
1073  * the number of transmit FIFO entries is less than or equal to this value,
1074  *
1075  * the transmit FIFO empty interrupt is triggered.
1076  *
1077  * Field Access Macros:
1078  *
1079  */
1080 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
1081 #define ALT_SPIS_TXFTLR_TFT_LSB 0
1082 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
1083 #define ALT_SPIS_TXFTLR_TFT_MSB 7
1084 /* The width in bits of the ALT_SPIS_TXFTLR_TFT register field. */
1085 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
1086 /* The mask used to set the ALT_SPIS_TXFTLR_TFT register field value. */
1087 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
1088 /* The mask used to clear the ALT_SPIS_TXFTLR_TFT register field value. */
1089 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
1090 /* The reset value of the ALT_SPIS_TXFTLR_TFT register field. */
1091 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
1092 /* Extracts the ALT_SPIS_TXFTLR_TFT field value from a register. */
1093 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1094 /* Produces a ALT_SPIS_TXFTLR_TFT register field value suitable for setting the register. */
1095 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1096 
1097 #ifndef __ASSEMBLY__
1098 /*
1099  * WARNING: The C register and register group struct declarations are provided for
1100  * convenience and illustrative purposes. They should, however, be used with
1101  * caution as the C language standard provides no guarantees about the alignment or
1102  * atomicity of device memory accesses. The recommended practice for writing
1103  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1104  * alt_write_word() functions.
1105  *
1106  * The struct declaration for register ALT_SPIS_TXFTLR.
1107  */
1108 struct ALT_SPIS_TXFTLR_s
1109 {
1110  uint32_t tft : 8; /* ALT_SPIS_TXFTLR_TFT */
1111  uint32_t : 24; /* *UNDEFINED* */
1112 };
1113 
1114 /* The typedef declaration for register ALT_SPIS_TXFTLR. */
1115 typedef volatile struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
1116 #endif /* __ASSEMBLY__ */
1117 
1118 /* The reset value of the ALT_SPIS_TXFTLR register. */
1119 #define ALT_SPIS_TXFTLR_RESET 0x00000000
1120 /* The byte offset of the ALT_SPIS_TXFTLR register from the beginning of the component. */
1121 #define ALT_SPIS_TXFTLR_OFST 0x18
1122 /* The address of the ALT_SPIS_TXFTLR register. */
1123 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
1124 
1125 /*
1126  * Register : rxftlr
1127  *
1128  * Receive FIFO Threshold level.
1129  *
1130  * This register controls the threshold value for the receive FIFO memory.
1131  *
1132  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1133  *
1134  * Register Layout
1135  *
1136  * Bits | Access | Reset | Description
1137  * :-------|:-------|:------|:--------------------
1138  * [7:0] | RW | 0x0 | ALT_SPIS_RXFTLR_RFT
1139  * [31:8] | ??? | 0x0 | *UNDEFINED*
1140  *
1141  */
1142 /*
1143  * Field : rft
1144  *
1145  * Receive FIFO Threshold.
1146  *
1147  * Controls the level of entries (or above) at which the receive FIFO
1148  *
1149  * controller triggers an interrupt. The FIFO depth is configurable in
1150  *
1151  * the range 2-256. This register is sized to the number of address bits
1152  *
1153  * needed to access the FIFO. If you attempt to set this value greater
1154  *
1155  * than the depth of the FIFO, this field is not written and retains its
1156  *
1157  * current value. When the number of receive FIFO entries is greater than
1158  *
1159  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
1160  *
1161  * Field Access Macros:
1162  *
1163  */
1164 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
1165 #define ALT_SPIS_RXFTLR_RFT_LSB 0
1166 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
1167 #define ALT_SPIS_RXFTLR_RFT_MSB 7
1168 /* The width in bits of the ALT_SPIS_RXFTLR_RFT register field. */
1169 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
1170 /* The mask used to set the ALT_SPIS_RXFTLR_RFT register field value. */
1171 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
1172 /* The mask used to clear the ALT_SPIS_RXFTLR_RFT register field value. */
1173 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
1174 /* The reset value of the ALT_SPIS_RXFTLR_RFT register field. */
1175 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
1176 /* Extracts the ALT_SPIS_RXFTLR_RFT field value from a register. */
1177 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1178 /* Produces a ALT_SPIS_RXFTLR_RFT register field value suitable for setting the register. */
1179 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1180 
1181 #ifndef __ASSEMBLY__
1182 /*
1183  * WARNING: The C register and register group struct declarations are provided for
1184  * convenience and illustrative purposes. They should, however, be used with
1185  * caution as the C language standard provides no guarantees about the alignment or
1186  * atomicity of device memory accesses. The recommended practice for writing
1187  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1188  * alt_write_word() functions.
1189  *
1190  * The struct declaration for register ALT_SPIS_RXFTLR.
1191  */
1192 struct ALT_SPIS_RXFTLR_s
1193 {
1194  uint32_t rft : 8; /* ALT_SPIS_RXFTLR_RFT */
1195  uint32_t : 24; /* *UNDEFINED* */
1196 };
1197 
1198 /* The typedef declaration for register ALT_SPIS_RXFTLR. */
1199 typedef volatile struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
1200 #endif /* __ASSEMBLY__ */
1201 
1202 /* The reset value of the ALT_SPIS_RXFTLR register. */
1203 #define ALT_SPIS_RXFTLR_RESET 0x00000000
1204 /* The byte offset of the ALT_SPIS_RXFTLR register from the beginning of the component. */
1205 #define ALT_SPIS_RXFTLR_OFST 0x1c
1206 /* The address of the ALT_SPIS_RXFTLR register. */
1207 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
1208 
1209 /*
1210  * Register : txflr
1211  *
1212  * Transmit FIFO Level Register
1213  *
1214  * Register Layout
1215  *
1216  * Bits | Access | Reset | Description
1217  * :-------|:-------|:------|:---------------------
1218  * [8:0] | R | 0x0 | ALT_SPIS_TXFLR_TXTFL
1219  * [31:9] | ??? | 0x0 | *UNDEFINED*
1220  *
1221  */
1222 /*
1223  * Field : txtfl
1224  *
1225  * Transmit FIFO Level.
1226  *
1227  * Contains the number of valid data entries in the transmit FIFO.
1228  *
1229  * Field Access Macros:
1230  *
1231  */
1232 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
1233 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
1234 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
1235 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
1236 /* The width in bits of the ALT_SPIS_TXFLR_TXTFL register field. */
1237 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
1238 /* The mask used to set the ALT_SPIS_TXFLR_TXTFL register field value. */
1239 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
1240 /* The mask used to clear the ALT_SPIS_TXFLR_TXTFL register field value. */
1241 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1242 /* The reset value of the ALT_SPIS_TXFLR_TXTFL register field. */
1243 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
1244 /* Extracts the ALT_SPIS_TXFLR_TXTFL field value from a register. */
1245 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1246 /* Produces a ALT_SPIS_TXFLR_TXTFL register field value suitable for setting the register. */
1247 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1248 
1249 #ifndef __ASSEMBLY__
1250 /*
1251  * WARNING: The C register and register group struct declarations are provided for
1252  * convenience and illustrative purposes. They should, however, be used with
1253  * caution as the C language standard provides no guarantees about the alignment or
1254  * atomicity of device memory accesses. The recommended practice for writing
1255  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1256  * alt_write_word() functions.
1257  *
1258  * The struct declaration for register ALT_SPIS_TXFLR.
1259  */
1260 struct ALT_SPIS_TXFLR_s
1261 {
1262  const uint32_t txtfl : 9; /* ALT_SPIS_TXFLR_TXTFL */
1263  uint32_t : 23; /* *UNDEFINED* */
1264 };
1265 
1266 /* The typedef declaration for register ALT_SPIS_TXFLR. */
1267 typedef volatile struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
1268 #endif /* __ASSEMBLY__ */
1269 
1270 /* The reset value of the ALT_SPIS_TXFLR register. */
1271 #define ALT_SPIS_TXFLR_RESET 0x00000000
1272 /* The byte offset of the ALT_SPIS_TXFLR register from the beginning of the component. */
1273 #define ALT_SPIS_TXFLR_OFST 0x20
1274 /* The address of the ALT_SPIS_TXFLR register. */
1275 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
1276 
1277 /*
1278  * Register : rxflr
1279  *
1280  * Receive FIFO Level Register
1281  *
1282  * Register Layout
1283  *
1284  * Bits | Access | Reset | Description
1285  * :-------|:-------|:------|:---------------------
1286  * [8:0] | R | 0x0 | ALT_SPIS_RXFLR_RXTFL
1287  * [31:9] | ??? | 0x0 | *UNDEFINED*
1288  *
1289  */
1290 /*
1291  * Field : rxtfl
1292  *
1293  * Receive FIFO Level.
1294  *
1295  * Contains the number of valid data entries in the receive FIFO.
1296  *
1297  * Field Access Macros:
1298  *
1299  */
1300 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
1301 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
1302 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
1303 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
1304 /* The width in bits of the ALT_SPIS_RXFLR_RXTFL register field. */
1305 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
1306 /* The mask used to set the ALT_SPIS_RXFLR_RXTFL register field value. */
1307 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
1308 /* The mask used to clear the ALT_SPIS_RXFLR_RXTFL register field value. */
1309 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1310 /* The reset value of the ALT_SPIS_RXFLR_RXTFL register field. */
1311 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
1312 /* Extracts the ALT_SPIS_RXFLR_RXTFL field value from a register. */
1313 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1314 /* Produces a ALT_SPIS_RXFLR_RXTFL register field value suitable for setting the register. */
1315 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1316 
1317 #ifndef __ASSEMBLY__
1318 /*
1319  * WARNING: The C register and register group struct declarations are provided for
1320  * convenience and illustrative purposes. They should, however, be used with
1321  * caution as the C language standard provides no guarantees about the alignment or
1322  * atomicity of device memory accesses. The recommended practice for writing
1323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1324  * alt_write_word() functions.
1325  *
1326  * The struct declaration for register ALT_SPIS_RXFLR.
1327  */
1328 struct ALT_SPIS_RXFLR_s
1329 {
1330  const uint32_t rxtfl : 9; /* ALT_SPIS_RXFLR_RXTFL */
1331  uint32_t : 23; /* *UNDEFINED* */
1332 };
1333 
1334 /* The typedef declaration for register ALT_SPIS_RXFLR. */
1335 typedef volatile struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1336 #endif /* __ASSEMBLY__ */
1337 
1338 /* The reset value of the ALT_SPIS_RXFLR register. */
1339 #define ALT_SPIS_RXFLR_RESET 0x00000000
1340 /* The byte offset of the ALT_SPIS_RXFLR register from the beginning of the component. */
1341 #define ALT_SPIS_RXFLR_OFST 0x24
1342 /* The address of the ALT_SPIS_RXFLR register. */
1343 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1344 
1345 /*
1346  * Register : sr
1347  *
1348  * Status Register.
1349  *
1350  * This is a read-only register used to indicate the current transfer status,
1351  *
1352  * FIFO status, and any transmission/reception errors that may have occurred.
1353  *
1354  * The status register may be read at any time. None of the bits in this
1355  *
1356  * register request an interrupt.
1357  *
1358  * Register Layout
1359  *
1360  * Bits | Access | Reset | Description
1361  * :-------|:-------|:------|:-----------------
1362  * [0] | R | 0x0 | ALT_SPIS_SR_BUSY
1363  * [1] | R | 0x1 | ALT_SPIS_SR_TFNF
1364  * [2] | R | 0x1 | ALT_SPIS_SR_TFE
1365  * [3] | R | 0x0 | ALT_SPIS_SR_RFNE
1366  * [4] | R | 0x0 | ALT_SPIS_SR_RFF
1367  * [5] | R | 0x0 | ALT_SPIS_SR_TXE
1368  * [31:6] | ??? | 0x0 | *UNDEFINED*
1369  *
1370  */
1371 /*
1372  * Field : busy
1373  *
1374  * SSI Busy Flag.
1375  *
1376  * When set, indicates that a serial transfer is in progress; when cleared
1377  *
1378  * indicates that the DW_apb_ssi is idle or disabled.
1379  *
1380  * 0 - DW_apb_ssi is idle or disabled
1381  *
1382  * 1 - DW_apb_ssi is actively transferring data
1383  *
1384  * Field Enumeration Values:
1385  *
1386  * Enum | Value | Description
1387  * :-------------------------|:------|:-----------------------------------------
1388  * ALT_SPIS_SR_BUSY_E_INACT | 0x0 | SPI Slave is inactive (idle or disabled)
1389  * ALT_SPIS_SR_BUSY_E_ACT | 0x1 | SPI Slave is actively transferring data
1390  *
1391  * Field Access Macros:
1392  *
1393  */
1394 /*
1395  * Enumerated value for register field ALT_SPIS_SR_BUSY
1396  *
1397  * SPI Slave is inactive (idle or disabled)
1398  */
1399 #define ALT_SPIS_SR_BUSY_E_INACT 0x0
1400 /*
1401  * Enumerated value for register field ALT_SPIS_SR_BUSY
1402  *
1403  * SPI Slave is actively transferring data
1404  */
1405 #define ALT_SPIS_SR_BUSY_E_ACT 0x1
1406 
1407 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_BUSY register field. */
1408 #define ALT_SPIS_SR_BUSY_LSB 0
1409 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_BUSY register field. */
1410 #define ALT_SPIS_SR_BUSY_MSB 0
1411 /* The width in bits of the ALT_SPIS_SR_BUSY register field. */
1412 #define ALT_SPIS_SR_BUSY_WIDTH 1
1413 /* The mask used to set the ALT_SPIS_SR_BUSY register field value. */
1414 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1415 /* The mask used to clear the ALT_SPIS_SR_BUSY register field value. */
1416 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1417 /* The reset value of the ALT_SPIS_SR_BUSY register field. */
1418 #define ALT_SPIS_SR_BUSY_RESET 0x0
1419 /* Extracts the ALT_SPIS_SR_BUSY field value from a register. */
1420 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1421 /* Produces a ALT_SPIS_SR_BUSY register field value suitable for setting the register. */
1422 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1423 
1424 /*
1425  * Field : tfnf
1426  *
1427  * Transmit FIFO Not Full. Set when the transmit FIFO contains one or more
1428  *
1429  * empty locations, and is cleared when the FIFO is full.
1430  *
1431  * 0 - Transmit FIFO is full
1432  *
1433  * 1 - Transmit FIFO is not full
1434  *
1435  * Field Enumeration Values:
1436  *
1437  * Enum | Value | Description
1438  * :---------------------------|:------|:--------------------------
1439  * ALT_SPIS_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
1440  * ALT_SPIS_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
1441  *
1442  * Field Access Macros:
1443  *
1444  */
1445 /*
1446  * Enumerated value for register field ALT_SPIS_SR_TFNF
1447  *
1448  * Transmit FIFO is full
1449  */
1450 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1451 /*
1452  * Enumerated value for register field ALT_SPIS_SR_TFNF
1453  *
1454  * Transmit FIFO is not full
1455  */
1456 #define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1457 
1458 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFNF register field. */
1459 #define ALT_SPIS_SR_TFNF_LSB 1
1460 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFNF register field. */
1461 #define ALT_SPIS_SR_TFNF_MSB 1
1462 /* The width in bits of the ALT_SPIS_SR_TFNF register field. */
1463 #define ALT_SPIS_SR_TFNF_WIDTH 1
1464 /* The mask used to set the ALT_SPIS_SR_TFNF register field value. */
1465 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1466 /* The mask used to clear the ALT_SPIS_SR_TFNF register field value. */
1467 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1468 /* The reset value of the ALT_SPIS_SR_TFNF register field. */
1469 #define ALT_SPIS_SR_TFNF_RESET 0x1
1470 /* Extracts the ALT_SPIS_SR_TFNF field value from a register. */
1471 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1472 /* Produces a ALT_SPIS_SR_TFNF register field value suitable for setting the register. */
1473 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1474 
1475 /*
1476  * Field : tfe
1477  *
1478  * Transmit FIFO Empty.
1479  *
1480  * When the transmit FIFO is completely empty, this bit is set. When the
1481  *
1482  * transmit FIFO contains one or more valid entries, this bit is cleared.
1483  *
1484  * This bit field does not request an interrupt.
1485  *
1486  * 0 - Transmit FIFO is not empty
1487  *
1488  * 1 - Transmit FIFO is empty
1489  *
1490  * Field Enumeration Values:
1491  *
1492  * Enum | Value | Description
1493  * :---------------------------|:------|:---------------------------
1494  * ALT_SPIS_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
1495  * ALT_SPIS_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
1496  *
1497  * Field Access Macros:
1498  *
1499  */
1500 /*
1501  * Enumerated value for register field ALT_SPIS_SR_TFE
1502  *
1503  * Transmit FIFO is not empty
1504  */
1505 #define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1506 /*
1507  * Enumerated value for register field ALT_SPIS_SR_TFE
1508  *
1509  * Transmit FIFO is empty
1510  */
1511 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1512 
1513 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFE register field. */
1514 #define ALT_SPIS_SR_TFE_LSB 2
1515 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFE register field. */
1516 #define ALT_SPIS_SR_TFE_MSB 2
1517 /* The width in bits of the ALT_SPIS_SR_TFE register field. */
1518 #define ALT_SPIS_SR_TFE_WIDTH 1
1519 /* The mask used to set the ALT_SPIS_SR_TFE register field value. */
1520 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1521 /* The mask used to clear the ALT_SPIS_SR_TFE register field value. */
1522 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1523 /* The reset value of the ALT_SPIS_SR_TFE register field. */
1524 #define ALT_SPIS_SR_TFE_RESET 0x1
1525 /* Extracts the ALT_SPIS_SR_TFE field value from a register. */
1526 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1527 /* Produces a ALT_SPIS_SR_TFE register field value suitable for setting the register. */
1528 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1529 
1530 /*
1531  * Field : rfne
1532  *
1533  * Receive FIFO Not Empty.
1534  *
1535  * Set when the receive FIFO contains one or more entries and is cleared
1536  *
1537  * when the receive FIFO is empty. This bit can be polled by software to
1538  *
1539  * completely empty the receive FIFO.
1540  *
1541  * 0 - Receive FIFO is empty
1542  *
1543  * 1 - Receive FIFO is not empty
1544  *
1545  * Field Enumeration Values:
1546  *
1547  * Enum | Value | Description
1548  * :----------------------------|:------|:--------------------------
1549  * ALT_SPIS_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
1550  * ALT_SPIS_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
1551  *
1552  * Field Access Macros:
1553  *
1554  */
1555 /*
1556  * Enumerated value for register field ALT_SPIS_SR_RFNE
1557  *
1558  * Receive FIFO is empty
1559  */
1560 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1561 /*
1562  * Enumerated value for register field ALT_SPIS_SR_RFNE
1563  *
1564  * Receive FIFO is not empty
1565  */
1566 #define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1567 
1568 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFNE register field. */
1569 #define ALT_SPIS_SR_RFNE_LSB 3
1570 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFNE register field. */
1571 #define ALT_SPIS_SR_RFNE_MSB 3
1572 /* The width in bits of the ALT_SPIS_SR_RFNE register field. */
1573 #define ALT_SPIS_SR_RFNE_WIDTH 1
1574 /* The mask used to set the ALT_SPIS_SR_RFNE register field value. */
1575 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1576 /* The mask used to clear the ALT_SPIS_SR_RFNE register field value. */
1577 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1578 /* The reset value of the ALT_SPIS_SR_RFNE register field. */
1579 #define ALT_SPIS_SR_RFNE_RESET 0x0
1580 /* Extracts the ALT_SPIS_SR_RFNE field value from a register. */
1581 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1582 /* Produces a ALT_SPIS_SR_RFNE register field value suitable for setting the register. */
1583 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1584 
1585 /*
1586  * Field : rff
1587  *
1588  * Receive FIFO Full. When the receive FIFO is completely full, this bit
1589  *
1590  * is set. When the receive FIFO contains one or more empty location, this
1591  *
1592  * bit is cleared.
1593  *
1594  * 0 - Receive FIFO is not full
1595  *
1596  * 1 - Receive FIFO is full
1597  *
1598  * Field Enumeration Values:
1599  *
1600  * Enum | Value | Description
1601  * :--------------------------|:------|:-------------------------
1602  * ALT_SPIS_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
1603  * ALT_SPIS_SR_RFF_E_FULL | 0x1 | Receive FIFO is full
1604  *
1605  * Field Access Macros:
1606  *
1607  */
1608 /*
1609  * Enumerated value for register field ALT_SPIS_SR_RFF
1610  *
1611  * Receive FIFO is not full
1612  */
1613 #define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1614 /*
1615  * Enumerated value for register field ALT_SPIS_SR_RFF
1616  *
1617  * Receive FIFO is full
1618  */
1619 #define ALT_SPIS_SR_RFF_E_FULL 0x1
1620 
1621 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFF register field. */
1622 #define ALT_SPIS_SR_RFF_LSB 4
1623 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFF register field. */
1624 #define ALT_SPIS_SR_RFF_MSB 4
1625 /* The width in bits of the ALT_SPIS_SR_RFF register field. */
1626 #define ALT_SPIS_SR_RFF_WIDTH 1
1627 /* The mask used to set the ALT_SPIS_SR_RFF register field value. */
1628 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1629 /* The mask used to clear the ALT_SPIS_SR_RFF register field value. */
1630 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1631 /* The reset value of the ALT_SPIS_SR_RFF register field. */
1632 #define ALT_SPIS_SR_RFF_RESET 0x0
1633 /* Extracts the ALT_SPIS_SR_RFF field value from a register. */
1634 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1635 /* Produces a ALT_SPIS_SR_RFF register field value suitable for setting the register. */
1636 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1637 
1638 /*
1639  * Field : txe
1640  *
1641  * Transmission Error.
1642  *
1643  * Set if the transmit FIFO is empty when a transfer is started. This bit can
1644  *
1645  * be set only when the DW_apb_ssi is configured as a slave device. Datafrom
1646  *
1647  * the previous transmission is resent on the txd line. This bit is cleared
1648  *
1649  * when read.
1650  *
1651  * 0 - No error
1652  *
1653  * 1 - Transmission error
1654  *
1655  * Field Enumeration Values:
1656  *
1657  * Enum | Value | Description
1658  * :--------------------------|:------|:-------------------
1659  * ALT_SPIS_SR_TXE_E_NOERROR | 0x0 | No Error
1660  * ALT_SPIS_SR_TXE_E_ERROR | 0x1 | Transmission Error
1661  *
1662  * Field Access Macros:
1663  *
1664  */
1665 /*
1666  * Enumerated value for register field ALT_SPIS_SR_TXE
1667  *
1668  * No Error
1669  */
1670 #define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1671 /*
1672  * Enumerated value for register field ALT_SPIS_SR_TXE
1673  *
1674  * Transmission Error
1675  */
1676 #define ALT_SPIS_SR_TXE_E_ERROR 0x1
1677 
1678 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TXE register field. */
1679 #define ALT_SPIS_SR_TXE_LSB 5
1680 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TXE register field. */
1681 #define ALT_SPIS_SR_TXE_MSB 5
1682 /* The width in bits of the ALT_SPIS_SR_TXE register field. */
1683 #define ALT_SPIS_SR_TXE_WIDTH 1
1684 /* The mask used to set the ALT_SPIS_SR_TXE register field value. */
1685 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1686 /* The mask used to clear the ALT_SPIS_SR_TXE register field value. */
1687 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1688 /* The reset value of the ALT_SPIS_SR_TXE register field. */
1689 #define ALT_SPIS_SR_TXE_RESET 0x0
1690 /* Extracts the ALT_SPIS_SR_TXE field value from a register. */
1691 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1692 /* Produces a ALT_SPIS_SR_TXE register field value suitable for setting the register. */
1693 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1694 
1695 #ifndef __ASSEMBLY__
1696 /*
1697  * WARNING: The C register and register group struct declarations are provided for
1698  * convenience and illustrative purposes. They should, however, be used with
1699  * caution as the C language standard provides no guarantees about the alignment or
1700  * atomicity of device memory accesses. The recommended practice for writing
1701  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1702  * alt_write_word() functions.
1703  *
1704  * The struct declaration for register ALT_SPIS_SR.
1705  */
1706 struct ALT_SPIS_SR_s
1707 {
1708  const uint32_t busy : 1; /* ALT_SPIS_SR_BUSY */
1709  const uint32_t tfnf : 1; /* ALT_SPIS_SR_TFNF */
1710  const uint32_t tfe : 1; /* ALT_SPIS_SR_TFE */
1711  const uint32_t rfne : 1; /* ALT_SPIS_SR_RFNE */
1712  const uint32_t rff : 1; /* ALT_SPIS_SR_RFF */
1713  const uint32_t txe : 1; /* ALT_SPIS_SR_TXE */
1714  uint32_t : 26; /* *UNDEFINED* */
1715 };
1716 
1717 /* The typedef declaration for register ALT_SPIS_SR. */
1718 typedef volatile struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
1719 #endif /* __ASSEMBLY__ */
1720 
1721 /* The reset value of the ALT_SPIS_SR register. */
1722 #define ALT_SPIS_SR_RESET 0x00000006
1723 /* The byte offset of the ALT_SPIS_SR register from the beginning of the component. */
1724 #define ALT_SPIS_SR_OFST 0x28
1725 /* The address of the ALT_SPIS_SR register. */
1726 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1727 
1728 /*
1729  * Register : imr
1730  *
1731  * Interrupt Mask Register
1732  *
1733  * Register Layout
1734  *
1735  * Bits | Access | Reset | Description
1736  * :-------|:-------|:------|:-------------------
1737  * [0] | RW | 0x1 | ALT_SPIS_IMR_TXEIM
1738  * [1] | RW | 0x1 | ALT_SPIS_IMR_TXOIM
1739  * [2] | RW | 0x1 | ALT_SPIS_IMR_RXUIM
1740  * [3] | RW | 0x1 | ALT_SPIS_IMR_RXOIM
1741  * [4] | RW | 0x1 | ALT_SPIS_IMR_RXFIM
1742  * [31:5] | ??? | 0x0 | *UNDEFINED*
1743  *
1744  */
1745 /*
1746  * Field : txeim
1747  *
1748  * Transmit FIFO Empty Interrupt Mask
1749  *
1750  * 0 - ssi_txe_intr interrupt is masked
1751  *
1752  * 1 - ssi_txe_intr interrupt is not masked
1753  *
1754  * Field Enumeration Values:
1755  *
1756  * Enum | Value | Description
1757  * :---------------------------|:------|:--------------------------------------------
1758  * ALT_SPIS_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled)
1759  * ALT_SPIS_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled
1760  *
1761  * Field Access Macros:
1762  *
1763  */
1764 /*
1765  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
1766  *
1767  * spi_txe_intr interrupt is masked (disabled)
1768  */
1769 #define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1770 /*
1771  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
1772  *
1773  * spi_txe_intr interrupt is enabled
1774  */
1775 #define ALT_SPIS_IMR_TXEIM_E_END 0x1
1776 
1777 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXEIM register field. */
1778 #define ALT_SPIS_IMR_TXEIM_LSB 0
1779 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXEIM register field. */
1780 #define ALT_SPIS_IMR_TXEIM_MSB 0
1781 /* The width in bits of the ALT_SPIS_IMR_TXEIM register field. */
1782 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
1783 /* The mask used to set the ALT_SPIS_IMR_TXEIM register field value. */
1784 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1785 /* The mask used to clear the ALT_SPIS_IMR_TXEIM register field value. */
1786 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1787 /* The reset value of the ALT_SPIS_IMR_TXEIM register field. */
1788 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
1789 /* Extracts the ALT_SPIS_IMR_TXEIM field value from a register. */
1790 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1791 /* Produces a ALT_SPIS_IMR_TXEIM register field value suitable for setting the register. */
1792 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1793 
1794 /*
1795  * Field : txoim
1796  *
1797  * Transmit FIFO Overflow Interrupt Mask
1798  *
1799  * 0 - ssi_txo_intr interrupt is masked
1800  *
1801  * 1 - ssi_txo_intr interrupt is not masked
1802  *
1803  * Field Enumeration Values:
1804  *
1805  * Enum | Value | Description
1806  * :---------------------------|:------|:--------------------------------------------
1807  * ALT_SPIS_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled)
1808  * ALT_SPIS_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled
1809  *
1810  * Field Access Macros:
1811  *
1812  */
1813 /*
1814  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
1815  *
1816  * spi_txo_intr interrupt is masked (disabled)
1817  */
1818 #define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1819 /*
1820  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
1821  *
1822  * spi_txo_intr interrupt is enabled
1823  */
1824 #define ALT_SPIS_IMR_TXOIM_E_END 0x1
1825 
1826 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXOIM register field. */
1827 #define ALT_SPIS_IMR_TXOIM_LSB 1
1828 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXOIM register field. */
1829 #define ALT_SPIS_IMR_TXOIM_MSB 1
1830 /* The width in bits of the ALT_SPIS_IMR_TXOIM register field. */
1831 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
1832 /* The mask used to set the ALT_SPIS_IMR_TXOIM register field value. */
1833 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1834 /* The mask used to clear the ALT_SPIS_IMR_TXOIM register field value. */
1835 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1836 /* The reset value of the ALT_SPIS_IMR_TXOIM register field. */
1837 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
1838 /* Extracts the ALT_SPIS_IMR_TXOIM field value from a register. */
1839 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1840 /* Produces a ALT_SPIS_IMR_TXOIM register field value suitable for setting the register. */
1841 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1842 
1843 /*
1844  * Field : rxuim
1845  *
1846  * Receive FIFO Underflow Interrupt Mask
1847  *
1848  * 0 - ssi_rxu_intr interrupt is masked
1849  *
1850  * 1 - ssi_rxu_intr interrupt is not masked
1851  *
1852  * Field Enumeration Values:
1853  *
1854  * Enum | Value | Description
1855  * :---------------------------|:------|:--------------------------------------------
1856  * ALT_SPIS_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled)
1857  * ALT_SPIS_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled
1858  *
1859  * Field Access Macros:
1860  *
1861  */
1862 /*
1863  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
1864  *
1865  * spi_rxu_intr interrupt is masked (disabled)
1866  */
1867 #define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1868 /*
1869  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
1870  *
1871  * spi_rxu_intr interrupt is enabled
1872  */
1873 #define ALT_SPIS_IMR_RXUIM_E_END 0x1
1874 
1875 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXUIM register field. */
1876 #define ALT_SPIS_IMR_RXUIM_LSB 2
1877 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXUIM register field. */
1878 #define ALT_SPIS_IMR_RXUIM_MSB 2
1879 /* The width in bits of the ALT_SPIS_IMR_RXUIM register field. */
1880 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
1881 /* The mask used to set the ALT_SPIS_IMR_RXUIM register field value. */
1882 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1883 /* The mask used to clear the ALT_SPIS_IMR_RXUIM register field value. */
1884 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1885 /* The reset value of the ALT_SPIS_IMR_RXUIM register field. */
1886 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
1887 /* Extracts the ALT_SPIS_IMR_RXUIM field value from a register. */
1888 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1889 /* Produces a ALT_SPIS_IMR_RXUIM register field value suitable for setting the register. */
1890 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1891 
1892 /*
1893  * Field : rxoim
1894  *
1895  * Receive FIFO Overflow Interrupt Mask
1896  *
1897  * 0 - ssi_rxo_intr interrupt is masked
1898  *
1899  * 1 - ssi_rxo_intr interrupt is not masked
1900  *
1901  * Field Enumeration Values:
1902  *
1903  * Enum | Value | Description
1904  * :---------------------------|:------|:--------------------------------------------
1905  * ALT_SPIS_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled)
1906  * ALT_SPIS_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled
1907  *
1908  * Field Access Macros:
1909  *
1910  */
1911 /*
1912  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
1913  *
1914  * spi_rxo_intr interrupt is masked (disabled)
1915  */
1916 #define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1917 /*
1918  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
1919  *
1920  * spi_rxo_intr interrupt is enabled
1921  */
1922 #define ALT_SPIS_IMR_RXOIM_E_END 0x1
1923 
1924 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXOIM register field. */
1925 #define ALT_SPIS_IMR_RXOIM_LSB 3
1926 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXOIM register field. */
1927 #define ALT_SPIS_IMR_RXOIM_MSB 3
1928 /* The width in bits of the ALT_SPIS_IMR_RXOIM register field. */
1929 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
1930 /* The mask used to set the ALT_SPIS_IMR_RXOIM register field value. */
1931 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1932 /* The mask used to clear the ALT_SPIS_IMR_RXOIM register field value. */
1933 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1934 /* The reset value of the ALT_SPIS_IMR_RXOIM register field. */
1935 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
1936 /* Extracts the ALT_SPIS_IMR_RXOIM field value from a register. */
1937 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1938 /* Produces a ALT_SPIS_IMR_RXOIM register field value suitable for setting the register. */
1939 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1940 
1941 /*
1942  * Field : rxfim
1943  *
1944  * Receive FIFO Full Interrupt Mask
1945  *
1946  * 0 - ssi_rxf_intr interrupt is masked
1947  *
1948  * 1 - ssi_rxf_intr interrupt is not masked
1949  *
1950  * Field Enumeration Values:
1951  *
1952  * Enum | Value | Description
1953  * :---------------------------|:------|:--------------------------------------------
1954  * ALT_SPIS_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled)
1955  * ALT_SPIS_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled
1956  *
1957  * Field Access Macros:
1958  *
1959  */
1960 /*
1961  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
1962  *
1963  * spi_rxf_intr interrupt is masked (disabled)
1964  */
1965 #define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1966 /*
1967  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
1968  *
1969  * spi_rxf_intr interrupt is enabled
1970  */
1971 #define ALT_SPIS_IMR_RXFIM_E_END 0x1
1972 
1973 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXFIM register field. */
1974 #define ALT_SPIS_IMR_RXFIM_LSB 4
1975 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXFIM register field. */
1976 #define ALT_SPIS_IMR_RXFIM_MSB 4
1977 /* The width in bits of the ALT_SPIS_IMR_RXFIM register field. */
1978 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
1979 /* The mask used to set the ALT_SPIS_IMR_RXFIM register field value. */
1980 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1981 /* The mask used to clear the ALT_SPIS_IMR_RXFIM register field value. */
1982 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1983 /* The reset value of the ALT_SPIS_IMR_RXFIM register field. */
1984 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
1985 /* Extracts the ALT_SPIS_IMR_RXFIM field value from a register. */
1986 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1987 /* Produces a ALT_SPIS_IMR_RXFIM register field value suitable for setting the register. */
1988 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1989 
1990 #ifndef __ASSEMBLY__
1991 /*
1992  * WARNING: The C register and register group struct declarations are provided for
1993  * convenience and illustrative purposes. They should, however, be used with
1994  * caution as the C language standard provides no guarantees about the alignment or
1995  * atomicity of device memory accesses. The recommended practice for writing
1996  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1997  * alt_write_word() functions.
1998  *
1999  * The struct declaration for register ALT_SPIS_IMR.
2000  */
2001 struct ALT_SPIS_IMR_s
2002 {
2003  uint32_t txeim : 1; /* ALT_SPIS_IMR_TXEIM */
2004  uint32_t txoim : 1; /* ALT_SPIS_IMR_TXOIM */
2005  uint32_t rxuim : 1; /* ALT_SPIS_IMR_RXUIM */
2006  uint32_t rxoim : 1; /* ALT_SPIS_IMR_RXOIM */
2007  uint32_t rxfim : 1; /* ALT_SPIS_IMR_RXFIM */
2008  uint32_t : 27; /* *UNDEFINED* */
2009 };
2010 
2011 /* The typedef declaration for register ALT_SPIS_IMR. */
2012 typedef volatile struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
2013 #endif /* __ASSEMBLY__ */
2014 
2015 /* The reset value of the ALT_SPIS_IMR register. */
2016 #define ALT_SPIS_IMR_RESET 0x0000001f
2017 /* The byte offset of the ALT_SPIS_IMR register from the beginning of the component. */
2018 #define ALT_SPIS_IMR_OFST 0x2c
2019 /* The address of the ALT_SPIS_IMR register. */
2020 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
2021 
2022 /*
2023  * Register : isr
2024  *
2025  * Interrupt Status Register
2026  *
2027  * Register Layout
2028  *
2029  * Bits | Access | Reset | Description
2030  * :-------|:-------|:------|:-------------------
2031  * [0] | R | 0x0 | ALT_SPIS_ISR_TXEIS
2032  * [1] | R | 0x0 | ALT_SPIS_ISR_TXOIS
2033  * [2] | R | 0x0 | ALT_SPIS_ISR_RXUIS
2034  * [3] | R | 0x0 | ALT_SPIS_ISR_RXOIS
2035  * [4] | R | 0x0 | ALT_SPIS_ISR_RXFIS
2036  * [31:5] | ??? | 0x0 | *UNDEFINED*
2037  *
2038  */
2039 /*
2040  * Field : txeis
2041  *
2042  * Transmit FIFO Empty Interrupt Status
2043  *
2044  * 0 = ssi_txe_intr interrupt is not active after masking
2045  *
2046  * 1 = ssi_txe_intr interrupt is active after masking
2047  *
2048  * Field Enumeration Values:
2049  *
2050  * Enum | Value | Description
2051  * :---------------------------|:------|:-----------------------------------------------
2052  * ALT_SPIS_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after
2053  * : | | masking
2054  * ALT_SPIS_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking
2055  *
2056  * Field Access Macros:
2057  *
2058  */
2059 /*
2060  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
2061  *
2062  * spi_txe_intr interrupt is not active after masking
2063  */
2064 #define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
2065 /*
2066  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
2067  *
2068  * spi_txe_intr interrupt is active after masking
2069  */
2070 #define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
2071 
2072 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXEIS register field. */
2073 #define ALT_SPIS_ISR_TXEIS_LSB 0
2074 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXEIS register field. */
2075 #define ALT_SPIS_ISR_TXEIS_MSB 0
2076 /* The width in bits of the ALT_SPIS_ISR_TXEIS register field. */
2077 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
2078 /* The mask used to set the ALT_SPIS_ISR_TXEIS register field value. */
2079 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
2080 /* The mask used to clear the ALT_SPIS_ISR_TXEIS register field value. */
2081 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
2082 /* The reset value of the ALT_SPIS_ISR_TXEIS register field. */
2083 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
2084 /* Extracts the ALT_SPIS_ISR_TXEIS field value from a register. */
2085 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2086 /* Produces a ALT_SPIS_ISR_TXEIS register field value suitable for setting the register. */
2087 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2088 
2089 /*
2090  * Field : txois
2091  *
2092  * Transmit FIFO Overflow Interrupt Status
2093  *
2094  * 0 = ssi_txo_intr interrupt is not active after masking
2095  *
2096  * 1 = ssi_txo_intr interrupt is active after masking
2097  *
2098  * Field Enumeration Values:
2099  *
2100  * Enum | Value | Description
2101  * :---------------------------|:------|:-----------------------------------------------
2102  * ALT_SPIS_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after
2103  * : | | masking
2104  * ALT_SPIS_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking
2105  *
2106  * Field Access Macros:
2107  *
2108  */
2109 /*
2110  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
2111  *
2112  * spi_txo_intr interrupt is not active after masking
2113  */
2114 #define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
2115 /*
2116  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
2117  *
2118  * spi_txo_intr interrupt is active after masking
2119  */
2120 #define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
2121 
2122 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXOIS register field. */
2123 #define ALT_SPIS_ISR_TXOIS_LSB 1
2124 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXOIS register field. */
2125 #define ALT_SPIS_ISR_TXOIS_MSB 1
2126 /* The width in bits of the ALT_SPIS_ISR_TXOIS register field. */
2127 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
2128 /* The mask used to set the ALT_SPIS_ISR_TXOIS register field value. */
2129 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
2130 /* The mask used to clear the ALT_SPIS_ISR_TXOIS register field value. */
2131 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
2132 /* The reset value of the ALT_SPIS_ISR_TXOIS register field. */
2133 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
2134 /* Extracts the ALT_SPIS_ISR_TXOIS field value from a register. */
2135 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2136 /* Produces a ALT_SPIS_ISR_TXOIS register field value suitable for setting the register. */
2137 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2138 
2139 /*
2140  * Field : rxuis
2141  *
2142  * Receive FIFO Underflow Interrupt Status
2143  *
2144  * 0 = ssi_rxu_intr interrupt is not active after masking
2145  *
2146  * 1 = ssi_rxu_intr interrupt is active after masking
2147  *
2148  * Field Enumeration Values:
2149  *
2150  * Enum | Value | Description
2151  * :---------------------------|:------|:-----------------------------------------------
2152  * ALT_SPIS_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after
2153  * : | | masking
2154  * ALT_SPIS_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking
2155  *
2156  * Field Access Macros:
2157  *
2158  */
2159 /*
2160  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
2161  *
2162  * spi_rxu_intr interrupt is not active after masking
2163  */
2164 #define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
2165 /*
2166  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
2167  *
2168  * spi_rxu_intr interrupt is active after masking
2169  */
2170 #define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
2171 
2172 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXUIS register field. */
2173 #define ALT_SPIS_ISR_RXUIS_LSB 2
2174 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXUIS register field. */
2175 #define ALT_SPIS_ISR_RXUIS_MSB 2
2176 /* The width in bits of the ALT_SPIS_ISR_RXUIS register field. */
2177 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
2178 /* The mask used to set the ALT_SPIS_ISR_RXUIS register field value. */
2179 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
2180 /* The mask used to clear the ALT_SPIS_ISR_RXUIS register field value. */
2181 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
2182 /* The reset value of the ALT_SPIS_ISR_RXUIS register field. */
2183 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
2184 /* Extracts the ALT_SPIS_ISR_RXUIS field value from a register. */
2185 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2186 /* Produces a ALT_SPIS_ISR_RXUIS register field value suitable for setting the register. */
2187 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2188 
2189 /*
2190  * Field : rxois
2191  *
2192  * Receive FIFO Overflow Interrupt Status
2193  *
2194  * 0 = ssi_rxo_intr interrupt is not active after masking
2195  *
2196  * 1 = ssi_rxo_intr interrupt is active after masking
2197  *
2198  * Field Enumeration Values:
2199  *
2200  * Enum | Value | Description
2201  * :---------------------------|:------|:-----------------------------------------------
2202  * ALT_SPIS_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after
2203  * : | | masking
2204  * ALT_SPIS_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking
2205  *
2206  * Field Access Macros:
2207  *
2208  */
2209 /*
2210  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
2211  *
2212  * spi_rxo_intr interrupt is not active after masking
2213  */
2214 #define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
2215 /*
2216  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
2217  *
2218  * spi_rxo_intr interrupt is active after masking
2219  */
2220 #define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
2221 
2222 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXOIS register field. */
2223 #define ALT_SPIS_ISR_RXOIS_LSB 3
2224 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXOIS register field. */
2225 #define ALT_SPIS_ISR_RXOIS_MSB 3
2226 /* The width in bits of the ALT_SPIS_ISR_RXOIS register field. */
2227 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
2228 /* The mask used to set the ALT_SPIS_ISR_RXOIS register field value. */
2229 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
2230 /* The mask used to clear the ALT_SPIS_ISR_RXOIS register field value. */
2231 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
2232 /* The reset value of the ALT_SPIS_ISR_RXOIS register field. */
2233 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
2234 /* Extracts the ALT_SPIS_ISR_RXOIS field value from a register. */
2235 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2236 /* Produces a ALT_SPIS_ISR_RXOIS register field value suitable for setting the register. */
2237 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2238 
2239 /*
2240  * Field : rxfis
2241  *
2242  * Receive FIFO Full Interrupt Status
2243  *
2244  * 0 = ssi_rxf_intr interrupt is not active after masking
2245  *
2246  * 1 = ssi_rxf_intr interrupt is full after masking
2247  *
2248  * Field Enumeration Values:
2249  *
2250  * Enum | Value | Description
2251  * :---------------------------|:------|:---------------------------------------------
2252  * ALT_SPIS_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after
2253  * : | | masking
2254  * ALT_SPIS_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking
2255  *
2256  * Field Access Macros:
2257  *
2258  */
2259 /*
2260  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
2261  *
2262  * spi_rxf_intr interrupt is not active after masking
2263  */
2264 #define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
2265 /*
2266  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
2267  *
2268  * spi_rxf_intr interrupt is full after masking
2269  */
2270 #define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
2271 
2272 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXFIS register field. */
2273 #define ALT_SPIS_ISR_RXFIS_LSB 4
2274 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXFIS register field. */
2275 #define ALT_SPIS_ISR_RXFIS_MSB 4
2276 /* The width in bits of the ALT_SPIS_ISR_RXFIS register field. */
2277 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
2278 /* The mask used to set the ALT_SPIS_ISR_RXFIS register field value. */
2279 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
2280 /* The mask used to clear the ALT_SPIS_ISR_RXFIS register field value. */
2281 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
2282 /* The reset value of the ALT_SPIS_ISR_RXFIS register field. */
2283 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
2284 /* Extracts the ALT_SPIS_ISR_RXFIS field value from a register. */
2285 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2286 /* Produces a ALT_SPIS_ISR_RXFIS register field value suitable for setting the register. */
2287 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2288 
2289 #ifndef __ASSEMBLY__
2290 /*
2291  * WARNING: The C register and register group struct declarations are provided for
2292  * convenience and illustrative purposes. They should, however, be used with
2293  * caution as the C language standard provides no guarantees about the alignment or
2294  * atomicity of device memory accesses. The recommended practice for writing
2295  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2296  * alt_write_word() functions.
2297  *
2298  * The struct declaration for register ALT_SPIS_ISR.
2299  */
2300 struct ALT_SPIS_ISR_s
2301 {
2302  const uint32_t txeis : 1; /* ALT_SPIS_ISR_TXEIS */
2303  const uint32_t txois : 1; /* ALT_SPIS_ISR_TXOIS */
2304  const uint32_t rxuis : 1; /* ALT_SPIS_ISR_RXUIS */
2305  const uint32_t rxois : 1; /* ALT_SPIS_ISR_RXOIS */
2306  const uint32_t rxfis : 1; /* ALT_SPIS_ISR_RXFIS */
2307  uint32_t : 27; /* *UNDEFINED* */
2308 };
2309 
2310 /* The typedef declaration for register ALT_SPIS_ISR. */
2311 typedef volatile struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
2312 #endif /* __ASSEMBLY__ */
2313 
2314 /* The reset value of the ALT_SPIS_ISR register. */
2315 #define ALT_SPIS_ISR_RESET 0x00000000
2316 /* The byte offset of the ALT_SPIS_ISR register from the beginning of the component. */
2317 #define ALT_SPIS_ISR_OFST 0x30
2318 /* The address of the ALT_SPIS_ISR register. */
2319 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
2320 
2321 /*
2322  * Register : risr
2323  *
2324  * Raw Interrupt StatusRegister
2325  *
2326  * Register Layout
2327  *
2328  * Bits | Access | Reset | Description
2329  * :-------|:-------|:------|:--------------------
2330  * [0] | R | 0x0 | ALT_SPIS_RISR_TXEIR
2331  * [1] | R | 0x0 | ALT_SPIS_RISR_TXOIR
2332  * [2] | R | 0x0 | ALT_SPIS_RISR_RXUIR
2333  * [3] | R | 0x0 | ALT_SPIS_RISR_RXOIR
2334  * [4] | R | 0x0 | ALT_SPIS_RISR_RXFIR
2335  * [31:5] | ??? | 0x0 | *UNDEFINED*
2336  *
2337  */
2338 /*
2339  * Field : txeir
2340  *
2341  * Transmit FIFO Empty Raw Interrupt Status
2342  *
2343  * 0 = ssi_txe_intr interrupt is not active prior to masking
2344  *
2345  * 1 = ssi_txe_intr interrupt is active prior masking
2346  *
2347  * Field Enumeration Values:
2348  *
2349  * Enum | Value | Description
2350  * :----------------------------|:------|:-----------------------------------------------
2351  * ALT_SPIS_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to
2352  * : | | masking
2353  * ALT_SPIS_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking
2354  *
2355  * Field Access Macros:
2356  *
2357  */
2358 /*
2359  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
2360  *
2361  * spi_txe_intr interrupt is not active prior to masking
2362  */
2363 #define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
2364 /*
2365  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
2366  *
2367  * spi_txe_intr interrupt is active prior masking
2368  */
2369 #define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
2370 
2371 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXEIR register field. */
2372 #define ALT_SPIS_RISR_TXEIR_LSB 0
2373 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXEIR register field. */
2374 #define ALT_SPIS_RISR_TXEIR_MSB 0
2375 /* The width in bits of the ALT_SPIS_RISR_TXEIR register field. */
2376 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
2377 /* The mask used to set the ALT_SPIS_RISR_TXEIR register field value. */
2378 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
2379 /* The mask used to clear the ALT_SPIS_RISR_TXEIR register field value. */
2380 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
2381 /* The reset value of the ALT_SPIS_RISR_TXEIR register field. */
2382 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
2383 /* Extracts the ALT_SPIS_RISR_TXEIR field value from a register. */
2384 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2385 /* Produces a ALT_SPIS_RISR_TXEIR register field value suitable for setting the register. */
2386 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2387 
2388 /*
2389  * Field : txoir
2390  *
2391  * Transmit FIFO Overflow Raw Interrupt Status
2392  *
2393  * 0 = ssi_txo_intr interrupt is not active prior to masking
2394  *
2395  * 1 = ssi_txo_intr interrupt is active prior masking
2396  *
2397  * Field Enumeration Values:
2398  *
2399  * Enum | Value | Description
2400  * :----------------------------|:------|:-----------------------------------------------
2401  * ALT_SPIS_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to
2402  * : | | masking
2403  * ALT_SPIS_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking
2404  *
2405  * Field Access Macros:
2406  *
2407  */
2408 /*
2409  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
2410  *
2411  * spi_txo_intr interrupt is not active prior to masking
2412  */
2413 #define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
2414 /*
2415  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
2416  *
2417  * spi_txo_intr interrupt is active prior masking
2418  */
2419 #define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
2420 
2421 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXOIR register field. */
2422 #define ALT_SPIS_RISR_TXOIR_LSB 1
2423 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXOIR register field. */
2424 #define ALT_SPIS_RISR_TXOIR_MSB 1
2425 /* The width in bits of the ALT_SPIS_RISR_TXOIR register field. */
2426 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
2427 /* The mask used to set the ALT_SPIS_RISR_TXOIR register field value. */
2428 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
2429 /* The mask used to clear the ALT_SPIS_RISR_TXOIR register field value. */
2430 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
2431 /* The reset value of the ALT_SPIS_RISR_TXOIR register field. */
2432 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
2433 /* Extracts the ALT_SPIS_RISR_TXOIR field value from a register. */
2434 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2435 /* Produces a ALT_SPIS_RISR_TXOIR register field value suitable for setting the register. */
2436 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2437 
2438 /*
2439  * Field : rxuir
2440  *
2441  * Receive FIFO Underflow Raw Interrupt Status
2442  *
2443  * 0 = ssi_rxu_intr interrupt is not active prior to masking
2444  *
2445  * 1 = ssi_rxu_intr interrupt is active prior to masking
2446  *
2447  * Field Enumeration Values:
2448  *
2449  * Enum | Value | Description
2450  * :----------------------------|:------|:----------------------------------------------
2451  * ALT_SPIS_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to
2452  * : | | masking
2453  * ALT_SPIS_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to
2454  * : | | masking
2455  *
2456  * Field Access Macros:
2457  *
2458  */
2459 /*
2460  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
2461  *
2462  * spi_rxu_intr interrupt is not active prior to masking
2463  */
2464 #define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2465 /*
2466  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
2467  *
2468  * spi_rxu_intr interrupt is active prior to masking
2469  */
2470 #define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2471 
2472 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXUIR register field. */
2473 #define ALT_SPIS_RISR_RXUIR_LSB 2
2474 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXUIR register field. */
2475 #define ALT_SPIS_RISR_RXUIR_MSB 2
2476 /* The width in bits of the ALT_SPIS_RISR_RXUIR register field. */
2477 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
2478 /* The mask used to set the ALT_SPIS_RISR_RXUIR register field value. */
2479 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2480 /* The mask used to clear the ALT_SPIS_RISR_RXUIR register field value. */
2481 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2482 /* The reset value of the ALT_SPIS_RISR_RXUIR register field. */
2483 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
2484 /* Extracts the ALT_SPIS_RISR_RXUIR field value from a register. */
2485 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2486 /* Produces a ALT_SPIS_RISR_RXUIR register field value suitable for setting the register. */
2487 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2488 
2489 /*
2490  * Field : rxoir
2491  *
2492  * Receive FIFO Overflow Raw Interrupt Status
2493  *
2494  * 0 = ssi_rxo_intr interrupt is not active prior to masking
2495  *
2496  * 1 = ssi_rxo_intr interrupt is active prior masking
2497  *
2498  * Field Enumeration Values:
2499  *
2500  * Enum | Value | Description
2501  * :----------------------------|:------|:-----------------------------------------------
2502  * ALT_SPIS_RISR_RXOIR_E_INACT | 0x0 | spi_rxo_intr interrupt is not active prior to
2503  * : | | masking
2504  * ALT_SPIS_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking
2505  *
2506  * Field Access Macros:
2507  *
2508  */
2509 /*
2510  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
2511  *
2512  * spi_rxo_intr interrupt is not active prior to masking
2513  */
2514 #define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2515 /*
2516  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
2517  *
2518  * spi_rxo_intr interrupt is active prior masking
2519  */
2520 #define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2521 
2522 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXOIR register field. */
2523 #define ALT_SPIS_RISR_RXOIR_LSB 3
2524 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXOIR register field. */
2525 #define ALT_SPIS_RISR_RXOIR_MSB 3
2526 /* The width in bits of the ALT_SPIS_RISR_RXOIR register field. */
2527 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
2528 /* The mask used to set the ALT_SPIS_RISR_RXOIR register field value. */
2529 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2530 /* The mask used to clear the ALT_SPIS_RISR_RXOIR register field value. */
2531 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2532 /* The reset value of the ALT_SPIS_RISR_RXOIR register field. */
2533 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
2534 /* Extracts the ALT_SPIS_RISR_RXOIR field value from a register. */
2535 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2536 /* Produces a ALT_SPIS_RISR_RXOIR register field value suitable for setting the register. */
2537 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2538 
2539 /*
2540  * Field : rxfir
2541  *
2542  * Receive FIFO Full Raw Interrupt Status
2543  *
2544  * 0 = ssi_rxf_intr interrupt is not active prior to masking
2545  *
2546  * 1 = ssi_rxf_intr interrupt is active prior to masking
2547  *
2548  * Field Enumeration Values:
2549  *
2550  * Enum | Value | Description
2551  * :----------------------------|:------|:----------------------------------------------
2552  * ALT_SPIS_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to
2553  * : | | masking
2554  * ALT_SPIS_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to
2555  * : | | masking
2556  *
2557  * Field Access Macros:
2558  *
2559  */
2560 /*
2561  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
2562  *
2563  * spi_rxf_intr interrupt is not active prior to masking
2564  */
2565 #define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2566 /*
2567  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
2568  *
2569  * spi_rxf_intr interrupt is active prior to masking
2570  */
2571 #define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2572 
2573 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXFIR register field. */
2574 #define ALT_SPIS_RISR_RXFIR_LSB 4
2575 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXFIR register field. */
2576 #define ALT_SPIS_RISR_RXFIR_MSB 4
2577 /* The width in bits of the ALT_SPIS_RISR_RXFIR register field. */
2578 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
2579 /* The mask used to set the ALT_SPIS_RISR_RXFIR register field value. */
2580 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2581 /* The mask used to clear the ALT_SPIS_RISR_RXFIR register field value. */
2582 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2583 /* The reset value of the ALT_SPIS_RISR_RXFIR register field. */
2584 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
2585 /* Extracts the ALT_SPIS_RISR_RXFIR field value from a register. */
2586 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2587 /* Produces a ALT_SPIS_RISR_RXFIR register field value suitable for setting the register. */
2588 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2589 
2590 #ifndef __ASSEMBLY__
2591 /*
2592  * WARNING: The C register and register group struct declarations are provided for
2593  * convenience and illustrative purposes. They should, however, be used with
2594  * caution as the C language standard provides no guarantees about the alignment or
2595  * atomicity of device memory accesses. The recommended practice for writing
2596  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2597  * alt_write_word() functions.
2598  *
2599  * The struct declaration for register ALT_SPIS_RISR.
2600  */
2601 struct ALT_SPIS_RISR_s
2602 {
2603  const uint32_t txeir : 1; /* ALT_SPIS_RISR_TXEIR */
2604  const uint32_t txoir : 1; /* ALT_SPIS_RISR_TXOIR */
2605  const uint32_t rxuir : 1; /* ALT_SPIS_RISR_RXUIR */
2606  const uint32_t rxoir : 1; /* ALT_SPIS_RISR_RXOIR */
2607  const uint32_t rxfir : 1; /* ALT_SPIS_RISR_RXFIR */
2608  uint32_t : 27; /* *UNDEFINED* */
2609 };
2610 
2611 /* The typedef declaration for register ALT_SPIS_RISR. */
2612 typedef volatile struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
2613 #endif /* __ASSEMBLY__ */
2614 
2615 /* The reset value of the ALT_SPIS_RISR register. */
2616 #define ALT_SPIS_RISR_RESET 0x00000000
2617 /* The byte offset of the ALT_SPIS_RISR register from the beginning of the component. */
2618 #define ALT_SPIS_RISR_OFST 0x34
2619 /* The address of the ALT_SPIS_RISR register. */
2620 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2621 
2622 /*
2623  * Register : txoicr
2624  *
2625  * Transmit FIFO Overflow Interrupt Clear Register
2626  *
2627  * Register Layout
2628  *
2629  * Bits | Access | Reset | Description
2630  * :-------|:-------|:------|:-----------------------
2631  * [0] | R | 0x0 | ALT_SPIS_TXOICR_TXOICR
2632  * [31:1] | ??? | 0x0 | *UNDEFINED*
2633  *
2634  */
2635 /*
2636  * Field : txoicr
2637  *
2638  * Clear Transmit FIFO Overflow Interrupt.
2639  *
2640  * This register reflects the status of the interrupt. A read from this
2641  *
2642  * register clears the ssi_txo_intr interrupt; writing has no effect.
2643  *
2644  * Field Access Macros:
2645  *
2646  */
2647 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
2648 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
2649 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
2650 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
2651 /* The width in bits of the ALT_SPIS_TXOICR_TXOICR register field. */
2652 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2653 /* The mask used to set the ALT_SPIS_TXOICR_TXOICR register field value. */
2654 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2655 /* The mask used to clear the ALT_SPIS_TXOICR_TXOICR register field value. */
2656 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2657 /* The reset value of the ALT_SPIS_TXOICR_TXOICR register field. */
2658 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2659 /* Extracts the ALT_SPIS_TXOICR_TXOICR field value from a register. */
2660 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2661 /* Produces a ALT_SPIS_TXOICR_TXOICR register field value suitable for setting the register. */
2662 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2663 
2664 #ifndef __ASSEMBLY__
2665 /*
2666  * WARNING: The C register and register group struct declarations are provided for
2667  * convenience and illustrative purposes. They should, however, be used with
2668  * caution as the C language standard provides no guarantees about the alignment or
2669  * atomicity of device memory accesses. The recommended practice for writing
2670  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2671  * alt_write_word() functions.
2672  *
2673  * The struct declaration for register ALT_SPIS_TXOICR.
2674  */
2675 struct ALT_SPIS_TXOICR_s
2676 {
2677  const uint32_t txoicr : 1; /* ALT_SPIS_TXOICR_TXOICR */
2678  uint32_t : 31; /* *UNDEFINED* */
2679 };
2680 
2681 /* The typedef declaration for register ALT_SPIS_TXOICR. */
2682 typedef volatile struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
2683 #endif /* __ASSEMBLY__ */
2684 
2685 /* The reset value of the ALT_SPIS_TXOICR register. */
2686 #define ALT_SPIS_TXOICR_RESET 0x00000000
2687 /* The byte offset of the ALT_SPIS_TXOICR register from the beginning of the component. */
2688 #define ALT_SPIS_TXOICR_OFST 0x38
2689 /* The address of the ALT_SPIS_TXOICR register. */
2690 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2691 
2692 /*
2693  * Register : rxoicr
2694  *
2695  * Receive FIFO Overflow Interrupt Clear Register
2696  *
2697  * Register Layout
2698  *
2699  * Bits | Access | Reset | Description
2700  * :-------|:-------|:------|:-----------------------
2701  * [0] | R | 0x0 | ALT_SPIS_RXOICR_RXOICR
2702  * [31:1] | ??? | 0x0 | *UNDEFINED*
2703  *
2704  */
2705 /*
2706  * Field : rxoicr
2707  *
2708  * Clear Receive FIFO Overflow Interrupt.
2709  *
2710  * This register reflects the status of the interrupt. A read from this
2711  *
2712  * register clears the ssi_rxo_intr interrupt; writing has no effect.
2713  *
2714  * Field Access Macros:
2715  *
2716  */
2717 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
2718 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
2719 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
2720 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
2721 /* The width in bits of the ALT_SPIS_RXOICR_RXOICR register field. */
2722 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2723 /* The mask used to set the ALT_SPIS_RXOICR_RXOICR register field value. */
2724 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2725 /* The mask used to clear the ALT_SPIS_RXOICR_RXOICR register field value. */
2726 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2727 /* The reset value of the ALT_SPIS_RXOICR_RXOICR register field. */
2728 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2729 /* Extracts the ALT_SPIS_RXOICR_RXOICR field value from a register. */
2730 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2731 /* Produces a ALT_SPIS_RXOICR_RXOICR register field value suitable for setting the register. */
2732 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2733 
2734 #ifndef __ASSEMBLY__
2735 /*
2736  * WARNING: The C register and register group struct declarations are provided for
2737  * convenience and illustrative purposes. They should, however, be used with
2738  * caution as the C language standard provides no guarantees about the alignment or
2739  * atomicity of device memory accesses. The recommended practice for writing
2740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2741  * alt_write_word() functions.
2742  *
2743  * The struct declaration for register ALT_SPIS_RXOICR.
2744  */
2745 struct ALT_SPIS_RXOICR_s
2746 {
2747  const uint32_t rxoicr : 1; /* ALT_SPIS_RXOICR_RXOICR */
2748  uint32_t : 31; /* *UNDEFINED* */
2749 };
2750 
2751 /* The typedef declaration for register ALT_SPIS_RXOICR. */
2752 typedef volatile struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
2753 #endif /* __ASSEMBLY__ */
2754 
2755 /* The reset value of the ALT_SPIS_RXOICR register. */
2756 #define ALT_SPIS_RXOICR_RESET 0x00000000
2757 /* The byte offset of the ALT_SPIS_RXOICR register from the beginning of the component. */
2758 #define ALT_SPIS_RXOICR_OFST 0x3c
2759 /* The address of the ALT_SPIS_RXOICR register. */
2760 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2761 
2762 /*
2763  * Register : rxuicr
2764  *
2765  * Receive FIFO Underflow Interrupt Clear Register
2766  *
2767  * Register Layout
2768  *
2769  * Bits | Access | Reset | Description
2770  * :-------|:-------|:------|:-----------------------
2771  * [0] | R | 0x0 | ALT_SPIS_RXUICR_RXUICR
2772  * [31:1] | ??? | 0x0 | *UNDEFINED*
2773  *
2774  */
2775 /*
2776  * Field : rxuicr
2777  *
2778  * Clear Receive FIFO Underflow Interrupt.
2779  *
2780  * This register reflects the status of the interrupt. A read from this
2781  *
2782  * register clears the ssi_rxu_intr interrupt; writing has no effect.
2783  *
2784  * Field Access Macros:
2785  *
2786  */
2787 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
2788 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
2789 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
2790 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
2791 /* The width in bits of the ALT_SPIS_RXUICR_RXUICR register field. */
2792 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2793 /* The mask used to set the ALT_SPIS_RXUICR_RXUICR register field value. */
2794 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2795 /* The mask used to clear the ALT_SPIS_RXUICR_RXUICR register field value. */
2796 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2797 /* The reset value of the ALT_SPIS_RXUICR_RXUICR register field. */
2798 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2799 /* Extracts the ALT_SPIS_RXUICR_RXUICR field value from a register. */
2800 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2801 /* Produces a ALT_SPIS_RXUICR_RXUICR register field value suitable for setting the register. */
2802 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2803 
2804 #ifndef __ASSEMBLY__
2805 /*
2806  * WARNING: The C register and register group struct declarations are provided for
2807  * convenience and illustrative purposes. They should, however, be used with
2808  * caution as the C language standard provides no guarantees about the alignment or
2809  * atomicity of device memory accesses. The recommended practice for writing
2810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2811  * alt_write_word() functions.
2812  *
2813  * The struct declaration for register ALT_SPIS_RXUICR.
2814  */
2815 struct ALT_SPIS_RXUICR_s
2816 {
2817  const uint32_t rxuicr : 1; /* ALT_SPIS_RXUICR_RXUICR */
2818  uint32_t : 31; /* *UNDEFINED* */
2819 };
2820 
2821 /* The typedef declaration for register ALT_SPIS_RXUICR. */
2822 typedef volatile struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
2823 #endif /* __ASSEMBLY__ */
2824 
2825 /* The reset value of the ALT_SPIS_RXUICR register. */
2826 #define ALT_SPIS_RXUICR_RESET 0x00000000
2827 /* The byte offset of the ALT_SPIS_RXUICR register from the beginning of the component. */
2828 #define ALT_SPIS_RXUICR_OFST 0x40
2829 /* The address of the ALT_SPIS_RXUICR register. */
2830 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2831 
2832 /*
2833  * Register : msticr
2834  *
2835  * Multi-Master Interrupt Clear Register
2836  *
2837  * Register Layout
2838  *
2839  * Bits | Access | Reset | Description
2840  * :-------|:-------|:------|:-----------------------
2841  * [0] | R | 0x0 | ALT_SPIS_MSTICR_MSTICR
2842  * [31:1] | ??? | 0x0 | *UNDEFINED*
2843  *
2844  */
2845 /*
2846  * Field : msticr
2847  *
2848  * Clear Multi-Master Contention Interrupt.
2849  *
2850  * This register reflects the status of the interrupt. A read from this
2851  *
2852  * register clears the ssi_mst_intr interrupt; writing has no effect.
2853  *
2854  * Field Access Macros:
2855  *
2856  */
2857 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MSTICR_MSTICR register field. */
2858 #define ALT_SPIS_MSTICR_MSTICR_LSB 0
2859 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MSTICR_MSTICR register field. */
2860 #define ALT_SPIS_MSTICR_MSTICR_MSB 0
2861 /* The width in bits of the ALT_SPIS_MSTICR_MSTICR register field. */
2862 #define ALT_SPIS_MSTICR_MSTICR_WIDTH 1
2863 /* The mask used to set the ALT_SPIS_MSTICR_MSTICR register field value. */
2864 #define ALT_SPIS_MSTICR_MSTICR_SET_MSK 0x00000001
2865 /* The mask used to clear the ALT_SPIS_MSTICR_MSTICR register field value. */
2866 #define ALT_SPIS_MSTICR_MSTICR_CLR_MSK 0xfffffffe
2867 /* The reset value of the ALT_SPIS_MSTICR_MSTICR register field. */
2868 #define ALT_SPIS_MSTICR_MSTICR_RESET 0x0
2869 /* Extracts the ALT_SPIS_MSTICR_MSTICR field value from a register. */
2870 #define ALT_SPIS_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
2871 /* Produces a ALT_SPIS_MSTICR_MSTICR register field value suitable for setting the register. */
2872 #define ALT_SPIS_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
2873 
2874 #ifndef __ASSEMBLY__
2875 /*
2876  * WARNING: The C register and register group struct declarations are provided for
2877  * convenience and illustrative purposes. They should, however, be used with
2878  * caution as the C language standard provides no guarantees about the alignment or
2879  * atomicity of device memory accesses. The recommended practice for writing
2880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2881  * alt_write_word() functions.
2882  *
2883  * The struct declaration for register ALT_SPIS_MSTICR.
2884  */
2885 struct ALT_SPIS_MSTICR_s
2886 {
2887  const uint32_t msticr : 1; /* ALT_SPIS_MSTICR_MSTICR */
2888  uint32_t : 31; /* *UNDEFINED* */
2889 };
2890 
2891 /* The typedef declaration for register ALT_SPIS_MSTICR. */
2892 typedef volatile struct ALT_SPIS_MSTICR_s ALT_SPIS_MSTICR_t;
2893 #endif /* __ASSEMBLY__ */
2894 
2895 /* The reset value of the ALT_SPIS_MSTICR register. */
2896 #define ALT_SPIS_MSTICR_RESET 0x00000000
2897 /* The byte offset of the ALT_SPIS_MSTICR register from the beginning of the component. */
2898 #define ALT_SPIS_MSTICR_OFST 0x44
2899 /* The address of the ALT_SPIS_MSTICR register. */
2900 #define ALT_SPIS_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MSTICR_OFST))
2901 
2902 /*
2903  * Register : icr
2904  *
2905  * Interrupt Clear Register
2906  *
2907  * Register Layout
2908  *
2909  * Bits | Access | Reset | Description
2910  * :-------|:-------|:------|:-----------------
2911  * [0] | R | 0x0 | ALT_SPIS_ICR_ICR
2912  * [31:1] | ??? | 0x0 | *UNDEFINED*
2913  *
2914  */
2915 /*
2916  * Field : icr
2917  *
2918  * Clear Interrupts.
2919  *
2920  * This register is set if any of the interrupts below are active. A read
2921  *
2922  * clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr
2923  *
2924  * interrupts. Writing to this register has no effect.
2925  *
2926  * Field Access Macros:
2927  *
2928  */
2929 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ICR_ICR register field. */
2930 #define ALT_SPIS_ICR_ICR_LSB 0
2931 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ICR_ICR register field. */
2932 #define ALT_SPIS_ICR_ICR_MSB 0
2933 /* The width in bits of the ALT_SPIS_ICR_ICR register field. */
2934 #define ALT_SPIS_ICR_ICR_WIDTH 1
2935 /* The mask used to set the ALT_SPIS_ICR_ICR register field value. */
2936 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2937 /* The mask used to clear the ALT_SPIS_ICR_ICR register field value. */
2938 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2939 /* The reset value of the ALT_SPIS_ICR_ICR register field. */
2940 #define ALT_SPIS_ICR_ICR_RESET 0x0
2941 /* Extracts the ALT_SPIS_ICR_ICR field value from a register. */
2942 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2943 /* Produces a ALT_SPIS_ICR_ICR register field value suitable for setting the register. */
2944 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2945 
2946 #ifndef __ASSEMBLY__
2947 /*
2948  * WARNING: The C register and register group struct declarations are provided for
2949  * convenience and illustrative purposes. They should, however, be used with
2950  * caution as the C language standard provides no guarantees about the alignment or
2951  * atomicity of device memory accesses. The recommended practice for writing
2952  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2953  * alt_write_word() functions.
2954  *
2955  * The struct declaration for register ALT_SPIS_ICR.
2956  */
2957 struct ALT_SPIS_ICR_s
2958 {
2959  const uint32_t icr : 1; /* ALT_SPIS_ICR_ICR */
2960  uint32_t : 31; /* *UNDEFINED* */
2961 };
2962 
2963 /* The typedef declaration for register ALT_SPIS_ICR. */
2964 typedef volatile struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
2965 #endif /* __ASSEMBLY__ */
2966 
2967 /* The reset value of the ALT_SPIS_ICR register. */
2968 #define ALT_SPIS_ICR_RESET 0x00000000
2969 /* The byte offset of the ALT_SPIS_ICR register from the beginning of the component. */
2970 #define ALT_SPIS_ICR_OFST 0x48
2971 /* The address of the ALT_SPIS_ICR register. */
2972 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
2973 
2974 /*
2975  * Register : dmacr
2976  *
2977  * DMA Control Register.
2978  *
2979  * This register is only valid when DW_apb_ssi is configured with a set of
2980  *
2981  * DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
2982  *
2983  * not configured for DMA operation, this register will not exist and writing
2984  *
2985  * to the register's address will have no effect; reading from this register
2986  *
2987  * address will return zero. The register is used to enable the DMA
2988  *
2989  * Controller interface operation.
2990  *
2991  * Register Layout
2992  *
2993  * Bits | Access | Reset | Description
2994  * :-------|:-------|:------|:---------------------
2995  * [0] | RW | 0x0 | ALT_SPIS_DMACR_RDMAE
2996  * [1] | RW | 0x0 | ALT_SPIS_DMACR_TDMAE
2997  * [31:2] | ??? | 0x0 | *UNDEFINED*
2998  *
2999  */
3000 /*
3001  * Field : rdmae
3002  *
3003  * Receive DMA Enable.
3004  *
3005  * This bit enables/disables the receive FIFO DMA channel
3006  *
3007  * 0 = Receive DMA disabled
3008  *
3009  * 1 = Receive DMA enabled
3010  *
3011  * Field Enumeration Values:
3012  *
3013  * Enum | Value | Description
3014  * :----------------------------|:------|:---------------------
3015  * ALT_SPIS_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled
3016  * ALT_SPIS_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled
3017  *
3018  * Field Access Macros:
3019  *
3020  */
3021 /*
3022  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
3023  *
3024  * Receive DMA disabled
3025  */
3026 #define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
3027 /*
3028  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
3029  *
3030  * Receive DMA enabled
3031  */
3032 #define ALT_SPIS_DMACR_RDMAE_E_END 0x1
3033 
3034 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
3035 #define ALT_SPIS_DMACR_RDMAE_LSB 0
3036 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
3037 #define ALT_SPIS_DMACR_RDMAE_MSB 0
3038 /* The width in bits of the ALT_SPIS_DMACR_RDMAE register field. */
3039 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
3040 /* The mask used to set the ALT_SPIS_DMACR_RDMAE register field value. */
3041 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
3042 /* The mask used to clear the ALT_SPIS_DMACR_RDMAE register field value. */
3043 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
3044 /* The reset value of the ALT_SPIS_DMACR_RDMAE register field. */
3045 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
3046 /* Extracts the ALT_SPIS_DMACR_RDMAE field value from a register. */
3047 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3048 /* Produces a ALT_SPIS_DMACR_RDMAE register field value suitable for setting the register. */
3049 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3050 
3051 /*
3052  * Field : tdmae
3053  *
3054  * Transmit DMA Enable.
3055  *
3056  * This bit enables/disables the transmit FIFO DMA channel.
3057  *
3058  * 0 = Transmit DMA disabled
3059  *
3060  * 1 = Transmit DMA enabled
3061  *
3062  * Field Enumeration Values:
3063  *
3064  * Enum | Value | Description
3065  * :----------------------------|:------|:----------------------
3066  * ALT_SPIS_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled
3067  * ALT_SPIS_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled
3068  *
3069  * Field Access Macros:
3070  *
3071  */
3072 /*
3073  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
3074  *
3075  * Transmit DMA disabled
3076  */
3077 #define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
3078 /*
3079  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
3080  *
3081  * Transmit DMA enabled
3082  */
3083 #define ALT_SPIS_DMACR_TDMAE_E_END 0x1
3084 
3085 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
3086 #define ALT_SPIS_DMACR_TDMAE_LSB 1
3087 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
3088 #define ALT_SPIS_DMACR_TDMAE_MSB 1
3089 /* The width in bits of the ALT_SPIS_DMACR_TDMAE register field. */
3090 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
3091 /* The mask used to set the ALT_SPIS_DMACR_TDMAE register field value. */
3092 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
3093 /* The mask used to clear the ALT_SPIS_DMACR_TDMAE register field value. */
3094 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
3095 /* The reset value of the ALT_SPIS_DMACR_TDMAE register field. */
3096 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
3097 /* Extracts the ALT_SPIS_DMACR_TDMAE field value from a register. */
3098 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3099 /* Produces a ALT_SPIS_DMACR_TDMAE register field value suitable for setting the register. */
3100 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3101 
3102 #ifndef __ASSEMBLY__
3103 /*
3104  * WARNING: The C register and register group struct declarations are provided for
3105  * convenience and illustrative purposes. They should, however, be used with
3106  * caution as the C language standard provides no guarantees about the alignment or
3107  * atomicity of device memory accesses. The recommended practice for writing
3108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3109  * alt_write_word() functions.
3110  *
3111  * The struct declaration for register ALT_SPIS_DMACR.
3112  */
3113 struct ALT_SPIS_DMACR_s
3114 {
3115  uint32_t rdmae : 1; /* ALT_SPIS_DMACR_RDMAE */
3116  uint32_t tdmae : 1; /* ALT_SPIS_DMACR_TDMAE */
3117  uint32_t : 30; /* *UNDEFINED* */
3118 };
3119 
3120 /* The typedef declaration for register ALT_SPIS_DMACR. */
3121 typedef volatile struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
3122 #endif /* __ASSEMBLY__ */
3123 
3124 /* The reset value of the ALT_SPIS_DMACR register. */
3125 #define ALT_SPIS_DMACR_RESET 0x00000000
3126 /* The byte offset of the ALT_SPIS_DMACR register from the beginning of the component. */
3127 #define ALT_SPIS_DMACR_OFST 0x4c
3128 /* The address of the ALT_SPIS_DMACR register. */
3129 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
3130 
3131 /*
3132  * Register : dmatdlr
3133  *
3134  * DMA Transmit Data Level.
3135  *
3136  * This register is only valid when the DW_apb_ssi is configured with a set
3137  *
3138  * of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
3139  *
3140  * configured for DMA operation, this register will not exist and writing
3141  *
3142  * to its address will have no effect; reading from its address will
3143  *
3144  * return zero.
3145  *
3146  * Register Layout
3147  *
3148  * Bits | Access | Reset | Description
3149  * :-------|:-------|:------|:------------------------
3150  * [7:0] | RW | 0x0 | ALT_SPIS_DMATDLR_DMATDL
3151  * [31:8] | ??? | 0x0 | *UNDEFINED*
3152  *
3153  */
3154 /*
3155  * Field : dmatdl
3156  *
3157  * Transmit Data Level.
3158  *
3159  * This bit field controls the level at which a DMA request is made by the
3160  *
3161  * transmit logic. It is equal to the watermark level; that is, the
3162  *
3163  * dma_tx_req signal is generated when the number of valid data entries
3164  *
3165  * in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
3166  *
3167  * Field Access Macros:
3168  *
3169  */
3170 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
3171 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
3172 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
3173 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
3174 /* The width in bits of the ALT_SPIS_DMATDLR_DMATDL register field. */
3175 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
3176 /* The mask used to set the ALT_SPIS_DMATDLR_DMATDL register field value. */
3177 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
3178 /* The mask used to clear the ALT_SPIS_DMATDLR_DMATDL register field value. */
3179 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
3180 /* The reset value of the ALT_SPIS_DMATDLR_DMATDL register field. */
3181 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
3182 /* Extracts the ALT_SPIS_DMATDLR_DMATDL field value from a register. */
3183 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
3184 /* Produces a ALT_SPIS_DMATDLR_DMATDL register field value suitable for setting the register. */
3185 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
3186 
3187 #ifndef __ASSEMBLY__
3188 /*
3189  * WARNING: The C register and register group struct declarations are provided for
3190  * convenience and illustrative purposes. They should, however, be used with
3191  * caution as the C language standard provides no guarantees about the alignment or
3192  * atomicity of device memory accesses. The recommended practice for writing
3193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3194  * alt_write_word() functions.
3195  *
3196  * The struct declaration for register ALT_SPIS_DMATDLR.
3197  */
3198 struct ALT_SPIS_DMATDLR_s
3199 {
3200  uint32_t dmatdl : 8; /* ALT_SPIS_DMATDLR_DMATDL */
3201  uint32_t : 24; /* *UNDEFINED* */
3202 };
3203 
3204 /* The typedef declaration for register ALT_SPIS_DMATDLR. */
3205 typedef volatile struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
3206 #endif /* __ASSEMBLY__ */
3207 
3208 /* The reset value of the ALT_SPIS_DMATDLR register. */
3209 #define ALT_SPIS_DMATDLR_RESET 0x00000000
3210 /* The byte offset of the ALT_SPIS_DMATDLR register from the beginning of the component. */
3211 #define ALT_SPIS_DMATDLR_OFST 0x50
3212 /* The address of the ALT_SPIS_DMATDLR register. */
3213 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
3214 
3215 /*
3216  * Register : dmardlr
3217  *
3218  * DMA Receive Data Level.
3219  *
3220  * This register is only valid when DW_apb_ssi is configured with a set of
3221  *
3222  * DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
3223  *
3224  * for DMA operation, this register will not exist and writing to its address
3225  *
3226  * will have no effect; reading from its address will return zero.
3227  *
3228  * Register Layout
3229  *
3230  * Bits | Access | Reset | Description
3231  * :-------|:-------|:------|:------------------------
3232  * [7:0] | RW | 0x0 | ALT_SPIS_DMARDLR_DMARDL
3233  * [31:8] | ??? | 0x0 | *UNDEFINED*
3234  *
3235  */
3236 /*
3237  * Field : dmardl
3238  *
3239  * Receive Data Level.
3240  *
3241  * This bit field controls the level at which a DMA request is made by the
3242  *
3243  * receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
3244  *
3245  * generated when the number of valid data entries in the receive FIFO is
3246  *
3247  * equal to or above this field value + 1, and RDMAE=1.
3248  *
3249  * Field Access Macros:
3250  *
3251  */
3252 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
3253 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
3254 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
3255 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
3256 /* The width in bits of the ALT_SPIS_DMARDLR_DMARDL register field. */
3257 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
3258 /* The mask used to set the ALT_SPIS_DMARDLR_DMARDL register field value. */
3259 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
3260 /* The mask used to clear the ALT_SPIS_DMARDLR_DMARDL register field value. */
3261 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
3262 /* The reset value of the ALT_SPIS_DMARDLR_DMARDL register field. */
3263 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
3264 /* Extracts the ALT_SPIS_DMARDLR_DMARDL field value from a register. */
3265 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
3266 /* Produces a ALT_SPIS_DMARDLR_DMARDL register field value suitable for setting the register. */
3267 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
3268 
3269 #ifndef __ASSEMBLY__
3270 /*
3271  * WARNING: The C register and register group struct declarations are provided for
3272  * convenience and illustrative purposes. They should, however, be used with
3273  * caution as the C language standard provides no guarantees about the alignment or
3274  * atomicity of device memory accesses. The recommended practice for writing
3275  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3276  * alt_write_word() functions.
3277  *
3278  * The struct declaration for register ALT_SPIS_DMARDLR.
3279  */
3280 struct ALT_SPIS_DMARDLR_s
3281 {
3282  uint32_t dmardl : 8; /* ALT_SPIS_DMARDLR_DMARDL */
3283  uint32_t : 24; /* *UNDEFINED* */
3284 };
3285 
3286 /* The typedef declaration for register ALT_SPIS_DMARDLR. */
3287 typedef volatile struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
3288 #endif /* __ASSEMBLY__ */
3289 
3290 /* The reset value of the ALT_SPIS_DMARDLR register. */
3291 #define ALT_SPIS_DMARDLR_RESET 0x00000000
3292 /* The byte offset of the ALT_SPIS_DMARDLR register from the beginning of the component. */
3293 #define ALT_SPIS_DMARDLR_OFST 0x54
3294 /* The address of the ALT_SPIS_DMARDLR register. */
3295 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
3296 
3297 /*
3298  * Register : idr
3299  *
3300  * Identification Register.
3301  *
3302  * This register contains the peripherals identification code, which is
3303  *
3304  * written into the register at configuration time using coreConsultant.
3305  *
3306  * Register Layout
3307  *
3308  * Bits | Access | Reset | Description
3309  * :-------|:-------|:----------|:--------------------
3310  * [31:0] | R | 0x5510005 | Identification Code
3311  *
3312  */
3313 /*
3314  * Field : Identification Code - idr
3315  *
3316  * This filed contains the peripherals identification code, 0x05510005.
3317  *
3318  * Field Access Macros:
3319  *
3320  */
3321 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IDR_IDR register field. */
3322 #define ALT_SPIS_IDR_IDR_LSB 0
3323 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IDR_IDR register field. */
3324 #define ALT_SPIS_IDR_IDR_MSB 31
3325 /* The width in bits of the ALT_SPIS_IDR_IDR register field. */
3326 #define ALT_SPIS_IDR_IDR_WIDTH 32
3327 /* The mask used to set the ALT_SPIS_IDR_IDR register field value. */
3328 #define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
3329 /* The mask used to clear the ALT_SPIS_IDR_IDR register field value. */
3330 #define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
3331 /* The reset value of the ALT_SPIS_IDR_IDR register field. */
3332 #define ALT_SPIS_IDR_IDR_RESET 0x5510005
3333 /* Extracts the ALT_SPIS_IDR_IDR field value from a register. */
3334 #define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
3335 /* Produces a ALT_SPIS_IDR_IDR register field value suitable for setting the register. */
3336 #define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
3337 
3338 #ifndef __ASSEMBLY__
3339 /*
3340  * WARNING: The C register and register group struct declarations are provided for
3341  * convenience and illustrative purposes. They should, however, be used with
3342  * caution as the C language standard provides no guarantees about the alignment or
3343  * atomicity of device memory accesses. The recommended practice for writing
3344  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3345  * alt_write_word() functions.
3346  *
3347  * The struct declaration for register ALT_SPIS_IDR.
3348  */
3349 struct ALT_SPIS_IDR_s
3350 {
3351  const uint32_t idr : 32; /* Identification Code */
3352 };
3353 
3354 /* The typedef declaration for register ALT_SPIS_IDR. */
3355 typedef volatile struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
3356 #endif /* __ASSEMBLY__ */
3357 
3358 /* The reset value of the ALT_SPIS_IDR register. */
3359 #define ALT_SPIS_IDR_RESET 0x05510005
3360 /* The byte offset of the ALT_SPIS_IDR register from the beginning of the component. */
3361 #define ALT_SPIS_IDR_OFST 0x58
3362 /* The address of the ALT_SPIS_IDR register. */
3363 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
3364 
3365 /*
3366  * Register : spi_version_id
3367  *
3368  * coreKit Version ID Register
3369  *
3370  * Register Layout
3371  *
3372  * Bits | Access | Reset | Description
3373  * :-------|:-------|:-----------|:------------------
3374  * [31:0] | RW | 0x3332322a | Component Version
3375  *
3376  */
3377 /*
3378  * Field : Component Version - spi_version_id
3379  *
3380  * Contains the hex representation of the Synopsys component version. Consists of
3381  * ASCII value for each number in the version.
3382  *
3383  * Field Access Macros:
3384  *
3385  */
3386 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
3387 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
3388 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
3389 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
3390 /* The width in bits of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
3391 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3392 /* The mask used to set the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */
3393 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3394 /* The mask used to clear the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value. */
3395 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3396 /* The reset value of the ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field. */
3397 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332322a
3398 /* Extracts the ALT_SPIS_SPI_VER_ID_SPI_VER_ID field value from a register. */
3399 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3400 /* Produces a ALT_SPIS_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */
3401 #define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3402 
3403 #ifndef __ASSEMBLY__
3404 /*
3405  * WARNING: The C register and register group struct declarations are provided for
3406  * convenience and illustrative purposes. They should, however, be used with
3407  * caution as the C language standard provides no guarantees about the alignment or
3408  * atomicity of device memory accesses. The recommended practice for writing
3409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3410  * alt_write_word() functions.
3411  *
3412  * The struct declaration for register ALT_SPIS_SPI_VER_ID.
3413  */
3414 struct ALT_SPIS_SPI_VER_ID_s
3415 {
3416  uint32_t spi_version_id : 32; /* Component Version */
3417 };
3418 
3419 /* The typedef declaration for register ALT_SPIS_SPI_VER_ID. */
3420 typedef volatile struct ALT_SPIS_SPI_VER_ID_s ALT_SPIS_SPI_VER_ID_t;
3421 #endif /* __ASSEMBLY__ */
3422 
3423 /* The reset value of the ALT_SPIS_SPI_VER_ID register. */
3424 #define ALT_SPIS_SPI_VER_ID_RESET 0x3332322a
3425 /* The byte offset of the ALT_SPIS_SPI_VER_ID register from the beginning of the component. */
3426 #define ALT_SPIS_SPI_VER_ID_OFST 0x5c
3427 /* The address of the ALT_SPIS_SPI_VER_ID register. */
3428 #define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
3429 
3430 /*
3431  * Register : dr
3432  *
3433  * The DW_apb_ssi data register is a 16-bit read/write buffer for the
3434  *
3435  * transmit/receive FIFOs. When the register is read, data in the receive
3436  *
3437  * FIFO buffer is accessed. When it is written to, data are moved into the
3438  *
3439  * transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are
3440  *
3441  * reset when SSI_EN = 0.
3442  *
3443  * Register Layout
3444  *
3445  * Bits | Access | Reset | Description
3446  * :--------|:-------|:------|:---------------
3447  * [15:0] | RW | 0x0 | ALT_SPIS_DR_DR
3448  * [31:16] | ??? | 0x0 | *UNDEFINED*
3449  *
3450  */
3451 /*
3452  * Field : dr
3453  *
3454  * Data Register.
3455  *
3456  * When writing to this register, you must right-justify the data. Read
3457  *
3458  * data are automatically right-justified.
3459  *
3460  * Read = Receive FIFO buffer
3461  *
3462  * Write = Transmit FIFO buffer
3463  *
3464  * Field Access Macros:
3465  *
3466  */
3467 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR_DR register field. */
3468 #define ALT_SPIS_DR_DR_LSB 0
3469 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR_DR register field. */
3470 #define ALT_SPIS_DR_DR_MSB 15
3471 /* The width in bits of the ALT_SPIS_DR_DR register field. */
3472 #define ALT_SPIS_DR_DR_WIDTH 16
3473 /* The mask used to set the ALT_SPIS_DR_DR register field value. */
3474 #define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
3475 /* The mask used to clear the ALT_SPIS_DR_DR register field value. */
3476 #define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
3477 /* The reset value of the ALT_SPIS_DR_DR register field. */
3478 #define ALT_SPIS_DR_DR_RESET 0x0
3479 /* Extracts the ALT_SPIS_DR_DR field value from a register. */
3480 #define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3481 /* Produces a ALT_SPIS_DR_DR register field value suitable for setting the register. */
3482 #define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3483 
3484 #ifndef __ASSEMBLY__
3485 /*
3486  * WARNING: The C register and register group struct declarations are provided for
3487  * convenience and illustrative purposes. They should, however, be used with
3488  * caution as the C language standard provides no guarantees about the alignment or
3489  * atomicity of device memory accesses. The recommended practice for writing
3490  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3491  * alt_write_word() functions.
3492  *
3493  * The struct declaration for register ALT_SPIS_DR.
3494  */
3495 struct ALT_SPIS_DR_s
3496 {
3497  uint32_t dr : 16; /* ALT_SPIS_DR_DR */
3498  uint32_t : 16; /* *UNDEFINED* */
3499 };
3500 
3501 /* The typedef declaration for register ALT_SPIS_DR. */
3502 typedef volatile struct ALT_SPIS_DR_s ALT_SPIS_DR_t;
3503 #endif /* __ASSEMBLY__ */
3504 
3505 /* The reset value of the ALT_SPIS_DR register. */
3506 #define ALT_SPIS_DR_RESET 0x00000000
3507 /* The byte offset of the ALT_SPIS_DR register from the beginning of the component. */
3508 #define ALT_SPIS_DR_OFST 0x60
3509 /* The address of the ALT_SPIS_DR register. */
3510 #define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
3511 
3512 #ifndef __ASSEMBLY__
3513 /*
3514  * WARNING: The C register and register group struct declarations are provided for
3515  * convenience and illustrative purposes. They should, however, be used with
3516  * caution as the C language standard provides no guarantees about the alignment or
3517  * atomicity of device memory accesses. The recommended practice for writing
3518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3519  * alt_write_word() functions.
3520  *
3521  * The struct declaration for register group ALT_SPIS.
3522  */
3523 struct ALT_SPIS_s
3524 {
3525  ALT_SPIS_CTLR0_t ctrlr0; /* ALT_SPIS_CTLR0 */
3526  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
3527  ALT_SPIS_SPIENR_t spienr; /* ALT_SPIS_SPIENR */
3528  ALT_SPIS_MWCR_t mwcr; /* ALT_SPIS_MWCR */
3529  volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
3530  ALT_SPIS_TXFTLR_t txftlr; /* ALT_SPIS_TXFTLR */
3531  ALT_SPIS_RXFTLR_t rxftlr; /* ALT_SPIS_RXFTLR */
3532  ALT_SPIS_TXFLR_t txflr; /* ALT_SPIS_TXFLR */
3533  ALT_SPIS_RXFLR_t rxflr; /* ALT_SPIS_RXFLR */
3534  ALT_SPIS_SR_t sr; /* ALT_SPIS_SR */
3535  ALT_SPIS_IMR_t imr; /* ALT_SPIS_IMR */
3536  ALT_SPIS_ISR_t isr; /* ALT_SPIS_ISR */
3537  ALT_SPIS_RISR_t risr; /* ALT_SPIS_RISR */
3538  ALT_SPIS_TXOICR_t txoicr; /* ALT_SPIS_TXOICR */
3539  ALT_SPIS_RXOICR_t rxoicr; /* ALT_SPIS_RXOICR */
3540  ALT_SPIS_RXUICR_t rxuicr; /* ALT_SPIS_RXUICR */
3541  ALT_SPIS_MSTICR_t msticr; /* ALT_SPIS_MSTICR */
3542  ALT_SPIS_ICR_t icr; /* ALT_SPIS_ICR */
3543  ALT_SPIS_DMACR_t dmacr; /* ALT_SPIS_DMACR */
3544  ALT_SPIS_DMATDLR_t dmatdlr; /* ALT_SPIS_DMATDLR */
3545  ALT_SPIS_DMARDLR_t dmardlr; /* ALT_SPIS_DMARDLR */
3546  ALT_SPIS_IDR_t idr; /* ALT_SPIS_IDR */
3547  ALT_SPIS_SPI_VER_ID_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */
3548  ALT_SPIS_DR_t dr; /* ALT_SPIS_DR */
3549  volatile uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */
3550 };
3551 
3552 /* The typedef declaration for register group ALT_SPIS. */
3553 typedef volatile struct ALT_SPIS_s ALT_SPIS_t;
3554 /* The struct declaration for the raw register contents of register group ALT_SPIS. */
3555 struct ALT_SPIS_raw_s
3556 {
3557  volatile uint32_t ctrlr0; /* ALT_SPIS_CTLR0 */
3558  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
3559  volatile uint32_t spienr; /* ALT_SPIS_SPIENR */
3560  volatile uint32_t mwcr; /* ALT_SPIS_MWCR */
3561  uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
3562  volatile uint32_t txftlr; /* ALT_SPIS_TXFTLR */
3563  volatile uint32_t rxftlr; /* ALT_SPIS_RXFTLR */
3564  volatile uint32_t txflr; /* ALT_SPIS_TXFLR */
3565  volatile uint32_t rxflr; /* ALT_SPIS_RXFLR */
3566  volatile uint32_t sr; /* ALT_SPIS_SR */
3567  volatile uint32_t imr; /* ALT_SPIS_IMR */
3568  volatile uint32_t isr; /* ALT_SPIS_ISR */
3569  volatile uint32_t risr; /* ALT_SPIS_RISR */
3570  volatile uint32_t txoicr; /* ALT_SPIS_TXOICR */
3571  volatile uint32_t rxoicr; /* ALT_SPIS_RXOICR */
3572  volatile uint32_t rxuicr; /* ALT_SPIS_RXUICR */
3573  volatile uint32_t msticr; /* ALT_SPIS_MSTICR */
3574  volatile uint32_t icr; /* ALT_SPIS_ICR */
3575  volatile uint32_t dmacr; /* ALT_SPIS_DMACR */
3576  volatile uint32_t dmatdlr; /* ALT_SPIS_DMATDLR */
3577  volatile uint32_t dmardlr; /* ALT_SPIS_DMARDLR */
3578  volatile uint32_t idr; /* ALT_SPIS_IDR */
3579  volatile uint32_t spi_version_id; /* ALT_SPIS_SPI_VER_ID */
3580  volatile uint32_t dr; /* ALT_SPIS_DR */
3581  uint32_t _pad_0x64_0x80[7]; /* *UNDEFINED* */
3582 };
3583 
3584 /* The typedef declaration for the raw register contents of register group ALT_SPIS. */
3585 typedef volatile struct ALT_SPIS_raw_s ALT_SPIS_raw_t;
3586 #endif /* __ASSEMBLY__ */
3587 
3588 
3589 #ifdef __cplusplus
3590 }
3591 #endif /* __cplusplus */
3592 #endif /* __ALT_SOCAL_SPIS_H__ */
3593