Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
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alt_rstmgr.h
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32 
33 /* Altera - ALT_RSTMGR */
34 
35 #ifndef __ALT_SOCAL_RSTMGR_H__
36 #define __ALT_SOCAL_RSTMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Reset Manager Module - RSTMGR
50  * Reset Manager Module
51  *
52  * Registers in the Reset Manager module
53  *
54  */
55 /*
56  * Register : Reset Status Register - stat
57  *
58  * The "stat" register contains bits that indicate the reset source. A field is 1
59  * if its associated reset requester caused the reset.
60  *
61  * Software clears bits by writing them with a value of 1. Writes to bits with a
62  * value of 0 are ignored.
63  *
64  * After a cold reset is complete, all bits are reset to their reset value, except
65  * the sdmcoldrst, debugrst, csdaprst and sdmporlastrst bits. sdmcoldrst, debugrst,
66  * csdaprst and sdmporlastrst are reset to their reset value on POR.
67  *
68  * Register Layout
69  *
70  * Bits | Access | Reset | Description
71  * :--------|:-------|:------|:-------------------
72  * [0] | RW | 0x0 | SDM Cold Reset
73  * [1] | RW | 0x0 | SDM Warm Reset
74  * [2] | RW | 0x1 | SDM Last POR Reset
75  * [7:3] | ??? | 0x0 | *UNDEFINED*
76  * [8] | RW | 0x0 | mpu0rst
77  * [9] | RW | 0x0 | mpu1rst
78  * [10] | RW | 0x0 | mpu2rst
79  * [11] | RW | 0x0 | mpu3rst
80  * [15:12] | ??? | 0x0 | *UNDEFINED*
81  * [16] | RW | 0x0 | l4wd0rst
82  * [17] | RW | 0x0 | l4wd1rst
83  * [18] | RW | 0x0 | l4wd2rst
84  * [19] | RW | 0x0 | l4wd3rst
85  * [23:20] | ??? | 0x0 | *UNDEFINED*
86  * [24] | RW | 0x0 | debugrst
87  * [25] | RW | 0x0 | csdaprst
88  * [31:26] | ??? | 0x0 | *UNDEFINED*
89  *
90  */
91 /*
92  * Field : SDM Cold Reset - sdmcoldrst
93  *
94  * SDM triggered cold reset. This bit is reset to its reset value on POR, not on
95  * warm or cold reset.
96  *
97  * Field Access Macros:
98  *
99  */
100 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDMCOLDRST register field. */
101 #define ALT_RSTMGR_STAT_SDMCOLDRST_LSB 0
102 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDMCOLDRST register field. */
103 #define ALT_RSTMGR_STAT_SDMCOLDRST_MSB 0
104 /* The width in bits of the ALT_RSTMGR_STAT_SDMCOLDRST register field. */
105 #define ALT_RSTMGR_STAT_SDMCOLDRST_WIDTH 1
106 /* The mask used to set the ALT_RSTMGR_STAT_SDMCOLDRST register field value. */
107 #define ALT_RSTMGR_STAT_SDMCOLDRST_SET_MSK 0x00000001
108 /* The mask used to clear the ALT_RSTMGR_STAT_SDMCOLDRST register field value. */
109 #define ALT_RSTMGR_STAT_SDMCOLDRST_CLR_MSK 0xfffffffe
110 /* The reset value of the ALT_RSTMGR_STAT_SDMCOLDRST register field. */
111 #define ALT_RSTMGR_STAT_SDMCOLDRST_RESET 0x0
112 /* Extracts the ALT_RSTMGR_STAT_SDMCOLDRST field value from a register. */
113 #define ALT_RSTMGR_STAT_SDMCOLDRST_GET(value) (((value) & 0x00000001) >> 0)
114 /* Produces a ALT_RSTMGR_STAT_SDMCOLDRST register field value suitable for setting the register. */
115 #define ALT_RSTMGR_STAT_SDMCOLDRST_SET(value) (((value) << 0) & 0x00000001)
116 
117 /*
118  * Field : SDM Warm Reset - sdmwarmrst
119  *
120  * SDM triggered warm reset.
121  *
122  * Field Access Macros:
123  *
124  */
125 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDMWARMRST register field. */
126 #define ALT_RSTMGR_STAT_SDMWARMRST_LSB 1
127 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDMWARMRST register field. */
128 #define ALT_RSTMGR_STAT_SDMWARMRST_MSB 1
129 /* The width in bits of the ALT_RSTMGR_STAT_SDMWARMRST register field. */
130 #define ALT_RSTMGR_STAT_SDMWARMRST_WIDTH 1
131 /* The mask used to set the ALT_RSTMGR_STAT_SDMWARMRST register field value. */
132 #define ALT_RSTMGR_STAT_SDMWARMRST_SET_MSK 0x00000002
133 /* The mask used to clear the ALT_RSTMGR_STAT_SDMWARMRST register field value. */
134 #define ALT_RSTMGR_STAT_SDMWARMRST_CLR_MSK 0xfffffffd
135 /* The reset value of the ALT_RSTMGR_STAT_SDMWARMRST register field. */
136 #define ALT_RSTMGR_STAT_SDMWARMRST_RESET 0x0
137 /* Extracts the ALT_RSTMGR_STAT_SDMWARMRST field value from a register. */
138 #define ALT_RSTMGR_STAT_SDMWARMRST_GET(value) (((value) & 0x00000002) >> 1)
139 /* Produces a ALT_RSTMGR_STAT_SDMWARMRST register field value suitable for setting the register. */
140 #define ALT_RSTMGR_STAT_SDMWARMRST_SET(value) (((value) << 1) & 0x00000002)
141 
142 /*
143  * Field : SDM Last POR Reset - sdmlastporrst
144  *
145  * SDM triggered last por reset. This bit is reset to its reset value on POR, not
146  * on warm or cold reset.
147  *
148  * Field Access Macros:
149  *
150  */
151 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDMLASTPORRST register field. */
152 #define ALT_RSTMGR_STAT_SDMLASTPORRST_LSB 2
153 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDMLASTPORRST register field. */
154 #define ALT_RSTMGR_STAT_SDMLASTPORRST_MSB 2
155 /* The width in bits of the ALT_RSTMGR_STAT_SDMLASTPORRST register field. */
156 #define ALT_RSTMGR_STAT_SDMLASTPORRST_WIDTH 1
157 /* The mask used to set the ALT_RSTMGR_STAT_SDMLASTPORRST register field value. */
158 #define ALT_RSTMGR_STAT_SDMLASTPORRST_SET_MSK 0x00000004
159 /* The mask used to clear the ALT_RSTMGR_STAT_SDMLASTPORRST register field value. */
160 #define ALT_RSTMGR_STAT_SDMLASTPORRST_CLR_MSK 0xfffffffb
161 /* The reset value of the ALT_RSTMGR_STAT_SDMLASTPORRST register field. */
162 #define ALT_RSTMGR_STAT_SDMLASTPORRST_RESET 0x1
163 /* Extracts the ALT_RSTMGR_STAT_SDMLASTPORRST field value from a register. */
164 #define ALT_RSTMGR_STAT_SDMLASTPORRST_GET(value) (((value) & 0x00000004) >> 2)
165 /* Produces a ALT_RSTMGR_STAT_SDMLASTPORRST register field value suitable for setting the register. */
166 #define ALT_RSTMGR_STAT_SDMLASTPORRST_SET(value) (((value) << 2) & 0x00000004)
167 
168 /*
169  * Field : mpu0rst - mpu0rst
170  *
171  * MPU0 triggered a hardware sequenced warm reset.
172  *
173  * Field Access Macros:
174  *
175  */
176 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPU0RST register field. */
177 #define ALT_RSTMGR_STAT_MPU0RST_LSB 8
178 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPU0RST register field. */
179 #define ALT_RSTMGR_STAT_MPU0RST_MSB 8
180 /* The width in bits of the ALT_RSTMGR_STAT_MPU0RST register field. */
181 #define ALT_RSTMGR_STAT_MPU0RST_WIDTH 1
182 /* The mask used to set the ALT_RSTMGR_STAT_MPU0RST register field value. */
183 #define ALT_RSTMGR_STAT_MPU0RST_SET_MSK 0x00000100
184 /* The mask used to clear the ALT_RSTMGR_STAT_MPU0RST register field value. */
185 #define ALT_RSTMGR_STAT_MPU0RST_CLR_MSK 0xfffffeff
186 /* The reset value of the ALT_RSTMGR_STAT_MPU0RST register field. */
187 #define ALT_RSTMGR_STAT_MPU0RST_RESET 0x0
188 /* Extracts the ALT_RSTMGR_STAT_MPU0RST field value from a register. */
189 #define ALT_RSTMGR_STAT_MPU0RST_GET(value) (((value) & 0x00000100) >> 8)
190 /* Produces a ALT_RSTMGR_STAT_MPU0RST register field value suitable for setting the register. */
191 #define ALT_RSTMGR_STAT_MPU0RST_SET(value) (((value) << 8) & 0x00000100)
192 
193 /*
194  * Field : mpu1rst - mpu1rst
195  *
196  * MPU1 triggered a hardware sequenced warm reset.
197  *
198  * Field Access Macros:
199  *
200  */
201 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPU1RST register field. */
202 #define ALT_RSTMGR_STAT_MPU1RST_LSB 9
203 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPU1RST register field. */
204 #define ALT_RSTMGR_STAT_MPU1RST_MSB 9
205 /* The width in bits of the ALT_RSTMGR_STAT_MPU1RST register field. */
206 #define ALT_RSTMGR_STAT_MPU1RST_WIDTH 1
207 /* The mask used to set the ALT_RSTMGR_STAT_MPU1RST register field value. */
208 #define ALT_RSTMGR_STAT_MPU1RST_SET_MSK 0x00000200
209 /* The mask used to clear the ALT_RSTMGR_STAT_MPU1RST register field value. */
210 #define ALT_RSTMGR_STAT_MPU1RST_CLR_MSK 0xfffffdff
211 /* The reset value of the ALT_RSTMGR_STAT_MPU1RST register field. */
212 #define ALT_RSTMGR_STAT_MPU1RST_RESET 0x0
213 /* Extracts the ALT_RSTMGR_STAT_MPU1RST field value from a register. */
214 #define ALT_RSTMGR_STAT_MPU1RST_GET(value) (((value) & 0x00000200) >> 9)
215 /* Produces a ALT_RSTMGR_STAT_MPU1RST register field value suitable for setting the register. */
216 #define ALT_RSTMGR_STAT_MPU1RST_SET(value) (((value) << 9) & 0x00000200)
217 
218 /*
219  * Field : mpu2rst - mpu2rst
220  *
221  * MPU2 triggered a hardware sequenced warm reset.
222  *
223  * Field Access Macros:
224  *
225  */
226 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPU2RST register field. */
227 #define ALT_RSTMGR_STAT_MPU2RST_LSB 10
228 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPU2RST register field. */
229 #define ALT_RSTMGR_STAT_MPU2RST_MSB 10
230 /* The width in bits of the ALT_RSTMGR_STAT_MPU2RST register field. */
231 #define ALT_RSTMGR_STAT_MPU2RST_WIDTH 1
232 /* The mask used to set the ALT_RSTMGR_STAT_MPU2RST register field value. */
233 #define ALT_RSTMGR_STAT_MPU2RST_SET_MSK 0x00000400
234 /* The mask used to clear the ALT_RSTMGR_STAT_MPU2RST register field value. */
235 #define ALT_RSTMGR_STAT_MPU2RST_CLR_MSK 0xfffffbff
236 /* The reset value of the ALT_RSTMGR_STAT_MPU2RST register field. */
237 #define ALT_RSTMGR_STAT_MPU2RST_RESET 0x0
238 /* Extracts the ALT_RSTMGR_STAT_MPU2RST field value from a register. */
239 #define ALT_RSTMGR_STAT_MPU2RST_GET(value) (((value) & 0x00000400) >> 10)
240 /* Produces a ALT_RSTMGR_STAT_MPU2RST register field value suitable for setting the register. */
241 #define ALT_RSTMGR_STAT_MPU2RST_SET(value) (((value) << 10) & 0x00000400)
242 
243 /*
244  * Field : mpu3rst - mpu3rst
245  *
246  * MPU3 triggered a hardware sequenced warm reset.
247  *
248  * Field Access Macros:
249  *
250  */
251 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPU3RST register field. */
252 #define ALT_RSTMGR_STAT_MPU3RST_LSB 11
253 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPU3RST register field. */
254 #define ALT_RSTMGR_STAT_MPU3RST_MSB 11
255 /* The width in bits of the ALT_RSTMGR_STAT_MPU3RST register field. */
256 #define ALT_RSTMGR_STAT_MPU3RST_WIDTH 1
257 /* The mask used to set the ALT_RSTMGR_STAT_MPU3RST register field value. */
258 #define ALT_RSTMGR_STAT_MPU3RST_SET_MSK 0x00000800
259 /* The mask used to clear the ALT_RSTMGR_STAT_MPU3RST register field value. */
260 #define ALT_RSTMGR_STAT_MPU3RST_CLR_MSK 0xfffff7ff
261 /* The reset value of the ALT_RSTMGR_STAT_MPU3RST register field. */
262 #define ALT_RSTMGR_STAT_MPU3RST_RESET 0x0
263 /* Extracts the ALT_RSTMGR_STAT_MPU3RST field value from a register. */
264 #define ALT_RSTMGR_STAT_MPU3RST_GET(value) (((value) & 0x00000800) >> 11)
265 /* Produces a ALT_RSTMGR_STAT_MPU3RST register field value suitable for setting the register. */
266 #define ALT_RSTMGR_STAT_MPU3RST_SET(value) (((value) << 11) & 0x00000800)
267 
268 /*
269  * Field : l4wd0rst - l4wd0rst
270  *
271  * L4 Watchdog0 triggered a hardware sequenced warm reset.
272  *
273  * Field Access Macros:
274  *
275  */
276 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
277 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 16
278 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
279 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 16
280 /* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
281 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
282 /* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
283 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00010000
284 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
285 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xfffeffff
286 /* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
287 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
288 /* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
289 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00010000) >> 16)
290 /* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
291 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 16) & 0x00010000)
292 
293 /*
294  * Field : l4wd1rst - l4wd1rst
295  *
296  * L4 Watchdog1 triggered a hardware sequenced warm reset.
297  *
298  * Field Access Macros:
299  *
300  */
301 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
302 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 17
303 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
304 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 17
305 /* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
306 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
307 /* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
308 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00020000
309 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
310 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xfffdffff
311 /* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
312 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
313 /* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
314 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00020000) >> 17)
315 /* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
316 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 17) & 0x00020000)
317 
318 /*
319  * Field : l4wd2rst - l4wd2rst
320  *
321  * L4 Watchdog2 triggered a hardware sequenced warm reset.
322  *
323  * Field Access Macros:
324  *
325  */
326 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD2RST register field. */
327 #define ALT_RSTMGR_STAT_L4WD2RST_LSB 18
328 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD2RST register field. */
329 #define ALT_RSTMGR_STAT_L4WD2RST_MSB 18
330 /* The width in bits of the ALT_RSTMGR_STAT_L4WD2RST register field. */
331 #define ALT_RSTMGR_STAT_L4WD2RST_WIDTH 1
332 /* The mask used to set the ALT_RSTMGR_STAT_L4WD2RST register field value. */
333 #define ALT_RSTMGR_STAT_L4WD2RST_SET_MSK 0x00040000
334 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD2RST register field value. */
335 #define ALT_RSTMGR_STAT_L4WD2RST_CLR_MSK 0xfffbffff
336 /* The reset value of the ALT_RSTMGR_STAT_L4WD2RST register field. */
337 #define ALT_RSTMGR_STAT_L4WD2RST_RESET 0x0
338 /* Extracts the ALT_RSTMGR_STAT_L4WD2RST field value from a register. */
339 #define ALT_RSTMGR_STAT_L4WD2RST_GET(value) (((value) & 0x00040000) >> 18)
340 /* Produces a ALT_RSTMGR_STAT_L4WD2RST register field value suitable for setting the register. */
341 #define ALT_RSTMGR_STAT_L4WD2RST_SET(value) (((value) << 18) & 0x00040000)
342 
343 /*
344  * Field : l4wd3rst - l4wd3rst
345  *
346  * L4 Watchdog3 triggered a hardware sequenced warm reset.
347  *
348  * Field Access Macros:
349  *
350  */
351 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD3RST register field. */
352 #define ALT_RSTMGR_STAT_L4WD3RST_LSB 19
353 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD3RST register field. */
354 #define ALT_RSTMGR_STAT_L4WD3RST_MSB 19
355 /* The width in bits of the ALT_RSTMGR_STAT_L4WD3RST register field. */
356 #define ALT_RSTMGR_STAT_L4WD3RST_WIDTH 1
357 /* The mask used to set the ALT_RSTMGR_STAT_L4WD3RST register field value. */
358 #define ALT_RSTMGR_STAT_L4WD3RST_SET_MSK 0x00080000
359 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD3RST register field value. */
360 #define ALT_RSTMGR_STAT_L4WD3RST_CLR_MSK 0xfff7ffff
361 /* The reset value of the ALT_RSTMGR_STAT_L4WD3RST register field. */
362 #define ALT_RSTMGR_STAT_L4WD3RST_RESET 0x0
363 /* Extracts the ALT_RSTMGR_STAT_L4WD3RST field value from a register. */
364 #define ALT_RSTMGR_STAT_L4WD3RST_GET(value) (((value) & 0x00080000) >> 19)
365 /* Produces a ALT_RSTMGR_STAT_L4WD3RST register field value suitable for setting the register. */
366 #define ALT_RSTMGR_STAT_L4WD3RST_SET(value) (((value) << 19) & 0x00080000)
367 
368 /*
369  * Field : debugrst - debugrst
370  *
371  * "debugrst" indicates if the debug reset has been asserted. This bit is reset to
372  * its reset value on POR, not on warm or cold reset.
373  *
374  * Field Access Macros:
375  *
376  */
377 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_DEBUGRST register field. */
378 #define ALT_RSTMGR_STAT_DEBUGRST_LSB 24
379 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_DEBUGRST register field. */
380 #define ALT_RSTMGR_STAT_DEBUGRST_MSB 24
381 /* The width in bits of the ALT_RSTMGR_STAT_DEBUGRST register field. */
382 #define ALT_RSTMGR_STAT_DEBUGRST_WIDTH 1
383 /* The mask used to set the ALT_RSTMGR_STAT_DEBUGRST register field value. */
384 #define ALT_RSTMGR_STAT_DEBUGRST_SET_MSK 0x01000000
385 /* The mask used to clear the ALT_RSTMGR_STAT_DEBUGRST register field value. */
386 #define ALT_RSTMGR_STAT_DEBUGRST_CLR_MSK 0xfeffffff
387 /* The reset value of the ALT_RSTMGR_STAT_DEBUGRST register field. */
388 #define ALT_RSTMGR_STAT_DEBUGRST_RESET 0x0
389 /* Extracts the ALT_RSTMGR_STAT_DEBUGRST field value from a register. */
390 #define ALT_RSTMGR_STAT_DEBUGRST_GET(value) (((value) & 0x01000000) >> 24)
391 /* Produces a ALT_RSTMGR_STAT_DEBUGRST register field value suitable for setting the register. */
392 #define ALT_RSTMGR_STAT_DEBUGRST_SET(value) (((value) << 24) & 0x01000000)
393 
394 /*
395  * Field : csdaprst - csdaprst
396  *
397  * This bit indicates that CS DAP block has been reset. This bit is reset to its
398  * reset value on POR, not on warm or cold reset.
399  *
400  * Field Access Macros:
401  *
402  */
403 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CSDAPRST register field. */
404 #define ALT_RSTMGR_STAT_CSDAPRST_LSB 25
405 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CSDAPRST register field. */
406 #define ALT_RSTMGR_STAT_CSDAPRST_MSB 25
407 /* The width in bits of the ALT_RSTMGR_STAT_CSDAPRST register field. */
408 #define ALT_RSTMGR_STAT_CSDAPRST_WIDTH 1
409 /* The mask used to set the ALT_RSTMGR_STAT_CSDAPRST register field value. */
410 #define ALT_RSTMGR_STAT_CSDAPRST_SET_MSK 0x02000000
411 /* The mask used to clear the ALT_RSTMGR_STAT_CSDAPRST register field value. */
412 #define ALT_RSTMGR_STAT_CSDAPRST_CLR_MSK 0xfdffffff
413 /* The reset value of the ALT_RSTMGR_STAT_CSDAPRST register field. */
414 #define ALT_RSTMGR_STAT_CSDAPRST_RESET 0x0
415 /* Extracts the ALT_RSTMGR_STAT_CSDAPRST field value from a register. */
416 #define ALT_RSTMGR_STAT_CSDAPRST_GET(value) (((value) & 0x02000000) >> 25)
417 /* Produces a ALT_RSTMGR_STAT_CSDAPRST register field value suitable for setting the register. */
418 #define ALT_RSTMGR_STAT_CSDAPRST_SET(value) (((value) << 25) & 0x02000000)
419 
420 #ifndef __ASSEMBLY__
421 /*
422  * WARNING: The C register and register group struct declarations are provided for
423  * convenience and illustrative purposes. They should, however, be used with
424  * caution as the C language standard provides no guarantees about the alignment or
425  * atomicity of device memory accesses. The recommended practice for coding device
426  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
427  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
428  * alt_write_dword() functions for 64 bit registers.
429  *
430  * The struct declaration for register ALT_RSTMGR_STAT.
431  */
432 struct ALT_RSTMGR_STAT_s
433 {
434  volatile uint32_t sdmcoldrst : 1; /* SDM Cold Reset */
435  volatile uint32_t sdmwarmrst : 1; /* SDM Warm Reset */
436  volatile uint32_t sdmlastporrst : 1; /* SDM Last POR Reset */
437  uint32_t : 5; /* *UNDEFINED* */
438  volatile uint32_t mpu0rst : 1; /* mpu0rst */
439  volatile uint32_t mpu1rst : 1; /* mpu1rst */
440  volatile uint32_t mpu2rst : 1; /* mpu2rst */
441  volatile uint32_t mpu3rst : 1; /* mpu3rst */
442  uint32_t : 4; /* *UNDEFINED* */
443  volatile uint32_t l4wd0rst : 1; /* l4wd0rst */
444  volatile uint32_t l4wd1rst : 1; /* l4wd1rst */
445  volatile uint32_t l4wd2rst : 1; /* l4wd2rst */
446  volatile uint32_t l4wd3rst : 1; /* l4wd3rst */
447  uint32_t : 4; /* *UNDEFINED* */
448  volatile uint32_t debugrst : 1; /* debugrst */
449  volatile uint32_t csdaprst : 1; /* csdaprst */
450  uint32_t : 6; /* *UNDEFINED* */
451 };
452 
453 /* The typedef declaration for register ALT_RSTMGR_STAT. */
454 typedef struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
455 #endif /* __ASSEMBLY__ */
456 
457 /* The reset value of the ALT_RSTMGR_STAT register. */
458 #define ALT_RSTMGR_STAT_RESET 0x00000004
459 /* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
460 #define ALT_RSTMGR_STAT_OFST 0x0
461 
462 /*
463  * Register : MPU Reset Status - mpurststat
464  *
465  * The "mpurststat" register contains bits which indicate SDM that a CPU and/or
466  * Core reset has been asserted by MPU Software which is triggered by writing to
467  * the "mpumodrst" register and cpupor* fields of "coldmodrst" register.
468  *
469  * Hardware writes 1 to the respective bits to indicate which cpu or core has been
470  * reset. Software clears bits by writing 1.
471  *
472  * All the fields are cleared by cold reset.
473  *
474  * Register Layout
475  *
476  * Bits | Access | Reset | Description
477  * :--------|:-------|:------|:----------------------------------
478  * [0] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ
479  * [1] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ
480  * [2] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ
481  * [3] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ
482  * [7:4] | ??? | 0x0 | *UNDEFINED*
483  * [8] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ
484  * [9] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ
485  * [10] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ
486  * [11] | RW | 0x0 | ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ
487  * [31:12] | ??? | 0x0 | *UNDEFINED*
488  *
489  */
490 /*
491  * Field : cpupor0_irq
492  *
493  * This bit indicates SDM that MPU software has asserted reset to CPU0 by writing
494  * to the 'cpupor0' bit of register "coldmodrst".
495  *
496  * Field Access Macros:
497  *
498  */
499 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field. */
500 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_LSB 0
501 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field. */
502 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_MSB 0
503 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field. */
504 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_WIDTH 1
505 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field value. */
506 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_SET_MSK 0x00000001
507 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field value. */
508 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_CLR_MSK 0xfffffffe
509 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field. */
510 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_RESET 0x0
511 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ field value from a register. */
512 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_GET(value) (((value) & 0x00000001) >> 0)
513 /* Produces a ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ register field value suitable for setting the register. */
514 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_SET(value) (((value) << 0) & 0x00000001)
515 
516 /*
517  * Field : cpupor1_irq
518  *
519  * This bit indicates SDM that MPU software has asserted reset to CPU1 by writing
520  * to the 'cpupor1' bit of register "coldmodrst".
521  *
522  * Field Access Macros:
523  *
524  */
525 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field. */
526 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_LSB 1
527 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field. */
528 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_MSB 1
529 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field. */
530 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_WIDTH 1
531 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field value. */
532 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_SET_MSK 0x00000002
533 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field value. */
534 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_CLR_MSK 0xfffffffd
535 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field. */
536 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_RESET 0x0
537 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ field value from a register. */
538 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_GET(value) (((value) & 0x00000002) >> 1)
539 /* Produces a ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ register field value suitable for setting the register. */
540 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_SET(value) (((value) << 1) & 0x00000002)
541 
542 /*
543  * Field : cpupor2_irq
544  *
545  * This bit indicates SDM that MPU software has asserted reset to CPU2 by writing
546  * to the 'cpupor2' bit of register "coldmodrst".
547  *
548  * Field Access Macros:
549  *
550  */
551 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field. */
552 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_LSB 2
553 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field. */
554 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_MSB 2
555 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field. */
556 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_WIDTH 1
557 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field value. */
558 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_SET_MSK 0x00000004
559 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field value. */
560 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_CLR_MSK 0xfffffffb
561 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field. */
562 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_RESET 0x0
563 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ field value from a register. */
564 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_GET(value) (((value) & 0x00000004) >> 2)
565 /* Produces a ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ register field value suitable for setting the register. */
566 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_SET(value) (((value) << 2) & 0x00000004)
567 
568 /*
569  * Field : cpupor3_irq
570  *
571  * This bit indicates SDM that MPU software has asserted reset to CPU3 by writing
572  * to the 'cpupor3' bit of register "coldmodrst".
573  *
574  * Field Access Macros:
575  *
576  */
577 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field. */
578 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_LSB 3
579 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field. */
580 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_MSB 3
581 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field. */
582 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_WIDTH 1
583 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field value. */
584 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_SET_MSK 0x00000008
585 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field value. */
586 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_CLR_MSK 0xfffffff7
587 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field. */
588 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_RESET 0x0
589 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ field value from a register. */
590 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_GET(value) (((value) & 0x00000008) >> 3)
591 /* Produces a ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ register field value suitable for setting the register. */
592 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_SET(value) (((value) << 3) & 0x00000008)
593 
594 /*
595  * Field : core0_irq
596  *
597  * This bit indicates SDM that MPU software has asserted reset to core0 by writing
598  * to "mpumodrst" register.
599  *
600  * Field Access Macros:
601  *
602  */
603 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field. */
604 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_LSB 8
605 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field. */
606 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_MSB 8
607 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field. */
608 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_WIDTH 1
609 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field value. */
610 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_SET_MSK 0x00000100
611 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field value. */
612 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_CLR_MSK 0xfffffeff
613 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field. */
614 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_RESET 0x0
615 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ field value from a register. */
616 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_GET(value) (((value) & 0x00000100) >> 8)
617 /* Produces a ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ register field value suitable for setting the register. */
618 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_SET(value) (((value) << 8) & 0x00000100)
619 
620 /*
621  * Field : core1_irq
622  *
623  * This bit indicates SDM that MPU software has asserted reset to core1 by writing
624  * to "mpumodrst" register.
625  *
626  * Field Access Macros:
627  *
628  */
629 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field. */
630 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_LSB 9
631 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field. */
632 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_MSB 9
633 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field. */
634 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_WIDTH 1
635 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field value. */
636 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_SET_MSK 0x00000200
637 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field value. */
638 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_CLR_MSK 0xfffffdff
639 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field. */
640 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_RESET 0x0
641 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ field value from a register. */
642 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_GET(value) (((value) & 0x00000200) >> 9)
643 /* Produces a ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ register field value suitable for setting the register. */
644 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_SET(value) (((value) << 9) & 0x00000200)
645 
646 /*
647  * Field : core2_irq
648  *
649  * This bit indicates SDM that MPU software has asserted reset to core2 by writing
650  * to "mpumodrst" register.
651  *
652  * Field Access Macros:
653  *
654  */
655 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field. */
656 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_LSB 10
657 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field. */
658 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_MSB 10
659 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field. */
660 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_WIDTH 1
661 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field value. */
662 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_SET_MSK 0x00000400
663 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field value. */
664 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_CLR_MSK 0xfffffbff
665 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field. */
666 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_RESET 0x0
667 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ field value from a register. */
668 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_GET(value) (((value) & 0x00000400) >> 10)
669 /* Produces a ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ register field value suitable for setting the register. */
670 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_SET(value) (((value) << 10) & 0x00000400)
671 
672 /*
673  * Field : core3_irq
674  *
675  * This bit indicates SDM that MPU software has asserted reset to core3 by writing
676  * to "mpumodrst" register.
677  *
678  * Field Access Macros:
679  *
680  */
681 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field. */
682 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_LSB 11
683 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field. */
684 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_MSB 11
685 /* The width in bits of the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field. */
686 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_WIDTH 1
687 /* The mask used to set the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field value. */
688 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_SET_MSK 0x00000800
689 /* The mask used to clear the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field value. */
690 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_CLR_MSK 0xfffff7ff
691 /* The reset value of the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field. */
692 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_RESET 0x0
693 /* Extracts the ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ field value from a register. */
694 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_GET(value) (((value) & 0x00000800) >> 11)
695 /* Produces a ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ register field value suitable for setting the register. */
696 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_SET(value) (((value) << 11) & 0x00000800)
697 
698 #ifndef __ASSEMBLY__
699 /*
700  * WARNING: The C register and register group struct declarations are provided for
701  * convenience and illustrative purposes. They should, however, be used with
702  * caution as the C language standard provides no guarantees about the alignment or
703  * atomicity of device memory accesses. The recommended practice for coding device
704  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
705  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
706  * alt_write_dword() functions for 64 bit registers.
707  *
708  * The struct declaration for register ALT_RSTMGR_MPURSTSTAT.
709  */
710 struct ALT_RSTMGR_MPURSTSTAT_s
711 {
712  volatile uint32_t cpupor0_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ */
713  volatile uint32_t cpupor1_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ */
714  volatile uint32_t cpupor2_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ */
715  volatile uint32_t cpupor3_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ */
716  uint32_t : 4; /* *UNDEFINED* */
717  volatile uint32_t core0_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ */
718  volatile uint32_t core1_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ */
719  volatile uint32_t core2_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ */
720  volatile uint32_t core3_irq : 1; /* ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ */
721  uint32_t : 20; /* *UNDEFINED* */
722 };
723 
724 /* The typedef declaration for register ALT_RSTMGR_MPURSTSTAT. */
725 typedef struct ALT_RSTMGR_MPURSTSTAT_s ALT_RSTMGR_MPURSTSTAT_t;
726 #endif /* __ASSEMBLY__ */
727 
728 /* The reset value of the ALT_RSTMGR_MPURSTSTAT register. */
729 #define ALT_RSTMGR_MPURSTSTAT_RESET 0x00000000
730 /* The byte offset of the ALT_RSTMGR_MPURSTSTAT register from the beginning of the component. */
731 #define ALT_RSTMGR_MPURSTSTAT_OFST 0x4
732 
733 /*
734  * Register : Timeout Status Register - miscstat
735  *
736  * The "miscstat" register contains bits that indicate the timeout event. For
737  * timeout events, a field is 1 if its associated timeout occured as part of a
738  * hardware sequenced warm/debug reset.
739  *
740  * After a cold reset is complete, all bits are reset to their reset value. A warm
741  * reset does not clear any of the bits in the "miscstat" register. These bits must
742  * be cleared by software writing 1 to the "miscstat" register.
743  *
744  * Register Layout
745  *
746  * Bits | Access | Reset | Description
747  * :--------|:-------|:------|:---------------------------
748  * [0] | RW | 0x0 | SDRAM Self-Refresh Timeout
749  * [1] | ??? | 0x0 | *UNDEFINED*
750  * [2] | RW | 0x0 | FPGA Handshake Timeout
751  * [3] | RW | 0x0 | ETR Stall Timeout
752  * [7:4] | ??? | 0x0 | *UNDEFINED*
753  * [8] | RW | 0x0 | L2 Flush Handshake Timeout
754  * [15:9] | ??? | 0x0 | *UNDEFINED*
755  * [16] | RW | 0x0 | L3 NOC Handshake Timeout
756  * [31:17] | ??? | 0x0 | *UNDEFINED*
757  *
758  */
759 /*
760  * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
761  *
762  * A 1 indicates that Reset Manager's handshake request to the SDRAM Controller
763  * Subsystem timed out and the Reset Manager had to proceed with the warm/watchdog
764  * reset anyway.
765  *
766  * Field Access Macros:
767  *
768  */
769 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field. */
770 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_LSB 0
771 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field. */
772 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_MSB 0
773 /* The width in bits of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field. */
774 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_WIDTH 1
775 /* The mask used to set the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field value. */
776 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_SET_MSK 0x00000001
777 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field value. */
778 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_CLR_MSK 0xfffffffe
779 /* The reset value of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field. */
780 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_RESET 0x0
781 /* Extracts the ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT field value from a register. */
782 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_GET(value) (((value) & 0x00000001) >> 0)
783 /* Produces a ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT register field value suitable for setting the register. */
784 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_SET(value) (((value) << 0) & 0x00000001)
785 
786 /*
787  * Field : FPGA Handshake Timeout - fpgahstimeout
788  *
789  * A 1 indicates that Reset Manager's handshake request to FPGA before starting a
790  * hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to
791  * proceed with the warm/watchdog reset anyway.
792  *
793  * Field Access Macros:
794  *
795  */
796 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field. */
797 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_LSB 2
798 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field. */
799 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_MSB 2
800 /* The width in bits of the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field. */
801 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_WIDTH 1
802 /* The mask used to set the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field value. */
803 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_SET_MSK 0x00000004
804 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field value. */
805 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_CLR_MSK 0xfffffffb
806 /* The reset value of the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field. */
807 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_RESET 0x0
808 /* Extracts the ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT field value from a register. */
809 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_GET(value) (((value) & 0x00000004) >> 2)
810 /* Produces a ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT register field value suitable for setting the register. */
811 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_SET(value) (((value) << 2) & 0x00000004)
812 
813 /*
814  * Field : ETR Stall Timeout - etrstalltimeout
815  *
816  * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
817  * stall its AXI master port before starting a hardware sequenced warm/watchdog
818  * reset timed-out and the Reset Manager had to proceed with the warm/watchdog
819  * reset anyway.
820  *
821  * Field Access Macros:
822  *
823  */
824 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field. */
825 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_LSB 3
826 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field. */
827 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_MSB 3
828 /* The width in bits of the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field. */
829 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_WIDTH 1
830 /* The mask used to set the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field value. */
831 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_SET_MSK 0x00000008
832 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field value. */
833 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_CLR_MSK 0xfffffff7
834 /* The reset value of the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field. */
835 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_RESET 0x0
836 /* Extracts the ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT field value from a register. */
837 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_GET(value) (((value) & 0x00000008) >> 3)
838 /* Produces a ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT register field value suitable for setting the register. */
839 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_SET(value) (((value) << 3) & 0x00000008)
840 
841 /*
842  * Field : L2 Flush Handshake Timeout - mpul2flushtimeout
843  *
844  * A 1 indicates that Reset Manager's handshake request to L2 Flush timed-out and
845  * the Reset Manager had to proceed with reset anyway.
846  *
847  * Field Access Macros:
848  *
849  */
850 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field. */
851 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_LSB 8
852 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field. */
853 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_MSB 8
854 /* The width in bits of the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field. */
855 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_WIDTH 1
856 /* The mask used to set the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field value. */
857 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_SET_MSK 0x00000100
858 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field value. */
859 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_CLR_MSK 0xfffffeff
860 /* The reset value of the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field. */
861 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_RESET 0x0
862 /* Extracts the ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT field value from a register. */
863 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_GET(value) (((value) & 0x00000100) >> 8)
864 /* Produces a ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT register field value suitable for setting the register. */
865 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_SET(value) (((value) << 8) & 0x00000100)
866 
867 /*
868  * Field : L3 NOC Handshake Timeout - l3nocdbgtimeout
869  *
870  * A 1 indicates that Reset Manager's request to the NOC before starting a hardware
871  * sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed
872  * with the warm/watchdog reset anyway. Reset Manager performs this handshake with
873  * NOC when NOC is getting reset but debug logic does not get reset.
874  *
875  * Field Access Macros:
876  *
877  */
878 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field. */
879 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_LSB 16
880 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field. */
881 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_MSB 16
882 /* The width in bits of the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field. */
883 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_WIDTH 1
884 /* The mask used to set the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field value. */
885 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_SET_MSK 0x00010000
886 /* The mask used to clear the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field value. */
887 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_CLR_MSK 0xfffeffff
888 /* The reset value of the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field. */
889 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_RESET 0x0
890 /* Extracts the ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT field value from a register. */
891 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_GET(value) (((value) & 0x00010000) >> 16)
892 /* Produces a ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT register field value suitable for setting the register. */
893 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_SET(value) (((value) << 16) & 0x00010000)
894 
895 #ifndef __ASSEMBLY__
896 /*
897  * WARNING: The C register and register group struct declarations are provided for
898  * convenience and illustrative purposes. They should, however, be used with
899  * caution as the C language standard provides no guarantees about the alignment or
900  * atomicity of device memory accesses. The recommended practice for coding device
901  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
902  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
903  * alt_write_dword() functions for 64 bit registers.
904  *
905  * The struct declaration for register ALT_RSTMGR_MISCSTAT.
906  */
907 struct ALT_RSTMGR_MISCSTAT_s
908 {
909  volatile uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */
910  uint32_t : 1; /* *UNDEFINED* */
911  volatile uint32_t fpgahstimeout : 1; /* FPGA Handshake Timeout */
912  volatile uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */
913  uint32_t : 4; /* *UNDEFINED* */
914  volatile uint32_t mpul2flushtimeout : 1; /* L2 Flush Handshake Timeout */
915  uint32_t : 7; /* *UNDEFINED* */
916  volatile uint32_t l3nocdbgtimeout : 1; /* L3 NOC Handshake Timeout */
917  uint32_t : 15; /* *UNDEFINED* */
918 };
919 
920 /* The typedef declaration for register ALT_RSTMGR_MISCSTAT. */
921 typedef struct ALT_RSTMGR_MISCSTAT_s ALT_RSTMGR_MISCSTAT_t;
922 #endif /* __ASSEMBLY__ */
923 
924 /* The reset value of the ALT_RSTMGR_MISCSTAT register. */
925 #define ALT_RSTMGR_MISCSTAT_RESET 0x00000000
926 /* The byte offset of the ALT_RSTMGR_MISCSTAT register from the beginning of the component. */
927 #define ALT_RSTMGR_MISCSTAT_OFST 0x8
928 
929 /*
930  * Register : Handshake Enable - hdsken
931  *
932  * This register allows software to control whether or not to perform a handshake
933  * with certain peripherals before issuing a reset. These bits are cleared on a
934  * cold reset. If these bits are not set, writing to the "hdskreq" register to
935  * request a software-triggered handshake will not perform the handshake.
936  *
937  * If the peripheral is being held in reset, then the handshake will be skipped,
938  * regardless of whether the handshake enable bit is set or not.
939  *
940  * Register Layout
941  *
942  * Bits | Access | Reset | Description
943  * :--------|:-------|:------|:---------------------------------------------
944  * [0] | RW | 0x0 | SDRAM Self-Refresh Enable
945  * [1] | ??? | 0x0 | *UNDEFINED*
946  * [2] | RW | 0x0 | FPGA Handshake Enable
947  * [3] | RW | 0x0 | ETR (Embedded Trace Router) Handshake Enable
948  * [7:4] | ??? | 0x0 | *UNDEFINED*
949  * [8] | RW | 0x0 | L2 Flush Enable
950  * [15:9] | ??? | 0x0 | *UNDEFINED*
951  * [16] | RW | 0x0 | ALT_RSTMGR_HDSKEN_L3NOC_DBG
952  * [17] | RW | 0x0 | ALT_RSTMGR_HDSKEN_DEBUG_L3NOC
953  * [31:18] | ??? | 0x0 | *UNDEFINED*
954  *
955  */
956 /*
957  * Field : SDRAM Self-Refresh Enable - sdrselfrefen
958  *
959  * This field controls whether to perform handshake with the SDRAM memory interface
960  * before issuing a reset. If set to 1, the Reset Manager makes a request to the
961  * SDRAM memory interface before issuing a reset. If set to 0, the handshake is not
962  * performed.
963  *
964  * Field Access Macros:
965  *
966  */
967 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
968 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB 0
969 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
970 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB 0
971 /* The width in bits of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
972 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH 1
973 /* The mask used to set the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value. */
974 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
975 /* The mask used to clear the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value. */
976 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK 0xfffffffe
977 /* The reset value of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field. */
978 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET 0x0
979 /* Extracts the ALT_RSTMGR_HDSKEN_SDRSELFREFEN field value from a register. */
980 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value) (((value) & 0x00000001) >> 0)
981 /* Produces a ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value suitable for setting the register. */
982 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value) (((value) << 0) & 0x00000001)
983 
984 /*
985  * Field : FPGA Handshake Enable - fpgahsen
986  *
987  * This field controls whether to perform handshake with FPGA before issuing a
988  * reset. If set to 1, the Reset Manager makes a request to the FPGA before issuing
989  * a reset. If set to 0, the handshake is not performed.
990  *
991  * Field Access Macros:
992  *
993  */
994 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
995 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB 2
996 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
997 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB 2
998 /* The width in bits of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
999 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH 1
1000 /* The mask used to set the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value. */
1001 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
1002 /* The mask used to clear the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value. */
1003 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK 0xfffffffb
1004 /* The reset value of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field. */
1005 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET 0x0
1006 /* Extracts the ALT_RSTMGR_HDSKEN_FPGAHSEN field value from a register. */
1007 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value) (((value) & 0x00000004) >> 2)
1008 /* Produces a ALT_RSTMGR_HDSKEN_FPGAHSEN register field value suitable for setting the register. */
1009 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value) (((value) << 2) & 0x00000004)
1010 
1011 /*
1012  * Field : ETR (Embedded Trace Router) Handshake Enable - etrstallen
1013  *
1014  * Software writes this field 1 to request to the ETR that it stalls its AXI master
1015  * to the L3 Interconnect.
1016  *
1017  * This field controls whether the hardware should perform a handhshake with the
1018  * ETR before issuing a reset. If set to 1, the Reset Manager handshakes with the
1019  * ETR. If set to 0, the handshake is not performed.
1020  *
1021  * Field Access Macros:
1022  *
1023  */
1024 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1025 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB 3
1026 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1027 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB 3
1028 /* The width in bits of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1029 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH 1
1030 /* The mask used to set the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value. */
1031 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
1032 /* The mask used to clear the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value. */
1033 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK 0xfffffff7
1034 /* The reset value of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field. */
1035 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET 0x0
1036 /* Extracts the ALT_RSTMGR_HDSKEN_ETRSTALLEN field value from a register. */
1037 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value) (((value) & 0x00000008) >> 3)
1038 /* Produces a ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value suitable for setting the register. */
1039 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value) (((value) << 3) & 0x00000008)
1040 
1041 /*
1042  * Field : L2 Flush Enable - l2flushen
1043  *
1044  * This field controls whether the L2 cache should be flushed before the L2 cache
1045  * is reset by a watchdog reset or a software-requested L2 cache reset.
1046  *
1047  * If bit to 1, the Reset Manager makes a request to the MPU to perform L2 flush
1048  * before performing ETR/HMC/FPGA handshakes. If bit to 0, the L2 Flush is not
1049  * performed. L2 Flush is not performed as a part of warm reset sequence.
1050  *
1051  * Field Access Macros:
1052  *
1053  */
1054 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field. */
1055 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_LSB 8
1056 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field. */
1057 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_MSB 8
1058 /* The width in bits of the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field. */
1059 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_WIDTH 1
1060 /* The mask used to set the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field value. */
1061 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_SET_MSK 0x00000100
1062 /* The mask used to clear the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field value. */
1063 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_CLR_MSK 0xfffffeff
1064 /* The reset value of the ALT_RSTMGR_HDSKEN_L2FLUSHEN register field. */
1065 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_RESET 0x0
1066 /* Extracts the ALT_RSTMGR_HDSKEN_L2FLUSHEN field value from a register. */
1067 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_GET(value) (((value) & 0x00000100) >> 8)
1068 /* Produces a ALT_RSTMGR_HDSKEN_L2FLUSHEN register field value suitable for setting the register. */
1069 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_SET(value) (((value) << 8) & 0x00000100)
1070 
1071 /*
1072  * Field : l3noc_dbg
1073  *
1074  * This field controls whether to perform handshake with L3 NOC before issuing a
1075  * reset. If set to 1, the Reset Manager makes a request to the L3 NOC before
1076  * issuing a reset. If set to 0, the handshake is not performed.
1077  *
1078  * This handshake is performed when NOC is getting reset but debug and dap are not
1079  * getting reset
1080  *
1081  * Field Access Macros:
1082  *
1083  */
1084 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field. */
1085 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_LSB 16
1086 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field. */
1087 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_MSB 16
1088 /* The width in bits of the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field. */
1089 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_WIDTH 1
1090 /* The mask used to set the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field value. */
1091 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_SET_MSK 0x00010000
1092 /* The mask used to clear the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field value. */
1093 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_CLR_MSK 0xfffeffff
1094 /* The reset value of the ALT_RSTMGR_HDSKEN_L3NOC_DBG register field. */
1095 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_RESET 0x0
1096 /* Extracts the ALT_RSTMGR_HDSKEN_L3NOC_DBG field value from a register. */
1097 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_GET(value) (((value) & 0x00010000) >> 16)
1098 /* Produces a ALT_RSTMGR_HDSKEN_L3NOC_DBG register field value suitable for setting the register. */
1099 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_SET(value) (((value) << 16) & 0x00010000)
1100 
1101 /*
1102  * Field : debug_l3noc
1103  *
1104  * This field controls whether to perform handshake with L3 NOC before asserting
1105  * the csdap_rst or/and dbg_rst. If set to 1, the Reset Manager makes a request to
1106  * the L3 NOC before issuing a reset. If set to 0, the handshake is not performed.
1107  *
1108  * This handshake is performed when CS DAP or/and DBG is getting reset but NOC is
1109  * not getting reset.
1110  *
1111  * Field Access Macros:
1112  *
1113  */
1114 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field. */
1115 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_LSB 17
1116 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field. */
1117 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_MSB 17
1118 /* The width in bits of the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field. */
1119 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_WIDTH 1
1120 /* The mask used to set the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field value. */
1121 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_SET_MSK 0x00020000
1122 /* The mask used to clear the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field value. */
1123 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_CLR_MSK 0xfffdffff
1124 /* The reset value of the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field. */
1125 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_RESET 0x0
1126 /* Extracts the ALT_RSTMGR_HDSKEN_DEBUG_L3NOC field value from a register. */
1127 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_GET(value) (((value) & 0x00020000) >> 17)
1128 /* Produces a ALT_RSTMGR_HDSKEN_DEBUG_L3NOC register field value suitable for setting the register. */
1129 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_SET(value) (((value) << 17) & 0x00020000)
1130 
1131 #ifndef __ASSEMBLY__
1132 /*
1133  * WARNING: The C register and register group struct declarations are provided for
1134  * convenience and illustrative purposes. They should, however, be used with
1135  * caution as the C language standard provides no guarantees about the alignment or
1136  * atomicity of device memory accesses. The recommended practice for coding device
1137  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1138  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1139  * alt_write_dword() functions for 64 bit registers.
1140  *
1141  * The struct declaration for register ALT_RSTMGR_HDSKEN.
1142  */
1143 struct ALT_RSTMGR_HDSKEN_s
1144 {
1145  volatile uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */
1146  uint32_t : 1; /* *UNDEFINED* */
1147  volatile uint32_t fpgahsen : 1; /* FPGA Handshake Enable */
1148  volatile uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Handshake Enable */
1149  uint32_t : 4; /* *UNDEFINED* */
1150  volatile uint32_t l2flushen : 1; /* L2 Flush Enable */
1151  uint32_t : 7; /* *UNDEFINED* */
1152  volatile uint32_t l3noc_dbg : 1; /* ALT_RSTMGR_HDSKEN_L3NOC_DBG */
1153  volatile uint32_t debug_l3noc : 1; /* ALT_RSTMGR_HDSKEN_DEBUG_L3NOC */
1154  uint32_t : 14; /* *UNDEFINED* */
1155 };
1156 
1157 /* The typedef declaration for register ALT_RSTMGR_HDSKEN. */
1158 typedef struct ALT_RSTMGR_HDSKEN_s ALT_RSTMGR_HDSKEN_t;
1159 #endif /* __ASSEMBLY__ */
1160 
1161 /* The reset value of the ALT_RSTMGR_HDSKEN register. */
1162 #define ALT_RSTMGR_HDSKEN_RESET 0x00000000
1163 /* The byte offset of the ALT_RSTMGR_HDSKEN register from the beginning of the component. */
1164 #define ALT_RSTMGR_HDSKEN_OFST 0x10
1165 
1166 /*
1167  * Register : Handshake Request Register - hdskreq
1168  *
1169  * This register includes fields for software to initiate the handshake with
1170  * certain peripherals. Software must clear the request bit except for
1171  * "debug_l3noc_req" once it sees the corresponding acknowledge bit has been set in
1172  * the hdskack register. "debug_l3noc_req" is cleared by hardware once the
1173  * corresponding dbg_rst or csdap_rst is/are asserted. Software should implement
1174  * its own timeout.
1175  *
1176  * Fields are reset by a cold reset. It is recommended that software should clear
1177  * this bit on every warm reset.
1178  *
1179  * Register Layout
1180  *
1181  * Bits | Access | Reset | Description
1182  * :-------|:-------|:------|:------------------------------------------
1183  * [0] | RW | 0x0 | SDRAM Self-Refresh Request
1184  * [1] | ??? | 0x0 | *UNDEFINED*
1185  * [2] | RW | 0x0 | FPGA Handshake Request
1186  * [3] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request
1187  * [4] | RW | 0x0 | ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ
1188  * [5] | RW | 0x0 | ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ
1189  * [31:6] | ??? | 0x0 | *UNDEFINED*
1190  *
1191  */
1192 /*
1193  * Field : SDRAM Self-Refresh Request - sdrselfrefreq
1194  *
1195  * Software writes this field 1 to request that the SDRAM Controller Subsystem to
1196  * stop accepting any new transactions and allows all outstanding transactions to
1197  * drain.
1198  *
1199  * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
1200  * Note that it is possible for the SDRAM Controller Subsystem to never assert
1201  * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
1202  *
1203  * Field Access Macros:
1204  *
1205  */
1206 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1207 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0
1208 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1209 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0
1210 /* The width in bits of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1211 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1
1212 /* The mask used to set the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value. */
1213 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001
1214 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value. */
1215 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe
1216 /* The reset value of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field. */
1217 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0
1218 /* Extracts the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ field value from a register. */
1219 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0)
1220 /* Produces a ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value suitable for setting the register. */
1221 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001)
1222 
1223 /*
1224  * Field : FPGA Handshake Request - fpgahsreq
1225  *
1226  * Software writes this field 1 to initiate a handshake request to FPGA. Software
1227  * waits for the FPGAHSACK to be active and then writes this field to 0. Note that
1228  * it is possible for the FPGA to never assert FPGAHSACK so software should timeout
1229  * in this case.
1230  *
1231  * Field Access Macros:
1232  *
1233  */
1234 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1235 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2
1236 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1237 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2
1238 /* The width in bits of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1239 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1
1240 /* The mask used to set the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value. */
1241 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004
1242 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value. */
1243 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb
1244 /* The reset value of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field. */
1245 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0
1246 /* Extracts the ALT_RSTMGR_HDSKREQ_FPGAHSREQ field value from a register. */
1247 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2)
1248 /* Produces a ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value suitable for setting the register. */
1249 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004)
1250 
1251 /*
1252  * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
1253  *
1254  * Software sets bit field to 1 to ask the ETR to that stall its AXI master to the
1255  * L3 Interconnect.
1256  *
1257  * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note
1258  * that it is possible for the ETR to never assert ETRSTALLACK so software should
1259  * timeout if ETRSTALLACK is never asserted.
1260  *
1261  * Field Access Macros:
1262  *
1263  */
1264 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1265 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3
1266 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1267 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3
1268 /* The width in bits of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1269 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1
1270 /* The mask used to set the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value. */
1271 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008
1272 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value. */
1273 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7
1274 /* The reset value of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field. */
1275 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0
1276 /* Extracts the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ field value from a register. */
1277 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3)
1278 /* Produces a ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value suitable for setting the register. */
1279 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008)
1280 
1281 /*
1282  * Field : l3noc_dbg_req
1283  *
1284  * Software writes this field 1 to initiate a handshake request to L3 NOC. This
1285  * handshake is done to stop L3NOC accept any new transactions and allow all
1286  * outstanding transactions to drain. Software waits for the L3NOC_DBG_ACK to be
1287  * active and then writes this field to 0. Note that it is possible for the L3NOC
1288  * to never assert L3NOC_DBG_ACK so software should timeout in this case.
1289  *
1290  * Field Access Macros:
1291  *
1292  */
1293 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field. */
1294 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_LSB 4
1295 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field. */
1296 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_MSB 4
1297 /* The width in bits of the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field. */
1298 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_WIDTH 1
1299 /* The mask used to set the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field value. */
1300 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_SET_MSK 0x00000010
1301 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field value. */
1302 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_CLR_MSK 0xffffffef
1303 /* The reset value of the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field. */
1304 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_RESET 0x0
1305 /* Extracts the ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ field value from a register. */
1306 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_GET(value) (((value) & 0x00000010) >> 4)
1307 /* Produces a ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ register field value suitable for setting the register. */
1308 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_SET(value) (((value) << 4) & 0x00000010)
1309 
1310 /*
1311  * Field : debug_l3noc_req
1312  *
1313  * Software writes this field 1 to initiate a handshake request to L3 NOC. This
1314  * handshake is done to stop L3NOC accept any new transactions and allow all
1315  * outstanding transactions to drain.
1316  *
1317  * Hardware clears the request bit when dbg_rst or csdap_rst or both are asserted
1318  * by SW by writing to the dbgmodrst register. Note that it is possible for the
1319  * L3NOC to never assert DEBUG_L3NOC_ACK so software should timeout in this case.
1320  *
1321  * Field Access Macros:
1322  *
1323  */
1324 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field. */
1325 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_LSB 5
1326 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field. */
1327 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_MSB 5
1328 /* The width in bits of the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field. */
1329 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_WIDTH 1
1330 /* The mask used to set the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field value. */
1331 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_SET_MSK 0x00000020
1332 /* The mask used to clear the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field value. */
1333 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_CLR_MSK 0xffffffdf
1334 /* The reset value of the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field. */
1335 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_RESET 0x0
1336 /* Extracts the ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ field value from a register. */
1337 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_GET(value) (((value) & 0x00000020) >> 5)
1338 /* Produces a ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ register field value suitable for setting the register. */
1339 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_SET(value) (((value) << 5) & 0x00000020)
1340 
1341 #ifndef __ASSEMBLY__
1342 /*
1343  * WARNING: The C register and register group struct declarations are provided for
1344  * convenience and illustrative purposes. They should, however, be used with
1345  * caution as the C language standard provides no guarantees about the alignment or
1346  * atomicity of device memory accesses. The recommended practice for coding device
1347  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1348  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1349  * alt_write_dword() functions for 64 bit registers.
1350  *
1351  * The struct declaration for register ALT_RSTMGR_HDSKREQ.
1352  */
1353 struct ALT_RSTMGR_HDSKREQ_s
1354 {
1355  volatile uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */
1356  uint32_t : 1; /* *UNDEFINED* */
1357  volatile uint32_t fpgahsreq : 1; /* FPGA Handshake Request */
1358  volatile uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */
1359  volatile uint32_t l3noc_dbg_req : 1; /* ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ */
1360  volatile uint32_t debug_l3noc_req : 1; /* ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ */
1361  uint32_t : 26; /* *UNDEFINED* */
1362 };
1363 
1364 /* The typedef declaration for register ALT_RSTMGR_HDSKREQ. */
1365 typedef struct ALT_RSTMGR_HDSKREQ_s ALT_RSTMGR_HDSKREQ_t;
1366 #endif /* __ASSEMBLY__ */
1367 
1368 /* The reset value of the ALT_RSTMGR_HDSKREQ register. */
1369 #define ALT_RSTMGR_HDSKREQ_RESET 0x00000000
1370 /* The byte offset of the ALT_RSTMGR_HDSKREQ register from the beginning of the component. */
1371 #define ALT_RSTMGR_HDSKREQ_OFST 0x14
1372 
1373 /*
1374  * Register : Handshake Acknowledge Register - hdskack
1375  *
1376  * This register includes fields for software to detect the completion of the
1377  * handshake with certain peripherals. Once the peripheral has completed the
1378  * handshake, it will set the appropriate bit in this register. Once software has
1379  * detected that the acknowledge bit is set, it must clear the corresponding
1380  * request bit in the HDSREQ register.
1381  *
1382  * Software writes 1 to the corresponding bits to clear them.
1383  *
1384  * Fields are reset by a cold reset.
1385  *
1386  * Register Layout
1387  *
1388  * Bits | Access | Reset | Description
1389  * :-------|:-------|:------|:----------------------------------------------
1390  * [0] | RW | 0x0 | SDRAM Self-Refresh Acknowledge
1391  * [1] | ??? | 0x0 | *UNDEFINED*
1392  * [2] | RW | 0x0 | FPGA Handshake Acknowledge
1393  * [3] | RW | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge
1394  * [4] | RW | 0x0 | ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK
1395  * [5] | RW | 0x0 | ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK
1396  * [31:6] | ??? | 0x0 | *UNDEFINED*
1397  *
1398  */
1399 /*
1400  * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
1401  *
1402  * This is the acknowledge that SDRAM handshake acknowledge has been received by
1403  * Reset Manager. A 1 indicates that the SDRAM Controller Subsystem has
1404  * acknowledged the handshake request.
1405  *
1406  * Field Access Macros:
1407  *
1408  */
1409 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1410 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB 0
1411 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1412 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB 0
1413 /* The width in bits of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1414 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH 1
1415 /* The mask used to set the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value. */
1416 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK 0x00000001
1417 /* The mask used to clear the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value. */
1418 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK 0xfffffffe
1419 /* The reset value of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field. */
1420 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET 0x0
1421 /* Extracts the ALT_RSTMGR_HDSKACK_SDRSELFREQACK field value from a register. */
1422 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value) (((value) & 0x00000001) >> 0)
1423 /* Produces a ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value suitable for setting the register. */
1424 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value) (((value) << 0) & 0x00000001)
1425 
1426 /*
1427  * Field : FPGA Handshake Acknowledge - fpgahsack
1428  *
1429  * This is the acknowledge that the FPGA handshake acknowledge has been received by
1430  * Reset Manager. A 1 indicates that the FPGA has acknowledged the handshake
1431  * request.
1432  *
1433  * Field Access Macros:
1434  *
1435  */
1436 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1437 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB 2
1438 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1439 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB 2
1440 /* The width in bits of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1441 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH 1
1442 /* The mask used to set the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value. */
1443 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK 0x00000004
1444 /* The mask used to clear the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value. */
1445 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK 0xfffffffb
1446 /* The reset value of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field. */
1447 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET 0x0
1448 /* Extracts the ALT_RSTMGR_HDSKACK_FPGAHSACK field value from a register. */
1449 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value) (((value) & 0x00000004) >> 2)
1450 /* Produces a ALT_RSTMGR_HDSKACK_FPGAHSACK register field value suitable for setting the register. */
1451 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value) (((value) << 2) & 0x00000004)
1452 
1453 /*
1454  * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
1455  *
1456  * This is the acknowlege for a ETR AXI master stall initiated as a part of the ETR
1457  * handshake. A 1 indicates that the ETR has stalled its AXI master.
1458  *
1459  * Field Access Macros:
1460  *
1461  */
1462 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1463 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB 3
1464 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1465 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB 3
1466 /* The width in bits of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1467 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH 1
1468 /* The mask used to set the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value. */
1469 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK 0x00000008
1470 /* The mask used to clear the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value. */
1471 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK 0xfffffff7
1472 /* The reset value of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field. */
1473 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET 0x0
1474 /* Extracts the ALT_RSTMGR_HDSKACK_ETRSTALLACK field value from a register. */
1475 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value) (((value) & 0x00000008) >> 3)
1476 /* Produces a ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value suitable for setting the register. */
1477 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value) (((value) << 3) & 0x00000008)
1478 
1479 /*
1480  * Field : l3noc_dbg_ack
1481  *
1482  * This field indicates that L3NOC handshake acknowledge has been received by Reset
1483  * Manager. A 1 indicates that the L3NOC has acknowledged the handshake request.
1484  *
1485  * The handshake is initiated with L3NOC as a part of warm/watchdog reset assertion
1486  * sequence or handshake request initiated by the L3NOC_DBG_REQ field. This
1487  * handshake is done to stop L3NOC from accepting any new transactions and allow
1488  * all outstanding transactions to drain.
1489  *
1490  * Field Access Macros:
1491  *
1492  */
1493 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field. */
1494 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_LSB 4
1495 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field. */
1496 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_MSB 4
1497 /* The width in bits of the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field. */
1498 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_WIDTH 1
1499 /* The mask used to set the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field value. */
1500 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_SET_MSK 0x00000010
1501 /* The mask used to clear the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field value. */
1502 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_CLR_MSK 0xffffffef
1503 /* The reset value of the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field. */
1504 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_RESET 0x0
1505 /* Extracts the ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK field value from a register. */
1506 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_GET(value) (((value) & 0x00000010) >> 4)
1507 /* Produces a ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK register field value suitable for setting the register. */
1508 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_SET(value) (((value) << 4) & 0x00000010)
1509 
1510 /*
1511  * Field : debug_l3noc_ack
1512  *
1513  * This field indicates that L3NOC handshake acknowledge has been received by Reset
1514  * Manager. A 1 indicates that the L3NOC has acknowledged the handshake request.
1515  *
1516  * The handshake is initiated with L3NOC as a part of handshake request initiated
1517  * by the DEBUG_L3NOC_REQ field. This handshake is done to stop L3NOC from
1518  * accepting any new transactions and allow all outstanding transactions to drain.
1519  *
1520  * Field Access Macros:
1521  *
1522  */
1523 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field. */
1524 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_LSB 5
1525 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field. */
1526 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_MSB 5
1527 /* The width in bits of the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field. */
1528 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_WIDTH 1
1529 /* The mask used to set the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field value. */
1530 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_SET_MSK 0x00000020
1531 /* The mask used to clear the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field value. */
1532 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_CLR_MSK 0xffffffdf
1533 /* The reset value of the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field. */
1534 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_RESET 0x0
1535 /* Extracts the ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK field value from a register. */
1536 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_GET(value) (((value) & 0x00000020) >> 5)
1537 /* Produces a ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK register field value suitable for setting the register. */
1538 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_SET(value) (((value) << 5) & 0x00000020)
1539 
1540 #ifndef __ASSEMBLY__
1541 /*
1542  * WARNING: The C register and register group struct declarations are provided for
1543  * convenience and illustrative purposes. They should, however, be used with
1544  * caution as the C language standard provides no guarantees about the alignment or
1545  * atomicity of device memory accesses. The recommended practice for coding device
1546  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1547  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1548  * alt_write_dword() functions for 64 bit registers.
1549  *
1550  * The struct declaration for register ALT_RSTMGR_HDSKACK.
1551  */
1552 struct ALT_RSTMGR_HDSKACK_s
1553 {
1554  volatile uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */
1555  uint32_t : 1; /* *UNDEFINED* */
1556  volatile uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */
1557  volatile uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */
1558  volatile uint32_t l3noc_dbg_ack : 1; /* ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK */
1559  volatile uint32_t debug_l3noc_ack : 1; /* ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK */
1560  uint32_t : 26; /* *UNDEFINED* */
1561 };
1562 
1563 /* The typedef declaration for register ALT_RSTMGR_HDSKACK. */
1564 typedef struct ALT_RSTMGR_HDSKACK_s ALT_RSTMGR_HDSKACK_t;
1565 #endif /* __ASSEMBLY__ */
1566 
1567 /* The reset value of the ALT_RSTMGR_HDSKACK register. */
1568 #define ALT_RSTMGR_HDSKACK_RESET 0x00000000
1569 /* The byte offset of the ALT_RSTMGR_HDSKACK register from the beginning of the component. */
1570 #define ALT_RSTMGR_HDSKACK_OFST 0x18
1571 
1572 /*
1573  * Register : ETR Stall Status Register - hdskstall
1574  *
1575  * This register keeps the ETR stalled after a warm/watchdog reset occurs. If the
1576  * ETR handshake is enabled in the bit field ETRSTALLEN of HDSKEN register, then
1577  * the hardware will perform a handshake with the ETR before asserting a warm or
1578  * watchdog reset. When the reset is complete, the hardware will keep the request
1579  * signal to the ETR asserted to continue to stall it until software clears the
1580  * HSDKSTALL register bit.
1581  *
1582  * Field is reset by a cold reset.
1583  *
1584  * Register Layout
1585  *
1586  * Bits | Access | Reset | Description
1587  * :-------|:-------|:------|:----------------------------------------------
1588  * [0] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Reset
1589  * [31:1] | ??? | 0x0 | *UNDEFINED*
1590  *
1591  */
1592 /*
1593  * Field : ETR (Embedded Trace Router) Stall After Reset - etrstallwarmrst
1594  *
1595  * If ETRSTALLEN bit field is 1 and Reset manager generates the handshake request
1596  * to ETR, hardware sets this bit to 1 to indicate that the stall of the ETR AXI
1597  * master. Hardware leaves the ETR stalled after a warm or watchdog reset until
1598  * software clears this field by writing it with 1. Software must only clear this
1599  * field when it is ready to have the ETR AXI master start making AXI requests to
1600  * write trace data.
1601  *
1602  * Field Access Macros:
1603  *
1604  */
1605 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field. */
1606 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_LSB 0
1607 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field. */
1608 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_MSB 0
1609 /* The width in bits of the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field. */
1610 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_WIDTH 1
1611 /* The mask used to set the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field value. */
1612 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_SET_MSK 0x00000001
1613 /* The mask used to clear the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field value. */
1614 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_CLR_MSK 0xfffffffe
1615 /* The reset value of the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field. */
1616 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_RESET 0x0
1617 /* Extracts the ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST field value from a register. */
1618 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_GET(value) (((value) & 0x00000001) >> 0)
1619 /* Produces a ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST register field value suitable for setting the register. */
1620 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_SET(value) (((value) << 0) & 0x00000001)
1621 
1622 #ifndef __ASSEMBLY__
1623 /*
1624  * WARNING: The C register and register group struct declarations are provided for
1625  * convenience and illustrative purposes. They should, however, be used with
1626  * caution as the C language standard provides no guarantees about the alignment or
1627  * atomicity of device memory accesses. The recommended practice for coding device
1628  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1629  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1630  * alt_write_dword() functions for 64 bit registers.
1631  *
1632  * The struct declaration for register ALT_RSTMGR_HDSKSTALL.
1633  */
1634 struct ALT_RSTMGR_HDSKSTALL_s
1635 {
1636  volatile uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Reset */
1637  uint32_t : 31; /* *UNDEFINED* */
1638 };
1639 
1640 /* The typedef declaration for register ALT_RSTMGR_HDSKSTALL. */
1641 typedef struct ALT_RSTMGR_HDSKSTALL_s ALT_RSTMGR_HDSKSTALL_t;
1642 #endif /* __ASSEMBLY__ */
1643 
1644 /* The reset value of the ALT_RSTMGR_HDSKSTALL register. */
1645 #define ALT_RSTMGR_HDSKSTALL_RESET 0x00000000
1646 /* The byte offset of the ALT_RSTMGR_HDSKSTALL register from the beginning of the component. */
1647 #define ALT_RSTMGR_HDSKSTALL_OFST 0x1c
1648 
1649 /*
1650  * Register : MPU Module Reset Register - mpumodrst
1651  *
1652  * The MPUMODRST register is used by software to trigger module resets (individual
1653  * module reset signals). Writing 1 to any of these fields will cause the CPU core
1654  * reset signal to be asserted if that CPU is in WFI mode. The Reset Manager
1655  * hardware will bring the module back out of reset after the appropriate amount of
1656  * time.
1657  *
1658  * All fields are reset by a cold or a warm reset.
1659  *
1660  * Register Layout
1661  *
1662  * Bits | Access | Reset | Description
1663  * :-------|:-------|:------|:-------------
1664  * [0] | RW | 0x0 | Resets CORE0
1665  * [1] | RW | 0x0 | Resets CORE1
1666  * [2] | RW | 0x0 | Resets CORE2
1667  * [3] | RW | 0x0 | Resets CORE3
1668  * [31:4] | ??? | 0x0 | *UNDEFINED*
1669  *
1670  */
1671 /*
1672  * Field : Resets CORE0 - core0
1673  *
1674  * Resets ncorereset port of CPU0.
1675  *
1676  * Field Access Macros:
1677  *
1678  */
1679 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CORE0 register field. */
1680 #define ALT_RSTMGR_MPUMODRST_CORE0_LSB 0
1681 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CORE0 register field. */
1682 #define ALT_RSTMGR_MPUMODRST_CORE0_MSB 0
1683 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CORE0 register field. */
1684 #define ALT_RSTMGR_MPUMODRST_CORE0_WIDTH 1
1685 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CORE0 register field value. */
1686 #define ALT_RSTMGR_MPUMODRST_CORE0_SET_MSK 0x00000001
1687 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CORE0 register field value. */
1688 #define ALT_RSTMGR_MPUMODRST_CORE0_CLR_MSK 0xfffffffe
1689 /* The reset value of the ALT_RSTMGR_MPUMODRST_CORE0 register field. */
1690 #define ALT_RSTMGR_MPUMODRST_CORE0_RESET 0x0
1691 /* Extracts the ALT_RSTMGR_MPUMODRST_CORE0 field value from a register. */
1692 #define ALT_RSTMGR_MPUMODRST_CORE0_GET(value) (((value) & 0x00000001) >> 0)
1693 /* Produces a ALT_RSTMGR_MPUMODRST_CORE0 register field value suitable for setting the register. */
1694 #define ALT_RSTMGR_MPUMODRST_CORE0_SET(value) (((value) << 0) & 0x00000001)
1695 
1696 /*
1697  * Field : Resets CORE1 - core1
1698  *
1699  * Resets ncorereset port of CPU1.
1700  *
1701  * Field Access Macros:
1702  *
1703  */
1704 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CORE1 register field. */
1705 #define ALT_RSTMGR_MPUMODRST_CORE1_LSB 1
1706 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CORE1 register field. */
1707 #define ALT_RSTMGR_MPUMODRST_CORE1_MSB 1
1708 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CORE1 register field. */
1709 #define ALT_RSTMGR_MPUMODRST_CORE1_WIDTH 1
1710 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CORE1 register field value. */
1711 #define ALT_RSTMGR_MPUMODRST_CORE1_SET_MSK 0x00000002
1712 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CORE1 register field value. */
1713 #define ALT_RSTMGR_MPUMODRST_CORE1_CLR_MSK 0xfffffffd
1714 /* The reset value of the ALT_RSTMGR_MPUMODRST_CORE1 register field. */
1715 #define ALT_RSTMGR_MPUMODRST_CORE1_RESET 0x0
1716 /* Extracts the ALT_RSTMGR_MPUMODRST_CORE1 field value from a register. */
1717 #define ALT_RSTMGR_MPUMODRST_CORE1_GET(value) (((value) & 0x00000002) >> 1)
1718 /* Produces a ALT_RSTMGR_MPUMODRST_CORE1 register field value suitable for setting the register. */
1719 #define ALT_RSTMGR_MPUMODRST_CORE1_SET(value) (((value) << 1) & 0x00000002)
1720 
1721 /*
1722  * Field : Resets CORE2 - core2
1723  *
1724  * Resets ncorereset port of CPU2.
1725  *
1726  * Field Access Macros:
1727  *
1728  */
1729 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CORE2 register field. */
1730 #define ALT_RSTMGR_MPUMODRST_CORE2_LSB 2
1731 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CORE2 register field. */
1732 #define ALT_RSTMGR_MPUMODRST_CORE2_MSB 2
1733 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CORE2 register field. */
1734 #define ALT_RSTMGR_MPUMODRST_CORE2_WIDTH 1
1735 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CORE2 register field value. */
1736 #define ALT_RSTMGR_MPUMODRST_CORE2_SET_MSK 0x00000004
1737 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CORE2 register field value. */
1738 #define ALT_RSTMGR_MPUMODRST_CORE2_CLR_MSK 0xfffffffb
1739 /* The reset value of the ALT_RSTMGR_MPUMODRST_CORE2 register field. */
1740 #define ALT_RSTMGR_MPUMODRST_CORE2_RESET 0x0
1741 /* Extracts the ALT_RSTMGR_MPUMODRST_CORE2 field value from a register. */
1742 #define ALT_RSTMGR_MPUMODRST_CORE2_GET(value) (((value) & 0x00000004) >> 2)
1743 /* Produces a ALT_RSTMGR_MPUMODRST_CORE2 register field value suitable for setting the register. */
1744 #define ALT_RSTMGR_MPUMODRST_CORE2_SET(value) (((value) << 2) & 0x00000004)
1745 
1746 /*
1747  * Field : Resets CORE3 - core3
1748  *
1749  * Resets ncorereset port of CPU3.
1750  *
1751  * Field Access Macros:
1752  *
1753  */
1754 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CORE3 register field. */
1755 #define ALT_RSTMGR_MPUMODRST_CORE3_LSB 3
1756 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CORE3 register field. */
1757 #define ALT_RSTMGR_MPUMODRST_CORE3_MSB 3
1758 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CORE3 register field. */
1759 #define ALT_RSTMGR_MPUMODRST_CORE3_WIDTH 1
1760 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CORE3 register field value. */
1761 #define ALT_RSTMGR_MPUMODRST_CORE3_SET_MSK 0x00000008
1762 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CORE3 register field value. */
1763 #define ALT_RSTMGR_MPUMODRST_CORE3_CLR_MSK 0xfffffff7
1764 /* The reset value of the ALT_RSTMGR_MPUMODRST_CORE3 register field. */
1765 #define ALT_RSTMGR_MPUMODRST_CORE3_RESET 0x0
1766 /* Extracts the ALT_RSTMGR_MPUMODRST_CORE3 field value from a register. */
1767 #define ALT_RSTMGR_MPUMODRST_CORE3_GET(value) (((value) & 0x00000008) >> 3)
1768 /* Produces a ALT_RSTMGR_MPUMODRST_CORE3 register field value suitable for setting the register. */
1769 #define ALT_RSTMGR_MPUMODRST_CORE3_SET(value) (((value) << 3) & 0x00000008)
1770 
1771 #ifndef __ASSEMBLY__
1772 /*
1773  * WARNING: The C register and register group struct declarations are provided for
1774  * convenience and illustrative purposes. They should, however, be used with
1775  * caution as the C language standard provides no guarantees about the alignment or
1776  * atomicity of device memory accesses. The recommended practice for coding device
1777  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1778  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1779  * alt_write_dword() functions for 64 bit registers.
1780  *
1781  * The struct declaration for register ALT_RSTMGR_MPUMODRST.
1782  */
1783 struct ALT_RSTMGR_MPUMODRST_s
1784 {
1785  volatile uint32_t core0 : 1; /* Resets CORE0 */
1786  volatile uint32_t core1 : 1; /* Resets CORE1 */
1787  volatile uint32_t core2 : 1; /* Resets CORE2 */
1788  volatile uint32_t core3 : 1; /* Resets CORE3 */
1789  uint32_t : 28; /* *UNDEFINED* */
1790 };
1791 
1792 /* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
1793 typedef struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
1794 #endif /* __ASSEMBLY__ */
1795 
1796 /* The reset value of the ALT_RSTMGR_MPUMODRST register. */
1797 #define ALT_RSTMGR_MPUMODRST_RESET 0x00000000
1798 /* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
1799 #define ALT_RSTMGR_MPUMODRST_OFST 0x20
1800 
1801 /*
1802  * Register : Peripheral 0 Module Reset Register - per0modrst
1803  *
1804  * The PER0MODRST register is used by software to control module resets for
1805  * Peripheral Group and Fast Peripheral Group. Software explicitly asserts and de-
1806  * asserts module reset signals by writing bits in the appropriate *MODRST
1807  * register. It is up to software to ensure module reset signals are asserted for
1808  * the appropriate length of time and are de-asserted in the correct order. It is
1809  * also up to software to not assert a module reset signal that would prevent
1810  * software from de-asserting the module reset signal.
1811  *
1812  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1813  * assert the module reset signal.
1814  *
1815  * All fields are reset by a cold reset. All fields are also reset by a warm reset.
1816  *
1817  * The reset value of all fields is 1. This holds the corresponding module in reset
1818  * until software is ready to release the module from reset by writing 0 to its
1819  * field.
1820  *
1821  * Register Layout
1822  *
1823  * Bits | Access | Reset | Description
1824  * :-----|:-------|:------|:---------------
1825  * [0] | RW | 0x1 | EMAC0
1826  * [1] | RW | 0x1 | EMAC1
1827  * [2] | RW | 0x1 | EMAC2
1828  * [3] | RW | 0x1 | USB0
1829  * [4] | RW | 0x1 | USB1
1830  * [5] | RW | 0x1 | NAND Flash
1831  * [6] | ??? | 0x1 | *UNDEFINED*
1832  * [7] | RW | 0x1 | SD/MMC
1833  * [8] | RW | 0x1 | EMAC0OCP
1834  * [9] | RW | 0x1 | EMAC1OCP
1835  * [10] | RW | 0x1 | EMAC2OCP
1836  * [11] | RW | 0x1 | USB0OCP
1837  * [12] | RW | 0x1 | USB1OCP
1838  * [13] | RW | 0x1 | NANDOCP
1839  * [14] | ??? | 0x1 | *UNDEFINED*
1840  * [15] | RW | 0x1 | SDMMCOCP
1841  * [16] | RW | 0x1 | DMA Controller
1842  * [17] | RW | 0x1 | SPIM0
1843  * [18] | RW | 0x1 | SPIM1
1844  * [19] | RW | 0x1 | SPIS0
1845  * [20] | RW | 0x1 | SPIS1
1846  * [21] | RW | 0x1 | DMAOCP
1847  * [22] | RW | 0x1 | EMAC PTP
1848  * [23] | ??? | 0x1 | *UNDEFINED*
1849  * [24] | RW | 0x1 | FPGA DMA0
1850  * [25] | RW | 0x1 | FPGA DMA1
1851  * [26] | RW | 0x1 | FPGA DMA2
1852  * [27] | RW | 0x1 | FPGA DMA3
1853  * [28] | RW | 0x1 | FPGA DMA4
1854  * [29] | RW | 0x1 | FPGA DMA5
1855  * [30] | RW | 0x1 | FPGA DMA6
1856  * [31] | RW | 0x1 | FPGA DMA7
1857  *
1858  */
1859 /*
1860  * Field : EMAC0 - emac0
1861  *
1862  * Resets EMAC0.
1863  *
1864  * Field Access Macros:
1865  *
1866  */
1867 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
1868 #define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0
1869 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
1870 #define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0
1871 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
1872 #define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1
1873 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0 register field value. */
1874 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
1875 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0 register field value. */
1876 #define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe
1877 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0 register field. */
1878 #define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1
1879 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC0 field value from a register. */
1880 #define ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1881 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC0 register field value suitable for setting the register. */
1882 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1883 
1884 /*
1885  * Field : EMAC1 - emac1
1886  *
1887  * Resets EMAC1.
1888  *
1889  * Field Access Macros:
1890  *
1891  */
1892 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
1893 #define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1
1894 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
1895 #define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1
1896 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
1897 #define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1
1898 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1 register field value. */
1899 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
1900 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1 register field value. */
1901 #define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd
1902 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1 register field. */
1903 #define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1
1904 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC1 field value from a register. */
1905 #define ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1906 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC1 register field value suitable for setting the register. */
1907 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1908 
1909 /*
1910  * Field : EMAC2 - emac2
1911  *
1912  * Resets EMAC2.
1913  *
1914  * Field Access Macros:
1915  *
1916  */
1917 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
1918 #define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2
1919 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
1920 #define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2
1921 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
1922 #define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1
1923 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2 register field value. */
1924 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
1925 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2 register field value. */
1926 #define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb
1927 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2 register field. */
1928 #define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1
1929 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC2 field value from a register. */
1930 #define ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
1931 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC2 register field value suitable for setting the register. */
1932 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004)
1933 
1934 /*
1935  * Field : USB0 - usb0
1936  *
1937  * Resets USB0.
1938  *
1939  * Field Access Macros:
1940  *
1941  */
1942 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
1943 #define ALT_RSTMGR_PER0MODRST_USB0_LSB 3
1944 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
1945 #define ALT_RSTMGR_PER0MODRST_USB0_MSB 3
1946 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
1947 #define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1
1948 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB0 register field value. */
1949 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
1950 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0 register field value. */
1951 #define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7
1952 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB0 register field. */
1953 #define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1
1954 /* Extracts the ALT_RSTMGR_PER0MODRST_USB0 field value from a register. */
1955 #define ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3)
1956 /* Produces a ALT_RSTMGR_PER0MODRST_USB0 register field value suitable for setting the register. */
1957 #define ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008)
1958 
1959 /*
1960  * Field : USB1 - usb1
1961  *
1962  * Resets USB1.
1963  *
1964  * Field Access Macros:
1965  *
1966  */
1967 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
1968 #define ALT_RSTMGR_PER0MODRST_USB1_LSB 4
1969 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
1970 #define ALT_RSTMGR_PER0MODRST_USB1_MSB 4
1971 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
1972 #define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1
1973 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB1 register field value. */
1974 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
1975 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1 register field value. */
1976 #define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef
1977 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB1 register field. */
1978 #define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1
1979 /* Extracts the ALT_RSTMGR_PER0MODRST_USB1 field value from a register. */
1980 #define ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4)
1981 /* Produces a ALT_RSTMGR_PER0MODRST_USB1 register field value suitable for setting the register. */
1982 #define ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010)
1983 
1984 /*
1985  * Field : NAND Flash - nand
1986  *
1987  * Resets NAND flash controller.
1988  *
1989  * Field Access Macros:
1990  *
1991  */
1992 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field. */
1993 #define ALT_RSTMGR_PER0MODRST_NAND_LSB 5
1994 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field. */
1995 #define ALT_RSTMGR_PER0MODRST_NAND_MSB 5
1996 /* The width in bits of the ALT_RSTMGR_PER0MODRST_NAND register field. */
1997 #define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1
1998 /* The mask used to set the ALT_RSTMGR_PER0MODRST_NAND register field value. */
1999 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
2000 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_NAND register field value. */
2001 #define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf
2002 /* The reset value of the ALT_RSTMGR_PER0MODRST_NAND register field. */
2003 #define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1
2004 /* Extracts the ALT_RSTMGR_PER0MODRST_NAND field value from a register. */
2005 #define ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5)
2006 /* Produces a ALT_RSTMGR_PER0MODRST_NAND register field value suitable for setting the register. */
2007 #define ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020)
2008 
2009 /*
2010  * Field : SD/MMC - sdmmc
2011  *
2012  * Resets SD/MMC controller.
2013  *
2014  * Field Access Macros:
2015  *
2016  */
2017 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2018 #define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7
2019 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2020 #define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7
2021 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2022 #define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1
2023 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMC register field value. */
2024 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
2025 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMC register field value. */
2026 #define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f
2027 /* The reset value of the ALT_RSTMGR_PER0MODRST_SDMMC register field. */
2028 #define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1
2029 /* Extracts the ALT_RSTMGR_PER0MODRST_SDMMC field value from a register. */
2030 #define ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
2031 /* Produces a ALT_RSTMGR_PER0MODRST_SDMMC register field value suitable for setting the register. */
2032 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080)
2033 
2034 /*
2035  * Field : EMAC0OCP - emac0ocp
2036  *
2037  * Resets EMAC0 ECC OCP DIagnostics modules.
2038  *
2039  * Field Access Macros:
2040  *
2041  */
2042 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2043 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8
2044 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2045 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8
2046 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2047 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1
2048 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value. */
2049 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100
2050 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value. */
2051 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff
2052 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field. */
2053 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1
2054 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC0OCP field value from a register. */
2055 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
2056 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value suitable for setting the register. */
2057 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
2058 
2059 /*
2060  * Field : EMAC1OCP - emac1ocp
2061  *
2062  * Resets EMAC1 ECC OCP DIagnostics modules.
2063  *
2064  * Field Access Macros:
2065  *
2066  */
2067 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2068 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9
2069 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2070 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9
2071 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2072 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1
2073 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value. */
2074 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200
2075 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value. */
2076 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff
2077 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field. */
2078 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1
2079 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC1OCP field value from a register. */
2080 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
2081 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value suitable for setting the register. */
2082 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
2083 
2084 /*
2085  * Field : EMAC2OCP - emac2ocp
2086  *
2087  * Resets EMAC0 ECC OCP DIagnostics modules.
2088  *
2089  * Field Access Macros:
2090  *
2091  */
2092 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2093 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10
2094 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2095 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10
2096 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2097 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1
2098 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value. */
2099 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400
2100 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value. */
2101 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff
2102 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field. */
2103 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1
2104 /* Extracts the ALT_RSTMGR_PER0MODRST_EMAC2OCP field value from a register. */
2105 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
2106 /* Produces a ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value suitable for setting the register. */
2107 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
2108 
2109 /*
2110  * Field : USB0OCP - usb0ocp
2111  *
2112  * Resets USB0 ECC OCP DIagnostics modules.
2113  *
2114  * Field Access Macros:
2115  *
2116  */
2117 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2118 #define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11
2119 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2120 #define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11
2121 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2122 #define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1
2123 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB0OCP register field value. */
2124 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800
2125 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0OCP register field value. */
2126 #define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff
2127 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB0OCP register field. */
2128 #define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1
2129 /* Extracts the ALT_RSTMGR_PER0MODRST_USB0OCP field value from a register. */
2130 #define ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
2131 /* Produces a ALT_RSTMGR_PER0MODRST_USB0OCP register field value suitable for setting the register. */
2132 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
2133 
2134 /*
2135  * Field : USB1OCP - usb1ocp
2136  *
2137  * Resets USB1 ECC OCP DIagnostics modules.
2138  *
2139  * Field Access Macros:
2140  *
2141  */
2142 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2143 #define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12
2144 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2145 #define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12
2146 /* The width in bits of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2147 #define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1
2148 /* The mask used to set the ALT_RSTMGR_PER0MODRST_USB1OCP register field value. */
2149 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000
2150 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1OCP register field value. */
2151 #define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff
2152 /* The reset value of the ALT_RSTMGR_PER0MODRST_USB1OCP register field. */
2153 #define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1
2154 /* Extracts the ALT_RSTMGR_PER0MODRST_USB1OCP field value from a register. */
2155 #define ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
2156 /* Produces a ALT_RSTMGR_PER0MODRST_USB1OCP register field value suitable for setting the register. */
2157 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
2158 
2159 /*
2160  * Field : NANDOCP - nandocp
2161  *
2162  * Resets NAND ECC OCP DIagnostics modules.
2163  *
2164  * Field Access Macros:
2165  *
2166  */
2167 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2168 #define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13
2169 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2170 #define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13
2171 /* The width in bits of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2172 #define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1
2173 /* The mask used to set the ALT_RSTMGR_PER0MODRST_NANDOCP register field value. */
2174 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000
2175 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_NANDOCP register field value. */
2176 #define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff
2177 /* The reset value of the ALT_RSTMGR_PER0MODRST_NANDOCP register field. */
2178 #define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1
2179 /* Extracts the ALT_RSTMGR_PER0MODRST_NANDOCP field value from a register. */
2180 #define ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
2181 /* Produces a ALT_RSTMGR_PER0MODRST_NANDOCP register field value suitable for setting the register. */
2182 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
2183 
2184 /*
2185  * Field : SDMMCOCP - sdmmcocp
2186  *
2187  * Resets SDMMC ECC OCP DIagnostics modules.
2188  *
2189  * Field Access Macros:
2190  *
2191  */
2192 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2193 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15
2194 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2195 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15
2196 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2197 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1
2198 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value. */
2199 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000
2200 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value. */
2201 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff
2202 /* The reset value of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field. */
2203 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1
2204 /* Extracts the ALT_RSTMGR_PER0MODRST_SDMMCOCP field value from a register. */
2205 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
2206 /* Produces a ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value suitable for setting the register. */
2207 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
2208 
2209 /*
2210  * Field : DMA Controller - dma
2211  *
2212  * Resets DMA controller.
2213  *
2214  * Field Access Macros:
2215  *
2216  */
2217 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2218 #define ALT_RSTMGR_PER0MODRST_DMA_LSB 16
2219 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2220 #define ALT_RSTMGR_PER0MODRST_DMA_MSB 16
2221 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2222 #define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1
2223 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMA register field value. */
2224 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
2225 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMA register field value. */
2226 #define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff
2227 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMA register field. */
2228 #define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1
2229 /* Extracts the ALT_RSTMGR_PER0MODRST_DMA field value from a register. */
2230 #define ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16)
2231 /* Produces a ALT_RSTMGR_PER0MODRST_DMA register field value suitable for setting the register. */
2232 #define ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000)
2233 
2234 /*
2235  * Field : SPIM0 - spim0
2236  *
2237  * Resets SPIM0 controller.
2238  *
2239  * Field Access Macros:
2240  *
2241  */
2242 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2243 #define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17
2244 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2245 #define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17
2246 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2247 #define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1
2248 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM0 register field value. */
2249 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
2250 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM0 register field value. */
2251 #define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff
2252 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIM0 register field. */
2253 #define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1
2254 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIM0 field value from a register. */
2255 #define ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
2256 /* Produces a ALT_RSTMGR_PER0MODRST_SPIM0 register field value suitable for setting the register. */
2257 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000)
2258 
2259 /*
2260  * Field : SPIM1 - spim1
2261  *
2262  * Resets SPIM1 controller.
2263  *
2264  * Field Access Macros:
2265  *
2266  */
2267 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2268 #define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18
2269 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2270 #define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18
2271 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2272 #define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1
2273 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM1 register field value. */
2274 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
2275 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM1 register field value. */
2276 #define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff
2277 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIM1 register field. */
2278 #define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1
2279 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIM1 field value from a register. */
2280 #define ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
2281 /* Produces a ALT_RSTMGR_PER0MODRST_SPIM1 register field value suitable for setting the register. */
2282 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000)
2283 
2284 /*
2285  * Field : SPIS0 - spis0
2286  *
2287  * Resets SPIS0 controller.
2288  *
2289  * Field Access Macros:
2290  *
2291  */
2292 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2293 #define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19
2294 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2295 #define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19
2296 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2297 #define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1
2298 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS0 register field value. */
2299 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
2300 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS0 register field value. */
2301 #define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff
2302 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIS0 register field. */
2303 #define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1
2304 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIS0 field value from a register. */
2305 #define ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
2306 /* Produces a ALT_RSTMGR_PER0MODRST_SPIS0 register field value suitable for setting the register. */
2307 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000)
2308 
2309 /*
2310  * Field : SPIS1 - spis1
2311  *
2312  * Resets SPIS1 controller.
2313  *
2314  * Field Access Macros:
2315  *
2316  */
2317 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2318 #define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20
2319 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2320 #define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20
2321 /* The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2322 #define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1
2323 /* The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS1 register field value. */
2324 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
2325 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS1 register field value. */
2326 #define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff
2327 /* The reset value of the ALT_RSTMGR_PER0MODRST_SPIS1 register field. */
2328 #define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1
2329 /* Extracts the ALT_RSTMGR_PER0MODRST_SPIS1 field value from a register. */
2330 #define ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
2331 /* Produces a ALT_RSTMGR_PER0MODRST_SPIS1 register field value suitable for setting the register. */
2332 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000)
2333 
2334 /*
2335  * Field : DMAOCP - dmaocp
2336  *
2337  * Resets DMA Controller ECC OCP DIagnostics modules.
2338  *
2339  * Field Access Macros:
2340  *
2341  */
2342 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2343 #define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21
2344 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2345 #define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21
2346 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2347 #define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1
2348 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAOCP register field value. */
2349 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000
2350 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAOCP register field value. */
2351 #define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff
2352 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAOCP register field. */
2353 #define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1
2354 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAOCP field value from a register. */
2355 #define ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
2356 /* Produces a ALT_RSTMGR_PER0MODRST_DMAOCP register field value suitable for setting the register. */
2357 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
2358 
2359 /*
2360  * Field : EMAC PTP - emacptp
2361  *
2362  * Resets EMAC PTP.
2363  *
2364  * Field Access Macros:
2365  *
2366  */
2367 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2368 #define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22
2369 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2370 #define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22
2371 /* The width in bits of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2372 #define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1
2373 /* The mask used to set the ALT_RSTMGR_PER0MODRST_EMACPTP register field value. */
2374 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
2375 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_EMACPTP register field value. */
2376 #define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff
2377 /* The reset value of the ALT_RSTMGR_PER0MODRST_EMACPTP register field. */
2378 #define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1
2379 /* Extracts the ALT_RSTMGR_PER0MODRST_EMACPTP field value from a register. */
2380 #define ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
2381 /* Produces a ALT_RSTMGR_PER0MODRST_EMACPTP register field value suitable for setting the register. */
2382 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
2383 
2384 /*
2385  * Field : FPGA DMA0 - dmaif0
2386  *
2387  * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
2388  * Controller.
2389  *
2390  * Field Access Macros:
2391  *
2392  */
2393 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2394 #define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24
2395 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2396 #define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24
2397 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2398 #define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1
2399 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value. */
2400 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
2401 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value. */
2402 #define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff
2403 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field. */
2404 #define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1
2405 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF0 field value from a register. */
2406 #define ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
2407 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF0 register field value suitable for setting the register. */
2408 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
2409 
2410 /*
2411  * Field : FPGA DMA1 - dmaif1
2412  *
2413  * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
2414  * Controller
2415  *
2416  * Field Access Macros:
2417  *
2418  */
2419 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2420 #define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25
2421 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2422 #define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25
2423 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2424 #define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1
2425 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value. */
2426 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
2427 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value. */
2428 #define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff
2429 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field. */
2430 #define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1
2431 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF1 field value from a register. */
2432 #define ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
2433 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF1 register field value suitable for setting the register. */
2434 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
2435 
2436 /*
2437  * Field : FPGA DMA2 - dmaif2
2438  *
2439  * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
2440  * Controller.
2441  *
2442  * Field Access Macros:
2443  *
2444  */
2445 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2446 #define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26
2447 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2448 #define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26
2449 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2450 #define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1
2451 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value. */
2452 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
2453 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value. */
2454 #define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff
2455 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field. */
2456 #define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1
2457 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF2 field value from a register. */
2458 #define ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
2459 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF2 register field value suitable for setting the register. */
2460 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
2461 
2462 /*
2463  * Field : FPGA DMA3 - dmaif3
2464  *
2465  * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
2466  * Controller.
2467  *
2468  * Field Access Macros:
2469  *
2470  */
2471 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2472 #define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27
2473 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2474 #define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27
2475 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2476 #define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1
2477 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value. */
2478 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
2479 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value. */
2480 #define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff
2481 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field. */
2482 #define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1
2483 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF3 field value from a register. */
2484 #define ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
2485 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF3 register field value suitable for setting the register. */
2486 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
2487 
2488 /*
2489  * Field : FPGA DMA4 - dmaif4
2490  *
2491  * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
2492  * Controller
2493  *
2494  * Field Access Macros:
2495  *
2496  */
2497 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2498 #define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28
2499 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2500 #define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28
2501 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2502 #define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1
2503 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value. */
2504 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
2505 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value. */
2506 #define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff
2507 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field. */
2508 #define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1
2509 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF4 field value from a register. */
2510 #define ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
2511 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF4 register field value suitable for setting the register. */
2512 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
2513 
2514 /*
2515  * Field : FPGA DMA5 - dmaif5
2516  *
2517  * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
2518  * Controller
2519  *
2520  * Field Access Macros:
2521  *
2522  */
2523 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2524 #define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29
2525 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2526 #define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29
2527 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2528 #define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1
2529 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value. */
2530 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
2531 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value. */
2532 #define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff
2533 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field. */
2534 #define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1
2535 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF5 field value from a register. */
2536 #define ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
2537 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF5 register field value suitable for setting the register. */
2538 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
2539 
2540 /*
2541  * Field : FPGA DMA6 - dmaif6
2542  *
2543  * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
2544  * Controller
2545  *
2546  * Field Access Macros:
2547  *
2548  */
2549 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2550 #define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30
2551 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2552 #define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30
2553 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2554 #define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1
2555 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value. */
2556 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
2557 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value. */
2558 #define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff
2559 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field. */
2560 #define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1
2561 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF6 field value from a register. */
2562 #define ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
2563 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF6 register field value suitable for setting the register. */
2564 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
2565 
2566 /*
2567  * Field : FPGA DMA7 - dmaif7
2568  *
2569  * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
2570  * Controller
2571  *
2572  * Field Access Macros:
2573  *
2574  */
2575 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2576 #define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31
2577 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2578 #define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31
2579 /* The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2580 #define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1
2581 /* The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value. */
2582 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
2583 /* The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value. */
2584 #define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff
2585 /* The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field. */
2586 #define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1
2587 /* Extracts the ALT_RSTMGR_PER0MODRST_DMAIF7 field value from a register. */
2588 #define ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
2589 /* Produces a ALT_RSTMGR_PER0MODRST_DMAIF7 register field value suitable for setting the register. */
2590 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
2591 
2592 #ifndef __ASSEMBLY__
2593 /*
2594  * WARNING: The C register and register group struct declarations are provided for
2595  * convenience and illustrative purposes. They should, however, be used with
2596  * caution as the C language standard provides no guarantees about the alignment or
2597  * atomicity of device memory accesses. The recommended practice for coding device
2598  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2599  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2600  * alt_write_dword() functions for 64 bit registers.
2601  *
2602  * The struct declaration for register ALT_RSTMGR_PER0MODRST.
2603  */
2604 struct ALT_RSTMGR_PER0MODRST_s
2605 {
2606  volatile uint32_t emac0 : 1; /* EMAC0 */
2607  volatile uint32_t emac1 : 1; /* EMAC1 */
2608  volatile uint32_t emac2 : 1; /* EMAC2 */
2609  volatile uint32_t usb0 : 1; /* USB0 */
2610  volatile uint32_t usb1 : 1; /* USB1 */
2611  volatile uint32_t nand : 1; /* NAND Flash */
2612  uint32_t : 1; /* *UNDEFINED* */
2613  volatile uint32_t sdmmc : 1; /* SD/MMC */
2614  volatile uint32_t emac0ocp : 1; /* EMAC0OCP */
2615  volatile uint32_t emac1ocp : 1; /* EMAC1OCP */
2616  volatile uint32_t emac2ocp : 1; /* EMAC2OCP */
2617  volatile uint32_t usb0ocp : 1; /* USB0OCP */
2618  volatile uint32_t usb1ocp : 1; /* USB1OCP */
2619  volatile uint32_t nandocp : 1; /* NANDOCP */
2620  uint32_t : 1; /* *UNDEFINED* */
2621  volatile uint32_t sdmmcocp : 1; /* SDMMCOCP */
2622  volatile uint32_t dma : 1; /* DMA Controller */
2623  volatile uint32_t spim0 : 1; /* SPIM0 */
2624  volatile uint32_t spim1 : 1; /* SPIM1 */
2625  volatile uint32_t spis0 : 1; /* SPIS0 */
2626  volatile uint32_t spis1 : 1; /* SPIS1 */
2627  volatile uint32_t dmaocp : 1; /* DMAOCP */
2628  volatile uint32_t emacptp : 1; /* EMAC PTP */
2629  uint32_t : 1; /* *UNDEFINED* */
2630  volatile uint32_t dmaif0 : 1; /* FPGA DMA0 */
2631  volatile uint32_t dmaif1 : 1; /* FPGA DMA1 */
2632  volatile uint32_t dmaif2 : 1; /* FPGA DMA2 */
2633  volatile uint32_t dmaif3 : 1; /* FPGA DMA3 */
2634  volatile uint32_t dmaif4 : 1; /* FPGA DMA4 */
2635  volatile uint32_t dmaif5 : 1; /* FPGA DMA5 */
2636  volatile uint32_t dmaif6 : 1; /* FPGA DMA6 */
2637  volatile uint32_t dmaif7 : 1; /* FPGA DMA7 */
2638 };
2639 
2640 /* The typedef declaration for register ALT_RSTMGR_PER0MODRST. */
2641 typedef struct ALT_RSTMGR_PER0MODRST_s ALT_RSTMGR_PER0MODRST_t;
2642 #endif /* __ASSEMBLY__ */
2643 
2644 /* The reset value of the ALT_RSTMGR_PER0MODRST register. */
2645 #define ALT_RSTMGR_PER0MODRST_RESET 0xffffffff
2646 /* The byte offset of the ALT_RSTMGR_PER0MODRST register from the beginning of the component. */
2647 #define ALT_RSTMGR_PER0MODRST_OFST 0x24
2648 
2649 /*
2650  * Register : Peripheral Module Reset Register - per1modrst
2651  *
2652  * The PER1MODRST register is used by software to trigger module resets for Slow
2653  * Peripheral Group. Software explicitly asserts and de-asserts module reset
2654  * signals by writing bits in the appropriate *MODRST register. It is up to
2655  * software to ensure module reset signals are asserted for the appropriaThe
2656  * PER1MODRST register is used by software to control module resets for Slow
2657  * Peripheral Group. Software explicitly asserts and de-asserts module reset
2658  * signals by writing bits in the appropriate *MODRST register. It is up to
2659  * software to ensure module reset signals are asserted for the appropriate length
2660  * of time and are de-asserted in the correct order. It is also up to software to
2661  * not assert a module reset signal that would prevent software from de-asserting
2662  * the module reset signal.
2663  *
2664  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2665  * assert the module reset signal.
2666  *
2667  * All fields are reset by a cold reset. All fields are also reset by a warm reset.
2668  *
2669  * The reset value of all fields is 1. This holds the corresponding module in reset
2670  * until software is ready to release the module from reset by writing 0 to its
2671  * field.
2672  *
2673  * Register Layout
2674  *
2675  * Bits | Access | Reset | Description
2676  * :--------|:-------|:------|:-------------
2677  * [0] | RW | 0x1 | Watch Dog0
2678  * [1] | RW | 0x1 | Watch Dog1
2679  * [2] | RW | 0x1 | Watch Dog2
2680  * [3] | RW | 0x1 | Watch Dog3
2681  * [4] | RW | 0x1 | l4systimer0
2682  * [5] | RW | 0x1 | l4sys_timer1
2683  * [6] | RW | 0x1 | SP Timer 0
2684  * [7] | RW | 0x1 | SP Timer 1
2685  * [8] | RW | 0x1 | I2C0
2686  * [9] | RW | 0x1 | I2C1
2687  * [10] | RW | 0x1 | I2C2
2688  * [11] | RW | 0x1 | I2C3
2689  * [12] | RW | 0x1 | I2C4
2690  * [15:13] | ??? | 0x7 | *UNDEFINED*
2691  * [16] | RW | 0x1 | UART0
2692  * [17] | RW | 0x1 | UART1
2693  * [23:18] | ??? | 0x3f | *UNDEFINED*
2694  * [24] | RW | 0x1 | GPIO0
2695  * [25] | RW | 0x1 | GPIO1
2696  * [31:26] | ??? | 0x3f | *UNDEFINED*
2697  *
2698  */
2699 /*
2700  * Field : Watch Dog0 - watchdog0
2701  *
2702  * Resets Watchdog 0
2703  *
2704  * Field Access Macros:
2705  *
2706  */
2707 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field. */
2708 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_LSB 0
2709 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field. */
2710 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_MSB 0
2711 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field. */
2712 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_WIDTH 1
2713 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field value. */
2714 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_SET_MSK 0x00000001
2715 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field value. */
2716 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_CLR_MSK 0xfffffffe
2717 /* The reset value of the ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field. */
2718 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_RESET 0x1
2719 /* Extracts the ALT_RSTMGR_PER1MODRST_WATCHDOG0 field value from a register. */
2720 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_GET(value) (((value) & 0x00000001) >> 0)
2721 /* Produces a ALT_RSTMGR_PER1MODRST_WATCHDOG0 register field value suitable for setting the register. */
2722 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_SET(value) (((value) << 0) & 0x00000001)
2723 
2724 /*
2725  * Field : Watch Dog1 - watchdog1
2726  *
2727  * Resets Watchdog 1
2728  *
2729  * Field Access Macros:
2730  *
2731  */
2732 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field. */
2733 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_LSB 1
2734 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field. */
2735 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_MSB 1
2736 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field. */
2737 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_WIDTH 1
2738 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field value. */
2739 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_SET_MSK 0x00000002
2740 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field value. */
2741 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_CLR_MSK 0xfffffffd
2742 /* The reset value of the ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field. */
2743 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_RESET 0x1
2744 /* Extracts the ALT_RSTMGR_PER1MODRST_WATCHDOG1 field value from a register. */
2745 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_GET(value) (((value) & 0x00000002) >> 1)
2746 /* Produces a ALT_RSTMGR_PER1MODRST_WATCHDOG1 register field value suitable for setting the register. */
2747 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_SET(value) (((value) << 1) & 0x00000002)
2748 
2749 /*
2750  * Field : Watch Dog2 - watchdog2
2751  *
2752  * Resets Watchdog 2
2753  *
2754  * Field Access Macros:
2755  *
2756  */
2757 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field. */
2758 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_LSB 2
2759 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field. */
2760 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_MSB 2
2761 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field. */
2762 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_WIDTH 1
2763 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field value. */
2764 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_SET_MSK 0x00000004
2765 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field value. */
2766 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_CLR_MSK 0xfffffffb
2767 /* The reset value of the ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field. */
2768 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_RESET 0x1
2769 /* Extracts the ALT_RSTMGR_PER1MODRST_WATCHDOG2 field value from a register. */
2770 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_GET(value) (((value) & 0x00000004) >> 2)
2771 /* Produces a ALT_RSTMGR_PER1MODRST_WATCHDOG2 register field value suitable for setting the register. */
2772 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_SET(value) (((value) << 2) & 0x00000004)
2773 
2774 /*
2775  * Field : Watch Dog3 - watchdog3
2776  *
2777  * Resets Watchdog 3
2778  *
2779  * Field Access Macros:
2780  *
2781  */
2782 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field. */
2783 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_LSB 3
2784 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field. */
2785 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_MSB 3
2786 /* The width in bits of the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field. */
2787 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_WIDTH 1
2788 /* The mask used to set the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field value. */
2789 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_SET_MSK 0x00000008
2790 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field value. */
2791 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_CLR_MSK 0xfffffff7
2792 /* The reset value of the ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field. */
2793 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_RESET 0x1
2794 /* Extracts the ALT_RSTMGR_PER1MODRST_WATCHDOG3 field value from a register. */
2795 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_GET(value) (((value) & 0x00000008) >> 3)
2796 /* Produces a ALT_RSTMGR_PER1MODRST_WATCHDOG3 register field value suitable for setting the register. */
2797 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_SET(value) (((value) << 3) & 0x00000008)
2798 
2799 /*
2800  * Field : l4systimer0 - l4systimer0
2801  *
2802  * Resets l4sys_timer0
2803  *
2804  * Field Access Macros:
2805  *
2806  */
2807 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field. */
2808 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_LSB 4
2809 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field. */
2810 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_MSB 4
2811 /* The width in bits of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field. */
2812 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_WIDTH 1
2813 /* The mask used to set the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field value. */
2814 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_SET_MSK 0x00000010
2815 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field value. */
2816 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_CLR_MSK 0xffffffef
2817 /* The reset value of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field. */
2818 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_RESET 0x1
2819 /* Extracts the ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 field value from a register. */
2820 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_GET(value) (((value) & 0x00000010) >> 4)
2821 /* Produces a ALT_RSTMGR_PER1MODRST_L4SYSTIMER0 register field value suitable for setting the register. */
2822 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_SET(value) (((value) << 4) & 0x00000010)
2823 
2824 /*
2825  * Field : l4sys_timer1 - l4systimer1
2826  *
2827  * Resets l4sys_timer1
2828  *
2829  * Field Access Macros:
2830  *
2831  */
2832 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field. */
2833 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_LSB 5
2834 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field. */
2835 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_MSB 5
2836 /* The width in bits of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field. */
2837 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_WIDTH 1
2838 /* The mask used to set the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field value. */
2839 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_SET_MSK 0x00000020
2840 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field value. */
2841 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_CLR_MSK 0xffffffdf
2842 /* The reset value of the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field. */
2843 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_RESET 0x1
2844 /* Extracts the ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 field value from a register. */
2845 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_GET(value) (((value) & 0x00000020) >> 5)
2846 /* Produces a ALT_RSTMGR_PER1MODRST_L4SYSTIMER1 register field value suitable for setting the register. */
2847 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_SET(value) (((value) << 5) & 0x00000020)
2848 
2849 /*
2850  * Field : SP Timer 0 - sptimer0
2851  *
2852  * Resets SP timer 0 connected to L4
2853  *
2854  * Field Access Macros:
2855  *
2856  */
2857 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field. */
2858 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_LSB 6
2859 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field. */
2860 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_MSB 6
2861 /* The width in bits of the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field. */
2862 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_WIDTH 1
2863 /* The mask used to set the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field value. */
2864 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_SET_MSK 0x00000040
2865 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field value. */
2866 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_CLR_MSK 0xffffffbf
2867 /* The reset value of the ALT_RSTMGR_PER1MODRST_SPTIMER0 register field. */
2868 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_RESET 0x1
2869 /* Extracts the ALT_RSTMGR_PER1MODRST_SPTIMER0 field value from a register. */
2870 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_GET(value) (((value) & 0x00000040) >> 6)
2871 /* Produces a ALT_RSTMGR_PER1MODRST_SPTIMER0 register field value suitable for setting the register. */
2872 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_SET(value) (((value) << 6) & 0x00000040)
2873 
2874 /*
2875  * Field : SP Timer 1 - sptimer1
2876  *
2877  * Resets SP timer 1 connected to L4
2878  *
2879  * Field Access Macros:
2880  *
2881  */
2882 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field. */
2883 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_LSB 7
2884 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field. */
2885 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_MSB 7
2886 /* The width in bits of the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field. */
2887 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_WIDTH 1
2888 /* The mask used to set the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field value. */
2889 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_SET_MSK 0x00000080
2890 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field value. */
2891 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_CLR_MSK 0xffffff7f
2892 /* The reset value of the ALT_RSTMGR_PER1MODRST_SPTIMER1 register field. */
2893 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_RESET 0x1
2894 /* Extracts the ALT_RSTMGR_PER1MODRST_SPTIMER1 field value from a register. */
2895 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_GET(value) (((value) & 0x00000080) >> 7)
2896 /* Produces a ALT_RSTMGR_PER1MODRST_SPTIMER1 register field value suitable for setting the register. */
2897 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_SET(value) (((value) << 7) & 0x00000080)
2898 
2899 /*
2900  * Field : I2C0 - i2c0
2901  *
2902  * Resets I2C0 controller
2903  *
2904  * Field Access Macros:
2905  *
2906  */
2907 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
2908 #define ALT_RSTMGR_PER1MODRST_I2C0_LSB 8
2909 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
2910 #define ALT_RSTMGR_PER1MODRST_I2C0_MSB 8
2911 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
2912 #define ALT_RSTMGR_PER1MODRST_I2C0_WIDTH 1
2913 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C0 register field value. */
2914 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
2915 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C0 register field value. */
2916 #define ALT_RSTMGR_PER1MODRST_I2C0_CLR_MSK 0xfffffeff
2917 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C0 register field. */
2918 #define ALT_RSTMGR_PER1MODRST_I2C0_RESET 0x1
2919 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C0 field value from a register. */
2920 #define ALT_RSTMGR_PER1MODRST_I2C0_GET(value) (((value) & 0x00000100) >> 8)
2921 /* Produces a ALT_RSTMGR_PER1MODRST_I2C0 register field value suitable for setting the register. */
2922 #define ALT_RSTMGR_PER1MODRST_I2C0_SET(value) (((value) << 8) & 0x00000100)
2923 
2924 /*
2925  * Field : I2C1 - i2c1
2926  *
2927  * Resets I2C1 controller
2928  *
2929  * Field Access Macros:
2930  *
2931  */
2932 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
2933 #define ALT_RSTMGR_PER1MODRST_I2C1_LSB 9
2934 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
2935 #define ALT_RSTMGR_PER1MODRST_I2C1_MSB 9
2936 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
2937 #define ALT_RSTMGR_PER1MODRST_I2C1_WIDTH 1
2938 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C1 register field value. */
2939 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
2940 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C1 register field value. */
2941 #define ALT_RSTMGR_PER1MODRST_I2C1_CLR_MSK 0xfffffdff
2942 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C1 register field. */
2943 #define ALT_RSTMGR_PER1MODRST_I2C1_RESET 0x1
2944 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C1 field value from a register. */
2945 #define ALT_RSTMGR_PER1MODRST_I2C1_GET(value) (((value) & 0x00000200) >> 9)
2946 /* Produces a ALT_RSTMGR_PER1MODRST_I2C1 register field value suitable for setting the register. */
2947 #define ALT_RSTMGR_PER1MODRST_I2C1_SET(value) (((value) << 9) & 0x00000200)
2948 
2949 /*
2950  * Field : I2C2 - i2c2
2951  *
2952  * Resets I2C2 controller
2953  *
2954  * Field Access Macros:
2955  *
2956  */
2957 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
2958 #define ALT_RSTMGR_PER1MODRST_I2C2_LSB 10
2959 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
2960 #define ALT_RSTMGR_PER1MODRST_I2C2_MSB 10
2961 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
2962 #define ALT_RSTMGR_PER1MODRST_I2C2_WIDTH 1
2963 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C2 register field value. */
2964 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
2965 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C2 register field value. */
2966 #define ALT_RSTMGR_PER1MODRST_I2C2_CLR_MSK 0xfffffbff
2967 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C2 register field. */
2968 #define ALT_RSTMGR_PER1MODRST_I2C2_RESET 0x1
2969 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C2 field value from a register. */
2970 #define ALT_RSTMGR_PER1MODRST_I2C2_GET(value) (((value) & 0x00000400) >> 10)
2971 /* Produces a ALT_RSTMGR_PER1MODRST_I2C2 register field value suitable for setting the register. */
2972 #define ALT_RSTMGR_PER1MODRST_I2C2_SET(value) (((value) << 10) & 0x00000400)
2973 
2974 /*
2975  * Field : I2C3 - i2c3
2976  *
2977  * Resets I2C3 controller
2978  *
2979  * Field Access Macros:
2980  *
2981  */
2982 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
2983 #define ALT_RSTMGR_PER1MODRST_I2C3_LSB 11
2984 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
2985 #define ALT_RSTMGR_PER1MODRST_I2C3_MSB 11
2986 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
2987 #define ALT_RSTMGR_PER1MODRST_I2C3_WIDTH 1
2988 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C3 register field value. */
2989 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
2990 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C3 register field value. */
2991 #define ALT_RSTMGR_PER1MODRST_I2C3_CLR_MSK 0xfffff7ff
2992 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C3 register field. */
2993 #define ALT_RSTMGR_PER1MODRST_I2C3_RESET 0x1
2994 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C3 field value from a register. */
2995 #define ALT_RSTMGR_PER1MODRST_I2C3_GET(value) (((value) & 0x00000800) >> 11)
2996 /* Produces a ALT_RSTMGR_PER1MODRST_I2C3 register field value suitable for setting the register. */
2997 #define ALT_RSTMGR_PER1MODRST_I2C3_SET(value) (((value) << 11) & 0x00000800)
2998 
2999 /*
3000  * Field : I2C4 - i2c4
3001  *
3002  * Resets I2C4 controller
3003  *
3004  * Field Access Macros:
3005  *
3006  */
3007 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3008 #define ALT_RSTMGR_PER1MODRST_I2C4_LSB 12
3009 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3010 #define ALT_RSTMGR_PER1MODRST_I2C4_MSB 12
3011 /* The width in bits of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3012 #define ALT_RSTMGR_PER1MODRST_I2C4_WIDTH 1
3013 /* The mask used to set the ALT_RSTMGR_PER1MODRST_I2C4 register field value. */
3014 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
3015 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_I2C4 register field value. */
3016 #define ALT_RSTMGR_PER1MODRST_I2C4_CLR_MSK 0xffffefff
3017 /* The reset value of the ALT_RSTMGR_PER1MODRST_I2C4 register field. */
3018 #define ALT_RSTMGR_PER1MODRST_I2C4_RESET 0x1
3019 /* Extracts the ALT_RSTMGR_PER1MODRST_I2C4 field value from a register. */
3020 #define ALT_RSTMGR_PER1MODRST_I2C4_GET(value) (((value) & 0x00001000) >> 12)
3021 /* Produces a ALT_RSTMGR_PER1MODRST_I2C4 register field value suitable for setting the register. */
3022 #define ALT_RSTMGR_PER1MODRST_I2C4_SET(value) (((value) << 12) & 0x00001000)
3023 
3024 /*
3025  * Field : UART0 - uart0
3026  *
3027  * Resets UART0
3028  *
3029  * Field Access Macros:
3030  *
3031  */
3032 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3033 #define ALT_RSTMGR_PER1MODRST_UART0_LSB 16
3034 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3035 #define ALT_RSTMGR_PER1MODRST_UART0_MSB 16
3036 /* The width in bits of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3037 #define ALT_RSTMGR_PER1MODRST_UART0_WIDTH 1
3038 /* The mask used to set the ALT_RSTMGR_PER1MODRST_UART0 register field value. */
3039 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
3040 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_UART0 register field value. */
3041 #define ALT_RSTMGR_PER1MODRST_UART0_CLR_MSK 0xfffeffff
3042 /* The reset value of the ALT_RSTMGR_PER1MODRST_UART0 register field. */
3043 #define ALT_RSTMGR_PER1MODRST_UART0_RESET 0x1
3044 /* Extracts the ALT_RSTMGR_PER1MODRST_UART0 field value from a register. */
3045 #define ALT_RSTMGR_PER1MODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
3046 /* Produces a ALT_RSTMGR_PER1MODRST_UART0 register field value suitable for setting the register. */
3047 #define ALT_RSTMGR_PER1MODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
3048 
3049 /*
3050  * Field : UART1 - uart1
3051  *
3052  * Resets UART1
3053  *
3054  * Field Access Macros:
3055  *
3056  */
3057 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3058 #define ALT_RSTMGR_PER1MODRST_UART1_LSB 17
3059 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3060 #define ALT_RSTMGR_PER1MODRST_UART1_MSB 17
3061 /* The width in bits of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3062 #define ALT_RSTMGR_PER1MODRST_UART1_WIDTH 1
3063 /* The mask used to set the ALT_RSTMGR_PER1MODRST_UART1 register field value. */
3064 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
3065 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_UART1 register field value. */
3066 #define ALT_RSTMGR_PER1MODRST_UART1_CLR_MSK 0xfffdffff
3067 /* The reset value of the ALT_RSTMGR_PER1MODRST_UART1 register field. */
3068 #define ALT_RSTMGR_PER1MODRST_UART1_RESET 0x1
3069 /* Extracts the ALT_RSTMGR_PER1MODRST_UART1 field value from a register. */
3070 #define ALT_RSTMGR_PER1MODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
3071 /* Produces a ALT_RSTMGR_PER1MODRST_UART1 register field value suitable for setting the register. */
3072 #define ALT_RSTMGR_PER1MODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
3073 
3074 /*
3075  * Field : GPIO0 - gpio0
3076  *
3077  * Resets GPIO0
3078  *
3079  * Field Access Macros:
3080  *
3081  */
3082 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3083 #define ALT_RSTMGR_PER1MODRST_GPIO0_LSB 24
3084 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3085 #define ALT_RSTMGR_PER1MODRST_GPIO0_MSB 24
3086 /* The width in bits of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3087 #define ALT_RSTMGR_PER1MODRST_GPIO0_WIDTH 1
3088 /* The mask used to set the ALT_RSTMGR_PER1MODRST_GPIO0 register field value. */
3089 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
3090 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_GPIO0 register field value. */
3091 #define ALT_RSTMGR_PER1MODRST_GPIO0_CLR_MSK 0xfeffffff
3092 /* The reset value of the ALT_RSTMGR_PER1MODRST_GPIO0 register field. */
3093 #define ALT_RSTMGR_PER1MODRST_GPIO0_RESET 0x1
3094 /* Extracts the ALT_RSTMGR_PER1MODRST_GPIO0 field value from a register. */
3095 #define ALT_RSTMGR_PER1MODRST_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
3096 /* Produces a ALT_RSTMGR_PER1MODRST_GPIO0 register field value suitable for setting the register. */
3097 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET(value) (((value) << 24) & 0x01000000)
3098 
3099 /*
3100  * Field : GPIO1 - gpio1
3101  *
3102  * Resets GPIO1
3103  *
3104  * Field Access Macros:
3105  *
3106  */
3107 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3108 #define ALT_RSTMGR_PER1MODRST_GPIO1_LSB 25
3109 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3110 #define ALT_RSTMGR_PER1MODRST_GPIO1_MSB 25
3111 /* The width in bits of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3112 #define ALT_RSTMGR_PER1MODRST_GPIO1_WIDTH 1
3113 /* The mask used to set the ALT_RSTMGR_PER1MODRST_GPIO1 register field value. */
3114 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
3115 /* The mask used to clear the ALT_RSTMGR_PER1MODRST_GPIO1 register field value. */
3116 #define ALT_RSTMGR_PER1MODRST_GPIO1_CLR_MSK 0xfdffffff
3117 /* The reset value of the ALT_RSTMGR_PER1MODRST_GPIO1 register field. */
3118 #define ALT_RSTMGR_PER1MODRST_GPIO1_RESET 0x1
3119 /* Extracts the ALT_RSTMGR_PER1MODRST_GPIO1 field value from a register. */
3120 #define ALT_RSTMGR_PER1MODRST_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
3121 /* Produces a ALT_RSTMGR_PER1MODRST_GPIO1 register field value suitable for setting the register. */
3122 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET(value) (((value) << 25) & 0x02000000)
3123 
3124 #ifndef __ASSEMBLY__
3125 /*
3126  * WARNING: The C register and register group struct declarations are provided for
3127  * convenience and illustrative purposes. They should, however, be used with
3128  * caution as the C language standard provides no guarantees about the alignment or
3129  * atomicity of device memory accesses. The recommended practice for coding device
3130  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3131  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3132  * alt_write_dword() functions for 64 bit registers.
3133  *
3134  * The struct declaration for register ALT_RSTMGR_PER1MODRST.
3135  */
3136 struct ALT_RSTMGR_PER1MODRST_s
3137 {
3138  volatile uint32_t watchdog0 : 1; /* Watch Dog0 */
3139  volatile uint32_t watchdog1 : 1; /* Watch Dog1 */
3140  volatile uint32_t watchdog2 : 1; /* Watch Dog2 */
3141  volatile uint32_t watchdog3 : 1; /* Watch Dog3 */
3142  volatile uint32_t l4systimer0 : 1; /* l4systimer0 */
3143  volatile uint32_t l4systimer1 : 1; /* l4sys_timer1 */
3144  volatile uint32_t sptimer0 : 1; /* SP Timer 0 */
3145  volatile uint32_t sptimer1 : 1; /* SP Timer 1 */
3146  volatile uint32_t i2c0 : 1; /* I2C0 */
3147  volatile uint32_t i2c1 : 1; /* I2C1 */
3148  volatile uint32_t i2c2 : 1; /* I2C2 */
3149  volatile uint32_t i2c3 : 1; /* I2C3 */
3150  volatile uint32_t i2c4 : 1; /* I2C4 */
3151  uint32_t : 3; /* *UNDEFINED* */
3152  volatile uint32_t uart0 : 1; /* UART0 */
3153  volatile uint32_t uart1 : 1; /* UART1 */
3154  uint32_t : 6; /* *UNDEFINED* */
3155  volatile uint32_t gpio0 : 1; /* GPIO0 */
3156  volatile uint32_t gpio1 : 1; /* GPIO1 */
3157  uint32_t : 6; /* *UNDEFINED* */
3158 };
3159 
3160 /* The typedef declaration for register ALT_RSTMGR_PER1MODRST. */
3161 typedef struct ALT_RSTMGR_PER1MODRST_s ALT_RSTMGR_PER1MODRST_t;
3162 #endif /* __ASSEMBLY__ */
3163 
3164 /* The reset value of the ALT_RSTMGR_PER1MODRST register. */
3165 #define ALT_RSTMGR_PER1MODRST_RESET 0xffffffff
3166 /* The byte offset of the ALT_RSTMGR_PER1MODRST register from the beginning of the component. */
3167 #define ALT_RSTMGR_PER1MODRST_OFST 0x28
3168 
3169 /*
3170  * Register : Bridge Reset Register - brgmodrst
3171  *
3172  * The BRGMODRST register is used by software to control the bridge module resets.
3173  * Software explicitly asserts and de-asserts module reset signals by writing bits
3174  * in the appropriate *MODRST register. It is up to software to ensure module reset
3175  * signals are asserted for the appropriate length of time and are de-asserted in
3176  * the correct order. It is also up to software to not assert a module reset signal
3177  * that would prevent software from de-asserting the module reset signal.
3178  *
3179  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
3180  * assert the module reset signal.
3181  *
3182  * All fields are reset by a cold reset. All fields are also reset by a warm reset
3183  * if not masked by the corresponding BRGWARMMASK field.
3184  *
3185  * The reset value of all fields is 1. This holds the corresponding module in reset
3186  * until software is ready to release the module from reset by writing 0 to its
3187  * field.
3188  *
3189  * Register Layout
3190  *
3191  * Bits | Access | Reset | Description
3192  * :-------|:-------|:----------|:---------------------
3193  * [0] | RW | 0x1 | SOC2FPGA Bridge
3194  * [1] | RW | 0x1 | LWHPS2FPGA Bridge
3195  * [2] | RW | 0x1 | FPGA2SOC Bridge
3196  * [3] | RW | 0x1 | F2S SDRAM0 Bridge
3197  * [4] | RW | 0x1 | F2S SDRAM1 Bridge
3198  * [5] | RW | 0x1 | F2S SDRAM2 Bridge
3199  * [6] | RW | 0x1 | Resets DDR Scheduler
3200  * [31:7] | ??? | 0x1ffffff | *UNDEFINED*
3201  *
3202  */
3203 /*
3204  * Field : SOC2FPGA Bridge - soc2fpga
3205  *
3206  * Resets SOC2FPGA Bridge.
3207  *
3208  * Field Access Macros:
3209  *
3210  */
3211 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field. */
3212 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_LSB 0
3213 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field. */
3214 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_MSB 0
3215 /* The width in bits of the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field. */
3216 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_WIDTH 1
3217 /* The mask used to set the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field value. */
3218 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_SET_MSK 0x00000001
3219 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field value. */
3220 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_CLR_MSK 0xfffffffe
3221 /* The reset value of the ALT_RSTMGR_BRGMODRST_SOC2FPGA register field. */
3222 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_RESET 0x1
3223 /* Extracts the ALT_RSTMGR_BRGMODRST_SOC2FPGA field value from a register. */
3224 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
3225 /* Produces a ALT_RSTMGR_BRGMODRST_SOC2FPGA register field value suitable for setting the register. */
3226 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
3227 
3228 /*
3229  * Field : LWHPS2FPGA Bridge - lwhps2fpga
3230  *
3231  * Resets LWHPS2FPGA Bridge.
3232  *
3233  * Field Access Macros:
3234  *
3235  */
3236 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field. */
3237 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_LSB 1
3238 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field. */
3239 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_MSB 1
3240 /* The width in bits of the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field. */
3241 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_WIDTH 1
3242 /* The mask used to set the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field value. */
3243 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_SET_MSK 0x00000002
3244 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field value. */
3245 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_CLR_MSK 0xfffffffd
3246 /* The reset value of the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field. */
3247 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_RESET 0x1
3248 /* Extracts the ALT_RSTMGR_BRGMODRST_LWHPS2FPGA field value from a register. */
3249 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_GET(value) (((value) & 0x00000002) >> 1)
3250 /* Produces a ALT_RSTMGR_BRGMODRST_LWHPS2FPGA register field value suitable for setting the register. */
3251 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_SET(value) (((value) << 1) & 0x00000002)
3252 
3253 /*
3254  * Field : FPGA2SOC Bridge - fpga2soc
3255  *
3256  * Resets FPGA2SOC Bridge.
3257  *
3258  * Field Access Macros:
3259  *
3260  */
3261 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field. */
3262 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_LSB 2
3263 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field. */
3264 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_MSB 2
3265 /* The width in bits of the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field. */
3266 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_WIDTH 1
3267 /* The mask used to set the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field value. */
3268 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_SET_MSK 0x00000004
3269 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field value. */
3270 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_CLR_MSK 0xfffffffb
3271 /* The reset value of the ALT_RSTMGR_BRGMODRST_FPGA2SOC register field. */
3272 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_RESET 0x1
3273 /* Extracts the ALT_RSTMGR_BRGMODRST_FPGA2SOC field value from a register. */
3274 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_GET(value) (((value) & 0x00000004) >> 2)
3275 /* Produces a ALT_RSTMGR_BRGMODRST_FPGA2SOC register field value suitable for setting the register. */
3276 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_SET(value) (((value) << 2) & 0x00000004)
3277 
3278 /*
3279  * Field : F2S SDRAM0 Bridge - f2ssdram0
3280  *
3281  * Resets F2S_SDRAM0 Bridge.
3282  *
3283  * Field Access Macros:
3284  *
3285  */
3286 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3287 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_LSB 3
3288 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3289 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_MSB 3
3290 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3291 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_WIDTH 1
3292 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value. */
3293 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
3294 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value. */
3295 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_CLR_MSK 0xfffffff7
3296 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field. */
3297 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_RESET 0x1
3298 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM0 field value from a register. */
3299 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3300 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM0 register field value suitable for setting the register. */
3301 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3302 
3303 /*
3304  * Field : F2S SDRAM1 Bridge - f2ssdram1
3305  *
3306  * Resets F2S_SDRAM1 Bridge.
3307  *
3308  * Field Access Macros:
3309  *
3310  */
3311 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3312 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_LSB 4
3313 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3314 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_MSB 4
3315 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3316 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_WIDTH 1
3317 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value. */
3318 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
3319 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value. */
3320 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_CLR_MSK 0xffffffef
3321 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field. */
3322 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_RESET 0x1
3323 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM1 field value from a register. */
3324 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3325 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM1 register field value suitable for setting the register. */
3326 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3327 
3328 /*
3329  * Field : F2S SDRAM2 Bridge - f2ssdram2
3330  *
3331  * Resets F2S_SDRAM2 Bridge.
3332  *
3333  * Field Access Macros:
3334  *
3335  */
3336 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3337 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_LSB 5
3338 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3339 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_MSB 5
3340 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3341 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_WIDTH 1
3342 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value. */
3343 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
3344 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value. */
3345 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_CLR_MSK 0xffffffdf
3346 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field. */
3347 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_RESET 0x1
3348 /* Extracts the ALT_RSTMGR_BRGMODRST_F2SSDRAM2 field value from a register. */
3349 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3350 /* Produces a ALT_RSTMGR_BRGMODRST_F2SSDRAM2 register field value suitable for setting the register. */
3351 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3352 
3353 /*
3354  * Field : Resets DDR Scheduler - ddrsch
3355  *
3356  * Resets logic in the DDR Scheduler in the NOC.
3357  *
3358  * Field Access Macros:
3359  *
3360  */
3361 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3362 #define ALT_RSTMGR_BRGMODRST_DDRSCH_LSB 6
3363 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3364 #define ALT_RSTMGR_BRGMODRST_DDRSCH_MSB 6
3365 /* The width in bits of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3366 #define ALT_RSTMGR_BRGMODRST_DDRSCH_WIDTH 1
3367 /* The mask used to set the ALT_RSTMGR_BRGMODRST_DDRSCH register field value. */
3368 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
3369 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_DDRSCH register field value. */
3370 #define ALT_RSTMGR_BRGMODRST_DDRSCH_CLR_MSK 0xffffffbf
3371 /* The reset value of the ALT_RSTMGR_BRGMODRST_DDRSCH register field. */
3372 #define ALT_RSTMGR_BRGMODRST_DDRSCH_RESET 0x1
3373 /* Extracts the ALT_RSTMGR_BRGMODRST_DDRSCH field value from a register. */
3374 #define ALT_RSTMGR_BRGMODRST_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3375 /* Produces a ALT_RSTMGR_BRGMODRST_DDRSCH register field value suitable for setting the register. */
3376 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3377 
3378 #ifndef __ASSEMBLY__
3379 /*
3380  * WARNING: The C register and register group struct declarations are provided for
3381  * convenience and illustrative purposes. They should, however, be used with
3382  * caution as the C language standard provides no guarantees about the alignment or
3383  * atomicity of device memory accesses. The recommended practice for coding device
3384  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3385  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3386  * alt_write_dword() functions for 64 bit registers.
3387  *
3388  * The struct declaration for register ALT_RSTMGR_BRGMODRST.
3389  */
3390 struct ALT_RSTMGR_BRGMODRST_s
3391 {
3392  volatile uint32_t soc2fpga : 1; /* SOC2FPGA Bridge */
3393  volatile uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */
3394  volatile uint32_t fpga2soc : 1; /* FPGA2SOC Bridge */
3395  volatile uint32_t f2ssdram0 : 1; /* F2S SDRAM0 Bridge */
3396  volatile uint32_t f2ssdram1 : 1; /* F2S SDRAM1 Bridge */
3397  volatile uint32_t f2ssdram2 : 1; /* F2S SDRAM2 Bridge */
3398  volatile uint32_t ddrsch : 1; /* Resets DDR Scheduler */
3399  uint32_t : 25; /* *UNDEFINED* */
3400 };
3401 
3402 /* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
3403 typedef struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
3404 #endif /* __ASSEMBLY__ */
3405 
3406 /* The reset value of the ALT_RSTMGR_BRGMODRST register. */
3407 #define ALT_RSTMGR_BRGMODRST_RESET 0xffffffff
3408 /* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
3409 #define ALT_RSTMGR_BRGMODRST_OFST 0x2c
3410 
3411 /*
3412  * Register : COLD Module Reset Register - coldmodrst
3413  *
3414  * The COLDMODRST register is used by software to trigger module resets. Writing 1
3415  * to any of these fields will cause the L2 or CPU POR reset signal to be asserted
3416  * if that module is in WFI mode. The Reset Manager hardware will bring the module
3417  * back out of reset after the appropriate amount of time.
3418  *
3419  * All fields are only reset by a cold reset.
3420  *
3421  * Register Layout
3422  *
3423  * Bits | Access | Reset | Description
3424  * :-------|:-------|:------|:-----------------------------------------
3425  * [0] | RW | 0x0 | Resets CPUPOR0
3426  * [1] | RW | 0x0 | Resets CPUPOR1
3427  * [2] | RW | 0x0 | Resets CPUPOR2
3428  * [3] | RW | 0x0 | Resets CPUPOR3
3429  * [7:4] | ??? | 0x0 | *UNDEFINED*
3430  * [8] | RW | 0x0 | Resets L2 shared memory system contoller
3431  * [31:9] | ??? | 0x0 | *UNDEFINED*
3432  *
3433  */
3434 /*
3435  * Field : Resets CPUPOR0 - cpupor0
3436  *
3437  * Resets ncpuporreset port of CPU0.
3438  *
3439  * Field Access Macros:
3440  *
3441  */
3442 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field. */
3443 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_LSB 0
3444 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field. */
3445 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_MSB 0
3446 /* The width in bits of the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field. */
3447 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_WIDTH 1
3448 /* The mask used to set the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field value. */
3449 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_SET_MSK 0x00000001
3450 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field value. */
3451 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_CLR_MSK 0xfffffffe
3452 /* The reset value of the ALT_RSTMGR_COLDMODRST_CPUPOR0 register field. */
3453 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_RESET 0x0
3454 /* Extracts the ALT_RSTMGR_COLDMODRST_CPUPOR0 field value from a register. */
3455 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_GET(value) (((value) & 0x00000001) >> 0)
3456 /* Produces a ALT_RSTMGR_COLDMODRST_CPUPOR0 register field value suitable for setting the register. */
3457 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_SET(value) (((value) << 0) & 0x00000001)
3458 
3459 /*
3460  * Field : Resets CPUPOR1 - cpupor1
3461  *
3462  * Resets ncpuporreset port of CPU1.
3463  *
3464  * Field Access Macros:
3465  *
3466  */
3467 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field. */
3468 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_LSB 1
3469 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field. */
3470 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_MSB 1
3471 /* The width in bits of the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field. */
3472 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_WIDTH 1
3473 /* The mask used to set the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field value. */
3474 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_SET_MSK 0x00000002
3475 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field value. */
3476 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_CLR_MSK 0xfffffffd
3477 /* The reset value of the ALT_RSTMGR_COLDMODRST_CPUPOR1 register field. */
3478 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_RESET 0x0
3479 /* Extracts the ALT_RSTMGR_COLDMODRST_CPUPOR1 field value from a register. */
3480 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_GET(value) (((value) & 0x00000002) >> 1)
3481 /* Produces a ALT_RSTMGR_COLDMODRST_CPUPOR1 register field value suitable for setting the register. */
3482 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_SET(value) (((value) << 1) & 0x00000002)
3483 
3484 /*
3485  * Field : Resets CPUPOR2 - cpupor2
3486  *
3487  * Resets ncpuporreset port of CPU2.
3488  *
3489  * Field Access Macros:
3490  *
3491  */
3492 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field. */
3493 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_LSB 2
3494 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field. */
3495 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_MSB 2
3496 /* The width in bits of the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field. */
3497 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_WIDTH 1
3498 /* The mask used to set the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field value. */
3499 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_SET_MSK 0x00000004
3500 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field value. */
3501 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_CLR_MSK 0xfffffffb
3502 /* The reset value of the ALT_RSTMGR_COLDMODRST_CPUPOR2 register field. */
3503 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_RESET 0x0
3504 /* Extracts the ALT_RSTMGR_COLDMODRST_CPUPOR2 field value from a register. */
3505 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_GET(value) (((value) & 0x00000004) >> 2)
3506 /* Produces a ALT_RSTMGR_COLDMODRST_CPUPOR2 register field value suitable for setting the register. */
3507 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_SET(value) (((value) << 2) & 0x00000004)
3508 
3509 /*
3510  * Field : Resets CPUPOR3 - cpupor3
3511  *
3512  * Resets ncpuporreset port of CPU3.
3513  *
3514  * Field Access Macros:
3515  *
3516  */
3517 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field. */
3518 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_LSB 3
3519 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field. */
3520 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_MSB 3
3521 /* The width in bits of the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field. */
3522 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_WIDTH 1
3523 /* The mask used to set the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field value. */
3524 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_SET_MSK 0x00000008
3525 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field value. */
3526 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_CLR_MSK 0xfffffff7
3527 /* The reset value of the ALT_RSTMGR_COLDMODRST_CPUPOR3 register field. */
3528 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_RESET 0x0
3529 /* Extracts the ALT_RSTMGR_COLDMODRST_CPUPOR3 field value from a register. */
3530 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_GET(value) (((value) & 0x00000008) >> 3)
3531 /* Produces a ALT_RSTMGR_COLDMODRST_CPUPOR3 register field value suitable for setting the register. */
3532 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_SET(value) (((value) << 3) & 0x00000008)
3533 
3534 /*
3535  * Field : Resets L2 shared memory system contoller - l2
3536  *
3537  * Resets L2 shared memory system contoller.
3538  *
3539  * Field Access Macros:
3540  *
3541  */
3542 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COLDMODRST_L2 register field. */
3543 #define ALT_RSTMGR_COLDMODRST_L2_LSB 8
3544 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COLDMODRST_L2 register field. */
3545 #define ALT_RSTMGR_COLDMODRST_L2_MSB 8
3546 /* The width in bits of the ALT_RSTMGR_COLDMODRST_L2 register field. */
3547 #define ALT_RSTMGR_COLDMODRST_L2_WIDTH 1
3548 /* The mask used to set the ALT_RSTMGR_COLDMODRST_L2 register field value. */
3549 #define ALT_RSTMGR_COLDMODRST_L2_SET_MSK 0x00000100
3550 /* The mask used to clear the ALT_RSTMGR_COLDMODRST_L2 register field value. */
3551 #define ALT_RSTMGR_COLDMODRST_L2_CLR_MSK 0xfffffeff
3552 /* The reset value of the ALT_RSTMGR_COLDMODRST_L2 register field. */
3553 #define ALT_RSTMGR_COLDMODRST_L2_RESET 0x0
3554 /* Extracts the ALT_RSTMGR_COLDMODRST_L2 field value from a register. */
3555 #define ALT_RSTMGR_COLDMODRST_L2_GET(value) (((value) & 0x00000100) >> 8)
3556 /* Produces a ALT_RSTMGR_COLDMODRST_L2 register field value suitable for setting the register. */
3557 #define ALT_RSTMGR_COLDMODRST_L2_SET(value) (((value) << 8) & 0x00000100)
3558 
3559 #ifndef __ASSEMBLY__
3560 /*
3561  * WARNING: The C register and register group struct declarations are provided for
3562  * convenience and illustrative purposes. They should, however, be used with
3563  * caution as the C language standard provides no guarantees about the alignment or
3564  * atomicity of device memory accesses. The recommended practice for coding device
3565  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3566  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3567  * alt_write_dword() functions for 64 bit registers.
3568  *
3569  * The struct declaration for register ALT_RSTMGR_COLDMODRST.
3570  */
3571 struct ALT_RSTMGR_COLDMODRST_s
3572 {
3573  volatile uint32_t cpupor0 : 1; /* Resets CPUPOR0 */
3574  volatile uint32_t cpupor1 : 1; /* Resets CPUPOR1 */
3575  volatile uint32_t cpupor2 : 1; /* Resets CPUPOR2 */
3576  volatile uint32_t cpupor3 : 1; /* Resets CPUPOR3 */
3577  uint32_t : 4; /* *UNDEFINED* */
3578  volatile uint32_t l2 : 1; /* Resets L2 shared memory system contoller */
3579  uint32_t : 23; /* *UNDEFINED* */
3580 };
3581 
3582 /* The typedef declaration for register ALT_RSTMGR_COLDMODRST. */
3583 typedef struct ALT_RSTMGR_COLDMODRST_s ALT_RSTMGR_COLDMODRST_t;
3584 #endif /* __ASSEMBLY__ */
3585 
3586 /* The reset value of the ALT_RSTMGR_COLDMODRST register. */
3587 #define ALT_RSTMGR_COLDMODRST_RESET 0x00000000
3588 /* The byte offset of the ALT_RSTMGR_COLDMODRST register from the beginning of the component. */
3589 #define ALT_RSTMGR_COLDMODRST_OFST 0x34
3590 
3591 /*
3592  * Register : Debug Module Reset Register - dbgmodrst
3593  *
3594  * The DBGMODRST register is used by software to control module resets.
3595  *
3596  * When software writes the csdap_rst bit to 1, the RstMgr hardware will assert
3597  * both the csdap_rst and the dbg_rst resets, and then release just the dbg_rst
3598  * after 16 boot clock cycles . The csdap_rst will remain asserted until software
3599  * clears the csdap_rst bit.
3600  *
3601  * When software writes the dbg_rst bit to 1, the RstMgr hardware will assert both
3602  * the csdap_rst and the dbg_rst, and then release just the csdap_rst after 16 boot
3603  * clock cycles. The dbg_rst will remain asserted until software clears the dbg_rst
3604  * bit.
3605  *
3606  * When software writes 1 to both the cs_dap_rst and the dbg_rst, the RstMgr
3607  * hardware will assert both the cs_dap_rst and the dbg_rst, and then release both
3608  * the csdap_rst and dbg_rst after 16 boot clock cycles. Software does not need to
3609  * clear either bit.
3610  *
3611  * All fields are only reset by a cold reset.
3612  *
3613  * Note: It is recommended that software performs the handshake(debug_l3noc) by
3614  * using the corresponding bits of "hdsken" and "hdskreq" registers before
3615  * resetting dap or debug logic. SW should poll the "debug_l3noc_ack" bit and
3616  * implement its own timer. Only after the handshake is completed, SW should assert
3617  * these resets.
3618  *
3619  * Register Layout
3620  *
3621  * Bits | Access | Reset | Description
3622  * :-------|:-------|:------|:---------------------
3623  * [0] | RW | 0x0 | Resets Debug Domain
3624  * [1] | RW | 0x0 | Resets Coresight DAP
3625  * [31:2] | ??? | 0x0 | *UNDEFINED*
3626  *
3627  */
3628 /*
3629  * Field : Resets Debug Domain - dbg_rst
3630  *
3631  * Resets logic located in the debug domain.
3632  *
3633  * Field Access Macros:
3634  *
3635  */
3636 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_DBGMODRST_DBG_RST register field. */
3637 #define ALT_RSTMGR_DBGMODRST_DBG_RST_LSB 0
3638 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_DBGMODRST_DBG_RST register field. */
3639 #define ALT_RSTMGR_DBGMODRST_DBG_RST_MSB 0
3640 /* The width in bits of the ALT_RSTMGR_DBGMODRST_DBG_RST register field. */
3641 #define ALT_RSTMGR_DBGMODRST_DBG_RST_WIDTH 1
3642 /* The mask used to set the ALT_RSTMGR_DBGMODRST_DBG_RST register field value. */
3643 #define ALT_RSTMGR_DBGMODRST_DBG_RST_SET_MSK 0x00000001
3644 /* The mask used to clear the ALT_RSTMGR_DBGMODRST_DBG_RST register field value. */
3645 #define ALT_RSTMGR_DBGMODRST_DBG_RST_CLR_MSK 0xfffffffe
3646 /* The reset value of the ALT_RSTMGR_DBGMODRST_DBG_RST register field. */
3647 #define ALT_RSTMGR_DBGMODRST_DBG_RST_RESET 0x0
3648 /* Extracts the ALT_RSTMGR_DBGMODRST_DBG_RST field value from a register. */
3649 #define ALT_RSTMGR_DBGMODRST_DBG_RST_GET(value) (((value) & 0x00000001) >> 0)
3650 /* Produces a ALT_RSTMGR_DBGMODRST_DBG_RST register field value suitable for setting the register. */
3651 #define ALT_RSTMGR_DBGMODRST_DBG_RST_SET(value) (((value) << 0) & 0x00000001)
3652 
3653 /*
3654  * Field : Resets Coresight DAP - csdap_rst
3655  *
3656  * Resets logic located in the DAP domain.
3657  *
3658  * Field Access Macros:
3659  *
3660  */
3661 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field. */
3662 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_LSB 1
3663 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field. */
3664 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_MSB 1
3665 /* The width in bits of the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field. */
3666 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_WIDTH 1
3667 /* The mask used to set the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field value. */
3668 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_SET_MSK 0x00000002
3669 /* The mask used to clear the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field value. */
3670 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_CLR_MSK 0xfffffffd
3671 /* The reset value of the ALT_RSTMGR_DBGMODRST_CSDAP_RST register field. */
3672 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_RESET 0x0
3673 /* Extracts the ALT_RSTMGR_DBGMODRST_CSDAP_RST field value from a register. */
3674 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_GET(value) (((value) & 0x00000002) >> 1)
3675 /* Produces a ALT_RSTMGR_DBGMODRST_CSDAP_RST register field value suitable for setting the register. */
3676 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_SET(value) (((value) << 1) & 0x00000002)
3677 
3678 #ifndef __ASSEMBLY__
3679 /*
3680  * WARNING: The C register and register group struct declarations are provided for
3681  * convenience and illustrative purposes. They should, however, be used with
3682  * caution as the C language standard provides no guarantees about the alignment or
3683  * atomicity of device memory accesses. The recommended practice for coding device
3684  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3685  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3686  * alt_write_dword() functions for 64 bit registers.
3687  *
3688  * The struct declaration for register ALT_RSTMGR_DBGMODRST.
3689  */
3690 struct ALT_RSTMGR_DBGMODRST_s
3691 {
3692  volatile uint32_t dbg_rst : 1; /* Resets Debug Domain */
3693  volatile uint32_t csdap_rst : 1; /* Resets Coresight DAP */
3694  uint32_t : 30; /* *UNDEFINED* */
3695 };
3696 
3697 /* The typedef declaration for register ALT_RSTMGR_DBGMODRST. */
3698 typedef struct ALT_RSTMGR_DBGMODRST_s ALT_RSTMGR_DBGMODRST_t;
3699 #endif /* __ASSEMBLY__ */
3700 
3701 /* The reset value of the ALT_RSTMGR_DBGMODRST register. */
3702 #define ALT_RSTMGR_DBGMODRST_RESET 0x00000000
3703 /* The byte offset of the ALT_RSTMGR_DBGMODRST register from the beginning of the component. */
3704 #define ALT_RSTMGR_DBGMODRST_OFST 0x3c
3705 
3706 /*
3707  * Register : TAP Module Reset Register - tapmodrst
3708  *
3709  * The TAPMODRST register is used by software to trigger module resets. Software
3710  * triggers the assertion of the TAP module reset signal by writing 1 to the TAP
3711  * bit. The Reset Manager will hold the TAP module reset signal asserted for 1000
3712  * clock cycles and then release the TAP module reset. If the TAP module is
3713  * currently asserted, writing to this register has no effect.
3714  *
3715  * All fields are reset by a por reset. The reset value of all fields is 0.
3716  *
3717  * Register Layout
3718  *
3719  * Bits | Access | Reset | Description
3720  * :-------|:-------|:------|:-------------------------------
3721  * [0] | RW | 0x0 | JTAG TAP DOMAIN Reset Register
3722  * [31:1] | ??? | 0x0 | *UNDEFINED*
3723  *
3724  */
3725 /*
3726  * Field : JTAG TAP DOMAIN Reset Register - tap
3727  *
3728  * Resets logic located only in the jtag tap domain.
3729  *
3730  * Field Access Macros:
3731  *
3732  */
3733 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_TAPMODRST_TAP register field. */
3734 #define ALT_RSTMGR_TAPMODRST_TAP_LSB 0
3735 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_TAPMODRST_TAP register field. */
3736 #define ALT_RSTMGR_TAPMODRST_TAP_MSB 0
3737 /* The width in bits of the ALT_RSTMGR_TAPMODRST_TAP register field. */
3738 #define ALT_RSTMGR_TAPMODRST_TAP_WIDTH 1
3739 /* The mask used to set the ALT_RSTMGR_TAPMODRST_TAP register field value. */
3740 #define ALT_RSTMGR_TAPMODRST_TAP_SET_MSK 0x00000001
3741 /* The mask used to clear the ALT_RSTMGR_TAPMODRST_TAP register field value. */
3742 #define ALT_RSTMGR_TAPMODRST_TAP_CLR_MSK 0xfffffffe
3743 /* The reset value of the ALT_RSTMGR_TAPMODRST_TAP register field. */
3744 #define ALT_RSTMGR_TAPMODRST_TAP_RESET 0x0
3745 /* Extracts the ALT_RSTMGR_TAPMODRST_TAP field value from a register. */
3746 #define ALT_RSTMGR_TAPMODRST_TAP_GET(value) (((value) & 0x00000001) >> 0)
3747 /* Produces a ALT_RSTMGR_TAPMODRST_TAP register field value suitable for setting the register. */
3748 #define ALT_RSTMGR_TAPMODRST_TAP_SET(value) (((value) << 0) & 0x00000001)
3749 
3750 #ifndef __ASSEMBLY__
3751 /*
3752  * WARNING: The C register and register group struct declarations are provided for
3753  * convenience and illustrative purposes. They should, however, be used with
3754  * caution as the C language standard provides no guarantees about the alignment or
3755  * atomicity of device memory accesses. The recommended practice for coding device
3756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3758  * alt_write_dword() functions for 64 bit registers.
3759  *
3760  * The struct declaration for register ALT_RSTMGR_TAPMODRST.
3761  */
3762 struct ALT_RSTMGR_TAPMODRST_s
3763 {
3764  volatile uint32_t tap : 1; /* JTAG TAP DOMAIN Reset Register */
3765  uint32_t : 31; /* *UNDEFINED* */
3766 };
3767 
3768 /* The typedef declaration for register ALT_RSTMGR_TAPMODRST. */
3769 typedef struct ALT_RSTMGR_TAPMODRST_s ALT_RSTMGR_TAPMODRST_t;
3770 #endif /* __ASSEMBLY__ */
3771 
3772 /* The reset value of the ALT_RSTMGR_TAPMODRST register. */
3773 #define ALT_RSTMGR_TAPMODRST_RESET 0x00000000
3774 /* The byte offset of the ALT_RSTMGR_TAPMODRST register from the beginning of the component. */
3775 #define ALT_RSTMGR_TAPMODRST_OFST 0x40
3776 
3777 /*
3778  * Register : Bridge Warm Mask Register - brgwarmmask
3779  *
3780  * The "BRGWARMMASK" register is used by software to mask the assertion of module
3781  * reset signals on a warm reset. If the bit is 1, the module reset signal is
3782  * asserted during a warm reset. If the bit is 0, the module reset signal is not
3783  * asserted during a warm reset. The bit assignments of the *WARMMASK registers
3784  * match the corresponding *MODRST registers.
3785  *
3786  * All fields are only reset by a cold reset.
3787  *
3788  * Register Layout
3789  *
3790  * Bits | Access | Reset | Description
3791  * :-------|:-------|:----------|:----------------------------------
3792  * [0] | RW | 0x1 | Mask for SOC2FPGA Bridge Reset
3793  * [1] | RW | 0x1 | Mask for LWHPS2FPGA Bridge Reset.
3794  * [2] | RW | 0x1 | Mask for FPGA2SOC Bridge Reset.
3795  * [3] | RW | 0x1 | Mask for F2S SDRAM0 Bridge Reset
3796  * [4] | RW | 0x1 | Mask for F2S SDRAM1 Bridge Reset
3797  * [5] | RW | 0x1 | Mask for F2S SDRAM2 Bridge Reset
3798  * [6] | RW | 0x1 | Mask for DDR Scheduler Reset
3799  * [31:7] | ??? | 0x1ffffff | *UNDEFINED*
3800  *
3801  */
3802 /*
3803  * Field : Mask for SOC2FPGA Bridge Reset - soc2fpga
3804  *
3805  * Masks hardware sequenced warm reset for SOC2FPGA Bridge.
3806  *
3807  * Field Access Macros:
3808  *
3809  */
3810 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field. */
3811 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_LSB 0
3812 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field. */
3813 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_MSB 0
3814 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field. */
3815 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_WIDTH 1
3816 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field value. */
3817 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_SET_MSK 0x00000001
3818 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field value. */
3819 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_CLR_MSK 0xfffffffe
3820 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field. */
3821 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_RESET 0x1
3822 /* Extracts the ALT_RSTMGR_BRGWARMMASK_SOC2FPGA field value from a register. */
3823 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
3824 /* Produces a ALT_RSTMGR_BRGWARMMASK_SOC2FPGA register field value suitable for setting the register. */
3825 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
3826 
3827 /*
3828  * Field : Mask for LWHPS2FPGA Bridge Reset. - lwhps2fpga
3829  *
3830  * Masks hardware sequenced warm reset for LWHPS2FPGA Bridge
3831  *
3832  * Field Access Macros:
3833  *
3834  */
3835 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field. */
3836 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_LSB 1
3837 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field. */
3838 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_MSB 1
3839 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field. */
3840 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_WIDTH 1
3841 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field value. */
3842 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_SET_MSK 0x00000002
3843 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field value. */
3844 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_CLR_MSK 0xfffffffd
3845 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field. */
3846 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_RESET 0x1
3847 /* Extracts the ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA field value from a register. */
3848 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_GET(value) (((value) & 0x00000002) >> 1)
3849 /* Produces a ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA register field value suitable for setting the register. */
3850 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_SET(value) (((value) << 1) & 0x00000002)
3851 
3852 /*
3853  * Field : Mask for FPGA2SOC Bridge Reset. - fpga2soc
3854  *
3855  * Masks hardware sequenced warm reset for FPGA2SOC Bridge
3856  *
3857  * Field Access Macros:
3858  *
3859  */
3860 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field. */
3861 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_LSB 2
3862 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field. */
3863 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_MSB 2
3864 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field. */
3865 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_WIDTH 1
3866 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field value. */
3867 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_SET_MSK 0x00000004
3868 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field value. */
3869 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_CLR_MSK 0xfffffffb
3870 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field. */
3871 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_RESET 0x1
3872 /* Extracts the ALT_RSTMGR_BRGWARMMASK_FPGA2SOC field value from a register. */
3873 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_GET(value) (((value) & 0x00000004) >> 2)
3874 /* Produces a ALT_RSTMGR_BRGWARMMASK_FPGA2SOC register field value suitable for setting the register. */
3875 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_SET(value) (((value) << 2) & 0x00000004)
3876 
3877 /*
3878  * Field : Mask for F2S SDRAM0 Bridge Reset - f2ssdram0
3879  *
3880  * Masks hardware sequenced warm reset for F2S_SDRAM0 Bridge
3881  *
3882  * Field Access Macros:
3883  *
3884  */
3885 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field. */
3886 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_LSB 3
3887 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field. */
3888 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_MSB 3
3889 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field. */
3890 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_WIDTH 1
3891 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field value. */
3892 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_SET_MSK 0x00000008
3893 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field value. */
3894 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_CLR_MSK 0xfffffff7
3895 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field. */
3896 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_RESET 0x1
3897 /* Extracts the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 field value from a register. */
3898 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3899 /* Produces a ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0 register field value suitable for setting the register. */
3900 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3901 
3902 /*
3903  * Field : Mask for F2S SDRAM1 Bridge Reset - f2ssdram1
3904  *
3905  * Masks hardware sequenced warm reset for F2S_SDRAM1 Bridge.
3906  *
3907  * Field Access Macros:
3908  *
3909  */
3910 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field. */
3911 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_LSB 4
3912 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field. */
3913 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_MSB 4
3914 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field. */
3915 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_WIDTH 1
3916 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field value. */
3917 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_SET_MSK 0x00000010
3918 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field value. */
3919 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_CLR_MSK 0xffffffef
3920 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field. */
3921 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_RESET 0x1
3922 /* Extracts the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 field value from a register. */
3923 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3924 /* Produces a ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1 register field value suitable for setting the register. */
3925 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3926 
3927 /*
3928  * Field : Mask for F2S SDRAM2 Bridge Reset - f2ssdram2
3929  *
3930  * Masks hardware sequenced warm reset for F2S_SDRAM2 Bridge.
3931  *
3932  * Field Access Macros:
3933  *
3934  */
3935 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field. */
3936 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_LSB 5
3937 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field. */
3938 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_MSB 5
3939 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field. */
3940 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_WIDTH 1
3941 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field value. */
3942 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_SET_MSK 0x00000020
3943 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field value. */
3944 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_CLR_MSK 0xffffffdf
3945 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field. */
3946 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_RESET 0x1
3947 /* Extracts the ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 field value from a register. */
3948 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3949 /* Produces a ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2 register field value suitable for setting the register. */
3950 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3951 
3952 /*
3953  * Field : Mask for DDR Scheduler Reset - ddrsch
3954  *
3955  * Masks hardware sequenced warm reset for the DDR Scheduler in the NOC.
3956  *
3957  * Field Access Macros:
3958  *
3959  */
3960 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field. */
3961 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_LSB 6
3962 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field. */
3963 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_MSB 6
3964 /* The width in bits of the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field. */
3965 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_WIDTH 1
3966 /* The mask used to set the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field value. */
3967 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_SET_MSK 0x00000040
3968 /* The mask used to clear the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field value. */
3969 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_CLR_MSK 0xffffffbf
3970 /* The reset value of the ALT_RSTMGR_BRGWARMMASK_DDRSCH register field. */
3971 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_RESET 0x1
3972 /* Extracts the ALT_RSTMGR_BRGWARMMASK_DDRSCH field value from a register. */
3973 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3974 /* Produces a ALT_RSTMGR_BRGWARMMASK_DDRSCH register field value suitable for setting the register. */
3975 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3976 
3977 #ifndef __ASSEMBLY__
3978 /*
3979  * WARNING: The C register and register group struct declarations are provided for
3980  * convenience and illustrative purposes. They should, however, be used with
3981  * caution as the C language standard provides no guarantees about the alignment or
3982  * atomicity of device memory accesses. The recommended practice for coding device
3983  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3984  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3985  * alt_write_dword() functions for 64 bit registers.
3986  *
3987  * The struct declaration for register ALT_RSTMGR_BRGWARMMASK.
3988  */
3989 struct ALT_RSTMGR_BRGWARMMASK_s
3990 {
3991  volatile uint32_t soc2fpga : 1; /* Mask for SOC2FPGA Bridge Reset */
3992  volatile uint32_t lwhps2fpga : 1; /* Mask for LWHPS2FPGA Bridge Reset. */
3993  volatile uint32_t fpga2soc : 1; /* Mask for FPGA2SOC Bridge Reset. */
3994  volatile uint32_t f2ssdram0 : 1; /* Mask for F2S SDRAM0 Bridge Reset */
3995  volatile uint32_t f2ssdram1 : 1; /* Mask for F2S SDRAM1 Bridge Reset */
3996  volatile uint32_t f2ssdram2 : 1; /* Mask for F2S SDRAM2 Bridge Reset */
3997  volatile uint32_t ddrsch : 1; /* Mask for DDR Scheduler Reset */
3998  uint32_t : 25; /* *UNDEFINED* */
3999 };
4000 
4001 /* The typedef declaration for register ALT_RSTMGR_BRGWARMMASK. */
4002 typedef struct ALT_RSTMGR_BRGWARMMASK_s ALT_RSTMGR_BRGWARMMASK_t;
4003 #endif /* __ASSEMBLY__ */
4004 
4005 /* The reset value of the ALT_RSTMGR_BRGWARMMASK register. */
4006 #define ALT_RSTMGR_BRGWARMMASK_RESET 0xffffffff
4007 /* The byte offset of the ALT_RSTMGR_BRGWARMMASK register from the beginning of the component. */
4008 #define ALT_RSTMGR_BRGWARMMASK_OFST 0x4c
4009 
4010 /*
4011  * Register : Test Status - tststa
4012  *
4013  * Status fields used for testing the Reset Manager.
4014  *
4015  * Register Layout
4016  *
4017  * Bits | Access | Reset | Description
4018  * :-------|:-------|:------|:------------
4019  * [4:0] | R | 0x0 | Reset State
4020  * [31:5] | ??? | 0x0 | *UNDEFINED*
4021  *
4022  */
4023 /*
4024  * Field : Reset State - rstst
4025  *
4026  * Warm/cold reset control FSM state.
4027  *
4028  * Field Access Macros:
4029  *
4030  */
4031 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_TSTSTA_RSTST register field. */
4032 #define ALT_RSTMGR_TSTSTA_RSTST_LSB 0
4033 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_TSTSTA_RSTST register field. */
4034 #define ALT_RSTMGR_TSTSTA_RSTST_MSB 4
4035 /* The width in bits of the ALT_RSTMGR_TSTSTA_RSTST register field. */
4036 #define ALT_RSTMGR_TSTSTA_RSTST_WIDTH 5
4037 /* The mask used to set the ALT_RSTMGR_TSTSTA_RSTST register field value. */
4038 #define ALT_RSTMGR_TSTSTA_RSTST_SET_MSK 0x0000001f
4039 /* The mask used to clear the ALT_RSTMGR_TSTSTA_RSTST register field value. */
4040 #define ALT_RSTMGR_TSTSTA_RSTST_CLR_MSK 0xffffffe0
4041 /* The reset value of the ALT_RSTMGR_TSTSTA_RSTST register field. */
4042 #define ALT_RSTMGR_TSTSTA_RSTST_RESET 0x0
4043 /* Extracts the ALT_RSTMGR_TSTSTA_RSTST field value from a register. */
4044 #define ALT_RSTMGR_TSTSTA_RSTST_GET(value) (((value) & 0x0000001f) >> 0)
4045 /* Produces a ALT_RSTMGR_TSTSTA_RSTST register field value suitable for setting the register. */
4046 #define ALT_RSTMGR_TSTSTA_RSTST_SET(value) (((value) << 0) & 0x0000001f)
4047 
4048 #ifndef __ASSEMBLY__
4049 /*
4050  * WARNING: The C register and register group struct declarations are provided for
4051  * convenience and illustrative purposes. They should, however, be used with
4052  * caution as the C language standard provides no guarantees about the alignment or
4053  * atomicity of device memory accesses. The recommended practice for coding device
4054  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4055  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4056  * alt_write_dword() functions for 64 bit registers.
4057  *
4058  * The struct declaration for register ALT_RSTMGR_TSTSTA.
4059  */
4060 struct ALT_RSTMGR_TSTSTA_s
4061 {
4062  const volatile uint32_t rstst : 5; /* Reset State */
4063  uint32_t : 27; /* *UNDEFINED* */
4064 };
4065 
4066 /* The typedef declaration for register ALT_RSTMGR_TSTSTA. */
4067 typedef struct ALT_RSTMGR_TSTSTA_s ALT_RSTMGR_TSTSTA_t;
4068 #endif /* __ASSEMBLY__ */
4069 
4070 /* The reset value of the ALT_RSTMGR_TSTSTA register. */
4071 #define ALT_RSTMGR_TSTSTA_RESET 0x00000000
4072 /* The byte offset of the ALT_RSTMGR_TSTSTA register from the beginning of the component. */
4073 #define ALT_RSTMGR_TSTSTA_OFST 0x5c
4074 
4075 /*
4076  * Register : Hand Shake Time Out Value - hdsktimeout
4077  *
4078  * The Warm Reset handshake time-out controls the amount of time to wait for the
4079  * ETR, FPGA and SDRAM interface to respond to a reset handshake request. The
4080  * register defaults to 10,240 l4_sys_free_clk cycles, which at 100 MHz will be
4081  * 102.4 micro-seconds. This value will be a 25 bit programmable value in SW. The
4082  * maximum programmable value would be 2^25-1 l4_sys_free_clk cycles.
4083  *
4084  * Register Layout
4085  *
4086  * Bits | Access | Reset | Description
4087  * :-------|:-------|:-------|:---------------------------------
4088  * [31:0] | RW | 0x2800 | Handshake timeout value Register
4089  *
4090  */
4091 /*
4092  * Field : Handshake timeout value Register - val
4093  *
4094  * ETR, FPGA and SDRAM interface handshake time-out value.
4095  *
4096  * Field Access Macros:
4097  *
4098  */
4099 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKTIMEOUT_VAL register field. */
4100 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_LSB 0
4101 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKTIMEOUT_VAL register field. */
4102 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_MSB 31
4103 /* The width in bits of the ALT_RSTMGR_HDSKTIMEOUT_VAL register field. */
4104 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_WIDTH 32
4105 /* The mask used to set the ALT_RSTMGR_HDSKTIMEOUT_VAL register field value. */
4106 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_SET_MSK 0xffffffff
4107 /* The mask used to clear the ALT_RSTMGR_HDSKTIMEOUT_VAL register field value. */
4108 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_CLR_MSK 0x00000000
4109 /* The reset value of the ALT_RSTMGR_HDSKTIMEOUT_VAL register field. */
4110 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_RESET 0x2800
4111 /* Extracts the ALT_RSTMGR_HDSKTIMEOUT_VAL field value from a register. */
4112 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4113 /* Produces a ALT_RSTMGR_HDSKTIMEOUT_VAL register field value suitable for setting the register. */
4114 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4115 
4116 #ifndef __ASSEMBLY__
4117 /*
4118  * WARNING: The C register and register group struct declarations are provided for
4119  * convenience and illustrative purposes. They should, however, be used with
4120  * caution as the C language standard provides no guarantees about the alignment or
4121  * atomicity of device memory accesses. The recommended practice for coding device
4122  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4123  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4124  * alt_write_dword() functions for 64 bit registers.
4125  *
4126  * The struct declaration for register ALT_RSTMGR_HDSKTIMEOUT.
4127  */
4128 struct ALT_RSTMGR_HDSKTIMEOUT_s
4129 {
4130  volatile uint32_t val : 32; /* Handshake timeout value Register */
4131 };
4132 
4133 /* The typedef declaration for register ALT_RSTMGR_HDSKTIMEOUT. */
4134 typedef struct ALT_RSTMGR_HDSKTIMEOUT_s ALT_RSTMGR_HDSKTIMEOUT_t;
4135 #endif /* __ASSEMBLY__ */
4136 
4137 /* The reset value of the ALT_RSTMGR_HDSKTIMEOUT register. */
4138 #define ALT_RSTMGR_HDSKTIMEOUT_RESET 0x00002800
4139 /* The byte offset of the ALT_RSTMGR_HDSKTIMEOUT register from the beginning of the component. */
4140 #define ALT_RSTMGR_HDSKTIMEOUT_OFST 0x64
4141 
4142 /*
4143  * Register : MPU L2 FLUSH Time Out Value Register - mpul2flushtimeout
4144  *
4145  * The MPU L2 FLUSH handshake timeout will default to 1,048,576 which at 100 MHz
4146  * for l4_sys_free_clk will 1048 micro-seconds. This value will be a 32 bit
4147  * programmable value in SW.
4148  *
4149  * Register Layout
4150  *
4151  * Bits | Access | Reset | Description
4152  * :-------|:-------|:---------|:--------------------------
4153  * [31:0] | RW | 0x100000 | mpu l2flush timeout value
4154  *
4155  */
4156 /*
4157  * Field : mpu l2flush timeout value - val
4158  *
4159  * MPU L2 flush handshake time-out value.
4160  *
4161  * Field Access Macros:
4162  *
4163  */
4164 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field. */
4165 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_LSB 0
4166 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field. */
4167 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_MSB 31
4168 /* The width in bits of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field. */
4169 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_WIDTH 32
4170 /* The mask used to set the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field value. */
4171 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_SET_MSK 0xffffffff
4172 /* The mask used to clear the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field value. */
4173 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_CLR_MSK 0x00000000
4174 /* The reset value of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field. */
4175 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_RESET 0x100000
4176 /* Extracts the ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL field value from a register. */
4177 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4178 /* Produces a ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL register field value suitable for setting the register. */
4179 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4180 
4181 #ifndef __ASSEMBLY__
4182 /*
4183  * WARNING: The C register and register group struct declarations are provided for
4184  * convenience and illustrative purposes. They should, however, be used with
4185  * caution as the C language standard provides no guarantees about the alignment or
4186  * atomicity of device memory accesses. The recommended practice for coding device
4187  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4188  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4189  * alt_write_dword() functions for 64 bit registers.
4190  *
4191  * The struct declaration for register ALT_RSTMGR_MPUL2FLUSHTIMEOUT.
4192  */
4193 struct ALT_RSTMGR_MPUL2FLUSHTIMEOUT_s
4194 {
4195  volatile uint32_t val : 32; /* mpu l2flush timeout value */
4196 };
4197 
4198 /* The typedef declaration for register ALT_RSTMGR_MPUL2FLUSHTIMEOUT. */
4199 typedef struct ALT_RSTMGR_MPUL2FLUSHTIMEOUT_s ALT_RSTMGR_MPUL2FLUSHTIMEOUT_t;
4200 #endif /* __ASSEMBLY__ */
4201 
4202 /* The reset value of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT register. */
4203 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_RESET 0x00100000
4204 /* The byte offset of the ALT_RSTMGR_MPUL2FLUSHTIMEOUT register from the beginning of the component. */
4205 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_OFST 0x68
4206 
4207 /*
4208  * Register : L3NOC Debug CS_DAP Handshake Time Out Value - dbghdsktimeout
4209  *
4210  * The reset handshake time-out register controls the amount of time to wait for
4211  * the L3NOC interface to respond to a reset handshake request.
4212  *
4213  * Note that the reset handshake is initiated when either the L3NOC or Debug/DAP
4214  * domain is getting reset.
4215  *
4216  * Register Layout
4217  *
4218  * Bits | Access | Reset | Description
4219  * :-------|:-------|:---------|:---------------------------------
4220  * [31:0] | RW | 0x100000 | Handshake timeout value Register
4221  *
4222  */
4223 /*
4224  * Field : Handshake timeout value Register - val
4225  *
4226  * L3NOC interface handshake time-out value.
4227  *
4228  * Field Access Macros:
4229  *
4230  */
4231 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field. */
4232 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_LSB 0
4233 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field. */
4234 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_MSB 31
4235 /* The width in bits of the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field. */
4236 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_WIDTH 32
4237 /* The mask used to set the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field value. */
4238 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_SET_MSK 0xffffffff
4239 /* The mask used to clear the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field value. */
4240 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_CLR_MSK 0x00000000
4241 /* The reset value of the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field. */
4242 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_RESET 0x100000
4243 /* Extracts the ALT_RSTMGR_DBGHDSKTIMEOUT_VAL field value from a register. */
4244 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4245 /* Produces a ALT_RSTMGR_DBGHDSKTIMEOUT_VAL register field value suitable for setting the register. */
4246 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4247 
4248 #ifndef __ASSEMBLY__
4249 /*
4250  * WARNING: The C register and register group struct declarations are provided for
4251  * convenience and illustrative purposes. They should, however, be used with
4252  * caution as the C language standard provides no guarantees about the alignment or
4253  * atomicity of device memory accesses. The recommended practice for coding device
4254  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4255  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4256  * alt_write_dword() functions for 64 bit registers.
4257  *
4258  * The struct declaration for register ALT_RSTMGR_DBGHDSKTIMEOUT.
4259  */
4260 struct ALT_RSTMGR_DBGHDSKTIMEOUT_s
4261 {
4262  volatile uint32_t val : 32; /* Handshake timeout value Register */
4263 };
4264 
4265 /* The typedef declaration for register ALT_RSTMGR_DBGHDSKTIMEOUT. */
4266 typedef struct ALT_RSTMGR_DBGHDSKTIMEOUT_s ALT_RSTMGR_DBGHDSKTIMEOUT_t;
4267 #endif /* __ASSEMBLY__ */
4268 
4269 /* The reset value of the ALT_RSTMGR_DBGHDSKTIMEOUT register. */
4270 #define ALT_RSTMGR_DBGHDSKTIMEOUT_RESET 0x00100000
4271 /* The byte offset of the ALT_RSTMGR_DBGHDSKTIMEOUT register from the beginning of the component. */
4272 #define ALT_RSTMGR_DBGHDSKTIMEOUT_OFST 0x6c
4273 
4274 /*
4275  * Register : On Chip RAM load done - ocramload
4276  *
4277  * SDM will set this register bit to 1 to indicate that the Onchip RAM content
4278  * loading is complete. The Reset Manager will wait for this bit to be set before
4279  * releasing the MPU warm resets.
4280  *
4281  * This Register bit is reset by POR domain only.
4282  *
4283  * Register Layout
4284  *
4285  * Bits | Access | Reset | Description
4286  * :-------|:-------|:------|:------------
4287  * [0] | RW | 0x0 | done
4288  * [31:1] | ??? | 0x0 | *UNDEFINED*
4289  *
4290  */
4291 /*
4292  * Field : done - done
4293  *
4294  * SDM sets this bit to indicate the Reset Manager that the on chip ram loading is
4295  * done and it is safe to proceed with the MPU reset de-assertion sequence.
4296  *
4297  * Field Access Macros:
4298  *
4299  */
4300 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_OCRAMLOAD_DONE register field. */
4301 #define ALT_RSTMGR_OCRAMLOAD_DONE_LSB 0
4302 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_OCRAMLOAD_DONE register field. */
4303 #define ALT_RSTMGR_OCRAMLOAD_DONE_MSB 0
4304 /* The width in bits of the ALT_RSTMGR_OCRAMLOAD_DONE register field. */
4305 #define ALT_RSTMGR_OCRAMLOAD_DONE_WIDTH 1
4306 /* The mask used to set the ALT_RSTMGR_OCRAMLOAD_DONE register field value. */
4307 #define ALT_RSTMGR_OCRAMLOAD_DONE_SET_MSK 0x00000001
4308 /* The mask used to clear the ALT_RSTMGR_OCRAMLOAD_DONE register field value. */
4309 #define ALT_RSTMGR_OCRAMLOAD_DONE_CLR_MSK 0xfffffffe
4310 /* The reset value of the ALT_RSTMGR_OCRAMLOAD_DONE register field. */
4311 #define ALT_RSTMGR_OCRAMLOAD_DONE_RESET 0x0
4312 /* Extracts the ALT_RSTMGR_OCRAMLOAD_DONE field value from a register. */
4313 #define ALT_RSTMGR_OCRAMLOAD_DONE_GET(value) (((value) & 0x00000001) >> 0)
4314 /* Produces a ALT_RSTMGR_OCRAMLOAD_DONE register field value suitable for setting the register. */
4315 #define ALT_RSTMGR_OCRAMLOAD_DONE_SET(value) (((value) << 0) & 0x00000001)
4316 
4317 #ifndef __ASSEMBLY__
4318 /*
4319  * WARNING: The C register and register group struct declarations are provided for
4320  * convenience and illustrative purposes. They should, however, be used with
4321  * caution as the C language standard provides no guarantees about the alignment or
4322  * atomicity of device memory accesses. The recommended practice for coding device
4323  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4324  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4325  * alt_write_dword() functions for 64 bit registers.
4326  *
4327  * The struct declaration for register ALT_RSTMGR_OCRAMLOAD.
4328  */
4329 struct ALT_RSTMGR_OCRAMLOAD_s
4330 {
4331  volatile uint32_t done : 1; /* done */
4332  uint32_t : 31; /* *UNDEFINED* */
4333 };
4334 
4335 /* The typedef declaration for register ALT_RSTMGR_OCRAMLOAD. */
4336 typedef struct ALT_RSTMGR_OCRAMLOAD_s ALT_RSTMGR_OCRAMLOAD_t;
4337 #endif /* __ASSEMBLY__ */
4338 
4339 /* The reset value of the ALT_RSTMGR_OCRAMLOAD register. */
4340 #define ALT_RSTMGR_OCRAMLOAD_RESET 0x00000000
4341 /* The byte offset of the ALT_RSTMGR_OCRAMLOAD register from the beginning of the component. */
4342 #define ALT_RSTMGR_OCRAMLOAD_OFST 0x80
4343 
4344 #ifndef __ASSEMBLY__
4345 /*
4346  * WARNING: The C register and register group struct declarations are provided for
4347  * convenience and illustrative purposes. They should, however, be used with
4348  * caution as the C language standard provides no guarantees about the alignment or
4349  * atomicity of device memory accesses. The recommended practice for coding device
4350  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4351  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4352  * alt_write_dword() functions for 64 bit registers.
4353  *
4354  * The struct declaration for register group ALT_RSTMGR.
4355  */
4356 struct ALT_RSTMGR_s
4357 {
4358  volatile ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */
4359  volatile ALT_RSTMGR_MPURSTSTAT_t mpurststat; /* ALT_RSTMGR_MPURSTSTAT */
4360  volatile ALT_RSTMGR_MISCSTAT_t miscstat; /* ALT_RSTMGR_MISCSTAT */
4361  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
4362  volatile ALT_RSTMGR_HDSKEN_t hdsken; /* ALT_RSTMGR_HDSKEN */
4363  volatile ALT_RSTMGR_HDSKREQ_t hdskreq; /* ALT_RSTMGR_HDSKREQ */
4364  volatile ALT_RSTMGR_HDSKACK_t hdskack; /* ALT_RSTMGR_HDSKACK */
4365  volatile ALT_RSTMGR_HDSKSTALL_t hdskstall; /* ALT_RSTMGR_HDSKSTALL */
4366  volatile ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
4367  volatile ALT_RSTMGR_PER0MODRST_t per0modrst; /* ALT_RSTMGR_PER0MODRST */
4368  volatile ALT_RSTMGR_PER1MODRST_t per1modrst; /* ALT_RSTMGR_PER1MODRST */
4369  volatile ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
4370  volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
4371  volatile ALT_RSTMGR_COLDMODRST_t coldmodrst; /* ALT_RSTMGR_COLDMODRST */
4372  volatile uint32_t _pad_0x38_0x3b; /* *UNDEFINED* */
4373  volatile ALT_RSTMGR_DBGMODRST_t dbgmodrst; /* ALT_RSTMGR_DBGMODRST */
4374  volatile ALT_RSTMGR_TAPMODRST_t tapmodrst; /* ALT_RSTMGR_TAPMODRST */
4375  volatile uint32_t _pad_0x44_0x4b[2]; /* *UNDEFINED* */
4376  volatile ALT_RSTMGR_BRGWARMMASK_t brgwarmmask; /* ALT_RSTMGR_BRGWARMMASK */
4377  volatile uint32_t _pad_0x50_0x5b[3]; /* *UNDEFINED* */
4378  volatile ALT_RSTMGR_TSTSTA_t tststa; /* ALT_RSTMGR_TSTSTA */
4379  volatile uint32_t _pad_0x60_0x63; /* *UNDEFINED* */
4380  volatile ALT_RSTMGR_HDSKTIMEOUT_t hdsktimeout; /* ALT_RSTMGR_HDSKTIMEOUT */
4381  volatile ALT_RSTMGR_MPUL2FLUSHTIMEOUT_t mpul2flushtimeout; /* ALT_RSTMGR_MPUL2FLUSHTIMEOUT */
4382  volatile ALT_RSTMGR_DBGHDSKTIMEOUT_t dbghdsktimeout; /* ALT_RSTMGR_DBGHDSKTIMEOUT */
4383  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4384  volatile ALT_RSTMGR_OCRAMLOAD_t ocramload; /* ALT_RSTMGR_OCRAMLOAD */
4385  volatile uint32_t _pad_0x84_0x100[31]; /* *UNDEFINED* */
4386 };
4387 
4388 /* The typedef declaration for register group ALT_RSTMGR. */
4389 typedef struct ALT_RSTMGR_s ALT_RSTMGR_t;
4390 /* The struct declaration for the raw register contents of register group ALT_RSTMGR. */
4391 struct ALT_RSTMGR_raw_s
4392 {
4393  volatile uint32_t stat; /* ALT_RSTMGR_STAT */
4394  volatile uint32_t mpurststat; /* ALT_RSTMGR_MPURSTSTAT */
4395  volatile uint32_t miscstat; /* ALT_RSTMGR_MISCSTAT */
4396  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
4397  volatile uint32_t hdsken; /* ALT_RSTMGR_HDSKEN */
4398  volatile uint32_t hdskreq; /* ALT_RSTMGR_HDSKREQ */
4399  volatile uint32_t hdskack; /* ALT_RSTMGR_HDSKACK */
4400  volatile uint32_t hdskstall; /* ALT_RSTMGR_HDSKSTALL */
4401  volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
4402  volatile uint32_t per0modrst; /* ALT_RSTMGR_PER0MODRST */
4403  volatile uint32_t per1modrst; /* ALT_RSTMGR_PER1MODRST */
4404  volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
4405  volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
4406  volatile uint32_t coldmodrst; /* ALT_RSTMGR_COLDMODRST */
4407  volatile uint32_t _pad_0x38_0x3b; /* *UNDEFINED* */
4408  volatile uint32_t dbgmodrst; /* ALT_RSTMGR_DBGMODRST */
4409  volatile uint32_t tapmodrst; /* ALT_RSTMGR_TAPMODRST */
4410  volatile uint32_t _pad_0x44_0x4b[2]; /* *UNDEFINED* */
4411  volatile uint32_t brgwarmmask; /* ALT_RSTMGR_BRGWARMMASK */
4412  volatile uint32_t _pad_0x50_0x5b[3]; /* *UNDEFINED* */
4413  volatile uint32_t tststa; /* ALT_RSTMGR_TSTSTA */
4414  volatile uint32_t _pad_0x60_0x63; /* *UNDEFINED* */
4415  volatile uint32_t hdsktimeout; /* ALT_RSTMGR_HDSKTIMEOUT */
4416  volatile uint32_t mpul2flushtimeout; /* ALT_RSTMGR_MPUL2FLUSHTIMEOUT */
4417  volatile uint32_t dbghdsktimeout; /* ALT_RSTMGR_DBGHDSKTIMEOUT */
4418  volatile uint32_t _pad_0x70_0x7f[4]; /* *UNDEFINED* */
4419  volatile uint32_t ocramload; /* ALT_RSTMGR_OCRAMLOAD */
4420  volatile uint32_t _pad_0x84_0x100[31]; /* *UNDEFINED* */
4421 };
4422 
4423 /* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */
4424 typedef struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;
4425 #endif /* __ASSEMBLY__ */
4426 
4427 
4428 #ifdef __cplusplus
4429 }
4430 #endif /* __cplusplus */
4431 #endif /* __ALT_SOCAL_RSTMGR_H__ */
4432