Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
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alt_sysmgr.h
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32 
33 /* Altera - ALT_SYSMGR_CORE */
34 
35 #ifndef __ALT_SOCAL_SYSMGR_H__
36 #define __ALT_SOCAL_SYSMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Core Registers - SYSMGR_CORE
50  * Core Registers
51  *
52  * System Manager core registers
53  *
54  */
55 /*
56  * Register : Silicon ID1 Register - siliconid1
57  *
58  * Specifies Silicon ID and revision number.
59  *
60  * This is a read only register and a write should return error.
61  *
62  * Register Layout
63  *
64  * Bits | Access | Reset | Description
65  * :--------|:-------|:------|:-----------------
66  * [15:0] | R | 0x1 | Silicon Revision
67  * [31:16] | R | 0x2 | Silicon ID
68  *
69  */
70 /*
71  * Field : Silicon Revision - rev
72  *
73  * Silicon revision number.
74  *
75  * Field Enumeration Values:
76  *
77  * Enum | Value | Description
78  * :--------------------------------------|:------|:------------
79  * ALT_SYSMGR_CORE_SILICONID1_REV_E_REV1 | 0x1 |
80  *
81  * Field Access Macros:
82  *
83  */
84 /*
85  * Enumerated value for register field ALT_SYSMGR_CORE_SILICONID1_REV
86  *
87  */
88 #define ALT_SYSMGR_CORE_SILICONID1_REV_E_REV1 0x1
89 
90 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SILICONID1_REV register field. */
91 #define ALT_SYSMGR_CORE_SILICONID1_REV_LSB 0
92 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SILICONID1_REV register field. */
93 #define ALT_SYSMGR_CORE_SILICONID1_REV_MSB 15
94 /* The width in bits of the ALT_SYSMGR_CORE_SILICONID1_REV register field. */
95 #define ALT_SYSMGR_CORE_SILICONID1_REV_WIDTH 16
96 /* The mask used to set the ALT_SYSMGR_CORE_SILICONID1_REV register field value. */
97 #define ALT_SYSMGR_CORE_SILICONID1_REV_SET_MSK 0x0000ffff
98 /* The mask used to clear the ALT_SYSMGR_CORE_SILICONID1_REV register field value. */
99 #define ALT_SYSMGR_CORE_SILICONID1_REV_CLR_MSK 0xffff0000
100 /* The reset value of the ALT_SYSMGR_CORE_SILICONID1_REV register field. */
101 #define ALT_SYSMGR_CORE_SILICONID1_REV_RESET 0x1
102 /* Extracts the ALT_SYSMGR_CORE_SILICONID1_REV field value from a register. */
103 #define ALT_SYSMGR_CORE_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
104 /* Produces a ALT_SYSMGR_CORE_SILICONID1_REV register field value suitable for setting the register. */
105 #define ALT_SYSMGR_CORE_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
106 
107 /*
108  * Field : Silicon ID - id
109  *
110  * Silicon ID
111  *
112  * Field Enumeration Values:
113  *
114  * Enum | Value | Description
115  * :----------------------------------------------|:------|:------------
116  * ALT_SYSMGR_CORE_SILICONID1_ID_E_HPS_STRATIX10 | 0x2 |
117  *
118  * Field Access Macros:
119  *
120  */
121 /*
122  * Enumerated value for register field ALT_SYSMGR_CORE_SILICONID1_ID
123  *
124  */
125 #define ALT_SYSMGR_CORE_SILICONID1_ID_E_HPS_STRATIX10 0x2
126 
127 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SILICONID1_ID register field. */
128 #define ALT_SYSMGR_CORE_SILICONID1_ID_LSB 16
129 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SILICONID1_ID register field. */
130 #define ALT_SYSMGR_CORE_SILICONID1_ID_MSB 31
131 /* The width in bits of the ALT_SYSMGR_CORE_SILICONID1_ID register field. */
132 #define ALT_SYSMGR_CORE_SILICONID1_ID_WIDTH 16
133 /* The mask used to set the ALT_SYSMGR_CORE_SILICONID1_ID register field value. */
134 #define ALT_SYSMGR_CORE_SILICONID1_ID_SET_MSK 0xffff0000
135 /* The mask used to clear the ALT_SYSMGR_CORE_SILICONID1_ID register field value. */
136 #define ALT_SYSMGR_CORE_SILICONID1_ID_CLR_MSK 0x0000ffff
137 /* The reset value of the ALT_SYSMGR_CORE_SILICONID1_ID register field. */
138 #define ALT_SYSMGR_CORE_SILICONID1_ID_RESET 0x2
139 /* Extracts the ALT_SYSMGR_CORE_SILICONID1_ID field value from a register. */
140 #define ALT_SYSMGR_CORE_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
141 /* Produces a ALT_SYSMGR_CORE_SILICONID1_ID register field value suitable for setting the register. */
142 #define ALT_SYSMGR_CORE_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
143 
144 #ifndef __ASSEMBLY__
145 /*
146  * WARNING: The C register and register group struct declarations are provided for
147  * convenience and illustrative purposes. They should, however, be used with
148  * caution as the C language standard provides no guarantees about the alignment or
149  * atomicity of device memory accesses. The recommended practice for coding device
150  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
151  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
152  * alt_write_dword() functions for 64 bit registers.
153  *
154  * The struct declaration for register ALT_SYSMGR_CORE_SILICONID1.
155  */
156 struct ALT_SYSMGR_CORE_SILICONID1_s
157 {
158  const volatile uint32_t rev : 16; /* Silicon Revision */
159  const volatile uint32_t id : 16; /* Silicon ID */
160 };
161 
162 /* The typedef declaration for register ALT_SYSMGR_CORE_SILICONID1. */
163 typedef struct ALT_SYSMGR_CORE_SILICONID1_s ALT_SYSMGR_CORE_SILICONID1_t;
164 #endif /* __ASSEMBLY__ */
165 
166 /* The reset value of the ALT_SYSMGR_CORE_SILICONID1 register. */
167 #define ALT_SYSMGR_CORE_SILICONID1_RESET 0x00020001
168 /* The byte offset of the ALT_SYSMGR_CORE_SILICONID1 register from the beginning of the component. */
169 #define ALT_SYSMGR_CORE_SILICONID1_OFST 0x0
170 
171 /*
172  * Register : Silicon ID2 Register - siliconid2
173  *
174  * Reserved for future use.
175  *
176  * This is a read only register and a write should return error.
177  *
178  * Register Layout
179  *
180  * Bits | Access | Reset | Description
181  * :-------|:-------|:------|:------------
182  * [3:0] | R | 0x0 | Reserved
183  * [31:4] | R | 0x0 | Reserved
184  *
185  */
186 /*
187  * Field : Reserved - device_revision
188  *
189  * SDM writes the device revision value from fuses to HPS secure manager.
190  *
191  * Secure manager drives this value to system manager.
192  *
193  * Field Access Macros:
194  *
195  */
196 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field. */
197 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_LSB 0
198 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field. */
199 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_MSB 3
200 /* The width in bits of the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field. */
201 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_WIDTH 4
202 /* The mask used to set the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field value. */
203 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_SET_MSK 0x0000000f
204 /* The mask used to clear the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field value. */
205 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_CLR_MSK 0xfffffff0
206 /* The reset value of the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field. */
207 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_RESET 0x0
208 /* Extracts the ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION field value from a register. */
209 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_GET(value) (((value) & 0x0000000f) >> 0)
210 /* Produces a ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION register field value suitable for setting the register. */
211 #define ALT_SYSMGR_CORE_SILICONID2_DEVICE_REVISION_SET(value) (((value) << 0) & 0x0000000f)
212 
213 /*
214  * Field : Reserved - rsv
215  *
216  * Reserved for future use.
217  *
218  * Field Access Macros:
219  *
220  */
221 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SILICONID2_RSV register field. */
222 #define ALT_SYSMGR_CORE_SILICONID2_RSV_LSB 4
223 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SILICONID2_RSV register field. */
224 #define ALT_SYSMGR_CORE_SILICONID2_RSV_MSB 31
225 /* The width in bits of the ALT_SYSMGR_CORE_SILICONID2_RSV register field. */
226 #define ALT_SYSMGR_CORE_SILICONID2_RSV_WIDTH 28
227 /* The mask used to set the ALT_SYSMGR_CORE_SILICONID2_RSV register field value. */
228 #define ALT_SYSMGR_CORE_SILICONID2_RSV_SET_MSK 0xfffffff0
229 /* The mask used to clear the ALT_SYSMGR_CORE_SILICONID2_RSV register field value. */
230 #define ALT_SYSMGR_CORE_SILICONID2_RSV_CLR_MSK 0x0000000f
231 /* The reset value of the ALT_SYSMGR_CORE_SILICONID2_RSV register field. */
232 #define ALT_SYSMGR_CORE_SILICONID2_RSV_RESET 0x0
233 /* Extracts the ALT_SYSMGR_CORE_SILICONID2_RSV field value from a register. */
234 #define ALT_SYSMGR_CORE_SILICONID2_RSV_GET(value) (((value) & 0xfffffff0) >> 4)
235 /* Produces a ALT_SYSMGR_CORE_SILICONID2_RSV register field value suitable for setting the register. */
236 #define ALT_SYSMGR_CORE_SILICONID2_RSV_SET(value) (((value) << 4) & 0xfffffff0)
237 
238 #ifndef __ASSEMBLY__
239 /*
240  * WARNING: The C register and register group struct declarations are provided for
241  * convenience and illustrative purposes. They should, however, be used with
242  * caution as the C language standard provides no guarantees about the alignment or
243  * atomicity of device memory accesses. The recommended practice for coding device
244  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
245  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
246  * alt_write_dword() functions for 64 bit registers.
247  *
248  * The struct declaration for register ALT_SYSMGR_CORE_SILICONID2.
249  */
250 struct ALT_SYSMGR_CORE_SILICONID2_s
251 {
252  const volatile uint32_t device_revision : 4; /* Reserved */
253  const volatile uint32_t rsv : 28; /* Reserved */
254 };
255 
256 /* The typedef declaration for register ALT_SYSMGR_CORE_SILICONID2. */
257 typedef struct ALT_SYSMGR_CORE_SILICONID2_s ALT_SYSMGR_CORE_SILICONID2_t;
258 #endif /* __ASSEMBLY__ */
259 
260 /* The reset value of the ALT_SYSMGR_CORE_SILICONID2 register. */
261 #define ALT_SYSMGR_CORE_SILICONID2_RESET 0x00000000
262 /* The byte offset of the ALT_SYSMGR_CORE_SILICONID2 register from the beginning of the component. */
263 #define ALT_SYSMGR_CORE_SILICONID2_OFST 0x4
264 
265 /*
266  * Register : L4 Watchdog Debug Register - wddbg
267  *
268  * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These
269  * control registers are used to drive the pause input signal of the L4 watchdogs.
270  * Note that the watchdogs built into the MPU automatically are paused when their
271  * associated CPU enters debug mode. Only reset by a cold reset.
272  *
273  * Register Layout
274  *
275  * Bits | Access | Reset | Description
276  * :--------|:-------|:------|:------------
277  * [3:0] | RW | 0x8 | Debug Mode
278  * [7:4] | ??? | 0x0 | *UNDEFINED*
279  * [11:8] | RW | 0x8 | Debug Mode
280  * [15:12] | ??? | 0x0 | *UNDEFINED*
281  * [19:16] | RW | 0x8 | Debug Mode
282  * [23:20] | ??? | 0x0 | *UNDEFINED*
283  * [27:24] | RW | 0x8 | Debug Mode
284  * [31:28] | ??? | 0x0 | *UNDEFINED*
285  *
286  */
287 /*
288  * Field : Debug Mode - mode_0
289  *
290  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
291  * matches L4 watchdog index.
292  *
293  * Field Enumeration Values:
294  *
295  * Enum | Value | Description
296  * :--------------------------------------------------------|:------|:------------
297  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_DONT_PAUSE | 0x0 |
298  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU0 | 0x1 |
299  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU1 | 0x2 |
300  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU2 | 0x4 |
301  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU3 | 0x8 |
302  * ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_ANY_CPU | 0xf |
303  *
304  * Field Access Macros:
305  *
306  */
307 /*
308  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
309  *
310  */
311 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_DONT_PAUSE 0x0
312 /*
313  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
314  *
315  */
316 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU0 0x1
317 /*
318  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
319  *
320  */
321 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU1 0x2
322 /*
323  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
324  *
325  */
326 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU2 0x4
327 /*
328  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
329  *
330  */
331 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_CPU3 0x8
332 /*
333  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_0
334  *
335  */
336 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_E_MODE_0_PAUSE_FOR_ANY_CPU 0xf
337 
338 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field. */
339 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_LSB 0
340 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field. */
341 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_MSB 3
342 /* The width in bits of the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field. */
343 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_WIDTH 4
344 /* The mask used to set the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field value. */
345 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_SET_MSK 0x0000000f
346 /* The mask used to clear the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field value. */
347 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_CLR_MSK 0xfffffff0
348 /* The reset value of the ALT_SYSMGR_CORE_WDDBG_MODE_0 register field. */
349 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_RESET 0x8
350 /* Extracts the ALT_SYSMGR_CORE_WDDBG_MODE_0 field value from a register. */
351 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_GET(value) (((value) & 0x0000000f) >> 0)
352 /* Produces a ALT_SYSMGR_CORE_WDDBG_MODE_0 register field value suitable for setting the register. */
353 #define ALT_SYSMGR_CORE_WDDBG_MODE_0_SET(value) (((value) << 0) & 0x0000000f)
354 
355 /*
356  * Field : Debug Mode - mode_1
357  *
358  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
359  * matches L4 watchdog index.
360  *
361  * Field Enumeration Values:
362  *
363  * Enum | Value | Description
364  * :--------------------------------------------------------|:------|:------------
365  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_DONT_PAUSE | 0x0 |
366  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU0 | 0x1 |
367  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU1 | 0x2 |
368  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU2 | 0x4 |
369  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU3 | 0x8 |
370  * ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_ANY_CPU | 0xf |
371  *
372  * Field Access Macros:
373  *
374  */
375 /*
376  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
377  *
378  */
379 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_DONT_PAUSE 0x0
380 /*
381  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
382  *
383  */
384 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU0 0x1
385 /*
386  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
387  *
388  */
389 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU1 0x2
390 /*
391  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
392  *
393  */
394 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU2 0x4
395 /*
396  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
397  *
398  */
399 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_CPU3 0x8
400 /*
401  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_1
402  *
403  */
404 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_E_MODE_1_PAUSE_FOR_ANY_CPU 0xf
405 
406 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field. */
407 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_LSB 8
408 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field. */
409 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_MSB 11
410 /* The width in bits of the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field. */
411 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_WIDTH 4
412 /* The mask used to set the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field value. */
413 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_SET_MSK 0x00000f00
414 /* The mask used to clear the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field value. */
415 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_CLR_MSK 0xfffff0ff
416 /* The reset value of the ALT_SYSMGR_CORE_WDDBG_MODE_1 register field. */
417 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_RESET 0x8
418 /* Extracts the ALT_SYSMGR_CORE_WDDBG_MODE_1 field value from a register. */
419 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_GET(value) (((value) & 0x00000f00) >> 8)
420 /* Produces a ALT_SYSMGR_CORE_WDDBG_MODE_1 register field value suitable for setting the register. */
421 #define ALT_SYSMGR_CORE_WDDBG_MODE_1_SET(value) (((value) << 8) & 0x00000f00)
422 
423 /*
424  * Field : Debug Mode - mode_2
425  *
426  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
427  * matches L4 watchdog index.
428  *
429  * Field Enumeration Values:
430  *
431  * Enum | Value | Description
432  * :--------------------------------------------------------|:------|:------------
433  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_DONT_PAUSE | 0x0 |
434  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU0 | 0x1 |
435  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU1 | 0x2 |
436  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU2 | 0x4 |
437  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU3 | 0x8 |
438  * ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_ANY_CPU | 0xf |
439  *
440  * Field Access Macros:
441  *
442  */
443 /*
444  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
445  *
446  */
447 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_DONT_PAUSE 0x0
448 /*
449  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
450  *
451  */
452 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU0 0x1
453 /*
454  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
455  *
456  */
457 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU1 0x2
458 /*
459  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
460  *
461  */
462 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU2 0x4
463 /*
464  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
465  *
466  */
467 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_CPU3 0x8
468 /*
469  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_2
470  *
471  */
472 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_E_MODE_2_PAUSE_FOR_ANY_CPU 0xf
473 
474 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field. */
475 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_LSB 16
476 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field. */
477 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_MSB 19
478 /* The width in bits of the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field. */
479 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_WIDTH 4
480 /* The mask used to set the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field value. */
481 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_SET_MSK 0x000f0000
482 /* The mask used to clear the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field value. */
483 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_CLR_MSK 0xfff0ffff
484 /* The reset value of the ALT_SYSMGR_CORE_WDDBG_MODE_2 register field. */
485 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_RESET 0x8
486 /* Extracts the ALT_SYSMGR_CORE_WDDBG_MODE_2 field value from a register. */
487 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_GET(value) (((value) & 0x000f0000) >> 16)
488 /* Produces a ALT_SYSMGR_CORE_WDDBG_MODE_2 register field value suitable for setting the register. */
489 #define ALT_SYSMGR_CORE_WDDBG_MODE_2_SET(value) (((value) << 16) & 0x000f0000)
490 
491 /*
492  * Field : Debug Mode - mode_3
493  *
494  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
495  * matches L4 watchdog index.
496  *
497  * Field Enumeration Values:
498  *
499  * Enum | Value | Description
500  * :--------------------------------------------------------|:------|:------------
501  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_DONT_PAUSE | 0x0 |
502  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU0 | 0x1 |
503  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU1 | 0x2 |
504  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU2 | 0x4 |
505  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU3 | 0x8 |
506  * ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_ANY_CPU | 0xf |
507  *
508  * Field Access Macros:
509  *
510  */
511 /*
512  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
513  *
514  */
515 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_DONT_PAUSE 0x0
516 /*
517  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
518  *
519  */
520 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU0 0x1
521 /*
522  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
523  *
524  */
525 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU1 0x2
526 /*
527  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
528  *
529  */
530 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU2 0x4
531 /*
532  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
533  *
534  */
535 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_CPU3 0x8
536 /*
537  * Enumerated value for register field ALT_SYSMGR_CORE_WDDBG_MODE_3
538  *
539  */
540 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_E_MODE_3_PAUSE_FOR_ANY_CPU 0xf
541 
542 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field. */
543 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_LSB 24
544 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field. */
545 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_MSB 27
546 /* The width in bits of the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field. */
547 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_WIDTH 4
548 /* The mask used to set the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field value. */
549 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_SET_MSK 0x0f000000
550 /* The mask used to clear the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field value. */
551 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_CLR_MSK 0xf0ffffff
552 /* The reset value of the ALT_SYSMGR_CORE_WDDBG_MODE_3 register field. */
553 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_RESET 0x8
554 /* Extracts the ALT_SYSMGR_CORE_WDDBG_MODE_3 field value from a register. */
555 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_GET(value) (((value) & 0x0f000000) >> 24)
556 /* Produces a ALT_SYSMGR_CORE_WDDBG_MODE_3 register field value suitable for setting the register. */
557 #define ALT_SYSMGR_CORE_WDDBG_MODE_3_SET(value) (((value) << 24) & 0x0f000000)
558 
559 #ifndef __ASSEMBLY__
560 /*
561  * WARNING: The C register and register group struct declarations are provided for
562  * convenience and illustrative purposes. They should, however, be used with
563  * caution as the C language standard provides no guarantees about the alignment or
564  * atomicity of device memory accesses. The recommended practice for coding device
565  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
566  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
567  * alt_write_dword() functions for 64 bit registers.
568  *
569  * The struct declaration for register ALT_SYSMGR_CORE_WDDBG.
570  */
571 struct ALT_SYSMGR_CORE_WDDBG_s
572 {
573  volatile uint32_t mode_0 : 4; /* Debug Mode */
574  uint32_t : 4; /* *UNDEFINED* */
575  volatile uint32_t mode_1 : 4; /* Debug Mode */
576  uint32_t : 4; /* *UNDEFINED* */
577  volatile uint32_t mode_2 : 4; /* Debug Mode */
578  uint32_t : 4; /* *UNDEFINED* */
579  volatile uint32_t mode_3 : 4; /* Debug Mode */
580  uint32_t : 4; /* *UNDEFINED* */
581 };
582 
583 /* The typedef declaration for register ALT_SYSMGR_CORE_WDDBG. */
584 typedef struct ALT_SYSMGR_CORE_WDDBG_s ALT_SYSMGR_CORE_WDDBG_t;
585 #endif /* __ASSEMBLY__ */
586 
587 /* The reset value of the ALT_SYSMGR_CORE_WDDBG register. */
588 #define ALT_SYSMGR_CORE_WDDBG_RESET 0x08080808
589 /* The byte offset of the ALT_SYSMGR_CORE_WDDBG register from the beginning of the component. */
590 #define ALT_SYSMGR_CORE_WDDBG_OFST 0x8
591 
592 /*
593  * Register : mpu_status
594  *
595  * This is MPU control register
596  *
597  * Register Layout
598  *
599  * Bits | Access | Reset | Description
600  * :-------|:-------|:------|:-------------------------------------
601  * [0] | R | 0x0 | ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR
602  * [31:1] | ??? | 0x0 | *UNDEFINED*
603  *
604  */
605 /*
606  * Field : uncorrerr
607  *
608  * MPU sends 1 bit of ECC error signal(mpu_interrir_irq) to system manager. System
609  * manager synchronizes this
610  *
611  * signal, detects the assertion and then logs it mpu_status_uncorrerr register.
612  *
613  * Field Access Macros:
614  *
615  */
616 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field. */
617 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_LSB 0
618 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field. */
619 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_MSB 0
620 /* The width in bits of the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field. */
621 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_WIDTH 1
622 /* The mask used to set the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field value. */
623 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_SET_MSK 0x00000001
624 /* The mask used to clear the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field value. */
625 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_CLR_MSK 0xfffffffe
626 /* The reset value of the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field. */
627 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_RESET 0x0
628 /* Extracts the ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR field value from a register. */
629 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_GET(value) (((value) & 0x00000001) >> 0)
630 /* Produces a ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR register field value suitable for setting the register. */
631 #define ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR_SET(value) (((value) << 0) & 0x00000001)
632 
633 #ifndef __ASSEMBLY__
634 /*
635  * WARNING: The C register and register group struct declarations are provided for
636  * convenience and illustrative purposes. They should, however, be used with
637  * caution as the C language standard provides no guarantees about the alignment or
638  * atomicity of device memory accesses. The recommended practice for coding device
639  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
640  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
641  * alt_write_dword() functions for 64 bit registers.
642  *
643  * The struct declaration for register ALT_SYSMGR_CORE_MPU_STATUS.
644  */
645 struct ALT_SYSMGR_CORE_MPU_STATUS_s
646 {
647  const volatile uint32_t uncorrerr : 1; /* ALT_SYSMGR_CORE_MPU_STATUS_UNCORRERR */
648  uint32_t : 31; /* *UNDEFINED* */
649 };
650 
651 /* The typedef declaration for register ALT_SYSMGR_CORE_MPU_STATUS. */
652 typedef struct ALT_SYSMGR_CORE_MPU_STATUS_s ALT_SYSMGR_CORE_MPU_STATUS_t;
653 #endif /* __ASSEMBLY__ */
654 
655 /* The reset value of the ALT_SYSMGR_CORE_MPU_STATUS register. */
656 #define ALT_SYSMGR_CORE_MPU_STATUS_RESET 0x00000000
657 /* The byte offset of the ALT_SYSMGR_CORE_MPU_STATUS register from the beginning of the component. */
658 #define ALT_SYSMGR_CORE_MPU_STATUS_OFST 0x10
659 
660 /*
661  * Register : mpu_ace
662  *
663  * This is MPU control register
664  *
665  * Register Layout
666  *
667  * Bits | Access | Reset | Description
668  * :--------|:-------|:------|:------------------------------
669  * [3:0] | RW | 0x2 | ALT_SYSMGR_CORE_MPU_ACE_AWQOS
670  * [7:4] | ??? | 0x0 | *UNDEFINED*
671  * [12:8] | RW | 0x2 | ALT_SYSMGR_CORE_MPU_ACE_ARQOS
672  * [31:13] | ??? | 0x0 | *UNDEFINED*
673  *
674  */
675 /*
676  * Field : awqos
677  *
678  * Sets the Priority of all write transactions originating from the MPU ACE socket.
679  * Priority is used by interconnects and memory scheduler on the HPS. Defaults to
680  * the highest priority (>=2)
681  *
682  * Field Enumeration Values:
683  *
684  * Enum | Value | Description
685  * :-------------------------------------|:------|:------------
686  * ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_LOW | 0x0 |
687  * ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_MED | 0x1 |
688  * ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_HIGH | 0x2 |
689  *
690  * Field Access Macros:
691  *
692  */
693 /*
694  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_AWQOS
695  *
696  */
697 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_LOW 0x0
698 /*
699  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_AWQOS
700  *
701  */
702 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_MED 0x1
703 /*
704  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_AWQOS
705  *
706  */
707 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_E_HIGH 0x2
708 
709 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field. */
710 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_LSB 0
711 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field. */
712 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_MSB 3
713 /* The width in bits of the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field. */
714 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_WIDTH 4
715 /* The mask used to set the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field value. */
716 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_SET_MSK 0x0000000f
717 /* The mask used to clear the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field value. */
718 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_CLR_MSK 0xfffffff0
719 /* The reset value of the ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field. */
720 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_RESET 0x2
721 /* Extracts the ALT_SYSMGR_CORE_MPU_ACE_AWQOS field value from a register. */
722 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_GET(value) (((value) & 0x0000000f) >> 0)
723 /* Produces a ALT_SYSMGR_CORE_MPU_ACE_AWQOS register field value suitable for setting the register. */
724 #define ALT_SYSMGR_CORE_MPU_ACE_AWQOS_SET(value) (((value) << 0) & 0x0000000f)
725 
726 /*
727  * Field : arqos
728  *
729  * Sets the Priority of all write transactions originating from the MPU ACE socket.
730  * Priority is used by interconnects and memory scheduler on the HPS. Defaults to
731  * the highest priority (>=2)
732  *
733  * Field Enumeration Values:
734  *
735  * Enum | Value | Description
736  * :-------------------------------------|:------|:------------
737  * ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_LOW | 0x0 |
738  * ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_MED | 0x1 |
739  * ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_HIGH | 0x2 |
740  *
741  * Field Access Macros:
742  *
743  */
744 /*
745  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_ARQOS
746  *
747  */
748 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_LOW 0x0
749 /*
750  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_ARQOS
751  *
752  */
753 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_MED 0x1
754 /*
755  * Enumerated value for register field ALT_SYSMGR_CORE_MPU_ACE_ARQOS
756  *
757  */
758 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_E_HIGH 0x2
759 
760 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field. */
761 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_LSB 8
762 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field. */
763 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_MSB 12
764 /* The width in bits of the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field. */
765 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_WIDTH 5
766 /* The mask used to set the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field value. */
767 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_SET_MSK 0x00001f00
768 /* The mask used to clear the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field value. */
769 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_CLR_MSK 0xffffe0ff
770 /* The reset value of the ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field. */
771 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_RESET 0x2
772 /* Extracts the ALT_SYSMGR_CORE_MPU_ACE_ARQOS field value from a register. */
773 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_GET(value) (((value) & 0x00001f00) >> 8)
774 /* Produces a ALT_SYSMGR_CORE_MPU_ACE_ARQOS register field value suitable for setting the register. */
775 #define ALT_SYSMGR_CORE_MPU_ACE_ARQOS_SET(value) (((value) << 8) & 0x00001f00)
776 
777 #ifndef __ASSEMBLY__
778 /*
779  * WARNING: The C register and register group struct declarations are provided for
780  * convenience and illustrative purposes. They should, however, be used with
781  * caution as the C language standard provides no guarantees about the alignment or
782  * atomicity of device memory accesses. The recommended practice for coding device
783  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
784  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
785  * alt_write_dword() functions for 64 bit registers.
786  *
787  * The struct declaration for register ALT_SYSMGR_CORE_MPU_ACE.
788  */
789 struct ALT_SYSMGR_CORE_MPU_ACE_s
790 {
791  volatile uint32_t awqos : 4; /* ALT_SYSMGR_CORE_MPU_ACE_AWQOS */
792  uint32_t : 4; /* *UNDEFINED* */
793  volatile uint32_t arqos : 5; /* ALT_SYSMGR_CORE_MPU_ACE_ARQOS */
794  uint32_t : 19; /* *UNDEFINED* */
795 };
796 
797 /* The typedef declaration for register ALT_SYSMGR_CORE_MPU_ACE. */
798 typedef struct ALT_SYSMGR_CORE_MPU_ACE_s ALT_SYSMGR_CORE_MPU_ACE_t;
799 #endif /* __ASSEMBLY__ */
800 
801 /* The reset value of the ALT_SYSMGR_CORE_MPU_ACE register. */
802 #define ALT_SYSMGR_CORE_MPU_ACE_RESET 0x00000202
803 /* The byte offset of the ALT_SYSMGR_CORE_MPU_ACE register from the beginning of the component. */
804 #define ALT_SYSMGR_CORE_MPU_ACE_OFST 0x14
805 
806 /*
807  * Register : Control Register - dma
808  *
809  * Registers used by the DMA Controller. All fields are reset by a cold or warm
810  * reset.
811  *
812  * These register bits should be updated during system initialization prior to
813  * removing the DMA controller from reset. They may not be changed dynamically
814  * during DMA operation.
815  *
816  * Register Layout
817  *
818  * Bits | Access | Reset | Description
819  * :--------|:-------|:------|:------------------------
820  * [0] | RW | 0x0 | Channel Select I2C
821  * [3:1] | ??? | 0x0 | *UNDEFINED*
822  * [4] | RW | 0x0 | Channel Select I2C
823  * [15:5] | ??? | 0x0 | *UNDEFINED*
824  * [16] | RW | 0x0 | Manager Thread Security
825  * [23:17] | ??? | 0x0 | *UNDEFINED*
826  * [31:24] | RW | 0x0 | IRQ Security
827  *
828  */
829 /*
830  * Field : Channel Select I2C - chansel_0
831  *
832  * Channel 0 selects between FPGA and I2C4_EMAC_TX
833  *
834  * Field Enumeration Values:
835  *
836  * Enum | Value | Description
837  * :----------------------------------------|:------|:------------
838  * ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_FPGA | 0x0 |
839  * ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_I2C4_TX | 0x1 |
840  *
841  * Field Access Macros:
842  *
843  */
844 /*
845  * Enumerated value for register field ALT_SYSMGR_CORE_DMA_CHANSEL_0
846  *
847  */
848 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_FPGA 0x0
849 /*
850  * Enumerated value for register field ALT_SYSMGR_CORE_DMA_CHANSEL_0
851  *
852  */
853 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_E_I2C4_TX 0x1
854 
855 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field. */
856 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_LSB 0
857 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field. */
858 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_MSB 0
859 /* The width in bits of the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field. */
860 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_WIDTH 1
861 /* The mask used to set the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field value. */
862 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_SET_MSK 0x00000001
863 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field value. */
864 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_CLR_MSK 0xfffffffe
865 /* The reset value of the ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field. */
866 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_RESET 0x0
867 /* Extracts the ALT_SYSMGR_CORE_DMA_CHANSEL_0 field value from a register. */
868 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
869 /* Produces a ALT_SYSMGR_CORE_DMA_CHANSEL_0 register field value suitable for setting the register. */
870 #define ALT_SYSMGR_CORE_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
871 
872 /*
873  * Field : Channel Select I2C - chansel_1
874  *
875  * Channel 1 selects between FPGA and I2C4_EMAC_RX
876  *
877  * Field Enumeration Values:
878  *
879  * Enum | Value | Description
880  * :----------------------------------------|:------|:------------
881  * ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_FPGA | 0x0 |
882  * ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_I2C4_RX | 0x1 |
883  *
884  * Field Access Macros:
885  *
886  */
887 /*
888  * Enumerated value for register field ALT_SYSMGR_CORE_DMA_CHANSEL_1
889  *
890  */
891 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_FPGA 0x0
892 /*
893  * Enumerated value for register field ALT_SYSMGR_CORE_DMA_CHANSEL_1
894  *
895  */
896 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_E_I2C4_RX 0x1
897 
898 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field. */
899 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_LSB 4
900 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field. */
901 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_MSB 4
902 /* The width in bits of the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field. */
903 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_WIDTH 1
904 /* The mask used to set the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field value. */
905 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_SET_MSK 0x00000010
906 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field value. */
907 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_CLR_MSK 0xffffffef
908 /* The reset value of the ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field. */
909 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_RESET 0x0
910 /* Extracts the ALT_SYSMGR_CORE_DMA_CHANSEL_1 field value from a register. */
911 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4)
912 /* Produces a ALT_SYSMGR_CORE_DMA_CHANSEL_1 register field value suitable for setting the register. */
913 #define ALT_SYSMGR_CORE_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010)
914 
915 /*
916  * Field : Manager Thread Security - mgr_ns
917  *
918  * Specifies the security state of the DMA manager thread.
919  *
920  * 0 = assigns DMA manager to the Secure state.
921  *
922  * 1 = assigns DMA manager to the Non-secure state.
923  *
924  * Sampled by the DMA controller when it exits from reset.
925  *
926  * Field Access Macros:
927  *
928  */
929 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_MGR_NS register field. */
930 #define ALT_SYSMGR_CORE_DMA_MGR_NS_LSB 16
931 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_MGR_NS register field. */
932 #define ALT_SYSMGR_CORE_DMA_MGR_NS_MSB 16
933 /* The width in bits of the ALT_SYSMGR_CORE_DMA_MGR_NS register field. */
934 #define ALT_SYSMGR_CORE_DMA_MGR_NS_WIDTH 1
935 /* The mask used to set the ALT_SYSMGR_CORE_DMA_MGR_NS register field value. */
936 #define ALT_SYSMGR_CORE_DMA_MGR_NS_SET_MSK 0x00010000
937 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_MGR_NS register field value. */
938 #define ALT_SYSMGR_CORE_DMA_MGR_NS_CLR_MSK 0xfffeffff
939 /* The reset value of the ALT_SYSMGR_CORE_DMA_MGR_NS register field. */
940 #define ALT_SYSMGR_CORE_DMA_MGR_NS_RESET 0x0
941 /* Extracts the ALT_SYSMGR_CORE_DMA_MGR_NS field value from a register. */
942 #define ALT_SYSMGR_CORE_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16)
943 /* Produces a ALT_SYSMGR_CORE_DMA_MGR_NS register field value suitable for setting the register. */
944 #define ALT_SYSMGR_CORE_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000)
945 
946 /*
947  * Field : IRQ Security - irq_ns
948  *
949  * Specifies the security state of an event-interrupt resource.
950  *
951  * If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state.
952  *
953  * If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure
954  * state.
955  *
956  * Field Access Macros:
957  *
958  */
959 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_IRQ_NS register field. */
960 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_LSB 24
961 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_IRQ_NS register field. */
962 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_MSB 31
963 /* The width in bits of the ALT_SYSMGR_CORE_DMA_IRQ_NS register field. */
964 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_WIDTH 8
965 /* The mask used to set the ALT_SYSMGR_CORE_DMA_IRQ_NS register field value. */
966 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_SET_MSK 0xff000000
967 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_IRQ_NS register field value. */
968 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_CLR_MSK 0x00ffffff
969 /* The reset value of the ALT_SYSMGR_CORE_DMA_IRQ_NS register field. */
970 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_RESET 0x0
971 /* Extracts the ALT_SYSMGR_CORE_DMA_IRQ_NS field value from a register. */
972 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24)
973 /* Produces a ALT_SYSMGR_CORE_DMA_IRQ_NS register field value suitable for setting the register. */
974 #define ALT_SYSMGR_CORE_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000)
975 
976 #ifndef __ASSEMBLY__
977 /*
978  * WARNING: The C register and register group struct declarations are provided for
979  * convenience and illustrative purposes. They should, however, be used with
980  * caution as the C language standard provides no guarantees about the alignment or
981  * atomicity of device memory accesses. The recommended practice for coding device
982  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
983  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
984  * alt_write_dword() functions for 64 bit registers.
985  *
986  * The struct declaration for register ALT_SYSMGR_CORE_DMA.
987  */
988 struct ALT_SYSMGR_CORE_DMA_s
989 {
990  volatile uint32_t chansel_0 : 1; /* Channel Select I2C */
991  uint32_t : 3; /* *UNDEFINED* */
992  volatile uint32_t chansel_1 : 1; /* Channel Select I2C */
993  uint32_t : 11; /* *UNDEFINED* */
994  volatile uint32_t mgr_ns : 1; /* Manager Thread Security */
995  uint32_t : 7; /* *UNDEFINED* */
996  volatile uint32_t irq_ns : 8; /* IRQ Security */
997 };
998 
999 /* The typedef declaration for register ALT_SYSMGR_CORE_DMA. */
1000 typedef struct ALT_SYSMGR_CORE_DMA_s ALT_SYSMGR_CORE_DMA_t;
1001 #endif /* __ASSEMBLY__ */
1002 
1003 /* The reset value of the ALT_SYSMGR_CORE_DMA register. */
1004 #define ALT_SYSMGR_CORE_DMA_RESET 0x00000000
1005 /* The byte offset of the ALT_SYSMGR_CORE_DMA register from the beginning of the component. */
1006 #define ALT_SYSMGR_CORE_DMA_OFST 0x20
1007 
1008 /*
1009  * Register : Peripheral Security Register - dma_periph
1010  *
1011  * Controls the security state of a peripheral request interface. Sampled by the
1012  * DMA controller when it exits from reset.
1013  *
1014  * These register bits should be updated during system initialization prior to
1015  * removing the DMA controller from reset. They may not be changed dynamically
1016  * during DMA operation.
1017  *
1018  * Register Layout
1019  *
1020  * Bits | Access | Reset | Description
1021  * :-------|:-------|:------|:----------------------
1022  * [31:0] | RW | 0x0 | Peripheral Non-Secure
1023  *
1024  */
1025 /*
1026  * Field : Peripheral Non-Secure - ns
1027  *
1028  * If bit index [x] is 0, the DMA controller assigns peripheral request interface x
1029  * to the Secure state.
1030  *
1031  * If bit index [x] is 1, the DMA controller assigns peripheral request interface x
1032  * to the Non-secure state.
1033  *
1034  * Reset by a cold or warm reset.
1035  *
1036  * Field Access Macros:
1037  *
1038  */
1039 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field. */
1040 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_LSB 0
1041 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field. */
1042 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_MSB 31
1043 /* The width in bits of the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field. */
1044 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_WIDTH 32
1045 /* The mask used to set the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field value. */
1046 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_SET_MSK 0xffffffff
1047 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field value. */
1048 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_CLR_MSK 0x00000000
1049 /* The reset value of the ALT_SYSMGR_CORE_DMA_PERIPH_NS register field. */
1050 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_RESET 0x0
1051 /* Extracts the ALT_SYSMGR_CORE_DMA_PERIPH_NS field value from a register. */
1052 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_GET(value) (((value) & 0xffffffff) >> 0)
1053 /* Produces a ALT_SYSMGR_CORE_DMA_PERIPH_NS register field value suitable for setting the register. */
1054 #define ALT_SYSMGR_CORE_DMA_PERIPH_NS_SET(value) (((value) << 0) & 0xffffffff)
1055 
1056 #ifndef __ASSEMBLY__
1057 /*
1058  * WARNING: The C register and register group struct declarations are provided for
1059  * convenience and illustrative purposes. They should, however, be used with
1060  * caution as the C language standard provides no guarantees about the alignment or
1061  * atomicity of device memory accesses. The recommended practice for coding device
1062  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1063  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1064  * alt_write_dword() functions for 64 bit registers.
1065  *
1066  * The struct declaration for register ALT_SYSMGR_CORE_DMA_PERIPH.
1067  */
1068 struct ALT_SYSMGR_CORE_DMA_PERIPH_s
1069 {
1070  volatile uint32_t ns : 32; /* Peripheral Non-Secure */
1071 };
1072 
1073 /* The typedef declaration for register ALT_SYSMGR_CORE_DMA_PERIPH. */
1074 typedef struct ALT_SYSMGR_CORE_DMA_PERIPH_s ALT_SYSMGR_CORE_DMA_PERIPH_t;
1075 #endif /* __ASSEMBLY__ */
1076 
1077 /* The reset value of the ALT_SYSMGR_CORE_DMA_PERIPH register. */
1078 #define ALT_SYSMGR_CORE_DMA_PERIPH_RESET 0x00000000
1079 /* The byte offset of the ALT_SYSMGR_CORE_DMA_PERIPH register from the beginning of the component. */
1080 #define ALT_SYSMGR_CORE_DMA_PERIPH_OFST 0x24
1081 
1082 /*
1083  * Register : Control Register - sdmmc
1084  *
1085  * Registers used by the SDMMC Controller. All fields are reset by a cold or warm
1086  * reset.
1087  *
1088  * Register Layout
1089  *
1090  * Bits | Access | Reset | Description
1091  * :-------|:-------|:------|:--------------------------------
1092  * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select
1093  * [3] | ??? | 0x0 | *UNDEFINED*
1094  * [6:4] | RW | 0x0 | Sample Clock Phase Shift Select
1095  * [31:7] | ??? | 0x0 | *UNDEFINED*
1096  *
1097  */
1098 /*
1099  * Field : Drive Clock Phase Shift Select - drvsel
1100  *
1101  * Select which phase shift of the clock for cclk_in_drv.
1102  *
1103  * Field Enumeration Values:
1104  *
1105  * Enum | Value | Description
1106  * :------------------------------------------|:------|:------------
1107  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES0 | 0x0 |
1108  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES45 | 0x1 |
1109  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES90 | 0x2 |
1110  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES135 | 0x3 |
1111  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES180 | 0x4 |
1112  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES225 | 0x5 |
1113  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES270 | 0x6 |
1114  * ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES315 | 0x7 |
1115  *
1116  * Field Access Macros:
1117  *
1118  */
1119 /*
1120  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1121  *
1122  */
1123 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES0 0x0
1124 /*
1125  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1126  *
1127  */
1128 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES45 0x1
1129 /*
1130  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1131  *
1132  */
1133 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES90 0x2
1134 /*
1135  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1136  *
1137  */
1138 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES135 0x3
1139 /*
1140  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1141  *
1142  */
1143 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES180 0x4
1144 /*
1145  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1146  *
1147  */
1148 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES225 0x5
1149 /*
1150  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1151  *
1152  */
1153 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES270 0x6
1154 /*
1155  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_DRVSEL
1156  *
1157  */
1158 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_E_DEGREES315 0x7
1159 
1160 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field. */
1161 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_LSB 0
1162 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field. */
1163 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_MSB 2
1164 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field. */
1165 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_WIDTH 3
1166 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field value. */
1167 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_SET_MSK 0x00000007
1168 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field value. */
1169 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_CLR_MSK 0xfffffff8
1170 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_DRVSEL register field. */
1171 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_RESET 0x0
1172 /* Extracts the ALT_SYSMGR_CORE_SDMMC_DRVSEL field value from a register. */
1173 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
1174 /* Produces a ALT_SYSMGR_CORE_SDMMC_DRVSEL register field value suitable for setting the register. */
1175 #define ALT_SYSMGR_CORE_SDMMC_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
1176 
1177 /*
1178  * Field : Sample Clock Phase Shift Select - smplsel
1179  *
1180  * Select which phase shift of the clock for cclk_in_sample.
1181  *
1182  * Field Enumeration Values:
1183  *
1184  * Enum | Value | Description
1185  * :-------------------------------------------|:------|:------------
1186  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES0 | 0x0 |
1187  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES45 | 0x1 |
1188  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES90 | 0x2 |
1189  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES135 | 0x3 |
1190  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES180 | 0x4 |
1191  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES225 | 0x5 |
1192  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES270 | 0x6 |
1193  * ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES315 | 0x7 |
1194  *
1195  * Field Access Macros:
1196  *
1197  */
1198 /*
1199  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1200  *
1201  */
1202 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES0 0x0
1203 /*
1204  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1205  *
1206  */
1207 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES45 0x1
1208 /*
1209  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1210  *
1211  */
1212 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES90 0x2
1213 /*
1214  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1215  *
1216  */
1217 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES135 0x3
1218 /*
1219  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1220  *
1221  */
1222 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES180 0x4
1223 /*
1224  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1225  *
1226  */
1227 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES225 0x5
1228 /*
1229  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1230  *
1231  */
1232 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES270 0x6
1233 /*
1234  * Enumerated value for register field ALT_SYSMGR_CORE_SDMMC_SMPLSEL
1235  *
1236  */
1237 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_E_DEGREES315 0x7
1238 
1239 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field. */
1240 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_LSB 4
1241 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field. */
1242 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_MSB 6
1243 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field. */
1244 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_WIDTH 3
1245 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field value. */
1246 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_SET_MSK 0x00000070
1247 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field value. */
1248 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_CLR_MSK 0xffffff8f
1249 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field. */
1250 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_RESET 0x0
1251 /* Extracts the ALT_SYSMGR_CORE_SDMMC_SMPLSEL field value from a register. */
1252 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_GET(value) (((value) & 0x00000070) >> 4)
1253 /* Produces a ALT_SYSMGR_CORE_SDMMC_SMPLSEL register field value suitable for setting the register. */
1254 #define ALT_SYSMGR_CORE_SDMMC_SMPLSEL_SET(value) (((value) << 4) & 0x00000070)
1255 
1256 #ifndef __ASSEMBLY__
1257 /*
1258  * WARNING: The C register and register group struct declarations are provided for
1259  * convenience and illustrative purposes. They should, however, be used with
1260  * caution as the C language standard provides no guarantees about the alignment or
1261  * atomicity of device memory accesses. The recommended practice for coding device
1262  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1263  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1264  * alt_write_dword() functions for 64 bit registers.
1265  *
1266  * The struct declaration for register ALT_SYSMGR_CORE_SDMMC.
1267  */
1268 struct ALT_SYSMGR_CORE_SDMMC_s
1269 {
1270  volatile uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */
1271  uint32_t : 1; /* *UNDEFINED* */
1272  volatile uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */
1273  uint32_t : 25; /* *UNDEFINED* */
1274 };
1275 
1276 /* The typedef declaration for register ALT_SYSMGR_CORE_SDMMC. */
1277 typedef struct ALT_SYSMGR_CORE_SDMMC_s ALT_SYSMGR_CORE_SDMMC_t;
1278 #endif /* __ASSEMBLY__ */
1279 
1280 /* The reset value of the ALT_SYSMGR_CORE_SDMMC register. */
1281 #define ALT_SYSMGR_CORE_SDMMC_RESET 0x00000000
1282 /* The byte offset of the ALT_SYSMGR_CORE_SDMMC register from the beginning of the component. */
1283 #define ALT_SYSMGR_CORE_SDMMC_OFST 0x28
1284 
1285 /*
1286  * Register : SD/MMC L3 Master HPROT Register - sdmmc_l3master
1287  *
1288  * Controls the L3 master HPROT AHB-Lite signal.
1289  *
1290  * These register bits should be updated only during system initialization prior to
1291  * removing the peripheral from reset. They may not be changed dynamically during
1292  * peripheral operation
1293  *
1294  * All fields are reset by a cold or warm reset.
1295  *
1296  * Register Layout
1297  *
1298  * Bits | Access | Reset | Description
1299  * :--------|:-------|:------|:-------------------------------------
1300  * [3:0] | RW | 0x1 | ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT
1301  * [5:4] | RW | 0x0 | Global Interface
1302  * [7:6] | ??? | 0x0 | *UNDEFINED*
1303  * [9:8] | RW | 0x3 | Global Interface
1304  * [15:10] | ??? | 0x0 | *UNDEFINED*
1305  * [25:16] | RW | 0x0 | Global Interface
1306  * [31:26] | ??? | 0x0 | *UNDEFINED*
1307  *
1308  */
1309 /*
1310  * Field : hprot
1311  *
1312  * HPROT[3] Cachable
1313  *
1314  * 0: L3 master accesses for the module are non-cacheable.
1315  *
1316  * 1: L3 master accesses for the module are cacheable.
1317  *
1318  * ==========================
1319  *
1320  * HPROT[2] Bufferable
1321  *
1322  * 0: L3 master accesses for the module are not bufferable.
1323  *
1324  * 1: L3 master accesses for the module are bufferable.
1325  *
1326  * ==========================
1327  *
1328  * HPROT[1] Privileged
1329  *
1330  * 0: L3 master accesses for the module are not privileged.
1331  *
1332  * 1: L3 master accesses for the module are privileged.
1333  *
1334  * ==========================
1335  *
1336  * HPROT[0] Data/Opcode
1337  *
1338  * 0: Specifies if the L3 master access is for opcode
1339  *
1340  * 1: Specifies if the L3 master access is for data
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field. */
1346 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_LSB 0
1347 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field. */
1348 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_MSB 3
1349 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field. */
1350 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_WIDTH 4
1351 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field value. */
1352 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_SET_MSK 0x0000000f
1353 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field value. */
1354 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_CLR_MSK 0xfffffff0
1355 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field. */
1356 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_RESET 0x1
1357 /* Extracts the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT field value from a register. */
1358 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
1359 /* Produces a ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT register field value suitable for setting the register. */
1360 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
1361 
1362 /*
1363  * Field : Global Interface - hauser0_1
1364  *
1365  * bit[1] secure bit[0] allocate
1366  *
1367  * Field Access Macros:
1368  *
1369  */
1370 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field. */
1371 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_LSB 4
1372 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field. */
1373 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_MSB 5
1374 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field. */
1375 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_WIDTH 2
1376 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field value. */
1377 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_SET_MSK 0x00000030
1378 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field value. */
1379 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_CLR_MSK 0xffffffcf
1380 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field. */
1381 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_RESET 0x0
1382 /* Extracts the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 field value from a register. */
1383 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_GET(value) (((value) & 0x00000030) >> 4)
1384 /* Produces a ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1 register field value suitable for setting the register. */
1385 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER0_1_SET(value) (((value) << 4) & 0x00000030)
1386 
1387 /*
1388  * Field : Global Interface - hauser7_6
1389  *
1390  * bit[7:6] domai
1391  *
1392  * Field Access Macros:
1393  *
1394  */
1395 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field. */
1396 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_LSB 8
1397 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field. */
1398 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_MSB 9
1399 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field. */
1400 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_WIDTH 2
1401 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field value. */
1402 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_SET_MSK 0x00000300
1403 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field value. */
1404 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_CLR_MSK 0xfffffcff
1405 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field. */
1406 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_RESET 0x3
1407 /* Extracts the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 field value from a register. */
1408 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00000300) >> 8)
1409 /* Produces a ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6 register field value suitable for setting the register. */
1410 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER7_6_SET(value) (((value) << 8) & 0x00000300)
1411 
1412 /*
1413  * Field : Global Interface - hauser22_13
1414  *
1415  * bit[22:13] xsid
1416  *
1417  * Field Access Macros:
1418  *
1419  */
1420 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field. */
1421 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_LSB 16
1422 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field. */
1423 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_MSB 25
1424 /* The width in bits of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field. */
1425 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_WIDTH 10
1426 /* The mask used to set the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field value. */
1427 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
1428 /* The mask used to clear the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field value. */
1429 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
1430 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field. */
1431 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_RESET 0x0
1432 /* Extracts the ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 field value from a register. */
1433 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
1434 /* Produces a ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13 register field value suitable for setting the register. */
1435 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
1436 
1437 #ifndef __ASSEMBLY__
1438 /*
1439  * WARNING: The C register and register group struct declarations are provided for
1440  * convenience and illustrative purposes. They should, however, be used with
1441  * caution as the C language standard provides no guarantees about the alignment or
1442  * atomicity of device memory accesses. The recommended practice for coding device
1443  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1444  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1445  * alt_write_dword() functions for 64 bit registers.
1446  *
1447  * The struct declaration for register ALT_SYSMGR_CORE_SDMMC_L3MASTER.
1448  */
1449 struct ALT_SYSMGR_CORE_SDMMC_L3MASTER_s
1450 {
1451  volatile uint32_t hprot : 4; /* ALT_SYSMGR_CORE_SDMMC_L3MASTER_HPROT */
1452  volatile uint32_t hauser0_1 : 2; /* Global Interface */
1453  uint32_t : 2; /* *UNDEFINED* */
1454  volatile uint32_t hauser7_6 : 2; /* Global Interface */
1455  uint32_t : 6; /* *UNDEFINED* */
1456  volatile uint32_t hauser22_13 : 10; /* Global Interface */
1457  uint32_t : 6; /* *UNDEFINED* */
1458 };
1459 
1460 /* The typedef declaration for register ALT_SYSMGR_CORE_SDMMC_L3MASTER. */
1461 typedef struct ALT_SYSMGR_CORE_SDMMC_L3MASTER_s ALT_SYSMGR_CORE_SDMMC_L3MASTER_t;
1462 #endif /* __ASSEMBLY__ */
1463 
1464 /* The reset value of the ALT_SYSMGR_CORE_SDMMC_L3MASTER register. */
1465 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_RESET 0x00000301
1466 /* The byte offset of the ALT_SYSMGR_CORE_SDMMC_L3MASTER register from the beginning of the component. */
1467 #define ALT_SYSMGR_CORE_SDMMC_L3MASTER_OFST 0x2c
1468 
1469 /*
1470  * Register : Bootstrap Control Register - nand_bootstrap
1471  *
1472  * Bootstrap fields sampled by NAND Flash Controller when released from reset.
1473  *
1474  * All fields are reset by a cold or warm reset.
1475  *
1476  * Register Layout
1477  *
1478  * Bits | Access | Reset | Description
1479  * :--------|:-------|:------|:-------------------------------------------
1480  * [0] | RW | 0x0 | Bootstrap Inhibit Initialization
1481  * [7:1] | ??? | 0x0 | *UNDEFINED*
1482  * [8] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0
1483  * [15:9] | ??? | 0x0 | *UNDEFINED*
1484  * [16] | RW | 0x0 | Bootstrap Two Row Address Cycles
1485  * [23:17] | ??? | 0x0 | *UNDEFINED*
1486  * [24] | RW | 0x0 | Bootstrap 512 Byte Device
1487  * [27:25] | ??? | 0x0 | *UNDEFINED*
1488  * [28] | RW | 0x0 | ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16
1489  * [31:29] | ??? | 0x0 | *UNDEFINED*
1490  *
1491  */
1492 /*
1493  * Field : Bootstrap Inhibit Initialization - noinit
1494  *
1495  * If 1, inhibits NAND Flash Controller from performing initialization when coming
1496  * out of reset. Instead, software must program all registers pertaining to device
1497  * parameters like page size, width, etc.
1498  *
1499  * Field Access Macros:
1500  *
1501  */
1502 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field. */
1503 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_LSB 0
1504 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field. */
1505 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_MSB 0
1506 /* The width in bits of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field. */
1507 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_WIDTH 1
1508 /* The mask used to set the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field value. */
1509 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
1510 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field value. */
1511 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
1512 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field. */
1513 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_RESET 0x0
1514 /* Extracts the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT field value from a register. */
1515 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
1516 /* Produces a ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */
1517 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
1518 
1519 /*
1520  * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0
1521  *
1522  * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND
1523  * device as part of the initialization procedure.
1524  *
1525  * Field Access Macros:
1526  *
1527  */
1528 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field. */
1529 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_LSB 8
1530 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field. */
1531 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_MSB 8
1532 /* The width in bits of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field. */
1533 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_WIDTH 1
1534 /* The mask used to set the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field value. */
1535 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_SET_MSK 0x00000100
1536 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field value. */
1537 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_CLR_MSK 0xfffffeff
1538 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field. */
1539 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_RESET 0x0
1540 /* Extracts the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 field value from a register. */
1541 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_GET(value) (((value) & 0x00000100) >> 8)
1542 /* Produces a ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0 register field value suitable for setting the register. */
1543 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_NOLOADB0P0_SET(value) (((value) << 8) & 0x00000100)
1544 
1545 /*
1546  * Field : Bootstrap Two Row Address Cycles - tworowaddr
1547  *
1548  * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row
1549  * address cycles.
1550  *
1551  * Field Access Macros:
1552  *
1553  */
1554 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field. */
1555 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_LSB 16
1556 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field. */
1557 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_MSB 16
1558 /* The width in bits of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field. */
1559 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
1560 /* The mask used to set the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field value. */
1561 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00010000
1562 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field value. */
1563 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffeffff
1564 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field. */
1565 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
1566 /* Extracts the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */
1567 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00010000) >> 16)
1568 /* Produces a ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */
1569 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 16) & 0x00010000)
1570 
1571 /*
1572  * Field : Bootstrap 512 Byte Device - page512
1573  *
1574  * If 1, NAND device has a 512 byte page size.
1575  *
1576  * Field Access Macros:
1577  *
1578  */
1579 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field. */
1580 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_LSB 24
1581 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field. */
1582 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_MSB 24
1583 /* The width in bits of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field. */
1584 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_WIDTH 1
1585 /* The mask used to set the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field value. */
1586 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x01000000
1587 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field value. */
1588 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfeffffff
1589 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field. */
1590 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_RESET 0x0
1591 /* Extracts the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 field value from a register. */
1592 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x01000000) >> 24)
1593 /* Produces a ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */
1594 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 24) & 0x01000000)
1595 
1596 /*
1597  * Field : page512_x16
1598  *
1599  * Reset value - 0
1600  *
1601  * Field name: PAGE512_x16_DEVICE
1602  *
1603  * Description: If 1, NAND device has 512 bytes page size and I/O width is 16 bits.
1604  * This start should be asserted in case of 512 bytes devices only. This signal
1605  * must be stable and have proper value by the time Controller comes out of Reset
1606  *
1607  * Field Access Macros:
1608  *
1609  */
1610 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1611 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_LSB 28
1612 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1613 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_MSB 28
1614 /* The width in bits of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1615 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_WIDTH 1
1616 /* The mask used to set the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field value. */
1617 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_SET_MSK 0x10000000
1618 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field value. */
1619 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_CLR_MSK 0xefffffff
1620 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1621 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_RESET 0x0
1622 /* Extracts the ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 field value from a register. */
1623 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_GET(value) (((value) & 0x10000000) >> 28)
1624 /* Produces a ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 register field value suitable for setting the register. */
1625 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16_SET(value) (((value) << 28) & 0x10000000)
1626 
1627 #ifndef __ASSEMBLY__
1628 /*
1629  * WARNING: The C register and register group struct declarations are provided for
1630  * convenience and illustrative purposes. They should, however, be used with
1631  * caution as the C language standard provides no guarantees about the alignment or
1632  * atomicity of device memory accesses. The recommended practice for coding device
1633  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1634  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1635  * alt_write_dword() functions for 64 bit registers.
1636  *
1637  * The struct declaration for register ALT_SYSMGR_CORE_NAND_BOOTSTRAP.
1638  */
1639 struct ALT_SYSMGR_CORE_NAND_BOOTSTRAP_s
1640 {
1641  volatile uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */
1642  uint32_t : 7; /* *UNDEFINED* */
1643  volatile uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */
1644  uint32_t : 7; /* *UNDEFINED* */
1645  volatile uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */
1646  uint32_t : 7; /* *UNDEFINED* */
1647  volatile uint32_t page512 : 1; /* Bootstrap 512 Byte Device */
1648  uint32_t : 3; /* *UNDEFINED* */
1649  volatile uint32_t page512_x16 : 1; /* ALT_SYSMGR_CORE_NAND_BOOTSTRAP_PAGE512_X16 */
1650  uint32_t : 3; /* *UNDEFINED* */
1651 };
1652 
1653 /* The typedef declaration for register ALT_SYSMGR_CORE_NAND_BOOTSTRAP. */
1654 typedef struct ALT_SYSMGR_CORE_NAND_BOOTSTRAP_s ALT_SYSMGR_CORE_NAND_BOOTSTRAP_t;
1655 #endif /* __ASSEMBLY__ */
1656 
1657 /* The reset value of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP register. */
1658 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_RESET 0x00000000
1659 /* The byte offset of the ALT_SYSMGR_CORE_NAND_BOOTSTRAP register from the beginning of the component. */
1660 #define ALT_SYSMGR_CORE_NAND_BOOTSTRAP_OFST 0x30
1661 
1662 /*
1663  * Register : NAND L3 Master AxCACHE Register - nand_l3master
1664  *
1665  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
1666  *
1667  * These register bits should be updated only during system initialization prior to
1668  * removing the peripheral from reset. They may not be changed dynamically during
1669  * peripheral operation
1670  *
1671  * All fields are reset by a cold or warm reset.
1672  *
1673  * Register Layout
1674  *
1675  * Bits | Access | Reset | Description
1676  * :--------|:-------|:------|:---------------------------------------
1677  * [3:0] | RW | 0x0 | NAND ARCACHE
1678  * [7:4] | RW | 0x0 | NAND AWCACHE
1679  * [9:8] | RW | 0x3 | ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN
1680  * [11:10] | ??? | 0x0 | *UNDEFINED*
1681  * [13:12] | RW | 0x3 | ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN
1682  * [15:14] | ??? | 0x0 | *UNDEFINED*
1683  * [18:16] | RW | 0x0 | ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT
1684  * [19] | ??? | 0x0 | *UNDEFINED*
1685  * [22:20] | RW | 0x0 | ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT
1686  * [31:23] | ??? | 0x0 | *UNDEFINED*
1687  *
1688  */
1689 /*
1690  * Field : NAND ARCACHE - arcache_0
1691  *
1692  * Specifies the value of the module ARCACHE signal.
1693  *
1694  * Field Enumeration Values:
1695  *
1696  * Enum | Value | Description
1697  * :---------------------------------------------------------------|:------|:------------
1698  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 |
1699  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_BUFF | 0x1 |
1700  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_NONALLOC | 0x2 |
1701  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 |
1702  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED1 | 0x4 |
1703  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED2 | 0x5 |
1704  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 |
1705  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 |
1706  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED3 | 0x8 |
1707  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED4 | 0x9 |
1708  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa |
1709  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb |
1710  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED5 | 0xc |
1711  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED6 | 0xd |
1712  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe |
1713  * ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf |
1714  *
1715  * Field Access Macros:
1716  *
1717  */
1718 /*
1719  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1720  *
1721  */
1722 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
1723 /*
1724  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1725  *
1726  */
1727 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_BUFF 0x1
1728 /*
1729  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1730  *
1731  */
1732 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_NONALLOC 0x2
1733 /*
1734  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1735  *
1736  */
1737 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1738 /*
1739  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1740  *
1741  */
1742 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED1 0x4
1743 /*
1744  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1745  *
1746  */
1747 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED2 0x5
1748 /*
1749  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1750  *
1751  */
1752 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1753 /*
1754  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1755  *
1756  */
1757 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1758 /*
1759  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1760  *
1761  */
1762 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED3 0x8
1763 /*
1764  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1765  *
1766  */
1767 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED4 0x9
1768 /*
1769  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1770  *
1771  */
1772 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1773 /*
1774  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1775  *
1776  */
1777 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1778 /*
1779  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1780  *
1781  */
1782 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED5 0xc
1783 /*
1784  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1785  *
1786  */
1787 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_RESERVED6 0xd
1788 /*
1789  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1790  *
1791  */
1792 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1793 /*
1794  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0
1795  *
1796  */
1797 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1798 
1799 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field. */
1800 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_LSB 0
1801 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field. */
1802 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_MSB 3
1803 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field. */
1804 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_WIDTH 4
1805 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field value. */
1806 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_SET_MSK 0x0000000f
1807 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field value. */
1808 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_CLR_MSK 0xfffffff0
1809 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field. */
1810 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_RESET 0x0
1811 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 field value from a register. */
1812 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
1813 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0 register field value suitable for setting the register. */
1814 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
1815 
1816 /*
1817  * Field : NAND AWCACHE - awcache_0
1818  *
1819  * Specifies the value of the module AWCACHE signal.
1820  *
1821  * Field Enumeration Values:
1822  *
1823  * Enum | Value | Description
1824  * :---------------------------------------------------------------|:------|:------------
1825  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 |
1826  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_BUFF | 0x1 |
1827  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_NONALLOC | 0x2 |
1828  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 |
1829  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED1 | 0x4 |
1830  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED2 | 0x5 |
1831  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 |
1832  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 |
1833  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED3 | 0x8 |
1834  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED4 | 0x9 |
1835  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa |
1836  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb |
1837  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED5 | 0xc |
1838  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED6 | 0xd |
1839  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe |
1840  * ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf |
1841  *
1842  * Field Access Macros:
1843  *
1844  */
1845 /*
1846  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1847  *
1848  */
1849 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
1850 /*
1851  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1852  *
1853  */
1854 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_BUFF 0x1
1855 /*
1856  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1857  *
1858  */
1859 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_NONALLOC 0x2
1860 /*
1861  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1862  *
1863  */
1864 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1865 /*
1866  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1867  *
1868  */
1869 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED1 0x4
1870 /*
1871  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1872  *
1873  */
1874 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED2 0x5
1875 /*
1876  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1877  *
1878  */
1879 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1880 /*
1881  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1882  *
1883  */
1884 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1885 /*
1886  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1887  *
1888  */
1889 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED3 0x8
1890 /*
1891  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1892  *
1893  */
1894 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED4 0x9
1895 /*
1896  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1897  *
1898  */
1899 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1900 /*
1901  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1902  *
1903  */
1904 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1905 /*
1906  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1907  *
1908  */
1909 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED5 0xc
1910 /*
1911  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1912  *
1913  */
1914 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_RESERVED6 0xd
1915 /*
1916  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1917  *
1918  */
1919 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1920 /*
1921  * Enumerated value for register field ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0
1922  *
1923  */
1924 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1925 
1926 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field. */
1927 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_LSB 4
1928 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field. */
1929 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_MSB 7
1930 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field. */
1931 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_WIDTH 4
1932 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field value. */
1933 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_SET_MSK 0x000000f0
1934 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field value. */
1935 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_CLR_MSK 0xffffff0f
1936 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field. */
1937 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_RESET 0x0
1938 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 field value from a register. */
1939 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
1940 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0 register field value suitable for setting the register. */
1941 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
1942 
1943 /*
1944  * Field : awdomain
1945  *
1946  * aw domain register
1947  *
1948  * Field Access Macros:
1949  *
1950  */
1951 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field. */
1952 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_LSB 8
1953 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field. */
1954 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_MSB 9
1955 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field. */
1956 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_WIDTH 2
1957 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field value. */
1958 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_SET_MSK 0x00000300
1959 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field value. */
1960 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_CLR_MSK 0xfffffcff
1961 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field. */
1962 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_RESET 0x3
1963 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN field value from a register. */
1964 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00000300) >> 8)
1965 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN register field value suitable for setting the register. */
1966 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN_SET(value) (((value) << 8) & 0x00000300)
1967 
1968 /*
1969  * Field : ardomain
1970  *
1971  * ar domain register
1972  *
1973  * Field Access Macros:
1974  *
1975  */
1976 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field. */
1977 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_LSB 12
1978 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field. */
1979 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_MSB 13
1980 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field. */
1981 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_WIDTH 2
1982 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field value. */
1983 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_SET_MSK 0x00003000
1984 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field value. */
1985 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_CLR_MSK 0xffffcfff
1986 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field. */
1987 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_RESET 0x3
1988 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN field value from a register. */
1989 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
1990 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN register field value suitable for setting the register. */
1991 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN_SET(value) (((value) << 12) & 0x00003000)
1992 
1993 /*
1994  * Field : awprot
1995  *
1996  * aw prot register
1997  *
1998  * Field Access Macros:
1999  *
2000  */
2001 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field. */
2002 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_LSB 16
2003 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field. */
2004 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_MSB 18
2005 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field. */
2006 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_WIDTH 3
2007 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field value. */
2008 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_SET_MSK 0x00070000
2009 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field value. */
2010 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_CLR_MSK 0xfff8ffff
2011 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field. */
2012 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_RESET 0x0
2013 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT field value from a register. */
2014 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_GET(value) (((value) & 0x00070000) >> 16)
2015 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT register field value suitable for setting the register. */
2016 #define ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT_SET(value) (((value) << 16) & 0x00070000)
2017 
2018 /*
2019  * Field : arprot
2020  *
2021  * ar prot register
2022  *
2023  * Field Access Macros:
2024  *
2025  */
2026 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field. */
2027 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_LSB 20
2028 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field. */
2029 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_MSB 22
2030 /* The width in bits of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field. */
2031 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_WIDTH 3
2032 /* The mask used to set the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field value. */
2033 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_SET_MSK 0x00700000
2034 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field value. */
2035 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_CLR_MSK 0xff8fffff
2036 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field. */
2037 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_RESET 0x0
2038 /* Extracts the ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT field value from a register. */
2039 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_GET(value) (((value) & 0x00700000) >> 20)
2040 /* Produces a ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT register field value suitable for setting the register. */
2041 #define ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT_SET(value) (((value) << 20) & 0x00700000)
2042 
2043 #ifndef __ASSEMBLY__
2044 /*
2045  * WARNING: The C register and register group struct declarations are provided for
2046  * convenience and illustrative purposes. They should, however, be used with
2047  * caution as the C language standard provides no guarantees about the alignment or
2048  * atomicity of device memory accesses. The recommended practice for coding device
2049  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2050  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2051  * alt_write_dword() functions for 64 bit registers.
2052  *
2053  * The struct declaration for register ALT_SYSMGR_CORE_NAND_L3MASTER.
2054  */
2055 struct ALT_SYSMGR_CORE_NAND_L3MASTER_s
2056 {
2057  volatile uint32_t arcache_0 : 4; /* NAND ARCACHE */
2058  volatile uint32_t awcache_0 : 4; /* NAND AWCACHE */
2059  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_NAND_L3MASTER_AWDOMAIN */
2060  uint32_t : 2; /* *UNDEFINED* */
2061  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_NAND_L3MASTER_ARDOMAIN */
2062  uint32_t : 2; /* *UNDEFINED* */
2063  volatile uint32_t awprot : 3; /* ALT_SYSMGR_CORE_NAND_L3MASTER_AWPROT */
2064  uint32_t : 1; /* *UNDEFINED* */
2065  volatile uint32_t arprot : 3; /* ALT_SYSMGR_CORE_NAND_L3MASTER_ARPROT */
2066  uint32_t : 9; /* *UNDEFINED* */
2067 };
2068 
2069 /* The typedef declaration for register ALT_SYSMGR_CORE_NAND_L3MASTER. */
2070 typedef struct ALT_SYSMGR_CORE_NAND_L3MASTER_s ALT_SYSMGR_CORE_NAND_L3MASTER_t;
2071 #endif /* __ASSEMBLY__ */
2072 
2073 /* The reset value of the ALT_SYSMGR_CORE_NAND_L3MASTER register. */
2074 #define ALT_SYSMGR_CORE_NAND_L3MASTER_RESET 0x00003300
2075 /* The byte offset of the ALT_SYSMGR_CORE_NAND_L3MASTER register from the beginning of the component. */
2076 #define ALT_SYSMGR_CORE_NAND_L3MASTER_OFST 0x34
2077 
2078 /*
2079  * Register : USB L3 Master HPROT AHB-Lite Register - usb0_l3master
2080  *
2081  * Controls the L3 master HPROT AHB-Lite signal.
2082  *
2083  * These register bits should be updated only during system initialization prior to
2084  * removing the peripheral from reset. They may not be changed dynamically during
2085  * peripheral operation
2086  *
2087  * All fields are reset by a cold or warm reset.
2088  *
2089  * Register Layout
2090  *
2091  * Bits | Access | Reset | Description
2092  * :--------|:-------|:------|:------------------------------------------
2093  * [3:0] | RW | 0x1 | ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT
2094  * [7:4] | ??? | 0x0 | *UNDEFINED*
2095  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0
2096  * [9] | RW | 0x0 | ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1
2097  * [11:10] | ??? | 0x0 | *UNDEFINED*
2098  * [13:12] | RW | 0x3 | ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6
2099  * [15:14] | ??? | 0x0 | *UNDEFINED*
2100  * [25:16] | RW | 0x0 | ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13
2101  * [31:26] | ??? | 0x0 | *UNDEFINED*
2102  *
2103  */
2104 /*
2105  * Field : hprot
2106  *
2107  * HPROT[0]: Opcode/Data
2108  *
2109  * HPROT[1]: User/Privilege
2110  *
2111  * HPROT[2]: Non-Bufferable/Bufferable
2112  *
2113  * HPROT[3]: Non-Cacheable/Cacheable
2114  *
2115  * Field Access Macros:
2116  *
2117  */
2118 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field. */
2119 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_LSB 0
2120 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field. */
2121 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_MSB 3
2122 /* The width in bits of the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field. */
2123 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_WIDTH 4
2124 /* The mask used to set the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field value. */
2125 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_SET_MSK 0x0000000f
2126 /* The mask used to clear the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field value. */
2127 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_CLR_MSK 0xfffffff0
2128 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field. */
2129 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_RESET 0x1
2130 /* Extracts the ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT field value from a register. */
2131 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2132 /* Produces a ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT register field value suitable for setting the register. */
2133 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2134 
2135 /*
2136  * Field : hauser_0
2137  *
2138  * hauser[0] allocate
2139  *
2140  * Field Access Macros:
2141  *
2142  */
2143 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field. */
2144 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_LSB 8
2145 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field. */
2146 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_MSB 8
2147 /* The width in bits of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field. */
2148 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_WIDTH 1
2149 /* The mask used to set the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field value. */
2150 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_SET_MSK 0x00000100
2151 /* The mask used to clear the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field value. */
2152 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_CLR_MSK 0xfffffeff
2153 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field. */
2154 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_RESET 0x0
2155 /* Extracts the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 field value from a register. */
2156 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_GET(value) (((value) & 0x00000100) >> 8)
2157 /* Produces a ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 register field value suitable for setting the register. */
2158 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0_SET(value) (((value) << 8) & 0x00000100)
2159 
2160 /*
2161  * Field : hauser_1
2162  *
2163  * hauser[1] secure
2164  *
2165  * Field Access Macros:
2166  *
2167  */
2168 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field. */
2169 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_LSB 9
2170 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field. */
2171 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_MSB 9
2172 /* The width in bits of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field. */
2173 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_WIDTH 1
2174 /* The mask used to set the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field value. */
2175 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_SET_MSK 0x00000200
2176 /* The mask used to clear the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field value. */
2177 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_CLR_MSK 0xfffffdff
2178 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field. */
2179 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_RESET 0x0
2180 /* Extracts the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 field value from a register. */
2181 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_GET(value) (((value) & 0x00000200) >> 9)
2182 /* Produces a ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 register field value suitable for setting the register. */
2183 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1_SET(value) (((value) << 9) & 0x00000200)
2184 
2185 /*
2186  * Field : hauser7_6
2187  *
2188  * hauser[7:6]
2189  *
2190  * Field Access Macros:
2191  *
2192  */
2193 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field. */
2194 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_LSB 12
2195 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field. */
2196 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_MSB 13
2197 /* The width in bits of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field. */
2198 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_WIDTH 2
2199 /* The mask used to set the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field value. */
2200 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_SET_MSK 0x00003000
2201 /* The mask used to clear the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field value. */
2202 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_CLR_MSK 0xffffcfff
2203 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field. */
2204 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_RESET 0x3
2205 /* Extracts the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 field value from a register. */
2206 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00003000) >> 12)
2207 /* Produces a ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 register field value suitable for setting the register. */
2208 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6_SET(value) (((value) << 12) & 0x00003000)
2209 
2210 /*
2211  * Field : hauser22_13
2212  *
2213  * hauser[22:13]
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field. */
2219 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_LSB 16
2220 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field. */
2221 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_MSB 25
2222 /* The width in bits of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field. */
2223 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_WIDTH 10
2224 /* The mask used to set the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field value. */
2225 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
2226 /* The mask used to clear the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field value. */
2227 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
2228 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field. */
2229 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_RESET 0x0
2230 /* Extracts the ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 field value from a register. */
2231 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
2232 /* Produces a ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 register field value suitable for setting the register. */
2233 #define ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
2234 
2235 #ifndef __ASSEMBLY__
2236 /*
2237  * WARNING: The C register and register group struct declarations are provided for
2238  * convenience and illustrative purposes. They should, however, be used with
2239  * caution as the C language standard provides no guarantees about the alignment or
2240  * atomicity of device memory accesses. The recommended practice for coding device
2241  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2242  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2243  * alt_write_dword() functions for 64 bit registers.
2244  *
2245  * The struct declaration for register ALT_SYSMGR_CORE_USB0_L3MASTER.
2246  */
2247 struct ALT_SYSMGR_CORE_USB0_L3MASTER_s
2248 {
2249  volatile uint32_t hprot : 4; /* ALT_SYSMGR_CORE_USB0_L3MASTER_HPROT */
2250  uint32_t : 4; /* *UNDEFINED* */
2251  volatile uint32_t hauser_0 : 1; /* ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_0 */
2252  volatile uint32_t hauser_1 : 1; /* ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER_1 */
2253  uint32_t : 2; /* *UNDEFINED* */
2254  volatile uint32_t hauser7_6 : 2; /* ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER7_6 */
2255  uint32_t : 2; /* *UNDEFINED* */
2256  volatile uint32_t hauser22_13 : 10; /* ALT_SYSMGR_CORE_USB0_L3MASTER_HAUSER22_13 */
2257  uint32_t : 6; /* *UNDEFINED* */
2258 };
2259 
2260 /* The typedef declaration for register ALT_SYSMGR_CORE_USB0_L3MASTER. */
2261 typedef struct ALT_SYSMGR_CORE_USB0_L3MASTER_s ALT_SYSMGR_CORE_USB0_L3MASTER_t;
2262 #endif /* __ASSEMBLY__ */
2263 
2264 /* The reset value of the ALT_SYSMGR_CORE_USB0_L3MASTER register. */
2265 #define ALT_SYSMGR_CORE_USB0_L3MASTER_RESET 0x00003001
2266 /* The byte offset of the ALT_SYSMGR_CORE_USB0_L3MASTER register from the beginning of the component. */
2267 #define ALT_SYSMGR_CORE_USB0_L3MASTER_OFST 0x38
2268 
2269 /*
2270  * Register : USB L3 Master HPROT AHB-Lite Register - usb1_l3master
2271  *
2272  * Controls the L3 master HPROT AHB-Lite signal.
2273  *
2274  * These register bits should be updated only during system initialization prior to
2275  * removing the peripheral from reset. They may not be changed dynamically during
2276  * peripheral operation
2277  *
2278  * All fields are reset by a cold or warm reset.
2279  *
2280  * Register Layout
2281  *
2282  * Bits | Access | Reset | Description
2283  * :--------|:-------|:------|:------------------------------------------
2284  * [3:0] | RW | 0x1 | ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT
2285  * [7:4] | ??? | 0x0 | *UNDEFINED*
2286  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0
2287  * [9] | RW | 0x0 | ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1
2288  * [11:10] | ??? | 0x0 | *UNDEFINED*
2289  * [13:12] | RW | 0x3 | ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6
2290  * [15:14] | ??? | 0x0 | *UNDEFINED*
2291  * [25:16] | RW | 0x0 | ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13
2292  * [31:26] | ??? | 0x0 | *UNDEFINED*
2293  *
2294  */
2295 /*
2296  * Field : hprot
2297  *
2298  * HPROT[0]: Opcode/Data
2299  *
2300  * HPROT[1]: User/Privilege
2301  *
2302  * HPROT[2]: Non-Bufferable/Bufferable
2303  *
2304  * HPROT[3]: Non-Cacheable/Cacheable
2305  *
2306  * Field Access Macros:
2307  *
2308  */
2309 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field. */
2310 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_LSB 0
2311 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field. */
2312 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_MSB 3
2313 /* The width in bits of the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field. */
2314 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_WIDTH 4
2315 /* The mask used to set the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field value. */
2316 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_SET_MSK 0x0000000f
2317 /* The mask used to clear the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field value. */
2318 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_CLR_MSK 0xfffffff0
2319 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field. */
2320 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_RESET 0x1
2321 /* Extracts the ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT field value from a register. */
2322 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2323 /* Produces a ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT register field value suitable for setting the register. */
2324 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2325 
2326 /*
2327  * Field : hauser_0
2328  *
2329  * hauser[0] allocate
2330  *
2331  * Field Access Macros:
2332  *
2333  */
2334 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field. */
2335 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_LSB 8
2336 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field. */
2337 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_MSB 8
2338 /* The width in bits of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field. */
2339 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_WIDTH 1
2340 /* The mask used to set the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field value. */
2341 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_SET_MSK 0x00000100
2342 /* The mask used to clear the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field value. */
2343 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_CLR_MSK 0xfffffeff
2344 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field. */
2345 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_RESET 0x0
2346 /* Extracts the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 field value from a register. */
2347 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_GET(value) (((value) & 0x00000100) >> 8)
2348 /* Produces a ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 register field value suitable for setting the register. */
2349 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0_SET(value) (((value) << 8) & 0x00000100)
2350 
2351 /*
2352  * Field : hauser_1
2353  *
2354  * hauser[1] secure
2355  *
2356  * Field Access Macros:
2357  *
2358  */
2359 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field. */
2360 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_LSB 9
2361 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field. */
2362 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_MSB 9
2363 /* The width in bits of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field. */
2364 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_WIDTH 1
2365 /* The mask used to set the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field value. */
2366 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_SET_MSK 0x00000200
2367 /* The mask used to clear the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field value. */
2368 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_CLR_MSK 0xfffffdff
2369 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field. */
2370 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_RESET 0x0
2371 /* Extracts the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 field value from a register. */
2372 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_GET(value) (((value) & 0x00000200) >> 9)
2373 /* Produces a ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 register field value suitable for setting the register. */
2374 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1_SET(value) (((value) << 9) & 0x00000200)
2375 
2376 /*
2377  * Field : hauser7_6
2378  *
2379  * hauser[7:6] domain
2380  *
2381  * Field Access Macros:
2382  *
2383  */
2384 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field. */
2385 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_LSB 12
2386 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field. */
2387 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_MSB 13
2388 /* The width in bits of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field. */
2389 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_WIDTH 2
2390 /* The mask used to set the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field value. */
2391 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_SET_MSK 0x00003000
2392 /* The mask used to clear the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field value. */
2393 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_CLR_MSK 0xffffcfff
2394 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field. */
2395 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_RESET 0x3
2396 /* Extracts the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 field value from a register. */
2397 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_GET(value) (((value) & 0x00003000) >> 12)
2398 /* Produces a ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 register field value suitable for setting the register. */
2399 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6_SET(value) (((value) << 12) & 0x00003000)
2400 
2401 /*
2402  * Field : hauser22_13
2403  *
2404  * hauser[22:13] sid
2405  *
2406  * Field Access Macros:
2407  *
2408  */
2409 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field. */
2410 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_LSB 16
2411 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field. */
2412 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_MSB 25
2413 /* The width in bits of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field. */
2414 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_WIDTH 10
2415 /* The mask used to set the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field value. */
2416 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_SET_MSK 0x03ff0000
2417 /* The mask used to clear the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field value. */
2418 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_CLR_MSK 0xfc00ffff
2419 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field. */
2420 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_RESET 0x0
2421 /* Extracts the ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 field value from a register. */
2422 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_GET(value) (((value) & 0x03ff0000) >> 16)
2423 /* Produces a ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 register field value suitable for setting the register. */
2424 #define ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13_SET(value) (((value) << 16) & 0x03ff0000)
2425 
2426 #ifndef __ASSEMBLY__
2427 /*
2428  * WARNING: The C register and register group struct declarations are provided for
2429  * convenience and illustrative purposes. They should, however, be used with
2430  * caution as the C language standard provides no guarantees about the alignment or
2431  * atomicity of device memory accesses. The recommended practice for coding device
2432  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2433  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2434  * alt_write_dword() functions for 64 bit registers.
2435  *
2436  * The struct declaration for register ALT_SYSMGR_CORE_USB1_L3MASTER.
2437  */
2438 struct ALT_SYSMGR_CORE_USB1_L3MASTER_s
2439 {
2440  volatile uint32_t hprot : 4; /* ALT_SYSMGR_CORE_USB1_L3MASTER_HPROT */
2441  uint32_t : 4; /* *UNDEFINED* */
2442  volatile uint32_t hauser_0 : 1; /* ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_0 */
2443  volatile uint32_t hauser_1 : 1; /* ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER_1 */
2444  uint32_t : 2; /* *UNDEFINED* */
2445  volatile uint32_t hauser7_6 : 2; /* ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER7_6 */
2446  uint32_t : 2; /* *UNDEFINED* */
2447  volatile uint32_t hauser22_13 : 10; /* ALT_SYSMGR_CORE_USB1_L3MASTER_HAUSER22_13 */
2448  uint32_t : 6; /* *UNDEFINED* */
2449 };
2450 
2451 /* The typedef declaration for register ALT_SYSMGR_CORE_USB1_L3MASTER. */
2452 typedef struct ALT_SYSMGR_CORE_USB1_L3MASTER_s ALT_SYSMGR_CORE_USB1_L3MASTER_t;
2453 #endif /* __ASSEMBLY__ */
2454 
2455 /* The reset value of the ALT_SYSMGR_CORE_USB1_L3MASTER register. */
2456 #define ALT_SYSMGR_CORE_USB1_L3MASTER_RESET 0x00003001
2457 /* The byte offset of the ALT_SYSMGR_CORE_USB1_L3MASTER register from the beginning of the component. */
2458 #define ALT_SYSMGR_CORE_USB1_L3MASTER_OFST 0x3c
2459 
2460 /*
2461  * Register : EMAC L3 Master AxCACHE Register - emac_global
2462  *
2463  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
2464  *
2465  * These register bits should be updated only during system initialization prior to
2466  * removing the peripheral from reset. They may not be changed dynamically during
2467  * peripheral operation
2468  *
2469  * All fields are reset by a cold or warm reset.
2470  *
2471  * Register Layout
2472  *
2473  * Bits | Access | Reset | Description
2474  * :-------|:-------|:------|:-----------------
2475  * [0] | RW | 0x0 | PTP Clock Select
2476  * [31:1] | ??? | 0x0 | *UNDEFINED*
2477  *
2478  */
2479 /*
2480  * Field : PTP Clock Select - ptp_clk_sel
2481  *
2482  * Selects the source of the PTP reference clock between emac_ptp_clk from the
2483  * Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric.
2484  *
2485  * Field Enumeration Values:
2486  *
2487  * Enum | Value | Description
2488  * :----------------------------------------------------------|:------|:------------
2489  * ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_EMAC_PTP_CLK | 0x0 |
2490  * ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_F2S_PTP_REF_CLK | 0x1 |
2491  *
2492  * Field Access Macros:
2493  *
2494  */
2495 /*
2496  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL
2497  *
2498  */
2499 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_EMAC_PTP_CLK 0x0
2500 /*
2501  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL
2502  *
2503  */
2504 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_E_F2S_PTP_REF_CLK 0x1
2505 
2506 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field. */
2507 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_LSB 0
2508 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field. */
2509 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_MSB 0
2510 /* The width in bits of the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field. */
2511 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_WIDTH 1
2512 /* The mask used to set the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field value. */
2513 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_SET_MSK 0x00000001
2514 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field value. */
2515 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_CLR_MSK 0xfffffffe
2516 /* The reset value of the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field. */
2517 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_RESET 0x0
2518 /* Extracts the ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL field value from a register. */
2519 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_GET(value) (((value) & 0x00000001) >> 0)
2520 /* Produces a ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL register field value suitable for setting the register. */
2521 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_PTP_CLK_SEL_SET(value) (((value) << 0) & 0x00000001)
2522 
2523 #ifndef __ASSEMBLY__
2524 /*
2525  * WARNING: The C register and register group struct declarations are provided for
2526  * convenience and illustrative purposes. They should, however, be used with
2527  * caution as the C language standard provides no guarantees about the alignment or
2528  * atomicity of device memory accesses. The recommended practice for coding device
2529  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2530  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2531  * alt_write_dword() functions for 64 bit registers.
2532  *
2533  * The struct declaration for register ALT_SYSMGR_CORE_EMAC_GLOBAL.
2534  */
2535 struct ALT_SYSMGR_CORE_EMAC_GLOBAL_s
2536 {
2537  volatile uint32_t ptp_clk_sel : 1; /* PTP Clock Select */
2538  uint32_t : 31; /* *UNDEFINED* */
2539 };
2540 
2541 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC_GLOBAL. */
2542 typedef struct ALT_SYSMGR_CORE_EMAC_GLOBAL_s ALT_SYSMGR_CORE_EMAC_GLOBAL_t;
2543 #endif /* __ASSEMBLY__ */
2544 
2545 /* The reset value of the ALT_SYSMGR_CORE_EMAC_GLOBAL register. */
2546 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_RESET 0x00000000
2547 /* The byte offset of the ALT_SYSMGR_CORE_EMAC_GLOBAL register from the beginning of the component. */
2548 #define ALT_SYSMGR_CORE_EMAC_GLOBAL_OFST 0x40
2549 
2550 /*
2551  * Register : Control Register - emac0
2552  *
2553  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
2554  *
2555  * Register Layout
2556  *
2557  * Bits | Access | Reset | Description
2558  * :--------|:-------|:------|:------------------------------------------
2559  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL
2560  * [7:2] | ??? | 0x0 | *UNDEFINED*
2561  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL
2562  * [11:9] | ??? | 0x0 | *UNDEFINED*
2563  * [12] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL
2564  * [15:13] | ??? | 0x0 | *UNDEFINED*
2565  * [19:16] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_ARCACHE
2566  * [23:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_AWCACHE
2567  * [26:24] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC0_ARPROT
2568  * [29:27] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC0_AWPROT
2569  * [30] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS
2570  * [31] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE
2571  *
2572  */
2573 /*
2574  * Field : phy_intf_sel
2575  *
2576  * PHY Interface Select
2577  *
2578  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
2579  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
2580  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
2581  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
2582  * clocks use the Clock Manager reference rather than depending on the PHY to have
2583  * active clocks.
2584  *
2585  * Field Enumeration Values:
2586  *
2587  * Enum | Value | Description
2588  * :----------------------------------------------|:------|:------------
2589  * ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_GMII_MII | 0x0 |
2590  * ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RGMII | 0x1 |
2591  * ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RMII | 0x2 |
2592  * ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RESET | 0x3 |
2593  *
2594  * Field Access Macros:
2595  *
2596  */
2597 /*
2598  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL
2599  *
2600  */
2601 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_GMII_MII 0x0
2602 /*
2603  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL
2604  *
2605  */
2606 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
2607 /*
2608  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL
2609  *
2610  */
2611 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RMII 0x2
2612 /*
2613  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL
2614  *
2615  */
2616 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RESET 0x3
2617 
2618 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field. */
2619 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_LSB 0
2620 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field. */
2621 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_MSB 1
2622 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field. */
2623 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_WIDTH 2
2624 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field value. */
2625 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
2626 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field value. */
2627 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_CLR_MSK 0xfffffffc
2628 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field. */
2629 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_RESET 0x3
2630 /* Extracts the ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL field value from a register. */
2631 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
2632 /* Produces a ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL register field value suitable for setting the register. */
2633 #define ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
2634 
2635 /*
2636  * Field : ptp_ref_sel
2637  *
2638  * This field selects if the Timestamp reference is internally or externally
2639  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
2640  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
2641  * Internal or External.
2642  *
2643  * Field Enumeration Values:
2644  *
2645  * Enum | Value | Description
2646  * :---------------------------------------------|:------|:------------
2647  * ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_INTERNAL | 0x0 |
2648  * ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_EXTERNAL | 0x1 |
2649  *
2650  * Field Access Macros:
2651  *
2652  */
2653 /*
2654  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL
2655  *
2656  */
2657 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_INTERNAL 0x0
2658 /*
2659  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL
2660  *
2661  */
2662 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_E_EXTERNAL 0x1
2663 
2664 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field. */
2665 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_LSB 8
2666 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field. */
2667 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_MSB 8
2668 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field. */
2669 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_WIDTH 1
2670 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field value. */
2671 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_SET_MSK 0x00000100
2672 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field value. */
2673 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_CLR_MSK 0xfffffeff
2674 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field. */
2675 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_RESET 0x0
2676 /* Extracts the ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL field value from a register. */
2677 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
2678 /* Produces a ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL register field value suitable for setting the register. */
2679 #define ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
2680 
2681 /*
2682  * Field : app_clk_sel
2683  *
2684  * Selects the source of the Application clock for the datapath to either l4_mp_clk
2685  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
2686  * the FPGA fabric.
2687  *
2688  * Field Enumeration Values:
2689  *
2690  * Enum | Value | Description
2691  * :-----------------------------------------------|:------|:------------
2692  * ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
2693  * ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
2694  *
2695  * Field Access Macros:
2696  *
2697  */
2698 /*
2699  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL
2700  *
2701  */
2702 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_L4_MP_CLK 0x0
2703 /*
2704  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL
2705  *
2706  */
2707 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK 0x1
2708 
2709 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field. */
2710 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_LSB 12
2711 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field. */
2712 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_MSB 12
2713 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field. */
2714 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_WIDTH 1
2715 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field value. */
2716 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_SET_MSK 0x00001000
2717 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field value. */
2718 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_CLR_MSK 0xffffefff
2719 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field. */
2720 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_RESET 0x0
2721 /* Extracts the ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL field value from a register. */
2722 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
2723 /* Produces a ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL register field value suitable for setting the register. */
2724 #define ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
2725 
2726 /*
2727  * Field : arcache
2728  *
2729  * Specifies the values of the 2 EMAC ARCACHE signals.
2730  *
2731  * The field array index corresponds to the EMAC index.
2732  *
2733  * Field Enumeration Values:
2734  *
2735  * Enum | Value | Description
2736  * :-----------------------------------------------------|:------|:------------
2737  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_NONCACHE_NONBUFF | 0x0 |
2738  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_BUFF | 0x1 |
2739  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_NONALLOC | 0x2 |
2740  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
2741  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED1 | 0x4 |
2742  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED2 | 0x5 |
2743  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
2744  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
2745  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED3 | 0x8 |
2746  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED4 | 0x9 |
2747  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
2748  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
2749  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED5 | 0xc |
2750  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED6 | 0xd |
2751  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
2752  * ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
2753  *
2754  * Field Access Macros:
2755  *
2756  */
2757 /*
2758  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2759  *
2760  */
2761 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_NONCACHE_NONBUFF 0x0
2762 /*
2763  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2764  *
2765  */
2766 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_BUFF 0x1
2767 /*
2768  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2769  *
2770  */
2771 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_NONALLOC 0x2
2772 /*
2773  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2774  *
2775  */
2776 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
2777 /*
2778  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2779  *
2780  */
2781 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED1 0x4
2782 /*
2783  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2784  *
2785  */
2786 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED2 0x5
2787 /*
2788  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2789  *
2790  */
2791 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2792 /*
2793  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2794  *
2795  */
2796 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2797 /*
2798  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2799  *
2800  */
2801 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED3 0x8
2802 /*
2803  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2804  *
2805  */
2806 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED4 0x9
2807 /*
2808  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2809  *
2810  */
2811 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2812 /*
2813  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2814  *
2815  */
2816 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2817 /*
2818  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2819  *
2820  */
2821 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED5 0xc
2822 /*
2823  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2824  *
2825  */
2826 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_RESERVED6 0xd
2827 /*
2828  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2829  *
2830  */
2831 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2832 /*
2833  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARCACHE
2834  *
2835  */
2836 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
2837 
2838 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field. */
2839 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_LSB 16
2840 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field. */
2841 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_MSB 19
2842 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field. */
2843 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_WIDTH 4
2844 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field value. */
2845 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_SET_MSK 0x000f0000
2846 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field value. */
2847 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_CLR_MSK 0xfff0ffff
2848 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ARCACHE register field. */
2849 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_RESET 0x0
2850 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ARCACHE field value from a register. */
2851 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
2852 /* Produces a ALT_SYSMGR_CORE_EMAC0_ARCACHE register field value suitable for setting the register. */
2853 #define ALT_SYSMGR_CORE_EMAC0_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
2854 
2855 /*
2856  * Field : awcache
2857  *
2858  * Specifies the values of the 2 EMAC AWCACHE signals.
2859  *
2860  * The field array index corresponds to the EMAC index.
2861  *
2862  * Field Enumeration Values:
2863  *
2864  * Enum | Value | Description
2865  * :-----------------------------------------------------|:------|:------------
2866  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
2867  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_BUFF | 0x1 |
2868  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_NONALLOC | 0x2 |
2869  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
2870  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED1 | 0x4 |
2871  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED2 | 0x5 |
2872  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
2873  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
2874  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED3 | 0x8 |
2875  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED4 | 0x9 |
2876  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
2877  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
2878  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED5 | 0xc |
2879  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED6 | 0xd |
2880  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
2881  * ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
2882  *
2883  * Field Access Macros:
2884  *
2885  */
2886 /*
2887  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2888  *
2889  */
2890 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_NONCACHE_NONBUFF 0x0
2891 /*
2892  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2893  *
2894  */
2895 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_BUFF 0x1
2896 /*
2897  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2898  *
2899  */
2900 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_NONALLOC 0x2
2901 /*
2902  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2903  *
2904  */
2905 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
2906 /*
2907  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2908  *
2909  */
2910 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED1 0x4
2911 /*
2912  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2913  *
2914  */
2915 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED2 0x5
2916 /*
2917  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2918  *
2919  */
2920 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2921 /*
2922  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2923  *
2924  */
2925 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2926 /*
2927  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2928  *
2929  */
2930 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED3 0x8
2931 /*
2932  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2933  *
2934  */
2935 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED4 0x9
2936 /*
2937  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2938  *
2939  */
2940 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2941 /*
2942  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2943  *
2944  */
2945 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2946 /*
2947  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2948  *
2949  */
2950 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED5 0xc
2951 /*
2952  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2953  *
2954  */
2955 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_RESERVED6 0xd
2956 /*
2957  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2958  *
2959  */
2960 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2961 /*
2962  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWCACHE
2963  *
2964  */
2965 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
2966 
2967 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field. */
2968 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_LSB 20
2969 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field. */
2970 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_MSB 23
2971 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field. */
2972 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_WIDTH 4
2973 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field value. */
2974 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_SET_MSK 0x00f00000
2975 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field value. */
2976 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_CLR_MSK 0xff0fffff
2977 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_AWCACHE register field. */
2978 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_RESET 0x0
2979 /* Extracts the ALT_SYSMGR_CORE_EMAC0_AWCACHE field value from a register. */
2980 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
2981 /* Produces a ALT_SYSMGR_CORE_EMAC0_AWCACHE register field value suitable for setting the register. */
2982 #define ALT_SYSMGR_CORE_EMAC0_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
2983 
2984 /*
2985  * Field : arprot
2986  *
2987  * Specifies the values of the ARPROT signals.
2988  *
2989  * ==========================
2990  *
2991  * AxPROT[1]
2992  *
2993  * LOW: Secure Access
2994  *
2995  * HIGH: NonSecure Access
2996  *
2997  * ==========================
2998  *
2999  * AxPROT[0]
3000  *
3001  * LOW: Normal Access
3002  *
3003  * HIGH: Privileged Access
3004  *
3005  * ==========================
3006  *
3007  * Field Enumeration Values:
3008  *
3009  * Enum | Value | Description
3010  * :----------------------------------------------------|:------|:------------
3011  * ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_NORMAL | 0x0 |
3012  * ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
3013  * ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_NORMAL | 0x2 |
3014  * ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3015  *
3016  * Field Access Macros:
3017  *
3018  */
3019 /*
3020  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARPROT
3021  *
3022  * Secure Normal(non-privileged) access
3023  */
3024 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_NORMAL 0x0
3025 /*
3026  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARPROT
3027  *
3028  * Secure Privileged access
3029  */
3030 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_SECURE_PRIVILEGED 0x1
3031 /*
3032  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARPROT
3033  *
3034  * Non-Secure Normal(non-privileged) access
3035  */
3036 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_NORMAL 0x2
3037 /*
3038  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_ARPROT
3039  *
3040  * Non-Secure Privileged access
3041  */
3042 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3043 
3044 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ARPROT register field. */
3045 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_LSB 24
3046 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ARPROT register field. */
3047 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_MSB 26
3048 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ARPROT register field. */
3049 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_WIDTH 3
3050 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ARPROT register field value. */
3051 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_SET_MSK 0x07000000
3052 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ARPROT register field value. */
3053 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_CLR_MSK 0xf8ffffff
3054 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ARPROT register field. */
3055 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_RESET 0x2
3056 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ARPROT field value from a register. */
3057 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
3058 /* Produces a ALT_SYSMGR_CORE_EMAC0_ARPROT register field value suitable for setting the register. */
3059 #define ALT_SYSMGR_CORE_EMAC0_ARPROT_SET(value) (((value) << 24) & 0x07000000)
3060 
3061 /*
3062  * Field : awprot
3063  *
3064  * Specifies the values of the 2 EMAC AWCACHE signals.
3065  *
3066  * ==========================
3067  *
3068  * AxPROT[1]
3069  *
3070  * LOW: Secure Access
3071  *
3072  * HIGH: NonSecure Access
3073  *
3074  * ==========================
3075  *
3076  * AxPROT[0]
3077  *
3078  * LOW: Normal Access
3079  *
3080  * HIGH: Privileged Access
3081  *
3082  * ==========================
3083  *
3084  * Field Enumeration Values:
3085  *
3086  * Enum | Value | Description
3087  * :----------------------------------------------------|:------|:------------
3088  * ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_NORMAL | 0x0 |
3089  * ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
3090  * ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_NORMAL | 0x2 |
3091  * ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3092  *
3093  * Field Access Macros:
3094  *
3095  */
3096 /*
3097  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWPROT
3098  *
3099  * Secure Normal(non-privileged) access
3100  */
3101 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_NORMAL 0x0
3102 /*
3103  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWPROT
3104  *
3105  * Secure Privileged access
3106  */
3107 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_SECURE_PRIVILEGED 0x1
3108 /*
3109  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWPROT
3110  *
3111  * Non-Secure Normal(non-privileged) access
3112  */
3113 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_NORMAL 0x2
3114 /*
3115  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_AWPROT
3116  *
3117  * Non-Secure Privileged access
3118  */
3119 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3120 
3121 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_AWPROT register field. */
3122 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_LSB 27
3123 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_AWPROT register field. */
3124 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_MSB 29
3125 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_AWPROT register field. */
3126 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_WIDTH 3
3127 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_AWPROT register field value. */
3128 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_SET_MSK 0x38000000
3129 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_AWPROT register field value. */
3130 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_CLR_MSK 0xc7ffffff
3131 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_AWPROT register field. */
3132 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_RESET 0x2
3133 /* Extracts the ALT_SYSMGR_CORE_EMAC0_AWPROT field value from a register. */
3134 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
3135 /* Produces a ALT_SYSMGR_CORE_EMAC0_AWPROT register field value suitable for setting the register. */
3136 #define ALT_SYSMGR_CORE_EMAC0_AWPROT_SET(value) (((value) << 27) & 0x38000000)
3137 
3138 /*
3139  * Field : sbd_data_endianness
3140  *
3141  * Specifies the endianness of the EMAC DMA transfers.
3142  *
3143  * The field array index corresponds to the EMAC index.
3144  *
3145  * Field Enumeration Values:
3146  *
3147  * Enum | Value | Description
3148  * :----------------------------------------------------------|:------|:------------
3149  * ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
3150  * ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
3151  *
3152  * Field Access Macros:
3153  *
3154  */
3155 /*
3156  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS
3157  *
3158  */
3159 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3160 /*
3161  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS
3162  *
3163  */
3164 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3165 
3166 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field. */
3167 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_LSB 30
3168 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field. */
3169 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_MSB 30
3170 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field. */
3171 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_WIDTH 1
3172 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field value. */
3173 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3174 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field value. */
3175 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3176 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field. */
3177 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_RESET 0x0
3178 /* Extracts the ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS field value from a register. */
3179 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3180 /* Produces a ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
3181 #define ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3182 
3183 /*
3184  * Field : axi_disable
3185  *
3186  * AXI Disable
3187  *
3188  * Field Access Macros:
3189  *
3190  */
3191 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field. */
3192 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_LSB 31
3193 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field. */
3194 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_MSB 31
3195 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field. */
3196 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_WIDTH 1
3197 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field value. */
3198 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_SET_MSK 0x80000000
3199 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field value. */
3200 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_CLR_MSK 0x7fffffff
3201 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field. */
3202 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_RESET 0x0
3203 /* Extracts the ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE field value from a register. */
3204 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
3205 /* Produces a ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE register field value suitable for setting the register. */
3206 #define ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
3207 
3208 #ifndef __ASSEMBLY__
3209 /*
3210  * WARNING: The C register and register group struct declarations are provided for
3211  * convenience and illustrative purposes. They should, however, be used with
3212  * caution as the C language standard provides no guarantees about the alignment or
3213  * atomicity of device memory accesses. The recommended practice for coding device
3214  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3215  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3216  * alt_write_dword() functions for 64 bit registers.
3217  *
3218  * The struct declaration for register ALT_SYSMGR_CORE_EMAC0.
3219  */
3220 struct ALT_SYSMGR_CORE_EMAC0_s
3221 {
3222  volatile uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_CORE_EMAC0_PHY_INTF_SEL */
3223  uint32_t : 6; /* *UNDEFINED* */
3224  volatile uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_CORE_EMAC0_PTP_REF_SEL */
3225  uint32_t : 3; /* *UNDEFINED* */
3226  volatile uint32_t app_clk_sel : 1; /* ALT_SYSMGR_CORE_EMAC0_APP_CLK_SEL */
3227  uint32_t : 3; /* *UNDEFINED* */
3228  volatile uint32_t arcache : 4; /* ALT_SYSMGR_CORE_EMAC0_ARCACHE */
3229  volatile uint32_t awcache : 4; /* ALT_SYSMGR_CORE_EMAC0_AWCACHE */
3230  volatile uint32_t arprot : 3; /* ALT_SYSMGR_CORE_EMAC0_ARPROT */
3231  volatile uint32_t awprot : 3; /* ALT_SYSMGR_CORE_EMAC0_AWPROT */
3232  volatile uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_CORE_EMAC0_SBD_DATA_ENDIANNESS */
3233  volatile uint32_t axi_disable : 1; /* ALT_SYSMGR_CORE_EMAC0_AXI_DISABLE */
3234 };
3235 
3236 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC0. */
3237 typedef struct ALT_SYSMGR_CORE_EMAC0_s ALT_SYSMGR_CORE_EMAC0_t;
3238 #endif /* __ASSEMBLY__ */
3239 
3240 /* The reset value of the ALT_SYSMGR_CORE_EMAC0 register. */
3241 #define ALT_SYSMGR_CORE_EMAC0_RESET 0x12000003
3242 /* The byte offset of the ALT_SYSMGR_CORE_EMAC0 register from the beginning of the component. */
3243 #define ALT_SYSMGR_CORE_EMAC0_OFST 0x44
3244 
3245 /*
3246  * Register : Control Register - emac1
3247  *
3248  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
3249  *
3250  * Register Layout
3251  *
3252  * Bits | Access | Reset | Description
3253  * :--------|:-------|:------|:------------------------------------------
3254  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL
3255  * [7:2] | ??? | 0x0 | *UNDEFINED*
3256  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL
3257  * [11:9] | ??? | 0x0 | *UNDEFINED*
3258  * [12] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL
3259  * [15:13] | ??? | 0x0 | *UNDEFINED*
3260  * [19:16] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_ARCACHE
3261  * [23:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_AWCACHE
3262  * [26:24] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC1_ARPROT
3263  * [29:27] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC1_AWPROT
3264  * [30] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS
3265  * [31] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE
3266  *
3267  */
3268 /*
3269  * Field : phy_intf_sel
3270  *
3271  * PHY Interface Select
3272  *
3273  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
3274  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
3275  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
3276  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
3277  * clocks use the Clock Manager reference rather than depending on the PHY to have
3278  * active clocks.
3279  *
3280  * Field Enumeration Values:
3281  *
3282  * Enum | Value | Description
3283  * :----------------------------------------------|:------|:------------
3284  * ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_GMII_MII | 0x0 |
3285  * ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RGMII | 0x1 |
3286  * ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RMII | 0x2 |
3287  * ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RESET | 0x3 |
3288  *
3289  * Field Access Macros:
3290  *
3291  */
3292 /*
3293  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL
3294  *
3295  */
3296 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_GMII_MII 0x0
3297 /*
3298  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL
3299  *
3300  */
3301 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RGMII 0x1
3302 /*
3303  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL
3304  *
3305  */
3306 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RMII 0x2
3307 /*
3308  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL
3309  *
3310  */
3311 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_E_RESET 0x3
3312 
3313 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field. */
3314 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_LSB 0
3315 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field. */
3316 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_MSB 1
3317 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field. */
3318 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_WIDTH 2
3319 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field value. */
3320 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_SET_MSK 0x00000003
3321 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field value. */
3322 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3323 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field. */
3324 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_RESET 0x3
3325 /* Extracts the ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL field value from a register. */
3326 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3327 /* Produces a ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL register field value suitable for setting the register. */
3328 #define ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3329 
3330 /*
3331  * Field : ptp_ref_sel
3332  *
3333  * This field selects if the Timestamp reference is internally or externally
3334  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
3335  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
3336  * Internal or External.
3337  *
3338  * Field Enumeration Values:
3339  *
3340  * Enum | Value | Description
3341  * :---------------------------------------------|:------|:------------
3342  * ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_INTERNAL | 0x0 |
3343  * ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_EXTERNAL | 0x1 |
3344  *
3345  * Field Access Macros:
3346  *
3347  */
3348 /*
3349  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL
3350  *
3351  */
3352 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_INTERNAL 0x0
3353 /*
3354  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL
3355  *
3356  */
3357 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_E_EXTERNAL 0x1
3358 
3359 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field. */
3360 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_LSB 8
3361 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field. */
3362 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_MSB 8
3363 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field. */
3364 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_WIDTH 1
3365 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field value. */
3366 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_SET_MSK 0x00000100
3367 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field value. */
3368 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_CLR_MSK 0xfffffeff
3369 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field. */
3370 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_RESET 0x0
3371 /* Extracts the ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL field value from a register. */
3372 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3373 /* Produces a ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL register field value suitable for setting the register. */
3374 #define ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3375 
3376 /*
3377  * Field : app_clk_sel
3378  *
3379  * Selects the source of the Application clock for the datapath to either l4_mp_clk
3380  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
3381  * the FPGA fabric.
3382  *
3383  * Field Enumeration Values:
3384  *
3385  * Enum | Value | Description
3386  * :-----------------------------------------------|:------|:------------
3387  * ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
3388  * ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
3389  *
3390  * Field Access Macros:
3391  *
3392  */
3393 /*
3394  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL
3395  *
3396  */
3397 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_L4_MP_CLK 0x0
3398 /*
3399  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL
3400  *
3401  */
3402 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3403 
3404 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field. */
3405 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_LSB 12
3406 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field. */
3407 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_MSB 12
3408 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field. */
3409 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_WIDTH 1
3410 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field value. */
3411 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_SET_MSK 0x00001000
3412 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field value. */
3413 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_CLR_MSK 0xffffefff
3414 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field. */
3415 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_RESET 0x0
3416 /* Extracts the ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL field value from a register. */
3417 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3418 /* Produces a ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL register field value suitable for setting the register. */
3419 #define ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3420 
3421 /*
3422  * Field : arcache
3423  *
3424  * Specifies the values of the 2 EMAC ARCACHE signals.
3425  *
3426  * The field array index corresponds to the EMAC index.
3427  *
3428  * Field Enumeration Values:
3429  *
3430  * Enum | Value | Description
3431  * :-----------------------------------------------------|:------|:------------
3432  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_F2S_AP_CLK | 0x0 |
3433  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_BUFF | 0x1 |
3434  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_NONALLOC | 0x2 |
3435  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
3436  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED1 | 0x4 |
3437  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED2 | 0x5 |
3438  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
3439  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
3440  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED3 | 0x8 |
3441  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED4 | 0x9 |
3442  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
3443  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
3444  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED5 | 0xc |
3445  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED6 | 0xd |
3446  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
3447  * ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
3448  *
3449  * Field Access Macros:
3450  *
3451  */
3452 /*
3453  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3454  *
3455  */
3456 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_F2S_AP_CLK 0x0
3457 /*
3458  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3459  *
3460  */
3461 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_BUFF 0x1
3462 /*
3463  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3464  *
3465  */
3466 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_NONALLOC 0x2
3467 /*
3468  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3469  *
3470  */
3471 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3472 /*
3473  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3474  *
3475  */
3476 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED1 0x4
3477 /*
3478  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3479  *
3480  */
3481 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED2 0x5
3482 /*
3483  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3484  *
3485  */
3486 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3487 /*
3488  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3489  *
3490  */
3491 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3492 /*
3493  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3494  *
3495  */
3496 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED3 0x8
3497 /*
3498  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3499  *
3500  */
3501 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED4 0x9
3502 /*
3503  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3504  *
3505  */
3506 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3507 /*
3508  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3509  *
3510  */
3511 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3512 /*
3513  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3514  *
3515  */
3516 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED5 0xc
3517 /*
3518  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3519  *
3520  */
3521 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_RESERVED6 0xd
3522 /*
3523  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3524  *
3525  */
3526 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3527 /*
3528  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARCACHE
3529  *
3530  */
3531 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
3532 
3533 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field. */
3534 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_LSB 16
3535 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field. */
3536 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_MSB 19
3537 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field. */
3538 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_WIDTH 4
3539 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field value. */
3540 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_SET_MSK 0x000f0000
3541 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field value. */
3542 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_CLR_MSK 0xfff0ffff
3543 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ARCACHE register field. */
3544 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_RESET 0x0
3545 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ARCACHE field value from a register. */
3546 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
3547 /* Produces a ALT_SYSMGR_CORE_EMAC1_ARCACHE register field value suitable for setting the register. */
3548 #define ALT_SYSMGR_CORE_EMAC1_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
3549 
3550 /*
3551  * Field : awcache
3552  *
3553  * Specifies the values of the 2 EMAC AWCACHE signals.
3554  *
3555  * The field array index corresponds to the EMAC index.
3556  *
3557  * Field Enumeration Values:
3558  *
3559  * Enum | Value | Description
3560  * :-----------------------------------------------------|:------|:------------
3561  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
3562  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_BUFF | 0x1 |
3563  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_NONALLOC | 0x2 |
3564  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
3565  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED1 | 0x4 |
3566  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED2 | 0x5 |
3567  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
3568  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
3569  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED3 | 0x8 |
3570  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED4 | 0x9 |
3571  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
3572  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
3573  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED5 | 0xc |
3574  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED6 | 0xd |
3575  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
3576  * ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
3577  *
3578  * Field Access Macros:
3579  *
3580  */
3581 /*
3582  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3583  *
3584  */
3585 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_NONCACHE_NONBUFF 0x0
3586 /*
3587  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3588  *
3589  */
3590 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_BUFF 0x1
3591 /*
3592  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3593  *
3594  */
3595 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_NONALLOC 0x2
3596 /*
3597  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3598  *
3599  */
3600 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
3601 /*
3602  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3603  *
3604  */
3605 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED1 0x4
3606 /*
3607  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3608  *
3609  */
3610 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED2 0x5
3611 /*
3612  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3613  *
3614  */
3615 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3616 /*
3617  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3618  *
3619  */
3620 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3621 /*
3622  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3623  *
3624  */
3625 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED3 0x8
3626 /*
3627  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3628  *
3629  */
3630 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED4 0x9
3631 /*
3632  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3633  *
3634  */
3635 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3636 /*
3637  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3638  *
3639  */
3640 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3641 /*
3642  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3643  *
3644  */
3645 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED5 0xc
3646 /*
3647  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3648  *
3649  */
3650 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_RESERVED6 0xd
3651 /*
3652  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3653  *
3654  */
3655 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3656 /*
3657  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWCACHE
3658  *
3659  */
3660 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
3661 
3662 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field. */
3663 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_LSB 20
3664 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field. */
3665 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_MSB 23
3666 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field. */
3667 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_WIDTH 4
3668 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field value. */
3669 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_SET_MSK 0x00f00000
3670 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field value. */
3671 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_CLR_MSK 0xff0fffff
3672 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_AWCACHE register field. */
3673 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_RESET 0x0
3674 /* Extracts the ALT_SYSMGR_CORE_EMAC1_AWCACHE field value from a register. */
3675 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
3676 /* Produces a ALT_SYSMGR_CORE_EMAC1_AWCACHE register field value suitable for setting the register. */
3677 #define ALT_SYSMGR_CORE_EMAC1_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3678 
3679 /*
3680  * Field : arprot
3681  *
3682  * Specifies the values of the ARPROT signals.
3683  *
3684  * ==========================
3685  *
3686  * AxPROT[1]
3687  *
3688  * LOW: Secure Access
3689  *
3690  * HIGH: NonSecure Access
3691  *
3692  * ==========================
3693  *
3694  * AxPROT[0]
3695  *
3696  * LOW: Normal Access
3697  *
3698  * HIGH: Privileged Access
3699  *
3700  * ==========================
3701  *
3702  * Field Enumeration Values:
3703  *
3704  * Enum | Value | Description
3705  * :----------------------------------------------------|:------|:------------
3706  * ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_NORMAL | 0x0 |
3707  * ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
3708  * ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_NORMAL | 0x2 |
3709  * ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3710  *
3711  * Field Access Macros:
3712  *
3713  */
3714 /*
3715  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARPROT
3716  *
3717  * Secure Normal(non-privileged) access
3718  */
3719 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_NORMAL 0x0
3720 /*
3721  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARPROT
3722  *
3723  * Secure Privileged access
3724  */
3725 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_SECURE_PRIVILEGED 0x1
3726 /*
3727  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARPROT
3728  *
3729  * Non-Secure Normal(non-privileged) access
3730  */
3731 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_NORMAL 0x2
3732 /*
3733  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_ARPROT
3734  *
3735  * Non-Secure Privileged access
3736  */
3737 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3738 
3739 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ARPROT register field. */
3740 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_LSB 24
3741 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ARPROT register field. */
3742 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_MSB 26
3743 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ARPROT register field. */
3744 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_WIDTH 3
3745 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ARPROT register field value. */
3746 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_SET_MSK 0x07000000
3747 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ARPROT register field value. */
3748 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_CLR_MSK 0xf8ffffff
3749 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ARPROT register field. */
3750 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_RESET 0x2
3751 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ARPROT field value from a register. */
3752 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
3753 /* Produces a ALT_SYSMGR_CORE_EMAC1_ARPROT register field value suitable for setting the register. */
3754 #define ALT_SYSMGR_CORE_EMAC1_ARPROT_SET(value) (((value) << 24) & 0x07000000)
3755 
3756 /*
3757  * Field : awprot
3758  *
3759  * Specifies the values of the 2 EMAC AWCACHE signals.
3760  *
3761  * ==========================
3762  *
3763  * AxPROT[1]
3764  *
3765  * LOW: Secure Access
3766  *
3767  * HIGH: NonSecure Access
3768  *
3769  * ==========================
3770  *
3771  * AxPROT[0]
3772  *
3773  * LOW: Normal Access
3774  *
3775  * HIGH: Privileged Access
3776  *
3777  * ==========================
3778  *
3779  * Field Enumeration Values:
3780  *
3781  * Enum | Value | Description
3782  * :----------------------------------------------------|:------|:------------
3783  * ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_NORMAL | 0x0 |
3784  * ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
3785  * ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_NORMAL | 0x2 |
3786  * ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3787  *
3788  * Field Access Macros:
3789  *
3790  */
3791 /*
3792  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWPROT
3793  *
3794  * Secure Normal(non-privileged) access
3795  */
3796 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_NORMAL 0x0
3797 /*
3798  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWPROT
3799  *
3800  * Secure Privileged access
3801  */
3802 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_SECURE_PRIVILEGED 0x1
3803 /*
3804  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWPROT
3805  *
3806  * Non-Secure Normal(non-privileged) access
3807  */
3808 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_NORMAL 0x2
3809 /*
3810  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_AWPROT
3811  *
3812  * Non-Secure Privileged access
3813  */
3814 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3815 
3816 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_AWPROT register field. */
3817 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_LSB 27
3818 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_AWPROT register field. */
3819 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_MSB 29
3820 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_AWPROT register field. */
3821 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_WIDTH 3
3822 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_AWPROT register field value. */
3823 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_SET_MSK 0x38000000
3824 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_AWPROT register field value. */
3825 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_CLR_MSK 0xc7ffffff
3826 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_AWPROT register field. */
3827 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_RESET 0x2
3828 /* Extracts the ALT_SYSMGR_CORE_EMAC1_AWPROT field value from a register. */
3829 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
3830 /* Produces a ALT_SYSMGR_CORE_EMAC1_AWPROT register field value suitable for setting the register. */
3831 #define ALT_SYSMGR_CORE_EMAC1_AWPROT_SET(value) (((value) << 27) & 0x38000000)
3832 
3833 /*
3834  * Field : sbd_data_endianness
3835  *
3836  * Specifies the endianness of the EMAC DMA transfers.
3837  *
3838  * The field array index corresponds to the EMAC index.
3839  *
3840  * Field Enumeration Values:
3841  *
3842  * Enum | Value | Description
3843  * :----------------------------------------------------------|:------|:------------
3844  * ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
3845  * ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
3846  *
3847  * Field Access Macros:
3848  *
3849  */
3850 /*
3851  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS
3852  *
3853  */
3854 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3855 /*
3856  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS
3857  *
3858  */
3859 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3860 
3861 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field. */
3862 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_LSB 30
3863 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field. */
3864 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_MSB 30
3865 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field. */
3866 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_WIDTH 1
3867 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field value. */
3868 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3869 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field value. */
3870 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3871 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field. */
3872 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_RESET 0x0
3873 /* Extracts the ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS field value from a register. */
3874 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3875 /* Produces a ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
3876 #define ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3877 
3878 /*
3879  * Field : axi_disable
3880  *
3881  * AXI Disable
3882  *
3883  * Field Access Macros:
3884  *
3885  */
3886 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field. */
3887 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_LSB 31
3888 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field. */
3889 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_MSB 31
3890 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field. */
3891 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_WIDTH 1
3892 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field value. */
3893 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_SET_MSK 0x80000000
3894 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field value. */
3895 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_CLR_MSK 0x7fffffff
3896 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field. */
3897 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_RESET 0x0
3898 /* Extracts the ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE field value from a register. */
3899 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
3900 /* Produces a ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE register field value suitable for setting the register. */
3901 #define ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
3902 
3903 #ifndef __ASSEMBLY__
3904 /*
3905  * WARNING: The C register and register group struct declarations are provided for
3906  * convenience and illustrative purposes. They should, however, be used with
3907  * caution as the C language standard provides no guarantees about the alignment or
3908  * atomicity of device memory accesses. The recommended practice for coding device
3909  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3910  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3911  * alt_write_dword() functions for 64 bit registers.
3912  *
3913  * The struct declaration for register ALT_SYSMGR_CORE_EMAC1.
3914  */
3915 struct ALT_SYSMGR_CORE_EMAC1_s
3916 {
3917  volatile uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_CORE_EMAC1_PHY_INTF_SEL */
3918  uint32_t : 6; /* *UNDEFINED* */
3919  volatile uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_CORE_EMAC1_PTP_REF_SEL */
3920  uint32_t : 3; /* *UNDEFINED* */
3921  volatile uint32_t app_clk_sel : 1; /* ALT_SYSMGR_CORE_EMAC1_APP_CLK_SEL */
3922  uint32_t : 3; /* *UNDEFINED* */
3923  volatile uint32_t arcache : 4; /* ALT_SYSMGR_CORE_EMAC1_ARCACHE */
3924  volatile uint32_t awcache : 4; /* ALT_SYSMGR_CORE_EMAC1_AWCACHE */
3925  volatile uint32_t arprot : 3; /* ALT_SYSMGR_CORE_EMAC1_ARPROT */
3926  volatile uint32_t awprot : 3; /* ALT_SYSMGR_CORE_EMAC1_AWPROT */
3927  volatile uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_CORE_EMAC1_SBD_DATA_ENDIANNESS */
3928  volatile uint32_t axi_disable : 1; /* ALT_SYSMGR_CORE_EMAC1_AXI_DISABLE */
3929 };
3930 
3931 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC1. */
3932 typedef struct ALT_SYSMGR_CORE_EMAC1_s ALT_SYSMGR_CORE_EMAC1_t;
3933 #endif /* __ASSEMBLY__ */
3934 
3935 /* The reset value of the ALT_SYSMGR_CORE_EMAC1 register. */
3936 #define ALT_SYSMGR_CORE_EMAC1_RESET 0x12000003
3937 /* The byte offset of the ALT_SYSMGR_CORE_EMAC1 register from the beginning of the component. */
3938 #define ALT_SYSMGR_CORE_EMAC1_OFST 0x48
3939 
3940 /*
3941  * Register : Control Register - emac2
3942  *
3943  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
3944  *
3945  * Register Layout
3946  *
3947  * Bits | Access | Reset | Description
3948  * :--------|:-------|:------|:------------------------------------------
3949  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL
3950  * [7:2] | ??? | 0x0 | *UNDEFINED*
3951  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL
3952  * [11:9] | ??? | 0x0 | *UNDEFINED*
3953  * [12] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL
3954  * [15:13] | ??? | 0x0 | *UNDEFINED*
3955  * [19:16] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_ARCACHE
3956  * [23:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_AWCACHE
3957  * [26:24] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC2_ARPROT
3958  * [29:27] | RW | 0x2 | ALT_SYSMGR_CORE_EMAC2_AWPROT
3959  * [30] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS
3960  * [31] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE
3961  *
3962  */
3963 /*
3964  * Field : phy_intf_sel
3965  *
3966  * PHY Interface Select
3967  *
3968  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
3969  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
3970  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
3971  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
3972  * clocks use the Clock Manager reference rather than depending on the PHY to have
3973  * active clocks.
3974  *
3975  * Field Enumeration Values:
3976  *
3977  * Enum | Value | Description
3978  * :----------------------------------------------|:------|:------------
3979  * ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_GMII_MII | 0x0 |
3980  * ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RGMII | 0x1 |
3981  * ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RMII | 0x2 |
3982  * ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RESET | 0x3 |
3983  *
3984  * Field Access Macros:
3985  *
3986  */
3987 /*
3988  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL
3989  *
3990  */
3991 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_GMII_MII 0x0
3992 /*
3993  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL
3994  *
3995  */
3996 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RGMII 0x1
3997 /*
3998  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL
3999  *
4000  */
4001 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RMII 0x2
4002 /*
4003  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL
4004  *
4005  */
4006 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_E_RESET 0x3
4007 
4008 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field. */
4009 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_LSB 0
4010 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field. */
4011 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_MSB 1
4012 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field. */
4013 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_WIDTH 2
4014 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field value. */
4015 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_SET_MSK 0x00000003
4016 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field value. */
4017 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_CLR_MSK 0xfffffffc
4018 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field. */
4019 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_RESET 0x3
4020 /* Extracts the ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL field value from a register. */
4021 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
4022 /* Produces a ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL register field value suitable for setting the register. */
4023 #define ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
4024 
4025 /*
4026  * Field : ptp_ref_sel
4027  *
4028  * This field selects if the Timestamp reference is internally or externally
4029  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
4030  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
4031  * Internal or External.
4032  *
4033  * Field Enumeration Values:
4034  *
4035  * Enum | Value | Description
4036  * :---------------------------------------------|:------|:------------
4037  * ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_INTERNAL | 0x0 |
4038  * ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_EXTERNAL | 0x1 |
4039  *
4040  * Field Access Macros:
4041  *
4042  */
4043 /*
4044  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL
4045  *
4046  */
4047 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_INTERNAL 0x0
4048 /*
4049  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL
4050  *
4051  */
4052 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_E_EXTERNAL 0x1
4053 
4054 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field. */
4055 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_LSB 8
4056 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field. */
4057 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_MSB 8
4058 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field. */
4059 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_WIDTH 1
4060 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field value. */
4061 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_SET_MSK 0x00000100
4062 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field value. */
4063 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_CLR_MSK 0xfffffeff
4064 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field. */
4065 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_RESET 0x0
4066 /* Extracts the ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL field value from a register. */
4067 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
4068 /* Produces a ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL register field value suitable for setting the register. */
4069 #define ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
4070 
4071 /*
4072  * Field : app_clk_sel
4073  *
4074  * Selects the source of the Application clock for the datapath to either l4_mp_clk
4075  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
4076  * the FPGA fabric.
4077  *
4078  * Field Enumeration Values:
4079  *
4080  * Enum | Value | Description
4081  * :-----------------------------------------------|:------|:------------
4082  * ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
4083  * ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
4084  *
4085  * Field Access Macros:
4086  *
4087  */
4088 /*
4089  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL
4090  *
4091  */
4092 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_L4_MP_CLK 0x0
4093 /*
4094  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL
4095  *
4096  */
4097 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK 0x1
4098 
4099 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field. */
4100 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_LSB 12
4101 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field. */
4102 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_MSB 12
4103 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field. */
4104 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_WIDTH 1
4105 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field value. */
4106 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_SET_MSK 0x00001000
4107 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field value. */
4108 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_CLR_MSK 0xffffefff
4109 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field. */
4110 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_RESET 0x0
4111 /* Extracts the ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL field value from a register. */
4112 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
4113 /* Produces a ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL register field value suitable for setting the register. */
4114 #define ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
4115 
4116 /*
4117  * Field : arcache
4118  *
4119  * Specifies the values of the 2 EMAC ARCACHE signals.
4120  *
4121  * The field array index corresponds to the EMAC index.
4122  *
4123  * Field Enumeration Values:
4124  *
4125  * Enum | Value | Description
4126  * :-----------------------------------------------------|:------|:------------
4127  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_NONCACHE_NONBUFF | 0x0 |
4128  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_BUFF | 0x1 |
4129  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_NONALLOC | 0x2 |
4130  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
4131  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED1 | 0x4 |
4132  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED2 | 0x5 |
4133  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
4134  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
4135  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED3 | 0x8 |
4136  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED4 | 0x9 |
4137  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
4138  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
4139  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED5 | 0xc |
4140  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED6 | 0xd |
4141  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
4142  * ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
4143  *
4144  * Field Access Macros:
4145  *
4146  */
4147 /*
4148  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4149  *
4150  */
4151 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_NONCACHE_NONBUFF 0x0
4152 /*
4153  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4154  *
4155  */
4156 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_BUFF 0x1
4157 /*
4158  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4159  *
4160  */
4161 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_NONALLOC 0x2
4162 /*
4163  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4164  *
4165  */
4166 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
4167 /*
4168  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4169  *
4170  */
4171 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED1 0x4
4172 /*
4173  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4174  *
4175  */
4176 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED2 0x5
4177 /*
4178  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4179  *
4180  */
4181 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4182 /*
4183  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4184  *
4185  */
4186 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4187 /*
4188  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4189  *
4190  */
4191 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED3 0x8
4192 /*
4193  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4194  *
4195  */
4196 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED4 0x9
4197 /*
4198  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4199  *
4200  */
4201 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4202 /*
4203  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4204  *
4205  */
4206 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4207 /*
4208  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4209  *
4210  */
4211 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED5 0xc
4212 /*
4213  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4214  *
4215  */
4216 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_RESERVED6 0xd
4217 /*
4218  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4219  *
4220  */
4221 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4222 /*
4223  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARCACHE
4224  *
4225  */
4226 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
4227 
4228 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field. */
4229 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_LSB 16
4230 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field. */
4231 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_MSB 19
4232 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field. */
4233 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_WIDTH 4
4234 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field value. */
4235 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_SET_MSK 0x000f0000
4236 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field value. */
4237 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_CLR_MSK 0xfff0ffff
4238 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ARCACHE register field. */
4239 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_RESET 0x0
4240 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ARCACHE field value from a register. */
4241 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
4242 /* Produces a ALT_SYSMGR_CORE_EMAC2_ARCACHE register field value suitable for setting the register. */
4243 #define ALT_SYSMGR_CORE_EMAC2_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
4244 
4245 /*
4246  * Field : awcache
4247  *
4248  * Specifies the values of the 2 EMAC AWCACHE signals.
4249  *
4250  * The field array index corresponds to the EMAC index.
4251  *
4252  * Field Enumeration Values:
4253  *
4254  * Enum | Value | Description
4255  * :-----------------------------------------------------|:------|:------------
4256  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
4257  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_BUFF | 0x1 |
4258  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_NONALLOC | 0x2 |
4259  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
4260  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED1 | 0x4 |
4261  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED2 | 0x5 |
4262  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
4263  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
4264  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED3 | 0x8 |
4265  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED4 | 0x9 |
4266  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
4267  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
4268  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED5 | 0xc |
4269  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED6 | 0xd |
4270  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
4271  * ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
4272  *
4273  * Field Access Macros:
4274  *
4275  */
4276 /*
4277  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4278  *
4279  */
4280 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_NONCACHE_NONBUFF 0x0
4281 /*
4282  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4283  *
4284  */
4285 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_BUFF 0x1
4286 /*
4287  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4288  *
4289  */
4290 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_NONALLOC 0x2
4291 /*
4292  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4293  *
4294  */
4295 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
4296 /*
4297  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4298  *
4299  */
4300 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED1 0x4
4301 /*
4302  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4303  *
4304  */
4305 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED2 0x5
4306 /*
4307  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4308  *
4309  */
4310 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4311 /*
4312  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4313  *
4314  */
4315 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4316 /*
4317  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4318  *
4319  */
4320 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED3 0x8
4321 /*
4322  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4323  *
4324  */
4325 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED4 0x9
4326 /*
4327  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4328  *
4329  */
4330 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4331 /*
4332  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4333  *
4334  */
4335 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4336 /*
4337  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4338  *
4339  */
4340 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED5 0xc
4341 /*
4342  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4343  *
4344  */
4345 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_RESERVED6 0xd
4346 /*
4347  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4348  *
4349  */
4350 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4351 /*
4352  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWCACHE
4353  *
4354  */
4355 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
4356 
4357 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field. */
4358 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_LSB 20
4359 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field. */
4360 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_MSB 23
4361 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field. */
4362 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_WIDTH 4
4363 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field value. */
4364 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_SET_MSK 0x00f00000
4365 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field value. */
4366 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_CLR_MSK 0xff0fffff
4367 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_AWCACHE register field. */
4368 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_RESET 0x0
4369 /* Extracts the ALT_SYSMGR_CORE_EMAC2_AWCACHE field value from a register. */
4370 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
4371 /* Produces a ALT_SYSMGR_CORE_EMAC2_AWCACHE register field value suitable for setting the register. */
4372 #define ALT_SYSMGR_CORE_EMAC2_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
4373 
4374 /*
4375  * Field : arprot
4376  *
4377  * Specifies the values of the ARPROT signals.
4378  *
4379  * ==========================
4380  *
4381  * AxPROT[1]
4382  *
4383  * LOW: Secure Access
4384  *
4385  * HIGH: NonSecure Access
4386  *
4387  * ==========================
4388  *
4389  * AxPROT[0]
4390  *
4391  * LOW: Normal Access
4392  *
4393  * HIGH: Privileged Access
4394  *
4395  * ==========================
4396  *
4397  * Field Enumeration Values:
4398  *
4399  * Enum | Value | Description
4400  * :----------------------------------------------------|:------|:------------
4401  * ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_NORMAL | 0x0 |
4402  * ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
4403  * ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_NORMAL | 0x2 |
4404  * ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
4405  *
4406  * Field Access Macros:
4407  *
4408  */
4409 /*
4410  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARPROT
4411  *
4412  * Secure Normal(non-privileged) access
4413  */
4414 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_NORMAL 0x0
4415 /*
4416  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARPROT
4417  *
4418  * Secure Privileged access
4419  */
4420 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_SECURE_PRIVILEGED 0x1
4421 /*
4422  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARPROT
4423  *
4424  * Non-Secure Normal(non-privileged) access
4425  */
4426 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_NORMAL 0x2
4427 /*
4428  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_ARPROT
4429  *
4430  * Non-Secure Privileged access
4431  */
4432 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED 0x3
4433 
4434 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ARPROT register field. */
4435 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_LSB 24
4436 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ARPROT register field. */
4437 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_MSB 26
4438 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ARPROT register field. */
4439 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_WIDTH 3
4440 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ARPROT register field value. */
4441 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_SET_MSK 0x07000000
4442 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ARPROT register field value. */
4443 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_CLR_MSK 0xf8ffffff
4444 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ARPROT register field. */
4445 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_RESET 0x2
4446 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ARPROT field value from a register. */
4447 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_GET(value) (((value) & 0x07000000) >> 24)
4448 /* Produces a ALT_SYSMGR_CORE_EMAC2_ARPROT register field value suitable for setting the register. */
4449 #define ALT_SYSMGR_CORE_EMAC2_ARPROT_SET(value) (((value) << 24) & 0x07000000)
4450 
4451 /*
4452  * Field : awprot
4453  *
4454  * Specifies the values of the 2 EMAC AWCACHE signals.
4455  *
4456  * ==========================
4457  *
4458  * AxPROT[1]
4459  *
4460  * LOW: Secure Access
4461  *
4462  * HIGH: NonSecure Access
4463  *
4464  * ==========================
4465  *
4466  * AxPROT[0]
4467  *
4468  * LOW: Normal Access
4469  *
4470  * HIGH: Privileged Access
4471  *
4472  * ==========================
4473  *
4474  * Field Enumeration Values:
4475  *
4476  * Enum | Value | Description
4477  * :----------------------------------------------------|:------|:------------
4478  * ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_NORMAL | 0x0 |
4479  * ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
4480  * ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_NORMAL | 0x2 |
4481  * ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
4482  *
4483  * Field Access Macros:
4484  *
4485  */
4486 /*
4487  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWPROT
4488  *
4489  * Secure Normal(non-privileged) access
4490  */
4491 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_NORMAL 0x0
4492 /*
4493  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWPROT
4494  *
4495  * Secure Privileged access
4496  */
4497 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_SECURE_PRIVILEGED 0x1
4498 /*
4499  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWPROT
4500  *
4501  * Non-Secure Normal(non-privileged) access
4502  */
4503 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_NORMAL 0x2
4504 /*
4505  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_AWPROT
4506  *
4507  * Non-Secure Privileged access
4508  */
4509 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED 0x3
4510 
4511 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_AWPROT register field. */
4512 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_LSB 27
4513 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_AWPROT register field. */
4514 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_MSB 29
4515 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_AWPROT register field. */
4516 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_WIDTH 3
4517 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_AWPROT register field value. */
4518 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_SET_MSK 0x38000000
4519 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_AWPROT register field value. */
4520 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_CLR_MSK 0xc7ffffff
4521 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_AWPROT register field. */
4522 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_RESET 0x2
4523 /* Extracts the ALT_SYSMGR_CORE_EMAC2_AWPROT field value from a register. */
4524 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_GET(value) (((value) & 0x38000000) >> 27)
4525 /* Produces a ALT_SYSMGR_CORE_EMAC2_AWPROT register field value suitable for setting the register. */
4526 #define ALT_SYSMGR_CORE_EMAC2_AWPROT_SET(value) (((value) << 27) & 0x38000000)
4527 
4528 /*
4529  * Field : sbd_data_endianness
4530  *
4531  * Specifies the endianness of the EMAC DMA transfers.
4532  *
4533  * The field array index corresponds to the EMAC index.
4534  *
4535  * Field Enumeration Values:
4536  *
4537  * Enum | Value | Description
4538  * :----------------------------------------------------------|:------|:------------
4539  * ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
4540  * ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
4541  *
4542  * Field Access Macros:
4543  *
4544  */
4545 /*
4546  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS
4547  *
4548  */
4549 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
4550 /*
4551  * Enumerated value for register field ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS
4552  *
4553  */
4554 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
4555 
4556 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field. */
4557 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_LSB 30
4558 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field. */
4559 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_MSB 30
4560 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field. */
4561 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_WIDTH 1
4562 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field value. */
4563 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
4564 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field value. */
4565 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
4566 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field. */
4567 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_RESET 0x0
4568 /* Extracts the ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS field value from a register. */
4569 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
4570 /* Produces a ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
4571 #define ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
4572 
4573 /*
4574  * Field : axi_disable
4575  *
4576  * AXI Disable
4577  *
4578  * Field Access Macros:
4579  *
4580  */
4581 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field. */
4582 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_LSB 31
4583 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field. */
4584 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_MSB 31
4585 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field. */
4586 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_WIDTH 1
4587 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field value. */
4588 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_SET_MSK 0x80000000
4589 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field value. */
4590 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_CLR_MSK 0x7fffffff
4591 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field. */
4592 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_RESET 0x0
4593 /* Extracts the ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE field value from a register. */
4594 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_GET(value) (((value) & 0x80000000) >> 31)
4595 /* Produces a ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE register field value suitable for setting the register. */
4596 #define ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE_SET(value) (((value) << 31) & 0x80000000)
4597 
4598 #ifndef __ASSEMBLY__
4599 /*
4600  * WARNING: The C register and register group struct declarations are provided for
4601  * convenience and illustrative purposes. They should, however, be used with
4602  * caution as the C language standard provides no guarantees about the alignment or
4603  * atomicity of device memory accesses. The recommended practice for coding device
4604  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4605  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4606  * alt_write_dword() functions for 64 bit registers.
4607  *
4608  * The struct declaration for register ALT_SYSMGR_CORE_EMAC2.
4609  */
4610 struct ALT_SYSMGR_CORE_EMAC2_s
4611 {
4612  volatile uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_CORE_EMAC2_PHY_INTF_SEL */
4613  uint32_t : 6; /* *UNDEFINED* */
4614  volatile uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_CORE_EMAC2_PTP_REF_SEL */
4615  uint32_t : 3; /* *UNDEFINED* */
4616  volatile uint32_t app_clk_sel : 1; /* ALT_SYSMGR_CORE_EMAC2_APP_CLK_SEL */
4617  uint32_t : 3; /* *UNDEFINED* */
4618  volatile uint32_t arcache : 4; /* ALT_SYSMGR_CORE_EMAC2_ARCACHE */
4619  volatile uint32_t awcache : 4; /* ALT_SYSMGR_CORE_EMAC2_AWCACHE */
4620  volatile uint32_t arprot : 3; /* ALT_SYSMGR_CORE_EMAC2_ARPROT */
4621  volatile uint32_t awprot : 3; /* ALT_SYSMGR_CORE_EMAC2_AWPROT */
4622  volatile uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_CORE_EMAC2_SBD_DATA_ENDIANNESS */
4623  volatile uint32_t axi_disable : 1; /* ALT_SYSMGR_CORE_EMAC2_AXI_DISABLE */
4624 };
4625 
4626 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC2. */
4627 typedef struct ALT_SYSMGR_CORE_EMAC2_s ALT_SYSMGR_CORE_EMAC2_t;
4628 #endif /* __ASSEMBLY__ */
4629 
4630 /* The reset value of the ALT_SYSMGR_CORE_EMAC2 register. */
4631 #define ALT_SYSMGR_CORE_EMAC2_RESET 0x12000003
4632 /* The byte offset of the ALT_SYSMGR_CORE_EMAC2 register from the beginning of the component. */
4633 #define ALT_SYSMGR_CORE_EMAC2_OFST 0x4c
4634 
4635 /*
4636  * Register : emac0_ace
4637  *
4638  * The EMAC0 ACE-lite control register
4639  *
4640  * Register Layout
4641  *
4642  * Bits | Access | Reset | Description
4643  * :--------|:-------|:------|:-----------------------------------
4644  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN
4645  * [3:2] | ??? | 0x0 | *UNDEFINED*
4646  * [5:4] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN
4647  * [7:6] | ??? | 0x0 | *UNDEFINED*
4648  * [17:8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_ACE_ARSID
4649  * [19:18] | ??? | 0x0 | *UNDEFINED*
4650  * [29:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC0_ACE_AWSID
4651  * [31:30] | ??? | 0x0 | *UNDEFINED*
4652  *
4653  */
4654 /*
4655  * Field : ardomain
4656  *
4657  * ar domain
4658  *
4659  * Field Access Macros:
4660  *
4661  */
4662 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field. */
4663 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_LSB 0
4664 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field. */
4665 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_MSB 1
4666 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field. */
4667 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_WIDTH 2
4668 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field value. */
4669 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_SET_MSK 0x00000003
4670 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field value. */
4671 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4672 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field. */
4673 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_RESET 0x3
4674 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN field value from a register. */
4675 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4676 /* Produces a ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN register field value suitable for setting the register. */
4677 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4678 
4679 /*
4680  * Field : awdomain
4681  *
4682  * aw domain
4683  *
4684  * Field Access Macros:
4685  *
4686  */
4687 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field. */
4688 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_LSB 4
4689 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field. */
4690 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_MSB 5
4691 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field. */
4692 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_WIDTH 2
4693 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field value. */
4694 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_SET_MSK 0x00000030
4695 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field value. */
4696 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
4697 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field. */
4698 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_RESET 0x3
4699 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN field value from a register. */
4700 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
4701 /* Produces a ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN register field value suitable for setting the register. */
4702 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
4703 
4704 /*
4705  * Field : arsid
4706  *
4707  * arsid
4708  *
4709  * Field Access Macros:
4710  *
4711  */
4712 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field. */
4713 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_LSB 8
4714 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field. */
4715 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_MSB 17
4716 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field. */
4717 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_WIDTH 10
4718 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field value. */
4719 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_SET_MSK 0x0003ff00
4720 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field value. */
4721 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_CLR_MSK 0xfffc00ff
4722 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field. */
4723 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_RESET 0x0
4724 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ACE_ARSID field value from a register. */
4725 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
4726 /* Produces a ALT_SYSMGR_CORE_EMAC0_ACE_ARSID register field value suitable for setting the register. */
4727 #define ALT_SYSMGR_CORE_EMAC0_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
4728 
4729 /*
4730  * Field : awsid
4731  *
4732  * awsid
4733  *
4734  * Field Access Macros:
4735  *
4736  */
4737 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field. */
4738 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_LSB 20
4739 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field. */
4740 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_MSB 29
4741 /* The width in bits of the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field. */
4742 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_WIDTH 10
4743 /* The mask used to set the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field value. */
4744 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_SET_MSK 0x3ff00000
4745 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field value. */
4746 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_CLR_MSK 0xc00fffff
4747 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field. */
4748 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_RESET 0x0
4749 /* Extracts the ALT_SYSMGR_CORE_EMAC0_ACE_AWSID field value from a register. */
4750 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
4751 /* Produces a ALT_SYSMGR_CORE_EMAC0_ACE_AWSID register field value suitable for setting the register. */
4752 #define ALT_SYSMGR_CORE_EMAC0_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
4753 
4754 #ifndef __ASSEMBLY__
4755 /*
4756  * WARNING: The C register and register group struct declarations are provided for
4757  * convenience and illustrative purposes. They should, however, be used with
4758  * caution as the C language standard provides no guarantees about the alignment or
4759  * atomicity of device memory accesses. The recommended practice for coding device
4760  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4761  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4762  * alt_write_dword() functions for 64 bit registers.
4763  *
4764  * The struct declaration for register ALT_SYSMGR_CORE_EMAC0_ACE.
4765  */
4766 struct ALT_SYSMGR_CORE_EMAC0_ACE_s
4767 {
4768  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_EMAC0_ACE_ARDOMAIN */
4769  uint32_t : 2; /* *UNDEFINED* */
4770  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_EMAC0_ACE_AWDOMAIN */
4771  uint32_t : 2; /* *UNDEFINED* */
4772  volatile uint32_t arsid : 10; /* ALT_SYSMGR_CORE_EMAC0_ACE_ARSID */
4773  uint32_t : 2; /* *UNDEFINED* */
4774  volatile uint32_t awsid : 10; /* ALT_SYSMGR_CORE_EMAC0_ACE_AWSID */
4775  uint32_t : 2; /* *UNDEFINED* */
4776 };
4777 
4778 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC0_ACE. */
4779 typedef struct ALT_SYSMGR_CORE_EMAC0_ACE_s ALT_SYSMGR_CORE_EMAC0_ACE_t;
4780 #endif /* __ASSEMBLY__ */
4781 
4782 /* The reset value of the ALT_SYSMGR_CORE_EMAC0_ACE register. */
4783 #define ALT_SYSMGR_CORE_EMAC0_ACE_RESET 0x00000033
4784 /* The byte offset of the ALT_SYSMGR_CORE_EMAC0_ACE register from the beginning of the component. */
4785 #define ALT_SYSMGR_CORE_EMAC0_ACE_OFST 0x50
4786 
4787 /*
4788  * Register : emac1_ace
4789  *
4790  * The EMAC1 ACE-lite control register
4791  *
4792  * Register Layout
4793  *
4794  * Bits | Access | Reset | Description
4795  * :--------|:-------|:------|:-----------------------------------
4796  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN
4797  * [3:2] | ??? | 0x0 | *UNDEFINED*
4798  * [5:4] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN
4799  * [7:6] | ??? | 0x0 | *UNDEFINED*
4800  * [17:8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_ACE_ARSID
4801  * [19:18] | ??? | 0x0 | *UNDEFINED*
4802  * [29:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC1_ACE_AWSID
4803  * [31:30] | ??? | 0x0 | *UNDEFINED*
4804  *
4805  */
4806 /*
4807  * Field : ardomain
4808  *
4809  * ar domain register
4810  *
4811  * Field Access Macros:
4812  *
4813  */
4814 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field. */
4815 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_LSB 0
4816 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field. */
4817 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_MSB 1
4818 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field. */
4819 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_WIDTH 2
4820 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field value. */
4821 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_SET_MSK 0x00000003
4822 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field value. */
4823 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4824 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field. */
4825 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_RESET 0x3
4826 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN field value from a register. */
4827 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4828 /* Produces a ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN register field value suitable for setting the register. */
4829 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4830 
4831 /*
4832  * Field : awdomain
4833  *
4834  * aw domain register
4835  *
4836  * Field Access Macros:
4837  *
4838  */
4839 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field. */
4840 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_LSB 4
4841 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field. */
4842 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_MSB 5
4843 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field. */
4844 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_WIDTH 2
4845 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field value. */
4846 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_SET_MSK 0x00000030
4847 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field value. */
4848 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
4849 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field. */
4850 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_RESET 0x3
4851 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN field value from a register. */
4852 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
4853 /* Produces a ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN register field value suitable for setting the register. */
4854 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
4855 
4856 /*
4857  * Field : arsid
4858  *
4859  * arsid register
4860  *
4861  * Field Access Macros:
4862  *
4863  */
4864 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field. */
4865 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_LSB 8
4866 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field. */
4867 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_MSB 17
4868 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field. */
4869 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_WIDTH 10
4870 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field value. */
4871 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_SET_MSK 0x0003ff00
4872 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field value. */
4873 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_CLR_MSK 0xfffc00ff
4874 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field. */
4875 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_RESET 0x0
4876 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ACE_ARSID field value from a register. */
4877 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
4878 /* Produces a ALT_SYSMGR_CORE_EMAC1_ACE_ARSID register field value suitable for setting the register. */
4879 #define ALT_SYSMGR_CORE_EMAC1_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
4880 
4881 /*
4882  * Field : awsid
4883  *
4884  * awsid register
4885  *
4886  * Field Access Macros:
4887  *
4888  */
4889 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field. */
4890 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_LSB 20
4891 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field. */
4892 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_MSB 29
4893 /* The width in bits of the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field. */
4894 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_WIDTH 10
4895 /* The mask used to set the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field value. */
4896 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_SET_MSK 0x3ff00000
4897 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field value. */
4898 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_CLR_MSK 0xc00fffff
4899 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field. */
4900 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_RESET 0x0
4901 /* Extracts the ALT_SYSMGR_CORE_EMAC1_ACE_AWSID field value from a register. */
4902 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
4903 /* Produces a ALT_SYSMGR_CORE_EMAC1_ACE_AWSID register field value suitable for setting the register. */
4904 #define ALT_SYSMGR_CORE_EMAC1_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
4905 
4906 #ifndef __ASSEMBLY__
4907 /*
4908  * WARNING: The C register and register group struct declarations are provided for
4909  * convenience and illustrative purposes. They should, however, be used with
4910  * caution as the C language standard provides no guarantees about the alignment or
4911  * atomicity of device memory accesses. The recommended practice for coding device
4912  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4913  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4914  * alt_write_dword() functions for 64 bit registers.
4915  *
4916  * The struct declaration for register ALT_SYSMGR_CORE_EMAC1_ACE.
4917  */
4918 struct ALT_SYSMGR_CORE_EMAC1_ACE_s
4919 {
4920  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_EMAC1_ACE_ARDOMAIN */
4921  uint32_t : 2; /* *UNDEFINED* */
4922  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_EMAC1_ACE_AWDOMAIN */
4923  uint32_t : 2; /* *UNDEFINED* */
4924  volatile uint32_t arsid : 10; /* ALT_SYSMGR_CORE_EMAC1_ACE_ARSID */
4925  uint32_t : 2; /* *UNDEFINED* */
4926  volatile uint32_t awsid : 10; /* ALT_SYSMGR_CORE_EMAC1_ACE_AWSID */
4927  uint32_t : 2; /* *UNDEFINED* */
4928 };
4929 
4930 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC1_ACE. */
4931 typedef struct ALT_SYSMGR_CORE_EMAC1_ACE_s ALT_SYSMGR_CORE_EMAC1_ACE_t;
4932 #endif /* __ASSEMBLY__ */
4933 
4934 /* The reset value of the ALT_SYSMGR_CORE_EMAC1_ACE register. */
4935 #define ALT_SYSMGR_CORE_EMAC1_ACE_RESET 0x00000033
4936 /* The byte offset of the ALT_SYSMGR_CORE_EMAC1_ACE register from the beginning of the component. */
4937 #define ALT_SYSMGR_CORE_EMAC1_ACE_OFST 0x54
4938 
4939 /*
4940  * Register : emac2_ace
4941  *
4942  * The EMAC2 ACE-lite control register
4943  *
4944  * Register Layout
4945  *
4946  * Bits | Access | Reset | Description
4947  * :--------|:-------|:------|:-----------------------------------
4948  * [1:0] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN
4949  * [3:2] | ??? | 0x0 | *UNDEFINED*
4950  * [5:4] | RW | 0x3 | ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN
4951  * [7:6] | ??? | 0x0 | *UNDEFINED*
4952  * [17:8] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_ACE_ARSID
4953  * [19:18] | ??? | 0x0 | *UNDEFINED*
4954  * [29:20] | RW | 0x0 | ALT_SYSMGR_CORE_EMAC2_ACE_AWSID
4955  * [31:30] | ??? | 0x0 | *UNDEFINED*
4956  *
4957  */
4958 /*
4959  * Field : ardomain
4960  *
4961  * ar domain register
4962  *
4963  * Field Access Macros:
4964  *
4965  */
4966 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field. */
4967 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_LSB 0
4968 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field. */
4969 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_MSB 1
4970 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field. */
4971 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_WIDTH 2
4972 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field value. */
4973 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_SET_MSK 0x00000003
4974 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field value. */
4975 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_CLR_MSK 0xfffffffc
4976 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field. */
4977 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_RESET 0x3
4978 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN field value from a register. */
4979 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_GET(value) (((value) & 0x00000003) >> 0)
4980 /* Produces a ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN register field value suitable for setting the register. */
4981 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN_SET(value) (((value) << 0) & 0x00000003)
4982 
4983 /*
4984  * Field : awdomain
4985  *
4986  * aw domain register
4987  *
4988  * Field Access Macros:
4989  *
4990  */
4991 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field. */
4992 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_LSB 4
4993 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field. */
4994 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_MSB 5
4995 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field. */
4996 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_WIDTH 2
4997 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field value. */
4998 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_SET_MSK 0x00000030
4999 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field value. */
5000 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_CLR_MSK 0xffffffcf
5001 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field. */
5002 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_RESET 0x3
5003 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN field value from a register. */
5004 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_GET(value) (((value) & 0x00000030) >> 4)
5005 /* Produces a ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN register field value suitable for setting the register. */
5006 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN_SET(value) (((value) << 4) & 0x00000030)
5007 
5008 /*
5009  * Field : arsid
5010  *
5011  * arsid register
5012  *
5013  * Field Access Macros:
5014  *
5015  */
5016 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field. */
5017 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_LSB 8
5018 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field. */
5019 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_MSB 17
5020 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field. */
5021 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_WIDTH 10
5022 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field value. */
5023 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_SET_MSK 0x0003ff00
5024 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field value. */
5025 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_CLR_MSK 0xfffc00ff
5026 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field. */
5027 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_RESET 0x0
5028 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ACE_ARSID field value from a register. */
5029 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_GET(value) (((value) & 0x0003ff00) >> 8)
5030 /* Produces a ALT_SYSMGR_CORE_EMAC2_ACE_ARSID register field value suitable for setting the register. */
5031 #define ALT_SYSMGR_CORE_EMAC2_ACE_ARSID_SET(value) (((value) << 8) & 0x0003ff00)
5032 
5033 /*
5034  * Field : awsid
5035  *
5036  * awsid register
5037  *
5038  * Field Access Macros:
5039  *
5040  */
5041 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field. */
5042 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_LSB 20
5043 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field. */
5044 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_MSB 29
5045 /* The width in bits of the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field. */
5046 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_WIDTH 10
5047 /* The mask used to set the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field value. */
5048 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_SET_MSK 0x3ff00000
5049 /* The mask used to clear the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field value. */
5050 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_CLR_MSK 0xc00fffff
5051 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field. */
5052 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_RESET 0x0
5053 /* Extracts the ALT_SYSMGR_CORE_EMAC2_ACE_AWSID field value from a register. */
5054 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_GET(value) (((value) & 0x3ff00000) >> 20)
5055 /* Produces a ALT_SYSMGR_CORE_EMAC2_ACE_AWSID register field value suitable for setting the register. */
5056 #define ALT_SYSMGR_CORE_EMAC2_ACE_AWSID_SET(value) (((value) << 20) & 0x3ff00000)
5057 
5058 #ifndef __ASSEMBLY__
5059 /*
5060  * WARNING: The C register and register group struct declarations are provided for
5061  * convenience and illustrative purposes. They should, however, be used with
5062  * caution as the C language standard provides no guarantees about the alignment or
5063  * atomicity of device memory accesses. The recommended practice for coding device
5064  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5065  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5066  * alt_write_dword() functions for 64 bit registers.
5067  *
5068  * The struct declaration for register ALT_SYSMGR_CORE_EMAC2_ACE.
5069  */
5070 struct ALT_SYSMGR_CORE_EMAC2_ACE_s
5071 {
5072  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_EMAC2_ACE_ARDOMAIN */
5073  uint32_t : 2; /* *UNDEFINED* */
5074  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_EMAC2_ACE_AWDOMAIN */
5075  uint32_t : 2; /* *UNDEFINED* */
5076  volatile uint32_t arsid : 10; /* ALT_SYSMGR_CORE_EMAC2_ACE_ARSID */
5077  uint32_t : 2; /* *UNDEFINED* */
5078  volatile uint32_t awsid : 10; /* ALT_SYSMGR_CORE_EMAC2_ACE_AWSID */
5079  uint32_t : 2; /* *UNDEFINED* */
5080 };
5081 
5082 /* The typedef declaration for register ALT_SYSMGR_CORE_EMAC2_ACE. */
5083 typedef struct ALT_SYSMGR_CORE_EMAC2_ACE_s ALT_SYSMGR_CORE_EMAC2_ACE_t;
5084 #endif /* __ASSEMBLY__ */
5085 
5086 /* The reset value of the ALT_SYSMGR_CORE_EMAC2_ACE register. */
5087 #define ALT_SYSMGR_CORE_EMAC2_ACE_RESET 0x00000033
5088 /* The byte offset of the ALT_SYSMGR_CORE_EMAC2_ACE register from the beginning of the component. */
5089 #define ALT_SYSMGR_CORE_EMAC2_ACE_OFST 0x58
5090 
5091 /*
5092  * Register : nand_axuser
5093  *
5094  * The NAND ACE-lite contrl a(w/r)user register
5095  *
5096  * Register Layout
5097  *
5098  * Bits | Access | Reset | Description
5099  * :--------|:-------|:------|:-----------------------------------
5100  * [9:0] | RW | 0x0 | ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER
5101  * [15:10] | ??? | 0x0 | *UNDEFINED*
5102  * [25:16] | RW | 0x0 | ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER
5103  * [31:26] | ??? | 0x0 | *UNDEFINED*
5104  *
5105  */
5106 /*
5107  * Field : awuser
5108  *
5109  * ar user register sid
5110  *
5111  * Field Access Macros:
5112  *
5113  */
5114 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field. */
5115 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_LSB 0
5116 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field. */
5117 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_MSB 9
5118 /* The width in bits of the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field. */
5119 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_WIDTH 10
5120 /* The mask used to set the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field value. */
5121 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_SET_MSK 0x000003ff
5122 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field value. */
5123 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_CLR_MSK 0xfffffc00
5124 /* The reset value of the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field. */
5125 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_RESET 0x0
5126 /* Extracts the ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER field value from a register. */
5127 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
5128 /* Produces a ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER register field value suitable for setting the register. */
5129 #define ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
5130 
5131 /*
5132  * Field : aruser
5133  *
5134  * aw user register sid
5135  *
5136  * Field Access Macros:
5137  *
5138  */
5139 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field. */
5140 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_LSB 16
5141 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field. */
5142 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_MSB 25
5143 /* The width in bits of the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field. */
5144 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_WIDTH 10
5145 /* The mask used to set the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field value. */
5146 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_SET_MSK 0x03ff0000
5147 /* The mask used to clear the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field value. */
5148 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_CLR_MSK 0xfc00ffff
5149 /* The reset value of the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field. */
5150 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_RESET 0x0
5151 /* Extracts the ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER field value from a register. */
5152 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
5153 /* Produces a ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER register field value suitable for setting the register. */
5154 #define ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
5155 
5156 #ifndef __ASSEMBLY__
5157 /*
5158  * WARNING: The C register and register group struct declarations are provided for
5159  * convenience and illustrative purposes. They should, however, be used with
5160  * caution as the C language standard provides no guarantees about the alignment or
5161  * atomicity of device memory accesses. The recommended practice for coding device
5162  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5163  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5164  * alt_write_dword() functions for 64 bit registers.
5165  *
5166  * The struct declaration for register ALT_SYSMGR_CORE_NAND_AXUSER.
5167  */
5168 struct ALT_SYSMGR_CORE_NAND_AXUSER_s
5169 {
5170  volatile uint32_t awuser : 10; /* ALT_SYSMGR_CORE_NAND_AXUSER_AWUSER */
5171  uint32_t : 6; /* *UNDEFINED* */
5172  volatile uint32_t aruser : 10; /* ALT_SYSMGR_CORE_NAND_AXUSER_ARUSER */
5173  uint32_t : 6; /* *UNDEFINED* */
5174 };
5175 
5176 /* The typedef declaration for register ALT_SYSMGR_CORE_NAND_AXUSER. */
5177 typedef struct ALT_SYSMGR_CORE_NAND_AXUSER_s ALT_SYSMGR_CORE_NAND_AXUSER_t;
5178 #endif /* __ASSEMBLY__ */
5179 
5180 /* The reset value of the ALT_SYSMGR_CORE_NAND_AXUSER register. */
5181 #define ALT_SYSMGR_CORE_NAND_AXUSER_RESET 0x00000000
5182 /* The byte offset of the ALT_SYSMGR_CORE_NAND_AXUSER register from the beginning of the component. */
5183 #define ALT_SYSMGR_CORE_NAND_AXUSER_OFST 0x5c
5184 
5185 /*
5186  * Register : FPGA interface Individual Enable Register - fpgaintf_en_1
5187  *
5188  * Used to disable individual interfaces between the FPGA and HPS.
5189  *
5190  * This register is reset only on a cold reset (ignores warm reset).
5191  *
5192  * Register Layout
5193  *
5194  * Bits | Access | Reset | Description
5195  * :--------|:-------|:------|:------------------------------
5196  * [0] | RW | 0x0 | Trace Interface
5197  * [3:1] | ??? | 0x0 | *UNDEFINED*
5198  * [4] | RW | 0x1 | Trace Interface
5199  * [7:5] | ??? | 0x0 | *UNDEFINED*
5200  * [8] | RW | 0x1 | Debug APB Interface
5201  * [15:9] | ??? | 0x0 | *UNDEFINED*
5202  * [16] | RW | 0x1 | STM Event Interface
5203  * [23:17] | ??? | 0x0 | *UNDEFINED*
5204  * [24] | RW | 0x1 | Cross Trigger Interface (CTI)
5205  * [31:25] | ??? | 0x0 | *UNDEFINED*
5206  *
5207  */
5208 /*
5209  * Field : Trace Interface - tracein
5210  *
5211  * Gates the isolator of TPIU
5212  *
5213  * Field Enumeration Values:
5214  *
5215  * Enum | Value | Description
5216  * :------------------------------------------------|:------|:------------
5217  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_DISABLE | 0x0 |
5218  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_ENABLE | 0x1 |
5219  *
5220  * Field Access Macros:
5221  *
5222  */
5223 /*
5224  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN
5225  *
5226  */
5227 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_DISABLE 0x0
5228 /*
5229  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN
5230  *
5231  */
5232 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_E_ENABLE 0x1
5233 
5234 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field. */
5235 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_LSB 0
5236 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field. */
5237 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_MSB 0
5238 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field. */
5239 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_WIDTH 1
5240 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field value. */
5241 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_SET_MSK 0x00000001
5242 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field value. */
5243 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_CLR_MSK 0xfffffffe
5244 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field. */
5245 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_RESET 0x0
5246 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN field value from a register. */
5247 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_GET(value) (((value) & 0x00000001) >> 0)
5248 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN register field value suitable for setting the register. */
5249 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEIN_SET(value) (((value) << 0) & 0x00000001)
5250 
5251 /*
5252  * Field : Trace Interface - traceout
5253  *
5254  * Gates the isolator of CoreSight
5255  *
5256  * Field Enumeration Values:
5257  *
5258  * Enum | Value | Description
5259  * :-------------------------------------------------|:------|:------------
5260  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_DISABLE | 0x0 |
5261  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_ENABLE | 0x1 |
5262  *
5263  * Field Access Macros:
5264  *
5265  */
5266 /*
5267  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT
5268  *
5269  */
5270 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_DISABLE 0x0
5271 /*
5272  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT
5273  *
5274  */
5275 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_E_ENABLE 0x1
5276 
5277 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field. */
5278 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_LSB 4
5279 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field. */
5280 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_MSB 4
5281 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field. */
5282 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_WIDTH 1
5283 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field value. */
5284 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_SET_MSK 0x00000010
5285 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field value. */
5286 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_CLR_MSK 0xffffffef
5287 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field. */
5288 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_RESET 0x1
5289 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT field value from a register. */
5290 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_GET(value) (((value) & 0x00000010) >> 4)
5291 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT register field value suitable for setting the register. */
5292 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_TRACEOUT_SET(value) (((value) << 4) & 0x00000010)
5293 
5294 /*
5295  * Field : Debug APB Interface - dbgapb
5296  *
5297  * Used to disable the debug APB interface. This interface allows the HPS debug
5298  * logic to communicate with debug APB slaves in the FPGA fabric.
5299  *
5300  * Field Enumeration Values:
5301  *
5302  * Enum | Value | Description
5303  * :-----------------------------------------------|:------|:------------
5304  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_DISABLE | 0x0 |
5305  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_ENABLE | 0x1 |
5306  *
5307  * Field Access Macros:
5308  *
5309  */
5310 /*
5311  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB
5312  *
5313  */
5314 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_DISABLE 0x0
5315 /*
5316  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB
5317  *
5318  */
5319 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_E_ENABLE 0x1
5320 
5321 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field. */
5322 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_LSB 8
5323 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field. */
5324 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_MSB 8
5325 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field. */
5326 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_WIDTH 1
5327 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field value. */
5328 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_SET_MSK 0x00000100
5329 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field value. */
5330 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_CLR_MSK 0xfffffeff
5331 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field. */
5332 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_RESET 0x1
5333 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB field value from a register. */
5334 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_GET(value) (((value) & 0x00000100) >> 8)
5335 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB register field value suitable for setting the register. */
5336 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_DBGAPB_SET(value) (((value) << 8) & 0x00000100)
5337 
5338 /*
5339  * Field : STM Event Interface - stmevent
5340  *
5341  * Used to disable the STM event interface. This interface allows logic in the FPGA
5342  * fabric to trigger events to the STM debug module in the HPS.
5343  *
5344  * Field Enumeration Values:
5345  *
5346  * Enum | Value | Description
5347  * :-------------------------------------------------|:------|:------------
5348  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_DISABLE | 0x0 |
5349  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_ENABLE | 0x1 |
5350  *
5351  * Field Access Macros:
5352  *
5353  */
5354 /*
5355  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT
5356  *
5357  */
5358 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_DISABLE 0x0
5359 /*
5360  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT
5361  *
5362  */
5363 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_E_ENABLE 0x1
5364 
5365 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field. */
5366 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_LSB 16
5367 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field. */
5368 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_MSB 16
5369 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field. */
5370 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_WIDTH 1
5371 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field value. */
5372 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_SET_MSK 0x00010000
5373 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field value. */
5374 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_CLR_MSK 0xfffeffff
5375 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field. */
5376 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_RESET 0x1
5377 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT field value from a register. */
5378 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_GET(value) (((value) & 0x00010000) >> 16)
5379 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT register field value suitable for setting the register. */
5380 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_STMEVENT_SET(value) (((value) << 16) & 0x00010000)
5381 
5382 /*
5383  * Field : Cross Trigger Interface (CTI) - ctmtrigger
5384  *
5385  * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note
5386  * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA
5387  * Fabric.
5388  *
5389  * Field Enumeration Values:
5390  *
5391  * Enum | Value | Description
5392  * :---------------------------------------------------|:------|:------------
5393  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_DISABLE | 0x0 |
5394  * ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_ENABLE | 0x1 |
5395  *
5396  * Field Access Macros:
5397  *
5398  */
5399 /*
5400  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER
5401  *
5402  */
5403 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_DISABLE 0x0
5404 /*
5405  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER
5406  *
5407  */
5408 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_E_ENABLE 0x1
5409 
5410 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field. */
5411 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_LSB 24
5412 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field. */
5413 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_MSB 24
5414 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field. */
5415 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_WIDTH 1
5416 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field value. */
5417 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_SET_MSK 0x01000000
5418 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field value. */
5419 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_CLR_MSK 0xfeffffff
5420 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field. */
5421 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_RESET 0x1
5422 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER field value from a register. */
5423 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_GET(value) (((value) & 0x01000000) >> 24)
5424 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER register field value suitable for setting the register. */
5425 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_CTMTRIGGER_SET(value) (((value) << 24) & 0x01000000)
5426 
5427 #ifndef __ASSEMBLY__
5428 /*
5429  * WARNING: The C register and register group struct declarations are provided for
5430  * convenience and illustrative purposes. They should, however, be used with
5431  * caution as the C language standard provides no guarantees about the alignment or
5432  * atomicity of device memory accesses. The recommended practice for coding device
5433  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5434  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5435  * alt_write_dword() functions for 64 bit registers.
5436  *
5437  * The struct declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_1.
5438  */
5439 struct ALT_SYSMGR_CORE_FPGAINTF_EN_1_s
5440 {
5441  volatile uint32_t tracein : 1; /* Trace Interface */
5442  uint32_t : 3; /* *UNDEFINED* */
5443  volatile uint32_t traceout : 1; /* Trace Interface */
5444  uint32_t : 3; /* *UNDEFINED* */
5445  volatile uint32_t dbgapb : 1; /* Debug APB Interface */
5446  uint32_t : 7; /* *UNDEFINED* */
5447  volatile uint32_t stmevent : 1; /* STM Event Interface */
5448  uint32_t : 7; /* *UNDEFINED* */
5449  volatile uint32_t ctmtrigger : 1; /* Cross Trigger Interface (CTI) */
5450  uint32_t : 7; /* *UNDEFINED* */
5451 };
5452 
5453 /* The typedef declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_1. */
5454 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_1_s ALT_SYSMGR_CORE_FPGAINTF_EN_1_t;
5455 #endif /* __ASSEMBLY__ */
5456 
5457 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_1 register. */
5458 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_RESET 0x01010110
5459 /* The byte offset of the ALT_SYSMGR_CORE_FPGAINTF_EN_1 register from the beginning of the component. */
5460 #define ALT_SYSMGR_CORE_FPGAINTF_EN_1_OFST 0x68
5461 
5462 /*
5463  * Register : FPGA interface Individual Enable Register - fpgaintf_en_2
5464  *
5465  * Used to disable individual interfaces between the FPGA and HPS.
5466  *
5467  * This register is reset only on a cold reset (ignores warm reset).
5468  *
5469  * Register Layout
5470  *
5471  * Bits | Access | Reset | Description
5472  * :--------|:-------|:------|:-----------------------------
5473  * [3:0] | ??? | 0x0 | *UNDEFINED*
5474  * [4] | RW | 0x0 | NAND Flash Controller Module
5475  * [7:5] | ??? | 0x0 | *UNDEFINED*
5476  * [8] | RW | 0x0 | SD/MMC Controller Module
5477  * [15:9] | ??? | 0x0 | *UNDEFINED*
5478  * [16] | RW | 0x0 | SPI Master Module
5479  * [23:17] | ??? | 0x0 | *UNDEFINED*
5480  * [24] | RW | 0x0 | SPI Master Module
5481  * [31:25] | ??? | 0x0 | *UNDEFINED*
5482  *
5483  */
5484 /*
5485  * Field : NAND Flash Controller Module - nand
5486  *
5487  * Used to disable signals from the FPGA fabric to the NAND flash controller module
5488  * that could potentially interfere with its normal operation.
5489  *
5490  * Field Enumeration Values:
5491  *
5492  * Enum | Value | Description
5493  * :---------------------------------------------|:------|:------------
5494  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_DISABLE | 0x0 |
5495  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_ENABLE | 0x1 |
5496  *
5497  * Field Access Macros:
5498  *
5499  */
5500 /*
5501  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND
5502  *
5503  */
5504 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_DISABLE 0x0
5505 /*
5506  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND
5507  *
5508  */
5509 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_E_ENABLE 0x1
5510 
5511 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field. */
5512 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_LSB 4
5513 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field. */
5514 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_MSB 4
5515 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field. */
5516 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_WIDTH 1
5517 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field value. */
5518 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010
5519 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field value. */
5520 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef
5521 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field. */
5522 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_RESET 0x0
5523 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND field value from a register. */
5524 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4)
5525 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND register field value suitable for setting the register. */
5526 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010)
5527 
5528 /*
5529  * Field : SD/MMC Controller Module - sdmmc
5530  *
5531  * Used to disable signals from the FPGA fabric to the SD/MMC controller module
5532  * that could potentially interfere with its normal operation.
5533  *
5534  * Field Enumeration Values:
5535  *
5536  * Enum | Value | Description
5537  * :----------------------------------------------|:------|:------------
5538  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_DISABLE | 0x0 |
5539  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_ENABLE | 0x1 |
5540  *
5541  * Field Access Macros:
5542  *
5543  */
5544 /*
5545  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC
5546  *
5547  */
5548 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_DISABLE 0x0
5549 /*
5550  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC
5551  *
5552  */
5553 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_E_ENABLE 0x1
5554 
5555 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field. */
5556 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_LSB 8
5557 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field. */
5558 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_MSB 8
5559 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field. */
5560 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_WIDTH 1
5561 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field value. */
5562 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100
5563 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field value. */
5564 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff
5565 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field. */
5566 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_RESET 0x0
5567 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC field value from a register. */
5568 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8)
5569 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC register field value suitable for setting the register. */
5570 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100)
5571 
5572 /*
5573  * Field : SPI Master Module - spim_0
5574  *
5575  * Used to disable signals from the FPGA fabric to the SPI master modules that
5576  * could potentially interfere with their normal operation.
5577  *
5578  * The array index corresponds to the SPI master module instance.
5579  *
5580  * Field Enumeration Values:
5581  *
5582  * Enum | Value | Description
5583  * :-----------------------------------------------|:------|:------------
5584  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_DISABLE | 0x0 |
5585  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_ENABLE | 0x1 |
5586  *
5587  * Field Access Macros:
5588  *
5589  */
5590 /*
5591  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0
5592  *
5593  */
5594 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_DISABLE 0x0
5595 /*
5596  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0
5597  *
5598  */
5599 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_E_ENABLE 0x1
5600 
5601 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field. */
5602 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_LSB 16
5603 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field. */
5604 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_MSB 16
5605 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field. */
5606 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_WIDTH 1
5607 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field value. */
5608 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000
5609 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field value. */
5610 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff
5611 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field. */
5612 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_RESET 0x0
5613 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 field value from a register. */
5614 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16)
5615 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0 register field value suitable for setting the register. */
5616 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000)
5617 
5618 /*
5619  * Field : SPI Master Module - spim_1
5620  *
5621  * Used to disable signals from the FPGA fabric to the SPI master modules that
5622  * could potentially interfere with their normal operation.
5623  *
5624  * The array index corresponds to the SPI master module instance.
5625  *
5626  * Field Enumeration Values:
5627  *
5628  * Enum | Value | Description
5629  * :-----------------------------------------------|:------|:------------
5630  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_DISABLE | 0x0 |
5631  * ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_ENABLE | 0x1 |
5632  *
5633  * Field Access Macros:
5634  *
5635  */
5636 /*
5637  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1
5638  *
5639  */
5640 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_DISABLE 0x0
5641 /*
5642  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1
5643  *
5644  */
5645 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_E_ENABLE 0x1
5646 
5647 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field. */
5648 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_LSB 24
5649 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field. */
5650 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_MSB 24
5651 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field. */
5652 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_WIDTH 1
5653 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field value. */
5654 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000
5655 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field value. */
5656 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff
5657 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field. */
5658 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_RESET 0x0
5659 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 field value from a register. */
5660 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24)
5661 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1 register field value suitable for setting the register. */
5662 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000)
5663 
5664 #ifndef __ASSEMBLY__
5665 /*
5666  * WARNING: The C register and register group struct declarations are provided for
5667  * convenience and illustrative purposes. They should, however, be used with
5668  * caution as the C language standard provides no guarantees about the alignment or
5669  * atomicity of device memory accesses. The recommended practice for coding device
5670  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5671  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5672  * alt_write_dword() functions for 64 bit registers.
5673  *
5674  * The struct declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_2.
5675  */
5676 struct ALT_SYSMGR_CORE_FPGAINTF_EN_2_s
5677 {
5678  uint32_t : 4; /* *UNDEFINED* */
5679  volatile uint32_t nand : 1; /* NAND Flash Controller Module */
5680  uint32_t : 3; /* *UNDEFINED* */
5681  volatile uint32_t sdmmc : 1; /* SD/MMC Controller Module */
5682  uint32_t : 7; /* *UNDEFINED* */
5683  volatile uint32_t spim_0 : 1; /* SPI Master Module */
5684  uint32_t : 7; /* *UNDEFINED* */
5685  volatile uint32_t spim_1 : 1; /* SPI Master Module */
5686  uint32_t : 7; /* *UNDEFINED* */
5687 };
5688 
5689 /* The typedef declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_2. */
5690 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_2_s ALT_SYSMGR_CORE_FPGAINTF_EN_2_t;
5691 #endif /* __ASSEMBLY__ */
5692 
5693 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_2 register. */
5694 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_RESET 0x00000000
5695 /* The byte offset of the ALT_SYSMGR_CORE_FPGAINTF_EN_2 register from the beginning of the component. */
5696 #define ALT_SYSMGR_CORE_FPGAINTF_EN_2_OFST 0x6c
5697 
5698 /*
5699  * Register : FPGA interface Individual Enable Register - fpgaintf_en_3
5700  *
5701  * Used to disable individual interfaces between the FPGA and HPS.
5702  *
5703  * This register is reset only on a cold reset (ignores warm reset).
5704  *
5705  * Register Layout
5706  *
5707  * Bits | Access | Reset | Description
5708  * :--------|:-------|:------|:------------
5709  * [0] | RW | 0x0 | EMAC Module
5710  * [3:1] | ??? | 0x0 | *UNDEFINED*
5711  * [4] | RW | 0x0 | EMAC Module
5712  * [7:5] | ??? | 0x0 | *UNDEFINED*
5713  * [8] | RW | 0x0 | EMAC Module
5714  * [11:9] | ??? | 0x0 | *UNDEFINED*
5715  * [12] | RW | 0x0 | EMAC Module
5716  * [15:13] | ??? | 0x0 | *UNDEFINED*
5717  * [16] | RW | 0x0 | EMAC Module
5718  * [19:17] | ??? | 0x0 | *UNDEFINED*
5719  * [20] | RW | 0x0 | EMAC Module
5720  * [31:21] | ??? | 0x0 | *UNDEFINED*
5721  *
5722  */
5723 /*
5724  * Field : EMAC Module - emac_0
5725  *
5726  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5727  * potentially interfere with their normal operation.
5728  *
5729  * The array index corresponds to the EMAC module instance.
5730  *
5731  * Field Enumeration Values:
5732  *
5733  * Enum | Value | Description
5734  * :-----------------------------------------------|:------|:------------
5735  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_DISABLE | 0x0 |
5736  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_ENABLE | 0x1 |
5737  *
5738  * Field Access Macros:
5739  *
5740  */
5741 /*
5742  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0
5743  *
5744  */
5745 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_DISABLE 0x0
5746 /*
5747  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0
5748  *
5749  */
5750 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_E_ENABLE 0x1
5751 
5752 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field. */
5753 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_LSB 0
5754 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field. */
5755 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_MSB 0
5756 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field. */
5757 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_WIDTH 1
5758 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field value. */
5759 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SET_MSK 0x00000001
5760 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field value. */
5761 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_CLR_MSK 0xfffffffe
5762 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field. */
5763 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_RESET 0x0
5764 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 field value from a register. */
5765 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_GET(value) (((value) & 0x00000001) >> 0)
5766 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0 register field value suitable for setting the register. */
5767 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SET(value) (((value) << 0) & 0x00000001)
5768 
5769 /*
5770  * Field : EMAC Module - emac_0_switch
5771  *
5772  * EMAC FPGA interface switch Enable
5773  *
5774  * Field Enumeration Values:
5775  *
5776  * Enum | Value | Description
5777  * :------------------------------------------------------|:------|:------------
5778  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DISABLE | 0x0 |
5779  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_ENABLE | 0x1 |
5780  *
5781  * Field Access Macros:
5782  *
5783  */
5784 /*
5785  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH
5786  *
5787  */
5788 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DISABLE 0x0
5789 /*
5790  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH
5791  *
5792  */
5793 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_E_ENABLE 0x1
5794 
5795 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5796 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_LSB 4
5797 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5798 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_MSB 4
5799 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5800 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_WIDTH 1
5801 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field value. */
5802 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_SET_MSK 0x00000010
5803 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field value. */
5804 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_CLR_MSK 0xffffffef
5805 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5806 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_RESET 0x0
5807 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH field value from a register. */
5808 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_GET(value) (((value) & 0x00000010) >> 4)
5809 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH register field value suitable for setting the register. */
5810 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SWITCH_SET(value) (((value) << 4) & 0x00000010)
5811 
5812 /*
5813  * Field : EMAC Module - emac_1
5814  *
5815  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5816  * potentially interfere with their normal operation.
5817  *
5818  * The array index corresponds to the EMAC module instance.
5819  *
5820  * Field Enumeration Values:
5821  *
5822  * Enum | Value | Description
5823  * :-----------------------------------------------|:------|:------------
5824  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_DISABLE | 0x0 |
5825  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_ENABLE | 0x1 |
5826  *
5827  * Field Access Macros:
5828  *
5829  */
5830 /*
5831  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1
5832  *
5833  */
5834 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_DISABLE 0x0
5835 /*
5836  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1
5837  *
5838  */
5839 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_E_ENABLE 0x1
5840 
5841 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field. */
5842 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_LSB 8
5843 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field. */
5844 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_MSB 8
5845 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field. */
5846 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_WIDTH 1
5847 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field value. */
5848 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SET_MSK 0x00000100
5849 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field value. */
5850 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_CLR_MSK 0xfffffeff
5851 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field. */
5852 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_RESET 0x0
5853 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 field value from a register. */
5854 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_GET(value) (((value) & 0x00000100) >> 8)
5855 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1 register field value suitable for setting the register. */
5856 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SET(value) (((value) << 8) & 0x00000100)
5857 
5858 /*
5859  * Field : EMAC Module - emac_1_switch
5860  *
5861  * EMAC FPGA interface switch Enable
5862  *
5863  * Field Enumeration Values:
5864  *
5865  * Enum | Value | Description
5866  * :------------------------------------------------------|:------|:------------
5867  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DISABLE | 0x0 |
5868  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_ENABLE | 0x1 |
5869  *
5870  * Field Access Macros:
5871  *
5872  */
5873 /*
5874  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH
5875  *
5876  */
5877 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DISABLE 0x0
5878 /*
5879  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH
5880  *
5881  */
5882 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_E_ENABLE 0x1
5883 
5884 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5885 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_LSB 12
5886 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5887 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_MSB 12
5888 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5889 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_WIDTH 1
5890 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field value. */
5891 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_SET_MSK 0x00001000
5892 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field value. */
5893 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_CLR_MSK 0xffffefff
5894 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5895 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_RESET 0x0
5896 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH field value from a register. */
5897 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_GET(value) (((value) & 0x00001000) >> 12)
5898 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH register field value suitable for setting the register. */
5899 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SWITCH_SET(value) (((value) << 12) & 0x00001000)
5900 
5901 /*
5902  * Field : EMAC Module - emac_2
5903  *
5904  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5905  * potentially interfere with their normal operation.
5906  *
5907  * The array index corresponds to the EMAC module instance.
5908  *
5909  * Field Enumeration Values:
5910  *
5911  * Enum | Value | Description
5912  * :-----------------------------------------------|:------|:------------
5913  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_DISABLE | 0x0 |
5914  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_ENABLE | 0x1 |
5915  *
5916  * Field Access Macros:
5917  *
5918  */
5919 /*
5920  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2
5921  *
5922  */
5923 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_DISABLE 0x0
5924 /*
5925  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2
5926  *
5927  */
5928 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_E_ENABLE 0x1
5929 
5930 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field. */
5931 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_LSB 16
5932 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field. */
5933 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_MSB 16
5934 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field. */
5935 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_WIDTH 1
5936 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field value. */
5937 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SET_MSK 0x00010000
5938 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field value. */
5939 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_CLR_MSK 0xfffeffff
5940 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field. */
5941 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_RESET 0x0
5942 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 field value from a register. */
5943 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_GET(value) (((value) & 0x00010000) >> 16)
5944 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2 register field value suitable for setting the register. */
5945 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SET(value) (((value) << 16) & 0x00010000)
5946 
5947 /*
5948  * Field : EMAC Module - emac_2_switch
5949  *
5950  * EMAC FPGA interface switch Enable
5951  *
5952  * Field Enumeration Values:
5953  *
5954  * Enum | Value | Description
5955  * :------------------------------------------------------|:------|:------------
5956  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DISABLE | 0x0 |
5957  * ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_ENABLE | 0x1 |
5958  *
5959  * Field Access Macros:
5960  *
5961  */
5962 /*
5963  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH
5964  *
5965  */
5966 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DISABLE 0x0
5967 /*
5968  * Enumerated value for register field ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH
5969  *
5970  */
5971 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_E_ENABLE 0x1
5972 
5973 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5974 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_LSB 20
5975 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5976 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_MSB 20
5977 /* The width in bits of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5978 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_WIDTH 1
5979 /* The mask used to set the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field value. */
5980 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_SET_MSK 0x00100000
5981 /* The mask used to clear the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field value. */
5982 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_CLR_MSK 0xffefffff
5983 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5984 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_RESET 0x0
5985 /* Extracts the ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH field value from a register. */
5986 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_GET(value) (((value) & 0x00100000) >> 20)
5987 /* Produces a ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH register field value suitable for setting the register. */
5988 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SWITCH_SET(value) (((value) << 20) & 0x00100000)
5989 
5990 #ifndef __ASSEMBLY__
5991 /*
5992  * WARNING: The C register and register group struct declarations are provided for
5993  * convenience and illustrative purposes. They should, however, be used with
5994  * caution as the C language standard provides no guarantees about the alignment or
5995  * atomicity of device memory accesses. The recommended practice for coding device
5996  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5997  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5998  * alt_write_dword() functions for 64 bit registers.
5999  *
6000  * The struct declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_3.
6001  */
6002 struct ALT_SYSMGR_CORE_FPGAINTF_EN_3_s
6003 {
6004  volatile uint32_t emac_0 : 1; /* EMAC Module */
6005  uint32_t : 3; /* *UNDEFINED* */
6006  volatile uint32_t emac_0_switch : 1; /* EMAC Module */
6007  uint32_t : 3; /* *UNDEFINED* */
6008  volatile uint32_t emac_1 : 1; /* EMAC Module */
6009  uint32_t : 3; /* *UNDEFINED* */
6010  volatile uint32_t emac_1_switch : 1; /* EMAC Module */
6011  uint32_t : 3; /* *UNDEFINED* */
6012  volatile uint32_t emac_2 : 1; /* EMAC Module */
6013  uint32_t : 3; /* *UNDEFINED* */
6014  volatile uint32_t emac_2_switch : 1; /* EMAC Module */
6015  uint32_t : 11; /* *UNDEFINED* */
6016 };
6017 
6018 /* The typedef declaration for register ALT_SYSMGR_CORE_FPGAINTF_EN_3. */
6019 typedef struct ALT_SYSMGR_CORE_FPGAINTF_EN_3_s ALT_SYSMGR_CORE_FPGAINTF_EN_3_t;
6020 #endif /* __ASSEMBLY__ */
6021 
6022 /* The reset value of the ALT_SYSMGR_CORE_FPGAINTF_EN_3 register. */
6023 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_RESET 0x00000000
6024 /* The byte offset of the ALT_SYSMGR_CORE_FPGAINTF_EN_3 register from the beginning of the component. */
6025 #define ALT_SYSMGR_CORE_FPGAINTF_EN_3_OFST 0x70
6026 
6027 /*
6028  * Register : dma_l3master
6029  *
6030  * Register for ACE-lite control - dma_l3master
6031  *
6032  * Register Layout
6033  *
6034  * Bits | Access | Reset | Description
6035  * :--------|:-------|:------|:--------------------------------------
6036  * [9:0] | RW | 0x0 | ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER
6037  * [11:10] | ??? | 0x0 | *UNDEFINED*
6038  * [13:12] | RW | 0x3 | ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN
6039  * [15:14] | RW | 0x3 | ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN
6040  * [25:16] | RW | 0x0 | ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER
6041  * [31:26] | ??? | 0x0 | *UNDEFINED*
6042  *
6043  */
6044 /*
6045  * Field : awuser
6046  *
6047  * aw sid register
6048  *
6049  * Field Access Macros:
6050  *
6051  */
6052 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field. */
6053 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_LSB 0
6054 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field. */
6055 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_MSB 9
6056 /* The width in bits of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field. */
6057 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_WIDTH 10
6058 /* The mask used to set the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field value. */
6059 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_SET_MSK 0x000003ff
6060 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field value. */
6061 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_CLR_MSK 0xfffffc00
6062 /* The reset value of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field. */
6063 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_RESET 0x0
6064 /* Extracts the ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER field value from a register. */
6065 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
6066 /* Produces a ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER register field value suitable for setting the register. */
6067 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
6068 
6069 /*
6070  * Field : awdomain
6071  *
6072  * aw domain register
6073  *
6074  * Field Access Macros:
6075  *
6076  */
6077 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field. */
6078 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_LSB 12
6079 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field. */
6080 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_MSB 13
6081 /* The width in bits of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field. */
6082 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_WIDTH 2
6083 /* The mask used to set the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field value. */
6084 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_SET_MSK 0x00003000
6085 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field value. */
6086 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_CLR_MSK 0xffffcfff
6087 /* The reset value of the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field. */
6088 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_RESET 0x3
6089 /* Extracts the ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN field value from a register. */
6090 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
6091 /* Produces a ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN register field value suitable for setting the register. */
6092 #define ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN_SET(value) (((value) << 12) & 0x00003000)
6093 
6094 /*
6095  * Field : ardomain
6096  *
6097  * ar domain regisger
6098  *
6099  * Field Access Macros:
6100  *
6101  */
6102 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field. */
6103 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_LSB 14
6104 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field. */
6105 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_MSB 15
6106 /* The width in bits of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field. */
6107 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_WIDTH 2
6108 /* The mask used to set the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field value. */
6109 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_SET_MSK 0x0000c000
6110 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field value. */
6111 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_CLR_MSK 0xffff3fff
6112 /* The reset value of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field. */
6113 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_RESET 0x3
6114 /* Extracts the ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN field value from a register. */
6115 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x0000c000) >> 14)
6116 /* Produces a ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN register field value suitable for setting the register. */
6117 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN_SET(value) (((value) << 14) & 0x0000c000)
6118 
6119 /*
6120  * Field : aruser
6121  *
6122  * ar sid register
6123  *
6124  * Field Access Macros:
6125  *
6126  */
6127 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field. */
6128 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_LSB 16
6129 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field. */
6130 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_MSB 25
6131 /* The width in bits of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field. */
6132 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_WIDTH 10
6133 /* The mask used to set the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field value. */
6134 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_SET_MSK 0x03ff0000
6135 /* The mask used to clear the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field value. */
6136 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_CLR_MSK 0xfc00ffff
6137 /* The reset value of the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field. */
6138 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_RESET 0x0
6139 /* Extracts the ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER field value from a register. */
6140 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
6141 /* Produces a ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER register field value suitable for setting the register. */
6142 #define ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
6143 
6144 #ifndef __ASSEMBLY__
6145 /*
6146  * WARNING: The C register and register group struct declarations are provided for
6147  * convenience and illustrative purposes. They should, however, be used with
6148  * caution as the C language standard provides no guarantees about the alignment or
6149  * atomicity of device memory accesses. The recommended practice for coding device
6150  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6151  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6152  * alt_write_dword() functions for 64 bit registers.
6153  *
6154  * The struct declaration for register ALT_SYSMGR_CORE_DMA_L3MASTER.
6155  */
6156 struct ALT_SYSMGR_CORE_DMA_L3MASTER_s
6157 {
6158  volatile uint32_t awuser : 10; /* ALT_SYSMGR_CORE_DMA_L3MASTER_AWUSER */
6159  uint32_t : 2; /* *UNDEFINED* */
6160  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_DMA_L3MASTER_AWDOMAIN */
6161  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_DMA_L3MASTER_ARDOMAIN */
6162  volatile uint32_t aruser : 10; /* ALT_SYSMGR_CORE_DMA_L3MASTER_ARUSER */
6163  uint32_t : 6; /* *UNDEFINED* */
6164 };
6165 
6166 /* The typedef declaration for register ALT_SYSMGR_CORE_DMA_L3MASTER. */
6167 typedef struct ALT_SYSMGR_CORE_DMA_L3MASTER_s ALT_SYSMGR_CORE_DMA_L3MASTER_t;
6168 #endif /* __ASSEMBLY__ */
6169 
6170 /* The reset value of the ALT_SYSMGR_CORE_DMA_L3MASTER register. */
6171 #define ALT_SYSMGR_CORE_DMA_L3MASTER_RESET 0x0000f000
6172 /* The byte offset of the ALT_SYSMGR_CORE_DMA_L3MASTER register from the beginning of the component. */
6173 #define ALT_SYSMGR_CORE_DMA_L3MASTER_OFST 0x74
6174 
6175 /*
6176  * Register : etr_l3master
6177  *
6178  * Register for ACE-lite control - etr_l3master
6179  *
6180  * Register Layout
6181  *
6182  * Bits | Access | Reset | Description
6183  * :--------|:-------|:------|:--------------------------------------
6184  * [9:0] | RW | 0x0 | ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER
6185  * [11:10] | ??? | 0x0 | *UNDEFINED*
6186  * [13:12] | RW | 0x3 | ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN
6187  * [15:14] | RW | 0x3 | ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN
6188  * [25:16] | RW | 0x0 | ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER
6189  * [31:26] | ??? | 0x0 | *UNDEFINED*
6190  *
6191  */
6192 /*
6193  * Field : awuser
6194  *
6195  * aw sid register
6196  *
6197  * Field Access Macros:
6198  *
6199  */
6200 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field. */
6201 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_LSB 0
6202 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field. */
6203 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_MSB 9
6204 /* The width in bits of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field. */
6205 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_WIDTH 10
6206 /* The mask used to set the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field value. */
6207 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_SET_MSK 0x000003ff
6208 /* The mask used to clear the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field value. */
6209 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_CLR_MSK 0xfffffc00
6210 /* The reset value of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field. */
6211 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_RESET 0x0
6212 /* Extracts the ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER field value from a register. */
6213 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_GET(value) (((value) & 0x000003ff) >> 0)
6214 /* Produces a ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER register field value suitable for setting the register. */
6215 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER_SET(value) (((value) << 0) & 0x000003ff)
6216 
6217 /*
6218  * Field : awdomain
6219  *
6220  * aw domain register
6221  *
6222  * Field Access Macros:
6223  *
6224  */
6225 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field. */
6226 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_LSB 12
6227 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field. */
6228 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_MSB 13
6229 /* The width in bits of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field. */
6230 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_WIDTH 2
6231 /* The mask used to set the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field value. */
6232 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_SET_MSK 0x00003000
6233 /* The mask used to clear the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field value. */
6234 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_CLR_MSK 0xffffcfff
6235 /* The reset value of the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field. */
6236 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_RESET 0x3
6237 /* Extracts the ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN field value from a register. */
6238 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_GET(value) (((value) & 0x00003000) >> 12)
6239 /* Produces a ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN register field value suitable for setting the register. */
6240 #define ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN_SET(value) (((value) << 12) & 0x00003000)
6241 
6242 /*
6243  * Field : ardomain
6244  *
6245  * ar domain regisger
6246  *
6247  * Field Access Macros:
6248  *
6249  */
6250 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field. */
6251 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_LSB 14
6252 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field. */
6253 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_MSB 15
6254 /* The width in bits of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field. */
6255 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_WIDTH 2
6256 /* The mask used to set the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field value. */
6257 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_SET_MSK 0x0000c000
6258 /* The mask used to clear the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field value. */
6259 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_CLR_MSK 0xffff3fff
6260 /* The reset value of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field. */
6261 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_RESET 0x3
6262 /* Extracts the ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN field value from a register. */
6263 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_GET(value) (((value) & 0x0000c000) >> 14)
6264 /* Produces a ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN register field value suitable for setting the register. */
6265 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN_SET(value) (((value) << 14) & 0x0000c000)
6266 
6267 /*
6268  * Field : aruser
6269  *
6270  * ar sid register
6271  *
6272  * Field Access Macros:
6273  *
6274  */
6275 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field. */
6276 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_LSB 16
6277 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field. */
6278 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_MSB 25
6279 /* The width in bits of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field. */
6280 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_WIDTH 10
6281 /* The mask used to set the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field value. */
6282 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_SET_MSK 0x03ff0000
6283 /* The mask used to clear the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field value. */
6284 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_CLR_MSK 0xfc00ffff
6285 /* The reset value of the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field. */
6286 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_RESET 0x0
6287 /* Extracts the ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER field value from a register. */
6288 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_GET(value) (((value) & 0x03ff0000) >> 16)
6289 /* Produces a ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER register field value suitable for setting the register. */
6290 #define ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER_SET(value) (((value) << 16) & 0x03ff0000)
6291 
6292 #ifndef __ASSEMBLY__
6293 /*
6294  * WARNING: The C register and register group struct declarations are provided for
6295  * convenience and illustrative purposes. They should, however, be used with
6296  * caution as the C language standard provides no guarantees about the alignment or
6297  * atomicity of device memory accesses. The recommended practice for coding device
6298  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6299  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6300  * alt_write_dword() functions for 64 bit registers.
6301  *
6302  * The struct declaration for register ALT_SYSMGR_CORE_ETR_L3MASTER.
6303  */
6304 struct ALT_SYSMGR_CORE_ETR_L3MASTER_s
6305 {
6306  volatile uint32_t awuser : 10; /* ALT_SYSMGR_CORE_ETR_L3MASTER_AWUSER */
6307  uint32_t : 2; /* *UNDEFINED* */
6308  volatile uint32_t awdomain : 2; /* ALT_SYSMGR_CORE_ETR_L3MASTER_AWDOMAIN */
6309  volatile uint32_t ardomain : 2; /* ALT_SYSMGR_CORE_ETR_L3MASTER_ARDOMAIN */
6310  volatile uint32_t aruser : 10; /* ALT_SYSMGR_CORE_ETR_L3MASTER_ARUSER */
6311  uint32_t : 6; /* *UNDEFINED* */
6312 };
6313 
6314 /* The typedef declaration for register ALT_SYSMGR_CORE_ETR_L3MASTER. */
6315 typedef struct ALT_SYSMGR_CORE_ETR_L3MASTER_s ALT_SYSMGR_CORE_ETR_L3MASTER_t;
6316 #endif /* __ASSEMBLY__ */
6317 
6318 /* The reset value of the ALT_SYSMGR_CORE_ETR_L3MASTER register. */
6319 #define ALT_SYSMGR_CORE_ETR_L3MASTER_RESET 0x0000f000
6320 /* The byte offset of the ALT_SYSMGR_CORE_ETR_L3MASTER register from the beginning of the component. */
6321 #define ALT_SYSMGR_CORE_ETR_L3MASTER_OFST 0x78
6322 
6323 /*
6324  * Register : sec_ctrl_slt
6325  *
6326  * This is the clock selection register. The APS oscillator selection is read only
6327  * register. This value is driven from secure manager FS.
6328  *
6329  * Register Layout
6330  *
6331  * Bits | Access | Reset | Description
6332  * :-------|:-------|:------|:---------------------------------
6333  * [0] | R | 0x1 | ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL
6334  * [31:1] | ??? | 0x0 | *UNDEFINED*
6335  *
6336  */
6337 /*
6338  * Field : val
6339  *
6340  * 1 bit register to read the value secure clock selection: secure internal
6341  * oscillator and eosc1
6342  *
6343  * Field Access Macros:
6344  *
6345  */
6346 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field. */
6347 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_LSB 0
6348 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field. */
6349 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_MSB 0
6350 /* The width in bits of the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field. */
6351 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_WIDTH 1
6352 /* The mask used to set the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field value. */
6353 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_SET_MSK 0x00000001
6354 /* The mask used to clear the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field value. */
6355 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_CLR_MSK 0xfffffffe
6356 /* The reset value of the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field. */
6357 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_RESET 0x1
6358 /* Extracts the ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL field value from a register. */
6359 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_GET(value) (((value) & 0x00000001) >> 0)
6360 /* Produces a ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL register field value suitable for setting the register. */
6361 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL_SET(value) (((value) << 0) & 0x00000001)
6362 
6363 #ifndef __ASSEMBLY__
6364 /*
6365  * WARNING: The C register and register group struct declarations are provided for
6366  * convenience and illustrative purposes. They should, however, be used with
6367  * caution as the C language standard provides no guarantees about the alignment or
6368  * atomicity of device memory accesses. The recommended practice for coding device
6369  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6370  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6371  * alt_write_dword() functions for 64 bit registers.
6372  *
6373  * The struct declaration for register ALT_SYSMGR_CORE_SEC_CTRL_SLT.
6374  */
6375 struct ALT_SYSMGR_CORE_SEC_CTRL_SLT_s
6376 {
6377  const volatile uint32_t val : 1; /* ALT_SYSMGR_CORE_SEC_CTRL_SLT_VAL */
6378  uint32_t : 31; /* *UNDEFINED* */
6379 };
6380 
6381 /* The typedef declaration for register ALT_SYSMGR_CORE_SEC_CTRL_SLT. */
6382 typedef struct ALT_SYSMGR_CORE_SEC_CTRL_SLT_s ALT_SYSMGR_CORE_SEC_CTRL_SLT_t;
6383 #endif /* __ASSEMBLY__ */
6384 
6385 /* The reset value of the ALT_SYSMGR_CORE_SEC_CTRL_SLT register. */
6386 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_RESET 0x00000001
6387 /* The byte offset of the ALT_SYSMGR_CORE_SEC_CTRL_SLT register from the beginning of the component. */
6388 #define ALT_SYSMGR_CORE_SEC_CTRL_SLT_OFST 0x80
6389 
6390 /*
6391  * Register : osc_trim
6392  *
6393  * This is the osc_trim register to show internal oscillator
6394  *
6395  * Register Layout
6396  *
6397  * Bits | Access | Reset | Description
6398  * :-------|:-------|:------|:-----------------------------
6399  * [7:0] | R | 0x0 | ALT_SYSMGR_CORE_OSC_TRIM_VAL
6400  * [31:8] | ??? | 0x0 | *UNDEFINED*
6401  *
6402  */
6403 /*
6404  * Field : val
6405  *
6406  * RO 8 bit register that shows trim of internal oscillator
6407  *
6408  * Field Access Macros:
6409  *
6410  */
6411 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field. */
6412 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_LSB 0
6413 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field. */
6414 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_MSB 7
6415 /* The width in bits of the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field. */
6416 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_WIDTH 8
6417 /* The mask used to set the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field value. */
6418 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_SET_MSK 0x000000ff
6419 /* The mask used to clear the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field value. */
6420 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_CLR_MSK 0xffffff00
6421 /* The reset value of the ALT_SYSMGR_CORE_OSC_TRIM_VAL register field. */
6422 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_RESET 0x0
6423 /* Extracts the ALT_SYSMGR_CORE_OSC_TRIM_VAL field value from a register. */
6424 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_GET(value) (((value) & 0x000000ff) >> 0)
6425 /* Produces a ALT_SYSMGR_CORE_OSC_TRIM_VAL register field value suitable for setting the register. */
6426 #define ALT_SYSMGR_CORE_OSC_TRIM_VAL_SET(value) (((value) << 0) & 0x000000ff)
6427 
6428 #ifndef __ASSEMBLY__
6429 /*
6430  * WARNING: The C register and register group struct declarations are provided for
6431  * convenience and illustrative purposes. They should, however, be used with
6432  * caution as the C language standard provides no guarantees about the alignment or
6433  * atomicity of device memory accesses. The recommended practice for coding device
6434  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6435  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6436  * alt_write_dword() functions for 64 bit registers.
6437  *
6438  * The struct declaration for register ALT_SYSMGR_CORE_OSC_TRIM.
6439  */
6440 struct ALT_SYSMGR_CORE_OSC_TRIM_s
6441 {
6442  const volatile uint32_t val : 8; /* ALT_SYSMGR_CORE_OSC_TRIM_VAL */
6443  uint32_t : 24; /* *UNDEFINED* */
6444 };
6445 
6446 /* The typedef declaration for register ALT_SYSMGR_CORE_OSC_TRIM. */
6447 typedef struct ALT_SYSMGR_CORE_OSC_TRIM_s ALT_SYSMGR_CORE_OSC_TRIM_t;
6448 #endif /* __ASSEMBLY__ */
6449 
6450 /* The reset value of the ALT_SYSMGR_CORE_OSC_TRIM register. */
6451 #define ALT_SYSMGR_CORE_OSC_TRIM_RESET 0x00000000
6452 /* The byte offset of the ALT_SYSMGR_CORE_OSC_TRIM register from the beginning of the component. */
6453 #define ALT_SYSMGR_CORE_OSC_TRIM_OFST 0x84
6454 
6455 /*
6456  * Register : ecc_intmask_value
6457  *
6458  * ECC interrupt mask register.
6459  *
6460  * This is a read/write register.
6461  *
6462  * Register Layout
6463  *
6464  * Bits | Access | Reset | Description
6465  * :--------|:-------|:------|:-------------------------------------------
6466  * [0] | ??? | 0x0 | *UNDEFINED*
6467  * [1] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM
6468  * [2] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0
6469  * [3] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1
6470  * [4] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX
6471  * [5] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX
6472  * [6] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX
6473  * [7] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX
6474  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX
6475  * [9] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX
6476  * [10] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA
6477  * [11] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF
6478  * [12] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR
6479  * [13] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD
6480  * [14] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA
6481  * [15] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB
6482  * [16] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0
6483  * [17] | RW | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1
6484  * [31:18] | ??? | 0x0 | *UNDEFINED*
6485  *
6486  */
6487 /*
6488  * Field : ocram
6489  *
6490  * Field Access Macros:
6491  *
6492  */
6493 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field. */
6494 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_LSB 1
6495 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field. */
6496 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_MSB 1
6497 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field. */
6498 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_WIDTH 1
6499 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field value. */
6500 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_SET_MSK 0x00000002
6501 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field value. */
6502 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_CLR_MSK 0xfffffffd
6503 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field. */
6504 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_RESET 0x0
6505 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM field value from a register. */
6506 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6507 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM register field value suitable for setting the register. */
6508 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6509 
6510 /*
6511  * Field : usb0
6512  *
6513  * Field Access Macros:
6514  *
6515  */
6516 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field. */
6517 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_LSB 2
6518 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field. */
6519 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_MSB 2
6520 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field. */
6521 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_WIDTH 1
6522 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field value. */
6523 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_SET_MSK 0x00000004
6524 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field value. */
6525 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_CLR_MSK 0xfffffffb
6526 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field. */
6527 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_RESET 0x0
6528 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 field value from a register. */
6529 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_GET(value) (((value) & 0x00000004) >> 2)
6530 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 register field value suitable for setting the register. */
6531 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0_SET(value) (((value) << 2) & 0x00000004)
6532 
6533 /*
6534  * Field : usb1
6535  *
6536  * Field Access Macros:
6537  *
6538  */
6539 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field. */
6540 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_LSB 3
6541 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field. */
6542 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_MSB 3
6543 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field. */
6544 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_WIDTH 1
6545 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field value. */
6546 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_SET_MSK 0x00000008
6547 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field value. */
6548 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_CLR_MSK 0xfffffff7
6549 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field. */
6550 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_RESET 0x0
6551 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 field value from a register. */
6552 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_GET(value) (((value) & 0x00000008) >> 3)
6553 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 register field value suitable for setting the register. */
6554 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1_SET(value) (((value) << 3) & 0x00000008)
6555 
6556 /*
6557  * Field : emac0_rx
6558  *
6559  * Field Access Macros:
6560  *
6561  */
6562 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field. */
6563 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_LSB 4
6564 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field. */
6565 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_MSB 4
6566 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field. */
6567 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_WIDTH 1
6568 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field value. */
6569 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_SET_MSK 0x00000010
6570 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field value. */
6571 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_CLR_MSK 0xffffffef
6572 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field. */
6573 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_RESET 0x0
6574 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX field value from a register. */
6575 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6576 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX register field value suitable for setting the register. */
6577 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6578 
6579 /*
6580  * Field : emac0_tx
6581  *
6582  * Field Access Macros:
6583  *
6584  */
6585 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field. */
6586 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_LSB 5
6587 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field. */
6588 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_MSB 5
6589 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field. */
6590 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_WIDTH 1
6591 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field value. */
6592 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_SET_MSK 0x00000020
6593 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field value. */
6594 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_CLR_MSK 0xffffffdf
6595 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field. */
6596 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_RESET 0x0
6597 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX field value from a register. */
6598 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6599 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX register field value suitable for setting the register. */
6600 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6601 
6602 /*
6603  * Field : emac1_rx
6604  *
6605  * Field Access Macros:
6606  *
6607  */
6608 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field. */
6609 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_LSB 6
6610 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field. */
6611 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_MSB 6
6612 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field. */
6613 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_WIDTH 1
6614 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field value. */
6615 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_SET_MSK 0x00000040
6616 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field value. */
6617 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_CLR_MSK 0xffffffbf
6618 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field. */
6619 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_RESET 0x0
6620 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX field value from a register. */
6621 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
6622 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX register field value suitable for setting the register. */
6623 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
6624 
6625 /*
6626  * Field : emac1_tx
6627  *
6628  * Field Access Macros:
6629  *
6630  */
6631 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field. */
6632 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_LSB 7
6633 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field. */
6634 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_MSB 7
6635 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field. */
6636 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_WIDTH 1
6637 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field value. */
6638 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_SET_MSK 0x00000080
6639 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field value. */
6640 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_CLR_MSK 0xffffff7f
6641 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field. */
6642 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_RESET 0x0
6643 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX field value from a register. */
6644 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6645 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX register field value suitable for setting the register. */
6646 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6647 
6648 /*
6649  * Field : emac2_rx
6650  *
6651  * Field Access Macros:
6652  *
6653  */
6654 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field. */
6655 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_LSB 8
6656 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field. */
6657 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_MSB 8
6658 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field. */
6659 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_WIDTH 1
6660 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field value. */
6661 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_SET_MSK 0x00000100
6662 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field value. */
6663 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_CLR_MSK 0xfffffeff
6664 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field. */
6665 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_RESET 0x0
6666 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX field value from a register. */
6667 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6668 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX register field value suitable for setting the register. */
6669 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6670 
6671 /*
6672  * Field : emac2_tx
6673  *
6674  * Field Access Macros:
6675  *
6676  */
6677 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field. */
6678 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_LSB 9
6679 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field. */
6680 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_MSB 9
6681 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field. */
6682 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_WIDTH 1
6683 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field value. */
6684 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_SET_MSK 0x00000200
6685 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field value. */
6686 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_CLR_MSK 0xfffffdff
6687 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field. */
6688 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_RESET 0x0
6689 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX field value from a register. */
6690 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6691 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX register field value suitable for setting the register. */
6692 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6693 
6694 /*
6695  * Field : dma
6696  *
6697  * Field Access Macros:
6698  *
6699  */
6700 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field. */
6701 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_LSB 10
6702 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field. */
6703 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_MSB 10
6704 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field. */
6705 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_WIDTH 1
6706 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field value. */
6707 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_SET_MSK 0x00000400
6708 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field value. */
6709 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_CLR_MSK 0xfffffbff
6710 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field. */
6711 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_RESET 0x0
6712 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA field value from a register. */
6713 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_GET(value) (((value) & 0x00000400) >> 10)
6714 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA register field value suitable for setting the register. */
6715 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA_SET(value) (((value) << 10) & 0x00000400)
6716 
6717 /*
6718  * Field : nand_buf
6719  *
6720  * Field Access Macros:
6721  *
6722  */
6723 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field. */
6724 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_LSB 11
6725 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field. */
6726 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_MSB 11
6727 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field. */
6728 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_WIDTH 1
6729 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field value. */
6730 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_SET_MSK 0x00000800
6731 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field value. */
6732 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_CLR_MSK 0xfffff7ff
6733 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field. */
6734 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_RESET 0x0
6735 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF field value from a register. */
6736 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6737 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF register field value suitable for setting the register. */
6738 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6739 
6740 /*
6741  * Field : nand_wr
6742  *
6743  * Field Access Macros:
6744  *
6745  */
6746 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field. */
6747 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_LSB 12
6748 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field. */
6749 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_MSB 12
6750 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field. */
6751 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_WIDTH 1
6752 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field value. */
6753 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_SET_MSK 0x00001000
6754 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field value. */
6755 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_CLR_MSK 0xffffefff
6756 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field. */
6757 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_RESET 0x0
6758 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR field value from a register. */
6759 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6760 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR register field value suitable for setting the register. */
6761 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6762 
6763 /*
6764  * Field : nand_rd
6765  *
6766  * Field Access Macros:
6767  *
6768  */
6769 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field. */
6770 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_LSB 13
6771 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field. */
6772 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_MSB 13
6773 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field. */
6774 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_WIDTH 1
6775 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field value. */
6776 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_SET_MSK 0x00002000
6777 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field value. */
6778 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_CLR_MSK 0xffffdfff
6779 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field. */
6780 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_RESET 0x0
6781 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD field value from a register. */
6782 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6783 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD register field value suitable for setting the register. */
6784 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6785 
6786 /*
6787  * Field : sdmmca
6788  *
6789  * Field Access Macros:
6790  *
6791  */
6792 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field. */
6793 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_LSB 14
6794 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field. */
6795 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_MSB 14
6796 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field. */
6797 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_WIDTH 1
6798 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field value. */
6799 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_SET_MSK 0x00004000
6800 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field value. */
6801 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_CLR_MSK 0xffffbfff
6802 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field. */
6803 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_RESET 0x0
6804 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA field value from a register. */
6805 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
6806 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA register field value suitable for setting the register. */
6807 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
6808 
6809 /*
6810  * Field : sdmmcb
6811  *
6812  * Field Access Macros:
6813  *
6814  */
6815 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field. */
6816 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_LSB 15
6817 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field. */
6818 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_MSB 15
6819 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field. */
6820 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_WIDTH 1
6821 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field value. */
6822 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_SET_MSK 0x00008000
6823 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field value. */
6824 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_CLR_MSK 0xffff7fff
6825 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field. */
6826 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_RESET 0x0
6827 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB field value from a register. */
6828 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
6829 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB register field value suitable for setting the register. */
6830 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
6831 
6832 /*
6833  * Field : ddr0
6834  *
6835  * Field Access Macros:
6836  *
6837  */
6838 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field. */
6839 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_LSB 16
6840 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field. */
6841 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_MSB 16
6842 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field. */
6843 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_WIDTH 1
6844 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field value. */
6845 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_SET_MSK 0x00010000
6846 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field value. */
6847 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_CLR_MSK 0xfffeffff
6848 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field. */
6849 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_RESET 0x0
6850 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 field value from a register. */
6851 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_GET(value) (((value) & 0x00010000) >> 16)
6852 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 register field value suitable for setting the register. */
6853 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0_SET(value) (((value) << 16) & 0x00010000)
6854 
6855 /*
6856  * Field : ddr1
6857  *
6858  * Field Access Macros:
6859  *
6860  */
6861 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field. */
6862 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_LSB 17
6863 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field. */
6864 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_MSB 17
6865 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field. */
6866 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_WIDTH 1
6867 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field value. */
6868 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_SET_MSK 0x00020000
6869 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field value. */
6870 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_CLR_MSK 0xfffdffff
6871 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field. */
6872 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_RESET 0x0
6873 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 field value from a register. */
6874 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_GET(value) (((value) & 0x00020000) >> 17)
6875 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 register field value suitable for setting the register. */
6876 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1_SET(value) (((value) << 17) & 0x00020000)
6877 
6878 #ifndef __ASSEMBLY__
6879 /*
6880  * WARNING: The C register and register group struct declarations are provided for
6881  * convenience and illustrative purposes. They should, however, be used with
6882  * caution as the C language standard provides no guarantees about the alignment or
6883  * atomicity of device memory accesses. The recommended practice for coding device
6884  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6885  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6886  * alt_write_dword() functions for 64 bit registers.
6887  *
6888  * The struct declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_VALUE.
6889  */
6890 struct ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_s
6891 {
6892  uint32_t : 1; /* *UNDEFINED* */
6893  volatile uint32_t ocram : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OCRAM */
6894  volatile uint32_t usb0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB0 */
6895  volatile uint32_t usb1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_USB1 */
6896  volatile uint32_t emac0_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_RX */
6897  volatile uint32_t emac0_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC0_TX */
6898  volatile uint32_t emac1_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_RX */
6899  volatile uint32_t emac1_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC1_TX */
6900  volatile uint32_t emac2_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_RX */
6901  volatile uint32_t emac2_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_EMAC2_TX */
6902  volatile uint32_t dma : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DMA */
6903  volatile uint32_t nand_buf : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_BUF */
6904  volatile uint32_t nand_wr : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_WR */
6905  volatile uint32_t nand_rd : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_NAND_RD */
6906  volatile uint32_t sdmmca : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCA */
6907  volatile uint32_t sdmmcb : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_SDMMCB */
6908  volatile uint32_t ddr0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR0 */
6909  volatile uint32_t ddr1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_DDR1 */
6910  uint32_t : 14; /* *UNDEFINED* */
6911 };
6912 
6913 /* The typedef declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_VALUE. */
6914 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_s ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_t;
6915 #endif /* __ASSEMBLY__ */
6916 
6917 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE register. */
6918 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_RESET 0x00000000
6919 /* The byte offset of the ALT_SYSMGR_CORE_ECC_INTMASK_VALUE register from the beginning of the component. */
6920 #define ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_OFST 0x90
6921 
6922 /*
6923  * Register : ECC interrupt mask Set register - ecc_intmask_set
6924  *
6925  * Write 1 to set a specific modules interrupt mask.
6926  *
6927  * Reads should not return an error, but the actual read value is "Undefined" .
6928  *
6929  * Register Layout
6930  *
6931  * Bits | Access | Reset | Description
6932  * :--------|:-------|:------|:-----------------------------------------
6933  * [0] | ??? | 0x0 | *UNDEFINED*
6934  * [1] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM
6935  * [2] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0
6936  * [3] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1
6937  * [4] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX
6938  * [5] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX
6939  * [6] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX
6940  * [7] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX
6941  * [8] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX
6942  * [9] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX
6943  * [10] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA
6944  * [11] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF
6945  * [12] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR
6946  * [13] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD
6947  * [14] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA
6948  * [15] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB
6949  * [16] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0
6950  * [17] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1
6951  * [31:18] | ??? | 0x0 | *UNDEFINED*
6952  *
6953  */
6954 /*
6955  * Field : ocram
6956  *
6957  * Field Access Macros:
6958  *
6959  */
6960 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field. */
6961 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_LSB 1
6962 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field. */
6963 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_MSB 1
6964 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field. */
6965 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_WIDTH 1
6966 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field value. */
6967 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_SET_MSK 0x00000002
6968 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field value. */
6969 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_CLR_MSK 0xfffffffd
6970 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field. */
6971 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_RESET 0x0
6972 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM field value from a register. */
6973 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6974 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM register field value suitable for setting the register. */
6975 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6976 
6977 /*
6978  * Field : usb0
6979  *
6980  * Field Access Macros:
6981  *
6982  */
6983 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field. */
6984 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_LSB 2
6985 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field. */
6986 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_MSB 2
6987 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field. */
6988 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_WIDTH 1
6989 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field value. */
6990 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_SET_MSK 0x00000004
6991 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field value. */
6992 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_CLR_MSK 0xfffffffb
6993 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field. */
6994 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_RESET 0x0
6995 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 field value from a register. */
6996 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_GET(value) (((value) & 0x00000004) >> 2)
6997 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 register field value suitable for setting the register. */
6998 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0_SET(value) (((value) << 2) & 0x00000004)
6999 
7000 /*
7001  * Field : usb1
7002  *
7003  * Field Access Macros:
7004  *
7005  */
7006 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field. */
7007 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_LSB 3
7008 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field. */
7009 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_MSB 3
7010 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field. */
7011 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_WIDTH 1
7012 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field value. */
7013 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_SET_MSK 0x00000008
7014 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field value. */
7015 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_CLR_MSK 0xfffffff7
7016 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field. */
7017 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_RESET 0x0
7018 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 field value from a register. */
7019 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_GET(value) (((value) & 0x00000008) >> 3)
7020 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 register field value suitable for setting the register. */
7021 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1_SET(value) (((value) << 3) & 0x00000008)
7022 
7023 /*
7024  * Field : emac0_rx
7025  *
7026  * Field Access Macros:
7027  *
7028  */
7029 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field. */
7030 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_LSB 4
7031 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field. */
7032 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_MSB 4
7033 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field. */
7034 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_WIDTH 1
7035 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field value. */
7036 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_SET_MSK 0x00000010
7037 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field value. */
7038 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_CLR_MSK 0xffffffef
7039 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field. */
7040 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_RESET 0x0
7041 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX field value from a register. */
7042 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7043 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX register field value suitable for setting the register. */
7044 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7045 
7046 /*
7047  * Field : emac0_tx
7048  *
7049  * Field Access Macros:
7050  *
7051  */
7052 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field. */
7053 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_LSB 5
7054 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field. */
7055 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_MSB 5
7056 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field. */
7057 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_WIDTH 1
7058 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field value. */
7059 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_SET_MSK 0x00000020
7060 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field value. */
7061 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_CLR_MSK 0xffffffdf
7062 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field. */
7063 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_RESET 0x0
7064 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX field value from a register. */
7065 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7066 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX register field value suitable for setting the register. */
7067 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7068 
7069 /*
7070  * Field : emac1_rx
7071  *
7072  * Field Access Macros:
7073  *
7074  */
7075 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field. */
7076 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_LSB 6
7077 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field. */
7078 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_MSB 6
7079 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field. */
7080 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_WIDTH 1
7081 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field value. */
7082 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_SET_MSK 0x00000040
7083 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field value. */
7084 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_CLR_MSK 0xffffffbf
7085 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field. */
7086 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_RESET 0x0
7087 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX field value from a register. */
7088 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7089 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX register field value suitable for setting the register. */
7090 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7091 
7092 /*
7093  * Field : emac1_tx
7094  *
7095  * Field Access Macros:
7096  *
7097  */
7098 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field. */
7099 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_LSB 7
7100 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field. */
7101 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_MSB 7
7102 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field. */
7103 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_WIDTH 1
7104 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field value. */
7105 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_SET_MSK 0x00000080
7106 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field value. */
7107 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_CLR_MSK 0xffffff7f
7108 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field. */
7109 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_RESET 0x0
7110 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX field value from a register. */
7111 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7112 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX register field value suitable for setting the register. */
7113 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7114 
7115 /*
7116  * Field : emac2_rx
7117  *
7118  * Field Access Macros:
7119  *
7120  */
7121 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field. */
7122 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_LSB 8
7123 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field. */
7124 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_MSB 8
7125 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field. */
7126 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_WIDTH 1
7127 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field value. */
7128 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_SET_MSK 0x00000100
7129 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field value. */
7130 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_CLR_MSK 0xfffffeff
7131 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field. */
7132 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_RESET 0x0
7133 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX field value from a register. */
7134 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7135 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX register field value suitable for setting the register. */
7136 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7137 
7138 /*
7139  * Field : emac2_tx
7140  *
7141  * Field Access Macros:
7142  *
7143  */
7144 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field. */
7145 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_LSB 9
7146 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field. */
7147 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_MSB 9
7148 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field. */
7149 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_WIDTH 1
7150 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field value. */
7151 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_SET_MSK 0x00000200
7152 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field value. */
7153 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_CLR_MSK 0xfffffdff
7154 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field. */
7155 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_RESET 0x0
7156 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX field value from a register. */
7157 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7158 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX register field value suitable for setting the register. */
7159 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7160 
7161 /*
7162  * Field : dma
7163  *
7164  * Field Access Macros:
7165  *
7166  */
7167 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field. */
7168 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_LSB 10
7169 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field. */
7170 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_MSB 10
7171 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field. */
7172 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_WIDTH 1
7173 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field value. */
7174 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_SET_MSK 0x00000400
7175 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field value. */
7176 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_CLR_MSK 0xfffffbff
7177 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field. */
7178 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_RESET 0x0
7179 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA field value from a register. */
7180 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_GET(value) (((value) & 0x00000400) >> 10)
7181 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA register field value suitable for setting the register. */
7182 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA_SET(value) (((value) << 10) & 0x00000400)
7183 
7184 /*
7185  * Field : nand_buf
7186  *
7187  * Field Access Macros:
7188  *
7189  */
7190 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field. */
7191 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_LSB 11
7192 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field. */
7193 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_MSB 11
7194 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field. */
7195 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_WIDTH 1
7196 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field value. */
7197 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_SET_MSK 0x00000800
7198 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field value. */
7199 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_CLR_MSK 0xfffff7ff
7200 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field. */
7201 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_RESET 0x0
7202 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF field value from a register. */
7203 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7204 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF register field value suitable for setting the register. */
7205 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7206 
7207 /*
7208  * Field : nand_wr
7209  *
7210  * Field Access Macros:
7211  *
7212  */
7213 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field. */
7214 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_LSB 12
7215 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field. */
7216 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_MSB 12
7217 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field. */
7218 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_WIDTH 1
7219 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field value. */
7220 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_SET_MSK 0x00001000
7221 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field value. */
7222 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_CLR_MSK 0xffffefff
7223 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field. */
7224 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_RESET 0x0
7225 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR field value from a register. */
7226 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7227 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR register field value suitable for setting the register. */
7228 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7229 
7230 /*
7231  * Field : nand_rd
7232  *
7233  * Field Access Macros:
7234  *
7235  */
7236 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field. */
7237 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_LSB 13
7238 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field. */
7239 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_MSB 13
7240 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field. */
7241 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_WIDTH 1
7242 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field value. */
7243 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_SET_MSK 0x00002000
7244 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field value. */
7245 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_CLR_MSK 0xffffdfff
7246 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field. */
7247 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_RESET 0x0
7248 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD field value from a register. */
7249 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7250 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD register field value suitable for setting the register. */
7251 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7252 
7253 /*
7254  * Field : sdmmca
7255  *
7256  * Field Access Macros:
7257  *
7258  */
7259 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field. */
7260 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_LSB 14
7261 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field. */
7262 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_MSB 14
7263 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field. */
7264 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_WIDTH 1
7265 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field value. */
7266 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_SET_MSK 0x00004000
7267 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field value. */
7268 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_CLR_MSK 0xffffbfff
7269 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field. */
7270 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_RESET 0x0
7271 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA field value from a register. */
7272 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
7273 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA register field value suitable for setting the register. */
7274 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
7275 
7276 /*
7277  * Field : sdmmcb
7278  *
7279  * Field Access Macros:
7280  *
7281  */
7282 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field. */
7283 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_LSB 15
7284 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field. */
7285 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_MSB 15
7286 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field. */
7287 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_WIDTH 1
7288 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field value. */
7289 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_SET_MSK 0x00008000
7290 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field value. */
7291 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_CLR_MSK 0xffff7fff
7292 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field. */
7293 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_RESET 0x0
7294 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB field value from a register. */
7295 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
7296 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB register field value suitable for setting the register. */
7297 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
7298 
7299 /*
7300  * Field : ddr0
7301  *
7302  * Field Access Macros:
7303  *
7304  */
7305 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field. */
7306 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_LSB 16
7307 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field. */
7308 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_MSB 16
7309 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field. */
7310 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_WIDTH 1
7311 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field value. */
7312 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_SET_MSK 0x00010000
7313 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field value. */
7314 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_CLR_MSK 0xfffeffff
7315 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field. */
7316 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_RESET 0x0
7317 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 field value from a register. */
7318 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_GET(value) (((value) & 0x00010000) >> 16)
7319 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 register field value suitable for setting the register. */
7320 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0_SET(value) (((value) << 16) & 0x00010000)
7321 
7322 /*
7323  * Field : ddr1
7324  *
7325  * Field Access Macros:
7326  *
7327  */
7328 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field. */
7329 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_LSB 17
7330 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field. */
7331 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_MSB 17
7332 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field. */
7333 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_WIDTH 1
7334 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field value. */
7335 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_SET_MSK 0x00020000
7336 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field value. */
7337 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_CLR_MSK 0xfffdffff
7338 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field. */
7339 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_RESET 0x0
7340 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 field value from a register. */
7341 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_GET(value) (((value) & 0x00020000) >> 17)
7342 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 register field value suitable for setting the register. */
7343 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1_SET(value) (((value) << 17) & 0x00020000)
7344 
7345 #ifndef __ASSEMBLY__
7346 /*
7347  * WARNING: The C register and register group struct declarations are provided for
7348  * convenience and illustrative purposes. They should, however, be used with
7349  * caution as the C language standard provides no guarantees about the alignment or
7350  * atomicity of device memory accesses. The recommended practice for coding device
7351  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7352  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7353  * alt_write_dword() functions for 64 bit registers.
7354  *
7355  * The struct declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_SET.
7356  */
7357 struct ALT_SYSMGR_CORE_ECC_INTMASK_SET_s
7358 {
7359  uint32_t : 1; /* *UNDEFINED* */
7360  volatile uint32_t ocram : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_OCRAM */
7361  volatile uint32_t usb0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB0 */
7362  volatile uint32_t usb1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_USB1 */
7363  volatile uint32_t emac0_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_RX */
7364  volatile uint32_t emac0_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC0_TX */
7365  volatile uint32_t emac1_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_RX */
7366  volatile uint32_t emac1_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC1_TX */
7367  volatile uint32_t emac2_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_RX */
7368  volatile uint32_t emac2_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_EMAC2_TX */
7369  volatile uint32_t dma : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_DMA */
7370  volatile uint32_t nand_buf : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_BUF */
7371  volatile uint32_t nand_wr : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_WR */
7372  volatile uint32_t nand_rd : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_NAND_RD */
7373  volatile uint32_t sdmmca : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCA */
7374  volatile uint32_t sdmmcb : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_SDMMCB */
7375  volatile uint32_t ddr0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR0 */
7376  volatile uint32_t ddr1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET_DDR1 */
7377  uint32_t : 14; /* *UNDEFINED* */
7378 };
7379 
7380 /* The typedef declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_SET. */
7381 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_SET_s ALT_SYSMGR_CORE_ECC_INTMASK_SET_t;
7382 #endif /* __ASSEMBLY__ */
7383 
7384 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_SET register. */
7385 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_RESET 0x00000000
7386 /* The byte offset of the ALT_SYSMGR_CORE_ECC_INTMASK_SET register from the beginning of the component. */
7387 #define ALT_SYSMGR_CORE_ECC_INTMASK_SET_OFST 0x94
7388 
7389 /*
7390  * Register : ECC interrupt mask Clear register - ecc_intmask_clr
7391  *
7392  * Write 1 to Clear a specific modules interrupt mask.
7393  *
7394  * Reads should not return an error, but the actual read value is "Undefined" .
7395  *
7396  * Register Layout
7397  *
7398  * Bits | Access | Reset | Description
7399  * :--------|:-------|:------|:-----------------------------------------
7400  * [0] | ??? | 0x0 | *UNDEFINED*
7401  * [1] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM
7402  * [2] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0
7403  * [3] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1
7404  * [4] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX
7405  * [5] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX
7406  * [6] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX
7407  * [7] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX
7408  * [8] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX
7409  * [9] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX
7410  * [10] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA
7411  * [11] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF
7412  * [12] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR
7413  * [13] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD
7414  * [14] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA
7415  * [15] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB
7416  * [16] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0
7417  * [17] | W | 0x0 | ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1
7418  * [31:18] | ??? | 0x0 | *UNDEFINED*
7419  *
7420  */
7421 /*
7422  * Field : ocram
7423  *
7424  * Field Access Macros:
7425  *
7426  */
7427 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field. */
7428 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_LSB 1
7429 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field. */
7430 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_MSB 1
7431 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field. */
7432 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_WIDTH 1
7433 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field value. */
7434 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_SET_MSK 0x00000002
7435 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field value. */
7436 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_CLR_MSK 0xfffffffd
7437 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field. */
7438 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_RESET 0x0
7439 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM field value from a register. */
7440 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7441 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM register field value suitable for setting the register. */
7442 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7443 
7444 /*
7445  * Field : usb0
7446  *
7447  * Field Access Macros:
7448  *
7449  */
7450 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field. */
7451 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_LSB 2
7452 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field. */
7453 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_MSB 2
7454 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field. */
7455 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_WIDTH 1
7456 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field value. */
7457 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_SET_MSK 0x00000004
7458 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field value. */
7459 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_CLR_MSK 0xfffffffb
7460 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field. */
7461 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_RESET 0x0
7462 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 field value from a register. */
7463 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7464 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 register field value suitable for setting the register. */
7465 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0_SET(value) (((value) << 2) & 0x00000004)
7466 
7467 /*
7468  * Field : usb1
7469  *
7470  * Field Access Macros:
7471  *
7472  */
7473 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field. */
7474 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_LSB 3
7475 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field. */
7476 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_MSB 3
7477 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field. */
7478 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_WIDTH 1
7479 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field value. */
7480 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_SET_MSK 0x00000008
7481 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field value. */
7482 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_CLR_MSK 0xfffffff7
7483 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field. */
7484 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_RESET 0x0
7485 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 field value from a register. */
7486 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7487 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 register field value suitable for setting the register. */
7488 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1_SET(value) (((value) << 3) & 0x00000008)
7489 
7490 /*
7491  * Field : emac0_rx
7492  *
7493  * Field Access Macros:
7494  *
7495  */
7496 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field. */
7497 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_LSB 4
7498 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field. */
7499 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_MSB 4
7500 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field. */
7501 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_WIDTH 1
7502 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field value. */
7503 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_SET_MSK 0x00000010
7504 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field value. */
7505 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_CLR_MSK 0xffffffef
7506 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field. */
7507 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_RESET 0x0
7508 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX field value from a register. */
7509 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7510 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX register field value suitable for setting the register. */
7511 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7512 
7513 /*
7514  * Field : emac0_tx
7515  *
7516  * Field Access Macros:
7517  *
7518  */
7519 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field. */
7520 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_LSB 5
7521 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field. */
7522 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_MSB 5
7523 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field. */
7524 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_WIDTH 1
7525 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field value. */
7526 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_SET_MSK 0x00000020
7527 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field value. */
7528 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_CLR_MSK 0xffffffdf
7529 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field. */
7530 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_RESET 0x0
7531 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX field value from a register. */
7532 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7533 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX register field value suitable for setting the register. */
7534 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7535 
7536 /*
7537  * Field : emac1_rx
7538  *
7539  * Field Access Macros:
7540  *
7541  */
7542 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field. */
7543 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_LSB 6
7544 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field. */
7545 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_MSB 6
7546 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field. */
7547 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_WIDTH 1
7548 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field value. */
7549 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_SET_MSK 0x00000040
7550 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field value. */
7551 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_CLR_MSK 0xffffffbf
7552 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field. */
7553 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_RESET 0x0
7554 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX field value from a register. */
7555 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7556 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX register field value suitable for setting the register. */
7557 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7558 
7559 /*
7560  * Field : emac1_tx
7561  *
7562  * Field Access Macros:
7563  *
7564  */
7565 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field. */
7566 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_LSB 7
7567 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field. */
7568 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_MSB 7
7569 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field. */
7570 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_WIDTH 1
7571 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field value. */
7572 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_SET_MSK 0x00000080
7573 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field value. */
7574 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_CLR_MSK 0xffffff7f
7575 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field. */
7576 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_RESET 0x0
7577 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX field value from a register. */
7578 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7579 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX register field value suitable for setting the register. */
7580 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7581 
7582 /*
7583  * Field : emac2_rx
7584  *
7585  * Field Access Macros:
7586  *
7587  */
7588 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field. */
7589 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_LSB 8
7590 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field. */
7591 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_MSB 8
7592 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field. */
7593 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_WIDTH 1
7594 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field value. */
7595 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_SET_MSK 0x00000100
7596 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field value. */
7597 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_CLR_MSK 0xfffffeff
7598 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field. */
7599 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_RESET 0x0
7600 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX field value from a register. */
7601 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7602 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX register field value suitable for setting the register. */
7603 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7604 
7605 /*
7606  * Field : emac2_tx
7607  *
7608  * Field Access Macros:
7609  *
7610  */
7611 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field. */
7612 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_LSB 9
7613 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field. */
7614 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_MSB 9
7615 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field. */
7616 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_WIDTH 1
7617 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field value. */
7618 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_SET_MSK 0x00000200
7619 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field value. */
7620 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_CLR_MSK 0xfffffdff
7621 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field. */
7622 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_RESET 0x0
7623 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX field value from a register. */
7624 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7625 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX register field value suitable for setting the register. */
7626 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7627 
7628 /*
7629  * Field : dma
7630  *
7631  * Field Access Macros:
7632  *
7633  */
7634 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field. */
7635 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_LSB 10
7636 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field. */
7637 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_MSB 10
7638 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field. */
7639 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_WIDTH 1
7640 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field value. */
7641 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_SET_MSK 0x00000400
7642 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field value. */
7643 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_CLR_MSK 0xfffffbff
7644 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field. */
7645 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_RESET 0x0
7646 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA field value from a register. */
7647 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7648 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA register field value suitable for setting the register. */
7649 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA_SET(value) (((value) << 10) & 0x00000400)
7650 
7651 /*
7652  * Field : nand_buf
7653  *
7654  * Field Access Macros:
7655  *
7656  */
7657 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field. */
7658 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_LSB 11
7659 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field. */
7660 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_MSB 11
7661 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field. */
7662 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_WIDTH 1
7663 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field value. */
7664 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_SET_MSK 0x00000800
7665 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field value. */
7666 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_CLR_MSK 0xfffff7ff
7667 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field. */
7668 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_RESET 0x0
7669 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF field value from a register. */
7670 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7671 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF register field value suitable for setting the register. */
7672 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7673 
7674 /*
7675  * Field : nand_wr
7676  *
7677  * Field Access Macros:
7678  *
7679  */
7680 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field. */
7681 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_LSB 12
7682 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field. */
7683 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_MSB 12
7684 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field. */
7685 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_WIDTH 1
7686 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field value. */
7687 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_SET_MSK 0x00001000
7688 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field value. */
7689 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_CLR_MSK 0xffffefff
7690 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field. */
7691 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_RESET 0x0
7692 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR field value from a register. */
7693 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7694 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR register field value suitable for setting the register. */
7695 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7696 
7697 /*
7698  * Field : nand_rd
7699  *
7700  * Field Access Macros:
7701  *
7702  */
7703 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field. */
7704 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_LSB 13
7705 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field. */
7706 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_MSB 13
7707 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field. */
7708 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_WIDTH 1
7709 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field value. */
7710 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_SET_MSK 0x00002000
7711 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field value. */
7712 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_CLR_MSK 0xffffdfff
7713 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field. */
7714 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_RESET 0x0
7715 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD field value from a register. */
7716 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7717 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD register field value suitable for setting the register. */
7718 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7719 
7720 /*
7721  * Field : sdmmca
7722  *
7723  * Field Access Macros:
7724  *
7725  */
7726 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field. */
7727 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_LSB 14
7728 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field. */
7729 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_MSB 14
7730 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field. */
7731 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_WIDTH 1
7732 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field value. */
7733 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_SET_MSK 0x00004000
7734 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field value. */
7735 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_CLR_MSK 0xffffbfff
7736 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field. */
7737 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_RESET 0x0
7738 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA field value from a register. */
7739 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
7740 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA register field value suitable for setting the register. */
7741 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
7742 
7743 /*
7744  * Field : sdmmcb
7745  *
7746  * Field Access Macros:
7747  *
7748  */
7749 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field. */
7750 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_LSB 15
7751 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field. */
7752 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_MSB 15
7753 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field. */
7754 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_WIDTH 1
7755 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field value. */
7756 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_SET_MSK 0x00008000
7757 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field value. */
7758 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_CLR_MSK 0xffff7fff
7759 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field. */
7760 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_RESET 0x0
7761 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB field value from a register. */
7762 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
7763 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB register field value suitable for setting the register. */
7764 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
7765 
7766 /*
7767  * Field : ddr0
7768  *
7769  * Field Access Macros:
7770  *
7771  */
7772 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field. */
7773 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_LSB 16
7774 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field. */
7775 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_MSB 16
7776 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field. */
7777 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_WIDTH 1
7778 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field value. */
7779 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_SET_MSK 0x00010000
7780 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field value. */
7781 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_CLR_MSK 0xfffeffff
7782 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field. */
7783 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_RESET 0x0
7784 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 field value from a register. */
7785 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
7786 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 register field value suitable for setting the register. */
7787 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0_SET(value) (((value) << 16) & 0x00010000)
7788 
7789 /*
7790  * Field : ddr1
7791  *
7792  * Field Access Macros:
7793  *
7794  */
7795 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field. */
7796 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_LSB 17
7797 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field. */
7798 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_MSB 17
7799 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field. */
7800 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_WIDTH 1
7801 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field value. */
7802 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_SET_MSK 0x00020000
7803 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field value. */
7804 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_CLR_MSK 0xfffdffff
7805 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field. */
7806 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_RESET 0x0
7807 /* Extracts the ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 field value from a register. */
7808 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
7809 /* Produces a ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 register field value suitable for setting the register. */
7810 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1_SET(value) (((value) << 17) & 0x00020000)
7811 
7812 #ifndef __ASSEMBLY__
7813 /*
7814  * WARNING: The C register and register group struct declarations are provided for
7815  * convenience and illustrative purposes. They should, however, be used with
7816  * caution as the C language standard provides no guarantees about the alignment or
7817  * atomicity of device memory accesses. The recommended practice for coding device
7818  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7819  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7820  * alt_write_dword() functions for 64 bit registers.
7821  *
7822  * The struct declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_CLR.
7823  */
7824 struct ALT_SYSMGR_CORE_ECC_INTMASK_CLR_s
7825 {
7826  uint32_t : 1; /* *UNDEFINED* */
7827  volatile uint32_t ocram : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OCRAM */
7828  volatile uint32_t usb0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB0 */
7829  volatile uint32_t usb1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_USB1 */
7830  volatile uint32_t emac0_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_RX */
7831  volatile uint32_t emac0_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC0_TX */
7832  volatile uint32_t emac1_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_RX */
7833  volatile uint32_t emac1_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC1_TX */
7834  volatile uint32_t emac2_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_RX */
7835  volatile uint32_t emac2_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_EMAC2_TX */
7836  volatile uint32_t dma : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DMA */
7837  volatile uint32_t nand_buf : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_BUF */
7838  volatile uint32_t nand_wr : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_WR */
7839  volatile uint32_t nand_rd : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_NAND_RD */
7840  volatile uint32_t sdmmca : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCA */
7841  volatile uint32_t sdmmcb : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_SDMMCB */
7842  volatile uint32_t ddr0 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR0 */
7843  volatile uint32_t ddr1 : 1; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR_DDR1 */
7844  uint32_t : 14; /* *UNDEFINED* */
7845 };
7846 
7847 /* The typedef declaration for register ALT_SYSMGR_CORE_ECC_INTMASK_CLR. */
7848 typedef struct ALT_SYSMGR_CORE_ECC_INTMASK_CLR_s ALT_SYSMGR_CORE_ECC_INTMASK_CLR_t;
7849 #endif /* __ASSEMBLY__ */
7850 
7851 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR register. */
7852 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_RESET 0x00000000
7853 /* The byte offset of the ALT_SYSMGR_CORE_ECC_INTMASK_CLR register from the beginning of the component. */
7854 #define ALT_SYSMGR_CORE_ECC_INTMASK_CLR_OFST 0x98
7855 
7856 /*
7857  * Register : ecc_intstatus_serr
7858  *
7859  * ECC single bit error status of individual modules.
7860  *
7861  * A write to this register should return an error.
7862  *
7863  * Register Layout
7864  *
7865  * Bits | Access | Reset | Description
7866  * :--------|:-------|:------|:--------------------------------------------
7867  * [0] | ??? | 0x0 | *UNDEFINED*
7868  * [1] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM
7869  * [2] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0
7870  * [3] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1
7871  * [4] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX
7872  * [5] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX
7873  * [6] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX
7874  * [7] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX
7875  * [8] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX
7876  * [9] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX
7877  * [10] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA
7878  * [11] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF
7879  * [12] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR
7880  * [13] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD
7881  * [14] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA
7882  * [15] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB
7883  * [16] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0
7884  * [17] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1
7885  * [31:18] | ??? | 0x0 | *UNDEFINED*
7886  *
7887  */
7888 /*
7889  * Field : ocram
7890  *
7891  * Field Access Macros:
7892  *
7893  */
7894 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field. */
7895 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_LSB 1
7896 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field. */
7897 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_MSB 1
7898 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field. */
7899 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_WIDTH 1
7900 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field value. */
7901 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_SET_MSK 0x00000002
7902 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field value. */
7903 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_CLR_MSK 0xfffffffd
7904 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field. */
7905 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_RESET 0x0
7906 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM field value from a register. */
7907 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7908 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM register field value suitable for setting the register. */
7909 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7910 
7911 /*
7912  * Field : usb0
7913  *
7914  * Field Access Macros:
7915  *
7916  */
7917 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field. */
7918 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_LSB 2
7919 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field. */
7920 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_MSB 2
7921 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field. */
7922 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_WIDTH 1
7923 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field value. */
7924 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_SET_MSK 0x00000004
7925 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field value. */
7926 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_CLR_MSK 0xfffffffb
7927 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field. */
7928 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_RESET 0x0
7929 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 field value from a register. */
7930 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7931 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 register field value suitable for setting the register. */
7932 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7933 
7934 /*
7935  * Field : usb1
7936  *
7937  * Field Access Macros:
7938  *
7939  */
7940 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field. */
7941 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_LSB 3
7942 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field. */
7943 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_MSB 3
7944 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field. */
7945 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_WIDTH 1
7946 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field value. */
7947 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_SET_MSK 0x00000008
7948 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field value. */
7949 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_CLR_MSK 0xfffffff7
7950 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field. */
7951 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_RESET 0x0
7952 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 field value from a register. */
7953 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7954 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 register field value suitable for setting the register. */
7955 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7956 
7957 /*
7958  * Field : emac0_rx
7959  *
7960  * Field Access Macros:
7961  *
7962  */
7963 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field. */
7964 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_LSB 4
7965 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field. */
7966 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_MSB 4
7967 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field. */
7968 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_WIDTH 1
7969 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field value. */
7970 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_SET_MSK 0x00000010
7971 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field value. */
7972 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_CLR_MSK 0xffffffef
7973 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field. */
7974 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_RESET 0x0
7975 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX field value from a register. */
7976 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7977 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX register field value suitable for setting the register. */
7978 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7979 
7980 /*
7981  * Field : emac0_tx
7982  *
7983  * Field Access Macros:
7984  *
7985  */
7986 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field. */
7987 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_LSB 5
7988 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field. */
7989 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_MSB 5
7990 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field. */
7991 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_WIDTH 1
7992 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field value. */
7993 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_SET_MSK 0x00000020
7994 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field value. */
7995 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_CLR_MSK 0xffffffdf
7996 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field. */
7997 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_RESET 0x0
7998 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX field value from a register. */
7999 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8000 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX register field value suitable for setting the register. */
8001 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8002 
8003 /*
8004  * Field : emac1_rx
8005  *
8006  * Field Access Macros:
8007  *
8008  */
8009 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field. */
8010 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_LSB 6
8011 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field. */
8012 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_MSB 6
8013 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field. */
8014 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_WIDTH 1
8015 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field value. */
8016 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_SET_MSK 0x00000040
8017 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field value. */
8018 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_CLR_MSK 0xffffffbf
8019 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field. */
8020 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_RESET 0x0
8021 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX field value from a register. */
8022 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8023 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX register field value suitable for setting the register. */
8024 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8025 
8026 /*
8027  * Field : emac1_tx
8028  *
8029  * Field Access Macros:
8030  *
8031  */
8032 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field. */
8033 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_LSB 7
8034 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field. */
8035 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_MSB 7
8036 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field. */
8037 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_WIDTH 1
8038 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field value. */
8039 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_SET_MSK 0x00000080
8040 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field value. */
8041 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_CLR_MSK 0xffffff7f
8042 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field. */
8043 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_RESET 0x0
8044 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX field value from a register. */
8045 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8046 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX register field value suitable for setting the register. */
8047 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8048 
8049 /*
8050  * Field : emac2_rx
8051  *
8052  * Field Access Macros:
8053  *
8054  */
8055 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field. */
8056 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_LSB 8
8057 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field. */
8058 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_MSB 8
8059 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field. */
8060 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_WIDTH 1
8061 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field value. */
8062 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_SET_MSK 0x00000100
8063 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field value. */
8064 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_CLR_MSK 0xfffffeff
8065 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field. */
8066 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_RESET 0x0
8067 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX field value from a register. */
8068 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8069 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX register field value suitable for setting the register. */
8070 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8071 
8072 /*
8073  * Field : emac2_tx
8074  *
8075  * Field Access Macros:
8076  *
8077  */
8078 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field. */
8079 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_LSB 9
8080 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field. */
8081 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_MSB 9
8082 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field. */
8083 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_WIDTH 1
8084 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field value. */
8085 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_SET_MSK 0x00000200
8086 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field value. */
8087 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_CLR_MSK 0xfffffdff
8088 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field. */
8089 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_RESET 0x0
8090 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX field value from a register. */
8091 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8092 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX register field value suitable for setting the register. */
8093 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8094 
8095 /*
8096  * Field : dma
8097  *
8098  * Field Access Macros:
8099  *
8100  */
8101 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field. */
8102 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_LSB 10
8103 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field. */
8104 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_MSB 10
8105 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field. */
8106 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_WIDTH 1
8107 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field value. */
8108 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_SET_MSK 0x00000400
8109 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field value. */
8110 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_CLR_MSK 0xfffffbff
8111 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field. */
8112 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_RESET 0x0
8113 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA field value from a register. */
8114 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8115 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA register field value suitable for setting the register. */
8116 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8117 
8118 /*
8119  * Field : nand_buf
8120  *
8121  * Field Access Macros:
8122  *
8123  */
8124 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field. */
8125 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_LSB 11
8126 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field. */
8127 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_MSB 11
8128 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field. */
8129 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_WIDTH 1
8130 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field value. */
8131 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_SET_MSK 0x00000800
8132 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field value. */
8133 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_CLR_MSK 0xfffff7ff
8134 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field. */
8135 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_RESET 0x0
8136 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF field value from a register. */
8137 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8138 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF register field value suitable for setting the register. */
8139 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8140 
8141 /*
8142  * Field : nand_wr
8143  *
8144  * Field Access Macros:
8145  *
8146  */
8147 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field. */
8148 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_LSB 12
8149 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field. */
8150 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_MSB 12
8151 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field. */
8152 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_WIDTH 1
8153 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field value. */
8154 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_SET_MSK 0x00001000
8155 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field value. */
8156 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_CLR_MSK 0xffffefff
8157 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field. */
8158 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_RESET 0x0
8159 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR field value from a register. */
8160 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8161 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR register field value suitable for setting the register. */
8162 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8163 
8164 /*
8165  * Field : nand_rd
8166  *
8167  * Field Access Macros:
8168  *
8169  */
8170 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field. */
8171 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_LSB 13
8172 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field. */
8173 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_MSB 13
8174 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field. */
8175 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_WIDTH 1
8176 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field value. */
8177 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_SET_MSK 0x00002000
8178 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field value. */
8179 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_CLR_MSK 0xffffdfff
8180 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field. */
8181 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_RESET 0x0
8182 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD field value from a register. */
8183 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8184 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD register field value suitable for setting the register. */
8185 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8186 
8187 /*
8188  * Field : sdmmca
8189  *
8190  * Field Access Macros:
8191  *
8192  */
8193 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field. */
8194 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_LSB 14
8195 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field. */
8196 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_MSB 14
8197 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field. */
8198 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_WIDTH 1
8199 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field value. */
8200 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_SET_MSK 0x00004000
8201 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field value. */
8202 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_CLR_MSK 0xffffbfff
8203 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field. */
8204 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_RESET 0x0
8205 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA field value from a register. */
8206 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
8207 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA register field value suitable for setting the register. */
8208 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
8209 
8210 /*
8211  * Field : sdmmcb
8212  *
8213  * Field Access Macros:
8214  *
8215  */
8216 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field. */
8217 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_LSB 15
8218 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field. */
8219 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_MSB 15
8220 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field. */
8221 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_WIDTH 1
8222 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field value. */
8223 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_SET_MSK 0x00008000
8224 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field value. */
8225 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_CLR_MSK 0xffff7fff
8226 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field. */
8227 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_RESET 0x0
8228 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB field value from a register. */
8229 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
8230 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB register field value suitable for setting the register. */
8231 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
8232 
8233 /*
8234  * Field : ddr0
8235  *
8236  * Field Access Macros:
8237  *
8238  */
8239 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field. */
8240 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_LSB 16
8241 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field. */
8242 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_MSB 16
8243 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field. */
8244 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_WIDTH 1
8245 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field value. */
8246 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_SET_MSK 0x00010000
8247 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field value. */
8248 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_CLR_MSK 0xfffeffff
8249 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field. */
8250 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_RESET 0x0
8251 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 field value from a register. */
8252 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
8253 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 register field value suitable for setting the register. */
8254 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0_SET(value) (((value) << 16) & 0x00010000)
8255 
8256 /*
8257  * Field : ddr1
8258  *
8259  * Field Access Macros:
8260  *
8261  */
8262 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field. */
8263 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_LSB 17
8264 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field. */
8265 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_MSB 17
8266 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field. */
8267 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_WIDTH 1
8268 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field value. */
8269 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_SET_MSK 0x00020000
8270 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field value. */
8271 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_CLR_MSK 0xfffdffff
8272 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field. */
8273 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_RESET 0x0
8274 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 field value from a register. */
8275 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
8276 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 register field value suitable for setting the register. */
8277 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1_SET(value) (((value) << 17) & 0x00020000)
8278 
8279 #ifndef __ASSEMBLY__
8280 /*
8281  * WARNING: The C register and register group struct declarations are provided for
8282  * convenience and illustrative purposes. They should, however, be used with
8283  * caution as the C language standard provides no guarantees about the alignment or
8284  * atomicity of device memory accesses. The recommended practice for coding device
8285  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8286  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8287  * alt_write_dword() functions for 64 bit registers.
8288  *
8289  * The struct declaration for register ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR.
8290  */
8291 struct ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_s
8292 {
8293  uint32_t : 1; /* *UNDEFINED* */
8294  const volatile uint32_t ocram : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OCRAM */
8295  const volatile uint32_t usb0 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB0 */
8296  const volatile uint32_t usb1 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_USB1 */
8297  const volatile uint32_t emac0_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_RX */
8298  const volatile uint32_t emac0_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC0_TX */
8299  const volatile uint32_t emac1_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_RX */
8300  const volatile uint32_t emac1_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC1_TX */
8301  const volatile uint32_t emac2_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_RX */
8302  const volatile uint32_t emac2_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_EMAC2_TX */
8303  const volatile uint32_t dma : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DMA */
8304  const volatile uint32_t nand_buf : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_BUF */
8305  const volatile uint32_t nand_wr : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_WR */
8306  const volatile uint32_t nand_rd : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_NAND_RD */
8307  const volatile uint32_t sdmmca : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCA */
8308  const volatile uint32_t sdmmcb : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_SDMMCB */
8309  const volatile uint32_t ddr0 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR0 */
8310  const volatile uint32_t ddr1 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_DDR1 */
8311  uint32_t : 14; /* *UNDEFINED* */
8312 };
8313 
8314 /* The typedef declaration for register ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR. */
8315 typedef struct ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_s ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_t;
8316 #endif /* __ASSEMBLY__ */
8317 
8318 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR register. */
8319 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_RESET 0x00000000
8320 /* The byte offset of the ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR register from the beginning of the component. */
8321 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_OFST 0x9c
8322 
8323 /*
8324  * Register : ecc_intstatus_derr
8325  *
8326  * ECC double bit error status of individual modules.
8327  *
8328  * A write to this register should return an error.
8329  *
8330  * Register Layout
8331  *
8332  * Bits | Access | Reset | Description
8333  * :--------|:-------|:------|:--------------------------------------------
8334  * [0] | ??? | 0x0 | *UNDEFINED*
8335  * [1] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM
8336  * [2] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0
8337  * [3] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1
8338  * [4] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX
8339  * [5] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX
8340  * [6] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX
8341  * [7] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX
8342  * [8] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX
8343  * [9] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX
8344  * [10] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA
8345  * [11] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF
8346  * [12] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR
8347  * [13] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD
8348  * [14] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA
8349  * [15] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB
8350  * [16] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0
8351  * [17] | R | 0x0 | ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1
8352  * [31:18] | ??? | 0x0 | *UNDEFINED*
8353  *
8354  */
8355 /*
8356  * Field : ocram
8357  *
8358  * Field Access Macros:
8359  *
8360  */
8361 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field. */
8362 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_LSB 1
8363 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field. */
8364 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_MSB 1
8365 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field. */
8366 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_WIDTH 1
8367 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field value. */
8368 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_SET_MSK 0x00000002
8369 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field value. */
8370 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_CLR_MSK 0xfffffffd
8371 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field. */
8372 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_RESET 0x0
8373 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM field value from a register. */
8374 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
8375 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM register field value suitable for setting the register. */
8376 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
8377 
8378 /*
8379  * Field : usb0
8380  *
8381  * Field Access Macros:
8382  *
8383  */
8384 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field. */
8385 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_LSB 2
8386 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field. */
8387 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_MSB 2
8388 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field. */
8389 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_WIDTH 1
8390 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field value. */
8391 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_SET_MSK 0x00000004
8392 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field value. */
8393 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_CLR_MSK 0xfffffffb
8394 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field. */
8395 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_RESET 0x0
8396 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 field value from a register. */
8397 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
8398 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 register field value suitable for setting the register. */
8399 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0_SET(value) (((value) << 2) & 0x00000004)
8400 
8401 /*
8402  * Field : usb1
8403  *
8404  * Field Access Macros:
8405  *
8406  */
8407 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field. */
8408 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_LSB 3
8409 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field. */
8410 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_MSB 3
8411 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field. */
8412 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_WIDTH 1
8413 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field value. */
8414 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_SET_MSK 0x00000008
8415 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field value. */
8416 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_CLR_MSK 0xfffffff7
8417 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field. */
8418 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_RESET 0x0
8419 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 field value from a register. */
8420 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
8421 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 register field value suitable for setting the register. */
8422 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1_SET(value) (((value) << 3) & 0x00000008)
8423 
8424 /*
8425  * Field : emac0_rx
8426  *
8427  * Field Access Macros:
8428  *
8429  */
8430 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field. */
8431 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_LSB 4
8432 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field. */
8433 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_MSB 4
8434 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field. */
8435 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_WIDTH 1
8436 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field value. */
8437 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_SET_MSK 0x00000010
8438 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field value. */
8439 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_CLR_MSK 0xffffffef
8440 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field. */
8441 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_RESET 0x0
8442 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX field value from a register. */
8443 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
8444 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX register field value suitable for setting the register. */
8445 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
8446 
8447 /*
8448  * Field : emac0_tx
8449  *
8450  * Field Access Macros:
8451  *
8452  */
8453 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field. */
8454 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_LSB 5
8455 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field. */
8456 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_MSB 5
8457 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field. */
8458 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_WIDTH 1
8459 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field value. */
8460 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_SET_MSK 0x00000020
8461 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field value. */
8462 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_CLR_MSK 0xffffffdf
8463 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field. */
8464 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_RESET 0x0
8465 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX field value from a register. */
8466 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8467 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX register field value suitable for setting the register. */
8468 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8469 
8470 /*
8471  * Field : emac1_rx
8472  *
8473  * Field Access Macros:
8474  *
8475  */
8476 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field. */
8477 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_LSB 6
8478 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field. */
8479 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_MSB 6
8480 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field. */
8481 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_WIDTH 1
8482 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field value. */
8483 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_SET_MSK 0x00000040
8484 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field value. */
8485 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_CLR_MSK 0xffffffbf
8486 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field. */
8487 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_RESET 0x0
8488 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX field value from a register. */
8489 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8490 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX register field value suitable for setting the register. */
8491 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8492 
8493 /*
8494  * Field : emac1_tx
8495  *
8496  * Field Access Macros:
8497  *
8498  */
8499 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field. */
8500 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_LSB 7
8501 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field. */
8502 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_MSB 7
8503 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field. */
8504 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_WIDTH 1
8505 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field value. */
8506 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_SET_MSK 0x00000080
8507 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field value. */
8508 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_CLR_MSK 0xffffff7f
8509 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field. */
8510 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_RESET 0x0
8511 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX field value from a register. */
8512 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8513 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX register field value suitable for setting the register. */
8514 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8515 
8516 /*
8517  * Field : emac2_rx
8518  *
8519  * Field Access Macros:
8520  *
8521  */
8522 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field. */
8523 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_LSB 8
8524 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field. */
8525 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_MSB 8
8526 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field. */
8527 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_WIDTH 1
8528 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field value. */
8529 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_SET_MSK 0x00000100
8530 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field value. */
8531 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_CLR_MSK 0xfffffeff
8532 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field. */
8533 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_RESET 0x0
8534 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX field value from a register. */
8535 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8536 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX register field value suitable for setting the register. */
8537 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8538 
8539 /*
8540  * Field : emac2_tx
8541  *
8542  * Field Access Macros:
8543  *
8544  */
8545 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field. */
8546 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_LSB 9
8547 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field. */
8548 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_MSB 9
8549 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field. */
8550 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_WIDTH 1
8551 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field value. */
8552 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_SET_MSK 0x00000200
8553 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field value. */
8554 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_CLR_MSK 0xfffffdff
8555 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field. */
8556 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_RESET 0x0
8557 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX field value from a register. */
8558 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8559 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX register field value suitable for setting the register. */
8560 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8561 
8562 /*
8563  * Field : dma
8564  *
8565  * Field Access Macros:
8566  *
8567  */
8568 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field. */
8569 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_LSB 10
8570 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field. */
8571 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_MSB 10
8572 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field. */
8573 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_WIDTH 1
8574 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field value. */
8575 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_SET_MSK 0x00000400
8576 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field value. */
8577 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_CLR_MSK 0xfffffbff
8578 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field. */
8579 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_RESET 0x0
8580 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA field value from a register. */
8581 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8582 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA register field value suitable for setting the register. */
8583 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8584 
8585 /*
8586  * Field : nand_buf
8587  *
8588  * Field Access Macros:
8589  *
8590  */
8591 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field. */
8592 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_LSB 11
8593 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field. */
8594 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_MSB 11
8595 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field. */
8596 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_WIDTH 1
8597 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field value. */
8598 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_SET_MSK 0x00000800
8599 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field value. */
8600 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_CLR_MSK 0xfffff7ff
8601 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field. */
8602 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_RESET 0x0
8603 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF field value from a register. */
8604 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8605 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF register field value suitable for setting the register. */
8606 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8607 
8608 /*
8609  * Field : nand_wr
8610  *
8611  * Field Access Macros:
8612  *
8613  */
8614 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field. */
8615 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_LSB 12
8616 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field. */
8617 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_MSB 12
8618 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field. */
8619 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_WIDTH 1
8620 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field value. */
8621 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_SET_MSK 0x00001000
8622 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field value. */
8623 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_CLR_MSK 0xffffefff
8624 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field. */
8625 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_RESET 0x0
8626 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR field value from a register. */
8627 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8628 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR register field value suitable for setting the register. */
8629 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8630 
8631 /*
8632  * Field : nand_rd
8633  *
8634  * Field Access Macros:
8635  *
8636  */
8637 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field. */
8638 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_LSB 13
8639 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field. */
8640 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_MSB 13
8641 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field. */
8642 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_WIDTH 1
8643 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field value. */
8644 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_SET_MSK 0x00002000
8645 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field value. */
8646 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_CLR_MSK 0xffffdfff
8647 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field. */
8648 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_RESET 0x0
8649 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD field value from a register. */
8650 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8651 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD register field value suitable for setting the register. */
8652 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8653 
8654 /*
8655  * Field : sdmmca
8656  *
8657  * Field Access Macros:
8658  *
8659  */
8660 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field. */
8661 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_LSB 14
8662 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field. */
8663 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_MSB 14
8664 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field. */
8665 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_WIDTH 1
8666 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field value. */
8667 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_SET_MSK 0x00004000
8668 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field value. */
8669 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_CLR_MSK 0xffffbfff
8670 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field. */
8671 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_RESET 0x0
8672 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA field value from a register. */
8673 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_GET(value) (((value) & 0x00004000) >> 14)
8674 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA register field value suitable for setting the register. */
8675 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA_SET(value) (((value) << 14) & 0x00004000)
8676 
8677 /*
8678  * Field : sdmmcb
8679  *
8680  * Field Access Macros:
8681  *
8682  */
8683 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field. */
8684 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_LSB 15
8685 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field. */
8686 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_MSB 15
8687 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field. */
8688 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_WIDTH 1
8689 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field value. */
8690 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_SET_MSK 0x00008000
8691 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field value. */
8692 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_CLR_MSK 0xffff7fff
8693 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field. */
8694 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_RESET 0x0
8695 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB field value from a register. */
8696 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_GET(value) (((value) & 0x00008000) >> 15)
8697 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB register field value suitable for setting the register. */
8698 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB_SET(value) (((value) << 15) & 0x00008000)
8699 
8700 /*
8701  * Field : ddr0
8702  *
8703  * Field Access Macros:
8704  *
8705  */
8706 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field. */
8707 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_LSB 16
8708 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field. */
8709 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_MSB 16
8710 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field. */
8711 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_WIDTH 1
8712 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field value. */
8713 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_SET_MSK 0x00010000
8714 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field value. */
8715 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_CLR_MSK 0xfffeffff
8716 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field. */
8717 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_RESET 0x0
8718 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 field value from a register. */
8719 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_GET(value) (((value) & 0x00010000) >> 16)
8720 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 register field value suitable for setting the register. */
8721 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0_SET(value) (((value) << 16) & 0x00010000)
8722 
8723 /*
8724  * Field : ddr1
8725  *
8726  * Field Access Macros:
8727  *
8728  */
8729 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field. */
8730 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_LSB 17
8731 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field. */
8732 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_MSB 17
8733 /* The width in bits of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field. */
8734 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_WIDTH 1
8735 /* The mask used to set the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field value. */
8736 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_SET_MSK 0x00020000
8737 /* The mask used to clear the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field value. */
8738 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_CLR_MSK 0xfffdffff
8739 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field. */
8740 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_RESET 0x0
8741 /* Extracts the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 field value from a register. */
8742 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_GET(value) (((value) & 0x00020000) >> 17)
8743 /* Produces a ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 register field value suitable for setting the register. */
8744 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1_SET(value) (((value) << 17) & 0x00020000)
8745 
8746 #ifndef __ASSEMBLY__
8747 /*
8748  * WARNING: The C register and register group struct declarations are provided for
8749  * convenience and illustrative purposes. They should, however, be used with
8750  * caution as the C language standard provides no guarantees about the alignment or
8751  * atomicity of device memory accesses. The recommended practice for coding device
8752  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8753  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8754  * alt_write_dword() functions for 64 bit registers.
8755  *
8756  * The struct declaration for register ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR.
8757  */
8758 struct ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_s
8759 {
8760  uint32_t : 1; /* *UNDEFINED* */
8761  const volatile uint32_t ocram : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OCRAM */
8762  const volatile uint32_t usb0 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB0 */
8763  const volatile uint32_t usb1 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_USB1 */
8764  const volatile uint32_t emac0_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_RX */
8765  const volatile uint32_t emac0_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC0_TX */
8766  const volatile uint32_t emac1_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_RX */
8767  const volatile uint32_t emac1_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC1_TX */
8768  const volatile uint32_t emac2_rx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_RX */
8769  const volatile uint32_t emac2_tx : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_EMAC2_TX */
8770  const volatile uint32_t dma : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DMA */
8771  const volatile uint32_t nand_buf : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_BUF */
8772  const volatile uint32_t nand_wr : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_WR */
8773  const volatile uint32_t nand_rd : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_NAND_RD */
8774  const volatile uint32_t sdmmca : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCA */
8775  const volatile uint32_t sdmmcb : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_SDMMCB */
8776  const volatile uint32_t ddr0 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR0 */
8777  const volatile uint32_t ddr1 : 1; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_DDR1 */
8778  uint32_t : 14; /* *UNDEFINED* */
8779 };
8780 
8781 /* The typedef declaration for register ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR. */
8782 typedef struct ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_s ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_t;
8783 #endif /* __ASSEMBLY__ */
8784 
8785 /* The reset value of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR register. */
8786 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_RESET 0x00000000
8787 /* The byte offset of the ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR register from the beginning of the component. */
8788 #define ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_OFST 0xa0
8789 
8790 /*
8791  * Register : noc_addr_remap
8792  *
8793  * The noc_addr_repmap register to view the HPS memory map (specifically on-chip
8794  * RAM)
8795  *
8796  * Register Layout
8797  *
8798  * Bits | Access | Reset | Description
8799  * :-------|:-------|:------|:------------------------------------------
8800  * [0] | RW | 0x0 | ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE
8801  * [31:1] | ??? | 0x0 | *UNDEFINED*
8802  *
8803  */
8804 /*
8805  * Field : sdm2hps_be
8806  *
8807  * 0: lowest 1 MB of SDM2HPS_BE memory view decodes to on-chip RAM. The rest is
8808  * DRAM.
8809  *
8810  * 1: lowest 1 MB of SDM2HPS_BE memory view decodes to DRAM
8811  *
8812  * Field Access Macros:
8813  *
8814  */
8815 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field. */
8816 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_LSB 0
8817 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field. */
8818 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_MSB 0
8819 /* The width in bits of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field. */
8820 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_WIDTH 1
8821 /* The mask used to set the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field value. */
8822 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_SET_MSK 0x00000001
8823 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field value. */
8824 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_CLR_MSK 0xfffffffe
8825 /* The reset value of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field. */
8826 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_RESET 0x0
8827 /* Extracts the ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE field value from a register. */
8828 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_GET(value) (((value) & 0x00000001) >> 0)
8829 /* Produces a ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE register field value suitable for setting the register. */
8830 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE_SET(value) (((value) << 0) & 0x00000001)
8831 
8832 #ifndef __ASSEMBLY__
8833 /*
8834  * WARNING: The C register and register group struct declarations are provided for
8835  * convenience and illustrative purposes. They should, however, be used with
8836  * caution as the C language standard provides no guarantees about the alignment or
8837  * atomicity of device memory accesses. The recommended practice for coding device
8838  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8839  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8840  * alt_write_dword() functions for 64 bit registers.
8841  *
8842  * The struct declaration for register ALT_SYSMGR_CORE_NOC_ADDR_REMAP.
8843  */
8844 struct ALT_SYSMGR_CORE_NOC_ADDR_REMAP_s
8845 {
8846  volatile uint32_t sdm2hps_be : 1; /* ALT_SYSMGR_CORE_NOC_ADDR_REMAP_SDM2HPS_BE */
8847  uint32_t : 31; /* *UNDEFINED* */
8848 };
8849 
8850 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_ADDR_REMAP. */
8851 typedef struct ALT_SYSMGR_CORE_NOC_ADDR_REMAP_s ALT_SYSMGR_CORE_NOC_ADDR_REMAP_t;
8852 #endif /* __ASSEMBLY__ */
8853 
8854 /* The reset value of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP register. */
8855 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_RESET 0x00000000
8856 /* The byte offset of the ALT_SYSMGR_CORE_NOC_ADDR_REMAP register from the beginning of the component. */
8857 #define ALT_SYSMGR_CORE_NOC_ADDR_REMAP_OFST 0xb0
8858 
8859 /*
8860  * Register : hmc_clk
8861  *
8862  * HMC Clock and IO Lock status indicator
8863  *
8864  * Register Layout
8865  *
8866  * Bits | Access | Reset | Description
8867  * :--------|:-------|:--------|:--------------------------------------
8868  * [0] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_STATUS
8869  * [7:1] | ??? | Unknown | *UNDEFINED*
8870  * [8] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A
8871  * [9] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B
8872  * [10] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C
8873  * [15:11] | ??? | Unknown | *UNDEFINED*
8874  * [16] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A
8875  * [17] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B
8876  * [18] | R | Unknown | ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C
8877  * [31:19] | ??? | Unknown | *UNDEFINED*
8878  *
8879  */
8880 /*
8881  * Field : status
8882  *
8883  * HMC clock status: HMC clock not running = 0; HMC clock running = 1.
8884  *
8885  * Field Access Macros:
8886  *
8887  */
8888 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field. */
8889 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_LSB 0
8890 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field. */
8891 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_MSB 0
8892 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field. */
8893 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_WIDTH 1
8894 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field value. */
8895 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_SET_MSK 0x00000001
8896 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field value. */
8897 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_CLR_MSK 0xfffffffe
8898 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_STATUS register field is UNKNOWN. */
8899 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_RESET 0x0
8900 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_STATUS field value from a register. */
8901 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_GET(value) (((value) & 0x00000001) >> 0)
8902 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_STATUS register field value suitable for setting the register. */
8903 #define ALT_SYSMGR_CORE_HMC_CLK_STATUS_SET(value) (((value) << 0) & 0x00000001)
8904 
8905 /*
8906  * Field : io_pll_lock_a
8907  *
8908  * PLL Lock A status
8909  *
8910  * Field Access Macros:
8911  *
8912  */
8913 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field. */
8914 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_LSB 8
8915 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field. */
8916 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_MSB 8
8917 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field. */
8918 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_WIDTH 1
8919 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field value. */
8920 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_SET_MSK 0x00000100
8921 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field value. */
8922 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_CLR_MSK 0xfffffeff
8923 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field is UNKNOWN. */
8924 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_RESET 0x0
8925 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A field value from a register. */
8926 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_GET(value) (((value) & 0x00000100) >> 8)
8927 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A register field value suitable for setting the register. */
8928 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A_SET(value) (((value) << 8) & 0x00000100)
8929 
8930 /*
8931  * Field : io_pll_lock_b
8932  *
8933  * PLL Lock B status
8934  *
8935  * Field Access Macros:
8936  *
8937  */
8938 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field. */
8939 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_LSB 9
8940 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field. */
8941 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_MSB 9
8942 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field. */
8943 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_WIDTH 1
8944 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field value. */
8945 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_SET_MSK 0x00000200
8946 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field value. */
8947 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_CLR_MSK 0xfffffdff
8948 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field is UNKNOWN. */
8949 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_RESET 0x0
8950 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B field value from a register. */
8951 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_GET(value) (((value) & 0x00000200) >> 9)
8952 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B register field value suitable for setting the register. */
8953 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B_SET(value) (((value) << 9) & 0x00000200)
8954 
8955 /*
8956  * Field : io_pll_lock_c
8957  *
8958  * PLL Lock C status
8959  *
8960  * Field Access Macros:
8961  *
8962  */
8963 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field. */
8964 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_LSB 10
8965 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field. */
8966 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_MSB 10
8967 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field. */
8968 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_WIDTH 1
8969 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field value. */
8970 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_SET_MSK 0x00000400
8971 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field value. */
8972 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_CLR_MSK 0xfffffbff
8973 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field is UNKNOWN. */
8974 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_RESET 0x0
8975 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C field value from a register. */
8976 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_GET(value) (((value) & 0x00000400) >> 10)
8977 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C register field value suitable for setting the register. */
8978 #define ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C_SET(value) (((value) << 10) & 0x00000400)
8979 
8980 /*
8981  * Field : io_cpa_lock_a
8982  *
8983  * CPA Lock A status
8984  *
8985  * Field Access Macros:
8986  *
8987  */
8988 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field. */
8989 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_LSB 16
8990 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field. */
8991 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_MSB 16
8992 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field. */
8993 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_WIDTH 1
8994 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field value. */
8995 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_SET_MSK 0x00010000
8996 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field value. */
8997 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_CLR_MSK 0xfffeffff
8998 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field is UNKNOWN. */
8999 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_RESET 0x0
9000 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A field value from a register. */
9001 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_GET(value) (((value) & 0x00010000) >> 16)
9002 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A register field value suitable for setting the register. */
9003 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A_SET(value) (((value) << 16) & 0x00010000)
9004 
9005 /*
9006  * Field : io_cpa_lock_b
9007  *
9008  * CPA Lock B status
9009  *
9010  * Field Access Macros:
9011  *
9012  */
9013 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field. */
9014 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_LSB 17
9015 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field. */
9016 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_MSB 17
9017 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field. */
9018 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_WIDTH 1
9019 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field value. */
9020 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_SET_MSK 0x00020000
9021 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field value. */
9022 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_CLR_MSK 0xfffdffff
9023 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field is UNKNOWN. */
9024 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_RESET 0x0
9025 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B field value from a register. */
9026 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_GET(value) (((value) & 0x00020000) >> 17)
9027 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B register field value suitable for setting the register. */
9028 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B_SET(value) (((value) << 17) & 0x00020000)
9029 
9030 /*
9031  * Field : io_cpa_lock_c
9032  *
9033  * CPA Lock C status
9034  *
9035  * Field Access Macros:
9036  *
9037  */
9038 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field. */
9039 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_LSB 18
9040 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field. */
9041 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_MSB 18
9042 /* The width in bits of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field. */
9043 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_WIDTH 1
9044 /* The mask used to set the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field value. */
9045 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_SET_MSK 0x00040000
9046 /* The mask used to clear the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field value. */
9047 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_CLR_MSK 0xfffbffff
9048 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field is UNKNOWN. */
9049 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_RESET 0x0
9050 /* Extracts the ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C field value from a register. */
9051 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_GET(value) (((value) & 0x00040000) >> 18)
9052 /* Produces a ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C register field value suitable for setting the register. */
9053 #define ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C_SET(value) (((value) << 18) & 0x00040000)
9054 
9055 #ifndef __ASSEMBLY__
9056 /*
9057  * WARNING: The C register and register group struct declarations are provided for
9058  * convenience and illustrative purposes. They should, however, be used with
9059  * caution as the C language standard provides no guarantees about the alignment or
9060  * atomicity of device memory accesses. The recommended practice for coding device
9061  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9062  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9063  * alt_write_dword() functions for 64 bit registers.
9064  *
9065  * The struct declaration for register ALT_SYSMGR_CORE_HMC_CLK.
9066  */
9067 struct ALT_SYSMGR_CORE_HMC_CLK_s
9068 {
9069  const volatile uint32_t status : 1; /* ALT_SYSMGR_CORE_HMC_CLK_STATUS */
9070  uint32_t : 7; /* *UNDEFINED* */
9071  const volatile uint32_t io_pll_lock_a : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_A */
9072  const volatile uint32_t io_pll_lock_b : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_B */
9073  const volatile uint32_t io_pll_lock_c : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_PLL_LOCK_C */
9074  uint32_t : 5; /* *UNDEFINED* */
9075  const volatile uint32_t io_cpa_lock_a : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_A */
9076  const volatile uint32_t io_cpa_lock_b : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_B */
9077  const volatile uint32_t io_cpa_lock_c : 1; /* ALT_SYSMGR_CORE_HMC_CLK_IO_CPA_LOCK_C */
9078  uint32_t : 13; /* *UNDEFINED* */
9079 };
9080 
9081 /* The typedef declaration for register ALT_SYSMGR_CORE_HMC_CLK. */
9082 typedef struct ALT_SYSMGR_CORE_HMC_CLK_s ALT_SYSMGR_CORE_HMC_CLK_t;
9083 #endif /* __ASSEMBLY__ */
9084 
9085 /* The reset value of the ALT_SYSMGR_CORE_HMC_CLK register. */
9086 #define ALT_SYSMGR_CORE_HMC_CLK_RESET 0x00000000
9087 /* The byte offset of the ALT_SYSMGR_CORE_HMC_CLK register from the beginning of the component. */
9088 #define ALT_SYSMGR_CORE_HMC_CLK_OFST 0xb4
9089 
9090 /*
9091  * Register : io_pa_ctrl
9092  *
9093  * HMC clock status indicator
9094  *
9095  * Register Layout
9096  *
9097  * Bits | Access | Reset | Description
9098  * :-------|:-------|:------|:-------------------------------------------
9099  * [0] | RW | 0x1 | ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A
9100  * [1] | RW | 0x1 | ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B
9101  * [2] | RW | 0x1 | ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C
9102  * [31:3] | ??? | 0x0 | *UNDEFINED*
9103  *
9104  */
9105 /*
9106  * Field : io_pa_reset_n_a
9107  *
9108  * This will allow HPS software to control when it wants to start receiving the
9109  * IO48 clock.
9110  *
9111  * Field Access Macros:
9112  *
9113  */
9114 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field. */
9115 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_LSB 0
9116 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field. */
9117 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_MSB 0
9118 /* The width in bits of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field. */
9119 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_WIDTH 1
9120 /* The mask used to set the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field value. */
9121 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_SET_MSK 0x00000001
9122 /* The mask used to clear the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field value. */
9123 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_CLR_MSK 0xfffffffe
9124 /* The reset value of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field. */
9125 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_RESET 0x1
9126 /* Extracts the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A field value from a register. */
9127 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_GET(value) (((value) & 0x00000001) >> 0)
9128 /* Produces a ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A register field value suitable for setting the register. */
9129 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A_SET(value) (((value) << 0) & 0x00000001)
9130 
9131 /*
9132  * Field : io_pa_reset_n_b
9133  *
9134  * This will allow HPS software to control when it wants to start receiving the
9135  * IO48 clock.
9136  *
9137  * Field Access Macros:
9138  *
9139  */
9140 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field. */
9141 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_LSB 1
9142 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field. */
9143 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_MSB 1
9144 /* The width in bits of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field. */
9145 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_WIDTH 1
9146 /* The mask used to set the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field value. */
9147 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_SET_MSK 0x00000002
9148 /* The mask used to clear the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field value. */
9149 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_CLR_MSK 0xfffffffd
9150 /* The reset value of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field. */
9151 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_RESET 0x1
9152 /* Extracts the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B field value from a register. */
9153 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_GET(value) (((value) & 0x00000002) >> 1)
9154 /* Produces a ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B register field value suitable for setting the register. */
9155 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B_SET(value) (((value) << 1) & 0x00000002)
9156 
9157 /*
9158  * Field : io_pa_reset_n_c
9159  *
9160  * This will allow HPS software to control when it wants to start receiving the
9161  * IO48 clock.
9162  *
9163  * Field Access Macros:
9164  *
9165  */
9166 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field. */
9167 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_LSB 2
9168 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field. */
9169 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_MSB 2
9170 /* The width in bits of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field. */
9171 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_WIDTH 1
9172 /* The mask used to set the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field value. */
9173 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_SET_MSK 0x00000004
9174 /* The mask used to clear the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field value. */
9175 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_CLR_MSK 0xfffffffb
9176 /* The reset value of the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field. */
9177 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_RESET 0x1
9178 /* Extracts the ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C field value from a register. */
9179 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_GET(value) (((value) & 0x00000004) >> 2)
9180 /* Produces a ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C register field value suitable for setting the register. */
9181 #define ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C_SET(value) (((value) << 2) & 0x00000004)
9182 
9183 #ifndef __ASSEMBLY__
9184 /*
9185  * WARNING: The C register and register group struct declarations are provided for
9186  * convenience and illustrative purposes. They should, however, be used with
9187  * caution as the C language standard provides no guarantees about the alignment or
9188  * atomicity of device memory accesses. The recommended practice for coding device
9189  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9190  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9191  * alt_write_dword() functions for 64 bit registers.
9192  *
9193  * The struct declaration for register ALT_SYSMGR_CORE_IO_PA_CTRL.
9194  */
9195 struct ALT_SYSMGR_CORE_IO_PA_CTRL_s
9196 {
9197  volatile uint32_t io_pa_reset_n_a : 1; /* ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_A */
9198  volatile uint32_t io_pa_reset_n_b : 1; /* ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_B */
9199  volatile uint32_t io_pa_reset_n_c : 1; /* ALT_SYSMGR_CORE_IO_PA_CTRL_IO_PA_RESET_N_C */
9200  uint32_t : 29; /* *UNDEFINED* */
9201 };
9202 
9203 /* The typedef declaration for register ALT_SYSMGR_CORE_IO_PA_CTRL. */
9204 typedef struct ALT_SYSMGR_CORE_IO_PA_CTRL_s ALT_SYSMGR_CORE_IO_PA_CTRL_t;
9205 #endif /* __ASSEMBLY__ */
9206 
9207 /* The reset value of the ALT_SYSMGR_CORE_IO_PA_CTRL register. */
9208 #define ALT_SYSMGR_CORE_IO_PA_CTRL_RESET 0x00000007
9209 /* The byte offset of the ALT_SYSMGR_CORE_IO_PA_CTRL register from the beginning of the component. */
9210 #define ALT_SYSMGR_CORE_IO_PA_CTRL_OFST 0xb8
9211 
9212 /*
9213  * Register : noc_timeout
9214  *
9215  * Register Layout
9216  *
9217  * Bits | Access | Reset | Description
9218  * :-------|:-------|:------|:-------------------------------
9219  * [0] | RW | 0x0 | ALT_SYSMGR_CORE_NOC_TIMEOUT_EN
9220  * [31:1] | ??? | 0x0 | *UNDEFINED*
9221  *
9222  */
9223 /*
9224  * Field : en
9225  *
9226  * NOC Timeout Enable. Write 1 to enable noc timeout.
9227  *
9228  * Field Access Macros:
9229  *
9230  */
9231 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field. */
9232 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_LSB 0
9233 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field. */
9234 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_MSB 0
9235 /* The width in bits of the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field. */
9236 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_WIDTH 1
9237 /* The mask used to set the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field value. */
9238 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_SET_MSK 0x00000001
9239 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field value. */
9240 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_CLR_MSK 0xfffffffe
9241 /* The reset value of the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field. */
9242 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_RESET 0x0
9243 /* Extracts the ALT_SYSMGR_CORE_NOC_TIMEOUT_EN field value from a register. */
9244 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_GET(value) (((value) & 0x00000001) >> 0)
9245 /* Produces a ALT_SYSMGR_CORE_NOC_TIMEOUT_EN register field value suitable for setting the register. */
9246 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_EN_SET(value) (((value) << 0) & 0x00000001)
9247 
9248 #ifndef __ASSEMBLY__
9249 /*
9250  * WARNING: The C register and register group struct declarations are provided for
9251  * convenience and illustrative purposes. They should, however, be used with
9252  * caution as the C language standard provides no guarantees about the alignment or
9253  * atomicity of device memory accesses. The recommended practice for coding device
9254  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9255  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9256  * alt_write_dword() functions for 64 bit registers.
9257  *
9258  * The struct declaration for register ALT_SYSMGR_CORE_NOC_TIMEOUT.
9259  */
9260 struct ALT_SYSMGR_CORE_NOC_TIMEOUT_s
9261 {
9262  volatile uint32_t en : 1; /* ALT_SYSMGR_CORE_NOC_TIMEOUT_EN */
9263  uint32_t : 31; /* *UNDEFINED* */
9264 };
9265 
9266 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_TIMEOUT. */
9267 typedef struct ALT_SYSMGR_CORE_NOC_TIMEOUT_s ALT_SYSMGR_CORE_NOC_TIMEOUT_t;
9268 #endif /* __ASSEMBLY__ */
9269 
9270 /* The reset value of the ALT_SYSMGR_CORE_NOC_TIMEOUT register. */
9271 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_RESET 0x00000000
9272 /* The byte offset of the ALT_SYSMGR_CORE_NOC_TIMEOUT register from the beginning of the component. */
9273 #define ALT_SYSMGR_CORE_NOC_TIMEOUT_OFST 0xc0
9274 
9275 /*
9276  * Register : noc_idlereq_set
9277  *
9278  * Set IDLE request to each NOC master.
9279  *
9280  * Register Layout
9281  *
9282  * Bits | Access | Reset | Description
9283  * :-------|:-------|:------|:-------------------------------------------
9284  * [0] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA
9285  * [3:1] | ??? | 0x0 | *UNDEFINED*
9286  * [4] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA
9287  * [31:5] | ??? | 0x0 | *UNDEFINED*
9288  *
9289  */
9290 /*
9291  * Field : soc2fpga
9292  *
9293  * Field Access Macros:
9294  *
9295  */
9296 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field. */
9297 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_LSB 0
9298 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field. */
9299 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_MSB 0
9300 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field. */
9301 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_WIDTH 1
9302 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field value. */
9303 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_SET_MSK 0x00000001
9304 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field value. */
9305 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_CLR_MSK 0xfffffffe
9306 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field. */
9307 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_RESET 0x0
9308 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA field value from a register. */
9309 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9310 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA register field value suitable for setting the register. */
9311 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9312 
9313 /*
9314  * Field : lwsoc2fpga
9315  *
9316  * Field Access Macros:
9317  *
9318  */
9319 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field. */
9320 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_LSB 4
9321 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field. */
9322 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_MSB 4
9323 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field. */
9324 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_WIDTH 1
9325 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field value. */
9326 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_SET_MSK 0x00000010
9327 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field value. */
9328 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_CLR_MSK 0xffffffef
9329 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field. */
9330 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_RESET 0x0
9331 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA field value from a register. */
9332 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9333 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA register field value suitable for setting the register. */
9334 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9335 
9336 #ifndef __ASSEMBLY__
9337 /*
9338  * WARNING: The C register and register group struct declarations are provided for
9339  * convenience and illustrative purposes. They should, however, be used with
9340  * caution as the C language standard provides no guarantees about the alignment or
9341  * atomicity of device memory accesses. The recommended practice for coding device
9342  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9343  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9344  * alt_write_dword() functions for 64 bit registers.
9345  *
9346  * The struct declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_SET.
9347  */
9348 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_s
9349 {
9350  volatile uint32_t soc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_SOC2FPGA */
9351  uint32_t : 3; /* *UNDEFINED* */
9352  volatile uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_LWSOC2FPGA */
9353  uint32_t : 27; /* *UNDEFINED* */
9354 };
9355 
9356 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_SET. */
9357 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_s ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_t;
9358 #endif /* __ASSEMBLY__ */
9359 
9360 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET register. */
9361 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_RESET 0x00000000
9362 /* The byte offset of the ALT_SYSMGR_CORE_NOC_IDLEREQ_SET register from the beginning of the component. */
9363 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_OFST 0xc4
9364 
9365 /*
9366  * Register : noc_idlereq_clr
9367  *
9368  * Clear IDLE request to each NOC master.
9369  *
9370  * Register Layout
9371  *
9372  * Bits | Access | Reset | Description
9373  * :-------|:-------|:------|:-------------------------------------------
9374  * [0] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA
9375  * [3:1] | ??? | 0x0 | *UNDEFINED*
9376  * [4] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA
9377  * [31:5] | ??? | 0x0 | *UNDEFINED*
9378  *
9379  */
9380 /*
9381  * Field : soc2fpga
9382  *
9383  * Field Access Macros:
9384  *
9385  */
9386 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field. */
9387 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_LSB 0
9388 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field. */
9389 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_MSB 0
9390 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field. */
9391 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_WIDTH 1
9392 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field value. */
9393 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_SET_MSK 0x00000001
9394 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field value. */
9395 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_CLR_MSK 0xfffffffe
9396 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field. */
9397 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_RESET 0x0
9398 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA field value from a register. */
9399 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9400 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA register field value suitable for setting the register. */
9401 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9402 
9403 /*
9404  * Field : lwsoc2fpga
9405  *
9406  * Field Access Macros:
9407  *
9408  */
9409 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field. */
9410 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_LSB 4
9411 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field. */
9412 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_MSB 4
9413 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field. */
9414 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_WIDTH 1
9415 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field value. */
9416 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_SET_MSK 0x00000010
9417 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field value. */
9418 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_CLR_MSK 0xffffffef
9419 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field. */
9420 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_RESET 0x0
9421 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA field value from a register. */
9422 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9423 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA register field value suitable for setting the register. */
9424 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9425 
9426 #ifndef __ASSEMBLY__
9427 /*
9428  * WARNING: The C register and register group struct declarations are provided for
9429  * convenience and illustrative purposes. They should, however, be used with
9430  * caution as the C language standard provides no guarantees about the alignment or
9431  * atomicity of device memory accesses. The recommended practice for coding device
9432  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9433  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9434  * alt_write_dword() functions for 64 bit registers.
9435  *
9436  * The struct declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR.
9437  */
9438 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_s
9439 {
9440  volatile uint32_t soc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_SOC2FPGA */
9441  uint32_t : 3; /* *UNDEFINED* */
9442  volatile uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_LWSOC2FPGA */
9443  uint32_t : 27; /* *UNDEFINED* */
9444 };
9445 
9446 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR. */
9447 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_s ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_t;
9448 #endif /* __ASSEMBLY__ */
9449 
9450 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR register. */
9451 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_RESET 0x00000000
9452 /* The byte offset of the ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR register from the beginning of the component. */
9453 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_OFST 0xc8
9454 
9455 /*
9456  * Register : noc_idlereq_value
9457  *
9458  * IDLE request to each NOC master.
9459  *
9460  * This register can be set by writing 1 to the specific bit in noc_idlereq_set
9461  * register.
9462  *
9463  * This register can be cleared by writing 1 to the specific bit in noc_idlereq_clr
9464  * register
9465  *
9466  * Register Layout
9467  *
9468  * Bits | Access | Reset | Description
9469  * :-------|:-------|:------|:---------------------------------------------
9470  * [0] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA
9471  * [3:1] | ??? | 0x0 | *UNDEFINED*
9472  * [4] | W | 0x0 | ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA
9473  * [31:5] | ??? | 0x0 | *UNDEFINED*
9474  *
9475  */
9476 /*
9477  * Field : soc2fpga
9478  *
9479  * Field Access Macros:
9480  *
9481  */
9482 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field. */
9483 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_LSB 0
9484 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field. */
9485 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_MSB 0
9486 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field. */
9487 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_WIDTH 1
9488 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field value. */
9489 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_SET_MSK 0x00000001
9490 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field value. */
9491 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_CLR_MSK 0xfffffffe
9492 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field. */
9493 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_RESET 0x0
9494 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA field value from a register. */
9495 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9496 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA register field value suitable for setting the register. */
9497 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9498 
9499 /*
9500  * Field : lwsoc2fpga
9501  *
9502  * Field Access Macros:
9503  *
9504  */
9505 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field. */
9506 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_LSB 4
9507 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field. */
9508 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_MSB 4
9509 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field. */
9510 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_WIDTH 1
9511 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field value. */
9512 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_SET_MSK 0x00000010
9513 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field value. */
9514 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_CLR_MSK 0xffffffef
9515 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field. */
9516 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_RESET 0x0
9517 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA field value from a register. */
9518 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9519 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA register field value suitable for setting the register. */
9520 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9521 
9522 #ifndef __ASSEMBLY__
9523 /*
9524  * WARNING: The C register and register group struct declarations are provided for
9525  * convenience and illustrative purposes. They should, however, be used with
9526  * caution as the C language standard provides no guarantees about the alignment or
9527  * atomicity of device memory accesses. The recommended practice for coding device
9528  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9529  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9530  * alt_write_dword() functions for 64 bit registers.
9531  *
9532  * The struct declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE.
9533  */
9534 struct ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_s
9535 {
9536  volatile uint32_t soc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_SOC2FPGA */
9537  uint32_t : 3; /* *UNDEFINED* */
9538  volatile uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_LWSOC2FPGA */
9539  uint32_t : 27; /* *UNDEFINED* */
9540 };
9541 
9542 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE. */
9543 typedef struct ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_s ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_t;
9544 #endif /* __ASSEMBLY__ */
9545 
9546 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE register. */
9547 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_RESET 0x00000000
9548 /* The byte offset of the ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE register from the beginning of the component. */
9549 #define ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_OFST 0xcc
9550 
9551 /*
9552  * Register : noc_idleack
9553  *
9554  * Idle acknowledge value from NOC Masters. This is asserted (value 1 in the field)
9555  * in response to the IDLE requests asserted by software.
9556  *
9557  * Register Layout
9558  *
9559  * Bits | Access | Reset | Description
9560  * :-------|:-------|:------|:---------------------------------------
9561  * [0] | R | 0x1 | ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA
9562  * [3:1] | ??? | 0x0 | *UNDEFINED*
9563  * [4] | R | 0x1 | ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA
9564  * [31:5] | ??? | 0x0 | *UNDEFINED*
9565  *
9566  */
9567 /*
9568  * Field : soc2fpga
9569  *
9570  * Field Access Macros:
9571  *
9572  */
9573 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field. */
9574 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_LSB 0
9575 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field. */
9576 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_MSB 0
9577 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field. */
9578 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_WIDTH 1
9579 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field value. */
9580 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_SET_MSK 0x00000001
9581 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field value. */
9582 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_CLR_MSK 0xfffffffe
9583 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field. */
9584 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_RESET 0x1
9585 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA field value from a register. */
9586 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9587 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA register field value suitable for setting the register. */
9588 #define ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9589 
9590 /*
9591  * Field : lwsoc2fpga
9592  *
9593  * Field Access Macros:
9594  *
9595  */
9596 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field. */
9597 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_LSB 4
9598 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field. */
9599 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_MSB 4
9600 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field. */
9601 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_WIDTH 1
9602 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field value. */
9603 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_SET_MSK 0x00000010
9604 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field value. */
9605 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_CLR_MSK 0xffffffef
9606 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field. */
9607 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_RESET 0x1
9608 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA field value from a register. */
9609 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9610 /* Produces a ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA register field value suitable for setting the register. */
9611 #define ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9612 
9613 #ifndef __ASSEMBLY__
9614 /*
9615  * WARNING: The C register and register group struct declarations are provided for
9616  * convenience and illustrative purposes. They should, however, be used with
9617  * caution as the C language standard provides no guarantees about the alignment or
9618  * atomicity of device memory accesses. The recommended practice for coding device
9619  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9620  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9621  * alt_write_dword() functions for 64 bit registers.
9622  *
9623  * The struct declaration for register ALT_SYSMGR_CORE_NOC_IDLEACK.
9624  */
9625 struct ALT_SYSMGR_CORE_NOC_IDLEACK_s
9626 {
9627  const volatile uint32_t soc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEACK_SOC2FPGA */
9628  uint32_t : 3; /* *UNDEFINED* */
9629  const volatile uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLEACK_LWSOC2FPGA */
9630  uint32_t : 27; /* *UNDEFINED* */
9631 };
9632 
9633 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_IDLEACK. */
9634 typedef struct ALT_SYSMGR_CORE_NOC_IDLEACK_s ALT_SYSMGR_CORE_NOC_IDLEACK_t;
9635 #endif /* __ASSEMBLY__ */
9636 
9637 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLEACK register. */
9638 #define ALT_SYSMGR_CORE_NOC_IDLEACK_RESET 0x00000011
9639 /* The byte offset of the ALT_SYSMGR_CORE_NOC_IDLEACK register from the beginning of the component. */
9640 #define ALT_SYSMGR_CORE_NOC_IDLEACK_OFST 0xd0
9641 
9642 /*
9643  * Register : noc_idlestatus
9644  *
9645  * Status of IDLE from the NOC masters. A 1 in the field means the specific master
9646  * is idle.
9647  *
9648  * Register Layout
9649  *
9650  * Bits | Access | Reset | Description
9651  * :-------|:-------|:------|:------------------------------------------
9652  * [0] | R | 0x1 | ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA
9653  * [3:1] | ??? | 0x0 | *UNDEFINED*
9654  * [4] | R | 0x1 | ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA
9655  * [31:5] | ??? | 0x0 | *UNDEFINED*
9656  *
9657  */
9658 /*
9659  * Field : soc2fpga
9660  *
9661  * Field Access Macros:
9662  *
9663  */
9664 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field. */
9665 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_LSB 0
9666 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field. */
9667 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_MSB 0
9668 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field. */
9669 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_WIDTH 1
9670 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field value. */
9671 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_SET_MSK 0x00000001
9672 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field value. */
9673 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_CLR_MSK 0xfffffffe
9674 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field. */
9675 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_RESET 0x1
9676 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA field value from a register. */
9677 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
9678 /* Produces a ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA register field value suitable for setting the register. */
9679 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
9680 
9681 /*
9682  * Field : lwsoc2fpga
9683  *
9684  * Field Access Macros:
9685  *
9686  */
9687 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field. */
9688 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_LSB 4
9689 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field. */
9690 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_MSB 4
9691 /* The width in bits of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field. */
9692 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_WIDTH 1
9693 /* The mask used to set the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field value. */
9694 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_SET_MSK 0x00000010
9695 /* The mask used to clear the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field value. */
9696 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_CLR_MSK 0xffffffef
9697 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field. */
9698 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_RESET 0x1
9699 /* Extracts the ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA field value from a register. */
9700 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_GET(value) (((value) & 0x00000010) >> 4)
9701 /* Produces a ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA register field value suitable for setting the register. */
9702 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA_SET(value) (((value) << 4) & 0x00000010)
9703 
9704 #ifndef __ASSEMBLY__
9705 /*
9706  * WARNING: The C register and register group struct declarations are provided for
9707  * convenience and illustrative purposes. They should, however, be used with
9708  * caution as the C language standard provides no guarantees about the alignment or
9709  * atomicity of device memory accesses. The recommended practice for coding device
9710  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9711  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9712  * alt_write_dword() functions for 64 bit registers.
9713  *
9714  * The struct declaration for register ALT_SYSMGR_CORE_NOC_IDLESTATUS.
9715  */
9716 struct ALT_SYSMGR_CORE_NOC_IDLESTATUS_s
9717 {
9718  const volatile uint32_t soc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLESTATUS_SOC2FPGA */
9719  uint32_t : 3; /* *UNDEFINED* */
9720  const volatile uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_CORE_NOC_IDLESTATUS_LWSOC2FPGA */
9721  uint32_t : 27; /* *UNDEFINED* */
9722 };
9723 
9724 /* The typedef declaration for register ALT_SYSMGR_CORE_NOC_IDLESTATUS. */
9725 typedef struct ALT_SYSMGR_CORE_NOC_IDLESTATUS_s ALT_SYSMGR_CORE_NOC_IDLESTATUS_t;
9726 #endif /* __ASSEMBLY__ */
9727 
9728 /* The reset value of the ALT_SYSMGR_CORE_NOC_IDLESTATUS register. */
9729 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_RESET 0x00000011
9730 /* The byte offset of the ALT_SYSMGR_CORE_NOC_IDLESTATUS register from the beginning of the component. */
9731 #define ALT_SYSMGR_CORE_NOC_IDLESTATUS_OFST 0xd4
9732 
9733 /*
9734  * Register : fpga2soc_ctrl
9735  *
9736  * Register Layout
9737  *
9738  * Bits | Access | Reset | Description
9739  * :-------|:-------|:------|:-------------------------------------------
9740  * [0] | RW | 0x1 | ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE
9741  * [31:1] | ??? | 0x0 | *UNDEFINED*
9742  *
9743  */
9744 /*
9745  * Field : allow_secure
9746  *
9747  * 0 - All Transactions from FPGA2SOC is converted to be Non-Secure
9748  *
9749  * 1 - Both Secure and Non-Secure Transactions is allowed by FPGA2SOC.
9750  *
9751  * Field Access Macros:
9752  *
9753  */
9754 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field. */
9755 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_LSB 0
9756 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field. */
9757 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_MSB 0
9758 /* The width in bits of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field. */
9759 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_WIDTH 1
9760 /* The mask used to set the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field value. */
9761 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_SET_MSK 0x00000001
9762 /* The mask used to clear the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field value. */
9763 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_CLR_MSK 0xfffffffe
9764 /* The reset value of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field. */
9765 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_RESET 0x1
9766 /* Extracts the ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE field value from a register. */
9767 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_GET(value) (((value) & 0x00000001) >> 0)
9768 /* Produces a ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE register field value suitable for setting the register. */
9769 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE_SET(value) (((value) << 0) & 0x00000001)
9770 
9771 #ifndef __ASSEMBLY__
9772 /*
9773  * WARNING: The C register and register group struct declarations are provided for
9774  * convenience and illustrative purposes. They should, however, be used with
9775  * caution as the C language standard provides no guarantees about the alignment or
9776  * atomicity of device memory accesses. The recommended practice for coding device
9777  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9778  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9779  * alt_write_dword() functions for 64 bit registers.
9780  *
9781  * The struct declaration for register ALT_SYSMGR_CORE_FPGA2SOC_CTRL.
9782  */
9783 struct ALT_SYSMGR_CORE_FPGA2SOC_CTRL_s
9784 {
9785  volatile uint32_t allow_secure : 1; /* ALT_SYSMGR_CORE_FPGA2SOC_CTRL_ALLOW_SECURE */
9786  uint32_t : 31; /* *UNDEFINED* */
9787 };
9788 
9789 /* The typedef declaration for register ALT_SYSMGR_CORE_FPGA2SOC_CTRL. */
9790 typedef struct ALT_SYSMGR_CORE_FPGA2SOC_CTRL_s ALT_SYSMGR_CORE_FPGA2SOC_CTRL_t;
9791 #endif /* __ASSEMBLY__ */
9792 
9793 /* The reset value of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL register. */
9794 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_RESET 0x00000001
9795 /* The byte offset of the ALT_SYSMGR_CORE_FPGA2SOC_CTRL register from the beginning of the component. */
9796 #define ALT_SYSMGR_CORE_FPGA2SOC_CTRL_OFST 0xd8
9797 
9798 /*
9799  * Register : fpga_config
9800  *
9801  * FPGA configuration read only register
9802  *
9803  * Register Layout
9804  *
9805  * Bits | Access | Reset | Description
9806  * :-------|:-------|:------|:-------------------------------------------
9807  * [0] | R | 0x0 | ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE
9808  * [1] | R | 0x0 | ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE
9809  * [31:2] | ??? | 0x0 | *UNDEFINED*
9810  *
9811  */
9812 /*
9813  * Field : fpga_complete
9814  *
9815  * FGPA configuration complete
9816  *
9817  * Field Access Macros:
9818  *
9819  */
9820 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field. */
9821 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_LSB 0
9822 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field. */
9823 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_MSB 0
9824 /* The width in bits of the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field. */
9825 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_WIDTH 1
9826 /* The mask used to set the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field value. */
9827 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_SET_MSK 0x00000001
9828 /* The mask used to clear the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field value. */
9829 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_CLR_MSK 0xfffffffe
9830 /* The reset value of the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field. */
9831 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_RESET 0x0
9832 /* Extracts the ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE field value from a register. */
9833 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_GET(value) (((value) & 0x00000001) >> 0)
9834 /* Produces a ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE register field value suitable for setting the register. */
9835 #define ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE_SET(value) (((value) << 0) & 0x00000001)
9836 
9837 /*
9838  * Field : early_usermode
9839  *
9840  * FGPA configuration complete
9841  *
9842  * Field Access Macros:
9843  *
9844  */
9845 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field. */
9846 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_LSB 1
9847 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field. */
9848 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_MSB 1
9849 /* The width in bits of the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field. */
9850 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_WIDTH 1
9851 /* The mask used to set the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field value. */
9852 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_SET_MSK 0x00000002
9853 /* The mask used to clear the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field value. */
9854 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_CLR_MSK 0xfffffffd
9855 /* The reset value of the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field. */
9856 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_RESET 0x0
9857 /* Extracts the ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE field value from a register. */
9858 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_GET(value) (((value) & 0x00000002) >> 1)
9859 /* Produces a ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE register field value suitable for setting the register. */
9860 #define ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE_SET(value) (((value) << 1) & 0x00000002)
9861 
9862 #ifndef __ASSEMBLY__
9863 /*
9864  * WARNING: The C register and register group struct declarations are provided for
9865  * convenience and illustrative purposes. They should, however, be used with
9866  * caution as the C language standard provides no guarantees about the alignment or
9867  * atomicity of device memory accesses. The recommended practice for coding device
9868  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9869  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9870  * alt_write_dword() functions for 64 bit registers.
9871  *
9872  * The struct declaration for register ALT_SYSMGR_CORE_FPGA_CONFIG.
9873  */
9874 struct ALT_SYSMGR_CORE_FPGA_CONFIG_s
9875 {
9876  const volatile uint32_t fpga_complete : 1; /* ALT_SYSMGR_CORE_FPGA_CONFIG_FPGA_COMPLETE */
9877  const volatile uint32_t early_usermode : 1; /* ALT_SYSMGR_CORE_FPGA_CONFIG_EARLY_USERMODE */
9878  uint32_t : 30; /* *UNDEFINED* */
9879 };
9880 
9881 /* The typedef declaration for register ALT_SYSMGR_CORE_FPGA_CONFIG. */
9882 typedef struct ALT_SYSMGR_CORE_FPGA_CONFIG_s ALT_SYSMGR_CORE_FPGA_CONFIG_t;
9883 #endif /* __ASSEMBLY__ */
9884 
9885 /* The reset value of the ALT_SYSMGR_CORE_FPGA_CONFIG register. */
9886 #define ALT_SYSMGR_CORE_FPGA_CONFIG_RESET 0x00000000
9887 /* The byte offset of the ALT_SYSMGR_CORE_FPGA_CONFIG register from the beginning of the component. */
9888 #define ALT_SYSMGR_CORE_FPGA_CONFIG_OFST 0xdc
9889 
9890 /*
9891  * Register : iocsrclk_gate
9892  *
9893  * IO Clock control
9894  *
9895  * Register Layout
9896  *
9897  * Bits | Access | Reset | Description
9898  * :--------|:-------|:------|:------------------------------------
9899  * [0] | RW | 0x0 | ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA
9900  * [7:1] | ??? | 0x0 | *UNDEFINED*
9901  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB
9902  * [15:9] | ??? | 0x0 | *UNDEFINED*
9903  * [16] | RW | 0x0 | ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC
9904  * [31:17] | ??? | 0x0 | *UNDEFINED*
9905  *
9906  */
9907 /*
9908  * Field : tilea
9909  *
9910  * Tile A clock control
9911  *
9912  * Field Access Macros:
9913  *
9914  */
9915 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field. */
9916 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_LSB 0
9917 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field. */
9918 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_MSB 0
9919 /* The width in bits of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field. */
9920 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_WIDTH 1
9921 /* The mask used to set the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field value. */
9922 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_SET_MSK 0x00000001
9923 /* The mask used to clear the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field value. */
9924 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_CLR_MSK 0xfffffffe
9925 /* The reset value of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field. */
9926 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_RESET 0x0
9927 /* Extracts the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA field value from a register. */
9928 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_GET(value) (((value) & 0x00000001) >> 0)
9929 /* Produces a ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA register field value suitable for setting the register. */
9930 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA_SET(value) (((value) << 0) & 0x00000001)
9931 
9932 /*
9933  * Field : tileb
9934  *
9935  * Tile B clock control
9936  *
9937  * Field Access Macros:
9938  *
9939  */
9940 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field. */
9941 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_LSB 8
9942 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field. */
9943 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_MSB 8
9944 /* The width in bits of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field. */
9945 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_WIDTH 1
9946 /* The mask used to set the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field value. */
9947 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_SET_MSK 0x00000100
9948 /* The mask used to clear the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field value. */
9949 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_CLR_MSK 0xfffffeff
9950 /* The reset value of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field. */
9951 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_RESET 0x0
9952 /* Extracts the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB field value from a register. */
9953 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_GET(value) (((value) & 0x00000100) >> 8)
9954 /* Produces a ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB register field value suitable for setting the register. */
9955 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB_SET(value) (((value) << 8) & 0x00000100)
9956 
9957 /*
9958  * Field : tilec
9959  *
9960  * Tile C clock control
9961  *
9962  * Field Access Macros:
9963  *
9964  */
9965 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field. */
9966 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_LSB 16
9967 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field. */
9968 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_MSB 16
9969 /* The width in bits of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field. */
9970 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_WIDTH 1
9971 /* The mask used to set the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field value. */
9972 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_SET_MSK 0x00010000
9973 /* The mask used to clear the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field value. */
9974 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_CLR_MSK 0xfffeffff
9975 /* The reset value of the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field. */
9976 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_RESET 0x0
9977 /* Extracts the ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC field value from a register. */
9978 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_GET(value) (((value) & 0x00010000) >> 16)
9979 /* Produces a ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC register field value suitable for setting the register. */
9980 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC_SET(value) (((value) << 16) & 0x00010000)
9981 
9982 #ifndef __ASSEMBLY__
9983 /*
9984  * WARNING: The C register and register group struct declarations are provided for
9985  * convenience and illustrative purposes. They should, however, be used with
9986  * caution as the C language standard provides no guarantees about the alignment or
9987  * atomicity of device memory accesses. The recommended practice for coding device
9988  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9989  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9990  * alt_write_dword() functions for 64 bit registers.
9991  *
9992  * The struct declaration for register ALT_SYSMGR_CORE_IOCSRCLK_GATE.
9993  */
9994 struct ALT_SYSMGR_CORE_IOCSRCLK_GATE_s
9995 {
9996  volatile uint32_t tilea : 1; /* ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEA */
9997  uint32_t : 7; /* *UNDEFINED* */
9998  volatile uint32_t tileb : 1; /* ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEB */
9999  uint32_t : 7; /* *UNDEFINED* */
10000  volatile uint32_t tilec : 1; /* ALT_SYSMGR_CORE_IOCSRCLK_GATE_TILEC */
10001  uint32_t : 15; /* *UNDEFINED* */
10002 };
10003 
10004 /* The typedef declaration for register ALT_SYSMGR_CORE_IOCSRCLK_GATE. */
10005 typedef struct ALT_SYSMGR_CORE_IOCSRCLK_GATE_s ALT_SYSMGR_CORE_IOCSRCLK_GATE_t;
10006 #endif /* __ASSEMBLY__ */
10007 
10008 /* The reset value of the ALT_SYSMGR_CORE_IOCSRCLK_GATE register. */
10009 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_RESET 0x00000000
10010 /* The byte offset of the ALT_SYSMGR_CORE_IOCSRCLK_GATE register from the beginning of the component. */
10011 #define ALT_SYSMGR_CORE_IOCSRCLK_GATE_OFST 0xe0
10012 
10013 /*
10014  * Register : gpo
10015  *
10016  * Provides a low-latency, low-performance, and simple way to drive general-purpose
10017  * signals to the FPGA fabric
10018  *
10019  * Register Layout
10020  *
10021  * Bits | Access | Reset | Description
10022  * :-------|:-------|:------|:------------------------
10023  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_GPO_VAL
10024  *
10025  */
10026 /*
10027  * Field : val
10028  *
10029  * Drives s2f_gp[31:0] with specified value. When read, returns the current value
10030  * being driven to the FPGA fabric
10031  *
10032  * Field Access Macros:
10033  *
10034  */
10035 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_GPO_VAL register field. */
10036 #define ALT_SYSMGR_CORE_GPO_VAL_LSB 0
10037 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_GPO_VAL register field. */
10038 #define ALT_SYSMGR_CORE_GPO_VAL_MSB 31
10039 /* The width in bits of the ALT_SYSMGR_CORE_GPO_VAL register field. */
10040 #define ALT_SYSMGR_CORE_GPO_VAL_WIDTH 32
10041 /* The mask used to set the ALT_SYSMGR_CORE_GPO_VAL register field value. */
10042 #define ALT_SYSMGR_CORE_GPO_VAL_SET_MSK 0xffffffff
10043 /* The mask used to clear the ALT_SYSMGR_CORE_GPO_VAL register field value. */
10044 #define ALT_SYSMGR_CORE_GPO_VAL_CLR_MSK 0x00000000
10045 /* The reset value of the ALT_SYSMGR_CORE_GPO_VAL register field. */
10046 #define ALT_SYSMGR_CORE_GPO_VAL_RESET 0x0
10047 /* Extracts the ALT_SYSMGR_CORE_GPO_VAL field value from a register. */
10048 #define ALT_SYSMGR_CORE_GPO_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10049 /* Produces a ALT_SYSMGR_CORE_GPO_VAL register field value suitable for setting the register. */
10050 #define ALT_SYSMGR_CORE_GPO_VAL_SET(value) (((value) << 0) & 0xffffffff)
10051 
10052 #ifndef __ASSEMBLY__
10053 /*
10054  * WARNING: The C register and register group struct declarations are provided for
10055  * convenience and illustrative purposes. They should, however, be used with
10056  * caution as the C language standard provides no guarantees about the alignment or
10057  * atomicity of device memory accesses. The recommended practice for coding device
10058  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10059  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10060  * alt_write_dword() functions for 64 bit registers.
10061  *
10062  * The struct declaration for register ALT_SYSMGR_CORE_GPO.
10063  */
10064 struct ALT_SYSMGR_CORE_GPO_s
10065 {
10066  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_GPO_VAL */
10067 };
10068 
10069 /* The typedef declaration for register ALT_SYSMGR_CORE_GPO. */
10070 typedef struct ALT_SYSMGR_CORE_GPO_s ALT_SYSMGR_CORE_GPO_t;
10071 #endif /* __ASSEMBLY__ */
10072 
10073 /* The reset value of the ALT_SYSMGR_CORE_GPO register. */
10074 #define ALT_SYSMGR_CORE_GPO_RESET 0x00000000
10075 /* The byte offset of the ALT_SYSMGR_CORE_GPO register from the beginning of the component. */
10076 #define ALT_SYSMGR_CORE_GPO_OFST 0xe4
10077 
10078 /*
10079  * Register : gpi
10080  *
10081  * Provides a low-latency, low-performance, and simple way to read general-purpose
10082  * signals driven from the FPGA fabric.
10083  *
10084  * Register Layout
10085  *
10086  * Bits | Access | Reset | Description
10087  * :-------|:-------|:------|:------------------------
10088  * [31:0] | R | 0x0 | ALT_SYSMGR_CORE_GPI_VAL
10089  *
10090  */
10091 /*
10092  * Field : val
10093  *
10094  * The value being driven from the FPGA fabric on f2s_gp[31:0]. If the FPGA is not
10095  * in User Mode, the value of this field is undefined.
10096  *
10097  * Field Access Macros:
10098  *
10099  */
10100 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_GPI_VAL register field. */
10101 #define ALT_SYSMGR_CORE_GPI_VAL_LSB 0
10102 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_GPI_VAL register field. */
10103 #define ALT_SYSMGR_CORE_GPI_VAL_MSB 31
10104 /* The width in bits of the ALT_SYSMGR_CORE_GPI_VAL register field. */
10105 #define ALT_SYSMGR_CORE_GPI_VAL_WIDTH 32
10106 /* The mask used to set the ALT_SYSMGR_CORE_GPI_VAL register field value. */
10107 #define ALT_SYSMGR_CORE_GPI_VAL_SET_MSK 0xffffffff
10108 /* The mask used to clear the ALT_SYSMGR_CORE_GPI_VAL register field value. */
10109 #define ALT_SYSMGR_CORE_GPI_VAL_CLR_MSK 0x00000000
10110 /* The reset value of the ALT_SYSMGR_CORE_GPI_VAL register field. */
10111 #define ALT_SYSMGR_CORE_GPI_VAL_RESET 0x0
10112 /* Extracts the ALT_SYSMGR_CORE_GPI_VAL field value from a register. */
10113 #define ALT_SYSMGR_CORE_GPI_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10114 /* Produces a ALT_SYSMGR_CORE_GPI_VAL register field value suitable for setting the register. */
10115 #define ALT_SYSMGR_CORE_GPI_VAL_SET(value) (((value) << 0) & 0xffffffff)
10116 
10117 #ifndef __ASSEMBLY__
10118 /*
10119  * WARNING: The C register and register group struct declarations are provided for
10120  * convenience and illustrative purposes. They should, however, be used with
10121  * caution as the C language standard provides no guarantees about the alignment or
10122  * atomicity of device memory accesses. The recommended practice for coding device
10123  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10124  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10125  * alt_write_dword() functions for 64 bit registers.
10126  *
10127  * The struct declaration for register ALT_SYSMGR_CORE_GPI.
10128  */
10129 struct ALT_SYSMGR_CORE_GPI_s
10130 {
10131  const volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_GPI_VAL */
10132 };
10133 
10134 /* The typedef declaration for register ALT_SYSMGR_CORE_GPI. */
10135 typedef struct ALT_SYSMGR_CORE_GPI_s ALT_SYSMGR_CORE_GPI_t;
10136 #endif /* __ASSEMBLY__ */
10137 
10138 /* The reset value of the ALT_SYSMGR_CORE_GPI register. */
10139 #define ALT_SYSMGR_CORE_GPI_RESET 0x00000000
10140 /* The byte offset of the ALT_SYSMGR_CORE_GPI register from the beginning of the component. */
10141 #define ALT_SYSMGR_CORE_GPI_OFST 0xe8
10142 
10143 /*
10144  * Register : mpu
10145  *
10146  * Provides a low-latency, low-performance, and simple way to read general-purpose
10147  * signals driven from the FPGA fabric.
10148  *
10149  * Register Layout
10150  *
10151  * Bits | Access | Reset | Description
10152  * :-------|:-------|:------|:------------------------------------
10153  * [0] | RW | 0x0 | ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE
10154  * [31:1] | ??? | 0x0 | *UNDEFINED*
10155  *
10156  */
10157 /*
10158  * Field : mpu_cfgsdisable
10159  *
10160  * CFGSDISABLE is typically de-asserted (0) from reset until Secure software has
10161  * configured the GIC-400 and then subsequently asserted permanently to provide
10162  * extra security.
10163  *
10164  * Field Access Macros:
10165  *
10166  */
10167 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field. */
10168 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_LSB 0
10169 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field. */
10170 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_MSB 0
10171 /* The width in bits of the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field. */
10172 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_WIDTH 1
10173 /* The mask used to set the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field value. */
10174 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_SET_MSK 0x00000001
10175 /* The mask used to clear the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field value. */
10176 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_CLR_MSK 0xfffffffe
10177 /* The reset value of the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field. */
10178 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_RESET 0x0
10179 /* Extracts the ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE field value from a register. */
10180 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_GET(value) (((value) & 0x00000001) >> 0)
10181 /* Produces a ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE register field value suitable for setting the register. */
10182 #define ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE_SET(value) (((value) << 0) & 0x00000001)
10183 
10184 #ifndef __ASSEMBLY__
10185 /*
10186  * WARNING: The C register and register group struct declarations are provided for
10187  * convenience and illustrative purposes. They should, however, be used with
10188  * caution as the C language standard provides no guarantees about the alignment or
10189  * atomicity of device memory accesses. The recommended practice for coding device
10190  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10191  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10192  * alt_write_dword() functions for 64 bit registers.
10193  *
10194  * The struct declaration for register ALT_SYSMGR_CORE_MPU.
10195  */
10196 struct ALT_SYSMGR_CORE_MPU_s
10197 {
10198  volatile uint32_t mpu_cfgsdisable : 1; /* ALT_SYSMGR_CORE_MPU_MPU_CFGSDISABLE */
10199  uint32_t : 31; /* *UNDEFINED* */
10200 };
10201 
10202 /* The typedef declaration for register ALT_SYSMGR_CORE_MPU. */
10203 typedef struct ALT_SYSMGR_CORE_MPU_s ALT_SYSMGR_CORE_MPU_t;
10204 #endif /* __ASSEMBLY__ */
10205 
10206 /* The reset value of the ALT_SYSMGR_CORE_MPU register. */
10207 #define ALT_SYSMGR_CORE_MPU_RESET 0x00000000
10208 /* The byte offset of the ALT_SYSMGR_CORE_MPU register from the beginning of the component. */
10209 #define ALT_SYSMGR_CORE_MPU_OFST 0xf0
10210 
10211 /*
10212  * Register : sdm_hps_spare
10213  *
10214  * SDM to HPS spare signals are mapped to a system manager register. PSI side band
10215  * signals will set these bits and HPS SW will clear this register
10216  *
10217  * Register Layout
10218  *
10219  * Bits | Access | Reset | Description
10220  * :--------|:-------|:------|:-------------------------------------
10221  * [0] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0
10222  * [1] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1
10223  * [2] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2
10224  * [3] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3
10225  * [4] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4
10226  * [5] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5
10227  * [6] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6
10228  * [7] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7
10229  * [8] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8
10230  * [9] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9
10231  * [10] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10
10232  * [11] | RW | 0x0 | ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11
10233  * [31:12] | ??? | 0x0 | *UNDEFINED*
10234  *
10235  */
10236 /*
10237  * Field : bit_0
10238  *
10239  * Field Access Macros:
10240  *
10241  */
10242 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field. */
10243 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_LSB 0
10244 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field. */
10245 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_MSB 0
10246 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field. */
10247 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_WIDTH 1
10248 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field value. */
10249 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_SET_MSK 0x00000001
10250 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field value. */
10251 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_CLR_MSK 0xfffffffe
10252 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field. */
10253 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_RESET 0x0
10254 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 field value from a register. */
10255 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_GET(value) (((value) & 0x00000001) >> 0)
10256 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 register field value suitable for setting the register. */
10257 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0_SET(value) (((value) << 0) & 0x00000001)
10258 
10259 /*
10260  * Field : bit_1
10261  *
10262  * Field Access Macros:
10263  *
10264  */
10265 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field. */
10266 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_LSB 1
10267 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field. */
10268 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_MSB 1
10269 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field. */
10270 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_WIDTH 1
10271 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field value. */
10272 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_SET_MSK 0x00000002
10273 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field value. */
10274 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_CLR_MSK 0xfffffffd
10275 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field. */
10276 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_RESET 0x0
10277 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 field value from a register. */
10278 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_GET(value) (((value) & 0x00000002) >> 1)
10279 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 register field value suitable for setting the register. */
10280 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1_SET(value) (((value) << 1) & 0x00000002)
10281 
10282 /*
10283  * Field : bit_2
10284  *
10285  * Field Access Macros:
10286  *
10287  */
10288 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field. */
10289 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_LSB 2
10290 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field. */
10291 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_MSB 2
10292 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field. */
10293 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_WIDTH 1
10294 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field value. */
10295 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_SET_MSK 0x00000004
10296 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field value. */
10297 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_CLR_MSK 0xfffffffb
10298 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field. */
10299 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_RESET 0x0
10300 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 field value from a register. */
10301 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_GET(value) (((value) & 0x00000004) >> 2)
10302 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 register field value suitable for setting the register. */
10303 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2_SET(value) (((value) << 2) & 0x00000004)
10304 
10305 /*
10306  * Field : bit_3
10307  *
10308  * Field Access Macros:
10309  *
10310  */
10311 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field. */
10312 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_LSB 3
10313 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field. */
10314 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_MSB 3
10315 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field. */
10316 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_WIDTH 1
10317 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field value. */
10318 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_SET_MSK 0x00000008
10319 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field value. */
10320 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_CLR_MSK 0xfffffff7
10321 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field. */
10322 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_RESET 0x0
10323 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 field value from a register. */
10324 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_GET(value) (((value) & 0x00000008) >> 3)
10325 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 register field value suitable for setting the register. */
10326 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3_SET(value) (((value) << 3) & 0x00000008)
10327 
10328 /*
10329  * Field : bit_4
10330  *
10331  * Field Access Macros:
10332  *
10333  */
10334 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field. */
10335 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_LSB 4
10336 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field. */
10337 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_MSB 4
10338 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field. */
10339 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_WIDTH 1
10340 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field value. */
10341 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_SET_MSK 0x00000010
10342 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field value. */
10343 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_CLR_MSK 0xffffffef
10344 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field. */
10345 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_RESET 0x0
10346 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 field value from a register. */
10347 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_GET(value) (((value) & 0x00000010) >> 4)
10348 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 register field value suitable for setting the register. */
10349 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4_SET(value) (((value) << 4) & 0x00000010)
10350 
10351 /*
10352  * Field : bit_5
10353  *
10354  * Field Access Macros:
10355  *
10356  */
10357 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field. */
10358 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_LSB 5
10359 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field. */
10360 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_MSB 5
10361 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field. */
10362 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_WIDTH 1
10363 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field value. */
10364 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_SET_MSK 0x00000020
10365 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field value. */
10366 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_CLR_MSK 0xffffffdf
10367 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field. */
10368 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_RESET 0x0
10369 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 field value from a register. */
10370 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_GET(value) (((value) & 0x00000020) >> 5)
10371 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 register field value suitable for setting the register. */
10372 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5_SET(value) (((value) << 5) & 0x00000020)
10373 
10374 /*
10375  * Field : bit_6
10376  *
10377  * Field Access Macros:
10378  *
10379  */
10380 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field. */
10381 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_LSB 6
10382 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field. */
10383 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_MSB 6
10384 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field. */
10385 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_WIDTH 1
10386 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field value. */
10387 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_SET_MSK 0x00000040
10388 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field value. */
10389 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_CLR_MSK 0xffffffbf
10390 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field. */
10391 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_RESET 0x0
10392 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 field value from a register. */
10393 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_GET(value) (((value) & 0x00000040) >> 6)
10394 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 register field value suitable for setting the register. */
10395 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6_SET(value) (((value) << 6) & 0x00000040)
10396 
10397 /*
10398  * Field : bit_7
10399  *
10400  * Field Access Macros:
10401  *
10402  */
10403 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field. */
10404 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_LSB 7
10405 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field. */
10406 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_MSB 7
10407 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field. */
10408 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_WIDTH 1
10409 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field value. */
10410 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_SET_MSK 0x00000080
10411 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field value. */
10412 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_CLR_MSK 0xffffff7f
10413 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field. */
10414 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_RESET 0x0
10415 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 field value from a register. */
10416 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_GET(value) (((value) & 0x00000080) >> 7)
10417 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 register field value suitable for setting the register. */
10418 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7_SET(value) (((value) << 7) & 0x00000080)
10419 
10420 /*
10421  * Field : bit_8
10422  *
10423  * Field Access Macros:
10424  *
10425  */
10426 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field. */
10427 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_LSB 8
10428 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field. */
10429 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_MSB 8
10430 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field. */
10431 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_WIDTH 1
10432 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field value. */
10433 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_SET_MSK 0x00000100
10434 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field value. */
10435 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_CLR_MSK 0xfffffeff
10436 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field. */
10437 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_RESET 0x0
10438 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 field value from a register. */
10439 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_GET(value) (((value) & 0x00000100) >> 8)
10440 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 register field value suitable for setting the register. */
10441 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8_SET(value) (((value) << 8) & 0x00000100)
10442 
10443 /*
10444  * Field : bit_9
10445  *
10446  * Field Access Macros:
10447  *
10448  */
10449 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field. */
10450 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_LSB 9
10451 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field. */
10452 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_MSB 9
10453 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field. */
10454 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_WIDTH 1
10455 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field value. */
10456 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_SET_MSK 0x00000200
10457 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field value. */
10458 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_CLR_MSK 0xfffffdff
10459 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field. */
10460 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_RESET 0x0
10461 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 field value from a register. */
10462 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_GET(value) (((value) & 0x00000200) >> 9)
10463 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 register field value suitable for setting the register. */
10464 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9_SET(value) (((value) << 9) & 0x00000200)
10465 
10466 /*
10467  * Field : bit_10
10468  *
10469  * Field Access Macros:
10470  *
10471  */
10472 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field. */
10473 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_LSB 10
10474 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field. */
10475 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_MSB 10
10476 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field. */
10477 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_WIDTH 1
10478 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field value. */
10479 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_SET_MSK 0x00000400
10480 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field value. */
10481 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_CLR_MSK 0xfffffbff
10482 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field. */
10483 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_RESET 0x0
10484 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 field value from a register. */
10485 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_GET(value) (((value) & 0x00000400) >> 10)
10486 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 register field value suitable for setting the register. */
10487 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10_SET(value) (((value) << 10) & 0x00000400)
10488 
10489 /*
10490  * Field : bit_11
10491  *
10492  * Field Access Macros:
10493  *
10494  */
10495 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field. */
10496 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_LSB 11
10497 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field. */
10498 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_MSB 11
10499 /* The width in bits of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field. */
10500 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_WIDTH 1
10501 /* The mask used to set the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field value. */
10502 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_SET_MSK 0x00000800
10503 /* The mask used to clear the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field value. */
10504 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_CLR_MSK 0xfffff7ff
10505 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field. */
10506 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_RESET 0x0
10507 /* Extracts the ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 field value from a register. */
10508 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_GET(value) (((value) & 0x00000800) >> 11)
10509 /* Produces a ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 register field value suitable for setting the register. */
10510 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11_SET(value) (((value) << 11) & 0x00000800)
10511 
10512 #ifndef __ASSEMBLY__
10513 /*
10514  * WARNING: The C register and register group struct declarations are provided for
10515  * convenience and illustrative purposes. They should, however, be used with
10516  * caution as the C language standard provides no guarantees about the alignment or
10517  * atomicity of device memory accesses. The recommended practice for coding device
10518  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10519  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10520  * alt_write_dword() functions for 64 bit registers.
10521  *
10522  * The struct declaration for register ALT_SYSMGR_CORE_SDM_HPS_SPARE.
10523  */
10524 struct ALT_SYSMGR_CORE_SDM_HPS_SPARE_s
10525 {
10526  volatile uint32_t bit_0 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_0 */
10527  volatile uint32_t bit_1 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_1 */
10528  volatile uint32_t bit_2 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_2 */
10529  volatile uint32_t bit_3 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_3 */
10530  volatile uint32_t bit_4 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_4 */
10531  volatile uint32_t bit_5 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_5 */
10532  volatile uint32_t bit_6 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_6 */
10533  volatile uint32_t bit_7 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_7 */
10534  volatile uint32_t bit_8 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_8 */
10535  volatile uint32_t bit_9 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_9 */
10536  volatile uint32_t bit_10 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_10 */
10537  volatile uint32_t bit_11 : 1; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE_BIT_11 */
10538  uint32_t : 20; /* *UNDEFINED* */
10539 };
10540 
10541 /* The typedef declaration for register ALT_SYSMGR_CORE_SDM_HPS_SPARE. */
10542 typedef struct ALT_SYSMGR_CORE_SDM_HPS_SPARE_s ALT_SYSMGR_CORE_SDM_HPS_SPARE_t;
10543 #endif /* __ASSEMBLY__ */
10544 
10545 /* The reset value of the ALT_SYSMGR_CORE_SDM_HPS_SPARE register. */
10546 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_RESET 0x00000000
10547 /* The byte offset of the ALT_SYSMGR_CORE_SDM_HPS_SPARE register from the beginning of the component. */
10548 #define ALT_SYSMGR_CORE_SDM_HPS_SPARE_OFST 0xf4
10549 
10550 /*
10551  * Register : hps_sdm_spare
10552  *
10553  * HPS to SDM spare signals are mapped to a system manager register.
10554  *
10555  * Register Layout
10556  *
10557  * Bits | Access | Reset | Description
10558  * :--------|:-------|:------|:----------------------------------
10559  * [18:0] | RW | 0x0 | ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL
10560  * [31:19] | ??? | 0x0 | *UNDEFINED*
10561  *
10562  */
10563 /*
10564  * Field : val
10565  *
10566  * write to this register will drive the value PSI spare ports.
10567  *
10568  * Field Access Macros:
10569  *
10570  */
10571 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field. */
10572 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_LSB 0
10573 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field. */
10574 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_MSB 18
10575 /* The width in bits of the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field. */
10576 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_WIDTH 19
10577 /* The mask used to set the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field value. */
10578 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_SET_MSK 0x0007ffff
10579 /* The mask used to clear the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field value. */
10580 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_CLR_MSK 0xfff80000
10581 /* The reset value of the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field. */
10582 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_RESET 0x0
10583 /* Extracts the ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL field value from a register. */
10584 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_GET(value) (((value) & 0x0007ffff) >> 0)
10585 /* Produces a ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL register field value suitable for setting the register. */
10586 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL_SET(value) (((value) << 0) & 0x0007ffff)
10587 
10588 #ifndef __ASSEMBLY__
10589 /*
10590  * WARNING: The C register and register group struct declarations are provided for
10591  * convenience and illustrative purposes. They should, however, be used with
10592  * caution as the C language standard provides no guarantees about the alignment or
10593  * atomicity of device memory accesses. The recommended practice for coding device
10594  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10595  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10596  * alt_write_dword() functions for 64 bit registers.
10597  *
10598  * The struct declaration for register ALT_SYSMGR_CORE_HPS_SDM_SPARE.
10599  */
10600 struct ALT_SYSMGR_CORE_HPS_SDM_SPARE_s
10601 {
10602  volatile uint32_t val : 19; /* ALT_SYSMGR_CORE_HPS_SDM_SPARE_VAL */
10603  uint32_t : 13; /* *UNDEFINED* */
10604 };
10605 
10606 /* The typedef declaration for register ALT_SYSMGR_CORE_HPS_SDM_SPARE. */
10607 typedef struct ALT_SYSMGR_CORE_HPS_SDM_SPARE_s ALT_SYSMGR_CORE_HPS_SDM_SPARE_t;
10608 #endif /* __ASSEMBLY__ */
10609 
10610 /* The reset value of the ALT_SYSMGR_CORE_HPS_SDM_SPARE register. */
10611 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_RESET 0x00000000
10612 /* The byte offset of the ALT_SYSMGR_CORE_HPS_SDM_SPARE register from the beginning of the component. */
10613 #define ALT_SYSMGR_CORE_HPS_SDM_SPARE_OFST 0xf8
10614 
10615 /*
10616  * Register : boot_scratch_cold0
10617  *
10618  * Boot scratch register 0
10619  *
10620  * Register Layout
10621  *
10622  * Bits | Access | Reset | Description
10623  * :-------|:-------|:------|:---------------------------------------
10624  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL
10625  *
10626  */
10627 /*
10628  * Field : val
10629  *
10630  * the scratch register value
10631  *
10632  * Field Access Macros:
10633  *
10634  */
10635 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field. */
10636 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_LSB 0
10637 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field. */
10638 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_MSB 31
10639 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field. */
10640 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_WIDTH 32
10641 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field value. */
10642 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_SET_MSK 0xffffffff
10643 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field value. */
10644 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_CLR_MSK 0x00000000
10645 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field. */
10646 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_RESET 0x0
10647 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL field value from a register. */
10648 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10649 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL register field value suitable for setting the register. */
10650 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL_SET(value) (((value) << 0) & 0xffffffff)
10651 
10652 #ifndef __ASSEMBLY__
10653 /*
10654  * WARNING: The C register and register group struct declarations are provided for
10655  * convenience and illustrative purposes. They should, however, be used with
10656  * caution as the C language standard provides no guarantees about the alignment or
10657  * atomicity of device memory accesses. The recommended practice for coding device
10658  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10659  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10660  * alt_write_dword() functions for 64 bit registers.
10661  *
10662  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0.
10663  */
10664 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_s
10665 {
10666  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_VAL */
10667 };
10668 
10669 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0. */
10670 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_t;
10671 #endif /* __ASSEMBLY__ */
10672 
10673 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0 register. */
10674 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_RESET 0x00000000
10675 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0 register from the beginning of the component. */
10676 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_OFST 0x200
10677 
10678 /*
10679  * Register : boot_scratch_cold1
10680  *
10681  * Boot scratch register 1
10682  *
10683  * Register Layout
10684  *
10685  * Bits | Access | Reset | Description
10686  * :-------|:-------|:------|:---------------------------------------
10687  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL
10688  *
10689  */
10690 /*
10691  * Field : val
10692  *
10693  * the scratch register value
10694  *
10695  * Field Access Macros:
10696  *
10697  */
10698 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field. */
10699 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_LSB 0
10700 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field. */
10701 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_MSB 31
10702 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field. */
10703 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_WIDTH 32
10704 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field value. */
10705 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_SET_MSK 0xffffffff
10706 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field value. */
10707 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_CLR_MSK 0x00000000
10708 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field. */
10709 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_RESET 0x0
10710 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL field value from a register. */
10711 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10712 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL register field value suitable for setting the register. */
10713 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL_SET(value) (((value) << 0) & 0xffffffff)
10714 
10715 #ifndef __ASSEMBLY__
10716 /*
10717  * WARNING: The C register and register group struct declarations are provided for
10718  * convenience and illustrative purposes. They should, however, be used with
10719  * caution as the C language standard provides no guarantees about the alignment or
10720  * atomicity of device memory accesses. The recommended practice for coding device
10721  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10722  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10723  * alt_write_dword() functions for 64 bit registers.
10724  *
10725  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1.
10726  */
10727 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_s
10728 {
10729  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_VAL */
10730 };
10731 
10732 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1. */
10733 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_t;
10734 #endif /* __ASSEMBLY__ */
10735 
10736 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1 register. */
10737 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_RESET 0x00000000
10738 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1 register from the beginning of the component. */
10739 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_OFST 0x204
10740 
10741 /*
10742  * Register : boot_scratch_cold2
10743  *
10744  * Boot scratch register 2
10745  *
10746  * Register Layout
10747  *
10748  * Bits | Access | Reset | Description
10749  * :-------|:-------|:------|:---------------------------------------
10750  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL
10751  *
10752  */
10753 /*
10754  * Field : val
10755  *
10756  * the scratch register value
10757  *
10758  * Field Access Macros:
10759  *
10760  */
10761 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field. */
10762 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_LSB 0
10763 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field. */
10764 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_MSB 31
10765 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field. */
10766 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_WIDTH 32
10767 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field value. */
10768 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_SET_MSK 0xffffffff
10769 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field value. */
10770 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_CLR_MSK 0x00000000
10771 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field. */
10772 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_RESET 0x0
10773 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL field value from a register. */
10774 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10775 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL register field value suitable for setting the register. */
10776 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL_SET(value) (((value) << 0) & 0xffffffff)
10777 
10778 #ifndef __ASSEMBLY__
10779 /*
10780  * WARNING: The C register and register group struct declarations are provided for
10781  * convenience and illustrative purposes. They should, however, be used with
10782  * caution as the C language standard provides no guarantees about the alignment or
10783  * atomicity of device memory accesses. The recommended practice for coding device
10784  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10785  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10786  * alt_write_dword() functions for 64 bit registers.
10787  *
10788  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2.
10789  */
10790 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_s
10791 {
10792  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_VAL */
10793 };
10794 
10795 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2. */
10796 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_t;
10797 #endif /* __ASSEMBLY__ */
10798 
10799 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2 register. */
10800 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_RESET 0x00000000
10801 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2 register from the beginning of the component. */
10802 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_OFST 0x208
10803 
10804 /*
10805  * Register : boot_scratch_cold3
10806  *
10807  * Boot scratch register 3
10808  *
10809  * Register Layout
10810  *
10811  * Bits | Access | Reset | Description
10812  * :-------|:-------|:------|:---------------------------------------
10813  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL
10814  *
10815  */
10816 /*
10817  * Field : val
10818  *
10819  * the scratch register value
10820  *
10821  * Field Access Macros:
10822  *
10823  */
10824 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field. */
10825 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_LSB 0
10826 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field. */
10827 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_MSB 31
10828 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field. */
10829 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_WIDTH 32
10830 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field value. */
10831 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_SET_MSK 0xffffffff
10832 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field value. */
10833 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_CLR_MSK 0x00000000
10834 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field. */
10835 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_RESET 0x0
10836 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL field value from a register. */
10837 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10838 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL register field value suitable for setting the register. */
10839 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL_SET(value) (((value) << 0) & 0xffffffff)
10840 
10841 #ifndef __ASSEMBLY__
10842 /*
10843  * WARNING: The C register and register group struct declarations are provided for
10844  * convenience and illustrative purposes. They should, however, be used with
10845  * caution as the C language standard provides no guarantees about the alignment or
10846  * atomicity of device memory accesses. The recommended practice for coding device
10847  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10848  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10849  * alt_write_dword() functions for 64 bit registers.
10850  *
10851  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3.
10852  */
10853 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_s
10854 {
10855  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_VAL */
10856 };
10857 
10858 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3. */
10859 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_t;
10860 #endif /* __ASSEMBLY__ */
10861 
10862 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3 register. */
10863 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_RESET 0x00000000
10864 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3 register from the beginning of the component. */
10865 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_OFST 0x20c
10866 
10867 /*
10868  * Register : boot_scratch_cold4
10869  *
10870  * Boot scratch register 4
10871  *
10872  * Register Layout
10873  *
10874  * Bits | Access | Reset | Description
10875  * :-------|:-------|:------|:---------------------------------------
10876  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL
10877  *
10878  */
10879 /*
10880  * Field : val
10881  *
10882  * the scratch register value
10883  *
10884  * Field Access Macros:
10885  *
10886  */
10887 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field. */
10888 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_LSB 0
10889 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field. */
10890 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_MSB 31
10891 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field. */
10892 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_WIDTH 32
10893 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field value. */
10894 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_SET_MSK 0xffffffff
10895 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field value. */
10896 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_CLR_MSK 0x00000000
10897 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field. */
10898 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_RESET 0x0
10899 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL field value from a register. */
10900 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10901 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL register field value suitable for setting the register. */
10902 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL_SET(value) (((value) << 0) & 0xffffffff)
10903 
10904 #ifndef __ASSEMBLY__
10905 /*
10906  * WARNING: The C register and register group struct declarations are provided for
10907  * convenience and illustrative purposes. They should, however, be used with
10908  * caution as the C language standard provides no guarantees about the alignment or
10909  * atomicity of device memory accesses. The recommended practice for coding device
10910  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10911  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10912  * alt_write_dword() functions for 64 bit registers.
10913  *
10914  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4.
10915  */
10916 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_s
10917 {
10918  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_VAL */
10919 };
10920 
10921 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4. */
10922 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_t;
10923 #endif /* __ASSEMBLY__ */
10924 
10925 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4 register. */
10926 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_RESET 0x00000000
10927 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4 register from the beginning of the component. */
10928 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_OFST 0x210
10929 
10930 /*
10931  * Register : boot_scratch_cold5
10932  *
10933  * Boot scratch register 5
10934  *
10935  * Register Layout
10936  *
10937  * Bits | Access | Reset | Description
10938  * :-------|:-------|:------|:---------------------------------------
10939  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL
10940  *
10941  */
10942 /*
10943  * Field : val
10944  *
10945  * the scratch register value
10946  *
10947  * Field Access Macros:
10948  *
10949  */
10950 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field. */
10951 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_LSB 0
10952 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field. */
10953 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_MSB 31
10954 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field. */
10955 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_WIDTH 32
10956 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field value. */
10957 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_SET_MSK 0xffffffff
10958 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field value. */
10959 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_CLR_MSK 0x00000000
10960 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field. */
10961 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_RESET 0x0
10962 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL field value from a register. */
10963 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_GET(value) (((value) & 0xffffffff) >> 0)
10964 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL register field value suitable for setting the register. */
10965 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL_SET(value) (((value) << 0) & 0xffffffff)
10966 
10967 #ifndef __ASSEMBLY__
10968 /*
10969  * WARNING: The C register and register group struct declarations are provided for
10970  * convenience and illustrative purposes. They should, however, be used with
10971  * caution as the C language standard provides no guarantees about the alignment or
10972  * atomicity of device memory accesses. The recommended practice for coding device
10973  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10974  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10975  * alt_write_dword() functions for 64 bit registers.
10976  *
10977  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5.
10978  */
10979 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_s
10980 {
10981  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_VAL */
10982 };
10983 
10984 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5. */
10985 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_t;
10986 #endif /* __ASSEMBLY__ */
10987 
10988 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5 register. */
10989 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_RESET 0x00000000
10990 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5 register from the beginning of the component. */
10991 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_OFST 0x214
10992 
10993 /*
10994  * Register : boot_scratch_cold6
10995  *
10996  * Boot scratch register 6
10997  *
10998  * Register Layout
10999  *
11000  * Bits | Access | Reset | Description
11001  * :-------|:-------|:------|:---------------------------------------
11002  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL
11003  *
11004  */
11005 /*
11006  * Field : val
11007  *
11008  * the scratch register value
11009  *
11010  * Field Access Macros:
11011  *
11012  */
11013 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field. */
11014 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_LSB 0
11015 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field. */
11016 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_MSB 31
11017 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field. */
11018 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_WIDTH 32
11019 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field value. */
11020 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_SET_MSK 0xffffffff
11021 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field value. */
11022 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_CLR_MSK 0x00000000
11023 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field. */
11024 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_RESET 0x0
11025 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL field value from a register. */
11026 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11027 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL register field value suitable for setting the register. */
11028 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL_SET(value) (((value) << 0) & 0xffffffff)
11029 
11030 #ifndef __ASSEMBLY__
11031 /*
11032  * WARNING: The C register and register group struct declarations are provided for
11033  * convenience and illustrative purposes. They should, however, be used with
11034  * caution as the C language standard provides no guarantees about the alignment or
11035  * atomicity of device memory accesses. The recommended practice for coding device
11036  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11037  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11038  * alt_write_dword() functions for 64 bit registers.
11039  *
11040  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6.
11041  */
11042 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_s
11043 {
11044  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_VAL */
11045 };
11046 
11047 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6. */
11048 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_t;
11049 #endif /* __ASSEMBLY__ */
11050 
11051 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6 register. */
11052 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_RESET 0x00000000
11053 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6 register from the beginning of the component. */
11054 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_OFST 0x218
11055 
11056 /*
11057  * Register : boot_scratch_cold7
11058  *
11059  * Boot scratch register 7
11060  *
11061  * Register Layout
11062  *
11063  * Bits | Access | Reset | Description
11064  * :-------|:-------|:------|:---------------------------------------
11065  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL
11066  *
11067  */
11068 /*
11069  * Field : val
11070  *
11071  * the scratch register value
11072  *
11073  * Field Access Macros:
11074  *
11075  */
11076 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field. */
11077 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_LSB 0
11078 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field. */
11079 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_MSB 31
11080 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field. */
11081 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_WIDTH 32
11082 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field value. */
11083 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_SET_MSK 0xffffffff
11084 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field value. */
11085 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_CLR_MSK 0x00000000
11086 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field. */
11087 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_RESET 0x0
11088 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL field value from a register. */
11089 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11090 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL register field value suitable for setting the register. */
11091 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL_SET(value) (((value) << 0) & 0xffffffff)
11092 
11093 #ifndef __ASSEMBLY__
11094 /*
11095  * WARNING: The C register and register group struct declarations are provided for
11096  * convenience and illustrative purposes. They should, however, be used with
11097  * caution as the C language standard provides no guarantees about the alignment or
11098  * atomicity of device memory accesses. The recommended practice for coding device
11099  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11100  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11101  * alt_write_dword() functions for 64 bit registers.
11102  *
11103  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7.
11104  */
11105 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_s
11106 {
11107  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_VAL */
11108 };
11109 
11110 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7. */
11111 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_t;
11112 #endif /* __ASSEMBLY__ */
11113 
11114 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7 register. */
11115 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_RESET 0x00000000
11116 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7 register from the beginning of the component. */
11117 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_OFST 0x21c
11118 
11119 /*
11120  * Register : boot_scratch_cold8
11121  *
11122  * Boot scratch register 8
11123  *
11124  * Register Layout
11125  *
11126  * Bits | Access | Reset | Description
11127  * :-------|:-------|:------|:---------------------------------------
11128  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL
11129  *
11130  */
11131 /*
11132  * Field : val
11133  *
11134  * the scratch register value
11135  *
11136  * Field Access Macros:
11137  *
11138  */
11139 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field. */
11140 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_LSB 0
11141 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field. */
11142 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_MSB 31
11143 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field. */
11144 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_WIDTH 32
11145 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field value. */
11146 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_SET_MSK 0xffffffff
11147 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field value. */
11148 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_CLR_MSK 0x00000000
11149 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field. */
11150 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_RESET 0x0
11151 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL field value from a register. */
11152 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11153 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL register field value suitable for setting the register. */
11154 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL_SET(value) (((value) << 0) & 0xffffffff)
11155 
11156 #ifndef __ASSEMBLY__
11157 /*
11158  * WARNING: The C register and register group struct declarations are provided for
11159  * convenience and illustrative purposes. They should, however, be used with
11160  * caution as the C language standard provides no guarantees about the alignment or
11161  * atomicity of device memory accesses. The recommended practice for coding device
11162  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11163  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11164  * alt_write_dword() functions for 64 bit registers.
11165  *
11166  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8.
11167  */
11168 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_s
11169 {
11170  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_VAL */
11171 };
11172 
11173 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8. */
11174 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_t;
11175 #endif /* __ASSEMBLY__ */
11176 
11177 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8 register. */
11178 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_RESET 0x00000000
11179 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8 register from the beginning of the component. */
11180 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_OFST 0x220
11181 
11182 /*
11183  * Register : boot_scratch_cold9
11184  *
11185  * Boot scratch register 9
11186  *
11187  * Register Layout
11188  *
11189  * Bits | Access | Reset | Description
11190  * :-------|:-------|:------|:---------------------------------------
11191  * [31:0] | RW | 0x0 | ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL
11192  *
11193  */
11194 /*
11195  * Field : val
11196  *
11197  * the scratch register value
11198  *
11199  * Field Access Macros:
11200  *
11201  */
11202 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field. */
11203 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_LSB 0
11204 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field. */
11205 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_MSB 31
11206 /* The width in bits of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field. */
11207 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_WIDTH 32
11208 /* The mask used to set the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field value. */
11209 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_SET_MSK 0xffffffff
11210 /* The mask used to clear the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field value. */
11211 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_CLR_MSK 0x00000000
11212 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field. */
11213 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_RESET 0x0
11214 /* Extracts the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL field value from a register. */
11215 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_GET(value) (((value) & 0xffffffff) >> 0)
11216 /* Produces a ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL register field value suitable for setting the register. */
11217 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL_SET(value) (((value) << 0) & 0xffffffff)
11218 
11219 #ifndef __ASSEMBLY__
11220 /*
11221  * WARNING: The C register and register group struct declarations are provided for
11222  * convenience and illustrative purposes. They should, however, be used with
11223  * caution as the C language standard provides no guarantees about the alignment or
11224  * atomicity of device memory accesses. The recommended practice for coding device
11225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11227  * alt_write_dword() functions for 64 bit registers.
11228  *
11229  * The struct declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9.
11230  */
11231 struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_s
11232 {
11233  volatile uint32_t val : 32; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_VAL */
11234 };
11235 
11236 /* The typedef declaration for register ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9. */
11237 typedef struct ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_s ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_t;
11238 #endif /* __ASSEMBLY__ */
11239 
11240 /* The reset value of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9 register. */
11241 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_RESET 0x00000000
11242 /* The byte offset of the ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9 register from the beginning of the component. */
11243 #define ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_OFST 0x224
11244 
11245 #ifndef __ASSEMBLY__
11246 /*
11247  * WARNING: The C register and register group struct declarations are provided for
11248  * convenience and illustrative purposes. They should, however, be used with
11249  * caution as the C language standard provides no guarantees about the alignment or
11250  * atomicity of device memory accesses. The recommended practice for coding device
11251  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11252  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11253  * alt_write_dword() functions for 64 bit registers.
11254  *
11255  * The struct declaration for register group ALT_SYSMGR_CORE.
11256  */
11257 struct ALT_SYSMGR_CORE_s
11258 {
11259  volatile ALT_SYSMGR_CORE_SILICONID1_t siliconid1; /* ALT_SYSMGR_CORE_SILICONID1 */
11260  volatile ALT_SYSMGR_CORE_SILICONID2_t siliconid2; /* ALT_SYSMGR_CORE_SILICONID2 */
11261  volatile ALT_SYSMGR_CORE_WDDBG_t wddbg; /* ALT_SYSMGR_CORE_WDDBG */
11262  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
11263  volatile ALT_SYSMGR_CORE_MPU_STATUS_t mpu_status; /* ALT_SYSMGR_CORE_MPU_STATUS */
11264  volatile ALT_SYSMGR_CORE_MPU_ACE_t mpu_ace; /* ALT_SYSMGR_CORE_MPU_ACE */
11265  volatile uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */
11266  volatile ALT_SYSMGR_CORE_DMA_t dma; /* ALT_SYSMGR_CORE_DMA */
11267  volatile ALT_SYSMGR_CORE_DMA_PERIPH_t dma_periph; /* ALT_SYSMGR_CORE_DMA_PERIPH */
11268  volatile ALT_SYSMGR_CORE_SDMMC_t sdmmc; /* ALT_SYSMGR_CORE_SDMMC */
11269  volatile ALT_SYSMGR_CORE_SDMMC_L3MASTER_t sdmmc_l3master; /* ALT_SYSMGR_CORE_SDMMC_L3MASTER */
11270  volatile ALT_SYSMGR_CORE_NAND_BOOTSTRAP_t nand_bootstrap; /* ALT_SYSMGR_CORE_NAND_BOOTSTRAP */
11271  volatile ALT_SYSMGR_CORE_NAND_L3MASTER_t nand_l3master; /* ALT_SYSMGR_CORE_NAND_L3MASTER */
11272  volatile ALT_SYSMGR_CORE_USB0_L3MASTER_t usb0_l3master; /* ALT_SYSMGR_CORE_USB0_L3MASTER */
11273  volatile ALT_SYSMGR_CORE_USB1_L3MASTER_t usb1_l3master; /* ALT_SYSMGR_CORE_USB1_L3MASTER */
11274  volatile ALT_SYSMGR_CORE_EMAC_GLOBAL_t emac_global; /* ALT_SYSMGR_CORE_EMAC_GLOBAL */
11275  volatile ALT_SYSMGR_CORE_EMAC0_t emac0; /* ALT_SYSMGR_CORE_EMAC0 */
11276  volatile ALT_SYSMGR_CORE_EMAC1_t emac1; /* ALT_SYSMGR_CORE_EMAC1 */
11277  volatile ALT_SYSMGR_CORE_EMAC2_t emac2; /* ALT_SYSMGR_CORE_EMAC2 */
11278  volatile ALT_SYSMGR_CORE_EMAC0_ACE_t emac0_ace; /* ALT_SYSMGR_CORE_EMAC0_ACE */
11279  volatile ALT_SYSMGR_CORE_EMAC1_ACE_t emac1_ace; /* ALT_SYSMGR_CORE_EMAC1_ACE */
11280  volatile ALT_SYSMGR_CORE_EMAC2_ACE_t emac2_ace; /* ALT_SYSMGR_CORE_EMAC2_ACE */
11281  volatile ALT_SYSMGR_CORE_NAND_AXUSER_t nand_axuser; /* ALT_SYSMGR_CORE_NAND_AXUSER */
11282  volatile uint32_t _pad_0x60_0x67[2]; /* *UNDEFINED* */
11283  volatile ALT_SYSMGR_CORE_FPGAINTF_EN_1_t fpgaintf_en_1; /* ALT_SYSMGR_CORE_FPGAINTF_EN_1 */
11284  volatile ALT_SYSMGR_CORE_FPGAINTF_EN_2_t fpgaintf_en_2; /* ALT_SYSMGR_CORE_FPGAINTF_EN_2 */
11285  volatile ALT_SYSMGR_CORE_FPGAINTF_EN_3_t fpgaintf_en_3; /* ALT_SYSMGR_CORE_FPGAINTF_EN_3 */
11286  volatile ALT_SYSMGR_CORE_DMA_L3MASTER_t dma_l3master; /* ALT_SYSMGR_CORE_DMA_L3MASTER */
11287  volatile ALT_SYSMGR_CORE_ETR_L3MASTER_t etr_l3master; /* ALT_SYSMGR_CORE_ETR_L3MASTER */
11288  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
11289  volatile ALT_SYSMGR_CORE_SEC_CTRL_SLT_t sec_ctrl_slt; /* ALT_SYSMGR_CORE_SEC_CTRL_SLT */
11290  volatile ALT_SYSMGR_CORE_OSC_TRIM_t osc_trim; /* ALT_SYSMGR_CORE_OSC_TRIM */
11291  volatile uint32_t _pad_0x88_0x8f[2]; /* *UNDEFINED* */
11292  volatile ALT_SYSMGR_CORE_ECC_INTMASK_VALUE_t ecc_intmask_value; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE */
11293  volatile ALT_SYSMGR_CORE_ECC_INTMASK_SET_t ecc_intmask_set; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET */
11294  volatile ALT_SYSMGR_CORE_ECC_INTMASK_CLR_t ecc_intmask_clr; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR */
11295  volatile ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR_t ecc_intstatus_serr; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR */
11296  volatile ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR_t ecc_intstatus_derr; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR */
11297  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
11298  volatile ALT_SYSMGR_CORE_NOC_ADDR_REMAP_t noc_addr_remap; /* ALT_SYSMGR_CORE_NOC_ADDR_REMAP */
11299  volatile ALT_SYSMGR_CORE_HMC_CLK_t hmc_clk; /* ALT_SYSMGR_CORE_HMC_CLK */
11300  volatile ALT_SYSMGR_CORE_IO_PA_CTRL_t io_pa_ctrl; /* ALT_SYSMGR_CORE_IO_PA_CTRL */
11301  volatile uint32_t _pad_0xbc_0xbf; /* *UNDEFINED* */
11302  volatile ALT_SYSMGR_CORE_NOC_TIMEOUT_t noc_timeout; /* ALT_SYSMGR_CORE_NOC_TIMEOUT */
11303  volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_SET_t noc_idlereq_set; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_SET */
11304  volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR_t noc_idlereq_clr; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR */
11305  volatile ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE_t noc_idlereq_value; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE */
11306  volatile ALT_SYSMGR_CORE_NOC_IDLEACK_t noc_idleack; /* ALT_SYSMGR_CORE_NOC_IDLEACK */
11307  volatile ALT_SYSMGR_CORE_NOC_IDLESTATUS_t noc_idlestatus; /* ALT_SYSMGR_CORE_NOC_IDLESTATUS */
11308  volatile ALT_SYSMGR_CORE_FPGA2SOC_CTRL_t fpga2soc_ctrl; /* ALT_SYSMGR_CORE_FPGA2SOC_CTRL */
11309  volatile ALT_SYSMGR_CORE_FPGA_CONFIG_t fpga_config; /* ALT_SYSMGR_CORE_FPGA_CONFIG */
11310  volatile ALT_SYSMGR_CORE_IOCSRCLK_GATE_t iocsrclk_gate; /* ALT_SYSMGR_CORE_IOCSRCLK_GATE */
11311  volatile ALT_SYSMGR_CORE_GPO_t gpo; /* ALT_SYSMGR_CORE_GPO */
11312  volatile ALT_SYSMGR_CORE_GPI_t gpi; /* ALT_SYSMGR_CORE_GPI */
11313  volatile uint32_t _pad_0xec_0xef; /* *UNDEFINED* */
11314  volatile ALT_SYSMGR_CORE_MPU_t mpu; /* ALT_SYSMGR_CORE_MPU */
11315  volatile ALT_SYSMGR_CORE_SDM_HPS_SPARE_t sdm_hps_spare; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE */
11316  volatile ALT_SYSMGR_CORE_HPS_SDM_SPARE_t hps_sdm_spare; /* ALT_SYSMGR_CORE_HPS_SDM_SPARE */
11317  volatile uint32_t _pad_0xfc_0x1ff[65]; /* *UNDEFINED* */
11318  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0_t boot_scratch_cold0; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0 */
11319  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1_t boot_scratch_cold1; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1 */
11320  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2_t boot_scratch_cold2; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2 */
11321  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3_t boot_scratch_cold3; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3 */
11322  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4_t boot_scratch_cold4; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4 */
11323  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5_t boot_scratch_cold5; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5 */
11324  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6_t boot_scratch_cold6; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6 */
11325  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7_t boot_scratch_cold7; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7 */
11326  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8_t boot_scratch_cold8; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8 */
11327  volatile ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9_t boot_scratch_cold9; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9 */
11328  volatile uint32_t _pad_0x228_0x500[182]; /* *UNDEFINED* */
11329 };
11330 
11331 /* The typedef declaration for register group ALT_SYSMGR_CORE. */
11332 typedef struct ALT_SYSMGR_CORE_s ALT_SYSMGR_CORE_t;
11333 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_CORE. */
11334 struct ALT_SYSMGR_CORE_raw_s
11335 {
11336  volatile uint32_t siliconid1; /* ALT_SYSMGR_CORE_SILICONID1 */
11337  volatile uint32_t siliconid2; /* ALT_SYSMGR_CORE_SILICONID2 */
11338  volatile uint32_t wddbg; /* ALT_SYSMGR_CORE_WDDBG */
11339  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
11340  volatile uint32_t mpu_status; /* ALT_SYSMGR_CORE_MPU_STATUS */
11341  volatile uint32_t mpu_ace; /* ALT_SYSMGR_CORE_MPU_ACE */
11342  volatile uint32_t _pad_0x18_0x1f[2]; /* *UNDEFINED* */
11343  volatile uint32_t dma; /* ALT_SYSMGR_CORE_DMA */
11344  volatile uint32_t dma_periph; /* ALT_SYSMGR_CORE_DMA_PERIPH */
11345  volatile uint32_t sdmmc; /* ALT_SYSMGR_CORE_SDMMC */
11346  volatile uint32_t sdmmc_l3master; /* ALT_SYSMGR_CORE_SDMMC_L3MASTER */
11347  volatile uint32_t nand_bootstrap; /* ALT_SYSMGR_CORE_NAND_BOOTSTRAP */
11348  volatile uint32_t nand_l3master; /* ALT_SYSMGR_CORE_NAND_L3MASTER */
11349  volatile uint32_t usb0_l3master; /* ALT_SYSMGR_CORE_USB0_L3MASTER */
11350  volatile uint32_t usb1_l3master; /* ALT_SYSMGR_CORE_USB1_L3MASTER */
11351  volatile uint32_t emac_global; /* ALT_SYSMGR_CORE_EMAC_GLOBAL */
11352  volatile uint32_t emac0; /* ALT_SYSMGR_CORE_EMAC0 */
11353  volatile uint32_t emac1; /* ALT_SYSMGR_CORE_EMAC1 */
11354  volatile uint32_t emac2; /* ALT_SYSMGR_CORE_EMAC2 */
11355  volatile uint32_t emac0_ace; /* ALT_SYSMGR_CORE_EMAC0_ACE */
11356  volatile uint32_t emac1_ace; /* ALT_SYSMGR_CORE_EMAC1_ACE */
11357  volatile uint32_t emac2_ace; /* ALT_SYSMGR_CORE_EMAC2_ACE */
11358  volatile uint32_t nand_axuser; /* ALT_SYSMGR_CORE_NAND_AXUSER */
11359  volatile uint32_t _pad_0x60_0x67[2]; /* *UNDEFINED* */
11360  volatile uint32_t fpgaintf_en_1; /* ALT_SYSMGR_CORE_FPGAINTF_EN_1 */
11361  volatile uint32_t fpgaintf_en_2; /* ALT_SYSMGR_CORE_FPGAINTF_EN_2 */
11362  volatile uint32_t fpgaintf_en_3; /* ALT_SYSMGR_CORE_FPGAINTF_EN_3 */
11363  volatile uint32_t dma_l3master; /* ALT_SYSMGR_CORE_DMA_L3MASTER */
11364  volatile uint32_t etr_l3master; /* ALT_SYSMGR_CORE_ETR_L3MASTER */
11365  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
11366  volatile uint32_t sec_ctrl_slt; /* ALT_SYSMGR_CORE_SEC_CTRL_SLT */
11367  volatile uint32_t osc_trim; /* ALT_SYSMGR_CORE_OSC_TRIM */
11368  volatile uint32_t _pad_0x88_0x8f[2]; /* *UNDEFINED* */
11369  volatile uint32_t ecc_intmask_value; /* ALT_SYSMGR_CORE_ECC_INTMASK_VALUE */
11370  volatile uint32_t ecc_intmask_set; /* ALT_SYSMGR_CORE_ECC_INTMASK_SET */
11371  volatile uint32_t ecc_intmask_clr; /* ALT_SYSMGR_CORE_ECC_INTMASK_CLR */
11372  volatile uint32_t ecc_intstatus_serr; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_SERR */
11373  volatile uint32_t ecc_intstatus_derr; /* ALT_SYSMGR_CORE_ECC_INTSTATUS_DERR */
11374  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
11375  volatile uint32_t noc_addr_remap; /* ALT_SYSMGR_CORE_NOC_ADDR_REMAP */
11376  volatile uint32_t hmc_clk; /* ALT_SYSMGR_CORE_HMC_CLK */
11377  volatile uint32_t io_pa_ctrl; /* ALT_SYSMGR_CORE_IO_PA_CTRL */
11378  volatile uint32_t _pad_0xbc_0xbf; /* *UNDEFINED* */
11379  volatile uint32_t noc_timeout; /* ALT_SYSMGR_CORE_NOC_TIMEOUT */
11380  volatile uint32_t noc_idlereq_set; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_SET */
11381  volatile uint32_t noc_idlereq_clr; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_CLR */
11382  volatile uint32_t noc_idlereq_value; /* ALT_SYSMGR_CORE_NOC_IDLEREQ_VALUE */
11383  volatile uint32_t noc_idleack; /* ALT_SYSMGR_CORE_NOC_IDLEACK */
11384  volatile uint32_t noc_idlestatus; /* ALT_SYSMGR_CORE_NOC_IDLESTATUS */
11385  volatile uint32_t fpga2soc_ctrl; /* ALT_SYSMGR_CORE_FPGA2SOC_CTRL */
11386  volatile uint32_t fpga_config; /* ALT_SYSMGR_CORE_FPGA_CONFIG */
11387  volatile uint32_t iocsrclk_gate; /* ALT_SYSMGR_CORE_IOCSRCLK_GATE */
11388  volatile uint32_t gpo; /* ALT_SYSMGR_CORE_GPO */
11389  volatile uint32_t gpi; /* ALT_SYSMGR_CORE_GPI */
11390  volatile uint32_t _pad_0xec_0xef; /* *UNDEFINED* */
11391  volatile uint32_t mpu; /* ALT_SYSMGR_CORE_MPU */
11392  volatile uint32_t sdm_hps_spare; /* ALT_SYSMGR_CORE_SDM_HPS_SPARE */
11393  volatile uint32_t hps_sdm_spare; /* ALT_SYSMGR_CORE_HPS_SDM_SPARE */
11394  volatile uint32_t _pad_0xfc_0x1ff[65]; /* *UNDEFINED* */
11395  volatile uint32_t boot_scratch_cold0; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD0 */
11396  volatile uint32_t boot_scratch_cold1; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD1 */
11397  volatile uint32_t boot_scratch_cold2; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD2 */
11398  volatile uint32_t boot_scratch_cold3; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD3 */
11399  volatile uint32_t boot_scratch_cold4; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD4 */
11400  volatile uint32_t boot_scratch_cold5; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD5 */
11401  volatile uint32_t boot_scratch_cold6; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD6 */
11402  volatile uint32_t boot_scratch_cold7; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD7 */
11403  volatile uint32_t boot_scratch_cold8; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD8 */
11404  volatile uint32_t boot_scratch_cold9; /* ALT_SYSMGR_CORE_BOOT_SCRATCH_COLD9 */
11405  volatile uint32_t _pad_0x228_0x500[182]; /* *UNDEFINED* */
11406 };
11407 
11408 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_CORE. */
11409 typedef struct ALT_SYSMGR_CORE_raw_s ALT_SYSMGR_CORE_raw_t;
11410 #endif /* __ASSEMBLY__ */
11411 
11412 
11413 #ifdef __cplusplus
11414 }
11415 #endif /* __cplusplus */
11416 #endif /* __ALT_SOCAL_SYSMGR_H__ */
11417