35 #ifndef __ALT_SOCAL_NOC_MPU_DDR_H__
36 #define __ALT_SOCAL_NOC_MPU_DDR_H__
72 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_LSB 0
74 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_MSB 7
76 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_WIDTH 8
78 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET_MSK 0x000000ff
80 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_CLR_MSK 0xffffff00
82 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_RESET 0x6
84 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
86 #define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
97 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_LSB 8
99 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_MSB 31
101 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_WIDTH 24
103 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET_MSK 0xffffff00
105 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_CLR_MSK 0x000000ff
107 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_RESET 0xfa9ecc
109 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
111 #define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
124 struct ALT_NOC_MPU_DDR_T_PRB_COREID_s
126 const uint32_t CORETYPEID : 8;
127 const uint32_t CORECHECKSUM : 24;
131 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_COREID_s ALT_NOC_MPU_DDR_T_PRB_COREID_t;
135 #define ALT_NOC_MPU_DDR_T_PRB_COREID_RESET 0xfa9ecc06
137 #define ALT_NOC_MPU_DDR_T_PRB_COREID_OFST 0x0
159 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_LSB 0
161 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_MSB 7
163 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_WIDTH 8
165 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET_MSK 0x000000ff
167 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_CLR_MSK 0xffffff00
169 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_RESET 0x0
171 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
173 #define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
185 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_LSB 8
187 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_MSB 31
189 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_WIDTH 24
191 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET_MSK 0xffffff00
193 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_CLR_MSK 0x000000ff
195 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_RESET 0x129ff
197 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
199 #define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
212 struct ALT_NOC_MPU_DDR_T_PRB_REVID_s
214 const uint32_t USERID : 8;
215 const uint32_t FLEXNOCID : 24;
219 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_REVID_s ALT_NOC_MPU_DDR_T_PRB_REVID_t;
223 #define ALT_NOC_MPU_DDR_T_PRB_REVID_RESET 0x0129ff00
225 #define ALT_NOC_MPU_DDR_T_PRB_REVID_OFST 0x4
259 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_LSB 0
261 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_MSB 0
263 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_WIDTH 1
265 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET_MSK 0x00000001
267 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_CLR_MSK 0xfffffffe
269 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_RESET 0x0
271 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
273 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
285 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_LSB 1
287 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_MSB 1
289 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_WIDTH 1
291 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET_MSK 0x00000002
293 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
295 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_RESET 0x0
297 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
299 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
311 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_LSB 2
313 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_MSB 2
315 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_WIDTH 1
317 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET_MSK 0x00000004
319 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
321 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_RESET 0x0
323 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
325 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
339 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_LSB 3
341 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_MSB 3
343 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_WIDTH 1
345 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET_MSK 0x00000008
347 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_CLR_MSK 0xfffffff7
349 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_RESET 0x0
351 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
353 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
366 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_LSB 4
368 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_MSB 4
370 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_WIDTH 1
372 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET_MSK 0x00000010
374 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
376 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_RESET 0x0
378 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
380 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
395 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_LSB 5
397 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_MSB 5
399 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_WIDTH 1
401 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
403 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
405 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_RESET 0x0
407 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
409 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
422 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_LSB 6
424 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_MSB 6
426 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_WIDTH 1
428 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
430 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
432 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_RESET 0x0
434 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
436 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
451 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
453 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
455 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
457 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
459 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
461 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
463 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
465 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
478 struct ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s
481 uint32_t TRACEEN : 1;
482 uint32_t PAYLOADEN : 1;
484 uint32_t ALARMEN : 1;
485 uint32_t STATCONDDUMP : 1;
486 uint32_t INTRUSIVEMODE : 1;
487 uint32_t FILTBYTEALWAYSCHAINABLEEN : 1;
492 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t;
496 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_RESET 0x00000000
498 #define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_OFST 0x8
520 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_LSB 0
522 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_MSB 0
524 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_WIDTH 1
526 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET_MSK 0x00000001
528 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
530 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_RESET 0x0
532 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
534 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
544 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_LSB 1
546 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_MSB 1
548 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_WIDTH 1
550 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET_MSK 0x00000002
552 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_CLR_MSK 0xfffffffd
554 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_RESET 0x0
556 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
558 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
571 struct ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s
573 uint32_t GLOBALEN : 1;
574 const uint32_t ACTIVE : 1;
579 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t;
583 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_RESET 0x00000000
585 #define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_OFST 0xc
612 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_LSB 0
614 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_MSB 15
616 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_WIDTH 16
618 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET_MSK 0x0000ffff
620 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_CLR_MSK 0xffff0000
622 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_RESET 0x0
624 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000ffff) >> 0)
626 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000ffff)
639 struct ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s
641 uint32_t FILTERLUT : 16;
646 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t;
650 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_RESET 0x00000000
652 #define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_OFST 0x14
680 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_LSB 0
682 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_MSB 4
684 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_WIDTH 5
686 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x0000001f
688 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xffffffe0
690 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_RESET 0x0
692 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x0000001f) >> 0)
694 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x0000001f)
707 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s
709 uint32_t TRACEALARMEN : 5;
714 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t;
718 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_RESET 0x00000000
720 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_OFST 0x18
747 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
749 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_MSB 4
751 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 5
753 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x0000001f
755 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xffffffe0
757 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
759 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x0000001f) >> 0)
761 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x0000001f)
774 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s
776 const uint32_t TRACEALARMSTATUS : 5;
781 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t;
785 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_RESET 0x00000000
787 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_OFST 0x1c
813 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_LSB 0
815 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_MSB 4
817 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5
819 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f
821 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0
823 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
825 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0)
827 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f)
840 struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s
842 uint32_t TRACEALARMCLR : 5;
847 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t;
851 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_RESET 0x00000000
853 #define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_OFST 0x20
883 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_LSB 0
885 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_MSB 4
887 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_WIDTH 5
889 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
891 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
893 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_RESET 0x0
895 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
897 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
910 struct ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s
912 uint32_t STATPERIOD : 5;
917 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t;
921 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_RESET 0x00000000
923 #define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_OFST 0x24
949 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_LSB 0
951 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_MSB 0
953 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_WIDTH 1
955 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET_MSK 0x00000001
957 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_CLR_MSK 0xfffffffe
959 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_RESET 0x0
961 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
963 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
976 struct ALT_NOC_MPU_DDR_T_PRB_STATGO_s
983 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATGO_s ALT_NOC_MPU_DDR_T_PRB_STATGO_t;
987 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_RESET 0x00000000
989 #define ALT_NOC_MPU_DDR_T_PRB_STATGO_OFST 0x28
1014 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_LSB 0
1016 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_MSB 31
1018 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_WIDTH 32
1020 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1022 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1024 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_RESET 0x0
1026 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1028 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1030 #ifndef __ASSEMBLY__
1041 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s
1043 uint32_t STATALARMMIN : 32;
1047 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t;
1051 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_RESET 0x00000000
1053 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_OFST 0x2c
1078 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_LSB 0
1080 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_MSB 31
1082 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_WIDTH 32
1084 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1086 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1088 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_RESET 0x0
1090 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1092 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1094 #ifndef __ASSEMBLY__
1105 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s
1107 uint32_t STATALARMMAX : 32;
1111 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t;
1115 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_RESET 0x00000000
1117 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_OFST 0x30
1144 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_LSB 0
1146 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_MSB 0
1148 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_WIDTH 1
1150 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
1152 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
1154 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_RESET 0x0
1156 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
1158 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
1160 #ifndef __ASSEMBLY__
1171 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s
1173 const uint32_t STATALARMSTATUS : 1;
1178 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t;
1182 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_RESET 0x00000000
1184 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_OFST 0x34
1210 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_LSB 0
1212 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_MSB 0
1214 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_WIDTH 1
1216 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1218 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1220 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_RESET 0x0
1222 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1224 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1226 #ifndef __ASSEMBLY__
1237 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s
1239 uint32_t STATALARMCLR : 1;
1244 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t;
1248 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_RESET 0x00000000
1250 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_OFST 0x38
1274 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_LSB 0
1276 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_MSB 0
1278 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_WIDTH 1
1280 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1282 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1284 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_RESET 0x1
1286 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1288 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1290 #ifndef __ASSEMBLY__
1301 struct ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s
1303 uint32_t STATALARMEN : 1;
1308 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t;
1312 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_RESET 0x00000001
1314 #define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_OFST 0x3c
1338 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
1340 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
1342 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
1344 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
1346 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
1348 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
1350 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
1352 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
1354 #ifndef __ASSEMBLY__
1365 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s
1367 uint32_t FILTERS_0_ROUTEIDBASE : 19;
1372 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t;
1376 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_RESET 0x00000000
1378 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_OFST 0x44
1403 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
1405 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
1407 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
1409 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
1411 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
1413 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
1415 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
1417 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
1419 #ifndef __ASSEMBLY__
1430 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s
1432 uint32_t FILTERS_0_ROUTEIDMASK : 19;
1437 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t;
1441 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_RESET 0x00000000
1443 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_OFST 0x48
1465 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
1467 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
1469 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
1471 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1473 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1475 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
1477 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1481 #ifndef __ASSEMBLY__
1492 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s
1494 uint32_t FILTERS_0_ADDRBASE_LOW : 32;
1498 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t;
1502 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
1504 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_OFST 0x4c
1531 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
1533 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
1535 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
1537 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
1539 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1541 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
1543 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1545 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1547 #ifndef __ASSEMBLY__
1558 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s
1560 uint32_t FILTERS_0_WINDOWSIZE : 6;
1565 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t;
1569 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_RESET 0x00000000
1571 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_OFST 0x54
1594 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
1596 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
1598 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
1600 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
1602 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
1604 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
1606 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1608 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1610 #ifndef __ASSEMBLY__
1621 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s
1623 uint32_t FILTERS_0_SECURITYBASE : 3;
1628 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t;
1632 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_RESET 0x00000000
1634 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_OFST 0x58
1659 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
1661 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
1663 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
1665 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
1667 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
1669 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
1671 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1673 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1675 #ifndef __ASSEMBLY__
1686 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s
1688 uint32_t FILTERS_0_SECURITYMASK : 3;
1693 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t;
1697 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_RESET 0x00000000
1699 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_OFST 0x5c
1727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_LSB 0
1729 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_MSB 0
1731 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_WIDTH 1
1733 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
1735 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1737 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_RESET 0x0
1739 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1741 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1752 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_LSB 1
1754 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_MSB 1
1756 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_WIDTH 1
1758 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
1760 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1762 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_RESET 0x0
1764 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1766 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1777 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_LSB 2
1779 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_MSB 2
1781 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_WIDTH 1
1783 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1785 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1787 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_RESET 0x0
1789 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1791 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1802 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_LSB 3
1804 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_MSB 3
1806 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_WIDTH 1
1808 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
1810 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1812 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_RESET 0x0
1814 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1816 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1818 #ifndef __ASSEMBLY__
1829 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s
1833 uint32_t LOCKEN : 1;
1839 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t;
1843 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RESET 0x00000000
1845 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_OFST 0x60
1871 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_LSB 0
1873 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_MSB 0
1875 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_WIDTH 1
1877 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
1879 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
1881 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_RESET 0x0
1883 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1885 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
1896 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_LSB 1
1898 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_MSB 1
1900 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_WIDTH 1
1902 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
1904 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
1906 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_RESET 0x0
1908 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1910 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1912 #ifndef __ASSEMBLY__
1923 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s
1931 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t;
1935 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RESET 0x00000000
1937 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_OFST 0x64
1961 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_LSB 0
1963 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_MSB 3
1965 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
1967 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
1969 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
1971 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
1973 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
1975 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
1977 #ifndef __ASSEMBLY__
1988 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s
1990 uint32_t FILTERS_0_LENGTH : 4;
1995 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t;
1999 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_RESET 0x00000000
2001 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_OFST 0x68
2026 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
2028 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
2030 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
2032 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
2034 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
2036 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
2038 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2040 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2042 #ifndef __ASSEMBLY__
2053 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s
2055 uint32_t FILTERS_0_URGENCY : 2;
2060 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t;
2064 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_RESET 0x00000000
2066 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_OFST 0x6c
2090 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
2092 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
2094 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
2096 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
2098 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
2100 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
2102 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2104 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2106 #ifndef __ASSEMBLY__
2117 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s
2119 uint32_t FILTERS_1_ROUTEIDBASE : 19;
2124 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t;
2128 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_RESET 0x00000000
2130 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_OFST 0x80
2155 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
2157 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
2159 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
2161 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
2163 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
2165 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
2167 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2169 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2171 #ifndef __ASSEMBLY__
2182 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s
2184 uint32_t FILTERS_1_ROUTEIDMASK : 19;
2189 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t;
2193 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_RESET 0x00000000
2195 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_OFST 0x84
2217 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
2219 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
2221 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
2223 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2225 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2227 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
2229 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2233 #ifndef __ASSEMBLY__
2244 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s
2246 uint32_t FILTERS_1_ADDRBASE_LOW : 32;
2250 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t;
2254 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
2256 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_OFST 0x88
2283 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
2285 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
2287 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
2289 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
2291 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2293 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
2295 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2297 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2299 #ifndef __ASSEMBLY__
2310 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s
2312 uint32_t FILTERS_1_WINDOWSIZE : 6;
2317 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t;
2321 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_RESET 0x00000000
2323 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_OFST 0x90
2346 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
2348 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
2350 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
2352 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
2354 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
2356 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
2358 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
2360 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
2362 #ifndef __ASSEMBLY__
2373 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s
2375 uint32_t FILTERS_1_SECURITYBASE : 3;
2380 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t;
2384 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_RESET 0x00000000
2386 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_OFST 0x94
2411 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
2413 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
2415 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
2417 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
2419 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
2421 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
2423 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
2425 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
2427 #ifndef __ASSEMBLY__
2438 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s
2440 uint32_t FILTERS_1_SECURITYMASK : 3;
2445 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t;
2449 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_RESET 0x00000000
2451 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_OFST 0x98
2479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_LSB 0
2481 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_MSB 0
2483 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_WIDTH 1
2485 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
2487 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2489 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_RESET 0x0
2491 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2493 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2504 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_LSB 1
2506 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_MSB 1
2508 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_WIDTH 1
2510 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
2512 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2514 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_RESET 0x0
2516 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2518 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2529 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_LSB 2
2531 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_MSB 2
2533 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_WIDTH 1
2535 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2537 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2539 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_RESET 0x0
2541 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2543 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2554 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_LSB 3
2556 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_MSB 3
2558 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_WIDTH 1
2560 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
2562 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2564 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_RESET 0x0
2566 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2568 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2570 #ifndef __ASSEMBLY__
2581 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s
2585 uint32_t LOCKEN : 1;
2591 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t;
2595 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RESET 0x00000000
2597 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_OFST 0x9c
2623 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_LSB 0
2625 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_MSB 0
2627 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_WIDTH 1
2629 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
2631 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
2633 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_RESET 0x0
2635 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2637 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
2648 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_LSB 1
2650 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_MSB 1
2652 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_WIDTH 1
2654 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
2656 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
2658 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_RESET 0x0
2660 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2662 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2664 #ifndef __ASSEMBLY__
2675 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s
2683 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t;
2687 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RESET 0x00000000
2689 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_OFST 0xa0
2713 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_LSB 0
2715 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_MSB 3
2717 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
2719 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
2721 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
2723 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
2725 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
2729 #ifndef __ASSEMBLY__
2740 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s
2742 uint32_t FILTERS_1_LENGTH : 4;
2747 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t;
2751 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_RESET 0x00000000
2753 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_OFST 0xa4
2778 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
2780 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
2782 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
2784 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
2786 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
2788 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
2790 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2792 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2794 #ifndef __ASSEMBLY__
2805 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s
2807 uint32_t FILTERS_1_URGENCY : 2;
2812 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t;
2816 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_RESET 0x00000000
2818 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_OFST 0xa8
2842 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_LSB 0
2844 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_MSB 18
2846 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_WIDTH 19
2848 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET_MSK 0x0007ffff
2850 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_CLR_MSK 0xfff80000
2852 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_RESET 0x0
2854 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2856 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2858 #ifndef __ASSEMBLY__
2869 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s
2871 uint32_t FILTERS_2_ROUTEIDBASE : 19;
2876 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t;
2880 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_RESET 0x00000000
2882 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_OFST 0xbc
2907 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_LSB 0
2909 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_MSB 18
2911 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_WIDTH 19
2913 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET_MSK 0x0007ffff
2915 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_CLR_MSK 0xfff80000
2917 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_RESET 0x0
2919 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2921 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2923 #ifndef __ASSEMBLY__
2934 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s
2936 uint32_t FILTERS_2_ROUTEIDMASK : 19;
2941 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t;
2945 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_RESET 0x00000000
2947 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_OFST 0xc0
2969 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_LSB 0
2971 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_MSB 31
2973 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_WIDTH 32
2975 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET_MSK 0xffffffff
2977 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_CLR_MSK 0x00000000
2979 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_RESET 0x0
2981 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2983 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2985 #ifndef __ASSEMBLY__
2996 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s
2998 uint32_t FILTERS_2_ADDRBASE_LOW : 32;
3002 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t;
3006 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_RESET 0x00000000
3008 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_OFST 0xc4
3035 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_LSB 0
3037 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_MSB 5
3039 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_WIDTH 6
3041 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET_MSK 0x0000003f
3043 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_CLR_MSK 0xffffffc0
3045 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_RESET 0x0
3047 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3049 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3051 #ifndef __ASSEMBLY__
3062 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s
3064 uint32_t FILTERS_2_WINDOWSIZE : 6;
3069 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t;
3073 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_RESET 0x00000000
3075 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_OFST 0xcc
3098 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_LSB 0
3100 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_MSB 2
3102 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_WIDTH 3
3104 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET_MSK 0x00000007
3106 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_CLR_MSK 0xfffffff8
3108 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_RESET 0x0
3110 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3112 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3114 #ifndef __ASSEMBLY__
3125 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s
3127 uint32_t FILTERS_2_SECURITYBASE : 3;
3132 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t;
3136 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_RESET 0x00000000
3138 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_OFST 0xd0
3163 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_LSB 0
3165 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_MSB 2
3167 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_WIDTH 3
3169 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET_MSK 0x00000007
3171 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_CLR_MSK 0xfffffff8
3173 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_RESET 0x0
3175 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3177 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3179 #ifndef __ASSEMBLY__
3190 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s
3192 uint32_t FILTERS_2_SECURITYMASK : 3;
3197 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t;
3201 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_RESET 0x00000000
3203 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_OFST 0xd4
3231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_LSB 0
3233 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_MSB 0
3235 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_WIDTH 1
3237 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET_MSK 0x00000001
3239 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_CLR_MSK 0xfffffffe
3241 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_RESET 0x0
3243 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3245 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3256 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_LSB 1
3258 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_MSB 1
3260 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_WIDTH 1
3262 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET_MSK 0x00000002
3264 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_CLR_MSK 0xfffffffd
3266 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_RESET 0x0
3268 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
3270 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
3281 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_LSB 2
3283 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_MSB 2
3285 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_WIDTH 1
3287 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET_MSK 0x00000004
3289 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
3291 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_RESET 0x0
3293 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
3295 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
3306 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_LSB 3
3308 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_MSB 3
3310 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_WIDTH 1
3312 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET_MSK 0x00000008
3314 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_CLR_MSK 0xfffffff7
3316 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_RESET 0x0
3318 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
3320 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
3322 #ifndef __ASSEMBLY__
3333 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s
3337 uint32_t LOCKEN : 1;
3343 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t;
3347 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RESET 0x00000000
3349 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_OFST 0xd8
3375 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_LSB 0
3377 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_MSB 0
3379 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_WIDTH 1
3381 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET_MSK 0x00000001
3383 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_CLR_MSK 0xfffffffe
3385 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_RESET 0x0
3387 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
3389 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
3400 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_LSB 1
3402 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_MSB 1
3404 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_WIDTH 1
3406 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET_MSK 0x00000002
3408 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_CLR_MSK 0xfffffffd
3410 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_RESET 0x0
3412 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
3414 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
3416 #ifndef __ASSEMBLY__
3427 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s
3435 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t;
3439 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RESET 0x00000000
3441 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_OFST 0xdc
3465 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_LSB 0
3467 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_MSB 3
3469 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_WIDTH 4
3471 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET_MSK 0x0000000f
3473 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_CLR_MSK 0xfffffff0
3475 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_RESET 0x0
3477 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_GET(value) (((value) & 0x0000000f) >> 0)
3479 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET(value) (((value) << 0) & 0x0000000f)
3481 #ifndef __ASSEMBLY__
3492 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s
3494 uint32_t FILTERS_2_LENGTH : 4;
3499 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t;
3503 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_RESET 0x00000000
3505 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_OFST 0xe0
3530 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_LSB 0
3532 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_MSB 1
3534 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_WIDTH 2
3536 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET_MSK 0x00000003
3538 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_CLR_MSK 0xfffffffc
3540 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_RESET 0x0
3542 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
3544 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET(value) (((value) << 0) & 0x00000003)
3546 #ifndef __ASSEMBLY__
3557 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s
3559 uint32_t FILTERS_2_URGENCY : 2;
3564 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t;
3568 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_RESET 0x00000000
3570 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_OFST 0xe4
3594 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_LSB 0
3596 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_MSB 18
3598 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_WIDTH 19
3600 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET_MSK 0x0007ffff
3602 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_CLR_MSK 0xfff80000
3604 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_RESET 0x0
3606 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
3608 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
3610 #ifndef __ASSEMBLY__
3621 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s
3623 uint32_t FILTERS_3_ROUTEIDBASE : 19;
3628 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t;
3632 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_RESET 0x00000000
3634 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_OFST 0xf8
3659 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_LSB 0
3661 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_MSB 18
3663 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_WIDTH 19
3665 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET_MSK 0x0007ffff
3667 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_CLR_MSK 0xfff80000
3669 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_RESET 0x0
3671 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
3673 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
3675 #ifndef __ASSEMBLY__
3686 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s
3688 uint32_t FILTERS_3_ROUTEIDMASK : 19;
3693 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t;
3697 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_RESET 0x00000000
3699 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_OFST 0xfc
3721 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_LSB 0
3723 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_MSB 31
3725 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_WIDTH 32
3727 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET_MSK 0xffffffff
3729 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_CLR_MSK 0x00000000
3731 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_RESET 0x0
3733 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3735 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3737 #ifndef __ASSEMBLY__
3748 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s
3750 uint32_t FILTERS_3_ADDRBASE_LOW : 32;
3754 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t;
3758 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_RESET 0x00000000
3760 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_OFST 0x100
3787 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_LSB 0
3789 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_MSB 5
3791 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_WIDTH 6
3793 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET_MSK 0x0000003f
3795 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_CLR_MSK 0xffffffc0
3797 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_RESET 0x0
3799 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3801 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3803 #ifndef __ASSEMBLY__
3814 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s
3816 uint32_t FILTERS_3_WINDOWSIZE : 6;
3821 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t;
3825 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_RESET 0x00000000
3827 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_OFST 0x108
3850 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_LSB 0
3852 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_MSB 2
3854 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_WIDTH 3
3856 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET_MSK 0x00000007
3858 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_CLR_MSK 0xfffffff8
3860 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_RESET 0x0
3862 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3864 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3866 #ifndef __ASSEMBLY__
3877 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s
3879 uint32_t FILTERS_3_SECURITYBASE : 3;
3884 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t;
3888 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_RESET 0x00000000
3890 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_OFST 0x10c
3915 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_LSB 0
3917 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_MSB 2
3919 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_WIDTH 3
3921 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET_MSK 0x00000007
3923 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_CLR_MSK 0xfffffff8
3925 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_RESET 0x0
3927 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3929 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3931 #ifndef __ASSEMBLY__
3942 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s
3944 uint32_t FILTERS_3_SECURITYMASK : 3;
3949 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t;
3953 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_RESET 0x00000000
3955 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_OFST 0x110
3983 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_LSB 0
3985 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_MSB 0
3987 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_WIDTH 1
3989 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET_MSK 0x00000001
3991 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_CLR_MSK 0xfffffffe
3993 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_RESET 0x0
3995 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3997 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
4008 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_LSB 1
4010 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_MSB 1
4012 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_WIDTH 1
4014 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET_MSK 0x00000002
4016 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_CLR_MSK 0xfffffffd
4018 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_RESET 0x0
4020 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
4022 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
4033 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_LSB 2
4035 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_MSB 2
4037 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_WIDTH 1
4039 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET_MSK 0x00000004
4041 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
4043 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_RESET 0x0
4045 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
4047 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
4058 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_LSB 3
4060 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_MSB 3
4062 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_WIDTH 1
4064 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET_MSK 0x00000008
4066 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_CLR_MSK 0xfffffff7
4068 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_RESET 0x0
4070 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
4072 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
4074 #ifndef __ASSEMBLY__
4085 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s
4089 uint32_t LOCKEN : 1;
4095 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t;
4099 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RESET 0x00000000
4101 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_OFST 0x114
4127 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_LSB 0
4129 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_MSB 0
4131 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_WIDTH 1
4133 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET_MSK 0x00000001
4135 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_CLR_MSK 0xfffffffe
4137 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_RESET 0x0
4139 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
4141 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
4152 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_LSB 1
4154 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_MSB 1
4156 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_WIDTH 1
4158 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET_MSK 0x00000002
4160 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_CLR_MSK 0xfffffffd
4162 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_RESET 0x0
4164 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
4166 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
4168 #ifndef __ASSEMBLY__
4179 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s
4187 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t;
4191 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RESET 0x00000000
4193 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_OFST 0x118
4217 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_LSB 0
4219 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_MSB 3
4221 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_WIDTH 4
4223 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET_MSK 0x0000000f
4225 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_CLR_MSK 0xfffffff0
4227 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_RESET 0x0
4229 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_GET(value) (((value) & 0x0000000f) >> 0)
4231 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET(value) (((value) << 0) & 0x0000000f)
4233 #ifndef __ASSEMBLY__
4244 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s
4246 uint32_t FILTERS_3_LENGTH : 4;
4251 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t;
4255 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_RESET 0x00000000
4257 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_OFST 0x11c
4282 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_LSB 0
4284 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_MSB 1
4286 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_WIDTH 2
4288 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET_MSK 0x00000003
4290 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_CLR_MSK 0xfffffffc
4292 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_RESET 0x0
4294 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
4296 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET(value) (((value) << 0) & 0x00000003)
4298 #ifndef __ASSEMBLY__
4309 struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s
4311 uint32_t FILTERS_3_URGENCY : 2;
4316 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t;
4320 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_RESET 0x00000000
4322 #define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_OFST 0x120
4348 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_LSB 0
4350 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_MSB 4
4352 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_WIDTH 5
4354 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
4356 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
4358 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_RESET 0x0
4360 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4362 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4364 #ifndef __ASSEMBLY__
4375 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s
4377 uint32_t INTEVENT : 5;
4382 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t;
4386 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_RESET 0x00000000
4388 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_OFST 0x138
4413 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
4415 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
4417 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
4419 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
4421 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
4423 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
4425 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4427 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4429 #ifndef __ASSEMBLY__
4440 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s
4442 uint32_t COUNTERS_0_ALARMMODE : 2;
4447 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t;
4451 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_RESET 0x00000000
4453 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_OFST 0x13c
4478 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
4480 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
4482 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
4484 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
4486 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
4488 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
4490 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4492 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4494 #ifndef __ASSEMBLY__
4505 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s
4507 const uint32_t COUNTERS_0_VAL : 16;
4512 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t;
4516 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_RESET 0x00000000
4518 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_OFST 0x140
4544 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_LSB 0
4546 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_MSB 4
4548 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_WIDTH 5
4550 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
4552 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
4554 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_RESET 0x0
4556 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4558 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4560 #ifndef __ASSEMBLY__
4571 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s
4573 uint32_t INTEVENT : 5;
4578 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t;
4582 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_RESET 0x00000000
4584 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_OFST 0x14c
4609 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
4611 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
4613 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
4615 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
4617 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
4619 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
4621 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4623 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4625 #ifndef __ASSEMBLY__
4636 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s
4638 uint32_t COUNTERS_1_ALARMMODE : 2;
4643 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t;
4647 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_RESET 0x00000000
4649 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_OFST 0x150
4674 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
4676 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
4678 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
4680 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
4682 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
4684 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
4686 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4688 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4690 #ifndef __ASSEMBLY__
4701 struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s
4703 const uint32_t COUNTERS_1_VAL : 16;
4708 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t;
4712 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_RESET 0x00000000
4714 #define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_OFST 0x154
4716 #ifndef __ASSEMBLY__
4727 struct ALT_NOC_MPU_DDR_T_PRB_s
4729 ALT_NOC_MPU_DDR_T_PRB_COREID_t ddr_T_main_Probe_Id_CoreId;
4730 ALT_NOC_MPU_DDR_T_PRB_REVID_t ddr_T_main_Probe_Id_RevisionId;
4731 ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t ddr_T_main_Probe_MainCtl;
4732 ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t ddr_T_main_Probe_CfgCtl;
4733 volatile uint32_t _pad_0x10_0x13;
4734 ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t ddr_T_main_Probe_FilterLut;
4735 ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t ddr_T_main_Probe_TraceAlarmEn;
4736 ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t ddr_T_main_Probe_TraceAlarmStatus;
4737 ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t ddr_T_main_Probe_TraceAlarmClr;
4738 ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t ddr_T_main_Probe_StatPeriod;
4739 ALT_NOC_MPU_DDR_T_PRB_STATGO_t ddr_T_main_Probe_StatGo;
4740 ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t ddr_T_main_Probe_StatAlarmMin;
4741 ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t ddr_T_main_Probe_StatAlarmMax;
4742 ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t ddr_T_main_Probe_StatAlarmStatus;
4743 ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t ddr_T_main_Probe_StatAlarmClr;
4744 ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t ddr_T_main_Probe_StatAlarmEn;
4745 volatile uint32_t _pad_0x40_0x43;
4746 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t ddr_T_main_Probe_Filters_0_RouteIdBase;
4747 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t ddr_T_main_Probe_Filters_0_RouteIdMask;
4748 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_0_AddrBase_Low;
4749 volatile uint32_t _pad_0x50_0x53;
4750 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t ddr_T_main_Probe_Filters_0_WindowSize;
4751 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t ddr_T_main_Probe_Filters_0_SecurityBase;
4752 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t ddr_T_main_Probe_Filters_0_SecurityMask;
4753 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t ddr_T_main_Probe_Filters_0_Opcode;
4754 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t ddr_T_main_Probe_Filters_0_Status;
4755 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t ddr_T_main_Probe_Filters_0_Length;
4756 ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t ddr_T_main_Probe_Filters_0_Urgency;
4757 volatile uint32_t _pad_0x70_0x7f[4];
4758 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t ddr_T_main_Probe_Filters_1_RouteIdBase;
4759 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t ddr_T_main_Probe_Filters_1_RouteIdMask;
4760 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_1_AddrBase_Low;
4761 volatile uint32_t _pad_0x8c_0x8f;
4762 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t ddr_T_main_Probe_Filters_1_WindowSize;
4763 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t ddr_T_main_Probe_Filters_1_SecurityBase;
4764 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t ddr_T_main_Probe_Filters_1_SecurityMask;
4765 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t ddr_T_main_Probe_Filters_1_Opcode;
4766 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t ddr_T_main_Probe_Filters_1_Status;
4767 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t ddr_T_main_Probe_Filters_1_Length;
4768 ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t ddr_T_main_Probe_Filters_1_Urgency;
4769 volatile uint32_t _pad_0xac_0xbb[4];
4770 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t ddr_T_main_Probe_Filters_2_RouteIdBase;
4771 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t ddr_T_main_Probe_Filters_2_RouteIdMask;
4772 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_2_AddrBase_Low;
4773 volatile uint32_t _pad_0xc8_0xcb;
4774 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t ddr_T_main_Probe_Filters_2_WindowSize;
4775 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t ddr_T_main_Probe_Filters_2_SecurityBase;
4776 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t ddr_T_main_Probe_Filters_2_SecurityMask;
4777 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t ddr_T_main_Probe_Filters_2_Opcode;
4778 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t ddr_T_main_Probe_Filters_2_Status;
4779 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t ddr_T_main_Probe_Filters_2_Length;
4780 ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t ddr_T_main_Probe_Filters_2_Urgency;
4781 volatile uint32_t _pad_0xe8_0xf7[4];
4782 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t ddr_T_main_Probe_Filters_3_RouteIdBase;
4783 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t ddr_T_main_Probe_Filters_3_RouteIdMask;
4784 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t ddr_T_main_Probe_Filters_3_AddrBase_Low;
4785 volatile uint32_t _pad_0x104_0x107;
4786 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t ddr_T_main_Probe_Filters_3_WindowSize;
4787 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t ddr_T_main_Probe_Filters_3_SecurityBase;
4788 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t ddr_T_main_Probe_Filters_3_SecurityMask;
4789 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t ddr_T_main_Probe_Filters_3_Opcode;
4790 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t ddr_T_main_Probe_Filters_3_Status;
4791 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t ddr_T_main_Probe_Filters_3_Length;
4792 ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t ddr_T_main_Probe_Filters_3_Urgency;
4793 volatile uint32_t _pad_0x124_0x137[5];
4794 ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t ddr_T_main_Probe_Counters_0_Src;
4795 ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t ddr_T_main_Probe_Counters_0_AlarmMode;
4796 ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t ddr_T_main_Probe_Counters_0_Val;
4797 volatile uint32_t _pad_0x144_0x14b[2];
4798 ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t ddr_T_main_Probe_Counters_1_Src;
4799 ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t ddr_T_main_Probe_Counters_1_AlarmMode;
4800 ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t ddr_T_main_Probe_Counters_1_Val;
4801 volatile uint32_t _pad_0x158_0x400[170];
4805 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_s ALT_NOC_MPU_DDR_T_PRB_t;
4807 struct ALT_NOC_MPU_DDR_T_PRB_raw_s
4809 volatile uint32_t ddr_T_main_Probe_Id_CoreId;
4810 volatile uint32_t ddr_T_main_Probe_Id_RevisionId;
4811 volatile uint32_t ddr_T_main_Probe_MainCtl;
4812 volatile uint32_t ddr_T_main_Probe_CfgCtl;
4813 uint32_t _pad_0x10_0x13;
4814 volatile uint32_t ddr_T_main_Probe_FilterLut;
4815 volatile uint32_t ddr_T_main_Probe_TraceAlarmEn;
4816 volatile uint32_t ddr_T_main_Probe_TraceAlarmStatus;
4817 volatile uint32_t ddr_T_main_Probe_TraceAlarmClr;
4818 volatile uint32_t ddr_T_main_Probe_StatPeriod;
4819 volatile uint32_t ddr_T_main_Probe_StatGo;
4820 volatile uint32_t ddr_T_main_Probe_StatAlarmMin;
4821 volatile uint32_t ddr_T_main_Probe_StatAlarmMax;
4822 volatile uint32_t ddr_T_main_Probe_StatAlarmStatus;
4823 volatile uint32_t ddr_T_main_Probe_StatAlarmClr;
4824 volatile uint32_t ddr_T_main_Probe_StatAlarmEn;
4825 uint32_t _pad_0x40_0x43;
4826 volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdBase;
4827 volatile uint32_t ddr_T_main_Probe_Filters_0_RouteIdMask;
4828 volatile uint32_t ddr_T_main_Probe_Filters_0_AddrBase_Low;
4829 uint32_t _pad_0x50_0x53;
4830 volatile uint32_t ddr_T_main_Probe_Filters_0_WindowSize;
4831 volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityBase;
4832 volatile uint32_t ddr_T_main_Probe_Filters_0_SecurityMask;
4833 volatile uint32_t ddr_T_main_Probe_Filters_0_Opcode;
4834 volatile uint32_t ddr_T_main_Probe_Filters_0_Status;
4835 volatile uint32_t ddr_T_main_Probe_Filters_0_Length;
4836 volatile uint32_t ddr_T_main_Probe_Filters_0_Urgency;
4837 uint32_t _pad_0x70_0x7f[4];
4838 volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdBase;
4839 volatile uint32_t ddr_T_main_Probe_Filters_1_RouteIdMask;
4840 volatile uint32_t ddr_T_main_Probe_Filters_1_AddrBase_Low;
4841 uint32_t _pad_0x8c_0x8f;
4842 volatile uint32_t ddr_T_main_Probe_Filters_1_WindowSize;
4843 volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityBase;
4844 volatile uint32_t ddr_T_main_Probe_Filters_1_SecurityMask;
4845 volatile uint32_t ddr_T_main_Probe_Filters_1_Opcode;
4846 volatile uint32_t ddr_T_main_Probe_Filters_1_Status;
4847 volatile uint32_t ddr_T_main_Probe_Filters_1_Length;
4848 volatile uint32_t ddr_T_main_Probe_Filters_1_Urgency;
4849 uint32_t _pad_0xac_0xbb[4];
4850 volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdBase;
4851 volatile uint32_t ddr_T_main_Probe_Filters_2_RouteIdMask;
4852 volatile uint32_t ddr_T_main_Probe_Filters_2_AddrBase_Low;
4853 uint32_t _pad_0xc8_0xcb;
4854 volatile uint32_t ddr_T_main_Probe_Filters_2_WindowSize;
4855 volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityBase;
4856 volatile uint32_t ddr_T_main_Probe_Filters_2_SecurityMask;
4857 volatile uint32_t ddr_T_main_Probe_Filters_2_Opcode;
4858 volatile uint32_t ddr_T_main_Probe_Filters_2_Status;
4859 volatile uint32_t ddr_T_main_Probe_Filters_2_Length;
4860 volatile uint32_t ddr_T_main_Probe_Filters_2_Urgency;
4861 uint32_t _pad_0xe8_0xf7[4];
4862 volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdBase;
4863 volatile uint32_t ddr_T_main_Probe_Filters_3_RouteIdMask;
4864 volatile uint32_t ddr_T_main_Probe_Filters_3_AddrBase_Low;
4865 uint32_t _pad_0x104_0x107;
4866 volatile uint32_t ddr_T_main_Probe_Filters_3_WindowSize;
4867 volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityBase;
4868 volatile uint32_t ddr_T_main_Probe_Filters_3_SecurityMask;
4869 volatile uint32_t ddr_T_main_Probe_Filters_3_Opcode;
4870 volatile uint32_t ddr_T_main_Probe_Filters_3_Status;
4871 volatile uint32_t ddr_T_main_Probe_Filters_3_Length;
4872 volatile uint32_t ddr_T_main_Probe_Filters_3_Urgency;
4873 uint32_t _pad_0x124_0x137[5];
4874 volatile uint32_t ddr_T_main_Probe_Counters_0_Src;
4875 volatile uint32_t ddr_T_main_Probe_Counters_0_AlarmMode;
4876 volatile uint32_t ddr_T_main_Probe_Counters_0_Val;
4877 uint32_t _pad_0x144_0x14b[2];
4878 volatile uint32_t ddr_T_main_Probe_Counters_1_Src;
4879 volatile uint32_t ddr_T_main_Probe_Counters_1_AlarmMode;
4880 volatile uint32_t ddr_T_main_Probe_Counters_1_Val;
4881 uint32_t _pad_0x158_0x400[170];
4885 typedef volatile struct ALT_NOC_MPU_DDR_T_PRB_raw_s ALT_NOC_MPU_DDR_T_PRB_raw_t;
4913 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_LSB 0
4915 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_MSB 7
4917 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_WIDTH 8
4919 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET_MSK 0x000000ff
4921 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_CLR_MSK 0xffffff00
4923 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_RESET 0x2
4925 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
4927 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
4938 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_LSB 8
4940 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_MSB 31
4942 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_WIDTH 24
4944 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET_MSK 0xffffff00
4946 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_CLR_MSK 0x000000ff
4948 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_RESET 0x7242e2
4950 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
4952 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
4954 #ifndef __ASSEMBLY__
4965 struct ALT_NOC_MPU_DDR_T_SCHED_COREID_s
4967 const uint32_t CORETYPEID : 8;
4968 const uint32_t CORECHECKSUM : 24;
4972 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_COREID_s ALT_NOC_MPU_DDR_T_SCHED_COREID_t;
4976 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_RESET 0x7242e202
4978 #define ALT_NOC_MPU_DDR_T_SCHED_COREID_OFST 0x0
5000 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_LSB 0
5002 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_MSB 7
5004 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_WIDTH 8
5006 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET_MSK 0x000000ff
5008 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_CLR_MSK 0xffffff00
5010 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_RESET 0x0
5012 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
5014 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
5026 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_LSB 8
5028 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_MSB 31
5030 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_WIDTH 24
5032 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET_MSK 0xffffff00
5034 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_CLR_MSK 0x000000ff
5036 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_RESET 0x129ff
5038 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
5040 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
5042 #ifndef __ASSEMBLY__
5053 struct ALT_NOC_MPU_DDR_T_SCHED_REVID_s
5055 const uint32_t USERID : 8;
5056 const uint32_t FLEXNOCID : 24;
5060 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_REVID_s ALT_NOC_MPU_DDR_T_SCHED_REVID_t;
5064 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_RESET 0x0129ff00
5066 #define ALT_NOC_MPU_DDR_T_SCHED_REVID_OFST 0x4
5127 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R12_B3_C10 0x00
5133 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R13_B3_C10 0x01
5139 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C10 0x02
5145 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C10 0x03
5151 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C10 0x04
5157 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B3_C10 0x05
5163 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C11 0x06
5169 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C11 0x07
5175 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C11 0x08
5181 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C12 0x09
5187 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B4_C10 0x0A
5193 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B4_C10 0x0B
5199 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B4_C10 0x0C
5205 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B4_C10 0x0D
5211 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R12_C10 0x0E
5217 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R13_C10 0x0F
5223 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C10 0x10
5229 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C10 0x11
5235 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C10 0x12
5241 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R17_C10 0x13
5247 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C11 0x14
5253 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C11 0x15
5259 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C11 0x16
5265 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C12 0x17
5271 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R14_C10 0x18
5277 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R15_C10 0x19
5283 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R16_C10 0x1A
5289 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R17_C10 0x1B
5292 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_LSB 0
5294 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_MSB 4
5296 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_WIDTH 5
5298 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET_MSK 0x0000001f
5300 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_CLR_MSK 0xffffffe0
5302 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_RESET 0x0
5304 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_GET(value) (((value) & 0x0000001f) >> 0)
5306 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET(value) (((value) << 0) & 0x0000001f)
5308 #ifndef __ASSEMBLY__
5319 struct ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s
5321 uint32_t DDRCONF : 5;
5326 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t;
5330 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_RESET 0x00000000
5332 #define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_OFST 0x8
5362 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
5364 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_MSB 5
5366 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_WIDTH 6
5368 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f
5370 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0
5372 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_RESET 0x1c
5374 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0)
5376 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f)
5388 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
5390 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_MSB 11
5392 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_WIDTH 6
5394 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0
5396 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f
5398 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_RESET 0x13
5400 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6)
5402 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0)
5414 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
5416 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_MSB 17
5418 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_WIDTH 6
5420 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000
5422 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff
5424 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_RESET 0x21
5426 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12)
5428 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000)
5440 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
5442 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_MSB 20
5444 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_WIDTH 3
5446 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000
5448 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff
5450 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_RESET 0x2
5452 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18)
5454 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000)
5466 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
5468 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_MSB 25
5470 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_WIDTH 5
5472 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET_MSK 0x03e00000
5474 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff
5476 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_RESET 0x1
5478 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21)
5480 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000)
5492 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
5494 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_MSB 30
5496 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_WIDTH 5
5498 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET_MSK 0x7c000000
5500 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff
5502 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_RESET 0xb
5504 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26)
5506 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000)
5517 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
5519 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_MSB 31
5521 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_WIDTH 1
5523 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET_MSK 0x80000000
5525 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff
5527 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_RESET 0x1
5529 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31)
5531 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000)
5533 #ifndef __ASSEMBLY__
5544 struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s
5546 uint32_t ACTTOACT : 6;
5547 uint32_t RDTOMISS : 6;
5548 uint32_t WRTOMISS : 6;
5549 uint32_t BURSTLEN : 3;
5550 uint32_t RDTOWR : 5;
5551 uint32_t WRTORD : 5;
5552 uint32_t BWRATIO : 1;
5556 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t;
5560 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RESET 0xac2a14dc
5562 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_OFST 0xc
5588 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
5590 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_MSB 0
5592 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_WIDTH 1
5594 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET_MSK 0x00000001
5596 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_CLR_MSK 0xfffffffe
5598 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_RESET 0x0
5600 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_GET(value) (((value) & 0x00000001) >> 0)
5602 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET(value) (((value) << 0) & 0x00000001)
5613 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
5615 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_MSB 1
5617 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_WIDTH 1
5619 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET_MSK 0x00000002
5621 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_CLR_MSK 0xfffffffd
5623 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_RESET 0x0
5625 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_GET(value) (((value) & 0x00000002) >> 1)
5627 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET(value) (((value) << 1) & 0x00000002)
5629 #ifndef __ASSEMBLY__
5640 struct ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s
5642 uint32_t AUTOPRECHARGE : 1;
5643 uint32_t BWRATIOEXTENDED : 1;
5648 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t;
5652 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_RESET 0x00000000
5654 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_OFST 0x10
5677 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_LSB 0
5679 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_MSB 7
5681 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_WIDTH 8
5683 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET_MSK 0x000000ff
5685 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_CLR_MSK 0xffffff00
5687 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_RESET 0x13
5689 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_GET(value) (((value) & 0x000000ff) >> 0)
5691 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET(value) (((value) << 0) & 0x000000ff)
5693 #ifndef __ASSEMBLY__
5704 struct ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s
5706 uint32_t READLATENCY : 8;
5711 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t;
5715 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RESET 0x00000013
5717 #define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_OFST 0x14
5744 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
5746 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_MSB 3
5748 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_WIDTH 4
5750 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET_MSK 0x0000000f
5752 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_CLR_MSK 0xfffffff0
5754 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_RESET 0x2
5756 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_GET(value) (((value) & 0x0000000f) >> 0)
5758 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET(value) (((value) << 0) & 0x0000000f)
5769 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
5771 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_MSB 9
5773 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_WIDTH 6
5775 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET_MSK 0x000003f0
5777 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_CLR_MSK 0xfffffc0f
5779 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_RESET 0xd
5781 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_GET(value) (((value) & 0x000003f0) >> 4)
5783 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET(value) (((value) << 4) & 0x000003f0)
5794 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
5796 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_MSB 10
5798 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_WIDTH 1
5800 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET_MSK 0x00000400
5802 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_CLR_MSK 0xfffffbff
5804 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_RESET 0x1
5806 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_GET(value) (((value) & 0x00000400) >> 10)
5808 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET(value) (((value) << 10) & 0x00000400)
5810 #ifndef __ASSEMBLY__
5821 struct ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s
5825 uint32_t FAWBANK : 1;
5830 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t;
5834 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RESET 0x000004d2
5836 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_OFST 0x38
5864 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
5866 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_MSB 1
5868 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_WIDTH 2
5870 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET_MSK 0x00000003
5872 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_CLR_MSK 0xfffffffc
5874 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_RESET 0x1
5876 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_GET(value) (((value) & 0x00000003) >> 0)
5878 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET(value) (((value) << 0) & 0x00000003)
5890 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
5892 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_MSB 3
5894 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_WIDTH 2
5896 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET_MSK 0x0000000c
5898 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_CLR_MSK 0xfffffff3
5900 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_RESET 0x1
5902 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_GET(value) (((value) & 0x0000000c) >> 2)
5904 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET(value) (((value) << 2) & 0x0000000c)
5916 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
5918 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_MSB 5
5920 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_WIDTH 2
5922 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET_MSK 0x00000030
5924 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_CLR_MSK 0xffffffcf
5926 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_RESET 0x1
5928 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_GET(value) (((value) & 0x00000030) >> 4)
5930 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET(value) (((value) << 4) & 0x00000030)
5932 #ifndef __ASSEMBLY__
5943 struct ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s
5945 uint32_t BUSRDTORD : 2;
5946 uint32_t BUSRDTOWR : 2;
5947 uint32_t BUSWRTORD : 2;
5952 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t;
5956 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_RESET 0x00000015
5958 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_OFST 0x3c
5960 #ifndef __ASSEMBLY__
5971 struct ALT_NOC_MPU_DDR_T_SCHED_s
5973 ALT_NOC_MPU_DDR_T_SCHED_COREID_t ddr_T_main_Scheduler_Id_CoreId;
5974 ALT_NOC_MPU_DDR_T_SCHED_REVID_t ddr_T_main_Scheduler_Id_RevisionId;
5975 ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t ddr_T_main_Scheduler_DdrConf;
5976 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t ddr_T_main_Scheduler_DdrTiming;
5977 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t ddr_T_main_Scheduler_DdrMode;
5978 ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t ddr_T_main_Scheduler_ReadLatency;
5979 volatile uint32_t _pad_0x18_0x37[8];
5980 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t ddr_T_main_Scheduler_Activate;
5981 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t ddr_T_main_Scheduler_DevToDev;
5982 volatile uint32_t _pad_0x40_0x80[16];
5986 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_s ALT_NOC_MPU_DDR_T_SCHED_t;
5988 struct ALT_NOC_MPU_DDR_T_SCHED_raw_s
5990 volatile uint32_t ddr_T_main_Scheduler_Id_CoreId;
5991 volatile uint32_t ddr_T_main_Scheduler_Id_RevisionId;
5992 volatile uint32_t ddr_T_main_Scheduler_DdrConf;
5993 volatile uint32_t ddr_T_main_Scheduler_DdrTiming;
5994 volatile uint32_t ddr_T_main_Scheduler_DdrMode;
5995 volatile uint32_t ddr_T_main_Scheduler_ReadLatency;
5996 uint32_t _pad_0x18_0x37[8];
5997 volatile uint32_t ddr_T_main_Scheduler_Activate;
5998 volatile uint32_t ddr_T_main_Scheduler_DevToDev;
5999 uint32_t _pad_0x40_0x80[16];
6003 typedef volatile struct ALT_NOC_MPU_DDR_T_SCHED_raw_s ALT_NOC_MPU_DDR_T_SCHED_raw_t;