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alt_noc_fw_lwh2f_scr.h
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32 
33 /* Altera - ALT_NOC_FW_LWH2F_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_LWH2F_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_LWH2F_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_FW_LWH2F_SCR
50  * SOC2FPGA Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : lwsoc2fpga
55  *
56  * Per-Master Security bit for Lightweight SOC2FPGA
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:------|:------------------------------------------
62  * [0] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU
63  * [7:1] | ??? | 0x0 | *UNDEFINED*
64  * [8] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA
65  * [16:9] | ??? | 0x0 | *UNDEFINED*
66  * [17] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0
67  * [18] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1
68  * [19] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2
69  * [20] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0
70  * [21] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1
71  * [22] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC
72  * [23] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND
73  * [24] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP
74  * [25] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR
75  * [26] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC
76  * [27] | RW | 0x0 | ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND
77  * [31:28] | ??? | 0x0 | *UNDEFINED*
78  *
79  */
80 /*
81  * Field : mpu
82  *
83  * Security bit configuration for transactions from mpu to lwsoc2fpga. When cleared
84  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
85  * Secure transactions are allowed.
86  *
87  * Field Access Macros:
88  *
89  */
90 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field. */
91 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_LSB 0
92 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field. */
93 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_MSB 0
94 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field. */
95 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_WIDTH 1
96 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field value. */
97 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_SET_MSK 0x00000001
98 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field value. */
99 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_CLR_MSK 0xfffffffe
100 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field. */
101 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_RESET 0x0
102 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU field value from a register. */
103 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_GET(value) (((value) & 0x00000001) >> 0)
104 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU register field value suitable for setting the register. */
105 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_SET(value) (((value) << 0) & 0x00000001)
106 
107 /*
108  * Field : dma
109  *
110  * Security bit configuration for transactions from dma to lwsoc2fpga. When cleared
111  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
112  * Secure transactions are allowed.
113  *
114  * Field Access Macros:
115  *
116  */
117 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field. */
118 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_LSB 8
119 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field. */
120 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_MSB 8
121 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field. */
122 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_WIDTH 1
123 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field value. */
124 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_SET_MSK 0x00000100
125 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field value. */
126 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_CLR_MSK 0xfffffeff
127 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field. */
128 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_RESET 0x0
129 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA field value from a register. */
130 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_GET(value) (((value) & 0x00000100) >> 8)
131 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA register field value suitable for setting the register. */
132 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_SET(value) (((value) << 8) & 0x00000100)
133 
134 /*
135  * Field : emac0
136  *
137  * Security bit configuration for transactions from emac0 to lwsoc2fpga. When
138  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
139  * Non-Secure transactions are allowed.
140  *
141  * Field Access Macros:
142  *
143  */
144 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field. */
145 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_LSB 17
146 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field. */
147 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_MSB 17
148 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field. */
149 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_WIDTH 1
150 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field value. */
151 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_SET_MSK 0x00020000
152 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field value. */
153 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_CLR_MSK 0xfffdffff
154 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field. */
155 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_RESET 0x0
156 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 field value from a register. */
157 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_GET(value) (((value) & 0x00020000) >> 17)
158 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 register field value suitable for setting the register. */
159 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_SET(value) (((value) << 17) & 0x00020000)
160 
161 /*
162  * Field : emac1
163  *
164  * Security bit configuration for transactions from emac1 to lwsoc2fpga. When
165  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
166  * Non-Secure transactions are allowed.
167  *
168  * Field Access Macros:
169  *
170  */
171 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field. */
172 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_LSB 18
173 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field. */
174 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_MSB 18
175 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field. */
176 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_WIDTH 1
177 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field value. */
178 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_SET_MSK 0x00040000
179 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field value. */
180 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_CLR_MSK 0xfffbffff
181 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field. */
182 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_RESET 0x0
183 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 field value from a register. */
184 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_GET(value) (((value) & 0x00040000) >> 18)
185 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 register field value suitable for setting the register. */
186 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_SET(value) (((value) << 18) & 0x00040000)
187 
188 /*
189  * Field : emac2
190  *
191  * Security bit configuration for transactions from emac2 to lwsoc2fpga. When
192  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
193  * Non-Secure transactions are allowed.
194  *
195  * Field Access Macros:
196  *
197  */
198 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field. */
199 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_LSB 19
200 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field. */
201 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_MSB 19
202 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field. */
203 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_WIDTH 1
204 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field value. */
205 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_SET_MSK 0x00080000
206 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field value. */
207 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_CLR_MSK 0xfff7ffff
208 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field. */
209 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_RESET 0x0
210 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 field value from a register. */
211 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_GET(value) (((value) & 0x00080000) >> 19)
212 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 register field value suitable for setting the register. */
213 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_SET(value) (((value) << 19) & 0x00080000)
214 
215 /*
216  * Field : usb0
217  *
218  * Security bit configuration for transactions from usb0 to lwsoc2fpga. When
219  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
220  * Non-Secure transactions are allowed.
221  *
222  * Field Access Macros:
223  *
224  */
225 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field. */
226 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_LSB 20
227 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field. */
228 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_MSB 20
229 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field. */
230 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_WIDTH 1
231 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field value. */
232 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_SET_MSK 0x00100000
233 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field value. */
234 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_CLR_MSK 0xffefffff
235 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field. */
236 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_RESET 0x0
237 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 field value from a register. */
238 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_GET(value) (((value) & 0x00100000) >> 20)
239 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 register field value suitable for setting the register. */
240 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_SET(value) (((value) << 20) & 0x00100000)
241 
242 /*
243  * Field : usb1
244  *
245  * Security bit configuration for transactions from usb1 to lwsoc2fpga. When
246  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
247  * Non-Secure transactions are allowed.
248  *
249  * Field Access Macros:
250  *
251  */
252 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field. */
253 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_LSB 21
254 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field. */
255 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_MSB 21
256 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field. */
257 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_WIDTH 1
258 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field value. */
259 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_SET_MSK 0x00200000
260 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field value. */
261 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_CLR_MSK 0xffdfffff
262 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field. */
263 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_RESET 0x0
264 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 field value from a register. */
265 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_GET(value) (((value) & 0x00200000) >> 21)
266 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 register field value suitable for setting the register. */
267 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_SET(value) (((value) << 21) & 0x00200000)
268 
269 /*
270  * Field : sdmmc
271  *
272  * Security bit configuration for transactions from sdmmc to lwsoc2fpga. When
273  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
274  * Non-Secure transactions are allowed.
275  *
276  * Field Access Macros:
277  *
278  */
279 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field. */
280 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_LSB 22
281 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field. */
282 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_MSB 22
283 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field. */
284 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_WIDTH 1
285 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field value. */
286 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_SET_MSK 0x00400000
287 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field value. */
288 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_CLR_MSK 0xffbfffff
289 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field. */
290 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_RESET 0x0
291 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC field value from a register. */
292 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
293 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC register field value suitable for setting the register. */
294 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_SET(value) (((value) << 22) & 0x00400000)
295 
296 /*
297  * Field : nand
298  *
299  * Security bit configuration for transactions from nand to lwsoc2fpga. When
300  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
301  * Non-Secure transactions are allowed.
302  *
303  * Field Access Macros:
304  *
305  */
306 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field. */
307 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_LSB 23
308 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field. */
309 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_MSB 23
310 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field. */
311 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_WIDTH 1
312 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field value. */
313 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_SET_MSK 0x00800000
314 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field value. */
315 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_CLR_MSK 0xff7fffff
316 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field. */
317 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_RESET 0x0
318 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND field value from a register. */
319 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_GET(value) (((value) & 0x00800000) >> 23)
320 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND register field value suitable for setting the register. */
321 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_SET(value) (((value) << 23) & 0x00800000)
322 
323 /*
324  * Field : axi_ap
325  *
326  * Security bit configuration for transactions from axi_ap to lwsoc2fpga. When
327  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
328  * Non-Secure transactions are allowed.
329  *
330  * Field Access Macros:
331  *
332  */
333 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field. */
334 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_LSB 24
335 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field. */
336 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_MSB 24
337 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field. */
338 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_WIDTH 1
339 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field value. */
340 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_SET_MSK 0x01000000
341 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field value. */
342 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_CLR_MSK 0xfeffffff
343 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field. */
344 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_RESET 0x0
345 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP field value from a register. */
346 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
347 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP register field value suitable for setting the register. */
348 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
349 
350 /*
351  * Field : etr
352  *
353  * Security bit configuration for transactions from etr to lwsoc2fpga. When cleared
354  * (0), only Secure transactions are allowed. When set (1), both Secure and Non-
355  * Secure transactions are allowed.
356  *
357  * Field Access Macros:
358  *
359  */
360 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field. */
361 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_LSB 25
362 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field. */
363 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_MSB 25
364 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field. */
365 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_WIDTH 1
366 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field value. */
367 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_SET_MSK 0x02000000
368 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field value. */
369 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_CLR_MSK 0xfdffffff
370 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field. */
371 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_RESET 0x0
372 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR field value from a register. */
373 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_GET(value) (((value) & 0x02000000) >> 25)
374 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR register field value suitable for setting the register. */
375 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_SET(value) (((value) << 25) & 0x02000000)
376 
377 /*
378  * Field : sdm_sdmmc
379  *
380  * Security bit configuration for transactions from SDM SDMMC to lwsoc2fpga. When
381  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
382  * Non-Secure transactions are allowed.
383  *
384  * Field Access Macros:
385  *
386  */
387 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field. */
388 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_LSB 26
389 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field. */
390 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_MSB 26
391 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field. */
392 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_WIDTH 1
393 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field value. */
394 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_SET_MSK 0x04000000
395 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field value. */
396 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_CLR_MSK 0xfbffffff
397 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field. */
398 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_RESET 0x0
399 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC field value from a register. */
400 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_GET(value) (((value) & 0x04000000) >> 26)
401 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC register field value suitable for setting the register. */
402 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_SET(value) (((value) << 26) & 0x04000000)
403 
404 /*
405  * Field : sdm_nand
406  *
407  * Security bit configuration for transactions from SDM NAND to lwsoc2fpga. When
408  * cleared (0), only Secure transactions are allowed. When set (1), both Secure and
409  * Non-Secure transactions are allowed.
410  *
411  * Field Access Macros:
412  *
413  */
414 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field. */
415 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_LSB 27
416 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field. */
417 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_MSB 27
418 /* The width in bits of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field. */
419 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_WIDTH 1
420 /* The mask used to set the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field value. */
421 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_SET_MSK 0x08000000
422 /* The mask used to clear the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field value. */
423 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_CLR_MSK 0xf7ffffff
424 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field. */
425 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_RESET 0x0
426 /* Extracts the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND field value from a register. */
427 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_GET(value) (((value) & 0x08000000) >> 27)
428 /* Produces a ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND register field value suitable for setting the register. */
429 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_SET(value) (((value) << 27) & 0x08000000)
430 
431 #ifndef __ASSEMBLY__
432 /*
433  * WARNING: The C register and register group struct declarations are provided for
434  * convenience and illustrative purposes. They should, however, be used with
435  * caution as the C language standard provides no guarantees about the alignment or
436  * atomicity of device memory accesses. The recommended practice for coding device
437  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
438  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
439  * alt_write_dword() functions for 64 bit registers.
440  *
441  * The struct declaration for register ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA.
442  */
443 struct ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_s
444 {
445  volatile uint32_t mpu : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU */
446  uint32_t : 7; /* *UNDEFINED* */
447  volatile uint32_t dma : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA */
448  uint32_t : 8; /* *UNDEFINED* */
449  volatile uint32_t emac0 : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0 */
450  volatile uint32_t emac1 : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1 */
451  volatile uint32_t emac2 : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2 */
452  volatile uint32_t usb0 : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0 */
453  volatile uint32_t usb1 : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1 */
454  volatile uint32_t sdmmc : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC */
455  volatile uint32_t nand : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND */
456  volatile uint32_t axi_ap : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP */
457  volatile uint32_t etr : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR */
458  volatile uint32_t sdm_sdmmc : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC */
459  volatile uint32_t sdm_nand : 1; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND */
460  uint32_t : 4; /* *UNDEFINED* */
461 };
462 
463 /* The typedef declaration for register ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA. */
464 typedef struct ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_s ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_t;
465 #endif /* __ASSEMBLY__ */
466 
467 /* The reset value of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA register. */
468 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_RESET 0x00000000
469 /* The byte offset of the ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA register from the beginning of the component. */
470 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_OFST 0x0
471 
472 #ifndef __ASSEMBLY__
473 /*
474  * WARNING: The C register and register group struct declarations are provided for
475  * convenience and illustrative purposes. They should, however, be used with
476  * caution as the C language standard provides no guarantees about the alignment or
477  * atomicity of device memory accesses. The recommended practice for coding device
478  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
479  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
480  * alt_write_dword() functions for 64 bit registers.
481  *
482  * The struct declaration for register group ALT_NOC_FW_LWH2F_SCR.
483  */
484 struct ALT_NOC_FW_LWH2F_SCR_s
485 {
486  volatile ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_t lwsoc2fpga; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA */
487  volatile uint32_t _pad_0x4_0x100[63]; /* *UNDEFINED* */
488 };
489 
490 /* The typedef declaration for register group ALT_NOC_FW_LWH2F_SCR. */
491 typedef struct ALT_NOC_FW_LWH2F_SCR_s ALT_NOC_FW_LWH2F_SCR_t;
492 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_LWH2F_SCR. */
493 struct ALT_NOC_FW_LWH2F_SCR_raw_s
494 {
495  volatile uint32_t lwsoc2fpga; /* ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA */
496  volatile uint32_t _pad_0x4_0x100[63]; /* *UNDEFINED* */
497 };
498 
499 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_LWH2F_SCR. */
500 typedef struct ALT_NOC_FW_LWH2F_SCR_raw_s ALT_NOC_FW_LWH2F_SCR_raw_t;
501 #endif /* __ASSEMBLY__ */
502 
503 
504 #ifdef __cplusplus
505 }
506 #endif /* __cplusplus */
507 #endif /* __ALT_SOCAL_NOC_FW_LWH2F_SCR_H__ */
508