35 #ifndef __ALT_SOCAL_EMAC_DMA_H__
36 #define __ALT_SOCAL_EMAC_DMA_H__
107 #define ALT_EMAC_DMA_BUS_MODE_SWR_LSB 0
109 #define ALT_EMAC_DMA_BUS_MODE_SWR_MSB 0
111 #define ALT_EMAC_DMA_BUS_MODE_SWR_WIDTH 1
113 #define ALT_EMAC_DMA_BUS_MODE_SWR_SET_MSK 0x00000001
115 #define ALT_EMAC_DMA_BUS_MODE_SWR_CLR_MSK 0xfffffffe
117 #define ALT_EMAC_DMA_BUS_MODE_SWR_RESET 0x1
119 #define ALT_EMAC_DMA_BUS_MODE_SWR_GET(value) (((value) & 0x00000001) >> 0)
121 #define ALT_EMAC_DMA_BUS_MODE_SWR_SET(value) (((value) << 0) & 0x00000001)
147 #define ALT_EMAC_DMA_BUS_MODE_DA_LSB 1
149 #define ALT_EMAC_DMA_BUS_MODE_DA_MSB 1
151 #define ALT_EMAC_DMA_BUS_MODE_DA_WIDTH 1
153 #define ALT_EMAC_DMA_BUS_MODE_DA_SET_MSK 0x00000002
155 #define ALT_EMAC_DMA_BUS_MODE_DA_CLR_MSK 0xfffffffd
157 #define ALT_EMAC_DMA_BUS_MODE_DA_RESET 0x0
159 #define ALT_EMAC_DMA_BUS_MODE_DA_GET(value) (((value) & 0x00000002) >> 1)
161 #define ALT_EMAC_DMA_BUS_MODE_DA_SET(value) (((value) << 1) & 0x00000002)
178 #define ALT_EMAC_DMA_BUS_MODE_DSL_LSB 2
180 #define ALT_EMAC_DMA_BUS_MODE_DSL_MSB 6
182 #define ALT_EMAC_DMA_BUS_MODE_DSL_WIDTH 5
184 #define ALT_EMAC_DMA_BUS_MODE_DSL_SET_MSK 0x0000007c
186 #define ALT_EMAC_DMA_BUS_MODE_DSL_CLR_MSK 0xffffff83
188 #define ALT_EMAC_DMA_BUS_MODE_DSL_RESET 0x0
190 #define ALT_EMAC_DMA_BUS_MODE_DSL_GET(value) (((value) & 0x0000007c) >> 2)
192 #define ALT_EMAC_DMA_BUS_MODE_DSL_SET(value) (((value) << 2) & 0x0000007c)
227 #define ALT_EMAC_DMA_BUS_MODE_ATDS_LSB 7
229 #define ALT_EMAC_DMA_BUS_MODE_ATDS_MSB 7
231 #define ALT_EMAC_DMA_BUS_MODE_ATDS_WIDTH 1
233 #define ALT_EMAC_DMA_BUS_MODE_ATDS_SET_MSK 0x00000080
235 #define ALT_EMAC_DMA_BUS_MODE_ATDS_CLR_MSK 0xffffff7f
237 #define ALT_EMAC_DMA_BUS_MODE_ATDS_RESET 0x0
239 #define ALT_EMAC_DMA_BUS_MODE_ATDS_GET(value) (((value) & 0x00000080) >> 7)
241 #define ALT_EMAC_DMA_BUS_MODE_ATDS_SET(value) (((value) << 7) & 0x00000080)
346 #define ALT_EMAC_DMA_BUS_MODE_PBL_LSB 8
348 #define ALT_EMAC_DMA_BUS_MODE_PBL_MSB 13
350 #define ALT_EMAC_DMA_BUS_MODE_PBL_WIDTH 6
352 #define ALT_EMAC_DMA_BUS_MODE_PBL_SET_MSK 0x00003f00
354 #define ALT_EMAC_DMA_BUS_MODE_PBL_CLR_MSK 0xffffc0ff
356 #define ALT_EMAC_DMA_BUS_MODE_PBL_RESET 0x1
358 #define ALT_EMAC_DMA_BUS_MODE_PBL_GET(value) (((value) & 0x00003f00) >> 8)
360 #define ALT_EMAC_DMA_BUS_MODE_PBL_SET(value) (((value) << 8) & 0x00003f00)
386 #define ALT_EMAC_DMA_BUS_MODE_PR_LSB 14
388 #define ALT_EMAC_DMA_BUS_MODE_PR_MSB 15
390 #define ALT_EMAC_DMA_BUS_MODE_PR_WIDTH 2
392 #define ALT_EMAC_DMA_BUS_MODE_PR_SET_MSK 0x0000c000
394 #define ALT_EMAC_DMA_BUS_MODE_PR_CLR_MSK 0xffff3fff
396 #define ALT_EMAC_DMA_BUS_MODE_PR_RESET 0x0
398 #define ALT_EMAC_DMA_BUS_MODE_PR_GET(value) (((value) & 0x0000c000) >> 14)
400 #define ALT_EMAC_DMA_BUS_MODE_PR_SET(value) (((value) << 14) & 0x0000c000)
419 #define ALT_EMAC_DMA_BUS_MODE_FB_LSB 16
421 #define ALT_EMAC_DMA_BUS_MODE_FB_MSB 16
423 #define ALT_EMAC_DMA_BUS_MODE_FB_WIDTH 1
425 #define ALT_EMAC_DMA_BUS_MODE_FB_SET_MSK 0x00010000
427 #define ALT_EMAC_DMA_BUS_MODE_FB_CLR_MSK 0xfffeffff
429 #define ALT_EMAC_DMA_BUS_MODE_FB_RESET 0x0
431 #define ALT_EMAC_DMA_BUS_MODE_FB_GET(value) (((value) & 0x00010000) >> 16)
433 #define ALT_EMAC_DMA_BUS_MODE_FB_SET(value) (((value) << 16) & 0x00010000)
454 #define ALT_EMAC_DMA_BUS_MODE_RPBL_LSB 17
456 #define ALT_EMAC_DMA_BUS_MODE_RPBL_MSB 22
458 #define ALT_EMAC_DMA_BUS_MODE_RPBL_WIDTH 6
460 #define ALT_EMAC_DMA_BUS_MODE_RPBL_SET_MSK 0x007e0000
462 #define ALT_EMAC_DMA_BUS_MODE_RPBL_CLR_MSK 0xff81ffff
464 #define ALT_EMAC_DMA_BUS_MODE_RPBL_RESET 0x1
466 #define ALT_EMAC_DMA_BUS_MODE_RPBL_GET(value) (((value) & 0x007e0000) >> 17)
468 #define ALT_EMAC_DMA_BUS_MODE_RPBL_SET(value) (((value) << 17) & 0x007e0000)
486 #define ALT_EMAC_DMA_BUS_MODE_USP_LSB 23
488 #define ALT_EMAC_DMA_BUS_MODE_USP_MSB 23
490 #define ALT_EMAC_DMA_BUS_MODE_USP_WIDTH 1
492 #define ALT_EMAC_DMA_BUS_MODE_USP_SET_MSK 0x00800000
494 #define ALT_EMAC_DMA_BUS_MODE_USP_CLR_MSK 0xff7fffff
496 #define ALT_EMAC_DMA_BUS_MODE_USP_RESET 0x0
498 #define ALT_EMAC_DMA_BUS_MODE_USP_GET(value) (((value) & 0x00800000) >> 23)
500 #define ALT_EMAC_DMA_BUS_MODE_USP_SET(value) (((value) << 23) & 0x00800000)
518 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_LSB 24
520 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_MSB 24
522 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_WIDTH 1
524 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_SET_MSK 0x01000000
526 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_CLR_MSK 0xfeffffff
528 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_RESET 0x0
530 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_GET(value) (((value) & 0x01000000) >> 24)
532 #define ALT_EMAC_DMA_BUS_MODE_PBLX8_SET(value) (((value) << 24) & 0x01000000)
551 #define ALT_EMAC_DMA_BUS_MODE_AAL_LSB 25
553 #define ALT_EMAC_DMA_BUS_MODE_AAL_MSB 25
555 #define ALT_EMAC_DMA_BUS_MODE_AAL_WIDTH 1
557 #define ALT_EMAC_DMA_BUS_MODE_AAL_SET_MSK 0x02000000
559 #define ALT_EMAC_DMA_BUS_MODE_AAL_CLR_MSK 0xfdffffff
561 #define ALT_EMAC_DMA_BUS_MODE_AAL_RESET 0x0
563 #define ALT_EMAC_DMA_BUS_MODE_AAL_GET(value) (((value) & 0x02000000) >> 25)
565 #define ALT_EMAC_DMA_BUS_MODE_AAL_SET(value) (((value) << 25) & 0x02000000)
583 #define ALT_EMAC_DMA_BUS_MODE_MB_LSB 26
585 #define ALT_EMAC_DMA_BUS_MODE_MB_MSB 26
587 #define ALT_EMAC_DMA_BUS_MODE_MB_WIDTH 1
589 #define ALT_EMAC_DMA_BUS_MODE_MB_SET_MSK 0x04000000
591 #define ALT_EMAC_DMA_BUS_MODE_MB_CLR_MSK 0xfbffffff
593 #define ALT_EMAC_DMA_BUS_MODE_MB_RESET 0x0
595 #define ALT_EMAC_DMA_BUS_MODE_MB_GET(value) (((value) & 0x04000000) >> 26)
597 #define ALT_EMAC_DMA_BUS_MODE_MB_SET(value) (((value) << 26) & 0x04000000)
612 #define ALT_EMAC_DMA_BUS_MODE_TXPR_LSB 27
614 #define ALT_EMAC_DMA_BUS_MODE_TXPR_MSB 27
616 #define ALT_EMAC_DMA_BUS_MODE_TXPR_WIDTH 1
618 #define ALT_EMAC_DMA_BUS_MODE_TXPR_SET_MSK 0x08000000
620 #define ALT_EMAC_DMA_BUS_MODE_TXPR_CLR_MSK 0xf7ffffff
622 #define ALT_EMAC_DMA_BUS_MODE_TXPR_RESET 0x0
624 #define ALT_EMAC_DMA_BUS_MODE_TXPR_GET(value) (((value) & 0x08000000) >> 27)
626 #define ALT_EMAC_DMA_BUS_MODE_TXPR_SET(value) (((value) << 27) & 0x08000000)
651 #define ALT_EMAC_DMA_BUS_MODE_PRWG_LSB 28
653 #define ALT_EMAC_DMA_BUS_MODE_PRWG_MSB 29
655 #define ALT_EMAC_DMA_BUS_MODE_PRWG_WIDTH 2
657 #define ALT_EMAC_DMA_BUS_MODE_PRWG_SET_MSK 0x30000000
659 #define ALT_EMAC_DMA_BUS_MODE_PRWG_CLR_MSK 0xcfffffff
661 #define ALT_EMAC_DMA_BUS_MODE_PRWG_RESET 0x0
663 #define ALT_EMAC_DMA_BUS_MODE_PRWG_GET(value) (((value) & 0x30000000) >> 28)
665 #define ALT_EMAC_DMA_BUS_MODE_PRWG_SET(value) (((value) << 28) & 0x30000000)
676 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_LSB 30
678 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_MSB 30
680 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_WIDTH 1
682 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_SET_MSK 0x40000000
684 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_CLR_MSK 0xbfffffff
686 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_RESET 0x0
688 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_GET(value) (((value) & 0x40000000) >> 30)
690 #define ALT_EMAC_DMA_BUS_MODE_RESERVED_30_SET(value) (((value) << 30) & 0x40000000)
711 #define ALT_EMAC_DMA_BUS_MODE_RIB_LSB 31
713 #define ALT_EMAC_DMA_BUS_MODE_RIB_MSB 31
715 #define ALT_EMAC_DMA_BUS_MODE_RIB_WIDTH 1
717 #define ALT_EMAC_DMA_BUS_MODE_RIB_SET_MSK 0x80000000
719 #define ALT_EMAC_DMA_BUS_MODE_RIB_CLR_MSK 0x7fffffff
721 #define ALT_EMAC_DMA_BUS_MODE_RIB_RESET 0x0
723 #define ALT_EMAC_DMA_BUS_MODE_RIB_GET(value) (((value) & 0x80000000) >> 31)
725 #define ALT_EMAC_DMA_BUS_MODE_RIB_SET(value) (((value) << 31) & 0x80000000)
738 struct ALT_EMAC_DMA_BUS_MODE_s
740 volatile uint32_t SWR : 1;
741 const volatile uint32_t DA : 1;
742 volatile uint32_t DSL : 5;
743 volatile uint32_t ATDS : 1;
744 volatile uint32_t PBL : 6;
745 const volatile uint32_t PR : 2;
746 volatile uint32_t FB : 1;
747 volatile uint32_t RPBL : 6;
748 volatile uint32_t USP : 1;
749 volatile uint32_t PBLx8 : 1;
750 volatile uint32_t AAL : 1;
751 const volatile uint32_t MB : 1;
752 const volatile uint32_t TXPR : 1;
753 const volatile uint32_t PRWG : 2;
754 const volatile uint32_t Reserved_30 : 1;
755 const volatile uint32_t RIB : 1;
759 typedef struct ALT_EMAC_DMA_BUS_MODE_s ALT_EMAC_DMA_BUS_MODE_t;
763 #define ALT_EMAC_DMA_BUS_MODE_RESET 0x00020101
765 #define ALT_EMAC_DMA_BUS_MODE_OFST 0x0
767 #define ALT_EMAC_DMA_BUS_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MODE_OFST))
804 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_LSB 0
806 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_MSB 31
808 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_WIDTH 32
810 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_SET_MSK 0xffffffff
812 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_CLR_MSK 0x00000000
814 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_RESET 0x0
816 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0)
818 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff)
831 struct ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_s
833 volatile uint32_t TPD : 32;
837 typedef struct ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_s ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_t;
841 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_RESET 0x00000000
843 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_OFST 0x4
845 #define ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_OFST))
880 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_LSB 0
882 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_MSB 31
884 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_WIDTH 32
886 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_SET_MSK 0xffffffff
888 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_CLR_MSK 0x00000000
890 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_RESET 0x0
892 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0)
894 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff)
907 struct ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_s
909 volatile uint32_t RPD : 32;
913 typedef struct ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_s ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_t;
917 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_RESET 0x00000000
919 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_OFST 0x8
921 #define ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_OFST))
961 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_LSB 0
963 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_MSB 1
965 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_WIDTH 2
967 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET_MSK 0x00000003
969 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_CLR_MSK 0xfffffffc
971 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_RESET 0x0
973 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_GET(value) (((value) & 0x00000003) >> 0)
975 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET(value) (((value) << 0) & 0x00000003)
991 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_LSB 2
993 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_MSB 31
995 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_WIDTH 30
997 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_SET_MSK 0xfffffffc
999 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_CLR_MSK 0x00000003
1001 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_RESET 0x0
1003 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
1005 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
1007 #ifndef __ASSEMBLY__
1018 struct ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_s
1020 const volatile uint32_t Reserved_1_0 : 2;
1021 volatile uint32_t RDESLA_32bit : 30;
1025 typedef struct ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_s ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_t;
1029 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RESET 0x00000000
1031 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST 0xc
1033 #define ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST))
1071 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_LSB 0
1073 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_MSB 1
1075 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_WIDTH 2
1077 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET_MSK 0x00000003
1079 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_CLR_MSK 0xfffffffc
1081 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_RESET 0x0
1083 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_GET(value) (((value) & 0x00000003) >> 0)
1085 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESERVED_1_0_SET(value) (((value) << 0) & 0x00000003)
1101 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_LSB 2
1103 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_MSB 31
1105 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_WIDTH 30
1107 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_SET_MSK 0xfffffffc
1109 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_CLR_MSK 0x00000003
1111 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_RESET 0x0
1113 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
1115 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
1117 #ifndef __ASSEMBLY__
1128 struct ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_s
1130 const volatile uint32_t Reserved_1_0 : 2;
1131 volatile uint32_t TDESLA_32bit : 30;
1135 typedef struct ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_s ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_t;
1139 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_RESET 0x00000000
1141 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST 0x10
1143 #define ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST))
1202 #define ALT_EMAC_DMA_STATUS_TI_LSB 0
1204 #define ALT_EMAC_DMA_STATUS_TI_MSB 0
1206 #define ALT_EMAC_DMA_STATUS_TI_WIDTH 1
1208 #define ALT_EMAC_DMA_STATUS_TI_SET_MSK 0x00000001
1210 #define ALT_EMAC_DMA_STATUS_TI_CLR_MSK 0xfffffffe
1212 #define ALT_EMAC_DMA_STATUS_TI_RESET 0x0
1214 #define ALT_EMAC_DMA_STATUS_TI_GET(value) (((value) & 0x00000001) >> 0)
1216 #define ALT_EMAC_DMA_STATUS_TI_SET(value) (((value) << 0) & 0x00000001)
1229 #define ALT_EMAC_DMA_STATUS_TPS_LSB 1
1231 #define ALT_EMAC_DMA_STATUS_TPS_MSB 1
1233 #define ALT_EMAC_DMA_STATUS_TPS_WIDTH 1
1235 #define ALT_EMAC_DMA_STATUS_TPS_SET_MSK 0x00000002
1237 #define ALT_EMAC_DMA_STATUS_TPS_CLR_MSK 0xfffffffd
1239 #define ALT_EMAC_DMA_STATUS_TPS_RESET 0x0
1241 #define ALT_EMAC_DMA_STATUS_TPS_GET(value) (((value) & 0x00000002) >> 1)
1243 #define ALT_EMAC_DMA_STATUS_TPS_SET(value) (((value) << 1) & 0x00000002)
1262 #define ALT_EMAC_DMA_STATUS_TU_LSB 2
1264 #define ALT_EMAC_DMA_STATUS_TU_MSB 2
1266 #define ALT_EMAC_DMA_STATUS_TU_WIDTH 1
1268 #define ALT_EMAC_DMA_STATUS_TU_SET_MSK 0x00000004
1270 #define ALT_EMAC_DMA_STATUS_TU_CLR_MSK 0xfffffffb
1272 #define ALT_EMAC_DMA_STATUS_TU_RESET 0x0
1274 #define ALT_EMAC_DMA_STATUS_TU_GET(value) (((value) & 0x00000004) >> 2)
1276 #define ALT_EMAC_DMA_STATUS_TU_SET(value) (((value) << 2) & 0x00000004)
1293 #define ALT_EMAC_DMA_STATUS_TJT_LSB 3
1295 #define ALT_EMAC_DMA_STATUS_TJT_MSB 3
1297 #define ALT_EMAC_DMA_STATUS_TJT_WIDTH 1
1299 #define ALT_EMAC_DMA_STATUS_TJT_SET_MSK 0x00000008
1301 #define ALT_EMAC_DMA_STATUS_TJT_CLR_MSK 0xfffffff7
1303 #define ALT_EMAC_DMA_STATUS_TJT_RESET 0x0
1305 #define ALT_EMAC_DMA_STATUS_TJT_GET(value) (((value) & 0x00000008) >> 3)
1307 #define ALT_EMAC_DMA_STATUS_TJT_SET(value) (((value) << 3) & 0x00000008)
1322 #define ALT_EMAC_DMA_STATUS_OVF_LSB 4
1324 #define ALT_EMAC_DMA_STATUS_OVF_MSB 4
1326 #define ALT_EMAC_DMA_STATUS_OVF_WIDTH 1
1328 #define ALT_EMAC_DMA_STATUS_OVF_SET_MSK 0x00000010
1330 #define ALT_EMAC_DMA_STATUS_OVF_CLR_MSK 0xffffffef
1332 #define ALT_EMAC_DMA_STATUS_OVF_RESET 0x0
1334 #define ALT_EMAC_DMA_STATUS_OVF_GET(value) (((value) & 0x00000010) >> 4)
1336 #define ALT_EMAC_DMA_STATUS_OVF_SET(value) (((value) << 4) & 0x00000010)
1350 #define ALT_EMAC_DMA_STATUS_UNF_LSB 5
1352 #define ALT_EMAC_DMA_STATUS_UNF_MSB 5
1354 #define ALT_EMAC_DMA_STATUS_UNF_WIDTH 1
1356 #define ALT_EMAC_DMA_STATUS_UNF_SET_MSK 0x00000020
1358 #define ALT_EMAC_DMA_STATUS_UNF_CLR_MSK 0xffffffdf
1360 #define ALT_EMAC_DMA_STATUS_UNF_RESET 0x0
1362 #define ALT_EMAC_DMA_STATUS_UNF_GET(value) (((value) & 0x00000020) >> 5)
1364 #define ALT_EMAC_DMA_STATUS_UNF_SET(value) (((value) << 5) & 0x00000020)
1382 #define ALT_EMAC_DMA_STATUS_RI_LSB 6
1384 #define ALT_EMAC_DMA_STATUS_RI_MSB 6
1386 #define ALT_EMAC_DMA_STATUS_RI_WIDTH 1
1388 #define ALT_EMAC_DMA_STATUS_RI_SET_MSK 0x00000040
1390 #define ALT_EMAC_DMA_STATUS_RI_CLR_MSK 0xffffffbf
1392 #define ALT_EMAC_DMA_STATUS_RI_RESET 0x0
1394 #define ALT_EMAC_DMA_STATUS_RI_GET(value) (((value) & 0x00000040) >> 6)
1396 #define ALT_EMAC_DMA_STATUS_RI_SET(value) (((value) << 6) & 0x00000040)
1415 #define ALT_EMAC_DMA_STATUS_RU_LSB 7
1417 #define ALT_EMAC_DMA_STATUS_RU_MSB 7
1419 #define ALT_EMAC_DMA_STATUS_RU_WIDTH 1
1421 #define ALT_EMAC_DMA_STATUS_RU_SET_MSK 0x00000080
1423 #define ALT_EMAC_DMA_STATUS_RU_CLR_MSK 0xffffff7f
1425 #define ALT_EMAC_DMA_STATUS_RU_RESET 0x0
1427 #define ALT_EMAC_DMA_STATUS_RU_GET(value) (((value) & 0x00000080) >> 7)
1429 #define ALT_EMAC_DMA_STATUS_RU_SET(value) (((value) << 7) & 0x00000080)
1442 #define ALT_EMAC_DMA_STATUS_RPS_LSB 8
1444 #define ALT_EMAC_DMA_STATUS_RPS_MSB 8
1446 #define ALT_EMAC_DMA_STATUS_RPS_WIDTH 1
1448 #define ALT_EMAC_DMA_STATUS_RPS_SET_MSK 0x00000100
1450 #define ALT_EMAC_DMA_STATUS_RPS_CLR_MSK 0xfffffeff
1452 #define ALT_EMAC_DMA_STATUS_RPS_RESET 0x0
1454 #define ALT_EMAC_DMA_STATUS_RPS_GET(value) (((value) & 0x00000100) >> 8)
1456 #define ALT_EMAC_DMA_STATUS_RPS_SET(value) (((value) << 8) & 0x00000100)
1471 #define ALT_EMAC_DMA_STATUS_RWT_LSB 9
1473 #define ALT_EMAC_DMA_STATUS_RWT_MSB 9
1475 #define ALT_EMAC_DMA_STATUS_RWT_WIDTH 1
1477 #define ALT_EMAC_DMA_STATUS_RWT_SET_MSK 0x00000200
1479 #define ALT_EMAC_DMA_STATUS_RWT_CLR_MSK 0xfffffdff
1481 #define ALT_EMAC_DMA_STATUS_RWT_RESET 0x0
1483 #define ALT_EMAC_DMA_STATUS_RWT_GET(value) (((value) & 0x00000200) >> 9)
1485 #define ALT_EMAC_DMA_STATUS_RWT_SET(value) (((value) << 9) & 0x00000200)
1499 #define ALT_EMAC_DMA_STATUS_ETI_LSB 10
1501 #define ALT_EMAC_DMA_STATUS_ETI_MSB 10
1503 #define ALT_EMAC_DMA_STATUS_ETI_WIDTH 1
1505 #define ALT_EMAC_DMA_STATUS_ETI_SET_MSK 0x00000400
1507 #define ALT_EMAC_DMA_STATUS_ETI_CLR_MSK 0xfffffbff
1509 #define ALT_EMAC_DMA_STATUS_ETI_RESET 0x0
1511 #define ALT_EMAC_DMA_STATUS_ETI_GET(value) (((value) & 0x00000400) >> 10)
1513 #define ALT_EMAC_DMA_STATUS_ETI_SET(value) (((value) << 10) & 0x00000400)
1524 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_LSB 11
1526 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_MSB 12
1528 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_WIDTH 2
1530 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_SET_MSK 0x00001800
1532 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_CLR_MSK 0xffffe7ff
1534 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_RESET 0x0
1536 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_GET(value) (((value) & 0x00001800) >> 11)
1538 #define ALT_EMAC_DMA_STATUS_RESERVED_12_11_SET(value) (((value) << 11) & 0x00001800)
1552 #define ALT_EMAC_DMA_STATUS_FBI_LSB 13
1554 #define ALT_EMAC_DMA_STATUS_FBI_MSB 13
1556 #define ALT_EMAC_DMA_STATUS_FBI_WIDTH 1
1558 #define ALT_EMAC_DMA_STATUS_FBI_SET_MSK 0x00002000
1560 #define ALT_EMAC_DMA_STATUS_FBI_CLR_MSK 0xffffdfff
1562 #define ALT_EMAC_DMA_STATUS_FBI_RESET 0x0
1564 #define ALT_EMAC_DMA_STATUS_FBI_GET(value) (((value) & 0x00002000) >> 13)
1566 #define ALT_EMAC_DMA_STATUS_FBI_SET(value) (((value) << 13) & 0x00002000)
1581 #define ALT_EMAC_DMA_STATUS_ERI_LSB 14
1583 #define ALT_EMAC_DMA_STATUS_ERI_MSB 14
1585 #define ALT_EMAC_DMA_STATUS_ERI_WIDTH 1
1587 #define ALT_EMAC_DMA_STATUS_ERI_SET_MSK 0x00004000
1589 #define ALT_EMAC_DMA_STATUS_ERI_CLR_MSK 0xffffbfff
1591 #define ALT_EMAC_DMA_STATUS_ERI_RESET 0x0
1593 #define ALT_EMAC_DMA_STATUS_ERI_GET(value) (((value) & 0x00004000) >> 14)
1595 #define ALT_EMAC_DMA_STATUS_ERI_SET(value) (((value) << 14) & 0x00004000)
1633 #define ALT_EMAC_DMA_STATUS_AIS_LSB 15
1635 #define ALT_EMAC_DMA_STATUS_AIS_MSB 15
1637 #define ALT_EMAC_DMA_STATUS_AIS_WIDTH 1
1639 #define ALT_EMAC_DMA_STATUS_AIS_SET_MSK 0x00008000
1641 #define ALT_EMAC_DMA_STATUS_AIS_CLR_MSK 0xffff7fff
1643 #define ALT_EMAC_DMA_STATUS_AIS_RESET 0x0
1645 #define ALT_EMAC_DMA_STATUS_AIS_GET(value) (((value) & 0x00008000) >> 15)
1647 #define ALT_EMAC_DMA_STATUS_AIS_SET(value) (((value) << 15) & 0x00008000)
1676 #define ALT_EMAC_DMA_STATUS_NIS_LSB 16
1678 #define ALT_EMAC_DMA_STATUS_NIS_MSB 16
1680 #define ALT_EMAC_DMA_STATUS_NIS_WIDTH 1
1682 #define ALT_EMAC_DMA_STATUS_NIS_SET_MSK 0x00010000
1684 #define ALT_EMAC_DMA_STATUS_NIS_CLR_MSK 0xfffeffff
1686 #define ALT_EMAC_DMA_STATUS_NIS_RESET 0x0
1688 #define ALT_EMAC_DMA_STATUS_NIS_GET(value) (((value) & 0x00010000) >> 16)
1690 #define ALT_EMAC_DMA_STATUS_NIS_SET(value) (((value) << 16) & 0x00010000)
1721 #define ALT_EMAC_DMA_STATUS_RS_LSB 17
1723 #define ALT_EMAC_DMA_STATUS_RS_MSB 19
1725 #define ALT_EMAC_DMA_STATUS_RS_WIDTH 3
1727 #define ALT_EMAC_DMA_STATUS_RS_SET_MSK 0x000e0000
1729 #define ALT_EMAC_DMA_STATUS_RS_CLR_MSK 0xfff1ffff
1731 #define ALT_EMAC_DMA_STATUS_RS_RESET 0x0
1733 #define ALT_EMAC_DMA_STATUS_RS_GET(value) (((value) & 0x000e0000) >> 17)
1735 #define ALT_EMAC_DMA_STATUS_RS_SET(value) (((value) << 17) & 0x000e0000)
1767 #define ALT_EMAC_DMA_STATUS_TS_LSB 20
1769 #define ALT_EMAC_DMA_STATUS_TS_MSB 22
1771 #define ALT_EMAC_DMA_STATUS_TS_WIDTH 3
1773 #define ALT_EMAC_DMA_STATUS_TS_SET_MSK 0x00700000
1775 #define ALT_EMAC_DMA_STATUS_TS_CLR_MSK 0xff8fffff
1777 #define ALT_EMAC_DMA_STATUS_TS_RESET 0x0
1779 #define ALT_EMAC_DMA_STATUS_TS_GET(value) (((value) & 0x00700000) >> 20)
1781 #define ALT_EMAC_DMA_STATUS_TS_SET(value) (((value) << 20) & 0x00700000)
1810 #define ALT_EMAC_DMA_STATUS_EB_LSB 23
1812 #define ALT_EMAC_DMA_STATUS_EB_MSB 25
1814 #define ALT_EMAC_DMA_STATUS_EB_WIDTH 3
1816 #define ALT_EMAC_DMA_STATUS_EB_SET_MSK 0x03800000
1818 #define ALT_EMAC_DMA_STATUS_EB_CLR_MSK 0xfc7fffff
1820 #define ALT_EMAC_DMA_STATUS_EB_RESET 0x0
1822 #define ALT_EMAC_DMA_STATUS_EB_GET(value) (((value) & 0x03800000) >> 23)
1824 #define ALT_EMAC_DMA_STATUS_EB_SET(value) (((value) << 23) & 0x03800000)
1861 #define ALT_EMAC_DMA_STATUS_GLI_LSB 26
1863 #define ALT_EMAC_DMA_STATUS_GLI_MSB 26
1865 #define ALT_EMAC_DMA_STATUS_GLI_WIDTH 1
1867 #define ALT_EMAC_DMA_STATUS_GLI_SET_MSK 0x04000000
1869 #define ALT_EMAC_DMA_STATUS_GLI_CLR_MSK 0xfbffffff
1871 #define ALT_EMAC_DMA_STATUS_GLI_RESET 0x0
1873 #define ALT_EMAC_DMA_STATUS_GLI_GET(value) (((value) & 0x04000000) >> 26)
1875 #define ALT_EMAC_DMA_STATUS_GLI_SET(value) (((value) << 26) & 0x04000000)
1895 #define ALT_EMAC_DMA_STATUS_GMI_LSB 27
1897 #define ALT_EMAC_DMA_STATUS_GMI_MSB 27
1899 #define ALT_EMAC_DMA_STATUS_GMI_WIDTH 1
1901 #define ALT_EMAC_DMA_STATUS_GMI_SET_MSK 0x08000000
1903 #define ALT_EMAC_DMA_STATUS_GMI_CLR_MSK 0xf7ffffff
1905 #define ALT_EMAC_DMA_STATUS_GMI_RESET 0x0
1907 #define ALT_EMAC_DMA_STATUS_GMI_GET(value) (((value) & 0x08000000) >> 27)
1909 #define ALT_EMAC_DMA_STATUS_GMI_SET(value) (((value) << 27) & 0x08000000)
1932 #define ALT_EMAC_DMA_STATUS_GPI_LSB 28
1934 #define ALT_EMAC_DMA_STATUS_GPI_MSB 28
1936 #define ALT_EMAC_DMA_STATUS_GPI_WIDTH 1
1938 #define ALT_EMAC_DMA_STATUS_GPI_SET_MSK 0x10000000
1940 #define ALT_EMAC_DMA_STATUS_GPI_CLR_MSK 0xefffffff
1942 #define ALT_EMAC_DMA_STATUS_GPI_RESET 0x0
1944 #define ALT_EMAC_DMA_STATUS_GPI_GET(value) (((value) & 0x10000000) >> 28)
1946 #define ALT_EMAC_DMA_STATUS_GPI_SET(value) (((value) << 28) & 0x10000000)
1966 #define ALT_EMAC_DMA_STATUS_TTI_LSB 29
1968 #define ALT_EMAC_DMA_STATUS_TTI_MSB 29
1970 #define ALT_EMAC_DMA_STATUS_TTI_WIDTH 1
1972 #define ALT_EMAC_DMA_STATUS_TTI_SET_MSK 0x20000000
1974 #define ALT_EMAC_DMA_STATUS_TTI_CLR_MSK 0xdfffffff
1976 #define ALT_EMAC_DMA_STATUS_TTI_RESET 0x0
1978 #define ALT_EMAC_DMA_STATUS_TTI_GET(value) (((value) & 0x20000000) >> 29)
1980 #define ALT_EMAC_DMA_STATUS_TTI_SET(value) (((value) << 29) & 0x20000000)
2000 #define ALT_EMAC_DMA_STATUS_GLPII_LSB 30
2002 #define ALT_EMAC_DMA_STATUS_GLPII_MSB 30
2004 #define ALT_EMAC_DMA_STATUS_GLPII_WIDTH 1
2006 #define ALT_EMAC_DMA_STATUS_GLPII_SET_MSK 0x40000000
2008 #define ALT_EMAC_DMA_STATUS_GLPII_CLR_MSK 0xbfffffff
2010 #define ALT_EMAC_DMA_STATUS_GLPII_RESET 0x0
2012 #define ALT_EMAC_DMA_STATUS_GLPII_GET(value) (((value) & 0x40000000) >> 30)
2014 #define ALT_EMAC_DMA_STATUS_GLPII_SET(value) (((value) << 30) & 0x40000000)
2025 #define ALT_EMAC_DMA_STATUS_RESERVED_31_LSB 31
2027 #define ALT_EMAC_DMA_STATUS_RESERVED_31_MSB 31
2029 #define ALT_EMAC_DMA_STATUS_RESERVED_31_WIDTH 1
2031 #define ALT_EMAC_DMA_STATUS_RESERVED_31_SET_MSK 0x80000000
2033 #define ALT_EMAC_DMA_STATUS_RESERVED_31_CLR_MSK 0x7fffffff
2035 #define ALT_EMAC_DMA_STATUS_RESERVED_31_RESET 0x0
2037 #define ALT_EMAC_DMA_STATUS_RESERVED_31_GET(value) (((value) & 0x80000000) >> 31)
2039 #define ALT_EMAC_DMA_STATUS_RESERVED_31_SET(value) (((value) << 31) & 0x80000000)
2041 #ifndef __ASSEMBLY__
2052 struct ALT_EMAC_DMA_STATUS_s
2054 volatile uint32_t TI : 1;
2055 volatile uint32_t TPS : 1;
2056 volatile uint32_t TU : 1;
2057 volatile uint32_t TJT : 1;
2058 volatile uint32_t OVF : 1;
2059 volatile uint32_t UNF : 1;
2060 volatile uint32_t RI : 1;
2061 volatile uint32_t RU : 1;
2062 volatile uint32_t RPS : 1;
2063 volatile uint32_t RWT : 1;
2064 volatile uint32_t ETI : 1;
2065 const volatile uint32_t Reserved_12_11 : 2;
2066 volatile uint32_t FBI : 1;
2067 volatile uint32_t ERI : 1;
2068 volatile uint32_t AIS : 1;
2069 volatile uint32_t NIS : 1;
2070 const volatile uint32_t RS : 3;
2071 const volatile uint32_t TS : 3;
2072 const volatile uint32_t EB : 3;
2073 const volatile uint32_t GLI : 1;
2074 const volatile uint32_t GMI : 1;
2075 const volatile uint32_t GPI : 1;
2076 const volatile uint32_t TTI : 1;
2077 const volatile uint32_t GLPII : 1;
2078 const volatile uint32_t Reserved_31 : 1;
2082 typedef struct ALT_EMAC_DMA_STATUS_s ALT_EMAC_DMA_STATUS_t;
2086 #define ALT_EMAC_DMA_STATUS_RESET 0x00000000
2088 #define ALT_EMAC_DMA_STATUS_OFST 0x14
2090 #define ALT_EMAC_DMA_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STATUS_OFST))
2138 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_LSB 0
2140 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_MSB 0
2142 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_WIDTH 1
2144 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_SET_MSK 0x00000001
2146 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_CLR_MSK 0xfffffffe
2148 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_RESET 0x0
2150 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_GET(value) (((value) & 0x00000001) >> 0)
2152 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_0_SET(value) (((value) << 0) & 0x00000001)
2180 #define ALT_EMAC_DMA_OPERATION_MODE_SR_LSB 1
2182 #define ALT_EMAC_DMA_OPERATION_MODE_SR_MSB 1
2184 #define ALT_EMAC_DMA_OPERATION_MODE_SR_WIDTH 1
2186 #define ALT_EMAC_DMA_OPERATION_MODE_SR_SET_MSK 0x00000002
2188 #define ALT_EMAC_DMA_OPERATION_MODE_SR_CLR_MSK 0xfffffffd
2190 #define ALT_EMAC_DMA_OPERATION_MODE_SR_RESET 0x0
2192 #define ALT_EMAC_DMA_OPERATION_MODE_SR_GET(value) (((value) & 0x00000002) >> 1)
2194 #define ALT_EMAC_DMA_OPERATION_MODE_SR_SET(value) (((value) << 1) & 0x00000002)
2208 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_LSB 2
2210 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_MSB 2
2212 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_WIDTH 1
2214 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_SET_MSK 0x00000004
2216 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_CLR_MSK 0xfffffffb
2218 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_RESET 0x0
2220 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_GET(value) (((value) & 0x00000004) >> 2)
2222 #define ALT_EMAC_DMA_OPERATION_MODE_OSF_SET(value) (((value) << 2) & 0x00000004)
2250 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_LSB 3
2252 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_MSB 4
2254 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_WIDTH 2
2256 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_SET_MSK 0x00000018
2258 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_CLR_MSK 0xffffffe7
2260 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_RESET 0x0
2262 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_GET(value) (((value) & 0x00000018) >> 3)
2264 #define ALT_EMAC_DMA_OPERATION_MODE_RTC_SET(value) (((value) << 3) & 0x00000018)
2292 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_LSB 5
2294 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_MSB 5
2296 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_WIDTH 1
2298 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_SET_MSK 0x00000020
2300 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_CLR_MSK 0xffffffdf
2302 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_RESET 0x0
2304 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_GET(value) (((value) & 0x00000020) >> 5)
2306 #define ALT_EMAC_DMA_OPERATION_MODE_DGF_SET(value) (((value) << 5) & 0x00000020)
2324 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_LSB 6
2326 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_MSB 6
2328 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_WIDTH 1
2330 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_SET_MSK 0x00000040
2332 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_CLR_MSK 0xffffffbf
2334 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_RESET 0x0
2336 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_GET(value) (((value) & 0x00000040) >> 6)
2338 #define ALT_EMAC_DMA_OPERATION_MODE_FUF_SET(value) (((value) << 6) & 0x00000040)
2380 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_LSB 7
2382 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_MSB 7
2384 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_WIDTH 1
2386 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_SET_MSK 0x00000080
2388 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_CLR_MSK 0xffffff7f
2390 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_RESET 0x0
2392 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_GET(value) (((value) & 0x00000080) >> 7)
2394 #define ALT_EMAC_DMA_OPERATION_MODE_FEF_SET(value) (((value) << 7) & 0x00000080)
2409 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_LSB 8
2411 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_MSB 8
2413 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_WIDTH 1
2415 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_SET_MSK 0x00000100
2417 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_CLR_MSK 0xfffffeff
2419 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_RESET 0x0
2421 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_GET(value) (((value) & 0x00000100) >> 8)
2423 #define ALT_EMAC_DMA_OPERATION_MODE_EFC_SET(value) (((value) << 8) & 0x00000100)
2454 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_LSB 9
2456 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_MSB 10
2458 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_WIDTH 2
2460 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_SET_MSK 0x00000600
2462 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_CLR_MSK 0xfffff9ff
2464 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_RESET 0x0
2466 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_GET(value) (((value) & 0x00000600) >> 9)
2468 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_SET(value) (((value) << 9) & 0x00000600)
2498 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_LSB 11
2500 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_MSB 12
2502 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_WIDTH 2
2504 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_SET_MSK 0x00001800
2506 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_CLR_MSK 0xffffe7ff
2508 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_RESET 0x0
2510 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_GET(value) (((value) & 0x00001800) >> 11)
2512 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_SET(value) (((value) << 11) & 0x00001800)
2544 #define ALT_EMAC_DMA_OPERATION_MODE_ST_LSB 13
2546 #define ALT_EMAC_DMA_OPERATION_MODE_ST_MSB 13
2548 #define ALT_EMAC_DMA_OPERATION_MODE_ST_WIDTH 1
2550 #define ALT_EMAC_DMA_OPERATION_MODE_ST_SET_MSK 0x00002000
2552 #define ALT_EMAC_DMA_OPERATION_MODE_ST_CLR_MSK 0xffffdfff
2554 #define ALT_EMAC_DMA_OPERATION_MODE_ST_RESET 0x0
2556 #define ALT_EMAC_DMA_OPERATION_MODE_ST_GET(value) (((value) & 0x00002000) >> 13)
2558 #define ALT_EMAC_DMA_OPERATION_MODE_ST_SET(value) (((value) << 13) & 0x00002000)
2590 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_LSB 14
2592 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_MSB 16
2594 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_WIDTH 3
2596 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_SET_MSK 0x0001c000
2598 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_CLR_MSK 0xfffe3fff
2600 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_RESET 0x0
2602 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_GET(value) (((value) & 0x0001c000) >> 14)
2604 #define ALT_EMAC_DMA_OPERATION_MODE_TTC_SET(value) (((value) << 14) & 0x0001c000)
2615 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_LSB 17
2617 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_MSB 19
2619 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_WIDTH 3
2621 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_SET_MSK 0x000e0000
2623 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_CLR_MSK 0xfff1ffff
2625 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_RESET 0x0
2627 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_GET(value) (((value) & 0x000e0000) >> 17)
2629 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_19_17_SET(value) (((value) << 17) & 0x000e0000)
2652 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_LSB 20
2654 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_MSB 20
2656 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_WIDTH 1
2658 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_SET_MSK 0x00100000
2660 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_CLR_MSK 0xffefffff
2662 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_RESET 0x0
2664 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_GET(value) (((value) & 0x00100000) >> 20)
2666 #define ALT_EMAC_DMA_OPERATION_MODE_FTF_SET(value) (((value) << 20) & 0x00100000)
2681 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_LSB 21
2683 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_MSB 21
2685 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_WIDTH 1
2687 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_SET_MSK 0x00200000
2689 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_CLR_MSK 0xffdfffff
2691 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_RESET 0x0
2693 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_GET(value) (((value) & 0x00200000) >> 21)
2695 #define ALT_EMAC_DMA_OPERATION_MODE_TSF_SET(value) (((value) << 21) & 0x00200000)
2722 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_LSB 22
2724 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_MSB 22
2726 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_WIDTH 1
2728 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_SET_MSK 0x00400000
2730 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_CLR_MSK 0xffbfffff
2732 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_RESET 0x0
2734 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_GET(value) (((value) & 0x00400000) >> 22)
2736 #define ALT_EMAC_DMA_OPERATION_MODE_RFD_2_SET(value) (((value) << 22) & 0x00400000)
2763 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_LSB 23
2765 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_MSB 23
2767 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_WIDTH 1
2769 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_SET_MSK 0x00800000
2771 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_CLR_MSK 0xff7fffff
2773 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_RESET 0x0
2775 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_GET(value) (((value) & 0x00800000) >> 23)
2777 #define ALT_EMAC_DMA_OPERATION_MODE_RFA_2_SET(value) (((value) << 23) & 0x00800000)
2794 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_LSB 24
2796 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_MSB 24
2798 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_WIDTH 1
2800 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_SET_MSK 0x01000000
2802 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_CLR_MSK 0xfeffffff
2804 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_RESET 0x0
2806 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_GET(value) (((value) & 0x01000000) >> 24)
2808 #define ALT_EMAC_DMA_OPERATION_MODE_DFF_SET(value) (((value) << 24) & 0x01000000)
2824 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_LSB 25
2826 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_MSB 25
2828 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_WIDTH 1
2830 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_SET_MSK 0x02000000
2832 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_CLR_MSK 0xfdffffff
2834 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_RESET 0x0
2836 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_GET(value) (((value) & 0x02000000) >> 25)
2838 #define ALT_EMAC_DMA_OPERATION_MODE_RSF_SET(value) (((value) << 25) & 0x02000000)
2858 #define ALT_EMAC_DMA_OPERATION_MODE_DT_LSB 26
2860 #define ALT_EMAC_DMA_OPERATION_MODE_DT_MSB 26
2862 #define ALT_EMAC_DMA_OPERATION_MODE_DT_WIDTH 1
2864 #define ALT_EMAC_DMA_OPERATION_MODE_DT_SET_MSK 0x04000000
2866 #define ALT_EMAC_DMA_OPERATION_MODE_DT_CLR_MSK 0xfbffffff
2868 #define ALT_EMAC_DMA_OPERATION_MODE_DT_RESET 0x0
2870 #define ALT_EMAC_DMA_OPERATION_MODE_DT_GET(value) (((value) & 0x04000000) >> 26)
2872 #define ALT_EMAC_DMA_OPERATION_MODE_DT_SET(value) (((value) << 26) & 0x04000000)
2883 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_LSB 27
2885 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_MSB 31
2887 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_WIDTH 5
2889 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_SET_MSK 0xf8000000
2891 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_CLR_MSK 0x07ffffff
2893 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_RESET 0x0
2895 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_GET(value) (((value) & 0xf8000000) >> 27)
2897 #define ALT_EMAC_DMA_OPERATION_MODE_RESERVED_31_27_SET(value) (((value) << 27) & 0xf8000000)
2899 #ifndef __ASSEMBLY__
2910 struct ALT_EMAC_DMA_OPERATION_MODE_s
2912 const volatile uint32_t Reserved_0 : 1;
2913 volatile uint32_t SR : 1;
2914 volatile uint32_t OSF : 1;
2915 volatile uint32_t RTC : 2;
2916 volatile uint32_t DGF : 1;
2917 volatile uint32_t FUF : 1;
2918 volatile uint32_t FEF : 1;
2919 volatile uint32_t EFC : 1;
2920 volatile uint32_t RFA : 2;
2921 volatile uint32_t RFD : 2;
2922 volatile uint32_t ST : 1;
2923 volatile uint32_t TTC : 3;
2924 const volatile uint32_t Reserved_19_17 : 3;
2925 volatile uint32_t FTF : 1;
2926 volatile uint32_t TSF : 1;
2927 volatile uint32_t RFD_2 : 1;
2928 volatile uint32_t RFA_2 : 1;
2929 volatile uint32_t DFF : 1;
2930 volatile uint32_t RSF : 1;
2931 volatile uint32_t DT : 1;
2932 const volatile uint32_t Reserved_31_27 : 5;
2936 typedef struct ALT_EMAC_DMA_OPERATION_MODE_s ALT_EMAC_DMA_OPERATION_MODE_t;
2940 #define ALT_EMAC_DMA_OPERATION_MODE_RESET 0x00000000
2942 #define ALT_EMAC_DMA_OPERATION_MODE_OFST 0x18
2944 #define ALT_EMAC_DMA_OPERATION_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OPERATION_MODE_OFST))
2991 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_LSB 0
2993 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_MSB 0
2995 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_WIDTH 1
2997 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_SET_MSK 0x00000001
2999 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_CLR_MSK 0xfffffffe
3001 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_RESET 0x0
3003 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_GET(value) (((value) & 0x00000001) >> 0)
3005 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TIE_SET(value) (((value) << 0) & 0x00000001)
3020 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_LSB 1
3022 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_MSB 1
3024 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_WIDTH 1
3026 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_SET_MSK 0x00000002
3028 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_CLR_MSK 0xfffffffd
3030 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_RESET 0x0
3032 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_GET(value) (((value) & 0x00000002) >> 1)
3034 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TSE_SET(value) (((value) << 1) & 0x00000002)
3049 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_LSB 2
3051 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_MSB 2
3053 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_WIDTH 1
3055 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_SET_MSK 0x00000004
3057 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_CLR_MSK 0xfffffffb
3059 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_RESET 0x0
3061 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_GET(value) (((value) & 0x00000004) >> 2)
3063 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TUE_SET(value) (((value) << 2) & 0x00000004)
3078 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_LSB 3
3080 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_MSB 3
3082 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_WIDTH 1
3084 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_SET_MSK 0x00000008
3086 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_CLR_MSK 0xfffffff7
3088 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_RESET 0x0
3090 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_GET(value) (((value) & 0x00000008) >> 3)
3092 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_TJE_SET(value) (((value) << 3) & 0x00000008)
3107 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_LSB 4
3109 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_MSB 4
3111 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_WIDTH 1
3113 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_SET_MSK 0x00000010
3115 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_CLR_MSK 0xffffffef
3117 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_RESET 0x0
3119 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_GET(value) (((value) & 0x00000010) >> 4)
3121 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OVE_SET(value) (((value) << 4) & 0x00000010)
3136 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_LSB 5
3138 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_MSB 5
3140 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_WIDTH 1
3142 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_SET_MSK 0x00000020
3144 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_CLR_MSK 0xffffffdf
3146 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_RESET 0x0
3148 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_GET(value) (((value) & 0x00000020) >> 5)
3150 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_UNE_SET(value) (((value) << 5) & 0x00000020)
3164 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_LSB 6
3166 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_MSB 6
3168 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_WIDTH 1
3170 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_SET_MSK 0x00000040
3172 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_CLR_MSK 0xffffffbf
3174 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_RESET 0x0
3176 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_GET(value) (((value) & 0x00000040) >> 6)
3178 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RIE_SET(value) (((value) << 6) & 0x00000040)
3193 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_LSB 7
3195 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_MSB 7
3197 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_WIDTH 1
3199 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_SET_MSK 0x00000080
3201 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_CLR_MSK 0xffffff7f
3203 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_RESET 0x0
3205 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_GET(value) (((value) & 0x00000080) >> 7)
3207 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RUE_SET(value) (((value) << 7) & 0x00000080)
3222 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_LSB 8
3224 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_MSB 8
3226 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_WIDTH 1
3228 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_SET_MSK 0x00000100
3230 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_CLR_MSK 0xfffffeff
3232 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_RESET 0x0
3234 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_GET(value) (((value) & 0x00000100) >> 8)
3236 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RSE_SET(value) (((value) << 8) & 0x00000100)
3251 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_LSB 9
3253 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_MSB 9
3255 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_WIDTH 1
3257 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_SET_MSK 0x00000200
3259 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_CLR_MSK 0xfffffdff
3261 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_RESET 0x0
3263 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_GET(value) (((value) & 0x00000200) >> 9)
3265 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RWE_SET(value) (((value) << 9) & 0x00000200)
3280 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_LSB 10
3282 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_MSB 10
3284 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_WIDTH 1
3286 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_SET_MSK 0x00000400
3288 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_CLR_MSK 0xfffffbff
3290 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_RESET 0x0
3292 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_GET(value) (((value) & 0x00000400) >> 10)
3294 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ETE_SET(value) (((value) << 10) & 0x00000400)
3305 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_LSB 11
3307 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_MSB 12
3309 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_WIDTH 2
3311 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_SET_MSK 0x00001800
3313 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_CLR_MSK 0xffffe7ff
3315 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_RESET 0x0
3317 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_GET(value) (((value) & 0x00001800) >> 11)
3319 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_12_11_SET(value) (((value) << 11) & 0x00001800)
3334 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_LSB 13
3336 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_MSB 13
3338 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_WIDTH 1
3340 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_SET_MSK 0x00002000
3342 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_CLR_MSK 0xffffdfff
3344 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_RESET 0x0
3346 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_GET(value) (((value) & 0x00002000) >> 13)
3348 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_FBE_SET(value) (((value) << 13) & 0x00002000)
3363 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_LSB 14
3365 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_MSB 14
3367 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_WIDTH 1
3369 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_SET_MSK 0x00004000
3371 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_CLR_MSK 0xffffbfff
3373 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_RESET 0x0
3375 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_GET(value) (((value) & 0x00004000) >> 14)
3377 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ERE_SET(value) (((value) << 14) & 0x00004000)
3410 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_LSB 15
3412 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_MSB 15
3414 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_WIDTH 1
3416 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_SET_MSK 0x00008000
3418 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_CLR_MSK 0xffff7fff
3420 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_RESET 0x0
3422 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_GET(value) (((value) & 0x00008000) >> 15)
3424 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_AIE_SET(value) (((value) << 15) & 0x00008000)
3447 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_LSB 16
3449 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_MSB 16
3451 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_WIDTH 1
3453 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_SET_MSK 0x00010000
3455 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_CLR_MSK 0xfffeffff
3457 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_RESET 0x0
3459 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_GET(value) (((value) & 0x00010000) >> 16)
3461 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_NIE_SET(value) (((value) << 16) & 0x00010000)
3472 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_LSB 17
3474 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_MSB 31
3476 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_WIDTH 15
3478 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_SET_MSK 0xfffe0000
3480 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_CLR_MSK 0x0001ffff
3482 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_RESET 0x0
3484 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_GET(value) (((value) & 0xfffe0000) >> 17)
3486 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESERVED_31_17_SET(value) (((value) << 17) & 0xfffe0000)
3488 #ifndef __ASSEMBLY__
3499 struct ALT_EMAC_DMA_INTERRUPT_ENABLE_s
3501 volatile uint32_t TIE : 1;
3502 volatile uint32_t TSE : 1;
3503 volatile uint32_t TUE : 1;
3504 volatile uint32_t TJE : 1;
3505 volatile uint32_t OVE : 1;
3506 volatile uint32_t UNE : 1;
3507 volatile uint32_t RIE : 1;
3508 volatile uint32_t RUE : 1;
3509 volatile uint32_t RSE : 1;
3510 volatile uint32_t RWE : 1;
3511 volatile uint32_t ETE : 1;
3512 const volatile uint32_t Reserved_12_11 : 2;
3513 volatile uint32_t FBE : 1;
3514 volatile uint32_t ERE : 1;
3515 volatile uint32_t AIE : 1;
3516 volatile uint32_t NIE : 1;
3517 const volatile uint32_t Reserved_31_17 : 15;
3521 typedef struct ALT_EMAC_DMA_INTERRUPT_ENABLE_s ALT_EMAC_DMA_INTERRUPT_ENABLE_t;
3525 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_RESET 0x00000000
3527 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_OFST 0x1c
3529 #define ALT_EMAC_DMA_INTERRUPT_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INTERRUPT_ENABLE_OFST))
3568 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_LSB 0
3570 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_MSB 15
3572 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_WIDTH 16
3574 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_SET_MSK 0x0000ffff
3576 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_CLR_MSK 0xffff0000
3578 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_RESET 0x0
3580 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0)
3582 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff)
3599 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_LSB 16
3601 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_MSB 16
3603 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_WIDTH 1
3605 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_SET_MSK 0x00010000
3607 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_CLR_MSK 0xfffeffff
3609 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_RESET 0x0
3611 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16)
3613 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000)
3628 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_LSB 17
3630 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_MSB 27
3632 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_WIDTH 11
3634 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_SET_MSK 0x0ffe0000
3636 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_CLR_MSK 0xf001ffff
3638 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_RESET 0x0
3640 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17)
3642 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000)
3658 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_LSB 28
3660 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_MSB 28
3662 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_WIDTH 1
3664 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_SET_MSK 0x10000000
3666 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_CLR_MSK 0xefffffff
3668 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_RESET 0x0
3670 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28)
3672 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000)
3683 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_LSB 29
3685 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_MSB 31
3687 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_WIDTH 3
3689 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_SET_MSK 0xe0000000
3691 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_CLR_MSK 0x1fffffff
3693 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_RESET 0x0
3695 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_GET(value) (((value) & 0xe0000000) >> 29)
3697 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESERVED_31_29_SET(value) (((value) << 29) & 0xe0000000)
3699 #ifndef __ASSEMBLY__
3710 struct ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_s
3712 const volatile uint32_t MISFRMCNT : 16;
3713 const volatile uint32_t MISCNTOVF : 1;
3714 const volatile uint32_t OVFFRMCNT : 11;
3715 const volatile uint32_t OVFCNTOVF : 1;
3716 const volatile uint32_t Reserved_31_29 : 3;
3720 typedef struct ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_s ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_t;
3724 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_RESET 0x00000000
3726 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OFST 0x20
3728 #define ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OFST))
3763 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_LSB 0
3765 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_MSB 7
3767 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_WIDTH 8
3769 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_SET_MSK 0x000000ff
3771 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_CLR_MSK 0xffffff00
3773 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_RESET 0x0
3775 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_GET(value) (((value) & 0x000000ff) >> 0)
3777 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_SET(value) (((value) << 0) & 0x000000ff)
3788 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_LSB 8
3790 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_MSB 31
3792 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_WIDTH 24
3794 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_SET_MSK 0xffffff00
3796 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_CLR_MSK 0x000000ff
3798 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_RESET 0x0
3800 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_GET(value) (((value) & 0xffffff00) >> 8)
3802 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESERVED_31_8_SET(value) (((value) << 8) & 0xffffff00)
3804 #ifndef __ASSEMBLY__
3815 struct ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_s
3817 volatile uint32_t RIWT : 8;
3818 const volatile uint32_t Reserved_31_8 : 24;
3822 typedef struct ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_s ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_t;
3826 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RESET 0x00000000
3828 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFST 0x24
3830 #define ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFST))
3889 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_LSB 0
3891 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_MSB 0
3893 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_WIDTH 1
3895 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_SET_MSK 0x00000001
3897 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_CLR_MSK 0xfffffffe
3899 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_RESET 0x1
3901 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_GET(value) (((value) & 0x00000001) >> 0)
3903 #define ALT_EMAC_DMA_AXI_BUS_MODE_UNDEF_SET(value) (((value) << 0) & 0x00000001)
3919 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_LSB 1
3921 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_MSB 1
3923 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_WIDTH 1
3925 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_SET_MSK 0x00000002
3927 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_CLR_MSK 0xfffffffd
3929 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_RESET 0x0
3931 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_GET(value) (((value) & 0x00000002) >> 1)
3933 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN4_SET(value) (((value) << 1) & 0x00000002)
3949 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_LSB 2
3951 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_MSB 2
3953 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_WIDTH 1
3955 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_SET_MSK 0x00000004
3957 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_CLR_MSK 0xfffffffb
3959 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_RESET 0x0
3961 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_GET(value) (((value) & 0x00000004) >> 2)
3963 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN8_SET(value) (((value) << 2) & 0x00000004)
3977 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_LSB 3
3979 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_MSB 3
3981 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_WIDTH 1
3983 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_SET_MSK 0x00000008
3985 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_CLR_MSK 0xfffffff7
3987 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_RESET 0x0
3989 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_GET(value) (((value) & 0x00000008) >> 3)
3991 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN16_SET(value) (((value) << 3) & 0x00000008)
4008 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_LSB 4
4010 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_MSB 4
4012 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_WIDTH 1
4014 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_SET_MSK 0x00000010
4016 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_CLR_MSK 0xffffffef
4018 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_RESET 0x0
4020 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_GET(value) (((value) & 0x00000010) >> 4)
4022 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN32_SET(value) (((value) << 4) & 0x00000010)
4039 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_LSB 5
4041 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_MSB 5
4043 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_WIDTH 1
4045 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_SET_MSK 0x00000020
4047 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_CLR_MSK 0xffffffdf
4049 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_RESET 0x0
4051 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_GET(value) (((value) & 0x00000020) >> 5)
4053 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN64_SET(value) (((value) << 5) & 0x00000020)
4070 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_LSB 6
4072 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_MSB 6
4074 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_WIDTH 1
4076 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_SET_MSK 0x00000040
4078 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_CLR_MSK 0xffffffbf
4080 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_RESET 0x0
4082 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_GET(value) (((value) & 0x00000040) >> 6)
4084 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN128_SET(value) (((value) << 6) & 0x00000040)
4101 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_LSB 7
4103 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_MSB 7
4105 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_WIDTH 1
4107 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_SET_MSK 0x00000080
4109 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_CLR_MSK 0xffffff7f
4111 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_RESET 0x0
4113 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_GET(value) (((value) & 0x00000080) >> 7)
4115 #define ALT_EMAC_DMA_AXI_BUS_MODE_BLEN256_SET(value) (((value) << 7) & 0x00000080)
4126 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_LSB 8
4128 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_MSB 11
4130 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_WIDTH 4
4132 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_SET_MSK 0x00000f00
4134 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_CLR_MSK 0xfffff0ff
4136 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_RESET 0x0
4138 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_GET(value) (((value) & 0x00000f00) >> 8)
4140 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_11_8_SET(value) (((value) << 8) & 0x00000f00)
4157 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_LSB 12
4159 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_MSB 12
4161 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_WIDTH 1
4163 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_SET_MSK 0x00001000
4165 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_CLR_MSK 0xffffefff
4167 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_RESET 0x0
4169 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12)
4171 #define ALT_EMAC_DMA_AXI_BUS_MODE_AXI_AAL_SET(value) (((value) << 12) & 0x00001000)
4186 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_LSB 13
4188 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_MSB 13
4190 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_WIDTH 1
4192 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_SET_MSK 0x00002000
4194 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_CLR_MSK 0xffffdfff
4196 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_RESET 0x0
4198 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13)
4200 #define ALT_EMAC_DMA_AXI_BUS_MODE_ONEKBBE_SET(value) (((value) << 13) & 0x00002000)
4211 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_LSB 14
4213 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_MSB 15
4215 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_WIDTH 2
4217 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_SET_MSK 0x0000c000
4219 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_CLR_MSK 0xffff3fff
4221 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_RESET 0x0
4223 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_GET(value) (((value) & 0x0000c000) >> 14)
4225 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_15_14_SET(value) (((value) << 14) & 0x0000c000)
4246 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_LSB 16
4248 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_MSB 17
4250 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_WIDTH 2
4252 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_SET_MSK 0x00030000
4254 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_CLR_MSK 0xfffcffff
4256 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_RESET 0x1
4258 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GET(value) (((value) & 0x00030000) >> 16)
4260 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_SET(value) (((value) << 16) & 0x00030000)
4271 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_LSB 18
4273 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_MSB 18
4275 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_WIDTH 1
4277 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_SET_MSK 0x00040000
4279 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_CLR_MSK 0xfffbffff
4281 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_RESET 0x0
4283 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_GET(value) (((value) & 0x00040000) >> 18)
4285 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT4_SET(value) (((value) << 18) & 0x00040000)
4296 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_LSB 19
4298 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_MSB 19
4300 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_WIDTH 1
4302 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_SET_MSK 0x00080000
4304 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_CLR_MSK 0xfff7ffff
4306 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_RESET 0x0
4308 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_GET(value) (((value) & 0x00080000) >> 19)
4310 #define ALT_EMAC_DMA_AXI_BUS_MODE_RD_OSR_LMT_GT8_SET(value) (((value) << 19) & 0x00080000)
4321 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_LSB 20
4323 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_MSB 21
4325 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_WIDTH 2
4327 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_SET_MSK 0x00300000
4329 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_CLR_MSK 0xffcfffff
4331 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_RESET 0x1
4333 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GET(value) (((value) & 0x00300000) >> 20)
4335 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00300000)
4346 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_LSB 22
4348 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_MSB 22
4350 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_WIDTH 1
4352 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_SET_MSK 0x00400000
4354 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_CLR_MSK 0xffbfffff
4356 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_RESET 0x0
4358 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_GET(value) (((value) & 0x00400000) >> 22)
4360 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT4_SET(value) (((value) << 22) & 0x00400000)
4371 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_LSB 23
4373 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_MSB 23
4375 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_WIDTH 1
4377 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_SET_MSK 0x00800000
4379 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_CLR_MSK 0xff7fffff
4381 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_RESET 0x0
4383 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_GET(value) (((value) & 0x00800000) >> 23)
4385 #define ALT_EMAC_DMA_AXI_BUS_MODE_WR_OSR_LMT_GT8_SET(value) (((value) << 23) & 0x00800000)
4396 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_LSB 24
4398 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_MSB 29
4400 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_WIDTH 6
4402 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_SET_MSK 0x3f000000
4404 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_CLR_MSK 0xc0ffffff
4406 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_RESET 0x0
4408 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_GET(value) (((value) & 0x3f000000) >> 24)
4410 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESERVED_29_24_SET(value) (((value) << 24) & 0x3f000000)
4427 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_LSB 30
4429 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_MSB 30
4431 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_WIDTH 1
4433 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_SET_MSK 0x40000000
4435 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_CLR_MSK 0xbfffffff
4437 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_RESET 0x0
4439 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30)
4441 #define ALT_EMAC_DMA_AXI_BUS_MODE_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000)
4458 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_LSB 31
4460 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_MSB 31
4462 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_WIDTH 1
4464 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_SET_MSK 0x80000000
4466 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_CLR_MSK 0x7fffffff
4468 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_RESET 0x0
4470 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_GET(value) (((value) & 0x80000000) >> 31)
4472 #define ALT_EMAC_DMA_AXI_BUS_MODE_EN_LPI_SET(value) (((value) << 31) & 0x80000000)
4474 #ifndef __ASSEMBLY__
4485 struct ALT_EMAC_DMA_AXI_BUS_MODE_s
4487 const volatile uint32_t UNDEF : 1;
4488 volatile uint32_t BLEN4 : 1;
4489 volatile uint32_t BLEN8 : 1;
4490 volatile uint32_t BLEN16 : 1;
4491 const volatile uint32_t BLEN32 : 1;
4492 const volatile uint32_t BLEN64 : 1;
4493 const volatile uint32_t BLEN128 : 1;
4494 const volatile uint32_t BLEN256 : 1;
4495 const volatile uint32_t Reserved_11_8 : 4;
4496 const volatile uint32_t AXI_AAL : 1;
4497 volatile uint32_t ONEKBBE : 1;
4498 const volatile uint32_t Reserved_15_14 : 2;
4499 volatile uint32_t RD_OSR_LMT : 2;
4500 volatile uint32_t RD_OSR_LMT_GT4 : 1;
4501 volatile uint32_t RD_OSR_LMT_GT8 : 1;
4502 volatile uint32_t WR_OSR_LMT : 2;
4503 volatile uint32_t WR_OSR_LMT_GT4 : 1;
4504 volatile uint32_t WR_OSR_LMT_GT8 : 1;
4505 const volatile uint32_t Reserved_29_24 : 6;
4506 volatile uint32_t LPI_XIT_FRM : 1;
4507 volatile uint32_t EN_LPI : 1;
4511 typedef struct ALT_EMAC_DMA_AXI_BUS_MODE_s ALT_EMAC_DMA_AXI_BUS_MODE_t;
4515 #define ALT_EMAC_DMA_AXI_BUS_MODE_RESET 0x00110001
4517 #define ALT_EMAC_DMA_AXI_BUS_MODE_OFST 0x28
4519 #define ALT_EMAC_DMA_AXI_BUS_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MODE_OFST))
4554 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_LSB 0
4556 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_MSB 0
4558 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_WIDTH 1
4560 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_SET_MSK 0x00000001
4562 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_CLR_MSK 0xfffffffe
4564 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_RESET 0x0
4566 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0)
4568 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXWHSTS_SET(value) (((value) << 0) & 0x00000001)
4582 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_LSB 1
4584 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_MSB 1
4586 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_WIDTH 1
4588 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_SET_MSK 0x00000002
4590 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_CLR_MSK 0xfffffffd
4592 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_RESET 0x0
4594 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1)
4596 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002)
4607 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_LSB 2
4609 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_MSB 31
4611 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_WIDTH 30
4613 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_SET_MSK 0xfffffffc
4615 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_CLR_MSK 0x00000003
4617 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_RESET 0x0
4619 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_GET(value) (((value) & 0xfffffffc) >> 2)
4621 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESERVED_31_2_SET(value) (((value) << 2) & 0xfffffffc)
4623 #ifndef __ASSEMBLY__
4634 struct ALT_EMAC_DMA_AHB_OR_AXI_STATUS_s
4636 const volatile uint32_t AXWHSTS : 1;
4637 const volatile uint32_t AXIRDSTS : 1;
4638 const volatile uint32_t Reserved_31_2 : 30;
4642 typedef struct ALT_EMAC_DMA_AHB_OR_AXI_STATUS_s ALT_EMAC_DMA_AHB_OR_AXI_STATUS_t;
4646 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_RESET 0x00000000
4648 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_OFST 0x2c
4650 #define ALT_EMAC_DMA_AHB_OR_AXI_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STATUS_OFST))
4678 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_LSB 0
4680 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_MSB 31
4682 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_WIDTH 32
4684 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_SET_MSK 0xffffffff
4686 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_CLR_MSK 0x00000000
4688 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_RESET 0x0
4690 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4692 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
4694 #ifndef __ASSEMBLY__
4705 struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_s
4707 const volatile uint32_t CURTDESAPTR : 32;
4711 typedef struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_s ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_t;
4715 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_RESET 0x00000000
4717 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFST 0x48
4719 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFST))
4747 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_LSB 0
4749 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_MSB 31
4751 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_WIDTH 32
4753 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_SET_MSK 0xffffffff
4755 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_CLR_MSK 0x00000000
4757 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_RESET 0x0
4759 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4761 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
4763 #ifndef __ASSEMBLY__
4774 struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_s
4776 const volatile uint32_t CURRDESAPTR : 32;
4780 typedef struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_s ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_t;
4784 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_RESET 0x00000000
4786 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFST 0x4c
4788 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFST))
4816 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_LSB 0
4818 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_MSB 31
4820 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_WIDTH 32
4822 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_SET_MSK 0xffffffff
4824 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_CLR_MSK 0x00000000
4826 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_RESET 0x0
4828 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4830 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
4832 #ifndef __ASSEMBLY__
4843 struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_s
4845 const volatile uint32_t CURTBUFAPTR : 32;
4849 typedef struct ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_s ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_t;
4853 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_RESET 0x00000000
4855 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFST 0x50
4857 #define ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFST))
4885 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_LSB 0
4887 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_MSB 31
4889 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_WIDTH 32
4891 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_SET_MSK 0xffffffff
4893 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_CLR_MSK 0x00000000
4895 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_RESET 0x0
4897 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
4899 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
4901 #ifndef __ASSEMBLY__
4912 struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_s
4914 const volatile uint32_t CURRBUFAPTR : 32;
4918 typedef struct ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_s ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_t;
4922 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_RESET 0x00000000
4924 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFST 0x54
4926 #define ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFST))
4983 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB 0
4985 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB 0
4987 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH 1
4989 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK 0x00000001
4991 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK 0xfffffffe
4993 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET 0x1
4995 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0)
4997 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001)
5008 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB 1
5010 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB 1
5012 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH 1
5014 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK 0x00000002
5016 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK 0xfffffffd
5018 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET 0x1
5020 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1)
5022 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002)
5033 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB 2
5035 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB 2
5037 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH 1
5039 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK 0x00000004
5041 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK 0xfffffffb
5043 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET 0x1
5045 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2)
5047 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004)
5058 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_LSB 3
5060 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_MSB 3
5062 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_WIDTH 1
5064 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET_MSK 0x00000008
5066 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_CLR_MSK 0xfffffff7
5068 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_RESET 0x1
5070 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_GET(value) (((value) & 0x00000008) >> 3)
5072 #define ALT_EMAC_DMA_HW_FEATURE_EXTHASHEN_SET(value) (((value) << 3) & 0x00000008)
5083 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB 4
5085 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB 4
5087 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH 1
5089 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK 0x00000010
5091 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK 0xffffffef
5093 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET 0x1
5095 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4)
5097 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010)
5108 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB 5
5110 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB 5
5112 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH 1
5114 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK 0x00000020
5116 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK 0xffffffdf
5118 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET 0x1
5120 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5)
5122 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020)
5133 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB 6
5135 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB 6
5137 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH 1
5139 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK 0x00000040
5141 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK 0xffffffbf
5143 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET 0x0
5145 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6)
5147 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040)
5158 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_LSB 7
5160 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_MSB 7
5162 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_WIDTH 1
5164 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET_MSK 0x00000080
5166 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_CLR_MSK 0xffffff7f
5168 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_RESET 0x1
5170 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_GET(value) (((value) & 0x00000080) >> 7)
5172 #define ALT_EMAC_DMA_HW_FEATURE_L3L4FLTREN_SET(value) (((value) << 7) & 0x00000080)
5183 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB 8
5185 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB 8
5187 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH 1
5189 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK 0x00000100
5191 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK 0xfffffeff
5193 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET 0x1
5195 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8)
5197 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100)
5208 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB 9
5210 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB 9
5212 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH 1
5214 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK 0x00000200
5216 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK 0xfffffdff
5218 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET 0x0
5220 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9)
5222 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200)
5233 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB 10
5235 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB 10
5237 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH 1
5239 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK 0x00000400
5241 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK 0xfffffbff
5243 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET 0x0
5245 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10)
5247 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400)
5258 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB 11
5260 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB 11
5262 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH 1
5264 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK 0x00000800
5266 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK 0xfffff7ff
5268 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET 0x1
5270 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11)
5272 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800)
5283 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB 12
5285 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB 12
5287 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH 1
5289 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK 0x00001000
5291 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK 0xffffefff
5293 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET 0x0
5295 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12)
5297 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000)
5308 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB 13
5310 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB 13
5312 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH 1
5314 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK 0x00002000
5316 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK 0xffffdfff
5318 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET 0x1
5320 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13)
5322 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000)
5333 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB 14
5335 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB 14
5337 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH 1
5339 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK 0x00004000
5341 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK 0xffffbfff
5343 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET 0x1
5345 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14)
5347 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000)
5358 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB 15
5360 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB 15
5362 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH 1
5364 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK 0x00008000
5366 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK 0xffff7fff
5368 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET 0x0
5370 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15)
5372 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000)
5383 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_LSB 16
5385 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_MSB 16
5387 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_WIDTH 1
5389 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_SET_MSK 0x00010000
5391 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_CLR_MSK 0xfffeffff
5393 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_RESET 0x1
5395 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_GET(value) (((value) & 0x00010000) >> 16)
5397 #define ALT_EMAC_DMA_HW_FEATURE_TXCOESEL_SET(value) (((value) << 16) & 0x00010000)
5411 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB 17
5413 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB 17
5415 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH 1
5417 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK 0x00020000
5419 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK 0xfffdffff
5421 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET 0x0
5423 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17)
5425 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000)
5436 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB 18
5438 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB 18
5440 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH 1
5442 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK 0x00040000
5444 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK 0xfffbffff
5446 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET 0x1
5448 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18)
5450 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000)
5461 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB 19
5463 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB 19
5465 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH 1
5467 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK 0x00080000
5469 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK 0xfff7ffff
5471 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET 0x1
5473 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19)
5475 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000)
5486 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB 20
5488 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB 21
5490 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH 2
5492 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK 0x00300000
5494 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK 0xffcfffff
5496 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET 0x0
5498 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20)
5500 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000)
5511 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB 22
5513 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB 23
5515 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH 2
5517 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK 0x00c00000
5519 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK 0xff3fffff
5521 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET 0x0
5523 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22)
5525 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000)
5536 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB 24
5538 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB 24
5540 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH 1
5542 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK 0x01000000
5544 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK 0xfeffffff
5546 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET 0x1
5548 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24)
5550 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000)
5561 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_LSB 25
5563 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_MSB 25
5565 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_WIDTH 1
5567 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET_MSK 0x02000000
5569 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_CLR_MSK 0xfdffffff
5571 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_RESET 0x1
5573 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_GET(value) (((value) & 0x02000000) >> 25)
5575 #define ALT_EMAC_DMA_HW_FEATURE_INTTSEN_SET(value) (((value) << 25) & 0x02000000)
5586 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_LSB 26
5588 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_MSB 26
5590 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_WIDTH 1
5592 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET_MSK 0x04000000
5594 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_CLR_MSK 0xfbffffff
5596 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_RESET 0x1
5598 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_GET(value) (((value) & 0x04000000) >> 26)
5600 #define ALT_EMAC_DMA_HW_FEATURE_FLEXIPPSEN_SET(value) (((value) << 26) & 0x04000000)
5611 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_LSB 27
5613 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_MSB 27
5615 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_WIDTH 1
5617 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET_MSK 0x08000000
5619 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_CLR_MSK 0xf7ffffff
5621 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_RESET 0x1
5623 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_GET(value) (((value) & 0x08000000) >> 27)
5625 #define ALT_EMAC_DMA_HW_FEATURE_SAVLANINS_SET(value) (((value) << 27) & 0x08000000)
5657 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB 28
5659 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB 30
5661 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH 3
5663 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK 0x70000000
5665 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK 0x8fffffff
5667 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET 0x0
5669 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28)
5671 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000)
5682 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_LSB 31
5684 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_MSB 31
5686 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_WIDTH 1
5688 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_SET_MSK 0x80000000
5690 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_CLR_MSK 0x7fffffff
5692 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_RESET 0x0
5694 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_GET(value) (((value) & 0x80000000) >> 31)
5696 #define ALT_EMAC_DMA_HW_FEATURE_RESERVED_31_SET(value) (((value) << 31) & 0x80000000)
5698 #ifndef __ASSEMBLY__
5709 struct ALT_EMAC_DMA_HW_FEATURE_s
5711 const volatile uint32_t MIISEL : 1;
5712 const volatile uint32_t GMIISEL : 1;
5713 const volatile uint32_t HDSEL : 1;
5714 const volatile uint32_t EXTHASHEN : 1;
5715 const volatile uint32_t HASHSEL : 1;
5716 const volatile uint32_t ADDMACADRSEL : 1;
5717 const volatile uint32_t PCSSEL : 1;
5718 const volatile uint32_t L3L4FLTREN : 1;
5719 const volatile uint32_t SMASEL : 1;
5720 const volatile uint32_t RWKSEL : 1;
5721 const volatile uint32_t MGKSEL : 1;
5722 const volatile uint32_t MMCSEL : 1;
5723 const volatile uint32_t TSVER1SEL : 1;
5724 const volatile uint32_t TSVER2SEL : 1;
5725 const volatile uint32_t EEESEL : 1;
5726 const volatile uint32_t AVSEL : 1;
5727 const volatile uint32_t TXCOESEL : 1;
5728 const volatile uint32_t RXTYP1COE : 1;
5729 const volatile uint32_t RXTYP2COE : 1;
5730 const volatile uint32_t RXFIFOSIZE : 1;
5731 const volatile uint32_t RXCHCNT : 2;
5732 const volatile uint32_t TXCHCNT : 2;
5733 const volatile uint32_t ENHDESSEL : 1;
5734 const volatile uint32_t INTTSEN : 1;
5735 const volatile uint32_t FLEXIPPSEN : 1;
5736 const volatile uint32_t SAVLANINS : 1;
5737 const volatile uint32_t ACTPHYIF : 3;
5738 const volatile uint32_t Reserved_31 : 1;
5742 typedef struct ALT_EMAC_DMA_HW_FEATURE_s ALT_EMAC_DMA_HW_FEATURE_t;
5746 #define ALT_EMAC_DMA_HW_FEATURE_RESET 0x0f0d69bf
5748 #define ALT_EMAC_DMA_HW_FEATURE_OFST 0x58
5750 #define ALT_EMAC_DMA_HW_FEATURE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))
5752 #ifndef __ASSEMBLY__
5763 struct ALT_EMAC_DMA_s
5765 volatile ALT_EMAC_DMA_BUS_MODE_t Bus_Mode;
5766 volatile ALT_EMAC_DMA_TRANSMIT_POLL_DEMAND_t Transmit_Poll_Demand;
5767 volatile ALT_EMAC_DMA_RECEIVE_POLL_DEMAND_t Receive_Poll_Demand;
5768 volatile ALT_EMAC_DMA_RECEIVE_DESCRIPTOR_LIST_ADDRESS_t Receive_Descriptor_List_Address;
5769 volatile ALT_EMAC_DMA_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_t Transmit_Descriptor_List_Address;
5770 volatile ALT_EMAC_DMA_STATUS_t Status;
5771 volatile ALT_EMAC_DMA_OPERATION_MODE_t Operation_Mode;
5772 volatile ALT_EMAC_DMA_INTERRUPT_ENABLE_t Interrupt_Enable;
5773 volatile ALT_EMAC_DMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_t Missed_Frame_And_Buffer_Overflow_Counter;
5774 volatile ALT_EMAC_DMA_RECEIVE_INTERRUPT_WATCHDOG_TIMER_t Receive_Interrupt_Watchdog_Timer;
5775 volatile ALT_EMAC_DMA_AXI_BUS_MODE_t AXI_Bus_Mode;
5776 volatile ALT_EMAC_DMA_AHB_OR_AXI_STATUS_t AHB_or_AXI_Status;
5777 volatile uint32_t _pad_0x30_0x47[6];
5778 volatile ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_DESCRIPTOR_t Current_Host_Transmit_Descriptor;
5779 volatile ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_DESCRIPTOR_t Current_Host_Receive_Descriptor;
5780 volatile ALT_EMAC_DMA_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_t Current_Host_Transmit_Buffer_Address;
5781 volatile ALT_EMAC_DMA_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_t Current_Host_Receive_Buffer_Address;
5782 volatile ALT_EMAC_DMA_HW_FEATURE_t HW_Feature;
5783 volatile uint32_t _pad_0x5c_0x100[41];
5787 typedef struct ALT_EMAC_DMA_s ALT_EMAC_DMA_t;
5789 struct ALT_EMAC_DMA_raw_s
5791 volatile uint32_t Bus_Mode;
5792 volatile uint32_t Transmit_Poll_Demand;
5793 volatile uint32_t Receive_Poll_Demand;
5794 volatile uint32_t Receive_Descriptor_List_Address;
5795 volatile uint32_t Transmit_Descriptor_List_Address;
5796 volatile uint32_t Status;
5797 volatile uint32_t Operation_Mode;
5798 volatile uint32_t Interrupt_Enable;
5799 volatile uint32_t Missed_Frame_And_Buffer_Overflow_Counter;
5800 volatile uint32_t Receive_Interrupt_Watchdog_Timer;
5801 volatile uint32_t AXI_Bus_Mode;
5802 volatile uint32_t AHB_or_AXI_Status;
5803 volatile uint32_t _pad_0x30_0x47[6];
5804 volatile uint32_t Current_Host_Transmit_Descriptor;
5805 volatile uint32_t Current_Host_Receive_Descriptor;
5806 volatile uint32_t Current_Host_Transmit_Buffer_Address;
5807 volatile uint32_t Current_Host_Receive_Buffer_Address;
5808 volatile uint32_t HW_Feature;
5809 volatile uint32_t _pad_0x5c_0x100[41];
5813 typedef struct ALT_EMAC_DMA_raw_s ALT_EMAC_DMA_raw_t;