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alt_l3.h
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32 
33 /* Altera - ALT_L3 */
34 
35 #ifndef __ALTERA_ALT_L3_H__
36 #define __ALTERA_ALT_L3_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : L3 (NIC-301) GPV Registers - ALT_L3
45  * L3 (NIC-301) GPV Registers
46  *
47  * Registers to control L3 interconnect settings
48  *
49  */
50 /*
51  * Register : Remap - remap
52  *
53  * The L3 interconnect has separate address maps for the various L3 Masters.
54  * Generally, the addresses are the same for most masters. However, the sparse
55  * interconnect of the L3 switch causes some masters to have holes in their memory
56  * maps. The remap bits are not mutually exclusive. Each bit can be set
57  * independently and in combinations. Priority for the bits is determined by the
58  * bit offset: lower offset bits take precedence over higher offset bits.
59  *
60  * Register Layout
61  *
62  * Bits | Access | Reset | Description
63  * :-------|:-------|:------|:---------------------------------
64  * [0] | W | 0x0 | MPU at 0x0
65  * [1] | W | 0x0 | Non-MPU at 0x0
66  * [2] | ??? | 0x0 | *UNDEFINED*
67  * [3] | W | 0x0 | HPS2FPGA AXI Bridge Visibility
68  * [4] | W | 0x0 | LWHPS2FPGA AXI Bridge Visibility
69  * [31:5] | ??? | 0x0 | *UNDEFINED*
70  *
71  */
72 /*
73  * Field : MPU at 0x0 - mpuzero
74  *
75  * Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or
76  * On-chip RAM. This field only has an effect on the MPU L3 master.
77  *
78  * Field Enumeration Values:
79  *
80  * Enum | Value | Description
81  * :-------------------------------|:------|:-------------------------------------------------
82  * ALT_L3_REMAP_MPUZERO_E_BOOTROM | 0x0 | Maps the Boot ROM to address 0x0 for the MPU L3
83  * : | | master. Note that the Boot ROM is also always
84  * : | | mapped to address 0xfffd_0000 for the MPU L3
85  * : | | master independent of this field's value.
86  * ALT_L3_REMAP_MPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the MPU
87  * : | | L3 master. Note that the On-chip RAM is also
88  * : | | always mapped to address 0xffff_0000 for the MPU
89  * : | | L3 master independent of this field's value.
90  *
91  * Field Access Macros:
92  *
93  */
94 /*
95  * Enumerated value for register field ALT_L3_REMAP_MPUZERO
96  *
97  * Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM
98  * is also always mapped to address 0xfffd_0000 for the MPU L3 master independent
99  * of this field's value.
100  */
101 #define ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0
102 /*
103  * Enumerated value for register field ALT_L3_REMAP_MPUZERO
104  *
105  * Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip
106  * RAM is also always mapped to address 0xffff_0000 for the MPU L3 master
107  * independent of this field's value.
108  */
109 #define ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1
110 
111 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field. */
112 #define ALT_L3_REMAP_MPUZERO_LSB 0
113 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field. */
114 #define ALT_L3_REMAP_MPUZERO_MSB 0
115 /* The width in bits of the ALT_L3_REMAP_MPUZERO register field. */
116 #define ALT_L3_REMAP_MPUZERO_WIDTH 1
117 /* The mask used to set the ALT_L3_REMAP_MPUZERO register field value. */
118 #define ALT_L3_REMAP_MPUZERO_SET_MSK 0x00000001
119 /* The mask used to clear the ALT_L3_REMAP_MPUZERO register field value. */
120 #define ALT_L3_REMAP_MPUZERO_CLR_MSK 0xfffffffe
121 /* The reset value of the ALT_L3_REMAP_MPUZERO register field. */
122 #define ALT_L3_REMAP_MPUZERO_RESET 0x0
123 /* Extracts the ALT_L3_REMAP_MPUZERO field value from a register. */
124 #define ALT_L3_REMAP_MPUZERO_GET(value) (((value) & 0x00000001) >> 0)
125 /* Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register. */
126 #define ALT_L3_REMAP_MPUZERO_SET(value) (((value) << 0) & 0x00000001)
127 
128 /*
129  * Field : Non-MPU at 0x0 - nonmpuzero
130  *
131  * Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM
132  * or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The
133  * non-MPU L3 masters are the DMA controllers (standalone and those built-in to
134  * peripherals), the FPGA2HPS AXI Bridge, and the DAP.
135  *
136  * Field Enumeration Values:
137  *
138  * Enum | Value | Description
139  * :--------------------------------|:------|:-------------------------------------------------
140  * ALT_L3_REMAP_NONMPUZERO_E_SDRAM | 0x0 | Maps the SDRAM to address 0x0 for the non-MPU L3
141  * : | | masters.
142  * ALT_L3_REMAP_NONMPUZERO_E_OCRAM | 0x1 | Maps the On-chip RAM to address 0x0 for the non-
143  * : | | MPU L3 masters. Note that the On-chip RAM is
144  * : | | also always mapped to address 0xffff_0000 for
145  * : | | the non-MPU L3 masters independent of this
146  * : | | field's value.
147  *
148  * Field Access Macros:
149  *
150  */
151 /*
152  * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
153  *
154  * Maps the SDRAM to address 0x0 for the non-MPU L3 masters.
155  */
156 #define ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0
157 /*
158  * Enumerated value for register field ALT_L3_REMAP_NONMPUZERO
159  *
160  * Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the
161  * On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3
162  * masters independent of this field's value.
163  */
164 #define ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1
165 
166 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
167 #define ALT_L3_REMAP_NONMPUZERO_LSB 1
168 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field. */
169 #define ALT_L3_REMAP_NONMPUZERO_MSB 1
170 /* The width in bits of the ALT_L3_REMAP_NONMPUZERO register field. */
171 #define ALT_L3_REMAP_NONMPUZERO_WIDTH 1
172 /* The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value. */
173 #define ALT_L3_REMAP_NONMPUZERO_SET_MSK 0x00000002
174 /* The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value. */
175 #define ALT_L3_REMAP_NONMPUZERO_CLR_MSK 0xfffffffd
176 /* The reset value of the ALT_L3_REMAP_NONMPUZERO register field. */
177 #define ALT_L3_REMAP_NONMPUZERO_RESET 0x0
178 /* Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register. */
179 #define ALT_L3_REMAP_NONMPUZERO_GET(value) (((value) & 0x00000002) >> 1)
180 /* Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register. */
181 #define ALT_L3_REMAP_NONMPUZERO_SET(value) (((value) << 1) & 0x00000002)
182 
183 /*
184  * Field : HPS2FPGA AXI Bridge Visibility - hps2fpga
185  *
186  * Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not.
187  *
188  * Field Enumeration Values:
189  *
190  * Enum | Value | Description
191  * :-----------------------------|:------|:------------------------------------------------
192  * ALT_L3_REMAP_H2F_E_INVISIBLE | 0x0 | The HPS2FPGA AXI Bridge is not visible to L3
193  * : | | masters. Accesses to the associated address
194  * : | | range return an AXI decode error to the master.
195  * ALT_L3_REMAP_H2F_E_VISIBLE | 0x1 | The HPS2FPGA AXI Bridge is visible to L3
196  * : | | masters.
197  *
198  * Field Access Macros:
199  *
200  */
201 /*
202  * Enumerated value for register field ALT_L3_REMAP_H2F
203  *
204  * The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated
205  * address range return an AXI decode error to the master.
206  */
207 #define ALT_L3_REMAP_H2F_E_INVISIBLE 0x0
208 /*
209  * Enumerated value for register field ALT_L3_REMAP_H2F
210  *
211  * The HPS2FPGA AXI Bridge is visible to L3 masters.
212  */
213 #define ALT_L3_REMAP_H2F_E_VISIBLE 0x1
214 
215 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field. */
216 #define ALT_L3_REMAP_H2F_LSB 3
217 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field. */
218 #define ALT_L3_REMAP_H2F_MSB 3
219 /* The width in bits of the ALT_L3_REMAP_H2F register field. */
220 #define ALT_L3_REMAP_H2F_WIDTH 1
221 /* The mask used to set the ALT_L3_REMAP_H2F register field value. */
222 #define ALT_L3_REMAP_H2F_SET_MSK 0x00000008
223 /* The mask used to clear the ALT_L3_REMAP_H2F register field value. */
224 #define ALT_L3_REMAP_H2F_CLR_MSK 0xfffffff7
225 /* The reset value of the ALT_L3_REMAP_H2F register field. */
226 #define ALT_L3_REMAP_H2F_RESET 0x0
227 /* Extracts the ALT_L3_REMAP_H2F field value from a register. */
228 #define ALT_L3_REMAP_H2F_GET(value) (((value) & 0x00000008) >> 3)
229 /* Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register. */
230 #define ALT_L3_REMAP_H2F_SET(value) (((value) << 3) & 0x00000008)
231 
232 /*
233  * Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga
234  *
235  * Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or
236  * not.
237  *
238  * Field Enumeration Values:
239  *
240  * Enum | Value | Description
241  * :-------------------------------|:------|:------------------------------------------------
242  * ALT_L3_REMAP_LWH2F_E_INVISIBLE | 0x0 | The LWHPS2FPGA AXI Bridge is not visible to L3
243  * : | | masters. Accesses to the associated address
244  * : | | range return an AXI decode error to the master.
245  * ALT_L3_REMAP_LWH2F_E_VISIBLE | 0x1 | The LWHPS2FPGA AXI Bridge is visible to L3
246  * : | | masters.
247  *
248  * Field Access Macros:
249  *
250  */
251 /*
252  * Enumerated value for register field ALT_L3_REMAP_LWH2F
253  *
254  * The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the
255  * associated address range return an AXI decode error to the master.
256  */
257 #define ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0
258 /*
259  * Enumerated value for register field ALT_L3_REMAP_LWH2F
260  *
261  * The LWHPS2FPGA AXI Bridge is visible to L3 masters.
262  */
263 #define ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1
264 
265 /* The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field. */
266 #define ALT_L3_REMAP_LWH2F_LSB 4
267 /* The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field. */
268 #define ALT_L3_REMAP_LWH2F_MSB 4
269 /* The width in bits of the ALT_L3_REMAP_LWH2F register field. */
270 #define ALT_L3_REMAP_LWH2F_WIDTH 1
271 /* The mask used to set the ALT_L3_REMAP_LWH2F register field value. */
272 #define ALT_L3_REMAP_LWH2F_SET_MSK 0x00000010
273 /* The mask used to clear the ALT_L3_REMAP_LWH2F register field value. */
274 #define ALT_L3_REMAP_LWH2F_CLR_MSK 0xffffffef
275 /* The reset value of the ALT_L3_REMAP_LWH2F register field. */
276 #define ALT_L3_REMAP_LWH2F_RESET 0x0
277 /* Extracts the ALT_L3_REMAP_LWH2F field value from a register. */
278 #define ALT_L3_REMAP_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
279 /* Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register. */
280 #define ALT_L3_REMAP_LWH2F_SET(value) (((value) << 4) & 0x00000010)
281 
282 #ifndef __ASSEMBLY__
283 /*
284  * WARNING: The C register and register group struct declarations are provided for
285  * convenience and illustrative purposes. They should, however, be used with
286  * caution as the C language standard provides no guarantees about the alignment or
287  * atomicity of device memory accesses. The recommended practice for writing
288  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
289  * alt_write_word() functions.
290  *
291  * The struct declaration for register ALT_L3_REMAP.
292  */
293 struct ALT_L3_REMAP_s
294 {
295  uint32_t mpuzero : 1; /* MPU at 0x0 */
296  uint32_t nonmpuzero : 1; /* Non-MPU at 0x0 */
297  uint32_t : 1; /* *UNDEFINED* */
298  uint32_t hps2fpga : 1; /* HPS2FPGA AXI Bridge Visibility */
299  uint32_t lwhps2fpga : 1; /* LWHPS2FPGA AXI Bridge Visibility */
300  uint32_t : 27; /* *UNDEFINED* */
301 };
302 
303 /* The typedef declaration for register ALT_L3_REMAP. */
304 typedef volatile struct ALT_L3_REMAP_s ALT_L3_REMAP_t;
305 #endif /* __ASSEMBLY__ */
306 
307 /* The byte offset of the ALT_L3_REMAP register from the beginning of the component. */
308 #define ALT_L3_REMAP_OFST 0x0
309 
310 /*
311  * Register Group : Security Register Group - ALT_L3_SECGRP
312  * Security Register Group
313  *
314  * Registers that control slave security.
315  *
316  */
317 /*
318  * Register : L4 Main Peripherals Security - l4main
319  *
320  * Controls security settings for L4 Main peripherals.
321  *
322  * Register Layout
323  *
324  * Bits | Access | Reset | Description
325  * :-------|:-------|:------|:------------------------
326  * [0] | W | 0x0 | SPI Slave 0 Security
327  * [1] | W | 0x0 | SPI Slave 1 Security
328  * [2] | W | 0x0 | DMA Secure Security
329  * [3] | W | 0x0 | DMA Non-secure Security
330  * [31:4] | ??? | 0x0 | *UNDEFINED*
331  *
332  */
333 /*
334  * Field : SPI Slave 0 Security - spis0
335  *
336  * Controls whether secure or non-secure masters can access the SPI Slave 0 slave.
337  *
338  * Field Enumeration Values:
339  *
340  * Enum | Value | Description
341  * :------------------------------------|:------|:----------------------------------------------
342  * ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE | 0x0 | The slave can only be accessed by a secure
343  * : | | master.
344  * ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
345  * : | | non-secure masters.
346  *
347  * Field Access Macros:
348  *
349  */
350 /*
351  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
352  *
353  * The slave can only be accessed by a secure master.
354  */
355 #define ALT_L3_SEC_L4MAIN_SPIS0_E_SECURE 0x0
356 /*
357  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS0
358  *
359  * The slave can only be accessed by a secure or non-secure masters.
360  */
361 #define ALT_L3_SEC_L4MAIN_SPIS0_E_NONSECURE 0x1
362 
363 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
364 #define ALT_L3_SEC_L4MAIN_SPIS0_LSB 0
365 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
366 #define ALT_L3_SEC_L4MAIN_SPIS0_MSB 0
367 /* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
368 #define ALT_L3_SEC_L4MAIN_SPIS0_WIDTH 1
369 /* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
370 #define ALT_L3_SEC_L4MAIN_SPIS0_SET_MSK 0x00000001
371 /* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS0 register field value. */
372 #define ALT_L3_SEC_L4MAIN_SPIS0_CLR_MSK 0xfffffffe
373 /* The reset value of the ALT_L3_SEC_L4MAIN_SPIS0 register field. */
374 #define ALT_L3_SEC_L4MAIN_SPIS0_RESET 0x0
375 /* Extracts the ALT_L3_SEC_L4MAIN_SPIS0 field value from a register. */
376 #define ALT_L3_SEC_L4MAIN_SPIS0_GET(value) (((value) & 0x00000001) >> 0)
377 /* Produces a ALT_L3_SEC_L4MAIN_SPIS0 register field value suitable for setting the register. */
378 #define ALT_L3_SEC_L4MAIN_SPIS0_SET(value) (((value) << 0) & 0x00000001)
379 
380 /*
381  * Field : SPI Slave 1 Security - spis1
382  *
383  * Controls whether secure or non-secure masters can access the SPI Slave 1 slave.
384  *
385  * Field Enumeration Values:
386  *
387  * Enum | Value | Description
388  * :------------------------------------|:------|:----------------------------------------------
389  * ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE | 0x0 | The slave can only be accessed by a secure
390  * : | | master.
391  * ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
392  * : | | non-secure masters.
393  *
394  * Field Access Macros:
395  *
396  */
397 /*
398  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
399  *
400  * The slave can only be accessed by a secure master.
401  */
402 #define ALT_L3_SEC_L4MAIN_SPIS1_E_SECURE 0x0
403 /*
404  * Enumerated value for register field ALT_L3_SEC_L4MAIN_SPIS1
405  *
406  * The slave can only be accessed by a secure or non-secure masters.
407  */
408 #define ALT_L3_SEC_L4MAIN_SPIS1_E_NONSECURE 0x1
409 
410 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
411 #define ALT_L3_SEC_L4MAIN_SPIS1_LSB 1
412 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
413 #define ALT_L3_SEC_L4MAIN_SPIS1_MSB 1
414 /* The width in bits of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
415 #define ALT_L3_SEC_L4MAIN_SPIS1_WIDTH 1
416 /* The mask used to set the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
417 #define ALT_L3_SEC_L4MAIN_SPIS1_SET_MSK 0x00000002
418 /* The mask used to clear the ALT_L3_SEC_L4MAIN_SPIS1 register field value. */
419 #define ALT_L3_SEC_L4MAIN_SPIS1_CLR_MSK 0xfffffffd
420 /* The reset value of the ALT_L3_SEC_L4MAIN_SPIS1 register field. */
421 #define ALT_L3_SEC_L4MAIN_SPIS1_RESET 0x0
422 /* Extracts the ALT_L3_SEC_L4MAIN_SPIS1 field value from a register. */
423 #define ALT_L3_SEC_L4MAIN_SPIS1_GET(value) (((value) & 0x00000002) >> 1)
424 /* Produces a ALT_L3_SEC_L4MAIN_SPIS1 register field value suitable for setting the register. */
425 #define ALT_L3_SEC_L4MAIN_SPIS1_SET(value) (((value) << 1) & 0x00000002)
426 
427 /*
428  * Field : DMA Secure Security - dmasecure
429  *
430  * Controls whether secure or non-secure masters can access the DMA Secure slave.
431  *
432  * Field Enumeration Values:
433  *
434  * Enum | Value | Description
435  * :----------------------------------------|:------|:----------------------------------------------
436  * ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure
437  * : | | master.
438  * ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
439  * : | | non-secure masters.
440  *
441  * Field Access Macros:
442  *
443  */
444 /*
445  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
446  *
447  * The slave can only be accessed by a secure master.
448  */
449 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_SECURE 0x0
450 /*
451  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMASECURE
452  *
453  * The slave can only be accessed by a secure or non-secure masters.
454  */
455 #define ALT_L3_SEC_L4MAIN_DMASECURE_E_NONSECURE 0x1
456 
457 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
458 #define ALT_L3_SEC_L4MAIN_DMASECURE_LSB 2
459 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
460 #define ALT_L3_SEC_L4MAIN_DMASECURE_MSB 2
461 /* The width in bits of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
462 #define ALT_L3_SEC_L4MAIN_DMASECURE_WIDTH 1
463 /* The mask used to set the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
464 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET_MSK 0x00000004
465 /* The mask used to clear the ALT_L3_SEC_L4MAIN_DMASECURE register field value. */
466 #define ALT_L3_SEC_L4MAIN_DMASECURE_CLR_MSK 0xfffffffb
467 /* The reset value of the ALT_L3_SEC_L4MAIN_DMASECURE register field. */
468 #define ALT_L3_SEC_L4MAIN_DMASECURE_RESET 0x0
469 /* Extracts the ALT_L3_SEC_L4MAIN_DMASECURE field value from a register. */
470 #define ALT_L3_SEC_L4MAIN_DMASECURE_GET(value) (((value) & 0x00000004) >> 2)
471 /* Produces a ALT_L3_SEC_L4MAIN_DMASECURE register field value suitable for setting the register. */
472 #define ALT_L3_SEC_L4MAIN_DMASECURE_SET(value) (((value) << 2) & 0x00000004)
473 
474 /*
475  * Field : DMA Non-secure Security - dmanonsecure
476  *
477  * Controls whether secure or non-secure masters can access the DMA Non-secure
478  * slave.
479  *
480  * Field Enumeration Values:
481  *
482  * Enum | Value | Description
483  * :-------------------------------------------|:------|:----------------------------------------------
484  * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE | 0x0 | The slave can only be accessed by a secure
485  * : | | master.
486  * ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
487  * : | | non-secure masters.
488  *
489  * Field Access Macros:
490  *
491  */
492 /*
493  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
494  *
495  * The slave can only be accessed by a secure master.
496  */
497 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_SECURE 0x0
498 /*
499  * Enumerated value for register field ALT_L3_SEC_L4MAIN_DMANONSECURE
500  *
501  * The slave can only be accessed by a secure or non-secure masters.
502  */
503 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_E_NONSECURE 0x1
504 
505 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
506 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_LSB 3
507 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
508 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_MSB 3
509 /* The width in bits of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
510 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_WIDTH 1
511 /* The mask used to set the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
512 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET_MSK 0x00000008
513 /* The mask used to clear the ALT_L3_SEC_L4MAIN_DMANONSECURE register field value. */
514 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_CLR_MSK 0xfffffff7
515 /* The reset value of the ALT_L3_SEC_L4MAIN_DMANONSECURE register field. */
516 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_RESET 0x0
517 /* Extracts the ALT_L3_SEC_L4MAIN_DMANONSECURE field value from a register. */
518 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_GET(value) (((value) & 0x00000008) >> 3)
519 /* Produces a ALT_L3_SEC_L4MAIN_DMANONSECURE register field value suitable for setting the register. */
520 #define ALT_L3_SEC_L4MAIN_DMANONSECURE_SET(value) (((value) << 3) & 0x00000008)
521 
522 #ifndef __ASSEMBLY__
523 /*
524  * WARNING: The C register and register group struct declarations are provided for
525  * convenience and illustrative purposes. They should, however, be used with
526  * caution as the C language standard provides no guarantees about the alignment or
527  * atomicity of device memory accesses. The recommended practice for writing
528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
529  * alt_write_word() functions.
530  *
531  * The struct declaration for register ALT_L3_SEC_L4MAIN.
532  */
533 struct ALT_L3_SEC_L4MAIN_s
534 {
535  uint32_t spis0 : 1; /* SPI Slave 0 Security */
536  uint32_t spis1 : 1; /* SPI Slave 1 Security */
537  uint32_t dmasecure : 1; /* DMA Secure Security */
538  uint32_t dmanonsecure : 1; /* DMA Non-secure Security */
539  uint32_t : 28; /* *UNDEFINED* */
540 };
541 
542 /* The typedef declaration for register ALT_L3_SEC_L4MAIN. */
543 typedef volatile struct ALT_L3_SEC_L4MAIN_s ALT_L3_SEC_L4MAIN_t;
544 #endif /* __ASSEMBLY__ */
545 
546 /* The byte offset of the ALT_L3_SEC_L4MAIN register from the beginning of the component. */
547 #define ALT_L3_SEC_L4MAIN_OFST 0x0
548 
549 /*
550  * Register : L4 SP Peripherals Security - l4sp
551  *
552  * Controls security settings for L4 SP peripherals.
553  *
554  * Register Layout
555  *
556  * Bits | Access | Reset | Description
557  * :--------|:-------|:------|:-------------------------
558  * [0] | W | 0x0 | SDRAM Registers Security
559  * [1] | W | 0x0 | SP Timer 0 Security
560  * [2] | W | 0x0 | I2C0 Security
561  * [3] | W | 0x0 | I2C1 Security
562  * [4] | W | 0x0 | I2C2 (EMAC 0) Security
563  * [5] | W | 0x0 | I2C3 (EMAC 1) Security
564  * [6] | W | 0x0 | UART 0 Security
565  * [7] | W | 0x0 | UART 1 Security
566  * [8] | W | 0x0 | CAN 0 Security
567  * [9] | W | 0x0 | CAN 1 Security
568  * [10] | W | 0x0 | SP Timer 1 Security
569  * [31:11] | ??? | 0x0 | *UNDEFINED*
570  *
571  */
572 /*
573  * Field : SDRAM Registers Security - sdrregs
574  *
575  * Controls whether secure or non-secure masters can access the SDRAM Registers
576  * slave.
577  *
578  * Field Enumeration Values:
579  *
580  * Enum | Value | Description
581  * :------------------------------------|:------|:----------------------------------------------
582  * ALT_L3_SEC_L4SP_SDRREGS_E_SECURE | 0x0 | The slave can only be accessed by a secure
583  * : | | master.
584  * ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
585  * : | | non-secure masters.
586  *
587  * Field Access Macros:
588  *
589  */
590 /*
591  * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
592  *
593  * The slave can only be accessed by a secure master.
594  */
595 #define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0
596 /*
597  * Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS
598  *
599  * The slave can only be accessed by a secure or non-secure masters.
600  */
601 #define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1
602 
603 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
604 #define ALT_L3_SEC_L4SP_SDRREGS_LSB 0
605 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field. */
606 #define ALT_L3_SEC_L4SP_SDRREGS_MSB 0
607 /* The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field. */
608 #define ALT_L3_SEC_L4SP_SDRREGS_WIDTH 1
609 /* The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value. */
610 #define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK 0x00000001
611 /* The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value. */
612 #define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK 0xfffffffe
613 /* The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field. */
614 #define ALT_L3_SEC_L4SP_SDRREGS_RESET 0x0
615 /* Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register. */
616 #define ALT_L3_SEC_L4SP_SDRREGS_GET(value) (((value) & 0x00000001) >> 0)
617 /* Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register. */
618 #define ALT_L3_SEC_L4SP_SDRREGS_SET(value) (((value) << 0) & 0x00000001)
619 
620 /*
621  * Field : SP Timer 0 Security - sptimer0
622  *
623  * Controls whether secure or non-secure masters can access the SP Timer 0 slave.
624  *
625  * Field Enumeration Values:
626  *
627  * Enum | Value | Description
628  * :-----------------------------------|:------|:----------------------------------------------
629  * ALT_L3_SEC_L4SP_SPTMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure
630  * : | | master.
631  * ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
632  * : | | non-secure masters.
633  *
634  * Field Access Macros:
635  *
636  */
637 /*
638  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
639  *
640  * The slave can only be accessed by a secure master.
641  */
642 #define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0
643 /*
644  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0
645  *
646  * The slave can only be accessed by a secure or non-secure masters.
647  */
648 #define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1
649 
650 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
651 #define ALT_L3_SEC_L4SP_SPTMR0_LSB 1
652 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
653 #define ALT_L3_SEC_L4SP_SPTMR0_MSB 1
654 /* The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
655 #define ALT_L3_SEC_L4SP_SPTMR0_WIDTH 1
656 /* The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
657 #define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK 0x00000002
658 /* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value. */
659 #define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK 0xfffffffd
660 /* The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field. */
661 #define ALT_L3_SEC_L4SP_SPTMR0_RESET 0x0
662 /* Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register. */
663 #define ALT_L3_SEC_L4SP_SPTMR0_GET(value) (((value) & 0x00000002) >> 1)
664 /* Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register. */
665 #define ALT_L3_SEC_L4SP_SPTMR0_SET(value) (((value) << 1) & 0x00000002)
666 
667 /*
668  * Field : I2C0 Security - i2c0
669  *
670  * Controls whether secure or non-secure masters can access the I2C0 slave.
671  *
672  * Field Enumeration Values:
673  *
674  * Enum | Value | Description
675  * :---------------------------------|:------|:----------------------------------------------
676  * ALT_L3_SEC_L4SP_I2C0_E_SECURE | 0x0 | The slave can only be accessed by a secure
677  * : | | master.
678  * ALT_L3_SEC_L4SP_I2C0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
679  * : | | non-secure masters.
680  *
681  * Field Access Macros:
682  *
683  */
684 /*
685  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
686  *
687  * The slave can only be accessed by a secure master.
688  */
689 #define ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0
690 /*
691  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C0
692  *
693  * The slave can only be accessed by a secure or non-secure masters.
694  */
695 #define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1
696 
697 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
698 #define ALT_L3_SEC_L4SP_I2C0_LSB 2
699 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field. */
700 #define ALT_L3_SEC_L4SP_I2C0_MSB 2
701 /* The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field. */
702 #define ALT_L3_SEC_L4SP_I2C0_WIDTH 1
703 /* The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value. */
704 #define ALT_L3_SEC_L4SP_I2C0_SET_MSK 0x00000004
705 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value. */
706 #define ALT_L3_SEC_L4SP_I2C0_CLR_MSK 0xfffffffb
707 /* The reset value of the ALT_L3_SEC_L4SP_I2C0 register field. */
708 #define ALT_L3_SEC_L4SP_I2C0_RESET 0x0
709 /* Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register. */
710 #define ALT_L3_SEC_L4SP_I2C0_GET(value) (((value) & 0x00000004) >> 2)
711 /* Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register. */
712 #define ALT_L3_SEC_L4SP_I2C0_SET(value) (((value) << 2) & 0x00000004)
713 
714 /*
715  * Field : I2C1 Security - i2c1
716  *
717  * Controls whether secure or non-secure masters can access the I2C1 slave.
718  *
719  * Field Enumeration Values:
720  *
721  * Enum | Value | Description
722  * :---------------------------------|:------|:----------------------------------------------
723  * ALT_L3_SEC_L4SP_I2C1_E_SECURE | 0x0 | The slave can only be accessed by a secure
724  * : | | master.
725  * ALT_L3_SEC_L4SP_I2C1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
726  * : | | non-secure masters.
727  *
728  * Field Access Macros:
729  *
730  */
731 /*
732  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
733  *
734  * The slave can only be accessed by a secure master.
735  */
736 #define ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0
737 /*
738  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C1
739  *
740  * The slave can only be accessed by a secure or non-secure masters.
741  */
742 #define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1
743 
744 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
745 #define ALT_L3_SEC_L4SP_I2C1_LSB 3
746 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field. */
747 #define ALT_L3_SEC_L4SP_I2C1_MSB 3
748 /* The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field. */
749 #define ALT_L3_SEC_L4SP_I2C1_WIDTH 1
750 /* The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value. */
751 #define ALT_L3_SEC_L4SP_I2C1_SET_MSK 0x00000008
752 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value. */
753 #define ALT_L3_SEC_L4SP_I2C1_CLR_MSK 0xfffffff7
754 /* The reset value of the ALT_L3_SEC_L4SP_I2C1 register field. */
755 #define ALT_L3_SEC_L4SP_I2C1_RESET 0x0
756 /* Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register. */
757 #define ALT_L3_SEC_L4SP_I2C1_GET(value) (((value) & 0x00000008) >> 3)
758 /* Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register. */
759 #define ALT_L3_SEC_L4SP_I2C1_SET(value) (((value) << 3) & 0x00000008)
760 
761 /*
762  * Field : I2C2 (EMAC 0) Security - i2c2
763  *
764  * Controls whether secure or non-secure masters can access the I2C2 (EMAC 0)
765  * slave.
766  *
767  * Field Enumeration Values:
768  *
769  * Enum | Value | Description
770  * :---------------------------------|:------|:----------------------------------------------
771  * ALT_L3_SEC_L4SP_I2C2_E_SECURE | 0x0 | The slave can only be accessed by a secure
772  * : | | master.
773  * ALT_L3_SEC_L4SP_I2C2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
774  * : | | non-secure masters.
775  *
776  * Field Access Macros:
777  *
778  */
779 /*
780  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
781  *
782  * The slave can only be accessed by a secure master.
783  */
784 #define ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0
785 /*
786  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C2
787  *
788  * The slave can only be accessed by a secure or non-secure masters.
789  */
790 #define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1
791 
792 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
793 #define ALT_L3_SEC_L4SP_I2C2_LSB 4
794 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field. */
795 #define ALT_L3_SEC_L4SP_I2C2_MSB 4
796 /* The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field. */
797 #define ALT_L3_SEC_L4SP_I2C2_WIDTH 1
798 /* The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value. */
799 #define ALT_L3_SEC_L4SP_I2C2_SET_MSK 0x00000010
800 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value. */
801 #define ALT_L3_SEC_L4SP_I2C2_CLR_MSK 0xffffffef
802 /* The reset value of the ALT_L3_SEC_L4SP_I2C2 register field. */
803 #define ALT_L3_SEC_L4SP_I2C2_RESET 0x0
804 /* Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register. */
805 #define ALT_L3_SEC_L4SP_I2C2_GET(value) (((value) & 0x00000010) >> 4)
806 /* Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register. */
807 #define ALT_L3_SEC_L4SP_I2C2_SET(value) (((value) << 4) & 0x00000010)
808 
809 /*
810  * Field : I2C3 (EMAC 1) Security - i2c3
811  *
812  * Controls whether secure or non-secure masters can access the I2C3 (EMAC 1)
813  * slave.
814  *
815  * Field Enumeration Values:
816  *
817  * Enum | Value | Description
818  * :---------------------------------|:------|:----------------------------------------------
819  * ALT_L3_SEC_L4SP_I2C3_E_SECURE | 0x0 | The slave can only be accessed by a secure
820  * : | | master.
821  * ALT_L3_SEC_L4SP_I2C3_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
822  * : | | non-secure masters.
823  *
824  * Field Access Macros:
825  *
826  */
827 /*
828  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
829  *
830  * The slave can only be accessed by a secure master.
831  */
832 #define ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0
833 /*
834  * Enumerated value for register field ALT_L3_SEC_L4SP_I2C3
835  *
836  * The slave can only be accessed by a secure or non-secure masters.
837  */
838 #define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1
839 
840 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
841 #define ALT_L3_SEC_L4SP_I2C3_LSB 5
842 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field. */
843 #define ALT_L3_SEC_L4SP_I2C3_MSB 5
844 /* The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field. */
845 #define ALT_L3_SEC_L4SP_I2C3_WIDTH 1
846 /* The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value. */
847 #define ALT_L3_SEC_L4SP_I2C3_SET_MSK 0x00000020
848 /* The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value. */
849 #define ALT_L3_SEC_L4SP_I2C3_CLR_MSK 0xffffffdf
850 /* The reset value of the ALT_L3_SEC_L4SP_I2C3 register field. */
851 #define ALT_L3_SEC_L4SP_I2C3_RESET 0x0
852 /* Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register. */
853 #define ALT_L3_SEC_L4SP_I2C3_GET(value) (((value) & 0x00000020) >> 5)
854 /* Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register. */
855 #define ALT_L3_SEC_L4SP_I2C3_SET(value) (((value) << 5) & 0x00000020)
856 
857 /*
858  * Field : UART 0 Security - uart0
859  *
860  * Controls whether secure or non-secure masters can access the UART 0 slave.
861  *
862  * Field Enumeration Values:
863  *
864  * Enum | Value | Description
865  * :----------------------------------|:------|:----------------------------------------------
866  * ALT_L3_SEC_L4SP_UART0_E_SECURE | 0x0 | The slave can only be accessed by a secure
867  * : | | master.
868  * ALT_L3_SEC_L4SP_UART0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
869  * : | | non-secure masters.
870  *
871  * Field Access Macros:
872  *
873  */
874 /*
875  * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
876  *
877  * The slave can only be accessed by a secure master.
878  */
879 #define ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0
880 /*
881  * Enumerated value for register field ALT_L3_SEC_L4SP_UART0
882  *
883  * The slave can only be accessed by a secure or non-secure masters.
884  */
885 #define ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1
886 
887 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
888 #define ALT_L3_SEC_L4SP_UART0_LSB 6
889 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field. */
890 #define ALT_L3_SEC_L4SP_UART0_MSB 6
891 /* The width in bits of the ALT_L3_SEC_L4SP_UART0 register field. */
892 #define ALT_L3_SEC_L4SP_UART0_WIDTH 1
893 /* The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value. */
894 #define ALT_L3_SEC_L4SP_UART0_SET_MSK 0x00000040
895 /* The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value. */
896 #define ALT_L3_SEC_L4SP_UART0_CLR_MSK 0xffffffbf
897 /* The reset value of the ALT_L3_SEC_L4SP_UART0 register field. */
898 #define ALT_L3_SEC_L4SP_UART0_RESET 0x0
899 /* Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register. */
900 #define ALT_L3_SEC_L4SP_UART0_GET(value) (((value) & 0x00000040) >> 6)
901 /* Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register. */
902 #define ALT_L3_SEC_L4SP_UART0_SET(value) (((value) << 6) & 0x00000040)
903 
904 /*
905  * Field : UART 1 Security - uart1
906  *
907  * Controls whether secure or non-secure masters can access the UART 1 slave.
908  *
909  * Field Enumeration Values:
910  *
911  * Enum | Value | Description
912  * :----------------------------------|:------|:----------------------------------------------
913  * ALT_L3_SEC_L4SP_UART1_E_SECURE | 0x0 | The slave can only be accessed by a secure
914  * : | | master.
915  * ALT_L3_SEC_L4SP_UART1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
916  * : | | non-secure masters.
917  *
918  * Field Access Macros:
919  *
920  */
921 /*
922  * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
923  *
924  * The slave can only be accessed by a secure master.
925  */
926 #define ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0
927 /*
928  * Enumerated value for register field ALT_L3_SEC_L4SP_UART1
929  *
930  * The slave can only be accessed by a secure or non-secure masters.
931  */
932 #define ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1
933 
934 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
935 #define ALT_L3_SEC_L4SP_UART1_LSB 7
936 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field. */
937 #define ALT_L3_SEC_L4SP_UART1_MSB 7
938 /* The width in bits of the ALT_L3_SEC_L4SP_UART1 register field. */
939 #define ALT_L3_SEC_L4SP_UART1_WIDTH 1
940 /* The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value. */
941 #define ALT_L3_SEC_L4SP_UART1_SET_MSK 0x00000080
942 /* The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value. */
943 #define ALT_L3_SEC_L4SP_UART1_CLR_MSK 0xffffff7f
944 /* The reset value of the ALT_L3_SEC_L4SP_UART1 register field. */
945 #define ALT_L3_SEC_L4SP_UART1_RESET 0x0
946 /* Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register. */
947 #define ALT_L3_SEC_L4SP_UART1_GET(value) (((value) & 0x00000080) >> 7)
948 /* Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register. */
949 #define ALT_L3_SEC_L4SP_UART1_SET(value) (((value) << 7) & 0x00000080)
950 
951 /*
952  * Field : CAN 0 Security - can0
953  *
954  * Controls whether secure or non-secure masters can access the CAN 0 slave.
955  *
956  * Field Enumeration Values:
957  *
958  * Enum | Value | Description
959  * :---------------------------------|:------|:----------------------------------------------
960  * ALT_L3_SEC_L4SP_CAN0_E_SECURE | 0x0 | The slave can only be accessed by a secure
961  * : | | master.
962  * ALT_L3_SEC_L4SP_CAN0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
963  * : | | non-secure masters.
964  *
965  * Field Access Macros:
966  *
967  */
968 /*
969  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
970  *
971  * The slave can only be accessed by a secure master.
972  */
973 #define ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0
974 /*
975  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN0
976  *
977  * The slave can only be accessed by a secure or non-secure masters.
978  */
979 #define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1
980 
981 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
982 #define ALT_L3_SEC_L4SP_CAN0_LSB 8
983 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field. */
984 #define ALT_L3_SEC_L4SP_CAN0_MSB 8
985 /* The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field. */
986 #define ALT_L3_SEC_L4SP_CAN0_WIDTH 1
987 /* The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value. */
988 #define ALT_L3_SEC_L4SP_CAN0_SET_MSK 0x00000100
989 /* The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value. */
990 #define ALT_L3_SEC_L4SP_CAN0_CLR_MSK 0xfffffeff
991 /* The reset value of the ALT_L3_SEC_L4SP_CAN0 register field. */
992 #define ALT_L3_SEC_L4SP_CAN0_RESET 0x0
993 /* Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register. */
994 #define ALT_L3_SEC_L4SP_CAN0_GET(value) (((value) & 0x00000100) >> 8)
995 /* Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register. */
996 #define ALT_L3_SEC_L4SP_CAN0_SET(value) (((value) << 8) & 0x00000100)
997 
998 /*
999  * Field : CAN 1 Security - can1
1000  *
1001  * Controls whether secure or non-secure masters can access the CAN 1 slave.
1002  *
1003  * Field Enumeration Values:
1004  *
1005  * Enum | Value | Description
1006  * :---------------------------------|:------|:----------------------------------------------
1007  * ALT_L3_SEC_L4SP_CAN1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1008  * : | | master.
1009  * ALT_L3_SEC_L4SP_CAN1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1010  * : | | non-secure masters.
1011  *
1012  * Field Access Macros:
1013  *
1014  */
1015 /*
1016  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
1017  *
1018  * The slave can only be accessed by a secure master.
1019  */
1020 #define ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0
1021 /*
1022  * Enumerated value for register field ALT_L3_SEC_L4SP_CAN1
1023  *
1024  * The slave can only be accessed by a secure or non-secure masters.
1025  */
1026 #define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1
1027 
1028 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
1029 #define ALT_L3_SEC_L4SP_CAN1_LSB 9
1030 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field. */
1031 #define ALT_L3_SEC_L4SP_CAN1_MSB 9
1032 /* The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field. */
1033 #define ALT_L3_SEC_L4SP_CAN1_WIDTH 1
1034 /* The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value. */
1035 #define ALT_L3_SEC_L4SP_CAN1_SET_MSK 0x00000200
1036 /* The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value. */
1037 #define ALT_L3_SEC_L4SP_CAN1_CLR_MSK 0xfffffdff
1038 /* The reset value of the ALT_L3_SEC_L4SP_CAN1 register field. */
1039 #define ALT_L3_SEC_L4SP_CAN1_RESET 0x0
1040 /* Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register. */
1041 #define ALT_L3_SEC_L4SP_CAN1_GET(value) (((value) & 0x00000200) >> 9)
1042 /* Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register. */
1043 #define ALT_L3_SEC_L4SP_CAN1_SET(value) (((value) << 9) & 0x00000200)
1044 
1045 /*
1046  * Field : SP Timer 1 Security - sptimer1
1047  *
1048  * Controls whether secure or non-secure masters can access the SP Timer 1 slave.
1049  *
1050  * Field Enumeration Values:
1051  *
1052  * Enum | Value | Description
1053  * :-----------------------------------|:------|:----------------------------------------------
1054  * ALT_L3_SEC_L4SP_SPTMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1055  * : | | master.
1056  * ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1057  * : | | non-secure masters.
1058  *
1059  * Field Access Macros:
1060  *
1061  */
1062 /*
1063  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
1064  *
1065  * The slave can only be accessed by a secure master.
1066  */
1067 #define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0
1068 /*
1069  * Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1
1070  *
1071  * The slave can only be accessed by a secure or non-secure masters.
1072  */
1073 #define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1
1074 
1075 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1076 #define ALT_L3_SEC_L4SP_SPTMR1_LSB 10
1077 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1078 #define ALT_L3_SEC_L4SP_SPTMR1_MSB 10
1079 /* The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1080 #define ALT_L3_SEC_L4SP_SPTMR1_WIDTH 1
1081 /* The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
1082 #define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK 0x00000400
1083 /* The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value. */
1084 #define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK 0xfffffbff
1085 /* The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field. */
1086 #define ALT_L3_SEC_L4SP_SPTMR1_RESET 0x0
1087 /* Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register. */
1088 #define ALT_L3_SEC_L4SP_SPTMR1_GET(value) (((value) & 0x00000400) >> 10)
1089 /* Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register. */
1090 #define ALT_L3_SEC_L4SP_SPTMR1_SET(value) (((value) << 10) & 0x00000400)
1091 
1092 #ifndef __ASSEMBLY__
1093 /*
1094  * WARNING: The C register and register group struct declarations are provided for
1095  * convenience and illustrative purposes. They should, however, be used with
1096  * caution as the C language standard provides no guarantees about the alignment or
1097  * atomicity of device memory accesses. The recommended practice for writing
1098  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1099  * alt_write_word() functions.
1100  *
1101  * The struct declaration for register ALT_L3_SEC_L4SP.
1102  */
1103 struct ALT_L3_SEC_L4SP_s
1104 {
1105  uint32_t sdrregs : 1; /* SDRAM Registers Security */
1106  uint32_t sptimer0 : 1; /* SP Timer 0 Security */
1107  uint32_t i2c0 : 1; /* I2C0 Security */
1108  uint32_t i2c1 : 1; /* I2C1 Security */
1109  uint32_t i2c2 : 1; /* I2C2 (EMAC 0) Security */
1110  uint32_t i2c3 : 1; /* I2C3 (EMAC 1) Security */
1111  uint32_t uart0 : 1; /* UART 0 Security */
1112  uint32_t uart1 : 1; /* UART 1 Security */
1113  uint32_t can0 : 1; /* CAN 0 Security */
1114  uint32_t can1 : 1; /* CAN 1 Security */
1115  uint32_t sptimer1 : 1; /* SP Timer 1 Security */
1116  uint32_t : 21; /* *UNDEFINED* */
1117 };
1118 
1119 /* The typedef declaration for register ALT_L3_SEC_L4SP. */
1120 typedef volatile struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t;
1121 #endif /* __ASSEMBLY__ */
1122 
1123 /* The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component. */
1124 #define ALT_L3_SEC_L4SP_OFST 0x4
1125 
1126 /*
1127  * Register : L4 MP Peripherals Security - l4mp
1128  *
1129  * Controls security settings for L4 MP peripherals.
1130  *
1131  * Register Layout
1132  *
1133  * Bits | Access | Reset | Description
1134  * :--------|:-------|:------|:-------------------------------
1135  * [0] | W | 0x0 | FPGA Manager Register Security
1136  * [1] | W | 0x0 | DAP Security
1137  * [2] | W | 0x0 | QSPI Registers Security
1138  * [3] | W | 0x0 | SDMMC Security
1139  * [4] | W | 0x0 | EMAC 0 Security
1140  * [5] | W | 0x0 | EMAC 1 Security
1141  * [6] | W | 0x0 | ACP ID Mapper Security
1142  * [7] | W | 0x0 | GPIO 0 Security
1143  * [8] | W | 0x0 | GPIO 1 Security
1144  * [9] | W | 0x0 | GPIO 2 Security
1145  * [31:10] | ??? | 0x0 | *UNDEFINED*
1146  *
1147  */
1148 /*
1149  * Field : FPGA Manager Register Security - fpgamgrregs
1150  *
1151  * Controls whether secure or non-secure masters can access the FPGA Manager
1152  * Register slave.
1153  *
1154  * Field Enumeration Values:
1155  *
1156  * Enum | Value | Description
1157  * :------------------------------------|:------|:----------------------------------------------
1158  * ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1159  * : | | master.
1160  * ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1161  * : | | non-secure masters.
1162  *
1163  * Field Access Macros:
1164  *
1165  */
1166 /*
1167  * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
1168  *
1169  * The slave can only be accessed by a secure master.
1170  */
1171 #define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0
1172 /*
1173  * Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR
1174  *
1175  * The slave can only be accessed by a secure or non-secure masters.
1176  */
1177 #define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1
1178 
1179 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1180 #define ALT_L3_SEC_L4MP_FPGAMGR_LSB 0
1181 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1182 #define ALT_L3_SEC_L4MP_FPGAMGR_MSB 0
1183 /* The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1184 #define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH 1
1185 /* The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
1186 #define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK 0x00000001
1187 /* The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value. */
1188 #define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK 0xfffffffe
1189 /* The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field. */
1190 #define ALT_L3_SEC_L4MP_FPGAMGR_RESET 0x0
1191 /* Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register. */
1192 #define ALT_L3_SEC_L4MP_FPGAMGR_GET(value) (((value) & 0x00000001) >> 0)
1193 /* Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register. */
1194 #define ALT_L3_SEC_L4MP_FPGAMGR_SET(value) (((value) << 0) & 0x00000001)
1195 
1196 /*
1197  * Field : DAP Security - dap
1198  *
1199  * Controls whether secure or non-secure masters can access the DAP slave.
1200  *
1201  * Field Enumeration Values:
1202  *
1203  * Enum | Value | Description
1204  * :--------------------------------|:------|:----------------------------------------------
1205  * ALT_L3_SEC_L4MP_DAP_E_SECURE | 0x0 | The slave can only be accessed by a secure
1206  * : | | master.
1207  * ALT_L3_SEC_L4MP_DAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1208  * : | | non-secure masters.
1209  *
1210  * Field Access Macros:
1211  *
1212  */
1213 /*
1214  * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
1215  *
1216  * The slave can only be accessed by a secure master.
1217  */
1218 #define ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0
1219 /*
1220  * Enumerated value for register field ALT_L3_SEC_L4MP_DAP
1221  *
1222  * The slave can only be accessed by a secure or non-secure masters.
1223  */
1224 #define ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1
1225 
1226 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
1227 #define ALT_L3_SEC_L4MP_DAP_LSB 1
1228 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field. */
1229 #define ALT_L3_SEC_L4MP_DAP_MSB 1
1230 /* The width in bits of the ALT_L3_SEC_L4MP_DAP register field. */
1231 #define ALT_L3_SEC_L4MP_DAP_WIDTH 1
1232 /* The mask used to set the ALT_L3_SEC_L4MP_DAP register field value. */
1233 #define ALT_L3_SEC_L4MP_DAP_SET_MSK 0x00000002
1234 /* The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value. */
1235 #define ALT_L3_SEC_L4MP_DAP_CLR_MSK 0xfffffffd
1236 /* The reset value of the ALT_L3_SEC_L4MP_DAP register field. */
1237 #define ALT_L3_SEC_L4MP_DAP_RESET 0x0
1238 /* Extracts the ALT_L3_SEC_L4MP_DAP field value from a register. */
1239 #define ALT_L3_SEC_L4MP_DAP_GET(value) (((value) & 0x00000002) >> 1)
1240 /* Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register. */
1241 #define ALT_L3_SEC_L4MP_DAP_SET(value) (((value) << 1) & 0x00000002)
1242 
1243 /*
1244  * Field : QSPI Registers Security - qspiregs
1245  *
1246  * Controls whether secure or non-secure masters can access the QSPI Registers
1247  * slave.
1248  *
1249  * Field Enumeration Values:
1250  *
1251  * Enum | Value | Description
1252  * :---------------------------------|:------|:----------------------------------------------
1253  * ALT_L3_SEC_L4MP_QSPI_E_SECURE | 0x0 | The slave can only be accessed by a secure
1254  * : | | master.
1255  * ALT_L3_SEC_L4MP_QSPI_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1256  * : | | non-secure masters.
1257  *
1258  * Field Access Macros:
1259  *
1260  */
1261 /*
1262  * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
1263  *
1264  * The slave can only be accessed by a secure master.
1265  */
1266 #define ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0
1267 /*
1268  * Enumerated value for register field ALT_L3_SEC_L4MP_QSPI
1269  *
1270  * The slave can only be accessed by a secure or non-secure masters.
1271  */
1272 #define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1
1273 
1274 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
1275 #define ALT_L3_SEC_L4MP_QSPI_LSB 2
1276 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field. */
1277 #define ALT_L3_SEC_L4MP_QSPI_MSB 2
1278 /* The width in bits of the ALT_L3_SEC_L4MP_QSPI register field. */
1279 #define ALT_L3_SEC_L4MP_QSPI_WIDTH 1
1280 /* The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value. */
1281 #define ALT_L3_SEC_L4MP_QSPI_SET_MSK 0x00000004
1282 /* The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value. */
1283 #define ALT_L3_SEC_L4MP_QSPI_CLR_MSK 0xfffffffb
1284 /* The reset value of the ALT_L3_SEC_L4MP_QSPI register field. */
1285 #define ALT_L3_SEC_L4MP_QSPI_RESET 0x0
1286 /* Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register. */
1287 #define ALT_L3_SEC_L4MP_QSPI_GET(value) (((value) & 0x00000004) >> 2)
1288 /* Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register. */
1289 #define ALT_L3_SEC_L4MP_QSPI_SET(value) (((value) << 2) & 0x00000004)
1290 
1291 /*
1292  * Field : SDMMC Security - sdmmc
1293  *
1294  * Controls whether secure or non-secure masters can access the SDMMC slave.
1295  *
1296  * Field Enumeration Values:
1297  *
1298  * Enum | Value | Description
1299  * :----------------------------------|:------|:----------------------------------------------
1300  * ALT_L3_SEC_L4MP_SDMMC_E_SECURE | 0x0 | The slave can only be accessed by a secure
1301  * : | | master.
1302  * ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1303  * : | | non-secure masters.
1304  *
1305  * Field Access Macros:
1306  *
1307  */
1308 /*
1309  * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
1310  *
1311  * The slave can only be accessed by a secure master.
1312  */
1313 #define ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0
1314 /*
1315  * Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC
1316  *
1317  * The slave can only be accessed by a secure or non-secure masters.
1318  */
1319 #define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1
1320 
1321 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
1322 #define ALT_L3_SEC_L4MP_SDMMC_LSB 3
1323 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field. */
1324 #define ALT_L3_SEC_L4MP_SDMMC_MSB 3
1325 /* The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field. */
1326 #define ALT_L3_SEC_L4MP_SDMMC_WIDTH 1
1327 /* The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value. */
1328 #define ALT_L3_SEC_L4MP_SDMMC_SET_MSK 0x00000008
1329 /* The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value. */
1330 #define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK 0xfffffff7
1331 /* The reset value of the ALT_L3_SEC_L4MP_SDMMC register field. */
1332 #define ALT_L3_SEC_L4MP_SDMMC_RESET 0x0
1333 /* Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register. */
1334 #define ALT_L3_SEC_L4MP_SDMMC_GET(value) (((value) & 0x00000008) >> 3)
1335 /* Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register. */
1336 #define ALT_L3_SEC_L4MP_SDMMC_SET(value) (((value) << 3) & 0x00000008)
1337 
1338 /*
1339  * Field : EMAC 0 Security - emac0
1340  *
1341  * Controls whether secure or non-secure masters can access the EMAC 0 slave.
1342  *
1343  * Field Enumeration Values:
1344  *
1345  * Enum | Value | Description
1346  * :----------------------------------|:------|:----------------------------------------------
1347  * ALT_L3_SEC_L4MP_EMAC0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1348  * : | | master.
1349  * ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1350  * : | | non-secure masters.
1351  *
1352  * Field Access Macros:
1353  *
1354  */
1355 /*
1356  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
1357  *
1358  * The slave can only be accessed by a secure master.
1359  */
1360 #define ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0
1361 /*
1362  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0
1363  *
1364  * The slave can only be accessed by a secure or non-secure masters.
1365  */
1366 #define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1
1367 
1368 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1369 #define ALT_L3_SEC_L4MP_EMAC0_LSB 4
1370 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1371 #define ALT_L3_SEC_L4MP_EMAC0_MSB 4
1372 /* The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1373 #define ALT_L3_SEC_L4MP_EMAC0_WIDTH 1
1374 /* The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value. */
1375 #define ALT_L3_SEC_L4MP_EMAC0_SET_MSK 0x00000010
1376 /* The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value. */
1377 #define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK 0xffffffef
1378 /* The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field. */
1379 #define ALT_L3_SEC_L4MP_EMAC0_RESET 0x0
1380 /* Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register. */
1381 #define ALT_L3_SEC_L4MP_EMAC0_GET(value) (((value) & 0x00000010) >> 4)
1382 /* Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register. */
1383 #define ALT_L3_SEC_L4MP_EMAC0_SET(value) (((value) << 4) & 0x00000010)
1384 
1385 /*
1386  * Field : EMAC 1 Security - emac1
1387  *
1388  * Controls whether secure or non-secure masters can access the EMAC 1 slave.
1389  *
1390  * Field Enumeration Values:
1391  *
1392  * Enum | Value | Description
1393  * :----------------------------------|:------|:----------------------------------------------
1394  * ALT_L3_SEC_L4MP_EMAC1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1395  * : | | master.
1396  * ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1397  * : | | non-secure masters.
1398  *
1399  * Field Access Macros:
1400  *
1401  */
1402 /*
1403  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
1404  *
1405  * The slave can only be accessed by a secure master.
1406  */
1407 #define ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0
1408 /*
1409  * Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1
1410  *
1411  * The slave can only be accessed by a secure or non-secure masters.
1412  */
1413 #define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1
1414 
1415 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1416 #define ALT_L3_SEC_L4MP_EMAC1_LSB 5
1417 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1418 #define ALT_L3_SEC_L4MP_EMAC1_MSB 5
1419 /* The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1420 #define ALT_L3_SEC_L4MP_EMAC1_WIDTH 1
1421 /* The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value. */
1422 #define ALT_L3_SEC_L4MP_EMAC1_SET_MSK 0x00000020
1423 /* The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value. */
1424 #define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK 0xffffffdf
1425 /* The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field. */
1426 #define ALT_L3_SEC_L4MP_EMAC1_RESET 0x0
1427 /* Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register. */
1428 #define ALT_L3_SEC_L4MP_EMAC1_GET(value) (((value) & 0x00000020) >> 5)
1429 /* Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register. */
1430 #define ALT_L3_SEC_L4MP_EMAC1_SET(value) (((value) << 5) & 0x00000020)
1431 
1432 /*
1433  * Field : ACP ID Mapper Security - acpidmap
1434  *
1435  * Controls whether secure or non-secure masters can access the ACP ID Mapper
1436  * slave.
1437  *
1438  * Field Enumeration Values:
1439  *
1440  * Enum | Value | Description
1441  * :-------------------------------------|:------|:----------------------------------------------
1442  * ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE | 0x0 | The slave can only be accessed by a secure
1443  * : | | master.
1444  * ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1445  * : | | non-secure masters.
1446  *
1447  * Field Access Macros:
1448  *
1449  */
1450 /*
1451  * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
1452  *
1453  * The slave can only be accessed by a secure master.
1454  */
1455 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0
1456 /*
1457  * Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP
1458  *
1459  * The slave can only be accessed by a secure or non-secure masters.
1460  */
1461 #define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1
1462 
1463 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1464 #define ALT_L3_SEC_L4MP_ACPIDMAP_LSB 6
1465 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1466 #define ALT_L3_SEC_L4MP_ACPIDMAP_MSB 6
1467 /* The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1468 #define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH 1
1469 /* The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
1470 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK 0x00000040
1471 /* The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value. */
1472 #define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK 0xffffffbf
1473 /* The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field. */
1474 #define ALT_L3_SEC_L4MP_ACPIDMAP_RESET 0x0
1475 /* Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register. */
1476 #define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value) (((value) & 0x00000040) >> 6)
1477 /* Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register. */
1478 #define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value) (((value) << 6) & 0x00000040)
1479 
1480 /*
1481  * Field : GPIO 0 Security - gpio0
1482  *
1483  * Controls whether secure or non-secure masters can access the GPIO 0 slave.
1484  *
1485  * Field Enumeration Values:
1486  *
1487  * Enum | Value | Description
1488  * :----------------------------------|:------|:----------------------------------------------
1489  * ALT_L3_SEC_L4MP_GPIO0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1490  * : | | master.
1491  * ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1492  * : | | non-secure masters.
1493  *
1494  * Field Access Macros:
1495  *
1496  */
1497 /*
1498  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
1499  *
1500  * The slave can only be accessed by a secure master.
1501  */
1502 #define ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0
1503 /*
1504  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0
1505  *
1506  * The slave can only be accessed by a secure or non-secure masters.
1507  */
1508 #define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1
1509 
1510 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1511 #define ALT_L3_SEC_L4MP_GPIO0_LSB 7
1512 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1513 #define ALT_L3_SEC_L4MP_GPIO0_MSB 7
1514 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1515 #define ALT_L3_SEC_L4MP_GPIO0_WIDTH 1
1516 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value. */
1517 #define ALT_L3_SEC_L4MP_GPIO0_SET_MSK 0x00000080
1518 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value. */
1519 #define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK 0xffffff7f
1520 /* The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field. */
1521 #define ALT_L3_SEC_L4MP_GPIO0_RESET 0x0
1522 /* Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register. */
1523 #define ALT_L3_SEC_L4MP_GPIO0_GET(value) (((value) & 0x00000080) >> 7)
1524 /* Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register. */
1525 #define ALT_L3_SEC_L4MP_GPIO0_SET(value) (((value) << 7) & 0x00000080)
1526 
1527 /*
1528  * Field : GPIO 1 Security - gpio1
1529  *
1530  * Controls whether secure or non-secure masters can access the GPIO 1 slave.
1531  *
1532  * Field Enumeration Values:
1533  *
1534  * Enum | Value | Description
1535  * :----------------------------------|:------|:----------------------------------------------
1536  * ALT_L3_SEC_L4MP_GPIO1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1537  * : | | master.
1538  * ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1539  * : | | non-secure masters.
1540  *
1541  * Field Access Macros:
1542  *
1543  */
1544 /*
1545  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
1546  *
1547  * The slave can only be accessed by a secure master.
1548  */
1549 #define ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0
1550 /*
1551  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1
1552  *
1553  * The slave can only be accessed by a secure or non-secure masters.
1554  */
1555 #define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1
1556 
1557 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1558 #define ALT_L3_SEC_L4MP_GPIO1_LSB 8
1559 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1560 #define ALT_L3_SEC_L4MP_GPIO1_MSB 8
1561 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1562 #define ALT_L3_SEC_L4MP_GPIO1_WIDTH 1
1563 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value. */
1564 #define ALT_L3_SEC_L4MP_GPIO1_SET_MSK 0x00000100
1565 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value. */
1566 #define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK 0xfffffeff
1567 /* The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field. */
1568 #define ALT_L3_SEC_L4MP_GPIO1_RESET 0x0
1569 /* Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register. */
1570 #define ALT_L3_SEC_L4MP_GPIO1_GET(value) (((value) & 0x00000100) >> 8)
1571 /* Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register. */
1572 #define ALT_L3_SEC_L4MP_GPIO1_SET(value) (((value) << 8) & 0x00000100)
1573 
1574 /*
1575  * Field : GPIO 2 Security - gpio2
1576  *
1577  * Controls whether secure or non-secure masters can access the GPIO 2 slave.
1578  *
1579  * Field Enumeration Values:
1580  *
1581  * Enum | Value | Description
1582  * :----------------------------------|:------|:----------------------------------------------
1583  * ALT_L3_SEC_L4MP_GPIO2_E_SECURE | 0x0 | The slave can only be accessed by a secure
1584  * : | | master.
1585  * ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1586  * : | | non-secure masters.
1587  *
1588  * Field Access Macros:
1589  *
1590  */
1591 /*
1592  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
1593  *
1594  * The slave can only be accessed by a secure master.
1595  */
1596 #define ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0
1597 /*
1598  * Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2
1599  *
1600  * The slave can only be accessed by a secure or non-secure masters.
1601  */
1602 #define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1
1603 
1604 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1605 #define ALT_L3_SEC_L4MP_GPIO2_LSB 9
1606 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1607 #define ALT_L3_SEC_L4MP_GPIO2_MSB 9
1608 /* The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1609 #define ALT_L3_SEC_L4MP_GPIO2_WIDTH 1
1610 /* The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value. */
1611 #define ALT_L3_SEC_L4MP_GPIO2_SET_MSK 0x00000200
1612 /* The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value. */
1613 #define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK 0xfffffdff
1614 /* The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field. */
1615 #define ALT_L3_SEC_L4MP_GPIO2_RESET 0x0
1616 /* Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register. */
1617 #define ALT_L3_SEC_L4MP_GPIO2_GET(value) (((value) & 0x00000200) >> 9)
1618 /* Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register. */
1619 #define ALT_L3_SEC_L4MP_GPIO2_SET(value) (((value) << 9) & 0x00000200)
1620 
1621 #ifndef __ASSEMBLY__
1622 /*
1623  * WARNING: The C register and register group struct declarations are provided for
1624  * convenience and illustrative purposes. They should, however, be used with
1625  * caution as the C language standard provides no guarantees about the alignment or
1626  * atomicity of device memory accesses. The recommended practice for writing
1627  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1628  * alt_write_word() functions.
1629  *
1630  * The struct declaration for register ALT_L3_SEC_L4MP.
1631  */
1632 struct ALT_L3_SEC_L4MP_s
1633 {
1634  uint32_t fpgamgrregs : 1; /* FPGA Manager Register Security */
1635  uint32_t dap : 1; /* DAP Security */
1636  uint32_t qspiregs : 1; /* QSPI Registers Security */
1637  uint32_t sdmmc : 1; /* SDMMC Security */
1638  uint32_t emac0 : 1; /* EMAC 0 Security */
1639  uint32_t emac1 : 1; /* EMAC 1 Security */
1640  uint32_t acpidmap : 1; /* ACP ID Mapper Security */
1641  uint32_t gpio0 : 1; /* GPIO 0 Security */
1642  uint32_t gpio1 : 1; /* GPIO 1 Security */
1643  uint32_t gpio2 : 1; /* GPIO 2 Security */
1644  uint32_t : 22; /* *UNDEFINED* */
1645 };
1646 
1647 /* The typedef declaration for register ALT_L3_SEC_L4MP. */
1648 typedef volatile struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t;
1649 #endif /* __ASSEMBLY__ */
1650 
1651 /* The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component. */
1652 #define ALT_L3_SEC_L4MP_OFST 0x8
1653 
1654 /*
1655  * Register : L4 OSC1 Peripherals Security - l4osc1
1656  *
1657  * Controls security settings for L4 OSC1 peripherals.
1658  *
1659  * Register Layout
1660  *
1661  * Bits | Access | Reset | Description
1662  * :-------|:-------|:------|:-----------------------------
1663  * [0] | W | 0x0 | L4 Watchdog Timer 0 Security
1664  * [1] | W | 0x0 | L4 Watchdog Timer 0 Security
1665  * [2] | W | 0x0 | Clock Manager Security
1666  * [3] | W | 0x0 | Reset Manager Security
1667  * [4] | W | 0x0 | System Manager Security
1668  * [5] | W | 0x0 | OSC1 Timer 0 Security
1669  * [6] | W | 0x0 | OSC1 Timer 1 Security
1670  * [31:7] | ??? | 0x0 | *UNDEFINED*
1671  *
1672  */
1673 /*
1674  * Field : L4 Watchdog Timer 0 Security - l4wd0
1675  *
1676  * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
1677  * slave.
1678  *
1679  * Field Enumeration Values:
1680  *
1681  * Enum | Value | Description
1682  * :------------------------------------|:------|:----------------------------------------------
1683  * ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1684  * : | | master.
1685  * ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1686  * : | | non-secure masters.
1687  *
1688  * Field Access Macros:
1689  *
1690  */
1691 /*
1692  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
1693  *
1694  * The slave can only be accessed by a secure master.
1695  */
1696 #define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0
1697 /*
1698  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0
1699  *
1700  * The slave can only be accessed by a secure or non-secure masters.
1701  */
1702 #define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1
1703 
1704 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1705 #define ALT_L3_SEC_L4OSC1_L4WD0_LSB 0
1706 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1707 #define ALT_L3_SEC_L4OSC1_L4WD0_MSB 0
1708 /* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1709 #define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH 1
1710 /* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
1711 #define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK 0x00000001
1712 /* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value. */
1713 #define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK 0xfffffffe
1714 /* The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field. */
1715 #define ALT_L3_SEC_L4OSC1_L4WD0_RESET 0x0
1716 /* Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register. */
1717 #define ALT_L3_SEC_L4OSC1_L4WD0_GET(value) (((value) & 0x00000001) >> 0)
1718 /* Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register. */
1719 #define ALT_L3_SEC_L4OSC1_L4WD0_SET(value) (((value) << 0) & 0x00000001)
1720 
1721 /*
1722  * Field : L4 Watchdog Timer 0 Security - l4wd1
1723  *
1724  * Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0
1725  * slave.
1726  *
1727  * Field Enumeration Values:
1728  *
1729  * Enum | Value | Description
1730  * :------------------------------------|:------|:----------------------------------------------
1731  * ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1732  * : | | master.
1733  * ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1734  * : | | non-secure masters.
1735  *
1736  * Field Access Macros:
1737  *
1738  */
1739 /*
1740  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
1741  *
1742  * The slave can only be accessed by a secure master.
1743  */
1744 #define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0
1745 /*
1746  * Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1
1747  *
1748  * The slave can only be accessed by a secure or non-secure masters.
1749  */
1750 #define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1
1751 
1752 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1753 #define ALT_L3_SEC_L4OSC1_L4WD1_LSB 1
1754 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1755 #define ALT_L3_SEC_L4OSC1_L4WD1_MSB 1
1756 /* The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1757 #define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH 1
1758 /* The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
1759 #define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK 0x00000002
1760 /* The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value. */
1761 #define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK 0xfffffffd
1762 /* The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field. */
1763 #define ALT_L3_SEC_L4OSC1_L4WD1_RESET 0x0
1764 /* Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register. */
1765 #define ALT_L3_SEC_L4OSC1_L4WD1_GET(value) (((value) & 0x00000002) >> 1)
1766 /* Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register. */
1767 #define ALT_L3_SEC_L4OSC1_L4WD1_SET(value) (((value) << 1) & 0x00000002)
1768 
1769 /*
1770  * Field : Clock Manager Security - clkmgr
1771  *
1772  * Controls whether secure or non-secure masters can access the Clock Manager
1773  * slave.
1774  *
1775  * Field Enumeration Values:
1776  *
1777  * Enum | Value | Description
1778  * :-------------------------------------|:------|:----------------------------------------------
1779  * ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1780  * : | | master.
1781  * ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1782  * : | | non-secure masters.
1783  *
1784  * Field Access Macros:
1785  *
1786  */
1787 /*
1788  * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
1789  *
1790  * The slave can only be accessed by a secure master.
1791  */
1792 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0
1793 /*
1794  * Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR
1795  *
1796  * The slave can only be accessed by a secure or non-secure masters.
1797  */
1798 #define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1
1799 
1800 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1801 #define ALT_L3_SEC_L4OSC1_CLKMGR_LSB 2
1802 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1803 #define ALT_L3_SEC_L4OSC1_CLKMGR_MSB 2
1804 /* The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1805 #define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH 1
1806 /* The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
1807 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK 0x00000004
1808 /* The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value. */
1809 #define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK 0xfffffffb
1810 /* The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field. */
1811 #define ALT_L3_SEC_L4OSC1_CLKMGR_RESET 0x0
1812 /* Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register. */
1813 #define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value) (((value) & 0x00000004) >> 2)
1814 /* Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register. */
1815 #define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value) (((value) << 2) & 0x00000004)
1816 
1817 /*
1818  * Field : Reset Manager Security - rstmgr
1819  *
1820  * Controls whether secure or non-secure masters can access the Reset Manager
1821  * slave.
1822  *
1823  * Field Enumeration Values:
1824  *
1825  * Enum | Value | Description
1826  * :-------------------------------------|:------|:----------------------------------------------
1827  * ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1828  * : | | master.
1829  * ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1830  * : | | non-secure masters.
1831  *
1832  * Field Access Macros:
1833  *
1834  */
1835 /*
1836  * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
1837  *
1838  * The slave can only be accessed by a secure master.
1839  */
1840 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0
1841 /*
1842  * Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR
1843  *
1844  * The slave can only be accessed by a secure or non-secure masters.
1845  */
1846 #define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1
1847 
1848 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1849 #define ALT_L3_SEC_L4OSC1_RSTMGR_LSB 3
1850 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1851 #define ALT_L3_SEC_L4OSC1_RSTMGR_MSB 3
1852 /* The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1853 #define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH 1
1854 /* The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
1855 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK 0x00000008
1856 /* The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value. */
1857 #define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK 0xfffffff7
1858 /* The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field. */
1859 #define ALT_L3_SEC_L4OSC1_RSTMGR_RESET 0x0
1860 /* Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register. */
1861 #define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value) (((value) & 0x00000008) >> 3)
1862 /* Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register. */
1863 #define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value) (((value) << 3) & 0x00000008)
1864 
1865 /*
1866  * Field : System Manager Security - sysmgr
1867  *
1868  * Controls whether secure or non-secure masters can access the System Manager
1869  * slave.
1870  *
1871  * Field Enumeration Values:
1872  *
1873  * Enum | Value | Description
1874  * :-------------------------------------|:------|:----------------------------------------------
1875  * ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
1876  * : | | master.
1877  * ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1878  * : | | non-secure masters.
1879  *
1880  * Field Access Macros:
1881  *
1882  */
1883 /*
1884  * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
1885  *
1886  * The slave can only be accessed by a secure master.
1887  */
1888 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0
1889 /*
1890  * Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR
1891  *
1892  * The slave can only be accessed by a secure or non-secure masters.
1893  */
1894 #define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1
1895 
1896 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1897 #define ALT_L3_SEC_L4OSC1_SYSMGR_LSB 4
1898 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1899 #define ALT_L3_SEC_L4OSC1_SYSMGR_MSB 4
1900 /* The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1901 #define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH 1
1902 /* The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
1903 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK 0x00000010
1904 /* The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value. */
1905 #define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK 0xffffffef
1906 /* The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field. */
1907 #define ALT_L3_SEC_L4OSC1_SYSMGR_RESET 0x0
1908 /* Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register. */
1909 #define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value) (((value) & 0x00000010) >> 4)
1910 /* Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register. */
1911 #define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value) (((value) << 4) & 0x00000010)
1912 
1913 /*
1914  * Field : OSC1 Timer 0 Security - osc1timer0
1915  *
1916  * Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave.
1917  *
1918  * Field Enumeration Values:
1919  *
1920  * Enum | Value | Description
1921  * :---------------------------------------|:------|:----------------------------------------------
1922  * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE | 0x0 | The slave can only be accessed by a secure
1923  * : | | master.
1924  * ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1925  * : | | non-secure masters.
1926  *
1927  * Field Access Macros:
1928  *
1929  */
1930 /*
1931  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
1932  *
1933  * The slave can only be accessed by a secure master.
1934  */
1935 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0
1936 /*
1937  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0
1938  *
1939  * The slave can only be accessed by a secure or non-secure masters.
1940  */
1941 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1
1942 
1943 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1944 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB 5
1945 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1946 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB 5
1947 /* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1948 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH 1
1949 /* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
1950 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK 0x00000020
1951 /* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value. */
1952 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK 0xffffffdf
1953 /* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field. */
1954 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET 0x0
1955 /* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register. */
1956 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value) (((value) & 0x00000020) >> 5)
1957 /* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register. */
1958 #define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value) (((value) << 5) & 0x00000020)
1959 
1960 /*
1961  * Field : OSC1 Timer 1 Security - osc1timer1
1962  *
1963  * Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave.
1964  *
1965  * Field Enumeration Values:
1966  *
1967  * Enum | Value | Description
1968  * :---------------------------------------|:------|:----------------------------------------------
1969  * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE | 0x0 | The slave can only be accessed by a secure
1970  * : | | master.
1971  * ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
1972  * : | | non-secure masters.
1973  *
1974  * Field Access Macros:
1975  *
1976  */
1977 /*
1978  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
1979  *
1980  * The slave can only be accessed by a secure master.
1981  */
1982 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0
1983 /*
1984  * Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1
1985  *
1986  * The slave can only be accessed by a secure or non-secure masters.
1987  */
1988 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1
1989 
1990 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1991 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB 6
1992 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1993 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB 6
1994 /* The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
1995 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH 1
1996 /* The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
1997 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK 0x00000040
1998 /* The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value. */
1999 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK 0xffffffbf
2000 /* The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field. */
2001 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET 0x0
2002 /* Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register. */
2003 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value) (((value) & 0x00000040) >> 6)
2004 /* Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register. */
2005 #define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value) (((value) << 6) & 0x00000040)
2006 
2007 #ifndef __ASSEMBLY__
2008 /*
2009  * WARNING: The C register and register group struct declarations are provided for
2010  * convenience and illustrative purposes. They should, however, be used with
2011  * caution as the C language standard provides no guarantees about the alignment or
2012  * atomicity of device memory accesses. The recommended practice for writing
2013  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2014  * alt_write_word() functions.
2015  *
2016  * The struct declaration for register ALT_L3_SEC_L4OSC1.
2017  */
2018 struct ALT_L3_SEC_L4OSC1_s
2019 {
2020  uint32_t l4wd0 : 1; /* L4 Watchdog Timer 0 Security */
2021  uint32_t l4wd1 : 1; /* L4 Watchdog Timer 0 Security */
2022  uint32_t clkmgr : 1; /* Clock Manager Security */
2023  uint32_t rstmgr : 1; /* Reset Manager Security */
2024  uint32_t sysmgr : 1; /* System Manager Security */
2025  uint32_t osc1timer0 : 1; /* OSC1 Timer 0 Security */
2026  uint32_t osc1timer1 : 1; /* OSC1 Timer 1 Security */
2027  uint32_t : 25; /* *UNDEFINED* */
2028 };
2029 
2030 /* The typedef declaration for register ALT_L3_SEC_L4OSC1. */
2031 typedef volatile struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t;
2032 #endif /* __ASSEMBLY__ */
2033 
2034 /* The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component. */
2035 #define ALT_L3_SEC_L4OSC1_OFST 0xc
2036 
2037 /*
2038  * Register : L4 SPIM Peripherals Security - l4spim
2039  *
2040  * Controls security settings for L4 SPIM peripherals.
2041  *
2042  * Register Layout
2043  *
2044  * Bits | Access | Reset | Description
2045  * :-------|:-------|:------|:----------------------
2046  * [0] | W | 0x0 | SPI Master 0 Security
2047  * [1] | W | 0x0 | SPI Master 1 Security
2048  * [2] | W | 0x0 | Scan Manager Security
2049  * [31:3] | ??? | 0x0 | *UNDEFINED*
2050  *
2051  */
2052 /*
2053  * Field : SPI Master 0 Security - spim0
2054  *
2055  * Controls whether secure or non-secure masters can access the SPI Master 0 slave.
2056  *
2057  * Field Enumeration Values:
2058  *
2059  * Enum | Value | Description
2060  * :------------------------------------|:------|:----------------------------------------------
2061  * ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE | 0x0 | The slave can only be accessed by a secure
2062  * : | | master.
2063  * ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2064  * : | | non-secure masters.
2065  *
2066  * Field Access Macros:
2067  *
2068  */
2069 /*
2070  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
2071  *
2072  * The slave can only be accessed by a secure master.
2073  */
2074 #define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0
2075 /*
2076  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0
2077  *
2078  * The slave can only be accessed by a secure or non-secure masters.
2079  */
2080 #define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1
2081 
2082 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2083 #define ALT_L3_SEC_L4SPIM_SPIM0_LSB 0
2084 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2085 #define ALT_L3_SEC_L4SPIM_SPIM0_MSB 0
2086 /* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2087 #define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH 1
2088 /* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
2089 #define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK 0x00000001
2090 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value. */
2091 #define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK 0xfffffffe
2092 /* The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field. */
2093 #define ALT_L3_SEC_L4SPIM_SPIM0_RESET 0x0
2094 /* Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register. */
2095 #define ALT_L3_SEC_L4SPIM_SPIM0_GET(value) (((value) & 0x00000001) >> 0)
2096 /* Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register. */
2097 #define ALT_L3_SEC_L4SPIM_SPIM0_SET(value) (((value) << 0) & 0x00000001)
2098 
2099 /*
2100  * Field : SPI Master 1 Security - spim1
2101  *
2102  * Controls whether secure or non-secure masters can access the SPI Master 1 slave.
2103  *
2104  * Field Enumeration Values:
2105  *
2106  * Enum | Value | Description
2107  * :------------------------------------|:------|:----------------------------------------------
2108  * ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE | 0x0 | The slave can only be accessed by a secure
2109  * : | | master.
2110  * ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2111  * : | | non-secure masters.
2112  *
2113  * Field Access Macros:
2114  *
2115  */
2116 /*
2117  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
2118  *
2119  * The slave can only be accessed by a secure master.
2120  */
2121 #define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0
2122 /*
2123  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1
2124  *
2125  * The slave can only be accessed by a secure or non-secure masters.
2126  */
2127 #define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1
2128 
2129 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2130 #define ALT_L3_SEC_L4SPIM_SPIM1_LSB 1
2131 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2132 #define ALT_L3_SEC_L4SPIM_SPIM1_MSB 1
2133 /* The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2134 #define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH 1
2135 /* The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
2136 #define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK 0x00000002
2137 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value. */
2138 #define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK 0xfffffffd
2139 /* The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field. */
2140 #define ALT_L3_SEC_L4SPIM_SPIM1_RESET 0x0
2141 /* Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register. */
2142 #define ALT_L3_SEC_L4SPIM_SPIM1_GET(value) (((value) & 0x00000002) >> 1)
2143 /* Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register. */
2144 #define ALT_L3_SEC_L4SPIM_SPIM1_SET(value) (((value) << 1) & 0x00000002)
2145 
2146 /*
2147  * Field : Scan Manager Security - scanmgr
2148  *
2149  * Controls whether secure or non-secure masters can access the Scan Manager slave.
2150  *
2151  * Field Enumeration Values:
2152  *
2153  * Enum | Value | Description
2154  * :--------------------------------------|:------|:----------------------------------------------
2155  * ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE | 0x0 | The slave can only be accessed by a secure
2156  * : | | master.
2157  * ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2158  * : | | non-secure masters.
2159  *
2160  * Field Access Macros:
2161  *
2162  */
2163 /*
2164  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
2165  *
2166  * The slave can only be accessed by a secure master.
2167  */
2168 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0
2169 /*
2170  * Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR
2171  *
2172  * The slave can only be accessed by a secure or non-secure masters.
2173  */
2174 #define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1
2175 
2176 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2177 #define ALT_L3_SEC_L4SPIM_SCANMGR_LSB 2
2178 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2179 #define ALT_L3_SEC_L4SPIM_SCANMGR_MSB 2
2180 /* The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2181 #define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH 1
2182 /* The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
2183 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK 0x00000004
2184 /* The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value. */
2185 #define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK 0xfffffffb
2186 /* The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field. */
2187 #define ALT_L3_SEC_L4SPIM_SCANMGR_RESET 0x0
2188 /* Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register. */
2189 #define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value) (((value) & 0x00000004) >> 2)
2190 /* Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register. */
2191 #define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value) (((value) << 2) & 0x00000004)
2192 
2193 #ifndef __ASSEMBLY__
2194 /*
2195  * WARNING: The C register and register group struct declarations are provided for
2196  * convenience and illustrative purposes. They should, however, be used with
2197  * caution as the C language standard provides no guarantees about the alignment or
2198  * atomicity of device memory accesses. The recommended practice for writing
2199  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2200  * alt_write_word() functions.
2201  *
2202  * The struct declaration for register ALT_L3_SEC_L4SPIM.
2203  */
2204 struct ALT_L3_SEC_L4SPIM_s
2205 {
2206  uint32_t spim0 : 1; /* SPI Master 0 Security */
2207  uint32_t spim1 : 1; /* SPI Master 1 Security */
2208  uint32_t scanmgr : 1; /* Scan Manager Security */
2209  uint32_t : 29; /* *UNDEFINED* */
2210 };
2211 
2212 /* The typedef declaration for register ALT_L3_SEC_L4SPIM. */
2213 typedef volatile struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t;
2214 #endif /* __ASSEMBLY__ */
2215 
2216 /* The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component. */
2217 #define ALT_L3_SEC_L4SPIM_OFST 0x10
2218 
2219 /*
2220  * Register : STM Peripheral Security - stm
2221  *
2222  * Controls security settings for STM peripheral.
2223  *
2224  * Register Layout
2225  *
2226  * Bits | Access | Reset | Description
2227  * :-------|:-------|:------|:-------------
2228  * [0] | W | 0x0 | STM Security
2229  * [31:1] | ??? | 0x0 | *UNDEFINED*
2230  *
2231  */
2232 /*
2233  * Field : STM Security - s
2234  *
2235  * Controls whether secure or non-secure masters can access the STM slave.
2236  *
2237  * Field Enumeration Values:
2238  *
2239  * Enum | Value | Description
2240  * :-----------------------------|:------|:----------------------------------------------
2241  * ALT_L3_SEC_STM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2242  * : | | master.
2243  * ALT_L3_SEC_STM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2244  * : | | non-secure masters.
2245  *
2246  * Field Access Macros:
2247  *
2248  */
2249 /*
2250  * Enumerated value for register field ALT_L3_SEC_STM_S
2251  *
2252  * The slave can only be accessed by a secure master.
2253  */
2254 #define ALT_L3_SEC_STM_S_E_SECURE 0x0
2255 /*
2256  * Enumerated value for register field ALT_L3_SEC_STM_S
2257  *
2258  * The slave can only be accessed by a secure or non-secure masters.
2259  */
2260 #define ALT_L3_SEC_STM_S_E_NONSECURE 0x1
2261 
2262 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_STM_S register field. */
2263 #define ALT_L3_SEC_STM_S_LSB 0
2264 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_STM_S register field. */
2265 #define ALT_L3_SEC_STM_S_MSB 0
2266 /* The width in bits of the ALT_L3_SEC_STM_S register field. */
2267 #define ALT_L3_SEC_STM_S_WIDTH 1
2268 /* The mask used to set the ALT_L3_SEC_STM_S register field value. */
2269 #define ALT_L3_SEC_STM_S_SET_MSK 0x00000001
2270 /* The mask used to clear the ALT_L3_SEC_STM_S register field value. */
2271 #define ALT_L3_SEC_STM_S_CLR_MSK 0xfffffffe
2272 /* The reset value of the ALT_L3_SEC_STM_S register field. */
2273 #define ALT_L3_SEC_STM_S_RESET 0x0
2274 /* Extracts the ALT_L3_SEC_STM_S field value from a register. */
2275 #define ALT_L3_SEC_STM_S_GET(value) (((value) & 0x00000001) >> 0)
2276 /* Produces a ALT_L3_SEC_STM_S register field value suitable for setting the register. */
2277 #define ALT_L3_SEC_STM_S_SET(value) (((value) << 0) & 0x00000001)
2278 
2279 #ifndef __ASSEMBLY__
2280 /*
2281  * WARNING: The C register and register group struct declarations are provided for
2282  * convenience and illustrative purposes. They should, however, be used with
2283  * caution as the C language standard provides no guarantees about the alignment or
2284  * atomicity of device memory accesses. The recommended practice for writing
2285  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2286  * alt_write_word() functions.
2287  *
2288  * The struct declaration for register ALT_L3_SEC_STM.
2289  */
2290 struct ALT_L3_SEC_STM_s
2291 {
2292  uint32_t s : 1; /* STM Security */
2293  uint32_t : 31; /* *UNDEFINED* */
2294 };
2295 
2296 /* The typedef declaration for register ALT_L3_SEC_STM. */
2297 typedef volatile struct ALT_L3_SEC_STM_s ALT_L3_SEC_STM_t;
2298 #endif /* __ASSEMBLY__ */
2299 
2300 /* The byte offset of the ALT_L3_SEC_STM register from the beginning of the component. */
2301 #define ALT_L3_SEC_STM_OFST 0x14
2302 
2303 /*
2304  * Register : LWHPS2FPGA AXI Bridge Registers Peripheral Security - lwhps2fpgaregs
2305  *
2306  * Controls security settings for LWHPS2FPGA AXI Bridge Registers peripheral.
2307  *
2308  * Register Layout
2309  *
2310  * Bits | Access | Reset | Description
2311  * :-------|:-------|:------|:-----------------------------------------
2312  * [0] | W | 0x0 | LWHPS2FPGA AXI Bridge Registers Security
2313  * [31:1] | ??? | 0x0 | *UNDEFINED*
2314  *
2315  */
2316 /*
2317  * Field : LWHPS2FPGA AXI Bridge Registers Security - s
2318  *
2319  * Controls whether secure or non-secure masters can access the LWHPS2FPGA AXI
2320  * Bridge Registers slave.
2321  *
2322  * Field Enumeration Values:
2323  *
2324  * Enum | Value | Description
2325  * :-------------------------------|:------|:----------------------------------------------
2326  * ALT_L3_SEC_LWH2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2327  * : | | master.
2328  * ALT_L3_SEC_LWH2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2329  * : | | non-secure masters.
2330  *
2331  * Field Access Macros:
2332  *
2333  */
2334 /*
2335  * Enumerated value for register field ALT_L3_SEC_LWH2F_S
2336  *
2337  * The slave can only be accessed by a secure master.
2338  */
2339 #define ALT_L3_SEC_LWH2F_S_E_SECURE 0x0
2340 /*
2341  * Enumerated value for register field ALT_L3_SEC_LWH2F_S
2342  *
2343  * The slave can only be accessed by a secure or non-secure masters.
2344  */
2345 #define ALT_L3_SEC_LWH2F_S_E_NONSECURE 0x1
2346 
2347 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_LWH2F_S register field. */
2348 #define ALT_L3_SEC_LWH2F_S_LSB 0
2349 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_LWH2F_S register field. */
2350 #define ALT_L3_SEC_LWH2F_S_MSB 0
2351 /* The width in bits of the ALT_L3_SEC_LWH2F_S register field. */
2352 #define ALT_L3_SEC_LWH2F_S_WIDTH 1
2353 /* The mask used to set the ALT_L3_SEC_LWH2F_S register field value. */
2354 #define ALT_L3_SEC_LWH2F_S_SET_MSK 0x00000001
2355 /* The mask used to clear the ALT_L3_SEC_LWH2F_S register field value. */
2356 #define ALT_L3_SEC_LWH2F_S_CLR_MSK 0xfffffffe
2357 /* The reset value of the ALT_L3_SEC_LWH2F_S register field. */
2358 #define ALT_L3_SEC_LWH2F_S_RESET 0x0
2359 /* Extracts the ALT_L3_SEC_LWH2F_S field value from a register. */
2360 #define ALT_L3_SEC_LWH2F_S_GET(value) (((value) & 0x00000001) >> 0)
2361 /* Produces a ALT_L3_SEC_LWH2F_S register field value suitable for setting the register. */
2362 #define ALT_L3_SEC_LWH2F_S_SET(value) (((value) << 0) & 0x00000001)
2363 
2364 #ifndef __ASSEMBLY__
2365 /*
2366  * WARNING: The C register and register group struct declarations are provided for
2367  * convenience and illustrative purposes. They should, however, be used with
2368  * caution as the C language standard provides no guarantees about the alignment or
2369  * atomicity of device memory accesses. The recommended practice for writing
2370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2371  * alt_write_word() functions.
2372  *
2373  * The struct declaration for register ALT_L3_SEC_LWH2F.
2374  */
2375 struct ALT_L3_SEC_LWH2F_s
2376 {
2377  uint32_t s : 1; /* LWHPS2FPGA AXI Bridge Registers Security */
2378  uint32_t : 31; /* *UNDEFINED* */
2379 };
2380 
2381 /* The typedef declaration for register ALT_L3_SEC_LWH2F. */
2382 typedef volatile struct ALT_L3_SEC_LWH2F_s ALT_L3_SEC_LWH2F_t;
2383 #endif /* __ASSEMBLY__ */
2384 
2385 /* The byte offset of the ALT_L3_SEC_LWH2F register from the beginning of the component. */
2386 #define ALT_L3_SEC_LWH2F_OFST 0x18
2387 
2388 /*
2389  * Register : USB1 Registers Peripheral Security - usb1
2390  *
2391  * Controls security settings for USB1 Registers peripheral.
2392  *
2393  * Register Layout
2394  *
2395  * Bits | Access | Reset | Description
2396  * :-------|:-------|:------|:------------------------
2397  * [0] | W | 0x0 | USB1 Registers Security
2398  * [31:1] | ??? | 0x0 | *UNDEFINED*
2399  *
2400  */
2401 /*
2402  * Field : USB1 Registers Security - s
2403  *
2404  * Controls whether secure or non-secure masters can access the USB1 Registers
2405  * slave.
2406  *
2407  * Field Enumeration Values:
2408  *
2409  * Enum | Value | Description
2410  * :------------------------------|:------|:----------------------------------------------
2411  * ALT_L3_SEC_USB1_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2412  * : | | master.
2413  * ALT_L3_SEC_USB1_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2414  * : | | non-secure masters.
2415  *
2416  * Field Access Macros:
2417  *
2418  */
2419 /*
2420  * Enumerated value for register field ALT_L3_SEC_USB1_S
2421  *
2422  * The slave can only be accessed by a secure master.
2423  */
2424 #define ALT_L3_SEC_USB1_S_E_SECURE 0x0
2425 /*
2426  * Enumerated value for register field ALT_L3_SEC_USB1_S
2427  *
2428  * The slave can only be accessed by a secure or non-secure masters.
2429  */
2430 #define ALT_L3_SEC_USB1_S_E_NONSECURE 0x1
2431 
2432 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB1_S register field. */
2433 #define ALT_L3_SEC_USB1_S_LSB 0
2434 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB1_S register field. */
2435 #define ALT_L3_SEC_USB1_S_MSB 0
2436 /* The width in bits of the ALT_L3_SEC_USB1_S register field. */
2437 #define ALT_L3_SEC_USB1_S_WIDTH 1
2438 /* The mask used to set the ALT_L3_SEC_USB1_S register field value. */
2439 #define ALT_L3_SEC_USB1_S_SET_MSK 0x00000001
2440 /* The mask used to clear the ALT_L3_SEC_USB1_S register field value. */
2441 #define ALT_L3_SEC_USB1_S_CLR_MSK 0xfffffffe
2442 /* The reset value of the ALT_L3_SEC_USB1_S register field. */
2443 #define ALT_L3_SEC_USB1_S_RESET 0x0
2444 /* Extracts the ALT_L3_SEC_USB1_S field value from a register. */
2445 #define ALT_L3_SEC_USB1_S_GET(value) (((value) & 0x00000001) >> 0)
2446 /* Produces a ALT_L3_SEC_USB1_S register field value suitable for setting the register. */
2447 #define ALT_L3_SEC_USB1_S_SET(value) (((value) << 0) & 0x00000001)
2448 
2449 #ifndef __ASSEMBLY__
2450 /*
2451  * WARNING: The C register and register group struct declarations are provided for
2452  * convenience and illustrative purposes. They should, however, be used with
2453  * caution as the C language standard provides no guarantees about the alignment or
2454  * atomicity of device memory accesses. The recommended practice for writing
2455  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2456  * alt_write_word() functions.
2457  *
2458  * The struct declaration for register ALT_L3_SEC_USB1.
2459  */
2460 struct ALT_L3_SEC_USB1_s
2461 {
2462  uint32_t s : 1; /* USB1 Registers Security */
2463  uint32_t : 31; /* *UNDEFINED* */
2464 };
2465 
2466 /* The typedef declaration for register ALT_L3_SEC_USB1. */
2467 typedef volatile struct ALT_L3_SEC_USB1_s ALT_L3_SEC_USB1_t;
2468 #endif /* __ASSEMBLY__ */
2469 
2470 /* The byte offset of the ALT_L3_SEC_USB1 register from the beginning of the component. */
2471 #define ALT_L3_SEC_USB1_OFST 0x20
2472 
2473 /*
2474  * Register : NAND Flash Controller Data Peripheral Security - nanddata
2475  *
2476  * Controls security settings for NAND Flash Controller Data peripheral.
2477  *
2478  * Register Layout
2479  *
2480  * Bits | Access | Reset | Description
2481  * :-------|:-------|:------|:------------------------------------
2482  * [0] | W | 0x0 | NAND Flash Controller Data Security
2483  * [31:1] | ??? | 0x0 | *UNDEFINED*
2484  *
2485  */
2486 /*
2487  * Field : NAND Flash Controller Data Security - s
2488  *
2489  * Controls whether secure or non-secure masters can access the NAND Flash
2490  * Controller Data slave.
2491  *
2492  * Field Enumeration Values:
2493  *
2494  * Enum | Value | Description
2495  * :----------------------------------|:------|:----------------------------------------------
2496  * ALT_L3_SEC_NANDDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2497  * : | | master.
2498  * ALT_L3_SEC_NANDDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2499  * : | | non-secure masters.
2500  *
2501  * Field Access Macros:
2502  *
2503  */
2504 /*
2505  * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
2506  *
2507  * The slave can only be accessed by a secure master.
2508  */
2509 #define ALT_L3_SEC_NANDDATA_S_E_SECURE 0x0
2510 /*
2511  * Enumerated value for register field ALT_L3_SEC_NANDDATA_S
2512  *
2513  * The slave can only be accessed by a secure or non-secure masters.
2514  */
2515 #define ALT_L3_SEC_NANDDATA_S_E_NONSECURE 0x1
2516 
2517 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
2518 #define ALT_L3_SEC_NANDDATA_S_LSB 0
2519 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NANDDATA_S register field. */
2520 #define ALT_L3_SEC_NANDDATA_S_MSB 0
2521 /* The width in bits of the ALT_L3_SEC_NANDDATA_S register field. */
2522 #define ALT_L3_SEC_NANDDATA_S_WIDTH 1
2523 /* The mask used to set the ALT_L3_SEC_NANDDATA_S register field value. */
2524 #define ALT_L3_SEC_NANDDATA_S_SET_MSK 0x00000001
2525 /* The mask used to clear the ALT_L3_SEC_NANDDATA_S register field value. */
2526 #define ALT_L3_SEC_NANDDATA_S_CLR_MSK 0xfffffffe
2527 /* The reset value of the ALT_L3_SEC_NANDDATA_S register field. */
2528 #define ALT_L3_SEC_NANDDATA_S_RESET 0x0
2529 /* Extracts the ALT_L3_SEC_NANDDATA_S field value from a register. */
2530 #define ALT_L3_SEC_NANDDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2531 /* Produces a ALT_L3_SEC_NANDDATA_S register field value suitable for setting the register. */
2532 #define ALT_L3_SEC_NANDDATA_S_SET(value) (((value) << 0) & 0x00000001)
2533 
2534 #ifndef __ASSEMBLY__
2535 /*
2536  * WARNING: The C register and register group struct declarations are provided for
2537  * convenience and illustrative purposes. They should, however, be used with
2538  * caution as the C language standard provides no guarantees about the alignment or
2539  * atomicity of device memory accesses. The recommended practice for writing
2540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2541  * alt_write_word() functions.
2542  *
2543  * The struct declaration for register ALT_L3_SEC_NANDDATA.
2544  */
2545 struct ALT_L3_SEC_NANDDATA_s
2546 {
2547  uint32_t s : 1; /* NAND Flash Controller Data Security */
2548  uint32_t : 31; /* *UNDEFINED* */
2549 };
2550 
2551 /* The typedef declaration for register ALT_L3_SEC_NANDDATA. */
2552 typedef volatile struct ALT_L3_SEC_NANDDATA_s ALT_L3_SEC_NANDDATA_t;
2553 #endif /* __ASSEMBLY__ */
2554 
2555 /* The byte offset of the ALT_L3_SEC_NANDDATA register from the beginning of the component. */
2556 #define ALT_L3_SEC_NANDDATA_OFST 0x24
2557 
2558 /*
2559  * Register : USB0 Registers Peripheral Security - usb0
2560  *
2561  * Controls security settings for USB0 Registers peripheral.
2562  *
2563  * Register Layout
2564  *
2565  * Bits | Access | Reset | Description
2566  * :-------|:-------|:------|:------------------------
2567  * [0] | W | 0x0 | USB0 Registers Security
2568  * [31:1] | ??? | 0x0 | *UNDEFINED*
2569  *
2570  */
2571 /*
2572  * Field : USB0 Registers Security - s
2573  *
2574  * Controls whether secure or non-secure masters can access the USB0 Registers
2575  * slave.
2576  *
2577  * Field Enumeration Values:
2578  *
2579  * Enum | Value | Description
2580  * :------------------------------|:------|:----------------------------------------------
2581  * ALT_L3_SEC_USB0_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2582  * : | | master.
2583  * ALT_L3_SEC_USB0_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2584  * : | | non-secure masters.
2585  *
2586  * Field Access Macros:
2587  *
2588  */
2589 /*
2590  * Enumerated value for register field ALT_L3_SEC_USB0_S
2591  *
2592  * The slave can only be accessed by a secure master.
2593  */
2594 #define ALT_L3_SEC_USB0_S_E_SECURE 0x0
2595 /*
2596  * Enumerated value for register field ALT_L3_SEC_USB0_S
2597  *
2598  * The slave can only be accessed by a secure or non-secure masters.
2599  */
2600 #define ALT_L3_SEC_USB0_S_E_NONSECURE 0x1
2601 
2602 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_USB0_S register field. */
2603 #define ALT_L3_SEC_USB0_S_LSB 0
2604 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_USB0_S register field. */
2605 #define ALT_L3_SEC_USB0_S_MSB 0
2606 /* The width in bits of the ALT_L3_SEC_USB0_S register field. */
2607 #define ALT_L3_SEC_USB0_S_WIDTH 1
2608 /* The mask used to set the ALT_L3_SEC_USB0_S register field value. */
2609 #define ALT_L3_SEC_USB0_S_SET_MSK 0x00000001
2610 /* The mask used to clear the ALT_L3_SEC_USB0_S register field value. */
2611 #define ALT_L3_SEC_USB0_S_CLR_MSK 0xfffffffe
2612 /* The reset value of the ALT_L3_SEC_USB0_S register field. */
2613 #define ALT_L3_SEC_USB0_S_RESET 0x0
2614 /* Extracts the ALT_L3_SEC_USB0_S field value from a register. */
2615 #define ALT_L3_SEC_USB0_S_GET(value) (((value) & 0x00000001) >> 0)
2616 /* Produces a ALT_L3_SEC_USB0_S register field value suitable for setting the register. */
2617 #define ALT_L3_SEC_USB0_S_SET(value) (((value) << 0) & 0x00000001)
2618 
2619 #ifndef __ASSEMBLY__
2620 /*
2621  * WARNING: The C register and register group struct declarations are provided for
2622  * convenience and illustrative purposes. They should, however, be used with
2623  * caution as the C language standard provides no guarantees about the alignment or
2624  * atomicity of device memory accesses. The recommended practice for writing
2625  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2626  * alt_write_word() functions.
2627  *
2628  * The struct declaration for register ALT_L3_SEC_USB0.
2629  */
2630 struct ALT_L3_SEC_USB0_s
2631 {
2632  uint32_t s : 1; /* USB0 Registers Security */
2633  uint32_t : 31; /* *UNDEFINED* */
2634 };
2635 
2636 /* The typedef declaration for register ALT_L3_SEC_USB0. */
2637 typedef volatile struct ALT_L3_SEC_USB0_s ALT_L3_SEC_USB0_t;
2638 #endif /* __ASSEMBLY__ */
2639 
2640 /* The byte offset of the ALT_L3_SEC_USB0 register from the beginning of the component. */
2641 #define ALT_L3_SEC_USB0_OFST 0x78
2642 
2643 /*
2644  * Register : NAND Flash Controller Registers Peripheral Security - nandregs
2645  *
2646  * Controls security settings for NAND Flash Controller Registers peripheral.
2647  *
2648  * Register Layout
2649  *
2650  * Bits | Access | Reset | Description
2651  * :-------|:-------|:------|:-----------------------------------------
2652  * [0] | W | 0x0 | NAND Flash Controller Registers Security
2653  * [31:1] | ??? | 0x0 | *UNDEFINED*
2654  *
2655  */
2656 /*
2657  * Field : NAND Flash Controller Registers Security - s
2658  *
2659  * Controls whether secure or non-secure masters can access the NAND Flash
2660  * Controller Registers slave.
2661  *
2662  * Field Enumeration Values:
2663  *
2664  * Enum | Value | Description
2665  * :------------------------------|:------|:----------------------------------------------
2666  * ALT_L3_SEC_NAND_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2667  * : | | master.
2668  * ALT_L3_SEC_NAND_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2669  * : | | non-secure masters.
2670  *
2671  * Field Access Macros:
2672  *
2673  */
2674 /*
2675  * Enumerated value for register field ALT_L3_SEC_NAND_S
2676  *
2677  * The slave can only be accessed by a secure master.
2678  */
2679 #define ALT_L3_SEC_NAND_S_E_SECURE 0x0
2680 /*
2681  * Enumerated value for register field ALT_L3_SEC_NAND_S
2682  *
2683  * The slave can only be accessed by a secure or non-secure masters.
2684  */
2685 #define ALT_L3_SEC_NAND_S_E_NONSECURE 0x1
2686 
2687 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_NAND_S register field. */
2688 #define ALT_L3_SEC_NAND_S_LSB 0
2689 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_NAND_S register field. */
2690 #define ALT_L3_SEC_NAND_S_MSB 0
2691 /* The width in bits of the ALT_L3_SEC_NAND_S register field. */
2692 #define ALT_L3_SEC_NAND_S_WIDTH 1
2693 /* The mask used to set the ALT_L3_SEC_NAND_S register field value. */
2694 #define ALT_L3_SEC_NAND_S_SET_MSK 0x00000001
2695 /* The mask used to clear the ALT_L3_SEC_NAND_S register field value. */
2696 #define ALT_L3_SEC_NAND_S_CLR_MSK 0xfffffffe
2697 /* The reset value of the ALT_L3_SEC_NAND_S register field. */
2698 #define ALT_L3_SEC_NAND_S_RESET 0x0
2699 /* Extracts the ALT_L3_SEC_NAND_S field value from a register. */
2700 #define ALT_L3_SEC_NAND_S_GET(value) (((value) & 0x00000001) >> 0)
2701 /* Produces a ALT_L3_SEC_NAND_S register field value suitable for setting the register. */
2702 #define ALT_L3_SEC_NAND_S_SET(value) (((value) << 0) & 0x00000001)
2703 
2704 #ifndef __ASSEMBLY__
2705 /*
2706  * WARNING: The C register and register group struct declarations are provided for
2707  * convenience and illustrative purposes. They should, however, be used with
2708  * caution as the C language standard provides no guarantees about the alignment or
2709  * atomicity of device memory accesses. The recommended practice for writing
2710  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2711  * alt_write_word() functions.
2712  *
2713  * The struct declaration for register ALT_L3_SEC_NAND.
2714  */
2715 struct ALT_L3_SEC_NAND_s
2716 {
2717  uint32_t s : 1; /* NAND Flash Controller Registers Security */
2718  uint32_t : 31; /* *UNDEFINED* */
2719 };
2720 
2721 /* The typedef declaration for register ALT_L3_SEC_NAND. */
2722 typedef volatile struct ALT_L3_SEC_NAND_s ALT_L3_SEC_NAND_t;
2723 #endif /* __ASSEMBLY__ */
2724 
2725 /* The byte offset of the ALT_L3_SEC_NAND register from the beginning of the component. */
2726 #define ALT_L3_SEC_NAND_OFST 0x7c
2727 
2728 /*
2729  * Register : QSPI Flash Controller Data Peripheral Security - qspidata
2730  *
2731  * Controls security settings for QSPI Flash Controller Data peripheral.
2732  *
2733  * Register Layout
2734  *
2735  * Bits | Access | Reset | Description
2736  * :-------|:-------|:------|:------------------------------------
2737  * [0] | W | 0x0 | QSPI Flash Controller Data Security
2738  * [31:1] | ??? | 0x0 | *UNDEFINED*
2739  *
2740  */
2741 /*
2742  * Field : QSPI Flash Controller Data Security - s
2743  *
2744  * Controls whether secure or non-secure masters can access the QSPI Flash
2745  * Controller Data slave.
2746  *
2747  * Field Enumeration Values:
2748  *
2749  * Enum | Value | Description
2750  * :----------------------------------|:------|:----------------------------------------------
2751  * ALT_L3_SEC_QSPIDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2752  * : | | master.
2753  * ALT_L3_SEC_QSPIDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2754  * : | | non-secure masters.
2755  *
2756  * Field Access Macros:
2757  *
2758  */
2759 /*
2760  * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
2761  *
2762  * The slave can only be accessed by a secure master.
2763  */
2764 #define ALT_L3_SEC_QSPIDATA_S_E_SECURE 0x0
2765 /*
2766  * Enumerated value for register field ALT_L3_SEC_QSPIDATA_S
2767  *
2768  * The slave can only be accessed by a secure or non-secure masters.
2769  */
2770 #define ALT_L3_SEC_QSPIDATA_S_E_NONSECURE 0x1
2771 
2772 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
2773 #define ALT_L3_SEC_QSPIDATA_S_LSB 0
2774 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_QSPIDATA_S register field. */
2775 #define ALT_L3_SEC_QSPIDATA_S_MSB 0
2776 /* The width in bits of the ALT_L3_SEC_QSPIDATA_S register field. */
2777 #define ALT_L3_SEC_QSPIDATA_S_WIDTH 1
2778 /* The mask used to set the ALT_L3_SEC_QSPIDATA_S register field value. */
2779 #define ALT_L3_SEC_QSPIDATA_S_SET_MSK 0x00000001
2780 /* The mask used to clear the ALT_L3_SEC_QSPIDATA_S register field value. */
2781 #define ALT_L3_SEC_QSPIDATA_S_CLR_MSK 0xfffffffe
2782 /* The reset value of the ALT_L3_SEC_QSPIDATA_S register field. */
2783 #define ALT_L3_SEC_QSPIDATA_S_RESET 0x0
2784 /* Extracts the ALT_L3_SEC_QSPIDATA_S field value from a register. */
2785 #define ALT_L3_SEC_QSPIDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2786 /* Produces a ALT_L3_SEC_QSPIDATA_S register field value suitable for setting the register. */
2787 #define ALT_L3_SEC_QSPIDATA_S_SET(value) (((value) << 0) & 0x00000001)
2788 
2789 #ifndef __ASSEMBLY__
2790 /*
2791  * WARNING: The C register and register group struct declarations are provided for
2792  * convenience and illustrative purposes. They should, however, be used with
2793  * caution as the C language standard provides no guarantees about the alignment or
2794  * atomicity of device memory accesses. The recommended practice for writing
2795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2796  * alt_write_word() functions.
2797  *
2798  * The struct declaration for register ALT_L3_SEC_QSPIDATA.
2799  */
2800 struct ALT_L3_SEC_QSPIDATA_s
2801 {
2802  uint32_t s : 1; /* QSPI Flash Controller Data Security */
2803  uint32_t : 31; /* *UNDEFINED* */
2804 };
2805 
2806 /* The typedef declaration for register ALT_L3_SEC_QSPIDATA. */
2807 typedef volatile struct ALT_L3_SEC_QSPIDATA_s ALT_L3_SEC_QSPIDATA_t;
2808 #endif /* __ASSEMBLY__ */
2809 
2810 /* The byte offset of the ALT_L3_SEC_QSPIDATA register from the beginning of the component. */
2811 #define ALT_L3_SEC_QSPIDATA_OFST 0x80
2812 
2813 /*
2814  * Register : FPGA Manager Data Peripheral Security - fpgamgrdata
2815  *
2816  * Controls security settings for FPGA Manager Data peripheral.
2817  *
2818  * Register Layout
2819  *
2820  * Bits | Access | Reset | Description
2821  * :-------|:-------|:------|:---------------------------
2822  * [0] | W | 0x0 | FPGA Manager Data Security
2823  * [31:1] | ??? | 0x0 | *UNDEFINED*
2824  *
2825  */
2826 /*
2827  * Field : FPGA Manager Data Security - s
2828  *
2829  * Controls whether secure or non-secure masters can access the FPGA Manager Data
2830  * slave.
2831  *
2832  * Field Enumeration Values:
2833  *
2834  * Enum | Value | Description
2835  * :-------------------------------------|:------|:----------------------------------------------
2836  * ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2837  * : | | master.
2838  * ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2839  * : | | non-secure masters.
2840  *
2841  * Field Access Macros:
2842  *
2843  */
2844 /*
2845  * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
2846  *
2847  * The slave can only be accessed by a secure master.
2848  */
2849 #define ALT_L3_SEC_FPGAMGRDATA_S_E_SECURE 0x0
2850 /*
2851  * Enumerated value for register field ALT_L3_SEC_FPGAMGRDATA_S
2852  *
2853  * The slave can only be accessed by a secure or non-secure masters.
2854  */
2855 #define ALT_L3_SEC_FPGAMGRDATA_S_E_NONSECURE 0x1
2856 
2857 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2858 #define ALT_L3_SEC_FPGAMGRDATA_S_LSB 0
2859 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2860 #define ALT_L3_SEC_FPGAMGRDATA_S_MSB 0
2861 /* The width in bits of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2862 #define ALT_L3_SEC_FPGAMGRDATA_S_WIDTH 1
2863 /* The mask used to set the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
2864 #define ALT_L3_SEC_FPGAMGRDATA_S_SET_MSK 0x00000001
2865 /* The mask used to clear the ALT_L3_SEC_FPGAMGRDATA_S register field value. */
2866 #define ALT_L3_SEC_FPGAMGRDATA_S_CLR_MSK 0xfffffffe
2867 /* The reset value of the ALT_L3_SEC_FPGAMGRDATA_S register field. */
2868 #define ALT_L3_SEC_FPGAMGRDATA_S_RESET 0x0
2869 /* Extracts the ALT_L3_SEC_FPGAMGRDATA_S field value from a register. */
2870 #define ALT_L3_SEC_FPGAMGRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
2871 /* Produces a ALT_L3_SEC_FPGAMGRDATA_S register field value suitable for setting the register. */
2872 #define ALT_L3_SEC_FPGAMGRDATA_S_SET(value) (((value) << 0) & 0x00000001)
2873 
2874 #ifndef __ASSEMBLY__
2875 /*
2876  * WARNING: The C register and register group struct declarations are provided for
2877  * convenience and illustrative purposes. They should, however, be used with
2878  * caution as the C language standard provides no guarantees about the alignment or
2879  * atomicity of device memory accesses. The recommended practice for writing
2880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2881  * alt_write_word() functions.
2882  *
2883  * The struct declaration for register ALT_L3_SEC_FPGAMGRDATA.
2884  */
2885 struct ALT_L3_SEC_FPGAMGRDATA_s
2886 {
2887  uint32_t s : 1; /* FPGA Manager Data Security */
2888  uint32_t : 31; /* *UNDEFINED* */
2889 };
2890 
2891 /* The typedef declaration for register ALT_L3_SEC_FPGAMGRDATA. */
2892 typedef volatile struct ALT_L3_SEC_FPGAMGRDATA_s ALT_L3_SEC_FPGAMGRDATA_t;
2893 #endif /* __ASSEMBLY__ */
2894 
2895 /* The byte offset of the ALT_L3_SEC_FPGAMGRDATA register from the beginning of the component. */
2896 #define ALT_L3_SEC_FPGAMGRDATA_OFST 0x84
2897 
2898 /*
2899  * Register : HPS2FPGA AXI Bridge Registers Peripheral Security - hps2fpgaregs
2900  *
2901  * Controls security settings for HPS2FPGA AXI Bridge Registers peripheral.
2902  *
2903  * Register Layout
2904  *
2905  * Bits | Access | Reset | Description
2906  * :-------|:-------|:------|:---------------------------------------
2907  * [0] | W | 0x0 | HPS2FPGA AXI Bridge Registers Security
2908  * [31:1] | ??? | 0x0 | *UNDEFINED*
2909  *
2910  */
2911 /*
2912  * Field : HPS2FPGA AXI Bridge Registers Security - s
2913  *
2914  * Controls whether secure or non-secure masters can access the HPS2FPGA AXI Bridge
2915  * Registers slave.
2916  *
2917  * Field Enumeration Values:
2918  *
2919  * Enum | Value | Description
2920  * :-----------------------------|:------|:----------------------------------------------
2921  * ALT_L3_SEC_H2F_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
2922  * : | | master.
2923  * ALT_L3_SEC_H2F_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
2924  * : | | non-secure masters.
2925  *
2926  * Field Access Macros:
2927  *
2928  */
2929 /*
2930  * Enumerated value for register field ALT_L3_SEC_H2F_S
2931  *
2932  * The slave can only be accessed by a secure master.
2933  */
2934 #define ALT_L3_SEC_H2F_S_E_SECURE 0x0
2935 /*
2936  * Enumerated value for register field ALT_L3_SEC_H2F_S
2937  *
2938  * The slave can only be accessed by a secure or non-secure masters.
2939  */
2940 #define ALT_L3_SEC_H2F_S_E_NONSECURE 0x1
2941 
2942 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_H2F_S register field. */
2943 #define ALT_L3_SEC_H2F_S_LSB 0
2944 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_H2F_S register field. */
2945 #define ALT_L3_SEC_H2F_S_MSB 0
2946 /* The width in bits of the ALT_L3_SEC_H2F_S register field. */
2947 #define ALT_L3_SEC_H2F_S_WIDTH 1
2948 /* The mask used to set the ALT_L3_SEC_H2F_S register field value. */
2949 #define ALT_L3_SEC_H2F_S_SET_MSK 0x00000001
2950 /* The mask used to clear the ALT_L3_SEC_H2F_S register field value. */
2951 #define ALT_L3_SEC_H2F_S_CLR_MSK 0xfffffffe
2952 /* The reset value of the ALT_L3_SEC_H2F_S register field. */
2953 #define ALT_L3_SEC_H2F_S_RESET 0x0
2954 /* Extracts the ALT_L3_SEC_H2F_S field value from a register. */
2955 #define ALT_L3_SEC_H2F_S_GET(value) (((value) & 0x00000001) >> 0)
2956 /* Produces a ALT_L3_SEC_H2F_S register field value suitable for setting the register. */
2957 #define ALT_L3_SEC_H2F_S_SET(value) (((value) << 0) & 0x00000001)
2958 
2959 #ifndef __ASSEMBLY__
2960 /*
2961  * WARNING: The C register and register group struct declarations are provided for
2962  * convenience and illustrative purposes. They should, however, be used with
2963  * caution as the C language standard provides no guarantees about the alignment or
2964  * atomicity of device memory accesses. The recommended practice for writing
2965  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2966  * alt_write_word() functions.
2967  *
2968  * The struct declaration for register ALT_L3_SEC_H2F.
2969  */
2970 struct ALT_L3_SEC_H2F_s
2971 {
2972  uint32_t s : 1; /* HPS2FPGA AXI Bridge Registers Security */
2973  uint32_t : 31; /* *UNDEFINED* */
2974 };
2975 
2976 /* The typedef declaration for register ALT_L3_SEC_H2F. */
2977 typedef volatile struct ALT_L3_SEC_H2F_s ALT_L3_SEC_H2F_t;
2978 #endif /* __ASSEMBLY__ */
2979 
2980 /* The byte offset of the ALT_L3_SEC_H2F register from the beginning of the component. */
2981 #define ALT_L3_SEC_H2F_OFST 0x88
2982 
2983 /*
2984  * Register : MPU ACP Peripheral Security - acp
2985  *
2986  * Controls security settings for MPU ACP peripheral.
2987  *
2988  * Register Layout
2989  *
2990  * Bits | Access | Reset | Description
2991  * :-------|:-------|:------|:-----------------
2992  * [0] | W | 0x0 | MPU ACP Security
2993  * [31:1] | ??? | 0x0 | *UNDEFINED*
2994  *
2995  */
2996 /*
2997  * Field : MPU ACP Security - s
2998  *
2999  * Controls whether secure or non-secure masters can access the MPU ACP slave.
3000  *
3001  * Field Enumeration Values:
3002  *
3003  * Enum | Value | Description
3004  * :-----------------------------|:------|:----------------------------------------------
3005  * ALT_L3_SEC_ACP_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3006  * : | | master.
3007  * ALT_L3_SEC_ACP_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3008  * : | | non-secure masters.
3009  *
3010  * Field Access Macros:
3011  *
3012  */
3013 /*
3014  * Enumerated value for register field ALT_L3_SEC_ACP_S
3015  *
3016  * The slave can only be accessed by a secure master.
3017  */
3018 #define ALT_L3_SEC_ACP_S_E_SECURE 0x0
3019 /*
3020  * Enumerated value for register field ALT_L3_SEC_ACP_S
3021  *
3022  * The slave can only be accessed by a secure or non-secure masters.
3023  */
3024 #define ALT_L3_SEC_ACP_S_E_NONSECURE 0x1
3025 
3026 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ACP_S register field. */
3027 #define ALT_L3_SEC_ACP_S_LSB 0
3028 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ACP_S register field. */
3029 #define ALT_L3_SEC_ACP_S_MSB 0
3030 /* The width in bits of the ALT_L3_SEC_ACP_S register field. */
3031 #define ALT_L3_SEC_ACP_S_WIDTH 1
3032 /* The mask used to set the ALT_L3_SEC_ACP_S register field value. */
3033 #define ALT_L3_SEC_ACP_S_SET_MSK 0x00000001
3034 /* The mask used to clear the ALT_L3_SEC_ACP_S register field value. */
3035 #define ALT_L3_SEC_ACP_S_CLR_MSK 0xfffffffe
3036 /* The reset value of the ALT_L3_SEC_ACP_S register field. */
3037 #define ALT_L3_SEC_ACP_S_RESET 0x0
3038 /* Extracts the ALT_L3_SEC_ACP_S field value from a register. */
3039 #define ALT_L3_SEC_ACP_S_GET(value) (((value) & 0x00000001) >> 0)
3040 /* Produces a ALT_L3_SEC_ACP_S register field value suitable for setting the register. */
3041 #define ALT_L3_SEC_ACP_S_SET(value) (((value) << 0) & 0x00000001)
3042 
3043 #ifndef __ASSEMBLY__
3044 /*
3045  * WARNING: The C register and register group struct declarations are provided for
3046  * convenience and illustrative purposes. They should, however, be used with
3047  * caution as the C language standard provides no guarantees about the alignment or
3048  * atomicity of device memory accesses. The recommended practice for writing
3049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3050  * alt_write_word() functions.
3051  *
3052  * The struct declaration for register ALT_L3_SEC_ACP.
3053  */
3054 struct ALT_L3_SEC_ACP_s
3055 {
3056  uint32_t s : 1; /* MPU ACP Security */
3057  uint32_t : 31; /* *UNDEFINED* */
3058 };
3059 
3060 /* The typedef declaration for register ALT_L3_SEC_ACP. */
3061 typedef volatile struct ALT_L3_SEC_ACP_s ALT_L3_SEC_ACP_t;
3062 #endif /* __ASSEMBLY__ */
3063 
3064 /* The byte offset of the ALT_L3_SEC_ACP register from the beginning of the component. */
3065 #define ALT_L3_SEC_ACP_OFST 0x8c
3066 
3067 /*
3068  * Register : ROM Peripheral Security - rom
3069  *
3070  * Controls security settings for ROM peripheral.
3071  *
3072  * Register Layout
3073  *
3074  * Bits | Access | Reset | Description
3075  * :-------|:-------|:------|:-------------
3076  * [0] | W | 0x0 | ROM Security
3077  * [31:1] | ??? | 0x0 | *UNDEFINED*
3078  *
3079  */
3080 /*
3081  * Field : ROM Security - s
3082  *
3083  * Controls whether secure or non-secure masters can access the ROM slave.
3084  *
3085  * Field Enumeration Values:
3086  *
3087  * Enum | Value | Description
3088  * :-----------------------------|:------|:----------------------------------------------
3089  * ALT_L3_SEC_ROM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3090  * : | | master.
3091  * ALT_L3_SEC_ROM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3092  * : | | non-secure masters.
3093  *
3094  * Field Access Macros:
3095  *
3096  */
3097 /*
3098  * Enumerated value for register field ALT_L3_SEC_ROM_S
3099  *
3100  * The slave can only be accessed by a secure master.
3101  */
3102 #define ALT_L3_SEC_ROM_S_E_SECURE 0x0
3103 /*
3104  * Enumerated value for register field ALT_L3_SEC_ROM_S
3105  *
3106  * The slave can only be accessed by a secure or non-secure masters.
3107  */
3108 #define ALT_L3_SEC_ROM_S_E_NONSECURE 0x1
3109 
3110 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_ROM_S register field. */
3111 #define ALT_L3_SEC_ROM_S_LSB 0
3112 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_ROM_S register field. */
3113 #define ALT_L3_SEC_ROM_S_MSB 0
3114 /* The width in bits of the ALT_L3_SEC_ROM_S register field. */
3115 #define ALT_L3_SEC_ROM_S_WIDTH 1
3116 /* The mask used to set the ALT_L3_SEC_ROM_S register field value. */
3117 #define ALT_L3_SEC_ROM_S_SET_MSK 0x00000001
3118 /* The mask used to clear the ALT_L3_SEC_ROM_S register field value. */
3119 #define ALT_L3_SEC_ROM_S_CLR_MSK 0xfffffffe
3120 /* The reset value of the ALT_L3_SEC_ROM_S register field. */
3121 #define ALT_L3_SEC_ROM_S_RESET 0x0
3122 /* Extracts the ALT_L3_SEC_ROM_S field value from a register. */
3123 #define ALT_L3_SEC_ROM_S_GET(value) (((value) & 0x00000001) >> 0)
3124 /* Produces a ALT_L3_SEC_ROM_S register field value suitable for setting the register. */
3125 #define ALT_L3_SEC_ROM_S_SET(value) (((value) << 0) & 0x00000001)
3126 
3127 #ifndef __ASSEMBLY__
3128 /*
3129  * WARNING: The C register and register group struct declarations are provided for
3130  * convenience and illustrative purposes. They should, however, be used with
3131  * caution as the C language standard provides no guarantees about the alignment or
3132  * atomicity of device memory accesses. The recommended practice for writing
3133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3134  * alt_write_word() functions.
3135  *
3136  * The struct declaration for register ALT_L3_SEC_ROM.
3137  */
3138 struct ALT_L3_SEC_ROM_s
3139 {
3140  uint32_t s : 1; /* ROM Security */
3141  uint32_t : 31; /* *UNDEFINED* */
3142 };
3143 
3144 /* The typedef declaration for register ALT_L3_SEC_ROM. */
3145 typedef volatile struct ALT_L3_SEC_ROM_s ALT_L3_SEC_ROM_t;
3146 #endif /* __ASSEMBLY__ */
3147 
3148 /* The byte offset of the ALT_L3_SEC_ROM register from the beginning of the component. */
3149 #define ALT_L3_SEC_ROM_OFST 0x90
3150 
3151 /*
3152  * Register : On-chip RAM Peripheral Security - ocram
3153  *
3154  * Controls security settings for On-chip RAM peripheral.
3155  *
3156  * Register Layout
3157  *
3158  * Bits | Access | Reset | Description
3159  * :-------|:-------|:------|:---------------------
3160  * [0] | W | 0x0 | On-chip RAM Security
3161  * [31:1] | ??? | 0x0 | *UNDEFINED*
3162  *
3163  */
3164 /*
3165  * Field : On-chip RAM Security - s
3166  *
3167  * Controls whether secure or non-secure masters can access the On-chip RAM slave.
3168  *
3169  * Field Enumeration Values:
3170  *
3171  * Enum | Value | Description
3172  * :-------------------------------|:------|:----------------------------------------------
3173  * ALT_L3_SEC_OCRAM_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3174  * : | | master.
3175  * ALT_L3_SEC_OCRAM_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3176  * : | | non-secure masters.
3177  *
3178  * Field Access Macros:
3179  *
3180  */
3181 /*
3182  * Enumerated value for register field ALT_L3_SEC_OCRAM_S
3183  *
3184  * The slave can only be accessed by a secure master.
3185  */
3186 #define ALT_L3_SEC_OCRAM_S_E_SECURE 0x0
3187 /*
3188  * Enumerated value for register field ALT_L3_SEC_OCRAM_S
3189  *
3190  * The slave can only be accessed by a secure or non-secure masters.
3191  */
3192 #define ALT_L3_SEC_OCRAM_S_E_NONSECURE 0x1
3193 
3194 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_OCRAM_S register field. */
3195 #define ALT_L3_SEC_OCRAM_S_LSB 0
3196 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_OCRAM_S register field. */
3197 #define ALT_L3_SEC_OCRAM_S_MSB 0
3198 /* The width in bits of the ALT_L3_SEC_OCRAM_S register field. */
3199 #define ALT_L3_SEC_OCRAM_S_WIDTH 1
3200 /* The mask used to set the ALT_L3_SEC_OCRAM_S register field value. */
3201 #define ALT_L3_SEC_OCRAM_S_SET_MSK 0x00000001
3202 /* The mask used to clear the ALT_L3_SEC_OCRAM_S register field value. */
3203 #define ALT_L3_SEC_OCRAM_S_CLR_MSK 0xfffffffe
3204 /* The reset value of the ALT_L3_SEC_OCRAM_S register field. */
3205 #define ALT_L3_SEC_OCRAM_S_RESET 0x0
3206 /* Extracts the ALT_L3_SEC_OCRAM_S field value from a register. */
3207 #define ALT_L3_SEC_OCRAM_S_GET(value) (((value) & 0x00000001) >> 0)
3208 /* Produces a ALT_L3_SEC_OCRAM_S register field value suitable for setting the register. */
3209 #define ALT_L3_SEC_OCRAM_S_SET(value) (((value) << 0) & 0x00000001)
3210 
3211 #ifndef __ASSEMBLY__
3212 /*
3213  * WARNING: The C register and register group struct declarations are provided for
3214  * convenience and illustrative purposes. They should, however, be used with
3215  * caution as the C language standard provides no guarantees about the alignment or
3216  * atomicity of device memory accesses. The recommended practice for writing
3217  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3218  * alt_write_word() functions.
3219  *
3220  * The struct declaration for register ALT_L3_SEC_OCRAM.
3221  */
3222 struct ALT_L3_SEC_OCRAM_s
3223 {
3224  uint32_t s : 1; /* On-chip RAM Security */
3225  uint32_t : 31; /* *UNDEFINED* */
3226 };
3227 
3228 /* The typedef declaration for register ALT_L3_SEC_OCRAM. */
3229 typedef volatile struct ALT_L3_SEC_OCRAM_s ALT_L3_SEC_OCRAM_t;
3230 #endif /* __ASSEMBLY__ */
3231 
3232 /* The byte offset of the ALT_L3_SEC_OCRAM register from the beginning of the component. */
3233 #define ALT_L3_SEC_OCRAM_OFST 0x94
3234 
3235 /*
3236  * Register : SDRAM Data Peripheral Security - sdrdata
3237  *
3238  * Controls security settings for SDRAM Data peripheral.
3239  *
3240  * Register Layout
3241  *
3242  * Bits | Access | Reset | Description
3243  * :-------|:-------|:------|:--------------------
3244  * [0] | W | 0x0 | SDRAM Data Security
3245  * [31:1] | ??? | 0x0 | *UNDEFINED*
3246  *
3247  */
3248 /*
3249  * Field : SDRAM Data Security - s
3250  *
3251  * Controls whether secure or non-secure masters can access the SDRAM Data slave.
3252  *
3253  * Field Enumeration Values:
3254  *
3255  * Enum | Value | Description
3256  * :---------------------------------|:------|:----------------------------------------------
3257  * ALT_L3_SEC_SDRDATA_S_E_SECURE | 0x0 | The slave can only be accessed by a secure
3258  * : | | master.
3259  * ALT_L3_SEC_SDRDATA_S_E_NONSECURE | 0x1 | The slave can only be accessed by a secure or
3260  * : | | non-secure masters.
3261  *
3262  * Field Access Macros:
3263  *
3264  */
3265 /*
3266  * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
3267  *
3268  * The slave can only be accessed by a secure master.
3269  */
3270 #define ALT_L3_SEC_SDRDATA_S_E_SECURE 0x0
3271 /*
3272  * Enumerated value for register field ALT_L3_SEC_SDRDATA_S
3273  *
3274  * The slave can only be accessed by a secure or non-secure masters.
3275  */
3276 #define ALT_L3_SEC_SDRDATA_S_E_NONSECURE 0x1
3277 
3278 /* The Least Significant Bit (LSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
3279 #define ALT_L3_SEC_SDRDATA_S_LSB 0
3280 /* The Most Significant Bit (MSB) position of the ALT_L3_SEC_SDRDATA_S register field. */
3281 #define ALT_L3_SEC_SDRDATA_S_MSB 0
3282 /* The width in bits of the ALT_L3_SEC_SDRDATA_S register field. */
3283 #define ALT_L3_SEC_SDRDATA_S_WIDTH 1
3284 /* The mask used to set the ALT_L3_SEC_SDRDATA_S register field value. */
3285 #define ALT_L3_SEC_SDRDATA_S_SET_MSK 0x00000001
3286 /* The mask used to clear the ALT_L3_SEC_SDRDATA_S register field value. */
3287 #define ALT_L3_SEC_SDRDATA_S_CLR_MSK 0xfffffffe
3288 /* The reset value of the ALT_L3_SEC_SDRDATA_S register field. */
3289 #define ALT_L3_SEC_SDRDATA_S_RESET 0x0
3290 /* Extracts the ALT_L3_SEC_SDRDATA_S field value from a register. */
3291 #define ALT_L3_SEC_SDRDATA_S_GET(value) (((value) & 0x00000001) >> 0)
3292 /* Produces a ALT_L3_SEC_SDRDATA_S register field value suitable for setting the register. */
3293 #define ALT_L3_SEC_SDRDATA_S_SET(value) (((value) << 0) & 0x00000001)
3294 
3295 #ifndef __ASSEMBLY__
3296 /*
3297  * WARNING: The C register and register group struct declarations are provided for
3298  * convenience and illustrative purposes. They should, however, be used with
3299  * caution as the C language standard provides no guarantees about the alignment or
3300  * atomicity of device memory accesses. The recommended practice for writing
3301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3302  * alt_write_word() functions.
3303  *
3304  * The struct declaration for register ALT_L3_SEC_SDRDATA.
3305  */
3306 struct ALT_L3_SEC_SDRDATA_s
3307 {
3308  uint32_t s : 1; /* SDRAM Data Security */
3309  uint32_t : 31; /* *UNDEFINED* */
3310 };
3311 
3312 /* The typedef declaration for register ALT_L3_SEC_SDRDATA. */
3313 typedef volatile struct ALT_L3_SEC_SDRDATA_s ALT_L3_SEC_SDRDATA_t;
3314 #endif /* __ASSEMBLY__ */
3315 
3316 /* The byte offset of the ALT_L3_SEC_SDRDATA register from the beginning of the component. */
3317 #define ALT_L3_SEC_SDRDATA_OFST 0x98
3318 
3319 #ifndef __ASSEMBLY__
3320 /*
3321  * WARNING: The C register and register group struct declarations are provided for
3322  * convenience and illustrative purposes. They should, however, be used with
3323  * caution as the C language standard provides no guarantees about the alignment or
3324  * atomicity of device memory accesses. The recommended practice for writing
3325  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3326  * alt_write_word() functions.
3327  *
3328  * The struct declaration for register group ALT_L3_SECGRP.
3329  */
3330 struct ALT_L3_SECGRP_s
3331 {
3332  ALT_L3_SEC_L4MAIN_t l4main; /* ALT_L3_SEC_L4MAIN */
3333  ALT_L3_SEC_L4SP_t l4sp; /* ALT_L3_SEC_L4SP */
3334  ALT_L3_SEC_L4MP_t l4mp; /* ALT_L3_SEC_L4MP */
3335  ALT_L3_SEC_L4OSC1_t l4osc1; /* ALT_L3_SEC_L4OSC1 */
3336  ALT_L3_SEC_L4SPIM_t l4spim; /* ALT_L3_SEC_L4SPIM */
3337  ALT_L3_SEC_STM_t stm; /* ALT_L3_SEC_STM */
3338  ALT_L3_SEC_LWH2F_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */
3339  volatile uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */
3340  ALT_L3_SEC_USB1_t usb1; /* ALT_L3_SEC_USB1 */
3341  ALT_L3_SEC_NANDDATA_t nanddata; /* ALT_L3_SEC_NANDDATA */
3342  volatile uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */
3343  ALT_L3_SEC_USB0_t usb0; /* ALT_L3_SEC_USB0 */
3344  ALT_L3_SEC_NAND_t nandregs; /* ALT_L3_SEC_NAND */
3345  ALT_L3_SEC_QSPIDATA_t qspidata; /* ALT_L3_SEC_QSPIDATA */
3346  ALT_L3_SEC_FPGAMGRDATA_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */
3347  ALT_L3_SEC_H2F_t hps2fpgaregs; /* ALT_L3_SEC_H2F */
3348  ALT_L3_SEC_ACP_t acp; /* ALT_L3_SEC_ACP */
3349  ALT_L3_SEC_ROM_t rom; /* ALT_L3_SEC_ROM */
3350  ALT_L3_SEC_OCRAM_t ocram; /* ALT_L3_SEC_OCRAM */
3351  ALT_L3_SEC_SDRDATA_t sdrdata; /* ALT_L3_SEC_SDRDATA */
3352 };
3353 
3354 /* The typedef declaration for register group ALT_L3_SECGRP. */
3355 typedef volatile struct ALT_L3_SECGRP_s ALT_L3_SECGRP_t;
3356 /* The struct declaration for the raw register contents of register group ALT_L3_SECGRP. */
3357 struct ALT_L3_SECGRP_raw_s
3358 {
3359  volatile uint32_t l4main; /* ALT_L3_SEC_L4MAIN */
3360  volatile uint32_t l4sp; /* ALT_L3_SEC_L4SP */
3361  volatile uint32_t l4mp; /* ALT_L3_SEC_L4MP */
3362  volatile uint32_t l4osc1; /* ALT_L3_SEC_L4OSC1 */
3363  volatile uint32_t l4spim; /* ALT_L3_SEC_L4SPIM */
3364  volatile uint32_t stm; /* ALT_L3_SEC_STM */
3365  volatile uint32_t lwhps2fpgaregs; /* ALT_L3_SEC_LWH2F */
3366  uint32_t _pad_0x1c_0x1f; /* *UNDEFINED* */
3367  volatile uint32_t usb1; /* ALT_L3_SEC_USB1 */
3368  volatile uint32_t nanddata; /* ALT_L3_SEC_NANDDATA */
3369  uint32_t _pad_0x28_0x77[20]; /* *UNDEFINED* */
3370  volatile uint32_t usb0; /* ALT_L3_SEC_USB0 */
3371  volatile uint32_t nandregs; /* ALT_L3_SEC_NAND */
3372  volatile uint32_t qspidata; /* ALT_L3_SEC_QSPIDATA */
3373  volatile uint32_t fpgamgrdata; /* ALT_L3_SEC_FPGAMGRDATA */
3374  volatile uint32_t hps2fpgaregs; /* ALT_L3_SEC_H2F */
3375  volatile uint32_t acp; /* ALT_L3_SEC_ACP */
3376  volatile uint32_t rom; /* ALT_L3_SEC_ROM */
3377  volatile uint32_t ocram; /* ALT_L3_SEC_OCRAM */
3378  volatile uint32_t sdrdata; /* ALT_L3_SEC_SDRDATA */
3379 };
3380 
3381 /* The typedef declaration for the raw register contents of register group ALT_L3_SECGRP. */
3382 typedef volatile struct ALT_L3_SECGRP_raw_s ALT_L3_SECGRP_raw_t;
3383 #endif /* __ASSEMBLY__ */
3384 
3385 
3386 /*
3387  * Register Group : ID Register Group - ALT_L3_IDGRP
3388  * ID Register Group
3389  *
3390  * Contains registers that identify the ARM NIC-301 IP Core.
3391  *
3392  */
3393 /*
3394  * Register : Peripheral ID4 Register - periph_id_4
3395  *
3396  * JEP106 continuation code
3397  *
3398  * Register Layout
3399  *
3400  * Bits | Access | Reset | Description
3401  * :-------|:-------|:------|:---------------
3402  * [7:0] | R | 0x4 | Peripheral ID4
3403  * [31:8] | ??? | 0x0 | *UNDEFINED*
3404  *
3405  */
3406 /*
3407  * Field : Peripheral ID4 - periph_id_4
3408  *
3409  * JEP106 continuation code
3410  *
3411  * Field Access Macros:
3412  *
3413  */
3414 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3415 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0
3416 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3417 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7
3418 /* The width in bits of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3419 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8
3420 /* The mask used to set the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
3421 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff
3422 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
3423 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00
3424 /* The reset value of the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
3425 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4
3426 /* Extracts the ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */
3427 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0)
3428 /* Produces a ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */
3429 #define ALT_L3_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff)
3430 
3431 #ifndef __ASSEMBLY__
3432 /*
3433  * WARNING: The C register and register group struct declarations are provided for
3434  * convenience and illustrative purposes. They should, however, be used with
3435  * caution as the C language standard provides no guarantees about the alignment or
3436  * atomicity of device memory accesses. The recommended practice for writing
3437  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3438  * alt_write_word() functions.
3439  *
3440  * The struct declaration for register ALT_L3_ID_PERIPH_ID_4.
3441  */
3442 struct ALT_L3_ID_PERIPH_ID_4_s
3443 {
3444  const uint32_t periph_id_4 : 8; /* Peripheral ID4 */
3445  uint32_t : 24; /* *UNDEFINED* */
3446 };
3447 
3448 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_4. */
3449 typedef volatile struct ALT_L3_ID_PERIPH_ID_4_s ALT_L3_ID_PERIPH_ID_4_t;
3450 #endif /* __ASSEMBLY__ */
3451 
3452 /* The byte offset of the ALT_L3_ID_PERIPH_ID_4 register from the beginning of the component. */
3453 #define ALT_L3_ID_PERIPH_ID_4_OFST 0xfd0
3454 
3455 /*
3456  * Register : Peripheral ID0 Register - periph_id_0
3457  *
3458  * Peripheral ID0
3459  *
3460  * Register Layout
3461  *
3462  * Bits | Access | Reset | Description
3463  * :-------|:-------|:------|:------------------
3464  * [7:0] | R | 0x1 | Part Number [7:0]
3465  * [31:8] | ??? | 0x0 | *UNDEFINED*
3466  *
3467  */
3468 /*
3469  * Field : Part Number [7:0] - pn7to0
3470  *
3471  * Part Number [7:0]
3472  *
3473  * Field Access Macros:
3474  *
3475  */
3476 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3477 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_LSB 0
3478 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3479 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_MSB 7
3480 /* The width in bits of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3481 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_WIDTH 8
3482 /* The mask used to set the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
3483 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff
3484 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value. */
3485 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00
3486 /* The reset value of the ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field. */
3487 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_RESET 0x1
3488 /* Extracts the ALT_L3_ID_PERIPH_ID_0_PN7TO0 field value from a register. */
3489 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0)
3490 /* Produces a ALT_L3_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */
3491 #define ALT_L3_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff)
3492 
3493 #ifndef __ASSEMBLY__
3494 /*
3495  * WARNING: The C register and register group struct declarations are provided for
3496  * convenience and illustrative purposes. They should, however, be used with
3497  * caution as the C language standard provides no guarantees about the alignment or
3498  * atomicity of device memory accesses. The recommended practice for writing
3499  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3500  * alt_write_word() functions.
3501  *
3502  * The struct declaration for register ALT_L3_ID_PERIPH_ID_0.
3503  */
3504 struct ALT_L3_ID_PERIPH_ID_0_s
3505 {
3506  const uint32_t pn7to0 : 8; /* Part Number [7:0] */
3507  uint32_t : 24; /* *UNDEFINED* */
3508 };
3509 
3510 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_0. */
3511 typedef volatile struct ALT_L3_ID_PERIPH_ID_0_s ALT_L3_ID_PERIPH_ID_0_t;
3512 #endif /* __ASSEMBLY__ */
3513 
3514 /* The byte offset of the ALT_L3_ID_PERIPH_ID_0 register from the beginning of the component. */
3515 #define ALT_L3_ID_PERIPH_ID_0_OFST 0xfe0
3516 
3517 /*
3518  * Register : Peripheral ID1 Register - periph_id_1
3519  *
3520  * Peripheral ID1
3521  *
3522  * Register Layout
3523  *
3524  * Bits | Access | Reset | Description
3525  * :-------|:-------|:------|:--------------------------------
3526  * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8]
3527  * [31:8] | ??? | 0x0 | *UNDEFINED*
3528  *
3529  */
3530 /*
3531  * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8
3532  *
3533  * JEP106[3:0], Part Number [11:8]
3534  *
3535  * Field Access Macros:
3536  *
3537  */
3538 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3539 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0
3540 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3541 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7
3542 /* The width in bits of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3543 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8
3544 /* The mask used to set the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
3545 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff
3546 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
3547 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00
3548 /* The reset value of the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
3549 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3
3550 /* Extracts the ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */
3551 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0)
3552 /* Produces a ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */
3553 #define ALT_L3_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff)
3554 
3555 #ifndef __ASSEMBLY__
3556 /*
3557  * WARNING: The C register and register group struct declarations are provided for
3558  * convenience and illustrative purposes. They should, however, be used with
3559  * caution as the C language standard provides no guarantees about the alignment or
3560  * atomicity of device memory accesses. The recommended practice for writing
3561  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3562  * alt_write_word() functions.
3563  *
3564  * The struct declaration for register ALT_L3_ID_PERIPH_ID_1.
3565  */
3566 struct ALT_L3_ID_PERIPH_ID_1_s
3567 {
3568  const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */
3569  uint32_t : 24; /* *UNDEFINED* */
3570 };
3571 
3572 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_1. */
3573 typedef volatile struct ALT_L3_ID_PERIPH_ID_1_s ALT_L3_ID_PERIPH_ID_1_t;
3574 #endif /* __ASSEMBLY__ */
3575 
3576 /* The byte offset of the ALT_L3_ID_PERIPH_ID_1 register from the beginning of the component. */
3577 #define ALT_L3_ID_PERIPH_ID_1_OFST 0xfe4
3578 
3579 /*
3580  * Register : Peripheral ID2 Register - periph_id_2
3581  *
3582  * Peripheral ID2
3583  *
3584  * Register Layout
3585  *
3586  * Bits | Access | Reset | Description
3587  * :-------|:-------|:------|:----------------------------------------
3588  * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4]
3589  * [31:8] | ??? | 0x0 | *UNDEFINED*
3590  *
3591  */
3592 /*
3593  * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4
3594  *
3595  * Revision, JEP106 code flag, JEP106[6:4]
3596  *
3597  * Field Access Macros:
3598  *
3599  */
3600 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3601 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0
3602 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3603 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7
3604 /* The width in bits of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3605 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8
3606 /* The mask used to set the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
3607 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff
3608 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
3609 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00
3610 /* The reset value of the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
3611 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b
3612 /* Extracts the ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */
3613 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0)
3614 /* Produces a ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */
3615 #define ALT_L3_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff)
3616 
3617 #ifndef __ASSEMBLY__
3618 /*
3619  * WARNING: The C register and register group struct declarations are provided for
3620  * convenience and illustrative purposes. They should, however, be used with
3621  * caution as the C language standard provides no guarantees about the alignment or
3622  * atomicity of device memory accesses. The recommended practice for writing
3623  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3624  * alt_write_word() functions.
3625  *
3626  * The struct declaration for register ALT_L3_ID_PERIPH_ID_2.
3627  */
3628 struct ALT_L3_ID_PERIPH_ID_2_s
3629 {
3630  const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */
3631  uint32_t : 24; /* *UNDEFINED* */
3632 };
3633 
3634 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_2. */
3635 typedef volatile struct ALT_L3_ID_PERIPH_ID_2_s ALT_L3_ID_PERIPH_ID_2_t;
3636 #endif /* __ASSEMBLY__ */
3637 
3638 /* The byte offset of the ALT_L3_ID_PERIPH_ID_2 register from the beginning of the component. */
3639 #define ALT_L3_ID_PERIPH_ID_2_OFST 0xfe8
3640 
3641 /*
3642  * Register : Peripheral ID3 Register - periph_id_3
3643  *
3644  * Peripheral ID3
3645  *
3646  * Register Layout
3647  *
3648  * Bits | Access | Reset | Description
3649  * :-------|:-------|:------|:----------------------
3650  * [3:0] | R | 0x0 | Customer Model Number
3651  * [7:4] | R | 0x0 | Revision
3652  * [31:8] | ??? | 0x0 | *UNDEFINED*
3653  *
3654  */
3655 /*
3656  * Field : Customer Model Number - cust_mod_num
3657  *
3658  * Customer Model Number
3659  *
3660  * Field Access Macros:
3661  *
3662  */
3663 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3664 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0
3665 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3666 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3
3667 /* The width in bits of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3668 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4
3669 /* The mask used to set the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
3670 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f
3671 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
3672 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0
3673 /* The reset value of the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
3674 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0
3675 /* Extracts the ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */
3676 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0)
3677 /* Produces a ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */
3678 #define ALT_L3_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f)
3679 
3680 /*
3681  * Field : Revision - rev_and
3682  *
3683  * Revision
3684  *
3685  * Field Access Macros:
3686  *
3687  */
3688 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3689 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_LSB 4
3690 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3691 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_MSB 7
3692 /* The width in bits of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3693 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_WIDTH 4
3694 /* The mask used to set the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
3695 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0
3696 /* The mask used to clear the ALT_L3_ID_PERIPH_ID_3_REV_AND register field value. */
3697 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f
3698 /* The reset value of the ALT_L3_ID_PERIPH_ID_3_REV_AND register field. */
3699 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_RESET 0x0
3700 /* Extracts the ALT_L3_ID_PERIPH_ID_3_REV_AND field value from a register. */
3701 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4)
3702 /* Produces a ALT_L3_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */
3703 #define ALT_L3_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0)
3704 
3705 #ifndef __ASSEMBLY__
3706 /*
3707  * WARNING: The C register and register group struct declarations are provided for
3708  * convenience and illustrative purposes. They should, however, be used with
3709  * caution as the C language standard provides no guarantees about the alignment or
3710  * atomicity of device memory accesses. The recommended practice for writing
3711  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3712  * alt_write_word() functions.
3713  *
3714  * The struct declaration for register ALT_L3_ID_PERIPH_ID_3.
3715  */
3716 struct ALT_L3_ID_PERIPH_ID_3_s
3717 {
3718  const uint32_t cust_mod_num : 4; /* Customer Model Number */
3719  const uint32_t rev_and : 4; /* Revision */
3720  uint32_t : 24; /* *UNDEFINED* */
3721 };
3722 
3723 /* The typedef declaration for register ALT_L3_ID_PERIPH_ID_3. */
3724 typedef volatile struct ALT_L3_ID_PERIPH_ID_3_s ALT_L3_ID_PERIPH_ID_3_t;
3725 #endif /* __ASSEMBLY__ */
3726 
3727 /* The byte offset of the ALT_L3_ID_PERIPH_ID_3 register from the beginning of the component. */
3728 #define ALT_L3_ID_PERIPH_ID_3_OFST 0xfec
3729 
3730 /*
3731  * Register : Component ID0 Register - comp_id_0
3732  *
3733  * Component ID0
3734  *
3735  * Register Layout
3736  *
3737  * Bits | Access | Reset | Description
3738  * :-------|:-------|:------|:------------
3739  * [7:0] | R | 0xd | Preamble
3740  * [31:8] | ??? | 0x0 | *UNDEFINED*
3741  *
3742  */
3743 /*
3744  * Field : Preamble - preamble
3745  *
3746  * Preamble
3747  *
3748  * Field Access Macros:
3749  *
3750  */
3751 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3752 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_LSB 0
3753 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3754 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_MSB 7
3755 /* The width in bits of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3756 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_WIDTH 8
3757 /* The mask used to set the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
3758 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff
3759 /* The mask used to clear the ALT_L3_ID_COMP_ID_0_PREAMBLE register field value. */
3760 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00
3761 /* The reset value of the ALT_L3_ID_COMP_ID_0_PREAMBLE register field. */
3762 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_RESET 0xd
3763 /* Extracts the ALT_L3_ID_COMP_ID_0_PREAMBLE field value from a register. */
3764 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3765 /* Produces a ALT_L3_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */
3766 #define ALT_L3_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3767 
3768 #ifndef __ASSEMBLY__
3769 /*
3770  * WARNING: The C register and register group struct declarations are provided for
3771  * convenience and illustrative purposes. They should, however, be used with
3772  * caution as the C language standard provides no guarantees about the alignment or
3773  * atomicity of device memory accesses. The recommended practice for writing
3774  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3775  * alt_write_word() functions.
3776  *
3777  * The struct declaration for register ALT_L3_ID_COMP_ID_0.
3778  */
3779 struct ALT_L3_ID_COMP_ID_0_s
3780 {
3781  const uint32_t preamble : 8; /* Preamble */
3782  uint32_t : 24; /* *UNDEFINED* */
3783 };
3784 
3785 /* The typedef declaration for register ALT_L3_ID_COMP_ID_0. */
3786 typedef volatile struct ALT_L3_ID_COMP_ID_0_s ALT_L3_ID_COMP_ID_0_t;
3787 #endif /* __ASSEMBLY__ */
3788 
3789 /* The byte offset of the ALT_L3_ID_COMP_ID_0 register from the beginning of the component. */
3790 #define ALT_L3_ID_COMP_ID_0_OFST 0xff0
3791 
3792 /*
3793  * Register : Component ID1 Register - comp_id_1
3794  *
3795  * Component ID1
3796  *
3797  * Register Layout
3798  *
3799  * Bits | Access | Reset | Description
3800  * :-------|:-------|:------|:-------------------------------------
3801  * [7:0] | R | 0xf0 | Generic IP component class, Preamble
3802  * [31:8] | ??? | 0x0 | *UNDEFINED*
3803  *
3804  */
3805 /*
3806  * Field : Generic IP component class, Preamble - genipcompcls_preamble
3807  *
3808  * Generic IP component class, Preamble
3809  *
3810  * Field Access Macros:
3811  *
3812  */
3813 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3814 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0
3815 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3816 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7
3817 /* The width in bits of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3818 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8
3819 /* The mask used to set the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
3820 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff
3821 /* The mask used to clear the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
3822 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00
3823 /* The reset value of the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
3824 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0
3825 /* Extracts the ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */
3826 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3827 /* Produces a ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */
3828 #define ALT_L3_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3829 
3830 #ifndef __ASSEMBLY__
3831 /*
3832  * WARNING: The C register and register group struct declarations are provided for
3833  * convenience and illustrative purposes. They should, however, be used with
3834  * caution as the C language standard provides no guarantees about the alignment or
3835  * atomicity of device memory accesses. The recommended practice for writing
3836  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3837  * alt_write_word() functions.
3838  *
3839  * The struct declaration for register ALT_L3_ID_COMP_ID_1.
3840  */
3841 struct ALT_L3_ID_COMP_ID_1_s
3842 {
3843  const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */
3844  uint32_t : 24; /* *UNDEFINED* */
3845 };
3846 
3847 /* The typedef declaration for register ALT_L3_ID_COMP_ID_1. */
3848 typedef volatile struct ALT_L3_ID_COMP_ID_1_s ALT_L3_ID_COMP_ID_1_t;
3849 #endif /* __ASSEMBLY__ */
3850 
3851 /* The byte offset of the ALT_L3_ID_COMP_ID_1 register from the beginning of the component. */
3852 #define ALT_L3_ID_COMP_ID_1_OFST 0xff4
3853 
3854 /*
3855  * Register : Component ID2 Register - comp_id_2
3856  *
3857  * Component ID2
3858  *
3859  * Register Layout
3860  *
3861  * Bits | Access | Reset | Description
3862  * :-------|:-------|:------|:------------
3863  * [7:0] | R | 0x5 | Preamble
3864  * [31:8] | ??? | 0x0 | *UNDEFINED*
3865  *
3866  */
3867 /*
3868  * Field : Preamble - preamble
3869  *
3870  * Preamble
3871  *
3872  * Field Access Macros:
3873  *
3874  */
3875 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3876 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_LSB 0
3877 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3878 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_MSB 7
3879 /* The width in bits of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3880 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_WIDTH 8
3881 /* The mask used to set the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
3882 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff
3883 /* The mask used to clear the ALT_L3_ID_COMP_ID_2_PREAMBLE register field value. */
3884 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00
3885 /* The reset value of the ALT_L3_ID_COMP_ID_2_PREAMBLE register field. */
3886 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_RESET 0x5
3887 /* Extracts the ALT_L3_ID_COMP_ID_2_PREAMBLE field value from a register. */
3888 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3889 /* Produces a ALT_L3_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */
3890 #define ALT_L3_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3891 
3892 #ifndef __ASSEMBLY__
3893 /*
3894  * WARNING: The C register and register group struct declarations are provided for
3895  * convenience and illustrative purposes. They should, however, be used with
3896  * caution as the C language standard provides no guarantees about the alignment or
3897  * atomicity of device memory accesses. The recommended practice for writing
3898  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3899  * alt_write_word() functions.
3900  *
3901  * The struct declaration for register ALT_L3_ID_COMP_ID_2.
3902  */
3903 struct ALT_L3_ID_COMP_ID_2_s
3904 {
3905  const uint32_t preamble : 8; /* Preamble */
3906  uint32_t : 24; /* *UNDEFINED* */
3907 };
3908 
3909 /* The typedef declaration for register ALT_L3_ID_COMP_ID_2. */
3910 typedef volatile struct ALT_L3_ID_COMP_ID_2_s ALT_L3_ID_COMP_ID_2_t;
3911 #endif /* __ASSEMBLY__ */
3912 
3913 /* The byte offset of the ALT_L3_ID_COMP_ID_2 register from the beginning of the component. */
3914 #define ALT_L3_ID_COMP_ID_2_OFST 0xff8
3915 
3916 /*
3917  * Register : Component ID3 Register - comp_id_3
3918  *
3919  * Component ID3
3920  *
3921  * Register Layout
3922  *
3923  * Bits | Access | Reset | Description
3924  * :-------|:-------|:------|:------------
3925  * [7:0] | R | 0xb1 | Preamble
3926  * [31:8] | ??? | 0x0 | *UNDEFINED*
3927  *
3928  */
3929 /*
3930  * Field : Preamble - preamble
3931  *
3932  * Preamble
3933  *
3934  * Field Access Macros:
3935  *
3936  */
3937 /* The Least Significant Bit (LSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3938 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_LSB 0
3939 /* The Most Significant Bit (MSB) position of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3940 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_MSB 7
3941 /* The width in bits of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3942 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_WIDTH 8
3943 /* The mask used to set the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
3944 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff
3945 /* The mask used to clear the ALT_L3_ID_COMP_ID_3_PREAMBLE register field value. */
3946 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00
3947 /* The reset value of the ALT_L3_ID_COMP_ID_3_PREAMBLE register field. */
3948 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_RESET 0xb1
3949 /* Extracts the ALT_L3_ID_COMP_ID_3_PREAMBLE field value from a register. */
3950 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
3951 /* Produces a ALT_L3_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */
3952 #define ALT_L3_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
3953 
3954 #ifndef __ASSEMBLY__
3955 /*
3956  * WARNING: The C register and register group struct declarations are provided for
3957  * convenience and illustrative purposes. They should, however, be used with
3958  * caution as the C language standard provides no guarantees about the alignment or
3959  * atomicity of device memory accesses. The recommended practice for writing
3960  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3961  * alt_write_word() functions.
3962  *
3963  * The struct declaration for register ALT_L3_ID_COMP_ID_3.
3964  */
3965 struct ALT_L3_ID_COMP_ID_3_s
3966 {
3967  const uint32_t preamble : 8; /* Preamble */
3968  uint32_t : 24; /* *UNDEFINED* */
3969 };
3970 
3971 /* The typedef declaration for register ALT_L3_ID_COMP_ID_3. */
3972 typedef volatile struct ALT_L3_ID_COMP_ID_3_s ALT_L3_ID_COMP_ID_3_t;
3973 #endif /* __ASSEMBLY__ */
3974 
3975 /* The byte offset of the ALT_L3_ID_COMP_ID_3 register from the beginning of the component. */
3976 #define ALT_L3_ID_COMP_ID_3_OFST 0xffc
3977 
3978 #ifndef __ASSEMBLY__
3979 /*
3980  * WARNING: The C register and register group struct declarations are provided for
3981  * convenience and illustrative purposes. They should, however, be used with
3982  * caution as the C language standard provides no guarantees about the alignment or
3983  * atomicity of device memory accesses. The recommended practice for writing
3984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3985  * alt_write_word() functions.
3986  *
3987  * The struct declaration for register group ALT_L3_IDGRP.
3988  */
3989 struct ALT_L3_IDGRP_s
3990 {
3991  volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
3992  ALT_L3_ID_PERIPH_ID_4_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */
3993  volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
3994  ALT_L3_ID_PERIPH_ID_0_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */
3995  ALT_L3_ID_PERIPH_ID_1_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */
3996  ALT_L3_ID_PERIPH_ID_2_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */
3997  ALT_L3_ID_PERIPH_ID_3_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */
3998  ALT_L3_ID_COMP_ID_0_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */
3999  ALT_L3_ID_COMP_ID_1_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */
4000  ALT_L3_ID_COMP_ID_2_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */
4001  ALT_L3_ID_COMP_ID_3_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */
4002 };
4003 
4004 /* The typedef declaration for register group ALT_L3_IDGRP. */
4005 typedef volatile struct ALT_L3_IDGRP_s ALT_L3_IDGRP_t;
4006 /* The struct declaration for the raw register contents of register group ALT_L3_IDGRP. */
4007 struct ALT_L3_IDGRP_raw_s
4008 {
4009  uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
4010  volatile uint32_t periph_id_4; /* ALT_L3_ID_PERIPH_ID_4 */
4011  uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
4012  volatile uint32_t periph_id_0; /* ALT_L3_ID_PERIPH_ID_0 */
4013  volatile uint32_t periph_id_1; /* ALT_L3_ID_PERIPH_ID_1 */
4014  volatile uint32_t periph_id_2; /* ALT_L3_ID_PERIPH_ID_2 */
4015  volatile uint32_t periph_id_3; /* ALT_L3_ID_PERIPH_ID_3 */
4016  volatile uint32_t comp_id_0; /* ALT_L3_ID_COMP_ID_0 */
4017  volatile uint32_t comp_id_1; /* ALT_L3_ID_COMP_ID_1 */
4018  volatile uint32_t comp_id_2; /* ALT_L3_ID_COMP_ID_2 */
4019  volatile uint32_t comp_id_3; /* ALT_L3_ID_COMP_ID_3 */
4020 };
4021 
4022 /* The typedef declaration for the raw register contents of register group ALT_L3_IDGRP. */
4023 typedef volatile struct ALT_L3_IDGRP_raw_s ALT_L3_IDGRP_raw_t;
4024 #endif /* __ASSEMBLY__ */
4025 
4026 
4027 /*
4028  * Register Group : Master Register Group - ALT_L3_MSTGRP
4029  * Master Register Group
4030  *
4031  * Registers associated with master interfaces in the L3 Interconnect. Note that a
4032  * master in the L3 Interconnect connects to a slave in a module.
4033  *
4034  */
4035 /*
4036  * Register Group : L4 MAIN - ALT_L3_MST_L4MAIN
4037  * L4 MAIN
4038  *
4039  * Registers associated with the L4 MAIN master. This master is used to access the
4040  * APB slaves on the L4 MAIN bus.
4041  *
4042  */
4043 /*
4044  * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss
4045  *
4046  * Sets the issuing capability of the preceding switch arbitration scheme to
4047  * multiple or single outstanding transactions.
4048  *
4049  * Register Layout
4050  *
4051  * Bits | Access | Reset | Description
4052  * :-------|:-------|:------|:------------------------
4053  * [0] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_RD
4054  * [1] | RW | 0x0 | ALT_L3_FN_MOD_BM_ISS_WR
4055  * [31:2] | ??? | 0x0 | *UNDEFINED*
4056  *
4057  */
4058 /*
4059  * Field : rd
4060  *
4061  * Field Enumeration Values:
4062  *
4063  * Enum | Value | Description
4064  * :---------------------------------|:------|:-------------------------------------------
4065  * ALT_L3_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions
4066  * ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
4067  *
4068  * Field Access Macros:
4069  *
4070  */
4071 /*
4072  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
4073  *
4074  * Multiple outstanding read transactions
4075  */
4076 #define ALT_L3_FN_MOD_BM_ISS_RD_E_MULT 0x0
4077 /*
4078  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_RD
4079  *
4080  * Only a single outstanding read transaction
4081  */
4082 #define ALT_L3_FN_MOD_BM_ISS_RD_E_SINGLE 0x1
4083 
4084 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4085 #define ALT_L3_FN_MOD_BM_ISS_RD_LSB 0
4086 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4087 #define ALT_L3_FN_MOD_BM_ISS_RD_MSB 0
4088 /* The width in bits of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4089 #define ALT_L3_FN_MOD_BM_ISS_RD_WIDTH 1
4090 /* The mask used to set the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
4091 #define ALT_L3_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001
4092 /* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_RD register field value. */
4093 #define ALT_L3_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe
4094 /* The reset value of the ALT_L3_FN_MOD_BM_ISS_RD register field. */
4095 #define ALT_L3_FN_MOD_BM_ISS_RD_RESET 0x0
4096 /* Extracts the ALT_L3_FN_MOD_BM_ISS_RD field value from a register. */
4097 #define ALT_L3_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0)
4098 /* Produces a ALT_L3_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */
4099 #define ALT_L3_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001)
4100 
4101 /*
4102  * Field : wr
4103  *
4104  * Field Enumeration Values:
4105  *
4106  * Enum | Value | Description
4107  * :---------------------------------|:------|:--------------------------------------------
4108  * ALT_L3_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions
4109  * ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
4110  *
4111  * Field Access Macros:
4112  *
4113  */
4114 /*
4115  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
4116  *
4117  * Multiple outstanding write transactions
4118  */
4119 #define ALT_L3_FN_MOD_BM_ISS_WR_E_MULT 0x0
4120 /*
4121  * Enumerated value for register field ALT_L3_FN_MOD_BM_ISS_WR
4122  *
4123  * Only a single outstanding write transaction
4124  */
4125 #define ALT_L3_FN_MOD_BM_ISS_WR_E_SINGLE 0x1
4126 
4127 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4128 #define ALT_L3_FN_MOD_BM_ISS_WR_LSB 1
4129 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4130 #define ALT_L3_FN_MOD_BM_ISS_WR_MSB 1
4131 /* The width in bits of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4132 #define ALT_L3_FN_MOD_BM_ISS_WR_WIDTH 1
4133 /* The mask used to set the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
4134 #define ALT_L3_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002
4135 /* The mask used to clear the ALT_L3_FN_MOD_BM_ISS_WR register field value. */
4136 #define ALT_L3_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd
4137 /* The reset value of the ALT_L3_FN_MOD_BM_ISS_WR register field. */
4138 #define ALT_L3_FN_MOD_BM_ISS_WR_RESET 0x0
4139 /* Extracts the ALT_L3_FN_MOD_BM_ISS_WR field value from a register. */
4140 #define ALT_L3_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1)
4141 /* Produces a ALT_L3_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */
4142 #define ALT_L3_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002)
4143 
4144 #ifndef __ASSEMBLY__
4145 /*
4146  * WARNING: The C register and register group struct declarations are provided for
4147  * convenience and illustrative purposes. They should, however, be used with
4148  * caution as the C language standard provides no guarantees about the alignment or
4149  * atomicity of device memory accesses. The recommended practice for writing
4150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4151  * alt_write_word() functions.
4152  *
4153  * The struct declaration for register ALT_L3_FN_MOD_BM_ISS.
4154  */
4155 struct ALT_L3_FN_MOD_BM_ISS_s
4156 {
4157  uint32_t rd : 1; /* ALT_L3_FN_MOD_BM_ISS_RD */
4158  uint32_t wr : 1; /* ALT_L3_FN_MOD_BM_ISS_WR */
4159  uint32_t : 30; /* *UNDEFINED* */
4160 };
4161 
4162 /* The typedef declaration for register ALT_L3_FN_MOD_BM_ISS. */
4163 typedef volatile struct ALT_L3_FN_MOD_BM_ISS_s ALT_L3_FN_MOD_BM_ISS_t;
4164 #endif /* __ASSEMBLY__ */
4165 
4166 /* The byte offset of the ALT_L3_FN_MOD_BM_ISS register from the beginning of the component. */
4167 #define ALT_L3_FN_MOD_BM_ISS_OFST 0x8
4168 /* The address of the ALT_L3_FN_MOD_BM_ISS register. */
4169 #define ALT_L3_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_BM_ISS_OFST))
4170 
4171 #ifndef __ASSEMBLY__
4172 /*
4173  * WARNING: The C register and register group struct declarations are provided for
4174  * convenience and illustrative purposes. They should, however, be used with
4175  * caution as the C language standard provides no guarantees about the alignment or
4176  * atomicity of device memory accesses. The recommended practice for writing
4177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4178  * alt_write_word() functions.
4179  *
4180  * The struct declaration for register group ALT_L3_MST_L4MAIN.
4181  */
4182 struct ALT_L3_MST_L4MAIN_s
4183 {
4184  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4185  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4186 };
4187 
4188 /* The typedef declaration for register group ALT_L3_MST_L4MAIN. */
4189 typedef volatile struct ALT_L3_MST_L4MAIN_s ALT_L3_MST_L4MAIN_t;
4190 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
4191 struct ALT_L3_MST_L4MAIN_raw_s
4192 {
4193  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4194  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4195 };
4196 
4197 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MAIN. */
4198 typedef volatile struct ALT_L3_MST_L4MAIN_raw_s ALT_L3_MST_L4MAIN_raw_t;
4199 #endif /* __ASSEMBLY__ */
4200 
4201 
4202 /*
4203  * Register Group : L4 SP - ALT_L3_MST_L4SP
4204  * L4 SP
4205  *
4206  * Registers associated with the L4 SP master. This master is used to access the
4207  * APB slaves on the L4 SP bus.
4208  *
4209  */
4210 #ifndef __ASSEMBLY__
4211 /*
4212  * WARNING: The C register and register group struct declarations are provided for
4213  * convenience and illustrative purposes. They should, however, be used with
4214  * caution as the C language standard provides no guarantees about the alignment or
4215  * atomicity of device memory accesses. The recommended practice for writing
4216  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4217  * alt_write_word() functions.
4218  *
4219  * The struct declaration for register group ALT_L3_MST_L4SP.
4220  */
4221 struct ALT_L3_MST_L4SP_s
4222 {
4223  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4224  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4225 };
4226 
4227 /* The typedef declaration for register group ALT_L3_MST_L4SP. */
4228 typedef volatile struct ALT_L3_MST_L4SP_s ALT_L3_MST_L4SP_t;
4229 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
4230 struct ALT_L3_MST_L4SP_raw_s
4231 {
4232  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4233  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4234 };
4235 
4236 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SP. */
4237 typedef volatile struct ALT_L3_MST_L4SP_raw_s ALT_L3_MST_L4SP_raw_t;
4238 #endif /* __ASSEMBLY__ */
4239 
4240 
4241 /*
4242  * Register Group : L4 MP - ALT_L3_MST_L4MP
4243  * L4 MP
4244  *
4245  * Registers associated with the L4 MP master. This master is used to access the
4246  * APB slaves on the L4 MP bus.
4247  *
4248  */
4249 #ifndef __ASSEMBLY__
4250 /*
4251  * WARNING: The C register and register group struct declarations are provided for
4252  * convenience and illustrative purposes. They should, however, be used with
4253  * caution as the C language standard provides no guarantees about the alignment or
4254  * atomicity of device memory accesses. The recommended practice for writing
4255  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4256  * alt_write_word() functions.
4257  *
4258  * The struct declaration for register group ALT_L3_MST_L4MP.
4259  */
4260 struct ALT_L3_MST_L4MP_s
4261 {
4262  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4263  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4264 };
4265 
4266 /* The typedef declaration for register group ALT_L3_MST_L4MP. */
4267 typedef volatile struct ALT_L3_MST_L4MP_s ALT_L3_MST_L4MP_t;
4268 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
4269 struct ALT_L3_MST_L4MP_raw_s
4270 {
4271  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4272  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4273 };
4274 
4275 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4MP. */
4276 typedef volatile struct ALT_L3_MST_L4MP_raw_s ALT_L3_MST_L4MP_raw_t;
4277 #endif /* __ASSEMBLY__ */
4278 
4279 
4280 /*
4281  * Register Group : L4 OSC1 - ALT_L3_MST_L4OSC1
4282  * L4 OSC1
4283  *
4284  * Registers associated with the L4 OSC1 master. This master is used to access the
4285  * APB slaves on the L4 OSC1 bus.
4286  *
4287  */
4288 #ifndef __ASSEMBLY__
4289 /*
4290  * WARNING: The C register and register group struct declarations are provided for
4291  * convenience and illustrative purposes. They should, however, be used with
4292  * caution as the C language standard provides no guarantees about the alignment or
4293  * atomicity of device memory accesses. The recommended practice for writing
4294  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4295  * alt_write_word() functions.
4296  *
4297  * The struct declaration for register group ALT_L3_MST_L4OSC1.
4298  */
4299 struct ALT_L3_MST_L4OSC1_s
4300 {
4301  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4302  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4303 };
4304 
4305 /* The typedef declaration for register group ALT_L3_MST_L4OSC1. */
4306 typedef volatile struct ALT_L3_MST_L4OSC1_s ALT_L3_MST_L4OSC1_t;
4307 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
4308 struct ALT_L3_MST_L4OSC1_raw_s
4309 {
4310  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4311  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4312 };
4313 
4314 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4OSC1. */
4315 typedef volatile struct ALT_L3_MST_L4OSC1_raw_s ALT_L3_MST_L4OSC1_raw_t;
4316 #endif /* __ASSEMBLY__ */
4317 
4318 
4319 /*
4320  * Register Group : L4 SPIM - ALT_L3_MST_L4SPIM
4321  * L4 SPIM
4322  *
4323  * Registers associated with the L4 SPIM master. This master is used to access the
4324  * APB slaves on the L4 SPIM bus.
4325  *
4326  */
4327 #ifndef __ASSEMBLY__
4328 /*
4329  * WARNING: The C register and register group struct declarations are provided for
4330  * convenience and illustrative purposes. They should, however, be used with
4331  * caution as the C language standard provides no guarantees about the alignment or
4332  * atomicity of device memory accesses. The recommended practice for writing
4333  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4334  * alt_write_word() functions.
4335  *
4336  * The struct declaration for register group ALT_L3_MST_L4SPIM.
4337  */
4338 struct ALT_L3_MST_L4SPIM_s
4339 {
4340  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4341  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4342 };
4343 
4344 /* The typedef declaration for register group ALT_L3_MST_L4SPIM. */
4345 typedef volatile struct ALT_L3_MST_L4SPIM_s ALT_L3_MST_L4SPIM_t;
4346 /* The struct declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
4347 struct ALT_L3_MST_L4SPIM_raw_s
4348 {
4349  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4350  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4351 };
4352 
4353 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_L4SPIM. */
4354 typedef volatile struct ALT_L3_MST_L4SPIM_raw_s ALT_L3_MST_L4SPIM_raw_t;
4355 #endif /* __ASSEMBLY__ */
4356 
4357 
4358 /*
4359  * Register Group : STM - ALT_L3_MST_STM
4360  * STM
4361  *
4362  * Registers associated with the STM master. This master is used to access the STM
4363  * AXI slave.
4364  *
4365  */
4366 /*
4367  * Register : Issuing Functionality Modification Register - fn_mod
4368  *
4369  * Sets the block issuing capability to multiple or single outstanding
4370  * transactions.
4371  *
4372  * Register Layout
4373  *
4374  * Bits | Access | Reset | Description
4375  * :-------|:-------|:------|:-----------------
4376  * [0] | RW | 0x0 | ALT_L3_FN_MOD_RD
4377  * [1] | RW | 0x0 | ALT_L3_FN_MOD_WR
4378  * [31:2] | ??? | 0x0 | *UNDEFINED*
4379  *
4380  */
4381 /*
4382  * Field : rd
4383  *
4384  * Field Enumeration Values:
4385  *
4386  * Enum | Value | Description
4387  * :--------------------------|:------|:-------------------------------------------
4388  * ALT_L3_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions
4389  * ALT_L3_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
4390  *
4391  * Field Access Macros:
4392  *
4393  */
4394 /*
4395  * Enumerated value for register field ALT_L3_FN_MOD_RD
4396  *
4397  * Multiple outstanding read transactions
4398  */
4399 #define ALT_L3_FN_MOD_RD_E_MULT 0x0
4400 /*
4401  * Enumerated value for register field ALT_L3_FN_MOD_RD
4402  *
4403  * Only a single outstanding read transaction
4404  */
4405 #define ALT_L3_FN_MOD_RD_E_SINGLE 0x1
4406 
4407 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_RD register field. */
4408 #define ALT_L3_FN_MOD_RD_LSB 0
4409 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_RD register field. */
4410 #define ALT_L3_FN_MOD_RD_MSB 0
4411 /* The width in bits of the ALT_L3_FN_MOD_RD register field. */
4412 #define ALT_L3_FN_MOD_RD_WIDTH 1
4413 /* The mask used to set the ALT_L3_FN_MOD_RD register field value. */
4414 #define ALT_L3_FN_MOD_RD_SET_MSK 0x00000001
4415 /* The mask used to clear the ALT_L3_FN_MOD_RD register field value. */
4416 #define ALT_L3_FN_MOD_RD_CLR_MSK 0xfffffffe
4417 /* The reset value of the ALT_L3_FN_MOD_RD register field. */
4418 #define ALT_L3_FN_MOD_RD_RESET 0x0
4419 /* Extracts the ALT_L3_FN_MOD_RD field value from a register. */
4420 #define ALT_L3_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0)
4421 /* Produces a ALT_L3_FN_MOD_RD register field value suitable for setting the register. */
4422 #define ALT_L3_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001)
4423 
4424 /*
4425  * Field : wr
4426  *
4427  * Field Enumeration Values:
4428  *
4429  * Enum | Value | Description
4430  * :--------------------------|:------|:--------------------------------------------
4431  * ALT_L3_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions
4432  * ALT_L3_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
4433  *
4434  * Field Access Macros:
4435  *
4436  */
4437 /*
4438  * Enumerated value for register field ALT_L3_FN_MOD_WR
4439  *
4440  * Multiple outstanding write transactions
4441  */
4442 #define ALT_L3_FN_MOD_WR_E_MULT 0x0
4443 /*
4444  * Enumerated value for register field ALT_L3_FN_MOD_WR
4445  *
4446  * Only a single outstanding write transaction
4447  */
4448 #define ALT_L3_FN_MOD_WR_E_SINGLE 0x1
4449 
4450 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_WR register field. */
4451 #define ALT_L3_FN_MOD_WR_LSB 1
4452 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_WR register field. */
4453 #define ALT_L3_FN_MOD_WR_MSB 1
4454 /* The width in bits of the ALT_L3_FN_MOD_WR register field. */
4455 #define ALT_L3_FN_MOD_WR_WIDTH 1
4456 /* The mask used to set the ALT_L3_FN_MOD_WR register field value. */
4457 #define ALT_L3_FN_MOD_WR_SET_MSK 0x00000002
4458 /* The mask used to clear the ALT_L3_FN_MOD_WR register field value. */
4459 #define ALT_L3_FN_MOD_WR_CLR_MSK 0xfffffffd
4460 /* The reset value of the ALT_L3_FN_MOD_WR register field. */
4461 #define ALT_L3_FN_MOD_WR_RESET 0x0
4462 /* Extracts the ALT_L3_FN_MOD_WR field value from a register. */
4463 #define ALT_L3_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1)
4464 /* Produces a ALT_L3_FN_MOD_WR register field value suitable for setting the register. */
4465 #define ALT_L3_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002)
4466 
4467 #ifndef __ASSEMBLY__
4468 /*
4469  * WARNING: The C register and register group struct declarations are provided for
4470  * convenience and illustrative purposes. They should, however, be used with
4471  * caution as the C language standard provides no guarantees about the alignment or
4472  * atomicity of device memory accesses. The recommended practice for writing
4473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4474  * alt_write_word() functions.
4475  *
4476  * The struct declaration for register ALT_L3_FN_MOD.
4477  */
4478 struct ALT_L3_FN_MOD_s
4479 {
4480  uint32_t rd : 1; /* ALT_L3_FN_MOD_RD */
4481  uint32_t wr : 1; /* ALT_L3_FN_MOD_WR */
4482  uint32_t : 30; /* *UNDEFINED* */
4483 };
4484 
4485 /* The typedef declaration for register ALT_L3_FN_MOD. */
4486 typedef volatile struct ALT_L3_FN_MOD_s ALT_L3_FN_MOD_t;
4487 #endif /* __ASSEMBLY__ */
4488 
4489 /* The byte offset of the ALT_L3_FN_MOD register from the beginning of the component. */
4490 #define ALT_L3_FN_MOD_OFST 0x108
4491 /* The address of the ALT_L3_FN_MOD register. */
4492 #define ALT_L3_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_OFST))
4493 
4494 #ifndef __ASSEMBLY__
4495 /*
4496  * WARNING: The C register and register group struct declarations are provided for
4497  * convenience and illustrative purposes. They should, however, be used with
4498  * caution as the C language standard provides no guarantees about the alignment or
4499  * atomicity of device memory accesses. The recommended practice for writing
4500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4501  * alt_write_word() functions.
4502  *
4503  * The struct declaration for register group ALT_L3_MST_STM.
4504  */
4505 struct ALT_L3_MST_STM_s
4506 {
4507  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4508  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4509  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4510  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4511 };
4512 
4513 /* The typedef declaration for register group ALT_L3_MST_STM. */
4514 typedef volatile struct ALT_L3_MST_STM_s ALT_L3_MST_STM_t;
4515 /* The struct declaration for the raw register contents of register group ALT_L3_MST_STM. */
4516 struct ALT_L3_MST_STM_raw_s
4517 {
4518  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4519  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4520  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4521  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4522 };
4523 
4524 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_STM. */
4525 typedef volatile struct ALT_L3_MST_STM_raw_s ALT_L3_MST_STM_raw_t;
4526 #endif /* __ASSEMBLY__ */
4527 
4528 
4529 /*
4530  * Register Group : LWHPS2FPGA - ALT_L3_MST_LWH2F
4531  * LWHPS2FPGA
4532  *
4533  * Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used
4534  * to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the
4535  * registers for all 3 AXI bridges and to access slaves in the FPGA connected to
4536  * the LWHPS2FPGA AXI Bridge.
4537  *
4538  */
4539 #ifndef __ASSEMBLY__
4540 /*
4541  * WARNING: The C register and register group struct declarations are provided for
4542  * convenience and illustrative purposes. They should, however, be used with
4543  * caution as the C language standard provides no guarantees about the alignment or
4544  * atomicity of device memory accesses. The recommended practice for writing
4545  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4546  * alt_write_word() functions.
4547  *
4548  * The struct declaration for register group ALT_L3_MST_LWH2F.
4549  */
4550 struct ALT_L3_MST_LWH2F_s
4551 {
4552  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4553  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4554  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4555  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4556 };
4557 
4558 /* The typedef declaration for register group ALT_L3_MST_LWH2F. */
4559 typedef volatile struct ALT_L3_MST_LWH2F_s ALT_L3_MST_LWH2F_t;
4560 /* The struct declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
4561 struct ALT_L3_MST_LWH2F_raw_s
4562 {
4563  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4564  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4565  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4566  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4567 };
4568 
4569 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_LWH2F. */
4570 typedef volatile struct ALT_L3_MST_LWH2F_raw_s ALT_L3_MST_LWH2F_raw_t;
4571 #endif /* __ASSEMBLY__ */
4572 
4573 
4574 /*
4575  * Register Group : USB1 - ALT_L3_MST_USB1
4576  * USB1
4577  *
4578  * Registers associated with the USB1 master. This master is used to access the
4579  * registers in USB1.
4580  *
4581  */
4582 /*
4583  * Register : AHB Control Register - ahb_cntl
4584  *
4585  * Sets the block issuing capability to one outstanding transaction.
4586  *
4587  * Register Layout
4588  *
4589  * Bits | Access | Reset | Description
4590  * :-------|:-------|:------|:---------------------------
4591  * [0] | RW | 0x0 | ALT_L3_AHB_CNTL_DECERR_EN
4592  * [1] | RW | 0x0 | ALT_L3_AHB_CNTL_FORCE_INCR
4593  * [31:2] | ??? | 0x0 | *UNDEFINED*
4594  *
4595  */
4596 /*
4597  * Field : decerr_en
4598  *
4599  * Field Enumeration Values:
4600  *
4601  * Enum | Value | Description
4602  * :--------------------------------|:------|:-------------------------------------------------
4603  * ALT_L3_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response.
4604  * ALT_L3_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives
4605  * : | | an unaligned address or a write data beat
4606  * : | | without all the byte strobes set, creates a
4607  * : | | DECERR response.
4608  *
4609  * Field Access Macros:
4610  *
4611  */
4612 /*
4613  * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
4614  *
4615  * No DECERR response.
4616  */
4617 #define ALT_L3_AHB_CNTL_DECERR_EN_E_DIS 0x0
4618 /*
4619  * Enumerated value for register field ALT_L3_AHB_CNTL_DECERR_EN
4620  *
4621  * If the AHB protocol conversion function receives an unaligned address or a write
4622  * data beat without all the byte strobes set, creates a DECERR response.
4623  */
4624 #define ALT_L3_AHB_CNTL_DECERR_EN_E_EN 0x1
4625 
4626 /* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4627 #define ALT_L3_AHB_CNTL_DECERR_EN_LSB 0
4628 /* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4629 #define ALT_L3_AHB_CNTL_DECERR_EN_MSB 0
4630 /* The width in bits of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4631 #define ALT_L3_AHB_CNTL_DECERR_EN_WIDTH 1
4632 /* The mask used to set the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
4633 #define ALT_L3_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001
4634 /* The mask used to clear the ALT_L3_AHB_CNTL_DECERR_EN register field value. */
4635 #define ALT_L3_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe
4636 /* The reset value of the ALT_L3_AHB_CNTL_DECERR_EN register field. */
4637 #define ALT_L3_AHB_CNTL_DECERR_EN_RESET 0x0
4638 /* Extracts the ALT_L3_AHB_CNTL_DECERR_EN field value from a register. */
4639 #define ALT_L3_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0)
4640 /* Produces a ALT_L3_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */
4641 #define ALT_L3_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001)
4642 
4643 /*
4644  * Field : force_incr
4645  *
4646  * Field Enumeration Values:
4647  *
4648  * Enum | Value | Description
4649  * :---------------------------------|:------|:-------------------------------------------------
4650  * ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions
4651  * ALT_L3_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data
4652  * : | | strobes set, that write data beat is replaced
4653  * : | | with an IDLE beat. Also, causes all transactions
4654  * : | | that are to be output to the AHB domain to be an
4655  * : | | undefined length INCR.
4656  *
4657  * Field Access Macros:
4658  *
4659  */
4660 /*
4661  * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
4662  *
4663  * Multiple outstanding write transactions
4664  */
4665 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_DIS 0x0
4666 /*
4667  * Enumerated value for register field ALT_L3_AHB_CNTL_FORCE_INCR
4668  *
4669  * If a beat is received that has no write data strobes set, that write data beat
4670  * is replaced with an IDLE beat. Also, causes all transactions that are to be
4671  * output to the AHB domain to be an undefined length INCR.
4672  */
4673 #define ALT_L3_AHB_CNTL_FORCE_INCR_E_EN 0x1
4674 
4675 /* The Least Significant Bit (LSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4676 #define ALT_L3_AHB_CNTL_FORCE_INCR_LSB 1
4677 /* The Most Significant Bit (MSB) position of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4678 #define ALT_L3_AHB_CNTL_FORCE_INCR_MSB 1
4679 /* The width in bits of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4680 #define ALT_L3_AHB_CNTL_FORCE_INCR_WIDTH 1
4681 /* The mask used to set the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
4682 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002
4683 /* The mask used to clear the ALT_L3_AHB_CNTL_FORCE_INCR register field value. */
4684 #define ALT_L3_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd
4685 /* The reset value of the ALT_L3_AHB_CNTL_FORCE_INCR register field. */
4686 #define ALT_L3_AHB_CNTL_FORCE_INCR_RESET 0x0
4687 /* Extracts the ALT_L3_AHB_CNTL_FORCE_INCR field value from a register. */
4688 #define ALT_L3_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1)
4689 /* Produces a ALT_L3_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */
4690 #define ALT_L3_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002)
4691 
4692 #ifndef __ASSEMBLY__
4693 /*
4694  * WARNING: The C register and register group struct declarations are provided for
4695  * convenience and illustrative purposes. They should, however, be used with
4696  * caution as the C language standard provides no guarantees about the alignment or
4697  * atomicity of device memory accesses. The recommended practice for writing
4698  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4699  * alt_write_word() functions.
4700  *
4701  * The struct declaration for register ALT_L3_AHB_CNTL.
4702  */
4703 struct ALT_L3_AHB_CNTL_s
4704 {
4705  uint32_t decerr_en : 1; /* ALT_L3_AHB_CNTL_DECERR_EN */
4706  uint32_t force_incr : 1; /* ALT_L3_AHB_CNTL_FORCE_INCR */
4707  uint32_t : 30; /* *UNDEFINED* */
4708 };
4709 
4710 /* The typedef declaration for register ALT_L3_AHB_CNTL. */
4711 typedef volatile struct ALT_L3_AHB_CNTL_s ALT_L3_AHB_CNTL_t;
4712 #endif /* __ASSEMBLY__ */
4713 
4714 /* The byte offset of the ALT_L3_AHB_CNTL register from the beginning of the component. */
4715 #define ALT_L3_AHB_CNTL_OFST 0x44
4716 /* The address of the ALT_L3_AHB_CNTL register. */
4717 #define ALT_L3_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_AHB_CNTL_OFST))
4718 
4719 #ifndef __ASSEMBLY__
4720 /*
4721  * WARNING: The C register and register group struct declarations are provided for
4722  * convenience and illustrative purposes. They should, however, be used with
4723  * caution as the C language standard provides no guarantees about the alignment or
4724  * atomicity of device memory accesses. The recommended practice for writing
4725  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4726  * alt_write_word() functions.
4727  *
4728  * The struct declaration for register group ALT_L3_MST_USB1.
4729  */
4730 struct ALT_L3_MST_USB1_s
4731 {
4732  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4733  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4734  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4735  ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4736 };
4737 
4738 /* The typedef declaration for register group ALT_L3_MST_USB1. */
4739 typedef volatile struct ALT_L3_MST_USB1_s ALT_L3_MST_USB1_t;
4740 /* The struct declaration for the raw register contents of register group ALT_L3_MST_USB1. */
4741 struct ALT_L3_MST_USB1_raw_s
4742 {
4743  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4744  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4745  uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4746  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4747 };
4748 
4749 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB1. */
4750 typedef volatile struct ALT_L3_MST_USB1_raw_s ALT_L3_MST_USB1_raw_t;
4751 #endif /* __ASSEMBLY__ */
4752 
4753 
4754 /*
4755  * Register Group : NANDDATA - ALT_L3_MST_NANDDATA
4756  * NANDDATA
4757  *
4758  * Registers associated with the NANDDATA master. This master is used to access
4759  * data in the NAND flash controller.
4760  *
4761  */
4762 #ifndef __ASSEMBLY__
4763 /*
4764  * WARNING: The C register and register group struct declarations are provided for
4765  * convenience and illustrative purposes. They should, however, be used with
4766  * caution as the C language standard provides no guarantees about the alignment or
4767  * atomicity of device memory accesses. The recommended practice for writing
4768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4769  * alt_write_word() functions.
4770  *
4771  * The struct declaration for register group ALT_L3_MST_NANDDATA.
4772  */
4773 struct ALT_L3_MST_NANDDATA_s
4774 {
4775  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4776  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4777  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4778  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4779 };
4780 
4781 /* The typedef declaration for register group ALT_L3_MST_NANDDATA. */
4782 typedef volatile struct ALT_L3_MST_NANDDATA_s ALT_L3_MST_NANDDATA_t;
4783 /* The struct declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
4784 struct ALT_L3_MST_NANDDATA_raw_s
4785 {
4786  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4787  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4788  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4789  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4790 };
4791 
4792 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_NANDDATA. */
4793 typedef volatile struct ALT_L3_MST_NANDDATA_raw_s ALT_L3_MST_NANDDATA_raw_t;
4794 #endif /* __ASSEMBLY__ */
4795 
4796 
4797 /*
4798  * Register Group : USB0 - ALT_L3_MST_USB0
4799  * USB0
4800  *
4801  * Registers associated with the USB0 master. This master is used to access the
4802  * registers in USB0.
4803  *
4804  */
4805 #ifndef __ASSEMBLY__
4806 /*
4807  * WARNING: The C register and register group struct declarations are provided for
4808  * convenience and illustrative purposes. They should, however, be used with
4809  * caution as the C language standard provides no guarantees about the alignment or
4810  * atomicity of device memory accesses. The recommended practice for writing
4811  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4812  * alt_write_word() functions.
4813  *
4814  * The struct declaration for register group ALT_L3_MST_USB0.
4815  */
4816 struct ALT_L3_MST_USB0_s
4817 {
4818  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4819  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4820  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4821  ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4822 };
4823 
4824 /* The typedef declaration for register group ALT_L3_MST_USB0. */
4825 typedef volatile struct ALT_L3_MST_USB0_s ALT_L3_MST_USB0_t;
4826 /* The struct declaration for the raw register contents of register group ALT_L3_MST_USB0. */
4827 struct ALT_L3_MST_USB0_raw_s
4828 {
4829  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4830  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4831  uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4832  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4833 };
4834 
4835 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_USB0. */
4836 typedef volatile struct ALT_L3_MST_USB0_raw_s ALT_L3_MST_USB0_raw_t;
4837 #endif /* __ASSEMBLY__ */
4838 
4839 
4840 /*
4841  * Register Group : NANDREGS - ALT_L3_MST_NAND
4842  * NANDREGS
4843  *
4844  * Registers associated with the NANDREGS master. This master is used to access the
4845  * registers in the NAND flash controller.
4846  *
4847  */
4848 #ifndef __ASSEMBLY__
4849 /*
4850  * WARNING: The C register and register group struct declarations are provided for
4851  * convenience and illustrative purposes. They should, however, be used with
4852  * caution as the C language standard provides no guarantees about the alignment or
4853  * atomicity of device memory accesses. The recommended practice for writing
4854  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4855  * alt_write_word() functions.
4856  *
4857  * The struct declaration for register group ALT_L3_MST_NAND.
4858  */
4859 struct ALT_L3_MST_NAND_s
4860 {
4861  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4862  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4863  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4864  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
4865 };
4866 
4867 /* The typedef declaration for register group ALT_L3_MST_NAND. */
4868 typedef volatile struct ALT_L3_MST_NAND_s ALT_L3_MST_NAND_t;
4869 /* The struct declaration for the raw register contents of register group ALT_L3_MST_NAND. */
4870 struct ALT_L3_MST_NAND_raw_s
4871 {
4872  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4873  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4874  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
4875  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
4876 };
4877 
4878 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_NAND. */
4879 typedef volatile struct ALT_L3_MST_NAND_raw_s ALT_L3_MST_NAND_raw_t;
4880 #endif /* __ASSEMBLY__ */
4881 
4882 
4883 /*
4884  * Register Group : QSPIDATA - ALT_L3_MST_QSPIDATA
4885  * QSPIDATA
4886  *
4887  * Registers associated with the QSPIDATA master. This master is used to access
4888  * data in the QSPI flash controller.
4889  *
4890  */
4891 #ifndef __ASSEMBLY__
4892 /*
4893  * WARNING: The C register and register group struct declarations are provided for
4894  * convenience and illustrative purposes. They should, however, be used with
4895  * caution as the C language standard provides no guarantees about the alignment or
4896  * atomicity of device memory accesses. The recommended practice for writing
4897  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4898  * alt_write_word() functions.
4899  *
4900  * The struct declaration for register group ALT_L3_MST_QSPIDATA.
4901  */
4902 struct ALT_L3_MST_QSPIDATA_s
4903 {
4904  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4905  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4906  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4907  ALT_L3_AHB_CNTL_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4908 };
4909 
4910 /* The typedef declaration for register group ALT_L3_MST_QSPIDATA. */
4911 typedef volatile struct ALT_L3_MST_QSPIDATA_s ALT_L3_MST_QSPIDATA_t;
4912 /* The struct declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
4913 struct ALT_L3_MST_QSPIDATA_raw_s
4914 {
4915  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
4916  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
4917  uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
4918  volatile uint32_t ahb_cntl; /* ALT_L3_AHB_CNTL */
4919 };
4920 
4921 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_QSPIDATA. */
4922 typedef volatile struct ALT_L3_MST_QSPIDATA_raw_s ALT_L3_MST_QSPIDATA_raw_t;
4923 #endif /* __ASSEMBLY__ */
4924 
4925 
4926 /*
4927  * Register Group : FPGAMGRDATA - ALT_L3_MST_FPGAMGRDATA
4928  * FPGAMGRDATA
4929  *
4930  * Registers associated with the FPGAMGRDATA master. This master is used to send
4931  * FPGA configuration image data to the FPGA Manager.
4932  *
4933  */
4934 /*
4935  * Register : Write Tidemark - wr_tidemark
4936  *
4937  * Controls the release of the transaction in the write data FIFO.
4938  *
4939  * Register Layout
4940  *
4941  * Bits | Access | Reset | Description
4942  * :-------|:-------|:------|:------------
4943  * [3:0] | RW | 0x4 | Level
4944  * [31:4] | ??? | 0x0 | *UNDEFINED*
4945  *
4946  */
4947 /*
4948  * Field : Level - level
4949  *
4950  * Stalls the transaction in the write data FIFO until the number of occupied slots
4951  * in the write data FIFO exceeds the level. Note that the transaction is released
4952  * before this level is achieved if the network receives the WLAST beat or the
4953  * write FIFO becomes full.
4954  *
4955  * Field Access Macros:
4956  *
4957  */
4958 /* The Least Significant Bit (LSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4959 #define ALT_L3_WR_TIDEMARK_LEVEL_LSB 0
4960 /* The Most Significant Bit (MSB) position of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4961 #define ALT_L3_WR_TIDEMARK_LEVEL_MSB 3
4962 /* The width in bits of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4963 #define ALT_L3_WR_TIDEMARK_LEVEL_WIDTH 4
4964 /* The mask used to set the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
4965 #define ALT_L3_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f
4966 /* The mask used to clear the ALT_L3_WR_TIDEMARK_LEVEL register field value. */
4967 #define ALT_L3_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0
4968 /* The reset value of the ALT_L3_WR_TIDEMARK_LEVEL register field. */
4969 #define ALT_L3_WR_TIDEMARK_LEVEL_RESET 0x4
4970 /* Extracts the ALT_L3_WR_TIDEMARK_LEVEL field value from a register. */
4971 #define ALT_L3_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
4972 /* Produces a ALT_L3_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */
4973 #define ALT_L3_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
4974 
4975 #ifndef __ASSEMBLY__
4976 /*
4977  * WARNING: The C register and register group struct declarations are provided for
4978  * convenience and illustrative purposes. They should, however, be used with
4979  * caution as the C language standard provides no guarantees about the alignment or
4980  * atomicity of device memory accesses. The recommended practice for writing
4981  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4982  * alt_write_word() functions.
4983  *
4984  * The struct declaration for register ALT_L3_WR_TIDEMARK.
4985  */
4986 struct ALT_L3_WR_TIDEMARK_s
4987 {
4988  uint32_t level : 4; /* Level */
4989  uint32_t : 28; /* *UNDEFINED* */
4990 };
4991 
4992 /* The typedef declaration for register ALT_L3_WR_TIDEMARK. */
4993 typedef volatile struct ALT_L3_WR_TIDEMARK_s ALT_L3_WR_TIDEMARK_t;
4994 #endif /* __ASSEMBLY__ */
4995 
4996 /* The byte offset of the ALT_L3_WR_TIDEMARK register from the beginning of the component. */
4997 #define ALT_L3_WR_TIDEMARK_OFST 0x40
4998 /* The address of the ALT_L3_WR_TIDEMARK register. */
4999 #define ALT_L3_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_TIDEMARK_OFST))
5000 
5001 #ifndef __ASSEMBLY__
5002 /*
5003  * WARNING: The C register and register group struct declarations are provided for
5004  * convenience and illustrative purposes. They should, however, be used with
5005  * caution as the C language standard provides no guarantees about the alignment or
5006  * atomicity of device memory accesses. The recommended practice for writing
5007  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5008  * alt_write_word() functions.
5009  *
5010  * The struct declaration for register group ALT_L3_MST_FPGAMGRDATA.
5011  */
5012 struct ALT_L3_MST_FPGAMGRDATA_s
5013 {
5014  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5015  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5016  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5017  ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5018  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5019  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5020 };
5021 
5022 /* The typedef declaration for register group ALT_L3_MST_FPGAMGRDATA. */
5023 typedef volatile struct ALT_L3_MST_FPGAMGRDATA_s ALT_L3_MST_FPGAMGRDATA_t;
5024 /* The struct declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
5025 struct ALT_L3_MST_FPGAMGRDATA_raw_s
5026 {
5027  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5028  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5029  uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5030  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5031  uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5032  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5033 };
5034 
5035 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_FPGAMGRDATA. */
5036 typedef volatile struct ALT_L3_MST_FPGAMGRDATA_raw_s ALT_L3_MST_FPGAMGRDATA_raw_t;
5037 #endif /* __ASSEMBLY__ */
5038 
5039 
5040 /*
5041  * Register Group : HPS2FPGA - ALT_L3_MST_H2F
5042  * HPS2FPGA
5043  *
5044  * Registers associated with the HPS2FPGA AXI Bridge master. This master is used to
5045  * access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the
5046  * FPGA connected to the HPS2FPGA AXI Bridge.
5047  *
5048  */
5049 #ifndef __ASSEMBLY__
5050 /*
5051  * WARNING: The C register and register group struct declarations are provided for
5052  * convenience and illustrative purposes. They should, however, be used with
5053  * caution as the C language standard provides no guarantees about the alignment or
5054  * atomicity of device memory accesses. The recommended practice for writing
5055  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5056  * alt_write_word() functions.
5057  *
5058  * The struct declaration for register group ALT_L3_MST_H2F.
5059  */
5060 struct ALT_L3_MST_H2F_s
5061 {
5062  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5063  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5064  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5065  ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5066  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5067  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5068 };
5069 
5070 /* The typedef declaration for register group ALT_L3_MST_H2F. */
5071 typedef volatile struct ALT_L3_MST_H2F_s ALT_L3_MST_H2F_t;
5072 /* The struct declaration for the raw register contents of register group ALT_L3_MST_H2F. */
5073 struct ALT_L3_MST_H2F_raw_s
5074 {
5075  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5076  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5077  uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5078  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5079  uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5080  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5081 };
5082 
5083 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_H2F. */
5084 typedef volatile struct ALT_L3_MST_H2F_raw_s ALT_L3_MST_H2F_raw_t;
5085 #endif /* __ASSEMBLY__ */
5086 
5087 
5088 /*
5089  * Register Group : ACP - ALT_L3_MST_ACP
5090  * ACP
5091  *
5092  * Registers associated with the ACP master. This master is used to access the MPU
5093  * ACP slave via the ACP ID Mapper.
5094  *
5095  */
5096 #ifndef __ASSEMBLY__
5097 /*
5098  * WARNING: The C register and register group struct declarations are provided for
5099  * convenience and illustrative purposes. They should, however, be used with
5100  * caution as the C language standard provides no guarantees about the alignment or
5101  * atomicity of device memory accesses. The recommended practice for writing
5102  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5103  * alt_write_word() functions.
5104  *
5105  * The struct declaration for register group ALT_L3_MST_ACP.
5106  */
5107 struct ALT_L3_MST_ACP_s
5108 {
5109  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5110  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5111  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5112  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5113 };
5114 
5115 /* The typedef declaration for register group ALT_L3_MST_ACP. */
5116 typedef volatile struct ALT_L3_MST_ACP_s ALT_L3_MST_ACP_t;
5117 /* The struct declaration for the raw register contents of register group ALT_L3_MST_ACP. */
5118 struct ALT_L3_MST_ACP_raw_s
5119 {
5120  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5121  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5122  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5123  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5124 };
5125 
5126 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_ACP. */
5127 typedef volatile struct ALT_L3_MST_ACP_raw_s ALT_L3_MST_ACP_raw_t;
5128 #endif /* __ASSEMBLY__ */
5129 
5130 
5131 /*
5132  * Register Group : Boot ROM - ALT_L3_MST_ROM
5133  * Boot ROM
5134  *
5135  * Registers associated with the Boot ROM master. This master is used to access the
5136  * contents of the Boot ROM.
5137  *
5138  */
5139 #ifndef __ASSEMBLY__
5140 /*
5141  * WARNING: The C register and register group struct declarations are provided for
5142  * convenience and illustrative purposes. They should, however, be used with
5143  * caution as the C language standard provides no guarantees about the alignment or
5144  * atomicity of device memory accesses. The recommended practice for writing
5145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5146  * alt_write_word() functions.
5147  *
5148  * The struct declaration for register group ALT_L3_MST_ROM.
5149  */
5150 struct ALT_L3_MST_ROM_s
5151 {
5152  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5153  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5154  volatile uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5155  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5156 };
5157 
5158 /* The typedef declaration for register group ALT_L3_MST_ROM. */
5159 typedef volatile struct ALT_L3_MST_ROM_s ALT_L3_MST_ROM_t;
5160 /* The struct declaration for the raw register contents of register group ALT_L3_MST_ROM. */
5161 struct ALT_L3_MST_ROM_raw_s
5162 {
5163  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5164  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5165  uint32_t _pad_0xc_0x107[63]; /* *UNDEFINED* */
5166  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5167 };
5168 
5169 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_ROM. */
5170 typedef volatile struct ALT_L3_MST_ROM_raw_s ALT_L3_MST_ROM_raw_t;
5171 #endif /* __ASSEMBLY__ */
5172 
5173 
5174 /*
5175  * Register Group : On-chip RAM - ALT_L3_MST_OCRAM
5176  * On-chip RAM
5177  *
5178  * Registers associated with the On-chip RAM master. This master is used to access
5179  * the contents of the On-chip RAM.
5180  *
5181  */
5182 #ifndef __ASSEMBLY__
5183 /*
5184  * WARNING: The C register and register group struct declarations are provided for
5185  * convenience and illustrative purposes. They should, however, be used with
5186  * caution as the C language standard provides no guarantees about the alignment or
5187  * atomicity of device memory accesses. The recommended practice for writing
5188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5189  * alt_write_word() functions.
5190  *
5191  * The struct declaration for register group ALT_L3_MST_OCRAM.
5192  */
5193 struct ALT_L3_MST_OCRAM_s
5194 {
5195  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5196  ALT_L3_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5197  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5198  ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5199  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5200  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5201 };
5202 
5203 /* The typedef declaration for register group ALT_L3_MST_OCRAM. */
5204 typedef volatile struct ALT_L3_MST_OCRAM_s ALT_L3_MST_OCRAM_t;
5205 /* The struct declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
5206 struct ALT_L3_MST_OCRAM_raw_s
5207 {
5208  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
5209  volatile uint32_t fn_mod_bm_iss; /* ALT_L3_FN_MOD_BM_ISS */
5210  uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
5211  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5212  uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
5213  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5214 };
5215 
5216 /* The typedef declaration for the raw register contents of register group ALT_L3_MST_OCRAM. */
5217 typedef volatile struct ALT_L3_MST_OCRAM_raw_s ALT_L3_MST_OCRAM_raw_t;
5218 #endif /* __ASSEMBLY__ */
5219 
5220 
5221 #ifndef __ASSEMBLY__
5222 /*
5223  * WARNING: The C register and register group struct declarations are provided for
5224  * convenience and illustrative purposes. They should, however, be used with
5225  * caution as the C language standard provides no guarantees about the alignment or
5226  * atomicity of device memory accesses. The recommended practice for writing
5227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5228  * alt_write_word() functions.
5229  *
5230  * The struct declaration for register group ALT_L3_MSTGRP.
5231  */
5232 struct ALT_L3_MSTGRP_s
5233 {
5234  ALT_L3_MST_L4MAIN_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */
5235  volatile uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */
5236  ALT_L3_MST_L4SP_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */
5237  volatile uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */
5238  ALT_L3_MST_L4MP_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */
5239  volatile uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */
5240  ALT_L3_MST_L4OSC1_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */
5241  volatile uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */
5242  ALT_L3_MST_L4SPIM_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */
5243  volatile uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */
5244  ALT_L3_MST_STM_t mastergrp_stm; /* ALT_L3_MST_STM */
5245  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
5246  ALT_L3_MST_LWH2F_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */
5247  volatile uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */
5248  ALT_L3_MST_USB1_t mastergrp_usb1; /* ALT_L3_MST_USB1 */
5249  volatile uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */
5250  ALT_L3_MST_NANDDATA_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */
5251  volatile uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */
5252  ALT_L3_MST_USB0_t mastergrp_usb0; /* ALT_L3_MST_USB0 */
5253  volatile uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */
5254  ALT_L3_MST_NAND_t mastergrp_nandregs; /* ALT_L3_MST_NAND */
5255  volatile uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */
5256  ALT_L3_MST_QSPIDATA_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */
5257  volatile uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */
5258  ALT_L3_MST_FPGAMGRDATA_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */
5259  volatile uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */
5260  ALT_L3_MST_H2F_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */
5261  volatile uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */
5262  ALT_L3_MST_ACP_t mastergrp_acp; /* ALT_L3_MST_ACP */
5263  volatile uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */
5264  ALT_L3_MST_ROM_t mastergrp_rom; /* ALT_L3_MST_ROM */
5265  volatile uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */
5266  ALT_L3_MST_OCRAM_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */
5267 };
5268 
5269 /* The typedef declaration for register group ALT_L3_MSTGRP. */
5270 typedef volatile struct ALT_L3_MSTGRP_s ALT_L3_MSTGRP_t;
5271 /* The struct declaration for the raw register contents of register group ALT_L3_MSTGRP. */
5272 struct ALT_L3_MSTGRP_raw_s
5273 {
5274  ALT_L3_MST_L4MAIN_raw_t mastergrp_l4main; /* ALT_L3_MST_L4MAIN */
5275  uint32_t _pad_0xc_0xfff[1021]; /* *UNDEFINED* */
5276  ALT_L3_MST_L4SP_raw_t mastergrp_l4sp; /* ALT_L3_MST_L4SP */
5277  uint32_t _pad_0x100c_0x1fff[1021]; /* *UNDEFINED* */
5278  ALT_L3_MST_L4MP_raw_t mastergrp_l4mp; /* ALT_L3_MST_L4MP */
5279  uint32_t _pad_0x200c_0x2fff[1021]; /* *UNDEFINED* */
5280  ALT_L3_MST_L4OSC1_raw_t mastergrp_l4osc1; /* ALT_L3_MST_L4OSC1 */
5281  uint32_t _pad_0x300c_0x3fff[1021]; /* *UNDEFINED* */
5282  ALT_L3_MST_L4SPIM_raw_t mastergrp_l4spim; /* ALT_L3_MST_L4SPIM */
5283  uint32_t _pad_0x400c_0x4fff[1021]; /* *UNDEFINED* */
5284  ALT_L3_MST_STM_raw_t mastergrp_stm; /* ALT_L3_MST_STM */
5285  uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
5286  ALT_L3_MST_LWH2F_raw_t mastergrp_lwhps2fpga; /* ALT_L3_MST_LWH2F */
5287  uint32_t _pad_0x610c_0x7fff[1981]; /* *UNDEFINED* */
5288  ALT_L3_MST_USB1_raw_t mastergrp_usb1; /* ALT_L3_MST_USB1 */
5289  uint32_t _pad_0x8048_0x8fff[1006]; /* *UNDEFINED* */
5290  ALT_L3_MST_NANDDATA_raw_t mastergrp_nanddata; /* ALT_L3_MST_NANDDATA */
5291  uint32_t _pad_0x910c_0x1dfff[21437]; /* *UNDEFINED* */
5292  ALT_L3_MST_USB0_raw_t mastergrp_usb0; /* ALT_L3_MST_USB0 */
5293  uint32_t _pad_0x1e048_0x1efff[1006]; /* *UNDEFINED* */
5294  ALT_L3_MST_NAND_raw_t mastergrp_nandregs; /* ALT_L3_MST_NAND */
5295  uint32_t _pad_0x1f10c_0x1ffff[957]; /* *UNDEFINED* */
5296  ALT_L3_MST_QSPIDATA_raw_t mastergrp_qspidata; /* ALT_L3_MST_QSPIDATA */
5297  uint32_t _pad_0x20048_0x20fff[1006]; /* *UNDEFINED* */
5298  ALT_L3_MST_FPGAMGRDATA_raw_t mastergrp_fpgamgrdata; /* ALT_L3_MST_FPGAMGRDATA */
5299  uint32_t _pad_0x2110c_0x21fff[957]; /* *UNDEFINED* */
5300  ALT_L3_MST_H2F_raw_t mastergrp_hps2fpga; /* ALT_L3_MST_H2F */
5301  uint32_t _pad_0x2210c_0x22fff[957]; /* *UNDEFINED* */
5302  ALT_L3_MST_ACP_raw_t mastergrp_acp; /* ALT_L3_MST_ACP */
5303  uint32_t _pad_0x2310c_0x23fff[957]; /* *UNDEFINED* */
5304  ALT_L3_MST_ROM_raw_t mastergrp_rom; /* ALT_L3_MST_ROM */
5305  uint32_t _pad_0x2410c_0x24fff[957]; /* *UNDEFINED* */
5306  ALT_L3_MST_OCRAM_raw_t mastergrp_ocram; /* ALT_L3_MST_OCRAM */
5307 };
5308 
5309 /* The typedef declaration for the raw register contents of register group ALT_L3_MSTGRP. */
5310 typedef volatile struct ALT_L3_MSTGRP_raw_s ALT_L3_MSTGRP_raw_t;
5311 #endif /* __ASSEMBLY__ */
5312 
5313 
5314 /*
5315  * Register Group : Slave Register Group - ALT_L3_SLVGRP
5316  * Slave Register Group
5317  *
5318  * Registers associated with slave interfaces.
5319  *
5320  */
5321 /*
5322  * Register Group : DAP - ALT_L3_SLV_DAP
5323  * DAP
5324  *
5325  * Registers associated with the DAP slave interface. This slave is used by the DAP
5326  * to access slaves attached to the L3/L4 Interconnect.
5327  *
5328  */
5329 /*
5330  * Register : Functionality Modification 2 Register - fn_mod2
5331  *
5332  * Controls bypass merge of upsizing/downsizing.
5333  *
5334  * Register Layout
5335  *
5336  * Bits | Access | Reset | Description
5337  * :-------|:-------|:------|:-------------
5338  * [0] | RW | 0x0 | Bypass Merge
5339  * [31:1] | ??? | 0x0 | *UNDEFINED*
5340  *
5341  */
5342 /*
5343  * Field : Bypass Merge - bypass_merge
5344  *
5345  * Controls bypass merge of upsizing/downsizing.
5346  *
5347  * Field Enumeration Values:
5348  *
5349  * Enum | Value | Description
5350  * :--------------------------------------|:------|:-------------------------------------------------
5351  * ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER | 0x0 | The network can alter transactions.
5352  * ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER | 0x1 | The network does not alter any transactions that
5353  * : | | could pass through the upsizer legally without
5354  * : | | alteration.
5355  *
5356  * Field Access Macros:
5357  *
5358  */
5359 /*
5360  * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
5361  *
5362  * The network can alter transactions.
5363  */
5364 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_ALTER 0x0
5365 /*
5366  * Enumerated value for register field ALT_L3_FN_MOD2_BYPASS_MERGE
5367  *
5368  * The network does not alter any transactions that could pass through the upsizer
5369  * legally without alteration.
5370  */
5371 #define ALT_L3_FN_MOD2_BYPASS_MERGE_E_NOALTER 0x1
5372 
5373 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5374 #define ALT_L3_FN_MOD2_BYPASS_MERGE_LSB 0
5375 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5376 #define ALT_L3_FN_MOD2_BYPASS_MERGE_MSB 0
5377 /* The width in bits of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5378 #define ALT_L3_FN_MOD2_BYPASS_MERGE_WIDTH 1
5379 /* The mask used to set the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
5380 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET_MSK 0x00000001
5381 /* The mask used to clear the ALT_L3_FN_MOD2_BYPASS_MERGE register field value. */
5382 #define ALT_L3_FN_MOD2_BYPASS_MERGE_CLR_MSK 0xfffffffe
5383 /* The reset value of the ALT_L3_FN_MOD2_BYPASS_MERGE register field. */
5384 #define ALT_L3_FN_MOD2_BYPASS_MERGE_RESET 0x0
5385 /* Extracts the ALT_L3_FN_MOD2_BYPASS_MERGE field value from a register. */
5386 #define ALT_L3_FN_MOD2_BYPASS_MERGE_GET(value) (((value) & 0x00000001) >> 0)
5387 /* Produces a ALT_L3_FN_MOD2_BYPASS_MERGE register field value suitable for setting the register. */
5388 #define ALT_L3_FN_MOD2_BYPASS_MERGE_SET(value) (((value) << 0) & 0x00000001)
5389 
5390 #ifndef __ASSEMBLY__
5391 /*
5392  * WARNING: The C register and register group struct declarations are provided for
5393  * convenience and illustrative purposes. They should, however, be used with
5394  * caution as the C language standard provides no guarantees about the alignment or
5395  * atomicity of device memory accesses. The recommended practice for writing
5396  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5397  * alt_write_word() functions.
5398  *
5399  * The struct declaration for register ALT_L3_FN_MOD2.
5400  */
5401 struct ALT_L3_FN_MOD2_s
5402 {
5403  uint32_t bypass_merge : 1; /* Bypass Merge */
5404  uint32_t : 31; /* *UNDEFINED* */
5405 };
5406 
5407 /* The typedef declaration for register ALT_L3_FN_MOD2. */
5408 typedef volatile struct ALT_L3_FN_MOD2_s ALT_L3_FN_MOD2_t;
5409 #endif /* __ASSEMBLY__ */
5410 
5411 /* The byte offset of the ALT_L3_FN_MOD2 register from the beginning of the component. */
5412 #define ALT_L3_FN_MOD2_OFST 0x24
5413 /* The address of the ALT_L3_FN_MOD2 register. */
5414 #define ALT_L3_FN_MOD2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD2_OFST))
5415 
5416 /*
5417  * Register : Functionality Modification AHB Register - fn_mod_ahb
5418  *
5419  * Controls how AHB-lite burst transactions are converted to AXI tranactions.
5420  *
5421  * Register Layout
5422  *
5423  * Bits | Access | Reset | Description
5424  * :-------|:-------|:------|:-------------------------
5425  * [0] | RW | 0x0 | Read Increment Override
5426  * [1] | RW | 0x0 | Write Increment Override
5427  * [31:2] | ??? | 0x0 | *UNDEFINED*
5428  *
5429  */
5430 /*
5431  * Field : Read Increment Override - rd_incr_override
5432  *
5433  * Controls how AHB-lite read burst transactions are converted to AXI tranactions.
5434  *
5435  * Field Enumeration Values:
5436  *
5437  * Enum | Value | Description
5438  * :---------------------------------------------|:------|:----------------------------------------------
5439  * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite read
5440  * : | | bursts to AXI transactions in accordance with
5441  * : | | the default behavior as specified in the ARM
5442  * : | | NIC-301 documentation.
5443  * ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite read
5444  * : | | bursts to AXI single transactions.
5445  *
5446  * Field Access Macros:
5447  *
5448  */
5449 /*
5450  * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
5451  *
5452  * The L3 Interconnect converts AHB-lite read bursts to AXI transactions in
5453  * accordance with the default behavior as specified in the ARM NIC-301
5454  * documentation.
5455  */
5456 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_DEFAULT 0x0
5457 /*
5458  * Enumerated value for register field ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE
5459  *
5460  * The L3 Interconnect converts AHB-lite read bursts to AXI single transactions.
5461  */
5462 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_E_SINGLES 0x1
5463 
5464 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5465 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_LSB 0
5466 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5467 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_MSB 0
5468 /* The width in bits of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5469 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_WIDTH 1
5470 /* The mask used to set the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
5471 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET_MSK 0x00000001
5472 /* The mask used to clear the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value. */
5473 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_CLR_MSK 0xfffffffe
5474 /* The reset value of the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field. */
5475 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_RESET 0x0
5476 /* Extracts the ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE field value from a register. */
5477 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_GET(value) (((value) & 0x00000001) >> 0)
5478 /* Produces a ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE register field value suitable for setting the register. */
5479 #define ALT_L3_FN_MOD_AHB_RD_INCR_OVERRIDE_SET(value) (((value) << 0) & 0x00000001)
5480 
5481 /*
5482  * Field : Write Increment Override - wr_incr_override
5483  *
5484  * Controls how AHB-lite write burst transactions are converted to AXI tranactions.
5485  *
5486  * Field Enumeration Values:
5487  *
5488  * Enum | Value | Description
5489  * :---------------------------------------------|:------|:----------------------------------------------
5490  * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT | 0x0 | The L3 Interconnect converts AHB-lite write
5491  * : | | bursts to AXI transactions in accordance with
5492  * : | | the default behavior as specified in the ARM
5493  * : | | NIC-301 documentation.
5494  * ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES | 0x1 | The L3 Interconnect converts AHB-lite write
5495  * : | | bursts to AXI single transactions.
5496  *
5497  * Field Access Macros:
5498  *
5499  */
5500 /*
5501  * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
5502  *
5503  * The L3 Interconnect converts AHB-lite write bursts to AXI transactions in
5504  * accordance with the default behavior as specified in the ARM NIC-301
5505  * documentation.
5506  */
5507 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_DEFAULT 0x0
5508 /*
5509  * Enumerated value for register field ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE
5510  *
5511  * The L3 Interconnect converts AHB-lite write bursts to AXI single transactions.
5512  */
5513 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_E_SINGLES 0x1
5514 
5515 /* The Least Significant Bit (LSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5516 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_LSB 1
5517 /* The Most Significant Bit (MSB) position of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5518 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_MSB 1
5519 /* The width in bits of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5520 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_WIDTH 1
5521 /* The mask used to set the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
5522 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET_MSK 0x00000002
5523 /* The mask used to clear the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value. */
5524 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_CLR_MSK 0xfffffffd
5525 /* The reset value of the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field. */
5526 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_RESET 0x0
5527 /* Extracts the ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE field value from a register. */
5528 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_GET(value) (((value) & 0x00000002) >> 1)
5529 /* Produces a ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE register field value suitable for setting the register. */
5530 #define ALT_L3_FN_MOD_AHB_WR_INCR_OVERRIDE_SET(value) (((value) << 1) & 0x00000002)
5531 
5532 #ifndef __ASSEMBLY__
5533 /*
5534  * WARNING: The C register and register group struct declarations are provided for
5535  * convenience and illustrative purposes. They should, however, be used with
5536  * caution as the C language standard provides no guarantees about the alignment or
5537  * atomicity of device memory accesses. The recommended practice for writing
5538  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5539  * alt_write_word() functions.
5540  *
5541  * The struct declaration for register ALT_L3_FN_MOD_AHB.
5542  */
5543 struct ALT_L3_FN_MOD_AHB_s
5544 {
5545  uint32_t rd_incr_override : 1; /* Read Increment Override */
5546  uint32_t wr_incr_override : 1; /* Write Increment Override */
5547  uint32_t : 30; /* *UNDEFINED* */
5548 };
5549 
5550 /* The typedef declaration for register ALT_L3_FN_MOD_AHB. */
5551 typedef volatile struct ALT_L3_FN_MOD_AHB_s ALT_L3_FN_MOD_AHB_t;
5552 #endif /* __ASSEMBLY__ */
5553 
5554 /* The byte offset of the ALT_L3_FN_MOD_AHB register from the beginning of the component. */
5555 #define ALT_L3_FN_MOD_AHB_OFST 0x28
5556 /* The address of the ALT_L3_FN_MOD_AHB register. */
5557 #define ALT_L3_FN_MOD_AHB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_FN_MOD_AHB_OFST))
5558 
5559 /*
5560  * Register : Read Channel QoS Value - read_qos
5561  *
5562  * QoS (Quality of Service) value for the read channel.
5563  *
5564  * Register Layout
5565  *
5566  * Bits | Access | Reset | Description
5567  * :-------|:-------|:------|:------------
5568  * [3:0] | RW | 0x0 | Priority
5569  * [31:4] | ??? | 0x0 | *UNDEFINED*
5570  *
5571  */
5572 /*
5573  * Field : Priority - pri
5574  *
5575  * QoS (Quality of Service) value for the read channel. A higher value has a higher
5576  * priority.
5577  *
5578  * Field Access Macros:
5579  *
5580  */
5581 /* The Least Significant Bit (LSB) position of the ALT_L3_RD_QOS_PRI register field. */
5582 #define ALT_L3_RD_QOS_PRI_LSB 0
5583 /* The Most Significant Bit (MSB) position of the ALT_L3_RD_QOS_PRI register field. */
5584 #define ALT_L3_RD_QOS_PRI_MSB 3
5585 /* The width in bits of the ALT_L3_RD_QOS_PRI register field. */
5586 #define ALT_L3_RD_QOS_PRI_WIDTH 4
5587 /* The mask used to set the ALT_L3_RD_QOS_PRI register field value. */
5588 #define ALT_L3_RD_QOS_PRI_SET_MSK 0x0000000f
5589 /* The mask used to clear the ALT_L3_RD_QOS_PRI register field value. */
5590 #define ALT_L3_RD_QOS_PRI_CLR_MSK 0xfffffff0
5591 /* The reset value of the ALT_L3_RD_QOS_PRI register field. */
5592 #define ALT_L3_RD_QOS_PRI_RESET 0x0
5593 /* Extracts the ALT_L3_RD_QOS_PRI field value from a register. */
5594 #define ALT_L3_RD_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
5595 /* Produces a ALT_L3_RD_QOS_PRI register field value suitable for setting the register. */
5596 #define ALT_L3_RD_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
5597 
5598 #ifndef __ASSEMBLY__
5599 /*
5600  * WARNING: The C register and register group struct declarations are provided for
5601  * convenience and illustrative purposes. They should, however, be used with
5602  * caution as the C language standard provides no guarantees about the alignment or
5603  * atomicity of device memory accesses. The recommended practice for writing
5604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5605  * alt_write_word() functions.
5606  *
5607  * The struct declaration for register ALT_L3_RD_QOS.
5608  */
5609 struct ALT_L3_RD_QOS_s
5610 {
5611  uint32_t pri : 4; /* Priority */
5612  uint32_t : 28; /* *UNDEFINED* */
5613 };
5614 
5615 /* The typedef declaration for register ALT_L3_RD_QOS. */
5616 typedef volatile struct ALT_L3_RD_QOS_s ALT_L3_RD_QOS_t;
5617 #endif /* __ASSEMBLY__ */
5618 
5619 /* The byte offset of the ALT_L3_RD_QOS register from the beginning of the component. */
5620 #define ALT_L3_RD_QOS_OFST 0x100
5621 /* The address of the ALT_L3_RD_QOS register. */
5622 #define ALT_L3_RD_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_RD_QOS_OFST))
5623 
5624 /*
5625  * Register : Write Channel QoS Value - write_qos
5626  *
5627  * QoS (Quality of Service) value for the write channel.
5628  *
5629  * Register Layout
5630  *
5631  * Bits | Access | Reset | Description
5632  * :-------|:-------|:------|:------------
5633  * [3:0] | RW | 0x0 | Priority
5634  * [31:4] | ??? | 0x0 | *UNDEFINED*
5635  *
5636  */
5637 /*
5638  * Field : Priority - pri
5639  *
5640  * QoS (Quality of Service) value for the write channel. A higher value has a
5641  * higher priority.
5642  *
5643  * Field Access Macros:
5644  *
5645  */
5646 /* The Least Significant Bit (LSB) position of the ALT_L3_WR_QOS_PRI register field. */
5647 #define ALT_L3_WR_QOS_PRI_LSB 0
5648 /* The Most Significant Bit (MSB) position of the ALT_L3_WR_QOS_PRI register field. */
5649 #define ALT_L3_WR_QOS_PRI_MSB 3
5650 /* The width in bits of the ALT_L3_WR_QOS_PRI register field. */
5651 #define ALT_L3_WR_QOS_PRI_WIDTH 4
5652 /* The mask used to set the ALT_L3_WR_QOS_PRI register field value. */
5653 #define ALT_L3_WR_QOS_PRI_SET_MSK 0x0000000f
5654 /* The mask used to clear the ALT_L3_WR_QOS_PRI register field value. */
5655 #define ALT_L3_WR_QOS_PRI_CLR_MSK 0xfffffff0
5656 /* The reset value of the ALT_L3_WR_QOS_PRI register field. */
5657 #define ALT_L3_WR_QOS_PRI_RESET 0x0
5658 /* Extracts the ALT_L3_WR_QOS_PRI field value from a register. */
5659 #define ALT_L3_WR_QOS_PRI_GET(value) (((value) & 0x0000000f) >> 0)
5660 /* Produces a ALT_L3_WR_QOS_PRI register field value suitable for setting the register. */
5661 #define ALT_L3_WR_QOS_PRI_SET(value) (((value) << 0) & 0x0000000f)
5662 
5663 #ifndef __ASSEMBLY__
5664 /*
5665  * WARNING: The C register and register group struct declarations are provided for
5666  * convenience and illustrative purposes. They should, however, be used with
5667  * caution as the C language standard provides no guarantees about the alignment or
5668  * atomicity of device memory accesses. The recommended practice for writing
5669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5670  * alt_write_word() functions.
5671  *
5672  * The struct declaration for register ALT_L3_WR_QOS.
5673  */
5674 struct ALT_L3_WR_QOS_s
5675 {
5676  uint32_t pri : 4; /* Priority */
5677  uint32_t : 28; /* *UNDEFINED* */
5678 };
5679 
5680 /* The typedef declaration for register ALT_L3_WR_QOS. */
5681 typedef volatile struct ALT_L3_WR_QOS_s ALT_L3_WR_QOS_t;
5682 #endif /* __ASSEMBLY__ */
5683 
5684 /* The byte offset of the ALT_L3_WR_QOS register from the beginning of the component. */
5685 #define ALT_L3_WR_QOS_OFST 0x104
5686 /* The address of the ALT_L3_WR_QOS register. */
5687 #define ALT_L3_WR_QOS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L3_WR_QOS_OFST))
5688 
5689 #ifndef __ASSEMBLY__
5690 /*
5691  * WARNING: The C register and register group struct declarations are provided for
5692  * convenience and illustrative purposes. They should, however, be used with
5693  * caution as the C language standard provides no guarantees about the alignment or
5694  * atomicity of device memory accesses. The recommended practice for writing
5695  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5696  * alt_write_word() functions.
5697  *
5698  * The struct declaration for register group ALT_L3_SLV_DAP.
5699  */
5700 struct ALT_L3_SLV_DAP_s
5701 {
5702  volatile uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */
5703  ALT_L3_FN_MOD2_t fn_mod2; /* ALT_L3_FN_MOD2 */
5704  ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5705  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5706  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5707  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5708  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5709 };
5710 
5711 /* The typedef declaration for register group ALT_L3_SLV_DAP. */
5712 typedef volatile struct ALT_L3_SLV_DAP_s ALT_L3_SLV_DAP_t;
5713 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
5714 struct ALT_L3_SLV_DAP_raw_s
5715 {
5716  uint32_t _pad_0x0_0x23[9]; /* *UNDEFINED* */
5717  volatile uint32_t fn_mod2; /* ALT_L3_FN_MOD2 */
5718  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5719  uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5720  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5721  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5722  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5723 };
5724 
5725 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DAP. */
5726 typedef volatile struct ALT_L3_SLV_DAP_raw_s ALT_L3_SLV_DAP_raw_t;
5727 #endif /* __ASSEMBLY__ */
5728 
5729 
5730 /*
5731  * Register Group : MPU - ALT_L3_SLV_MPU
5732  * MPU
5733  *
5734  * Registers associated with the MPU slave interface. This slave is used by the MPU
5735  * to access slaves attached to the L3/L4 Interconnect.
5736  *
5737  */
5738 #ifndef __ASSEMBLY__
5739 /*
5740  * WARNING: The C register and register group struct declarations are provided for
5741  * convenience and illustrative purposes. They should, however, be used with
5742  * caution as the C language standard provides no guarantees about the alignment or
5743  * atomicity of device memory accesses. The recommended practice for writing
5744  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5745  * alt_write_word() functions.
5746  *
5747  * The struct declaration for register group ALT_L3_SLV_MPU.
5748  */
5749 struct ALT_L3_SLV_MPU_s
5750 {
5751  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5752  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5753  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5754  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5755 };
5756 
5757 /* The typedef declaration for register group ALT_L3_SLV_MPU. */
5758 typedef volatile struct ALT_L3_SLV_MPU_s ALT_L3_SLV_MPU_t;
5759 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
5760 struct ALT_L3_SLV_MPU_raw_s
5761 {
5762  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5763  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5764  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5765  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5766 };
5767 
5768 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_MPU. */
5769 typedef volatile struct ALT_L3_SLV_MPU_raw_s ALT_L3_SLV_MPU_raw_t;
5770 #endif /* __ASSEMBLY__ */
5771 
5772 
5773 /*
5774  * Register Group : SDMMC - ALT_L3_SLV_SDMMC
5775  * SDMMC
5776  *
5777  * Registers associated with the SDMMC slave interface. This slave is used by the
5778  * DMA controller built into the SDMMC to access slaves attached to the L3/L4
5779  * Interconnect.
5780  *
5781  */
5782 #ifndef __ASSEMBLY__
5783 /*
5784  * WARNING: The C register and register group struct declarations are provided for
5785  * convenience and illustrative purposes. They should, however, be used with
5786  * caution as the C language standard provides no guarantees about the alignment or
5787  * atomicity of device memory accesses. The recommended practice for writing
5788  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5789  * alt_write_word() functions.
5790  *
5791  * The struct declaration for register group ALT_L3_SLV_SDMMC.
5792  */
5793 struct ALT_L3_SLV_SDMMC_s
5794 {
5795  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
5796  ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5797  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5798  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5799  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5800  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5801 };
5802 
5803 /* The typedef declaration for register group ALT_L3_SLV_SDMMC. */
5804 typedef volatile struct ALT_L3_SLV_SDMMC_s ALT_L3_SLV_SDMMC_t;
5805 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
5806 struct ALT_L3_SLV_SDMMC_raw_s
5807 {
5808  uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
5809  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
5810  uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
5811  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5812  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5813  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5814 };
5815 
5816 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_SDMMC. */
5817 typedef volatile struct ALT_L3_SLV_SDMMC_raw_s ALT_L3_SLV_SDMMC_raw_t;
5818 #endif /* __ASSEMBLY__ */
5819 
5820 
5821 /*
5822  * Register Group : DMA - ALT_L3_SLV_DMA
5823  * DMA
5824  *
5825  * Registers associated with the DMA Controller slave interface. This slave is used
5826  * by the DMA Controller to access slaves attached to the L3/L4 Interconnect.
5827  *
5828  */
5829 #ifndef __ASSEMBLY__
5830 /*
5831  * WARNING: The C register and register group struct declarations are provided for
5832  * convenience and illustrative purposes. They should, however, be used with
5833  * caution as the C language standard provides no guarantees about the alignment or
5834  * atomicity of device memory accesses. The recommended practice for writing
5835  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5836  * alt_write_word() functions.
5837  *
5838  * The struct declaration for register group ALT_L3_SLV_DMA.
5839  */
5840 struct ALT_L3_SLV_DMA_s
5841 {
5842  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5843  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5844  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5845  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5846 };
5847 
5848 /* The typedef declaration for register group ALT_L3_SLV_DMA. */
5849 typedef volatile struct ALT_L3_SLV_DMA_s ALT_L3_SLV_DMA_t;
5850 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
5851 struct ALT_L3_SLV_DMA_raw_s
5852 {
5853  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5854  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5855  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5856  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5857 };
5858 
5859 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_DMA. */
5860 typedef volatile struct ALT_L3_SLV_DMA_raw_s ALT_L3_SLV_DMA_raw_t;
5861 #endif /* __ASSEMBLY__ */
5862 
5863 
5864 /*
5865  * Register Group : FPGA2HPS - ALT_L3_SLV_F2H
5866  * FPGA2HPS
5867  *
5868  * Registers associated with the FPGA2HPS AXI Bridge slave interface. This slave is
5869  * used by the FPGA2HPS AXI Bridge to access slaves attached to the L3/L4
5870  * Interconnect.
5871  *
5872  */
5873 #ifndef __ASSEMBLY__
5874 /*
5875  * WARNING: The C register and register group struct declarations are provided for
5876  * convenience and illustrative purposes. They should, however, be used with
5877  * caution as the C language standard provides no guarantees about the alignment or
5878  * atomicity of device memory accesses. The recommended practice for writing
5879  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5880  * alt_write_word() functions.
5881  *
5882  * The struct declaration for register group ALT_L3_SLV_F2H.
5883  */
5884 struct ALT_L3_SLV_F2H_s
5885 {
5886  volatile uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */
5887  ALT_L3_WR_TIDEMARK_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5888  volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
5889  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5890  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5891  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5892 };
5893 
5894 /* The typedef declaration for register group ALT_L3_SLV_F2H. */
5895 typedef volatile struct ALT_L3_SLV_F2H_s ALT_L3_SLV_F2H_t;
5896 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
5897 struct ALT_L3_SLV_F2H_raw_s
5898 {
5899  uint32_t _pad_0x0_0x3f[16]; /* *UNDEFINED* */
5900  volatile uint32_t wr_tidemark; /* ALT_L3_WR_TIDEMARK */
5901  uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
5902  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5903  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5904  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5905 };
5906 
5907 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_F2H. */
5908 typedef volatile struct ALT_L3_SLV_F2H_raw_s ALT_L3_SLV_F2H_raw_t;
5909 #endif /* __ASSEMBLY__ */
5910 
5911 
5912 /*
5913  * Register Group : ETR - ALT_L3_SLV_ETR
5914  * ETR
5915  *
5916  * Registers associated with the ETR (TMC) slave interface. This slave is used by
5917  * the ETR to access slaves attached to the L3/L4 Interconnect.
5918  *
5919  */
5920 #ifndef __ASSEMBLY__
5921 /*
5922  * WARNING: The C register and register group struct declarations are provided for
5923  * convenience and illustrative purposes. They should, however, be used with
5924  * caution as the C language standard provides no guarantees about the alignment or
5925  * atomicity of device memory accesses. The recommended practice for writing
5926  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5927  * alt_write_word() functions.
5928  *
5929  * The struct declaration for register group ALT_L3_SLV_ETR.
5930  */
5931 struct ALT_L3_SLV_ETR_s
5932 {
5933  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5934  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5935  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5936  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5937 };
5938 
5939 /* The typedef declaration for register group ALT_L3_SLV_ETR. */
5940 typedef volatile struct ALT_L3_SLV_ETR_s ALT_L3_SLV_ETR_t;
5941 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
5942 struct ALT_L3_SLV_ETR_raw_s
5943 {
5944  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5945  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5946  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5947  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5948 };
5949 
5950 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_ETR. */
5951 typedef volatile struct ALT_L3_SLV_ETR_raw_s ALT_L3_SLV_ETR_raw_t;
5952 #endif /* __ASSEMBLY__ */
5953 
5954 
5955 /*
5956  * Register Group : EMAC0 - ALT_L3_SLV_EMAC0
5957  * EMAC0
5958  *
5959  * Registers associated with the EMAC0 slave interface. This slave is used by the
5960  * DMA controller built into the EMAC0 to access slaves attached to the L3/L4
5961  * Interconnect.
5962  *
5963  */
5964 #ifndef __ASSEMBLY__
5965 /*
5966  * WARNING: The C register and register group struct declarations are provided for
5967  * convenience and illustrative purposes. They should, however, be used with
5968  * caution as the C language standard provides no guarantees about the alignment or
5969  * atomicity of device memory accesses. The recommended practice for writing
5970  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5971  * alt_write_word() functions.
5972  *
5973  * The struct declaration for register group ALT_L3_SLV_EMAC0.
5974  */
5975 struct ALT_L3_SLV_EMAC0_s
5976 {
5977  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5978  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
5979  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
5980  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
5981 };
5982 
5983 /* The typedef declaration for register group ALT_L3_SLV_EMAC0. */
5984 typedef volatile struct ALT_L3_SLV_EMAC0_s ALT_L3_SLV_EMAC0_t;
5985 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
5986 struct ALT_L3_SLV_EMAC0_raw_s
5987 {
5988  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
5989  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
5990  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
5991  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
5992 };
5993 
5994 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC0. */
5995 typedef volatile struct ALT_L3_SLV_EMAC0_raw_s ALT_L3_SLV_EMAC0_raw_t;
5996 #endif /* __ASSEMBLY__ */
5997 
5998 
5999 /*
6000  * Register Group : EMAC1 - ALT_L3_SLV_EMAC1
6001  * EMAC1
6002  *
6003  * Registers associated with the EMAC1 slave interface. This slave is used by the
6004  * DMA controller built into the EMAC1 to access slaves attached to the L3/L4
6005  * Interconnect.
6006  *
6007  */
6008 #ifndef __ASSEMBLY__
6009 /*
6010  * WARNING: The C register and register group struct declarations are provided for
6011  * convenience and illustrative purposes. They should, however, be used with
6012  * caution as the C language standard provides no guarantees about the alignment or
6013  * atomicity of device memory accesses. The recommended practice for writing
6014  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6015  * alt_write_word() functions.
6016  *
6017  * The struct declaration for register group ALT_L3_SLV_EMAC1.
6018  */
6019 struct ALT_L3_SLV_EMAC1_s
6020 {
6021  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6022  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6023  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6024  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6025 };
6026 
6027 /* The typedef declaration for register group ALT_L3_SLV_EMAC1. */
6028 typedef volatile struct ALT_L3_SLV_EMAC1_s ALT_L3_SLV_EMAC1_t;
6029 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
6030 struct ALT_L3_SLV_EMAC1_raw_s
6031 {
6032  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6033  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6034  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6035  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6036 };
6037 
6038 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_EMAC1. */
6039 typedef volatile struct ALT_L3_SLV_EMAC1_raw_s ALT_L3_SLV_EMAC1_raw_t;
6040 #endif /* __ASSEMBLY__ */
6041 
6042 
6043 /*
6044  * Register Group : USB0 - ALT_L3_SLV_USB0
6045  * USB0
6046  *
6047  * Registers associated with the USB0 slave interface. This slave is used by the
6048  * DMA controller built into the USB0 to access slaves attached to the L3/L4
6049  * Interconnect.
6050  *
6051  */
6052 #ifndef __ASSEMBLY__
6053 /*
6054  * WARNING: The C register and register group struct declarations are provided for
6055  * convenience and illustrative purposes. They should, however, be used with
6056  * caution as the C language standard provides no guarantees about the alignment or
6057  * atomicity of device memory accesses. The recommended practice for writing
6058  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6059  * alt_write_word() functions.
6060  *
6061  * The struct declaration for register group ALT_L3_SLV_USB0.
6062  */
6063 struct ALT_L3_SLV_USB0_s
6064 {
6065  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6066  ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6067  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6068  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6069  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6070  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6071 };
6072 
6073 /* The typedef declaration for register group ALT_L3_SLV_USB0. */
6074 typedef volatile struct ALT_L3_SLV_USB0_s ALT_L3_SLV_USB0_t;
6075 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
6076 struct ALT_L3_SLV_USB0_raw_s
6077 {
6078  uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6079  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6080  uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6081  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6082  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6083  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6084 };
6085 
6086 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB0. */
6087 typedef volatile struct ALT_L3_SLV_USB0_raw_s ALT_L3_SLV_USB0_raw_t;
6088 #endif /* __ASSEMBLY__ */
6089 
6090 
6091 /*
6092  * Register Group : NAND - ALT_L3_SLV_NAND
6093  * NAND
6094  *
6095  * Registers associated with the NAND slave interface. This slave is used by the
6096  * DMA controller built into the NAND flash controller to access slaves attached to
6097  * the L3/L4 Interconnect.
6098  *
6099  */
6100 #ifndef __ASSEMBLY__
6101 /*
6102  * WARNING: The C register and register group struct declarations are provided for
6103  * convenience and illustrative purposes. They should, however, be used with
6104  * caution as the C language standard provides no guarantees about the alignment or
6105  * atomicity of device memory accesses. The recommended practice for writing
6106  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6107  * alt_write_word() functions.
6108  *
6109  * The struct declaration for register group ALT_L3_SLV_NAND.
6110  */
6111 struct ALT_L3_SLV_NAND_s
6112 {
6113  volatile uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6114  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6115  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6116  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6117 };
6118 
6119 /* The typedef declaration for register group ALT_L3_SLV_NAND. */
6120 typedef volatile struct ALT_L3_SLV_NAND_s ALT_L3_SLV_NAND_t;
6121 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
6122 struct ALT_L3_SLV_NAND_raw_s
6123 {
6124  uint32_t _pad_0x0_0xff[64]; /* *UNDEFINED* */
6125  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6126  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6127  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6128 };
6129 
6130 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_NAND. */
6131 typedef volatile struct ALT_L3_SLV_NAND_raw_s ALT_L3_SLV_NAND_raw_t;
6132 #endif /* __ASSEMBLY__ */
6133 
6134 
6135 /*
6136  * Register Group : USB1 - ALT_L3_SLV_USB1
6137  * USB1
6138  *
6139  * Registers associated with the USB1 slave interface. This slave is used by the
6140  * DMA controller built into the USB1 to access slaves attached to the L3/L4
6141  * Interconnect.
6142  *
6143  */
6144 #ifndef __ASSEMBLY__
6145 /*
6146  * WARNING: The C register and register group struct declarations are provided for
6147  * convenience and illustrative purposes. They should, however, be used with
6148  * caution as the C language standard provides no guarantees about the alignment or
6149  * atomicity of device memory accesses. The recommended practice for writing
6150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6151  * alt_write_word() functions.
6152  *
6153  * The struct declaration for register group ALT_L3_SLV_USB1.
6154  */
6155 struct ALT_L3_SLV_USB1_s
6156 {
6157  volatile uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6158  ALT_L3_FN_MOD_AHB_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6159  volatile uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6160  ALT_L3_RD_QOS_t read_qos; /* ALT_L3_RD_QOS */
6161  ALT_L3_WR_QOS_t write_qos; /* ALT_L3_WR_QOS */
6162  ALT_L3_FN_MOD_t fn_mod; /* ALT_L3_FN_MOD */
6163 };
6164 
6165 /* The typedef declaration for register group ALT_L3_SLV_USB1. */
6166 typedef volatile struct ALT_L3_SLV_USB1_s ALT_L3_SLV_USB1_t;
6167 /* The struct declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
6168 struct ALT_L3_SLV_USB1_raw_s
6169 {
6170  uint32_t _pad_0x0_0x27[10]; /* *UNDEFINED* */
6171  volatile uint32_t fn_mod_ahb; /* ALT_L3_FN_MOD_AHB */
6172  uint32_t _pad_0x2c_0xff[53]; /* *UNDEFINED* */
6173  volatile uint32_t read_qos; /* ALT_L3_RD_QOS */
6174  volatile uint32_t write_qos; /* ALT_L3_WR_QOS */
6175  volatile uint32_t fn_mod; /* ALT_L3_FN_MOD */
6176 };
6177 
6178 /* The typedef declaration for the raw register contents of register group ALT_L3_SLV_USB1. */
6179 typedef volatile struct ALT_L3_SLV_USB1_raw_s ALT_L3_SLV_USB1_raw_t;
6180 #endif /* __ASSEMBLY__ */
6181 
6182 
6183 #ifndef __ASSEMBLY__
6184 /*
6185  * WARNING: The C register and register group struct declarations are provided for
6186  * convenience and illustrative purposes. They should, however, be used with
6187  * caution as the C language standard provides no guarantees about the alignment or
6188  * atomicity of device memory accesses. The recommended practice for writing
6189  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6190  * alt_write_word() functions.
6191  *
6192  * The struct declaration for register group ALT_L3_SLVGRP.
6193  */
6194 struct ALT_L3_SLVGRP_s
6195 {
6196  ALT_L3_SLV_DAP_t slavegrp_dap; /* ALT_L3_SLV_DAP */
6197  volatile uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */
6198  ALT_L3_SLV_MPU_t slavegrp_mpu; /* ALT_L3_SLV_MPU */
6199  volatile uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */
6200  ALT_L3_SLV_SDMMC_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */
6201  volatile uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */
6202  ALT_L3_SLV_DMA_t slavegrp_dma; /* ALT_L3_SLV_DMA */
6203  volatile uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */
6204  ALT_L3_SLV_F2H_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */
6205  volatile uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */
6206  ALT_L3_SLV_ETR_t slavegrp_etr; /* ALT_L3_SLV_ETR */
6207  volatile uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
6208  ALT_L3_SLV_EMAC0_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */
6209  volatile uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */
6210  ALT_L3_SLV_EMAC1_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */
6211  volatile uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */
6212  ALT_L3_SLV_USB0_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */
6213  volatile uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */
6214  ALT_L3_SLV_NAND_t slavegrp_nand; /* ALT_L3_SLV_NAND */
6215  volatile uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */
6216  ALT_L3_SLV_USB1_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */
6217 };
6218 
6219 /* The typedef declaration for register group ALT_L3_SLVGRP. */
6220 typedef volatile struct ALT_L3_SLVGRP_s ALT_L3_SLVGRP_t;
6221 /* The struct declaration for the raw register contents of register group ALT_L3_SLVGRP. */
6222 struct ALT_L3_SLVGRP_raw_s
6223 {
6224  ALT_L3_SLV_DAP_raw_t slavegrp_dap; /* ALT_L3_SLV_DAP */
6225  uint32_t _pad_0x10c_0xfff[957]; /* *UNDEFINED* */
6226  ALT_L3_SLV_MPU_raw_t slavegrp_mpu; /* ALT_L3_SLV_MPU */
6227  uint32_t _pad_0x110c_0x1fff[957]; /* *UNDEFINED* */
6228  ALT_L3_SLV_SDMMC_raw_t slavegrp_sdmmc; /* ALT_L3_SLV_SDMMC */
6229  uint32_t _pad_0x210c_0x2fff[957]; /* *UNDEFINED* */
6230  ALT_L3_SLV_DMA_raw_t slavegrp_dma; /* ALT_L3_SLV_DMA */
6231  uint32_t _pad_0x310c_0x3fff[957]; /* *UNDEFINED* */
6232  ALT_L3_SLV_F2H_raw_t slavegrp_fpga2hps; /* ALT_L3_SLV_F2H */
6233  uint32_t _pad_0x410c_0x4fff[957]; /* *UNDEFINED* */
6234  ALT_L3_SLV_ETR_raw_t slavegrp_etr; /* ALT_L3_SLV_ETR */
6235  uint32_t _pad_0x510c_0x5fff[957]; /* *UNDEFINED* */
6236  ALT_L3_SLV_EMAC0_raw_t slavegrp_emac0; /* ALT_L3_SLV_EMAC0 */
6237  uint32_t _pad_0x610c_0x6fff[957]; /* *UNDEFINED* */
6238  ALT_L3_SLV_EMAC1_raw_t slavegrp_emac1; /* ALT_L3_SLV_EMAC1 */
6239  uint32_t _pad_0x710c_0x7fff[957]; /* *UNDEFINED* */
6240  ALT_L3_SLV_USB0_raw_t slavegrp_usb0; /* ALT_L3_SLV_USB0 */
6241  uint32_t _pad_0x810c_0x8fff[957]; /* *UNDEFINED* */
6242  ALT_L3_SLV_NAND_raw_t slavegrp_nand; /* ALT_L3_SLV_NAND */
6243  uint32_t _pad_0x910c_0x9fff[957]; /* *UNDEFINED* */
6244  ALT_L3_SLV_USB1_raw_t slavegrp_usb1; /* ALT_L3_SLV_USB1 */
6245 };
6246 
6247 /* The typedef declaration for the raw register contents of register group ALT_L3_SLVGRP. */
6248 typedef volatile struct ALT_L3_SLVGRP_raw_s ALT_L3_SLVGRP_raw_t;
6249 #endif /* __ASSEMBLY__ */
6250 
6251 
6252 #ifndef __ASSEMBLY__
6253 /*
6254  * WARNING: The C register and register group struct declarations are provided for
6255  * convenience and illustrative purposes. They should, however, be used with
6256  * caution as the C language standard provides no guarantees about the alignment or
6257  * atomicity of device memory accesses. The recommended practice for writing
6258  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6259  * alt_write_word() functions.
6260  *
6261  * The struct declaration for register group ALT_L3.
6262  */
6263 struct ALT_L3_s
6264 {
6265  ALT_L3_REMAP_t remap; /* ALT_L3_REMAP */
6266  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
6267  ALT_L3_SECGRP_t secgrp; /* ALT_L3_SECGRP */
6268  volatile uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */
6269  ALT_L3_IDGRP_t idgrp; /* ALT_L3_IDGRP */
6270  ALT_L3_MSTGRP_t mastergrp; /* ALT_L3_MSTGRP */
6271  volatile uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */
6272  ALT_L3_SLVGRP_t slavegrp; /* ALT_L3_SLVGRP */
6273  volatile uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */
6274 };
6275 
6276 /* The typedef declaration for register group ALT_L3. */
6277 typedef volatile struct ALT_L3_s ALT_L3_t;
6278 /* The struct declaration for the raw register contents of register group ALT_L3. */
6279 struct ALT_L3_raw_s
6280 {
6281  volatile uint32_t remap; /* ALT_L3_REMAP */
6282  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
6283  ALT_L3_SECGRP_raw_t secgrp; /* ALT_L3_SECGRP */
6284  uint32_t _pad_0xa4_0xfff[983]; /* *UNDEFINED* */
6285  ALT_L3_IDGRP_raw_t idgrp; /* ALT_L3_IDGRP */
6286  ALT_L3_MSTGRP_raw_t mastergrp; /* ALT_L3_MSTGRP */
6287  uint32_t _pad_0x2710c_0x41fff[27581]; /* *UNDEFINED* */
6288  ALT_L3_SLVGRP_raw_t slavegrp; /* ALT_L3_SLVGRP */
6289  uint32_t _pad_0x4c10c_0x80000[53181]; /* *UNDEFINED* */
6290 };
6291 
6292 /* The typedef declaration for the raw register contents of register group ALT_L3. */
6293 typedef volatile struct ALT_L3_raw_s ALT_L3_raw_t;
6294 #endif /* __ASSEMBLY__ */
6295 
6296 
6297 #ifdef __cplusplus
6298 }
6299 #endif /* __cplusplus */
6300 #endif /* __ALTERA_ALT_L3_H__ */
6301