35 #ifndef __ALTERA_ALT_SDR_H__
36 #define __ALTERA_ALT_SDR_H__
96 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0
98 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2
100 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3
102 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007
104 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8
106 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0
108 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0)
110 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007)
126 #define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3
128 #define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7
130 #define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5
132 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8
134 #define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07
136 #define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0
138 #define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3)
140 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8)
155 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8
157 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9
159 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2
161 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300
163 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff
165 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0
167 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8)
169 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300)
182 #define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10
184 #define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10
186 #define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1
188 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400
190 #define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff
192 #define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0
194 #define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10)
196 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400)
208 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11
210 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11
212 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1
214 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800
216 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff
218 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0
220 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11)
222 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800)
235 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12
237 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12
239 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1
241 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000
243 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff
245 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0
247 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12)
249 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000)
261 #define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13
263 #define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13
265 #define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1
267 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000
269 #define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff
271 #define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0
273 #define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13)
275 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000)
287 #define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14
289 #define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14
291 #define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1
293 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000
295 #define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff
297 #define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0
299 #define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14)
301 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000)
313 #define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15
315 #define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15
317 #define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1
319 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000
321 #define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff
323 #define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0
325 #define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15)
327 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000)
340 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16
342 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21
344 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6
346 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000
348 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff
350 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0
352 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16)
354 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000)
365 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22
367 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22
369 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1
371 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000
373 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff
375 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0
377 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22)
379 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000)
390 #define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23
392 #define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23
394 #define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1
396 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000
398 #define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff
400 #define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0
402 #define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23)
404 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000)
416 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24
418 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24
420 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1
422 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000
424 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff
426 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0
428 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24)
430 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000)
442 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25
444 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25
446 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1
448 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000
450 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff
452 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0
454 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25)
456 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000)
469 struct ALT_SDR_CTL_CTLCFG_s
471 uint32_t memtype : 3;
473 uint32_t addrorder : 2;
475 uint32_t ecccorren : 1;
476 uint32_t cfg_enable_ecc_code_overwrites : 1;
479 uint32_t reorderen : 1;
480 uint32_t starvelimit : 6;
481 uint32_t dqstrken : 1;
482 uint32_t nodmpins : 1;
483 uint32_t burstintren : 1;
484 uint32_t bursttermen : 1;
489 typedef volatile struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t;
493 #define ALT_SDR_CTL_CTLCFG_OFST 0x0
522 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0
524 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3
526 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4
528 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f
530 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0
532 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0
534 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0)
536 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f)
547 #define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4
549 #define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8
551 #define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5
553 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0
555 #define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f
557 #define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0
559 #define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4)
561 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0)
572 #define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9
574 #define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13
576 #define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5
578 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00
580 #define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff
582 #define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0
584 #define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9)
586 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00)
597 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14
599 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17
601 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4
603 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000
605 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff
607 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0
609 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14)
611 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000)
622 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18
624 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23
626 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6
628 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000
630 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff
632 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0
634 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18)
636 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000)
647 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24
649 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31
651 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8
653 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000
655 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff
657 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0
659 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24)
661 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000)
674 struct ALT_SDR_CTL_DRAMTIMING1_s
685 typedef volatile struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t;
689 #define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4
718 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0
720 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12
722 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13
724 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff
726 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000
728 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0
730 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0)
732 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff)
743 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13
745 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16
747 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4
749 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000
751 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff
753 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0
755 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13)
757 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000)
768 #define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17
770 #define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20
772 #define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4
774 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000
776 #define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff
778 #define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0
780 #define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17)
782 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000)
793 #define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21
795 #define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24
797 #define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4
799 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000
801 #define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff
803 #define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0
805 #define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21)
807 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000)
818 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25
820 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28
822 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4
824 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000
826 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff
828 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0
830 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25)
832 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000)
845 struct ALT_SDR_CTL_DRAMTIMING2_s
856 typedef volatile struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t;
860 #define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8
889 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0
891 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3
893 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4
895 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f
897 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0
899 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0
901 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0)
903 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f)
914 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4
916 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8
918 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5
920 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0
922 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f
924 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0
926 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4)
928 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0)
939 #define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9
941 #define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14
943 #define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6
945 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00
947 #define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff
949 #define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0
951 #define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9)
953 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00)
964 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15
966 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18
968 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4
970 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000
972 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff
974 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0
976 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15)
978 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000)
989 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19
991 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22
993 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4
995 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000
997 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff
999 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0
1001 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19)
1003 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000)
1005 #ifndef __ASSEMBLY__
1016 struct ALT_SDR_CTL_DRAMTIMING3_s
1027 typedef volatile struct ALT_SDR_CTL_DRAMTIMING3_s ALT_SDR_CTL_DRAMTIMING3_t;
1031 #define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc
1058 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0
1060 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9
1062 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10
1064 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff
1066 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00
1068 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0
1070 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0)
1072 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff)
1083 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10
1085 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19
1087 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10
1089 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00
1091 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff
1093 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0
1095 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10)
1097 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00)
1109 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
1111 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23
1113 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4
1115 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000
1117 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff
1119 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0
1121 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20)
1123 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000)
1125 #ifndef __ASSEMBLY__
1136 struct ALT_SDR_CTL_DRAMTIMING4_s
1138 uint32_t selfrfshexit : 10;
1139 uint32_t pwrdownexit : 10;
1140 uint32_t minpwrsavecycles : 4;
1145 typedef volatile struct ALT_SDR_CTL_DRAMTIMING4_s ALT_SDR_CTL_DRAMTIMING4_t;
1149 #define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10
1175 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
1177 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15
1179 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16
1181 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff
1183 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000
1185 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0
1187 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0)
1189 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff)
1202 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16
1204 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19
1206 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4
1208 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000
1210 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff
1212 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0
1214 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16)
1216 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000)
1218 #ifndef __ASSEMBLY__
1229 struct ALT_SDR_CTL_LOWPWRTIMING_s
1231 uint32_t autopdcycles : 16;
1232 uint32_t clkdisablecycles : 4;
1237 typedef volatile struct ALT_SDR_CTL_LOWPWRTIMING_s ALT_SDR_CTL_LOWPWRTIMING_t;
1241 #define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14
1271 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0
1273 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3
1275 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4
1277 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f
1279 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0
1281 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0
1283 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0)
1285 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f)
1296 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4
1298 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7
1300 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4
1302 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0
1304 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f
1306 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0
1308 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4)
1310 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0)
1312 #ifndef __ASSEMBLY__
1323 struct ALT_SDR_CTL_DRAMODT_s
1325 uint32_t cfg_write_odt_chip : 4;
1326 uint32_t cfg_read_odt_chip : 4;
1331 typedef volatile struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t;
1335 #define ALT_SDR_CTL_DRAMODT_OFST 0x18
1364 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0
1366 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4
1368 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5
1370 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f
1372 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0
1374 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0
1376 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0)
1378 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f)
1389 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5
1391 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9
1393 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5
1395 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0
1397 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f
1399 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0
1401 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5)
1403 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0)
1414 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10
1416 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12
1418 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3
1420 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00
1422 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff
1424 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0
1426 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10)
1428 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00)
1440 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13
1442 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15
1444 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3
1446 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000
1448 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff
1450 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0
1452 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13)
1454 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000)
1456 #ifndef __ASSEMBLY__
1467 struct ALT_SDR_CTL_DRAMADDRW_s
1469 uint32_t colbits : 5;
1470 uint32_t rowbits : 5;
1471 uint32_t bankbits : 3;
1472 uint32_t csbits : 3;
1477 typedef volatile struct ALT_SDR_CTL_DRAMADDRW_s ALT_SDR_CTL_DRAMADDRW_t;
1481 #define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c
1506 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0
1508 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7
1510 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8
1512 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff
1514 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00
1516 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0
1518 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0)
1520 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff)
1522 #ifndef __ASSEMBLY__
1533 struct ALT_SDR_CTL_DRAMIFWIDTH_s
1535 uint32_t ifwidth : 8;
1540 typedef volatile struct ALT_SDR_CTL_DRAMIFWIDTH_s ALT_SDR_CTL_DRAMIFWIDTH_t;
1544 #define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30
1568 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0
1570 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3
1572 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4
1574 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f
1576 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0
1578 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0
1580 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
1582 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f)
1584 #ifndef __ASSEMBLY__
1595 struct ALT_SDR_CTL_DRAMDEVWIDTH_s
1597 uint32_t devwidth : 4;
1602 typedef volatile struct ALT_SDR_CTL_DRAMDEVWIDTH_s ALT_SDR_CTL_DRAMDEVWIDTH_t;
1606 #define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34
1634 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0
1636 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0
1638 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1
1640 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001
1642 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe
1644 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0
1646 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0)
1648 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001)
1659 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1
1661 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1
1663 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1
1665 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002
1667 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd
1669 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0
1671 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1)
1673 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002)
1684 #define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2
1686 #define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2
1688 #define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1
1690 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004
1692 #define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb
1694 #define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0
1696 #define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2)
1698 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004)
1709 #define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3
1711 #define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3
1713 #define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1
1715 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008
1717 #define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7
1719 #define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0
1721 #define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3)
1723 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008)
1734 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4
1736 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4
1738 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1
1740 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010
1742 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef
1744 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0
1746 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4)
1748 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010)
1750 #ifndef __ASSEMBLY__
1761 struct ALT_SDR_CTL_DRAMSTS_s
1763 uint32_t calsuccess : 1;
1764 uint32_t calfail : 1;
1765 uint32_t sbeerr : 1;
1766 uint32_t dbeerr : 1;
1767 uint32_t corrdrop : 1;
1772 typedef volatile struct ALT_SDR_CTL_DRAMSTS_s ALT_SDR_CTL_DRAMSTS_t;
1776 #define ALT_SDR_CTL_DRAMSTS_OFST 0x38
1803 #define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0
1805 #define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0
1807 #define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1
1809 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001
1811 #define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe
1813 #define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0
1815 #define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0)
1817 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001)
1828 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1
1830 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1
1832 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1
1834 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002
1836 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd
1838 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0
1840 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1)
1842 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002)
1853 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2
1855 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2
1857 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1
1859 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004
1861 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb
1863 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0
1865 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2)
1867 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004)
1880 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3
1882 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3
1884 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1
1886 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008
1888 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7
1890 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0
1892 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3)
1894 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008)
1906 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4
1908 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4
1910 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1
1912 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010
1914 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef
1916 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0
1918 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4)
1920 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010)
1922 #ifndef __ASSEMBLY__
1933 struct ALT_SDR_CTL_DRAMINTR_s
1935 uint32_t intren : 1;
1936 uint32_t sbemask : 1;
1937 uint32_t dbemask : 1;
1938 uint32_t corrdropmask : 1;
1939 uint32_t intrclr : 1;
1944 typedef volatile struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t;
1948 #define ALT_SDR_CTL_DRAMINTR_OFST 0x3c
1972 #define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0
1974 #define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7
1976 #define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8
1978 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff
1980 #define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00
1982 #define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0
1984 #define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
1986 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
1988 #ifndef __ASSEMBLY__
1999 struct ALT_SDR_CTL_SBECOUNT_s
2006 typedef volatile struct ALT_SDR_CTL_SBECOUNT_s ALT_SDR_CTL_SBECOUNT_t;
2010 #define ALT_SDR_CTL_SBECOUNT_OFST 0x40
2034 #define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0
2036 #define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7
2038 #define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8
2040 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff
2042 #define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00
2044 #define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0
2046 #define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
2048 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
2050 #ifndef __ASSEMBLY__
2061 struct ALT_SDR_CTL_DBECOUNT_s
2068 typedef volatile struct ALT_SDR_CTL_DBECOUNT_s ALT_SDR_CTL_DBECOUNT_t;
2072 #define ALT_SDR_CTL_DBECOUNT_OFST 0x44
2094 #define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0
2096 #define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31
2098 #define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32
2100 #define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff
2102 #define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000
2104 #define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0
2106 #define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2108 #define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2110 #ifndef __ASSEMBLY__
2121 struct ALT_SDR_CTL_ERRADDR_s
2127 typedef volatile struct ALT_SDR_CTL_ERRADDR_s ALT_SDR_CTL_ERRADDR_t;
2131 #define ALT_SDR_CTL_ERRADDR_OFST 0x48
2155 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0
2157 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7
2159 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8
2161 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff
2163 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00
2165 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0
2167 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0)
2169 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff)
2171 #ifndef __ASSEMBLY__
2182 struct ALT_SDR_CTL_DROPCOUNT_s
2184 uint32_t corrdropcount : 8;
2189 typedef volatile struct ALT_SDR_CTL_DROPCOUNT_s ALT_SDR_CTL_DROPCOUNT_t;
2193 #define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c
2215 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0
2217 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31
2219 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32
2221 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff
2223 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000
2225 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0
2227 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0)
2229 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff)
2231 #ifndef __ASSEMBLY__
2242 struct ALT_SDR_CTL_DROPADDR_s
2244 uint32_t corrdropaddr : 32;
2248 typedef volatile struct ALT_SDR_CTL_DROPADDR_s ALT_SDR_CTL_DROPADDR_t;
2252 #define ALT_SDR_CTL_DROPADDR_OFST 0x50
2281 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0
2283 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0
2285 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1
2287 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001
2289 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe
2291 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0
2293 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0)
2295 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001)
2309 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1
2311 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2
2313 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2
2315 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006
2317 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9
2319 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0
2321 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1)
2323 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006)
2337 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3
2339 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3
2341 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1
2343 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008
2345 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7
2347 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0
2349 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3)
2351 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008)
2363 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4
2365 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5
2367 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2
2369 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030
2371 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf
2373 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0
2375 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4)
2377 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030)
2379 #ifndef __ASSEMBLY__
2390 struct ALT_SDR_CTL_LOWPWREQ_s
2392 uint32_t deeppwrdnreq : 1;
2393 uint32_t deeppwrdnmask : 2;
2394 uint32_t selfrshreq : 1;
2395 uint32_t selfrfshmask : 2;
2400 typedef volatile struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t;
2404 #define ALT_SDR_CTL_LOWPWREQ_OFST 0x54
2430 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0
2432 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0
2434 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1
2436 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001
2438 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe
2440 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0
2442 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0)
2444 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001)
2455 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1
2457 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1
2459 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1
2461 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002
2463 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd
2465 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0
2467 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1)
2469 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002)
2471 #ifndef __ASSEMBLY__
2482 struct ALT_SDR_CTL_LOWPWRACK_s
2484 uint32_t deeppwrdnack : 1;
2485 uint32_t selfrfshack : 1;
2490 typedef volatile struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t;
2494 #define ALT_SDR_CTL_LOWPWRACK_OFST 0x58
2529 #define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0
2531 #define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1
2533 #define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2
2535 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003
2537 #define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc
2539 #define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0
2541 #define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0)
2543 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003)
2557 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2
2559 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2
2561 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1
2563 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004
2565 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb
2567 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0
2569 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2)
2571 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004)
2583 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3
2585 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3
2587 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1
2589 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008
2591 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7
2593 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0
2595 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3)
2597 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008)
2599 #ifndef __ASSEMBLY__
2610 struct ALT_SDR_CTL_STATICCFG_s
2613 uint32_t useeccasdata : 1;
2614 uint32_t applycfg : 1;
2619 typedef volatile struct ALT_SDR_CTL_STATICCFG_s ALT_SDR_CTL_STATICCFG_t;
2623 #define ALT_SDR_CTL_STATICCFG_OFST 0x5c
2650 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0
2652 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1
2654 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2
2656 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003
2658 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc
2660 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0
2662 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0)
2664 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003)
2666 #ifndef __ASSEMBLY__
2677 struct ALT_SDR_CTL_CTLWIDTH_s
2679 uint32_t ctrlwidth : 2;
2684 typedef volatile struct ALT_SDR_CTL_CTLWIDTH_s ALT_SDR_CTL_CTLWIDTH_t;
2688 #define ALT_SDR_CTL_CTLWIDTH_OFST 0x60
2719 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10
2721 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19
2723 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10
2725 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00
2727 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff
2729 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0
2731 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10)
2733 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00)
2735 #ifndef __ASSEMBLY__
2746 struct ALT_SDR_CTL_PORTCFG_s
2749 uint32_t autopchen : 10;
2754 typedef volatile struct ALT_SDR_CTL_PORTCFG_s ALT_SDR_CTL_PORTCFG_t;
2758 #define ALT_SDR_CTL_PORTCFG_OFST 0x7c
2790 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0
2792 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13
2794 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14
2796 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff
2798 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000
2800 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0
2802 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0)
2804 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff)
2806 #ifndef __ASSEMBLY__
2817 struct ALT_SDR_CTL_FPGAPORTRST_s
2819 uint32_t portrstn : 14;
2824 typedef volatile struct ALT_SDR_CTL_FPGAPORTRST_s ALT_SDR_CTL_FPGAPORTRST_t;
2828 #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
2859 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0
2861 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9
2863 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10
2865 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff
2867 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00
2869 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0
2871 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0)
2873 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff)
2875 #ifndef __ASSEMBLY__
2886 struct ALT_SDR_CTL_PROTPORTDEFAULT_s
2888 uint32_t portdefault : 10;
2893 typedef volatile struct ALT_SDR_CTL_PROTPORTDEFAULT_s ALT_SDR_CTL_PROTPORTDEFAULT_t;
2897 #define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c
2931 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0
2933 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11
2935 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12
2937 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff
2939 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000
2941 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0
2943 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0)
2945 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff)
2960 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12
2962 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23
2964 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12
2966 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000
2968 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff
2970 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0
2972 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12)
2974 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000)
2976 #ifndef __ASSEMBLY__
2987 struct ALT_SDR_CTL_PROTRULEADDR_s
2989 uint32_t lowaddr : 12;
2990 uint32_t highaddr : 12;
2995 typedef volatile struct ALT_SDR_CTL_PROTRULEADDR_s ALT_SDR_CTL_PROTRULEADDR_t;
2999 #define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90
3025 #define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0
3027 #define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11
3029 #define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12
3031 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff
3033 #define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000
3035 #define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0
3037 #define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0)
3039 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff)
3052 #define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12
3054 #define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23
3056 #define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12
3058 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000
3060 #define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff
3062 #define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0
3064 #define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12)
3066 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000)
3068 #ifndef __ASSEMBLY__
3079 struct ALT_SDR_CTL_PROTRULEID_s
3081 uint32_t lowid : 12;
3082 uint32_t highid : 12;
3087 typedef volatile struct ALT_SDR_CTL_PROTRULEID_s ALT_SDR_CTL_PROTRULEID_t;
3091 #define ALT_SDR_CTL_PROTRULEID_OFST 0x94
3122 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0
3124 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1
3126 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2
3128 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003
3130 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc
3132 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0
3134 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0)
3136 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003)
3147 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2
3149 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2
3151 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1
3153 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004
3155 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb
3157 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0
3159 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2)
3161 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004)
3175 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3
3177 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12
3179 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10
3181 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8
3183 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007
3185 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0
3187 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3)
3189 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8)
3201 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13
3203 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13
3205 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1
3207 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000
3209 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff
3211 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0
3213 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13)
3215 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000)
3217 #ifndef __ASSEMBLY__
3228 struct ALT_SDR_CTL_PROTRULEDATA_s
3230 uint32_t security : 2;
3231 uint32_t validrule : 1;
3232 uint32_t portmask : 10;
3233 uint32_t ruleresult : 1;
3238 typedef volatile struct ALT_SDR_CTL_PROTRULEDATA_s ALT_SDR_CTL_PROTRULEDATA_t;
3242 #define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98
3270 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0
3272 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4
3274 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5
3276 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f
3278 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0
3280 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0
3282 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0)
3284 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f)
3297 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5
3299 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5
3301 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1
3303 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020
3305 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf
3307 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0
3309 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5)
3311 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020)
3325 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6
3327 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6
3329 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1
3331 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040
3333 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf
3335 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0
3337 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6)
3339 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040)
3341 #ifndef __ASSEMBLY__
3352 struct ALT_SDR_CTL_PROTRULERDWR_s
3354 uint32_t ruleoffset : 5;
3355 uint32_t writerule : 1;
3356 uint32_t readrule : 1;
3361 typedef volatile struct ALT_SDR_CTL_PROTRULERDWR_s ALT_SDR_CTL_PROTRULERDWR_t;
3365 #define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c
3391 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0
3393 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19
3395 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20
3397 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff
3399 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000
3401 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0
3403 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3405 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3407 #ifndef __ASSEMBLY__
3418 struct ALT_SDR_CTL_QOSLOWPRI_s
3420 uint32_t lowpriorityval : 20;
3425 typedef volatile struct ALT_SDR_CTL_QOSLOWPRI_s ALT_SDR_CTL_QOSLOWPRI_t;
3429 #define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0
3453 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0
3455 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19
3457 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20
3459 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff
3461 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000
3463 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0
3465 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3467 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3469 #ifndef __ASSEMBLY__
3480 struct ALT_SDR_CTL_QOSHIGHPRI_s
3482 uint32_t highpriorityval : 20;
3487 typedef volatile struct ALT_SDR_CTL_QOSHIGHPRI_s ALT_SDR_CTL_QOSHIGHPRI_t;
3491 #define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4
3514 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0
3516 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9
3518 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10
3520 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff
3522 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00
3524 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0
3526 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0)
3528 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff)
3530 #ifndef __ASSEMBLY__
3541 struct ALT_SDR_CTL_QOSPRIORITYEN_s
3543 uint32_t priorityen : 10;
3548 typedef volatile struct ALT_SDR_CTL_QOSPRIORITYEN_s ALT_SDR_CTL_QOSPRIORITYEN_t;
3552 #define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8
3578 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0
3580 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29
3582 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30
3584 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff
3586 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000
3588 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0
3590 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0)
3592 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff)
3594 #ifndef __ASSEMBLY__
3605 struct ALT_SDR_CTL_MPPRIORITY_s
3607 uint32_t userpriority : 30;
3612 typedef volatile struct ALT_SDR_CTL_MPPRIORITY_s ALT_SDR_CTL_MPPRIORITY_t;
3616 #define ALT_SDR_CTL_MPPRIORITY_OFST 0xac
3642 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0
3644 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7
3646 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8
3648 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff
3650 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00
3652 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0
3654 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0)
3656 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff)
3658 #ifndef __ASSEMBLY__
3669 struct ALT_SDR_CTL_REMAPPRIORITY_s
3671 uint32_t priorityremap : 8;
3676 typedef volatile struct ALT_SDR_CTL_REMAPPRIORITY_s ALT_SDR_CTL_REMAPPRIORITY_t;
3680 #define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0
3711 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0
3713 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31
3715 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32
3717 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff
3719 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000
3721 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0
3723 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0)
3725 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff)
3727 #ifndef __ASSEMBLY__
3738 struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s
3740 uint32_t staticweight_31_0 : 32;
3744 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t;
3748 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0
3750 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))
3775 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0
3777 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17
3779 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18
3781 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff
3783 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000
3785 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0
3787 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0)
3789 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff)
3802 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18
3804 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31
3806 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14
3808 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000
3810 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff
3812 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0
3814 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18)
3816 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000)
3818 #ifndef __ASSEMBLY__
3829 struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s
3831 uint32_t staticweight_49_32 : 18;
3832 uint32_t sumofweights_13_0 : 14;
3836 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t;
3840 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4
3842 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))
3867 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0
3869 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31
3871 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32
3873 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff
3875 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000
3877 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0
3879 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0)
3881 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff)
3883 #ifndef __ASSEMBLY__
3894 struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s
3896 uint32_t sumofweights_45_14 : 32;
3900 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t;
3904 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8
3906 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))
3932 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0
3934 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17
3936 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18
3938 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff
3940 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000
3942 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0
3944 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0)
3946 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff)
3948 #ifndef __ASSEMBLY__
3959 struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s
3961 uint32_t sumofweights_63_46 : 18;
3966 typedef volatile struct ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_s ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t;
3970 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc
3972 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))
3974 #ifndef __ASSEMBLY__
3985 struct ALT_SDR_CTL_MPWT_s
3987 ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_t mpweight_0_4;
3988 ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_t mpweight_1_4;
3989 ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_t mpweight_2_4;
3990 ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_t mpweight_3_4;
3994 typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t;
3996 struct ALT_SDR_CTL_MPWT_raw_s
3998 volatile uint32_t mpweight_0_4;
3999 volatile uint32_t mpweight_1_4;
4000 volatile uint32_t mpweight_2_4;
4001 volatile uint32_t mpweight_3_4;
4005 typedef volatile struct ALT_SDR_CTL_MPWT_raw_s ALT_SDR_CTL_MPWT_raw_t;
4009 #ifndef __ASSEMBLY__
4020 struct ALT_SDR_CTL_s
4022 ALT_SDR_CTL_CTLCFG_t ctrlcfg;
4023 ALT_SDR_CTL_DRAMTIMING1_t dramtiming1;
4024 ALT_SDR_CTL_DRAMTIMING2_t dramtiming2;
4025 ALT_SDR_CTL_DRAMTIMING3_t dramtiming3;
4026 ALT_SDR_CTL_DRAMTIMING4_t dramtiming4;
4027 ALT_SDR_CTL_LOWPWRTIMING_t lowpwrtiming;
4028 ALT_SDR_CTL_DRAMODT_t dramodt;
4029 volatile uint32_t _pad_0x1c_0x2b[4];
4030 ALT_SDR_CTL_DRAMADDRW_t dramaddrw;
4031 ALT_SDR_CTL_DRAMIFWIDTH_t dramifwidth;
4032 ALT_SDR_CTL_DRAMDEVWIDTH_t dramdevwidth;
4033 ALT_SDR_CTL_DRAMSTS_t dramsts;
4034 ALT_SDR_CTL_DRAMINTR_t dramintr;
4035 ALT_SDR_CTL_SBECOUNT_t sbecount;
4036 ALT_SDR_CTL_DBECOUNT_t dbecount;
4037 ALT_SDR_CTL_ERRADDR_t erraddr;
4038 ALT_SDR_CTL_DROPCOUNT_t dropcount;
4039 ALT_SDR_CTL_DROPADDR_t dropaddr;
4040 ALT_SDR_CTL_LOWPWREQ_t lowpwreq;
4041 ALT_SDR_CTL_LOWPWRACK_t lowpwrack;
4042 ALT_SDR_CTL_STATICCFG_t staticcfg;
4043 ALT_SDR_CTL_CTLWIDTH_t ctrlwidth;
4044 volatile uint32_t _pad_0x64_0x7b[6];
4045 ALT_SDR_CTL_PORTCFG_t portcfg;
4046 ALT_SDR_CTL_FPGAPORTRST_t fpgaportrst;
4047 volatile uint32_t _pad_0x84_0x8b[2];
4048 ALT_SDR_CTL_PROTPORTDEFAULT_t protportdefault;
4049 ALT_SDR_CTL_PROTRULEADDR_t protruleaddr;
4050 ALT_SDR_CTL_PROTRULEID_t protruleid;
4051 ALT_SDR_CTL_PROTRULEDATA_t protruledata;
4052 ALT_SDR_CTL_PROTRULERDWR_t protrulerdwr;
4053 ALT_SDR_CTL_QOSLOWPRI_t qoslowpri;
4054 ALT_SDR_CTL_QOSHIGHPRI_t qoshighpri;
4055 ALT_SDR_CTL_QOSPRIORITYEN_t qospriorityen;
4056 ALT_SDR_CTL_MPPRIORITY_t mppriority;
4057 ALT_SDR_CTL_MPWT_t ctrlgrp_mpweight;
4058 volatile uint32_t _pad_0xc0_0xdf[8];
4059 ALT_SDR_CTL_REMAPPRIORITY_t remappriority;
4060 volatile uint32_t _pad_0xe4_0x1000[967];
4064 typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t;
4066 struct ALT_SDR_CTL_raw_s
4068 volatile uint32_t ctrlcfg;
4069 volatile uint32_t dramtiming1;
4070 volatile uint32_t dramtiming2;
4071 volatile uint32_t dramtiming3;
4072 volatile uint32_t dramtiming4;
4073 volatile uint32_t lowpwrtiming;
4074 volatile uint32_t dramodt;
4075 uint32_t _pad_0x1c_0x2b[4];
4076 volatile uint32_t dramaddrw;
4077 volatile uint32_t dramifwidth;
4078 volatile uint32_t dramdevwidth;
4079 volatile uint32_t dramsts;
4080 volatile uint32_t dramintr;
4081 volatile uint32_t sbecount;
4082 volatile uint32_t dbecount;
4083 volatile uint32_t erraddr;
4084 volatile uint32_t dropcount;
4085 volatile uint32_t dropaddr;
4086 volatile uint32_t lowpwreq;
4087 volatile uint32_t lowpwrack;
4088 volatile uint32_t staticcfg;
4089 volatile uint32_t ctrlwidth;
4090 uint32_t _pad_0x64_0x7b[6];
4091 volatile uint32_t portcfg;
4092 volatile uint32_t fpgaportrst;
4093 uint32_t _pad_0x84_0x8b[2];
4094 volatile uint32_t protportdefault;
4095 volatile uint32_t protruleaddr;
4096 volatile uint32_t protruleid;
4097 volatile uint32_t protruledata;
4098 volatile uint32_t protrulerdwr;
4099 volatile uint32_t qoslowpri;
4100 volatile uint32_t qoshighpri;
4101 volatile uint32_t qospriorityen;
4102 volatile uint32_t mppriority;
4103 ALT_SDR_CTL_MPWT_raw_t ctrlgrp_mpweight;
4104 uint32_t _pad_0xc0_0xdf[8];
4105 volatile uint32_t remappriority;
4106 uint32_t _pad_0xe4_0x1000[967];
4110 typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t;
4114 #ifndef __ASSEMBLY__
4127 volatile uint32_t _pad_0x0_0x4fff[5120];
4128 ALT_SDR_CTL_t ctrlgrp;
4129 volatile uint32_t _pad_0x6000_0x20000[26624];
4133 typedef volatile struct ALT_SDR_s ALT_SDR_t;
4135 struct ALT_SDR_raw_s
4137 uint32_t _pad_0x0_0x4fff[5120];
4138 ALT_SDR_CTL_raw_t ctrlgrp;
4139 uint32_t _pad_0x6000_0x20000[26624];
4143 typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t;