35 #ifndef __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
36 #define __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_LSB 0
114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_MSB 0
116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_WIDTH 1
118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET_MSK 0x00000001
120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_CLR_MSK 0xfffffffe
122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_RESET 0x0
124 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
126 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_LSB 1
141 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_MSB 1
143 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_WIDTH 1
145 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET_MSK 0x00000002
147 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_CLR_MSK 0xfffffffd
149 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_RESET 0x0
151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_LSB 2
168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_MSB 2
170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_WIDTH 1
172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET_MSK 0x00000004
174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_CLR_MSK 0xfffffffb
176 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_RESET 0x0
178 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
180 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
193 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_LSB 3
195 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_MSB 3
197 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_WIDTH 1
199 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET_MSK 0x00000008
201 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_CLR_MSK 0xfffffff7
203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_RESET 0x0
205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_LSB 4
222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_MSB 4
224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_WIDTH 1
226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET_MSK 0x00000010
228 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_CLR_MSK 0xffffffef
230 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_RESET 0x0
232 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
234 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
247 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_LSB 5
249 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_MSB 5
251 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_WIDTH 1
253 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET_MSK 0x00000020
255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_CLR_MSK 0xffffffdf
257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_RESET 0x0
259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_LSB 6
276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_MSB 6
278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_WIDTH 1
280 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET_MSK 0x00000040
282 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_CLR_MSK 0xffffffbf
284 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_RESET 0x0
286 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
288 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
301 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_LSB 7
303 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_MSB 7
305 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_WIDTH 1
307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET_MSK 0x00000080
309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_CLR_MSK 0xffffff7f
311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_RESET 0x0
313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_LSB 8
330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_MSB 8
332 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_WIDTH 1
334 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET_MSK 0x00000100
336 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_CLR_MSK 0xfffffeff
338 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_RESET 0x0
340 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
355 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_LSB 9
357 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_MSB 9
359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_WIDTH 1
361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET_MSK 0x00000200
363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_CLR_MSK 0xfffffdff
365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_RESET 0x0
367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_LSB 10
384 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_MSB 10
386 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_WIDTH 1
388 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET_MSK 0x00000400
390 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_CLR_MSK 0xfffffbff
392 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_RESET 0x0
394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
409 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_LSB 11
411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_MSB 11
413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_WIDTH 1
415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET_MSK 0x00000800
417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_CLR_MSK 0xfffff7ff
419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_RESET 0x0
421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET(value) (((value) << 11) & 0x00000800)
436 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_LSB 12
438 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_MSB 12
440 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_WIDTH 1
442 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET_MSK 0x00001000
444 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_CLR_MSK 0xffffefff
446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_RESET 0x0
448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET(value) (((value) << 12) & 0x00001000)
463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_LSB 13
465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_MSB 13
467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_WIDTH 1
469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET_MSK 0x00002000
471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_CLR_MSK 0xffffdfff
473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_RESET 0x0
475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET(value) (((value) << 13) & 0x00002000)
490 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_LSB 14
492 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_MSB 14
494 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_WIDTH 1
496 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET_MSK 0x00004000
498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_CLR_MSK 0xffffbfff
500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_RESET 0x0
502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET(value) (((value) << 14) & 0x00004000)
517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_LSB 15
519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_MSB 15
521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_WIDTH 1
523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET_MSK 0x00008000
525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_CLR_MSK 0xffff7fff
527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_RESET 0x0
529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_GET(value) (((value) & 0x00008000) >> 15)
531 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET(value) (((value) << 15) & 0x00008000)
544 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_LSB 16
546 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_MSB 16
548 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_WIDTH 1
550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET_MSK 0x00010000
552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_CLR_MSK 0xfffeffff
554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_RESET 0x0
556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET(value) (((value) << 16) & 0x00010000)
571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_LSB 17
573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_MSB 17
575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_WIDTH 1
577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET_MSK 0x00020000
579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_CLR_MSK 0xfffdffff
581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_RESET 0x0
583 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
585 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET(value) (((value) << 17) & 0x00020000)
598 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_LSB 18
600 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_MSB 18
602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_WIDTH 1
604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET_MSK 0x00040000
606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_CLR_MSK 0xfffbffff
608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_RESET 0x0
610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET(value) (((value) << 18) & 0x00040000)
625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_LSB 19
627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_MSB 19
629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_WIDTH 1
631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET_MSK 0x00080000
633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_CLR_MSK 0xfff7ffff
635 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_RESET 0x0
637 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
639 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET(value) (((value) << 19) & 0x00080000)
652 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_LSB 20
654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_MSB 20
656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_WIDTH 1
658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET_MSK 0x00100000
660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_CLR_MSK 0xffefffff
662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_RESET 0x0
664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_GET(value) (((value) & 0x00100000) >> 20)
666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET(value) (((value) << 20) & 0x00100000)
679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_LSB 21
681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_MSB 21
683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_WIDTH 1
685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET_MSK 0x00200000
687 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_CLR_MSK 0xffdfffff
689 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_RESET 0x0
691 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_GET(value) (((value) & 0x00200000) >> 21)
693 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET(value) (((value) << 21) & 0x00200000)
706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_LSB 22
708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_MSB 22
710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_WIDTH 1
712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET_MSK 0x00400000
714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_CLR_MSK 0xffbfffff
716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_RESET 0x0
718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_GET(value) (((value) & 0x00400000) >> 22)
720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET(value) (((value) << 22) & 0x00400000)
733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_LSB 23
735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_MSB 23
737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_WIDTH 1
739 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET_MSK 0x00800000
741 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_CLR_MSK 0xff7fffff
743 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_RESET 0x0
745 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_GET(value) (((value) & 0x00800000) >> 23)
747 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET(value) (((value) << 23) & 0x00800000)
760 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_LSB 24
762 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_MSB 24
764 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_WIDTH 1
766 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET_MSK 0x01000000
768 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_CLR_MSK 0xfeffffff
770 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_RESET 0x0
772 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_GET(value) (((value) & 0x01000000) >> 24)
774 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET(value) (((value) << 24) & 0x01000000)
787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_LSB 25
789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_MSB 25
791 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_WIDTH 1
793 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET_MSK 0x02000000
795 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_CLR_MSK 0xfdffffff
797 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_RESET 0x0
799 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
814 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_LSB 26
816 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_MSB 26
818 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_WIDTH 1
820 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET_MSK 0x04000000
822 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_CLR_MSK 0xfbffffff
824 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_RESET 0x0
826 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
828 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_LSB 27
843 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_MSB 27
845 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_WIDTH 1
847 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET_MSK 0x08000000
849 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_CLR_MSK 0xf7ffffff
851 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_RESET 0x0
853 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_GET(value) (((value) & 0x08000000) >> 27)
855 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET(value) (((value) << 27) & 0x08000000)
868 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_LSB 28
870 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_MSB 28
872 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_WIDTH 1
874 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET_MSK 0x10000000
876 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_CLR_MSK 0xefffffff
878 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_RESET 0x0
880 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_GET(value) (((value) & 0x10000000) >> 28)
882 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET(value) (((value) << 28) & 0x10000000)
895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_LSB 29
897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_MSB 29
899 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_WIDTH 1
901 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET_MSK 0x20000000
903 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_CLR_MSK 0xdfffffff
905 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_RESET 0x0
907 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
909 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET(value) (((value) << 29) & 0x20000000)
922 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_LSB 30
924 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_MSB 30
926 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_WIDTH 1
928 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET_MSK 0x40000000
930 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_CLR_MSK 0xbfffffff
932 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_RESET 0x0
934 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_GET(value) (((value) & 0x40000000) >> 30)
936 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET(value) (((value) << 30) & 0x40000000)
949 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_s
951 uint32_t nand_register : 1;
952 uint32_t nand_data : 1;
953 uint32_t qspi_data : 1;
954 uint32_t usb0_register : 1;
955 uint32_t usb1_register : 1;
956 uint32_t dma_nonsecure : 1;
957 uint32_t dma_secure : 1;
958 uint32_t spi_master0 : 1;
959 uint32_t spi_master1 : 1;
960 uint32_t spi_slave0 : 1;
961 uint32_t spi_slave1 : 1;
976 uint32_t sp_timer0 : 1;
977 uint32_t sp_timer1 : 1;
980 uint32_t lwsoc2fpga : 1;
981 uint32_t soc2fpga : 1;
986 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_t;
990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_RESET 0x00000000
992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_OFST 0x0
1047 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_LSB 0
1049 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_MSB 0
1051 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_WIDTH 1
1053 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET_MSK 0x00000001
1055 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_CLR_MSK 0xfffffffe
1057 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_RESET 0x0
1059 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1061 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1073 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_LSB 1
1075 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_MSB 1
1077 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_WIDTH 1
1079 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET_MSK 0x00000002
1081 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_CLR_MSK 0xfffffffd
1083 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_RESET 0x0
1085 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1087 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1099 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_LSB 2
1101 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_MSB 2
1103 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_WIDTH 1
1105 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET_MSK 0x00000004
1107 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_CLR_MSK 0xfffffffb
1109 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_RESET 0x0
1111 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
1113 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
1125 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_LSB 3
1127 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_MSB 3
1129 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_WIDTH 1
1131 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET_MSK 0x00000008
1133 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_CLR_MSK 0xfffffff7
1135 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_RESET 0x0
1137 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
1139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
1151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_LSB 4
1153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_MSB 4
1155 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_WIDTH 1
1157 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET_MSK 0x00000010
1159 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_CLR_MSK 0xffffffef
1161 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_RESET 0x0
1163 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
1165 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
1177 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_LSB 5
1179 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_MSB 5
1181 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_WIDTH 1
1183 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET_MSK 0x00000020
1185 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_CLR_MSK 0xffffffdf
1187 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_RESET 0x0
1189 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1191 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_LSB 6
1205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_MSB 6
1207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_WIDTH 1
1209 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET_MSK 0x00000040
1211 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_CLR_MSK 0xffffffbf
1213 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_RESET 0x0
1215 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1217 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1229 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_LSB 7
1231 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_MSB 7
1233 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_WIDTH 1
1235 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET_MSK 0x00000080
1237 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_CLR_MSK 0xffffff7f
1239 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_RESET 0x0
1241 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
1243 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
1255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_LSB 8
1257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_MSB 8
1259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_WIDTH 1
1261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET_MSK 0x00000100
1263 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_CLR_MSK 0xfffffeff
1265 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_RESET 0x0
1267 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
1269 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
1281 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_LSB 9
1283 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_MSB 9
1285 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_WIDTH 1
1287 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET_MSK 0x00000200
1289 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_CLR_MSK 0xfffffdff
1291 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_RESET 0x0
1293 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
1295 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
1307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_LSB 10
1309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_MSB 10
1311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_WIDTH 1
1313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET_MSK 0x00000400
1315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_CLR_MSK 0xfffffbff
1317 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_RESET 0x0
1319 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
1321 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
1333 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_LSB 11
1335 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_MSB 11
1337 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_WIDTH 1
1339 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET_MSK 0x00000800
1341 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_CLR_MSK 0xfffff7ff
1343 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_RESET 0x0
1345 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
1347 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET(value) (((value) << 11) & 0x00000800)
1359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_LSB 12
1361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_MSB 12
1363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_WIDTH 1
1365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET_MSK 0x00001000
1367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_CLR_MSK 0xffffefff
1369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_RESET 0x0
1371 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
1373 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET(value) (((value) << 12) & 0x00001000)
1385 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_LSB 13
1387 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_MSB 13
1389 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_WIDTH 1
1391 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET_MSK 0x00002000
1393 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_CLR_MSK 0xffffdfff
1395 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_RESET 0x0
1397 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
1399 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET(value) (((value) << 13) & 0x00002000)
1411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_LSB 14
1413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_MSB 14
1415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_WIDTH 1
1417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET_MSK 0x00004000
1419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_CLR_MSK 0xffffbfff
1421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_RESET 0x0
1423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
1425 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET(value) (((value) << 14) & 0x00004000)
1437 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_LSB 15
1439 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_MSB 15
1441 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_WIDTH 1
1443 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET_MSK 0x00008000
1445 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_CLR_MSK 0xffff7fff
1447 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_RESET 0x0
1449 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_GET(value) (((value) & 0x00008000) >> 15)
1451 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET(value) (((value) << 15) & 0x00008000)
1463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_LSB 16
1465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_MSB 16
1467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_WIDTH 1
1469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET_MSK 0x00010000
1471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_CLR_MSK 0xfffeffff
1473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_RESET 0x0
1475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
1477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET(value) (((value) << 16) & 0x00010000)
1489 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_LSB 17
1491 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_MSB 17
1493 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_WIDTH 1
1495 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET_MSK 0x00020000
1497 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_CLR_MSK 0xfffdffff
1499 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_RESET 0x0
1501 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
1503 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET(value) (((value) << 17) & 0x00020000)
1515 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_LSB 18
1517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_MSB 18
1519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_WIDTH 1
1521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET_MSK 0x00040000
1523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_CLR_MSK 0xfffbffff
1525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_RESET 0x0
1527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
1529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET(value) (((value) << 18) & 0x00040000)
1541 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_LSB 19
1543 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_MSB 19
1545 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_WIDTH 1
1547 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET_MSK 0x00080000
1549 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_CLR_MSK 0xfff7ffff
1551 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_RESET 0x0
1553 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
1555 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET(value) (((value) << 19) & 0x00080000)
1567 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_LSB 20
1569 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_MSB 20
1571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_WIDTH 1
1573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET_MSK 0x00100000
1575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_CLR_MSK 0xffefffff
1577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_RESET 0x0
1579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_GET(value) (((value) & 0x00100000) >> 20)
1581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET(value) (((value) << 20) & 0x00100000)
1593 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_LSB 21
1595 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_MSB 21
1597 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_WIDTH 1
1599 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET_MSK 0x00200000
1601 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_CLR_MSK 0xffdfffff
1603 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_RESET 0x0
1605 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_GET(value) (((value) & 0x00200000) >> 21)
1607 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET(value) (((value) << 21) & 0x00200000)
1619 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_LSB 22
1621 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_MSB 22
1623 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_WIDTH 1
1625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET_MSK 0x00400000
1627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_CLR_MSK 0xffbfffff
1629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_RESET 0x0
1631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_GET(value) (((value) & 0x00400000) >> 22)
1633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET(value) (((value) << 22) & 0x00400000)
1645 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_LSB 23
1647 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_MSB 23
1649 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_WIDTH 1
1651 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET_MSK 0x00800000
1653 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_CLR_MSK 0xff7fffff
1655 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_RESET 0x0
1657 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_GET(value) (((value) & 0x00800000) >> 23)
1659 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET(value) (((value) << 23) & 0x00800000)
1671 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_LSB 24
1673 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_MSB 24
1675 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_WIDTH 1
1677 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET_MSK 0x01000000
1679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_CLR_MSK 0xfeffffff
1681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_RESET 0x0
1683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_GET(value) (((value) & 0x01000000) >> 24)
1685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET(value) (((value) << 24) & 0x01000000)
1697 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_LSB 25
1699 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_MSB 25
1701 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_WIDTH 1
1703 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET_MSK 0x02000000
1705 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_CLR_MSK 0xfdffffff
1707 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_RESET 0x0
1709 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
1711 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
1723 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_LSB 26
1725 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_MSB 26
1727 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_WIDTH 1
1729 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET_MSK 0x04000000
1731 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_CLR_MSK 0xfbffffff
1733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_RESET 0x0
1735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
1737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
1749 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_LSB 27
1751 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_MSB 27
1753 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_WIDTH 1
1755 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET_MSK 0x08000000
1757 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_CLR_MSK 0xf7ffffff
1759 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_RESET 0x0
1761 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_GET(value) (((value) & 0x08000000) >> 27)
1763 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET(value) (((value) << 27) & 0x08000000)
1775 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_LSB 28
1777 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_MSB 28
1779 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_WIDTH 1
1781 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET_MSK 0x10000000
1783 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_CLR_MSK 0xefffffff
1785 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_RESET 0x0
1787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_GET(value) (((value) & 0x10000000) >> 28)
1789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET(value) (((value) << 28) & 0x10000000)
1801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_LSB 29
1803 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_MSB 29
1805 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_WIDTH 1
1807 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET_MSK 0x20000000
1809 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_CLR_MSK 0xdfffffff
1811 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_RESET 0x0
1813 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
1815 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET(value) (((value) << 29) & 0x20000000)
1827 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_LSB 30
1829 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_MSB 30
1831 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_WIDTH 1
1833 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET_MSK 0x40000000
1835 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_CLR_MSK 0xbfffffff
1837 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_RESET 0x0
1839 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_GET(value) (((value) & 0x40000000) >> 30)
1841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET(value) (((value) << 30) & 0x40000000)
1843 #ifndef __ASSEMBLY__
1854 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_s
1856 uint32_t nand_register : 1;
1857 uint32_t nand_data : 1;
1858 uint32_t qspi_data : 1;
1859 uint32_t usb0_register : 1;
1860 uint32_t usb1_register : 1;
1861 uint32_t dma_nonsecure : 1;
1862 uint32_t dma_secure : 1;
1863 uint32_t spi_master0 : 1;
1864 uint32_t spi_master1 : 1;
1865 uint32_t spi_slave0 : 1;
1866 uint32_t spi_slave1 : 1;
1881 uint32_t sp_timer0 : 1;
1882 uint32_t sp_timer1 : 1;
1885 uint32_t lwsoc2fpga : 1;
1886 uint32_t soc2fpga : 1;
1891 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_t;
1895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_RESET 0x00000000
1897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_OFST 0x4
1952 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_LSB 0
1954 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_MSB 0
1956 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_WIDTH 1
1958 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET_MSK 0x00000001
1960 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_CLR_MSK 0xfffffffe
1962 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_RESET 0x0
1964 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1966 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1978 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_LSB 1
1980 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_MSB 1
1982 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_WIDTH 1
1984 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET_MSK 0x00000002
1986 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_CLR_MSK 0xfffffffd
1988 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_RESET 0x0
1990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
2004 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_LSB 2
2006 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_MSB 2
2008 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_WIDTH 1
2010 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET_MSK 0x00000004
2012 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_CLR_MSK 0xfffffffb
2014 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_RESET 0x0
2016 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
2018 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
2030 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_LSB 3
2032 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_MSB 3
2034 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_WIDTH 1
2036 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET_MSK 0x00000008
2038 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_CLR_MSK 0xfffffff7
2040 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_RESET 0x0
2042 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
2044 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
2056 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_LSB 4
2058 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_MSB 4
2060 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_WIDTH 1
2062 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET_MSK 0x00000010
2064 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_CLR_MSK 0xffffffef
2066 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_RESET 0x0
2068 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
2070 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
2082 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_LSB 5
2084 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_MSB 5
2086 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_WIDTH 1
2088 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET_MSK 0x00000020
2090 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_CLR_MSK 0xffffffdf
2092 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_RESET 0x0
2094 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
2096 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
2108 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_LSB 6
2110 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_MSB 6
2112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_WIDTH 1
2114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET_MSK 0x00000040
2116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_CLR_MSK 0xffffffbf
2118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_RESET 0x0
2120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
2122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
2134 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_LSB 7
2136 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_MSB 7
2138 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_WIDTH 1
2140 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET_MSK 0x00000080
2142 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_CLR_MSK 0xffffff7f
2144 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_RESET 0x0
2146 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
2148 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
2160 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_LSB 8
2162 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_MSB 8
2164 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_WIDTH 1
2166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET_MSK 0x00000100
2168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_CLR_MSK 0xfffffeff
2170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_RESET 0x0
2172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
2174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
2186 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_LSB 9
2188 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_MSB 9
2190 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_WIDTH 1
2192 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET_MSK 0x00000200
2194 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_CLR_MSK 0xfffffdff
2196 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_RESET 0x0
2198 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
2200 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
2212 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_LSB 10
2214 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_MSB 10
2216 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_WIDTH 1
2218 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET_MSK 0x00000400
2220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_CLR_MSK 0xfffffbff
2222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_RESET 0x0
2224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
2226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
2238 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_LSB 11
2240 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_MSB 11
2242 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_WIDTH 1
2244 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET_MSK 0x00000800
2246 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_CLR_MSK 0xfffff7ff
2248 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_RESET 0x0
2250 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
2252 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET(value) (((value) << 11) & 0x00000800)
2264 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_LSB 12
2266 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_MSB 12
2268 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_WIDTH 1
2270 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET_MSK 0x00001000
2272 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_CLR_MSK 0xffffefff
2274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_RESET 0x0
2276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
2278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET(value) (((value) << 12) & 0x00001000)
2290 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_LSB 13
2292 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_MSB 13
2294 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_WIDTH 1
2296 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET_MSK 0x00002000
2298 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_CLR_MSK 0xffffdfff
2300 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_RESET 0x0
2302 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
2304 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET(value) (((value) << 13) & 0x00002000)
2316 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_LSB 14
2318 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_MSB 14
2320 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_WIDTH 1
2322 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET_MSK 0x00004000
2324 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_CLR_MSK 0xffffbfff
2326 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_RESET 0x0
2328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
2330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET(value) (((value) << 14) & 0x00004000)
2342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_LSB 15
2344 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_MSB 15
2346 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_WIDTH 1
2348 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET_MSK 0x00008000
2350 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_CLR_MSK 0xffff7fff
2352 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_RESET 0x0
2354 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_GET(value) (((value) & 0x00008000) >> 15)
2356 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET(value) (((value) << 15) & 0x00008000)
2368 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_LSB 16
2370 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_MSB 16
2372 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_WIDTH 1
2374 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET_MSK 0x00010000
2376 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_CLR_MSK 0xfffeffff
2378 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_RESET 0x0
2380 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
2382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET(value) (((value) << 16) & 0x00010000)
2394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_LSB 17
2396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_MSB 17
2398 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_WIDTH 1
2400 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET_MSK 0x00020000
2402 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_CLR_MSK 0xfffdffff
2404 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_RESET 0x0
2406 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
2408 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET(value) (((value) << 17) & 0x00020000)
2420 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_LSB 18
2422 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_MSB 18
2424 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_WIDTH 1
2426 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET_MSK 0x00040000
2428 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_CLR_MSK 0xfffbffff
2430 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_RESET 0x0
2432 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
2434 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET(value) (((value) << 18) & 0x00040000)
2446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_LSB 19
2448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_MSB 19
2450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_WIDTH 1
2452 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET_MSK 0x00080000
2454 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_CLR_MSK 0xfff7ffff
2456 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_RESET 0x0
2458 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
2460 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET(value) (((value) << 19) & 0x00080000)
2472 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_LSB 20
2474 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_MSB 20
2476 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_WIDTH 1
2478 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET_MSK 0x00100000
2480 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_CLR_MSK 0xffefffff
2482 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_RESET 0x0
2484 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_GET(value) (((value) & 0x00100000) >> 20)
2486 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET(value) (((value) << 20) & 0x00100000)
2498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_LSB 21
2500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_MSB 21
2502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_WIDTH 1
2504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET_MSK 0x00200000
2506 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_CLR_MSK 0xffdfffff
2508 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_RESET 0x0
2510 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_GET(value) (((value) & 0x00200000) >> 21)
2512 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET(value) (((value) << 21) & 0x00200000)
2524 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_LSB 22
2526 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_MSB 22
2528 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_WIDTH 1
2530 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET_MSK 0x00400000
2532 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_CLR_MSK 0xffbfffff
2534 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_RESET 0x0
2536 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_GET(value) (((value) & 0x00400000) >> 22)
2538 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET(value) (((value) << 22) & 0x00400000)
2550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_LSB 23
2552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_MSB 23
2554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_WIDTH 1
2556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET_MSK 0x00800000
2558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_CLR_MSK 0xff7fffff
2560 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_RESET 0x0
2562 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_GET(value) (((value) & 0x00800000) >> 23)
2564 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET(value) (((value) << 23) & 0x00800000)
2576 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_LSB 24
2578 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_MSB 24
2580 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_WIDTH 1
2582 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET_MSK 0x01000000
2584 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_CLR_MSK 0xfeffffff
2586 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_RESET 0x0
2588 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_GET(value) (((value) & 0x01000000) >> 24)
2590 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET(value) (((value) << 24) & 0x01000000)
2602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_LSB 25
2604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_MSB 25
2606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_WIDTH 1
2608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET_MSK 0x02000000
2610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_CLR_MSK 0xfdffffff
2612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_RESET 0x0
2614 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
2616 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
2628 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_LSB 26
2630 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_MSB 26
2632 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_WIDTH 1
2634 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET_MSK 0x04000000
2636 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_CLR_MSK 0xfbffffff
2638 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_RESET 0x0
2640 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
2642 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
2654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_LSB 27
2656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_MSB 27
2658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_WIDTH 1
2660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET_MSK 0x08000000
2662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_CLR_MSK 0xf7ffffff
2664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_RESET 0x0
2666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_GET(value) (((value) & 0x08000000) >> 27)
2668 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET(value) (((value) << 27) & 0x08000000)
2680 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_LSB 28
2682 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_MSB 28
2684 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_WIDTH 1
2686 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET_MSK 0x10000000
2688 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_CLR_MSK 0xefffffff
2690 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_RESET 0x0
2692 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_GET(value) (((value) & 0x10000000) >> 28)
2694 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET(value) (((value) << 28) & 0x10000000)
2706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_LSB 29
2708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_MSB 29
2710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_WIDTH 1
2712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET_MSK 0x20000000
2714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_CLR_MSK 0xdfffffff
2716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_RESET 0x0
2718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
2720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET(value) (((value) << 29) & 0x20000000)
2732 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_LSB 30
2734 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_MSB 30
2736 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_WIDTH 1
2738 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET_MSK 0x40000000
2740 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_CLR_MSK 0xbfffffff
2742 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_RESET 0x0
2744 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_GET(value) (((value) & 0x40000000) >> 30)
2746 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET(value) (((value) << 30) & 0x40000000)
2748 #ifndef __ASSEMBLY__
2759 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_s
2761 uint32_t nand_register : 1;
2762 uint32_t nand_data : 1;
2763 uint32_t qspi_data : 1;
2764 uint32_t usb0_register : 1;
2765 uint32_t usb1_register : 1;
2766 uint32_t dma_nonsecure : 1;
2767 uint32_t dma_secure : 1;
2768 uint32_t spi_master0 : 1;
2769 uint32_t spi_master1 : 1;
2770 uint32_t spi_slave0 : 1;
2771 uint32_t spi_slave1 : 1;
2786 uint32_t sp_timer0 : 1;
2787 uint32_t sp_timer1 : 1;
2790 uint32_t lwsoc2fpga : 1;
2791 uint32_t soc2fpga : 1;
2796 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_t;
2800 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_RESET 0x00000000
2802 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_OFST 0x8
2804 #ifndef __ASSEMBLY__
2815 struct ALT_NOC_L4_PRIV_FLT_s
2817 ALT_NOC_L4_PRIV_FLT_L4_PRIV_t l4_priv;
2818 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_t l4_priv_set;
2819 ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_t l4_priv_clear;
2820 volatile uint32_t _pad_0xc_0x100[61];
2824 typedef volatile struct ALT_NOC_L4_PRIV_FLT_s ALT_NOC_L4_PRIV_FLT_t;
2826 struct ALT_NOC_L4_PRIV_FLT_raw_s
2828 volatile uint32_t l4_priv;
2829 volatile uint32_t l4_priv_set;
2830 volatile uint32_t l4_priv_clear;
2831 uint32_t _pad_0xc_0x100[61];
2835 typedef volatile struct ALT_NOC_L4_PRIV_FLT_raw_s ALT_NOC_L4_PRIV_FLT_raw_t;