35 #ifndef __ALT_SOCAL_SPIM_H__
36 #define __ALT_SOCAL_SPIM_H__
136 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_04BITS 0x3
142 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_05BITS 0x4
148 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_06BITS 0x5
154 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_07BITS 0x6
160 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_08BITS 0x7
166 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_09BITS 0x8
172 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_10BITS 0x9
178 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_11BITS 0xa
184 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_12BITS 0xb
190 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_13BITS 0xc
196 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_14BITS 0xd
202 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_15BITS 0xe
208 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_16BITS 0xf
211 #define ALT_SPIM_CTRLR0_DFS_LSB 0
213 #define ALT_SPIM_CTRLR0_DFS_MSB 3
215 #define ALT_SPIM_CTRLR0_DFS_WIDTH 4
217 #define ALT_SPIM_CTRLR0_DFS_SET_MSK 0x0000000f
219 #define ALT_SPIM_CTRLR0_DFS_CLR_MSK 0xfffffff0
221 #define ALT_SPIM_CTRLR0_DFS_RESET 0x0
223 #define ALT_SPIM_CTRLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
225 #define ALT_SPIM_CTRLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
258 #define ALT_SPIM_CTRLR0_FRF_E_MOTOROLLA_SPI 0x0
264 #define ALT_SPIM_CTRLR0_FRF_E_TEXAS_SSP 0x1
270 #define ALT_SPIM_CTRLR0_FRF_E_NS_MICROWIRE 0x2
273 #define ALT_SPIM_CTRLR0_FRF_LSB 4
275 #define ALT_SPIM_CTRLR0_FRF_MSB 5
277 #define ALT_SPIM_CTRLR0_FRF_WIDTH 2
279 #define ALT_SPIM_CTRLR0_FRF_SET_MSK 0x00000030
281 #define ALT_SPIM_CTRLR0_FRF_CLR_MSK 0xffffffcf
283 #define ALT_SPIM_CTRLR0_FRF_RESET 0x0
285 #define ALT_SPIM_CTRLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
287 #define ALT_SPIM_CTRLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
325 #define ALT_SPIM_CTRLR0_SCPH_E_MIDDLE_BIT 0x0
331 #define ALT_SPIM_CTRLR0_SCPH_E_START_BIT 0x1
334 #define ALT_SPIM_CTRLR0_SCPH_LSB 6
336 #define ALT_SPIM_CTRLR0_SCPH_MSB 6
338 #define ALT_SPIM_CTRLR0_SCPH_WIDTH 1
340 #define ALT_SPIM_CTRLR0_SCPH_SET_MSK 0x00000040
342 #define ALT_SPIM_CTRLR0_SCPH_CLR_MSK 0xffffffbf
344 #define ALT_SPIM_CTRLR0_SCPH_RESET 0x0
346 #define ALT_SPIM_CTRLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
348 #define ALT_SPIM_CTRLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
380 #define ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_HIGH 0x0
386 #define ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_LOW 0x1
389 #define ALT_SPIM_CTRLR0_SCPOL_LSB 7
391 #define ALT_SPIM_CTRLR0_SCPOL_MSB 7
393 #define ALT_SPIM_CTRLR0_SCPOL_WIDTH 1
395 #define ALT_SPIM_CTRLR0_SCPOL_SET_MSK 0x00000080
397 #define ALT_SPIM_CTRLR0_SCPOL_CLR_MSK 0xffffff7f
399 #define ALT_SPIM_CTRLR0_SCPOL_RESET 0x0
401 #define ALT_SPIM_CTRLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
403 #define ALT_SPIM_CTRLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
466 #define ALT_SPIM_CTRLR0_TMOD_E_TX_AND_RX 0x0
472 #define ALT_SPIM_CTRLR0_TMOD_E_TX_ONLY 0x1
478 #define ALT_SPIM_CTRLR0_TMOD_E_RX_ONLY 0x2
484 #define ALT_SPIM_CTRLR0_TMOD_E_EEPROM_READ 0x3
487 #define ALT_SPIM_CTRLR0_TMOD_LSB 8
489 #define ALT_SPIM_CTRLR0_TMOD_MSB 9
491 #define ALT_SPIM_CTRLR0_TMOD_WIDTH 2
493 #define ALT_SPIM_CTRLR0_TMOD_SET_MSK 0x00000300
495 #define ALT_SPIM_CTRLR0_TMOD_CLR_MSK 0xfffffcff
497 #define ALT_SPIM_CTRLR0_TMOD_RESET 0x0
499 #define ALT_SPIM_CTRLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
501 #define ALT_SPIM_CTRLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
512 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_LSB 10
514 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_MSB 10
516 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_WIDTH 1
518 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_SET_MSK 0x00000400
520 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_CLR_MSK 0xfffffbff
522 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_RESET 0x0
524 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
526 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
556 #define ALT_SPIM_CTRLR0_SRL_E_NORMAL_MODE 0x0
562 #define ALT_SPIM_CTRLR0_SRL_E_TESTING_MODE 0x1
565 #define ALT_SPIM_CTRLR0_SRL_LSB 11
567 #define ALT_SPIM_CTRLR0_SRL_MSB 11
569 #define ALT_SPIM_CTRLR0_SRL_WIDTH 1
571 #define ALT_SPIM_CTRLR0_SRL_SET_MSK 0x00000800
573 #define ALT_SPIM_CTRLR0_SRL_CLR_MSK 0xfffff7ff
575 #define ALT_SPIM_CTRLR0_SRL_RESET 0x0
577 #define ALT_SPIM_CTRLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
579 #define ALT_SPIM_CTRLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
625 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_01_BIT 0x0
631 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_02_BIT 0x1
637 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_03_BIT 0x2
643 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_04_BIT 0x3
649 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_05_BIT 0x4
655 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_06_BIT 0x5
661 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_07_BIT 0x6
667 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_08_BIT 0x7
673 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_09_BIT 0x8
679 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_10_BIT 0x9
685 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_11_BIT 0xa
691 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_12_BIT 0xb
697 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_13_BIT 0xc
703 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_14_BIT 0xd
709 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_15_BIT 0xe
715 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_16_BIT 0xf
718 #define ALT_SPIM_CTRLR0_CFS_LSB 12
720 #define ALT_SPIM_CTRLR0_CFS_MSB 15
722 #define ALT_SPIM_CTRLR0_CFS_WIDTH 4
724 #define ALT_SPIM_CTRLR0_CFS_SET_MSK 0x0000f000
726 #define ALT_SPIM_CTRLR0_CFS_CLR_MSK 0xffff0fff
728 #define ALT_SPIM_CTRLR0_CFS_RESET 0x0
730 #define ALT_SPIM_CTRLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
732 #define ALT_SPIM_CTRLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
800 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_04BITS 0x3
806 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_05BITS 0x4
812 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_06BITS 0x5
818 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_07BITS 0x6
824 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_08BITS 0x7
830 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_09BITS 0x8
836 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_10BITS 0x9
842 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_11BITS 0xa
848 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_12BITS 0xb
854 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_13BITS 0xc
860 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_14BITS 0xd
866 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_15BITS 0xe
872 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_16BITS 0xf
878 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_17BITS 0x10
884 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_18BITS 0x11
890 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_19BITS 0x12
896 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_20BITS 0x13
902 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_21BITS 0x14
908 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_22BITS 0x15
914 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_23BITS 0x16
920 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_24BITS 0x17
926 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_25BITS 0x18
932 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_26BITS 0x19
938 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_27BITS 0x1a
944 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_28BITS 0x1b
950 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_29BITS 0x1c
956 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_30BITS 0x1d
962 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_31BITS 0x1e
968 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_32BITS 0x1f
971 #define ALT_SPIM_CTRLR0_DFS_32_LSB 16
973 #define ALT_SPIM_CTRLR0_DFS_32_MSB 20
975 #define ALT_SPIM_CTRLR0_DFS_32_WIDTH 5
977 #define ALT_SPIM_CTRLR0_DFS_32_SET_MSK 0x001f0000
979 #define ALT_SPIM_CTRLR0_DFS_32_CLR_MSK 0xffe0ffff
981 #define ALT_SPIM_CTRLR0_DFS_32_RESET 0x7
983 #define ALT_SPIM_CTRLR0_DFS_32_GET(value) (((value) & 0x001f0000) >> 16)
985 #define ALT_SPIM_CTRLR0_DFS_32_SET(value) (((value) << 16) & 0x001f0000)
1007 #define ALT_SPIM_CTRLR0_SPI_FRF_LSB 21
1009 #define ALT_SPIM_CTRLR0_SPI_FRF_MSB 22
1011 #define ALT_SPIM_CTRLR0_SPI_FRF_WIDTH 2
1013 #define ALT_SPIM_CTRLR0_SPI_FRF_SET_MSK 0x00600000
1015 #define ALT_SPIM_CTRLR0_SPI_FRF_CLR_MSK 0xff9fffff
1017 #define ALT_SPIM_CTRLR0_SPI_FRF_RESET 0x0
1019 #define ALT_SPIM_CTRLR0_SPI_FRF_GET(value) (((value) & 0x00600000) >> 21)
1021 #define ALT_SPIM_CTRLR0_SPI_FRF_SET(value) (((value) << 21) & 0x00600000)
1032 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_LSB 23
1034 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_MSB 31
1036 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_WIDTH 9
1038 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_SET_MSK 0xff800000
1040 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_CLR_MSK 0x007fffff
1042 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_RESET 0x0
1044 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_GET(value) (((value) & 0xff800000) >> 23)
1046 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_SET(value) (((value) << 23) & 0xff800000)
1048 #ifndef __ASSEMBLY__
1060 struct ALT_SPIM_CTRLR0_s
1062 const volatile uint32_t DFS : 4;
1063 volatile uint32_t FRF : 2;
1064 volatile uint32_t SCPH : 1;
1065 volatile uint32_t SCPOL : 1;
1066 volatile uint32_t TMOD : 2;
1067 const volatile uint32_t RSVD_SLV_OE : 1;
1068 volatile uint32_t SRL : 1;
1069 volatile uint32_t CFS : 4;
1070 volatile uint32_t DFS_32 : 5;
1071 const volatile uint32_t SPI_FRF : 2;
1072 const volatile uint32_t RSVD_CTRLR0 : 9;
1076 typedef struct ALT_SPIM_CTRLR0_s ALT_SPIM_CTRLR0_t;
1080 #define ALT_SPIM_CTRLR0_RESET 0x00070000
1082 #define ALT_SPIM_CTRLR0_OFST 0x0
1084 #define ALT_SPIM_CTRLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTRLR0_OFST))
1139 #define ALT_SPIM_CTRLR1_NDF_LSB 0
1141 #define ALT_SPIM_CTRLR1_NDF_MSB 15
1143 #define ALT_SPIM_CTRLR1_NDF_WIDTH 16
1145 #define ALT_SPIM_CTRLR1_NDF_SET_MSK 0x0000ffff
1147 #define ALT_SPIM_CTRLR1_NDF_CLR_MSK 0xffff0000
1149 #define ALT_SPIM_CTRLR1_NDF_RESET 0x0
1151 #define ALT_SPIM_CTRLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
1153 #define ALT_SPIM_CTRLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
1164 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_LSB 16
1166 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_MSB 31
1168 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_WIDTH 16
1170 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_SET_MSK 0xffff0000
1172 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_CLR_MSK 0x0000ffff
1174 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_RESET 0x0
1176 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_GET(value) (((value) & 0xffff0000) >> 16)
1178 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_SET(value) (((value) << 16) & 0xffff0000)
1180 #ifndef __ASSEMBLY__
1192 struct ALT_SPIM_CTRLR1_s
1194 volatile uint32_t NDF : 16;
1195 const volatile uint32_t RSVD_CTRLR1 : 16;
1199 typedef struct ALT_SPIM_CTRLR1_s ALT_SPIM_CTRLR1_t;
1203 #define ALT_SPIM_CTRLR1_RESET 0x00000000
1205 #define ALT_SPIM_CTRLR1_OFST 0x4
1207 #define ALT_SPIM_CTRLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTRLR1_OFST))
1254 #define ALT_SPIM_SSIENR_SSI_EN_E_DISABLE 0x0
1260 #define ALT_SPIM_SSIENR_SSI_EN_E_ENABLED 0x1
1263 #define ALT_SPIM_SSIENR_SSI_EN_LSB 0
1265 #define ALT_SPIM_SSIENR_SSI_EN_MSB 0
1267 #define ALT_SPIM_SSIENR_SSI_EN_WIDTH 1
1269 #define ALT_SPIM_SSIENR_SSI_EN_SET_MSK 0x00000001
1271 #define ALT_SPIM_SSIENR_SSI_EN_CLR_MSK 0xfffffffe
1273 #define ALT_SPIM_SSIENR_SSI_EN_RESET 0x0
1275 #define ALT_SPIM_SSIENR_SSI_EN_GET(value) (((value) & 0x00000001) >> 0)
1277 #define ALT_SPIM_SSIENR_SSI_EN_SET(value) (((value) << 0) & 0x00000001)
1288 #define ALT_SPIM_SSIENR_RSVD_SSIENR_LSB 1
1290 #define ALT_SPIM_SSIENR_RSVD_SSIENR_MSB 31
1292 #define ALT_SPIM_SSIENR_RSVD_SSIENR_WIDTH 31
1294 #define ALT_SPIM_SSIENR_RSVD_SSIENR_SET_MSK 0xfffffffe
1296 #define ALT_SPIM_SSIENR_RSVD_SSIENR_CLR_MSK 0x00000001
1298 #define ALT_SPIM_SSIENR_RSVD_SSIENR_RESET 0x0
1300 #define ALT_SPIM_SSIENR_RSVD_SSIENR_GET(value) (((value) & 0xfffffffe) >> 1)
1302 #define ALT_SPIM_SSIENR_RSVD_SSIENR_SET(value) (((value) << 1) & 0xfffffffe)
1304 #ifndef __ASSEMBLY__
1316 struct ALT_SPIM_SSIENR_s
1318 volatile uint32_t SSI_EN : 1;
1319 const volatile uint32_t RSVD_SSIENR : 31;
1323 typedef struct ALT_SPIM_SSIENR_s ALT_SPIM_SSIENR_t;
1327 #define ALT_SPIM_SSIENR_RESET 0x00000000
1329 #define ALT_SPIM_SSIENR_OFST 0x8
1331 #define ALT_SPIM_SSIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SSIENR_OFST))
1390 #define ALT_SPIM_MWCR_MWMOD_E_NON_SEQUENTIAL 0x0
1396 #define ALT_SPIM_MWCR_MWMOD_E_SEQUENTIAL 0x1
1399 #define ALT_SPIM_MWCR_MWMOD_LSB 0
1401 #define ALT_SPIM_MWCR_MWMOD_MSB 0
1403 #define ALT_SPIM_MWCR_MWMOD_WIDTH 1
1405 #define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
1407 #define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
1409 #define ALT_SPIM_MWCR_MWMOD_RESET 0x0
1411 #define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
1413 #define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
1445 #define ALT_SPIM_MWCR_MDD_E_RECEIVE 0x0
1451 #define ALT_SPIM_MWCR_MDD_E_TRANSMIT 0x1
1454 #define ALT_SPIM_MWCR_MDD_LSB 1
1456 #define ALT_SPIM_MWCR_MDD_MSB 1
1458 #define ALT_SPIM_MWCR_MDD_WIDTH 1
1460 #define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
1462 #define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
1464 #define ALT_SPIM_MWCR_MDD_RESET 0x0
1466 #define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1468 #define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1506 #define ALT_SPIM_MWCR_MHS_E_DISABLE 0x0
1512 #define ALT_SPIM_MWCR_MHS_E_ENABLED 0x1
1515 #define ALT_SPIM_MWCR_MHS_LSB 2
1517 #define ALT_SPIM_MWCR_MHS_MSB 2
1519 #define ALT_SPIM_MWCR_MHS_WIDTH 1
1521 #define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
1523 #define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
1525 #define ALT_SPIM_MWCR_MHS_RESET 0x0
1527 #define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
1529 #define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
1540 #define ALT_SPIM_MWCR_RSVD_MWCR_LSB 3
1542 #define ALT_SPIM_MWCR_RSVD_MWCR_MSB 31
1544 #define ALT_SPIM_MWCR_RSVD_MWCR_WIDTH 29
1546 #define ALT_SPIM_MWCR_RSVD_MWCR_SET_MSK 0xfffffff8
1548 #define ALT_SPIM_MWCR_RSVD_MWCR_CLR_MSK 0x00000007
1550 #define ALT_SPIM_MWCR_RSVD_MWCR_RESET 0x0
1552 #define ALT_SPIM_MWCR_RSVD_MWCR_GET(value) (((value) & 0xfffffff8) >> 3)
1554 #define ALT_SPIM_MWCR_RSVD_MWCR_SET(value) (((value) << 3) & 0xfffffff8)
1556 #ifndef __ASSEMBLY__
1568 struct ALT_SPIM_MWCR_s
1570 volatile uint32_t MWMOD : 1;
1571 volatile uint32_t MDD : 1;
1572 volatile uint32_t MHS : 1;
1573 const volatile uint32_t RSVD_MWCR : 29;
1577 typedef struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t;
1581 #define ALT_SPIM_MWCR_RESET 0x00000000
1583 #define ALT_SPIM_MWCR_OFST 0xc
1585 #define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
1656 #define ALT_SPIM_SER_SER_E_NOT_SELECTED 0x0
1662 #define ALT_SPIM_SER_SER_E_SELECTED 0x1
1665 #define ALT_SPIM_SER_SER_LSB 0
1667 #define ALT_SPIM_SER_SER_MSB 3
1669 #define ALT_SPIM_SER_SER_WIDTH 4
1671 #define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
1673 #define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
1675 #define ALT_SPIM_SER_SER_RESET 0x0
1677 #define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
1679 #define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
1690 #define ALT_SPIM_SER_RSVD_SER_LSB 4
1692 #define ALT_SPIM_SER_RSVD_SER_MSB 31
1694 #define ALT_SPIM_SER_RSVD_SER_WIDTH 28
1696 #define ALT_SPIM_SER_RSVD_SER_SET_MSK 0xfffffff0
1698 #define ALT_SPIM_SER_RSVD_SER_CLR_MSK 0x0000000f
1700 #define ALT_SPIM_SER_RSVD_SER_RESET 0x0
1702 #define ALT_SPIM_SER_RSVD_SER_GET(value) (((value) & 0xfffffff0) >> 4)
1704 #define ALT_SPIM_SER_RSVD_SER_SET(value) (((value) << 4) & 0xfffffff0)
1706 #ifndef __ASSEMBLY__
1718 struct ALT_SPIM_SER_s
1720 volatile uint32_t SER : 4;
1721 const volatile uint32_t RSVD_SER : 28;
1725 typedef struct ALT_SPIM_SER_s ALT_SPIM_SER_t;
1729 #define ALT_SPIM_SER_RESET 0x00000000
1731 #define ALT_SPIM_SER_OFST 0x10
1733 #define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
1789 #define ALT_SPIM_BAUDR_SCKDV_LSB 0
1791 #define ALT_SPIM_BAUDR_SCKDV_MSB 15
1793 #define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
1795 #define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
1797 #define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
1799 #define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
1801 #define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
1803 #define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
1814 #define ALT_SPIM_BAUDR_RSVD_BAUDR_LSB 16
1816 #define ALT_SPIM_BAUDR_RSVD_BAUDR_MSB 31
1818 #define ALT_SPIM_BAUDR_RSVD_BAUDR_WIDTH 16
1820 #define ALT_SPIM_BAUDR_RSVD_BAUDR_SET_MSK 0xffff0000
1822 #define ALT_SPIM_BAUDR_RSVD_BAUDR_CLR_MSK 0x0000ffff
1824 #define ALT_SPIM_BAUDR_RSVD_BAUDR_RESET 0x0
1826 #define ALT_SPIM_BAUDR_RSVD_BAUDR_GET(value) (((value) & 0xffff0000) >> 16)
1828 #define ALT_SPIM_BAUDR_RSVD_BAUDR_SET(value) (((value) << 16) & 0xffff0000)
1830 #ifndef __ASSEMBLY__
1842 struct ALT_SPIM_BAUDR_s
1844 volatile uint32_t SCKDV : 16;
1845 const volatile uint32_t RSVD_BAUDR : 16;
1849 typedef struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t;
1853 #define ALT_SPIM_BAUDR_RESET 0x00000000
1855 #define ALT_SPIM_BAUDR_OFST 0x14
1857 #define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
1899 #define ALT_SPIM_TXFTLR_TFT_LSB 0
1901 #define ALT_SPIM_TXFTLR_TFT_MSB 7
1903 #define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1905 #define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1907 #define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1909 #define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1911 #define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1913 #define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1924 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_LSB 8
1926 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_MSB 31
1928 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_WIDTH 24
1930 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_SET_MSK 0xffffff00
1932 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_CLR_MSK 0x000000ff
1934 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_RESET 0x0
1936 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1938 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1940 #ifndef __ASSEMBLY__
1952 struct ALT_SPIM_TXFTLR_s
1954 volatile uint32_t TFT : 8;
1955 const volatile uint32_t RSVD_TXFTLR : 24;
1959 typedef struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t;
1963 #define ALT_SPIM_TXFTLR_RESET 0x00000000
1965 #define ALT_SPIM_TXFTLR_OFST 0x18
1967 #define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
2009 #define ALT_SPIM_RXFTLR_RFT_LSB 0
2011 #define ALT_SPIM_RXFTLR_RFT_MSB 7
2013 #define ALT_SPIM_RXFTLR_RFT_WIDTH 8
2015 #define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
2017 #define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
2019 #define ALT_SPIM_RXFTLR_RFT_RESET 0x0
2021 #define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
2023 #define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
2034 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_LSB 8
2036 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_MSB 31
2038 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_WIDTH 24
2040 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_SET_MSK 0xffffff00
2042 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_CLR_MSK 0x000000ff
2044 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_RESET 0x0
2046 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
2048 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_SET(value) (((value) << 8) & 0xffffff00)
2050 #ifndef __ASSEMBLY__
2062 struct ALT_SPIM_RXFTLR_s
2064 volatile uint32_t RFT : 8;
2065 const volatile uint32_t RSVD_RXFTLR : 24;
2069 typedef struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t;
2073 #define ALT_SPIM_RXFTLR_RESET 0x00000000
2075 #define ALT_SPIM_RXFTLR_OFST 0x1c
2077 #define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
2103 #define ALT_SPIM_TXFLR_TXTFL_LSB 0
2105 #define ALT_SPIM_TXFLR_TXTFL_MSB 8
2107 #define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
2109 #define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
2111 #define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
2113 #define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
2115 #define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
2117 #define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
2128 #define ALT_SPIM_TXFLR_RSVD_TXFLR_LSB 9
2130 #define ALT_SPIM_TXFLR_RSVD_TXFLR_MSB 31
2132 #define ALT_SPIM_TXFLR_RSVD_TXFLR_WIDTH 23
2134 #define ALT_SPIM_TXFLR_RSVD_TXFLR_SET_MSK 0xfffffe00
2136 #define ALT_SPIM_TXFLR_RSVD_TXFLR_CLR_MSK 0x000001ff
2138 #define ALT_SPIM_TXFLR_RSVD_TXFLR_RESET 0x0
2140 #define ALT_SPIM_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
2142 #define ALT_SPIM_TXFLR_RSVD_TXFLR_SET(value) (((value) << 9) & 0xfffffe00)
2144 #ifndef __ASSEMBLY__
2156 struct ALT_SPIM_TXFLR_s
2158 const volatile uint32_t TXTFL : 9;
2159 const volatile uint32_t RSVD_TXFLR : 23;
2163 typedef struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t;
2167 #define ALT_SPIM_TXFLR_RESET 0x00000000
2169 #define ALT_SPIM_TXFLR_OFST 0x20
2171 #define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
2197 #define ALT_SPIM_RXFLR_RXTFL_LSB 0
2199 #define ALT_SPIM_RXFLR_RXTFL_MSB 8
2201 #define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
2203 #define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
2205 #define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
2207 #define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
2209 #define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
2211 #define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
2222 #define ALT_SPIM_RXFLR_RSVD_RXFLR_LSB 9
2224 #define ALT_SPIM_RXFLR_RSVD_RXFLR_MSB 31
2226 #define ALT_SPIM_RXFLR_RSVD_RXFLR_WIDTH 23
2228 #define ALT_SPIM_RXFLR_RSVD_RXFLR_SET_MSK 0xfffffe00
2230 #define ALT_SPIM_RXFLR_RSVD_RXFLR_CLR_MSK 0x000001ff
2232 #define ALT_SPIM_RXFLR_RSVD_RXFLR_RESET 0x0
2234 #define ALT_SPIM_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
2236 #define ALT_SPIM_RXFLR_RSVD_RXFLR_SET(value) (((value) << 9) & 0xfffffe00)
2238 #ifndef __ASSEMBLY__
2250 struct ALT_SPIM_RXFLR_s
2252 const volatile uint32_t RXTFL : 9;
2253 const volatile uint32_t RSVD_RXFLR : 23;
2257 typedef struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t;
2261 #define ALT_SPIM_RXFLR_RESET 0x00000000
2263 #define ALT_SPIM_RXFLR_OFST 0x24
2265 #define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
2322 #define ALT_SPIM_SR_BUSY_E_INACTIVE 0x0
2328 #define ALT_SPIM_SR_BUSY_E_ACTIVE 0x1
2331 #define ALT_SPIM_SR_BUSY_LSB 0
2333 #define ALT_SPIM_SR_BUSY_MSB 0
2335 #define ALT_SPIM_SR_BUSY_WIDTH 1
2337 #define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
2339 #define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
2341 #define ALT_SPIM_SR_BUSY_RESET 0x0
2343 #define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
2345 #define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
2373 #define ALT_SPIM_SR_TFNF_E_FULL 0x0
2379 #define ALT_SPIM_SR_TFNF_E_NOT_FULL 0x1
2382 #define ALT_SPIM_SR_TFNF_LSB 1
2384 #define ALT_SPIM_SR_TFNF_MSB 1
2386 #define ALT_SPIM_SR_TFNF_WIDTH 1
2388 #define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
2390 #define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
2392 #define ALT_SPIM_SR_TFNF_RESET 0x1
2394 #define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
2396 #define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
2428 #define ALT_SPIM_SR_TFE_E_NOT_EMPTY 0x0
2434 #define ALT_SPIM_SR_TFE_E_EMPTY 0x1
2437 #define ALT_SPIM_SR_TFE_LSB 2
2439 #define ALT_SPIM_SR_TFE_MSB 2
2441 #define ALT_SPIM_SR_TFE_WIDTH 1
2443 #define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
2445 #define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
2447 #define ALT_SPIM_SR_TFE_RESET 0x1
2449 #define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
2451 #define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
2483 #define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
2489 #define ALT_SPIM_SR_RFNE_E_NOT_EMPTY 0x1
2492 #define ALT_SPIM_SR_RFNE_LSB 3
2494 #define ALT_SPIM_SR_RFNE_MSB 3
2496 #define ALT_SPIM_SR_RFNE_WIDTH 1
2498 #define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
2500 #define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
2502 #define ALT_SPIM_SR_RFNE_RESET 0x0
2504 #define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
2506 #define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
2536 #define ALT_SPIM_SR_RFF_E_NOT_FULL 0x0
2542 #define ALT_SPIM_SR_RFF_E_FULL 0x1
2545 #define ALT_SPIM_SR_RFF_LSB 4
2547 #define ALT_SPIM_SR_RFF_MSB 4
2549 #define ALT_SPIM_SR_RFF_WIDTH 1
2551 #define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
2553 #define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
2555 #define ALT_SPIM_SR_RFF_RESET 0x0
2557 #define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
2559 #define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
2570 #define ALT_SPIM_SR_RSVD_TXE_LSB 5
2572 #define ALT_SPIM_SR_RSVD_TXE_MSB 5
2574 #define ALT_SPIM_SR_RSVD_TXE_WIDTH 1
2576 #define ALT_SPIM_SR_RSVD_TXE_SET_MSK 0x00000020
2578 #define ALT_SPIM_SR_RSVD_TXE_CLR_MSK 0xffffffdf
2580 #define ALT_SPIM_SR_RSVD_TXE_RESET 0x0
2582 #define ALT_SPIM_SR_RSVD_TXE_GET(value) (((value) & 0x00000020) >> 5)
2584 #define ALT_SPIM_SR_RSVD_TXE_SET(value) (((value) << 5) & 0x00000020)
2621 #define ALT_SPIM_SR_DCOL_E_NO_ERROR_CONDITION 0x0
2627 #define ALT_SPIM_SR_DCOL_E_TX_COLLISION_ERROR 0x1
2630 #define ALT_SPIM_SR_DCOL_LSB 6
2632 #define ALT_SPIM_SR_DCOL_MSB 6
2634 #define ALT_SPIM_SR_DCOL_WIDTH 1
2636 #define ALT_SPIM_SR_DCOL_SET_MSK 0x00000040
2638 #define ALT_SPIM_SR_DCOL_CLR_MSK 0xffffffbf
2640 #define ALT_SPIM_SR_DCOL_RESET 0x0
2642 #define ALT_SPIM_SR_DCOL_GET(value) (((value) & 0x00000040) >> 6)
2644 #define ALT_SPIM_SR_DCOL_SET(value) (((value) << 6) & 0x00000040)
2655 #define ALT_SPIM_SR_RSVD_SR_LSB 7
2657 #define ALT_SPIM_SR_RSVD_SR_MSB 31
2659 #define ALT_SPIM_SR_RSVD_SR_WIDTH 25
2661 #define ALT_SPIM_SR_RSVD_SR_SET_MSK 0xffffff80
2663 #define ALT_SPIM_SR_RSVD_SR_CLR_MSK 0x0000007f
2665 #define ALT_SPIM_SR_RSVD_SR_RESET 0x0
2667 #define ALT_SPIM_SR_RSVD_SR_GET(value) (((value) & 0xffffff80) >> 7)
2669 #define ALT_SPIM_SR_RSVD_SR_SET(value) (((value) << 7) & 0xffffff80)
2671 #ifndef __ASSEMBLY__
2683 struct ALT_SPIM_SR_s
2685 const volatile uint32_t BUSY : 1;
2686 const volatile uint32_t TFNF : 1;
2687 const volatile uint32_t TFE : 1;
2688 const volatile uint32_t RFNE : 1;
2689 const volatile uint32_t RFF : 1;
2690 const volatile uint32_t RSVD_TXE : 1;
2691 const volatile uint32_t DCOL : 1;
2692 const volatile uint32_t RSVD_SR : 25;
2696 typedef struct ALT_SPIM_SR_s ALT_SPIM_SR_t;
2700 #define ALT_SPIM_SR_RESET 0x00000006
2702 #define ALT_SPIM_SR_OFST 0x28
2704 #define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
2748 #define ALT_SPIM_IMR_TXEIM_E_MASKED 0x0
2754 #define ALT_SPIM_IMR_TXEIM_E_UNMASKED 0x1
2757 #define ALT_SPIM_IMR_TXEIM_LSB 0
2759 #define ALT_SPIM_IMR_TXEIM_MSB 0
2761 #define ALT_SPIM_IMR_TXEIM_WIDTH 1
2763 #define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
2765 #define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
2767 #define ALT_SPIM_IMR_TXEIM_RESET 0x1
2769 #define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2771 #define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2797 #define ALT_SPIM_IMR_TXOIM_E_MASKED 0x0
2803 #define ALT_SPIM_IMR_TXOIM_E_UNMASKED 0x1
2806 #define ALT_SPIM_IMR_TXOIM_LSB 1
2808 #define ALT_SPIM_IMR_TXOIM_MSB 1
2810 #define ALT_SPIM_IMR_TXOIM_WIDTH 1
2812 #define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
2814 #define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
2816 #define ALT_SPIM_IMR_TXOIM_RESET 0x1
2818 #define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2820 #define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2846 #define ALT_SPIM_IMR_RXUIM_E_MASKED 0x0
2852 #define ALT_SPIM_IMR_RXUIM_E_UNMASKED 0x1
2855 #define ALT_SPIM_IMR_RXUIM_LSB 2
2857 #define ALT_SPIM_IMR_RXUIM_MSB 2
2859 #define ALT_SPIM_IMR_RXUIM_WIDTH 1
2861 #define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
2863 #define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
2865 #define ALT_SPIM_IMR_RXUIM_RESET 0x1
2867 #define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2869 #define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2895 #define ALT_SPIM_IMR_RXOIM_E_MASKED 0x0
2901 #define ALT_SPIM_IMR_RXOIM_E_UNMASKED 0x1
2904 #define ALT_SPIM_IMR_RXOIM_LSB 3
2906 #define ALT_SPIM_IMR_RXOIM_MSB 3
2908 #define ALT_SPIM_IMR_RXOIM_WIDTH 1
2910 #define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
2912 #define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
2914 #define ALT_SPIM_IMR_RXOIM_RESET 0x1
2916 #define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2918 #define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2944 #define ALT_SPIM_IMR_RXFIM_E_MASKED 0x0
2950 #define ALT_SPIM_IMR_RXFIM_E_UNMASKED 0x1
2953 #define ALT_SPIM_IMR_RXFIM_LSB 4
2955 #define ALT_SPIM_IMR_RXFIM_MSB 4
2957 #define ALT_SPIM_IMR_RXFIM_WIDTH 1
2959 #define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
2961 #define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
2963 #define ALT_SPIM_IMR_RXFIM_RESET 0x1
2965 #define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2967 #define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2995 #define ALT_SPIM_IMR_MSTIM_E_MASKED 0x0
3001 #define ALT_SPIM_IMR_MSTIM_E_UNMASKED 0x1
3004 #define ALT_SPIM_IMR_MSTIM_LSB 5
3006 #define ALT_SPIM_IMR_MSTIM_MSB 5
3008 #define ALT_SPIM_IMR_MSTIM_WIDTH 1
3010 #define ALT_SPIM_IMR_MSTIM_SET_MSK 0x00000020
3012 #define ALT_SPIM_IMR_MSTIM_CLR_MSK 0xffffffdf
3014 #define ALT_SPIM_IMR_MSTIM_RESET 0x1
3016 #define ALT_SPIM_IMR_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
3018 #define ALT_SPIM_IMR_MSTIM_SET(value) (((value) << 5) & 0x00000020)
3029 #define ALT_SPIM_IMR_RSVD_IMR_LSB 6
3031 #define ALT_SPIM_IMR_RSVD_IMR_MSB 31
3033 #define ALT_SPIM_IMR_RSVD_IMR_WIDTH 26
3035 #define ALT_SPIM_IMR_RSVD_IMR_SET_MSK 0xffffffc0
3037 #define ALT_SPIM_IMR_RSVD_IMR_CLR_MSK 0x0000003f
3039 #define ALT_SPIM_IMR_RSVD_IMR_RESET 0x0
3041 #define ALT_SPIM_IMR_RSVD_IMR_GET(value) (((value) & 0xffffffc0) >> 6)
3043 #define ALT_SPIM_IMR_RSVD_IMR_SET(value) (((value) << 6) & 0xffffffc0)
3045 #ifndef __ASSEMBLY__
3057 struct ALT_SPIM_IMR_s
3059 volatile uint32_t TXEIM : 1;
3060 volatile uint32_t TXOIM : 1;
3061 volatile uint32_t RXUIM : 1;
3062 volatile uint32_t RXOIM : 1;
3063 volatile uint32_t RXFIM : 1;
3064 volatile uint32_t MSTIM : 1;
3065 const volatile uint32_t RSVD_IMR : 26;
3069 typedef struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t;
3073 #define ALT_SPIM_IMR_RESET 0x0000003f
3075 #define ALT_SPIM_IMR_OFST 0x2c
3077 #define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
3121 #define ALT_SPIM_ISR_TXEIS_E_INACTIVE 0x0
3127 #define ALT_SPIM_ISR_TXEIS_E_ACTIVE 0x1
3130 #define ALT_SPIM_ISR_TXEIS_LSB 0
3132 #define ALT_SPIM_ISR_TXEIS_MSB 0
3134 #define ALT_SPIM_ISR_TXEIS_WIDTH 1
3136 #define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
3138 #define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
3140 #define ALT_SPIM_ISR_TXEIS_RESET 0x0
3142 #define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
3144 #define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
3170 #define ALT_SPIM_ISR_TXOIS_E_INACTIVE 0x0
3176 #define ALT_SPIM_ISR_TXOIS_E_ACTIVE 0x1
3179 #define ALT_SPIM_ISR_TXOIS_LSB 1
3181 #define ALT_SPIM_ISR_TXOIS_MSB 1
3183 #define ALT_SPIM_ISR_TXOIS_WIDTH 1
3185 #define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
3187 #define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
3189 #define ALT_SPIM_ISR_TXOIS_RESET 0x0
3191 #define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
3193 #define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
3219 #define ALT_SPIM_ISR_RXUIS_E_INACTIVE 0x0
3225 #define ALT_SPIM_ISR_RXUIS_E_ACTIVE 0x1
3228 #define ALT_SPIM_ISR_RXUIS_LSB 2
3230 #define ALT_SPIM_ISR_RXUIS_MSB 2
3232 #define ALT_SPIM_ISR_RXUIS_WIDTH 1
3234 #define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
3236 #define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
3238 #define ALT_SPIM_ISR_RXUIS_RESET 0x0
3240 #define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
3242 #define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
3268 #define ALT_SPIM_ISR_RXOIS_E_INACTIVE 0x0
3274 #define ALT_SPIM_ISR_RXOIS_E_ACTIVE 0x1
3277 #define ALT_SPIM_ISR_RXOIS_LSB 3
3279 #define ALT_SPIM_ISR_RXOIS_MSB 3
3281 #define ALT_SPIM_ISR_RXOIS_WIDTH 1
3283 #define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
3285 #define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
3287 #define ALT_SPIM_ISR_RXOIS_RESET 0x0
3289 #define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
3291 #define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
3317 #define ALT_SPIM_ISR_RXFIS_E_INACTIVE 0x0
3323 #define ALT_SPIM_ISR_RXFIS_E_ACTIVE 0x1
3326 #define ALT_SPIM_ISR_RXFIS_LSB 4
3328 #define ALT_SPIM_ISR_RXFIS_MSB 4
3330 #define ALT_SPIM_ISR_RXFIS_WIDTH 1
3332 #define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
3334 #define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
3336 #define ALT_SPIM_ISR_RXFIS_RESET 0x0
3338 #define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
3340 #define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
3368 #define ALT_SPIM_ISR_MSTIS_E_INACTIVE 0x0
3374 #define ALT_SPIM_ISR_MSTIS_E_ACTIVE 0x1
3377 #define ALT_SPIM_ISR_MSTIS_LSB 5
3379 #define ALT_SPIM_ISR_MSTIS_MSB 5
3381 #define ALT_SPIM_ISR_MSTIS_WIDTH 1
3383 #define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
3385 #define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
3387 #define ALT_SPIM_ISR_MSTIS_RESET 0x0
3389 #define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
3391 #define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
3402 #define ALT_SPIM_ISR_RSVD_ISR_LSB 6
3404 #define ALT_SPIM_ISR_RSVD_ISR_MSB 31
3406 #define ALT_SPIM_ISR_RSVD_ISR_WIDTH 26
3408 #define ALT_SPIM_ISR_RSVD_ISR_SET_MSK 0xffffffc0
3410 #define ALT_SPIM_ISR_RSVD_ISR_CLR_MSK 0x0000003f
3412 #define ALT_SPIM_ISR_RSVD_ISR_RESET 0x0
3414 #define ALT_SPIM_ISR_RSVD_ISR_GET(value) (((value) & 0xffffffc0) >> 6)
3416 #define ALT_SPIM_ISR_RSVD_ISR_SET(value) (((value) << 6) & 0xffffffc0)
3418 #ifndef __ASSEMBLY__
3430 struct ALT_SPIM_ISR_s
3432 const volatile uint32_t TXEIS : 1;
3433 const volatile uint32_t TXOIS : 1;
3434 const volatile uint32_t RXUIS : 1;
3435 const volatile uint32_t RXOIS : 1;
3436 const volatile uint32_t RXFIS : 1;
3437 const volatile uint32_t MSTIS : 1;
3438 const volatile uint32_t RSVD_ISR : 26;
3442 typedef struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t;
3446 #define ALT_SPIM_ISR_RESET 0x00000000
3448 #define ALT_SPIM_ISR_OFST 0x30
3450 #define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
3494 #define ALT_SPIM_RISR_TXEIR_E_INACTIVE 0x0
3500 #define ALT_SPIM_RISR_TXEIR_E_ACTIVE 0x1
3503 #define ALT_SPIM_RISR_TXEIR_LSB 0
3505 #define ALT_SPIM_RISR_TXEIR_MSB 0
3507 #define ALT_SPIM_RISR_TXEIR_WIDTH 1
3509 #define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
3511 #define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
3513 #define ALT_SPIM_RISR_TXEIR_RESET 0x0
3515 #define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
3517 #define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
3543 #define ALT_SPIM_RISR_TXOIR_E_INACTIVE 0x0
3549 #define ALT_SPIM_RISR_TXOIR_E_ACTIVE 0x1
3552 #define ALT_SPIM_RISR_TXOIR_LSB 1
3554 #define ALT_SPIM_RISR_TXOIR_MSB 1
3556 #define ALT_SPIM_RISR_TXOIR_WIDTH 1
3558 #define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
3560 #define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
3562 #define ALT_SPIM_RISR_TXOIR_RESET 0x0
3564 #define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
3566 #define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
3592 #define ALT_SPIM_RISR_RXUIR_E_INACTIVE 0x0
3598 #define ALT_SPIM_RISR_RXUIR_E_ACTIVE 0x1
3601 #define ALT_SPIM_RISR_RXUIR_LSB 2
3603 #define ALT_SPIM_RISR_RXUIR_MSB 2
3605 #define ALT_SPIM_RISR_RXUIR_WIDTH 1
3607 #define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
3609 #define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
3611 #define ALT_SPIM_RISR_RXUIR_RESET 0x0
3613 #define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
3615 #define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
3641 #define ALT_SPIM_RISR_RXOIR_E_INACTIVE 0x0
3647 #define ALT_SPIM_RISR_RXOIR_E_ACTIVE 0x1
3650 #define ALT_SPIM_RISR_RXOIR_LSB 3
3652 #define ALT_SPIM_RISR_RXOIR_MSB 3
3654 #define ALT_SPIM_RISR_RXOIR_WIDTH 1
3656 #define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
3658 #define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
3660 #define ALT_SPIM_RISR_RXOIR_RESET 0x0
3662 #define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
3664 #define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
3690 #define ALT_SPIM_RISR_RXFIR_E_INACTIVE 0x0
3696 #define ALT_SPIM_RISR_RXFIR_E_ACTIVE 0x1
3699 #define ALT_SPIM_RISR_RXFIR_LSB 4
3701 #define ALT_SPIM_RISR_RXFIR_MSB 4
3703 #define ALT_SPIM_RISR_RXFIR_WIDTH 1
3705 #define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
3707 #define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
3709 #define ALT_SPIM_RISR_RXFIR_RESET 0x0
3711 #define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
3713 #define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
3743 #define ALT_SPIM_RISR_MSTIR_E_INACTIVE 0x0
3749 #define ALT_SPIM_RISR_MSTIR_E_ACTIVE 0x1
3752 #define ALT_SPIM_RISR_MSTIR_LSB 5
3754 #define ALT_SPIM_RISR_MSTIR_MSB 5
3756 #define ALT_SPIM_RISR_MSTIR_WIDTH 1
3758 #define ALT_SPIM_RISR_MSTIR_SET_MSK 0x00000020
3760 #define ALT_SPIM_RISR_MSTIR_CLR_MSK 0xffffffdf
3762 #define ALT_SPIM_RISR_MSTIR_RESET 0x0
3764 #define ALT_SPIM_RISR_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
3766 #define ALT_SPIM_RISR_MSTIR_SET(value) (((value) << 5) & 0x00000020)
3777 #define ALT_SPIM_RISR_RSVD_RISR_LSB 6
3779 #define ALT_SPIM_RISR_RSVD_RISR_MSB 31
3781 #define ALT_SPIM_RISR_RSVD_RISR_WIDTH 26
3783 #define ALT_SPIM_RISR_RSVD_RISR_SET_MSK 0xffffffc0
3785 #define ALT_SPIM_RISR_RSVD_RISR_CLR_MSK 0x0000003f
3787 #define ALT_SPIM_RISR_RSVD_RISR_RESET 0x0
3789 #define ALT_SPIM_RISR_RSVD_RISR_GET(value) (((value) & 0xffffffc0) >> 6)
3791 #define ALT_SPIM_RISR_RSVD_RISR_SET(value) (((value) << 6) & 0xffffffc0)
3793 #ifndef __ASSEMBLY__
3805 struct ALT_SPIM_RISR_s
3807 const volatile uint32_t TXEIR : 1;
3808 const volatile uint32_t TXOIR : 1;
3809 const volatile uint32_t RXUIR : 1;
3810 const volatile uint32_t RXOIR : 1;
3811 const volatile uint32_t RXFIR : 1;
3812 const volatile uint32_t MSTIR : 1;
3813 const volatile uint32_t RSVD_RISR : 26;
3817 typedef struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t;
3821 #define ALT_SPIM_RISR_RESET 0x00000000
3823 #define ALT_SPIM_RISR_OFST 0x34
3825 #define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
3853 #define ALT_SPIM_TXOICR_TXOICR_LSB 0
3855 #define ALT_SPIM_TXOICR_TXOICR_MSB 0
3857 #define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
3859 #define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
3861 #define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3863 #define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
3865 #define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3867 #define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3878 #define ALT_SPIM_TXOICR_RSVD_TXOICR_LSB 1
3880 #define ALT_SPIM_TXOICR_RSVD_TXOICR_MSB 31
3882 #define ALT_SPIM_TXOICR_RSVD_TXOICR_WIDTH 31
3884 #define ALT_SPIM_TXOICR_RSVD_TXOICR_SET_MSK 0xfffffffe
3886 #define ALT_SPIM_TXOICR_RSVD_TXOICR_CLR_MSK 0x00000001
3888 #define ALT_SPIM_TXOICR_RSVD_TXOICR_RESET 0x0
3890 #define ALT_SPIM_TXOICR_RSVD_TXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3892 #define ALT_SPIM_TXOICR_RSVD_TXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3894 #ifndef __ASSEMBLY__
3906 struct ALT_SPIM_TXOICR_s
3908 const volatile uint32_t TXOICR : 1;
3909 const volatile uint32_t RSVD_TXOICR : 31;
3913 typedef struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t;
3917 #define ALT_SPIM_TXOICR_RESET 0x00000000
3919 #define ALT_SPIM_TXOICR_OFST 0x38
3921 #define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
3949 #define ALT_SPIM_RXOICR_RXOICR_LSB 0
3951 #define ALT_SPIM_RXOICR_RXOICR_MSB 0
3953 #define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
3955 #define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
3957 #define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3959 #define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
3961 #define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3963 #define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3974 #define ALT_SPIM_RXOICR_RSVD_RXOICR_LSB 1
3976 #define ALT_SPIM_RXOICR_RSVD_RXOICR_MSB 31
3978 #define ALT_SPIM_RXOICR_RSVD_RXOICR_WIDTH 31
3980 #define ALT_SPIM_RXOICR_RSVD_RXOICR_SET_MSK 0xfffffffe
3982 #define ALT_SPIM_RXOICR_RSVD_RXOICR_CLR_MSK 0x00000001
3984 #define ALT_SPIM_RXOICR_RSVD_RXOICR_RESET 0x0
3986 #define ALT_SPIM_RXOICR_RSVD_RXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3988 #define ALT_SPIM_RXOICR_RSVD_RXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3990 #ifndef __ASSEMBLY__
4002 struct ALT_SPIM_RXOICR_s
4004 const volatile uint32_t RXOICR : 1;
4005 const volatile uint32_t RSVD_RXOICR : 31;
4009 typedef struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t;
4013 #define ALT_SPIM_RXOICR_RESET 0x00000000
4015 #define ALT_SPIM_RXOICR_OFST 0x3c
4017 #define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
4045 #define ALT_SPIM_RXUICR_RXUICR_LSB 0
4047 #define ALT_SPIM_RXUICR_RXUICR_MSB 0
4049 #define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
4051 #define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
4053 #define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
4055 #define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
4057 #define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
4059 #define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
4070 #define ALT_SPIM_RXUICR_RSVD_RXUICR_LSB 1
4072 #define ALT_SPIM_RXUICR_RSVD_RXUICR_MSB 31
4074 #define ALT_SPIM_RXUICR_RSVD_RXUICR_WIDTH 31
4076 #define ALT_SPIM_RXUICR_RSVD_RXUICR_SET_MSK 0xfffffffe
4078 #define ALT_SPIM_RXUICR_RSVD_RXUICR_CLR_MSK 0x00000001
4080 #define ALT_SPIM_RXUICR_RSVD_RXUICR_RESET 0x0
4082 #define ALT_SPIM_RXUICR_RSVD_RXUICR_GET(value) (((value) & 0xfffffffe) >> 1)
4084 #define ALT_SPIM_RXUICR_RSVD_RXUICR_SET(value) (((value) << 1) & 0xfffffffe)
4086 #ifndef __ASSEMBLY__
4098 struct ALT_SPIM_RXUICR_s
4100 const volatile uint32_t RXUICR : 1;
4101 const volatile uint32_t RSVD_RXUICR : 31;
4105 typedef struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t;
4109 #define ALT_SPIM_RXUICR_RESET 0x00000000
4111 #define ALT_SPIM_RXUICR_OFST 0x40
4113 #define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
4141 #define ALT_SPIM_MSTICR_MSTICR_LSB 0
4143 #define ALT_SPIM_MSTICR_MSTICR_MSB 0
4145 #define ALT_SPIM_MSTICR_MSTICR_WIDTH 1
4147 #define ALT_SPIM_MSTICR_MSTICR_SET_MSK 0x00000001
4149 #define ALT_SPIM_MSTICR_MSTICR_CLR_MSK 0xfffffffe
4151 #define ALT_SPIM_MSTICR_MSTICR_RESET 0x0
4153 #define ALT_SPIM_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
4155 #define ALT_SPIM_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
4166 #define ALT_SPIM_MSTICR_RSVD_MSTICR_LSB 1
4168 #define ALT_SPIM_MSTICR_RSVD_MSTICR_MSB 31
4170 #define ALT_SPIM_MSTICR_RSVD_MSTICR_WIDTH 31
4172 #define ALT_SPIM_MSTICR_RSVD_MSTICR_SET_MSK 0xfffffffe
4174 #define ALT_SPIM_MSTICR_RSVD_MSTICR_CLR_MSK 0x00000001
4176 #define ALT_SPIM_MSTICR_RSVD_MSTICR_RESET 0x0
4178 #define ALT_SPIM_MSTICR_RSVD_MSTICR_GET(value) (((value) & 0xfffffffe) >> 1)
4180 #define ALT_SPIM_MSTICR_RSVD_MSTICR_SET(value) (((value) << 1) & 0xfffffffe)
4182 #ifndef __ASSEMBLY__
4194 struct ALT_SPIM_MSTICR_s
4196 const volatile uint32_t MSTICR : 1;
4197 const volatile uint32_t RSVD_MSTICR : 31;
4201 typedef struct ALT_SPIM_MSTICR_s ALT_SPIM_MSTICR_t;
4205 #define ALT_SPIM_MSTICR_RESET 0x00000000
4207 #define ALT_SPIM_MSTICR_OFST 0x44
4209 #define ALT_SPIM_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MSTICR_OFST))
4239 #define ALT_SPIM_ICR_ICR_LSB 0
4241 #define ALT_SPIM_ICR_ICR_MSB 0
4243 #define ALT_SPIM_ICR_ICR_WIDTH 1
4245 #define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
4247 #define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
4249 #define ALT_SPIM_ICR_ICR_RESET 0x0
4251 #define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
4253 #define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
4264 #define ALT_SPIM_ICR_RSVD_ICR_LSB 1
4266 #define ALT_SPIM_ICR_RSVD_ICR_MSB 31
4268 #define ALT_SPIM_ICR_RSVD_ICR_WIDTH 31
4270 #define ALT_SPIM_ICR_RSVD_ICR_SET_MSK 0xfffffffe
4272 #define ALT_SPIM_ICR_RSVD_ICR_CLR_MSK 0x00000001
4274 #define ALT_SPIM_ICR_RSVD_ICR_RESET 0x0
4276 #define ALT_SPIM_ICR_RSVD_ICR_GET(value) (((value) & 0xfffffffe) >> 1)
4278 #define ALT_SPIM_ICR_RSVD_ICR_SET(value) (((value) << 1) & 0xfffffffe)
4280 #ifndef __ASSEMBLY__
4292 struct ALT_SPIM_ICR_s
4294 const volatile uint32_t ICR : 1;
4295 const volatile uint32_t RSVD_ICR : 31;
4299 typedef struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t;
4303 #define ALT_SPIM_ICR_RESET 0x00000000
4305 #define ALT_SPIM_ICR_OFST 0x48
4307 #define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
4361 #define ALT_SPIM_DMACR_RDMAE_E_DISABLE 0x0
4367 #define ALT_SPIM_DMACR_RDMAE_E_ENABLED 0x1
4370 #define ALT_SPIM_DMACR_RDMAE_LSB 0
4372 #define ALT_SPIM_DMACR_RDMAE_MSB 0
4374 #define ALT_SPIM_DMACR_RDMAE_WIDTH 1
4376 #define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
4378 #define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
4380 #define ALT_SPIM_DMACR_RDMAE_RESET 0x0
4382 #define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
4384 #define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
4412 #define ALT_SPIM_DMACR_TDMAE_E_DISABLE 0x0
4418 #define ALT_SPIM_DMACR_TDMAE_E_ENABLED 0x1
4421 #define ALT_SPIM_DMACR_TDMAE_LSB 1
4423 #define ALT_SPIM_DMACR_TDMAE_MSB 1
4425 #define ALT_SPIM_DMACR_TDMAE_WIDTH 1
4427 #define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
4429 #define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
4431 #define ALT_SPIM_DMACR_TDMAE_RESET 0x0
4433 #define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
4435 #define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
4446 #define ALT_SPIM_DMACR_RSVD_DMACR_LSB 2
4448 #define ALT_SPIM_DMACR_RSVD_DMACR_MSB 31
4450 #define ALT_SPIM_DMACR_RSVD_DMACR_WIDTH 30
4452 #define ALT_SPIM_DMACR_RSVD_DMACR_SET_MSK 0xfffffffc
4454 #define ALT_SPIM_DMACR_RSVD_DMACR_CLR_MSK 0x00000003
4456 #define ALT_SPIM_DMACR_RSVD_DMACR_RESET 0x0
4458 #define ALT_SPIM_DMACR_RSVD_DMACR_GET(value) (((value) & 0xfffffffc) >> 2)
4460 #define ALT_SPIM_DMACR_RSVD_DMACR_SET(value) (((value) << 2) & 0xfffffffc)
4462 #ifndef __ASSEMBLY__
4474 struct ALT_SPIM_DMACR_s
4476 volatile uint32_t RDMAE : 1;
4477 volatile uint32_t TDMAE : 1;
4478 const volatile uint32_t RSVD_DMACR : 30;
4482 typedef struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t;
4486 #define ALT_SPIM_DMACR_RESET 0x00000000
4488 #define ALT_SPIM_DMACR_OFST 0x4c
4490 #define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
4532 #define ALT_SPIM_DMATDLR_DMATDL_LSB 0
4534 #define ALT_SPIM_DMATDLR_DMATDL_MSB 7
4536 #define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
4538 #define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
4540 #define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
4542 #define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
4544 #define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
4546 #define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
4557 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_LSB 8
4559 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_MSB 31
4561 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_WIDTH 24
4563 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_SET_MSK 0xffffff00
4565 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_CLR_MSK 0x000000ff
4567 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_RESET 0x0
4569 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_GET(value) (((value) & 0xffffff00) >> 8)
4571 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_SET(value) (((value) << 8) & 0xffffff00)
4573 #ifndef __ASSEMBLY__
4585 struct ALT_SPIM_DMATDLR_s
4587 volatile uint32_t DMATDL : 8;
4588 const volatile uint32_t RSVD_DMATDLR : 24;
4592 typedef struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t;
4596 #define ALT_SPIM_DMATDLR_RESET 0x00000000
4598 #define ALT_SPIM_DMATDLR_OFST 0x50
4600 #define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
4640 #define ALT_SPIM_DMARDLR_DMARDL_LSB 0
4642 #define ALT_SPIM_DMARDLR_DMARDL_MSB 7
4644 #define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
4646 #define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
4648 #define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
4650 #define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
4652 #define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
4654 #define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
4665 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_LSB 8
4667 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_MSB 31
4669 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_WIDTH 24
4671 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_SET_MSK 0xffffff00
4673 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_CLR_MSK 0x000000ff
4675 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_RESET 0x0
4677 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_GET(value) (((value) & 0xffffff00) >> 8)
4679 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_SET(value) (((value) << 8) & 0xffffff00)
4681 #ifndef __ASSEMBLY__
4693 struct ALT_SPIM_DMARDLR_s
4695 volatile uint32_t DMARDL : 8;
4696 const volatile uint32_t RSVD_DMARDLR : 24;
4700 typedef struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t;
4704 #define ALT_SPIM_DMARDLR_RESET 0x00000000
4706 #define ALT_SPIM_DMARDLR_OFST 0x54
4708 #define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
4736 #define ALT_SPIM_IDR_IDCODE_LSB 0
4738 #define ALT_SPIM_IDR_IDCODE_MSB 31
4740 #define ALT_SPIM_IDR_IDCODE_WIDTH 32
4742 #define ALT_SPIM_IDR_IDCODE_SET_MSK 0xffffffff
4744 #define ALT_SPIM_IDR_IDCODE_CLR_MSK 0x00000000
4746 #define ALT_SPIM_IDR_IDCODE_RESET 0x5510000
4748 #define ALT_SPIM_IDR_IDCODE_GET(value) (((value) & 0xffffffff) >> 0)
4750 #define ALT_SPIM_IDR_IDCODE_SET(value) (((value) << 0) & 0xffffffff)
4752 #ifndef __ASSEMBLY__
4764 struct ALT_SPIM_IDR_s
4766 const volatile uint32_t IDCODE : 32;
4770 typedef struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t;
4774 #define ALT_SPIM_IDR_RESET 0x05510000
4776 #define ALT_SPIM_IDR_OFST 0x58
4778 #define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
4803 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0
4805 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31
4807 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_WIDTH 32
4809 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_SET_MSK 0xffffffff
4811 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_CLR_MSK 0x00000000
4813 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430302a
4815 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
4817 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
4819 #ifndef __ASSEMBLY__
4831 struct ALT_SPIM_SSI_VERSION_ID_s
4833 const volatile uint32_t SSI_COMP_VERSION : 32;
4837 typedef struct ALT_SPIM_SSI_VERSION_ID_s ALT_SPIM_SSI_VERSION_ID_t;
4841 #define ALT_SPIM_SSI_VERSION_ID_RESET 0x3430302a
4843 #define ALT_SPIM_SSI_VERSION_ID_OFST 0x5c
4845 #define ALT_SPIM_SSI_VERSION_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SSI_VERSION_ID_OFST))
4892 #define ALT_SPIM_DR0_DR0_LSB 0
4894 #define ALT_SPIM_DR0_DR0_MSB 31
4896 #define ALT_SPIM_DR0_DR0_WIDTH 32
4898 #define ALT_SPIM_DR0_DR0_SET_MSK 0xffffffff
4900 #define ALT_SPIM_DR0_DR0_CLR_MSK 0x00000000
4902 #define ALT_SPIM_DR0_DR0_RESET 0x0
4904 #define ALT_SPIM_DR0_DR0_GET(value) (((value) & 0xffffffff) >> 0)
4906 #define ALT_SPIM_DR0_DR0_SET(value) (((value) << 0) & 0xffffffff)
4908 #ifndef __ASSEMBLY__
4920 struct ALT_SPIM_DR0_s
4922 volatile uint32_t dr0 : 32;
4926 typedef struct ALT_SPIM_DR0_s ALT_SPIM_DR0_t;
4930 #define ALT_SPIM_DR0_RESET 0x00000000
4932 #define ALT_SPIM_DR0_OFST 0x60
4934 #define ALT_SPIM_DR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR0_OFST))
4981 #define ALT_SPIM_DR1_DR1_LSB 0
4983 #define ALT_SPIM_DR1_DR1_MSB 31
4985 #define ALT_SPIM_DR1_DR1_WIDTH 32
4987 #define ALT_SPIM_DR1_DR1_SET_MSK 0xffffffff
4989 #define ALT_SPIM_DR1_DR1_CLR_MSK 0x00000000
4991 #define ALT_SPIM_DR1_DR1_RESET 0x0
4993 #define ALT_SPIM_DR1_DR1_GET(value) (((value) & 0xffffffff) >> 0)
4995 #define ALT_SPIM_DR1_DR1_SET(value) (((value) << 0) & 0xffffffff)
4997 #ifndef __ASSEMBLY__
5009 struct ALT_SPIM_DR1_s
5011 volatile uint32_t dr1 : 32;
5015 typedef struct ALT_SPIM_DR1_s ALT_SPIM_DR1_t;
5019 #define ALT_SPIM_DR1_RESET 0x00000000
5021 #define ALT_SPIM_DR1_OFST 0x64
5023 #define ALT_SPIM_DR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR1_OFST))
5070 #define ALT_SPIM_DR2_DR2_LSB 0
5072 #define ALT_SPIM_DR2_DR2_MSB 31
5074 #define ALT_SPIM_DR2_DR2_WIDTH 32
5076 #define ALT_SPIM_DR2_DR2_SET_MSK 0xffffffff
5078 #define ALT_SPIM_DR2_DR2_CLR_MSK 0x00000000
5080 #define ALT_SPIM_DR2_DR2_RESET 0x0
5082 #define ALT_SPIM_DR2_DR2_GET(value) (((value) & 0xffffffff) >> 0)
5084 #define ALT_SPIM_DR2_DR2_SET(value) (((value) << 0) & 0xffffffff)
5086 #ifndef __ASSEMBLY__
5098 struct ALT_SPIM_DR2_s
5100 volatile uint32_t dr2 : 32;
5104 typedef struct ALT_SPIM_DR2_s ALT_SPIM_DR2_t;
5108 #define ALT_SPIM_DR2_RESET 0x00000000
5110 #define ALT_SPIM_DR2_OFST 0x68
5112 #define ALT_SPIM_DR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR2_OFST))
5159 #define ALT_SPIM_DR3_DR3_LSB 0
5161 #define ALT_SPIM_DR3_DR3_MSB 31
5163 #define ALT_SPIM_DR3_DR3_WIDTH 32
5165 #define ALT_SPIM_DR3_DR3_SET_MSK 0xffffffff
5167 #define ALT_SPIM_DR3_DR3_CLR_MSK 0x00000000
5169 #define ALT_SPIM_DR3_DR3_RESET 0x0
5171 #define ALT_SPIM_DR3_DR3_GET(value) (((value) & 0xffffffff) >> 0)
5173 #define ALT_SPIM_DR3_DR3_SET(value) (((value) << 0) & 0xffffffff)
5175 #ifndef __ASSEMBLY__
5187 struct ALT_SPIM_DR3_s
5189 volatile uint32_t dr3 : 32;
5193 typedef struct ALT_SPIM_DR3_s ALT_SPIM_DR3_t;
5197 #define ALT_SPIM_DR3_RESET 0x00000000
5199 #define ALT_SPIM_DR3_OFST 0x6c
5201 #define ALT_SPIM_DR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR3_OFST))
5248 #define ALT_SPIM_DR4_DR4_LSB 0
5250 #define ALT_SPIM_DR4_DR4_MSB 31
5252 #define ALT_SPIM_DR4_DR4_WIDTH 32
5254 #define ALT_SPIM_DR4_DR4_SET_MSK 0xffffffff
5256 #define ALT_SPIM_DR4_DR4_CLR_MSK 0x00000000
5258 #define ALT_SPIM_DR4_DR4_RESET 0x0
5260 #define ALT_SPIM_DR4_DR4_GET(value) (((value) & 0xffffffff) >> 0)
5262 #define ALT_SPIM_DR4_DR4_SET(value) (((value) << 0) & 0xffffffff)
5264 #ifndef __ASSEMBLY__
5276 struct ALT_SPIM_DR4_s
5278 volatile uint32_t dr4 : 32;
5282 typedef struct ALT_SPIM_DR4_s ALT_SPIM_DR4_t;
5286 #define ALT_SPIM_DR4_RESET 0x00000000
5288 #define ALT_SPIM_DR4_OFST 0x70
5290 #define ALT_SPIM_DR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR4_OFST))
5337 #define ALT_SPIM_DR5_DR5_LSB 0
5339 #define ALT_SPIM_DR5_DR5_MSB 31
5341 #define ALT_SPIM_DR5_DR5_WIDTH 32
5343 #define ALT_SPIM_DR5_DR5_SET_MSK 0xffffffff
5345 #define ALT_SPIM_DR5_DR5_CLR_MSK 0x00000000
5347 #define ALT_SPIM_DR5_DR5_RESET 0x0
5349 #define ALT_SPIM_DR5_DR5_GET(value) (((value) & 0xffffffff) >> 0)
5351 #define ALT_SPIM_DR5_DR5_SET(value) (((value) << 0) & 0xffffffff)
5353 #ifndef __ASSEMBLY__
5365 struct ALT_SPIM_DR5_s
5367 volatile uint32_t dr5 : 32;
5371 typedef struct ALT_SPIM_DR5_s ALT_SPIM_DR5_t;
5375 #define ALT_SPIM_DR5_RESET 0x00000000
5377 #define ALT_SPIM_DR5_OFST 0x74
5379 #define ALT_SPIM_DR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR5_OFST))
5426 #define ALT_SPIM_DR6_DR6_LSB 0
5428 #define ALT_SPIM_DR6_DR6_MSB 31
5430 #define ALT_SPIM_DR6_DR6_WIDTH 32
5432 #define ALT_SPIM_DR6_DR6_SET_MSK 0xffffffff
5434 #define ALT_SPIM_DR6_DR6_CLR_MSK 0x00000000
5436 #define ALT_SPIM_DR6_DR6_RESET 0x0
5438 #define ALT_SPIM_DR6_DR6_GET(value) (((value) & 0xffffffff) >> 0)
5440 #define ALT_SPIM_DR6_DR6_SET(value) (((value) << 0) & 0xffffffff)
5442 #ifndef __ASSEMBLY__
5454 struct ALT_SPIM_DR6_s
5456 volatile uint32_t dr6 : 32;
5460 typedef struct ALT_SPIM_DR6_s ALT_SPIM_DR6_t;
5464 #define ALT_SPIM_DR6_RESET 0x00000000
5466 #define ALT_SPIM_DR6_OFST 0x78
5468 #define ALT_SPIM_DR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR6_OFST))
5515 #define ALT_SPIM_DR7_DR7_LSB 0
5517 #define ALT_SPIM_DR7_DR7_MSB 31
5519 #define ALT_SPIM_DR7_DR7_WIDTH 32
5521 #define ALT_SPIM_DR7_DR7_SET_MSK 0xffffffff
5523 #define ALT_SPIM_DR7_DR7_CLR_MSK 0x00000000
5525 #define ALT_SPIM_DR7_DR7_RESET 0x0
5527 #define ALT_SPIM_DR7_DR7_GET(value) (((value) & 0xffffffff) >> 0)
5529 #define ALT_SPIM_DR7_DR7_SET(value) (((value) << 0) & 0xffffffff)
5531 #ifndef __ASSEMBLY__
5543 struct ALT_SPIM_DR7_s
5545 volatile uint32_t dr7 : 32;
5549 typedef struct ALT_SPIM_DR7_s ALT_SPIM_DR7_t;
5553 #define ALT_SPIM_DR7_RESET 0x00000000
5555 #define ALT_SPIM_DR7_OFST 0x7c
5557 #define ALT_SPIM_DR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR7_OFST))
5604 #define ALT_SPIM_DR8_DR8_LSB 0
5606 #define ALT_SPIM_DR8_DR8_MSB 31
5608 #define ALT_SPIM_DR8_DR8_WIDTH 32
5610 #define ALT_SPIM_DR8_DR8_SET_MSK 0xffffffff
5612 #define ALT_SPIM_DR8_DR8_CLR_MSK 0x00000000
5614 #define ALT_SPIM_DR8_DR8_RESET 0x0
5616 #define ALT_SPIM_DR8_DR8_GET(value) (((value) & 0xffffffff) >> 0)
5618 #define ALT_SPIM_DR8_DR8_SET(value) (((value) << 0) & 0xffffffff)
5620 #ifndef __ASSEMBLY__
5632 struct ALT_SPIM_DR8_s
5634 volatile uint32_t dr8 : 32;
5638 typedef struct ALT_SPIM_DR8_s ALT_SPIM_DR8_t;
5642 #define ALT_SPIM_DR8_RESET 0x00000000
5644 #define ALT_SPIM_DR8_OFST 0x80
5646 #define ALT_SPIM_DR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR8_OFST))
5693 #define ALT_SPIM_DR9_DR9_LSB 0
5695 #define ALT_SPIM_DR9_DR9_MSB 31
5697 #define ALT_SPIM_DR9_DR9_WIDTH 32
5699 #define ALT_SPIM_DR9_DR9_SET_MSK 0xffffffff
5701 #define ALT_SPIM_DR9_DR9_CLR_MSK 0x00000000
5703 #define ALT_SPIM_DR9_DR9_RESET 0x0
5705 #define ALT_SPIM_DR9_DR9_GET(value) (((value) & 0xffffffff) >> 0)
5707 #define ALT_SPIM_DR9_DR9_SET(value) (((value) << 0) & 0xffffffff)
5709 #ifndef __ASSEMBLY__
5721 struct ALT_SPIM_DR9_s
5723 volatile uint32_t dr9 : 32;
5727 typedef struct ALT_SPIM_DR9_s ALT_SPIM_DR9_t;
5731 #define ALT_SPIM_DR9_RESET 0x00000000
5733 #define ALT_SPIM_DR9_OFST 0x84
5735 #define ALT_SPIM_DR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR9_OFST))
5782 #define ALT_SPIM_DR10_DR10_LSB 0
5784 #define ALT_SPIM_DR10_DR10_MSB 31
5786 #define ALT_SPIM_DR10_DR10_WIDTH 32
5788 #define ALT_SPIM_DR10_DR10_SET_MSK 0xffffffff
5790 #define ALT_SPIM_DR10_DR10_CLR_MSK 0x00000000
5792 #define ALT_SPIM_DR10_DR10_RESET 0x0
5794 #define ALT_SPIM_DR10_DR10_GET(value) (((value) & 0xffffffff) >> 0)
5796 #define ALT_SPIM_DR10_DR10_SET(value) (((value) << 0) & 0xffffffff)
5798 #ifndef __ASSEMBLY__
5810 struct ALT_SPIM_DR10_s
5812 volatile uint32_t dr10 : 32;
5816 typedef struct ALT_SPIM_DR10_s ALT_SPIM_DR10_t;
5820 #define ALT_SPIM_DR10_RESET 0x00000000
5822 #define ALT_SPIM_DR10_OFST 0x88
5824 #define ALT_SPIM_DR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR10_OFST))
5871 #define ALT_SPIM_DR11_DR11_LSB 0
5873 #define ALT_SPIM_DR11_DR11_MSB 31
5875 #define ALT_SPIM_DR11_DR11_WIDTH 32
5877 #define ALT_SPIM_DR11_DR11_SET_MSK 0xffffffff
5879 #define ALT_SPIM_DR11_DR11_CLR_MSK 0x00000000
5881 #define ALT_SPIM_DR11_DR11_RESET 0x0
5883 #define ALT_SPIM_DR11_DR11_GET(value) (((value) & 0xffffffff) >> 0)
5885 #define ALT_SPIM_DR11_DR11_SET(value) (((value) << 0) & 0xffffffff)
5887 #ifndef __ASSEMBLY__
5899 struct ALT_SPIM_DR11_s
5901 volatile uint32_t dr11 : 32;
5905 typedef struct ALT_SPIM_DR11_s ALT_SPIM_DR11_t;
5909 #define ALT_SPIM_DR11_RESET 0x00000000
5911 #define ALT_SPIM_DR11_OFST 0x8c
5913 #define ALT_SPIM_DR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR11_OFST))
5960 #define ALT_SPIM_DR12_DR12_LSB 0
5962 #define ALT_SPIM_DR12_DR12_MSB 31
5964 #define ALT_SPIM_DR12_DR12_WIDTH 32
5966 #define ALT_SPIM_DR12_DR12_SET_MSK 0xffffffff
5968 #define ALT_SPIM_DR12_DR12_CLR_MSK 0x00000000
5970 #define ALT_SPIM_DR12_DR12_RESET 0x0
5972 #define ALT_SPIM_DR12_DR12_GET(value) (((value) & 0xffffffff) >> 0)
5974 #define ALT_SPIM_DR12_DR12_SET(value) (((value) << 0) & 0xffffffff)
5976 #ifndef __ASSEMBLY__
5988 struct ALT_SPIM_DR12_s
5990 volatile uint32_t dr12 : 32;
5994 typedef struct ALT_SPIM_DR12_s ALT_SPIM_DR12_t;
5998 #define ALT_SPIM_DR12_RESET 0x00000000
6000 #define ALT_SPIM_DR12_OFST 0x90
6002 #define ALT_SPIM_DR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR12_OFST))
6049 #define ALT_SPIM_DR13_DR13_LSB 0
6051 #define ALT_SPIM_DR13_DR13_MSB 31
6053 #define ALT_SPIM_DR13_DR13_WIDTH 32
6055 #define ALT_SPIM_DR13_DR13_SET_MSK 0xffffffff
6057 #define ALT_SPIM_DR13_DR13_CLR_MSK 0x00000000
6059 #define ALT_SPIM_DR13_DR13_RESET 0x0
6061 #define ALT_SPIM_DR13_DR13_GET(value) (((value) & 0xffffffff) >> 0)
6063 #define ALT_SPIM_DR13_DR13_SET(value) (((value) << 0) & 0xffffffff)
6065 #ifndef __ASSEMBLY__
6077 struct ALT_SPIM_DR13_s
6079 volatile uint32_t dr13 : 32;
6083 typedef struct ALT_SPIM_DR13_s ALT_SPIM_DR13_t;
6087 #define ALT_SPIM_DR13_RESET 0x00000000
6089 #define ALT_SPIM_DR13_OFST 0x94
6091 #define ALT_SPIM_DR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR13_OFST))
6138 #define ALT_SPIM_DR14_DR14_LSB 0
6140 #define ALT_SPIM_DR14_DR14_MSB 31
6142 #define ALT_SPIM_DR14_DR14_WIDTH 32
6144 #define ALT_SPIM_DR14_DR14_SET_MSK 0xffffffff
6146 #define ALT_SPIM_DR14_DR14_CLR_MSK 0x00000000
6148 #define ALT_SPIM_DR14_DR14_RESET 0x0
6150 #define ALT_SPIM_DR14_DR14_GET(value) (((value) & 0xffffffff) >> 0)
6152 #define ALT_SPIM_DR14_DR14_SET(value) (((value) << 0) & 0xffffffff)
6154 #ifndef __ASSEMBLY__
6166 struct ALT_SPIM_DR14_s
6168 volatile uint32_t dr14 : 32;
6172 typedef struct ALT_SPIM_DR14_s ALT_SPIM_DR14_t;
6176 #define ALT_SPIM_DR14_RESET 0x00000000
6178 #define ALT_SPIM_DR14_OFST 0x98
6180 #define ALT_SPIM_DR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR14_OFST))
6227 #define ALT_SPIM_DR15_DR15_LSB 0
6229 #define ALT_SPIM_DR15_DR15_MSB 31
6231 #define ALT_SPIM_DR15_DR15_WIDTH 32
6233 #define ALT_SPIM_DR15_DR15_SET_MSK 0xffffffff
6235 #define ALT_SPIM_DR15_DR15_CLR_MSK 0x00000000
6237 #define ALT_SPIM_DR15_DR15_RESET 0x0
6239 #define ALT_SPIM_DR15_DR15_GET(value) (((value) & 0xffffffff) >> 0)
6241 #define ALT_SPIM_DR15_DR15_SET(value) (((value) << 0) & 0xffffffff)
6243 #ifndef __ASSEMBLY__
6255 struct ALT_SPIM_DR15_s
6257 volatile uint32_t dr15 : 32;
6261 typedef struct ALT_SPIM_DR15_s ALT_SPIM_DR15_t;
6265 #define ALT_SPIM_DR15_RESET 0x00000000
6267 #define ALT_SPIM_DR15_OFST 0x9c
6269 #define ALT_SPIM_DR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR15_OFST))
6316 #define ALT_SPIM_DR16_DR16_LSB 0
6318 #define ALT_SPIM_DR16_DR16_MSB 31
6320 #define ALT_SPIM_DR16_DR16_WIDTH 32
6322 #define ALT_SPIM_DR16_DR16_SET_MSK 0xffffffff
6324 #define ALT_SPIM_DR16_DR16_CLR_MSK 0x00000000
6326 #define ALT_SPIM_DR16_DR16_RESET 0x0
6328 #define ALT_SPIM_DR16_DR16_GET(value) (((value) & 0xffffffff) >> 0)
6330 #define ALT_SPIM_DR16_DR16_SET(value) (((value) << 0) & 0xffffffff)
6332 #ifndef __ASSEMBLY__
6344 struct ALT_SPIM_DR16_s
6346 volatile uint32_t dr16 : 32;
6350 typedef struct ALT_SPIM_DR16_s ALT_SPIM_DR16_t;
6354 #define ALT_SPIM_DR16_RESET 0x00000000
6356 #define ALT_SPIM_DR16_OFST 0xa0
6358 #define ALT_SPIM_DR16_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR16_OFST))
6405 #define ALT_SPIM_DR17_DR17_LSB 0
6407 #define ALT_SPIM_DR17_DR17_MSB 31
6409 #define ALT_SPIM_DR17_DR17_WIDTH 32
6411 #define ALT_SPIM_DR17_DR17_SET_MSK 0xffffffff
6413 #define ALT_SPIM_DR17_DR17_CLR_MSK 0x00000000
6415 #define ALT_SPIM_DR17_DR17_RESET 0x0
6417 #define ALT_SPIM_DR17_DR17_GET(value) (((value) & 0xffffffff) >> 0)
6419 #define ALT_SPIM_DR17_DR17_SET(value) (((value) << 0) & 0xffffffff)
6421 #ifndef __ASSEMBLY__
6433 struct ALT_SPIM_DR17_s
6435 volatile uint32_t dr17 : 32;
6439 typedef struct ALT_SPIM_DR17_s ALT_SPIM_DR17_t;
6443 #define ALT_SPIM_DR17_RESET 0x00000000
6445 #define ALT_SPIM_DR17_OFST 0xa4
6447 #define ALT_SPIM_DR17_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR17_OFST))
6494 #define ALT_SPIM_DR18_DR18_LSB 0
6496 #define ALT_SPIM_DR18_DR18_MSB 31
6498 #define ALT_SPIM_DR18_DR18_WIDTH 32
6500 #define ALT_SPIM_DR18_DR18_SET_MSK 0xffffffff
6502 #define ALT_SPIM_DR18_DR18_CLR_MSK 0x00000000
6504 #define ALT_SPIM_DR18_DR18_RESET 0x0
6506 #define ALT_SPIM_DR18_DR18_GET(value) (((value) & 0xffffffff) >> 0)
6508 #define ALT_SPIM_DR18_DR18_SET(value) (((value) << 0) & 0xffffffff)
6510 #ifndef __ASSEMBLY__
6522 struct ALT_SPIM_DR18_s
6524 volatile uint32_t dr18 : 32;
6528 typedef struct ALT_SPIM_DR18_s ALT_SPIM_DR18_t;
6532 #define ALT_SPIM_DR18_RESET 0x00000000
6534 #define ALT_SPIM_DR18_OFST 0xa8
6536 #define ALT_SPIM_DR18_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR18_OFST))
6583 #define ALT_SPIM_DR19_DR19_LSB 0
6585 #define ALT_SPIM_DR19_DR19_MSB 31
6587 #define ALT_SPIM_DR19_DR19_WIDTH 32
6589 #define ALT_SPIM_DR19_DR19_SET_MSK 0xffffffff
6591 #define ALT_SPIM_DR19_DR19_CLR_MSK 0x00000000
6593 #define ALT_SPIM_DR19_DR19_RESET 0x0
6595 #define ALT_SPIM_DR19_DR19_GET(value) (((value) & 0xffffffff) >> 0)
6597 #define ALT_SPIM_DR19_DR19_SET(value) (((value) << 0) & 0xffffffff)
6599 #ifndef __ASSEMBLY__
6611 struct ALT_SPIM_DR19_s
6613 volatile uint32_t dr19 : 32;
6617 typedef struct ALT_SPIM_DR19_s ALT_SPIM_DR19_t;
6621 #define ALT_SPIM_DR19_RESET 0x00000000
6623 #define ALT_SPIM_DR19_OFST 0xac
6625 #define ALT_SPIM_DR19_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR19_OFST))
6672 #define ALT_SPIM_DR20_DR20_LSB 0
6674 #define ALT_SPIM_DR20_DR20_MSB 31
6676 #define ALT_SPIM_DR20_DR20_WIDTH 32
6678 #define ALT_SPIM_DR20_DR20_SET_MSK 0xffffffff
6680 #define ALT_SPIM_DR20_DR20_CLR_MSK 0x00000000
6682 #define ALT_SPIM_DR20_DR20_RESET 0x0
6684 #define ALT_SPIM_DR20_DR20_GET(value) (((value) & 0xffffffff) >> 0)
6686 #define ALT_SPIM_DR20_DR20_SET(value) (((value) << 0) & 0xffffffff)
6688 #ifndef __ASSEMBLY__
6700 struct ALT_SPIM_DR20_s
6702 volatile uint32_t dr20 : 32;
6706 typedef struct ALT_SPIM_DR20_s ALT_SPIM_DR20_t;
6710 #define ALT_SPIM_DR20_RESET 0x00000000
6712 #define ALT_SPIM_DR20_OFST 0xb0
6714 #define ALT_SPIM_DR20_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR20_OFST))
6761 #define ALT_SPIM_DR21_DR21_LSB 0
6763 #define ALT_SPIM_DR21_DR21_MSB 31
6765 #define ALT_SPIM_DR21_DR21_WIDTH 32
6767 #define ALT_SPIM_DR21_DR21_SET_MSK 0xffffffff
6769 #define ALT_SPIM_DR21_DR21_CLR_MSK 0x00000000
6771 #define ALT_SPIM_DR21_DR21_RESET 0x0
6773 #define ALT_SPIM_DR21_DR21_GET(value) (((value) & 0xffffffff) >> 0)
6775 #define ALT_SPIM_DR21_DR21_SET(value) (((value) << 0) & 0xffffffff)
6777 #ifndef __ASSEMBLY__
6789 struct ALT_SPIM_DR21_s
6791 volatile uint32_t dr21 : 32;
6795 typedef struct ALT_SPIM_DR21_s ALT_SPIM_DR21_t;
6799 #define ALT_SPIM_DR21_RESET 0x00000000
6801 #define ALT_SPIM_DR21_OFST 0xb4
6803 #define ALT_SPIM_DR21_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR21_OFST))
6850 #define ALT_SPIM_DR22_DR22_LSB 0
6852 #define ALT_SPIM_DR22_DR22_MSB 31
6854 #define ALT_SPIM_DR22_DR22_WIDTH 32
6856 #define ALT_SPIM_DR22_DR22_SET_MSK 0xffffffff
6858 #define ALT_SPIM_DR22_DR22_CLR_MSK 0x00000000
6860 #define ALT_SPIM_DR22_DR22_RESET 0x0
6862 #define ALT_SPIM_DR22_DR22_GET(value) (((value) & 0xffffffff) >> 0)
6864 #define ALT_SPIM_DR22_DR22_SET(value) (((value) << 0) & 0xffffffff)
6866 #ifndef __ASSEMBLY__
6878 struct ALT_SPIM_DR22_s
6880 volatile uint32_t dr22 : 32;
6884 typedef struct ALT_SPIM_DR22_s ALT_SPIM_DR22_t;
6888 #define ALT_SPIM_DR22_RESET 0x00000000
6890 #define ALT_SPIM_DR22_OFST 0xb8
6892 #define ALT_SPIM_DR22_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR22_OFST))
6939 #define ALT_SPIM_DR23_DR23_LSB 0
6941 #define ALT_SPIM_DR23_DR23_MSB 31
6943 #define ALT_SPIM_DR23_DR23_WIDTH 32
6945 #define ALT_SPIM_DR23_DR23_SET_MSK 0xffffffff
6947 #define ALT_SPIM_DR23_DR23_CLR_MSK 0x00000000
6949 #define ALT_SPIM_DR23_DR23_RESET 0x0
6951 #define ALT_SPIM_DR23_DR23_GET(value) (((value) & 0xffffffff) >> 0)
6953 #define ALT_SPIM_DR23_DR23_SET(value) (((value) << 0) & 0xffffffff)
6955 #ifndef __ASSEMBLY__
6967 struct ALT_SPIM_DR23_s
6969 volatile uint32_t dr23 : 32;
6973 typedef struct ALT_SPIM_DR23_s ALT_SPIM_DR23_t;
6977 #define ALT_SPIM_DR23_RESET 0x00000000
6979 #define ALT_SPIM_DR23_OFST 0xbc
6981 #define ALT_SPIM_DR23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR23_OFST))
7028 #define ALT_SPIM_DR24_DR24_LSB 0
7030 #define ALT_SPIM_DR24_DR24_MSB 31
7032 #define ALT_SPIM_DR24_DR24_WIDTH 32
7034 #define ALT_SPIM_DR24_DR24_SET_MSK 0xffffffff
7036 #define ALT_SPIM_DR24_DR24_CLR_MSK 0x00000000
7038 #define ALT_SPIM_DR24_DR24_RESET 0x0
7040 #define ALT_SPIM_DR24_DR24_GET(value) (((value) & 0xffffffff) >> 0)
7042 #define ALT_SPIM_DR24_DR24_SET(value) (((value) << 0) & 0xffffffff)
7044 #ifndef __ASSEMBLY__
7056 struct ALT_SPIM_DR24_s
7058 volatile uint32_t dr24 : 32;
7062 typedef struct ALT_SPIM_DR24_s ALT_SPIM_DR24_t;
7066 #define ALT_SPIM_DR24_RESET 0x00000000
7068 #define ALT_SPIM_DR24_OFST 0xc0
7070 #define ALT_SPIM_DR24_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR24_OFST))
7117 #define ALT_SPIM_DR25_DR25_LSB 0
7119 #define ALT_SPIM_DR25_DR25_MSB 31
7121 #define ALT_SPIM_DR25_DR25_WIDTH 32
7123 #define ALT_SPIM_DR25_DR25_SET_MSK 0xffffffff
7125 #define ALT_SPIM_DR25_DR25_CLR_MSK 0x00000000
7127 #define ALT_SPIM_DR25_DR25_RESET 0x0
7129 #define ALT_SPIM_DR25_DR25_GET(value) (((value) & 0xffffffff) >> 0)
7131 #define ALT_SPIM_DR25_DR25_SET(value) (((value) << 0) & 0xffffffff)
7133 #ifndef __ASSEMBLY__
7145 struct ALT_SPIM_DR25_s
7147 volatile uint32_t dr25 : 32;
7151 typedef struct ALT_SPIM_DR25_s ALT_SPIM_DR25_t;
7155 #define ALT_SPIM_DR25_RESET 0x00000000
7157 #define ALT_SPIM_DR25_OFST 0xc4
7159 #define ALT_SPIM_DR25_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR25_OFST))
7206 #define ALT_SPIM_DR26_DR26_LSB 0
7208 #define ALT_SPIM_DR26_DR26_MSB 31
7210 #define ALT_SPIM_DR26_DR26_WIDTH 32
7212 #define ALT_SPIM_DR26_DR26_SET_MSK 0xffffffff
7214 #define ALT_SPIM_DR26_DR26_CLR_MSK 0x00000000
7216 #define ALT_SPIM_DR26_DR26_RESET 0x0
7218 #define ALT_SPIM_DR26_DR26_GET(value) (((value) & 0xffffffff) >> 0)
7220 #define ALT_SPIM_DR26_DR26_SET(value) (((value) << 0) & 0xffffffff)
7222 #ifndef __ASSEMBLY__
7234 struct ALT_SPIM_DR26_s
7236 volatile uint32_t dr26 : 32;
7240 typedef struct ALT_SPIM_DR26_s ALT_SPIM_DR26_t;
7244 #define ALT_SPIM_DR26_RESET 0x00000000
7246 #define ALT_SPIM_DR26_OFST 0xc8
7248 #define ALT_SPIM_DR26_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR26_OFST))
7295 #define ALT_SPIM_DR27_DR27_LSB 0
7297 #define ALT_SPIM_DR27_DR27_MSB 31
7299 #define ALT_SPIM_DR27_DR27_WIDTH 32
7301 #define ALT_SPIM_DR27_DR27_SET_MSK 0xffffffff
7303 #define ALT_SPIM_DR27_DR27_CLR_MSK 0x00000000
7305 #define ALT_SPIM_DR27_DR27_RESET 0x0
7307 #define ALT_SPIM_DR27_DR27_GET(value) (((value) & 0xffffffff) >> 0)
7309 #define ALT_SPIM_DR27_DR27_SET(value) (((value) << 0) & 0xffffffff)
7311 #ifndef __ASSEMBLY__
7323 struct ALT_SPIM_DR27_s
7325 volatile uint32_t dr27 : 32;
7329 typedef struct ALT_SPIM_DR27_s ALT_SPIM_DR27_t;
7333 #define ALT_SPIM_DR27_RESET 0x00000000
7335 #define ALT_SPIM_DR27_OFST 0xcc
7337 #define ALT_SPIM_DR27_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR27_OFST))
7384 #define ALT_SPIM_DR28_DR28_LSB 0
7386 #define ALT_SPIM_DR28_DR28_MSB 31
7388 #define ALT_SPIM_DR28_DR28_WIDTH 32
7390 #define ALT_SPIM_DR28_DR28_SET_MSK 0xffffffff
7392 #define ALT_SPIM_DR28_DR28_CLR_MSK 0x00000000
7394 #define ALT_SPIM_DR28_DR28_RESET 0x0
7396 #define ALT_SPIM_DR28_DR28_GET(value) (((value) & 0xffffffff) >> 0)
7398 #define ALT_SPIM_DR28_DR28_SET(value) (((value) << 0) & 0xffffffff)
7400 #ifndef __ASSEMBLY__
7412 struct ALT_SPIM_DR28_s
7414 volatile uint32_t dr28 : 32;
7418 typedef struct ALT_SPIM_DR28_s ALT_SPIM_DR28_t;
7422 #define ALT_SPIM_DR28_RESET 0x00000000
7424 #define ALT_SPIM_DR28_OFST 0xd0
7426 #define ALT_SPIM_DR28_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR28_OFST))
7473 #define ALT_SPIM_DR29_DR29_LSB 0
7475 #define ALT_SPIM_DR29_DR29_MSB 31
7477 #define ALT_SPIM_DR29_DR29_WIDTH 32
7479 #define ALT_SPIM_DR29_DR29_SET_MSK 0xffffffff
7481 #define ALT_SPIM_DR29_DR29_CLR_MSK 0x00000000
7483 #define ALT_SPIM_DR29_DR29_RESET 0x0
7485 #define ALT_SPIM_DR29_DR29_GET(value) (((value) & 0xffffffff) >> 0)
7487 #define ALT_SPIM_DR29_DR29_SET(value) (((value) << 0) & 0xffffffff)
7489 #ifndef __ASSEMBLY__
7501 struct ALT_SPIM_DR29_s
7503 volatile uint32_t dr29 : 32;
7507 typedef struct ALT_SPIM_DR29_s ALT_SPIM_DR29_t;
7511 #define ALT_SPIM_DR29_RESET 0x00000000
7513 #define ALT_SPIM_DR29_OFST 0xd4
7515 #define ALT_SPIM_DR29_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR29_OFST))
7562 #define ALT_SPIM_DR30_DR30_LSB 0
7564 #define ALT_SPIM_DR30_DR30_MSB 31
7566 #define ALT_SPIM_DR30_DR30_WIDTH 32
7568 #define ALT_SPIM_DR30_DR30_SET_MSK 0xffffffff
7570 #define ALT_SPIM_DR30_DR30_CLR_MSK 0x00000000
7572 #define ALT_SPIM_DR30_DR30_RESET 0x0
7574 #define ALT_SPIM_DR30_DR30_GET(value) (((value) & 0xffffffff) >> 0)
7576 #define ALT_SPIM_DR30_DR30_SET(value) (((value) << 0) & 0xffffffff)
7578 #ifndef __ASSEMBLY__
7590 struct ALT_SPIM_DR30_s
7592 volatile uint32_t dr30 : 32;
7596 typedef struct ALT_SPIM_DR30_s ALT_SPIM_DR30_t;
7600 #define ALT_SPIM_DR30_RESET 0x00000000
7602 #define ALT_SPIM_DR30_OFST 0xd8
7604 #define ALT_SPIM_DR30_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR30_OFST))
7651 #define ALT_SPIM_DR31_DR31_LSB 0
7653 #define ALT_SPIM_DR31_DR31_MSB 31
7655 #define ALT_SPIM_DR31_DR31_WIDTH 32
7657 #define ALT_SPIM_DR31_DR31_SET_MSK 0xffffffff
7659 #define ALT_SPIM_DR31_DR31_CLR_MSK 0x00000000
7661 #define ALT_SPIM_DR31_DR31_RESET 0x0
7663 #define ALT_SPIM_DR31_DR31_GET(value) (((value) & 0xffffffff) >> 0)
7665 #define ALT_SPIM_DR31_DR31_SET(value) (((value) << 0) & 0xffffffff)
7667 #ifndef __ASSEMBLY__
7679 struct ALT_SPIM_DR31_s
7681 volatile uint32_t dr31 : 32;
7685 typedef struct ALT_SPIM_DR31_s ALT_SPIM_DR31_t;
7689 #define ALT_SPIM_DR31_RESET 0x00000000
7691 #define ALT_SPIM_DR31_OFST 0xdc
7693 #define ALT_SPIM_DR31_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR31_OFST))
7740 #define ALT_SPIM_DR32_DR32_LSB 0
7742 #define ALT_SPIM_DR32_DR32_MSB 31
7744 #define ALT_SPIM_DR32_DR32_WIDTH 32
7746 #define ALT_SPIM_DR32_DR32_SET_MSK 0xffffffff
7748 #define ALT_SPIM_DR32_DR32_CLR_MSK 0x00000000
7750 #define ALT_SPIM_DR32_DR32_RESET 0x0
7752 #define ALT_SPIM_DR32_DR32_GET(value) (((value) & 0xffffffff) >> 0)
7754 #define ALT_SPIM_DR32_DR32_SET(value) (((value) << 0) & 0xffffffff)
7756 #ifndef __ASSEMBLY__
7768 struct ALT_SPIM_DR32_s
7770 volatile uint32_t dr32 : 32;
7774 typedef struct ALT_SPIM_DR32_s ALT_SPIM_DR32_t;
7778 #define ALT_SPIM_DR32_RESET 0x00000000
7780 #define ALT_SPIM_DR32_OFST 0xe0
7782 #define ALT_SPIM_DR32_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR32_OFST))
7829 #define ALT_SPIM_DR33_DR33_LSB 0
7831 #define ALT_SPIM_DR33_DR33_MSB 31
7833 #define ALT_SPIM_DR33_DR33_WIDTH 32
7835 #define ALT_SPIM_DR33_DR33_SET_MSK 0xffffffff
7837 #define ALT_SPIM_DR33_DR33_CLR_MSK 0x00000000
7839 #define ALT_SPIM_DR33_DR33_RESET 0x0
7841 #define ALT_SPIM_DR33_DR33_GET(value) (((value) & 0xffffffff) >> 0)
7843 #define ALT_SPIM_DR33_DR33_SET(value) (((value) << 0) & 0xffffffff)
7845 #ifndef __ASSEMBLY__
7857 struct ALT_SPIM_DR33_s
7859 volatile uint32_t dr33 : 32;
7863 typedef struct ALT_SPIM_DR33_s ALT_SPIM_DR33_t;
7867 #define ALT_SPIM_DR33_RESET 0x00000000
7869 #define ALT_SPIM_DR33_OFST 0xe4
7871 #define ALT_SPIM_DR33_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR33_OFST))
7918 #define ALT_SPIM_DR34_DR34_LSB 0
7920 #define ALT_SPIM_DR34_DR34_MSB 31
7922 #define ALT_SPIM_DR34_DR34_WIDTH 32
7924 #define ALT_SPIM_DR34_DR34_SET_MSK 0xffffffff
7926 #define ALT_SPIM_DR34_DR34_CLR_MSK 0x00000000
7928 #define ALT_SPIM_DR34_DR34_RESET 0x0
7930 #define ALT_SPIM_DR34_DR34_GET(value) (((value) & 0xffffffff) >> 0)
7932 #define ALT_SPIM_DR34_DR34_SET(value) (((value) << 0) & 0xffffffff)
7934 #ifndef __ASSEMBLY__
7946 struct ALT_SPIM_DR34_s
7948 volatile uint32_t dr34 : 32;
7952 typedef struct ALT_SPIM_DR34_s ALT_SPIM_DR34_t;
7956 #define ALT_SPIM_DR34_RESET 0x00000000
7958 #define ALT_SPIM_DR34_OFST 0xe8
7960 #define ALT_SPIM_DR34_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR34_OFST))
8007 #define ALT_SPIM_DR35_DR35_LSB 0
8009 #define ALT_SPIM_DR35_DR35_MSB 31
8011 #define ALT_SPIM_DR35_DR35_WIDTH 32
8013 #define ALT_SPIM_DR35_DR35_SET_MSK 0xffffffff
8015 #define ALT_SPIM_DR35_DR35_CLR_MSK 0x00000000
8017 #define ALT_SPIM_DR35_DR35_RESET 0x0
8019 #define ALT_SPIM_DR35_DR35_GET(value) (((value) & 0xffffffff) >> 0)
8021 #define ALT_SPIM_DR35_DR35_SET(value) (((value) << 0) & 0xffffffff)
8023 #ifndef __ASSEMBLY__
8035 struct ALT_SPIM_DR35_s
8037 volatile uint32_t dr35 : 32;
8041 typedef struct ALT_SPIM_DR35_s ALT_SPIM_DR35_t;
8045 #define ALT_SPIM_DR35_RESET 0x00000000
8047 #define ALT_SPIM_DR35_OFST 0xec
8049 #define ALT_SPIM_DR35_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR35_OFST))
8099 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_LSB 0
8101 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_MSB 7
8103 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_WIDTH 8
8105 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_SET_MSK 0x000000ff
8107 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_CLR_MSK 0xffffff00
8109 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_RESET 0x0
8111 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_GET(value) (((value) & 0x000000ff) >> 0)
8113 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_SET(value) (((value) << 0) & 0x000000ff)
8124 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_LSB 8
8126 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_MSB 31
8128 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_WIDTH 24
8130 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_SET_MSK 0xffffff00
8132 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_CLR_MSK 0x000000ff
8134 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_RESET 0x0
8136 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_GET(value) (((value) & 0xffffff00) >> 8)
8138 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_SET(value) (((value) << 8) & 0xffffff00)
8140 #ifndef __ASSEMBLY__
8152 struct ALT_SPIM_RX_SAMPLE_DLY_s
8154 volatile uint32_t RSD : 8;
8155 const volatile uint32_t RSVD_RX_SAMPLE_DLY : 24;
8159 typedef struct ALT_SPIM_RX_SAMPLE_DLY_s ALT_SPIM_RX_SAMPLE_DLY_t;
8163 #define ALT_SPIM_RX_SAMPLE_DLY_RESET 0x00000000
8165 #define ALT_SPIM_RX_SAMPLE_DLY_OFST 0xf0
8167 #define ALT_SPIM_RX_SAMPLE_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SAMPLE_DLY_OFST))
8190 #define ALT_SPIM_RSVD_1_RSVD1_LSB 0
8192 #define ALT_SPIM_RSVD_1_RSVD1_MSB 31
8194 #define ALT_SPIM_RSVD_1_RSVD1_WIDTH 32
8196 #define ALT_SPIM_RSVD_1_RSVD1_SET_MSK 0xffffffff
8198 #define ALT_SPIM_RSVD_1_RSVD1_CLR_MSK 0x00000000
8200 #define ALT_SPIM_RSVD_1_RSVD1_RESET 0x0
8202 #define ALT_SPIM_RSVD_1_RSVD1_GET(value) (((value) & 0xffffffff) >> 0)
8204 #define ALT_SPIM_RSVD_1_RSVD1_SET(value) (((value) << 0) & 0xffffffff)
8206 #ifndef __ASSEMBLY__
8218 struct ALT_SPIM_RSVD_1_s
8220 const volatile uint32_t RSVD1 : 32;
8224 typedef struct ALT_SPIM_RSVD_1_s ALT_SPIM_RSVD_1_t;
8228 #define ALT_SPIM_RSVD_1_RESET 0x00000000
8230 #define ALT_SPIM_RSVD_1_OFST 0xf8
8232 #define ALT_SPIM_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_1_OFST))
8255 #define ALT_SPIM_RSVD_2_RSVD2_LSB 0
8257 #define ALT_SPIM_RSVD_2_RSVD2_MSB 31
8259 #define ALT_SPIM_RSVD_2_RSVD2_WIDTH 32
8261 #define ALT_SPIM_RSVD_2_RSVD2_SET_MSK 0xffffffff
8263 #define ALT_SPIM_RSVD_2_RSVD2_CLR_MSK 0x00000000
8265 #define ALT_SPIM_RSVD_2_RSVD2_RESET 0x0
8267 #define ALT_SPIM_RSVD_2_RSVD2_GET(value) (((value) & 0xffffffff) >> 0)
8269 #define ALT_SPIM_RSVD_2_RSVD2_SET(value) (((value) << 0) & 0xffffffff)
8271 #ifndef __ASSEMBLY__
8283 struct ALT_SPIM_RSVD_2_s
8285 const volatile uint32_t RSVD2 : 32;
8289 typedef struct ALT_SPIM_RSVD_2_s ALT_SPIM_RSVD_2_t;
8293 #define ALT_SPIM_RSVD_2_RESET 0x00000000
8295 #define ALT_SPIM_RSVD_2_OFST 0xfc
8297 #define ALT_SPIM_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_2_OFST))
8299 #ifndef __ASSEMBLY__
8313 volatile ALT_SPIM_CTRLR0_t CTRLR0;
8314 volatile ALT_SPIM_CTRLR1_t CTRLR1;
8315 volatile ALT_SPIM_SSIENR_t SSIENR;
8316 volatile ALT_SPIM_MWCR_t MWCR;
8317 volatile ALT_SPIM_SER_t SER;
8318 volatile ALT_SPIM_BAUDR_t BAUDR;
8319 volatile ALT_SPIM_TXFTLR_t TXFTLR;
8320 volatile ALT_SPIM_RXFTLR_t RXFTLR;
8321 volatile ALT_SPIM_TXFLR_t TXFLR;
8322 volatile ALT_SPIM_RXFLR_t RXFLR;
8323 volatile ALT_SPIM_SR_t SR;
8324 volatile ALT_SPIM_IMR_t IMR;
8325 volatile ALT_SPIM_ISR_t ISR;
8326 volatile ALT_SPIM_RISR_t RISR;
8327 volatile ALT_SPIM_TXOICR_t TXOICR;
8328 volatile ALT_SPIM_RXOICR_t RXOICR;
8329 volatile ALT_SPIM_RXUICR_t RXUICR;
8330 volatile ALT_SPIM_MSTICR_t MSTICR;
8331 volatile ALT_SPIM_ICR_t ICR;
8332 volatile ALT_SPIM_DMACR_t DMACR;
8333 volatile ALT_SPIM_DMATDLR_t DMATDLR;
8334 volatile ALT_SPIM_DMARDLR_t DMARDLR;
8335 volatile ALT_SPIM_IDR_t IDR;
8336 volatile ALT_SPIM_SSI_VERSION_ID_t SSI_VERSION_ID;
8337 volatile ALT_SPIM_DR0_t DR0;
8338 volatile ALT_SPIM_DR1_t DR1;
8339 volatile ALT_SPIM_DR2_t DR2;
8340 volatile ALT_SPIM_DR3_t DR3;
8341 volatile ALT_SPIM_DR4_t DR4;
8342 volatile ALT_SPIM_DR5_t DR5;
8343 volatile ALT_SPIM_DR6_t DR6;
8344 volatile ALT_SPIM_DR7_t DR7;
8345 volatile ALT_SPIM_DR8_t DR8;
8346 volatile ALT_SPIM_DR9_t DR9;
8347 volatile ALT_SPIM_DR10_t DR10;
8348 volatile ALT_SPIM_DR11_t DR11;
8349 volatile ALT_SPIM_DR12_t DR12;
8350 volatile ALT_SPIM_DR13_t DR13;
8351 volatile ALT_SPIM_DR14_t DR14;
8352 volatile ALT_SPIM_DR15_t DR15;
8353 volatile ALT_SPIM_DR16_t DR16;
8354 volatile ALT_SPIM_DR17_t DR17;
8355 volatile ALT_SPIM_DR18_t DR18;
8356 volatile ALT_SPIM_DR19_t DR19;
8357 volatile ALT_SPIM_DR20_t DR20;
8358 volatile ALT_SPIM_DR21_t DR21;
8359 volatile ALT_SPIM_DR22_t DR22;
8360 volatile ALT_SPIM_DR23_t DR23;
8361 volatile ALT_SPIM_DR24_t DR24;
8362 volatile ALT_SPIM_DR25_t DR25;
8363 volatile ALT_SPIM_DR26_t DR26;
8364 volatile ALT_SPIM_DR27_t DR27;
8365 volatile ALT_SPIM_DR28_t DR28;
8366 volatile ALT_SPIM_DR29_t DR29;
8367 volatile ALT_SPIM_DR30_t DR30;
8368 volatile ALT_SPIM_DR31_t DR31;
8369 volatile ALT_SPIM_DR32_t DR32;
8370 volatile ALT_SPIM_DR33_t DR33;
8371 volatile ALT_SPIM_DR34_t DR34;
8372 volatile ALT_SPIM_DR35_t DR35;
8373 volatile ALT_SPIM_RX_SAMPLE_DLY_t RX_SAMPLE_DLY;
8374 volatile uint32_t _pad_0xf4_0xf7;
8375 volatile ALT_SPIM_RSVD_1_t RSVD_1;
8376 volatile ALT_SPIM_RSVD_2_t RSVD_2;
8380 typedef struct ALT_SPIM_s ALT_SPIM_t;
8382 struct ALT_SPIM_raw_s
8384 volatile uint32_t CTRLR0;
8385 volatile uint32_t CTRLR1;
8386 volatile uint32_t SSIENR;
8387 volatile uint32_t MWCR;
8388 volatile uint32_t SER;
8389 volatile uint32_t BAUDR;
8390 volatile uint32_t TXFTLR;
8391 volatile uint32_t RXFTLR;
8392 volatile uint32_t TXFLR;
8393 volatile uint32_t RXFLR;
8394 volatile uint32_t SR;
8395 volatile uint32_t IMR;
8396 volatile uint32_t ISR;
8397 volatile uint32_t RISR;
8398 volatile uint32_t TXOICR;
8399 volatile uint32_t RXOICR;
8400 volatile uint32_t RXUICR;
8401 volatile uint32_t MSTICR;
8402 volatile uint32_t ICR;
8403 volatile uint32_t DMACR;
8404 volatile uint32_t DMATDLR;
8405 volatile uint32_t DMARDLR;
8406 volatile uint32_t IDR;
8407 volatile uint32_t SSI_VERSION_ID;
8408 volatile uint32_t DR0;
8409 volatile uint32_t DR1;
8410 volatile uint32_t DR2;
8411 volatile uint32_t DR3;
8412 volatile uint32_t DR4;
8413 volatile uint32_t DR5;
8414 volatile uint32_t DR6;
8415 volatile uint32_t DR7;
8416 volatile uint32_t DR8;
8417 volatile uint32_t DR9;
8418 volatile uint32_t DR10;
8419 volatile uint32_t DR11;
8420 volatile uint32_t DR12;
8421 volatile uint32_t DR13;
8422 volatile uint32_t DR14;
8423 volatile uint32_t DR15;
8424 volatile uint32_t DR16;
8425 volatile uint32_t DR17;
8426 volatile uint32_t DR18;
8427 volatile uint32_t DR19;
8428 volatile uint32_t DR20;
8429 volatile uint32_t DR21;
8430 volatile uint32_t DR22;
8431 volatile uint32_t DR23;
8432 volatile uint32_t DR24;
8433 volatile uint32_t DR25;
8434 volatile uint32_t DR26;
8435 volatile uint32_t DR27;
8436 volatile uint32_t DR28;
8437 volatile uint32_t DR29;
8438 volatile uint32_t DR30;
8439 volatile uint32_t DR31;
8440 volatile uint32_t DR32;
8441 volatile uint32_t DR33;
8442 volatile uint32_t DR34;
8443 volatile uint32_t DR35;
8444 volatile uint32_t RX_SAMPLE_DLY;
8445 volatile uint32_t _pad_0xf4_0xf7;
8446 volatile uint32_t RSVD_1;
8447 volatile uint32_t RSVD_2;
8451 typedef struct ALT_SPIM_raw_s ALT_SPIM_raw_t;