Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_fpga_manager.h
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32 
33 /*
34  * $Id: //acds/rel/20.1std/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_fpga_manager.h#1 $
35  */
36 
37 #ifndef __ALT_FPGA_MGR_H__
38 #define __ALT_FPGA_MGR_H__
39 
40 #include "hwlib.h"
41 #include "alt_dma.h"
42 #include <stdio.h>
43 
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif /* __cplusplus */
48 
67 #ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
68 #define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
69 #endif
70 
78 ALT_STATUS_CODE alt_fpga_init(void);
79 
86 ALT_STATUS_CODE alt_fpga_uninit(void);
87 
108 ALT_STATUS_CODE alt_fpga_control_enable(void);
109 
118 ALT_STATUS_CODE alt_fpga_control_disable(void);
119 
128 bool alt_fpga_control_is_enabled(void);
129 
134 typedef enum ALT_FPGA_STATE_e
135 {
147 
155 
163 
170 
177 
183 
195 
197 
204 
210 {
216 
222 
228 
234 
240 
246 
252 
258 
268 
278 
288 
293 
295 
312 uint32_t alt_fpga_mon_status_get(void);
313 
329 ALT_STATUS_CODE alt_fpga_reset_assert(void);
330 
345 ALT_STATUS_CODE alt_fpga_reset_deassert(void);
346 
367 {
373 
379 
385 
391 
397 
403 
409 
415 
421 
427 
433 
439 
444 
446 
457 
478 ALT_STATUS_CODE alt_fpga_cfg_mode_set(ALT_FPGA_CFG_MODE_t cfg_mode);
479 
523 typedef int32_t (*alt_fpga_istream_t)(void* buf, size_t buf_len, void* user_data);
524 
564 ALT_STATUS_CODE alt_fpga_configure(const void* cfg_buf,
565  size_t cfg_buf_len);
566 
567 #if ALT_FPGA_ENABLE_DMA_SUPPORT
568 
603 ALT_STATUS_CODE alt_fpga_configure_dma(const void* cfg_buf,
604  size_t cfg_buf_len,
605  ALT_DMA_CHANNEL_t dma_channel);
606 
607 #endif
608 
643 ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream,
644  void * user_data);
645 
646 #if ALT_FPGA_ENABLE_DMA_SUPPORT
647 
685 ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream,
686  void * user_data,
687  ALT_DMA_CHANNEL_t dma_channel);
688 
689 #endif
690 
751 ALT_STATUS_CODE alt_fpga_man_irq_disable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
752 
775 ALT_STATUS_CODE alt_fpga_man_irq_enable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
776 
788 uint32_t alt_fpga_man_irq_type_get(ALT_FPGA_MON_STATUS_t mon_stat_mask);
789 
804 ALT_STATUS_CODE alt_fpga_man_irq_type_set(ALT_FPGA_MON_STATUS_t mon_stat_mask,
805  ALT_FPGA_MON_STATUS_t mon_stat_config);
806 
817 uint32_t alt_fpga_man_irq_pol_get(ALT_FPGA_MON_STATUS_t mon_stat_mask);
818 
833 ALT_STATUS_CODE alt_fpga_man_irq_pol_set(ALT_FPGA_MON_STATUS_t mon_stat_mask,
834  ALT_FPGA_MON_STATUS_t mon_stat_config);
835 
856 typedef enum ALT_FPGA_GPI_e
857 {
859  ALT_FPGA_GPI_0 = (int32_t)(1UL << 0),
860 
862  ALT_FPGA_GPI_1 = (int32_t)(1UL << 1),
863 
865  ALT_FPGA_GPI_2 = (int32_t)(1UL << 2),
866 
868  ALT_FPGA_GPI_3 = (int32_t)(1UL << 3),
869 
871  ALT_FPGA_GPI_4 = (int32_t)(1UL << 4),
872 
874  ALT_FPGA_GPI_5 = (int32_t)(1UL << 5),
875 
877  ALT_FPGA_GPI_6 = (int32_t)(1UL << 6),
878 
880  ALT_FPGA_GPI_7 = (int32_t)(1UL << 7),
881 
883  ALT_FPGA_GPI_8 = (int32_t)(1UL << 8),
884 
886  ALT_FPGA_GPI_9 = (int32_t)(1UL << 9),
887 
889  ALT_FPGA_GPI_10 = (int32_t)(1UL << 10),
890 
892  ALT_FPGA_GPI_11 = (int32_t)(1UL << 11),
893 
895  ALT_FPGA_GPI_12 = (int32_t)(1UL << 12),
896 
898  ALT_FPGA_GPI_13 = (int32_t)(1UL << 13),
899 
901  ALT_FPGA_GPI_14 = (int32_t)(1UL << 14),
902 
904  ALT_FPGA_GPI_15 = (int32_t)(1UL << 15),
905 
907  ALT_FPGA_GPI_16 = (int32_t)(1UL << 16),
908 
910  ALT_FPGA_GPI_17 = (int32_t)(1UL << 17),
911 
913  ALT_FPGA_GPI_18 = (int32_t)(1UL << 18),
914 
916  ALT_FPGA_GPI_19 = (int32_t)(1UL << 19),
917 
919  ALT_FPGA_GPI_20 = (int32_t)(1UL << 20),
920 
922  ALT_FPGA_GPI_21 = (int32_t)(1UL << 21),
923 
925  ALT_FPGA_GPI_22 = (int32_t)(1UL << 22),
926 
928  ALT_FPGA_GPI_23 = (int32_t)(1UL << 23),
929 
931  ALT_FPGA_GPI_24 = (int32_t)(1UL << 24),
932 
934  ALT_FPGA_GPI_25 = (int32_t)(1UL << 25),
935 
937  ALT_FPGA_GPI_26 = (int32_t)(1UL << 26),
938 
940  ALT_FPGA_GPI_27 = (int32_t)(1UL << 27),
941 
943  ALT_FPGA_GPI_28 = (int32_t)(1UL << 28),
944 
946  ALT_FPGA_GPI_29 = (int32_t)(1UL << 29),
947 
949  ALT_FPGA_GPI_30 = (int32_t)(1UL << 30),
950 
952  ALT_FPGA_GPI_31 = (int32_t)(1UL << 31)
953 
955 
973 uint32_t alt_fpga_gpi_read(uint32_t mask);
974 
979 typedef enum ALT_FPGA_GPO_e
980 {
982  ALT_FPGA_GPO_0 = (int32_t)(1UL << 0),
983 
985  ALT_FPGA_GPO_1 = (int32_t)(1UL << 1),
986 
988  ALT_FPGA_GPO_2 = (int32_t)(1UL << 2),
989 
991  ALT_FPGA_GPO_3 = (int32_t)(1UL << 3),
992 
994  ALT_FPGA_GPO_4 = (int32_t)(1UL << 4),
995 
997  ALT_FPGA_GPO_5 = (int32_t)(1UL << 5),
998 
1000  ALT_FPGA_GPO_6 = (int32_t)(1UL << 6),
1001 
1003  ALT_FPGA_GPO_7 = (int32_t)(1UL << 7),
1004 
1006  ALT_FPGA_GPO_8 = (int32_t)(1UL << 8),
1007 
1009  ALT_FPGA_GPO_9 = (int32_t)(1UL << 9),
1010 
1012  ALT_FPGA_GPO_10 = (int32_t)(1UL << 10),
1013 
1015  ALT_FPGA_GPO_11 = (int32_t)(1UL << 11),
1016 
1018  ALT_FPGA_GPO_12 = (int32_t)(1UL << 12),
1019 
1021  ALT_FPGA_GPO_13 = (int32_t)(1UL << 13),
1022 
1024  ALT_FPGA_GPO_14 = (int32_t)(1UL << 14),
1025 
1027  ALT_FPGA_GPO_15 = (int32_t)(1UL << 15),
1028 
1030  ALT_FPGA_GPO_16 = (int32_t)(1UL << 16),
1031 
1033  ALT_FPGA_GPO_17 = (int32_t)(1UL << 17),
1034 
1036  ALT_FPGA_GPO_18 = (int32_t)(1UL << 18),
1037 
1039  ALT_FPGA_GPO_19 = (int32_t)(1UL << 19),
1040 
1042  ALT_FPGA_GPO_20 = (int32_t)(1UL << 20),
1043 
1045  ALT_FPGA_GPO_21 = (int32_t)(1UL << 21),
1046 
1048  ALT_FPGA_GPO_22 = (int32_t)(1UL << 22),
1049 
1051  ALT_FPGA_GPO_23 = (int32_t)(1UL << 23),
1052 
1054  ALT_FPGA_GPO_24 = (int32_t)(1UL << 24),
1055 
1057  ALT_FPGA_GPO_25 = (int32_t)(1UL << 25),
1058 
1060  ALT_FPGA_GPO_26 = (int32_t)(1UL << 26),
1061 
1063  ALT_FPGA_GPO_27 = (int32_t)(1UL << 27),
1064 
1066  ALT_FPGA_GPO_28 = (int32_t)(1UL << 28),
1067 
1069  ALT_FPGA_GPO_29 = (int32_t)(1UL << 29),
1070 
1072  ALT_FPGA_GPO_30 = (int32_t)(1UL << 30),
1073 
1075  ALT_FPGA_GPO_31 = (int32_t)(1UL << 31)
1076 
1077 } ALT_FPGA_GPO_t;
1078 
1103 ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value);
1104 
1113 #ifdef __cplusplus
1114 }
1115 #endif /* __cplusplus */
1116 
1117 #endif /* __ALT_FPGA_MGR_H__ */