ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC |
16-bit Passive Parallel with Fast power on reset delay; No Design Security; No Data Compression.
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ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC |
16-bit Passive Parallel with Fast power on reset delay; With Design Security; No Data Compression.
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ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_DC |
16-bit Passive Parallel with Fast power on reset delay; No design security; With Data Compression.
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ALT_FPGA_CFG_MODE_PP16_FAST_AES_DC |
16-bit Passive Parallel with Fast power on reset delay; With design security; With Data Compression.
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ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC |
32-bit Passive Parallel with Fast power on reset delay; No Design Security; No Data Compression.
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ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC |
32-bit Passive Parallel with Fast power on reset delay; With design security; No Data Comression.
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ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_DC |
32-bit Passive Parallel with Fast power on reset delay; No design security; With Data Compression. This is the default configuration.
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ALT_FPGA_CFG_MODE_PP32_FAST_AES_DC |
32-bit Passive Parallel with Fast power on reset delay; With design security; With Data Compression.
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ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC |
16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.
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ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC |
16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.
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ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC |
16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.
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ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC |
16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.
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ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC |
16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.
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ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC |
16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.
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ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC |
32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.
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ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC |
32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.
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ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC |
32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.
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ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC |
32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.
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ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC |
32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.
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ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC |
32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.
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ALT_FPGA_CFG_MODE_UNKNOWN |
Unknown FPGA Configuration Mode.
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