Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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Error Correcting Code (ECC) Management for Arria 10 SoC

Description

This module provides programmatic access and control of the Error-Correcting Code (ECC) protection features for the embedded RAM blocks in HPS peripherals.

ECC protection can be enabled or disabled for each of the following HPS peripheral embedded RAM blocks:

All ECC protected peripherals support detection of single bit, correctable errors and double bit, non-correctable errors.

With the exception of L2 cache data RAM, each of the ECC protected memories generates single and double bit interrupts to the global interrupt controller (GIC) and sets error status condition bits in the ECC Manager. The L2 cache interrupt only generates single and double bit interrupts to the global interrupt controller (GIC) - no error status conditions are set in the ECC Manager.

When ECC protection is enabled, RAM data should first be written before ever being read. Otherwise the ECC syndrome encoding bits for each memory location probably contain random uninitialized data that will result in spurious ECC errors. A utility function is provided to guarantee proper initialization is performed on a memory block once ECC is enabled.

Fault injection capabilities for single, correctable errors and double, non-correctable errors are provided for test purposes.

Typedefs

typedef enum ALT_ECC_RAM_ENUM_e ALT_ECC_RAM_ENUM_t
 
typedef enum ALT_ECC_STATUS_e ALT_ECC_STATUS_t
 

ENUMS

enum  ALT_ECC_RAM_ENUM_e {
  ALT_ECC_RAM_L2_DATA = 1, ALT_ECC_RAM_OCRAM = 2, ALT_ECC_RAM_USB0 = 3, ALT_ECC_RAM_USB1 = 4,
  ALT_ECC_RAM_EMAC0 = 5, ALT_ECC_RAM_EMAC1 = 6, ALT_ECC_RAM_EMAC2 = 7, ALT_ECC_RAM_DMA = 8,
  ALT_ECC_RAM_NAND = 9, ALT_ECC_RAM_QSPI = 10, ALT_ECC_RAM_SDMMC = 11, ALT_ECC_RAM_L2_DATA,
  ALT_ECC_RAM_OCRAM, ALT_ECC_RAM_USB0, ALT_ECC_RAM_USB1, ALT_ECC_RAM_EMAC0,
  ALT_ECC_RAM_EMAC1, ALT_ECC_RAM_DMA, ALT_ECC_RAM_CAN0, ALT_ECC_RAM_CAN1,
  ALT_ECC_RAM_NAND, ALT_ECC_RAM_QSPI, ALT_ECC_RAM_SDMMC
}
 
enum  ALT_ECC_STATUS_e {
  ALT_ECC_STATUS_L2_BYTE_WR = 0x1, ALT_ECC_STATUS_L2_SERR = 0x2, ALT_ECC_STATUS_L2_DERR = 0x4, ALT_ECC_STATUS_OCRAM_SERR = 0x1,
  ALT_ECC_STATUS_OCRAM_DERR = 0x2, ALT_ECC_STATUS_USB0_SERR = 0x1, ALT_ECC_STATUS_USB0_DERR = 0x2, ALT_ECC_STATUS_USB1_SERR = 0x1,
  ALT_ECC_STATUS_USB1_DERR = 0x2, ALT_ECC_STATUS_EMAC0_TX_FIFO_SERR = 0x1, ALT_ECC_STATUS_EMAC0_TX_FIFO_DERR = 0x2, ALT_ECC_STATUS_EMAC0_RX_FIFO_SERR = 0x4,
  ALT_ECC_STATUS_EMAC0_RX_FIFO_DERR = 0x8, ALT_ECC_STATUS_EMAC1_TX_FIFO_SERR = 0x1, ALT_ECC_STATUS_EMAC1_TX_FIFO_DERR = 0x2, ALT_ECC_STATUS_EMAC1_RX_FIFO_SERR = 0x4,
  ALT_ECC_STATUS_EMAC1_RX_FIFO_DERR = 0x8, ALT_ECC_STATUS_EMAC2_TX_FIFO_SERR = 0x1, ALT_ECC_STATUS_EMAC2_TX_FIFO_DERR = 0x2, ALT_ECC_STATUS_EMAC2_RX_FIFO_SERR = 0x4,
  ALT_ECC_STATUS_EMAC2_RX_FIFO_DERR = 0x8, ALT_ECC_STATUS_DMA_SERR = 0x1, ALT_ECC_STATUS_DMA_DERR = 0x2, ALT_ECC_STATUS_NAND_BUFFER_SERR = 0x1,
  ALT_ECC_STATUS_NAND_BUFFER_DERR = 0x2, ALT_ECC_STATUS_NAND_WR_FIFO_SERR = 0x4, ALT_ECC_STATUS_NAND_WR_FIFO_DERR = 0x8, ALT_ECC_STATUS_NAND_RD_FIFO_SERR = 0x10,
  ALT_ECC_STATUS_NAND_RD_FIFO_DERR = 0x20, ALT_ECC_STATUS_QSPI_SERR = 0x1, ALT_ECC_STATUS_QSPI_DERR = 0x2, ALT_ECC_STATUS_SDMMC_PORT_A_SERR = 0x1,
  ALT_ECC_STATUS_SDMMC_PORT_A_DERR = 0x2, ALT_ECC_STATUS_SDMMC_PORT_B_SERR = 0x4, ALT_ECC_STATUS_SDMMC_PORT_B_DERR = 0x8
}
 

Functions

ALT_STATUS_CODE alt_ecc_init (void)
 
ALT_STATUS_CODE alt_ecc_uninit (void)
 
ALT_STATUS_CODE alt_ecc_start (ALT_ECC_RAM_ENUM_t ram_block)
 
ALT_STATUS_CODE alt_ecc_stop (ALT_ECC_RAM_ENUM_t ram_block)
 
ALT_STATUS_CODE alt_ecc_is_enabled (ALT_ECC_RAM_ENUM_t ram_block)
 
ALT_STATUS_CODE alt_ecc_status_get (ALT_ECC_RAM_ENUM_t ram_block, uint32_t *status)
 
ALT_STATUS_CODE alt_ecc_status_get_next (ALT_ECC_RAM_ENUM_t *ram_block, uint32_t *status)
 
ALT_STATUS_CODE alt_ecc_status_clear (ALT_ECC_RAM_ENUM_t ram_block, uint32_t ecc_mask)
 
ALT_STATUS_CODE alt_ecc_status_int_enable (ALT_ECC_RAM_ENUM_t ram_block)
 
ALT_STATUS_CODE alt_ecc_status_int_disable (ALT_ECC_RAM_ENUM_t ram_block)
 
ALT_STATUS_CODE alt_ecc_serr_inject (ALT_ECC_RAM_ENUM_t ram_block, uintptr_t location, uint32_t mem_size)
 
ALT_STATUS_CODE alt_ecc_derr_inject (ALT_ECC_RAM_ENUM_t ram_block, uintptr_t location, uint32_t mem_size)
 

Typedef Documentation

This type enumerates the ECC protected RAM blocks embedded in HPS peripherals.

This type definition enumerates the ECC status conditions for each of the HPS embedded RAM blocks.

The enumerations serve as masks for the ECC status conditions monitored in each of the individual embedded RAM blocks. If ECC protection is enabled on the selected RAM block, then a mask bit corresponding to the type of ECC error is set to 1 if the error occurs.

Additionally, when any of these ECC error conditions occur, then an ECC interrupt signal is asserted.

Interrupt sources are cleared by calling alt_ecc_status_clear(). The ECC interrupt sources are enabled by calling alt_ecc_status_int_enable(). This causes the selected RAM block ECC status to contribute to the ALT_INT_INTERRUPT_SERR_GLOBAL and ALT_INT_INTERRUPT_DERR_GLOBAL interrupt generation.

Enumeration Type Documentation

This type enumerates the ECC protected RAM blocks embedded in HPS peripherals.

Enumerator:
ALT_ECC_RAM_L2_DATA 

L2 Cache Data RAM.

ALT_ECC_RAM_OCRAM 

On-chip RAM.

ALT_ECC_RAM_USB0 

USB0 Controller RAM.

ALT_ECC_RAM_USB1 

USB1 Controller RAM.

ALT_ECC_RAM_EMAC0 

EMAC0 Receive/Transmit Data FIFO Buffer RAMs.

ALT_ECC_RAM_EMAC1 

EMAC1 Receive/Transmit Data FIFO Buffer RAMs.

ALT_ECC_RAM_EMAC2 

EMAC2 Receive/Transmit Data FIFO Buffer RAMs.

ALT_ECC_RAM_DMA 

DMA Controller RAM.

ALT_ECC_RAM_NAND 

NAND Controller Buffer, Read FIFO, Write FIFO RAMs.

ALT_ECC_RAM_QSPI 

QSPI Controller RAM.

ALT_ECC_RAM_SDMMC 

SD/MMC Controller Port A and Port B RAMs.

ALT_ECC_RAM_L2_DATA 

L2 Cache Data RAM

ALT_ECC_RAM_OCRAM 

On-chip RAM

ALT_ECC_RAM_USB0 

USB0 Controller RAM

ALT_ECC_RAM_USB1 

USB1 Controller RAM

ALT_ECC_RAM_EMAC0 

EMAC0 Receive/Transmit Data FIFO Buffer RAMs

ALT_ECC_RAM_EMAC1 

EMAC1 Receive/Transmit Data FIFO Buffer RAMs

ALT_ECC_RAM_DMA 

DMA Controller RAM

ALT_ECC_RAM_CAN0 

CAN0 RAM

ALT_ECC_RAM_CAN1 

CAN1 RAM

ALT_ECC_RAM_NAND 

NAND Controller Buffer, Read FIFO, Write FIFO RAMs

ALT_ECC_RAM_QSPI 

QSPI Controller RAM

ALT_ECC_RAM_SDMMC 

SD/MMC Controller Port A and Port B RAMs

This type definition enumerates the ECC status conditions for each of the HPS embedded RAM blocks.

The enumerations serve as masks for the ECC status conditions monitored in each of the individual embedded RAM blocks. If ECC protection is enabled on the selected RAM block, then a mask bit corresponding to the type of ECC error is set to 1 if the error occurs.

Additionally, when any of these ECC error conditions occur, then an ECC interrupt signal is asserted.

Interrupt sources are cleared by calling alt_ecc_status_clear(). The ECC interrupt sources are enabled by calling alt_ecc_status_int_enable(). This causes the selected RAM block ECC status to contribute to the ALT_INT_INTERRUPT_SERR_GLOBAL and ALT_INT_INTERRUPT_DERR_GLOBAL interrupt generation.

Enumerator:
ALT_ECC_STATUS_L2_BYTE_WR 

L2 cache ECC protection bits are not valid because a cache write violated data width and/or alignment requirements.

ALT_ECC_STATUS_L2_SERR 

L2 Cache ECC single bit, correctable error status.

ALT_ECC_STATUS_L2_DERR 

L2 Cache ECC double bit, non-correctable error status.

ALT_ECC_STATUS_OCRAM_SERR 

On-chip RAM ECC single bit, correctable error status.

ALT_ECC_STATUS_OCRAM_DERR 

On-chip RAM ECC double bit, non-correctable error status.

ALT_ECC_STATUS_USB0_SERR 

USB0 Controller ECC single bit, correctable error status.

ALT_ECC_STATUS_USB0_DERR 

USB0 Controller ECC double bit, non-correctable error status.

ALT_ECC_STATUS_USB1_SERR 

USB1 Controller ECC single bit, correctable error status.

ALT_ECC_STATUS_USB1_DERR 

USB1 Controller ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC0_TX_FIFO_SERR 

EMAC0 Transmit Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC0_TX_FIFO_DERR 

EMAC0 Transmit Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC0_RX_FIFO_SERR 

EMAC0 Receive Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC0_RX_FIFO_DERR 

EMAC0 Receive Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC1_TX_FIFO_SERR 

EMAC1 Transmit Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC1_TX_FIFO_DERR 

EMAC1 Transmit Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC1_RX_FIFO_SERR 

EMAC1 Receive Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC1_RX_FIFO_DERR 

EMAC1 Receive Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC2_TX_FIFO_SERR 

EMAC2 Transmit Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC2_TX_FIFO_DERR 

EMAC2 Transmit Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_EMAC2_RX_FIFO_SERR 

EMAC2 Receive Data FIFO Buffer ECC single bit, correctable error status.

ALT_ECC_STATUS_EMAC2_RX_FIFO_DERR 

EMAC2 Receive Data FIFO Buffer ECC double bit, non-correctable error status.

ALT_ECC_STATUS_DMA_SERR 

DMA Controller ECC single bit, correctable error status.

ALT_ECC_STATUS_DMA_DERR 

DMA Controller ECC double bit, non-correctable error status.

ALT_ECC_STATUS_NAND_BUFFER_SERR 

NAND Controller Buffer RAM ECC single bit, correctable error status.

ALT_ECC_STATUS_NAND_BUFFER_DERR 

NAND Controller Buffer RAM ECC double bit, non-correctable error status.

ALT_ECC_STATUS_NAND_WR_FIFO_SERR 

NAND Controller Write FIFO ECC single bit, correctable error status.

ALT_ECC_STATUS_NAND_WR_FIFO_DERR 

NAND Controller Write FIFO ECC double bit, non-correctable error status.

ALT_ECC_STATUS_NAND_RD_FIFO_SERR 

NAND Controller Read FIFO ECC single bit, correctable error status.

ALT_ECC_STATUS_NAND_RD_FIFO_DERR 

NAND Controller Read FIFO ECC double bit, non-correctable error status.

ALT_ECC_STATUS_QSPI_SERR 

QSPI Controller ECC single bit, correctable error status.

ALT_ECC_STATUS_QSPI_DERR 

QSPI Controller ECC double bit, non-correctable error status.

ALT_ECC_STATUS_SDMMC_PORT_A_SERR 

SD/MMC Controller Port A ECC single bit, correctable error status.

ALT_ECC_STATUS_SDMMC_PORT_A_DERR 

SD/MMC Controller Port A ECC double bit, non-correctable error status.

ALT_ECC_STATUS_SDMMC_PORT_B_SERR 

SD/MMC Controller Port B ECC single bit, correctable error status.

ALT_ECC_STATUS_SDMMC_PORT_B_DERR 

SD/MMC Controller Port B ECC double bit, non-correctable error status.

Function Documentation

ALT_STATUS_CODE alt_ecc_init ( void  )

Initializes the ECC subsystem. This API should be called before any other ECC related operation.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORError status.
ALT_STATUS_CODE alt_ecc_uninit ( void  )

Uninitializes the ECC subsystem. This API should be called after all other ECC related operation.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORError status.
ALT_STATUS_CODE alt_ecc_start ( ALT_ECC_RAM_ENUM_t  ram_block)

Initializes and starts ECC protection for the specified embedded RAM block.

This function performs any necessary initialization on the embedded RAM block for the specified peripheral. The decision on whether to enable ECC protection for the peripheral embedded RAM block should be made before commencing normal operational use of the peripheral. Ideally, ECC protection for a peripheral should be enabled immediately after calling the peripheral's initialization function and calling the alt_ecc_init() function designating the applicable peripheral embedded RAM block.

For example, the proper initialization sequence for enabling ECC for the QSPI controller embedded RAM block is:

    alt_qspi_init();                    // Initialize the QSPI controller.
    alt_qspi_enable();                  // Enable the QSPI controller.
    alt_ecc_init();                     // Initialize the ECC subsystem.
    alt_ecc_start(ALT_ECC_RAM_QSPI);    // Bring up ECC protection for QSPI.

NOTE: The contents of the embedded RAM block are overwritten during initialization. This should not normally present a problem as the presumption is that this routine is called as part of the peripheral's initialization sequence. As well, any special RAM configurations may be overwritten as part of the initialization. Particularly, the L2 data RAM may alter the lockdown settings.

Parameters
ram_blockThe RAM block to initialize.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe ram_block argument is invalid.
ALT_E_TMOTimeout initializing RAM block contents.
ALT_STATUS_CODE alt_ecc_stop ( ALT_ECC_RAM_ENUM_t  ram_block)

Stops and Uninitializes ECC protection for the specified embedded RAM block.

Parameters
ram_blockThe RAM block to uninitialize.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe ram_block argument is invalid.
ALT_STATUS_CODE alt_ecc_is_enabled ( ALT_ECC_RAM_ENUM_t  ram_block)

Returns ALT_E_TRUE if the specified RAM block is enabled for ECC protection and ALT_E_FALSE otherwise.

Parameters
ram_blockThe RAM block to check for ECC protection enablement.
Return values
ALT_E_TRUEECC protection is enabled.
ALT_E_FALSEECC protection is not enabled.
ALT_E_BAD_ARGThe ram_block argument is invalid.
ALT_STATUS_CODE alt_ecc_status_get ( ALT_ECC_RAM_ENUM_t  ram_block,
uint32_t *  status 
)

Returns an ECC error status bit mask for the specified RAM block.

The returned bit mask reflects the ECC status conditions for the specified RAM block.

Parameters
ram_blockThe RAM block to return the ECC error status mask for.
status[out] An ECC status condition bit mask is returned indicating the single bit, correctable (SERR) and/or double bit, non-correctable error (DERR) conditions set for the specified RAM block. A set (1) bit indicates an error detection for the corresponding ECC error type mask.
Return values
ALT_E_TRUEECC protection is enabled.
ALT_E_FALSEECC protection is not enabled.
ALT_E_BAD_ARGThe ram_block argument is invalid.
ALT_STATUS_CODE alt_ecc_status_get_next ( ALT_ECC_RAM_ENUM_t ram_block,
uint32_t *  status 
)

Scans the status of all ECC enabled RAM blocks and reports an active ECC status and the associated RAM block.

Parameters
ram_block[out] A RAM block that has status to report.
status[out] An ECC status condition bit mask is returned indicating the single bit, correctable (SERR) and/or double bit, non-correctable error (DERR) conditions set for the specified RAM block. A set (1) bit indicates an error detection for the corresponding ECC error type mask.
Return values
ALT_E_ERRORNo RAM blocks have ECC status to report. The output values for ram_block and status should be ignored.
ALT_E_SUCCESS
ALT_STATUS_CODE alt_ecc_status_clear ( ALT_ECC_RAM_ENUM_t  ram_block,
uint32_t  ecc_mask 
)

Clears the selected ECC error conditions for the specified RAM block.

A bit mask is returned containing indications of any single bit, correctable (SERR) and/or double bit, non-correctable error (DERR) occurrences for the specified RAM block. A 1 indicates an error detection of the corresponding error type mask position.

Parameters
ram_blockThe RAM block to clear the ECC error condition statuses for.
ecc_maskA bit mask specification of the ECC error condition statuses (ALT_ECC_STATUS_t) to clear.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORAn invalid ecc_mask was specified.
ALT_E_BAD_ARGEither the ram_block or ecc_mask argument is invalid.
ALT_STATUS_CODE alt_ecc_status_int_enable ( ALT_ECC_RAM_ENUM_t  ram_block)

Enables the particular RAM block ECC status to trigger the system interrupt ALT_INT_INTERRUPT_SERR_GLOBAL and ALT_INT_INTERRUPT_DERR_GLOBAL generation.

Parameters
ram_blockThe RAM block to clear the ECC error condition statuses for.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORFailure status.
ALT_E_BAD_ARGThe ram_block is invalid.
ALT_STATUS_CODE alt_ecc_status_int_disable ( ALT_ECC_RAM_ENUM_t  ram_block)

Disables the particular RAM block ECC status from triggering the system interrupt ALT_INT_INTERRUPT_SERR_GLOBAL and ALT_INT_INTERRUPT_DERR_GLOBAL generation.

Parameters
ram_blockThe RAM block to clear the ECC error condition statuses for.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORFailure status.
ALT_E_BAD_ARGThe ram_block is invalid.
ALT_STATUS_CODE alt_ecc_serr_inject ( ALT_ECC_RAM_ENUM_t  ram_block,
uintptr_t  location,
uint32_t  mem_size 
)

Injects a single bit, correctable error into the specified ECC protected RAM block for test purposes. For RAM blocks which have mutliple RAM sub-blocks, all sub-blocks are injected. This affects the EMAC0, EMAC1, EMAC2, NAND, and SDMMC.

ECC protection is required to be enabled on the RAM block.

For error injection into L2, this API may alter the memory cached state in L1 and L2.

Parameters
ram_blockThe RAM block to inject the ECC error into.
locationFor L2, this speicifies the virtual address of a cache line where the error will be injected. For all other ROM blocks, this parameter specifies the index into the protected memory. The maximum value value varies depending on the size and organization of that memory.
mem_sizeFor SDMMC, this specifies how much of the memory will written and read. For all other RAM blocks, it is not used.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe ram_block argument is invalid or location in valid for the specified RAM.
ALT_E_BAD_OPERATIONECC is not enabled on the specified RAM block.
ALT_STATUS_CODE alt_ecc_derr_inject ( ALT_ECC_RAM_ENUM_t  ram_block,
uintptr_t  location,
uint32_t  mem_size 
)

Injects a double bit, non-correctable error into the specified ECC protected RAM block for test purposes. For RAM blocks which have mutliple RAM sub-blocks, all sub-blocks are injected. This affects the EMAC0, EMAC1, EMAC2, NAND, and SDMMC.

ECC protection is required to be enabled on the RAM block.

For error injection into L2, this API may alter the memory cached state in L1 and L2.

Parameters
ram_blockThe RAM block to disable ECC protection for.
locationFor L2, this speicifies the virtual address of a cache line where the error will be injected. For all other ROM blocks, this parameter specifies the index into the protected memory. The maximum value value varies depending on the size and organization of that memory.
mem_sizeFor SDMMC, this specifies how much of the memory will be written and read. For all other RAM blocks, it is not used.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_E_BAD_ARGThe ram_block argument is invalid or location in valid for the specified RAM.
ALT_E_BAD_OPERATIONECC is not enabled on the specified RAM block.