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alt_spi.h
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1 /******************************************************************************
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31 ******************************************************************************/
32 
33 /*
34  * $Id: //acds/main/embedded/ip/hps/armv8/hwlib/include/alt_spi.h#3 $
35  */
36 
41 #ifndef __ALT_SPI_H__
42 #define __ALT_SPI_H__
43 
44 #include "hwlib.h"
45 #include "alt_clock_manager.h"
46 #include "socal/alt_spis.h"
47 #include "socal/alt_spim.h"
48 #include "socal/alt_sysmgr.h"
49 #include "socal/hps.h"
50 #include "socal/socal.h"
51 
52 #ifdef __cplusplus
53 extern "C"
54 {
55 #endif /* __cplusplus */
56 
57 /******************************************************************************/
73 typedef enum ALT_SPI_CTLR_e
74 {
80 
90 typedef enum ALT_SPI_FRF_e
91 {
103 } ALT_SPI_FRF_t;
104 
111 typedef enum ALT_SPI_SCPOL_e
112 {
116 
126 typedef enum ALT_SPI_SCPH_e
127 {
131 
136 typedef enum ALT_SPI_DFS_e
137 {
151 } ALT_SPI_DFS_t;
152 
157 typedef enum ALT_SPI_TMOD_e
158 {
164 
168 typedef enum ALT_SPI_OP_MODE_e
169 {
173 
174 /*
175  * A pointer or handle to the SPI controller device instance. The ALT_SPI_DEV_t is
176  * initialized by a call to alt_spi_init() and subsequently used by the other SPI
177  * controller API functions as a reference to a specific device.
178  */
179 typedef struct ALT_SPI_DEV_s
180 {
181  void * location;
183  alt_freq_t clock_freq;
185  uint32_t last_slave_mask;
187  uint32_t last_transfer_mode;
189  ALT_SPI_OP_MODE_t op_mode;
191 } ALT_SPI_DEV_t;
192 
197 typedef struct ALT_SPI_CONFIG_s
198 {
233  bool slave_output_enable;
255  bool loopback_mode;
270 } __attribute__((aligned(4))) ALT_SPI_CONFIG_t;
271 
279 typedef enum ALT_SPI_MW_MODE_e
280 {
284 
289 typedef enum ALT_SPI_SS_e
290 {
291  ALT_SPI_SS0 = 1UL << 0,
292  ALT_SPI_SS1 = 1UL << 1,
293  ALT_SPI_SS2 = 1UL << 2,
294  ALT_SPI_SS3 = 1UL << 3
295 } ALT_SPI_SS_t;
302 typedef enum ALT_SPI_MW_DIR_e
303 {
312 
316 #define ALT_SPI_MW_CTL_FRAME_SIZE_MAX (16)
317 
322 typedef struct ALT_SPI_MW_CONFIG_s
323 {
324  uint32_t ctl_frame_size;
340  bool handshake_enabled;
352 } __attribute__((aligned(4))) ALT_SPI_MW_CONFIG_t;
353 
367 ALT_STATUS_CODE alt_spi_init(const ALT_SPI_CTLR_t spi, ALT_SPI_DEV_t *spi_dev);
368 
378 ALT_STATUS_CODE alt_spi_reset(ALT_SPI_DEV_t * spi_dev);
379 
393 ALT_STATUS_CODE alt_spi_uninit(ALT_SPI_DEV_t *spi_dev);
394 
408 ALT_STATUS_CODE alt_spi_disable(ALT_SPI_DEV_t *spi_dev);
409 
419 ALT_STATUS_CODE alt_spi_enable(ALT_SPI_DEV_t *spi_dev);
420 
431 ALT_STATUS_CODE alt_spi_is_enabled(ALT_SPI_DEV_t *spi_dev);
432 
448 ALT_STATUS_CODE alt_spi_is_busy(ALT_SPI_DEV_t *spi_dev);
449 
464 ALT_STATUS_CODE alt_spi_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_CONFIG_t *cfg);
465 
480 ALT_STATUS_CODE alt_spi_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_CONFIG_t *cfg);
481 
498 ALT_STATUS_CODE alt_spi_mw_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_MW_CONFIG_t *cfg);
499 
514 ALT_STATUS_CODE alt_spi_mw_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_MW_CONFIG_t *cfg);
515 
519 #define ALT_SPI_SLAVE_MASK_ALL 0xF
520 
537 ALT_STATUS_CODE alt_spi_slave_select_disable(ALT_SPI_DEV_t *spi_dev,
538  const uint32_t mask);
539 
560 ALT_STATUS_CODE alt_spi_slave_select_enable(ALT_SPI_DEV_t *spi_dev,
561  const uint32_t mask);
562 
578 ALT_STATUS_CODE alt_spi_divider_get(ALT_SPI_DEV_t *spi_dev, uint32_t *div);
579 
606 ALT_STATUS_CODE alt_spi_divider_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div);
607 
624 ALT_STATUS_CODE alt_spi_speed_get(ALT_SPI_DEV_t * spi_dev,
625  uint32_t * speed_in_hz);
626 
640 ALT_STATUS_CODE alt_spi_speed_set(ALT_SPI_DEV_t * spi_dev,
641  uint32_t speed_in_hz);
642 
656 ALT_STATUS_CODE alt_spi_num_data_frames_get(ALT_SPI_DEV_t *spi_dev, uint32_t *num_data_frames);
657 
678 ALT_STATUS_CODE alt_spi_num_data_frames_set(ALT_SPI_DEV_t *spi_dev, const uint32_t num_data_frames);
679 
680 /******************************************************************************/
735 typedef enum ALT_SPI_STATUS_e
736 {
737  ALT_SPI_STATUS_TXEI = 1UL << 0,
738  ALT_SPI_STATUS_TXOI = 1UL << 1,
739  ALT_SPI_STATUS_RXUI = 1UL << 2,
740  ALT_SPI_STATUS_RXOI = 1UL << 3,
741  ALT_SPI_STATUS_RXFI = 1UL << 4,
744 
762 ALT_STATUS_CODE alt_spi_int_status_get(ALT_SPI_DEV_t *spi_dev,
763  uint32_t *status);
764 
783 ALT_STATUS_CODE alt_spi_int_raw_status_get(ALT_SPI_DEV_t *spi_dev,
784  uint32_t *status);
785 
805 ALT_STATUS_CODE alt_spi_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
806 
832 ALT_STATUS_CODE alt_spi_int_disable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
833 
859 ALT_STATUS_CODE alt_spi_int_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
860 
863 /******************************************************************************/
881 #define ALT_SPI_RXD_SAMPLE_DELAY_MAX 4
882 
896 ALT_STATUS_CODE alt_spi_rx_sample_delay_get(ALT_SPI_DEV_t *spi_dev, uint32_t *delay);
897 
911 ALT_STATUS_CODE alt_spi_rx_sample_delay_set(ALT_SPI_DEV_t *spi_dev, const uint32_t delay);
912 
915 /******************************************************************************/
933 #define ALT_SPI_RX_FIFO_NUM_ENTRIES 256
934 
949 ALT_STATUS_CODE alt_spi_rx_fifo_deq(ALT_SPI_DEV_t *spi_dev, uint16_t *data);
950 
960 ALT_STATUS_CODE alt_spi_rx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev);
961 
971 ALT_STATUS_CODE alt_spi_rx_fifo_is_full(ALT_SPI_DEV_t *spi_dev);
972 
985 ALT_STATUS_CODE alt_spi_rx_fifo_level_get(ALT_SPI_DEV_t *spi_dev,
986  uint32_t *num_entries);
987 
1000 ALT_STATUS_CODE alt_spi_rx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev,
1001  uint8_t *threshold);
1002 
1015 ALT_STATUS_CODE alt_spi_rx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev,
1016  const uint8_t threshold);
1017 
1020 /******************************************************************************/
1038 #define ALT_SPI_TX_FIFO_NUM_ENTRIES 256
1039 
1056 ALT_STATUS_CODE alt_spi_tx_fifo_enq(ALT_SPI_DEV_t *spi_dev, const uint16_t data);
1057 
1067 ALT_STATUS_CODE alt_spi_tx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev);
1068 
1078 ALT_STATUS_CODE alt_spi_tx_fifo_is_full(ALT_SPI_DEV_t *spi_dev);
1079 
1092 ALT_STATUS_CODE alt_spi_tx_fifo_level_get(ALT_SPI_DEV_t *spi_dev,
1093  uint32_t *num_entries);
1094 
1107 ALT_STATUS_CODE alt_spi_tx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev,
1108  uint8_t *threshold);
1109 
1122 ALT_STATUS_CODE alt_spi_tx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev,
1123  const uint8_t threshold);
1124 
1127 /******************************************************************************/
1144 /******************************************************************************/
1189 ALT_STATUS_CODE alt_spi_master_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1190  const uint32_t slave_select,
1191  const size_t num_frames,
1192  const uint16_t * tx_buf,
1193  uint16_t * rx_buf);
1194 
1223 ALT_STATUS_CODE alt_spi_master_tx_transfer(ALT_SPI_DEV_t *spi_dev,
1224  const uint32_t slave_select,
1225  const size_t num_frames,
1226  const uint16_t * tx_buf);
1227 
1254 ALT_STATUS_CODE alt_spi_master_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1255  const uint32_t slave_select,
1256  const size_t num_frames,
1257  uint16_t * rx_buf);
1258 
1291 ALT_STATUS_CODE alt_spi_master_eeprom_transfer(ALT_SPI_DEV_t *spi_dev,
1292  const uint32_t slave_select,
1293  const uint8_t opcode,
1294  const uint16_t eeprom_addr,
1295  const size_t num_frames,
1296  uint16_t * rx_buf);
1297 
1300 /******************************************************************************/
1341 ALT_STATUS_CODE alt_spi_slave_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1342  const uint16_t * tx_buf,
1343  uint16_t * rx_buf,
1344  const size_t buf_len);
1345 
1370 ALT_STATUS_CODE alt_spi_slave_tx_transfer(ALT_SPI_DEV_t *spi_dev,
1371  const uint16_t * tx_buf,
1372  const size_t buf_len);
1373 
1397 ALT_STATUS_CODE alt_spi_slave_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1398  uint16_t * rx_buf,
1399  const size_t buf_len);
1400 
1405 /******************************************************************************/
1432 ALT_STATUS_CODE alt_spi_dma_tx_disable(ALT_SPI_DEV_t *spi_dev);
1433 
1450 ALT_STATUS_CODE alt_spi_dma_tx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level);
1451 
1461 ALT_STATUS_CODE alt_spi_dma_rx_disable(ALT_SPI_DEV_t *spi_dev);
1462 
1479 ALT_STATUS_CODE alt_spi_dma_rx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level);
1480 
1485 #ifdef __cplusplus
1486 }
1487 #endif /* __cplusplus */
1488 #endif /* __ALT_SPI_H__ */