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alt_ecc_hmc_ocp.h
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32 
33 /* Altera - ALT_ECC_HMC_OCP */
34 
35 #ifndef __ALT_SOCAL_ECC_HMC_OCP_H__
36 #define __ALT_SOCAL_ECC_HMC_OCP_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_ECC_HMC_OCP
50  *
51  */
52 /*
53  * Register : IP_REV_ID - IP_REV_ID
54  *
55  * IDO Register
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:--------------------------------
61  * [15:0] | RW | 0x0 | ALT_ECC_HMC_OCP_IP_REV_ID_SIREV
62  * [31:16] | ??? | 0x0 | *UNDEFINED*
63  *
64  */
65 /*
66  * Field : SIREV
67  *
68  * IP Rev #These bits indicate the silicon revision number
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field. */
74 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_MSB 15
77 /* The width in bits of the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_WIDTH 16
79 /* The mask used to set the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field value. */
80 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 /* The mask used to clear the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 /* The reset value of the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field. */
84 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_RESET 0x0
85 /* Extracts the ALT_ECC_HMC_OCP_IP_REV_ID_SIREV field value from a register. */
86 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 /* Produces a ALT_ECC_HMC_OCP_IP_REV_ID_SIREV register field value suitable for setting the register. */
88 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_ECC_HMC_OCP_IP_REV_ID.
100  */
101 struct ALT_ECC_HMC_OCP_IP_REV_ID_s
102 {
103  uint32_t SIREV : 16; /* ALT_ECC_HMC_OCP_IP_REV_ID_SIREV */
104  uint32_t : 16; /* *UNDEFINED* */
105 };
106 
107 /* The typedef declaration for register ALT_ECC_HMC_OCP_IP_REV_ID. */
108 typedef volatile struct ALT_ECC_HMC_OCP_IP_REV_ID_s ALT_ECC_HMC_OCP_IP_REV_ID_t;
109 #endif /* __ASSEMBLY__ */
110 
111 /* The reset value of the ALT_ECC_HMC_OCP_IP_REV_ID register. */
112 #define ALT_ECC_HMC_OCP_IP_REV_ID_RESET 0x00000000
113 /* The byte offset of the ALT_ECC_HMC_OCP_IP_REV_ID register from the beginning of the component. */
114 #define ALT_ECC_HMC_OCP_IP_REV_ID_OFST 0x0
115 
116 /*
117  * Register : DDRIOCTRL
118  *
119  * DDR IO Control Register
120  *
121  * Register Layout
122  *
123  * Bits | Access | Reset | Description
124  * :-------|:-------|:------|:---------------------------------
125  * [1:0] | RW | 0x0 | ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE
126  * [31:2] | ??? | 0x0 | *UNDEFINED*
127  *
128  */
129 /*
130  * Field : IO_SIZE
131  *
132  * External Configuration of DDR IO size.
133  *
134  * These bits are configured at start to indicate the external DDR IO size.
135  *
136  * 2b00 = DDR IO x16. default value after reset
137  *
138  * 2b01 = DDR IO x32
139  *
140  * 2b10 = DDR IO x64
141  *
142  * Field Access Macros:
143  *
144  */
145 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field. */
146 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_LSB 0
147 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field. */
148 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_MSB 1
149 /* The width in bits of the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field. */
150 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_WIDTH 2
151 /* The mask used to set the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field value. */
152 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET_MSK 0x00000003
153 /* The mask used to clear the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field value. */
154 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_CLR_MSK 0xfffffffc
155 /* The reset value of the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field. */
156 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_RESET 0x0
157 /* Extracts the ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE field value from a register. */
158 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_GET(value) (((value) & 0x00000003) >> 0)
159 /* Produces a ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE register field value suitable for setting the register. */
160 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET(value) (((value) << 0) & 0x00000003)
161 
162 #ifndef __ASSEMBLY__
163 /*
164  * WARNING: The C register and register group struct declarations are provided for
165  * convenience and illustrative purposes. They should, however, be used with
166  * caution as the C language standard provides no guarantees about the alignment or
167  * atomicity of device memory accesses. The recommended practice for writing
168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
169  * alt_write_word() functions.
170  *
171  * The struct declaration for register ALT_ECC_HMC_OCP_DDRIOCTL.
172  */
173 struct ALT_ECC_HMC_OCP_DDRIOCTL_s
174 {
175  uint32_t IO_SIZE : 2; /* ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE */
176  uint32_t : 30; /* *UNDEFINED* */
177 };
178 
179 /* The typedef declaration for register ALT_ECC_HMC_OCP_DDRIOCTL. */
180 typedef volatile struct ALT_ECC_HMC_OCP_DDRIOCTL_s ALT_ECC_HMC_OCP_DDRIOCTL_t;
181 #endif /* __ASSEMBLY__ */
182 
183 /* The reset value of the ALT_ECC_HMC_OCP_DDRIOCTL register. */
184 #define ALT_ECC_HMC_OCP_DDRIOCTL_RESET 0x00000000
185 /* The byte offset of the ALT_ECC_HMC_OCP_DDRIOCTL register from the beginning of the component. */
186 #define ALT_ECC_HMC_OCP_DDRIOCTL_OFST 0x8
187 
188 /*
189  * Register : DDRCALSTAT
190  *
191  * DDR Calibration Register
192  *
193  * Register Layout
194  *
195  * Bits | Access | Reset | Description
196  * :-------|:-------|:------|:-------------------------------
197  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_DDRCALSTAT_CAL
198  * [31:1] | ??? | 0x0 | *UNDEFINED*
199  *
200  */
201 /*
202  * Field : CAL
203  *
204  * DDR calibration status.
205  *
206  * Indicates the DDR calibration status.
207  *
208  * 1'b0: When set to 0, calibration is either on going, hasn't started or failed.
209  *
210  * 1'b1: When set to 1, calibration has succeeded.
211  *
212  * Field Access Macros:
213  *
214  */
215 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field. */
216 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_LSB 0
217 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field. */
218 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_MSB 0
219 /* The width in bits of the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field. */
220 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_WIDTH 1
221 /* The mask used to set the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field value. */
222 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET_MSK 0x00000001
223 /* The mask used to clear the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field value. */
224 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_CLR_MSK 0xfffffffe
225 /* The reset value of the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field. */
226 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_RESET 0x0
227 /* Extracts the ALT_ECC_HMC_OCP_DDRCALSTAT_CAL field value from a register. */
228 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_GET(value) (((value) & 0x00000001) >> 0)
229 /* Produces a ALT_ECC_HMC_OCP_DDRCALSTAT_CAL register field value suitable for setting the register. */
230 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET(value) (((value) << 0) & 0x00000001)
231 
232 #ifndef __ASSEMBLY__
233 /*
234  * WARNING: The C register and register group struct declarations are provided for
235  * convenience and illustrative purposes. They should, however, be used with
236  * caution as the C language standard provides no guarantees about the alignment or
237  * atomicity of device memory accesses. The recommended practice for writing
238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
239  * alt_write_word() functions.
240  *
241  * The struct declaration for register ALT_ECC_HMC_OCP_DDRCALSTAT.
242  */
243 struct ALT_ECC_HMC_OCP_DDRCALSTAT_s
244 {
245  uint32_t CAL : 1; /* ALT_ECC_HMC_OCP_DDRCALSTAT_CAL */
246  uint32_t : 31; /* *UNDEFINED* */
247 };
248 
249 /* The typedef declaration for register ALT_ECC_HMC_OCP_DDRCALSTAT. */
250 typedef volatile struct ALT_ECC_HMC_OCP_DDRCALSTAT_s ALT_ECC_HMC_OCP_DDRCALSTAT_t;
251 #endif /* __ASSEMBLY__ */
252 
253 /* The reset value of the ALT_ECC_HMC_OCP_DDRCALSTAT register. */
254 #define ALT_ECC_HMC_OCP_DDRCALSTAT_RESET 0x00000000
255 /* The byte offset of the ALT_ECC_HMC_OCP_DDRCALSTAT register from the beginning of the component. */
256 #define ALT_ECC_HMC_OCP_DDRCALSTAT_OFST 0xc
257 
258 /*
259  * Register : MPR_0BEAT1
260  *
261  * MPR register [31:0] for first beat
262  *
263  * Register Layout
264  *
265  * Bits | Access | Reset | Description
266  * :-------|:-------|:------|:--------------------------------
267  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0
268  *
269  */
270 /*
271  * Field : MPR0
272  *
273  * MPR reg[31:0] for first beat
274  *
275  * Field Access Macros:
276  *
277  */
278 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field. */
279 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_LSB 0
280 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field. */
281 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_MSB 31
282 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field. */
283 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_WIDTH 32
284 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field value. */
285 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET_MSK 0xffffffff
286 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field value. */
287 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_CLR_MSK 0x00000000
288 /* The reset value of the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field. */
289 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_RESET 0x0
290 /* Extracts the ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 field value from a register. */
291 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
292 /* Produces a ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 register field value suitable for setting the register. */
293 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET(value) (((value) << 0) & 0xffffffff)
294 
295 #ifndef __ASSEMBLY__
296 /*
297  * WARNING: The C register and register group struct declarations are provided for
298  * convenience and illustrative purposes. They should, however, be used with
299  * caution as the C language standard provides no guarantees about the alignment or
300  * atomicity of device memory accesses. The recommended practice for writing
301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
302  * alt_write_word() functions.
303  *
304  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_0BEAT1.
305  */
306 struct ALT_ECC_HMC_OCP_MPR_0BEAT1_s
307 {
308  uint32_t MPR0 : 32; /* ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0 */
309 };
310 
311 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_0BEAT1. */
312 typedef volatile struct ALT_ECC_HMC_OCP_MPR_0BEAT1_s ALT_ECC_HMC_OCP_MPR_0BEAT1_t;
313 #endif /* __ASSEMBLY__ */
314 
315 /* The reset value of the ALT_ECC_HMC_OCP_MPR_0BEAT1 register. */
316 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_RESET 0x00000000
317 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_0BEAT1 register from the beginning of the component. */
318 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_OFST 0x10
319 
320 /*
321  * Register : MPR_1BEAT1
322  *
323  * MPR register [63:32] for first beat
324  *
325  * Register Layout
326  *
327  * Bits | Access | Reset | Description
328  * :-------|:-------|:------|:---------------------------------
329  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32
330  *
331  */
332 /*
333  * Field : MPR32
334  *
335  * MPR reg[63:32] for first beat
336  *
337  * Field Access Macros:
338  *
339  */
340 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field. */
341 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_LSB 0
342 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field. */
343 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_MSB 31
344 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field. */
345 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_WIDTH 32
346 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field value. */
347 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET_MSK 0xffffffff
348 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field value. */
349 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_CLR_MSK 0x00000000
350 /* The reset value of the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field. */
351 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_RESET 0x0
352 /* Extracts the ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 field value from a register. */
353 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
354 /* Produces a ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 register field value suitable for setting the register. */
355 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET(value) (((value) << 0) & 0xffffffff)
356 
357 #ifndef __ASSEMBLY__
358 /*
359  * WARNING: The C register and register group struct declarations are provided for
360  * convenience and illustrative purposes. They should, however, be used with
361  * caution as the C language standard provides no guarantees about the alignment or
362  * atomicity of device memory accesses. The recommended practice for writing
363  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
364  * alt_write_word() functions.
365  *
366  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_1BEAT1.
367  */
368 struct ALT_ECC_HMC_OCP_MPR_1BEAT1_s
369 {
370  uint32_t MPR32 : 32; /* ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32 */
371 };
372 
373 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_1BEAT1. */
374 typedef volatile struct ALT_ECC_HMC_OCP_MPR_1BEAT1_s ALT_ECC_HMC_OCP_MPR_1BEAT1_t;
375 #endif /* __ASSEMBLY__ */
376 
377 /* The reset value of the ALT_ECC_HMC_OCP_MPR_1BEAT1 register. */
378 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_RESET 0x00000000
379 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_1BEAT1 register from the beginning of the component. */
380 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_OFST 0x14
381 
382 /*
383  * Register : MPR_2BEAT1
384  *
385  * MPR register [95:64] for first beat
386  *
387  * Register Layout
388  *
389  * Bits | Access | Reset | Description
390  * :-------|:-------|:------|:---------------------------------
391  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64
392  *
393  */
394 /*
395  * Field : MPR64
396  *
397  * MPR reg[95:64] for first beat
398  *
399  * Field Access Macros:
400  *
401  */
402 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field. */
403 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_LSB 0
404 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field. */
405 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_MSB 31
406 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field. */
407 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_WIDTH 32
408 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field value. */
409 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET_MSK 0xffffffff
410 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field value. */
411 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_CLR_MSK 0x00000000
412 /* The reset value of the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field. */
413 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_RESET 0x0
414 /* Extracts the ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 field value from a register. */
415 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
416 /* Produces a ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 register field value suitable for setting the register. */
417 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET(value) (((value) << 0) & 0xffffffff)
418 
419 #ifndef __ASSEMBLY__
420 /*
421  * WARNING: The C register and register group struct declarations are provided for
422  * convenience and illustrative purposes. They should, however, be used with
423  * caution as the C language standard provides no guarantees about the alignment or
424  * atomicity of device memory accesses. The recommended practice for writing
425  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
426  * alt_write_word() functions.
427  *
428  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_2BEAT1.
429  */
430 struct ALT_ECC_HMC_OCP_MPR_2BEAT1_s
431 {
432  uint32_t MPR64 : 32; /* ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64 */
433 };
434 
435 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_2BEAT1. */
436 typedef volatile struct ALT_ECC_HMC_OCP_MPR_2BEAT1_s ALT_ECC_HMC_OCP_MPR_2BEAT1_t;
437 #endif /* __ASSEMBLY__ */
438 
439 /* The reset value of the ALT_ECC_HMC_OCP_MPR_2BEAT1 register. */
440 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_RESET 0x00000000
441 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_2BEAT1 register from the beginning of the component. */
442 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_OFST 0x18
443 
444 /*
445  * Register : MPR_3BEAT1
446  *
447  * MPR register [127:96] for first beat
448  *
449  * Register Layout
450  *
451  * Bits | Access | Reset | Description
452  * :-------|:-------|:------|:---------------------------------
453  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96
454  *
455  */
456 /*
457  * Field : MPR96
458  *
459  * MPR reg[127:96] for first beat
460  *
461  * Field Access Macros:
462  *
463  */
464 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field. */
465 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_LSB 0
466 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field. */
467 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_MSB 31
468 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field. */
469 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_WIDTH 32
470 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field value. */
471 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET_MSK 0xffffffff
472 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field value. */
473 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_CLR_MSK 0x00000000
474 /* The reset value of the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field. */
475 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_RESET 0x0
476 /* Extracts the ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 field value from a register. */
477 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
478 /* Produces a ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 register field value suitable for setting the register. */
479 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET(value) (((value) << 0) & 0xffffffff)
480 
481 #ifndef __ASSEMBLY__
482 /*
483  * WARNING: The C register and register group struct declarations are provided for
484  * convenience and illustrative purposes. They should, however, be used with
485  * caution as the C language standard provides no guarantees about the alignment or
486  * atomicity of device memory accesses. The recommended practice for writing
487  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
488  * alt_write_word() functions.
489  *
490  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_3BEAT1.
491  */
492 struct ALT_ECC_HMC_OCP_MPR_3BEAT1_s
493 {
494  uint32_t MPR96 : 32; /* ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96 */
495 };
496 
497 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_3BEAT1. */
498 typedef volatile struct ALT_ECC_HMC_OCP_MPR_3BEAT1_s ALT_ECC_HMC_OCP_MPR_3BEAT1_t;
499 #endif /* __ASSEMBLY__ */
500 
501 /* The reset value of the ALT_ECC_HMC_OCP_MPR_3BEAT1 register. */
502 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_RESET 0x00000000
503 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_3BEAT1 register from the beginning of the component. */
504 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_OFST 0x1c
505 
506 /*
507  * Register : MPR_4BEAT1
508  *
509  * MPR register [159:128] for first beat
510  *
511  * Register Layout
512  *
513  * Bits | Access | Reset | Description
514  * :-------|:-------|:------|:----------------------------------
515  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128
516  *
517  */
518 /*
519  * Field : MPR128
520  *
521  * MPR reg[159:128] for first beat
522  *
523  * Field Access Macros:
524  *
525  */
526 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field. */
527 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_LSB 0
528 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field. */
529 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_MSB 31
530 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field. */
531 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_WIDTH 32
532 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field value. */
533 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET_MSK 0xffffffff
534 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field value. */
535 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_CLR_MSK 0x00000000
536 /* The reset value of the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field. */
537 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_RESET 0x0
538 /* Extracts the ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 field value from a register. */
539 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
540 /* Produces a ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 register field value suitable for setting the register. */
541 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET(value) (((value) << 0) & 0xffffffff)
542 
543 #ifndef __ASSEMBLY__
544 /*
545  * WARNING: The C register and register group struct declarations are provided for
546  * convenience and illustrative purposes. They should, however, be used with
547  * caution as the C language standard provides no guarantees about the alignment or
548  * atomicity of device memory accesses. The recommended practice for writing
549  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
550  * alt_write_word() functions.
551  *
552  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_4BEAT1.
553  */
554 struct ALT_ECC_HMC_OCP_MPR_4BEAT1_s
555 {
556  uint32_t MPR128 : 32; /* ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128 */
557 };
558 
559 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_4BEAT1. */
560 typedef volatile struct ALT_ECC_HMC_OCP_MPR_4BEAT1_s ALT_ECC_HMC_OCP_MPR_4BEAT1_t;
561 #endif /* __ASSEMBLY__ */
562 
563 /* The reset value of the ALT_ECC_HMC_OCP_MPR_4BEAT1 register. */
564 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_RESET 0x00000000
565 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_4BEAT1 register from the beginning of the component. */
566 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_OFST 0x20
567 
568 /*
569  * Register : MPR_5BEAT1
570  *
571  * MPR register [191:160] for first beat
572  *
573  * Register Layout
574  *
575  * Bits | Access | Reset | Description
576  * :-------|:-------|:------|:----------------------------------
577  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160
578  *
579  */
580 /*
581  * Field : MPR160
582  *
583  * MPR reg[191:160] for first beat
584  *
585  * Field Access Macros:
586  *
587  */
588 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field. */
589 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_LSB 0
590 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field. */
591 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_MSB 31
592 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field. */
593 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_WIDTH 32
594 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field value. */
595 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET_MSK 0xffffffff
596 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field value. */
597 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_CLR_MSK 0x00000000
598 /* The reset value of the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field. */
599 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_RESET 0x0
600 /* Extracts the ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 field value from a register. */
601 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
602 /* Produces a ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 register field value suitable for setting the register. */
603 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET(value) (((value) << 0) & 0xffffffff)
604 
605 #ifndef __ASSEMBLY__
606 /*
607  * WARNING: The C register and register group struct declarations are provided for
608  * convenience and illustrative purposes. They should, however, be used with
609  * caution as the C language standard provides no guarantees about the alignment or
610  * atomicity of device memory accesses. The recommended practice for writing
611  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
612  * alt_write_word() functions.
613  *
614  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_5BEAT1.
615  */
616 struct ALT_ECC_HMC_OCP_MPR_5BEAT1_s
617 {
618  uint32_t MPR160 : 32; /* ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160 */
619 };
620 
621 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_5BEAT1. */
622 typedef volatile struct ALT_ECC_HMC_OCP_MPR_5BEAT1_s ALT_ECC_HMC_OCP_MPR_5BEAT1_t;
623 #endif /* __ASSEMBLY__ */
624 
625 /* The reset value of the ALT_ECC_HMC_OCP_MPR_5BEAT1 register. */
626 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_RESET 0x00000000
627 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_5BEAT1 register from the beginning of the component. */
628 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_OFST 0x24
629 
630 /*
631  * Register : MPR_6BEAT1
632  *
633  * MPR register [223:192] for first beat
634  *
635  * Register Layout
636  *
637  * Bits | Access | Reset | Description
638  * :-------|:-------|:------|:----------------------------------
639  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192
640  *
641  */
642 /*
643  * Field : MPR192
644  *
645  * MPR reg[223:192] for first beat
646  *
647  * Field Access Macros:
648  *
649  */
650 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field. */
651 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_LSB 0
652 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field. */
653 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_MSB 31
654 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field. */
655 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_WIDTH 32
656 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field value. */
657 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET_MSK 0xffffffff
658 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field value. */
659 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_CLR_MSK 0x00000000
660 /* The reset value of the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field. */
661 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_RESET 0x0
662 /* Extracts the ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 field value from a register. */
663 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
664 /* Produces a ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 register field value suitable for setting the register. */
665 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET(value) (((value) << 0) & 0xffffffff)
666 
667 #ifndef __ASSEMBLY__
668 /*
669  * WARNING: The C register and register group struct declarations are provided for
670  * convenience and illustrative purposes. They should, however, be used with
671  * caution as the C language standard provides no guarantees about the alignment or
672  * atomicity of device memory accesses. The recommended practice for writing
673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
674  * alt_write_word() functions.
675  *
676  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_6BEAT1.
677  */
678 struct ALT_ECC_HMC_OCP_MPR_6BEAT1_s
679 {
680  uint32_t MPR192 : 32; /* ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192 */
681 };
682 
683 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_6BEAT1. */
684 typedef volatile struct ALT_ECC_HMC_OCP_MPR_6BEAT1_s ALT_ECC_HMC_OCP_MPR_6BEAT1_t;
685 #endif /* __ASSEMBLY__ */
686 
687 /* The reset value of the ALT_ECC_HMC_OCP_MPR_6BEAT1 register. */
688 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_RESET 0x00000000
689 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_6BEAT1 register from the beginning of the component. */
690 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_OFST 0x28
691 
692 /*
693  * Register : MPR_7BEAT1
694  *
695  * MPR register [255:224] for first beat
696  *
697  * Register Layout
698  *
699  * Bits | Access | Reset | Description
700  * :-------|:-------|:------|:----------------------------------
701  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224
702  *
703  */
704 /*
705  * Field : MPR224
706  *
707  * MPR reg[255:224] for first beat
708  *
709  * Field Access Macros:
710  *
711  */
712 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field. */
713 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_LSB 0
714 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field. */
715 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_MSB 31
716 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field. */
717 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_WIDTH 32
718 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field value. */
719 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET_MSK 0xffffffff
720 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field value. */
721 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_CLR_MSK 0x00000000
722 /* The reset value of the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field. */
723 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_RESET 0x0
724 /* Extracts the ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 field value from a register. */
725 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
726 /* Produces a ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 register field value suitable for setting the register. */
727 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET(value) (((value) << 0) & 0xffffffff)
728 
729 #ifndef __ASSEMBLY__
730 /*
731  * WARNING: The C register and register group struct declarations are provided for
732  * convenience and illustrative purposes. They should, however, be used with
733  * caution as the C language standard provides no guarantees about the alignment or
734  * atomicity of device memory accesses. The recommended practice for writing
735  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
736  * alt_write_word() functions.
737  *
738  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_7BEAT1.
739  */
740 struct ALT_ECC_HMC_OCP_MPR_7BEAT1_s
741 {
742  uint32_t MPR224 : 32; /* ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224 */
743 };
744 
745 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_7BEAT1. */
746 typedef volatile struct ALT_ECC_HMC_OCP_MPR_7BEAT1_s ALT_ECC_HMC_OCP_MPR_7BEAT1_t;
747 #endif /* __ASSEMBLY__ */
748 
749 /* The reset value of the ALT_ECC_HMC_OCP_MPR_7BEAT1 register. */
750 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_RESET 0x00000000
751 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_7BEAT1 register from the beginning of the component. */
752 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_OFST 0x2c
753 
754 /*
755  * Register : MPR_8BEAT1
756  *
757  * MPR register [287:256] for first beat
758  *
759  * Register Layout
760  *
761  * Bits | Access | Reset | Description
762  * :-------|:-------|:------|:----------------------------------
763  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256
764  *
765  */
766 /*
767  * Field : MPR256
768  *
769  * MPR reg[287:256] for first beat
770  *
771  * Field Access Macros:
772  *
773  */
774 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field. */
775 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_LSB 0
776 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field. */
777 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_MSB 31
778 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field. */
779 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_WIDTH 32
780 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field value. */
781 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET_MSK 0xffffffff
782 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field value. */
783 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_CLR_MSK 0x00000000
784 /* The reset value of the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field. */
785 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_RESET 0x0
786 /* Extracts the ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 field value from a register. */
787 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
788 /* Produces a ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 register field value suitable for setting the register. */
789 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET(value) (((value) << 0) & 0xffffffff)
790 
791 #ifndef __ASSEMBLY__
792 /*
793  * WARNING: The C register and register group struct declarations are provided for
794  * convenience and illustrative purposes. They should, however, be used with
795  * caution as the C language standard provides no guarantees about the alignment or
796  * atomicity of device memory accesses. The recommended practice for writing
797  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
798  * alt_write_word() functions.
799  *
800  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_8BEAT1.
801  */
802 struct ALT_ECC_HMC_OCP_MPR_8BEAT1_s
803 {
804  uint32_t MPR256 : 32; /* ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256 */
805 };
806 
807 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_8BEAT1. */
808 typedef volatile struct ALT_ECC_HMC_OCP_MPR_8BEAT1_s ALT_ECC_HMC_OCP_MPR_8BEAT1_t;
809 #endif /* __ASSEMBLY__ */
810 
811 /* The reset value of the ALT_ECC_HMC_OCP_MPR_8BEAT1 register. */
812 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_RESET 0x00000000
813 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_8BEAT1 register from the beginning of the component. */
814 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_OFST 0x30
815 
816 /*
817  * Register : MPR_0BEAT2
818  *
819  * MPR register [31:0] for second beat
820  *
821  * Register Layout
822  *
823  * Bits | Access | Reset | Description
824  * :-------|:-------|:------|:--------------------------------
825  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0
826  *
827  */
828 /*
829  * Field : MPR0
830  *
831  * MPR reg[31:0] for second beat
832  *
833  * Field Access Macros:
834  *
835  */
836 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field. */
837 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_LSB 0
838 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field. */
839 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_MSB 31
840 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field. */
841 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_WIDTH 32
842 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field value. */
843 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET_MSK 0xffffffff
844 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field value. */
845 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_CLR_MSK 0x00000000
846 /* The reset value of the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field. */
847 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_RESET 0x0
848 /* Extracts the ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 field value from a register. */
849 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
850 /* Produces a ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 register field value suitable for setting the register. */
851 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET(value) (((value) << 0) & 0xffffffff)
852 
853 #ifndef __ASSEMBLY__
854 /*
855  * WARNING: The C register and register group struct declarations are provided for
856  * convenience and illustrative purposes. They should, however, be used with
857  * caution as the C language standard provides no guarantees about the alignment or
858  * atomicity of device memory accesses. The recommended practice for writing
859  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
860  * alt_write_word() functions.
861  *
862  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_0BEAT2.
863  */
864 struct ALT_ECC_HMC_OCP_MPR_0BEAT2_s
865 {
866  uint32_t MPR0 : 32; /* ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0 */
867 };
868 
869 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_0BEAT2. */
870 typedef volatile struct ALT_ECC_HMC_OCP_MPR_0BEAT2_s ALT_ECC_HMC_OCP_MPR_0BEAT2_t;
871 #endif /* __ASSEMBLY__ */
872 
873 /* The reset value of the ALT_ECC_HMC_OCP_MPR_0BEAT2 register. */
874 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_RESET 0x00000000
875 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_0BEAT2 register from the beginning of the component. */
876 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_OFST 0x34
877 
878 /*
879  * Register : MPR_1BEAT2
880  *
881  * MPR register [63:32] for second beat
882  *
883  * Register Layout
884  *
885  * Bits | Access | Reset | Description
886  * :-------|:-------|:------|:---------------------------------
887  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32
888  *
889  */
890 /*
891  * Field : MPR32
892  *
893  * MPR reg[63:32] for second beat
894  *
895  * Field Access Macros:
896  *
897  */
898 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field. */
899 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_LSB 0
900 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field. */
901 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_MSB 31
902 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field. */
903 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_WIDTH 32
904 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field value. */
905 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET_MSK 0xffffffff
906 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field value. */
907 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_CLR_MSK 0x00000000
908 /* The reset value of the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field. */
909 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_RESET 0x0
910 /* Extracts the ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 field value from a register. */
911 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
912 /* Produces a ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 register field value suitable for setting the register. */
913 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET(value) (((value) << 0) & 0xffffffff)
914 
915 #ifndef __ASSEMBLY__
916 /*
917  * WARNING: The C register and register group struct declarations are provided for
918  * convenience and illustrative purposes. They should, however, be used with
919  * caution as the C language standard provides no guarantees about the alignment or
920  * atomicity of device memory accesses. The recommended practice for writing
921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
922  * alt_write_word() functions.
923  *
924  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_1BEAT2.
925  */
926 struct ALT_ECC_HMC_OCP_MPR_1BEAT2_s
927 {
928  uint32_t MPR32 : 32; /* ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32 */
929 };
930 
931 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_1BEAT2. */
932 typedef volatile struct ALT_ECC_HMC_OCP_MPR_1BEAT2_s ALT_ECC_HMC_OCP_MPR_1BEAT2_t;
933 #endif /* __ASSEMBLY__ */
934 
935 /* The reset value of the ALT_ECC_HMC_OCP_MPR_1BEAT2 register. */
936 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_RESET 0x00000000
937 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_1BEAT2 register from the beginning of the component. */
938 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_OFST 0x38
939 
940 /*
941  * Register : MPR_2BEAT2
942  *
943  * MPR register [95:64] for second beat
944  *
945  * Register Layout
946  *
947  * Bits | Access | Reset | Description
948  * :-------|:-------|:------|:---------------------------------
949  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64
950  *
951  */
952 /*
953  * Field : MPR64
954  *
955  * MPR reg[95:64] for second beat
956  *
957  * Field Access Macros:
958  *
959  */
960 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field. */
961 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_LSB 0
962 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field. */
963 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_MSB 31
964 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field. */
965 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_WIDTH 32
966 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field value. */
967 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET_MSK 0xffffffff
968 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field value. */
969 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_CLR_MSK 0x00000000
970 /* The reset value of the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field. */
971 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_RESET 0x0
972 /* Extracts the ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 field value from a register. */
973 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
974 /* Produces a ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 register field value suitable for setting the register. */
975 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET(value) (((value) << 0) & 0xffffffff)
976 
977 #ifndef __ASSEMBLY__
978 /*
979  * WARNING: The C register and register group struct declarations are provided for
980  * convenience and illustrative purposes. They should, however, be used with
981  * caution as the C language standard provides no guarantees about the alignment or
982  * atomicity of device memory accesses. The recommended practice for writing
983  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
984  * alt_write_word() functions.
985  *
986  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_2BEAT2.
987  */
988 struct ALT_ECC_HMC_OCP_MPR_2BEAT2_s
989 {
990  uint32_t MPR64 : 32; /* ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64 */
991 };
992 
993 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_2BEAT2. */
994 typedef volatile struct ALT_ECC_HMC_OCP_MPR_2BEAT2_s ALT_ECC_HMC_OCP_MPR_2BEAT2_t;
995 #endif /* __ASSEMBLY__ */
996 
997 /* The reset value of the ALT_ECC_HMC_OCP_MPR_2BEAT2 register. */
998 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_RESET 0x00000000
999 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_2BEAT2 register from the beginning of the component. */
1000 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_OFST 0x3c
1001 
1002 /*
1003  * Register : MPR_3BEAT2
1004  *
1005  * MPR register [127:96] for second beat
1006  *
1007  * Register Layout
1008  *
1009  * Bits | Access | Reset | Description
1010  * :-------|:-------|:------|:---------------------------------
1011  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96
1012  *
1013  */
1014 /*
1015  * Field : MPR96
1016  *
1017  * MPR reg[127:96] for second beat
1018  *
1019  * Field Access Macros:
1020  *
1021  */
1022 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field. */
1023 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_LSB 0
1024 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field. */
1025 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_MSB 31
1026 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field. */
1027 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_WIDTH 32
1028 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field value. */
1029 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET_MSK 0xffffffff
1030 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field value. */
1031 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_CLR_MSK 0x00000000
1032 /* The reset value of the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field. */
1033 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_RESET 0x0
1034 /* Extracts the ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 field value from a register. */
1035 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
1036 /* Produces a ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 register field value suitable for setting the register. */
1037 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET(value) (((value) << 0) & 0xffffffff)
1038 
1039 #ifndef __ASSEMBLY__
1040 /*
1041  * WARNING: The C register and register group struct declarations are provided for
1042  * convenience and illustrative purposes. They should, however, be used with
1043  * caution as the C language standard provides no guarantees about the alignment or
1044  * atomicity of device memory accesses. The recommended practice for writing
1045  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1046  * alt_write_word() functions.
1047  *
1048  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_3BEAT2.
1049  */
1050 struct ALT_ECC_HMC_OCP_MPR_3BEAT2_s
1051 {
1052  uint32_t MPR96 : 32; /* ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96 */
1053 };
1054 
1055 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_3BEAT2. */
1056 typedef volatile struct ALT_ECC_HMC_OCP_MPR_3BEAT2_s ALT_ECC_HMC_OCP_MPR_3BEAT2_t;
1057 #endif /* __ASSEMBLY__ */
1058 
1059 /* The reset value of the ALT_ECC_HMC_OCP_MPR_3BEAT2 register. */
1060 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_RESET 0x00000000
1061 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_3BEAT2 register from the beginning of the component. */
1062 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_OFST 0x40
1063 
1064 /*
1065  * Register : MPR_4BEAT2
1066  *
1067  * MPR register [159:128] for second beat
1068  *
1069  * Register Layout
1070  *
1071  * Bits | Access | Reset | Description
1072  * :-------|:-------|:------|:----------------------------------
1073  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128
1074  *
1075  */
1076 /*
1077  * Field : MPR128
1078  *
1079  * MPR reg[159:128] for second beat
1080  *
1081  * Field Access Macros:
1082  *
1083  */
1084 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field. */
1085 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_LSB 0
1086 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field. */
1087 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_MSB 31
1088 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field. */
1089 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_WIDTH 32
1090 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field value. */
1091 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET_MSK 0xffffffff
1092 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field value. */
1093 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_CLR_MSK 0x00000000
1094 /* The reset value of the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field. */
1095 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_RESET 0x0
1096 /* Extracts the ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 field value from a register. */
1097 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
1098 /* Produces a ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 register field value suitable for setting the register. */
1099 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET(value) (((value) << 0) & 0xffffffff)
1100 
1101 #ifndef __ASSEMBLY__
1102 /*
1103  * WARNING: The C register and register group struct declarations are provided for
1104  * convenience and illustrative purposes. They should, however, be used with
1105  * caution as the C language standard provides no guarantees about the alignment or
1106  * atomicity of device memory accesses. The recommended practice for writing
1107  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1108  * alt_write_word() functions.
1109  *
1110  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_4BEAT2.
1111  */
1112 struct ALT_ECC_HMC_OCP_MPR_4BEAT2_s
1113 {
1114  uint32_t MPR128 : 32; /* ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128 */
1115 };
1116 
1117 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_4BEAT2. */
1118 typedef volatile struct ALT_ECC_HMC_OCP_MPR_4BEAT2_s ALT_ECC_HMC_OCP_MPR_4BEAT2_t;
1119 #endif /* __ASSEMBLY__ */
1120 
1121 /* The reset value of the ALT_ECC_HMC_OCP_MPR_4BEAT2 register. */
1122 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_RESET 0x00000000
1123 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_4BEAT2 register from the beginning of the component. */
1124 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_OFST 0x44
1125 
1126 /*
1127  * Register : MPR_5BEAT2
1128  *
1129  * MPR register [191:160] for second beat
1130  *
1131  * Register Layout
1132  *
1133  * Bits | Access | Reset | Description
1134  * :-------|:-------|:------|:----------------------------------
1135  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160
1136  *
1137  */
1138 /*
1139  * Field : MPR160
1140  *
1141  * MPR reg[191:160] for second beat
1142  *
1143  * Field Access Macros:
1144  *
1145  */
1146 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field. */
1147 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_LSB 0
1148 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field. */
1149 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_MSB 31
1150 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field. */
1151 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_WIDTH 32
1152 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field value. */
1153 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET_MSK 0xffffffff
1154 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field value. */
1155 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_CLR_MSK 0x00000000
1156 /* The reset value of the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field. */
1157 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_RESET 0x0
1158 /* Extracts the ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 field value from a register. */
1159 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
1160 /* Produces a ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 register field value suitable for setting the register. */
1161 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET(value) (((value) << 0) & 0xffffffff)
1162 
1163 #ifndef __ASSEMBLY__
1164 /*
1165  * WARNING: The C register and register group struct declarations are provided for
1166  * convenience and illustrative purposes. They should, however, be used with
1167  * caution as the C language standard provides no guarantees about the alignment or
1168  * atomicity of device memory accesses. The recommended practice for writing
1169  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1170  * alt_write_word() functions.
1171  *
1172  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_5BEAT2.
1173  */
1174 struct ALT_ECC_HMC_OCP_MPR_5BEAT2_s
1175 {
1176  uint32_t MPR160 : 32; /* ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160 */
1177 };
1178 
1179 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_5BEAT2. */
1180 typedef volatile struct ALT_ECC_HMC_OCP_MPR_5BEAT2_s ALT_ECC_HMC_OCP_MPR_5BEAT2_t;
1181 #endif /* __ASSEMBLY__ */
1182 
1183 /* The reset value of the ALT_ECC_HMC_OCP_MPR_5BEAT2 register. */
1184 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_RESET 0x00000000
1185 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_5BEAT2 register from the beginning of the component. */
1186 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_OFST 0x48
1187 
1188 /*
1189  * Register : MPR_6BEAT2
1190  *
1191  * MPR register [223:192] for second beat
1192  *
1193  * Register Layout
1194  *
1195  * Bits | Access | Reset | Description
1196  * :-------|:-------|:------|:----------------------------------
1197  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192
1198  *
1199  */
1200 /*
1201  * Field : MPR192
1202  *
1203  * MPR reg[223:192] for second beat
1204  *
1205  * Field Access Macros:
1206  *
1207  */
1208 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field. */
1209 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_LSB 0
1210 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field. */
1211 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_MSB 31
1212 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field. */
1213 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_WIDTH 32
1214 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field value. */
1215 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET_MSK 0xffffffff
1216 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field value. */
1217 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_CLR_MSK 0x00000000
1218 /* The reset value of the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field. */
1219 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_RESET 0x0
1220 /* Extracts the ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 field value from a register. */
1221 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
1222 /* Produces a ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 register field value suitable for setting the register. */
1223 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET(value) (((value) << 0) & 0xffffffff)
1224 
1225 #ifndef __ASSEMBLY__
1226 /*
1227  * WARNING: The C register and register group struct declarations are provided for
1228  * convenience and illustrative purposes. They should, however, be used with
1229  * caution as the C language standard provides no guarantees about the alignment or
1230  * atomicity of device memory accesses. The recommended practice for writing
1231  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1232  * alt_write_word() functions.
1233  *
1234  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_6BEAT2.
1235  */
1236 struct ALT_ECC_HMC_OCP_MPR_6BEAT2_s
1237 {
1238  uint32_t MPR192 : 32; /* ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192 */
1239 };
1240 
1241 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_6BEAT2. */
1242 typedef volatile struct ALT_ECC_HMC_OCP_MPR_6BEAT2_s ALT_ECC_HMC_OCP_MPR_6BEAT2_t;
1243 #endif /* __ASSEMBLY__ */
1244 
1245 /* The reset value of the ALT_ECC_HMC_OCP_MPR_6BEAT2 register. */
1246 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_RESET 0x00000000
1247 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_6BEAT2 register from the beginning of the component. */
1248 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_OFST 0x4c
1249 
1250 /*
1251  * Register : MPR_7BEAT2
1252  *
1253  * MPR register [255:224] for second beat
1254  *
1255  * Register Layout
1256  *
1257  * Bits | Access | Reset | Description
1258  * :-------|:-------|:------|:----------------------------------
1259  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224
1260  *
1261  */
1262 /*
1263  * Field : MPR224
1264  *
1265  * MPR reg[255:224] for second beat
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field. */
1271 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_LSB 0
1272 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field. */
1273 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_MSB 31
1274 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field. */
1275 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_WIDTH 32
1276 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field value. */
1277 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET_MSK 0xffffffff
1278 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field value. */
1279 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_CLR_MSK 0x00000000
1280 /* The reset value of the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field. */
1281 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_RESET 0x0
1282 /* Extracts the ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 field value from a register. */
1283 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
1284 /* Produces a ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 register field value suitable for setting the register. */
1285 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET(value) (((value) << 0) & 0xffffffff)
1286 
1287 #ifndef __ASSEMBLY__
1288 /*
1289  * WARNING: The C register and register group struct declarations are provided for
1290  * convenience and illustrative purposes. They should, however, be used with
1291  * caution as the C language standard provides no guarantees about the alignment or
1292  * atomicity of device memory accesses. The recommended practice for writing
1293  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1294  * alt_write_word() functions.
1295  *
1296  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_7BEAT2.
1297  */
1298 struct ALT_ECC_HMC_OCP_MPR_7BEAT2_s
1299 {
1300  uint32_t MPR224 : 32; /* ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224 */
1301 };
1302 
1303 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_7BEAT2. */
1304 typedef volatile struct ALT_ECC_HMC_OCP_MPR_7BEAT2_s ALT_ECC_HMC_OCP_MPR_7BEAT2_t;
1305 #endif /* __ASSEMBLY__ */
1306 
1307 /* The reset value of the ALT_ECC_HMC_OCP_MPR_7BEAT2 register. */
1308 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_RESET 0x00000000
1309 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_7BEAT2 register from the beginning of the component. */
1310 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_OFST 0x50
1311 
1312 /*
1313  * Register : MPR_8BEAT2
1314  *
1315  * MPR register [287:256] for second beat
1316  *
1317  * Register Layout
1318  *
1319  * Bits | Access | Reset | Description
1320  * :-------|:-------|:------|:----------------------------------
1321  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256
1322  *
1323  */
1324 /*
1325  * Field : MPR256
1326  *
1327  * MPR reg[287:256] for second beat
1328  *
1329  * Field Access Macros:
1330  *
1331  */
1332 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field. */
1333 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_LSB 0
1334 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field. */
1335 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_MSB 31
1336 /* The width in bits of the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field. */
1337 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_WIDTH 32
1338 /* The mask used to set the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field value. */
1339 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET_MSK 0xffffffff
1340 /* The mask used to clear the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field value. */
1341 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_CLR_MSK 0x00000000
1342 /* The reset value of the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field. */
1343 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_RESET 0x0
1344 /* Extracts the ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 field value from a register. */
1345 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
1346 /* Produces a ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 register field value suitable for setting the register. */
1347 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET(value) (((value) << 0) & 0xffffffff)
1348 
1349 #ifndef __ASSEMBLY__
1350 /*
1351  * WARNING: The C register and register group struct declarations are provided for
1352  * convenience and illustrative purposes. They should, however, be used with
1353  * caution as the C language standard provides no guarantees about the alignment or
1354  * atomicity of device memory accesses. The recommended practice for writing
1355  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1356  * alt_write_word() functions.
1357  *
1358  * The struct declaration for register ALT_ECC_HMC_OCP_MPR_8BEAT2.
1359  */
1360 struct ALT_ECC_HMC_OCP_MPR_8BEAT2_s
1361 {
1362  uint32_t MPR256 : 32; /* ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256 */
1363 };
1364 
1365 /* The typedef declaration for register ALT_ECC_HMC_OCP_MPR_8BEAT2. */
1366 typedef volatile struct ALT_ECC_HMC_OCP_MPR_8BEAT2_s ALT_ECC_HMC_OCP_MPR_8BEAT2_t;
1367 #endif /* __ASSEMBLY__ */
1368 
1369 /* The reset value of the ALT_ECC_HMC_OCP_MPR_8BEAT2 register. */
1370 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_RESET 0x00000000
1371 /* The byte offset of the ALT_ECC_HMC_OCP_MPR_8BEAT2 register from the beginning of the component. */
1372 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_OFST 0x54
1373 
1374 /*
1375  * Register : AUTO_PRECHARGE
1376  *
1377  * auto-precharge bit
1378  *
1379  * Register Layout
1380  *
1381  * Bits | Access | Reset | Description
1382  * :-------|:-------|:------|:-----------------------------------
1383  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL
1384  * [31:1] | ??? | 0x0 | *UNDEFINED*
1385  *
1386  */
1387 /*
1388  * Field : CTRL
1389  *
1390  * Control bit to drive auto-precharge bit on command interface to HMC
1391  *
1392  * Field Access Macros:
1393  *
1394  */
1395 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field. */
1396 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_LSB 0
1397 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field. */
1398 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_MSB 0
1399 /* The width in bits of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field. */
1400 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_WIDTH 1
1401 /* The mask used to set the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field value. */
1402 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET_MSK 0x00000001
1403 /* The mask used to clear the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field value. */
1404 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_CLR_MSK 0xfffffffe
1405 /* The reset value of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field. */
1406 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_RESET 0x0
1407 /* Extracts the ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL field value from a register. */
1408 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_GET(value) (((value) & 0x00000001) >> 0)
1409 /* Produces a ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL register field value suitable for setting the register. */
1410 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET(value) (((value) << 0) & 0x00000001)
1411 
1412 #ifndef __ASSEMBLY__
1413 /*
1414  * WARNING: The C register and register group struct declarations are provided for
1415  * convenience and illustrative purposes. They should, however, be used with
1416  * caution as the C language standard provides no guarantees about the alignment or
1417  * atomicity of device memory accesses. The recommended practice for writing
1418  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1419  * alt_write_word() functions.
1420  *
1421  * The struct declaration for register ALT_ECC_HMC_OCP_AUTO_PRECHARGE.
1422  */
1423 struct ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s
1424 {
1425  uint32_t CTRL : 1; /* ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL */
1426  uint32_t : 31; /* *UNDEFINED* */
1427 };
1428 
1429 /* The typedef declaration for register ALT_ECC_HMC_OCP_AUTO_PRECHARGE. */
1430 typedef volatile struct ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t;
1431 #endif /* __ASSEMBLY__ */
1432 
1433 /* The reset value of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE register. */
1434 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_RESET 0x00000000
1435 /* The byte offset of the ALT_ECC_HMC_OCP_AUTO_PRECHARGE register from the beginning of the component. */
1436 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_OFST 0x60
1437 
1438 /*
1439  * Register : ECCCTRL1
1440  *
1441  * ECC control 1.
1442  *
1443  * This bit is used to set the initialize the memory and ecc to a known value
1444  *
1445  * Register Layout
1446  *
1447  * Bits | Access | Reset | Description
1448  * :--------|:-------|:------|:---------------------------------------
1449  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN
1450  * [7:1] | ??? | 0x0 | *UNDEFINED*
1451  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST
1452  * [15:9] | ??? | 0x0 | *UNDEFINED*
1453  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST
1454  * [31:17] | ??? | 0x0 | *UNDEFINED*
1455  *
1456  */
1457 /*
1458  * Field : ECC_EN
1459  *
1460  * Enable for the ECC detection and correction logic.
1461  *
1462  * 1'b0:ECC block is disabled. Default value after reset.
1463  *
1464  * 1'b1: ECC block is enabled. Every RAM access will verify the data and generate
1465  * any necessary error requests.
1466  *
1467  * Field Access Macros:
1468  *
1469  */
1470 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field. */
1471 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_LSB 0
1472 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field. */
1473 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_MSB 0
1474 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field. */
1475 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_WIDTH 1
1476 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value. */
1477 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET_MSK 0x00000001
1478 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value. */
1479 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_CLR_MSK 0xfffffffe
1480 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field. */
1481 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_RESET 0x0
1482 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN field value from a register. */
1483 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
1484 /* Produces a ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value suitable for setting the register. */
1485 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
1486 
1487 /*
1488  * Field : CNT_RST
1489  *
1490  * Reset of internal counter.
1491  *
1492  * 1'b0: No effect on internal counter. Dafault value after reset
1493  *
1494  * 1'b1: Reset the internal counter to zero
1495  *
1496  * Field Access Macros:
1497  *
1498  */
1499 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field. */
1500 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_LSB 8
1501 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field. */
1502 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_MSB 8
1503 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field. */
1504 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_WIDTH 1
1505 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value. */
1506 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET_MSK 0x00000100
1507 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value. */
1508 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_CLR_MSK 0xfffffeff
1509 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field. */
1510 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_RESET 0x0
1511 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST field value from a register. */
1512 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_GET(value) (((value) & 0x00000100) >> 8)
1513 /* Produces a ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value suitable for setting the register. */
1514 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET(value) (((value) << 8) & 0x00000100)
1515 
1516 /*
1517  * Field : AUTOWB_CNT_RST
1518  *
1519  * Reset the autoWB internal counter to zero.
1520  *
1521  * 1'b0 : No effect on autoWB internal counter. Default value after reset
1522  *
1523  * 1'b1 : Reset the autoWB internal counter to zero
1524  *
1525  * Field Access Macros:
1526  *
1527  */
1528 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field. */
1529 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_LSB 16
1530 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field. */
1531 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_MSB 16
1532 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field. */
1533 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_WIDTH 1
1534 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value. */
1535 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
1536 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value. */
1537 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_CLR_MSK 0xfffeffff
1538 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field. */
1539 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_RESET 0x0
1540 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST field value from a register. */
1541 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_GET(value) (((value) & 0x00010000) >> 16)
1542 /* Produces a ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value suitable for setting the register. */
1543 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET(value) (((value) << 16) & 0x00010000)
1544 
1545 #ifndef __ASSEMBLY__
1546 /*
1547  * WARNING: The C register and register group struct declarations are provided for
1548  * convenience and illustrative purposes. They should, however, be used with
1549  * caution as the C language standard provides no guarantees about the alignment or
1550  * atomicity of device memory accesses. The recommended practice for writing
1551  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1552  * alt_write_word() functions.
1553  *
1554  * The struct declaration for register ALT_ECC_HMC_OCP_ECCCTL1.
1555  */
1556 struct ALT_ECC_HMC_OCP_ECCCTL1_s
1557 {
1558  uint32_t ECC_EN : 1; /* ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN */
1559  uint32_t : 7; /* *UNDEFINED* */
1560  uint32_t CNT_RST : 1; /* ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST */
1561  uint32_t : 7; /* *UNDEFINED* */
1562  uint32_t AUTOWB_CNT_RST : 1; /* ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST */
1563  uint32_t : 15; /* *UNDEFINED* */
1564 };
1565 
1566 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECCCTL1. */
1567 typedef volatile struct ALT_ECC_HMC_OCP_ECCCTL1_s ALT_ECC_HMC_OCP_ECCCTL1_t;
1568 #endif /* __ASSEMBLY__ */
1569 
1570 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL1 register. */
1571 #define ALT_ECC_HMC_OCP_ECCCTL1_RESET 0x00000000
1572 /* The byte offset of the ALT_ECC_HMC_OCP_ECCCTL1 register from the beginning of the component. */
1573 #define ALT_ECC_HMC_OCP_ECCCTL1_OFST 0x100
1574 
1575 /*
1576  * Register : ECCCTRL2
1577  *
1578  * ECC control 2.
1579  *
1580  * This bit is used to set the initialize the memory and ecc to a known value
1581  *
1582  * Register Layout
1583  *
1584  * Bits | Access | Reset | Description
1585  * :--------|:-------|:------|:---------------------------------------
1586  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN
1587  * [7:1] | ??? | 0x0 | *UNDEFINED*
1588  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN
1589  * [15:9] | ??? | 0x0 | *UNDEFINED*
1590  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN
1591  * [31:17] | ??? | 0x0 | *UNDEFINED*
1592  *
1593  */
1594 /*
1595  * Field : AUTOWB_EN
1596  *
1597  * Enable auto write back correction feature.
1598  *
1599  * When serr is detected on outgoing reads, HMC adaptor schedules the corrected
1600  * data and ECC to the written to the DDR memory. This bit enables auto correction
1601  * of DDR memory.
1602  *
1603  * 1'b0: disable auto WB drop correction. Default value after reset.
1604  *
1605  * 1'b1: enable auto WB drop correction.
1606  *
1607  * Field Access Macros:
1608  *
1609  */
1610 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field. */
1611 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_LSB 0
1612 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field. */
1613 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_MSB 0
1614 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field. */
1615 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_WIDTH 1
1616 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value. */
1617 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET_MSK 0x00000001
1618 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value. */
1619 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_CLR_MSK 0xfffffffe
1620 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field. */
1621 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_RESET 0x0
1622 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN field value from a register. */
1623 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0)
1624 /* Produces a ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value suitable for setting the register. */
1625 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001)
1626 
1627 /*
1628  * Field : RMW_EN
1629  *
1630  * Enable read modify write logic.
1631  *
1632  * When ECC is enabled and sub word accesses require correct ECC to be calculated,
1633  * this bit should be enabled. RMW_EN bit should be disabled when ECC_EN is
1634  * disabled.
1635  *
1636  * 1'b0: disable RMW logic. Default value after reset.
1637  *
1638  * 1'b1: enable RMW logic.
1639  *
1640  * Field Access Macros:
1641  *
1642  */
1643 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field. */
1644 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_LSB 8
1645 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field. */
1646 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_MSB 8
1647 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field. */
1648 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_WIDTH 1
1649 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value. */
1650 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100
1651 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value. */
1652 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_CLR_MSK 0xfffffeff
1653 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field. */
1654 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_RESET 0x0
1655 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN field value from a register. */
1656 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8)
1657 /* Produces a ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value suitable for setting the register. */
1658 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100)
1659 
1660 /*
1661  * Field : OVRW_RB_ECC_EN
1662  *
1663  * Overwrite the read-back ecc code during RMW process if DBE is detected.
1664  *
1665  * 1'b0: write the read-back ECC from RMW process if derr is detected. Default
1666  * value after reset.
1667  *
1668  * 1'b1: write of 1 will overwrite the ECC overwrite feature.
1669  *
1670  * Field Access Macros:
1671  *
1672  */
1673 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field. */
1674 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_LSB 16
1675 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field. */
1676 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_MSB 16
1677 /* The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field. */
1678 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_WIDTH 1
1679 /* The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value. */
1680 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
1681 /* The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value. */
1682 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff
1683 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field. */
1684 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_RESET 0x0
1685 /* Extracts the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN field value from a register. */
1686 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16)
1687 /* Produces a ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value suitable for setting the register. */
1688 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000)
1689 
1690 #ifndef __ASSEMBLY__
1691 /*
1692  * WARNING: The C register and register group struct declarations are provided for
1693  * convenience and illustrative purposes. They should, however, be used with
1694  * caution as the C language standard provides no guarantees about the alignment or
1695  * atomicity of device memory accesses. The recommended practice for writing
1696  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1697  * alt_write_word() functions.
1698  *
1699  * The struct declaration for register ALT_ECC_HMC_OCP_ECCCTL2.
1700  */
1701 struct ALT_ECC_HMC_OCP_ECCCTL2_s
1702 {
1703  uint32_t AUTOWB_EN : 1; /* ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN */
1704  uint32_t : 7; /* *UNDEFINED* */
1705  uint32_t RMW_EN : 1; /* ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN */
1706  uint32_t : 7; /* *UNDEFINED* */
1707  uint32_t OVRW_RB_ECC_EN : 1; /* ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN */
1708  uint32_t : 15; /* *UNDEFINED* */
1709 };
1710 
1711 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECCCTL2. */
1712 typedef volatile struct ALT_ECC_HMC_OCP_ECCCTL2_s ALT_ECC_HMC_OCP_ECCCTL2_t;
1713 #endif /* __ASSEMBLY__ */
1714 
1715 /* The reset value of the ALT_ECC_HMC_OCP_ECCCTL2 register. */
1716 #define ALT_ECC_HMC_OCP_ECCCTL2_RESET 0x00000000
1717 /* The byte offset of the ALT_ECC_HMC_OCP_ECCCTL2 register from the beginning of the component. */
1718 #define ALT_ECC_HMC_OCP_ECCCTL2_OFST 0x104
1719 
1720 /*
1721  * Register : ERRINTEN
1722  *
1723  * Error Interrupt enable
1724  *
1725  * Register Layout
1726  *
1727  * Bits | Access | Reset | Description
1728  * :-------|:-------|:------|:------------------------------------
1729  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN
1730  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN
1731  * [2] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN
1732  * [31:3] | ??? | 0x0 | *UNDEFINED*
1733  *
1734  */
1735 /*
1736  * Field : SERRINTEN
1737  *
1738  * This bit is used to enable the single bit error to system manager. It enables
1739  * the interrupt modes (sbe request,compare match)
1740  *
1741  * 1'b0: SBE interrupt generation logic is disabled.
1742  *
1743  * 1'b1: SBE interrupt generation logic is enabled,
1744  *
1745  * Field Access Macros:
1746  *
1747  */
1748 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field. */
1749 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_LSB 0
1750 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field. */
1751 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_MSB 0
1752 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field. */
1753 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_WIDTH 1
1754 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value. */
1755 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
1756 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value. */
1757 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
1758 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field. */
1759 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_RESET 0x0
1760 /* Extracts the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN field value from a register. */
1761 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
1762 /* Produces a ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
1763 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
1764 
1765 /*
1766  * Field : DERRINTEN
1767  *
1768  * This bit is used to enable the double bit error interrupt to system
1769  *
1770  * manager.When dbe error occurs, bus error is always generated with the
1771  * transaction.DERR interrupt (derr_req)will be generated when this bit is enabled.
1772  *
1773  * 1'b0: DBE interrupt generation logic is disabled.
1774  *
1775  * 1'b1: DBE interrupt generation logic is enabled,
1776  *
1777  * Field Access Macros:
1778  *
1779  */
1780 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field. */
1781 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_LSB 1
1782 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field. */
1783 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_MSB 1
1784 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field. */
1785 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_WIDTH 1
1786 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value. */
1787 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
1788 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value. */
1789 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_CLR_MSK 0xfffffffd
1790 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field. */
1791 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_RESET 0x0
1792 /* Extracts the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN field value from a register. */
1793 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_GET(value) (((value) & 0x00000002) >> 1)
1794 /* Produces a ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value suitable for setting the register. */
1795 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET(value) (((value) << 1) & 0x00000002)
1796 
1797 /*
1798  * Field : HMI_INTREN
1799  *
1800  * Enables GP HMI interrupt.
1801  *
1802  * This bit is used to enable the general purpose HMI interrupt error interrupt to
1803  * system manager. When this bit is enabled along with autoWB_drop_en, it compares
1804  * the internal counter with autoWB_drop_cntreg value. If the value is greater than
1805  * or equal to, then the interrupt will be asserted..
1806  *
1807  * 1'b0: hmi interrupt generation logic is disabled.
1808  *
1809  * 1'b1: hmi interrupt generation logic is enabled.
1810  *
1811  * Field Access Macros:
1812  *
1813  */
1814 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field. */
1815 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_LSB 2
1816 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field. */
1817 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_MSB 2
1818 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field. */
1819 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_WIDTH 1
1820 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value. */
1821 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET_MSK 0x00000004
1822 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value. */
1823 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_CLR_MSK 0xfffffffb
1824 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field. */
1825 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_RESET 0x0
1826 /* Extracts the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN field value from a register. */
1827 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_GET(value) (((value) & 0x00000004) >> 2)
1828 /* Produces a ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value suitable for setting the register. */
1829 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET(value) (((value) << 2) & 0x00000004)
1830 
1831 #ifndef __ASSEMBLY__
1832 /*
1833  * WARNING: The C register and register group struct declarations are provided for
1834  * convenience and illustrative purposes. They should, however, be used with
1835  * caution as the C language standard provides no guarantees about the alignment or
1836  * atomicity of device memory accesses. The recommended practice for writing
1837  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1838  * alt_write_word() functions.
1839  *
1840  * The struct declaration for register ALT_ECC_HMC_OCP_ERRINTEN.
1841  */
1842 struct ALT_ECC_HMC_OCP_ERRINTEN_s
1843 {
1844  uint32_t SERRINTEN : 1; /* ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN */
1845  uint32_t DERRINTEN : 1; /* ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN */
1846  uint32_t HMI_INTREN : 1; /* ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN */
1847  uint32_t : 29; /* *UNDEFINED* */
1848 };
1849 
1850 /* The typedef declaration for register ALT_ECC_HMC_OCP_ERRINTEN. */
1851 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTEN_s ALT_ECC_HMC_OCP_ERRINTEN_t;
1852 #endif /* __ASSEMBLY__ */
1853 
1854 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTEN register. */
1855 #define ALT_ECC_HMC_OCP_ERRINTEN_RESET 0x00000000
1856 /* The byte offset of the ALT_ECC_HMC_OCP_ERRINTEN register from the beginning of the component. */
1857 #define ALT_ECC_HMC_OCP_ERRINTEN_OFST 0x110
1858 
1859 /*
1860  * Register : ERRINTENS
1861  *
1862  * Error Interrupt set
1863  *
1864  * Register Layout
1865  *
1866  * Bits | Access | Reset | Description
1867  * :-------|:-------|:------|:------------------------------------
1868  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS
1869  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS
1870  * [2] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS
1871  * [31:3] | ??? | 0x0 | *UNDEFINED*
1872  *
1873  */
1874 /*
1875  * Field : SERRINTS
1876  *
1877  * This bit is used to set the single-bit error interrupt bit.
1878  *
1879  * Reads reflect SERRINTEN.
1880  *
1881  * 1'b0: writing of zero has no effect
1882  *
1883  * 1'b1: writing one, this bit will set SERRINTEN bit to 1.
1884  *
1885  * This is performing a bitwise writing, not implemented as a FF.
1886  *
1887  * Field Access Macros:
1888  *
1889  */
1890 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field. */
1891 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_LSB 0
1892 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field. */
1893 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_MSB 0
1894 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field. */
1895 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_WIDTH 1
1896 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field value. */
1897 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET_MSK 0x00000001
1898 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field value. */
1899 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
1900 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field. */
1901 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_RESET 0x0
1902 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS field value from a register. */
1903 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
1904 /* Produces a ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS register field value suitable for setting the register. */
1905 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
1906 
1907 /*
1908  * Field : DERRINTS
1909  *
1910  * This bit is used to set the double-bit error interrupt bit.
1911  *
1912  * Reads reflect DERRINTEN.
1913  *
1914  * 1'b0: writing of zero has no effect
1915  *
1916  * 1'b1: writing one, DERRINTEN bit to 1.
1917  *
1918  * This is performing a bitwise writing, not implemented as a FF.
1919  *
1920  * Field Access Macros:
1921  *
1922  */
1923 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field. */
1924 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_LSB 1
1925 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field. */
1926 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_MSB 1
1927 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field. */
1928 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_WIDTH 1
1929 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field value. */
1930 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET_MSK 0x00000002
1931 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field value. */
1932 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_CLR_MSK 0xfffffffd
1933 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field. */
1934 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_RESET 0x0
1935 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS field value from a register. */
1936 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_GET(value) (((value) & 0x00000002) >> 1)
1937 /* Produces a ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS register field value suitable for setting the register. */
1938 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET(value) (((value) << 1) & 0x00000002)
1939 
1940 /*
1941  * Field : HMI_INTRS
1942  *
1943  * This bit is used to set the general purposes HMI interrupt error.
1944  *
1945  * 1'b0: writing of zero has no effect
1946  *
1947  * 1'b1: writing one, HMI_INTREN bit to 1.
1948  *
1949  * This is performing a bitwise writing, not implemented as a FF.
1950  *
1951  * Field Access Macros:
1952  *
1953  */
1954 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field. */
1955 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_LSB 2
1956 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field. */
1957 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_MSB 2
1958 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field. */
1959 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_WIDTH 1
1960 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field value. */
1961 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET_MSK 0x00000004
1962 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field value. */
1963 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_CLR_MSK 0xfffffffb
1964 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field. */
1965 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_RESET 0x0
1966 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS field value from a register. */
1967 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_GET(value) (((value) & 0x00000004) >> 2)
1968 /* Produces a ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS register field value suitable for setting the register. */
1969 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET(value) (((value) << 2) & 0x00000004)
1970 
1971 #ifndef __ASSEMBLY__
1972 /*
1973  * WARNING: The C register and register group struct declarations are provided for
1974  * convenience and illustrative purposes. They should, however, be used with
1975  * caution as the C language standard provides no guarantees about the alignment or
1976  * atomicity of device memory accesses. The recommended practice for writing
1977  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1978  * alt_write_word() functions.
1979  *
1980  * The struct declaration for register ALT_ECC_HMC_OCP_ERRINTENS.
1981  */
1982 struct ALT_ECC_HMC_OCP_ERRINTENS_s
1983 {
1984  uint32_t SERRINTS : 1; /* ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS */
1985  uint32_t DERRINTS : 1; /* ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS */
1986  uint32_t HMI_INTRS : 1; /* ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS */
1987  uint32_t : 29; /* *UNDEFINED* */
1988 };
1989 
1990 /* The typedef declaration for register ALT_ECC_HMC_OCP_ERRINTENS. */
1991 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTENS_s ALT_ECC_HMC_OCP_ERRINTENS_t;
1992 #endif /* __ASSEMBLY__ */
1993 
1994 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENS register. */
1995 #define ALT_ECC_HMC_OCP_ERRINTENS_RESET 0x00000000
1996 /* The byte offset of the ALT_ECC_HMC_OCP_ERRINTENS register from the beginning of the component. */
1997 #define ALT_ECC_HMC_OCP_ERRINTENS_OFST 0x114
1998 
1999 /*
2000  * Register : ERRINTENR
2001  *
2002  * Error Interrupt reset.
2003  *
2004  * Register Layout
2005  *
2006  * Bits | Access | Reset | Description
2007  * :-------|:-------|:------|:------------------------------------
2008  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR
2009  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR
2010  * [2] | RW | 0x0 | ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR
2011  * [31:3] | ??? | 0x0 | *UNDEFINED*
2012  *
2013  */
2014 /*
2015  * Field : SERRINTR
2016  *
2017  * This bit is used to reset the single-bit error interrupt bit.
2018  *
2019  * Reads reflect SERRINTEN.
2020  *
2021  * 1'b0: Writing of zero has no effect.
2022  *
2023  * 1'b1: By writing one, this bit will reset SERRINTEN bit to 0.
2024  *
2025  * This is performing a bitwise writing of this feature.
2026  *
2027  * Field Access Macros:
2028  *
2029  */
2030 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field. */
2031 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_LSB 0
2032 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field. */
2033 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_MSB 0
2034 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field. */
2035 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_WIDTH 1
2036 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field value. */
2037 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET_MSK 0x00000001
2038 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field value. */
2039 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
2040 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field. */
2041 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_RESET 0x0
2042 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR field value from a register. */
2043 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
2044 /* Produces a ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR register field value suitable for setting the register. */
2045 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
2046 
2047 /*
2048  * Field : DERRINTR
2049  *
2050  * This bit is used to reset the double-bit error interrupt bit.
2051  *
2052  * Reads reflect DERRINTEN.
2053  *
2054  * 1'b0: Writing of zero has no effect.
2055  *
2056  * 1'b1: By writing one, this bit will reset DERRINTEN bit to 0.
2057  *
2058  * This is performing a bitwise writing of this feature.
2059  *
2060  * Field Access Macros:
2061  *
2062  */
2063 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field. */
2064 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_LSB 1
2065 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field. */
2066 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_MSB 1
2067 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field. */
2068 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_WIDTH 1
2069 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field value. */
2070 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET_MSK 0x00000002
2071 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field value. */
2072 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_CLR_MSK 0xfffffffd
2073 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field. */
2074 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_RESET 0x0
2075 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR field value from a register. */
2076 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_GET(value) (((value) & 0x00000002) >> 1)
2077 /* Produces a ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR register field value suitable for setting the register. */
2078 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET(value) (((value) << 1) & 0x00000002)
2079 
2080 /*
2081  * Field : HMI_INTRR
2082  *
2083  * This bit is used to reset the general purpose HMI interrupt error interrupt to
2084  * system manager
2085  *
2086  * 1'b0: Writing of zero has no effect.
2087  *
2088  * 1'b1: By writing one, this bit will reset HMI_INTREN bit to 0.
2089  *
2090  * This is performing a bitwise writing of this feature.
2091  *
2092  * Field Access Macros:
2093  *
2094  */
2095 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field. */
2096 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_LSB 2
2097 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field. */
2098 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_MSB 2
2099 /* The width in bits of the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field. */
2100 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_WIDTH 1
2101 /* The mask used to set the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field value. */
2102 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET_MSK 0x00000004
2103 /* The mask used to clear the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field value. */
2104 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_CLR_MSK 0xfffffffb
2105 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field. */
2106 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_RESET 0x0
2107 /* Extracts the ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR field value from a register. */
2108 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_GET(value) (((value) & 0x00000004) >> 2)
2109 /* Produces a ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR register field value suitable for setting the register. */
2110 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET(value) (((value) << 2) & 0x00000004)
2111 
2112 #ifndef __ASSEMBLY__
2113 /*
2114  * WARNING: The C register and register group struct declarations are provided for
2115  * convenience and illustrative purposes. They should, however, be used with
2116  * caution as the C language standard provides no guarantees about the alignment or
2117  * atomicity of device memory accesses. The recommended practice for writing
2118  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2119  * alt_write_word() functions.
2120  *
2121  * The struct declaration for register ALT_ECC_HMC_OCP_ERRINTENR.
2122  */
2123 struct ALT_ECC_HMC_OCP_ERRINTENR_s
2124 {
2125  uint32_t SERRINTR : 1; /* ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR */
2126  uint32_t DERRINTR : 1; /* ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR */
2127  uint32_t HMI_INTRR : 1; /* ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR */
2128  uint32_t : 29; /* *UNDEFINED* */
2129 };
2130 
2131 /* The typedef declaration for register ALT_ECC_HMC_OCP_ERRINTENR. */
2132 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTENR_s ALT_ECC_HMC_OCP_ERRINTENR_t;
2133 #endif /* __ASSEMBLY__ */
2134 
2135 /* The reset value of the ALT_ECC_HMC_OCP_ERRINTENR register. */
2136 #define ALT_ECC_HMC_OCP_ERRINTENR_RESET 0x00000000
2137 /* The byte offset of the ALT_ECC_HMC_OCP_ERRINTENR register from the beginning of the component. */
2138 #define ALT_ECC_HMC_OCP_ERRINTENR_OFST 0x118
2139 
2140 /*
2141  * Register : INTMODE
2142  *
2143  * Interrupt mode
2144  *
2145  * Register Layout
2146  *
2147  * Bits | Access | Reset | Description
2148  * :--------|:-------|:------|:-----------------------------------------
2149  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_INTMOD_INTMOD
2150  * [7:1] | ??? | 0x0 | *UNDEFINED*
2151  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN
2152  * [15:9] | ??? | 0x0 | *UNDEFINED*
2153  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_INTMOD_INTONCMP
2154  * [23:17] | ??? | 0x0 | *UNDEFINED*
2155  * [24] | RW | 0x0 | ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN
2156  * [31:25] | ??? | 0x0 | *UNDEFINED*
2157  *
2158  */
2159 /*
2160  * Field : INTMODE
2161  *
2162  * Interrupt mode for single-bit error.This is disabled when SERRINTEN is disabled.
2163  *
2164  * 1'b0: interrupt disbaled
2165  *
2166  * 1'b1: generate interrupt on every SERR
2167  *
2168  * Field Access Macros:
2169  *
2170  */
2171 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field. */
2172 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_LSB 0
2173 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field. */
2174 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_MSB 0
2175 /* The width in bits of the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field. */
2176 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_WIDTH 1
2177 /* The mask used to set the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field value. */
2178 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET_MSK 0x00000001
2179 /* The mask used to clear the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field value. */
2180 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_CLR_MSK 0xfffffffe
2181 /* The reset value of the ALT_ECC_HMC_OCP_INTMOD_INTMOD register field. */
2182 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_RESET 0x0
2183 /* Extracts the ALT_ECC_HMC_OCP_INTMOD_INTMOD field value from a register. */
2184 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
2185 /* Produces a ALT_ECC_HMC_OCP_INTMOD_INTMOD register field value suitable for setting the register. */
2186 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
2187 
2188 /*
2189  * Field : EXT_ADDRPARITY_EN
2190  *
2191  * Enable address parity for DDR4 memories.
2192  *
2193  * This bit is used to enable the interrupt that generate externally when address
2194  * parity is detected. when enabled, this will be generating derr_req signal
2195  *
2196  * 1'b0: disable address parity on DERR interrupt
2197  *
2198  * 1'b1: enable address parity on DERR interrupt
2199  *
2200  * Field Access Macros:
2201  *
2202  */
2203 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field. */
2204 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_LSB 8
2205 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field. */
2206 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_MSB 8
2207 /* The width in bits of the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field. */
2208 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_WIDTH 1
2209 /* The mask used to set the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field value. */
2210 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET_MSK 0x00000100
2211 /* The mask used to clear the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field value. */
2212 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_CLR_MSK 0xfffffeff
2213 /* The reset value of the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field. */
2214 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_RESET 0x0
2215 /* Extracts the ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN field value from a register. */
2216 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_GET(value) (((value) & 0x00000100) >> 8)
2217 /* Produces a ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN register field value suitable for setting the register. */
2218 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET(value) (((value) << 8) & 0x00000100)
2219 
2220 /*
2221  * Field : INTONCMP
2222  *
2223  * Enable interrupt on compare match.
2224  *
2225  * This bit is used to enable interrupt when the internal counter and SERRCNTA
2226  * value matches. serr_req signal will be asserted on a match.
2227  *
2228  * 1'b0: SERR interrupt on compare match is disabled
2229  *
2230  * 1'b1: SERR interrupt on compare match is enabled
2231  *
2232  * Field Access Macros:
2233  *
2234  */
2235 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field. */
2236 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_LSB 16
2237 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field. */
2238 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_MSB 16
2239 /* The width in bits of the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field. */
2240 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_WIDTH 1
2241 /* The mask used to set the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field value. */
2242 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK 0x00010000
2243 /* The mask used to clear the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field value. */
2244 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
2245 /* The reset value of the ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field. */
2246 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_RESET 0x0
2247 /* Extracts the ALT_ECC_HMC_OCP_INTMOD_INTONCMP field value from a register. */
2248 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
2249 /* Produces a ALT_ECC_HMC_OCP_INTMOD_INTONCMP register field value suitable for setting the register. */
2250 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
2251 
2252 /*
2253  * Field : AFICAL_EN
2254  *
2255  * Enable interrupt of AFI Cal success.
2256  *
2257  * This bit is used to enable interrupt of AFI Cal success. hmi_intr signal will be
2258  * asserted on a match.
2259  *
2260  * 1'b0: HMI interrupts on compare match is disabled.
2261  *
2262  * 1'b1: HMI interrupts on compare matched is enabled.
2263  *
2264  * Field Access Macros:
2265  *
2266  */
2267 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field. */
2268 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_LSB 24
2269 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field. */
2270 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_MSB 24
2271 /* The width in bits of the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field. */
2272 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_WIDTH 1
2273 /* The mask used to set the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field value. */
2274 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET_MSK 0x01000000
2275 /* The mask used to clear the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field value. */
2276 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_CLR_MSK 0xfeffffff
2277 /* The reset value of the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field. */
2278 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_RESET 0x0
2279 /* Extracts the ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN field value from a register. */
2280 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_GET(value) (((value) & 0x01000000) >> 24)
2281 /* Produces a ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN register field value suitable for setting the register. */
2282 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET(value) (((value) << 24) & 0x01000000)
2283 
2284 #ifndef __ASSEMBLY__
2285 /*
2286  * WARNING: The C register and register group struct declarations are provided for
2287  * convenience and illustrative purposes. They should, however, be used with
2288  * caution as the C language standard provides no guarantees about the alignment or
2289  * atomicity of device memory accesses. The recommended practice for writing
2290  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2291  * alt_write_word() functions.
2292  *
2293  * The struct declaration for register ALT_ECC_HMC_OCP_INTMOD.
2294  */
2295 struct ALT_ECC_HMC_OCP_INTMOD_s
2296 {
2297  uint32_t INTMODE : 1; /* ALT_ECC_HMC_OCP_INTMOD_INTMOD */
2298  uint32_t : 7; /* *UNDEFINED* */
2299  uint32_t EXT_ADDRPARITY_EN : 1; /* ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN */
2300  uint32_t : 7; /* *UNDEFINED* */
2301  uint32_t INTONCMP : 1; /* ALT_ECC_HMC_OCP_INTMOD_INTONCMP */
2302  uint32_t : 7; /* *UNDEFINED* */
2303  uint32_t AFICAL_EN : 1; /* ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN */
2304  uint32_t : 7; /* *UNDEFINED* */
2305 };
2306 
2307 /* The typedef declaration for register ALT_ECC_HMC_OCP_INTMOD. */
2308 typedef volatile struct ALT_ECC_HMC_OCP_INTMOD_s ALT_ECC_HMC_OCP_INTMOD_t;
2309 #endif /* __ASSEMBLY__ */
2310 
2311 /* The reset value of the ALT_ECC_HMC_OCP_INTMOD register. */
2312 #define ALT_ECC_HMC_OCP_INTMOD_RESET 0x00000000
2313 /* The byte offset of the ALT_ECC_HMC_OCP_INTMOD register from the beginning of the component. */
2314 #define ALT_ECC_HMC_OCP_INTMOD_OFST 0x11c
2315 
2316 /*
2317  * Register : INTSTAT
2318  *
2319  * Interrupt status
2320  *
2321  * Register Layout
2322  *
2323  * Bits | Access | Reset | Description
2324  * :--------|:-------|:------|:-----------------------------------
2325  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA
2326  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA
2327  * [2] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA
2328  * [15:3] | ??? | 0x0 | *UNDEFINED*
2329  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG
2330  * [17] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG
2331  * [18] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG
2332  * [31:19] | ??? | 0x0 | *UNDEFINED*
2333  *
2334  */
2335 /*
2336  * Field : SERRPENA
2337  *
2338  * Single-bit error pending
2339  *
2340  * This bit is used to clear the pending SBE.
2341  *
2342  * 1'b0: No effect.
2343  *
2344  * 1'b1: indicates SBE is pending. Write of one will clear the pending. This will
2345  * de-assert the serr_req signal.
2346  *
2347  * Field Access Macros:
2348  *
2349  */
2350 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field. */
2351 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_LSB 0
2352 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field. */
2353 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_MSB 0
2354 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field. */
2355 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_WIDTH 1
2356 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value. */
2357 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001
2358 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value. */
2359 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
2360 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field. */
2361 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_RESET 0x0
2362 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA field value from a register. */
2363 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
2364 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value suitable for setting the register. */
2365 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
2366 
2367 /*
2368  * Field : DERRPENA
2369  *
2370  * Double bit error pending
2371  *
2372  * This bit is used to clear the pending DBE.
2373  *
2374  * 1'b0: No effect.
2375  *
2376  * 1'b1: indicates DBE is pending. Write of one will clear the pending DBE. This
2377  * will de-assert the derr_req signal.
2378  *
2379  * Field Access Macros:
2380  *
2381  */
2382 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field. */
2383 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_LSB 1
2384 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field. */
2385 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_MSB 1
2386 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field. */
2387 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_WIDTH 1
2388 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value. */
2389 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002
2390 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value. */
2391 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd
2392 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field. */
2393 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_RESET 0x0
2394 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA field value from a register. */
2395 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1)
2396 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value suitable for setting the register. */
2397 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002)
2398 
2399 /*
2400  * Field : HMI_PENA
2401  *
2402  * HMI interrupt pending
2403  *
2404  * This bit is used to clear the pending hmi interrupt bit.
2405  *
2406  * 1'b0: No effect
2407  *
2408  * 1'b1: indicates hmi interrupt is pending. Write of one will clear the pending
2409  * interrupt. This will de-assert the hmi_intr signal.
2410  *
2411  * Field Access Macros:
2412  *
2413  */
2414 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field. */
2415 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_LSB 2
2416 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field. */
2417 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_MSB 2
2418 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field. */
2419 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_WIDTH 1
2420 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value. */
2421 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET_MSK 0x00000004
2422 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value. */
2423 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb
2424 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field. */
2425 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_RESET 0x0
2426 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA field value from a register. */
2427 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2)
2428 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value suitable for setting the register. */
2429 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004)
2430 
2431 /*
2432  * Field : ADDRMTCFLG
2433  *
2434  * Address mismatch error flag.
2435  *
2436  * This bit is used to flag the last transaction was flagged with address mismatch
2437  * error.
2438  *
2439  * 1'b0: No effect.
2440  *
2441  * 1'b1: indicates address mismatch error has occured. This will drive the bus to
2442  * respond the read with bus error. Write of one will clears this register address
2443  * mismatch error.
2444  *
2445  * Bus error occurs as part of the transaction but this indicates the SW the cause
2446  * of the error. This should occur once per transaction.
2447  *
2448  * Field Access Macros:
2449  *
2450  */
2451 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field. */
2452 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_LSB 16
2453 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field. */
2454 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_MSB 16
2455 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field. */
2456 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_WIDTH 1
2457 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value. */
2458 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000
2459 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value. */
2460 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff
2461 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field. */
2462 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_RESET 0x0
2463 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG field value from a register. */
2464 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16)
2465 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value suitable for setting the register. */
2466 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000)
2467 
2468 /*
2469  * Field : ADDRPARFLG
2470  *
2471  * External address parity flag for DDR4 memory.
2472  *
2473  * This bit is used to flag external address parity flag which is driven with
2474  * derr_req port.
2475  *
2476  * 1'b0: No Effect.
2477  *
2478  * 1'b1: Read of one indicates double-bit interrupt has occurred. Write of one
2479  * will clear this register last address parity flag.
2480  *
2481  * Field Access Macros:
2482  *
2483  */
2484 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field. */
2485 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_LSB 17
2486 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field. */
2487 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_MSB 17
2488 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field. */
2489 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_WIDTH 1
2490 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value. */
2491 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000
2492 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value. */
2493 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff
2494 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field. */
2495 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_RESET 0x0
2496 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG field value from a register. */
2497 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17)
2498 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value suitable for setting the register. */
2499 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000)
2500 
2501 /*
2502  * Field : DERRBUSFLG
2503  *
2504  * This bit is used to flag the last transaction was flagged with double-bit error.
2505  *
2506  * 1'b0: no effect.
2507  *
2508  * 1'b1: indicates double-bit error has occured. This will drive the bus to respond
2509  * the read with bus error. Write of one will clear this register double-but bus
2510  * error.
2511  *
2512  * Bus error occurs as part of the transaction but this indicates the SW the cause
2513  * of the error. This should only occur once per transaction
2514  *
2515  * Field Access Macros:
2516  *
2517  */
2518 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field. */
2519 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_LSB 18
2520 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field. */
2521 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_MSB 18
2522 /* The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field. */
2523 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_WIDTH 1
2524 /* The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value. */
2525 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000
2526 /* The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value. */
2527 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff
2528 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field. */
2529 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_RESET 0x0
2530 /* Extracts the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG field value from a register. */
2531 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18)
2532 /* Produces a ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value suitable for setting the register. */
2533 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000)
2534 
2535 #ifndef __ASSEMBLY__
2536 /*
2537  * WARNING: The C register and register group struct declarations are provided for
2538  * convenience and illustrative purposes. They should, however, be used with
2539  * caution as the C language standard provides no guarantees about the alignment or
2540  * atomicity of device memory accesses. The recommended practice for writing
2541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2542  * alt_write_word() functions.
2543  *
2544  * The struct declaration for register ALT_ECC_HMC_OCP_INTSTAT.
2545  */
2546 struct ALT_ECC_HMC_OCP_INTSTAT_s
2547 {
2548  uint32_t SERRPENA : 1; /* ALT_ECC_HMC_OCP_INTSTAT_SERRPENA */
2549  uint32_t DERRPENA : 1; /* ALT_ECC_HMC_OCP_INTSTAT_DERRPENA */
2550  uint32_t HMI_PENA : 1; /* ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA */
2551  uint32_t : 13; /* *UNDEFINED* */
2552  uint32_t ADDRMTCFLG : 1; /* ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG */
2553  uint32_t ADDRPARFLG : 1; /* ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG */
2554  uint32_t DERRBUSFLG : 1; /* ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG */
2555  uint32_t : 13; /* *UNDEFINED* */
2556 };
2557 
2558 /* The typedef declaration for register ALT_ECC_HMC_OCP_INTSTAT. */
2559 typedef volatile struct ALT_ECC_HMC_OCP_INTSTAT_s ALT_ECC_HMC_OCP_INTSTAT_t;
2560 #endif /* __ASSEMBLY__ */
2561 
2562 /* The reset value of the ALT_ECC_HMC_OCP_INTSTAT register. */
2563 #define ALT_ECC_HMC_OCP_INTSTAT_RESET 0x00000000
2564 /* The byte offset of the ALT_ECC_HMC_OCP_INTSTAT register from the beginning of the component. */
2565 #define ALT_ECC_HMC_OCP_INTSTAT_OFST 0x120
2566 
2567 /*
2568  * Register : DIAGINTTEST
2569  *
2570  * Enable diagnostic errors
2571  *
2572  * Register Layout
2573  *
2574  * Bits | Access | Reset | Description
2575  * :--------|:-------|:------|:-------------------------------------
2576  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA
2577  * [7:1] | ??? | 0x0 | *UNDEFINED*
2578  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA
2579  * [15:9] | ??? | 0x0 | *UNDEFINED*
2580  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC
2581  * [23:17] | ??? | 0x0 | *UNDEFINED*
2582  * [24] | RW | 0x0 | ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR
2583  * [31:25] | ??? | 0x0 | *UNDEFINED*
2584  *
2585  */
2586 /*
2587  * Field : TSERRA
2588  *
2589  * This bit is used to test a single-bit error.
2590  *
2591  * 1'b0: Write of zero has no effect.
2592  *
2593  * 1'b1: When this bit is set to 1, serr_req signal is generated to the system
2594  * manager when the ECC decoder detects a single-bit error. By writing to this bit,
2595  * SERRPENA bit will be pending. Write of one to SERRPENA will clear this bit.
2596  *
2597  * Field Access Macros:
2598  *
2599  */
2600 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field. */
2601 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_LSB 0
2602 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field. */
2603 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_MSB 0
2604 /* The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field. */
2605 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_WIDTH 1
2606 /* The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value. */
2607 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET_MSK 0x00000001
2608 /* The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value. */
2609 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_CLR_MSK 0xfffffffe
2610 /* The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field. */
2611 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_RESET 0x0
2612 /* Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA field value from a register. */
2613 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
2614 /* Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value suitable for setting the register. */
2615 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
2616 
2617 /*
2618  * Field : TDERRA
2619  *
2620  * Diagnostic enable of Double-bit error.
2621  *
2622  * This bit is used to test double-bit error.
2623  *
2624  * 1'b0: Write of zero has no effect.
2625  *
2626  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
2627  * manager when the ECC decoder detects a double-bit error. By writing to this bit,
2628  * DERRBUSFLG bit will be pending. Write of one to DERRBUSFLG will clear this bit.
2629  * SW needs to explicitly write to DERRPENA to clear it.
2630  *
2631  * Field Access Macros:
2632  *
2633  */
2634 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field. */
2635 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_LSB 8
2636 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field. */
2637 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_MSB 8
2638 /* The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field. */
2639 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_WIDTH 1
2640 /* The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value. */
2641 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET_MSK 0x00000100
2642 /* The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value. */
2643 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_CLR_MSK 0xfffffeff
2644 /* The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field. */
2645 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_RESET 0x0
2646 /* Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA field value from a register. */
2647 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
2648 /* Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value suitable for setting the register. */
2649 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
2650 
2651 /*
2652  * Field : TADDRMTC
2653  *
2654  * Diagnostic enable of Address mismatch error.
2655  *
2656  * This bit is used to flag that the last transaction was flagged with address
2657  * mismatch error.
2658  *
2659  * 1'b0: Disables generating address match bus error as part of the transaction.
2660  *
2661  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
2662  * manager when the ECC decoder detects a ecc address mismatch. By writing to this
2663  * bit, ADDRMTCFLG bit will be pending. Write of one to ADDRMTCFLG will clear this
2664  * bit. SW needs to explicitly write to DERRPENA to clear it.
2665  *
2666  * Field Access Macros:
2667  *
2668  */
2669 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field. */
2670 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_LSB 16
2671 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field. */
2672 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_MSB 16
2673 /* The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field. */
2674 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_WIDTH 1
2675 /* The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value. */
2676 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET_MSK 0x00010000
2677 /* The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value. */
2678 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_CLR_MSK 0xfffeffff
2679 /* The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field. */
2680 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_RESET 0x0
2681 /* Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC field value from a register. */
2682 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_GET(value) (((value) & 0x00010000) >> 16)
2683 /* Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value suitable for setting the register. */
2684 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET(value) (((value) << 16) & 0x00010000)
2685 
2686 /*
2687  * Field : TADDRPAR
2688  *
2689  * Diagnostic of address parity of DDR4.
2690  *
2691  * This bit is used to test the address parity error path.
2692  *
2693  * 1'b0: Disables generating address match bus error as part of the transaction.
2694  *
2695  * 1'b1: When this bit is set to 1, derr_req signal is generated to the system
2696  * manager when the ECC decoder detects an ecc address parity error. By writing to
2697  * this bit, ADDRPARFLG bit will be pending. Write of one to ADDRPARFLG will clear
2698  * this bit. SW needs to explicitly write to DERRPENA to clear it.
2699  *
2700  * Field Access Macros:
2701  *
2702  */
2703 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field. */
2704 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_LSB 24
2705 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field. */
2706 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_MSB 24
2707 /* The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field. */
2708 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_WIDTH 1
2709 /* The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value. */
2710 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET_MSK 0x01000000
2711 /* The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value. */
2712 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_CLR_MSK 0xfeffffff
2713 /* The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field. */
2714 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_RESET 0x0
2715 /* Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR field value from a register. */
2716 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_GET(value) (((value) & 0x01000000) >> 24)
2717 /* Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value suitable for setting the register. */
2718 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET(value) (((value) << 24) & 0x01000000)
2719 
2720 #ifndef __ASSEMBLY__
2721 /*
2722  * WARNING: The C register and register group struct declarations are provided for
2723  * convenience and illustrative purposes. They should, however, be used with
2724  * caution as the C language standard provides no guarantees about the alignment or
2725  * atomicity of device memory accesses. The recommended practice for writing
2726  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2727  * alt_write_word() functions.
2728  *
2729  * The struct declaration for register ALT_ECC_HMC_OCP_DIAGINTTEST.
2730  */
2731 struct ALT_ECC_HMC_OCP_DIAGINTTEST_s
2732 {
2733  uint32_t TSERRA : 1; /* ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA */
2734  uint32_t : 7; /* *UNDEFINED* */
2735  uint32_t TDERRA : 1; /* ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA */
2736  uint32_t : 7; /* *UNDEFINED* */
2737  uint32_t TADDRMTC : 1; /* ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC */
2738  uint32_t : 7; /* *UNDEFINED* */
2739  uint32_t TADDRPAR : 1; /* ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR */
2740  uint32_t : 7; /* *UNDEFINED* */
2741 };
2742 
2743 /* The typedef declaration for register ALT_ECC_HMC_OCP_DIAGINTTEST. */
2744 typedef volatile struct ALT_ECC_HMC_OCP_DIAGINTTEST_s ALT_ECC_HMC_OCP_DIAGINTTEST_t;
2745 #endif /* __ASSEMBLY__ */
2746 
2747 /* The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST register. */
2748 #define ALT_ECC_HMC_OCP_DIAGINTTEST_RESET 0x00000000
2749 /* The byte offset of the ALT_ECC_HMC_OCP_DIAGINTTEST register from the beginning of the component. */
2750 #define ALT_ECC_HMC_OCP_DIAGINTTEST_OFST 0x124
2751 
2752 /*
2753  * Register : MODSTAT
2754  *
2755  * Counter feature status flag
2756  *
2757  * Register Layout
2758  *
2759  * Bits | Access | Reset | Description
2760  * :-------|:-------|:------|:----------------------------------------
2761  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA
2762  * [7:1] | ??? | 0x0 | *UNDEFINED*
2763  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG
2764  * [31:9] | ??? | 0x0 | *UNDEFINED*
2765  *
2766  */
2767 /*
2768  * Field : CMPFLGA
2769  *
2770  * Counter Match occurred flag.
2771  *
2772  * This bit indicates that the internal counter and SERRCNT value matched.
2773  *
2774  * 1'b0: read indicates match check of SERR interrupt on compare match is disabled.
2775  *
2776  * 1'b1: read indicates compare has matched. Write of one will clear the pending
2777  * compare match. This will not de-assert the serr_req signal - software needs to
2778  * write to serrpen bit to clear the interrupt.
2779  *
2780  * When the match occurs, additional errors will not increment count until the
2781  * compare status flag is cleared. If the software does not change the SERRCNT
2782  * register prior to clearing this flag or reset the internal counter, next
2783  * increment of internal counter could set this flag again in the next cycle.
2784  *
2785  * Field Access Macros:
2786  *
2787  */
2788 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field. */
2789 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_LSB 0
2790 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field. */
2791 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_MSB 0
2792 /* The width in bits of the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field. */
2793 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_WIDTH 1
2794 /* The mask used to set the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field value. */
2795 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET_MSK 0x00000001
2796 /* The mask used to clear the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field value. */
2797 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
2798 /* The reset value of the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field. */
2799 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_RESET 0x0
2800 /* Extracts the ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA field value from a register. */
2801 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
2802 /* Produces a ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA register field value suitable for setting the register. */
2803 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
2804 
2805 /*
2806  * Field : AUTOWB_DROP_FLG
2807  *
2808  * Auto writeback counter match flag.
2809  *
2810  * This bit indicates that the internal autoWB counter and autoWB_drop_cnt value
2811  * matched.
2812  *
2813  * 1'b0: read indicates match check of hmi_intr interrupt on compare match is
2814  * disabled.
2815  *
2816  * 1'b1: read indicates compare has matched. Write of one will clear the pending
2817  * compare match. This will not de-assert the hmi_intr signal - software needs to
2818  * write to hmi_intrpen bit to clear the interrupt.
2819  *
2820  * When the match occurs, additional errors will not increment count until the
2821  * compare status flag is cleared. If the software does not change the
2822  * autoWB_drop_cnt register prior to clearing this flag or reset the autoWB
2823  * counter, next increment of internal autoWB counter could set this flag in the
2824  * next cycle.
2825  *
2826  * Field Access Macros:
2827  *
2828  */
2829 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field. */
2830 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_LSB 8
2831 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field. */
2832 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_MSB 8
2833 /* The width in bits of the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field. */
2834 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_WIDTH 1
2835 /* The mask used to set the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field value. */
2836 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET_MSK 0x00000100
2837 /* The mask used to clear the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field value. */
2838 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_CLR_MSK 0xfffffeff
2839 /* The reset value of the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field. */
2840 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_RESET 0x0
2841 /* Extracts the ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG field value from a register. */
2842 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_GET(value) (((value) & 0x00000100) >> 8)
2843 /* Produces a ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG register field value suitable for setting the register. */
2844 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET(value) (((value) << 8) & 0x00000100)
2845 
2846 #ifndef __ASSEMBLY__
2847 /*
2848  * WARNING: The C register and register group struct declarations are provided for
2849  * convenience and illustrative purposes. They should, however, be used with
2850  * caution as the C language standard provides no guarantees about the alignment or
2851  * atomicity of device memory accesses. The recommended practice for writing
2852  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2853  * alt_write_word() functions.
2854  *
2855  * The struct declaration for register ALT_ECC_HMC_OCP_MODSTAT.
2856  */
2857 struct ALT_ECC_HMC_OCP_MODSTAT_s
2858 {
2859  uint32_t CMPFLGA : 1; /* ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA */
2860  uint32_t : 7; /* *UNDEFINED* */
2861  uint32_t AUTOWB_DROP_FLG : 1; /* ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG */
2862  uint32_t : 23; /* *UNDEFINED* */
2863 };
2864 
2865 /* The typedef declaration for register ALT_ECC_HMC_OCP_MODSTAT. */
2866 typedef volatile struct ALT_ECC_HMC_OCP_MODSTAT_s ALT_ECC_HMC_OCP_MODSTAT_t;
2867 #endif /* __ASSEMBLY__ */
2868 
2869 /* The reset value of the ALT_ECC_HMC_OCP_MODSTAT register. */
2870 #define ALT_ECC_HMC_OCP_MODSTAT_RESET 0x00000000
2871 /* The byte offset of the ALT_ECC_HMC_OCP_MODSTAT register from the beginning of the component. */
2872 #define ALT_ECC_HMC_OCP_MODSTAT_OFST 0x128
2873 
2874 /*
2875  * Register : DERRADDRA
2876  *
2877  * Double-bit error address
2878  *
2879  * Register Layout
2880  *
2881  * Bits | Access | Reset | Description
2882  * :-------|:-------|:------|:--------------------------------
2883  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_DERRADDRA_DADDR
2884  *
2885  */
2886 /*
2887  * Field : DADDRESS
2888  *
2889  * Recent DBE address.
2890  *
2891  * This register shows the address of the current double-bit error. RAM size will
2892  * determine the maximum number of address bits.
2893  *
2894  * This address is logged when a new derr_req or bus error is generated to the
2895  * system. This is gated by the ecc_en enable bit and derrinten bit.
2896  *
2897  * Field Access Macros:
2898  *
2899  */
2900 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field. */
2901 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_LSB 0
2902 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field. */
2903 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_MSB 31
2904 /* The width in bits of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field. */
2905 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_WIDTH 32
2906 /* The mask used to set the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value. */
2907 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET_MSK 0xffffffff
2908 /* The mask used to clear the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value. */
2909 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_CLR_MSK 0x00000000
2910 /* The reset value of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field. */
2911 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_RESET 0x0
2912 /* Extracts the ALT_ECC_HMC_OCP_DERRADDRA_DADDR field value from a register. */
2913 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_GET(value) (((value) & 0xffffffff) >> 0)
2914 /* Produces a ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value suitable for setting the register. */
2915 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET(value) (((value) << 0) & 0xffffffff)
2916 
2917 #ifndef __ASSEMBLY__
2918 /*
2919  * WARNING: The C register and register group struct declarations are provided for
2920  * convenience and illustrative purposes. They should, however, be used with
2921  * caution as the C language standard provides no guarantees about the alignment or
2922  * atomicity of device memory accesses. The recommended practice for writing
2923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2924  * alt_write_word() functions.
2925  *
2926  * The struct declaration for register ALT_ECC_HMC_OCP_DERRADDRA.
2927  */
2928 struct ALT_ECC_HMC_OCP_DERRADDRA_s
2929 {
2930  uint32_t DADDRESS : 32; /* ALT_ECC_HMC_OCP_DERRADDRA_DADDR */
2931 };
2932 
2933 /* The typedef declaration for register ALT_ECC_HMC_OCP_DERRADDRA. */
2934 typedef volatile struct ALT_ECC_HMC_OCP_DERRADDRA_s ALT_ECC_HMC_OCP_DERRADDRA_t;
2935 #endif /* __ASSEMBLY__ */
2936 
2937 /* The reset value of the ALT_ECC_HMC_OCP_DERRADDRA register. */
2938 #define ALT_ECC_HMC_OCP_DERRADDRA_RESET 0x00000000
2939 /* The byte offset of the ALT_ECC_HMC_OCP_DERRADDRA register from the beginning of the component. */
2940 #define ALT_ECC_HMC_OCP_DERRADDRA_OFST 0x12c
2941 
2942 /*
2943  * Register : SERRADDRA
2944  *
2945  * Single-bit error address
2946  *
2947  * Register Layout
2948  *
2949  * Bits | Access | Reset | Description
2950  * :-------|:-------|:------|:--------------------------------
2951  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_SERRADDRA_SADDR
2952  *
2953  */
2954 /*
2955  * Field : SADDRESS
2956  *
2957  * Recent single-bit error address.
2958  *
2959  * This register shows the address of the current single-bit error. This address is
2960  * logged when a new serr_req is generated to the system. This is gated by the
2961  * single-bit error interrupt enable and ecc_en.
2962  *
2963  * Field Access Macros:
2964  *
2965  */
2966 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field. */
2967 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_LSB 0
2968 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field. */
2969 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_MSB 31
2970 /* The width in bits of the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field. */
2971 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_WIDTH 32
2972 /* The mask used to set the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field value. */
2973 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET_MSK 0xffffffff
2974 /* The mask used to clear the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field value. */
2975 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_CLR_MSK 0x00000000
2976 /* The reset value of the ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field. */
2977 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_RESET 0x0
2978 /* Extracts the ALT_ECC_HMC_OCP_SERRADDRA_SADDR field value from a register. */
2979 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_GET(value) (((value) & 0xffffffff) >> 0)
2980 /* Produces a ALT_ECC_HMC_OCP_SERRADDRA_SADDR register field value suitable for setting the register. */
2981 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET(value) (((value) << 0) & 0xffffffff)
2982 
2983 #ifndef __ASSEMBLY__
2984 /*
2985  * WARNING: The C register and register group struct declarations are provided for
2986  * convenience and illustrative purposes. They should, however, be used with
2987  * caution as the C language standard provides no guarantees about the alignment or
2988  * atomicity of device memory accesses. The recommended practice for writing
2989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2990  * alt_write_word() functions.
2991  *
2992  * The struct declaration for register ALT_ECC_HMC_OCP_SERRADDRA.
2993  */
2994 struct ALT_ECC_HMC_OCP_SERRADDRA_s
2995 {
2996  uint32_t SADDRESS : 32; /* ALT_ECC_HMC_OCP_SERRADDRA_SADDR */
2997 };
2998 
2999 /* The typedef declaration for register ALT_ECC_HMC_OCP_SERRADDRA. */
3000 typedef volatile struct ALT_ECC_HMC_OCP_SERRADDRA_s ALT_ECC_HMC_OCP_SERRADDRA_t;
3001 #endif /* __ASSEMBLY__ */
3002 
3003 /* The reset value of the ALT_ECC_HMC_OCP_SERRADDRA register. */
3004 #define ALT_ECC_HMC_OCP_SERRADDRA_RESET 0x00000000
3005 /* The byte offset of the ALT_ECC_HMC_OCP_SERRADDRA register from the beginning of the component. */
3006 #define ALT_ECC_HMC_OCP_SERRADDRA_OFST 0x130
3007 
3008 /*
3009  * Register : AUTOWB_CORRADDR
3010  *
3011  * This register shows the address of the current autoWB correction SBE.
3012  *
3013  * Register Layout
3014  *
3015  * Bits | Access | Reset | Description
3016  * :-------|:-------|:------|:----------------------------------------
3017  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR
3018  *
3019  */
3020 /*
3021  * Field : SWBADDRESS
3022  *
3023  * recent autoWB correction address.
3024  *
3025  * This register shows the address of the current autoWB correction single-bit
3026  * error. This address is logged when a new serr_req is generated to the system.
3027  * This is gated by the single-bit error interrupt enable and ecc_en.
3028  *
3029  * Field Access Macros:
3030  *
3031  */
3032 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field. */
3033 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_LSB 0
3034 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field. */
3035 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_MSB 31
3036 /* The width in bits of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field. */
3037 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_WIDTH 32
3038 /* The mask used to set the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field value. */
3039 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET_MSK 0xffffffff
3040 /* The mask used to clear the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field value. */
3041 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_CLR_MSK 0x00000000
3042 /* The reset value of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field. */
3043 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_RESET 0x0
3044 /* Extracts the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR field value from a register. */
3045 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_GET(value) (((value) & 0xffffffff) >> 0)
3046 /* Produces a ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR register field value suitable for setting the register. */
3047 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET(value) (((value) << 0) & 0xffffffff)
3048 
3049 #ifndef __ASSEMBLY__
3050 /*
3051  * WARNING: The C register and register group struct declarations are provided for
3052  * convenience and illustrative purposes. They should, however, be used with
3053  * caution as the C language standard provides no guarantees about the alignment or
3054  * atomicity of device memory accesses. The recommended practice for writing
3055  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3056  * alt_write_word() functions.
3057  *
3058  * The struct declaration for register ALT_ECC_HMC_OCP_AUTOWB_CORRADDR.
3059  */
3060 struct ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s
3061 {
3062  uint32_t SWBADDRESS : 32; /* ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR */
3063 };
3064 
3065 /* The typedef declaration for register ALT_ECC_HMC_OCP_AUTOWB_CORRADDR. */
3066 typedef volatile struct ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t;
3067 #endif /* __ASSEMBLY__ */
3068 
3069 /* The reset value of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR register. */
3070 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_RESET 0x00000000
3071 /* The byte offset of the ALT_ECC_HMC_OCP_AUTOWB_CORRADDR register from the beginning of the component. */
3072 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_OFST 0x138
3073 
3074 /*
3075  * Register : SERRCNTREG
3076  *
3077  * Maximum counter value for single-bit error interrupt
3078  *
3079  * Register Layout
3080  *
3081  * Bits | Access | Reset | Description
3082  * :-------|:-------|:------|:-----------------------------------
3083  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT
3084  *
3085  */
3086 /*
3087  * Field : SERRCNT
3088  *
3089  * Compare value for the internal single-bit errors.
3090  *
3091  * This register sets the value to compare with the internal counter. Software
3092  * should write to this register before enabling the interrupt on compare.
3093  *
3094  * 0x0: If the serrcnt bits are not modified before enabling the intoncmp, internal
3095  * counter=0 and serrcnt=0, serr compare interrupt will not occur. Default after
3096  * reset.
3097  *
3098  * Nonzero: if internal counter == serrcnt == nonzero will create a serr compare
3099  * interrupt.
3100  *
3101  * When the compare matches, autoWB_drop_cmpflga will be set.
3102  *
3103  * Field Access Macros:
3104  *
3105  */
3106 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field. */
3107 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_LSB 0
3108 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field. */
3109 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_MSB 31
3110 /* The width in bits of the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field. */
3111 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_WIDTH 32
3112 /* The mask used to set the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field value. */
3113 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
3114 /* The mask used to clear the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field value. */
3115 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
3116 /* The reset value of the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field. */
3117 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_RESET 0x0
3118 /* Extracts the ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT field value from a register. */
3119 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
3120 /* Produces a ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
3121 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
3122 
3123 #ifndef __ASSEMBLY__
3124 /*
3125  * WARNING: The C register and register group struct declarations are provided for
3126  * convenience and illustrative purposes. They should, however, be used with
3127  * caution as the C language standard provides no guarantees about the alignment or
3128  * atomicity of device memory accesses. The recommended practice for writing
3129  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3130  * alt_write_word() functions.
3131  *
3132  * The struct declaration for register ALT_ECC_HMC_OCP_SERRCNTREG.
3133  */
3134 struct ALT_ECC_HMC_OCP_SERRCNTREG_s
3135 {
3136  uint32_t SERRCNT : 32; /* ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT */
3137 };
3138 
3139 /* The typedef declaration for register ALT_ECC_HMC_OCP_SERRCNTREG. */
3140 typedef volatile struct ALT_ECC_HMC_OCP_SERRCNTREG_s ALT_ECC_HMC_OCP_SERRCNTREG_t;
3141 #endif /* __ASSEMBLY__ */
3142 
3143 /* The reset value of the ALT_ECC_HMC_OCP_SERRCNTREG register. */
3144 #define ALT_ECC_HMC_OCP_SERRCNTREG_RESET 0x00000000
3145 /* The byte offset of the ALT_ECC_HMC_OCP_SERRCNTREG register from the beginning of the component. */
3146 #define ALT_ECC_HMC_OCP_SERRCNTREG_OFST 0x13c
3147 
3148 /*
3149  * Register : AUTOWB_DROP_CNTREG
3150  *
3151  * Maximum counter value for AUTOWB correction interrupt
3152  *
3153  * Register Layout
3154  *
3155  * Bits | Access | Reset | Description
3156  * :-------|:-------|:------|:---------------------------------------
3157  * [31:0] | RW | 0x1 | ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT
3158  *
3159  */
3160 /*
3161  * Field : CNT
3162  *
3163  * Compare value for the internal autoWB correction count.
3164  *
3165  * This register sets the value to compare with the autoWB internal counter.
3166  * Software should write to this register before enabling the interrupt on compare.
3167  *
3168  * 0x1: If the autoWB_drop_cntreg bits are not modified before enabling the
3169  * hmi_intr, autoWB internal counter=0 and autoWB_dop_cnt =1, serr compare
3170  * interrupt will not occur. Default after reset.
3171  *
3172  * Nonzero: if autoWB internal counter == autoWB_drop_cnt == nonzero will create a
3173  * serr compare interrupt.
3174  *
3175  * When the compare matches, autoWB_drop_flg will be set.
3176  *
3177  * Field Access Macros:
3178  *
3179  */
3180 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field. */
3181 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_LSB 0
3182 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field. */
3183 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_MSB 31
3184 /* The width in bits of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field. */
3185 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_WIDTH 32
3186 /* The mask used to set the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field value. */
3187 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET_MSK 0xffffffff
3188 /* The mask used to clear the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field value. */
3189 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_CLR_MSK 0x00000000
3190 /* The reset value of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field. */
3191 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_RESET 0x1
3192 /* Extracts the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT field value from a register. */
3193 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_GET(value) (((value) & 0xffffffff) >> 0)
3194 /* Produces a ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT register field value suitable for setting the register. */
3195 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET(value) (((value) << 0) & 0xffffffff)
3196 
3197 #ifndef __ASSEMBLY__
3198 /*
3199  * WARNING: The C register and register group struct declarations are provided for
3200  * convenience and illustrative purposes. They should, however, be used with
3201  * caution as the C language standard provides no guarantees about the alignment or
3202  * atomicity of device memory accesses. The recommended practice for writing
3203  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3204  * alt_write_word() functions.
3205  *
3206  * The struct declaration for register ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG.
3207  */
3208 struct ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s
3209 {
3210  uint32_t CNT : 32; /* ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT */
3211 };
3212 
3213 /* The typedef declaration for register ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG. */
3214 typedef volatile struct ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t;
3215 #endif /* __ASSEMBLY__ */
3216 
3217 /* The reset value of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG register. */
3218 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_RESET 0x00000001
3219 /* The byte offset of the ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG register from the beginning of the component. */
3220 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_OFST 0x140
3221 
3222 /*
3223  * Register : ECC_REG2WRECCDATABUS
3224  *
3225  * ECC from register associated to data which will be written to the RAM
3226  *
3227  * Register Layout
3228  *
3229  * Bits | Access | Reset | Description
3230  * :--------|:-------|:------|:---------------------------------------------
3231  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS
3232  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS
3233  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS
3234  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS
3235  *
3236  */
3237 /*
3238  * Field : ECC0BUS
3239  *
3240  * ECC from register associated to data [63:0] which will be written to the RAM
3241  *
3242  * Field Access Macros:
3243  *
3244  */
3245 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
3246 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_LSB 0
3247 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
3248 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_MSB 7
3249 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
3250 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_WIDTH 8
3251 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field value. */
3252 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3253 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field value. */
3254 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3255 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field. */
3256 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_RESET 0x0
3257 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS field value from a register. */
3258 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3259 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS register field value suitable for setting the register. */
3260 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3261 
3262 /*
3263  * Field : ECC1BUS
3264  *
3265  * ECC from register associated to data [127:64] which will be written to the RAM
3266  *
3267  * Field Access Macros:
3268  *
3269  */
3270 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
3271 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_LSB 8
3272 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
3273 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_MSB 15
3274 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
3275 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_WIDTH 8
3276 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field value. */
3277 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3278 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field value. */
3279 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3280 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field. */
3281 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_RESET 0x0
3282 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS field value from a register. */
3283 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3284 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS register field value suitable for setting the register. */
3285 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3286 
3287 /*
3288  * Field : ECC2BUS
3289  *
3290  * ECC from register associated to data [191:128] which will be written to the RAM
3291  *
3292  * Field Access Macros:
3293  *
3294  */
3295 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
3296 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_LSB 16
3297 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
3298 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_MSB 23
3299 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
3300 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_WIDTH 8
3301 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field value. */
3302 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3303 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field value. */
3304 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3305 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field. */
3306 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_RESET 0x0
3307 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS field value from a register. */
3308 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3309 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS register field value suitable for setting the register. */
3310 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3311 
3312 /*
3313  * Field : ECC3BUS
3314  *
3315  * ECC from register associated to data [255:192] which will be written to the RAM
3316  *
3317  * Field Access Macros:
3318  *
3319  */
3320 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
3321 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_LSB 24
3322 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
3323 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_MSB 31
3324 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
3325 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_WIDTH 8
3326 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field value. */
3327 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3328 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field value. */
3329 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3330 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field. */
3331 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_RESET 0x0
3332 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS field value from a register. */
3333 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3334 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS register field value suitable for setting the register. */
3335 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3336 
3337 #ifndef __ASSEMBLY__
3338 /*
3339  * WARNING: The C register and register group struct declarations are provided for
3340  * convenience and illustrative purposes. They should, however, be used with
3341  * caution as the C language standard provides no guarantees about the alignment or
3342  * atomicity of device memory accesses. The recommended practice for writing
3343  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3344  * alt_write_word() functions.
3345  *
3346  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS.
3347  */
3348 struct ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s
3349 {
3350  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS */
3351  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS */
3352  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS */
3353  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS */
3354 };
3355 
3356 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS. */
3357 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t;
3358 #endif /* __ASSEMBLY__ */
3359 
3360 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS register. */
3361 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_RESET 0x00000000
3362 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS register from the beginning of the component. */
3363 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_OFST 0x144
3364 
3365 /*
3366  * Register : ECC_RDECCDATA2REGBUS
3367  *
3368  * ECC of data from RAM will be written to register
3369  *
3370  * Register Layout
3371  *
3372  * Bits | Access | Reset | Description
3373  * :--------|:-------|:------|:---------------------------------------------
3374  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS
3375  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS
3376  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS
3377  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS
3378  *
3379  */
3380 /*
3381  * Field : ECC0BUS
3382  *
3383  * ECC of data [63:0] from RAM which will be written to register.
3384  *
3385  * Based on the DDR IO width, unimplemented bytes of this register will read as
3386  * zero.
3387  *
3388  * Field Access Macros:
3389  *
3390  */
3391 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
3392 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_LSB 0
3393 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
3394 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_MSB 7
3395 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
3396 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_WIDTH 8
3397 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value. */
3398 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET_MSK 0x000000ff
3399 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value. */
3400 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_CLR_MSK 0xffffff00
3401 /* The reset value of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field. */
3402 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_RESET 0x0
3403 /* Extracts the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS field value from a register. */
3404 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3405 /* Produces a ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS register field value suitable for setting the register. */
3406 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3407 
3408 /*
3409  * Field : ECC1BUS
3410  *
3411  * ECC of data [127:64] from RAM which will be written to register.
3412  *
3413  * Based on the DDR IO width, unimplemented bytes of this register will read as
3414  * zero.
3415  *
3416  * Field Access Macros:
3417  *
3418  */
3419 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
3420 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_LSB 8
3421 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
3422 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_MSB 15
3423 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
3424 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_WIDTH 8
3425 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value. */
3426 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET_MSK 0x0000ff00
3427 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value. */
3428 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_CLR_MSK 0xffff00ff
3429 /* The reset value of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field. */
3430 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_RESET 0x0
3431 /* Extracts the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS field value from a register. */
3432 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3433 /* Produces a ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS register field value suitable for setting the register. */
3434 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3435 
3436 /*
3437  * Field : ECC2BUS
3438  *
3439  * ECC of data [191:128] from RAM which will be written to register.
3440  *
3441  * Based on the DDR IO width, unimplemented bytes of this register will read as
3442  * zero.
3443  *
3444  * Field Access Macros:
3445  *
3446  */
3447 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
3448 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_LSB 16
3449 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
3450 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_MSB 23
3451 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
3452 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_WIDTH 8
3453 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value. */
3454 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET_MSK 0x00ff0000
3455 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value. */
3456 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_CLR_MSK 0xff00ffff
3457 /* The reset value of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field. */
3458 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_RESET 0x0
3459 /* Extracts the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS field value from a register. */
3460 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3461 /* Produces a ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS register field value suitable for setting the register. */
3462 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3463 
3464 /*
3465  * Field : ECC3BUS
3466  *
3467  * ECC of data [255:192] from RAM which will be written to register.
3468  *
3469  * Based on the DDR IO width, unimplemented bytes of this register will read as
3470  * zero.
3471  *
3472  * Field Access Macros:
3473  *
3474  */
3475 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
3476 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_LSB 24
3477 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
3478 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_MSB 31
3479 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
3480 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_WIDTH 8
3481 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value. */
3482 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET_MSK 0xff000000
3483 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value. */
3484 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_CLR_MSK 0x00ffffff
3485 /* The reset value of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field. */
3486 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_RESET 0x0
3487 /* Extracts the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS field value from a register. */
3488 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3489 /* Produces a ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS register field value suitable for setting the register. */
3490 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3491 
3492 #ifndef __ASSEMBLY__
3493 /*
3494  * WARNING: The C register and register group struct declarations are provided for
3495  * convenience and illustrative purposes. They should, however, be used with
3496  * caution as the C language standard provides no guarantees about the alignment or
3497  * atomicity of device memory accesses. The recommended practice for writing
3498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3499  * alt_write_word() functions.
3500  *
3501  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS.
3502  */
3503 struct ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s
3504 {
3505  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS */
3506  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS */
3507  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS */
3508  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS */
3509 };
3510 
3511 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS. */
3512 typedef volatile struct ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t;
3513 #endif /* __ASSEMBLY__ */
3514 
3515 /* The reset value of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS register. */
3516 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_RESET 0x00000000
3517 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS register from the beginning of the component. */
3518 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_OFST 0x148
3519 
3520 /*
3521  * Register : ECC_REG2RDECCDATABUS
3522  *
3523  * ECC from register associated to RD data which will be written to hmc ecc
3524  *
3525  * Register Layout
3526  *
3527  * Bits | Access | Reset | Description
3528  * :--------|:-------|:------|:---------------------------------------------
3529  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS
3530  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS
3531  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS
3532  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS
3533  *
3534  */
3535 /*
3536  * Field : ECC0BUS
3537  *
3538  * ECC from register associated to RD data [63:0] which will be written to hmc ecc.
3539  *
3540  * Based on the DDR IO width, unimplemented bytes of this register will read as
3541  * zero.
3542  *
3543  * Field Access Macros:
3544  *
3545  */
3546 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
3547 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0
3548 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
3549 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7
3550 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
3551 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8
3552 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value. */
3553 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3554 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value. */
3555 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3556 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field. */
3557 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0
3558 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS field value from a register. */
3559 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3560 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value suitable for setting the register. */
3561 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3562 
3563 /*
3564  * Field : ECC1BUS
3565  *
3566  * ECC from register associated to RD data [127:64] which will be written to hmc
3567  * ecc.
3568  *
3569  * Based on the DDR IO width, unimplemented bytes of this register will read as
3570  * zero.
3571  *
3572  * Field Access Macros:
3573  *
3574  */
3575 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
3576 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8
3577 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
3578 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15
3579 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
3580 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8
3581 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value. */
3582 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3583 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value. */
3584 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3585 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field. */
3586 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0
3587 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS field value from a register. */
3588 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3589 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value suitable for setting the register. */
3590 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3591 
3592 /*
3593  * Field : ECC2BUS
3594  *
3595  * ECC from register associated to RD data [191:128] which will be written to hmc
3596  * ecc.
3597  *
3598  * Based on the DDR IO width, unimplemented bytes of this register will read as
3599  * zero.
3600  *
3601  * Field Access Macros:
3602  *
3603  */
3604 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
3605 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16
3606 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
3607 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23
3608 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
3609 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8
3610 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value. */
3611 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3612 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value. */
3613 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3614 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field. */
3615 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0
3616 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS field value from a register. */
3617 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3618 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value suitable for setting the register. */
3619 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3620 
3621 /*
3622  * Field : ECC3BUS
3623  *
3624  * ECC from register associated to RD data [255:192] which will be written to hmc
3625  * ecc.
3626  *
3627  * Based on the DDR IO width, unimplemented bytes of this register will read as
3628  * zero.
3629  *
3630  * Field Access Macros:
3631  *
3632  */
3633 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
3634 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24
3635 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
3636 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31
3637 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
3638 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8
3639 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value. */
3640 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3641 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value. */
3642 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3643 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field. */
3644 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0
3645 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS field value from a register. */
3646 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3647 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value suitable for setting the register. */
3648 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3649 
3650 #ifndef __ASSEMBLY__
3651 /*
3652  * WARNING: The C register and register group struct declarations are provided for
3653  * convenience and illustrative purposes. They should, however, be used with
3654  * caution as the C language standard provides no guarantees about the alignment or
3655  * atomicity of device memory accesses. The recommended practice for writing
3656  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3657  * alt_write_word() functions.
3658  *
3659  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS.
3660  */
3661 struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s
3662 {
3663  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS */
3664  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS */
3665  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS */
3666  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS */
3667 };
3668 
3669 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS. */
3670 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t;
3671 #endif /* __ASSEMBLY__ */
3672 
3673 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS register. */
3674 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_RESET 0x00000000
3675 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS register from the beginning of the component. */
3676 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_OFST 0x14c
3677 
3678 /*
3679  * Register : ECC_DIAGON
3680  *
3681  * Enable diagnostics access
3682  *
3683  * Register Layout
3684  *
3685  * Bits | Access | Reset | Description
3686  * :--------|:-------|:------|:-------------------------------------
3687  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON
3688  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON
3689  * [15:2] | ??? | 0x0 | *UNDEFINED*
3690  * [16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON
3691  * [31:17] | ??? | 0x0 | *UNDEFINED*
3692  *
3693  */
3694 /*
3695  * Field : WRDIAGON
3696  *
3697  * Write diagnostics mux enabled.
3698  *
3699  * This overrides the encoder output with the register data ecc.
3700  *
3701  * 1'b0: Write diagnostics path via the ecc_reg2wdatabus is disabled.
3702  *
3703  * 1'b1: Write diagnostics path via the ecc_reg2wdatabus is enabled.
3704  *
3705  * Both Rddiagon and Wrdiagon bits can be enabled.
3706  *
3707  * Field Access Macros:
3708  *
3709  */
3710 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field. */
3711 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_LSB 0
3712 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field. */
3713 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_MSB 0
3714 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field. */
3715 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_WIDTH 1
3716 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value. */
3717 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001
3718 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value. */
3719 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe
3720 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field. */
3721 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_RESET 0x0
3722 /* Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON field value from a register. */
3723 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0)
3724 /* Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value suitable for setting the register. */
3725 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001)
3726 
3727 /*
3728  * Field : RDDIAGON
3729  *
3730  * Read diagnostics mux enabled.
3731  *
3732  * This overrides the data entering the ECC decoder.
3733  *
3734  * 1'b0: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is
3735  * disabled.
3736  *
3737  * 1'b1: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is
3738  * enabled.
3739  *
3740  * Both Rddiagon and Wrdiagon bits can be enabled.
3741  *
3742  * Field Access Macros:
3743  *
3744  */
3745 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field. */
3746 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_LSB 1
3747 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field. */
3748 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_MSB 1
3749 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field. */
3750 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_WIDTH 1
3751 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value. */
3752 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002
3753 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value. */
3754 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd
3755 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field. */
3756 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_RESET 0x0
3757 /* Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON field value from a register. */
3758 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1)
3759 /* Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value suitable for setting the register. */
3760 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002)
3761 
3762 /*
3763  * Field : ECCDIAGON
3764  *
3765  * ECC diagnostics mode.
3766  *
3767  * 1'b0: ECC diagnostics logic is disabled. ECC encoder bypass is disabled.
3768  *
3769  * 1'b1: ECC diagnostics logic is enabled. Direction of ECC data from the register
3770  * to data bus or data bus to ecc register is determined by ECC_rddiagon or
3771  * ECC_wrdiagon.
3772  *
3773  * Field Access Macros:
3774  *
3775  */
3776 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field. */
3777 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_LSB 16
3778 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field. */
3779 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_MSB 16
3780 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field. */
3781 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_WIDTH 1
3782 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value. */
3783 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000
3784 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value. */
3785 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff
3786 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field. */
3787 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_RESET 0x0
3788 /* Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON field value from a register. */
3789 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16)
3790 /* Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value suitable for setting the register. */
3791 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000)
3792 
3793 #ifndef __ASSEMBLY__
3794 /*
3795  * WARNING: The C register and register group struct declarations are provided for
3796  * convenience and illustrative purposes. They should, however, be used with
3797  * caution as the C language standard provides no guarantees about the alignment or
3798  * atomicity of device memory accesses. The recommended practice for writing
3799  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3800  * alt_write_word() functions.
3801  *
3802  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_DIAGON.
3803  */
3804 struct ALT_ECC_HMC_OCP_ECC_DIAGON_s
3805 {
3806  uint32_t WRDIAGON : 1; /* ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON */
3807  uint32_t RDDIAGON : 1; /* ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON */
3808  uint32_t : 14; /* *UNDEFINED* */
3809  uint32_t ECCDIAGON : 1; /* ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON */
3810  uint32_t : 15; /* *UNDEFINED* */
3811 };
3812 
3813 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_DIAGON. */
3814 typedef volatile struct ALT_ECC_HMC_OCP_ECC_DIAGON_s ALT_ECC_HMC_OCP_ECC_DIAGON_t;
3815 #endif /* __ASSEMBLY__ */
3816 
3817 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON register. */
3818 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RESET 0x00000000
3819 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_DIAGON register from the beginning of the component. */
3820 #define ALT_ECC_HMC_OCP_ECC_DIAGON_OFST 0x150
3821 
3822 /*
3823  * Register : ECC_DECSTAT
3824  *
3825  * Diagnostic decoder status
3826  *
3827  * Register Layout
3828  *
3829  * Bits | Access | Reset | Description
3830  * :--------|:-------|:------|:----------------------------------------
3831  * [0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG
3832  * [1] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG
3833  * [2] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG
3834  * [3] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG
3835  * [4] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG
3836  * [5] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG
3837  * [6] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG
3838  * [7] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG
3839  * [8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG
3840  * [9] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG
3841  * [10] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG
3842  * [11] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG
3843  * [31:12] | ??? | 0x0 | *UNDEFINED*
3844  *
3845  */
3846 /*
3847  * Field : DEC0SERRFLG
3848  *
3849  * indicates decoder for data [63:0] has detected SBE.
3850  *
3851  * 1'b0: No error has been captured with this flag.
3852  *
3853  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
3854  * hardware and it will be cleared by the writing 1. This flag will be set till SW
3855  * clears. Additional errors will not change the state of this bit. Error flag is
3856  * set on the first beat of erred data.
3857  *
3858  * This won't be reset by the ecc_en bit.
3859  *
3860  * Field Access Macros:
3861  *
3862  */
3863 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field. */
3864 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_LSB 0
3865 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field. */
3866 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_MSB 0
3867 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field. */
3868 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_WIDTH 1
3869 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value. */
3870 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK 0x00000001
3871 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value. */
3872 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
3873 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field. */
3874 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_RESET 0x0
3875 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG field value from a register. */
3876 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
3877 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value suitable for setting the register. */
3878 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
3879 
3880 /*
3881  * Field : DEC1SERRFLG
3882  *
3883  * indicates decoder for data [127:64] has detected SBE.
3884  *
3885  * 1'b0: No error has been captured with this flag.
3886  *
3887  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
3888  * hardware and it will be cleared by the writing 1. This flag will be set till SW
3889  * clears. Additional errors will not change the state of this bit. Error flag is
3890  * set on the first beat of erred data.
3891  *
3892  * This won't be reset by the ecc_en bit.
3893  *
3894  * Field Access Macros:
3895  *
3896  */
3897 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field. */
3898 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_LSB 1
3899 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field. */
3900 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_MSB 1
3901 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field. */
3902 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_WIDTH 1
3903 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value. */
3904 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK 0x00000002
3905 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value. */
3906 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
3907 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field. */
3908 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_RESET 0x0
3909 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG field value from a register. */
3910 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
3911 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value suitable for setting the register. */
3912 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
3913 
3914 /*
3915  * Field : DEC2SERRFLG
3916  *
3917  * indicates decoder for data [191:128] has detected SBE.
3918  *
3919  * 1'b0: No error has been captured with this flag.
3920  *
3921  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
3922  * hardware and it will be cleared by the writing 1. This flag will be set till SW
3923  * clears. Additional errors will not change the state of this bit.Error flag is
3924  * set on the first beat of erred data.
3925  *
3926  * This won't be reset by the ecc_en bit.
3927  *
3928  * Field Access Macros:
3929  *
3930  */
3931 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field. */
3932 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_LSB 2
3933 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field. */
3934 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_MSB 2
3935 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field. */
3936 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_WIDTH 1
3937 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value. */
3938 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK 0x00000004
3939 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value. */
3940 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
3941 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field. */
3942 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_RESET 0x0
3943 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG field value from a register. */
3944 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
3945 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value suitable for setting the register. */
3946 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
3947 
3948 /*
3949  * Field : DEC3SERRFLG
3950  *
3951  * indicates decoder for data [255:192] has detected SBE.
3952  *
3953  * 1'b0: No error has been captured with this flag.
3954  *
3955  * 1'b1: Decoder 0 detected a single bit error. This flag will be set by the
3956  * hardware and it will be cleared by the writing 1. This flag will be set till SW
3957  * clears. Additional errors will not change the state of this bit.Error flag is
3958  * set on the first beat of erred data.
3959  *
3960  * This won't be reset by the ecc_en bit.
3961  *
3962  * Field Access Macros:
3963  *
3964  */
3965 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field. */
3966 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_LSB 3
3967 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field. */
3968 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_MSB 3
3969 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field. */
3970 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_WIDTH 1
3971 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value. */
3972 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK 0x00000008
3973 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value. */
3974 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
3975 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field. */
3976 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_RESET 0x0
3977 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG field value from a register. */
3978 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
3979 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value suitable for setting the register. */
3980 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
3981 
3982 /*
3983  * Field : DEC0ADDRFLG
3984  *
3985  * indicates decoder for data [63:0] has detected address error.
3986  *
3987  * 1'b0: No error has been captured with this flag.
3988  *
3989  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
3990  * hardware and it will be cleared by the writing 1. This flag will be set till SW
3991  * clears.Additional errors will not change the state of this bit.Error flag is set
3992  * on the first beat of erred data.
3993  *
3994  * This won't be reset by the ecc_en bit.
3995  *
3996  * Field Access Macros:
3997  *
3998  */
3999 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field. */
4000 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_LSB 4
4001 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field. */
4002 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_MSB 4
4003 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field. */
4004 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH 1
4005 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value. */
4006 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK 0x00000010
4007 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value. */
4008 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK 0xffffffef
4009 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field. */
4010 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_RESET 0x0
4011 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG field value from a register. */
4012 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_GET(value) (((value) & 0x00000010) >> 4)
4013 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value suitable for setting the register. */
4014 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET(value) (((value) << 4) & 0x00000010)
4015 
4016 /*
4017  * Field : DEC1ADDRFLG
4018  *
4019  * indicates decoder for data [127:64] has detected address error.
4020  *
4021  * 1'b0: No error has been captured with this flag.
4022  *
4023  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
4024  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4025  * clears.Additional errors will not change the state of this bit.Error flag is set
4026  * on the first beat of erred data.
4027  *
4028  * This won't be reset by the ecc_en bit.
4029  *
4030  * Field Access Macros:
4031  *
4032  */
4033 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field. */
4034 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_LSB 5
4035 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field. */
4036 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_MSB 5
4037 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field. */
4038 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH 1
4039 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value. */
4040 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK 0x00000020
4041 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value. */
4042 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK 0xffffffdf
4043 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field. */
4044 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_RESET 0x0
4045 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG field value from a register. */
4046 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_GET(value) (((value) & 0x00000020) >> 5)
4047 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value suitable for setting the register. */
4048 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET(value) (((value) << 5) & 0x00000020)
4049 
4050 /*
4051  * Field : DEC2ADDRFLG
4052  *
4053  * indicates decoder for data [191:128] has detected address error.
4054  *
4055  * 1'b0: No error has been captured with this flag.
4056  *
4057  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
4058  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4059  * clears.Additional errors will not change the state of this bit.Error flag is set
4060  * on the first beat of erred data.
4061  *
4062  * This won't be reset by the ecc_en bit.
4063  *
4064  * Field Access Macros:
4065  *
4066  */
4067 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field. */
4068 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_LSB 6
4069 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field. */
4070 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_MSB 6
4071 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field. */
4072 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH 1
4073 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value. */
4074 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK 0x00000040
4075 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value. */
4076 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK 0xffffffbf
4077 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field. */
4078 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_RESET 0x0
4079 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG field value from a register. */
4080 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_GET(value) (((value) & 0x00000040) >> 6)
4081 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value suitable for setting the register. */
4082 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET(value) (((value) << 6) & 0x00000040)
4083 
4084 /*
4085  * Field : DEC3ADDRFLG
4086  *
4087  * indicates decoder for data [255:192] has detected address error.
4088  *
4089  * 1'b0: No error has been captured with this flag.
4090  *
4091  * 1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the
4092  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4093  * clears.Additional errors will not change the state of this bit.Error flag is set
4094  * on the first beat of erred data.
4095  *
4096  * This won't be reset by the ecc_en bit.
4097  *
4098  * Field Access Macros:
4099  *
4100  */
4101 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field. */
4102 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_LSB 7
4103 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field. */
4104 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_MSB 7
4105 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field. */
4106 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH 1
4107 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value. */
4108 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK 0x00000080
4109 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value. */
4110 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK 0xffffff7f
4111 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field. */
4112 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_RESET 0x0
4113 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG field value from a register. */
4114 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_GET(value) (((value) & 0x00000080) >> 7)
4115 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value suitable for setting the register. */
4116 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET(value) (((value) << 7) & 0x00000080)
4117 
4118 /*
4119  * Field : DEC0DERRFLG
4120  *
4121  * indicates decoder for data [63:0] has detected DBE.
4122  *
4123  * 1'b0: No error has been captured with this flag.
4124  *
4125  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
4126  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4127  * clears. Additional errors will not change the state of this bit. Error flag is
4128  * set on the first beat of erred data.
4129  *
4130  * This won't be reset by the ecc_en bit.
4131  *
4132  * Field Access Macros:
4133  *
4134  */
4135 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field. */
4136 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_LSB 8
4137 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field. */
4138 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_MSB 8
4139 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field. */
4140 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_WIDTH 1
4141 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value. */
4142 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK 0x00000100
4143 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value. */
4144 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
4145 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field. */
4146 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_RESET 0x0
4147 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG field value from a register. */
4148 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
4149 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value suitable for setting the register. */
4150 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
4151 
4152 /*
4153  * Field : DEC1DERRFLG
4154  *
4155  * indicates decoder for data [127:64] has detected DBE.
4156  *
4157  * 1'b0: No error has been captured with this flag.
4158  *
4159  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
4160  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4161  * clears. Additional errors will not change the state of this bit.Error flag is
4162  * set on the first beat of erred data.
4163  *
4164  * This won't be reset by the ecc_en bit.
4165  *
4166  * Field Access Macros:
4167  *
4168  */
4169 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field. */
4170 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_LSB 9
4171 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field. */
4172 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_MSB 9
4173 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field. */
4174 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_WIDTH 1
4175 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value. */
4176 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK 0x00000200
4177 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value. */
4178 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
4179 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field. */
4180 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_RESET 0x0
4181 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG field value from a register. */
4182 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
4183 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value suitable for setting the register. */
4184 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
4185 
4186 /*
4187  * Field : DEC2DERRFLG
4188  *
4189  * indicates decoder for data [191:128] has detected DBE.
4190  *
4191  * 1'b0: No error has been captured with this flag.
4192  *
4193  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
4194  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4195  * clears. Additional errors will not change the state of this bit.Error flag is
4196  * set on the first beat of erred data.
4197  *
4198  * This won't be reset by the ecc_en bit.
4199  *
4200  * Field Access Macros:
4201  *
4202  */
4203 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field. */
4204 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_LSB 10
4205 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field. */
4206 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_MSB 10
4207 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field. */
4208 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_WIDTH 1
4209 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value. */
4210 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK 0x00000400
4211 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value. */
4212 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
4213 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field. */
4214 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_RESET 0x0
4215 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG field value from a register. */
4216 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
4217 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value suitable for setting the register. */
4218 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
4219 
4220 /*
4221  * Field : DEC3DERRFLG
4222  *
4223  * indicates decoder for data [255:192] has detected DBE.
4224  *
4225  * 1'b0: No error has been captured with this flag.
4226  *
4227  * 1'b1: Decoder 0 detected a double-bit error. This flag will be set by the
4228  * hardware and it will be cleared by the writing 1. This flag will be set till SW
4229  * clears. Additional errors will not change the state of this bit. Error flag is
4230  * set on the first beat of erred data.
4231  *
4232  * This won't be reset by the ecc_en bit.
4233  *
4234  * Field Access Macros:
4235  *
4236  */
4237 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field. */
4238 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_LSB 11
4239 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field. */
4240 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_MSB 11
4241 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field. */
4242 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_WIDTH 1
4243 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value. */
4244 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK 0x00000800
4245 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value. */
4246 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
4247 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field. */
4248 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_RESET 0x0
4249 /* Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG field value from a register. */
4250 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
4251 /* Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value suitable for setting the register. */
4252 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
4253 
4254 #ifndef __ASSEMBLY__
4255 /*
4256  * WARNING: The C register and register group struct declarations are provided for
4257  * convenience and illustrative purposes. They should, however, be used with
4258  * caution as the C language standard provides no guarantees about the alignment or
4259  * atomicity of device memory accesses. The recommended practice for writing
4260  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4261  * alt_write_word() functions.
4262  *
4263  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_DECSTAT.
4264  */
4265 struct ALT_ECC_HMC_OCP_ECC_DECSTAT_s
4266 {
4267  uint32_t DEC0SERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG */
4268  uint32_t DEC1SERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG */
4269  uint32_t DEC2SERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG */
4270  uint32_t DEC3SERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG */
4271  uint32_t DEC0ADDRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG */
4272  uint32_t DEC1ADDRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG */
4273  uint32_t DEC2ADDRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG */
4274  uint32_t DEC3ADDRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG */
4275  uint32_t DEC0DERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG */
4276  uint32_t DEC1DERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG */
4277  uint32_t DEC2DERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG */
4278  uint32_t DEC3DERRFLG : 1; /* ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG */
4279  uint32_t : 20; /* *UNDEFINED* */
4280 };
4281 
4282 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_DECSTAT. */
4283 typedef volatile struct ALT_ECC_HMC_OCP_ECC_DECSTAT_s ALT_ECC_HMC_OCP_ECC_DECSTAT_t;
4284 #endif /* __ASSEMBLY__ */
4285 
4286 /* The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT register. */
4287 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_RESET 0x00000000
4288 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_DECSTAT register from the beginning of the component. */
4289 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_OFST 0x154
4290 
4291 /*
4292  * Register : ECC_ERRGENADDR_0
4293  *
4294  * Error address register
4295  *
4296  * Register Layout
4297  *
4298  * Bits | Access | Reset | Description
4299  * :-------|:-------|:------|:--------------------------------------
4300  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR
4301  *
4302  */
4303 /*
4304  * Field : ADDR
4305  *
4306  * For decoder 0.
4307  *
4308  * Address generated with SER or address mismatch logic. Address will be driven by
4309  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
4310  *
4311  * Field Access Macros:
4312  *
4313  */
4314 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field. */
4315 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_LSB 0
4316 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field. */
4317 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_MSB 31
4318 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field. */
4319 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_WIDTH 32
4320 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value. */
4321 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET_MSK 0xffffffff
4322 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value. */
4323 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_CLR_MSK 0x00000000
4324 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field. */
4325 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_RESET 0x0
4326 /* Extracts the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR field value from a register. */
4327 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4328 /* Produces a ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value suitable for setting the register. */
4329 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4330 
4331 #ifndef __ASSEMBLY__
4332 /*
4333  * WARNING: The C register and register group struct declarations are provided for
4334  * convenience and illustrative purposes. They should, however, be used with
4335  * caution as the C language standard provides no guarantees about the alignment or
4336  * atomicity of device memory accesses. The recommended practice for writing
4337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4338  * alt_write_word() functions.
4339  *
4340  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0.
4341  */
4342 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s
4343 {
4344  uint32_t ADDR : 32; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR */
4345 };
4346 
4347 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0. */
4348 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t;
4349 #endif /* __ASSEMBLY__ */
4350 
4351 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 register. */
4352 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_RESET 0x00000000
4353 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 register from the beginning of the component. */
4354 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_OFST 0x160
4355 
4356 /*
4357  * Register : ECC_ERRGENADDR_1
4358  *
4359  * Error address register
4360  *
4361  * Register Layout
4362  *
4363  * Bits | Access | Reset | Description
4364  * :-------|:-------|:------|:--------------------------------------
4365  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR
4366  *
4367  */
4368 /*
4369  * Field : ADDR
4370  *
4371  * For decoder 1.
4372  *
4373  * Address generated with SER or address mismatch logic. Address will be driven by
4374  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
4375  *
4376  * Field Access Macros:
4377  *
4378  */
4379 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field. */
4380 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_LSB 0
4381 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field. */
4382 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_MSB 31
4383 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field. */
4384 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_WIDTH 32
4385 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field value. */
4386 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET_MSK 0xffffffff
4387 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field value. */
4388 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_CLR_MSK 0x00000000
4389 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field. */
4390 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_RESET 0x0
4391 /* Extracts the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR field value from a register. */
4392 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4393 /* Produces a ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR register field value suitable for setting the register. */
4394 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4395 
4396 #ifndef __ASSEMBLY__
4397 /*
4398  * WARNING: The C register and register group struct declarations are provided for
4399  * convenience and illustrative purposes. They should, however, be used with
4400  * caution as the C language standard provides no guarantees about the alignment or
4401  * atomicity of device memory accesses. The recommended practice for writing
4402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4403  * alt_write_word() functions.
4404  *
4405  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1.
4406  */
4407 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s
4408 {
4409  uint32_t ADDR : 32; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR */
4410 };
4411 
4412 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1. */
4413 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t;
4414 #endif /* __ASSEMBLY__ */
4415 
4416 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1 register. */
4417 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_RESET 0x00000000
4418 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1 register from the beginning of the component. */
4419 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_OFST 0x164
4420 
4421 /*
4422  * Register : ECC_ERRGENADDR_2
4423  *
4424  * Error address register
4425  *
4426  * Register Layout
4427  *
4428  * Bits | Access | Reset | Description
4429  * :-------|:-------|:------|:--------------------------------------
4430  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR
4431  *
4432  */
4433 /*
4434  * Field : ADDR
4435  *
4436  * For decoder 2.
4437  *
4438  * Address generated with SER or address mismatch logic. Address will be driven by
4439  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
4440  *
4441  * Field Access Macros:
4442  *
4443  */
4444 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field. */
4445 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_LSB 0
4446 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field. */
4447 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_MSB 31
4448 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field. */
4449 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_WIDTH 32
4450 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field value. */
4451 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET_MSK 0xffffffff
4452 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field value. */
4453 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_CLR_MSK 0x00000000
4454 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field. */
4455 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_RESET 0x0
4456 /* Extracts the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR field value from a register. */
4457 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4458 /* Produces a ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR register field value suitable for setting the register. */
4459 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4460 
4461 #ifndef __ASSEMBLY__
4462 /*
4463  * WARNING: The C register and register group struct declarations are provided for
4464  * convenience and illustrative purposes. They should, however, be used with
4465  * caution as the C language standard provides no guarantees about the alignment or
4466  * atomicity of device memory accesses. The recommended practice for writing
4467  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4468  * alt_write_word() functions.
4469  *
4470  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2.
4471  */
4472 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s
4473 {
4474  uint32_t ADDR : 32; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR */
4475 };
4476 
4477 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2. */
4478 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t;
4479 #endif /* __ASSEMBLY__ */
4480 
4481 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2 register. */
4482 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_RESET 0x00000000
4483 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2 register from the beginning of the component. */
4484 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_OFST 0x168
4485 
4486 /*
4487  * Register : ECC_ERRGENADDR_3
4488  *
4489  * Error address register
4490  *
4491  * Register Layout
4492  *
4493  * Bits | Access | Reset | Description
4494  * :-------|:-------|:------|:--------------------------------------
4495  * [31:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR
4496  *
4497  */
4498 /*
4499  * Field : ADDR
4500  *
4501  * For decoder 3.
4502  *
4503  * Address generated with SER or address mismatch logic. Address will be driven by
4504  * the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.
4505  *
4506  * Field Access Macros:
4507  *
4508  */
4509 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field. */
4510 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_LSB 0
4511 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field. */
4512 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_MSB 31
4513 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field. */
4514 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_WIDTH 32
4515 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field value. */
4516 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET_MSK 0xffffffff
4517 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field value. */
4518 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_CLR_MSK 0x00000000
4519 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field. */
4520 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_RESET 0x0
4521 /* Extracts the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR field value from a register. */
4522 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4523 /* Produces a ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR register field value suitable for setting the register. */
4524 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4525 
4526 #ifndef __ASSEMBLY__
4527 /*
4528  * WARNING: The C register and register group struct declarations are provided for
4529  * convenience and illustrative purposes. They should, however, be used with
4530  * caution as the C language standard provides no guarantees about the alignment or
4531  * atomicity of device memory accesses. The recommended practice for writing
4532  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4533  * alt_write_word() functions.
4534  *
4535  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3.
4536  */
4537 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s
4538 {
4539  uint32_t ADDR : 32; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR */
4540 };
4541 
4542 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3. */
4543 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t;
4544 #endif /* __ASSEMBLY__ */
4545 
4546 /* The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3 register. */
4547 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_RESET 0x00000000
4548 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3 register from the beginning of the component. */
4549 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_OFST 0x16c
4550 
4551 /*
4552  * Register : ECC_REG2RDDATABUS_BEAT0
4553  *
4554  * ECC Reg2Rddatabus_beat0
4555  *
4556  * Register Layout
4557  *
4558  * Bits | Access | Reset | Description
4559  * :--------|:-------|:------|:------------------------------------------------
4560  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS
4561  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS
4562  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS
4563  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS
4564  *
4565  */
4566 /*
4567  * Field : ECC0BUS
4568  *
4569  * Data ECC from the register will be written to the RAM
4570  *
4571  * Field Access Macros:
4572  *
4573  */
4574 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
4575 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_LSB 0
4576 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
4577 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_MSB 7
4578 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
4579 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_WIDTH 8
4580 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value. */
4581 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET_MSK 0x000000ff
4582 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value. */
4583 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_CLR_MSK 0xffffff00
4584 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field. */
4585 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_RESET 0x0
4586 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS field value from a register. */
4587 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4588 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS register field value suitable for setting the register. */
4589 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4590 
4591 /*
4592  * Field : ECC1BUS
4593  *
4594  * Data ECC from the register will be written to the RAM
4595  *
4596  * Field Access Macros:
4597  *
4598  */
4599 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
4600 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_LSB 8
4601 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
4602 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_MSB 15
4603 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
4604 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_WIDTH 8
4605 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value. */
4606 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET_MSK 0x0000ff00
4607 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value. */
4608 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_CLR_MSK 0xffff00ff
4609 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field. */
4610 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_RESET 0x0
4611 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS field value from a register. */
4612 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4613 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS register field value suitable for setting the register. */
4614 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4615 
4616 /*
4617  * Field : ECC2BUS
4618  *
4619  * Data ECC from the register will be written to the RAM
4620  *
4621  * Field Access Macros:
4622  *
4623  */
4624 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
4625 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_LSB 16
4626 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
4627 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_MSB 23
4628 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
4629 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_WIDTH 8
4630 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value. */
4631 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET_MSK 0x00ff0000
4632 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value. */
4633 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_CLR_MSK 0xff00ffff
4634 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field. */
4635 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_RESET 0x0
4636 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS field value from a register. */
4637 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4638 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS register field value suitable for setting the register. */
4639 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4640 
4641 /*
4642  * Field : ECC3BUS
4643  *
4644  * Data ECC from the register will be written to the RAM
4645  *
4646  * Field Access Macros:
4647  *
4648  */
4649 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
4650 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_LSB 24
4651 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
4652 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_MSB 31
4653 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
4654 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_WIDTH 8
4655 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value. */
4656 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET_MSK 0xff000000
4657 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value. */
4658 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_CLR_MSK 0x00ffffff
4659 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field. */
4660 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_RESET 0x0
4661 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS field value from a register. */
4662 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4663 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS register field value suitable for setting the register. */
4664 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4665 
4666 #ifndef __ASSEMBLY__
4667 /*
4668  * WARNING: The C register and register group struct declarations are provided for
4669  * convenience and illustrative purposes. They should, however, be used with
4670  * caution as the C language standard provides no guarantees about the alignment or
4671  * atomicity of device memory accesses. The recommended practice for writing
4672  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4673  * alt_write_word() functions.
4674  *
4675  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0.
4676  */
4677 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s
4678 {
4679  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS */
4680  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS */
4681  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS */
4682  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS */
4683 };
4684 
4685 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0. */
4686 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t;
4687 #endif /* __ASSEMBLY__ */
4688 
4689 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0 register. */
4690 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_RESET 0x00000000
4691 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0 register from the beginning of the component. */
4692 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_OFST 0x170
4693 
4694 /*
4695  * Register : ECC_REG2RDDATABUS_BEAT1
4696  *
4697  * ECC Reg2Rddatabus_beat1
4698  *
4699  * Register Layout
4700  *
4701  * Bits | Access | Reset | Description
4702  * :--------|:-------|:------|:------------------------------------------------
4703  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS
4704  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS
4705  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS
4706  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS
4707  *
4708  */
4709 /*
4710  * Field : ECC0BUS
4711  *
4712  * Data ECC from the register will be written to the RAM
4713  *
4714  * Field Access Macros:
4715  *
4716  */
4717 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
4718 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_LSB 0
4719 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
4720 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_MSB 7
4721 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
4722 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_WIDTH 8
4723 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value. */
4724 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET_MSK 0x000000ff
4725 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value. */
4726 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_CLR_MSK 0xffffff00
4727 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field. */
4728 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_RESET 0x0
4729 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS field value from a register. */
4730 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4731 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS register field value suitable for setting the register. */
4732 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4733 
4734 /*
4735  * Field : ECC1BUS
4736  *
4737  * Data ECC from the register will be written to the RAM
4738  *
4739  * Field Access Macros:
4740  *
4741  */
4742 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
4743 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_LSB 8
4744 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
4745 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_MSB 15
4746 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
4747 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_WIDTH 8
4748 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value. */
4749 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET_MSK 0x0000ff00
4750 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value. */
4751 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_CLR_MSK 0xffff00ff
4752 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field. */
4753 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_RESET 0x0
4754 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS field value from a register. */
4755 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4756 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS register field value suitable for setting the register. */
4757 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4758 
4759 /*
4760  * Field : ECC2BUS
4761  *
4762  * Data ECC from the register will be written to the RAM
4763  *
4764  * Field Access Macros:
4765  *
4766  */
4767 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
4768 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_LSB 16
4769 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
4770 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_MSB 23
4771 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
4772 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_WIDTH 8
4773 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value. */
4774 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET_MSK 0x00ff0000
4775 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value. */
4776 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_CLR_MSK 0xff00ffff
4777 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field. */
4778 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_RESET 0x0
4779 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS field value from a register. */
4780 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4781 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS register field value suitable for setting the register. */
4782 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4783 
4784 /*
4785  * Field : ECC3BUS
4786  *
4787  * Data ECC from the register will be written to the RAM
4788  *
4789  * Field Access Macros:
4790  *
4791  */
4792 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
4793 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_LSB 24
4794 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
4795 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_MSB 31
4796 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
4797 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_WIDTH 8
4798 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value. */
4799 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET_MSK 0xff000000
4800 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value. */
4801 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_CLR_MSK 0x00ffffff
4802 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field. */
4803 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_RESET 0x0
4804 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS field value from a register. */
4805 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4806 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS register field value suitable for setting the register. */
4807 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4808 
4809 #ifndef __ASSEMBLY__
4810 /*
4811  * WARNING: The C register and register group struct declarations are provided for
4812  * convenience and illustrative purposes. They should, however, be used with
4813  * caution as the C language standard provides no guarantees about the alignment or
4814  * atomicity of device memory accesses. The recommended practice for writing
4815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4816  * alt_write_word() functions.
4817  *
4818  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1.
4819  */
4820 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s
4821 {
4822  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS */
4823  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS */
4824  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS */
4825  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS */
4826 };
4827 
4828 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1. */
4829 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t;
4830 #endif /* __ASSEMBLY__ */
4831 
4832 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1 register. */
4833 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_RESET 0x00000000
4834 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1 register from the beginning of the component. */
4835 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_OFST 0x174
4836 
4837 /*
4838  * Register : ECC_REG2RDDATABUS_BEAT2
4839  *
4840  * ECC Reg2Rddatabus_beat2
4841  *
4842  * Register Layout
4843  *
4844  * Bits | Access | Reset | Description
4845  * :--------|:-------|:------|:------------------------------------------------
4846  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS
4847  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS
4848  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS
4849  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS
4850  *
4851  */
4852 /*
4853  * Field : ECC0BUS
4854  *
4855  * Data ECC from the register will be written to the RAM
4856  *
4857  * Field Access Macros:
4858  *
4859  */
4860 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
4861 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_LSB 0
4862 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
4863 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_MSB 7
4864 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
4865 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_WIDTH 8
4866 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value. */
4867 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET_MSK 0x000000ff
4868 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value. */
4869 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_CLR_MSK 0xffffff00
4870 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field. */
4871 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_RESET 0x0
4872 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS field value from a register. */
4873 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4874 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS register field value suitable for setting the register. */
4875 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4876 
4877 /*
4878  * Field : ECC1BUS
4879  *
4880  * Data ECC from the register will be written to the RAM
4881  *
4882  * Field Access Macros:
4883  *
4884  */
4885 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
4886 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_LSB 8
4887 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
4888 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_MSB 15
4889 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
4890 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_WIDTH 8
4891 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value. */
4892 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET_MSK 0x0000ff00
4893 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value. */
4894 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_CLR_MSK 0xffff00ff
4895 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field. */
4896 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_RESET 0x0
4897 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS field value from a register. */
4898 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4899 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS register field value suitable for setting the register. */
4900 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4901 
4902 /*
4903  * Field : ECC2BUS
4904  *
4905  * Data ECC from the register will be written to the RAM
4906  *
4907  * Field Access Macros:
4908  *
4909  */
4910 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
4911 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_LSB 16
4912 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
4913 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_MSB 23
4914 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
4915 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_WIDTH 8
4916 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value. */
4917 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET_MSK 0x00ff0000
4918 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value. */
4919 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_CLR_MSK 0xff00ffff
4920 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field. */
4921 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_RESET 0x0
4922 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS field value from a register. */
4923 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4924 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS register field value suitable for setting the register. */
4925 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4926 
4927 /*
4928  * Field : ECC3BUS
4929  *
4930  * Data ECC from the register will be written to the RAM
4931  *
4932  * Field Access Macros:
4933  *
4934  */
4935 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
4936 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_LSB 24
4937 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
4938 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_MSB 31
4939 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
4940 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_WIDTH 8
4941 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value. */
4942 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET_MSK 0xff000000
4943 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value. */
4944 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_CLR_MSK 0x00ffffff
4945 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field. */
4946 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_RESET 0x0
4947 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS field value from a register. */
4948 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4949 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS register field value suitable for setting the register. */
4950 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4951 
4952 #ifndef __ASSEMBLY__
4953 /*
4954  * WARNING: The C register and register group struct declarations are provided for
4955  * convenience and illustrative purposes. They should, however, be used with
4956  * caution as the C language standard provides no guarantees about the alignment or
4957  * atomicity of device memory accesses. The recommended practice for writing
4958  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4959  * alt_write_word() functions.
4960  *
4961  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2.
4962  */
4963 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s
4964 {
4965  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS */
4966  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS */
4967  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS */
4968  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS */
4969 };
4970 
4971 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2. */
4972 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t;
4973 #endif /* __ASSEMBLY__ */
4974 
4975 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2 register. */
4976 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_RESET 0x00000000
4977 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2 register from the beginning of the component. */
4978 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_OFST 0x178
4979 
4980 /*
4981  * Register : ECC_REG2RDDATABUS_BEAT3
4982  *
4983  * ECC Reg2Rddatabus_beat3
4984  *
4985  * Register Layout
4986  *
4987  * Bits | Access | Reset | Description
4988  * :--------|:-------|:------|:------------------------------------------------
4989  * [7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS
4990  * [15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS
4991  * [23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS
4992  * [31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS
4993  *
4994  */
4995 /*
4996  * Field : ECC0BUS
4997  *
4998  * Data ECC from the register will be written to the RAM
4999  *
5000  * Field Access Macros:
5001  *
5002  */
5003 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
5004 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_LSB 0
5005 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
5006 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_MSB 7
5007 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
5008 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_WIDTH 8
5009 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value. */
5010 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET_MSK 0x000000ff
5011 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value. */
5012 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_CLR_MSK 0xffffff00
5013 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field. */
5014 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_RESET 0x0
5015 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS field value from a register. */
5016 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
5017 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS register field value suitable for setting the register. */
5018 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
5019 
5020 /*
5021  * Field : ECC1BUS
5022  *
5023  * Data ECC from the register will be written to the RAM
5024  *
5025  * Field Access Macros:
5026  *
5027  */
5028 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
5029 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_LSB 8
5030 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
5031 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_MSB 15
5032 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
5033 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_WIDTH 8
5034 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value. */
5035 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET_MSK 0x0000ff00
5036 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value. */
5037 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_CLR_MSK 0xffff00ff
5038 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field. */
5039 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_RESET 0x0
5040 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS field value from a register. */
5041 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
5042 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS register field value suitable for setting the register. */
5043 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
5044 
5045 /*
5046  * Field : ECC2BUS
5047  *
5048  * Data ECC from the register will be written to the RAM
5049  *
5050  * Field Access Macros:
5051  *
5052  */
5053 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
5054 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_LSB 16
5055 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
5056 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_MSB 23
5057 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
5058 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_WIDTH 8
5059 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value. */
5060 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET_MSK 0x00ff0000
5061 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value. */
5062 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_CLR_MSK 0xff00ffff
5063 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field. */
5064 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_RESET 0x0
5065 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS field value from a register. */
5066 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
5067 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS register field value suitable for setting the register. */
5068 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
5069 
5070 /*
5071  * Field : ECC3BUS
5072  *
5073  * Data ECC from the register will be written to the RAM
5074  *
5075  * Field Access Macros:
5076  *
5077  */
5078 /* The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
5079 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_LSB 24
5080 /* The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
5081 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_MSB 31
5082 /* The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
5083 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_WIDTH 8
5084 /* The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value. */
5085 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET_MSK 0xff000000
5086 /* The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value. */
5087 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_CLR_MSK 0x00ffffff
5088 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field. */
5089 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_RESET 0x0
5090 /* Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS field value from a register. */
5091 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
5092 /* Produces a ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS register field value suitable for setting the register. */
5093 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
5094 
5095 #ifndef __ASSEMBLY__
5096 /*
5097  * WARNING: The C register and register group struct declarations are provided for
5098  * convenience and illustrative purposes. They should, however, be used with
5099  * caution as the C language standard provides no guarantees about the alignment or
5100  * atomicity of device memory accesses. The recommended practice for writing
5101  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5102  * alt_write_word() functions.
5103  *
5104  * The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3.
5105  */
5106 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s
5107 {
5108  uint32_t ECC0BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS */
5109  uint32_t ECC1BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS */
5110  uint32_t ECC2BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS */
5111  uint32_t ECC3BUS : 8; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS */
5112 };
5113 
5114 /* The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3. */
5115 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t;
5116 #endif /* __ASSEMBLY__ */
5117 
5118 /* The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3 register. */
5119 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_RESET 0x00000000
5120 /* The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3 register from the beginning of the component. */
5121 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_OFST 0x17c
5122 
5123 #ifndef __ASSEMBLY__
5124 /*
5125  * WARNING: The C register and register group struct declarations are provided for
5126  * convenience and illustrative purposes. They should, however, be used with
5127  * caution as the C language standard provides no guarantees about the alignment or
5128  * atomicity of device memory accesses. The recommended practice for writing
5129  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5130  * alt_write_word() functions.
5131  *
5132  * The struct declaration for register group ALT_ECC_HMC_OCP.
5133  */
5134 struct ALT_ECC_HMC_OCP_s
5135 {
5136  ALT_ECC_HMC_OCP_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_HMC_OCP_IP_REV_ID */
5137  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
5138  ALT_ECC_HMC_OCP_DDRIOCTL_t DDRIOCTRL; /* ALT_ECC_HMC_OCP_DDRIOCTL */
5139  ALT_ECC_HMC_OCP_DDRCALSTAT_t DDRCALSTAT; /* ALT_ECC_HMC_OCP_DDRCALSTAT */
5140  ALT_ECC_HMC_OCP_MPR_0BEAT1_t MPR_0BEAT1; /* ALT_ECC_HMC_OCP_MPR_0BEAT1 */
5141  ALT_ECC_HMC_OCP_MPR_1BEAT1_t MPR_1BEAT1; /* ALT_ECC_HMC_OCP_MPR_1BEAT1 */
5142  ALT_ECC_HMC_OCP_MPR_2BEAT1_t MPR_2BEAT1; /* ALT_ECC_HMC_OCP_MPR_2BEAT1 */
5143  ALT_ECC_HMC_OCP_MPR_3BEAT1_t MPR_3BEAT1; /* ALT_ECC_HMC_OCP_MPR_3BEAT1 */
5144  ALT_ECC_HMC_OCP_MPR_4BEAT1_t MPR_4BEAT1; /* ALT_ECC_HMC_OCP_MPR_4BEAT1 */
5145  ALT_ECC_HMC_OCP_MPR_5BEAT1_t MPR_5BEAT1; /* ALT_ECC_HMC_OCP_MPR_5BEAT1 */
5146  ALT_ECC_HMC_OCP_MPR_6BEAT1_t MPR_6BEAT1; /* ALT_ECC_HMC_OCP_MPR_6BEAT1 */
5147  ALT_ECC_HMC_OCP_MPR_7BEAT1_t MPR_7BEAT1; /* ALT_ECC_HMC_OCP_MPR_7BEAT1 */
5148  ALT_ECC_HMC_OCP_MPR_8BEAT1_t MPR_8BEAT1; /* ALT_ECC_HMC_OCP_MPR_8BEAT1 */
5149  ALT_ECC_HMC_OCP_MPR_0BEAT2_t MPR_0BEAT2; /* ALT_ECC_HMC_OCP_MPR_0BEAT2 */
5150  ALT_ECC_HMC_OCP_MPR_1BEAT2_t MPR_1BEAT2; /* ALT_ECC_HMC_OCP_MPR_1BEAT2 */
5151  ALT_ECC_HMC_OCP_MPR_2BEAT2_t MPR_2BEAT2; /* ALT_ECC_HMC_OCP_MPR_2BEAT2 */
5152  ALT_ECC_HMC_OCP_MPR_3BEAT2_t MPR_3BEAT2; /* ALT_ECC_HMC_OCP_MPR_3BEAT2 */
5153  ALT_ECC_HMC_OCP_MPR_4BEAT2_t MPR_4BEAT2; /* ALT_ECC_HMC_OCP_MPR_4BEAT2 */
5154  ALT_ECC_HMC_OCP_MPR_5BEAT2_t MPR_5BEAT2; /* ALT_ECC_HMC_OCP_MPR_5BEAT2 */
5155  ALT_ECC_HMC_OCP_MPR_6BEAT2_t MPR_6BEAT2; /* ALT_ECC_HMC_OCP_MPR_6BEAT2 */
5156  ALT_ECC_HMC_OCP_MPR_7BEAT2_t MPR_7BEAT2; /* ALT_ECC_HMC_OCP_MPR_7BEAT2 */
5157  ALT_ECC_HMC_OCP_MPR_8BEAT2_t MPR_8BEAT2; /* ALT_ECC_HMC_OCP_MPR_8BEAT2 */
5158  volatile uint32_t _pad_0x58_0x5f[2]; /* *UNDEFINED* */
5159  ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t AUTO_PRECHARGE; /* ALT_ECC_HMC_OCP_AUTO_PRECHARGE */
5160  volatile uint32_t _pad_0x64_0xff[39]; /* *UNDEFINED* */
5161  ALT_ECC_HMC_OCP_ECCCTL1_t ECCCTRL1; /* ALT_ECC_HMC_OCP_ECCCTL1 */
5162  ALT_ECC_HMC_OCP_ECCCTL2_t ECCCTRL2; /* ALT_ECC_HMC_OCP_ECCCTL2 */
5163  volatile uint32_t _pad_0x108_0x10f[2]; /* *UNDEFINED* */
5164  ALT_ECC_HMC_OCP_ERRINTEN_t ERRINTEN; /* ALT_ECC_HMC_OCP_ERRINTEN */
5165  ALT_ECC_HMC_OCP_ERRINTENS_t ERRINTENS; /* ALT_ECC_HMC_OCP_ERRINTENS */
5166  ALT_ECC_HMC_OCP_ERRINTENR_t ERRINTENR; /* ALT_ECC_HMC_OCP_ERRINTENR */
5167  ALT_ECC_HMC_OCP_INTMOD_t INTMODE; /* ALT_ECC_HMC_OCP_INTMOD */
5168  ALT_ECC_HMC_OCP_INTSTAT_t INTSTAT; /* ALT_ECC_HMC_OCP_INTSTAT */
5169  ALT_ECC_HMC_OCP_DIAGINTTEST_t DIAGINTTEST; /* ALT_ECC_HMC_OCP_DIAGINTTEST */
5170  ALT_ECC_HMC_OCP_MODSTAT_t MODSTAT; /* ALT_ECC_HMC_OCP_MODSTAT */
5171  ALT_ECC_HMC_OCP_DERRADDRA_t DERRADDRA; /* ALT_ECC_HMC_OCP_DERRADDRA */
5172  ALT_ECC_HMC_OCP_SERRADDRA_t SERRADDRA; /* ALT_ECC_HMC_OCP_SERRADDRA */
5173  volatile uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
5174  ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t AUTOWB_CORRADDR; /* ALT_ECC_HMC_OCP_AUTOWB_CORRADDR */
5175  ALT_ECC_HMC_OCP_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_HMC_OCP_SERRCNTREG */
5176  ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t AUTOWB_DROP_CNTREG; /* ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG */
5177  ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t ECC_REG2WRECCDATABUS; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS */
5178  ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t ECC_RDECCDATA2REGBUS; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS */
5179  ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t ECC_REG2RDECCDATABUS; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS */
5180  ALT_ECC_HMC_OCP_ECC_DIAGON_t ECC_DIAGON; /* ALT_ECC_HMC_OCP_ECC_DIAGON */
5181  ALT_ECC_HMC_OCP_ECC_DECSTAT_t ECC_DECSTAT; /* ALT_ECC_HMC_OCP_ECC_DECSTAT */
5182  volatile uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
5183  ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t ECC_ERRGENADDR_0; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 */
5184  ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t ECC_ERRGENADDR_1; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1 */
5185  ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t ECC_ERRGENADDR_2; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2 */
5186  ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t ECC_ERRGENADDR_3; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3 */
5187  ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t ECC_REG2RDDATABUS_BEAT0; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0 */
5188  ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t ECC_REG2RDDATABUS_BEAT1; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1 */
5189  ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t ECC_REG2RDDATABUS_BEAT2; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2 */
5190  ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t ECC_REG2RDDATABUS_BEAT3; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3 */
5191  volatile uint32_t _pad_0x180_0x500[224]; /* *UNDEFINED* */
5192 };
5193 
5194 /* The typedef declaration for register group ALT_ECC_HMC_OCP. */
5195 typedef volatile struct ALT_ECC_HMC_OCP_s ALT_ECC_HMC_OCP_t;
5196 /* The struct declaration for the raw register contents of register group ALT_ECC_HMC_OCP. */
5197 struct ALT_ECC_HMC_OCP_raw_s
5198 {
5199  volatile uint32_t IP_REV_ID; /* ALT_ECC_HMC_OCP_IP_REV_ID */
5200  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
5201  volatile uint32_t DDRIOCTRL; /* ALT_ECC_HMC_OCP_DDRIOCTL */
5202  volatile uint32_t DDRCALSTAT; /* ALT_ECC_HMC_OCP_DDRCALSTAT */
5203  volatile uint32_t MPR_0BEAT1; /* ALT_ECC_HMC_OCP_MPR_0BEAT1 */
5204  volatile uint32_t MPR_1BEAT1; /* ALT_ECC_HMC_OCP_MPR_1BEAT1 */
5205  volatile uint32_t MPR_2BEAT1; /* ALT_ECC_HMC_OCP_MPR_2BEAT1 */
5206  volatile uint32_t MPR_3BEAT1; /* ALT_ECC_HMC_OCP_MPR_3BEAT1 */
5207  volatile uint32_t MPR_4BEAT1; /* ALT_ECC_HMC_OCP_MPR_4BEAT1 */
5208  volatile uint32_t MPR_5BEAT1; /* ALT_ECC_HMC_OCP_MPR_5BEAT1 */
5209  volatile uint32_t MPR_6BEAT1; /* ALT_ECC_HMC_OCP_MPR_6BEAT1 */
5210  volatile uint32_t MPR_7BEAT1; /* ALT_ECC_HMC_OCP_MPR_7BEAT1 */
5211  volatile uint32_t MPR_8BEAT1; /* ALT_ECC_HMC_OCP_MPR_8BEAT1 */
5212  volatile uint32_t MPR_0BEAT2; /* ALT_ECC_HMC_OCP_MPR_0BEAT2 */
5213  volatile uint32_t MPR_1BEAT2; /* ALT_ECC_HMC_OCP_MPR_1BEAT2 */
5214  volatile uint32_t MPR_2BEAT2; /* ALT_ECC_HMC_OCP_MPR_2BEAT2 */
5215  volatile uint32_t MPR_3BEAT2; /* ALT_ECC_HMC_OCP_MPR_3BEAT2 */
5216  volatile uint32_t MPR_4BEAT2; /* ALT_ECC_HMC_OCP_MPR_4BEAT2 */
5217  volatile uint32_t MPR_5BEAT2; /* ALT_ECC_HMC_OCP_MPR_5BEAT2 */
5218  volatile uint32_t MPR_6BEAT2; /* ALT_ECC_HMC_OCP_MPR_6BEAT2 */
5219  volatile uint32_t MPR_7BEAT2; /* ALT_ECC_HMC_OCP_MPR_7BEAT2 */
5220  volatile uint32_t MPR_8BEAT2; /* ALT_ECC_HMC_OCP_MPR_8BEAT2 */
5221  uint32_t _pad_0x58_0x5f[2]; /* *UNDEFINED* */
5222  volatile uint32_t AUTO_PRECHARGE; /* ALT_ECC_HMC_OCP_AUTO_PRECHARGE */
5223  uint32_t _pad_0x64_0xff[39]; /* *UNDEFINED* */
5224  volatile uint32_t ECCCTRL1; /* ALT_ECC_HMC_OCP_ECCCTL1 */
5225  volatile uint32_t ECCCTRL2; /* ALT_ECC_HMC_OCP_ECCCTL2 */
5226  uint32_t _pad_0x108_0x10f[2]; /* *UNDEFINED* */
5227  volatile uint32_t ERRINTEN; /* ALT_ECC_HMC_OCP_ERRINTEN */
5228  volatile uint32_t ERRINTENS; /* ALT_ECC_HMC_OCP_ERRINTENS */
5229  volatile uint32_t ERRINTENR; /* ALT_ECC_HMC_OCP_ERRINTENR */
5230  volatile uint32_t INTMODE; /* ALT_ECC_HMC_OCP_INTMOD */
5231  volatile uint32_t INTSTAT; /* ALT_ECC_HMC_OCP_INTSTAT */
5232  volatile uint32_t DIAGINTTEST; /* ALT_ECC_HMC_OCP_DIAGINTTEST */
5233  volatile uint32_t MODSTAT; /* ALT_ECC_HMC_OCP_MODSTAT */
5234  volatile uint32_t DERRADDRA; /* ALT_ECC_HMC_OCP_DERRADDRA */
5235  volatile uint32_t SERRADDRA; /* ALT_ECC_HMC_OCP_SERRADDRA */
5236  uint32_t _pad_0x134_0x137; /* *UNDEFINED* */
5237  volatile uint32_t AUTOWB_CORRADDR; /* ALT_ECC_HMC_OCP_AUTOWB_CORRADDR */
5238  volatile uint32_t SERRCNTREG; /* ALT_ECC_HMC_OCP_SERRCNTREG */
5239  volatile uint32_t AUTOWB_DROP_CNTREG; /* ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG */
5240  volatile uint32_t ECC_REG2WRECCDATABUS; /* ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS */
5241  volatile uint32_t ECC_RDECCDATA2REGBUS; /* ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS */
5242  volatile uint32_t ECC_REG2RDECCDATABUS; /* ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS */
5243  volatile uint32_t ECC_DIAGON; /* ALT_ECC_HMC_OCP_ECC_DIAGON */
5244  volatile uint32_t ECC_DECSTAT; /* ALT_ECC_HMC_OCP_ECC_DECSTAT */
5245  uint32_t _pad_0x158_0x15f[2]; /* *UNDEFINED* */
5246  volatile uint32_t ECC_ERRGENADDR_0; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 */
5247  volatile uint32_t ECC_ERRGENADDR_1; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1 */
5248  volatile uint32_t ECC_ERRGENADDR_2; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2 */
5249  volatile uint32_t ECC_ERRGENADDR_3; /* ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3 */
5250  volatile uint32_t ECC_REG2RDDATABUS_BEAT0; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0 */
5251  volatile uint32_t ECC_REG2RDDATABUS_BEAT1; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1 */
5252  volatile uint32_t ECC_REG2RDDATABUS_BEAT2; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2 */
5253  volatile uint32_t ECC_REG2RDDATABUS_BEAT3; /* ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3 */
5254  uint32_t _pad_0x180_0x500[224]; /* *UNDEFINED* */
5255 };
5256 
5257 /* The typedef declaration for the raw register contents of register group ALT_ECC_HMC_OCP. */
5258 typedef volatile struct ALT_ECC_HMC_OCP_raw_s ALT_ECC_HMC_OCP_raw_t;
5259 #endif /* __ASSEMBLY__ */
5260 
5261 
5262 #ifdef __cplusplus
5263 }
5264 #endif /* __cplusplus */
5265 #endif /* __ALT_SOCAL_ECC_HMC_OCP_H__ */
5266