Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_ecc_nandw.h
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32 
33 /* Altera - ALT_ECC_NANDW */
34 
35 #ifndef __ALT_SOCAL_ECC_NANDW_H__
36 #define __ALT_SOCAL_ECC_NANDW_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_ECC_NANDW
50  *
51  */
52 /*
53  * Register : IP_REV_ID
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:------------------------------
59  * [15:0] | R | 0x0 | ALT_ECC_NANDW_IP_REV_ID_SIREV
60  * [31:16] | ??? | 0x0 | *UNDEFINED*
61  *
62  */
63 /*
64  * Field : SIREV
65  *
66  * IP Rev #
67  *
68  * These bits indicate the silicon revision number.
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_IP_REV_ID_SIREV register field. */
74 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_MSB 15
77 /* The width in bits of the ALT_ECC_NANDW_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_WIDTH 16
79 /* The mask used to set the ALT_ECC_NANDW_IP_REV_ID_SIREV register field value. */
80 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 /* The mask used to clear the ALT_ECC_NANDW_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 /* The reset value of the ALT_ECC_NANDW_IP_REV_ID_SIREV register field. */
84 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_RESET 0x0
85 /* Extracts the ALT_ECC_NANDW_IP_REV_ID_SIREV field value from a register. */
86 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 /* Produces a ALT_ECC_NANDW_IP_REV_ID_SIREV register field value suitable for setting the register. */
88 #define ALT_ECC_NANDW_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_ECC_NANDW_IP_REV_ID.
100  */
101 struct ALT_ECC_NANDW_IP_REV_ID_s
102 {
103  const uint32_t SIREV : 16; /* ALT_ECC_NANDW_IP_REV_ID_SIREV */
104  uint32_t : 16; /* *UNDEFINED* */
105 };
106 
107 /* The typedef declaration for register ALT_ECC_NANDW_IP_REV_ID. */
108 typedef volatile struct ALT_ECC_NANDW_IP_REV_ID_s ALT_ECC_NANDW_IP_REV_ID_t;
109 #endif /* __ASSEMBLY__ */
110 
111 /* The reset value of the ALT_ECC_NANDW_IP_REV_ID register. */
112 #define ALT_ECC_NANDW_IP_REV_ID_RESET 0x00000000
113 /* The byte offset of the ALT_ECC_NANDW_IP_REV_ID register from the beginning of the component. */
114 #define ALT_ECC_NANDW_IP_REV_ID_OFST 0x0
115 
116 /*
117  * Register : CTRL
118  *
119  * ECC Control Register
120  *
121  * Register Layout
122  *
123  * Bits | Access | Reset | Description
124  * :--------|:-------|:------|:---------------------------
125  * [0] | RW | 0x0 | ALT_ECC_NANDW_CTL_ECC_EN
126  * [7:1] | ??? | 0x0 | *UNDEFINED*
127  * [8] | RW | 0x0 | ALT_ECC_NANDW_CTL_CNT_RSTA
128  * [15:9] | ??? | 0x0 | *UNDEFINED*
129  * [16] | RW | 0x0 | ALT_ECC_NANDW_CTL_INITA
130  * [31:17] | ??? | 0x0 | *UNDEFINED*
131  *
132  */
133 /*
134  * Field : ECC_EN
135  *
136  * Enable for the ECC detection and correction logic.
137  *
138  * Field Access Macros:
139  *
140  */
141 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_CTL_ECC_EN register field. */
142 #define ALT_ECC_NANDW_CTL_ECC_EN_LSB 0
143 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_CTL_ECC_EN register field. */
144 #define ALT_ECC_NANDW_CTL_ECC_EN_MSB 0
145 /* The width in bits of the ALT_ECC_NANDW_CTL_ECC_EN register field. */
146 #define ALT_ECC_NANDW_CTL_ECC_EN_WIDTH 1
147 /* The mask used to set the ALT_ECC_NANDW_CTL_ECC_EN register field value. */
148 #define ALT_ECC_NANDW_CTL_ECC_EN_SET_MSK 0x00000001
149 /* The mask used to clear the ALT_ECC_NANDW_CTL_ECC_EN register field value. */
150 #define ALT_ECC_NANDW_CTL_ECC_EN_CLR_MSK 0xfffffffe
151 /* The reset value of the ALT_ECC_NANDW_CTL_ECC_EN register field. */
152 #define ALT_ECC_NANDW_CTL_ECC_EN_RESET 0x0
153 /* Extracts the ALT_ECC_NANDW_CTL_ECC_EN field value from a register. */
154 #define ALT_ECC_NANDW_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
155 /* Produces a ALT_ECC_NANDW_CTL_ECC_EN register field value suitable for setting the register. */
156 #define ALT_ECC_NANDW_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
157 
158 /*
159  * Field : CNT_RSTA
160  *
161  * Enable to reset internal single-bit error counter A value to zero
162  *
163  * Field Access Macros:
164  *
165  */
166 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_CTL_CNT_RSTA register field. */
167 #define ALT_ECC_NANDW_CTL_CNT_RSTA_LSB 8
168 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_CTL_CNT_RSTA register field. */
169 #define ALT_ECC_NANDW_CTL_CNT_RSTA_MSB 8
170 /* The width in bits of the ALT_ECC_NANDW_CTL_CNT_RSTA register field. */
171 #define ALT_ECC_NANDW_CTL_CNT_RSTA_WIDTH 1
172 /* The mask used to set the ALT_ECC_NANDW_CTL_CNT_RSTA register field value. */
173 #define ALT_ECC_NANDW_CTL_CNT_RSTA_SET_MSK 0x00000100
174 /* The mask used to clear the ALT_ECC_NANDW_CTL_CNT_RSTA register field value. */
175 #define ALT_ECC_NANDW_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
176 /* The reset value of the ALT_ECC_NANDW_CTL_CNT_RSTA register field. */
177 #define ALT_ECC_NANDW_CTL_CNT_RSTA_RESET 0x0
178 /* Extracts the ALT_ECC_NANDW_CTL_CNT_RSTA field value from a register. */
179 #define ALT_ECC_NANDW_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
180 /* Produces a ALT_ECC_NANDW_CTL_CNT_RSTA register field value suitable for setting the register. */
181 #define ALT_ECC_NANDW_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
182 
183 /*
184  * Field : INITA
185  *
186  * Enable for the hardware memory initialization PORTA.
187  *
188  * Field Access Macros:
189  *
190  */
191 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_CTL_INITA register field. */
192 #define ALT_ECC_NANDW_CTL_INITA_LSB 16
193 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_CTL_INITA register field. */
194 #define ALT_ECC_NANDW_CTL_INITA_MSB 16
195 /* The width in bits of the ALT_ECC_NANDW_CTL_INITA register field. */
196 #define ALT_ECC_NANDW_CTL_INITA_WIDTH 1
197 /* The mask used to set the ALT_ECC_NANDW_CTL_INITA register field value. */
198 #define ALT_ECC_NANDW_CTL_INITA_SET_MSK 0x00010000
199 /* The mask used to clear the ALT_ECC_NANDW_CTL_INITA register field value. */
200 #define ALT_ECC_NANDW_CTL_INITA_CLR_MSK 0xfffeffff
201 /* The reset value of the ALT_ECC_NANDW_CTL_INITA register field. */
202 #define ALT_ECC_NANDW_CTL_INITA_RESET 0x0
203 /* Extracts the ALT_ECC_NANDW_CTL_INITA field value from a register. */
204 #define ALT_ECC_NANDW_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
205 /* Produces a ALT_ECC_NANDW_CTL_INITA register field value suitable for setting the register. */
206 #define ALT_ECC_NANDW_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
207 
208 #ifndef __ASSEMBLY__
209 /*
210  * WARNING: The C register and register group struct declarations are provided for
211  * convenience and illustrative purposes. They should, however, be used with
212  * caution as the C language standard provides no guarantees about the alignment or
213  * atomicity of device memory accesses. The recommended practice for writing
214  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
215  * alt_write_word() functions.
216  *
217  * The struct declaration for register ALT_ECC_NANDW_CTL.
218  */
219 struct ALT_ECC_NANDW_CTL_s
220 {
221  uint32_t ECC_EN : 1; /* ALT_ECC_NANDW_CTL_ECC_EN */
222  uint32_t : 7; /* *UNDEFINED* */
223  uint32_t CNT_RSTA : 1; /* ALT_ECC_NANDW_CTL_CNT_RSTA */
224  uint32_t : 7; /* *UNDEFINED* */
225  uint32_t INITA : 1; /* ALT_ECC_NANDW_CTL_INITA */
226  uint32_t : 15; /* *UNDEFINED* */
227 };
228 
229 /* The typedef declaration for register ALT_ECC_NANDW_CTL. */
230 typedef volatile struct ALT_ECC_NANDW_CTL_s ALT_ECC_NANDW_CTL_t;
231 #endif /* __ASSEMBLY__ */
232 
233 /* The reset value of the ALT_ECC_NANDW_CTL register. */
234 #define ALT_ECC_NANDW_CTL_RESET 0x00000000
235 /* The byte offset of the ALT_ECC_NANDW_CTL register from the beginning of the component. */
236 #define ALT_ECC_NANDW_CTL_OFST 0x8
237 
238 /*
239  * Register : INITSTAT
240  *
241  * This bit is used to set the initialize the memory and ecc to a known value
242  *
243  * Register Layout
244  *
245  * Bits | Access | Reset | Description
246  * :-------|:-------|:------|:-------------------------------------
247  * [0] | RW | 0x0 | ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA
248  * [31:1] | ??? | 0x0 | *UNDEFINED*
249  *
250  */
251 /*
252  * Field : INITCOMPLETEA
253  *
254  * This bit is used to verify if the hardware memory initialization has completed
255  * PORTB.
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field. */
261 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_LSB 0
262 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field. */
263 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_MSB 0
264 /* The width in bits of the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field. */
265 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_WIDTH 1
266 /* The mask used to set the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field value. */
267 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
268 /* The mask used to clear the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field value. */
269 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
270 /* The reset value of the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field. */
271 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_RESET 0x0
272 /* Extracts the ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA field value from a register. */
273 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
274 /* Produces a ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA register field value suitable for setting the register. */
275 #define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
276 
277 #ifndef __ASSEMBLY__
278 /*
279  * WARNING: The C register and register group struct declarations are provided for
280  * convenience and illustrative purposes. They should, however, be used with
281  * caution as the C language standard provides no guarantees about the alignment or
282  * atomicity of device memory accesses. The recommended practice for writing
283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
284  * alt_write_word() functions.
285  *
286  * The struct declaration for register ALT_ECC_NANDW_INITSTAT.
287  */
288 struct ALT_ECC_NANDW_INITSTAT_s
289 {
290  uint32_t INITCOMPLETEA : 1; /* ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA */
291  uint32_t : 31; /* *UNDEFINED* */
292 };
293 
294 /* The typedef declaration for register ALT_ECC_NANDW_INITSTAT. */
295 typedef volatile struct ALT_ECC_NANDW_INITSTAT_s ALT_ECC_NANDW_INITSTAT_t;
296 #endif /* __ASSEMBLY__ */
297 
298 /* The reset value of the ALT_ECC_NANDW_INITSTAT register. */
299 #define ALT_ECC_NANDW_INITSTAT_RESET 0x00000000
300 /* The byte offset of the ALT_ECC_NANDW_INITSTAT register from the beginning of the component. */
301 #define ALT_ECC_NANDW_INITSTAT_OFST 0xc
302 
303 /*
304  * Register : ERRINTEN
305  *
306  * Error Interrupt enable
307  *
308  * Register Layout
309  *
310  * Bits | Access | Reset | Description
311  * :-------|:-------|:------|:---------------------------------
312  * [0] | RW | 0x0 | ALT_ECC_NANDW_ERRINTEN_SERRINTEN
313  * [31:1] | ??? | 0x0 | *UNDEFINED*
314  *
315  */
316 /*
317  * Field : SERRINTEN
318  *
319  * This bit is used to enable the single bit error interrupt of ECC RAM system
320  *
321  * Field Access Macros:
322  *
323  */
324 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field. */
325 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_LSB 0
326 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field. */
327 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_MSB 0
328 /* The width in bits of the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field. */
329 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_WIDTH 1
330 /* The mask used to set the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field value. */
331 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
332 /* The mask used to clear the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field value. */
333 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
334 /* The reset value of the ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field. */
335 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_RESET 0x0
336 /* Extracts the ALT_ECC_NANDW_ERRINTEN_SERRINTEN field value from a register. */
337 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
338 /* Produces a ALT_ECC_NANDW_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
339 #define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
340 
341 #ifndef __ASSEMBLY__
342 /*
343  * WARNING: The C register and register group struct declarations are provided for
344  * convenience and illustrative purposes. They should, however, be used with
345  * caution as the C language standard provides no guarantees about the alignment or
346  * atomicity of device memory accesses. The recommended practice for writing
347  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
348  * alt_write_word() functions.
349  *
350  * The struct declaration for register ALT_ECC_NANDW_ERRINTEN.
351  */
352 struct ALT_ECC_NANDW_ERRINTEN_s
353 {
354  uint32_t SERRINTEN : 1; /* ALT_ECC_NANDW_ERRINTEN_SERRINTEN */
355  uint32_t : 31; /* *UNDEFINED* */
356 };
357 
358 /* The typedef declaration for register ALT_ECC_NANDW_ERRINTEN. */
359 typedef volatile struct ALT_ECC_NANDW_ERRINTEN_s ALT_ECC_NANDW_ERRINTEN_t;
360 #endif /* __ASSEMBLY__ */
361 
362 /* The reset value of the ALT_ECC_NANDW_ERRINTEN register. */
363 #define ALT_ECC_NANDW_ERRINTEN_RESET 0x00000000
364 /* The byte offset of the ALT_ECC_NANDW_ERRINTEN register from the beginning of the component. */
365 #define ALT_ECC_NANDW_ERRINTEN_OFST 0x10
366 
367 /*
368  * Register : ERRINTENS
369  *
370  * Error Interrupt set
371  *
372  * Register Layout
373  *
374  * Bits | Access | Reset | Description
375  * :-------|:-------|:------|:---------------------------------
376  * [0] | RW | 0x0 | ALT_ECC_NANDW_ERRINTENS_SERRINTS
377  * [31:1] | ??? | 0x0 | *UNDEFINED*
378  *
379  */
380 /*
381  * Field : SERRINTS
382  *
383  * This bit is used to set the single-bit error interrupt bit.
384  *
385  * Field Access Macros:
386  *
387  */
388 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field. */
389 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_LSB 0
390 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field. */
391 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_MSB 0
392 /* The width in bits of the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field. */
393 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_WIDTH 1
394 /* The mask used to set the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field value. */
395 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_SET_MSK 0x00000001
396 /* The mask used to clear the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field value. */
397 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
398 /* The reset value of the ALT_ECC_NANDW_ERRINTENS_SERRINTS register field. */
399 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_RESET 0x0
400 /* Extracts the ALT_ECC_NANDW_ERRINTENS_SERRINTS field value from a register. */
401 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
402 /* Produces a ALT_ECC_NANDW_ERRINTENS_SERRINTS register field value suitable for setting the register. */
403 #define ALT_ECC_NANDW_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
404 
405 #ifndef __ASSEMBLY__
406 /*
407  * WARNING: The C register and register group struct declarations are provided for
408  * convenience and illustrative purposes. They should, however, be used with
409  * caution as the C language standard provides no guarantees about the alignment or
410  * atomicity of device memory accesses. The recommended practice for writing
411  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
412  * alt_write_word() functions.
413  *
414  * The struct declaration for register ALT_ECC_NANDW_ERRINTENS.
415  */
416 struct ALT_ECC_NANDW_ERRINTENS_s
417 {
418  uint32_t SERRINTS : 1; /* ALT_ECC_NANDW_ERRINTENS_SERRINTS */
419  uint32_t : 31; /* *UNDEFINED* */
420 };
421 
422 /* The typedef declaration for register ALT_ECC_NANDW_ERRINTENS. */
423 typedef volatile struct ALT_ECC_NANDW_ERRINTENS_s ALT_ECC_NANDW_ERRINTENS_t;
424 #endif /* __ASSEMBLY__ */
425 
426 /* The reset value of the ALT_ECC_NANDW_ERRINTENS register. */
427 #define ALT_ECC_NANDW_ERRINTENS_RESET 0x00000000
428 /* The byte offset of the ALT_ECC_NANDW_ERRINTENS register from the beginning of the component. */
429 #define ALT_ECC_NANDW_ERRINTENS_OFST 0x14
430 
431 /*
432  * Register : ERRINTENR
433  *
434  * Error Interrupt reset.
435  *
436  * Register Layout
437  *
438  * Bits | Access | Reset | Description
439  * :-------|:-------|:------|:---------------------------------
440  * [0] | RW | 0x0 | ALT_ECC_NANDW_ERRINTENR_SERRINTR
441  * [31:1] | ??? | 0x0 | *UNDEFINED*
442  *
443  */
444 /*
445  * Field : SERRINTR
446  *
447  * This bit is used to reset the single-bit error interrupt bit. o
448  *
449  * Reads reflect SERRINTEN.
450  *
451  * 1'b0: Writing of zero has no effect.
452  *
453  * 1'b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing
454  * a bitwise writing of this feature.
455  *
456  * Field Access Macros:
457  *
458  */
459 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field. */
460 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_LSB 0
461 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field. */
462 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_MSB 0
463 /* The width in bits of the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field. */
464 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_WIDTH 1
465 /* The mask used to set the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field value. */
466 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_SET_MSK 0x00000001
467 /* The mask used to clear the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field value. */
468 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
469 /* The reset value of the ALT_ECC_NANDW_ERRINTENR_SERRINTR register field. */
470 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_RESET 0x0
471 /* Extracts the ALT_ECC_NANDW_ERRINTENR_SERRINTR field value from a register. */
472 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
473 /* Produces a ALT_ECC_NANDW_ERRINTENR_SERRINTR register field value suitable for setting the register. */
474 #define ALT_ECC_NANDW_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
475 
476 #ifndef __ASSEMBLY__
477 /*
478  * WARNING: The C register and register group struct declarations are provided for
479  * convenience and illustrative purposes. They should, however, be used with
480  * caution as the C language standard provides no guarantees about the alignment or
481  * atomicity of device memory accesses. The recommended practice for writing
482  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
483  * alt_write_word() functions.
484  *
485  * The struct declaration for register ALT_ECC_NANDW_ERRINTENR.
486  */
487 struct ALT_ECC_NANDW_ERRINTENR_s
488 {
489  uint32_t SERRINTR : 1; /* ALT_ECC_NANDW_ERRINTENR_SERRINTR */
490  uint32_t : 31; /* *UNDEFINED* */
491 };
492 
493 /* The typedef declaration for register ALT_ECC_NANDW_ERRINTENR. */
494 typedef volatile struct ALT_ECC_NANDW_ERRINTENR_s ALT_ECC_NANDW_ERRINTENR_t;
495 #endif /* __ASSEMBLY__ */
496 
497 /* The reset value of the ALT_ECC_NANDW_ERRINTENR register. */
498 #define ALT_ECC_NANDW_ERRINTENR_RESET 0x00000000
499 /* The byte offset of the ALT_ECC_NANDW_ERRINTENR register from the beginning of the component. */
500 #define ALT_ECC_NANDW_ERRINTENR_OFST 0x18
501 
502 /*
503  * Register : INTMODE
504  *
505  * Reads reflect SERRINTEN.
506  *
507  * Register Layout
508  *
509  * Bits | Access | Reset | Description
510  * :--------|:-------|:------|:------------------------------
511  * [0] | RW | 0x0 | ALT_ECC_NANDW_INTMOD_INTMOD
512  * [7:1] | ??? | 0x0 | *UNDEFINED*
513  * [8] | RW | 0x0 | ALT_ECC_NANDW_INTMOD_INTONOVF
514  * [15:9] | ??? | 0x0 | *UNDEFINED*
515  * [16] | RW | 0x0 | ALT_ECC_NANDW_INTMOD_INTONCMP
516  * [31:17] | ??? | 0x0 | *UNDEFINED*
517  *
518  */
519 /*
520  * Field : INTMODE
521  *
522  * Interrupt mode for single-bit errors.
523  *
524  * Field Access Macros:
525  *
526  */
527 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTMOD_INTMOD register field. */
528 #define ALT_ECC_NANDW_INTMOD_INTMOD_LSB 0
529 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTMOD_INTMOD register field. */
530 #define ALT_ECC_NANDW_INTMOD_INTMOD_MSB 0
531 /* The width in bits of the ALT_ECC_NANDW_INTMOD_INTMOD register field. */
532 #define ALT_ECC_NANDW_INTMOD_INTMOD_WIDTH 1
533 /* The mask used to set the ALT_ECC_NANDW_INTMOD_INTMOD register field value. */
534 #define ALT_ECC_NANDW_INTMOD_INTMOD_SET_MSK 0x00000001
535 /* The mask used to clear the ALT_ECC_NANDW_INTMOD_INTMOD register field value. */
536 #define ALT_ECC_NANDW_INTMOD_INTMOD_CLR_MSK 0xfffffffe
537 /* The reset value of the ALT_ECC_NANDW_INTMOD_INTMOD register field. */
538 #define ALT_ECC_NANDW_INTMOD_INTMOD_RESET 0x0
539 /* Extracts the ALT_ECC_NANDW_INTMOD_INTMOD field value from a register. */
540 #define ALT_ECC_NANDW_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
541 /* Produces a ALT_ECC_NANDW_INTMOD_INTMOD register field value suitable for setting the register. */
542 #define ALT_ECC_NANDW_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
543 
544 /*
545  * Field : INTONOVF
546  *
547  * Enable interrupt on overflow.
548  *
549  * Field Access Macros:
550  *
551  */
552 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTMOD_INTONOVF register field. */
553 #define ALT_ECC_NANDW_INTMOD_INTONOVF_LSB 8
554 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTMOD_INTONOVF register field. */
555 #define ALT_ECC_NANDW_INTMOD_INTONOVF_MSB 8
556 /* The width in bits of the ALT_ECC_NANDW_INTMOD_INTONOVF register field. */
557 #define ALT_ECC_NANDW_INTMOD_INTONOVF_WIDTH 1
558 /* The mask used to set the ALT_ECC_NANDW_INTMOD_INTONOVF register field value. */
559 #define ALT_ECC_NANDW_INTMOD_INTONOVF_SET_MSK 0x00000100
560 /* The mask used to clear the ALT_ECC_NANDW_INTMOD_INTONOVF register field value. */
561 #define ALT_ECC_NANDW_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
562 /* The reset value of the ALT_ECC_NANDW_INTMOD_INTONOVF register field. */
563 #define ALT_ECC_NANDW_INTMOD_INTONOVF_RESET 0x0
564 /* Extracts the ALT_ECC_NANDW_INTMOD_INTONOVF field value from a register. */
565 #define ALT_ECC_NANDW_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
566 /* Produces a ALT_ECC_NANDW_INTMOD_INTONOVF register field value suitable for setting the register. */
567 #define ALT_ECC_NANDW_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
568 
569 /*
570  * Field : INTONCMP
571  *
572  * Enable interrupt on compare.
573  *
574  * Field Access Macros:
575  *
576  */
577 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTMOD_INTONCMP register field. */
578 #define ALT_ECC_NANDW_INTMOD_INTONCMP_LSB 16
579 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTMOD_INTONCMP register field. */
580 #define ALT_ECC_NANDW_INTMOD_INTONCMP_MSB 16
581 /* The width in bits of the ALT_ECC_NANDW_INTMOD_INTONCMP register field. */
582 #define ALT_ECC_NANDW_INTMOD_INTONCMP_WIDTH 1
583 /* The mask used to set the ALT_ECC_NANDW_INTMOD_INTONCMP register field value. */
584 #define ALT_ECC_NANDW_INTMOD_INTONCMP_SET_MSK 0x00010000
585 /* The mask used to clear the ALT_ECC_NANDW_INTMOD_INTONCMP register field value. */
586 #define ALT_ECC_NANDW_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
587 /* The reset value of the ALT_ECC_NANDW_INTMOD_INTONCMP register field. */
588 #define ALT_ECC_NANDW_INTMOD_INTONCMP_RESET 0x0
589 /* Extracts the ALT_ECC_NANDW_INTMOD_INTONCMP field value from a register. */
590 #define ALT_ECC_NANDW_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
591 /* Produces a ALT_ECC_NANDW_INTMOD_INTONCMP register field value suitable for setting the register. */
592 #define ALT_ECC_NANDW_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
593 
594 #ifndef __ASSEMBLY__
595 /*
596  * WARNING: The C register and register group struct declarations are provided for
597  * convenience and illustrative purposes. They should, however, be used with
598  * caution as the C language standard provides no guarantees about the alignment or
599  * atomicity of device memory accesses. The recommended practice for writing
600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
601  * alt_write_word() functions.
602  *
603  * The struct declaration for register ALT_ECC_NANDW_INTMOD.
604  */
605 struct ALT_ECC_NANDW_INTMOD_s
606 {
607  uint32_t INTMODE : 1; /* ALT_ECC_NANDW_INTMOD_INTMOD */
608  uint32_t : 7; /* *UNDEFINED* */
609  uint32_t INTONOVF : 1; /* ALT_ECC_NANDW_INTMOD_INTONOVF */
610  uint32_t : 7; /* *UNDEFINED* */
611  uint32_t INTONCMP : 1; /* ALT_ECC_NANDW_INTMOD_INTONCMP */
612  uint32_t : 15; /* *UNDEFINED* */
613 };
614 
615 /* The typedef declaration for register ALT_ECC_NANDW_INTMOD. */
616 typedef volatile struct ALT_ECC_NANDW_INTMOD_s ALT_ECC_NANDW_INTMOD_t;
617 #endif /* __ASSEMBLY__ */
618 
619 /* The reset value of the ALT_ECC_NANDW_INTMOD register. */
620 #define ALT_ECC_NANDW_INTMOD_RESET 0x00000000
621 /* The byte offset of the ALT_ECC_NANDW_INTMOD register from the beginning of the component. */
622 #define ALT_ECC_NANDW_INTMOD_OFST 0x1c
623 
624 /*
625  * Register : INTSTAT
626  *
627  * This bit is used to enable interrupt generation on SERR lookup table overflow.
628  * When all the entries in the table are valid=1 and this is bit is enabled,
629  * serr_req signal will be asserted.
630  *
631  * Register Layout
632  *
633  * Bits | Access | Reset | Description
634  * :-------|:-------|:------|:-------------------------------
635  * [0] | RW | 0x0 | ALT_ECC_NANDW_INTSTAT_SERRPENA
636  * [7:1] | ??? | 0x0 | *UNDEFINED*
637  * [8] | RW | 0x0 | ALT_ECC_NANDW_INTSTAT_DERRPENA
638  * [31:9] | ??? | 0x0 | *UNDEFINED*
639  *
640  */
641 /*
642  * Field : SERRPENA
643  *
644  * Single-bit error pending for PORTA.
645  *
646  * Field Access Macros:
647  *
648  */
649 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTSTAT_SERRPENA register field. */
650 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_LSB 0
651 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTSTAT_SERRPENA register field. */
652 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_MSB 0
653 /* The width in bits of the ALT_ECC_NANDW_INTSTAT_SERRPENA register field. */
654 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_WIDTH 1
655 /* The mask used to set the ALT_ECC_NANDW_INTSTAT_SERRPENA register field value. */
656 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_SET_MSK 0x00000001
657 /* The mask used to clear the ALT_ECC_NANDW_INTSTAT_SERRPENA register field value. */
658 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
659 /* The reset value of the ALT_ECC_NANDW_INTSTAT_SERRPENA register field. */
660 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_RESET 0x0
661 /* Extracts the ALT_ECC_NANDW_INTSTAT_SERRPENA field value from a register. */
662 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
663 /* Produces a ALT_ECC_NANDW_INTSTAT_SERRPENA register field value suitable for setting the register. */
664 #define ALT_ECC_NANDW_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
665 
666 /*
667  * Field : DERRPENA
668  *
669  * Double-bit error pending for PORTA.
670  *
671  * Field Access Macros:
672  *
673  */
674 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTSTAT_DERRPENA register field. */
675 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_LSB 8
676 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTSTAT_DERRPENA register field. */
677 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_MSB 8
678 /* The width in bits of the ALT_ECC_NANDW_INTSTAT_DERRPENA register field. */
679 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_WIDTH 1
680 /* The mask used to set the ALT_ECC_NANDW_INTSTAT_DERRPENA register field value. */
681 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_SET_MSK 0x00000100
682 /* The mask used to clear the ALT_ECC_NANDW_INTSTAT_DERRPENA register field value. */
683 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
684 /* The reset value of the ALT_ECC_NANDW_INTSTAT_DERRPENA register field. */
685 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_RESET 0x0
686 /* Extracts the ALT_ECC_NANDW_INTSTAT_DERRPENA field value from a register. */
687 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
688 /* Produces a ALT_ECC_NANDW_INTSTAT_DERRPENA register field value suitable for setting the register. */
689 #define ALT_ECC_NANDW_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
690 
691 #ifndef __ASSEMBLY__
692 /*
693  * WARNING: The C register and register group struct declarations are provided for
694  * convenience and illustrative purposes. They should, however, be used with
695  * caution as the C language standard provides no guarantees about the alignment or
696  * atomicity of device memory accesses. The recommended practice for writing
697  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
698  * alt_write_word() functions.
699  *
700  * The struct declaration for register ALT_ECC_NANDW_INTSTAT.
701  */
702 struct ALT_ECC_NANDW_INTSTAT_s
703 {
704  uint32_t SERRPENA : 1; /* ALT_ECC_NANDW_INTSTAT_SERRPENA */
705  uint32_t : 7; /* *UNDEFINED* */
706  uint32_t DERRPENA : 1; /* ALT_ECC_NANDW_INTSTAT_DERRPENA */
707  uint32_t : 23; /* *UNDEFINED* */
708 };
709 
710 /* The typedef declaration for register ALT_ECC_NANDW_INTSTAT. */
711 typedef volatile struct ALT_ECC_NANDW_INTSTAT_s ALT_ECC_NANDW_INTSTAT_t;
712 #endif /* __ASSEMBLY__ */
713 
714 /* The reset value of the ALT_ECC_NANDW_INTSTAT register. */
715 #define ALT_ECC_NANDW_INTSTAT_RESET 0x00000000
716 /* The byte offset of the ALT_ECC_NANDW_INTSTAT register from the beginning of the component. */
717 #define ALT_ECC_NANDW_INTSTAT_OFST 0x20
718 
719 /*
720  * Register : INTTEST
721  *
722  * This bits is used to test interrupt from ECC RAM to GIC
723  *
724  * Register Layout
725  *
726  * Bits | Access | Reset | Description
727  * :-------|:-------|:------|:-----------------------------
728  * [0] | RW | 0x0 | ALT_ECC_NANDW_INTTEST_TSERRA
729  * [7:1] | ??? | 0x0 | *UNDEFINED*
730  * [8] | RW | 0x0 | ALT_ECC_NANDW_INTTEST_TDERRA
731  * [31:9] | ??? | 0x0 | *UNDEFINED*
732  *
733  */
734 /*
735  * Field : TSERRA
736  *
737  * Test PORTA Single-bit error.
738  *
739  * Field Access Macros:
740  *
741  */
742 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTTEST_TSERRA register field. */
743 #define ALT_ECC_NANDW_INTTEST_TSERRA_LSB 0
744 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTTEST_TSERRA register field. */
745 #define ALT_ECC_NANDW_INTTEST_TSERRA_MSB 0
746 /* The width in bits of the ALT_ECC_NANDW_INTTEST_TSERRA register field. */
747 #define ALT_ECC_NANDW_INTTEST_TSERRA_WIDTH 1
748 /* The mask used to set the ALT_ECC_NANDW_INTTEST_TSERRA register field value. */
749 #define ALT_ECC_NANDW_INTTEST_TSERRA_SET_MSK 0x00000001
750 /* The mask used to clear the ALT_ECC_NANDW_INTTEST_TSERRA register field value. */
751 #define ALT_ECC_NANDW_INTTEST_TSERRA_CLR_MSK 0xfffffffe
752 /* The reset value of the ALT_ECC_NANDW_INTTEST_TSERRA register field. */
753 #define ALT_ECC_NANDW_INTTEST_TSERRA_RESET 0x0
754 /* Extracts the ALT_ECC_NANDW_INTTEST_TSERRA field value from a register. */
755 #define ALT_ECC_NANDW_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
756 /* Produces a ALT_ECC_NANDW_INTTEST_TSERRA register field value suitable for setting the register. */
757 #define ALT_ECC_NANDW_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
758 
759 /*
760  * Field : TDERRA
761  *
762  * Test PORTA Double-bit error.
763  *
764  * Field Access Macros:
765  *
766  */
767 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_INTTEST_TDERRA register field. */
768 #define ALT_ECC_NANDW_INTTEST_TDERRA_LSB 8
769 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_INTTEST_TDERRA register field. */
770 #define ALT_ECC_NANDW_INTTEST_TDERRA_MSB 8
771 /* The width in bits of the ALT_ECC_NANDW_INTTEST_TDERRA register field. */
772 #define ALT_ECC_NANDW_INTTEST_TDERRA_WIDTH 1
773 /* The mask used to set the ALT_ECC_NANDW_INTTEST_TDERRA register field value. */
774 #define ALT_ECC_NANDW_INTTEST_TDERRA_SET_MSK 0x00000100
775 /* The mask used to clear the ALT_ECC_NANDW_INTTEST_TDERRA register field value. */
776 #define ALT_ECC_NANDW_INTTEST_TDERRA_CLR_MSK 0xfffffeff
777 /* The reset value of the ALT_ECC_NANDW_INTTEST_TDERRA register field. */
778 #define ALT_ECC_NANDW_INTTEST_TDERRA_RESET 0x0
779 /* Extracts the ALT_ECC_NANDW_INTTEST_TDERRA field value from a register. */
780 #define ALT_ECC_NANDW_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
781 /* Produces a ALT_ECC_NANDW_INTTEST_TDERRA register field value suitable for setting the register. */
782 #define ALT_ECC_NANDW_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
783 
784 #ifndef __ASSEMBLY__
785 /*
786  * WARNING: The C register and register group struct declarations are provided for
787  * convenience and illustrative purposes. They should, however, be used with
788  * caution as the C language standard provides no guarantees about the alignment or
789  * atomicity of device memory accesses. The recommended practice for writing
790  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
791  * alt_write_word() functions.
792  *
793  * The struct declaration for register ALT_ECC_NANDW_INTTEST.
794  */
795 struct ALT_ECC_NANDW_INTTEST_s
796 {
797  uint32_t TSERRA : 1; /* ALT_ECC_NANDW_INTTEST_TSERRA */
798  uint32_t : 7; /* *UNDEFINED* */
799  uint32_t TDERRA : 1; /* ALT_ECC_NANDW_INTTEST_TDERRA */
800  uint32_t : 23; /* *UNDEFINED* */
801 };
802 
803 /* The typedef declaration for register ALT_ECC_NANDW_INTTEST. */
804 typedef volatile struct ALT_ECC_NANDW_INTTEST_s ALT_ECC_NANDW_INTTEST_t;
805 #endif /* __ASSEMBLY__ */
806 
807 /* The reset value of the ALT_ECC_NANDW_INTTEST register. */
808 #define ALT_ECC_NANDW_INTTEST_RESET 0x00000000
809 /* The byte offset of the ALT_ECC_NANDW_INTTEST register from the beginning of the component. */
810 #define ALT_ECC_NANDW_INTTEST_OFST 0x24
811 
812 /*
813  * Register : MODSTAT
814  *
815  * Counter feature status flag
816  *
817  * Register Layout
818  *
819  * Bits | Access | Reset | Description
820  * :-------|:-------|:------|:------------------------------
821  * [0] | RW | 0x0 | ALT_ECC_NANDW_MODSTAT_CMPFLGA
822  * [31:1] | ??? | 0x0 | *UNDEFINED*
823  *
824  */
825 /*
826  * Field : CMPFLGA
827  *
828  * Port A compare status flag
829  *
830  * Field Access Macros:
831  *
832  */
833 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field. */
834 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_LSB 0
835 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field. */
836 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_MSB 0
837 /* The width in bits of the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field. */
838 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_WIDTH 1
839 /* The mask used to set the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field value. */
840 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_SET_MSK 0x00000001
841 /* The mask used to clear the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field value. */
842 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
843 /* The reset value of the ALT_ECC_NANDW_MODSTAT_CMPFLGA register field. */
844 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_RESET 0x0
845 /* Extracts the ALT_ECC_NANDW_MODSTAT_CMPFLGA field value from a register. */
846 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
847 /* Produces a ALT_ECC_NANDW_MODSTAT_CMPFLGA register field value suitable for setting the register. */
848 #define ALT_ECC_NANDW_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
849 
850 #ifndef __ASSEMBLY__
851 /*
852  * WARNING: The C register and register group struct declarations are provided for
853  * convenience and illustrative purposes. They should, however, be used with
854  * caution as the C language standard provides no guarantees about the alignment or
855  * atomicity of device memory accesses. The recommended practice for writing
856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
857  * alt_write_word() functions.
858  *
859  * The struct declaration for register ALT_ECC_NANDW_MODSTAT.
860  */
861 struct ALT_ECC_NANDW_MODSTAT_s
862 {
863  uint32_t CMPFLGA : 1; /* ALT_ECC_NANDW_MODSTAT_CMPFLGA */
864  uint32_t : 31; /* *UNDEFINED* */
865 };
866 
867 /* The typedef declaration for register ALT_ECC_NANDW_MODSTAT. */
868 typedef volatile struct ALT_ECC_NANDW_MODSTAT_s ALT_ECC_NANDW_MODSTAT_t;
869 #endif /* __ASSEMBLY__ */
870 
871 /* The reset value of the ALT_ECC_NANDW_MODSTAT register. */
872 #define ALT_ECC_NANDW_MODSTAT_RESET 0x00000000
873 /* The byte offset of the ALT_ECC_NANDW_MODSTAT register from the beginning of the component. */
874 #define ALT_ECC_NANDW_MODSTAT_OFST 0x28
875 
876 /*
877  * Register : DERRADDRA
878  *
879  * This register shows the address of PORTA current double-bit error. RAM size will
880  * determine the maximum number of address bits.
881  *
882  * Register Layout
883  *
884  * Bits | Access | Reset | Description
885  * :-------|:-------|:------|:-----------------------------
886  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_DERRADDRA_ADDR
887  * [31:7] | ??? | 0x0 | *UNDEFINED*
888  *
889  */
890 /*
891  * Field : Address
892  *
893  * Recent double-bit error address.
894  *
895  * Field Access Macros:
896  *
897  */
898 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_DERRADDRA_ADDR register field. */
899 #define ALT_ECC_NANDW_DERRADDRA_ADDR_LSB 0
900 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_DERRADDRA_ADDR register field. */
901 #define ALT_ECC_NANDW_DERRADDRA_ADDR_MSB 6
902 /* The width in bits of the ALT_ECC_NANDW_DERRADDRA_ADDR register field. */
903 #define ALT_ECC_NANDW_DERRADDRA_ADDR_WIDTH 7
904 /* The mask used to set the ALT_ECC_NANDW_DERRADDRA_ADDR register field value. */
905 #define ALT_ECC_NANDW_DERRADDRA_ADDR_SET_MSK 0x0000007f
906 /* The mask used to clear the ALT_ECC_NANDW_DERRADDRA_ADDR register field value. */
907 #define ALT_ECC_NANDW_DERRADDRA_ADDR_CLR_MSK 0xffffff80
908 /* The reset value of the ALT_ECC_NANDW_DERRADDRA_ADDR register field. */
909 #define ALT_ECC_NANDW_DERRADDRA_ADDR_RESET 0x0
910 /* Extracts the ALT_ECC_NANDW_DERRADDRA_ADDR field value from a register. */
911 #define ALT_ECC_NANDW_DERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
912 /* Produces a ALT_ECC_NANDW_DERRADDRA_ADDR register field value suitable for setting the register. */
913 #define ALT_ECC_NANDW_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
914 
915 #ifndef __ASSEMBLY__
916 /*
917  * WARNING: The C register and register group struct declarations are provided for
918  * convenience and illustrative purposes. They should, however, be used with
919  * caution as the C language standard provides no guarantees about the alignment or
920  * atomicity of device memory accesses. The recommended practice for writing
921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
922  * alt_write_word() functions.
923  *
924  * The struct declaration for register ALT_ECC_NANDW_DERRADDRA.
925  */
926 struct ALT_ECC_NANDW_DERRADDRA_s
927 {
928  uint32_t Address : 7; /* ALT_ECC_NANDW_DERRADDRA_ADDR */
929  uint32_t : 25; /* *UNDEFINED* */
930 };
931 
932 /* The typedef declaration for register ALT_ECC_NANDW_DERRADDRA. */
933 typedef volatile struct ALT_ECC_NANDW_DERRADDRA_s ALT_ECC_NANDW_DERRADDRA_t;
934 #endif /* __ASSEMBLY__ */
935 
936 /* The reset value of the ALT_ECC_NANDW_DERRADDRA register. */
937 #define ALT_ECC_NANDW_DERRADDRA_RESET 0x00000000
938 /* The byte offset of the ALT_ECC_NANDW_DERRADDRA register from the beginning of the component. */
939 #define ALT_ECC_NANDW_DERRADDRA_OFST 0x2c
940 
941 /*
942  * Register : SERRADDRA
943  *
944  * This register shows the address of PORTA current single-bit error. RAM size will
945  * determine the maximum number of address bits.
946  *
947  * Register Layout
948  *
949  * Bits | Access | Reset | Description
950  * :-------|:-------|:------|:-----------------------------
951  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_SERRADDRA_ADDR
952  * [31:7] | ??? | 0x0 | *UNDEFINED*
953  *
954  */
955 /*
956  * Field : Address
957  *
958  * Recent single-bit error address.
959  *
960  * Field Access Macros:
961  *
962  */
963 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_SERRADDRA_ADDR register field. */
964 #define ALT_ECC_NANDW_SERRADDRA_ADDR_LSB 0
965 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_SERRADDRA_ADDR register field. */
966 #define ALT_ECC_NANDW_SERRADDRA_ADDR_MSB 6
967 /* The width in bits of the ALT_ECC_NANDW_SERRADDRA_ADDR register field. */
968 #define ALT_ECC_NANDW_SERRADDRA_ADDR_WIDTH 7
969 /* The mask used to set the ALT_ECC_NANDW_SERRADDRA_ADDR register field value. */
970 #define ALT_ECC_NANDW_SERRADDRA_ADDR_SET_MSK 0x0000007f
971 /* The mask used to clear the ALT_ECC_NANDW_SERRADDRA_ADDR register field value. */
972 #define ALT_ECC_NANDW_SERRADDRA_ADDR_CLR_MSK 0xffffff80
973 /* The reset value of the ALT_ECC_NANDW_SERRADDRA_ADDR register field. */
974 #define ALT_ECC_NANDW_SERRADDRA_ADDR_RESET 0x0
975 /* Extracts the ALT_ECC_NANDW_SERRADDRA_ADDR field value from a register. */
976 #define ALT_ECC_NANDW_SERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
977 /* Produces a ALT_ECC_NANDW_SERRADDRA_ADDR register field value suitable for setting the register. */
978 #define ALT_ECC_NANDW_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
979 
980 #ifndef __ASSEMBLY__
981 /*
982  * WARNING: The C register and register group struct declarations are provided for
983  * convenience and illustrative purposes. They should, however, be used with
984  * caution as the C language standard provides no guarantees about the alignment or
985  * atomicity of device memory accesses. The recommended practice for writing
986  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
987  * alt_write_word() functions.
988  *
989  * The struct declaration for register ALT_ECC_NANDW_SERRADDRA.
990  */
991 struct ALT_ECC_NANDW_SERRADDRA_s
992 {
993  uint32_t Address : 7; /* ALT_ECC_NANDW_SERRADDRA_ADDR */
994  uint32_t : 25; /* *UNDEFINED* */
995 };
996 
997 /* The typedef declaration for register ALT_ECC_NANDW_SERRADDRA. */
998 typedef volatile struct ALT_ECC_NANDW_SERRADDRA_s ALT_ECC_NANDW_SERRADDRA_t;
999 #endif /* __ASSEMBLY__ */
1000 
1001 /* The reset value of the ALT_ECC_NANDW_SERRADDRA register. */
1002 #define ALT_ECC_NANDW_SERRADDRA_RESET 0x00000000
1003 /* The byte offset of the ALT_ECC_NANDW_SERRADDRA register from the beginning of the component. */
1004 #define ALT_ECC_NANDW_SERRADDRA_OFST 0x30
1005 
1006 /*
1007  * Register : SERRCNTREG
1008  *
1009  * Maximum counter value for single-bit error interrupt
1010  *
1011  * Register Layout
1012  *
1013  * Bits | Access | Reset | Description
1014  * :-------|:-------|:------|:---------------------------------
1015  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_SERRCNTREG_SERRCNT
1016  *
1017  */
1018 /*
1019  * Field : SERRCNT
1020  *
1021  * Counter value
1022  *
1023  * Field Access Macros:
1024  *
1025  */
1026 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field. */
1027 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_LSB 0
1028 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field. */
1029 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_MSB 31
1030 /* The width in bits of the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field. */
1031 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_WIDTH 32
1032 /* The mask used to set the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field value. */
1033 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1034 /* The mask used to clear the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field value. */
1035 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1036 /* The reset value of the ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field. */
1037 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_RESET 0x0
1038 /* Extracts the ALT_ECC_NANDW_SERRCNTREG_SERRCNT field value from a register. */
1039 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1040 /* Produces a ALT_ECC_NANDW_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
1041 #define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1042 
1043 #ifndef __ASSEMBLY__
1044 /*
1045  * WARNING: The C register and register group struct declarations are provided for
1046  * convenience and illustrative purposes. They should, however, be used with
1047  * caution as the C language standard provides no guarantees about the alignment or
1048  * atomicity of device memory accesses. The recommended practice for writing
1049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1050  * alt_write_word() functions.
1051  *
1052  * The struct declaration for register ALT_ECC_NANDW_SERRCNTREG.
1053  */
1054 struct ALT_ECC_NANDW_SERRCNTREG_s
1055 {
1056  uint32_t SERRCNT : 32; /* ALT_ECC_NANDW_SERRCNTREG_SERRCNT */
1057 };
1058 
1059 /* The typedef declaration for register ALT_ECC_NANDW_SERRCNTREG. */
1060 typedef volatile struct ALT_ECC_NANDW_SERRCNTREG_s ALT_ECC_NANDW_SERRCNTREG_t;
1061 #endif /* __ASSEMBLY__ */
1062 
1063 /* The reset value of the ALT_ECC_NANDW_SERRCNTREG register. */
1064 #define ALT_ECC_NANDW_SERRCNTREG_RESET 0x00000000
1065 /* The byte offset of the ALT_ECC_NANDW_SERRCNTREG register from the beginning of the component. */
1066 #define ALT_ECC_NANDW_SERRCNTREG_OFST 0x3c
1067 
1068 /*
1069  * Register : ECC_Addrbus
1070  *
1071  * MSB bit of address is determined by ADR.
1072  *
1073  * Register Layout
1074  *
1075  * Bits | Access | Reset | Description
1076  * :-------|:-------|:------|:----------------------------------
1077  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS
1078  * [31:7] | ??? | 0x0 | *UNDEFINED*
1079  *
1080  */
1081 /*
1082  * Field : ECC_AddrBUS
1083  *
1084  * Address will be driven to RAM to either read or write the data. Address will be
1085  * latched by the RAM when the Enbus is asserted.
1086  *
1087  * Field Access Macros:
1088  *
1089  */
1090 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field. */
1091 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_LSB 0
1092 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field. */
1093 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_MSB 6
1094 /* The width in bits of the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field. */
1095 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_WIDTH 7
1096 /* The mask used to set the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field value. */
1097 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x0000007f
1098 /* The mask used to clear the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field value. */
1099 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffffff80
1100 /* The reset value of the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field. */
1101 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1102 /* Extracts the ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS field value from a register. */
1103 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x0000007f) >> 0)
1104 /* Produces a ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS register field value suitable for setting the register. */
1105 #define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x0000007f)
1106 
1107 #ifndef __ASSEMBLY__
1108 /*
1109  * WARNING: The C register and register group struct declarations are provided for
1110  * convenience and illustrative purposes. They should, however, be used with
1111  * caution as the C language standard provides no guarantees about the alignment or
1112  * atomicity of device memory accesses. The recommended practice for writing
1113  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1114  * alt_write_word() functions.
1115  *
1116  * The struct declaration for register ALT_ECC_NANDW_ADDRBUS.
1117  */
1118 struct ALT_ECC_NANDW_ADDRBUS_s
1119 {
1120  uint32_t ECC_AddrBUS : 7; /* ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS */
1121  uint32_t : 25; /* *UNDEFINED* */
1122 };
1123 
1124 /* The typedef declaration for register ALT_ECC_NANDW_ADDRBUS. */
1125 typedef volatile struct ALT_ECC_NANDW_ADDRBUS_s ALT_ECC_NANDW_ADDRBUS_t;
1126 #endif /* __ASSEMBLY__ */
1127 
1128 /* The reset value of the ALT_ECC_NANDW_ADDRBUS register. */
1129 #define ALT_ECC_NANDW_ADDRBUS_RESET 0x00000000
1130 /* The byte offset of the ALT_ECC_NANDW_ADDRBUS register from the beginning of the component. */
1131 #define ALT_ECC_NANDW_ADDRBUS_OFST 0x40
1132 /* The address of the ALT_ECC_NANDW_ADDRBUS register. */
1133 #define ALT_ECC_NANDW_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_ADDRBUS_OFST))
1134 
1135 /*
1136  * Register : ECC_RData0bus
1137  *
1138  * Data will be read to this register field.
1139  *
1140  * Register Layout
1141  *
1142  * Bits | Access | Reset | Description
1143  * :-------|:-------|:------|:-------------------------------------
1144  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS
1145  *
1146  */
1147 /*
1148  * Field : ECC_RDataBUS
1149  *
1150  * ECC_RDataBUS[31:0].
1151  *
1152  * Field Access Macros:
1153  *
1154  */
1155 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field. */
1156 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_LSB 0
1157 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field. */
1158 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_MSB 31
1159 /* The width in bits of the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field. */
1160 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1161 /* The mask used to set the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field value. */
1162 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1163 /* The mask used to clear the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field value. */
1164 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1165 /* The reset value of the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field. */
1166 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1167 /* Extracts the ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS field value from a register. */
1168 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1169 /* Produces a ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS register field value suitable for setting the register. */
1170 #define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1171 
1172 #ifndef __ASSEMBLY__
1173 /*
1174  * WARNING: The C register and register group struct declarations are provided for
1175  * convenience and illustrative purposes. They should, however, be used with
1176  * caution as the C language standard provides no guarantees about the alignment or
1177  * atomicity of device memory accesses. The recommended practice for writing
1178  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1179  * alt_write_word() functions.
1180  *
1181  * The struct declaration for register ALT_ECC_NANDW_RDATA0BUS.
1182  */
1183 struct ALT_ECC_NANDW_RDATA0BUS_s
1184 {
1185  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS */
1186 };
1187 
1188 /* The typedef declaration for register ALT_ECC_NANDW_RDATA0BUS. */
1189 typedef volatile struct ALT_ECC_NANDW_RDATA0BUS_s ALT_ECC_NANDW_RDATA0BUS_t;
1190 #endif /* __ASSEMBLY__ */
1191 
1192 /* The reset value of the ALT_ECC_NANDW_RDATA0BUS register. */
1193 #define ALT_ECC_NANDW_RDATA0BUS_RESET 0x00000000
1194 /* The byte offset of the ALT_ECC_NANDW_RDATA0BUS register from the beginning of the component. */
1195 #define ALT_ECC_NANDW_RDATA0BUS_OFST 0x44
1196 /* The address of the ALT_ECC_NANDW_RDATA0BUS register. */
1197 #define ALT_ECC_NANDW_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA0BUS_OFST))
1198 
1199 /*
1200  * Register : ECC_RData1bus
1201  *
1202  * Data will be read to this register field.
1203  *
1204  * Register Layout
1205  *
1206  * Bits | Access | Reset | Description
1207  * :-------|:-------|:------|:-------------------------------------
1208  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS
1209  *
1210  */
1211 /*
1212  * Field : ECC_RDataBUS
1213  *
1214  * ECC_RDataBUS[63:32].
1215  *
1216  * Field Access Macros:
1217  *
1218  */
1219 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field. */
1220 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_LSB 0
1221 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field. */
1222 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_MSB 31
1223 /* The width in bits of the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field. */
1224 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1225 /* The mask used to set the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field value. */
1226 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1227 /* The mask used to clear the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field value. */
1228 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1229 /* The reset value of the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field. */
1230 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1231 /* Extracts the ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS field value from a register. */
1232 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1233 /* Produces a ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS register field value suitable for setting the register. */
1234 #define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1235 
1236 #ifndef __ASSEMBLY__
1237 /*
1238  * WARNING: The C register and register group struct declarations are provided for
1239  * convenience and illustrative purposes. They should, however, be used with
1240  * caution as the C language standard provides no guarantees about the alignment or
1241  * atomicity of device memory accesses. The recommended practice for writing
1242  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1243  * alt_write_word() functions.
1244  *
1245  * The struct declaration for register ALT_ECC_NANDW_RDATA1BUS.
1246  */
1247 struct ALT_ECC_NANDW_RDATA1BUS_s
1248 {
1249  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS */
1250 };
1251 
1252 /* The typedef declaration for register ALT_ECC_NANDW_RDATA1BUS. */
1253 typedef volatile struct ALT_ECC_NANDW_RDATA1BUS_s ALT_ECC_NANDW_RDATA1BUS_t;
1254 #endif /* __ASSEMBLY__ */
1255 
1256 /* The reset value of the ALT_ECC_NANDW_RDATA1BUS register. */
1257 #define ALT_ECC_NANDW_RDATA1BUS_RESET 0x00000000
1258 /* The byte offset of the ALT_ECC_NANDW_RDATA1BUS register from the beginning of the component. */
1259 #define ALT_ECC_NANDW_RDATA1BUS_OFST 0x48
1260 /* The address of the ALT_ECC_NANDW_RDATA1BUS register. */
1261 #define ALT_ECC_NANDW_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA1BUS_OFST))
1262 
1263 /*
1264  * Register : ECC_RData2bus
1265  *
1266  * Data will be read to this register field.
1267  *
1268  * Register Layout
1269  *
1270  * Bits | Access | Reset | Description
1271  * :-------|:-------|:------|:-------------------------------------
1272  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS
1273  *
1274  */
1275 /*
1276  * Field : ECC_RDataBUS
1277  *
1278  * ECC_RDataBUS[95:64].
1279  *
1280  * Field Access Macros:
1281  *
1282  */
1283 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field. */
1284 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_LSB 0
1285 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field. */
1286 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_MSB 31
1287 /* The width in bits of the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field. */
1288 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1289 /* The mask used to set the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field value. */
1290 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1291 /* The mask used to clear the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field value. */
1292 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1293 /* The reset value of the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field. */
1294 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1295 /* Extracts the ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS field value from a register. */
1296 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1297 /* Produces a ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS register field value suitable for setting the register. */
1298 #define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1299 
1300 #ifndef __ASSEMBLY__
1301 /*
1302  * WARNING: The C register and register group struct declarations are provided for
1303  * convenience and illustrative purposes. They should, however, be used with
1304  * caution as the C language standard provides no guarantees about the alignment or
1305  * atomicity of device memory accesses. The recommended practice for writing
1306  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1307  * alt_write_word() functions.
1308  *
1309  * The struct declaration for register ALT_ECC_NANDW_RDATA2BUS.
1310  */
1311 struct ALT_ECC_NANDW_RDATA2BUS_s
1312 {
1313  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS */
1314 };
1315 
1316 /* The typedef declaration for register ALT_ECC_NANDW_RDATA2BUS. */
1317 typedef volatile struct ALT_ECC_NANDW_RDATA2BUS_s ALT_ECC_NANDW_RDATA2BUS_t;
1318 #endif /* __ASSEMBLY__ */
1319 
1320 /* The reset value of the ALT_ECC_NANDW_RDATA2BUS register. */
1321 #define ALT_ECC_NANDW_RDATA2BUS_RESET 0x00000000
1322 /* The byte offset of the ALT_ECC_NANDW_RDATA2BUS register from the beginning of the component. */
1323 #define ALT_ECC_NANDW_RDATA2BUS_OFST 0x4c
1324 /* The address of the ALT_ECC_NANDW_RDATA2BUS register. */
1325 #define ALT_ECC_NANDW_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA2BUS_OFST))
1326 
1327 /*
1328  * Register : ECC_RData3bus
1329  *
1330  * Data will be read to this register field.
1331  *
1332  * Register Layout
1333  *
1334  * Bits | Access | Reset | Description
1335  * :-------|:-------|:------|:-------------------------------------
1336  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS
1337  *
1338  */
1339 /*
1340  * Field : ECC_RDataBUS
1341  *
1342  * ECC_RDataBUS[127-96].
1343  *
1344  * Field Access Macros:
1345  *
1346  */
1347 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field. */
1348 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_LSB 0
1349 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field. */
1350 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_MSB 31
1351 /* The width in bits of the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field. */
1352 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1353 /* The mask used to set the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field value. */
1354 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1355 /* The mask used to clear the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field value. */
1356 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1357 /* The reset value of the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field. */
1358 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1359 /* Extracts the ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS field value from a register. */
1360 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1361 /* Produces a ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS register field value suitable for setting the register. */
1362 #define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1363 
1364 #ifndef __ASSEMBLY__
1365 /*
1366  * WARNING: The C register and register group struct declarations are provided for
1367  * convenience and illustrative purposes. They should, however, be used with
1368  * caution as the C language standard provides no guarantees about the alignment or
1369  * atomicity of device memory accesses. The recommended practice for writing
1370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1371  * alt_write_word() functions.
1372  *
1373  * The struct declaration for register ALT_ECC_NANDW_RDATA3BUS.
1374  */
1375 struct ALT_ECC_NANDW_RDATA3BUS_s
1376 {
1377  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS */
1378 };
1379 
1380 /* The typedef declaration for register ALT_ECC_NANDW_RDATA3BUS. */
1381 typedef volatile struct ALT_ECC_NANDW_RDATA3BUS_s ALT_ECC_NANDW_RDATA3BUS_t;
1382 #endif /* __ASSEMBLY__ */
1383 
1384 /* The reset value of the ALT_ECC_NANDW_RDATA3BUS register. */
1385 #define ALT_ECC_NANDW_RDATA3BUS_RESET 0x00000000
1386 /* The byte offset of the ALT_ECC_NANDW_RDATA3BUS register from the beginning of the component. */
1387 #define ALT_ECC_NANDW_RDATA3BUS_OFST 0x50
1388 /* The address of the ALT_ECC_NANDW_RDATA3BUS register. */
1389 #define ALT_ECC_NANDW_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA3BUS_OFST))
1390 
1391 /*
1392  * Register : ECC_WData0bus
1393  *
1394  * Data from the register will be written to the RAM.
1395  *
1396  * Register Layout
1397  *
1398  * Bits | Access | Reset | Description
1399  * :-------|:-------|:------|:-------------------------------------
1400  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS
1401  *
1402  */
1403 /*
1404  * Field : ECC_WDataBUS
1405  *
1406  * ECC_WDataBUS[31:0].
1407  *
1408  * Field Access Macros:
1409  *
1410  */
1411 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field. */
1412 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_LSB 0
1413 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field. */
1414 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_MSB 31
1415 /* The width in bits of the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field. */
1416 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1417 /* The mask used to set the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field value. */
1418 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1419 /* The mask used to clear the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field value. */
1420 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1421 /* The reset value of the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field. */
1422 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1423 /* Extracts the ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS field value from a register. */
1424 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1425 /* Produces a ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS register field value suitable for setting the register. */
1426 #define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1427 
1428 #ifndef __ASSEMBLY__
1429 /*
1430  * WARNING: The C register and register group struct declarations are provided for
1431  * convenience and illustrative purposes. They should, however, be used with
1432  * caution as the C language standard provides no guarantees about the alignment or
1433  * atomicity of device memory accesses. The recommended practice for writing
1434  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1435  * alt_write_word() functions.
1436  *
1437  * The struct declaration for register ALT_ECC_NANDW_WDATA0BUS.
1438  */
1439 struct ALT_ECC_NANDW_WDATA0BUS_s
1440 {
1441  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS */
1442 };
1443 
1444 /* The typedef declaration for register ALT_ECC_NANDW_WDATA0BUS. */
1445 typedef volatile struct ALT_ECC_NANDW_WDATA0BUS_s ALT_ECC_NANDW_WDATA0BUS_t;
1446 #endif /* __ASSEMBLY__ */
1447 
1448 /* The reset value of the ALT_ECC_NANDW_WDATA0BUS register. */
1449 #define ALT_ECC_NANDW_WDATA0BUS_RESET 0x00000000
1450 /* The byte offset of the ALT_ECC_NANDW_WDATA0BUS register from the beginning of the component. */
1451 #define ALT_ECC_NANDW_WDATA0BUS_OFST 0x54
1452 /* The address of the ALT_ECC_NANDW_WDATA0BUS register. */
1453 #define ALT_ECC_NANDW_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA0BUS_OFST))
1454 
1455 /*
1456  * Register : ECC_WData1bus
1457  *
1458  * Data from the register will be written to the RAM.
1459  *
1460  * Register Layout
1461  *
1462  * Bits | Access | Reset | Description
1463  * :-------|:-------|:------|:-------------------------------------
1464  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS
1465  *
1466  */
1467 /*
1468  * Field : ECC_WDataBUS
1469  *
1470  * ECC_WDataBUS[63:32].
1471  *
1472  * Field Access Macros:
1473  *
1474  */
1475 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field. */
1476 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_LSB 0
1477 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field. */
1478 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_MSB 31
1479 /* The width in bits of the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field. */
1480 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1481 /* The mask used to set the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field value. */
1482 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1483 /* The mask used to clear the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field value. */
1484 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1485 /* The reset value of the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field. */
1486 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1487 /* Extracts the ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS field value from a register. */
1488 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1489 /* Produces a ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS register field value suitable for setting the register. */
1490 #define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1491 
1492 #ifndef __ASSEMBLY__
1493 /*
1494  * WARNING: The C register and register group struct declarations are provided for
1495  * convenience and illustrative purposes. They should, however, be used with
1496  * caution as the C language standard provides no guarantees about the alignment or
1497  * atomicity of device memory accesses. The recommended practice for writing
1498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1499  * alt_write_word() functions.
1500  *
1501  * The struct declaration for register ALT_ECC_NANDW_WDATA1BUS.
1502  */
1503 struct ALT_ECC_NANDW_WDATA1BUS_s
1504 {
1505  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS */
1506 };
1507 
1508 /* The typedef declaration for register ALT_ECC_NANDW_WDATA1BUS. */
1509 typedef volatile struct ALT_ECC_NANDW_WDATA1BUS_s ALT_ECC_NANDW_WDATA1BUS_t;
1510 #endif /* __ASSEMBLY__ */
1511 
1512 /* The reset value of the ALT_ECC_NANDW_WDATA1BUS register. */
1513 #define ALT_ECC_NANDW_WDATA1BUS_RESET 0x00000000
1514 /* The byte offset of the ALT_ECC_NANDW_WDATA1BUS register from the beginning of the component. */
1515 #define ALT_ECC_NANDW_WDATA1BUS_OFST 0x58
1516 /* The address of the ALT_ECC_NANDW_WDATA1BUS register. */
1517 #define ALT_ECC_NANDW_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA1BUS_OFST))
1518 
1519 /*
1520  * Register : ECC_WData2bus
1521  *
1522  * Data from the register will be written to the RAM.
1523  *
1524  * Register Layout
1525  *
1526  * Bits | Access | Reset | Description
1527  * :-------|:-------|:------|:-------------------------------------
1528  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS
1529  *
1530  */
1531 /*
1532  * Field : ECC_WDataBUS
1533  *
1534  * ECC_WDataBUS[95-64].
1535  *
1536  * Field Access Macros:
1537  *
1538  */
1539 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field. */
1540 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_LSB 0
1541 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field. */
1542 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_MSB 31
1543 /* The width in bits of the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field. */
1544 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1545 /* The mask used to set the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field value. */
1546 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1547 /* The mask used to clear the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field value. */
1548 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1549 /* The reset value of the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field. */
1550 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1551 /* Extracts the ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS field value from a register. */
1552 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1553 /* Produces a ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS register field value suitable for setting the register. */
1554 #define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1555 
1556 #ifndef __ASSEMBLY__
1557 /*
1558  * WARNING: The C register and register group struct declarations are provided for
1559  * convenience and illustrative purposes. They should, however, be used with
1560  * caution as the C language standard provides no guarantees about the alignment or
1561  * atomicity of device memory accesses. The recommended practice for writing
1562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1563  * alt_write_word() functions.
1564  *
1565  * The struct declaration for register ALT_ECC_NANDW_WDATA2BUS.
1566  */
1567 struct ALT_ECC_NANDW_WDATA2BUS_s
1568 {
1569  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS */
1570 };
1571 
1572 /* The typedef declaration for register ALT_ECC_NANDW_WDATA2BUS. */
1573 typedef volatile struct ALT_ECC_NANDW_WDATA2BUS_s ALT_ECC_NANDW_WDATA2BUS_t;
1574 #endif /* __ASSEMBLY__ */
1575 
1576 /* The reset value of the ALT_ECC_NANDW_WDATA2BUS register. */
1577 #define ALT_ECC_NANDW_WDATA2BUS_RESET 0x00000000
1578 /* The byte offset of the ALT_ECC_NANDW_WDATA2BUS register from the beginning of the component. */
1579 #define ALT_ECC_NANDW_WDATA2BUS_OFST 0x5c
1580 /* The address of the ALT_ECC_NANDW_WDATA2BUS register. */
1581 #define ALT_ECC_NANDW_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA2BUS_OFST))
1582 
1583 /*
1584  * Register : ECC_WData3bus
1585  *
1586  * Data from the register will be written to the RAM.
1587  *
1588  * Register Layout
1589  *
1590  * Bits | Access | Reset | Description
1591  * :-------|:-------|:------|:-------------------------------------
1592  * [31:0] | RW | 0x0 | ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS
1593  *
1594  */
1595 /*
1596  * Field : ECC_WDataBUS
1597  *
1598  * ECC_WDataBUS[127-96].
1599  *
1600  * Field Access Macros:
1601  *
1602  */
1603 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field. */
1604 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_LSB 0
1605 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field. */
1606 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_MSB 31
1607 /* The width in bits of the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field. */
1608 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1609 /* The mask used to set the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field value. */
1610 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1611 /* The mask used to clear the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field value. */
1612 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1613 /* The reset value of the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field. */
1614 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1615 /* Extracts the ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS field value from a register. */
1616 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1617 /* Produces a ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS register field value suitable for setting the register. */
1618 #define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1619 
1620 #ifndef __ASSEMBLY__
1621 /*
1622  * WARNING: The C register and register group struct declarations are provided for
1623  * convenience and illustrative purposes. They should, however, be used with
1624  * caution as the C language standard provides no guarantees about the alignment or
1625  * atomicity of device memory accesses. The recommended practice for writing
1626  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1627  * alt_write_word() functions.
1628  *
1629  * The struct declaration for register ALT_ECC_NANDW_WDATA3BUS.
1630  */
1631 struct ALT_ECC_NANDW_WDATA3BUS_s
1632 {
1633  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS */
1634 };
1635 
1636 /* The typedef declaration for register ALT_ECC_NANDW_WDATA3BUS. */
1637 typedef volatile struct ALT_ECC_NANDW_WDATA3BUS_s ALT_ECC_NANDW_WDATA3BUS_t;
1638 #endif /* __ASSEMBLY__ */
1639 
1640 /* The reset value of the ALT_ECC_NANDW_WDATA3BUS register. */
1641 #define ALT_ECC_NANDW_WDATA3BUS_RESET 0x00000000
1642 /* The byte offset of the ALT_ECC_NANDW_WDATA3BUS register from the beginning of the component. */
1643 #define ALT_ECC_NANDW_WDATA3BUS_OFST 0x60
1644 /* The address of the ALT_ECC_NANDW_WDATA3BUS register. */
1645 #define ALT_ECC_NANDW_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA3BUS_OFST))
1646 
1647 /*
1648  * Register : ECC_RDataecc0bus
1649  *
1650  * The msb bit for the register is configured based on DAT parameter (RAM word
1651  * size). Unimplemented bytes of this register will be reserved.
1652  *
1653  * Register Layout
1654  *
1655  * Bits | Access | Reset | Description
1656  * :--------|:-------|:------|:--------------------------------------------
1657  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS
1658  * [7] | ??? | 0x0 | *UNDEFINED*
1659  * [14:8] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS
1660  * [15] | ??? | 0x0 | *UNDEFINED*
1661  * [22:16] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS
1662  * [23] | ??? | 0x0 | *UNDEFINED*
1663  * [30:24] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS
1664  * [31] | ??? | 0x0 | *UNDEFINED*
1665  *
1666  */
1667 /*
1668  * Field : ECC_RDataecc0BUS
1669  *
1670  * Eccdata will be read to this register field.
1671  *
1672  * Field Access Macros:
1673  *
1674  */
1675 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1676 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1677 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1678 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1679 /* The width in bits of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1680 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1681 /* The mask used to set the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1682 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1683 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1684 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1685 /* The reset value of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1686 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1687 /* Extracts the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register. */
1688 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1689 /* Produces a ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register. */
1690 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1691 
1692 /*
1693  * Field : ECC_RDataecc1BUS
1694  *
1695  * Eccdata will be read to this register field.
1696  *
1697  * Field Access Macros:
1698  *
1699  */
1700 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1701 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1702 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1703 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1704 /* The width in bits of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1705 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1706 /* The mask used to set the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1707 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1708 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1709 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1710 /* The reset value of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1711 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1712 /* Extracts the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register. */
1713 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1714 /* Produces a ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register. */
1715 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1716 
1717 /*
1718  * Field : ECC_RDataecc2BUS
1719  *
1720  * Eccdata will be read to this register field.
1721  *
1722  * Field Access Macros:
1723  *
1724  */
1725 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1726 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1727 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1728 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1729 /* The width in bits of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1730 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1731 /* The mask used to set the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1732 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1733 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1734 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1735 /* The reset value of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1736 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1737 /* Extracts the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register. */
1738 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1739 /* Produces a ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register. */
1740 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1741 
1742 /*
1743  * Field : ECC_RDataecc3BUS
1744  *
1745  * Eccdata will be read to this register field.
1746  *
1747  * Field Access Macros:
1748  *
1749  */
1750 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1751 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1752 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1753 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1754 /* The width in bits of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1755 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1756 /* The mask used to set the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1757 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1758 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1759 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1760 /* The reset value of the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1761 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1762 /* Extracts the ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register. */
1763 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1764 /* Produces a ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register. */
1765 #define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1766 
1767 #ifndef __ASSEMBLY__
1768 /*
1769  * WARNING: The C register and register group struct declarations are provided for
1770  * convenience and illustrative purposes. They should, however, be used with
1771  * caution as the C language standard provides no guarantees about the alignment or
1772  * atomicity of device memory accesses. The recommended practice for writing
1773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1774  * alt_write_word() functions.
1775  *
1776  * The struct declaration for register ALT_ECC_NANDW_RDATAECC0BUS.
1777  */
1778 struct ALT_ECC_NANDW_RDATAECC0BUS_s
1779 {
1780  uint32_t ECC_RDataecc0BUS : 7; /* ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS */
1781  uint32_t : 1; /* *UNDEFINED* */
1782  uint32_t ECC_RDataecc1BUS : 7; /* ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS */
1783  uint32_t : 1; /* *UNDEFINED* */
1784  uint32_t ECC_RDataecc2BUS : 7; /* ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS */
1785  uint32_t : 1; /* *UNDEFINED* */
1786  uint32_t ECC_RDataecc3BUS : 7; /* ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS */
1787  uint32_t : 1; /* *UNDEFINED* */
1788 };
1789 
1790 /* The typedef declaration for register ALT_ECC_NANDW_RDATAECC0BUS. */
1791 typedef volatile struct ALT_ECC_NANDW_RDATAECC0BUS_s ALT_ECC_NANDW_RDATAECC0BUS_t;
1792 #endif /* __ASSEMBLY__ */
1793 
1794 /* The reset value of the ALT_ECC_NANDW_RDATAECC0BUS register. */
1795 #define ALT_ECC_NANDW_RDATAECC0BUS_RESET 0x00000000
1796 /* The byte offset of the ALT_ECC_NANDW_RDATAECC0BUS register from the beginning of the component. */
1797 #define ALT_ECC_NANDW_RDATAECC0BUS_OFST 0x64
1798 /* The address of the ALT_ECC_NANDW_RDATAECC0BUS register. */
1799 #define ALT_ECC_NANDW_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATAECC0BUS_OFST))
1800 
1801 /*
1802  * Register : ECC_RDataecc1bus
1803  *
1804  * The msb bit for the register is configured based on DAT parameter (RAM word
1805  * size). Unimplemented bytes of this register will be reserved.
1806  *
1807  * Register Layout
1808  *
1809  * Bits | Access | Reset | Description
1810  * :--------|:-------|:------|:--------------------------------------------
1811  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS
1812  * [7] | ??? | 0x0 | *UNDEFINED*
1813  * [14:8] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS
1814  * [15] | ??? | 0x0 | *UNDEFINED*
1815  * [22:16] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS
1816  * [23] | ??? | 0x0 | *UNDEFINED*
1817  * [30:24] | RW | 0x0 | ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS
1818  * [31] | ??? | 0x0 | *UNDEFINED*
1819  *
1820  */
1821 /*
1822  * Field : ECC_RDataecc4BUS
1823  *
1824  * Eccdata will be read to this register field.
1825  *
1826  * Field Access Macros:
1827  *
1828  */
1829 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1830 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1831 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1832 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1833 /* The width in bits of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1834 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1835 /* The mask used to set the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1836 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1837 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1838 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1839 /* The reset value of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1840 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1841 /* Extracts the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS field value from a register. */
1842 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1843 /* Produces a ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS register field value suitable for setting the register. */
1844 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1845 
1846 /*
1847  * Field : ECC_RDataecc5BUS
1848  *
1849  * Eccdata will be read to this register field.
1850  *
1851  * Field Access Macros:
1852  *
1853  */
1854 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1855 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1856 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1857 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1858 /* The width in bits of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1859 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1860 /* The mask used to set the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1861 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1862 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1863 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1864 /* The reset value of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1865 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1866 /* Extracts the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS field value from a register. */
1867 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1868 /* Produces a ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS register field value suitable for setting the register. */
1869 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1870 
1871 /*
1872  * Field : ECC_RDataecc6BUS
1873  *
1874  * Eccdata will be read to this register field.
1875  *
1876  * Field Access Macros:
1877  *
1878  */
1879 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1880 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1881 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1882 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1883 /* The width in bits of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1884 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1885 /* The mask used to set the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1886 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1887 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1888 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1889 /* The reset value of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1890 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1891 /* Extracts the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS field value from a register. */
1892 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1893 /* Produces a ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS register field value suitable for setting the register. */
1894 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1895 
1896 /*
1897  * Field : ECC_RDataecc7BUS
1898  *
1899  * Eccdata will be read to this register field.
1900  *
1901  * Field Access Macros:
1902  *
1903  */
1904 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1905 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1906 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1907 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1908 /* The width in bits of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1909 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1910 /* The mask used to set the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1911 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1912 /* The mask used to clear the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1913 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1914 /* The reset value of the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1915 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1916 /* Extracts the ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS field value from a register. */
1917 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1918 /* Produces a ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS register field value suitable for setting the register. */
1919 #define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1920 
1921 #ifndef __ASSEMBLY__
1922 /*
1923  * WARNING: The C register and register group struct declarations are provided for
1924  * convenience and illustrative purposes. They should, however, be used with
1925  * caution as the C language standard provides no guarantees about the alignment or
1926  * atomicity of device memory accesses. The recommended practice for writing
1927  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1928  * alt_write_word() functions.
1929  *
1930  * The struct declaration for register ALT_ECC_NANDW_RDATAECC1BUS.
1931  */
1932 struct ALT_ECC_NANDW_RDATAECC1BUS_s
1933 {
1934  uint32_t ECC_RDataecc4BUS : 7; /* ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS */
1935  uint32_t : 1; /* *UNDEFINED* */
1936  uint32_t ECC_RDataecc5BUS : 7; /* ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS */
1937  uint32_t : 1; /* *UNDEFINED* */
1938  uint32_t ECC_RDataecc6BUS : 7; /* ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS */
1939  uint32_t : 1; /* *UNDEFINED* */
1940  uint32_t ECC_RDataecc7BUS : 7; /* ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS */
1941  uint32_t : 1; /* *UNDEFINED* */
1942 };
1943 
1944 /* The typedef declaration for register ALT_ECC_NANDW_RDATAECC1BUS. */
1945 typedef volatile struct ALT_ECC_NANDW_RDATAECC1BUS_s ALT_ECC_NANDW_RDATAECC1BUS_t;
1946 #endif /* __ASSEMBLY__ */
1947 
1948 /* The reset value of the ALT_ECC_NANDW_RDATAECC1BUS register. */
1949 #define ALT_ECC_NANDW_RDATAECC1BUS_RESET 0x00000000
1950 /* The byte offset of the ALT_ECC_NANDW_RDATAECC1BUS register from the beginning of the component. */
1951 #define ALT_ECC_NANDW_RDATAECC1BUS_OFST 0x68
1952 /* The address of the ALT_ECC_NANDW_RDATAECC1BUS register. */
1953 #define ALT_ECC_NANDW_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATAECC1BUS_OFST))
1954 
1955 /*
1956  * Register : ECC_WDataecc0bus
1957  *
1958  * The msb bit for the register is configured based on DAT parameter (RAM word
1959  * size). Unimplemented bytes of this register will be reserved.
1960  *
1961  * Register Layout
1962  *
1963  * Bits | Access | Reset | Description
1964  * :--------|:-------|:------|:--------------------------------------------
1965  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS
1966  * [7] | ??? | 0x0 | *UNDEFINED*
1967  * [14:8] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS
1968  * [15] | ??? | 0x0 | *UNDEFINED*
1969  * [22:16] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS
1970  * [23] | ??? | 0x0 | *UNDEFINED*
1971  * [30:24] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS
1972  * [31] | ??? | 0x0 | *UNDEFINED*
1973  *
1974  */
1975 /*
1976  * Field : ECC_WDataecc0BUS
1977  *
1978  * Eccdata from the register will be written to the RAM.
1979  *
1980  * Field Access Macros:
1981  *
1982  */
1983 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1984 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1985 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1986 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1987 /* The width in bits of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1988 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1989 /* The mask used to set the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
1990 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1991 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
1992 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1993 /* The reset value of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1994 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1995 /* Extracts the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register. */
1996 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1997 /* Produces a ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register. */
1998 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1999 
2000 /*
2001  * Field : ECC_WDataecc1BUS
2002  *
2003  * Eccdata from the register will be written to the RAM.
2004  *
2005  * Field Access Macros:
2006  *
2007  */
2008 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2009 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2010 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2011 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2012 /* The width in bits of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2013 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2014 /* The mask used to set the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2015 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2016 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2017 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2018 /* The reset value of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2019 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2020 /* Extracts the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register. */
2021 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2022 /* Produces a ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register. */
2023 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2024 
2025 /*
2026  * Field : ECC_WDataecc2BUS
2027  *
2028  * Eccdata from the register will be written to the RAM.
2029  *
2030  * Field Access Macros:
2031  *
2032  */
2033 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2034 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2035 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2036 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2037 /* The width in bits of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2038 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2039 /* The mask used to set the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2040 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2041 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2042 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2043 /* The reset value of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2044 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2045 /* Extracts the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register. */
2046 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2047 /* Produces a ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register. */
2048 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2049 
2050 /*
2051  * Field : ECC_WDataecc3BUS
2052  *
2053  * Eccdata from the register will be written to the RAM.
2054  *
2055  * Field Access Macros:
2056  *
2057  */
2058 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2059 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2060 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2061 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2062 /* The width in bits of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2063 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2064 /* The mask used to set the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2065 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2066 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2067 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2068 /* The reset value of the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2069 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2070 /* Extracts the ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register. */
2071 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2072 /* Produces a ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register. */
2073 #define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2074 
2075 #ifndef __ASSEMBLY__
2076 /*
2077  * WARNING: The C register and register group struct declarations are provided for
2078  * convenience and illustrative purposes. They should, however, be used with
2079  * caution as the C language standard provides no guarantees about the alignment or
2080  * atomicity of device memory accesses. The recommended practice for writing
2081  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2082  * alt_write_word() functions.
2083  *
2084  * The struct declaration for register ALT_ECC_NANDW_WDATAECC0BUS.
2085  */
2086 struct ALT_ECC_NANDW_WDATAECC0BUS_s
2087 {
2088  uint32_t ECC_WDataecc0BUS : 7; /* ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS */
2089  uint32_t : 1; /* *UNDEFINED* */
2090  uint32_t ECC_WDataecc1BUS : 7; /* ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS */
2091  uint32_t : 1; /* *UNDEFINED* */
2092  uint32_t ECC_WDataecc2BUS : 7; /* ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS */
2093  uint32_t : 1; /* *UNDEFINED* */
2094  uint32_t ECC_WDataecc3BUS : 7; /* ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS */
2095  uint32_t : 1; /* *UNDEFINED* */
2096 };
2097 
2098 /* The typedef declaration for register ALT_ECC_NANDW_WDATAECC0BUS. */
2099 typedef volatile struct ALT_ECC_NANDW_WDATAECC0BUS_s ALT_ECC_NANDW_WDATAECC0BUS_t;
2100 #endif /* __ASSEMBLY__ */
2101 
2102 /* The reset value of the ALT_ECC_NANDW_WDATAECC0BUS register. */
2103 #define ALT_ECC_NANDW_WDATAECC0BUS_RESET 0x00000000
2104 /* The byte offset of the ALT_ECC_NANDW_WDATAECC0BUS register from the beginning of the component. */
2105 #define ALT_ECC_NANDW_WDATAECC0BUS_OFST 0x6c
2106 /* The address of the ALT_ECC_NANDW_WDATAECC0BUS register. */
2107 #define ALT_ECC_NANDW_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATAECC0BUS_OFST))
2108 
2109 /*
2110  * Register : ECC_WDataecc1bus
2111  *
2112  * The msb bit for the register is configured based on DAT parameter (RAM word
2113  * size). Unimplemented bytes of this register will be reserved.
2114  *
2115  * Register Layout
2116  *
2117  * Bits | Access | Reset | Description
2118  * :--------|:-------|:------|:--------------------------------------------
2119  * [6:0] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS
2120  * [7] | ??? | 0x0 | *UNDEFINED*
2121  * [14:8] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS
2122  * [15] | ??? | 0x0 | *UNDEFINED*
2123  * [22:16] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS
2124  * [23] | ??? | 0x0 | *UNDEFINED*
2125  * [30:24] | RW | 0x0 | ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS
2126  * [31] | ??? | 0x0 | *UNDEFINED*
2127  *
2128  */
2129 /*
2130  * Field : ECC_WDataecc4BUS
2131  *
2132  * Eccdata from the register will be written to the RAM.
2133  *
2134  * Field Access Macros:
2135  *
2136  */
2137 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2138 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2139 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2140 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2141 /* The width in bits of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2142 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2143 /* The mask used to set the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2144 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2145 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2146 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2147 /* The reset value of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2148 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2149 /* Extracts the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register. */
2150 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2151 /* Produces a ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register. */
2152 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2153 
2154 /*
2155  * Field : ECC_WDataecc5BUS
2156  *
2157  * Eccdata from the register will be written to the RAM.
2158  *
2159  * Field Access Macros:
2160  *
2161  */
2162 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2163 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2164 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2165 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2166 /* The width in bits of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2167 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2168 /* The mask used to set the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2169 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2170 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2171 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2172 /* The reset value of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2173 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2174 /* Extracts the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register. */
2175 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2176 /* Produces a ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register. */
2177 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2178 
2179 /*
2180  * Field : ECC_WDataecc6BUS
2181  *
2182  * Eccdata from the register will be written to the RAM.
2183  *
2184  * Field Access Macros:
2185  *
2186  */
2187 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2188 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2189 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2190 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2191 /* The width in bits of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2192 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2193 /* The mask used to set the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2194 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2195 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2196 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2197 /* The reset value of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2198 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2199 /* Extracts the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register. */
2200 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2201 /* Produces a ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register. */
2202 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2203 
2204 /*
2205  * Field : ECC_WDataecc7BUS
2206  *
2207  * Eccdata from the register will be written to the RAM.
2208  *
2209  * Field Access Macros:
2210  *
2211  */
2212 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2213 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2214 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2215 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2216 /* The width in bits of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2217 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2218 /* The mask used to set the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2219 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2220 /* The mask used to clear the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2221 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2222 /* The reset value of the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2223 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2224 /* Extracts the ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register. */
2225 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2226 /* Produces a ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register. */
2227 #define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2228 
2229 #ifndef __ASSEMBLY__
2230 /*
2231  * WARNING: The C register and register group struct declarations are provided for
2232  * convenience and illustrative purposes. They should, however, be used with
2233  * caution as the C language standard provides no guarantees about the alignment or
2234  * atomicity of device memory accesses. The recommended practice for writing
2235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2236  * alt_write_word() functions.
2237  *
2238  * The struct declaration for register ALT_ECC_NANDW_WDATAECC1BUS.
2239  */
2240 struct ALT_ECC_NANDW_WDATAECC1BUS_s
2241 {
2242  uint32_t ECC_WDataecc4BUS : 7; /* ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS */
2243  uint32_t : 1; /* *UNDEFINED* */
2244  uint32_t ECC_WDataecc5BUS : 7; /* ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS */
2245  uint32_t : 1; /* *UNDEFINED* */
2246  uint32_t ECC_WDataecc6BUS : 7; /* ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS */
2247  uint32_t : 1; /* *UNDEFINED* */
2248  uint32_t ECC_WDataecc7BUS : 7; /* ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS */
2249  uint32_t : 1; /* *UNDEFINED* */
2250 };
2251 
2252 /* The typedef declaration for register ALT_ECC_NANDW_WDATAECC1BUS. */
2253 typedef volatile struct ALT_ECC_NANDW_WDATAECC1BUS_s ALT_ECC_NANDW_WDATAECC1BUS_t;
2254 #endif /* __ASSEMBLY__ */
2255 
2256 /* The reset value of the ALT_ECC_NANDW_WDATAECC1BUS register. */
2257 #define ALT_ECC_NANDW_WDATAECC1BUS_RESET 0x00000000
2258 /* The byte offset of the ALT_ECC_NANDW_WDATAECC1BUS register from the beginning of the component. */
2259 #define ALT_ECC_NANDW_WDATAECC1BUS_OFST 0x70
2260 /* The address of the ALT_ECC_NANDW_WDATAECC1BUS register. */
2261 #define ALT_ECC_NANDW_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATAECC1BUS_OFST))
2262 
2263 /*
2264  * Register : ECC_dbytectrl
2265  *
2266  * Max number of implemented byte enabled is DAT/8
2267  *
2268  * Register Layout
2269  *
2270  * Bits | Access | Reset | Description
2271  * :-------|:-------|:------|:----------------------------
2272  * [0] | RW | 0x0 | ALT_ECC_NANDW_DBYTECTL_DBEN
2273  * [31:1] | ??? | 0x0 | *UNDEFINED*
2274  *
2275  */
2276 /*
2277  * Field : DBEN
2278  *
2279  * Byte or word enable for access.
2280  *
2281  * Field Access Macros:
2282  *
2283  */
2284 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_DBYTECTL_DBEN register field. */
2285 #define ALT_ECC_NANDW_DBYTECTL_DBEN_LSB 0
2286 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_DBYTECTL_DBEN register field. */
2287 #define ALT_ECC_NANDW_DBYTECTL_DBEN_MSB 0
2288 /* The width in bits of the ALT_ECC_NANDW_DBYTECTL_DBEN register field. */
2289 #define ALT_ECC_NANDW_DBYTECTL_DBEN_WIDTH 1
2290 /* The mask used to set the ALT_ECC_NANDW_DBYTECTL_DBEN register field value. */
2291 #define ALT_ECC_NANDW_DBYTECTL_DBEN_SET_MSK 0x00000001
2292 /* The mask used to clear the ALT_ECC_NANDW_DBYTECTL_DBEN register field value. */
2293 #define ALT_ECC_NANDW_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2294 /* The reset value of the ALT_ECC_NANDW_DBYTECTL_DBEN register field. */
2295 #define ALT_ECC_NANDW_DBYTECTL_DBEN_RESET 0x0
2296 /* Extracts the ALT_ECC_NANDW_DBYTECTL_DBEN field value from a register. */
2297 #define ALT_ECC_NANDW_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2298 /* Produces a ALT_ECC_NANDW_DBYTECTL_DBEN register field value suitable for setting the register. */
2299 #define ALT_ECC_NANDW_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2300 
2301 #ifndef __ASSEMBLY__
2302 /*
2303  * WARNING: The C register and register group struct declarations are provided for
2304  * convenience and illustrative purposes. They should, however, be used with
2305  * caution as the C language standard provides no guarantees about the alignment or
2306  * atomicity of device memory accesses. The recommended practice for writing
2307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2308  * alt_write_word() functions.
2309  *
2310  * The struct declaration for register ALT_ECC_NANDW_DBYTECTL.
2311  */
2312 struct ALT_ECC_NANDW_DBYTECTL_s
2313 {
2314  uint32_t DBEN : 1; /* ALT_ECC_NANDW_DBYTECTL_DBEN */
2315  uint32_t : 31; /* *UNDEFINED* */
2316 };
2317 
2318 /* The typedef declaration for register ALT_ECC_NANDW_DBYTECTL. */
2319 typedef volatile struct ALT_ECC_NANDW_DBYTECTL_s ALT_ECC_NANDW_DBYTECTL_t;
2320 #endif /* __ASSEMBLY__ */
2321 
2322 /* The reset value of the ALT_ECC_NANDW_DBYTECTL register. */
2323 #define ALT_ECC_NANDW_DBYTECTL_RESET 0x00000000
2324 /* The byte offset of the ALT_ECC_NANDW_DBYTECTL register from the beginning of the component. */
2325 #define ALT_ECC_NANDW_DBYTECTL_OFST 0x74
2326 /* The address of the ALT_ECC_NANDW_DBYTECTL register. */
2327 #define ALT_ECC_NANDW_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_DBYTECTL_OFST))
2328 
2329 /*
2330  * Register : ECC_accctrl
2331  *
2332  * These bits determine which byte of data/ecc to write to RAM.
2333  *
2334  * Register Layout
2335  *
2336  * Bits | Access | Reset | Description
2337  * :-------|:-------|:------|:-----------------------------
2338  * [0] | RW | 0x0 | ALT_ECC_NANDW_ACCCTL_DATAOVR
2339  * [1] | RW | 0x0 | ALT_ECC_NANDW_ACCCTL_ECCOVR
2340  * [7:2] | ??? | 0x0 | *UNDEFINED*
2341  * [8] | RW | 0x0 | ALT_ECC_NANDW_ACCCTL_RDWR
2342  * [31:9] | ??? | 0x0 | *UNDEFINED*
2343  *
2344  */
2345 /*
2346  * Field : DATAOVR
2347  *
2348  * RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode
2349  * set by ECC_RW.
2350  *
2351  * 1'b0: Data override disabled.
2352  *
2353  * 1'b1: Data override enabled.
2354  *
2355  * Field Access Macros:
2356  *
2357  */
2358 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ACCCTL_DATAOVR register field. */
2359 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_LSB 0
2360 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ACCCTL_DATAOVR register field. */
2361 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_MSB 0
2362 /* The width in bits of the ALT_ECC_NANDW_ACCCTL_DATAOVR register field. */
2363 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_WIDTH 1
2364 /* The mask used to set the ALT_ECC_NANDW_ACCCTL_DATAOVR register field value. */
2365 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_SET_MSK 0x00000001
2366 /* The mask used to clear the ALT_ECC_NANDW_ACCCTL_DATAOVR register field value. */
2367 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2368 /* The reset value of the ALT_ECC_NANDW_ACCCTL_DATAOVR register field. */
2369 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_RESET 0x0
2370 /* Extracts the ALT_ECC_NANDW_ACCCTL_DATAOVR field value from a register. */
2371 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2372 /* Produces a ALT_ECC_NANDW_ACCCTL_DATAOVR register field value suitable for setting the register. */
2373 #define ALT_ECC_NANDW_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2374 
2375 /*
2376  * Field : ECCOVR
2377  *
2378  * ECC Data Override.
2379  *
2380  * Field Access Macros:
2381  *
2382  */
2383 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ACCCTL_ECCOVR register field. */
2384 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_LSB 1
2385 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ACCCTL_ECCOVR register field. */
2386 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_MSB 1
2387 /* The width in bits of the ALT_ECC_NANDW_ACCCTL_ECCOVR register field. */
2388 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_WIDTH 1
2389 /* The mask used to set the ALT_ECC_NANDW_ACCCTL_ECCOVR register field value. */
2390 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_SET_MSK 0x00000002
2391 /* The mask used to clear the ALT_ECC_NANDW_ACCCTL_ECCOVR register field value. */
2392 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2393 /* The reset value of the ALT_ECC_NANDW_ACCCTL_ECCOVR register field. */
2394 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_RESET 0x0
2395 /* Extracts the ALT_ECC_NANDW_ACCCTL_ECCOVR field value from a register. */
2396 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2397 /* Produces a ALT_ECC_NANDW_ACCCTL_ECCOVR register field value suitable for setting the register. */
2398 #define ALT_ECC_NANDW_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2399 
2400 /*
2401  * Field : RDWR
2402  *
2403  * Control for read/write.
2404  *
2405  * Field Access Macros:
2406  *
2407  */
2408 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_ACCCTL_RDWR register field. */
2409 #define ALT_ECC_NANDW_ACCCTL_RDWR_LSB 8
2410 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_ACCCTL_RDWR register field. */
2411 #define ALT_ECC_NANDW_ACCCTL_RDWR_MSB 8
2412 /* The width in bits of the ALT_ECC_NANDW_ACCCTL_RDWR register field. */
2413 #define ALT_ECC_NANDW_ACCCTL_RDWR_WIDTH 1
2414 /* The mask used to set the ALT_ECC_NANDW_ACCCTL_RDWR register field value. */
2415 #define ALT_ECC_NANDW_ACCCTL_RDWR_SET_MSK 0x00000100
2416 /* The mask used to clear the ALT_ECC_NANDW_ACCCTL_RDWR register field value. */
2417 #define ALT_ECC_NANDW_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2418 /* The reset value of the ALT_ECC_NANDW_ACCCTL_RDWR register field. */
2419 #define ALT_ECC_NANDW_ACCCTL_RDWR_RESET 0x0
2420 /* Extracts the ALT_ECC_NANDW_ACCCTL_RDWR field value from a register. */
2421 #define ALT_ECC_NANDW_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2422 /* Produces a ALT_ECC_NANDW_ACCCTL_RDWR register field value suitable for setting the register. */
2423 #define ALT_ECC_NANDW_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2424 
2425 #ifndef __ASSEMBLY__
2426 /*
2427  * WARNING: The C register and register group struct declarations are provided for
2428  * convenience and illustrative purposes. They should, however, be used with
2429  * caution as the C language standard provides no guarantees about the alignment or
2430  * atomicity of device memory accesses. The recommended practice for writing
2431  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2432  * alt_write_word() functions.
2433  *
2434  * The struct declaration for register ALT_ECC_NANDW_ACCCTL.
2435  */
2436 struct ALT_ECC_NANDW_ACCCTL_s
2437 {
2438  uint32_t DATAOVR : 1; /* ALT_ECC_NANDW_ACCCTL_DATAOVR */
2439  uint32_t ECCOVR : 1; /* ALT_ECC_NANDW_ACCCTL_ECCOVR */
2440  uint32_t : 6; /* *UNDEFINED* */
2441  uint32_t RDWR : 1; /* ALT_ECC_NANDW_ACCCTL_RDWR */
2442  uint32_t : 23; /* *UNDEFINED* */
2443 };
2444 
2445 /* The typedef declaration for register ALT_ECC_NANDW_ACCCTL. */
2446 typedef volatile struct ALT_ECC_NANDW_ACCCTL_s ALT_ECC_NANDW_ACCCTL_t;
2447 #endif /* __ASSEMBLY__ */
2448 
2449 /* The reset value of the ALT_ECC_NANDW_ACCCTL register. */
2450 #define ALT_ECC_NANDW_ACCCTL_RESET 0x00000000
2451 /* The byte offset of the ALT_ECC_NANDW_ACCCTL register from the beginning of the component. */
2452 #define ALT_ECC_NANDW_ACCCTL_OFST 0x78
2453 /* The address of the ALT_ECC_NANDW_ACCCTL register. */
2454 #define ALT_ECC_NANDW_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_ACCCTL_OFST))
2455 
2456 /*
2457  * Register : ECC_startacc
2458  *
2459  * These bits determine which byte of data/ecc to write to RAM.
2460  *
2461  * Register Layout
2462  *
2463  * Bits | Access | Reset | Description
2464  * :--------|:-------|:------|:------------------------------
2465  * [15:0] | ??? | 0x0 | *UNDEFINED*
2466  * [16] | RW | 0x0 | ALT_ECC_NANDW_STARTACC_ENBUSA
2467  * [31:17] | ??? | 0x0 | *UNDEFINED*
2468  *
2469  */
2470 /*
2471  * Field : ENBUSA
2472  *
2473  * Start RAM access for PORTA.
2474  *
2475  * Field Access Macros:
2476  *
2477  */
2478 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_STARTACC_ENBUSA register field. */
2479 #define ALT_ECC_NANDW_STARTACC_ENBUSA_LSB 16
2480 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_STARTACC_ENBUSA register field. */
2481 #define ALT_ECC_NANDW_STARTACC_ENBUSA_MSB 16
2482 /* The width in bits of the ALT_ECC_NANDW_STARTACC_ENBUSA register field. */
2483 #define ALT_ECC_NANDW_STARTACC_ENBUSA_WIDTH 1
2484 /* The mask used to set the ALT_ECC_NANDW_STARTACC_ENBUSA register field value. */
2485 #define ALT_ECC_NANDW_STARTACC_ENBUSA_SET_MSK 0x00010000
2486 /* The mask used to clear the ALT_ECC_NANDW_STARTACC_ENBUSA register field value. */
2487 #define ALT_ECC_NANDW_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2488 /* The reset value of the ALT_ECC_NANDW_STARTACC_ENBUSA register field. */
2489 #define ALT_ECC_NANDW_STARTACC_ENBUSA_RESET 0x0
2490 /* Extracts the ALT_ECC_NANDW_STARTACC_ENBUSA field value from a register. */
2491 #define ALT_ECC_NANDW_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2492 /* Produces a ALT_ECC_NANDW_STARTACC_ENBUSA register field value suitable for setting the register. */
2493 #define ALT_ECC_NANDW_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2494 
2495 #ifndef __ASSEMBLY__
2496 /*
2497  * WARNING: The C register and register group struct declarations are provided for
2498  * convenience and illustrative purposes. They should, however, be used with
2499  * caution as the C language standard provides no guarantees about the alignment or
2500  * atomicity of device memory accesses. The recommended practice for writing
2501  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2502  * alt_write_word() functions.
2503  *
2504  * The struct declaration for register ALT_ECC_NANDW_STARTACC.
2505  */
2506 struct ALT_ECC_NANDW_STARTACC_s
2507 {
2508  uint32_t : 16; /* *UNDEFINED* */
2509  uint32_t ENBUSA : 1; /* ALT_ECC_NANDW_STARTACC_ENBUSA */
2510  uint32_t : 15; /* *UNDEFINED* */
2511 };
2512 
2513 /* The typedef declaration for register ALT_ECC_NANDW_STARTACC. */
2514 typedef volatile struct ALT_ECC_NANDW_STARTACC_s ALT_ECC_NANDW_STARTACC_t;
2515 #endif /* __ASSEMBLY__ */
2516 
2517 /* The reset value of the ALT_ECC_NANDW_STARTACC register. */
2518 #define ALT_ECC_NANDW_STARTACC_RESET 0x00000000
2519 /* The byte offset of the ALT_ECC_NANDW_STARTACC register from the beginning of the component. */
2520 #define ALT_ECC_NANDW_STARTACC_OFST 0x7c
2521 /* The address of the ALT_ECC_NANDW_STARTACC register. */
2522 #define ALT_ECC_NANDW_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_STARTACC_OFST))
2523 
2524 /*
2525  * Register : ECC_wdctrl
2526  *
2527  * Bits to Enable/Disable Watch Dog Timer
2528  *
2529  * Register Layout
2530  *
2531  * Bits | Access | Reset | Description
2532  * :-------|:-------|:------|:-----------------------------
2533  * [0] | RW | 0x0 | ALT_ECC_NANDW_WDCTL_WDEN_RAM
2534  * [31:1] | ??? | 0x0 | *UNDEFINED*
2535  *
2536  */
2537 /*
2538  * Field : WDEN_RAM
2539  *
2540  * Enable watchdog timeout for OCP register access to IP RAM.
2541  *
2542  * Field Access Macros:
2543  *
2544  */
2545 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field. */
2546 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_LSB 0
2547 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field. */
2548 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_MSB 0
2549 /* The width in bits of the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field. */
2550 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_WIDTH 1
2551 /* The mask used to set the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field value. */
2552 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2553 /* The mask used to clear the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field value. */
2554 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2555 /* The reset value of the ALT_ECC_NANDW_WDCTL_WDEN_RAM register field. */
2556 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_RESET 0x0
2557 /* Extracts the ALT_ECC_NANDW_WDCTL_WDEN_RAM field value from a register. */
2558 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2559 /* Produces a ALT_ECC_NANDW_WDCTL_WDEN_RAM register field value suitable for setting the register. */
2560 #define ALT_ECC_NANDW_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2561 
2562 #ifndef __ASSEMBLY__
2563 /*
2564  * WARNING: The C register and register group struct declarations are provided for
2565  * convenience and illustrative purposes. They should, however, be used with
2566  * caution as the C language standard provides no guarantees about the alignment or
2567  * atomicity of device memory accesses. The recommended practice for writing
2568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2569  * alt_write_word() functions.
2570  *
2571  * The struct declaration for register ALT_ECC_NANDW_WDCTL.
2572  */
2573 struct ALT_ECC_NANDW_WDCTL_s
2574 {
2575  uint32_t WDEN_RAM : 1; /* ALT_ECC_NANDW_WDCTL_WDEN_RAM */
2576  uint32_t : 31; /* *UNDEFINED* */
2577 };
2578 
2579 /* The typedef declaration for register ALT_ECC_NANDW_WDCTL. */
2580 typedef volatile struct ALT_ECC_NANDW_WDCTL_s ALT_ECC_NANDW_WDCTL_t;
2581 #endif /* __ASSEMBLY__ */
2582 
2583 /* The reset value of the ALT_ECC_NANDW_WDCTL register. */
2584 #define ALT_ECC_NANDW_WDCTL_RESET 0x00000000
2585 /* The byte offset of the ALT_ECC_NANDW_WDCTL register from the beginning of the component. */
2586 #define ALT_ECC_NANDW_WDCTL_OFST 0x80
2587 /* The address of the ALT_ECC_NANDW_WDCTL register. */
2588 #define ALT_ECC_NANDW_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDCTL_OFST))
2589 
2590 /*
2591  * Register : SERRLKUPA0
2592  *
2593  * Single-bit error address in LOOKUP TABLE for PORTA.
2594  *
2595  * Register Layout
2596  *
2597  * Bits | Access | Reset | Description
2598  * :-------|:-------|:------|:-------------------------------
2599  * [6:0] | R | 0x0 | ALT_ECC_NANDW_SERRLKUPA0_ADDR
2600  * [30:7] | ??? | 0x0 | *UNDEFINED*
2601  * [31] | RW | 0x0 | ALT_ECC_NANDW_SERRLKUPA0_VALID
2602  *
2603  */
2604 /*
2605  * Field : Address
2606  *
2607  * Recent Single-bit error address.
2608  *
2609  * This register shows the address of the each single-bit error. RAM size will
2610  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
2611  * 30-16 will be reserved and read as zero.
2612  *
2613  * Field Access Macros:
2614  *
2615  */
2616 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field. */
2617 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_LSB 0
2618 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field. */
2619 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_MSB 6
2620 /* The width in bits of the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field. */
2621 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_WIDTH 7
2622 /* The mask used to set the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field value. */
2623 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_SET_MSK 0x0000007f
2624 /* The mask used to clear the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field value. */
2625 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_CLR_MSK 0xffffff80
2626 /* The reset value of the ALT_ECC_NANDW_SERRLKUPA0_ADDR register field. */
2627 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_RESET 0x0
2628 /* Extracts the ALT_ECC_NANDW_SERRLKUPA0_ADDR field value from a register. */
2629 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
2630 /* Produces a ALT_ECC_NANDW_SERRLKUPA0_ADDR register field value suitable for setting the register. */
2631 #define ALT_ECC_NANDW_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x0000007f)
2632 
2633 /*
2634  * Field : VALID
2635  *
2636  * Valid flag bit. Valid bit indicates if the address in this register is current
2637  * or stale.
2638  *
2639  * Field Access Macros:
2640  *
2641  */
2642 /* The Least Significant Bit (LSB) position of the ALT_ECC_NANDW_SERRLKUPA0_VALID register field. */
2643 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_LSB 31
2644 /* The Most Significant Bit (MSB) position of the ALT_ECC_NANDW_SERRLKUPA0_VALID register field. */
2645 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_MSB 31
2646 /* The width in bits of the ALT_ECC_NANDW_SERRLKUPA0_VALID register field. */
2647 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_WIDTH 1
2648 /* The mask used to set the ALT_ECC_NANDW_SERRLKUPA0_VALID register field value. */
2649 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_SET_MSK 0x80000000
2650 /* The mask used to clear the ALT_ECC_NANDW_SERRLKUPA0_VALID register field value. */
2651 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2652 /* The reset value of the ALT_ECC_NANDW_SERRLKUPA0_VALID register field. */
2653 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_RESET 0x0
2654 /* Extracts the ALT_ECC_NANDW_SERRLKUPA0_VALID field value from a register. */
2655 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2656 /* Produces a ALT_ECC_NANDW_SERRLKUPA0_VALID register field value suitable for setting the register. */
2657 #define ALT_ECC_NANDW_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2658 
2659 #ifndef __ASSEMBLY__
2660 /*
2661  * WARNING: The C register and register group struct declarations are provided for
2662  * convenience and illustrative purposes. They should, however, be used with
2663  * caution as the C language standard provides no guarantees about the alignment or
2664  * atomicity of device memory accesses. The recommended practice for writing
2665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2666  * alt_write_word() functions.
2667  *
2668  * The struct declaration for register ALT_ECC_NANDW_SERRLKUPA0.
2669  */
2670 struct ALT_ECC_NANDW_SERRLKUPA0_s
2671 {
2672  const uint32_t Address : 7; /* ALT_ECC_NANDW_SERRLKUPA0_ADDR */
2673  uint32_t : 24; /* *UNDEFINED* */
2674  uint32_t VALID : 1; /* ALT_ECC_NANDW_SERRLKUPA0_VALID */
2675 };
2676 
2677 /* The typedef declaration for register ALT_ECC_NANDW_SERRLKUPA0. */
2678 typedef volatile struct ALT_ECC_NANDW_SERRLKUPA0_s ALT_ECC_NANDW_SERRLKUPA0_t;
2679 #endif /* __ASSEMBLY__ */
2680 
2681 /* The reset value of the ALT_ECC_NANDW_SERRLKUPA0 register. */
2682 #define ALT_ECC_NANDW_SERRLKUPA0_RESET 0x00000000
2683 /* The byte offset of the ALT_ECC_NANDW_SERRLKUPA0 register from the beginning of the component. */
2684 #define ALT_ECC_NANDW_SERRLKUPA0_OFST 0x90
2685 
2686 #ifndef __ASSEMBLY__
2687 /*
2688  * WARNING: The C register and register group struct declarations are provided for
2689  * convenience and illustrative purposes. They should, however, be used with
2690  * caution as the C language standard provides no guarantees about the alignment or
2691  * atomicity of device memory accesses. The recommended practice for writing
2692  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2693  * alt_write_word() functions.
2694  *
2695  * The struct declaration for register group ALT_ECC_NANDW.
2696  */
2697 struct ALT_ECC_NANDW_s
2698 {
2699  ALT_ECC_NANDW_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_NANDW_IP_REV_ID */
2700  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2701  ALT_ECC_NANDW_CTL_t CTRL; /* ALT_ECC_NANDW_CTL */
2702  ALT_ECC_NANDW_INITSTAT_t INITSTAT; /* ALT_ECC_NANDW_INITSTAT */
2703  ALT_ECC_NANDW_ERRINTEN_t ERRINTEN; /* ALT_ECC_NANDW_ERRINTEN */
2704  ALT_ECC_NANDW_ERRINTENS_t ERRINTENS; /* ALT_ECC_NANDW_ERRINTENS */
2705  ALT_ECC_NANDW_ERRINTENR_t ERRINTENR; /* ALT_ECC_NANDW_ERRINTENR */
2706  ALT_ECC_NANDW_INTMOD_t INTMODE; /* ALT_ECC_NANDW_INTMOD */
2707  ALT_ECC_NANDW_INTSTAT_t INTSTAT; /* ALT_ECC_NANDW_INTSTAT */
2708  ALT_ECC_NANDW_INTTEST_t INTTEST; /* ALT_ECC_NANDW_INTTEST */
2709  ALT_ECC_NANDW_MODSTAT_t MODSTAT; /* ALT_ECC_NANDW_MODSTAT */
2710  ALT_ECC_NANDW_DERRADDRA_t DERRADDRA; /* ALT_ECC_NANDW_DERRADDRA */
2711  ALT_ECC_NANDW_SERRADDRA_t SERRADDRA; /* ALT_ECC_NANDW_SERRADDRA */
2712  volatile uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2713  ALT_ECC_NANDW_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_NANDW_SERRCNTREG */
2714  ALT_ECC_NANDW_ADDRBUS_t ECC_Addrbus; /* ALT_ECC_NANDW_ADDRBUS */
2715  ALT_ECC_NANDW_RDATA0BUS_t ECC_RData0bus; /* ALT_ECC_NANDW_RDATA0BUS */
2716  ALT_ECC_NANDW_RDATA1BUS_t ECC_RData1bus; /* ALT_ECC_NANDW_RDATA1BUS */
2717  ALT_ECC_NANDW_RDATA2BUS_t ECC_RData2bus; /* ALT_ECC_NANDW_RDATA2BUS */
2718  ALT_ECC_NANDW_RDATA3BUS_t ECC_RData3bus; /* ALT_ECC_NANDW_RDATA3BUS */
2719  ALT_ECC_NANDW_WDATA0BUS_t ECC_WData0bus; /* ALT_ECC_NANDW_WDATA0BUS */
2720  ALT_ECC_NANDW_WDATA1BUS_t ECC_WData1bus; /* ALT_ECC_NANDW_WDATA1BUS */
2721  ALT_ECC_NANDW_WDATA2BUS_t ECC_WData2bus; /* ALT_ECC_NANDW_WDATA2BUS */
2722  ALT_ECC_NANDW_WDATA3BUS_t ECC_WData3bus; /* ALT_ECC_NANDW_WDATA3BUS */
2723  ALT_ECC_NANDW_RDATAECC0BUS_t ECC_RDataecc0bus; /* ALT_ECC_NANDW_RDATAECC0BUS */
2724  ALT_ECC_NANDW_RDATAECC1BUS_t ECC_RDataecc1bus; /* ALT_ECC_NANDW_RDATAECC1BUS */
2725  ALT_ECC_NANDW_WDATAECC0BUS_t ECC_WDataecc0bus; /* ALT_ECC_NANDW_WDATAECC0BUS */
2726  ALT_ECC_NANDW_WDATAECC1BUS_t ECC_WDataecc1bus; /* ALT_ECC_NANDW_WDATAECC1BUS */
2727  ALT_ECC_NANDW_DBYTECTL_t ECC_dbytectrl; /* ALT_ECC_NANDW_DBYTECTL */
2728  ALT_ECC_NANDW_ACCCTL_t ECC_accctrl; /* ALT_ECC_NANDW_ACCCTL */
2729  ALT_ECC_NANDW_STARTACC_t ECC_startacc; /* ALT_ECC_NANDW_STARTACC */
2730  ALT_ECC_NANDW_WDCTL_t ECC_wdctrl; /* ALT_ECC_NANDW_WDCTL */
2731  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2732  ALT_ECC_NANDW_SERRLKUPA0_t SERRLKUPA0; /* ALT_ECC_NANDW_SERRLKUPA0 */
2733  volatile uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2734 };
2735 
2736 /* The typedef declaration for register group ALT_ECC_NANDW. */
2737 typedef volatile struct ALT_ECC_NANDW_s ALT_ECC_NANDW_t;
2738 /* The struct declaration for the raw register contents of register group ALT_ECC_NANDW. */
2739 struct ALT_ECC_NANDW_raw_s
2740 {
2741  volatile uint32_t IP_REV_ID; /* ALT_ECC_NANDW_IP_REV_ID */
2742  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2743  volatile uint32_t CTRL; /* ALT_ECC_NANDW_CTL */
2744  volatile uint32_t INITSTAT; /* ALT_ECC_NANDW_INITSTAT */
2745  volatile uint32_t ERRINTEN; /* ALT_ECC_NANDW_ERRINTEN */
2746  volatile uint32_t ERRINTENS; /* ALT_ECC_NANDW_ERRINTENS */
2747  volatile uint32_t ERRINTENR; /* ALT_ECC_NANDW_ERRINTENR */
2748  volatile uint32_t INTMODE; /* ALT_ECC_NANDW_INTMOD */
2749  volatile uint32_t INTSTAT; /* ALT_ECC_NANDW_INTSTAT */
2750  volatile uint32_t INTTEST; /* ALT_ECC_NANDW_INTTEST */
2751  volatile uint32_t MODSTAT; /* ALT_ECC_NANDW_MODSTAT */
2752  volatile uint32_t DERRADDRA; /* ALT_ECC_NANDW_DERRADDRA */
2753  volatile uint32_t SERRADDRA; /* ALT_ECC_NANDW_SERRADDRA */
2754  uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2755  volatile uint32_t SERRCNTREG; /* ALT_ECC_NANDW_SERRCNTREG */
2756  volatile uint32_t ECC_Addrbus; /* ALT_ECC_NANDW_ADDRBUS */
2757  volatile uint32_t ECC_RData0bus; /* ALT_ECC_NANDW_RDATA0BUS */
2758  volatile uint32_t ECC_RData1bus; /* ALT_ECC_NANDW_RDATA1BUS */
2759  volatile uint32_t ECC_RData2bus; /* ALT_ECC_NANDW_RDATA2BUS */
2760  volatile uint32_t ECC_RData3bus; /* ALT_ECC_NANDW_RDATA3BUS */
2761  volatile uint32_t ECC_WData0bus; /* ALT_ECC_NANDW_WDATA0BUS */
2762  volatile uint32_t ECC_WData1bus; /* ALT_ECC_NANDW_WDATA1BUS */
2763  volatile uint32_t ECC_WData2bus; /* ALT_ECC_NANDW_WDATA2BUS */
2764  volatile uint32_t ECC_WData3bus; /* ALT_ECC_NANDW_WDATA3BUS */
2765  volatile uint32_t ECC_RDataecc0bus; /* ALT_ECC_NANDW_RDATAECC0BUS */
2766  volatile uint32_t ECC_RDataecc1bus; /* ALT_ECC_NANDW_RDATAECC1BUS */
2767  volatile uint32_t ECC_WDataecc0bus; /* ALT_ECC_NANDW_WDATAECC0BUS */
2768  volatile uint32_t ECC_WDataecc1bus; /* ALT_ECC_NANDW_WDATAECC1BUS */
2769  volatile uint32_t ECC_dbytectrl; /* ALT_ECC_NANDW_DBYTECTL */
2770  volatile uint32_t ECC_accctrl; /* ALT_ECC_NANDW_ACCCTL */
2771  volatile uint32_t ECC_startacc; /* ALT_ECC_NANDW_STARTACC */
2772  volatile uint32_t ECC_wdctrl; /* ALT_ECC_NANDW_WDCTL */
2773  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2774  volatile uint32_t SERRLKUPA0; /* ALT_ECC_NANDW_SERRLKUPA0 */
2775  uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2776 };
2777 
2778 /* The typedef declaration for the raw register contents of register group ALT_ECC_NANDW. */
2779 typedef volatile struct ALT_ECC_NANDW_raw_s ALT_ECC_NANDW_raw_t;
2780 #endif /* __ASSEMBLY__ */
2781 
2782 
2783 #ifdef __cplusplus
2784 }
2785 #endif /* __cplusplus */
2786 #endif /* __ALT_SOCAL_ECC_NANDW_H__ */
2787