35 #ifndef __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
82 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_LSB 0
84 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_MSB 0
86 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_WIDTH 1
88 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET_MSK 0x00000001
90 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_CLR_MSK 0xfffffffe
92 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_RESET 0x0
94 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
96 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
108 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_LSB 1
110 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_MSB 1
112 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_WIDTH 1
114 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET_MSK 0x00000002
116 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_CLR_MSK 0xfffffffd
118 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_RESET 0x0
120 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
122 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
134 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_LSB 2
136 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_MSB 2
138 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_WIDTH 1
140 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET_MSK 0x00000004
142 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_CLR_MSK 0xfffffffb
144 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_RESET 0x0
146 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
148 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
160 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_LSB 3
162 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_MSB 3
164 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_WIDTH 1
166 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET_MSK 0x00000008
168 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_CLR_MSK 0xfffffff7
170 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_RESET 0x0
172 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
174 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
186 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_LSB 4
188 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_MSB 4
190 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_WIDTH 1
192 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET_MSK 0x00000010
194 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_CLR_MSK 0xffffffef
196 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_RESET 0x0
198 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
200 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
212 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_LSB 5
214 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_MSB 5
216 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_WIDTH 1
218 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET_MSK 0x00000020
220 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_CLR_MSK 0xffffffdf
222 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_RESET 0x0
224 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
226 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
238 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_LSB 6
240 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_MSB 6
242 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_WIDTH 1
244 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET_MSK 0x00000040
246 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_CLR_MSK 0xffffffbf
248 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_RESET 0x0
250 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
252 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
264 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_LSB 7
266 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_MSB 7
268 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_WIDTH 1
270 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET_MSK 0x00000080
272 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_CLR_MSK 0xffffff7f
274 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_RESET 0x0
276 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
278 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
291 struct ALT_NOC_FW_DDR_L3_SCR_EN_s
293 uint32_t hpsregion0enable : 1;
294 uint32_t hpsregion1enable : 1;
295 uint32_t hpsregion2enable : 1;
296 uint32_t hpsregion3enable : 1;
297 uint32_t hpsregion4enable : 1;
298 uint32_t hpsregion5enable : 1;
299 uint32_t hpsregion6enable : 1;
300 uint32_t hpsregion7enable : 1;
305 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_s ALT_NOC_FW_DDR_L3_SCR_EN_t;
309 #define ALT_NOC_FW_DDR_L3_SCR_EN_RESET 0x00000000
311 #define ALT_NOC_FW_DDR_L3_SCR_EN_OFST 0x0
346 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_LSB 0
348 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_MSB 0
350 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_WIDTH 1
352 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET_MSK 0x00000001
354 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_CLR_MSK 0xfffffffe
356 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_RESET 0x0
358 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
360 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
375 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_LSB 1
377 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_MSB 1
379 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_WIDTH 1
381 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET_MSK 0x00000002
383 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_CLR_MSK 0xfffffffd
385 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_RESET 0x0
387 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
389 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
404 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_LSB 2
406 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_MSB 2
408 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_WIDTH 1
410 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET_MSK 0x00000004
412 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_CLR_MSK 0xfffffffb
414 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_RESET 0x0
416 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
418 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
433 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_LSB 3
435 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_MSB 3
437 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_WIDTH 1
439 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET_MSK 0x00000008
441 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_CLR_MSK 0xfffffff7
443 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_RESET 0x0
445 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
447 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
462 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_LSB 4
464 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_MSB 4
466 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_WIDTH 1
468 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET_MSK 0x00000010
470 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_CLR_MSK 0xffffffef
472 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_RESET 0x0
474 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
476 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
491 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_LSB 5
493 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_MSB 5
495 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_WIDTH 1
497 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET_MSK 0x00000020
499 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_CLR_MSK 0xffffffdf
501 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_RESET 0x0
503 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
505 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
520 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_LSB 6
522 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_MSB 6
524 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_WIDTH 1
526 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET_MSK 0x00000040
528 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_CLR_MSK 0xffffffbf
530 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_RESET 0x0
532 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
534 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
549 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_LSB 7
551 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_MSB 7
553 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_WIDTH 1
555 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET_MSK 0x00000080
557 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_CLR_MSK 0xffffff7f
559 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_RESET 0x0
561 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
563 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
576 struct ALT_NOC_FW_DDR_L3_SCR_EN_SET_s
578 uint32_t hpsregion0enable : 1;
579 uint32_t hpsregion1enable : 1;
580 uint32_t hpsregion2enable : 1;
581 uint32_t hpsregion3enable : 1;
582 uint32_t hpsregion4enable : 1;
583 uint32_t hpsregion5enable : 1;
584 uint32_t hpsregion6enable : 1;
585 uint32_t hpsregion7enable : 1;
590 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_SET_s ALT_NOC_FW_DDR_L3_SCR_EN_SET_t;
594 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_RESET 0x00000000
596 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_OFST 0x4
631 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0
633 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0
635 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1
637 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001
639 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe
641 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0
643 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
645 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
660 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1
662 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1
664 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1
666 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002
668 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd
670 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0
672 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
674 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
689 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2
691 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2
693 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1
695 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004
697 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb
699 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0
701 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
703 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
718 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3
720 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3
722 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1
724 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008
726 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7
728 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0
730 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
732 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
747 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4
749 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4
751 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1
753 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010
755 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef
757 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0
759 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
761 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
776 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5
778 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5
780 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1
782 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020
784 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf
786 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0
788 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
790 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
805 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6
807 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6
809 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1
811 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040
813 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf
815 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0
817 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
819 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
834 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7
836 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7
838 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1
840 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080
842 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f
844 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0
846 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
848 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
861 struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s
863 uint32_t hpsregion0enable : 1;
864 uint32_t hpsregion1enable : 1;
865 uint32_t hpsregion2enable : 1;
866 uint32_t hpsregion3enable : 1;
867 uint32_t hpsregion4enable : 1;
868 uint32_t hpsregion5enable : 1;
869 uint32_t hpsregion6enable : 1;
870 uint32_t hpsregion7enable : 1;
875 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t;
879 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000
881 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8
906 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_LSB 0
908 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_MSB 15
910 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_WIDTH 16
912 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET_MSK 0x0000ffff
914 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_CLR_MSK 0xffff0000
916 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_RESET 0x0
918 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
920 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
932 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_LSB 16
934 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_MSB 31
936 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_WIDTH 16
938 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET_MSK 0xffff0000
940 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
942 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_RESET 0x0
944 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
946 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
959 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s
966 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t;
970 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_RESET 0x00000000
972 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_OFST 0xc
997 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_LSB 0
999 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_MSB 15
1001 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_WIDTH 16
1003 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET_MSK 0x0000ffff
1005 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_CLR_MSK 0xffff0000
1007 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_RESET 0x0
1009 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1011 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1023 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_LSB 16
1025 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_MSB 31
1027 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_WIDTH 16
1029 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET_MSK 0xffff0000
1031 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1033 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_RESET 0x0
1035 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1037 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1039 #ifndef __ASSEMBLY__
1050 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s
1053 uint32_t limit : 16;
1057 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t;
1061 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_RESET 0x00000000
1063 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_OFST 0x10
1088 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_LSB 0
1090 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_MSB 15
1092 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_WIDTH 16
1094 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET_MSK 0x0000ffff
1096 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_CLR_MSK 0xffff0000
1098 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_RESET 0x0
1100 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1102 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1114 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_LSB 16
1116 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_MSB 31
1118 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_WIDTH 16
1120 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET_MSK 0xffff0000
1122 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1124 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_RESET 0x0
1126 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1128 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1130 #ifndef __ASSEMBLY__
1141 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s
1144 uint32_t limit : 16;
1148 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t;
1152 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_RESET 0x00000000
1154 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_OFST 0x14
1179 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_LSB 0
1181 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_MSB 15
1183 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_WIDTH 16
1185 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET_MSK 0x0000ffff
1187 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_CLR_MSK 0xffff0000
1189 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_RESET 0x0
1191 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1193 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1205 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_LSB 16
1207 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_MSB 31
1209 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_WIDTH 16
1211 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET_MSK 0xffff0000
1213 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1215 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_RESET 0x0
1217 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1219 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1221 #ifndef __ASSEMBLY__
1232 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s
1235 uint32_t limit : 16;
1239 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t;
1243 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_RESET 0x00000000
1245 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_OFST 0x18
1270 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0
1272 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15
1274 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16
1276 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff
1278 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000
1280 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0
1282 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1284 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1296 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16
1298 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31
1300 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16
1302 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000
1304 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff
1306 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0
1308 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1310 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1312 #ifndef __ASSEMBLY__
1323 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s
1326 uint32_t limit : 16;
1330 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t;
1334 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000
1336 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c
1361 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_LSB 0
1363 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_MSB 15
1365 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_WIDTH 16
1367 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET_MSK 0x0000ffff
1369 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_CLR_MSK 0xffff0000
1371 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_RESET 0x0
1373 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1375 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1387 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_LSB 16
1389 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_MSB 31
1391 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_WIDTH 16
1393 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET_MSK 0xffff0000
1395 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_CLR_MSK 0x0000ffff
1397 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_RESET 0x0
1399 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1401 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1403 #ifndef __ASSEMBLY__
1414 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s
1417 uint32_t limit : 16;
1421 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t;
1425 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_RESET 0x00000000
1427 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_OFST 0x20
1452 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_LSB 0
1454 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_MSB 15
1456 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_WIDTH 16
1458 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET_MSK 0x0000ffff
1460 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_CLR_MSK 0xffff0000
1462 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_RESET 0x0
1464 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1466 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1478 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_LSB 16
1480 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_MSB 31
1482 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_WIDTH 16
1484 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET_MSK 0xffff0000
1486 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_CLR_MSK 0x0000ffff
1488 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_RESET 0x0
1490 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1492 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1494 #ifndef __ASSEMBLY__
1505 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s
1508 uint32_t limit : 16;
1512 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t;
1516 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_RESET 0x00000000
1518 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_OFST 0x24
1543 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_LSB 0
1545 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_MSB 15
1547 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_WIDTH 16
1549 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET_MSK 0x0000ffff
1551 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_CLR_MSK 0xffff0000
1553 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_RESET 0x0
1555 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1557 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1569 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_LSB 16
1571 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_MSB 31
1573 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_WIDTH 16
1575 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET_MSK 0xffff0000
1577 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_CLR_MSK 0x0000ffff
1579 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_RESET 0x0
1581 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1583 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1585 #ifndef __ASSEMBLY__
1596 struct ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s
1599 uint32_t limit : 16;
1603 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t;
1607 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_RESET 0x00000000
1609 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_OFST 0x28
1636 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_LSB 0
1638 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_MSB 0
1640 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_WIDTH 1
1642 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET_MSK 0x00000001
1644 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_CLR_MSK 0xfffffffe
1646 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_RESET 0x0
1648 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_GET(value) (((value) & 0x00000001) >> 0)
1650 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET(value) (((value) << 0) & 0x00000001)
1652 #ifndef __ASSEMBLY__
1663 struct ALT_NOC_FW_DDR_L3_SCR_GLOB_s
1665 uint32_t error_response : 1;
1670 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_GLOB_s ALT_NOC_FW_DDR_L3_SCR_GLOB_t;
1674 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_RESET 0x00000000
1676 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_OFST 0x2c
1678 #ifndef __ASSEMBLY__
1689 struct ALT_NOC_FW_DDR_L3_SCR_s
1691 ALT_NOC_FW_DDR_L3_SCR_EN_t enable;
1692 ALT_NOC_FW_DDR_L3_SCR_EN_SET_t enable_set;
1693 ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t enable_clear;
1694 ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t hpsregion0addr;
1695 ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t hpsregion1addr;
1696 ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t hpsregion2addr;
1697 ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t hpsregion3addr;
1698 ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t hpsregion4addr;
1699 ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t hpsregion5addr;
1700 ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t hpsregion6addr;
1701 ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t hpsregion7addr;
1702 ALT_NOC_FW_DDR_L3_SCR_GLOB_t global;
1703 volatile uint32_t _pad_0x30_0x100[52];
1707 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_s ALT_NOC_FW_DDR_L3_SCR_t;
1709 struct ALT_NOC_FW_DDR_L3_SCR_raw_s
1711 volatile uint32_t enable;
1712 volatile uint32_t enable_set;
1713 volatile uint32_t enable_clear;
1714 volatile uint32_t hpsregion0addr;
1715 volatile uint32_t hpsregion1addr;
1716 volatile uint32_t hpsregion2addr;
1717 volatile uint32_t hpsregion3addr;
1718 volatile uint32_t hpsregion4addr;
1719 volatile uint32_t hpsregion5addr;
1720 volatile uint32_t hpsregion6addr;
1721 volatile uint32_t hpsregion7addr;
1722 volatile uint32_t global;
1723 uint32_t _pad_0x30_0x100[52];
1727 typedef volatile struct ALT_NOC_FW_DDR_L3_SCR_raw_s ALT_NOC_FW_DDR_L3_SCR_raw_t;