35 #ifndef __ALT_SOCAL_QSPI_H__
36 #define __ALT_SOCAL_QSPI_H__
99 #define ALT_QSPI_CFG_EN_E_DISABLE 0x0
105 #define ALT_QSPI_CFG_EN_E_ENABLE 0x1
108 #define ALT_QSPI_CFG_EN_LSB 0
110 #define ALT_QSPI_CFG_EN_MSB 0
112 #define ALT_QSPI_CFG_EN_WIDTH 1
114 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
116 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
118 #define ALT_QSPI_CFG_EN_RESET 0x0
120 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
122 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
144 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
150 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
153 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
155 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
157 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
159 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
161 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
163 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
165 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
167 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
191 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACTIVE 0x0
197 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACTIVE 0x1
200 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
202 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
204 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
206 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
208 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
210 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
212 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
214 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
223 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_LSB 3
225 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_MSB 6
227 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_WIDTH 4
229 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_SET_MSK 0x00000078
231 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_CLR_MSK 0xffffff87
233 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_RESET 0x0
235 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_GET(value) (((value) & 0x00000078) >> 3)
237 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_SET(value) (((value) << 3) & 0x00000078)
262 #define ALT_QSPI_CFG_ENDIRACC_E_DISABLE 0x0
268 #define ALT_QSPI_CFG_ENDIRACC_E_ENABLE 0x1
271 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
273 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
275 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
277 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
279 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
281 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
283 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
285 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
312 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMODE 0x0
318 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMODE 0x1
321 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
323 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
325 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
327 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
329 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
331 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
333 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
335 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
358 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
364 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
367 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
369 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
371 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
373 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
375 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
377 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
379 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
381 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
394 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
396 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
398 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
400 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
402 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
404 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
406 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
408 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
431 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
437 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
440 #define ALT_QSPI_CFG_WP_LSB 14
442 #define ALT_QSPI_CFG_WP_MSB 14
444 #define ALT_QSPI_CFG_WP_WIDTH 1
446 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
448 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
450 #define ALT_QSPI_CFG_WP_RESET 0x0
452 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
454 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
477 #define ALT_QSPI_CFG_ENDMA_E_DISABLE 0x0
483 #define ALT_QSPI_CFG_ENDMA_E_ENABLE 0x1
486 #define ALT_QSPI_CFG_ENDMA_LSB 15
488 #define ALT_QSPI_CFG_ENDMA_MSB 15
490 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
492 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
494 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
496 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
498 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
500 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
524 #define ALT_QSPI_CFG_ENAHBREMAP_E_DISABLE 0x0
530 #define ALT_QSPI_CFG_ENAHBREMAP_E_ENABLE 0x1
533 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
535 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
537 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
539 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
541 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
543 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
545 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
547 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
579 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DISABLE 0x0
585 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_ENABLE 0x1
588 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
590 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
592 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
594 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
596 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
598 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
600 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
602 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
633 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DISABLE 0x0
639 #define ALT_QSPI_CFG_ENTERXIPIMM_E_ENABLE 0x1
642 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
644 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
646 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
648 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
650 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
652 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
654 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
656 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
692 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
698 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
704 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
710 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
716 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
722 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
728 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
734 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
740 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
746 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
752 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
758 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
764 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
770 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
776 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
782 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
785 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
787 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
789 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
791 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
793 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
795 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
797 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
799 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
808 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_LSB 23
810 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_MSB 30
812 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_WIDTH 8
814 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_SET_MSK 0x7f800000
816 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_CLR_MSK 0x807fffff
818 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_RESET 0x0
820 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_GET(value) (((value) & 0x7f800000) >> 23)
822 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_SET(value) (((value) << 23) & 0x7f800000)
845 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
851 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
854 #define ALT_QSPI_CFG_IDLE_LSB 31
856 #define ALT_QSPI_CFG_IDLE_MSB 31
858 #define ALT_QSPI_CFG_IDLE_WIDTH 1
860 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
862 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
864 #define ALT_QSPI_CFG_IDLE_RESET 0x1
866 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
868 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
882 struct ALT_QSPI_CFG_s
884 volatile uint32_t en : 1;
885 volatile uint32_t selclkpol : 1;
886 volatile uint32_t selclkphase : 1;
887 const volatile uint32_t config_resv1_fld : 4;
888 volatile uint32_t endiracc : 1;
889 volatile uint32_t enlegacyip : 1;
890 volatile uint32_t perseldec : 1;
891 volatile uint32_t percslines : 4;
892 volatile uint32_t wp : 1;
893 volatile uint32_t endma : 1;
894 volatile uint32_t enahbremap : 1;
895 volatile uint32_t enterxipnextrd : 1;
896 volatile uint32_t enterxipimm : 1;
897 volatile uint32_t bauddiv : 4;
898 const volatile uint32_t config_resv2_fld : 8;
899 const volatile uint32_t idle : 1;
903 typedef struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
907 #define ALT_QSPI_CFG_RESET 0x80780000
909 #define ALT_QSPI_CFG_OFST 0x0
911 #define ALT_QSPI_CFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_CFG_OFST))
953 #define ALT_QSPI_DEVRD_RDOPCODE_E_READ 0x3
959 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTREAD 0xb
962 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
964 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
966 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
968 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
970 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
972 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
974 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
976 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
1007 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
1014 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
1021 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
1024 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
1026 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
1028 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
1030 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
1032 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
1034 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
1036 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
1038 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1047 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10
1049 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11
1051 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2
1053 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00
1055 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff
1057 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0
1059 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10)
1061 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00)
1095 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1103 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1111 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1114 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1116 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1118 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1120 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1122 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1124 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1126 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1128 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1137 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14
1139 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15
1141 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2
1143 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1145 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1147 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0
1149 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1151 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1187 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1195 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1203 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1206 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1208 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1210 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1212 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1214 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1216 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1218 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1220 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1229 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18
1231 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19
1233 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2
1235 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000
1237 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff
1239 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0
1241 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18)
1243 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000)
1266 #define ALT_QSPI_DEVRD_ENMODEBITS_E_NOORDER 0x0
1272 #define ALT_QSPI_DEVRD_ENMODEBITS_E_ORDER 0x1
1275 #define ALT_QSPI_DEVRD_ENMODEBITS_LSB 20
1277 #define ALT_QSPI_DEVRD_ENMODEBITS_MSB 20
1279 #define ALT_QSPI_DEVRD_ENMODEBITS_WIDTH 1
1281 #define ALT_QSPI_DEVRD_ENMODEBITS_SET_MSK 0x00100000
1283 #define ALT_QSPI_DEVRD_ENMODEBITS_CLR_MSK 0xffefffff
1285 #define ALT_QSPI_DEVRD_ENMODEBITS_RESET 0x0
1287 #define ALT_QSPI_DEVRD_ENMODEBITS_GET(value) (((value) & 0x00100000) >> 20)
1289 #define ALT_QSPI_DEVRD_ENMODEBITS_SET(value) (((value) << 20) & 0x00100000)
1298 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21
1300 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23
1302 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3
1304 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000
1306 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff
1308 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0
1310 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21)
1312 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000)
1323 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1325 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1327 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1329 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1331 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1333 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1335 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1337 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1346 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29
1348 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31
1350 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3
1352 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000
1354 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff
1356 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0
1358 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1360 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000)
1362 #ifndef __ASSEMBLY__
1374 struct ALT_QSPI_DEVRD_s
1376 volatile uint32_t rdopcode : 8;
1377 volatile uint32_t instwidth : 2;
1378 const volatile uint32_t rd_instr_resv1_fld : 2;
1379 volatile uint32_t addrwidth : 2;
1380 const volatile uint32_t rd_instr_resv2_fld : 2;
1381 volatile uint32_t datawidth : 2;
1382 const volatile uint32_t rd_instr_resv3_fld : 2;
1383 volatile uint32_t enmodebits : 1;
1384 const volatile uint32_t rd_instr_resv4_fld : 3;
1385 volatile uint32_t dummyrdclks : 5;
1386 const volatile uint32_t rd_instr_resv5_fld : 3;
1390 typedef struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1394 #define ALT_QSPI_DEVRD_RESET 0x00000003
1396 #define ALT_QSPI_DEVRD_OFST 0x4
1398 #define ALT_QSPI_DEVRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVRD_OFST))
1426 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1428 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1430 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1432 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1434 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1436 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1438 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1440 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1449 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8
1451 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11
1453 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4
1455 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00
1457 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff
1459 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0
1461 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8)
1463 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00)
1497 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1505 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1513 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1516 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1518 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1520 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1522 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1524 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1526 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1528 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1530 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1539 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14
1541 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15
1543 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2
1545 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1547 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1549 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0
1551 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1553 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1589 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1597 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1605 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1608 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1610 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1612 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1614 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1616 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1618 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1620 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1622 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1631 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18
1633 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23
1635 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6
1637 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000
1639 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff
1641 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0
1643 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18)
1645 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000)
1656 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1658 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1660 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1662 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1664 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1666 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1668 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1670 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1679 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29
1681 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31
1683 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3
1685 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000
1687 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff
1689 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0
1691 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1693 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000)
1695 #ifndef __ASSEMBLY__
1707 struct ALT_QSPI_DEVWR_s
1709 volatile uint32_t wropcode : 8;
1710 const volatile uint32_t wr_instr_resv1_fld : 4;
1711 volatile uint32_t addrwidth : 2;
1712 const volatile uint32_t wr_instr_resv2_fld : 2;
1713 volatile uint32_t datawidth : 2;
1714 const volatile uint32_t wr_instr_resv3_fld : 6;
1715 volatile uint32_t dummywrclks : 5;
1716 const volatile uint32_t wr_instr_resv4_fld : 3;
1720 typedef struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1724 #define ALT_QSPI_DEVWR_RESET 0x00000002
1726 #define ALT_QSPI_DEVWR_OFST 0x8
1728 #define ALT_QSPI_DEVWR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVWR_OFST))
1757 #define ALT_QSPI_DELAY_INIT_LSB 0
1759 #define ALT_QSPI_DELAY_INIT_MSB 7
1761 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1763 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1765 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1767 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1769 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1771 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1784 #define ALT_QSPI_DELAY_AFTER_LSB 8
1786 #define ALT_QSPI_DELAY_AFTER_MSB 15
1788 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1790 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1792 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1794 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1796 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1798 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1811 #define ALT_QSPI_DELAY_BTWN_LSB 16
1813 #define ALT_QSPI_DELAY_BTWN_MSB 23
1815 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1817 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1819 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1821 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1823 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1825 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1838 #define ALT_QSPI_DELAY_NSS_LSB 24
1840 #define ALT_QSPI_DELAY_NSS_MSB 31
1842 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1844 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1846 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1848 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1850 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1852 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1854 #ifndef __ASSEMBLY__
1866 struct ALT_QSPI_DELAY_s
1868 volatile uint32_t init : 8;
1869 volatile uint32_t after : 8;
1870 volatile uint32_t btwn : 8;
1871 volatile uint32_t nss : 8;
1875 typedef struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1879 #define ALT_QSPI_DELAY_RESET 0x00000000
1881 #define ALT_QSPI_DELAY_OFST 0xc
1883 #define ALT_QSPI_DELAY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DELAY_OFST))
1917 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x0
1923 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x1
1926 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1928 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1930 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1932 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1934 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1936 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1938 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1940 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1951 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1953 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1955 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1957 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1959 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1961 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1963 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1965 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1974 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_LSB 5
1976 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_MSB 31
1978 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_WIDTH 27
1980 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET_MSK 0xffffffe0
1982 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_CLR_MSK 0x0000001f
1984 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_RESET 0x0
1986 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_GET(value) (((value) & 0xffffffe0) >> 5)
1988 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET(value) (((value) << 5) & 0xffffffe0)
1990 #ifndef __ASSEMBLY__
2002 struct ALT_QSPI_RDDATACAP_s
2004 volatile uint32_t byp : 1;
2005 volatile uint32_t delay : 4;
2006 const volatile uint32_t rd_data_resv_fld : 27;
2010 typedef struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
2014 #define ALT_QSPI_RDDATACAP_RESET 0x00000001
2016 #define ALT_QSPI_RDDATACAP_OFST 0x10
2018 #define ALT_QSPI_RDDATACAP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_RDDATACAP_OFST))
2042 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
2044 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
2046 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
2048 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
2050 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
2052 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
2054 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2056 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
2068 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
2070 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
2072 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
2074 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
2076 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
2078 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
2080 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
2082 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
2095 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
2097 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
2099 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
2101 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
2103 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
2105 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
2107 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
2109 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
2118 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_LSB 21
2120 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_MSB 31
2122 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_WIDTH 11
2124 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET_MSK 0xffe00000
2126 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_CLR_MSK 0x001fffff
2128 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_RESET 0x0
2130 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_GET(value) (((value) & 0xffe00000) >> 21)
2132 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET(value) (((value) << 21) & 0xffe00000)
2134 #ifndef __ASSEMBLY__
2146 struct ALT_QSPI_DEVSZ_s
2148 volatile uint32_t numaddrbytes : 4;
2149 volatile uint32_t bytesperdevicepage : 12;
2150 volatile uint32_t bytespersubsector : 5;
2151 const volatile uint32_t dev_size_resv_fld : 11;
2155 typedef struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
2159 #define ALT_QSPI_DEVSZ_RESET 0x00101002
2161 #define ALT_QSPI_DEVSZ_OFST 0x14
2163 #define ALT_QSPI_DEVSZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVSZ_OFST))
2188 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
2190 #define ALT_QSPI_SRAMPART_ADDR_MSB 9
2192 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 10
2194 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x000003ff
2196 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xfffffc00
2198 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x80
2200 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2202 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2211 #define ALT_QSPI_SRAMPART_RESV_FLD_LSB 10
2213 #define ALT_QSPI_SRAMPART_RESV_FLD_MSB 31
2215 #define ALT_QSPI_SRAMPART_RESV_FLD_WIDTH 22
2217 #define ALT_QSPI_SRAMPART_RESV_FLD_SET_MSK 0xfffffc00
2219 #define ALT_QSPI_SRAMPART_RESV_FLD_CLR_MSK 0x000003ff
2221 #define ALT_QSPI_SRAMPART_RESV_FLD_RESET 0x0
2223 #define ALT_QSPI_SRAMPART_RESV_FLD_GET(value) (((value) & 0xfffffc00) >> 10)
2225 #define ALT_QSPI_SRAMPART_RESV_FLD_SET(value) (((value) << 10) & 0xfffffc00)
2227 #ifndef __ASSEMBLY__
2239 struct ALT_QSPI_SRAMPART_s
2241 volatile uint32_t addr : 10;
2242 const volatile uint32_t resv_fld : 22;
2246 typedef struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
2250 #define ALT_QSPI_SRAMPART_RESET 0x00000080
2252 #define ALT_QSPI_SRAMPART_OFST 0x18
2254 #define ALT_QSPI_SRAMPART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_SRAMPART_OFST))
2278 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
2280 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
2282 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
2284 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
2286 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
2288 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
2290 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2292 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2294 #ifndef __ASSEMBLY__
2306 struct ALT_QSPI_INDADDRTRIG_s
2308 volatile uint32_t addr : 32;
2312 typedef struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
2316 #define ALT_QSPI_INDADDRTRIG_RESET 0x00000000
2318 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
2320 #define ALT_QSPI_INDADDRTRIG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDADDRTRIG_OFST))
2347 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
2349 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
2351 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
2353 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
2355 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
2357 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
2359 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2361 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
2370 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_LSB 4
2372 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_MSB 7
2374 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_WIDTH 4
2376 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET_MSK 0x000000f0
2378 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_CLR_MSK 0xffffff0f
2380 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_RESET 0x0
2382 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_GET(value) (((value) & 0x000000f0) >> 4)
2384 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET(value) (((value) << 4) & 0x000000f0)
2398 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2400 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2402 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2404 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2406 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2408 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2410 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2412 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2421 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_LSB 12
2423 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_MSB 31
2425 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_WIDTH 20
2427 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET_MSK 0xfffff000
2429 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_CLR_MSK 0x00000fff
2431 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_RESET 0x0
2433 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_GET(value) (((value) & 0xfffff000) >> 12)
2435 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET(value) (((value) << 12) & 0xfffff000)
2437 #ifndef __ASSEMBLY__
2449 struct ALT_QSPI_DMAPER_s
2451 volatile uint32_t numsglreqbytes : 4;
2452 const volatile uint32_t dma_periph_resv1_fld : 4;
2453 volatile uint32_t numburstreqbytes : 4;
2454 const volatile uint32_t dma_periph_resv2_fld : 20;
2458 typedef struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2462 #define ALT_QSPI_DMAPER_RESET 0x00000000
2464 #define ALT_QSPI_DMAPER_OFST 0x20
2466 #define ALT_QSPI_DMAPER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DMAPER_OFST))
2488 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2490 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2492 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2494 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2496 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2498 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2500 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2502 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2504 #ifndef __ASSEMBLY__
2516 struct ALT_QSPI_REMAPADDR_s
2518 volatile uint32_t value : 32;
2522 typedef struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2526 #define ALT_QSPI_REMAPADDR_RESET 0x00000000
2528 #define ALT_QSPI_REMAPADDR_OFST 0x24
2530 #define ALT_QSPI_REMAPADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_REMAPADDR_OFST))
2553 #define ALT_QSPI_MODEBIT_MODE_LSB 0
2555 #define ALT_QSPI_MODEBIT_MODE_MSB 7
2557 #define ALT_QSPI_MODEBIT_MODE_WIDTH 8
2559 #define ALT_QSPI_MODEBIT_MODE_SET_MSK 0x000000ff
2561 #define ALT_QSPI_MODEBIT_MODE_CLR_MSK 0xffffff00
2563 #define ALT_QSPI_MODEBIT_MODE_RESET 0x0
2565 #define ALT_QSPI_MODEBIT_MODE_GET(value) (((value) & 0x000000ff) >> 0)
2567 #define ALT_QSPI_MODEBIT_MODE_SET(value) (((value) << 0) & 0x000000ff)
2576 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_LSB 8
2578 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_MSB 31
2580 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_WIDTH 24
2582 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_SET_MSK 0xffffff00
2584 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_CLR_MSK 0x000000ff
2586 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_RESET 0x0
2588 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2590 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2592 #ifndef __ASSEMBLY__
2604 struct ALT_QSPI_MODEBIT_s
2606 volatile uint32_t
mode : 8;
2607 const volatile uint32_t mode_resv_fld : 24;
2611 typedef struct ALT_QSPI_MODEBIT_s ALT_QSPI_MODEBIT_t;
2615 #define ALT_QSPI_MODEBIT_RESET 0x00000000
2617 #define ALT_QSPI_MODEBIT_OFST 0x28
2619 #define ALT_QSPI_MODEBIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_MODEBIT_OFST))
2641 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2643 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2645 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2647 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2649 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2651 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2653 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2655 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2666 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2668 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2670 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2672 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2674 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2676 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2678 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2680 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2682 #ifndef __ASSEMBLY__
2694 struct ALT_QSPI_SRAMFILL_s
2696 const volatile uint32_t indrdpart : 16;
2697 const volatile uint32_t indwrpart : 16;
2701 typedef struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2705 #define ALT_QSPI_SRAMFILL_RESET 0x00000000
2707 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2709 #define ALT_QSPI_SRAMFILL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_SRAMFILL_OFST))
2731 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2733 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2735 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2737 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2739 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2741 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2743 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2745 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2754 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_LSB 4
2756 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_MSB 31
2758 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_WIDTH 28
2760 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2762 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2764 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_RESET 0x0
2766 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2768 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2770 #ifndef __ASSEMBLY__
2782 struct ALT_QSPI_TXTHRESH_s
2784 volatile uint32_t level : 4;
2785 const volatile uint32_t tx_thresh_resv_fld : 28;
2789 typedef struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2793 #define ALT_QSPI_TXTHRESH_RESET 0x00000001
2795 #define ALT_QSPI_TXTHRESH_OFST 0x30
2797 #define ALT_QSPI_TXTHRESH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_TXTHRESH_OFST))
2821 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2823 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2825 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2827 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2829 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2831 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2833 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2835 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2844 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_LSB 4
2846 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_MSB 31
2848 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_WIDTH 28
2850 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2852 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2854 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_RESET 0x0
2856 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2858 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2860 #ifndef __ASSEMBLY__
2872 struct ALT_QSPI_RXTHRESH_s
2874 volatile uint32_t level : 4;
2875 const volatile uint32_t rx_thresh_resv_fld : 28;
2879 typedef struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2883 #define ALT_QSPI_RXTHRESH_RESET 0x00000001
2885 #define ALT_QSPI_RXTHRESH_OFST 0x34
2887 #define ALT_QSPI_RXTHRESH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_RXTHRESH_OFST))
2931 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_LSB 0
2933 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_MSB 0
2935 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_WIDTH 1
2937 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_SET_MSK 0x00000001
2939 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_CLR_MSK 0xfffffffe
2941 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_RESET 0x0
2943 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_GET(value) (((value) & 0x00000001) >> 0)
2945 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_SET(value) (((value) << 0) & 0x00000001)
2971 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2977 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2980 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2982 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2984 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2986 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2988 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2990 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2992 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2994 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3016 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
3022 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
3025 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
3027 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
3029 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
3031 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
3033 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
3035 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
3037 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3039 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3062 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
3068 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
3071 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
3073 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
3075 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
3077 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
3079 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
3081 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
3083 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3085 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3107 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRITEPROT 0x0
3113 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRITEPROT 0x1
3116 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
3118 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
3120 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
3122 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
3124 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
3126 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
3128 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3130 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3153 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
3159 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
3162 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
3164 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
3166 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
3168 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
3170 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
3172 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
3174 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3176 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3198 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
3204 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
3207 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
3209 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
3211 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
3213 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
3215 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
3217 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
3219 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3221 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3247 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
3253 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
3256 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
3258 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
3260 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
3262 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
3264 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
3266 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
3268 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3270 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3293 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
3299 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
3302 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
3304 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
3306 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
3308 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
3310 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
3312 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
3314 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3316 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3339 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
3345 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
3348 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
3350 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
3352 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
3354 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
3356 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
3358 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
3360 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3362 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3385 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
3391 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
3394 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
3396 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
3398 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
3400 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
3402 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
3404 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
3406 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3408 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3431 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
3437 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
3440 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
3442 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
3444 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
3446 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
3448 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
3450 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
3452 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3454 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3477 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
3483 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
3486 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
3488 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
3490 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
3492 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
3494 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
3496 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
3498 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3500 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3509 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_LSB 13
3511 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_MSB 31
3513 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_WIDTH 19
3515 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET_MSK 0xffffe000
3517 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_CLR_MSK 0x00001fff
3519 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_RESET 0x0
3521 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
3523 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
3525 #ifndef __ASSEMBLY__
3537 struct ALT_QSPI_IRQSTAT_s
3539 volatile uint32_t mode_m_fail_fld : 1;
3540 volatile uint32_t underflowdet : 1;
3541 volatile uint32_t indopdone : 1;
3542 volatile uint32_t indrdreject : 1;
3543 volatile uint32_t protwrattempt : 1;
3544 volatile uint32_t illegalacc : 1;
3545 volatile uint32_t indxfrlvl : 1;
3546 volatile uint32_t rxover : 1;
3547 volatile uint32_t txthreshcmp : 1;
3548 volatile uint32_t txfull : 1;
3549 volatile uint32_t rxthreshcmp : 1;
3550 volatile uint32_t rxfull : 1;
3551 volatile uint32_t indsramfull : 1;
3552 const volatile uint32_t irq_stat_resv_fld : 19;
3556 typedef struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
3560 #define ALT_QSPI_IRQSTAT_RESET 0x00000100
3562 #define ALT_QSPI_IRQSTAT_OFST 0x40
3564 #define ALT_QSPI_IRQSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_IRQSTAT_OFST))
3600 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_LSB 0
3602 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_MSB 0
3604 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_WIDTH 1
3606 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_SET_MSK 0x00000001
3608 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_CLR_MSK 0xfffffffe
3610 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_RESET 0x0
3612 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_GET(value) (((value) & 0x00000001) >> 0)
3614 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_SET(value) (((value) << 0) & 0x00000001)
3634 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_E_DISABLED 0x0
3640 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_E_ENABLED 0x1
3643 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_LSB 1
3645 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_MSB 1
3647 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_WIDTH 1
3649 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_SET_MSK 0x00000002
3651 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3653 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_RESET 0x0
3655 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3657 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3677 #define ALT_QSPI_IRQMASK_INDOPDONE_E_DISABLED 0x0
3683 #define ALT_QSPI_IRQMASK_INDOPDONE_E_ENABLED 0x1
3686 #define ALT_QSPI_IRQMASK_INDOPDONE_LSB 2
3688 #define ALT_QSPI_IRQMASK_INDOPDONE_MSB 2
3690 #define ALT_QSPI_IRQMASK_INDOPDONE_WIDTH 1
3692 #define ALT_QSPI_IRQMASK_INDOPDONE_SET_MSK 0x00000004
3694 #define ALT_QSPI_IRQMASK_INDOPDONE_CLR_MSK 0xfffffffb
3696 #define ALT_QSPI_IRQMASK_INDOPDONE_RESET 0x0
3698 #define ALT_QSPI_IRQMASK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3700 #define ALT_QSPI_IRQMASK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3720 #define ALT_QSPI_IRQMASK_INDRDREJECT_E_DISABLED 0x0
3726 #define ALT_QSPI_IRQMASK_INDRDREJECT_E_ENABLED 0x1
3729 #define ALT_QSPI_IRQMASK_INDRDREJECT_LSB 3
3731 #define ALT_QSPI_IRQMASK_INDRDREJECT_MSB 3
3733 #define ALT_QSPI_IRQMASK_INDRDREJECT_WIDTH 1
3735 #define ALT_QSPI_IRQMASK_INDRDREJECT_SET_MSK 0x00000008
3737 #define ALT_QSPI_IRQMASK_INDRDREJECT_CLR_MSK 0xfffffff7
3739 #define ALT_QSPI_IRQMASK_INDRDREJECT_RESET 0x0
3741 #define ALT_QSPI_IRQMASK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3743 #define ALT_QSPI_IRQMASK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3763 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_DISABLED 0x0
3769 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_ENABLED 0x1
3772 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_LSB 4
3774 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_MSB 4
3776 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_WIDTH 1
3778 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_SET_MSK 0x00000010
3780 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3782 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_RESET 0x0
3784 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3786 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3806 #define ALT_QSPI_IRQMASK_ILLEGALACC_E_DISABLED 0x0
3812 #define ALT_QSPI_IRQMASK_ILLEGALACC_E_ENABLED 0x1
3815 #define ALT_QSPI_IRQMASK_ILLEGALACC_LSB 5
3817 #define ALT_QSPI_IRQMASK_ILLEGALACC_MSB 5
3819 #define ALT_QSPI_IRQMASK_ILLEGALACC_WIDTH 1
3821 #define ALT_QSPI_IRQMASK_ILLEGALACC_SET_MSK 0x00000020
3823 #define ALT_QSPI_IRQMASK_ILLEGALACC_CLR_MSK 0xffffffdf
3825 #define ALT_QSPI_IRQMASK_ILLEGALACC_RESET 0x0
3827 #define ALT_QSPI_IRQMASK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3829 #define ALT_QSPI_IRQMASK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3849 #define ALT_QSPI_IRQMASK_INDXFRLVL_E_DISABLED 0x0
3855 #define ALT_QSPI_IRQMASK_INDXFRLVL_E_ENABLED 0x1
3858 #define ALT_QSPI_IRQMASK_INDXFRLVL_LSB 6
3860 #define ALT_QSPI_IRQMASK_INDXFRLVL_MSB 6
3862 #define ALT_QSPI_IRQMASK_INDXFRLVL_WIDTH 1
3864 #define ALT_QSPI_IRQMASK_INDXFRLVL_SET_MSK 0x00000040
3866 #define ALT_QSPI_IRQMASK_INDXFRLVL_CLR_MSK 0xffffffbf
3868 #define ALT_QSPI_IRQMASK_INDXFRLVL_RESET 0x0
3870 #define ALT_QSPI_IRQMASK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3872 #define ALT_QSPI_IRQMASK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3892 #define ALT_QSPI_IRQMASK_RXOVER_E_DISABLED 0x0
3898 #define ALT_QSPI_IRQMASK_RXOVER_E_ENABLED 0x1
3901 #define ALT_QSPI_IRQMASK_RXOVER_LSB 7
3903 #define ALT_QSPI_IRQMASK_RXOVER_MSB 7
3905 #define ALT_QSPI_IRQMASK_RXOVER_WIDTH 1
3907 #define ALT_QSPI_IRQMASK_RXOVER_SET_MSK 0x00000080
3909 #define ALT_QSPI_IRQMASK_RXOVER_CLR_MSK 0xffffff7f
3911 #define ALT_QSPI_IRQMASK_RXOVER_RESET 0x0
3913 #define ALT_QSPI_IRQMASK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3915 #define ALT_QSPI_IRQMASK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3935 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_E_DISABLED 0x0
3941 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_E_ENABLED 0x1
3944 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_LSB 8
3946 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_MSB 8
3948 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_WIDTH 1
3950 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_SET_MSK 0x00000100
3952 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3954 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_RESET 0x0
3956 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3958 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3978 #define ALT_QSPI_IRQMASK_TXFULL_E_DISABLED 0x0
3984 #define ALT_QSPI_IRQMASK_TXFULL_E_ENABLED 0x1
3987 #define ALT_QSPI_IRQMASK_TXFULL_LSB 9
3989 #define ALT_QSPI_IRQMASK_TXFULL_MSB 9
3991 #define ALT_QSPI_IRQMASK_TXFULL_WIDTH 1
3993 #define ALT_QSPI_IRQMASK_TXFULL_SET_MSK 0x00000200
3995 #define ALT_QSPI_IRQMASK_TXFULL_CLR_MSK 0xfffffdff
3997 #define ALT_QSPI_IRQMASK_TXFULL_RESET 0x0
3999 #define ALT_QSPI_IRQMASK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
4001 #define ALT_QSPI_IRQMASK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
4021 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_E_DISABLED 0x0
4027 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_E_ENABLED 0x1
4030 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_LSB 10
4032 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_MSB 10
4034 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_WIDTH 1
4036 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_SET_MSK 0x00000400
4038 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_CLR_MSK 0xfffffbff
4040 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_RESET 0x0
4042 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
4044 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
4064 #define ALT_QSPI_IRQMASK_RXFULL_E_DISABLED 0x0
4070 #define ALT_QSPI_IRQMASK_RXFULL_E_ENABLED 0x1
4073 #define ALT_QSPI_IRQMASK_RXFULL_LSB 11
4075 #define ALT_QSPI_IRQMASK_RXFULL_MSB 11
4077 #define ALT_QSPI_IRQMASK_RXFULL_WIDTH 1
4079 #define ALT_QSPI_IRQMASK_RXFULL_SET_MSK 0x00000800
4081 #define ALT_QSPI_IRQMASK_RXFULL_CLR_MSK 0xfffff7ff
4083 #define ALT_QSPI_IRQMASK_RXFULL_RESET 0x0
4085 #define ALT_QSPI_IRQMASK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
4087 #define ALT_QSPI_IRQMASK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
4107 #define ALT_QSPI_IRQMASK_INDSRAMFULL_E_DISABLED 0x0
4113 #define ALT_QSPI_IRQMASK_INDSRAMFULL_E_ENABLED 0x1
4116 #define ALT_QSPI_IRQMASK_INDSRAMFULL_LSB 12
4118 #define ALT_QSPI_IRQMASK_INDSRAMFULL_MSB 12
4120 #define ALT_QSPI_IRQMASK_INDSRAMFULL_WIDTH 1
4122 #define ALT_QSPI_IRQMASK_INDSRAMFULL_SET_MSK 0x00001000
4124 #define ALT_QSPI_IRQMASK_INDSRAMFULL_CLR_MSK 0xffffefff
4126 #define ALT_QSPI_IRQMASK_INDSRAMFULL_RESET 0x0
4128 #define ALT_QSPI_IRQMASK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
4130 #define ALT_QSPI_IRQMASK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
4139 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_LSB 13
4141 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_MSB 31
4143 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_WIDTH 19
4145 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_SET_MSK 0xffffe000
4147 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_CLR_MSK 0x00001fff
4149 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_RESET 0x0
4151 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
4153 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
4155 #ifndef __ASSEMBLY__
4167 struct ALT_QSPI_IRQMASK_s
4169 volatile uint32_t mode_m_fail_mask_fld : 1;
4170 volatile uint32_t underflowdet : 1;
4171 volatile uint32_t indopdone : 1;
4172 volatile uint32_t indrdreject : 1;
4173 volatile uint32_t protwrattempt : 1;
4174 volatile uint32_t illegalacc : 1;
4175 volatile uint32_t indxfrlvl : 1;
4176 volatile uint32_t rxover : 1;
4177 volatile uint32_t txthreshcmp : 1;
4178 volatile uint32_t txfull : 1;
4179 volatile uint32_t rxthreshcmp : 1;
4180 volatile uint32_t rxfull : 1;
4181 volatile uint32_t indsramfull : 1;
4182 const volatile uint32_t irq_mask_resv_fld : 19;
4186 typedef struct ALT_QSPI_IRQMASK_s ALT_QSPI_IRQMASK_t;
4190 #define ALT_QSPI_IRQMASK_RESET 0x00000000
4192 #define ALT_QSPI_IRQMASK_OFST 0x44
4194 #define ALT_QSPI_IRQMASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_IRQMASK_OFST))
4217 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
4219 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
4221 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
4223 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4225 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4227 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
4229 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4231 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4233 #ifndef __ASSEMBLY__
4245 struct ALT_QSPI_LOWWRPROT_s
4247 volatile uint32_t subsector : 32;
4251 typedef struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
4255 #define ALT_QSPI_LOWWRPROT_RESET 0x00000000
4257 #define ALT_QSPI_LOWWRPROT_OFST 0x50
4259 #define ALT_QSPI_LOWWRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_LOWWRPROT_OFST))
4282 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
4284 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
4286 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
4288 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4290 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4292 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
4294 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4296 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4298 #ifndef __ASSEMBLY__
4310 struct ALT_QSPI_UPPWRPROT_s
4312 volatile uint32_t subsector : 32;
4316 typedef struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
4320 #define ALT_QSPI_UPPWRPROT_RESET 0x00000000
4322 #define ALT_QSPI_UPPWRPROT_OFST 0x54
4324 #define ALT_QSPI_UPPWRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_UPPWRPROT_OFST))
4362 #define ALT_QSPI_WRPROT_INV_E_DISABLE 0x0
4368 #define ALT_QSPI_WRPROT_INV_E_ENABLE 0x1
4371 #define ALT_QSPI_WRPROT_INV_LSB 0
4373 #define ALT_QSPI_WRPROT_INV_MSB 0
4375 #define ALT_QSPI_WRPROT_INV_WIDTH 1
4377 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
4379 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
4381 #define ALT_QSPI_WRPROT_INV_RESET 0x0
4383 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
4385 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
4410 #define ALT_QSPI_WRPROT_EN_E_DISABLE 0x0
4416 #define ALT_QSPI_WRPROT_EN_E_ENABLE 0x1
4419 #define ALT_QSPI_WRPROT_EN_LSB 1
4421 #define ALT_QSPI_WRPROT_EN_MSB 1
4423 #define ALT_QSPI_WRPROT_EN_WIDTH 1
4425 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
4427 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
4429 #define ALT_QSPI_WRPROT_EN_RESET 0x0
4431 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
4433 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
4442 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_LSB 2
4444 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_MSB 31
4446 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_WIDTH 30
4448 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_SET_MSK 0xfffffffc
4450 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_CLR_MSK 0x00000003
4452 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_RESET 0x0
4454 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_GET(value) (((value) & 0xfffffffc) >> 2)
4456 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_SET(value) (((value) << 2) & 0xfffffffc)
4458 #ifndef __ASSEMBLY__
4470 struct ALT_QSPI_WRPROT_s
4472 volatile uint32_t inv : 1;
4473 volatile uint32_t en : 1;
4474 const volatile uint32_t wr_prot_ctrl_resv_fld : 30;
4478 typedef struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
4482 #define ALT_QSPI_WRPROT_RESET 0x00000000
4484 #define ALT_QSPI_WRPROT_OFST 0x58
4486 #define ALT_QSPI_WRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_WRPROT_OFST))
4527 #define ALT_QSPI_INDRD_START_E_DISABLED 0x0
4533 #define ALT_QSPI_INDRD_START_E_ENABLED 0x1
4536 #define ALT_QSPI_INDRD_START_LSB 0
4538 #define ALT_QSPI_INDRD_START_MSB 0
4540 #define ALT_QSPI_INDRD_START_WIDTH 1
4542 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
4544 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
4546 #define ALT_QSPI_INDRD_START_RESET 0x0
4548 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
4550 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
4572 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
4578 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
4581 #define ALT_QSPI_INDRD_CANCEL_LSB 1
4583 #define ALT_QSPI_INDRD_CANCEL_MSB 1
4585 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
4587 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
4589 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
4591 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
4593 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4595 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4617 #define ALT_QSPI_INDRD_RD_STATUS_E_NOACTION 0x0
4623 #define ALT_QSPI_INDRD_RD_STATUS_E_READOP 0x1
4626 #define ALT_QSPI_INDRD_RD_STATUS_LSB 2
4628 #define ALT_QSPI_INDRD_RD_STATUS_MSB 2
4630 #define ALT_QSPI_INDRD_RD_STATUS_WIDTH 1
4632 #define ALT_QSPI_INDRD_RD_STATUS_SET_MSK 0x00000004
4634 #define ALT_QSPI_INDRD_RD_STATUS_CLR_MSK 0xfffffffb
4636 #define ALT_QSPI_INDRD_RD_STATUS_RESET 0x0
4638 #define ALT_QSPI_INDRD_RD_STATUS_GET(value) (((value) & 0x00000004) >> 2)
4640 #define ALT_QSPI_INDRD_RD_STATUS_SET(value) (((value) << 2) & 0x00000004)
4663 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4669 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4672 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4674 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4676 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4678 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4680 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4682 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4684 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4686 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4708 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4714 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4717 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4719 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4721 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4723 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4725 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4727 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4729 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4731 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4754 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_NOACTION 0x0
4760 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_INDCOMP 0x1
4763 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_LSB 5
4765 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_MSB 5
4767 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_WIDTH 1
4769 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_SET_MSK 0x00000020
4771 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_CLR_MSK 0xffffffdf
4773 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_RESET 0x0
4775 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_GET(value) (((value) & 0x00000020) >> 5)
4777 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_SET(value) (((value) << 5) & 0x00000020)
4791 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4793 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4795 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4797 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4799 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4801 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4803 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4805 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4814 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_LSB 8
4816 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_MSB 31
4818 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_WIDTH 24
4820 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET_MSK 0xffffff00
4822 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_CLR_MSK 0x000000ff
4824 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_RESET 0x0
4826 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
4828 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
4830 #ifndef __ASSEMBLY__
4842 struct ALT_QSPI_INDRD_s
4844 volatile uint32_t start : 1;
4845 volatile uint32_t cancel : 1;
4846 const volatile uint32_t rd_status : 1;
4847 volatile uint32_t sram_full : 1;
4848 const volatile uint32_t rd_queued : 1;
4849 volatile uint32_t ind_ops_done_status : 1;
4850 const volatile uint32_t num_ind_ops_done : 2;
4851 const volatile uint32_t indir_rd_xfer_resv_fld : 24;
4855 typedef struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4859 #define ALT_QSPI_INDRD_RESET 0x00000000
4861 #define ALT_QSPI_INDRD_OFST 0x60
4863 #define ALT_QSPI_INDRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRD_OFST))
4886 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4888 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4890 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4892 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4894 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4896 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4898 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4900 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4902 #ifndef __ASSEMBLY__
4914 struct ALT_QSPI_INDRDWATER_s
4916 volatile uint32_t level : 32;
4920 typedef struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4924 #define ALT_QSPI_INDRDWATER_RESET 0x00000000
4926 #define ALT_QSPI_INDRDWATER_OFST 0x64
4928 #define ALT_QSPI_INDRDWATER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDWATER_OFST))
4950 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4952 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4954 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4956 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4958 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4960 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4962 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4964 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4966 #ifndef __ASSEMBLY__
4978 struct ALT_QSPI_INDRDSTADDR_s
4980 volatile uint32_t addr : 32;
4984 typedef struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4988 #define ALT_QSPI_INDRDSTADDR_RESET 0x00000000
4990 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4992 #define ALT_QSPI_INDRDSTADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDSTADDR_OFST))
5014 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
5016 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
5018 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
5020 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
5022 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
5024 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
5026 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5028 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5030 #ifndef __ASSEMBLY__
5042 struct ALT_QSPI_INDRDCNT_s
5044 volatile uint32_t value : 32;
5048 typedef struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
5052 #define ALT_QSPI_INDRDCNT_RESET 0x00000000
5054 #define ALT_QSPI_INDRDCNT_OFST 0x6c
5056 #define ALT_QSPI_INDRDCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDCNT_OFST))
5097 #define ALT_QSPI_INDWR_START_E_DISABLED 0x0
5103 #define ALT_QSPI_INDWR_START_E_ENABLED 0x1
5106 #define ALT_QSPI_INDWR_START_LSB 0
5108 #define ALT_QSPI_INDWR_START_MSB 0
5110 #define ALT_QSPI_INDWR_START_WIDTH 1
5112 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
5114 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
5116 #define ALT_QSPI_INDWR_START_RESET 0x0
5118 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
5120 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
5142 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
5148 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
5151 #define ALT_QSPI_INDWR_CANCEL_LSB 1
5153 #define ALT_QSPI_INDWR_CANCEL_MSB 1
5155 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
5157 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
5159 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
5161 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
5163 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
5165 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
5187 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
5193 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
5196 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
5198 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
5200 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
5202 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
5204 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
5206 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
5208 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
5210 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
5219 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_LSB 3
5221 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_MSB 3
5223 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_WIDTH 1
5225 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET_MSK 0x00000008
5227 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_CLR_MSK 0xfffffff7
5229 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_RESET 0x0
5231 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_GET(value) (((value) & 0x00000008) >> 3)
5233 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET(value) (((value) << 3) & 0x00000008)
5255 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
5261 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
5264 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
5266 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
5268 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
5270 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
5272 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
5274 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
5276 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
5278 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
5301 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
5307 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
5310 #define ALT_QSPI_INDWR_INDDONE_LSB 5
5312 #define ALT_QSPI_INDWR_INDDONE_MSB 5
5314 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
5316 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
5318 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
5320 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
5322 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
5324 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
5338 #define ALT_QSPI_INDWR_INDCNT_LSB 6
5340 #define ALT_QSPI_INDWR_INDCNT_MSB 7
5342 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
5344 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
5346 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
5348 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
5350 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
5352 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
5361 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_LSB 8
5363 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_MSB 31
5365 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_WIDTH 24
5367 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET_MSK 0xffffff00
5369 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_CLR_MSK 0x000000ff
5371 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_RESET 0x0
5373 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_GET(value) (((value) & 0xffffff00) >> 8)
5375 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET(value) (((value) << 8) & 0xffffff00)
5377 #ifndef __ASSEMBLY__
5389 struct ALT_QSPI_INDWR_s
5391 volatile uint32_t start : 1;
5392 volatile uint32_t cancel : 1;
5393 const volatile uint32_t rdstat : 1;
5394 const volatile uint32_t indir_wr_rsvd_fld : 1;
5395 const volatile uint32_t rdqueued : 1;
5396 volatile uint32_t inddone : 1;
5397 const volatile uint32_t indcnt : 2;
5398 const volatile uint32_t indir_wr_xfer_resv2_fld : 24;
5402 typedef struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
5406 #define ALT_QSPI_INDWR_RESET 0x00000000
5408 #define ALT_QSPI_INDWR_OFST 0x70
5410 #define ALT_QSPI_INDWR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWR_OFST))
5434 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
5436 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
5438 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
5440 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
5442 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
5444 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
5446 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
5448 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
5450 #ifndef __ASSEMBLY__
5462 struct ALT_QSPI_INDWRWATER_s
5464 volatile uint32_t level : 32;
5468 typedef struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
5472 #define ALT_QSPI_INDWRWATER_RESET 0xffffffff
5474 #define ALT_QSPI_INDWRWATER_OFST 0x74
5476 #define ALT_QSPI_INDWRWATER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRWATER_OFST))
5498 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
5500 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
5502 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
5504 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
5506 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
5508 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
5510 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5512 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5514 #ifndef __ASSEMBLY__
5526 struct ALT_QSPI_INDWRSTADDR_s
5528 volatile uint32_t addr : 32;
5532 typedef struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
5536 #define ALT_QSPI_INDWRSTADDR_RESET 0x00000000
5538 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
5540 #define ALT_QSPI_INDWRSTADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRSTADDR_OFST))
5562 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
5564 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
5566 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
5568 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
5570 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
5572 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
5574 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5576 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5578 #ifndef __ASSEMBLY__
5590 struct ALT_QSPI_INDWRCNT_s
5592 volatile uint32_t value : 32;
5596 typedef struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
5600 #define ALT_QSPI_INDWRCNT_RESET 0x00000000
5602 #define ALT_QSPI_INDWRCNT_OFST 0x7c
5604 #define ALT_QSPI_INDWRCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRCNT_OFST))
5647 #define ALT_QSPI_FLASHCMD_EXECCMD_E_NOACTION 0x0
5653 #define ALT_QSPI_FLASHCMD_EXECCMD_E_EXECUTE 0x1
5656 #define ALT_QSPI_FLASHCMD_EXECCMD_LSB 0
5658 #define ALT_QSPI_FLASHCMD_EXECCMD_MSB 0
5660 #define ALT_QSPI_FLASHCMD_EXECCMD_WIDTH 1
5662 #define ALT_QSPI_FLASHCMD_EXECCMD_SET_MSK 0x00000001
5664 #define ALT_QSPI_FLASHCMD_EXECCMD_CLR_MSK 0xfffffffe
5666 #define ALT_QSPI_FLASHCMD_EXECCMD_RESET 0x0
5668 #define ALT_QSPI_FLASHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
5670 #define ALT_QSPI_FLASHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
5692 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_NOACTION 0x0
5698 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
5701 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_LSB 1
5703 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_MSB 1
5705 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_WIDTH 1
5707 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_SET_MSK 0x00000002
5709 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
5711 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_RESET 0x0
5713 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
5715 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
5724 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_LSB 2
5726 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_MSB 6
5728 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_WIDTH 5
5730 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_SET_MSK 0x0000007c
5732 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_CLR_MSK 0xffffff83
5734 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_RESET 0x0
5736 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_GET(value) (((value) & 0x0000007c) >> 2)
5738 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_SET(value) (((value) << 2) & 0x0000007c)
5750 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_LSB 7
5752 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_MSB 11
5754 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_WIDTH 5
5756 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
5758 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
5760 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_RESET 0x0
5762 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
5764 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5793 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5799 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5805 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5811 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5817 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5823 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5829 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5835 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5838 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_LSB 12
5840 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_MSB 14
5842 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_WIDTH 3
5844 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5846 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5848 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_RESET 0x0
5850 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5852 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5875 #define ALT_QSPI_FLASHCMD_ENWRDATA_E_NOACTION 0x0
5881 #define ALT_QSPI_FLASHCMD_ENWRDATA_E_WRDATABYTES 0x1
5884 #define ALT_QSPI_FLASHCMD_ENWRDATA_LSB 15
5886 #define ALT_QSPI_FLASHCMD_ENWRDATA_MSB 15
5888 #define ALT_QSPI_FLASHCMD_ENWRDATA_WIDTH 1
5890 #define ALT_QSPI_FLASHCMD_ENWRDATA_SET_MSK 0x00008000
5892 #define ALT_QSPI_FLASHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5894 #define ALT_QSPI_FLASHCMD_ENWRDATA_RESET 0x0
5896 #define ALT_QSPI_FLASHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5898 #define ALT_QSPI_FLASHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5925 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5931 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5937 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5943 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5946 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_LSB 16
5948 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_MSB 17
5950 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_WIDTH 2
5952 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5954 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5956 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_RESET 0x0
5958 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5960 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5983 #define ALT_QSPI_FLASHCMD_ENMODEBIT_E_DISABLED 0x0
5989 #define ALT_QSPI_FLASHCMD_ENMODEBIT_E_ENABLED 0x1
5992 #define ALT_QSPI_FLASHCMD_ENMODEBIT_LSB 18
5994 #define ALT_QSPI_FLASHCMD_ENMODEBIT_MSB 18
5996 #define ALT_QSPI_FLASHCMD_ENMODEBIT_WIDTH 1
5998 #define ALT_QSPI_FLASHCMD_ENMODEBIT_SET_MSK 0x00040000
6000 #define ALT_QSPI_FLASHCMD_ENMODEBIT_CLR_MSK 0xfffbffff
6002 #define ALT_QSPI_FLASHCMD_ENMODEBIT_RESET 0x0
6004 #define ALT_QSPI_FLASHCMD_ENMODEBIT_GET(value) (((value) & 0x00040000) >> 18)
6006 #define ALT_QSPI_FLASHCMD_ENMODEBIT_SET(value) (((value) << 18) & 0x00040000)
6029 #define ALT_QSPI_FLASHCMD_ENCMDADDR_E_DISABLED 0x0
6035 #define ALT_QSPI_FLASHCMD_ENCMDADDR_E_ENABLED 0x1
6038 #define ALT_QSPI_FLASHCMD_ENCMDADDR_LSB 19
6040 #define ALT_QSPI_FLASHCMD_ENCMDADDR_MSB 19
6042 #define ALT_QSPI_FLASHCMD_ENCMDADDR_WIDTH 1
6044 #define ALT_QSPI_FLASHCMD_ENCMDADDR_SET_MSK 0x00080000
6046 #define ALT_QSPI_FLASHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
6048 #define ALT_QSPI_FLASHCMD_ENCMDADDR_RESET 0x0
6050 #define ALT_QSPI_FLASHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
6052 #define ALT_QSPI_FLASHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
6081 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
6087 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
6093 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
6099 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
6105 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
6111 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
6117 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
6123 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
6126 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_LSB 20
6128 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_MSB 22
6130 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_WIDTH 3
6132 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
6134 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
6136 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_RESET 0x0
6138 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
6140 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
6163 #define ALT_QSPI_FLASHCMD_ENRDDATA_E_NOACTION 0x0
6169 #define ALT_QSPI_FLASHCMD_ENRDDATA_E_ENABLE 0x1
6172 #define ALT_QSPI_FLASHCMD_ENRDDATA_LSB 23
6174 #define ALT_QSPI_FLASHCMD_ENRDDATA_MSB 23
6176 #define ALT_QSPI_FLASHCMD_ENRDDATA_WIDTH 1
6178 #define ALT_QSPI_FLASHCMD_ENRDDATA_SET_MSK 0x00800000
6180 #define ALT_QSPI_FLASHCMD_ENRDDATA_CLR_MSK 0xff7fffff
6182 #define ALT_QSPI_FLASHCMD_ENRDDATA_RESET 0x0
6184 #define ALT_QSPI_FLASHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
6186 #define ALT_QSPI_FLASHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
6207 #define ALT_QSPI_FLASHCMD_CMDOPCODE_LSB 24
6209 #define ALT_QSPI_FLASHCMD_CMDOPCODE_MSB 31
6211 #define ALT_QSPI_FLASHCMD_CMDOPCODE_WIDTH 8
6213 #define ALT_QSPI_FLASHCMD_CMDOPCODE_SET_MSK 0xff000000
6215 #define ALT_QSPI_FLASHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
6217 #define ALT_QSPI_FLASHCMD_CMDOPCODE_RESET 0x0
6219 #define ALT_QSPI_FLASHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
6221 #define ALT_QSPI_FLASHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
6223 #ifndef __ASSEMBLY__
6235 struct ALT_QSPI_FLASHCMD_s
6237 volatile uint32_t execcmd : 1;
6238 const volatile uint32_t cmdexecstat : 1;
6239 const volatile uint32_t flash_cmd_cntrl_resv1_fld : 5;
6240 volatile uint32_t numdummybytes : 5;
6241 volatile uint32_t numwrdatabytes : 3;
6242 volatile uint32_t enwrdata : 1;
6243 volatile uint32_t numaddrbytes : 2;
6244 volatile uint32_t enmodebit : 1;
6245 volatile uint32_t encmdaddr : 1;
6246 volatile uint32_t numrddatabytes : 3;
6247 volatile uint32_t enrddata : 1;
6248 volatile uint32_t cmdopcode : 8;
6252 typedef struct ALT_QSPI_FLASHCMD_s ALT_QSPI_FLASHCMD_t;
6256 #define ALT_QSPI_FLASHCMD_RESET 0x00000000
6258 #define ALT_QSPI_FLASHCMD_OFST 0x90
6260 #define ALT_QSPI_FLASHCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMD_OFST))
6284 #define ALT_QSPI_FLASHCMDADDR_ADDR_LSB 0
6286 #define ALT_QSPI_FLASHCMDADDR_ADDR_MSB 31
6288 #define ALT_QSPI_FLASHCMDADDR_ADDR_WIDTH 32
6290 #define ALT_QSPI_FLASHCMDADDR_ADDR_SET_MSK 0xffffffff
6292 #define ALT_QSPI_FLASHCMDADDR_ADDR_CLR_MSK 0x00000000
6294 #define ALT_QSPI_FLASHCMDADDR_ADDR_RESET 0x0
6296 #define ALT_QSPI_FLASHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
6298 #define ALT_QSPI_FLASHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
6300 #ifndef __ASSEMBLY__
6312 struct ALT_QSPI_FLASHCMDADDR_s
6314 volatile uint32_t addr : 32;
6318 typedef struct ALT_QSPI_FLASHCMDADDR_s ALT_QSPI_FLASHCMDADDR_t;
6322 #define ALT_QSPI_FLASHCMDADDR_RESET 0x00000000
6324 #define ALT_QSPI_FLASHCMDADDR_OFST 0x94
6326 #define ALT_QSPI_FLASHCMDADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDADDR_OFST))
6350 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_LSB 0
6352 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_MSB 31
6354 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_WIDTH 32
6356 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_SET_MSK 0xffffffff
6358 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_CLR_MSK 0x00000000
6360 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_RESET 0x0
6362 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6364 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6366 #ifndef __ASSEMBLY__
6378 struct ALT_QSPI_FLASHCMDRDDATALO_s
6380 volatile uint32_t data : 32;
6384 typedef struct ALT_QSPI_FLASHCMDRDDATALO_s ALT_QSPI_FLASHCMDRDDATALO_t;
6388 #define ALT_QSPI_FLASHCMDRDDATALO_RESET 0x00000000
6390 #define ALT_QSPI_FLASHCMDRDDATALO_OFST 0xa0
6392 #define ALT_QSPI_FLASHCMDRDDATALO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDRDDATALO_OFST))
6418 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_LSB 0
6420 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_MSB 31
6422 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_WIDTH 32
6424 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
6426 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
6428 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_RESET 0x0
6430 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6432 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6434 #ifndef __ASSEMBLY__
6446 struct ALT_QSPI_FLASHCMDRDDATAUP_s
6448 volatile uint32_t data : 32;
6452 typedef struct ALT_QSPI_FLASHCMDRDDATAUP_s ALT_QSPI_FLASHCMDRDDATAUP_t;
6456 #define ALT_QSPI_FLASHCMDRDDATAUP_RESET 0x00000000
6458 #define ALT_QSPI_FLASHCMDRDDATAUP_OFST 0xa4
6460 #define ALT_QSPI_FLASHCMDRDDATAUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDRDDATAUP_OFST))
6485 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_LSB 0
6487 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_MSB 31
6489 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_WIDTH 32
6491 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_SET_MSK 0xffffffff
6493 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_CLR_MSK 0x00000000
6495 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_RESET 0x0
6497 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6499 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6501 #ifndef __ASSEMBLY__
6513 struct ALT_QSPI_FLASHCMDWRDATALO_s
6515 volatile uint32_t data : 32;
6519 typedef struct ALT_QSPI_FLASHCMDWRDATALO_s ALT_QSPI_FLASHCMDWRDATALO_t;
6523 #define ALT_QSPI_FLASHCMDWRDATALO_RESET 0x00000000
6525 #define ALT_QSPI_FLASHCMDWRDATALO_OFST 0xa8
6527 #define ALT_QSPI_FLASHCMDWRDATALO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDWRDATALO_OFST))
6552 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_LSB 0
6554 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_MSB 31
6556 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_WIDTH 32
6558 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
6560 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
6562 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_RESET 0x0
6564 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6566 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6568 #ifndef __ASSEMBLY__
6580 struct ALT_QSPI_FLASHCMDWRDATAUP_s
6582 volatile uint32_t data : 32;
6586 typedef struct ALT_QSPI_FLASHCMDWRDATAUP_s ALT_QSPI_FLASHCMDWRDATAUP_t;
6590 #define ALT_QSPI_FLASHCMDWRDATAUP_RESET 0x00000000
6592 #define ALT_QSPI_FLASHCMDWRDATAUP_OFST 0xac
6594 #define ALT_QSPI_FLASHCMDWRDATAUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDWRDATAUP_OFST))
6614 #define ALT_QSPI_MODULEID_VALUE_LSB 0
6616 #define ALT_QSPI_MODULEID_VALUE_MSB 24
6618 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
6620 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
6622 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
6624 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
6626 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
6628 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
6637 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_LSB 25
6639 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_MSB 31
6641 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_WIDTH 7
6643 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET_MSK 0xfe000000
6645 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_CLR_MSK 0x01ffffff
6647 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_RESET 0x0
6649 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_GET(value) (((value) & 0xfe000000) >> 25)
6651 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET(value) (((value) << 25) & 0xfe000000)
6653 #ifndef __ASSEMBLY__
6665 struct ALT_QSPI_MODULEID_s
6667 const volatile uint32_t value : 25;
6668 const volatile uint32_t mod_id_resv_fld : 7;
6672 typedef struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
6676 #define ALT_QSPI_MODULEID_RESET 0x00001001
6678 #define ALT_QSPI_MODULEID_OFST 0xfc
6680 #define ALT_QSPI_MODULEID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_MODULEID_OFST))
6682 #ifndef __ASSEMBLY__
6696 volatile ALT_QSPI_CFG_t cfg;
6697 volatile ALT_QSPI_DEVRD_t devrd;
6698 volatile ALT_QSPI_DEVWR_t devwr;
6699 volatile ALT_QSPI_DELAY_t delay;
6700 volatile ALT_QSPI_RDDATACAP_t rddatacap;
6701 volatile ALT_QSPI_DEVSZ_t devsz;
6702 volatile ALT_QSPI_SRAMPART_t srampart;
6703 volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig;
6704 volatile ALT_QSPI_DMAPER_t dmaper;
6705 volatile ALT_QSPI_REMAPADDR_t remapaddr;
6706 volatile ALT_QSPI_MODEBIT_t modebit;
6707 volatile ALT_QSPI_SRAMFILL_t sramfill;
6708 volatile ALT_QSPI_TXTHRESH_t txthresh;
6709 volatile ALT_QSPI_RXTHRESH_t rxthresh;
6710 volatile uint32_t _pad_0x38_0x3f[2];
6711 volatile ALT_QSPI_IRQSTAT_t irqstat;
6712 volatile ALT_QSPI_IRQMASK_t irqmask;
6713 volatile uint32_t _pad_0x48_0x4f[2];
6714 volatile ALT_QSPI_LOWWRPROT_t lowwrprot;
6715 volatile ALT_QSPI_UPPWRPROT_t uppwrprot;
6716 volatile ALT_QSPI_WRPROT_t wrprot;
6717 volatile uint32_t _pad_0x5c_0x5f;
6718 volatile ALT_QSPI_INDRD_t indrd;
6719 volatile ALT_QSPI_INDRDWATER_t indrdwater;
6720 volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr;
6721 volatile ALT_QSPI_INDRDCNT_t indrdcnt;
6722 volatile ALT_QSPI_INDWR_t indwr;
6723 volatile ALT_QSPI_INDWRWATER_t indwrwater;
6724 volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr;
6725 volatile ALT_QSPI_INDWRCNT_t indwrcnt;
6726 volatile uint32_t _pad_0x80_0x8f[4];
6727 volatile ALT_QSPI_FLASHCMD_t flashcmd;
6728 volatile ALT_QSPI_FLASHCMDADDR_t flashcmdaddr;
6729 volatile uint32_t _pad_0x98_0x9f[2];
6730 volatile ALT_QSPI_FLASHCMDRDDATALO_t flashcmdrddatalo;
6731 volatile ALT_QSPI_FLASHCMDRDDATAUP_t flashcmdrddataup;
6732 volatile ALT_QSPI_FLASHCMDWRDATALO_t flashcmdwrdatalo;
6733 volatile ALT_QSPI_FLASHCMDWRDATAUP_t flashcmdwrdataup;
6734 volatile uint32_t _pad_0xb0_0xfb[19];
6735 volatile ALT_QSPI_MODULEID_t moduleid;
6739 typedef struct ALT_QSPI_s ALT_QSPI_t;
6741 struct ALT_QSPI_raw_s
6743 volatile uint32_t cfg;
6744 volatile uint32_t devrd;
6745 volatile uint32_t devwr;
6746 volatile uint32_t delay;
6747 volatile uint32_t rddatacap;
6748 volatile uint32_t devsz;
6749 volatile uint32_t srampart;
6750 volatile uint32_t indaddrtrig;
6751 volatile uint32_t dmaper;
6752 volatile uint32_t remapaddr;
6753 volatile uint32_t modebit;
6754 volatile uint32_t sramfill;
6755 volatile uint32_t txthresh;
6756 volatile uint32_t rxthresh;
6757 volatile uint32_t _pad_0x38_0x3f[2];
6758 volatile uint32_t irqstat;
6759 volatile uint32_t irqmask;
6760 volatile uint32_t _pad_0x48_0x4f[2];
6761 volatile uint32_t lowwrprot;
6762 volatile uint32_t uppwrprot;
6763 volatile uint32_t wrprot;
6764 volatile uint32_t _pad_0x5c_0x5f;
6765 volatile uint32_t indrd;
6766 volatile uint32_t indrdwater;
6767 volatile uint32_t indrdstaddr;
6768 volatile uint32_t indrdcnt;
6769 volatile uint32_t indwr;
6770 volatile uint32_t indwrwater;
6771 volatile uint32_t indwrstaddr;
6772 volatile uint32_t indwrcnt;
6773 volatile uint32_t _pad_0x80_0x8f[4];
6774 volatile uint32_t flashcmd;
6775 volatile uint32_t flashcmdaddr;
6776 volatile uint32_t _pad_0x98_0x9f[2];
6777 volatile uint32_t flashcmdrddatalo;
6778 volatile uint32_t flashcmdrddataup;
6779 volatile uint32_t flashcmdwrdatalo;
6780 volatile uint32_t flashcmdwrdataup;
6781 volatile uint32_t _pad_0xb0_0xfb[19];
6782 volatile uint32_t moduleid;
6786 typedef struct ALT_QSPI_raw_s ALT_QSPI_raw_t;