Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
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alt_clkmgr.h
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32 
33 /* Altera - ALT_CLKMGR */
34 
35 #ifndef __ALT_SOCAL_CLKMGR_H__
36 #define __ALT_SOCAL_CLKMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Clock Manager Module - CLKMGR
50  * Clock Manager Module
51  *
52  * Registers in the Clock Manager module
53  *
54  */
55 /*
56  * Register : Control Register - ctrl
57  *
58  * Contains fields that control the entire Clock Manager.
59  *
60  * Register Layout
61  *
62  * Bits | Access | Reset | Description
63  * :--------|:-------|:------|:-----------------------------
64  * [0] | RW | 0x1 | Boot Mode
65  * [7:1] | ??? | 0x1 | *UNDEFINED*
66  * [8] | RW | 0x0 | SW Control Boot Clock Enable
67  * [9] | RW | 0x0 | SW Control Boot Clock Select
68  * [31:10] | ??? | 0x0 | *UNDEFINED*
69  *
70  */
71 /*
72  * Field : Boot Mode - bootmode
73  *
74  * When set the Clock Manager is in Boot Mode.
75  *
76  * In Boot Mode Clock Manager register settings defining clock behavior are ignored
77  * and clocks are set to their Boot Mode settings. All clocks will be bypassed and
78  * external HW managed counters and dividers will be set to divide by 1.
79  *
80  * This bit should only be cleared when clocks have been correctly configured.
81  *
82  * This field is set on a cold reset and optionally on a warm reset. SW may set
83  * this bit to force the clocks into Boot Mode. SW exits Boot Mode by clearing
84  * this bit.
85  *
86  * Field Access Macros:
87  *
88  */
89 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTRL_BOOTMODE register field. */
90 #define ALT_CLKMGR_CTRL_BOOTMODE_LSB 0
91 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTRL_BOOTMODE register field. */
92 #define ALT_CLKMGR_CTRL_BOOTMODE_MSB 0
93 /* The width in bits of the ALT_CLKMGR_CTRL_BOOTMODE register field. */
94 #define ALT_CLKMGR_CTRL_BOOTMODE_WIDTH 1
95 /* The mask used to set the ALT_CLKMGR_CTRL_BOOTMODE register field value. */
96 #define ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001
97 /* The mask used to clear the ALT_CLKMGR_CTRL_BOOTMODE register field value. */
98 #define ALT_CLKMGR_CTRL_BOOTMODE_CLR_MSK 0xfffffffe
99 /* The reset value of the ALT_CLKMGR_CTRL_BOOTMODE register field. */
100 #define ALT_CLKMGR_CTRL_BOOTMODE_RESET 0x1
101 /* Extracts the ALT_CLKMGR_CTRL_BOOTMODE field value from a register. */
102 #define ALT_CLKMGR_CTRL_BOOTMODE_GET(value) (((value) & 0x00000001) >> 0)
103 /* Produces a ALT_CLKMGR_CTRL_BOOTMODE register field value suitable for setting the register. */
104 #define ALT_CLKMGR_CTRL_BOOTMODE_SET(value) (((value) << 0) & 0x00000001)
105 
106 /*
107  * Field : SW Control Boot Clock Enable - swctrlbtclken
108  *
109  * If set, then Software will take control of the boot_clk mux select. If set,
110  * then swctrlbtclksel will determine the mux setting. If not set, the security
111  * features will determine the fuse settings.
112  *
113  * This bit is cleared on a cold reset. Warm reset has no affect on this bit.
114  *
115  * Field Access Macros:
116  *
117  */
118 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field. */
119 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_LSB 8
120 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field. */
121 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_MSB 8
122 /* The width in bits of the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field. */
123 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_WIDTH 1
124 /* The mask used to set the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field value. */
125 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_SET_MSK 0x00000100
126 /* The mask used to clear the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field value. */
127 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_CLR_MSK 0xfffffeff
128 /* The reset value of the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field. */
129 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_RESET 0x0
130 /* Extracts the ALT_CLKMGR_CTRL_SWCTRLBTCLKEN field value from a register. */
131 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_GET(value) (((value) & 0x00000100) >> 8)
132 /* Produces a ALT_CLKMGR_CTRL_SWCTRLBTCLKEN register field value suitable for setting the register. */
133 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKEN_SET(value) (((value) << 8) & 0x00000100)
134 
135 /*
136  * Field : SW Control Boot Clock Select - swctrlbtclksel
137  *
138  * This bit is only used if swctrlbtclken is set.
139  *
140  * If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2. If 0,
141  * boot_clk source will be from the external oscillator (EOSC1).
142  *
143  * This bit is cleared on a cold reset. Warm reset has no affect on this bit.
144  *
145  * Field Access Macros:
146  *
147  */
148 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field. */
149 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_LSB 9
150 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field. */
151 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_MSB 9
152 /* The width in bits of the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field. */
153 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_WIDTH 1
154 /* The mask used to set the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field value. */
155 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_SET_MSK 0x00000200
156 /* The mask used to clear the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field value. */
157 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_CLR_MSK 0xfffffdff
158 /* The reset value of the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field. */
159 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_RESET 0x0
160 /* Extracts the ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL field value from a register. */
161 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_GET(value) (((value) & 0x00000200) >> 9)
162 /* Produces a ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL register field value suitable for setting the register. */
163 #define ALT_CLKMGR_CTRL_SWCTRLBTCLKSEL_SET(value) (((value) << 9) & 0x00000200)
164 
165 #ifndef __ASSEMBLY__
166 /*
167  * WARNING: The C register and register group struct declarations are provided for
168  * convenience and illustrative purposes. They should, however, be used with
169  * caution as the C language standard provides no guarantees about the alignment or
170  * atomicity of device memory accesses. The recommended practice for coding device
171  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
172  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
173  * alt_write_dword() functions for 64 bit registers.
174  *
175  * The struct declaration for register ALT_CLKMGR_CTRL.
176  */
177 struct ALT_CLKMGR_CTRL_s
178 {
179  volatile uint32_t bootmode : 1; /* Boot Mode */
180  uint32_t : 7; /* *UNDEFINED* */
181  volatile uint32_t swctrlbtclken : 1; /* SW Control Boot Clock Enable */
182  volatile uint32_t swctrlbtclksel : 1; /* SW Control Boot Clock Select */
183  uint32_t : 22; /* *UNDEFINED* */
184 };
185 
186 /* The typedef declaration for register ALT_CLKMGR_CTRL. */
187 typedef struct ALT_CLKMGR_CTRL_s ALT_CLKMGR_CTRL_t;
188 #endif /* __ASSEMBLY__ */
189 
190 /* The reset value of the ALT_CLKMGR_CTRL register. */
191 #define ALT_CLKMGR_CTRL_RESET 0x00000003
192 /* The byte offset of the ALT_CLKMGR_CTRL register from the beginning of the component. */
193 #define ALT_CLKMGR_CTRL_OFST 0x0
194 
195 /*
196  * Register : Status Register - stat
197  *
198  * Provides status for Clock Manager including PLL lock and HW Managed Clock State
199  * Machine busy.
200  *
201  * Register Layout
202  *
203  * Bits | Access | Reset | Description
204  * :--------|:-------|:------|:-----------------------------------
205  * [0] | R | 0x0 | HW Managed Clocks BUSY
206  * [7:1] | ??? | 0x0 | *UNDEFINED*
207  * [8] | R | 0x0 | Main PLL Current Lock Status
208  * [9] | R | 0x0 | Peripheral PLL Current Lock Status
209  * [15:10] | ??? | 0x0 | *UNDEFINED*
210  * [16] | R | 0x1 | Boot Mode Status
211  * [17] | R | 0x0 | Boot Clock Source Status
212  * [31:18] | ??? | 0x0 | *UNDEFINED*
213  *
214  */
215 /*
216  * Field : HW Managed Clocks BUSY - busy
217  *
218  * This read only bit indicates that the Hardware Managed clock's state machine is
219  * active. If the state machine is active, then the clocks are in transition.
220  * Software should poll this bit after changing the source of internal clocks when
221  * changing the state of CTRL.BOOTMODE, MAINPLLGRP.BYPASS.MPU or
222  * MAINPLLGRP.BYPASS.NOC register bits. Immediately following writes to any of
223  * these registers, SW should wait 0.5 usecs and then poll this BUSY bit until it
224  * is IDLE before proceeding with any other register writes in the Clock Manager.
225  *
226  * The reset value of this bit is applied on a cold reset; warm reset has no affect
227  * on this bit.
228  *
229  * Field Enumeration Values:
230  *
231  * Enum | Value | Description
232  * :----------------------------|:------|:---------------------
233  * ALT_CLKMGR_STAT_BUSY_E_IDLE | 0x0 | Clocks stable
234  * ALT_CLKMGR_STAT_BUSY_E_BUSY | 0x1 | Clocks in transition
235  *
236  * Field Access Macros:
237  *
238  */
239 /*
240  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
241  *
242  * Clocks stable
243  */
244 #define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
245 /*
246  * Enumerated value for register field ALT_CLKMGR_STAT_BUSY
247  *
248  * Clocks in transition
249  */
250 #define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
251 
252 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
253 #define ALT_CLKMGR_STAT_BUSY_LSB 0
254 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BUSY register field. */
255 #define ALT_CLKMGR_STAT_BUSY_MSB 0
256 /* The width in bits of the ALT_CLKMGR_STAT_BUSY register field. */
257 #define ALT_CLKMGR_STAT_BUSY_WIDTH 1
258 /* The mask used to set the ALT_CLKMGR_STAT_BUSY register field value. */
259 #define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
260 /* The mask used to clear the ALT_CLKMGR_STAT_BUSY register field value. */
261 #define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
262 /* The reset value of the ALT_CLKMGR_STAT_BUSY register field. */
263 #define ALT_CLKMGR_STAT_BUSY_RESET 0x0
264 /* Extracts the ALT_CLKMGR_STAT_BUSY field value from a register. */
265 #define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
266 /* Produces a ALT_CLKMGR_STAT_BUSY register field value suitable for setting the register. */
267 #define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
268 
269 /*
270  * Field : Main PLL Current Lock Status - mainplllocked
271  *
272  * If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not
273  * locked.
274  *
275  * Field Access Macros:
276  *
277  */
278 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_MAINPLLLOCKED register field. */
279 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_LSB 8
280 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_MAINPLLLOCKED register field. */
281 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_MSB 8
282 /* The width in bits of the ALT_CLKMGR_STAT_MAINPLLLOCKED register field. */
283 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_WIDTH 1
284 /* The mask used to set the ALT_CLKMGR_STAT_MAINPLLLOCKED register field value. */
285 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100
286 /* The mask used to clear the ALT_CLKMGR_STAT_MAINPLLLOCKED register field value. */
287 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_CLR_MSK 0xfffffeff
288 /* The reset value of the ALT_CLKMGR_STAT_MAINPLLLOCKED register field. */
289 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_RESET 0x0
290 /* Extracts the ALT_CLKMGR_STAT_MAINPLLLOCKED field value from a register. */
291 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
292 /* Produces a ALT_CLKMGR_STAT_MAINPLLLOCKED register field value suitable for setting the register. */
293 #define ALT_CLKMGR_STAT_MAINPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
294 
295 /*
296  * Field : Peripheral PLL Current Lock Status - perplllocked
297  *
298  * If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is
299  * currently not locked.
300  *
301  * Field Access Macros:
302  *
303  */
304 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_PERPLLLOCKED register field. */
305 #define ALT_CLKMGR_STAT_PERPLLLOCKED_LSB 9
306 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_PERPLLLOCKED register field. */
307 #define ALT_CLKMGR_STAT_PERPLLLOCKED_MSB 9
308 /* The width in bits of the ALT_CLKMGR_STAT_PERPLLLOCKED register field. */
309 #define ALT_CLKMGR_STAT_PERPLLLOCKED_WIDTH 1
310 /* The mask used to set the ALT_CLKMGR_STAT_PERPLLLOCKED register field value. */
311 #define ALT_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200
312 /* The mask used to clear the ALT_CLKMGR_STAT_PERPLLLOCKED register field value. */
313 #define ALT_CLKMGR_STAT_PERPLLLOCKED_CLR_MSK 0xfffffdff
314 /* The reset value of the ALT_CLKMGR_STAT_PERPLLLOCKED register field. */
315 #define ALT_CLKMGR_STAT_PERPLLLOCKED_RESET 0x0
316 /* Extracts the ALT_CLKMGR_STAT_PERPLLLOCKED field value from a register. */
317 #define ALT_CLKMGR_STAT_PERPLLLOCKED_GET(value) (((value) & 0x00000200) >> 9)
318 /* Produces a ALT_CLKMGR_STAT_PERPLLLOCKED register field value suitable for setting the register. */
319 #define ALT_CLKMGR_STAT_PERPLLLOCKED_SET(value) (((value) << 9) & 0x00000200)
320 
321 /*
322  * Field : Boot Mode Status - bootmode
323  *
324  * If 1, the clocks are currently in Boot Mode. If 0, the clocks are not in Boot
325  * Mode.
326  *
327  * This is a read only status. For SW to exit Boot Mode, SW must clear the RW bit
328  * CTRL.BOOTMODE.
329  *
330  * Field Access Macros:
331  *
332  */
333 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BOOTMODE register field. */
334 #define ALT_CLKMGR_STAT_BOOTMODE_LSB 16
335 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BOOTMODE register field. */
336 #define ALT_CLKMGR_STAT_BOOTMODE_MSB 16
337 /* The width in bits of the ALT_CLKMGR_STAT_BOOTMODE register field. */
338 #define ALT_CLKMGR_STAT_BOOTMODE_WIDTH 1
339 /* The mask used to set the ALT_CLKMGR_STAT_BOOTMODE register field value. */
340 #define ALT_CLKMGR_STAT_BOOTMODE_SET_MSK 0x00010000
341 /* The mask used to clear the ALT_CLKMGR_STAT_BOOTMODE register field value. */
342 #define ALT_CLKMGR_STAT_BOOTMODE_CLR_MSK 0xfffeffff
343 /* The reset value of the ALT_CLKMGR_STAT_BOOTMODE register field. */
344 #define ALT_CLKMGR_STAT_BOOTMODE_RESET 0x1
345 /* Extracts the ALT_CLKMGR_STAT_BOOTMODE field value from a register. */
346 #define ALT_CLKMGR_STAT_BOOTMODE_GET(value) (((value) & 0x00010000) >> 16)
347 /* Produces a ALT_CLKMGR_STAT_BOOTMODE register field value suitable for setting the register. */
348 #define ALT_CLKMGR_STAT_BOOTMODE_SET(value) (((value) << 16) & 0x00010000)
349 
350 /*
351  * Field : Boot Clock Source Status - bootclksrc
352  *
353  * If 1, the source of boot_clk is cb_intosc_hs_div2_clk. . If 0, the boot_clk
354  * source is the external oscillator (EOSC1).
355  *
356  * This is a read only status.
357  *
358  * Field Access Macros:
359  *
360  */
361 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_STAT_BOOTCLKSRC register field. */
362 #define ALT_CLKMGR_STAT_BOOTCLKSRC_LSB 17
363 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_STAT_BOOTCLKSRC register field. */
364 #define ALT_CLKMGR_STAT_BOOTCLKSRC_MSB 17
365 /* The width in bits of the ALT_CLKMGR_STAT_BOOTCLKSRC register field. */
366 #define ALT_CLKMGR_STAT_BOOTCLKSRC_WIDTH 1
367 /* The mask used to set the ALT_CLKMGR_STAT_BOOTCLKSRC register field value. */
368 #define ALT_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000
369 /* The mask used to clear the ALT_CLKMGR_STAT_BOOTCLKSRC register field value. */
370 #define ALT_CLKMGR_STAT_BOOTCLKSRC_CLR_MSK 0xfffdffff
371 /* The reset value of the ALT_CLKMGR_STAT_BOOTCLKSRC register field. */
372 #define ALT_CLKMGR_STAT_BOOTCLKSRC_RESET 0x0
373 /* Extracts the ALT_CLKMGR_STAT_BOOTCLKSRC field value from a register. */
374 #define ALT_CLKMGR_STAT_BOOTCLKSRC_GET(value) (((value) & 0x00020000) >> 17)
375 /* Produces a ALT_CLKMGR_STAT_BOOTCLKSRC register field value suitable for setting the register. */
376 #define ALT_CLKMGR_STAT_BOOTCLKSRC_SET(value) (((value) << 17) & 0x00020000)
377 
378 #ifndef __ASSEMBLY__
379 /*
380  * WARNING: The C register and register group struct declarations are provided for
381  * convenience and illustrative purposes. They should, however, be used with
382  * caution as the C language standard provides no guarantees about the alignment or
383  * atomicity of device memory accesses. The recommended practice for coding device
384  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
385  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
386  * alt_write_dword() functions for 64 bit registers.
387  *
388  * The struct declaration for register ALT_CLKMGR_STAT.
389  */
390 struct ALT_CLKMGR_STAT_s
391 {
392  const volatile uint32_t busy : 1; /* HW Managed Clocks BUSY */
393  uint32_t : 7; /* *UNDEFINED* */
394  const volatile uint32_t mainplllocked : 1; /* Main PLL Current Lock Status */
395  const volatile uint32_t perplllocked : 1; /* Peripheral PLL Current Lock Status */
396  uint32_t : 6; /* *UNDEFINED* */
397  const volatile uint32_t bootmode : 1; /* Boot Mode Status */
398  const volatile uint32_t bootclksrc : 1; /* Boot Clock Source Status */
399  uint32_t : 14; /* *UNDEFINED* */
400 };
401 
402 /* The typedef declaration for register ALT_CLKMGR_STAT. */
403 typedef struct ALT_CLKMGR_STAT_s ALT_CLKMGR_STAT_t;
404 #endif /* __ASSEMBLY__ */
405 
406 /* The reset value of the ALT_CLKMGR_STAT register. */
407 #define ALT_CLKMGR_STAT_RESET 0x00010000
408 /* The byte offset of the ALT_CLKMGR_STAT register from the beginning of the component. */
409 #define ALT_CLKMGR_STAT_OFST 0x4
410 
411 /*
412  * Register : Test IO Control Register - testioctrl
413  *
414  * Contains fields setting the IO output select for Test Clock and Debug outputs.
415  *
416  * For debug purpose, clock manager send the PLL clocks and PLL lock status out to
417  * the dedicated IO and DFT fabric. Dedicated IO expects 4 signals from clock
418  * manager i.e. osc_clk, main pll c0/c1, peripheral pll c0/c1 and lock status.
419  *
420  * testioctrl_debugclksel is used to select between main pll lock and peripheral
421  * pll lock status
422  *
423  * testioctrl_mainclksel is used to select between channel 0 and channel 1 of main
424  * PLL
425  *
426  * testioctrl_peripclksel is used to select between channel 0 and channel 1 of
427  * peripheral PLL
428  *
429  * Register Layout
430  *
431  * Bits | Access | Reset | Description
432  * :-------|:-------|:-------|:------------------------
433  * [0] | RW | 0x0 | Main Clock Select
434  * [1] | ??? | 0x0 | *UNDEFINED*
435  * [2] | RW | 0x0 | Peripheral Clock Select
436  * [3] | ??? | 0x1 | *UNDEFINED*
437  * [4] | RW | 0x0 | Debug Clock Select
438  * [31:5] | ??? | 0x8040 | *UNDEFINED*
439  *
440  */
441 /*
442  * Field : Main Clock Select - mainclksel
443  *
444  * Selects between Channel 1 and channel 0 of the main PLL.
445  *
446  * 0 -> main PLL C0
447  *
448  * 1 -> main PLL C1
449  *
450  * Field Enumeration Values:
451  *
452  * Enum | Value | Description
453  * :---------------------------------------|:------|:------------
454  * ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_E_MPU | 0x0 |
455  * ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_E_NOC | 0x1 |
456  *
457  * Field Access Macros:
458  *
459  */
460 /*
461  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL
462  *
463  */
464 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_E_MPU 0x0
465 /*
466  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL
467  *
468  */
469 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_E_NOC 0x1
470 
471 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field. */
472 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_LSB 0
473 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field. */
474 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_MSB 0
475 /* The width in bits of the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field. */
476 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_WIDTH 1
477 /* The mask used to set the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field value. */
478 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_SET_MSK 0x00000001
479 /* The mask used to clear the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field value. */
480 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_CLR_MSK 0xfffffffe
481 /* The reset value of the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field. */
482 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_RESET 0x0
483 /* Extracts the ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL field value from a register. */
484 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_GET(value) (((value) & 0x00000001) >> 0)
485 /* Produces a ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL register field value suitable for setting the register. */
486 #define ALT_CLKMGR_TESTIOCTRL_MAINCLKSEL_SET(value) (((value) << 0) & 0x00000001)
487 
488 /*
489  * Field : Peripheral Clock Select - periclksel
490  *
491  * Selects between Channel 1 and channel 0 of the peripheral PLL.
492  *
493  * 0 -> periph PLL C0
494  *
495  * 1 -> periph PLL C1
496  *
497  * Field Enumeration Values:
498  *
499  * Enum | Value | Description
500  * :---------------------------------------|:------|:------------
501  * ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_E_MPU | 0x0 |
502  * ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_E_NOC | 0x1 |
503  *
504  * Field Access Macros:
505  *
506  */
507 /*
508  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_PERICLKSEL
509  *
510  */
511 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_E_MPU 0x0
512 /*
513  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_PERICLKSEL
514  *
515  */
516 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_E_NOC 0x1
517 
518 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field. */
519 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_LSB 2
520 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field. */
521 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_MSB 2
522 /* The width in bits of the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field. */
523 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_WIDTH 1
524 /* The mask used to set the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field value. */
525 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_SET_MSK 0x00000004
526 /* The mask used to clear the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field value. */
527 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_CLR_MSK 0xfffffffb
528 /* The reset value of the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field. */
529 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_RESET 0x0
530 /* Extracts the ALT_CLKMGR_TESTIOCTRL_PERICLKSEL field value from a register. */
531 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_GET(value) (((value) & 0x00000004) >> 2)
532 /* Produces a ALT_CLKMGR_TESTIOCTRL_PERICLKSEL register field value suitable for setting the register. */
533 #define ALT_CLKMGR_TESTIOCTRL_PERICLKSEL_SET(value) (((value) << 2) & 0x00000004)
534 
535 /*
536  * Field : Debug Clock Select - debugclksel
537  *
538  * Selects the source of PLL_lock for debug purpose.
539  *
540  * 0 -main PLL lock
541  *
542  * 1- peri pLL lock
543  *
544  * Field Enumeration Values:
545  *
546  * Enum | Value | Description
547  * :-------------------------------------------|:------|:------------
548  * ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_E_MAIN | 0x0 |
549  * ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_E_PERIPH | 0x1 |
550  *
551  * Field Access Macros:
552  *
553  */
554 /*
555  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL
556  *
557  */
558 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_E_MAIN 0x0
559 /*
560  * Enumerated value for register field ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL
561  *
562  */
563 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_E_PERIPH 0x1
564 
565 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field. */
566 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_LSB 4
567 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field. */
568 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_MSB 4
569 /* The width in bits of the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field. */
570 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_WIDTH 1
571 /* The mask used to set the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field value. */
572 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_SET_MSK 0x00000010
573 /* The mask used to clear the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field value. */
574 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_CLR_MSK 0xffffffef
575 /* The reset value of the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field. */
576 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_RESET 0x0
577 /* Extracts the ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL field value from a register. */
578 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_GET(value) (((value) & 0x00000010) >> 4)
579 /* Produces a ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL register field value suitable for setting the register. */
580 #define ALT_CLKMGR_TESTIOCTRL_DEBUGCLKSEL_SET(value) (((value) << 4) & 0x00000010)
581 
582 #ifndef __ASSEMBLY__
583 /*
584  * WARNING: The C register and register group struct declarations are provided for
585  * convenience and illustrative purposes. They should, however, be used with
586  * caution as the C language standard provides no guarantees about the alignment or
587  * atomicity of device memory accesses. The recommended practice for coding device
588  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
589  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
590  * alt_write_dword() functions for 64 bit registers.
591  *
592  * The struct declaration for register ALT_CLKMGR_TESTIOCTRL.
593  */
594 struct ALT_CLKMGR_TESTIOCTRL_s
595 {
596  volatile uint32_t mainclksel : 1; /* Main Clock Select */
597  uint32_t : 1; /* *UNDEFINED* */
598  volatile uint32_t periclksel : 1; /* Peripheral Clock Select */
599  uint32_t : 1; /* *UNDEFINED* */
600  volatile uint32_t debugclksel : 1; /* Debug Clock Select */
601  uint32_t : 27; /* *UNDEFINED* */
602 };
603 
604 /* The typedef declaration for register ALT_CLKMGR_TESTIOCTRL. */
605 typedef struct ALT_CLKMGR_TESTIOCTRL_s ALT_CLKMGR_TESTIOCTRL_t;
606 #endif /* __ASSEMBLY__ */
607 
608 /* The reset value of the ALT_CLKMGR_TESTIOCTRL register. */
609 #define ALT_CLKMGR_TESTIOCTRL_RESET 0x00100808
610 /* The byte offset of the ALT_CLKMGR_TESTIOCTRL register from the beginning of the component. */
611 #define ALT_CLKMGR_TESTIOCTRL_OFST 0x8
612 
613 /*
614  * Register : intrgen
615  *
616  * Global Interrupt Enable
617  *
618  * Writing 0 will disable any functions from this IP to cause a hardware interrupt.
619  *
620  * Interrupt pending status register can still be set but the hardware interrupt
621  * signal will remain de-asserted.
622  *
623  * Writing 1 will enable the hardware interrupt from this IP.
624  *
625  * Register Layout
626  *
627  * Bits | Access | Reset | Description
628  * :-------|:-------|:------|:----------------------
629  * [0] | RW | 0x0 | ALT_CLKMGR_INTRGEN_EN
630  * [31:1] | ??? | 0x0 | *UNDEFINED*
631  *
632  */
633 /*
634  * Field : en
635  *
636  * Field Access Macros:
637  *
638  */
639 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRGEN_EN register field. */
640 #define ALT_CLKMGR_INTRGEN_EN_LSB 0
641 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRGEN_EN register field. */
642 #define ALT_CLKMGR_INTRGEN_EN_MSB 0
643 /* The width in bits of the ALT_CLKMGR_INTRGEN_EN register field. */
644 #define ALT_CLKMGR_INTRGEN_EN_WIDTH 1
645 /* The mask used to set the ALT_CLKMGR_INTRGEN_EN register field value. */
646 #define ALT_CLKMGR_INTRGEN_EN_SET_MSK 0x00000001
647 /* The mask used to clear the ALT_CLKMGR_INTRGEN_EN register field value. */
648 #define ALT_CLKMGR_INTRGEN_EN_CLR_MSK 0xfffffffe
649 /* The reset value of the ALT_CLKMGR_INTRGEN_EN register field. */
650 #define ALT_CLKMGR_INTRGEN_EN_RESET 0x0
651 /* Extracts the ALT_CLKMGR_INTRGEN_EN field value from a register. */
652 #define ALT_CLKMGR_INTRGEN_EN_GET(value) (((value) & 0x00000001) >> 0)
653 /* Produces a ALT_CLKMGR_INTRGEN_EN register field value suitable for setting the register. */
654 #define ALT_CLKMGR_INTRGEN_EN_SET(value) (((value) << 0) & 0x00000001)
655 
656 #ifndef __ASSEMBLY__
657 /*
658  * WARNING: The C register and register group struct declarations are provided for
659  * convenience and illustrative purposes. They should, however, be used with
660  * caution as the C language standard provides no guarantees about the alignment or
661  * atomicity of device memory accesses. The recommended practice for coding device
662  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
663  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
664  * alt_write_dword() functions for 64 bit registers.
665  *
666  * The struct declaration for register ALT_CLKMGR_INTRGEN.
667  */
668 struct ALT_CLKMGR_INTRGEN_s
669 {
670  volatile uint32_t en : 1; /* ALT_CLKMGR_INTRGEN_EN */
671  uint32_t : 31; /* *UNDEFINED* */
672 };
673 
674 /* The typedef declaration for register ALT_CLKMGR_INTRGEN. */
675 typedef struct ALT_CLKMGR_INTRGEN_s ALT_CLKMGR_INTRGEN_t;
676 #endif /* __ASSEMBLY__ */
677 
678 /* The reset value of the ALT_CLKMGR_INTRGEN register. */
679 #define ALT_CLKMGR_INTRGEN_RESET 0x00000000
680 /* The byte offset of the ALT_CLKMGR_INTRGEN register from the beginning of the component. */
681 #define ALT_CLKMGR_INTRGEN_OFST 0xc
682 
683 /*
684  * Register : intrmsk
685  *
686  * Interrupt Mask
687  *
688  * A 0 in the curresponding bitfield will mask that particular interrupt.
689  *
690  * Register Layout
691  *
692  * Bits | Access | Reset | Description
693  * :-------|:-------|:------|:------------------------------------
694  * [0] | RW | 0x0 | ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED
695  * [1] | RW | 0x0 | ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED
696  * [2] | RW | 0x0 | ALT_CLKMGR_INTRMSK_MAINLOCKLOST
697  * [3] | RW | 0x0 | ALT_CLKMGR_INTRMSK_PERLOCKLOST
698  * [31:4] | ??? | 0x0 | *UNDEFINED*
699  *
700  */
701 /*
702  * Field : mainlockachieved
703  *
704  * To mask lock achieved interrupt from main PLL
705  *
706  * Field Access Macros:
707  *
708  */
709 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field. */
710 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_LSB 0
711 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field. */
712 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_MSB 0
713 /* The width in bits of the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field. */
714 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_WIDTH 1
715 /* The mask used to set the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field value. */
716 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_SET_MSK 0x00000001
717 /* The mask used to clear the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field value. */
718 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_CLR_MSK 0xfffffffe
719 /* The reset value of the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field. */
720 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_RESET 0x0
721 /* Extracts the ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED field value from a register. */
722 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
723 /* Produces a ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED register field value suitable for setting the register. */
724 #define ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED_SET(value) (((value) << 0) & 0x00000001)
725 
726 /*
727  * Field : perlockachieved
728  *
729  * To mask lock achieved interrupt from periph PLL
730  *
731  * Field Access Macros:
732  *
733  */
734 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field. */
735 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_LSB 1
736 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field. */
737 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_MSB 1
738 /* The width in bits of the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field. */
739 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_WIDTH 1
740 /* The mask used to set the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field value. */
741 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_SET_MSK 0x00000002
742 /* The mask used to clear the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field value. */
743 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_CLR_MSK 0xfffffffd
744 /* The reset value of the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field. */
745 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_RESET 0x0
746 /* Extracts the ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED field value from a register. */
747 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
748 /* Produces a ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED register field value suitable for setting the register. */
749 #define ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED_SET(value) (((value) << 1) & 0x00000002)
750 
751 /*
752  * Field : mainlocklost
753  *
754  * To mask lock lost interrupt from main PLL
755  *
756  * Field Access Macros:
757  *
758  */
759 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field. */
760 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_LSB 2
761 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field. */
762 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_MSB 2
763 /* The width in bits of the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field. */
764 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_WIDTH 1
765 /* The mask used to set the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field value. */
766 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_SET_MSK 0x00000004
767 /* The mask used to clear the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field value. */
768 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_CLR_MSK 0xfffffffb
769 /* The reset value of the ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field. */
770 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_RESET 0x0
771 /* Extracts the ALT_CLKMGR_INTRMSK_MAINLOCKLOST field value from a register. */
772 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_GET(value) (((value) & 0x00000004) >> 2)
773 /* Produces a ALT_CLKMGR_INTRMSK_MAINLOCKLOST register field value suitable for setting the register. */
774 #define ALT_CLKMGR_INTRMSK_MAINLOCKLOST_SET(value) (((value) << 2) & 0x00000004)
775 
776 /*
777  * Field : perlocklost
778  *
779  * To mask lock lost interrupt from periph PLL
780  *
781  * Field Access Macros:
782  *
783  */
784 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field. */
785 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_LSB 3
786 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field. */
787 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_MSB 3
788 /* The width in bits of the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field. */
789 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_WIDTH 1
790 /* The mask used to set the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field value. */
791 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_SET_MSK 0x00000008
792 /* The mask used to clear the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field value. */
793 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_CLR_MSK 0xfffffff7
794 /* The reset value of the ALT_CLKMGR_INTRMSK_PERLOCKLOST register field. */
795 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_RESET 0x0
796 /* Extracts the ALT_CLKMGR_INTRMSK_PERLOCKLOST field value from a register. */
797 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_GET(value) (((value) & 0x00000008) >> 3)
798 /* Produces a ALT_CLKMGR_INTRMSK_PERLOCKLOST register field value suitable for setting the register. */
799 #define ALT_CLKMGR_INTRMSK_PERLOCKLOST_SET(value) (((value) << 3) & 0x00000008)
800 
801 #ifndef __ASSEMBLY__
802 /*
803  * WARNING: The C register and register group struct declarations are provided for
804  * convenience and illustrative purposes. They should, however, be used with
805  * caution as the C language standard provides no guarantees about the alignment or
806  * atomicity of device memory accesses. The recommended practice for coding device
807  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
808  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
809  * alt_write_dword() functions for 64 bit registers.
810  *
811  * The struct declaration for register ALT_CLKMGR_INTRMSK.
812  */
813 struct ALT_CLKMGR_INTRMSK_s
814 {
815  volatile uint32_t mainlockachieved : 1; /* ALT_CLKMGR_INTRMSK_MAINLOCKACHIEVED */
816  volatile uint32_t perlockachieved : 1; /* ALT_CLKMGR_INTRMSK_PERLOCKACHIEVED */
817  volatile uint32_t mainlocklost : 1; /* ALT_CLKMGR_INTRMSK_MAINLOCKLOST */
818  volatile uint32_t perlocklost : 1; /* ALT_CLKMGR_INTRMSK_PERLOCKLOST */
819  uint32_t : 28; /* *UNDEFINED* */
820 };
821 
822 /* The typedef declaration for register ALT_CLKMGR_INTRMSK. */
823 typedef struct ALT_CLKMGR_INTRMSK_s ALT_CLKMGR_INTRMSK_t;
824 #endif /* __ASSEMBLY__ */
825 
826 /* The reset value of the ALT_CLKMGR_INTRMSK register. */
827 #define ALT_CLKMGR_INTRMSK_RESET 0x00000000
828 /* The byte offset of the ALT_CLKMGR_INTRMSK register from the beginning of the component. */
829 #define ALT_CLKMGR_INTRMSK_OFST 0x10
830 
831 /*
832  * Register : intrclr
833  *
834  * Interrupt Clear.
835  *
836  * Writing 1 to a particular bit will cause that interrupt to be cleared if it was
837  * set.
838  *
839  * Register Layout
840  *
841  * Bits | Access | Reset | Description
842  * :-------|:-------|:------|:-------------------------------
843  * [0] | RW | 0x0 | main PLL lock achieved clear
844  * [1] | RW | 0x0 | periph PLL lock achieved clear
845  * [2] | RW | 0x0 | main PLL lock lost clear
846  * [3] | RW | 0x0 | periph PLL lock lost clear
847  * [31:4] | ??? | 0x0 | *UNDEFINED*
848  *
849  */
850 /*
851  * Field : main PLL lock achieved clear - mainlockachieved
852  *
853  * This is used to clear sticky main PLL lock achieved signal.
854  *
855  * Field Access Macros:
856  *
857  */
858 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field. */
859 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_LSB 0
860 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field. */
861 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_MSB 0
862 /* The width in bits of the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field. */
863 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_WIDTH 1
864 /* The mask used to set the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field value. */
865 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_SET_MSK 0x00000001
866 /* The mask used to clear the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field value. */
867 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_CLR_MSK 0xfffffffe
868 /* The reset value of the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field. */
869 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_RESET 0x0
870 /* Extracts the ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED field value from a register. */
871 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
872 /* Produces a ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED register field value suitable for setting the register. */
873 #define ALT_CLKMGR_INTRCLR_MAINLOCKACHIEVED_SET(value) (((value) << 0) & 0x00000001)
874 
875 /*
876  * Field : periph PLL lock achieved clear - perlockachieved
877  *
878  * This is used to clear sticky periph PLL lock achieved signal.
879  *
880  * Field Access Macros:
881  *
882  */
883 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field. */
884 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_LSB 1
885 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field. */
886 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_MSB 1
887 /* The width in bits of the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field. */
888 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_WIDTH 1
889 /* The mask used to set the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field value. */
890 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_SET_MSK 0x00000002
891 /* The mask used to clear the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field value. */
892 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_CLR_MSK 0xfffffffd
893 /* The reset value of the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field. */
894 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_RESET 0x0
895 /* Extracts the ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED field value from a register. */
896 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
897 /* Produces a ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED register field value suitable for setting the register. */
898 #define ALT_CLKMGR_INTRCLR_PERLOCKACHIEVED_SET(value) (((value) << 1) & 0x00000002)
899 
900 /*
901  * Field : main PLL lock lost clear - mainlocklost
902  *
903  * This is used to clear sticky main PLL lock lost signal.
904  *
905  * Field Access Macros:
906  *
907  */
908 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field. */
909 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_LSB 2
910 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field. */
911 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_MSB 2
912 /* The width in bits of the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field. */
913 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_WIDTH 1
914 /* The mask used to set the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field value. */
915 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
916 /* The mask used to clear the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field value. */
917 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_CLR_MSK 0xfffffffb
918 /* The reset value of the ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field. */
919 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_RESET 0x0
920 /* Extracts the ALT_CLKMGR_INTRCLR_MAINLOCKLOST field value from a register. */
921 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_GET(value) (((value) & 0x00000004) >> 2)
922 /* Produces a ALT_CLKMGR_INTRCLR_MAINLOCKLOST register field value suitable for setting the register. */
923 #define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET(value) (((value) << 2) & 0x00000004)
924 
925 /*
926  * Field : periph PLL lock lost clear - perlocklost
927  *
928  * This is used to clear sticky periph PLL lock lost signal.
929  *
930  * Field Access Macros:
931  *
932  */
933 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field. */
934 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_LSB 3
935 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field. */
936 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_MSB 3
937 /* The width in bits of the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field. */
938 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_WIDTH 1
939 /* The mask used to set the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field value. */
940 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
941 /* The mask used to clear the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field value. */
942 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_CLR_MSK 0xfffffff7
943 /* The reset value of the ALT_CLKMGR_INTRCLR_PERLOCKLOST register field. */
944 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_RESET 0x0
945 /* Extracts the ALT_CLKMGR_INTRCLR_PERLOCKLOST field value from a register. */
946 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_GET(value) (((value) & 0x00000008) >> 3)
947 /* Produces a ALT_CLKMGR_INTRCLR_PERLOCKLOST register field value suitable for setting the register. */
948 #define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET(value) (((value) << 3) & 0x00000008)
949 
950 #ifndef __ASSEMBLY__
951 /*
952  * WARNING: The C register and register group struct declarations are provided for
953  * convenience and illustrative purposes. They should, however, be used with
954  * caution as the C language standard provides no guarantees about the alignment or
955  * atomicity of device memory accesses. The recommended practice for coding device
956  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
957  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
958  * alt_write_dword() functions for 64 bit registers.
959  *
960  * The struct declaration for register ALT_CLKMGR_INTRCLR.
961  */
962 struct ALT_CLKMGR_INTRCLR_s
963 {
964  volatile uint32_t mainlockachieved : 1; /* main PLL lock achieved clear */
965  volatile uint32_t perlockachieved : 1; /* periph PLL lock achieved clear */
966  volatile uint32_t mainlocklost : 1; /* main PLL lock lost clear */
967  volatile uint32_t perlocklost : 1; /* periph PLL lock lost clear */
968  uint32_t : 28; /* *UNDEFINED* */
969 };
970 
971 /* The typedef declaration for register ALT_CLKMGR_INTRCLR. */
972 typedef struct ALT_CLKMGR_INTRCLR_s ALT_CLKMGR_INTRCLR_t;
973 #endif /* __ASSEMBLY__ */
974 
975 /* The reset value of the ALT_CLKMGR_INTRCLR register. */
976 #define ALT_CLKMGR_INTRCLR_RESET 0x00000000
977 /* The byte offset of the ALT_CLKMGR_INTRCLR register from the beginning of the component. */
978 #define ALT_CLKMGR_INTRCLR_OFST 0x14
979 
980 /*
981  * Register : intrsts
982  *
983  * Interrupt Pending Status after the interrupt masks.
984  *
985  * Set by hardware and read by software.
986  *
987  * Sticky behavior. Once set by hardware, the bit will remain set, till cleared by
988  * software by writing to intrclr register.
989  *
990  * The status for a particular bit would be read as 0, if the curresponding mask
991  * bit is set.
992  *
993  * Register Layout
994  *
995  * Bits | Access | Reset | Description
996  * :-------|:-------|:------|:-------------------------------------------------
997  * [0] | RW | 0x0 | main PLL lock achieved pending after intr mask
998  * [1] | RW | 0x0 | periph PLL lock achieved pending after intr mask
999  * [2] | RW | 0x0 | main PLL lock lost pending after intr mask
1000  * [3] | RW | 0x0 | periph PLL lock lost pending after intr mask
1001  * [31:4] | ??? | 0x0 | *UNDEFINED*
1002  *
1003  */
1004 /*
1005  * Field : main PLL lock achieved pending after intr mask - mainlockachieved
1006  *
1007  * Pending status for main PLL lock achieved interrupt after intr mask
1008  *
1009  * Field Access Macros:
1010  *
1011  */
1012 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field. */
1013 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_LSB 0
1014 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field. */
1015 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_MSB 0
1016 /* The width in bits of the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field. */
1017 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_WIDTH 1
1018 /* The mask used to set the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field value. */
1019 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_SET_MSK 0x00000001
1020 /* The mask used to clear the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field value. */
1021 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_CLR_MSK 0xfffffffe
1022 /* The reset value of the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field. */
1023 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_RESET 0x0
1024 /* Extracts the ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED field value from a register. */
1025 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1026 /* Produces a ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED register field value suitable for setting the register. */
1027 #define ALT_CLKMGR_INTRSTS_MAINLOCKACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1028 
1029 /*
1030  * Field : periph PLL lock achieved pending after intr mask - perlockachieved
1031  *
1032  * Pending status for periph PLL lock achieved interrupt after intr mask
1033  *
1034  * Field Access Macros:
1035  *
1036  */
1037 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field. */
1038 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_LSB 1
1039 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field. */
1040 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_MSB 1
1041 /* The width in bits of the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field. */
1042 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_WIDTH 1
1043 /* The mask used to set the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field value. */
1044 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_SET_MSK 0x00000002
1045 /* The mask used to clear the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field value. */
1046 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_CLR_MSK 0xfffffffd
1047 /* The reset value of the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field. */
1048 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_RESET 0x0
1049 /* Extracts the ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED field value from a register. */
1050 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1051 /* Produces a ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED register field value suitable for setting the register. */
1052 #define ALT_CLKMGR_INTRSTS_PERLOCKACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1053 
1054 /*
1055  * Field : main PLL lock lost pending after intr mask - mainlocklost
1056  *
1057  * Pending status for main PLL lock lost interrupt after intr mask
1058  *
1059  * Field Access Macros:
1060  *
1061  */
1062 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field. */
1063 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_LSB 2
1064 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field. */
1065 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_MSB 2
1066 /* The width in bits of the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field. */
1067 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_WIDTH 1
1068 /* The mask used to set the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field value. */
1069 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_SET_MSK 0x00000004
1070 /* The mask used to clear the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field value. */
1071 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_CLR_MSK 0xfffffffb
1072 /* The reset value of the ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field. */
1073 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_RESET 0x0
1074 /* Extracts the ALT_CLKMGR_INTRSTS_MAINLOCKLOST field value from a register. */
1075 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_GET(value) (((value) & 0x00000004) >> 2)
1076 /* Produces a ALT_CLKMGR_INTRSTS_MAINLOCKLOST register field value suitable for setting the register. */
1077 #define ALT_CLKMGR_INTRSTS_MAINLOCKLOST_SET(value) (((value) << 2) & 0x00000004)
1078 
1079 /*
1080  * Field : periph PLL lock lost pending after intr mask - perlocklost
1081  *
1082  * Pending status for periph PLL lock lost interrupt after intr mask
1083  *
1084  * Field Access Macros:
1085  *
1086  */
1087 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field. */
1088 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_LSB 3
1089 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field. */
1090 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_MSB 3
1091 /* The width in bits of the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field. */
1092 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_WIDTH 1
1093 /* The mask used to set the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field value. */
1094 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_SET_MSK 0x00000008
1095 /* The mask used to clear the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field value. */
1096 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_CLR_MSK 0xfffffff7
1097 /* The reset value of the ALT_CLKMGR_INTRSTS_PERLOCKLOST register field. */
1098 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_RESET 0x0
1099 /* Extracts the ALT_CLKMGR_INTRSTS_PERLOCKLOST field value from a register. */
1100 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_GET(value) (((value) & 0x00000008) >> 3)
1101 /* Produces a ALT_CLKMGR_INTRSTS_PERLOCKLOST register field value suitable for setting the register. */
1102 #define ALT_CLKMGR_INTRSTS_PERLOCKLOST_SET(value) (((value) << 3) & 0x00000008)
1103 
1104 #ifndef __ASSEMBLY__
1105 /*
1106  * WARNING: The C register and register group struct declarations are provided for
1107  * convenience and illustrative purposes. They should, however, be used with
1108  * caution as the C language standard provides no guarantees about the alignment or
1109  * atomicity of device memory accesses. The recommended practice for coding device
1110  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1111  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1112  * alt_write_dword() functions for 64 bit registers.
1113  *
1114  * The struct declaration for register ALT_CLKMGR_INTRSTS.
1115  */
1116 struct ALT_CLKMGR_INTRSTS_s
1117 {
1118  volatile uint32_t mainlockachieved : 1; /* main PLL lock achieved pending after intr mask */
1119  volatile uint32_t perlockachieved : 1; /* periph PLL lock achieved pending after intr mask */
1120  volatile uint32_t mainlocklost : 1; /* main PLL lock lost pending after intr mask */
1121  volatile uint32_t perlocklost : 1; /* periph PLL lock lost pending after intr mask */
1122  uint32_t : 28; /* *UNDEFINED* */
1123 };
1124 
1125 /* The typedef declaration for register ALT_CLKMGR_INTRSTS. */
1126 typedef struct ALT_CLKMGR_INTRSTS_s ALT_CLKMGR_INTRSTS_t;
1127 #endif /* __ASSEMBLY__ */
1128 
1129 /* The reset value of the ALT_CLKMGR_INTRSTS register. */
1130 #define ALT_CLKMGR_INTRSTS_RESET 0x00000000
1131 /* The byte offset of the ALT_CLKMGR_INTRSTS register from the beginning of the component. */
1132 #define ALT_CLKMGR_INTRSTS_OFST 0x18
1133 
1134 /*
1135  * Register : intrstk
1136  *
1137  * Interrupt Pending Status without considering the interrupt masks.
1138  *
1139  * Set by hardware and read by software.
1140  *
1141  * Hardware can set the particular bit, even if the corresponding bit is masked by
1142  * software by intrmsk register.
1143  *
1144  * Sticky behavior. Once set by hardware, the bit will remain set, till cleared by
1145  * software by writing to intrclr register.
1146  *
1147  * Register Layout
1148  *
1149  * Bits | Access | Reset | Description
1150  * :-------|:-------|:------|:--------------------------------------------------
1151  * [0] | RW | 0x0 | main PLL lock achieved pending before intr mask
1152  * [1] | RW | 0x0 | periph PLL lock achieved pending before intr mask
1153  * [2] | RW | 0x0 | main PLL lock lost pending before intr mask
1154  * [3] | RW | 0x0 | periph PLL lock lost pending before intr mask
1155  * [31:4] | ??? | 0x0 | *UNDEFINED*
1156  *
1157  */
1158 /*
1159  * Field : main PLL lock achieved pending before intr mask - mainlockachieved
1160  *
1161  * Pending status for main PLL lock achieved interrupt before intr mask
1162  *
1163  * Field Access Macros:
1164  *
1165  */
1166 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field. */
1167 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_LSB 0
1168 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field. */
1169 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_MSB 0
1170 /* The width in bits of the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field. */
1171 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_WIDTH 1
1172 /* The mask used to set the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field value. */
1173 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_SET_MSK 0x00000001
1174 /* The mask used to clear the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field value. */
1175 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_CLR_MSK 0xfffffffe
1176 /* The reset value of the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field. */
1177 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_RESET 0x0
1178 /* Extracts the ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED field value from a register. */
1179 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1180 /* Produces a ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED register field value suitable for setting the register. */
1181 #define ALT_CLKMGR_INTRSTK_MAINLOCKACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1182 
1183 /*
1184  * Field : periph PLL lock achieved pending before intr mask - perlockachieved
1185  *
1186  * Pending status for periph PLL lock achieved interrupt before intr mask
1187  *
1188  * Field Access Macros:
1189  *
1190  */
1191 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field. */
1192 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_LSB 1
1193 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field. */
1194 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_MSB 1
1195 /* The width in bits of the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field. */
1196 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_WIDTH 1
1197 /* The mask used to set the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field value. */
1198 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_SET_MSK 0x00000002
1199 /* The mask used to clear the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field value. */
1200 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_CLR_MSK 0xfffffffd
1201 /* The reset value of the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field. */
1202 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_RESET 0x0
1203 /* Extracts the ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED field value from a register. */
1204 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1205 /* Produces a ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED register field value suitable for setting the register. */
1206 #define ALT_CLKMGR_INTRSTK_PERLOCKACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1207 
1208 /*
1209  * Field : main PLL lock lost pending before intr mask - mainlocklost
1210  *
1211  * Pending status for main PLL lock lost interrupt before intr mask
1212  *
1213  * Field Access Macros:
1214  *
1215  */
1216 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field. */
1217 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_LSB 2
1218 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field. */
1219 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_MSB 2
1220 /* The width in bits of the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field. */
1221 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_WIDTH 1
1222 /* The mask used to set the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field value. */
1223 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_SET_MSK 0x00000004
1224 /* The mask used to clear the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field value. */
1225 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_CLR_MSK 0xfffffffb
1226 /* The reset value of the ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field. */
1227 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_RESET 0x0
1228 /* Extracts the ALT_CLKMGR_INTRSTK_MAINLOCKLOST field value from a register. */
1229 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_GET(value) (((value) & 0x00000004) >> 2)
1230 /* Produces a ALT_CLKMGR_INTRSTK_MAINLOCKLOST register field value suitable for setting the register. */
1231 #define ALT_CLKMGR_INTRSTK_MAINLOCKLOST_SET(value) (((value) << 2) & 0x00000004)
1232 
1233 /*
1234  * Field : periph PLL lock lost pending before intr mask - perlocklost
1235  *
1236  * Pending status for periph PLL lock lost interrupt before intr mask
1237  *
1238  * Field Access Macros:
1239  *
1240  */
1241 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field. */
1242 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_LSB 3
1243 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field. */
1244 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_MSB 3
1245 /* The width in bits of the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field. */
1246 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_WIDTH 1
1247 /* The mask used to set the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field value. */
1248 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_SET_MSK 0x00000008
1249 /* The mask used to clear the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field value. */
1250 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_CLR_MSK 0xfffffff7
1251 /* The reset value of the ALT_CLKMGR_INTRSTK_PERLOCKLOST register field. */
1252 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_RESET 0x0
1253 /* Extracts the ALT_CLKMGR_INTRSTK_PERLOCKLOST field value from a register. */
1254 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_GET(value) (((value) & 0x00000008) >> 3)
1255 /* Produces a ALT_CLKMGR_INTRSTK_PERLOCKLOST register field value suitable for setting the register. */
1256 #define ALT_CLKMGR_INTRSTK_PERLOCKLOST_SET(value) (((value) << 3) & 0x00000008)
1257 
1258 #ifndef __ASSEMBLY__
1259 /*
1260  * WARNING: The C register and register group struct declarations are provided for
1261  * convenience and illustrative purposes. They should, however, be used with
1262  * caution as the C language standard provides no guarantees about the alignment or
1263  * atomicity of device memory accesses. The recommended practice for coding device
1264  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1265  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1266  * alt_write_dword() functions for 64 bit registers.
1267  *
1268  * The struct declaration for register ALT_CLKMGR_INTRSTK.
1269  */
1270 struct ALT_CLKMGR_INTRSTK_s
1271 {
1272  volatile uint32_t mainlockachieved : 1; /* main PLL lock achieved pending before intr mask */
1273  volatile uint32_t perlockachieved : 1; /* periph PLL lock achieved pending before intr mask */
1274  volatile uint32_t mainlocklost : 1; /* main PLL lock lost pending before intr mask */
1275  volatile uint32_t perlocklost : 1; /* periph PLL lock lost pending before intr mask */
1276  uint32_t : 28; /* *UNDEFINED* */
1277 };
1278 
1279 /* The typedef declaration for register ALT_CLKMGR_INTRSTK. */
1280 typedef struct ALT_CLKMGR_INTRSTK_s ALT_CLKMGR_INTRSTK_t;
1281 #endif /* __ASSEMBLY__ */
1282 
1283 /* The reset value of the ALT_CLKMGR_INTRSTK register. */
1284 #define ALT_CLKMGR_INTRSTK_RESET 0x00000000
1285 /* The byte offset of the ALT_CLKMGR_INTRSTK register from the beginning of the component. */
1286 #define ALT_CLKMGR_INTRSTK_OFST 0x1c
1287 
1288 /*
1289  * Register : intrraw
1290  *
1291  * Realtime Status of the bits which could have caused interrupt.
1292  *
1293  * Set and clear by hardware.
1294  *
1295  * Realtime behavior. Bits follow the current hardware status.
1296  *
1297  * Register Layout
1298  *
1299  * Bits | Access | Reset | Description
1300  * :-------|:-------|:------|:-----------------------------
1301  * [0] | RW | 0x0 | raw main pll lock achieved
1302  * [1] | RW | 0x0 | raw periph pll lock achieved
1303  * [2] | RW | 0x0 | raw main pll lock lost
1304  * [3] | RW | 0x0 | raw periph pll lock lost
1305  * [31:4] | ??? | 0x0 | *UNDEFINED*
1306  *
1307  */
1308 /*
1309  * Field : raw main pll lock achieved - mainlockachieved
1310  *
1311  * Raw signal (before masking) for main PLL lock achieved. It comed from clock
1312  * manager
1313  *
1314  * Field Access Macros:
1315  *
1316  */
1317 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field. */
1318 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_LSB 0
1319 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field. */
1320 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_MSB 0
1321 /* The width in bits of the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field. */
1322 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_WIDTH 1
1323 /* The mask used to set the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field value. */
1324 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_SET_MSK 0x00000001
1325 /* The mask used to clear the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field value. */
1326 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_CLR_MSK 0xfffffffe
1327 /* The reset value of the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field. */
1328 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_RESET 0x0
1329 /* Extracts the ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED field value from a register. */
1330 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1331 /* Produces a ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED register field value suitable for setting the register. */
1332 #define ALT_CLKMGR_INTRRAW_MAINLOCKACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1333 
1334 /*
1335  * Field : raw periph pll lock achieved - perlockachieved
1336  *
1337  * Raw signal (before masking) for periph PLL lock achieved. It comed from clock
1338  * manager
1339  *
1340  * Field Access Macros:
1341  *
1342  */
1343 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field. */
1344 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_LSB 1
1345 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field. */
1346 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_MSB 1
1347 /* The width in bits of the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field. */
1348 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_WIDTH 1
1349 /* The mask used to set the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field value. */
1350 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_SET_MSK 0x00000002
1351 /* The mask used to clear the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field value. */
1352 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_CLR_MSK 0xfffffffd
1353 /* The reset value of the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field. */
1354 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_RESET 0x0
1355 /* Extracts the ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED field value from a register. */
1356 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1357 /* Produces a ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED register field value suitable for setting the register. */
1358 #define ALT_CLKMGR_INTRRAW_PERLOCKACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1359 
1360 /*
1361  * Field : raw main pll lock lost - mainlocklost
1362  *
1363  * Raw signal (before masking) for main PLL lock lost. It comed from clock manager
1364  *
1365  * Field Access Macros:
1366  *
1367  */
1368 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field. */
1369 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_LSB 2
1370 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field. */
1371 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_MSB 2
1372 /* The width in bits of the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field. */
1373 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_WIDTH 1
1374 /* The mask used to set the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field value. */
1375 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_SET_MSK 0x00000004
1376 /* The mask used to clear the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field value. */
1377 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_CLR_MSK 0xfffffffb
1378 /* The reset value of the ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field. */
1379 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_RESET 0x0
1380 /* Extracts the ALT_CLKMGR_INTRRAW_MAINLOCKLOST field value from a register. */
1381 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_GET(value) (((value) & 0x00000004) >> 2)
1382 /* Produces a ALT_CLKMGR_INTRRAW_MAINLOCKLOST register field value suitable for setting the register. */
1383 #define ALT_CLKMGR_INTRRAW_MAINLOCKLOST_SET(value) (((value) << 2) & 0x00000004)
1384 
1385 /*
1386  * Field : raw periph pll lock lost - perlocklost
1387  *
1388  * Raw signal (before masking) for periph PLL lock lost. It comed from clock
1389  * manager
1390  *
1391  * Field Access Macros:
1392  *
1393  */
1394 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field. */
1395 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_LSB 3
1396 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field. */
1397 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_MSB 3
1398 /* The width in bits of the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field. */
1399 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_WIDTH 1
1400 /* The mask used to set the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field value. */
1401 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_SET_MSK 0x00000008
1402 /* The mask used to clear the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field value. */
1403 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_CLR_MSK 0xfffffff7
1404 /* The reset value of the ALT_CLKMGR_INTRRAW_PERLOCKLOST register field. */
1405 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_RESET 0x0
1406 /* Extracts the ALT_CLKMGR_INTRRAW_PERLOCKLOST field value from a register. */
1407 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_GET(value) (((value) & 0x00000008) >> 3)
1408 /* Produces a ALT_CLKMGR_INTRRAW_PERLOCKLOST register field value suitable for setting the register. */
1409 #define ALT_CLKMGR_INTRRAW_PERLOCKLOST_SET(value) (((value) << 3) & 0x00000008)
1410 
1411 #ifndef __ASSEMBLY__
1412 /*
1413  * WARNING: The C register and register group struct declarations are provided for
1414  * convenience and illustrative purposes. They should, however, be used with
1415  * caution as the C language standard provides no guarantees about the alignment or
1416  * atomicity of device memory accesses. The recommended practice for coding device
1417  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1418  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1419  * alt_write_dword() functions for 64 bit registers.
1420  *
1421  * The struct declaration for register ALT_CLKMGR_INTRRAW.
1422  */
1423 struct ALT_CLKMGR_INTRRAW_s
1424 {
1425  volatile uint32_t mainlockachieved : 1; /* raw main pll lock achieved */
1426  volatile uint32_t perlockachieved : 1; /* raw periph pll lock achieved */
1427  volatile uint32_t mainlocklost : 1; /* raw main pll lock lost */
1428  volatile uint32_t perlocklost : 1; /* raw periph pll lock lost */
1429  uint32_t : 28; /* *UNDEFINED* */
1430 };
1431 
1432 /* The typedef declaration for register ALT_CLKMGR_INTRRAW. */
1433 typedef struct ALT_CLKMGR_INTRRAW_s ALT_CLKMGR_INTRRAW_t;
1434 #endif /* __ASSEMBLY__ */
1435 
1436 /* The reset value of the ALT_CLKMGR_INTRRAW register. */
1437 #define ALT_CLKMGR_INTRRAW_RESET 0x00000000
1438 /* The byte offset of the ALT_CLKMGR_INTRRAW register from the beginning of the component. */
1439 #define ALT_CLKMGR_INTRRAW_OFST 0x20
1440 
1441 #ifndef __ASSEMBLY__
1442 /*
1443  * WARNING: The C register and register group struct declarations are provided for
1444  * convenience and illustrative purposes. They should, however, be used with
1445  * caution as the C language standard provides no guarantees about the alignment or
1446  * atomicity of device memory accesses. The recommended practice for coding device
1447  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1448  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1449  * alt_write_dword() functions for 64 bit registers.
1450  *
1451  * The struct declaration for register group ALT_CLKMGR.
1452  */
1453 struct ALT_CLKMGR_s
1454 {
1455  volatile ALT_CLKMGR_CTRL_t ctrl; /* ALT_CLKMGR_CTRL */
1456  volatile ALT_CLKMGR_STAT_t stat; /* ALT_CLKMGR_STAT */
1457  volatile ALT_CLKMGR_TESTIOCTRL_t testioctrl; /* ALT_CLKMGR_TESTIOCTRL */
1458  volatile ALT_CLKMGR_INTRGEN_t intrgen; /* ALT_CLKMGR_INTRGEN */
1459  volatile ALT_CLKMGR_INTRMSK_t intrmsk; /* ALT_CLKMGR_INTRMSK */
1460  volatile ALT_CLKMGR_INTRCLR_t intrclr; /* ALT_CLKMGR_INTRCLR */
1461  volatile ALT_CLKMGR_INTRSTS_t intrsts; /* ALT_CLKMGR_INTRSTS */
1462  volatile ALT_CLKMGR_INTRSTK_t intrstk; /* ALT_CLKMGR_INTRSTK */
1463  volatile ALT_CLKMGR_INTRRAW_t intrraw; /* ALT_CLKMGR_INTRRAW */
1464  volatile uint32_t _pad_0x24_0x2c[2]; /* *UNDEFINED* */
1465 };
1466 
1467 /* The typedef declaration for register group ALT_CLKMGR. */
1468 typedef struct ALT_CLKMGR_s ALT_CLKMGR_t;
1469 /* The struct declaration for the raw register contents of register group ALT_CLKMGR. */
1470 struct ALT_CLKMGR_raw_s
1471 {
1472  volatile uint32_t ctrl; /* ALT_CLKMGR_CTRL */
1473  volatile uint32_t stat; /* ALT_CLKMGR_STAT */
1474  volatile uint32_t testioctrl; /* ALT_CLKMGR_TESTIOCTRL */
1475  volatile uint32_t intrgen; /* ALT_CLKMGR_INTRGEN */
1476  volatile uint32_t intrmsk; /* ALT_CLKMGR_INTRMSK */
1477  volatile uint32_t intrclr; /* ALT_CLKMGR_INTRCLR */
1478  volatile uint32_t intrsts; /* ALT_CLKMGR_INTRSTS */
1479  volatile uint32_t intrstk; /* ALT_CLKMGR_INTRSTK */
1480  volatile uint32_t intrraw; /* ALT_CLKMGR_INTRRAW */
1481  volatile uint32_t _pad_0x24_0x2c[2]; /* *UNDEFINED* */
1482 };
1483 
1484 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR. */
1485 typedef struct ALT_CLKMGR_raw_s ALT_CLKMGR_raw_t;
1486 #endif /* __ASSEMBLY__ */
1487 
1488 
1489 #ifdef __cplusplus
1490 }
1491 #endif /* __cplusplus */
1492 #endif /* __ALT_SOCAL_CLKMGR_H__ */
1493