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alt_clkmgr_perpll.h
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32 
33 /* Altera - ALT_CLKMGR_PERPLL */
34 
35 #ifndef __ALT_SOCAL_CLKMGR_PERPLL_H__
36 #define __ALT_SOCAL_CLKMGR_PERPLL_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Peripheral PLL Group - CLKMGR_PERPLL
50  * Peripheral PLL Group
51  *
52  * Contains registers with settings for the Peripheral PLL.
53  *
54  */
55 /*
56  * Register : Enable Register - en
57  *
58  * Contains fields that control clock enables for clocks derived from the
59  * Peripheral PLL.
60  *
61  * 1: The clock is enabled.
62  *
63  * 0: The clock is disabled.
64  *
65  * Register Layout
66  *
67  * Bits | Access | Reset | Description
68  * :--------|:-------|:------|:---------------------
69  * [0] | RW | 0x1 | emac0_clk Enable
70  * [1] | RW | 0x1 | emac1_clk_clk Enable
71  * [2] | RW | 0x1 | emac2_clk Enable
72  * [3] | RW | 0x1 | emac_ptp_clk Enable
73  * [4] | RW | 0x1 | gpio_db_clk Enable
74  * [5] | RW | 0x1 | SDMMC Clock Enable
75  * [6] | RW | 0x1 | s2f_user1_clk Enable
76  * [7] | RW | 0x1 | PSI_REF Clock Enable
77  * [8] | RW | 0x1 | USB Clock Enable
78  * [9] | RW | 0x1 | SPIM Clock Enable
79  * [10] | RW | 0x1 | NAND Clock Enable
80  * [31:11] | ??? | 0x1 | *UNDEFINED*
81  *
82  */
83 /*
84  * Field : emac0_clk Enable - emac0en
85  *
86  * Enables clock emac0_clk output
87  *
88  * Field Access Macros:
89  *
90  */
91 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
92 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_LSB 0
93 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
94 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_MSB 0
95 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
96 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_WIDTH 1
97 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value. */
98 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET_MSK 0x00000001
99 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value. */
100 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_CLR_MSK 0xfffffffe
101 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0EN register field. */
102 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_RESET 0x1
103 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0EN field value from a register. */
104 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
105 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC0EN register field value suitable for setting the register. */
106 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
107 
108 /*
109  * Field : emac1_clk_clk Enable - emac1en
110  *
111  * Enables clock emac1_clk output
112  *
113  * Field Access Macros:
114  *
115  */
116 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
117 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_LSB 1
118 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
119 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_MSB 1
120 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
121 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_WIDTH 1
122 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value. */
123 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET_MSK 0x00000002
124 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value. */
125 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_CLR_MSK 0xfffffffd
126 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1EN register field. */
127 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_RESET 0x1
128 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1EN field value from a register. */
129 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
130 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC1EN register field value suitable for setting the register. */
131 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
132 
133 /*
134  * Field : emac2_clk Enable - emac2en
135  *
136  * Enables clock emac2_clk output
137  *
138  * Field Access Macros:
139  *
140  */
141 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
142 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_LSB 2
143 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
144 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_MSB 2
145 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
146 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_WIDTH 1
147 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value. */
148 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET_MSK 0x00000004
149 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value. */
150 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_CLR_MSK 0xfffffffb
151 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC2EN register field. */
152 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_RESET 0x1
153 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMAC2EN field value from a register. */
154 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
155 /* Produces a ALT_CLKMGR_PERPLL_EN_EMAC2EN register field value suitable for setting the register. */
156 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
157 
158 /*
159  * Field : emac_ptp_clk Enable - emacptpen
160  *
161  * Enables clock emac_ptp_clk output
162  *
163  * Field Access Macros:
164  *
165  */
166 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
167 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_LSB 3
168 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
169 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_MSB 3
170 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
171 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_WIDTH 1
172 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value. */
173 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET_MSK 0x00000008
174 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value. */
175 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_CLR_MSK 0xfffffff7
176 /* The reset value of the ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field. */
177 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_RESET 0x1
178 /* Extracts the ALT_CLKMGR_PERPLL_EN_EMACPTPEN field value from a register. */
179 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
180 /* Produces a ALT_CLKMGR_PERPLL_EN_EMACPTPEN register field value suitable for setting the register. */
181 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
182 
183 /*
184  * Field : gpio_db_clk Enable - gpiodben
185  *
186  * Enables clock gpio_db_clk output
187  *
188  * Field Access Macros:
189  *
190  */
191 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
192 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_LSB 4
193 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
194 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_MSB 4
195 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
196 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_WIDTH 1
197 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value. */
198 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET_MSK 0x00000010
199 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value. */
200 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_CLR_MSK 0xffffffef
201 /* The reset value of the ALT_CLKMGR_PERPLL_EN_GPIODBEN register field. */
202 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_RESET 0x1
203 /* Extracts the ALT_CLKMGR_PERPLL_EN_GPIODBEN field value from a register. */
204 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
205 /* Produces a ALT_CLKMGR_PERPLL_EN_GPIODBEN register field value suitable for setting the register. */
206 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
207 
208 /*
209  * Field : SDMMC Clock Enable - sdmmcclken
210  *
211  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
212  * to the SDMMC directly.
213  *
214  * Field Access Macros:
215  *
216  */
217 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
218 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_LSB 5
219 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
220 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_MSB 5
221 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
222 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_WIDTH 1
223 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value. */
224 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET_MSK 0x00000020
225 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value. */
226 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_CLR_MSK 0xffffffdf
227 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field. */
228 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_RESET 0x1
229 /* Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN field value from a register. */
230 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
231 /* Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN register field value suitable for setting the register. */
232 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
233 
234 /*
235  * Field : s2f_user1_clk Enable - s2fuser1clken
236  *
237  * Enables clock s2f_user1_clk output
238  *
239  * Field Access Macros:
240  *
241  */
242 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
243 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_LSB 6
244 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
245 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_MSB 6
246 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
247 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_WIDTH 1
248 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value. */
249 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET_MSK 0x00000040
250 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value. */
251 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
252 /* The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field. */
253 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_RESET 0x1
254 /* Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN field value from a register. */
255 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
256 /* Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN register field value suitable for setting the register. */
257 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
258 
259 /*
260  * Field : PSI_REF Clock Enable - psiclken
261  *
262  * Enables psi_ref clock.
263  *
264  * Field Access Macros:
265  *
266  */
267 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field. */
268 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_LSB 7
269 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field. */
270 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_MSB 7
271 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field. */
272 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_WIDTH 1
273 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field value. */
274 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_SET_MSK 0x00000080
275 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field value. */
276 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_CLR_MSK 0xffffff7f
277 /* The reset value of the ALT_CLKMGR_PERPLL_EN_PSICLKEN register field. */
278 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_RESET 0x1
279 /* Extracts the ALT_CLKMGR_PERPLL_EN_PSICLKEN field value from a register. */
280 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
281 /* Produces a ALT_CLKMGR_PERPLL_EN_PSICLKEN register field value suitable for setting the register. */
282 #define ALT_CLKMGR_PERPLL_EN_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
283 
284 /*
285  * Field : USB Clock Enable - usbclken
286  *
287  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
288  * the USB directly.
289  *
290  * Field Access Macros:
291  *
292  */
293 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
294 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_LSB 8
295 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
296 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_MSB 8
297 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
298 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_WIDTH 1
299 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value. */
300 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET_MSK 0x00000100
301 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value. */
302 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_CLR_MSK 0xfffffeff
303 /* The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLKEN register field. */
304 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_RESET 0x1
305 /* Extracts the ALT_CLKMGR_PERPLL_EN_USBCLKEN field value from a register. */
306 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
307 /* Produces a ALT_CLKMGR_PERPLL_EN_USBCLKEN register field value suitable for setting the register. */
308 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
309 
310 /*
311  * Field : SPIM Clock Enable - spimclken
312  *
313  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
314  * Manger to the SPIM directly.
315  *
316  * Field Access Macros:
317  *
318  */
319 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
320 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_LSB 9
321 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
322 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_MSB 9
323 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
324 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_WIDTH 1
325 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value. */
326 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET_MSK 0x00000200
327 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value. */
328 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_CLR_MSK 0xfffffdff
329 /* The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field. */
330 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_RESET 0x1
331 /* Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLKEN field value from a register. */
332 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
333 /* Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLKEN register field value suitable for setting the register. */
334 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
335 
336 /*
337  * Field : NAND Clock Enable - nandclken
338  *
339  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
340  * the NAND directly.
341  *
342  * Field Access Macros:
343  *
344  */
345 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
346 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_LSB 10
347 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
348 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_MSB 10
349 /* The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
350 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_WIDTH 1
351 /* The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value. */
352 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET_MSK 0x00000400
353 /* The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value. */
354 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_CLR_MSK 0xfffffbff
355 /* The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field. */
356 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_RESET 0x1
357 /* Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLKEN field value from a register. */
358 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
359 /* Produces a ALT_CLKMGR_PERPLL_EN_NANDCLKEN register field value suitable for setting the register. */
360 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
361 
362 #ifndef __ASSEMBLY__
363 /*
364  * WARNING: The C register and register group struct declarations are provided for
365  * convenience and illustrative purposes. They should, however, be used with
366  * caution as the C language standard provides no guarantees about the alignment or
367  * atomicity of device memory accesses. The recommended practice for coding device
368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
370  * alt_write_dword() functions for 64 bit registers.
371  *
372  * The struct declaration for register ALT_CLKMGR_PERPLL_EN.
373  */
374 struct ALT_CLKMGR_PERPLL_EN_s
375 {
376  volatile uint32_t emac0en : 1; /* emac0_clk Enable */
377  volatile uint32_t emac1en : 1; /* emac1_clk_clk Enable */
378  volatile uint32_t emac2en : 1; /* emac2_clk Enable */
379  volatile uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
380  volatile uint32_t gpiodben : 1; /* gpio_db_clk Enable */
381  volatile uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
382  volatile uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
383  volatile uint32_t psiclken : 1; /* PSI_REF Clock Enable */
384  volatile uint32_t usbclken : 1; /* USB Clock Enable */
385  volatile uint32_t spimclken : 1; /* SPIM Clock Enable */
386  volatile uint32_t nandclken : 1; /* NAND Clock Enable */
387  uint32_t : 21; /* *UNDEFINED* */
388 };
389 
390 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EN. */
391 typedef struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t;
392 #endif /* __ASSEMBLY__ */
393 
394 /* The reset value of the ALT_CLKMGR_PERPLL_EN register. */
395 #define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff
396 /* The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component. */
397 #define ALT_CLKMGR_PERPLL_EN_OFST 0x0
398 
399 /*
400  * Register : Enable Set Register - ens
401  *
402  * Write One to Set corresonding fields in Enable Register.
403  *
404  * Register Layout
405  *
406  * Bits | Access | Reset | Description
407  * :--------|:-------|:------|:---------------------
408  * [0] | RW | 0x1 | emac0_clk Enable
409  * [1] | RW | 0x1 | emac1_clk_clk Enable
410  * [2] | RW | 0x1 | emac2_clk Enable
411  * [3] | RW | 0x1 | emac_ptp_clk Enable
412  * [4] | RW | 0x1 | gpio_db_clk Enable
413  * [5] | RW | 0x1 | SDMMC Clock Enable
414  * [6] | RW | 0x1 | s2f_user1_clk Enable
415  * [7] | RW | 0x1 | PSI_REF Clock Enable
416  * [8] | RW | 0x1 | USB Clock Enable
417  * [9] | RW | 0x1 | SPIM Clock Enable
418  * [10] | RW | 0x1 | NAND Clock Enable
419  * [31:11] | ??? | 0x1 | *UNDEFINED*
420  *
421  */
422 /*
423  * Field : emac0_clk Enable - emac0en
424  *
425  * Enables clock emac0_clk output
426  *
427  * Field Access Macros:
428  *
429  */
430 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
431 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0
432 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
433 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0
434 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
435 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1
436 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value. */
437 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001
438 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value. */
439 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe
440 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field. */
441 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1
442 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC0EN field value from a register. */
443 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
444 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value suitable for setting the register. */
445 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
446 
447 /*
448  * Field : emac1_clk_clk Enable - emac1en
449  *
450  * Enables clock emac1_clk output
451  *
452  * Field Access Macros:
453  *
454  */
455 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
456 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1
457 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
458 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1
459 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
460 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1
461 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value. */
462 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002
463 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value. */
464 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd
465 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field. */
466 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1
467 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC1EN field value from a register. */
468 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
469 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value suitable for setting the register. */
470 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
471 
472 /*
473  * Field : emac2_clk Enable - emac2en
474  *
475  * Enables clock emac2_clk output
476  *
477  * Field Access Macros:
478  *
479  */
480 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
481 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2
482 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
483 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2
484 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
485 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1
486 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value. */
487 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004
488 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value. */
489 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb
490 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field. */
491 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1
492 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC2EN field value from a register. */
493 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
494 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value suitable for setting the register. */
495 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
496 
497 /*
498  * Field : emac_ptp_clk Enable - emacptpen
499  *
500  * Enables clock emac_ptp_clk output
501  *
502  * Field Access Macros:
503  *
504  */
505 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
506 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3
507 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
508 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3
509 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
510 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1
511 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value. */
512 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008
513 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value. */
514 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7
515 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field. */
516 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1
517 /* Extracts the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN field value from a register. */
518 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
519 /* Produces a ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value suitable for setting the register. */
520 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
521 
522 /*
523  * Field : gpio_db_clk Enable - gpiodben
524  *
525  * Enables clock gpio_db_clk output
526  *
527  * Field Access Macros:
528  *
529  */
530 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
531 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4
532 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
533 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4
534 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
535 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1
536 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value. */
537 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010
538 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value. */
539 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef
540 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field. */
541 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1
542 /* Extracts the ALT_CLKMGR_PERPLL_ENS_GPIODBEN field value from a register. */
543 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
544 /* Produces a ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value suitable for setting the register. */
545 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
546 
547 /*
548  * Field : SDMMC Clock Enable - sdmmcclken
549  *
550  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
551  * to the SDMMC directly.
552  *
553  * Field Access Macros:
554  *
555  */
556 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
557 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5
558 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
559 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5
560 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
561 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1
562 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value. */
563 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020
564 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value. */
565 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf
566 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field. */
567 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1
568 /* Extracts the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN field value from a register. */
569 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
570 /* Produces a ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value suitable for setting the register. */
571 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
572 
573 /*
574  * Field : s2f_user1_clk Enable - s2fuser1clken
575  *
576  * Enables clock s2f_user1_clk output
577  *
578  * Field Access Macros:
579  *
580  */
581 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
582 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6
583 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
584 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6
585 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
586 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1
587 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value. */
588 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040
589 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value. */
590 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
591 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field. */
592 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1
593 /* Extracts the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN field value from a register. */
594 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
595 /* Produces a ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value suitable for setting the register. */
596 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
597 
598 /*
599  * Field : PSI_REF Clock Enable - psiclken
600  *
601  * Enables psi_ref clock.
602  *
603  * Field Access Macros:
604  *
605  */
606 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field. */
607 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_LSB 7
608 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field. */
609 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_MSB 7
610 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field. */
611 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_WIDTH 1
612 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field value. */
613 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_SET_MSK 0x00000080
614 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field value. */
615 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_CLR_MSK 0xffffff7f
616 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field. */
617 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_RESET 0x1
618 /* Extracts the ALT_CLKMGR_PERPLL_ENS_PSICLKEN field value from a register. */
619 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
620 /* Produces a ALT_CLKMGR_PERPLL_ENS_PSICLKEN register field value suitable for setting the register. */
621 #define ALT_CLKMGR_PERPLL_ENS_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
622 
623 /*
624  * Field : USB Clock Enable - usbclken
625  *
626  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
627  * the USB directly.
628  *
629  * Field Access Macros:
630  *
631  */
632 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
633 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8
634 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
635 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8
636 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
637 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1
638 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value. */
639 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100
640 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value. */
641 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff
642 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field. */
643 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1
644 /* Extracts the ALT_CLKMGR_PERPLL_ENS_USBCLKEN field value from a register. */
645 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
646 /* Produces a ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value suitable for setting the register. */
647 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
648 
649 /*
650  * Field : SPIM Clock Enable - spimclken
651  *
652  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
653  * Manger to the SPIM directly.
654  *
655  * Field Access Macros:
656  *
657  */
658 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
659 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9
660 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
661 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9
662 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
663 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1
664 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value. */
665 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200
666 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value. */
667 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff
668 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field. */
669 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1
670 /* Extracts the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN field value from a register. */
671 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
672 /* Produces a ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value suitable for setting the register. */
673 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
674 
675 /*
676  * Field : NAND Clock Enable - nandclken
677  *
678  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
679  * the NAND directly.
680  *
681  * Field Access Macros:
682  *
683  */
684 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
685 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10
686 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
687 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10
688 /* The width in bits of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
689 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1
690 /* The mask used to set the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value. */
691 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400
692 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value. */
693 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff
694 /* The reset value of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field. */
695 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1
696 /* Extracts the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN field value from a register. */
697 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
698 /* Produces a ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value suitable for setting the register. */
699 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
700 
701 #ifndef __ASSEMBLY__
702 /*
703  * WARNING: The C register and register group struct declarations are provided for
704  * convenience and illustrative purposes. They should, however, be used with
705  * caution as the C language standard provides no guarantees about the alignment or
706  * atomicity of device memory accesses. The recommended practice for coding device
707  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
708  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
709  * alt_write_dword() functions for 64 bit registers.
710  *
711  * The struct declaration for register ALT_CLKMGR_PERPLL_ENS.
712  */
713 struct ALT_CLKMGR_PERPLL_ENS_s
714 {
715  volatile uint32_t emac0en : 1; /* emac0_clk Enable */
716  volatile uint32_t emac1en : 1; /* emac1_clk_clk Enable */
717  volatile uint32_t emac2en : 1; /* emac2_clk Enable */
718  volatile uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
719  volatile uint32_t gpiodben : 1; /* gpio_db_clk Enable */
720  volatile uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
721  volatile uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
722  volatile uint32_t psiclken : 1; /* PSI_REF Clock Enable */
723  volatile uint32_t usbclken : 1; /* USB Clock Enable */
724  volatile uint32_t spimclken : 1; /* SPIM Clock Enable */
725  volatile uint32_t nandclken : 1; /* NAND Clock Enable */
726  uint32_t : 21; /* *UNDEFINED* */
727 };
728 
729 /* The typedef declaration for register ALT_CLKMGR_PERPLL_ENS. */
730 typedef struct ALT_CLKMGR_PERPLL_ENS_s ALT_CLKMGR_PERPLL_ENS_t;
731 #endif /* __ASSEMBLY__ */
732 
733 /* The reset value of the ALT_CLKMGR_PERPLL_ENS register. */
734 #define ALT_CLKMGR_PERPLL_ENS_RESET 0x00000fff
735 /* The byte offset of the ALT_CLKMGR_PERPLL_ENS register from the beginning of the component. */
736 #define ALT_CLKMGR_PERPLL_ENS_OFST 0x4
737 
738 /*
739  * Register : Enable Reset Register - enr
740  *
741  * Write One to Clear corresponding fields in Enable Register.
742  *
743  * Register Layout
744  *
745  * Bits | Access | Reset | Description
746  * :--------|:-------|:------|:---------------------
747  * [0] | RW | 0x1 | emac0_clk Enable
748  * [1] | RW | 0x1 | emac1_clk_clk Enable
749  * [2] | RW | 0x1 | emac2_clk Enable
750  * [3] | RW | 0x1 | emac_ptp_clk Enable
751  * [4] | RW | 0x1 | gpio_db_clk Enable
752  * [5] | RW | 0x1 | SDMMC Clock Enable
753  * [6] | RW | 0x1 | s2f_user1_clk Enable
754  * [7] | RW | 0x1 | PSI_REF Clock Enable
755  * [8] | RW | 0x1 | USB Clock Enable
756  * [9] | RW | 0x1 | SPIM Clock Enable
757  * [10] | RW | 0x1 | NAND Clock Enable
758  * [31:11] | ??? | 0x1 | *UNDEFINED*
759  *
760  */
761 /*
762  * Field : emac0_clk Enable - emac0en
763  *
764  * Enables clock emac0_clk output
765  *
766  * Field Access Macros:
767  *
768  */
769 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
770 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_LSB 0
771 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
772 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_MSB 0
773 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
774 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_WIDTH 1
775 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value. */
776 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET_MSK 0x00000001
777 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value. */
778 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_CLR_MSK 0xfffffffe
779 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field. */
780 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_RESET 0x1
781 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC0EN field value from a register. */
782 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
783 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC0EN register field value suitable for setting the register. */
784 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
785 
786 /*
787  * Field : emac1_clk_clk Enable - emac1en
788  *
789  * Enables clock emac1_clk output
790  *
791  * Field Access Macros:
792  *
793  */
794 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
795 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_LSB 1
796 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
797 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_MSB 1
798 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
799 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_WIDTH 1
800 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value. */
801 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET_MSK 0x00000002
802 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value. */
803 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_CLR_MSK 0xfffffffd
804 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field. */
805 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_RESET 0x1
806 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC1EN field value from a register. */
807 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
808 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC1EN register field value suitable for setting the register. */
809 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
810 
811 /*
812  * Field : emac2_clk Enable - emac2en
813  *
814  * Enables clock emac2_clk output
815  *
816  * Field Access Macros:
817  *
818  */
819 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
820 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_LSB 2
821 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
822 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_MSB 2
823 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
824 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_WIDTH 1
825 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value. */
826 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET_MSK 0x00000004
827 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value. */
828 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_CLR_MSK 0xfffffffb
829 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field. */
830 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_RESET 0x1
831 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMAC2EN field value from a register. */
832 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
833 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMAC2EN register field value suitable for setting the register. */
834 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
835 
836 /*
837  * Field : emac_ptp_clk Enable - emacptpen
838  *
839  * Enables clock emac_ptp_clk output
840  *
841  * Field Access Macros:
842  *
843  */
844 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
845 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_LSB 3
846 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
847 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_MSB 3
848 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
849 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_WIDTH 1
850 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value. */
851 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET_MSK 0x00000008
852 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value. */
853 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_CLR_MSK 0xfffffff7
854 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field. */
855 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_RESET 0x1
856 /* Extracts the ALT_CLKMGR_PERPLL_ENR_EMACPTPEN field value from a register. */
857 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
858 /* Produces a ALT_CLKMGR_PERPLL_ENR_EMACPTPEN register field value suitable for setting the register. */
859 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
860 
861 /*
862  * Field : gpio_db_clk Enable - gpiodben
863  *
864  * Enables clock gpio_db_clk output
865  *
866  * Field Access Macros:
867  *
868  */
869 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
870 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_LSB 4
871 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
872 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_MSB 4
873 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
874 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_WIDTH 1
875 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value. */
876 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET_MSK 0x00000010
877 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value. */
878 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_CLR_MSK 0xffffffef
879 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field. */
880 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_RESET 0x1
881 /* Extracts the ALT_CLKMGR_PERPLL_ENR_GPIODBEN field value from a register. */
882 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
883 /* Produces a ALT_CLKMGR_PERPLL_ENR_GPIODBEN register field value suitable for setting the register. */
884 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
885 
886 /*
887  * Field : SDMMC Clock Enable - sdmmcclken
888  *
889  * Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger
890  * to the SDMMC directly.
891  *
892  * Field Access Macros:
893  *
894  */
895 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
896 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_LSB 5
897 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
898 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_MSB 5
899 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
900 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_WIDTH 1
901 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value. */
902 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET_MSK 0x00000020
903 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value. */
904 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_CLR_MSK 0xffffffdf
905 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field. */
906 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_RESET 0x1
907 /* Extracts the ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN field value from a register. */
908 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
909 /* Produces a ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN register field value suitable for setting the register. */
910 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
911 
912 /*
913  * Field : s2f_user1_clk Enable - s2fuser1clken
914  *
915  * Enables clock s2f_user1_clk output
916  *
917  * Field Access Macros:
918  *
919  */
920 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
921 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_LSB 6
922 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
923 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_MSB 6
924 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
925 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_WIDTH 1
926 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value. */
927 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET_MSK 0x00000040
928 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value. */
929 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
930 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field. */
931 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_RESET 0x1
932 /* Extracts the ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN field value from a register. */
933 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
934 /* Produces a ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN register field value suitable for setting the register. */
935 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
936 
937 /*
938  * Field : PSI_REF Clock Enable - psiclken
939  *
940  * Enables psi_ref clock.
941  *
942  * Field Access Macros:
943  *
944  */
945 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field. */
946 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_LSB 7
947 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field. */
948 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_MSB 7
949 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field. */
950 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_WIDTH 1
951 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field value. */
952 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_SET_MSK 0x00000080
953 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field value. */
954 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_CLR_MSK 0xffffff7f
955 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field. */
956 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_RESET 0x1
957 /* Extracts the ALT_CLKMGR_PERPLL_ENR_PSICLKEN field value from a register. */
958 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_GET(value) (((value) & 0x00000080) >> 7)
959 /* Produces a ALT_CLKMGR_PERPLL_ENR_PSICLKEN register field value suitable for setting the register. */
960 #define ALT_CLKMGR_PERPLL_ENR_PSICLKEN_SET(value) (((value) << 7) & 0x00000080)
961 
962 /*
963  * Field : USB Clock Enable - usbclken
964  *
965  * Enables USB peripheral clock. This enable goes outside of the Clock Manger to
966  * the USB directly.
967  *
968  * Field Access Macros:
969  *
970  */
971 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
972 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_LSB 8
973 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
974 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_MSB 8
975 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
976 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_WIDTH 1
977 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value. */
978 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET_MSK 0x00000100
979 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value. */
980 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_CLR_MSK 0xfffffeff
981 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field. */
982 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_RESET 0x1
983 /* Extracts the ALT_CLKMGR_PERPLL_ENR_USBCLKEN field value from a register. */
984 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
985 /* Produces a ALT_CLKMGR_PERPLL_ENR_USBCLKEN register field value suitable for setting the register. */
986 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
987 
988 /*
989  * Field : SPIM Clock Enable - spimclken
990  *
991  * Enables SPI Master peripheral clock. This enable goes outside of the Clock
992  * Manger to the SPIM directly.
993  *
994  * Field Access Macros:
995  *
996  */
997 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
998 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_LSB 9
999 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
1000 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_MSB 9
1001 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
1002 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_WIDTH 1
1003 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value. */
1004 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET_MSK 0x00000200
1005 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value. */
1006 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_CLR_MSK 0xfffffdff
1007 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field. */
1008 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_RESET 0x1
1009 /* Extracts the ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN field value from a register. */
1010 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
1011 /* Produces a ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN register field value suitable for setting the register. */
1012 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
1013 
1014 /*
1015  * Field : NAND Clock Enable - nandclken
1016  *
1017  * Enables NAND peripheral clock. This enable goes outside of the Clock Manger to
1018  * the NAND directly.
1019  *
1020  * Field Access Macros:
1021  *
1022  */
1023 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
1024 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_LSB 10
1025 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
1026 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_MSB 10
1027 /* The width in bits of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
1028 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_WIDTH 1
1029 /* The mask used to set the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value. */
1030 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET_MSK 0x00000400
1031 /* The mask used to clear the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value. */
1032 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_CLR_MSK 0xfffffbff
1033 /* The reset value of the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field. */
1034 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_RESET 0x1
1035 /* Extracts the ALT_CLKMGR_PERPLL_ENR_NANDCLKEN field value from a register. */
1036 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
1037 /* Produces a ALT_CLKMGR_PERPLL_ENR_NANDCLKEN register field value suitable for setting the register. */
1038 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
1039 
1040 #ifndef __ASSEMBLY__
1041 /*
1042  * WARNING: The C register and register group struct declarations are provided for
1043  * convenience and illustrative purposes. They should, however, be used with
1044  * caution as the C language standard provides no guarantees about the alignment or
1045  * atomicity of device memory accesses. The recommended practice for coding device
1046  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1047  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1048  * alt_write_dword() functions for 64 bit registers.
1049  *
1050  * The struct declaration for register ALT_CLKMGR_PERPLL_ENR.
1051  */
1052 struct ALT_CLKMGR_PERPLL_ENR_s
1053 {
1054  volatile uint32_t emac0en : 1; /* emac0_clk Enable */
1055  volatile uint32_t emac1en : 1; /* emac1_clk_clk Enable */
1056  volatile uint32_t emac2en : 1; /* emac2_clk Enable */
1057  volatile uint32_t emacptpen : 1; /* emac_ptp_clk Enable */
1058  volatile uint32_t gpiodben : 1; /* gpio_db_clk Enable */
1059  volatile uint32_t sdmmcclken : 1; /* SDMMC Clock Enable */
1060  volatile uint32_t s2fuser1clken : 1; /* s2f_user1_clk Enable */
1061  volatile uint32_t psiclken : 1; /* PSI_REF Clock Enable */
1062  volatile uint32_t usbclken : 1; /* USB Clock Enable */
1063  volatile uint32_t spimclken : 1; /* SPIM Clock Enable */
1064  volatile uint32_t nandclken : 1; /* NAND Clock Enable */
1065  uint32_t : 21; /* *UNDEFINED* */
1066 };
1067 
1068 /* The typedef declaration for register ALT_CLKMGR_PERPLL_ENR. */
1069 typedef struct ALT_CLKMGR_PERPLL_ENR_s ALT_CLKMGR_PERPLL_ENR_t;
1070 #endif /* __ASSEMBLY__ */
1071 
1072 /* The reset value of the ALT_CLKMGR_PERPLL_ENR register. */
1073 #define ALT_CLKMGR_PERPLL_ENR_RESET 0x00000fff
1074 /* The byte offset of the ALT_CLKMGR_PERPLL_ENR register from the beginning of the component. */
1075 #define ALT_CLKMGR_PERPLL_ENR_OFST 0x8
1076 
1077 /*
1078  * Register : Bypass Register - bypass
1079  *
1080  * Contains fields that control bypass for clocks derived from the Peripheral PLL.
1081  *
1082  * 1: The clock is bypassed.
1083  *
1084  * 0: The clock is derived from the 5:1 active mux.
1085  *
1086  * Register Layout
1087  *
1088  * Bits | Access | Reset | Description
1089  * :-------|:-------|:------|:---------------------
1090  * [0] | RW | 0x1 | EMACA Bypass
1091  * [1] | RW | 0x1 | EMACB Bypass
1092  * [2] | RW | 0x1 | EMAC PTP Bypass
1093  * [3] | RW | 0x1 | GPIO Debounce Bypass
1094  * [4] | RW | 0x1 | SDMMC Bypass
1095  * [5] | RW | 0x1 | S2F User1 Bypass
1096  * [6] | RW | 0x1 | PSI_REF Bypass
1097  * [31:7] | ??? | 0x1 | *UNDEFINED*
1098  *
1099  */
1100 /*
1101  * Field : EMACA Bypass - emaca
1102  *
1103  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
1104  * Main PLL.
1105  *
1106  * Field Access Macros:
1107  *
1108  */
1109 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
1110 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_LSB 0
1111 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
1112 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_MSB 0
1113 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
1114 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_WIDTH 1
1115 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value. */
1116 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET_MSK 0x00000001
1117 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value. */
1118 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_CLR_MSK 0xfffffffe
1119 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACA register field. */
1120 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_RESET 0x1
1121 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACA field value from a register. */
1122 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1123 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACA register field value suitable for setting the register. */
1124 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET(value) (((value) << 0) & 0x00000001)
1125 
1126 /*
1127  * Field : EMACB Bypass - emacb
1128  *
1129  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
1130  * Main PLL.
1131  *
1132  * Field Access Macros:
1133  *
1134  */
1135 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
1136 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_LSB 1
1137 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
1138 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_MSB 1
1139 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
1140 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_WIDTH 1
1141 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value. */
1142 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET_MSK 0x00000002
1143 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value. */
1144 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_CLR_MSK 0xfffffffd
1145 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACB register field. */
1146 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_RESET 0x1
1147 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACB field value from a register. */
1148 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1149 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACB register field value suitable for setting the register. */
1150 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET(value) (((value) << 1) & 0x00000002)
1151 
1152 /*
1153  * Field : EMAC PTP Bypass - emacptp
1154  *
1155  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
1156  * Peripheral PLL.
1157  *
1158  * Field Access Macros:
1159  *
1160  */
1161 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
1162 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_LSB 2
1163 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
1164 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_MSB 2
1165 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
1166 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_WIDTH 1
1167 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value. */
1168 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET_MSK 0x00000004
1169 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value. */
1170 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_CLR_MSK 0xfffffffb
1171 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field. */
1172 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_RESET 0x1
1173 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_EMACPTP field value from a register. */
1174 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1175 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_EMACPTP register field value suitable for setting the register. */
1176 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1177 
1178 /*
1179  * Field : GPIO Debounce Bypass - gpiodb
1180  *
1181  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
1182  * Peripheral PLL.
1183  *
1184  * Field Access Macros:
1185  *
1186  */
1187 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
1188 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_LSB 3
1189 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
1190 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_MSB 3
1191 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
1192 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_WIDTH 1
1193 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value. */
1194 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET_MSK 0x00000008
1195 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value. */
1196 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_CLR_MSK 0xfffffff7
1197 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field. */
1198 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_RESET 0x1
1199 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_GPIODB field value from a register. */
1200 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1201 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_GPIODB register field value suitable for setting the register. */
1202 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1203 
1204 /*
1205  * Field : SDMMC Bypass - sdmmc
1206  *
1207  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
1208  * Peripheral PLL.
1209  *
1210  * Field Access Macros:
1211  *
1212  */
1213 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
1214 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_LSB 4
1215 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
1216 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_MSB 4
1217 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
1218 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_WIDTH 1
1219 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value. */
1220 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET_MSK 0x00000010
1221 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value. */
1222 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_CLR_MSK 0xffffffef
1223 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field. */
1224 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_RESET 0x1
1225 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_SDMMC field value from a register. */
1226 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1227 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_SDMMC register field value suitable for setting the register. */
1228 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1229 
1230 /*
1231  * Field : S2F User1 Bypass - s2fuser1
1232  *
1233  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
1234  * Peripheral PLL.
1235  *
1236  * Field Access Macros:
1237  *
1238  */
1239 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
1240 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_LSB 5
1241 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
1242 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_MSB 5
1243 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
1244 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_WIDTH 1
1245 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value. */
1246 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET_MSK 0x00000020
1247 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value. */
1248 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_CLR_MSK 0xffffffdf
1249 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field. */
1250 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_RESET 0x1
1251 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 field value from a register. */
1252 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1253 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1 register field value suitable for setting the register. */
1254 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1255 
1256 /*
1257  * Field : PSI_REF Bypass - psiref
1258  *
1259  * If set, the psi_ref_clk will be bypassed to the input clock reference of the
1260  * Peripheral PLL.
1261  *
1262  * Field Access Macros:
1263  *
1264  */
1265 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field. */
1266 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_LSB 6
1267 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field. */
1268 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_MSB 6
1269 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field. */
1270 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_WIDTH 1
1271 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field value. */
1272 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_SET_MSK 0x00000040
1273 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field value. */
1274 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_CLR_MSK 0xffffffbf
1275 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field. */
1276 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_RESET 0x1
1277 /* Extracts the ALT_CLKMGR_PERPLL_BYPASS_PSIREF field value from a register. */
1278 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1279 /* Produces a ALT_CLKMGR_PERPLL_BYPASS_PSIREF register field value suitable for setting the register. */
1280 #define ALT_CLKMGR_PERPLL_BYPASS_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1281 
1282 #ifndef __ASSEMBLY__
1283 /*
1284  * WARNING: The C register and register group struct declarations are provided for
1285  * convenience and illustrative purposes. They should, however, be used with
1286  * caution as the C language standard provides no guarantees about the alignment or
1287  * atomicity of device memory accesses. The recommended practice for coding device
1288  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1289  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1290  * alt_write_dword() functions for 64 bit registers.
1291  *
1292  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASS.
1293  */
1294 struct ALT_CLKMGR_PERPLL_BYPASS_s
1295 {
1296  volatile uint32_t emaca : 1; /* EMACA Bypass */
1297  volatile uint32_t emacb : 1; /* EMACB Bypass */
1298  volatile uint32_t emacptp : 1; /* EMAC PTP Bypass */
1299  volatile uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
1300  volatile uint32_t sdmmc : 1; /* SDMMC Bypass */
1301  volatile uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
1302  volatile uint32_t psiref : 1; /* PSI_REF Bypass */
1303  uint32_t : 25; /* *UNDEFINED* */
1304 };
1305 
1306 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASS. */
1307 typedef struct ALT_CLKMGR_PERPLL_BYPASS_s ALT_CLKMGR_PERPLL_BYPASS_t;
1308 #endif /* __ASSEMBLY__ */
1309 
1310 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASS register. */
1311 #define ALT_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
1312 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASS register from the beginning of the component. */
1313 #define ALT_CLKMGR_PERPLL_BYPASS_OFST 0xc
1314 
1315 /*
1316  * Register : Bypass Set Register - bypasss
1317  *
1318  * Write One to Set corresponding fields in Bypass Register.
1319  *
1320  * Register Layout
1321  *
1322  * Bits | Access | Reset | Description
1323  * :-------|:-------|:------|:---------------------
1324  * [0] | RW | 0x1 | EMACA Bypass
1325  * [1] | RW | 0x1 | EMACB Bypass
1326  * [2] | RW | 0x1 | EMAC PTP Bypass
1327  * [3] | RW | 0x1 | GPIO Debounce Bypass
1328  * [4] | RW | 0x1 | SDMMC Bypass
1329  * [5] | RW | 0x1 | S2F User1 Bypass
1330  * [6] | RW | 0x1 | PSI_REF Bypass
1331  * [31:7] | ??? | 0x1 | *UNDEFINED*
1332  *
1333  */
1334 /*
1335  * Field : EMACA Bypass - emaca
1336  *
1337  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
1338  * Periphal PLL.
1339  *
1340  * Field Access Macros:
1341  *
1342  */
1343 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
1344 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_LSB 0
1345 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
1346 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_MSB 0
1347 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
1348 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_WIDTH 1
1349 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value. */
1350 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET_MSK 0x00000001
1351 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value. */
1352 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_CLR_MSK 0xfffffffe
1353 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field. */
1354 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_RESET 0x1
1355 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACA field value from a register. */
1356 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1357 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACA register field value suitable for setting the register. */
1358 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET(value) (((value) << 0) & 0x00000001)
1359 
1360 /*
1361  * Field : EMACB Bypass - emacb
1362  *
1363  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
1364  * Main PLL.
1365  *
1366  * Field Access Macros:
1367  *
1368  */
1369 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
1370 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_LSB 1
1371 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
1372 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_MSB 1
1373 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
1374 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_WIDTH 1
1375 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value. */
1376 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET_MSK 0x00000002
1377 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value. */
1378 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_CLR_MSK 0xfffffffd
1379 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field. */
1380 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_RESET 0x1
1381 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACB field value from a register. */
1382 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1383 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACB register field value suitable for setting the register. */
1384 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET(value) (((value) << 1) & 0x00000002)
1385 
1386 /*
1387  * Field : EMAC PTP Bypass - emacptp
1388  *
1389  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
1390  * Peripheral PLL.
1391  *
1392  * Field Access Macros:
1393  *
1394  */
1395 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
1396 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_LSB 2
1397 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
1398 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_MSB 2
1399 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
1400 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_WIDTH 1
1401 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value. */
1402 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET_MSK 0x00000004
1403 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value. */
1404 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_CLR_MSK 0xfffffffb
1405 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field. */
1406 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_RESET 0x1
1407 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP field value from a register. */
1408 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1409 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP register field value suitable for setting the register. */
1410 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1411 
1412 /*
1413  * Field : GPIO Debounce Bypass - gpiodb
1414  *
1415  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
1416  * Peripheral PLL.
1417  *
1418  * Field Access Macros:
1419  *
1420  */
1421 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
1422 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_LSB 3
1423 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
1424 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_MSB 3
1425 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
1426 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_WIDTH 1
1427 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value. */
1428 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET_MSK 0x00000008
1429 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value. */
1430 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_CLR_MSK 0xfffffff7
1431 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field. */
1432 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_RESET 0x1
1433 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_GPIODB field value from a register. */
1434 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1435 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_GPIODB register field value suitable for setting the register. */
1436 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1437 
1438 /*
1439  * Field : SDMMC Bypass - sdmmc
1440  *
1441  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
1442  * Peripheral PLL.
1443  *
1444  * Field Access Macros:
1445  *
1446  */
1447 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
1448 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_LSB 4
1449 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
1450 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_MSB 4
1451 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
1452 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_WIDTH 1
1453 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value. */
1454 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET_MSK 0x00000010
1455 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value. */
1456 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_CLR_MSK 0xffffffef
1457 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field. */
1458 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_RESET 0x1
1459 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_SDMMC field value from a register. */
1460 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1461 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_SDMMC register field value suitable for setting the register. */
1462 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1463 
1464 /*
1465  * Field : S2F User1 Bypass - s2fuser1
1466  *
1467  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
1468  * Peripheral PLL.
1469  *
1470  * Field Access Macros:
1471  *
1472  */
1473 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
1474 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_LSB 5
1475 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
1476 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_MSB 5
1477 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
1478 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_WIDTH 1
1479 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value. */
1480 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET_MSK 0x00000020
1481 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value. */
1482 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_CLR_MSK 0xffffffdf
1483 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field. */
1484 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_RESET 0x1
1485 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 field value from a register. */
1486 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1487 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1 register field value suitable for setting the register. */
1488 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1489 
1490 /*
1491  * Field : PSI_REF Bypass - psiref
1492  *
1493  * If set, the psi_ref_clk will be bypassed to the input clock reference of the
1494  * Peripheral PLL.
1495  *
1496  * Field Access Macros:
1497  *
1498  */
1499 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field. */
1500 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_LSB 6
1501 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field. */
1502 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_MSB 6
1503 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field. */
1504 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_WIDTH 1
1505 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field value. */
1506 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_SET_MSK 0x00000040
1507 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field value. */
1508 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_CLR_MSK 0xffffffbf
1509 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field. */
1510 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_RESET 0x1
1511 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSS_PSIREF field value from a register. */
1512 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1513 /* Produces a ALT_CLKMGR_PERPLL_BYPASSS_PSIREF register field value suitable for setting the register. */
1514 #define ALT_CLKMGR_PERPLL_BYPASSS_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1515 
1516 #ifndef __ASSEMBLY__
1517 /*
1518  * WARNING: The C register and register group struct declarations are provided for
1519  * convenience and illustrative purposes. They should, however, be used with
1520  * caution as the C language standard provides no guarantees about the alignment or
1521  * atomicity of device memory accesses. The recommended practice for coding device
1522  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1523  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1524  * alt_write_dword() functions for 64 bit registers.
1525  *
1526  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASSS.
1527  */
1528 struct ALT_CLKMGR_PERPLL_BYPASSS_s
1529 {
1530  volatile uint32_t emaca : 1; /* EMACA Bypass */
1531  volatile uint32_t emacb : 1; /* EMACB Bypass */
1532  volatile uint32_t emacptp : 1; /* EMAC PTP Bypass */
1533  volatile uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
1534  volatile uint32_t sdmmc : 1; /* SDMMC Bypass */
1535  volatile uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
1536  volatile uint32_t psiref : 1; /* PSI_REF Bypass */
1537  uint32_t : 25; /* *UNDEFINED* */
1538 };
1539 
1540 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASSS. */
1541 typedef struct ALT_CLKMGR_PERPLL_BYPASSS_s ALT_CLKMGR_PERPLL_BYPASSS_t;
1542 #endif /* __ASSEMBLY__ */
1543 
1544 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSS register. */
1545 #define ALT_CLKMGR_PERPLL_BYPASSS_RESET 0x000000ff
1546 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASSS register from the beginning of the component. */
1547 #define ALT_CLKMGR_PERPLL_BYPASSS_OFST 0x10
1548 
1549 /*
1550  * Register : Bypass Reset Register - bypassr
1551  *
1552  * Write One to Clear corresponding fields in Bypass Register.
1553  *
1554  * Register Layout
1555  *
1556  * Bits | Access | Reset | Description
1557  * :-------|:-------|:------|:---------------------
1558  * [0] | RW | 0x1 | EMACA Bypass
1559  * [1] | RW | 0x1 | EMACB Bypass
1560  * [2] | RW | 0x1 | EMAC PTP Bypass
1561  * [3] | RW | 0x1 | GPIO Debounce Bypass
1562  * [4] | RW | 0x1 | SDMMC Bypass
1563  * [5] | RW | 0x1 | S2F User1 Bypass
1564  * [6] | RW | 0x1 | PSI_REF Bypass
1565  * [31:7] | ??? | 0x1 | *UNDEFINED*
1566  *
1567  */
1568 /*
1569  * Field : EMACA Bypass - emaca
1570  *
1571  * If set, the emaca_free_clk will be bypassed to the input clock reference of the
1572  * Periphal PLL.
1573  *
1574  * Field Access Macros:
1575  *
1576  */
1577 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
1578 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_LSB 0
1579 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
1580 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_MSB 0
1581 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
1582 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_WIDTH 1
1583 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value. */
1584 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET_MSK 0x00000001
1585 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value. */
1586 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_CLR_MSK 0xfffffffe
1587 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field. */
1588 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_RESET 0x1
1589 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACA field value from a register. */
1590 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_GET(value) (((value) & 0x00000001) >> 0)
1591 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACA register field value suitable for setting the register. */
1592 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET(value) (((value) << 0) & 0x00000001)
1593 
1594 /*
1595  * Field : EMACB Bypass - emacb
1596  *
1597  * If set, the emacb_free_clk will be bypassed to the input clock reference of the
1598  * Main PLL.
1599  *
1600  * Field Access Macros:
1601  *
1602  */
1603 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
1604 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_LSB 1
1605 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
1606 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_MSB 1
1607 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
1608 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_WIDTH 1
1609 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value. */
1610 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET_MSK 0x00000002
1611 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value. */
1612 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_CLR_MSK 0xfffffffd
1613 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field. */
1614 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_RESET 0x1
1615 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACB field value from a register. */
1616 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_GET(value) (((value) & 0x00000002) >> 1)
1617 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACB register field value suitable for setting the register. */
1618 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET(value) (((value) << 1) & 0x00000002)
1619 
1620 /*
1621  * Field : EMAC PTP Bypass - emacptp
1622  *
1623  * If set, the emac_ptp_clk will be bypassed to the input clock reference of the
1624  * Peripheral PLL.
1625  *
1626  * Field Access Macros:
1627  *
1628  */
1629 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
1630 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_LSB 2
1631 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
1632 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_MSB 2
1633 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
1634 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_WIDTH 1
1635 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value. */
1636 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET_MSK 0x00000004
1637 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value. */
1638 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_CLR_MSK 0xfffffffb
1639 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field. */
1640 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_RESET 0x1
1641 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP field value from a register. */
1642 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
1643 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP register field value suitable for setting the register. */
1644 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
1645 
1646 /*
1647  * Field : GPIO Debounce Bypass - gpiodb
1648  *
1649  * If set, the gpio_db_clk will be bypassed to the input clock reference of the
1650  * Peripheral PLL.
1651  *
1652  * Field Access Macros:
1653  *
1654  */
1655 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
1656 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_LSB 3
1657 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
1658 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_MSB 3
1659 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
1660 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_WIDTH 1
1661 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value. */
1662 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET_MSK 0x00000008
1663 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value. */
1664 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_CLR_MSK 0xfffffff7
1665 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field. */
1666 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_RESET 0x1
1667 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_GPIODB field value from a register. */
1668 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
1669 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_GPIODB register field value suitable for setting the register. */
1670 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET(value) (((value) << 3) & 0x00000008)
1671 
1672 /*
1673  * Field : SDMMC Bypass - sdmmc
1674  *
1675  * If set, the sdmmc_clk will be bypassed to the input clock reference of the
1676  * Peripheral PLL.
1677  *
1678  * Field Access Macros:
1679  *
1680  */
1681 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
1682 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_LSB 4
1683 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
1684 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_MSB 4
1685 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
1686 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_WIDTH 1
1687 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value. */
1688 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET_MSK 0x00000010
1689 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value. */
1690 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_CLR_MSK 0xffffffef
1691 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field. */
1692 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_RESET 0x1
1693 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_SDMMC field value from a register. */
1694 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
1695 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_SDMMC register field value suitable for setting the register. */
1696 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET(value) (((value) << 4) & 0x00000010)
1697 
1698 /*
1699  * Field : S2F User1 Bypass - s2fuser1
1700  *
1701  * If set, the s2f_user1_clk will be bypassed to the input clock reference of the
1702  * Peripheral PLL.
1703  *
1704  * Field Access Macros:
1705  *
1706  */
1707 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
1708 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_LSB 5
1709 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
1710 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_MSB 5
1711 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
1712 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_WIDTH 1
1713 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value. */
1714 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET_MSK 0x00000020
1715 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value. */
1716 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_CLR_MSK 0xffffffdf
1717 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field. */
1718 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_RESET 0x1
1719 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 field value from a register. */
1720 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
1721 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1 register field value suitable for setting the register. */
1722 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
1723 
1724 /*
1725  * Field : PSI_REF Bypass - psiref
1726  *
1727  * If set, the psi_ref_clk will be bypassed to the input clock reference of the
1728  * Peripheral PLL.
1729  *
1730  * Field Access Macros:
1731  *
1732  */
1733 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field. */
1734 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_LSB 6
1735 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field. */
1736 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_MSB 6
1737 /* The width in bits of the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field. */
1738 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_WIDTH 1
1739 /* The mask used to set the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field value. */
1740 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_SET_MSK 0x00000040
1741 /* The mask used to clear the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field value. */
1742 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_CLR_MSK 0xffffffbf
1743 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field. */
1744 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_RESET 0x1
1745 /* Extracts the ALT_CLKMGR_PERPLL_BYPASSR_PSIREF field value from a register. */
1746 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_GET(value) (((value) & 0x00000040) >> 6)
1747 /* Produces a ALT_CLKMGR_PERPLL_BYPASSR_PSIREF register field value suitable for setting the register. */
1748 #define ALT_CLKMGR_PERPLL_BYPASSR_PSIREF_SET(value) (((value) << 6) & 0x00000040)
1749 
1750 #ifndef __ASSEMBLY__
1751 /*
1752  * WARNING: The C register and register group struct declarations are provided for
1753  * convenience and illustrative purposes. They should, however, be used with
1754  * caution as the C language standard provides no guarantees about the alignment or
1755  * atomicity of device memory accesses. The recommended practice for coding device
1756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1758  * alt_write_dword() functions for 64 bit registers.
1759  *
1760  * The struct declaration for register ALT_CLKMGR_PERPLL_BYPASSR.
1761  */
1762 struct ALT_CLKMGR_PERPLL_BYPASSR_s
1763 {
1764  volatile uint32_t emaca : 1; /* EMACA Bypass */
1765  volatile uint32_t emacb : 1; /* EMACB Bypass */
1766  volatile uint32_t emacptp : 1; /* EMAC PTP Bypass */
1767  volatile uint32_t gpiodb : 1; /* GPIO Debounce Bypass */
1768  volatile uint32_t sdmmc : 1; /* SDMMC Bypass */
1769  volatile uint32_t s2fuser1 : 1; /* S2F User1 Bypass */
1770  volatile uint32_t psiref : 1; /* PSI_REF Bypass */
1771  uint32_t : 25; /* *UNDEFINED* */
1772 };
1773 
1774 /* The typedef declaration for register ALT_CLKMGR_PERPLL_BYPASSR. */
1775 typedef struct ALT_CLKMGR_PERPLL_BYPASSR_s ALT_CLKMGR_PERPLL_BYPASSR_t;
1776 #endif /* __ASSEMBLY__ */
1777 
1778 /* The reset value of the ALT_CLKMGR_PERPLL_BYPASSR register. */
1779 #define ALT_CLKMGR_PERPLL_BYPASSR_RESET 0x000000ff
1780 /* The byte offset of the ALT_CLKMGR_PERPLL_BYPASSR register from the beginning of the component. */
1781 #define ALT_CLKMGR_PERPLL_BYPASSR_OFST 0x14
1782 
1783 /*
1784  * Register : Peripheral PLL Control Register for Counter 2 Clock - cntr2clk
1785  *
1786  * Contains settings that control Couner 2 clock generated from the Peripheral PLL
1787  * VCO clock.
1788  *
1789  * Register Layout
1790  *
1791  * Bits | Access | Reset | Description
1792  * :--------|:-------|:------|:-------------------------------
1793  * [10:0] | RW | 0x1 | Counter
1794  * [15:11] | ??? | 0x0 | *UNDEFINED*
1795  * [18:16] | RW | 0x1 | ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1796  * [31:19] | ??? | 0x0 | *UNDEFINED*
1797  *
1798  */
1799 /*
1800  * Field : Counter - cnt
1801  *
1802  * Divides the VCO frequency by the value+1 in this field.
1803  *
1804  * Field Access Macros:
1805  *
1806  */
1807 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
1808 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_LSB 0
1809 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
1810 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_MSB 10
1811 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
1812 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_WIDTH 11
1813 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value. */
1814 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
1815 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value. */
1816 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
1817 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field. */
1818 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_RESET 0x1
1819 /* Extracts the ALT_CLKMGR_PERPLL_CNTR2CLK_CNT field value from a register. */
1820 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1821 /* Produces a ALT_CLKMGR_PERPLL_CNTR2CLK_CNT register field value suitable for setting the register. */
1822 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1823 
1824 /*
1825  * Field : src
1826  *
1827  * Selects the source for the active 5:1 clock selection when the PLL is not
1828  * bypassed.
1829  *
1830  * Field Enumeration Values:
1831  *
1832  * Enum | Value | Description
1833  * :----------------------------------------|:------|:------------
1834  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN | 0x0 |
1835  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI | 0x1 |
1836  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 | 0x2 |
1837  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC | 0x3 |
1838  * ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA | 0x4 |
1839  *
1840  * Field Access Macros:
1841  *
1842  */
1843 /*
1844  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1845  *
1846  */
1847 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN 0x0
1848 /*
1849  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1850  *
1851  */
1852 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI 0x1
1853 /*
1854  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1855  *
1856  */
1857 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 0x2
1858 /*
1859  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1860  *
1861  */
1862 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC 0x3
1863 /*
1864  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR2CLK_SRC
1865  *
1866  */
1867 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA 0x4
1868 
1869 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
1870 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
1871 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
1872 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_MSB 18
1873 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
1874 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_WIDTH 3
1875 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value. */
1876 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET_MSK 0x00070000
1877 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value. */
1878 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_CLR_MSK 0xfff8ffff
1879 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field. */
1880 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_RESET 0x1
1881 /* Extracts the ALT_CLKMGR_PERPLL_CNTR2CLK_SRC field value from a register. */
1882 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
1883 /* Produces a ALT_CLKMGR_PERPLL_CNTR2CLK_SRC register field value suitable for setting the register. */
1884 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
1885 
1886 #ifndef __ASSEMBLY__
1887 /*
1888  * WARNING: The C register and register group struct declarations are provided for
1889  * convenience and illustrative purposes. They should, however, be used with
1890  * caution as the C language standard provides no guarantees about the alignment or
1891  * atomicity of device memory accesses. The recommended practice for coding device
1892  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1893  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1894  * alt_write_dword() functions for 64 bit registers.
1895  *
1896  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR2CLK.
1897  */
1898 struct ALT_CLKMGR_PERPLL_CNTR2CLK_s
1899 {
1900  volatile uint32_t cnt : 11; /* Counter */
1901  uint32_t : 5; /* *UNDEFINED* */
1902  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR2CLK_SRC */
1903  uint32_t : 13; /* *UNDEFINED* */
1904 };
1905 
1906 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR2CLK. */
1907 typedef struct ALT_CLKMGR_PERPLL_CNTR2CLK_s ALT_CLKMGR_PERPLL_CNTR2CLK_t;
1908 #endif /* __ASSEMBLY__ */
1909 
1910 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR2CLK register. */
1911 #define ALT_CLKMGR_PERPLL_CNTR2CLK_RESET 0x00010001
1912 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR2CLK register from the beginning of the component. */
1913 #define ALT_CLKMGR_PERPLL_CNTR2CLK_OFST 0x18
1914 
1915 /*
1916  * Register : Peripheral PLL Control Register for Counter 3 Clock - cntr3clk
1917  *
1918  * Contains settings that control Counter 3 clock generated from the Peripheral PLL
1919  * VCO clock.
1920  *
1921  * Register Layout
1922  *
1923  * Bits | Access | Reset | Description
1924  * :--------|:-------|:------|:-------------------------------
1925  * [10:0] | RW | 0x1 | Counter
1926  * [15:11] | ??? | 0x0 | *UNDEFINED*
1927  * [18:16] | RW | 0x1 | ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1928  * [31:19] | ??? | 0x0 | *UNDEFINED*
1929  *
1930  */
1931 /*
1932  * Field : Counter - cnt
1933  *
1934  * Divides the VCO frequency by the value+1 in this field.
1935  *
1936  * Field Access Macros:
1937  *
1938  */
1939 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
1940 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_LSB 0
1941 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
1942 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_MSB 10
1943 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
1944 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_WIDTH 11
1945 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value. */
1946 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
1947 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value. */
1948 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
1949 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field. */
1950 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_RESET 0x1
1951 /* Extracts the ALT_CLKMGR_PERPLL_CNTR3CLK_CNT field value from a register. */
1952 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1953 /* Produces a ALT_CLKMGR_PERPLL_CNTR3CLK_CNT register field value suitable for setting the register. */
1954 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1955 
1956 /*
1957  * Field : src
1958  *
1959  * Selects the source for the active 5:1 clock selection when the PLL is not
1960  * bypassed.
1961  *
1962  * Field Enumeration Values:
1963  *
1964  * Enum | Value | Description
1965  * :----------------------------------------|:------|:------------
1966  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN | 0x0 |
1967  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI | 0x1 |
1968  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 | 0x2 |
1969  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC | 0x3 |
1970  * ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA | 0x4 |
1971  *
1972  * Field Access Macros:
1973  *
1974  */
1975 /*
1976  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1977  *
1978  */
1979 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN 0x0
1980 /*
1981  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1982  *
1983  */
1984 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI 0x1
1985 /*
1986  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1987  *
1988  */
1989 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 0x2
1990 /*
1991  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1992  *
1993  */
1994 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC 0x3
1995 /*
1996  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR3CLK_SRC
1997  *
1998  */
1999 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA 0x4
2000 
2001 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
2002 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
2003 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
2004 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_MSB 18
2005 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
2006 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_WIDTH 3
2007 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value. */
2008 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET_MSK 0x00070000
2009 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value. */
2010 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_CLR_MSK 0xfff8ffff
2011 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field. */
2012 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_RESET 0x1
2013 /* Extracts the ALT_CLKMGR_PERPLL_CNTR3CLK_SRC field value from a register. */
2014 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2015 /* Produces a ALT_CLKMGR_PERPLL_CNTR3CLK_SRC register field value suitable for setting the register. */
2016 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2017 
2018 #ifndef __ASSEMBLY__
2019 /*
2020  * WARNING: The C register and register group struct declarations are provided for
2021  * convenience and illustrative purposes. They should, however, be used with
2022  * caution as the C language standard provides no guarantees about the alignment or
2023  * atomicity of device memory accesses. The recommended practice for coding device
2024  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2025  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2026  * alt_write_dword() functions for 64 bit registers.
2027  *
2028  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR3CLK.
2029  */
2030 struct ALT_CLKMGR_PERPLL_CNTR3CLK_s
2031 {
2032  volatile uint32_t cnt : 11; /* Counter */
2033  uint32_t : 5; /* *UNDEFINED* */
2034  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR3CLK_SRC */
2035  uint32_t : 13; /* *UNDEFINED* */
2036 };
2037 
2038 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR3CLK. */
2039 typedef struct ALT_CLKMGR_PERPLL_CNTR3CLK_s ALT_CLKMGR_PERPLL_CNTR3CLK_t;
2040 #endif /* __ASSEMBLY__ */
2041 
2042 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR3CLK register. */
2043 #define ALT_CLKMGR_PERPLL_CNTR3CLK_RESET 0x00010001
2044 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR3CLK register from the beginning of the component. */
2045 #define ALT_CLKMGR_PERPLL_CNTR3CLK_OFST 0x1c
2046 
2047 /*
2048  * Register : Peripheral PLL Control Register for Counter 4 Clock - cntr4clk
2049  *
2050  * Contains settings that control Couner 4 clock generated from the Peripheral PLL
2051  * VCO clock.
2052  *
2053  * Register Layout
2054  *
2055  * Bits | Access | Reset | Description
2056  * :--------|:-------|:------|:-------------------------------
2057  * [10:0] | RW | 0x4 | Counter
2058  * [15:11] | ??? | 0x0 | *UNDEFINED*
2059  * [18:16] | RW | 0x1 | ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2060  * [31:19] | ??? | 0x0 | *UNDEFINED*
2061  *
2062  */
2063 /*
2064  * Field : Counter - cnt
2065  *
2066  * Divides the VCO frequency by the value+1 in this field.
2067  *
2068  * Field Access Macros:
2069  *
2070  */
2071 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
2072 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_LSB 0
2073 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
2074 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_MSB 10
2075 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
2076 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_WIDTH 11
2077 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value. */
2078 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
2079 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value. */
2080 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
2081 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field. */
2082 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_RESET 0x4
2083 /* Extracts the ALT_CLKMGR_PERPLL_CNTR4CLK_CNT field value from a register. */
2084 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2085 /* Produces a ALT_CLKMGR_PERPLL_CNTR4CLK_CNT register field value suitable for setting the register. */
2086 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2087 
2088 /*
2089  * Field : src
2090  *
2091  * Selects the source for the active 5:1 clock selection when the PLL is not
2092  * bypassed.
2093  *
2094  * Field Enumeration Values:
2095  *
2096  * Enum | Value | Description
2097  * :----------------------------------------|:------|:------------
2098  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN | 0x0 |
2099  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI | 0x1 |
2100  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 | 0x2 |
2101  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC | 0x3 |
2102  * ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA | 0x4 |
2103  *
2104  * Field Access Macros:
2105  *
2106  */
2107 /*
2108  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2109  *
2110  */
2111 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN 0x0
2112 /*
2113  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2114  *
2115  */
2116 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI 0x1
2117 /*
2118  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2119  *
2120  */
2121 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 0x2
2122 /*
2123  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2124  *
2125  */
2126 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC 0x3
2127 /*
2128  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR4CLK_SRC
2129  *
2130  */
2131 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA 0x4
2132 
2133 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
2134 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
2135 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
2136 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_MSB 18
2137 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
2138 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_WIDTH 3
2139 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value. */
2140 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET_MSK 0x00070000
2141 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value. */
2142 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_CLR_MSK 0xfff8ffff
2143 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field. */
2144 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_RESET 0x1
2145 /* Extracts the ALT_CLKMGR_PERPLL_CNTR4CLK_SRC field value from a register. */
2146 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2147 /* Produces a ALT_CLKMGR_PERPLL_CNTR4CLK_SRC register field value suitable for setting the register. */
2148 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2149 
2150 #ifndef __ASSEMBLY__
2151 /*
2152  * WARNING: The C register and register group struct declarations are provided for
2153  * convenience and illustrative purposes. They should, however, be used with
2154  * caution as the C language standard provides no guarantees about the alignment or
2155  * atomicity of device memory accesses. The recommended practice for coding device
2156  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2157  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2158  * alt_write_dword() functions for 64 bit registers.
2159  *
2160  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR4CLK.
2161  */
2162 struct ALT_CLKMGR_PERPLL_CNTR4CLK_s
2163 {
2164  volatile uint32_t cnt : 11; /* Counter */
2165  uint32_t : 5; /* *UNDEFINED* */
2166  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR4CLK_SRC */
2167  uint32_t : 13; /* *UNDEFINED* */
2168 };
2169 
2170 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR4CLK. */
2171 typedef struct ALT_CLKMGR_PERPLL_CNTR4CLK_s ALT_CLKMGR_PERPLL_CNTR4CLK_t;
2172 #endif /* __ASSEMBLY__ */
2173 
2174 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR4CLK register. */
2175 #define ALT_CLKMGR_PERPLL_CNTR4CLK_RESET 0x00010004
2176 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR4CLK register from the beginning of the component. */
2177 #define ALT_CLKMGR_PERPLL_CNTR4CLK_OFST 0x20
2178 
2179 /*
2180  * Register : Peripheral PLL Control Register for Counter 5 Clock - cntr5clk
2181  *
2182  * Contains settings that control Couner 5 clock generated from the Peripheral PLL
2183  * VCO clock.
2184  *
2185  * Register Layout
2186  *
2187  * Bits | Access | Reset | Description
2188  * :--------|:-------|:------|:-------------------------------
2189  * [10:0] | RW | 0x1 | Counter
2190  * [15:11] | ??? | 0x0 | *UNDEFINED*
2191  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2192  * [31:19] | ??? | 0x0 | *UNDEFINED*
2193  *
2194  */
2195 /*
2196  * Field : Counter - cnt
2197  *
2198  * Divides the VCO frequency by the value+1 in this field.
2199  *
2200  * Field Access Macros:
2201  *
2202  */
2203 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
2204 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0
2205 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
2206 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10
2207 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
2208 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11
2209 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value. */
2210 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
2211 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value. */
2212 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
2213 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field. */
2214 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x1
2215 /* Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT field value from a register. */
2216 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2217 /* Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value suitable for setting the register. */
2218 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2219 
2220 /*
2221  * Field : src
2222  *
2223  * Selects the source for the active 5:1 clock selection when the PLL is not
2224  * bypassed.
2225  *
2226  * Field Enumeration Values:
2227  *
2228  * Enum | Value | Description
2229  * :----------------------------------------|:------|:------------
2230  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN | 0x0 |
2231  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI | 0x1 |
2232  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 | 0x2 |
2233  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC | 0x3 |
2234  * ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA | 0x4 |
2235  *
2236  * Field Access Macros:
2237  *
2238  */
2239 /*
2240  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2241  *
2242  */
2243 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN 0x0
2244 /*
2245  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2246  *
2247  */
2248 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI 0x1
2249 /*
2250  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2251  *
2252  */
2253 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 0x2
2254 /*
2255  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2256  *
2257  */
2258 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC 0x3
2259 /*
2260  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
2261  *
2262  */
2263 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA 0x4
2264 
2265 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
2266 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
2267 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
2268 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_MSB 18
2269 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
2270 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_WIDTH 3
2271 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value. */
2272 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET_MSK 0x00070000
2273 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value. */
2274 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_CLR_MSK 0xfff8ffff
2275 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field. */
2276 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_RESET 0x0
2277 /* Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC field value from a register. */
2278 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2279 /* Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value suitable for setting the register. */
2280 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2281 
2282 #ifndef __ASSEMBLY__
2283 /*
2284  * WARNING: The C register and register group struct declarations are provided for
2285  * convenience and illustrative purposes. They should, however, be used with
2286  * caution as the C language standard provides no guarantees about the alignment or
2287  * atomicity of device memory accesses. The recommended practice for coding device
2288  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2289  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2290  * alt_write_dword() functions for 64 bit registers.
2291  *
2292  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK.
2293  */
2294 struct ALT_CLKMGR_PERPLL_CNTR5CLK_s
2295 {
2296  volatile uint32_t cnt : 11; /* Counter */
2297  uint32_t : 5; /* *UNDEFINED* */
2298  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR5CLK_SRC */
2299  uint32_t : 13; /* *UNDEFINED* */
2300 };
2301 
2302 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK. */
2303 typedef struct ALT_CLKMGR_PERPLL_CNTR5CLK_s ALT_CLKMGR_PERPLL_CNTR5CLK_t;
2304 #endif /* __ASSEMBLY__ */
2305 
2306 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK register. */
2307 #define ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000001
2308 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR5CLK register from the beginning of the component. */
2309 #define ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x24
2310 
2311 /*
2312  * Register : Peripheral PLL Control Register for Counter 6 Clock - cntr6clk
2313  *
2314  * Contains settings that control Couner 6 clock generated from the Peripheral PLL
2315  * VCO clock.
2316  *
2317  * Register Layout
2318  *
2319  * Bits | Access | Reset | Description
2320  * :--------|:-------|:------|:-------------------------------
2321  * [10:0] | RW | 0x1 | Counter
2322  * [15:11] | ??? | 0x0 | *UNDEFINED*
2323  * [18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2324  * [31:19] | ??? | 0x0 | *UNDEFINED*
2325  *
2326  */
2327 /*
2328  * Field : Counter - cnt
2329  *
2330  * Divides the VCO frequency by the value+1 in this field.
2331  *
2332  * Field Access Macros:
2333  *
2334  */
2335 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
2336 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_LSB 0
2337 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
2338 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_MSB 10
2339 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
2340 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_WIDTH 11
2341 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value. */
2342 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
2343 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value. */
2344 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
2345 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field. */
2346 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_RESET 0x1
2347 /* Extracts the ALT_CLKMGR_PERPLL_CNTR6CLK_CNT field value from a register. */
2348 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2349 /* Produces a ALT_CLKMGR_PERPLL_CNTR6CLK_CNT register field value suitable for setting the register. */
2350 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2351 
2352 /*
2353  * Field : src
2354  *
2355  * Selects the source for the active 5:1 clock selection when the PLL is not
2356  * bypassed.
2357  *
2358  * Field Enumeration Values:
2359  *
2360  * Enum | Value | Description
2361  * :----------------------------------------|:------|:------------
2362  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN | 0x0 |
2363  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI | 0x1 |
2364  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 | 0x2 |
2365  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC | 0x3 |
2366  * ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA | 0x4 |
2367  *
2368  * Field Access Macros:
2369  *
2370  */
2371 /*
2372  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2373  *
2374  */
2375 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN 0x0
2376 /*
2377  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2378  *
2379  */
2380 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI 0x1
2381 /*
2382  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2383  *
2384  */
2385 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 0x2
2386 /*
2387  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2388  *
2389  */
2390 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC 0x3
2391 /*
2392  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR6CLK_SRC
2393  *
2394  */
2395 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA 0x4
2396 
2397 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
2398 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
2399 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
2400 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_MSB 18
2401 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
2402 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_WIDTH 3
2403 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value. */
2404 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET_MSK 0x00070000
2405 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value. */
2406 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_CLR_MSK 0xfff8ffff
2407 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field. */
2408 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_RESET 0x0
2409 /* Extracts the ALT_CLKMGR_PERPLL_CNTR6CLK_SRC field value from a register. */
2410 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2411 /* Produces a ALT_CLKMGR_PERPLL_CNTR6CLK_SRC register field value suitable for setting the register. */
2412 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2413 
2414 #ifndef __ASSEMBLY__
2415 /*
2416  * WARNING: The C register and register group struct declarations are provided for
2417  * convenience and illustrative purposes. They should, however, be used with
2418  * caution as the C language standard provides no guarantees about the alignment or
2419  * atomicity of device memory accesses. The recommended practice for coding device
2420  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2421  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2422  * alt_write_dword() functions for 64 bit registers.
2423  *
2424  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR6CLK.
2425  */
2426 struct ALT_CLKMGR_PERPLL_CNTR6CLK_s
2427 {
2428  volatile uint32_t cnt : 11; /* Counter */
2429  uint32_t : 5; /* *UNDEFINED* */
2430  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR6CLK_SRC */
2431  uint32_t : 13; /* *UNDEFINED* */
2432 };
2433 
2434 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR6CLK. */
2435 typedef struct ALT_CLKMGR_PERPLL_CNTR6CLK_s ALT_CLKMGR_PERPLL_CNTR6CLK_t;
2436 #endif /* __ASSEMBLY__ */
2437 
2438 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR6CLK register. */
2439 #define ALT_CLKMGR_PERPLL_CNTR6CLK_RESET 0x00000001
2440 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR6CLK register from the beginning of the component. */
2441 #define ALT_CLKMGR_PERPLL_CNTR6CLK_OFST 0x28
2442 
2443 /*
2444  * Register : Peripheral PLL Control Register for Counter 7 Clock - cntr7clk
2445  *
2446  * Contains settings that control Couner 7 clock generated from the Peripheral PLL
2447  * VCO clock.
2448  *
2449  * Register Layout
2450  *
2451  * Bits | Access | Reset | Description
2452  * :--------|:-------|:------|:------------
2453  * [10:0] | RW | 0x0 | Counter
2454  * [31:11] | ??? | 0x0 | *UNDEFINED*
2455  *
2456  */
2457 /*
2458  * Field : Counter - cnt
2459  *
2460  * Divides the VCO frequency by the value+1 in this field.
2461  *
2462  * Field Access Macros:
2463  *
2464  */
2465 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
2466 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_LSB 0
2467 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
2468 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_MSB 10
2469 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
2470 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_WIDTH 11
2471 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value. */
2472 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
2473 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value. */
2474 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
2475 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field. */
2476 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_RESET 0x0
2477 /* Extracts the ALT_CLKMGR_PERPLL_CNTR7CLK_CNT field value from a register. */
2478 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2479 /* Produces a ALT_CLKMGR_PERPLL_CNTR7CLK_CNT register field value suitable for setting the register. */
2480 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2481 
2482 #ifndef __ASSEMBLY__
2483 /*
2484  * WARNING: The C register and register group struct declarations are provided for
2485  * convenience and illustrative purposes. They should, however, be used with
2486  * caution as the C language standard provides no guarantees about the alignment or
2487  * atomicity of device memory accesses. The recommended practice for coding device
2488  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2489  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2490  * alt_write_dword() functions for 64 bit registers.
2491  *
2492  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR7CLK.
2493  */
2494 struct ALT_CLKMGR_PERPLL_CNTR7CLK_s
2495 {
2496  volatile uint32_t cnt : 11; /* Counter */
2497  uint32_t : 21; /* *UNDEFINED* */
2498 };
2499 
2500 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR7CLK. */
2501 typedef struct ALT_CLKMGR_PERPLL_CNTR7CLK_s ALT_CLKMGR_PERPLL_CNTR7CLK_t;
2502 #endif /* __ASSEMBLY__ */
2503 
2504 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR7CLK register. */
2505 #define ALT_CLKMGR_PERPLL_CNTR7CLK_RESET 0x00000000
2506 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR7CLK register from the beginning of the component. */
2507 #define ALT_CLKMGR_PERPLL_CNTR7CLK_OFST 0x2c
2508 
2509 /*
2510  * Register : Peripheral PLL Control Register for Counter 8 Clock - cntr8clk
2511  *
2512  * Contains settings that control Couner 8 clock generated from the Peripheral PLL
2513  * VCO clock.
2514  *
2515  * Register Layout
2516  *
2517  * Bits | Access | Reset | Description
2518  * :--------|:-------|:------|:-------------------------------
2519  * [10:0] | RW | 0x0 | Counter
2520  * [15:11] | ??? | 0x0 | *UNDEFINED*
2521  * [18:16] | RW | 0x1 | ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2522  * [31:19] | ??? | 0x0 | *UNDEFINED*
2523  *
2524  */
2525 /*
2526  * Field : Counter - cnt
2527  *
2528  * Divides the VCO frequency by the value+1 in this field.
2529  *
2530  * Field Access Macros:
2531  *
2532  */
2533 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
2534 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_LSB 0
2535 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
2536 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_MSB 10
2537 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
2538 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_WIDTH 11
2539 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value. */
2540 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
2541 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value. */
2542 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
2543 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field. */
2544 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_RESET 0x0
2545 /* Extracts the ALT_CLKMGR_PERPLL_CNTR8CLK_CNT field value from a register. */
2546 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2547 /* Produces a ALT_CLKMGR_PERPLL_CNTR8CLK_CNT register field value suitable for setting the register. */
2548 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2549 
2550 /*
2551  * Field : src
2552  *
2553  * Selects the source for the active 5:1 clock selection when the PLL is not
2554  * bypassed.
2555  *
2556  * Field Enumeration Values:
2557  *
2558  * Enum | Value | Description
2559  * :----------------------------------------|:------|:------------
2560  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN | 0x0 |
2561  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI | 0x1 |
2562  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 | 0x2 |
2563  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC | 0x3 |
2564  * ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA | 0x4 |
2565  *
2566  * Field Access Macros:
2567  *
2568  */
2569 /*
2570  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2571  *
2572  */
2573 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN 0x0
2574 /*
2575  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2576  *
2577  */
2578 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI 0x1
2579 /*
2580  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2581  *
2582  */
2583 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 0x2
2584 /*
2585  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2586  *
2587  */
2588 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC 0x3
2589 /*
2590  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR8CLK_SRC
2591  *
2592  */
2593 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA 0x4
2594 
2595 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
2596 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
2597 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
2598 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_MSB 18
2599 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
2600 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_WIDTH 3
2601 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value. */
2602 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET_MSK 0x00070000
2603 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value. */
2604 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_CLR_MSK 0xfff8ffff
2605 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field. */
2606 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_RESET 0x1
2607 /* Extracts the ALT_CLKMGR_PERPLL_CNTR8CLK_SRC field value from a register. */
2608 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2609 /* Produces a ALT_CLKMGR_PERPLL_CNTR8CLK_SRC register field value suitable for setting the register. */
2610 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2611 
2612 #ifndef __ASSEMBLY__
2613 /*
2614  * WARNING: The C register and register group struct declarations are provided for
2615  * convenience and illustrative purposes. They should, however, be used with
2616  * caution as the C language standard provides no guarantees about the alignment or
2617  * atomicity of device memory accesses. The recommended practice for coding device
2618  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2619  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2620  * alt_write_dword() functions for 64 bit registers.
2621  *
2622  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR8CLK.
2623  */
2624 struct ALT_CLKMGR_PERPLL_CNTR8CLK_s
2625 {
2626  volatile uint32_t cnt : 11; /* Counter */
2627  uint32_t : 5; /* *UNDEFINED* */
2628  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR8CLK_SRC */
2629  uint32_t : 13; /* *UNDEFINED* */
2630 };
2631 
2632 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR8CLK. */
2633 typedef struct ALT_CLKMGR_PERPLL_CNTR8CLK_s ALT_CLKMGR_PERPLL_CNTR8CLK_t;
2634 #endif /* __ASSEMBLY__ */
2635 
2636 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR8CLK register. */
2637 #define ALT_CLKMGR_PERPLL_CNTR8CLK_RESET 0x00010000
2638 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR8CLK register from the beginning of the component. */
2639 #define ALT_CLKMGR_PERPLL_CNTR8CLK_OFST 0x30
2640 
2641 /*
2642  * Register : periph PLL Control Register for Counter 10 Clock - cntr9clk
2643  *
2644  * Contains settings that control Couner 10 clock generated from the periph PLL VCO
2645  * clock.
2646  *
2647  * Register Layout
2648  *
2649  * Bits | Access | Reset | Description
2650  * :--------|:-------|:------|:-------------------------------
2651  * [10:0] | RW | 0x0 | Counter
2652  * [15:11] | ??? | 0x0 | *UNDEFINED*
2653  * [18:16] | RW | 0x1 | ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2654  * [31:19] | ??? | 0x0 | *UNDEFINED*
2655  *
2656  */
2657 /*
2658  * Field : Counter - cnt
2659  *
2660  * Divides the VCO frequency by the value+1 in this field.
2661  *
2662  * Field Access Macros:
2663  *
2664  */
2665 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
2666 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_LSB 0
2667 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
2668 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_MSB 10
2669 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
2670 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_WIDTH 11
2671 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value. */
2672 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
2673 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value. */
2674 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
2675 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field. */
2676 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_RESET 0x0
2677 /* Extracts the ALT_CLKMGR_PERPLL_CNTR9CLK_CNT field value from a register. */
2678 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
2679 /* Produces a ALT_CLKMGR_PERPLL_CNTR9CLK_CNT register field value suitable for setting the register. */
2680 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
2681 
2682 /*
2683  * Field : src
2684  *
2685  * Selects the source for the active 5:1 clock selection when the PLL is not
2686  * bypassed.
2687  *
2688  * Field Enumeration Values:
2689  *
2690  * Enum | Value | Description
2691  * :----------------------------------------|:------|:------------
2692  * ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_MAIN | 0x0 |
2693  * ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_PERI | 0x1 |
2694  * ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_OSC1 | 0x2 |
2695  * ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_INTOSC | 0x3 |
2696  * ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_FPGA | 0x4 |
2697  *
2698  * Field Access Macros:
2699  *
2700  */
2701 /*
2702  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2703  *
2704  */
2705 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_MAIN 0x0
2706 /*
2707  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2708  *
2709  */
2710 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_PERI 0x1
2711 /*
2712  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2713  *
2714  */
2715 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_OSC1 0x2
2716 /*
2717  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2718  *
2719  */
2720 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_INTOSC 0x3
2721 /*
2722  * Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR9CLK_SRC
2723  *
2724  */
2725 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_E_FPGA 0x4
2726 
2727 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field. */
2728 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_LSB 16
2729 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field. */
2730 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_MSB 18
2731 /* The width in bits of the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field. */
2732 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_WIDTH 3
2733 /* The mask used to set the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field value. */
2734 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_SET_MSK 0x00070000
2735 /* The mask used to clear the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field value. */
2736 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_CLR_MSK 0xfff8ffff
2737 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field. */
2738 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_RESET 0x1
2739 /* Extracts the ALT_CLKMGR_PERPLL_CNTR9CLK_SRC field value from a register. */
2740 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
2741 /* Produces a ALT_CLKMGR_PERPLL_CNTR9CLK_SRC register field value suitable for setting the register. */
2742 #define ALT_CLKMGR_PERPLL_CNTR9CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
2743 
2744 #ifndef __ASSEMBLY__
2745 /*
2746  * WARNING: The C register and register group struct declarations are provided for
2747  * convenience and illustrative purposes. They should, however, be used with
2748  * caution as the C language standard provides no guarantees about the alignment or
2749  * atomicity of device memory accesses. The recommended practice for coding device
2750  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2751  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2752  * alt_write_dword() functions for 64 bit registers.
2753  *
2754  * The struct declaration for register ALT_CLKMGR_PERPLL_CNTR9CLK.
2755  */
2756 struct ALT_CLKMGR_PERPLL_CNTR9CLK_s
2757 {
2758  volatile uint32_t cnt : 11; /* Counter */
2759  uint32_t : 5; /* *UNDEFINED* */
2760  volatile uint32_t src : 3; /* ALT_CLKMGR_PERPLL_CNTR9CLK_SRC */
2761  uint32_t : 13; /* *UNDEFINED* */
2762 };
2763 
2764 /* The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR9CLK. */
2765 typedef struct ALT_CLKMGR_PERPLL_CNTR9CLK_s ALT_CLKMGR_PERPLL_CNTR9CLK_t;
2766 #endif /* __ASSEMBLY__ */
2767 
2768 /* The reset value of the ALT_CLKMGR_PERPLL_CNTR9CLK register. */
2769 #define ALT_CLKMGR_PERPLL_CNTR9CLK_RESET 0x00010000
2770 /* The byte offset of the ALT_CLKMGR_PERPLL_CNTR9CLK register from the beginning of the component. */
2771 #define ALT_CLKMGR_PERPLL_CNTR9CLK_OFST 0x34
2772 
2773 /*
2774  * Register : Main Divide Register - emacctl
2775  *
2776  * Contains fields that control clock dividers for main clocks derived from the
2777  * Main PLL
2778  *
2779  * Register Layout
2780  *
2781  * Bits | Access | Reset | Description
2782  * :--------|:-------|:------|:-------------------
2783  * [25:0] | ??? | 0x0 | *UNDEFINED*
2784  * [26] | RW | 0x0 | EMAC0 clock select
2785  * [27] | RW | 0x0 | EMAC1 clock select
2786  * [28] | RW | 0x0 | EMAC2 clock select
2787  * [31:29] | ??? | 0x0 | *UNDEFINED*
2788  *
2789  */
2790 /*
2791  * Field : EMAC0 clock select - emac0sel
2792  *
2793  * Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk.
2794  *
2795  * Field Enumeration Values:
2796  *
2797  * Enum | Value | Description
2798  * :-------------------------------------------|:------|:------------
2799  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA | 0x0 | EMAC A
2800  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB | 0x1 | EMAC B
2801  *
2802  * Field Access Macros:
2803  *
2804  */
2805 /*
2806  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
2807  *
2808  * EMAC A
2809  */
2810 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0
2811 /*
2812  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
2813  *
2814  * EMAC B
2815  */
2816 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1
2817 
2818 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
2819 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
2820 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
2821 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26
2822 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
2823 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1
2824 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value. */
2825 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000
2826 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value. */
2827 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff
2828 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field. */
2829 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0
2830 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL field value from a register. */
2831 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET(value) (((value) & 0x04000000) >> 26)
2832 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value suitable for setting the register. */
2833 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET(value) (((value) << 26) & 0x04000000)
2834 
2835 /*
2836  * Field : EMAC1 clock select - emac1sel
2837  *
2838  * Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk.
2839  *
2840  * Field Enumeration Values:
2841  *
2842  * Enum | Value | Description
2843  * :-------------------------------------------|:------|:------------
2844  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA | 0x0 | EMAC A
2845  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB | 0x1 | EMAC B
2846  *
2847  * Field Access Macros:
2848  *
2849  */
2850 /*
2851  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
2852  *
2853  * EMAC A
2854  */
2855 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0
2856 /*
2857  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
2858  *
2859  * EMAC B
2860  */
2861 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1
2862 
2863 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
2864 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
2865 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
2866 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27
2867 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
2868 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1
2869 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value. */
2870 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000
2871 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value. */
2872 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff
2873 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field. */
2874 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0
2875 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL field value from a register. */
2876 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET(value) (((value) & 0x08000000) >> 27)
2877 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value suitable for setting the register. */
2878 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET(value) (((value) << 27) & 0x08000000)
2879 
2880 /*
2881  * Field : EMAC2 clock select - emac2sel
2882  *
2883  * Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk.
2884  *
2885  * Field Enumeration Values:
2886  *
2887  * Enum | Value | Description
2888  * :-------------------------------------------|:------|:------------
2889  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA | 0x0 | EMAC A
2890  * ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB | 0x1 | EMAC B
2891  *
2892  * Field Access Macros:
2893  *
2894  */
2895 /*
2896  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
2897  *
2898  * EMAC A
2899  */
2900 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0
2901 /*
2902  * Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
2903  *
2904  * EMAC B
2905  */
2906 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1
2907 
2908 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
2909 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
2910 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
2911 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28
2912 /* The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
2913 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1
2914 /* The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value. */
2915 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000
2916 /* The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value. */
2917 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff
2918 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field. */
2919 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0
2920 /* Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL field value from a register. */
2921 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET(value) (((value) & 0x10000000) >> 28)
2922 /* Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value suitable for setting the register. */
2923 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET(value) (((value) << 28) & 0x10000000)
2924 
2925 #ifndef __ASSEMBLY__
2926 /*
2927  * WARNING: The C register and register group struct declarations are provided for
2928  * convenience and illustrative purposes. They should, however, be used with
2929  * caution as the C language standard provides no guarantees about the alignment or
2930  * atomicity of device memory accesses. The recommended practice for coding device
2931  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2932  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2933  * alt_write_dword() functions for 64 bit registers.
2934  *
2935  * The struct declaration for register ALT_CLKMGR_PERPLL_EMACCTL.
2936  */
2937 struct ALT_CLKMGR_PERPLL_EMACCTL_s
2938 {
2939  uint32_t : 26; /* *UNDEFINED* */
2940  volatile uint32_t emac0sel : 1; /* EMAC0 clock select */
2941  volatile uint32_t emac1sel : 1; /* EMAC1 clock select */
2942  volatile uint32_t emac2sel : 1; /* EMAC2 clock select */
2943  uint32_t : 3; /* *UNDEFINED* */
2944 };
2945 
2946 /* The typedef declaration for register ALT_CLKMGR_PERPLL_EMACCTL. */
2947 typedef struct ALT_CLKMGR_PERPLL_EMACCTL_s ALT_CLKMGR_PERPLL_EMACCTL_t;
2948 #endif /* __ASSEMBLY__ */
2949 
2950 /* The reset value of the ALT_CLKMGR_PERPLL_EMACCTL register. */
2951 #define ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000
2952 /* The byte offset of the ALT_CLKMGR_PERPLL_EMACCTL register from the beginning of the component. */
2953 #define ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x38
2954 
2955 /*
2956  * Register : GPIO Divide Register - gpiodiv
2957  *
2958  * Contains a field that controls the clock divider for the GPIO De-bounce clock.
2959  *
2960  * Register Layout
2961  *
2962  * Bits | Access | Reset | Description
2963  * :--------|:-------|:------|:-----------------------------
2964  * [15:0] | RW | 0x1 | GPIO De-bounce Clock Divider
2965  * [31:16] | ??? | 0x0 | *UNDEFINED*
2966  *
2967  */
2968 /*
2969  * Field : GPIO De-bounce Clock Divider - gpiodbclk
2970  *
2971  * The gpio_db_clk is divided down from the periph_base_clk by the value plus one
2972  * specified in this field. The value 0 (divide by 1) is illegal. A value of 1
2973  * indicates divide by 2, 2 divide by 3, etc.
2974  *
2975  * Field Access Macros:
2976  *
2977  */
2978 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
2979 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
2980 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
2981 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 15
2982 /* The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
2983 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 16
2984 /* The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
2985 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x0000ffff
2986 /* The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value. */
2987 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xffff0000
2988 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field. */
2989 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
2990 /* Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register. */
2991 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x0000ffff) >> 0)
2992 /* Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register. */
2993 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x0000ffff)
2994 
2995 #ifndef __ASSEMBLY__
2996 /*
2997  * WARNING: The C register and register group struct declarations are provided for
2998  * convenience and illustrative purposes. They should, however, be used with
2999  * caution as the C language standard provides no guarantees about the alignment or
3000  * atomicity of device memory accesses. The recommended practice for coding device
3001  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3002  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3003  * alt_write_dword() functions for 64 bit registers.
3004  *
3005  * The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.
3006  */
3007 struct ALT_CLKMGR_PERPLL_GPIODIV_s
3008 {
3009  volatile uint32_t gpiodbclk : 16; /* GPIO De-bounce Clock Divider */
3010  uint32_t : 16; /* *UNDEFINED* */
3011 };
3012 
3013 /* The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV. */
3014 typedef struct ALT_CLKMGR_PERPLL_GPIODIV_s ALT_CLKMGR_PERPLL_GPIODIV_t;
3015 #endif /* __ASSEMBLY__ */
3016 
3017 /* The reset value of the ALT_CLKMGR_PERPLL_GPIODIV register. */
3018 #define ALT_CLKMGR_PERPLL_GPIODIV_RESET 0x00000001
3019 /* The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component. */
3020 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x3c
3021 
3022 /*
3023  * Register : pllglob
3024  *
3025  * This refects register settings for both the channels of the periph PLL
3026  *
3027  * Register Layout
3028  *
3029  * Bits | Access | Reset | Description
3030  * :--------|:-------|:------|:------------------------------------
3031  * [0] | RW | 0x0 | main PLL power down
3032  * [1] | RW | 0x0 | main PLL reset
3033  * [2] | RW | 0x0 | main PLL mute
3034  * [3] | RW | 0x0 | Int mode sel
3035  * [4] | RW | 0x0 | Bypass clock source select control
3036  * [7:5] | ??? | 0x0 | *UNDEFINED*
3037  * [13:8] | RW | 0x1 | ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV
3038  * [15:14] | ??? | 0x0 | *UNDEFINED*
3039  * [17:16] | RW | 0x0 | Clock Source
3040  * [31:18] | ??? | 0x0 | *UNDEFINED*
3041  *
3042  */
3043 /*
3044  * Field : main PLL power down - pd
3045  *
3046  * PLL Disable/Power-Down Control:
3047  *
3048  * 1: PLL Analog circuits are Enabled;
3049  *
3050  * 0: PLL is Disabled.
3051  *
3052  * By default the signal is asserted. Software should come and write '1' in this
3053  * reg to bring up the PLL
3054  *
3055  * Field Enumeration Values:
3056  *
3057  * Enum | Value | Description
3058  * :-----------------------------------------|:------|:------------
3059  * ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERDOWN | 0x0 |
3060  * ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERUP | 0x1 |
3061  *
3062  * Field Access Macros:
3063  *
3064  */
3065 /*
3066  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_PD
3067  *
3068  */
3069 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERDOWN 0x0
3070 /*
3071  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_PD
3072  *
3073  */
3074 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_E_POWERUP 0x1
3075 
3076 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field. */
3077 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_LSB 0
3078 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field. */
3079 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_MSB 0
3080 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field. */
3081 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_WIDTH 1
3082 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field value. */
3083 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
3084 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field value. */
3085 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_CLR_MSK 0xfffffffe
3086 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_PD register field. */
3087 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_RESET 0x0
3088 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_PD field value from a register. */
3089 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_GET(value) (((value) & 0x00000001) >> 0)
3090 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_PD register field value suitable for setting the register. */
3091 #define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET(value) (((value) << 0) & 0x00000001)
3092 
3093 /*
3094  * Field : main PLL reset - rst
3095  *
3096  * PLL Reset. Used to power down and initialize the synthesizer. Must be asserted
3097  * when power supply pins are applied.
3098  *
3099  * 1- Hard Reset Is De-Asserted;
3100  *
3101  * 0-Hard Reset Is Asserted.
3102  *
3103  * By default the signal is asserted. Software should come and write '1' in this
3104  * reg to bring up the PLL
3105  *
3106  * Field Access Macros:
3107  *
3108  */
3109 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field. */
3110 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_LSB 1
3111 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field. */
3112 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_MSB 1
3113 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field. */
3114 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_WIDTH 1
3115 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field value. */
3116 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
3117 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field value. */
3118 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_CLR_MSK 0xfffffffd
3119 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_RST register field. */
3120 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_RESET 0x0
3121 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_RST field value from a register. */
3122 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_GET(value) (((value) & 0x00000002) >> 1)
3123 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_RST register field value suitable for setting the register. */
3124 #define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET(value) (((value) << 1) & 0x00000002)
3125 
3126 /*
3127  * Field : main PLL mute - mute
3128  *
3129  * Mutes All PLL Outputs Glitch-Free:
3130  *
3131  * 1 - Output Clocks Are Muted To 1'B0;
3132  *
3133  * 0 - Output Clocks Are Active
3134  *
3135  * Field Enumeration Values:
3136  *
3137  * Enum | Value | Description
3138  * :----------------------------------------|:------|:------------
3139  * ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_UNMUTE | 0x0 |
3140  * ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_MUTE | 0x1 |
3141  *
3142  * Field Access Macros:
3143  *
3144  */
3145 /*
3146  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_MUTE
3147  *
3148  */
3149 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_UNMUTE 0x0
3150 /*
3151  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_MUTE
3152  *
3153  */
3154 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_E_MUTE 0x1
3155 
3156 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field. */
3157 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_LSB 2
3158 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field. */
3159 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_MSB 2
3160 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field. */
3161 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_WIDTH 1
3162 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field value. */
3163 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_SET_MSK 0x00000004
3164 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field value. */
3165 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_CLR_MSK 0xfffffffb
3166 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field. */
3167 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_RESET 0x0
3168 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_MUTE field value from a register. */
3169 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_GET(value) (((value) & 0x00000004) >> 2)
3170 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_MUTE register field value suitable for setting the register. */
3171 #define ALT_CLKMGR_PERPLL_PLLGLOB_MUTE_SET(value) (((value) << 2) & 0x00000004)
3172 
3173 /*
3174  * Field : Int mode sel - modsel
3175  *
3176  * terger mode, feedback divident to PLL is considered integer. It can be only set
3177  * while the PLL is at reset or power down state. It cannot be switched
3178  * dynamically.
3179  *
3180  * Select: 1'B1 - Fractional Mode
3181  *
3182  * 1'B0 - Integer Mode;
3183  *
3184  * Field Enumeration Values:
3185  *
3186  * Enum | Value | Description
3187  * :-----------------------------------------|:------|:------------
3188  * ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_INT | 0x0 |
3189  * ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_FLOAT | 0x1 |
3190  *
3191  * Field Access Macros:
3192  *
3193  */
3194 /*
3195  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL
3196  *
3197  */
3198 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_INT 0x0
3199 /*
3200  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL
3201  *
3202  */
3203 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_E_FLOAT 0x1
3204 
3205 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field. */
3206 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_LSB 3
3207 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field. */
3208 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_MSB 3
3209 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field. */
3210 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_WIDTH 1
3211 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field value. */
3212 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_SET_MSK 0x00000008
3213 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field value. */
3214 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_CLR_MSK 0xfffffff7
3215 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field. */
3216 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_RESET 0x0
3217 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL field value from a register. */
3218 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_GET(value) (((value) & 0x00000008) >> 3)
3219 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL register field value suitable for setting the register. */
3220 #define ALT_CLKMGR_PERPLL_PLLGLOB_MODSEL_SET(value) (((value) << 3) & 0x00000008)
3221 
3222 /*
3223  * Field : Bypass clock source select control - bysctl
3224  *
3225  * This bit is resposible for selecting source for bypass clock in PLL bypass mode.
3226  * In the current version of the PLL. this feature is not supported.
3227  *
3228  * Therefore it can be '0' or '1'. The value does not matter at all.
3229  *
3230  * Making it '0' by defaut
3231  *
3232  * Field Access Macros:
3233  *
3234  */
3235 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field. */
3236 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_LSB 4
3237 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field. */
3238 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_MSB 4
3239 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field. */
3240 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_WIDTH 1
3241 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field value. */
3242 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_SET_MSK 0x00000010
3243 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field value. */
3244 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_CLR_MSK 0xffffffef
3245 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field. */
3246 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_RESET 0x0
3247 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL field value from a register. */
3248 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_GET(value) (((value) & 0x00000010) >> 4)
3249 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL register field value suitable for setting the register. */
3250 #define ALT_CLKMGR_PERPLL_PLLGLOB_BYSCTL_SET(value) (((value) << 4) & 0x00000010)
3251 
3252 /*
3253  * Field : refclkdiv
3254  *
3255  * Reference Clock Divider Control Registers;
3256  *
3257  * Fref_eff = (Fref)/(refdiv[5:0])
3258  *
3259  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
3260  *
3261  * Fsyn = Frq_mul * Fref_eff
3262  *
3263  * (Fsyn /6) >= 3* Fref_eff
3264  *
3265  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
3266  *
3267  * Field Access Macros:
3268  *
3269  */
3270 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field. */
3271 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_LSB 8
3272 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field. */
3273 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_MSB 13
3274 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field. */
3275 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_WIDTH 6
3276 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field value. */
3277 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET_MSK 0x00003f00
3278 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field value. */
3279 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_CLR_MSK 0xffffc0ff
3280 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field. */
3281 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_RESET 0x1
3282 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV field value from a register. */
3283 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_GET(value) (((value) & 0x00003f00) >> 8)
3284 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV register field value suitable for setting the register. */
3285 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(value) (((value) << 8) & 0x00003f00)
3286 
3287 /*
3288  * Field : Clock Source - psrc
3289  *
3290  * Controls the VCO input clock source.
3291  *
3292  * Field Enumeration Values:
3293  *
3294  * Enum | Value | Description
3295  * :----------------------------------------|:------|:--------------
3296  * ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_EOSC1 | 0x0 | eosc1_clk
3297  * ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_INTOSC | 0x1 | cb_intosc_clk
3298  * ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_F2S | 0x2 | f2s_free_clk
3299  *
3300  * Field Access Macros:
3301  *
3302  */
3303 /*
3304  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_PSRC
3305  *
3306  * eosc1_clk
3307  */
3308 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_EOSC1 0x0
3309 /*
3310  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_PSRC
3311  *
3312  * cb_intosc_clk
3313  */
3314 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_INTOSC 0x1
3315 /*
3316  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLGLOB_PSRC
3317  *
3318  * f2s_free_clk
3319  */
3320 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_E_F2S 0x2
3321 
3322 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field. */
3323 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_LSB 16
3324 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field. */
3325 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_MSB 17
3326 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field. */
3327 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_WIDTH 2
3328 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field value. */
3329 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_SET_MSK 0x00030000
3330 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field value. */
3331 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_CLR_MSK 0xfffcffff
3332 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field. */
3333 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_RESET 0x0
3334 /* Extracts the ALT_CLKMGR_PERPLL_PLLGLOB_PSRC field value from a register. */
3335 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_GET(value) (((value) & 0x00030000) >> 16)
3336 /* Produces a ALT_CLKMGR_PERPLL_PLLGLOB_PSRC register field value suitable for setting the register. */
3337 #define ALT_CLKMGR_PERPLL_PLLGLOB_PSRC_SET(value) (((value) << 16) & 0x00030000)
3338 
3339 #ifndef __ASSEMBLY__
3340 /*
3341  * WARNING: The C register and register group struct declarations are provided for
3342  * convenience and illustrative purposes. They should, however, be used with
3343  * caution as the C language standard provides no guarantees about the alignment or
3344  * atomicity of device memory accesses. The recommended practice for coding device
3345  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3346  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3347  * alt_write_dword() functions for 64 bit registers.
3348  *
3349  * The struct declaration for register ALT_CLKMGR_PERPLL_PLLGLOB.
3350  */
3351 struct ALT_CLKMGR_PERPLL_PLLGLOB_s
3352 {
3353  volatile uint32_t pd : 1; /* main PLL power down */
3354  volatile uint32_t rst : 1; /* main PLL reset */
3355  volatile uint32_t mute : 1; /* main PLL mute */
3356  volatile uint32_t modsel : 1; /* Int mode sel */
3357  volatile uint32_t bysctl : 1; /* Bypass clock source select control */
3358  uint32_t : 3; /* *UNDEFINED* */
3359  volatile uint32_t refclkdiv : 6; /* ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV */
3360  uint32_t : 2; /* *UNDEFINED* */
3361  volatile uint32_t psrc : 2; /* Clock Source */
3362  uint32_t : 14; /* *UNDEFINED* */
3363 };
3364 
3365 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PLLGLOB. */
3366 typedef struct ALT_CLKMGR_PERPLL_PLLGLOB_s ALT_CLKMGR_PERPLL_PLLGLOB_t;
3367 #endif /* __ASSEMBLY__ */
3368 
3369 /* The reset value of the ALT_CLKMGR_PERPLL_PLLGLOB register. */
3370 #define ALT_CLKMGR_PERPLL_PLLGLOB_RESET 0x00000100
3371 /* The byte offset of the ALT_CLKMGR_PERPLL_PLLGLOB register from the beginning of the component. */
3372 #define ALT_CLKMGR_PERPLL_PLLGLOB_OFST 0x40
3373 
3374 /*
3375  * Register : fdbck
3376  *
3377  * VCO freq register counters
3378  *
3379  * Register Layout
3380  *
3381  * Bits | Access | Reset | Description
3382  * :--------|:-------|:------|:-----------------------------
3383  * [23:0] | RW | 0x0 | ALT_CLKMGR_PERPLL_FDBCK_FDIV
3384  * [31:24] | RW | 0x22 | ALT_CLKMGR_PERPLL_FDBCK_MDIV
3385  *
3386  */
3387 /*
3388  * Field : fdiv
3389  *
3390  * Fractional Synthesizer Center Frequency Control Word. The PLL Initially Operates
3391  * At The Frequency Based On The Mdiv Value Set At Reset. After Pll Exits Reset,
3392  * Any Change In Mdiv Value At The Interface Is Stored Internally.
3393  *
3394  * Fref_eff = (Fref)/(refdiv[5:0])
3395  *
3396  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
3397  *
3398  * Fsyn = Frq_mul * Fref_eff
3399  *
3400  * (Fsyn /6) >= 3* Fref_eff
3401  *
3402  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
3403  *
3404  * Field Access Macros:
3405  *
3406  */
3407 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field. */
3408 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_LSB 0
3409 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field. */
3410 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_MSB 23
3411 /* The width in bits of the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field. */
3412 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_WIDTH 24
3413 /* The mask used to set the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field value. */
3414 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_SET_MSK 0x00ffffff
3415 /* The mask used to clear the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field value. */
3416 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_CLR_MSK 0xff000000
3417 /* The reset value of the ALT_CLKMGR_PERPLL_FDBCK_FDIV register field. */
3418 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_RESET 0x0
3419 /* Extracts the ALT_CLKMGR_PERPLL_FDBCK_FDIV field value from a register. */
3420 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_GET(value) (((value) & 0x00ffffff) >> 0)
3421 /* Produces a ALT_CLKMGR_PERPLL_FDBCK_FDIV register field value suitable for setting the register. */
3422 #define ALT_CLKMGR_PERPLL_FDBCK_FDIV_SET(value) (((value) << 0) & 0x00ffffff)
3423 
3424 /*
3425  * Field : mdiv
3426  *
3427  * Feedback Clock Divider. The Pll Initially Operates At The Frequency Based On The
3428  * Mdiv And Fdiv Values Set At Reset. After Pll Exits Reset, Any Change In Mdiv Or
3429  * Fdiv Values At The Interface Are Stored Internally. ictl_vpll_mdiv_a_[7:0] =
3430  * (Fvco /( Fref / ictl_vpll_refdiv_nt_[5:0])) - 6.
3431  *
3432  * Fref_eff = (Fref)/(refdiv[5:0])
3433  *
3434  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0] / (2^24)))}
3435  *
3436  * Fsyn = Frq_mul * Fref_eff
3437  *
3438  * (Fsyn /6) >= 3* Fref_eff
3439  *
3440  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
3441  *
3442  * Field Access Macros:
3443  *
3444  */
3445 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field. */
3446 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_LSB 24
3447 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field. */
3448 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_MSB 31
3449 /* The width in bits of the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field. */
3450 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_WIDTH 8
3451 /* The mask used to set the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field value. */
3452 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_SET_MSK 0xff000000
3453 /* The mask used to clear the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field value. */
3454 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_CLR_MSK 0x00ffffff
3455 /* The reset value of the ALT_CLKMGR_PERPLL_FDBCK_MDIV register field. */
3456 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_RESET 0x22
3457 /* Extracts the ALT_CLKMGR_PERPLL_FDBCK_MDIV field value from a register. */
3458 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_GET(value) (((value) & 0xff000000) >> 24)
3459 /* Produces a ALT_CLKMGR_PERPLL_FDBCK_MDIV register field value suitable for setting the register. */
3460 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV_SET(value) (((value) << 24) & 0xff000000)
3461 
3462 #ifndef __ASSEMBLY__
3463 /*
3464  * WARNING: The C register and register group struct declarations are provided for
3465  * convenience and illustrative purposes. They should, however, be used with
3466  * caution as the C language standard provides no guarantees about the alignment or
3467  * atomicity of device memory accesses. The recommended practice for coding device
3468  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3469  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3470  * alt_write_dword() functions for 64 bit registers.
3471  *
3472  * The struct declaration for register ALT_CLKMGR_PERPLL_FDBCK.
3473  */
3474 struct ALT_CLKMGR_PERPLL_FDBCK_s
3475 {
3476  volatile uint32_t fdiv : 24; /* ALT_CLKMGR_PERPLL_FDBCK_FDIV */
3477  volatile uint32_t mdiv : 8; /* ALT_CLKMGR_PERPLL_FDBCK_MDIV */
3478 };
3479 
3480 /* The typedef declaration for register ALT_CLKMGR_PERPLL_FDBCK. */
3481 typedef struct ALT_CLKMGR_PERPLL_FDBCK_s ALT_CLKMGR_PERPLL_FDBCK_t;
3482 #endif /* __ASSEMBLY__ */
3483 
3484 /* The reset value of the ALT_CLKMGR_PERPLL_FDBCK register. */
3485 #define ALT_CLKMGR_PERPLL_FDBCK_RESET 0x22000000
3486 /* The byte offset of the ALT_CLKMGR_PERPLL_FDBCK register from the beginning of the component. */
3487 #define ALT_CLKMGR_PERPLL_FDBCK_OFST 0x44
3488 
3489 /*
3490  * Register : mem
3491  *
3492  * Registers dealing with PLL internal memory access.
3493  *
3494  * Register Layout
3495  *
3496  * Bits | Access | Reset | Description
3497  * :--------|:-------|:------|:---------------------------
3498  * [9:0] | RW | 0x0 | ALT_CLKMGR_PERPLL_MEM_ADDR
3499  * [15:10] | ??? | 0x0 | *UNDEFINED*
3500  * [23:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_MEM_WDAT
3501  * [24] | RW | 0x0 | ALT_CLKMGR_PERPLL_MEM_REQ
3502  * [25] | RW | 0x0 | ALT_CLKMGR_PERPLL_MEM_WR
3503  * [31:26] | ??? | 0x0 | *UNDEFINED*
3504  *
3505  */
3506 /*
3507  * Field : addr
3508  *
3509  * PLL Memory Addressing
3510  *
3511  * Field Access Macros:
3512  *
3513  */
3514 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MEM_ADDR register field. */
3515 #define ALT_CLKMGR_PERPLL_MEM_ADDR_LSB 0
3516 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MEM_ADDR register field. */
3517 #define ALT_CLKMGR_PERPLL_MEM_ADDR_MSB 9
3518 /* The width in bits of the ALT_CLKMGR_PERPLL_MEM_ADDR register field. */
3519 #define ALT_CLKMGR_PERPLL_MEM_ADDR_WIDTH 10
3520 /* The mask used to set the ALT_CLKMGR_PERPLL_MEM_ADDR register field value. */
3521 #define ALT_CLKMGR_PERPLL_MEM_ADDR_SET_MSK 0x000003ff
3522 /* The mask used to clear the ALT_CLKMGR_PERPLL_MEM_ADDR register field value. */
3523 #define ALT_CLKMGR_PERPLL_MEM_ADDR_CLR_MSK 0xfffffc00
3524 /* The reset value of the ALT_CLKMGR_PERPLL_MEM_ADDR register field. */
3525 #define ALT_CLKMGR_PERPLL_MEM_ADDR_RESET 0x0
3526 /* Extracts the ALT_CLKMGR_PERPLL_MEM_ADDR field value from a register. */
3527 #define ALT_CLKMGR_PERPLL_MEM_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3528 /* Produces a ALT_CLKMGR_PERPLL_MEM_ADDR register field value suitable for setting the register. */
3529 #define ALT_CLKMGR_PERPLL_MEM_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3530 
3531 /*
3532  * Field : wdat
3533  *
3534  * Memory Write Data
3535  *
3536  * Field Access Macros:
3537  *
3538  */
3539 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MEM_WDAT register field. */
3540 #define ALT_CLKMGR_PERPLL_MEM_WDAT_LSB 16
3541 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MEM_WDAT register field. */
3542 #define ALT_CLKMGR_PERPLL_MEM_WDAT_MSB 23
3543 /* The width in bits of the ALT_CLKMGR_PERPLL_MEM_WDAT register field. */
3544 #define ALT_CLKMGR_PERPLL_MEM_WDAT_WIDTH 8
3545 /* The mask used to set the ALT_CLKMGR_PERPLL_MEM_WDAT register field value. */
3546 #define ALT_CLKMGR_PERPLL_MEM_WDAT_SET_MSK 0x00ff0000
3547 /* The mask used to clear the ALT_CLKMGR_PERPLL_MEM_WDAT register field value. */
3548 #define ALT_CLKMGR_PERPLL_MEM_WDAT_CLR_MSK 0xff00ffff
3549 /* The reset value of the ALT_CLKMGR_PERPLL_MEM_WDAT register field. */
3550 #define ALT_CLKMGR_PERPLL_MEM_WDAT_RESET 0x0
3551 /* Extracts the ALT_CLKMGR_PERPLL_MEM_WDAT field value from a register. */
3552 #define ALT_CLKMGR_PERPLL_MEM_WDAT_GET(value) (((value) & 0x00ff0000) >> 16)
3553 /* Produces a ALT_CLKMGR_PERPLL_MEM_WDAT register field value suitable for setting the register. */
3554 #define ALT_CLKMGR_PERPLL_MEM_WDAT_SET(value) (((value) << 16) & 0x00ff0000)
3555 
3556 /*
3557  * Field : req
3558  *
3559  * Memory Request Signal
3560  *
3561  * Field Access Macros:
3562  *
3563  */
3564 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MEM_REQ register field. */
3565 #define ALT_CLKMGR_PERPLL_MEM_REQ_LSB 24
3566 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MEM_REQ register field. */
3567 #define ALT_CLKMGR_PERPLL_MEM_REQ_MSB 24
3568 /* The width in bits of the ALT_CLKMGR_PERPLL_MEM_REQ register field. */
3569 #define ALT_CLKMGR_PERPLL_MEM_REQ_WIDTH 1
3570 /* The mask used to set the ALT_CLKMGR_PERPLL_MEM_REQ register field value. */
3571 #define ALT_CLKMGR_PERPLL_MEM_REQ_SET_MSK 0x01000000
3572 /* The mask used to clear the ALT_CLKMGR_PERPLL_MEM_REQ register field value. */
3573 #define ALT_CLKMGR_PERPLL_MEM_REQ_CLR_MSK 0xfeffffff
3574 /* The reset value of the ALT_CLKMGR_PERPLL_MEM_REQ register field. */
3575 #define ALT_CLKMGR_PERPLL_MEM_REQ_RESET 0x0
3576 /* Extracts the ALT_CLKMGR_PERPLL_MEM_REQ field value from a register. */
3577 #define ALT_CLKMGR_PERPLL_MEM_REQ_GET(value) (((value) & 0x01000000) >> 24)
3578 /* Produces a ALT_CLKMGR_PERPLL_MEM_REQ register field value suitable for setting the register. */
3579 #define ALT_CLKMGR_PERPLL_MEM_REQ_SET(value) (((value) << 24) & 0x01000000)
3580 
3581 /*
3582  * Field : wr
3583  *
3584  * Memory Read/Write Signal. 0 - Indicates A Read Transaction. 1 - Indicates A
3585  * Write Transaction
3586  *
3587  * Field Enumeration Values:
3588  *
3589  * Enum | Value | Description
3590  * :---------------------------------|:------|:------------
3591  * ALT_CLKMGR_PERPLL_MEM_WR_E_READ | 0x0 |
3592  * ALT_CLKMGR_PERPLL_MEM_WR_E_WRITE | 0x1 |
3593  *
3594  * Field Access Macros:
3595  *
3596  */
3597 /*
3598  * Enumerated value for register field ALT_CLKMGR_PERPLL_MEM_WR
3599  *
3600  */
3601 #define ALT_CLKMGR_PERPLL_MEM_WR_E_READ 0x0
3602 /*
3603  * Enumerated value for register field ALT_CLKMGR_PERPLL_MEM_WR
3604  *
3605  */
3606 #define ALT_CLKMGR_PERPLL_MEM_WR_E_WRITE 0x1
3607 
3608 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MEM_WR register field. */
3609 #define ALT_CLKMGR_PERPLL_MEM_WR_LSB 25
3610 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MEM_WR register field. */
3611 #define ALT_CLKMGR_PERPLL_MEM_WR_MSB 25
3612 /* The width in bits of the ALT_CLKMGR_PERPLL_MEM_WR register field. */
3613 #define ALT_CLKMGR_PERPLL_MEM_WR_WIDTH 1
3614 /* The mask used to set the ALT_CLKMGR_PERPLL_MEM_WR register field value. */
3615 #define ALT_CLKMGR_PERPLL_MEM_WR_SET_MSK 0x02000000
3616 /* The mask used to clear the ALT_CLKMGR_PERPLL_MEM_WR register field value. */
3617 #define ALT_CLKMGR_PERPLL_MEM_WR_CLR_MSK 0xfdffffff
3618 /* The reset value of the ALT_CLKMGR_PERPLL_MEM_WR register field. */
3619 #define ALT_CLKMGR_PERPLL_MEM_WR_RESET 0x0
3620 /* Extracts the ALT_CLKMGR_PERPLL_MEM_WR field value from a register. */
3621 #define ALT_CLKMGR_PERPLL_MEM_WR_GET(value) (((value) & 0x02000000) >> 25)
3622 /* Produces a ALT_CLKMGR_PERPLL_MEM_WR register field value suitable for setting the register. */
3623 #define ALT_CLKMGR_PERPLL_MEM_WR_SET(value) (((value) << 25) & 0x02000000)
3624 
3625 #ifndef __ASSEMBLY__
3626 /*
3627  * WARNING: The C register and register group struct declarations are provided for
3628  * convenience and illustrative purposes. They should, however, be used with
3629  * caution as the C language standard provides no guarantees about the alignment or
3630  * atomicity of device memory accesses. The recommended practice for coding device
3631  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3632  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3633  * alt_write_dword() functions for 64 bit registers.
3634  *
3635  * The struct declaration for register ALT_CLKMGR_PERPLL_MEM.
3636  */
3637 struct ALT_CLKMGR_PERPLL_MEM_s
3638 {
3639  volatile uint32_t addr : 10; /* ALT_CLKMGR_PERPLL_MEM_ADDR */
3640  uint32_t : 6; /* *UNDEFINED* */
3641  volatile uint32_t wdat : 8; /* ALT_CLKMGR_PERPLL_MEM_WDAT */
3642  volatile uint32_t req : 1; /* ALT_CLKMGR_PERPLL_MEM_REQ */
3643  volatile uint32_t wr : 1; /* ALT_CLKMGR_PERPLL_MEM_WR */
3644  uint32_t : 6; /* *UNDEFINED* */
3645 };
3646 
3647 /* The typedef declaration for register ALT_CLKMGR_PERPLL_MEM. */
3648 typedef struct ALT_CLKMGR_PERPLL_MEM_s ALT_CLKMGR_PERPLL_MEM_t;
3649 #endif /* __ASSEMBLY__ */
3650 
3651 /* The reset value of the ALT_CLKMGR_PERPLL_MEM register. */
3652 #define ALT_CLKMGR_PERPLL_MEM_RESET 0x00000000
3653 /* The byte offset of the ALT_CLKMGR_PERPLL_MEM register from the beginning of the component. */
3654 #define ALT_CLKMGR_PERPLL_MEM_OFST 0x48
3655 
3656 /*
3657  * Register : memstat
3658  *
3659  * Periph PLL memstatus register. contains ack and memory read data
3660  *
3661  * Register Layout
3662  *
3663  * Bits | Access | Reset | Description
3664  * :-------|:-------|:------|:--------------------------------
3665  * [7:0] | R | 0x0 | ALT_CLKMGR_PERPLL_MEMSTAT_RDATA
3666  * [31:8] | ??? | 0x0 | *UNDEFINED*
3667  *
3668  */
3669 /*
3670  * Field : rdata
3671  *
3672  * Memory Read Data
3673  *
3674  * Field Access Macros:
3675  *
3676  */
3677 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field. */
3678 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_LSB 0
3679 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field. */
3680 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_MSB 7
3681 /* The width in bits of the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field. */
3682 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_WIDTH 8
3683 /* The mask used to set the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field value. */
3684 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_SET_MSK 0x000000ff
3685 /* The mask used to clear the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field value. */
3686 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_CLR_MSK 0xffffff00
3687 /* The reset value of the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field. */
3688 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_RESET 0x0
3689 /* Extracts the ALT_CLKMGR_PERPLL_MEMSTAT_RDATA field value from a register. */
3690 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_GET(value) (((value) & 0x000000ff) >> 0)
3691 /* Produces a ALT_CLKMGR_PERPLL_MEMSTAT_RDATA register field value suitable for setting the register. */
3692 #define ALT_CLKMGR_PERPLL_MEMSTAT_RDATA_SET(value) (((value) << 0) & 0x000000ff)
3693 
3694 #ifndef __ASSEMBLY__
3695 /*
3696  * WARNING: The C register and register group struct declarations are provided for
3697  * convenience and illustrative purposes. They should, however, be used with
3698  * caution as the C language standard provides no guarantees about the alignment or
3699  * atomicity of device memory accesses. The recommended practice for coding device
3700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3702  * alt_write_dword() functions for 64 bit registers.
3703  *
3704  * The struct declaration for register ALT_CLKMGR_PERPLL_MEMSTAT.
3705  */
3706 struct ALT_CLKMGR_PERPLL_MEMSTAT_s
3707 {
3708  const volatile uint32_t rdata : 8; /* ALT_CLKMGR_PERPLL_MEMSTAT_RDATA */
3709  uint32_t : 24; /* *UNDEFINED* */
3710 };
3711 
3712 /* The typedef declaration for register ALT_CLKMGR_PERPLL_MEMSTAT. */
3713 typedef struct ALT_CLKMGR_PERPLL_MEMSTAT_s ALT_CLKMGR_PERPLL_MEMSTAT_t;
3714 #endif /* __ASSEMBLY__ */
3715 
3716 /* The reset value of the ALT_CLKMGR_PERPLL_MEMSTAT register. */
3717 #define ALT_CLKMGR_PERPLL_MEMSTAT_RESET 0x00000000
3718 /* The byte offset of the ALT_CLKMGR_PERPLL_MEMSTAT register from the beginning of the component. */
3719 #define ALT_CLKMGR_PERPLL_MEMSTAT_OFST 0x4c
3720 
3721 /*
3722  * Register : pllc0
3723  *
3724  * Channel C0 frequency settings for the periph PLL
3725  *
3726  * Register Layout
3727  *
3728  * Bits | Access | Reset | Description
3729  * :--------|:-------|:------|:------------------------------
3730  * [7:0] | RW | 0x2 | ALT_CLKMGR_PERPLL_PLLC0_DIV
3731  * [23:8] | ??? | 0x0 | *UNDEFINED*
3732  * [24] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC0_PHINC
3733  * [25] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC0_PHRST
3734  * [26] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC0_BYPAS
3735  * [27] | RW | 0x1 | ALT_CLKMGR_PERPLL_PLLC0_EN
3736  * [31:28] | ??? | 0x0 | *UNDEFINED*
3737  *
3738  */
3739 /*
3740  * Field : div
3741  *
3742  * PLL channel 0 divider ratio in binary code; Can be dynamically updated after
3743  * lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter
3744  * glitches for 8'd1 and 8d'2 cases.
3745  *
3746  * Field Access Macros:
3747  *
3748  */
3749 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC0_DIV register field. */
3750 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_LSB 0
3751 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC0_DIV register field. */
3752 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_MSB 7
3753 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC0_DIV register field. */
3754 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_WIDTH 8
3755 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC0_DIV register field value. */
3756 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_SET_MSK 0x000000ff
3757 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC0_DIV register field value. */
3758 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_CLR_MSK 0xffffff00
3759 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0_DIV register field. */
3760 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_RESET 0x2
3761 /* Extracts the ALT_CLKMGR_PERPLL_PLLC0_DIV field value from a register. */
3762 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_GET(value) (((value) & 0x000000ff) >> 0)
3763 /* Produces a ALT_CLKMGR_PERPLL_PLLC0_DIV register field value suitable for setting the register. */
3764 #define ALT_CLKMGR_PERPLL_PLLC0_DIV_SET(value) (((value) << 0) & 0x000000ff)
3765 
3766 /*
3767  * Field : phinc
3768  *
3769  * When a positive edge is induced, one of the positive edges of PLLC0 clock is
3770  * pushed out by 1/8th of VCO period.
3771  *
3772  * Field Enumeration Values:
3773  *
3774  * Enum | Value | Description
3775  * :---------------------------------------|:------|:------------
3776  * ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_UNPUSH | 0x0 |
3777  * ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_PUSH | 0x1 |
3778  *
3779  * Field Access Macros:
3780  *
3781  */
3782 /*
3783  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_PHINC
3784  *
3785  */
3786 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_UNPUSH 0x0
3787 /*
3788  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_PHINC
3789  *
3790  */
3791 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_E_PUSH 0x1
3792 
3793 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field. */
3794 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_LSB 24
3795 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field. */
3796 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_MSB 24
3797 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field. */
3798 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_WIDTH 1
3799 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field value. */
3800 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_SET_MSK 0x01000000
3801 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field value. */
3802 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_CLR_MSK 0xfeffffff
3803 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0_PHINC register field. */
3804 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_RESET 0x0
3805 /* Extracts the ALT_CLKMGR_PERPLL_PLLC0_PHINC field value from a register. */
3806 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_GET(value) (((value) & 0x01000000) >> 24)
3807 /* Produces a ALT_CLKMGR_PERPLL_PLLC0_PHINC register field value suitable for setting the register. */
3808 #define ALT_CLKMGR_PERPLL_PLLC0_PHINC_SET(value) (((value) << 24) & 0x01000000)
3809 
3810 /*
3811  * Field : phrst
3812  *
3813  * If ictl_vpll_pr1_phrst_a=1'b1, the phase of PLLC0 clock is reset to default
3814  * phase as the PLL is just started.
3815  *
3816  * Field Enumeration Values:
3817  *
3818  * Enum | Value | Description
3819  * :--------------------------------------------|:------|:------------
3820  * ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTDEASSERT | 0x0 |
3821  * ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTASSERT | 0x1 |
3822  *
3823  * Field Access Macros:
3824  *
3825  */
3826 /*
3827  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_PHRST
3828  *
3829  */
3830 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTDEASSERT 0x0
3831 /*
3832  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_PHRST
3833  *
3834  */
3835 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_E_RSTASSERT 0x1
3836 
3837 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field. */
3838 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_LSB 25
3839 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field. */
3840 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_MSB 25
3841 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field. */
3842 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_WIDTH 1
3843 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field value. */
3844 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_SET_MSK 0x02000000
3845 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field value. */
3846 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_CLR_MSK 0xfdffffff
3847 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0_PHRST register field. */
3848 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_RESET 0x0
3849 /* Extracts the ALT_CLKMGR_PERPLL_PLLC0_PHRST field value from a register. */
3850 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_GET(value) (((value) & 0x02000000) >> 25)
3851 /* Produces a ALT_CLKMGR_PERPLL_PLLC0_PHRST register field value suitable for setting the register. */
3852 #define ALT_CLKMGR_PERPLL_PLLC0_PHRST_SET(value) (((value) << 25) & 0x02000000)
3853 
3854 /*
3855  * Field : bypas
3856  *
3857  * PLL channel 0 output bypass; before lock, it is muted, regardless of its value.
3858  * After lock, if enabled and bypass=1, this outputs refclk.
3859  *
3860  * Field Enumeration Values:
3861  *
3862  * Enum | Value | Description
3863  * :-----------------------------------------|:------|:------------
3864  * ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_UNBYPASS | 0x0 |
3865  * ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_BYPASS | 0x1 |
3866  *
3867  * Field Access Macros:
3868  *
3869  */
3870 /*
3871  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_BYPAS
3872  *
3873  */
3874 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_UNBYPASS 0x0
3875 /*
3876  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_BYPAS
3877  *
3878  */
3879 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_E_BYPASS 0x1
3880 
3881 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field. */
3882 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_LSB 26
3883 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field. */
3884 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_MSB 26
3885 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field. */
3886 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_WIDTH 1
3887 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field value. */
3888 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_SET_MSK 0x04000000
3889 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field value. */
3890 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_CLR_MSK 0xfbffffff
3891 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field. */
3892 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_RESET 0x0
3893 /* Extracts the ALT_CLKMGR_PERPLL_PLLC0_BYPAS field value from a register. */
3894 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_GET(value) (((value) & 0x04000000) >> 26)
3895 /* Produces a ALT_CLKMGR_PERPLL_PLLC0_BYPAS register field value suitable for setting the register. */
3896 #define ALT_CLKMGR_PERPLL_PLLC0_BYPAS_SET(value) (((value) << 26) & 0x04000000)
3897 
3898 /*
3899  * Field : en
3900  *
3901  * PLL channel 0 output enable; the output is muted before lock signal is asserted,
3902  * regardless of the value; after lock is asserted, it is glitch-free enable
3903  * ock_vpll_pr1, if enabled
3904  *
3905  * Field Enumeration Values:
3906  *
3907  * Enum | Value | Description
3908  * :-------------------------------------|:------|:------------
3909  * ALT_CLKMGR_PERPLL_PLLC0_EN_E_DISABLE | 0x0 |
3910  * ALT_CLKMGR_PERPLL_PLLC0_EN_E_ENABLE | 0x1 |
3911  *
3912  * Field Access Macros:
3913  *
3914  */
3915 /*
3916  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_EN
3917  *
3918  */
3919 #define ALT_CLKMGR_PERPLL_PLLC0_EN_E_DISABLE 0x0
3920 /*
3921  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC0_EN
3922  *
3923  */
3924 #define ALT_CLKMGR_PERPLL_PLLC0_EN_E_ENABLE 0x1
3925 
3926 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC0_EN register field. */
3927 #define ALT_CLKMGR_PERPLL_PLLC0_EN_LSB 27
3928 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC0_EN register field. */
3929 #define ALT_CLKMGR_PERPLL_PLLC0_EN_MSB 27
3930 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC0_EN register field. */
3931 #define ALT_CLKMGR_PERPLL_PLLC0_EN_WIDTH 1
3932 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC0_EN register field value. */
3933 #define ALT_CLKMGR_PERPLL_PLLC0_EN_SET_MSK 0x08000000
3934 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC0_EN register field value. */
3935 #define ALT_CLKMGR_PERPLL_PLLC0_EN_CLR_MSK 0xf7ffffff
3936 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0_EN register field. */
3937 #define ALT_CLKMGR_PERPLL_PLLC0_EN_RESET 0x1
3938 /* Extracts the ALT_CLKMGR_PERPLL_PLLC0_EN field value from a register. */
3939 #define ALT_CLKMGR_PERPLL_PLLC0_EN_GET(value) (((value) & 0x08000000) >> 27)
3940 /* Produces a ALT_CLKMGR_PERPLL_PLLC0_EN register field value suitable for setting the register. */
3941 #define ALT_CLKMGR_PERPLL_PLLC0_EN_SET(value) (((value) << 27) & 0x08000000)
3942 
3943 #ifndef __ASSEMBLY__
3944 /*
3945  * WARNING: The C register and register group struct declarations are provided for
3946  * convenience and illustrative purposes. They should, however, be used with
3947  * caution as the C language standard provides no guarantees about the alignment or
3948  * atomicity of device memory accesses. The recommended practice for coding device
3949  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3950  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3951  * alt_write_dword() functions for 64 bit registers.
3952  *
3953  * The struct declaration for register ALT_CLKMGR_PERPLL_PLLC0.
3954  */
3955 struct ALT_CLKMGR_PERPLL_PLLC0_s
3956 {
3957  volatile uint32_t div : 8; /* ALT_CLKMGR_PERPLL_PLLC0_DIV */
3958  uint32_t : 16; /* *UNDEFINED* */
3959  volatile uint32_t phinc : 1; /* ALT_CLKMGR_PERPLL_PLLC0_PHINC */
3960  volatile uint32_t phrst : 1; /* ALT_CLKMGR_PERPLL_PLLC0_PHRST */
3961  volatile uint32_t bypas : 1; /* ALT_CLKMGR_PERPLL_PLLC0_BYPAS */
3962  volatile uint32_t en : 1; /* ALT_CLKMGR_PERPLL_PLLC0_EN */
3963  uint32_t : 4; /* *UNDEFINED* */
3964 };
3965 
3966 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PLLC0. */
3967 typedef struct ALT_CLKMGR_PERPLL_PLLC0_s ALT_CLKMGR_PERPLL_PLLC0_t;
3968 #endif /* __ASSEMBLY__ */
3969 
3970 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC0 register. */
3971 #define ALT_CLKMGR_PERPLL_PLLC0_RESET 0x08000002
3972 /* The byte offset of the ALT_CLKMGR_PERPLL_PLLC0 register from the beginning of the component. */
3973 #define ALT_CLKMGR_PERPLL_PLLC0_OFST 0x50
3974 
3975 /*
3976  * Register : pllc1
3977  *
3978  * Channel C1 settings for the periph PLL
3979  *
3980  * Register Layout
3981  *
3982  * Bits | Access | Reset | Description
3983  * :--------|:-------|:------|:------------------------------
3984  * [7:0] | RW | 0x4 | ALT_CLKMGR_PERPLL_PLLC1_DIV
3985  * [23:8] | ??? | 0x0 | *UNDEFINED*
3986  * [24] | RW | 0x1 | ALT_CLKMGR_PERPLL_PLLC1_EN
3987  * [25] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC1_BYPAS
3988  * [26] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC1_PHINC
3989  * [27] | RW | 0x0 | ALT_CLKMGR_PERPLL_PLLC1_PHRST
3990  * [31:28] | ??? | 0x0 | *UNDEFINED*
3991  *
3992  */
3993 /*
3994  * Field : div
3995  *
3996  * PLL channel 1 divider ratio in binary code; Can be dynamically updated after
3997  * lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter
3998  * glitches for 8'd1 and 8d'2 cases.
3999  *
4000  * Field Access Macros:
4001  *
4002  */
4003 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC1_DIV register field. */
4004 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_LSB 0
4005 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC1_DIV register field. */
4006 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_MSB 7
4007 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC1_DIV register field. */
4008 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_WIDTH 8
4009 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC1_DIV register field value. */
4010 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_SET_MSK 0x000000ff
4011 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC1_DIV register field value. */
4012 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_CLR_MSK 0xffffff00
4013 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1_DIV register field. */
4014 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_RESET 0x4
4015 /* Extracts the ALT_CLKMGR_PERPLL_PLLC1_DIV field value from a register. */
4016 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_GET(value) (((value) & 0x000000ff) >> 0)
4017 /* Produces a ALT_CLKMGR_PERPLL_PLLC1_DIV register field value suitable for setting the register. */
4018 #define ALT_CLKMGR_PERPLL_PLLC1_DIV_SET(value) (((value) << 0) & 0x000000ff)
4019 
4020 /*
4021  * Field : en
4022  *
4023  * PLL channel 1 output enable; the output is muted before lock signal is asserted,
4024  * regardless of the value; after lock is asserted, it is glitch-free enable
4025  * ock_vpll_pr1, if enabled
4026  *
4027  * Field Enumeration Values:
4028  *
4029  * Enum | Value | Description
4030  * :-------------------------------------|:------|:------------
4031  * ALT_CLKMGR_PERPLL_PLLC1_EN_E_DISABLE | 0x0 |
4032  * ALT_CLKMGR_PERPLL_PLLC1_EN_E_ENABLE | 0x1 |
4033  *
4034  * Field Access Macros:
4035  *
4036  */
4037 /*
4038  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_EN
4039  *
4040  */
4041 #define ALT_CLKMGR_PERPLL_PLLC1_EN_E_DISABLE 0x0
4042 /*
4043  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_EN
4044  *
4045  */
4046 #define ALT_CLKMGR_PERPLL_PLLC1_EN_E_ENABLE 0x1
4047 
4048 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC1_EN register field. */
4049 #define ALT_CLKMGR_PERPLL_PLLC1_EN_LSB 24
4050 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC1_EN register field. */
4051 #define ALT_CLKMGR_PERPLL_PLLC1_EN_MSB 24
4052 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC1_EN register field. */
4053 #define ALT_CLKMGR_PERPLL_PLLC1_EN_WIDTH 1
4054 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC1_EN register field value. */
4055 #define ALT_CLKMGR_PERPLL_PLLC1_EN_SET_MSK 0x01000000
4056 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC1_EN register field value. */
4057 #define ALT_CLKMGR_PERPLL_PLLC1_EN_CLR_MSK 0xfeffffff
4058 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1_EN register field. */
4059 #define ALT_CLKMGR_PERPLL_PLLC1_EN_RESET 0x1
4060 /* Extracts the ALT_CLKMGR_PERPLL_PLLC1_EN field value from a register. */
4061 #define ALT_CLKMGR_PERPLL_PLLC1_EN_GET(value) (((value) & 0x01000000) >> 24)
4062 /* Produces a ALT_CLKMGR_PERPLL_PLLC1_EN register field value suitable for setting the register. */
4063 #define ALT_CLKMGR_PERPLL_PLLC1_EN_SET(value) (((value) << 24) & 0x01000000)
4064 
4065 /*
4066  * Field : bypas
4067  *
4068  * PLL channel 1 output bypass; before lock, it is muted, regardless of its value.
4069  * After lock, if enabled and bypass=1, this outputs refclk.
4070  *
4071  * Field Enumeration Values:
4072  *
4073  * Enum | Value | Description
4074  * :-----------------------------------------|:------|:------------
4075  * ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_UNBYPASS | 0x0 |
4076  * ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_BYPASS | 0x1 |
4077  *
4078  * Field Access Macros:
4079  *
4080  */
4081 /*
4082  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_BYPAS
4083  *
4084  */
4085 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_UNBYPASS 0x0
4086 /*
4087  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_BYPAS
4088  *
4089  */
4090 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_E_BYPASS 0x1
4091 
4092 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field. */
4093 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_LSB 25
4094 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field. */
4095 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_MSB 25
4096 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field. */
4097 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_WIDTH 1
4098 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field value. */
4099 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_SET_MSK 0x02000000
4100 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field value. */
4101 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_CLR_MSK 0xfdffffff
4102 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field. */
4103 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_RESET 0x0
4104 /* Extracts the ALT_CLKMGR_PERPLL_PLLC1_BYPAS field value from a register. */
4105 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_GET(value) (((value) & 0x02000000) >> 25)
4106 /* Produces a ALT_CLKMGR_PERPLL_PLLC1_BYPAS register field value suitable for setting the register. */
4107 #define ALT_CLKMGR_PERPLL_PLLC1_BYPAS_SET(value) (((value) << 25) & 0x02000000)
4108 
4109 /*
4110  * Field : phinc
4111  *
4112  * When a positive edge is induced, one of the positive edges of PLLC1 clock is
4113  * pushed out by 1/8th of VCO period.
4114  *
4115  * Field Enumeration Values:
4116  *
4117  * Enum | Value | Description
4118  * :---------------------------------------|:------|:------------
4119  * ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_UNPUSH | 0x0 |
4120  * ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_PUSH | 0x1 |
4121  *
4122  * Field Access Macros:
4123  *
4124  */
4125 /*
4126  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_PHINC
4127  *
4128  */
4129 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_UNPUSH 0x0
4130 /*
4131  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_PHINC
4132  *
4133  */
4134 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_E_PUSH 0x1
4135 
4136 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field. */
4137 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_LSB 26
4138 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field. */
4139 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_MSB 26
4140 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field. */
4141 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_WIDTH 1
4142 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field value. */
4143 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_SET_MSK 0x04000000
4144 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field value. */
4145 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_CLR_MSK 0xfbffffff
4146 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1_PHINC register field. */
4147 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_RESET 0x0
4148 /* Extracts the ALT_CLKMGR_PERPLL_PLLC1_PHINC field value from a register. */
4149 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_GET(value) (((value) & 0x04000000) >> 26)
4150 /* Produces a ALT_CLKMGR_PERPLL_PLLC1_PHINC register field value suitable for setting the register. */
4151 #define ALT_CLKMGR_PERPLL_PLLC1_PHINC_SET(value) (((value) << 26) & 0x04000000)
4152 
4153 /*
4154  * Field : phrst
4155  *
4156  * If ictl_vpll_pr1_phrst_a=1'b1, the phase of PLLC1 clock is reset to default
4157  * phase as the PLL is just started.
4158  *
4159  * Field Enumeration Values:
4160  *
4161  * Enum | Value | Description
4162  * :--------------------------------------------|:------|:------------
4163  * ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTDEASSERT | 0x0 |
4164  * ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTASSERT | 0x1 |
4165  *
4166  * Field Access Macros:
4167  *
4168  */
4169 /*
4170  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_PHRST
4171  *
4172  */
4173 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTDEASSERT 0x0
4174 /*
4175  * Enumerated value for register field ALT_CLKMGR_PERPLL_PLLC1_PHRST
4176  *
4177  */
4178 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_E_RSTASSERT 0x1
4179 
4180 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field. */
4181 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_LSB 27
4182 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field. */
4183 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_MSB 27
4184 /* The width in bits of the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field. */
4185 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_WIDTH 1
4186 /* The mask used to set the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field value. */
4187 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_SET_MSK 0x08000000
4188 /* The mask used to clear the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field value. */
4189 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_CLR_MSK 0xf7ffffff
4190 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1_PHRST register field. */
4191 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_RESET 0x0
4192 /* Extracts the ALT_CLKMGR_PERPLL_PLLC1_PHRST field value from a register. */
4193 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_GET(value) (((value) & 0x08000000) >> 27)
4194 /* Produces a ALT_CLKMGR_PERPLL_PLLC1_PHRST register field value suitable for setting the register. */
4195 #define ALT_CLKMGR_PERPLL_PLLC1_PHRST_SET(value) (((value) << 27) & 0x08000000)
4196 
4197 #ifndef __ASSEMBLY__
4198 /*
4199  * WARNING: The C register and register group struct declarations are provided for
4200  * convenience and illustrative purposes. They should, however, be used with
4201  * caution as the C language standard provides no guarantees about the alignment or
4202  * atomicity of device memory accesses. The recommended practice for coding device
4203  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4204  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4205  * alt_write_dword() functions for 64 bit registers.
4206  *
4207  * The struct declaration for register ALT_CLKMGR_PERPLL_PLLC1.
4208  */
4209 struct ALT_CLKMGR_PERPLL_PLLC1_s
4210 {
4211  volatile uint32_t div : 8; /* ALT_CLKMGR_PERPLL_PLLC1_DIV */
4212  uint32_t : 16; /* *UNDEFINED* */
4213  volatile uint32_t en : 1; /* ALT_CLKMGR_PERPLL_PLLC1_EN */
4214  volatile uint32_t bypas : 1; /* ALT_CLKMGR_PERPLL_PLLC1_BYPAS */
4215  volatile uint32_t phinc : 1; /* ALT_CLKMGR_PERPLL_PLLC1_PHINC */
4216  volatile uint32_t phrst : 1; /* ALT_CLKMGR_PERPLL_PLLC1_PHRST */
4217  uint32_t : 4; /* *UNDEFINED* */
4218 };
4219 
4220 /* The typedef declaration for register ALT_CLKMGR_PERPLL_PLLC1. */
4221 typedef struct ALT_CLKMGR_PERPLL_PLLC1_s ALT_CLKMGR_PERPLL_PLLC1_t;
4222 #endif /* __ASSEMBLY__ */
4223 
4224 /* The reset value of the ALT_CLKMGR_PERPLL_PLLC1 register. */
4225 #define ALT_CLKMGR_PERPLL_PLLC1_RESET 0x01000004
4226 /* The byte offset of the ALT_CLKMGR_PERPLL_PLLC1 register from the beginning of the component. */
4227 #define ALT_CLKMGR_PERPLL_PLLC1_OFST 0x54
4228 
4229 /*
4230  * Register : vcocalib
4231  *
4232  * VCO calibration control registers.
4233  *
4234  * Register Layout
4235  *
4236  * Bits | Access | Reset | Description
4237  * :--------|:-------|:------|:----------------------------------
4238  * [7:0] | RW | 0xbf | ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT
4239  * [8] | ??? | 0x0 | *UNDEFINED*
4240  * [16:9] | RW | 0x5 | ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT
4241  * [22:17] | ??? | 0x0 | *UNDEFINED*
4242  * [24:23] | RW | 0x0 | ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN
4243  * [31:25] | ??? | 0x0 | *UNDEFINED*
4244  *
4245  */
4246 /*
4247  * Field : hscnt
4248  *
4249  * VCO calibration parameter.
4250  *
4251  * hscnt= (mdiv+ 6) * mscnt/ refdiv-9.
4252  *
4253  * It can be only set while the pll is at reset or power down state.
4254  *
4255  * It cannot be switched dynamically.
4256  *
4257  * Field Access Macros:
4258  *
4259  */
4260 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field. */
4261 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_LSB 0
4262 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field. */
4263 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_MSB 7
4264 /* The width in bits of the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field. */
4265 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_WIDTH 8
4266 /* The mask used to set the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field value. */
4267 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET_MSK 0x000000ff
4268 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field value. */
4269 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_CLR_MSK 0xffffff00
4270 /* The reset value of the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field. */
4271 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_RESET 0xbf
4272 /* Extracts the ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT field value from a register. */
4273 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_GET(value) (((value) & 0x000000ff) >> 0)
4274 /* Produces a ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT register field value suitable for setting the register. */
4275 #define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(value) (((value) << 0) & 0x000000ff)
4276 
4277 /*
4278  * Field : mscnt
4279  *
4280  * mscnt = 200/(fvco/fref).
4281  *
4282  * It can be only set while the PLL is at reset or power down state.
4283  *
4284  * It cannot be switched dynamically.
4285  *
4286  * Field Access Macros:
4287  *
4288  */
4289 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field. */
4290 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_LSB 9
4291 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field. */
4292 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_MSB 16
4293 /* The width in bits of the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field. */
4294 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_WIDTH 8
4295 /* The mask used to set the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field value. */
4296 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET_MSK 0x0001fe00
4297 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field value. */
4298 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_CLR_MSK 0xfffe01ff
4299 /* The reset value of the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field. */
4300 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_RESET 0x5
4301 /* Extracts the ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT field value from a register. */
4302 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_GET(value) (((value) & 0x0001fe00) >> 9)
4303 /* Produces a ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT register field value suitable for setting the register. */
4304 #define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(value) (((value) << 9) & 0x0001fe00)
4305 
4306 /*
4307  * Field : termin
4308  *
4309  * Termination Calibration Control Look-Up Table Select
4310  *
4311  * Field Access Macros:
4312  *
4313  */
4314 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field. */
4315 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_LSB 23
4316 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field. */
4317 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_MSB 24
4318 /* The width in bits of the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field. */
4319 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_WIDTH 2
4320 /* The mask used to set the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field value. */
4321 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_SET_MSK 0x01800000
4322 /* The mask used to clear the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field value. */
4323 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_CLR_MSK 0xfe7fffff
4324 /* The reset value of the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field. */
4325 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_RESET 0x0
4326 /* Extracts the ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN field value from a register. */
4327 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_GET(value) (((value) & 0x01800000) >> 23)
4328 /* Produces a ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN register field value suitable for setting the register. */
4329 #define ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN_SET(value) (((value) << 23) & 0x01800000)
4330 
4331 #ifndef __ASSEMBLY__
4332 /*
4333  * WARNING: The C register and register group struct declarations are provided for
4334  * convenience and illustrative purposes. They should, however, be used with
4335  * caution as the C language standard provides no guarantees about the alignment or
4336  * atomicity of device memory accesses. The recommended practice for coding device
4337  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4338  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4339  * alt_write_dword() functions for 64 bit registers.
4340  *
4341  * The struct declaration for register ALT_CLKMGR_PERPLL_VCOCALIB.
4342  */
4343 struct ALT_CLKMGR_PERPLL_VCOCALIB_s
4344 {
4345  volatile uint32_t hscnt : 8; /* ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT */
4346  uint32_t : 1; /* *UNDEFINED* */
4347  volatile uint32_t mscnt : 8; /* ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT */
4348  uint32_t : 6; /* *UNDEFINED* */
4349  volatile uint32_t termin : 2; /* ALT_CLKMGR_PERPLL_VCOCALIB_TERMIN */
4350  uint32_t : 7; /* *UNDEFINED* */
4351 };
4352 
4353 /* The typedef declaration for register ALT_CLKMGR_PERPLL_VCOCALIB. */
4354 typedef struct ALT_CLKMGR_PERPLL_VCOCALIB_s ALT_CLKMGR_PERPLL_VCOCALIB_t;
4355 #endif /* __ASSEMBLY__ */
4356 
4357 /* The reset value of the ALT_CLKMGR_PERPLL_VCOCALIB register. */
4358 #define ALT_CLKMGR_PERPLL_VCOCALIB_RESET 0x00000abf
4359 /* The byte offset of the ALT_CLKMGR_PERPLL_VCOCALIB register from the beginning of the component. */
4360 #define ALT_CLKMGR_PERPLL_VCOCALIB_OFST 0x58
4361 
4362 #ifndef __ASSEMBLY__
4363 /*
4364  * WARNING: The C register and register group struct declarations are provided for
4365  * convenience and illustrative purposes. They should, however, be used with
4366  * caution as the C language standard provides no guarantees about the alignment or
4367  * atomicity of device memory accesses. The recommended practice for coding device
4368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4370  * alt_write_dword() functions for 64 bit registers.
4371  *
4372  * The struct declaration for register group ALT_CLKMGR_PERPLL.
4373  */
4374 struct ALT_CLKMGR_PERPLL_s
4375 {
4376  volatile ALT_CLKMGR_PERPLL_EN_t en; /* ALT_CLKMGR_PERPLL_EN */
4377  volatile ALT_CLKMGR_PERPLL_ENS_t ens; /* ALT_CLKMGR_PERPLL_ENS */
4378  volatile ALT_CLKMGR_PERPLL_ENR_t enr; /* ALT_CLKMGR_PERPLL_ENR */
4379  volatile ALT_CLKMGR_PERPLL_BYPASS_t bypass; /* ALT_CLKMGR_PERPLL_BYPASS */
4380  volatile ALT_CLKMGR_PERPLL_BYPASSS_t bypasss; /* ALT_CLKMGR_PERPLL_BYPASSS */
4381  volatile ALT_CLKMGR_PERPLL_BYPASSR_t bypassr; /* ALT_CLKMGR_PERPLL_BYPASSR */
4382  volatile ALT_CLKMGR_PERPLL_CNTR2CLK_t cntr2clk; /* ALT_CLKMGR_PERPLL_CNTR2CLK */
4383  volatile ALT_CLKMGR_PERPLL_CNTR3CLK_t cntr3clk; /* ALT_CLKMGR_PERPLL_CNTR3CLK */
4384  volatile ALT_CLKMGR_PERPLL_CNTR4CLK_t cntr4clk; /* ALT_CLKMGR_PERPLL_CNTR4CLK */
4385  volatile ALT_CLKMGR_PERPLL_CNTR5CLK_t cntr5clk; /* ALT_CLKMGR_PERPLL_CNTR5CLK */
4386  volatile ALT_CLKMGR_PERPLL_CNTR6CLK_t cntr6clk; /* ALT_CLKMGR_PERPLL_CNTR6CLK */
4387  volatile ALT_CLKMGR_PERPLL_CNTR7CLK_t cntr7clk; /* ALT_CLKMGR_PERPLL_CNTR7CLK */
4388  volatile ALT_CLKMGR_PERPLL_CNTR8CLK_t cntr8clk; /* ALT_CLKMGR_PERPLL_CNTR8CLK */
4389  volatile ALT_CLKMGR_PERPLL_CNTR9CLK_t cntr9clk; /* ALT_CLKMGR_PERPLL_CNTR9CLK */
4390  volatile ALT_CLKMGR_PERPLL_EMACCTL_t emacctl; /* ALT_CLKMGR_PERPLL_EMACCTL */
4391  volatile ALT_CLKMGR_PERPLL_GPIODIV_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
4392  volatile ALT_CLKMGR_PERPLL_PLLGLOB_t pllglob; /* ALT_CLKMGR_PERPLL_PLLGLOB */
4393  volatile ALT_CLKMGR_PERPLL_FDBCK_t fdbck; /* ALT_CLKMGR_PERPLL_FDBCK */
4394  volatile ALT_CLKMGR_PERPLL_MEM_t mem; /* ALT_CLKMGR_PERPLL_MEM */
4395  volatile ALT_CLKMGR_PERPLL_MEMSTAT_t memstat; /* ALT_CLKMGR_PERPLL_MEMSTAT */
4396  volatile ALT_CLKMGR_PERPLL_PLLC0_t pllc0; /* ALT_CLKMGR_PERPLL_PLLC0 */
4397  volatile ALT_CLKMGR_PERPLL_PLLC1_t pllc1; /* ALT_CLKMGR_PERPLL_PLLC1 */
4398  volatile ALT_CLKMGR_PERPLL_VCOCALIB_t vcocalib; /* ALT_CLKMGR_PERPLL_VCOCALIB */
4399  volatile uint32_t _pad_0x5c_0x80[9]; /* *UNDEFINED* */
4400 };
4401 
4402 /* The typedef declaration for register group ALT_CLKMGR_PERPLL. */
4403 typedef struct ALT_CLKMGR_PERPLL_s ALT_CLKMGR_PERPLL_t;
4404 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
4405 struct ALT_CLKMGR_PERPLL_raw_s
4406 {
4407  volatile uint32_t en; /* ALT_CLKMGR_PERPLL_EN */
4408  volatile uint32_t ens; /* ALT_CLKMGR_PERPLL_ENS */
4409  volatile uint32_t enr; /* ALT_CLKMGR_PERPLL_ENR */
4410  volatile uint32_t bypass; /* ALT_CLKMGR_PERPLL_BYPASS */
4411  volatile uint32_t bypasss; /* ALT_CLKMGR_PERPLL_BYPASSS */
4412  volatile uint32_t bypassr; /* ALT_CLKMGR_PERPLL_BYPASSR */
4413  volatile uint32_t cntr2clk; /* ALT_CLKMGR_PERPLL_CNTR2CLK */
4414  volatile uint32_t cntr3clk; /* ALT_CLKMGR_PERPLL_CNTR3CLK */
4415  volatile uint32_t cntr4clk; /* ALT_CLKMGR_PERPLL_CNTR4CLK */
4416  volatile uint32_t cntr5clk; /* ALT_CLKMGR_PERPLL_CNTR5CLK */
4417  volatile uint32_t cntr6clk; /* ALT_CLKMGR_PERPLL_CNTR6CLK */
4418  volatile uint32_t cntr7clk; /* ALT_CLKMGR_PERPLL_CNTR7CLK */
4419  volatile uint32_t cntr8clk; /* ALT_CLKMGR_PERPLL_CNTR8CLK */
4420  volatile uint32_t cntr9clk; /* ALT_CLKMGR_PERPLL_CNTR9CLK */
4421  volatile uint32_t emacctl; /* ALT_CLKMGR_PERPLL_EMACCTL */
4422  volatile uint32_t gpiodiv; /* ALT_CLKMGR_PERPLL_GPIODIV */
4423  volatile uint32_t pllglob; /* ALT_CLKMGR_PERPLL_PLLGLOB */
4424  volatile uint32_t fdbck; /* ALT_CLKMGR_PERPLL_FDBCK */
4425  volatile uint32_t mem; /* ALT_CLKMGR_PERPLL_MEM */
4426  volatile uint32_t memstat; /* ALT_CLKMGR_PERPLL_MEMSTAT */
4427  volatile uint32_t pllc0; /* ALT_CLKMGR_PERPLL_PLLC0 */
4428  volatile uint32_t pllc1; /* ALT_CLKMGR_PERPLL_PLLC1 */
4429  volatile uint32_t vcocalib; /* ALT_CLKMGR_PERPLL_VCOCALIB */
4430  volatile uint32_t _pad_0x5c_0x80[9]; /* *UNDEFINED* */
4431 };
4432 
4433 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_PERPLL. */
4434 typedef struct ALT_CLKMGR_PERPLL_raw_s ALT_CLKMGR_PERPLL_raw_t;
4435 #endif /* __ASSEMBLY__ */
4436 
4437 
4438 #ifdef __cplusplus
4439 }
4440 #endif /* __cplusplus */
4441 #endif /* __ALT_SOCAL_CLKMGR_PERPLL_H__ */
4442