35 #ifndef __ALTERA_ALT_QSPI_H__
36 #define __ALTERA_ALT_QSPI_H__
97 #define ALT_QSPI_CFG_EN_E_DIS 0x0
103 #define ALT_QSPI_CFG_EN_E_EN 0x1
106 #define ALT_QSPI_CFG_EN_LSB 0
108 #define ALT_QSPI_CFG_EN_MSB 0
110 #define ALT_QSPI_CFG_EN_WIDTH 1
112 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
114 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
116 #define ALT_QSPI_CFG_EN_RESET 0x0
118 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
120 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
142 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
148 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
151 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
153 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
155 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
157 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
159 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
161 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
163 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
165 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
188 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
194 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
197 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
199 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
201 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
203 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
205 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
207 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
209 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
211 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
236 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
242 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
245 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
247 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
249 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
251 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
253 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
255 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
257 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
259 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
286 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
292 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
295 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
297 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
299 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
301 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
303 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
305 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
307 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
309 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
332 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
338 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
341 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
343 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
345 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
347 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
349 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
351 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
353 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
355 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
369 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
371 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
373 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
375 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
377 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
379 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
381 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
383 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
407 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
413 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
416 #define ALT_QSPI_CFG_WP_LSB 14
418 #define ALT_QSPI_CFG_WP_MSB 14
420 #define ALT_QSPI_CFG_WP_WIDTH 1
422 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
424 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
426 #define ALT_QSPI_CFG_WP_RESET 0x0
428 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
430 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
453 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
459 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
462 #define ALT_QSPI_CFG_ENDMA_LSB 15
464 #define ALT_QSPI_CFG_ENDMA_MSB 15
466 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
468 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
470 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
472 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
474 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
476 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
500 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
506 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
509 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
511 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
513 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
515 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
517 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
519 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
521 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
523 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
555 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
561 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
564 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
566 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
568 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
570 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
572 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
574 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
576 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
578 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
610 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
616 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
619 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
621 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
623 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
625 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
627 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
629 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
631 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
633 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
669 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
675 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
681 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
687 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
693 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
699 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
705 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
711 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
717 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
723 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
729 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
735 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
741 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
747 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
753 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
759 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
762 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
764 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
766 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
768 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
770 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
772 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
774 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
776 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
799 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
805 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
808 #define ALT_QSPI_CFG_IDLE_LSB 31
810 #define ALT_QSPI_CFG_IDLE_MSB 31
812 #define ALT_QSPI_CFG_IDLE_WIDTH 1
814 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
816 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
818 #define ALT_QSPI_CFG_IDLE_RESET 0x0
820 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
822 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
835 struct ALT_QSPI_CFG_s
838 uint32_t selclkpol : 1;
839 uint32_t selclkphase : 1;
841 uint32_t endiracc : 1;
842 uint32_t enlegacyip : 1;
843 uint32_t perseldec : 1;
844 uint32_t percslines : 4;
847 uint32_t enahbremap : 1;
848 uint32_t enterxipnextrd : 1;
849 uint32_t enterxipimm : 1;
850 uint32_t bauddiv : 4;
852 const uint32_t idle : 1;
856 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
860 #define ALT_QSPI_CFG_OFST 0x0
902 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
908 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
911 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
913 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
915 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
917 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
919 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
921 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
923 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
925 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
954 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
961 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
968 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
971 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
973 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
975 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
977 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
979 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
981 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
983 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
985 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1017 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1025 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1033 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1036 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1038 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1040 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1042 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1044 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1046 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1048 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1050 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1082 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1090 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1098 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1101 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1103 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1105 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1107 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1109 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1111 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1113 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1115 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1138 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1144 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1147 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1149 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1151 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1153 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1155 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1157 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1159 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1161 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1172 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1174 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1176 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1178 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1180 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1182 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1184 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1186 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1188 #ifndef __ASSEMBLY__
1199 struct ALT_QSPI_DEVRD_s
1201 uint32_t rdopcode : 8;
1202 uint32_t instwidth : 2;
1204 uint32_t addrwidth : 2;
1206 uint32_t datawidth : 2;
1208 uint32_t enmodebits : 1;
1210 uint32_t dummyrdclks : 5;
1215 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1219 #define ALT_QSPI_DEVRD_OFST 0x4
1247 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1249 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1251 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1253 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1255 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1257 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1259 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1261 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1293 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1301 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1309 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1312 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1314 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1316 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1318 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1320 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1322 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1324 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1326 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1358 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1366 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1374 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1377 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1379 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1381 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1383 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1385 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1387 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1389 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1391 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1402 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1404 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1406 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1408 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1410 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1412 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1414 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1416 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1418 #ifndef __ASSEMBLY__
1429 struct ALT_QSPI_DEVWR_s
1431 uint32_t wropcode : 8;
1433 uint32_t addrwidth : 2;
1435 uint32_t datawidth : 2;
1437 uint32_t dummywrclks : 5;
1442 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1446 #define ALT_QSPI_DEVWR_OFST 0x8
1474 #define ALT_QSPI_DELAY_INIT_LSB 0
1476 #define ALT_QSPI_DELAY_INIT_MSB 7
1478 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1480 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1482 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1484 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1486 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1488 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1502 #define ALT_QSPI_DELAY_AFTER_LSB 8
1504 #define ALT_QSPI_DELAY_AFTER_MSB 15
1506 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1508 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1510 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1512 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1514 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1516 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1529 #define ALT_QSPI_DELAY_BTWN_LSB 16
1531 #define ALT_QSPI_DELAY_BTWN_MSB 23
1533 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1535 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1537 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1539 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1541 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1543 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1557 #define ALT_QSPI_DELAY_NSS_LSB 24
1559 #define ALT_QSPI_DELAY_NSS_MSB 31
1561 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1563 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1565 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1567 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1569 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1571 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1573 #ifndef __ASSEMBLY__
1584 struct ALT_QSPI_DELAY_s
1593 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1597 #define ALT_QSPI_DELAY_OFST 0xc
1631 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
1637 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
1640 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1642 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1644 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1646 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1648 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1650 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1652 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1654 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1665 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1667 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1669 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1671 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1673 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1675 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1677 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1679 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1681 #ifndef __ASSEMBLY__
1692 struct ALT_QSPI_RDDATACAP_s
1700 typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
1704 #define ALT_QSPI_RDDATACAP_OFST 0x10
1728 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
1730 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
1732 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
1734 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
1736 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
1738 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
1740 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1742 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
1754 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
1756 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
1758 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
1760 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
1762 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
1764 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
1766 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
1768 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
1781 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
1783 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
1785 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
1787 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
1789 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
1791 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
1793 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
1795 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
1797 #ifndef __ASSEMBLY__
1808 struct ALT_QSPI_DEVSZ_s
1810 uint32_t numaddrbytes : 4;
1811 uint32_t bytesperdevicepage : 12;
1812 uint32_t bytespersubsector : 5;
1817 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
1821 #define ALT_QSPI_DEVSZ_OFST 0x14
1845 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
1847 #define ALT_QSPI_SRAMPART_ADDR_MSB 6
1849 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 7
1851 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
1853 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
1855 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x40
1857 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
1859 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
1861 #ifndef __ASSEMBLY__
1872 struct ALT_QSPI_SRAMPART_s
1879 typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
1883 #define ALT_QSPI_SRAMPART_OFST 0x18
1907 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
1909 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
1911 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
1913 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
1915 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
1917 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
1919 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
1921 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
1923 #ifndef __ASSEMBLY__
1934 struct ALT_QSPI_INDADDRTRIG_s
1940 typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
1944 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
1971 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
1973 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
1975 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
1977 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
1979 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
1981 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
1983 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1985 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
1999 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2001 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2003 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2005 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2007 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2009 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2011 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2013 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2015 #ifndef __ASSEMBLY__
2026 struct ALT_QSPI_DMAPER_s
2028 uint32_t numsglreqbytes : 4;
2030 uint32_t numburstreqbytes : 4;
2035 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2039 #define ALT_QSPI_DMAPER_OFST 0x20
2064 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2066 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2068 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2070 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2072 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2074 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2076 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2078 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2080 #ifndef __ASSEMBLY__
2091 struct ALT_QSPI_REMAPADDR_s
2093 uint32_t value : 32;
2097 typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2101 #define ALT_QSPI_REMAPADDR_OFST 0x24
2124 #define ALT_QSPI_MODBIT_MOD_LSB 0
2126 #define ALT_QSPI_MODBIT_MOD_MSB 7
2128 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
2130 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2132 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2134 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
2136 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2138 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2140 #ifndef __ASSEMBLY__
2151 struct ALT_QSPI_MODBIT_s
2158 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2162 #define ALT_QSPI_MODBIT_OFST 0x28
2182 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2184 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2186 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2188 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2190 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2192 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2194 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2196 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2205 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2207 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2209 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2211 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2213 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2215 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2217 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2219 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2221 #ifndef __ASSEMBLY__
2232 struct ALT_QSPI_SRAMFILL_s
2234 const uint32_t indrdpart : 16;
2235 const uint32_t indwrpart : 16;
2239 typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2243 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2265 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2267 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2269 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2271 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2273 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2275 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2277 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2279 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2281 #ifndef __ASSEMBLY__
2292 struct ALT_QSPI_TXTHRESH_s
2299 typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2303 #define ALT_QSPI_TXTHRESH_OFST 0x30
2327 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2329 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2331 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2333 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2335 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2337 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2339 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2341 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2343 #ifndef __ASSEMBLY__
2354 struct ALT_QSPI_RXTHRESH_s
2361 typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2365 #define ALT_QSPI_RXTHRESH_OFST 0x34
2419 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2425 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2428 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2430 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2432 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2434 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2436 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2438 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2440 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2442 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2464 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2470 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2473 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2475 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2477 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2479 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2481 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2483 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2485 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2487 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2510 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
2516 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
2519 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
2521 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
2523 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
2525 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
2527 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
2529 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
2531 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
2533 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
2555 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
2561 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
2564 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
2566 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
2568 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
2570 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
2572 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
2574 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
2576 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
2578 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
2601 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
2607 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
2610 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
2612 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
2614 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
2616 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
2618 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
2620 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
2622 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
2624 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
2646 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
2652 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
2655 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
2657 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
2659 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
2661 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
2663 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
2665 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
2667 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
2669 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
2695 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
2701 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
2704 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
2706 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
2708 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
2710 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
2712 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
2714 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
2716 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
2718 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
2741 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
2747 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
2750 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
2752 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
2754 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
2756 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
2758 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
2760 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
2762 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
2764 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
2787 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
2793 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
2796 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
2798 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
2800 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
2802 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
2804 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
2806 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
2808 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
2810 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
2833 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
2839 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
2842 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
2844 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
2846 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
2848 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
2850 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
2852 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
2854 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
2856 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
2879 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
2885 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
2888 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
2890 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
2892 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
2894 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
2896 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
2898 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
2900 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
2902 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
2925 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
2931 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
2934 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
2936 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
2938 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
2940 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
2942 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
2944 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
2946 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
2948 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
2950 #ifndef __ASSEMBLY__
2961 struct ALT_QSPI_IRQSTAT_s
2964 uint32_t underflowdet : 1;
2965 uint32_t indopdone : 1;
2966 uint32_t indrdreject : 1;
2967 uint32_t protwrattempt : 1;
2968 uint32_t illegalacc : 1;
2969 uint32_t indxfrlvl : 1;
2970 uint32_t rxover : 1;
2971 uint32_t txthreshcmp : 1;
2972 uint32_t txfull : 1;
2973 uint32_t rxthreshcmp : 1;
2974 uint32_t rxfull : 1;
2975 uint32_t indsramfull : 1;
2980 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
2984 #define ALT_QSPI_IRQSTAT_OFST 0x40
3031 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3037 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3040 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3042 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3044 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3046 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3048 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3050 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3052 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3054 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3074 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3080 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3083 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3085 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3087 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3089 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3091 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3093 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3095 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3097 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3117 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3123 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3126 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3128 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3130 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3132 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3134 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3136 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3138 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3140 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3160 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3166 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3169 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3171 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3173 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3175 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3177 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3179 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3181 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3183 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3203 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3209 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3212 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3214 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3216 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3218 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3220 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3222 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3224 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3226 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3246 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3252 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3255 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3257 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3259 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3261 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3263 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3265 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3267 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3269 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3289 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3295 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3298 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3300 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3302 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3304 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3306 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3308 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3310 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3312 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3332 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3338 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3341 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3343 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3345 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3347 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3349 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3351 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3353 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3355 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3375 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3381 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3384 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3386 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3388 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3390 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3392 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3394 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3396 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3398 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3418 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3424 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3427 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3429 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3431 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3433 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3435 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3437 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3439 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3441 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3461 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
3467 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
3470 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
3472 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
3474 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
3476 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
3478 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
3480 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
3482 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3484 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3504 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
3510 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
3513 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
3515 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
3517 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
3519 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
3521 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
3523 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
3525 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3527 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3529 #ifndef __ASSEMBLY__
3540 struct ALT_QSPI_IRQMSK_s
3543 uint32_t underflowdet : 1;
3544 uint32_t indopdone : 1;
3545 uint32_t indrdreject : 1;
3546 uint32_t protwrattempt : 1;
3547 uint32_t illegalacc : 1;
3548 uint32_t indxfrlvl : 1;
3549 uint32_t rxover : 1;
3550 uint32_t txthreshcmp : 1;
3551 uint32_t txfull : 1;
3552 uint32_t rxthreshcmp : 1;
3553 uint32_t rxfull : 1;
3554 uint32_t indsramfull : 1;
3559 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
3563 #define ALT_QSPI_IRQMSK_OFST 0x44
3586 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
3588 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
3590 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
3592 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3594 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3596 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
3598 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3600 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3602 #ifndef __ASSEMBLY__
3613 struct ALT_QSPI_LOWWRPROT_s
3615 uint32_t subsector : 32;
3619 typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
3623 #define ALT_QSPI_LOWWRPROT_OFST 0x50
3646 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
3648 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
3650 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
3652 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3654 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3656 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
3658 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3660 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3662 #ifndef __ASSEMBLY__
3673 struct ALT_QSPI_UPPWRPROT_s
3675 uint32_t subsector : 32;
3679 typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
3683 #define ALT_QSPI_UPPWRPROT_OFST 0x54
3721 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
3727 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
3730 #define ALT_QSPI_WRPROT_INV_LSB 0
3732 #define ALT_QSPI_WRPROT_INV_MSB 0
3734 #define ALT_QSPI_WRPROT_INV_WIDTH 1
3736 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
3738 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
3740 #define ALT_QSPI_WRPROT_INV_RESET 0x0
3742 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
3744 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
3769 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
3775 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
3778 #define ALT_QSPI_WRPROT_EN_LSB 1
3780 #define ALT_QSPI_WRPROT_EN_MSB 1
3782 #define ALT_QSPI_WRPROT_EN_WIDTH 1
3784 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
3786 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
3788 #define ALT_QSPI_WRPROT_EN_RESET 0x0
3790 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
3792 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
3794 #ifndef __ASSEMBLY__
3805 struct ALT_QSPI_WRPROT_s
3813 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
3817 #define ALT_QSPI_WRPROT_OFST 0x58
3858 #define ALT_QSPI_INDRD_START_E_END 0x1
3864 #define ALT_QSPI_INDRD_START_E_DISD 0x0
3867 #define ALT_QSPI_INDRD_START_LSB 0
3869 #define ALT_QSPI_INDRD_START_MSB 0
3871 #define ALT_QSPI_INDRD_START_WIDTH 1
3873 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
3875 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
3877 #define ALT_QSPI_INDRD_START_RESET 0x0
3879 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
3881 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
3903 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
3909 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
3912 #define ALT_QSPI_INDRD_CANCEL_LSB 1
3914 #define ALT_QSPI_INDRD_CANCEL_MSB 1
3916 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
3918 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
3920 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
3922 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
3924 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
3926 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
3948 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
3954 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
3957 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
3959 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
3961 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
3963 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
3965 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
3967 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
3969 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
3971 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
3994 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4000 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4003 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4005 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4007 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4009 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4011 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4013 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4015 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4017 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4039 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4045 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4048 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4050 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4052 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4054 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4056 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4058 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4060 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4062 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4085 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4091 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4094 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4096 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4098 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4100 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4102 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4104 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4106 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4108 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4120 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4122 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4124 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4126 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4128 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4130 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4132 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4134 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4136 #ifndef __ASSEMBLY__
4147 struct ALT_QSPI_INDRD_s
4150 uint32_t cancel : 1;
4151 const uint32_t rd_status : 1;
4152 uint32_t sram_full : 1;
4153 const uint32_t rd_queued : 1;
4154 uint32_t ind_ops_done_status : 1;
4155 const uint32_t num_ind_ops_done : 2;
4160 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4164 #define ALT_QSPI_INDRD_OFST 0x60
4188 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4190 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4192 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4194 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4196 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4198 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4200 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4202 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4204 #ifndef __ASSEMBLY__
4215 struct ALT_QSPI_INDRDWATER_s
4217 uint32_t level : 32;
4221 typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4225 #define ALT_QSPI_INDRDWATER_OFST 0x64
4247 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4249 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4251 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4253 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4255 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4257 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4259 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4261 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4263 #ifndef __ASSEMBLY__
4274 struct ALT_QSPI_INDRDSTADDR_s
4280 typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4284 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4306 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4308 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4310 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4312 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4314 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4316 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4318 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4320 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4322 #ifndef __ASSEMBLY__
4333 struct ALT_QSPI_INDRDCNT_s
4335 uint32_t value : 32;
4339 typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
4343 #define ALT_QSPI_INDRDCNT_OFST 0x6c
4384 #define ALT_QSPI_INDWR_START_E_END 0x1
4390 #define ALT_QSPI_INDWR_START_E_DISD 0x0
4393 #define ALT_QSPI_INDWR_START_LSB 0
4395 #define ALT_QSPI_INDWR_START_MSB 0
4397 #define ALT_QSPI_INDWR_START_WIDTH 1
4399 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
4401 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
4403 #define ALT_QSPI_INDWR_START_RESET 0x0
4405 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
4407 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
4429 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
4435 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
4438 #define ALT_QSPI_INDWR_CANCEL_LSB 1
4440 #define ALT_QSPI_INDWR_CANCEL_MSB 1
4442 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
4444 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
4446 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
4448 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
4450 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4452 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4474 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
4480 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
4483 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
4485 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
4487 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
4489 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
4491 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
4493 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
4495 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
4497 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
4506 #define ALT_QSPI_INDWR_SRAMFULL_LSB 3
4508 #define ALT_QSPI_INDWR_SRAMFULL_MSB 3
4510 #define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
4512 #define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
4514 #define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
4516 #define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
4518 #define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
4520 #define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
4542 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
4548 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
4551 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
4553 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
4555 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
4557 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
4559 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
4561 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
4563 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
4565 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
4588 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
4594 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
4597 #define ALT_QSPI_INDWR_INDDONE_LSB 5
4599 #define ALT_QSPI_INDWR_INDDONE_MSB 5
4601 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
4603 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
4605 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
4607 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
4609 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
4611 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
4623 #define ALT_QSPI_INDWR_INDCNT_LSB 6
4625 #define ALT_QSPI_INDWR_INDCNT_MSB 7
4627 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
4629 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
4631 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
4633 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
4635 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
4637 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
4639 #ifndef __ASSEMBLY__
4650 struct ALT_QSPI_INDWR_s
4653 uint32_t cancel : 1;
4654 const uint32_t rdstat : 1;
4655 const uint32_t sramfull : 1;
4656 const uint32_t rdqueued : 1;
4657 uint32_t inddone : 1;
4658 const uint32_t indcnt : 2;
4663 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
4667 #define ALT_QSPI_INDWR_OFST 0x70
4691 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
4693 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
4695 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
4697 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
4699 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
4701 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
4703 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4705 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4707 #ifndef __ASSEMBLY__
4718 struct ALT_QSPI_INDWRWATER_s
4720 uint32_t level : 32;
4724 typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
4728 #define ALT_QSPI_INDWRWATER_OFST 0x74
4750 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
4752 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
4754 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
4756 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
4758 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
4760 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
4762 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4764 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4766 #ifndef __ASSEMBLY__
4777 struct ALT_QSPI_INDWRSTADDR_s
4783 typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
4787 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
4809 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
4811 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
4813 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
4815 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
4817 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
4819 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
4821 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4823 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4825 #ifndef __ASSEMBLY__
4836 struct ALT_QSPI_INDWRCNT_s
4838 uint32_t value : 32;
4842 typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
4846 #define ALT_QSPI_INDWRCNT_OFST 0x7c
4889 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
4895 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
4898 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
4900 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
4902 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
4904 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
4906 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
4908 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
4910 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
4912 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
4934 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
4940 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
4943 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
4945 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
4947 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
4949 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
4951 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
4953 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
4955 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
4957 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
4969 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
4971 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
4973 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
4975 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
4977 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
4979 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
4981 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
4983 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5011 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5017 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5023 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5029 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5035 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5041 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5047 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5053 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5056 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5058 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5060 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5062 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5064 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5066 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5068 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5070 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5093 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5099 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5102 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5104 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5106 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5108 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5110 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5112 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5114 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5116 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5143 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5149 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5155 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5161 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5164 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5166 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5168 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5170 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5172 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5174 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5176 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5178 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5201 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5207 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5210 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5212 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5214 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5216 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5218 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5220 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5222 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5224 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5247 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5253 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5256 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5258 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5260 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5262 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5264 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5266 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5268 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5270 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5299 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
5305 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
5311 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
5317 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
5323 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
5329 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
5335 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
5341 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
5344 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
5346 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
5348 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
5350 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
5352 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
5354 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
5356 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
5358 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
5381 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
5387 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
5390 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
5392 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
5394 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
5396 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
5398 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
5400 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
5402 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
5404 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
5425 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
5427 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
5429 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
5431 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
5433 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
5435 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
5437 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
5439 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
5441 #ifndef __ASSEMBLY__
5452 struct ALT_QSPI_FLSHCMD_s
5454 uint32_t execcmd : 1;
5455 const uint32_t cmdexecstat : 1;
5457 uint32_t numdummybytes : 5;
5458 uint32_t numwrdatabytes : 3;
5459 uint32_t enwrdata : 1;
5460 uint32_t numaddrbytes : 2;
5461 uint32_t enmodebit : 1;
5462 uint32_t encmdaddr : 1;
5463 uint32_t numrddatabytes : 3;
5464 uint32_t enrddata : 1;
5465 uint32_t cmdopcode : 8;
5469 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
5473 #define ALT_QSPI_FLSHCMD_OFST 0x90
5497 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
5499 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
5501 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
5503 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
5505 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
5507 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
5509 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5511 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5513 #ifndef __ASSEMBLY__
5524 struct ALT_QSPI_FLSHCMDADDR_s
5530 typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
5534 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
5558 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
5560 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
5562 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
5564 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
5566 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
5568 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
5570 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5572 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5574 #ifndef __ASSEMBLY__
5585 struct ALT_QSPI_FLSHCMDRDDATALO_s
5591 typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
5595 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
5621 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
5623 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
5625 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
5627 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
5629 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
5631 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
5633 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5635 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5637 #ifndef __ASSEMBLY__
5648 struct ALT_QSPI_FLSHCMDRDDATAUP_s
5654 typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
5658 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
5683 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
5685 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
5687 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
5689 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
5691 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
5693 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
5695 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5697 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5699 #ifndef __ASSEMBLY__
5710 struct ALT_QSPI_FLSHCMDWRDATALO_s
5716 typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
5720 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
5745 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
5747 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
5749 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
5751 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
5753 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
5755 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
5757 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5759 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5761 #ifndef __ASSEMBLY__
5772 struct ALT_QSPI_FLSHCMDWRDATAUP_s
5778 typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
5782 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
5802 #define ALT_QSPI_MODULEID_VALUE_LSB 0
5804 #define ALT_QSPI_MODULEID_VALUE_MSB 24
5806 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
5808 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
5810 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
5812 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
5814 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
5816 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
5818 #ifndef __ASSEMBLY__
5829 struct ALT_QSPI_MODULEID_s
5831 const uint32_t value : 25;
5836 typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
5840 #define ALT_QSPI_MODULEID_OFST 0xfc
5842 #ifndef __ASSEMBLY__
5856 ALT_QSPI_DEVRD_t devrd;
5857 ALT_QSPI_DEVWR_t devwr;
5858 ALT_QSPI_DELAY_t delay;
5859 ALT_QSPI_RDDATACAP_t rddatacap;
5860 ALT_QSPI_DEVSZ_t devsz;
5861 ALT_QSPI_SRAMPART_t srampart;
5862 ALT_QSPI_INDADDRTRIG_t indaddrtrig;
5863 ALT_QSPI_DMAPER_t dmaper;
5864 ALT_QSPI_REMAPADDR_t remapaddr;
5865 ALT_QSPI_MODBIT_t modebit;
5866 ALT_QSPI_SRAMFILL_t sramfill;
5867 ALT_QSPI_TXTHRESH_t txthresh;
5868 ALT_QSPI_RXTHRESH_t rxthresh;
5869 volatile uint32_t _pad_0x38_0x3f[2];
5870 ALT_QSPI_IRQSTAT_t irqstat;
5871 ALT_QSPI_IRQMSK_t irqmask;
5872 volatile uint32_t _pad_0x48_0x4f[2];
5873 ALT_QSPI_LOWWRPROT_t lowwrprot;
5874 ALT_QSPI_UPPWRPROT_t uppwrprot;
5875 ALT_QSPI_WRPROT_t wrprot;
5876 volatile uint32_t _pad_0x5c_0x5f;
5877 ALT_QSPI_INDRD_t indrd;
5878 ALT_QSPI_INDRDWATER_t indrdwater;
5879 ALT_QSPI_INDRDSTADDR_t indrdstaddr;
5880 ALT_QSPI_INDRDCNT_t indrdcnt;
5881 ALT_QSPI_INDWR_t indwr;
5882 ALT_QSPI_INDWRWATER_t indwrwater;
5883 ALT_QSPI_INDWRSTADDR_t indwrstaddr;
5884 ALT_QSPI_INDWRCNT_t indwrcnt;
5885 volatile uint32_t _pad_0x80_0x8f[4];
5886 ALT_QSPI_FLSHCMD_t flashcmd;
5887 ALT_QSPI_FLSHCMDADDR_t flashcmdaddr;
5888 volatile uint32_t _pad_0x98_0x9f[2];
5889 ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo;
5890 ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup;
5891 ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo;
5892 ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup;
5893 volatile uint32_t _pad_0xb0_0xfb[19];
5894 ALT_QSPI_MODULEID_t moduleid;
5898 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
5900 struct ALT_QSPI_raw_s
5902 volatile uint32_t cfg;
5903 volatile uint32_t devrd;
5904 volatile uint32_t devwr;
5905 volatile uint32_t delay;
5906 volatile uint32_t rddatacap;
5907 volatile uint32_t devsz;
5908 volatile uint32_t srampart;
5909 volatile uint32_t indaddrtrig;
5910 volatile uint32_t dmaper;
5911 volatile uint32_t remapaddr;
5912 volatile uint32_t modebit;
5913 volatile uint32_t sramfill;
5914 volatile uint32_t txthresh;
5915 volatile uint32_t rxthresh;
5916 uint32_t _pad_0x38_0x3f[2];
5917 volatile uint32_t irqstat;
5918 volatile uint32_t irqmask;
5919 uint32_t _pad_0x48_0x4f[2];
5920 volatile uint32_t lowwrprot;
5921 volatile uint32_t uppwrprot;
5922 volatile uint32_t wrprot;
5923 uint32_t _pad_0x5c_0x5f;
5924 volatile uint32_t indrd;
5925 volatile uint32_t indrdwater;
5926 volatile uint32_t indrdstaddr;
5927 volatile uint32_t indrdcnt;
5928 volatile uint32_t indwr;
5929 volatile uint32_t indwrwater;
5930 volatile uint32_t indwrstaddr;
5931 volatile uint32_t indwrcnt;
5932 uint32_t _pad_0x80_0x8f[4];
5933 volatile uint32_t flashcmd;
5934 volatile uint32_t flashcmdaddr;
5935 uint32_t _pad_0x98_0x9f[2];
5936 volatile uint32_t flashcmdrddatalo;
5937 volatile uint32_t flashcmdrddataup;
5938 volatile uint32_t flashcmdwrdatalo;
5939 volatile uint32_t flashcmdwrdataup;
5940 uint32_t _pad_0xb0_0xfb[19];
5941 volatile uint32_t moduleid;
5945 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;