Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
altx_ethernet.h
Go to the documentation of this file.
1 /******************************************************************************
2  *
3  * Copyright 2017 Altera Corporation. All Rights Reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its contributors
16  * may be used to endorse or promote products derived from this software without
17  * specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  ******************************************************************************/
38 #ifndef __ALTX_ETHERNET_H__
39 #define __ALTX_ETHERNET_H__
40 
41 #ifdef __cplusplus
42 extern "C"
43 {
44 #endif /* __cplusplus */
45 
46 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_PA_SET ALT_EMAC_GMAC_GMII_ADDR_PA_SET
47 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_GR_SET ALT_EMAC_GMAC_GMII_ADDR_GR_SET
48 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_GW_CLR_MSK ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK
49 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_GW_SET_MSK ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK
50 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_CR_SET ALT_EMAC_GMAC_GMII_ADDR_CR_SET
51 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_CR_E_DIV102 ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102
52 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_GB_SET ALT_EMAC_GMAC_GMII_ADDR_GB_SET
53 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_GB_SET_MSK ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK
54 #define ALTX_EMAC_GMACGRP_GMII_ADDRESS_ADDR ALT_EMAC_GMAC_GMII_ADDR_ADDR
55 #define ALTX_EMAC_GMACGRP_GMII_DATA_ADDR ALT_EMAC_GMAC_GMII_DATA_ADDR
56 
57 #define ALTX_SYSMGR_CORE_EMAC0_ADDR ALT_SYSMGR_EMAC0_ADDR
58 #define ALTX_SYSMGR_CORE_EMAC1_ADDR ALT_SYSMGR_EMAC1_ADDR
59 #define ALTX_SYSMGR_CORE_EMAC2_ADDR ALT_SYSMGR_EMAC2_ADDR
60 #define ALTX_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_0_SET_MSK ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET_MSK
61 #define ALTX_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_1_SET_MSK ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET_MSK
62 #define ALTX_SYSMGR_CORE_FPGAINTF_EN_3_EMAC_2_SET_MSK ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET_MSK
63 #define ALTX_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_SET_MSK ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK
64 #define ALTX_SYSMGR_CORE_EMAC1_PHY_INTF_SEL_SET_MSK ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK
65 #define ALTX_SYSMGR_CORE_EMAC2_PHY_INTF_SEL_SET_MSK ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK
66 #define ALTX_SYSMGR_CORE_EMAC0_PHY_INTF_SEL_E_RGMII ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII
67 #define ALTX_SYSMGR_CORE_FPGAINTF_EN_3_ADDR ALT_SYSMGR_FPGAINTF_EN_3_ADDR
68 
69 #define ALTX_EMAC_DMAGRP_AHB_OR_AXI_STATUS_ADDR ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR
70 #define ALTX_EMAC_DMAGRP_BUS_MODE_AAL_SET_MSK ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK
71 #define ALTX_EMAC_DMAGRP_BUS_MODE_ADDR ALT_EMAC_DMA_BUS_MOD_ADDR
72 #define ALTX_EMAC_DMAGRP_BUS_MODE_ATDS_SET_MSK ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK
73 #define ALTX_EMAC_DMAGRP_BUS_MODE_EIGHTXPBL_SET ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET
74 #define ALTX_EMAC_DMAGRP_BUS_MODE_FB_SET_MSK ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK
75 #define ALTX_EMAC_DMAGRP_BUS_MODE_PBL_SET ALT_EMAC_DMA_BUS_MOD_PBL_SET
76 #define ALTX_EMAC_DMAGRP_BUS_MODE_RPBL_SET ALT_EMAC_DMA_BUS_MOD_RPBL_SET
77 #define ALTX_EMAC_DMAGRP_BUS_MODE_SWR_GET ALT_EMAC_DMA_BUS_MOD_SWR_GET
78 #define ALTX_EMAC_DMAGRP_BUS_MODE_SWR_SET_MSK ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK
79 #define ALTX_EMAC_DMAGRP_BUS_MODE_USP_SET_MSK ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK
80 #define ALTX_EMAC_DMAGRP_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_ADDR ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR
81 #define ALTX_EMAC_DMAGRP_CURRENT_HOST_RECEIVE_DESCRIPTOR_ADDR ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR
82 #define ALTX_EMAC_DMAGRP_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_ADDR ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR
83 #define ALTX_EMAC_DMAGRP_CURRENT_HOST_TRANSMIT_DESCRIPTOR_ADDR ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR
84 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_ADDR ALT_EMAC_DMA_INT_EN_ADDR
85 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_NIE_SET_MSK ALT_EMAC_DMA_INT_EN_NIE_SET_MSK
86 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_TUE_SET_MSK ALT_EMAC_DMA_INT_EN_TUE_SET_MSK
87 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_AIE_SET_MSK ALT_EMAC_DMA_INT_EN_AIE_SET_MSK
88 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_ERE_SET_MSK ALT_EMAC_DMA_INT_EN_ERE_SET_MSK
89 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_ETE_SET_MSK ALT_EMAC_DMA_INT_EN_ETE_SET_MSK
90 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_FBE_SET_MSK ALT_EMAC_DMA_INT_EN_FBE_SET_MSK
91 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_OVE_SET_MSK ALT_EMAC_DMA_INT_EN_OVE_SET_MSK
92 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_RIE_SET_MSK ALT_EMAC_DMA_INT_EN_RIE_SET_MSK
93 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_RSE_SET_MSK ALT_EMAC_DMA_INT_EN_RSE_SET_MSK
94 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_RUE_SET_MSK ALT_EMAC_DMA_INT_EN_RUE_SET_MSK
95 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_RWE_SET_MSK ALT_EMAC_DMA_INT_EN_RWE_SET_MSK
96 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_TIE_SET_MSK ALT_EMAC_DMA_INT_EN_TIE_SET_MSK
97 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_TJE_SET_MSK ALT_EMAC_DMA_INT_EN_TJE_SET_MSK
98 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_TSE_SET_MSK ALT_EMAC_DMA_INT_EN_TSE_SET_MSK
99 #define ALTX_EMAC_DMAGRP_INTERRUPT_ENABLE_UNE_SET_MSK ALT_EMAC_DMA_INT_EN_UNE_SET_MSK
100 #define ALTX_EMAC_DMAGRP_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_ADDR ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR
101 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_ADDR ALT_EMAC_DMA_OP_MOD_ADDR
102 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_FTF_GET ALT_EMAC_DMA_OP_MOD_FTF_GET
103 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK
104 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_OSF_SET_MSK ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK
105 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_RSF_SET_MSK ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK
106 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_SR_SET_MSK ALT_EMAC_DMA_OP_MOD_SR_SET_MSK
107 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_ST_SET_MSK ALT_EMAC_DMA_OP_MOD_ST_SET_MSK
108 #define ALTX_EMAC_DMAGRP_OPERATION_MODE_TSF_SET_MSK ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK
109 #define ALTX_EMAC_DMAGRP_RECEIVE_DESCRIPTOR_LIST_ADDRESS_ADDR ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR
110 #define ALTX_EMAC_DMAGRP_RECEIVE_POLL_DEMAND_ADDR ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR
111 #define ALTX_EMAC_DMAGRP_STATUS_ADDR ALT_EMAC_DMA_STAT_ADDR
112 #define ALTX_EMAC_DMAGRP_STATUS_OVF_SET_MSK ALT_EMAC_DMA_STAT_OVF_SET_MSK
113 #define ALTX_EMAC_DMAGRP_STATUS_RS_SET_MSK ALT_EMAC_DMA_STAT_RS_SET_MSK
114 #define ALTX_EMAC_DMAGRP_STATUS_RU_SET_MSK ALT_EMAC_DMA_STAT_RU_SET_MSK
115 #define ALTX_EMAC_DMAGRP_STATUS_TS_SET_MSK ALT_EMAC_DMA_STAT_TS_SET_MSK
116 #define ALTX_EMAC_DMAGRP_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_ADDR ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR
117 #define ALTX_EMAC_DMAGRP_TRANSMIT_POLL_DEMAND_ADDR ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR
118 
119 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_IPC_SET_MSK ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK
120 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_JD_SET_MSK ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK
121 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK
122 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_BE_SET_MSK ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK
123 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_WD_SET_MSK ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK
124 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_DO_SET_MSK ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK
125 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_DM_SET_MSK ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK
126 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_FES_SET_MSK ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK
127 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK
128 #define ALTX_EMAC_GMACGRP_INTERRUPT_STATUS_LPIIS_SET_MSK ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK
129 #define ALTX_EMAC_GMACGRP_INTERRUPT_STATUS_TSIS_SET_MSK ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK
130 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR
131 #define ALTX_EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR
132 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR
133 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK
134 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR
135 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK
136 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR
137 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK
138 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_ADDR ALT_EMAC_GMAC_MAC_CFG_ADDR
139 #define ALTX_EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK
140 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_FCA_BPA_GET ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET
141 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR
142 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR
143 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_FCA_BPA_SET_MSK ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK
144 #define ALTX_EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_LNKSTS_GET ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET
145 #define ALTX_EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_ADDR ALT_EMAC_GMAC_MII_CTL_STAT_ADDR
146 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR
147 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_FCA_BPA_SET_MSK ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK
148 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_ADDR ALT_EMAC_GMAC_FLOW_CTL_ADDR
149 #define ALTX_EMAC_GMACGRP_FLOW_CONTROL_FCA_BPA_SET_MSK ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK
150 #define ALTX_EMAC_GMACGRP_INTERRUPT_STATUS_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR
151 #define ALTX_EMAC_GMACGRP_INTERRUPT_STATUS_ADDR ALT_EMAC_GMAC_INT_STAT_ADDR
152 #define ALTX_EMAC_GMACGRP_INTERRUPT_MASK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR
153 #define ALTX_EMAC_GMACGRP_INTERRUPT_MASK_ADDR ALT_EMAC_GMAC_INT_MSK_ADDR
154 #define ALTX_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR
155 #define ALTX_EMAC_GMACGRP_MAC_ADDRESS0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR
156 #define ALTX_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_ADDR ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR
157 #define ALTX_EMAC_GMACGRP_MAC_ADDRESS0_LOW_ADDR ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR
158 #define ALTX_EMAC_GMACGRP_INTERRUPT_STATUS_RGSMIIIS_SET_MSK ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK
159 
160 #ifdef __cplusplus
161 }
162 #endif /* __cplusplus */
163 
164 #endif /* __ALTX_ETHERNET_H__ */