Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Groups
alt_lwh2f.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_LWH2F */
34 
35 #ifndef __ALTERA_ALT_LWH2F_H__
36 #define __ALTERA_ALT_LWH2F_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : LWHPS2FPGA AXI Bridge Module - ALT_LWH2F
45  * LWHPS2FPGA AXI Bridge Module
46  *
47  * Registers in the LWHPS2FPGA AXI Bridge Module.
48  *
49  */
50 /*
51  * Register Group : ID Register Group - ALT_LWH2F_ID
52  * ID Register Group
53  *
54  * Contains registers that identify the ARM NIC-301 IP Core.
55  *
56  */
57 /*
58  * Register : Peripheral ID4 Register - periph_id_4
59  *
60  * JEP106 continuation code
61  *
62  * Register Layout
63  *
64  * Bits | Access | Reset | Description
65  * :-------|:-------|:------|:---------------
66  * [7:0] | R | 0x4 | Peripheral ID4
67  * [31:8] | ??? | 0x0 | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : Peripheral ID4 - periph_id_4
72  *
73  * JEP106 continuation code
74  *
75  * Field Access Macros:
76  *
77  */
78 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
79 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_LSB 0
80 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
81 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_MSB 7
82 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
83 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_WIDTH 8
84 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
85 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET_MSK 0x000000ff
86 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value. */
87 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_CLR_MSK 0xffffff00
88 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field. */
89 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_RESET 0x4
90 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 field value from a register. */
91 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_GET(value) (((value) & 0x000000ff) >> 0)
92 /* Produces a ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4 register field value suitable for setting the register. */
93 #define ALT_LWH2F_ID_PERIPH_ID_4_PERIPH_ID_4_SET(value) (((value) << 0) & 0x000000ff)
94 
95 #ifndef __ASSEMBLY__
96 /*
97  * WARNING: The C register and register group struct declarations are provided for
98  * convenience and illustrative purposes. They should, however, be used with
99  * caution as the C language standard provides no guarantees about the alignment or
100  * atomicity of device memory accesses. The recommended practice for writing
101  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102  * alt_write_word() functions.
103  *
104  * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_4.
105  */
106 struct ALT_LWH2F_ID_PERIPH_ID_4_s
107 {
108  const uint32_t periph_id_4 : 8; /* Peripheral ID4 */
109  uint32_t : 24; /* *UNDEFINED* */
110 };
111 
112 /* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_4. */
113 typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_4_s ALT_LWH2F_ID_PERIPH_ID_4_t;
114 #endif /* __ASSEMBLY__ */
115 
116 /* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_4 register from the beginning of the component. */
117 #define ALT_LWH2F_ID_PERIPH_ID_4_OFST 0xfd0
118 
119 /*
120  * Register : Peripheral ID0 Register - periph_id_0
121  *
122  * Peripheral ID0
123  *
124  * Register Layout
125  *
126  * Bits | Access | Reset | Description
127  * :-------|:-------|:------|:------------------
128  * [7:0] | R | 0x1 | Part Number [7:0]
129  * [31:8] | ??? | 0x0 | *UNDEFINED*
130  *
131  */
132 /*
133  * Field : Part Number [7:0] - pn7to0
134  *
135  * Part Number [7:0]
136  *
137  * Field Access Macros:
138  *
139  */
140 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */
141 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_LSB 0
142 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */
143 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_MSB 7
144 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */
145 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_WIDTH 8
146 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value. */
147 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_SET_MSK 0x000000ff
148 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value. */
149 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_CLR_MSK 0xffffff00
150 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field. */
151 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_RESET 0x1
152 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 field value from a register. */
153 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_GET(value) (((value) & 0x000000ff) >> 0)
154 /* Produces a ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0 register field value suitable for setting the register. */
155 #define ALT_LWH2F_ID_PERIPH_ID_0_PN7TO0_SET(value) (((value) << 0) & 0x000000ff)
156 
157 #ifndef __ASSEMBLY__
158 /*
159  * WARNING: The C register and register group struct declarations are provided for
160  * convenience and illustrative purposes. They should, however, be used with
161  * caution as the C language standard provides no guarantees about the alignment or
162  * atomicity of device memory accesses. The recommended practice for writing
163  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
164  * alt_write_word() functions.
165  *
166  * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_0.
167  */
168 struct ALT_LWH2F_ID_PERIPH_ID_0_s
169 {
170  const uint32_t pn7to0 : 8; /* Part Number [7:0] */
171  uint32_t : 24; /* *UNDEFINED* */
172 };
173 
174 /* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_0. */
175 typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_0_s ALT_LWH2F_ID_PERIPH_ID_0_t;
176 #endif /* __ASSEMBLY__ */
177 
178 /* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_0 register from the beginning of the component. */
179 #define ALT_LWH2F_ID_PERIPH_ID_0_OFST 0xfe0
180 
181 /*
182  * Register : Peripheral ID1 Register - periph_id_1
183  *
184  * Peripheral ID1
185  *
186  * Register Layout
187  *
188  * Bits | Access | Reset | Description
189  * :-------|:-------|:------|:--------------------------------
190  * [7:0] | R | 0xb3 | JEP106[3:0], Part Number [11:8]
191  * [31:8] | ??? | 0x0 | *UNDEFINED*
192  *
193  */
194 /*
195  * Field : JEP106[3:0], Part Number [11:8] - jep3to0_pn11to8
196  *
197  * JEP106[3:0], Part Number [11:8]
198  *
199  * Field Access Macros:
200  *
201  */
202 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
203 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_LSB 0
204 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
205 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_MSB 7
206 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
207 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_WIDTH 8
208 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
209 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET_MSK 0x000000ff
210 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value. */
211 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_CLR_MSK 0xffffff00
212 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field. */
213 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_RESET 0xb3
214 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 field value from a register. */
215 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_GET(value) (((value) & 0x000000ff) >> 0)
216 /* Produces a ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8 register field value suitable for setting the register. */
217 #define ALT_LWH2F_ID_PERIPH_ID_1_JEP3TO0_PN11TO8_SET(value) (((value) << 0) & 0x000000ff)
218 
219 #ifndef __ASSEMBLY__
220 /*
221  * WARNING: The C register and register group struct declarations are provided for
222  * convenience and illustrative purposes. They should, however, be used with
223  * caution as the C language standard provides no guarantees about the alignment or
224  * atomicity of device memory accesses. The recommended practice for writing
225  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
226  * alt_write_word() functions.
227  *
228  * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_1.
229  */
230 struct ALT_LWH2F_ID_PERIPH_ID_1_s
231 {
232  const uint32_t jep3to0_pn11to8 : 8; /* JEP106[3:0], Part Number [11:8] */
233  uint32_t : 24; /* *UNDEFINED* */
234 };
235 
236 /* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_1. */
237 typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_1_s ALT_LWH2F_ID_PERIPH_ID_1_t;
238 #endif /* __ASSEMBLY__ */
239 
240 /* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_1 register from the beginning of the component. */
241 #define ALT_LWH2F_ID_PERIPH_ID_1_OFST 0xfe4
242 
243 /*
244  * Register : Peripheral ID2 Register - periph_id_2
245  *
246  * Peripheral ID2
247  *
248  * Register Layout
249  *
250  * Bits | Access | Reset | Description
251  * :-------|:-------|:------|:----------------------------------------
252  * [7:0] | R | 0x6b | Revision, JEP106 code flag, JEP106[6:4]
253  * [31:8] | ??? | 0x0 | *UNDEFINED*
254  *
255  */
256 /*
257  * Field : Revision, JEP106 code flag, JEP106[6:4] - rev_jepcode_jep6to4
258  *
259  * Revision, JEP106 code flag, JEP106[6:4]
260  *
261  * Field Access Macros:
262  *
263  */
264 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
265 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_LSB 0
266 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
267 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_MSB 7
268 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
269 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_WIDTH 8
270 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
271 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET_MSK 0x000000ff
272 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value. */
273 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_CLR_MSK 0xffffff00
274 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field. */
275 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_RESET 0x6b
276 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 field value from a register. */
277 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_GET(value) (((value) & 0x000000ff) >> 0)
278 /* Produces a ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4 register field value suitable for setting the register. */
279 #define ALT_LWH2F_ID_PERIPH_ID_2_REV_JEPCODE_JEP6TO4_SET(value) (((value) << 0) & 0x000000ff)
280 
281 #ifndef __ASSEMBLY__
282 /*
283  * WARNING: The C register and register group struct declarations are provided for
284  * convenience and illustrative purposes. They should, however, be used with
285  * caution as the C language standard provides no guarantees about the alignment or
286  * atomicity of device memory accesses. The recommended practice for writing
287  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
288  * alt_write_word() functions.
289  *
290  * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_2.
291  */
292 struct ALT_LWH2F_ID_PERIPH_ID_2_s
293 {
294  const uint32_t rev_jepcode_jep6to4 : 8; /* Revision, JEP106 code flag, JEP106[6:4] */
295  uint32_t : 24; /* *UNDEFINED* */
296 };
297 
298 /* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_2. */
299 typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_2_s ALT_LWH2F_ID_PERIPH_ID_2_t;
300 #endif /* __ASSEMBLY__ */
301 
302 /* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_2 register from the beginning of the component. */
303 #define ALT_LWH2F_ID_PERIPH_ID_2_OFST 0xfe8
304 
305 /*
306  * Register : Peripheral ID3 Register - periph_id_3
307  *
308  * Peripheral ID3
309  *
310  * Register Layout
311  *
312  * Bits | Access | Reset | Description
313  * :-------|:-------|:------|:----------------------
314  * [3:0] | R | 0x0 | Customer Model Number
315  * [7:4] | R | 0x0 | Revision
316  * [31:8] | ??? | 0x0 | *UNDEFINED*
317  *
318  */
319 /*
320  * Field : Customer Model Number - cust_mod_num
321  *
322  * Customer Model Number
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
328 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_LSB 0
329 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
330 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_MSB 3
331 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
332 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_WIDTH 4
333 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
334 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET_MSK 0x0000000f
335 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value. */
336 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_CLR_MSK 0xfffffff0
337 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field. */
338 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_RESET 0x0
339 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM field value from a register. */
340 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_GET(value) (((value) & 0x0000000f) >> 0)
341 /* Produces a ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM register field value suitable for setting the register. */
342 #define ALT_LWH2F_ID_PERIPH_ID_3_CUST_MOD_NUM_SET(value) (((value) << 0) & 0x0000000f)
343 
344 /*
345  * Field : Revision - rev_and
346  *
347  * Revision
348  *
349  * Field Access Macros:
350  *
351  */
352 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */
353 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_LSB 4
354 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */
355 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_MSB 7
356 /* The width in bits of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */
357 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_WIDTH 4
358 /* The mask used to set the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value. */
359 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_SET_MSK 0x000000f0
360 /* The mask used to clear the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value. */
361 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_CLR_MSK 0xffffff0f
362 /* The reset value of the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field. */
363 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_RESET 0x0
364 /* Extracts the ALT_LWH2F_ID_PERIPH_ID_3_REV_AND field value from a register. */
365 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_GET(value) (((value) & 0x000000f0) >> 4)
366 /* Produces a ALT_LWH2F_ID_PERIPH_ID_3_REV_AND register field value suitable for setting the register. */
367 #define ALT_LWH2F_ID_PERIPH_ID_3_REV_AND_SET(value) (((value) << 4) & 0x000000f0)
368 
369 #ifndef __ASSEMBLY__
370 /*
371  * WARNING: The C register and register group struct declarations are provided for
372  * convenience and illustrative purposes. They should, however, be used with
373  * caution as the C language standard provides no guarantees about the alignment or
374  * atomicity of device memory accesses. The recommended practice for writing
375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
376  * alt_write_word() functions.
377  *
378  * The struct declaration for register ALT_LWH2F_ID_PERIPH_ID_3.
379  */
380 struct ALT_LWH2F_ID_PERIPH_ID_3_s
381 {
382  const uint32_t cust_mod_num : 4; /* Customer Model Number */
383  const uint32_t rev_and : 4; /* Revision */
384  uint32_t : 24; /* *UNDEFINED* */
385 };
386 
387 /* The typedef declaration for register ALT_LWH2F_ID_PERIPH_ID_3. */
388 typedef volatile struct ALT_LWH2F_ID_PERIPH_ID_3_s ALT_LWH2F_ID_PERIPH_ID_3_t;
389 #endif /* __ASSEMBLY__ */
390 
391 /* The byte offset of the ALT_LWH2F_ID_PERIPH_ID_3 register from the beginning of the component. */
392 #define ALT_LWH2F_ID_PERIPH_ID_3_OFST 0xfec
393 
394 /*
395  * Register : Component ID0 Register - comp_id_0
396  *
397  * Component ID0
398  *
399  * Register Layout
400  *
401  * Bits | Access | Reset | Description
402  * :-------|:-------|:------|:------------
403  * [7:0] | R | 0xd | Preamble
404  * [31:8] | ??? | 0x0 | *UNDEFINED*
405  *
406  */
407 /*
408  * Field : Preamble - preamble
409  *
410  * Preamble
411  *
412  * Field Access Macros:
413  *
414  */
415 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */
416 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_LSB 0
417 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */
418 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_MSB 7
419 /* The width in bits of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */
420 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_WIDTH 8
421 /* The mask used to set the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value. */
422 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_SET_MSK 0x000000ff
423 /* The mask used to clear the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value. */
424 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_CLR_MSK 0xffffff00
425 /* The reset value of the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field. */
426 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_RESET 0xd
427 /* Extracts the ALT_LWH2F_ID_COMP_ID_0_PREAMBLE field value from a register. */
428 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
429 /* Produces a ALT_LWH2F_ID_COMP_ID_0_PREAMBLE register field value suitable for setting the register. */
430 #define ALT_LWH2F_ID_COMP_ID_0_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
431 
432 #ifndef __ASSEMBLY__
433 /*
434  * WARNING: The C register and register group struct declarations are provided for
435  * convenience and illustrative purposes. They should, however, be used with
436  * caution as the C language standard provides no guarantees about the alignment or
437  * atomicity of device memory accesses. The recommended practice for writing
438  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
439  * alt_write_word() functions.
440  *
441  * The struct declaration for register ALT_LWH2F_ID_COMP_ID_0.
442  */
443 struct ALT_LWH2F_ID_COMP_ID_0_s
444 {
445  const uint32_t preamble : 8; /* Preamble */
446  uint32_t : 24; /* *UNDEFINED* */
447 };
448 
449 /* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_0. */
450 typedef volatile struct ALT_LWH2F_ID_COMP_ID_0_s ALT_LWH2F_ID_COMP_ID_0_t;
451 #endif /* __ASSEMBLY__ */
452 
453 /* The byte offset of the ALT_LWH2F_ID_COMP_ID_0 register from the beginning of the component. */
454 #define ALT_LWH2F_ID_COMP_ID_0_OFST 0xff0
455 
456 /*
457  * Register : Component ID1 Register - comp_id_1
458  *
459  * Component ID1
460  *
461  * Register Layout
462  *
463  * Bits | Access | Reset | Description
464  * :-------|:-------|:------|:-------------------------------------
465  * [7:0] | R | 0xf0 | Generic IP component class, Preamble
466  * [31:8] | ??? | 0x0 | *UNDEFINED*
467  *
468  */
469 /*
470  * Field : Generic IP component class, Preamble - genipcompcls_preamble
471  *
472  * Generic IP component class, Preamble
473  *
474  * Field Access Macros:
475  *
476  */
477 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
478 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_LSB 0
479 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
480 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_MSB 7
481 /* The width in bits of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
482 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_WIDTH 8
483 /* The mask used to set the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
484 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET_MSK 0x000000ff
485 /* The mask used to clear the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value. */
486 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_CLR_MSK 0xffffff00
487 /* The reset value of the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field. */
488 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_RESET 0xf0
489 /* Extracts the ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE field value from a register. */
490 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
491 /* Produces a ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE register field value suitable for setting the register. */
492 #define ALT_LWH2F_ID_COMP_ID_1_GENIPCOMPCLS_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
493 
494 #ifndef __ASSEMBLY__
495 /*
496  * WARNING: The C register and register group struct declarations are provided for
497  * convenience and illustrative purposes. They should, however, be used with
498  * caution as the C language standard provides no guarantees about the alignment or
499  * atomicity of device memory accesses. The recommended practice for writing
500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
501  * alt_write_word() functions.
502  *
503  * The struct declaration for register ALT_LWH2F_ID_COMP_ID_1.
504  */
505 struct ALT_LWH2F_ID_COMP_ID_1_s
506 {
507  const uint32_t genipcompcls_preamble : 8; /* Generic IP component class, Preamble */
508  uint32_t : 24; /* *UNDEFINED* */
509 };
510 
511 /* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_1. */
512 typedef volatile struct ALT_LWH2F_ID_COMP_ID_1_s ALT_LWH2F_ID_COMP_ID_1_t;
513 #endif /* __ASSEMBLY__ */
514 
515 /* The byte offset of the ALT_LWH2F_ID_COMP_ID_1 register from the beginning of the component. */
516 #define ALT_LWH2F_ID_COMP_ID_1_OFST 0xff4
517 
518 /*
519  * Register : Component ID2 Register - comp_id_2
520  *
521  * Component ID2
522  *
523  * Register Layout
524  *
525  * Bits | Access | Reset | Description
526  * :-------|:-------|:------|:------------
527  * [7:0] | R | 0x5 | Preamble
528  * [31:8] | ??? | 0x0 | *UNDEFINED*
529  *
530  */
531 /*
532  * Field : Preamble - preamble
533  *
534  * Preamble
535  *
536  * Field Access Macros:
537  *
538  */
539 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */
540 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_LSB 0
541 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */
542 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_MSB 7
543 /* The width in bits of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */
544 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_WIDTH 8
545 /* The mask used to set the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value. */
546 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_SET_MSK 0x000000ff
547 /* The mask used to clear the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value. */
548 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_CLR_MSK 0xffffff00
549 /* The reset value of the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field. */
550 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_RESET 0x5
551 /* Extracts the ALT_LWH2F_ID_COMP_ID_2_PREAMBLE field value from a register. */
552 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
553 /* Produces a ALT_LWH2F_ID_COMP_ID_2_PREAMBLE register field value suitable for setting the register. */
554 #define ALT_LWH2F_ID_COMP_ID_2_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
555 
556 #ifndef __ASSEMBLY__
557 /*
558  * WARNING: The C register and register group struct declarations are provided for
559  * convenience and illustrative purposes. They should, however, be used with
560  * caution as the C language standard provides no guarantees about the alignment or
561  * atomicity of device memory accesses. The recommended practice for writing
562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
563  * alt_write_word() functions.
564  *
565  * The struct declaration for register ALT_LWH2F_ID_COMP_ID_2.
566  */
567 struct ALT_LWH2F_ID_COMP_ID_2_s
568 {
569  const uint32_t preamble : 8; /* Preamble */
570  uint32_t : 24; /* *UNDEFINED* */
571 };
572 
573 /* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_2. */
574 typedef volatile struct ALT_LWH2F_ID_COMP_ID_2_s ALT_LWH2F_ID_COMP_ID_2_t;
575 #endif /* __ASSEMBLY__ */
576 
577 /* The byte offset of the ALT_LWH2F_ID_COMP_ID_2 register from the beginning of the component. */
578 #define ALT_LWH2F_ID_COMP_ID_2_OFST 0xff8
579 
580 /*
581  * Register : Component ID3 Register - comp_id_3
582  *
583  * Component ID3
584  *
585  * Register Layout
586  *
587  * Bits | Access | Reset | Description
588  * :-------|:-------|:------|:------------
589  * [7:0] | R | 0xb1 | Preamble
590  * [31:8] | ??? | 0x0 | *UNDEFINED*
591  *
592  */
593 /*
594  * Field : Preamble - preamble
595  *
596  * Preamble
597  *
598  * Field Access Macros:
599  *
600  */
601 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */
602 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_LSB 0
603 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */
604 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_MSB 7
605 /* The width in bits of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */
606 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_WIDTH 8
607 /* The mask used to set the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value. */
608 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_SET_MSK 0x000000ff
609 /* The mask used to clear the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value. */
610 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_CLR_MSK 0xffffff00
611 /* The reset value of the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field. */
612 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_RESET 0xb1
613 /* Extracts the ALT_LWH2F_ID_COMP_ID_3_PREAMBLE field value from a register. */
614 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_GET(value) (((value) & 0x000000ff) >> 0)
615 /* Produces a ALT_LWH2F_ID_COMP_ID_3_PREAMBLE register field value suitable for setting the register. */
616 #define ALT_LWH2F_ID_COMP_ID_3_PREAMBLE_SET(value) (((value) << 0) & 0x000000ff)
617 
618 #ifndef __ASSEMBLY__
619 /*
620  * WARNING: The C register and register group struct declarations are provided for
621  * convenience and illustrative purposes. They should, however, be used with
622  * caution as the C language standard provides no guarantees about the alignment or
623  * atomicity of device memory accesses. The recommended practice for writing
624  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
625  * alt_write_word() functions.
626  *
627  * The struct declaration for register ALT_LWH2F_ID_COMP_ID_3.
628  */
629 struct ALT_LWH2F_ID_COMP_ID_3_s
630 {
631  const uint32_t preamble : 8; /* Preamble */
632  uint32_t : 24; /* *UNDEFINED* */
633 };
634 
635 /* The typedef declaration for register ALT_LWH2F_ID_COMP_ID_3. */
636 typedef volatile struct ALT_LWH2F_ID_COMP_ID_3_s ALT_LWH2F_ID_COMP_ID_3_t;
637 #endif /* __ASSEMBLY__ */
638 
639 /* The byte offset of the ALT_LWH2F_ID_COMP_ID_3 register from the beginning of the component. */
640 #define ALT_LWH2F_ID_COMP_ID_3_OFST 0xffc
641 
642 #ifndef __ASSEMBLY__
643 /*
644  * WARNING: The C register and register group struct declarations are provided for
645  * convenience and illustrative purposes. They should, however, be used with
646  * caution as the C language standard provides no guarantees about the alignment or
647  * atomicity of device memory accesses. The recommended practice for writing
648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
649  * alt_write_word() functions.
650  *
651  * The struct declaration for register group ALT_LWH2F_ID.
652  */
653 struct ALT_LWH2F_ID_s
654 {
655  volatile uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
656  ALT_LWH2F_ID_PERIPH_ID_4_t periph_id_4; /* ALT_LWH2F_ID_PERIPH_ID_4 */
657  volatile uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
658  ALT_LWH2F_ID_PERIPH_ID_0_t periph_id_0; /* ALT_LWH2F_ID_PERIPH_ID_0 */
659  ALT_LWH2F_ID_PERIPH_ID_1_t periph_id_1; /* ALT_LWH2F_ID_PERIPH_ID_1 */
660  ALT_LWH2F_ID_PERIPH_ID_2_t periph_id_2; /* ALT_LWH2F_ID_PERIPH_ID_2 */
661  ALT_LWH2F_ID_PERIPH_ID_3_t periph_id_3; /* ALT_LWH2F_ID_PERIPH_ID_3 */
662  ALT_LWH2F_ID_COMP_ID_0_t comp_id_0; /* ALT_LWH2F_ID_COMP_ID_0 */
663  ALT_LWH2F_ID_COMP_ID_1_t comp_id_1; /* ALT_LWH2F_ID_COMP_ID_1 */
664  ALT_LWH2F_ID_COMP_ID_2_t comp_id_2; /* ALT_LWH2F_ID_COMP_ID_2 */
665  ALT_LWH2F_ID_COMP_ID_3_t comp_id_3; /* ALT_LWH2F_ID_COMP_ID_3 */
666 };
667 
668 /* The typedef declaration for register group ALT_LWH2F_ID. */
669 typedef volatile struct ALT_LWH2F_ID_s ALT_LWH2F_ID_t;
670 /* The struct declaration for the raw register contents of register group ALT_LWH2F_ID. */
671 struct ALT_LWH2F_ID_raw_s
672 {
673  uint32_t _pad_0x0_0xfcf[1012]; /* *UNDEFINED* */
674  volatile uint32_t periph_id_4; /* ALT_LWH2F_ID_PERIPH_ID_4 */
675  uint32_t _pad_0xfd4_0xfdf[3]; /* *UNDEFINED* */
676  volatile uint32_t periph_id_0; /* ALT_LWH2F_ID_PERIPH_ID_0 */
677  volatile uint32_t periph_id_1; /* ALT_LWH2F_ID_PERIPH_ID_1 */
678  volatile uint32_t periph_id_2; /* ALT_LWH2F_ID_PERIPH_ID_2 */
679  volatile uint32_t periph_id_3; /* ALT_LWH2F_ID_PERIPH_ID_3 */
680  volatile uint32_t comp_id_0; /* ALT_LWH2F_ID_COMP_ID_0 */
681  volatile uint32_t comp_id_1; /* ALT_LWH2F_ID_COMP_ID_1 */
682  volatile uint32_t comp_id_2; /* ALT_LWH2F_ID_COMP_ID_2 */
683  volatile uint32_t comp_id_3; /* ALT_LWH2F_ID_COMP_ID_3 */
684 };
685 
686 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_ID. */
687 typedef volatile struct ALT_LWH2F_ID_raw_s ALT_LWH2F_ID_raw_t;
688 #endif /* __ASSEMBLY__ */
689 
690 
691 /*
692  * Register Group : Master Register Group - ALT_LWH2F_MST
693  * Master Register Group
694  *
695  * Registers associated with master interfaces.
696  *
697  */
698 /*
699  * Register Group : FPGA2HPS AXI Bridge Registers - ALT_LWH2F_MST_F2H
700  * FPGA2HPS AXI Bridge Registers
701  *
702  * Registers associated with the FPGA2HPS master interface.
703  *
704  * This master interface provides access to the registers in the FPGA2HPS AXI
705  * Bridge.
706  *
707  */
708 /*
709  * Register : Bus Matrix Issuing Functionality Modification Register - fn_mod_bm_iss
710  *
711  * Sets the issuing capability of the preceding switch arbitration scheme to
712  * multiple or single outstanding transactions.
713  *
714  * Register Layout
715  *
716  * Bits | Access | Reset | Description
717  * :-------|:-------|:------|:---------------------------
718  * [0] | RW | 0x0 | ALT_LWH2F_FN_MOD_BM_ISS_RD
719  * [1] | RW | 0x0 | ALT_LWH2F_FN_MOD_BM_ISS_WR
720  * [31:2] | ??? | 0x0 | *UNDEFINED*
721  *
722  */
723 /*
724  * Field : rd
725  *
726  * Field Enumeration Values:
727  *
728  * Enum | Value | Description
729  * :------------------------------------|:------|:-------------------------------------------
730  * ALT_LWH2F_FN_MOD_BM_ISS_RD_E_MULT | 0x0 | Multiple outstanding read transactions
731  * ALT_LWH2F_FN_MOD_BM_ISS_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
732  *
733  * Field Access Macros:
734  *
735  */
736 /*
737  * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_RD
738  *
739  * Multiple outstanding read transactions
740  */
741 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_E_MULT 0x0
742 /*
743  * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_RD
744  *
745  * Only a single outstanding read transaction
746  */
747 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_E_SINGLE 0x1
748 
749 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */
750 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_LSB 0
751 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */
752 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_MSB 0
753 /* The width in bits of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */
754 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_WIDTH 1
755 /* The mask used to set the ALT_LWH2F_FN_MOD_BM_ISS_RD register field value. */
756 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_SET_MSK 0x00000001
757 /* The mask used to clear the ALT_LWH2F_FN_MOD_BM_ISS_RD register field value. */
758 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_CLR_MSK 0xfffffffe
759 /* The reset value of the ALT_LWH2F_FN_MOD_BM_ISS_RD register field. */
760 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_RESET 0x0
761 /* Extracts the ALT_LWH2F_FN_MOD_BM_ISS_RD field value from a register. */
762 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_GET(value) (((value) & 0x00000001) >> 0)
763 /* Produces a ALT_LWH2F_FN_MOD_BM_ISS_RD register field value suitable for setting the register. */
764 #define ALT_LWH2F_FN_MOD_BM_ISS_RD_SET(value) (((value) << 0) & 0x00000001)
765 
766 /*
767  * Field : wr
768  *
769  * Field Enumeration Values:
770  *
771  * Enum | Value | Description
772  * :------------------------------------|:------|:--------------------------------------------
773  * ALT_LWH2F_FN_MOD_BM_ISS_WR_E_MULT | 0x0 | Multiple outstanding write transactions
774  * ALT_LWH2F_FN_MOD_BM_ISS_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
775  *
776  * Field Access Macros:
777  *
778  */
779 /*
780  * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_WR
781  *
782  * Multiple outstanding write transactions
783  */
784 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_E_MULT 0x0
785 /*
786  * Enumerated value for register field ALT_LWH2F_FN_MOD_BM_ISS_WR
787  *
788  * Only a single outstanding write transaction
789  */
790 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_E_SINGLE 0x1
791 
792 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */
793 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_LSB 1
794 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */
795 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_MSB 1
796 /* The width in bits of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */
797 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_WIDTH 1
798 /* The mask used to set the ALT_LWH2F_FN_MOD_BM_ISS_WR register field value. */
799 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_SET_MSK 0x00000002
800 /* The mask used to clear the ALT_LWH2F_FN_MOD_BM_ISS_WR register field value. */
801 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_CLR_MSK 0xfffffffd
802 /* The reset value of the ALT_LWH2F_FN_MOD_BM_ISS_WR register field. */
803 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_RESET 0x0
804 /* Extracts the ALT_LWH2F_FN_MOD_BM_ISS_WR field value from a register. */
805 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_GET(value) (((value) & 0x00000002) >> 1)
806 /* Produces a ALT_LWH2F_FN_MOD_BM_ISS_WR register field value suitable for setting the register. */
807 #define ALT_LWH2F_FN_MOD_BM_ISS_WR_SET(value) (((value) << 1) & 0x00000002)
808 
809 #ifndef __ASSEMBLY__
810 /*
811  * WARNING: The C register and register group struct declarations are provided for
812  * convenience and illustrative purposes. They should, however, be used with
813  * caution as the C language standard provides no guarantees about the alignment or
814  * atomicity of device memory accesses. The recommended practice for writing
815  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
816  * alt_write_word() functions.
817  *
818  * The struct declaration for register ALT_LWH2F_FN_MOD_BM_ISS.
819  */
820 struct ALT_LWH2F_FN_MOD_BM_ISS_s
821 {
822  uint32_t rd : 1; /* ALT_LWH2F_FN_MOD_BM_ISS_RD */
823  uint32_t wr : 1; /* ALT_LWH2F_FN_MOD_BM_ISS_WR */
824  uint32_t : 30; /* *UNDEFINED* */
825 };
826 
827 /* The typedef declaration for register ALT_LWH2F_FN_MOD_BM_ISS. */
828 typedef volatile struct ALT_LWH2F_FN_MOD_BM_ISS_s ALT_LWH2F_FN_MOD_BM_ISS_t;
829 #endif /* __ASSEMBLY__ */
830 
831 /* The byte offset of the ALT_LWH2F_FN_MOD_BM_ISS register from the beginning of the component. */
832 #define ALT_LWH2F_FN_MOD_BM_ISS_OFST 0x8
833 /* The address of the ALT_LWH2F_FN_MOD_BM_ISS register. */
834 #define ALT_LWH2F_FN_MOD_BM_ISS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_FN_MOD_BM_ISS_OFST))
835 
836 /*
837  * Register : AHB Control Register - ahb_cntl
838  *
839  * Sets the block issuing capability to one outstanding transaction.
840  *
841  * Register Layout
842  *
843  * Bits | Access | Reset | Description
844  * :-------|:-------|:------|:------------------------------
845  * [0] | RW | 0x0 | ALT_LWH2F_AHB_CNTL_DECERR_EN
846  * [1] | RW | 0x0 | ALT_LWH2F_AHB_CNTL_FORCE_INCR
847  * [31:2] | ??? | 0x0 | *UNDEFINED*
848  *
849  */
850 /*
851  * Field : decerr_en
852  *
853  * Field Enumeration Values:
854  *
855  * Enum | Value | Description
856  * :-----------------------------------|:------|:-------------------------------------------------
857  * ALT_LWH2F_AHB_CNTL_DECERR_EN_E_DIS | 0x0 | No DECERR response.
858  * ALT_LWH2F_AHB_CNTL_DECERR_EN_E_EN | 0x1 | If the AHB protocol conversion function receives
859  * : | | an unaligned address or a write data beat
860  * : | | without all the byte strobes set, creates a
861  * : | | DECERR response.
862  *
863  * Field Access Macros:
864  *
865  */
866 /*
867  * Enumerated value for register field ALT_LWH2F_AHB_CNTL_DECERR_EN
868  *
869  * No DECERR response.
870  */
871 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_E_DIS 0x0
872 /*
873  * Enumerated value for register field ALT_LWH2F_AHB_CNTL_DECERR_EN
874  *
875  * If the AHB protocol conversion function receives an unaligned address or a write
876  * data beat without all the byte strobes set, creates a DECERR response.
877  */
878 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_E_EN 0x1
879 
880 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */
881 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_LSB 0
882 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */
883 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_MSB 0
884 /* The width in bits of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */
885 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_WIDTH 1
886 /* The mask used to set the ALT_LWH2F_AHB_CNTL_DECERR_EN register field value. */
887 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_SET_MSK 0x00000001
888 /* The mask used to clear the ALT_LWH2F_AHB_CNTL_DECERR_EN register field value. */
889 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_CLR_MSK 0xfffffffe
890 /* The reset value of the ALT_LWH2F_AHB_CNTL_DECERR_EN register field. */
891 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_RESET 0x0
892 /* Extracts the ALT_LWH2F_AHB_CNTL_DECERR_EN field value from a register. */
893 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_GET(value) (((value) & 0x00000001) >> 0)
894 /* Produces a ALT_LWH2F_AHB_CNTL_DECERR_EN register field value suitable for setting the register. */
895 #define ALT_LWH2F_AHB_CNTL_DECERR_EN_SET(value) (((value) << 0) & 0x00000001)
896 
897 /*
898  * Field : force_incr
899  *
900  * Field Enumeration Values:
901  *
902  * Enum | Value | Description
903  * :------------------------------------|:------|:-------------------------------------------------
904  * ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_DIS | 0x0 | Multiple outstanding write transactions
905  * ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_EN | 0x1 | If a beat is received that has no write data
906  * : | | strobes set, that write data beat is replaced
907  * : | | with an IDLE beat. Also, causes all transactions
908  * : | | that are to be output to the AHB domain to be an
909  * : | | undefined length INCR.
910  *
911  * Field Access Macros:
912  *
913  */
914 /*
915  * Enumerated value for register field ALT_LWH2F_AHB_CNTL_FORCE_INCR
916  *
917  * Multiple outstanding write transactions
918  */
919 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_DIS 0x0
920 /*
921  * Enumerated value for register field ALT_LWH2F_AHB_CNTL_FORCE_INCR
922  *
923  * If a beat is received that has no write data strobes set, that write data beat
924  * is replaced with an IDLE beat. Also, causes all transactions that are to be
925  * output to the AHB domain to be an undefined length INCR.
926  */
927 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_E_EN 0x1
928 
929 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */
930 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_LSB 1
931 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */
932 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_MSB 1
933 /* The width in bits of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */
934 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_WIDTH 1
935 /* The mask used to set the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value. */
936 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_SET_MSK 0x00000002
937 /* The mask used to clear the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value. */
938 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_CLR_MSK 0xfffffffd
939 /* The reset value of the ALT_LWH2F_AHB_CNTL_FORCE_INCR register field. */
940 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_RESET 0x0
941 /* Extracts the ALT_LWH2F_AHB_CNTL_FORCE_INCR field value from a register. */
942 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_GET(value) (((value) & 0x00000002) >> 1)
943 /* Produces a ALT_LWH2F_AHB_CNTL_FORCE_INCR register field value suitable for setting the register. */
944 #define ALT_LWH2F_AHB_CNTL_FORCE_INCR_SET(value) (((value) << 1) & 0x00000002)
945 
946 #ifndef __ASSEMBLY__
947 /*
948  * WARNING: The C register and register group struct declarations are provided for
949  * convenience and illustrative purposes. They should, however, be used with
950  * caution as the C language standard provides no guarantees about the alignment or
951  * atomicity of device memory accesses. The recommended practice for writing
952  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
953  * alt_write_word() functions.
954  *
955  * The struct declaration for register ALT_LWH2F_AHB_CNTL.
956  */
957 struct ALT_LWH2F_AHB_CNTL_s
958 {
959  uint32_t decerr_en : 1; /* ALT_LWH2F_AHB_CNTL_DECERR_EN */
960  uint32_t force_incr : 1; /* ALT_LWH2F_AHB_CNTL_FORCE_INCR */
961  uint32_t : 30; /* *UNDEFINED* */
962 };
963 
964 /* The typedef declaration for register ALT_LWH2F_AHB_CNTL. */
965 typedef volatile struct ALT_LWH2F_AHB_CNTL_s ALT_LWH2F_AHB_CNTL_t;
966 #endif /* __ASSEMBLY__ */
967 
968 /* The byte offset of the ALT_LWH2F_AHB_CNTL register from the beginning of the component. */
969 #define ALT_LWH2F_AHB_CNTL_OFST 0x44
970 /* The address of the ALT_LWH2F_AHB_CNTL register. */
971 #define ALT_LWH2F_AHB_CNTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_AHB_CNTL_OFST))
972 
973 #ifndef __ASSEMBLY__
974 /*
975  * WARNING: The C register and register group struct declarations are provided for
976  * convenience and illustrative purposes. They should, however, be used with
977  * caution as the C language standard provides no guarantees about the alignment or
978  * atomicity of device memory accesses. The recommended practice for writing
979  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
980  * alt_write_word() functions.
981  *
982  * The struct declaration for register group ALT_LWH2F_MST_F2H.
983  */
984 struct ALT_LWH2F_MST_F2H_s
985 {
986  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
987  ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
988  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
989  ALT_LWH2F_AHB_CNTL_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */
990 };
991 
992 /* The typedef declaration for register group ALT_LWH2F_MST_F2H. */
993 typedef volatile struct ALT_LWH2F_MST_F2H_s ALT_LWH2F_MST_F2H_t;
994 /* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_F2H. */
995 struct ALT_LWH2F_MST_F2H_raw_s
996 {
997  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
998  volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
999  uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
1000  volatile uint32_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */
1001 };
1002 
1003 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_F2H. */
1004 typedef volatile struct ALT_LWH2F_MST_F2H_raw_s ALT_LWH2F_MST_F2H_raw_t;
1005 #endif /* __ASSEMBLY__ */
1006 
1007 
1008 /*
1009  * Register Group : HPS2FPGA AXI Bridge Registers - ALT_LWH2F_MST_H2F
1010  * HPS2FPGA AXI Bridge Registers
1011  *
1012  * Registers associated with the HPS2FPGA master interface.
1013  *
1014  * This master interface provides access to the registers in the HPS2FPGA AXI
1015  * Bridge.
1016  *
1017  */
1018 #ifndef __ASSEMBLY__
1019 /*
1020  * WARNING: The C register and register group struct declarations are provided for
1021  * convenience and illustrative purposes. They should, however, be used with
1022  * caution as the C language standard provides no guarantees about the alignment or
1023  * atomicity of device memory accesses. The recommended practice for writing
1024  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1025  * alt_write_word() functions.
1026  *
1027  * The struct declaration for register group ALT_LWH2F_MST_H2F.
1028  */
1029 struct ALT_LWH2F_MST_H2F_s
1030 {
1031  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
1032  ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
1033  volatile uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
1034  ALT_LWH2F_AHB_CNTL_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */
1035 };
1036 
1037 /* The typedef declaration for register group ALT_LWH2F_MST_H2F. */
1038 typedef volatile struct ALT_LWH2F_MST_H2F_s ALT_LWH2F_MST_H2F_t;
1039 /* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_H2F. */
1040 struct ALT_LWH2F_MST_H2F_raw_s
1041 {
1042  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
1043  volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
1044  uint32_t _pad_0xc_0x43[14]; /* *UNDEFINED* */
1045  volatile uint32_t ahb_cntl; /* ALT_LWH2F_AHB_CNTL */
1046 };
1047 
1048 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_H2F. */
1049 typedef volatile struct ALT_LWH2F_MST_H2F_raw_s ALT_LWH2F_MST_H2F_raw_t;
1050 #endif /* __ASSEMBLY__ */
1051 
1052 
1053 /*
1054  * Register Group : 32-bit Master - ALT_LWH2F_MST_B32
1055  * 32-bit Master
1056  *
1057  * Registers associated with the 32-bit AXI master interface. This master provides
1058  * access to slaves in the FPGA.
1059  *
1060  */
1061 /*
1062  * Register : Write Tidemark - wr_tidemark
1063  *
1064  * Controls the release of the transaction in the write data FIFO.
1065  *
1066  * Register Layout
1067  *
1068  * Bits | Access | Reset | Description
1069  * :-------|:-------|:------|:------------
1070  * [3:0] | RW | 0x4 | Level
1071  * [31:4] | ??? | 0x0 | *UNDEFINED*
1072  *
1073  */
1074 /*
1075  * Field : Level - level
1076  *
1077  * Stalls the transaction in the write data FIFO until the number of occupied slots
1078  * in the write data FIFO exceeds the level. Note that the transaction is released
1079  * before this level is achieved if the network receives the WLAST beat or the
1080  * write FIFO becomes full.
1081  *
1082  * Field Access Macros:
1083  *
1084  */
1085 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */
1086 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_LSB 0
1087 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */
1088 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_MSB 3
1089 /* The width in bits of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */
1090 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_WIDTH 4
1091 /* The mask used to set the ALT_LWH2F_WR_TIDEMARK_LEVEL register field value. */
1092 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_SET_MSK 0x0000000f
1093 /* The mask used to clear the ALT_LWH2F_WR_TIDEMARK_LEVEL register field value. */
1094 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_CLR_MSK 0xfffffff0
1095 /* The reset value of the ALT_LWH2F_WR_TIDEMARK_LEVEL register field. */
1096 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_RESET 0x4
1097 /* Extracts the ALT_LWH2F_WR_TIDEMARK_LEVEL field value from a register. */
1098 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
1099 /* Produces a ALT_LWH2F_WR_TIDEMARK_LEVEL register field value suitable for setting the register. */
1100 #define ALT_LWH2F_WR_TIDEMARK_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
1101 
1102 #ifndef __ASSEMBLY__
1103 /*
1104  * WARNING: The C register and register group struct declarations are provided for
1105  * convenience and illustrative purposes. They should, however, be used with
1106  * caution as the C language standard provides no guarantees about the alignment or
1107  * atomicity of device memory accesses. The recommended practice for writing
1108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1109  * alt_write_word() functions.
1110  *
1111  * The struct declaration for register ALT_LWH2F_WR_TIDEMARK.
1112  */
1113 struct ALT_LWH2F_WR_TIDEMARK_s
1114 {
1115  uint32_t level : 4; /* Level */
1116  uint32_t : 28; /* *UNDEFINED* */
1117 };
1118 
1119 /* The typedef declaration for register ALT_LWH2F_WR_TIDEMARK. */
1120 typedef volatile struct ALT_LWH2F_WR_TIDEMARK_s ALT_LWH2F_WR_TIDEMARK_t;
1121 #endif /* __ASSEMBLY__ */
1122 
1123 /* The byte offset of the ALT_LWH2F_WR_TIDEMARK register from the beginning of the component. */
1124 #define ALT_LWH2F_WR_TIDEMARK_OFST 0x40
1125 /* The address of the ALT_LWH2F_WR_TIDEMARK register. */
1126 #define ALT_LWH2F_WR_TIDEMARK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_WR_TIDEMARK_OFST))
1127 
1128 /*
1129  * Register : Issuing Functionality Modification Register - fn_mod
1130  *
1131  * Sets the block issuing capability to multiple or single outstanding
1132  * transactions.
1133  *
1134  * Register Layout
1135  *
1136  * Bits | Access | Reset | Description
1137  * :-------|:-------|:------|:--------------------
1138  * [0] | RW | 0x0 | ALT_LWH2F_FN_MOD_RD
1139  * [1] | RW | 0x0 | ALT_LWH2F_FN_MOD_WR
1140  * [31:2] | ??? | 0x0 | *UNDEFINED*
1141  *
1142  */
1143 /*
1144  * Field : rd
1145  *
1146  * Field Enumeration Values:
1147  *
1148  * Enum | Value | Description
1149  * :-----------------------------|:------|:-------------------------------------------
1150  * ALT_LWH2F_FN_MOD_RD_E_MULT | 0x0 | Multiple outstanding read transactions
1151  * ALT_LWH2F_FN_MOD_RD_E_SINGLE | 0x1 | Only a single outstanding read transaction
1152  *
1153  * Field Access Macros:
1154  *
1155  */
1156 /*
1157  * Enumerated value for register field ALT_LWH2F_FN_MOD_RD
1158  *
1159  * Multiple outstanding read transactions
1160  */
1161 #define ALT_LWH2F_FN_MOD_RD_E_MULT 0x0
1162 /*
1163  * Enumerated value for register field ALT_LWH2F_FN_MOD_RD
1164  *
1165  * Only a single outstanding read transaction
1166  */
1167 #define ALT_LWH2F_FN_MOD_RD_E_SINGLE 0x1
1168 
1169 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_RD register field. */
1170 #define ALT_LWH2F_FN_MOD_RD_LSB 0
1171 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_RD register field. */
1172 #define ALT_LWH2F_FN_MOD_RD_MSB 0
1173 /* The width in bits of the ALT_LWH2F_FN_MOD_RD register field. */
1174 #define ALT_LWH2F_FN_MOD_RD_WIDTH 1
1175 /* The mask used to set the ALT_LWH2F_FN_MOD_RD register field value. */
1176 #define ALT_LWH2F_FN_MOD_RD_SET_MSK 0x00000001
1177 /* The mask used to clear the ALT_LWH2F_FN_MOD_RD register field value. */
1178 #define ALT_LWH2F_FN_MOD_RD_CLR_MSK 0xfffffffe
1179 /* The reset value of the ALT_LWH2F_FN_MOD_RD register field. */
1180 #define ALT_LWH2F_FN_MOD_RD_RESET 0x0
1181 /* Extracts the ALT_LWH2F_FN_MOD_RD field value from a register. */
1182 #define ALT_LWH2F_FN_MOD_RD_GET(value) (((value) & 0x00000001) >> 0)
1183 /* Produces a ALT_LWH2F_FN_MOD_RD register field value suitable for setting the register. */
1184 #define ALT_LWH2F_FN_MOD_RD_SET(value) (((value) << 0) & 0x00000001)
1185 
1186 /*
1187  * Field : wr
1188  *
1189  * Field Enumeration Values:
1190  *
1191  * Enum | Value | Description
1192  * :-----------------------------|:------|:--------------------------------------------
1193  * ALT_LWH2F_FN_MOD_WR_E_MULT | 0x0 | Multiple outstanding write transactions
1194  * ALT_LWH2F_FN_MOD_WR_E_SINGLE | 0x1 | Only a single outstanding write transaction
1195  *
1196  * Field Access Macros:
1197  *
1198  */
1199 /*
1200  * Enumerated value for register field ALT_LWH2F_FN_MOD_WR
1201  *
1202  * Multiple outstanding write transactions
1203  */
1204 #define ALT_LWH2F_FN_MOD_WR_E_MULT 0x0
1205 /*
1206  * Enumerated value for register field ALT_LWH2F_FN_MOD_WR
1207  *
1208  * Only a single outstanding write transaction
1209  */
1210 #define ALT_LWH2F_FN_MOD_WR_E_SINGLE 0x1
1211 
1212 /* The Least Significant Bit (LSB) position of the ALT_LWH2F_FN_MOD_WR register field. */
1213 #define ALT_LWH2F_FN_MOD_WR_LSB 1
1214 /* The Most Significant Bit (MSB) position of the ALT_LWH2F_FN_MOD_WR register field. */
1215 #define ALT_LWH2F_FN_MOD_WR_MSB 1
1216 /* The width in bits of the ALT_LWH2F_FN_MOD_WR register field. */
1217 #define ALT_LWH2F_FN_MOD_WR_WIDTH 1
1218 /* The mask used to set the ALT_LWH2F_FN_MOD_WR register field value. */
1219 #define ALT_LWH2F_FN_MOD_WR_SET_MSK 0x00000002
1220 /* The mask used to clear the ALT_LWH2F_FN_MOD_WR register field value. */
1221 #define ALT_LWH2F_FN_MOD_WR_CLR_MSK 0xfffffffd
1222 /* The reset value of the ALT_LWH2F_FN_MOD_WR register field. */
1223 #define ALT_LWH2F_FN_MOD_WR_RESET 0x0
1224 /* Extracts the ALT_LWH2F_FN_MOD_WR field value from a register. */
1225 #define ALT_LWH2F_FN_MOD_WR_GET(value) (((value) & 0x00000002) >> 1)
1226 /* Produces a ALT_LWH2F_FN_MOD_WR register field value suitable for setting the register. */
1227 #define ALT_LWH2F_FN_MOD_WR_SET(value) (((value) << 1) & 0x00000002)
1228 
1229 #ifndef __ASSEMBLY__
1230 /*
1231  * WARNING: The C register and register group struct declarations are provided for
1232  * convenience and illustrative purposes. They should, however, be used with
1233  * caution as the C language standard provides no guarantees about the alignment or
1234  * atomicity of device memory accesses. The recommended practice for writing
1235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1236  * alt_write_word() functions.
1237  *
1238  * The struct declaration for register ALT_LWH2F_FN_MOD.
1239  */
1240 struct ALT_LWH2F_FN_MOD_s
1241 {
1242  uint32_t rd : 1; /* ALT_LWH2F_FN_MOD_RD */
1243  uint32_t wr : 1; /* ALT_LWH2F_FN_MOD_WR */
1244  uint32_t : 30; /* *UNDEFINED* */
1245 };
1246 
1247 /* The typedef declaration for register ALT_LWH2F_FN_MOD. */
1248 typedef volatile struct ALT_LWH2F_FN_MOD_s ALT_LWH2F_FN_MOD_t;
1249 #endif /* __ASSEMBLY__ */
1250 
1251 /* The byte offset of the ALT_LWH2F_FN_MOD register from the beginning of the component. */
1252 #define ALT_LWH2F_FN_MOD_OFST 0x108
1253 /* The address of the ALT_LWH2F_FN_MOD register. */
1254 #define ALT_LWH2F_FN_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_LWH2F_FN_MOD_OFST))
1255 
1256 #ifndef __ASSEMBLY__
1257 /*
1258  * WARNING: The C register and register group struct declarations are provided for
1259  * convenience and illustrative purposes. They should, however, be used with
1260  * caution as the C language standard provides no guarantees about the alignment or
1261  * atomicity of device memory accesses. The recommended practice for writing
1262  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1263  * alt_write_word() functions.
1264  *
1265  * The struct declaration for register group ALT_LWH2F_MST_B32.
1266  */
1267 struct ALT_LWH2F_MST_B32_s
1268 {
1269  volatile uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
1270  ALT_LWH2F_FN_MOD_BM_ISS_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
1271  volatile uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
1272  ALT_LWH2F_WR_TIDEMARK_t wr_tidemark; /* ALT_LWH2F_WR_TIDEMARK */
1273  volatile uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
1274  ALT_LWH2F_FN_MOD_t fn_mod; /* ALT_LWH2F_FN_MOD */
1275 };
1276 
1277 /* The typedef declaration for register group ALT_LWH2F_MST_B32. */
1278 typedef volatile struct ALT_LWH2F_MST_B32_s ALT_LWH2F_MST_B32_t;
1279 /* The struct declaration for the raw register contents of register group ALT_LWH2F_MST_B32. */
1280 struct ALT_LWH2F_MST_B32_raw_s
1281 {
1282  uint32_t _pad_0x0_0x7[2]; /* *UNDEFINED* */
1283  volatile uint32_t fn_mod_bm_iss; /* ALT_LWH2F_FN_MOD_BM_ISS */
1284  uint32_t _pad_0xc_0x3f[13]; /* *UNDEFINED* */
1285  volatile uint32_t wr_tidemark; /* ALT_LWH2F_WR_TIDEMARK */
1286  uint32_t _pad_0x44_0x107[49]; /* *UNDEFINED* */
1287  volatile uint32_t fn_mod; /* ALT_LWH2F_FN_MOD */
1288 };
1289 
1290 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST_B32. */
1291 typedef volatile struct ALT_LWH2F_MST_B32_raw_s ALT_LWH2F_MST_B32_raw_t;
1292 #endif /* __ASSEMBLY__ */
1293 
1294 
1295 #ifndef __ASSEMBLY__
1296 /*
1297  * WARNING: The C register and register group struct declarations are provided for
1298  * convenience and illustrative purposes. They should, however, be used with
1299  * caution as the C language standard provides no guarantees about the alignment or
1300  * atomicity of device memory accesses. The recommended practice for writing
1301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1302  * alt_write_word() functions.
1303  *
1304  * The struct declaration for register group ALT_LWH2F_MST.
1305  */
1306 struct ALT_LWH2F_MST_s
1307 {
1308  ALT_LWH2F_MST_F2H_t mastergrp_fpga2hpsregs; /* ALT_LWH2F_MST_F2H */
1309  volatile uint32_t _pad_0x48_0xfff[1006]; /* *UNDEFINED* */
1310  ALT_LWH2F_MST_H2F_t mastergrp_hps2fpgaregs; /* ALT_LWH2F_MST_H2F */
1311  volatile uint32_t _pad_0x1048_0x2fff[2030]; /* *UNDEFINED* */
1312  ALT_LWH2F_MST_B32_t mastergrp_b32; /* ALT_LWH2F_MST_B32 */
1313 };
1314 
1315 /* The typedef declaration for register group ALT_LWH2F_MST. */
1316 typedef volatile struct ALT_LWH2F_MST_s ALT_LWH2F_MST_t;
1317 /* The struct declaration for the raw register contents of register group ALT_LWH2F_MST. */
1318 struct ALT_LWH2F_MST_raw_s
1319 {
1320  ALT_LWH2F_MST_F2H_raw_t mastergrp_fpga2hpsregs; /* ALT_LWH2F_MST_F2H */
1321  uint32_t _pad_0x48_0xfff[1006]; /* *UNDEFINED* */
1322  ALT_LWH2F_MST_H2F_raw_t mastergrp_hps2fpgaregs; /* ALT_LWH2F_MST_H2F */
1323  uint32_t _pad_0x1048_0x2fff[2030]; /* *UNDEFINED* */
1324  ALT_LWH2F_MST_B32_raw_t mastergrp_b32; /* ALT_LWH2F_MST_B32 */
1325 };
1326 
1327 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_MST. */
1328 typedef volatile struct ALT_LWH2F_MST_raw_s ALT_LWH2F_MST_raw_t;
1329 #endif /* __ASSEMBLY__ */
1330 
1331 
1332 /*
1333  * Register Group : Slave Register Group - ALT_LWH2F_SLV
1334  * Slave Register Group
1335  *
1336  * Registers associated with slave interfaces.
1337  *
1338  */
1339 /*
1340  * Register Group : L3 Slave Register Group - ALT_LWH2F_SLV_B32
1341  * L3 Slave Register Group
1342  *
1343  * Registers associated with the 32-bit AXI slave interface. This slave connects to
1344  * the L3 Interconnect.
1345  *
1346  */
1347 #ifndef __ASSEMBLY__
1348 /*
1349  * WARNING: The C register and register group struct declarations are provided for
1350  * convenience and illustrative purposes. They should, however, be used with
1351  * caution as the C language standard provides no guarantees about the alignment or
1352  * atomicity of device memory accesses. The recommended practice for writing
1353  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1354  * alt_write_word() functions.
1355  *
1356  * The struct declaration for register group ALT_LWH2F_SLV_B32.
1357  */
1358 struct ALT_LWH2F_SLV_B32_s
1359 {
1360  volatile uint32_t _pad_0x0_0x107[66]; /* *UNDEFINED* */
1361  ALT_LWH2F_FN_MOD_t fn_mod; /* ALT_LWH2F_FN_MOD */
1362 };
1363 
1364 /* The typedef declaration for register group ALT_LWH2F_SLV_B32. */
1365 typedef volatile struct ALT_LWH2F_SLV_B32_s ALT_LWH2F_SLV_B32_t;
1366 /* The struct declaration for the raw register contents of register group ALT_LWH2F_SLV_B32. */
1367 struct ALT_LWH2F_SLV_B32_raw_s
1368 {
1369  uint32_t _pad_0x0_0x107[66]; /* *UNDEFINED* */
1370  volatile uint32_t fn_mod; /* ALT_LWH2F_FN_MOD */
1371 };
1372 
1373 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_SLV_B32. */
1374 typedef volatile struct ALT_LWH2F_SLV_B32_raw_s ALT_LWH2F_SLV_B32_raw_t;
1375 #endif /* __ASSEMBLY__ */
1376 
1377 
1378 #ifndef __ASSEMBLY__
1379 /*
1380  * WARNING: The C register and register group struct declarations are provided for
1381  * convenience and illustrative purposes. They should, however, be used with
1382  * caution as the C language standard provides no guarantees about the alignment or
1383  * atomicity of device memory accesses. The recommended practice for writing
1384  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1385  * alt_write_word() functions.
1386  *
1387  * The struct declaration for register group ALT_LWH2F_SLV.
1388  */
1389 struct ALT_LWH2F_SLV_s
1390 {
1391  volatile uint32_t _pad_0x0_0x2fff[3072]; /* *UNDEFINED* */
1392  ALT_LWH2F_SLV_B32_t slavegrp_b32; /* ALT_LWH2F_SLV_B32 */
1393 };
1394 
1395 /* The typedef declaration for register group ALT_LWH2F_SLV. */
1396 typedef volatile struct ALT_LWH2F_SLV_s ALT_LWH2F_SLV_t;
1397 /* The struct declaration for the raw register contents of register group ALT_LWH2F_SLV. */
1398 struct ALT_LWH2F_SLV_raw_s
1399 {
1400  uint32_t _pad_0x0_0x2fff[3072]; /* *UNDEFINED* */
1401  ALT_LWH2F_SLV_B32_raw_t slavegrp_b32; /* ALT_LWH2F_SLV_B32 */
1402 };
1403 
1404 /* The typedef declaration for the raw register contents of register group ALT_LWH2F_SLV. */
1405 typedef volatile struct ALT_LWH2F_SLV_raw_s ALT_LWH2F_SLV_raw_t;
1406 #endif /* __ASSEMBLY__ */
1407 
1408 
1409 #ifndef __ASSEMBLY__
1410 /*
1411  * WARNING: The C register and register group struct declarations are provided for
1412  * convenience and illustrative purposes. They should, however, be used with
1413  * caution as the C language standard provides no guarantees about the alignment or
1414  * atomicity of device memory accesses. The recommended practice for writing
1415  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1416  * alt_write_word() functions.
1417  *
1418  * The struct declaration for register group ALT_LWH2F.
1419  */
1420 struct ALT_LWH2F_s
1421 {
1422  volatile uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */
1423  ALT_LWH2F_ID_t idgrp; /* ALT_LWH2F_ID */
1424  ALT_LWH2F_MST_t mastergrp; /* ALT_LWH2F_MST */
1425  volatile uint32_t _pad_0x510c_0x41fff[62397]; /* *UNDEFINED* */
1426  ALT_LWH2F_SLV_t slavegrp; /* ALT_LWH2F_SLV */
1427  volatile uint32_t _pad_0x4510c_0x80000[60349]; /* *UNDEFINED* */
1428 };
1429 
1430 /* The typedef declaration for register group ALT_LWH2F. */
1431 typedef volatile struct ALT_LWH2F_s ALT_LWH2F_t;
1432 /* The struct declaration for the raw register contents of register group ALT_LWH2F. */
1433 struct ALT_LWH2F_raw_s
1434 {
1435  uint32_t _pad_0x0_0xfff[1024]; /* *UNDEFINED* */
1436  ALT_LWH2F_ID_raw_t idgrp; /* ALT_LWH2F_ID */
1437  ALT_LWH2F_MST_raw_t mastergrp; /* ALT_LWH2F_MST */
1438  uint32_t _pad_0x510c_0x41fff[62397]; /* *UNDEFINED* */
1439  ALT_LWH2F_SLV_raw_t slavegrp; /* ALT_LWH2F_SLV */
1440  uint32_t _pad_0x4510c_0x80000[60349]; /* *UNDEFINED* */
1441 };
1442 
1443 /* The typedef declaration for the raw register contents of register group ALT_LWH2F. */
1444 typedef volatile struct ALT_LWH2F_raw_s ALT_LWH2F_raw_t;
1445 #endif /* __ASSEMBLY__ */
1446 
1447 
1448 #ifdef __cplusplus
1449 }
1450 #endif /* __cplusplus */
1451 #endif /* __ALTERA_ALT_LWH2F_H__ */
1452