Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_gpio.h
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32 
33 /* Altera - ALT_GPIO */
34 
35 #ifndef __ALT_SOCAL_GPIO_H__
36 #define __ALT_SOCAL_GPIO_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_GPIO
50  *
51  */
52 /*
53  * Register : gpio_swporta_dr
54  *
55  * Name: Port A data register
56  *
57  * set_attribute $reg -attr RALAttribute -sub NO_BIT_BASH_TEST -value 1
58  *
59  * Size: 1-32 bits
60  *
61  * Address Offset: 0x00
62  *
63  * Read/Write Access: Read/Write
64  *
65  * Register Layout
66  *
67  * Bits | Access | Reset | Description
68  * :--------|:-------|:------|:------------------------------------
69  * [23:0] | RW | 0x0 | ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR
70  * [31:24] | ??? | 0x0 | *UNDEFINED*
71  *
72  */
73 /*
74  * Field : gpio_swporta_dr
75  *
76  * Values written to this register are output on the I/O signals
77  *
78  * for Port A if the corresponding data direction bits for Port A
79  *
80  * are set to Output mode and the corresponding control bit for
81  *
82  * Port A is set to Software mode. The value read back is equal
83  *
84  * to the last value written to this register.
85  *
86  * Field Access Macros:
87  *
88  */
89 /* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
90 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0
91 /* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
92 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 23
93 /* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
94 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 24
95 /* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
96 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x00ffffff
97 /* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
98 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xff000000
99 /* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
100 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0
101 /* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
102 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x00ffffff) >> 0)
103 /* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
104 #define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x00ffffff)
105 
106 #ifndef __ASSEMBLY__
107 /*
108  * WARNING: The C register and register group struct declarations are provided for
109  * convenience and illustrative purposes. They should, however, be used with
110  * caution as the C language standard provides no guarantees about the alignment or
111  * atomicity of device memory accesses. The recommended practice for writing
112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
113  * alt_write_word() functions.
114  *
115  * The struct declaration for register ALT_GPIO_SWPORTA_DR.
116  */
117 struct ALT_GPIO_SWPORTA_DR_s
118 {
119  uint32_t gpio_swporta_dr : 24; /* ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR */
120  uint32_t : 8; /* *UNDEFINED* */
121 };
122 
123 /* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */
124 typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t;
125 #endif /* __ASSEMBLY__ */
126 
127 /* The reset value of the ALT_GPIO_SWPORTA_DR register. */
128 #define ALT_GPIO_SWPORTA_DR_RESET 0x00000000
129 /* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */
130 #define ALT_GPIO_SWPORTA_DR_OFST 0x0
131 /* The address of the ALT_GPIO_SWPORTA_DR register. */
132 #define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST))
133 
134 /*
135  * Register : gpio_swporta_ddr
136  *
137  * Name: Port A Data Direction Register
138  *
139  * Size: 1-32 bits
140  *
141  * Address Offset: 0x04
142  *
143  * Read/Write Access: Read/Write
144  *
145  * Register Layout
146  *
147  * Bits | Access | Reset | Description
148  * :--------|:-------|:--------|:--------------------------------------
149  * [23:0] | RW | Unknown | ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
150  * [31:24] | ??? | Unknown | *UNDEFINED*
151  *
152  */
153 /*
154  * Field : gpio_swporta_ddr
155  *
156  * Values written to this register independently control the
157  *
158  * direction of the corresponding data bit in Port A. The
159  *
160  * default direction can be configured as input or output after
161  *
162  * system reset through the GPIO_DFLT_SRC_A parameter.
163  *
164  * 0 Input (default)
165  *
166  * 1 Output
167  *
168  * Field Enumeration Values:
169  *
170  * Enum | Value | Description
171  * :--------------------------------------------|:------|:-----------------
172  * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction
173  * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction
174  *
175  * Field Access Macros:
176  *
177  */
178 /*
179  * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
180  *
181  * Input Direction
182  */
183 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0
184 /*
185  * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
186  *
187  * Output Direction
188  */
189 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
190 
191 /* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
192 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0
193 /* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
194 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 23
195 /* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
196 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 24
197 /* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
198 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x00ffffff
199 /* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
200 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xff000000
201 /* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field is UNKNOWN. */
202 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0
203 /* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
204 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x00ffffff) >> 0)
205 /* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
206 #define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x00ffffff)
207 
208 #ifndef __ASSEMBLY__
209 /*
210  * WARNING: The C register and register group struct declarations are provided for
211  * convenience and illustrative purposes. They should, however, be used with
212  * caution as the C language standard provides no guarantees about the alignment or
213  * atomicity of device memory accesses. The recommended practice for writing
214  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
215  * alt_write_word() functions.
216  *
217  * The struct declaration for register ALT_GPIO_SWPORTA_DDR.
218  */
219 struct ALT_GPIO_SWPORTA_DDR_s
220 {
221  uint32_t gpio_swporta_ddr : 24; /* ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR */
222  uint32_t : 8; /* *UNDEFINED* */
223 };
224 
225 /* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */
226 typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t;
227 #endif /* __ASSEMBLY__ */
228 
229 /* The reset value of the ALT_GPIO_SWPORTA_DDR register. */
230 #define ALT_GPIO_SWPORTA_DDR_RESET 0x00000000
231 /* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */
232 #define ALT_GPIO_SWPORTA_DDR_OFST 0x4
233 /* The address of the ALT_GPIO_SWPORTA_DDR register. */
234 #define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST))
235 
236 /*
237  * Register : gpio_inten
238  *
239  * Name: Interrupt enable register
240  *
241  * Size: 1-32 bits
242  *
243  * Address Offset: 0x30
244  *
245  * Read/Write Access: Read/Write
246  *
247  * Register Layout
248  *
249  * Bits | Access | Reset | Description
250  * :--------|:-------|:------|:--------------------------
251  * [23:0] | RW | 0x0 | ALT_GPIO_INTEN_GPIO_INTEN
252  * [31:24] | ??? | 0x0 | *UNDEFINED*
253  *
254  */
255 /*
256  * Field : gpio_inten
257  *
258  * Allows each bit of Port A to be configured for interrupts. By
259  *
260  * default the generation of interrupts is disabled. Whenever a 1
261  *
262  * is written to a bit of this register, it configures the
263  *
264  * corresponding bit on Port A to become an interrupt;
265  *
266  * otherwise, Port A operates as a normal GPIO signal.
267  *
268  * Interrupts are disabled on the corresponding bits of Port A if
269  *
270  * the corresponding data direction register is set to Output or if
271  *
272  * Port A mode is set to Hardware.
273  *
274  * 0 Configure Port A bit as normal GPIO signal (default)
275  *
276  * 1 Configure Port A bit as interrupt
277  *
278  * Field Enumeration Values:
279  *
280  * Enum | Value | Description
281  * :--------------------------------|:------|:----------------------------
282  * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A
283  * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A
284  *
285  * Field Access Macros:
286  *
287  */
288 /*
289  * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
290  *
291  * Disable Interrupt on Port A
292  */
293 #define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0
294 /*
295  * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
296  *
297  * Enable Interrupt on Port A
298  */
299 #define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1
300 
301 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
302 #define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0
303 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
304 #define ALT_GPIO_INTEN_GPIO_INTEN_MSB 23
305 /* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
306 #define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 24
307 /* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
308 #define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x00ffffff
309 /* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
310 #define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xff000000
311 /* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
312 #define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0
313 /* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */
314 #define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x00ffffff) >> 0)
315 /* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
316 #define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x00ffffff)
317 
318 #ifndef __ASSEMBLY__
319 /*
320  * WARNING: The C register and register group struct declarations are provided for
321  * convenience and illustrative purposes. They should, however, be used with
322  * caution as the C language standard provides no guarantees about the alignment or
323  * atomicity of device memory accesses. The recommended practice for writing
324  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
325  * alt_write_word() functions.
326  *
327  * The struct declaration for register ALT_GPIO_INTEN.
328  */
329 struct ALT_GPIO_INTEN_s
330 {
331  uint32_t gpio_inten : 24; /* ALT_GPIO_INTEN_GPIO_INTEN */
332  uint32_t : 8; /* *UNDEFINED* */
333 };
334 
335 /* The typedef declaration for register ALT_GPIO_INTEN. */
336 typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t;
337 #endif /* __ASSEMBLY__ */
338 
339 /* The reset value of the ALT_GPIO_INTEN register. */
340 #define ALT_GPIO_INTEN_RESET 0x00000000
341 /* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */
342 #define ALT_GPIO_INTEN_OFST 0x30
343 /* The address of the ALT_GPIO_INTEN register. */
344 #define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST))
345 
346 /*
347  * Register : gpio_intmask
348  *
349  * Name: Interrupt mask register
350  *
351  * Size: 1-32 bits
352  *
353  * Address Offset: 0x34
354  *
355  * Read/Write Access: Read/Write
356  *
357  * Register Layout
358  *
359  * Bits | Access | Reset | Description
360  * :--------|:-------|:------|:----------------------------
361  * [23:0] | RW | 0x0 | ALT_GPIO_INTMSK_GPIO_INTMSK
362  * [31:24] | ??? | 0x0 | *UNDEFINED*
363  *
364  */
365 /*
366  * Field : gpio_intmask
367  *
368  * Controls whether an interrupt on Port A can create an
369  *
370  * interrupt for the interrupt controller by not masking it. By
371  *
372  * default, all interrupts bits are unmasked. Whenever a 1 is
373  *
374  * written to a bit in this register, it masks the interrupt
375  *
376  * generation capability for this signal; otherwise interrupts are
377  *
378  * allowed through. The unmasked status can be read as well as
379  *
380  * the resultant status after masking.
381  *
382  * 0 Interrupt bits are unmasked (default)
383  *
384  * 1 Mask interrupt
385  *
386  * Field Enumeration Values:
387  *
388  * Enum | Value | Description
389  * :----------------------------------|:------|:----------------------------
390  * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked
391  * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt
392  *
393  * Field Access Macros:
394  *
395  */
396 /*
397  * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
398  *
399  * Interrupt bits are unmasked
400  */
401 #define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0
402 /*
403  * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
404  *
405  * Mask Interrupt
406  */
407 #define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1
408 
409 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
410 #define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0
411 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
412 #define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 23
413 /* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
414 #define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 24
415 /* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
416 #define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x00ffffff
417 /* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
418 #define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xff000000
419 /* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
420 #define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0
421 /* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */
422 #define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x00ffffff) >> 0)
423 /* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */
424 #define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x00ffffff)
425 
426 #ifndef __ASSEMBLY__
427 /*
428  * WARNING: The C register and register group struct declarations are provided for
429  * convenience and illustrative purposes. They should, however, be used with
430  * caution as the C language standard provides no guarantees about the alignment or
431  * atomicity of device memory accesses. The recommended practice for writing
432  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
433  * alt_write_word() functions.
434  *
435  * The struct declaration for register ALT_GPIO_INTMSK.
436  */
437 struct ALT_GPIO_INTMSK_s
438 {
439  uint32_t gpio_intmask : 24; /* ALT_GPIO_INTMSK_GPIO_INTMSK */
440  uint32_t : 8; /* *UNDEFINED* */
441 };
442 
443 /* The typedef declaration for register ALT_GPIO_INTMSK. */
444 typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t;
445 #endif /* __ASSEMBLY__ */
446 
447 /* The reset value of the ALT_GPIO_INTMSK register. */
448 #define ALT_GPIO_INTMSK_RESET 0x00000000
449 /* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */
450 #define ALT_GPIO_INTMSK_OFST 0x34
451 /* The address of the ALT_GPIO_INTMSK register. */
452 #define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST))
453 
454 /*
455  * Register : gpio_inttype_level
456  *
457  * Name: Interrupt level
458  *
459  * Size: 1-32 bits
460  *
461  * Address Offset: 0x38
462  *
463  * Read/Write Access: Read/Write
464  *
465  * Register Layout
466  *
467  * Bits | Access | Reset | Description
468  * :--------|:-------|:------|:------------------------------------------
469  * [23:0] | RW | 0x0 | ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
470  * [31:24] | ??? | 0x0 | *UNDEFINED*
471  *
472  */
473 /*
474  * Field : gpio_inttype_level
475  *
476  * Controls the type of interrupt that can occur on Port A.
477  *
478  * Whenever a 0 is written to a bit of this register, it configures
479  *
480  * the interrupt type to be level-sensitive; otherwise, it is
481  *
482  * edge-sensitive.
483  *
484  * 0 Level-sensitive (default)
485  *
486  * 1 Edge-sensitive
487  *
488  * Field Enumeration Values:
489  *
490  * Enum | Value | Description
491  * :--------------------------------------------------|:------|:----------------
492  * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive
493  * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive
494  *
495  * Field Access Macros:
496  *
497  */
498 /*
499  * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
500  *
501  * Level-sensitive
502  */
503 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0
504 /*
505  * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
506  *
507  * Edge-sensitive
508  */
509 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1
510 
511 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
512 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0
513 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
514 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 23
515 /* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
516 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 24
517 /* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
518 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x00ffffff
519 /* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
520 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xff000000
521 /* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
522 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0
523 /* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
524 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x00ffffff) >> 0)
525 /* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
526 #define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x00ffffff)
527 
528 #ifndef __ASSEMBLY__
529 /*
530  * WARNING: The C register and register group struct declarations are provided for
531  * convenience and illustrative purposes. They should, however, be used with
532  * caution as the C language standard provides no guarantees about the alignment or
533  * atomicity of device memory accesses. The recommended practice for writing
534  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
535  * alt_write_word() functions.
536  *
537  * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL.
538  */
539 struct ALT_GPIO_INTTYPE_LEVEL_s
540 {
541  uint32_t gpio_inttype_level : 24; /* ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL */
542  uint32_t : 8; /* *UNDEFINED* */
543 };
544 
545 /* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */
546 typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t;
547 #endif /* __ASSEMBLY__ */
548 
549 /* The reset value of the ALT_GPIO_INTTYPE_LEVEL register. */
550 #define ALT_GPIO_INTTYPE_LEVEL_RESET 0x00000000
551 /* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
552 #define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38
553 /* The address of the ALT_GPIO_INTTYPE_LEVEL register. */
554 #define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST))
555 
556 /*
557  * Register : gpio_int_polarity
558  *
559  * Name: Interrupt polarity
560  *
561  * Size: 1-32 bits
562  *
563  * Address Offset: 0x3c
564  *
565  * Read/Write Access: Read/Write
566  *
567  * Register Layout
568  *
569  * Bits | Access | Reset | Description
570  * :--------|:-------|:------|:------------------------------
571  * [23:0] | RW | 0x0 | ALT_GPIO_INT_POL_GPIO_INT_POL
572  * [31:24] | ??? | 0x0 | *UNDEFINED*
573  *
574  */
575 /*
576  * Field : gpio_int_polarity
577  *
578  * Controls the polarity of edge or level sensitivity that can
579  *
580  * occur on input of Port A. Whenever a 0 is written to a bit of
581  *
582  * this register, it configures the interrupt type to falling-edge or
583  *
584  * active-low sensitive; otherwise, it is rising-edge or
585  *
586  * active-high sensitive.
587  *
588  * 0 Active-low (default)
589  *
590  * 1 Active-high
591  *
592  * Field Enumeration Values:
593  *
594  * Enum | Value | Description
595  * :----------------------------------------|:------|:------------
596  * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low
597  * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high
598  *
599  * Field Access Macros:
600  *
601  */
602 /*
603  * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
604  *
605  * Active low
606  */
607 #define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0
608 /*
609  * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
610  *
611  * Active high
612  */
613 #define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1
614 
615 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
616 #define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0
617 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
618 #define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 23
619 /* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
620 #define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 24
621 /* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
622 #define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x00ffffff
623 /* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
624 #define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xff000000
625 /* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
626 #define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0
627 /* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */
628 #define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x00ffffff) >> 0)
629 /* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */
630 #define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x00ffffff)
631 
632 #ifndef __ASSEMBLY__
633 /*
634  * WARNING: The C register and register group struct declarations are provided for
635  * convenience and illustrative purposes. They should, however, be used with
636  * caution as the C language standard provides no guarantees about the alignment or
637  * atomicity of device memory accesses. The recommended practice for writing
638  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
639  * alt_write_word() functions.
640  *
641  * The struct declaration for register ALT_GPIO_INT_POL.
642  */
643 struct ALT_GPIO_INT_POL_s
644 {
645  uint32_t gpio_int_polarity : 24; /* ALT_GPIO_INT_POL_GPIO_INT_POL */
646  uint32_t : 8; /* *UNDEFINED* */
647 };
648 
649 /* The typedef declaration for register ALT_GPIO_INT_POL. */
650 typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t;
651 #endif /* __ASSEMBLY__ */
652 
653 /* The reset value of the ALT_GPIO_INT_POL register. */
654 #define ALT_GPIO_INT_POL_RESET 0x00000000
655 /* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */
656 #define ALT_GPIO_INT_POL_OFST 0x3c
657 /* The address of the ALT_GPIO_INT_POL register. */
658 #define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST))
659 
660 /*
661  * Register : gpio_intstatus
662  *
663  * Name: Interrupt status
664  *
665  * Size: 1-32 bits
666  *
667  * Address Offset: 0x40
668  *
669  * Read/Write Access: Read/Write
670  *
671  * Register Layout
672  *
673  * Bits | Access | Reset | Description
674  * :--------|:-------|:------|:------------------------------
675  * [23:0] | R | 0x0 | ALT_GPIO_INTSTAT_GPIO_INTSTAT
676  * [31:24] | ??? | 0x0 | *UNDEFINED*
677  *
678  */
679 /*
680  * Field : gpio_intstatus
681  *
682  * Interrupt status of Port A.
683  *
684  * Field Enumeration Values:
685  *
686  * Enum | Value | Description
687  * :--------------------------------------|:------|:------------
688  * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive
689  * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active
690  *
691  * Field Access Macros:
692  *
693  */
694 /*
695  * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
696  *
697  * Inactive
698  */
699 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0
700 /*
701  * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
702  *
703  * Active
704  */
705 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1
706 
707 /* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
708 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0
709 /* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
710 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 23
711 /* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
712 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 24
713 /* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
714 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x00ffffff
715 /* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
716 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xff000000
717 /* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
718 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0
719 /* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */
720 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x00ffffff) >> 0)
721 /* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */
722 #define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x00ffffff)
723 
724 #ifndef __ASSEMBLY__
725 /*
726  * WARNING: The C register and register group struct declarations are provided for
727  * convenience and illustrative purposes. They should, however, be used with
728  * caution as the C language standard provides no guarantees about the alignment or
729  * atomicity of device memory accesses. The recommended practice for writing
730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
731  * alt_write_word() functions.
732  *
733  * The struct declaration for register ALT_GPIO_INTSTAT.
734  */
735 struct ALT_GPIO_INTSTAT_s
736 {
737  const uint32_t gpio_intstatus : 24; /* ALT_GPIO_INTSTAT_GPIO_INTSTAT */
738  uint32_t : 8; /* *UNDEFINED* */
739 };
740 
741 /* The typedef declaration for register ALT_GPIO_INTSTAT. */
742 typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t;
743 #endif /* __ASSEMBLY__ */
744 
745 /* The reset value of the ALT_GPIO_INTSTAT register. */
746 #define ALT_GPIO_INTSTAT_RESET 0x00000000
747 /* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */
748 #define ALT_GPIO_INTSTAT_OFST 0x40
749 /* The address of the ALT_GPIO_INTSTAT register. */
750 #define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST))
751 
752 /*
753  * Register : gpio_raw_intstatus
754  *
755  * Name: Raw interrupt status
756  *
757  * Size: 1-32 bits
758  *
759  * Address Offset: 0x44
760  *
761  * Read/Write Access: Read/Write
762  *
763  * Register Layout
764  *
765  * Bits | Access | Reset | Description
766  * :--------|:-------|:------|:--------------------------------------
767  * [23:0] | R | 0x0 | ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
768  * [31:24] | ??? | 0x0 | *UNDEFINED*
769  *
770  */
771 /*
772  * Field : gpio_raw_intstatus
773  *
774  * Raw interrupt of status of Port A (premasking bits)
775  *
776  * Field Enumeration Values:
777  *
778  * Enum | Value | Description
779  * :----------------------------------------------|:------|:------------
780  * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive
781  * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active
782  *
783  * Field Access Macros:
784  *
785  */
786 /*
787  * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
788  *
789  * Inactive
790  */
791 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0
792 /*
793  * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
794  *
795  * Active
796  */
797 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1
798 
799 /* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
800 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0
801 /* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
802 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 23
803 /* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
804 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 24
805 /* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
806 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x00ffffff
807 /* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
808 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xff000000
809 /* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
810 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0
811 /* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */
812 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x00ffffff) >> 0)
813 /* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */
814 #define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x00ffffff)
815 
816 #ifndef __ASSEMBLY__
817 /*
818  * WARNING: The C register and register group struct declarations are provided for
819  * convenience and illustrative purposes. They should, however, be used with
820  * caution as the C language standard provides no guarantees about the alignment or
821  * atomicity of device memory accesses. The recommended practice for writing
822  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
823  * alt_write_word() functions.
824  *
825  * The struct declaration for register ALT_GPIO_RAW_INTSTAT.
826  */
827 struct ALT_GPIO_RAW_INTSTAT_s
828 {
829  const uint32_t gpio_raw_intstatus : 24; /* ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT */
830  uint32_t : 8; /* *UNDEFINED* */
831 };
832 
833 /* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */
834 typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t;
835 #endif /* __ASSEMBLY__ */
836 
837 /* The reset value of the ALT_GPIO_RAW_INTSTAT register. */
838 #define ALT_GPIO_RAW_INTSTAT_RESET 0x00000000
839 /* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */
840 #define ALT_GPIO_RAW_INTSTAT_OFST 0x44
841 /* The address of the ALT_GPIO_RAW_INTSTAT register. */
842 #define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST))
843 
844 /*
845  * Register : gpio_debounce
846  *
847  * Name: Debounce enable
848  *
849  * Size: 1-32 bits
850  *
851  * Address Offset: 0x48
852  *
853  * Read/Write Access: Read/Write
854  *
855  * Register Layout
856  *
857  * Bits | Access | Reset | Description
858  * :--------|:-------|:------|:--------------------------------
859  * [23:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
860  * [31:24] | ??? | 0x0 | *UNDEFINED*
861  *
862  */
863 /*
864  * Field : gpio_debounce
865  *
866  * Controls whether an external signal that is the source
867  *
868  * of an interrupt needs to be debounced to remove any
869  *
870  * spurious glitches. Writing a 1 to a bit in this register
871  *
872  * enables the debouncing circuitry. A signal must be
873  *
874  * valid for two periods of an external clock before it is
875  *
876  * internally processed.
877  *
878  * 0 No debounce (default)
879  *
880  * 1 Enable debounce
881  *
882  * Field Enumeration Values:
883  *
884  * Enum | Value | Description
885  * :--------------------------------------|:------|:----------------
886  * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce
887  * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce
888  *
889  * Field Access Macros:
890  *
891  */
892 /*
893  * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
894  *
895  * No debounce
896  */
897 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0
898 /*
899  * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
900  *
901  * Enable debounce
902  */
903 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1
904 
905 /* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
906 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0
907 /* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
908 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 23
909 /* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
910 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 24
911 /* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
912 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x00ffffff
913 /* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
914 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xff000000
915 /* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
916 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0
917 /* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
918 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x00ffffff) >> 0)
919 /* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
920 #define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x00ffffff)
921 
922 #ifndef __ASSEMBLY__
923 /*
924  * WARNING: The C register and register group struct declarations are provided for
925  * convenience and illustrative purposes. They should, however, be used with
926  * caution as the C language standard provides no guarantees about the alignment or
927  * atomicity of device memory accesses. The recommended practice for writing
928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
929  * alt_write_word() functions.
930  *
931  * The struct declaration for register ALT_GPIO_DEBOUNCE.
932  */
933 struct ALT_GPIO_DEBOUNCE_s
934 {
935  uint32_t gpio_debounce : 24; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
936  uint32_t : 8; /* *UNDEFINED* */
937 };
938 
939 /* The typedef declaration for register ALT_GPIO_DEBOUNCE. */
940 typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t;
941 #endif /* __ASSEMBLY__ */
942 
943 /* The reset value of the ALT_GPIO_DEBOUNCE register. */
944 #define ALT_GPIO_DEBOUNCE_RESET 0x00000000
945 /* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */
946 #define ALT_GPIO_DEBOUNCE_OFST 0x48
947 /* The address of the ALT_GPIO_DEBOUNCE register. */
948 #define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST))
949 
950 /*
951  * Register : gpio_porta_eoi
952  *
953  * Name: Port A clear interrupt register
954  *
955  * Size: 1-32 bits
956  *
957  * Address Offset: 0x4c
958  *
959  * Read/Write Access: Write
960  *
961  * Register Layout
962  *
963  * Bits | Access | Reset | Description
964  * :--------|:-------|:------|:----------------------------------
965  * [23:0] | W | 0x0 | ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
966  * [31:24] | ??? | 0x0 | *UNDEFINED*
967  *
968  */
969 /*
970  * Field : gpio_porta_eoi
971  *
972  * Controls the clearing of edge type interrupts from Port A.
973  *
974  * When a 1 is written into a corresponding bit of this register,
975  *
976  * the interrupt is cleared. All interrupts are cleared when
977  *
978  * Port A is not configured for interrupts.
979  *
980  * 0 No interrupt clear (default)
981  *
982  * 1 Clear interrupt
983  *
984  * Field Enumeration Values:
985  *
986  * Enum | Value | Description
987  * :------------------------------------------|:------|:-------------------
988  * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear
989  * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt
990  *
991  * Field Access Macros:
992  *
993  */
994 /*
995  * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
996  *
997  * No interrupt clear
998  */
999 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0
1000 /*
1001  * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
1002  *
1003  * Clear interrupt
1004  */
1005 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1
1006 
1007 /* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1008 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0
1009 /* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1010 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 23
1011 /* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1012 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 24
1013 /* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
1014 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x00ffffff
1015 /* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
1016 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xff000000
1017 /* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1018 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0
1019 /* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
1020 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x00ffffff) >> 0)
1021 /* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
1022 #define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x00ffffff)
1023 
1024 #ifndef __ASSEMBLY__
1025 /*
1026  * WARNING: The C register and register group struct declarations are provided for
1027  * convenience and illustrative purposes. They should, however, be used with
1028  * caution as the C language standard provides no guarantees about the alignment or
1029  * atomicity of device memory accesses. The recommended practice for writing
1030  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1031  * alt_write_word() functions.
1032  *
1033  * The struct declaration for register ALT_GPIO_PORTA_EOI.
1034  */
1035 struct ALT_GPIO_PORTA_EOI_s
1036 {
1037  uint32_t gpio_porta_eoi : 24; /* ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI */
1038  uint32_t : 8; /* *UNDEFINED* */
1039 };
1040 
1041 /* The typedef declaration for register ALT_GPIO_PORTA_EOI. */
1042 typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t;
1043 #endif /* __ASSEMBLY__ */
1044 
1045 /* The reset value of the ALT_GPIO_PORTA_EOI register. */
1046 #define ALT_GPIO_PORTA_EOI_RESET 0x00000000
1047 /* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */
1048 #define ALT_GPIO_PORTA_EOI_OFST 0x4c
1049 /* The address of the ALT_GPIO_PORTA_EOI register. */
1050 #define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST))
1051 
1052 /*
1053  * Register : gpio_ext_porta
1054  *
1055  * Name: Port A external port register
1056  *
1057  * Size: 1-32 bits
1058  *
1059  * Address Offset: 0x50
1060  *
1061  * Read/Write Access: Read
1062  *
1063  * Register Layout
1064  *
1065  * Bits | Access | Reset | Description
1066  * :--------|:-------|:------|:----------------------------------
1067  * [23:0] | R | 0x0 | ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA
1068  * [31:24] | ??? | 0x0 | *UNDEFINED*
1069  *
1070  */
1071 /*
1072  * Field : gpio_ext_porta
1073  *
1074  * When Port A is configured as Input, then reading this
1075  *
1076  * location reads the values on the signal. When the data
1077  *
1078  * direction of Port A is set as Output, reading this location
1079  *
1080  * reads the data register for Port A.
1081  *
1082  * Field Access Macros:
1083  *
1084  */
1085 /* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1086 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0
1087 /* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1088 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 23
1089 /* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1090 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 24
1091 /* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
1092 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x00ffffff
1093 /* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
1094 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xff000000
1095 /* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1096 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0
1097 /* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
1098 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x00ffffff) >> 0)
1099 /* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
1100 #define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x00ffffff)
1101 
1102 #ifndef __ASSEMBLY__
1103 /*
1104  * WARNING: The C register and register group struct declarations are provided for
1105  * convenience and illustrative purposes. They should, however, be used with
1106  * caution as the C language standard provides no guarantees about the alignment or
1107  * atomicity of device memory accesses. The recommended practice for writing
1108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1109  * alt_write_word() functions.
1110  *
1111  * The struct declaration for register ALT_GPIO_EXT_PORTA.
1112  */
1113 struct ALT_GPIO_EXT_PORTA_s
1114 {
1115  const uint32_t gpio_ext_porta : 24; /* ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA */
1116  uint32_t : 8; /* *UNDEFINED* */
1117 };
1118 
1119 /* The typedef declaration for register ALT_GPIO_EXT_PORTA. */
1120 typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t;
1121 #endif /* __ASSEMBLY__ */
1122 
1123 /* The reset value of the ALT_GPIO_EXT_PORTA register. */
1124 #define ALT_GPIO_EXT_PORTA_RESET 0x00000000
1125 /* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */
1126 #define ALT_GPIO_EXT_PORTA_OFST 0x50
1127 /* The address of the ALT_GPIO_EXT_PORTA register. */
1128 #define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST))
1129 
1130 /*
1131  * Register : gpio_ls_sync
1132  *
1133  * Name: Synchronization level
1134  *
1135  * Size: 1 bit
1136  *
1137  * Address Offset: 0x60
1138  *
1139  * Read/Write Access: Read/Write
1140  *
1141  * Register Layout
1142  *
1143  * Bits | Access | Reset | Description
1144  * :-------|:-------|:------|:------------------------------
1145  * [0] | RW | 0x0 | ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
1146  * [31:1] | ??? | 0x0 | *UNDEFINED*
1147  *
1148  */
1149 /*
1150  * Field : gpio_ls_sync
1151  *
1152  * Writing a 1 to this register results in all level-sensitive interrupts being
1153  *
1154  * synchronized to pclk_intr.
1155  *
1156  * 0 No synchronization to pclk_intr (default)
1157  *
1158  * 1 Synchronize to pclk_intr
1159  *
1160  * Field Enumeration Values:
1161  *
1162  * Enum | Value | Description
1163  * :---------------------------------------|:------|:--------------------------------
1164  * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk
1165  * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk
1166  *
1167  * Field Access Macros:
1168  *
1169  */
1170 /*
1171  * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
1172  *
1173  * No synchronization to l4_mp_clk
1174  */
1175 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0
1176 /*
1177  * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
1178  *
1179  * Synchronize to l4_mp_clk
1180  */
1181 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1
1182 
1183 /* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1184 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
1185 /* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1186 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
1187 /* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1188 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
1189 /* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1190 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
1191 /* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1192 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
1193 /* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1194 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
1195 /* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
1196 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
1197 /* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
1198 #define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
1199 
1200 #ifndef __ASSEMBLY__
1201 /*
1202  * WARNING: The C register and register group struct declarations are provided for
1203  * convenience and illustrative purposes. They should, however, be used with
1204  * caution as the C language standard provides no guarantees about the alignment or
1205  * atomicity of device memory accesses. The recommended practice for writing
1206  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1207  * alt_write_word() functions.
1208  *
1209  * The struct declaration for register ALT_GPIO_LS_SYNC.
1210  */
1211 struct ALT_GPIO_LS_SYNC_s
1212 {
1213  uint32_t gpio_ls_sync : 1; /* ALT_GPIO_LS_SYNC_GPIO_LS_SYNC */
1214  uint32_t : 31; /* *UNDEFINED* */
1215 };
1216 
1217 /* The typedef declaration for register ALT_GPIO_LS_SYNC. */
1218 typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t;
1219 #endif /* __ASSEMBLY__ */
1220 
1221 /* The reset value of the ALT_GPIO_LS_SYNC register. */
1222 #define ALT_GPIO_LS_SYNC_RESET 0x00000000
1223 /* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */
1224 #define ALT_GPIO_LS_SYNC_OFST 0x60
1225 /* The address of the ALT_GPIO_LS_SYNC register. */
1226 #define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST))
1227 
1228 /*
1229  * Register : gpio_id_code
1230  *
1231  * Name: GPIO ID code
1232  *
1233  * Size: 1-32 bits
1234  *
1235  * Address Offset: 0x64
1236  *
1237  * Read/Write Access: Read
1238  *
1239  * Register Layout
1240  *
1241  * Bits | Access | Reset | Description
1242  * :-------|:-------|:------|:------------------------------
1243  * [31:0] | R | 0x0 | ALT_GPIO_ID_CODE_GPIO_ID_CODE
1244  *
1245  */
1246 /*
1247  * Field : gpio_id_code
1248  *
1249  * This is a user-specified code that a system can read. It can
1250  *
1251  * be used for chip identification, and so on.
1252  *
1253  * Field Access Macros:
1254  *
1255  */
1256 /* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1257 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0
1258 /* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1259 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31
1260 /* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1261 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32
1262 /* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1263 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff
1264 /* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1265 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000
1266 /* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1267 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0
1268 /* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
1269 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1270 /* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
1271 #define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1272 
1273 #ifndef __ASSEMBLY__
1274 /*
1275  * WARNING: The C register and register group struct declarations are provided for
1276  * convenience and illustrative purposes. They should, however, be used with
1277  * caution as the C language standard provides no guarantees about the alignment or
1278  * atomicity of device memory accesses. The recommended practice for writing
1279  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1280  * alt_write_word() functions.
1281  *
1282  * The struct declaration for register ALT_GPIO_ID_CODE.
1283  */
1284 struct ALT_GPIO_ID_CODE_s
1285 {
1286  const uint32_t gpio_id_code : 32; /* ALT_GPIO_ID_CODE_GPIO_ID_CODE */
1287 };
1288 
1289 /* The typedef declaration for register ALT_GPIO_ID_CODE. */
1290 typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t;
1291 #endif /* __ASSEMBLY__ */
1292 
1293 /* The reset value of the ALT_GPIO_ID_CODE register. */
1294 #define ALT_GPIO_ID_CODE_RESET 0x00000000
1295 /* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */
1296 #define ALT_GPIO_ID_CODE_OFST 0x64
1297 /* The address of the ALT_GPIO_ID_CODE register. */
1298 #define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST))
1299 
1300 /*
1301  * Register : gpio_ver_id_code
1302  *
1303  * Name: GPIO Component Version
1304  *
1305  * Size: 32 bits
1306  *
1307  * Address Offset: 0x6c
1308  *
1309  * Read/Write Access: Read
1310  *
1311  * Register Layout
1312  *
1313  * Bits | Access | Reset | Description
1314  * :-------|:-------|:-----------|:--------------------------------------
1315  * [31:0] | R | 0x3230392a | ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE
1316  *
1317  */
1318 /*
1319  * Field : gpio_ver_id_code
1320  *
1321  * ASCII value for each number in the version.
1322  *
1323  * Field Access Macros:
1324  *
1325  */
1326 /* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1327 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
1328 /* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1329 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
1330 /* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1331 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
1332 /* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1333 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
1334 /* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1335 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
1336 /* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1337 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230392a
1338 /* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
1339 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1340 /* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
1341 #define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1342 
1343 #ifndef __ASSEMBLY__
1344 /*
1345  * WARNING: The C register and register group struct declarations are provided for
1346  * convenience and illustrative purposes. They should, however, be used with
1347  * caution as the C language standard provides no guarantees about the alignment or
1348  * atomicity of device memory accesses. The recommended practice for writing
1349  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1350  * alt_write_word() functions.
1351  *
1352  * The struct declaration for register ALT_GPIO_VER_ID_CODE.
1353  */
1354 struct ALT_GPIO_VER_ID_CODE_s
1355 {
1356  const uint32_t gpio_ver_id_code : 32; /* ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE */
1357 };
1358 
1359 /* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */
1360 typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t;
1361 #endif /* __ASSEMBLY__ */
1362 
1363 /* The reset value of the ALT_GPIO_VER_ID_CODE register. */
1364 #define ALT_GPIO_VER_ID_CODE_RESET 0x3230392a
1365 /* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */
1366 #define ALT_GPIO_VER_ID_CODE_OFST 0x6c
1367 /* The address of the ALT_GPIO_VER_ID_CODE register. */
1368 #define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST))
1369 
1370 /*
1371  * Register : gpio_config_reg2
1372  *
1373  * Name: GPIO Configuration Register 2
1374  *
1375  * Size: 32 bits
1376  *
1377  * Address Offset: 0x70
1378  *
1379  * Read/Write Access: Read
1380  *
1381  * Register Layout
1382  *
1383  * Bits | Access | Reset | Description
1384  * :--------|:-------|:------|:----------------------------------
1385  * [4:0] | R | 0x17 | ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1386  * [9:5] | R | 0x7 | ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1387  * [14:10] | R | 0x7 | ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1388  * [19:15] | R | 0x7 | ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1389  * [31:20] | ??? | 0x0 | *UNDEFINED*
1390  *
1391  */
1392 /*
1393  * Field : encoded_id_pwidth_a
1394  *
1395  * The value of this register is derived from the
1396  *
1397  * GPIO_PWIDTH_A configuration parameter.
1398  *
1399  * 0x0 = 8 bits
1400  *
1401  * 0x1 = 16 bits
1402  *
1403  * 0x2 = 32 bits
1404  *
1405  * 0x3 = Reserved
1406  *
1407  * Field Enumeration Values:
1408  *
1409  * Enum | Value | Description
1410  * :-------------------------------------------------------|:------|:--------------------------
1411  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1412  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE24BITS | 0x1c | Width (less 1) of 24 bits
1413  *
1414  * Field Access Macros:
1415  *
1416  */
1417 /*
1418  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1419  *
1420  * Width (less 1) of 8 bits
1421  */
1422 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7
1423 /*
1424  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1425  *
1426  * Width (less 1) of 24 bits
1427  */
1428 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE24BITS 0x1c
1429 
1430 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1431 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0
1432 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1433 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4
1434 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1435 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5
1436 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1437 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f
1438 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1439 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0
1440 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1441 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x17
1442 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
1443 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
1444 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
1445 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
1446 
1447 /*
1448  * Field : encoded_id_pwidth_b
1449  *
1450  * The value of this register is derived from the
1451  *
1452  * GPIO_PWIDTH_B configuration parameter.
1453  *
1454  * 0x0 = 8 bits
1455  *
1456  * 0x1 = 16 bits
1457  *
1458  * 0x2 = 32 bits
1459  *
1460  * 0x3 = Reserved
1461  *
1462  * Field Enumeration Values:
1463  *
1464  * Enum | Value | Description
1465  * :-------------------------------------------------------|:------|:--------------------------
1466  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1467  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE24BITS | 0x1c | Width (less 1) of 24 bits
1468  *
1469  * Field Access Macros:
1470  *
1471  */
1472 /*
1473  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1474  *
1475  * Width (less 1) of 8 bits
1476  */
1477 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7
1478 /*
1479  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1480  *
1481  * Width (less 1) of 24 bits
1482  */
1483 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE24BITS 0x1c
1484 
1485 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1486 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5
1487 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1488 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9
1489 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1490 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5
1491 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1492 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0
1493 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1494 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
1495 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1496 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7
1497 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
1498 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
1499 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
1500 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
1501 
1502 /*
1503  * Field : encoded_id_pwidth_c
1504  *
1505  * The value of this register is derived from the
1506  *
1507  * GPIO_PWIDTH_C configuration parameter.
1508  *
1509  * 0x0 = 8 bits
1510  *
1511  * 0x1 = 16 bits
1512  *
1513  * 0x2 = 32 bits
1514  *
1515  * 0x3 = Reserved
1516  *
1517  * Field Enumeration Values:
1518  *
1519  * Enum | Value | Description
1520  * :-------------------------------------------------------|:------|:--------------------------
1521  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1522  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE24BITS | 0x1c | Width (less 1) of 24 bits
1523  *
1524  * Field Access Macros:
1525  *
1526  */
1527 /*
1528  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1529  *
1530  * Width (less 1) of 8 bits
1531  */
1532 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7
1533 /*
1534  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1535  *
1536  * Width (less 1) of 24 bits
1537  */
1538 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE24BITS 0x1c
1539 
1540 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1541 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10
1542 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1543 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14
1544 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1545 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5
1546 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1547 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00
1548 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1549 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff
1550 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1551 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7
1552 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
1553 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
1554 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
1555 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
1556 
1557 /*
1558  * Field : encoded_id_pwidth_d
1559  *
1560  * The value of this register is derived from the
1561  *
1562  * GPIO_PWIDTH_D configuration parameter.
1563  *
1564  * 0x0 = 8 bits
1565  *
1566  * 0x1 = 16 bits
1567  *
1568  * 0x2 = 32 bits
1569  *
1570  * 0x3 = Reserved
1571  *
1572  * Field Enumeration Values:
1573  *
1574  * Enum | Value | Description
1575  * :-------------------------------------------------------|:------|:--------------------------
1576  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1577  * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE24BITS | 0x1c | Width (less 1) of 24 bits
1578  *
1579  * Field Access Macros:
1580  *
1581  */
1582 /*
1583  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1584  *
1585  * Width (less 1) of 8 bits
1586  */
1587 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7
1588 /*
1589  * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1590  *
1591  * Width (less 1) of 24 bits
1592  */
1593 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE24BITS 0x1c
1594 
1595 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1596 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15
1597 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1598 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19
1599 /* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1600 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5
1601 /* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1602 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000
1603 /* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1604 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff
1605 /* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1606 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7
1607 /* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
1608 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
1609 /* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
1610 #define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
1611 
1612 #ifndef __ASSEMBLY__
1613 /*
1614  * WARNING: The C register and register group struct declarations are provided for
1615  * convenience and illustrative purposes. They should, however, be used with
1616  * caution as the C language standard provides no guarantees about the alignment or
1617  * atomicity of device memory accesses. The recommended practice for writing
1618  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1619  * alt_write_word() functions.
1620  *
1621  * The struct declaration for register ALT_GPIO_CFG_REG2.
1622  */
1623 struct ALT_GPIO_CFG_REG2_s
1624 {
1625  const uint32_t encoded_id_pwidth_a : 5; /* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A */
1626  const uint32_t encoded_id_pwidth_b : 5; /* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B */
1627  const uint32_t encoded_id_pwidth_c : 5; /* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C */
1628  const uint32_t encoded_id_pwidth_d : 5; /* ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D */
1629  uint32_t : 12; /* *UNDEFINED* */
1630 };
1631 
1632 /* The typedef declaration for register ALT_GPIO_CFG_REG2. */
1633 typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t;
1634 #endif /* __ASSEMBLY__ */
1635 
1636 /* The reset value of the ALT_GPIO_CFG_REG2 register. */
1637 #define ALT_GPIO_CFG_REG2_RESET 0x00039cf7
1638 /* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */
1639 #define ALT_GPIO_CFG_REG2_OFST 0x70
1640 /* The address of the ALT_GPIO_CFG_REG2 register. */
1641 #define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))
1642 
1643 /*
1644  * Register : gpio_config_reg1
1645  *
1646  * Name: GPIO Configuration Register 1
1647  *
1648  * Size: 32 bits
1649  *
1650  * Address Offset: 0x74
1651  *
1652  * Read/Write Access: Read
1653  *
1654  * Register Layout
1655  *
1656  * Bits | Access | Reset | Description
1657  * :--------|:-------|:------|:-----------------------------------
1658  * [1:0] | R | 0x2 | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
1659  * [3:2] | R | 0x0 | ALT_GPIO_CFG_REG1_NUM_PORTS
1660  * [4] | R | 0x1 | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
1661  * [5] | R | 0x1 | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
1662  * [6] | R | 0x1 | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
1663  * [7] | R | 0x1 | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
1664  * [8] | R | 0x0 | ALT_GPIO_CFG_REG1_HW_PORTA
1665  * [9] | R | 0x0 | ALT_GPIO_CFG_REG1_HW_PORTB
1666  * [10] | R | 0x0 | ALT_GPIO_CFG_REG1_HW_PORTC
1667  * [11] | R | 0x0 | ALT_GPIO_CFG_REG1_HW_PORTD
1668  * [12] | R | 0x1 | ALT_GPIO_CFG_REG1_PORTA_INTR
1669  * [13] | R | 0x1 | ALT_GPIO_CFG_REG1_DEBOUNCE
1670  * [14] | R | 0x1 | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
1671  * [15] | R | 0x1 | ALT_GPIO_CFG_REG1_GPIO_ID
1672  * [20:16] | R | 0x1f | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
1673  * [31:21] | ??? | 0x0 | *UNDEFINED*
1674  *
1675  */
1676 /*
1677  * Field : apb_data_width
1678  *
1679  * The value of this register is derived from the
1680  *
1681  * GPIO_APB_DATA_WIDTH configuration parameter.
1682  *
1683  * 0x0 = 8 bits
1684  *
1685  * 0x1 = 16 bits
1686  *
1687  * 0x2 = 32 bits
1688  *
1689  * 0x3 = Reserved
1690  *
1691  * Field Enumeration Values:
1692  *
1693  * Enum | Value | Description
1694  * :-----------------------------------------------|:------|:-------------------------
1695  * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
1696  *
1697  * Field Access Macros:
1698  *
1699  */
1700 /*
1701  * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
1702  *
1703  * APB Data Width = 32-bits
1704  */
1705 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1706 
1707 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1708 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0
1709 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1710 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1
1711 /* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1712 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2
1713 /* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1714 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
1715 /* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1716 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
1717 /* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1718 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2
1719 /* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
1720 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
1721 /* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
1722 #define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
1723 
1724 /*
1725  * Field : num_ports
1726  *
1727  * The value of this register is derived from the
1728  *
1729  * GPIO_NUM_PORT configuration parameter.
1730  *
1731  * 0x0 =1
1732  *
1733  * 0x1 = 2
1734  *
1735  * 0x2 = 3
1736  *
1737  * 0x3 = 4
1738  *
1739  * Field Enumeration Values:
1740  *
1741  * Enum | Value | Description
1742  * :---------------------------------------|:------|:-------------------------
1743  * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1
1744  *
1745  * Field Access Macros:
1746  *
1747  */
1748 /*
1749  * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
1750  *
1751  * Number of GPIO Ports = 1
1752  */
1753 #define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0
1754 
1755 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1756 #define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2
1757 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1758 #define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3
1759 /* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1760 #define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2
1761 /* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1762 #define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c
1763 /* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1764 #define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
1765 /* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1766 #define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0
1767 /* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
1768 #define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
1769 /* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
1770 #define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
1771 
1772 /*
1773  * Field : porta_single_ctl
1774  *
1775  * The value of this register is derived from the
1776  *
1777  * GPIO_PORTA_SINGLE_CTL configuration parameter.
1778  *
1779  * 0 = False
1780  *
1781  * 1 = True
1782  *
1783  * Field Enumeration Values:
1784  *
1785  * Enum | Value | Description
1786  * :-------------------------------------------------|:------|:-----------------------------------------
1787  * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1788  *
1789  * Field Access Macros:
1790  *
1791  */
1792 /*
1793  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
1794  *
1795  * Software Enabled Individual Port Control
1796  */
1797 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1
1798 
1799 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1800 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4
1801 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1802 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4
1803 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1804 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1
1805 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1806 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
1807 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1808 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
1809 /* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1810 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1
1811 /* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
1812 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
1813 /* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
1814 #define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
1815 
1816 /*
1817  * Field : portb_single_ctl
1818  *
1819  * The value of this register is derived from the
1820  *
1821  * GPIO_PORTB_SINGLE_CTL configuration parameter.
1822  *
1823  * 0 = False
1824  *
1825  * 1 = True
1826  *
1827  * Field Enumeration Values:
1828  *
1829  * Enum | Value | Description
1830  * :-------------------------------------------------|:------|:-----------------------------------------
1831  * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1832  *
1833  * Field Access Macros:
1834  *
1835  */
1836 /*
1837  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
1838  *
1839  * Software Enabled Individual Port Control
1840  */
1841 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1
1842 
1843 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1844 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5
1845 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1846 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5
1847 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1848 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1
1849 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1850 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
1851 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1852 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
1853 /* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1854 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1
1855 /* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
1856 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
1857 /* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
1858 #define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
1859 
1860 /*
1861  * Field : portc_single_ctl
1862  *
1863  * The value of this register is derived from the
1864  *
1865  * GPIO_PORTC_SINGLE_CTL configuration parameter.
1866  *
1867  * 0 = False
1868  *
1869  * 1 = True
1870  *
1871  * Field Enumeration Values:
1872  *
1873  * Enum | Value | Description
1874  * :-------------------------------------------------|:------|:-----------------------------------------
1875  * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1876  *
1877  * Field Access Macros:
1878  *
1879  */
1880 /*
1881  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
1882  *
1883  * Software Enabled Individual Port Control
1884  */
1885 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1
1886 
1887 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1888 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6
1889 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1890 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6
1891 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1892 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1
1893 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1894 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
1895 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1896 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
1897 /* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1898 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1
1899 /* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
1900 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
1901 /* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
1902 #define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
1903 
1904 /*
1905  * Field : portd_single_ctl
1906  *
1907  * The value of this register is derived from the
1908  *
1909  * GPIO_PORTD_SINGLE_CTL configuration parameter.
1910  *
1911  * 0 = False
1912  *
1913  * 1 = True
1914  *
1915  * Field Enumeration Values:
1916  *
1917  * Enum | Value | Description
1918  * :-------------------------------------------------|:------|:-----------------------------------------
1919  * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1920  *
1921  * Field Access Macros:
1922  *
1923  */
1924 /*
1925  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
1926  *
1927  * Software Enabled Individual Port Control
1928  */
1929 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1
1930 
1931 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1932 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7
1933 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1934 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7
1935 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1936 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1
1937 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1938 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
1939 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1940 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
1941 /* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1942 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1
1943 /* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
1944 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
1945 /* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
1946 #define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
1947 
1948 /*
1949  * Field : hw_porta
1950  *
1951  * The value of this register is derived from the
1952  *
1953  * GPIO_HW_PORTA configuration parameter.
1954  *
1955  * 0 = Exclude
1956  *
1957  * 1 = Include
1958  *
1959  * Field Enumeration Values:
1960  *
1961  * Enum | Value | Description
1962  * :-----------------------------------------|:------|:---------------------------------------
1963  * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled
1964  *
1965  * Field Access Macros:
1966  *
1967  */
1968 /*
1969  * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
1970  *
1971  * Software Configuration Control Enabled
1972  */
1973 #define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0
1974 
1975 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1976 #define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8
1977 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1978 #define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8
1979 /* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1980 #define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1
1981 /* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1982 #define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100
1983 /* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1984 #define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
1985 /* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1986 #define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0
1987 /* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */
1988 #define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
1989 /* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
1990 #define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
1991 
1992 /*
1993  * Field : hw_portb
1994  *
1995  * The value of this register is derived from the
1996  *
1997  * GPIO_HW_PORTB configuration parameter.
1998  *
1999  * 0 = Exclude
2000  *
2001  * 1 = Include
2002  *
2003  * Field Access Macros:
2004  *
2005  */
2006 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTB register field. */
2007 #define ALT_GPIO_CFG_REG1_HW_PORTB_LSB 9
2008 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTB register field. */
2009 #define ALT_GPIO_CFG_REG1_HW_PORTB_MSB 9
2010 /* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTB register field. */
2011 #define ALT_GPIO_CFG_REG1_HW_PORTB_WIDTH 1
2012 /* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTB register field value. */
2013 #define ALT_GPIO_CFG_REG1_HW_PORTB_SET_MSK 0x00000200
2014 /* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTB register field value. */
2015 #define ALT_GPIO_CFG_REG1_HW_PORTB_CLR_MSK 0xfffffdff
2016 /* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTB register field. */
2017 #define ALT_GPIO_CFG_REG1_HW_PORTB_RESET 0x0
2018 /* Extracts the ALT_GPIO_CFG_REG1_HW_PORTB field value from a register. */
2019 #define ALT_GPIO_CFG_REG1_HW_PORTB_GET(value) (((value) & 0x00000200) >> 9)
2020 /* Produces a ALT_GPIO_CFG_REG1_HW_PORTB register field value suitable for setting the register. */
2021 #define ALT_GPIO_CFG_REG1_HW_PORTB_SET(value) (((value) << 9) & 0x00000200)
2022 
2023 /*
2024  * Field : hw_portc
2025  *
2026  * The value of this register is derived from the
2027  *
2028  * GPIO_HW_PORTC configuration parameter.
2029  *
2030  * 0 = Exclude
2031  *
2032  * 1 = Include
2033  *
2034  * Field Access Macros:
2035  *
2036  */
2037 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTC register field. */
2038 #define ALT_GPIO_CFG_REG1_HW_PORTC_LSB 10
2039 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTC register field. */
2040 #define ALT_GPIO_CFG_REG1_HW_PORTC_MSB 10
2041 /* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTC register field. */
2042 #define ALT_GPIO_CFG_REG1_HW_PORTC_WIDTH 1
2043 /* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTC register field value. */
2044 #define ALT_GPIO_CFG_REG1_HW_PORTC_SET_MSK 0x00000400
2045 /* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTC register field value. */
2046 #define ALT_GPIO_CFG_REG1_HW_PORTC_CLR_MSK 0xfffffbff
2047 /* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTC register field. */
2048 #define ALT_GPIO_CFG_REG1_HW_PORTC_RESET 0x0
2049 /* Extracts the ALT_GPIO_CFG_REG1_HW_PORTC field value from a register. */
2050 #define ALT_GPIO_CFG_REG1_HW_PORTC_GET(value) (((value) & 0x00000400) >> 10)
2051 /* Produces a ALT_GPIO_CFG_REG1_HW_PORTC register field value suitable for setting the register. */
2052 #define ALT_GPIO_CFG_REG1_HW_PORTC_SET(value) (((value) << 10) & 0x00000400)
2053 
2054 /*
2055  * Field : hw_portd
2056  *
2057  * The value of this register is derived from the
2058  *
2059  * GPIO_HW_PORTD configuration parameter.
2060  *
2061  * 0 = Exclude
2062  *
2063  * 1 = Include
2064  *
2065  * Field Access Macros:
2066  *
2067  */
2068 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTD register field. */
2069 #define ALT_GPIO_CFG_REG1_HW_PORTD_LSB 11
2070 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTD register field. */
2071 #define ALT_GPIO_CFG_REG1_HW_PORTD_MSB 11
2072 /* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTD register field. */
2073 #define ALT_GPIO_CFG_REG1_HW_PORTD_WIDTH 1
2074 /* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTD register field value. */
2075 #define ALT_GPIO_CFG_REG1_HW_PORTD_SET_MSK 0x00000800
2076 /* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTD register field value. */
2077 #define ALT_GPIO_CFG_REG1_HW_PORTD_CLR_MSK 0xfffff7ff
2078 /* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTD register field. */
2079 #define ALT_GPIO_CFG_REG1_HW_PORTD_RESET 0x0
2080 /* Extracts the ALT_GPIO_CFG_REG1_HW_PORTD field value from a register. */
2081 #define ALT_GPIO_CFG_REG1_HW_PORTD_GET(value) (((value) & 0x00000800) >> 11)
2082 /* Produces a ALT_GPIO_CFG_REG1_HW_PORTD register field value suitable for setting the register. */
2083 #define ALT_GPIO_CFG_REG1_HW_PORTD_SET(value) (((value) << 11) & 0x00000800)
2084 
2085 /*
2086  * Field : porta_intr
2087  *
2088  * The value of this register is derived from the
2089  *
2090  * GPIO_PORTA_INTR configuration parameter.
2091  *
2092  * 0 = Exclude
2093  *
2094  * 1 = Include
2095  *
2096  * Field Enumeration Values:
2097  *
2098  * Enum | Value | Description
2099  * :-------------------------------------------|:------|:--------------------------
2100  * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled
2101  *
2102  * Field Access Macros:
2103  *
2104  */
2105 /*
2106  * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
2107  *
2108  * Port A Interrupts Enabled
2109  */
2110 #define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1
2111 
2112 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
2113 #define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12
2114 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
2115 #define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12
2116 /* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
2117 #define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1
2118 /* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
2119 #define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000
2120 /* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
2121 #define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
2122 /* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
2123 #define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1
2124 /* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
2125 #define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
2126 /* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
2127 #define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
2128 
2129 /*
2130  * Field : debounce
2131  *
2132  * The value of this register is derived from the
2133  *
2134  * GPIO_DEBOUNCE configuration parameter.
2135  *
2136  * 0 = Exclude
2137  *
2138  * 1 = Include
2139  *
2140  * Field Enumeration Values:
2141  *
2142  * Enum | Value | Description
2143  * :---------------------------------------|:------|:--------------------
2144  * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled
2145  *
2146  * Field Access Macros:
2147  *
2148  */
2149 /*
2150  * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
2151  *
2152  * Debounce is Enabled
2153  */
2154 #define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1
2155 
2156 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
2157 #define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13
2158 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
2159 #define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13
2160 /* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
2161 #define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1
2162 /* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
2163 #define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000
2164 /* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
2165 #define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
2166 /* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
2167 #define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1
2168 /* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
2169 #define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
2170 /* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
2171 #define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
2172 
2173 /*
2174  * Field : add_encoded_params
2175  *
2176  * The value of this register is derived from the
2177  *
2178  * GPIO_ADD_ENCODED_PARAMS configuration parameter.
2179  *
2180  * 0 = False
2181  *
2182  * 1 = True
2183  *
2184  * Field Enumeration Values:
2185  *
2186  * Enum | Value | Description
2187  * :------------------------------------------------|:------|:--------------------------
2188  * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification
2189  *
2190  * Field Access Macros:
2191  *
2192  */
2193 /*
2194  * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
2195  *
2196  * Enable IP indentification
2197  */
2198 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
2199 
2200 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
2201 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14
2202 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
2203 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14
2204 /* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
2205 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1
2206 /* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
2207 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000
2208 /* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
2209 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff
2210 /* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
2211 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1
2212 /* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
2213 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
2214 /* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
2215 #define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
2216 
2217 /*
2218  * Field : gpio_id
2219  *
2220  * The value of this register is derived from the
2221  *
2222  * GPIO_ID configuration parameter.
2223  *
2224  * 0 = Exclude
2225  *
2226  * 1 = Include
2227  *
2228  * Field Enumeration Values:
2229  *
2230  * Enum | Value | Description
2231  * :-----------------------------------|:------|:-------------
2232  * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code
2233  *
2234  * Field Access Macros:
2235  *
2236  */
2237 /*
2238  * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
2239  *
2240  * GPIO ID Code
2241  */
2242 #define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1
2243 
2244 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
2245 #define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15
2246 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
2247 #define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15
2248 /* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
2249 #define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1
2250 /* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
2251 #define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000
2252 /* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
2253 #define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
2254 /* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
2255 #define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1
2256 /* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */
2257 #define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
2258 /* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
2259 #define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
2260 
2261 /*
2262  * Field : encoded_id_width
2263  *
2264  * The value of this register is derived from the
2265  *
2266  * GPIO_ID_WIDTH configuration parameter.
2267  *
2268  * Field Enumeration Values:
2269  *
2270  * Enum | Value | Description
2271  * :--------------------------------------------|:------|:------------------
2272  * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field
2273  *
2274  * Field Access Macros:
2275  *
2276  */
2277 /*
2278  * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
2279  *
2280  * Width of ID Field
2281  */
2282 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
2283 
2284 /* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
2285 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16
2286 /* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
2287 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20
2288 /* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
2289 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5
2290 /* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
2291 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000
2292 /* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
2293 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff
2294 /* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
2295 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f
2296 /* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
2297 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
2298 /* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
2299 #define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
2300 
2301 #ifndef __ASSEMBLY__
2302 /*
2303  * WARNING: The C register and register group struct declarations are provided for
2304  * convenience and illustrative purposes. They should, however, be used with
2305  * caution as the C language standard provides no guarantees about the alignment or
2306  * atomicity of device memory accesses. The recommended practice for writing
2307  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2308  * alt_write_word() functions.
2309  *
2310  * The struct declaration for register ALT_GPIO_CFG_REG1.
2311  */
2312 struct ALT_GPIO_CFG_REG1_s
2313 {
2314  const uint32_t apb_data_width : 2; /* ALT_GPIO_CFG_REG1_APB_DATA_WIDTH */
2315  const uint32_t num_ports : 2; /* ALT_GPIO_CFG_REG1_NUM_PORTS */
2316  const uint32_t porta_single_ctl : 1; /* ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL */
2317  const uint32_t portb_single_ctl : 1; /* ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL */
2318  const uint32_t portc_single_ctl : 1; /* ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL */
2319  const uint32_t portd_single_ctl : 1; /* ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL */
2320  const uint32_t hw_porta : 1; /* ALT_GPIO_CFG_REG1_HW_PORTA */
2321  const uint32_t hw_portb : 1; /* ALT_GPIO_CFG_REG1_HW_PORTB */
2322  const uint32_t hw_portc : 1; /* ALT_GPIO_CFG_REG1_HW_PORTC */
2323  const uint32_t hw_portd : 1; /* ALT_GPIO_CFG_REG1_HW_PORTD */
2324  const uint32_t porta_intr : 1; /* ALT_GPIO_CFG_REG1_PORTA_INTR */
2325  const uint32_t debounce : 1; /* ALT_GPIO_CFG_REG1_DEBOUNCE */
2326  const uint32_t add_encoded_params : 1; /* ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS */
2327  const uint32_t gpio_id : 1; /* ALT_GPIO_CFG_REG1_GPIO_ID */
2328  const uint32_t encoded_id_width : 5; /* ALT_GPIO_CFG_REG1_ENC_ID_WIDTH */
2329  uint32_t : 11; /* *UNDEFINED* */
2330 };
2331 
2332 /* The typedef declaration for register ALT_GPIO_CFG_REG1. */
2333 typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t;
2334 #endif /* __ASSEMBLY__ */
2335 
2336 /* The reset value of the ALT_GPIO_CFG_REG1 register. */
2337 #define ALT_GPIO_CFG_REG1_RESET 0x001ff0f2
2338 /* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */
2339 #define ALT_GPIO_CFG_REG1_OFST 0x74
2340 /* The address of the ALT_GPIO_CFG_REG1 register. */
2341 #define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST))
2342 
2343 #ifndef __ASSEMBLY__
2344 /*
2345  * WARNING: The C register and register group struct declarations are provided for
2346  * convenience and illustrative purposes. They should, however, be used with
2347  * caution as the C language standard provides no guarantees about the alignment or
2348  * atomicity of device memory accesses. The recommended practice for writing
2349  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2350  * alt_write_word() functions.
2351  *
2352  * The struct declaration for register group ALT_GPIO.
2353  */
2354 struct ALT_GPIO_s
2355 {
2356  ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
2357  ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
2358  volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
2359  ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */
2360  ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */
2361  ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
2362  ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
2363  ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
2364  ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
2365  ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
2366  ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
2367  ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
2368  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
2369  ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
2370  ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */
2371  volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
2372  ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
2373  ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
2374  ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
2375  volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
2376 };
2377 
2378 /* The typedef declaration for register group ALT_GPIO. */
2379 typedef volatile struct ALT_GPIO_s ALT_GPIO_t;
2380 /* The struct declaration for the raw register contents of register group ALT_GPIO. */
2381 struct ALT_GPIO_raw_s
2382 {
2383  volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
2384  volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
2385  uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
2386  volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */
2387  volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */
2388  volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
2389  volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
2390  volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
2391  volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
2392  volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
2393  volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
2394  volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
2395  uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
2396  volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
2397  volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */
2398  uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
2399  volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
2400  volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
2401  volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
2402  uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
2403 };
2404 
2405 /* The typedef declaration for the raw register contents of register group ALT_GPIO. */
2406 typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t;
2407 #endif /* __ASSEMBLY__ */
2408 
2409 
2410 #ifdef __cplusplus
2411 }
2412 #endif /* __cplusplus */
2413 #endif /* __ALT_SOCAL_GPIO_H__ */
2414