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20.1
Arria 10 SoC Hardware Manager
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alt_reset_manager.h
Go to the documentation of this file.
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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/*
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* $Id: //acds/rel/20.1std/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_reset_manager.h#1 $
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*/
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#ifndef __ALT_RESET_MGR_H__
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#define __ALT_RESET_MGR_H__
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#include "hwlib.h"
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#include <stdbool.h>
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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/******************************************************************************/
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/******************************************************************************/
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typedef
enum
ALT_RESET_EVENT_e
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{
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ALT_RESET_EVENT_PORVOLTRST
= 0x00000001,
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ALT_RESET_EVENT_NPORPINRST
= 0x00000002,
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ALT_RESET_EVENT_FPGACOLDRST
= 0x00000004,
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ALT_RESET_EVENT_CONFIGIOCOLDRST
= 0x00000008,
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ALT_RESET_EVENT_SWCOLDRST
= 0x00000010,
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ALT_RESET_EVENT_NRSTPINRST
= 0x00000100,
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ALT_RESET_EVENT_FPGAWARMRST
= 0x00000200,
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ALT_RESET_EVENT_SWWARMRST
= 0x00000400,
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ALT_RESET_EVENT_MPUWD0RST
= 0x00001000,
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ALT_RESET_EVENT_MPUWD1RST
= 0x00002000,
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ALT_RESET_EVENT_L4WD0RST
= 0x00004000,
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ALT_RESET_EVENT_L4WD1RST
= 0x00008000,
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ALT_RESET_EVENT_FPGADBGRST
= 0x00040000,
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ALT_RESET_EVENT_CDBGREQRST
= 0x00080000,
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ALT_RESET_EVENT_SDRSELFREFTIMEOUT
= 0x01000000,
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ALT_RESET_EVENT_FPGAMGRHSTIMEOUT
= 0x02000000,
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ALT_RESET_EVENT_SCANHSTIMEOUT
= 0x04000000,
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ALT_RESET_EVENT_FPGAHSTIMEOUT
= 0x08000000,
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ALT_RESET_EVENT_ETRSTALLTIMEOUT
= 0x10000000
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}
ALT_RESET_EVENT_t
;
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/******************************************************************************/
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uint32_t
alt_reset_event_get
(
void
);
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/******************************************************************************/
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ALT_STATUS_CODE
alt_reset_event_clear
(uint32_t event_mask);
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/******************************************************************************/
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/******************************************************************************/
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ALT_STATUS_CODE
alt_reset_cold_reset
(
void
);
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/******************************************************************************/
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ALT_STATUS_CODE
alt_reset_warm_reset
(uint32_t warm_reset_delay,
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uint32_t nRST_pin_clk_assertion,
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bool
sdram_refresh,
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bool
fpga_mgr_handshake,
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bool
scan_mgr_handshake,
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bool
fpga_handshake,
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bool
etr_stall);
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#if 0
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#endif
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#ifdef __cplusplus
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}
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#endif
/* __cplusplus */
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#endif
/* __ALT_RESET_MGR_H__ */
include
soc_cv_av
alt_reset_manager.h
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