Hardware Libraries  20.1
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alt_ethernet.h File Reference
#include "hwlib.h"
#include "socal/hps.h"
#include "socal/alt_emac.h"
#include "alt_interrupt.h"

Go to the source code of this file.

Detailed Description

Contains definitions for the Altera Hardware Libraries Ethernet Application Programming Interface

Data Structures

struct  alt_eth_dma_desc_t
 DMA descriptors types. More...
 
struct  ALT_ETH_EMAC_INSTANCE_s
 

Macros

#define ETH_DMATXDESC_OWN   ((uint32_t)0x80000000)
 Bit definition of TDES0 register: DMA Tx descriptor status register.
 
#define ETH_DMATXDESC_IC   ((uint32_t)0x40000000)
 
#define ETH_DMATXDESC_LS   ((uint32_t)0x20000000)
 
#define ETH_DMATXDESC_FS   ((uint32_t)0x10000000)
 
#define ETH_DMATXDESC_DC   ((uint32_t)0x08000000)
 
#define ETH_DMATXDESC_DP   ((uint32_t)0x04000000)
 
#define ETH_DMATXDESC_TTSE   ((uint32_t)0x02000000)
 
#define ETH_DMATXDESC_CIC   ((uint32_t)0x00C00000)
 
#define ETH_DMATXDESC_CIC_BYPASS   ((uint32_t)0x00000000)
 
#define ETH_DMATXDESC_CIC_IPV4HEADER   ((uint32_t)0x00400000)
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT   ((uint32_t)0x00800000)
 
#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL   ((uint32_t)0x00C00000)
 
#define ETH_DMATXDESC_TER   ((uint32_t)0x00200000)
 
#define ETH_DMATXDESC_TCH   ((uint32_t)0x00100000)
 
#define ETH_DMATXDESC_TTSS   ((uint32_t)0x00020000)
 
#define ETH_DMATXDESC_IHE   ((uint32_t)0x00010000)
 
#define ETH_DMATXDESC_ES   ((uint32_t)0x00008000)
 
#define ETH_DMATXDESC_JT   ((uint32_t)0x00004000)
 
#define ETH_DMATXDESC_FF   ((uint32_t)0x00002000)
 
#define ETH_DMATXDESC_PCE   ((uint32_t)0x00001000)
 
#define ETH_DMATXDESC_LCA   ((uint32_t)0x00000800)
 
#define ETH_DMATXDESC_NC   ((uint32_t)0x00000400)
 
#define ETH_DMATXDESC_LCO   ((uint32_t)0x00000200)
 
#define ETH_DMATXDESC_EC   ((uint32_t)0x00000100)
 
#define ETH_DMATXDESC_VF   ((uint32_t)0x00000080)
 
#define ETH_DMATXDESC_CC   ((uint32_t)0x00000078)
 
#define ETH_DMATXDESC_ED   ((uint32_t)0x00000004)
 
#define ETH_DMATXDESC_UF   ((uint32_t)0x00000002)
 
#define ETH_DMATXDESC_DB   ((uint32_t)0x00000001)
 
#define ETH_DMATXDESC_TBS2   ((uint32_t)0x1FFF0000)
 
#define ETH_DMATXDESC_TBS1   ((uint32_t)0x00001FFF)
 
#define ETH_DMATXDESC_B1AP   ((uint32_t)0xFFFFFFFF)
 
#define ETH_DMATXDESC_B2AP   ((uint32_t)0xFFFFFFFF)
 
#define ETH_DMARXDESC_OWN   ((uint32_t)0x80000000)
 
#define ETH_DMARXDESC_AFM   ((uint32_t)0x40000000)
 
#define ETH_DMARXDESC_FL   ((uint32_t)0x3FFF0000)
 
#define ETH_DMARXDESC_ES   ((uint32_t)0x00008000)
 
#define ETH_DMARXDESC_DE   ((uint32_t)0x00004000)
 
#define ETH_DMARXDESC_SAF   ((uint32_t)0x00002000)
 
#define ETH_DMARXDESC_LE   ((uint32_t)0x00001000)
 
#define ETH_DMARXDESC_OE   ((uint32_t)0x00000800)
 
#define ETH_DMARXDESC_VLAN   ((uint32_t)0x00000400)
 
#define ETH_DMARXDESC_FS   ((uint32_t)0x00000200)
 
#define ETH_DMARXDESC_LS   ((uint32_t)0x00000100)
 
#define ETH_DMARXDESC_IPV4HCE   ((uint32_t)0x00000080)
 
#define ETH_DMARXDESC_LC   ((uint32_t)0x00000040)
 
#define ETH_DMARXDESC_FT   ((uint32_t)0x00000020)
 
#define ETH_DMARXDESC_RWT   ((uint32_t)0x00000010)
 
#define ETH_DMARXDESC_RE   ((uint32_t)0x00000008)
 
#define ETH_DMARXDESC_DBE   ((uint32_t)0x00000004)
 
#define ETH_DMARXDESC_CE   ((uint32_t)0x00000002)
 
#define ETH_DMARXDESC_MAMPCE   ((uint32_t)0x00000001)
 
#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)
 
#define ETH_DMARXDESC_RBS2   ((uint32_t)0x1FFF0000)
 
#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)
 
#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)
 
#define ETH_DMARXDESC_RBS1   ((uint32_t)0x00001FFF)
 
#define ETH_DMARXDESC_B1AP   ((uint32_t)0xFFFFFFFF)
 
#define ETH_DMARXDESC_B2AP   ((uint32_t)0xFFFFFFFF)
 

Typedefs

typedef struct
ALT_ETH_EMAC_INSTANCE_s 
alt_eth_emac_instance_t
 

Functions

void alt_eth_delay (volatile uint32_t delay)
 
void alt_eth_reset_mac (uint32_t instance)
 
void alt_eth_setup_rxdesc (alt_eth_emac_instance_t *emac)
 
void alt_eth_setup_txdesc (alt_eth_emac_instance_t *emac)
 
ALT_STATUS_CODE alt_eth_irq_init (alt_eth_emac_instance_t *emac, alt_int_callback_t callback)
 
void alt_eth_irq_callback (uint32_t icciar, void *context)
 
ALT_STATUS_CODE alt_eth_software_reset (uint32_t instance)
 
void alt_eth_start (uint32_t instance)
 
void alt_eth_stop (uint32_t instance)
 
ALT_STATUS_CODE alt_eth_dma_mac_config (alt_eth_emac_instance_t *emac)
 
ALT_STATUS_CODE alt_eth_send_packet (uint8_t *pkt, uint32_t len, uint32_t first, uint32_t last, alt_eth_emac_instance_t *emac)
 
ALT_STATUS_CODE alt_eth_get_packet (uint8_t *pkt, uint32_t *len, alt_eth_emac_instance_t *emac)
 
void alt_eth_mac_set_tx_state (alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
void alt_eth_mac_set_rx_state (alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
void alt_eth_mac_set_bpa_state (alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
alt_eth_enable_disable_state_t alt_eth_mac_get_bpa_state (uint32_t instance)
 
void alt_eth_mac_set_irq_reg (uint32_t mac_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
alt_eth_set_reset_state_t alt_eth_mac_get_mii_link_state (uint32_t instance)
 
alt_eth_set_reset_state_t alt_eth_mac_check_status_reg (uint32_t mac_bit_mask, uint32_t instance)
 
uint32_t alt_eth_mac_get_irq_status_reg (uint32_t instance)
 
void alt_eth_mac_pause_ctrl_frame (uint32_t instance)
 
void alt_eth_mac_set_mac_addr (uint8_t *address, uint32_t instance)
 
void alt_eth_mac_get_mac_addr (uint8_t *address, uint32_t instance)
 
void alt_eth_mac_check_mii_link_status (uint32_t instance)
 
uint32_t alt_eth_dma_get_status_reg (uint32_t instance)
 
alt_eth_set_reset_state_t alt_eth_dma_check_status_reg (uint32_t dma_bit_mask, uint32_t instance)
 
void alt_eth_dma_clear_status_bits (uint32_t dma_bit_mask, uint32_t instance)
 
void alt_eth_dma_flush_tx_fifo (uint32_t instance)
 
alt_eth_set_reset_state_t alt_eth_dma_get_tx_fifo_flush_state (uint32_t instance)
 
void alt_eth_dma_set_tx_state (alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
void alt_eth_dma_set_rx_state (alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
void alt_eth_dma_set_irq_reg (uint32_t dma_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance)
 
alt_eth_set_reset_state_t alt_eth_dma_check_overflow_counter_reg (uint32_t dma_overflow_mask, uint32_t instance)
 
uint32_t alt_eth_dma_get_curr_tx_desc_addr (uint32_t instance)
 
uint32_t alt_eth_dma_get_curr_rx_desc_addr (uint32_t instance)
 
uint32_t alt_eth_dma_get_curr_tx_buff_addr (uint32_t instance)
 
uint32_t alt_eth_dma_get_curr_rx_buff_addr (uint32_t instance)
 
void alt_eth_dma_set_tx_desc_addr (uint32_t tx_desc_list_addr, uint32_t instance)
 
void alt_eth_dma_set_rx_desc_addr (uint32_t rx_desc_list_addr, uint32_t instance)
 
void alt_eth_dma_resume_dma_tx (uint32_t instance)
 
void alt_eth_dma_resume_dma_rx (uint32_t instance)
 
ALT_STATUS_CODE alt_eth_phy_config (uint32_t instance)
 
ALT_STATUS_CODE alt_eth_phy_reset (uint32_t instance)
 
ALT_STATUS_CODE alt_eth_phy_get_duplex_and_speed (uint32_t *phy_duplex_status, uint32_t *phy_speed, uint32_t instance)
 

Data Structure Documentation

struct alt_eth_dma_desc_t

DMA descriptors types.


--------------------------------------------------------------------—— ETH DMA Descriptors data structure definition

Data Fields
uint32_t status Status
uint32_t control_buffer_size Control and Buffer1, Buffer2 sizes
uint32_t buffer1_addr Buffer1 address pointer
uint32_t buffer2_next_desc_addr Buffer2 or next desc address pointer
struct ALT_ETH_EMAC_INSTANCE_s

This type definition defines the structure that must be passed into various Ethernet API functions. This structure must be allocated by the application program. This structure allows using the Ethernet API with more than one instance. After the application program allocates this structure, the instance variable must be set to the desired EMAC, 0,1, or 2. The other variables are maintained by the Ethernet API and do not have to be set by the application program.

Macro Definition Documentation

#define ETH_DMATXDESC_OWN   ((uint32_t)0x80000000)

Bit definition of TDES0 register: DMA Tx descriptor status register.

DMA Tx Desciptor

TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |

TDES2 | Buffer1 Address [31:0] |

TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |

OWN bit: descriptor is owned by DMA engine

#define ETH_DMATXDESC_IC   ((uint32_t)0x40000000)

Interrupt on Completion

#define ETH_DMATXDESC_LS   ((uint32_t)0x20000000)

Last Segment

#define ETH_DMATXDESC_FS   ((uint32_t)0x10000000)

First Segment

#define ETH_DMATXDESC_DC   ((uint32_t)0x08000000)

Disable CRC

#define ETH_DMATXDESC_DP   ((uint32_t)0x04000000)

Disable Padding

#define ETH_DMATXDESC_TTSE   ((uint32_t)0x02000000)

Transmit Time Stamp Enable

#define ETH_DMATXDESC_CIC   ((uint32_t)0x00C00000)

Checksum Insertion Control: 4 cases

#define ETH_DMATXDESC_CIC_BYPASS   ((uint32_t)0x00000000)

Do Nothing: Checksum Engine is bypassed

#define ETH_DMATXDESC_CIC_IPV4HEADER   ((uint32_t)0x00400000)

IPV4 header Checksum Insertion

#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT   ((uint32_t)0x00800000)

TCP/UDP/ICMP Checksum Insertion calculated over segment only

#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL   ((uint32_t)0x00C00000)

TCP/UDP/ICMP Checksum Insertion fully calculated

#define ETH_DMATXDESC_TER   ((uint32_t)0x00200000)

Transmit End of Ring

#define ETH_DMATXDESC_TCH   ((uint32_t)0x00100000)

Second Address Chained

#define ETH_DMATXDESC_TTSS   ((uint32_t)0x00020000)

Tx Time Stamp Status

#define ETH_DMATXDESC_IHE   ((uint32_t)0x00010000)

IP Header Error

#define ETH_DMATXDESC_ES   ((uint32_t)0x00008000)

Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT

#define ETH_DMATXDESC_JT   ((uint32_t)0x00004000)

Jabber Timeout

#define ETH_DMATXDESC_FF   ((uint32_t)0x00002000)

Frame Flushed: DMA/MTL flushed the frame due to SW flush

#define ETH_DMATXDESC_PCE   ((uint32_t)0x00001000)

Payload Checksum Error

#define ETH_DMATXDESC_LCA   ((uint32_t)0x00000800)

Loss of Carrier: carrier lost during transmission

#define ETH_DMATXDESC_NC   ((uint32_t)0x00000400)

No Carrier: no carrier signal from the transceiver

#define ETH_DMATXDESC_LCO   ((uint32_t)0x00000200)

Late Collision: transmission aborted due to collision

#define ETH_DMATXDESC_EC   ((uint32_t)0x00000100)

Excessive Collision: transmission aborted after 16 collisions

#define ETH_DMATXDESC_VF   ((uint32_t)0x00000080)

VLAN Frame

#define ETH_DMATXDESC_CC   ((uint32_t)0x00000078)

Collision Count

#define ETH_DMATXDESC_ED   ((uint32_t)0x00000004)

Excessive Deferral

#define ETH_DMATXDESC_UF   ((uint32_t)0x00000002)

Underflow Error: late data arrival from the memory

#define ETH_DMATXDESC_DB   ((uint32_t)0x00000001)

Deferred Bit

#define ETH_DMATXDESC_TBS2   ((uint32_t)0x1FFF0000)

Transmit Buffer2 Size

#define ETH_DMATXDESC_TBS1   ((uint32_t)0x00001FFF)

Transmit Buffer1 Size

#define ETH_DMATXDESC_B1AP   ((uint32_t)0xFFFFFFFF)

Buffer1 Address Pointer

#define ETH_DMATXDESC_B2AP   ((uint32_t)0xFFFFFFFF)

Buffer2 Address Pointer

#define ETH_DMARXDESC_OWN   ((uint32_t)0x80000000)

DMA Rx Descriptor

RDES0 | OWN(31) | Status [30:0] |

RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |

RDES2 | Buffer1 Address [31:0] |

RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |

OWN bit: descriptor is owned by DMA engine

#define ETH_DMARXDESC_AFM   ((uint32_t)0x40000000)

DA Filter Fail for the rx frame

#define ETH_DMARXDESC_FL   ((uint32_t)0x3FFF0000)

Receive descriptor frame length

#define ETH_DMARXDESC_ES   ((uint32_t)0x00008000)

Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE

#define ETH_DMARXDESC_DE   ((uint32_t)0x00004000)

Descriptor error: no more descriptors for receive frame

#define ETH_DMARXDESC_SAF   ((uint32_t)0x00002000)

SA Filter Fail for the received frame

#define ETH_DMARXDESC_LE   ((uint32_t)0x00001000)

Frame size not matching with length field

#define ETH_DMARXDESC_OE   ((uint32_t)0x00000800)

Overflow Error: Frame was damaged due to buffer overflow

#define ETH_DMARXDESC_VLAN   ((uint32_t)0x00000400)

VLAN Tag: received frame is a VLAN frame

#define ETH_DMARXDESC_FS   ((uint32_t)0x00000200)

First descriptor of the frame

#define ETH_DMARXDESC_LS   ((uint32_t)0x00000100)

Last descriptor of the frame

#define ETH_DMARXDESC_IPV4HCE   ((uint32_t)0x00000080)

IPC Checksum Error: Rx Ipv4 header checksum error

#define ETH_DMARXDESC_LC   ((uint32_t)0x00000040)

Late collision occurred during reception

#define ETH_DMARXDESC_FT   ((uint32_t)0x00000020)

Frame type - Ethernet, otherwise 802.3

#define ETH_DMARXDESC_RWT   ((uint32_t)0x00000010)

Receive Watchdog Timeout: watchdog timer expired during reception

#define ETH_DMARXDESC_RE   ((uint32_t)0x00000008)

Receive error: error reported by MII interface

#define ETH_DMARXDESC_DBE   ((uint32_t)0x00000004)

Dribble bit error: frame contains non int multiple of 8 bits

#define ETH_DMARXDESC_CE   ((uint32_t)0x00000002)

CRC error

#define ETH_DMARXDESC_MAMPCE   ((uint32_t)0x00000001)

Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error

#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)

Disable Interrupt on Completion

#define ETH_DMARXDESC_RBS2   ((uint32_t)0x1FFF0000)

Receive Buffer2 Size

#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)

Receive End of Ring

#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)

Second Address Chained

#define ETH_DMARXDESC_RBS1   ((uint32_t)0x00001FFF)

Receive Buffer1 Size

#define ETH_DMARXDESC_B1AP   ((uint32_t)0xFFFFFFFF)

Buffer1 Address Pointer

#define ETH_DMARXDESC_B2AP   ((uint32_t)0xFFFFFFFF)

Buffer2 Address Pointer

Typedef Documentation

This type definition defines the structure that must be passed into various Ethernet API functions. This structure must be allocated by the application program. This structure allows using the Ethernet API with more than one instance. After the application program allocates this structure, the instance variable must be set to the desired EMAC, 0,1, or 2. The other variables are maintained by the Ethernet API and do not have to be set by the application program.

Function Documentation

void alt_eth_delay ( volatile uint32_t  delay)

A simple delay function which loops until the specified count is reached.

Parameters
delayThe number to count to.
void alt_eth_reset_mac ( uint32_t  instance)

Reset the EMAC, Disable the FPGA Interface, and set the PHY mode to RGMII

Parameters
instanceThe EMAC instance 0,1, or 2.
void alt_eth_setup_rxdesc ( alt_eth_emac_instance_t emac)

Initalizes the RX Descriptor ring

Parameters
emacThe application allocated EMAC instance structure.
void alt_eth_setup_txdesc ( alt_eth_emac_instance_t emac)

Initalizes the TX Descriptor ring

Parameters
emacThe application allocated EMAC instance structure.
ALT_STATUS_CODE alt_eth_irq_init ( alt_eth_emac_instance_t emac,
alt_int_callback_t  callback 
)

Initializes the Ethernet IRQ handler

Parameters
emacThe application allocated EMAC instance structure.
callbackThe function to call when an interrupt is recieved.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
void alt_eth_irq_callback ( uint32_t  icciar,
void *  context 
)

The Ethernet IRQ Callback function This IRQ Handler is used for rx and tx stats only as the Ethernet API is operated in a polled mode.

The IRQ handler is initialized to use this function in the alt_eth_dma_mac_config function.

Parameters
icciarThe Interrupt controller CPU interrupt
contextThe application allocated EMAC instance structure.
ALT_STATUS_CODE alt_eth_software_reset ( uint32_t  instance)

Set the SWR bit: resets all MAC subsystem internal registers and logic

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
void alt_eth_start ( uint32_t  instance)

Start the receive and transmit DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
void alt_eth_stop ( uint32_t  instance)

Stop the receive and transmit DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
ALT_STATUS_CODE alt_eth_dma_mac_config ( alt_eth_emac_instance_t emac)

This is the main configuration routine. This routine sets up the PHY, EMAC, and DMA and starts the DMA rx and tx.

For an application to initialize and use Ethernet 1) Allocate the alt_eth_emac_instance_t structure. 2) Set the structure instance variable to the EMAC you want to use 3) Call this function. 4) Use the alt_eth_send_packet and alt_eth_get_packet functions to send and get packets.

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_eth_send_packet ( uint8_t *  pkt,
uint32_t  len,
uint32_t  first,
uint32_t  last,
alt_eth_emac_instance_t emac 
)

Sends a Packet to the Ethernet Interface

Parameters
pktThe array containing the packet to send.
lenThe length of the data to send in bytes.
firstThis indicates if this is the first packet in a frame.
lastThis indicates if this is the last packet in a frame.
emacThe application allocated EMAC instance structure.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed.
ALT_STATUS_CODE alt_eth_get_packet ( uint8_t *  pkt,
uint32_t *  len,
alt_eth_emac_instance_t emac 
)

Gets a Packet from the Ethernet Interface

Parameters
pktThe array to recieve the packet.
lenThe size of the pkt received.
emacThe application allocated EMAC instance structure.
Return values
ALT_E_SUCCESSThe operation was successful.
ALT_E_ERRORThe operation failed, no packet returned. Note the failure code is also used when no packet is available from the interface.
void alt_eth_mac_set_tx_state ( alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable Mac Transmission

Parameters
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
void alt_eth_mac_set_rx_state ( alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable Mac Reception

Parameters
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
void alt_eth_mac_set_bpa_state ( alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable the MAC BackPressure operation In Half duplex: during backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision

Parameters
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
alt_eth_enable_disable_state_t alt_eth_mac_get_bpa_state ( uint32_t  instance)

Get the Backpressure Activate state

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_ENABLEEnabled
ALT_ETH_DISABLEDisabled
void alt_eth_mac_set_irq_reg ( uint32_t  mac_irq_mask,
alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable the selected ETHERNET MAC interrupts

Parameters
mac_irq_maskThe mask of the desired IRQ(s).
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
alt_eth_set_reset_state_t alt_eth_mac_get_mii_link_state ( uint32_t  instance)

Get the link state

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETThe link is down
ALT_ETH_SETThe link is up
alt_eth_set_reset_state_t alt_eth_mac_check_status_reg ( uint32_t  mac_bit_mask,
uint32_t  instance 
)

check the gmac int status bits specified by mask

Parameters
mac_bit_maskmask of the gmac int status bits to check
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETNo bits in the mask are set
ALT_ETH_SETAt least one bit in the mask is set
uint32_t alt_eth_mac_get_irq_status_reg ( uint32_t  instance)

Gets the gmac int status register value

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe gmac int status register value
void alt_eth_mac_pause_ctrl_frame ( uint32_t  instance)

Initiates mac pause control frame This is only valid in full duplex mode

Parameters
instanceThe EMAC instance 0,1, or 2.
void alt_eth_mac_set_mac_addr ( uint8_t *  address,
uint32_t  instance 
)

Sets the mac address specified

Parameters
address8 bit array containing the mac address to set where address[5] is the high order mac byte.
instanceThe EMAC instance 0,1, or 2.
void alt_eth_mac_get_mac_addr ( uint8_t *  address,
uint32_t  instance 
)

Gets the mac address

Parameters
address8 bit array to recieve the 5 byte mac address where address[5] is the high order mac byte.
instanceThe EMAC instance 0,1, or 2.
void alt_eth_mac_check_mii_link_status ( uint32_t  instance)

Checks the PHY link status and if changed renegotiates the link

Parameters
instanceThe EMAC instance 0,1, or 2.
uint32_t alt_eth_dma_get_status_reg ( uint32_t  instance)

Get the dma status register value

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe value of the dma irq stat register
alt_eth_set_reset_state_t alt_eth_dma_check_status_reg ( uint32_t  dma_bit_mask,
uint32_t  instance 
)

Checks the specified bits in the dma status reg

Parameters
dma_bit_maskmask of the dma status bits to check
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETNo bits in the mask are set
ALT_ETH_SETAt least one bit in the mask is set
void alt_eth_dma_clear_status_bits ( uint32_t  dma_bit_mask,
uint32_t  instance 
)

Clear bits in the dma status reg

Parameters
dma_bit_maskmask of the dma int status bits to clear
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETNo bits in the mask are set
ALT_ETH_SETAt least one bit in the mask is set
void alt_eth_dma_flush_tx_fifo ( uint32_t  instance)

Flush the tx fifo

Parameters
instanceThe EMAC instance 0,1, or 2.
alt_eth_set_reset_state_t alt_eth_dma_get_tx_fifo_flush_state ( uint32_t  instance)

Get the tx fifo flush state

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETTx fifo flush is complete
ALT_ETH_SETTx fifo flush is in progress
void alt_eth_dma_set_tx_state ( alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable the TX DMA

Parameters
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
void alt_eth_dma_set_rx_state ( alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable the RX DMA

Parameters
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
void alt_eth_dma_set_irq_reg ( uint32_t  dma_irq_mask,
alt_eth_enable_disable_state_t  new_state,
uint32_t  instance 
)

Enable or Disable the selected DMA interrupts

Parameters
dma_irq_maskThe mask of the desired IRQ(s).
new_stateALT_ETH_ENABLE or ALT_ETH_DISABLE
instanceThe EMAC instance 0,1, or 2.
alt_eth_set_reset_state_t alt_eth_dma_check_overflow_counter_reg ( uint32_t  dma_overflow_mask,
uint32_t  instance 
)

Check the state of bits in the DMA overflow counter register

Parameters
dma_overflow_maskThe mask of the desired bits to check.
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_ETH_RESETNo bits specified by the mask are set
ALT_ETH_SETAt least 1 bit specified by the mask is set
uint32_t alt_eth_dma_get_curr_tx_desc_addr ( uint32_t  instance)

Get the address of the current Transmit Descriptor being read by the DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe tx address
uint32_t alt_eth_dma_get_curr_rx_desc_addr ( uint32_t  instance)

Get the address of the current Receive Descriptor being read by the DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe rx address
uint32_t alt_eth_dma_get_curr_tx_buff_addr ( uint32_t  instance)

Get the address of the current Transmit buffer address being read by the DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe tx buf address
uint32_t alt_eth_dma_get_curr_rx_buff_addr ( uint32_t  instance)

Get the address of the current Receive buffer address being read by the DMA

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe rx buf address
void alt_eth_dma_set_tx_desc_addr ( uint32_t  tx_desc_list_addr,
uint32_t  instance 
)

Set the start address of the Transmit Descriptor list

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe tx list address
void alt_eth_dma_set_rx_desc_addr ( uint32_t  rx_desc_list_addr,
uint32_t  instance 
)

Set the start address of the Receive Descriptor list

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
uint32_tThe rx list address
void alt_eth_dma_resume_dma_tx ( uint32_t  instance)

Resume TX DMA operations suspended by underflow or no available descriptor

Parameters
instanceThe EMAC instance 0,1, or 2.
void alt_eth_dma_resume_dma_rx ( uint32_t  instance)

Resume RX DMA operations suspended by no available descriptor

Parameters
instanceThe EMAC instance 0,1, or 2.
ALT_STATUS_CODE alt_eth_phy_config ( uint32_t  instance)

Configure the phy This routine is contained in a separate phy file that must be included in the build. This is one of the 3 functions comprising the software interface between the phy and the alt_ethernet files. To use a different phy simply include the proper phy c file in the build.

This routine must initialize the phy, bring the link up, and complete negotiation. The phy instance is derived from the emac instance via a lookup table in the phy .h file.

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_E_SUCCESSPhy configuration was successful.
ALT_E_ERRORPhy configuration failed.
ALT_STATUS_CODE alt_eth_phy_reset ( uint32_t  instance)

Reset the phy This routine is contained in a separate phy file that must be included in the build. This is one of the 3 functions comprising the software interface between the phy and the alt_ethernet files. To use a different phy simply include the proper phy c file in the build.

The phy instance is derived from the emac instance via a lookup table in the phy .h file.

Parameters
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_E_SUCCESSPhy reset successful.
ALT_E_ERRORPhy reset failed.
ALT_STATUS_CODE alt_eth_phy_get_duplex_and_speed ( uint32_t *  phy_duplex_status,
uint32_t *  phy_speed,
uint32_t  instance 
)

Get phy duplex and speed As a result of the alt_eth_phy_config phy negotiation, a certain phy speed and duplex was obtained. This function returns those values.

This routine is contained in a separate phy file that must be included in the build. This is one of the 3 functions comprising the software interface between the phy and the alt_ethernet files. To use a different phy simply include the proper phy c file in the build.

The phy instance is derived from the emac instance via a lookup table in the phy .h file.

Parameters
phy_duplex_statusreturns 1 for Duplex Mode is set, 0 for Duplex mode is not set
phy_speedreturns 10, 100, or 1000
instanceThe EMAC instance 0,1, or 2.
Return values
ALT_E_SUCCESSPhy duplex and speed obtained successfully
ALT_E_ERRORPhy duplex and speed query failed