Hardware Libraries  20.1
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alt_clkmgr_mainpll.h
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32 
33 /* Altera - ALT_CLKMGR_MAINPLL */
34 
35 #ifndef __ALT_SOCAL_CLKMGR_MAINPLL_H__
36 #define __ALT_SOCAL_CLKMGR_MAINPLL_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Main PLL Group - CLKMGR_MAINPLL
50  * Main PLL Group
51  *
52  * Contains registers with settings for the Main PLL.
53  *
54  */
55 /*
56  * Register : Enable Register - en
57  *
58  * Contains fields that control clock enables for Main Clocks.
59  *
60  * 1: The clock is enabled.
61  *
62  * 0: The clock is disabled.
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :-------|:-------|:------|:-----------------------
68  * [0] | RW | 0x1 | MPU Clock Group Enable
69  * [1] | RW | 0x1 | l4_main_clk Enable
70  * [2] | RW | 0x1 | l4_mp_clk Enable
71  * [3] | RW | 0x1 | l4_sp_clk Enable
72  * [4] | RW | 0x1 | Debug Group Enable
73  * [5] | RW | 0x1 | Debug Timer Enable
74  * [6] | RW | 0x1 | s2f_user0_clk Enable
75  * [31:7] | ??? | 0x1 | *UNDEFINED*
76  *
77  */
78 /*
79  * Field : MPU Clock Group Enable - mpuclken
80  *
81  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
82  *
83  * Field Access Macros:
84  *
85  */
86 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
87 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_LSB 0
88 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
89 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_MSB 0
90 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
91 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_WIDTH 1
92 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value. */
93 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET_MSK 0x00000001
94 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value. */
95 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_CLR_MSK 0xfffffffe
96 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field. */
97 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_RESET 0x1
98 /* Extracts the ALT_CLKMGR_MAINPLL_EN_MPUCLKEN field value from a register. */
99 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
100 /* Produces a ALT_CLKMGR_MAINPLL_EN_MPUCLKEN register field value suitable for setting the register. */
101 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
102 
103 /*
104  * Field : l4_main_clk Enable - l4mainclken
105  *
106  * Enables clock l4_main_clk output
107  *
108  * Field Access Macros:
109  *
110  */
111 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
112 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_LSB 1
113 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
114 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_MSB 1
115 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
116 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_WIDTH 1
117 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value. */
118 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET_MSK 0x00000002
119 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value. */
120 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_CLR_MSK 0xfffffffd
121 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field. */
122 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_RESET 0x1
123 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN field value from a register. */
124 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
125 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN register field value suitable for setting the register. */
126 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
127 
128 /*
129  * Field : l4_mp_clk Enable - l4mpclken
130  *
131  * Enables clock l4_mp_clk output
132  *
133  * Field Access Macros:
134  *
135  */
136 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
137 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_LSB 2
138 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
139 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_MSB 2
140 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
141 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_WIDTH 1
142 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value. */
143 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET_MSK 0x00000004
144 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value. */
145 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_CLR_MSK 0xfffffffb
146 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field. */
147 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_RESET 0x1
148 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN field value from a register. */
149 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
150 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN register field value suitable for setting the register. */
151 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
152 
153 /*
154  * Field : l4_sp_clk Enable - l4spclken
155  *
156  * Enables clock l4_sp_clk output
157  *
158  * Field Access Macros:
159  *
160  */
161 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
162 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_LSB 3
163 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
164 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_MSB 3
165 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
166 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_WIDTH 1
167 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value. */
168 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET_MSK 0x00000008
169 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value. */
170 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_CLR_MSK 0xfffffff7
171 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field. */
172 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_RESET 0x1
173 /* Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN field value from a register. */
174 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
175 /* Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN register field value suitable for setting the register. */
176 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
177 
178 /*
179  * Field : Debug Group Enable - csclken
180  *
181  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk, and cs_trace_clk)
182  *
183  * Field Access Macros:
184  *
185  */
186 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
187 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_LSB 4
188 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
189 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_MSB 4
190 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
191 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_WIDTH 1
192 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value. */
193 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET_MSK 0x00000010
194 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value. */
195 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_CLR_MSK 0xffffffef
196 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field. */
197 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_RESET 0x1
198 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CSCLKEN field value from a register. */
199 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
200 /* Produces a ALT_CLKMGR_MAINPLL_EN_CSCLKEN register field value suitable for setting the register. */
201 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
202 
203 /*
204  * Field : Debug Timer Enable - cstimerclken
205  *
206  * Enables Debug Timer Clock output (cs_timer_clk)
207  *
208  * Field Access Macros:
209  *
210  */
211 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field. */
212 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_LSB 5
213 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field. */
214 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_MSB 5
215 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field. */
216 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_WIDTH 1
217 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field value. */
218 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_SET_MSK 0x00000020
219 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field value. */
220 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_CLR_MSK 0xffffffdf
221 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field. */
222 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_RESET 0x1
223 /* Extracts the ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN field value from a register. */
224 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_GET(value) (((value) & 0x00000020) >> 5)
225 /* Produces a ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN register field value suitable for setting the register. */
226 #define ALT_CLKMGR_MAINPLL_EN_CSTIMERCLKEN_SET(value) (((value) << 5) & 0x00000020)
227 
228 /*
229  * Field : s2f_user0_clk Enable - s2fuser0clken
230  *
231  * Enables clock s2f_user0_clk output
232  *
233  * Field Access Macros:
234  *
235  */
236 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
237 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_LSB 6
238 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
239 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_MSB 6
240 /* The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
241 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_WIDTH 1
242 /* The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value. */
243 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040
244 /* The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value. */
245 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
246 /* The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field. */
247 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_RESET 0x1
248 /* Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN field value from a register. */
249 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
250 /* Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN register field value suitable for setting the register. */
251 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
252 
253 #ifndef __ASSEMBLY__
254 /*
255  * WARNING: The C register and register group struct declarations are provided for
256  * convenience and illustrative purposes. They should, however, be used with
257  * caution as the C language standard provides no guarantees about the alignment or
258  * atomicity of device memory accesses. The recommended practice for coding device
259  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
260  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
261  * alt_write_dword() functions for 64 bit registers.
262  *
263  * The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
264  */
265 struct ALT_CLKMGR_MAINPLL_EN_s
266 {
267  volatile uint32_t mpuclken : 1; /* MPU Clock Group Enable */
268  volatile uint32_t l4mainclken : 1; /* l4_main_clk Enable */
269  volatile uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
270  volatile uint32_t l4spclken : 1; /* l4_sp_clk Enable */
271  volatile uint32_t csclken : 1; /* Debug Group Enable */
272  volatile uint32_t cstimerclken : 1; /* Debug Timer Enable */
273  volatile uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
274  uint32_t : 25; /* *UNDEFINED* */
275 };
276 
277 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_EN. */
278 typedef struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t;
279 #endif /* __ASSEMBLY__ */
280 
281 /* The reset value of the ALT_CLKMGR_MAINPLL_EN register. */
282 #define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
283 /* The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component. */
284 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x0
285 
286 /*
287  * Register : Enable Set Register - ens
288  *
289  * Write One to Set correspondng fields in the Enable Register.
290  *
291  * Register Layout
292  *
293  * Bits | Access | Reset | Description
294  * :-------|:-------|:------|:-----------------------
295  * [0] | RW | 0x1 | MPU Clock Group Enable
296  * [1] | RW | 0x1 | l4_main_clk Enable
297  * [2] | RW | 0x1 | l4_mp_clk Enable
298  * [3] | RW | 0x1 | l4_sp_clk Enable
299  * [4] | RW | 0x1 | Debug Group Enable
300  * [5] | RW | 0x1 | Debug Timer Enable
301  * [6] | RW | 0x1 | s2f_user0_clk Enable
302  * [31:7] | ??? | 0x1 | *UNDEFINED*
303  *
304  */
305 /*
306  * Field : MPU Clock Group Enable - mpuclken
307  *
308  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
309  *
310  * Field Access Macros:
311  *
312  */
313 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
314 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_LSB 0
315 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
316 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_MSB 0
317 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
318 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_WIDTH 1
319 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value. */
320 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET_MSK 0x00000001
321 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value. */
322 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_CLR_MSK 0xfffffffe
323 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field. */
324 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_RESET 0x1
325 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN field value from a register. */
326 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
327 /* Produces a ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN register field value suitable for setting the register. */
328 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
329 
330 /*
331  * Field : l4_main_clk Enable - l4mainclken
332  *
333  * Enables clock l4_main_clk output
334  *
335  * Field Access Macros:
336  *
337  */
338 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
339 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_LSB 1
340 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
341 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_MSB 1
342 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
343 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_WIDTH 1
344 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value. */
345 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET_MSK 0x00000002
346 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value. */
347 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_CLR_MSK 0xfffffffd
348 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field. */
349 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_RESET 0x1
350 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN field value from a register. */
351 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
352 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN register field value suitable for setting the register. */
353 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
354 
355 /*
356  * Field : l4_mp_clk Enable - l4mpclken
357  *
358  * Enables clock l4_mp_clk output
359  *
360  * Field Access Macros:
361  *
362  */
363 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
364 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_LSB 2
365 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
366 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_MSB 2
367 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
368 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_WIDTH 1
369 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value. */
370 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET_MSK 0x00000004
371 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value. */
372 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_CLR_MSK 0xfffffffb
373 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field. */
374 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_RESET 0x1
375 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN field value from a register. */
376 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
377 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN register field value suitable for setting the register. */
378 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
379 
380 /*
381  * Field : l4_sp_clk Enable - l4spclken
382  *
383  * Enables clock l4_sp_clk output
384  *
385  * Field Access Macros:
386  *
387  */
388 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
389 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_LSB 3
390 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
391 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_MSB 3
392 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
393 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_WIDTH 1
394 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value. */
395 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET_MSK 0x00000008
396 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value. */
397 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_CLR_MSK 0xfffffff7
398 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field. */
399 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_RESET 0x1
400 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN field value from a register. */
401 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
402 /* Produces a ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN register field value suitable for setting the register. */
403 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
404 
405 /*
406  * Field : Debug Group Enable - csclken
407  *
408  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)
409  *
410  * Field Access Macros:
411  *
412  */
413 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
414 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_LSB 4
415 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
416 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_MSB 4
417 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
418 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_WIDTH 1
419 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value. */
420 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET_MSK 0x00000010
421 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value. */
422 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_CLR_MSK 0xffffffef
423 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field. */
424 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_RESET 0x1
425 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_CSCLKEN field value from a register. */
426 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
427 /* Produces a ALT_CLKMGR_MAINPLL_ENS_CSCLKEN register field value suitable for setting the register. */
428 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
429 
430 /*
431  * Field : Debug Timer Enable - cstimerclken
432  *
433  * Enables Debug Timer Clock output (cs_timer_clk)
434  *
435  * Field Access Macros:
436  *
437  */
438 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field. */
439 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_LSB 5
440 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field. */
441 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_MSB 5
442 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field. */
443 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_WIDTH 1
444 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field value. */
445 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_SET_MSK 0x00000020
446 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field value. */
447 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_CLR_MSK 0xffffffdf
448 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field. */
449 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_RESET 0x1
450 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN field value from a register. */
451 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_GET(value) (((value) & 0x00000020) >> 5)
452 /* Produces a ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN register field value suitable for setting the register. */
453 #define ALT_CLKMGR_MAINPLL_ENS_CSTIMERCLKEN_SET(value) (((value) << 5) & 0x00000020)
454 
455 /*
456  * Field : s2f_user0_clk Enable - s2fuser0clken
457  *
458  * Enables clock s2f_user0_clk output
459  *
460  * Field Access Macros:
461  *
462  */
463 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
464 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_LSB 6
465 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
466 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_MSB 6
467 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
468 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_WIDTH 1
469 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value. */
470 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET_MSK 0x00000040
471 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value. */
472 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
473 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field. */
474 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_RESET 0x1
475 /* Extracts the ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN field value from a register. */
476 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
477 /* Produces a ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN register field value suitable for setting the register. */
478 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
479 
480 #ifndef __ASSEMBLY__
481 /*
482  * WARNING: The C register and register group struct declarations are provided for
483  * convenience and illustrative purposes. They should, however, be used with
484  * caution as the C language standard provides no guarantees about the alignment or
485  * atomicity of device memory accesses. The recommended practice for coding device
486  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
487  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
488  * alt_write_dword() functions for 64 bit registers.
489  *
490  * The struct declaration for register ALT_CLKMGR_MAINPLL_ENS.
491  */
492 struct ALT_CLKMGR_MAINPLL_ENS_s
493 {
494  volatile uint32_t mpuclken : 1; /* MPU Clock Group Enable */
495  volatile uint32_t l4mainclken : 1; /* l4_main_clk Enable */
496  volatile uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
497  volatile uint32_t l4spclken : 1; /* l4_sp_clk Enable */
498  volatile uint32_t csclken : 1; /* Debug Group Enable */
499  volatile uint32_t cstimerclken : 1; /* Debug Timer Enable */
500  volatile uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
501  uint32_t : 25; /* *UNDEFINED* */
502 };
503 
504 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_ENS. */
505 typedef struct ALT_CLKMGR_MAINPLL_ENS_s ALT_CLKMGR_MAINPLL_ENS_t;
506 #endif /* __ASSEMBLY__ */
507 
508 /* The reset value of the ALT_CLKMGR_MAINPLL_ENS register. */
509 #define ALT_CLKMGR_MAINPLL_ENS_RESET 0x000000ff
510 /* The byte offset of the ALT_CLKMGR_MAINPLL_ENS register from the beginning of the component. */
511 #define ALT_CLKMGR_MAINPLL_ENS_OFST 0x4
512 
513 /*
514  * Register : Enable Reset Register - enr
515  *
516  * Write One to Clear corresponding fields in Enable Register.
517  *
518  * Register Layout
519  *
520  * Bits | Access | Reset | Description
521  * :-------|:-------|:------|:-----------------------
522  * [0] | RW | 0x1 | MPU Clock Group Enable
523  * [1] | RW | 0x1 | l4_main_clk Enable
524  * [2] | RW | 0x1 | l4_mp_clk Enable
525  * [3] | RW | 0x1 | l4_sp_clk Enable
526  * [4] | RW | 0x1 | Debug Group Enable
527  * [5] | RW | 0x1 | Debug Timer Enable
528  * [6] | RW | 0x1 | s2f_user0_clk Enable
529  * [31:7] | ??? | 0x1 | *UNDEFINED*
530  *
531  */
532 /*
533  * Field : MPU Clock Group Enable - mpuclken
534  *
535  * Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).
536  *
537  * Field Access Macros:
538  *
539  */
540 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
541 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_LSB 0
542 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
543 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_MSB 0
544 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
545 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_WIDTH 1
546 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value. */
547 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET_MSK 0x00000001
548 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value. */
549 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_CLR_MSK 0xfffffffe
550 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field. */
551 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_RESET 0x1
552 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN field value from a register. */
553 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
554 /* Produces a ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value suitable for setting the register. */
555 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
556 
557 /*
558  * Field : l4_main_clk Enable - l4mainclken
559  *
560  * Enables clock l4_main_clk output
561  *
562  * Field Access Macros:
563  *
564  */
565 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
566 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_LSB 1
567 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
568 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_MSB 1
569 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
570 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_WIDTH 1
571 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value. */
572 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET_MSK 0x00000002
573 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value. */
574 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_CLR_MSK 0xfffffffd
575 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field. */
576 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_RESET 0x1
577 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN field value from a register. */
578 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
579 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value suitable for setting the register. */
580 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
581 
582 /*
583  * Field : l4_mp_clk Enable - l4mpclken
584  *
585  * Enables clock l4_mp_clk output
586  *
587  * Field Access Macros:
588  *
589  */
590 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
591 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_LSB 2
592 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
593 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_MSB 2
594 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
595 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_WIDTH 1
596 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value. */
597 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET_MSK 0x00000004
598 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value. */
599 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_CLR_MSK 0xfffffffb
600 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field. */
601 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_RESET 0x1
602 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN field value from a register. */
603 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
604 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value suitable for setting the register. */
605 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
606 
607 /*
608  * Field : l4_sp_clk Enable - l4spclken
609  *
610  * Enables clock l4_sp_clk output
611  *
612  * Field Access Macros:
613  *
614  */
615 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
616 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_LSB 3
617 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
618 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_MSB 3
619 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
620 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_WIDTH 1
621 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value. */
622 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET_MSK 0x00000008
623 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value. */
624 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_CLR_MSK 0xfffffff7
625 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field. */
626 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_RESET 0x1
627 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN field value from a register. */
628 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
629 /* Produces a ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value suitable for setting the register. */
630 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
631 
632 /*
633  * Field : Debug Group Enable - csclken
634  *
635  * Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)
636  *
637  * Field Access Macros:
638  *
639  */
640 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
641 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_LSB 4
642 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
643 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_MSB 4
644 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
645 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_WIDTH 1
646 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value. */
647 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET_MSK 0x00000010
648 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value. */
649 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_CLR_MSK 0xffffffef
650 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field. */
651 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_RESET 0x1
652 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN field value from a register. */
653 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
654 /* Produces a ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value suitable for setting the register. */
655 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
656 
657 /*
658  * Field : Debug Timer Enable - cstimerclken
659  *
660  * Enables Debug Timer Clock output (cs_timer_clk)
661  *
662  * Field Access Macros:
663  *
664  */
665 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field. */
666 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_LSB 5
667 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field. */
668 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_MSB 5
669 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field. */
670 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_WIDTH 1
671 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field value. */
672 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_SET_MSK 0x00000020
673 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field value. */
674 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_CLR_MSK 0xffffffdf
675 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field. */
676 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_RESET 0x1
677 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN field value from a register. */
678 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_GET(value) (((value) & 0x00000020) >> 5)
679 /* Produces a ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN register field value suitable for setting the register. */
680 #define ALT_CLKMGR_MAINPLL_ENR_CSTIMERCLKEN_SET(value) (((value) << 5) & 0x00000020)
681 
682 /*
683  * Field : s2f_user0_clk Enable - s2fuser0clken
684  *
685  * Enables clock s2f_user0_clk output
686  *
687  * Field Access Macros:
688  *
689  */
690 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
691 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_LSB 6
692 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
693 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_MSB 6
694 /* The width in bits of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
695 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_WIDTH 1
696 /* The mask used to set the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value. */
697 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET_MSK 0x00000040
698 /* The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value. */
699 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
700 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field. */
701 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_RESET 0x1
702 /* Extracts the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN field value from a register. */
703 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
704 /* Produces a ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value suitable for setting the register. */
705 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
706 
707 #ifndef __ASSEMBLY__
708 /*
709  * WARNING: The C register and register group struct declarations are provided for
710  * convenience and illustrative purposes. They should, however, be used with
711  * caution as the C language standard provides no guarantees about the alignment or
712  * atomicity of device memory accesses. The recommended practice for coding device
713  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
714  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
715  * alt_write_dword() functions for 64 bit registers.
716  *
717  * The struct declaration for register ALT_CLKMGR_MAINPLL_ENR.
718  */
719 struct ALT_CLKMGR_MAINPLL_ENR_s
720 {
721  volatile uint32_t mpuclken : 1; /* MPU Clock Group Enable */
722  volatile uint32_t l4mainclken : 1; /* l4_main_clk Enable */
723  volatile uint32_t l4mpclken : 1; /* l4_mp_clk Enable */
724  volatile uint32_t l4spclken : 1; /* l4_sp_clk Enable */
725  volatile uint32_t csclken : 1; /* Debug Group Enable */
726  volatile uint32_t cstimerclken : 1; /* Debug Timer Enable */
727  volatile uint32_t s2fuser0clken : 1; /* s2f_user0_clk Enable */
728  uint32_t : 25; /* *UNDEFINED* */
729 };
730 
731 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_ENR. */
732 typedef struct ALT_CLKMGR_MAINPLL_ENR_s ALT_CLKMGR_MAINPLL_ENR_t;
733 #endif /* __ASSEMBLY__ */
734 
735 /* The reset value of the ALT_CLKMGR_MAINPLL_ENR register. */
736 #define ALT_CLKMGR_MAINPLL_ENR_RESET 0x000000ff
737 /* The byte offset of the ALT_CLKMGR_MAINPLL_ENR register from the beginning of the component. */
738 #define ALT_CLKMGR_MAINPLL_ENR_OFST 0x8
739 
740 /*
741  * Register : Bypass Register - bypass
742  *
743  * Contains fields that control bypass for clocks derived from the Main PLL.
744  *
745  * 1: The clock is bypassed to boot_clk.
746  *
747  * 0: The clock is derived from the 5:1 active mux.
748  *
749  * Register Layout
750  *
751  * Bits | Access | Reset | Description
752  * :-------|:-------|:------|:-----------------
753  * [0] | RW | 0x1 | MPU Bypass
754  * [1] | RW | 0x1 | NOC Bypass
755  * [2] | RW | 0x1 | S2F User0 Bypass
756  * [31:3] | ??? | 0x7 | *UNDEFINED*
757  *
758  */
759 /*
760  * Field : MPU Bypass - mpu
761  *
762  * If set, the MPU clock group will be bypassed to the boot_clk.
763  *
764  * Field Access Macros:
765  *
766  */
767 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
768 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_LSB 0
769 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
770 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_MSB 0
771 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
772 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_WIDTH 1
773 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value. */
774 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET_MSK 0x00000001
775 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value. */
776 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_CLR_MSK 0xfffffffe
777 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_MPU register field. */
778 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_RESET 0x1
779 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_MPU field value from a register. */
780 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_GET(value) (((value) & 0x00000001) >> 0)
781 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_MPU register field value suitable for setting the register. */
782 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET(value) (((value) << 0) & 0x00000001)
783 
784 /*
785  * Field : NOC Bypass - noc
786  *
787  * If set, the NOC clock group will be bypassed to boot_clk.
788  *
789  * Field Access Macros:
790  *
791  */
792 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
793 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_LSB 1
794 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
795 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_MSB 1
796 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
797 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_WIDTH 1
798 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value. */
799 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET_MSK 0x00000002
800 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value. */
801 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_CLR_MSK 0xfffffffd
802 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_NOC register field. */
803 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_RESET 0x1
804 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_NOC field value from a register. */
805 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_GET(value) (((value) & 0x00000002) >> 1)
806 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_NOC register field value suitable for setting the register. */
807 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET(value) (((value) << 1) & 0x00000002)
808 
809 /*
810  * Field : S2F User0 Bypass - s2fuser0
811  *
812  * If set, the s2f_user0_clk will be bypassed to the boot_clk.
813  *
814  * Field Access Macros:
815  *
816  */
817 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
818 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_LSB 2
819 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
820 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_MSB 2
821 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
822 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_WIDTH 1
823 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value. */
824 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET_MSK 0x00000004
825 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value. */
826 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_CLR_MSK 0xfffffffb
827 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field. */
828 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_RESET 0x1
829 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 field value from a register. */
830 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
831 /* Produces a ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0 register field value suitable for setting the register. */
832 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
833 
834 #ifndef __ASSEMBLY__
835 /*
836  * WARNING: The C register and register group struct declarations are provided for
837  * convenience and illustrative purposes. They should, however, be used with
838  * caution as the C language standard provides no guarantees about the alignment or
839  * atomicity of device memory accesses. The recommended practice for coding device
840  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
841  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
842  * alt_write_dword() functions for 64 bit registers.
843  *
844  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASS.
845  */
846 struct ALT_CLKMGR_MAINPLL_BYPASS_s
847 {
848  volatile uint32_t mpu : 1; /* MPU Bypass */
849  volatile uint32_t noc : 1; /* NOC Bypass */
850  volatile uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
851  uint32_t : 29; /* *UNDEFINED* */
852 };
853 
854 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASS. */
855 typedef struct ALT_CLKMGR_MAINPLL_BYPASS_s ALT_CLKMGR_MAINPLL_BYPASS_t;
856 #endif /* __ASSEMBLY__ */
857 
858 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASS register. */
859 #define ALT_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
860 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASS register from the beginning of the component. */
861 #define ALT_CLKMGR_MAINPLL_BYPASS_OFST 0xc
862 
863 /*
864  * Register : Bypass Set Register - bypasss
865  *
866  * Write One to Set corresponding fields in Bypass Register.
867  *
868  * Register Layout
869  *
870  * Bits | Access | Reset | Description
871  * :-------|:-------|:------|:-----------------
872  * [0] | RW | 0x1 | MPU Bypass
873  * [1] | RW | 0x1 | NOC Bypass
874  * [2] | RW | 0x1 | S2F User0 Bypass
875  * [31:3] | ??? | 0x7 | *UNDEFINED*
876  *
877  */
878 /*
879  * Field : MPU Bypass - mpu
880  *
881  * If set, the MPU clock group will be bypassed to the input clock reference of the
882  * Main PLL.
883  *
884  * Field Access Macros:
885  *
886  */
887 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
888 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_LSB 0
889 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
890 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_MSB 0
891 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
892 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_WIDTH 1
893 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value. */
894 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET_MSK 0x00000001
895 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value. */
896 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_CLR_MSK 0xfffffffe
897 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field. */
898 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_RESET 0x1
899 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_MPU field value from a register. */
900 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_GET(value) (((value) & 0x00000001) >> 0)
901 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_MPU register field value suitable for setting the register. */
902 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET(value) (((value) << 0) & 0x00000001)
903 
904 /*
905  * Field : NOC Bypass - noc
906  *
907  * If set, the NOC clock group will be bypassed to the input clock reference of the
908  * Main PLL.
909  *
910  * Field Access Macros:
911  *
912  */
913 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
914 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_LSB 1
915 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
916 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_MSB 1
917 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
918 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_WIDTH 1
919 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value. */
920 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET_MSK 0x00000002
921 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value. */
922 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_CLR_MSK 0xfffffffd
923 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field. */
924 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_RESET 0x1
925 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_NOC field value from a register. */
926 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_GET(value) (((value) & 0x00000002) >> 1)
927 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_NOC register field value suitable for setting the register. */
928 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET(value) (((value) << 1) & 0x00000002)
929 
930 /*
931  * Field : S2F User0 Bypass - s2fuser0
932  *
933  * If set, the s2f_user0_clk will be bypassed to the input clock reference of the
934  * Main PLL.
935  *
936  * Field Access Macros:
937  *
938  */
939 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
940 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_LSB 2
941 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
942 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_MSB 2
943 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
944 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_WIDTH 1
945 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value. */
946 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET_MSK 0x00000004
947 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value. */
948 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_CLR_MSK 0xfffffffb
949 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field. */
950 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_RESET 0x1
951 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 field value from a register. */
952 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
953 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0 register field value suitable for setting the register. */
954 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
955 
956 #ifndef __ASSEMBLY__
957 /*
958  * WARNING: The C register and register group struct declarations are provided for
959  * convenience and illustrative purposes. They should, however, be used with
960  * caution as the C language standard provides no guarantees about the alignment or
961  * atomicity of device memory accesses. The recommended practice for coding device
962  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
963  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
964  * alt_write_dword() functions for 64 bit registers.
965  *
966  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASSS.
967  */
968 struct ALT_CLKMGR_MAINPLL_BYPASSS_s
969 {
970  volatile uint32_t mpu : 1; /* MPU Bypass */
971  volatile uint32_t noc : 1; /* NOC Bypass */
972  volatile uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
973  uint32_t : 29; /* *UNDEFINED* */
974 };
975 
976 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASSS. */
977 typedef struct ALT_CLKMGR_MAINPLL_BYPASSS_s ALT_CLKMGR_MAINPLL_BYPASSS_t;
978 #endif /* __ASSEMBLY__ */
979 
980 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSS register. */
981 #define ALT_CLKMGR_MAINPLL_BYPASSS_RESET 0x0000003f
982 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASSS register from the beginning of the component. */
983 #define ALT_CLKMGR_MAINPLL_BYPASSS_OFST 0x10
984 
985 /*
986  * Register : Bypass Reset Register - bypassr
987  *
988  * Write One to Clear corresponding fields in Bypass Register.
989  *
990  * Register Layout
991  *
992  * Bits | Access | Reset | Description
993  * :-------|:-------|:------|:-----------------
994  * [0] | RW | 0x1 | MPU Bypass
995  * [1] | RW | 0x1 | NOC Bypass
996  * [2] | RW | 0x1 | S2F User0 Bypass
997  * [31:3] | ??? | 0x7 | *UNDEFINED*
998  *
999  */
1000 /*
1001  * Field : MPU Bypass - mpu
1002  *
1003  * If set, the MPU clock group will be bypassed to the input clock reference of the
1004  * Main PLL.
1005  *
1006  * Field Access Macros:
1007  *
1008  */
1009 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
1010 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_LSB 0
1011 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
1012 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_MSB 0
1013 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
1014 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_WIDTH 1
1015 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value. */
1016 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET_MSK 0x00000001
1017 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value. */
1018 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_CLR_MSK 0xfffffffe
1019 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field. */
1020 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_RESET 0x1
1021 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_MPU field value from a register. */
1022 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_GET(value) (((value) & 0x00000001) >> 0)
1023 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value suitable for setting the register. */
1024 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET(value) (((value) << 0) & 0x00000001)
1025 
1026 /*
1027  * Field : NOC Bypass - noc
1028  *
1029  * If set, the NOC clock group will be bypassed to the input clock reference of the
1030  * Main PLL.
1031  *
1032  * Field Access Macros:
1033  *
1034  */
1035 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
1036 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_LSB 1
1037 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
1038 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_MSB 1
1039 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
1040 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_WIDTH 1
1041 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value. */
1042 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET_MSK 0x00000002
1043 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value. */
1044 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_CLR_MSK 0xfffffffd
1045 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field. */
1046 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_RESET 0x1
1047 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_NOC field value from a register. */
1048 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_GET(value) (((value) & 0x00000002) >> 1)
1049 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value suitable for setting the register. */
1050 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET(value) (((value) << 1) & 0x00000002)
1051 
1052 /*
1053  * Field : S2F User0 Bypass - s2fuser0
1054  *
1055  * If set, the s2f_user0_clk will be bypassed to the input clock reference of the
1056  * Main PLL.
1057  *
1058  * Field Access Macros:
1059  *
1060  */
1061 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
1062 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_LSB 2
1063 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
1064 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_MSB 2
1065 /* The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
1066 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_WIDTH 1
1067 /* The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value. */
1068 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET_MSK 0x00000004
1069 /* The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value. */
1070 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_CLR_MSK 0xfffffffb
1071 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field. */
1072 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_RESET 0x1
1073 /* Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 field value from a register. */
1074 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
1075 /* Produces a ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value suitable for setting the register. */
1076 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
1077 
1078 #ifndef __ASSEMBLY__
1079 /*
1080  * WARNING: The C register and register group struct declarations are provided for
1081  * convenience and illustrative purposes. They should, however, be used with
1082  * caution as the C language standard provides no guarantees about the alignment or
1083  * atomicity of device memory accesses. The recommended practice for coding device
1084  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1085  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1086  * alt_write_dword() functions for 64 bit registers.
1087  *
1088  * The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASSR.
1089  */
1090 struct ALT_CLKMGR_MAINPLL_BYPASSR_s
1091 {
1092  volatile uint32_t mpu : 1; /* MPU Bypass */
1093  volatile uint32_t noc : 1; /* NOC Bypass */
1094  volatile uint32_t s2fuser0 : 1; /* S2F User0 Bypass */
1095  uint32_t : 29; /* *UNDEFINED* */
1096 };
1097 
1098 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASSR. */
1099 typedef struct ALT_CLKMGR_MAINPLL_BYPASSR_s ALT_CLKMGR_MAINPLL_BYPASSR_t;
1100 #endif /* __ASSEMBLY__ */
1101 
1102 /* The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR register. */
1103 #define ALT_CLKMGR_MAINPLL_BYPASSR_RESET 0x0000003f
1104 /* The byte offset of the ALT_CLKMGR_MAINPLL_BYPASSR register from the beginning of the component. */
1105 #define ALT_CLKMGR_MAINPLL_BYPASSR_OFST 0x14
1106 
1107 /*
1108  * Register : Main PLL Control Register for MPU Clock Group. - mpuclk
1109  *
1110  * Contains settings that control clock mpu_clk generated from the Main PLL VCO
1111  * clock.
1112  *
1113  * Register Layout
1114  *
1115  * Bits | Access | Reset | Description
1116  * :--------|:-------|:------|:------------------------------
1117  * [10:0] | RW | 0x0 | Counter
1118  * [15:11] | ??? | 0x0 | *UNDEFINED*
1119  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1120  * [31:19] | ??? | 0x0 | *UNDEFINED*
1121  *
1122  */
1123 /*
1124  * Field : Counter - cnt
1125  *
1126  * Divides the VCO/2 frequency by the value+1 in this field.
1127  *
1128  * Field Access Macros:
1129  *
1130  */
1131 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1132 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
1133 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1134 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 10
1135 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1136 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 11
1137 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1138 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000007ff
1139 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value. */
1140 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffff800
1141 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field. */
1142 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
1143 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_CNT field value from a register. */
1144 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1145 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_CNT register field value suitable for setting the register. */
1146 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1147 
1148 /*
1149  * Field : src
1150  *
1151  * Selects the source for the active 5:1 clock selection when the PLL is not
1152  * bypassed.
1153  *
1154  * Field Enumeration Values:
1155  *
1156  * Enum | Value | Description
1157  * :---------------------------------------|:------|:------------
1158  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_MAIN | 0x0 |
1159  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_PERI | 0x1 |
1160  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_OSC1 | 0x2 |
1161  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_INTOSC | 0x3 |
1162  * ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_FPGA | 0x4 |
1163  *
1164  * Field Access Macros:
1165  *
1166  */
1167 /*
1168  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1169  *
1170  */
1171 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_MAIN 0x0
1172 /*
1173  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1174  *
1175  */
1176 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_PERI 0x1
1177 /*
1178  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1179  *
1180  */
1181 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_OSC1 0x2
1182 /*
1183  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1184  *
1185  */
1186 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_INTOSC 0x3
1187 /*
1188  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MPUCLK_SRC
1189  *
1190  */
1191 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_FPGA 0x4
1192 
1193 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
1194 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
1195 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
1196 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_MSB 18
1197 /* The width in bits of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
1198 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_WIDTH 3
1199 /* The mask used to set the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value. */
1200 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET_MSK 0x00070000
1201 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value. */
1202 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_CLR_MSK 0xfff8ffff
1203 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field. */
1204 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_RESET 0x0
1205 /* Extracts the ALT_CLKMGR_MAINPLL_MPUCLK_SRC field value from a register. */
1206 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
1207 /* Produces a ALT_CLKMGR_MAINPLL_MPUCLK_SRC register field value suitable for setting the register. */
1208 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
1209 
1210 #ifndef __ASSEMBLY__
1211 /*
1212  * WARNING: The C register and register group struct declarations are provided for
1213  * convenience and illustrative purposes. They should, however, be used with
1214  * caution as the C language standard provides no guarantees about the alignment or
1215  * atomicity of device memory accesses. The recommended practice for coding device
1216  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1217  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1218  * alt_write_dword() functions for 64 bit registers.
1219  *
1220  * The struct declaration for register ALT_CLKMGR_MAINPLL_MPUCLK.
1221  */
1222 struct ALT_CLKMGR_MAINPLL_MPUCLK_s
1223 {
1224  volatile uint32_t cnt : 11; /* Counter */
1225  uint32_t : 5; /* *UNDEFINED* */
1226  volatile uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_MPUCLK_SRC */
1227  uint32_t : 13; /* *UNDEFINED* */
1228 };
1229 
1230 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MPUCLK. */
1231 typedef struct ALT_CLKMGR_MAINPLL_MPUCLK_s ALT_CLKMGR_MAINPLL_MPUCLK_t;
1232 #endif /* __ASSEMBLY__ */
1233 
1234 /* The reset value of the ALT_CLKMGR_MAINPLL_MPUCLK register. */
1235 #define ALT_CLKMGR_MAINPLL_MPUCLK_RESET 0x00000000
1236 /* The byte offset of the ALT_CLKMGR_MAINPLL_MPUCLK register from the beginning of the component. */
1237 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x18
1238 
1239 /*
1240  * Register : Main PLL Control Register for NOC Clock Group. - nocclk
1241  *
1242  * Contains settings that control clock main_clk generated from the Main PLL VCO
1243  * clock.
1244  *
1245  * Register Layout
1246  *
1247  * Bits | Access | Reset | Description
1248  * :--------|:-------|:------|:------------------------------
1249  * [10:0] | RW | 0x0 | Counter
1250  * [15:11] | ??? | 0x0 | *UNDEFINED*
1251  * [18:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1252  * [31:19] | ??? | 0x0 | *UNDEFINED*
1253  *
1254  */
1255 /*
1256  * Field : Counter - cnt
1257  *
1258  * Divides the VCO frequency by the value+1 in this field.
1259  *
1260  * Field Access Macros:
1261  *
1262  */
1263 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
1264 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_LSB 0
1265 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
1266 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_MSB 10
1267 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
1268 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_WIDTH 11
1269 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value. */
1270 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET_MSK 0x000007ff
1271 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value. */
1272 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_CLR_MSK 0xfffff800
1273 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field. */
1274 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_RESET 0x0
1275 /* Extracts the ALT_CLKMGR_MAINPLL_NOCCLK_CNT field value from a register. */
1276 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1277 /* Produces a ALT_CLKMGR_MAINPLL_NOCCLK_CNT register field value suitable for setting the register. */
1278 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1279 
1280 /*
1281  * Field : src
1282  *
1283  * Selects the source for the active 5:1 clock selection when the PLL is not
1284  * bypassed.
1285  *
1286  * Field Enumeration Values:
1287  *
1288  * Enum | Value | Description
1289  * :---------------------------------------|:------|:------------
1290  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_MAIN | 0x0 |
1291  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_PERI | 0x1 |
1292  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_OSC1 | 0x2 |
1293  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_INTOSC | 0x3 |
1294  * ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_FPGA | 0x4 |
1295  *
1296  * Field Access Macros:
1297  *
1298  */
1299 /*
1300  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1301  *
1302  */
1303 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_MAIN 0x0
1304 /*
1305  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1306  *
1307  */
1308 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_PERI 0x1
1309 /*
1310  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1311  *
1312  */
1313 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_OSC1 0x2
1314 /*
1315  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1316  *
1317  */
1318 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_INTOSC 0x3
1319 /*
1320  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCCLK_SRC
1321  *
1322  */
1323 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_FPGA 0x4
1324 
1325 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
1326 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
1327 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
1328 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_MSB 18
1329 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
1330 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_WIDTH 3
1331 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value. */
1332 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET_MSK 0x00070000
1333 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value. */
1334 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_CLR_MSK 0xfff8ffff
1335 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field. */
1336 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_RESET 0x0
1337 /* Extracts the ALT_CLKMGR_MAINPLL_NOCCLK_SRC field value from a register. */
1338 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
1339 /* Produces a ALT_CLKMGR_MAINPLL_NOCCLK_SRC register field value suitable for setting the register. */
1340 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
1341 
1342 #ifndef __ASSEMBLY__
1343 /*
1344  * WARNING: The C register and register group struct declarations are provided for
1345  * convenience and illustrative purposes. They should, however, be used with
1346  * caution as the C language standard provides no guarantees about the alignment or
1347  * atomicity of device memory accesses. The recommended practice for coding device
1348  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1349  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1350  * alt_write_dword() functions for 64 bit registers.
1351  *
1352  * The struct declaration for register ALT_CLKMGR_MAINPLL_NOCCLK.
1353  */
1354 struct ALT_CLKMGR_MAINPLL_NOCCLK_s
1355 {
1356  volatile uint32_t cnt : 11; /* Counter */
1357  uint32_t : 5; /* *UNDEFINED* */
1358  volatile uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_NOCCLK_SRC */
1359  uint32_t : 13; /* *UNDEFINED* */
1360 };
1361 
1362 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_NOCCLK. */
1363 typedef struct ALT_CLKMGR_MAINPLL_NOCCLK_s ALT_CLKMGR_MAINPLL_NOCCLK_t;
1364 #endif /* __ASSEMBLY__ */
1365 
1366 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCCLK register. */
1367 #define ALT_CLKMGR_MAINPLL_NOCCLK_RESET 0x00000000
1368 /* The byte offset of the ALT_CLKMGR_MAINPLL_NOCCLK register from the beginning of the component. */
1369 #define ALT_CLKMGR_MAINPLL_NOCCLK_OFST 0x1c
1370 
1371 /*
1372  * Register : Main PLL Control Register for Counter 2 Clock - cntr2clk
1373  *
1374  * Contains settings that control Couner 2 clock generated from the Main PLL VCO
1375  * clock.
1376  *
1377  * Register Layout
1378  *
1379  * Bits | Access | Reset | Description
1380  * :--------|:-------|:------|:------------
1381  * [10:0] | RW | 0x1 | Counter
1382  * [31:11] | ??? | 0x0 | *UNDEFINED*
1383  *
1384  */
1385 /*
1386  * Field : Counter - cnt
1387  *
1388  * Divides the VCO frequency by the value+1 in this field.
1389  *
1390  * Field Access Macros:
1391  *
1392  */
1393 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
1394 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_LSB 0
1395 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
1396 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_MSB 10
1397 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
1398 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_WIDTH 11
1399 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value. */
1400 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
1401 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value. */
1402 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
1403 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field. */
1404 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_RESET 0x1
1405 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT field value from a register. */
1406 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1407 /* Produces a ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT register field value suitable for setting the register. */
1408 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1409 
1410 #ifndef __ASSEMBLY__
1411 /*
1412  * WARNING: The C register and register group struct declarations are provided for
1413  * convenience and illustrative purposes. They should, however, be used with
1414  * caution as the C language standard provides no guarantees about the alignment or
1415  * atomicity of device memory accesses. The recommended practice for coding device
1416  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1417  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1418  * alt_write_dword() functions for 64 bit registers.
1419  *
1420  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR2CLK.
1421  */
1422 struct ALT_CLKMGR_MAINPLL_CNTR2CLK_s
1423 {
1424  volatile uint32_t cnt : 11; /* Counter */
1425  uint32_t : 21; /* *UNDEFINED* */
1426 };
1427 
1428 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR2CLK. */
1429 typedef struct ALT_CLKMGR_MAINPLL_CNTR2CLK_s ALT_CLKMGR_MAINPLL_CNTR2CLK_t;
1430 #endif /* __ASSEMBLY__ */
1431 
1432 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR2CLK register. */
1433 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_RESET 0x00000001
1434 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR2CLK register from the beginning of the component. */
1435 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_OFST 0x20
1436 
1437 /*
1438  * Register : Main PLL Control Register for Counter 3 Clock - cntr3clk
1439  *
1440  * Contains settings that control Couner 3 clock generated from the Main PLL VCO
1441  * clock.
1442  *
1443  * Register Layout
1444  *
1445  * Bits | Access | Reset | Description
1446  * :--------|:-------|:------|:------------
1447  * [10:0] | RW | 0x1 | Counter
1448  * [31:11] | ??? | 0x0 | *UNDEFINED*
1449  *
1450  */
1451 /*
1452  * Field : Counter - cnt
1453  *
1454  * Divides the VCO frequency by the value+1 in this field.
1455  *
1456  * Field Access Macros:
1457  *
1458  */
1459 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
1460 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_LSB 0
1461 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
1462 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_MSB 10
1463 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
1464 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_WIDTH 11
1465 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value. */
1466 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
1467 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value. */
1468 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
1469 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field. */
1470 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_RESET 0x1
1471 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT field value from a register. */
1472 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1473 /* Produces a ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT register field value suitable for setting the register. */
1474 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1475 
1476 #ifndef __ASSEMBLY__
1477 /*
1478  * WARNING: The C register and register group struct declarations are provided for
1479  * convenience and illustrative purposes. They should, however, be used with
1480  * caution as the C language standard provides no guarantees about the alignment or
1481  * atomicity of device memory accesses. The recommended practice for coding device
1482  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1483  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1484  * alt_write_dword() functions for 64 bit registers.
1485  *
1486  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR3CLK.
1487  */
1488 struct ALT_CLKMGR_MAINPLL_CNTR3CLK_s
1489 {
1490  volatile uint32_t cnt : 11; /* Counter */
1491  uint32_t : 21; /* *UNDEFINED* */
1492 };
1493 
1494 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR3CLK. */
1495 typedef struct ALT_CLKMGR_MAINPLL_CNTR3CLK_s ALT_CLKMGR_MAINPLL_CNTR3CLK_t;
1496 #endif /* __ASSEMBLY__ */
1497 
1498 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR3CLK register. */
1499 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_RESET 0x00000001
1500 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR3CLK register from the beginning of the component. */
1501 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_OFST 0x24
1502 
1503 /*
1504  * Register : Main PLL Control Register for Counter 4 Clock - cntr4clk
1505  *
1506  * Contains settings that control Couner 4 clock generated from the Main PLL VCO
1507  * clock.
1508  *
1509  * Register Layout
1510  *
1511  * Bits | Access | Reset | Description
1512  * :--------|:-------|:------|:------------
1513  * [10:0] | RW | 0x3 | Counter
1514  * [31:11] | ??? | 0x0 | *UNDEFINED*
1515  *
1516  */
1517 /*
1518  * Field : Counter - cnt
1519  *
1520  * Divides the VCO frequency by the value+1 in this field.
1521  *
1522  * Field Access Macros:
1523  *
1524  */
1525 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
1526 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_LSB 0
1527 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
1528 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_MSB 10
1529 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
1530 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_WIDTH 11
1531 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value. */
1532 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
1533 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value. */
1534 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
1535 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field. */
1536 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_RESET 0x3
1537 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT field value from a register. */
1538 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1539 /* Produces a ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT register field value suitable for setting the register. */
1540 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1541 
1542 #ifndef __ASSEMBLY__
1543 /*
1544  * WARNING: The C register and register group struct declarations are provided for
1545  * convenience and illustrative purposes. They should, however, be used with
1546  * caution as the C language standard provides no guarantees about the alignment or
1547  * atomicity of device memory accesses. The recommended practice for coding device
1548  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1549  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1550  * alt_write_dword() functions for 64 bit registers.
1551  *
1552  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR4CLK.
1553  */
1554 struct ALT_CLKMGR_MAINPLL_CNTR4CLK_s
1555 {
1556  volatile uint32_t cnt : 11; /* Counter */
1557  uint32_t : 21; /* *UNDEFINED* */
1558 };
1559 
1560 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR4CLK. */
1561 typedef struct ALT_CLKMGR_MAINPLL_CNTR4CLK_s ALT_CLKMGR_MAINPLL_CNTR4CLK_t;
1562 #endif /* __ASSEMBLY__ */
1563 
1564 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR4CLK register. */
1565 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_RESET 0x00000003
1566 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR4CLK register from the beginning of the component. */
1567 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_OFST 0x28
1568 
1569 /*
1570  * Register : Main PLL Control Register for Counter 5 Clock - cntr5clk
1571  *
1572  * Contains settings that control Couner 5 clock generated from the Main PLL VCO
1573  * clock.
1574  *
1575  * Register Layout
1576  *
1577  * Bits | Access | Reset | Description
1578  * :--------|:-------|:------|:------------
1579  * [10:0] | RW | 0x1 | Counter
1580  * [31:11] | ??? | 0x0 | *UNDEFINED*
1581  *
1582  */
1583 /*
1584  * Field : Counter - cnt
1585  *
1586  * Divides the VCO frequency by the value+1 in this field.
1587  *
1588  * Field Access Macros:
1589  *
1590  */
1591 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
1592 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_LSB 0
1593 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
1594 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_MSB 10
1595 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
1596 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_WIDTH 11
1597 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value. */
1598 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
1599 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value. */
1600 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
1601 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field. */
1602 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_RESET 0x1
1603 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT field value from a register. */
1604 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1605 /* Produces a ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT register field value suitable for setting the register. */
1606 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1607 
1608 #ifndef __ASSEMBLY__
1609 /*
1610  * WARNING: The C register and register group struct declarations are provided for
1611  * convenience and illustrative purposes. They should, however, be used with
1612  * caution as the C language standard provides no guarantees about the alignment or
1613  * atomicity of device memory accesses. The recommended practice for coding device
1614  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1615  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1616  * alt_write_dword() functions for 64 bit registers.
1617  *
1618  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR5CLK.
1619  */
1620 struct ALT_CLKMGR_MAINPLL_CNTR5CLK_s
1621 {
1622  volatile uint32_t cnt : 11; /* Counter */
1623  uint32_t : 21; /* *UNDEFINED* */
1624 };
1625 
1626 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR5CLK. */
1627 typedef struct ALT_CLKMGR_MAINPLL_CNTR5CLK_s ALT_CLKMGR_MAINPLL_CNTR5CLK_t;
1628 #endif /* __ASSEMBLY__ */
1629 
1630 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR5CLK register. */
1631 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_RESET 0x00000001
1632 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR5CLK register from the beginning of the component. */
1633 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_OFST 0x2c
1634 
1635 /*
1636  * Register : Main PLL Control Register for Counter 6 Clock - cntr6clk
1637  *
1638  * Contains settings that control Couner 6 clock generated from the Main PLL VCO
1639  * clock.
1640  *
1641  * Register Layout
1642  *
1643  * Bits | Access | Reset | Description
1644  * :--------|:-------|:------|:------------
1645  * [10:0] | RW | 0x1 | Counter
1646  * [31:11] | ??? | 0x0 | *UNDEFINED*
1647  *
1648  */
1649 /*
1650  * Field : Counter - cnt
1651  *
1652  * Divides the VCO frequency by the value+1 in this field.
1653  *
1654  * Field Access Macros:
1655  *
1656  */
1657 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
1658 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_LSB 0
1659 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
1660 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_MSB 10
1661 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
1662 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_WIDTH 11
1663 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value. */
1664 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
1665 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value. */
1666 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
1667 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field. */
1668 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_RESET 0x1
1669 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT field value from a register. */
1670 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1671 /* Produces a ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT register field value suitable for setting the register. */
1672 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1673 
1674 #ifndef __ASSEMBLY__
1675 /*
1676  * WARNING: The C register and register group struct declarations are provided for
1677  * convenience and illustrative purposes. They should, however, be used with
1678  * caution as the C language standard provides no guarantees about the alignment or
1679  * atomicity of device memory accesses. The recommended practice for coding device
1680  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1681  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1682  * alt_write_dword() functions for 64 bit registers.
1683  *
1684  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR6CLK.
1685  */
1686 struct ALT_CLKMGR_MAINPLL_CNTR6CLK_s
1687 {
1688  volatile uint32_t cnt : 11; /* Counter */
1689  uint32_t : 21; /* *UNDEFINED* */
1690 };
1691 
1692 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR6CLK. */
1693 typedef struct ALT_CLKMGR_MAINPLL_CNTR6CLK_s ALT_CLKMGR_MAINPLL_CNTR6CLK_t;
1694 #endif /* __ASSEMBLY__ */
1695 
1696 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR6CLK register. */
1697 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_RESET 0x00000001
1698 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR6CLK register from the beginning of the component. */
1699 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_OFST 0x30
1700 
1701 /*
1702  * Register : Main PLL Control Register for Counter 7 Clock - cntr7clk
1703  *
1704  * Contains settings that control Couner 7 clock generated from the Main PLL VCO
1705  * clock.
1706  *
1707  * Register Layout
1708  *
1709  * Bits | Access | Reset | Description
1710  * :--------|:-------|:------|:--------------------------------
1711  * [10:0] | RW | 0x0 | Counter
1712  * [15:11] | ??? | 0x0 | *UNDEFINED*
1713  * [18:16] | RW | 0x1 | ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1714  * [31:19] | ??? | 0x0 | *UNDEFINED*
1715  *
1716  */
1717 /*
1718  * Field : Counter - cnt
1719  *
1720  * Divides the VCO frequency by the value+1 in this field.
1721  *
1722  * Field Access Macros:
1723  *
1724  */
1725 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
1726 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_LSB 0
1727 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
1728 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_MSB 10
1729 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
1730 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_WIDTH 11
1731 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value. */
1732 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
1733 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value. */
1734 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
1735 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field. */
1736 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_RESET 0x0
1737 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT field value from a register. */
1738 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1739 /* Produces a ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT register field value suitable for setting the register. */
1740 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1741 
1742 /*
1743  * Field : src
1744  *
1745  * Selects the source for the active 5:1 clock selection when the PLL is not
1746  * bypassed.
1747  *
1748  * Field Enumeration Values:
1749  *
1750  * Enum | Value | Description
1751  * :-----------------------------------------|:------|:------------
1752  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_MAIN | 0x0 |
1753  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_PERI | 0x1 |
1754  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_OSC1 | 0x2 |
1755  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_INTOSC | 0x3 |
1756  * ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_FPGA | 0x4 |
1757  *
1758  * Field Access Macros:
1759  *
1760  */
1761 /*
1762  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1763  *
1764  */
1765 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_MAIN 0x0
1766 /*
1767  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1768  *
1769  */
1770 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_PERI 0x1
1771 /*
1772  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1773  *
1774  */
1775 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_OSC1 0x2
1776 /*
1777  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1778  *
1779  */
1780 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_INTOSC 0x3
1781 /*
1782  * Enumerated value for register field ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC
1783  *
1784  */
1785 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_FPGA 0x4
1786 
1787 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
1788 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
1789 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
1790 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_MSB 18
1791 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
1792 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_WIDTH 3
1793 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value. */
1794 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET_MSK 0x00070000
1795 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value. */
1796 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_CLR_MSK 0xfff8ffff
1797 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field. */
1798 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_RESET 0x1
1799 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC field value from a register. */
1800 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
1801 /* Produces a ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC register field value suitable for setting the register. */
1802 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
1803 
1804 #ifndef __ASSEMBLY__
1805 /*
1806  * WARNING: The C register and register group struct declarations are provided for
1807  * convenience and illustrative purposes. They should, however, be used with
1808  * caution as the C language standard provides no guarantees about the alignment or
1809  * atomicity of device memory accesses. The recommended practice for coding device
1810  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1811  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1812  * alt_write_dword() functions for 64 bit registers.
1813  *
1814  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR7CLK.
1815  */
1816 struct ALT_CLKMGR_MAINPLL_CNTR7CLK_s
1817 {
1818  volatile uint32_t cnt : 11; /* Counter */
1819  uint32_t : 5; /* *UNDEFINED* */
1820  volatile uint32_t src : 3; /* ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC */
1821  uint32_t : 13; /* *UNDEFINED* */
1822 };
1823 
1824 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR7CLK. */
1825 typedef struct ALT_CLKMGR_MAINPLL_CNTR7CLK_s ALT_CLKMGR_MAINPLL_CNTR7CLK_t;
1826 #endif /* __ASSEMBLY__ */
1827 
1828 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR7CLK register. */
1829 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_RESET 0x00010000
1830 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR7CLK register from the beginning of the component. */
1831 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_OFST 0x34
1832 
1833 /*
1834  * Register : Main PLL Control Register for Counter 8 Clock - cntr8clk
1835  *
1836  * Contains settings that control Couner 8 clock generated from the Main PLL VCO
1837  * clock.
1838  *
1839  * Register Layout
1840  *
1841  * Bits | Access | Reset | Description
1842  * :--------|:-------|:------|:------------
1843  * [10:0] | RW | 0x0 | Counter
1844  * [31:11] | ??? | 0x0 | *UNDEFINED*
1845  *
1846  */
1847 /*
1848  * Field : Counter - cnt
1849  *
1850  * Divides the VCO frequency by the value+1 in this field.
1851  *
1852  * Field Access Macros:
1853  *
1854  */
1855 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
1856 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_LSB 0
1857 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
1858 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_MSB 10
1859 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
1860 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_WIDTH 11
1861 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value. */
1862 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
1863 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value. */
1864 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
1865 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field. */
1866 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_RESET 0x0
1867 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT field value from a register. */
1868 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1869 /* Produces a ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT register field value suitable for setting the register. */
1870 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1871 
1872 #ifndef __ASSEMBLY__
1873 /*
1874  * WARNING: The C register and register group struct declarations are provided for
1875  * convenience and illustrative purposes. They should, however, be used with
1876  * caution as the C language standard provides no guarantees about the alignment or
1877  * atomicity of device memory accesses. The recommended practice for coding device
1878  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1879  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1880  * alt_write_dword() functions for 64 bit registers.
1881  *
1882  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR8CLK.
1883  */
1884 struct ALT_CLKMGR_MAINPLL_CNTR8CLK_s
1885 {
1886  volatile uint32_t cnt : 11; /* Counter */
1887  uint32_t : 21; /* *UNDEFINED* */
1888 };
1889 
1890 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR8CLK. */
1891 typedef struct ALT_CLKMGR_MAINPLL_CNTR8CLK_s ALT_CLKMGR_MAINPLL_CNTR8CLK_t;
1892 #endif /* __ASSEMBLY__ */
1893 
1894 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR8CLK register. */
1895 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_RESET 0x00000000
1896 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR8CLK register from the beginning of the component. */
1897 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_OFST 0x38
1898 
1899 /*
1900  * Register : Main PLL Control Register for Counter 10 Clock - cntr9clk
1901  *
1902  * Contains settings that control Couner 10 clock generated from the Main PLL VCO
1903  * clock.
1904  *
1905  * Register Layout
1906  *
1907  * Bits | Access | Reset | Description
1908  * :--------|:-------|:------|:------------
1909  * [10:0] | RW | 0x0 | Counter
1910  * [31:11] | ??? | 0x0 | *UNDEFINED*
1911  *
1912  */
1913 /*
1914  * Field : Counter - cnt
1915  *
1916  * Divides the VCO frequency by the value+1 in this field.
1917  *
1918  * Field Access Macros:
1919  *
1920  */
1921 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
1922 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_LSB 0
1923 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
1924 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_MSB 10
1925 /* The width in bits of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
1926 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_WIDTH 11
1927 /* The mask used to set the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value. */
1928 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
1929 /* The mask used to clear the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value. */
1930 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
1931 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field. */
1932 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_RESET 0x0
1933 /* Extracts the ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT field value from a register. */
1934 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
1935 /* Produces a ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT register field value suitable for setting the register. */
1936 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
1937 
1938 #ifndef __ASSEMBLY__
1939 /*
1940  * WARNING: The C register and register group struct declarations are provided for
1941  * convenience and illustrative purposes. They should, however, be used with
1942  * caution as the C language standard provides no guarantees about the alignment or
1943  * atomicity of device memory accesses. The recommended practice for coding device
1944  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1945  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1946  * alt_write_dword() functions for 64 bit registers.
1947  *
1948  * The struct declaration for register ALT_CLKMGR_MAINPLL_CNTR9CLK.
1949  */
1950 struct ALT_CLKMGR_MAINPLL_CNTR9CLK_s
1951 {
1952  volatile uint32_t cnt : 11; /* Counter */
1953  uint32_t : 21; /* *UNDEFINED* */
1954 };
1955 
1956 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_CNTR9CLK. */
1957 typedef struct ALT_CLKMGR_MAINPLL_CNTR9CLK_s ALT_CLKMGR_MAINPLL_CNTR9CLK_t;
1958 #endif /* __ASSEMBLY__ */
1959 
1960 /* The reset value of the ALT_CLKMGR_MAINPLL_CNTR9CLK register. */
1961 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_RESET 0x00000000
1962 /* The byte offset of the ALT_CLKMGR_MAINPLL_CNTR9CLK register from the beginning of the component. */
1963 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_OFST 0x3c
1964 
1965 /*
1966  * Register : NoC Divide Register - nocdiv
1967  *
1968  * Contains fields that control clock dividers for NoC Clocks.
1969  *
1970  * Register Layout
1971  *
1972  * Bits | Access | Reset | Description
1973  * :--------|:-------|:------|:----------------------------------------
1974  * [1:0] | RW | 0x0 | L4 Main Clock Divider
1975  * [7:2] | ??? | 0x0 | *UNDEFINED*
1976  * [9:8] | RW | 0x1 | L4 MP Clock Divider
1977  * [15:10] | ??? | 0x0 | *UNDEFINED*
1978  * [17:16] | RW | 0x2 | L4 SP Clock Divider
1979  * [23:18] | ??? | 0x0 | *UNDEFINED*
1980  * [25:24] | RW | 0x0 | CoreSight Trace Clock Divider
1981  * [27:26] | RW | 0x2 | CoreSight Trace Interface Clock Divider
1982  * [28] | RW | 0x1 | CoreSight Debug Clock Divider
1983  * [31:29] | ??? | 0x0 | *UNDEFINED*
1984  *
1985  */
1986 /*
1987  * Field : L4 Main Clock Divider - l4mainclk
1988  *
1989  * The external l4_main_clk divider is specified in this field.
1990  *
1991  * Field Enumeration Values:
1992  *
1993  * Enum | Value | Description
1994  * :-------------------------------------------|:------|:------------
1995  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 | 0x0 | Divide By 1
1996  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 | 0x1 | Divide By 2
1997  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 | 0x2 | Divide By 4
1998  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 | 0x3 | Divide By 8
1999  *
2000  * Field Access Macros:
2001  *
2002  */
2003 /*
2004  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
2005  *
2006  * Divide By 1
2007  */
2008 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 0x0
2009 /*
2010  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
2011  *
2012  * Divide By 2
2013  */
2014 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 0x1
2015 /*
2016  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
2017  *
2018  * Divide By 4
2019  */
2020 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 0x2
2021 /*
2022  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
2023  *
2024  * Divide By 8
2025  */
2026 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 0x3
2027 
2028 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
2029 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
2030 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
2031 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_MSB 1
2032 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
2033 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_WIDTH 2
2034 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value. */
2035 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET_MSK 0x00000003
2036 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value. */
2037 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_CLR_MSK 0xfffffffc
2038 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field. */
2039 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_RESET 0x0
2040 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK field value from a register. */
2041 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_GET(value) (((value) & 0x00000003) >> 0)
2042 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value suitable for setting the register. */
2043 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET(value) (((value) << 0) & 0x00000003)
2044 
2045 /*
2046  * Field : L4 MP Clock Divider - l4mpclk
2047  *
2048  * The external l4_mp_clk divider is specified in this field.
2049  *
2050  * Field Enumeration Values:
2051  *
2052  * Enum | Value | Description
2053  * :-----------------------------------------|:------|:------------
2054  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 | 0x0 | Divide By 1
2055  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 | 0x1 | Divide By 2
2056  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 | 0x2 | Divide By 4
2057  * ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 | 0x3 | Divide By 8
2058  *
2059  * Field Access Macros:
2060  *
2061  */
2062 /*
2063  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
2064  *
2065  * Divide By 1
2066  */
2067 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 0x0
2068 /*
2069  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
2070  *
2071  * Divide By 2
2072  */
2073 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 0x1
2074 /*
2075  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
2076  *
2077  * Divide By 4
2078  */
2079 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 0x2
2080 /*
2081  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
2082  *
2083  * Divide By 8
2084  */
2085 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 0x3
2086 
2087 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
2088 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
2089 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
2090 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_MSB 9
2091 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
2092 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_WIDTH 2
2093 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value. */
2094 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET_MSK 0x00000300
2095 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value. */
2096 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_CLR_MSK 0xfffffcff
2097 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field. */
2098 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_RESET 0x1
2099 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK field value from a register. */
2100 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_GET(value) (((value) & 0x00000300) >> 8)
2101 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value suitable for setting the register. */
2102 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET(value) (((value) << 8) & 0x00000300)
2103 
2104 /*
2105  * Field : L4 SP Clock Divider - l4spclk
2106  *
2107  * The external l4_sp_clk divider is specified in this field.
2108  *
2109  * Field Enumeration Values:
2110  *
2111  * Enum | Value | Description
2112  * :-----------------------------------------|:------|:------------
2113  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 | 0x0 | Divide By 1
2114  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 | 0x1 | Divide By 2
2115  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 | 0x2 | Divide By 4
2116  * ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 | 0x3 | Divide By 8
2117  *
2118  * Field Access Macros:
2119  *
2120  */
2121 /*
2122  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
2123  *
2124  * Divide By 1
2125  */
2126 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 0x0
2127 /*
2128  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
2129  *
2130  * Divide By 2
2131  */
2132 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 0x1
2133 /*
2134  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
2135  *
2136  * Divide By 4
2137  */
2138 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 0x2
2139 /*
2140  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
2141  *
2142  * Divide By 8
2143  */
2144 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 0x3
2145 
2146 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
2147 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
2148 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
2149 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_MSB 17
2150 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
2151 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_WIDTH 2
2152 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value. */
2153 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET_MSK 0x00030000
2154 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value. */
2155 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_CLR_MSK 0xfffcffff
2156 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field. */
2157 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_RESET 0x2
2158 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK field value from a register. */
2159 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_GET(value) (((value) & 0x00030000) >> 16)
2160 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value suitable for setting the register. */
2161 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET(value) (((value) << 16) & 0x00030000)
2162 
2163 /*
2164  * Field : CoreSight Trace Clock Divider - csatclk
2165  *
2166  * The external cs_at_clk divider is specified in this field.
2167  *
2168  * Field Enumeration Values:
2169  *
2170  * Enum | Value | Description
2171  * :-----------------------------------------|:------|:------------
2172  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 | 0x0 | Divide By 1
2173  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 | 0x1 | Divide By 2
2174  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 | 0x2 | Divide By 4
2175  * ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 | 0x3 | Divide By 8
2176  *
2177  * Field Access Macros:
2178  *
2179  */
2180 /*
2181  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
2182  *
2183  * Divide By 1
2184  */
2185 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 0x0
2186 /*
2187  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
2188  *
2189  * Divide By 2
2190  */
2191 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 0x1
2192 /*
2193  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
2194  *
2195  * Divide By 4
2196  */
2197 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 0x2
2198 /*
2199  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
2200  *
2201  * Divide By 8
2202  */
2203 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 0x3
2204 
2205 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
2206 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
2207 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
2208 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_MSB 25
2209 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
2210 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_WIDTH 2
2211 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value. */
2212 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET_MSK 0x03000000
2213 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value. */
2214 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_CLR_MSK 0xfcffffff
2215 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field. */
2216 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_RESET 0x0
2217 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK field value from a register. */
2218 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_GET(value) (((value) & 0x03000000) >> 24)
2219 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value suitable for setting the register. */
2220 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET(value) (((value) << 24) & 0x03000000)
2221 
2222 /*
2223  * Field : CoreSight Trace Interface Clock Divider - cstraceclk
2224  *
2225  * The external cs_trace_clk divider is specified in this field. The cs_trace_clk
2226  * is used by the actual trace interface to the debugger. This divider is cascaded
2227  * after the cs_at_clk external divider.
2228  *
2229  * Field Enumeration Values:
2230  *
2231  * Enum | Value | Description
2232  * :--------------------------------------------|:------|:------------
2233  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 | 0x0 | Divide By 1
2234  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 | 0x1 | Divide By 2
2235  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 | 0x2 | Divide By 4
2236  * ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 | 0x3 | Divide By 8
2237  *
2238  * Field Access Macros:
2239  *
2240  */
2241 /*
2242  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
2243  *
2244  * Divide By 1
2245  */
2246 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 0x0
2247 /*
2248  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
2249  *
2250  * Divide By 2
2251  */
2252 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 0x1
2253 /*
2254  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
2255  *
2256  * Divide By 4
2257  */
2258 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 0x2
2259 /*
2260  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
2261  *
2262  * Divide By 8
2263  */
2264 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 0x3
2265 
2266 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
2267 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
2268 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
2269 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_MSB 27
2270 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
2271 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_WIDTH 2
2272 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value. */
2273 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET_MSK 0x0c000000
2274 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value. */
2275 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_CLR_MSK 0xf3ffffff
2276 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field. */
2277 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_RESET 0x2
2278 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK field value from a register. */
2279 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_GET(value) (((value) & 0x0c000000) >> 26)
2280 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value suitable for setting the register. */
2281 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET(value) (((value) << 26) & 0x0c000000)
2282 
2283 /*
2284  * Field : CoreSight Debug Clock Divider - cspdbgclk
2285  *
2286  * The external cs_pdbg_clk divider is specified in this field. This divider is
2287  * cascaded after the cs_at_clk external divider.
2288  *
2289  * Field Enumeration Values:
2290  *
2291  * Enum | Value | Description
2292  * :-------------------------------------------|:------|:------------
2293  * ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 | 0x0 | Divide By 1
2294  * ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 | 0x1 | Divide By 4
2295  *
2296  * Field Access Macros:
2297  *
2298  */
2299 /*
2300  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
2301  *
2302  * Divide By 1
2303  */
2304 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 0x0
2305 /*
2306  * Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
2307  *
2308  * Divide By 4
2309  */
2310 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 0x1
2311 
2312 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
2313 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
2314 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
2315 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_MSB 28
2316 /* The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
2317 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_WIDTH 1
2318 /* The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value. */
2319 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET_MSK 0x10000000
2320 /* The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value. */
2321 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_CLR_MSK 0xefffffff
2322 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field. */
2323 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_RESET 0x1
2324 /* Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK field value from a register. */
2325 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_GET(value) (((value) & 0x10000000) >> 28)
2326 /* Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value suitable for setting the register. */
2327 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET(value) (((value) << 28) & 0x10000000)
2328 
2329 #ifndef __ASSEMBLY__
2330 /*
2331  * WARNING: The C register and register group struct declarations are provided for
2332  * convenience and illustrative purposes. They should, however, be used with
2333  * caution as the C language standard provides no guarantees about the alignment or
2334  * atomicity of device memory accesses. The recommended practice for coding device
2335  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2336  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2337  * alt_write_dword() functions for 64 bit registers.
2338  *
2339  * The struct declaration for register ALT_CLKMGR_MAINPLL_NOCDIV.
2340  */
2341 struct ALT_CLKMGR_MAINPLL_NOCDIV_s
2342 {
2343  volatile uint32_t l4mainclk : 2; /* L4 Main Clock Divider */
2344  uint32_t : 6; /* *UNDEFINED* */
2345  volatile uint32_t l4mpclk : 2; /* L4 MP Clock Divider */
2346  uint32_t : 6; /* *UNDEFINED* */
2347  volatile uint32_t l4spclk : 2; /* L4 SP Clock Divider */
2348  uint32_t : 6; /* *UNDEFINED* */
2349  volatile uint32_t csatclk : 2; /* CoreSight Trace Clock Divider */
2350  volatile uint32_t cstraceclk : 2; /* CoreSight Trace Interface Clock Divider */
2351  volatile uint32_t cspdbgclk : 1; /* CoreSight Debug Clock Divider */
2352  uint32_t : 3; /* *UNDEFINED* */
2353 };
2354 
2355 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_NOCDIV. */
2356 typedef struct ALT_CLKMGR_MAINPLL_NOCDIV_s ALT_CLKMGR_MAINPLL_NOCDIV_t;
2357 #endif /* __ASSEMBLY__ */
2358 
2359 /* The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV register. */
2360 #define ALT_CLKMGR_MAINPLL_NOCDIV_RESET 0x18020100
2361 /* The byte offset of the ALT_CLKMGR_MAINPLL_NOCDIV register from the beginning of the component. */
2362 #define ALT_CLKMGR_MAINPLL_NOCDIV_OFST 0x40
2363 
2364 /*
2365  * Register : pllglob
2366  *
2367  * This refects register settings for both the channels of the main PLL
2368  *
2369  * Register Layout
2370  *
2371  * Bits | Access | Reset | Description
2372  * :--------|:-------|:------|:-------------------------------------
2373  * [0] | RW | 0x0 | main PLL power down
2374  * [1] | RW | 0x0 | main PLL reset
2375  * [2] | RW | 0x0 | main PLL mute
2376  * [3] | RW | 0x0 | Int mode sel
2377  * [4] | RW | 0x0 | Bypass clock source select control
2378  * [7:5] | ??? | 0x0 | *UNDEFINED*
2379  * [13:8] | RW | 0x1 | ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV
2380  * [15:14] | ??? | 0x0 | *UNDEFINED*
2381  * [17:16] | RW | 0x0 | Clock Source
2382  * [31:18] | ??? | 0x0 | *UNDEFINED*
2383  *
2384  */
2385 /*
2386  * Field : main PLL power down - pd
2387  *
2388  * Pll Disable/Power-Down Control. This is an active low signal
2389  *
2390  * 1: Pll Analog circuits are Enabled;
2391  *
2392  * 0: Pll is Disabled.
2393  *
2394  * By default the signal is asserted. Software should come and write '1' in this
2395  * reg to bring up the PLL
2396  *
2397  * Field Enumeration Values:
2398  *
2399  * Enum | Value | Description
2400  * :------------------------------------------|:------|:------------
2401  * ALT_CLKMGR_MAINPLL_PLLGLOB_PD_E_POWERDOWN | 0x0 |
2402  * ALT_CLKMGR_MAINPLL_PLLGLOB_PD_E_POWERUP | 0x1 |
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /*
2408  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_PD
2409  *
2410  */
2411 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_E_POWERDOWN 0x0
2412 /*
2413  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_PD
2414  *
2415  */
2416 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_E_POWERUP 0x1
2417 
2418 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field. */
2419 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_LSB 0
2420 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field. */
2421 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_MSB 0
2422 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field. */
2423 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_WIDTH 1
2424 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field value. */
2425 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
2426 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field value. */
2427 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_CLR_MSK 0xfffffffe
2428 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field. */
2429 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_RESET 0x0
2430 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_PD field value from a register. */
2431 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_GET(value) (((value) & 0x00000001) >> 0)
2432 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_PD register field value suitable for setting the register. */
2433 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET(value) (((value) << 0) & 0x00000001)
2434 
2435 /*
2436  * Field : main PLL reset - rst
2437  *
2438  * Pll Reset. Used to power down and initialize the synthesizer. Must be asserted
2439  * when power supply pins are applied.
2440  *
2441  * 1- Hard Reset Is De-Asserted;
2442  *
2443  * 0-Hard Reset Is Asserted.
2444  *
2445  * This is an active low signal.
2446  *
2447  * By default the signal is asserted. Software should come and write '1' in this
2448  * reg to bring up the PLL
2449  *
2450  * Field Access Macros:
2451  *
2452  */
2453 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field. */
2454 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_LSB 1
2455 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field. */
2456 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_MSB 1
2457 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field. */
2458 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_WIDTH 1
2459 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field value. */
2460 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
2461 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field value. */
2462 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_CLR_MSK 0xfffffffd
2463 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field. */
2464 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_RESET 0x0
2465 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_RST field value from a register. */
2466 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_GET(value) (((value) & 0x00000002) >> 1)
2467 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_RST register field value suitable for setting the register. */
2468 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET(value) (((value) << 1) & 0x00000002)
2469 
2470 /*
2471  * Field : main PLL mute - mute
2472  *
2473  * Mutes All Pll Outputs Glitch-Free:
2474  *
2475  * 1 - Output Clocks Are Muted To 1'B0;
2476  *
2477  * 0 - Output Clocks Are Active
2478  *
2479  * Field Enumeration Values:
2480  *
2481  * Enum | Value | Description
2482  * :-----------------------------------------|:------|:------------
2483  * ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_E_UNMUTE | 0x0 |
2484  * ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_E_MUTE | 0x1 |
2485  *
2486  * Field Access Macros:
2487  *
2488  */
2489 /*
2490  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE
2491  *
2492  */
2493 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_E_UNMUTE 0x0
2494 /*
2495  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE
2496  *
2497  */
2498 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_E_MUTE 0x1
2499 
2500 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field. */
2501 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_LSB 2
2502 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field. */
2503 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_MSB 2
2504 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field. */
2505 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_WIDTH 1
2506 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field value. */
2507 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_SET_MSK 0x00000004
2508 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field value. */
2509 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_CLR_MSK 0xfffffffb
2510 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field. */
2511 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_RESET 0x0
2512 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE field value from a register. */
2513 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_GET(value) (((value) & 0x00000004) >> 2)
2514 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE register field value suitable for setting the register. */
2515 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MUTE_SET(value) (((value) << 2) & 0x00000004)
2516 
2517 /*
2518  * Field : Int mode sel - modsel
2519  *
2520  * terger mode, feedback divident to PLL is considered integer. It can be only set
2521  * while the PLL is at reset or power down state. It cannot be switched
2522  * dynamically.
2523  *
2524  * Select: 1'B1 - Fractional Mode
2525  *
2526  * 1'B0 - Integer Mode;
2527  *
2528  * Field Enumeration Values:
2529  *
2530  * Enum | Value | Description
2531  * :------------------------------------------|:------|:------------
2532  * ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_E_INT | 0x0 |
2533  * ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_E_FLOAT | 0x1 |
2534  *
2535  * Field Access Macros:
2536  *
2537  */
2538 /*
2539  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL
2540  *
2541  */
2542 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_E_INT 0x0
2543 /*
2544  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL
2545  *
2546  */
2547 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_E_FLOAT 0x1
2548 
2549 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field. */
2550 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_LSB 3
2551 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field. */
2552 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_MSB 3
2553 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field. */
2554 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_WIDTH 1
2555 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field value. */
2556 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_SET_MSK 0x00000008
2557 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field value. */
2558 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_CLR_MSK 0xfffffff7
2559 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field. */
2560 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_RESET 0x0
2561 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL field value from a register. */
2562 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_GET(value) (((value) & 0x00000008) >> 3)
2563 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL register field value suitable for setting the register. */
2564 #define ALT_CLKMGR_MAINPLL_PLLGLOB_MODSEL_SET(value) (((value) << 3) & 0x00000008)
2565 
2566 /*
2567  * Field : Bypass clock source select control - bysctl
2568  *
2569  * This bit is resposible for selecting source for bypass clock in PLL bypass mode.
2570  * In the current version of the PLL. this feature is not supported.
2571  *
2572  * Therefore it can be '0' or '1'. The value does not matter at all.
2573  *
2574  * Making it '0' by defaut
2575  *
2576  * Field Access Macros:
2577  *
2578  */
2579 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field. */
2580 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_LSB 4
2581 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field. */
2582 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_MSB 4
2583 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field. */
2584 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_WIDTH 1
2585 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field value. */
2586 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_SET_MSK 0x00000010
2587 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field value. */
2588 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_CLR_MSK 0xffffffef
2589 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field. */
2590 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_RESET 0x0
2591 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL field value from a register. */
2592 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_GET(value) (((value) & 0x00000010) >> 4)
2593 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL register field value suitable for setting the register. */
2594 #define ALT_CLKMGR_MAINPLL_PLLGLOB_BYSCTL_SET(value) (((value) << 4) & 0x00000010)
2595 
2596 /*
2597  * Field : refclkdiv
2598  *
2599  * Reference Clock Divider Control Registers;
2600  *
2601  * Fref_eff = (Fref)/(refdiv[5:0])
2602  *
2603  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
2604  *
2605  * Fsyn = Frq_mul * Fref_eff
2606  *
2607  * (Fsyn /6) >= 3* Fref_eff
2608  *
2609  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
2610  *
2611  * Field Access Macros:
2612  *
2613  */
2614 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field. */
2615 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_LSB 8
2616 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field. */
2617 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_MSB 13
2618 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field. */
2619 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_WIDTH 6
2620 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field value. */
2621 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_SET_MSK 0x00003f00
2622 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field value. */
2623 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_CLR_MSK 0xffffc0ff
2624 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field. */
2625 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_RESET 0x1
2626 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV field value from a register. */
2627 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_GET(value) (((value) & 0x00003f00) >> 8)
2628 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV register field value suitable for setting the register. */
2629 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV_SET(value) (((value) << 8) & 0x00003f00)
2630 
2631 /*
2632  * Field : Clock Source - psrc
2633  *
2634  * Controls the VCO input clock source.
2635  *
2636  * Field Enumeration Values:
2637  *
2638  * Enum | Value | Description
2639  * :-----------------------------------------|:------|:--------------
2640  * ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_EOSC1 | 0x0 | eosc1_clk
2641  * ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_INTOSC | 0x1 | cb_intosc_clk
2642  * ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_F2S | 0x2 | f2s_free_clk
2643  *
2644  * Field Access Macros:
2645  *
2646  */
2647 /*
2648  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC
2649  *
2650  * eosc1_clk
2651  */
2652 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_EOSC1 0x0
2653 /*
2654  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC
2655  *
2656  * cb_intosc_clk
2657  */
2658 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_INTOSC 0x1
2659 /*
2660  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC
2661  *
2662  * f2s_free_clk
2663  */
2664 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_E_F2S 0x2
2665 
2666 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field. */
2667 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_LSB 16
2668 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field. */
2669 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_MSB 17
2670 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field. */
2671 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_WIDTH 2
2672 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field value. */
2673 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_SET_MSK 0x00030000
2674 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field value. */
2675 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_CLR_MSK 0xfffcffff
2676 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field. */
2677 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_RESET 0x0
2678 /* Extracts the ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC field value from a register. */
2679 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_GET(value) (((value) & 0x00030000) >> 16)
2680 /* Produces a ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC register field value suitable for setting the register. */
2681 #define ALT_CLKMGR_MAINPLL_PLLGLOB_PSRC_SET(value) (((value) << 16) & 0x00030000)
2682 
2683 #ifndef __ASSEMBLY__
2684 /*
2685  * WARNING: The C register and register group struct declarations are provided for
2686  * convenience and illustrative purposes. They should, however, be used with
2687  * caution as the C language standard provides no guarantees about the alignment or
2688  * atomicity of device memory accesses. The recommended practice for coding device
2689  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2690  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2691  * alt_write_dword() functions for 64 bit registers.
2692  *
2693  * The struct declaration for register ALT_CLKMGR_MAINPLL_PLLGLOB.
2694  */
2695 struct ALT_CLKMGR_MAINPLL_PLLGLOB_s
2696 {
2697  volatile uint32_t pd : 1; /* main PLL power down */
2698  volatile uint32_t rst : 1; /* main PLL reset */
2699  volatile uint32_t mute : 1; /* main PLL mute */
2700  volatile uint32_t modsel : 1; /* Int mode sel */
2701  volatile uint32_t bysctl : 1; /* Bypass clock source select control */
2702  uint32_t : 3; /* *UNDEFINED* */
2703  volatile uint32_t refclkdiv : 6; /* ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV */
2704  uint32_t : 2; /* *UNDEFINED* */
2705  volatile uint32_t psrc : 2; /* Clock Source */
2706  uint32_t : 14; /* *UNDEFINED* */
2707 };
2708 
2709 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_PLLGLOB. */
2710 typedef struct ALT_CLKMGR_MAINPLL_PLLGLOB_s ALT_CLKMGR_MAINPLL_PLLGLOB_t;
2711 #endif /* __ASSEMBLY__ */
2712 
2713 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLGLOB register. */
2714 #define ALT_CLKMGR_MAINPLL_PLLGLOB_RESET 0x00000100
2715 /* The byte offset of the ALT_CLKMGR_MAINPLL_PLLGLOB register from the beginning of the component. */
2716 #define ALT_CLKMGR_MAINPLL_PLLGLOB_OFST 0x44
2717 
2718 /*
2719  * Register : fdbck
2720  *
2721  * VCO freq register counters
2722  *
2723  * Register Layout
2724  *
2725  * Bits | Access | Reset | Description
2726  * :--------|:-------|:------|:------------------------------
2727  * [23:0] | RW | 0x0 | ALT_CLKMGR_MAINPLL_FDBCK_FDIV
2728  * [31:24] | RW | 0x2a | ALT_CLKMGR_MAINPLL_FDBCK_MDIV
2729  *
2730  */
2731 /*
2732  * Field : fdiv
2733  *
2734  * Fractional Synthesizer Center Frequency Control Word. The PLL Initially Operates
2735  * At The Frequency Based On The Mdiv Value Set At Reset. After Pll Exits Reset,
2736  * Any Change In Mdiv Value At The Interface Is Stored Internally.
2737  *
2738  * Fref_eff = (Fref)/(refdiv[5:0])
2739  *
2740  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
2741  *
2742  * Fsyn = Frq_mul * Fref_eff
2743  *
2744  * (Fsyn /6) >= 3* Fref_eff
2745  *
2746  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
2747  *
2748  * Field Access Macros:
2749  *
2750  */
2751 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field. */
2752 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_LSB 0
2753 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field. */
2754 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_MSB 23
2755 /* The width in bits of the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field. */
2756 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_WIDTH 24
2757 /* The mask used to set the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field value. */
2758 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_SET_MSK 0x00ffffff
2759 /* The mask used to clear the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field value. */
2760 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_CLR_MSK 0xff000000
2761 /* The reset value of the ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field. */
2762 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_RESET 0x0
2763 /* Extracts the ALT_CLKMGR_MAINPLL_FDBCK_FDIV field value from a register. */
2764 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_GET(value) (((value) & 0x00ffffff) >> 0)
2765 /* Produces a ALT_CLKMGR_MAINPLL_FDBCK_FDIV register field value suitable for setting the register. */
2766 #define ALT_CLKMGR_MAINPLL_FDBCK_FDIV_SET(value) (((value) << 0) & 0x00ffffff)
2767 
2768 /*
2769  * Field : mdiv
2770  *
2771  * Feedback Clock Divider. The Pll Initially Operates At The Frequency Based On The
2772  * Mdiv And Fdiv Values Set At Reset. After Pll Exits Reset, Any Change In Mdiv Or
2773  * Fdiv Values At The Interface Are Stored Internally. ictl_vpll_mdiv_a_[7:0] =
2774  * (Fvco /( Fref / ictl_vpll_refdiv_nt_[5:0])) - 6.
2775  *
2776  * Fref_eff = (Fref)/(refdiv[5:0])
2777  *
2778  * Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
2779  *
2780  * Fsyn = Frq_mul * Fref_eff
2781  *
2782  * (Fsyn /6) >= 3* Fref_eff
2783  *
2784  * Fock_vpll_pr1 = Fsyn /(pr1[7:0])
2785  *
2786  * Field Access Macros:
2787  *
2788  */
2789 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field. */
2790 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_LSB 24
2791 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field. */
2792 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_MSB 31
2793 /* The width in bits of the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field. */
2794 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_WIDTH 8
2795 /* The mask used to set the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field value. */
2796 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_SET_MSK 0xff000000
2797 /* The mask used to clear the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field value. */
2798 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_CLR_MSK 0x00ffffff
2799 /* The reset value of the ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field. */
2800 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_RESET 0x2a
2801 /* Extracts the ALT_CLKMGR_MAINPLL_FDBCK_MDIV field value from a register. */
2802 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_GET(value) (((value) & 0xff000000) >> 24)
2803 /* Produces a ALT_CLKMGR_MAINPLL_FDBCK_MDIV register field value suitable for setting the register. */
2804 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV_SET(value) (((value) << 24) & 0xff000000)
2805 
2806 #ifndef __ASSEMBLY__
2807 /*
2808  * WARNING: The C register and register group struct declarations are provided for
2809  * convenience and illustrative purposes. They should, however, be used with
2810  * caution as the C language standard provides no guarantees about the alignment or
2811  * atomicity of device memory accesses. The recommended practice for coding device
2812  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2813  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2814  * alt_write_dword() functions for 64 bit registers.
2815  *
2816  * The struct declaration for register ALT_CLKMGR_MAINPLL_FDBCK.
2817  */
2818 struct ALT_CLKMGR_MAINPLL_FDBCK_s
2819 {
2820  volatile uint32_t fdiv : 24; /* ALT_CLKMGR_MAINPLL_FDBCK_FDIV */
2821  volatile uint32_t mdiv : 8; /* ALT_CLKMGR_MAINPLL_FDBCK_MDIV */
2822 };
2823 
2824 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_FDBCK. */
2825 typedef struct ALT_CLKMGR_MAINPLL_FDBCK_s ALT_CLKMGR_MAINPLL_FDBCK_t;
2826 #endif /* __ASSEMBLY__ */
2827 
2828 /* The reset value of the ALT_CLKMGR_MAINPLL_FDBCK register. */
2829 #define ALT_CLKMGR_MAINPLL_FDBCK_RESET 0x2a000000
2830 /* The byte offset of the ALT_CLKMGR_MAINPLL_FDBCK register from the beginning of the component. */
2831 #define ALT_CLKMGR_MAINPLL_FDBCK_OFST 0x48
2832 
2833 /*
2834  * Register : mem
2835  *
2836  * Registers dealing with PLL internal memory access.
2837  *
2838  * Register Layout
2839  *
2840  * Bits | Access | Reset | Description
2841  * :--------|:-------|:------|:----------------------------
2842  * [9:0] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MEM_ADDR
2843  * [15:10] | ??? | 0x0 | *UNDEFINED*
2844  * [23:16] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MEM_WDAT
2845  * [24] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MEM_REQ
2846  * [25] | RW | 0x0 | ALT_CLKMGR_MAINPLL_MEM_WR
2847  * [31:26] | ??? | 0x0 | *UNDEFINED*
2848  *
2849  */
2850 /*
2851  * Field : addr
2852  *
2853  * PLL Memory Addressing
2854  *
2855  * Field Access Macros:
2856  *
2857  */
2858 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MEM_ADDR register field. */
2859 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_LSB 0
2860 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MEM_ADDR register field. */
2861 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_MSB 9
2862 /* The width in bits of the ALT_CLKMGR_MAINPLL_MEM_ADDR register field. */
2863 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_WIDTH 10
2864 /* The mask used to set the ALT_CLKMGR_MAINPLL_MEM_ADDR register field value. */
2865 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_SET_MSK 0x000003ff
2866 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MEM_ADDR register field value. */
2867 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_CLR_MSK 0xfffffc00
2868 /* The reset value of the ALT_CLKMGR_MAINPLL_MEM_ADDR register field. */
2869 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_RESET 0x0
2870 /* Extracts the ALT_CLKMGR_MAINPLL_MEM_ADDR field value from a register. */
2871 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2872 /* Produces a ALT_CLKMGR_MAINPLL_MEM_ADDR register field value suitable for setting the register. */
2873 #define ALT_CLKMGR_MAINPLL_MEM_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2874 
2875 /*
2876  * Field : wdat
2877  *
2878  * Memory Write Data
2879  *
2880  * Field Access Macros:
2881  *
2882  */
2883 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MEM_WDAT register field. */
2884 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_LSB 16
2885 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MEM_WDAT register field. */
2886 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_MSB 23
2887 /* The width in bits of the ALT_CLKMGR_MAINPLL_MEM_WDAT register field. */
2888 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_WIDTH 8
2889 /* The mask used to set the ALT_CLKMGR_MAINPLL_MEM_WDAT register field value. */
2890 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_SET_MSK 0x00ff0000
2891 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MEM_WDAT register field value. */
2892 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_CLR_MSK 0xff00ffff
2893 /* The reset value of the ALT_CLKMGR_MAINPLL_MEM_WDAT register field. */
2894 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_RESET 0x0
2895 /* Extracts the ALT_CLKMGR_MAINPLL_MEM_WDAT field value from a register. */
2896 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_GET(value) (((value) & 0x00ff0000) >> 16)
2897 /* Produces a ALT_CLKMGR_MAINPLL_MEM_WDAT register field value suitable for setting the register. */
2898 #define ALT_CLKMGR_MAINPLL_MEM_WDAT_SET(value) (((value) << 16) & 0x00ff0000)
2899 
2900 /*
2901  * Field : req
2902  *
2903  * Memory Request Signal
2904  *
2905  * Field Access Macros:
2906  *
2907  */
2908 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MEM_REQ register field. */
2909 #define ALT_CLKMGR_MAINPLL_MEM_REQ_LSB 24
2910 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MEM_REQ register field. */
2911 #define ALT_CLKMGR_MAINPLL_MEM_REQ_MSB 24
2912 /* The width in bits of the ALT_CLKMGR_MAINPLL_MEM_REQ register field. */
2913 #define ALT_CLKMGR_MAINPLL_MEM_REQ_WIDTH 1
2914 /* The mask used to set the ALT_CLKMGR_MAINPLL_MEM_REQ register field value. */
2915 #define ALT_CLKMGR_MAINPLL_MEM_REQ_SET_MSK 0x01000000
2916 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MEM_REQ register field value. */
2917 #define ALT_CLKMGR_MAINPLL_MEM_REQ_CLR_MSK 0xfeffffff
2918 /* The reset value of the ALT_CLKMGR_MAINPLL_MEM_REQ register field. */
2919 #define ALT_CLKMGR_MAINPLL_MEM_REQ_RESET 0x0
2920 /* Extracts the ALT_CLKMGR_MAINPLL_MEM_REQ field value from a register. */
2921 #define ALT_CLKMGR_MAINPLL_MEM_REQ_GET(value) (((value) & 0x01000000) >> 24)
2922 /* Produces a ALT_CLKMGR_MAINPLL_MEM_REQ register field value suitable for setting the register. */
2923 #define ALT_CLKMGR_MAINPLL_MEM_REQ_SET(value) (((value) << 24) & 0x01000000)
2924 
2925 /*
2926  * Field : wr
2927  *
2928  * Memory Read/Write Signal. 0 - Indicates A Read Transaction. 1 - Indicates A
2929  * Write Transaction
2930  *
2931  * Field Enumeration Values:
2932  *
2933  * Enum | Value | Description
2934  * :----------------------------------|:------|:------------
2935  * ALT_CLKMGR_MAINPLL_MEM_WR_E_READ | 0x0 |
2936  * ALT_CLKMGR_MAINPLL_MEM_WR_E_WRITE | 0x1 |
2937  *
2938  * Field Access Macros:
2939  *
2940  */
2941 /*
2942  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MEM_WR
2943  *
2944  */
2945 #define ALT_CLKMGR_MAINPLL_MEM_WR_E_READ 0x0
2946 /*
2947  * Enumerated value for register field ALT_CLKMGR_MAINPLL_MEM_WR
2948  *
2949  */
2950 #define ALT_CLKMGR_MAINPLL_MEM_WR_E_WRITE 0x1
2951 
2952 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MEM_WR register field. */
2953 #define ALT_CLKMGR_MAINPLL_MEM_WR_LSB 25
2954 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MEM_WR register field. */
2955 #define ALT_CLKMGR_MAINPLL_MEM_WR_MSB 25
2956 /* The width in bits of the ALT_CLKMGR_MAINPLL_MEM_WR register field. */
2957 #define ALT_CLKMGR_MAINPLL_MEM_WR_WIDTH 1
2958 /* The mask used to set the ALT_CLKMGR_MAINPLL_MEM_WR register field value. */
2959 #define ALT_CLKMGR_MAINPLL_MEM_WR_SET_MSK 0x02000000
2960 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MEM_WR register field value. */
2961 #define ALT_CLKMGR_MAINPLL_MEM_WR_CLR_MSK 0xfdffffff
2962 /* The reset value of the ALT_CLKMGR_MAINPLL_MEM_WR register field. */
2963 #define ALT_CLKMGR_MAINPLL_MEM_WR_RESET 0x0
2964 /* Extracts the ALT_CLKMGR_MAINPLL_MEM_WR field value from a register. */
2965 #define ALT_CLKMGR_MAINPLL_MEM_WR_GET(value) (((value) & 0x02000000) >> 25)
2966 /* Produces a ALT_CLKMGR_MAINPLL_MEM_WR register field value suitable for setting the register. */
2967 #define ALT_CLKMGR_MAINPLL_MEM_WR_SET(value) (((value) << 25) & 0x02000000)
2968 
2969 #ifndef __ASSEMBLY__
2970 /*
2971  * WARNING: The C register and register group struct declarations are provided for
2972  * convenience and illustrative purposes. They should, however, be used with
2973  * caution as the C language standard provides no guarantees about the alignment or
2974  * atomicity of device memory accesses. The recommended practice for coding device
2975  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2976  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2977  * alt_write_dword() functions for 64 bit registers.
2978  *
2979  * The struct declaration for register ALT_CLKMGR_MAINPLL_MEM.
2980  */
2981 struct ALT_CLKMGR_MAINPLL_MEM_s
2982 {
2983  volatile uint32_t addr : 10; /* ALT_CLKMGR_MAINPLL_MEM_ADDR */
2984  uint32_t : 6; /* *UNDEFINED* */
2985  volatile uint32_t wdat : 8; /* ALT_CLKMGR_MAINPLL_MEM_WDAT */
2986  volatile uint32_t req : 1; /* ALT_CLKMGR_MAINPLL_MEM_REQ */
2987  volatile uint32_t wr : 1; /* ALT_CLKMGR_MAINPLL_MEM_WR */
2988  uint32_t : 6; /* *UNDEFINED* */
2989 };
2990 
2991 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MEM. */
2992 typedef struct ALT_CLKMGR_MAINPLL_MEM_s ALT_CLKMGR_MAINPLL_MEM_t;
2993 #endif /* __ASSEMBLY__ */
2994 
2995 /* The reset value of the ALT_CLKMGR_MAINPLL_MEM register. */
2996 #define ALT_CLKMGR_MAINPLL_MEM_RESET 0x00000000
2997 /* The byte offset of the ALT_CLKMGR_MAINPLL_MEM register from the beginning of the component. */
2998 #define ALT_CLKMGR_MAINPLL_MEM_OFST 0x4c
2999 
3000 /*
3001  * Register : memstat
3002  *
3003  * Periph PLL memstatus register. contains ack and memory read data
3004  *
3005  * Register Layout
3006  *
3007  * Bits | Access | Reset | Description
3008  * :-------|:-------|:------|:---------------------------------
3009  * [7:0] | R | 0x0 | ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA
3010  * [31:8] | ??? | 0x0 | *UNDEFINED*
3011  *
3012  */
3013 /*
3014  * Field : rdata
3015  *
3016  * Memory Read Data
3017  *
3018  * Field Access Macros:
3019  *
3020  */
3021 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field. */
3022 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_LSB 0
3023 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field. */
3024 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_MSB 7
3025 /* The width in bits of the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field. */
3026 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_WIDTH 8
3027 /* The mask used to set the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field value. */
3028 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_SET_MSK 0x000000ff
3029 /* The mask used to clear the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field value. */
3030 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_CLR_MSK 0xffffff00
3031 /* The reset value of the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field. */
3032 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_RESET 0x0
3033 /* Extracts the ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA field value from a register. */
3034 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_GET(value) (((value) & 0x000000ff) >> 0)
3035 /* Produces a ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA register field value suitable for setting the register. */
3036 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA_SET(value) (((value) << 0) & 0x000000ff)
3037 
3038 #ifndef __ASSEMBLY__
3039 /*
3040  * WARNING: The C register and register group struct declarations are provided for
3041  * convenience and illustrative purposes. They should, however, be used with
3042  * caution as the C language standard provides no guarantees about the alignment or
3043  * atomicity of device memory accesses. The recommended practice for coding device
3044  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3045  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3046  * alt_write_dword() functions for 64 bit registers.
3047  *
3048  * The struct declaration for register ALT_CLKMGR_MAINPLL_MEMSTAT.
3049  */
3050 struct ALT_CLKMGR_MAINPLL_MEMSTAT_s
3051 {
3052  const volatile uint32_t rdata : 8; /* ALT_CLKMGR_MAINPLL_MEMSTAT_RDATA */
3053  uint32_t : 24; /* *UNDEFINED* */
3054 };
3055 
3056 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_MEMSTAT. */
3057 typedef struct ALT_CLKMGR_MAINPLL_MEMSTAT_s ALT_CLKMGR_MAINPLL_MEMSTAT_t;
3058 #endif /* __ASSEMBLY__ */
3059 
3060 /* The reset value of the ALT_CLKMGR_MAINPLL_MEMSTAT register. */
3061 #define ALT_CLKMGR_MAINPLL_MEMSTAT_RESET 0x00000000
3062 /* The byte offset of the ALT_CLKMGR_MAINPLL_MEMSTAT register from the beginning of the component. */
3063 #define ALT_CLKMGR_MAINPLL_MEMSTAT_OFST 0x50
3064 
3065 /*
3066  * Register : pllc0
3067  *
3068  * Channel C0 frequency settings for the main PLL
3069  *
3070  * Register Layout
3071  *
3072  * Bits | Access | Reset | Description
3073  * :--------|:-------|:------|:-------------------------------
3074  * [7:0] | RW | 0x2 | ALT_CLKMGR_MAINPLL_PLLC0_DIV
3075  * [23:8] | ??? | 0x0 | *UNDEFINED*
3076  * [24] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC0_PHINC
3077  * [25] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC0_PHRST
3078  * [26] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC0_BYPAS
3079  * [27] | RW | 0x1 | ALT_CLKMGR_MAINPLL_PLLC0_EN
3080  * [31:28] | ??? | 0x0 | *UNDEFINED*
3081  *
3082  */
3083 /*
3084  * Field : div
3085  *
3086  * PLL channel 0 divider ratio in binary code; Can be dynamically updated after
3087  * lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter
3088  * glitches for 8'd1 and 8d'2 cases.
3089  *
3090  * Field Access Macros:
3091  *
3092  */
3093 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field. */
3094 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_LSB 0
3095 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field. */
3096 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_MSB 7
3097 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field. */
3098 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_WIDTH 8
3099 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field value. */
3100 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_SET_MSK 0x000000ff
3101 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field value. */
3102 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_CLR_MSK 0xffffff00
3103 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0_DIV register field. */
3104 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_RESET 0x2
3105 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC0_DIV field value from a register. */
3106 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_GET(value) (((value) & 0x000000ff) >> 0)
3107 /* Produces a ALT_CLKMGR_MAINPLL_PLLC0_DIV register field value suitable for setting the register. */
3108 #define ALT_CLKMGR_MAINPLL_PLLC0_DIV_SET(value) (((value) << 0) & 0x000000ff)
3109 
3110 /*
3111  * Field : phinc
3112  *
3113  * When a positive edge is induced, one of the positive edges of PLLC0 clock is
3114  * pushed out by 1/8th of VCO period.
3115  *
3116  * Field Enumeration Values:
3117  *
3118  * Enum | Value | Description
3119  * :----------------------------------------|:------|:------------
3120  * ALT_CLKMGR_MAINPLL_PLLC0_PHINC_E_UNPUSH | 0x0 |
3121  * ALT_CLKMGR_MAINPLL_PLLC0_PHINC_E_PUSH | 0x1 |
3122  *
3123  * Field Access Macros:
3124  *
3125  */
3126 /*
3127  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_PHINC
3128  *
3129  */
3130 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_E_UNPUSH 0x0
3131 /*
3132  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_PHINC
3133  *
3134  */
3135 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_E_PUSH 0x1
3136 
3137 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field. */
3138 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_LSB 24
3139 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field. */
3140 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_MSB 24
3141 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field. */
3142 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_WIDTH 1
3143 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field value. */
3144 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_SET_MSK 0x01000000
3145 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field value. */
3146 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_CLR_MSK 0xfeffffff
3147 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field. */
3148 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_RESET 0x0
3149 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC0_PHINC field value from a register. */
3150 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_GET(value) (((value) & 0x01000000) >> 24)
3151 /* Produces a ALT_CLKMGR_MAINPLL_PLLC0_PHINC register field value suitable for setting the register. */
3152 #define ALT_CLKMGR_MAINPLL_PLLC0_PHINC_SET(value) (((value) << 24) & 0x01000000)
3153 
3154 /*
3155  * Field : phrst
3156  *
3157  * If ictl_vpll_pr1_phrst_a=1'b1, the phase of PLLC0 clock is reset to default
3158  * phase as the PLL is just started.
3159  *
3160  * Field Enumeration Values:
3161  *
3162  * Enum | Value | Description
3163  * :---------------------------------------------|:------|:------------
3164  * ALT_CLKMGR_MAINPLL_PLLC0_PHRST_E_RSTDEASSERT | 0x0 |
3165  * ALT_CLKMGR_MAINPLL_PLLC0_PHRST_E_RSTASSERT | 0x1 |
3166  *
3167  * Field Access Macros:
3168  *
3169  */
3170 /*
3171  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_PHRST
3172  *
3173  */
3174 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_E_RSTDEASSERT 0x0
3175 /*
3176  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_PHRST
3177  *
3178  */
3179 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_E_RSTASSERT 0x1
3180 
3181 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field. */
3182 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_LSB 25
3183 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field. */
3184 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_MSB 25
3185 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field. */
3186 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_WIDTH 1
3187 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field value. */
3188 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_SET_MSK 0x02000000
3189 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field value. */
3190 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_CLR_MSK 0xfdffffff
3191 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field. */
3192 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_RESET 0x0
3193 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC0_PHRST field value from a register. */
3194 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_GET(value) (((value) & 0x02000000) >> 25)
3195 /* Produces a ALT_CLKMGR_MAINPLL_PLLC0_PHRST register field value suitable for setting the register. */
3196 #define ALT_CLKMGR_MAINPLL_PLLC0_PHRST_SET(value) (((value) << 25) & 0x02000000)
3197 
3198 /*
3199  * Field : bypas
3200  *
3201  * PLL channel 0 output bypass. Before lock, it is muted, regardless of its value.
3202  *
3203  * After lock, if enabled (en==1) and bypass=1, this outputs refclk.
3204  *
3205  * Field Enumeration Values:
3206  *
3207  * Enum | Value | Description
3208  * :------------------------------------------|:------|:------------
3209  * ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_E_UNBYPASS | 0x0 |
3210  * ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_E_BYPASS | 0x1 |
3211  *
3212  * Field Access Macros:
3213  *
3214  */
3215 /*
3216  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_BYPAS
3217  *
3218  */
3219 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_E_UNBYPASS 0x0
3220 /*
3221  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_BYPAS
3222  *
3223  */
3224 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_E_BYPASS 0x1
3225 
3226 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field. */
3227 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_LSB 26
3228 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field. */
3229 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_MSB 26
3230 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field. */
3231 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_WIDTH 1
3232 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field value. */
3233 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_SET_MSK 0x04000000
3234 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field value. */
3235 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_CLR_MSK 0xfbffffff
3236 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field. */
3237 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_RESET 0x0
3238 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC0_BYPAS field value from a register. */
3239 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_GET(value) (((value) & 0x04000000) >> 26)
3240 /* Produces a ALT_CLKMGR_MAINPLL_PLLC0_BYPAS register field value suitable for setting the register. */
3241 #define ALT_CLKMGR_MAINPLL_PLLC0_BYPAS_SET(value) (((value) << 26) & 0x04000000)
3242 
3243 /*
3244  * Field : en
3245  *
3246  * PLL channel 0 output enable; the output is muted before lock signal is asserted,
3247  * regardless of the value; after lock is asserted, it is glitch-free enable
3248  * ock_vpll_pr1, if enabled
3249  *
3250  * Field Enumeration Values:
3251  *
3252  * Enum | Value | Description
3253  * :--------------------------------------|:------|:------------
3254  * ALT_CLKMGR_MAINPLL_PLLC0_EN_E_DISABLE | 0x0 |
3255  * ALT_CLKMGR_MAINPLL_PLLC0_EN_E_ENABLE | 0x1 |
3256  *
3257  * Field Access Macros:
3258  *
3259  */
3260 /*
3261  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_EN
3262  *
3263  */
3264 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_E_DISABLE 0x0
3265 /*
3266  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC0_EN
3267  *
3268  */
3269 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_E_ENABLE 0x1
3270 
3271 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_EN register field. */
3272 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_LSB 27
3273 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC0_EN register field. */
3274 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_MSB 27
3275 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC0_EN register field. */
3276 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_WIDTH 1
3277 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC0_EN register field value. */
3278 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_SET_MSK 0x08000000
3279 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC0_EN register field value. */
3280 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_CLR_MSK 0xf7ffffff
3281 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0_EN register field. */
3282 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_RESET 0x1
3283 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC0_EN field value from a register. */
3284 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_GET(value) (((value) & 0x08000000) >> 27)
3285 /* Produces a ALT_CLKMGR_MAINPLL_PLLC0_EN register field value suitable for setting the register. */
3286 #define ALT_CLKMGR_MAINPLL_PLLC0_EN_SET(value) (((value) << 27) & 0x08000000)
3287 
3288 #ifndef __ASSEMBLY__
3289 /*
3290  * WARNING: The C register and register group struct declarations are provided for
3291  * convenience and illustrative purposes. They should, however, be used with
3292  * caution as the C language standard provides no guarantees about the alignment or
3293  * atomicity of device memory accesses. The recommended practice for coding device
3294  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3295  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3296  * alt_write_dword() functions for 64 bit registers.
3297  *
3298  * The struct declaration for register ALT_CLKMGR_MAINPLL_PLLC0.
3299  */
3300 struct ALT_CLKMGR_MAINPLL_PLLC0_s
3301 {
3302  volatile uint32_t div : 8; /* ALT_CLKMGR_MAINPLL_PLLC0_DIV */
3303  uint32_t : 16; /* *UNDEFINED* */
3304  volatile uint32_t phinc : 1; /* ALT_CLKMGR_MAINPLL_PLLC0_PHINC */
3305  volatile uint32_t phrst : 1; /* ALT_CLKMGR_MAINPLL_PLLC0_PHRST */
3306  volatile uint32_t bypas : 1; /* ALT_CLKMGR_MAINPLL_PLLC0_BYPAS */
3307  volatile uint32_t en : 1; /* ALT_CLKMGR_MAINPLL_PLLC0_EN */
3308  uint32_t : 4; /* *UNDEFINED* */
3309 };
3310 
3311 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_PLLC0. */
3312 typedef struct ALT_CLKMGR_MAINPLL_PLLC0_s ALT_CLKMGR_MAINPLL_PLLC0_t;
3313 #endif /* __ASSEMBLY__ */
3314 
3315 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC0 register. */
3316 #define ALT_CLKMGR_MAINPLL_PLLC0_RESET 0x08000002
3317 /* The byte offset of the ALT_CLKMGR_MAINPLL_PLLC0 register from the beginning of the component. */
3318 #define ALT_CLKMGR_MAINPLL_PLLC0_OFST 0x54
3319 
3320 /*
3321  * Register : pllc1
3322  *
3323  * Channel C1 settings for the main PLL
3324  *
3325  * Register Layout
3326  *
3327  * Bits | Access | Reset | Description
3328  * :--------|:-------|:------|:-------------------------------
3329  * [7:0] | RW | 0x6 | ALT_CLKMGR_MAINPLL_PLLC1_DIV
3330  * [23:8] | ??? | 0x0 | *UNDEFINED*
3331  * [24] | RW | 0x1 | ALT_CLKMGR_MAINPLL_PLLC1_EN
3332  * [25] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC1_BYPAS
3333  * [26] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC1_PHINC
3334  * [27] | RW | 0x0 | ALT_CLKMGR_MAINPLL_PLLC1_PHRST
3335  * [31:28] | ??? | 0x0 | *UNDEFINED*
3336  *
3337  */
3338 /*
3339  * Field : div
3340  *
3341  * PLL channel 1 divider ratio in binary code; Can be dynamically updated after
3342  * lock signal is asserted, glitch-free from 8'd3 to 8'd255; could encounter
3343  * glitches for 8'd1 and 8d'2 cases.
3344  *
3345  * Field Access Macros:
3346  *
3347  */
3348 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field. */
3349 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_LSB 0
3350 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field. */
3351 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_MSB 7
3352 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field. */
3353 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_WIDTH 8
3354 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field value. */
3355 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_SET_MSK 0x000000ff
3356 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field value. */
3357 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_CLR_MSK 0xffffff00
3358 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1_DIV register field. */
3359 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_RESET 0x6
3360 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC1_DIV field value from a register. */
3361 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_GET(value) (((value) & 0x000000ff) >> 0)
3362 /* Produces a ALT_CLKMGR_MAINPLL_PLLC1_DIV register field value suitable for setting the register. */
3363 #define ALT_CLKMGR_MAINPLL_PLLC1_DIV_SET(value) (((value) << 0) & 0x000000ff)
3364 
3365 /*
3366  * Field : en
3367  *
3368  * PLL channel 1 output enable; the output is muted before lock signal is asserted,
3369  * regardless of the value; after lock is asserted, it is glitch-free enable
3370  * ock_vpll_pr1, if enabled
3371  *
3372  * Field Enumeration Values:
3373  *
3374  * Enum | Value | Description
3375  * :--------------------------------------|:------|:------------
3376  * ALT_CLKMGR_MAINPLL_PLLC1_EN_E_DISABLE | 0x0 |
3377  * ALT_CLKMGR_MAINPLL_PLLC1_EN_E_ENABLE | 0x1 |
3378  *
3379  * Field Access Macros:
3380  *
3381  */
3382 /*
3383  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_EN
3384  *
3385  */
3386 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_E_DISABLE 0x0
3387 /*
3388  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_EN
3389  *
3390  */
3391 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_E_ENABLE 0x1
3392 
3393 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_EN register field. */
3394 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_LSB 24
3395 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_EN register field. */
3396 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_MSB 24
3397 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC1_EN register field. */
3398 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_WIDTH 1
3399 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC1_EN register field value. */
3400 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_SET_MSK 0x01000000
3401 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC1_EN register field value. */
3402 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_CLR_MSK 0xfeffffff
3403 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1_EN register field. */
3404 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_RESET 0x1
3405 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC1_EN field value from a register. */
3406 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_GET(value) (((value) & 0x01000000) >> 24)
3407 /* Produces a ALT_CLKMGR_MAINPLL_PLLC1_EN register field value suitable for setting the register. */
3408 #define ALT_CLKMGR_MAINPLL_PLLC1_EN_SET(value) (((value) << 24) & 0x01000000)
3409 
3410 /*
3411  * Field : bypas
3412  *
3413  * PLL channel 1 output bypass; before lock, it is muted, regardless of its value.
3414  * After lock, if enabled and bypass=1, this outputs refclk.
3415  *
3416  * Field Enumeration Values:
3417  *
3418  * Enum | Value | Description
3419  * :------------------------------------------|:------|:------------
3420  * ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_E_UNBYPASS | 0x0 |
3421  * ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_E_BYPASS | 0x1 |
3422  *
3423  * Field Access Macros:
3424  *
3425  */
3426 /*
3427  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_BYPAS
3428  *
3429  */
3430 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_E_UNBYPASS 0x0
3431 /*
3432  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_BYPAS
3433  *
3434  */
3435 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_E_BYPASS 0x1
3436 
3437 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field. */
3438 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_LSB 25
3439 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field. */
3440 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_MSB 25
3441 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field. */
3442 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_WIDTH 1
3443 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field value. */
3444 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_SET_MSK 0x02000000
3445 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field value. */
3446 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_CLR_MSK 0xfdffffff
3447 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field. */
3448 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_RESET 0x0
3449 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC1_BYPAS field value from a register. */
3450 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_GET(value) (((value) & 0x02000000) >> 25)
3451 /* Produces a ALT_CLKMGR_MAINPLL_PLLC1_BYPAS register field value suitable for setting the register. */
3452 #define ALT_CLKMGR_MAINPLL_PLLC1_BYPAS_SET(value) (((value) << 25) & 0x02000000)
3453 
3454 /*
3455  * Field : phinc
3456  *
3457  * When a positive edge is induced, one of the positive edges of PLLC1 clock is
3458  * pushed out by 1/8th of VCO period.
3459  *
3460  * Field Enumeration Values:
3461  *
3462  * Enum | Value | Description
3463  * :----------------------------------------|:------|:------------
3464  * ALT_CLKMGR_MAINPLL_PLLC1_PHINC_E_UNPUSH | 0x0 |
3465  * ALT_CLKMGR_MAINPLL_PLLC1_PHINC_E_PUSH | 0x1 |
3466  *
3467  * Field Access Macros:
3468  *
3469  */
3470 /*
3471  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_PHINC
3472  *
3473  */
3474 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_E_UNPUSH 0x0
3475 /*
3476  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_PHINC
3477  *
3478  */
3479 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_E_PUSH 0x1
3480 
3481 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field. */
3482 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_LSB 26
3483 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field. */
3484 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_MSB 26
3485 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field. */
3486 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_WIDTH 1
3487 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field value. */
3488 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_SET_MSK 0x04000000
3489 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field value. */
3490 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_CLR_MSK 0xfbffffff
3491 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field. */
3492 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_RESET 0x0
3493 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC1_PHINC field value from a register. */
3494 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_GET(value) (((value) & 0x04000000) >> 26)
3495 /* Produces a ALT_CLKMGR_MAINPLL_PLLC1_PHINC register field value suitable for setting the register. */
3496 #define ALT_CLKMGR_MAINPLL_PLLC1_PHINC_SET(value) (((value) << 26) & 0x04000000)
3497 
3498 /*
3499  * Field : phrst
3500  *
3501  * If ictl_vpll_pr1_phrst_a=1'b1, the phase of PLLC1 clock is reset to default
3502  * phase as the PLL is just started.
3503  *
3504  * Field Enumeration Values:
3505  *
3506  * Enum | Value | Description
3507  * :---------------------------------------------|:------|:------------
3508  * ALT_CLKMGR_MAINPLL_PLLC1_PHRST_E_RSTDEASSERT | 0x0 |
3509  * ALT_CLKMGR_MAINPLL_PLLC1_PHRST_E_RSTASSERT | 0x1 |
3510  *
3511  * Field Access Macros:
3512  *
3513  */
3514 /*
3515  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_PHRST
3516  *
3517  */
3518 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_E_RSTDEASSERT 0x0
3519 /*
3520  * Enumerated value for register field ALT_CLKMGR_MAINPLL_PLLC1_PHRST
3521  *
3522  */
3523 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_E_RSTASSERT 0x1
3524 
3525 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field. */
3526 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_LSB 27
3527 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field. */
3528 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_MSB 27
3529 /* The width in bits of the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field. */
3530 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_WIDTH 1
3531 /* The mask used to set the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field value. */
3532 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_SET_MSK 0x08000000
3533 /* The mask used to clear the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field value. */
3534 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_CLR_MSK 0xf7ffffff
3535 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field. */
3536 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_RESET 0x0
3537 /* Extracts the ALT_CLKMGR_MAINPLL_PLLC1_PHRST field value from a register. */
3538 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_GET(value) (((value) & 0x08000000) >> 27)
3539 /* Produces a ALT_CLKMGR_MAINPLL_PLLC1_PHRST register field value suitable for setting the register. */
3540 #define ALT_CLKMGR_MAINPLL_PLLC1_PHRST_SET(value) (((value) << 27) & 0x08000000)
3541 
3542 #ifndef __ASSEMBLY__
3543 /*
3544  * WARNING: The C register and register group struct declarations are provided for
3545  * convenience and illustrative purposes. They should, however, be used with
3546  * caution as the C language standard provides no guarantees about the alignment or
3547  * atomicity of device memory accesses. The recommended practice for coding device
3548  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3549  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3550  * alt_write_dword() functions for 64 bit registers.
3551  *
3552  * The struct declaration for register ALT_CLKMGR_MAINPLL_PLLC1.
3553  */
3554 struct ALT_CLKMGR_MAINPLL_PLLC1_s
3555 {
3556  volatile uint32_t div : 8; /* ALT_CLKMGR_MAINPLL_PLLC1_DIV */
3557  uint32_t : 16; /* *UNDEFINED* */
3558  volatile uint32_t en : 1; /* ALT_CLKMGR_MAINPLL_PLLC1_EN */
3559  volatile uint32_t bypas : 1; /* ALT_CLKMGR_MAINPLL_PLLC1_BYPAS */
3560  volatile uint32_t phinc : 1; /* ALT_CLKMGR_MAINPLL_PLLC1_PHINC */
3561  volatile uint32_t phrst : 1; /* ALT_CLKMGR_MAINPLL_PLLC1_PHRST */
3562  uint32_t : 4; /* *UNDEFINED* */
3563 };
3564 
3565 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_PLLC1. */
3566 typedef struct ALT_CLKMGR_MAINPLL_PLLC1_s ALT_CLKMGR_MAINPLL_PLLC1_t;
3567 #endif /* __ASSEMBLY__ */
3568 
3569 /* The reset value of the ALT_CLKMGR_MAINPLL_PLLC1 register. */
3570 #define ALT_CLKMGR_MAINPLL_PLLC1_RESET 0x01000006
3571 /* The byte offset of the ALT_CLKMGR_MAINPLL_PLLC1 register from the beginning of the component. */
3572 #define ALT_CLKMGR_MAINPLL_PLLC1_OFST 0x58
3573 
3574 /*
3575  * Register : vcocalib
3576  *
3577  * VCO calibration control registers.
3578  *
3579  * Register Layout
3580  *
3581  * Bits | Access | Reset | Description
3582  * :--------|:-------|:------|:-----------------------------------
3583  * [7:0] | RW | 0xb7 | ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT
3584  * [8] | ??? | 0x1 | *UNDEFINED*
3585  * [16:9] | RW | 0x4 | ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT
3586  * [22:17] | ??? | 0x0 | *UNDEFINED*
3587  * [24:23] | RW | 0x0 | ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN
3588  * [31:25] | ??? | 0x0 | *UNDEFINED*
3589  *
3590  */
3591 /*
3592  * Field : hscnt
3593  *
3594  * VCO calibration parameter.
3595  *
3596  * hscnt= (mdiv+ 6) * mscnt/ refdiv-9.
3597  *
3598  * It can be only set while the pll is at reset or power down state.
3599  *
3600  * It cannot be switched dynamically.
3601  *
3602  * Field Access Macros:
3603  *
3604  */
3605 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field. */
3606 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_LSB 0
3607 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field. */
3608 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_MSB 7
3609 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field. */
3610 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_WIDTH 8
3611 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field value. */
3612 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET_MSK 0x000000ff
3613 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field value. */
3614 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_CLR_MSK 0xffffff00
3615 /* The reset value of the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field. */
3616 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_RESET 0xb7
3617 /* Extracts the ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT field value from a register. */
3618 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_GET(value) (((value) & 0x000000ff) >> 0)
3619 /* Produces a ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT register field value suitable for setting the register. */
3620 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(value) (((value) << 0) & 0x000000ff)
3621 
3622 /*
3623  * Field : mscnt
3624  *
3625  * mscnt = 200/(fvco/fref).
3626  *
3627  * It can be only set while the PLL is at reset or power down state.
3628  *
3629  * It cannot be switched dynamically.
3630  *
3631  * Field Access Macros:
3632  *
3633  */
3634 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field. */
3635 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_LSB 9
3636 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field. */
3637 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_MSB 16
3638 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field. */
3639 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_WIDTH 8
3640 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field value. */
3641 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET_MSK 0x0001fe00
3642 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field value. */
3643 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_CLR_MSK 0xfffe01ff
3644 /* The reset value of the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field. */
3645 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_RESET 0x4
3646 /* Extracts the ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT field value from a register. */
3647 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_GET(value) (((value) & 0x0001fe00) >> 9)
3648 /* Produces a ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT register field value suitable for setting the register. */
3649 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(value) (((value) << 9) & 0x0001fe00)
3650 
3651 /*
3652  * Field : termin
3653  *
3654  * Termination Calibration Control Look-Up Table Select
3655  *
3656  * Field Access Macros:
3657  *
3658  */
3659 /* The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field. */
3660 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_LSB 23
3661 /* The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field. */
3662 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_MSB 24
3663 /* The width in bits of the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field. */
3664 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_WIDTH 2
3665 /* The mask used to set the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field value. */
3666 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_SET_MSK 0x01800000
3667 /* The mask used to clear the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field value. */
3668 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_CLR_MSK 0xfe7fffff
3669 /* The reset value of the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field. */
3670 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_RESET 0x0
3671 /* Extracts the ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN field value from a register. */
3672 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_GET(value) (((value) & 0x01800000) >> 23)
3673 /* Produces a ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN register field value suitable for setting the register. */
3674 #define ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN_SET(value) (((value) << 23) & 0x01800000)
3675 
3676 #ifndef __ASSEMBLY__
3677 /*
3678  * WARNING: The C register and register group struct declarations are provided for
3679  * convenience and illustrative purposes. They should, however, be used with
3680  * caution as the C language standard provides no guarantees about the alignment or
3681  * atomicity of device memory accesses. The recommended practice for coding device
3682  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3683  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3684  * alt_write_dword() functions for 64 bit registers.
3685  *
3686  * The struct declaration for register ALT_CLKMGR_MAINPLL_VCOCALIB.
3687  */
3688 struct ALT_CLKMGR_MAINPLL_VCOCALIB_s
3689 {
3690  volatile uint32_t hscnt : 8; /* ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT */
3691  uint32_t : 1; /* *UNDEFINED* */
3692  volatile uint32_t mscnt : 8; /* ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT */
3693  uint32_t : 6; /* *UNDEFINED* */
3694  volatile uint32_t termin : 2; /* ALT_CLKMGR_MAINPLL_VCOCALIB_TERMIN */
3695  uint32_t : 7; /* *UNDEFINED* */
3696 };
3697 
3698 /* The typedef declaration for register ALT_CLKMGR_MAINPLL_VCOCALIB. */
3699 typedef struct ALT_CLKMGR_MAINPLL_VCOCALIB_s ALT_CLKMGR_MAINPLL_VCOCALIB_t;
3700 #endif /* __ASSEMBLY__ */
3701 
3702 /* The reset value of the ALT_CLKMGR_MAINPLL_VCOCALIB register. */
3703 #define ALT_CLKMGR_MAINPLL_VCOCALIB_RESET 0x000009b7
3704 /* The byte offset of the ALT_CLKMGR_MAINPLL_VCOCALIB register from the beginning of the component. */
3705 #define ALT_CLKMGR_MAINPLL_VCOCALIB_OFST 0x5c
3706 
3707 #ifndef __ASSEMBLY__
3708 /*
3709  * WARNING: The C register and register group struct declarations are provided for
3710  * convenience and illustrative purposes. They should, however, be used with
3711  * caution as the C language standard provides no guarantees about the alignment or
3712  * atomicity of device memory accesses. The recommended practice for coding device
3713  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3714  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3715  * alt_write_dword() functions for 64 bit registers.
3716  *
3717  * The struct declaration for register group ALT_CLKMGR_MAINPLL.
3718  */
3719 struct ALT_CLKMGR_MAINPLL_s
3720 {
3721  volatile ALT_CLKMGR_MAINPLL_EN_t en; /* ALT_CLKMGR_MAINPLL_EN */
3722  volatile ALT_CLKMGR_MAINPLL_ENS_t ens; /* ALT_CLKMGR_MAINPLL_ENS */
3723  volatile ALT_CLKMGR_MAINPLL_ENR_t enr; /* ALT_CLKMGR_MAINPLL_ENR */
3724  volatile ALT_CLKMGR_MAINPLL_BYPASS_t bypass; /* ALT_CLKMGR_MAINPLL_BYPASS */
3725  volatile ALT_CLKMGR_MAINPLL_BYPASSS_t bypasss; /* ALT_CLKMGR_MAINPLL_BYPASSS */
3726  volatile ALT_CLKMGR_MAINPLL_BYPASSR_t bypassr; /* ALT_CLKMGR_MAINPLL_BYPASSR */
3727  volatile ALT_CLKMGR_MAINPLL_MPUCLK_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3728  volatile ALT_CLKMGR_MAINPLL_NOCCLK_t nocclk; /* ALT_CLKMGR_MAINPLL_NOCCLK */
3729  volatile ALT_CLKMGR_MAINPLL_CNTR2CLK_t cntr2clk; /* ALT_CLKMGR_MAINPLL_CNTR2CLK */
3730  volatile ALT_CLKMGR_MAINPLL_CNTR3CLK_t cntr3clk; /* ALT_CLKMGR_MAINPLL_CNTR3CLK */
3731  volatile ALT_CLKMGR_MAINPLL_CNTR4CLK_t cntr4clk; /* ALT_CLKMGR_MAINPLL_CNTR4CLK */
3732  volatile ALT_CLKMGR_MAINPLL_CNTR5CLK_t cntr5clk; /* ALT_CLKMGR_MAINPLL_CNTR5CLK */
3733  volatile ALT_CLKMGR_MAINPLL_CNTR6CLK_t cntr6clk; /* ALT_CLKMGR_MAINPLL_CNTR6CLK */
3734  volatile ALT_CLKMGR_MAINPLL_CNTR7CLK_t cntr7clk; /* ALT_CLKMGR_MAINPLL_CNTR7CLK */
3735  volatile ALT_CLKMGR_MAINPLL_CNTR8CLK_t cntr8clk; /* ALT_CLKMGR_MAINPLL_CNTR8CLK */
3736  volatile ALT_CLKMGR_MAINPLL_CNTR9CLK_t cntr9clk; /* ALT_CLKMGR_MAINPLL_CNTR9CLK */
3737  volatile ALT_CLKMGR_MAINPLL_NOCDIV_t nocdiv; /* ALT_CLKMGR_MAINPLL_NOCDIV */
3738  volatile ALT_CLKMGR_MAINPLL_PLLGLOB_t pllglob; /* ALT_CLKMGR_MAINPLL_PLLGLOB */
3739  volatile ALT_CLKMGR_MAINPLL_FDBCK_t fdbck; /* ALT_CLKMGR_MAINPLL_FDBCK */
3740  volatile ALT_CLKMGR_MAINPLL_MEM_t mem; /* ALT_CLKMGR_MAINPLL_MEM */
3741  volatile ALT_CLKMGR_MAINPLL_MEMSTAT_t memstat; /* ALT_CLKMGR_MAINPLL_MEMSTAT */
3742  volatile ALT_CLKMGR_MAINPLL_PLLC0_t pllc0; /* ALT_CLKMGR_MAINPLL_PLLC0 */
3743  volatile ALT_CLKMGR_MAINPLL_PLLC1_t pllc1; /* ALT_CLKMGR_MAINPLL_PLLC1 */
3744  volatile ALT_CLKMGR_MAINPLL_VCOCALIB_t vcocalib; /* ALT_CLKMGR_MAINPLL_VCOCALIB */
3745  volatile uint32_t _pad_0x60_0x70[4]; /* *UNDEFINED* */
3746 };
3747 
3748 /* The typedef declaration for register group ALT_CLKMGR_MAINPLL. */
3749 typedef struct ALT_CLKMGR_MAINPLL_s ALT_CLKMGR_MAINPLL_t;
3750 /* The struct declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3751 struct ALT_CLKMGR_MAINPLL_raw_s
3752 {
3753  volatile uint32_t en; /* ALT_CLKMGR_MAINPLL_EN */
3754  volatile uint32_t ens; /* ALT_CLKMGR_MAINPLL_ENS */
3755  volatile uint32_t enr; /* ALT_CLKMGR_MAINPLL_ENR */
3756  volatile uint32_t bypass; /* ALT_CLKMGR_MAINPLL_BYPASS */
3757  volatile uint32_t bypasss; /* ALT_CLKMGR_MAINPLL_BYPASSS */
3758  volatile uint32_t bypassr; /* ALT_CLKMGR_MAINPLL_BYPASSR */
3759  volatile uint32_t mpuclk; /* ALT_CLKMGR_MAINPLL_MPUCLK */
3760  volatile uint32_t nocclk; /* ALT_CLKMGR_MAINPLL_NOCCLK */
3761  volatile uint32_t cntr2clk; /* ALT_CLKMGR_MAINPLL_CNTR2CLK */
3762  volatile uint32_t cntr3clk; /* ALT_CLKMGR_MAINPLL_CNTR3CLK */
3763  volatile uint32_t cntr4clk; /* ALT_CLKMGR_MAINPLL_CNTR4CLK */
3764  volatile uint32_t cntr5clk; /* ALT_CLKMGR_MAINPLL_CNTR5CLK */
3765  volatile uint32_t cntr6clk; /* ALT_CLKMGR_MAINPLL_CNTR6CLK */
3766  volatile uint32_t cntr7clk; /* ALT_CLKMGR_MAINPLL_CNTR7CLK */
3767  volatile uint32_t cntr8clk; /* ALT_CLKMGR_MAINPLL_CNTR8CLK */
3768  volatile uint32_t cntr9clk; /* ALT_CLKMGR_MAINPLL_CNTR9CLK */
3769  volatile uint32_t nocdiv; /* ALT_CLKMGR_MAINPLL_NOCDIV */
3770  volatile uint32_t pllglob; /* ALT_CLKMGR_MAINPLL_PLLGLOB */
3771  volatile uint32_t fdbck; /* ALT_CLKMGR_MAINPLL_FDBCK */
3772  volatile uint32_t mem; /* ALT_CLKMGR_MAINPLL_MEM */
3773  volatile uint32_t memstat; /* ALT_CLKMGR_MAINPLL_MEMSTAT */
3774  volatile uint32_t pllc0; /* ALT_CLKMGR_MAINPLL_PLLC0 */
3775  volatile uint32_t pllc1; /* ALT_CLKMGR_MAINPLL_PLLC1 */
3776  volatile uint32_t vcocalib; /* ALT_CLKMGR_MAINPLL_VCOCALIB */
3777  volatile uint32_t _pad_0x60_0x70[4]; /* *UNDEFINED* */
3778 };
3779 
3780 /* The typedef declaration for the raw register contents of register group ALT_CLKMGR_MAINPLL. */
3781 typedef struct ALT_CLKMGR_MAINPLL_raw_s ALT_CLKMGR_MAINPLL_raw_t;
3782 #endif /* __ASSEMBLY__ */
3783 
3784 
3785 #ifdef __cplusplus
3786 }
3787 #endif /* __cplusplus */
3788 #endif /* __ALT_SOCAL_CLKMGR_MAINPLL_H__ */
3789