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alt_ecc.h
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32 
33 /* Altera - ALT_ECC */
34 
35 #ifndef __ALT_SOCAL_ECC_H__
36 #define __ALT_SOCAL_ECC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ECC
50  *
51  */
52 /*
53  * Register : IP_REV_ID
54  *
55  * <p>IP slicon revision ID</p>
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:------------------------
61  * [15:0] | R | 0x0 | ALT_ECC_IP_REV_ID_SIREV
62  * [31:16] | ??? | 0x0 | *UNDEFINED*
63  *
64  */
65 /*
66  * Field : SIREV
67  *
68  * <p>IP Rev#</p>
69  *
70  * <p>These bits indicate the silicon revision number.</p>
71  *
72  * Field Access Macros:
73  *
74  */
75 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_IP_REV_ID_SIREV_LSB 0
77 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_IP_REV_ID_SIREV_MSB 15
79 /* The width in bits of the ALT_ECC_IP_REV_ID_SIREV register field. */
80 #define ALT_ECC_IP_REV_ID_SIREV_WIDTH 16
81 /* The mask used to set the ALT_ECC_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
83 /* The mask used to clear the ALT_ECC_IP_REV_ID_SIREV register field value. */
84 #define ALT_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
85 /* The reset value of the ALT_ECC_IP_REV_ID_SIREV register field. */
86 #define ALT_ECC_IP_REV_ID_SIREV_RESET 0x0
87 /* Extracts the ALT_ECC_IP_REV_ID_SIREV field value from a register. */
88 #define ALT_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
89 /* Produces a ALT_ECC_IP_REV_ID_SIREV register field value suitable for setting the register. */
90 #define ALT_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
91 
92 #ifndef __ASSEMBLY__
93 /*
94  * WARNING: The C register and register group struct declarations are provided for
95  * convenience and illustrative purposes. They should, however, be used with
96  * caution as the C language standard provides no guarantees about the alignment or
97  * atomicity of device memory accesses. The recommended practice for coding device
98  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
99  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
100  * alt_write_dword() functions for 64 bit registers.
101  *
102  * The struct declaration for register ALT_ECC_IP_REV_ID.
103  */
104 struct ALT_ECC_IP_REV_ID_s
105 {
106  const volatile uint32_t SIREV : 16; /* ALT_ECC_IP_REV_ID_SIREV */
107  uint32_t : 16; /* *UNDEFINED* */
108 };
109 
110 /* The typedef declaration for register ALT_ECC_IP_REV_ID. */
111 typedef struct ALT_ECC_IP_REV_ID_s ALT_ECC_IP_REV_ID_t;
112 #endif /* __ASSEMBLY__ */
113 
114 /* The reset value of the ALT_ECC_IP_REV_ID register. */
115 #define ALT_ECC_IP_REV_ID_RESET 0x00000000
116 /* The byte offset of the ALT_ECC_IP_REV_ID register from the beginning of the component. */
117 #define ALT_ECC_IP_REV_ID_OFST 0x0
118 /* The address of the ALT_ECC_IP_REV_ID register. */
119 #define ALT_ECC_IP_REV_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_IP_REV_ID_OFST))
120 
121 /*
122  * Register : IP_REV_ID2
123  *
124  * <p>IP memory configuration</p>
125  *
126  * Register Layout
127  *
128  * Bits | Access | Reset | Description
129  * :--------|:-------|:------|:-------------------------------
130  * [4:0] | R | 0x0 | ALT_ECC_IP_REV_ID2_ADDR
131  * [9:5] | R | 0x0 | ALT_ECC_IP_REV_ID2_DAT
132  * [12:10] | R | 0x0 | ALT_ECC_IP_REV_ID2_ECC_SIZE
133  * [15:13] | R | 0x0 | ALT_ECC_IP_REV_ID2_RAM_TYPE
134  * [19:16] | R | 0x0 | ALT_ECC_IP_REV_ID2_LUT_TBL_DEP
135  * [31:20] | ??? | 0x0 | *UNDEFINED*
136  *
137  */
138 /*
139  * Field : ADDR
140  *
141  * <p>Number of address bits (This represent the memory size)Support 32 - 0 address
142  * bits.</p>
143  *
144  * <p>For example:</p>
145  *
146  * <p>10 - 1Kbytes memory size 2^10 - 1K</p>
147  *
148  * <p>15 - 32Kbytes memory size 2^15 - 32K</p>
149  *
150  * Field Access Macros:
151  *
152  */
153 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID2_ADDR register field. */
154 #define ALT_ECC_IP_REV_ID2_ADDR_LSB 0
155 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID2_ADDR register field. */
156 #define ALT_ECC_IP_REV_ID2_ADDR_MSB 4
157 /* The width in bits of the ALT_ECC_IP_REV_ID2_ADDR register field. */
158 #define ALT_ECC_IP_REV_ID2_ADDR_WIDTH 5
159 /* The mask used to set the ALT_ECC_IP_REV_ID2_ADDR register field value. */
160 #define ALT_ECC_IP_REV_ID2_ADDR_SET_MSK 0x0000001f
161 /* The mask used to clear the ALT_ECC_IP_REV_ID2_ADDR register field value. */
162 #define ALT_ECC_IP_REV_ID2_ADDR_CLR_MSK 0xffffffe0
163 /* The reset value of the ALT_ECC_IP_REV_ID2_ADDR register field. */
164 #define ALT_ECC_IP_REV_ID2_ADDR_RESET 0x0
165 /* Extracts the ALT_ECC_IP_REV_ID2_ADDR field value from a register. */
166 #define ALT_ECC_IP_REV_ID2_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
167 /* Produces a ALT_ECC_IP_REV_ID2_ADDR register field value suitable for setting the register. */
168 #define ALT_ECC_IP_REV_ID2_ADDR_SET(value) (((value) << 0) & 0x0000001f)
169 
170 /*
171  * Field : DAT
172  *
173  * <p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for
174  * exact data width size.</p>
175  *
176  * <p>0 - 8 bits</p>
177  *
178  * <p>1 - 16 bits</p>
179  *
180  * <p>2 - 32 bits</p>
181  *
182  * <p>3 - 35 bits</p>
183  *
184  * <p>4 - 64 bits</p>
185  *
186  * <p>5 - 128 bits</p>
187  *
188  * <p>6 - 256 bits</p>
189  *
190  * <p>7 - 512 bits</p>
191  *
192  * <p>Others - UNUSED</p>
193  *
194  * Field Access Macros:
195  *
196  */
197 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID2_DAT register field. */
198 #define ALT_ECC_IP_REV_ID2_DAT_LSB 5
199 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID2_DAT register field. */
200 #define ALT_ECC_IP_REV_ID2_DAT_MSB 9
201 /* The width in bits of the ALT_ECC_IP_REV_ID2_DAT register field. */
202 #define ALT_ECC_IP_REV_ID2_DAT_WIDTH 5
203 /* The mask used to set the ALT_ECC_IP_REV_ID2_DAT register field value. */
204 #define ALT_ECC_IP_REV_ID2_DAT_SET_MSK 0x000003e0
205 /* The mask used to clear the ALT_ECC_IP_REV_ID2_DAT register field value. */
206 #define ALT_ECC_IP_REV_ID2_DAT_CLR_MSK 0xfffffc1f
207 /* The reset value of the ALT_ECC_IP_REV_ID2_DAT register field. */
208 #define ALT_ECC_IP_REV_ID2_DAT_RESET 0x0
209 /* Extracts the ALT_ECC_IP_REV_ID2_DAT field value from a register. */
210 #define ALT_ECC_IP_REV_ID2_DAT_GET(value) (((value) & 0x000003e0) >> 5)
211 /* Produces a ALT_ECC_IP_REV_ID2_DAT register field value suitable for setting the register. */
212 #define ALT_ECC_IP_REV_ID2_DAT_SET(value) (((value) << 5) & 0x000003e0)
213 
214 /*
215  * Field : ECC_SIZE
216  *
217  * <p>ECC Size.</p>
218  *
219  * <p>Total number of ECC bits is dependent on the number of encoder/decoder
220  * implemented. This is specifying the width of the ECC syndrome.</p>
221  *
222  * <p>1 - syndrome is 5 bits</p>
223  *
224  * <p>2 - syndrome is 6 bits</p>
225  *
226  * <p>3 - syndrome is 7 bits</p>
227  *
228  * <p>4 - syndrome is 8 bits</p>
229  *
230  * <p>Others - UNUSED</p>
231  *
232  * Field Access Macros:
233  *
234  */
235 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID2_ECC_SIZE register field. */
236 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_LSB 10
237 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID2_ECC_SIZE register field. */
238 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_MSB 12
239 /* The width in bits of the ALT_ECC_IP_REV_ID2_ECC_SIZE register field. */
240 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_WIDTH 3
241 /* The mask used to set the ALT_ECC_IP_REV_ID2_ECC_SIZE register field value. */
242 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_SET_MSK 0x00001c00
243 /* The mask used to clear the ALT_ECC_IP_REV_ID2_ECC_SIZE register field value. */
244 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_CLR_MSK 0xffffe3ff
245 /* The reset value of the ALT_ECC_IP_REV_ID2_ECC_SIZE register field. */
246 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_RESET 0x0
247 /* Extracts the ALT_ECC_IP_REV_ID2_ECC_SIZE field value from a register. */
248 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_GET(value) (((value) & 0x00001c00) >> 10)
249 /* Produces a ALT_ECC_IP_REV_ID2_ECC_SIZE register field value suitable for setting the register. */
250 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_SET(value) (((value) << 10) & 0x00001c00)
251 
252 /*
253  * Field : RAM_TYPE
254  *
255  * <p>Defines RAM type.</p>
256  *
257  * <p>1 - single port</p>
258  *
259  * <p>2 - simple dual port</p>
260  *
261  * <p>3 - true dual port</p>
262  *
263  * <p>Others - UNUSED</p>
264  *
265  * Field Access Macros:
266  *
267  */
268 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID2_RAM_TYPE register field. */
269 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_LSB 13
270 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID2_RAM_TYPE register field. */
271 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_MSB 15
272 /* The width in bits of the ALT_ECC_IP_REV_ID2_RAM_TYPE register field. */
273 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_WIDTH 3
274 /* The mask used to set the ALT_ECC_IP_REV_ID2_RAM_TYPE register field value. */
275 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_SET_MSK 0x0000e000
276 /* The mask used to clear the ALT_ECC_IP_REV_ID2_RAM_TYPE register field value. */
277 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_CLR_MSK 0xffff1fff
278 /* The reset value of the ALT_ECC_IP_REV_ID2_RAM_TYPE register field. */
279 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_RESET 0x0
280 /* Extracts the ALT_ECC_IP_REV_ID2_RAM_TYPE field value from a register. */
281 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_GET(value) (((value) & 0x0000e000) >> 13)
282 /* Produces a ALT_ECC_IP_REV_ID2_RAM_TYPE register field value suitable for setting the register. */
283 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_SET(value) (((value) << 13) & 0x0000e000)
284 
285 /*
286  * Field : LUT_TBL_DEP
287  *
288  * <p>Lookup Table Depth.</p>
289  *
290  * <p><br />1 - 4 words (less than or equal) 64KB RAM size</p>
291  *
292  * <p>2 - 8 words (less than or equal) 128KB RAM size</p>
293  *
294  * <p>4 - 16 words (less than or equal) 256KB RAM size</p>
295  *
296  * <p>8 - 20 words (less than or equal) 512KB RAM size</p>
297  *
298  * <p>Others - UNUSED</p>
299  *
300  * Field Access Macros:
301  *
302  */
303 /* The Least Significant Bit (LSB) position of the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field. */
304 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_LSB 16
305 /* The Most Significant Bit (MSB) position of the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field. */
306 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_MSB 19
307 /* The width in bits of the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field. */
308 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_WIDTH 4
309 /* The mask used to set the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field value. */
310 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_SET_MSK 0x000f0000
311 /* The mask used to clear the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field value. */
312 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_CLR_MSK 0xfff0ffff
313 /* The reset value of the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field. */
314 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_RESET 0x0
315 /* Extracts the ALT_ECC_IP_REV_ID2_LUT_TBL_DEP field value from a register. */
316 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_GET(value) (((value) & 0x000f0000) >> 16)
317 /* Produces a ALT_ECC_IP_REV_ID2_LUT_TBL_DEP register field value suitable for setting the register. */
318 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_SET(value) (((value) << 16) & 0x000f0000)
319 
320 #ifndef __ASSEMBLY__
321 /*
322  * WARNING: The C register and register group struct declarations are provided for
323  * convenience and illustrative purposes. They should, however, be used with
324  * caution as the C language standard provides no guarantees about the alignment or
325  * atomicity of device memory accesses. The recommended practice for coding device
326  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
327  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
328  * alt_write_dword() functions for 64 bit registers.
329  *
330  * The struct declaration for register ALT_ECC_IP_REV_ID2.
331  */
332 struct ALT_ECC_IP_REV_ID2_s
333 {
334  const volatile uint32_t ADDR : 5; /* ALT_ECC_IP_REV_ID2_ADDR */
335  const volatile uint32_t DAT : 5; /* ALT_ECC_IP_REV_ID2_DAT */
336  const volatile uint32_t ECC_SIZE : 3; /* ALT_ECC_IP_REV_ID2_ECC_SIZE */
337  const volatile uint32_t RAM_TYPE : 3; /* ALT_ECC_IP_REV_ID2_RAM_TYPE */
338  const volatile uint32_t LUT_TBL_DEP : 4; /* ALT_ECC_IP_REV_ID2_LUT_TBL_DEP */
339  uint32_t : 12; /* *UNDEFINED* */
340 };
341 
342 /* The typedef declaration for register ALT_ECC_IP_REV_ID2. */
343 typedef struct ALT_ECC_IP_REV_ID2_s ALT_ECC_IP_REV_ID2_t;
344 #endif /* __ASSEMBLY__ */
345 
346 /* The reset value of the ALT_ECC_IP_REV_ID2 register. */
347 #define ALT_ECC_IP_REV_ID2_RESET 0x00000000
348 /* The byte offset of the ALT_ECC_IP_REV_ID2 register from the beginning of the component. */
349 #define ALT_ECC_IP_REV_ID2_OFST 0x4
350 /* The address of the ALT_ECC_IP_REV_ID2 register. */
351 #define ALT_ECC_IP_REV_ID2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_IP_REV_ID2_OFST))
352 
353 /*
354  * Register : CTRL
355  *
356  * ECC Control Register
357  *
358  * Register Layout
359  *
360  * Bits | Access | Reset | Description
361  * :--------|:-------|:------|:----------------------------
362  * [0] | RW | 0x0 | ALT_ECC_CTRL_ECC_EN
363  * [1] | RW | 0x1 | ALT_ECC_CTRL_ECC_SLVERR_DIS
364  * [7:2] | ??? | 0x0 | *UNDEFINED*
365  * [8] | RW | 0x0 | ALT_ECC_CTRL_CNT_RSTA
366  * [9] | RW | 0x0 | ALT_ECC_CTRL_CNT_RSTB
367  * [15:10] | ??? | 0x0 | *UNDEFINED*
368  * [16] | RW | 0x0 | ALT_ECC_CTRL_INITA
369  * [23:17] | ??? | 0x0 | *UNDEFINED*
370  * [24] | RW | 0x0 | ALT_ECC_CTRL_INITB
371  * [31:25] | ??? | 0x0 | *UNDEFINED*
372  *
373  */
374 /*
375  * Field : ECC_EN
376  *
377  * Enable for the ECC detection and correction logic.
378  *
379  * Field Enumeration Values:
380  *
381  * Enum | Value | Description
382  * :------------------------------|:------|:------------
383  * ALT_ECC_CTRL_ECC_EN_E_DISABLE | 0x0 |
384  * ALT_ECC_CTRL_ECC_EN_E_ENABLE | 0x1 |
385  *
386  * Field Access Macros:
387  *
388  */
389 /*
390  * Enumerated value for register field ALT_ECC_CTRL_ECC_EN
391  *
392  */
393 #define ALT_ECC_CTRL_ECC_EN_E_DISABLE 0x0
394 /*
395  * Enumerated value for register field ALT_ECC_CTRL_ECC_EN
396  *
397  */
398 #define ALT_ECC_CTRL_ECC_EN_E_ENABLE 0x1
399 
400 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_ECC_EN register field. */
401 #define ALT_ECC_CTRL_ECC_EN_LSB 0
402 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_ECC_EN register field. */
403 #define ALT_ECC_CTRL_ECC_EN_MSB 0
404 /* The width in bits of the ALT_ECC_CTRL_ECC_EN register field. */
405 #define ALT_ECC_CTRL_ECC_EN_WIDTH 1
406 /* The mask used to set the ALT_ECC_CTRL_ECC_EN register field value. */
407 #define ALT_ECC_CTRL_ECC_EN_SET_MSK 0x00000001
408 /* The mask used to clear the ALT_ECC_CTRL_ECC_EN register field value. */
409 #define ALT_ECC_CTRL_ECC_EN_CLR_MSK 0xfffffffe
410 /* The reset value of the ALT_ECC_CTRL_ECC_EN register field. */
411 #define ALT_ECC_CTRL_ECC_EN_RESET 0x0
412 /* Extracts the ALT_ECC_CTRL_ECC_EN field value from a register. */
413 #define ALT_ECC_CTRL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
414 /* Produces a ALT_ECC_CTRL_ECC_EN register field value suitable for setting the register. */
415 #define ALT_ECC_CTRL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
416 
417 /*
418  * Field : ECC_SLVERR_DIS
419  *
420  * Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-
421  * interface.
422  *
423  * Field Enumeration Values:
424  *
425  * Enum | Value | Description
426  * :--------------------------------------|:------|:------------
427  * ALT_ECC_CTRL_ECC_SLVERR_DIS_E_DISABLE | 0x0 |
428  * ALT_ECC_CTRL_ECC_SLVERR_DIS_E_ENABLE | 0x1 |
429  *
430  * Field Access Macros:
431  *
432  */
433 /*
434  * Enumerated value for register field ALT_ECC_CTRL_ECC_SLVERR_DIS
435  *
436  */
437 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_E_DISABLE 0x0
438 /*
439  * Enumerated value for register field ALT_ECC_CTRL_ECC_SLVERR_DIS
440  *
441  */
442 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_E_ENABLE 0x1
443 
444 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_ECC_SLVERR_DIS register field. */
445 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_LSB 1
446 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_ECC_SLVERR_DIS register field. */
447 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_MSB 1
448 /* The width in bits of the ALT_ECC_CTRL_ECC_SLVERR_DIS register field. */
449 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_WIDTH 1
450 /* The mask used to set the ALT_ECC_CTRL_ECC_SLVERR_DIS register field value. */
451 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_SET_MSK 0x00000002
452 /* The mask used to clear the ALT_ECC_CTRL_ECC_SLVERR_DIS register field value. */
453 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_CLR_MSK 0xfffffffd
454 /* The reset value of the ALT_ECC_CTRL_ECC_SLVERR_DIS register field. */
455 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_RESET 0x1
456 /* Extracts the ALT_ECC_CTRL_ECC_SLVERR_DIS field value from a register. */
457 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_GET(value) (((value) & 0x00000002) >> 1)
458 /* Produces a ALT_ECC_CTRL_ECC_SLVERR_DIS register field value suitable for setting the register. */
459 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_SET(value) (((value) << 1) & 0x00000002)
460 
461 /*
462  * Field : CNT_RSTA
463  *
464  * Clear internal single-bit error counter A value to zero
465  *
466  * Field Access Macros:
467  *
468  */
469 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_CNT_RSTA register field. */
470 #define ALT_ECC_CTRL_CNT_RSTA_LSB 8
471 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_CNT_RSTA register field. */
472 #define ALT_ECC_CTRL_CNT_RSTA_MSB 8
473 /* The width in bits of the ALT_ECC_CTRL_CNT_RSTA register field. */
474 #define ALT_ECC_CTRL_CNT_RSTA_WIDTH 1
475 /* The mask used to set the ALT_ECC_CTRL_CNT_RSTA register field value. */
476 #define ALT_ECC_CTRL_CNT_RSTA_SET_MSK 0x00000100
477 /* The mask used to clear the ALT_ECC_CTRL_CNT_RSTA register field value. */
478 #define ALT_ECC_CTRL_CNT_RSTA_CLR_MSK 0xfffffeff
479 /* The reset value of the ALT_ECC_CTRL_CNT_RSTA register field. */
480 #define ALT_ECC_CTRL_CNT_RSTA_RESET 0x0
481 /* Extracts the ALT_ECC_CTRL_CNT_RSTA field value from a register. */
482 #define ALT_ECC_CTRL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
483 /* Produces a ALT_ECC_CTRL_CNT_RSTA register field value suitable for setting the register. */
484 #define ALT_ECC_CTRL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
485 
486 /*
487  * Field : CNT_RSTB
488  *
489  * Clear internal single-bit error counter B value to zero
490  *
491  * Field Access Macros:
492  *
493  */
494 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_CNT_RSTB register field. */
495 #define ALT_ECC_CTRL_CNT_RSTB_LSB 9
496 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_CNT_RSTB register field. */
497 #define ALT_ECC_CTRL_CNT_RSTB_MSB 9
498 /* The width in bits of the ALT_ECC_CTRL_CNT_RSTB register field. */
499 #define ALT_ECC_CTRL_CNT_RSTB_WIDTH 1
500 /* The mask used to set the ALT_ECC_CTRL_CNT_RSTB register field value. */
501 #define ALT_ECC_CTRL_CNT_RSTB_SET_MSK 0x00000200
502 /* The mask used to clear the ALT_ECC_CTRL_CNT_RSTB register field value. */
503 #define ALT_ECC_CTRL_CNT_RSTB_CLR_MSK 0xfffffdff
504 /* The reset value of the ALT_ECC_CTRL_CNT_RSTB register field. */
505 #define ALT_ECC_CTRL_CNT_RSTB_RESET 0x0
506 /* Extracts the ALT_ECC_CTRL_CNT_RSTB field value from a register. */
507 #define ALT_ECC_CTRL_CNT_RSTB_GET(value) (((value) & 0x00000200) >> 9)
508 /* Produces a ALT_ECC_CTRL_CNT_RSTB register field value suitable for setting the register. */
509 #define ALT_ECC_CTRL_CNT_RSTB_SET(value) (((value) << 9) & 0x00000200)
510 
511 /*
512  * Field : INITA
513  *
514  * Start for the hardware memory initialization PORTA.
515  *
516  * Field Access Macros:
517  *
518  */
519 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_INITA register field. */
520 #define ALT_ECC_CTRL_INITA_LSB 16
521 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_INITA register field. */
522 #define ALT_ECC_CTRL_INITA_MSB 16
523 /* The width in bits of the ALT_ECC_CTRL_INITA register field. */
524 #define ALT_ECC_CTRL_INITA_WIDTH 1
525 /* The mask used to set the ALT_ECC_CTRL_INITA register field value. */
526 #define ALT_ECC_CTRL_INITA_SET_MSK 0x00010000
527 /* The mask used to clear the ALT_ECC_CTRL_INITA register field value. */
528 #define ALT_ECC_CTRL_INITA_CLR_MSK 0xfffeffff
529 /* The reset value of the ALT_ECC_CTRL_INITA register field. */
530 #define ALT_ECC_CTRL_INITA_RESET 0x0
531 /* Extracts the ALT_ECC_CTRL_INITA field value from a register. */
532 #define ALT_ECC_CTRL_INITA_GET(value) (((value) & 0x00010000) >> 16)
533 /* Produces a ALT_ECC_CTRL_INITA register field value suitable for setting the register. */
534 #define ALT_ECC_CTRL_INITA_SET(value) (((value) << 16) & 0x00010000)
535 
536 /*
537  * Field : INITB
538  *
539  * Start for the hardware memory initialization PORTB.
540  *
541  * Field Access Macros:
542  *
543  */
544 /* The Least Significant Bit (LSB) position of the ALT_ECC_CTRL_INITB register field. */
545 #define ALT_ECC_CTRL_INITB_LSB 24
546 /* The Most Significant Bit (MSB) position of the ALT_ECC_CTRL_INITB register field. */
547 #define ALT_ECC_CTRL_INITB_MSB 24
548 /* The width in bits of the ALT_ECC_CTRL_INITB register field. */
549 #define ALT_ECC_CTRL_INITB_WIDTH 1
550 /* The mask used to set the ALT_ECC_CTRL_INITB register field value. */
551 #define ALT_ECC_CTRL_INITB_SET_MSK 0x01000000
552 /* The mask used to clear the ALT_ECC_CTRL_INITB register field value. */
553 #define ALT_ECC_CTRL_INITB_CLR_MSK 0xfeffffff
554 /* The reset value of the ALT_ECC_CTRL_INITB register field. */
555 #define ALT_ECC_CTRL_INITB_RESET 0x0
556 /* Extracts the ALT_ECC_CTRL_INITB field value from a register. */
557 #define ALT_ECC_CTRL_INITB_GET(value) (((value) & 0x01000000) >> 24)
558 /* Produces a ALT_ECC_CTRL_INITB register field value suitable for setting the register. */
559 #define ALT_ECC_CTRL_INITB_SET(value) (((value) << 24) & 0x01000000)
560 
561 #ifndef __ASSEMBLY__
562 /*
563  * WARNING: The C register and register group struct declarations are provided for
564  * convenience and illustrative purposes. They should, however, be used with
565  * caution as the C language standard provides no guarantees about the alignment or
566  * atomicity of device memory accesses. The recommended practice for coding device
567  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
568  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
569  * alt_write_dword() functions for 64 bit registers.
570  *
571  * The struct declaration for register ALT_ECC_CTRL.
572  */
573 struct ALT_ECC_CTRL_s
574 {
575  volatile uint32_t ECC_EN : 1; /* ALT_ECC_CTRL_ECC_EN */
576  volatile uint32_t ECC_SLVERR_DIS : 1; /* ALT_ECC_CTRL_ECC_SLVERR_DIS */
577  uint32_t : 6; /* *UNDEFINED* */
578  volatile uint32_t CNT_RSTA : 1; /* ALT_ECC_CTRL_CNT_RSTA */
579  volatile uint32_t CNT_RSTB : 1; /* ALT_ECC_CTRL_CNT_RSTB */
580  uint32_t : 6; /* *UNDEFINED* */
581  volatile uint32_t INITA : 1; /* ALT_ECC_CTRL_INITA */
582  uint32_t : 7; /* *UNDEFINED* */
583  volatile uint32_t INITB : 1; /* ALT_ECC_CTRL_INITB */
584  uint32_t : 7; /* *UNDEFINED* */
585 };
586 
587 /* The typedef declaration for register ALT_ECC_CTRL. */
588 typedef struct ALT_ECC_CTRL_s ALT_ECC_CTRL_t;
589 #endif /* __ASSEMBLY__ */
590 
591 /* The reset value of the ALT_ECC_CTRL register. */
592 #define ALT_ECC_CTRL_RESET 0x00000002
593 /* The byte offset of the ALT_ECC_CTRL register from the beginning of the component. */
594 #define ALT_ECC_CTRL_OFST 0x8
595 /* The address of the ALT_ECC_CTRL register. */
596 #define ALT_ECC_CTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_CTRL_OFST))
597 
598 /*
599  * Register : INITSTAT
600  *
601  * Initialization status used to indicate completion of hardware memory
602  * initialization done through CTRL.INITA / CTRL.INITB
603  *
604  * Register Layout
605  *
606  * Bits | Access | Reset | Description
607  * :-------|:-------|:------|:-------------------------------
608  * [0] | RW | 0x0 | ALT_ECC_INITSTAT_INITCOMPLETEA
609  * [7:1] | ??? | 0x0 | *UNDEFINED*
610  * [8] | RW | 0x0 | ALT_ECC_INITSTAT_INITCOMPLETEB
611  * [31:9] | ??? | 0x0 | *UNDEFINED*
612  *
613  */
614 /*
615  * Field : INITCOMPLETEA
616  *
617  * Indicate hardware memory initialization has completed on PORTA.
618  *
619  * Field Access Macros:
620  *
621  */
622 /* The Least Significant Bit (LSB) position of the ALT_ECC_INITSTAT_INITCOMPLETEA register field. */
623 #define ALT_ECC_INITSTAT_INITCOMPLETEA_LSB 0
624 /* The Most Significant Bit (MSB) position of the ALT_ECC_INITSTAT_INITCOMPLETEA register field. */
625 #define ALT_ECC_INITSTAT_INITCOMPLETEA_MSB 0
626 /* The width in bits of the ALT_ECC_INITSTAT_INITCOMPLETEA register field. */
627 #define ALT_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
628 /* The mask used to set the ALT_ECC_INITSTAT_INITCOMPLETEA register field value. */
629 #define ALT_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
630 /* The mask used to clear the ALT_ECC_INITSTAT_INITCOMPLETEA register field value. */
631 #define ALT_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
632 /* The reset value of the ALT_ECC_INITSTAT_INITCOMPLETEA register field. */
633 #define ALT_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
634 /* Extracts the ALT_ECC_INITSTAT_INITCOMPLETEA field value from a register. */
635 #define ALT_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
636 /* Produces a ALT_ECC_INITSTAT_INITCOMPLETEA register field value suitable for setting the register. */
637 #define ALT_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
638 
639 /*
640  * Field : INITCOMPLETEB
641  *
642  * Indicate hardware memory initialization has completed on PORTB.
643  *
644  * Field Access Macros:
645  *
646  */
647 /* The Least Significant Bit (LSB) position of the ALT_ECC_INITSTAT_INITCOMPLETEB register field. */
648 #define ALT_ECC_INITSTAT_INITCOMPLETEB_LSB 8
649 /* The Most Significant Bit (MSB) position of the ALT_ECC_INITSTAT_INITCOMPLETEB register field. */
650 #define ALT_ECC_INITSTAT_INITCOMPLETEB_MSB 8
651 /* The width in bits of the ALT_ECC_INITSTAT_INITCOMPLETEB register field. */
652 #define ALT_ECC_INITSTAT_INITCOMPLETEB_WIDTH 1
653 /* The mask used to set the ALT_ECC_INITSTAT_INITCOMPLETEB register field value. */
654 #define ALT_ECC_INITSTAT_INITCOMPLETEB_SET_MSK 0x00000100
655 /* The mask used to clear the ALT_ECC_INITSTAT_INITCOMPLETEB register field value. */
656 #define ALT_ECC_INITSTAT_INITCOMPLETEB_CLR_MSK 0xfffffeff
657 /* The reset value of the ALT_ECC_INITSTAT_INITCOMPLETEB register field. */
658 #define ALT_ECC_INITSTAT_INITCOMPLETEB_RESET 0x0
659 /* Extracts the ALT_ECC_INITSTAT_INITCOMPLETEB field value from a register. */
660 #define ALT_ECC_INITSTAT_INITCOMPLETEB_GET(value) (((value) & 0x00000100) >> 8)
661 /* Produces a ALT_ECC_INITSTAT_INITCOMPLETEB register field value suitable for setting the register. */
662 #define ALT_ECC_INITSTAT_INITCOMPLETEB_SET(value) (((value) << 8) & 0x00000100)
663 
664 #ifndef __ASSEMBLY__
665 /*
666  * WARNING: The C register and register group struct declarations are provided for
667  * convenience and illustrative purposes. They should, however, be used with
668  * caution as the C language standard provides no guarantees about the alignment or
669  * atomicity of device memory accesses. The recommended practice for coding device
670  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
671  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
672  * alt_write_dword() functions for 64 bit registers.
673  *
674  * The struct declaration for register ALT_ECC_INITSTAT.
675  */
676 struct ALT_ECC_INITSTAT_s
677 {
678  volatile uint32_t INITCOMPLETEA : 1; /* ALT_ECC_INITSTAT_INITCOMPLETEA */
679  uint32_t : 7; /* *UNDEFINED* */
680  volatile uint32_t INITCOMPLETEB : 1; /* ALT_ECC_INITSTAT_INITCOMPLETEB */
681  uint32_t : 23; /* *UNDEFINED* */
682 };
683 
684 /* The typedef declaration for register ALT_ECC_INITSTAT. */
685 typedef struct ALT_ECC_INITSTAT_s ALT_ECC_INITSTAT_t;
686 #endif /* __ASSEMBLY__ */
687 
688 /* The reset value of the ALT_ECC_INITSTAT register. */
689 #define ALT_ECC_INITSTAT_RESET 0x00000000
690 /* The byte offset of the ALT_ECC_INITSTAT register from the beginning of the component. */
691 #define ALT_ECC_INITSTAT_OFST 0xc
692 /* The address of the ALT_ECC_INITSTAT register. */
693 #define ALT_ECC_INITSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INITSTAT_OFST))
694 
695 /*
696  * Register : ERRINTEN
697  *
698  * Error Interrupt enable
699  *
700  * Register Layout
701  *
702  * Bits | Access | Reset | Description
703  * :-------|:-------|:------|:---------------------------
704  * [0] | RW | 0x0 | ALT_ECC_ERRINTEN_SERRINTEN
705  * [31:1] | ??? | 0x0 | *UNDEFINED*
706  *
707  */
708 /*
709  * Field : SERRINTEN
710  *
711  * This bit is used to enable single bit error interrupt of ECC RAM system
712  *
713  * Field Enumeration Values:
714  *
715  * Enum | Value | Description
716  * :-------------------------------------|:------|:------------
717  * ALT_ECC_ERRINTEN_SERRINTEN_E_DISABLE | 0x0 |
718  * ALT_ECC_ERRINTEN_SERRINTEN_E_ENABLE | 0x1 |
719  *
720  * Field Access Macros:
721  *
722  */
723 /*
724  * Enumerated value for register field ALT_ECC_ERRINTEN_SERRINTEN
725  *
726  */
727 #define ALT_ECC_ERRINTEN_SERRINTEN_E_DISABLE 0x0
728 /*
729  * Enumerated value for register field ALT_ECC_ERRINTEN_SERRINTEN
730  *
731  */
732 #define ALT_ECC_ERRINTEN_SERRINTEN_E_ENABLE 0x1
733 
734 /* The Least Significant Bit (LSB) position of the ALT_ECC_ERRINTEN_SERRINTEN register field. */
735 #define ALT_ECC_ERRINTEN_SERRINTEN_LSB 0
736 /* The Most Significant Bit (MSB) position of the ALT_ECC_ERRINTEN_SERRINTEN register field. */
737 #define ALT_ECC_ERRINTEN_SERRINTEN_MSB 0
738 /* The width in bits of the ALT_ECC_ERRINTEN_SERRINTEN register field. */
739 #define ALT_ECC_ERRINTEN_SERRINTEN_WIDTH 1
740 /* The mask used to set the ALT_ECC_ERRINTEN_SERRINTEN register field value. */
741 #define ALT_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
742 /* The mask used to clear the ALT_ECC_ERRINTEN_SERRINTEN register field value. */
743 #define ALT_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
744 /* The reset value of the ALT_ECC_ERRINTEN_SERRINTEN register field. */
745 #define ALT_ECC_ERRINTEN_SERRINTEN_RESET 0x0
746 /* Extracts the ALT_ECC_ERRINTEN_SERRINTEN field value from a register. */
747 #define ALT_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
748 /* Produces a ALT_ECC_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
749 #define ALT_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
750 
751 #ifndef __ASSEMBLY__
752 /*
753  * WARNING: The C register and register group struct declarations are provided for
754  * convenience and illustrative purposes. They should, however, be used with
755  * caution as the C language standard provides no guarantees about the alignment or
756  * atomicity of device memory accesses. The recommended practice for coding device
757  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
758  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
759  * alt_write_dword() functions for 64 bit registers.
760  *
761  * The struct declaration for register ALT_ECC_ERRINTEN.
762  */
763 struct ALT_ECC_ERRINTEN_s
764 {
765  volatile uint32_t SERRINTEN : 1; /* ALT_ECC_ERRINTEN_SERRINTEN */
766  uint32_t : 31; /* *UNDEFINED* */
767 };
768 
769 /* The typedef declaration for register ALT_ECC_ERRINTEN. */
770 typedef struct ALT_ECC_ERRINTEN_s ALT_ECC_ERRINTEN_t;
771 #endif /* __ASSEMBLY__ */
772 
773 /* The reset value of the ALT_ECC_ERRINTEN register. */
774 #define ALT_ECC_ERRINTEN_RESET 0x00000000
775 /* The byte offset of the ALT_ECC_ERRINTEN register from the beginning of the component. */
776 #define ALT_ECC_ERRINTEN_OFST 0x10
777 /* The address of the ALT_ECC_ERRINTEN register. */
778 #define ALT_ECC_ERRINTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTEN_OFST))
779 
780 /*
781  * Register : ERRINTENS
782  *
783  * Error interrupt set
784  *
785  * Register Layout
786  *
787  * Bits | Access | Reset | Description
788  * :-------|:-------|:------|:---------------------------
789  * [0] | RW | 0x0 | ALT_ECC_ERRINTENS_SERRINTS
790  * [31:1] | ??? | 0x0 | *UNDEFINED*
791  *
792  */
793 /*
794  * Field : SERRINTS
795  *
796  * This bit is used to enable ERRINTENS.SERRINTEN field
797  *
798  * Field Access Macros:
799  *
800  */
801 /* The Least Significant Bit (LSB) position of the ALT_ECC_ERRINTENS_SERRINTS register field. */
802 #define ALT_ECC_ERRINTENS_SERRINTS_LSB 0
803 /* The Most Significant Bit (MSB) position of the ALT_ECC_ERRINTENS_SERRINTS register field. */
804 #define ALT_ECC_ERRINTENS_SERRINTS_MSB 0
805 /* The width in bits of the ALT_ECC_ERRINTENS_SERRINTS register field. */
806 #define ALT_ECC_ERRINTENS_SERRINTS_WIDTH 1
807 /* The mask used to set the ALT_ECC_ERRINTENS_SERRINTS register field value. */
808 #define ALT_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
809 /* The mask used to clear the ALT_ECC_ERRINTENS_SERRINTS register field value. */
810 #define ALT_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
811 /* The reset value of the ALT_ECC_ERRINTENS_SERRINTS register field. */
812 #define ALT_ECC_ERRINTENS_SERRINTS_RESET 0x0
813 /* Extracts the ALT_ECC_ERRINTENS_SERRINTS field value from a register. */
814 #define ALT_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
815 /* Produces a ALT_ECC_ERRINTENS_SERRINTS register field value suitable for setting the register. */
816 #define ALT_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
817 
818 #ifndef __ASSEMBLY__
819 /*
820  * WARNING: The C register and register group struct declarations are provided for
821  * convenience and illustrative purposes. They should, however, be used with
822  * caution as the C language standard provides no guarantees about the alignment or
823  * atomicity of device memory accesses. The recommended practice for coding device
824  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
825  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
826  * alt_write_dword() functions for 64 bit registers.
827  *
828  * The struct declaration for register ALT_ECC_ERRINTENS.
829  */
830 struct ALT_ECC_ERRINTENS_s
831 {
832  volatile uint32_t SERRINTS : 1; /* ALT_ECC_ERRINTENS_SERRINTS */
833  uint32_t : 31; /* *UNDEFINED* */
834 };
835 
836 /* The typedef declaration for register ALT_ECC_ERRINTENS. */
837 typedef struct ALT_ECC_ERRINTENS_s ALT_ECC_ERRINTENS_t;
838 #endif /* __ASSEMBLY__ */
839 
840 /* The reset value of the ALT_ECC_ERRINTENS register. */
841 #define ALT_ECC_ERRINTENS_RESET 0x00000000
842 /* The byte offset of the ALT_ECC_ERRINTENS register from the beginning of the component. */
843 #define ALT_ECC_ERRINTENS_OFST 0x14
844 /* The address of the ALT_ECC_ERRINTENS register. */
845 #define ALT_ECC_ERRINTENS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTENS_OFST))
846 
847 /*
848  * Register : ERRINTENR
849  *
850  * Error Interrupt reset
851  *
852  * Register Layout
853  *
854  * Bits | Access | Reset | Description
855  * :-------|:-------|:------|:---------------------------
856  * [0] | RW | 0x0 | ALT_ECC_ERRINTENR_SERRINTR
857  * [31:1] | ??? | 0x0 | *UNDEFINED*
858  *
859  */
860 /*
861  * Field : SERRINTR
862  *
863  * This bit is used to disable ERRINTENS.SERRINTEN field
864  *
865  * Field Access Macros:
866  *
867  */
868 /* The Least Significant Bit (LSB) position of the ALT_ECC_ERRINTENR_SERRINTR register field. */
869 #define ALT_ECC_ERRINTENR_SERRINTR_LSB 0
870 /* The Most Significant Bit (MSB) position of the ALT_ECC_ERRINTENR_SERRINTR register field. */
871 #define ALT_ECC_ERRINTENR_SERRINTR_MSB 0
872 /* The width in bits of the ALT_ECC_ERRINTENR_SERRINTR register field. */
873 #define ALT_ECC_ERRINTENR_SERRINTR_WIDTH 1
874 /* The mask used to set the ALT_ECC_ERRINTENR_SERRINTR register field value. */
875 #define ALT_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
876 /* The mask used to clear the ALT_ECC_ERRINTENR_SERRINTR register field value. */
877 #define ALT_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
878 /* The reset value of the ALT_ECC_ERRINTENR_SERRINTR register field. */
879 #define ALT_ECC_ERRINTENR_SERRINTR_RESET 0x0
880 /* Extracts the ALT_ECC_ERRINTENR_SERRINTR field value from a register. */
881 #define ALT_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
882 /* Produces a ALT_ECC_ERRINTENR_SERRINTR register field value suitable for setting the register. */
883 #define ALT_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
884 
885 #ifndef __ASSEMBLY__
886 /*
887  * WARNING: The C register and register group struct declarations are provided for
888  * convenience and illustrative purposes. They should, however, be used with
889  * caution as the C language standard provides no guarantees about the alignment or
890  * atomicity of device memory accesses. The recommended practice for coding device
891  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
892  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
893  * alt_write_dword() functions for 64 bit registers.
894  *
895  * The struct declaration for register ALT_ECC_ERRINTENR.
896  */
897 struct ALT_ECC_ERRINTENR_s
898 {
899  volatile uint32_t SERRINTR : 1; /* ALT_ECC_ERRINTENR_SERRINTR */
900  uint32_t : 31; /* *UNDEFINED* */
901 };
902 
903 /* The typedef declaration for register ALT_ECC_ERRINTENR. */
904 typedef struct ALT_ECC_ERRINTENR_s ALT_ECC_ERRINTENR_t;
905 #endif /* __ASSEMBLY__ */
906 
907 /* The reset value of the ALT_ECC_ERRINTENR register. */
908 #define ALT_ECC_ERRINTENR_RESET 0x00000000
909 /* The byte offset of the ALT_ECC_ERRINTENR register from the beginning of the component. */
910 #define ALT_ECC_ERRINTENR_OFST 0x18
911 /* The address of the ALT_ECC_ERRINTENR register. */
912 #define ALT_ECC_ERRINTENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTENR_OFST))
913 
914 /*
915  * Register : INTMODE
916  *
917  * Interrupt modes of ECC RAM system
918  *
919  * Register Layout
920  *
921  * Bits | Access | Reset | Description
922  * :--------|:-------|:------|:-------------------------
923  * [0] | RW | 0x0 | ALT_ECC_INTMODE_INTMODE
924  * [7:1] | ??? | 0x0 | *UNDEFINED*
925  * [8] | RW | 0x0 | ALT_ECC_INTMODE_INTONOVF
926  * [15:9] | ??? | 0x0 | *UNDEFINED*
927  * [16] | RW | 0x0 | ALT_ECC_INTMODE_INTONCMP
928  * [31:17] | ??? | 0x0 | *UNDEFINED*
929  *
930  */
931 /*
932  * Field : INTMODE
933  *
934  * Interrupt mode for single-bit error
935  *
936  * Field Enumeration Values:
937  *
938  * Enum | Value | Description
939  * :----------------------------------------|:------|:------------
940  * ALT_ECC_INTMODE_INTMODE_E_INTR_ALL_ERR | 0x0 |
941  * ALT_ECC_INTMODE_INTMODE_E_INTR_DIST_ERR | 0x1 |
942  *
943  * Field Access Macros:
944  *
945  */
946 /*
947  * Enumerated value for register field ALT_ECC_INTMODE_INTMODE
948  *
949  * Enable interrupt on all error mode.
950  *
951  * Every single-bit error will cause interrupt.
952  */
953 #define ALT_ECC_INTMODE_INTMODE_E_INTR_ALL_ERR 0x0
954 /*
955  * Enumerated value for register field ALT_ECC_INTMODE_INTMODE
956  *
957  * Enable interrupt on distinct error.
958  *
959  * Every distinct error which is logged into LUT will cause interrupt.
960  */
961 #define ALT_ECC_INTMODE_INTMODE_E_INTR_DIST_ERR 0x1
962 
963 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTMODE_INTMODE register field. */
964 #define ALT_ECC_INTMODE_INTMODE_LSB 0
965 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTMODE_INTMODE register field. */
966 #define ALT_ECC_INTMODE_INTMODE_MSB 0
967 /* The width in bits of the ALT_ECC_INTMODE_INTMODE register field. */
968 #define ALT_ECC_INTMODE_INTMODE_WIDTH 1
969 /* The mask used to set the ALT_ECC_INTMODE_INTMODE register field value. */
970 #define ALT_ECC_INTMODE_INTMODE_SET_MSK 0x00000001
971 /* The mask used to clear the ALT_ECC_INTMODE_INTMODE register field value. */
972 #define ALT_ECC_INTMODE_INTMODE_CLR_MSK 0xfffffffe
973 /* The reset value of the ALT_ECC_INTMODE_INTMODE register field. */
974 #define ALT_ECC_INTMODE_INTMODE_RESET 0x0
975 /* Extracts the ALT_ECC_INTMODE_INTMODE field value from a register. */
976 #define ALT_ECC_INTMODE_INTMODE_GET(value) (((value) & 0x00000001) >> 0)
977 /* Produces a ALT_ECC_INTMODE_INTMODE register field value suitable for setting the register. */
978 #define ALT_ECC_INTMODE_INTMODE_SET(value) (((value) << 0) & 0x00000001)
979 
980 /*
981  * Field : INTONOVF
982  *
983  * Enable interrupt on overflow.
984  *
985  * Field Enumeration Values:
986  *
987  * Enum | Value | Description
988  * :-----------------------------------|:------|:------------
989  * ALT_ECC_INTMODE_INTONOVF_E_DISABLE | 0x0 |
990  * ALT_ECC_INTMODE_INTONOVF_E_ENABLE | 0x1 |
991  *
992  * Field Access Macros:
993  *
994  */
995 /*
996  * Enumerated value for register field ALT_ECC_INTMODE_INTONOVF
997  *
998  * Disable interrupt on LUT overflow
999  */
1000 #define ALT_ECC_INTMODE_INTONOVF_E_DISABLE 0x0
1001 /*
1002  * Enumerated value for register field ALT_ECC_INTMODE_INTONOVF
1003  *
1004  * Enable interrupt on LUT overflow
1005  */
1006 #define ALT_ECC_INTMODE_INTONOVF_E_ENABLE 0x1
1007 
1008 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTMODE_INTONOVF register field. */
1009 #define ALT_ECC_INTMODE_INTONOVF_LSB 8
1010 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTMODE_INTONOVF register field. */
1011 #define ALT_ECC_INTMODE_INTONOVF_MSB 8
1012 /* The width in bits of the ALT_ECC_INTMODE_INTONOVF register field. */
1013 #define ALT_ECC_INTMODE_INTONOVF_WIDTH 1
1014 /* The mask used to set the ALT_ECC_INTMODE_INTONOVF register field value. */
1015 #define ALT_ECC_INTMODE_INTONOVF_SET_MSK 0x00000100
1016 /* The mask used to clear the ALT_ECC_INTMODE_INTONOVF register field value. */
1017 #define ALT_ECC_INTMODE_INTONOVF_CLR_MSK 0xfffffeff
1018 /* The reset value of the ALT_ECC_INTMODE_INTONOVF register field. */
1019 #define ALT_ECC_INTMODE_INTONOVF_RESET 0x0
1020 /* Extracts the ALT_ECC_INTMODE_INTONOVF field value from a register. */
1021 #define ALT_ECC_INTMODE_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
1022 /* Produces a ALT_ECC_INTMODE_INTONOVF register field value suitable for setting the register. */
1023 #define ALT_ECC_INTMODE_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
1024 
1025 /*
1026  * Field : INTONCMP
1027  *
1028  * Enable interrupt on compare.
1029  *
1030  * Field Enumeration Values:
1031  *
1032  * Enum | Value | Description
1033  * :-----------------------------------|:------|:------------
1034  * ALT_ECC_INTMODE_INTONCMP_E_DISABLE | 0x0 |
1035  * ALT_ECC_INTMODE_INTONCMP_E_ENABLE | 0x1 |
1036  *
1037  * Field Access Macros:
1038  *
1039  */
1040 /*
1041  * Enumerated value for register field ALT_ECC_INTMODE_INTONCMP
1042  *
1043  * Disable interrupt on compare feature
1044  */
1045 #define ALT_ECC_INTMODE_INTONCMP_E_DISABLE 0x0
1046 /*
1047  * Enumerated value for register field ALT_ECC_INTMODE_INTONCMP
1048  *
1049  * Enable interrupt on compare feature
1050  */
1051 #define ALT_ECC_INTMODE_INTONCMP_E_ENABLE 0x1
1052 
1053 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTMODE_INTONCMP register field. */
1054 #define ALT_ECC_INTMODE_INTONCMP_LSB 16
1055 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTMODE_INTONCMP register field. */
1056 #define ALT_ECC_INTMODE_INTONCMP_MSB 16
1057 /* The width in bits of the ALT_ECC_INTMODE_INTONCMP register field. */
1058 #define ALT_ECC_INTMODE_INTONCMP_WIDTH 1
1059 /* The mask used to set the ALT_ECC_INTMODE_INTONCMP register field value. */
1060 #define ALT_ECC_INTMODE_INTONCMP_SET_MSK 0x00010000
1061 /* The mask used to clear the ALT_ECC_INTMODE_INTONCMP register field value. */
1062 #define ALT_ECC_INTMODE_INTONCMP_CLR_MSK 0xfffeffff
1063 /* The reset value of the ALT_ECC_INTMODE_INTONCMP register field. */
1064 #define ALT_ECC_INTMODE_INTONCMP_RESET 0x0
1065 /* Extracts the ALT_ECC_INTMODE_INTONCMP field value from a register. */
1066 #define ALT_ECC_INTMODE_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
1067 /* Produces a ALT_ECC_INTMODE_INTONCMP register field value suitable for setting the register. */
1068 #define ALT_ECC_INTMODE_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
1069 
1070 #ifndef __ASSEMBLY__
1071 /*
1072  * WARNING: The C register and register group struct declarations are provided for
1073  * convenience and illustrative purposes. They should, however, be used with
1074  * caution as the C language standard provides no guarantees about the alignment or
1075  * atomicity of device memory accesses. The recommended practice for coding device
1076  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1077  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1078  * alt_write_dword() functions for 64 bit registers.
1079  *
1080  * The struct declaration for register ALT_ECC_INTMODE.
1081  */
1082 struct ALT_ECC_INTMODE_s
1083 {
1084  volatile uint32_t INTMODE : 1; /* ALT_ECC_INTMODE_INTMODE */
1085  uint32_t : 7; /* *UNDEFINED* */
1086  volatile uint32_t INTONOVF : 1; /* ALT_ECC_INTMODE_INTONOVF */
1087  uint32_t : 7; /* *UNDEFINED* */
1088  volatile uint32_t INTONCMP : 1; /* ALT_ECC_INTMODE_INTONCMP */
1089  uint32_t : 15; /* *UNDEFINED* */
1090 };
1091 
1092 /* The typedef declaration for register ALT_ECC_INTMODE. */
1093 typedef struct ALT_ECC_INTMODE_s ALT_ECC_INTMODE_t;
1094 #endif /* __ASSEMBLY__ */
1095 
1096 /* The reset value of the ALT_ECC_INTMODE register. */
1097 #define ALT_ECC_INTMODE_RESET 0x00000000
1098 /* The byte offset of the ALT_ECC_INTMODE register from the beginning of the component. */
1099 #define ALT_ECC_INTMODE_OFST 0x1c
1100 /* The address of the ALT_ECC_INTMODE register. */
1101 #define ALT_ECC_INTMODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTMODE_OFST))
1102 
1103 /*
1104  * Register : INTSTAT
1105  *
1106  * This bit is used to enable interrupt generation on SERR lookup table overflow.
1107  * When all the entries in the table are valid=1 and this is bit is enabled,
1108  * serr_req signal will be asserted.
1109  *
1110  * Register Layout
1111  *
1112  * Bits | Access | Reset | Description
1113  * :--------|:-------|:------|:-------------------------
1114  * [0] | RW | 0x0 | ALT_ECC_INTSTAT_SERRPENA
1115  * [7:1] | ??? | 0x0 | *UNDEFINED*
1116  * [8] | RW | 0x0 | ALT_ECC_INTSTAT_DERRPENA
1117  * [15:9] | ??? | 0x0 | *UNDEFINED*
1118  * [16] | RW | 0x0 | ALT_ECC_INTSTAT_SERRPENB
1119  * [23:17] | ??? | 0x0 | *UNDEFINED*
1120  * [24] | RW | 0x0 | ALT_ECC_INTSTAT_DERRPENB
1121  * [31:25] | ??? | 0x0 | *UNDEFINED*
1122  *
1123  */
1124 /*
1125  * Field : SERRPENA
1126  *
1127  * Single-bit error pending for PORTA.
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTSTAT_SERRPENA register field. */
1133 #define ALT_ECC_INTSTAT_SERRPENA_LSB 0
1134 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTSTAT_SERRPENA register field. */
1135 #define ALT_ECC_INTSTAT_SERRPENA_MSB 0
1136 /* The width in bits of the ALT_ECC_INTSTAT_SERRPENA register field. */
1137 #define ALT_ECC_INTSTAT_SERRPENA_WIDTH 1
1138 /* The mask used to set the ALT_ECC_INTSTAT_SERRPENA register field value. */
1139 #define ALT_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
1140 /* The mask used to clear the ALT_ECC_INTSTAT_SERRPENA register field value. */
1141 #define ALT_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
1142 /* The reset value of the ALT_ECC_INTSTAT_SERRPENA register field. */
1143 #define ALT_ECC_INTSTAT_SERRPENA_RESET 0x0
1144 /* Extracts the ALT_ECC_INTSTAT_SERRPENA field value from a register. */
1145 #define ALT_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
1146 /* Produces a ALT_ECC_INTSTAT_SERRPENA register field value suitable for setting the register. */
1147 #define ALT_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
1148 
1149 /*
1150  * Field : DERRPENA
1151  *
1152  * Double-bit error pending for PORTA.
1153  *
1154  * Field Access Macros:
1155  *
1156  */
1157 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTSTAT_DERRPENA register field. */
1158 #define ALT_ECC_INTSTAT_DERRPENA_LSB 8
1159 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTSTAT_DERRPENA register field. */
1160 #define ALT_ECC_INTSTAT_DERRPENA_MSB 8
1161 /* The width in bits of the ALT_ECC_INTSTAT_DERRPENA register field. */
1162 #define ALT_ECC_INTSTAT_DERRPENA_WIDTH 1
1163 /* The mask used to set the ALT_ECC_INTSTAT_DERRPENA register field value. */
1164 #define ALT_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
1165 /* The mask used to clear the ALT_ECC_INTSTAT_DERRPENA register field value. */
1166 #define ALT_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
1167 /* The reset value of the ALT_ECC_INTSTAT_DERRPENA register field. */
1168 #define ALT_ECC_INTSTAT_DERRPENA_RESET 0x0
1169 /* Extracts the ALT_ECC_INTSTAT_DERRPENA field value from a register. */
1170 #define ALT_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
1171 /* Produces a ALT_ECC_INTSTAT_DERRPENA register field value suitable for setting the register. */
1172 #define ALT_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
1173 
1174 /*
1175  * Field : SERRPENB
1176  *
1177  * Single-bit error pending for PORTB.
1178  *
1179  * Field Access Macros:
1180  *
1181  */
1182 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTSTAT_SERRPENB register field. */
1183 #define ALT_ECC_INTSTAT_SERRPENB_LSB 16
1184 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTSTAT_SERRPENB register field. */
1185 #define ALT_ECC_INTSTAT_SERRPENB_MSB 16
1186 /* The width in bits of the ALT_ECC_INTSTAT_SERRPENB register field. */
1187 #define ALT_ECC_INTSTAT_SERRPENB_WIDTH 1
1188 /* The mask used to set the ALT_ECC_INTSTAT_SERRPENB register field value. */
1189 #define ALT_ECC_INTSTAT_SERRPENB_SET_MSK 0x00010000
1190 /* The mask used to clear the ALT_ECC_INTSTAT_SERRPENB register field value. */
1191 #define ALT_ECC_INTSTAT_SERRPENB_CLR_MSK 0xfffeffff
1192 /* The reset value of the ALT_ECC_INTSTAT_SERRPENB register field. */
1193 #define ALT_ECC_INTSTAT_SERRPENB_RESET 0x0
1194 /* Extracts the ALT_ECC_INTSTAT_SERRPENB field value from a register. */
1195 #define ALT_ECC_INTSTAT_SERRPENB_GET(value) (((value) & 0x00010000) >> 16)
1196 /* Produces a ALT_ECC_INTSTAT_SERRPENB register field value suitable for setting the register. */
1197 #define ALT_ECC_INTSTAT_SERRPENB_SET(value) (((value) << 16) & 0x00010000)
1198 
1199 /*
1200  * Field : DERRPENB
1201  *
1202  * Double-bit error pending PORTB.
1203  *
1204  * Field Access Macros:
1205  *
1206  */
1207 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTSTAT_DERRPENB register field. */
1208 #define ALT_ECC_INTSTAT_DERRPENB_LSB 24
1209 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTSTAT_DERRPENB register field. */
1210 #define ALT_ECC_INTSTAT_DERRPENB_MSB 24
1211 /* The width in bits of the ALT_ECC_INTSTAT_DERRPENB register field. */
1212 #define ALT_ECC_INTSTAT_DERRPENB_WIDTH 1
1213 /* The mask used to set the ALT_ECC_INTSTAT_DERRPENB register field value. */
1214 #define ALT_ECC_INTSTAT_DERRPENB_SET_MSK 0x01000000
1215 /* The mask used to clear the ALT_ECC_INTSTAT_DERRPENB register field value. */
1216 #define ALT_ECC_INTSTAT_DERRPENB_CLR_MSK 0xfeffffff
1217 /* The reset value of the ALT_ECC_INTSTAT_DERRPENB register field. */
1218 #define ALT_ECC_INTSTAT_DERRPENB_RESET 0x0
1219 /* Extracts the ALT_ECC_INTSTAT_DERRPENB field value from a register. */
1220 #define ALT_ECC_INTSTAT_DERRPENB_GET(value) (((value) & 0x01000000) >> 24)
1221 /* Produces a ALT_ECC_INTSTAT_DERRPENB register field value suitable for setting the register. */
1222 #define ALT_ECC_INTSTAT_DERRPENB_SET(value) (((value) << 24) & 0x01000000)
1223 
1224 #ifndef __ASSEMBLY__
1225 /*
1226  * WARNING: The C register and register group struct declarations are provided for
1227  * convenience and illustrative purposes. They should, however, be used with
1228  * caution as the C language standard provides no guarantees about the alignment or
1229  * atomicity of device memory accesses. The recommended practice for coding device
1230  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1231  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1232  * alt_write_dword() functions for 64 bit registers.
1233  *
1234  * The struct declaration for register ALT_ECC_INTSTAT.
1235  */
1236 struct ALT_ECC_INTSTAT_s
1237 {
1238  volatile uint32_t SERRPENA : 1; /* ALT_ECC_INTSTAT_SERRPENA */
1239  uint32_t : 7; /* *UNDEFINED* */
1240  volatile uint32_t DERRPENA : 1; /* ALT_ECC_INTSTAT_DERRPENA */
1241  uint32_t : 7; /* *UNDEFINED* */
1242  volatile uint32_t SERRPENB : 1; /* ALT_ECC_INTSTAT_SERRPENB */
1243  uint32_t : 7; /* *UNDEFINED* */
1244  volatile uint32_t DERRPENB : 1; /* ALT_ECC_INTSTAT_DERRPENB */
1245  uint32_t : 7; /* *UNDEFINED* */
1246 };
1247 
1248 /* The typedef declaration for register ALT_ECC_INTSTAT. */
1249 typedef struct ALT_ECC_INTSTAT_s ALT_ECC_INTSTAT_t;
1250 #endif /* __ASSEMBLY__ */
1251 
1252 /* The reset value of the ALT_ECC_INTSTAT register. */
1253 #define ALT_ECC_INTSTAT_RESET 0x00000000
1254 /* The byte offset of the ALT_ECC_INTSTAT register from the beginning of the component. */
1255 #define ALT_ECC_INTSTAT_OFST 0x20
1256 /* The address of the ALT_ECC_INTSTAT register. */
1257 #define ALT_ECC_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTSTAT_OFST))
1258 
1259 /*
1260  * Register : INTTEST
1261  *
1262  * This bits is used to test interrupt from ECC RAM to GIC
1263  *
1264  * Register Layout
1265  *
1266  * Bits | Access | Reset | Description
1267  * :--------|:-------|:------|:-----------------------
1268  * [0] | RW | 0x0 | ALT_ECC_INTTEST_TSERRA
1269  * [7:1] | ??? | 0x0 | *UNDEFINED*
1270  * [8] | RW | 0x0 | ALT_ECC_INTTEST_TDERRA
1271  * [15:9] | ??? | 0x0 | *UNDEFINED*
1272  * [16] | RW | 0x0 | ALT_ECC_INTTEST_TSERRB
1273  * [23:17] | ??? | 0x0 | *UNDEFINED*
1274  * [24] | RW | 0x0 | ALT_ECC_INTTEST_TDERRB
1275  * [31:25] | ??? | 0x0 | *UNDEFINED*
1276  *
1277  */
1278 /*
1279  * Field : TSERRA
1280  *
1281  * Test PORTA Single-bit error.
1282  *
1283  * Field Access Macros:
1284  *
1285  */
1286 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTTEST_TSERRA register field. */
1287 #define ALT_ECC_INTTEST_TSERRA_LSB 0
1288 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTTEST_TSERRA register field. */
1289 #define ALT_ECC_INTTEST_TSERRA_MSB 0
1290 /* The width in bits of the ALT_ECC_INTTEST_TSERRA register field. */
1291 #define ALT_ECC_INTTEST_TSERRA_WIDTH 1
1292 /* The mask used to set the ALT_ECC_INTTEST_TSERRA register field value. */
1293 #define ALT_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
1294 /* The mask used to clear the ALT_ECC_INTTEST_TSERRA register field value. */
1295 #define ALT_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
1296 /* The reset value of the ALT_ECC_INTTEST_TSERRA register field. */
1297 #define ALT_ECC_INTTEST_TSERRA_RESET 0x0
1298 /* Extracts the ALT_ECC_INTTEST_TSERRA field value from a register. */
1299 #define ALT_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
1300 /* Produces a ALT_ECC_INTTEST_TSERRA register field value suitable for setting the register. */
1301 #define ALT_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
1302 
1303 /*
1304  * Field : TDERRA
1305  *
1306  * Test PORTA Double-bit error.
1307  *
1308  * Field Access Macros:
1309  *
1310  */
1311 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTTEST_TDERRA register field. */
1312 #define ALT_ECC_INTTEST_TDERRA_LSB 8
1313 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTTEST_TDERRA register field. */
1314 #define ALT_ECC_INTTEST_TDERRA_MSB 8
1315 /* The width in bits of the ALT_ECC_INTTEST_TDERRA register field. */
1316 #define ALT_ECC_INTTEST_TDERRA_WIDTH 1
1317 /* The mask used to set the ALT_ECC_INTTEST_TDERRA register field value. */
1318 #define ALT_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
1319 /* The mask used to clear the ALT_ECC_INTTEST_TDERRA register field value. */
1320 #define ALT_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
1321 /* The reset value of the ALT_ECC_INTTEST_TDERRA register field. */
1322 #define ALT_ECC_INTTEST_TDERRA_RESET 0x0
1323 /* Extracts the ALT_ECC_INTTEST_TDERRA field value from a register. */
1324 #define ALT_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
1325 /* Produces a ALT_ECC_INTTEST_TDERRA register field value suitable for setting the register. */
1326 #define ALT_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
1327 
1328 /*
1329  * Field : TSERRB
1330  *
1331  * Test PORTB Single-bit error.
1332  *
1333  * Field Access Macros:
1334  *
1335  */
1336 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTTEST_TSERRB register field. */
1337 #define ALT_ECC_INTTEST_TSERRB_LSB 16
1338 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTTEST_TSERRB register field. */
1339 #define ALT_ECC_INTTEST_TSERRB_MSB 16
1340 /* The width in bits of the ALT_ECC_INTTEST_TSERRB register field. */
1341 #define ALT_ECC_INTTEST_TSERRB_WIDTH 1
1342 /* The mask used to set the ALT_ECC_INTTEST_TSERRB register field value. */
1343 #define ALT_ECC_INTTEST_TSERRB_SET_MSK 0x00010000
1344 /* The mask used to clear the ALT_ECC_INTTEST_TSERRB register field value. */
1345 #define ALT_ECC_INTTEST_TSERRB_CLR_MSK 0xfffeffff
1346 /* The reset value of the ALT_ECC_INTTEST_TSERRB register field. */
1347 #define ALT_ECC_INTTEST_TSERRB_RESET 0x0
1348 /* Extracts the ALT_ECC_INTTEST_TSERRB field value from a register. */
1349 #define ALT_ECC_INTTEST_TSERRB_GET(value) (((value) & 0x00010000) >> 16)
1350 /* Produces a ALT_ECC_INTTEST_TSERRB register field value suitable for setting the register. */
1351 #define ALT_ECC_INTTEST_TSERRB_SET(value) (((value) << 16) & 0x00010000)
1352 
1353 /*
1354  * Field : TDERRB
1355  *
1356  * Test PORTB Double-bit error.
1357  *
1358  * Field Access Macros:
1359  *
1360  */
1361 /* The Least Significant Bit (LSB) position of the ALT_ECC_INTTEST_TDERRB register field. */
1362 #define ALT_ECC_INTTEST_TDERRB_LSB 24
1363 /* The Most Significant Bit (MSB) position of the ALT_ECC_INTTEST_TDERRB register field. */
1364 #define ALT_ECC_INTTEST_TDERRB_MSB 24
1365 /* The width in bits of the ALT_ECC_INTTEST_TDERRB register field. */
1366 #define ALT_ECC_INTTEST_TDERRB_WIDTH 1
1367 /* The mask used to set the ALT_ECC_INTTEST_TDERRB register field value. */
1368 #define ALT_ECC_INTTEST_TDERRB_SET_MSK 0x01000000
1369 /* The mask used to clear the ALT_ECC_INTTEST_TDERRB register field value. */
1370 #define ALT_ECC_INTTEST_TDERRB_CLR_MSK 0xfeffffff
1371 /* The reset value of the ALT_ECC_INTTEST_TDERRB register field. */
1372 #define ALT_ECC_INTTEST_TDERRB_RESET 0x0
1373 /* Extracts the ALT_ECC_INTTEST_TDERRB field value from a register. */
1374 #define ALT_ECC_INTTEST_TDERRB_GET(value) (((value) & 0x01000000) >> 24)
1375 /* Produces a ALT_ECC_INTTEST_TDERRB register field value suitable for setting the register. */
1376 #define ALT_ECC_INTTEST_TDERRB_SET(value) (((value) << 24) & 0x01000000)
1377 
1378 #ifndef __ASSEMBLY__
1379 /*
1380  * WARNING: The C register and register group struct declarations are provided for
1381  * convenience and illustrative purposes. They should, however, be used with
1382  * caution as the C language standard provides no guarantees about the alignment or
1383  * atomicity of device memory accesses. The recommended practice for coding device
1384  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1385  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1386  * alt_write_dword() functions for 64 bit registers.
1387  *
1388  * The struct declaration for register ALT_ECC_INTTEST.
1389  */
1390 struct ALT_ECC_INTTEST_s
1391 {
1392  volatile uint32_t TSERRA : 1; /* ALT_ECC_INTTEST_TSERRA */
1393  uint32_t : 7; /* *UNDEFINED* */
1394  volatile uint32_t TDERRA : 1; /* ALT_ECC_INTTEST_TDERRA */
1395  uint32_t : 7; /* *UNDEFINED* */
1396  volatile uint32_t TSERRB : 1; /* ALT_ECC_INTTEST_TSERRB */
1397  uint32_t : 7; /* *UNDEFINED* */
1398  volatile uint32_t TDERRB : 1; /* ALT_ECC_INTTEST_TDERRB */
1399  uint32_t : 7; /* *UNDEFINED* */
1400 };
1401 
1402 /* The typedef declaration for register ALT_ECC_INTTEST. */
1403 typedef struct ALT_ECC_INTTEST_s ALT_ECC_INTTEST_t;
1404 #endif /* __ASSEMBLY__ */
1405 
1406 /* The reset value of the ALT_ECC_INTTEST register. */
1407 #define ALT_ECC_INTTEST_RESET 0x00000000
1408 /* The byte offset of the ALT_ECC_INTTEST register from the beginning of the component. */
1409 #define ALT_ECC_INTTEST_OFST 0x24
1410 /* The address of the ALT_ECC_INTTEST register. */
1411 #define ALT_ECC_INTTEST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTTEST_OFST))
1412 
1413 /*
1414  * Register : MODSTAT
1415  *
1416  * <p>Mode status flag</p>
1417  *
1418  * Register Layout
1419  *
1420  * Bits | Access | Reset | Description
1421  * :-------|:-------|:------|:--------------------------
1422  * [0] | RW | 0x0 | ALT_ECC_MODSTAT_CMPFLGA
1423  * [1] | RW | 0x0 | ALT_ECC_MODSTAT_CMPFLGB
1424  * [2] | RW | 0x0 | ALT_ECC_MODSTAT_RMW_SERRA
1425  * [3] | RW | 0x0 | ALT_ECC_MODSTAT_RMW_SERRB
1426  * [4] | RW | 0x0 | ALT_ECC_MODSTAT_RMW_DERRA
1427  * [5] | RW | 0x0 | ALT_ECC_MODSTAT_RMW_DERRB
1428  * [31:6] | ??? | 0x0 | *UNDEFINED*
1429  *
1430  */
1431 /*
1432  * Field : CMPFLGA
1433  *
1434  * Port A compare status flag
1435  *
1436  * Field Access Macros:
1437  *
1438  */
1439 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_CMPFLGA register field. */
1440 #define ALT_ECC_MODSTAT_CMPFLGA_LSB 0
1441 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_CMPFLGA register field. */
1442 #define ALT_ECC_MODSTAT_CMPFLGA_MSB 0
1443 /* The width in bits of the ALT_ECC_MODSTAT_CMPFLGA register field. */
1444 #define ALT_ECC_MODSTAT_CMPFLGA_WIDTH 1
1445 /* The mask used to set the ALT_ECC_MODSTAT_CMPFLGA register field value. */
1446 #define ALT_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
1447 /* The mask used to clear the ALT_ECC_MODSTAT_CMPFLGA register field value. */
1448 #define ALT_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
1449 /* The reset value of the ALT_ECC_MODSTAT_CMPFLGA register field. */
1450 #define ALT_ECC_MODSTAT_CMPFLGA_RESET 0x0
1451 /* Extracts the ALT_ECC_MODSTAT_CMPFLGA field value from a register. */
1452 #define ALT_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
1453 /* Produces a ALT_ECC_MODSTAT_CMPFLGA register field value suitable for setting the register. */
1454 #define ALT_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
1455 
1456 /*
1457  * Field : CMPFLGB
1458  *
1459  * Port B compare status flag
1460  *
1461  * Field Access Macros:
1462  *
1463  */
1464 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_CMPFLGB register field. */
1465 #define ALT_ECC_MODSTAT_CMPFLGB_LSB 1
1466 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_CMPFLGB register field. */
1467 #define ALT_ECC_MODSTAT_CMPFLGB_MSB 1
1468 /* The width in bits of the ALT_ECC_MODSTAT_CMPFLGB register field. */
1469 #define ALT_ECC_MODSTAT_CMPFLGB_WIDTH 1
1470 /* The mask used to set the ALT_ECC_MODSTAT_CMPFLGB register field value. */
1471 #define ALT_ECC_MODSTAT_CMPFLGB_SET_MSK 0x00000002
1472 /* The mask used to clear the ALT_ECC_MODSTAT_CMPFLGB register field value. */
1473 #define ALT_ECC_MODSTAT_CMPFLGB_CLR_MSK 0xfffffffd
1474 /* The reset value of the ALT_ECC_MODSTAT_CMPFLGB register field. */
1475 #define ALT_ECC_MODSTAT_CMPFLGB_RESET 0x0
1476 /* Extracts the ALT_ECC_MODSTAT_CMPFLGB field value from a register. */
1477 #define ALT_ECC_MODSTAT_CMPFLGB_GET(value) (((value) & 0x00000002) >> 1)
1478 /* Produces a ALT_ECC_MODSTAT_CMPFLGB register field value suitable for setting the register. */
1479 #define ALT_ECC_MODSTAT_CMPFLGB_SET(value) (((value) << 1) & 0x00000002)
1480 
1481 /*
1482  * Field : RMW_SERRA
1483  *
1484  * This bit indicates that a RMW access due to a subword access generated a SERR
1485  *
1486  * Field Access Macros:
1487  *
1488  */
1489 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_RMW_SERRA register field. */
1490 #define ALT_ECC_MODSTAT_RMW_SERRA_LSB 2
1491 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_RMW_SERRA register field. */
1492 #define ALT_ECC_MODSTAT_RMW_SERRA_MSB 2
1493 /* The width in bits of the ALT_ECC_MODSTAT_RMW_SERRA register field. */
1494 #define ALT_ECC_MODSTAT_RMW_SERRA_WIDTH 1
1495 /* The mask used to set the ALT_ECC_MODSTAT_RMW_SERRA register field value. */
1496 #define ALT_ECC_MODSTAT_RMW_SERRA_SET_MSK 0x00000004
1497 /* The mask used to clear the ALT_ECC_MODSTAT_RMW_SERRA register field value. */
1498 #define ALT_ECC_MODSTAT_RMW_SERRA_CLR_MSK 0xfffffffb
1499 /* The reset value of the ALT_ECC_MODSTAT_RMW_SERRA register field. */
1500 #define ALT_ECC_MODSTAT_RMW_SERRA_RESET 0x0
1501 /* Extracts the ALT_ECC_MODSTAT_RMW_SERRA field value from a register. */
1502 #define ALT_ECC_MODSTAT_RMW_SERRA_GET(value) (((value) & 0x00000004) >> 2)
1503 /* Produces a ALT_ECC_MODSTAT_RMW_SERRA register field value suitable for setting the register. */
1504 #define ALT_ECC_MODSTAT_RMW_SERRA_SET(value) (((value) << 2) & 0x00000004)
1505 
1506 /*
1507  * Field : RMW_SERRB
1508  *
1509  * This bit indicates that a RMW access due to a subword access generated a SERR
1510  *
1511  * Field Access Macros:
1512  *
1513  */
1514 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_RMW_SERRB register field. */
1515 #define ALT_ECC_MODSTAT_RMW_SERRB_LSB 3
1516 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_RMW_SERRB register field. */
1517 #define ALT_ECC_MODSTAT_RMW_SERRB_MSB 3
1518 /* The width in bits of the ALT_ECC_MODSTAT_RMW_SERRB register field. */
1519 #define ALT_ECC_MODSTAT_RMW_SERRB_WIDTH 1
1520 /* The mask used to set the ALT_ECC_MODSTAT_RMW_SERRB register field value. */
1521 #define ALT_ECC_MODSTAT_RMW_SERRB_SET_MSK 0x00000008
1522 /* The mask used to clear the ALT_ECC_MODSTAT_RMW_SERRB register field value. */
1523 #define ALT_ECC_MODSTAT_RMW_SERRB_CLR_MSK 0xfffffff7
1524 /* The reset value of the ALT_ECC_MODSTAT_RMW_SERRB register field. */
1525 #define ALT_ECC_MODSTAT_RMW_SERRB_RESET 0x0
1526 /* Extracts the ALT_ECC_MODSTAT_RMW_SERRB field value from a register. */
1527 #define ALT_ECC_MODSTAT_RMW_SERRB_GET(value) (((value) & 0x00000008) >> 3)
1528 /* Produces a ALT_ECC_MODSTAT_RMW_SERRB register field value suitable for setting the register. */
1529 #define ALT_ECC_MODSTAT_RMW_SERRB_SET(value) (((value) << 3) & 0x00000008)
1530 
1531 /*
1532  * Field : RMW_DERRA
1533  *
1534  * This bit indicates that a RMW access due to a subword access generated a DERR
1535  *
1536  * Field Access Macros:
1537  *
1538  */
1539 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_RMW_DERRA register field. */
1540 #define ALT_ECC_MODSTAT_RMW_DERRA_LSB 4
1541 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_RMW_DERRA register field. */
1542 #define ALT_ECC_MODSTAT_RMW_DERRA_MSB 4
1543 /* The width in bits of the ALT_ECC_MODSTAT_RMW_DERRA register field. */
1544 #define ALT_ECC_MODSTAT_RMW_DERRA_WIDTH 1
1545 /* The mask used to set the ALT_ECC_MODSTAT_RMW_DERRA register field value. */
1546 #define ALT_ECC_MODSTAT_RMW_DERRA_SET_MSK 0x00000010
1547 /* The mask used to clear the ALT_ECC_MODSTAT_RMW_DERRA register field value. */
1548 #define ALT_ECC_MODSTAT_RMW_DERRA_CLR_MSK 0xffffffef
1549 /* The reset value of the ALT_ECC_MODSTAT_RMW_DERRA register field. */
1550 #define ALT_ECC_MODSTAT_RMW_DERRA_RESET 0x0
1551 /* Extracts the ALT_ECC_MODSTAT_RMW_DERRA field value from a register. */
1552 #define ALT_ECC_MODSTAT_RMW_DERRA_GET(value) (((value) & 0x00000010) >> 4)
1553 /* Produces a ALT_ECC_MODSTAT_RMW_DERRA register field value suitable for setting the register. */
1554 #define ALT_ECC_MODSTAT_RMW_DERRA_SET(value) (((value) << 4) & 0x00000010)
1555 
1556 /*
1557  * Field : RMW_DERRB
1558  *
1559  * This bit indicates that a RMW access due to a subword access generated a DERR
1560  *
1561  * Field Access Macros:
1562  *
1563  */
1564 /* The Least Significant Bit (LSB) position of the ALT_ECC_MODSTAT_RMW_DERRB register field. */
1565 #define ALT_ECC_MODSTAT_RMW_DERRB_LSB 5
1566 /* The Most Significant Bit (MSB) position of the ALT_ECC_MODSTAT_RMW_DERRB register field. */
1567 #define ALT_ECC_MODSTAT_RMW_DERRB_MSB 5
1568 /* The width in bits of the ALT_ECC_MODSTAT_RMW_DERRB register field. */
1569 #define ALT_ECC_MODSTAT_RMW_DERRB_WIDTH 1
1570 /* The mask used to set the ALT_ECC_MODSTAT_RMW_DERRB register field value. */
1571 #define ALT_ECC_MODSTAT_RMW_DERRB_SET_MSK 0x00000020
1572 /* The mask used to clear the ALT_ECC_MODSTAT_RMW_DERRB register field value. */
1573 #define ALT_ECC_MODSTAT_RMW_DERRB_CLR_MSK 0xffffffdf
1574 /* The reset value of the ALT_ECC_MODSTAT_RMW_DERRB register field. */
1575 #define ALT_ECC_MODSTAT_RMW_DERRB_RESET 0x0
1576 /* Extracts the ALT_ECC_MODSTAT_RMW_DERRB field value from a register. */
1577 #define ALT_ECC_MODSTAT_RMW_DERRB_GET(value) (((value) & 0x00000020) >> 5)
1578 /* Produces a ALT_ECC_MODSTAT_RMW_DERRB register field value suitable for setting the register. */
1579 #define ALT_ECC_MODSTAT_RMW_DERRB_SET(value) (((value) << 5) & 0x00000020)
1580 
1581 #ifndef __ASSEMBLY__
1582 /*
1583  * WARNING: The C register and register group struct declarations are provided for
1584  * convenience and illustrative purposes. They should, however, be used with
1585  * caution as the C language standard provides no guarantees about the alignment or
1586  * atomicity of device memory accesses. The recommended practice for coding device
1587  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1588  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1589  * alt_write_dword() functions for 64 bit registers.
1590  *
1591  * The struct declaration for register ALT_ECC_MODSTAT.
1592  */
1593 struct ALT_ECC_MODSTAT_s
1594 {
1595  volatile uint32_t CMPFLGA : 1; /* ALT_ECC_MODSTAT_CMPFLGA */
1596  volatile uint32_t CMPFLGB : 1; /* ALT_ECC_MODSTAT_CMPFLGB */
1597  volatile uint32_t RMW_SERRA : 1; /* ALT_ECC_MODSTAT_RMW_SERRA */
1598  volatile uint32_t RMW_SERRB : 1; /* ALT_ECC_MODSTAT_RMW_SERRB */
1599  volatile uint32_t RMW_DERRA : 1; /* ALT_ECC_MODSTAT_RMW_DERRA */
1600  volatile uint32_t RMW_DERRB : 1; /* ALT_ECC_MODSTAT_RMW_DERRB */
1601  uint32_t : 26; /* *UNDEFINED* */
1602 };
1603 
1604 /* The typedef declaration for register ALT_ECC_MODSTAT. */
1605 typedef struct ALT_ECC_MODSTAT_s ALT_ECC_MODSTAT_t;
1606 #endif /* __ASSEMBLY__ */
1607 
1608 /* The reset value of the ALT_ECC_MODSTAT register. */
1609 #define ALT_ECC_MODSTAT_RESET 0x00000000
1610 /* The byte offset of the ALT_ECC_MODSTAT register from the beginning of the component. */
1611 #define ALT_ECC_MODSTAT_OFST 0x28
1612 /* The address of the ALT_ECC_MODSTAT register. */
1613 #define ALT_ECC_MODSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_MODSTAT_OFST))
1614 
1615 /*
1616  * Register : DERRADDRA
1617  *
1618  * This register shows the address of PORTA current double-bit error. RAM size will
1619  * determine the maximum number of address bits.
1620  *
1621  * Register Layout
1622  *
1623  * Bits | Access | Reset | Description
1624  * :-------|:-------|:------|:--------------------------
1625  * [30:0] | RW | 0x0 | ALT_ECC_DERRADDRA_ADDRESS
1626  * [31] | ??? | 0x0 | *UNDEFINED*
1627  *
1628  */
1629 /*
1630  * Field : Address
1631  *
1632  * Recent double-bit error address.
1633  *
1634  * Field Access Macros:
1635  *
1636  */
1637 /* The Least Significant Bit (LSB) position of the ALT_ECC_DERRADDRA_ADDRESS register field. */
1638 #define ALT_ECC_DERRADDRA_ADDRESS_LSB 0
1639 /* The Most Significant Bit (MSB) position of the ALT_ECC_DERRADDRA_ADDRESS register field. */
1640 #define ALT_ECC_DERRADDRA_ADDRESS_MSB 30
1641 /* The width in bits of the ALT_ECC_DERRADDRA_ADDRESS register field. */
1642 #define ALT_ECC_DERRADDRA_ADDRESS_WIDTH 31
1643 /* The mask used to set the ALT_ECC_DERRADDRA_ADDRESS register field value. */
1644 #define ALT_ECC_DERRADDRA_ADDRESS_SET_MSK 0x7fffffff
1645 /* The mask used to clear the ALT_ECC_DERRADDRA_ADDRESS register field value. */
1646 #define ALT_ECC_DERRADDRA_ADDRESS_CLR_MSK 0x80000000
1647 /* The reset value of the ALT_ECC_DERRADDRA_ADDRESS register field. */
1648 #define ALT_ECC_DERRADDRA_ADDRESS_RESET 0x0
1649 /* Extracts the ALT_ECC_DERRADDRA_ADDRESS field value from a register. */
1650 #define ALT_ECC_DERRADDRA_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1651 /* Produces a ALT_ECC_DERRADDRA_ADDRESS register field value suitable for setting the register. */
1652 #define ALT_ECC_DERRADDRA_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1653 
1654 #ifndef __ASSEMBLY__
1655 /*
1656  * WARNING: The C register and register group struct declarations are provided for
1657  * convenience and illustrative purposes. They should, however, be used with
1658  * caution as the C language standard provides no guarantees about the alignment or
1659  * atomicity of device memory accesses. The recommended practice for coding device
1660  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1661  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1662  * alt_write_dword() functions for 64 bit registers.
1663  *
1664  * The struct declaration for register ALT_ECC_DERRADDRA.
1665  */
1666 struct ALT_ECC_DERRADDRA_s
1667 {
1668  volatile uint32_t Address : 31; /* ALT_ECC_DERRADDRA_ADDRESS */
1669  uint32_t : 1; /* *UNDEFINED* */
1670 };
1671 
1672 /* The typedef declaration for register ALT_ECC_DERRADDRA. */
1673 typedef struct ALT_ECC_DERRADDRA_s ALT_ECC_DERRADDRA_t;
1674 #endif /* __ASSEMBLY__ */
1675 
1676 /* The reset value of the ALT_ECC_DERRADDRA register. */
1677 #define ALT_ECC_DERRADDRA_RESET 0x00000000
1678 /* The byte offset of the ALT_ECC_DERRADDRA register from the beginning of the component. */
1679 #define ALT_ECC_DERRADDRA_OFST 0x2c
1680 /* The address of the ALT_ECC_DERRADDRA register. */
1681 #define ALT_ECC_DERRADDRA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_DERRADDRA_OFST))
1682 
1683 /*
1684  * Register : SERRADDRA
1685  *
1686  * This register shows the address of PORTA current single-bit error. RAM size will
1687  * determine the maximum number of address bits.
1688  *
1689  * Register Layout
1690  *
1691  * Bits | Access | Reset | Description
1692  * :-------|:-------|:------|:--------------------------
1693  * [30:0] | RW | 0x0 | ALT_ECC_SERRADDRA_ADDRESS
1694  * [31] | ??? | 0x0 | *UNDEFINED*
1695  *
1696  */
1697 /*
1698  * Field : Address
1699  *
1700  * Recent single-bit error address.
1701  *
1702  * Field Access Macros:
1703  *
1704  */
1705 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRADDRA_ADDRESS register field. */
1706 #define ALT_ECC_SERRADDRA_ADDRESS_LSB 0
1707 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRADDRA_ADDRESS register field. */
1708 #define ALT_ECC_SERRADDRA_ADDRESS_MSB 30
1709 /* The width in bits of the ALT_ECC_SERRADDRA_ADDRESS register field. */
1710 #define ALT_ECC_SERRADDRA_ADDRESS_WIDTH 31
1711 /* The mask used to set the ALT_ECC_SERRADDRA_ADDRESS register field value. */
1712 #define ALT_ECC_SERRADDRA_ADDRESS_SET_MSK 0x7fffffff
1713 /* The mask used to clear the ALT_ECC_SERRADDRA_ADDRESS register field value. */
1714 #define ALT_ECC_SERRADDRA_ADDRESS_CLR_MSK 0x80000000
1715 /* The reset value of the ALT_ECC_SERRADDRA_ADDRESS register field. */
1716 #define ALT_ECC_SERRADDRA_ADDRESS_RESET 0x0
1717 /* Extracts the ALT_ECC_SERRADDRA_ADDRESS field value from a register. */
1718 #define ALT_ECC_SERRADDRA_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1719 /* Produces a ALT_ECC_SERRADDRA_ADDRESS register field value suitable for setting the register. */
1720 #define ALT_ECC_SERRADDRA_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1721 
1722 #ifndef __ASSEMBLY__
1723 /*
1724  * WARNING: The C register and register group struct declarations are provided for
1725  * convenience and illustrative purposes. They should, however, be used with
1726  * caution as the C language standard provides no guarantees about the alignment or
1727  * atomicity of device memory accesses. The recommended practice for coding device
1728  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1729  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1730  * alt_write_dword() functions for 64 bit registers.
1731  *
1732  * The struct declaration for register ALT_ECC_SERRADDRA.
1733  */
1734 struct ALT_ECC_SERRADDRA_s
1735 {
1736  volatile uint32_t Address : 31; /* ALT_ECC_SERRADDRA_ADDRESS */
1737  uint32_t : 1; /* *UNDEFINED* */
1738 };
1739 
1740 /* The typedef declaration for register ALT_ECC_SERRADDRA. */
1741 typedef struct ALT_ECC_SERRADDRA_s ALT_ECC_SERRADDRA_t;
1742 #endif /* __ASSEMBLY__ */
1743 
1744 /* The reset value of the ALT_ECC_SERRADDRA register. */
1745 #define ALT_ECC_SERRADDRA_RESET 0x00000000
1746 /* The byte offset of the ALT_ECC_SERRADDRA register from the beginning of the component. */
1747 #define ALT_ECC_SERRADDRA_OFST 0x30
1748 /* The address of the ALT_ECC_SERRADDRA register. */
1749 #define ALT_ECC_SERRADDRA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRADDRA_OFST))
1750 
1751 /*
1752  * Register : DERRADDRB
1753  *
1754  * This register shows the address of PORTB current double-bit error. RAM size will
1755  * determine the maximum number of address bits.
1756  *
1757  * Register Layout
1758  *
1759  * Bits | Access | Reset | Description
1760  * :-------|:-------|:------|:--------------------------
1761  * [30:0] | RW | 0x0 | ALT_ECC_DERRADDRB_ADDRESS
1762  * [31] | ??? | 0x0 | *UNDEFINED*
1763  *
1764  */
1765 /*
1766  * Field : Address
1767  *
1768  * Recent double-bit error address.
1769  *
1770  * Field Access Macros:
1771  *
1772  */
1773 /* The Least Significant Bit (LSB) position of the ALT_ECC_DERRADDRB_ADDRESS register field. */
1774 #define ALT_ECC_DERRADDRB_ADDRESS_LSB 0
1775 /* The Most Significant Bit (MSB) position of the ALT_ECC_DERRADDRB_ADDRESS register field. */
1776 #define ALT_ECC_DERRADDRB_ADDRESS_MSB 30
1777 /* The width in bits of the ALT_ECC_DERRADDRB_ADDRESS register field. */
1778 #define ALT_ECC_DERRADDRB_ADDRESS_WIDTH 31
1779 /* The mask used to set the ALT_ECC_DERRADDRB_ADDRESS register field value. */
1780 #define ALT_ECC_DERRADDRB_ADDRESS_SET_MSK 0x7fffffff
1781 /* The mask used to clear the ALT_ECC_DERRADDRB_ADDRESS register field value. */
1782 #define ALT_ECC_DERRADDRB_ADDRESS_CLR_MSK 0x80000000
1783 /* The reset value of the ALT_ECC_DERRADDRB_ADDRESS register field. */
1784 #define ALT_ECC_DERRADDRB_ADDRESS_RESET 0x0
1785 /* Extracts the ALT_ECC_DERRADDRB_ADDRESS field value from a register. */
1786 #define ALT_ECC_DERRADDRB_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1787 /* Produces a ALT_ECC_DERRADDRB_ADDRESS register field value suitable for setting the register. */
1788 #define ALT_ECC_DERRADDRB_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1789 
1790 #ifndef __ASSEMBLY__
1791 /*
1792  * WARNING: The C register and register group struct declarations are provided for
1793  * convenience and illustrative purposes. They should, however, be used with
1794  * caution as the C language standard provides no guarantees about the alignment or
1795  * atomicity of device memory accesses. The recommended practice for coding device
1796  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1797  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1798  * alt_write_dword() functions for 64 bit registers.
1799  *
1800  * The struct declaration for register ALT_ECC_DERRADDRB.
1801  */
1802 struct ALT_ECC_DERRADDRB_s
1803 {
1804  volatile uint32_t Address : 31; /* ALT_ECC_DERRADDRB_ADDRESS */
1805  uint32_t : 1; /* *UNDEFINED* */
1806 };
1807 
1808 /* The typedef declaration for register ALT_ECC_DERRADDRB. */
1809 typedef struct ALT_ECC_DERRADDRB_s ALT_ECC_DERRADDRB_t;
1810 #endif /* __ASSEMBLY__ */
1811 
1812 /* The reset value of the ALT_ECC_DERRADDRB register. */
1813 #define ALT_ECC_DERRADDRB_RESET 0x00000000
1814 /* The byte offset of the ALT_ECC_DERRADDRB register from the beginning of the component. */
1815 #define ALT_ECC_DERRADDRB_OFST 0x34
1816 /* The address of the ALT_ECC_DERRADDRB register. */
1817 #define ALT_ECC_DERRADDRB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_DERRADDRB_OFST))
1818 
1819 /*
1820  * Register : SERRADDRB
1821  *
1822  * This register shows the address of PORTB current single-bit error. RAM size will
1823  * determine the maximum number of address bits.
1824  *
1825  * Register Layout
1826  *
1827  * Bits | Access | Reset | Description
1828  * :-------|:-------|:------|:--------------------------
1829  * [30:0] | RW | 0x0 | ALT_ECC_SERRADDRB_ADDRESS
1830  * [31] | ??? | 0x0 | *UNDEFINED*
1831  *
1832  */
1833 /*
1834  * Field : Address
1835  *
1836  * Recent single-bit error address.
1837  *
1838  * Field Access Macros:
1839  *
1840  */
1841 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRADDRB_ADDRESS register field. */
1842 #define ALT_ECC_SERRADDRB_ADDRESS_LSB 0
1843 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRADDRB_ADDRESS register field. */
1844 #define ALT_ECC_SERRADDRB_ADDRESS_MSB 30
1845 /* The width in bits of the ALT_ECC_SERRADDRB_ADDRESS register field. */
1846 #define ALT_ECC_SERRADDRB_ADDRESS_WIDTH 31
1847 /* The mask used to set the ALT_ECC_SERRADDRB_ADDRESS register field value. */
1848 #define ALT_ECC_SERRADDRB_ADDRESS_SET_MSK 0x7fffffff
1849 /* The mask used to clear the ALT_ECC_SERRADDRB_ADDRESS register field value. */
1850 #define ALT_ECC_SERRADDRB_ADDRESS_CLR_MSK 0x80000000
1851 /* The reset value of the ALT_ECC_SERRADDRB_ADDRESS register field. */
1852 #define ALT_ECC_SERRADDRB_ADDRESS_RESET 0x0
1853 /* Extracts the ALT_ECC_SERRADDRB_ADDRESS field value from a register. */
1854 #define ALT_ECC_SERRADDRB_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1855 /* Produces a ALT_ECC_SERRADDRB_ADDRESS register field value suitable for setting the register. */
1856 #define ALT_ECC_SERRADDRB_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1857 
1858 #ifndef __ASSEMBLY__
1859 /*
1860  * WARNING: The C register and register group struct declarations are provided for
1861  * convenience and illustrative purposes. They should, however, be used with
1862  * caution as the C language standard provides no guarantees about the alignment or
1863  * atomicity of device memory accesses. The recommended practice for coding device
1864  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1865  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1866  * alt_write_dword() functions for 64 bit registers.
1867  *
1868  * The struct declaration for register ALT_ECC_SERRADDRB.
1869  */
1870 struct ALT_ECC_SERRADDRB_s
1871 {
1872  volatile uint32_t Address : 31; /* ALT_ECC_SERRADDRB_ADDRESS */
1873  uint32_t : 1; /* *UNDEFINED* */
1874 };
1875 
1876 /* The typedef declaration for register ALT_ECC_SERRADDRB. */
1877 typedef struct ALT_ECC_SERRADDRB_s ALT_ECC_SERRADDRB_t;
1878 #endif /* __ASSEMBLY__ */
1879 
1880 /* The reset value of the ALT_ECC_SERRADDRB register. */
1881 #define ALT_ECC_SERRADDRB_RESET 0x00000000
1882 /* The byte offset of the ALT_ECC_SERRADDRB register from the beginning of the component. */
1883 #define ALT_ECC_SERRADDRB_OFST 0x38
1884 /* The address of the ALT_ECC_SERRADDRB register. */
1885 #define ALT_ECC_SERRADDRB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRADDRB_OFST))
1886 
1887 /*
1888  * Register : SERRCNTREG
1889  *
1890  * Maximum counter value for single-bit error interrupt
1891  *
1892  * Register Layout
1893  *
1894  * Bits | Access | Reset | Description
1895  * :-------|:-------|:------|:---------------------------
1896  * [31:0] | RW | 0x0 | ALT_ECC_SERRCNTREG_SERRCNT
1897  *
1898  */
1899 /*
1900  * Field : SERRCNT
1901  *
1902  * Counter value
1903  *
1904  * Field Access Macros:
1905  *
1906  */
1907 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRCNTREG_SERRCNT register field. */
1908 #define ALT_ECC_SERRCNTREG_SERRCNT_LSB 0
1909 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRCNTREG_SERRCNT register field. */
1910 #define ALT_ECC_SERRCNTREG_SERRCNT_MSB 31
1911 /* The width in bits of the ALT_ECC_SERRCNTREG_SERRCNT register field. */
1912 #define ALT_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1913 /* The mask used to set the ALT_ECC_SERRCNTREG_SERRCNT register field value. */
1914 #define ALT_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1915 /* The mask used to clear the ALT_ECC_SERRCNTREG_SERRCNT register field value. */
1916 #define ALT_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1917 /* The reset value of the ALT_ECC_SERRCNTREG_SERRCNT register field. */
1918 #define ALT_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1919 /* Extracts the ALT_ECC_SERRCNTREG_SERRCNT field value from a register. */
1920 #define ALT_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1921 /* Produces a ALT_ECC_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
1922 #define ALT_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1923 
1924 #ifndef __ASSEMBLY__
1925 /*
1926  * WARNING: The C register and register group struct declarations are provided for
1927  * convenience and illustrative purposes. They should, however, be used with
1928  * caution as the C language standard provides no guarantees about the alignment or
1929  * atomicity of device memory accesses. The recommended practice for coding device
1930  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1931  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1932  * alt_write_dword() functions for 64 bit registers.
1933  *
1934  * The struct declaration for register ALT_ECC_SERRCNTREG.
1935  */
1936 struct ALT_ECC_SERRCNTREG_s
1937 {
1938  volatile uint32_t SERRCNT : 32; /* ALT_ECC_SERRCNTREG_SERRCNT */
1939 };
1940 
1941 /* The typedef declaration for register ALT_ECC_SERRCNTREG. */
1942 typedef struct ALT_ECC_SERRCNTREG_s ALT_ECC_SERRCNTREG_t;
1943 #endif /* __ASSEMBLY__ */
1944 
1945 /* The reset value of the ALT_ECC_SERRCNTREG register. */
1946 #define ALT_ECC_SERRCNTREG_RESET 0x00000000
1947 /* The byte offset of the ALT_ECC_SERRCNTREG register from the beginning of the component. */
1948 #define ALT_ECC_SERRCNTREG_OFST 0x3c
1949 /* The address of the ALT_ECC_SERRCNTREG register. */
1950 #define ALT_ECC_SERRCNTREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRCNTREG_OFST))
1951 
1952 /*
1953  * Register : ECC_Addrbus
1954  *
1955  * MSB bit of address is determined by ADR.
1956  *
1957  * Register Layout
1958  *
1959  * Bits | Access | Reset | Description
1960  * :-------|:-------|:------|:--------------------------------
1961  * [30:0] | RW | 0x0 | ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS
1962  * [31] | ??? | 0x0 | *UNDEFINED*
1963  *
1964  */
1965 /*
1966  * Field : ECC_AddrBUS
1967  *
1968  * Address will be driven to RAM to either read or write the data. Address will be
1969  * latched by the RAM when the Enbus is asserted.
1970  *
1971  * Field Access Macros:
1972  *
1973  */
1974 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1975 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1976 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1977 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 30
1978 /* The width in bits of the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1979 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 31
1980 /* The mask used to set the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1981 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x7fffffff
1982 /* The mask used to clear the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1983 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0x80000000
1984 /* The reset value of the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1985 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1986 /* Extracts the ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS field value from a register. */
1987 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x7fffffff) >> 0)
1988 /* Produces a ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value suitable for setting the register. */
1989 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x7fffffff)
1990 
1991 #ifndef __ASSEMBLY__
1992 /*
1993  * WARNING: The C register and register group struct declarations are provided for
1994  * convenience and illustrative purposes. They should, however, be used with
1995  * caution as the C language standard provides no guarantees about the alignment or
1996  * atomicity of device memory accesses. The recommended practice for coding device
1997  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1998  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1999  * alt_write_dword() functions for 64 bit registers.
2000  *
2001  * The struct declaration for register ALT_ECC_ECC_ADDRBUS.
2002  */
2003 struct ALT_ECC_ECC_ADDRBUS_s
2004 {
2005  volatile uint32_t ECC_AddrBUS : 31; /* ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS */
2006  uint32_t : 1; /* *UNDEFINED* */
2007 };
2008 
2009 /* The typedef declaration for register ALT_ECC_ECC_ADDRBUS. */
2010 typedef struct ALT_ECC_ECC_ADDRBUS_s ALT_ECC_ECC_ADDRBUS_t;
2011 #endif /* __ASSEMBLY__ */
2012 
2013 /* The reset value of the ALT_ECC_ECC_ADDRBUS register. */
2014 #define ALT_ECC_ECC_ADDRBUS_RESET 0x00000000
2015 /* The byte offset of the ALT_ECC_ECC_ADDRBUS register from the beginning of the component. */
2016 #define ALT_ECC_ECC_ADDRBUS_OFST 0x40
2017 /* The address of the ALT_ECC_ECC_ADDRBUS register. */
2018 #define ALT_ECC_ECC_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_ADDRBUS_OFST))
2019 
2020 /*
2021  * Register : ECC_RData0bus
2022  *
2023  * Data will be read to this register field.
2024  *
2025  * Register Layout
2026  *
2027  * Bits | Access | Reset | Description
2028  * :-------|:-------|:------|:-----------------------------------
2029  * [31:0] | RW | 0x0 | ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS
2030  *
2031  */
2032 /*
2033  * Field : ECC_RDataBUS
2034  *
2035  * ECC_RDataBUS[31:0].
2036  *
2037  * Field Access Macros:
2038  *
2039  */
2040 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
2041 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
2042 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
2043 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
2044 /* The width in bits of the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
2045 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
2046 /* The mask used to set the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
2047 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2048 /* The mask used to clear the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
2049 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2050 /* The reset value of the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
2051 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
2052 /* Extracts the ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS field value from a register. */
2053 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2054 /* Produces a ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value suitable for setting the register. */
2055 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2056 
2057 #ifndef __ASSEMBLY__
2058 /*
2059  * WARNING: The C register and register group struct declarations are provided for
2060  * convenience and illustrative purposes. They should, however, be used with
2061  * caution as the C language standard provides no guarantees about the alignment or
2062  * atomicity of device memory accesses. The recommended practice for coding device
2063  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2064  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2065  * alt_write_dword() functions for 64 bit registers.
2066  *
2067  * The struct declaration for register ALT_ECC_ECC_RDATA0BUS.
2068  */
2069 struct ALT_ECC_ECC_RDATA0BUS_s
2070 {
2071  volatile uint32_t ECC_RDataBUS : 32; /* ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS */
2072 };
2073 
2074 /* The typedef declaration for register ALT_ECC_ECC_RDATA0BUS. */
2075 typedef struct ALT_ECC_ECC_RDATA0BUS_s ALT_ECC_ECC_RDATA0BUS_t;
2076 #endif /* __ASSEMBLY__ */
2077 
2078 /* The reset value of the ALT_ECC_ECC_RDATA0BUS register. */
2079 #define ALT_ECC_ECC_RDATA0BUS_RESET 0x00000000
2080 /* The byte offset of the ALT_ECC_ECC_RDATA0BUS register from the beginning of the component. */
2081 #define ALT_ECC_ECC_RDATA0BUS_OFST 0x44
2082 /* The address of the ALT_ECC_ECC_RDATA0BUS register. */
2083 #define ALT_ECC_ECC_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA0BUS_OFST))
2084 
2085 /*
2086  * Register : ECC_RData1bus
2087  *
2088  * Data will be read to this register field.
2089  *
2090  * Register Layout
2091  *
2092  * Bits | Access | Reset | Description
2093  * :-------|:-------|:------|:-----------------------------------
2094  * [31:0] | RW | 0x0 | ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS
2095  *
2096  */
2097 /*
2098  * Field : ECC_RDataBUS
2099  *
2100  * ECC_RDataBUS[63:32].
2101  *
2102  * Field Access Macros:
2103  *
2104  */
2105 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
2106 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
2107 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
2108 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 31
2109 /* The width in bits of the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
2110 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
2111 /* The mask used to set the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
2112 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2113 /* The mask used to clear the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
2114 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2115 /* The reset value of the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
2116 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
2117 /* Extracts the ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS field value from a register. */
2118 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2119 /* Produces a ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value suitable for setting the register. */
2120 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2121 
2122 #ifndef __ASSEMBLY__
2123 /*
2124  * WARNING: The C register and register group struct declarations are provided for
2125  * convenience and illustrative purposes. They should, however, be used with
2126  * caution as the C language standard provides no guarantees about the alignment or
2127  * atomicity of device memory accesses. The recommended practice for coding device
2128  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2129  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2130  * alt_write_dword() functions for 64 bit registers.
2131  *
2132  * The struct declaration for register ALT_ECC_ECC_RDATA1BUS.
2133  */
2134 struct ALT_ECC_ECC_RDATA1BUS_s
2135 {
2136  volatile uint32_t ECC_RDataBUS : 32; /* ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS */
2137 };
2138 
2139 /* The typedef declaration for register ALT_ECC_ECC_RDATA1BUS. */
2140 typedef struct ALT_ECC_ECC_RDATA1BUS_s ALT_ECC_ECC_RDATA1BUS_t;
2141 #endif /* __ASSEMBLY__ */
2142 
2143 /* The reset value of the ALT_ECC_ECC_RDATA1BUS register. */
2144 #define ALT_ECC_ECC_RDATA1BUS_RESET 0x00000000
2145 /* The byte offset of the ALT_ECC_ECC_RDATA1BUS register from the beginning of the component. */
2146 #define ALT_ECC_ECC_RDATA1BUS_OFST 0x48
2147 /* The address of the ALT_ECC_ECC_RDATA1BUS register. */
2148 #define ALT_ECC_ECC_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA1BUS_OFST))
2149 
2150 /*
2151  * Register : ECC_RData2bus
2152  *
2153  * Data will be read to this register field.
2154  *
2155  * Register Layout
2156  *
2157  * Bits | Access | Reset | Description
2158  * :-------|:-------|:------|:-----------------------------------
2159  * [31:0] | RW | 0x0 | ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS
2160  *
2161  */
2162 /*
2163  * Field : ECC_RDataBUS
2164  *
2165  * ECC_RDataBUS[95:64].
2166  *
2167  * Field Access Macros:
2168  *
2169  */
2170 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
2171 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
2172 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
2173 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
2174 /* The width in bits of the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
2175 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
2176 /* The mask used to set the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
2177 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2178 /* The mask used to clear the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
2179 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2180 /* The reset value of the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
2181 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
2182 /* Extracts the ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS field value from a register. */
2183 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2184 /* Produces a ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value suitable for setting the register. */
2185 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2186 
2187 #ifndef __ASSEMBLY__
2188 /*
2189  * WARNING: The C register and register group struct declarations are provided for
2190  * convenience and illustrative purposes. They should, however, be used with
2191  * caution as the C language standard provides no guarantees about the alignment or
2192  * atomicity of device memory accesses. The recommended practice for coding device
2193  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2194  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2195  * alt_write_dword() functions for 64 bit registers.
2196  *
2197  * The struct declaration for register ALT_ECC_ECC_RDATA2BUS.
2198  */
2199 struct ALT_ECC_ECC_RDATA2BUS_s
2200 {
2201  volatile uint32_t ECC_RDataBUS : 32; /* ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS */
2202 };
2203 
2204 /* The typedef declaration for register ALT_ECC_ECC_RDATA2BUS. */
2205 typedef struct ALT_ECC_ECC_RDATA2BUS_s ALT_ECC_ECC_RDATA2BUS_t;
2206 #endif /* __ASSEMBLY__ */
2207 
2208 /* The reset value of the ALT_ECC_ECC_RDATA2BUS register. */
2209 #define ALT_ECC_ECC_RDATA2BUS_RESET 0x00000000
2210 /* The byte offset of the ALT_ECC_ECC_RDATA2BUS register from the beginning of the component. */
2211 #define ALT_ECC_ECC_RDATA2BUS_OFST 0x4c
2212 /* The address of the ALT_ECC_ECC_RDATA2BUS register. */
2213 #define ALT_ECC_ECC_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA2BUS_OFST))
2214 
2215 /*
2216  * Register : ECC_RData3bus
2217  *
2218  * Data will be read to this register field.
2219  *
2220  * Register Layout
2221  *
2222  * Bits | Access | Reset | Description
2223  * :-------|:-------|:------|:-----------------------------------
2224  * [31:0] | RW | 0x0 | ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS
2225  *
2226  */
2227 /*
2228  * Field : ECC_RDataBUS
2229  *
2230  * ECC_RDataBUS[127-96].
2231  *
2232  * Field Access Macros:
2233  *
2234  */
2235 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
2236 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
2237 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
2238 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
2239 /* The width in bits of the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
2240 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
2241 /* The mask used to set the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
2242 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2243 /* The mask used to clear the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
2244 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2245 /* The reset value of the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
2246 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
2247 /* Extracts the ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS field value from a register. */
2248 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2249 /* Produces a ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value suitable for setting the register. */
2250 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2251 
2252 #ifndef __ASSEMBLY__
2253 /*
2254  * WARNING: The C register and register group struct declarations are provided for
2255  * convenience and illustrative purposes. They should, however, be used with
2256  * caution as the C language standard provides no guarantees about the alignment or
2257  * atomicity of device memory accesses. The recommended practice for coding device
2258  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2259  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2260  * alt_write_dword() functions for 64 bit registers.
2261  *
2262  * The struct declaration for register ALT_ECC_ECC_RDATA3BUS.
2263  */
2264 struct ALT_ECC_ECC_RDATA3BUS_s
2265 {
2266  volatile uint32_t ECC_RDataBUS : 32; /* ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS */
2267 };
2268 
2269 /* The typedef declaration for register ALT_ECC_ECC_RDATA3BUS. */
2270 typedef struct ALT_ECC_ECC_RDATA3BUS_s ALT_ECC_ECC_RDATA3BUS_t;
2271 #endif /* __ASSEMBLY__ */
2272 
2273 /* The reset value of the ALT_ECC_ECC_RDATA3BUS register. */
2274 #define ALT_ECC_ECC_RDATA3BUS_RESET 0x00000000
2275 /* The byte offset of the ALT_ECC_ECC_RDATA3BUS register from the beginning of the component. */
2276 #define ALT_ECC_ECC_RDATA3BUS_OFST 0x50
2277 /* The address of the ALT_ECC_ECC_RDATA3BUS register. */
2278 #define ALT_ECC_ECC_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA3BUS_OFST))
2279 
2280 /*
2281  * Register : ECC_WData0bus
2282  *
2283  * Data from the register will be written to the RAM.
2284  *
2285  * Register Layout
2286  *
2287  * Bits | Access | Reset | Description
2288  * :-------|:-------|:------|:-----------------------------------
2289  * [31:0] | RW | 0x0 | ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS
2290  *
2291  */
2292 /*
2293  * Field : ECC_WDataBUS
2294  *
2295  * ECC_WDataBUS[31:0].
2296  *
2297  * Field Access Macros:
2298  *
2299  */
2300 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
2301 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
2302 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
2303 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
2304 /* The width in bits of the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
2305 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
2306 /* The mask used to set the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
2307 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2308 /* The mask used to clear the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
2309 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2310 /* The reset value of the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
2311 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
2312 /* Extracts the ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS field value from a register. */
2313 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2314 /* Produces a ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value suitable for setting the register. */
2315 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2316 
2317 #ifndef __ASSEMBLY__
2318 /*
2319  * WARNING: The C register and register group struct declarations are provided for
2320  * convenience and illustrative purposes. They should, however, be used with
2321  * caution as the C language standard provides no guarantees about the alignment or
2322  * atomicity of device memory accesses. The recommended practice for coding device
2323  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2324  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2325  * alt_write_dword() functions for 64 bit registers.
2326  *
2327  * The struct declaration for register ALT_ECC_ECC_WDATA0BUS.
2328  */
2329 struct ALT_ECC_ECC_WDATA0BUS_s
2330 {
2331  volatile uint32_t ECC_WDataBUS : 32; /* ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS */
2332 };
2333 
2334 /* The typedef declaration for register ALT_ECC_ECC_WDATA0BUS. */
2335 typedef struct ALT_ECC_ECC_WDATA0BUS_s ALT_ECC_ECC_WDATA0BUS_t;
2336 #endif /* __ASSEMBLY__ */
2337 
2338 /* The reset value of the ALT_ECC_ECC_WDATA0BUS register. */
2339 #define ALT_ECC_ECC_WDATA0BUS_RESET 0x00000000
2340 /* The byte offset of the ALT_ECC_ECC_WDATA0BUS register from the beginning of the component. */
2341 #define ALT_ECC_ECC_WDATA0BUS_OFST 0x54
2342 /* The address of the ALT_ECC_ECC_WDATA0BUS register. */
2343 #define ALT_ECC_ECC_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA0BUS_OFST))
2344 
2345 /*
2346  * Register : ECC_WData1bus
2347  *
2348  * Data from the register will be written to the RAM.
2349  *
2350  * Register Layout
2351  *
2352  * Bits | Access | Reset | Description
2353  * :-------|:-------|:------|:-----------------------------------
2354  * [31:0] | RW | 0x0 | ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS
2355  *
2356  */
2357 /*
2358  * Field : ECC_WDataBUS
2359  *
2360  * ECC_WDataBUS[63:32].
2361  *
2362  * Field Access Macros:
2363  *
2364  */
2365 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
2366 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
2367 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
2368 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 31
2369 /* The width in bits of the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
2370 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
2371 /* The mask used to set the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
2372 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2373 /* The mask used to clear the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
2374 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2375 /* The reset value of the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
2376 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
2377 /* Extracts the ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS field value from a register. */
2378 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2379 /* Produces a ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value suitable for setting the register. */
2380 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2381 
2382 #ifndef __ASSEMBLY__
2383 /*
2384  * WARNING: The C register and register group struct declarations are provided for
2385  * convenience and illustrative purposes. They should, however, be used with
2386  * caution as the C language standard provides no guarantees about the alignment or
2387  * atomicity of device memory accesses. The recommended practice for coding device
2388  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2389  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2390  * alt_write_dword() functions for 64 bit registers.
2391  *
2392  * The struct declaration for register ALT_ECC_ECC_WDATA1BUS.
2393  */
2394 struct ALT_ECC_ECC_WDATA1BUS_s
2395 {
2396  volatile uint32_t ECC_WDataBUS : 32; /* ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS */
2397 };
2398 
2399 /* The typedef declaration for register ALT_ECC_ECC_WDATA1BUS. */
2400 typedef struct ALT_ECC_ECC_WDATA1BUS_s ALT_ECC_ECC_WDATA1BUS_t;
2401 #endif /* __ASSEMBLY__ */
2402 
2403 /* The reset value of the ALT_ECC_ECC_WDATA1BUS register. */
2404 #define ALT_ECC_ECC_WDATA1BUS_RESET 0x00000000
2405 /* The byte offset of the ALT_ECC_ECC_WDATA1BUS register from the beginning of the component. */
2406 #define ALT_ECC_ECC_WDATA1BUS_OFST 0x58
2407 /* The address of the ALT_ECC_ECC_WDATA1BUS register. */
2408 #define ALT_ECC_ECC_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA1BUS_OFST))
2409 
2410 /*
2411  * Register : ECC_WData2bus
2412  *
2413  * Data from the register will be written to the RAM.
2414  *
2415  * Register Layout
2416  *
2417  * Bits | Access | Reset | Description
2418  * :-------|:-------|:------|:-----------------------------------
2419  * [31:0] | RW | 0x0 | ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS
2420  *
2421  */
2422 /*
2423  * Field : ECC_WDataBUS
2424  *
2425  * ECC_WDataBUS[95-64].
2426  *
2427  * Field Access Macros:
2428  *
2429  */
2430 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
2431 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
2432 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
2433 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
2434 /* The width in bits of the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
2435 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
2436 /* The mask used to set the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
2437 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2438 /* The mask used to clear the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
2439 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2440 /* The reset value of the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
2441 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
2442 /* Extracts the ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS field value from a register. */
2443 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2444 /* Produces a ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value suitable for setting the register. */
2445 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2446 
2447 #ifndef __ASSEMBLY__
2448 /*
2449  * WARNING: The C register and register group struct declarations are provided for
2450  * convenience and illustrative purposes. They should, however, be used with
2451  * caution as the C language standard provides no guarantees about the alignment or
2452  * atomicity of device memory accesses. The recommended practice for coding device
2453  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2454  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2455  * alt_write_dword() functions for 64 bit registers.
2456  *
2457  * The struct declaration for register ALT_ECC_ECC_WDATA2BUS.
2458  */
2459 struct ALT_ECC_ECC_WDATA2BUS_s
2460 {
2461  volatile uint32_t ECC_WDataBUS : 32; /* ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS */
2462 };
2463 
2464 /* The typedef declaration for register ALT_ECC_ECC_WDATA2BUS. */
2465 typedef struct ALT_ECC_ECC_WDATA2BUS_s ALT_ECC_ECC_WDATA2BUS_t;
2466 #endif /* __ASSEMBLY__ */
2467 
2468 /* The reset value of the ALT_ECC_ECC_WDATA2BUS register. */
2469 #define ALT_ECC_ECC_WDATA2BUS_RESET 0x00000000
2470 /* The byte offset of the ALT_ECC_ECC_WDATA2BUS register from the beginning of the component. */
2471 #define ALT_ECC_ECC_WDATA2BUS_OFST 0x5c
2472 /* The address of the ALT_ECC_ECC_WDATA2BUS register. */
2473 #define ALT_ECC_ECC_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA2BUS_OFST))
2474 
2475 /*
2476  * Register : ECC_WData3bus
2477  *
2478  * Data from the register will be written to the RAM.
2479  *
2480  * Register Layout
2481  *
2482  * Bits | Access | Reset | Description
2483  * :-------|:-------|:------|:-----------------------------------
2484  * [31:0] | RW | 0x0 | ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS
2485  *
2486  */
2487 /*
2488  * Field : ECC_WDataBUS
2489  *
2490  * ECC_WDataBUS[127-96].
2491  *
2492  * Field Access Macros:
2493  *
2494  */
2495 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
2496 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
2497 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
2498 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
2499 /* The width in bits of the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
2500 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
2501 /* The mask used to set the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
2502 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2503 /* The mask used to clear the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
2504 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2505 /* The reset value of the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
2506 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
2507 /* Extracts the ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS field value from a register. */
2508 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2509 /* Produces a ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value suitable for setting the register. */
2510 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2511 
2512 #ifndef __ASSEMBLY__
2513 /*
2514  * WARNING: The C register and register group struct declarations are provided for
2515  * convenience and illustrative purposes. They should, however, be used with
2516  * caution as the C language standard provides no guarantees about the alignment or
2517  * atomicity of device memory accesses. The recommended practice for coding device
2518  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2519  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2520  * alt_write_dword() functions for 64 bit registers.
2521  *
2522  * The struct declaration for register ALT_ECC_ECC_WDATA3BUS.
2523  */
2524 struct ALT_ECC_ECC_WDATA3BUS_s
2525 {
2526  volatile uint32_t ECC_WDataBUS : 32; /* ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS */
2527 };
2528 
2529 /* The typedef declaration for register ALT_ECC_ECC_WDATA3BUS. */
2530 typedef struct ALT_ECC_ECC_WDATA3BUS_s ALT_ECC_ECC_WDATA3BUS_t;
2531 #endif /* __ASSEMBLY__ */
2532 
2533 /* The reset value of the ALT_ECC_ECC_WDATA3BUS register. */
2534 #define ALT_ECC_ECC_WDATA3BUS_RESET 0x00000000
2535 /* The byte offset of the ALT_ECC_ECC_WDATA3BUS register from the beginning of the component. */
2536 #define ALT_ECC_ECC_WDATA3BUS_OFST 0x60
2537 /* The address of the ALT_ECC_ECC_WDATA3BUS register. */
2538 #define ALT_ECC_ECC_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA3BUS_OFST))
2539 
2540 /*
2541  * Register : ECC_RDataecc0bus
2542  *
2543  * The msb bit for the register is configured based on DAT parameter (RAM word
2544  * size). Unimplemented bytes of this register will be reserved.
2545  *
2546  * Register Layout
2547  *
2548  * Bits | Access | Reset | Description
2549  * :--------|:-------|:------|:------------------------------------------
2550  * [7:0] | RW | 0x0 | ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS
2551  * [15:8] | RW | 0x0 | ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS
2552  * [23:16] | RW | 0x0 | ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS
2553  * [31:24] | RW | 0x0 | ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS
2554  *
2555  */
2556 /*
2557  * Field : ECC_RDataecc0BUS
2558  *
2559  * Eccdata will be read to this register field.
2560  *
2561  * Field Access Macros:
2562  *
2563  */
2564 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2565 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
2566 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2567 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 7
2568 /* The width in bits of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2569 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 8
2570 /* The mask used to set the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
2571 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x000000ff
2572 /* The mask used to clear the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
2573 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff00
2574 /* The reset value of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2575 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
2576 /* Extracts the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register. */
2577 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
2578 /* Produces a ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register. */
2579 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
2580 
2581 /*
2582  * Field : ECC_RDataecc1BUS
2583  *
2584  * Eccdata will be read to this register field.
2585  *
2586  * Field Access Macros:
2587  *
2588  */
2589 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2590 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
2591 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2592 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 15
2593 /* The width in bits of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2594 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 8
2595 /* The mask used to set the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
2596 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x0000ff00
2597 /* The mask used to clear the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
2598 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff00ff
2599 /* The reset value of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2600 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
2601 /* Extracts the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register. */
2602 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2603 /* Produces a ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register. */
2604 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
2605 
2606 /*
2607  * Field : ECC_RDataecc2BUS
2608  *
2609  * Eccdata will be read to this register field.
2610  *
2611  * Field Access Macros:
2612  *
2613  */
2614 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2615 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
2616 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2617 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 23
2618 /* The width in bits of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2619 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 8
2620 /* The mask used to set the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
2621 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x00ff0000
2622 /* The mask used to clear the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
2623 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff00ffff
2624 /* The reset value of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2625 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
2626 /* Extracts the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register. */
2627 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2628 /* Produces a ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register. */
2629 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
2630 
2631 /*
2632  * Field : ECC_RDataecc3BUS
2633  *
2634  * Eccdata will be read to this register field.
2635  *
2636  * Field Access Macros:
2637  *
2638  */
2639 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2640 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
2641 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2642 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 31
2643 /* The width in bits of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2644 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 8
2645 /* The mask used to set the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
2646 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0xff000000
2647 /* The mask used to clear the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
2648 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x00ffffff
2649 /* The reset value of the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2650 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
2651 /* Extracts the ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register. */
2652 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
2653 /* Produces a ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register. */
2654 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0xff000000)
2655 
2656 #ifndef __ASSEMBLY__
2657 /*
2658  * WARNING: The C register and register group struct declarations are provided for
2659  * convenience and illustrative purposes. They should, however, be used with
2660  * caution as the C language standard provides no guarantees about the alignment or
2661  * atomicity of device memory accesses. The recommended practice for coding device
2662  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2663  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2664  * alt_write_dword() functions for 64 bit registers.
2665  *
2666  * The struct declaration for register ALT_ECC_ECC_RDATAECC0BUS.
2667  */
2668 struct ALT_ECC_ECC_RDATAECC0BUS_s
2669 {
2670  volatile uint32_t ECC_RDataecc0BUS : 8; /* ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS */
2671  volatile uint32_t ECC_RDataecc1BUS : 8; /* ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS */
2672  volatile uint32_t ECC_RDataecc2BUS : 8; /* ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS */
2673  volatile uint32_t ECC_RDataecc3BUS : 8; /* ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS */
2674 };
2675 
2676 /* The typedef declaration for register ALT_ECC_ECC_RDATAECC0BUS. */
2677 typedef struct ALT_ECC_ECC_RDATAECC0BUS_s ALT_ECC_ECC_RDATAECC0BUS_t;
2678 #endif /* __ASSEMBLY__ */
2679 
2680 /* The reset value of the ALT_ECC_ECC_RDATAECC0BUS register. */
2681 #define ALT_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
2682 /* The byte offset of the ALT_ECC_ECC_RDATAECC0BUS register from the beginning of the component. */
2683 #define ALT_ECC_ECC_RDATAECC0BUS_OFST 0x64
2684 /* The address of the ALT_ECC_ECC_RDATAECC0BUS register. */
2685 #define ALT_ECC_ECC_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATAECC0BUS_OFST))
2686 
2687 /*
2688  * Register : ECC_RDataecc1bus
2689  *
2690  * The msb bit for the register is configured based on DAT parameter (RAM word
2691  * size). Unimplemented bytes of this register will be reserved.
2692  *
2693  * Register Layout
2694  *
2695  * Bits | Access | Reset | Description
2696  * :--------|:-------|:------|:------------------------------------------
2697  * [7:0] | RW | 0x0 | ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS
2698  * [15:8] | RW | 0x0 | ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS
2699  * [23:16] | RW | 0x0 | ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS
2700  * [31:24] | RW | 0x0 | ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS
2701  *
2702  */
2703 /*
2704  * Field : ECC_RDataecc4BUS
2705  *
2706  * Eccdata will be read to this register field.
2707  *
2708  * Field Access Macros:
2709  *
2710  */
2711 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2712 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
2713 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2714 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 7
2715 /* The width in bits of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2716 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 8
2717 /* The mask used to set the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
2718 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x000000ff
2719 /* The mask used to clear the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
2720 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff00
2721 /* The reset value of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2722 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
2723 /* Extracts the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS field value from a register. */
2724 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x000000ff) >> 0)
2725 /* Produces a ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value suitable for setting the register. */
2726 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x000000ff)
2727 
2728 /*
2729  * Field : ECC_RDataecc5BUS
2730  *
2731  * Eccdata will be read to this register field.
2732  *
2733  * Field Access Macros:
2734  *
2735  */
2736 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2737 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
2738 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2739 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 15
2740 /* The width in bits of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2741 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 8
2742 /* The mask used to set the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
2743 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x0000ff00
2744 /* The mask used to clear the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
2745 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff00ff
2746 /* The reset value of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2747 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
2748 /* Extracts the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS field value from a register. */
2749 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2750 /* Produces a ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value suitable for setting the register. */
2751 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x0000ff00)
2752 
2753 /*
2754  * Field : ECC_RDataecc6BUS
2755  *
2756  * Eccdata will be read to this register field.
2757  *
2758  * Field Access Macros:
2759  *
2760  */
2761 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2762 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
2763 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2764 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 23
2765 /* The width in bits of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2766 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 8
2767 /* The mask used to set the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
2768 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x00ff0000
2769 /* The mask used to clear the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
2770 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff00ffff
2771 /* The reset value of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2772 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
2773 /* Extracts the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS field value from a register. */
2774 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2775 /* Produces a ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value suitable for setting the register. */
2776 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x00ff0000)
2777 
2778 /*
2779  * Field : ECC_RDataecc7BUS
2780  *
2781  * Eccdata will be read to this register field.
2782  *
2783  * Field Access Macros:
2784  *
2785  */
2786 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2787 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
2788 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2789 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 31
2790 /* The width in bits of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2791 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 8
2792 /* The mask used to set the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
2793 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0xff000000
2794 /* The mask used to clear the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
2795 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x00ffffff
2796 /* The reset value of the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2797 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
2798 /* Extracts the ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS field value from a register. */
2799 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0xff000000) >> 24)
2800 /* Produces a ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value suitable for setting the register. */
2801 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0xff000000)
2802 
2803 #ifndef __ASSEMBLY__
2804 /*
2805  * WARNING: The C register and register group struct declarations are provided for
2806  * convenience and illustrative purposes. They should, however, be used with
2807  * caution as the C language standard provides no guarantees about the alignment or
2808  * atomicity of device memory accesses. The recommended practice for coding device
2809  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2810  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2811  * alt_write_dword() functions for 64 bit registers.
2812  *
2813  * The struct declaration for register ALT_ECC_ECC_RDATAECC1BUS.
2814  */
2815 struct ALT_ECC_ECC_RDATAECC1BUS_s
2816 {
2817  volatile uint32_t ECC_RDataecc4BUS : 8; /* ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS */
2818  volatile uint32_t ECC_RDataecc5BUS : 8; /* ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS */
2819  volatile uint32_t ECC_RDataecc6BUS : 8; /* ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS */
2820  volatile uint32_t ECC_RDataecc7BUS : 8; /* ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS */
2821 };
2822 
2823 /* The typedef declaration for register ALT_ECC_ECC_RDATAECC1BUS. */
2824 typedef struct ALT_ECC_ECC_RDATAECC1BUS_s ALT_ECC_ECC_RDATAECC1BUS_t;
2825 #endif /* __ASSEMBLY__ */
2826 
2827 /* The reset value of the ALT_ECC_ECC_RDATAECC1BUS register. */
2828 #define ALT_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
2829 /* The byte offset of the ALT_ECC_ECC_RDATAECC1BUS register from the beginning of the component. */
2830 #define ALT_ECC_ECC_RDATAECC1BUS_OFST 0x68
2831 /* The address of the ALT_ECC_ECC_RDATAECC1BUS register. */
2832 #define ALT_ECC_ECC_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATAECC1BUS_OFST))
2833 
2834 /*
2835  * Register : ECC_WDataecc0bus
2836  *
2837  * The msb bit for the register is configured based on DAT parameter (RAM word
2838  * size). Unimplemented bytes of this register will be reserved.
2839  *
2840  * Register Layout
2841  *
2842  * Bits | Access | Reset | Description
2843  * :--------|:-------|:------|:------------------------------------------
2844  * [7:0] | RW | 0x0 | ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS
2845  * [15:8] | RW | 0x0 | ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS
2846  * [23:16] | RW | 0x0 | ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS
2847  * [31:24] | RW | 0x0 | ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS
2848  *
2849  */
2850 /*
2851  * Field : ECC_WDataecc0BUS
2852  *
2853  * Eccdata from the register will be written to the RAM.
2854  *
2855  * Field Access Macros:
2856  *
2857  */
2858 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2859 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
2860 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2861 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 7
2862 /* The width in bits of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2863 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 8
2864 /* The mask used to set the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2865 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x000000ff
2866 /* The mask used to clear the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2867 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff00
2868 /* The reset value of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2869 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2870 /* Extracts the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register. */
2871 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
2872 /* Produces a ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register. */
2873 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
2874 
2875 /*
2876  * Field : ECC_WDataecc1BUS
2877  *
2878  * Eccdata from the register will be written to the RAM.
2879  *
2880  * Field Access Macros:
2881  *
2882  */
2883 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2884 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2885 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2886 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 15
2887 /* The width in bits of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2888 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 8
2889 /* The mask used to set the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2890 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x0000ff00
2891 /* The mask used to clear the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2892 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff00ff
2893 /* The reset value of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2894 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2895 /* Extracts the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register. */
2896 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2897 /* Produces a ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register. */
2898 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
2899 
2900 /*
2901  * Field : ECC_WDataecc2BUS
2902  *
2903  * Eccdata from the register will be written to the RAM.
2904  *
2905  * Field Access Macros:
2906  *
2907  */
2908 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2909 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2910 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2911 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 23
2912 /* The width in bits of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2913 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 8
2914 /* The mask used to set the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2915 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x00ff0000
2916 /* The mask used to clear the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2917 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff00ffff
2918 /* The reset value of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2919 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2920 /* Extracts the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register. */
2921 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2922 /* Produces a ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register. */
2923 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
2924 
2925 /*
2926  * Field : ECC_WDataecc3BUS
2927  *
2928  * Eccdata from the register will be written to the RAM.
2929  *
2930  * Field Access Macros:
2931  *
2932  */
2933 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2934 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2935 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2936 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 31
2937 /* The width in bits of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2938 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 8
2939 /* The mask used to set the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2940 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0xff000000
2941 /* The mask used to clear the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2942 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x00ffffff
2943 /* The reset value of the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2944 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2945 /* Extracts the ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register. */
2946 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
2947 /* Produces a ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register. */
2948 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0xff000000)
2949 
2950 #ifndef __ASSEMBLY__
2951 /*
2952  * WARNING: The C register and register group struct declarations are provided for
2953  * convenience and illustrative purposes. They should, however, be used with
2954  * caution as the C language standard provides no guarantees about the alignment or
2955  * atomicity of device memory accesses. The recommended practice for coding device
2956  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2957  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2958  * alt_write_dword() functions for 64 bit registers.
2959  *
2960  * The struct declaration for register ALT_ECC_ECC_WDATAECC0BUS.
2961  */
2962 struct ALT_ECC_ECC_WDATAECC0BUS_s
2963 {
2964  volatile uint32_t ECC_WDataecc0BUS : 8; /* ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS */
2965  volatile uint32_t ECC_WDataecc1BUS : 8; /* ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS */
2966  volatile uint32_t ECC_WDataecc2BUS : 8; /* ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS */
2967  volatile uint32_t ECC_WDataecc3BUS : 8; /* ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS */
2968 };
2969 
2970 /* The typedef declaration for register ALT_ECC_ECC_WDATAECC0BUS. */
2971 typedef struct ALT_ECC_ECC_WDATAECC0BUS_s ALT_ECC_ECC_WDATAECC0BUS_t;
2972 #endif /* __ASSEMBLY__ */
2973 
2974 /* The reset value of the ALT_ECC_ECC_WDATAECC0BUS register. */
2975 #define ALT_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2976 /* The byte offset of the ALT_ECC_ECC_WDATAECC0BUS register from the beginning of the component. */
2977 #define ALT_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2978 /* The address of the ALT_ECC_ECC_WDATAECC0BUS register. */
2979 #define ALT_ECC_ECC_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATAECC0BUS_OFST))
2980 
2981 /*
2982  * Register : ECC_WDataecc1bus
2983  *
2984  * The msb bit for the register is configured based on DAT parameter (RAM word
2985  * size). Unimplemented bytes of this register will be reserved.
2986  *
2987  * Register Layout
2988  *
2989  * Bits | Access | Reset | Description
2990  * :--------|:-------|:------|:------------------------------------------
2991  * [7:0] | RW | 0x0 | ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS
2992  * [15:8] | RW | 0x0 | ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS
2993  * [23:16] | RW | 0x0 | ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS
2994  * [31:24] | RW | 0x0 | ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS
2995  *
2996  */
2997 /*
2998  * Field : ECC_WDataecc4BUS
2999  *
3000  * Eccdata from the register will be written to the RAM.
3001  *
3002  * Field Access Macros:
3003  *
3004  */
3005 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
3006 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
3007 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
3008 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 7
3009 /* The width in bits of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
3010 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 8
3011 /* The mask used to set the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
3012 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x000000ff
3013 /* The mask used to clear the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
3014 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff00
3015 /* The reset value of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
3016 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
3017 /* Extracts the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register. */
3018 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x000000ff) >> 0)
3019 /* Produces a ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register. */
3020 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x000000ff)
3021 
3022 /*
3023  * Field : ECC_WDataecc5BUS
3024  *
3025  * Eccdata from the register will be written to the RAM.
3026  *
3027  * Field Access Macros:
3028  *
3029  */
3030 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
3031 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
3032 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
3033 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 15
3034 /* The width in bits of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
3035 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 8
3036 /* The mask used to set the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
3037 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x0000ff00
3038 /* The mask used to clear the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
3039 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff00ff
3040 /* The reset value of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
3041 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
3042 /* Extracts the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register. */
3043 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3044 /* Produces a ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register. */
3045 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x0000ff00)
3046 
3047 /*
3048  * Field : ECC_WDataecc6BUS
3049  *
3050  * Eccdata from the register will be written to the RAM.
3051  *
3052  * Field Access Macros:
3053  *
3054  */
3055 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
3056 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
3057 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
3058 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 23
3059 /* The width in bits of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
3060 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 8
3061 /* The mask used to set the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
3062 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x00ff0000
3063 /* The mask used to clear the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
3064 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff00ffff
3065 /* The reset value of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
3066 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
3067 /* Extracts the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register. */
3068 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3069 /* Produces a ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register. */
3070 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x00ff0000)
3071 
3072 /*
3073  * Field : ECC_WDataecc7BUS
3074  *
3075  * Eccdata from the register will be written to the RAM.
3076  *
3077  * Field Access Macros:
3078  *
3079  */
3080 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
3081 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
3082 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
3083 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 31
3084 /* The width in bits of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
3085 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 8
3086 /* The mask used to set the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
3087 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0xff000000
3088 /* The mask used to clear the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
3089 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x00ffffff
3090 /* The reset value of the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
3091 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
3092 /* Extracts the ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register. */
3093 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0xff000000) >> 24)
3094 /* Produces a ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register. */
3095 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0xff000000)
3096 
3097 #ifndef __ASSEMBLY__
3098 /*
3099  * WARNING: The C register and register group struct declarations are provided for
3100  * convenience and illustrative purposes. They should, however, be used with
3101  * caution as the C language standard provides no guarantees about the alignment or
3102  * atomicity of device memory accesses. The recommended practice for coding device
3103  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3104  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3105  * alt_write_dword() functions for 64 bit registers.
3106  *
3107  * The struct declaration for register ALT_ECC_ECC_WDATAECC1BUS.
3108  */
3109 struct ALT_ECC_ECC_WDATAECC1BUS_s
3110 {
3111  volatile uint32_t ECC_WDataecc4BUS : 8; /* ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS */
3112  volatile uint32_t ECC_WDataecc5BUS : 8; /* ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS */
3113  volatile uint32_t ECC_WDataecc6BUS : 8; /* ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS */
3114  volatile uint32_t ECC_WDataecc7BUS : 8; /* ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS */
3115 };
3116 
3117 /* The typedef declaration for register ALT_ECC_ECC_WDATAECC1BUS. */
3118 typedef struct ALT_ECC_ECC_WDATAECC1BUS_s ALT_ECC_ECC_WDATAECC1BUS_t;
3119 #endif /* __ASSEMBLY__ */
3120 
3121 /* The reset value of the ALT_ECC_ECC_WDATAECC1BUS register. */
3122 #define ALT_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
3123 /* The byte offset of the ALT_ECC_ECC_WDATAECC1BUS register from the beginning of the component. */
3124 #define ALT_ECC_ECC_WDATAECC1BUS_OFST 0x70
3125 /* The address of the ALT_ECC_ECC_WDATAECC1BUS register. */
3126 #define ALT_ECC_ECC_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATAECC1BUS_OFST))
3127 
3128 /*
3129  * Register : ECC_dbytectrl
3130  *
3131  * Max number of implemented byte enabled is DAT/8
3132  *
3133  * Register Layout
3134  *
3135  * Bits | Access | Reset | Description
3136  * :-------|:-------|:------|:---------------------------
3137  * [7:0] | RW | 0x0 | ALT_ECC_ECC_DBYTECTRL_DBEN
3138  * [31:8] | ??? | 0x0 | *UNDEFINED*
3139  *
3140  */
3141 /*
3142  * Field : DBEN
3143  *
3144  * Byte or word enable for access.
3145  *
3146  * Field Access Macros:
3147  *
3148  */
3149 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DBYTECTRL_DBEN register field. */
3150 #define ALT_ECC_ECC_DBYTECTRL_DBEN_LSB 0
3151 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DBYTECTRL_DBEN register field. */
3152 #define ALT_ECC_ECC_DBYTECTRL_DBEN_MSB 7
3153 /* The width in bits of the ALT_ECC_ECC_DBYTECTRL_DBEN register field. */
3154 #define ALT_ECC_ECC_DBYTECTRL_DBEN_WIDTH 8
3155 /* The mask used to set the ALT_ECC_ECC_DBYTECTRL_DBEN register field value. */
3156 #define ALT_ECC_ECC_DBYTECTRL_DBEN_SET_MSK 0x000000ff
3157 /* The mask used to clear the ALT_ECC_ECC_DBYTECTRL_DBEN register field value. */
3158 #define ALT_ECC_ECC_DBYTECTRL_DBEN_CLR_MSK 0xffffff00
3159 /* The reset value of the ALT_ECC_ECC_DBYTECTRL_DBEN register field. */
3160 #define ALT_ECC_ECC_DBYTECTRL_DBEN_RESET 0x0
3161 /* Extracts the ALT_ECC_ECC_DBYTECTRL_DBEN field value from a register. */
3162 #define ALT_ECC_ECC_DBYTECTRL_DBEN_GET(value) (((value) & 0x000000ff) >> 0)
3163 /* Produces a ALT_ECC_ECC_DBYTECTRL_DBEN register field value suitable for setting the register. */
3164 #define ALT_ECC_ECC_DBYTECTRL_DBEN_SET(value) (((value) << 0) & 0x000000ff)
3165 
3166 #ifndef __ASSEMBLY__
3167 /*
3168  * WARNING: The C register and register group struct declarations are provided for
3169  * convenience and illustrative purposes. They should, however, be used with
3170  * caution as the C language standard provides no guarantees about the alignment or
3171  * atomicity of device memory accesses. The recommended practice for coding device
3172  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3173  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3174  * alt_write_dword() functions for 64 bit registers.
3175  *
3176  * The struct declaration for register ALT_ECC_ECC_DBYTECTRL.
3177  */
3178 struct ALT_ECC_ECC_DBYTECTRL_s
3179 {
3180  volatile uint32_t DBEN : 8; /* ALT_ECC_ECC_DBYTECTRL_DBEN */
3181  uint32_t : 24; /* *UNDEFINED* */
3182 };
3183 
3184 /* The typedef declaration for register ALT_ECC_ECC_DBYTECTRL. */
3185 typedef struct ALT_ECC_ECC_DBYTECTRL_s ALT_ECC_ECC_DBYTECTRL_t;
3186 #endif /* __ASSEMBLY__ */
3187 
3188 /* The reset value of the ALT_ECC_ECC_DBYTECTRL register. */
3189 #define ALT_ECC_ECC_DBYTECTRL_RESET 0x00000000
3190 /* The byte offset of the ALT_ECC_ECC_DBYTECTRL register from the beginning of the component. */
3191 #define ALT_ECC_ECC_DBYTECTRL_OFST 0x74
3192 /* The address of the ALT_ECC_ECC_DBYTECTRL register. */
3193 #define ALT_ECC_ECC_DBYTECTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_DBYTECTRL_OFST))
3194 
3195 /*
3196  * Register : ECC_accctrl
3197  *
3198  * These bits determine which byte of data/ecc to write to RAM.
3199  *
3200  * Register Layout
3201  *
3202  * Bits | Access | Reset | Description
3203  * :-------|:-------|:------|:----------------------------
3204  * [0] | RW | 0x0 | ALT_ECC_ECC_ACCCTRL_DATAOVR
3205  * [1] | RW | 0x0 | ALT_ECC_ECC_ACCCTRL_ECCOVR
3206  * [7:2] | ??? | 0x0 | *UNDEFINED*
3207  * [8] | RW | 0x0 | ALT_ECC_ECC_ACCCTRL_RDWR
3208  * [31:9] | ??? | 0x0 | *UNDEFINED*
3209  *
3210  */
3211 /*
3212  * Field : DATAOVR
3213  *
3214  * RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode
3215  * set by ECC_RW.
3216  *
3217  * 1'b0: Data override disabled.
3218  *
3219  * 1'b1: Data override enabled.
3220  *
3221  * Field Access Macros:
3222  *
3223  */
3224 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_ACCCTRL_DATAOVR register field. */
3225 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_LSB 0
3226 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_ACCCTRL_DATAOVR register field. */
3227 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_MSB 0
3228 /* The width in bits of the ALT_ECC_ECC_ACCCTRL_DATAOVR register field. */
3229 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_WIDTH 1
3230 /* The mask used to set the ALT_ECC_ECC_ACCCTRL_DATAOVR register field value. */
3231 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_SET_MSK 0x00000001
3232 /* The mask used to clear the ALT_ECC_ECC_ACCCTRL_DATAOVR register field value. */
3233 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_CLR_MSK 0xfffffffe
3234 /* The reset value of the ALT_ECC_ECC_ACCCTRL_DATAOVR register field. */
3235 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_RESET 0x0
3236 /* Extracts the ALT_ECC_ECC_ACCCTRL_DATAOVR field value from a register. */
3237 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
3238 /* Produces a ALT_ECC_ECC_ACCCTRL_DATAOVR register field value suitable for setting the register. */
3239 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
3240 
3241 /*
3242  * Field : ECCOVR
3243  *
3244  * ECC Data Override.
3245  *
3246  * Field Access Macros:
3247  *
3248  */
3249 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_ACCCTRL_ECCOVR register field. */
3250 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_LSB 1
3251 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_ACCCTRL_ECCOVR register field. */
3252 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_MSB 1
3253 /* The width in bits of the ALT_ECC_ECC_ACCCTRL_ECCOVR register field. */
3254 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_WIDTH 1
3255 /* The mask used to set the ALT_ECC_ECC_ACCCTRL_ECCOVR register field value. */
3256 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_SET_MSK 0x00000002
3257 /* The mask used to clear the ALT_ECC_ECC_ACCCTRL_ECCOVR register field value. */
3258 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_CLR_MSK 0xfffffffd
3259 /* The reset value of the ALT_ECC_ECC_ACCCTRL_ECCOVR register field. */
3260 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_RESET 0x0
3261 /* Extracts the ALT_ECC_ECC_ACCCTRL_ECCOVR field value from a register. */
3262 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
3263 /* Produces a ALT_ECC_ECC_ACCCTRL_ECCOVR register field value suitable for setting the register. */
3264 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
3265 
3266 /*
3267  * Field : RDWR
3268  *
3269  * Control for read/write.
3270  *
3271  * Field Access Macros:
3272  *
3273  */
3274 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_ACCCTRL_RDWR register field. */
3275 #define ALT_ECC_ECC_ACCCTRL_RDWR_LSB 8
3276 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_ACCCTRL_RDWR register field. */
3277 #define ALT_ECC_ECC_ACCCTRL_RDWR_MSB 8
3278 /* The width in bits of the ALT_ECC_ECC_ACCCTRL_RDWR register field. */
3279 #define ALT_ECC_ECC_ACCCTRL_RDWR_WIDTH 1
3280 /* The mask used to set the ALT_ECC_ECC_ACCCTRL_RDWR register field value. */
3281 #define ALT_ECC_ECC_ACCCTRL_RDWR_SET_MSK 0x00000100
3282 /* The mask used to clear the ALT_ECC_ECC_ACCCTRL_RDWR register field value. */
3283 #define ALT_ECC_ECC_ACCCTRL_RDWR_CLR_MSK 0xfffffeff
3284 /* The reset value of the ALT_ECC_ECC_ACCCTRL_RDWR register field. */
3285 #define ALT_ECC_ECC_ACCCTRL_RDWR_RESET 0x0
3286 /* Extracts the ALT_ECC_ECC_ACCCTRL_RDWR field value from a register. */
3287 #define ALT_ECC_ECC_ACCCTRL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
3288 /* Produces a ALT_ECC_ECC_ACCCTRL_RDWR register field value suitable for setting the register. */
3289 #define ALT_ECC_ECC_ACCCTRL_RDWR_SET(value) (((value) << 8) & 0x00000100)
3290 
3291 #ifndef __ASSEMBLY__
3292 /*
3293  * WARNING: The C register and register group struct declarations are provided for
3294  * convenience and illustrative purposes. They should, however, be used with
3295  * caution as the C language standard provides no guarantees about the alignment or
3296  * atomicity of device memory accesses. The recommended practice for coding device
3297  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3298  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3299  * alt_write_dword() functions for 64 bit registers.
3300  *
3301  * The struct declaration for register ALT_ECC_ECC_ACCCTRL.
3302  */
3303 struct ALT_ECC_ECC_ACCCTRL_s
3304 {
3305  volatile uint32_t DATAOVR : 1; /* ALT_ECC_ECC_ACCCTRL_DATAOVR */
3306  volatile uint32_t ECCOVR : 1; /* ALT_ECC_ECC_ACCCTRL_ECCOVR */
3307  uint32_t : 6; /* *UNDEFINED* */
3308  volatile uint32_t RDWR : 1; /* ALT_ECC_ECC_ACCCTRL_RDWR */
3309  uint32_t : 23; /* *UNDEFINED* */
3310 };
3311 
3312 /* The typedef declaration for register ALT_ECC_ECC_ACCCTRL. */
3313 typedef struct ALT_ECC_ECC_ACCCTRL_s ALT_ECC_ECC_ACCCTRL_t;
3314 #endif /* __ASSEMBLY__ */
3315 
3316 /* The reset value of the ALT_ECC_ECC_ACCCTRL register. */
3317 #define ALT_ECC_ECC_ACCCTRL_RESET 0x00000000
3318 /* The byte offset of the ALT_ECC_ECC_ACCCTRL register from the beginning of the component. */
3319 #define ALT_ECC_ECC_ACCCTRL_OFST 0x78
3320 /* The address of the ALT_ECC_ECC_ACCCTRL register. */
3321 #define ALT_ECC_ECC_ACCCTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_ACCCTRL_OFST))
3322 
3323 /*
3324  * Register : ECC_startacc
3325  *
3326  * These bits determine which byte of data/ecc to write to RAM.
3327  *
3328  * Register Layout
3329  *
3330  * Bits | Access | Reset | Description
3331  * :--------|:-------|:------|:----------------------------
3332  * [0] | RW | 0x0 | ALT_ECC_ECC_STARTACC_ENBUSB
3333  * [15:1] | ??? | 0x0 | *UNDEFINED*
3334  * [16] | RW | 0x0 | ALT_ECC_ECC_STARTACC_ENBUSA
3335  * [31:17] | ??? | 0x0 | *UNDEFINED*
3336  *
3337  */
3338 /*
3339  * Field : ENBUSB
3340  *
3341  * Start RAM access for PORTB.
3342  *
3343  * Field Access Macros:
3344  *
3345  */
3346 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_STARTACC_ENBUSB register field. */
3347 #define ALT_ECC_ECC_STARTACC_ENBUSB_LSB 0
3348 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_STARTACC_ENBUSB register field. */
3349 #define ALT_ECC_ECC_STARTACC_ENBUSB_MSB 0
3350 /* The width in bits of the ALT_ECC_ECC_STARTACC_ENBUSB register field. */
3351 #define ALT_ECC_ECC_STARTACC_ENBUSB_WIDTH 1
3352 /* The mask used to set the ALT_ECC_ECC_STARTACC_ENBUSB register field value. */
3353 #define ALT_ECC_ECC_STARTACC_ENBUSB_SET_MSK 0x00000001
3354 /* The mask used to clear the ALT_ECC_ECC_STARTACC_ENBUSB register field value. */
3355 #define ALT_ECC_ECC_STARTACC_ENBUSB_CLR_MSK 0xfffffffe
3356 /* The reset value of the ALT_ECC_ECC_STARTACC_ENBUSB register field. */
3357 #define ALT_ECC_ECC_STARTACC_ENBUSB_RESET 0x0
3358 /* Extracts the ALT_ECC_ECC_STARTACC_ENBUSB field value from a register. */
3359 #define ALT_ECC_ECC_STARTACC_ENBUSB_GET(value) (((value) & 0x00000001) >> 0)
3360 /* Produces a ALT_ECC_ECC_STARTACC_ENBUSB register field value suitable for setting the register. */
3361 #define ALT_ECC_ECC_STARTACC_ENBUSB_SET(value) (((value) << 0) & 0x00000001)
3362 
3363 /*
3364  * Field : ENBUSA
3365  *
3366  * Start RAM access for PORTA.
3367  *
3368  * Field Access Macros:
3369  *
3370  */
3371 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_STARTACC_ENBUSA register field. */
3372 #define ALT_ECC_ECC_STARTACC_ENBUSA_LSB 16
3373 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_STARTACC_ENBUSA register field. */
3374 #define ALT_ECC_ECC_STARTACC_ENBUSA_MSB 16
3375 /* The width in bits of the ALT_ECC_ECC_STARTACC_ENBUSA register field. */
3376 #define ALT_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
3377 /* The mask used to set the ALT_ECC_ECC_STARTACC_ENBUSA register field value. */
3378 #define ALT_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
3379 /* The mask used to clear the ALT_ECC_ECC_STARTACC_ENBUSA register field value. */
3380 #define ALT_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
3381 /* The reset value of the ALT_ECC_ECC_STARTACC_ENBUSA register field. */
3382 #define ALT_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
3383 /* Extracts the ALT_ECC_ECC_STARTACC_ENBUSA field value from a register. */
3384 #define ALT_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
3385 /* Produces a ALT_ECC_ECC_STARTACC_ENBUSA register field value suitable for setting the register. */
3386 #define ALT_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
3387 
3388 #ifndef __ASSEMBLY__
3389 /*
3390  * WARNING: The C register and register group struct declarations are provided for
3391  * convenience and illustrative purposes. They should, however, be used with
3392  * caution as the C language standard provides no guarantees about the alignment or
3393  * atomicity of device memory accesses. The recommended practice for coding device
3394  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3395  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3396  * alt_write_dword() functions for 64 bit registers.
3397  *
3398  * The struct declaration for register ALT_ECC_ECC_STARTACC.
3399  */
3400 struct ALT_ECC_ECC_STARTACC_s
3401 {
3402  volatile uint32_t ENBUSB : 1; /* ALT_ECC_ECC_STARTACC_ENBUSB */
3403  uint32_t : 15; /* *UNDEFINED* */
3404  volatile uint32_t ENBUSA : 1; /* ALT_ECC_ECC_STARTACC_ENBUSA */
3405  uint32_t : 15; /* *UNDEFINED* */
3406 };
3407 
3408 /* The typedef declaration for register ALT_ECC_ECC_STARTACC. */
3409 typedef struct ALT_ECC_ECC_STARTACC_s ALT_ECC_ECC_STARTACC_t;
3410 #endif /* __ASSEMBLY__ */
3411 
3412 /* The reset value of the ALT_ECC_ECC_STARTACC register. */
3413 #define ALT_ECC_ECC_STARTACC_RESET 0x00000000
3414 /* The byte offset of the ALT_ECC_ECC_STARTACC register from the beginning of the component. */
3415 #define ALT_ECC_ECC_STARTACC_OFST 0x7c
3416 /* The address of the ALT_ECC_ECC_STARTACC register. */
3417 #define ALT_ECC_ECC_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_STARTACC_OFST))
3418 
3419 /*
3420  * Register : ECC_wdctrl
3421  *
3422  * Bits to Enable/Disable Watch Dog Timer
3423  *
3424  * Register Layout
3425  *
3426  * Bits | Access | Reset | Description
3427  * :-------|:-------|:------|:----------------------------
3428  * [0] | RW | 0x0 | ALT_ECC_ECC_WDCTRL_WDEN_RAM
3429  * [31:1] | ??? | 0x0 | *UNDEFINED*
3430  *
3431  */
3432 /*
3433  * Field : WDEN_RAM
3434  *
3435  * Enable watchdog timeout for OCP register access to IP RAM.
3436  *
3437  * Field Access Macros:
3438  *
3439  */
3440 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field. */
3441 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_LSB 0
3442 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field. */
3443 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_MSB 0
3444 /* The width in bits of the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field. */
3445 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_WIDTH 1
3446 /* The mask used to set the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field value. */
3447 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_SET_MSK 0x00000001
3448 /* The mask used to clear the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field value. */
3449 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_CLR_MSK 0xfffffffe
3450 /* The reset value of the ALT_ECC_ECC_WDCTRL_WDEN_RAM register field. */
3451 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_RESET 0x0
3452 /* Extracts the ALT_ECC_ECC_WDCTRL_WDEN_RAM field value from a register. */
3453 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
3454 /* Produces a ALT_ECC_ECC_WDCTRL_WDEN_RAM register field value suitable for setting the register. */
3455 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
3456 
3457 #ifndef __ASSEMBLY__
3458 /*
3459  * WARNING: The C register and register group struct declarations are provided for
3460  * convenience and illustrative purposes. They should, however, be used with
3461  * caution as the C language standard provides no guarantees about the alignment or
3462  * atomicity of device memory accesses. The recommended practice for coding device
3463  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3464  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3465  * alt_write_dword() functions for 64 bit registers.
3466  *
3467  * The struct declaration for register ALT_ECC_ECC_WDCTRL.
3468  */
3469 struct ALT_ECC_ECC_WDCTRL_s
3470 {
3471  volatile uint32_t WDEN_RAM : 1; /* ALT_ECC_ECC_WDCTRL_WDEN_RAM */
3472  uint32_t : 31; /* *UNDEFINED* */
3473 };
3474 
3475 /* The typedef declaration for register ALT_ECC_ECC_WDCTRL. */
3476 typedef struct ALT_ECC_ECC_WDCTRL_s ALT_ECC_ECC_WDCTRL_t;
3477 #endif /* __ASSEMBLY__ */
3478 
3479 /* The reset value of the ALT_ECC_ECC_WDCTRL register. */
3480 #define ALT_ECC_ECC_WDCTRL_RESET 0x00000000
3481 /* The byte offset of the ALT_ECC_ECC_WDCTRL register from the beginning of the component. */
3482 #define ALT_ECC_ECC_WDCTRL_OFST 0x80
3483 /* The address of the ALT_ECC_ECC_WDCTRL register. */
3484 #define ALT_ECC_ECC_WDCTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDCTRL_OFST))
3485 
3486 /*
3487  * Register : ECC_DECODERSTAT
3488  *
3489  * <p>Individual decoder flags for single and double bits errors.</p>
3490  *
3491  * <p>Each decoder flags used represent one decoder in the design.</p>
3492  *
3493  * Register Layout
3494  *
3495  * Bits | Access | Reset | Description
3496  * :--------|:-------|:------|:------------------------------------
3497  * [0] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG
3498  * [1] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG
3499  * [2] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG
3500  * [3] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG
3501  * [4] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG
3502  * [5] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG
3503  * [6] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG
3504  * [7] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG
3505  * [8] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG
3506  * [9] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG
3507  * [10] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG
3508  * [11] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG
3509  * [12] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG
3510  * [13] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG
3511  * [14] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG
3512  * [15] | RW | 0x0 | ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG
3513  * [31:16] | ??? | 0x0 | *UNDEFINED*
3514  *
3515  */
3516 /*
3517  * Field : DEC0SERRFLG
3518  *
3519  * This bit indicates deocder(*) has detected single-bit error.
3520  *
3521  * 1'b0: No error has been captured with this flag
3522  *
3523  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3524  * and it will be cleared by writing 1. This flag will be set till SW clears.
3525  * Additional errors will not change the state of this bit. Error flag is set on
3526  * the first beat of erred data.
3527  *
3528  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3529  * dependent.
3530  *
3531  * Field Access Macros:
3532  *
3533  */
3534 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field. */
3535 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_LSB 0
3536 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field. */
3537 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_MSB 0
3538 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field. */
3539 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_WIDTH 1
3540 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field value. */
3541 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_SET_MSK 0x00000001
3542 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field value. */
3543 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
3544 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field. */
3545 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_RESET 0x0
3546 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG field value from a register. */
3547 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
3548 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG register field value suitable for setting the register. */
3549 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
3550 
3551 /*
3552  * Field : DEC1SERRFLG
3553  *
3554  * This bit indicates deocder(*) has detected single-bit error.
3555  *
3556  * 1'b0: No error has been captured with this flag
3557  *
3558  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3559  * and it will be cleared by writing 1. This flag will be set till SW clears.
3560  * Additional errors will not change the state of this bit. Error flag is set on
3561  * the first beat of erred data.
3562  *
3563  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3564  * dependent.
3565  *
3566  * Field Access Macros:
3567  *
3568  */
3569 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field. */
3570 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_LSB 1
3571 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field. */
3572 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_MSB 1
3573 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field. */
3574 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_WIDTH 1
3575 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field value. */
3576 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_SET_MSK 0x00000002
3577 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field value. */
3578 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
3579 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field. */
3580 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_RESET 0x0
3581 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG field value from a register. */
3582 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
3583 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG register field value suitable for setting the register. */
3584 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
3585 
3586 /*
3587  * Field : DEC2SERRFLG
3588  *
3589  * This bit indicates deocder(*) has detected single-bit error.
3590  *
3591  * 1'b0: No error has been captured with this flag
3592  *
3593  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3594  * and it will be cleared by writing 1. This flag will be set till SW clears.
3595  * Additional errors will not change the state of this bit. Error flag is set on
3596  * the first beat of erred data.
3597  *
3598  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3599  * dependent.
3600  *
3601  * Field Access Macros:
3602  *
3603  */
3604 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field. */
3605 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_LSB 2
3606 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field. */
3607 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_MSB 2
3608 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field. */
3609 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_WIDTH 1
3610 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field value. */
3611 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_SET_MSK 0x00000004
3612 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field value. */
3613 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
3614 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field. */
3615 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_RESET 0x0
3616 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG field value from a register. */
3617 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
3618 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG register field value suitable for setting the register. */
3619 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
3620 
3621 /*
3622  * Field : DEC3SERRFLG
3623  *
3624  * This bit indicates deocder(*) has detected single-bit error.
3625  *
3626  * 1'b0: No error has been captured with this flag
3627  *
3628  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3629  * and it will be cleared by writing 1. This flag will be set till SW clears.
3630  * Additional errors will not change the state of this bit. Error flag is set on
3631  * the first beat of erred data.
3632  *
3633  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3634  * dependent.
3635  *
3636  * Field Access Macros:
3637  *
3638  */
3639 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field. */
3640 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_LSB 3
3641 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field. */
3642 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_MSB 3
3643 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field. */
3644 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_WIDTH 1
3645 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field value. */
3646 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_SET_MSK 0x00000008
3647 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field value. */
3648 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
3649 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field. */
3650 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_RESET 0x0
3651 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG field value from a register. */
3652 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
3653 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG register field value suitable for setting the register. */
3654 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
3655 
3656 /*
3657  * Field : DEC4SERRFLG
3658  *
3659  * This bit indicates deocder(*) has detected single-bit error.
3660  *
3661  * 1'b0: No error has been captured with this flag
3662  *
3663  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3664  * and it will be cleared by writing 1. This flag will be set till SW clears.
3665  * Additional errors will not change the state of this bit. Error flag is set on
3666  * the first beat of erred data.
3667  *
3668  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3669  * dependent.
3670  *
3671  * Field Access Macros:
3672  *
3673  */
3674 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field. */
3675 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_LSB 4
3676 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field. */
3677 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_MSB 4
3678 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field. */
3679 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_WIDTH 1
3680 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field value. */
3681 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_SET_MSK 0x00000010
3682 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field value. */
3683 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_CLR_MSK 0xffffffef
3684 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field. */
3685 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_RESET 0x0
3686 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG field value from a register. */
3687 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_GET(value) (((value) & 0x00000010) >> 4)
3688 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG register field value suitable for setting the register. */
3689 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_SET(value) (((value) << 4) & 0x00000010)
3690 
3691 /*
3692  * Field : DEC5SERRFLG
3693  *
3694  * This bit indicates deocder(*) has detected single-bit error.
3695  *
3696  * 1'b0: No error has been captured with this flag
3697  *
3698  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3699  * and it will be cleared by writing 1. This flag will be set till SW clears.
3700  * Additional errors will not change the state of this bit. Error flag is set on
3701  * the first beat of erred data.
3702  *
3703  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3704  * dependent.
3705  *
3706  * Field Access Macros:
3707  *
3708  */
3709 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field. */
3710 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_LSB 5
3711 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field. */
3712 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_MSB 5
3713 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field. */
3714 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_WIDTH 1
3715 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field value. */
3716 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_SET_MSK 0x00000020
3717 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field value. */
3718 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_CLR_MSK 0xffffffdf
3719 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field. */
3720 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_RESET 0x0
3721 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG field value from a register. */
3722 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_GET(value) (((value) & 0x00000020) >> 5)
3723 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG register field value suitable for setting the register. */
3724 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_SET(value) (((value) << 5) & 0x00000020)
3725 
3726 /*
3727  * Field : DEC6SERRFLG
3728  *
3729  * This bit indicates deocder(*) has detected single-bit error.
3730  *
3731  * 1'b0: No error has been captured with this flag
3732  *
3733  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3734  * and it will be cleared by writing 1. This flag will be set till SW clears.
3735  * Additional errors will not change the state of this bit. Error flag is set on
3736  * the first beat of erred data.
3737  *
3738  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3739  * dependent.
3740  *
3741  * Field Access Macros:
3742  *
3743  */
3744 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field. */
3745 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_LSB 6
3746 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field. */
3747 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_MSB 6
3748 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field. */
3749 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_WIDTH 1
3750 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field value. */
3751 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_SET_MSK 0x00000040
3752 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field value. */
3753 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_CLR_MSK 0xffffffbf
3754 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field. */
3755 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_RESET 0x0
3756 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG field value from a register. */
3757 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_GET(value) (((value) & 0x00000040) >> 6)
3758 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG register field value suitable for setting the register. */
3759 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_SET(value) (((value) << 6) & 0x00000040)
3760 
3761 /*
3762  * Field : DEC7SERRFLG
3763  *
3764  * This bit indicates deocder(*) has detected single-bit error.
3765  *
3766  * 1'b0: No error has been captured with this flag
3767  *
3768  * 1'b1: Decoder (*) detected a single-bit error. This flag will be set by hardware
3769  * and it will be cleared by writing 1. This flag will be set till SW clears.
3770  * Additional errors will not change the state of this bit. Error flag is set on
3771  * the first beat of erred data.
3772  *
3773  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3774  * dependent.
3775  *
3776  * Field Access Macros:
3777  *
3778  */
3779 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field. */
3780 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_LSB 7
3781 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field. */
3782 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_MSB 7
3783 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field. */
3784 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_WIDTH 1
3785 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field value. */
3786 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_SET_MSK 0x00000080
3787 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field value. */
3788 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_CLR_MSK 0xffffff7f
3789 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field. */
3790 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_RESET 0x0
3791 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG field value from a register. */
3792 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_GET(value) (((value) & 0x00000080) >> 7)
3793 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG register field value suitable for setting the register. */
3794 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_SET(value) (((value) << 7) & 0x00000080)
3795 
3796 /*
3797  * Field : DEC0DERRFLG
3798  *
3799  * This bit indicates decoder(*) has detected double-bit error.
3800  *
3801  * 1'b0: No error has been captured with this flag
3802  *
3803  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3804  * and it will be cleared by writing 1. This flag will be set till SW clears.
3805  * Additional errors will not change the state of this bit. Error flag is set on
3806  * the first beat of erred data.
3807  *
3808  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3809  * dependent.
3810  *
3811  * Field Access Macros:
3812  *
3813  */
3814 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field. */
3815 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_LSB 8
3816 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field. */
3817 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_MSB 8
3818 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field. */
3819 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_WIDTH 1
3820 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field value. */
3821 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_SET_MSK 0x00000100
3822 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field value. */
3823 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
3824 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field. */
3825 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_RESET 0x0
3826 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG field value from a register. */
3827 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
3828 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG register field value suitable for setting the register. */
3829 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
3830 
3831 /*
3832  * Field : DEC1DERRFLG
3833  *
3834  * This bit indicates decoder(*) has detected double-bit error.
3835  *
3836  * 1'b0: No error has been captured with this flag
3837  *
3838  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3839  * and it will be cleared by writing 1. This flag will be set till SW clears.
3840  * Additional errors will not change the state of this bit. Error flag is set on
3841  * the first beat of erred data.
3842  *
3843  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3844  * dependent.
3845  *
3846  * Field Access Macros:
3847  *
3848  */
3849 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field. */
3850 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_LSB 9
3851 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field. */
3852 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_MSB 9
3853 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field. */
3854 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_WIDTH 1
3855 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field value. */
3856 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_SET_MSK 0x00000200
3857 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field value. */
3858 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
3859 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field. */
3860 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_RESET 0x0
3861 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG field value from a register. */
3862 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
3863 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG register field value suitable for setting the register. */
3864 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
3865 
3866 /*
3867  * Field : DEC2DERRFLG
3868  *
3869  * This bit indicates decoder(*) has detected double-bit error.
3870  *
3871  * 1'b0: No error has been captured with this flag
3872  *
3873  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3874  * and it will be cleared by writing 1. This flag will be set till SW clears.
3875  * Additional errors will not change the state of this bit. Error flag is set on
3876  * the first beat of erred data.
3877  *
3878  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3879  * dependent.
3880  *
3881  * Field Access Macros:
3882  *
3883  */
3884 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field. */
3885 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_LSB 10
3886 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field. */
3887 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_MSB 10
3888 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field. */
3889 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_WIDTH 1
3890 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field value. */
3891 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_SET_MSK 0x00000400
3892 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field value. */
3893 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
3894 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field. */
3895 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_RESET 0x0
3896 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG field value from a register. */
3897 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
3898 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG register field value suitable for setting the register. */
3899 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
3900 
3901 /*
3902  * Field : DEC3DERRFLG
3903  *
3904  * This bit indicates decoder(*) has detected double-bit error.
3905  *
3906  * 1'b0: No error has been captured with this flag
3907  *
3908  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3909  * and it will be cleared by writing 1. This flag will be set till SW clears.
3910  * Additional errors will not change the state of this bit. Error flag is set on
3911  * the first beat of erred data.
3912  *
3913  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3914  * dependent.
3915  *
3916  * Field Access Macros:
3917  *
3918  */
3919 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field. */
3920 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_LSB 11
3921 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field. */
3922 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_MSB 11
3923 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field. */
3924 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_WIDTH 1
3925 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field value. */
3926 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_SET_MSK 0x00000800
3927 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field value. */
3928 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
3929 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field. */
3930 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_RESET 0x0
3931 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG field value from a register. */
3932 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
3933 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG register field value suitable for setting the register. */
3934 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
3935 
3936 /*
3937  * Field : DEC4DERRFLG
3938  *
3939  * This bit indicates decoder(*) has detected double-bit error.
3940  *
3941  * 1'b0: No error has been captured with this flag
3942  *
3943  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3944  * and it will be cleared by writing 1. This flag will be set till SW clears.
3945  * Additional errors will not change the state of this bit. Error flag is set on
3946  * the first beat of erred data.
3947  *
3948  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3949  * dependent.
3950  *
3951  * Field Access Macros:
3952  *
3953  */
3954 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field. */
3955 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_LSB 12
3956 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field. */
3957 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_MSB 12
3958 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field. */
3959 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_WIDTH 1
3960 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field value. */
3961 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_SET_MSK 0x00001000
3962 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field value. */
3963 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_CLR_MSK 0xffffefff
3964 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field. */
3965 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_RESET 0x0
3966 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG field value from a register. */
3967 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_GET(value) (((value) & 0x00001000) >> 12)
3968 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG register field value suitable for setting the register. */
3969 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_SET(value) (((value) << 12) & 0x00001000)
3970 
3971 /*
3972  * Field : DEC5DERRFLG
3973  *
3974  * This bit indicates decoder(*) has detected double-bit error.
3975  *
3976  * 1'b0: No error has been captured with this flag
3977  *
3978  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
3979  * and it will be cleared by writing 1. This flag will be set till SW clears.
3980  * Additional errors will not change the state of this bit. Error flag is set on
3981  * the first beat of erred data.
3982  *
3983  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
3984  * dependent.
3985  *
3986  * Field Access Macros:
3987  *
3988  */
3989 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field. */
3990 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_LSB 13
3991 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field. */
3992 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_MSB 13
3993 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field. */
3994 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_WIDTH 1
3995 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field value. */
3996 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_SET_MSK 0x00002000
3997 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field value. */
3998 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_CLR_MSK 0xffffdfff
3999 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field. */
4000 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_RESET 0x0
4001 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG field value from a register. */
4002 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_GET(value) (((value) & 0x00002000) >> 13)
4003 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG register field value suitable for setting the register. */
4004 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_SET(value) (((value) << 13) & 0x00002000)
4005 
4006 /*
4007  * Field : DEC6DERRFLG
4008  *
4009  * This bit indicates decoder(*) has detected double-bit error.
4010  *
4011  * 1'b0: No error has been captured with this flag
4012  *
4013  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
4014  * and it will be cleared by writing 1. This flag will be set till SW clears.
4015  * Additional errors will not change the state of this bit. Error flag is set on
4016  * the first beat of erred data.
4017  *
4018  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
4019  * dependent.
4020  *
4021  * Field Access Macros:
4022  *
4023  */
4024 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field. */
4025 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_LSB 14
4026 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field. */
4027 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_MSB 14
4028 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field. */
4029 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_WIDTH 1
4030 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field value. */
4031 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_SET_MSK 0x00004000
4032 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field value. */
4033 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_CLR_MSK 0xffffbfff
4034 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field. */
4035 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_RESET 0x0
4036 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG field value from a register. */
4037 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_GET(value) (((value) & 0x00004000) >> 14)
4038 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG register field value suitable for setting the register. */
4039 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_SET(value) (((value) << 14) & 0x00004000)
4040 
4041 /*
4042  * Field : DEC7DERRFLG
4043  *
4044  * This bit indicates decoder(*) has detected double-bit error.
4045  *
4046  * 1'b0: No error has been captured with this flag
4047  *
4048  * 1'b1: Decoder (*) detected a double-bit error. This flag will be set by hardware
4049  * and it will be cleared by writing 1. This flag will be set till SW clears.
4050  * Additional errors will not change the state of this bit. Error flag is set on
4051  * the first beat of erred data.
4052  *
4053  * This wont be reset by the ecc_en bit. Number of decoders implemented is IP
4054  * dependent.
4055  *
4056  * Field Access Macros:
4057  *
4058  */
4059 /* The Least Significant Bit (LSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field. */
4060 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_LSB 15
4061 /* The Most Significant Bit (MSB) position of the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field. */
4062 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_MSB 15
4063 /* The width in bits of the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field. */
4064 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_WIDTH 1
4065 /* The mask used to set the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field value. */
4066 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_SET_MSK 0x00008000
4067 /* The mask used to clear the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field value. */
4068 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_CLR_MSK 0xffff7fff
4069 /* The reset value of the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field. */
4070 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_RESET 0x0
4071 /* Extracts the ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG field value from a register. */
4072 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_GET(value) (((value) & 0x00008000) >> 15)
4073 /* Produces a ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG register field value suitable for setting the register. */
4074 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_SET(value) (((value) << 15) & 0x00008000)
4075 
4076 #ifndef __ASSEMBLY__
4077 /*
4078  * WARNING: The C register and register group struct declarations are provided for
4079  * convenience and illustrative purposes. They should, however, be used with
4080  * caution as the C language standard provides no guarantees about the alignment or
4081  * atomicity of device memory accesses. The recommended practice for coding device
4082  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4083  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4084  * alt_write_dword() functions for 64 bit registers.
4085  *
4086  * The struct declaration for register ALT_ECC_ECC_DECODERSTAT.
4087  */
4088 struct ALT_ECC_ECC_DECODERSTAT_s
4089 {
4090  volatile uint32_t DEC0SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG */
4091  volatile uint32_t DEC1SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG */
4092  volatile uint32_t DEC2SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG */
4093  volatile uint32_t DEC3SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG */
4094  volatile uint32_t DEC4SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG */
4095  volatile uint32_t DEC5SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG */
4096  volatile uint32_t DEC6SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG */
4097  volatile uint32_t DEC7SERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG */
4098  volatile uint32_t DEC0DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG */
4099  volatile uint32_t DEC1DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG */
4100  volatile uint32_t DEC2DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG */
4101  volatile uint32_t DEC3DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG */
4102  volatile uint32_t DEC4DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG */
4103  volatile uint32_t DEC5DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG */
4104  volatile uint32_t DEC6DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG */
4105  volatile uint32_t DEC7DERRFLG : 1; /* ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG */
4106  uint32_t : 16; /* *UNDEFINED* */
4107 };
4108 
4109 /* The typedef declaration for register ALT_ECC_ECC_DECODERSTAT. */
4110 typedef struct ALT_ECC_ECC_DECODERSTAT_s ALT_ECC_ECC_DECODERSTAT_t;
4111 #endif /* __ASSEMBLY__ */
4112 
4113 /* The reset value of the ALT_ECC_ECC_DECODERSTAT register. */
4114 #define ALT_ECC_ECC_DECODERSTAT_RESET 0x00000000
4115 /* The byte offset of the ALT_ECC_ECC_DECODERSTAT register from the beginning of the component. */
4116 #define ALT_ECC_ECC_DECODERSTAT_OFST 0x84
4117 /* The address of the ALT_ECC_ECC_DECODERSTAT register. */
4118 #define ALT_ECC_ECC_DECODERSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_DECODERSTAT_OFST))
4119 
4120 /*
4121  * Register : SERRLKUPA0
4122  *
4123  * Single-bit error address in LOOKUP TABLE for PORTA.
4124  *
4125  * Valid flag bit. Valid bit indicates if the address in this register is current
4126  * or stale.
4127  *
4128  * IF IP is having a single decoder, VALID8 will be used
4129  *
4130  * IF IP is having multiple decoder, The lowest decoder will be represented on
4131  * VALID1 and the next will on VALID2.
4132  *
4133  * It increases onward to VALID8.
4134  *
4135  * Register Layout
4136  *
4137  * Bits | Access | Reset | Description
4138  * :-------|:-------|:------|:---------------------------
4139  * [23:0] | R | 0x0 | ALT_ECC_SERRLKUPA0_ADDRESS
4140  * [24] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID1
4141  * [25] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID2
4142  * [26] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID3
4143  * [27] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID4
4144  * [28] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID5
4145  * [29] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID6
4146  * [30] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID7
4147  * [31] | RW | 0x0 | ALT_ECC_SERRLKUPA0_VALID8
4148  *
4149  */
4150 /*
4151  * Field : Address
4152  *
4153  * Recent Single-bit error address.
4154  *
4155  * This register shows the address of the each single-bit error. RAM size will
4156  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
4157  * 30-16 will be reserved and read as zero.
4158  *
4159  * Field Access Macros:
4160  *
4161  */
4162 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_ADDRESS register field. */
4163 #define ALT_ECC_SERRLKUPA0_ADDRESS_LSB 0
4164 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_ADDRESS register field. */
4165 #define ALT_ECC_SERRLKUPA0_ADDRESS_MSB 23
4166 /* The width in bits of the ALT_ECC_SERRLKUPA0_ADDRESS register field. */
4167 #define ALT_ECC_SERRLKUPA0_ADDRESS_WIDTH 24
4168 /* The mask used to set the ALT_ECC_SERRLKUPA0_ADDRESS register field value. */
4169 #define ALT_ECC_SERRLKUPA0_ADDRESS_SET_MSK 0x00ffffff
4170 /* The mask used to clear the ALT_ECC_SERRLKUPA0_ADDRESS register field value. */
4171 #define ALT_ECC_SERRLKUPA0_ADDRESS_CLR_MSK 0xff000000
4172 /* The reset value of the ALT_ECC_SERRLKUPA0_ADDRESS register field. */
4173 #define ALT_ECC_SERRLKUPA0_ADDRESS_RESET 0x0
4174 /* Extracts the ALT_ECC_SERRLKUPA0_ADDRESS field value from a register. */
4175 #define ALT_ECC_SERRLKUPA0_ADDRESS_GET(value) (((value) & 0x00ffffff) >> 0)
4176 /* Produces a ALT_ECC_SERRLKUPA0_ADDRESS register field value suitable for setting the register. */
4177 #define ALT_ECC_SERRLKUPA0_ADDRESS_SET(value) (((value) << 0) & 0x00ffffff)
4178 
4179 /*
4180  * Field : VALID1
4181  *
4182  *
4183  * Field Access Macros:
4184  *
4185  */
4186 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID1 register field. */
4187 #define ALT_ECC_SERRLKUPA0_VALID1_LSB 24
4188 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID1 register field. */
4189 #define ALT_ECC_SERRLKUPA0_VALID1_MSB 24
4190 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID1 register field. */
4191 #define ALT_ECC_SERRLKUPA0_VALID1_WIDTH 1
4192 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID1 register field value. */
4193 #define ALT_ECC_SERRLKUPA0_VALID1_SET_MSK 0x01000000
4194 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID1 register field value. */
4195 #define ALT_ECC_SERRLKUPA0_VALID1_CLR_MSK 0xfeffffff
4196 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID1 register field. */
4197 #define ALT_ECC_SERRLKUPA0_VALID1_RESET 0x0
4198 /* Extracts the ALT_ECC_SERRLKUPA0_VALID1 field value from a register. */
4199 #define ALT_ECC_SERRLKUPA0_VALID1_GET(value) (((value) & 0x01000000) >> 24)
4200 /* Produces a ALT_ECC_SERRLKUPA0_VALID1 register field value suitable for setting the register. */
4201 #define ALT_ECC_SERRLKUPA0_VALID1_SET(value) (((value) << 24) & 0x01000000)
4202 
4203 /*
4204  * Field : VALID2
4205  *
4206  *
4207  * Field Access Macros:
4208  *
4209  */
4210 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID2 register field. */
4211 #define ALT_ECC_SERRLKUPA0_VALID2_LSB 25
4212 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID2 register field. */
4213 #define ALT_ECC_SERRLKUPA0_VALID2_MSB 25
4214 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID2 register field. */
4215 #define ALT_ECC_SERRLKUPA0_VALID2_WIDTH 1
4216 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID2 register field value. */
4217 #define ALT_ECC_SERRLKUPA0_VALID2_SET_MSK 0x02000000
4218 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID2 register field value. */
4219 #define ALT_ECC_SERRLKUPA0_VALID2_CLR_MSK 0xfdffffff
4220 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID2 register field. */
4221 #define ALT_ECC_SERRLKUPA0_VALID2_RESET 0x0
4222 /* Extracts the ALT_ECC_SERRLKUPA0_VALID2 field value from a register. */
4223 #define ALT_ECC_SERRLKUPA0_VALID2_GET(value) (((value) & 0x02000000) >> 25)
4224 /* Produces a ALT_ECC_SERRLKUPA0_VALID2 register field value suitable for setting the register. */
4225 #define ALT_ECC_SERRLKUPA0_VALID2_SET(value) (((value) << 25) & 0x02000000)
4226 
4227 /*
4228  * Field : VALID3
4229  *
4230  *
4231  * Field Access Macros:
4232  *
4233  */
4234 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID3 register field. */
4235 #define ALT_ECC_SERRLKUPA0_VALID3_LSB 26
4236 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID3 register field. */
4237 #define ALT_ECC_SERRLKUPA0_VALID3_MSB 26
4238 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID3 register field. */
4239 #define ALT_ECC_SERRLKUPA0_VALID3_WIDTH 1
4240 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID3 register field value. */
4241 #define ALT_ECC_SERRLKUPA0_VALID3_SET_MSK 0x04000000
4242 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID3 register field value. */
4243 #define ALT_ECC_SERRLKUPA0_VALID3_CLR_MSK 0xfbffffff
4244 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID3 register field. */
4245 #define ALT_ECC_SERRLKUPA0_VALID3_RESET 0x0
4246 /* Extracts the ALT_ECC_SERRLKUPA0_VALID3 field value from a register. */
4247 #define ALT_ECC_SERRLKUPA0_VALID3_GET(value) (((value) & 0x04000000) >> 26)
4248 /* Produces a ALT_ECC_SERRLKUPA0_VALID3 register field value suitable for setting the register. */
4249 #define ALT_ECC_SERRLKUPA0_VALID3_SET(value) (((value) << 26) & 0x04000000)
4250 
4251 /*
4252  * Field : VALID4
4253  *
4254  *
4255  * Field Access Macros:
4256  *
4257  */
4258 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID4 register field. */
4259 #define ALT_ECC_SERRLKUPA0_VALID4_LSB 27
4260 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID4 register field. */
4261 #define ALT_ECC_SERRLKUPA0_VALID4_MSB 27
4262 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID4 register field. */
4263 #define ALT_ECC_SERRLKUPA0_VALID4_WIDTH 1
4264 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID4 register field value. */
4265 #define ALT_ECC_SERRLKUPA0_VALID4_SET_MSK 0x08000000
4266 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID4 register field value. */
4267 #define ALT_ECC_SERRLKUPA0_VALID4_CLR_MSK 0xf7ffffff
4268 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID4 register field. */
4269 #define ALT_ECC_SERRLKUPA0_VALID4_RESET 0x0
4270 /* Extracts the ALT_ECC_SERRLKUPA0_VALID4 field value from a register. */
4271 #define ALT_ECC_SERRLKUPA0_VALID4_GET(value) (((value) & 0x08000000) >> 27)
4272 /* Produces a ALT_ECC_SERRLKUPA0_VALID4 register field value suitable for setting the register. */
4273 #define ALT_ECC_SERRLKUPA0_VALID4_SET(value) (((value) << 27) & 0x08000000)
4274 
4275 /*
4276  * Field : VALID5
4277  *
4278  *
4279  * Field Access Macros:
4280  *
4281  */
4282 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID5 register field. */
4283 #define ALT_ECC_SERRLKUPA0_VALID5_LSB 28
4284 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID5 register field. */
4285 #define ALT_ECC_SERRLKUPA0_VALID5_MSB 28
4286 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID5 register field. */
4287 #define ALT_ECC_SERRLKUPA0_VALID5_WIDTH 1
4288 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID5 register field value. */
4289 #define ALT_ECC_SERRLKUPA0_VALID5_SET_MSK 0x10000000
4290 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID5 register field value. */
4291 #define ALT_ECC_SERRLKUPA0_VALID5_CLR_MSK 0xefffffff
4292 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID5 register field. */
4293 #define ALT_ECC_SERRLKUPA0_VALID5_RESET 0x0
4294 /* Extracts the ALT_ECC_SERRLKUPA0_VALID5 field value from a register. */
4295 #define ALT_ECC_SERRLKUPA0_VALID5_GET(value) (((value) & 0x10000000) >> 28)
4296 /* Produces a ALT_ECC_SERRLKUPA0_VALID5 register field value suitable for setting the register. */
4297 #define ALT_ECC_SERRLKUPA0_VALID5_SET(value) (((value) << 28) & 0x10000000)
4298 
4299 /*
4300  * Field : VALID6
4301  *
4302  *
4303  * Field Access Macros:
4304  *
4305  */
4306 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID6 register field. */
4307 #define ALT_ECC_SERRLKUPA0_VALID6_LSB 29
4308 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID6 register field. */
4309 #define ALT_ECC_SERRLKUPA0_VALID6_MSB 29
4310 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID6 register field. */
4311 #define ALT_ECC_SERRLKUPA0_VALID6_WIDTH 1
4312 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID6 register field value. */
4313 #define ALT_ECC_SERRLKUPA0_VALID6_SET_MSK 0x20000000
4314 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID6 register field value. */
4315 #define ALT_ECC_SERRLKUPA0_VALID6_CLR_MSK 0xdfffffff
4316 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID6 register field. */
4317 #define ALT_ECC_SERRLKUPA0_VALID6_RESET 0x0
4318 /* Extracts the ALT_ECC_SERRLKUPA0_VALID6 field value from a register. */
4319 #define ALT_ECC_SERRLKUPA0_VALID6_GET(value) (((value) & 0x20000000) >> 29)
4320 /* Produces a ALT_ECC_SERRLKUPA0_VALID6 register field value suitable for setting the register. */
4321 #define ALT_ECC_SERRLKUPA0_VALID6_SET(value) (((value) << 29) & 0x20000000)
4322 
4323 /*
4324  * Field : VALID7
4325  *
4326  *
4327  * Field Access Macros:
4328  *
4329  */
4330 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID7 register field. */
4331 #define ALT_ECC_SERRLKUPA0_VALID7_LSB 30
4332 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID7 register field. */
4333 #define ALT_ECC_SERRLKUPA0_VALID7_MSB 30
4334 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID7 register field. */
4335 #define ALT_ECC_SERRLKUPA0_VALID7_WIDTH 1
4336 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID7 register field value. */
4337 #define ALT_ECC_SERRLKUPA0_VALID7_SET_MSK 0x40000000
4338 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID7 register field value. */
4339 #define ALT_ECC_SERRLKUPA0_VALID7_CLR_MSK 0xbfffffff
4340 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID7 register field. */
4341 #define ALT_ECC_SERRLKUPA0_VALID7_RESET 0x0
4342 /* Extracts the ALT_ECC_SERRLKUPA0_VALID7 field value from a register. */
4343 #define ALT_ECC_SERRLKUPA0_VALID7_GET(value) (((value) & 0x40000000) >> 30)
4344 /* Produces a ALT_ECC_SERRLKUPA0_VALID7 register field value suitable for setting the register. */
4345 #define ALT_ECC_SERRLKUPA0_VALID7_SET(value) (((value) << 30) & 0x40000000)
4346 
4347 /*
4348  * Field : VALID8
4349  *
4350  *
4351  * Field Access Macros:
4352  *
4353  */
4354 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPA0_VALID8 register field. */
4355 #define ALT_ECC_SERRLKUPA0_VALID8_LSB 31
4356 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPA0_VALID8 register field. */
4357 #define ALT_ECC_SERRLKUPA0_VALID8_MSB 31
4358 /* The width in bits of the ALT_ECC_SERRLKUPA0_VALID8 register field. */
4359 #define ALT_ECC_SERRLKUPA0_VALID8_WIDTH 1
4360 /* The mask used to set the ALT_ECC_SERRLKUPA0_VALID8 register field value. */
4361 #define ALT_ECC_SERRLKUPA0_VALID8_SET_MSK 0x80000000
4362 /* The mask used to clear the ALT_ECC_SERRLKUPA0_VALID8 register field value. */
4363 #define ALT_ECC_SERRLKUPA0_VALID8_CLR_MSK 0x7fffffff
4364 /* The reset value of the ALT_ECC_SERRLKUPA0_VALID8 register field. */
4365 #define ALT_ECC_SERRLKUPA0_VALID8_RESET 0x0
4366 /* Extracts the ALT_ECC_SERRLKUPA0_VALID8 field value from a register. */
4367 #define ALT_ECC_SERRLKUPA0_VALID8_GET(value) (((value) & 0x80000000) >> 31)
4368 /* Produces a ALT_ECC_SERRLKUPA0_VALID8 register field value suitable for setting the register. */
4369 #define ALT_ECC_SERRLKUPA0_VALID8_SET(value) (((value) << 31) & 0x80000000)
4370 
4371 #ifndef __ASSEMBLY__
4372 /*
4373  * WARNING: The C register and register group struct declarations are provided for
4374  * convenience and illustrative purposes. They should, however, be used with
4375  * caution as the C language standard provides no guarantees about the alignment or
4376  * atomicity of device memory accesses. The recommended practice for coding device
4377  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4378  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4379  * alt_write_dword() functions for 64 bit registers.
4380  *
4381  * The struct declaration for register ALT_ECC_SERRLKUPA0.
4382  */
4383 struct ALT_ECC_SERRLKUPA0_s
4384 {
4385  const volatile uint32_t Address : 24; /* ALT_ECC_SERRLKUPA0_ADDRESS */
4386  volatile uint32_t VALID1 : 1; /* ALT_ECC_SERRLKUPA0_VALID1 */
4387  volatile uint32_t VALID2 : 1; /* ALT_ECC_SERRLKUPA0_VALID2 */
4388  volatile uint32_t VALID3 : 1; /* ALT_ECC_SERRLKUPA0_VALID3 */
4389  volatile uint32_t VALID4 : 1; /* ALT_ECC_SERRLKUPA0_VALID4 */
4390  volatile uint32_t VALID5 : 1; /* ALT_ECC_SERRLKUPA0_VALID5 */
4391  volatile uint32_t VALID6 : 1; /* ALT_ECC_SERRLKUPA0_VALID6 */
4392  volatile uint32_t VALID7 : 1; /* ALT_ECC_SERRLKUPA0_VALID7 */
4393  volatile uint32_t VALID8 : 1; /* ALT_ECC_SERRLKUPA0_VALID8 */
4394 };
4395 
4396 /* The typedef declaration for register ALT_ECC_SERRLKUPA0. */
4397 typedef struct ALT_ECC_SERRLKUPA0_s ALT_ECC_SERRLKUPA0_t;
4398 #endif /* __ASSEMBLY__ */
4399 
4400 /* The reset value of the ALT_ECC_SERRLKUPA0 register. */
4401 #define ALT_ECC_SERRLKUPA0_RESET 0x00000000
4402 /* The byte offset of the ALT_ECC_SERRLKUPA0 register from the beginning of the component. */
4403 #define ALT_ECC_SERRLKUPA0_OFST 0x90
4404 /* The address of the ALT_ECC_SERRLKUPA0 register. */
4405 #define ALT_ECC_SERRLKUPA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRLKUPA0_OFST))
4406 
4407 /*
4408  * Register : SERRLKUPB0
4409  *
4410  * Single-bit error address in LOOKUP TABLE for PORTB.
4411  *
4412  * Valid flag bit. Valid bit indicates if the address in this register is current
4413  * or stale.
4414  *
4415  * IF IP is having a single decoder, VALID8 will be used
4416  *
4417  * IF IP is having multiple decoder, The lowest decoder will be represented on
4418  * VALID1 and the next will on VALID2.
4419  *
4420  * It increases onward to VALID8.
4421  *
4422  * Register Layout
4423  *
4424  * Bits | Access | Reset | Description
4425  * :-------|:-------|:------|:---------------------------
4426  * [23:0] | R | 0x0 | ALT_ECC_SERRLKUPB0_ADDRESS
4427  * [24] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID1
4428  * [25] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID2
4429  * [26] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID3
4430  * [27] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID4
4431  * [28] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID5
4432  * [29] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID6
4433  * [30] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID7
4434  * [31] | RW | 0x0 | ALT_ECC_SERRLKUPB0_VALID8
4435  *
4436  */
4437 /*
4438  * Field : Address
4439  *
4440  * Recent Single-bit error address.
4441  *
4442  * This register shows the address of the each single-bit error. RAM size will
4443  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
4444  * 30-16 will be reserved and read as zero.
4445  *
4446  * Field Access Macros:
4447  *
4448  */
4449 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_ADDRESS register field. */
4450 #define ALT_ECC_SERRLKUPB0_ADDRESS_LSB 0
4451 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_ADDRESS register field. */
4452 #define ALT_ECC_SERRLKUPB0_ADDRESS_MSB 23
4453 /* The width in bits of the ALT_ECC_SERRLKUPB0_ADDRESS register field. */
4454 #define ALT_ECC_SERRLKUPB0_ADDRESS_WIDTH 24
4455 /* The mask used to set the ALT_ECC_SERRLKUPB0_ADDRESS register field value. */
4456 #define ALT_ECC_SERRLKUPB0_ADDRESS_SET_MSK 0x00ffffff
4457 /* The mask used to clear the ALT_ECC_SERRLKUPB0_ADDRESS register field value. */
4458 #define ALT_ECC_SERRLKUPB0_ADDRESS_CLR_MSK 0xff000000
4459 /* The reset value of the ALT_ECC_SERRLKUPB0_ADDRESS register field. */
4460 #define ALT_ECC_SERRLKUPB0_ADDRESS_RESET 0x0
4461 /* Extracts the ALT_ECC_SERRLKUPB0_ADDRESS field value from a register. */
4462 #define ALT_ECC_SERRLKUPB0_ADDRESS_GET(value) (((value) & 0x00ffffff) >> 0)
4463 /* Produces a ALT_ECC_SERRLKUPB0_ADDRESS register field value suitable for setting the register. */
4464 #define ALT_ECC_SERRLKUPB0_ADDRESS_SET(value) (((value) << 0) & 0x00ffffff)
4465 
4466 /*
4467  * Field : VALID1
4468  *
4469  *
4470  * Field Access Macros:
4471  *
4472  */
4473 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID1 register field. */
4474 #define ALT_ECC_SERRLKUPB0_VALID1_LSB 24
4475 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID1 register field. */
4476 #define ALT_ECC_SERRLKUPB0_VALID1_MSB 24
4477 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID1 register field. */
4478 #define ALT_ECC_SERRLKUPB0_VALID1_WIDTH 1
4479 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID1 register field value. */
4480 #define ALT_ECC_SERRLKUPB0_VALID1_SET_MSK 0x01000000
4481 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID1 register field value. */
4482 #define ALT_ECC_SERRLKUPB0_VALID1_CLR_MSK 0xfeffffff
4483 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID1 register field. */
4484 #define ALT_ECC_SERRLKUPB0_VALID1_RESET 0x0
4485 /* Extracts the ALT_ECC_SERRLKUPB0_VALID1 field value from a register. */
4486 #define ALT_ECC_SERRLKUPB0_VALID1_GET(value) (((value) & 0x01000000) >> 24)
4487 /* Produces a ALT_ECC_SERRLKUPB0_VALID1 register field value suitable for setting the register. */
4488 #define ALT_ECC_SERRLKUPB0_VALID1_SET(value) (((value) << 24) & 0x01000000)
4489 
4490 /*
4491  * Field : VALID2
4492  *
4493  *
4494  * Field Access Macros:
4495  *
4496  */
4497 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID2 register field. */
4498 #define ALT_ECC_SERRLKUPB0_VALID2_LSB 25
4499 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID2 register field. */
4500 #define ALT_ECC_SERRLKUPB0_VALID2_MSB 25
4501 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID2 register field. */
4502 #define ALT_ECC_SERRLKUPB0_VALID2_WIDTH 1
4503 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID2 register field value. */
4504 #define ALT_ECC_SERRLKUPB0_VALID2_SET_MSK 0x02000000
4505 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID2 register field value. */
4506 #define ALT_ECC_SERRLKUPB0_VALID2_CLR_MSK 0xfdffffff
4507 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID2 register field. */
4508 #define ALT_ECC_SERRLKUPB0_VALID2_RESET 0x0
4509 /* Extracts the ALT_ECC_SERRLKUPB0_VALID2 field value from a register. */
4510 #define ALT_ECC_SERRLKUPB0_VALID2_GET(value) (((value) & 0x02000000) >> 25)
4511 /* Produces a ALT_ECC_SERRLKUPB0_VALID2 register field value suitable for setting the register. */
4512 #define ALT_ECC_SERRLKUPB0_VALID2_SET(value) (((value) << 25) & 0x02000000)
4513 
4514 /*
4515  * Field : VALID3
4516  *
4517  *
4518  * Field Access Macros:
4519  *
4520  */
4521 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID3 register field. */
4522 #define ALT_ECC_SERRLKUPB0_VALID3_LSB 26
4523 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID3 register field. */
4524 #define ALT_ECC_SERRLKUPB0_VALID3_MSB 26
4525 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID3 register field. */
4526 #define ALT_ECC_SERRLKUPB0_VALID3_WIDTH 1
4527 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID3 register field value. */
4528 #define ALT_ECC_SERRLKUPB0_VALID3_SET_MSK 0x04000000
4529 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID3 register field value. */
4530 #define ALT_ECC_SERRLKUPB0_VALID3_CLR_MSK 0xfbffffff
4531 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID3 register field. */
4532 #define ALT_ECC_SERRLKUPB0_VALID3_RESET 0x0
4533 /* Extracts the ALT_ECC_SERRLKUPB0_VALID3 field value from a register. */
4534 #define ALT_ECC_SERRLKUPB0_VALID3_GET(value) (((value) & 0x04000000) >> 26)
4535 /* Produces a ALT_ECC_SERRLKUPB0_VALID3 register field value suitable for setting the register. */
4536 #define ALT_ECC_SERRLKUPB0_VALID3_SET(value) (((value) << 26) & 0x04000000)
4537 
4538 /*
4539  * Field : VALID4
4540  *
4541  *
4542  * Field Access Macros:
4543  *
4544  */
4545 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID4 register field. */
4546 #define ALT_ECC_SERRLKUPB0_VALID4_LSB 27
4547 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID4 register field. */
4548 #define ALT_ECC_SERRLKUPB0_VALID4_MSB 27
4549 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID4 register field. */
4550 #define ALT_ECC_SERRLKUPB0_VALID4_WIDTH 1
4551 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID4 register field value. */
4552 #define ALT_ECC_SERRLKUPB0_VALID4_SET_MSK 0x08000000
4553 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID4 register field value. */
4554 #define ALT_ECC_SERRLKUPB0_VALID4_CLR_MSK 0xf7ffffff
4555 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID4 register field. */
4556 #define ALT_ECC_SERRLKUPB0_VALID4_RESET 0x0
4557 /* Extracts the ALT_ECC_SERRLKUPB0_VALID4 field value from a register. */
4558 #define ALT_ECC_SERRLKUPB0_VALID4_GET(value) (((value) & 0x08000000) >> 27)
4559 /* Produces a ALT_ECC_SERRLKUPB0_VALID4 register field value suitable for setting the register. */
4560 #define ALT_ECC_SERRLKUPB0_VALID4_SET(value) (((value) << 27) & 0x08000000)
4561 
4562 /*
4563  * Field : VALID5
4564  *
4565  *
4566  * Field Access Macros:
4567  *
4568  */
4569 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID5 register field. */
4570 #define ALT_ECC_SERRLKUPB0_VALID5_LSB 28
4571 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID5 register field. */
4572 #define ALT_ECC_SERRLKUPB0_VALID5_MSB 28
4573 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID5 register field. */
4574 #define ALT_ECC_SERRLKUPB0_VALID5_WIDTH 1
4575 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID5 register field value. */
4576 #define ALT_ECC_SERRLKUPB0_VALID5_SET_MSK 0x10000000
4577 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID5 register field value. */
4578 #define ALT_ECC_SERRLKUPB0_VALID5_CLR_MSK 0xefffffff
4579 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID5 register field. */
4580 #define ALT_ECC_SERRLKUPB0_VALID5_RESET 0x0
4581 /* Extracts the ALT_ECC_SERRLKUPB0_VALID5 field value from a register. */
4582 #define ALT_ECC_SERRLKUPB0_VALID5_GET(value) (((value) & 0x10000000) >> 28)
4583 /* Produces a ALT_ECC_SERRLKUPB0_VALID5 register field value suitable for setting the register. */
4584 #define ALT_ECC_SERRLKUPB0_VALID5_SET(value) (((value) << 28) & 0x10000000)
4585 
4586 /*
4587  * Field : VALID6
4588  *
4589  *
4590  * Field Access Macros:
4591  *
4592  */
4593 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID6 register field. */
4594 #define ALT_ECC_SERRLKUPB0_VALID6_LSB 29
4595 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID6 register field. */
4596 #define ALT_ECC_SERRLKUPB0_VALID6_MSB 29
4597 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID6 register field. */
4598 #define ALT_ECC_SERRLKUPB0_VALID6_WIDTH 1
4599 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID6 register field value. */
4600 #define ALT_ECC_SERRLKUPB0_VALID6_SET_MSK 0x20000000
4601 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID6 register field value. */
4602 #define ALT_ECC_SERRLKUPB0_VALID6_CLR_MSK 0xdfffffff
4603 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID6 register field. */
4604 #define ALT_ECC_SERRLKUPB0_VALID6_RESET 0x0
4605 /* Extracts the ALT_ECC_SERRLKUPB0_VALID6 field value from a register. */
4606 #define ALT_ECC_SERRLKUPB0_VALID6_GET(value) (((value) & 0x20000000) >> 29)
4607 /* Produces a ALT_ECC_SERRLKUPB0_VALID6 register field value suitable for setting the register. */
4608 #define ALT_ECC_SERRLKUPB0_VALID6_SET(value) (((value) << 29) & 0x20000000)
4609 
4610 /*
4611  * Field : VALID7
4612  *
4613  *
4614  * Field Access Macros:
4615  *
4616  */
4617 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID7 register field. */
4618 #define ALT_ECC_SERRLKUPB0_VALID7_LSB 30
4619 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID7 register field. */
4620 #define ALT_ECC_SERRLKUPB0_VALID7_MSB 30
4621 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID7 register field. */
4622 #define ALT_ECC_SERRLKUPB0_VALID7_WIDTH 1
4623 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID7 register field value. */
4624 #define ALT_ECC_SERRLKUPB0_VALID7_SET_MSK 0x40000000
4625 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID7 register field value. */
4626 #define ALT_ECC_SERRLKUPB0_VALID7_CLR_MSK 0xbfffffff
4627 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID7 register field. */
4628 #define ALT_ECC_SERRLKUPB0_VALID7_RESET 0x0
4629 /* Extracts the ALT_ECC_SERRLKUPB0_VALID7 field value from a register. */
4630 #define ALT_ECC_SERRLKUPB0_VALID7_GET(value) (((value) & 0x40000000) >> 30)
4631 /* Produces a ALT_ECC_SERRLKUPB0_VALID7 register field value suitable for setting the register. */
4632 #define ALT_ECC_SERRLKUPB0_VALID7_SET(value) (((value) << 30) & 0x40000000)
4633 
4634 /*
4635  * Field : VALID8
4636  *
4637  *
4638  * Field Access Macros:
4639  *
4640  */
4641 /* The Least Significant Bit (LSB) position of the ALT_ECC_SERRLKUPB0_VALID8 register field. */
4642 #define ALT_ECC_SERRLKUPB0_VALID8_LSB 31
4643 /* The Most Significant Bit (MSB) position of the ALT_ECC_SERRLKUPB0_VALID8 register field. */
4644 #define ALT_ECC_SERRLKUPB0_VALID8_MSB 31
4645 /* The width in bits of the ALT_ECC_SERRLKUPB0_VALID8 register field. */
4646 #define ALT_ECC_SERRLKUPB0_VALID8_WIDTH 1
4647 /* The mask used to set the ALT_ECC_SERRLKUPB0_VALID8 register field value. */
4648 #define ALT_ECC_SERRLKUPB0_VALID8_SET_MSK 0x80000000
4649 /* The mask used to clear the ALT_ECC_SERRLKUPB0_VALID8 register field value. */
4650 #define ALT_ECC_SERRLKUPB0_VALID8_CLR_MSK 0x7fffffff
4651 /* The reset value of the ALT_ECC_SERRLKUPB0_VALID8 register field. */
4652 #define ALT_ECC_SERRLKUPB0_VALID8_RESET 0x0
4653 /* Extracts the ALT_ECC_SERRLKUPB0_VALID8 field value from a register. */
4654 #define ALT_ECC_SERRLKUPB0_VALID8_GET(value) (((value) & 0x80000000) >> 31)
4655 /* Produces a ALT_ECC_SERRLKUPB0_VALID8 register field value suitable for setting the register. */
4656 #define ALT_ECC_SERRLKUPB0_VALID8_SET(value) (((value) << 31) & 0x80000000)
4657 
4658 #ifndef __ASSEMBLY__
4659 /*
4660  * WARNING: The C register and register group struct declarations are provided for
4661  * convenience and illustrative purposes. They should, however, be used with
4662  * caution as the C language standard provides no guarantees about the alignment or
4663  * atomicity of device memory accesses. The recommended practice for coding device
4664  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4665  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4666  * alt_write_dword() functions for 64 bit registers.
4667  *
4668  * The struct declaration for register ALT_ECC_SERRLKUPB0.
4669  */
4670 struct ALT_ECC_SERRLKUPB0_s
4671 {
4672  const volatile uint32_t Address : 24; /* ALT_ECC_SERRLKUPB0_ADDRESS */
4673  volatile uint32_t VALID1 : 1; /* ALT_ECC_SERRLKUPB0_VALID1 */
4674  volatile uint32_t VALID2 : 1; /* ALT_ECC_SERRLKUPB0_VALID2 */
4675  volatile uint32_t VALID3 : 1; /* ALT_ECC_SERRLKUPB0_VALID3 */
4676  volatile uint32_t VALID4 : 1; /* ALT_ECC_SERRLKUPB0_VALID4 */
4677  volatile uint32_t VALID5 : 1; /* ALT_ECC_SERRLKUPB0_VALID5 */
4678  volatile uint32_t VALID6 : 1; /* ALT_ECC_SERRLKUPB0_VALID6 */
4679  volatile uint32_t VALID7 : 1; /* ALT_ECC_SERRLKUPB0_VALID7 */
4680  volatile uint32_t VALID8 : 1; /* ALT_ECC_SERRLKUPB0_VALID8 */
4681 };
4682 
4683 /* The typedef declaration for register ALT_ECC_SERRLKUPB0. */
4684 typedef struct ALT_ECC_SERRLKUPB0_s ALT_ECC_SERRLKUPB0_t;
4685 #endif /* __ASSEMBLY__ */
4686 
4687 /* The reset value of the ALT_ECC_SERRLKUPB0 register. */
4688 #define ALT_ECC_SERRLKUPB0_RESET 0x00000000
4689 /* The byte offset of the ALT_ECC_SERRLKUPB0 register from the beginning of the component. */
4690 #define ALT_ECC_SERRLKUPB0_OFST 0xd0
4691 /* The address of the ALT_ECC_SERRLKUPB0 register. */
4692 #define ALT_ECC_SERRLKUPB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRLKUPB0_OFST))
4693 
4694 #ifndef __ASSEMBLY__
4695 /*
4696  * WARNING: The C register and register group struct declarations are provided for
4697  * convenience and illustrative purposes. They should, however, be used with
4698  * caution as the C language standard provides no guarantees about the alignment or
4699  * atomicity of device memory accesses. The recommended practice for coding device
4700  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4701  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4702  * alt_write_dword() functions for 64 bit registers.
4703  *
4704  * The struct declaration for register group ALT_ECC.
4705  */
4706 struct ALT_ECC_s
4707 {
4708  volatile ALT_ECC_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_IP_REV_ID */
4709  volatile ALT_ECC_IP_REV_ID2_t IP_REV_ID2; /* ALT_ECC_IP_REV_ID2 */
4710  volatile ALT_ECC_CTRL_t CTRL; /* ALT_ECC_CTRL */
4711  volatile ALT_ECC_INITSTAT_t INITSTAT; /* ALT_ECC_INITSTAT */
4712  volatile ALT_ECC_ERRINTEN_t ERRINTEN; /* ALT_ECC_ERRINTEN */
4713  volatile ALT_ECC_ERRINTENS_t ERRINTENS; /* ALT_ECC_ERRINTENS */
4714  volatile ALT_ECC_ERRINTENR_t ERRINTENR; /* ALT_ECC_ERRINTENR */
4715  volatile ALT_ECC_INTMODE_t INTMODE; /* ALT_ECC_INTMODE */
4716  volatile ALT_ECC_INTSTAT_t INTSTAT; /* ALT_ECC_INTSTAT */
4717  volatile ALT_ECC_INTTEST_t INTTEST; /* ALT_ECC_INTTEST */
4718  volatile ALT_ECC_MODSTAT_t MODSTAT; /* ALT_ECC_MODSTAT */
4719  volatile ALT_ECC_DERRADDRA_t DERRADDRA; /* ALT_ECC_DERRADDRA */
4720  volatile ALT_ECC_SERRADDRA_t SERRADDRA; /* ALT_ECC_SERRADDRA */
4721  volatile ALT_ECC_DERRADDRB_t DERRADDRB; /* ALT_ECC_DERRADDRB */
4722  volatile ALT_ECC_SERRADDRB_t SERRADDRB; /* ALT_ECC_SERRADDRB */
4723  volatile ALT_ECC_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_SERRCNTREG */
4724  volatile ALT_ECC_ECC_ADDRBUS_t ECC_Addrbus; /* ALT_ECC_ECC_ADDRBUS */
4725  volatile ALT_ECC_ECC_RDATA0BUS_t ECC_RData0bus; /* ALT_ECC_ECC_RDATA0BUS */
4726  volatile ALT_ECC_ECC_RDATA1BUS_t ECC_RData1bus; /* ALT_ECC_ECC_RDATA1BUS */
4727  volatile ALT_ECC_ECC_RDATA2BUS_t ECC_RData2bus; /* ALT_ECC_ECC_RDATA2BUS */
4728  volatile ALT_ECC_ECC_RDATA3BUS_t ECC_RData3bus; /* ALT_ECC_ECC_RDATA3BUS */
4729  volatile ALT_ECC_ECC_WDATA0BUS_t ECC_WData0bus; /* ALT_ECC_ECC_WDATA0BUS */
4730  volatile ALT_ECC_ECC_WDATA1BUS_t ECC_WData1bus; /* ALT_ECC_ECC_WDATA1BUS */
4731  volatile ALT_ECC_ECC_WDATA2BUS_t ECC_WData2bus; /* ALT_ECC_ECC_WDATA2BUS */
4732  volatile ALT_ECC_ECC_WDATA3BUS_t ECC_WData3bus; /* ALT_ECC_ECC_WDATA3BUS */
4733  volatile ALT_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus; /* ALT_ECC_ECC_RDATAECC0BUS */
4734  volatile ALT_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus; /* ALT_ECC_ECC_RDATAECC1BUS */
4735  volatile ALT_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus; /* ALT_ECC_ECC_WDATAECC0BUS */
4736  volatile ALT_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus; /* ALT_ECC_ECC_WDATAECC1BUS */
4737  volatile ALT_ECC_ECC_DBYTECTRL_t ECC_dbytectrl; /* ALT_ECC_ECC_DBYTECTRL */
4738  volatile ALT_ECC_ECC_ACCCTRL_t ECC_accctrl; /* ALT_ECC_ECC_ACCCTRL */
4739  volatile ALT_ECC_ECC_STARTACC_t ECC_startacc; /* ALT_ECC_ECC_STARTACC */
4740  volatile ALT_ECC_ECC_WDCTRL_t ECC_wdctrl; /* ALT_ECC_ECC_WDCTRL */
4741  volatile ALT_ECC_ECC_DECODERSTAT_t ECC_DECODERSTAT; /* ALT_ECC_ECC_DECODERSTAT */
4742  volatile uint32_t _pad_0x88_0x8f[2]; /* *UNDEFINED* */
4743  volatile ALT_ECC_SERRLKUPA0_t SERRLKUPA0; /* ALT_ECC_SERRLKUPA0 */
4744  volatile uint32_t _pad_0x94_0xcf[15]; /* *UNDEFINED* */
4745  volatile ALT_ECC_SERRLKUPB0_t SERRLKUPB0; /* ALT_ECC_SERRLKUPB0 */
4746  volatile uint32_t _pad_0xd4_0x400[203]; /* *UNDEFINED* */
4747 };
4748 
4749 /* The typedef declaration for register group ALT_ECC. */
4750 typedef struct ALT_ECC_s ALT_ECC_t;
4751 /* The struct declaration for the raw register contents of register group ALT_ECC. */
4752 struct ALT_ECC_raw_s
4753 {
4754  volatile uint32_t IP_REV_ID; /* ALT_ECC_IP_REV_ID */
4755  volatile uint32_t IP_REV_ID2; /* ALT_ECC_IP_REV_ID2 */
4756  volatile uint32_t CTRL; /* ALT_ECC_CTRL */
4757  volatile uint32_t INITSTAT; /* ALT_ECC_INITSTAT */
4758  volatile uint32_t ERRINTEN; /* ALT_ECC_ERRINTEN */
4759  volatile uint32_t ERRINTENS; /* ALT_ECC_ERRINTENS */
4760  volatile uint32_t ERRINTENR; /* ALT_ECC_ERRINTENR */
4761  volatile uint32_t INTMODE; /* ALT_ECC_INTMODE */
4762  volatile uint32_t INTSTAT; /* ALT_ECC_INTSTAT */
4763  volatile uint32_t INTTEST; /* ALT_ECC_INTTEST */
4764  volatile uint32_t MODSTAT; /* ALT_ECC_MODSTAT */
4765  volatile uint32_t DERRADDRA; /* ALT_ECC_DERRADDRA */
4766  volatile uint32_t SERRADDRA; /* ALT_ECC_SERRADDRA */
4767  volatile uint32_t DERRADDRB; /* ALT_ECC_DERRADDRB */
4768  volatile uint32_t SERRADDRB; /* ALT_ECC_SERRADDRB */
4769  volatile uint32_t SERRCNTREG; /* ALT_ECC_SERRCNTREG */
4770  volatile uint32_t ECC_Addrbus; /* ALT_ECC_ECC_ADDRBUS */
4771  volatile uint32_t ECC_RData0bus; /* ALT_ECC_ECC_RDATA0BUS */
4772  volatile uint32_t ECC_RData1bus; /* ALT_ECC_ECC_RDATA1BUS */
4773  volatile uint32_t ECC_RData2bus; /* ALT_ECC_ECC_RDATA2BUS */
4774  volatile uint32_t ECC_RData3bus; /* ALT_ECC_ECC_RDATA3BUS */
4775  volatile uint32_t ECC_WData0bus; /* ALT_ECC_ECC_WDATA0BUS */
4776  volatile uint32_t ECC_WData1bus; /* ALT_ECC_ECC_WDATA1BUS */
4777  volatile uint32_t ECC_WData2bus; /* ALT_ECC_ECC_WDATA2BUS */
4778  volatile uint32_t ECC_WData3bus; /* ALT_ECC_ECC_WDATA3BUS */
4779  volatile uint32_t ECC_RDataecc0bus; /* ALT_ECC_ECC_RDATAECC0BUS */
4780  volatile uint32_t ECC_RDataecc1bus; /* ALT_ECC_ECC_RDATAECC1BUS */
4781  volatile uint32_t ECC_WDataecc0bus; /* ALT_ECC_ECC_WDATAECC0BUS */
4782  volatile uint32_t ECC_WDataecc1bus; /* ALT_ECC_ECC_WDATAECC1BUS */
4783  volatile uint32_t ECC_dbytectrl; /* ALT_ECC_ECC_DBYTECTRL */
4784  volatile uint32_t ECC_accctrl; /* ALT_ECC_ECC_ACCCTRL */
4785  volatile uint32_t ECC_startacc; /* ALT_ECC_ECC_STARTACC */
4786  volatile uint32_t ECC_wdctrl; /* ALT_ECC_ECC_WDCTRL */
4787  volatile uint32_t ECC_DECODERSTAT; /* ALT_ECC_ECC_DECODERSTAT */
4788  volatile uint32_t _pad_0x88_0x8f[2]; /* *UNDEFINED* */
4789  volatile uint32_t SERRLKUPA0; /* ALT_ECC_SERRLKUPA0 */
4790  volatile uint32_t _pad_0x94_0xcf[15]; /* *UNDEFINED* */
4791  volatile uint32_t SERRLKUPB0; /* ALT_ECC_SERRLKUPB0 */
4792  volatile uint32_t _pad_0xd4_0x400[203]; /* *UNDEFINED* */
4793 };
4794 
4795 /* The typedef declaration for the raw register contents of register group ALT_ECC. */
4796 typedef struct ALT_ECC_raw_s ALT_ECC_raw_t;
4797 #endif /* __ASSEMBLY__ */
4798 
4799 
4800 #ifdef __cplusplus
4801 }
4802 #endif /* __cplusplus */
4803 #endif /* __ALT_SOCAL_ECC_H__ */
4804