Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_gpio.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_GPIO */
34 
35 #ifndef __ALT_SOCAL_GPIO_H__
36 #define __ALT_SOCAL_GPIO_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : GPIO
50  * DW_apb_gpio address block
51  *
52  */
53 /*
54  * Register : Port A data register - GPIO_SWPORTA_DR
55  *
56  * Name: Port A data register
57  *
58  * Size: 1-32 bits
59  *
60  * Address Offset: 0x00
61  *
62  * Read/Write Access: Read/Write
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :--------|:-------|:------|:-----------------------------------------
68  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR
69  * [31:24] | ??? | 0x0 | *UNDEFINED*
70  *
71  */
72 /*
73  * Field : GPIO_SWPORTA_DR
74  *
75  * Values written to this register are output on the I/O signals
76  *
77  * for Port A if the corresponding data direction bits for Port A
78  *
79  * are set to Output mode and the corresponding control bit for
80  *
81  * Port A is set to Software mode. The value read back is equal
82  *
83  * to the last value written to this register.
84  *
85  * DO NOT PUBLISH BELOW THIS LINE
86  *
87  * For internal usage only, [0:18] for SDM, [0:23] for HPS
88  *
89  * Field Access Macros:
90  *
91  */
92 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
93 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0
94 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
95 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 23
96 /* The width in bits of the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
97 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 24
98 /* The mask used to set the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
99 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x00ffffff
100 /* The mask used to clear the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
101 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xff000000
102 /* The reset value of the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
103 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0
104 /* Extracts the ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
105 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x00ffffff) >> 0)
106 /* Produces a ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
107 #define ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x00ffffff)
108 
109 #ifndef __ASSEMBLY__
110 /*
111  * WARNING: The C register and register group struct declarations are provided for
112  * convenience and illustrative purposes. They should, however, be used with
113  * caution as the C language standard provides no guarantees about the alignment or
114  * atomicity of device memory accesses. The recommended practice for coding device
115  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
116  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
117  * alt_write_dword() functions for 64 bit registers.
118  *
119  * The struct declaration for register ALT_GPIO_GPIO_SWPORTA_DR.
120  */
121 struct ALT_GPIO_GPIO_SWPORTA_DR_s
122 {
123  volatile uint32_t GPIO_SWPORTA_DR : 24; /* ALT_GPIO_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR */
124  uint32_t : 8; /* *UNDEFINED* */
125 };
126 
127 /* The typedef declaration for register ALT_GPIO_GPIO_SWPORTA_DR. */
128 typedef struct ALT_GPIO_GPIO_SWPORTA_DR_s ALT_GPIO_GPIO_SWPORTA_DR_t;
129 #endif /* __ASSEMBLY__ */
130 
131 /* The reset value of the ALT_GPIO_GPIO_SWPORTA_DR register. */
132 #define ALT_GPIO_GPIO_SWPORTA_DR_RESET 0x00000000
133 /* The byte offset of the ALT_GPIO_GPIO_SWPORTA_DR register from the beginning of the component. */
134 #define ALT_GPIO_GPIO_SWPORTA_DR_OFST 0x0
135 /* The address of the ALT_GPIO_GPIO_SWPORTA_DR register. */
136 #define ALT_GPIO_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_SWPORTA_DR_OFST))
137 
138 /*
139  * Register : Port A Data Direction Register - GPIO_SWPORTA_DDR
140  *
141  * Name: Port A Data Direction Register
142  *
143  * Size: 1-32 bits
144  *
145  * Address Offset: 0x04
146  *
147  * Read/Write Access: Read/Write
148  *
149  * Register Layout
150  *
151  * Bits | Access | Reset | Description
152  * :--------|:-------|:--------|:-------------------------------------------
153  * [23:0] | RW | Unknown | ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
154  * [31:24] | ??? | Unknown | *UNDEFINED*
155  *
156  */
157 /*
158  * Field : GPIO_SWPORTA_DDR
159  *
160  * Values written to this register independently control the
161  *
162  * direction of the corresponding data bit in Port A. The
163  *
164  * default direction can be configured as input or output after
165  *
166  * system reset through the GPIO_DFLT_SRC_A parameter.
167  *
168  * 0 Input (default)
169  *
170  * 1 Output
171  *
172  * DO NOT PUBLISH BELOW THIS LINE
173  *
174  * For internal usage only, [0:18] for SDM, [0:23] for HPS
175  *
176  * Field Enumeration Values:
177  *
178  * Enum | Value | Description
179  * :-------------------------------------------------|:------|:-----------------
180  * ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction
181  * ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction
182  *
183  * Field Access Macros:
184  *
185  */
186 /*
187  * Enumerated value for register field ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
188  *
189  * Input Direction
190  */
191 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0
192 /*
193  * Enumerated value for register field ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
194  *
195  * Output Direction
196  */
197 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
198 
199 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
200 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0
201 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
202 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 23
203 /* The width in bits of the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
204 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 24
205 /* The mask used to set the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
206 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x00ffffff
207 /* The mask used to clear the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
208 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xff000000
209 /* The reset value of the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field is UNKNOWN. */
210 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0
211 /* Extracts the ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
212 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x00ffffff) >> 0)
213 /* Produces a ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
214 #define ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x00ffffff)
215 
216 #ifndef __ASSEMBLY__
217 /*
218  * WARNING: The C register and register group struct declarations are provided for
219  * convenience and illustrative purposes. They should, however, be used with
220  * caution as the C language standard provides no guarantees about the alignment or
221  * atomicity of device memory accesses. The recommended practice for coding device
222  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
223  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
224  * alt_write_dword() functions for 64 bit registers.
225  *
226  * The struct declaration for register ALT_GPIO_GPIO_SWPORTA_DDR.
227  */
228 struct ALT_GPIO_GPIO_SWPORTA_DDR_s
229 {
230  volatile uint32_t GPIO_SWPORTA_DDR : 24; /* ALT_GPIO_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR */
231  uint32_t : 8; /* *UNDEFINED* */
232 };
233 
234 /* The typedef declaration for register ALT_GPIO_GPIO_SWPORTA_DDR. */
235 typedef struct ALT_GPIO_GPIO_SWPORTA_DDR_s ALT_GPIO_GPIO_SWPORTA_DDR_t;
236 #endif /* __ASSEMBLY__ */
237 
238 /* The reset value of the ALT_GPIO_GPIO_SWPORTA_DDR register. */
239 #define ALT_GPIO_GPIO_SWPORTA_DDR_RESET 0x00000000
240 /* The byte offset of the ALT_GPIO_GPIO_SWPORTA_DDR register from the beginning of the component. */
241 #define ALT_GPIO_GPIO_SWPORTA_DDR_OFST 0x4
242 /* The address of the ALT_GPIO_GPIO_SWPORTA_DDR register. */
243 #define ALT_GPIO_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_SWPORTA_DDR_OFST))
244 
245 /*
246  * Register : Interrupt enable register - GPIO_INTEN
247  *
248  * Name: Interrupt enable register
249  *
250  * Size: 1-32 bits
251  *
252  * Address Offset: 0x30
253  *
254  * Read/Write Access: Read/Write
255  *
256  * Register Layout
257  *
258  * Bits | Access | Reset | Description
259  * :--------|:-------|:------|:-------------------------------
260  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_INTEN_GPIO_INTEN
261  * [31:24] | ??? | 0x0 | *UNDEFINED*
262  *
263  */
264 /*
265  * Field : GPIO_INTEN
266  *
267  * Allows each bit of Port A to be configured for interrupts. By
268  *
269  * default the generation of interrupts is disabled. Whenever a 1
270  *
271  * is written to a bit of this register, it configures the
272  *
273  * corresponding bit on Port A to become an interrupt;
274  *
275  * otherwise, Port A operates as a normal GPIO signal.
276  *
277  * Interrupts are disabled on the corresponding bits of Port A if
278  *
279  * the corresponding data direction register is set to Output or if
280  *
281  * Port A mode is set to Hardware.
282  *
283  * 0 Configure Port A bit as normal GPIO signal (default)
284  *
285  * 1 Configure Port A bit as interrupt
286  *
287  * DO NOT PUBLISH BELOW THIS LINE
288  *
289  * For internal usage only, [0:18] for SDM, [0:23] for HPS
290  *
291  * Field Enumeration Values:
292  *
293  * Enum | Value | Description
294  * :------------------------------------------|:------|:----------------------
295  * ALT_GPIO_GPIO_INTEN_GPIO_INTEN_E_DISABLED | 0x0 | Interrupt is disabled
296  * ALT_GPIO_GPIO_INTEN_GPIO_INTEN_E_ENABLED | 0x1 | Interrupt is enabled
297  *
298  * Field Access Macros:
299  *
300  */
301 /*
302  * Enumerated value for register field ALT_GPIO_GPIO_INTEN_GPIO_INTEN
303  *
304  * Interrupt is disabled
305  */
306 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_E_DISABLED 0x0
307 /*
308  * Enumerated value for register field ALT_GPIO_GPIO_INTEN_GPIO_INTEN
309  *
310  * Interrupt is enabled
311  */
312 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_E_ENABLED 0x1
313 
314 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field. */
315 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_LSB 0
316 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field. */
317 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_MSB 23
318 /* The width in bits of the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field. */
319 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_WIDTH 24
320 /* The mask used to set the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field value. */
321 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x00ffffff
322 /* The mask used to clear the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field value. */
323 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xff000000
324 /* The reset value of the ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field. */
325 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_RESET 0x0
326 /* Extracts the ALT_GPIO_GPIO_INTEN_GPIO_INTEN field value from a register. */
327 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x00ffffff) >> 0)
328 /* Produces a ALT_GPIO_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
329 #define ALT_GPIO_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x00ffffff)
330 
331 #ifndef __ASSEMBLY__
332 /*
333  * WARNING: The C register and register group struct declarations are provided for
334  * convenience and illustrative purposes. They should, however, be used with
335  * caution as the C language standard provides no guarantees about the alignment or
336  * atomicity of device memory accesses. The recommended practice for coding device
337  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
338  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
339  * alt_write_dword() functions for 64 bit registers.
340  *
341  * The struct declaration for register ALT_GPIO_GPIO_INTEN.
342  */
343 struct ALT_GPIO_GPIO_INTEN_s
344 {
345  volatile uint32_t GPIO_INTEN : 24; /* ALT_GPIO_GPIO_INTEN_GPIO_INTEN */
346  uint32_t : 8; /* *UNDEFINED* */
347 };
348 
349 /* The typedef declaration for register ALT_GPIO_GPIO_INTEN. */
350 typedef struct ALT_GPIO_GPIO_INTEN_s ALT_GPIO_GPIO_INTEN_t;
351 #endif /* __ASSEMBLY__ */
352 
353 /* The reset value of the ALT_GPIO_GPIO_INTEN register. */
354 #define ALT_GPIO_GPIO_INTEN_RESET 0x00000000
355 /* The byte offset of the ALT_GPIO_GPIO_INTEN register from the beginning of the component. */
356 #define ALT_GPIO_GPIO_INTEN_OFST 0x30
357 /* The address of the ALT_GPIO_GPIO_INTEN register. */
358 #define ALT_GPIO_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_INTEN_OFST))
359 
360 /*
361  * Register : Interrupt mask register - GPIO_INTMASK
362  *
363  * Name: Interrupt mask register
364  *
365  * Size: 1-32 bits
366  *
367  * Address Offset: 0x34
368  *
369  * Read/Write Access: Read/Write
370  *
371  * Register Layout
372  *
373  * Bits | Access | Reset | Description
374  * :--------|:-------|:------|:-----------------------------------
375  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK
376  * [31:24] | ??? | 0x0 | *UNDEFINED*
377  *
378  */
379 /*
380  * Field : GPIO_INTMASK
381  *
382  * Controls whether an interrupt on Port A can create an
383  *
384  * interrupt for the interrupt controller by not masking it. By
385  *
386  * default, all interrupts bits are unmasked. Whenever a 1 is
387  *
388  * written to a bit in this register, it masks the interrupt
389  *
390  * generation capability for this signal; otherwise interrupts are
391  *
392  * allowed through. The unmasked status can be read as well as
393  *
394  * the resultant status after masking.
395  *
396  * 0 Interrupt bits are unmasked (default)
397  *
398  * 1 Mask interrupt
399  *
400  * DO NOT PUBLISH BELOW THIS LINE
401  *
402  * For internal usage only, [0:18] for SDM, [0:23] for HPS
403  *
404  * Field Enumeration Values:
405  *
406  * Enum | Value | Description
407  * :----------------------------------------------|:------|:----------------------------
408  * ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_E_DISABLED | 0x0 | Interrupt bits are unmasked
409  * ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_E_ENABLED | 0x1 | Mask interrupt
410  *
411  * Field Access Macros:
412  *
413  */
414 /*
415  * Enumerated value for register field ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK
416  *
417  * Interrupt bits are unmasked
418  */
419 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_E_DISABLED 0x0
420 /*
421  * Enumerated value for register field ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK
422  *
423  * Mask interrupt
424  */
425 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_E_ENABLED 0x1
426 
427 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field. */
428 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_LSB 0
429 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field. */
430 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_MSB 23
431 /* The width in bits of the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field. */
432 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_WIDTH 24
433 /* The mask used to set the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field value. */
434 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_SET_MSK 0x00ffffff
435 /* The mask used to clear the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field value. */
436 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_CLR_MSK 0xff000000
437 /* The reset value of the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field. */
438 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_RESET 0x0
439 /* Extracts the ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK field value from a register. */
440 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_GET(value) (((value) & 0x00ffffff) >> 0)
441 /* Produces a ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK register field value suitable for setting the register. */
442 #define ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK_SET(value) (((value) << 0) & 0x00ffffff)
443 
444 #ifndef __ASSEMBLY__
445 /*
446  * WARNING: The C register and register group struct declarations are provided for
447  * convenience and illustrative purposes. They should, however, be used with
448  * caution as the C language standard provides no guarantees about the alignment or
449  * atomicity of device memory accesses. The recommended practice for coding device
450  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
451  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
452  * alt_write_dword() functions for 64 bit registers.
453  *
454  * The struct declaration for register ALT_GPIO_GPIO_INTMASK.
455  */
456 struct ALT_GPIO_GPIO_INTMASK_s
457 {
458  volatile uint32_t GPIO_INTMASK : 24; /* ALT_GPIO_GPIO_INTMASK_GPIO_INTMASK */
459  uint32_t : 8; /* *UNDEFINED* */
460 };
461 
462 /* The typedef declaration for register ALT_GPIO_GPIO_INTMASK. */
463 typedef struct ALT_GPIO_GPIO_INTMASK_s ALT_GPIO_GPIO_INTMASK_t;
464 #endif /* __ASSEMBLY__ */
465 
466 /* The reset value of the ALT_GPIO_GPIO_INTMASK register. */
467 #define ALT_GPIO_GPIO_INTMASK_RESET 0x00000000
468 /* The byte offset of the ALT_GPIO_GPIO_INTMASK register from the beginning of the component. */
469 #define ALT_GPIO_GPIO_INTMASK_OFST 0x34
470 /* The address of the ALT_GPIO_GPIO_INTMASK register. */
471 #define ALT_GPIO_GPIO_INTMASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_INTMASK_OFST))
472 
473 /*
474  * Register : Interrupt level - GPIO_INTTYPE_LEVEL
475  *
476  * Name: Interrupt level
477  *
478  * Size: 1-32 bits
479  *
480  * Address Offset: 0x38
481  *
482  * Read/Write Access: Read/Write
483  *
484  * Register Layout
485  *
486  * Bits | Access | Reset | Description
487  * :--------|:-------|:------|:-----------------------------------------------
488  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
489  * [31:24] | ??? | 0x0 | *UNDEFINED*
490  *
491  */
492 /*
493  * Field : GPIO_INTTYPE_LEVEL
494  *
495  * Controls the type of interrupt that can occur on Port A.
496  *
497  * Whenever a 0 is written to a bit of this register, it configures
498  *
499  * the interrupt type to be level-sensitive; otherwise, it is
500  *
501  * edge-sensitive.
502  *
503  * 0 Level-sensitive (default)
504  *
505  * 1 Edge-sensitive
506  *
507  * DO NOT PUBLISH BELOW THIS LINE
508  *
509  * For internal usage only, [0:18] for SDM, [0:23] for HPS
510  *
511  * Field Enumeration Values:
512  *
513  * Enum | Value | Description
514  * :-----------------------------------------------------------------|:------|:-----------------------------
515  * ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL_SENSITIVE | 0x0 | Interrupt is level sensitive
516  * ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE_SENSITIVE | 0x1 | Interrupt is edge sensitive
517  *
518  * Field Access Macros:
519  *
520  */
521 /*
522  * Enumerated value for register field ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
523  *
524  * Interrupt is level sensitive
525  */
526 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL_SENSITIVE 0x0
527 /*
528  * Enumerated value for register field ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
529  *
530  * Interrupt is edge sensitive
531  */
532 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE_SENSITIVE 0x1
533 
534 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
535 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0
536 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
537 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 23
538 /* The width in bits of the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
539 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 24
540 /* The mask used to set the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
541 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x00ffffff
542 /* The mask used to clear the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
543 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xff000000
544 /* The reset value of the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
545 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0
546 /* Extracts the ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
547 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x00ffffff) >> 0)
548 /* Produces a ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
549 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x00ffffff)
550 
551 #ifndef __ASSEMBLY__
552 /*
553  * WARNING: The C register and register group struct declarations are provided for
554  * convenience and illustrative purposes. They should, however, be used with
555  * caution as the C language standard provides no guarantees about the alignment or
556  * atomicity of device memory accesses. The recommended practice for coding device
557  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
558  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
559  * alt_write_dword() functions for 64 bit registers.
560  *
561  * The struct declaration for register ALT_GPIO_GPIO_INTTYPE_LEVEL.
562  */
563 struct ALT_GPIO_GPIO_INTTYPE_LEVEL_s
564 {
565  volatile uint32_t GPIO_INTTYPE_LEVEL : 24; /* ALT_GPIO_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL */
566  uint32_t : 8; /* *UNDEFINED* */
567 };
568 
569 /* The typedef declaration for register ALT_GPIO_GPIO_INTTYPE_LEVEL. */
570 typedef struct ALT_GPIO_GPIO_INTTYPE_LEVEL_s ALT_GPIO_GPIO_INTTYPE_LEVEL_t;
571 #endif /* __ASSEMBLY__ */
572 
573 /* The reset value of the ALT_GPIO_GPIO_INTTYPE_LEVEL register. */
574 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_RESET 0x00000000
575 /* The byte offset of the ALT_GPIO_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
576 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_OFST 0x38
577 /* The address of the ALT_GPIO_GPIO_INTTYPE_LEVEL register. */
578 #define ALT_GPIO_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_INTTYPE_LEVEL_OFST))
579 
580 /*
581  * Register : Interrupt polarity - GPIO_INT_POLARITY
582  *
583  * Name: Interrupt polarity
584  *
585  * Size: 1-32 bits
586  *
587  * Address Offset: 0x3c
588  *
589  * Read/Write Access: Read/Write
590  *
591  * Register Layout
592  *
593  * Bits | Access | Reset | Description
594  * :--------|:-------|:------|:---------------------------------------------
595  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY
596  * [31:24] | ??? | 0x0 | *UNDEFINED*
597  *
598  */
599 /*
600  * Field : GPIO_INT_POLARITY
601  *
602  * Controls the polarity of edge or level sensitivity that can
603  *
604  * occur on input of Port A. Whenever a 0 is written to a bit of
605  *
606  * this register, it configures the interrupt type to falling-edge or
607  *
608  * active-low sensitive; otherwise, it is rising-edge or
609  *
610  * active-high sensitive.
611  *
612  * 0 Active-low (default)
613  *
614  * 1 Active-high
615  *
616  * DO NOT PUBLISH BELOW THIS LINE
617  *
618  * For internal usage only, [0:18] for SDM, [0:23] for HPS
619  *
620  * Field Enumeration Values:
621  *
622  * Enum | Value | Description
623  * :-----------------------------------------------------------|:------|:---------------------
624  * ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_E_ACTIVE_LOW | 0x0 | Active Low polarity
625  * ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_E_ACTIVE_HIGH | 0x1 | Active High polarity
626  *
627  * Field Access Macros:
628  *
629  */
630 /*
631  * Enumerated value for register field ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY
632  *
633  * Active Low polarity
634  */
635 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_E_ACTIVE_LOW 0x0
636 /*
637  * Enumerated value for register field ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY
638  *
639  * Active High polarity
640  */
641 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_E_ACTIVE_HIGH 0x1
642 
643 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field. */
644 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_LSB 0
645 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field. */
646 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_MSB 23
647 /* The width in bits of the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field. */
648 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_WIDTH 24
649 /* The mask used to set the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field value. */
650 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_SET_MSK 0x00ffffff
651 /* The mask used to clear the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field value. */
652 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_CLR_MSK 0xff000000
653 /* The reset value of the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field. */
654 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_RESET 0x0
655 /* Extracts the ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY field value from a register. */
656 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_GET(value) (((value) & 0x00ffffff) >> 0)
657 /* Produces a ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY register field value suitable for setting the register. */
658 #define ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY_SET(value) (((value) << 0) & 0x00ffffff)
659 
660 #ifndef __ASSEMBLY__
661 /*
662  * WARNING: The C register and register group struct declarations are provided for
663  * convenience and illustrative purposes. They should, however, be used with
664  * caution as the C language standard provides no guarantees about the alignment or
665  * atomicity of device memory accesses. The recommended practice for coding device
666  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
667  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
668  * alt_write_dword() functions for 64 bit registers.
669  *
670  * The struct declaration for register ALT_GPIO_GPIO_INT_POLARITY.
671  */
672 struct ALT_GPIO_GPIO_INT_POLARITY_s
673 {
674  volatile uint32_t GPIO_INT_POLARITY : 24; /* ALT_GPIO_GPIO_INT_POLARITY_GPIO_INT_POLARITY */
675  uint32_t : 8; /* *UNDEFINED* */
676 };
677 
678 /* The typedef declaration for register ALT_GPIO_GPIO_INT_POLARITY. */
679 typedef struct ALT_GPIO_GPIO_INT_POLARITY_s ALT_GPIO_GPIO_INT_POLARITY_t;
680 #endif /* __ASSEMBLY__ */
681 
682 /* The reset value of the ALT_GPIO_GPIO_INT_POLARITY register. */
683 #define ALT_GPIO_GPIO_INT_POLARITY_RESET 0x00000000
684 /* The byte offset of the ALT_GPIO_GPIO_INT_POLARITY register from the beginning of the component. */
685 #define ALT_GPIO_GPIO_INT_POLARITY_OFST 0x3c
686 /* The address of the ALT_GPIO_GPIO_INT_POLARITY register. */
687 #define ALT_GPIO_GPIO_INT_POLARITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_INT_POLARITY_OFST))
688 
689 /*
690  * Register : Interrupt status - GPIO_INTSTATUS
691  *
692  * Name: Interrupt status
693  *
694  * Size: 1-32 bits
695  *
696  * Address Offset: 0x40
697  *
698  * Read/Write Access: Read
699  *
700  * Register Layout
701  *
702  * Bits | Access | Reset | Description
703  * :--------|:-------|:------|:---------------------------------------
704  * [23:0] | R | 0x0 | ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS
705  * [31:24] | ??? | 0x0 | *UNDEFINED*
706  *
707  */
708 /*
709  * Field : GPIO_INTSTATUS
710  *
711  * Interrupt status of Port A.
712  *
713  * DO NOT PUBLISH BELOW THIS LINE
714  *
715  * For internal usage only, [0:18] for SDM, [0:23] for HPS
716  *
717  * Field Enumeration Values:
718  *
719  * Enum | Value | Description
720  * :--------------------------------------------------|:------|:------------
721  * ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_E_INACTIVE | 0x0 | Inactive
722  * ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_E_ACTIVE | 0x1 | Active
723  *
724  * Field Access Macros:
725  *
726  */
727 /*
728  * Enumerated value for register field ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS
729  *
730  * Inactive
731  */
732 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_E_INACTIVE 0x0
733 /*
734  * Enumerated value for register field ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS
735  *
736  * Active
737  */
738 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_E_ACTIVE 0x1
739 
740 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field. */
741 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_LSB 0
742 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field. */
743 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_MSB 23
744 /* The width in bits of the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field. */
745 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_WIDTH 24
746 /* The mask used to set the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field value. */
747 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_SET_MSK 0x00ffffff
748 /* The mask used to clear the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field value. */
749 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_CLR_MSK 0xff000000
750 /* The reset value of the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field. */
751 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_RESET 0x0
752 /* Extracts the ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS field value from a register. */
753 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_GET(value) (((value) & 0x00ffffff) >> 0)
754 /* Produces a ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS register field value suitable for setting the register. */
755 #define ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS_SET(value) (((value) << 0) & 0x00ffffff)
756 
757 #ifndef __ASSEMBLY__
758 /*
759  * WARNING: The C register and register group struct declarations are provided for
760  * convenience and illustrative purposes. They should, however, be used with
761  * caution as the C language standard provides no guarantees about the alignment or
762  * atomicity of device memory accesses. The recommended practice for coding device
763  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
764  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
765  * alt_write_dword() functions for 64 bit registers.
766  *
767  * The struct declaration for register ALT_GPIO_GPIO_INTSTATUS.
768  */
769 struct ALT_GPIO_GPIO_INTSTATUS_s
770 {
771  const volatile uint32_t GPIO_INTSTATUS : 24; /* ALT_GPIO_GPIO_INTSTATUS_GPIO_INTSTATUS */
772  uint32_t : 8; /* *UNDEFINED* */
773 };
774 
775 /* The typedef declaration for register ALT_GPIO_GPIO_INTSTATUS. */
776 typedef struct ALT_GPIO_GPIO_INTSTATUS_s ALT_GPIO_GPIO_INTSTATUS_t;
777 #endif /* __ASSEMBLY__ */
778 
779 /* The reset value of the ALT_GPIO_GPIO_INTSTATUS register. */
780 #define ALT_GPIO_GPIO_INTSTATUS_RESET 0x00000000
781 /* The byte offset of the ALT_GPIO_GPIO_INTSTATUS register from the beginning of the component. */
782 #define ALT_GPIO_GPIO_INTSTATUS_OFST 0x40
783 /* The address of the ALT_GPIO_GPIO_INTSTATUS register. */
784 #define ALT_GPIO_GPIO_INTSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_INTSTATUS_OFST))
785 
786 /*
787  * Register : Raw interrupt status - GPIO_RAW_INTSTATUS
788  *
789  * Name: Raw interrupt status
790  *
791  * Size: 1-32 bits
792  *
793  * Address Offset: 0x44
794  *
795  * Read/Write Access: Read
796  *
797  * Register Layout
798  *
799  * Bits | Access | Reset | Description
800  * :--------|:-------|:------|:-----------------------------------------------
801  * [23:0] | R | 0x0 | ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS
802  * [31:24] | ??? | 0x0 | *UNDEFINED*
803  *
804  */
805 /*
806  * Field : GPIO_RAW_INTSTATUS
807  *
808  * Raw interrupt of status of Port A (premasking bits)
809  *
810  * DO NOT PUBLISH BELOW THIS LINE
811  *
812  * For internal usage only, [0:18] for SDM, [0:23] for HPS
813  *
814  * Field Enumeration Values:
815  *
816  * Enum | Value | Description
817  * :----------------------------------------------------------|:------|:------------
818  * ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_E_INACTIVE | 0x0 | Inactive
819  * ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_E_ACTIVE | 0x1 | Active
820  *
821  * Field Access Macros:
822  *
823  */
824 /*
825  * Enumerated value for register field ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS
826  *
827  * Inactive
828  */
829 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_E_INACTIVE 0x0
830 /*
831  * Enumerated value for register field ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS
832  *
833  * Active
834  */
835 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_E_ACTIVE 0x1
836 
837 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field. */
838 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_LSB 0
839 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field. */
840 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_MSB 23
841 /* The width in bits of the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field. */
842 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_WIDTH 24
843 /* The mask used to set the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field value. */
844 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_SET_MSK 0x00ffffff
845 /* The mask used to clear the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field value. */
846 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_CLR_MSK 0xff000000
847 /* The reset value of the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field. */
848 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_RESET 0x0
849 /* Extracts the ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS field value from a register. */
850 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_GET(value) (((value) & 0x00ffffff) >> 0)
851 /* Produces a ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS register field value suitable for setting the register. */
852 #define ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS_SET(value) (((value) << 0) & 0x00ffffff)
853 
854 #ifndef __ASSEMBLY__
855 /*
856  * WARNING: The C register and register group struct declarations are provided for
857  * convenience and illustrative purposes. They should, however, be used with
858  * caution as the C language standard provides no guarantees about the alignment or
859  * atomicity of device memory accesses. The recommended practice for coding device
860  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
861  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
862  * alt_write_dword() functions for 64 bit registers.
863  *
864  * The struct declaration for register ALT_GPIO_GPIO_RAW_INTSTATUS.
865  */
866 struct ALT_GPIO_GPIO_RAW_INTSTATUS_s
867 {
868  const volatile uint32_t GPIO_RAW_INTSTATUS : 24; /* ALT_GPIO_GPIO_RAW_INTSTATUS_GPIO_RAW_INTSTATUS */
869  uint32_t : 8; /* *UNDEFINED* */
870 };
871 
872 /* The typedef declaration for register ALT_GPIO_GPIO_RAW_INTSTATUS. */
873 typedef struct ALT_GPIO_GPIO_RAW_INTSTATUS_s ALT_GPIO_GPIO_RAW_INTSTATUS_t;
874 #endif /* __ASSEMBLY__ */
875 
876 /* The reset value of the ALT_GPIO_GPIO_RAW_INTSTATUS register. */
877 #define ALT_GPIO_GPIO_RAW_INTSTATUS_RESET 0x00000000
878 /* The byte offset of the ALT_GPIO_GPIO_RAW_INTSTATUS register from the beginning of the component. */
879 #define ALT_GPIO_GPIO_RAW_INTSTATUS_OFST 0x44
880 /* The address of the ALT_GPIO_GPIO_RAW_INTSTATUS register. */
881 #define ALT_GPIO_GPIO_RAW_INTSTATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_RAW_INTSTATUS_OFST))
882 
883 /*
884  * Register : Debounce enable - GPIO_DEBOUNCE
885  *
886  * Name: Debounce enable
887  *
888  * Size: 1-32 bits
889  *
890  * Address Offset: 0x48
891  *
892  * Read/Write Access: Read/Write
893  *
894  * Register Layout
895  *
896  * Bits | Access | Reset | Description
897  * :--------|:-------|:------|:-------------------------------------
898  * [23:0] | RW | 0x0 | ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE
899  * [31:24] | ??? | 0x0 | *UNDEFINED*
900  *
901  */
902 /*
903  * Field : GPIO_DEBOUNCE
904  *
905  * Controls whether an external signal that is the source
906  *
907  * of an interrupt needs to be debounced to remove any
908  *
909  * spurious glitches. Writing a 1 to a bit in this register
910  *
911  * enables the debouncing circuitry. A signal must be
912  *
913  * valid for two periods of an external clock before it is
914  *
915  * internally processed.
916  *
917  * 0 No debounce (default)
918  *
919  * 1 Enable debounce
920  *
921  * DO NOT PUBLISH BELOW THIS LINE
922  *
923  * For internal usage only, [0:18] for SDM, [0:23] for HPS
924  *
925  * Field Enumeration Values:
926  *
927  * Enum | Value | Description
928  * :------------------------------------------------|:------|:----------------
929  * ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DISABLED | 0x0 | No debounce
930  * ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_ENABLED | 0x1 | Enable debounce
931  *
932  * Field Access Macros:
933  *
934  */
935 /*
936  * Enumerated value for register field ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE
937  *
938  * No debounce
939  */
940 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DISABLED 0x0
941 /*
942  * Enumerated value for register field ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE
943  *
944  * Enable debounce
945  */
946 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_ENABLED 0x1
947 
948 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
949 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0
950 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
951 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 23
952 /* The width in bits of the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
953 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 24
954 /* The mask used to set the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
955 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x00ffffff
956 /* The mask used to clear the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
957 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xff000000
958 /* The reset value of the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
959 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0
960 /* Extracts the ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
961 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x00ffffff) >> 0)
962 /* Produces a ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
963 #define ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x00ffffff)
964 
965 #ifndef __ASSEMBLY__
966 /*
967  * WARNING: The C register and register group struct declarations are provided for
968  * convenience and illustrative purposes. They should, however, be used with
969  * caution as the C language standard provides no guarantees about the alignment or
970  * atomicity of device memory accesses. The recommended practice for coding device
971  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
972  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
973  * alt_write_dword() functions for 64 bit registers.
974  *
975  * The struct declaration for register ALT_GPIO_GPIO_DEBOUNCE.
976  */
977 struct ALT_GPIO_GPIO_DEBOUNCE_s
978 {
979  volatile uint32_t GPIO_DEBOUNCE : 24; /* ALT_GPIO_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
980  uint32_t : 8; /* *UNDEFINED* */
981 };
982 
983 /* The typedef declaration for register ALT_GPIO_GPIO_DEBOUNCE. */
984 typedef struct ALT_GPIO_GPIO_DEBOUNCE_s ALT_GPIO_GPIO_DEBOUNCE_t;
985 #endif /* __ASSEMBLY__ */
986 
987 /* The reset value of the ALT_GPIO_GPIO_DEBOUNCE register. */
988 #define ALT_GPIO_GPIO_DEBOUNCE_RESET 0x00000000
989 /* The byte offset of the ALT_GPIO_GPIO_DEBOUNCE register from the beginning of the component. */
990 #define ALT_GPIO_GPIO_DEBOUNCE_OFST 0x48
991 /* The address of the ALT_GPIO_GPIO_DEBOUNCE register. */
992 #define ALT_GPIO_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_DEBOUNCE_OFST))
993 
994 /*
995  * Register : Port A clear interrupt register - GPIO_PORTA_EOI
996  *
997  * Name: Port A clear interrupt register
998  *
999  * Size: 1-32 bits
1000  *
1001  * Address Offset: 0x4c
1002  *
1003  * Read/Write Access: Write
1004  *
1005  * Register Layout
1006  *
1007  * Bits | Access | Reset | Description
1008  * :--------|:-------|:------|:---------------------------------------
1009  * [23:0] | W | 0x0 | ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI
1010  * [31:24] | ??? | 0x0 | *UNDEFINED*
1011  *
1012  */
1013 /*
1014  * Field : GPIO_PORTA_EOI
1015  *
1016  * Controls the clearing of edge type interrupts from Port A.
1017  *
1018  * When a 1 is written into a corresponding bit of this register,
1019  *
1020  * the interrupt is cleared. All interrupts are cleared when
1021  *
1022  * Port A is not configured for interrupts.
1023  *
1024  * 0 No interrupt clear (default)
1025  *
1026  * 1 Clear interrupt
1027  *
1028  * DO NOT PUBLISH BELOW THIS LINE
1029  *
1030  * For internal usage only, [0:18] for SDM, [0:23] for HPS
1031  *
1032  * Field Enumeration Values:
1033  *
1034  * Enum | Value | Description
1035  * :--------------------------------------------------|:------|:-------------------
1036  * ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_DISABLED | 0x0 | No interrupt clear
1037  * ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_ENABLED | 0x1 | Clear Interrupt
1038  *
1039  * Field Access Macros:
1040  *
1041  */
1042 /*
1043  * Enumerated value for register field ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI
1044  *
1045  * No interrupt clear
1046  */
1047 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_DISABLED 0x0
1048 /*
1049  * Enumerated value for register field ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI
1050  *
1051  * Clear Interrupt
1052  */
1053 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_ENABLED 0x1
1054 
1055 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1056 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0
1057 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1058 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 23
1059 /* The width in bits of the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1060 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 24
1061 /* The mask used to set the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
1062 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x00ffffff
1063 /* The mask used to clear the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
1064 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xff000000
1065 /* The reset value of the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
1066 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0
1067 /* Extracts the ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
1068 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x00ffffff) >> 0)
1069 /* Produces a ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
1070 #define ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x00ffffff)
1071 
1072 #ifndef __ASSEMBLY__
1073 /*
1074  * WARNING: The C register and register group struct declarations are provided for
1075  * convenience and illustrative purposes. They should, however, be used with
1076  * caution as the C language standard provides no guarantees about the alignment or
1077  * atomicity of device memory accesses. The recommended practice for coding device
1078  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1079  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1080  * alt_write_dword() functions for 64 bit registers.
1081  *
1082  * The struct declaration for register ALT_GPIO_GPIO_PORTA_EOI.
1083  */
1084 struct ALT_GPIO_GPIO_PORTA_EOI_s
1085 {
1086  volatile uint32_t GPIO_PORTA_EOI : 24; /* ALT_GPIO_GPIO_PORTA_EOI_GPIO_PORTA_EOI */
1087  uint32_t : 8; /* *UNDEFINED* */
1088 };
1089 
1090 /* The typedef declaration for register ALT_GPIO_GPIO_PORTA_EOI. */
1091 typedef struct ALT_GPIO_GPIO_PORTA_EOI_s ALT_GPIO_GPIO_PORTA_EOI_t;
1092 #endif /* __ASSEMBLY__ */
1093 
1094 /* The reset value of the ALT_GPIO_GPIO_PORTA_EOI register. */
1095 #define ALT_GPIO_GPIO_PORTA_EOI_RESET 0x00000000
1096 /* The byte offset of the ALT_GPIO_GPIO_PORTA_EOI register from the beginning of the component. */
1097 #define ALT_GPIO_GPIO_PORTA_EOI_OFST 0x4c
1098 /* The address of the ALT_GPIO_GPIO_PORTA_EOI register. */
1099 #define ALT_GPIO_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_PORTA_EOI_OFST))
1100 
1101 /*
1102  * Register : Port A external port register - GPIO_EXT_PORTA
1103  *
1104  * Name: Port A external port register
1105  *
1106  * Size: 1-32 bits
1107  *
1108  * Address Offset: 0x50
1109  *
1110  * Read/Write Access: Read
1111  *
1112  * Register Layout
1113  *
1114  * Bits | Access | Reset | Description
1115  * :--------|:-------|:------|:---------------------------------------
1116  * [23:0] | R | 0x0 | ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA
1117  * [31:24] | ??? | 0x0 | *UNDEFINED*
1118  *
1119  */
1120 /*
1121  * Field : GPIO_EXT_PORTA
1122  *
1123  * This register always reflects the signals value on the External Port A.
1124  *
1125  * DO NOT PUBLISH BELOW THIS LINE
1126  *
1127  * For internal usage only, [0:18] for SDM, [0:23] for HPS
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1133 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0
1134 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1135 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 23
1136 /* The width in bits of the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1137 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 24
1138 /* The mask used to set the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
1139 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x00ffffff
1140 /* The mask used to clear the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
1141 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xff000000
1142 /* The reset value of the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
1143 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0
1144 /* Extracts the ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
1145 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x00ffffff) >> 0)
1146 /* Produces a ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
1147 #define ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x00ffffff)
1148 
1149 #ifndef __ASSEMBLY__
1150 /*
1151  * WARNING: The C register and register group struct declarations are provided for
1152  * convenience and illustrative purposes. They should, however, be used with
1153  * caution as the C language standard provides no guarantees about the alignment or
1154  * atomicity of device memory accesses. The recommended practice for coding device
1155  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1156  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1157  * alt_write_dword() functions for 64 bit registers.
1158  *
1159  * The struct declaration for register ALT_GPIO_GPIO_EXT_PORTA.
1160  */
1161 struct ALT_GPIO_GPIO_EXT_PORTA_s
1162 {
1163  const volatile uint32_t GPIO_EXT_PORTA : 24; /* ALT_GPIO_GPIO_EXT_PORTA_GPIO_EXT_PORTA */
1164  uint32_t : 8; /* *UNDEFINED* */
1165 };
1166 
1167 /* The typedef declaration for register ALT_GPIO_GPIO_EXT_PORTA. */
1168 typedef struct ALT_GPIO_GPIO_EXT_PORTA_s ALT_GPIO_GPIO_EXT_PORTA_t;
1169 #endif /* __ASSEMBLY__ */
1170 
1171 /* The reset value of the ALT_GPIO_GPIO_EXT_PORTA register. */
1172 #define ALT_GPIO_GPIO_EXT_PORTA_RESET 0x00000000
1173 /* The byte offset of the ALT_GPIO_GPIO_EXT_PORTA register from the beginning of the component. */
1174 #define ALT_GPIO_GPIO_EXT_PORTA_OFST 0x50
1175 /* The address of the ALT_GPIO_GPIO_EXT_PORTA register. */
1176 #define ALT_GPIO_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_EXT_PORTA_OFST))
1177 
1178 /*
1179  * Register : Synchronization level - GPIO_LS_SYNC
1180  *
1181  * Name: Synchronization level
1182  *
1183  * Size: 1 bit
1184  *
1185  * Address Offset: 0x60
1186  *
1187  * Read/Write Access: Read/Write
1188  *
1189  * Register Layout
1190  *
1191  * Bits | Access | Reset | Description
1192  * :-------|:-------|:------|:-----------------------------------
1193  * [0] | RW | 0x0 | ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC
1194  * [31:1] | ??? | 0x0 | *UNDEFINED*
1195  *
1196  */
1197 /*
1198  * Field : GPIO_LS_SYNC
1199  *
1200  * Writing a 1 to this register results in all level-sensitive interrupts being
1201  *
1202  * synchronized to pclk_intr.
1203  *
1204  * 0 No synchronization to pclk_intr (default)
1205  *
1206  * 1 Synchronize to pclk_intr
1207  *
1208  * Field Enumeration Values:
1209  *
1210  * Enum | Value | Description
1211  * :----------------------------------------------|:------|:--------------------------------
1212  * ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_E_DISABLED | 0x0 | No synchronization to pclk_intr
1213  * ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_E_ENABLED | 0x1 | Synchronize to pclk_intr
1214  *
1215  * Field Access Macros:
1216  *
1217  */
1218 /*
1219  * Enumerated value for register field ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC
1220  *
1221  * No synchronization to pclk_intr
1222  */
1223 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_E_DISABLED 0x0
1224 /*
1225  * Enumerated value for register field ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC
1226  *
1227  * Synchronize to pclk_intr
1228  */
1229 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_E_ENABLED 0x1
1230 
1231 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1232 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
1233 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1234 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
1235 /* The width in bits of the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1236 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
1237 /* The mask used to set the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1238 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
1239 /* The mask used to clear the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1240 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
1241 /* The reset value of the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1242 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
1243 /* Extracts the ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
1244 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
1245 /* Produces a ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
1246 #define ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
1247 
1248 #ifndef __ASSEMBLY__
1249 /*
1250  * WARNING: The C register and register group struct declarations are provided for
1251  * convenience and illustrative purposes. They should, however, be used with
1252  * caution as the C language standard provides no guarantees about the alignment or
1253  * atomicity of device memory accesses. The recommended practice for coding device
1254  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1255  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1256  * alt_write_dword() functions for 64 bit registers.
1257  *
1258  * The struct declaration for register ALT_GPIO_GPIO_LS_SYNC.
1259  */
1260 struct ALT_GPIO_GPIO_LS_SYNC_s
1261 {
1262  volatile uint32_t GPIO_LS_SYNC : 1; /* ALT_GPIO_GPIO_LS_SYNC_GPIO_LS_SYNC */
1263  uint32_t : 31; /* *UNDEFINED* */
1264 };
1265 
1266 /* The typedef declaration for register ALT_GPIO_GPIO_LS_SYNC. */
1267 typedef struct ALT_GPIO_GPIO_LS_SYNC_s ALT_GPIO_GPIO_LS_SYNC_t;
1268 #endif /* __ASSEMBLY__ */
1269 
1270 /* The reset value of the ALT_GPIO_GPIO_LS_SYNC register. */
1271 #define ALT_GPIO_GPIO_LS_SYNC_RESET 0x00000000
1272 /* The byte offset of the ALT_GPIO_GPIO_LS_SYNC register from the beginning of the component. */
1273 #define ALT_GPIO_GPIO_LS_SYNC_OFST 0x60
1274 /* The address of the ALT_GPIO_GPIO_LS_SYNC register. */
1275 #define ALT_GPIO_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_LS_SYNC_OFST))
1276 
1277 /*
1278  * Register : GPIO ID code - GPIO_ID_CODE
1279  *
1280  * Name: GPIO ID code
1281  *
1282  * Size: 1-32 bits
1283  *
1284  * Address Offset: 0x64
1285  *
1286  * Read/Write Access: Read
1287  *
1288  * Register Layout
1289  *
1290  * Bits | Access | Reset | Description
1291  * :-------|:-------|:------|:-----------------------------------
1292  * [31:0] | R | 0x0 | ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE
1293  *
1294  */
1295 /*
1296  * Field : GPIO_ID_CODE
1297  *
1298  * This is a user-specified code that a system can read. It can
1299  *
1300  * be used for chip identification, and so on.
1301  *
1302  * Field Access Macros:
1303  *
1304  */
1305 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1306 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0
1307 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1308 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31
1309 /* The width in bits of the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1310 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32
1311 /* The mask used to set the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1312 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff
1313 /* The mask used to clear the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1314 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000
1315 /* The reset value of the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1316 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0
1317 /* Extracts the ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
1318 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1319 /* Produces a ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
1320 #define ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1321 
1322 #ifndef __ASSEMBLY__
1323 /*
1324  * WARNING: The C register and register group struct declarations are provided for
1325  * convenience and illustrative purposes. They should, however, be used with
1326  * caution as the C language standard provides no guarantees about the alignment or
1327  * atomicity of device memory accesses. The recommended practice for coding device
1328  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1329  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1330  * alt_write_dword() functions for 64 bit registers.
1331  *
1332  * The struct declaration for register ALT_GPIO_GPIO_ID_CODE.
1333  */
1334 struct ALT_GPIO_GPIO_ID_CODE_s
1335 {
1336  const volatile uint32_t GPIO_ID_CODE : 32; /* ALT_GPIO_GPIO_ID_CODE_GPIO_ID_CODE */
1337 };
1338 
1339 /* The typedef declaration for register ALT_GPIO_GPIO_ID_CODE. */
1340 typedef struct ALT_GPIO_GPIO_ID_CODE_s ALT_GPIO_GPIO_ID_CODE_t;
1341 #endif /* __ASSEMBLY__ */
1342 
1343 /* The reset value of the ALT_GPIO_GPIO_ID_CODE register. */
1344 #define ALT_GPIO_GPIO_ID_CODE_RESET 0x00000000
1345 /* The byte offset of the ALT_GPIO_GPIO_ID_CODE register from the beginning of the component. */
1346 #define ALT_GPIO_GPIO_ID_CODE_OFST 0x64
1347 /* The address of the ALT_GPIO_GPIO_ID_CODE register. */
1348 #define ALT_GPIO_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_ID_CODE_OFST))
1349 
1350 /*
1351  * Register : GPIO Component Version - GPIO_VER_ID_CODE
1352  *
1353  * Name: GPIO Component Version
1354  *
1355  * Size: 32 bits
1356  *
1357  * Address Offset: 0x6c
1358  *
1359  * Read/Write Access: Read
1360  *
1361  * Register Layout
1362  *
1363  * Bits | Access | Reset | Description
1364  * :-------|:-------|:-----------|:-------------------------------------------
1365  * [31:0] | R | 0x3231302a | ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE
1366  *
1367  */
1368 /*
1369  * Field : GPIO_VER_ID_CODE
1370  *
1371  * ASCII value for each number in the version.
1372  *
1373  * Field Access Macros:
1374  *
1375  */
1376 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1377 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
1378 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1379 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
1380 /* The width in bits of the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1381 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
1382 /* The mask used to set the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1383 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
1384 /* The mask used to clear the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1385 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
1386 /* The reset value of the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1387 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3231302a
1388 /* Extracts the ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
1389 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1390 /* Produces a ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
1391 #define ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1392 
1393 #ifndef __ASSEMBLY__
1394 /*
1395  * WARNING: The C register and register group struct declarations are provided for
1396  * convenience and illustrative purposes. They should, however, be used with
1397  * caution as the C language standard provides no guarantees about the alignment or
1398  * atomicity of device memory accesses. The recommended practice for coding device
1399  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1400  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1401  * alt_write_dword() functions for 64 bit registers.
1402  *
1403  * The struct declaration for register ALT_GPIO_GPIO_VER_ID_CODE.
1404  */
1405 struct ALT_GPIO_GPIO_VER_ID_CODE_s
1406 {
1407  const volatile uint32_t GPIO_VER_ID_CODE : 32; /* ALT_GPIO_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE */
1408 };
1409 
1410 /* The typedef declaration for register ALT_GPIO_GPIO_VER_ID_CODE. */
1411 typedef struct ALT_GPIO_GPIO_VER_ID_CODE_s ALT_GPIO_GPIO_VER_ID_CODE_t;
1412 #endif /* __ASSEMBLY__ */
1413 
1414 /* The reset value of the ALT_GPIO_GPIO_VER_ID_CODE register. */
1415 #define ALT_GPIO_GPIO_VER_ID_CODE_RESET 0x3231302a
1416 /* The byte offset of the ALT_GPIO_GPIO_VER_ID_CODE register from the beginning of the component. */
1417 #define ALT_GPIO_GPIO_VER_ID_CODE_OFST 0x6c
1418 /* The address of the ALT_GPIO_GPIO_VER_ID_CODE register. */
1419 #define ALT_GPIO_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_VER_ID_CODE_OFST))
1420 
1421 /*
1422  * Register : GPIO Configuration Register 2 - GPIO_CONFIG_REG2
1423  *
1424  * Name: GPIO Configuration Register 2
1425  *
1426  * Size: 32 bits
1427  *
1428  * Address Offset: 0x70
1429  *
1430  * Read/Write Access: Read
1431  *
1432  * Register Layout
1433  *
1434  * Bits | Access | Reset | Description
1435  * :--------|:-------|:------|:----------------------------------------------
1436  * [4:0] | R | 0x17 | ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A
1437  * [9:5] | R | 0x7 | ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B
1438  * [14:10] | R | 0x7 | ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C
1439  * [19:15] | R | 0x7 | ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D
1440  * [31:20] | ??? | 0x0 | *UNDEFINED*
1441  *
1442  */
1443 /*
1444  * Field : ENCODED_ID_PWIDTH_A
1445  *
1446  * The value of this register is derived from the
1447  *
1448  * GPIO_PWIDTH_A configuration parameter.
1449  *
1450  * 0x0 = 8 bits
1451  *
1452  * 0x1 = 16 bits
1453  *
1454  * 0x2 = 32 bits
1455  *
1456  * 0x3 = Reserved
1457  *
1458  * Field Access Macros:
1459  *
1460  */
1461 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field. */
1462 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_LSB 0
1463 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field. */
1464 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_MSB 4
1465 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field. */
1466 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_WIDTH 5
1467 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field value. */
1468 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_SET_MSK 0x0000001f
1469 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field value. */
1470 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_CLR_MSK 0xffffffe0
1471 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field. */
1472 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_RESET 0x17
1473 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A field value from a register. */
1474 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
1475 /* Produces a ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A register field value suitable for setting the register. */
1476 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
1477 
1478 /*
1479  * Field : ENCODED_ID_PWIDTH_B
1480  *
1481  * The value of this register is derived from the
1482  *
1483  * GPIO_PWIDTH_B configuration parameter.
1484  *
1485  * 0x0 = 8 bits
1486  *
1487  * 0x1 = 16 bits
1488  *
1489  * 0x2 = 32 bits
1490  *
1491  * 0x3 = Reserved
1492  *
1493  * Field Access Macros:
1494  *
1495  */
1496 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field. */
1497 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_LSB 5
1498 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field. */
1499 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_MSB 9
1500 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field. */
1501 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_WIDTH 5
1502 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field value. */
1503 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_SET_MSK 0x000003e0
1504 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field value. */
1505 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
1506 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field. */
1507 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_RESET 0x7
1508 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B field value from a register. */
1509 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
1510 /* Produces a ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B register field value suitable for setting the register. */
1511 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
1512 
1513 /*
1514  * Field : ENCODED_ID_PWIDTH_C
1515  *
1516  * The value of this register is derived from the
1517  *
1518  * GPIO_PWIDTH_C configuration parameter.
1519  *
1520  * 0x0 = 8 bits
1521  *
1522  * 0x1 = 16 bits
1523  *
1524  * 0x2 = 32 bits
1525  *
1526  * 0x3 = Reserved
1527  *
1528  * Field Access Macros:
1529  *
1530  */
1531 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field. */
1532 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_LSB 10
1533 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field. */
1534 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_MSB 14
1535 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field. */
1536 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_WIDTH 5
1537 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field value. */
1538 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_SET_MSK 0x00007c00
1539 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field value. */
1540 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_CLR_MSK 0xffff83ff
1541 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field. */
1542 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_RESET 0x7
1543 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C field value from a register. */
1544 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
1545 /* Produces a ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C register field value suitable for setting the register. */
1546 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
1547 
1548 /*
1549  * Field : ENCODED_ID_PWIDTH_D
1550  *
1551  * The value of this register is derived from the
1552  *
1553  * GPIO_PWIDTH_D configuration parameter.
1554  *
1555  * 0x0 = 8 bits
1556  *
1557  * 0x1 = 16 bits
1558  *
1559  * 0x2 = 32 bits
1560  *
1561  * 0x3 = Reserved
1562  *
1563  * Field Access Macros:
1564  *
1565  */
1566 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field. */
1567 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_LSB 15
1568 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field. */
1569 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_MSB 19
1570 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field. */
1571 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_WIDTH 5
1572 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field value. */
1573 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_SET_MSK 0x000f8000
1574 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field value. */
1575 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_CLR_MSK 0xfff07fff
1576 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field. */
1577 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_RESET 0x7
1578 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D field value from a register. */
1579 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
1580 /* Produces a ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D register field value suitable for setting the register. */
1581 #define ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
1582 
1583 #ifndef __ASSEMBLY__
1584 /*
1585  * WARNING: The C register and register group struct declarations are provided for
1586  * convenience and illustrative purposes. They should, however, be used with
1587  * caution as the C language standard provides no guarantees about the alignment or
1588  * atomicity of device memory accesses. The recommended practice for coding device
1589  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1590  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1591  * alt_write_dword() functions for 64 bit registers.
1592  *
1593  * The struct declaration for register ALT_GPIO_GPIO_CONFIG_REG2.
1594  */
1595 struct ALT_GPIO_GPIO_CONFIG_REG2_s
1596 {
1597  const volatile uint32_t ENCODED_ID_PWIDTH_A : 5; /* ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_A */
1598  const volatile uint32_t ENCODED_ID_PWIDTH_B : 5; /* ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_B */
1599  const volatile uint32_t ENCODED_ID_PWIDTH_C : 5; /* ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_C */
1600  const volatile uint32_t ENCODED_ID_PWIDTH_D : 5; /* ALT_GPIO_GPIO_CONFIG_REG2_ENCODED_ID_PWIDTH_D */
1601  uint32_t : 12; /* *UNDEFINED* */
1602 };
1603 
1604 /* The typedef declaration for register ALT_GPIO_GPIO_CONFIG_REG2. */
1605 typedef struct ALT_GPIO_GPIO_CONFIG_REG2_s ALT_GPIO_GPIO_CONFIG_REG2_t;
1606 #endif /* __ASSEMBLY__ */
1607 
1608 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG2 register. */
1609 #define ALT_GPIO_GPIO_CONFIG_REG2_RESET 0x00039cf7
1610 /* The byte offset of the ALT_GPIO_GPIO_CONFIG_REG2 register from the beginning of the component. */
1611 #define ALT_GPIO_GPIO_CONFIG_REG2_OFST 0x70
1612 /* The address of the ALT_GPIO_GPIO_CONFIG_REG2 register. */
1613 #define ALT_GPIO_GPIO_CONFIG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_CONFIG_REG2_OFST))
1614 
1615 /*
1616  * Register : GPIO Configuration Register 1 - GPIO_CONFIG_REG1
1617  *
1618  * Name: GPIO Configuration Register 1
1619  *
1620  * Size: 32 bits
1621  *
1622  * Address Offset: 0x74
1623  *
1624  * Read/Write Access: Read
1625  *
1626  * Register Layout
1627  *
1628  * Bits | Access | Reset | Description
1629  * :--------|:-------|:------|:---------------------------------------------------
1630  * [1:0] | R | 0x2 | ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH
1631  * [3:2] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS
1632  * [4] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL
1633  * [5] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL
1634  * [6] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL
1635  * [7] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL
1636  * [8] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA
1637  * [9] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB
1638  * [10] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC
1639  * [11] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD
1640  * [12] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR
1641  * [13] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE
1642  * [14] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS
1643  * [15] | R | 0x1 | ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID
1644  * [20:16] | R | 0x1f | ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH
1645  * [21] | R | 0x0 | ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE
1646  * [31:22] | ??? | 0x0 | *UNDEFINED*
1647  *
1648  */
1649 /*
1650  * Field : APB_DATA_WIDTH
1651  *
1652  * The value of this register is derived from the
1653  *
1654  * GPIO_APB_DATA_WIDTH configuration parameter.
1655  *
1656  * 0x0 = 8 bits
1657  *
1658  * 0x1 = 16 bits
1659  *
1660  * 0x2 = 32 bits
1661  *
1662  * 0x3 = Reserved
1663  *
1664  * Field Enumeration Values:
1665  *
1666  * Enum | Value | Description
1667  * :------------------------------------------------------|:------|:--------------------------
1668  * ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_8BITS | 0x0 | APB DATA WIDTH is 8 bits
1669  * ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_16BITS | 0x1 | APB DATA WIDTH is 16 bits
1670  * ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_32BITS | 0x2 | APB DATA WIDTH is 32 bits
1671  *
1672  * Field Access Macros:
1673  *
1674  */
1675 /*
1676  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH
1677  *
1678  * APB DATA WIDTH is 8 bits
1679  */
1680 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_8BITS 0x0
1681 /*
1682  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH
1683  *
1684  * APB DATA WIDTH is 16 bits
1685  */
1686 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_16BITS 0x1
1687 /*
1688  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH
1689  *
1690  * APB DATA WIDTH is 32 bits
1691  */
1692 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_E_APB_32BITS 0x2
1693 
1694 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field. */
1695 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_LSB 0
1696 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field. */
1697 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_MSB 1
1698 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field. */
1699 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_WIDTH 2
1700 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field value. */
1701 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
1702 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field value. */
1703 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
1704 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field. */
1705 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_RESET 0x2
1706 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH field value from a register. */
1707 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
1708 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
1709 #define ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
1710 
1711 /*
1712  * Field : NUM_PORTS
1713  *
1714  * The value of this register is derived from the
1715  *
1716  * GPIO_NUM_PORT configuration parameter.
1717  *
1718  * 0x0 = 1
1719  *
1720  * 0x1 = 2
1721  *
1722  * 0x2 = 3
1723  *
1724  * 0x3 = 4
1725  *
1726  * Field Enumeration Values:
1727  *
1728  * Enum | Value | Description
1729  * :--------------------------------------------------|:------|:---------------------
1730  * ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_1 | 0x0 | Number of ports is 1
1731  * ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_2 | 0x1 | Number of ports is 2
1732  * ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_3 | 0x2 | Number of ports is 3
1733  * ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_4 | 0x3 | Number of ports is 4
1734  *
1735  * Field Access Macros:
1736  *
1737  */
1738 /*
1739  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS
1740  *
1741  * Number of ports is 1
1742  */
1743 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_1 0x0
1744 /*
1745  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS
1746  *
1747  * Number of ports is 2
1748  */
1749 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_2 0x1
1750 /*
1751  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS
1752  *
1753  * Number of ports is 3
1754  */
1755 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_3 0x2
1756 /*
1757  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS
1758  *
1759  * Number of ports is 4
1760  */
1761 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_E_NUM_PORTS_4 0x3
1762 
1763 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field. */
1764 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_LSB 2
1765 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field. */
1766 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_MSB 3
1767 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field. */
1768 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_WIDTH 2
1769 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field value. */
1770 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_SET_MSK 0x0000000c
1771 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field value. */
1772 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
1773 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field. */
1774 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_RESET 0x0
1775 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS field value from a register. */
1776 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
1777 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS register field value suitable for setting the register. */
1778 #define ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
1779 
1780 /*
1781  * Field : PORTA_SINGLE_CTL
1782  *
1783  * The value of this register is derived from the
1784  *
1785  * GPIO_PORTA_SINGLE_CTL configuration parameter.
1786  *
1787  * 0 = False
1788  *
1789  * 1 = True
1790  *
1791  * Field Enumeration Values:
1792  *
1793  * Enum | Value | Description
1794  * :------------------------------------------------------|:------|:---------------------------------------------
1795  * ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_E_DISABLED | 0x0 | PORTA is not controlled from a single source
1796  * ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_E_ENABLED | 0x1 | PORTA is controlled from a single source
1797  *
1798  * Field Access Macros:
1799  *
1800  */
1801 /*
1802  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL
1803  *
1804  * PORTA is not controlled from a single source
1805  */
1806 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_E_DISABLED 0x0
1807 /*
1808  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL
1809  *
1810  * PORTA is controlled from a single source
1811  */
1812 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_E_ENABLED 0x1
1813 
1814 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field. */
1815 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_LSB 4
1816 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field. */
1817 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_MSB 4
1818 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field. */
1819 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_WIDTH 1
1820 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field value. */
1821 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
1822 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field value. */
1823 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
1824 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field. */
1825 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_RESET 0x1
1826 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL field value from a register. */
1827 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
1828 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
1829 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
1830 
1831 /*
1832  * Field : PORTB_SINGLE_CTL
1833  *
1834  * The value of this register is derived from the
1835  *
1836  * GPIO_PORTB_SINGLE_CTL configuration parameter.
1837  *
1838  * 0 = False
1839  *
1840  * 1 = True
1841  *
1842  * Field Enumeration Values:
1843  *
1844  * Enum | Value | Description
1845  * :------------------------------------------------------|:------|:---------------------------------------------
1846  * ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_E_DISABLED | 0x0 | PORTB is not controlled from a single source
1847  * ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_E_ENABLED | 0x1 | PORTB is controlled from a single source
1848  *
1849  * Field Access Macros:
1850  *
1851  */
1852 /*
1853  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL
1854  *
1855  * PORTB is not controlled from a single source
1856  */
1857 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_E_DISABLED 0x0
1858 /*
1859  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL
1860  *
1861  * PORTB is controlled from a single source
1862  */
1863 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_E_ENABLED 0x1
1864 
1865 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field. */
1866 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_LSB 5
1867 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field. */
1868 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_MSB 5
1869 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field. */
1870 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_WIDTH 1
1871 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field value. */
1872 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
1873 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field value. */
1874 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
1875 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field. */
1876 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_RESET 0x1
1877 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL field value from a register. */
1878 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
1879 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
1880 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
1881 
1882 /*
1883  * Field : PORTC_SINGLE_CTL
1884  *
1885  * The value of this register is derived from the
1886  *
1887  * GPIO_PORTC_SINGLE_CTL configuration parameter.
1888  *
1889  * 0 = False
1890  *
1891  * 1 = True
1892  *
1893  * Field Enumeration Values:
1894  *
1895  * Enum | Value | Description
1896  * :------------------------------------------------------|:------|:---------------------------------------------
1897  * ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_E_DISABLED | 0x0 | PORTC is not controlled from a single source
1898  * ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_E_ENABLED | 0x1 | PORTC is controlled from a single source
1899  *
1900  * Field Access Macros:
1901  *
1902  */
1903 /*
1904  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL
1905  *
1906  * PORTC is not controlled from a single source
1907  */
1908 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_E_DISABLED 0x0
1909 /*
1910  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL
1911  *
1912  * PORTC is controlled from a single source
1913  */
1914 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_E_ENABLED 0x1
1915 
1916 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field. */
1917 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_LSB 6
1918 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field. */
1919 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_MSB 6
1920 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field. */
1921 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_WIDTH 1
1922 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field value. */
1923 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
1924 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field value. */
1925 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
1926 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field. */
1927 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_RESET 0x1
1928 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL field value from a register. */
1929 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
1930 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
1931 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
1932 
1933 /*
1934  * Field : PORTD_SINGLE_CTL
1935  *
1936  * The value of this register is derived from the
1937  *
1938  * GPIO_PORTD_SINGLE_CTL configuration parameter.
1939  *
1940  * 0 = False
1941  *
1942  * 1 = True
1943  *
1944  * Field Enumeration Values:
1945  *
1946  * Enum | Value | Description
1947  * :------------------------------------------------------|:------|:---------------------------------------------
1948  * ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_E_DISABLED | 0x0 | PORTD is not controlled from a single source
1949  * ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_E_ENABLED | 0x1 | PORTD is controlled from a single source
1950  *
1951  * Field Access Macros:
1952  *
1953  */
1954 /*
1955  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL
1956  *
1957  * PORTD is not controlled from a single source
1958  */
1959 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_E_DISABLED 0x0
1960 /*
1961  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL
1962  *
1963  * PORTD is controlled from a single source
1964  */
1965 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_E_ENABLED 0x1
1966 
1967 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field. */
1968 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_LSB 7
1969 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field. */
1970 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_MSB 7
1971 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field. */
1972 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_WIDTH 1
1973 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field value. */
1974 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
1975 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field value. */
1976 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
1977 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field. */
1978 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_RESET 0x1
1979 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL field value from a register. */
1980 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
1981 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
1982 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
1983 
1984 /*
1985  * Field : HW_PORTA
1986  *
1987  * The value of this register is derived from the
1988  *
1989  * GPIO_HW_PORTA configuration parameter.
1990  *
1991  * 0 = Exclude
1992  *
1993  * 1 = Include
1994  *
1995  * Field Enumeration Values:
1996  *
1997  * Enum | Value | Description
1998  * :----------------------------------------------|:------|:------------------------------------------------
1999  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_E_DISABLED | 0x0 | Port A has external, auxiliary hardware signals
2000  * : | | excluded
2001  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_E_ENABLED | 0x1 | Port A has external, auxiliary hardware signals
2002  * : | | included
2003  *
2004  * Field Access Macros:
2005  *
2006  */
2007 /*
2008  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA
2009  *
2010  * Port A has external, auxiliary hardware signals
2011  *
2012  * excluded
2013  */
2014 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_E_DISABLED 0x0
2015 /*
2016  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA
2017  *
2018  * Port A has external, auxiliary hardware signals
2019  *
2020  * included
2021  */
2022 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_E_ENABLED 0x1
2023 
2024 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field. */
2025 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_LSB 8
2026 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field. */
2027 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_MSB 8
2028 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field. */
2029 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_WIDTH 1
2030 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field value. */
2031 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_SET_MSK 0x00000100
2032 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field value. */
2033 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
2034 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field. */
2035 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_RESET 0x0
2036 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA field value from a register. */
2037 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
2038 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA register field value suitable for setting the register. */
2039 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
2040 
2041 /*
2042  * Field : HW_PORTB
2043  *
2044  * The value of this register is derived from the
2045  *
2046  * GPIO_HW_PORTB configuration parameter.
2047  *
2048  * 0 = Exclude
2049  *
2050  * 1 = Include
2051  *
2052  * Field Enumeration Values:
2053  *
2054  * Enum | Value | Description
2055  * :----------------------------------------------|:------|:------------------------------------------------
2056  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_E_DISABLED | 0x0 | Port B has external, auxiliary hardware signals
2057  * : | | excluded
2058  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_E_ENABLED | 0x1 | Port B has external, auxiliary hardware signals
2059  * : | | included
2060  *
2061  * Field Access Macros:
2062  *
2063  */
2064 /*
2065  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB
2066  *
2067  * Port B has external, auxiliary hardware signals
2068  *
2069  * excluded
2070  */
2071 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_E_DISABLED 0x0
2072 /*
2073  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB
2074  *
2075  * Port B has external, auxiliary hardware signals
2076  *
2077  * included
2078  */
2079 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_E_ENABLED 0x1
2080 
2081 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field. */
2082 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_LSB 9
2083 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field. */
2084 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_MSB 9
2085 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field. */
2086 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_WIDTH 1
2087 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field value. */
2088 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_SET_MSK 0x00000200
2089 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field value. */
2090 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_CLR_MSK 0xfffffdff
2091 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field. */
2092 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_RESET 0x0
2093 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB field value from a register. */
2094 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_GET(value) (((value) & 0x00000200) >> 9)
2095 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB register field value suitable for setting the register. */
2096 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB_SET(value) (((value) << 9) & 0x00000200)
2097 
2098 /*
2099  * Field : HW_PORTC
2100  *
2101  * The value of this register is derived from the
2102  *
2103  * GPIO_HW_PORTC configuration parameter.
2104  *
2105  * 0 = Exclude
2106  *
2107  * 1 = Include
2108  *
2109  * Field Enumeration Values:
2110  *
2111  * Enum | Value | Description
2112  * :----------------------------------------------|:------|:------------------------------------------------
2113  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_E_DISABLED | 0x0 | Port C has external, auxiliary hardware signals
2114  * : | | excluded
2115  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_E_ENABLED | 0x1 | Port C has external, auxiliary hardware signals
2116  * : | | included
2117  *
2118  * Field Access Macros:
2119  *
2120  */
2121 /*
2122  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC
2123  *
2124  * Port C has external, auxiliary hardware signals
2125  *
2126  * excluded
2127  */
2128 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_E_DISABLED 0x0
2129 /*
2130  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC
2131  *
2132  * Port C has external, auxiliary hardware signals
2133  *
2134  * included
2135  */
2136 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_E_ENABLED 0x1
2137 
2138 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field. */
2139 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_LSB 10
2140 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field. */
2141 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_MSB 10
2142 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field. */
2143 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_WIDTH 1
2144 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field value. */
2145 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_SET_MSK 0x00000400
2146 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field value. */
2147 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_CLR_MSK 0xfffffbff
2148 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field. */
2149 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_RESET 0x0
2150 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC field value from a register. */
2151 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_GET(value) (((value) & 0x00000400) >> 10)
2152 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC register field value suitable for setting the register. */
2153 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC_SET(value) (((value) << 10) & 0x00000400)
2154 
2155 /*
2156  * Field : HW_PORTD
2157  *
2158  * The value of this register is derived from the
2159  *
2160  * GPIO_HW_PORTD configuration parameter.
2161  *
2162  * 0 = Exclude
2163  *
2164  * 1 = Include
2165  *
2166  * Field Enumeration Values:
2167  *
2168  * Enum | Value | Description
2169  * :----------------------------------------------|:------|:------------------------------------------------
2170  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_E_DISABLED | 0x0 | Port D has external, auxiliary hardware signals
2171  * : | | excluded
2172  * ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_E_ENABLED | 0x1 | Port D has external, auxiliary hardware signals
2173  * : | | included
2174  *
2175  * Field Access Macros:
2176  *
2177  */
2178 /*
2179  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD
2180  *
2181  * Port D has external, auxiliary hardware signals
2182  *
2183  * excluded
2184  */
2185 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_E_DISABLED 0x0
2186 /*
2187  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD
2188  *
2189  * Port D has external, auxiliary hardware signals
2190  *
2191  * included
2192  */
2193 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_E_ENABLED 0x1
2194 
2195 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field. */
2196 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_LSB 11
2197 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field. */
2198 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_MSB 11
2199 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field. */
2200 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_WIDTH 1
2201 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field value. */
2202 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_SET_MSK 0x00000800
2203 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field value. */
2204 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_CLR_MSK 0xfffff7ff
2205 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field. */
2206 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_RESET 0x0
2207 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD field value from a register. */
2208 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_GET(value) (((value) & 0x00000800) >> 11)
2209 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD register field value suitable for setting the register. */
2210 #define ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD_SET(value) (((value) << 11) & 0x00000800)
2211 
2212 /*
2213  * Field : PORTA_INTR
2214  *
2215  * The value of this register is derived from the
2216  *
2217  * GPIO_PORTA_INTR configuration parameter.
2218  *
2219  * 0 = Exclude
2220  *
2221  * 1 = Include
2222  *
2223  * Field Enumeration Values:
2224  *
2225  * Enum | Value | Description
2226  * :------------------------------------------------|:------|:----------------------------------------------
2227  * ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_E_DISABLED | 0x0 | PORT A is not used as an interrupt source
2228  * ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_E_ENABLED | 0x1 | PORT A is required to be used as an interrupt
2229  * : | | source
2230  *
2231  * Field Access Macros:
2232  *
2233  */
2234 /*
2235  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR
2236  *
2237  * PORT A is not used as an interrupt source
2238  */
2239 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_E_DISABLED 0x0
2240 /*
2241  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR
2242  *
2243  * PORT A is required to be used as an interrupt
2244  *
2245  * source
2246  */
2247 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_E_ENABLED 0x1
2248 
2249 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field. */
2250 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_LSB 12
2251 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field. */
2252 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_MSB 12
2253 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field. */
2254 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_WIDTH 1
2255 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field value. */
2256 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_SET_MSK 0x00001000
2257 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field value. */
2258 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
2259 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field. */
2260 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_RESET 0x1
2261 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR field value from a register. */
2262 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
2263 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR register field value suitable for setting the register. */
2264 #define ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
2265 
2266 /*
2267  * Field : DEBOUNCE
2268  *
2269  * The value of this register is derived from the
2270  *
2271  * GPIO_DEBOUNCE configuration parameter.
2272  *
2273  * 0 = Exclude
2274  *
2275  * 1 = Include
2276  *
2277  * Field Enumeration Values:
2278  *
2279  * Enum | Value | Description
2280  * :----------------------------------------------|:------|:----------------------------
2281  * ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_E_DISABLED | 0x0 | Exclude debounce capability
2282  * ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_E_ENABLED | 0x1 | Include debounce capability
2283  *
2284  * Field Access Macros:
2285  *
2286  */
2287 /*
2288  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE
2289  *
2290  * Exclude debounce capability
2291  */
2292 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_E_DISABLED 0x0
2293 /*
2294  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE
2295  *
2296  * Include debounce capability
2297  */
2298 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_E_ENABLED 0x1
2299 
2300 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field. */
2301 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_LSB 13
2302 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field. */
2303 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_MSB 13
2304 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field. */
2305 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_WIDTH 1
2306 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field value. */
2307 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_SET_MSK 0x00002000
2308 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field value. */
2309 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
2310 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field. */
2311 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_RESET 0x1
2312 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE field value from a register. */
2313 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
2314 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE register field value suitable for setting the register. */
2315 #define ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
2316 
2317 /*
2318  * Field : ADD_ENCODED_PARAMS
2319  *
2320  * The value of this register is derived from the
2321  *
2322  * GPIO_ADD_ENCODED_PARAMS configuration parameter.
2323  *
2324  * 0 = False
2325  *
2326  * 1 = True
2327  *
2328  * Field Enumeration Values:
2329  *
2330  * Enum | Value | Description
2331  * :--------------------------------------------------------|:------|:-----------------------------
2332  * ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_E_DISABLED | 0x0 | Encoded parameters not added
2333  * ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_E_ENABLED | 0x1 | Encoded parameters added
2334  *
2335  * Field Access Macros:
2336  *
2337  */
2338 /*
2339  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS
2340  *
2341  * Encoded parameters not added
2342  */
2343 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_E_DISABLED 0x0
2344 /*
2345  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS
2346  *
2347  * Encoded parameters added
2348  */
2349 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_E_ENABLED 0x1
2350 
2351 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field. */
2352 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_LSB 14
2353 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field. */
2354 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_MSB 14
2355 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field. */
2356 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_WIDTH 1
2357 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field value. */
2358 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_SET_MSK 0x00004000
2359 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field value. */
2360 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_CLR_MSK 0xffffbfff
2361 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field. */
2362 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_RESET 0x1
2363 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS field value from a register. */
2364 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
2365 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS register field value suitable for setting the register. */
2366 #define ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS_SET(value) (((value) << 14) & 0x00004000)
2367 
2368 /*
2369  * Field : GPIO_ID
2370  *
2371  * The value of this register is derived from the
2372  *
2373  * GPIO_ID configuration parameter.
2374  *
2375  * 0 = Exclude
2376  *
2377  * 1 = Include
2378  *
2379  * Field Enumeration Values:
2380  *
2381  * Enum | Value | Description
2382  * :---------------------------------------------|:------|:---------------------
2383  * ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_E_DISABLED | 0x0 | GPIO_ID not included
2384  * ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_E_ENABLED | 0x1 | GPIO_ID is included
2385  *
2386  * Field Access Macros:
2387  *
2388  */
2389 /*
2390  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID
2391  *
2392  * GPIO_ID not included
2393  */
2394 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_E_DISABLED 0x0
2395 /*
2396  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID
2397  *
2398  * GPIO_ID is included
2399  */
2400 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_E_ENABLED 0x1
2401 
2402 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field. */
2403 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_LSB 15
2404 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field. */
2405 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_MSB 15
2406 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field. */
2407 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_WIDTH 1
2408 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field value. */
2409 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_SET_MSK 0x00008000
2410 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field value. */
2411 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
2412 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field. */
2413 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_RESET 0x1
2414 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID field value from a register. */
2415 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
2416 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID register field value suitable for setting the register. */
2417 #define ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
2418 
2419 /*
2420  * Field : ENCODED_ID_WIDTH
2421  *
2422  * The value of this register is derived from the
2423  *
2424  * GPIO_ID_WIDTH configuration parameter.
2425  *
2426  * Field Access Macros:
2427  *
2428  */
2429 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field. */
2430 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_LSB 16
2431 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field. */
2432 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_MSB 20
2433 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field. */
2434 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_WIDTH 5
2435 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field value. */
2436 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_SET_MSK 0x001f0000
2437 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field value. */
2438 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_CLR_MSK 0xffe0ffff
2439 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field. */
2440 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_RESET 0x1f
2441 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH field value from a register. */
2442 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
2443 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH register field value suitable for setting the register. */
2444 #define ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
2445 
2446 /*
2447  * Field : INTERRUPT_BOTH_EDGE_TYPE
2448  *
2449  * The value of this register is derived from the
2450  *
2451  * GPIO_INT_BOTH_EDGE configuration parameter
2452  *
2453  * Field Enumeration Values:
2454  *
2455  * Enum | Value | Description
2456  * :--------------------------------------------------------------|:------|:------------------------------------------------
2457  * ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_E_DISABLED | 0x0 | Interrupt generation on rising or falling edge
2458  * ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_E_ENABLED | 0x1 | Interrupt generation on both rising and falling
2459  * : | | edge
2460  *
2461  * Field Access Macros:
2462  *
2463  */
2464 /*
2465  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE
2466  *
2467  * Interrupt generation on rising or falling edge
2468  */
2469 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_E_DISABLED 0x0
2470 /*
2471  * Enumerated value for register field ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE
2472  *
2473  * Interrupt generation on both rising and falling edge
2474  */
2475 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_E_ENABLED 0x1
2476 
2477 /* The Least Significant Bit (LSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field. */
2478 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_LSB 21
2479 /* The Most Significant Bit (MSB) position of the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field. */
2480 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_MSB 21
2481 /* The width in bits of the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field. */
2482 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_WIDTH 1
2483 /* The mask used to set the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field value. */
2484 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_SET_MSK 0x00200000
2485 /* The mask used to clear the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field value. */
2486 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_CLR_MSK 0xffdfffff
2487 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field. */
2488 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_RESET 0x0
2489 /* Extracts the ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE field value from a register. */
2490 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_GET(value) (((value) & 0x00200000) >> 21)
2491 /* Produces a ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE register field value suitable for setting the register. */
2492 #define ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE_SET(value) (((value) << 21) & 0x00200000)
2493 
2494 #ifndef __ASSEMBLY__
2495 /*
2496  * WARNING: The C register and register group struct declarations are provided for
2497  * convenience and illustrative purposes. They should, however, be used with
2498  * caution as the C language standard provides no guarantees about the alignment or
2499  * atomicity of device memory accesses. The recommended practice for coding device
2500  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2501  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2502  * alt_write_dword() functions for 64 bit registers.
2503  *
2504  * The struct declaration for register ALT_GPIO_GPIO_CONFIG_REG1.
2505  */
2506 struct ALT_GPIO_GPIO_CONFIG_REG1_s
2507 {
2508  const volatile uint32_t APB_DATA_WIDTH : 2; /* ALT_GPIO_GPIO_CONFIG_REG1_APB_DATA_WIDTH */
2509  const volatile uint32_t NUM_PORTS : 2; /* ALT_GPIO_GPIO_CONFIG_REG1_NUM_PORTS */
2510  const volatile uint32_t PORTA_SINGLE_CTL : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_PORTA_SINGLE_CTL */
2511  const volatile uint32_t PORTB_SINGLE_CTL : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_PORTB_SINGLE_CTL */
2512  const volatile uint32_t PORTC_SINGLE_CTL : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_PORTC_SINGLE_CTL */
2513  const volatile uint32_t PORTD_SINGLE_CTL : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_PORTD_SINGLE_CTL */
2514  const volatile uint32_t HW_PORTA : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTA */
2515  const volatile uint32_t HW_PORTB : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTB */
2516  const volatile uint32_t HW_PORTC : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTC */
2517  const volatile uint32_t HW_PORTD : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_HW_PORTD */
2518  const volatile uint32_t PORTA_INTR : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_PORTA_INTR */
2519  const volatile uint32_t DEBOUNCE : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_DEBOUNCE */
2520  const volatile uint32_t ADD_ENCODED_PARAMS : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_ADD_ENCODED_PARAMS */
2521  const volatile uint32_t GPIO_ID : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_GPIO_ID */
2522  const volatile uint32_t ENCODED_ID_WIDTH : 5; /* ALT_GPIO_GPIO_CONFIG_REG1_ENCODED_ID_WIDTH */
2523  const volatile uint32_t INTERRUPT_BOTH_EDGE_TYPE : 1; /* ALT_GPIO_GPIO_CONFIG_REG1_INTERRUPT_BOTH_EDGE_TYPE */
2524  uint32_t : 10; /* *UNDEFINED* */
2525 };
2526 
2527 /* The typedef declaration for register ALT_GPIO_GPIO_CONFIG_REG1. */
2528 typedef struct ALT_GPIO_GPIO_CONFIG_REG1_s ALT_GPIO_GPIO_CONFIG_REG1_t;
2529 #endif /* __ASSEMBLY__ */
2530 
2531 /* The reset value of the ALT_GPIO_GPIO_CONFIG_REG1 register. */
2532 #define ALT_GPIO_GPIO_CONFIG_REG1_RESET 0x001ff0f2
2533 /* The byte offset of the ALT_GPIO_GPIO_CONFIG_REG1 register from the beginning of the component. */
2534 #define ALT_GPIO_GPIO_CONFIG_REG1_OFST 0x74
2535 /* The address of the ALT_GPIO_GPIO_CONFIG_REG1 register. */
2536 #define ALT_GPIO_GPIO_CONFIG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_GPIO_CONFIG_REG1_OFST))
2537 
2538 #ifndef __ASSEMBLY__
2539 /*
2540  * WARNING: The C register and register group struct declarations are provided for
2541  * convenience and illustrative purposes. They should, however, be used with
2542  * caution as the C language standard provides no guarantees about the alignment or
2543  * atomicity of device memory accesses. The recommended practice for coding device
2544  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2545  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2546  * alt_write_dword() functions for 64 bit registers.
2547  *
2548  * The struct declaration for register group ALT_GPIO.
2549  */
2550 struct ALT_GPIO_s
2551 {
2552  volatile ALT_GPIO_GPIO_SWPORTA_DR_t GPIO_SWPORTA_DR; /* ALT_GPIO_GPIO_SWPORTA_DR */
2553  volatile ALT_GPIO_GPIO_SWPORTA_DDR_t GPIO_SWPORTA_DDR; /* ALT_GPIO_GPIO_SWPORTA_DDR */
2554  volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
2555  volatile ALT_GPIO_GPIO_INTEN_t GPIO_INTEN; /* ALT_GPIO_GPIO_INTEN */
2556  volatile ALT_GPIO_GPIO_INTMASK_t GPIO_INTMASK; /* ALT_GPIO_GPIO_INTMASK */
2557  volatile ALT_GPIO_GPIO_INTTYPE_LEVEL_t GPIO_INTTYPE_LEVEL; /* ALT_GPIO_GPIO_INTTYPE_LEVEL */
2558  volatile ALT_GPIO_GPIO_INT_POLARITY_t GPIO_INT_POLARITY; /* ALT_GPIO_GPIO_INT_POLARITY */
2559  volatile ALT_GPIO_GPIO_INTSTATUS_t GPIO_INTSTATUS; /* ALT_GPIO_GPIO_INTSTATUS */
2560  volatile ALT_GPIO_GPIO_RAW_INTSTATUS_t GPIO_RAW_INTSTATUS; /* ALT_GPIO_GPIO_RAW_INTSTATUS */
2561  volatile ALT_GPIO_GPIO_DEBOUNCE_t GPIO_DEBOUNCE; /* ALT_GPIO_GPIO_DEBOUNCE */
2562  volatile ALT_GPIO_GPIO_PORTA_EOI_t GPIO_PORTA_EOI; /* ALT_GPIO_GPIO_PORTA_EOI */
2563  volatile ALT_GPIO_GPIO_EXT_PORTA_t GPIO_EXT_PORTA; /* ALT_GPIO_GPIO_EXT_PORTA */
2564  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
2565  volatile ALT_GPIO_GPIO_LS_SYNC_t GPIO_LS_SYNC; /* ALT_GPIO_GPIO_LS_SYNC */
2566  volatile ALT_GPIO_GPIO_ID_CODE_t GPIO_ID_CODE; /* ALT_GPIO_GPIO_ID_CODE */
2567  volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
2568  volatile ALT_GPIO_GPIO_VER_ID_CODE_t GPIO_VER_ID_CODE; /* ALT_GPIO_GPIO_VER_ID_CODE */
2569  volatile ALT_GPIO_GPIO_CONFIG_REG2_t GPIO_CONFIG_REG2; /* ALT_GPIO_GPIO_CONFIG_REG2 */
2570  volatile ALT_GPIO_GPIO_CONFIG_REG1_t GPIO_CONFIG_REG1; /* ALT_GPIO_GPIO_CONFIG_REG1 */
2571  volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
2572 };
2573 
2574 /* The typedef declaration for register group ALT_GPIO. */
2575 typedef struct ALT_GPIO_s ALT_GPIO_t;
2576 /* The struct declaration for the raw register contents of register group ALT_GPIO. */
2577 struct ALT_GPIO_raw_s
2578 {
2579  volatile uint32_t GPIO_SWPORTA_DR; /* ALT_GPIO_GPIO_SWPORTA_DR */
2580  volatile uint32_t GPIO_SWPORTA_DDR; /* ALT_GPIO_GPIO_SWPORTA_DDR */
2581  volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
2582  volatile uint32_t GPIO_INTEN; /* ALT_GPIO_GPIO_INTEN */
2583  volatile uint32_t GPIO_INTMASK; /* ALT_GPIO_GPIO_INTMASK */
2584  volatile uint32_t GPIO_INTTYPE_LEVEL; /* ALT_GPIO_GPIO_INTTYPE_LEVEL */
2585  volatile uint32_t GPIO_INT_POLARITY; /* ALT_GPIO_GPIO_INT_POLARITY */
2586  volatile uint32_t GPIO_INTSTATUS; /* ALT_GPIO_GPIO_INTSTATUS */
2587  volatile uint32_t GPIO_RAW_INTSTATUS; /* ALT_GPIO_GPIO_RAW_INTSTATUS */
2588  volatile uint32_t GPIO_DEBOUNCE; /* ALT_GPIO_GPIO_DEBOUNCE */
2589  volatile uint32_t GPIO_PORTA_EOI; /* ALT_GPIO_GPIO_PORTA_EOI */
2590  volatile uint32_t GPIO_EXT_PORTA; /* ALT_GPIO_GPIO_EXT_PORTA */
2591  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
2592  volatile uint32_t GPIO_LS_SYNC; /* ALT_GPIO_GPIO_LS_SYNC */
2593  volatile uint32_t GPIO_ID_CODE; /* ALT_GPIO_GPIO_ID_CODE */
2594  volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
2595  volatile uint32_t GPIO_VER_ID_CODE; /* ALT_GPIO_GPIO_VER_ID_CODE */
2596  volatile uint32_t GPIO_CONFIG_REG2; /* ALT_GPIO_GPIO_CONFIG_REG2 */
2597  volatile uint32_t GPIO_CONFIG_REG1; /* ALT_GPIO_GPIO_CONFIG_REG1 */
2598  volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
2599 };
2600 
2601 /* The typedef declaration for the raw register contents of register group ALT_GPIO. */
2602 typedef struct ALT_GPIO_raw_s ALT_GPIO_raw_t;
2603 #endif /* __ASSEMBLY__ */
2604 
2605 
2606 #ifdef __cplusplus
2607 }
2608 #endif /* __cplusplus */
2609 #endif /* __ALT_SOCAL_GPIO_H__ */
2610