Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_sysmgr.h
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32 
33 /* Altera - ALT_SYSMGR */
34 
35 #ifndef __ALT_SOCAL_SYSMGR_H__
36 #define __ALT_SOCAL_SYSMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_SYSMGR
50  *
51  */
52 /*
53  * Register : Silicon ID1 Register - siliconid1
54  *
55  * Specifies Silicon ID and revision number.
56  *
57  * This is a read only register and a write should return error.
58  *
59  * Register Layout
60  *
61  * Bits | Access | Reset | Description
62  * :--------|:-------|:------|:-----------------
63  * [15:0] | R | 0x1 | Silicon Revision
64  * [31:16] | R | 0x1 | Silicon ID
65  *
66  */
67 /*
68  * Field : Silicon Revision - rev
69  *
70  * Silicon revision number.
71  *
72  * Field Enumeration Values:
73  *
74  * Enum | Value | Description
75  * :---------------------------------|:------|:------------
76  * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x3 |
77  *
78  * Field Access Macros:
79  *
80  */
81 /*
82  * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV
83  *
84  */
85 #define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x3
86 
87 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
88 #define ALT_SYSMGR_SILICONID1_REV_LSB 0
89 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
90 #define ALT_SYSMGR_SILICONID1_REV_MSB 15
91 /* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */
92 #define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
93 /* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */
94 #define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
95 /* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */
96 #define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
97 /* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */
98 #define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
99 /* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */
100 #define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
101 /* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */
102 #define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
103 
104 /*
105  * Field : Silicon ID - id
106  *
107  * Silicon ID
108  *
109  * Field Enumeration Values:
110  *
111  * Enum | Value | Description
112  * :-------------------------------------|:------|:------------
113  * ALT_SYSMGR_SILICONID1_ID_E_NIGHTFURY | 0x3 |
114  *
115  * Field Access Macros:
116  *
117  */
118 /*
119  * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID
120  *
121  */
122 #define ALT_SYSMGR_SILICONID1_ID_E_NIGHTFURY 0x3
123 
124 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
125 #define ALT_SYSMGR_SILICONID1_ID_LSB 16
126 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
127 #define ALT_SYSMGR_SILICONID1_ID_MSB 31
128 /* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */
129 #define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
130 /* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */
131 #define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
132 /* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */
133 #define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
134 /* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */
135 #define ALT_SYSMGR_SILICONID1_ID_RESET 0x1
136 /* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */
137 #define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
138 /* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */
139 #define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
140 
141 #ifndef __ASSEMBLY__
142 /*
143  * WARNING: The C register and register group struct declarations are provided for
144  * convenience and illustrative purposes. They should, however, be used with
145  * caution as the C language standard provides no guarantees about the alignment or
146  * atomicity of device memory accesses. The recommended practice for writing
147  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
148  * alt_write_word() functions.
149  *
150  * The struct declaration for register ALT_SYSMGR_SILICONID1.
151  */
152 struct ALT_SYSMGR_SILICONID1_s
153 {
154  const uint32_t rev : 16; /* Silicon Revision */
155  const uint32_t id : 16; /* Silicon ID */
156 };
157 
158 /* The typedef declaration for register ALT_SYSMGR_SILICONID1. */
159 typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t;
160 #endif /* __ASSEMBLY__ */
161 
162 /* The reset value of the ALT_SYSMGR_SILICONID1 register. */
163 #define ALT_SYSMGR_SILICONID1_RESET 0x00010001
164 /* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */
165 #define ALT_SYSMGR_SILICONID1_OFST 0x0
166 
167 /*
168  * Register : Silicon ID2 Register - siliconid2
169  *
170  * Reserved for future use.
171  *
172  * This is a read only register and a write should return error.
173  *
174  * Register Layout
175  *
176  * Bits | Access | Reset | Description
177  * :-------|:-------|:------|:------------
178  * [31:0] | R | 0x0 | Reserved
179  *
180  */
181 /*
182  * Field : Reserved - rsv
183  *
184  * Reserved for future use.
185  *
186  * Field Access Macros:
187  *
188  */
189 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
190 #define ALT_SYSMGR_SILICONID2_RSV_LSB 0
191 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
192 #define ALT_SYSMGR_SILICONID2_RSV_MSB 31
193 /* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */
194 #define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
195 /* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */
196 #define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
197 /* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */
198 #define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
199 /* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */
200 #define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
201 /* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */
202 #define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
203 /* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */
204 #define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
205 
206 #ifndef __ASSEMBLY__
207 /*
208  * WARNING: The C register and register group struct declarations are provided for
209  * convenience and illustrative purposes. They should, however, be used with
210  * caution as the C language standard provides no guarantees about the alignment or
211  * atomicity of device memory accesses. The recommended practice for writing
212  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
213  * alt_write_word() functions.
214  *
215  * The struct declaration for register ALT_SYSMGR_SILICONID2.
216  */
217 struct ALT_SYSMGR_SILICONID2_s
218 {
219  const uint32_t rsv : 32; /* Reserved */
220 };
221 
222 /* The typedef declaration for register ALT_SYSMGR_SILICONID2. */
223 typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t;
224 #endif /* __ASSEMBLY__ */
225 
226 /* The reset value of the ALT_SYSMGR_SILICONID2 register. */
227 #define ALT_SYSMGR_SILICONID2_RESET 0x00000000
228 /* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */
229 #define ALT_SYSMGR_SILICONID2_OFST 0x4
230 
231 /*
232  * Register : L4 Watchdog Debug Register - wddbg
233  *
234  * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These
235  * control registers are used to drive the pause input signal of the L4 watchdogs.
236  * Note that the watchdogs built into the MPU automatically are paused when their
237  * associated CPU enters debug mode. Only reset by a cold reset.
238  *
239  * Register Layout
240  *
241  * Bits | Access | Reset | Description
242  * :-------|:-------|:------|:------------
243  * [1:0] | RW | 0x3 | Debug Mode
244  * [3:2] | RW | 0x3 | Debug Mode
245  * [31:4] | ??? | 0x0 | *UNDEFINED*
246  *
247  */
248 /*
249  * Field : Debug Mode - mode_0
250  *
251  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
252  * matches L4 watchdog index.
253  *
254  * Field Enumeration Values:
255  *
256  * Enum | Value | Description
257  * :-------------------------------------|:------|:------------
258  * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 |
259  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 |
260  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 |
261  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 |
262  *
263  * Field Access Macros:
264  *
265  */
266 /*
267  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
268  *
269  */
270 #define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
271 /*
272  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
273  *
274  */
275 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
276 /*
277  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
278  *
279  */
280 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
281 /*
282  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
283  *
284  */
285 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
286 
287 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
288 #define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
289 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
290 #define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
291 /* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
292 #define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
293 /* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
294 #define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
295 /* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
296 #define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
297 /* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
298 #define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
299 /* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */
300 #define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
301 /* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */
302 #define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
303 
304 /*
305  * Field : Debug Mode - mode_1
306  *
307  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
308  * matches L4 watchdog index.
309  *
310  * Field Enumeration Values:
311  *
312  * Enum | Value | Description
313  * :-------------------------------------|:------|:------------
314  * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 |
315  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 |
316  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 |
317  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 |
318  *
319  * Field Access Macros:
320  *
321  */
322 /*
323  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
324  *
325  */
326 #define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
327 /*
328  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
329  *
330  */
331 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
332 /*
333  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
334  *
335  */
336 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
337 /*
338  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
339  *
340  */
341 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
342 
343 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
344 #define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
345 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
346 #define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
347 /* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
348 #define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
349 /* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
350 #define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
351 /* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
352 #define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
353 /* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
354 #define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
355 /* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */
356 #define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
357 /* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */
358 #define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
359 
360 #ifndef __ASSEMBLY__
361 /*
362  * WARNING: The C register and register group struct declarations are provided for
363  * convenience and illustrative purposes. They should, however, be used with
364  * caution as the C language standard provides no guarantees about the alignment or
365  * atomicity of device memory accesses. The recommended practice for writing
366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
367  * alt_write_word() functions.
368  *
369  * The struct declaration for register ALT_SYSMGR_WDDBG.
370  */
371 struct ALT_SYSMGR_WDDBG_s
372 {
373  uint32_t mode_0 : 2; /* Debug Mode */
374  uint32_t mode_1 : 2; /* Debug Mode */
375  uint32_t : 28; /* *UNDEFINED* */
376 };
377 
378 /* The typedef declaration for register ALT_SYSMGR_WDDBG. */
379 typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
380 #endif /* __ASSEMBLY__ */
381 
382 /* The reset value of the ALT_SYSMGR_WDDBG register. */
383 #define ALT_SYSMGR_WDDBG_RESET 0x0000000f
384 /* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */
385 #define ALT_SYSMGR_WDDBG_OFST 0x8
386 
387 /*
388  * Register : Boot Info Register - bootinfo
389  *
390  * Provides access to boot configuration information.
391  *
392  * This is a read only register and a write should return error.
393  *
394  * This register gets reset only on a cold reset.
395  *
396  * Register Layout
397  *
398  * Bits | Access | Reset | Description
399  * :--------|:-------|:--------|:-----------------------------
400  * [0] | R | Unknown | ALT_SYSMGR_BOOT_FPGA_BSEL_EN
401  * [3:1] | ??? | Unknown | *UNDEFINED*
402  * [6:4] | R | Unknown | ALT_SYSMGR_BOOT_FPGA_BSEL
403  * [7] | ??? | Unknown | *UNDEFINED*
404  * [10:8] | R | Unknown | ALT_SYSMGR_BOOT_PIN_BSEL
405  * [11] | ??? | Unknown | *UNDEFINED*
406  * [14:12] | R | Unknown | ALT_SYSMGR_BOOT_BSEL
407  * [31:15] | ??? | Unknown | *UNDEFINED*
408  *
409  */
410 /*
411  * Field : fpga_bsel_en
412  *
413  * Specifies the value of the f2s_bsel_en. f2s_bsel_en is a signal from FPGA.
414  *
415  * If 1, boot select value is equal to FPGA boot select signal (f2s_bsel).
416  *
417  * If 0, boot select value is equal to the sampled value of HPS BSEL pins.
418  *
419  * Value of f2s_bsel_en is overidden to 0x0 if FPGA is not in user mode
420  * (fpga_config_complete = 0)
421  *
422  * Field Access Macros:
423  *
424  */
425 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field. */
426 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_LSB 0
427 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field. */
428 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_MSB 0
429 /* The width in bits of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field. */
430 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_WIDTH 1
431 /* The mask used to set the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value. */
432 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET_MSK 0x00000001
433 /* The mask used to clear the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value. */
434 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_CLR_MSK 0xfffffffe
435 /* The reset value of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field is UNKNOWN. */
436 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_RESET 0x0
437 /* Extracts the ALT_SYSMGR_BOOT_FPGA_BSEL_EN field value from a register. */
438 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_GET(value) (((value) & 0x00000001) >> 0)
439 /* Produces a ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value suitable for setting the register. */
440 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET(value) (((value) << 0) & 0x00000001)
441 
442 /*
443  * Field : fpga_bsel
444  *
445  * The boot select field specifies the boot source. It is read by the Boot ROM code
446  * on a cold or warm reset to determine the boot source.
447  *
448  * The boot select value is equal to the f2s_bsel signal from the FPGA if the
449  * f2s_bsel_en signal from the FPGA is 1 or equal to the sampled value of HPS BSEL
450  * pins if the f2s_bsel_en signal from the FPGA is 0 or the FPGA is not powered on
451  * or not in User Mode (fpga_config_complete = 0).
452  *
453  * The HPS BSEL pins value are sampled upon deassertion of cold reset.
454  *
455  * Field Enumeration Values:
456  *
457  * Enum | Value | Description
458  * :-------------------------------------------------------------|:------|:------------
459  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX | 0x0 |
460  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA | 0x1 |
461  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V | 0x2 |
462  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V | 0x3 |
463  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 |
464  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 |
465  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V | 0x6 |
466  * ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V | 0x7 |
467  *
468  * Field Access Macros:
469  *
470  */
471 /*
472  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
473  *
474  */
475 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX 0x0
476 /*
477  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
478  *
479  */
480 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA 0x1
481 /*
482  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
483  *
484  */
485 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V 0x2
486 /*
487  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
488  *
489  */
490 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V 0x3
491 /*
492  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
493  *
494  */
495 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
496 /*
497  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
498  *
499  */
500 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
501 /*
502  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
503  *
504  */
505 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V 0x6
506 /*
507  * Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL
508  *
509  */
510 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V 0x7
511 
512 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL register field. */
513 #define ALT_SYSMGR_BOOT_FPGA_BSEL_LSB 4
514 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL register field. */
515 #define ALT_SYSMGR_BOOT_FPGA_BSEL_MSB 6
516 /* The width in bits of the ALT_SYSMGR_BOOT_FPGA_BSEL register field. */
517 #define ALT_SYSMGR_BOOT_FPGA_BSEL_WIDTH 3
518 /* The mask used to set the ALT_SYSMGR_BOOT_FPGA_BSEL register field value. */
519 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET_MSK 0x00000070
520 /* The mask used to clear the ALT_SYSMGR_BOOT_FPGA_BSEL register field value. */
521 #define ALT_SYSMGR_BOOT_FPGA_BSEL_CLR_MSK 0xffffff8f
522 /* The reset value of the ALT_SYSMGR_BOOT_FPGA_BSEL register field is UNKNOWN. */
523 #define ALT_SYSMGR_BOOT_FPGA_BSEL_RESET 0x0
524 /* Extracts the ALT_SYSMGR_BOOT_FPGA_BSEL field value from a register. */
525 #define ALT_SYSMGR_BOOT_FPGA_BSEL_GET(value) (((value) & 0x00000070) >> 4)
526 /* Produces a ALT_SYSMGR_BOOT_FPGA_BSEL register field value suitable for setting the register. */
527 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET(value) (((value) << 4) & 0x00000070)
528 
529 /*
530  * Field : pin_bsel
531  *
532  * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are
533  * sampled upon deassertion of cold reset.
534  *
535  * Field Enumeration Values:
536  *
537  * Enum | Value | Description
538  * :------------------------------------------------------------|:------|:------------
539  * ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX | 0x0 |
540  * ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA | 0x1 |
541  * ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V | 0x2 |
542  * ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V | 0x3 |
543  * ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 |
544  * ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 |
545  * ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V | 0x6 |
546  * ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V | 0x7 |
547  *
548  * Field Access Macros:
549  *
550  */
551 /*
552  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
553  *
554  */
555 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX 0x0
556 /*
557  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
558  *
559  */
560 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA 0x1
561 /*
562  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
563  *
564  */
565 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V 0x2
566 /*
567  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
568  *
569  */
570 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V 0x3
571 /*
572  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
573  *
574  */
575 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
576 /*
577  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
578  *
579  */
580 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
581 /*
582  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
583  *
584  */
585 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V 0x6
586 /*
587  * Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL
588  *
589  */
590 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V 0x7
591 
592 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PIN_BSEL register field. */
593 #define ALT_SYSMGR_BOOT_PIN_BSEL_LSB 8
594 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PIN_BSEL register field. */
595 #define ALT_SYSMGR_BOOT_PIN_BSEL_MSB 10
596 /* The width in bits of the ALT_SYSMGR_BOOT_PIN_BSEL register field. */
597 #define ALT_SYSMGR_BOOT_PIN_BSEL_WIDTH 3
598 /* The mask used to set the ALT_SYSMGR_BOOT_PIN_BSEL register field value. */
599 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET_MSK 0x00000700
600 /* The mask used to clear the ALT_SYSMGR_BOOT_PIN_BSEL register field value. */
601 #define ALT_SYSMGR_BOOT_PIN_BSEL_CLR_MSK 0xfffff8ff
602 /* The reset value of the ALT_SYSMGR_BOOT_PIN_BSEL register field is UNKNOWN. */
603 #define ALT_SYSMGR_BOOT_PIN_BSEL_RESET 0x0
604 /* Extracts the ALT_SYSMGR_BOOT_PIN_BSEL field value from a register. */
605 #define ALT_SYSMGR_BOOT_PIN_BSEL_GET(value) (((value) & 0x00000700) >> 8)
606 /* Produces a ALT_SYSMGR_BOOT_PIN_BSEL register field value suitable for setting the register. */
607 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET(value) (((value) << 8) & 0x00000700)
608 
609 /*
610  * Field : bsel
611  *
612  * Multiplexed Value of Boot Select from pins and fpga
613  *
614  * Field Enumeration Values:
615  *
616  * Enum | Value | Description
617  * :--------------------------------------------------------|:------|:------------
618  * ALT_SYSMGR_BOOT_BSEL_E_RSVDX | 0x0 |
619  * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 |
620  * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 |
621  * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 |
622  * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 |
623  * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 |
624  * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 |
625  * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 |
626  *
627  * Field Access Macros:
628  *
629  */
630 /*
631  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
632  *
633  */
634 #define ALT_SYSMGR_BOOT_BSEL_E_RSVDX 0x0
635 /*
636  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
637  *
638  */
639 #define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
640 /*
641  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
642  *
643  */
644 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
645 /*
646  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
647  *
648  */
649 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
650 /*
651  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
652  *
653  */
654 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
655 /*
656  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
657  *
658  */
659 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
660 /*
661  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
662  *
663  */
664 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
665 /*
666  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
667  *
668  */
669 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
670 
671 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
672 #define ALT_SYSMGR_BOOT_BSEL_LSB 12
673 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
674 #define ALT_SYSMGR_BOOT_BSEL_MSB 14
675 /* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */
676 #define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
677 /* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */
678 #define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00007000
679 /* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */
680 #define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xffff8fff
681 /* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */
682 #define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
683 /* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */
684 #define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00007000) >> 12)
685 /* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */
686 #define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 12) & 0x00007000)
687 
688 #ifndef __ASSEMBLY__
689 /*
690  * WARNING: The C register and register group struct declarations are provided for
691  * convenience and illustrative purposes. They should, however, be used with
692  * caution as the C language standard provides no guarantees about the alignment or
693  * atomicity of device memory accesses. The recommended practice for writing
694  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
695  * alt_write_word() functions.
696  *
697  * The struct declaration for register ALT_SYSMGR_BOOT.
698  */
699 struct ALT_SYSMGR_BOOT_s
700 {
701  const uint32_t fpga_bsel_en : 1; /* ALT_SYSMGR_BOOT_FPGA_BSEL_EN */
702  uint32_t : 3; /* *UNDEFINED* */
703  const uint32_t fpga_bsel : 3; /* ALT_SYSMGR_BOOT_FPGA_BSEL */
704  uint32_t : 1; /* *UNDEFINED* */
705  const uint32_t pin_bsel : 3; /* ALT_SYSMGR_BOOT_PIN_BSEL */
706  uint32_t : 1; /* *UNDEFINED* */
707  const uint32_t bsel : 3; /* ALT_SYSMGR_BOOT_BSEL */
708  uint32_t : 17; /* *UNDEFINED* */
709 };
710 
711 /* The typedef declaration for register ALT_SYSMGR_BOOT. */
712 typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
713 #endif /* __ASSEMBLY__ */
714 
715 /* The reset value of the ALT_SYSMGR_BOOT register. */
716 #define ALT_SYSMGR_BOOT_RESET 0x00000000
717 /* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */
718 #define ALT_SYSMGR_BOOT_OFST 0xc
719 
720 /*
721  * Register : L2 Data RAM ECC Enable Register - mpu_ctrl_l2_ecc
722  *
723  * This register is used to enable ECC on the L2 Data RAM. ECC errors can be
724  * injected into the write path using bits in this register. This register contains
725  * interrupt status of the ECC single/double bit error.
726  *
727  * Some fileds of this register are only reset by a cold reset (ignores warm
728  * reset).
729  *
730  * Some fields are affected by both warm and cold reset.
731  *
732  * Register Layout
733  *
734  * Bits | Access | Reset | Description
735  * :--------|:-------|:------|:--------------------------------------------------
736  * [0] | RW | 0x0 | L2 Data RAM Error Correction and Detection Enable
737  * [7:1] | ??? | 0x0 | *UNDEFINED*
738  * [8] | RW | 0x0 | ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN
739  * [15:9] | ??? | 0x0 | *UNDEFINED*
740  * [16] | RW | 0x0 | ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE
741  * [31:17] | ??? | 0x0 | *UNDEFINED*
742  *
743  */
744 /*
745  * Field : L2 Data RAM Error Correction and Detection Enable - ecc_en
746  *
747  * Enable Single bit or Double bit error Detection and Single bit Error Correction
748  * for L2 Data RAM
749  *
750  * Only reset by a cold reset (ignores warm reset).
751  *
752  * Field Access Macros:
753  *
754  */
755 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field. */
756 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_LSB 0
757 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field. */
758 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_MSB 0
759 /* The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field. */
760 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_WIDTH 1
761 /* The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value. */
762 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET_MSK 0x00000001
763 /* The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value. */
764 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_CLR_MSK 0xfffffffe
765 /* The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field. */
766 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_RESET 0x0
767 /* Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN field value from a register. */
768 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
769 /* Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value suitable for setting the register. */
770 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
771 
772 /*
773  * Field : inj_en
774  *
775  * Error injection enable. Write 1 here to enable error injection to MPU L2.
776  *
777  * Please note that if ECC is not enabled by writing 1 to ecc_en bit there wont be
778  * any error injections.
779  *
780  * This bit will get reset on a warm reset and cold reset.
781  *
782  * Field Access Macros:
783  *
784  */
785 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field. */
786 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_LSB 8
787 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field. */
788 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_MSB 8
789 /* The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field. */
790 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_WIDTH 1
791 /* The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value. */
792 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET_MSK 0x00000100
793 /* The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value. */
794 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_CLR_MSK 0xfffffeff
795 /* The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field. */
796 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_RESET 0x0
797 /* Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN field value from a register. */
798 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_GET(value) (((value) & 0x00000100) >> 8)
799 /* Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value suitable for setting the register. */
800 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET(value) (((value) << 8) & 0x00000100)
801 
802 /*
803  * Field : inj_type
804  *
805  * MPU L2 ECC error injection type. This bit will get reset on a warm reset and
806  * cold reset.
807  *
808  * Field Enumeration Values:
809  *
810  * Enum | Value | Description
811  * :------------------------------------------------|:------|:------------
812  * ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT | 0x0 |
813  * ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT | 0x1 |
814  *
815  * Field Access Macros:
816  *
817  */
818 /*
819  * Enumerated value for register field ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE
820  *
821  */
822 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT 0x0
823 /*
824  * Enumerated value for register field ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE
825  *
826  */
827 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT 0x1
828 
829 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field. */
830 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_LSB 16
831 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field. */
832 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_MSB 16
833 /* The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field. */
834 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_WIDTH 1
835 /* The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value. */
836 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET_MSK 0x00010000
837 /* The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value. */
838 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_CLR_MSK 0xfffeffff
839 /* The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field. */
840 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_RESET 0x0
841 /* Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE field value from a register. */
842 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_GET(value) (((value) & 0x00010000) >> 16)
843 /* Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value suitable for setting the register. */
844 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET(value) (((value) << 16) & 0x00010000)
845 
846 #ifndef __ASSEMBLY__
847 /*
848  * WARNING: The C register and register group struct declarations are provided for
849  * convenience and illustrative purposes. They should, however, be used with
850  * caution as the C language standard provides no guarantees about the alignment or
851  * atomicity of device memory accesses. The recommended practice for writing
852  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
853  * alt_write_word() functions.
854  *
855  * The struct declaration for register ALT_SYSMGR_MPU_CTL_L2_ECC.
856  */
857 struct ALT_SYSMGR_MPU_CTL_L2_ECC_s
858 {
859  uint32_t ecc_en : 1; /* L2 Data RAM Error Correction and Detection Enable */
860  uint32_t : 7; /* *UNDEFINED* */
861  uint32_t inj_en : 1; /* ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN */
862  uint32_t : 7; /* *UNDEFINED* */
863  uint32_t inj_type : 1; /* ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE */
864  uint32_t : 15; /* *UNDEFINED* */
865 };
866 
867 /* The typedef declaration for register ALT_SYSMGR_MPU_CTL_L2_ECC. */
868 typedef volatile struct ALT_SYSMGR_MPU_CTL_L2_ECC_s ALT_SYSMGR_MPU_CTL_L2_ECC_t;
869 #endif /* __ASSEMBLY__ */
870 
871 /* The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC register. */
872 #define ALT_SYSMGR_MPU_CTL_L2_ECC_RESET 0x00000000
873 /* The byte offset of the ALT_SYSMGR_MPU_CTL_L2_ECC register from the beginning of the component. */
874 #define ALT_SYSMGR_MPU_CTL_L2_ECC_OFST 0x10
875 
876 /*
877  * Register : Control Register - dma
878  *
879  * Registers used by the DMA Controller. All fields are reset by a cold or warm
880  * reset.
881  *
882  * These register bits should be updated during system initialization prior to
883  * removing the DMA controller from reset. They may not be changed dynamically
884  * during DMA operation.
885  *
886  * Register Layout
887  *
888  * Bits | Access | Reset | Description
889  * :--------|:-------|:------|:--------------------------------
890  * [0] | RW | 0x0 | Channel Select I2C
891  * [3:1] | ??? | 0x0 | *UNDEFINED*
892  * [4] | RW | 0x0 | Channel Select I2C
893  * [7:5] | ??? | 0x0 | *UNDEFINED*
894  * [8] | RW | 0x1 | Channel Select Security Manager
895  * [15:9] | ??? | 0x0 | *UNDEFINED*
896  * [16] | RW | 0x0 | Manager Thread Security
897  * [23:17] | ??? | 0x0 | *UNDEFINED*
898  * [31:24] | RW | 0x0 | IRQ Security
899  *
900  */
901 /*
902  * Field : Channel Select I2C - chansel_0
903  *
904  * Select between FPGA interface 6 and I2C4_Tx to be mapped to DMA peripheral
905  * request index 6
906  *
907  * Field Enumeration Values:
908  *
909  * Enum | Value | Description
910  * :-----------------------------------|:------|:------------
911  * ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA | 0x0 |
912  * ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX | 0x1 |
913  *
914  * Field Access Macros:
915  *
916  */
917 /*
918  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_0
919  *
920  */
921 #define ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA 0x0
922 /*
923  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_0
924  *
925  */
926 #define ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX 0x1
927 
928 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_0 register field. */
929 #define ALT_SYSMGR_DMA_CHANSEL_0_LSB 0
930 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_0 register field. */
931 #define ALT_SYSMGR_DMA_CHANSEL_0_MSB 0
932 /* The width in bits of the ALT_SYSMGR_DMA_CHANSEL_0 register field. */
933 #define ALT_SYSMGR_DMA_CHANSEL_0_WIDTH 1
934 /* The mask used to set the ALT_SYSMGR_DMA_CHANSEL_0 register field value. */
935 #define ALT_SYSMGR_DMA_CHANSEL_0_SET_MSK 0x00000001
936 /* The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_0 register field value. */
937 #define ALT_SYSMGR_DMA_CHANSEL_0_CLR_MSK 0xfffffffe
938 /* The reset value of the ALT_SYSMGR_DMA_CHANSEL_0 register field. */
939 #define ALT_SYSMGR_DMA_CHANSEL_0_RESET 0x0
940 /* Extracts the ALT_SYSMGR_DMA_CHANSEL_0 field value from a register. */
941 #define ALT_SYSMGR_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
942 /* Produces a ALT_SYSMGR_DMA_CHANSEL_0 register field value suitable for setting the register. */
943 #define ALT_SYSMGR_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
944 
945 /*
946  * Field : Channel Select I2C - chansel_1
947  *
948  * select between FPGA interface 7 and I2C4_Rx to be mapped to DMA peripheral
949  * request index 7
950  *
951  * Field Enumeration Values:
952  *
953  * Enum | Value | Description
954  * :-----------------------------------|:------|:------------
955  * ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA | 0x0 |
956  * ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX | 0x1 |
957  *
958  * Field Access Macros:
959  *
960  */
961 /*
962  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_1
963  *
964  */
965 #define ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA 0x0
966 /*
967  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_1
968  *
969  */
970 #define ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX 0x1
971 
972 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_1 register field. */
973 #define ALT_SYSMGR_DMA_CHANSEL_1_LSB 4
974 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_1 register field. */
975 #define ALT_SYSMGR_DMA_CHANSEL_1_MSB 4
976 /* The width in bits of the ALT_SYSMGR_DMA_CHANSEL_1 register field. */
977 #define ALT_SYSMGR_DMA_CHANSEL_1_WIDTH 1
978 /* The mask used to set the ALT_SYSMGR_DMA_CHANSEL_1 register field value. */
979 #define ALT_SYSMGR_DMA_CHANSEL_1_SET_MSK 0x00000010
980 /* The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_1 register field value. */
981 #define ALT_SYSMGR_DMA_CHANSEL_1_CLR_MSK 0xffffffef
982 /* The reset value of the ALT_SYSMGR_DMA_CHANSEL_1 register field. */
983 #define ALT_SYSMGR_DMA_CHANSEL_1_RESET 0x0
984 /* Extracts the ALT_SYSMGR_DMA_CHANSEL_1 field value from a register. */
985 #define ALT_SYSMGR_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4)
986 /* Produces a ALT_SYSMGR_DMA_CHANSEL_1 register field value suitable for setting the register. */
987 #define ALT_SYSMGR_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010)
988 
989 /*
990  * Field : Channel Select Security Manager - chansel_2
991  *
992  * select between FPGA interface 5 and Security Manager to be mapped to DMA
993  * peripheral request index 5
994  *
995  * Field Enumeration Values:
996  *
997  * Enum | Value | Description
998  * :----------------------------------|:------|:------------
999  * ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA | 0x0 |
1000  * ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR | 0x1 |
1001  *
1002  * Field Access Macros:
1003  *
1004  */
1005 /*
1006  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_2
1007  *
1008  */
1009 #define ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA 0x0
1010 /*
1011  * Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_2
1012  *
1013  */
1014 #define ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR 0x1
1015 
1016 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_2 register field. */
1017 #define ALT_SYSMGR_DMA_CHANSEL_2_LSB 8
1018 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_2 register field. */
1019 #define ALT_SYSMGR_DMA_CHANSEL_2_MSB 8
1020 /* The width in bits of the ALT_SYSMGR_DMA_CHANSEL_2 register field. */
1021 #define ALT_SYSMGR_DMA_CHANSEL_2_WIDTH 1
1022 /* The mask used to set the ALT_SYSMGR_DMA_CHANSEL_2 register field value. */
1023 #define ALT_SYSMGR_DMA_CHANSEL_2_SET_MSK 0x00000100
1024 /* The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_2 register field value. */
1025 #define ALT_SYSMGR_DMA_CHANSEL_2_CLR_MSK 0xfffffeff
1026 /* The reset value of the ALT_SYSMGR_DMA_CHANSEL_2 register field. */
1027 #define ALT_SYSMGR_DMA_CHANSEL_2_RESET 0x1
1028 /* Extracts the ALT_SYSMGR_DMA_CHANSEL_2 field value from a register. */
1029 #define ALT_SYSMGR_DMA_CHANSEL_2_GET(value) (((value) & 0x00000100) >> 8)
1030 /* Produces a ALT_SYSMGR_DMA_CHANSEL_2 register field value suitable for setting the register. */
1031 #define ALT_SYSMGR_DMA_CHANSEL_2_SET(value) (((value) << 8) & 0x00000100)
1032 
1033 /*
1034  * Field : Manager Thread Security - mgr_ns
1035  *
1036  * Specifies the security state of the DMA manager thread.
1037  *
1038  * 0 = assigns DMA manager to the Secure state.
1039  *
1040  * 1 = assigns DMA manager to the Non-secure state.
1041  *
1042  * Sampled by the DMA controller when it exits from reset.
1043  *
1044  * Field Access Macros:
1045  *
1046  */
1047 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_MGR_NS register field. */
1048 #define ALT_SYSMGR_DMA_MGR_NS_LSB 16
1049 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_MGR_NS register field. */
1050 #define ALT_SYSMGR_DMA_MGR_NS_MSB 16
1051 /* The width in bits of the ALT_SYSMGR_DMA_MGR_NS register field. */
1052 #define ALT_SYSMGR_DMA_MGR_NS_WIDTH 1
1053 /* The mask used to set the ALT_SYSMGR_DMA_MGR_NS register field value. */
1054 #define ALT_SYSMGR_DMA_MGR_NS_SET_MSK 0x00010000
1055 /* The mask used to clear the ALT_SYSMGR_DMA_MGR_NS register field value. */
1056 #define ALT_SYSMGR_DMA_MGR_NS_CLR_MSK 0xfffeffff
1057 /* The reset value of the ALT_SYSMGR_DMA_MGR_NS register field. */
1058 #define ALT_SYSMGR_DMA_MGR_NS_RESET 0x0
1059 /* Extracts the ALT_SYSMGR_DMA_MGR_NS field value from a register. */
1060 #define ALT_SYSMGR_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16)
1061 /* Produces a ALT_SYSMGR_DMA_MGR_NS register field value suitable for setting the register. */
1062 #define ALT_SYSMGR_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000)
1063 
1064 /*
1065  * Field : IRQ Security - irq_ns
1066  *
1067  * Specifies the security state of an event-interrupt resource.
1068  *
1069  * If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state.
1070  *
1071  * If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure
1072  * state.
1073  *
1074  * Field Access Macros:
1075  *
1076  */
1077 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_IRQ_NS register field. */
1078 #define ALT_SYSMGR_DMA_IRQ_NS_LSB 24
1079 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_IRQ_NS register field. */
1080 #define ALT_SYSMGR_DMA_IRQ_NS_MSB 31
1081 /* The width in bits of the ALT_SYSMGR_DMA_IRQ_NS register field. */
1082 #define ALT_SYSMGR_DMA_IRQ_NS_WIDTH 8
1083 /* The mask used to set the ALT_SYSMGR_DMA_IRQ_NS register field value. */
1084 #define ALT_SYSMGR_DMA_IRQ_NS_SET_MSK 0xff000000
1085 /* The mask used to clear the ALT_SYSMGR_DMA_IRQ_NS register field value. */
1086 #define ALT_SYSMGR_DMA_IRQ_NS_CLR_MSK 0x00ffffff
1087 /* The reset value of the ALT_SYSMGR_DMA_IRQ_NS register field. */
1088 #define ALT_SYSMGR_DMA_IRQ_NS_RESET 0x0
1089 /* Extracts the ALT_SYSMGR_DMA_IRQ_NS field value from a register. */
1090 #define ALT_SYSMGR_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24)
1091 /* Produces a ALT_SYSMGR_DMA_IRQ_NS register field value suitable for setting the register. */
1092 #define ALT_SYSMGR_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000)
1093 
1094 #ifndef __ASSEMBLY__
1095 /*
1096  * WARNING: The C register and register group struct declarations are provided for
1097  * convenience and illustrative purposes. They should, however, be used with
1098  * caution as the C language standard provides no guarantees about the alignment or
1099  * atomicity of device memory accesses. The recommended practice for writing
1100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1101  * alt_write_word() functions.
1102  *
1103  * The struct declaration for register ALT_SYSMGR_DMA.
1104  */
1105 struct ALT_SYSMGR_DMA_s
1106 {
1107  uint32_t chansel_0 : 1; /* Channel Select I2C */
1108  uint32_t : 3; /* *UNDEFINED* */
1109  uint32_t chansel_1 : 1; /* Channel Select I2C */
1110  uint32_t : 3; /* *UNDEFINED* */
1111  uint32_t chansel_2 : 1; /* Channel Select Security Manager */
1112  uint32_t : 7; /* *UNDEFINED* */
1113  uint32_t mgr_ns : 1; /* Manager Thread Security */
1114  uint32_t : 7; /* *UNDEFINED* */
1115  uint32_t irq_ns : 8; /* IRQ Security */
1116 };
1117 
1118 /* The typedef declaration for register ALT_SYSMGR_DMA. */
1119 typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
1120 #endif /* __ASSEMBLY__ */
1121 
1122 /* The reset value of the ALT_SYSMGR_DMA register. */
1123 #define ALT_SYSMGR_DMA_RESET 0x00000100
1124 /* The byte offset of the ALT_SYSMGR_DMA register from the beginning of the component. */
1125 #define ALT_SYSMGR_DMA_OFST 0x20
1126 
1127 /*
1128  * Register : Peripheral Security Register - dma_periph
1129  *
1130  * Controls the security state of a peripheral request interface. Sampled by the
1131  * DMA controller when it exits from reset.
1132  *
1133  * These register bits should be updated during system initialization prior to
1134  * removing the DMA controller from reset. They may not be changed dynamically
1135  * during DMA operation.
1136  *
1137  * Register Layout
1138  *
1139  * Bits | Access | Reset | Description
1140  * :-------|:-------|:------|:----------------------
1141  * [31:0] | RW | 0x0 | Peripheral Non-Secure
1142  *
1143  */
1144 /*
1145  * Field : Peripheral Non-Secure - ns
1146  *
1147  * If bit index [x] is 0, the DMA controller assigns peripheral request interface x
1148  * to the Secure state.
1149  *
1150  * If bit index [x] is 1, the DMA controller assigns peripheral request interface x
1151  * to the Non-secure state.
1152  *
1153  * Reset by a cold or warm reset.
1154  *
1155  * Field Access Macros:
1156  *
1157  */
1158 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERIPH_NS register field. */
1159 #define ALT_SYSMGR_DMA_PERIPH_NS_LSB 0
1160 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERIPH_NS register field. */
1161 #define ALT_SYSMGR_DMA_PERIPH_NS_MSB 31
1162 /* The width in bits of the ALT_SYSMGR_DMA_PERIPH_NS register field. */
1163 #define ALT_SYSMGR_DMA_PERIPH_NS_WIDTH 32
1164 /* The mask used to set the ALT_SYSMGR_DMA_PERIPH_NS register field value. */
1165 #define ALT_SYSMGR_DMA_PERIPH_NS_SET_MSK 0xffffffff
1166 /* The mask used to clear the ALT_SYSMGR_DMA_PERIPH_NS register field value. */
1167 #define ALT_SYSMGR_DMA_PERIPH_NS_CLR_MSK 0x00000000
1168 /* The reset value of the ALT_SYSMGR_DMA_PERIPH_NS register field. */
1169 #define ALT_SYSMGR_DMA_PERIPH_NS_RESET 0x0
1170 /* Extracts the ALT_SYSMGR_DMA_PERIPH_NS field value from a register. */
1171 #define ALT_SYSMGR_DMA_PERIPH_NS_GET(value) (((value) & 0xffffffff) >> 0)
1172 /* Produces a ALT_SYSMGR_DMA_PERIPH_NS register field value suitable for setting the register. */
1173 #define ALT_SYSMGR_DMA_PERIPH_NS_SET(value) (((value) << 0) & 0xffffffff)
1174 
1175 #ifndef __ASSEMBLY__
1176 /*
1177  * WARNING: The C register and register group struct declarations are provided for
1178  * convenience and illustrative purposes. They should, however, be used with
1179  * caution as the C language standard provides no guarantees about the alignment or
1180  * atomicity of device memory accesses. The recommended practice for writing
1181  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1182  * alt_write_word() functions.
1183  *
1184  * The struct declaration for register ALT_SYSMGR_DMA_PERIPH.
1185  */
1186 struct ALT_SYSMGR_DMA_PERIPH_s
1187 {
1188  uint32_t ns : 32; /* Peripheral Non-Secure */
1189 };
1190 
1191 /* The typedef declaration for register ALT_SYSMGR_DMA_PERIPH. */
1192 typedef volatile struct ALT_SYSMGR_DMA_PERIPH_s ALT_SYSMGR_DMA_PERIPH_t;
1193 #endif /* __ASSEMBLY__ */
1194 
1195 /* The reset value of the ALT_SYSMGR_DMA_PERIPH register. */
1196 #define ALT_SYSMGR_DMA_PERIPH_RESET 0x00000000
1197 /* The byte offset of the ALT_SYSMGR_DMA_PERIPH register from the beginning of the component. */
1198 #define ALT_SYSMGR_DMA_PERIPH_OFST 0x24
1199 
1200 /*
1201  * Register : Control Register - sdmmc
1202  *
1203  * Registers used by the SDMMC Controller. All fields are reset by a cold or warm
1204  * reset.
1205  *
1206  * Register Layout
1207  *
1208  * Bits | Access | Reset | Description
1209  * :-------|:-------|:------|:--------------------------------
1210  * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select
1211  * [3] | ??? | 0x0 | *UNDEFINED*
1212  * [6:4] | RW | 0x0 | Sample Clock Phase Shift Select
1213  * [31:7] | ??? | 0x0 | *UNDEFINED*
1214  *
1215  */
1216 /*
1217  * Field : Drive Clock Phase Shift Select - drvsel
1218  *
1219  * Select which phase shift of the clock for cclk_in_drv.
1220  *
1221  * Field Enumeration Values:
1222  *
1223  * Enum | Value | Description
1224  * :-------------------------------------|:------|:------------
1225  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES0 | 0x0 |
1226  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES45 | 0x1 |
1227  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES90 | 0x2 |
1228  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES135 | 0x3 |
1229  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES180 | 0x4 |
1230  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES225 | 0x5 |
1231  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES270 | 0x6 |
1232  * ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES315 | 0x7 |
1233  *
1234  * Field Access Macros:
1235  *
1236  */
1237 /*
1238  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1239  *
1240  */
1241 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES0 0x0
1242 /*
1243  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1244  *
1245  */
1246 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES45 0x1
1247 /*
1248  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1249  *
1250  */
1251 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES90 0x2
1252 /*
1253  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1254  *
1255  */
1256 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES135 0x3
1257 /*
1258  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1259  *
1260  */
1261 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES180 0x4
1262 /*
1263  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1264  *
1265  */
1266 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES225 0x5
1267 /*
1268  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1269  *
1270  */
1271 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES270 0x6
1272 /*
1273  * Enumerated value for register field ALT_SYSMGR_SDMMC_DRVSEL
1274  *
1275  */
1276 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES315 0x7
1277 
1278 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_DRVSEL register field. */
1279 #define ALT_SYSMGR_SDMMC_DRVSEL_LSB 0
1280 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_DRVSEL register field. */
1281 #define ALT_SYSMGR_SDMMC_DRVSEL_MSB 2
1282 /* The width in bits of the ALT_SYSMGR_SDMMC_DRVSEL register field. */
1283 #define ALT_SYSMGR_SDMMC_DRVSEL_WIDTH 3
1284 /* The mask used to set the ALT_SYSMGR_SDMMC_DRVSEL register field value. */
1285 #define ALT_SYSMGR_SDMMC_DRVSEL_SET_MSK 0x00000007
1286 /* The mask used to clear the ALT_SYSMGR_SDMMC_DRVSEL register field value. */
1287 #define ALT_SYSMGR_SDMMC_DRVSEL_CLR_MSK 0xfffffff8
1288 /* The reset value of the ALT_SYSMGR_SDMMC_DRVSEL register field. */
1289 #define ALT_SYSMGR_SDMMC_DRVSEL_RESET 0x0
1290 /* Extracts the ALT_SYSMGR_SDMMC_DRVSEL field value from a register. */
1291 #define ALT_SYSMGR_SDMMC_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
1292 /* Produces a ALT_SYSMGR_SDMMC_DRVSEL register field value suitable for setting the register. */
1293 #define ALT_SYSMGR_SDMMC_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
1294 
1295 /*
1296  * Field : Sample Clock Phase Shift Select - smplsel
1297  *
1298  * Select which phase shift of the clock for cclk_in_sample.
1299  *
1300  * Field Enumeration Values:
1301  *
1302  * Enum | Value | Description
1303  * :--------------------------------------|:------|:------------
1304  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES0 | 0x0 |
1305  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES45 | 0x1 |
1306  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES90 | 0x2 |
1307  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES135 | 0x3 |
1308  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES180 | 0x4 |
1309  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES225 | 0x5 |
1310  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES270 | 0x6 |
1311  * ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES315 | 0x7 |
1312  *
1313  * Field Access Macros:
1314  *
1315  */
1316 /*
1317  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1318  *
1319  */
1320 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES0 0x0
1321 /*
1322  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1323  *
1324  */
1325 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES45 0x1
1326 /*
1327  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1328  *
1329  */
1330 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES90 0x2
1331 /*
1332  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1333  *
1334  */
1335 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES135 0x3
1336 /*
1337  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1338  *
1339  */
1340 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES180 0x4
1341 /*
1342  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1343  *
1344  */
1345 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES225 0x5
1346 /*
1347  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1348  *
1349  */
1350 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES270 0x6
1351 /*
1352  * Enumerated value for register field ALT_SYSMGR_SDMMC_SMPLSEL
1353  *
1354  */
1355 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES315 0x7
1356 
1357 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_SMPLSEL register field. */
1358 #define ALT_SYSMGR_SDMMC_SMPLSEL_LSB 4
1359 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_SMPLSEL register field. */
1360 #define ALT_SYSMGR_SDMMC_SMPLSEL_MSB 6
1361 /* The width in bits of the ALT_SYSMGR_SDMMC_SMPLSEL register field. */
1362 #define ALT_SYSMGR_SDMMC_SMPLSEL_WIDTH 3
1363 /* The mask used to set the ALT_SYSMGR_SDMMC_SMPLSEL register field value. */
1364 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET_MSK 0x00000070
1365 /* The mask used to clear the ALT_SYSMGR_SDMMC_SMPLSEL register field value. */
1366 #define ALT_SYSMGR_SDMMC_SMPLSEL_CLR_MSK 0xffffff8f
1367 /* The reset value of the ALT_SYSMGR_SDMMC_SMPLSEL register field. */
1368 #define ALT_SYSMGR_SDMMC_SMPLSEL_RESET 0x0
1369 /* Extracts the ALT_SYSMGR_SDMMC_SMPLSEL field value from a register. */
1370 #define ALT_SYSMGR_SDMMC_SMPLSEL_GET(value) (((value) & 0x00000070) >> 4)
1371 /* Produces a ALT_SYSMGR_SDMMC_SMPLSEL register field value suitable for setting the register. */
1372 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET(value) (((value) << 4) & 0x00000070)
1373 
1374 #ifndef __ASSEMBLY__
1375 /*
1376  * WARNING: The C register and register group struct declarations are provided for
1377  * convenience and illustrative purposes. They should, however, be used with
1378  * caution as the C language standard provides no guarantees about the alignment or
1379  * atomicity of device memory accesses. The recommended practice for writing
1380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1381  * alt_write_word() functions.
1382  *
1383  * The struct declaration for register ALT_SYSMGR_SDMMC.
1384  */
1385 struct ALT_SYSMGR_SDMMC_s
1386 {
1387  uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */
1388  uint32_t : 1; /* *UNDEFINED* */
1389  uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */
1390  uint32_t : 25; /* *UNDEFINED* */
1391 };
1392 
1393 /* The typedef declaration for register ALT_SYSMGR_SDMMC. */
1394 typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
1395 #endif /* __ASSEMBLY__ */
1396 
1397 /* The reset value of the ALT_SYSMGR_SDMMC register. */
1398 #define ALT_SYSMGR_SDMMC_RESET 0x00000000
1399 /* The byte offset of the ALT_SYSMGR_SDMMC register from the beginning of the component. */
1400 #define ALT_SYSMGR_SDMMC_OFST 0x28
1401 
1402 /*
1403  * Register : SD/MMC L3 Master HPROT Register - sdmmc_l3master
1404  *
1405  * Controls the L3 master HPROT AHB-Lite signal.
1406  *
1407  * These register bits should be updated only during system initialization prior to
1408  * removing the peripheral from reset. They may not be changed dynamically during
1409  * peripheral operation
1410  *
1411  * All fields are reset by a cold or warm reset.
1412  *
1413  * Register Layout
1414  *
1415  * Bits | Access | Reset | Description
1416  * :-------|:-------|:------|:-----------------------------
1417  * [4:0] | RW | 0x3 | ALT_SYSMGR_SDMMC_L3MST_HPROT
1418  * [31:5] | ??? | 0x0 | *UNDEFINED*
1419  *
1420  */
1421 /*
1422  * Field : hprot
1423  *
1424  * ==========================
1425  *
1426  * HPROT[4] Allocate
1427  *
1428  * 0: L3 master accesses for the module are non-allocatable
1429  *
1430  * 1: L3 master accesses for the module are allocatable
1431  *
1432  * ==========================
1433  *
1434  * HPROT[3] Cachable
1435  *
1436  * 0: L3 master accesses for the module are non-cacheable.
1437  *
1438  * 1: L3 master accesses for the module are cacheable.
1439  *
1440  * ==========================
1441  *
1442  * HPROT[2] Bufferable
1443  *
1444  * 0: L3 master accesses for the module are not bufferable.
1445  *
1446  * 1: L3 master accesses for the module are bufferable.
1447  *
1448  * ==========================
1449  *
1450  * HPROT[1] Privileged
1451  *
1452  * 0: L3 master accesses for the module are not privileged.
1453  *
1454  * 1: L3 master accesses for the module are privileged.
1455  *
1456  * ==========================
1457  *
1458  * HPROT[0] Data/Opcode
1459  *
1460  * 0: Specifies if the L3 master access is for opcode
1461  *
1462  * 1: Specifies if the L3 master access is for data
1463  *
1464  * ==========================
1465  *
1466  * HPROT[4:2] Example Encodings
1467  *
1468  * ==========================
1469  *
1470  * 0 0 0 Strongly Ordered, cannot be buffered
1471  *
1472  * 0 0 1 Device, can be buffered
1473  *
1474  * 0 1 0 Cachable (Outer Noncachable, do not allocate on reads or
1475  * writes)
1476  *
1477  * 1 1 0 Cachable Write-Through (allocate on reads only, no
1478  * allocate on write)
1479  *
1480  * 0 1 1 Cachable Write-Back (allocate on reads and writes)
1481  *
1482  * 1 1 1 Cachable Write-Back (allocate on reads only, no allocate
1483  * on write)
1484  *
1485  * ==========================
1486  *
1487  * HPROT[1:0] Example Encodings
1488  *
1489  * ==========================
1490  *
1491  * * 0 Opcode Fetch
1492  *
1493  * * 1 Data Access
1494  *
1495  * 0 - User Access
1496  *
1497  * 1 - Privileged Access
1498  *
1499  * ==========================
1500  *
1501  * Field Access Macros:
1502  *
1503  */
1504 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROT register field. */
1505 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_LSB 0
1506 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROT register field. */
1507 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_MSB 4
1508 /* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROT register field. */
1509 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_WIDTH 5
1510 /* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROT register field value. */
1511 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET_MSK 0x0000001f
1512 /* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROT register field value. */
1513 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_CLR_MSK 0xffffffe0
1514 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROT register field. */
1515 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_RESET 0x3
1516 /* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROT field value from a register. */
1517 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_GET(value) (((value) & 0x0000001f) >> 0)
1518 /* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROT register field value suitable for setting the register. */
1519 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000001f)
1520 
1521 #ifndef __ASSEMBLY__
1522 /*
1523  * WARNING: The C register and register group struct declarations are provided for
1524  * convenience and illustrative purposes. They should, however, be used with
1525  * caution as the C language standard provides no guarantees about the alignment or
1526  * atomicity of device memory accesses. The recommended practice for writing
1527  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1528  * alt_write_word() functions.
1529  *
1530  * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST.
1531  */
1532 struct ALT_SYSMGR_SDMMC_L3MST_s
1533 {
1534  uint32_t hprot : 5; /* ALT_SYSMGR_SDMMC_L3MST_HPROT */
1535  uint32_t : 27; /* *UNDEFINED* */
1536 };
1537 
1538 /* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */
1539 typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t;
1540 #endif /* __ASSEMBLY__ */
1541 
1542 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST register. */
1543 #define ALT_SYSMGR_SDMMC_L3MST_RESET 0x00000003
1544 /* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */
1545 #define ALT_SYSMGR_SDMMC_L3MST_OFST 0x2c
1546 
1547 /*
1548  * Register : Bootstrap Control Register - nand_bootstrap
1549  *
1550  * Bootstrap fields sampled by NAND Flash Controller when released from reset.
1551  *
1552  * All fields are reset by a cold or warm reset.
1553  *
1554  * Register Layout
1555  *
1556  * Bits | Access | Reset | Description
1557  * :--------|:-------|:------|:--------------------------------------
1558  * [0] | RW | 0x0 | Bootstrap Inhibit Initialization
1559  * [7:1] | ??? | 0x0 | *UNDEFINED*
1560  * [8] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0
1561  * [15:9] | ??? | 0x0 | *UNDEFINED*
1562  * [16] | RW | 0x0 | Bootstrap Two Row Address Cycles
1563  * [23:17] | ??? | 0x0 | *UNDEFINED*
1564  * [24] | RW | 0x0 | Bootstrap 512 Byte Device
1565  * [27:25] | ??? | 0x0 | *UNDEFINED*
1566  * [28] | RW | 0x0 | ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16
1567  * [31:29] | ??? | 0x0 | *UNDEFINED*
1568  *
1569  */
1570 /*
1571  * Field : Bootstrap Inhibit Initialization - noinit
1572  *
1573  * If 1, inhibits NAND Flash Controller from performing initialization when coming
1574  * out of reset. Instead, software must program all registers pertaining to device
1575  * parameters like page size, width, etc.
1576  *
1577  * Field Access Macros:
1578  *
1579  */
1580 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
1581 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
1582 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
1583 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
1584 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
1585 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
1586 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
1587 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
1588 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
1589 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
1590 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
1591 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
1592 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */
1593 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
1594 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */
1595 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
1596 
1597 /*
1598  * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0
1599  *
1600  * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND
1601  * device as part of the initialization procedure.
1602  *
1603  * Field Access Macros:
1604  *
1605  */
1606 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
1607 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 8
1608 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
1609 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 8
1610 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
1611 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
1612 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
1613 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000100
1614 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
1615 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffeff
1616 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
1617 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
1618 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */
1619 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000100) >> 8)
1620 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */
1621 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 8) & 0x00000100)
1622 
1623 /*
1624  * Field : Bootstrap Two Row Address Cycles - tworowaddr
1625  *
1626  * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row
1627  * address cycles.
1628  *
1629  * Field Access Macros:
1630  *
1631  */
1632 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
1633 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 16
1634 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
1635 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 16
1636 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
1637 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
1638 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
1639 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00010000
1640 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
1641 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffeffff
1642 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
1643 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
1644 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */
1645 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00010000) >> 16)
1646 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */
1647 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 16) & 0x00010000)
1648 
1649 /*
1650  * Field : Bootstrap 512 Byte Device - page512
1651  *
1652  * If 1, NAND device has a 512 byte page size.
1653  *
1654  * Field Access Macros:
1655  *
1656  */
1657 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
1658 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 24
1659 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
1660 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 24
1661 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
1662 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
1663 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
1664 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x01000000
1665 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
1666 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfeffffff
1667 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
1668 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
1669 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */
1670 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x01000000) >> 24)
1671 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */
1672 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 24) & 0x01000000)
1673 
1674 /*
1675  * Field : page512_x16
1676  *
1677  * Reset value - 0
1678  *
1679  * Field name: PAGE512_x16_DEVICE
1680  *
1681  * Description: If 1, NAND device has 512 bytes page size and I/O width is 16 bits.
1682  * This start should be asserted in case of 512 bytes devices only. This signal
1683  * must be stable and have proper value by the time Controller comes out of Reset
1684  *
1685  * Field Access Macros:
1686  *
1687  */
1688 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1689 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_LSB 28
1690 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1691 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_MSB 28
1692 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1693 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_WIDTH 1
1694 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field value. */
1695 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET_MSK 0x10000000
1696 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field value. */
1697 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_CLR_MSK 0xefffffff
1698 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field. */
1699 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_RESET 0x0
1700 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 field value from a register. */
1701 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_GET(value) (((value) & 0x10000000) >> 28)
1702 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 register field value suitable for setting the register. */
1703 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET(value) (((value) << 28) & 0x10000000)
1704 
1705 #ifndef __ASSEMBLY__
1706 /*
1707  * WARNING: The C register and register group struct declarations are provided for
1708  * convenience and illustrative purposes. They should, however, be used with
1709  * caution as the C language standard provides no guarantees about the alignment or
1710  * atomicity of device memory accesses. The recommended practice for writing
1711  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1712  * alt_write_word() functions.
1713  *
1714  * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP.
1715  */
1716 struct ALT_SYSMGR_NAND_BOOTSTRAP_s
1717 {
1718  uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */
1719  uint32_t : 7; /* *UNDEFINED* */
1720  uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */
1721  uint32_t : 7; /* *UNDEFINED* */
1722  uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */
1723  uint32_t : 7; /* *UNDEFINED* */
1724  uint32_t page512 : 1; /* Bootstrap 512 Byte Device */
1725  uint32_t : 3; /* *UNDEFINED* */
1726  uint32_t page512_x16 : 1; /* ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16 */
1727  uint32_t : 3; /* *UNDEFINED* */
1728 };
1729 
1730 /* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */
1731 typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t;
1732 #endif /* __ASSEMBLY__ */
1733 
1734 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP register. */
1735 #define ALT_SYSMGR_NAND_BOOTSTRAP_RESET 0x00000000
1736 /* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */
1737 #define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x30
1738 
1739 /*
1740  * Register : NAND L3 Master AxCACHE Register - nand_l3master
1741  *
1742  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
1743  *
1744  * These register bits should be updated only during system initialization prior to
1745  * removing the peripheral from reset. They may not be changed dynamically during
1746  * peripheral operation
1747  *
1748  * All fields are reset by a cold or warm reset.
1749  *
1750  * Register Layout
1751  *
1752  * Bits | Access | Reset | Description
1753  * :-------|:-------|:------|:-------------
1754  * [3:0] | RW | 0x0 | NAND ARCACHE
1755  * [7:4] | RW | 0x0 | NAND AWCACHE
1756  * [31:8] | ??? | 0x0 | *UNDEFINED*
1757  *
1758  */
1759 /*
1760  * Field : NAND ARCACHE - arcache_0
1761  *
1762  * Specifies the value of the module ARCACHE signal.
1763  *
1764  * Field Enumeration Values:
1765  *
1766  * Enum | Value | Description
1767  * :-------------------------------------------------------|:------|:------------
1768  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 |
1769  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 |
1770  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 |
1771  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 |
1772  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 |
1773  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 |
1774  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 |
1775  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 |
1776  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 |
1777  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 |
1778  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa |
1779  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb |
1780  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc |
1781  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd |
1782  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe |
1783  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf |
1784  *
1785  * Field Access Macros:
1786  *
1787  */
1788 /*
1789  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1790  *
1791  */
1792 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
1793 /*
1794  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1795  *
1796  */
1797 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
1798 /*
1799  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1800  *
1801  */
1802 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
1803 /*
1804  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1805  *
1806  */
1807 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1808 /*
1809  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1810  *
1811  */
1812 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
1813 /*
1814  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1815  *
1816  */
1817 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
1818 /*
1819  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1820  *
1821  */
1822 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1823 /*
1824  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1825  *
1826  */
1827 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1828 /*
1829  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1830  *
1831  */
1832 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
1833 /*
1834  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1835  *
1836  */
1837 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
1838 /*
1839  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1840  *
1841  */
1842 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1843 /*
1844  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1845  *
1846  */
1847 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1848 /*
1849  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1850  *
1851  */
1852 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
1853 /*
1854  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1855  *
1856  */
1857 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
1858 /*
1859  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1860  *
1861  */
1862 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1863 /*
1864  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
1865  *
1866  */
1867 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1868 
1869 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
1870 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
1871 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
1872 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
1873 /* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
1874 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
1875 /* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
1876 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
1877 /* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
1878 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
1879 /* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
1880 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
1881 /* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */
1882 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
1883 /* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */
1884 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
1885 
1886 /*
1887  * Field : NAND AWCACHE - awcache_0
1888  *
1889  * Specifies the value of the module AWCACHE signal.
1890  *
1891  * Field Enumeration Values:
1892  *
1893  * Enum | Value | Description
1894  * :-------------------------------------------------------|:------|:------------
1895  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 |
1896  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 |
1897  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 |
1898  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 |
1899  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 |
1900  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 |
1901  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 |
1902  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 |
1903  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 |
1904  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 |
1905  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa |
1906  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb |
1907  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc |
1908  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd |
1909  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe |
1910  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf |
1911  *
1912  * Field Access Macros:
1913  *
1914  */
1915 /*
1916  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1917  *
1918  */
1919 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
1920 /*
1921  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1922  *
1923  */
1924 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
1925 /*
1926  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1927  *
1928  */
1929 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
1930 /*
1931  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1932  *
1933  */
1934 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1935 /*
1936  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1937  *
1938  */
1939 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
1940 /*
1941  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1942  *
1943  */
1944 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
1945 /*
1946  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1947  *
1948  */
1949 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1950 /*
1951  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1952  *
1953  */
1954 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1955 /*
1956  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1957  *
1958  */
1959 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
1960 /*
1961  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1962  *
1963  */
1964 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
1965 /*
1966  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1967  *
1968  */
1969 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1970 /*
1971  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1972  *
1973  */
1974 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1975 /*
1976  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1977  *
1978  */
1979 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
1980 /*
1981  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1982  *
1983  */
1984 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
1985 /*
1986  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1987  *
1988  */
1989 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1990 /*
1991  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
1992  *
1993  */
1994 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1995 
1996 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
1997 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
1998 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
1999 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
2000 /* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
2001 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
2002 /* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
2003 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
2004 /* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
2005 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
2006 /* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
2007 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
2008 /* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */
2009 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
2010 /* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */
2011 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
2012 
2013 #ifndef __ASSEMBLY__
2014 /*
2015  * WARNING: The C register and register group struct declarations are provided for
2016  * convenience and illustrative purposes. They should, however, be used with
2017  * caution as the C language standard provides no guarantees about the alignment or
2018  * atomicity of device memory accesses. The recommended practice for writing
2019  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2020  * alt_write_word() functions.
2021  *
2022  * The struct declaration for register ALT_SYSMGR_NAND_L3MST.
2023  */
2024 struct ALT_SYSMGR_NAND_L3MST_s
2025 {
2026  uint32_t arcache_0 : 4; /* NAND ARCACHE */
2027  uint32_t awcache_0 : 4; /* NAND AWCACHE */
2028  uint32_t : 24; /* *UNDEFINED* */
2029 };
2030 
2031 /* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */
2032 typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t;
2033 #endif /* __ASSEMBLY__ */
2034 
2035 /* The reset value of the ALT_SYSMGR_NAND_L3MST register. */
2036 #define ALT_SYSMGR_NAND_L3MST_RESET 0x00000000
2037 /* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */
2038 #define ALT_SYSMGR_NAND_L3MST_OFST 0x34
2039 
2040 /*
2041  * Register : USB L3 Master HPROT Register - usb0_l3master
2042  *
2043  * Controls the L3 master HPROT AHB-Lite signal.
2044  *
2045  * These register bits should be updated only during system initialization prior to
2046  * removing the peripheral from reset. They may not be changed dynamically during
2047  * peripheral operation
2048  *
2049  * All fields are reset by a cold or warm reset.
2050  *
2051  * Register Layout
2052  *
2053  * Bits | Access | Reset | Description
2054  * :-------|:-------|:------|:----------------------------
2055  * [3:0] | RW | 0x1 | ALT_SYSMGR_USB0_L3MST_HPROT
2056  * [31:4] | ??? | 0x0 | *UNDEFINED*
2057  *
2058  */
2059 /*
2060  * Field : hprot
2061  *
2062  * Defines HPROT[4:1]. HPROT[0] from usb is tied HIGH allow only data access.
2063  *
2064  * ==========================
2065  *
2066  * HPROT[4] Allocate
2067  *
2068  * 0: L3 master accesses for the module are non-allocatable
2069  *
2070  * 1: L3 master accesses for the module are allocatable
2071  *
2072  * ==========================
2073  *
2074  * HPROT[3] Cachable
2075  *
2076  * 0: L3 master accesses for the module are non-cacheable.
2077  *
2078  * 1: L3 master accesses for the module are cacheable.
2079  *
2080  * ==========================
2081  *
2082  * HPROT[2] Bufferable
2083  *
2084  * 0: L3 master accesses for the module are not bufferable.
2085  *
2086  * 1: L3 master accesses for the module are bufferable.
2087  *
2088  * ==========================
2089  *
2090  * HPROT[1] Privileged
2091  *
2092  * 0: L3 master accesses for the module are not privileged.
2093  *
2094  * 1: L3 master accesses for the module are privileged.
2095  *
2096  * ==========================
2097  *
2098  * Field Access Macros:
2099  *
2100  */
2101 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB0_L3MST_HPROT register field. */
2102 #define ALT_SYSMGR_USB0_L3MST_HPROT_LSB 0
2103 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB0_L3MST_HPROT register field. */
2104 #define ALT_SYSMGR_USB0_L3MST_HPROT_MSB 3
2105 /* The width in bits of the ALT_SYSMGR_USB0_L3MST_HPROT register field. */
2106 #define ALT_SYSMGR_USB0_L3MST_HPROT_WIDTH 4
2107 /* The mask used to set the ALT_SYSMGR_USB0_L3MST_HPROT register field value. */
2108 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET_MSK 0x0000000f
2109 /* The mask used to clear the ALT_SYSMGR_USB0_L3MST_HPROT register field value. */
2110 #define ALT_SYSMGR_USB0_L3MST_HPROT_CLR_MSK 0xfffffff0
2111 /* The reset value of the ALT_SYSMGR_USB0_L3MST_HPROT register field. */
2112 #define ALT_SYSMGR_USB0_L3MST_HPROT_RESET 0x1
2113 /* Extracts the ALT_SYSMGR_USB0_L3MST_HPROT field value from a register. */
2114 #define ALT_SYSMGR_USB0_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2115 /* Produces a ALT_SYSMGR_USB0_L3MST_HPROT register field value suitable for setting the register. */
2116 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2117 
2118 #ifndef __ASSEMBLY__
2119 /*
2120  * WARNING: The C register and register group struct declarations are provided for
2121  * convenience and illustrative purposes. They should, however, be used with
2122  * caution as the C language standard provides no guarantees about the alignment or
2123  * atomicity of device memory accesses. The recommended practice for writing
2124  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2125  * alt_write_word() functions.
2126  *
2127  * The struct declaration for register ALT_SYSMGR_USB0_L3MST.
2128  */
2129 struct ALT_SYSMGR_USB0_L3MST_s
2130 {
2131  uint32_t hprot : 4; /* ALT_SYSMGR_USB0_L3MST_HPROT */
2132  uint32_t : 28; /* *UNDEFINED* */
2133 };
2134 
2135 /* The typedef declaration for register ALT_SYSMGR_USB0_L3MST. */
2136 typedef volatile struct ALT_SYSMGR_USB0_L3MST_s ALT_SYSMGR_USB0_L3MST_t;
2137 #endif /* __ASSEMBLY__ */
2138 
2139 /* The reset value of the ALT_SYSMGR_USB0_L3MST register. */
2140 #define ALT_SYSMGR_USB0_L3MST_RESET 0x00000001
2141 /* The byte offset of the ALT_SYSMGR_USB0_L3MST register from the beginning of the component. */
2142 #define ALT_SYSMGR_USB0_L3MST_OFST 0x38
2143 
2144 /*
2145  * Register : USB L3 Master HPROT Register - usb1_l3master
2146  *
2147  * Controls the L3 master HPROT AHB-Lite signal.
2148  *
2149  * These register bits should be updated only during system initialization prior to
2150  * removing the peripheral from reset. They may not be changed dynamically during
2151  * peripheral operation
2152  *
2153  * All fields are reset by a cold or warm reset.
2154  *
2155  * Register Layout
2156  *
2157  * Bits | Access | Reset | Description
2158  * :-------|:-------|:------|:----------------------------
2159  * [3:0] | RW | 0x1 | ALT_SYSMGR_USB1_L3MST_HPROT
2160  * [31:4] | ??? | 0x0 | *UNDEFINED*
2161  *
2162  */
2163 /*
2164  * Field : hprot
2165  *
2166  * Defines HPROT[4:1]. HPROT[0] from usb is tied HIGH to allow only data access.
2167  *
2168  * ==========================
2169  *
2170  * HPROT[4] Allocate
2171  *
2172  * 0: L3 master accesses for the module are non-allocatable
2173  *
2174  * 1: L3 master accesses for the module are allocatable
2175  *
2176  * ==========================
2177  *
2178  * HPROT[3] Cachable
2179  *
2180  * 0: L3 master accesses for the module are non-cacheable.
2181  *
2182  * 1: L3 master accesses for the module are cacheable.
2183  *
2184  * ==========================
2185  *
2186  * HPROT[2] Bufferable
2187  *
2188  * 0: L3 master accesses for the module are not bufferable.
2189  *
2190  * 1: L3 master accesses for the module are bufferable.
2191  *
2192  * ==========================
2193  *
2194  * HPROT[1] Privileged
2195  *
2196  * 0: L3 master accesses for the module are not privileged.
2197  *
2198  * 1: L3 master accesses for the module are privileged.
2199  *
2200  * ==========================
2201  *
2202  * Field Access Macros:
2203  *
2204  */
2205 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB1_L3MST_HPROT register field. */
2206 #define ALT_SYSMGR_USB1_L3MST_HPROT_LSB 0
2207 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB1_L3MST_HPROT register field. */
2208 #define ALT_SYSMGR_USB1_L3MST_HPROT_MSB 3
2209 /* The width in bits of the ALT_SYSMGR_USB1_L3MST_HPROT register field. */
2210 #define ALT_SYSMGR_USB1_L3MST_HPROT_WIDTH 4
2211 /* The mask used to set the ALT_SYSMGR_USB1_L3MST_HPROT register field value. */
2212 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET_MSK 0x0000000f
2213 /* The mask used to clear the ALT_SYSMGR_USB1_L3MST_HPROT register field value. */
2214 #define ALT_SYSMGR_USB1_L3MST_HPROT_CLR_MSK 0xfffffff0
2215 /* The reset value of the ALT_SYSMGR_USB1_L3MST_HPROT register field. */
2216 #define ALT_SYSMGR_USB1_L3MST_HPROT_RESET 0x1
2217 /* Extracts the ALT_SYSMGR_USB1_L3MST_HPROT field value from a register. */
2218 #define ALT_SYSMGR_USB1_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2219 /* Produces a ALT_SYSMGR_USB1_L3MST_HPROT register field value suitable for setting the register. */
2220 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2221 
2222 #ifndef __ASSEMBLY__
2223 /*
2224  * WARNING: The C register and register group struct declarations are provided for
2225  * convenience and illustrative purposes. They should, however, be used with
2226  * caution as the C language standard provides no guarantees about the alignment or
2227  * atomicity of device memory accesses. The recommended practice for writing
2228  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2229  * alt_write_word() functions.
2230  *
2231  * The struct declaration for register ALT_SYSMGR_USB1_L3MST.
2232  */
2233 struct ALT_SYSMGR_USB1_L3MST_s
2234 {
2235  uint32_t hprot : 4; /* ALT_SYSMGR_USB1_L3MST_HPROT */
2236  uint32_t : 28; /* *UNDEFINED* */
2237 };
2238 
2239 /* The typedef declaration for register ALT_SYSMGR_USB1_L3MST. */
2240 typedef volatile struct ALT_SYSMGR_USB1_L3MST_s ALT_SYSMGR_USB1_L3MST_t;
2241 #endif /* __ASSEMBLY__ */
2242 
2243 /* The reset value of the ALT_SYSMGR_USB1_L3MST register. */
2244 #define ALT_SYSMGR_USB1_L3MST_RESET 0x00000001
2245 /* The byte offset of the ALT_SYSMGR_USB1_L3MST register from the beginning of the component. */
2246 #define ALT_SYSMGR_USB1_L3MST_OFST 0x3c
2247 
2248 /*
2249  * Register : EMAC L3 Master AxCACHE Register - emac_global
2250  *
2251  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
2252  *
2253  * These register bits should be updated only during system initialization prior to
2254  * removing the peripheral from reset. They may not be changed dynamically during
2255  * peripheral operation
2256  *
2257  * All fields are reset by a cold or warm reset.
2258  *
2259  * Register Layout
2260  *
2261  * Bits | Access | Reset | Description
2262  * :-------|:-------|:------|:-----------------
2263  * [0] | RW | 0x0 | PTP Clock Select
2264  * [31:1] | ??? | 0x0 | *UNDEFINED*
2265  *
2266  */
2267 /*
2268  * Field : PTP Clock Select - ptp_clk_sel
2269  *
2270  * Selects the source of the PTP reference clock between emac_ptp_clk from the
2271  * Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric.
2272  *
2273  * Field Enumeration Values:
2274  *
2275  * Enum | Value | Description
2276  * :---------------------------------------------------|:------|:------------
2277  * ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK | 0x0 |
2278  * ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK | 0x1 |
2279  *
2280  * Field Access Macros:
2281  *
2282  */
2283 /*
2284  * Enumerated value for register field ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL
2285  *
2286  */
2287 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK 0x0
2288 /*
2289  * Enumerated value for register field ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL
2290  *
2291  */
2292 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK 0x1
2293 
2294 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field. */
2295 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_LSB 0
2296 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field. */
2297 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_MSB 0
2298 /* The width in bits of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field. */
2299 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_WIDTH 1
2300 /* The mask used to set the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value. */
2301 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET_MSK 0x00000001
2302 /* The mask used to clear the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value. */
2303 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_CLR_MSK 0xfffffffe
2304 /* The reset value of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field. */
2305 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_RESET 0x0
2306 /* Extracts the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL field value from a register. */
2307 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_GET(value) (((value) & 0x00000001) >> 0)
2308 /* Produces a ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value suitable for setting the register. */
2309 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET(value) (((value) << 0) & 0x00000001)
2310 
2311 #ifndef __ASSEMBLY__
2312 /*
2313  * WARNING: The C register and register group struct declarations are provided for
2314  * convenience and illustrative purposes. They should, however, be used with
2315  * caution as the C language standard provides no guarantees about the alignment or
2316  * atomicity of device memory accesses. The recommended practice for writing
2317  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2318  * alt_write_word() functions.
2319  *
2320  * The struct declaration for register ALT_SYSMGR_EMAC_GLOB.
2321  */
2322 struct ALT_SYSMGR_EMAC_GLOB_s
2323 {
2324  uint32_t ptp_clk_sel : 1; /* PTP Clock Select */
2325  uint32_t : 31; /* *UNDEFINED* */
2326 };
2327 
2328 /* The typedef declaration for register ALT_SYSMGR_EMAC_GLOB. */
2329 typedef volatile struct ALT_SYSMGR_EMAC_GLOB_s ALT_SYSMGR_EMAC_GLOB_t;
2330 #endif /* __ASSEMBLY__ */
2331 
2332 /* The reset value of the ALT_SYSMGR_EMAC_GLOB register. */
2333 #define ALT_SYSMGR_EMAC_GLOB_RESET 0x00000000
2334 /* The byte offset of the ALT_SYSMGR_EMAC_GLOB register from the beginning of the component. */
2335 #define ALT_SYSMGR_EMAC_GLOB_OFST 0x40
2336 
2337 /*
2338  * Register : Control Register - emac0
2339  *
2340  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
2341  *
2342  * Register Layout
2343  *
2344  * Bits | Access | Reset | Description
2345  * :--------|:-------|:------|:-------------------------------------
2346  * [1:0] | RW | 0x3 | ALT_SYSMGR_EMAC0_PHY_INTF_SEL
2347  * [7:2] | ??? | 0x0 | *UNDEFINED*
2348  * [8] | RW | 0x0 | ALT_SYSMGR_EMAC0_PTP_REF_SEL
2349  * [11:9] | ??? | 0x0 | *UNDEFINED*
2350  * [12] | RW | 0x0 | ALT_SYSMGR_EMAC0_APP_CLK_SEL
2351  * [15:13] | ??? | 0x0 | *UNDEFINED*
2352  * [19:16] | RW | 0x0 | ALT_SYSMGR_EMAC0_ARCACHE
2353  * [23:20] | RW | 0x0 | ALT_SYSMGR_EMAC0_AWCACHE
2354  * [25:24] | RW | 0x2 | ALT_SYSMGR_EMAC0_ARPROT
2355  * [26] | ??? | 0x0 | *UNDEFINED*
2356  * [28:27] | RW | 0x2 | ALT_SYSMGR_EMAC0_AWPROT
2357  * [29] | ??? | 0x0 | *UNDEFINED*
2358  * [30] | RW | 0x0 | ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS
2359  * [31] | RW | 0x0 | ALT_SYSMGR_EMAC0_AXI_DIS
2360  *
2361  */
2362 /*
2363  * Field : phy_intf_sel
2364  *
2365  * PHY Interface Select
2366  *
2367  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
2368  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
2369  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
2370  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
2371  * clocks use the Clock Manager reference rather than depending on the PHY to have
2372  * active clocks.
2373  *
2374  * Field Enumeration Values:
2375  *
2376  * Enum | Value | Description
2377  * :-----------------------------------------|:------|:------------
2378  * ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_GMII_MII | 0x0 |
2379  * ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII | 0x1 |
2380  * ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RMII | 0x2 |
2381  * ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RST | 0x3 |
2382  *
2383  * Field Access Macros:
2384  *
2385  */
2386 /*
2387  * Enumerated value for register field ALT_SYSMGR_EMAC0_PHY_INTF_SEL
2388  *
2389  */
2390 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_GMII_MII 0x0
2391 /*
2392  * Enumerated value for register field ALT_SYSMGR_EMAC0_PHY_INTF_SEL
2393  *
2394  */
2395 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
2396 /*
2397  * Enumerated value for register field ALT_SYSMGR_EMAC0_PHY_INTF_SEL
2398  *
2399  */
2400 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RMII 0x2
2401 /*
2402  * Enumerated value for register field ALT_SYSMGR_EMAC0_PHY_INTF_SEL
2403  *
2404  */
2405 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RST 0x3
2406 
2407 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field. */
2408 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_LSB 0
2409 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field. */
2410 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_MSB 1
2411 /* The width in bits of the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field. */
2412 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_WIDTH 2
2413 /* The mask used to set the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field value. */
2414 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
2415 /* The mask used to clear the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field value. */
2416 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_CLR_MSK 0xfffffffc
2417 /* The reset value of the ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field. */
2418 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_RESET 0x3
2419 /* Extracts the ALT_SYSMGR_EMAC0_PHY_INTF_SEL field value from a register. */
2420 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
2421 /* Produces a ALT_SYSMGR_EMAC0_PHY_INTF_SEL register field value suitable for setting the register. */
2422 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
2423 
2424 /*
2425  * Field : ptp_ref_sel
2426  *
2427  * This field selects if the Timestamp reference is internally or externally
2428  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
2429  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
2430  * Internal or External.
2431  *
2432  * Field Enumeration Values:
2433  *
2434  * Enum | Value | Description
2435  * :----------------------------------------|:------|:------------
2436  * ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_INTERNAL | 0x0 |
2437  * ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_EXTERNAL | 0x1 |
2438  *
2439  * Field Access Macros:
2440  *
2441  */
2442 /*
2443  * Enumerated value for register field ALT_SYSMGR_EMAC0_PTP_REF_SEL
2444  *
2445  */
2446 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_INTERNAL 0x0
2447 /*
2448  * Enumerated value for register field ALT_SYSMGR_EMAC0_PTP_REF_SEL
2449  *
2450  */
2451 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_EXTERNAL 0x1
2452 
2453 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field. */
2454 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_LSB 8
2455 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field. */
2456 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_MSB 8
2457 /* The width in bits of the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field. */
2458 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_WIDTH 1
2459 /* The mask used to set the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field value. */
2460 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET_MSK 0x00000100
2461 /* The mask used to clear the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field value. */
2462 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_CLR_MSK 0xfffffeff
2463 /* The reset value of the ALT_SYSMGR_EMAC0_PTP_REF_SEL register field. */
2464 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_RESET 0x0
2465 /* Extracts the ALT_SYSMGR_EMAC0_PTP_REF_SEL field value from a register. */
2466 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
2467 /* Produces a ALT_SYSMGR_EMAC0_PTP_REF_SEL register field value suitable for setting the register. */
2468 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
2469 
2470 /*
2471  * Field : app_clk_sel
2472  *
2473  * Selects the source of the Application clock for the datapath to either l4_mp_clk
2474  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
2475  * the FPGA fabric.
2476  *
2477  * Field Enumeration Values:
2478  *
2479  * Enum | Value | Description
2480  * :------------------------------------------|:------|:------------
2481  * ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
2482  * ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
2483  *
2484  * Field Access Macros:
2485  *
2486  */
2487 /*
2488  * Enumerated value for register field ALT_SYSMGR_EMAC0_APP_CLK_SEL
2489  *
2490  */
2491 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_L4_MP_CLK 0x0
2492 /*
2493  * Enumerated value for register field ALT_SYSMGR_EMAC0_APP_CLK_SEL
2494  *
2495  */
2496 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK 0x1
2497 
2498 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field. */
2499 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_LSB 12
2500 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field. */
2501 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_MSB 12
2502 /* The width in bits of the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field. */
2503 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_WIDTH 1
2504 /* The mask used to set the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field value. */
2505 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET_MSK 0x00001000
2506 /* The mask used to clear the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field value. */
2507 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_CLR_MSK 0xffffefff
2508 /* The reset value of the ALT_SYSMGR_EMAC0_APP_CLK_SEL register field. */
2509 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_RESET 0x0
2510 /* Extracts the ALT_SYSMGR_EMAC0_APP_CLK_SEL field value from a register. */
2511 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
2512 /* Produces a ALT_SYSMGR_EMAC0_APP_CLK_SEL register field value suitable for setting the register. */
2513 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
2514 
2515 /*
2516  * Field : arcache
2517  *
2518  * Specifies the values of the 2 EMAC ARCACHE signals.
2519  *
2520  * The field array index corresponds to the EMAC index.
2521  *
2522  * Field Enumeration Values:
2523  *
2524  * Enum | Value | Description
2525  * :------------------------------------------------|:------|:------------
2526  * ALT_SYSMGR_EMAC0_ARCACHE_E_NONCACHE_NONBUFF | 0x0 |
2527  * ALT_SYSMGR_EMAC0_ARCACHE_E_BUFF | 0x1 |
2528  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_NONALLOC | 0x2 |
2529  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
2530  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD1 | 0x4 |
2531  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD2 | 0x5 |
2532  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
2533  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
2534  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD3 | 0x8 |
2535  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD4 | 0x9 |
2536  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
2537  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
2538  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD5 | 0xc |
2539  * ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD6 | 0xd |
2540  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
2541  * ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
2542  *
2543  * Field Access Macros:
2544  *
2545  */
2546 /*
2547  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2548  *
2549  */
2550 #define ALT_SYSMGR_EMAC0_ARCACHE_E_NONCACHE_NONBUFF 0x0
2551 /*
2552  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2553  *
2554  */
2555 #define ALT_SYSMGR_EMAC0_ARCACHE_E_BUFF 0x1
2556 /*
2557  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2558  *
2559  */
2560 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_NONALLOC 0x2
2561 /*
2562  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2563  *
2564  */
2565 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
2566 /*
2567  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2568  *
2569  */
2570 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD1 0x4
2571 /*
2572  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2573  *
2574  */
2575 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD2 0x5
2576 /*
2577  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2578  *
2579  */
2580 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2581 /*
2582  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2583  *
2584  */
2585 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2586 /*
2587  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2588  *
2589  */
2590 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD3 0x8
2591 /*
2592  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2593  *
2594  */
2595 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD4 0x9
2596 /*
2597  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2598  *
2599  */
2600 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2601 /*
2602  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2603  *
2604  */
2605 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2606 /*
2607  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2608  *
2609  */
2610 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD5 0xc
2611 /*
2612  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2613  *
2614  */
2615 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD6 0xd
2616 /*
2617  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2618  *
2619  */
2620 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2621 /*
2622  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARCACHE
2623  *
2624  */
2625 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
2626 
2627 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_ARCACHE register field. */
2628 #define ALT_SYSMGR_EMAC0_ARCACHE_LSB 16
2629 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_ARCACHE register field. */
2630 #define ALT_SYSMGR_EMAC0_ARCACHE_MSB 19
2631 /* The width in bits of the ALT_SYSMGR_EMAC0_ARCACHE register field. */
2632 #define ALT_SYSMGR_EMAC0_ARCACHE_WIDTH 4
2633 /* The mask used to set the ALT_SYSMGR_EMAC0_ARCACHE register field value. */
2634 #define ALT_SYSMGR_EMAC0_ARCACHE_SET_MSK 0x000f0000
2635 /* The mask used to clear the ALT_SYSMGR_EMAC0_ARCACHE register field value. */
2636 #define ALT_SYSMGR_EMAC0_ARCACHE_CLR_MSK 0xfff0ffff
2637 /* The reset value of the ALT_SYSMGR_EMAC0_ARCACHE register field. */
2638 #define ALT_SYSMGR_EMAC0_ARCACHE_RESET 0x0
2639 /* Extracts the ALT_SYSMGR_EMAC0_ARCACHE field value from a register. */
2640 #define ALT_SYSMGR_EMAC0_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
2641 /* Produces a ALT_SYSMGR_EMAC0_ARCACHE register field value suitable for setting the register. */
2642 #define ALT_SYSMGR_EMAC0_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
2643 
2644 /*
2645  * Field : awcache
2646  *
2647  * Specifies the values of the 2 EMAC AWCACHE signals.
2648  *
2649  * The field array index corresponds to the EMAC index.
2650  *
2651  * Field Enumeration Values:
2652  *
2653  * Enum | Value | Description
2654  * :------------------------------------------------|:------|:------------
2655  * ALT_SYSMGR_EMAC0_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
2656  * ALT_SYSMGR_EMAC0_AWCACHE_E_BUFF | 0x1 |
2657  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_NONALLOC | 0x2 |
2658  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
2659  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD1 | 0x4 |
2660  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD2 | 0x5 |
2661  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
2662  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
2663  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD3 | 0x8 |
2664  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD4 | 0x9 |
2665  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
2666  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
2667  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD5 | 0xc |
2668  * ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD6 | 0xd |
2669  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
2670  * ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
2671  *
2672  * Field Access Macros:
2673  *
2674  */
2675 /*
2676  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2677  *
2678  */
2679 #define ALT_SYSMGR_EMAC0_AWCACHE_E_NONCACHE_NONBUFF 0x0
2680 /*
2681  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2682  *
2683  */
2684 #define ALT_SYSMGR_EMAC0_AWCACHE_E_BUFF 0x1
2685 /*
2686  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2687  *
2688  */
2689 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_NONALLOC 0x2
2690 /*
2691  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2692  *
2693  */
2694 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
2695 /*
2696  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2697  *
2698  */
2699 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD1 0x4
2700 /*
2701  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2702  *
2703  */
2704 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD2 0x5
2705 /*
2706  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2707  *
2708  */
2709 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2710 /*
2711  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2712  *
2713  */
2714 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2715 /*
2716  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2717  *
2718  */
2719 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD3 0x8
2720 /*
2721  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2722  *
2723  */
2724 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD4 0x9
2725 /*
2726  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2727  *
2728  */
2729 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2730 /*
2731  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2732  *
2733  */
2734 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2735 /*
2736  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2737  *
2738  */
2739 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD5 0xc
2740 /*
2741  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2742  *
2743  */
2744 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD6 0xd
2745 /*
2746  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2747  *
2748  */
2749 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2750 /*
2751  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWCACHE
2752  *
2753  */
2754 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
2755 
2756 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_AWCACHE register field. */
2757 #define ALT_SYSMGR_EMAC0_AWCACHE_LSB 20
2758 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_AWCACHE register field. */
2759 #define ALT_SYSMGR_EMAC0_AWCACHE_MSB 23
2760 /* The width in bits of the ALT_SYSMGR_EMAC0_AWCACHE register field. */
2761 #define ALT_SYSMGR_EMAC0_AWCACHE_WIDTH 4
2762 /* The mask used to set the ALT_SYSMGR_EMAC0_AWCACHE register field value. */
2763 #define ALT_SYSMGR_EMAC0_AWCACHE_SET_MSK 0x00f00000
2764 /* The mask used to clear the ALT_SYSMGR_EMAC0_AWCACHE register field value. */
2765 #define ALT_SYSMGR_EMAC0_AWCACHE_CLR_MSK 0xff0fffff
2766 /* The reset value of the ALT_SYSMGR_EMAC0_AWCACHE register field. */
2767 #define ALT_SYSMGR_EMAC0_AWCACHE_RESET 0x0
2768 /* Extracts the ALT_SYSMGR_EMAC0_AWCACHE field value from a register. */
2769 #define ALT_SYSMGR_EMAC0_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
2770 /* Produces a ALT_SYSMGR_EMAC0_AWCACHE register field value suitable for setting the register. */
2771 #define ALT_SYSMGR_EMAC0_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
2772 
2773 /*
2774  * Field : arprot
2775  *
2776  * Specifies the values of the ARPROT signals.
2777  *
2778  * ==========================
2779  *
2780  * AxPROT[1]
2781  *
2782  * LOW: Secure Access
2783  *
2784  * HIGH: NonSecure Access
2785  *
2786  * ==========================
2787  *
2788  * AxPROT[0]
2789  *
2790  * LOW: Normal Access
2791  *
2792  * HIGH: Privileged Access
2793  *
2794  * ==========================
2795  *
2796  * Field Enumeration Values:
2797  *
2798  * Enum | Value | Description
2799  * :-----------------------------------------------|:------|:------------
2800  * ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_NORMAL | 0x0 |
2801  * ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
2802  * ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_NORMAL | 0x2 |
2803  * ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
2804  *
2805  * Field Access Macros:
2806  *
2807  */
2808 /*
2809  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARPROT
2810  *
2811  * Secure Normal(non-privileged) access
2812  */
2813 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_NORMAL 0x0
2814 /*
2815  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARPROT
2816  *
2817  * Secure Privileged access
2818  */
2819 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_PRIVILEGED 0x1
2820 /*
2821  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARPROT
2822  *
2823  * Non-Secure Normal(non-privileged) access
2824  */
2825 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_NORMAL 0x2
2826 /*
2827  * Enumerated value for register field ALT_SYSMGR_EMAC0_ARPROT
2828  *
2829  * Non-Secure Privileged access
2830  */
2831 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED 0x3
2832 
2833 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_ARPROT register field. */
2834 #define ALT_SYSMGR_EMAC0_ARPROT_LSB 24
2835 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_ARPROT register field. */
2836 #define ALT_SYSMGR_EMAC0_ARPROT_MSB 25
2837 /* The width in bits of the ALT_SYSMGR_EMAC0_ARPROT register field. */
2838 #define ALT_SYSMGR_EMAC0_ARPROT_WIDTH 2
2839 /* The mask used to set the ALT_SYSMGR_EMAC0_ARPROT register field value. */
2840 #define ALT_SYSMGR_EMAC0_ARPROT_SET_MSK 0x03000000
2841 /* The mask used to clear the ALT_SYSMGR_EMAC0_ARPROT register field value. */
2842 #define ALT_SYSMGR_EMAC0_ARPROT_CLR_MSK 0xfcffffff
2843 /* The reset value of the ALT_SYSMGR_EMAC0_ARPROT register field. */
2844 #define ALT_SYSMGR_EMAC0_ARPROT_RESET 0x2
2845 /* Extracts the ALT_SYSMGR_EMAC0_ARPROT field value from a register. */
2846 #define ALT_SYSMGR_EMAC0_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
2847 /* Produces a ALT_SYSMGR_EMAC0_ARPROT register field value suitable for setting the register. */
2848 #define ALT_SYSMGR_EMAC0_ARPROT_SET(value) (((value) << 24) & 0x03000000)
2849 
2850 /*
2851  * Field : awprot
2852  *
2853  * Specifies the values of the 2 EMAC AWCACHE signals.
2854  *
2855  * ==========================
2856  *
2857  * AxPROT[1]
2858  *
2859  * LOW: Secure Access
2860  *
2861  * HIGH: NonSecure Access
2862  *
2863  * ==========================
2864  *
2865  * AxPROT[0]
2866  *
2867  * LOW: Normal Access
2868  *
2869  * HIGH: Privileged Access
2870  *
2871  * ==========================
2872  *
2873  * Field Enumeration Values:
2874  *
2875  * Enum | Value | Description
2876  * :-----------------------------------------------|:------|:------------
2877  * ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_NORMAL | 0x0 |
2878  * ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
2879  * ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_NORMAL | 0x2 |
2880  * ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
2881  *
2882  * Field Access Macros:
2883  *
2884  */
2885 /*
2886  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWPROT
2887  *
2888  * Secure Normal(non-privileged) access
2889  */
2890 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_NORMAL 0x0
2891 /*
2892  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWPROT
2893  *
2894  * Secure Privileged access
2895  */
2896 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_PRIVILEGED 0x1
2897 /*
2898  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWPROT
2899  *
2900  * Non-Secure Normal(non-privileged) access
2901  */
2902 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_NORMAL 0x2
2903 /*
2904  * Enumerated value for register field ALT_SYSMGR_EMAC0_AWPROT
2905  *
2906  * Non-Secure Privileged access
2907  */
2908 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED 0x3
2909 
2910 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_AWPROT register field. */
2911 #define ALT_SYSMGR_EMAC0_AWPROT_LSB 27
2912 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_AWPROT register field. */
2913 #define ALT_SYSMGR_EMAC0_AWPROT_MSB 28
2914 /* The width in bits of the ALT_SYSMGR_EMAC0_AWPROT register field. */
2915 #define ALT_SYSMGR_EMAC0_AWPROT_WIDTH 2
2916 /* The mask used to set the ALT_SYSMGR_EMAC0_AWPROT register field value. */
2917 #define ALT_SYSMGR_EMAC0_AWPROT_SET_MSK 0x18000000
2918 /* The mask used to clear the ALT_SYSMGR_EMAC0_AWPROT register field value. */
2919 #define ALT_SYSMGR_EMAC0_AWPROT_CLR_MSK 0xe7ffffff
2920 /* The reset value of the ALT_SYSMGR_EMAC0_AWPROT register field. */
2921 #define ALT_SYSMGR_EMAC0_AWPROT_RESET 0x2
2922 /* Extracts the ALT_SYSMGR_EMAC0_AWPROT field value from a register. */
2923 #define ALT_SYSMGR_EMAC0_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
2924 /* Produces a ALT_SYSMGR_EMAC0_AWPROT register field value suitable for setting the register. */
2925 #define ALT_SYSMGR_EMAC0_AWPROT_SET(value) (((value) << 27) & 0x18000000)
2926 
2927 /*
2928  * Field : sbd_data_endianness
2929  *
2930  * Specifies the endianness of the EMAC DMA transfers.
2931  *
2932  * The field array index corresponds to the EMAC index.
2933  *
2934  * Field Enumeration Values:
2935  *
2936  * Enum | Value | Description
2937  * :-----------------------------------------------------|:------|:------------
2938  * ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
2939  * ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
2940  *
2941  * Field Access Macros:
2942  *
2943  */
2944 /*
2945  * Enumerated value for register field ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS
2946  *
2947  */
2948 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
2949 /*
2950  * Enumerated value for register field ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS
2951  *
2952  */
2953 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
2954 
2955 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field. */
2956 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_LSB 30
2957 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field. */
2958 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_MSB 30
2959 /* The width in bits of the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field. */
2960 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_WIDTH 1
2961 /* The mask used to set the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field value. */
2962 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
2963 /* The mask used to clear the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field value. */
2964 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
2965 /* The reset value of the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field. */
2966 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_RESET 0x0
2967 /* Extracts the ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS field value from a register. */
2968 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
2969 /* Produces a ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
2970 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
2971 
2972 /*
2973  * Field : axi_disable
2974  *
2975  * AXI Disable
2976  *
2977  * Field Access Macros:
2978  *
2979  */
2980 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC0_AXI_DIS register field. */
2981 #define ALT_SYSMGR_EMAC0_AXI_DIS_LSB 31
2982 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC0_AXI_DIS register field. */
2983 #define ALT_SYSMGR_EMAC0_AXI_DIS_MSB 31
2984 /* The width in bits of the ALT_SYSMGR_EMAC0_AXI_DIS register field. */
2985 #define ALT_SYSMGR_EMAC0_AXI_DIS_WIDTH 1
2986 /* The mask used to set the ALT_SYSMGR_EMAC0_AXI_DIS register field value. */
2987 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET_MSK 0x80000000
2988 /* The mask used to clear the ALT_SYSMGR_EMAC0_AXI_DIS register field value. */
2989 #define ALT_SYSMGR_EMAC0_AXI_DIS_CLR_MSK 0x7fffffff
2990 /* The reset value of the ALT_SYSMGR_EMAC0_AXI_DIS register field. */
2991 #define ALT_SYSMGR_EMAC0_AXI_DIS_RESET 0x0
2992 /* Extracts the ALT_SYSMGR_EMAC0_AXI_DIS field value from a register. */
2993 #define ALT_SYSMGR_EMAC0_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
2994 /* Produces a ALT_SYSMGR_EMAC0_AXI_DIS register field value suitable for setting the register. */
2995 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
2996 
2997 #ifndef __ASSEMBLY__
2998 /*
2999  * WARNING: The C register and register group struct declarations are provided for
3000  * convenience and illustrative purposes. They should, however, be used with
3001  * caution as the C language standard provides no guarantees about the alignment or
3002  * atomicity of device memory accesses. The recommended practice for writing
3003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3004  * alt_write_word() functions.
3005  *
3006  * The struct declaration for register ALT_SYSMGR_EMAC0.
3007  */
3008 struct ALT_SYSMGR_EMAC0_s
3009 {
3010  uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_EMAC0_PHY_INTF_SEL */
3011  uint32_t : 6; /* *UNDEFINED* */
3012  uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_EMAC0_PTP_REF_SEL */
3013  uint32_t : 3; /* *UNDEFINED* */
3014  uint32_t app_clk_sel : 1; /* ALT_SYSMGR_EMAC0_APP_CLK_SEL */
3015  uint32_t : 3; /* *UNDEFINED* */
3016  uint32_t arcache : 4; /* ALT_SYSMGR_EMAC0_ARCACHE */
3017  uint32_t awcache : 4; /* ALT_SYSMGR_EMAC0_AWCACHE */
3018  uint32_t arprot : 2; /* ALT_SYSMGR_EMAC0_ARPROT */
3019  uint32_t : 1; /* *UNDEFINED* */
3020  uint32_t awprot : 2; /* ALT_SYSMGR_EMAC0_AWPROT */
3021  uint32_t : 1; /* *UNDEFINED* */
3022  uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS */
3023  uint32_t axi_disable : 1; /* ALT_SYSMGR_EMAC0_AXI_DIS */
3024 };
3025 
3026 /* The typedef declaration for register ALT_SYSMGR_EMAC0. */
3027 typedef volatile struct ALT_SYSMGR_EMAC0_s ALT_SYSMGR_EMAC0_t;
3028 #endif /* __ASSEMBLY__ */
3029 
3030 /* The reset value of the ALT_SYSMGR_EMAC0 register. */
3031 #define ALT_SYSMGR_EMAC0_RESET 0x12000003
3032 /* The byte offset of the ALT_SYSMGR_EMAC0 register from the beginning of the component. */
3033 #define ALT_SYSMGR_EMAC0_OFST 0x44
3034 
3035 /*
3036  * Register : Control Register - emac1
3037  *
3038  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
3039  *
3040  * Register Layout
3041  *
3042  * Bits | Access | Reset | Description
3043  * :--------|:-------|:------|:-------------------------------------
3044  * [1:0] | RW | 0x3 | ALT_SYSMGR_EMAC1_PHY_INTF_SEL
3045  * [7:2] | ??? | 0x0 | *UNDEFINED*
3046  * [8] | RW | 0x0 | ALT_SYSMGR_EMAC1_PTP_REF_SEL
3047  * [11:9] | ??? | 0x0 | *UNDEFINED*
3048  * [12] | RW | 0x0 | ALT_SYSMGR_EMAC1_APP_CLK_SEL
3049  * [15:13] | ??? | 0x0 | *UNDEFINED*
3050  * [19:16] | RW | 0x0 | ALT_SYSMGR_EMAC1_ARCACHE
3051  * [23:20] | RW | 0x0 | ALT_SYSMGR_EMAC1_AWCACHE
3052  * [25:24] | RW | 0x2 | ALT_SYSMGR_EMAC1_ARPROT
3053  * [26] | ??? | 0x0 | *UNDEFINED*
3054  * [28:27] | RW | 0x2 | ALT_SYSMGR_EMAC1_AWPROT
3055  * [29] | ??? | 0x0 | *UNDEFINED*
3056  * [30] | RW | 0x0 | ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS
3057  * [31] | RW | 0x0 | ALT_SYSMGR_EMAC1_AXI_DIS
3058  *
3059  */
3060 /*
3061  * Field : phy_intf_sel
3062  *
3063  * PHY Interface Select
3064  *
3065  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
3066  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
3067  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
3068  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
3069  * clocks use the Clock Manager reference rather than depending on the PHY to have
3070  * active clocks.
3071  *
3072  * Field Enumeration Values:
3073  *
3074  * Enum | Value | Description
3075  * :-----------------------------------------|:------|:------------
3076  * ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_GMII_MII | 0x0 |
3077  * ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII | 0x1 |
3078  * ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RMII | 0x2 |
3079  * ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RST | 0x3 |
3080  *
3081  * Field Access Macros:
3082  *
3083  */
3084 /*
3085  * Enumerated value for register field ALT_SYSMGR_EMAC1_PHY_INTF_SEL
3086  *
3087  */
3088 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_GMII_MII 0x0
3089 /*
3090  * Enumerated value for register field ALT_SYSMGR_EMAC1_PHY_INTF_SEL
3091  *
3092  */
3093 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII 0x1
3094 /*
3095  * Enumerated value for register field ALT_SYSMGR_EMAC1_PHY_INTF_SEL
3096  *
3097  */
3098 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RMII 0x2
3099 /*
3100  * Enumerated value for register field ALT_SYSMGR_EMAC1_PHY_INTF_SEL
3101  *
3102  */
3103 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RST 0x3
3104 
3105 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field. */
3106 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_LSB 0
3107 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field. */
3108 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_MSB 1
3109 /* The width in bits of the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field. */
3110 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_WIDTH 2
3111 /* The mask used to set the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field value. */
3112 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK 0x00000003
3113 /* The mask used to clear the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field value. */
3114 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3115 /* The reset value of the ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field. */
3116 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_RESET 0x3
3117 /* Extracts the ALT_SYSMGR_EMAC1_PHY_INTF_SEL field value from a register. */
3118 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3119 /* Produces a ALT_SYSMGR_EMAC1_PHY_INTF_SEL register field value suitable for setting the register. */
3120 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3121 
3122 /*
3123  * Field : ptp_ref_sel
3124  *
3125  * This field selects if the Timestamp reference is internally or externally
3126  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
3127  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
3128  * Internal or External.
3129  *
3130  * Field Enumeration Values:
3131  *
3132  * Enum | Value | Description
3133  * :----------------------------------------|:------|:------------
3134  * ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_INTERNAL | 0x0 |
3135  * ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_EXTERNAL | 0x1 |
3136  *
3137  * Field Access Macros:
3138  *
3139  */
3140 /*
3141  * Enumerated value for register field ALT_SYSMGR_EMAC1_PTP_REF_SEL
3142  *
3143  */
3144 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_INTERNAL 0x0
3145 /*
3146  * Enumerated value for register field ALT_SYSMGR_EMAC1_PTP_REF_SEL
3147  *
3148  */
3149 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_EXTERNAL 0x1
3150 
3151 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field. */
3152 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_LSB 8
3153 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field. */
3154 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_MSB 8
3155 /* The width in bits of the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field. */
3156 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_WIDTH 1
3157 /* The mask used to set the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field value. */
3158 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET_MSK 0x00000100
3159 /* The mask used to clear the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field value. */
3160 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_CLR_MSK 0xfffffeff
3161 /* The reset value of the ALT_SYSMGR_EMAC1_PTP_REF_SEL register field. */
3162 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_RESET 0x0
3163 /* Extracts the ALT_SYSMGR_EMAC1_PTP_REF_SEL field value from a register. */
3164 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3165 /* Produces a ALT_SYSMGR_EMAC1_PTP_REF_SEL register field value suitable for setting the register. */
3166 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3167 
3168 /*
3169  * Field : app_clk_sel
3170  *
3171  * Selects the source of the Application clock for the datapath to either l4_mp_clk
3172  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
3173  * the FPGA fabric.
3174  *
3175  * Field Enumeration Values:
3176  *
3177  * Enum | Value | Description
3178  * :------------------------------------------|:------|:------------
3179  * ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
3180  * ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
3181  *
3182  * Field Access Macros:
3183  *
3184  */
3185 /*
3186  * Enumerated value for register field ALT_SYSMGR_EMAC1_APP_CLK_SEL
3187  *
3188  */
3189 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_L4_MP_CLK 0x0
3190 /*
3191  * Enumerated value for register field ALT_SYSMGR_EMAC1_APP_CLK_SEL
3192  *
3193  */
3194 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3195 
3196 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field. */
3197 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_LSB 12
3198 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field. */
3199 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_MSB 12
3200 /* The width in bits of the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field. */
3201 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_WIDTH 1
3202 /* The mask used to set the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field value. */
3203 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET_MSK 0x00001000
3204 /* The mask used to clear the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field value. */
3205 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_CLR_MSK 0xffffefff
3206 /* The reset value of the ALT_SYSMGR_EMAC1_APP_CLK_SEL register field. */
3207 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_RESET 0x0
3208 /* Extracts the ALT_SYSMGR_EMAC1_APP_CLK_SEL field value from a register. */
3209 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3210 /* Produces a ALT_SYSMGR_EMAC1_APP_CLK_SEL register field value suitable for setting the register. */
3211 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3212 
3213 /*
3214  * Field : arcache
3215  *
3216  * Specifies the values of the 2 EMAC ARCACHE signals.
3217  *
3218  * The field array index corresponds to the EMAC index.
3219  *
3220  * Field Enumeration Values:
3221  *
3222  * Enum | Value | Description
3223  * :------------------------------------------------|:------|:------------
3224  * ALT_SYSMGR_EMAC1_ARCACHE_E_NONCACHE_NONBUFF | 0x0 |
3225  * ALT_SYSMGR_EMAC1_ARCACHE_E_BUFF | 0x1 |
3226  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_NONALLOC | 0x2 |
3227  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
3228  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD1 | 0x4 |
3229  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD2 | 0x5 |
3230  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
3231  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
3232  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD3 | 0x8 |
3233  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD4 | 0x9 |
3234  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
3235  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
3236  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD5 | 0xc |
3237  * ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD6 | 0xd |
3238  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
3239  * ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
3240  *
3241  * Field Access Macros:
3242  *
3243  */
3244 /*
3245  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3246  *
3247  */
3248 #define ALT_SYSMGR_EMAC1_ARCACHE_E_NONCACHE_NONBUFF 0x0
3249 /*
3250  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3251  *
3252  */
3253 #define ALT_SYSMGR_EMAC1_ARCACHE_E_BUFF 0x1
3254 /*
3255  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3256  *
3257  */
3258 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_NONALLOC 0x2
3259 /*
3260  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3261  *
3262  */
3263 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3264 /*
3265  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3266  *
3267  */
3268 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD1 0x4
3269 /*
3270  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3271  *
3272  */
3273 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD2 0x5
3274 /*
3275  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3276  *
3277  */
3278 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3279 /*
3280  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3281  *
3282  */
3283 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3284 /*
3285  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3286  *
3287  */
3288 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD3 0x8
3289 /*
3290  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3291  *
3292  */
3293 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD4 0x9
3294 /*
3295  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3296  *
3297  */
3298 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3299 /*
3300  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3301  *
3302  */
3303 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3304 /*
3305  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3306  *
3307  */
3308 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD5 0xc
3309 /*
3310  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3311  *
3312  */
3313 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD6 0xd
3314 /*
3315  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3316  *
3317  */
3318 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3319 /*
3320  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARCACHE
3321  *
3322  */
3323 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
3324 
3325 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_ARCACHE register field. */
3326 #define ALT_SYSMGR_EMAC1_ARCACHE_LSB 16
3327 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_ARCACHE register field. */
3328 #define ALT_SYSMGR_EMAC1_ARCACHE_MSB 19
3329 /* The width in bits of the ALT_SYSMGR_EMAC1_ARCACHE register field. */
3330 #define ALT_SYSMGR_EMAC1_ARCACHE_WIDTH 4
3331 /* The mask used to set the ALT_SYSMGR_EMAC1_ARCACHE register field value. */
3332 #define ALT_SYSMGR_EMAC1_ARCACHE_SET_MSK 0x000f0000
3333 /* The mask used to clear the ALT_SYSMGR_EMAC1_ARCACHE register field value. */
3334 #define ALT_SYSMGR_EMAC1_ARCACHE_CLR_MSK 0xfff0ffff
3335 /* The reset value of the ALT_SYSMGR_EMAC1_ARCACHE register field. */
3336 #define ALT_SYSMGR_EMAC1_ARCACHE_RESET 0x0
3337 /* Extracts the ALT_SYSMGR_EMAC1_ARCACHE field value from a register. */
3338 #define ALT_SYSMGR_EMAC1_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
3339 /* Produces a ALT_SYSMGR_EMAC1_ARCACHE register field value suitable for setting the register. */
3340 #define ALT_SYSMGR_EMAC1_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
3341 
3342 /*
3343  * Field : awcache
3344  *
3345  * Specifies the values of the 2 EMAC AWCACHE signals.
3346  *
3347  * The field array index corresponds to the EMAC index.
3348  *
3349  * Field Enumeration Values:
3350  *
3351  * Enum | Value | Description
3352  * :------------------------------------------------|:------|:------------
3353  * ALT_SYSMGR_EMAC1_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
3354  * ALT_SYSMGR_EMAC1_AWCACHE_E_BUFF | 0x1 |
3355  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_NONALLOC | 0x2 |
3356  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
3357  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD1 | 0x4 |
3358  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD2 | 0x5 |
3359  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
3360  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
3361  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD3 | 0x8 |
3362  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD4 | 0x9 |
3363  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
3364  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
3365  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD5 | 0xc |
3366  * ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD6 | 0xd |
3367  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
3368  * ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
3369  *
3370  * Field Access Macros:
3371  *
3372  */
3373 /*
3374  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3375  *
3376  */
3377 #define ALT_SYSMGR_EMAC1_AWCACHE_E_NONCACHE_NONBUFF 0x0
3378 /*
3379  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3380  *
3381  */
3382 #define ALT_SYSMGR_EMAC1_AWCACHE_E_BUFF 0x1
3383 /*
3384  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3385  *
3386  */
3387 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_NONALLOC 0x2
3388 /*
3389  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3390  *
3391  */
3392 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
3393 /*
3394  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3395  *
3396  */
3397 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD1 0x4
3398 /*
3399  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3400  *
3401  */
3402 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD2 0x5
3403 /*
3404  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3405  *
3406  */
3407 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3408 /*
3409  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3410  *
3411  */
3412 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3413 /*
3414  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3415  *
3416  */
3417 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD3 0x8
3418 /*
3419  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3420  *
3421  */
3422 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD4 0x9
3423 /*
3424  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3425  *
3426  */
3427 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3428 /*
3429  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3430  *
3431  */
3432 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3433 /*
3434  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3435  *
3436  */
3437 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD5 0xc
3438 /*
3439  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3440  *
3441  */
3442 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD6 0xd
3443 /*
3444  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3445  *
3446  */
3447 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3448 /*
3449  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWCACHE
3450  *
3451  */
3452 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
3453 
3454 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_AWCACHE register field. */
3455 #define ALT_SYSMGR_EMAC1_AWCACHE_LSB 20
3456 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_AWCACHE register field. */
3457 #define ALT_SYSMGR_EMAC1_AWCACHE_MSB 23
3458 /* The width in bits of the ALT_SYSMGR_EMAC1_AWCACHE register field. */
3459 #define ALT_SYSMGR_EMAC1_AWCACHE_WIDTH 4
3460 /* The mask used to set the ALT_SYSMGR_EMAC1_AWCACHE register field value. */
3461 #define ALT_SYSMGR_EMAC1_AWCACHE_SET_MSK 0x00f00000
3462 /* The mask used to clear the ALT_SYSMGR_EMAC1_AWCACHE register field value. */
3463 #define ALT_SYSMGR_EMAC1_AWCACHE_CLR_MSK 0xff0fffff
3464 /* The reset value of the ALT_SYSMGR_EMAC1_AWCACHE register field. */
3465 #define ALT_SYSMGR_EMAC1_AWCACHE_RESET 0x0
3466 /* Extracts the ALT_SYSMGR_EMAC1_AWCACHE field value from a register. */
3467 #define ALT_SYSMGR_EMAC1_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
3468 /* Produces a ALT_SYSMGR_EMAC1_AWCACHE register field value suitable for setting the register. */
3469 #define ALT_SYSMGR_EMAC1_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3470 
3471 /*
3472  * Field : arprot
3473  *
3474  * Specifies the values of the ARPROT signals.
3475  *
3476  * ==========================
3477  *
3478  * AxPROT[1]
3479  *
3480  * LOW: Secure Access
3481  *
3482  * HIGH: NonSecure Access
3483  *
3484  * ==========================
3485  *
3486  * AxPROT[0]
3487  *
3488  * LOW: Normal Access
3489  *
3490  * HIGH: Privileged Access
3491  *
3492  * ==========================
3493  *
3494  * Field Enumeration Values:
3495  *
3496  * Enum | Value | Description
3497  * :-----------------------------------------------|:------|:------------
3498  * ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_NORMAL | 0x0 |
3499  * ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
3500  * ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_NORMAL | 0x2 |
3501  * ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3502  *
3503  * Field Access Macros:
3504  *
3505  */
3506 /*
3507  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARPROT
3508  *
3509  * Secure Normal(non-privileged) access
3510  */
3511 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_NORMAL 0x0
3512 /*
3513  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARPROT
3514  *
3515  * Secure Privileged access
3516  */
3517 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_PRIVILEGED 0x1
3518 /*
3519  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARPROT
3520  *
3521  * Non-Secure Normal(non-privileged) access
3522  */
3523 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_NORMAL 0x2
3524 /*
3525  * Enumerated value for register field ALT_SYSMGR_EMAC1_ARPROT
3526  *
3527  * Non-Secure Privileged access
3528  */
3529 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3530 
3531 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_ARPROT register field. */
3532 #define ALT_SYSMGR_EMAC1_ARPROT_LSB 24
3533 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_ARPROT register field. */
3534 #define ALT_SYSMGR_EMAC1_ARPROT_MSB 25
3535 /* The width in bits of the ALT_SYSMGR_EMAC1_ARPROT register field. */
3536 #define ALT_SYSMGR_EMAC1_ARPROT_WIDTH 2
3537 /* The mask used to set the ALT_SYSMGR_EMAC1_ARPROT register field value. */
3538 #define ALT_SYSMGR_EMAC1_ARPROT_SET_MSK 0x03000000
3539 /* The mask used to clear the ALT_SYSMGR_EMAC1_ARPROT register field value. */
3540 #define ALT_SYSMGR_EMAC1_ARPROT_CLR_MSK 0xfcffffff
3541 /* The reset value of the ALT_SYSMGR_EMAC1_ARPROT register field. */
3542 #define ALT_SYSMGR_EMAC1_ARPROT_RESET 0x2
3543 /* Extracts the ALT_SYSMGR_EMAC1_ARPROT field value from a register. */
3544 #define ALT_SYSMGR_EMAC1_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
3545 /* Produces a ALT_SYSMGR_EMAC1_ARPROT register field value suitable for setting the register. */
3546 #define ALT_SYSMGR_EMAC1_ARPROT_SET(value) (((value) << 24) & 0x03000000)
3547 
3548 /*
3549  * Field : awprot
3550  *
3551  * Specifies the values of the 2 EMAC AWCACHE signals.
3552  *
3553  * ==========================
3554  *
3555  * AxPROT[1]
3556  *
3557  * LOW: Secure Access
3558  *
3559  * HIGH: NonSecure Access
3560  *
3561  * ==========================
3562  *
3563  * AxPROT[0]
3564  *
3565  * LOW: Normal Access
3566  *
3567  * HIGH: Privileged Access
3568  *
3569  * ==========================
3570  *
3571  * Field Enumeration Values:
3572  *
3573  * Enum | Value | Description
3574  * :-----------------------------------------------|:------|:------------
3575  * ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_NORMAL | 0x0 |
3576  * ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
3577  * ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_NORMAL | 0x2 |
3578  * ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
3579  *
3580  * Field Access Macros:
3581  *
3582  */
3583 /*
3584  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWPROT
3585  *
3586  * Secure Normal(non-privileged) access
3587  */
3588 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_NORMAL 0x0
3589 /*
3590  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWPROT
3591  *
3592  * Secure Privileged access
3593  */
3594 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_PRIVILEGED 0x1
3595 /*
3596  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWPROT
3597  *
3598  * Non-Secure Normal(non-privileged) access
3599  */
3600 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_NORMAL 0x2
3601 /*
3602  * Enumerated value for register field ALT_SYSMGR_EMAC1_AWPROT
3603  *
3604  * Non-Secure Privileged access
3605  */
3606 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3607 
3608 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_AWPROT register field. */
3609 #define ALT_SYSMGR_EMAC1_AWPROT_LSB 27
3610 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_AWPROT register field. */
3611 #define ALT_SYSMGR_EMAC1_AWPROT_MSB 28
3612 /* The width in bits of the ALT_SYSMGR_EMAC1_AWPROT register field. */
3613 #define ALT_SYSMGR_EMAC1_AWPROT_WIDTH 2
3614 /* The mask used to set the ALT_SYSMGR_EMAC1_AWPROT register field value. */
3615 #define ALT_SYSMGR_EMAC1_AWPROT_SET_MSK 0x18000000
3616 /* The mask used to clear the ALT_SYSMGR_EMAC1_AWPROT register field value. */
3617 #define ALT_SYSMGR_EMAC1_AWPROT_CLR_MSK 0xe7ffffff
3618 /* The reset value of the ALT_SYSMGR_EMAC1_AWPROT register field. */
3619 #define ALT_SYSMGR_EMAC1_AWPROT_RESET 0x2
3620 /* Extracts the ALT_SYSMGR_EMAC1_AWPROT field value from a register. */
3621 #define ALT_SYSMGR_EMAC1_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
3622 /* Produces a ALT_SYSMGR_EMAC1_AWPROT register field value suitable for setting the register. */
3623 #define ALT_SYSMGR_EMAC1_AWPROT_SET(value) (((value) << 27) & 0x18000000)
3624 
3625 /*
3626  * Field : sbd_data_endianness
3627  *
3628  * Specifies the endianness of the EMAC DMA transfers.
3629  *
3630  * The field array index corresponds to the EMAC index.
3631  *
3632  * Field Enumeration Values:
3633  *
3634  * Enum | Value | Description
3635  * :-----------------------------------------------------|:------|:------------
3636  * ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
3637  * ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
3638  *
3639  * Field Access Macros:
3640  *
3641  */
3642 /*
3643  * Enumerated value for register field ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS
3644  *
3645  */
3646 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3647 /*
3648  * Enumerated value for register field ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS
3649  *
3650  */
3651 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3652 
3653 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field. */
3654 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_LSB 30
3655 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field. */
3656 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_MSB 30
3657 /* The width in bits of the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field. */
3658 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_WIDTH 1
3659 /* The mask used to set the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field value. */
3660 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3661 /* The mask used to clear the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field value. */
3662 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3663 /* The reset value of the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field. */
3664 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_RESET 0x0
3665 /* Extracts the ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS field value from a register. */
3666 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3667 /* Produces a ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
3668 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3669 
3670 /*
3671  * Field : axi_disable
3672  *
3673  * AXI Disable
3674  *
3675  * Field Access Macros:
3676  *
3677  */
3678 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC1_AXI_DIS register field. */
3679 #define ALT_SYSMGR_EMAC1_AXI_DIS_LSB 31
3680 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC1_AXI_DIS register field. */
3681 #define ALT_SYSMGR_EMAC1_AXI_DIS_MSB 31
3682 /* The width in bits of the ALT_SYSMGR_EMAC1_AXI_DIS register field. */
3683 #define ALT_SYSMGR_EMAC1_AXI_DIS_WIDTH 1
3684 /* The mask used to set the ALT_SYSMGR_EMAC1_AXI_DIS register field value. */
3685 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET_MSK 0x80000000
3686 /* The mask used to clear the ALT_SYSMGR_EMAC1_AXI_DIS register field value. */
3687 #define ALT_SYSMGR_EMAC1_AXI_DIS_CLR_MSK 0x7fffffff
3688 /* The reset value of the ALT_SYSMGR_EMAC1_AXI_DIS register field. */
3689 #define ALT_SYSMGR_EMAC1_AXI_DIS_RESET 0x0
3690 /* Extracts the ALT_SYSMGR_EMAC1_AXI_DIS field value from a register. */
3691 #define ALT_SYSMGR_EMAC1_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
3692 /* Produces a ALT_SYSMGR_EMAC1_AXI_DIS register field value suitable for setting the register. */
3693 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
3694 
3695 #ifndef __ASSEMBLY__
3696 /*
3697  * WARNING: The C register and register group struct declarations are provided for
3698  * convenience and illustrative purposes. They should, however, be used with
3699  * caution as the C language standard provides no guarantees about the alignment or
3700  * atomicity of device memory accesses. The recommended practice for writing
3701  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3702  * alt_write_word() functions.
3703  *
3704  * The struct declaration for register ALT_SYSMGR_EMAC1.
3705  */
3706 struct ALT_SYSMGR_EMAC1_s
3707 {
3708  uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_EMAC1_PHY_INTF_SEL */
3709  uint32_t : 6; /* *UNDEFINED* */
3710  uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_EMAC1_PTP_REF_SEL */
3711  uint32_t : 3; /* *UNDEFINED* */
3712  uint32_t app_clk_sel : 1; /* ALT_SYSMGR_EMAC1_APP_CLK_SEL */
3713  uint32_t : 3; /* *UNDEFINED* */
3714  uint32_t arcache : 4; /* ALT_SYSMGR_EMAC1_ARCACHE */
3715  uint32_t awcache : 4; /* ALT_SYSMGR_EMAC1_AWCACHE */
3716  uint32_t arprot : 2; /* ALT_SYSMGR_EMAC1_ARPROT */
3717  uint32_t : 1; /* *UNDEFINED* */
3718  uint32_t awprot : 2; /* ALT_SYSMGR_EMAC1_AWPROT */
3719  uint32_t : 1; /* *UNDEFINED* */
3720  uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS */
3721  uint32_t axi_disable : 1; /* ALT_SYSMGR_EMAC1_AXI_DIS */
3722 };
3723 
3724 /* The typedef declaration for register ALT_SYSMGR_EMAC1. */
3725 typedef volatile struct ALT_SYSMGR_EMAC1_s ALT_SYSMGR_EMAC1_t;
3726 #endif /* __ASSEMBLY__ */
3727 
3728 /* The reset value of the ALT_SYSMGR_EMAC1 register. */
3729 #define ALT_SYSMGR_EMAC1_RESET 0x12000003
3730 /* The byte offset of the ALT_SYSMGR_EMAC1 register from the beginning of the component. */
3731 #define ALT_SYSMGR_EMAC1_OFST 0x48
3732 
3733 /*
3734  * Register : Control Register - emac2
3735  *
3736  * Registers used by the EMAC. All fields are reset by a cold or warm reset.
3737  *
3738  * Register Layout
3739  *
3740  * Bits | Access | Reset | Description
3741  * :--------|:-------|:------|:-------------------------------------
3742  * [1:0] | RW | 0x3 | ALT_SYSMGR_EMAC2_PHY_INTF_SEL
3743  * [7:2] | ??? | 0x0 | *UNDEFINED*
3744  * [8] | RW | 0x0 | ALT_SYSMGR_EMAC2_PTP_REF_SEL
3745  * [11:9] | ??? | 0x0 | *UNDEFINED*
3746  * [12] | RW | 0x0 | ALT_SYSMGR_EMAC2_APP_CLK_SEL
3747  * [15:13] | ??? | 0x0 | *UNDEFINED*
3748  * [19:16] | RW | 0x0 | ALT_SYSMGR_EMAC2_ARCACHE
3749  * [23:20] | RW | 0x0 | ALT_SYSMGR_EMAC2_AWCACHE
3750  * [25:24] | RW | 0x2 | ALT_SYSMGR_EMAC2_ARPROT
3751  * [26] | ??? | 0x0 | *UNDEFINED*
3752  * [28:27] | RW | 0x2 | ALT_SYSMGR_EMAC2_AWPROT
3753  * [29] | ??? | 0x0 | *UNDEFINED*
3754  * [30] | RW | 0x0 | ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS
3755  * [31] | RW | 0x0 | ALT_SYSMGR_EMAC2_AXI_DIS
3756  *
3757  */
3758 /*
3759  * Field : phy_intf_sel
3760  *
3761  * PHY Interface Select
3762  *
3763  * Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY
3764  * interface. Note, the MAC speed is an output of Synopsys IP. So the System
3765  * Manager PHY Select combined with MAC speed from the IP determine the clock/PHY
3766  * configuration. "Out of Reset" mode implies that the MAC RX and TX internal
3767  * clocks use the Clock Manager reference rather than depending on the PHY to have
3768  * active clocks.
3769  *
3770  * Field Enumeration Values:
3771  *
3772  * Enum | Value | Description
3773  * :-----------------------------------------|:------|:------------
3774  * ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII | 0x0 |
3775  * ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII | 0x1 |
3776  * ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII | 0x2 |
3777  * ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST | 0x3 |
3778  *
3779  * Field Access Macros:
3780  *
3781  */
3782 /*
3783  * Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL
3784  *
3785  */
3786 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII 0x0
3787 /*
3788  * Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL
3789  *
3790  */
3791 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII 0x1
3792 /*
3793  * Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL
3794  *
3795  */
3796 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII 0x2
3797 /*
3798  * Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL
3799  *
3800  */
3801 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST 0x3
3802 
3803 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field. */
3804 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_LSB 0
3805 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field. */
3806 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_MSB 1
3807 /* The width in bits of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field. */
3808 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_WIDTH 2
3809 /* The mask used to set the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value. */
3810 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK 0x00000003
3811 /* The mask used to clear the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value. */
3812 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3813 /* The reset value of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field. */
3814 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_RESET 0x3
3815 /* Extracts the ALT_SYSMGR_EMAC2_PHY_INTF_SEL field value from a register. */
3816 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3817 /* Produces a ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value suitable for setting the register. */
3818 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3819 
3820 /*
3821  * Field : ptp_ref_sel
3822  *
3823  * This field selects if the Timestamp reference is internally or externally
3824  * generated. EMAC0 may be the master to generate the timestamp for EMAC1 and
3825  * EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either
3826  * Internal or External.
3827  *
3828  * Field Enumeration Values:
3829  *
3830  * Enum | Value | Description
3831  * :----------------------------------------|:------|:------------
3832  * ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL | 0x0 |
3833  * ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL | 0x1 |
3834  *
3835  * Field Access Macros:
3836  *
3837  */
3838 /*
3839  * Enumerated value for register field ALT_SYSMGR_EMAC2_PTP_REF_SEL
3840  *
3841  */
3842 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL 0x0
3843 /*
3844  * Enumerated value for register field ALT_SYSMGR_EMAC2_PTP_REF_SEL
3845  *
3846  */
3847 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL 0x1
3848 
3849 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field. */
3850 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_LSB 8
3851 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field. */
3852 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_MSB 8
3853 /* The width in bits of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field. */
3854 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_WIDTH 1
3855 /* The mask used to set the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value. */
3856 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET_MSK 0x00000100
3857 /* The mask used to clear the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value. */
3858 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_CLR_MSK 0xfffffeff
3859 /* The reset value of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field. */
3860 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_RESET 0x0
3861 /* Extracts the ALT_SYSMGR_EMAC2_PTP_REF_SEL field value from a register. */
3862 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3863 /* Produces a ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value suitable for setting the register. */
3864 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3865 
3866 /*
3867  * Field : app_clk_sel
3868  *
3869  * Selects the source of the Application clock for the datapath to either l4_mp_clk
3870  * for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to
3871  * the FPGA fabric.
3872  *
3873  * Field Enumeration Values:
3874  *
3875  * Enum | Value | Description
3876  * :------------------------------------------|:------|:------------
3877  * ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK | 0x0 |
3878  * ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |
3879  *
3880  * Field Access Macros:
3881  *
3882  */
3883 /*
3884  * Enumerated value for register field ALT_SYSMGR_EMAC2_APP_CLK_SEL
3885  *
3886  */
3887 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK 0x0
3888 /*
3889  * Enumerated value for register field ALT_SYSMGR_EMAC2_APP_CLK_SEL
3890  *
3891  */
3892 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3893 
3894 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field. */
3895 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_LSB 12
3896 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field. */
3897 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_MSB 12
3898 /* The width in bits of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field. */
3899 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_WIDTH 1
3900 /* The mask used to set the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value. */
3901 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET_MSK 0x00001000
3902 /* The mask used to clear the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value. */
3903 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_CLR_MSK 0xffffefff
3904 /* The reset value of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field. */
3905 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_RESET 0x0
3906 /* Extracts the ALT_SYSMGR_EMAC2_APP_CLK_SEL field value from a register. */
3907 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3908 /* Produces a ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value suitable for setting the register. */
3909 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3910 
3911 /*
3912  * Field : arcache
3913  *
3914  * Specifies the values of the 2 EMAC ARCACHE signals.
3915  *
3916  * The field array index corresponds to the EMAC index.
3917  *
3918  * Field Enumeration Values:
3919  *
3920  * Enum | Value | Description
3921  * :------------------------------------------------|:------|:------------
3922  * ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF | 0x0 |
3923  * ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF | 0x1 |
3924  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC | 0x2 |
3925  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
3926  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1 | 0x4 |
3927  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2 | 0x5 |
3928  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
3929  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
3930  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3 | 0x8 |
3931  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4 | 0x9 |
3932  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
3933  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
3934  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5 | 0xc |
3935  * ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6 | 0xd |
3936  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
3937  * ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
3938  *
3939  * Field Access Macros:
3940  *
3941  */
3942 /*
3943  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3944  *
3945  */
3946 #define ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF 0x0
3947 /*
3948  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3949  *
3950  */
3951 #define ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF 0x1
3952 /*
3953  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3954  *
3955  */
3956 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC 0x2
3957 /*
3958  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3959  *
3960  */
3961 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3962 /*
3963  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3964  *
3965  */
3966 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1 0x4
3967 /*
3968  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3969  *
3970  */
3971 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2 0x5
3972 /*
3973  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3974  *
3975  */
3976 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3977 /*
3978  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3979  *
3980  */
3981 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3982 /*
3983  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3984  *
3985  */
3986 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3 0x8
3987 /*
3988  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3989  *
3990  */
3991 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4 0x9
3992 /*
3993  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3994  *
3995  */
3996 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3997 /*
3998  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
3999  *
4000  */
4001 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4002 /*
4003  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
4004  *
4005  */
4006 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5 0xc
4007 /*
4008  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
4009  *
4010  */
4011 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6 0xd
4012 /*
4013  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
4014  *
4015  */
4016 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4017 /*
4018  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE
4019  *
4020  */
4021 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
4022 
4023 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_ARCACHE register field. */
4024 #define ALT_SYSMGR_EMAC2_ARCACHE_LSB 16
4025 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_ARCACHE register field. */
4026 #define ALT_SYSMGR_EMAC2_ARCACHE_MSB 19
4027 /* The width in bits of the ALT_SYSMGR_EMAC2_ARCACHE register field. */
4028 #define ALT_SYSMGR_EMAC2_ARCACHE_WIDTH 4
4029 /* The mask used to set the ALT_SYSMGR_EMAC2_ARCACHE register field value. */
4030 #define ALT_SYSMGR_EMAC2_ARCACHE_SET_MSK 0x000f0000
4031 /* The mask used to clear the ALT_SYSMGR_EMAC2_ARCACHE register field value. */
4032 #define ALT_SYSMGR_EMAC2_ARCACHE_CLR_MSK 0xfff0ffff
4033 /* The reset value of the ALT_SYSMGR_EMAC2_ARCACHE register field. */
4034 #define ALT_SYSMGR_EMAC2_ARCACHE_RESET 0x0
4035 /* Extracts the ALT_SYSMGR_EMAC2_ARCACHE field value from a register. */
4036 #define ALT_SYSMGR_EMAC2_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
4037 /* Produces a ALT_SYSMGR_EMAC2_ARCACHE register field value suitable for setting the register. */
4038 #define ALT_SYSMGR_EMAC2_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
4039 
4040 /*
4041  * Field : awcache
4042  *
4043  * Specifies the values of the 2 EMAC AWCACHE signals.
4044  *
4045  * The field array index corresponds to the EMAC index.
4046  *
4047  * Field Enumeration Values:
4048  *
4049  * Enum | Value | Description
4050  * :------------------------------------------------|:------|:------------
4051  * ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF | 0x0 |
4052  * ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF | 0x1 |
4053  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC | 0x2 |
4054  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 |
4055  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1 | 0x4 |
4056  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2 | 0x5 |
4057  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 |
4058  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 |
4059  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3 | 0x8 |
4060  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4 | 0x9 |
4061  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa |
4062  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb |
4063  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5 | 0xc |
4064  * ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6 | 0xd |
4065  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe |
4066  * ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |
4067  *
4068  * Field Access Macros:
4069  *
4070  */
4071 /*
4072  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4073  *
4074  */
4075 #define ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF 0x0
4076 /*
4077  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4078  *
4079  */
4080 #define ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF 0x1
4081 /*
4082  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4083  *
4084  */
4085 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC 0x2
4086 /*
4087  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4088  *
4089  */
4090 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
4091 /*
4092  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4093  *
4094  */
4095 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1 0x4
4096 /*
4097  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4098  *
4099  */
4100 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2 0x5
4101 /*
4102  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4103  *
4104  */
4105 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4106 /*
4107  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4108  *
4109  */
4110 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4111 /*
4112  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4113  *
4114  */
4115 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3 0x8
4116 /*
4117  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4118  *
4119  */
4120 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4 0x9
4121 /*
4122  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4123  *
4124  */
4125 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4126 /*
4127  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4128  *
4129  */
4130 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4131 /*
4132  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4133  *
4134  */
4135 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5 0xc
4136 /*
4137  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4138  *
4139  */
4140 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6 0xd
4141 /*
4142  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4143  *
4144  */
4145 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4146 /*
4147  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE
4148  *
4149  */
4150 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
4151 
4152 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AWCACHE register field. */
4153 #define ALT_SYSMGR_EMAC2_AWCACHE_LSB 20
4154 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AWCACHE register field. */
4155 #define ALT_SYSMGR_EMAC2_AWCACHE_MSB 23
4156 /* The width in bits of the ALT_SYSMGR_EMAC2_AWCACHE register field. */
4157 #define ALT_SYSMGR_EMAC2_AWCACHE_WIDTH 4
4158 /* The mask used to set the ALT_SYSMGR_EMAC2_AWCACHE register field value. */
4159 #define ALT_SYSMGR_EMAC2_AWCACHE_SET_MSK 0x00f00000
4160 /* The mask used to clear the ALT_SYSMGR_EMAC2_AWCACHE register field value. */
4161 #define ALT_SYSMGR_EMAC2_AWCACHE_CLR_MSK 0xff0fffff
4162 /* The reset value of the ALT_SYSMGR_EMAC2_AWCACHE register field. */
4163 #define ALT_SYSMGR_EMAC2_AWCACHE_RESET 0x0
4164 /* Extracts the ALT_SYSMGR_EMAC2_AWCACHE field value from a register. */
4165 #define ALT_SYSMGR_EMAC2_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
4166 /* Produces a ALT_SYSMGR_EMAC2_AWCACHE register field value suitable for setting the register. */
4167 #define ALT_SYSMGR_EMAC2_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
4168 
4169 /*
4170  * Field : arprot
4171  *
4172  * Specifies the values of the ARPROT signals.
4173  *
4174  * ==========================
4175  *
4176  * AxPROT[1]
4177  *
4178  * LOW: Secure Access
4179  *
4180  * HIGH: NonSecure Access
4181  *
4182  * ==========================
4183  *
4184  * AxPROT[0]
4185  *
4186  * LOW: Normal Access
4187  *
4188  * HIGH: Privileged Access
4189  *
4190  * ==========================
4191  *
4192  * Field Enumeration Values:
4193  *
4194  * Enum | Value | Description
4195  * :-----------------------------------------------|:------|:------------
4196  * ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL | 0x0 |
4197  * ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED | 0x1 |
4198  * ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL | 0x2 |
4199  * ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |
4200  *
4201  * Field Access Macros:
4202  *
4203  */
4204 /*
4205  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT
4206  *
4207  * Secure Normal(non-privileged) access
4208  */
4209 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL 0x0
4210 /*
4211  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT
4212  *
4213  * Secure Privileged access
4214  */
4215 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED 0x1
4216 /*
4217  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT
4218  *
4219  * Non-Secure Normal(non-privileged) access
4220  */
4221 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL 0x2
4222 /*
4223  * Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT
4224  *
4225  * Non-Secure Privileged access
4226  */
4227 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED 0x3
4228 
4229 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_ARPROT register field. */
4230 #define ALT_SYSMGR_EMAC2_ARPROT_LSB 24
4231 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_ARPROT register field. */
4232 #define ALT_SYSMGR_EMAC2_ARPROT_MSB 25
4233 /* The width in bits of the ALT_SYSMGR_EMAC2_ARPROT register field. */
4234 #define ALT_SYSMGR_EMAC2_ARPROT_WIDTH 2
4235 /* The mask used to set the ALT_SYSMGR_EMAC2_ARPROT register field value. */
4236 #define ALT_SYSMGR_EMAC2_ARPROT_SET_MSK 0x03000000
4237 /* The mask used to clear the ALT_SYSMGR_EMAC2_ARPROT register field value. */
4238 #define ALT_SYSMGR_EMAC2_ARPROT_CLR_MSK 0xfcffffff
4239 /* The reset value of the ALT_SYSMGR_EMAC2_ARPROT register field. */
4240 #define ALT_SYSMGR_EMAC2_ARPROT_RESET 0x2
4241 /* Extracts the ALT_SYSMGR_EMAC2_ARPROT field value from a register. */
4242 #define ALT_SYSMGR_EMAC2_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
4243 /* Produces a ALT_SYSMGR_EMAC2_ARPROT register field value suitable for setting the register. */
4244 #define ALT_SYSMGR_EMAC2_ARPROT_SET(value) (((value) << 24) & 0x03000000)
4245 
4246 /*
4247  * Field : awprot
4248  *
4249  * Specifies the values of the 2 EMAC AWCACHE signals.
4250  *
4251  * ==========================
4252  *
4253  * AxPROT[1]
4254  *
4255  * LOW: Secure Access
4256  *
4257  * HIGH: NonSecure Access
4258  *
4259  * ==========================
4260  *
4261  * AxPROT[0]
4262  *
4263  * LOW: Normal Access
4264  *
4265  * HIGH: Privileged Access
4266  *
4267  * ==========================
4268  *
4269  * Field Enumeration Values:
4270  *
4271  * Enum | Value | Description
4272  * :-----------------------------------------------|:------|:------------
4273  * ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL | 0x0 |
4274  * ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED | 0x1 |
4275  * ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL | 0x2 |
4276  * ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |
4277  *
4278  * Field Access Macros:
4279  *
4280  */
4281 /*
4282  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT
4283  *
4284  * Secure Normal(non-privileged) access
4285  */
4286 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL 0x0
4287 /*
4288  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT
4289  *
4290  * Secure Privileged access
4291  */
4292 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED 0x1
4293 /*
4294  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT
4295  *
4296  * Non-Secure Normal(non-privileged) access
4297  */
4298 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL 0x2
4299 /*
4300  * Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT
4301  *
4302  * Non-Secure Privileged access
4303  */
4304 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED 0x3
4305 
4306 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AWPROT register field. */
4307 #define ALT_SYSMGR_EMAC2_AWPROT_LSB 27
4308 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AWPROT register field. */
4309 #define ALT_SYSMGR_EMAC2_AWPROT_MSB 28
4310 /* The width in bits of the ALT_SYSMGR_EMAC2_AWPROT register field. */
4311 #define ALT_SYSMGR_EMAC2_AWPROT_WIDTH 2
4312 /* The mask used to set the ALT_SYSMGR_EMAC2_AWPROT register field value. */
4313 #define ALT_SYSMGR_EMAC2_AWPROT_SET_MSK 0x18000000
4314 /* The mask used to clear the ALT_SYSMGR_EMAC2_AWPROT register field value. */
4315 #define ALT_SYSMGR_EMAC2_AWPROT_CLR_MSK 0xe7ffffff
4316 /* The reset value of the ALT_SYSMGR_EMAC2_AWPROT register field. */
4317 #define ALT_SYSMGR_EMAC2_AWPROT_RESET 0x2
4318 /* Extracts the ALT_SYSMGR_EMAC2_AWPROT field value from a register. */
4319 #define ALT_SYSMGR_EMAC2_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
4320 /* Produces a ALT_SYSMGR_EMAC2_AWPROT register field value suitable for setting the register. */
4321 #define ALT_SYSMGR_EMAC2_AWPROT_SET(value) (((value) << 27) & 0x18000000)
4322 
4323 /*
4324  * Field : sbd_data_endianness
4325  *
4326  * Specifies the endianness of the EMAC DMA transfers.
4327  *
4328  * The field array index corresponds to the EMAC index.
4329  *
4330  * Field Enumeration Values:
4331  *
4332  * Enum | Value | Description
4333  * :-----------------------------------------------------|:------|:------------
4334  * ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 |
4335  * ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |
4336  *
4337  * Field Access Macros:
4338  *
4339  */
4340 /*
4341  * Enumerated value for register field ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS
4342  *
4343  */
4344 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
4345 /*
4346  * Enumerated value for register field ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS
4347  *
4348  */
4349 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
4350 
4351 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field. */
4352 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_LSB 30
4353 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field. */
4354 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_MSB 30
4355 /* The width in bits of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field. */
4356 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_WIDTH 1
4357 /* The mask used to set the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value. */
4358 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
4359 /* The mask used to clear the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value. */
4360 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
4361 /* The reset value of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field. */
4362 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_RESET 0x0
4363 /* Extracts the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS field value from a register. */
4364 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
4365 /* Produces a ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value suitable for setting the register. */
4366 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
4367 
4368 /*
4369  * Field : axi_disable
4370  *
4371  * AXI Disable
4372  *
4373  * Field Access Macros:
4374  *
4375  */
4376 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AXI_DIS register field. */
4377 #define ALT_SYSMGR_EMAC2_AXI_DIS_LSB 31
4378 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AXI_DIS register field. */
4379 #define ALT_SYSMGR_EMAC2_AXI_DIS_MSB 31
4380 /* The width in bits of the ALT_SYSMGR_EMAC2_AXI_DIS register field. */
4381 #define ALT_SYSMGR_EMAC2_AXI_DIS_WIDTH 1
4382 /* The mask used to set the ALT_SYSMGR_EMAC2_AXI_DIS register field value. */
4383 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET_MSK 0x80000000
4384 /* The mask used to clear the ALT_SYSMGR_EMAC2_AXI_DIS register field value. */
4385 #define ALT_SYSMGR_EMAC2_AXI_DIS_CLR_MSK 0x7fffffff
4386 /* The reset value of the ALT_SYSMGR_EMAC2_AXI_DIS register field. */
4387 #define ALT_SYSMGR_EMAC2_AXI_DIS_RESET 0x0
4388 /* Extracts the ALT_SYSMGR_EMAC2_AXI_DIS field value from a register. */
4389 #define ALT_SYSMGR_EMAC2_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
4390 /* Produces a ALT_SYSMGR_EMAC2_AXI_DIS register field value suitable for setting the register. */
4391 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
4392 
4393 #ifndef __ASSEMBLY__
4394 /*
4395  * WARNING: The C register and register group struct declarations are provided for
4396  * convenience and illustrative purposes. They should, however, be used with
4397  * caution as the C language standard provides no guarantees about the alignment or
4398  * atomicity of device memory accesses. The recommended practice for writing
4399  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4400  * alt_write_word() functions.
4401  *
4402  * The struct declaration for register ALT_SYSMGR_EMAC2.
4403  */
4404 struct ALT_SYSMGR_EMAC2_s
4405 {
4406  uint32_t phy_intf_sel : 2; /* ALT_SYSMGR_EMAC2_PHY_INTF_SEL */
4407  uint32_t : 6; /* *UNDEFINED* */
4408  uint32_t ptp_ref_sel : 1; /* ALT_SYSMGR_EMAC2_PTP_REF_SEL */
4409  uint32_t : 3; /* *UNDEFINED* */
4410  uint32_t app_clk_sel : 1; /* ALT_SYSMGR_EMAC2_APP_CLK_SEL */
4411  uint32_t : 3; /* *UNDEFINED* */
4412  uint32_t arcache : 4; /* ALT_SYSMGR_EMAC2_ARCACHE */
4413  uint32_t awcache : 4; /* ALT_SYSMGR_EMAC2_AWCACHE */
4414  uint32_t arprot : 2; /* ALT_SYSMGR_EMAC2_ARPROT */
4415  uint32_t : 1; /* *UNDEFINED* */
4416  uint32_t awprot : 2; /* ALT_SYSMGR_EMAC2_AWPROT */
4417  uint32_t : 1; /* *UNDEFINED* */
4418  uint32_t sbd_data_endianness : 1; /* ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS */
4419  uint32_t axi_disable : 1; /* ALT_SYSMGR_EMAC2_AXI_DIS */
4420 };
4421 
4422 /* The typedef declaration for register ALT_SYSMGR_EMAC2. */
4423 typedef volatile struct ALT_SYSMGR_EMAC2_s ALT_SYSMGR_EMAC2_t;
4424 #endif /* __ASSEMBLY__ */
4425 
4426 /* The reset value of the ALT_SYSMGR_EMAC2 register. */
4427 #define ALT_SYSMGR_EMAC2_RESET 0x12000003
4428 /* The byte offset of the ALT_SYSMGR_EMAC2 register from the beginning of the component. */
4429 #define ALT_SYSMGR_EMAC2_OFST 0x4c
4430 
4431 /*
4432  * Register : Global Disable Register - fpgaintf_en_global
4433  *
4434  * Used to disable all interfaces between the FPGA and HPS.
4435  *
4436  * This register is reset only on a cold reset (ignores warm reset).
4437  *
4438  * Register Layout
4439  *
4440  * Bits | Access | Reset | Description
4441  * :-------|:-------|:------|:-----------------
4442  * [0] | RW | 0x1 | Global Interface
4443  * [31:1] | ??? | 0x0 | *UNDEFINED*
4444  *
4445  */
4446 /*
4447  * Field : Global Interface - intf
4448  *
4449  * Used to disable all interfaces between the FPGA and HPS. Software must ensure
4450  * that all interfaces between the FPGA and HPS are inactive before disabling them.
4451  *
4452  * Field Enumeration Values:
4453  *
4454  * Enum | Value | Description
4455  * :---------------------------------------|:------|:------------
4456  * ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_DIS | 0x0 |
4457  * ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_EN | 0x1 |
4458  *
4459  * Field Access Macros:
4460  *
4461  */
4462 /*
4463  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF
4464  *
4465  */
4466 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_DIS 0x0
4467 /*
4468  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF
4469  *
4470  */
4471 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_EN 0x1
4472 
4473 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field. */
4474 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_LSB 0
4475 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field. */
4476 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_MSB 0
4477 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field. */
4478 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_WIDTH 1
4479 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field value. */
4480 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET_MSK 0x00000001
4481 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field value. */
4482 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_CLR_MSK 0xfffffffe
4483 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field. */
4484 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_RESET 0x1
4485 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF field value from a register. */
4486 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_GET(value) (((value) & 0x00000001) >> 0)
4487 /* Produces a ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF register field value suitable for setting the register. */
4488 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET(value) (((value) << 0) & 0x00000001)
4489 
4490 #ifndef __ASSEMBLY__
4491 /*
4492  * WARNING: The C register and register group struct declarations are provided for
4493  * convenience and illustrative purposes. They should, however, be used with
4494  * caution as the C language standard provides no guarantees about the alignment or
4495  * atomicity of device memory accesses. The recommended practice for writing
4496  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4497  * alt_write_word() functions.
4498  *
4499  * The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_GLOB.
4500  */
4501 struct ALT_SYSMGR_FPGAINTF_EN_GLOB_s
4502 {
4503  uint32_t intf : 1; /* Global Interface */
4504  uint32_t : 31; /* *UNDEFINED* */
4505 };
4506 
4507 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_GLOB. */
4508 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_GLOB_s ALT_SYSMGR_FPGAINTF_EN_GLOB_t;
4509 #endif /* __ASSEMBLY__ */
4510 
4511 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_GLOB register. */
4512 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_RESET 0x00000001
4513 /* The byte offset of the ALT_SYSMGR_FPGAINTF_EN_GLOB register from the beginning of the component. */
4514 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_OFST 0x60
4515 
4516 /*
4517  * Register : FPGA interface Individual Enable Register - fpgaintf_en_0
4518  *
4519  * Used to disable individual interfaces between the FPGA and HPS.
4520  *
4521  * This register is reset only on a cold reset (ignores warm reset).
4522  *
4523  * Register Layout
4524  *
4525  * Bits | Access | Reset | Description
4526  * :--------|:-------|:-------|:------------------------
4527  * [0] | RW | 0x1 | Reset Request Interface
4528  * [7:1] | ??? | 0x7f | *UNDEFINED*
4529  * [8] | RW | 0x1 | CONFIG_IO Interface
4530  * [15:9] | ??? | 0x7f | *UNDEFINED*
4531  * [16] | RW | 0x1 | Boundary-Scan Interface
4532  * [31:17] | ??? | 0x7fff | *UNDEFINED*
4533  *
4534  */
4535 /*
4536  * Field : Reset Request Interface - rstreq
4537  *
4538  * Used to disable the reset request interface. This interface allows logic in the
4539  * FPGA fabric to request HPS resets. This field disables the following reset
4540  * request signals from the FPGA fabric to HPS:[list][*]f2s_cold_rst_req - Triggers
4541  * a cold reset of the HPS[*]f2s_warm_rst_req - Triggers a warm reset of the
4542  * HPS[*]f2s_dbg_rst_req - Triggers a debug reset of the HPS[/list]
4543  *
4544  * Field Enumeration Values:
4545  *
4546  * Enum | Value | Description
4547  * :--------------------------------------|:------|:------------
4548  * ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS | 0x0 |
4549  * ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN | 0x1 |
4550  *
4551  * Field Access Macros:
4552  *
4553  */
4554 /*
4555  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ
4556  *
4557  */
4558 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS 0x0
4559 /*
4560  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ
4561  *
4562  */
4563 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN 0x1
4564 
4565 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field. */
4566 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_LSB 0
4567 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field. */
4568 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_MSB 0
4569 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field. */
4570 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_WIDTH 1
4571 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value. */
4572 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET_MSK 0x00000001
4573 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value. */
4574 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_CLR_MSK 0xfffffffe
4575 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field. */
4576 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_RESET 0x1
4577 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ field value from a register. */
4578 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_GET(value) (((value) & 0x00000001) >> 0)
4579 /* Produces a ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value suitable for setting the register. */
4580 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET(value) (((value) << 0) & 0x00000001)
4581 
4582 /*
4583  * Field : CONFIG_IO Interface - cfgio
4584  *
4585  * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP
4586  * controller to execute the CONFIG_IO instruction and configure all device I/Os
4587  * (FPGA and HPS). This is typically done before executing boundary-scan
4588  * instructions. The CONFIG_IO interface must be enabled before attempting to send
4589  * the CONFIG_IO instruction to the FPGA JTAG TAP controller.
4590  *
4591  * Field Enumeration Values:
4592  *
4593  * Enum | Value | Description
4594  * :-------------------------------------|:------|:------------
4595  * ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS | 0x0 |
4596  * ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN | 0x1 |
4597  *
4598  * Field Access Macros:
4599  *
4600  */
4601 /*
4602  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_CFGIO
4603  *
4604  */
4605 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS 0x0
4606 /*
4607  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_CFGIO
4608  *
4609  */
4610 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN 0x1
4611 
4612 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field. */
4613 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_LSB 8
4614 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field. */
4615 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_MSB 8
4616 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field. */
4617 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_WIDTH 1
4618 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value. */
4619 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET_MSK 0x00000100
4620 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value. */
4621 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_CLR_MSK 0xfffffeff
4622 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field. */
4623 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_RESET 0x1
4624 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO field value from a register. */
4625 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_GET(value) (((value) & 0x00000100) >> 8)
4626 /* Produces a ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value suitable for setting the register. */
4627 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET(value) (((value) << 8) & 0x00000100)
4628 
4629 /*
4630  * Field : Boundary-Scan Interface - bscan
4631  *
4632  * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG
4633  * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD,
4634  * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting
4635  * to send the boundary-scan instructions to the FPGA JTAG TAP controller.
4636  *
4637  * Field Enumeration Values:
4638  *
4639  * Enum | Value | Description
4640  * :-------------------------------------|:------|:------------
4641  * ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS | 0x0 |
4642  * ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN | 0x1 |
4643  *
4644  * Field Access Macros:
4645  *
4646  */
4647 /*
4648  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_BSCAN
4649  *
4650  */
4651 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS 0x0
4652 /*
4653  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_BSCAN
4654  *
4655  */
4656 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN 0x1
4657 
4658 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field. */
4659 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_LSB 16
4660 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field. */
4661 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_MSB 16
4662 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field. */
4663 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_WIDTH 1
4664 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value. */
4665 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET_MSK 0x00010000
4666 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value. */
4667 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_CLR_MSK 0xfffeffff
4668 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field. */
4669 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_RESET 0x1
4670 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN field value from a register. */
4671 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_GET(value) (((value) & 0x00010000) >> 16)
4672 /* Produces a ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value suitable for setting the register. */
4673 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET(value) (((value) << 16) & 0x00010000)
4674 
4675 #ifndef __ASSEMBLY__
4676 /*
4677  * WARNING: The C register and register group struct declarations are provided for
4678  * convenience and illustrative purposes. They should, however, be used with
4679  * caution as the C language standard provides no guarantees about the alignment or
4680  * atomicity of device memory accesses. The recommended practice for writing
4681  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4682  * alt_write_word() functions.
4683  *
4684  * The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_0.
4685  */
4686 struct ALT_SYSMGR_FPGAINTF_EN_0_s
4687 {
4688  uint32_t rstreq : 1; /* Reset Request Interface */
4689  uint32_t : 7; /* *UNDEFINED* */
4690  uint32_t cfgio : 1; /* CONFIG_IO Interface */
4691  uint32_t : 7; /* *UNDEFINED* */
4692  uint32_t bscan : 1; /* Boundary-Scan Interface */
4693  uint32_t : 15; /* *UNDEFINED* */
4694 };
4695 
4696 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_0. */
4697 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_0_s ALT_SYSMGR_FPGAINTF_EN_0_t;
4698 #endif /* __ASSEMBLY__ */
4699 
4700 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_0 register. */
4701 #define ALT_SYSMGR_FPGAINTF_EN_0_RESET 0xffffffff
4702 /* The byte offset of the ALT_SYSMGR_FPGAINTF_EN_0 register from the beginning of the component. */
4703 #define ALT_SYSMGR_FPGAINTF_EN_0_OFST 0x64
4704 
4705 /*
4706  * Register : FPGA interface Individual Enable Register - fpgaintf_en_1
4707  *
4708  * Used to disable individual interfaces between the FPGA and HPS.
4709  *
4710  * This register is reset only on a cold reset (ignores warm reset).
4711  *
4712  * Register Layout
4713  *
4714  * Bits | Access | Reset | Description
4715  * :--------|:-------|:------|:------------------------------
4716  * [3:0] | ??? | 0xf | *UNDEFINED*
4717  * [4] | RW | 0x1 | Trace Interface
4718  * [7:5] | ??? | 0x7 | *UNDEFINED*
4719  * [8] | RW | 0x1 | Debug APB Interface
4720  * [15:9] | ??? | 0x7f | *UNDEFINED*
4721  * [16] | RW | 0x1 | STM Event Interface
4722  * [23:17] | ??? | 0x7f | *UNDEFINED*
4723  * [24] | RW | 0x1 | Cross Trigger Interface (CTI)
4724  * [31:25] | ??? | 0x7f | *UNDEFINED*
4725  *
4726  */
4727 /*
4728  * Field : Trace Interface - trace
4729  *
4730  * Used to disable the trace interface. This interface allows the HPS debug logic
4731  * to send trace data to logic in the FPGA fabric.
4732  *
4733  * Field Enumeration Values:
4734  *
4735  * Enum | Value | Description
4736  * :-------------------------------------|:------|:------------
4737  * ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_DIS | 0x0 |
4738  * ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_EN | 0x1 |
4739  *
4740  * Field Access Macros:
4741  *
4742  */
4743 /*
4744  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_TRACE
4745  *
4746  */
4747 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_DIS 0x0
4748 /*
4749  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_TRACE
4750  *
4751  */
4752 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_EN 0x1
4753 
4754 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field. */
4755 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_LSB 4
4756 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field. */
4757 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_MSB 4
4758 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field. */
4759 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_WIDTH 1
4760 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field value. */
4761 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET_MSK 0x00000010
4762 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field value. */
4763 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_CLR_MSK 0xffffffef
4764 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field. */
4765 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_RESET 0x1
4766 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_1_TRACE field value from a register. */
4767 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_GET(value) (((value) & 0x00000010) >> 4)
4768 /* Produces a ALT_SYSMGR_FPGAINTF_EN_1_TRACE register field value suitable for setting the register. */
4769 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET(value) (((value) << 4) & 0x00000010)
4770 
4771 /*
4772  * Field : Debug APB Interface - dbgapb
4773  *
4774  * Used to disable the debug APB interface. This interface allows the HPS debug
4775  * logic to communicate with debug APB slaves in the FPGA fabric.
4776  *
4777  * Field Enumeration Values:
4778  *
4779  * Enum | Value | Description
4780  * :--------------------------------------|:------|:------------
4781  * ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_DIS | 0x0 |
4782  * ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_EN | 0x1 |
4783  *
4784  * Field Access Macros:
4785  *
4786  */
4787 /*
4788  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB
4789  *
4790  */
4791 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_DIS 0x0
4792 /*
4793  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB
4794  *
4795  */
4796 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_EN 0x1
4797 
4798 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field. */
4799 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_LSB 8
4800 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field. */
4801 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_MSB 8
4802 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field. */
4803 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_WIDTH 1
4804 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field value. */
4805 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET_MSK 0x00000100
4806 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field value. */
4807 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_CLR_MSK 0xfffffeff
4808 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field. */
4809 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_RESET 0x1
4810 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB field value from a register. */
4811 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_GET(value) (((value) & 0x00000100) >> 8)
4812 /* Produces a ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB register field value suitable for setting the register. */
4813 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET(value) (((value) << 8) & 0x00000100)
4814 
4815 /*
4816  * Field : STM Event Interface - stmevent
4817  *
4818  * Used to disable the STM event interface. This interface allows logic in the FPGA
4819  * fabric to trigger events to the STM debug module in the HPS.
4820  *
4821  * Field Enumeration Values:
4822  *
4823  * Enum | Value | Description
4824  * :----------------------------------------|:------|:------------
4825  * ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_DIS | 0x0 |
4826  * ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_EN | 0x1 |
4827  *
4828  * Field Access Macros:
4829  *
4830  */
4831 /*
4832  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT
4833  *
4834  */
4835 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_DIS 0x0
4836 /*
4837  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT
4838  *
4839  */
4840 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_EN 0x1
4841 
4842 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field. */
4843 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_LSB 16
4844 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field. */
4845 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_MSB 16
4846 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field. */
4847 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_WIDTH 1
4848 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field value. */
4849 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET_MSK 0x00010000
4850 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field value. */
4851 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_CLR_MSK 0xfffeffff
4852 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field. */
4853 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_RESET 0x1
4854 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT field value from a register. */
4855 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_GET(value) (((value) & 0x00010000) >> 16)
4856 /* Produces a ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT register field value suitable for setting the register. */
4857 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET(value) (((value) << 16) & 0x00010000)
4858 
4859 /*
4860  * Field : Cross Trigger Interface (CTI) - ctmtrigger
4861  *
4862  * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note
4863  * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA
4864  * Fabric.
4865  *
4866  * Field Enumeration Values:
4867  *
4868  * Enum | Value | Description
4869  * :------------------------------------------|:------|:------------
4870  * ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_DIS | 0x0 |
4871  * ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_EN | 0x1 |
4872  *
4873  * Field Access Macros:
4874  *
4875  */
4876 /*
4877  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER
4878  *
4879  */
4880 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_DIS 0x0
4881 /*
4882  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER
4883  *
4884  */
4885 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_EN 0x1
4886 
4887 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field. */
4888 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_LSB 24
4889 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field. */
4890 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_MSB 24
4891 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field. */
4892 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_WIDTH 1
4893 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field value. */
4894 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET_MSK 0x01000000
4895 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field value. */
4896 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_CLR_MSK 0xfeffffff
4897 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field. */
4898 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_RESET 0x1
4899 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER field value from a register. */
4900 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_GET(value) (((value) & 0x01000000) >> 24)
4901 /* Produces a ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER register field value suitable for setting the register. */
4902 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET(value) (((value) << 24) & 0x01000000)
4903 
4904 #ifndef __ASSEMBLY__
4905 /*
4906  * WARNING: The C register and register group struct declarations are provided for
4907  * convenience and illustrative purposes. They should, however, be used with
4908  * caution as the C language standard provides no guarantees about the alignment or
4909  * atomicity of device memory accesses. The recommended practice for writing
4910  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4911  * alt_write_word() functions.
4912  *
4913  * The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_1.
4914  */
4915 struct ALT_SYSMGR_FPGAINTF_EN_1_s
4916 {
4917  uint32_t : 4; /* *UNDEFINED* */
4918  uint32_t trace : 1; /* Trace Interface */
4919  uint32_t : 3; /* *UNDEFINED* */
4920  uint32_t dbgapb : 1; /* Debug APB Interface */
4921  uint32_t : 7; /* *UNDEFINED* */
4922  uint32_t stmevent : 1; /* STM Event Interface */
4923  uint32_t : 7; /* *UNDEFINED* */
4924  uint32_t ctmtrigger : 1; /* Cross Trigger Interface (CTI) */
4925  uint32_t : 7; /* *UNDEFINED* */
4926 };
4927 
4928 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_1. */
4929 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_1_s ALT_SYSMGR_FPGAINTF_EN_1_t;
4930 #endif /* __ASSEMBLY__ */
4931 
4932 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_1 register. */
4933 #define ALT_SYSMGR_FPGAINTF_EN_1_RESET 0xffffffff
4934 /* The byte offset of the ALT_SYSMGR_FPGAINTF_EN_1 register from the beginning of the component. */
4935 #define ALT_SYSMGR_FPGAINTF_EN_1_OFST 0x68
4936 
4937 /*
4938  * Register : FPGA interface Individual Enable Register - fpgaintf_en_2
4939  *
4940  * Used to disable individual interfaces between the FPGA and HPS.
4941  *
4942  * This register is reset only on a cold reset (ignores warm reset).
4943  *
4944  * Register Layout
4945  *
4946  * Bits | Access | Reset | Description
4947  * :--------|:-------|:------|:-----------------------------
4948  * [3:0] | ??? | 0x0 | *UNDEFINED*
4949  * [4] | RW | 0x0 | NAND Flash Controller Module
4950  * [7:5] | ??? | 0x0 | *UNDEFINED*
4951  * [8] | RW | 0x0 | SD/MMC Controller Module
4952  * [15:9] | ??? | 0x0 | *UNDEFINED*
4953  * [16] | RW | 0x0 | SPI Master Module
4954  * [23:17] | ??? | 0x0 | *UNDEFINED*
4955  * [24] | RW | 0x0 | SPI Master Module
4956  * [31:25] | ??? | 0x0 | *UNDEFINED*
4957  *
4958  */
4959 /*
4960  * Field : NAND Flash Controller Module - nand
4961  *
4962  * Used to disable signals from the FPGA fabric to the NAND flash controller module
4963  * that could potentially interfere with its normal operation.
4964  *
4965  * Field Enumeration Values:
4966  *
4967  * Enum | Value | Description
4968  * :------------------------------------|:------|:------------
4969  * ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS | 0x0 |
4970  * ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN | 0x1 |
4971  *
4972  * Field Access Macros:
4973  *
4974  */
4975 /*
4976  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_NAND
4977  *
4978  */
4979 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS 0x0
4980 /*
4981  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_NAND
4982  *
4983  */
4984 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN 0x1
4985 
4986 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field. */
4987 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_LSB 4
4988 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field. */
4989 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_MSB 4
4990 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field. */
4991 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_WIDTH 1
4992 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value. */
4993 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010
4994 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value. */
4995 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef
4996 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field. */
4997 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_RESET 0x0
4998 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_2_NAND field value from a register. */
4999 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4)
5000 /* Produces a ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value suitable for setting the register. */
5001 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010)
5002 
5003 /*
5004  * Field : SD/MMC Controller Module - sdmmc
5005  *
5006  * Used to disable signals from the FPGA fabric to the SD/MMC controller module
5007  * that could potentially interfere with its normal operation.
5008  *
5009  * Field Enumeration Values:
5010  *
5011  * Enum | Value | Description
5012  * :-------------------------------------|:------|:------------
5013  * ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS | 0x0 |
5014  * ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN | 0x1 |
5015  *
5016  * Field Access Macros:
5017  *
5018  */
5019 /*
5020  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SDMMC
5021  *
5022  */
5023 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS 0x0
5024 /*
5025  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SDMMC
5026  *
5027  */
5028 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN 0x1
5029 
5030 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field. */
5031 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_LSB 8
5032 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field. */
5033 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_MSB 8
5034 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field. */
5035 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_WIDTH 1
5036 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value. */
5037 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100
5038 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value. */
5039 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff
5040 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field. */
5041 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_RESET 0x0
5042 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC field value from a register. */
5043 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8)
5044 /* Produces a ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value suitable for setting the register. */
5045 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100)
5046 
5047 /*
5048  * Field : SPI Master Module - spim_0
5049  *
5050  * Used to disable signals from the FPGA fabric to the SPI master modules that
5051  * could potentially interfere with their normal operation.
5052  *
5053  * The array index corresponds to the SPI master module instance.
5054  *
5055  * Field Enumeration Values:
5056  *
5057  * Enum | Value | Description
5058  * :--------------------------------------|:------|:------------
5059  * ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS | 0x0 |
5060  * ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN | 0x1 |
5061  *
5062  * Field Access Macros:
5063  *
5064  */
5065 /*
5066  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0
5067  *
5068  */
5069 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS 0x0
5070 /*
5071  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0
5072  *
5073  */
5074 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN 0x1
5075 
5076 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field. */
5077 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_LSB 16
5078 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field. */
5079 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_MSB 16
5080 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field. */
5081 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_WIDTH 1
5082 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value. */
5083 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000
5084 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value. */
5085 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff
5086 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field. */
5087 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_RESET 0x0
5088 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 field value from a register. */
5089 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16)
5090 /* Produces a ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value suitable for setting the register. */
5091 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000)
5092 
5093 /*
5094  * Field : SPI Master Module - spim_1
5095  *
5096  * Used to disable signals from the FPGA fabric to the SPI master modules that
5097  * could potentially interfere with their normal operation.
5098  *
5099  * The array index corresponds to the SPI master module instance.
5100  *
5101  * Field Enumeration Values:
5102  *
5103  * Enum | Value | Description
5104  * :--------------------------------------|:------|:------------
5105  * ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS | 0x0 |
5106  * ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN | 0x1 |
5107  *
5108  * Field Access Macros:
5109  *
5110  */
5111 /*
5112  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1
5113  *
5114  */
5115 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS 0x0
5116 /*
5117  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1
5118  *
5119  */
5120 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN 0x1
5121 
5122 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field. */
5123 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_LSB 24
5124 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field. */
5125 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_MSB 24
5126 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field. */
5127 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_WIDTH 1
5128 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value. */
5129 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000
5130 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value. */
5131 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff
5132 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field. */
5133 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_RESET 0x0
5134 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 field value from a register. */
5135 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24)
5136 /* Produces a ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value suitable for setting the register. */
5137 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000)
5138 
5139 #ifndef __ASSEMBLY__
5140 /*
5141  * WARNING: The C register and register group struct declarations are provided for
5142  * convenience and illustrative purposes. They should, however, be used with
5143  * caution as the C language standard provides no guarantees about the alignment or
5144  * atomicity of device memory accesses. The recommended practice for writing
5145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5146  * alt_write_word() functions.
5147  *
5148  * The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_2.
5149  */
5150 struct ALT_SYSMGR_FPGAINTF_EN_2_s
5151 {
5152  uint32_t : 4; /* *UNDEFINED* */
5153  uint32_t nand : 1; /* NAND Flash Controller Module */
5154  uint32_t : 3; /* *UNDEFINED* */
5155  uint32_t sdmmc : 1; /* SD/MMC Controller Module */
5156  uint32_t : 7; /* *UNDEFINED* */
5157  uint32_t spim_0 : 1; /* SPI Master Module */
5158  uint32_t : 7; /* *UNDEFINED* */
5159  uint32_t spim_1 : 1; /* SPI Master Module */
5160  uint32_t : 7; /* *UNDEFINED* */
5161 };
5162 
5163 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_2. */
5164 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_2_s ALT_SYSMGR_FPGAINTF_EN_2_t;
5165 #endif /* __ASSEMBLY__ */
5166 
5167 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_2 register. */
5168 #define ALT_SYSMGR_FPGAINTF_EN_2_RESET 0x00000000
5169 /* The byte offset of the ALT_SYSMGR_FPGAINTF_EN_2 register from the beginning of the component. */
5170 #define ALT_SYSMGR_FPGAINTF_EN_2_OFST 0x6c
5171 
5172 /*
5173  * Register : FPGA interface Individual Enable Register - fpgaintf_en_3
5174  *
5175  * Used to disable individual interfaces between the FPGA and HPS.
5176  *
5177  * This register is reset only on a cold reset (ignores warm reset).
5178  *
5179  * Register Layout
5180  *
5181  * Bits | Access | Reset | Description
5182  * :--------|:-------|:------|:------------
5183  * [0] | RW | 0x0 | EMAC Module
5184  * [3:1] | ??? | 0x0 | *UNDEFINED*
5185  * [4] | RW | 0x0 | EMAC Module
5186  * [7:5] | ??? | 0x0 | *UNDEFINED*
5187  * [8] | RW | 0x0 | EMAC Module
5188  * [11:9] | ??? | 0x0 | *UNDEFINED*
5189  * [12] | RW | 0x0 | EMAC Module
5190  * [15:13] | ??? | 0x0 | *UNDEFINED*
5191  * [16] | RW | 0x0 | EMAC Module
5192  * [19:17] | ??? | 0x0 | *UNDEFINED*
5193  * [20] | RW | 0x0 | EMAC Module
5194  * [31:21] | ??? | 0x0 | *UNDEFINED*
5195  *
5196  */
5197 /*
5198  * Field : EMAC Module - emac_0
5199  *
5200  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5201  * potentially interfere with their normal operation.
5202  *
5203  * The array index corresponds to the EMAC module instance.
5204  *
5205  * Field Enumeration Values:
5206  *
5207  * Enum | Value | Description
5208  * :--------------------------------------|:------|:------------
5209  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_DIS | 0x0 |
5210  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_EN | 0x1 |
5211  *
5212  * Field Access Macros:
5213  *
5214  */
5215 /*
5216  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0
5217  *
5218  */
5219 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_DIS 0x0
5220 /*
5221  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0
5222  *
5223  */
5224 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_EN 0x1
5225 
5226 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field. */
5227 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_LSB 0
5228 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field. */
5229 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_MSB 0
5230 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field. */
5231 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_WIDTH 1
5232 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field value. */
5233 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET_MSK 0x00000001
5234 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field value. */
5235 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_CLR_MSK 0xfffffffe
5236 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field. */
5237 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_RESET 0x0
5238 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 field value from a register. */
5239 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_GET(value) (((value) & 0x00000001) >> 0)
5240 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0 register field value suitable for setting the register. */
5241 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET(value) (((value) << 0) & 0x00000001)
5242 
5243 /*
5244  * Field : EMAC Module - emac_0_switch
5245  *
5246  * EMAC FPGA interface switch Enable
5247  *
5248  * Field Enumeration Values:
5249  *
5250  * Enum | Value | Description
5251  * :---------------------------------------------|:------|:------------
5252  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DIS | 0x0 |
5253  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_EN | 0x1 |
5254  *
5255  * Field Access Macros:
5256  *
5257  */
5258 /*
5259  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH
5260  *
5261  */
5262 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DIS 0x0
5263 /*
5264  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH
5265  *
5266  */
5267 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_EN 0x1
5268 
5269 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5270 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_LSB 4
5271 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5272 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_MSB 4
5273 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5274 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_WIDTH 1
5275 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field value. */
5276 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET_MSK 0x00000010
5277 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field value. */
5278 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_CLR_MSK 0xffffffef
5279 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field. */
5280 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_RESET 0x0
5281 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH field value from a register. */
5282 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_GET(value) (((value) & 0x00000010) >> 4)
5283 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH register field value suitable for setting the register. */
5284 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET(value) (((value) << 4) & 0x00000010)
5285 
5286 /*
5287  * Field : EMAC Module - emac_1
5288  *
5289  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5290  * potentially interfere with their normal operation.
5291  *
5292  * The array index corresponds to the EMAC module instance.
5293  *
5294  * Field Enumeration Values:
5295  *
5296  * Enum | Value | Description
5297  * :--------------------------------------|:------|:------------
5298  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_DIS | 0x0 |
5299  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_EN | 0x1 |
5300  *
5301  * Field Access Macros:
5302  *
5303  */
5304 /*
5305  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1
5306  *
5307  */
5308 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_DIS 0x0
5309 /*
5310  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1
5311  *
5312  */
5313 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_EN 0x1
5314 
5315 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field. */
5316 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_LSB 8
5317 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field. */
5318 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_MSB 8
5319 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field. */
5320 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_WIDTH 1
5321 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field value. */
5322 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET_MSK 0x00000100
5323 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field value. */
5324 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_CLR_MSK 0xfffffeff
5325 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field. */
5326 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_RESET 0x0
5327 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 field value from a register. */
5328 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_GET(value) (((value) & 0x00000100) >> 8)
5329 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1 register field value suitable for setting the register. */
5330 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET(value) (((value) << 8) & 0x00000100)
5331 
5332 /*
5333  * Field : EMAC Module - emac_1_switch
5334  *
5335  * EMAC FPGA interface switch Enable
5336  *
5337  * Field Enumeration Values:
5338  *
5339  * Enum | Value | Description
5340  * :---------------------------------------------|:------|:------------
5341  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DIS | 0x0 |
5342  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_EN | 0x1 |
5343  *
5344  * Field Access Macros:
5345  *
5346  */
5347 /*
5348  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH
5349  *
5350  */
5351 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DIS 0x0
5352 /*
5353  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH
5354  *
5355  */
5356 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_EN 0x1
5357 
5358 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5359 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_LSB 12
5360 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5361 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_MSB 12
5362 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5363 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_WIDTH 1
5364 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field value. */
5365 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET_MSK 0x00001000
5366 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field value. */
5367 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_CLR_MSK 0xffffefff
5368 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field. */
5369 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_RESET 0x0
5370 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH field value from a register. */
5371 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_GET(value) (((value) & 0x00001000) >> 12)
5372 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH register field value suitable for setting the register. */
5373 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET(value) (((value) << 12) & 0x00001000)
5374 
5375 /*
5376  * Field : EMAC Module - emac_2
5377  *
5378  * Used to disable signals from the FPGA fabric to the EMAC modules that could
5379  * potentially interfere with their normal operation.
5380  *
5381  * The array index corresponds to the EMAC module instance.
5382  *
5383  * Field Enumeration Values:
5384  *
5385  * Enum | Value | Description
5386  * :--------------------------------------|:------|:------------
5387  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_DIS | 0x0 |
5388  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_EN | 0x1 |
5389  *
5390  * Field Access Macros:
5391  *
5392  */
5393 /*
5394  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2
5395  *
5396  */
5397 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_DIS 0x0
5398 /*
5399  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2
5400  *
5401  */
5402 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_EN 0x1
5403 
5404 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field. */
5405 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_LSB 16
5406 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field. */
5407 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_MSB 16
5408 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field. */
5409 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_WIDTH 1
5410 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field value. */
5411 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET_MSK 0x00010000
5412 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field value. */
5413 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_CLR_MSK 0xfffeffff
5414 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field. */
5415 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_RESET 0x0
5416 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 field value from a register. */
5417 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_GET(value) (((value) & 0x00010000) >> 16)
5418 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2 register field value suitable for setting the register. */
5419 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET(value) (((value) << 16) & 0x00010000)
5420 
5421 /*
5422  * Field : EMAC Module - emac_2_switch
5423  *
5424  * EMAC FPGA interface switch Enable
5425  *
5426  * Field Enumeration Values:
5427  *
5428  * Enum | Value | Description
5429  * :---------------------------------------------|:------|:------------
5430  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DIS | 0x0 |
5431  * ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_EN | 0x1 |
5432  *
5433  * Field Access Macros:
5434  *
5435  */
5436 /*
5437  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH
5438  *
5439  */
5440 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DIS 0x0
5441 /*
5442  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH
5443  *
5444  */
5445 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_EN 0x1
5446 
5447 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5448 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_LSB 20
5449 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5450 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_MSB 20
5451 /* The width in bits of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5452 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_WIDTH 1
5453 /* The mask used to set the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field value. */
5454 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET_MSK 0x00100000
5455 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field value. */
5456 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_CLR_MSK 0xffefffff
5457 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field. */
5458 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_RESET 0x0
5459 /* Extracts the ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH field value from a register. */
5460 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_GET(value) (((value) & 0x00100000) >> 20)
5461 /* Produces a ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH register field value suitable for setting the register. */
5462 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET(value) (((value) << 20) & 0x00100000)
5463 
5464 #ifndef __ASSEMBLY__
5465 /*
5466  * WARNING: The C register and register group struct declarations are provided for
5467  * convenience and illustrative purposes. They should, however, be used with
5468  * caution as the C language standard provides no guarantees about the alignment or
5469  * atomicity of device memory accesses. The recommended practice for writing
5470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5471  * alt_write_word() functions.
5472  *
5473  * The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_3.
5474  */
5475 struct ALT_SYSMGR_FPGAINTF_EN_3_s
5476 {
5477  uint32_t emac_0 : 1; /* EMAC Module */
5478  uint32_t : 3; /* *UNDEFINED* */
5479  uint32_t emac_0_switch : 1; /* EMAC Module */
5480  uint32_t : 3; /* *UNDEFINED* */
5481  uint32_t emac_1 : 1; /* EMAC Module */
5482  uint32_t : 3; /* *UNDEFINED* */
5483  uint32_t emac_1_switch : 1; /* EMAC Module */
5484  uint32_t : 3; /* *UNDEFINED* */
5485  uint32_t emac_2 : 1; /* EMAC Module */
5486  uint32_t : 3; /* *UNDEFINED* */
5487  uint32_t emac_2_switch : 1; /* EMAC Module */
5488  uint32_t : 11; /* *UNDEFINED* */
5489 };
5490 
5491 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_3. */
5492 typedef volatile struct ALT_SYSMGR_FPGAINTF_EN_3_s ALT_SYSMGR_FPGAINTF_EN_3_t;
5493 #endif /* __ASSEMBLY__ */
5494 
5495 /* The reset value of the ALT_SYSMGR_FPGAINTF_EN_3 register. */
5496 #define ALT_SYSMGR_FPGAINTF_EN_3_RESET 0x00000000
5497 /* The byte offset of the ALT_SYSMGR_FPGAINTF_EN_3 register from the beginning of the component. */
5498 #define ALT_SYSMGR_FPGAINTF_EN_3_OFST 0x70
5499 
5500 /*
5501  * Register : noc_addr_remap_value
5502  *
5503  * Address remap register. This register drives the remap bits for the NOC.
5504  *
5505  * This is read / write register.
5506  *
5507  * Register Layout
5508  *
5509  * Bits | Access | Reset | Description
5510  * :-------|:-------|:------|:---------------------------------------
5511  * [0] | RW | 0x0 | ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0
5512  * [1] | RW | 0x0 | ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1
5513  * [31:2] | ??? | 0x0 | *UNDEFINED*
5514  *
5515  */
5516 /*
5517  * Field : remap0
5518  *
5519  * if this bit is 0 ROM is also mapped to base address 0x0000_0000
5520  *
5521  * if this bit is 1 ROM is NOT available at base address 0x0000_0000
5522  *
5523  * Note:
5524  *
5525  * ROM is always available at base address 0xFFFC_0000
5526  *
5527  * RAM is always available at base address 0xFFE0_0000
5528  *
5529  * Field Access Macros:
5530  *
5531  */
5532 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field. */
5533 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_LSB 0
5534 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field. */
5535 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_MSB 0
5536 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field. */
5537 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_WIDTH 1
5538 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field value. */
5539 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET_MSK 0x00000001
5540 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field value. */
5541 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_CLR_MSK 0xfffffffe
5542 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field. */
5543 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_RESET 0x0
5544 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 field value from a register. */
5545 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5546 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 register field value suitable for setting the register. */
5547 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5548 
5549 /*
5550  * Field : remap1
5551  *
5552  * if this bit is 0 RAM is NOT available at base address 0x0000_0000
5553  *
5554  * if this bit is 1 RAM is also mapped to base address 0x0000_0000, as long as ROM
5555  * is not being mapped to the same base address because of remap0
5556  *
5557  * Note:
5558  *
5559  * ROM is always available at base address 0xFFFC_0000
5560  *
5561  * RAM is always available at base address 0xFFE0_0000
5562  *
5563  * Field Access Macros:
5564  *
5565  */
5566 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field. */
5567 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_LSB 1
5568 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field. */
5569 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_MSB 1
5570 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field. */
5571 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_WIDTH 1
5572 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field value. */
5573 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET_MSK 0x00000002
5574 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field value. */
5575 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_CLR_MSK 0xfffffffd
5576 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field. */
5577 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_RESET 0x0
5578 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 field value from a register. */
5579 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5580 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 register field value suitable for setting the register. */
5581 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5582 
5583 #ifndef __ASSEMBLY__
5584 /*
5585  * WARNING: The C register and register group struct declarations are provided for
5586  * convenience and illustrative purposes. They should, however, be used with
5587  * caution as the C language standard provides no guarantees about the alignment or
5588  * atomicity of device memory accesses. The recommended practice for writing
5589  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5590  * alt_write_word() functions.
5591  *
5592  * The struct declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_VALUE.
5593  */
5594 struct ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_s
5595 {
5596  uint32_t remap0 : 1; /* ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0 */
5597  uint32_t remap1 : 1; /* ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1 */
5598  uint32_t : 30; /* *UNDEFINED* */
5599 };
5600 
5601 /* The typedef declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_VALUE. */
5602 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_s ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_t;
5603 #endif /* __ASSEMBLY__ */
5604 
5605 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE register. */
5606 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_RESET 0x00000000
5607 /* The byte offset of the ALT_SYSMGR_NOC_ADDR_REMAP_VALUE register from the beginning of the component. */
5608 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_OFST 0x80
5609 
5610 /*
5611  * Register : noc_addr_remap_set
5612  *
5613  * This is a Write 1 to Set register.
5614  *
5615  * Writing 0 is ignored, and writing 1 to a specific bit field sets the specific
5616  * remap bit.
5617  *
5618  * Reads should not return an error, but the actual read value is "Undefined" .
5619  *
5620  * Register Layout
5621  *
5622  * Bits | Access | Reset | Description
5623  * :-------|:-------|:------|:-------------------
5624  * [0] | RW | 0x0 | Remap Set register
5625  * [1] | RW | 0x0 | Remap Set register
5626  * [31:2] | ??? | 0x0 | *UNDEFINED*
5627  *
5628  */
5629 /*
5630  * Field : Remap Set register - remap0
5631  *
5632  * Field Access Macros:
5633  *
5634  */
5635 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field. */
5636 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_LSB 0
5637 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field. */
5638 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_MSB 0
5639 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field. */
5640 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_WIDTH 1
5641 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field value. */
5642 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET_MSK 0x00000001
5643 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field value. */
5644 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_CLR_MSK 0xfffffffe
5645 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field. */
5646 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_RESET 0x0
5647 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 field value from a register. */
5648 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5649 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0 register field value suitable for setting the register. */
5650 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5651 
5652 /*
5653  * Field : Remap Set register - remap1
5654  *
5655  * Field Access Macros:
5656  *
5657  */
5658 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field. */
5659 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_LSB 1
5660 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field. */
5661 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_MSB 1
5662 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field. */
5663 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_WIDTH 1
5664 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field value. */
5665 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET_MSK 0x00000002
5666 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field value. */
5667 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_CLR_MSK 0xfffffffd
5668 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field. */
5669 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_RESET 0x0
5670 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 field value from a register. */
5671 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5672 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1 register field value suitable for setting the register. */
5673 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5674 
5675 #ifndef __ASSEMBLY__
5676 /*
5677  * WARNING: The C register and register group struct declarations are provided for
5678  * convenience and illustrative purposes. They should, however, be used with
5679  * caution as the C language standard provides no guarantees about the alignment or
5680  * atomicity of device memory accesses. The recommended practice for writing
5681  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5682  * alt_write_word() functions.
5683  *
5684  * The struct declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_SET.
5685  */
5686 struct ALT_SYSMGR_NOC_ADDR_REMAP_SET_s
5687 {
5688  uint32_t remap0 : 1; /* Remap Set register */
5689  uint32_t remap1 : 1; /* Remap Set register */
5690  uint32_t : 30; /* *UNDEFINED* */
5691 };
5692 
5693 /* The typedef declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_SET. */
5694 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_SET_s ALT_SYSMGR_NOC_ADDR_REMAP_SET_t;
5695 #endif /* __ASSEMBLY__ */
5696 
5697 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_SET register. */
5698 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_RESET 0x00000000
5699 /* The byte offset of the ALT_SYSMGR_NOC_ADDR_REMAP_SET register from the beginning of the component. */
5700 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_OFST 0x84
5701 
5702 /*
5703  * Register : noc_addr_remap_clear
5704  *
5705  * This is a Write 1 to Clear register.
5706  *
5707  * Writing 0 is ignored, and writing 1 to a specific bit field Clears the specific
5708  * remap bit.
5709  *
5710  * Reads should not return an error, but the actual read value is "Undefined" .
5711  *
5712  * Register Layout
5713  *
5714  * Bits | Access | Reset | Description
5715  * :-------|:-------|:------|:-------------------
5716  * [0] | RW | 0x0 | Remap Set register
5717  * [1] | RW | 0x0 | Remap Set register
5718  * [31:2] | ??? | 0x0 | *UNDEFINED*
5719  *
5720  */
5721 /*
5722  * Field : Remap Set register - remap0
5723  *
5724  * Field Access Macros:
5725  *
5726  */
5727 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field. */
5728 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_LSB 0
5729 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field. */
5730 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_MSB 0
5731 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field. */
5732 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_WIDTH 1
5733 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field value. */
5734 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET_MSK 0x00000001
5735 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field value. */
5736 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_CLR_MSK 0xfffffffe
5737 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field. */
5738 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_RESET 0x0
5739 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 field value from a register. */
5740 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5741 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0 register field value suitable for setting the register. */
5742 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5743 
5744 /*
5745  * Field : Remap Set register - remap1
5746  *
5747  * Field Access Macros:
5748  *
5749  */
5750 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field. */
5751 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_LSB 1
5752 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field. */
5753 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_MSB 1
5754 /* The width in bits of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field. */
5755 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_WIDTH 1
5756 /* The mask used to set the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field value. */
5757 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET_MSK 0x00000002
5758 /* The mask used to clear the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field value. */
5759 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_CLR_MSK 0xfffffffd
5760 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field. */
5761 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_RESET 0x0
5762 /* Extracts the ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 field value from a register. */
5763 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5764 /* Produces a ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1 register field value suitable for setting the register. */
5765 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5766 
5767 #ifndef __ASSEMBLY__
5768 /*
5769  * WARNING: The C register and register group struct declarations are provided for
5770  * convenience and illustrative purposes. They should, however, be used with
5771  * caution as the C language standard provides no guarantees about the alignment or
5772  * atomicity of device memory accesses. The recommended practice for writing
5773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5774  * alt_write_word() functions.
5775  *
5776  * The struct declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_CLR.
5777  */
5778 struct ALT_SYSMGR_NOC_ADDR_REMAP_CLR_s
5779 {
5780  uint32_t remap0 : 1; /* Remap Set register */
5781  uint32_t remap1 : 1; /* Remap Set register */
5782  uint32_t : 30; /* *UNDEFINED* */
5783 };
5784 
5785 /* The typedef declaration for register ALT_SYSMGR_NOC_ADDR_REMAP_CLR. */
5786 typedef volatile struct ALT_SYSMGR_NOC_ADDR_REMAP_CLR_s ALT_SYSMGR_NOC_ADDR_REMAP_CLR_t;
5787 #endif /* __ASSEMBLY__ */
5788 
5789 /* The reset value of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR register. */
5790 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_RESET 0x00000000
5791 /* The byte offset of the ALT_SYSMGR_NOC_ADDR_REMAP_CLR register from the beginning of the component. */
5792 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_OFST 0x88
5793 
5794 /*
5795  * Register : ecc_intmask_value
5796  *
5797  * ECC interrupt mask register.
5798  *
5799  * This is a read/write register.
5800  *
5801  * Register Layout
5802  *
5803  * Bits | Access | Reset | Description
5804  * :--------|:-------|:------|:-------------------
5805  * [0] | RW | 0x0 | Interrupt Mask Set
5806  * [1] | RW | 0x0 | Interrupt Mask Set
5807  * [2] | RW | 0x0 | Interrupt Mask Set
5808  * [3] | RW | 0x0 | Interrupt Mask Set
5809  * [4] | RW | 0x0 | Interrupt Mask Set
5810  * [5] | RW | 0x0 | Interrupt Mask Set
5811  * [6] | RW | 0x0 | Interrupt Mask Set
5812  * [7] | RW | 0x0 | Interrupt Mask Set
5813  * [8] | RW | 0x0 | Interrupt Mask Set
5814  * [9] | RW | 0x0 | Interrupt Mask Set
5815  * [10] | RW | 0x0 | Interrupt Mask Set
5816  * [11] | RW | 0x0 | Interrupt Mask Set
5817  * [12] | RW | 0x0 | Interrupt Mask Set
5818  * [13] | RW | 0x0 | Interrupt Mask Set
5819  * [14] | RW | 0x0 | Interrupt Mask Set
5820  * [15] | RW | 0x0 | Interrupt Mask Set
5821  * [16] | RW | 0x0 | Interrupt Mask Set
5822  * [17] | RW | 0x0 | Interrupt Mask Set
5823  * [18] | RW | 0x0 | Interrupt Mask Set
5824  * [31:19] | ??? | 0x0 | *UNDEFINED*
5825  *
5826  */
5827 /*
5828  * Field : Interrupt Mask Set - l2
5829  *
5830  * Field Access Macros:
5831  *
5832  */
5833 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field. */
5834 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_LSB 0
5835 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field. */
5836 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_MSB 0
5837 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field. */
5838 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_WIDTH 1
5839 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value. */
5840 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET_MSK 0x00000001
5841 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value. */
5842 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_CLR_MSK 0xfffffffe
5843 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field. */
5844 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_RESET 0x0
5845 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 field value from a register. */
5846 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_GET(value) (((value) & 0x00000001) >> 0)
5847 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value suitable for setting the register. */
5848 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET(value) (((value) << 0) & 0x00000001)
5849 
5850 /*
5851  * Field : Interrupt Mask Set - ocram
5852  *
5853  * Field Access Macros:
5854  *
5855  */
5856 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field. */
5857 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_LSB 1
5858 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field. */
5859 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_MSB 1
5860 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field. */
5861 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_WIDTH 1
5862 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value. */
5863 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET_MSK 0x00000002
5864 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value. */
5865 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_CLR_MSK 0xfffffffd
5866 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field. */
5867 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_RESET 0x0
5868 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM field value from a register. */
5869 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
5870 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value suitable for setting the register. */
5871 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET(value) (((value) << 1) & 0x00000002)
5872 
5873 /*
5874  * Field : Interrupt Mask Set - usb0
5875  *
5876  * Field Access Macros:
5877  *
5878  */
5879 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field. */
5880 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_LSB 2
5881 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field. */
5882 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_MSB 2
5883 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field. */
5884 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_WIDTH 1
5885 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value. */
5886 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET_MSK 0x00000004
5887 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value. */
5888 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_CLR_MSK 0xfffffffb
5889 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field. */
5890 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_RESET 0x0
5891 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 field value from a register. */
5892 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_GET(value) (((value) & 0x00000004) >> 2)
5893 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value suitable for setting the register. */
5894 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET(value) (((value) << 2) & 0x00000004)
5895 
5896 /*
5897  * Field : Interrupt Mask Set - usb1
5898  *
5899  * Field Access Macros:
5900  *
5901  */
5902 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field. */
5903 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_LSB 3
5904 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field. */
5905 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_MSB 3
5906 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field. */
5907 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_WIDTH 1
5908 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value. */
5909 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET_MSK 0x00000008
5910 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value. */
5911 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_CLR_MSK 0xfffffff7
5912 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field. */
5913 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_RESET 0x0
5914 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 field value from a register. */
5915 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_GET(value) (((value) & 0x00000008) >> 3)
5916 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value suitable for setting the register. */
5917 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET(value) (((value) << 3) & 0x00000008)
5918 
5919 /*
5920  * Field : Interrupt Mask Set - emac0_rx
5921  *
5922  * Field Access Macros:
5923  *
5924  */
5925 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field. */
5926 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_LSB 4
5927 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field. */
5928 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_MSB 4
5929 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field. */
5930 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_WIDTH 1
5931 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value. */
5932 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET_MSK 0x00000010
5933 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value. */
5934 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_CLR_MSK 0xffffffef
5935 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field. */
5936 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_RESET 0x0
5937 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX field value from a register. */
5938 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
5939 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value suitable for setting the register. */
5940 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
5941 
5942 /*
5943  * Field : Interrupt Mask Set - emac0_tx
5944  *
5945  * Field Access Macros:
5946  *
5947  */
5948 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field. */
5949 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_LSB 5
5950 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field. */
5951 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_MSB 5
5952 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field. */
5953 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_WIDTH 1
5954 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value. */
5955 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET_MSK 0x00000020
5956 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value. */
5957 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_CLR_MSK 0xffffffdf
5958 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field. */
5959 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_RESET 0x0
5960 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX field value from a register. */
5961 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
5962 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value suitable for setting the register. */
5963 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
5964 
5965 /*
5966  * Field : Interrupt Mask Set - emac1_rx
5967  *
5968  * Field Access Macros:
5969  *
5970  */
5971 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field. */
5972 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_LSB 6
5973 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field. */
5974 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_MSB 6
5975 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field. */
5976 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_WIDTH 1
5977 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value. */
5978 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET_MSK 0x00000040
5979 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value. */
5980 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_CLR_MSK 0xffffffbf
5981 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field. */
5982 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_RESET 0x0
5983 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX field value from a register. */
5984 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
5985 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value suitable for setting the register. */
5986 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
5987 
5988 /*
5989  * Field : Interrupt Mask Set - emac1_tx
5990  *
5991  * Field Access Macros:
5992  *
5993  */
5994 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field. */
5995 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_LSB 7
5996 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field. */
5997 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_MSB 7
5998 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field. */
5999 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_WIDTH 1
6000 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value. */
6001 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET_MSK 0x00000080
6002 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value. */
6003 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_CLR_MSK 0xffffff7f
6004 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field. */
6005 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_RESET 0x0
6006 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX field value from a register. */
6007 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6008 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value suitable for setting the register. */
6009 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6010 
6011 /*
6012  * Field : Interrupt Mask Set - emac2_rx
6013  *
6014  * Field Access Macros:
6015  *
6016  */
6017 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field. */
6018 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_LSB 8
6019 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field. */
6020 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_MSB 8
6021 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field. */
6022 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_WIDTH 1
6023 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value. */
6024 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET_MSK 0x00000100
6025 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value. */
6026 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_CLR_MSK 0xfffffeff
6027 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field. */
6028 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_RESET 0x0
6029 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX field value from a register. */
6030 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6031 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value suitable for setting the register. */
6032 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6033 
6034 /*
6035  * Field : Interrupt Mask Set - emac2_tx
6036  *
6037  * Field Access Macros:
6038  *
6039  */
6040 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field. */
6041 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_LSB 9
6042 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field. */
6043 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_MSB 9
6044 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field. */
6045 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_WIDTH 1
6046 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value. */
6047 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET_MSK 0x00000200
6048 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value. */
6049 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_CLR_MSK 0xfffffdff
6050 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field. */
6051 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_RESET 0x0
6052 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX field value from a register. */
6053 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6054 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value suitable for setting the register. */
6055 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6056 
6057 /*
6058  * Field : Interrupt Mask Set - dma
6059  *
6060  * Field Access Macros:
6061  *
6062  */
6063 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field. */
6064 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_LSB 10
6065 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field. */
6066 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_MSB 10
6067 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field. */
6068 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_WIDTH 1
6069 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value. */
6070 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET_MSK 0x00000400
6071 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value. */
6072 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_CLR_MSK 0xfffffbff
6073 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field. */
6074 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_RESET 0x0
6075 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA field value from a register. */
6076 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_GET(value) (((value) & 0x00000400) >> 10)
6077 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value suitable for setting the register. */
6078 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET(value) (((value) << 10) & 0x00000400)
6079 
6080 /*
6081  * Field : Interrupt Mask Set - nand_buf
6082  *
6083  * Field Access Macros:
6084  *
6085  */
6086 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field. */
6087 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_LSB 11
6088 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field. */
6089 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_MSB 11
6090 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field. */
6091 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_WIDTH 1
6092 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value. */
6093 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET_MSK 0x00000800
6094 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value. */
6095 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_CLR_MSK 0xfffff7ff
6096 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field. */
6097 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_RESET 0x0
6098 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF field value from a register. */
6099 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6100 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value suitable for setting the register. */
6101 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6102 
6103 /*
6104  * Field : Interrupt Mask Set - nand_wr
6105  *
6106  * Field Access Macros:
6107  *
6108  */
6109 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field. */
6110 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_LSB 12
6111 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field. */
6112 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_MSB 12
6113 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field. */
6114 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_WIDTH 1
6115 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value. */
6116 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET_MSK 0x00001000
6117 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value. */
6118 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_CLR_MSK 0xffffefff
6119 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field. */
6120 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_RESET 0x0
6121 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR field value from a register. */
6122 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6123 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value suitable for setting the register. */
6124 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6125 
6126 /*
6127  * Field : Interrupt Mask Set - nand_rd
6128  *
6129  * Field Access Macros:
6130  *
6131  */
6132 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field. */
6133 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_LSB 13
6134 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field. */
6135 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_MSB 13
6136 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field. */
6137 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_WIDTH 1
6138 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value. */
6139 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET_MSK 0x00002000
6140 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value. */
6141 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_CLR_MSK 0xffffdfff
6142 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field. */
6143 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_RESET 0x0
6144 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD field value from a register. */
6145 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6146 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value suitable for setting the register. */
6147 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6148 
6149 /*
6150  * Field : Interrupt Mask Set - qspi
6151  *
6152  * Field Access Macros:
6153  *
6154  */
6155 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field. */
6156 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_LSB 14
6157 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field. */
6158 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_MSB 14
6159 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field. */
6160 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_WIDTH 1
6161 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value. */
6162 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET_MSK 0x00004000
6163 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value. */
6164 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_CLR_MSK 0xffffbfff
6165 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field. */
6166 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_RESET 0x0
6167 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI field value from a register. */
6168 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6169 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value suitable for setting the register. */
6170 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET(value) (((value) << 14) & 0x00004000)
6171 
6172 /*
6173  * Field : Interrupt Mask Set - sdmmca
6174  *
6175  * Field Access Macros:
6176  *
6177  */
6178 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field. */
6179 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_LSB 15
6180 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field. */
6181 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_MSB 15
6182 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field. */
6183 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_WIDTH 1
6184 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value. */
6185 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET_MSK 0x00008000
6186 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value. */
6187 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_CLR_MSK 0xffff7fff
6188 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field. */
6189 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_RESET 0x0
6190 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA field value from a register. */
6191 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6192 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value suitable for setting the register. */
6193 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6194 
6195 /*
6196  * Field : Interrupt Mask Set - sdmmcb
6197  *
6198  * Field Access Macros:
6199  *
6200  */
6201 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field. */
6202 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_LSB 16
6203 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field. */
6204 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_MSB 16
6205 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field. */
6206 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_WIDTH 1
6207 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value. */
6208 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET_MSK 0x00010000
6209 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value. */
6210 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_CLR_MSK 0xfffeffff
6211 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field. */
6212 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_RESET 0x0
6213 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB field value from a register. */
6214 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6215 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value suitable for setting the register. */
6216 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6217 
6218 /*
6219  * Field : Interrupt Mask Set - ddr0
6220  *
6221  * Field Access Macros:
6222  *
6223  */
6224 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field. */
6225 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_LSB 17
6226 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field. */
6227 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_MSB 17
6228 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field. */
6229 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_WIDTH 1
6230 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value. */
6231 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET_MSK 0x00020000
6232 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value. */
6233 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_CLR_MSK 0xfffdffff
6234 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field. */
6235 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_RESET 0x0
6236 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 field value from a register. */
6237 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6238 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value suitable for setting the register. */
6239 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET(value) (((value) << 17) & 0x00020000)
6240 
6241 /*
6242  * Field : Interrupt Mask Set - ddr1
6243  *
6244  * Field Access Macros:
6245  *
6246  */
6247 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field. */
6248 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_LSB 18
6249 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field. */
6250 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_MSB 18
6251 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field. */
6252 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_WIDTH 1
6253 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value. */
6254 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET_MSK 0x00040000
6255 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value. */
6256 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_CLR_MSK 0xfffbffff
6257 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field. */
6258 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_RESET 0x0
6259 /* Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 field value from a register. */
6260 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6261 /* Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value suitable for setting the register. */
6262 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET(value) (((value) << 18) & 0x00040000)
6263 
6264 #ifndef __ASSEMBLY__
6265 /*
6266  * WARNING: The C register and register group struct declarations are provided for
6267  * convenience and illustrative purposes. They should, however, be used with
6268  * caution as the C language standard provides no guarantees about the alignment or
6269  * atomicity of device memory accesses. The recommended practice for writing
6270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6271  * alt_write_word() functions.
6272  *
6273  * The struct declaration for register ALT_SYSMGR_ECC_INTMSK_VALUE.
6274  */
6275 struct ALT_SYSMGR_ECC_INTMSK_VALUE_s
6276 {
6277  uint32_t l2 : 1; /* Interrupt Mask Set */
6278  uint32_t ocram : 1; /* Interrupt Mask Set */
6279  uint32_t usb0 : 1; /* Interrupt Mask Set */
6280  uint32_t usb1 : 1; /* Interrupt Mask Set */
6281  uint32_t emac0_rx : 1; /* Interrupt Mask Set */
6282  uint32_t emac0_tx : 1; /* Interrupt Mask Set */
6283  uint32_t emac1_rx : 1; /* Interrupt Mask Set */
6284  uint32_t emac1_tx : 1; /* Interrupt Mask Set */
6285  uint32_t emac2_rx : 1; /* Interrupt Mask Set */
6286  uint32_t emac2_tx : 1; /* Interrupt Mask Set */
6287  uint32_t dma : 1; /* Interrupt Mask Set */
6288  uint32_t nand_buf : 1; /* Interrupt Mask Set */
6289  uint32_t nand_wr : 1; /* Interrupt Mask Set */
6290  uint32_t nand_rd : 1; /* Interrupt Mask Set */
6291  uint32_t qspi : 1; /* Interrupt Mask Set */
6292  uint32_t sdmmca : 1; /* Interrupt Mask Set */
6293  uint32_t sdmmcb : 1; /* Interrupt Mask Set */
6294  uint32_t ddr0 : 1; /* Interrupt Mask Set */
6295  uint32_t ddr1 : 1; /* Interrupt Mask Set */
6296  uint32_t : 13; /* *UNDEFINED* */
6297 };
6298 
6299 /* The typedef declaration for register ALT_SYSMGR_ECC_INTMSK_VALUE. */
6300 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_VALUE_s ALT_SYSMGR_ECC_INTMSK_VALUE_t;
6301 #endif /* __ASSEMBLY__ */
6302 
6303 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE register. */
6304 #define ALT_SYSMGR_ECC_INTMSK_VALUE_RESET 0x00000000
6305 /* The byte offset of the ALT_SYSMGR_ECC_INTMSK_VALUE register from the beginning of the component. */
6306 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OFST 0x90
6307 
6308 /*
6309  * Register : ECC interrupt mask Set register - ecc_intmask_set
6310  *
6311  * Write 1 to set a specific modules interrupt mask.
6312  *
6313  * Reads should not return an error, but the actual read value is "Undefined" .
6314  *
6315  * Register Layout
6316  *
6317  * Bits | Access | Reset | Description
6318  * :--------|:-------|:------|:-------------------
6319  * [0] | RW | 0x0 | Interrupt Mask Set
6320  * [1] | RW | 0x0 | Interrupt Mask Set
6321  * [2] | RW | 0x0 | Interrupt Mask Set
6322  * [3] | RW | 0x0 | Interrupt Mask Set
6323  * [4] | RW | 0x0 | Interrupt Mask Set
6324  * [5] | RW | 0x0 | Interrupt Mask Set
6325  * [6] | RW | 0x0 | Interrupt Mask Set
6326  * [7] | RW | 0x0 | Interrupt Mask Set
6327  * [8] | RW | 0x0 | Interrupt Mask Set
6328  * [9] | RW | 0x0 | Interrupt Mask Set
6329  * [10] | RW | 0x0 | Interrupt Mask Set
6330  * [11] | RW | 0x0 | Interrupt Mask Set
6331  * [12] | RW | 0x0 | Interrupt Mask Set
6332  * [13] | RW | 0x0 | Interrupt Mask Set
6333  * [14] | RW | 0x0 | Interrupt Mask Set
6334  * [15] | RW | 0x0 | Interrupt Mask Set
6335  * [16] | RW | 0x0 | Interrupt Mask Set
6336  * [17] | RW | 0x0 | Interrupt Mask Set
6337  * [18] | RW | 0x0 | Interrupt Mask Set
6338  * [31:19] | ??? | 0x0 | *UNDEFINED*
6339  *
6340  */
6341 /*
6342  * Field : Interrupt Mask Set - l2
6343  *
6344  * Field Access Macros:
6345  *
6346  */
6347 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field. */
6348 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_LSB 0
6349 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field. */
6350 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_MSB 0
6351 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field. */
6352 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_WIDTH 1
6353 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field value. */
6354 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET_MSK 0x00000001
6355 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field value. */
6356 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_CLR_MSK 0xfffffffe
6357 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_L2 register field. */
6358 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_RESET 0x0
6359 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_L2 field value from a register. */
6360 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_GET(value) (((value) & 0x00000001) >> 0)
6361 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_L2 register field value suitable for setting the register. */
6362 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET(value) (((value) << 0) & 0x00000001)
6363 
6364 /*
6365  * Field : Interrupt Mask Set - ocram
6366  *
6367  * Field Access Macros:
6368  *
6369  */
6370 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field. */
6371 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_LSB 1
6372 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field. */
6373 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_MSB 1
6374 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field. */
6375 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_WIDTH 1
6376 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field value. */
6377 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET_MSK 0x00000002
6378 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field value. */
6379 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_CLR_MSK 0xfffffffd
6380 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field. */
6381 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_RESET 0x0
6382 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_OCRAM field value from a register. */
6383 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6384 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_OCRAM register field value suitable for setting the register. */
6385 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6386 
6387 /*
6388  * Field : Interrupt Mask Set - usb0
6389  *
6390  * Field Access Macros:
6391  *
6392  */
6393 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field. */
6394 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_LSB 2
6395 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field. */
6396 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_MSB 2
6397 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field. */
6398 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_WIDTH 1
6399 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field value. */
6400 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET_MSK 0x00000004
6401 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field value. */
6402 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_CLR_MSK 0xfffffffb
6403 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field. */
6404 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_RESET 0x0
6405 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_USB0 field value from a register. */
6406 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_GET(value) (((value) & 0x00000004) >> 2)
6407 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_USB0 register field value suitable for setting the register. */
6408 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET(value) (((value) << 2) & 0x00000004)
6409 
6410 /*
6411  * Field : Interrupt Mask Set - usb1
6412  *
6413  * Field Access Macros:
6414  *
6415  */
6416 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field. */
6417 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_LSB 3
6418 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field. */
6419 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_MSB 3
6420 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field. */
6421 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_WIDTH 1
6422 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field value. */
6423 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET_MSK 0x00000008
6424 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field value. */
6425 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_CLR_MSK 0xfffffff7
6426 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field. */
6427 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_RESET 0x0
6428 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_USB1 field value from a register. */
6429 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_GET(value) (((value) & 0x00000008) >> 3)
6430 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_USB1 register field value suitable for setting the register. */
6431 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET(value) (((value) << 3) & 0x00000008)
6432 
6433 /*
6434  * Field : Interrupt Mask Set - emac0_rx
6435  *
6436  * Field Access Macros:
6437  *
6438  */
6439 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field. */
6440 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_LSB 4
6441 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field. */
6442 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_MSB 4
6443 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field. */
6444 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_WIDTH 1
6445 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field value. */
6446 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET_MSK 0x00000010
6447 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field value. */
6448 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_CLR_MSK 0xffffffef
6449 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field. */
6450 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_RESET 0x0
6451 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX field value from a register. */
6452 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6453 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX register field value suitable for setting the register. */
6454 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6455 
6456 /*
6457  * Field : Interrupt Mask Set - emac0_tx
6458  *
6459  * Field Access Macros:
6460  *
6461  */
6462 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field. */
6463 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_LSB 5
6464 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field. */
6465 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_MSB 5
6466 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field. */
6467 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_WIDTH 1
6468 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field value. */
6469 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET_MSK 0x00000020
6470 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field value. */
6471 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_CLR_MSK 0xffffffdf
6472 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field. */
6473 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_RESET 0x0
6474 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX field value from a register. */
6475 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6476 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX register field value suitable for setting the register. */
6477 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6478 
6479 /*
6480  * Field : Interrupt Mask Set - emac1_rx
6481  *
6482  * Field Access Macros:
6483  *
6484  */
6485 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field. */
6486 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_LSB 6
6487 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field. */
6488 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_MSB 6
6489 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field. */
6490 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_WIDTH 1
6491 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field value. */
6492 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET_MSK 0x00000040
6493 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field value. */
6494 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_CLR_MSK 0xffffffbf
6495 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field. */
6496 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_RESET 0x0
6497 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX field value from a register. */
6498 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
6499 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX register field value suitable for setting the register. */
6500 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
6501 
6502 /*
6503  * Field : Interrupt Mask Set - emac1_tx
6504  *
6505  * Field Access Macros:
6506  *
6507  */
6508 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field. */
6509 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_LSB 7
6510 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field. */
6511 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_MSB 7
6512 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field. */
6513 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_WIDTH 1
6514 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field value. */
6515 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET_MSK 0x00000080
6516 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field value. */
6517 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_CLR_MSK 0xffffff7f
6518 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field. */
6519 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_RESET 0x0
6520 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX field value from a register. */
6521 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6522 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX register field value suitable for setting the register. */
6523 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6524 
6525 /*
6526  * Field : Interrupt Mask Set - emac2_rx
6527  *
6528  * Field Access Macros:
6529  *
6530  */
6531 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field. */
6532 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_LSB 8
6533 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field. */
6534 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_MSB 8
6535 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field. */
6536 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_WIDTH 1
6537 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field value. */
6538 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET_MSK 0x00000100
6539 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field value. */
6540 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_CLR_MSK 0xfffffeff
6541 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field. */
6542 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_RESET 0x0
6543 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX field value from a register. */
6544 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6545 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX register field value suitable for setting the register. */
6546 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6547 
6548 /*
6549  * Field : Interrupt Mask Set - emac2_tx
6550  *
6551  * Field Access Macros:
6552  *
6553  */
6554 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field. */
6555 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_LSB 9
6556 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field. */
6557 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_MSB 9
6558 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field. */
6559 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_WIDTH 1
6560 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field value. */
6561 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET_MSK 0x00000200
6562 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field value. */
6563 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_CLR_MSK 0xfffffdff
6564 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field. */
6565 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_RESET 0x0
6566 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX field value from a register. */
6567 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6568 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX register field value suitable for setting the register. */
6569 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6570 
6571 /*
6572  * Field : Interrupt Mask Set - dma
6573  *
6574  * Field Access Macros:
6575  *
6576  */
6577 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field. */
6578 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_LSB 10
6579 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field. */
6580 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_MSB 10
6581 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field. */
6582 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_WIDTH 1
6583 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field value. */
6584 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET_MSK 0x00000400
6585 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field value. */
6586 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_CLR_MSK 0xfffffbff
6587 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_DMA register field. */
6588 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_RESET 0x0
6589 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_DMA field value from a register. */
6590 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_GET(value) (((value) & 0x00000400) >> 10)
6591 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_DMA register field value suitable for setting the register. */
6592 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET(value) (((value) << 10) & 0x00000400)
6593 
6594 /*
6595  * Field : Interrupt Mask Set - nand_buf
6596  *
6597  * Field Access Macros:
6598  *
6599  */
6600 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field. */
6601 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_LSB 11
6602 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field. */
6603 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_MSB 11
6604 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field. */
6605 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_WIDTH 1
6606 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field value. */
6607 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET_MSK 0x00000800
6608 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field value. */
6609 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_CLR_MSK 0xfffff7ff
6610 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field. */
6611 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_RESET 0x0
6612 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF field value from a register. */
6613 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6614 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF register field value suitable for setting the register. */
6615 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6616 
6617 /*
6618  * Field : Interrupt Mask Set - nand_wr
6619  *
6620  * Field Access Macros:
6621  *
6622  */
6623 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field. */
6624 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_LSB 12
6625 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field. */
6626 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_MSB 12
6627 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field. */
6628 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_WIDTH 1
6629 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field value. */
6630 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET_MSK 0x00001000
6631 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field value. */
6632 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_CLR_MSK 0xffffefff
6633 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field. */
6634 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_RESET 0x0
6635 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR field value from a register. */
6636 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6637 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR register field value suitable for setting the register. */
6638 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6639 
6640 /*
6641  * Field : Interrupt Mask Set - nand_rd
6642  *
6643  * Field Access Macros:
6644  *
6645  */
6646 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field. */
6647 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_LSB 13
6648 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field. */
6649 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_MSB 13
6650 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field. */
6651 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_WIDTH 1
6652 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field value. */
6653 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET_MSK 0x00002000
6654 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field value. */
6655 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_CLR_MSK 0xffffdfff
6656 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field. */
6657 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_RESET 0x0
6658 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD field value from a register. */
6659 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6660 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD register field value suitable for setting the register. */
6661 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6662 
6663 /*
6664  * Field : Interrupt Mask Set - qspi
6665  *
6666  * Field Access Macros:
6667  *
6668  */
6669 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field. */
6670 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_LSB 14
6671 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field. */
6672 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_MSB 14
6673 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field. */
6674 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_WIDTH 1
6675 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field value. */
6676 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET_MSK 0x00004000
6677 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field value. */
6678 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_CLR_MSK 0xffffbfff
6679 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field. */
6680 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_RESET 0x0
6681 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_QSPI field value from a register. */
6682 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6683 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_QSPI register field value suitable for setting the register. */
6684 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET(value) (((value) << 14) & 0x00004000)
6685 
6686 /*
6687  * Field : Interrupt Mask Set - sdmmca
6688  *
6689  * Field Access Macros:
6690  *
6691  */
6692 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field. */
6693 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_LSB 15
6694 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field. */
6695 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_MSB 15
6696 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field. */
6697 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_WIDTH 1
6698 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field value. */
6699 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET_MSK 0x00008000
6700 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field value. */
6701 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_CLR_MSK 0xffff7fff
6702 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field. */
6703 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_RESET 0x0
6704 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA field value from a register. */
6705 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6706 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA register field value suitable for setting the register. */
6707 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6708 
6709 /*
6710  * Field : Interrupt Mask Set - sdmmcb
6711  *
6712  * Field Access Macros:
6713  *
6714  */
6715 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field. */
6716 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_LSB 16
6717 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field. */
6718 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_MSB 16
6719 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field. */
6720 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_WIDTH 1
6721 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field value. */
6722 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET_MSK 0x00010000
6723 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field value. */
6724 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_CLR_MSK 0xfffeffff
6725 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field. */
6726 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_RESET 0x0
6727 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB field value from a register. */
6728 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6729 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB register field value suitable for setting the register. */
6730 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6731 
6732 /*
6733  * Field : Interrupt Mask Set - ddr0
6734  *
6735  * Field Access Macros:
6736  *
6737  */
6738 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field. */
6739 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_LSB 17
6740 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field. */
6741 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_MSB 17
6742 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field. */
6743 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_WIDTH 1
6744 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field value. */
6745 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET_MSK 0x00020000
6746 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field value. */
6747 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_CLR_MSK 0xfffdffff
6748 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field. */
6749 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_RESET 0x0
6750 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_DDR0 field value from a register. */
6751 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6752 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_DDR0 register field value suitable for setting the register. */
6753 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET(value) (((value) << 17) & 0x00020000)
6754 
6755 /*
6756  * Field : Interrupt Mask Set - ddr1
6757  *
6758  * Field Access Macros:
6759  *
6760  */
6761 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field. */
6762 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_LSB 18
6763 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field. */
6764 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_MSB 18
6765 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field. */
6766 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_WIDTH 1
6767 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field value. */
6768 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET_MSK 0x00040000
6769 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field value. */
6770 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_CLR_MSK 0xfffbffff
6771 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field. */
6772 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_RESET 0x0
6773 /* Extracts the ALT_SYSMGR_ECC_INTMSK_SET_DDR1 field value from a register. */
6774 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6775 /* Produces a ALT_SYSMGR_ECC_INTMSK_SET_DDR1 register field value suitable for setting the register. */
6776 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET(value) (((value) << 18) & 0x00040000)
6777 
6778 #ifndef __ASSEMBLY__
6779 /*
6780  * WARNING: The C register and register group struct declarations are provided for
6781  * convenience and illustrative purposes. They should, however, be used with
6782  * caution as the C language standard provides no guarantees about the alignment or
6783  * atomicity of device memory accesses. The recommended practice for writing
6784  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6785  * alt_write_word() functions.
6786  *
6787  * The struct declaration for register ALT_SYSMGR_ECC_INTMSK_SET.
6788  */
6789 struct ALT_SYSMGR_ECC_INTMSK_SET_s
6790 {
6791  uint32_t l2 : 1; /* Interrupt Mask Set */
6792  uint32_t ocram : 1; /* Interrupt Mask Set */
6793  uint32_t usb0 : 1; /* Interrupt Mask Set */
6794  uint32_t usb1 : 1; /* Interrupt Mask Set */
6795  uint32_t emac0_rx : 1; /* Interrupt Mask Set */
6796  uint32_t emac0_tx : 1; /* Interrupt Mask Set */
6797  uint32_t emac1_rx : 1; /* Interrupt Mask Set */
6798  uint32_t emac1_tx : 1; /* Interrupt Mask Set */
6799  uint32_t emac2_rx : 1; /* Interrupt Mask Set */
6800  uint32_t emac2_tx : 1; /* Interrupt Mask Set */
6801  uint32_t dma : 1; /* Interrupt Mask Set */
6802  uint32_t nand_buf : 1; /* Interrupt Mask Set */
6803  uint32_t nand_wr : 1; /* Interrupt Mask Set */
6804  uint32_t nand_rd : 1; /* Interrupt Mask Set */
6805  uint32_t qspi : 1; /* Interrupt Mask Set */
6806  uint32_t sdmmca : 1; /* Interrupt Mask Set */
6807  uint32_t sdmmcb : 1; /* Interrupt Mask Set */
6808  uint32_t ddr0 : 1; /* Interrupt Mask Set */
6809  uint32_t ddr1 : 1; /* Interrupt Mask Set */
6810  uint32_t : 13; /* *UNDEFINED* */
6811 };
6812 
6813 /* The typedef declaration for register ALT_SYSMGR_ECC_INTMSK_SET. */
6814 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_SET_s ALT_SYSMGR_ECC_INTMSK_SET_t;
6815 #endif /* __ASSEMBLY__ */
6816 
6817 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_SET register. */
6818 #define ALT_SYSMGR_ECC_INTMSK_SET_RESET 0x00000000
6819 /* The byte offset of the ALT_SYSMGR_ECC_INTMSK_SET register from the beginning of the component. */
6820 #define ALT_SYSMGR_ECC_INTMSK_SET_OFST 0x94
6821 
6822 /*
6823  * Register : ECC interrupt mask Clear register - ecc_intmask_clr
6824  *
6825  * Write 1 to Clear a specific modules interrupt mask.
6826  *
6827  * Reads should not return an error, but the actual read value is "Undefined" .
6828  *
6829  * Register Layout
6830  *
6831  * Bits | Access | Reset | Description
6832  * :--------|:-------|:------|:-------------------
6833  * [0] | RW | 0x0 | Interrupt Mask Set
6834  * [1] | RW | 0x0 | Interrupt Mask Set
6835  * [2] | RW | 0x0 | Interrupt Mask Set
6836  * [3] | RW | 0x0 | Interrupt Mask Set
6837  * [4] | RW | 0x0 | Interrupt Mask Set
6838  * [5] | RW | 0x0 | Interrupt Mask Set
6839  * [6] | RW | 0x0 | Interrupt Mask Set
6840  * [7] | RW | 0x0 | Interrupt Mask Set
6841  * [8] | RW | 0x0 | Interrupt Mask Set
6842  * [9] | RW | 0x0 | Interrupt Mask Set
6843  * [10] | RW | 0x0 | Interrupt Mask Set
6844  * [11] | RW | 0x0 | Interrupt Mask Set
6845  * [12] | RW | 0x0 | Interrupt Mask Set
6846  * [13] | RW | 0x0 | Interrupt Mask Set
6847  * [14] | RW | 0x0 | Interrupt Mask Set
6848  * [15] | RW | 0x0 | Interrupt Mask Set
6849  * [16] | RW | 0x0 | Interrupt Mask Set
6850  * [17] | RW | 0x0 | Interrupt Mask Set
6851  * [18] | RW | 0x0 | Interrupt Mask Set
6852  * [31:19] | ??? | 0x0 | *UNDEFINED*
6853  *
6854  */
6855 /*
6856  * Field : Interrupt Mask Set - l2
6857  *
6858  * Field Access Macros:
6859  *
6860  */
6861 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field. */
6862 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_LSB 0
6863 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field. */
6864 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_MSB 0
6865 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field. */
6866 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_WIDTH 1
6867 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field value. */
6868 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET_MSK 0x00000001
6869 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field value. */
6870 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_CLR_MSK 0xfffffffe
6871 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field. */
6872 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_RESET 0x0
6873 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_L2 field value from a register. */
6874 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_GET(value) (((value) & 0x00000001) >> 0)
6875 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_L2 register field value suitable for setting the register. */
6876 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET(value) (((value) << 0) & 0x00000001)
6877 
6878 /*
6879  * Field : Interrupt Mask Set - ocram
6880  *
6881  * Field Access Macros:
6882  *
6883  */
6884 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field. */
6885 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_LSB 1
6886 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field. */
6887 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_MSB 1
6888 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field. */
6889 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_WIDTH 1
6890 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field value. */
6891 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET_MSK 0x00000002
6892 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field value. */
6893 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_CLR_MSK 0xfffffffd
6894 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field. */
6895 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_RESET 0x0
6896 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM field value from a register. */
6897 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6898 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM register field value suitable for setting the register. */
6899 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6900 
6901 /*
6902  * Field : Interrupt Mask Set - usb0
6903  *
6904  * Field Access Macros:
6905  *
6906  */
6907 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field. */
6908 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_LSB 2
6909 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field. */
6910 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_MSB 2
6911 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field. */
6912 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_WIDTH 1
6913 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field value. */
6914 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET_MSK 0x00000004
6915 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field value. */
6916 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_CLR_MSK 0xfffffffb
6917 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field. */
6918 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_RESET 0x0
6919 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_USB0 field value from a register. */
6920 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_GET(value) (((value) & 0x00000004) >> 2)
6921 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_USB0 register field value suitable for setting the register. */
6922 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET(value) (((value) << 2) & 0x00000004)
6923 
6924 /*
6925  * Field : Interrupt Mask Set - usb1
6926  *
6927  * Field Access Macros:
6928  *
6929  */
6930 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field. */
6931 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_LSB 3
6932 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field. */
6933 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_MSB 3
6934 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field. */
6935 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_WIDTH 1
6936 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field value. */
6937 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET_MSK 0x00000008
6938 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field value. */
6939 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_CLR_MSK 0xfffffff7
6940 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field. */
6941 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_RESET 0x0
6942 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_USB1 field value from a register. */
6943 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_GET(value) (((value) & 0x00000008) >> 3)
6944 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_USB1 register field value suitable for setting the register. */
6945 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET(value) (((value) << 3) & 0x00000008)
6946 
6947 /*
6948  * Field : Interrupt Mask Set - emac0_rx
6949  *
6950  * Field Access Macros:
6951  *
6952  */
6953 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field. */
6954 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_LSB 4
6955 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field. */
6956 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_MSB 4
6957 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field. */
6958 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_WIDTH 1
6959 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field value. */
6960 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET_MSK 0x00000010
6961 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field value. */
6962 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_CLR_MSK 0xffffffef
6963 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field. */
6964 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_RESET 0x0
6965 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX field value from a register. */
6966 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6967 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX register field value suitable for setting the register. */
6968 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6969 
6970 /*
6971  * Field : Interrupt Mask Set - emac0_tx
6972  *
6973  * Field Access Macros:
6974  *
6975  */
6976 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field. */
6977 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_LSB 5
6978 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field. */
6979 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_MSB 5
6980 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field. */
6981 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_WIDTH 1
6982 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field value. */
6983 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET_MSK 0x00000020
6984 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field value. */
6985 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_CLR_MSK 0xffffffdf
6986 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field. */
6987 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_RESET 0x0
6988 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX field value from a register. */
6989 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6990 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX register field value suitable for setting the register. */
6991 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6992 
6993 /*
6994  * Field : Interrupt Mask Set - emac1_rx
6995  *
6996  * Field Access Macros:
6997  *
6998  */
6999 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field. */
7000 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_LSB 6
7001 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field. */
7002 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_MSB 6
7003 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field. */
7004 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_WIDTH 1
7005 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field value. */
7006 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET_MSK 0x00000040
7007 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field value. */
7008 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_CLR_MSK 0xffffffbf
7009 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field. */
7010 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_RESET 0x0
7011 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX field value from a register. */
7012 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7013 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX register field value suitable for setting the register. */
7014 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7015 
7016 /*
7017  * Field : Interrupt Mask Set - emac1_tx
7018  *
7019  * Field Access Macros:
7020  *
7021  */
7022 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field. */
7023 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_LSB 7
7024 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field. */
7025 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_MSB 7
7026 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field. */
7027 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_WIDTH 1
7028 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field value. */
7029 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET_MSK 0x00000080
7030 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field value. */
7031 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_CLR_MSK 0xffffff7f
7032 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field. */
7033 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_RESET 0x0
7034 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX field value from a register. */
7035 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7036 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX register field value suitable for setting the register. */
7037 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7038 
7039 /*
7040  * Field : Interrupt Mask Set - emac2_rx
7041  *
7042  * Field Access Macros:
7043  *
7044  */
7045 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field. */
7046 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_LSB 8
7047 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field. */
7048 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_MSB 8
7049 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field. */
7050 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_WIDTH 1
7051 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field value. */
7052 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET_MSK 0x00000100
7053 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field value. */
7054 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_CLR_MSK 0xfffffeff
7055 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field. */
7056 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_RESET 0x0
7057 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX field value from a register. */
7058 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7059 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX register field value suitable for setting the register. */
7060 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7061 
7062 /*
7063  * Field : Interrupt Mask Set - emac2_tx
7064  *
7065  * Field Access Macros:
7066  *
7067  */
7068 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field. */
7069 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_LSB 9
7070 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field. */
7071 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_MSB 9
7072 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field. */
7073 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_WIDTH 1
7074 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field value. */
7075 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET_MSK 0x00000200
7076 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field value. */
7077 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_CLR_MSK 0xfffffdff
7078 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field. */
7079 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_RESET 0x0
7080 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX field value from a register. */
7081 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7082 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX register field value suitable for setting the register. */
7083 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7084 
7085 /*
7086  * Field : Interrupt Mask Set - dma
7087  *
7088  * Field Access Macros:
7089  *
7090  */
7091 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field. */
7092 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_LSB 10
7093 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field. */
7094 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_MSB 10
7095 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field. */
7096 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_WIDTH 1
7097 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field value. */
7098 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET_MSK 0x00000400
7099 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field value. */
7100 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_CLR_MSK 0xfffffbff
7101 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field. */
7102 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_RESET 0x0
7103 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_DMA field value from a register. */
7104 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7105 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_DMA register field value suitable for setting the register. */
7106 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET(value) (((value) << 10) & 0x00000400)
7107 
7108 /*
7109  * Field : Interrupt Mask Set - nand_buf
7110  *
7111  * Field Access Macros:
7112  *
7113  */
7114 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field. */
7115 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_LSB 11
7116 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field. */
7117 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_MSB 11
7118 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field. */
7119 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_WIDTH 1
7120 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field value. */
7121 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET_MSK 0x00000800
7122 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field value. */
7123 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_CLR_MSK 0xfffff7ff
7124 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field. */
7125 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_RESET 0x0
7126 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF field value from a register. */
7127 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7128 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF register field value suitable for setting the register. */
7129 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7130 
7131 /*
7132  * Field : Interrupt Mask Set - nand_wr
7133  *
7134  * Field Access Macros:
7135  *
7136  */
7137 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field. */
7138 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_LSB 12
7139 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field. */
7140 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_MSB 12
7141 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field. */
7142 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_WIDTH 1
7143 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field value. */
7144 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET_MSK 0x00001000
7145 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field value. */
7146 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_CLR_MSK 0xffffefff
7147 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field. */
7148 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_RESET 0x0
7149 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR field value from a register. */
7150 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7151 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR register field value suitable for setting the register. */
7152 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7153 
7154 /*
7155  * Field : Interrupt Mask Set - nand_rd
7156  *
7157  * Field Access Macros:
7158  *
7159  */
7160 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field. */
7161 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_LSB 13
7162 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field. */
7163 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_MSB 13
7164 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field. */
7165 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_WIDTH 1
7166 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field value. */
7167 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET_MSK 0x00002000
7168 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field value. */
7169 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_CLR_MSK 0xffffdfff
7170 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field. */
7171 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_RESET 0x0
7172 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD field value from a register. */
7173 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7174 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD register field value suitable for setting the register. */
7175 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7176 
7177 /*
7178  * Field : Interrupt Mask Set - qspi
7179  *
7180  * Field Access Macros:
7181  *
7182  */
7183 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field. */
7184 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_LSB 14
7185 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field. */
7186 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_MSB 14
7187 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field. */
7188 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_WIDTH 1
7189 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field value. */
7190 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET_MSK 0x00004000
7191 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field value. */
7192 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_CLR_MSK 0xffffbfff
7193 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field. */
7194 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_RESET 0x0
7195 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_QSPI field value from a register. */
7196 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7197 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_QSPI register field value suitable for setting the register. */
7198 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7199 
7200 /*
7201  * Field : Interrupt Mask Set - sdmmca
7202  *
7203  * Field Access Macros:
7204  *
7205  */
7206 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field. */
7207 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_LSB 15
7208 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field. */
7209 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_MSB 15
7210 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field. */
7211 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_WIDTH 1
7212 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field value. */
7213 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET_MSK 0x00008000
7214 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field value. */
7215 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_CLR_MSK 0xffff7fff
7216 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field. */
7217 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_RESET 0x0
7218 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA field value from a register. */
7219 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7220 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA register field value suitable for setting the register. */
7221 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7222 
7223 /*
7224  * Field : Interrupt Mask Set - sdmmcb
7225  *
7226  * Field Access Macros:
7227  *
7228  */
7229 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field. */
7230 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_LSB 16
7231 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field. */
7232 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_MSB 16
7233 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field. */
7234 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_WIDTH 1
7235 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field value. */
7236 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET_MSK 0x00010000
7237 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field value. */
7238 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_CLR_MSK 0xfffeffff
7239 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field. */
7240 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_RESET 0x0
7241 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB field value from a register. */
7242 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7243 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB register field value suitable for setting the register. */
7244 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7245 
7246 /*
7247  * Field : Interrupt Mask Set - ddr0
7248  *
7249  * Field Access Macros:
7250  *
7251  */
7252 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field. */
7253 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_LSB 17
7254 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field. */
7255 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_MSB 17
7256 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field. */
7257 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_WIDTH 1
7258 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field value. */
7259 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET_MSK 0x00020000
7260 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field value. */
7261 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_CLR_MSK 0xfffdffff
7262 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field. */
7263 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_RESET 0x0
7264 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 field value from a register. */
7265 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7266 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_DDR0 register field value suitable for setting the register. */
7267 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7268 
7269 /*
7270  * Field : Interrupt Mask Set - ddr1
7271  *
7272  * Field Access Macros:
7273  *
7274  */
7275 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field. */
7276 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_LSB 18
7277 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field. */
7278 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_MSB 18
7279 /* The width in bits of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field. */
7280 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_WIDTH 1
7281 /* The mask used to set the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field value. */
7282 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET_MSK 0x00040000
7283 /* The mask used to clear the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field value. */
7284 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_CLR_MSK 0xfffbffff
7285 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field. */
7286 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_RESET 0x0
7287 /* Extracts the ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 field value from a register. */
7288 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7289 /* Produces a ALT_SYSMGR_ECC_INTMSK_CLR_DDR1 register field value suitable for setting the register. */
7290 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7291 
7292 #ifndef __ASSEMBLY__
7293 /*
7294  * WARNING: The C register and register group struct declarations are provided for
7295  * convenience and illustrative purposes. They should, however, be used with
7296  * caution as the C language standard provides no guarantees about the alignment or
7297  * atomicity of device memory accesses. The recommended practice for writing
7298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7299  * alt_write_word() functions.
7300  *
7301  * The struct declaration for register ALT_SYSMGR_ECC_INTMSK_CLR.
7302  */
7303 struct ALT_SYSMGR_ECC_INTMSK_CLR_s
7304 {
7305  uint32_t l2 : 1; /* Interrupt Mask Set */
7306  uint32_t ocram : 1; /* Interrupt Mask Set */
7307  uint32_t usb0 : 1; /* Interrupt Mask Set */
7308  uint32_t usb1 : 1; /* Interrupt Mask Set */
7309  uint32_t emac0_rx : 1; /* Interrupt Mask Set */
7310  uint32_t emac0_tx : 1; /* Interrupt Mask Set */
7311  uint32_t emac1_rx : 1; /* Interrupt Mask Set */
7312  uint32_t emac1_tx : 1; /* Interrupt Mask Set */
7313  uint32_t emac2_rx : 1; /* Interrupt Mask Set */
7314  uint32_t emac2_tx : 1; /* Interrupt Mask Set */
7315  uint32_t dma : 1; /* Interrupt Mask Set */
7316  uint32_t nand_buf : 1; /* Interrupt Mask Set */
7317  uint32_t nand_wr : 1; /* Interrupt Mask Set */
7318  uint32_t nand_rd : 1; /* Interrupt Mask Set */
7319  uint32_t qspi : 1; /* Interrupt Mask Set */
7320  uint32_t sdmmca : 1; /* Interrupt Mask Set */
7321  uint32_t sdmmcb : 1; /* Interrupt Mask Set */
7322  uint32_t ddr0 : 1; /* Interrupt Mask Set */
7323  uint32_t ddr1 : 1; /* Interrupt Mask Set */
7324  uint32_t : 13; /* *UNDEFINED* */
7325 };
7326 
7327 /* The typedef declaration for register ALT_SYSMGR_ECC_INTMSK_CLR. */
7328 typedef volatile struct ALT_SYSMGR_ECC_INTMSK_CLR_s ALT_SYSMGR_ECC_INTMSK_CLR_t;
7329 #endif /* __ASSEMBLY__ */
7330 
7331 /* The reset value of the ALT_SYSMGR_ECC_INTMSK_CLR register. */
7332 #define ALT_SYSMGR_ECC_INTMSK_CLR_RESET 0x00000000
7333 /* The byte offset of the ALT_SYSMGR_ECC_INTMSK_CLR register from the beginning of the component. */
7334 #define ALT_SYSMGR_ECC_INTMSK_CLR_OFST 0x98
7335 
7336 /*
7337  * Register : ecc_intstatus_serr
7338  *
7339  * ECC single bit error status of individual modules.
7340  *
7341  * A write to this register should return an error.
7342  *
7343  * Register Layout
7344  *
7345  * Bits | Access | Reset | Description
7346  * :--------|:-------|:------|:-------------------
7347  * [0] | RW | 0x0 | Interrupt Mask Set
7348  * [1] | RW | 0x0 | Interrupt Mask Set
7349  * [2] | RW | 0x0 | Interrupt Mask Set
7350  * [3] | RW | 0x0 | Interrupt Mask Set
7351  * [4] | RW | 0x0 | Interrupt Mask Set
7352  * [5] | RW | 0x0 | Interrupt Mask Set
7353  * [6] | RW | 0x0 | Interrupt Mask Set
7354  * [7] | RW | 0x0 | Interrupt Mask Set
7355  * [8] | RW | 0x0 | Interrupt Mask Set
7356  * [9] | RW | 0x0 | Interrupt Mask Set
7357  * [10] | RW | 0x0 | Interrupt Mask Set
7358  * [11] | RW | 0x0 | Interrupt Mask Set
7359  * [12] | RW | 0x0 | Interrupt Mask Set
7360  * [13] | RW | 0x0 | Interrupt Mask Set
7361  * [14] | RW | 0x0 | Interrupt Mask Set
7362  * [15] | RW | 0x0 | Interrupt Mask Set
7363  * [16] | RW | 0x0 | Interrupt Mask Set
7364  * [17] | RW | 0x0 | Interrupt Mask Set
7365  * [18] | RW | 0x0 | Interrupt Mask Set
7366  * [31:19] | ??? | 0x0 | *UNDEFINED*
7367  *
7368  */
7369 /*
7370  * Field : Interrupt Mask Set - l2
7371  *
7372  * Field Access Macros:
7373  *
7374  */
7375 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field. */
7376 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_LSB 0
7377 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field. */
7378 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_MSB 0
7379 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field. */
7380 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_WIDTH 1
7381 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field value. */
7382 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET_MSK 0x00000001
7383 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field value. */
7384 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_CLR_MSK 0xfffffffe
7385 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field. */
7386 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_RESET 0x0
7387 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_L2 field value from a register. */
7388 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7389 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_L2 register field value suitable for setting the register. */
7390 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET(value) (((value) << 0) & 0x00000001)
7391 
7392 /*
7393  * Field : Interrupt Mask Set - ocram
7394  *
7395  * Field Access Macros:
7396  *
7397  */
7398 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field. */
7399 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_LSB 1
7400 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field. */
7401 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_MSB 1
7402 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field. */
7403 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_WIDTH 1
7404 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field value. */
7405 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002
7406 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field value. */
7407 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_CLR_MSK 0xfffffffd
7408 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field. */
7409 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_RESET 0x0
7410 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM field value from a register. */
7411 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7412 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM register field value suitable for setting the register. */
7413 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7414 
7415 /*
7416  * Field : Interrupt Mask Set - usb0
7417  *
7418  * Field Access Macros:
7419  *
7420  */
7421 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field. */
7422 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_LSB 2
7423 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field. */
7424 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_MSB 2
7425 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field. */
7426 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_WIDTH 1
7427 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field value. */
7428 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET_MSK 0x00000004
7429 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field value. */
7430 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_CLR_MSK 0xfffffffb
7431 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field. */
7432 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_RESET 0x0
7433 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 field value from a register. */
7434 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7435 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_USB0 register field value suitable for setting the register. */
7436 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7437 
7438 /*
7439  * Field : Interrupt Mask Set - usb1
7440  *
7441  * Field Access Macros:
7442  *
7443  */
7444 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field. */
7445 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_LSB 3
7446 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field. */
7447 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_MSB 3
7448 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field. */
7449 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_WIDTH 1
7450 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field value. */
7451 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET_MSK 0x00000008
7452 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field value. */
7453 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_CLR_MSK 0xfffffff7
7454 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field. */
7455 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_RESET 0x0
7456 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 field value from a register. */
7457 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7458 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_USB1 register field value suitable for setting the register. */
7459 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7460 
7461 /*
7462  * Field : Interrupt Mask Set - emac0_rx
7463  *
7464  * Field Access Macros:
7465  *
7466  */
7467 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field. */
7468 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_LSB 4
7469 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field. */
7470 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_MSB 4
7471 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field. */
7472 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_WIDTH 1
7473 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field value. */
7474 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET_MSK 0x00000010
7475 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field value. */
7476 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_CLR_MSK 0xffffffef
7477 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field. */
7478 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_RESET 0x0
7479 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX field value from a register. */
7480 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7481 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX register field value suitable for setting the register. */
7482 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7483 
7484 /*
7485  * Field : Interrupt Mask Set - emac0_tx
7486  *
7487  * Field Access Macros:
7488  *
7489  */
7490 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field. */
7491 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_LSB 5
7492 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field. */
7493 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_MSB 5
7494 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field. */
7495 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_WIDTH 1
7496 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field value. */
7497 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET_MSK 0x00000020
7498 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field value. */
7499 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_CLR_MSK 0xffffffdf
7500 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field. */
7501 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_RESET 0x0
7502 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX field value from a register. */
7503 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7504 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX register field value suitable for setting the register. */
7505 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7506 
7507 /*
7508  * Field : Interrupt Mask Set - emac1_rx
7509  *
7510  * Field Access Macros:
7511  *
7512  */
7513 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field. */
7514 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_LSB 6
7515 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field. */
7516 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_MSB 6
7517 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field. */
7518 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_WIDTH 1
7519 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field value. */
7520 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET_MSK 0x00000040
7521 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field value. */
7522 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_CLR_MSK 0xffffffbf
7523 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field. */
7524 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_RESET 0x0
7525 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX field value from a register. */
7526 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7527 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX register field value suitable for setting the register. */
7528 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7529 
7530 /*
7531  * Field : Interrupt Mask Set - emac1_tx
7532  *
7533  * Field Access Macros:
7534  *
7535  */
7536 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field. */
7537 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_LSB 7
7538 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field. */
7539 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_MSB 7
7540 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field. */
7541 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_WIDTH 1
7542 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field value. */
7543 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET_MSK 0x00000080
7544 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field value. */
7545 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_CLR_MSK 0xffffff7f
7546 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field. */
7547 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_RESET 0x0
7548 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX field value from a register. */
7549 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7550 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX register field value suitable for setting the register. */
7551 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7552 
7553 /*
7554  * Field : Interrupt Mask Set - emac2_rx
7555  *
7556  * Field Access Macros:
7557  *
7558  */
7559 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field. */
7560 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_LSB 8
7561 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field. */
7562 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_MSB 8
7563 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field. */
7564 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_WIDTH 1
7565 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field value. */
7566 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET_MSK 0x00000100
7567 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field value. */
7568 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_CLR_MSK 0xfffffeff
7569 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field. */
7570 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_RESET 0x0
7571 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX field value from a register. */
7572 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7573 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX register field value suitable for setting the register. */
7574 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7575 
7576 /*
7577  * Field : Interrupt Mask Set - emac2_tx
7578  *
7579  * Field Access Macros:
7580  *
7581  */
7582 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field. */
7583 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_LSB 9
7584 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field. */
7585 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_MSB 9
7586 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field. */
7587 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_WIDTH 1
7588 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field value. */
7589 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET_MSK 0x00000200
7590 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field value. */
7591 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_CLR_MSK 0xfffffdff
7592 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field. */
7593 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_RESET 0x0
7594 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX field value from a register. */
7595 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7596 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX register field value suitable for setting the register. */
7597 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7598 
7599 /*
7600  * Field : Interrupt Mask Set - dma
7601  *
7602  * Field Access Macros:
7603  *
7604  */
7605 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field. */
7606 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_LSB 10
7607 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field. */
7608 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_MSB 10
7609 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field. */
7610 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_WIDTH 1
7611 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field value. */
7612 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET_MSK 0x00000400
7613 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field value. */
7614 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_CLR_MSK 0xfffffbff
7615 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field. */
7616 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_RESET 0x0
7617 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_DMA field value from a register. */
7618 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7619 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_DMA register field value suitable for setting the register. */
7620 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET(value) (((value) << 10) & 0x00000400)
7621 
7622 /*
7623  * Field : Interrupt Mask Set - nand_buf
7624  *
7625  * Field Access Macros:
7626  *
7627  */
7628 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field. */
7629 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_LSB 11
7630 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field. */
7631 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_MSB 11
7632 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field. */
7633 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_WIDTH 1
7634 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field value. */
7635 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET_MSK 0x00000800
7636 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field value. */
7637 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_CLR_MSK 0xfffff7ff
7638 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field. */
7639 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_RESET 0x0
7640 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF field value from a register. */
7641 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7642 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF register field value suitable for setting the register. */
7643 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7644 
7645 /*
7646  * Field : Interrupt Mask Set - nand_wr
7647  *
7648  * Field Access Macros:
7649  *
7650  */
7651 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field. */
7652 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_LSB 12
7653 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field. */
7654 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_MSB 12
7655 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field. */
7656 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_WIDTH 1
7657 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field value. */
7658 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET_MSK 0x00001000
7659 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field value. */
7660 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_CLR_MSK 0xffffefff
7661 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field. */
7662 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_RESET 0x0
7663 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR field value from a register. */
7664 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7665 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR register field value suitable for setting the register. */
7666 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7667 
7668 /*
7669  * Field : Interrupt Mask Set - nand_rd
7670  *
7671  * Field Access Macros:
7672  *
7673  */
7674 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field. */
7675 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_LSB 13
7676 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field. */
7677 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_MSB 13
7678 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field. */
7679 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_WIDTH 1
7680 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field value. */
7681 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET_MSK 0x00002000
7682 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field value. */
7683 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_CLR_MSK 0xffffdfff
7684 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field. */
7685 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_RESET 0x0
7686 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD field value from a register. */
7687 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7688 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD register field value suitable for setting the register. */
7689 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7690 
7691 /*
7692  * Field : Interrupt Mask Set - qspi
7693  *
7694  * Field Access Macros:
7695  *
7696  */
7697 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field. */
7698 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_LSB 14
7699 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field. */
7700 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_MSB 14
7701 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field. */
7702 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_WIDTH 1
7703 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field value. */
7704 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET_MSK 0x00004000
7705 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field value. */
7706 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_CLR_MSK 0xffffbfff
7707 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field. */
7708 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_RESET 0x0
7709 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI field value from a register. */
7710 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7711 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI register field value suitable for setting the register. */
7712 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7713 
7714 /*
7715  * Field : Interrupt Mask Set - sdmmca
7716  *
7717  * Field Access Macros:
7718  *
7719  */
7720 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field. */
7721 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_LSB 15
7722 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field. */
7723 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_MSB 15
7724 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field. */
7725 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_WIDTH 1
7726 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field value. */
7727 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET_MSK 0x00008000
7728 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field value. */
7729 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_CLR_MSK 0xffff7fff
7730 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field. */
7731 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_RESET 0x0
7732 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA field value from a register. */
7733 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7734 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA register field value suitable for setting the register. */
7735 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7736 
7737 /*
7738  * Field : Interrupt Mask Set - sdmmcb
7739  *
7740  * Field Access Macros:
7741  *
7742  */
7743 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field. */
7744 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_LSB 16
7745 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field. */
7746 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_MSB 16
7747 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field. */
7748 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_WIDTH 1
7749 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field value. */
7750 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET_MSK 0x00010000
7751 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field value. */
7752 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_CLR_MSK 0xfffeffff
7753 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field. */
7754 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_RESET 0x0
7755 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB field value from a register. */
7756 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7757 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB register field value suitable for setting the register. */
7758 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7759 
7760 /*
7761  * Field : Interrupt Mask Set - ddr0
7762  *
7763  * Field Access Macros:
7764  *
7765  */
7766 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field. */
7767 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_LSB 17
7768 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field. */
7769 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_MSB 17
7770 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field. */
7771 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_WIDTH 1
7772 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field value. */
7773 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET_MSK 0x00020000
7774 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field value. */
7775 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_CLR_MSK 0xfffdffff
7776 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field. */
7777 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_RESET 0x0
7778 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 field value from a register. */
7779 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7780 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0 register field value suitable for setting the register. */
7781 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7782 
7783 /*
7784  * Field : Interrupt Mask Set - ddr1
7785  *
7786  * Field Access Macros:
7787  *
7788  */
7789 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field. */
7790 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_LSB 18
7791 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field. */
7792 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_MSB 18
7793 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field. */
7794 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_WIDTH 1
7795 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field value. */
7796 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET_MSK 0x00040000
7797 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field value. */
7798 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_CLR_MSK 0xfffbffff
7799 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field. */
7800 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_RESET 0x0
7801 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 field value from a register. */
7802 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7803 /* Produces a ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1 register field value suitable for setting the register. */
7804 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7805 
7806 #ifndef __ASSEMBLY__
7807 /*
7808  * WARNING: The C register and register group struct declarations are provided for
7809  * convenience and illustrative purposes. They should, however, be used with
7810  * caution as the C language standard provides no guarantees about the alignment or
7811  * atomicity of device memory accesses. The recommended practice for writing
7812  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7813  * alt_write_word() functions.
7814  *
7815  * The struct declaration for register ALT_SYSMGR_ECC_INTSTAT_SERR.
7816  */
7817 struct ALT_SYSMGR_ECC_INTSTAT_SERR_s
7818 {
7819  uint32_t l2 : 1; /* Interrupt Mask Set */
7820  uint32_t ocram : 1; /* Interrupt Mask Set */
7821  uint32_t usb0 : 1; /* Interrupt Mask Set */
7822  uint32_t usb1 : 1; /* Interrupt Mask Set */
7823  uint32_t emac0_rx : 1; /* Interrupt Mask Set */
7824  uint32_t emac0_tx : 1; /* Interrupt Mask Set */
7825  uint32_t emac1_rx : 1; /* Interrupt Mask Set */
7826  uint32_t emac1_tx : 1; /* Interrupt Mask Set */
7827  uint32_t emac2_rx : 1; /* Interrupt Mask Set */
7828  uint32_t emac2_tx : 1; /* Interrupt Mask Set */
7829  uint32_t dma : 1; /* Interrupt Mask Set */
7830  uint32_t nand_buf : 1; /* Interrupt Mask Set */
7831  uint32_t nand_wr : 1; /* Interrupt Mask Set */
7832  uint32_t nand_rd : 1; /* Interrupt Mask Set */
7833  uint32_t qspi : 1; /* Interrupt Mask Set */
7834  uint32_t sdmmca : 1; /* Interrupt Mask Set */
7835  uint32_t sdmmcb : 1; /* Interrupt Mask Set */
7836  uint32_t ddr0 : 1; /* Interrupt Mask Set */
7837  uint32_t ddr1 : 1; /* Interrupt Mask Set */
7838  uint32_t : 13; /* *UNDEFINED* */
7839 };
7840 
7841 /* The typedef declaration for register ALT_SYSMGR_ECC_INTSTAT_SERR. */
7842 typedef volatile struct ALT_SYSMGR_ECC_INTSTAT_SERR_s ALT_SYSMGR_ECC_INTSTAT_SERR_t;
7843 #endif /* __ASSEMBLY__ */
7844 
7845 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_SERR register. */
7846 #define ALT_SYSMGR_ECC_INTSTAT_SERR_RESET 0x00000000
7847 /* The byte offset of the ALT_SYSMGR_ECC_INTSTAT_SERR register from the beginning of the component. */
7848 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9c
7849 
7850 /*
7851  * Register : ecc_intstatus_derr
7852  *
7853  * ECC double bit error status of individual modules.
7854  *
7855  * A write to this register should return an error.
7856  *
7857  * Register Layout
7858  *
7859  * Bits | Access | Reset | Description
7860  * :--------|:-------|:------|:-------------------
7861  * [0] | RW | 0x0 | Interrupt Mask Set
7862  * [1] | RW | 0x0 | Interrupt Mask Set
7863  * [2] | RW | 0x0 | Interrupt Mask Set
7864  * [3] | RW | 0x0 | Interrupt Mask Set
7865  * [4] | RW | 0x0 | Interrupt Mask Set
7866  * [5] | RW | 0x0 | Interrupt Mask Set
7867  * [6] | RW | 0x0 | Interrupt Mask Set
7868  * [7] | RW | 0x0 | Interrupt Mask Set
7869  * [8] | RW | 0x0 | Interrupt Mask Set
7870  * [9] | RW | 0x0 | Interrupt Mask Set
7871  * [10] | RW | 0x0 | Interrupt Mask Set
7872  * [11] | RW | 0x0 | Interrupt Mask Set
7873  * [12] | RW | 0x0 | Interrupt Mask Set
7874  * [13] | RW | 0x0 | Interrupt Mask Set
7875  * [14] | RW | 0x0 | Interrupt Mask Set
7876  * [15] | RW | 0x0 | Interrupt Mask Set
7877  * [16] | RW | 0x0 | Interrupt Mask Set
7878  * [17] | RW | 0x0 | Interrupt Mask Set
7879  * [18] | RW | 0x0 | Interrupt Mask Set
7880  * [31:19] | ??? | 0x0 | *UNDEFINED*
7881  *
7882  */
7883 /*
7884  * Field : Interrupt Mask Set - l2
7885  *
7886  * Field Access Macros:
7887  *
7888  */
7889 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field. */
7890 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_LSB 0
7891 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field. */
7892 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_MSB 0
7893 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field. */
7894 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_WIDTH 1
7895 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field value. */
7896 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET_MSK 0x00000001
7897 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field value. */
7898 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_CLR_MSK 0xfffffffe
7899 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field. */
7900 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_RESET 0x0
7901 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_L2 field value from a register. */
7902 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7903 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_L2 register field value suitable for setting the register. */
7904 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET(value) (((value) << 0) & 0x00000001)
7905 
7906 /*
7907  * Field : Interrupt Mask Set - ocram
7908  *
7909  * Field Access Macros:
7910  *
7911  */
7912 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field. */
7913 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_LSB 1
7914 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field. */
7915 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_MSB 1
7916 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field. */
7917 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_WIDTH 1
7918 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field value. */
7919 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002
7920 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field value. */
7921 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_CLR_MSK 0xfffffffd
7922 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field. */
7923 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_RESET 0x0
7924 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM field value from a register. */
7925 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7926 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM register field value suitable for setting the register. */
7927 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7928 
7929 /*
7930  * Field : Interrupt Mask Set - usb0
7931  *
7932  * Field Access Macros:
7933  *
7934  */
7935 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field. */
7936 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_LSB 2
7937 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field. */
7938 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_MSB 2
7939 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field. */
7940 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_WIDTH 1
7941 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field value. */
7942 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET_MSK 0x00000004
7943 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field value. */
7944 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_CLR_MSK 0xfffffffb
7945 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field. */
7946 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_RESET 0x0
7947 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 field value from a register. */
7948 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7949 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_USB0 register field value suitable for setting the register. */
7950 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7951 
7952 /*
7953  * Field : Interrupt Mask Set - usb1
7954  *
7955  * Field Access Macros:
7956  *
7957  */
7958 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field. */
7959 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_LSB 3
7960 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field. */
7961 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_MSB 3
7962 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field. */
7963 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_WIDTH 1
7964 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field value. */
7965 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET_MSK 0x00000008
7966 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field value. */
7967 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_CLR_MSK 0xfffffff7
7968 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field. */
7969 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_RESET 0x0
7970 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 field value from a register. */
7971 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7972 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_USB1 register field value suitable for setting the register. */
7973 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7974 
7975 /*
7976  * Field : Interrupt Mask Set - emac0_rx
7977  *
7978  * Field Access Macros:
7979  *
7980  */
7981 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field. */
7982 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_LSB 4
7983 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field. */
7984 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_MSB 4
7985 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field. */
7986 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_WIDTH 1
7987 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field value. */
7988 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET_MSK 0x00000010
7989 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field value. */
7990 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_CLR_MSK 0xffffffef
7991 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field. */
7992 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_RESET 0x0
7993 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX field value from a register. */
7994 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7995 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX register field value suitable for setting the register. */
7996 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7997 
7998 /*
7999  * Field : Interrupt Mask Set - emac0_tx
8000  *
8001  * Field Access Macros:
8002  *
8003  */
8004 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field. */
8005 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_LSB 5
8006 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field. */
8007 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_MSB 5
8008 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field. */
8009 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_WIDTH 1
8010 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field value. */
8011 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET_MSK 0x00000020
8012 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field value. */
8013 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_CLR_MSK 0xffffffdf
8014 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field. */
8015 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_RESET 0x0
8016 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX field value from a register. */
8017 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8018 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX register field value suitable for setting the register. */
8019 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8020 
8021 /*
8022  * Field : Interrupt Mask Set - emac1_rx
8023  *
8024  * Field Access Macros:
8025  *
8026  */
8027 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field. */
8028 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_LSB 6
8029 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field. */
8030 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_MSB 6
8031 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field. */
8032 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_WIDTH 1
8033 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field value. */
8034 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET_MSK 0x00000040
8035 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field value. */
8036 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_CLR_MSK 0xffffffbf
8037 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field. */
8038 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_RESET 0x0
8039 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX field value from a register. */
8040 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8041 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX register field value suitable for setting the register. */
8042 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8043 
8044 /*
8045  * Field : Interrupt Mask Set - emac1_tx
8046  *
8047  * Field Access Macros:
8048  *
8049  */
8050 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field. */
8051 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_LSB 7
8052 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field. */
8053 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_MSB 7
8054 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field. */
8055 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_WIDTH 1
8056 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field value. */
8057 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET_MSK 0x00000080
8058 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field value. */
8059 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_CLR_MSK 0xffffff7f
8060 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field. */
8061 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_RESET 0x0
8062 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX field value from a register. */
8063 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8064 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX register field value suitable for setting the register. */
8065 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8066 
8067 /*
8068  * Field : Interrupt Mask Set - emac2_rx
8069  *
8070  * Field Access Macros:
8071  *
8072  */
8073 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field. */
8074 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_LSB 8
8075 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field. */
8076 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_MSB 8
8077 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field. */
8078 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_WIDTH 1
8079 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field value. */
8080 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET_MSK 0x00000100
8081 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field value. */
8082 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_CLR_MSK 0xfffffeff
8083 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field. */
8084 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_RESET 0x0
8085 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX field value from a register. */
8086 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8087 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX register field value suitable for setting the register. */
8088 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8089 
8090 /*
8091  * Field : Interrupt Mask Set - emac2_tx
8092  *
8093  * Field Access Macros:
8094  *
8095  */
8096 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field. */
8097 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_LSB 9
8098 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field. */
8099 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_MSB 9
8100 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field. */
8101 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_WIDTH 1
8102 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field value. */
8103 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET_MSK 0x00000200
8104 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field value. */
8105 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_CLR_MSK 0xfffffdff
8106 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field. */
8107 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_RESET 0x0
8108 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX field value from a register. */
8109 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8110 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX register field value suitable for setting the register. */
8111 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8112 
8113 /*
8114  * Field : Interrupt Mask Set - dma
8115  *
8116  * Field Access Macros:
8117  *
8118  */
8119 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field. */
8120 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_LSB 10
8121 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field. */
8122 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_MSB 10
8123 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field. */
8124 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_WIDTH 1
8125 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field value. */
8126 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET_MSK 0x00000400
8127 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field value. */
8128 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_CLR_MSK 0xfffffbff
8129 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field. */
8130 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_RESET 0x0
8131 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_DMA field value from a register. */
8132 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8133 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_DMA register field value suitable for setting the register. */
8134 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8135 
8136 /*
8137  * Field : Interrupt Mask Set - nand_buf
8138  *
8139  * Field Access Macros:
8140  *
8141  */
8142 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field. */
8143 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_LSB 11
8144 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field. */
8145 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_MSB 11
8146 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field. */
8147 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_WIDTH 1
8148 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field value. */
8149 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET_MSK 0x00000800
8150 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field value. */
8151 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_CLR_MSK 0xfffff7ff
8152 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field. */
8153 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_RESET 0x0
8154 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF field value from a register. */
8155 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8156 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF register field value suitable for setting the register. */
8157 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8158 
8159 /*
8160  * Field : Interrupt Mask Set - nand_wr
8161  *
8162  * Field Access Macros:
8163  *
8164  */
8165 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field. */
8166 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_LSB 12
8167 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field. */
8168 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_MSB 12
8169 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field. */
8170 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_WIDTH 1
8171 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field value. */
8172 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET_MSK 0x00001000
8173 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field value. */
8174 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_CLR_MSK 0xffffefff
8175 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field. */
8176 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_RESET 0x0
8177 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR field value from a register. */
8178 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8179 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR register field value suitable for setting the register. */
8180 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8181 
8182 /*
8183  * Field : Interrupt Mask Set - nand_rd
8184  *
8185  * Field Access Macros:
8186  *
8187  */
8188 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field. */
8189 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_LSB 13
8190 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field. */
8191 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_MSB 13
8192 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field. */
8193 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_WIDTH 1
8194 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field value. */
8195 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET_MSK 0x00002000
8196 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field value. */
8197 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_CLR_MSK 0xffffdfff
8198 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field. */
8199 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_RESET 0x0
8200 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD field value from a register. */
8201 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8202 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD register field value suitable for setting the register. */
8203 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8204 
8205 /*
8206  * Field : Interrupt Mask Set - qspi
8207  *
8208  * Field Access Macros:
8209  *
8210  */
8211 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field. */
8212 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_LSB 14
8213 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field. */
8214 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_MSB 14
8215 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field. */
8216 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_WIDTH 1
8217 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field value. */
8218 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET_MSK 0x00004000
8219 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field value. */
8220 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_CLR_MSK 0xffffbfff
8221 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field. */
8222 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_RESET 0x0
8223 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI field value from a register. */
8224 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
8225 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI register field value suitable for setting the register. */
8226 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
8227 
8228 /*
8229  * Field : Interrupt Mask Set - sdmmca
8230  *
8231  * Field Access Macros:
8232  *
8233  */
8234 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field. */
8235 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_LSB 15
8236 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field. */
8237 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_MSB 15
8238 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field. */
8239 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_WIDTH 1
8240 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field value. */
8241 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET_MSK 0x00008000
8242 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field value. */
8243 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_CLR_MSK 0xffff7fff
8244 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field. */
8245 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_RESET 0x0
8246 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA field value from a register. */
8247 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
8248 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA register field value suitable for setting the register. */
8249 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
8250 
8251 /*
8252  * Field : Interrupt Mask Set - sdmmcb
8253  *
8254  * Field Access Macros:
8255  *
8256  */
8257 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field. */
8258 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_LSB 16
8259 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field. */
8260 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_MSB 16
8261 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field. */
8262 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_WIDTH 1
8263 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field value. */
8264 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET_MSK 0x00010000
8265 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field value. */
8266 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_CLR_MSK 0xfffeffff
8267 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field. */
8268 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_RESET 0x0
8269 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB field value from a register. */
8270 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
8271 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB register field value suitable for setting the register. */
8272 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
8273 
8274 /*
8275  * Field : Interrupt Mask Set - ddr0
8276  *
8277  * Field Access Macros:
8278  *
8279  */
8280 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field. */
8281 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_LSB 17
8282 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field. */
8283 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_MSB 17
8284 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field. */
8285 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_WIDTH 1
8286 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field value. */
8287 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET_MSK 0x00020000
8288 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field value. */
8289 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_CLR_MSK 0xfffdffff
8290 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field. */
8291 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_RESET 0x0
8292 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 field value from a register. */
8293 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
8294 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0 register field value suitable for setting the register. */
8295 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
8296 
8297 /*
8298  * Field : Interrupt Mask Set - ddr1
8299  *
8300  * Field Access Macros:
8301  *
8302  */
8303 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field. */
8304 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_LSB 18
8305 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field. */
8306 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_MSB 18
8307 /* The width in bits of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field. */
8308 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_WIDTH 1
8309 /* The mask used to set the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field value. */
8310 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET_MSK 0x00040000
8311 /* The mask used to clear the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field value. */
8312 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_CLR_MSK 0xfffbffff
8313 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field. */
8314 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_RESET 0x0
8315 /* Extracts the ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 field value from a register. */
8316 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
8317 /* Produces a ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1 register field value suitable for setting the register. */
8318 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
8319 
8320 #ifndef __ASSEMBLY__
8321 /*
8322  * WARNING: The C register and register group struct declarations are provided for
8323  * convenience and illustrative purposes. They should, however, be used with
8324  * caution as the C language standard provides no guarantees about the alignment or
8325  * atomicity of device memory accesses. The recommended practice for writing
8326  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8327  * alt_write_word() functions.
8328  *
8329  * The struct declaration for register ALT_SYSMGR_ECC_INTSTAT_DERR.
8330  */
8331 struct ALT_SYSMGR_ECC_INTSTAT_DERR_s
8332 {
8333  uint32_t l2 : 1; /* Interrupt Mask Set */
8334  uint32_t ocram : 1; /* Interrupt Mask Set */
8335  uint32_t usb0 : 1; /* Interrupt Mask Set */
8336  uint32_t usb1 : 1; /* Interrupt Mask Set */
8337  uint32_t emac0_rx : 1; /* Interrupt Mask Set */
8338  uint32_t emac0_tx : 1; /* Interrupt Mask Set */
8339  uint32_t emac1_rx : 1; /* Interrupt Mask Set */
8340  uint32_t emac1_tx : 1; /* Interrupt Mask Set */
8341  uint32_t emac2_rx : 1; /* Interrupt Mask Set */
8342  uint32_t emac2_tx : 1; /* Interrupt Mask Set */
8343  uint32_t dma : 1; /* Interrupt Mask Set */
8344  uint32_t nand_buf : 1; /* Interrupt Mask Set */
8345  uint32_t nand_wr : 1; /* Interrupt Mask Set */
8346  uint32_t nand_rd : 1; /* Interrupt Mask Set */
8347  uint32_t qspi : 1; /* Interrupt Mask Set */
8348  uint32_t sdmmca : 1; /* Interrupt Mask Set */
8349  uint32_t sdmmcb : 1; /* Interrupt Mask Set */
8350  uint32_t ddr0 : 1; /* Interrupt Mask Set */
8351  uint32_t ddr1 : 1; /* Interrupt Mask Set */
8352  uint32_t : 13; /* *UNDEFINED* */
8353 };
8354 
8355 /* The typedef declaration for register ALT_SYSMGR_ECC_INTSTAT_DERR. */
8356 typedef volatile struct ALT_SYSMGR_ECC_INTSTAT_DERR_s ALT_SYSMGR_ECC_INTSTAT_DERR_t;
8357 #endif /* __ASSEMBLY__ */
8358 
8359 /* The reset value of the ALT_SYSMGR_ECC_INTSTAT_DERR register. */
8360 #define ALT_SYSMGR_ECC_INTSTAT_DERR_RESET 0x00000000
8361 /* The byte offset of the ALT_SYSMGR_ECC_INTSTAT_DERR register from the beginning of the component. */
8362 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OFST 0xa0
8363 
8364 /*
8365  * Register : mpu_status_l2_ecc
8366  *
8367  * This is a read only register which reads the current mpu L2 ecc interrupt
8368  * status.
8369  *
8370  * A write to this register should return an error.
8371  *
8372  * Register Layout
8373  *
8374  * Bits | Access | Reset | Description
8375  * :--------|:-------|:--------|:----------------------------------------
8376  * [11:0] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO
8377  * [14:12] | ??? | Unknown | *UNDEFINED*
8378  * [15] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING
8379  * [27:16] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO
8380  * [30:28] | ??? | Unknown | *UNDEFINED*
8381  * [31] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING
8382  *
8383  */
8384 /*
8385  * Field : serr_info
8386  *
8387  * 12 bit Serr Info field.
8388  *
8389  * In Baum this will be the index and way information where the ECC error occured.
8390  *
8391  * Field Access Macros:
8392  *
8393  */
8394 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field. */
8395 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_LSB 0
8396 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field. */
8397 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_MSB 11
8398 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field. */
8399 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_WIDTH 12
8400 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value. */
8401 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET_MSK 0x00000fff
8402 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value. */
8403 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_CLR_MSK 0xfffff000
8404 /* The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field is UNKNOWN. */
8405 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_RESET 0x0
8406 /* Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO field value from a register. */
8407 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_GET(value) (((value) & 0x00000fff) >> 0)
8408 /* Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value suitable for setting the register. */
8409 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET(value) (((value) << 0) & 0x00000fff)
8410 
8411 /*
8412  * Field : serr_pending
8413  *
8414  * Unmaksed value of a pending single bit ECC error status.
8415  *
8416  * Field Access Macros:
8417  *
8418  */
8419 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field. */
8420 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_LSB 15
8421 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field. */
8422 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_MSB 15
8423 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field. */
8424 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_WIDTH 1
8425 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value. */
8426 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET_MSK 0x00008000
8427 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value. */
8428 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_CLR_MSK 0xffff7fff
8429 /* The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field is UNKNOWN. */
8430 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_RESET 0x0
8431 /* Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING field value from a register. */
8432 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_GET(value) (((value) & 0x00008000) >> 15)
8433 /* Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value suitable for setting the register. */
8434 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET(value) (((value) << 15) & 0x00008000)
8435 
8436 /*
8437  * Field : merr_info
8438  *
8439  * 12 bit Serr Info field.
8440  *
8441  * In Baum this will be the index and way information where the ECC error occured.
8442  *
8443  * Field Access Macros:
8444  *
8445  */
8446 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field. */
8447 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_LSB 16
8448 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field. */
8449 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_MSB 27
8450 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field. */
8451 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_WIDTH 12
8452 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value. */
8453 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET_MSK 0x0fff0000
8454 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value. */
8455 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_CLR_MSK 0xf000ffff
8456 /* The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field is UNKNOWN. */
8457 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_RESET 0x0
8458 /* Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO field value from a register. */
8459 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_GET(value) (((value) & 0x0fff0000) >> 16)
8460 /* Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value suitable for setting the register. */
8461 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET(value) (((value) << 16) & 0x0fff0000)
8462 
8463 /*
8464  * Field : merr_pending
8465  *
8466  * Unmaksed value of a pending multiple bits ECC error status.
8467  *
8468  * Field Access Macros:
8469  *
8470  */
8471 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field. */
8472 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_LSB 31
8473 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field. */
8474 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_MSB 31
8475 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field. */
8476 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_WIDTH 1
8477 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value. */
8478 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET_MSK 0x80000000
8479 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value. */
8480 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_CLR_MSK 0x7fffffff
8481 /* The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field is UNKNOWN. */
8482 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_RESET 0x0
8483 /* Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING field value from a register. */
8484 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_GET(value) (((value) & 0x80000000) >> 31)
8485 /* Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value suitable for setting the register. */
8486 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET(value) (((value) << 31) & 0x80000000)
8487 
8488 #ifndef __ASSEMBLY__
8489 /*
8490  * WARNING: The C register and register group struct declarations are provided for
8491  * convenience and illustrative purposes. They should, however, be used with
8492  * caution as the C language standard provides no guarantees about the alignment or
8493  * atomicity of device memory accesses. The recommended practice for writing
8494  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8495  * alt_write_word() functions.
8496  *
8497  * The struct declaration for register ALT_SYSMGR_MPU_STAT_L2_ECC.
8498  */
8499 struct ALT_SYSMGR_MPU_STAT_L2_ECC_s
8500 {
8501  uint32_t serr_info : 12; /* ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO */
8502  uint32_t : 3; /* *UNDEFINED* */
8503  uint32_t serr_pending : 1; /* ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING */
8504  uint32_t merr_info : 12; /* ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO */
8505  uint32_t : 3; /* *UNDEFINED* */
8506  uint32_t merr_pending : 1; /* ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING */
8507 };
8508 
8509 /* The typedef declaration for register ALT_SYSMGR_MPU_STAT_L2_ECC. */
8510 typedef volatile struct ALT_SYSMGR_MPU_STAT_L2_ECC_s ALT_SYSMGR_MPU_STAT_L2_ECC_t;
8511 #endif /* __ASSEMBLY__ */
8512 
8513 /* The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC register. */
8514 #define ALT_SYSMGR_MPU_STAT_L2_ECC_RESET 0x00000000
8515 /* The byte offset of the ALT_SYSMGR_MPU_STAT_L2_ECC register from the beginning of the component. */
8516 #define ALT_SYSMGR_MPU_STAT_L2_ECC_OFST 0xa4
8517 
8518 /*
8519  * Register : mpu_clear_l2_ecc
8520  *
8521  * Write 1 to Clear register to clear the specific bit field of mpu l2 ecc
8522  * interrupt pending status
8523  *
8524  * Reads should not return an error, but the read value is undefined.
8525  *
8526  * Register Layout
8527  *
8528  * Bits | Access | Reset | Description
8529  * :--------|:-------|:------|:-------------------------------
8530  * [14:0] | ??? | 0x0 | *UNDEFINED*
8531  * [15] | RW | 0x0 | ALT_SYSMGR_MPU_CLR_L2_ECC_SERR
8532  * [30:16] | ??? | 0x0 | *UNDEFINED*
8533  * [31] | RW | 0x0 | ALT_SYSMGR_MPU_CLR_L2_ECC_MERR
8534  *
8535  */
8536 /*
8537  * Field : serr
8538  *
8539  * Write 1 to this field to clear the MPU L2 ECC single bit Error interrupt Status
8540  * and the actual Interrupt.
8541  *
8542  * Field Access Macros:
8543  *
8544  */
8545 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field. */
8546 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_LSB 15
8547 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field. */
8548 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_MSB 15
8549 /* The width in bits of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field. */
8550 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_WIDTH 1
8551 /* The mask used to set the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value. */
8552 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET_MSK 0x00008000
8553 /* The mask used to clear the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value. */
8554 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_CLR_MSK 0xffff7fff
8555 /* The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field. */
8556 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_RESET 0x0
8557 /* Extracts the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR field value from a register. */
8558 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_GET(value) (((value) & 0x00008000) >> 15)
8559 /* Produces a ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value suitable for setting the register. */
8560 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET(value) (((value) << 15) & 0x00008000)
8561 
8562 /*
8563  * Field : merr
8564  *
8565  * Write 1 to this field to clear the MPU L2 ECC multiple bit Error interrupt
8566  * Status and the actual Interrupt.
8567  *
8568  * Field Access Macros:
8569  *
8570  */
8571 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field. */
8572 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_LSB 31
8573 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field. */
8574 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_MSB 31
8575 /* The width in bits of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field. */
8576 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_WIDTH 1
8577 /* The mask used to set the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value. */
8578 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET_MSK 0x80000000
8579 /* The mask used to clear the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value. */
8580 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_CLR_MSK 0x7fffffff
8581 /* The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field. */
8582 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_RESET 0x0
8583 /* Extracts the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR field value from a register. */
8584 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_GET(value) (((value) & 0x80000000) >> 31)
8585 /* Produces a ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value suitable for setting the register. */
8586 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET(value) (((value) << 31) & 0x80000000)
8587 
8588 #ifndef __ASSEMBLY__
8589 /*
8590  * WARNING: The C register and register group struct declarations are provided for
8591  * convenience and illustrative purposes. They should, however, be used with
8592  * caution as the C language standard provides no guarantees about the alignment or
8593  * atomicity of device memory accesses. The recommended practice for writing
8594  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8595  * alt_write_word() functions.
8596  *
8597  * The struct declaration for register ALT_SYSMGR_MPU_CLR_L2_ECC.
8598  */
8599 struct ALT_SYSMGR_MPU_CLR_L2_ECC_s
8600 {
8601  uint32_t : 15; /* *UNDEFINED* */
8602  uint32_t serr : 1; /* ALT_SYSMGR_MPU_CLR_L2_ECC_SERR */
8603  uint32_t : 15; /* *UNDEFINED* */
8604  uint32_t merr : 1; /* ALT_SYSMGR_MPU_CLR_L2_ECC_MERR */
8605 };
8606 
8607 /* The typedef declaration for register ALT_SYSMGR_MPU_CLR_L2_ECC. */
8608 typedef volatile struct ALT_SYSMGR_MPU_CLR_L2_ECC_s ALT_SYSMGR_MPU_CLR_L2_ECC_t;
8609 #endif /* __ASSEMBLY__ */
8610 
8611 /* The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC register. */
8612 #define ALT_SYSMGR_MPU_CLR_L2_ECC_RESET 0x00000000
8613 /* The byte offset of the ALT_SYSMGR_MPU_CLR_L2_ECC register from the beginning of the component. */
8614 #define ALT_SYSMGR_MPU_CLR_L2_ECC_OFST 0xa8
8615 
8616 /*
8617  * Register : mpu_status_l1_parity
8618  *
8619  * Parity status from L1 and scu. This is a read only register.
8620  *
8621  * A write to this register should return an error.
8622  *
8623  * [17] CPU1 SCU parity error
8624  *
8625  * [16] CPU0 SCU parity error
8626  *
8627  * [15] CPU1 BTAC parity error
8628  *
8629  * [14] CPU1 GHB parity error
8630  *
8631  * [13] CPU1 instruction tag RAM parity error
8632  *
8633  * [12] CPU1 instruction data RAM parity error
8634  *
8635  * [11] CPU1 main TLB parity error
8636  *
8637  * [10] CPU1 data outer RAM parity error
8638  *
8639  * [9] CPU1 data tag RAM parity error
8640  *
8641  * [8] CPU1 data data RAM parity error.
8642  *
8643  * [7] CPU0 BTAC parity error
8644  *
8645  * [6] CPU0 GHB parity error
8646  *
8647  * [5] CPU0 instruction tag RAM parity error
8648  *
8649  * [4] CPU0 instruction data RAM parity error
8650  *
8651  * [3] CPU0 main TLB parity error
8652  *
8653  * [2] CPU0 data outer RAM parity error
8654  *
8655  * [1] CPU0 data tag RAM parity error
8656  *
8657  * [0] CPU0 data data RAM parity error.
8658  *
8659  * Register Layout
8660  *
8661  * Bits | Access | Reset | Description
8662  * :--------|:-------|:--------|:-----------------------------------
8663  * [7:0] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0
8664  * [15:8] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1
8665  * [17:16] | RW | Unknown | ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU
8666  * [31:18] | ??? | Unknown | *UNDEFINED*
8667  *
8668  */
8669 /*
8670  * Field : cpu0
8671  *
8672  * CPU0 L1 parity interrupt status
8673  *
8674  * Field Access Macros:
8675  *
8676  */
8677 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field. */
8678 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_LSB 0
8679 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field. */
8680 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_MSB 7
8681 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field. */
8682 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_WIDTH 8
8683 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field value. */
8684 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET_MSK 0x000000ff
8685 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field value. */
8686 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8687 /* The reset value of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field is UNKNOWN. */
8688 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_RESET 0x0
8689 /* Extracts the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 field value from a register. */
8690 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8691 /* Produces a ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 register field value suitable for setting the register. */
8692 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8693 
8694 /*
8695  * Field : cpu1
8696  *
8697  * CPU1 L1 parity interrupt status
8698  *
8699  * Field Access Macros:
8700  *
8701  */
8702 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field. */
8703 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_LSB 8
8704 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field. */
8705 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_MSB 15
8706 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field. */
8707 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_WIDTH 8
8708 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field value. */
8709 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8710 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field value. */
8711 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8712 /* The reset value of the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field is UNKNOWN. */
8713 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_RESET 0x0
8714 /* Extracts the ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 field value from a register. */
8715 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8716 /* Produces a ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 register field value suitable for setting the register. */
8717 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8718 
8719 /*
8720  * Field : scu
8721  *
8722  * SCU parity interrupt status
8723  *
8724  * Field Access Macros:
8725  *
8726  */
8727 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field. */
8728 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_LSB 16
8729 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field. */
8730 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_MSB 17
8731 /* The width in bits of the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field. */
8732 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_WIDTH 2
8733 /* The mask used to set the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field value. */
8734 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET_MSK 0x00030000
8735 /* The mask used to clear the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field value. */
8736 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8737 /* The reset value of the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field is UNKNOWN. */
8738 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_RESET 0x0
8739 /* Extracts the ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU field value from a register. */
8740 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8741 /* Produces a ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU register field value suitable for setting the register. */
8742 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8743 
8744 #ifndef __ASSEMBLY__
8745 /*
8746  * WARNING: The C register and register group struct declarations are provided for
8747  * convenience and illustrative purposes. They should, however, be used with
8748  * caution as the C language standard provides no guarantees about the alignment or
8749  * atomicity of device memory accesses. The recommended practice for writing
8750  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8751  * alt_write_word() functions.
8752  *
8753  * The struct declaration for register ALT_SYSMGR_MPU_STAT_L1_PARITY.
8754  */
8755 struct ALT_SYSMGR_MPU_STAT_L1_PARITY_s
8756 {
8757  uint32_t cpu0 : 8; /* ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0 */
8758  uint32_t cpu1 : 8; /* ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1 */
8759  uint32_t scu : 2; /* ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU */
8760  uint32_t : 14; /* *UNDEFINED* */
8761 };
8762 
8763 /* The typedef declaration for register ALT_SYSMGR_MPU_STAT_L1_PARITY. */
8764 typedef volatile struct ALT_SYSMGR_MPU_STAT_L1_PARITY_s ALT_SYSMGR_MPU_STAT_L1_PARITY_t;
8765 #endif /* __ASSEMBLY__ */
8766 
8767 /* The reset value of the ALT_SYSMGR_MPU_STAT_L1_PARITY register. */
8768 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_RESET 0x00000000
8769 /* The byte offset of the ALT_SYSMGR_MPU_STAT_L1_PARITY register from the beginning of the component. */
8770 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_OFST 0xac
8771 
8772 /*
8773  * Register : mpu_clear_l1_parity
8774  *
8775  * Parity status clear bit.
8776  *
8777  * A write to 1 of a specific bit clears the curresponding parity status bit.
8778  *
8779  * A read of this register should not return an error, but the actual read value is
8780  * undefined.
8781  *
8782  * [17] CPU1 SCU parity error
8783  *
8784  * [16] CPU0 SCU parity error
8785  *
8786  * [15] CPU1 BTAC parity error
8787  *
8788  * [14] CPU1 GHB parity error
8789  *
8790  * [13] CPU1 instruction tag RAM parity error
8791  *
8792  * [12] CPU1 instruction data RAM parity error
8793  *
8794  * [11] CPU1 main TLB parity error
8795  *
8796  * [10] CPU1 data outer RAM parity error
8797  *
8798  * [9] CPU1 data tag RAM parity error
8799  *
8800  * [8] CPU1 data data RAM parity error.
8801  *
8802  * [7] CPU0 BTAC parity error
8803  *
8804  * [6] CPU0 GHB parity error
8805  *
8806  * [5] CPU0 instruction tag RAM parity error
8807  *
8808  * [4] CPU0 instruction data RAM parity error
8809  *
8810  * [3] CPU0 main TLB parity error
8811  *
8812  * [2] CPU0 data outer RAM parity error
8813  *
8814  * [1] CPU0 data tag RAM parity error
8815  *
8816  * [0] CPU0 data data RAM parity error.
8817  *
8818  * Register Layout
8819  *
8820  * Bits | Access | Reset | Description
8821  * :--------|:-------|:------|:----------------------------------
8822  * [7:0] | RW | 0x0 | ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0
8823  * [15:8] | RW | 0x0 | ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1
8824  * [17:16] | RW | 0x0 | ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU
8825  * [31:18] | ??? | 0x0 | *UNDEFINED*
8826  *
8827  */
8828 /*
8829  * Field : cpu0
8830  *
8831  * CPU0 L1 parity interrupt clear. Write 1 to Clear
8832  *
8833  * Field Access Macros:
8834  *
8835  */
8836 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field. */
8837 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_LSB 0
8838 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field. */
8839 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_MSB 7
8840 /* The width in bits of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field. */
8841 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_WIDTH 8
8842 /* The mask used to set the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field value. */
8843 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET_MSK 0x000000ff
8844 /* The mask used to clear the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field value. */
8845 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8846 /* The reset value of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field. */
8847 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_RESET 0x0
8848 /* Extracts the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 field value from a register. */
8849 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8850 /* Produces a ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 register field value suitable for setting the register. */
8851 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8852 
8853 /*
8854  * Field : cpu1
8855  *
8856  * CPU1 L1 parity interrupt clear. Write 1 to Clear
8857  *
8858  * Field Access Macros:
8859  *
8860  */
8861 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field. */
8862 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_LSB 8
8863 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field. */
8864 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_MSB 15
8865 /* The width in bits of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field. */
8866 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_WIDTH 8
8867 /* The mask used to set the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field value. */
8868 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8869 /* The mask used to clear the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field value. */
8870 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8871 /* The reset value of the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field. */
8872 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_RESET 0x0
8873 /* Extracts the ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 field value from a register. */
8874 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8875 /* Produces a ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 register field value suitable for setting the register. */
8876 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8877 
8878 /*
8879  * Field : scu
8880  *
8881  * SCU parity interrupt clear. Write 1 to Clear
8882  *
8883  * Field Access Macros:
8884  *
8885  */
8886 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field. */
8887 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_LSB 16
8888 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field. */
8889 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_MSB 17
8890 /* The width in bits of the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field. */
8891 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_WIDTH 2
8892 /* The mask used to set the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field value. */
8893 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET_MSK 0x00030000
8894 /* The mask used to clear the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field value. */
8895 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8896 /* The reset value of the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field. */
8897 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_RESET 0x0
8898 /* Extracts the ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU field value from a register. */
8899 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8900 /* Produces a ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU register field value suitable for setting the register. */
8901 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8902 
8903 #ifndef __ASSEMBLY__
8904 /*
8905  * WARNING: The C register and register group struct declarations are provided for
8906  * convenience and illustrative purposes. They should, however, be used with
8907  * caution as the C language standard provides no guarantees about the alignment or
8908  * atomicity of device memory accesses. The recommended practice for writing
8909  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8910  * alt_write_word() functions.
8911  *
8912  * The struct declaration for register ALT_SYSMGR_MPU_CLR_L1_PARITY.
8913  */
8914 struct ALT_SYSMGR_MPU_CLR_L1_PARITY_s
8915 {
8916  uint32_t cpu0 : 8; /* ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0 */
8917  uint32_t cpu1 : 8; /* ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1 */
8918  uint32_t scu : 2; /* ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU */
8919  uint32_t : 14; /* *UNDEFINED* */
8920 };
8921 
8922 /* The typedef declaration for register ALT_SYSMGR_MPU_CLR_L1_PARITY. */
8923 typedef volatile struct ALT_SYSMGR_MPU_CLR_L1_PARITY_s ALT_SYSMGR_MPU_CLR_L1_PARITY_t;
8924 #endif /* __ASSEMBLY__ */
8925 
8926 /* The reset value of the ALT_SYSMGR_MPU_CLR_L1_PARITY register. */
8927 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_RESET 0x00000000
8928 /* The byte offset of the ALT_SYSMGR_MPU_CLR_L1_PARITY register from the beginning of the component. */
8929 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_OFST 0xb0
8930 
8931 /*
8932  * Register : mpu_set_l1_parity
8933  *
8934  * Parity status set bit.
8935  *
8936  * A write to 1 of a specific bit sets the curresponding parity status bit.
8937  *
8938  * This register is used only to check the specific ISR routine.
8939  *
8940  * A read of this register should not return an error, but the actual read value is
8941  * undefined.
8942  *
8943  * [17] CPU1 SCU parity error
8944  *
8945  * [16] CPU0 SCU parity error
8946  *
8947  * [15] CPU1 BTAC parity error
8948  *
8949  * [14] CPU1 GHB parity error
8950  *
8951  * [13] CPU1 instruction tag RAM parity error
8952  *
8953  * [12] CPU1 instruction data RAM parity error
8954  *
8955  * [11] CPU1 main TLB parity error
8956  *
8957  * [10] CPU1 data outer RAM parity error
8958  *
8959  * [9] CPU1 data tag RAM parity error
8960  *
8961  * [8] CPU1 data data RAM parity error.
8962  *
8963  * [7] CPU0 BTAC parity error
8964  *
8965  * [6] CPU0 GHB parity error
8966  *
8967  * [5] CPU0 instruction tag RAM parity error
8968  *
8969  * [4] CPU0 instruction data RAM parity error
8970  *
8971  * [3] CPU0 main TLB parity error
8972  *
8973  * [2] CPU0 data outer RAM parity error
8974  *
8975  * [1] CPU0 data tag RAM parity error
8976  *
8977  * [0] CPU0 data data RAM parity error.
8978  *
8979  * Register Layout
8980  *
8981  * Bits | Access | Reset | Description
8982  * :--------|:-------|:------|:----------------------------------
8983  * [7:0] | RW | 0x0 | ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0
8984  * [15:8] | RW | 0x0 | ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1
8985  * [17:16] | RW | 0x0 | ALT_SYSMGR_MPU_SET_L1_PARITY_SCU
8986  * [31:18] | ??? | 0x0 | *UNDEFINED*
8987  *
8988  */
8989 /*
8990  * Field : cpu0
8991  *
8992  * CPU0 L1 parity interrupt set. Write 1 to Set
8993  *
8994  * Field Access Macros:
8995  *
8996  */
8997 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field. */
8998 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_LSB 0
8999 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field. */
9000 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_MSB 7
9001 /* The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field. */
9002 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_WIDTH 8
9003 /* The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value. */
9004 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET_MSK 0x000000ff
9005 /* The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value. */
9006 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_CLR_MSK 0xffffff00
9007 /* The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field. */
9008 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_RESET 0x0
9009 /* Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 field value from a register. */
9010 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
9011 /* Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value suitable for setting the register. */
9012 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
9013 
9014 /*
9015  * Field : cpu1
9016  *
9017  * CPU1 L1 parity interrupt set. Write 1 to Set
9018  *
9019  * Field Access Macros:
9020  *
9021  */
9022 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field. */
9023 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_LSB 8
9024 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field. */
9025 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_MSB 15
9026 /* The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field. */
9027 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_WIDTH 8
9028 /* The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value. */
9029 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET_MSK 0x0000ff00
9030 /* The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value. */
9031 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
9032 /* The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field. */
9033 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_RESET 0x0
9034 /* Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 field value from a register. */
9035 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
9036 /* Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value suitable for setting the register. */
9037 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
9038 
9039 /*
9040  * Field : scu
9041  *
9042  * SCU parity interrupt set. Write 1 to Set
9043  *
9044  * Field Access Macros:
9045  *
9046  */
9047 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field. */
9048 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_LSB 16
9049 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field. */
9050 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_MSB 17
9051 /* The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field. */
9052 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_WIDTH 2
9053 /* The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value. */
9054 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET_MSK 0x00030000
9055 /* The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value. */
9056 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_CLR_MSK 0xfffcffff
9057 /* The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field. */
9058 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_RESET 0x0
9059 /* Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU field value from a register. */
9060 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
9061 /* Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value suitable for setting the register. */
9062 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
9063 
9064 #ifndef __ASSEMBLY__
9065 /*
9066  * WARNING: The C register and register group struct declarations are provided for
9067  * convenience and illustrative purposes. They should, however, be used with
9068  * caution as the C language standard provides no guarantees about the alignment or
9069  * atomicity of device memory accesses. The recommended practice for writing
9070  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9071  * alt_write_word() functions.
9072  *
9073  * The struct declaration for register ALT_SYSMGR_MPU_SET_L1_PARITY.
9074  */
9075 struct ALT_SYSMGR_MPU_SET_L1_PARITY_s
9076 {
9077  uint32_t cpu0 : 8; /* ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 */
9078  uint32_t cpu1 : 8; /* ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 */
9079  uint32_t scu : 2; /* ALT_SYSMGR_MPU_SET_L1_PARITY_SCU */
9080  uint32_t : 14; /* *UNDEFINED* */
9081 };
9082 
9083 /* The typedef declaration for register ALT_SYSMGR_MPU_SET_L1_PARITY. */
9084 typedef volatile struct ALT_SYSMGR_MPU_SET_L1_PARITY_s ALT_SYSMGR_MPU_SET_L1_PARITY_t;
9085 #endif /* __ASSEMBLY__ */
9086 
9087 /* The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY register. */
9088 #define ALT_SYSMGR_MPU_SET_L1_PARITY_RESET 0x00000000
9089 /* The byte offset of the ALT_SYSMGR_MPU_SET_L1_PARITY register from the beginning of the component. */
9090 #define ALT_SYSMGR_MPU_SET_L1_PARITY_OFST 0xb4
9091 
9092 /*
9093  * Register : noc_timeout
9094  *
9095  * Register Layout
9096  *
9097  * Bits | Access | Reset | Description
9098  * :-------|:-------|:------|:----------------------
9099  * [0] | RW | 0x0 | ALT_SYSMGR_NOC_TMO_EN
9100  * [31:1] | ??? | 0x0 | *UNDEFINED*
9101  *
9102  */
9103 /*
9104  * Field : en
9105  *
9106  * NOC Timeout Enable. Write 1 to enable noc timeout.
9107  *
9108  * Field Access Macros:
9109  *
9110  */
9111 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_TMO_EN register field. */
9112 #define ALT_SYSMGR_NOC_TMO_EN_LSB 0
9113 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_TMO_EN register field. */
9114 #define ALT_SYSMGR_NOC_TMO_EN_MSB 0
9115 /* The width in bits of the ALT_SYSMGR_NOC_TMO_EN register field. */
9116 #define ALT_SYSMGR_NOC_TMO_EN_WIDTH 1
9117 /* The mask used to set the ALT_SYSMGR_NOC_TMO_EN register field value. */
9118 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001
9119 /* The mask used to clear the ALT_SYSMGR_NOC_TMO_EN register field value. */
9120 #define ALT_SYSMGR_NOC_TMO_EN_CLR_MSK 0xfffffffe
9121 /* The reset value of the ALT_SYSMGR_NOC_TMO_EN register field. */
9122 #define ALT_SYSMGR_NOC_TMO_EN_RESET 0x0
9123 /* Extracts the ALT_SYSMGR_NOC_TMO_EN field value from a register. */
9124 #define ALT_SYSMGR_NOC_TMO_EN_GET(value) (((value) & 0x00000001) >> 0)
9125 /* Produces a ALT_SYSMGR_NOC_TMO_EN register field value suitable for setting the register. */
9126 #define ALT_SYSMGR_NOC_TMO_EN_SET(value) (((value) << 0) & 0x00000001)
9127 
9128 #ifndef __ASSEMBLY__
9129 /*
9130  * WARNING: The C register and register group struct declarations are provided for
9131  * convenience and illustrative purposes. They should, however, be used with
9132  * caution as the C language standard provides no guarantees about the alignment or
9133  * atomicity of device memory accesses. The recommended practice for writing
9134  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9135  * alt_write_word() functions.
9136  *
9137  * The struct declaration for register ALT_SYSMGR_NOC_TMO.
9138  */
9139 struct ALT_SYSMGR_NOC_TMO_s
9140 {
9141  uint32_t en : 1; /* ALT_SYSMGR_NOC_TMO_EN */
9142  uint32_t : 31; /* *UNDEFINED* */
9143 };
9144 
9145 /* The typedef declaration for register ALT_SYSMGR_NOC_TMO. */
9146 typedef volatile struct ALT_SYSMGR_NOC_TMO_s ALT_SYSMGR_NOC_TMO_t;
9147 #endif /* __ASSEMBLY__ */
9148 
9149 /* The reset value of the ALT_SYSMGR_NOC_TMO register. */
9150 #define ALT_SYSMGR_NOC_TMO_RESET 0x00000000
9151 /* The byte offset of the ALT_SYSMGR_NOC_TMO register from the beginning of the component. */
9152 #define ALT_SYSMGR_NOC_TMO_OFST 0xc0
9153 
9154 /*
9155  * Register : noc_idlereq_set
9156  *
9157  * Set IDLE request to each NOC master.
9158  *
9159  * Register Layout
9160  *
9161  * Bits | Access | Reset | Description
9162  * :--------|:-------|:--------|:----------------------------------
9163  * [0] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_H2F
9164  * [3:1] | ??? | Unknown | *UNDEFINED*
9165  * [4] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F
9166  * [7:5] | ??? | Unknown | *UNDEFINED*
9167  * [8] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_F2H
9168  * [15:9] | ??? | Unknown | *UNDEFINED*
9169  * [16] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0
9170  * [19:17] | ??? | Unknown | *UNDEFINED*
9171  * [20] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1
9172  * [23:21] | ??? | Unknown | *UNDEFINED*
9173  * [24] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2
9174  * [31:25] | ??? | Unknown | *UNDEFINED*
9175  *
9176  */
9177 /*
9178  * Field : soc2fpga
9179  *
9180  * Field Access Macros:
9181  *
9182  */
9183 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field. */
9184 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_LSB 0
9185 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field. */
9186 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_MSB 0
9187 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field. */
9188 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_WIDTH 1
9189 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field value. */
9190 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET_MSK 0x00000001
9191 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field value. */
9192 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_CLR_MSK 0xfffffffe
9193 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field is UNKNOWN. */
9194 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_RESET 0x0
9195 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_H2F field value from a register. */
9196 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_GET(value) (((value) & 0x00000001) >> 0)
9197 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_H2F register field value suitable for setting the register. */
9198 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET(value) (((value) << 0) & 0x00000001)
9199 
9200 /*
9201  * Field : lwsoc2fpga
9202  *
9203  * Field Access Macros:
9204  *
9205  */
9206 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field. */
9207 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_LSB 4
9208 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field. */
9209 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_MSB 4
9210 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field. */
9211 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_WIDTH 1
9212 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field value. */
9213 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET_MSK 0x00000010
9214 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field value. */
9215 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_CLR_MSK 0xffffffef
9216 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field is UNKNOWN. */
9217 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_RESET 0x0
9218 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F field value from a register. */
9219 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9220 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F register field value suitable for setting the register. */
9221 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9222 
9223 /*
9224  * Field : fpga2soc
9225  *
9226  * Field Access Macros:
9227  *
9228  */
9229 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field. */
9230 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_LSB 8
9231 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field. */
9232 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_MSB 8
9233 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field. */
9234 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_WIDTH 1
9235 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field value. */
9236 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET_MSK 0x00000100
9237 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field value. */
9238 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_CLR_MSK 0xfffffeff
9239 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field is UNKNOWN. */
9240 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_RESET 0x0
9241 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_F2H field value from a register. */
9242 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_GET(value) (((value) & 0x00000100) >> 8)
9243 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_F2H register field value suitable for setting the register. */
9244 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET(value) (((value) << 8) & 0x00000100)
9245 
9246 /*
9247  * Field : fpga2sdram0
9248  *
9249  * Field Access Macros:
9250  *
9251  */
9252 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field. */
9253 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_LSB 16
9254 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field. */
9255 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_MSB 16
9256 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field. */
9257 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_WIDTH 1
9258 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field value. */
9259 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET_MSK 0x00010000
9260 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field value. */
9261 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_CLR_MSK 0xfffeffff
9262 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field is UNKNOWN. */
9263 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_RESET 0x0
9264 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 field value from a register. */
9265 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9266 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 register field value suitable for setting the register. */
9267 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9268 
9269 /*
9270  * Field : fpga2sdram1
9271  *
9272  * Field Access Macros:
9273  *
9274  */
9275 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field. */
9276 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_LSB 20
9277 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field. */
9278 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_MSB 20
9279 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field. */
9280 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_WIDTH 1
9281 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field value. */
9282 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET_MSK 0x00100000
9283 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field value. */
9284 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_CLR_MSK 0xffefffff
9285 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field is UNKNOWN. */
9286 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_RESET 0x0
9287 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 field value from a register. */
9288 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9289 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 register field value suitable for setting the register. */
9290 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9291 
9292 /*
9293  * Field : fpga2sdram2
9294  *
9295  * Field Access Macros:
9296  *
9297  */
9298 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field. */
9299 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_LSB 24
9300 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field. */
9301 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_MSB 24
9302 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field. */
9303 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_WIDTH 1
9304 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field value. */
9305 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET_MSK 0x01000000
9306 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field value. */
9307 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_CLR_MSK 0xfeffffff
9308 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field is UNKNOWN. */
9309 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_RESET 0x0
9310 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 field value from a register. */
9311 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9312 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 register field value suitable for setting the register. */
9313 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9314 
9315 #ifndef __ASSEMBLY__
9316 /*
9317  * WARNING: The C register and register group struct declarations are provided for
9318  * convenience and illustrative purposes. They should, however, be used with
9319  * caution as the C language standard provides no guarantees about the alignment or
9320  * atomicity of device memory accesses. The recommended practice for writing
9321  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9322  * alt_write_word() functions.
9323  *
9324  * The struct declaration for register ALT_SYSMGR_NOC_IDLEREQ_SET.
9325  */
9326 struct ALT_SYSMGR_NOC_IDLEREQ_SET_s
9327 {
9328  uint32_t soc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_H2F */
9329  uint32_t : 3; /* *UNDEFINED* */
9330  uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F */
9331  uint32_t : 3; /* *UNDEFINED* */
9332  uint32_t fpga2soc : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_F2H */
9333  uint32_t : 7; /* *UNDEFINED* */
9334  uint32_t fpga2sdram0 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0 */
9335  uint32_t : 3; /* *UNDEFINED* */
9336  uint32_t fpga2sdram1 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1 */
9337  uint32_t : 3; /* *UNDEFINED* */
9338  uint32_t fpga2sdram2 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2 */
9339  uint32_t : 7; /* *UNDEFINED* */
9340 };
9341 
9342 /* The typedef declaration for register ALT_SYSMGR_NOC_IDLEREQ_SET. */
9343 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_SET_s ALT_SYSMGR_NOC_IDLEREQ_SET_t;
9344 #endif /* __ASSEMBLY__ */
9345 
9346 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_SET register. */
9347 #define ALT_SYSMGR_NOC_IDLEREQ_SET_RESET 0x00000000
9348 /* The byte offset of the ALT_SYSMGR_NOC_IDLEREQ_SET register from the beginning of the component. */
9349 #define ALT_SYSMGR_NOC_IDLEREQ_SET_OFST 0xc4
9350 
9351 /*
9352  * Register : noc_idlereq_clr
9353  *
9354  * Clear IDLE request to each NOC master.
9355  *
9356  * Register Layout
9357  *
9358  * Bits | Access | Reset | Description
9359  * :--------|:-------|:--------|:----------------------------------
9360  * [0] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F
9361  * [3:1] | ??? | Unknown | *UNDEFINED*
9362  * [4] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F
9363  * [7:5] | ??? | Unknown | *UNDEFINED*
9364  * [8] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H
9365  * [15:9] | ??? | Unknown | *UNDEFINED*
9366  * [16] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0
9367  * [19:17] | ??? | Unknown | *UNDEFINED*
9368  * [20] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1
9369  * [23:21] | ??? | Unknown | *UNDEFINED*
9370  * [24] | RW | Unknown | ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2
9371  * [31:25] | ??? | Unknown | *UNDEFINED*
9372  *
9373  */
9374 /*
9375  * Field : soc2fpga
9376  *
9377  * Field Access Macros:
9378  *
9379  */
9380 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field. */
9381 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_LSB 0
9382 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field. */
9383 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_MSB 0
9384 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field. */
9385 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_WIDTH 1
9386 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field value. */
9387 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET_MSK 0x00000001
9388 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field value. */
9389 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_CLR_MSK 0xfffffffe
9390 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field is UNKNOWN. */
9391 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_RESET 0x0
9392 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F field value from a register. */
9393 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_GET(value) (((value) & 0x00000001) >> 0)
9394 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F register field value suitable for setting the register. */
9395 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET(value) (((value) << 0) & 0x00000001)
9396 
9397 /*
9398  * Field : lwsoc2fpga
9399  *
9400  * Field Access Macros:
9401  *
9402  */
9403 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field. */
9404 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_LSB 4
9405 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field. */
9406 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_MSB 4
9407 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field. */
9408 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_WIDTH 1
9409 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field value. */
9410 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET_MSK 0x00000010
9411 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field value. */
9412 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_CLR_MSK 0xffffffef
9413 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field is UNKNOWN. */
9414 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_RESET 0x0
9415 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F field value from a register. */
9416 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9417 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F register field value suitable for setting the register. */
9418 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9419 
9420 /*
9421  * Field : fpga2soc
9422  *
9423  * Field Access Macros:
9424  *
9425  */
9426 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field. */
9427 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_LSB 8
9428 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field. */
9429 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_MSB 8
9430 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field. */
9431 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_WIDTH 1
9432 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field value. */
9433 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET_MSK 0x00000100
9434 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field value. */
9435 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_CLR_MSK 0xfffffeff
9436 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field is UNKNOWN. */
9437 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_RESET 0x0
9438 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H field value from a register. */
9439 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_GET(value) (((value) & 0x00000100) >> 8)
9440 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H register field value suitable for setting the register. */
9441 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET(value) (((value) << 8) & 0x00000100)
9442 
9443 /*
9444  * Field : fpga2sdram0
9445  *
9446  * Field Access Macros:
9447  *
9448  */
9449 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field. */
9450 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_LSB 16
9451 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field. */
9452 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_MSB 16
9453 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field. */
9454 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_WIDTH 1
9455 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field value. */
9456 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET_MSK 0x00010000
9457 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field value. */
9458 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_CLR_MSK 0xfffeffff
9459 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field is UNKNOWN. */
9460 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_RESET 0x0
9461 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 field value from a register. */
9462 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9463 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 register field value suitable for setting the register. */
9464 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9465 
9466 /*
9467  * Field : fpga2sdram1
9468  *
9469  * Field Access Macros:
9470  *
9471  */
9472 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field. */
9473 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_LSB 20
9474 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field. */
9475 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_MSB 20
9476 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field. */
9477 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_WIDTH 1
9478 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field value. */
9479 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET_MSK 0x00100000
9480 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field value. */
9481 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_CLR_MSK 0xffefffff
9482 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field is UNKNOWN. */
9483 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_RESET 0x0
9484 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 field value from a register. */
9485 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9486 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 register field value suitable for setting the register. */
9487 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9488 
9489 /*
9490  * Field : fpga2sdram2
9491  *
9492  * Field Access Macros:
9493  *
9494  */
9495 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field. */
9496 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_LSB 24
9497 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field. */
9498 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_MSB 24
9499 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field. */
9500 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_WIDTH 1
9501 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field value. */
9502 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET_MSK 0x01000000
9503 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field value. */
9504 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_CLR_MSK 0xfeffffff
9505 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field is UNKNOWN. */
9506 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_RESET 0x0
9507 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 field value from a register. */
9508 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9509 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 register field value suitable for setting the register. */
9510 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9511 
9512 #ifndef __ASSEMBLY__
9513 /*
9514  * WARNING: The C register and register group struct declarations are provided for
9515  * convenience and illustrative purposes. They should, however, be used with
9516  * caution as the C language standard provides no guarantees about the alignment or
9517  * atomicity of device memory accesses. The recommended practice for writing
9518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9519  * alt_write_word() functions.
9520  *
9521  * The struct declaration for register ALT_SYSMGR_NOC_IDLEREQ_CLR.
9522  */
9523 struct ALT_SYSMGR_NOC_IDLEREQ_CLR_s
9524 {
9525  uint32_t soc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F */
9526  uint32_t : 3; /* *UNDEFINED* */
9527  uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F */
9528  uint32_t : 3; /* *UNDEFINED* */
9529  uint32_t fpga2soc : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H */
9530  uint32_t : 7; /* *UNDEFINED* */
9531  uint32_t fpga2sdram0 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0 */
9532  uint32_t : 3; /* *UNDEFINED* */
9533  uint32_t fpga2sdram1 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1 */
9534  uint32_t : 3; /* *UNDEFINED* */
9535  uint32_t fpga2sdram2 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2 */
9536  uint32_t : 7; /* *UNDEFINED* */
9537 };
9538 
9539 /* The typedef declaration for register ALT_SYSMGR_NOC_IDLEREQ_CLR. */
9540 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_CLR_s ALT_SYSMGR_NOC_IDLEREQ_CLR_t;
9541 #endif /* __ASSEMBLY__ */
9542 
9543 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_CLR register. */
9544 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_RESET 0x00000000
9545 /* The byte offset of the ALT_SYSMGR_NOC_IDLEREQ_CLR register from the beginning of the component. */
9546 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_OFST 0xc8
9547 
9548 /*
9549  * Register : noc_idlereq_value
9550  *
9551  * IDLE request to each NOC master.
9552  *
9553  * This register can be set by writing 1 to the specific bit in noc_idlereq_set
9554  * register.
9555  *
9556  * This register can be cleared by writing 1 to the specific bit in noc_idlereq_clr
9557  * register
9558  *
9559  * Register Layout
9560  *
9561  * Bits | Access | Reset | Description
9562  * :--------|:-------|:------|:------------------------------------
9563  * [0] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F
9564  * [3:1] | ??? | 0x0 | *UNDEFINED*
9565  * [4] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F
9566  * [7:5] | ??? | 0x0 | *UNDEFINED*
9567  * [8] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H
9568  * [15:9] | ??? | 0x0 | *UNDEFINED*
9569  * [16] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0
9570  * [19:17] | ??? | 0x0 | *UNDEFINED*
9571  * [20] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1
9572  * [23:21] | ??? | 0x0 | *UNDEFINED*
9573  * [24] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2
9574  * [31:25] | ??? | 0x0 | *UNDEFINED*
9575  *
9576  */
9577 /*
9578  * Field : soc2fpga
9579  *
9580  * Field Access Macros:
9581  *
9582  */
9583 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field. */
9584 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_LSB 0
9585 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field. */
9586 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_MSB 0
9587 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field. */
9588 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_WIDTH 1
9589 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field value. */
9590 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET_MSK 0x00000001
9591 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field value. */
9592 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_CLR_MSK 0xfffffffe
9593 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field. */
9594 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_RESET 0x0
9595 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F field value from a register. */
9596 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_GET(value) (((value) & 0x00000001) >> 0)
9597 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F register field value suitable for setting the register. */
9598 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET(value) (((value) << 0) & 0x00000001)
9599 
9600 /*
9601  * Field : lwsoc2fpga
9602  *
9603  * Field Access Macros:
9604  *
9605  */
9606 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field. */
9607 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_LSB 4
9608 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field. */
9609 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_MSB 4
9610 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field. */
9611 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_WIDTH 1
9612 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field value. */
9613 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET_MSK 0x00000010
9614 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field value. */
9615 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_CLR_MSK 0xffffffef
9616 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field. */
9617 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_RESET 0x0
9618 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F field value from a register. */
9619 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9620 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F register field value suitable for setting the register. */
9621 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9622 
9623 /*
9624  * Field : fpga2soc
9625  *
9626  * Field Access Macros:
9627  *
9628  */
9629 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field. */
9630 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_LSB 8
9631 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field. */
9632 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_MSB 8
9633 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field. */
9634 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_WIDTH 1
9635 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field value. */
9636 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET_MSK 0x00000100
9637 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field value. */
9638 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_CLR_MSK 0xfffffeff
9639 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field. */
9640 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_RESET 0x0
9641 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H field value from a register. */
9642 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_GET(value) (((value) & 0x00000100) >> 8)
9643 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H register field value suitable for setting the register. */
9644 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET(value) (((value) << 8) & 0x00000100)
9645 
9646 /*
9647  * Field : fpga2sdram0
9648  *
9649  * Field Access Macros:
9650  *
9651  */
9652 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field. */
9653 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_LSB 16
9654 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field. */
9655 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_MSB 16
9656 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field. */
9657 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_WIDTH 1
9658 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field value. */
9659 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET_MSK 0x00010000
9660 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field value. */
9661 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_CLR_MSK 0xfffeffff
9662 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field. */
9663 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_RESET 0x0
9664 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 field value from a register. */
9665 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9666 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 register field value suitable for setting the register. */
9667 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9668 
9669 /*
9670  * Field : fpga2sdram1
9671  *
9672  * Field Access Macros:
9673  *
9674  */
9675 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field. */
9676 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_LSB 20
9677 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field. */
9678 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_MSB 20
9679 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field. */
9680 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_WIDTH 1
9681 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field value. */
9682 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET_MSK 0x00100000
9683 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field value. */
9684 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_CLR_MSK 0xffefffff
9685 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field. */
9686 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_RESET 0x0
9687 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 field value from a register. */
9688 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9689 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 register field value suitable for setting the register. */
9690 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9691 
9692 /*
9693  * Field : fpga2sdram2
9694  *
9695  * Field Access Macros:
9696  *
9697  */
9698 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field. */
9699 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_LSB 24
9700 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field. */
9701 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_MSB 24
9702 /* The width in bits of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field. */
9703 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_WIDTH 1
9704 /* The mask used to set the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field value. */
9705 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET_MSK 0x01000000
9706 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field value. */
9707 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_CLR_MSK 0xfeffffff
9708 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field. */
9709 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_RESET 0x0
9710 /* Extracts the ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 field value from a register. */
9711 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9712 /* Produces a ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 register field value suitable for setting the register. */
9713 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9714 
9715 #ifndef __ASSEMBLY__
9716 /*
9717  * WARNING: The C register and register group struct declarations are provided for
9718  * convenience and illustrative purposes. They should, however, be used with
9719  * caution as the C language standard provides no guarantees about the alignment or
9720  * atomicity of device memory accesses. The recommended practice for writing
9721  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9722  * alt_write_word() functions.
9723  *
9724  * The struct declaration for register ALT_SYSMGR_NOC_IDLEREQ_VALUE.
9725  */
9726 struct ALT_SYSMGR_NOC_IDLEREQ_VALUE_s
9727 {
9728  uint32_t soc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F */
9729  uint32_t : 3; /* *UNDEFINED* */
9730  uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F */
9731  uint32_t : 3; /* *UNDEFINED* */
9732  uint32_t fpga2soc : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H */
9733  uint32_t : 7; /* *UNDEFINED* */
9734  uint32_t fpga2sdram0 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0 */
9735  uint32_t : 3; /* *UNDEFINED* */
9736  uint32_t fpga2sdram1 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1 */
9737  uint32_t : 3; /* *UNDEFINED* */
9738  uint32_t fpga2sdram2 : 1; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2 */
9739  uint32_t : 7; /* *UNDEFINED* */
9740 };
9741 
9742 /* The typedef declaration for register ALT_SYSMGR_NOC_IDLEREQ_VALUE. */
9743 typedef volatile struct ALT_SYSMGR_NOC_IDLEREQ_VALUE_s ALT_SYSMGR_NOC_IDLEREQ_VALUE_t;
9744 #endif /* __ASSEMBLY__ */
9745 
9746 /* The reset value of the ALT_SYSMGR_NOC_IDLEREQ_VALUE register. */
9747 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_RESET 0x00000000
9748 /* The byte offset of the ALT_SYSMGR_NOC_IDLEREQ_VALUE register from the beginning of the component. */
9749 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_OFST 0xcc
9750 
9751 /*
9752  * Register : noc_idleack
9753  *
9754  * Idle acknowledge value from NOC Masters. This is asserted (value 1 in the field)
9755  * in response to the IDLE requests asserted by software.
9756  *
9757  * Register Layout
9758  *
9759  * Bits | Access | Reset | Description
9760  * :--------|:-------|:------|:------------------------------
9761  * [0] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_H2F
9762  * [3:1] | ??? | 0x0 | *UNDEFINED*
9763  * [4] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_LWH2F
9764  * [7:5] | ??? | 0x0 | *UNDEFINED*
9765  * [8] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_F2H
9766  * [15:9] | ??? | 0x0 | *UNDEFINED*
9767  * [16] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_F2SDR0
9768  * [19:17] | ??? | 0x0 | *UNDEFINED*
9769  * [20] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_F2SDR1
9770  * [23:21] | ??? | 0x0 | *UNDEFINED*
9771  * [24] | RW | 0x0 | ALT_SYSMGR_NOC_IDLEACK_F2SDR2
9772  * [31:25] | ??? | 0x0 | *UNDEFINED*
9773  *
9774  */
9775 /*
9776  * Field : soc2fpga
9777  *
9778  * Field Access Macros:
9779  *
9780  */
9781 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_H2F register field. */
9782 #define ALT_SYSMGR_NOC_IDLEACK_H2F_LSB 0
9783 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_H2F register field. */
9784 #define ALT_SYSMGR_NOC_IDLEACK_H2F_MSB 0
9785 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_H2F register field. */
9786 #define ALT_SYSMGR_NOC_IDLEACK_H2F_WIDTH 1
9787 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_H2F register field value. */
9788 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET_MSK 0x00000001
9789 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_H2F register field value. */
9790 #define ALT_SYSMGR_NOC_IDLEACK_H2F_CLR_MSK 0xfffffffe
9791 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_H2F register field. */
9792 #define ALT_SYSMGR_NOC_IDLEACK_H2F_RESET 0x0
9793 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_H2F field value from a register. */
9794 #define ALT_SYSMGR_NOC_IDLEACK_H2F_GET(value) (((value) & 0x00000001) >> 0)
9795 /* Produces a ALT_SYSMGR_NOC_IDLEACK_H2F register field value suitable for setting the register. */
9796 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET(value) (((value) << 0) & 0x00000001)
9797 
9798 /*
9799  * Field : lwsoc2fpga
9800  *
9801  * Field Access Macros:
9802  *
9803  */
9804 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field. */
9805 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_LSB 4
9806 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field. */
9807 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_MSB 4
9808 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field. */
9809 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_WIDTH 1
9810 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field value. */
9811 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET_MSK 0x00000010
9812 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field value. */
9813 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_CLR_MSK 0xffffffef
9814 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_LWH2F register field. */
9815 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_RESET 0x0
9816 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_LWH2F field value from a register. */
9817 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9818 /* Produces a ALT_SYSMGR_NOC_IDLEACK_LWH2F register field value suitable for setting the register. */
9819 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9820 
9821 /*
9822  * Field : fpga2soc
9823  *
9824  * Field Access Macros:
9825  *
9826  */
9827 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2H register field. */
9828 #define ALT_SYSMGR_NOC_IDLEACK_F2H_LSB 8
9829 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2H register field. */
9830 #define ALT_SYSMGR_NOC_IDLEACK_F2H_MSB 8
9831 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_F2H register field. */
9832 #define ALT_SYSMGR_NOC_IDLEACK_F2H_WIDTH 1
9833 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_F2H register field value. */
9834 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET_MSK 0x00000100
9835 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_F2H register field value. */
9836 #define ALT_SYSMGR_NOC_IDLEACK_F2H_CLR_MSK 0xfffffeff
9837 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_F2H register field. */
9838 #define ALT_SYSMGR_NOC_IDLEACK_F2H_RESET 0x0
9839 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_F2H field value from a register. */
9840 #define ALT_SYSMGR_NOC_IDLEACK_F2H_GET(value) (((value) & 0x00000100) >> 8)
9841 /* Produces a ALT_SYSMGR_NOC_IDLEACK_F2H register field value suitable for setting the register. */
9842 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET(value) (((value) << 8) & 0x00000100)
9843 
9844 /*
9845  * Field : fpga2sdram0
9846  *
9847  * Field Access Macros:
9848  *
9849  */
9850 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field. */
9851 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_LSB 16
9852 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field. */
9853 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_MSB 16
9854 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field. */
9855 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_WIDTH 1
9856 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field value. */
9857 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET_MSK 0x00010000
9858 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field value. */
9859 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_CLR_MSK 0xfffeffff
9860 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field. */
9861 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_RESET 0x0
9862 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_F2SDR0 field value from a register. */
9863 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9864 /* Produces a ALT_SYSMGR_NOC_IDLEACK_F2SDR0 register field value suitable for setting the register. */
9865 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9866 
9867 /*
9868  * Field : fpga2sdram1
9869  *
9870  * Field Access Macros:
9871  *
9872  */
9873 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field. */
9874 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_LSB 20
9875 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field. */
9876 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_MSB 20
9877 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field. */
9878 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_WIDTH 1
9879 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field value. */
9880 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET_MSK 0x00100000
9881 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field value. */
9882 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_CLR_MSK 0xffefffff
9883 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field. */
9884 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_RESET 0x0
9885 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_F2SDR1 field value from a register. */
9886 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9887 /* Produces a ALT_SYSMGR_NOC_IDLEACK_F2SDR1 register field value suitable for setting the register. */
9888 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9889 
9890 /*
9891  * Field : fpga2sdram2
9892  *
9893  * Field Access Macros:
9894  *
9895  */
9896 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field. */
9897 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_LSB 24
9898 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field. */
9899 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_MSB 24
9900 /* The width in bits of the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field. */
9901 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_WIDTH 1
9902 /* The mask used to set the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field value. */
9903 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET_MSK 0x01000000
9904 /* The mask used to clear the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field value. */
9905 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_CLR_MSK 0xfeffffff
9906 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field. */
9907 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_RESET 0x0
9908 /* Extracts the ALT_SYSMGR_NOC_IDLEACK_F2SDR2 field value from a register. */
9909 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9910 /* Produces a ALT_SYSMGR_NOC_IDLEACK_F2SDR2 register field value suitable for setting the register. */
9911 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9912 
9913 #ifndef __ASSEMBLY__
9914 /*
9915  * WARNING: The C register and register group struct declarations are provided for
9916  * convenience and illustrative purposes. They should, however, be used with
9917  * caution as the C language standard provides no guarantees about the alignment or
9918  * atomicity of device memory accesses. The recommended practice for writing
9919  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9920  * alt_write_word() functions.
9921  *
9922  * The struct declaration for register ALT_SYSMGR_NOC_IDLEACK.
9923  */
9924 struct ALT_SYSMGR_NOC_IDLEACK_s
9925 {
9926  uint32_t soc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEACK_H2F */
9927  uint32_t : 3; /* *UNDEFINED* */
9928  uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_NOC_IDLEACK_LWH2F */
9929  uint32_t : 3; /* *UNDEFINED* */
9930  uint32_t fpga2soc : 1; /* ALT_SYSMGR_NOC_IDLEACK_F2H */
9931  uint32_t : 7; /* *UNDEFINED* */
9932  uint32_t fpga2sdram0 : 1; /* ALT_SYSMGR_NOC_IDLEACK_F2SDR0 */
9933  uint32_t : 3; /* *UNDEFINED* */
9934  uint32_t fpga2sdram1 : 1; /* ALT_SYSMGR_NOC_IDLEACK_F2SDR1 */
9935  uint32_t : 3; /* *UNDEFINED* */
9936  uint32_t fpga2sdram2 : 1; /* ALT_SYSMGR_NOC_IDLEACK_F2SDR2 */
9937  uint32_t : 7; /* *UNDEFINED* */
9938 };
9939 
9940 /* The typedef declaration for register ALT_SYSMGR_NOC_IDLEACK. */
9941 typedef volatile struct ALT_SYSMGR_NOC_IDLEACK_s ALT_SYSMGR_NOC_IDLEACK_t;
9942 #endif /* __ASSEMBLY__ */
9943 
9944 /* The reset value of the ALT_SYSMGR_NOC_IDLEACK register. */
9945 #define ALT_SYSMGR_NOC_IDLEACK_RESET 0x00000000
9946 /* The byte offset of the ALT_SYSMGR_NOC_IDLEACK register from the beginning of the component. */
9947 #define ALT_SYSMGR_NOC_IDLEACK_OFST 0xd0
9948 
9949 /*
9950  * Register : noc_idlestatus
9951  *
9952  * Status of IDLE from the NOC masters. A 1 in the field means the specific master
9953  * is idle.
9954  *
9955  * Register Layout
9956  *
9957  * Bits | Access | Reset | Description
9958  * :--------|:-------|:------|:-------------------------------
9959  * [0] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_H2F
9960  * [3:1] | ??? | 0x0 | *UNDEFINED*
9961  * [4] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_LWH2F
9962  * [7:5] | ??? | 0x0 | *UNDEFINED*
9963  * [8] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_F2H
9964  * [15:9] | ??? | 0x0 | *UNDEFINED*
9965  * [16] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_F2SDR0
9966  * [19:17] | ??? | 0x0 | *UNDEFINED*
9967  * [20] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_F2SDR1
9968  * [23:21] | ??? | 0x0 | *UNDEFINED*
9969  * [24] | RW | 0x0 | ALT_SYSMGR_NOC_IDLESTAT_F2SDR2
9970  * [31:25] | ??? | 0x0 | *UNDEFINED*
9971  *
9972  */
9973 /*
9974  * Field : soc2fpga
9975  *
9976  * Field Access Macros:
9977  *
9978  */
9979 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_H2F register field. */
9980 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_LSB 0
9981 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_H2F register field. */
9982 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_MSB 0
9983 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_H2F register field. */
9984 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_WIDTH 1
9985 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_H2F register field value. */
9986 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET_MSK 0x00000001
9987 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_H2F register field value. */
9988 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_CLR_MSK 0xfffffffe
9989 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_H2F register field. */
9990 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_RESET 0x0
9991 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_H2F field value from a register. */
9992 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_GET(value) (((value) & 0x00000001) >> 0)
9993 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_H2F register field value suitable for setting the register. */
9994 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET(value) (((value) << 0) & 0x00000001)
9995 
9996 /*
9997  * Field : lwsoc2fpga
9998  *
9999  * Field Access Macros:
10000  *
10001  */
10002 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field. */
10003 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_LSB 4
10004 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field. */
10005 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_MSB 4
10006 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field. */
10007 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_WIDTH 1
10008 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field value. */
10009 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET_MSK 0x00000010
10010 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field value. */
10011 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_CLR_MSK 0xffffffef
10012 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field. */
10013 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_RESET 0x0
10014 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_LWH2F field value from a register. */
10015 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
10016 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_LWH2F register field value suitable for setting the register. */
10017 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET(value) (((value) << 4) & 0x00000010)
10018 
10019 /*
10020  * Field : fpga2soc
10021  *
10022  * Field Access Macros:
10023  *
10024  */
10025 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2H register field. */
10026 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_LSB 8
10027 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2H register field. */
10028 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_MSB 8
10029 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_F2H register field. */
10030 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_WIDTH 1
10031 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_F2H register field value. */
10032 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET_MSK 0x00000100
10033 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_F2H register field value. */
10034 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_CLR_MSK 0xfffffeff
10035 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_F2H register field. */
10036 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_RESET 0x0
10037 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_F2H field value from a register. */
10038 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_GET(value) (((value) & 0x00000100) >> 8)
10039 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_F2H register field value suitable for setting the register. */
10040 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET(value) (((value) << 8) & 0x00000100)
10041 
10042 /*
10043  * Field : fpga2sdram0
10044  *
10045  * Field Access Macros:
10046  *
10047  */
10048 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field. */
10049 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_LSB 16
10050 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field. */
10051 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_MSB 16
10052 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field. */
10053 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_WIDTH 1
10054 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field value. */
10055 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET_MSK 0x00010000
10056 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field value. */
10057 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_CLR_MSK 0xfffeffff
10058 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field. */
10059 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_RESET 0x0
10060 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 field value from a register. */
10061 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
10062 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 register field value suitable for setting the register. */
10063 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
10064 
10065 /*
10066  * Field : fpga2sdram1
10067  *
10068  * Field Access Macros:
10069  *
10070  */
10071 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field. */
10072 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_LSB 20
10073 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field. */
10074 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_MSB 20
10075 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field. */
10076 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_WIDTH 1
10077 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field value. */
10078 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET_MSK 0x00100000
10079 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field value. */
10080 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_CLR_MSK 0xffefffff
10081 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field. */
10082 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_RESET 0x0
10083 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 field value from a register. */
10084 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
10085 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 register field value suitable for setting the register. */
10086 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
10087 
10088 /*
10089  * Field : fpga2sdram2
10090  *
10091  * Field Access Macros:
10092  *
10093  */
10094 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field. */
10095 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_LSB 24
10096 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field. */
10097 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_MSB 24
10098 /* The width in bits of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field. */
10099 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_WIDTH 1
10100 /* The mask used to set the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field value. */
10101 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET_MSK 0x01000000
10102 /* The mask used to clear the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field value. */
10103 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_CLR_MSK 0xfeffffff
10104 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field. */
10105 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_RESET 0x0
10106 /* Extracts the ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 field value from a register. */
10107 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
10108 /* Produces a ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 register field value suitable for setting the register. */
10109 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
10110 
10111 #ifndef __ASSEMBLY__
10112 /*
10113  * WARNING: The C register and register group struct declarations are provided for
10114  * convenience and illustrative purposes. They should, however, be used with
10115  * caution as the C language standard provides no guarantees about the alignment or
10116  * atomicity of device memory accesses. The recommended practice for writing
10117  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10118  * alt_write_word() functions.
10119  *
10120  * The struct declaration for register ALT_SYSMGR_NOC_IDLESTAT.
10121  */
10122 struct ALT_SYSMGR_NOC_IDLESTAT_s
10123 {
10124  uint32_t soc2fpga : 1; /* ALT_SYSMGR_NOC_IDLESTAT_H2F */
10125  uint32_t : 3; /* *UNDEFINED* */
10126  uint32_t lwsoc2fpga : 1; /* ALT_SYSMGR_NOC_IDLESTAT_LWH2F */
10127  uint32_t : 3; /* *UNDEFINED* */
10128  uint32_t fpga2soc : 1; /* ALT_SYSMGR_NOC_IDLESTAT_F2H */
10129  uint32_t : 7; /* *UNDEFINED* */
10130  uint32_t fpga2sdram0 : 1; /* ALT_SYSMGR_NOC_IDLESTAT_F2SDR0 */
10131  uint32_t : 3; /* *UNDEFINED* */
10132  uint32_t fpga2sdram1 : 1; /* ALT_SYSMGR_NOC_IDLESTAT_F2SDR1 */
10133  uint32_t : 3; /* *UNDEFINED* */
10134  uint32_t fpga2sdram2 : 1; /* ALT_SYSMGR_NOC_IDLESTAT_F2SDR2 */
10135  uint32_t : 7; /* *UNDEFINED* */
10136 };
10137 
10138 /* The typedef declaration for register ALT_SYSMGR_NOC_IDLESTAT. */
10139 typedef volatile struct ALT_SYSMGR_NOC_IDLESTAT_s ALT_SYSMGR_NOC_IDLESTAT_t;
10140 #endif /* __ASSEMBLY__ */
10141 
10142 /* The reset value of the ALT_SYSMGR_NOC_IDLESTAT register. */
10143 #define ALT_SYSMGR_NOC_IDLESTAT_RESET 0x00000000
10144 /* The byte offset of the ALT_SYSMGR_NOC_IDLESTAT register from the beginning of the component. */
10145 #define ALT_SYSMGR_NOC_IDLESTAT_OFST 0xd4
10146 
10147 /*
10148  * Register : fpga2soc_ctrl
10149  *
10150  * Register Layout
10151  *
10152  * Bits | Access | Reset | Description
10153  * :-------|:-------|:--------|:--------------------------------
10154  * [0] | RW | 0x0 | ALT_SYSMGR_F2H_CTL_ALLOW_SECURE
10155  * [31:1] | ??? | Unknown | *UNDEFINED*
10156  *
10157  */
10158 /*
10159  * Field : allow_secure
10160  *
10161  * 0 - All Transactions from FPGA2SOC is converted to be Non-Secure
10162  *
10163  * 1 - Both Secure and Non-Secure Transactions is allowed by FPGA2SOC.
10164  *
10165  * Field Access Macros:
10166  *
10167  */
10168 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field. */
10169 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_LSB 0
10170 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field. */
10171 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_MSB 0
10172 /* The width in bits of the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field. */
10173 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_WIDTH 1
10174 /* The mask used to set the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field value. */
10175 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET_MSK 0x00000001
10176 /* The mask used to clear the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field value. */
10177 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_CLR_MSK 0xfffffffe
10178 /* The reset value of the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field. */
10179 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_RESET 0x0
10180 /* Extracts the ALT_SYSMGR_F2H_CTL_ALLOW_SECURE field value from a register. */
10181 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_GET(value) (((value) & 0x00000001) >> 0)
10182 /* Produces a ALT_SYSMGR_F2H_CTL_ALLOW_SECURE register field value suitable for setting the register. */
10183 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET(value) (((value) << 0) & 0x00000001)
10184 
10185 #ifndef __ASSEMBLY__
10186 /*
10187  * WARNING: The C register and register group struct declarations are provided for
10188  * convenience and illustrative purposes. They should, however, be used with
10189  * caution as the C language standard provides no guarantees about the alignment or
10190  * atomicity of device memory accesses. The recommended practice for writing
10191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10192  * alt_write_word() functions.
10193  *
10194  * The struct declaration for register ALT_SYSMGR_F2H_CTL.
10195  */
10196 struct ALT_SYSMGR_F2H_CTL_s
10197 {
10198  uint32_t allow_secure : 1; /* ALT_SYSMGR_F2H_CTL_ALLOW_SECURE */
10199  uint32_t : 31; /* *UNDEFINED* */
10200 };
10201 
10202 /* The typedef declaration for register ALT_SYSMGR_F2H_CTL. */
10203 typedef volatile struct ALT_SYSMGR_F2H_CTL_s ALT_SYSMGR_F2H_CTL_t;
10204 #endif /* __ASSEMBLY__ */
10205 
10206 /* The reset value of the ALT_SYSMGR_F2H_CTL register. */
10207 #define ALT_SYSMGR_F2H_CTL_RESET 0x00000000
10208 /* The byte offset of the ALT_SYSMGR_F2H_CTL register from the beginning of the component. */
10209 #define ALT_SYSMGR_F2H_CTL_OFST 0xd8
10210 
10211 /*
10212  * Register : tsmc_tsel_0
10213  *
10214  * Register Layout
10215  *
10216  * Bits | Access | Reset | Description
10217  * :--------|:-------|:------|:-----------------------------------
10218  * [1:0] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL
10219  * [3:2] | ??? | 0x0 | *UNDEFINED*
10220  * [5:4] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL
10221  * [7:6] | ??? | 0x0 | *UNDEFINED*
10222  * [9:8] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB
10223  * [15:10] | ??? | 0x0 | *UNDEFINED*
10224  * [17:16] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW
10225  * [19:18] | ??? | 0x0 | *UNDEFINED*
10226  * [21:20] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR
10227  * [23:22] | ??? | 0x0 | *UNDEFINED*
10228  * [26:24] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL
10229  * [27] | ??? | 0x0 | *UNDEFINED*
10230  * [29:28] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL
10231  * [31:30] | ??? | 0x0 | *UNDEFINED*
10232  *
10233  */
10234 /*
10235  * Field : rom_rtsel
10236  *
10237  * Field Access Macros:
10238  *
10239  */
10240 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field. */
10241 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_LSB 0
10242 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field. */
10243 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_MSB 1
10244 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field. */
10245 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_WIDTH 2
10246 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field value. */
10247 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET_MSK 0x00000003
10248 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field value. */
10249 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_CLR_MSK 0xfffffffc
10250 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field. */
10251 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_RESET 0x1
10252 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL field value from a register. */
10253 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_GET(value) (((value) & 0x00000003) >> 0)
10254 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL register field value suitable for setting the register. */
10255 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET(value) (((value) << 0) & 0x00000003)
10256 
10257 /*
10258  * Field : rom_ptsel
10259  *
10260  * Field Access Macros:
10261  *
10262  */
10263 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field. */
10264 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_LSB 4
10265 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field. */
10266 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_MSB 5
10267 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field. */
10268 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_WIDTH 2
10269 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field value. */
10270 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET_MSK 0x00000030
10271 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field value. */
10272 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_CLR_MSK 0xffffffcf
10273 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field. */
10274 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_RESET 0x1
10275 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL field value from a register. */
10276 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_GET(value) (((value) & 0x00000030) >> 4)
10277 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL register field value suitable for setting the register. */
10278 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET(value) (((value) << 4) & 0x00000030)
10279 
10280 /*
10281  * Field : rom_trb
10282  *
10283  * Field Access Macros:
10284  *
10285  */
10286 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field. */
10287 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_LSB 8
10288 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field. */
10289 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_MSB 9
10290 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field. */
10291 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_WIDTH 2
10292 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field value. */
10293 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET_MSK 0x00000300
10294 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field value. */
10295 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_CLR_MSK 0xfffffcff
10296 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field. */
10297 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_RESET 0x1
10298 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB field value from a register. */
10299 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_GET(value) (((value) & 0x00000300) >> 8)
10300 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB register field value suitable for setting the register. */
10301 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET(value) (((value) << 8) & 0x00000300)
10302 
10303 /*
10304  * Field : mpul1_mcw
10305  *
10306  * Field Access Macros:
10307  *
10308  */
10309 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field. */
10310 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_LSB 16
10311 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field. */
10312 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_MSB 17
10313 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field. */
10314 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_WIDTH 2
10315 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field value. */
10316 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET_MSK 0x00030000
10317 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field value. */
10318 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_CLR_MSK 0xfffcffff
10319 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field. */
10320 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_RESET 0x0
10321 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW field value from a register. */
10322 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_GET(value) (((value) & 0x00030000) >> 16)
10323 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW register field value suitable for setting the register. */
10324 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET(value) (((value) << 16) & 0x00030000)
10325 
10326 /*
10327  * Field : mpul1_mcr
10328  *
10329  * Field Access Macros:
10330  *
10331  */
10332 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field. */
10333 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_LSB 20
10334 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field. */
10335 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_MSB 21
10336 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field. */
10337 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_WIDTH 2
10338 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field value. */
10339 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET_MSK 0x00300000
10340 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field value. */
10341 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_CLR_MSK 0xffcfffff
10342 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field. */
10343 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_RESET 0x0
10344 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR field value from a register. */
10345 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_GET(value) (((value) & 0x00300000) >> 20)
10346 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR register field value suitable for setting the register. */
10347 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET(value) (((value) << 20) & 0x00300000)
10348 
10349 /*
10350  * Field : mpul2_wtsel
10351  *
10352  * Field Access Macros:
10353  *
10354  */
10355 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field. */
10356 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_LSB 24
10357 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field. */
10358 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_MSB 26
10359 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field. */
10360 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_WIDTH 3
10361 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field value. */
10362 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET_MSK 0x07000000
10363 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field value. */
10364 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_CLR_MSK 0xf8ffffff
10365 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field. */
10366 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_RESET 0x0
10367 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL field value from a register. */
10368 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10369 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL register field value suitable for setting the register. */
10370 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10371 
10372 /*
10373  * Field : mpul2_rtsel
10374  *
10375  * Field Access Macros:
10376  *
10377  */
10378 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field. */
10379 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_LSB 28
10380 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field. */
10381 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_MSB 29
10382 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field. */
10383 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_WIDTH 2
10384 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field value. */
10385 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET_MSK 0x30000000
10386 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field value. */
10387 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_CLR_MSK 0xcfffffff
10388 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field. */
10389 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_RESET 0x1
10390 /* Extracts the ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL field value from a register. */
10391 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10392 /* Produces a ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL register field value suitable for setting the register. */
10393 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10394 
10395 #ifndef __ASSEMBLY__
10396 /*
10397  * WARNING: The C register and register group struct declarations are provided for
10398  * convenience and illustrative purposes. They should, however, be used with
10399  * caution as the C language standard provides no guarantees about the alignment or
10400  * atomicity of device memory accesses. The recommended practice for writing
10401  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10402  * alt_write_word() functions.
10403  *
10404  * The struct declaration for register ALT_SYSMGR_TSMC_TSEL_0.
10405  */
10406 struct ALT_SYSMGR_TSMC_TSEL_0_s
10407 {
10408  uint32_t rom_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL */
10409  uint32_t : 2; /* *UNDEFINED* */
10410  uint32_t rom_ptsel : 2; /* ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL */
10411  uint32_t : 2; /* *UNDEFINED* */
10412  uint32_t rom_trb : 2; /* ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB */
10413  uint32_t : 6; /* *UNDEFINED* */
10414  uint32_t mpul1_mcw : 2; /* ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW */
10415  uint32_t : 2; /* *UNDEFINED* */
10416  uint32_t mpul1_mcr : 2; /* ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR */
10417  uint32_t : 2; /* *UNDEFINED* */
10418  uint32_t mpul2_wtsel : 3; /* ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL */
10419  uint32_t : 1; /* *UNDEFINED* */
10420  uint32_t mpul2_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL */
10421  uint32_t : 2; /* *UNDEFINED* */
10422 };
10423 
10424 /* The typedef declaration for register ALT_SYSMGR_TSMC_TSEL_0. */
10425 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_0_s ALT_SYSMGR_TSMC_TSEL_0_t;
10426 #endif /* __ASSEMBLY__ */
10427 
10428 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_0 register. */
10429 #define ALT_SYSMGR_TSMC_TSEL_0_RESET 0x10000111
10430 /* The byte offset of the ALT_SYSMGR_TSMC_TSEL_0 register from the beginning of the component. */
10431 #define ALT_SYSMGR_TSMC_TSEL_0_OFST 0x100
10432 
10433 /*
10434  * Register : tsmc_tsel_1
10435  *
10436  * Register Layout
10437  *
10438  * Bits | Access | Reset | Description
10439  * :--------|:-------|:------|:-----------------------------------
10440  * [2:0] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL
10441  * [3] | ??? | 0x0 | *UNDEFINED*
10442  * [5:4] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL
10443  * [7:6] | ??? | 0x0 | *UNDEFINED*
10444  * [10:8] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL
10445  * [11] | ??? | 0x0 | *UNDEFINED*
10446  * [13:12] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL
10447  * [15:14] | ??? | 0x0 | *UNDEFINED*
10448  * [18:16] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL
10449  * [19] | ??? | 0x0 | *UNDEFINED*
10450  * [21:20] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL
10451  * [23:22] | ??? | 0x0 | *UNDEFINED*
10452  * [26:24] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL
10453  * [27] | ??? | 0x0 | *UNDEFINED*
10454  * [29:28] | RW | 0x1 | ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL
10455  * [31:30] | ??? | 0x0 | *UNDEFINED*
10456  *
10457  */
10458 /*
10459  * Field : ocram_wtsel
10460  *
10461  * Field Access Macros:
10462  *
10463  */
10464 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field. */
10465 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_LSB 0
10466 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field. */
10467 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_MSB 2
10468 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field. */
10469 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_WIDTH 3
10470 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field value. */
10471 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET_MSK 0x00000007
10472 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field value. */
10473 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_CLR_MSK 0xfffffff8
10474 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field. */
10475 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_RESET 0x0
10476 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL field value from a register. */
10477 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_GET(value) (((value) & 0x00000007) >> 0)
10478 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL register field value suitable for setting the register. */
10479 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET(value) (((value) << 0) & 0x00000007)
10480 
10481 /*
10482  * Field : ocram_rtsel
10483  *
10484  * Field Access Macros:
10485  *
10486  */
10487 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field. */
10488 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_LSB 4
10489 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field. */
10490 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_MSB 5
10491 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field. */
10492 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_WIDTH 2
10493 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field value. */
10494 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET_MSK 0x00000030
10495 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field value. */
10496 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_CLR_MSK 0xffffffcf
10497 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field. */
10498 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_RESET 0x1
10499 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL field value from a register. */
10500 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_GET(value) (((value) & 0x00000030) >> 4)
10501 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL register field value suitable for setting the register. */
10502 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET(value) (((value) << 4) & 0x00000030)
10503 
10504 /*
10505  * Field : otg_wtsel
10506  *
10507  * Field Access Macros:
10508  *
10509  */
10510 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field. */
10511 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_LSB 8
10512 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field. */
10513 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_MSB 10
10514 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field. */
10515 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_WIDTH 3
10516 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field value. */
10517 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET_MSK 0x00000700
10518 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field value. */
10519 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_CLR_MSK 0xfffff8ff
10520 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field. */
10521 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_RESET 0x0
10522 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL field value from a register. */
10523 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_GET(value) (((value) & 0x00000700) >> 8)
10524 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL register field value suitable for setting the register. */
10525 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET(value) (((value) << 8) & 0x00000700)
10526 
10527 /*
10528  * Field : otg_rtsel
10529  *
10530  * Field Access Macros:
10531  *
10532  */
10533 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field. */
10534 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_LSB 12
10535 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field. */
10536 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_MSB 13
10537 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field. */
10538 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_WIDTH 2
10539 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field value. */
10540 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET_MSK 0x00003000
10541 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field value. */
10542 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_CLR_MSK 0xffffcfff
10543 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field. */
10544 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_RESET 0x1
10545 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL field value from a register. */
10546 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_GET(value) (((value) & 0x00003000) >> 12)
10547 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL register field value suitable for setting the register. */
10548 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET(value) (((value) << 12) & 0x00003000)
10549 
10550 /*
10551  * Field : qspi_wtsel
10552  *
10553  * Field Access Macros:
10554  *
10555  */
10556 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field. */
10557 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_LSB 16
10558 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field. */
10559 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_MSB 18
10560 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field. */
10561 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_WIDTH 3
10562 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field value. */
10563 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET_MSK 0x00070000
10564 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field value. */
10565 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_CLR_MSK 0xfff8ffff
10566 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field. */
10567 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_RESET 0x0
10568 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL field value from a register. */
10569 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_GET(value) (((value) & 0x00070000) >> 16)
10570 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL register field value suitable for setting the register. */
10571 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET(value) (((value) << 16) & 0x00070000)
10572 
10573 /*
10574  * Field : qspi_rtsel
10575  *
10576  * Field Access Macros:
10577  *
10578  */
10579 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field. */
10580 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_LSB 20
10581 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field. */
10582 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_MSB 21
10583 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field. */
10584 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_WIDTH 2
10585 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field value. */
10586 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET_MSK 0x00300000
10587 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field value. */
10588 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_CLR_MSK 0xffcfffff
10589 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field. */
10590 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_RESET 0x1
10591 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL field value from a register. */
10592 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_GET(value) (((value) & 0x00300000) >> 20)
10593 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL register field value suitable for setting the register. */
10594 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET(value) (((value) << 20) & 0x00300000)
10595 
10596 /*
10597  * Field : etf_wtsel
10598  *
10599  * Field Access Macros:
10600  *
10601  */
10602 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field. */
10603 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_LSB 24
10604 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field. */
10605 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_MSB 26
10606 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field. */
10607 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_WIDTH 3
10608 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field value. */
10609 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET_MSK 0x07000000
10610 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field value. */
10611 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_CLR_MSK 0xf8ffffff
10612 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field. */
10613 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_RESET 0x0
10614 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL field value from a register. */
10615 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10616 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL register field value suitable for setting the register. */
10617 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10618 
10619 /*
10620  * Field : etf_rtsel
10621  *
10622  * Field Access Macros:
10623  *
10624  */
10625 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field. */
10626 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_LSB 28
10627 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field. */
10628 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_MSB 29
10629 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field. */
10630 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_WIDTH 2
10631 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field value. */
10632 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET_MSK 0x30000000
10633 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field value. */
10634 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_CLR_MSK 0xcfffffff
10635 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field. */
10636 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_RESET 0x1
10637 /* Extracts the ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL field value from a register. */
10638 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10639 /* Produces a ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL register field value suitable for setting the register. */
10640 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10641 
10642 #ifndef __ASSEMBLY__
10643 /*
10644  * WARNING: The C register and register group struct declarations are provided for
10645  * convenience and illustrative purposes. They should, however, be used with
10646  * caution as the C language standard provides no guarantees about the alignment or
10647  * atomicity of device memory accesses. The recommended practice for writing
10648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10649  * alt_write_word() functions.
10650  *
10651  * The struct declaration for register ALT_SYSMGR_TSMC_TSEL_1.
10652  */
10653 struct ALT_SYSMGR_TSMC_TSEL_1_s
10654 {
10655  uint32_t ocram_wtsel : 3; /* ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL */
10656  uint32_t : 1; /* *UNDEFINED* */
10657  uint32_t ocram_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL */
10658  uint32_t : 2; /* *UNDEFINED* */
10659  uint32_t otg_wtsel : 3; /* ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL */
10660  uint32_t : 1; /* *UNDEFINED* */
10661  uint32_t otg_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL */
10662  uint32_t : 2; /* *UNDEFINED* */
10663  uint32_t qspi_wtsel : 3; /* ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL */
10664  uint32_t : 1; /* *UNDEFINED* */
10665  uint32_t qspi_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL */
10666  uint32_t : 2; /* *UNDEFINED* */
10667  uint32_t etf_wtsel : 3; /* ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL */
10668  uint32_t : 1; /* *UNDEFINED* */
10669  uint32_t etf_rtsel : 2; /* ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL */
10670  uint32_t : 2; /* *UNDEFINED* */
10671 };
10672 
10673 /* The typedef declaration for register ALT_SYSMGR_TSMC_TSEL_1. */
10674 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_1_s ALT_SYSMGR_TSMC_TSEL_1_t;
10675 #endif /* __ASSEMBLY__ */
10676 
10677 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_1 register. */
10678 #define ALT_SYSMGR_TSMC_TSEL_1_RESET 0x10101010
10679 /* The byte offset of the ALT_SYSMGR_TSMC_TSEL_1 register from the beginning of the component. */
10680 #define ALT_SYSMGR_TSMC_TSEL_1_OFST 0x104
10681 
10682 /*
10683  * Register : tsmc_tsel_2
10684  *
10685  * Register Layout
10686  *
10687  * Bits | Access | Reset | Description
10688  * :--------|:-------|:------|:-----------------------------------
10689  * [1:0] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT
10690  * [3:2] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT
10691  * [6:4] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP
10692  * [7] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM
10693  * [9:8] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT
10694  * [11:10] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT
10695  * [14:12] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP
10696  * [15] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM
10697  * [17:16] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT
10698  * [19:18] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT
10699  * [22:20] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP
10700  * [23] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM
10701  * [25:24] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT
10702  * [27:26] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT
10703  * [30:28] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP
10704  * [31] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM
10705  *
10706  */
10707 /*
10708  * Field : nandecc_wct
10709  *
10710  * Field Access Macros:
10711  *
10712  */
10713 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field. */
10714 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_LSB 0
10715 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field. */
10716 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_MSB 1
10717 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field. */
10718 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_WIDTH 2
10719 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value. */
10720 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET_MSK 0x00000003
10721 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value. */
10722 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_CLR_MSK 0xfffffffc
10723 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field. */
10724 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_RESET 0x2
10725 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT field value from a register. */
10726 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_GET(value) (((value) & 0x00000003) >> 0)
10727 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value suitable for setting the register. */
10728 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET(value) (((value) << 0) & 0x00000003)
10729 
10730 /*
10731  * Field : nandecc_rct
10732  *
10733  * Field Access Macros:
10734  *
10735  */
10736 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field. */
10737 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_LSB 2
10738 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field. */
10739 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_MSB 3
10740 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field. */
10741 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_WIDTH 2
10742 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value. */
10743 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET_MSK 0x0000000c
10744 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value. */
10745 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_CLR_MSK 0xfffffff3
10746 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field. */
10747 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_RESET 0x2
10748 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT field value from a register. */
10749 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_GET(value) (((value) & 0x0000000c) >> 2)
10750 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value suitable for setting the register. */
10751 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET(value) (((value) << 2) & 0x0000000c)
10752 
10753 /*
10754  * Field : nandecc_kp
10755  *
10756  * Field Access Macros:
10757  *
10758  */
10759 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field. */
10760 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_LSB 4
10761 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field. */
10762 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_MSB 6
10763 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field. */
10764 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_WIDTH 3
10765 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value. */
10766 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET_MSK 0x00000070
10767 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value. */
10768 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_CLR_MSK 0xffffff8f
10769 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field. */
10770 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_RESET 0x4
10771 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP field value from a register. */
10772 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_GET(value) (((value) & 0x00000070) >> 4)
10773 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value suitable for setting the register. */
10774 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET(value) (((value) << 4) & 0x00000070)
10775 
10776 /*
10777  * Field : nandecc_tm
10778  *
10779  * Field Access Macros:
10780  *
10781  */
10782 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field. */
10783 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_LSB 7
10784 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field. */
10785 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_MSB 7
10786 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field. */
10787 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_WIDTH 1
10788 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value. */
10789 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET_MSK 0x00000080
10790 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value. */
10791 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_CLR_MSK 0xffffff7f
10792 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field. */
10793 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_RESET 0x0
10794 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM field value from a register. */
10795 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_GET(value) (((value) & 0x00000080) >> 7)
10796 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value suitable for setting the register. */
10797 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET(value) (((value) << 7) & 0x00000080)
10798 
10799 /*
10800  * Field : nandwr_wct
10801  *
10802  * Field Access Macros:
10803  *
10804  */
10805 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field. */
10806 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_LSB 8
10807 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field. */
10808 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_MSB 9
10809 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field. */
10810 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_WIDTH 2
10811 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value. */
10812 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET_MSK 0x00000300
10813 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value. */
10814 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_CLR_MSK 0xfffffcff
10815 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field. */
10816 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_RESET 0x2
10817 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT field value from a register. */
10818 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_GET(value) (((value) & 0x00000300) >> 8)
10819 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value suitable for setting the register. */
10820 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET(value) (((value) << 8) & 0x00000300)
10821 
10822 /*
10823  * Field : nandwr_rct
10824  *
10825  * Field Access Macros:
10826  *
10827  */
10828 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field. */
10829 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_LSB 10
10830 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field. */
10831 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_MSB 11
10832 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field. */
10833 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_WIDTH 2
10834 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value. */
10835 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET_MSK 0x00000c00
10836 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value. */
10837 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_CLR_MSK 0xfffff3ff
10838 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field. */
10839 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_RESET 0x2
10840 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT field value from a register. */
10841 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_GET(value) (((value) & 0x00000c00) >> 10)
10842 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value suitable for setting the register. */
10843 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET(value) (((value) << 10) & 0x00000c00)
10844 
10845 /*
10846  * Field : nandwr_kp
10847  *
10848  * Field Access Macros:
10849  *
10850  */
10851 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field. */
10852 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_LSB 12
10853 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field. */
10854 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_MSB 14
10855 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field. */
10856 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_WIDTH 3
10857 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value. */
10858 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET_MSK 0x00007000
10859 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value. */
10860 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_CLR_MSK 0xffff8fff
10861 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field. */
10862 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_RESET 0x4
10863 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP field value from a register. */
10864 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_GET(value) (((value) & 0x00007000) >> 12)
10865 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value suitable for setting the register. */
10866 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET(value) (((value) << 12) & 0x00007000)
10867 
10868 /*
10869  * Field : nandwr_tm
10870  *
10871  * Field Access Macros:
10872  *
10873  */
10874 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field. */
10875 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_LSB 15
10876 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field. */
10877 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_MSB 15
10878 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field. */
10879 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_WIDTH 1
10880 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value. */
10881 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET_MSK 0x00008000
10882 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value. */
10883 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_CLR_MSK 0xffff7fff
10884 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field. */
10885 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_RESET 0x0
10886 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM field value from a register. */
10887 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_GET(value) (((value) & 0x00008000) >> 15)
10888 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value suitable for setting the register. */
10889 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET(value) (((value) << 15) & 0x00008000)
10890 
10891 /*
10892  * Field : nandrd_wct
10893  *
10894  * Field Access Macros:
10895  *
10896  */
10897 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field. */
10898 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_LSB 16
10899 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field. */
10900 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_MSB 17
10901 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field. */
10902 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_WIDTH 2
10903 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value. */
10904 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET_MSK 0x00030000
10905 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value. */
10906 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_CLR_MSK 0xfffcffff
10907 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field. */
10908 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_RESET 0x2
10909 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT field value from a register. */
10910 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_GET(value) (((value) & 0x00030000) >> 16)
10911 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value suitable for setting the register. */
10912 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET(value) (((value) << 16) & 0x00030000)
10913 
10914 /*
10915  * Field : nandrd_rct
10916  *
10917  * Field Access Macros:
10918  *
10919  */
10920 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field. */
10921 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_LSB 18
10922 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field. */
10923 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_MSB 19
10924 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field. */
10925 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_WIDTH 2
10926 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value. */
10927 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET_MSK 0x000c0000
10928 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value. */
10929 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_CLR_MSK 0xfff3ffff
10930 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field. */
10931 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_RESET 0x2
10932 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT field value from a register. */
10933 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_GET(value) (((value) & 0x000c0000) >> 18)
10934 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value suitable for setting the register. */
10935 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET(value) (((value) << 18) & 0x000c0000)
10936 
10937 /*
10938  * Field : nandrd_kp
10939  *
10940  * Field Access Macros:
10941  *
10942  */
10943 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field. */
10944 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_LSB 20
10945 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field. */
10946 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_MSB 22
10947 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field. */
10948 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_WIDTH 3
10949 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value. */
10950 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET_MSK 0x00700000
10951 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value. */
10952 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_CLR_MSK 0xff8fffff
10953 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field. */
10954 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_RESET 0x4
10955 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP field value from a register. */
10956 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_GET(value) (((value) & 0x00700000) >> 20)
10957 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value suitable for setting the register. */
10958 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET(value) (((value) << 20) & 0x00700000)
10959 
10960 /*
10961  * Field : nandrd_tm
10962  *
10963  * Field Access Macros:
10964  *
10965  */
10966 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field. */
10967 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_LSB 23
10968 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field. */
10969 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_MSB 23
10970 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field. */
10971 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_WIDTH 1
10972 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value. */
10973 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET_MSK 0x00800000
10974 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value. */
10975 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_CLR_MSK 0xff7fffff
10976 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field. */
10977 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_RESET 0x0
10978 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM field value from a register. */
10979 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_GET(value) (((value) & 0x00800000) >> 23)
10980 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value suitable for setting the register. */
10981 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET(value) (((value) << 23) & 0x00800000)
10982 
10983 /*
10984  * Field : sdmmc_wct
10985  *
10986  * Field Access Macros:
10987  *
10988  */
10989 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field. */
10990 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_LSB 24
10991 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field. */
10992 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_MSB 25
10993 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field. */
10994 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_WIDTH 2
10995 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value. */
10996 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET_MSK 0x03000000
10997 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value. */
10998 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_CLR_MSK 0xfcffffff
10999 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field. */
11000 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_RESET 0x2
11001 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT field value from a register. */
11002 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_GET(value) (((value) & 0x03000000) >> 24)
11003 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value suitable for setting the register. */
11004 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET(value) (((value) << 24) & 0x03000000)
11005 
11006 /*
11007  * Field : sdmmc_rct
11008  *
11009  * Field Access Macros:
11010  *
11011  */
11012 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field. */
11013 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_LSB 26
11014 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field. */
11015 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_MSB 27
11016 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field. */
11017 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_WIDTH 2
11018 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value. */
11019 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET_MSK 0x0c000000
11020 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value. */
11021 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_CLR_MSK 0xf3ffffff
11022 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field. */
11023 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_RESET 0x2
11024 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT field value from a register. */
11025 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_GET(value) (((value) & 0x0c000000) >> 26)
11026 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value suitable for setting the register. */
11027 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET(value) (((value) << 26) & 0x0c000000)
11028 
11029 /*
11030  * Field : sdmmc_kp
11031  *
11032  * Field Access Macros:
11033  *
11034  */
11035 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field. */
11036 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_LSB 28
11037 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field. */
11038 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_MSB 30
11039 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field. */
11040 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_WIDTH 3
11041 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value. */
11042 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET_MSK 0x70000000
11043 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value. */
11044 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_CLR_MSK 0x8fffffff
11045 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field. */
11046 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_RESET 0x4
11047 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP field value from a register. */
11048 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_GET(value) (((value) & 0x70000000) >> 28)
11049 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value suitable for setting the register. */
11050 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET(value) (((value) << 28) & 0x70000000)
11051 
11052 /*
11053  * Field : sdmmc_tm
11054  *
11055  * Field Access Macros:
11056  *
11057  */
11058 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field. */
11059 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_LSB 31
11060 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field. */
11061 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_MSB 31
11062 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field. */
11063 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_WIDTH 1
11064 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value. */
11065 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET_MSK 0x80000000
11066 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value. */
11067 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_CLR_MSK 0x7fffffff
11068 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field. */
11069 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_RESET 0x0
11070 /* Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM field value from a register. */
11071 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_GET(value) (((value) & 0x80000000) >> 31)
11072 /* Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value suitable for setting the register. */
11073 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET(value) (((value) << 31) & 0x80000000)
11074 
11075 #ifndef __ASSEMBLY__
11076 /*
11077  * WARNING: The C register and register group struct declarations are provided for
11078  * convenience and illustrative purposes. They should, however, be used with
11079  * caution as the C language standard provides no guarantees about the alignment or
11080  * atomicity of device memory accesses. The recommended practice for writing
11081  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11082  * alt_write_word() functions.
11083  *
11084  * The struct declaration for register ALT_SYSMGR_TSMC_TSEL_2.
11085  */
11086 struct ALT_SYSMGR_TSMC_TSEL_2_s
11087 {
11088  uint32_t nandecc_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT */
11089  uint32_t nandecc_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT */
11090  uint32_t nandecc_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP */
11091  uint32_t nandecc_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM */
11092  uint32_t nandwr_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT */
11093  uint32_t nandwr_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT */
11094  uint32_t nandwr_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP */
11095  uint32_t nandwr_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM */
11096  uint32_t nandrd_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT */
11097  uint32_t nandrd_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT */
11098  uint32_t nandrd_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP */
11099  uint32_t nandrd_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM */
11100  uint32_t sdmmc_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT */
11101  uint32_t sdmmc_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT */
11102  uint32_t sdmmc_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP */
11103  uint32_t sdmmc_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM */
11104 };
11105 
11106 /* The typedef declaration for register ALT_SYSMGR_TSMC_TSEL_2. */
11107 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_2_s ALT_SYSMGR_TSMC_TSEL_2_t;
11108 #endif /* __ASSEMBLY__ */
11109 
11110 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_2 register. */
11111 #define ALT_SYSMGR_TSMC_TSEL_2_RESET 0x4a4a4a4a
11112 /* The byte offset of the ALT_SYSMGR_TSMC_TSEL_2 register from the beginning of the component. */
11113 #define ALT_SYSMGR_TSMC_TSEL_2_OFST 0x108
11114 
11115 /*
11116  * Register : tsmc_tsel_3
11117  *
11118  * Register Layout
11119  *
11120  * Bits | Access | Reset | Description
11121  * :--------|:-------|:------|:----------------------------------
11122  * [1:0] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT
11123  * [3:2] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT
11124  * [6:4] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP
11125  * [7] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM
11126  * [9:8] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT
11127  * [11:10] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT
11128  * [14:12] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP
11129  * [15] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM
11130  * [17:16] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT
11131  * [19:18] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT
11132  * [22:20] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP
11133  * [23] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM
11134  * [31:24] | ??? | 0x0 | *UNDEFINED*
11135  *
11136  */
11137 /*
11138  * Field : emacrx_wct
11139  *
11140  * Field Access Macros:
11141  *
11142  */
11143 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field. */
11144 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_LSB 0
11145 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field. */
11146 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_MSB 1
11147 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field. */
11148 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_WIDTH 2
11149 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field value. */
11150 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET_MSK 0x00000003
11151 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field value. */
11152 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_CLR_MSK 0xfffffffc
11153 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field. */
11154 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_RESET 0x2
11155 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT field value from a register. */
11156 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_GET(value) (((value) & 0x00000003) >> 0)
11157 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT register field value suitable for setting the register. */
11158 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET(value) (((value) << 0) & 0x00000003)
11159 
11160 /*
11161  * Field : emacrx_rct
11162  *
11163  * Field Access Macros:
11164  *
11165  */
11166 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field. */
11167 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_LSB 2
11168 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field. */
11169 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_MSB 3
11170 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field. */
11171 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_WIDTH 2
11172 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field value. */
11173 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET_MSK 0x0000000c
11174 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field value. */
11175 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_CLR_MSK 0xfffffff3
11176 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field. */
11177 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_RESET 0x2
11178 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT field value from a register. */
11179 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_GET(value) (((value) & 0x0000000c) >> 2)
11180 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT register field value suitable for setting the register. */
11181 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET(value) (((value) << 2) & 0x0000000c)
11182 
11183 /*
11184  * Field : emacrx_kp
11185  *
11186  * Field Access Macros:
11187  *
11188  */
11189 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field. */
11190 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_LSB 4
11191 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field. */
11192 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_MSB 6
11193 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field. */
11194 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_WIDTH 3
11195 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field value. */
11196 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET_MSK 0x00000070
11197 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field value. */
11198 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_CLR_MSK 0xffffff8f
11199 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field. */
11200 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_RESET 0x4
11201 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP field value from a register. */
11202 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_GET(value) (((value) & 0x00000070) >> 4)
11203 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP register field value suitable for setting the register. */
11204 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET(value) (((value) << 4) & 0x00000070)
11205 
11206 /*
11207  * Field : emacrx_tm
11208  *
11209  * Field Access Macros:
11210  *
11211  */
11212 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field. */
11213 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_LSB 7
11214 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field. */
11215 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_MSB 7
11216 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field. */
11217 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_WIDTH 1
11218 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field value. */
11219 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET_MSK 0x00000080
11220 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field value. */
11221 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_CLR_MSK 0xffffff7f
11222 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field. */
11223 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_RESET 0x0
11224 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM field value from a register. */
11225 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_GET(value) (((value) & 0x00000080) >> 7)
11226 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM register field value suitable for setting the register. */
11227 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET(value) (((value) << 7) & 0x00000080)
11228 
11229 /*
11230  * Field : emactx_wct
11231  *
11232  * Field Access Macros:
11233  *
11234  */
11235 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field. */
11236 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_LSB 8
11237 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field. */
11238 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_MSB 9
11239 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field. */
11240 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_WIDTH 2
11241 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field value. */
11242 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET_MSK 0x00000300
11243 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field value. */
11244 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_CLR_MSK 0xfffffcff
11245 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field. */
11246 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_RESET 0x2
11247 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT field value from a register. */
11248 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_GET(value) (((value) & 0x00000300) >> 8)
11249 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT register field value suitable for setting the register. */
11250 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET(value) (((value) << 8) & 0x00000300)
11251 
11252 /*
11253  * Field : emactx_rct
11254  *
11255  * Field Access Macros:
11256  *
11257  */
11258 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field. */
11259 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_LSB 10
11260 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field. */
11261 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_MSB 11
11262 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field. */
11263 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_WIDTH 2
11264 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field value. */
11265 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET_MSK 0x00000c00
11266 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field value. */
11267 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_CLR_MSK 0xfffff3ff
11268 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field. */
11269 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_RESET 0x2
11270 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT field value from a register. */
11271 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_GET(value) (((value) & 0x00000c00) >> 10)
11272 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT register field value suitable for setting the register. */
11273 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET(value) (((value) << 10) & 0x00000c00)
11274 
11275 /*
11276  * Field : emactx_kp
11277  *
11278  * Field Access Macros:
11279  *
11280  */
11281 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field. */
11282 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_LSB 12
11283 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field. */
11284 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_MSB 14
11285 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field. */
11286 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_WIDTH 3
11287 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field value. */
11288 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET_MSK 0x00007000
11289 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field value. */
11290 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_CLR_MSK 0xffff8fff
11291 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field. */
11292 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_RESET 0x4
11293 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP field value from a register. */
11294 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_GET(value) (((value) & 0x00007000) >> 12)
11295 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP register field value suitable for setting the register. */
11296 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET(value) (((value) << 12) & 0x00007000)
11297 
11298 /*
11299  * Field : emactx_tm
11300  *
11301  * Field Access Macros:
11302  *
11303  */
11304 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field. */
11305 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_LSB 15
11306 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field. */
11307 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_MSB 15
11308 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field. */
11309 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_WIDTH 1
11310 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field value. */
11311 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET_MSK 0x00008000
11312 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field value. */
11313 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_CLR_MSK 0xffff7fff
11314 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field. */
11315 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_RESET 0x0
11316 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM field value from a register. */
11317 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_GET(value) (((value) & 0x00008000) >> 15)
11318 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM register field value suitable for setting the register. */
11319 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET(value) (((value) << 15) & 0x00008000)
11320 
11321 /*
11322  * Field : dmac_wct
11323  *
11324  * Field Access Macros:
11325  *
11326  */
11327 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field. */
11328 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_LSB 16
11329 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field. */
11330 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_MSB 17
11331 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field. */
11332 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_WIDTH 2
11333 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field value. */
11334 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET_MSK 0x00030000
11335 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field value. */
11336 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_CLR_MSK 0xfffcffff
11337 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field. */
11338 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_RESET 0x2
11339 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT field value from a register. */
11340 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_GET(value) (((value) & 0x00030000) >> 16)
11341 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT register field value suitable for setting the register. */
11342 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET(value) (((value) << 16) & 0x00030000)
11343 
11344 /*
11345  * Field : dmac_rct
11346  *
11347  * Field Access Macros:
11348  *
11349  */
11350 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field. */
11351 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_LSB 18
11352 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field. */
11353 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_MSB 19
11354 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field. */
11355 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_WIDTH 2
11356 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field value. */
11357 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET_MSK 0x000c0000
11358 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field value. */
11359 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_CLR_MSK 0xfff3ffff
11360 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field. */
11361 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_RESET 0x2
11362 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT field value from a register. */
11363 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_GET(value) (((value) & 0x000c0000) >> 18)
11364 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT register field value suitable for setting the register. */
11365 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET(value) (((value) << 18) & 0x000c0000)
11366 
11367 /*
11368  * Field : dmac_kp
11369  *
11370  * Field Access Macros:
11371  *
11372  */
11373 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field. */
11374 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_LSB 20
11375 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field. */
11376 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_MSB 22
11377 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field. */
11378 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_WIDTH 3
11379 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field value. */
11380 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET_MSK 0x00700000
11381 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field value. */
11382 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_CLR_MSK 0xff8fffff
11383 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field. */
11384 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_RESET 0x4
11385 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP field value from a register. */
11386 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_GET(value) (((value) & 0x00700000) >> 20)
11387 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP register field value suitable for setting the register. */
11388 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET(value) (((value) << 20) & 0x00700000)
11389 
11390 /*
11391  * Field : dmac_tm
11392  *
11393  * Field Access Macros:
11394  *
11395  */
11396 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field. */
11397 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_LSB 23
11398 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field. */
11399 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_MSB 23
11400 /* The width in bits of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field. */
11401 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_WIDTH 1
11402 /* The mask used to set the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field value. */
11403 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET_MSK 0x00800000
11404 /* The mask used to clear the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field value. */
11405 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_CLR_MSK 0xff7fffff
11406 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field. */
11407 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_RESET 0x0
11408 /* Extracts the ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM field value from a register. */
11409 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_GET(value) (((value) & 0x00800000) >> 23)
11410 /* Produces a ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM register field value suitable for setting the register. */
11411 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET(value) (((value) << 23) & 0x00800000)
11412 
11413 #ifndef __ASSEMBLY__
11414 /*
11415  * WARNING: The C register and register group struct declarations are provided for
11416  * convenience and illustrative purposes. They should, however, be used with
11417  * caution as the C language standard provides no guarantees about the alignment or
11418  * atomicity of device memory accesses. The recommended practice for writing
11419  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11420  * alt_write_word() functions.
11421  *
11422  * The struct declaration for register ALT_SYSMGR_TSMC_TSEL_3.
11423  */
11424 struct ALT_SYSMGR_TSMC_TSEL_3_s
11425 {
11426  uint32_t emacrx_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT */
11427  uint32_t emacrx_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT */
11428  uint32_t emacrx_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP */
11429  uint32_t emacrx_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM */
11430  uint32_t emactx_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT */
11431  uint32_t emactx_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT */
11432  uint32_t emactx_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP */
11433  uint32_t emactx_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM */
11434  uint32_t dmac_wct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT */
11435  uint32_t dmac_rct : 2; /* ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT */
11436  uint32_t dmac_kp : 3; /* ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP */
11437  uint32_t dmac_tm : 1; /* ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM */
11438  uint32_t : 8; /* *UNDEFINED* */
11439 };
11440 
11441 /* The typedef declaration for register ALT_SYSMGR_TSMC_TSEL_3. */
11442 typedef volatile struct ALT_SYSMGR_TSMC_TSEL_3_s ALT_SYSMGR_TSMC_TSEL_3_t;
11443 #endif /* __ASSEMBLY__ */
11444 
11445 /* The reset value of the ALT_SYSMGR_TSMC_TSEL_3 register. */
11446 #define ALT_SYSMGR_TSMC_TSEL_3_RESET 0x004a4a4a
11447 /* The byte offset of the ALT_SYSMGR_TSMC_TSEL_3 register from the beginning of the component. */
11448 #define ALT_SYSMGR_TSMC_TSEL_3_OFST 0x10c
11449 
11450 #ifndef __ASSEMBLY__
11451 /*
11452  * WARNING: The C register and register group struct declarations are provided for
11453  * convenience and illustrative purposes. They should, however, be used with
11454  * caution as the C language standard provides no guarantees about the alignment or
11455  * atomicity of device memory accesses. The recommended practice for writing
11456  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11457  * alt_write_word() functions.
11458  *
11459  * The struct declaration for register group ALT_SYSMGR.
11460  */
11461 struct ALT_SYSMGR_s
11462 {
11463  ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
11464  ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
11465  ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */
11466  ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */
11467  ALT_SYSMGR_MPU_CTL_L2_ECC_t mpu_ctrl_l2_ecc; /* ALT_SYSMGR_MPU_CTL_L2_ECC */
11468  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
11469  ALT_SYSMGR_DMA_t dma; /* ALT_SYSMGR_DMA */
11470  ALT_SYSMGR_DMA_PERIPH_t dma_periph; /* ALT_SYSMGR_DMA_PERIPH */
11471  ALT_SYSMGR_SDMMC_t sdmmc; /* ALT_SYSMGR_SDMMC */
11472  ALT_SYSMGR_SDMMC_L3MST_t sdmmc_l3master; /* ALT_SYSMGR_SDMMC_L3MST */
11473  ALT_SYSMGR_NAND_BOOTSTRAP_t nand_bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
11474  ALT_SYSMGR_NAND_L3MST_t nand_l3master; /* ALT_SYSMGR_NAND_L3MST */
11475  ALT_SYSMGR_USB0_L3MST_t usb0_l3master; /* ALT_SYSMGR_USB0_L3MST */
11476  ALT_SYSMGR_USB1_L3MST_t usb1_l3master; /* ALT_SYSMGR_USB1_L3MST */
11477  ALT_SYSMGR_EMAC_GLOB_t emac_global; /* ALT_SYSMGR_EMAC_GLOB */
11478  ALT_SYSMGR_EMAC0_t emac0; /* ALT_SYSMGR_EMAC0 */
11479  ALT_SYSMGR_EMAC1_t emac1; /* ALT_SYSMGR_EMAC1 */
11480  ALT_SYSMGR_EMAC2_t emac2; /* ALT_SYSMGR_EMAC2 */
11481  volatile uint32_t _pad_0x50_0x5f[4]; /* *UNDEFINED* */
11482  ALT_SYSMGR_FPGAINTF_EN_GLOB_t fpgaintf_en_global; /* ALT_SYSMGR_FPGAINTF_EN_GLOB */
11483  ALT_SYSMGR_FPGAINTF_EN_0_t fpgaintf_en_0; /* ALT_SYSMGR_FPGAINTF_EN_0 */
11484  ALT_SYSMGR_FPGAINTF_EN_1_t fpgaintf_en_1; /* ALT_SYSMGR_FPGAINTF_EN_1 */
11485  ALT_SYSMGR_FPGAINTF_EN_2_t fpgaintf_en_2; /* ALT_SYSMGR_FPGAINTF_EN_2 */
11486  ALT_SYSMGR_FPGAINTF_EN_3_t fpgaintf_en_3; /* ALT_SYSMGR_FPGAINTF_EN_3 */
11487  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
11488  ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_t noc_addr_remap_value; /* ALT_SYSMGR_NOC_ADDR_REMAP_VALUE */
11489  ALT_SYSMGR_NOC_ADDR_REMAP_SET_t noc_addr_remap_set; /* ALT_SYSMGR_NOC_ADDR_REMAP_SET */
11490  ALT_SYSMGR_NOC_ADDR_REMAP_CLR_t noc_addr_remap_clear; /* ALT_SYSMGR_NOC_ADDR_REMAP_CLR */
11491  volatile uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
11492  ALT_SYSMGR_ECC_INTMSK_VALUE_t ecc_intmask_value; /* ALT_SYSMGR_ECC_INTMSK_VALUE */
11493  ALT_SYSMGR_ECC_INTMSK_SET_t ecc_intmask_set; /* ALT_SYSMGR_ECC_INTMSK_SET */
11494  ALT_SYSMGR_ECC_INTMSK_CLR_t ecc_intmask_clr; /* ALT_SYSMGR_ECC_INTMSK_CLR */
11495  ALT_SYSMGR_ECC_INTSTAT_SERR_t ecc_intstatus_serr; /* ALT_SYSMGR_ECC_INTSTAT_SERR */
11496  ALT_SYSMGR_ECC_INTSTAT_DERR_t ecc_intstatus_derr; /* ALT_SYSMGR_ECC_INTSTAT_DERR */
11497  ALT_SYSMGR_MPU_STAT_L2_ECC_t mpu_status_l2_ecc; /* ALT_SYSMGR_MPU_STAT_L2_ECC */
11498  ALT_SYSMGR_MPU_CLR_L2_ECC_t mpu_clear_l2_ecc; /* ALT_SYSMGR_MPU_CLR_L2_ECC */
11499  ALT_SYSMGR_MPU_STAT_L1_PARITY_t mpu_status_l1_parity; /* ALT_SYSMGR_MPU_STAT_L1_PARITY */
11500  ALT_SYSMGR_MPU_CLR_L1_PARITY_t mpu_clear_l1_parity; /* ALT_SYSMGR_MPU_CLR_L1_PARITY */
11501  ALT_SYSMGR_MPU_SET_L1_PARITY_t mpu_set_l1_parity; /* ALT_SYSMGR_MPU_SET_L1_PARITY */
11502  volatile uint32_t _pad_0xb8_0xbf[2]; /* *UNDEFINED* */
11503  ALT_SYSMGR_NOC_TMO_t noc_timeout; /* ALT_SYSMGR_NOC_TMO */
11504  ALT_SYSMGR_NOC_IDLEREQ_SET_t noc_idlereq_set; /* ALT_SYSMGR_NOC_IDLEREQ_SET */
11505  ALT_SYSMGR_NOC_IDLEREQ_CLR_t noc_idlereq_clr; /* ALT_SYSMGR_NOC_IDLEREQ_CLR */
11506  ALT_SYSMGR_NOC_IDLEREQ_VALUE_t noc_idlereq_value; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE */
11507  ALT_SYSMGR_NOC_IDLEACK_t noc_idleack; /* ALT_SYSMGR_NOC_IDLEACK */
11508  ALT_SYSMGR_NOC_IDLESTAT_t noc_idlestatus; /* ALT_SYSMGR_NOC_IDLESTAT */
11509  ALT_SYSMGR_F2H_CTL_t fpga2soc_ctrl; /* ALT_SYSMGR_F2H_CTL */
11510  volatile uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */
11511  ALT_SYSMGR_TSMC_TSEL_0_t tsmc_tsel_0; /* ALT_SYSMGR_TSMC_TSEL_0 */
11512  ALT_SYSMGR_TSMC_TSEL_1_t tsmc_tsel_1; /* ALT_SYSMGR_TSMC_TSEL_1 */
11513  ALT_SYSMGR_TSMC_TSEL_2_t tsmc_tsel_2; /* ALT_SYSMGR_TSMC_TSEL_2 */
11514  ALT_SYSMGR_TSMC_TSEL_3_t tsmc_tsel_3; /* ALT_SYSMGR_TSMC_TSEL_3 */
11515  volatile uint32_t _pad_0x110_0x200[60]; /* *UNDEFINED* */
11516 };
11517 
11518 /* The typedef declaration for register group ALT_SYSMGR. */
11519 typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
11520 /* The struct declaration for the raw register contents of register group ALT_SYSMGR. */
11521 struct ALT_SYSMGR_raw_s
11522 {
11523  volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
11524  volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
11525  volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */
11526  volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */
11527  volatile uint32_t mpu_ctrl_l2_ecc; /* ALT_SYSMGR_MPU_CTL_L2_ECC */
11528  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
11529  volatile uint32_t dma; /* ALT_SYSMGR_DMA */
11530  volatile uint32_t dma_periph; /* ALT_SYSMGR_DMA_PERIPH */
11531  volatile uint32_t sdmmc; /* ALT_SYSMGR_SDMMC */
11532  volatile uint32_t sdmmc_l3master; /* ALT_SYSMGR_SDMMC_L3MST */
11533  volatile uint32_t nand_bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
11534  volatile uint32_t nand_l3master; /* ALT_SYSMGR_NAND_L3MST */
11535  volatile uint32_t usb0_l3master; /* ALT_SYSMGR_USB0_L3MST */
11536  volatile uint32_t usb1_l3master; /* ALT_SYSMGR_USB1_L3MST */
11537  volatile uint32_t emac_global; /* ALT_SYSMGR_EMAC_GLOB */
11538  volatile uint32_t emac0; /* ALT_SYSMGR_EMAC0 */
11539  volatile uint32_t emac1; /* ALT_SYSMGR_EMAC1 */
11540  volatile uint32_t emac2; /* ALT_SYSMGR_EMAC2 */
11541  uint32_t _pad_0x50_0x5f[4]; /* *UNDEFINED* */
11542  volatile uint32_t fpgaintf_en_global; /* ALT_SYSMGR_FPGAINTF_EN_GLOB */
11543  volatile uint32_t fpgaintf_en_0; /* ALT_SYSMGR_FPGAINTF_EN_0 */
11544  volatile uint32_t fpgaintf_en_1; /* ALT_SYSMGR_FPGAINTF_EN_1 */
11545  volatile uint32_t fpgaintf_en_2; /* ALT_SYSMGR_FPGAINTF_EN_2 */
11546  volatile uint32_t fpgaintf_en_3; /* ALT_SYSMGR_FPGAINTF_EN_3 */
11547  uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
11548  volatile uint32_t noc_addr_remap_value; /* ALT_SYSMGR_NOC_ADDR_REMAP_VALUE */
11549  volatile uint32_t noc_addr_remap_set; /* ALT_SYSMGR_NOC_ADDR_REMAP_SET */
11550  volatile uint32_t noc_addr_remap_clear; /* ALT_SYSMGR_NOC_ADDR_REMAP_CLR */
11551  uint32_t _pad_0x8c_0x8f; /* *UNDEFINED* */
11552  volatile uint32_t ecc_intmask_value; /* ALT_SYSMGR_ECC_INTMSK_VALUE */
11553  volatile uint32_t ecc_intmask_set; /* ALT_SYSMGR_ECC_INTMSK_SET */
11554  volatile uint32_t ecc_intmask_clr; /* ALT_SYSMGR_ECC_INTMSK_CLR */
11555  volatile uint32_t ecc_intstatus_serr; /* ALT_SYSMGR_ECC_INTSTAT_SERR */
11556  volatile uint32_t ecc_intstatus_derr; /* ALT_SYSMGR_ECC_INTSTAT_DERR */
11557  volatile uint32_t mpu_status_l2_ecc; /* ALT_SYSMGR_MPU_STAT_L2_ECC */
11558  volatile uint32_t mpu_clear_l2_ecc; /* ALT_SYSMGR_MPU_CLR_L2_ECC */
11559  volatile uint32_t mpu_status_l1_parity; /* ALT_SYSMGR_MPU_STAT_L1_PARITY */
11560  volatile uint32_t mpu_clear_l1_parity; /* ALT_SYSMGR_MPU_CLR_L1_PARITY */
11561  volatile uint32_t mpu_set_l1_parity; /* ALT_SYSMGR_MPU_SET_L1_PARITY */
11562  uint32_t _pad_0xb8_0xbf[2]; /* *UNDEFINED* */
11563  volatile uint32_t noc_timeout; /* ALT_SYSMGR_NOC_TMO */
11564  volatile uint32_t noc_idlereq_set; /* ALT_SYSMGR_NOC_IDLEREQ_SET */
11565  volatile uint32_t noc_idlereq_clr; /* ALT_SYSMGR_NOC_IDLEREQ_CLR */
11566  volatile uint32_t noc_idlereq_value; /* ALT_SYSMGR_NOC_IDLEREQ_VALUE */
11567  volatile uint32_t noc_idleack; /* ALT_SYSMGR_NOC_IDLEACK */
11568  volatile uint32_t noc_idlestatus; /* ALT_SYSMGR_NOC_IDLESTAT */
11569  volatile uint32_t fpga2soc_ctrl; /* ALT_SYSMGR_F2H_CTL */
11570  uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */
11571  volatile uint32_t tsmc_tsel_0; /* ALT_SYSMGR_TSMC_TSEL_0 */
11572  volatile uint32_t tsmc_tsel_1; /* ALT_SYSMGR_TSMC_TSEL_1 */
11573  volatile uint32_t tsmc_tsel_2; /* ALT_SYSMGR_TSMC_TSEL_2 */
11574  volatile uint32_t tsmc_tsel_3; /* ALT_SYSMGR_TSMC_TSEL_3 */
11575  uint32_t _pad_0x110_0x200[60]; /* *UNDEFINED* */
11576 };
11577 
11578 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */
11579 typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
11580 #endif /* __ASSEMBLY__ */
11581 
11582 
11583 /*
11584  * Component : ALT_SYSMGR_ROM
11585  *
11586  */
11587 /*
11588  * Register : Boot ROM Hardware Control Register - romhw_ctrl
11589  *
11590  * Controls behavior of Boot ROM hardware.
11591  *
11592  * Reset only on a cold reset.
11593  *
11594  * Register Layout
11595  *
11596  * Bits | Access | Reset | Description
11597  * :-------|:-------|:------|:------------
11598  * [0] | RW | 0x0 | Wait State
11599  * [31:1] | ??? | 0x80 | *UNDEFINED*
11600  *
11601  */
11602 /*
11603  * Field : Wait State - waitstate
11604  *
11605  * Controls the number of wait states applied to the Boot ROM's read operation.
11606  *
11607  * This field is cleared on a cold reset and optionally updated by hardware upon
11608  * deassertion of warm reset.
11609  *
11610  * Field Enumeration Values:
11611  *
11612  * Enum | Value | Description
11613  * :-----------------------------------------|:------|:------------
11614  * ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 |
11615  * ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_EN | 0x1 |
11616  *
11617  * Field Access Macros:
11618  *
11619  */
11620 /*
11621  * Enumerated value for register field ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE
11622  *
11623  */
11624 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_DIS 0x0
11625 /*
11626  * Enumerated value for register field ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE
11627  *
11628  */
11629 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_EN 0x1
11630 
11631 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field. */
11632 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_LSB 0
11633 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field. */
11634 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_MSB 0
11635 /* The width in bits of the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field. */
11636 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_WIDTH 1
11637 /* The mask used to set the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field value. */
11638 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
11639 /* The mask used to clear the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field value. */
11640 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
11641 /* The reset value of the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field. */
11642 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_RESET 0x0
11643 /* Extracts the ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE field value from a register. */
11644 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
11645 /* Produces a ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */
11646 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
11647 
11648 #ifndef __ASSEMBLY__
11649 /*
11650  * WARNING: The C register and register group struct declarations are provided for
11651  * convenience and illustrative purposes. They should, however, be used with
11652  * caution as the C language standard provides no guarantees about the alignment or
11653  * atomicity of device memory accesses. The recommended practice for writing
11654  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11655  * alt_write_word() functions.
11656  *
11657  * The struct declaration for register ALT_SYSMGR_ROM_ROMHW_CTL.
11658  */
11659 struct ALT_SYSMGR_ROM_ROMHW_CTL_s
11660 {
11661  uint32_t waitstate : 1; /* Wait State */
11662  uint32_t : 31; /* *UNDEFINED* */
11663 };
11664 
11665 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMHW_CTL. */
11666 typedef volatile struct ALT_SYSMGR_ROM_ROMHW_CTL_s ALT_SYSMGR_ROM_ROMHW_CTL_t;
11667 #endif /* __ASSEMBLY__ */
11668 
11669 /* The reset value of the ALT_SYSMGR_ROM_ROMHW_CTL register. */
11670 #define ALT_SYSMGR_ROM_ROMHW_CTL_RESET 0x00000100
11671 /* The byte offset of the ALT_SYSMGR_ROM_ROMHW_CTL register from the beginning of the component. */
11672 #define ALT_SYSMGR_ROM_ROMHW_CTL_OFST 0x0
11673 
11674 /*
11675  * Register : Control Register - romcode_ctrl
11676  *
11677  * Contains information used to control Boot ROM code.
11678  *
11679  * Reset only on a cold reset.
11680  *
11681  * Register Layout
11682  *
11683  * Bits | Access | Reset | Description
11684  * :-------|:-------|:------|:-------------------------------------------
11685  * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins
11686  * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins
11687  * [31:2] | ??? | 0x0 | *UNDEFINED*
11688  *
11689  */
11690 /*
11691  * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux
11692  *
11693  * Specifies whether the Boot ROM code configures the pin mux for boot pins after a
11694  * warm reset. Note that the Boot ROM code always configures the pin mux for boot
11695  * pins after a cold reset. After the Boot ROM code configures the pin mux for boot
11696  * pins, it always disables this field. It is up to user software to enable this
11697  * field if it wants a different behavior.
11698  *
11699  * Field Enumeration Values:
11700  *
11701  * Enum | Value | Description
11702  * :---------------------------------------------------|:------|:------------
11703  * ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 |
11704  * ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 |
11705  *
11706  * Field Access Macros:
11707  *
11708  */
11709 /*
11710  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX
11711  *
11712  */
11713 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
11714 /*
11715  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX
11716  *
11717  */
11718 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
11719 
11720 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
11721 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
11722 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
11723 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
11724 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
11725 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
11726 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
11727 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
11728 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
11729 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
11730 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
11731 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
11732 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */
11733 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
11734 /* Produces a ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */
11735 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
11736 
11737 /*
11738  * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio
11739  *
11740  * Specifies whether the Boot ROM code configures the IOs used by boot after a warm
11741  * reset. Note that the Boot ROM code always configures the IOs used by boot after
11742  * a cold reset. After the Boot ROM code configures the IOs used by boot, it always
11743  * disables this field. It is up to user software to enable this field if it wants
11744  * a different behavior.
11745  *
11746  * Field Enumeration Values:
11747  *
11748  * Enum | Value | Description
11749  * :-----------------------------------------------|:------|:------------
11750  * ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 |
11751  * ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 |
11752  *
11753  * Field Access Macros:
11754  *
11755  */
11756 /*
11757  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO
11758  *
11759  */
11760 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
11761 /*
11762  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO
11763  *
11764  */
11765 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
11766 
11767 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field. */
11768 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
11769 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field. */
11770 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
11771 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field. */
11772 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
11773 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value. */
11774 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
11775 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value. */
11776 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
11777 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field. */
11778 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
11779 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */
11780 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
11781 /* Produces a ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */
11782 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
11783 
11784 #ifndef __ASSEMBLY__
11785 /*
11786  * WARNING: The C register and register group struct declarations are provided for
11787  * convenience and illustrative purposes. They should, however, be used with
11788  * caution as the C language standard provides no guarantees about the alignment or
11789  * atomicity of device memory accesses. The recommended practice for writing
11790  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11791  * alt_write_word() functions.
11792  *
11793  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_CTL.
11794  */
11795 struct ALT_SYSMGR_ROM_ROMCODE_CTL_s
11796 {
11797  uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */
11798  uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */
11799  uint32_t : 30; /* *UNDEFINED* */
11800 };
11801 
11802 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_CTL. */
11803 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_CTL_s ALT_SYSMGR_ROM_ROMCODE_CTL_t;
11804 #endif /* __ASSEMBLY__ */
11805 
11806 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL register. */
11807 #define ALT_SYSMGR_ROM_ROMCODE_CTL_RESET 0x00000000
11808 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_CTL register from the beginning of the component. */
11809 #define ALT_SYSMGR_ROM_ROMCODE_CTL_OFST 0x4
11810 
11811 /*
11812  * Register : QSPI reset command - romcode_qspi_reset_command
11813  *
11814  * Information used by bootrom to send specific reset command sequences to QSPI.
11815  *
11816  * This register value gets reset only on a cold reset.
11817  *
11818  * Below are the definisions used by bootrom
11819  *
11820  * 0xXXXXXX00: Don't software reset.
11821  *
11822  * 0xXXXXXX01: Send 0x66, 0x99 as reset command.
11823  *
11824  * 0xXXXXXX02: Send 0xFF as reset command.
11825  *
11826  * 0xXXXXXX03: Send TBA as reset command.
11827  *
11828  * There is also a custom command for devices we don't know about yet.
11829  *
11830  * 0xXXXXZZ81: Send byte 0xZZ as reset command.
11831  *
11832  * 0xXXWWZZ82: Send byte 0xZZ, 0xWW as reset command.
11833  *
11834  * 0xYYWWZZ83: Send byte 0xZZ, 0xWW, 0xYY as reset command.
11835  *
11836  * Register Layout
11837  *
11838  * Bits | Access | Reset | Description
11839  * :-------|:-------|:------|:------------
11840  * [31:0] | RW | 0x0 | Address
11841  *
11842  */
11843 /*
11844  * Field : Address - value
11845  *
11846  * Address for CPU1 to start executing at after coming out of reset.
11847  *
11848  * Field Access Macros:
11849  *
11850  */
11851 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field. */
11852 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_LSB 0
11853 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field. */
11854 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_MSB 31
11855 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field. */
11856 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_WIDTH 32
11857 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field value. */
11858 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET_MSK 0xffffffff
11859 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field value. */
11860 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_CLR_MSK 0x00000000
11861 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field. */
11862 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_RESET 0x0
11863 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE field value from a register. */
11864 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11865 /* Produces a ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE register field value suitable for setting the register. */
11866 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11867 
11868 #ifndef __ASSEMBLY__
11869 /*
11870  * WARNING: The C register and register group struct declarations are provided for
11871  * convenience and illustrative purposes. They should, however, be used with
11872  * caution as the C language standard provides no guarantees about the alignment or
11873  * atomicity of device memory accesses. The recommended practice for writing
11874  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11875  * alt_write_word() functions.
11876  *
11877  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD.
11878  */
11879 struct ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_s
11880 {
11881  uint32_t value : 32; /* Address */
11882 };
11883 
11884 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD. */
11885 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_s ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_t;
11886 #endif /* __ASSEMBLY__ */
11887 
11888 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD register. */
11889 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_RESET 0x00000000
11890 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD register from the beginning of the component. */
11891 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_OFST 0x8
11892 
11893 /*
11894  * Register : Initial Software State Register - romcode_initswstate
11895  *
11896  * Initial Software loaded by the Boot ROM writes the magic value 0x49535756 (ISWV
11897  * in ASCII) to this register when it has reached a valid state.
11898  *
11899  * Reset only on a cold reset.
11900  *
11901  * Register Layout
11902  *
11903  * Bits | Access | Reset | Description
11904  * :-------|:-------|:------|:------------
11905  * [31:0] | RW | 0x0 | Value
11906  *
11907  */
11908 /*
11909  * Field : Value - value
11910  *
11911  * Written with magic value.
11912  *
11913  * Field Enumeration Values:
11914  *
11915  * Enum | Value | Description
11916  * :---------------------------------------------------|:-----------|:------------
11917  * ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 |
11918  * ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 |
11919  *
11920  * Field Access Macros:
11921  *
11922  */
11923 /*
11924  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE
11925  *
11926  */
11927 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
11928 /*
11929  * Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE
11930  *
11931  */
11932 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
11933 
11934 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field. */
11935 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_LSB 0
11936 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field. */
11937 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_MSB 31
11938 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field. */
11939 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
11940 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field value. */
11941 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
11942 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field value. */
11943 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
11944 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field. */
11945 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
11946 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE field value from a register. */
11947 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11948 /* Produces a ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */
11949 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11950 
11951 #ifndef __ASSEMBLY__
11952 /*
11953  * WARNING: The C register and register group struct declarations are provided for
11954  * convenience and illustrative purposes. They should, however, be used with
11955  * caution as the C language standard provides no guarantees about the alignment or
11956  * atomicity of device memory accesses. The recommended practice for writing
11957  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11958  * alt_write_word() functions.
11959  *
11960  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE.
11961  */
11962 struct ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_s
11963 {
11964  uint32_t value : 32; /* Value */
11965 };
11966 
11967 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE. */
11968 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_t;
11969 #endif /* __ASSEMBLY__ */
11970 
11971 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE register. */
11972 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_RESET 0x00000000
11973 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE register from the beginning of the component. */
11974 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_OFST 0xc
11975 
11976 /*
11977  * Register : Initial Software Last Image Loaded Register - romcode_initswlastld
11978  *
11979  * Contains the index of the last Initial Software image loaded by the Boot ROM
11980  * from the boot device.
11981  *
11982  * Reset only on a cold reset.
11983  *
11984  * Register Layout
11985  *
11986  * Bits | Access | Reset | Description
11987  * :-------|:-------|:------|:------------
11988  * [1:0] | RW | 0x0 | Index
11989  * [31:2] | ??? | 0x0 | *UNDEFINED*
11990  *
11991  */
11992 /*
11993  * Field : Index - index
11994  *
11995  * Index of last image loaded.
11996  *
11997  * Field Access Macros:
11998  *
11999  */
12000 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field. */
12001 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_LSB 0
12002 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field. */
12003 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_MSB 1
12004 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field. */
12005 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
12006 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field value. */
12007 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
12008 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field value. */
12009 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
12010 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field. */
12011 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
12012 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX field value from a register. */
12013 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
12014 /* Produces a ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */
12015 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
12016 
12017 #ifndef __ASSEMBLY__
12018 /*
12019  * WARNING: The C register and register group struct declarations are provided for
12020  * convenience and illustrative purposes. They should, however, be used with
12021  * caution as the C language standard provides no guarantees about the alignment or
12022  * atomicity of device memory accesses. The recommended practice for writing
12023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12024  * alt_write_word() functions.
12025  *
12026  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD.
12027  */
12028 struct ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_s
12029 {
12030  uint32_t index : 2; /* Index */
12031  uint32_t : 30; /* *UNDEFINED* */
12032 };
12033 
12034 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD. */
12035 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_t;
12036 #endif /* __ASSEMBLY__ */
12037 
12038 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD register. */
12039 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_RESET 0x00000000
12040 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD register from the beginning of the component. */
12041 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_OFST 0x10
12042 
12043 /*
12044  * Register : Enable Register - warmram_enable
12045  *
12046  * Enables or disables the warm reset from On-chip RAM feature.
12047  *
12048  * Reset only on a cold reset.
12049  *
12050  * Register Layout
12051  *
12052  * Bits | Access | Reset | Description
12053  * :-------|:-------|:------|:----------------------------
12054  * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM
12055  *
12056  */
12057 /*
12058  * Field : Warm Reset from On-chip RAM - magic
12059  *
12060  * Controls whether Boot ROM will attempt to boot from the contents of the On-chip
12061  * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not
12062  * configure boot IOs, the pin mux, or clocks.
12063  *
12064  * Note that the enable value is a 32-bit magic value (provided by the enum).
12065  *
12066  * Field Enumeration Values:
12067  *
12068  * Enum | Value | Description
12069  * :---------------------------------------|:-----------|:------------
12070  * ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_DISD | 0x0 |
12071  * ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_END | 0xae9efebc |
12072  *
12073  * Field Access Macros:
12074  *
12075  */
12076 /*
12077  * Enumerated value for register field ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC
12078  *
12079  */
12080 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_DISD 0x0
12081 /*
12082  * Enumerated value for register field ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC
12083  *
12084  */
12085 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_END 0xae9efebc
12086 
12087 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field. */
12088 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_LSB 0
12089 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field. */
12090 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_MSB 31
12091 /* The width in bits of the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field. */
12092 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_WIDTH 32
12093 /* The mask used to set the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field value. */
12094 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
12095 /* The mask used to clear the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field value. */
12096 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
12097 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field. */
12098 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_RESET 0x0
12099 /* Extracts the ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC field value from a register. */
12100 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
12101 /* Produces a ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC register field value suitable for setting the register. */
12102 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
12103 
12104 #ifndef __ASSEMBLY__
12105 /*
12106  * WARNING: The C register and register group struct declarations are provided for
12107  * convenience and illustrative purposes. They should, however, be used with
12108  * caution as the C language standard provides no guarantees about the alignment or
12109  * atomicity of device memory accesses. The recommended practice for writing
12110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12111  * alt_write_word() functions.
12112  *
12113  * The struct declaration for register ALT_SYSMGR_ROM_WARMRAM_EN.
12114  */
12115 struct ALT_SYSMGR_ROM_WARMRAM_EN_s
12116 {
12117  uint32_t magic : 32; /* Warm Reset from On-chip RAM */
12118 };
12119 
12120 /* The typedef declaration for register ALT_SYSMGR_ROM_WARMRAM_EN. */
12121 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_EN_s ALT_SYSMGR_ROM_WARMRAM_EN_t;
12122 #endif /* __ASSEMBLY__ */
12123 
12124 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_EN register. */
12125 #define ALT_SYSMGR_ROM_WARMRAM_EN_RESET 0x00000000
12126 /* The byte offset of the ALT_SYSMGR_ROM_WARMRAM_EN register from the beginning of the component. */
12127 #define ALT_SYSMGR_ROM_WARMRAM_EN_OFST 0x18
12128 
12129 /*
12130  * Register : Data Start Register - warmram_datastart
12131  *
12132  * Offset into On-chip RAM of the start of the region for CRC validation
12133  *
12134  * Reset only on a cold reset.
12135  *
12136  * Register Layout
12137  *
12138  * Bits | Access | Reset | Description
12139  * :-------|:-------|:------|:------------------
12140  * [31:0] | RW | 0x0 | Data Start Offset
12141  *
12142  */
12143 /*
12144  * Field : Data Start Offset - offset
12145  *
12146  * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM
12147  * region for the warm boot CRC validation. The offset must be an integer multiple
12148  * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to
12149  * 0xFFFF and clear the bottom 2 bits.
12150  *
12151  * Field Access Macros:
12152  *
12153  */
12154 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field. */
12155 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_LSB 0
12156 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field. */
12157 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_MSB 31
12158 /* The width in bits of the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field. */
12159 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_WIDTH 32
12160 /* The mask used to set the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field value. */
12161 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET_MSK 0xffffffff
12162 /* The mask used to clear the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field value. */
12163 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_CLR_MSK 0x00000000
12164 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field. */
12165 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_RESET 0x0
12166 /* Extracts the ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET field value from a register. */
12167 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12168 /* Produces a ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */
12169 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12170 
12171 #ifndef __ASSEMBLY__
12172 /*
12173  * WARNING: The C register and register group struct declarations are provided for
12174  * convenience and illustrative purposes. They should, however, be used with
12175  * caution as the C language standard provides no guarantees about the alignment or
12176  * atomicity of device memory accesses. The recommended practice for writing
12177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12178  * alt_write_word() functions.
12179  *
12180  * The struct declaration for register ALT_SYSMGR_ROM_WARMRAM_DATASTART.
12181  */
12182 struct ALT_SYSMGR_ROM_WARMRAM_DATASTART_s
12183 {
12184  uint32_t offset : 32; /* Data Start Offset */
12185 };
12186 
12187 /* The typedef declaration for register ALT_SYSMGR_ROM_WARMRAM_DATASTART. */
12188 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_DATASTART_s ALT_SYSMGR_ROM_WARMRAM_DATASTART_t;
12189 #endif /* __ASSEMBLY__ */
12190 
12191 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_DATASTART register. */
12192 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_RESET 0x00000000
12193 /* The byte offset of the ALT_SYSMGR_ROM_WARMRAM_DATASTART register from the beginning of the component. */
12194 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFST 0x1c
12195 
12196 /*
12197  * Register : Length Register - warmram_length
12198  *
12199  * Length of region in On-chip RAM for CRC validation.
12200  *
12201  * Reset only on a cold reset.
12202  *
12203  * Register Layout
12204  *
12205  * Bits | Access | Reset | Description
12206  * :-------|:-------|:------|:------------
12207  * [31:0] | RW | 0x0 | Size
12208  *
12209  */
12210 /*
12211  * Field : Size - size
12212  *
12213  * Contains the length (in bytes) of the region in the On-chip RAM for the warm
12214  * boot CRC validation.
12215  *
12216  * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to
12217  * avoid overhead caused by CRC validation.
12218  *
12219  * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot
12220  * ROM won't boot from the On-chip RAM.
12221  *
12222  * The length must be an integer multiple of 4.
12223  *
12224  * The Boot ROM code will clear the top 16 bits and the bottom 2 bits.
12225  *
12226  * Field Access Macros:
12227  *
12228  */
12229 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field. */
12230 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_LSB 0
12231 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field. */
12232 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_MSB 31
12233 /* The width in bits of the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field. */
12234 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_WIDTH 32
12235 /* The mask used to set the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field value. */
12236 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET_MSK 0xffffffff
12237 /* The mask used to clear the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field value. */
12238 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_CLR_MSK 0x00000000
12239 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field. */
12240 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_RESET 0x0
12241 /* Extracts the ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE field value from a register. */
12242 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_GET(value) (((value) & 0xffffffff) >> 0)
12243 /* Produces a ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE register field value suitable for setting the register. */
12244 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0xffffffff)
12245 
12246 #ifndef __ASSEMBLY__
12247 /*
12248  * WARNING: The C register and register group struct declarations are provided for
12249  * convenience and illustrative purposes. They should, however, be used with
12250  * caution as the C language standard provides no guarantees about the alignment or
12251  * atomicity of device memory accesses. The recommended practice for writing
12252  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12253  * alt_write_word() functions.
12254  *
12255  * The struct declaration for register ALT_SYSMGR_ROM_WARMRAM_LEN.
12256  */
12257 struct ALT_SYSMGR_ROM_WARMRAM_LEN_s
12258 {
12259  uint32_t size : 32; /* Size */
12260 };
12261 
12262 /* The typedef declaration for register ALT_SYSMGR_ROM_WARMRAM_LEN. */
12263 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_LEN_s ALT_SYSMGR_ROM_WARMRAM_LEN_t;
12264 #endif /* __ASSEMBLY__ */
12265 
12266 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_LEN register. */
12267 #define ALT_SYSMGR_ROM_WARMRAM_LEN_RESET 0x00000000
12268 /* The byte offset of the ALT_SYSMGR_ROM_WARMRAM_LEN register from the beginning of the component. */
12269 #define ALT_SYSMGR_ROM_WARMRAM_LEN_OFST 0x20
12270 
12271 /*
12272  * Register : Execution Register - warmram_execution
12273  *
12274  * Offset into On-chip RAM to enter to on a warm boot.
12275  *
12276  * Reset only on a cold reset.
12277  *
12278  * Register Layout
12279  *
12280  * Bits | Access | Reset | Description
12281  * :-------|:-------|:------|:-----------------
12282  * [31:0] | RW | 0x0 | Execution Offset
12283  *
12284  */
12285 /*
12286  * Field : Execution Offset - offset
12287  *
12288  * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if
12289  * the CRC validation succeeds.
12290  *
12291  * The Boot ROM code will set the top 16 bits to 0xFFFF.
12292  *
12293  * Field Access Macros:
12294  *
12295  */
12296 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field. */
12297 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_LSB 0
12298 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field. */
12299 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_MSB 31
12300 /* The width in bits of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field. */
12301 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_WIDTH 32
12302 /* The mask used to set the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field value. */
12303 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET_MSK 0xffffffff
12304 /* The mask used to clear the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field value. */
12305 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0x00000000
12306 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field. */
12307 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_RESET 0x0
12308 /* Extracts the ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET field value from a register. */
12309 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12310 /* Produces a ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */
12311 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12312 
12313 #ifndef __ASSEMBLY__
12314 /*
12315  * WARNING: The C register and register group struct declarations are provided for
12316  * convenience and illustrative purposes. They should, however, be used with
12317  * caution as the C language standard provides no guarantees about the alignment or
12318  * atomicity of device memory accesses. The recommended practice for writing
12319  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12320  * alt_write_word() functions.
12321  *
12322  * The struct declaration for register ALT_SYSMGR_ROM_WARMRAM_EXECUTION.
12323  */
12324 struct ALT_SYSMGR_ROM_WARMRAM_EXECUTION_s
12325 {
12326  uint32_t offset : 32; /* Execution Offset */
12327 };
12328 
12329 /* The typedef declaration for register ALT_SYSMGR_ROM_WARMRAM_EXECUTION. */
12330 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_EXECUTION_s ALT_SYSMGR_ROM_WARMRAM_EXECUTION_t;
12331 #endif /* __ASSEMBLY__ */
12332 
12333 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION register. */
12334 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_RESET 0x00000000
12335 /* The byte offset of the ALT_SYSMGR_ROM_WARMRAM_EXECUTION register from the beginning of the component. */
12336 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFST 0x24
12337 
12338 /*
12339  * Register : Expected CRC Register - warmram_crc
12340  *
12341  * Length of region in On-chip RAM for CRC validation.
12342  *
12343  * Reset only on a cold reset.
12344  *
12345  * Register Layout
12346  *
12347  * Bits | Access | Reset | Description
12348  * :-------|:-------|:------|:-------------
12349  * [31:0] | RW | 0x0 | Expected CRC
12350  *
12351  */
12352 /*
12353  * Field : Expected CRC - expected
12354  *
12355  * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code
12356  * calculates the actual CRC for all bytes in the region specified by the DATA
12357  * START an LENGTH registers. The contents of the EXECUTION register (after it has
12358  * been read and modified by the Boot ROM code) is also included in the CRC
12359  * calculation. The contents of the EXECUTION register is added to the CRC
12360  * accumulator a byte at a time starting with the least significant byte. If the
12361  * actual CRC doesn't match the expected CRC value in this register, the Boot ROM
12362  * won't boot from the On-chip RAM.
12363  *
12364  * The CRC is a standard CRC32 with the polynomial:
12365  *
12366  * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 +
12367  * x^2 + x + 1
12368  *
12369  * There is no reflection of the bits and the initial value of the remainder is
12370  * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF.
12371  *
12372  * Field Access Macros:
12373  *
12374  */
12375 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field. */
12376 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_LSB 0
12377 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field. */
12378 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_MSB 31
12379 /* The width in bits of the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field. */
12380 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_WIDTH 32
12381 /* The mask used to set the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field value. */
12382 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
12383 /* The mask used to clear the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field value. */
12384 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
12385 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field. */
12386 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_RESET 0x0
12387 /* Extracts the ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED field value from a register. */
12388 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
12389 /* Produces a ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */
12390 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
12391 
12392 #ifndef __ASSEMBLY__
12393 /*
12394  * WARNING: The C register and register group struct declarations are provided for
12395  * convenience and illustrative purposes. They should, however, be used with
12396  * caution as the C language standard provides no guarantees about the alignment or
12397  * atomicity of device memory accesses. The recommended practice for writing
12398  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12399  * alt_write_word() functions.
12400  *
12401  * The struct declaration for register ALT_SYSMGR_ROM_WARMRAM_CRC.
12402  */
12403 struct ALT_SYSMGR_ROM_WARMRAM_CRC_s
12404 {
12405  uint32_t expected : 32; /* Expected CRC */
12406 };
12407 
12408 /* The typedef declaration for register ALT_SYSMGR_ROM_WARMRAM_CRC. */
12409 typedef volatile struct ALT_SYSMGR_ROM_WARMRAM_CRC_s ALT_SYSMGR_ROM_WARMRAM_CRC_t;
12410 #endif /* __ASSEMBLY__ */
12411 
12412 /* The reset value of the ALT_SYSMGR_ROM_WARMRAM_CRC register. */
12413 #define ALT_SYSMGR_ROM_WARMRAM_CRC_RESET 0x00000000
12414 /* The byte offset of the ALT_SYSMGR_ROM_WARMRAM_CRC register from the beginning of the component. */
12415 #define ALT_SYSMGR_ROM_WARMRAM_CRC_OFST 0x28
12416 
12417 /*
12418  * Register : Preloader to OS Handoff Information - isw_handoff
12419  *
12420  * These registers are used to store handoff infomation between the preloader and
12421  * the OS. These 8 registers can be used to store any information. The contents of
12422  * these registers have no impact on the state of the HPS hardware.
12423  *
12424  * A total of 8 x 32 bit registers for Second State Boot Loader handoff
12425  *
12426  * Reset only on a cold reset.
12427  *
12428  * Register Layout
12429  *
12430  * Bits | Access | Reset | Description
12431  * :-------|:-------|:------|:---------------------------------------
12432  * [31:0] | RW | 0x0 | ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF
12433  *
12434  */
12435 /*
12436  * Field : isw_handoff
12437  *
12438  * Field Access Macros:
12439  *
12440  */
12441 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field. */
12442 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_LSB 0
12443 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field. */
12444 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_MSB 31
12445 /* The width in bits of the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field. */
12446 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_WIDTH 32
12447 /* The mask used to set the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field value. */
12448 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET_MSK 0xffffffff
12449 /* The mask used to clear the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field value. */
12450 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_CLR_MSK 0x00000000
12451 /* The reset value of the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field. */
12452 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_RESET 0x0
12453 /* Extracts the ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF field value from a register. */
12454 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_GET(value) (((value) & 0xffffffff) >> 0)
12455 /* Produces a ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF register field value suitable for setting the register. */
12456 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET(value) (((value) << 0) & 0xffffffff)
12457 
12458 #ifndef __ASSEMBLY__
12459 /*
12460  * WARNING: The C register and register group struct declarations are provided for
12461  * convenience and illustrative purposes. They should, however, be used with
12462  * caution as the C language standard provides no guarantees about the alignment or
12463  * atomicity of device memory accesses. The recommended practice for writing
12464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12465  * alt_write_word() functions.
12466  *
12467  * The struct declaration for register ALT_SYSMGR_ROM_ISW_HANDOFF.
12468  */
12469 struct ALT_SYSMGR_ROM_ISW_HANDOFF_s
12470 {
12471  uint32_t isw_handoff : 32; /* ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF */
12472 };
12473 
12474 /* The typedef declaration for register ALT_SYSMGR_ROM_ISW_HANDOFF. */
12475 typedef volatile struct ALT_SYSMGR_ROM_ISW_HANDOFF_s ALT_SYSMGR_ROM_ISW_HANDOFF_t;
12476 #endif /* __ASSEMBLY__ */
12477 
12478 /* The reset value of the ALT_SYSMGR_ROM_ISW_HANDOFF register. */
12479 #define ALT_SYSMGR_ROM_ISW_HANDOFF_RESET 0x00000000
12480 /* The byte offset of the ALT_SYSMGR_ROM_ISW_HANDOFF register from the beginning of the component. */
12481 #define ALT_SYSMGR_ROM_ISW_HANDOFF_OFST 0x30
12482 
12483 /*
12484  * Register : Preloader to OS Handoff Information - romcode_bootromswstate
12485  *
12486  * general purpose register used by the Boot ROM code. Actual usage is defined in
12487  * the Boot ROM source code.
12488  *
12489  * Reset only on a cold reset.
12490  *
12491  * Register Layout
12492  *
12493  * Bits | Access | Reset | Description
12494  * :-------|:-------|:------|:--------------------------------------------
12495  * [31:0] | RW | 0x0 | ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE
12496  *
12497  */
12498 /*
12499  * Field : value
12500  *
12501  * Field Access Macros:
12502  *
12503  */
12504 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
12505 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
12506 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
12507 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
12508 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
12509 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
12510 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
12511 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
12512 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
12513 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
12514 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
12515 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
12516 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */
12517 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12518 /* Produces a ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */
12519 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12520 
12521 #ifndef __ASSEMBLY__
12522 /*
12523  * WARNING: The C register and register group struct declarations are provided for
12524  * convenience and illustrative purposes. They should, however, be used with
12525  * caution as the C language standard provides no guarantees about the alignment or
12526  * atomicity of device memory accesses. The recommended practice for writing
12527  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12528  * alt_write_word() functions.
12529  *
12530  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE.
12531  */
12532 struct ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_s
12533 {
12534  uint32_t value : 32; /* ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE */
12535 };
12536 
12537 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE. */
12538 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_t;
12539 #endif /* __ASSEMBLY__ */
12540 
12541 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE register. */
12542 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_RESET 0x00000000
12543 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */
12544 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_OFST 0x50
12545 
12546 /*
12547  * Register : romcode_stickyset_warmclr
12548  *
12549  * Write 1 to set each bit.
12550  *
12551  * Write 0 has no effect.
12552  *
12553  * Clears on warm/cold reset. No other way to clear the value once written 1.
12554  *
12555  * Register Layout
12556  *
12557  * Bits | Access | Reset | Description
12558  * :-------|:-------|:------|:-----------------------------------------------
12559  * [31:0] | RW | 0x0 | ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE
12560  *
12561  */
12562 /*
12563  * Field : value
12564  *
12565  * Field Access Macros:
12566  *
12567  */
12568 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field. */
12569 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_LSB 0
12570 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field. */
12571 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_MSB 31
12572 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field. */
12573 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_WIDTH 32
12574 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field value. */
12575 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET_MSK 0xffffffff
12576 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field value. */
12577 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_CLR_MSK 0x00000000
12578 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field. */
12579 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_RESET 0x0
12580 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE field value from a register. */
12581 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12582 /* Produces a ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE register field value suitable for setting the register. */
12583 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12584 
12585 #ifndef __ASSEMBLY__
12586 /*
12587  * WARNING: The C register and register group struct declarations are provided for
12588  * convenience and illustrative purposes. They should, however, be used with
12589  * caution as the C language standard provides no guarantees about the alignment or
12590  * atomicity of device memory accesses. The recommended practice for writing
12591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12592  * alt_write_word() functions.
12593  *
12594  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR.
12595  */
12596 struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_s
12597 {
12598  uint32_t value : 32; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE */
12599 };
12600 
12601 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR. */
12602 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_s ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_t;
12603 #endif /* __ASSEMBLY__ */
12604 
12605 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR register. */
12606 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_RESET 0x00000000
12607 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR register from the beginning of the component. */
12608 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_OFST 0x70
12609 
12610 /*
12611  * Register : romcode_stickyset_coldclr
12612  *
12613  * Write 1 to set each bit.
12614  *
12615  * Write 0 has no effect.
12616  *
12617  * Clears on cold reset. No other way to clear the value once written 1.
12618  *
12619  * Register Layout
12620  *
12621  * Bits | Access | Reset | Description
12622  * :-------|:-------|:------|:-----------------------------------------------
12623  * [31:0] | RW | 0x0 | ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE
12624  *
12625  */
12626 /*
12627  * Field : value
12628  *
12629  * Field Access Macros:
12630  *
12631  */
12632 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field. */
12633 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_LSB 0
12634 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field. */
12635 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_MSB 31
12636 /* The width in bits of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field. */
12637 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_WIDTH 32
12638 /* The mask used to set the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field value. */
12639 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET_MSK 0xffffffff
12640 /* The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field value. */
12641 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_CLR_MSK 0x00000000
12642 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field. */
12643 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_RESET 0x0
12644 /* Extracts the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE field value from a register. */
12645 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12646 /* Produces a ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE register field value suitable for setting the register. */
12647 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12648 
12649 #ifndef __ASSEMBLY__
12650 /*
12651  * WARNING: The C register and register group struct declarations are provided for
12652  * convenience and illustrative purposes. They should, however, be used with
12653  * caution as the C language standard provides no guarantees about the alignment or
12654  * atomicity of device memory accesses. The recommended practice for writing
12655  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12656  * alt_write_word() functions.
12657  *
12658  * The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR.
12659  */
12660 struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_s
12661 {
12662  uint32_t value : 32; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE */
12663 };
12664 
12665 /* The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR. */
12666 typedef volatile struct ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_s ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_t;
12667 #endif /* __ASSEMBLY__ */
12668 
12669 /* The reset value of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR register. */
12670 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_RESET 0x00000000
12671 /* The byte offset of the ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR register from the beginning of the component. */
12672 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_OFST 0x74
12673 
12674 #ifndef __ASSEMBLY__
12675 /*
12676  * WARNING: The C register and register group struct declarations are provided for
12677  * convenience and illustrative purposes. They should, however, be used with
12678  * caution as the C language standard provides no guarantees about the alignment or
12679  * atomicity of device memory accesses. The recommended practice for writing
12680  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12681  * alt_write_word() functions.
12682  *
12683  * The struct declaration for register group ALT_SYSMGR_ROM.
12684  */
12685 struct ALT_SYSMGR_ROM_s
12686 {
12687  ALT_SYSMGR_ROM_ROMHW_CTL_t romhw_ctrl; /* ALT_SYSMGR_ROM_ROMHW_CTL */
12688  ALT_SYSMGR_ROM_ROMCODE_CTL_t romcode_ctrl; /* ALT_SYSMGR_ROM_ROMCODE_CTL */
12689  ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_t romcode_qspi_reset_command; /* ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD */
12690  ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_t romcode_initswstate; /* ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE */
12691  ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_t romcode_initswlastld; /* ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD */
12692  volatile uint32_t _pad_0x14_0x17; /* *UNDEFINED* */
12693  ALT_SYSMGR_ROM_WARMRAM_EN_t warmram_enable; /* ALT_SYSMGR_ROM_WARMRAM_EN */
12694  ALT_SYSMGR_ROM_WARMRAM_DATASTART_t warmram_datastart; /* ALT_SYSMGR_ROM_WARMRAM_DATASTART */
12695  ALT_SYSMGR_ROM_WARMRAM_LEN_t warmram_length; /* ALT_SYSMGR_ROM_WARMRAM_LEN */
12696  ALT_SYSMGR_ROM_WARMRAM_EXECUTION_t warmram_execution; /* ALT_SYSMGR_ROM_WARMRAM_EXECUTION */
12697  ALT_SYSMGR_ROM_WARMRAM_CRC_t warmram_crc; /* ALT_SYSMGR_ROM_WARMRAM_CRC */
12698  volatile uint32_t _pad_0x2c_0x2f; /* *UNDEFINED* */
12699  ALT_SYSMGR_ROM_ISW_HANDOFF_t isw_handoff[8]; /* ALT_SYSMGR_ROM_ISW_HANDOFF */
12700  ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_t romcode_bootromswstate[8]; /* ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE */
12701  ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_t romcode_stickyset_warmclr; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR */
12702  ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_t romcode_stickyset_coldclr; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR */
12703  volatile uint32_t _pad_0x78_0x100[34]; /* *UNDEFINED* */
12704 };
12705 
12706 /* The typedef declaration for register group ALT_SYSMGR_ROM. */
12707 typedef volatile struct ALT_SYSMGR_ROM_s ALT_SYSMGR_ROM_t;
12708 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROM. */
12709 struct ALT_SYSMGR_ROM_raw_s
12710 {
12711  volatile uint32_t romhw_ctrl; /* ALT_SYSMGR_ROM_ROMHW_CTL */
12712  volatile uint32_t romcode_ctrl; /* ALT_SYSMGR_ROM_ROMCODE_CTL */
12713  volatile uint32_t romcode_qspi_reset_command; /* ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD */
12714  volatile uint32_t romcode_initswstate; /* ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE */
12715  volatile uint32_t romcode_initswlastld; /* ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD */
12716  uint32_t _pad_0x14_0x17; /* *UNDEFINED* */
12717  volatile uint32_t warmram_enable; /* ALT_SYSMGR_ROM_WARMRAM_EN */
12718  volatile uint32_t warmram_datastart; /* ALT_SYSMGR_ROM_WARMRAM_DATASTART */
12719  volatile uint32_t warmram_length; /* ALT_SYSMGR_ROM_WARMRAM_LEN */
12720  volatile uint32_t warmram_execution; /* ALT_SYSMGR_ROM_WARMRAM_EXECUTION */
12721  volatile uint32_t warmram_crc; /* ALT_SYSMGR_ROM_WARMRAM_CRC */
12722  uint32_t _pad_0x2c_0x2f; /* *UNDEFINED* */
12723  volatile uint32_t isw_handoff[8]; /* ALT_SYSMGR_ROM_ISW_HANDOFF */
12724  volatile uint32_t romcode_bootromswstate[8]; /* ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE */
12725  volatile uint32_t romcode_stickyset_warmclr; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR */
12726  volatile uint32_t romcode_stickyset_coldclr; /* ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR */
12727  uint32_t _pad_0x78_0x100[34]; /* *UNDEFINED* */
12728 };
12729 
12730 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROM. */
12731 typedef volatile struct ALT_SYSMGR_ROM_raw_s ALT_SYSMGR_ROM_raw_t;
12732 #endif /* __ASSEMBLY__ */
12733 
12734 
12735 #ifdef __cplusplus
12736 }
12737 #endif /* __cplusplus */
12738 #endif /* __ALT_SOCAL_SYSMGR_H__ */
12739