Hardware Libraries  20.1
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alt_sdmmc.h
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32 
33 /* Altera - ALT_SDMMC */
34 
35 #ifndef __ALT_SOCAL_SDMMC_H__
36 #define __ALT_SOCAL_SDMMC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SDMMC
50  * Block
51  *
52  */
53 /*
54  * Register : Control Register - CTRL
55  *
56  * Control register
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :--------|:-------|:------|:---------------------------------------------
62  * [0] | RW | 0x0 | ALT_SDMMC_CTRL_CONTROLLER_RESET
63  * [1] | RW | 0x0 | ALT_SDMMC_CTRL_FIFO_RESET
64  * [2] | RW | 0x0 | ALT_SDMMC_CTRL_DMA_RESET
65  * [3] | ??? | 0x0 | *UNDEFINED*
66  * [4] | RW | 0x0 | ALT_SDMMC_CTRL_INT_ENABLE
67  * [5] | RW | 0x0 | ALT_SDMMC_CTRL_DMA_ENABLE
68  * [6] | RW | 0x0 | ALT_SDMMC_CTRL_READ_WAIT
69  * [7] | RW | 0x0 | ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE
70  * [8] | RW | 0x0 | ALT_SDMMC_CTRL_ABORT_READ_DATA
71  * [9] | RW | 0x0 | ALT_SDMMC_CTRL_SEND_CCSD
72  * [10] | RW | 0x0 | ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD
73  * [11] | RW | 0x0 | ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS
74  * [15:12] | ??? | 0x0 | *UNDEFINED*
75  * [19:16] | RW | 0x0 | ALT_SDMMC_CTRL_CARD_VOLTAGE_A
76  * [23:20] | RW | 0x0 | ALT_SDMMC_CTRL_CARD_VOLTAGE_B
77  * [24] | RW | 0x0 | ALT_SDMMC_CTRL_ENABLE_OD_PULLUP
78  * [25] | RW | 0x0 | ALT_SDMMC_CTRL_USE_INTERNAL_DMAC
79  * [31:26] | ??? | 0x0 | *UNDEFINED*
80  *
81  */
82 /*
83  * Field : CONTROLLER_RESET
84  *
85  * 0-No change
86  *
87  * 1-Reset DWC_mobile_storage controller
88  *
89  * To reset controller, firmware should set bit to 1. This bit is auto-cleared
90  * after two AHB and two cclk_in clock cycles.
91  *
92  * This resets:
93  *
94  * * BIU/CIU interface
95  *
96  * * CIU and state machines
97  *
98  * * abort_read_data, send_irq_response, and read_wait bits of Control register
99  *
100  * * start_cmd bit of Command register
101  *
102  * Does not affect any registers or DMA interface, or FIFO or host
103  *
104  * interrupts
105  *
106  * Field Enumeration Values:
107  *
108  * Enum | Value | Description
109  * :-----------------------------------------------|:------|:------------------------------------
110  * ALT_SDMMC_CTRL_CONTROLLER_RESET_E_NO_CHANGE | 0x0 | No change
111  * ALT_SDMMC_CTRL_CONTROLLER_RESET_E_ASSERT_RESET | 0x1 | Reset DWC_mobile_storage controller
112  *
113  * Field Access Macros:
114  *
115  */
116 /*
117  * Enumerated value for register field ALT_SDMMC_CTRL_CONTROLLER_RESET
118  *
119  * No change
120  */
121 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_E_NO_CHANGE 0x0
122 /*
123  * Enumerated value for register field ALT_SDMMC_CTRL_CONTROLLER_RESET
124  *
125  * Reset DWC_mobile_storage controller
126  */
127 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_E_ASSERT_RESET 0x1
128 
129 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_CONTROLLER_RESET register field. */
130 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_LSB 0
131 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_CONTROLLER_RESET register field. */
132 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_MSB 0
133 /* The width in bits of the ALT_SDMMC_CTRL_CONTROLLER_RESET register field. */
134 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_WIDTH 1
135 /* The mask used to set the ALT_SDMMC_CTRL_CONTROLLER_RESET register field value. */
136 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_SET_MSK 0x00000001
137 /* The mask used to clear the ALT_SDMMC_CTRL_CONTROLLER_RESET register field value. */
138 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_CLR_MSK 0xfffffffe
139 /* The reset value of the ALT_SDMMC_CTRL_CONTROLLER_RESET register field. */
140 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_RESET 0x0
141 /* Extracts the ALT_SDMMC_CTRL_CONTROLLER_RESET field value from a register. */
142 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_GET(value) (((value) & 0x00000001) >> 0)
143 /* Produces a ALT_SDMMC_CTRL_CONTROLLER_RESET register field value suitable for setting the register. */
144 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_SET(value) (((value) << 0) & 0x00000001)
145 
146 /*
147  * Field : FIFO_RESET
148  *
149  * 0-No change
150  *
151  * 1-Reset to data FIFO To reset FIFO pointers
152  *
153  * To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
154  * completion of reset operation.
155  *
156  * Field Enumeration Values:
157  *
158  * Enum | Value | Description
159  * :-----------------------------------------|:------|:-----------------------------------------
160  * ALT_SDMMC_CTRL_FIFO_RESET_E_NO_CHANGE | 0x0 | No change
161  * ALT_SDMMC_CTRL_FIFO_RESET_E_ASSERT_RESET | 0x1 | Reset to data FIFO To reset FIFO pointer
162  *
163  * Field Access Macros:
164  *
165  */
166 /*
167  * Enumerated value for register field ALT_SDMMC_CTRL_FIFO_RESET
168  *
169  * No change
170  */
171 #define ALT_SDMMC_CTRL_FIFO_RESET_E_NO_CHANGE 0x0
172 /*
173  * Enumerated value for register field ALT_SDMMC_CTRL_FIFO_RESET
174  *
175  * Reset to data FIFO To reset FIFO pointer
176  */
177 #define ALT_SDMMC_CTRL_FIFO_RESET_E_ASSERT_RESET 0x1
178 
179 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_FIFO_RESET register field. */
180 #define ALT_SDMMC_CTRL_FIFO_RESET_LSB 1
181 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_FIFO_RESET register field. */
182 #define ALT_SDMMC_CTRL_FIFO_RESET_MSB 1
183 /* The width in bits of the ALT_SDMMC_CTRL_FIFO_RESET register field. */
184 #define ALT_SDMMC_CTRL_FIFO_RESET_WIDTH 1
185 /* The mask used to set the ALT_SDMMC_CTRL_FIFO_RESET register field value. */
186 #define ALT_SDMMC_CTRL_FIFO_RESET_SET_MSK 0x00000002
187 /* The mask used to clear the ALT_SDMMC_CTRL_FIFO_RESET register field value. */
188 #define ALT_SDMMC_CTRL_FIFO_RESET_CLR_MSK 0xfffffffd
189 /* The reset value of the ALT_SDMMC_CTRL_FIFO_RESET register field. */
190 #define ALT_SDMMC_CTRL_FIFO_RESET_RESET 0x0
191 /* Extracts the ALT_SDMMC_CTRL_FIFO_RESET field value from a register. */
192 #define ALT_SDMMC_CTRL_FIFO_RESET_GET(value) (((value) & 0x00000002) >> 1)
193 /* Produces a ALT_SDMMC_CTRL_FIFO_RESET register field value suitable for setting the register. */
194 #define ALT_SDMMC_CTRL_FIFO_RESET_SET(value) (((value) << 1) & 0x00000002)
195 
196 /*
197  * Field : DMA_RESET
198  *
199  * 0-No change
200  *
201  * 1-Reset internal DMA interface control logic
202  *
203  * To reset DMA interface, firmware should set bit to 1. This bit is
204  *
205  * auto-cleared after two AHB clocks.
206  *
207  * Field Enumeration Values:
208  *
209  * Enum | Value | Description
210  * :----------------------------------------|:------|:-------------------------------------------
211  * ALT_SDMMC_CTRL_DMA_RESET_E_NO_CHANGE | 0x0 | No change
212  * ALT_SDMMC_CTRL_DMA_RESET_E_ASSERT_RESET | 0x1 | Reset internal DMA interface control logic
213  *
214  * Field Access Macros:
215  *
216  */
217 /*
218  * Enumerated value for register field ALT_SDMMC_CTRL_DMA_RESET
219  *
220  * No change
221  */
222 #define ALT_SDMMC_CTRL_DMA_RESET_E_NO_CHANGE 0x0
223 /*
224  * Enumerated value for register field ALT_SDMMC_CTRL_DMA_RESET
225  *
226  * Reset internal DMA interface control logic
227  */
228 #define ALT_SDMMC_CTRL_DMA_RESET_E_ASSERT_RESET 0x1
229 
230 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_DMA_RESET register field. */
231 #define ALT_SDMMC_CTRL_DMA_RESET_LSB 2
232 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_DMA_RESET register field. */
233 #define ALT_SDMMC_CTRL_DMA_RESET_MSB 2
234 /* The width in bits of the ALT_SDMMC_CTRL_DMA_RESET register field. */
235 #define ALT_SDMMC_CTRL_DMA_RESET_WIDTH 1
236 /* The mask used to set the ALT_SDMMC_CTRL_DMA_RESET register field value. */
237 #define ALT_SDMMC_CTRL_DMA_RESET_SET_MSK 0x00000004
238 /* The mask used to clear the ALT_SDMMC_CTRL_DMA_RESET register field value. */
239 #define ALT_SDMMC_CTRL_DMA_RESET_CLR_MSK 0xfffffffb
240 /* The reset value of the ALT_SDMMC_CTRL_DMA_RESET register field. */
241 #define ALT_SDMMC_CTRL_DMA_RESET_RESET 0x0
242 /* Extracts the ALT_SDMMC_CTRL_DMA_RESET field value from a register. */
243 #define ALT_SDMMC_CTRL_DMA_RESET_GET(value) (((value) & 0x00000004) >> 2)
244 /* Produces a ALT_SDMMC_CTRL_DMA_RESET register field value suitable for setting the register. */
245 #define ALT_SDMMC_CTRL_DMA_RESET_SET(value) (((value) << 2) & 0x00000004)
246 
247 /*
248  * Field : INT_ENABLE
249  *
250  * Global interrupt enable/disable bit:
251  *
252  * 0-Disable interrupts
253  *
254  * 1-Enable interrupts
255  *
256  * The int port is 1 only when this bit is 1 and one or more unmasked
257  *
258  * interrupts are set.
259  *
260  * Field Enumeration Values:
261  *
262  * Enum | Value | Description
263  * :-------------------------------------|:------|:-------------------
264  * ALT_SDMMC_CTRL_INT_ENABLE_E_DISABLED | 0x0 | Disable interrupts
265  * ALT_SDMMC_CTRL_INT_ENABLE_E_ENABLED | 0x1 | Enable interrupts
266  *
267  * Field Access Macros:
268  *
269  */
270 /*
271  * Enumerated value for register field ALT_SDMMC_CTRL_INT_ENABLE
272  *
273  * Disable interrupts
274  */
275 #define ALT_SDMMC_CTRL_INT_ENABLE_E_DISABLED 0x0
276 /*
277  * Enumerated value for register field ALT_SDMMC_CTRL_INT_ENABLE
278  *
279  * Enable interrupts
280  */
281 #define ALT_SDMMC_CTRL_INT_ENABLE_E_ENABLED 0x1
282 
283 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_INT_ENABLE register field. */
284 #define ALT_SDMMC_CTRL_INT_ENABLE_LSB 4
285 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_INT_ENABLE register field. */
286 #define ALT_SDMMC_CTRL_INT_ENABLE_MSB 4
287 /* The width in bits of the ALT_SDMMC_CTRL_INT_ENABLE register field. */
288 #define ALT_SDMMC_CTRL_INT_ENABLE_WIDTH 1
289 /* The mask used to set the ALT_SDMMC_CTRL_INT_ENABLE register field value. */
290 #define ALT_SDMMC_CTRL_INT_ENABLE_SET_MSK 0x00000010
291 /* The mask used to clear the ALT_SDMMC_CTRL_INT_ENABLE register field value. */
292 #define ALT_SDMMC_CTRL_INT_ENABLE_CLR_MSK 0xffffffef
293 /* The reset value of the ALT_SDMMC_CTRL_INT_ENABLE register field. */
294 #define ALT_SDMMC_CTRL_INT_ENABLE_RESET 0x0
295 /* Extracts the ALT_SDMMC_CTRL_INT_ENABLE field value from a register. */
296 #define ALT_SDMMC_CTRL_INT_ENABLE_GET(value) (((value) & 0x00000010) >> 4)
297 /* Produces a ALT_SDMMC_CTRL_INT_ENABLE register field value suitable for setting the register. */
298 #define ALT_SDMMC_CTRL_INT_ENABLE_SET(value) (((value) << 4) & 0x00000010)
299 
300 /*
301  * Field : DMA_ENABLE
302  *
303  * 0-Disable DMA transfer mode
304  *
305  * 1-Enable DMA transfer mode
306  *
307  * Valid only if DWC_mobile_storage configured for External DMA interface.
308  *
309  * Field Enumeration Values:
310  *
311  * Enum | Value | Description
312  * :-------------------------------------|:------|:--------------------------
313  * ALT_SDMMC_CTRL_DMA_ENABLE_E_DISABLED | 0x0 | Disable DMA transfer mode
314  * ALT_SDMMC_CTRL_DMA_ENABLE_E_ENABLED | 0x1 | Enable DMA transfer mode
315  *
316  * Field Access Macros:
317  *
318  */
319 /*
320  * Enumerated value for register field ALT_SDMMC_CTRL_DMA_ENABLE
321  *
322  * Disable DMA transfer mode
323  */
324 #define ALT_SDMMC_CTRL_DMA_ENABLE_E_DISABLED 0x0
325 /*
326  * Enumerated value for register field ALT_SDMMC_CTRL_DMA_ENABLE
327  *
328  * Enable DMA transfer mode
329  */
330 #define ALT_SDMMC_CTRL_DMA_ENABLE_E_ENABLED 0x1
331 
332 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_DMA_ENABLE register field. */
333 #define ALT_SDMMC_CTRL_DMA_ENABLE_LSB 5
334 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_DMA_ENABLE register field. */
335 #define ALT_SDMMC_CTRL_DMA_ENABLE_MSB 5
336 /* The width in bits of the ALT_SDMMC_CTRL_DMA_ENABLE register field. */
337 #define ALT_SDMMC_CTRL_DMA_ENABLE_WIDTH 1
338 /* The mask used to set the ALT_SDMMC_CTRL_DMA_ENABLE register field value. */
339 #define ALT_SDMMC_CTRL_DMA_ENABLE_SET_MSK 0x00000020
340 /* The mask used to clear the ALT_SDMMC_CTRL_DMA_ENABLE register field value. */
341 #define ALT_SDMMC_CTRL_DMA_ENABLE_CLR_MSK 0xffffffdf
342 /* The reset value of the ALT_SDMMC_CTRL_DMA_ENABLE register field. */
343 #define ALT_SDMMC_CTRL_DMA_ENABLE_RESET 0x0
344 /* Extracts the ALT_SDMMC_CTRL_DMA_ENABLE field value from a register. */
345 #define ALT_SDMMC_CTRL_DMA_ENABLE_GET(value) (((value) & 0x00000020) >> 5)
346 /* Produces a ALT_SDMMC_CTRL_DMA_ENABLE register field value suitable for setting the register. */
347 #define ALT_SDMMC_CTRL_DMA_ENABLE_SET(value) (((value) << 5) & 0x00000020)
348 
349 /*
350  * Field : READ_WAIT
351  *
352  * 0-Clear read wait
353  *
354  * 1-Assert read wait
355  *
356  * For sending read-wait to SDIO cards.
357  *
358  * Field Enumeration Values:
359  *
360  * Enum | Value | Description
361  * :----------------------------------|:------|:-----------------
362  * ALT_SDMMC_CTRL_READ_WAIT_E_CLEAR | 0x0 | Clear read wait
363  * ALT_SDMMC_CTRL_READ_WAIT_E_ASSERT | 0x1 | Assert read wait
364  *
365  * Field Access Macros:
366  *
367  */
368 /*
369  * Enumerated value for register field ALT_SDMMC_CTRL_READ_WAIT
370  *
371  * Clear read wait
372  */
373 #define ALT_SDMMC_CTRL_READ_WAIT_E_CLEAR 0x0
374 /*
375  * Enumerated value for register field ALT_SDMMC_CTRL_READ_WAIT
376  *
377  * Assert read wait
378  */
379 #define ALT_SDMMC_CTRL_READ_WAIT_E_ASSERT 0x1
380 
381 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_READ_WAIT register field. */
382 #define ALT_SDMMC_CTRL_READ_WAIT_LSB 6
383 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_READ_WAIT register field. */
384 #define ALT_SDMMC_CTRL_READ_WAIT_MSB 6
385 /* The width in bits of the ALT_SDMMC_CTRL_READ_WAIT register field. */
386 #define ALT_SDMMC_CTRL_READ_WAIT_WIDTH 1
387 /* The mask used to set the ALT_SDMMC_CTRL_READ_WAIT register field value. */
388 #define ALT_SDMMC_CTRL_READ_WAIT_SET_MSK 0x00000040
389 /* The mask used to clear the ALT_SDMMC_CTRL_READ_WAIT register field value. */
390 #define ALT_SDMMC_CTRL_READ_WAIT_CLR_MSK 0xffffffbf
391 /* The reset value of the ALT_SDMMC_CTRL_READ_WAIT register field. */
392 #define ALT_SDMMC_CTRL_READ_WAIT_RESET 0x0
393 /* Extracts the ALT_SDMMC_CTRL_READ_WAIT field value from a register. */
394 #define ALT_SDMMC_CTRL_READ_WAIT_GET(value) (((value) & 0x00000040) >> 6)
395 /* Produces a ALT_SDMMC_CTRL_READ_WAIT register field value suitable for setting the register. */
396 #define ALT_SDMMC_CTRL_READ_WAIT_SET(value) (((value) << 6) & 0x00000040)
397 
398 /*
399  * Field : SEND_IRQ_RESPONSE
400  *
401  * 0-No Change in this
402  *
403  * 1-Send auto IRQ response
404  *
405  * Bit automatically clears once response is sent.
406  *
407  * To wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits
408  * for interrupt response from MMC card(s). In meantime, if host wants
409  * DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at
410  * which time DWC_mobile_storage command state-machine sends CMD40 response on bus
411  * and returns to idle state.
412  *
413  * Field Enumeration Values:
414  *
415  * Enum | Value | Description
416  * :-----------------------------------------|:------|:-----------------------
417  * ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_FALSE | 0x0 | No change
418  * ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_TRUE | 0x1 | Send auto IRQ response
419  *
420  * Field Access Macros:
421  *
422  */
423 /*
424  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE
425  *
426  * No change
427  */
428 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_FALSE 0x0
429 /*
430  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE
431  *
432  * Send auto IRQ response
433  */
434 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_TRUE 0x1
435 
436 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field. */
437 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_LSB 7
438 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field. */
439 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_MSB 7
440 /* The width in bits of the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field. */
441 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_WIDTH 1
442 /* The mask used to set the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field value. */
443 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
444 /* The mask used to clear the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field value. */
445 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
446 /* The reset value of the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field. */
447 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_RESET 0x0
448 /* Extracts the ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE field value from a register. */
449 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
450 /* Produces a ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE register field value suitable for setting the register. */
451 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
452 
453 /*
454  * Field : ABORT_READ_DATA
455  *
456  * 0-No change
457  *
458  * 1-After suspend command is issued during read-transfer, software
459  *
460  * polls card to find when suspend happened. Once suspend occurs,software sets bit
461  * to reset data state-machine, which is waiting for next block of data. Bit
462  * automatically clears once data statemachine resets to idle.
463  *
464  * Used in SDIO card suspend sequence.
465  *
466  * Field Enumeration Values:
467  *
468  * Enum | Value | Description
469  * :---------------------------------------|:------|:-------------------------
470  * ALT_SDMMC_CTRL_ABORT_READ_DATA_E_FALSE | 0x0 | No change
471  * ALT_SDMMC_CTRL_ABORT_READ_DATA_E_TRUE | 0x1 | Reset data state-machine
472  *
473  * Field Access Macros:
474  *
475  */
476 /*
477  * Enumerated value for register field ALT_SDMMC_CTRL_ABORT_READ_DATA
478  *
479  * No change
480  */
481 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_E_FALSE 0x0
482 /*
483  * Enumerated value for register field ALT_SDMMC_CTRL_ABORT_READ_DATA
484  *
485  * Reset data state-machine
486  */
487 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_E_TRUE 0x1
488 
489 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_ABORT_READ_DATA register field. */
490 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_LSB 8
491 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_ABORT_READ_DATA register field. */
492 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_MSB 8
493 /* The width in bits of the ALT_SDMMC_CTRL_ABORT_READ_DATA register field. */
494 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_WIDTH 1
495 /* The mask used to set the ALT_SDMMC_CTRL_ABORT_READ_DATA register field value. */
496 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_SET_MSK 0x00000100
497 /* The mask used to clear the ALT_SDMMC_CTRL_ABORT_READ_DATA register field value. */
498 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_CLR_MSK 0xfffffeff
499 /* The reset value of the ALT_SDMMC_CTRL_ABORT_READ_DATA register field. */
500 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_RESET 0x0
501 /* Extracts the ALT_SDMMC_CTRL_ABORT_READ_DATA field value from a register. */
502 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_GET(value) (((value) & 0x00000100) >> 8)
503 /* Produces a ALT_SDMMC_CTRL_ABORT_READ_DATA register field value suitable for setting the register. */
504 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_SET(value) (((value) << 8) & 0x00000100)
505 
506 /*
507  * Field : SEND_CCSD
508  *
509  * 0-Clear this bit if DWC_mobile_storage does not reset the bit
510  *
511  * 1-Send Command Completion Signal Disable (CCSD) to CE-ATA
512  *
513  * device
514  *
515  * Field Enumeration Values:
516  *
517  * Enum | Value | Description
518  * :-----------------------------------|:------|:-------------------------------------------------
519  * ALT_SDMMC_CTRL_SEND_CCSD_E_CLEAR | 0x0 | Clear bit if DWC_mobile_storage does not reset
520  * : | | the bit
521  * ALT_SDMMC_CTRL_SEND_CCSD_E_ENABLED | 0x1 | Send Command Completion Signal Disable (CCSD) to
522  * : | | CE-ATA device
523  *
524  * Field Access Macros:
525  *
526  */
527 /*
528  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_CCSD
529  *
530  * Clear bit if DWC_mobile_storage does not reset the bit
531  */
532 #define ALT_SDMMC_CTRL_SEND_CCSD_E_CLEAR 0x0
533 /*
534  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_CCSD
535  *
536  * Send Command Completion Signal Disable (CCSD) to CE-ATA
537  *
538  * device
539  */
540 #define ALT_SDMMC_CTRL_SEND_CCSD_E_ENABLED 0x1
541 
542 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_SEND_CCSD register field. */
543 #define ALT_SDMMC_CTRL_SEND_CCSD_LSB 9
544 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_SEND_CCSD register field. */
545 #define ALT_SDMMC_CTRL_SEND_CCSD_MSB 9
546 /* The width in bits of the ALT_SDMMC_CTRL_SEND_CCSD register field. */
547 #define ALT_SDMMC_CTRL_SEND_CCSD_WIDTH 1
548 /* The mask used to set the ALT_SDMMC_CTRL_SEND_CCSD register field value. */
549 #define ALT_SDMMC_CTRL_SEND_CCSD_SET_MSK 0x00000200
550 /* The mask used to clear the ALT_SDMMC_CTRL_SEND_CCSD register field value. */
551 #define ALT_SDMMC_CTRL_SEND_CCSD_CLR_MSK 0xfffffdff
552 /* The reset value of the ALT_SDMMC_CTRL_SEND_CCSD register field. */
553 #define ALT_SDMMC_CTRL_SEND_CCSD_RESET 0x0
554 /* Extracts the ALT_SDMMC_CTRL_SEND_CCSD field value from a register. */
555 #define ALT_SDMMC_CTRL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
556 /* Produces a ALT_SDMMC_CTRL_SEND_CCSD register field value suitable for setting the register. */
557 #define ALT_SDMMC_CTRL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
558 
559 /*
560  * Field : SEND_AUTO_STOP_CCSD
561  *
562  * 0-Clear bit if DWC_mobile_storage does not reset the bit
563  *
564  * 1-Send internally generated STOP after sending CCSD to
565  *
566  * CE-ATA device
567  *
568  * Field Enumeration Values:
569  *
570  * Enum | Value | Description
571  * :---------------------------------------------|:------|:-----------------------------------------------
572  * ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_CLEAR | 0x0 | Clear bit if DWC_mobile_storage does not reset
573  * : | | the bit
574  * ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_ENABLED | 0x1 | Send internally generated STOP after sending
575  * : | | CCSD to CE-ATA device
576  *
577  * Field Access Macros:
578  *
579  */
580 /*
581  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD
582  *
583  * Clear bit if DWC_mobile_storage does not reset the bit
584  */
585 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_CLEAR 0x0
586 /*
587  * Enumerated value for register field ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD
588  *
589  * Send internally generated STOP after sending CCSD to
590  *
591  * CE-ATA device
592  */
593 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_ENABLED 0x1
594 
595 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field. */
596 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_LSB 10
597 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field. */
598 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_MSB 10
599 /* The width in bits of the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field. */
600 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_WIDTH 1
601 /* The mask used to set the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field value. */
602 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
603 /* The mask used to clear the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field value. */
604 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
605 /* The reset value of the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field. */
606 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_RESET 0x0
607 /* Extracts the ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD field value from a register. */
608 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
609 /* Produces a ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register. */
610 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
611 
612 /*
613  * Field : CEATA_DEVICE_INTERRUPT_STATUS
614  *
615  * 0-Interrupts not enabled in CE-ATA device
616  *
617  * 1-Interrupts are enabled in CE-ATA device
618  *
619  * Field Enumeration Values:
620  *
621  * Enum | Value | Description
622  * :--------------------------------------------------------|:------|:----------------------------------------
623  * ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_DISABLED | 0x0 | Interrupts not enabled in CE-ATA device
624  * ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_ENABLED | 0x1 | Interrupts are enabled in CE-ATA device
625  *
626  * Field Access Macros:
627  *
628  */
629 /*
630  * Enumerated value for register field ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS
631  *
632  * Interrupts not enabled in CE-ATA device
633  */
634 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_DISABLED 0x0
635 /*
636  * Enumerated value for register field ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS
637  *
638  * Interrupts are enabled in CE-ATA device
639  */
640 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_ENABLED 0x1
641 
642 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field. */
643 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_LSB 11
644 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field. */
645 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MSB 11
646 /* The width in bits of the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field. */
647 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_WIDTH 1
648 /* The mask used to set the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field value. */
649 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SET_MSK 0x00000800
650 /* The mask used to clear the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field value. */
651 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_CLR_MSK 0xfffff7ff
652 /* The reset value of the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field. */
653 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_RESET 0x0
654 /* Extracts the ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS field value from a register. */
655 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_GET(value) (((value) & 0x00000800) >> 11)
656 /* Produces a ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS register field value suitable for setting the register. */
657 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SET(value) (((value) << 11) & 0x00000800)
658 
659 /*
660  * Field : CARD_VOLTAGE_A
661  *
662  * Card regulator-A voltage setting; output to card_volt_a port.
663  *
664  * Optional feature; ports can be used as general-purpose outputs
665  *
666  * Field Access Macros:
667  *
668  */
669 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field. */
670 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_LSB 16
671 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field. */
672 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_MSB 19
673 /* The width in bits of the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field. */
674 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_WIDTH 4
675 /* The mask used to set the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field value. */
676 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_SET_MSK 0x000f0000
677 /* The mask used to clear the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field value. */
678 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff
679 /* The reset value of the ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field. */
680 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_RESET 0x0
681 /* Extracts the ALT_SDMMC_CTRL_CARD_VOLTAGE_A field value from a register. */
682 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16)
683 /* Produces a ALT_SDMMC_CTRL_CARD_VOLTAGE_A register field value suitable for setting the register. */
684 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000)
685 
686 /*
687  * Field : CARD_VOLTAGE_B
688  *
689  * Card regulator-B voltage setting; output to card_volt_b port.
690  *
691  * Optional feature; ports can be used as general-purpose outputs
692  *
693  * Field Access Macros:
694  *
695  */
696 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field. */
697 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_LSB 20
698 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field. */
699 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_MSB 23
700 /* The width in bits of the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field. */
701 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_WIDTH 4
702 /* The mask used to set the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field value. */
703 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_SET_MSK 0x00f00000
704 /* The mask used to clear the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field value. */
705 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff
706 /* The reset value of the ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field. */
707 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_RESET 0x0
708 /* Extracts the ALT_SDMMC_CTRL_CARD_VOLTAGE_B field value from a register. */
709 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20)
710 /* Produces a ALT_SDMMC_CTRL_CARD_VOLTAGE_B register field value suitable for setting the register. */
711 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000)
712 
713 /*
714  * Field : ENABLE_OD_PULLUP
715  *
716  * External open-drain pullup
717  *
718  * 0-Disable
719  *
720  * 1-Enable
721  *
722  * Inverted value of this bit is output to ccmd_od_pullup_en_n port.
723  *
724  * When bit is set, command output always driven in open-drive mode; that is,
725  * DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1.
726  *
727  * Field Enumeration Values:
728  *
729  * Enum | Value | Description
730  * :-------------------------------------------|:------|:------------
731  * ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_DISABLED | 0x0 | Disable
732  * ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_ENABLED | 0x1 | Enable
733  *
734  * Field Access Macros:
735  *
736  */
737 /*
738  * Enumerated value for register field ALT_SDMMC_CTRL_ENABLE_OD_PULLUP
739  *
740  * Disable
741  */
742 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_DISABLED 0x0
743 /*
744  * Enumerated value for register field ALT_SDMMC_CTRL_ENABLE_OD_PULLUP
745  *
746  * Enable
747  */
748 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_ENABLED 0x1
749 
750 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field. */
751 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_LSB 24
752 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field. */
753 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_MSB 24
754 /* The width in bits of the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field. */
755 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_WIDTH 1
756 /* The mask used to set the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field value. */
757 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_SET_MSK 0x01000000
758 /* The mask used to clear the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field value. */
759 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_CLR_MSK 0xfeffffff
760 /* The reset value of the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field. */
761 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_RESET 0x0
762 /* Extracts the ALT_SDMMC_CTRL_ENABLE_OD_PULLUP field value from a register. */
763 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24)
764 /* Produces a ALT_SDMMC_CTRL_ENABLE_OD_PULLUP register field value suitable for setting the register. */
765 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000)
766 
767 /*
768  * Field : USE_INTERNAL_DMAC
769  *
770  * Present only for the Internal DMAC configuration; else, it is reserved.
771  *
772  * 0-The host performs data transfers through the slave interface
773  *
774  * 1-Internal DMAC used for data transfer
775  *
776  * Field Enumeration Values:
777  *
778  * Enum | Value | Description
779  * :--------------------------------------------|:------|:---------------------------------------------
780  * ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_DISABLED | 0x0 | The host performs data transfers through the
781  * : | | slave interface
782  * ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_ENABLED | 0x1 | Internal DMAC used for data transfer
783  *
784  * Field Access Macros:
785  *
786  */
787 /*
788  * Enumerated value for register field ALT_SDMMC_CTRL_USE_INTERNAL_DMAC
789  *
790  * The host performs data transfers through the slave interface
791  */
792 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_DISABLED 0x0
793 /*
794  * Enumerated value for register field ALT_SDMMC_CTRL_USE_INTERNAL_DMAC
795  *
796  * Internal DMAC used for data transfer
797  */
798 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_ENABLED 0x1
799 
800 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field. */
801 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_LSB 25
802 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field. */
803 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_MSB 25
804 /* The width in bits of the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field. */
805 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_WIDTH 1
806 /* The mask used to set the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field value. */
807 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
808 /* The mask used to clear the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field value. */
809 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
810 /* The reset value of the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field. */
811 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_RESET 0x0
812 /* Extracts the ALT_SDMMC_CTRL_USE_INTERNAL_DMAC field value from a register. */
813 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
814 /* Produces a ALT_SDMMC_CTRL_USE_INTERNAL_DMAC register field value suitable for setting the register. */
815 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
816 
817 #ifndef __ASSEMBLY__
818 /*
819  * WARNING: The C register and register group struct declarations are provided for
820  * convenience and illustrative purposes. They should, however, be used with
821  * caution as the C language standard provides no guarantees about the alignment or
822  * atomicity of device memory accesses. The recommended practice for coding device
823  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
824  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
825  * alt_write_dword() functions for 64 bit registers.
826  *
827  * The struct declaration for register ALT_SDMMC_CTRL.
828  */
829 struct ALT_SDMMC_CTRL_s
830 {
831  volatile uint32_t CONTROLLER_RESET : 1; /* ALT_SDMMC_CTRL_CONTROLLER_RESET */
832  volatile uint32_t FIFO_RESET : 1; /* ALT_SDMMC_CTRL_FIFO_RESET */
833  volatile uint32_t DMA_RESET : 1; /* ALT_SDMMC_CTRL_DMA_RESET */
834  uint32_t : 1; /* *UNDEFINED* */
835  volatile uint32_t INT_ENABLE : 1; /* ALT_SDMMC_CTRL_INT_ENABLE */
836  volatile uint32_t DMA_ENABLE : 1; /* ALT_SDMMC_CTRL_DMA_ENABLE */
837  volatile uint32_t READ_WAIT : 1; /* ALT_SDMMC_CTRL_READ_WAIT */
838  volatile uint32_t SEND_IRQ_RESPONSE : 1; /* ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE */
839  volatile uint32_t ABORT_READ_DATA : 1; /* ALT_SDMMC_CTRL_ABORT_READ_DATA */
840  volatile uint32_t SEND_CCSD : 1; /* ALT_SDMMC_CTRL_SEND_CCSD */
841  volatile uint32_t SEND_AUTO_STOP_CCSD : 1; /* ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD */
842  volatile uint32_t CEATA_DEVICE_INTERRUPT_STATUS : 1; /* ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS */
843  uint32_t : 4; /* *UNDEFINED* */
844  volatile uint32_t CARD_VOLTAGE_A : 4; /* ALT_SDMMC_CTRL_CARD_VOLTAGE_A */
845  volatile uint32_t CARD_VOLTAGE_B : 4; /* ALT_SDMMC_CTRL_CARD_VOLTAGE_B */
846  volatile uint32_t ENABLE_OD_PULLUP : 1; /* ALT_SDMMC_CTRL_ENABLE_OD_PULLUP */
847  volatile uint32_t USE_INTERNAL_DMAC : 1; /* ALT_SDMMC_CTRL_USE_INTERNAL_DMAC */
848  uint32_t : 6; /* *UNDEFINED* */
849 };
850 
851 /* The typedef declaration for register ALT_SDMMC_CTRL. */
852 typedef struct ALT_SDMMC_CTRL_s ALT_SDMMC_CTRL_t;
853 #endif /* __ASSEMBLY__ */
854 
855 /* The reset value of the ALT_SDMMC_CTRL register. */
856 #define ALT_SDMMC_CTRL_RESET 0x00000000
857 /* The byte offset of the ALT_SDMMC_CTRL register from the beginning of the component. */
858 #define ALT_SDMMC_CTRL_OFST 0x0
859 /* The address of the ALT_SDMMC_CTRL register. */
860 #define ALT_SDMMC_CTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CTRL_OFST))
861 
862 /*
863  * Register : Power Enable Register - PWREN
864  *
865  * Power Enable Register
866  *
867  * Register Layout
868  *
869  * Bits | Access | Reset | Description
870  * :-------|:-------|:------|:-------------------------------
871  * [0] | RW | 0x0 | ALT_SDMMC_PWREN_POWER_ENABLE_0
872  * [31:1] | ??? | 0x0 | *UNDEFINED*
873  *
874  */
875 /*
876  * Field : POWER_ENABLE_0
877  *
878  * Power on/off switch for up to 16 cards; for example, bit[0] controls card 0.Once
879  * power is turned on, firmware should wait for regulator/switch ramp-up time
880  * before trying to initialize card.
881  *
882  * 0-power off
883  *
884  * 1-power on
885  *
886  * Only NUM_CARDS number of bits are implemented.Bit values output to card_power_en
887  * port. Optional feature; ports can be used as general-purpose outputs.
888  *
889  * Field Enumeration Values:
890  *
891  * Enum | Value | Description
892  * :-------------------------------------------|:------|:------------
893  * ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_OFF | 0x0 | Power off
894  * ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_ON | 0x1 | Power on
895  *
896  * Field Access Macros:
897  *
898  */
899 /*
900  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_ENABLE_0
901  *
902  * Power off
903  */
904 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_OFF 0x0
905 /*
906  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_ENABLE_0
907  *
908  * Power on
909  */
910 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_ON 0x1
911 
912 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field. */
913 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_LSB 0
914 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field. */
915 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_MSB 0
916 /* The width in bits of the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field. */
917 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_WIDTH 1
918 /* The mask used to set the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field value. */
919 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_SET_MSK 0x00000001
920 /* The mask used to clear the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field value. */
921 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_CLR_MSK 0xfffffffe
922 /* The reset value of the ALT_SDMMC_PWREN_POWER_ENABLE_0 register field. */
923 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_RESET 0x0
924 /* Extracts the ALT_SDMMC_PWREN_POWER_ENABLE_0 field value from a register. */
925 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_GET(value) (((value) & 0x00000001) >> 0)
926 /* Produces a ALT_SDMMC_PWREN_POWER_ENABLE_0 register field value suitable for setting the register. */
927 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_SET(value) (((value) << 0) & 0x00000001)
928 
929 #ifndef __ASSEMBLY__
930 /*
931  * WARNING: The C register and register group struct declarations are provided for
932  * convenience and illustrative purposes. They should, however, be used with
933  * caution as the C language standard provides no guarantees about the alignment or
934  * atomicity of device memory accesses. The recommended practice for coding device
935  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
936  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
937  * alt_write_dword() functions for 64 bit registers.
938  *
939  * The struct declaration for register ALT_SDMMC_PWREN.
940  */
941 struct ALT_SDMMC_PWREN_s
942 {
943  volatile uint32_t POWER_ENABLE_0 : 1; /* ALT_SDMMC_PWREN_POWER_ENABLE_0 */
944  uint32_t : 31; /* *UNDEFINED* */
945 };
946 
947 /* The typedef declaration for register ALT_SDMMC_PWREN. */
948 typedef struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
949 #endif /* __ASSEMBLY__ */
950 
951 /* The reset value of the ALT_SDMMC_PWREN register. */
952 #define ALT_SDMMC_PWREN_RESET 0x00000000
953 /* The byte offset of the ALT_SDMMC_PWREN register from the beginning of the component. */
954 #define ALT_SDMMC_PWREN_OFST 0x4
955 /* The address of the ALT_SDMMC_PWREN register. */
956 #define ALT_SDMMC_PWREN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_PWREN_OFST))
957 
958 /*
959  * Register : Clock Divider Register - CLKDIV
960  *
961  * Clock Divider Register
962  *
963  * Register Layout
964  *
965  * Bits | Access | Reset | Description
966  * :--------|:-------|:------|:------------------------------
967  * [7:0] | RW | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVIDER0
968  * [15:8] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVIDER1
969  * [23:16] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVIDER2
970  * [31:24] | R | 0x0 | ALT_SDMMC_CLKDIV_CLK_DIVIDER3
971  *
972  */
973 /*
974  * Field : CLK_DIVIDER0
975  *
976  * Clock divider-0 value. Clock division is 2*n. For example, value of 0 means
977  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
978  * value of "ff" means divide by 2*255 = 510, and so on.
979  *
980  * Field Access Macros:
981  *
982  */
983 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field. */
984 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_LSB 0
985 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field. */
986 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_MSB 7
987 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field. */
988 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_WIDTH 8
989 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field value. */
990 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_SET_MSK 0x000000ff
991 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field value. */
992 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_CLR_MSK 0xffffff00
993 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field. */
994 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_RESET 0x0
995 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVIDER0 field value from a register. */
996 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_GET(value) (((value) & 0x000000ff) >> 0)
997 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVIDER0 register field value suitable for setting the register. */
998 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_SET(value) (((value) << 0) & 0x000000ff)
999 
1000 /*
1001  * Field : CLK_DIVIDER1
1002  *
1003  * Clock divider-1 value. Clock division is 2*n. For example, value of 0 means
1004  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
1005  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
1006  * mode, bits not implemented because only one clock divider is supported
1007  *
1008  * Field Access Macros:
1009  *
1010  */
1011 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field. */
1012 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_LSB 8
1013 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field. */
1014 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_MSB 15
1015 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field. */
1016 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_WIDTH 8
1017 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field value. */
1018 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_SET_MSK 0x0000ff00
1019 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field value. */
1020 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_CLR_MSK 0xffff00ff
1021 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field. */
1022 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_RESET 0x0
1023 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVIDER1 field value from a register. */
1024 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_GET(value) (((value) & 0x0000ff00) >> 8)
1025 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVIDER1 register field value suitable for setting the register. */
1026 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_SET(value) (((value) << 8) & 0x0000ff00)
1027 
1028 /*
1029  * Field : CLK_DIVIDER2
1030  *
1031  * Clock divider-2 value. Clock division is 2*n. For example, value of 0 means
1032  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
1033  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
1034  * mode, bits not implemented because only one clock divider is supported.
1035  *
1036  * Field Access Macros:
1037  *
1038  */
1039 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field. */
1040 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_LSB 16
1041 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field. */
1042 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_MSB 23
1043 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field. */
1044 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_WIDTH 8
1045 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field value. */
1046 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_SET_MSK 0x00ff0000
1047 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field value. */
1048 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_CLR_MSK 0xff00ffff
1049 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field. */
1050 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_RESET 0x0
1051 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVIDER2 field value from a register. */
1052 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_GET(value) (((value) & 0x00ff0000) >> 16)
1053 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVIDER2 register field value suitable for setting the register. */
1054 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_SET(value) (((value) << 16) & 0x00ff0000)
1055 
1056 /*
1057  * Field : CLK_DIVIDER3
1058  *
1059  * Clock divider-3 value. Clock division is 2*n. For example, value of 0 means
1060  * divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a
1061  * value of "ff" means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
1062  * mode, bits not implemented because only one clock divider is supported.
1063  *
1064  * Field Access Macros:
1065  *
1066  */
1067 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field. */
1068 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_LSB 24
1069 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field. */
1070 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_MSB 31
1071 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field. */
1072 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_WIDTH 8
1073 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field value. */
1074 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_SET_MSK 0xff000000
1075 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field value. */
1076 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_CLR_MSK 0x00ffffff
1077 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field. */
1078 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_RESET 0x0
1079 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVIDER3 field value from a register. */
1080 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_GET(value) (((value) & 0xff000000) >> 24)
1081 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVIDER3 register field value suitable for setting the register. */
1082 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_SET(value) (((value) << 24) & 0xff000000)
1083 
1084 #ifndef __ASSEMBLY__
1085 /*
1086  * WARNING: The C register and register group struct declarations are provided for
1087  * convenience and illustrative purposes. They should, however, be used with
1088  * caution as the C language standard provides no guarantees about the alignment or
1089  * atomicity of device memory accesses. The recommended practice for coding device
1090  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1091  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1092  * alt_write_dword() functions for 64 bit registers.
1093  *
1094  * The struct declaration for register ALT_SDMMC_CLKDIV.
1095  */
1096 struct ALT_SDMMC_CLKDIV_s
1097 {
1098  volatile uint32_t CLK_DIVIDER0 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVIDER0 */
1099  const volatile uint32_t CLK_DIVIDER1 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVIDER1 */
1100  const volatile uint32_t CLK_DIVIDER2 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVIDER2 */
1101  const volatile uint32_t CLK_DIVIDER3 : 8; /* ALT_SDMMC_CLKDIV_CLK_DIVIDER3 */
1102 };
1103 
1104 /* The typedef declaration for register ALT_SDMMC_CLKDIV. */
1105 typedef struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
1106 #endif /* __ASSEMBLY__ */
1107 
1108 /* The reset value of the ALT_SDMMC_CLKDIV register. */
1109 #define ALT_SDMMC_CLKDIV_RESET 0x00000000
1110 /* The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component. */
1111 #define ALT_SDMMC_CLKDIV_OFST 0x8
1112 /* The address of the ALT_SDMMC_CLKDIV register. */
1113 #define ALT_SDMMC_CLKDIV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKDIV_OFST))
1114 
1115 /*
1116  * Register : Clock Source Register - CLKSRC
1117  *
1118  * Clock Source Register
1119  *
1120  * Register Layout
1121  *
1122  * Bits | Access | Reset | Description
1123  * :--------|:-------|:------|:-----------------------------------
1124  * [1:0] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE
1125  * [3:2] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE
1126  * [5:4] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE
1127  * [7:6] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE
1128  * [9:8] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE
1129  * [11:10] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE
1130  * [13:12] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE
1131  * [15:14] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE
1132  * [17:16] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE
1133  * [19:18] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE
1134  * [21:20] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE
1135  * [23:22] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE
1136  * [25:24] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE
1137  * [27:26] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE
1138  * [29:28] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE
1139  * [31:30] | R | 0x0 | ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE
1140  *
1141  */
1142 /*
1143  * Field : CARD0_CLK_SOURCE
1144  *
1145  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1146  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1147  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1148  * on bit value.
1149  *
1150  * 00 Clock divider 0
1151  *
1152  * 01 Clock divider 1
1153  *
1154  * 10 Clock divider 2
1155  *
1156  * 11 Clock divider 3
1157  *
1158  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1159  * always from clock divider 0, and this register is not implemented.
1160  *
1161  * Field Enumeration Values:
1162  *
1163  * Enum | Value | Description
1164  * :-----------------------------------------|:------|:----------------
1165  * ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1166  * ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1167  * ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1168  * ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1169  *
1170  * Field Access Macros:
1171  *
1172  */
1173 /*
1174  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE
1175  *
1176  * Clock divider 0
1177  */
1178 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV0 0x0
1179 /*
1180  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE
1181  *
1182  * Clock divider 1
1183  */
1184 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV1 0x1
1185 /*
1186  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE
1187  *
1188  * Clock divider 2
1189  */
1190 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV2 0x2
1191 /*
1192  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE
1193  *
1194  * Clock divider 3
1195  */
1196 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV3 0x3
1197 
1198 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field. */
1199 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_LSB 0
1200 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field. */
1201 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_MSB 1
1202 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field. */
1203 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_WIDTH 2
1204 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field value. */
1205 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_SET_MSK 0x00000003
1206 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field value. */
1207 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_CLR_MSK 0xfffffffc
1208 /* The reset value of the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field. */
1209 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_RESET 0x0
1210 /* Extracts the ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE field value from a register. */
1211 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_GET(value) (((value) & 0x00000003) >> 0)
1212 /* Produces a ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE register field value suitable for setting the register. */
1213 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_SET(value) (((value) << 0) & 0x00000003)
1214 
1215 /*
1216  * Field : CARD1_CLK_SOURCE
1217  *
1218  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1219  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1220  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1221  * on bit value.
1222  *
1223  * 00 Clock divider 0
1224  *
1225  * 01 Clock divider 1
1226  *
1227  * 10 Clock divider 2
1228  *
1229  * 11 Clock divider 3
1230  *
1231  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1232  * always from clock divider 0, and this register is not implemented.
1233  *
1234  * Field Enumeration Values:
1235  *
1236  * Enum | Value | Description
1237  * :-----------------------------------------|:------|:----------------
1238  * ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1239  * ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1240  * ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1241  * ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1242  *
1243  * Field Access Macros:
1244  *
1245  */
1246 /*
1247  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE
1248  *
1249  * Clock divider 0
1250  */
1251 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV0 0x0
1252 /*
1253  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE
1254  *
1255  * Clock divider 1
1256  */
1257 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV1 0x1
1258 /*
1259  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE
1260  *
1261  * Clock divider 2
1262  */
1263 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV2 0x2
1264 /*
1265  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE
1266  *
1267  * Clock divider 3
1268  */
1269 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV3 0x3
1270 
1271 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field. */
1272 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_LSB 2
1273 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field. */
1274 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_MSB 3
1275 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field. */
1276 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_WIDTH 2
1277 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field value. */
1278 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_SET_MSK 0x0000000c
1279 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field value. */
1280 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_CLR_MSK 0xfffffff3
1281 /* The reset value of the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field. */
1282 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_RESET 0x0
1283 /* Extracts the ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE field value from a register. */
1284 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_GET(value) (((value) & 0x0000000c) >> 2)
1285 /* Produces a ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE register field value suitable for setting the register. */
1286 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_SET(value) (((value) << 2) & 0x0000000c)
1287 
1288 /*
1289  * Field : CARD2_CLK_SOURCE
1290  *
1291  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1292  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1293  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1294  * on bit value.
1295  *
1296  * 00 Clock divider 0
1297  *
1298  * 01 Clock divider 1
1299  *
1300  * 10 Clock divider 2
1301  *
1302  * 11 Clock divider 3
1303  *
1304  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1305  * always from clock divider 0, and this register is not implemented.
1306  *
1307  * Field Enumeration Values:
1308  *
1309  * Enum | Value | Description
1310  * :-----------------------------------------|:------|:----------------
1311  * ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1312  * ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1313  * ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1314  * ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1315  *
1316  * Field Access Macros:
1317  *
1318  */
1319 /*
1320  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE
1321  *
1322  * Clock divider 0
1323  */
1324 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV0 0x0
1325 /*
1326  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE
1327  *
1328  * Clock divider 1
1329  */
1330 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV1 0x1
1331 /*
1332  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE
1333  *
1334  * Clock divider 2
1335  */
1336 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV2 0x2
1337 /*
1338  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE
1339  *
1340  * Clock divider 3
1341  */
1342 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV3 0x3
1343 
1344 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field. */
1345 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_LSB 4
1346 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field. */
1347 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_MSB 5
1348 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field. */
1349 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_WIDTH 2
1350 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field value. */
1351 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_SET_MSK 0x00000030
1352 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field value. */
1353 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_CLR_MSK 0xffffffcf
1354 /* The reset value of the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field. */
1355 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_RESET 0x0
1356 /* Extracts the ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE field value from a register. */
1357 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_GET(value) (((value) & 0x00000030) >> 4)
1358 /* Produces a ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE register field value suitable for setting the register. */
1359 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_SET(value) (((value) << 4) & 0x00000030)
1360 
1361 /*
1362  * Field : CARD3_CLK_SOURCE
1363  *
1364  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1365  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1366  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1367  * on bit value.
1368  *
1369  * 00 Clock divider 0
1370  *
1371  * 01 Clock divider 1
1372  *
1373  * 10 Clock divider 2
1374  *
1375  * 11 Clock divider 3
1376  *
1377  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1378  * always from clock divider 0, and this register is not implemented.
1379  *
1380  * Field Enumeration Values:
1381  *
1382  * Enum | Value | Description
1383  * :-----------------------------------------|:------|:----------------
1384  * ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1385  * ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1386  * ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1387  * ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1388  *
1389  * Field Access Macros:
1390  *
1391  */
1392 /*
1393  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE
1394  *
1395  * Clock divider 0
1396  */
1397 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV0 0x0
1398 /*
1399  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE
1400  *
1401  * Clock divider 1
1402  */
1403 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV1 0x1
1404 /*
1405  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE
1406  *
1407  * Clock divider 2
1408  */
1409 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV2 0x2
1410 /*
1411  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE
1412  *
1413  * Clock divider 3
1414  */
1415 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV3 0x3
1416 
1417 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field. */
1418 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_LSB 6
1419 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field. */
1420 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_MSB 7
1421 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field. */
1422 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_WIDTH 2
1423 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field value. */
1424 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_SET_MSK 0x000000c0
1425 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field value. */
1426 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_CLR_MSK 0xffffff3f
1427 /* The reset value of the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field. */
1428 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_RESET 0x0
1429 /* Extracts the ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE field value from a register. */
1430 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_GET(value) (((value) & 0x000000c0) >> 6)
1431 /* Produces a ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE register field value suitable for setting the register. */
1432 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_SET(value) (((value) << 6) & 0x000000c0)
1433 
1434 /*
1435  * Field : CARD4_CLK_SOURCE
1436  *
1437  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1438  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1439  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1440  * on bit value.
1441  *
1442  * 00 Clock divider 0
1443  *
1444  * 01 Clock divider 1
1445  *
1446  * 10 Clock divider 2
1447  *
1448  * 11 Clock divider 3
1449  *
1450  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1451  * always from clock divider 0, and this register is not implemented.
1452  *
1453  * Field Enumeration Values:
1454  *
1455  * Enum | Value | Description
1456  * :-----------------------------------------|:------|:----------------
1457  * ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1458  * ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1459  * ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1460  * ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1461  *
1462  * Field Access Macros:
1463  *
1464  */
1465 /*
1466  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE
1467  *
1468  * Clock divider 0
1469  */
1470 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV0 0x0
1471 /*
1472  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE
1473  *
1474  * Clock divider 1
1475  */
1476 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV1 0x1
1477 /*
1478  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE
1479  *
1480  * Clock divider 2
1481  */
1482 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV2 0x2
1483 /*
1484  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE
1485  *
1486  * Clock divider 3
1487  */
1488 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV3 0x3
1489 
1490 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field. */
1491 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_LSB 8
1492 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field. */
1493 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_MSB 9
1494 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field. */
1495 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_WIDTH 2
1496 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field value. */
1497 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_SET_MSK 0x00000300
1498 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field value. */
1499 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_CLR_MSK 0xfffffcff
1500 /* The reset value of the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field. */
1501 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_RESET 0x0
1502 /* Extracts the ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE field value from a register. */
1503 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_GET(value) (((value) & 0x00000300) >> 8)
1504 /* Produces a ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE register field value suitable for setting the register. */
1505 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_SET(value) (((value) << 8) & 0x00000300)
1506 
1507 /*
1508  * Field : CARD5_CLK_SOURCE
1509  *
1510  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1511  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1512  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1513  * on bit value.
1514  *
1515  * 00 Clock divider 0
1516  *
1517  * 01 Clock divider 1
1518  *
1519  * 10 Clock divider 2
1520  *
1521  * 11 Clock divider 3
1522  *
1523  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1524  * always from clock divider 0, and this register is not implemented.
1525  *
1526  * Field Enumeration Values:
1527  *
1528  * Enum | Value | Description
1529  * :-----------------------------------------|:------|:----------------
1530  * ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1531  * ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1532  * ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1533  * ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1534  *
1535  * Field Access Macros:
1536  *
1537  */
1538 /*
1539  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE
1540  *
1541  * Clock divider 0
1542  */
1543 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV0 0x0
1544 /*
1545  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE
1546  *
1547  * Clock divider 1
1548  */
1549 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV1 0x1
1550 /*
1551  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE
1552  *
1553  * Clock divider 2
1554  */
1555 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV2 0x2
1556 /*
1557  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE
1558  *
1559  * Clock divider 3
1560  */
1561 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV3 0x3
1562 
1563 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field. */
1564 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_LSB 10
1565 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field. */
1566 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_MSB 11
1567 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field. */
1568 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_WIDTH 2
1569 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field value. */
1570 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_SET_MSK 0x00000c00
1571 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field value. */
1572 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_CLR_MSK 0xfffff3ff
1573 /* The reset value of the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field. */
1574 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_RESET 0x0
1575 /* Extracts the ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE field value from a register. */
1576 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_GET(value) (((value) & 0x00000c00) >> 10)
1577 /* Produces a ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE register field value suitable for setting the register. */
1578 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_SET(value) (((value) << 10) & 0x00000c00)
1579 
1580 /*
1581  * Field : CARD6_CLK_SOURCE
1582  *
1583  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1584  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1585  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1586  * on bit value.
1587  *
1588  * 00 Clock divider 0
1589  *
1590  * 01 Clock divider 1
1591  *
1592  * 10 Clock divider 2
1593  *
1594  * 11 Clock divider 3
1595  *
1596  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1597  * always from clock divider 0, and this register is not implemented.
1598  *
1599  * Field Enumeration Values:
1600  *
1601  * Enum | Value | Description
1602  * :-----------------------------------------|:------|:----------------
1603  * ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1604  * ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1605  * ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1606  * ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1607  *
1608  * Field Access Macros:
1609  *
1610  */
1611 /*
1612  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE
1613  *
1614  * Clock divider 0
1615  */
1616 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV0 0x0
1617 /*
1618  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE
1619  *
1620  * Clock divider 1
1621  */
1622 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV1 0x1
1623 /*
1624  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE
1625  *
1626  * Clock divider 2
1627  */
1628 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV2 0x2
1629 /*
1630  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE
1631  *
1632  * Clock divider 3
1633  */
1634 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV3 0x3
1635 
1636 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field. */
1637 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_LSB 12
1638 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field. */
1639 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_MSB 13
1640 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field. */
1641 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_WIDTH 2
1642 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field value. */
1643 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_SET_MSK 0x00003000
1644 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field value. */
1645 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_CLR_MSK 0xffffcfff
1646 /* The reset value of the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field. */
1647 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_RESET 0x0
1648 /* Extracts the ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE field value from a register. */
1649 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_GET(value) (((value) & 0x00003000) >> 12)
1650 /* Produces a ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE register field value suitable for setting the register. */
1651 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_SET(value) (((value) << 12) & 0x00003000)
1652 
1653 /*
1654  * Field : CARD7_CLK_SOURCE
1655  *
1656  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1657  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1658  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1659  * on bit value.
1660  *
1661  * 00 Clock divider 0
1662  *
1663  * 01 Clock divider 1
1664  *
1665  * 10 Clock divider 2
1666  *
1667  * 11 Clock divider 3
1668  *
1669  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1670  * always from clock divider 0, and this register is not implemented.
1671  *
1672  * Field Enumeration Values:
1673  *
1674  * Enum | Value | Description
1675  * :-----------------------------------------|:------|:----------------
1676  * ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1677  * ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1678  * ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1679  * ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1680  *
1681  * Field Access Macros:
1682  *
1683  */
1684 /*
1685  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE
1686  *
1687  * Clock divider 0
1688  */
1689 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV0 0x0
1690 /*
1691  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE
1692  *
1693  * Clock divider 1
1694  */
1695 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV1 0x1
1696 /*
1697  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE
1698  *
1699  * Clock divider 2
1700  */
1701 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV2 0x2
1702 /*
1703  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE
1704  *
1705  * Clock divider 3
1706  */
1707 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV3 0x3
1708 
1709 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field. */
1710 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_LSB 14
1711 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field. */
1712 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_MSB 15
1713 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field. */
1714 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_WIDTH 2
1715 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field value. */
1716 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_SET_MSK 0x0000c000
1717 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field value. */
1718 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_CLR_MSK 0xffff3fff
1719 /* The reset value of the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field. */
1720 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_RESET 0x0
1721 /* Extracts the ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE field value from a register. */
1722 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_GET(value) (((value) & 0x0000c000) >> 14)
1723 /* Produces a ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE register field value suitable for setting the register. */
1724 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_SET(value) (((value) << 14) & 0x0000c000)
1725 
1726 /*
1727  * Field : CARD8_CLK_SOURCE
1728  *
1729  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1730  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1731  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1732  * on bit value.
1733  *
1734  * 00 Clock divider 0
1735  *
1736  * 01 Clock divider 1
1737  *
1738  * 10 Clock divider 2
1739  *
1740  * 11 Clock divider 3
1741  *
1742  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1743  * always from clock divider 0, and this register is not implemented.
1744  *
1745  * Field Enumeration Values:
1746  *
1747  * Enum | Value | Description
1748  * :-----------------------------------------|:------|:----------------
1749  * ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1750  * ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1751  * ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1752  * ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1753  *
1754  * Field Access Macros:
1755  *
1756  */
1757 /*
1758  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE
1759  *
1760  * Clock divider 0
1761  */
1762 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV0 0x0
1763 /*
1764  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE
1765  *
1766  * Clock divider 1
1767  */
1768 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV1 0x1
1769 /*
1770  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE
1771  *
1772  * Clock divider 2
1773  */
1774 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV2 0x2
1775 /*
1776  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE
1777  *
1778  * Clock divider 3
1779  */
1780 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV3 0x3
1781 
1782 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field. */
1783 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_LSB 16
1784 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field. */
1785 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_MSB 17
1786 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field. */
1787 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_WIDTH 2
1788 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field value. */
1789 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_SET_MSK 0x00030000
1790 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field value. */
1791 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_CLR_MSK 0xfffcffff
1792 /* The reset value of the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field. */
1793 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_RESET 0x0
1794 /* Extracts the ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE field value from a register. */
1795 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_GET(value) (((value) & 0x00030000) >> 16)
1796 /* Produces a ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE register field value suitable for setting the register. */
1797 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_SET(value) (((value) << 16) & 0x00030000)
1798 
1799 /*
1800  * Field : CARD9_CLK_SOURCE
1801  *
1802  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1803  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1804  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1805  * on bit value.
1806  *
1807  * 00 Clock divider 0
1808  *
1809  * 01 Clock divider 1
1810  *
1811  * 10 Clock divider 2
1812  *
1813  * 11 Clock divider 3
1814  *
1815  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1816  * always from clock divider 0, and this register is not implemented.
1817  *
1818  * Field Enumeration Values:
1819  *
1820  * Enum | Value | Description
1821  * :-----------------------------------------|:------|:----------------
1822  * ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1823  * ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1824  * ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1825  * ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1826  *
1827  * Field Access Macros:
1828  *
1829  */
1830 /*
1831  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE
1832  *
1833  * Clock divider 0
1834  */
1835 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV0 0x0
1836 /*
1837  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE
1838  *
1839  * Clock divider 1
1840  */
1841 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV1 0x1
1842 /*
1843  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE
1844  *
1845  * Clock divider 2
1846  */
1847 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV2 0x2
1848 /*
1849  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE
1850  *
1851  * Clock divider 3
1852  */
1853 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV3 0x3
1854 
1855 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field. */
1856 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_LSB 18
1857 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field. */
1858 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_MSB 19
1859 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field. */
1860 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_WIDTH 2
1861 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field value. */
1862 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_SET_MSK 0x000c0000
1863 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field value. */
1864 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_CLR_MSK 0xfff3ffff
1865 /* The reset value of the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field. */
1866 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_RESET 0x0
1867 /* Extracts the ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE field value from a register. */
1868 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_GET(value) (((value) & 0x000c0000) >> 18)
1869 /* Produces a ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE register field value suitable for setting the register. */
1870 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_SET(value) (((value) << 18) & 0x000c0000)
1871 
1872 /*
1873  * Field : CARD10_CLK_SOURCE
1874  *
1875  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1876  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1877  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1878  * on bit value.
1879  *
1880  * 00 Clock divider 0
1881  *
1882  * 01 Clock divider 1
1883  *
1884  * 10 Clock divider 2
1885  *
1886  * 11 Clock divider 3
1887  *
1888  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1889  * always from clock divider 0, and this register is not implemented.
1890  *
1891  * Field Enumeration Values:
1892  *
1893  * Enum | Value | Description
1894  * :------------------------------------------|:------|:----------------
1895  * ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1896  * ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1897  * ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1898  * ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1899  *
1900  * Field Access Macros:
1901  *
1902  */
1903 /*
1904  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE
1905  *
1906  * Clock divider 0
1907  */
1908 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV0 0x0
1909 /*
1910  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE
1911  *
1912  * Clock divider 1
1913  */
1914 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV1 0x1
1915 /*
1916  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE
1917  *
1918  * Clock divider 2
1919  */
1920 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV2 0x2
1921 /*
1922  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE
1923  *
1924  * Clock divider 3
1925  */
1926 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV3 0x3
1927 
1928 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field. */
1929 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_LSB 20
1930 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field. */
1931 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_MSB 21
1932 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field. */
1933 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_WIDTH 2
1934 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field value. */
1935 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_SET_MSK 0x00300000
1936 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field value. */
1937 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_CLR_MSK 0xffcfffff
1938 /* The reset value of the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field. */
1939 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_RESET 0x0
1940 /* Extracts the ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE field value from a register. */
1941 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_GET(value) (((value) & 0x00300000) >> 20)
1942 /* Produces a ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE register field value suitable for setting the register. */
1943 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_SET(value) (((value) << 20) & 0x00300000)
1944 
1945 /*
1946  * Field : CARD11_CLK_SOURCE
1947  *
1948  * Clock divider source for up to 16 SD cards supported. Each card has two bits
1949  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
1950  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
1951  * on bit value.
1952  *
1953  * 00 Clock divider 0
1954  *
1955  * 01 Clock divider 1
1956  *
1957  * 10 Clock divider 2
1958  *
1959  * 11 Clock divider 3
1960  *
1961  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
1962  * always from clock divider 0, and this register is not implemented.
1963  *
1964  * Field Enumeration Values:
1965  *
1966  * Enum | Value | Description
1967  * :------------------------------------------|:------|:----------------
1968  * ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
1969  * ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
1970  * ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
1971  * ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
1972  *
1973  * Field Access Macros:
1974  *
1975  */
1976 /*
1977  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE
1978  *
1979  * Clock divider 0
1980  */
1981 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV0 0x0
1982 /*
1983  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE
1984  *
1985  * Clock divider 1
1986  */
1987 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV1 0x1
1988 /*
1989  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE
1990  *
1991  * Clock divider 2
1992  */
1993 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV2 0x2
1994 /*
1995  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE
1996  *
1997  * Clock divider 3
1998  */
1999 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV3 0x3
2000 
2001 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field. */
2002 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_LSB 22
2003 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field. */
2004 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_MSB 23
2005 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field. */
2006 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_WIDTH 2
2007 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field value. */
2008 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_SET_MSK 0x00c00000
2009 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field value. */
2010 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_CLR_MSK 0xff3fffff
2011 /* The reset value of the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field. */
2012 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_RESET 0x0
2013 /* Extracts the ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE field value from a register. */
2014 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_GET(value) (((value) & 0x00c00000) >> 22)
2015 /* Produces a ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE register field value suitable for setting the register. */
2016 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_SET(value) (((value) << 22) & 0x00c00000)
2017 
2018 /*
2019  * Field : CARD12_CLK_SOURCE
2020  *
2021  * Clock divider source for up to 16 SD cards supported. Each card has two bits
2022  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
2023  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
2024  * on bit value.
2025  *
2026  * 00 Clock divider 0
2027  *
2028  * 01 Clock divider 1
2029  *
2030  * 10 Clock divider 2
2031  *
2032  * 11 Clock divider 3
2033  *
2034  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
2035  * always from clock divider 0, and this register is not implemented.
2036  *
2037  * Field Enumeration Values:
2038  *
2039  * Enum | Value | Description
2040  * :------------------------------------------|:------|:----------------
2041  * ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
2042  * ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
2043  * ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
2044  * ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
2045  *
2046  * Field Access Macros:
2047  *
2048  */
2049 /*
2050  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE
2051  *
2052  * Clock divider 0
2053  */
2054 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV0 0x0
2055 /*
2056  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE
2057  *
2058  * Clock divider 1
2059  */
2060 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV1 0x1
2061 /*
2062  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE
2063  *
2064  * Clock divider 2
2065  */
2066 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV2 0x2
2067 /*
2068  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE
2069  *
2070  * Clock divider 3
2071  */
2072 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV3 0x3
2073 
2074 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field. */
2075 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_LSB 24
2076 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field. */
2077 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_MSB 25
2078 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field. */
2079 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_WIDTH 2
2080 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field value. */
2081 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_SET_MSK 0x03000000
2082 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field value. */
2083 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_CLR_MSK 0xfcffffff
2084 /* The reset value of the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field. */
2085 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_RESET 0x0
2086 /* Extracts the ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE field value from a register. */
2087 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_GET(value) (((value) & 0x03000000) >> 24)
2088 /* Produces a ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE register field value suitable for setting the register. */
2089 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_SET(value) (((value) << 24) & 0x03000000)
2090 
2091 /*
2092  * Field : CARD13_CLK_SOURCE
2093  *
2094  * Clock divider source for up to 16 SD cards supported. Each card has two bits
2095  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
2096  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
2097  * on bit value.
2098  *
2099  * 00 Clock divider 0
2100  *
2101  * 01 Clock divider 1
2102  *
2103  * 10 Clock divider 2
2104  *
2105  * 11 Clock divider 3
2106  *
2107  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
2108  * always from clock divider 0, and this register is not implemented.
2109  *
2110  * Field Enumeration Values:
2111  *
2112  * Enum | Value | Description
2113  * :------------------------------------------|:------|:----------------
2114  * ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
2115  * ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
2116  * ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
2117  * ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
2118  *
2119  * Field Access Macros:
2120  *
2121  */
2122 /*
2123  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE
2124  *
2125  * Clock divider 0
2126  */
2127 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV0 0x0
2128 /*
2129  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE
2130  *
2131  * Clock divider 1
2132  */
2133 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV1 0x1
2134 /*
2135  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE
2136  *
2137  * Clock divider 2
2138  */
2139 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV2 0x2
2140 /*
2141  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE
2142  *
2143  * Clock divider 3
2144  */
2145 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV3 0x3
2146 
2147 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field. */
2148 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_LSB 26
2149 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field. */
2150 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_MSB 27
2151 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field. */
2152 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_WIDTH 2
2153 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field value. */
2154 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_SET_MSK 0x0c000000
2155 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field value. */
2156 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_CLR_MSK 0xf3ffffff
2157 /* The reset value of the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field. */
2158 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_RESET 0x0
2159 /* Extracts the ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE field value from a register. */
2160 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_GET(value) (((value) & 0x0c000000) >> 26)
2161 /* Produces a ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE register field value suitable for setting the register. */
2162 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_SET(value) (((value) << 26) & 0x0c000000)
2163 
2164 /*
2165  * Field : CARD14_CLK_SOURCE
2166  *
2167  * Clock divider source for up to 16 SD cards supported. Each card has two bits
2168  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
2169  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
2170  * on bit value.
2171  *
2172  * 00 Clock divider 0
2173  *
2174  * 01 Clock divider 1
2175  *
2176  * 10 Clock divider 2
2177  *
2178  * 11 Clock divider 3
2179  *
2180  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
2181  * always from clock divider 0, and this register is not implemented.
2182  *
2183  * Field Enumeration Values:
2184  *
2185  * Enum | Value | Description
2186  * :------------------------------------------|:------|:----------------
2187  * ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
2188  * ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
2189  * ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
2190  * ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
2191  *
2192  * Field Access Macros:
2193  *
2194  */
2195 /*
2196  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE
2197  *
2198  * Clock divider 0
2199  */
2200 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV0 0x0
2201 /*
2202  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE
2203  *
2204  * Clock divider 1
2205  */
2206 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV1 0x1
2207 /*
2208  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE
2209  *
2210  * Clock divider 2
2211  */
2212 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV2 0x2
2213 /*
2214  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE
2215  *
2216  * Clock divider 3
2217  */
2218 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV3 0x3
2219 
2220 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field. */
2221 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_LSB 28
2222 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field. */
2223 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_MSB 29
2224 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field. */
2225 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_WIDTH 2
2226 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field value. */
2227 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_SET_MSK 0x30000000
2228 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field value. */
2229 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_CLR_MSK 0xcfffffff
2230 /* The reset value of the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field. */
2231 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_RESET 0x0
2232 /* Extracts the ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE field value from a register. */
2233 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_GET(value) (((value) & 0x30000000) >> 28)
2234 /* Produces a ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE register field value suitable for setting the register. */
2235 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_SET(value) (((value) << 28) & 0x30000000)
2236 
2237 /*
2238  * Field : CARD15_CLK_SOURCE
2239  *
2240  * Clock divider source for up to 16 SD cards supported. Each card has two bits
2241  * assigned to it. For example, bits[1:0] assigned for card-0, which maps and
2242  * internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending
2243  * on bit value.
2244  *
2245  * 00 Clock divider 0
2246  *
2247  * 01 Clock divider 1
2248  *
2249  * 10 Clock divider 2
2250  *
2251  * 11 Clock divider 3
2252  *
2253  * In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is
2254  * always from clock divider 0, and this register is not implemented.
2255  *
2256  * Field Enumeration Values:
2257  *
2258  * Enum | Value | Description
2259  * :------------------------------------------|:------|:----------------
2260  * ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV0 | 0x0 | Clock divider 0
2261  * ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV1 | 0x1 | Clock divider 1
2262  * ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV2 | 0x2 | Clock divider 2
2263  * ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV3 | 0x3 | Clock divider 3
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /*
2269  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE
2270  *
2271  * Clock divider 0
2272  */
2273 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV0 0x0
2274 /*
2275  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE
2276  *
2277  * Clock divider 1
2278  */
2279 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV1 0x1
2280 /*
2281  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE
2282  *
2283  * Clock divider 2
2284  */
2285 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV2 0x2
2286 /*
2287  * Enumerated value for register field ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE
2288  *
2289  * Clock divider 3
2290  */
2291 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV3 0x3
2292 
2293 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field. */
2294 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_LSB 30
2295 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field. */
2296 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_MSB 31
2297 /* The width in bits of the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field. */
2298 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_WIDTH 2
2299 /* The mask used to set the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field value. */
2300 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_SET_MSK 0xc0000000
2301 /* The mask used to clear the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field value. */
2302 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_CLR_MSK 0x3fffffff
2303 /* The reset value of the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field. */
2304 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_RESET 0x0
2305 /* Extracts the ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE field value from a register. */
2306 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_GET(value) (((value) & 0xc0000000) >> 30)
2307 /* Produces a ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE register field value suitable for setting the register. */
2308 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_SET(value) (((value) << 30) & 0xc0000000)
2309 
2310 #ifndef __ASSEMBLY__
2311 /*
2312  * WARNING: The C register and register group struct declarations are provided for
2313  * convenience and illustrative purposes. They should, however, be used with
2314  * caution as the C language standard provides no guarantees about the alignment or
2315  * atomicity of device memory accesses. The recommended practice for coding device
2316  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2317  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2318  * alt_write_dword() functions for 64 bit registers.
2319  *
2320  * The struct declaration for register ALT_SDMMC_CLKSRC.
2321  */
2322 struct ALT_SDMMC_CLKSRC_s
2323 {
2324  const volatile uint32_t CARD0_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE */
2325  const volatile uint32_t CARD1_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE */
2326  const volatile uint32_t CARD2_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE */
2327  const volatile uint32_t CARD3_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE */
2328  const volatile uint32_t CARD4_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE */
2329  const volatile uint32_t CARD5_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE */
2330  const volatile uint32_t CARD6_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE */
2331  const volatile uint32_t CARD7_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE */
2332  const volatile uint32_t CARD8_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE */
2333  const volatile uint32_t CARD9_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE */
2334  const volatile uint32_t CARD10_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE */
2335  const volatile uint32_t CARD11_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE */
2336  const volatile uint32_t CARD12_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE */
2337  const volatile uint32_t CARD13_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE */
2338  const volatile uint32_t CARD14_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE */
2339  const volatile uint32_t CARD15_CLK_SOURCE : 2; /* ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE */
2340 };
2341 
2342 /* The typedef declaration for register ALT_SDMMC_CLKSRC. */
2343 typedef struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
2344 #endif /* __ASSEMBLY__ */
2345 
2346 /* The reset value of the ALT_SDMMC_CLKSRC register. */
2347 #define ALT_SDMMC_CLKSRC_RESET 0x00000000
2348 /* The byte offset of the ALT_SDMMC_CLKSRC register from the beginning of the component. */
2349 #define ALT_SDMMC_CLKSRC_OFST 0xc
2350 /* The address of the ALT_SDMMC_CLKSRC register. */
2351 #define ALT_SDMMC_CLKSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKSRC_OFST))
2352 
2353 /*
2354  * Register : Clock Enable Register - CLKENA
2355  *
2356  * Clock Enable Register
2357  *
2358  * Register Layout
2359  *
2360  * Bits | Access | Reset | Description
2361  * :--------|:-------|:------|:----------------------------------
2362  * [0] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_ENABLE_0
2363  * [15:1] | ??? | 0x0 | *UNDEFINED*
2364  * [16] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0
2365  * [31:17] | ??? | 0x0 | *UNDEFINED*
2366  *
2367  */
2368 /*
2369  * Field : CCLK_ENABLE_0
2370  *
2371  * Clock-enable control for up to 16 SD card clocks and one MMC card clock
2372  * supported.
2373  *
2374  * 0-Clock disabled
2375  *
2376  * 1-Clock enabled
2377  *
2378  * In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0]
2379  * is used.
2380  *
2381  * Field Enumeration Values:
2382  *
2383  * Enum | Value | Description
2384  * :------------------------------------------|:------|:---------------
2385  * ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_DISABLED | 0x0 | Clock disabled
2386  * ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_ENABLED | 0x1 | Clock enabled
2387  *
2388  * Field Access Macros:
2389  *
2390  */
2391 /*
2392  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_ENABLE_0
2393  *
2394  * Clock disabled
2395  */
2396 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_DISABLED 0x0
2397 /*
2398  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_ENABLE_0
2399  *
2400  * Clock enabled
2401  */
2402 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_ENABLED 0x1
2403 
2404 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field. */
2405 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_LSB 0
2406 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field. */
2407 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_MSB 0
2408 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field. */
2409 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_WIDTH 1
2410 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field value. */
2411 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_SET_MSK 0x00000001
2412 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field value. */
2413 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_CLR_MSK 0xfffffffe
2414 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field. */
2415 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_RESET 0x0
2416 /* Extracts the ALT_SDMMC_CLKENA_CCLK_ENABLE_0 field value from a register. */
2417 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_GET(value) (((value) & 0x00000001) >> 0)
2418 /* Produces a ALT_SDMMC_CLKENA_CCLK_ENABLE_0 register field value suitable for setting the register. */
2419 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_SET(value) (((value) << 0) & 0x00000001)
2420 
2421 /*
2422  * Field : CCLK_LOW_POWER_0
2423  *
2424  * Low-power control for up to 16 SD card clocks and one MMC card clock supported.
2425  *
2426  * 0-Non-low-power mode
2427  *
2428  * 1-Low-power mode; stop clock when card in IDLE (should be normally set to only
2429  * MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock
2430  * should not be stopped).
2431  *
2432  * In MMC-Ver3.3-only mode, since there is only one cclk_out, only
2433  * cclk_low_power[0] is used.
2434  *
2435  * Field Enumeration Values:
2436  *
2437  * Enum | Value | Description
2438  * :--------------------------------------------------|:------|:-------------------
2439  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_NON_LOW_POWER | 0x0 | Non Low Power mode
2440  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_LOW_POWER | 0x1 | Low Power mode
2441  *
2442  * Field Access Macros:
2443  *
2444  */
2445 /*
2446  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0
2447  *
2448  * Non Low Power mode
2449  */
2450 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_NON_LOW_POWER 0x0
2451 /*
2452  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0
2453  *
2454  * Low Power mode
2455  */
2456 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_LOW_POWER 0x1
2457 
2458 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field. */
2459 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_LSB 16
2460 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field. */
2461 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_MSB 16
2462 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field. */
2463 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_WIDTH 1
2464 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field value. */
2465 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_SET_MSK 0x00010000
2466 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field value. */
2467 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_CLR_MSK 0xfffeffff
2468 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field. */
2469 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_RESET 0x0
2470 /* Extracts the ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 field value from a register. */
2471 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_GET(value) (((value) & 0x00010000) >> 16)
2472 /* Produces a ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 register field value suitable for setting the register. */
2473 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_SET(value) (((value) << 16) & 0x00010000)
2474 
2475 #ifndef __ASSEMBLY__
2476 /*
2477  * WARNING: The C register and register group struct declarations are provided for
2478  * convenience and illustrative purposes. They should, however, be used with
2479  * caution as the C language standard provides no guarantees about the alignment or
2480  * atomicity of device memory accesses. The recommended practice for coding device
2481  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2482  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2483  * alt_write_dword() functions for 64 bit registers.
2484  *
2485  * The struct declaration for register ALT_SDMMC_CLKENA.
2486  */
2487 struct ALT_SDMMC_CLKENA_s
2488 {
2489  volatile uint32_t CCLK_ENABLE_0 : 1; /* ALT_SDMMC_CLKENA_CCLK_ENABLE_0 */
2490  uint32_t : 15; /* *UNDEFINED* */
2491  volatile uint32_t CCLK_LOW_POWER_0 : 1; /* ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0 */
2492  uint32_t : 15; /* *UNDEFINED* */
2493 };
2494 
2495 /* The typedef declaration for register ALT_SDMMC_CLKENA. */
2496 typedef struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
2497 #endif /* __ASSEMBLY__ */
2498 
2499 /* The reset value of the ALT_SDMMC_CLKENA register. */
2500 #define ALT_SDMMC_CLKENA_RESET 0x00000000
2501 /* The byte offset of the ALT_SDMMC_CLKENA register from the beginning of the component. */
2502 #define ALT_SDMMC_CLKENA_OFST 0x10
2503 /* The address of the ALT_SDMMC_CLKENA register. */
2504 #define ALT_SDMMC_CLKENA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKENA_OFST))
2505 
2506 /*
2507  * Register : Timeout Register - TMOUT
2508  *
2509  * Timeout Register
2510  *
2511  * Register Layout
2512  *
2513  * Bits | Access | Reset | Description
2514  * :-------|:-------|:---------|:---------------------------------
2515  * [7:0] | RW | 0x40 | ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT
2516  * [31:8] | RW | 0xffffff | ALT_SDMMC_TMOUT_DATA_TIMEOUT
2517  *
2518  */
2519 /*
2520  * Field : RESPONSE_TIMEOUT
2521  *
2522  * Response timeout value.
2523  *
2524  * Value is in number of card output clocks cclk_out.
2525  *
2526  * Field Access Macros:
2527  *
2528  */
2529 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field. */
2530 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_LSB 0
2531 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field. */
2532 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_MSB 7
2533 /* The width in bits of the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field. */
2534 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_WIDTH 8
2535 /* The mask used to set the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field value. */
2536 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_SET_MSK 0x000000ff
2537 /* The mask used to clear the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field value. */
2538 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_CLR_MSK 0xffffff00
2539 /* The reset value of the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field. */
2540 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_RESET 0x40
2541 /* Extracts the ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT field value from a register. */
2542 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_GET(value) (((value) & 0x000000ff) >> 0)
2543 /* Produces a ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT register field value suitable for setting the register. */
2544 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_SET(value) (((value) << 0) & 0x000000ff)
2545 
2546 /*
2547  * Field : DATA_TIMEOUT
2548  *
2549  * Value for card Data Read Timeout; same value also used for Data
2550  *
2551  * Starvation by Host timeout. The timeout counter is started only after the card
2552  * clock is stopped.Value is in number of card output clocks cclk_out of selected
2553  * card.
2554  *
2555  * Note: The software timer should be used if the timeout value is in the order
2556  *
2557  * of 100 ms. In this case, read data timeout interrupt needs to be disabled.
2558  *
2559  * Field Access Macros:
2560  *
2561  */
2562 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field. */
2563 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_LSB 8
2564 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field. */
2565 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_MSB 31
2566 /* The width in bits of the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field. */
2567 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_WIDTH 24
2568 /* The mask used to set the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field value. */
2569 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_SET_MSK 0xffffff00
2570 /* The mask used to clear the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field value. */
2571 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_CLR_MSK 0x000000ff
2572 /* The reset value of the ALT_SDMMC_TMOUT_DATA_TIMEOUT register field. */
2573 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_RESET 0xffffff
2574 /* Extracts the ALT_SDMMC_TMOUT_DATA_TIMEOUT field value from a register. */
2575 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_GET(value) (((value) & 0xffffff00) >> 8)
2576 /* Produces a ALT_SDMMC_TMOUT_DATA_TIMEOUT register field value suitable for setting the register. */
2577 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_SET(value) (((value) << 8) & 0xffffff00)
2578 
2579 #ifndef __ASSEMBLY__
2580 /*
2581  * WARNING: The C register and register group struct declarations are provided for
2582  * convenience and illustrative purposes. They should, however, be used with
2583  * caution as the C language standard provides no guarantees about the alignment or
2584  * atomicity of device memory accesses. The recommended practice for coding device
2585  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2586  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2587  * alt_write_dword() functions for 64 bit registers.
2588  *
2589  * The struct declaration for register ALT_SDMMC_TMOUT.
2590  */
2591 struct ALT_SDMMC_TMOUT_s
2592 {
2593  volatile uint32_t RESPONSE_TIMEOUT : 8; /* ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT */
2594  volatile uint32_t DATA_TIMEOUT : 24; /* ALT_SDMMC_TMOUT_DATA_TIMEOUT */
2595 };
2596 
2597 /* The typedef declaration for register ALT_SDMMC_TMOUT. */
2598 typedef struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
2599 #endif /* __ASSEMBLY__ */
2600 
2601 /* The reset value of the ALT_SDMMC_TMOUT register. */
2602 #define ALT_SDMMC_TMOUT_RESET 0xffffff40
2603 /* The byte offset of the ALT_SDMMC_TMOUT register from the beginning of the component. */
2604 #define ALT_SDMMC_TMOUT_OFST 0x14
2605 /* The address of the ALT_SDMMC_TMOUT register. */
2606 #define ALT_SDMMC_TMOUT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TMOUT_OFST))
2607 
2608 /*
2609  * Register : Card Type Register - CTYPE
2610  *
2611  * Card Type Register
2612  *
2613  * Register Layout
2614  *
2615  * Bits | Access | Reset | Description
2616  * :--------|:-------|:------|:-----------------------------
2617  * [0] | RW | 0x0 | ALT_SDMMC_CTYPE_CARD0_WIDTH2
2618  * [15:1] | ??? | 0x0 | *UNDEFINED*
2619  * [16] | RW | 0x0 | ALT_SDMMC_CTYPE_CARD0_WIDTH1
2620  * [31:17] | ??? | 0x0 | *UNDEFINED*
2621  *
2622  */
2623 /*
2624  * Field : CARD0_WIDTH2
2625  *
2626  * One bit per card indicates if card is 1-bit or 4-bit:
2627  *
2628  * 0-1-bit mode
2629  *
2630  * 1-4-bit mode
2631  *
2632  * Bit[15] corresponds to card[15], bit[0] corresponds to card[0].
2633  *
2634  * Only NUM_CARDS*2 number of bits are implemented.
2635  *
2636  * Field Enumeration Values:
2637  *
2638  * Enum | Value | Description
2639  * :----------------------------------------|:------|:------------
2640  * ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_ONE_BIT | 0x0 | 1-bit mode
2641  * ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_FOUR_BIT | 0x1 | 4-bit mode
2642  *
2643  * Field Access Macros:
2644  *
2645  */
2646 /*
2647  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD0_WIDTH2
2648  *
2649  * 1-bit mode
2650  */
2651 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_ONE_BIT 0x0
2652 /*
2653  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD0_WIDTH2
2654  *
2655  * 4-bit mode
2656  */
2657 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_FOUR_BIT 0x1
2658 
2659 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field. */
2660 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_LSB 0
2661 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field. */
2662 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_MSB 0
2663 /* The width in bits of the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field. */
2664 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_WIDTH 1
2665 /* The mask used to set the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field value. */
2666 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_SET_MSK 0x00000001
2667 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field value. */
2668 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_CLR_MSK 0xfffffffe
2669 /* The reset value of the ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field. */
2670 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_RESET 0x0
2671 /* Extracts the ALT_SDMMC_CTYPE_CARD0_WIDTH2 field value from a register. */
2672 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
2673 /* Produces a ALT_SDMMC_CTYPE_CARD0_WIDTH2 register field value suitable for setting the register. */
2674 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
2675 
2676 /*
2677  * Field : CARD0_WIDTH1
2678  *
2679  * One bit per card indicates if card is 8-bit:
2680  *
2681  * 0-Non 8-bit mode
2682  *
2683  * 1-8-bit mode
2684  *
2685  * Bit[31] corresponds to card[15]; bit[16] corresponds to card[0].
2686  *
2687  * Field Enumeration Values:
2688  *
2689  * Enum | Value | Description
2690  * :----------------------------------------|:------|:---------------
2691  * ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_NON_8BIT | 0x0 | Non 8-bit mode
2692  * ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_YES_8BIT | 0x1 | 8-bit mode
2693  *
2694  * Field Access Macros:
2695  *
2696  */
2697 /*
2698  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD0_WIDTH1
2699  *
2700  * Non 8-bit mode
2701  */
2702 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_NON_8BIT 0x0
2703 /*
2704  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD0_WIDTH1
2705  *
2706  * 8-bit mode
2707  */
2708 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_YES_8BIT 0x1
2709 
2710 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field. */
2711 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_LSB 16
2712 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field. */
2713 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_MSB 16
2714 /* The width in bits of the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field. */
2715 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_WIDTH 1
2716 /* The mask used to set the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field value. */
2717 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_SET_MSK 0x00010000
2718 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field value. */
2719 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_CLR_MSK 0xfffeffff
2720 /* The reset value of the ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field. */
2721 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_RESET 0x0
2722 /* Extracts the ALT_SDMMC_CTYPE_CARD0_WIDTH1 field value from a register. */
2723 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
2724 /* Produces a ALT_SDMMC_CTYPE_CARD0_WIDTH1 register field value suitable for setting the register. */
2725 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
2726 
2727 #ifndef __ASSEMBLY__
2728 /*
2729  * WARNING: The C register and register group struct declarations are provided for
2730  * convenience and illustrative purposes. They should, however, be used with
2731  * caution as the C language standard provides no guarantees about the alignment or
2732  * atomicity of device memory accesses. The recommended practice for coding device
2733  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2734  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2735  * alt_write_dword() functions for 64 bit registers.
2736  *
2737  * The struct declaration for register ALT_SDMMC_CTYPE.
2738  */
2739 struct ALT_SDMMC_CTYPE_s
2740 {
2741  volatile uint32_t CARD0_WIDTH2 : 1; /* ALT_SDMMC_CTYPE_CARD0_WIDTH2 */
2742  uint32_t : 15; /* *UNDEFINED* */
2743  volatile uint32_t CARD0_WIDTH1 : 1; /* ALT_SDMMC_CTYPE_CARD0_WIDTH1 */
2744  uint32_t : 15; /* *UNDEFINED* */
2745 };
2746 
2747 /* The typedef declaration for register ALT_SDMMC_CTYPE. */
2748 typedef struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
2749 #endif /* __ASSEMBLY__ */
2750 
2751 /* The reset value of the ALT_SDMMC_CTYPE register. */
2752 #define ALT_SDMMC_CTYPE_RESET 0x00000000
2753 /* The byte offset of the ALT_SDMMC_CTYPE register from the beginning of the component. */
2754 #define ALT_SDMMC_CTYPE_OFST 0x18
2755 /* The address of the ALT_SDMMC_CTYPE register. */
2756 #define ALT_SDMMC_CTYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CTYPE_OFST))
2757 
2758 /*
2759  * Register : Block Size Register - BLKSIZ
2760  *
2761  * Block Size Register
2762  *
2763  * Register Layout
2764  *
2765  * Bits | Access | Reset | Description
2766  * :--------|:-------|:------|:----------------------------
2767  * [15:0] | RW | 0x200 | ALT_SDMMC_BLKSIZ_BLOCK_SIZE
2768  * [31:16] | ??? | 0x0 | *UNDEFINED*
2769  *
2770  */
2771 /*
2772  * Field : BLOCK_SIZE
2773  *
2774  * Block size
2775  *
2776  * Field Access Macros:
2777  *
2778  */
2779 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
2780 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
2781 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
2782 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
2783 /* The width in bits of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
2784 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
2785 /* The mask used to set the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
2786 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
2787 /* The mask used to clear the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
2788 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
2789 /* The reset value of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
2790 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
2791 /* Extracts the ALT_SDMMC_BLKSIZ_BLOCK_SIZE field value from a register. */
2792 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
2793 /* Produces a ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value suitable for setting the register. */
2794 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
2795 
2796 #ifndef __ASSEMBLY__
2797 /*
2798  * WARNING: The C register and register group struct declarations are provided for
2799  * convenience and illustrative purposes. They should, however, be used with
2800  * caution as the C language standard provides no guarantees about the alignment or
2801  * atomicity of device memory accesses. The recommended practice for coding device
2802  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2803  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2804  * alt_write_dword() functions for 64 bit registers.
2805  *
2806  * The struct declaration for register ALT_SDMMC_BLKSIZ.
2807  */
2808 struct ALT_SDMMC_BLKSIZ_s
2809 {
2810  volatile uint32_t BLOCK_SIZE : 16; /* ALT_SDMMC_BLKSIZ_BLOCK_SIZE */
2811  uint32_t : 16; /* *UNDEFINED* */
2812 };
2813 
2814 /* The typedef declaration for register ALT_SDMMC_BLKSIZ. */
2815 typedef struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
2816 #endif /* __ASSEMBLY__ */
2817 
2818 /* The reset value of the ALT_SDMMC_BLKSIZ register. */
2819 #define ALT_SDMMC_BLKSIZ_RESET 0x00000200
2820 /* The byte offset of the ALT_SDMMC_BLKSIZ register from the beginning of the component. */
2821 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
2822 /* The address of the ALT_SDMMC_BLKSIZ register. */
2823 #define ALT_SDMMC_BLKSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BLKSIZ_OFST))
2824 
2825 /*
2826  * Register : Byte Count Register - BYTCNT
2827  *
2828  * Byte Count Register
2829  *
2830  * Register Layout
2831  *
2832  * Bits | Access | Reset | Description
2833  * :-------|:-------|:------|:----------------------------
2834  * [31:0] | RW | 0x200 | ALT_SDMMC_BYTCNT_BYTE_COUNT
2835  *
2836  */
2837 /*
2838  * Field : BYTE_COUNT
2839  *
2840  * Number of bytes to be transferred; should be integer multiple of Block Size for
2841  * block transfers.
2842  *
2843  * For undefined number of byte transfers, byte count should be set to 0. When byte
2844  * count is set to 0, it is responsibility of host to explicitly send stop/abort
2845  * command to terminate data transfer.
2846  *
2847  * Field Access Macros:
2848  *
2849  */
2850 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
2851 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
2852 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
2853 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
2854 /* The width in bits of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
2855 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
2856 /* The mask used to set the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
2857 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
2858 /* The mask used to clear the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
2859 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
2860 /* The reset value of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
2861 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
2862 /* Extracts the ALT_SDMMC_BYTCNT_BYTE_COUNT field value from a register. */
2863 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
2864 /* Produces a ALT_SDMMC_BYTCNT_BYTE_COUNT register field value suitable for setting the register. */
2865 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
2866 
2867 #ifndef __ASSEMBLY__
2868 /*
2869  * WARNING: The C register and register group struct declarations are provided for
2870  * convenience and illustrative purposes. They should, however, be used with
2871  * caution as the C language standard provides no guarantees about the alignment or
2872  * atomicity of device memory accesses. The recommended practice for coding device
2873  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2874  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2875  * alt_write_dword() functions for 64 bit registers.
2876  *
2877  * The struct declaration for register ALT_SDMMC_BYTCNT.
2878  */
2879 struct ALT_SDMMC_BYTCNT_s
2880 {
2881  volatile uint32_t BYTE_COUNT : 32; /* ALT_SDMMC_BYTCNT_BYTE_COUNT */
2882 };
2883 
2884 /* The typedef declaration for register ALT_SDMMC_BYTCNT. */
2885 typedef struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
2886 #endif /* __ASSEMBLY__ */
2887 
2888 /* The reset value of the ALT_SDMMC_BYTCNT register. */
2889 #define ALT_SDMMC_BYTCNT_RESET 0x00000200
2890 /* The byte offset of the ALT_SDMMC_BYTCNT register from the beginning of the component. */
2891 #define ALT_SDMMC_BYTCNT_OFST 0x20
2892 /* The address of the ALT_SDMMC_BYTCNT register. */
2893 #define ALT_SDMMC_BYTCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BYTCNT_OFST))
2894 
2895 /*
2896  * Register : Interrupt Mask Register - INTMASK
2897  *
2898  * Interrupt Mask Register
2899  *
2900  * Register Layout
2901  *
2902  * Bits | Access | Reset | Description
2903  * :-----|:-------|:------|:---------------------------------------
2904  * [0] | RW | 0x0 | ALT_SDMMC_INTMASK_CD_INT_MASK
2905  * [1] | RW | 0x0 | ALT_SDMMC_INTMASK_RE_INT_MASK
2906  * [2] | RW | 0x0 | ALT_SDMMC_INTMASK_CMD_INT_MASK
2907  * [3] | RW | 0x0 | ALT_SDMMC_INTMASK_DTO_INT_MASK
2908  * [4] | RW | 0x0 | ALT_SDMMC_INTMASK_TXDR_INT_MASK
2909  * [5] | RW | 0x0 | ALT_SDMMC_INTMASK_RXDR_INT_MASK
2910  * [6] | RW | 0x0 | ALT_SDMMC_INTMASK_RCRC_INT_MASK
2911  * [7] | RW | 0x0 | ALT_SDMMC_INTMASK_DCRC_INT_MASK
2912  * [8] | RW | 0x0 | ALT_SDMMC_INTMASK_RTO_INT_MASK
2913  * [9] | RW | 0x0 | ALT_SDMMC_INTMASK_DRTO_INT_MASK
2914  * [10] | RW | 0x0 | ALT_SDMMC_INTMASK_HTO_INT_MASK
2915  * [11] | RW | 0x0 | ALT_SDMMC_INTMASK_FRUN_INT_MASK
2916  * [12] | RW | 0x0 | ALT_SDMMC_INTMASK_HLE_INT_MASK
2917  * [13] | RW | 0x0 | ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK
2918  * [14] | RW | 0x0 | ALT_SDMMC_INTMASK_ACD_INT_MASK
2919  * [15] | RW | 0x0 | ALT_SDMMC_INTMASK_EBE_INT_MASK
2920  * [16] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0
2921  * [17] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1
2922  * [18] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2
2923  * [19] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3
2924  * [20] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4
2925  * [21] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5
2926  * [22] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6
2927  * [23] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7
2928  * [24] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8
2929  * [25] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9
2930  * [26] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10
2931  * [27] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11
2932  * [28] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12
2933  * [29] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13
2934  * [30] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14
2935  * [31] | RW | 0x0 | ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15
2936  *
2937  */
2938 /*
2939  * Field : CD_INT_MASK
2940  *
2941  * Card detect (CD) interrupt enable.
2942  *
2943  * Value of 0 masks interrupt; value of 1 enables interrupt.
2944  *
2945  * Field Enumeration Values:
2946  *
2947  * Enum | Value | Description
2948  * :----------------------------------------|:------|:------------------
2949  * ALT_SDMMC_INTMASK_CD_INT_MASK_E_MASKED | 0x0 | Masks interrupt
2950  * ALT_SDMMC_INTMASK_CD_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
2951  *
2952  * Field Access Macros:
2953  *
2954  */
2955 /*
2956  * Enumerated value for register field ALT_SDMMC_INTMASK_CD_INT_MASK
2957  *
2958  * Masks interrupt
2959  */
2960 #define ALT_SDMMC_INTMASK_CD_INT_MASK_E_MASKED 0x0
2961 /*
2962  * Enumerated value for register field ALT_SDMMC_INTMASK_CD_INT_MASK
2963  *
2964  * Enables interrupt
2965  */
2966 #define ALT_SDMMC_INTMASK_CD_INT_MASK_E_ENABLED 0x1
2967 
2968 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_CD_INT_MASK register field. */
2969 #define ALT_SDMMC_INTMASK_CD_INT_MASK_LSB 0
2970 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_CD_INT_MASK register field. */
2971 #define ALT_SDMMC_INTMASK_CD_INT_MASK_MSB 0
2972 /* The width in bits of the ALT_SDMMC_INTMASK_CD_INT_MASK register field. */
2973 #define ALT_SDMMC_INTMASK_CD_INT_MASK_WIDTH 1
2974 /* The mask used to set the ALT_SDMMC_INTMASK_CD_INT_MASK register field value. */
2975 #define ALT_SDMMC_INTMASK_CD_INT_MASK_SET_MSK 0x00000001
2976 /* The mask used to clear the ALT_SDMMC_INTMASK_CD_INT_MASK register field value. */
2977 #define ALT_SDMMC_INTMASK_CD_INT_MASK_CLR_MSK 0xfffffffe
2978 /* The reset value of the ALT_SDMMC_INTMASK_CD_INT_MASK register field. */
2979 #define ALT_SDMMC_INTMASK_CD_INT_MASK_RESET 0x0
2980 /* Extracts the ALT_SDMMC_INTMASK_CD_INT_MASK field value from a register. */
2981 #define ALT_SDMMC_INTMASK_CD_INT_MASK_GET(value) (((value) & 0x00000001) >> 0)
2982 /* Produces a ALT_SDMMC_INTMASK_CD_INT_MASK register field value suitable for setting the register. */
2983 #define ALT_SDMMC_INTMASK_CD_INT_MASK_SET(value) (((value) << 0) & 0x00000001)
2984 
2985 /*
2986  * Field : RE_INT_MASK
2987  *
2988  * Response error (RE) interrupt enable.
2989  *
2990  * Value of 0 masks interrupt; value of 1 enables interrupt.
2991  *
2992  * Field Enumeration Values:
2993  *
2994  * Enum | Value | Description
2995  * :----------------------------------------|:------|:------------------
2996  * ALT_SDMMC_INTMASK_RE_INT_MASK_E_MASKED | 0x0 | Masks interrupt
2997  * ALT_SDMMC_INTMASK_RE_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
2998  *
2999  * Field Access Macros:
3000  *
3001  */
3002 /*
3003  * Enumerated value for register field ALT_SDMMC_INTMASK_RE_INT_MASK
3004  *
3005  * Masks interrupt
3006  */
3007 #define ALT_SDMMC_INTMASK_RE_INT_MASK_E_MASKED 0x0
3008 /*
3009  * Enumerated value for register field ALT_SDMMC_INTMASK_RE_INT_MASK
3010  *
3011  * Enables interrupt
3012  */
3013 #define ALT_SDMMC_INTMASK_RE_INT_MASK_E_ENABLED 0x1
3014 
3015 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_RE_INT_MASK register field. */
3016 #define ALT_SDMMC_INTMASK_RE_INT_MASK_LSB 1
3017 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_RE_INT_MASK register field. */
3018 #define ALT_SDMMC_INTMASK_RE_INT_MASK_MSB 1
3019 /* The width in bits of the ALT_SDMMC_INTMASK_RE_INT_MASK register field. */
3020 #define ALT_SDMMC_INTMASK_RE_INT_MASK_WIDTH 1
3021 /* The mask used to set the ALT_SDMMC_INTMASK_RE_INT_MASK register field value. */
3022 #define ALT_SDMMC_INTMASK_RE_INT_MASK_SET_MSK 0x00000002
3023 /* The mask used to clear the ALT_SDMMC_INTMASK_RE_INT_MASK register field value. */
3024 #define ALT_SDMMC_INTMASK_RE_INT_MASK_CLR_MSK 0xfffffffd
3025 /* The reset value of the ALT_SDMMC_INTMASK_RE_INT_MASK register field. */
3026 #define ALT_SDMMC_INTMASK_RE_INT_MASK_RESET 0x0
3027 /* Extracts the ALT_SDMMC_INTMASK_RE_INT_MASK field value from a register. */
3028 #define ALT_SDMMC_INTMASK_RE_INT_MASK_GET(value) (((value) & 0x00000002) >> 1)
3029 /* Produces a ALT_SDMMC_INTMASK_RE_INT_MASK register field value suitable for setting the register. */
3030 #define ALT_SDMMC_INTMASK_RE_INT_MASK_SET(value) (((value) << 1) & 0x00000002)
3031 
3032 /*
3033  * Field : CMD_INT_MASK
3034  *
3035  * Command done (CD) interrupt enable
3036  *
3037  * Value of 0 masks interrupt; value of 1 enables interrupt.
3038  *
3039  * Field Enumeration Values:
3040  *
3041  * Enum | Value | Description
3042  * :-----------------------------------------|:------|:------------------
3043  * ALT_SDMMC_INTMASK_CMD_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3044  * ALT_SDMMC_INTMASK_CMD_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3045  *
3046  * Field Access Macros:
3047  *
3048  */
3049 /*
3050  * Enumerated value for register field ALT_SDMMC_INTMASK_CMD_INT_MASK
3051  *
3052  * Masks interrupt
3053  */
3054 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_E_MASKED 0x0
3055 /*
3056  * Enumerated value for register field ALT_SDMMC_INTMASK_CMD_INT_MASK
3057  *
3058  * Enables interrupt
3059  */
3060 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_E_ENABLED 0x1
3061 
3062 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_CMD_INT_MASK register field. */
3063 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_LSB 2
3064 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_CMD_INT_MASK register field. */
3065 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_MSB 2
3066 /* The width in bits of the ALT_SDMMC_INTMASK_CMD_INT_MASK register field. */
3067 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_WIDTH 1
3068 /* The mask used to set the ALT_SDMMC_INTMASK_CMD_INT_MASK register field value. */
3069 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_SET_MSK 0x00000004
3070 /* The mask used to clear the ALT_SDMMC_INTMASK_CMD_INT_MASK register field value. */
3071 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_CLR_MSK 0xfffffffb
3072 /* The reset value of the ALT_SDMMC_INTMASK_CMD_INT_MASK register field. */
3073 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_RESET 0x0
3074 /* Extracts the ALT_SDMMC_INTMASK_CMD_INT_MASK field value from a register. */
3075 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_GET(value) (((value) & 0x00000004) >> 2)
3076 /* Produces a ALT_SDMMC_INTMASK_CMD_INT_MASK register field value suitable for setting the register. */
3077 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_SET(value) (((value) << 2) & 0x00000004)
3078 
3079 /*
3080  * Field : DTO_INT_MASK
3081  *
3082  * Data transfer over (DTO) interrupt enable.
3083  *
3084  * Value of 0 masks interrupt; value of 1 enables interrupt.
3085  *
3086  * Field Enumeration Values:
3087  *
3088  * Enum | Value | Description
3089  * :-----------------------------------------|:------|:------------------
3090  * ALT_SDMMC_INTMASK_DTO_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3091  * ALT_SDMMC_INTMASK_DTO_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3092  *
3093  * Field Access Macros:
3094  *
3095  */
3096 /*
3097  * Enumerated value for register field ALT_SDMMC_INTMASK_DTO_INT_MASK
3098  *
3099  * Masks interrupt
3100  */
3101 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_E_MASKED 0x0
3102 /*
3103  * Enumerated value for register field ALT_SDMMC_INTMASK_DTO_INT_MASK
3104  *
3105  * Enables interrupt
3106  */
3107 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_E_ENABLED 0x1
3108 
3109 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_DTO_INT_MASK register field. */
3110 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_LSB 3
3111 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_DTO_INT_MASK register field. */
3112 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_MSB 3
3113 /* The width in bits of the ALT_SDMMC_INTMASK_DTO_INT_MASK register field. */
3114 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_WIDTH 1
3115 /* The mask used to set the ALT_SDMMC_INTMASK_DTO_INT_MASK register field value. */
3116 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_SET_MSK 0x00000008
3117 /* The mask used to clear the ALT_SDMMC_INTMASK_DTO_INT_MASK register field value. */
3118 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_CLR_MSK 0xfffffff7
3119 /* The reset value of the ALT_SDMMC_INTMASK_DTO_INT_MASK register field. */
3120 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_RESET 0x0
3121 /* Extracts the ALT_SDMMC_INTMASK_DTO_INT_MASK field value from a register. */
3122 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_GET(value) (((value) & 0x00000008) >> 3)
3123 /* Produces a ALT_SDMMC_INTMASK_DTO_INT_MASK register field value suitable for setting the register. */
3124 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_SET(value) (((value) << 3) & 0x00000008)
3125 
3126 /*
3127  * Field : TXDR_INT_MASK
3128  *
3129  * Transmit FIFO data request (TXDR) interrupt enable.
3130  *
3131  * Value of 0 masks interrupt; value of 1 enables interrupt.
3132  *
3133  * Field Enumeration Values:
3134  *
3135  * Enum | Value | Description
3136  * :------------------------------------------|:------|:------------------
3137  * ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3138  * ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3139  *
3140  * Field Access Macros:
3141  *
3142  */
3143 /*
3144  * Enumerated value for register field ALT_SDMMC_INTMASK_TXDR_INT_MASK
3145  *
3146  * Masks interrupt
3147  */
3148 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_MASKED 0x0
3149 /*
3150  * Enumerated value for register field ALT_SDMMC_INTMASK_TXDR_INT_MASK
3151  *
3152  * Enables interrupt
3153  */
3154 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_ENABLED 0x1
3155 
3156 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field. */
3157 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_LSB 4
3158 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field. */
3159 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_MSB 4
3160 /* The width in bits of the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field. */
3161 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_WIDTH 1
3162 /* The mask used to set the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field value. */
3163 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_SET_MSK 0x00000010
3164 /* The mask used to clear the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field value. */
3165 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_CLR_MSK 0xffffffef
3166 /* The reset value of the ALT_SDMMC_INTMASK_TXDR_INT_MASK register field. */
3167 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_RESET 0x0
3168 /* Extracts the ALT_SDMMC_INTMASK_TXDR_INT_MASK field value from a register. */
3169 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_GET(value) (((value) & 0x00000010) >> 4)
3170 /* Produces a ALT_SDMMC_INTMASK_TXDR_INT_MASK register field value suitable for setting the register. */
3171 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_SET(value) (((value) << 4) & 0x00000010)
3172 
3173 /*
3174  * Field : RXDR_INT_MASK
3175  *
3176  * Receive FIFO data request (RXDR) interrupt enable.
3177  *
3178  * Value of 0 masks interrupt; value of 1 enables interrupt.
3179  *
3180  * Field Enumeration Values:
3181  *
3182  * Enum | Value | Description
3183  * :------------------------------------------|:------|:------------------
3184  * ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3185  * ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3186  *
3187  * Field Access Macros:
3188  *
3189  */
3190 /*
3191  * Enumerated value for register field ALT_SDMMC_INTMASK_RXDR_INT_MASK
3192  *
3193  * Masks interrupt
3194  */
3195 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_MASKED 0x0
3196 /*
3197  * Enumerated value for register field ALT_SDMMC_INTMASK_RXDR_INT_MASK
3198  *
3199  * Enables interrupt
3200  */
3201 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_ENABLED 0x1
3202 
3203 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field. */
3204 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_LSB 5
3205 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field. */
3206 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_MSB 5
3207 /* The width in bits of the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field. */
3208 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_WIDTH 1
3209 /* The mask used to set the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field value. */
3210 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_SET_MSK 0x00000020
3211 /* The mask used to clear the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field value. */
3212 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_CLR_MSK 0xffffffdf
3213 /* The reset value of the ALT_SDMMC_INTMASK_RXDR_INT_MASK register field. */
3214 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_RESET 0x0
3215 /* Extracts the ALT_SDMMC_INTMASK_RXDR_INT_MASK field value from a register. */
3216 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_GET(value) (((value) & 0x00000020) >> 5)
3217 /* Produces a ALT_SDMMC_INTMASK_RXDR_INT_MASK register field value suitable for setting the register. */
3218 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_SET(value) (((value) << 5) & 0x00000020)
3219 
3220 /*
3221  * Field : RCRC_INT_MASK
3222  *
3223  * Response CRC error (RCRC) interrupt enable.
3224  *
3225  * Value of 0 masks interrupt; value of 1 enables interrupt.
3226  *
3227  * Field Enumeration Values:
3228  *
3229  * Enum | Value | Description
3230  * :------------------------------------------|:------|:------------------
3231  * ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3232  * ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3233  *
3234  * Field Access Macros:
3235  *
3236  */
3237 /*
3238  * Enumerated value for register field ALT_SDMMC_INTMASK_RCRC_INT_MASK
3239  *
3240  * Masks interrupt
3241  */
3242 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_MASKED 0x0
3243 /*
3244  * Enumerated value for register field ALT_SDMMC_INTMASK_RCRC_INT_MASK
3245  *
3246  * Enables interrupt
3247  */
3248 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_ENABLED 0x1
3249 
3250 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field. */
3251 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_LSB 6
3252 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field. */
3253 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_MSB 6
3254 /* The width in bits of the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field. */
3255 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_WIDTH 1
3256 /* The mask used to set the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field value. */
3257 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_SET_MSK 0x00000040
3258 /* The mask used to clear the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field value. */
3259 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_CLR_MSK 0xffffffbf
3260 /* The reset value of the ALT_SDMMC_INTMASK_RCRC_INT_MASK register field. */
3261 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_RESET 0x0
3262 /* Extracts the ALT_SDMMC_INTMASK_RCRC_INT_MASK field value from a register. */
3263 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_GET(value) (((value) & 0x00000040) >> 6)
3264 /* Produces a ALT_SDMMC_INTMASK_RCRC_INT_MASK register field value suitable for setting the register. */
3265 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_SET(value) (((value) << 6) & 0x00000040)
3266 
3267 /*
3268  * Field : DCRC_INT_MASK
3269  *
3270  * Data CRC error (DCRC) interrupt enable.
3271  *
3272  * Value of 0 masks interrupt; value of 1 enables interrupt.
3273  *
3274  * Field Enumeration Values:
3275  *
3276  * Enum | Value | Description
3277  * :------------------------------------------|:------|:------------------
3278  * ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3279  * ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3280  *
3281  * Field Access Macros:
3282  *
3283  */
3284 /*
3285  * Enumerated value for register field ALT_SDMMC_INTMASK_DCRC_INT_MASK
3286  *
3287  * Masks interrupt
3288  */
3289 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_MASKED 0x0
3290 /*
3291  * Enumerated value for register field ALT_SDMMC_INTMASK_DCRC_INT_MASK
3292  *
3293  * Enables interrupt
3294  */
3295 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_ENABLED 0x1
3296 
3297 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field. */
3298 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_LSB 7
3299 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field. */
3300 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_MSB 7
3301 /* The width in bits of the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field. */
3302 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_WIDTH 1
3303 /* The mask used to set the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field value. */
3304 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_SET_MSK 0x00000080
3305 /* The mask used to clear the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field value. */
3306 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_CLR_MSK 0xffffff7f
3307 /* The reset value of the ALT_SDMMC_INTMASK_DCRC_INT_MASK register field. */
3308 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_RESET 0x0
3309 /* Extracts the ALT_SDMMC_INTMASK_DCRC_INT_MASK field value from a register. */
3310 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_GET(value) (((value) & 0x00000080) >> 7)
3311 /* Produces a ALT_SDMMC_INTMASK_DCRC_INT_MASK register field value suitable for setting the register. */
3312 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_SET(value) (((value) << 7) & 0x00000080)
3313 
3314 /*
3315  * Field : RTO_INT_MASK
3316  *
3317  * Response timeout (RTO) interrupt enable.
3318  *
3319  * Value of 0 masks interrupt; value of 1 enables interrupt.
3320  *
3321  * Field Enumeration Values:
3322  *
3323  * Enum | Value | Description
3324  * :-----------------------------------------|:------|:------------------
3325  * ALT_SDMMC_INTMASK_RTO_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3326  * ALT_SDMMC_INTMASK_RTO_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3327  *
3328  * Field Access Macros:
3329  *
3330  */
3331 /*
3332  * Enumerated value for register field ALT_SDMMC_INTMASK_RTO_INT_MASK
3333  *
3334  * Masks interrupt
3335  */
3336 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_E_MASKED 0x0
3337 /*
3338  * Enumerated value for register field ALT_SDMMC_INTMASK_RTO_INT_MASK
3339  *
3340  * Enables interrupt
3341  */
3342 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_E_ENABLED 0x1
3343 
3344 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_RTO_INT_MASK register field. */
3345 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_LSB 8
3346 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_RTO_INT_MASK register field. */
3347 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_MSB 8
3348 /* The width in bits of the ALT_SDMMC_INTMASK_RTO_INT_MASK register field. */
3349 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_WIDTH 1
3350 /* The mask used to set the ALT_SDMMC_INTMASK_RTO_INT_MASK register field value. */
3351 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_SET_MSK 0x00000100
3352 /* The mask used to clear the ALT_SDMMC_INTMASK_RTO_INT_MASK register field value. */
3353 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_CLR_MSK 0xfffffeff
3354 /* The reset value of the ALT_SDMMC_INTMASK_RTO_INT_MASK register field. */
3355 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_RESET 0x0
3356 /* Extracts the ALT_SDMMC_INTMASK_RTO_INT_MASK field value from a register. */
3357 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_GET(value) (((value) & 0x00000100) >> 8)
3358 /* Produces a ALT_SDMMC_INTMASK_RTO_INT_MASK register field value suitable for setting the register. */
3359 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_SET(value) (((value) << 8) & 0x00000100)
3360 
3361 /*
3362  * Field : DRTO_INT_MASK
3363  *
3364  * Data read timeout (DRTO) interrupt enable.
3365  *
3366  * Value of 0 masks interrupt; value of 1 enables interrupt.
3367  *
3368  * Field Enumeration Values:
3369  *
3370  * Enum | Value | Description
3371  * :------------------------------------------|:------|:------------------
3372  * ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3373  * ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3374  *
3375  * Field Access Macros:
3376  *
3377  */
3378 /*
3379  * Enumerated value for register field ALT_SDMMC_INTMASK_DRTO_INT_MASK
3380  *
3381  * Masks interrupt
3382  */
3383 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_MASKED 0x0
3384 /*
3385  * Enumerated value for register field ALT_SDMMC_INTMASK_DRTO_INT_MASK
3386  *
3387  * Enables interrupt
3388  */
3389 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_ENABLED 0x1
3390 
3391 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field. */
3392 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_LSB 9
3393 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field. */
3394 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_MSB 9
3395 /* The width in bits of the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field. */
3396 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_WIDTH 1
3397 /* The mask used to set the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field value. */
3398 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_SET_MSK 0x00000200
3399 /* The mask used to clear the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field value. */
3400 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_CLR_MSK 0xfffffdff
3401 /* The reset value of the ALT_SDMMC_INTMASK_DRTO_INT_MASK register field. */
3402 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_RESET 0x0
3403 /* Extracts the ALT_SDMMC_INTMASK_DRTO_INT_MASK field value from a register. */
3404 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_GET(value) (((value) & 0x00000200) >> 9)
3405 /* Produces a ALT_SDMMC_INTMASK_DRTO_INT_MASK register field value suitable for setting the register. */
3406 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_SET(value) (((value) << 9) & 0x00000200)
3407 
3408 /*
3409  * Field : HTO_INT_MASK
3410  *
3411  * Data starvation-by-host timeout (HTO) /Volt_switch_int interrupt enable.
3412  *
3413  * Value of 0 masks interrupt; value of 1 enables interrupt.
3414  *
3415  * Field Enumeration Values:
3416  *
3417  * Enum | Value | Description
3418  * :-----------------------------------------|:------|:------------------
3419  * ALT_SDMMC_INTMASK_HTO_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3420  * ALT_SDMMC_INTMASK_HTO_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3421  *
3422  * Field Access Macros:
3423  *
3424  */
3425 /*
3426  * Enumerated value for register field ALT_SDMMC_INTMASK_HTO_INT_MASK
3427  *
3428  * Masks interrupt
3429  */
3430 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_E_MASKED 0x0
3431 /*
3432  * Enumerated value for register field ALT_SDMMC_INTMASK_HTO_INT_MASK
3433  *
3434  * Enables interrupt
3435  */
3436 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_E_ENABLED 0x1
3437 
3438 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_HTO_INT_MASK register field. */
3439 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_LSB 10
3440 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_HTO_INT_MASK register field. */
3441 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_MSB 10
3442 /* The width in bits of the ALT_SDMMC_INTMASK_HTO_INT_MASK register field. */
3443 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_WIDTH 1
3444 /* The mask used to set the ALT_SDMMC_INTMASK_HTO_INT_MASK register field value. */
3445 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_SET_MSK 0x00000400
3446 /* The mask used to clear the ALT_SDMMC_INTMASK_HTO_INT_MASK register field value. */
3447 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_CLR_MSK 0xfffffbff
3448 /* The reset value of the ALT_SDMMC_INTMASK_HTO_INT_MASK register field. */
3449 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_RESET 0x0
3450 /* Extracts the ALT_SDMMC_INTMASK_HTO_INT_MASK field value from a register. */
3451 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_GET(value) (((value) & 0x00000400) >> 10)
3452 /* Produces a ALT_SDMMC_INTMASK_HTO_INT_MASK register field value suitable for setting the register. */
3453 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_SET(value) (((value) << 10) & 0x00000400)
3454 
3455 /*
3456  * Field : FRUN_INT_MASK
3457  *
3458  * FIFO underrun/overrun error (FRUN) interrupt enable.
3459  *
3460  * Value of 0 masks interrupt; value of 1 enables interrupt.
3461  *
3462  * Field Enumeration Values:
3463  *
3464  * Enum | Value | Description
3465  * :------------------------------------------|:------|:------------------
3466  * ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3467  * ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3468  *
3469  * Field Access Macros:
3470  *
3471  */
3472 /*
3473  * Enumerated value for register field ALT_SDMMC_INTMASK_FRUN_INT_MASK
3474  *
3475  * Masks interrupt
3476  */
3477 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_MASKED 0x0
3478 /*
3479  * Enumerated value for register field ALT_SDMMC_INTMASK_FRUN_INT_MASK
3480  *
3481  * Enables interrupt
3482  */
3483 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_ENABLED 0x1
3484 
3485 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field. */
3486 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_LSB 11
3487 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field. */
3488 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_MSB 11
3489 /* The width in bits of the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field. */
3490 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_WIDTH 1
3491 /* The mask used to set the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field value. */
3492 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_SET_MSK 0x00000800
3493 /* The mask used to clear the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field value. */
3494 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_CLR_MSK 0xfffff7ff
3495 /* The reset value of the ALT_SDMMC_INTMASK_FRUN_INT_MASK register field. */
3496 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_RESET 0x0
3497 /* Extracts the ALT_SDMMC_INTMASK_FRUN_INT_MASK field value from a register. */
3498 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_GET(value) (((value) & 0x00000800) >> 11)
3499 /* Produces a ALT_SDMMC_INTMASK_FRUN_INT_MASK register field value suitable for setting the register. */
3500 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_SET(value) (((value) << 11) & 0x00000800)
3501 
3502 /*
3503  * Field : HLE_INT_MASK
3504  *
3505  * Hardware locked write error (HLE) interrupt enable.
3506  *
3507  * Value of 0 masks interrupt; value of 1 enables interrupt.
3508  *
3509  * Field Enumeration Values:
3510  *
3511  * Enum | Value | Description
3512  * :-----------------------------------------|:------|:------------------
3513  * ALT_SDMMC_INTMASK_HLE_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3514  * ALT_SDMMC_INTMASK_HLE_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3515  *
3516  * Field Access Macros:
3517  *
3518  */
3519 /*
3520  * Enumerated value for register field ALT_SDMMC_INTMASK_HLE_INT_MASK
3521  *
3522  * Masks interrupt
3523  */
3524 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_E_MASKED 0x0
3525 /*
3526  * Enumerated value for register field ALT_SDMMC_INTMASK_HLE_INT_MASK
3527  *
3528  * Enables interrupt
3529  */
3530 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_E_ENABLED 0x1
3531 
3532 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_HLE_INT_MASK register field. */
3533 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_LSB 12
3534 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_HLE_INT_MASK register field. */
3535 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_MSB 12
3536 /* The width in bits of the ALT_SDMMC_INTMASK_HLE_INT_MASK register field. */
3537 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_WIDTH 1
3538 /* The mask used to set the ALT_SDMMC_INTMASK_HLE_INT_MASK register field value. */
3539 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_SET_MSK 0x00001000
3540 /* The mask used to clear the ALT_SDMMC_INTMASK_HLE_INT_MASK register field value. */
3541 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_CLR_MSK 0xffffefff
3542 /* The reset value of the ALT_SDMMC_INTMASK_HLE_INT_MASK register field. */
3543 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_RESET 0x0
3544 /* Extracts the ALT_SDMMC_INTMASK_HLE_INT_MASK field value from a register. */
3545 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_GET(value) (((value) & 0x00001000) >> 12)
3546 /* Produces a ALT_SDMMC_INTMASK_HLE_INT_MASK register field value suitable for setting the register. */
3547 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_SET(value) (((value) << 12) & 0x00001000)
3548 
3549 /*
3550  * Field : SBE_BCI_INT_MASK
3551  *
3552  * Start Bit Error(SBE)/Busy Complete Interrupt (BCI) interrupt enable.
3553  *
3554  * Value of 0 masks interrupt; value of 1 enables interrupt.
3555  *
3556  * Field Enumeration Values:
3557  *
3558  * Enum | Value | Description
3559  * :---------------------------------------------|:------|:------------------
3560  * ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3561  * ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3562  *
3563  * Field Access Macros:
3564  *
3565  */
3566 /*
3567  * Enumerated value for register field ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK
3568  *
3569  * Masks interrupt
3570  */
3571 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_MASKED 0x0
3572 /*
3573  * Enumerated value for register field ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK
3574  *
3575  * Enables interrupt
3576  */
3577 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_ENABLED 0x1
3578 
3579 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field. */
3580 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_LSB 13
3581 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field. */
3582 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_MSB 13
3583 /* The width in bits of the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field. */
3584 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_WIDTH 1
3585 /* The mask used to set the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field value. */
3586 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_SET_MSK 0x00002000
3587 /* The mask used to clear the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field value. */
3588 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_CLR_MSK 0xffffdfff
3589 /* The reset value of the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field. */
3590 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_RESET 0x0
3591 /* Extracts the ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK field value from a register. */
3592 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_GET(value) (((value) & 0x00002000) >> 13)
3593 /* Produces a ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK register field value suitable for setting the register. */
3594 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_SET(value) (((value) << 13) & 0x00002000)
3595 
3596 /*
3597  * Field : ACD_INT_MASK
3598  *
3599  * Auto command done (ACD) interrupt enable.
3600  *
3601  * Value of 0 masks interrupt; value of 1 enables interrupt.
3602  *
3603  * Field Enumeration Values:
3604  *
3605  * Enum | Value | Description
3606  * :-----------------------------------------|:------|:------------------
3607  * ALT_SDMMC_INTMASK_ACD_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3608  * ALT_SDMMC_INTMASK_ACD_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3609  *
3610  * Field Access Macros:
3611  *
3612  */
3613 /*
3614  * Enumerated value for register field ALT_SDMMC_INTMASK_ACD_INT_MASK
3615  *
3616  * Masks interrupt
3617  */
3618 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_E_MASKED 0x0
3619 /*
3620  * Enumerated value for register field ALT_SDMMC_INTMASK_ACD_INT_MASK
3621  *
3622  * Enables interrupt
3623  */
3624 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_E_ENABLED 0x1
3625 
3626 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_ACD_INT_MASK register field. */
3627 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_LSB 14
3628 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_ACD_INT_MASK register field. */
3629 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_MSB 14
3630 /* The width in bits of the ALT_SDMMC_INTMASK_ACD_INT_MASK register field. */
3631 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_WIDTH 1
3632 /* The mask used to set the ALT_SDMMC_INTMASK_ACD_INT_MASK register field value. */
3633 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_SET_MSK 0x00004000
3634 /* The mask used to clear the ALT_SDMMC_INTMASK_ACD_INT_MASK register field value. */
3635 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_CLR_MSK 0xffffbfff
3636 /* The reset value of the ALT_SDMMC_INTMASK_ACD_INT_MASK register field. */
3637 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_RESET 0x0
3638 /* Extracts the ALT_SDMMC_INTMASK_ACD_INT_MASK field value from a register. */
3639 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_GET(value) (((value) & 0x00004000) >> 14)
3640 /* Produces a ALT_SDMMC_INTMASK_ACD_INT_MASK register field value suitable for setting the register. */
3641 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_SET(value) (((value) << 14) & 0x00004000)
3642 
3643 /*
3644  * Field : EBE_INT_MASK
3645  *
3646  * End-bit error (read)/Write no CRC (EBE) interrupt enable.
3647  *
3648  * Value of 0 masks interrupt; value of 1 enables interrupt.
3649  *
3650  * Field Enumeration Values:
3651  *
3652  * Enum | Value | Description
3653  * :-----------------------------------------|:------|:------------------
3654  * ALT_SDMMC_INTMASK_EBE_INT_MASK_E_MASKED | 0x0 | Masks interrupt
3655  * ALT_SDMMC_INTMASK_EBE_INT_MASK_E_ENABLED | 0x1 | Enables interrupt
3656  *
3657  * Field Access Macros:
3658  *
3659  */
3660 /*
3661  * Enumerated value for register field ALT_SDMMC_INTMASK_EBE_INT_MASK
3662  *
3663  * Masks interrupt
3664  */
3665 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_E_MASKED 0x0
3666 /*
3667  * Enumerated value for register field ALT_SDMMC_INTMASK_EBE_INT_MASK
3668  *
3669  * Enables interrupt
3670  */
3671 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_E_ENABLED 0x1
3672 
3673 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_EBE_INT_MASK register field. */
3674 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_LSB 15
3675 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_EBE_INT_MASK register field. */
3676 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_MSB 15
3677 /* The width in bits of the ALT_SDMMC_INTMASK_EBE_INT_MASK register field. */
3678 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_WIDTH 1
3679 /* The mask used to set the ALT_SDMMC_INTMASK_EBE_INT_MASK register field value. */
3680 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_SET_MSK 0x00008000
3681 /* The mask used to clear the ALT_SDMMC_INTMASK_EBE_INT_MASK register field value. */
3682 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_CLR_MSK 0xffff7fff
3683 /* The reset value of the ALT_SDMMC_INTMASK_EBE_INT_MASK register field. */
3684 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_RESET 0x0
3685 /* Extracts the ALT_SDMMC_INTMASK_EBE_INT_MASK field value from a register. */
3686 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_GET(value) (((value) & 0x00008000) >> 15)
3687 /* Produces a ALT_SDMMC_INTMASK_EBE_INT_MASK register field value suitable for setting the register. */
3688 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_SET(value) (((value) << 15) & 0x00008000)
3689 
3690 /*
3691  * Field : SDIO_INT_MASK_CARD0
3692  *
3693  * Mask SDIO interrupts
3694  *
3695  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3696  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3697  * masks an interrupt, and 1 enables an interrupt.
3698  *
3699  * In MMC-Ver3.3-only mode, these bits are always 0.
3700  *
3701  * Field Enumeration Values:
3702  *
3703  * Enum | Value | Description
3704  * :------------------------------------------------|:------|:------------------
3705  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_MASKED | 0x0 | Masks interrupt
3706  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_ENABLED | 0x1 | Enables interrupt
3707  *
3708  * Field Access Macros:
3709  *
3710  */
3711 /*
3712  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0
3713  *
3714  * Masks interrupt
3715  */
3716 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_MASKED 0x0
3717 /*
3718  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0
3719  *
3720  * Enables interrupt
3721  */
3722 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_ENABLED 0x1
3723 
3724 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field. */
3725 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_LSB 16
3726 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field. */
3727 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_MSB 16
3728 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field. */
3729 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_WIDTH 1
3730 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field value. */
3731 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_SET_MSK 0x00010000
3732 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field value. */
3733 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_CLR_MSK 0xfffeffff
3734 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field. */
3735 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_RESET 0x0
3736 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 field value from a register. */
3737 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_GET(value) (((value) & 0x00010000) >> 16)
3738 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 register field value suitable for setting the register. */
3739 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_SET(value) (((value) << 16) & 0x00010000)
3740 
3741 /*
3742  * Field : SDIO_INT_MASK_CARD1
3743  *
3744  * Mask SDIO interrupts
3745  *
3746  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3747  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3748  * masks an interrupt, and 1 enables an interrupt.
3749  *
3750  * In MMC-Ver3.3-only mode, these bits are always 0.
3751  *
3752  * Field Enumeration Values:
3753  *
3754  * Enum | Value | Description
3755  * :------------------------------------------------|:------|:------------------
3756  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_MASKED | 0x0 | Masks interrupt
3757  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_ENABLED | 0x1 | Enables interrupt
3758  *
3759  * Field Access Macros:
3760  *
3761  */
3762 /*
3763  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1
3764  *
3765  * Masks interrupt
3766  */
3767 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_MASKED 0x0
3768 /*
3769  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1
3770  *
3771  * Enables interrupt
3772  */
3773 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_ENABLED 0x1
3774 
3775 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field. */
3776 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_LSB 17
3777 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field. */
3778 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_MSB 17
3779 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field. */
3780 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_WIDTH 1
3781 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field value. */
3782 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_SET_MSK 0x00020000
3783 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field value. */
3784 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_CLR_MSK 0xfffdffff
3785 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field. */
3786 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_RESET 0x0
3787 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 field value from a register. */
3788 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_GET(value) (((value) & 0x00020000) >> 17)
3789 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 register field value suitable for setting the register. */
3790 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_SET(value) (((value) << 17) & 0x00020000)
3791 
3792 /*
3793  * Field : SDIO_INT_MASK_CARD2
3794  *
3795  * Mask SDIO interrupts
3796  *
3797  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3798  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3799  * masks an interrupt, and 1 enables an interrupt.
3800  *
3801  * In MMC-Ver3.3-only mode, these bits are always 0.
3802  *
3803  * Field Enumeration Values:
3804  *
3805  * Enum | Value | Description
3806  * :------------------------------------------------|:------|:------------------
3807  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_MASKED | 0x0 | Masks interrupt
3808  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_ENABLED | 0x1 | Enables interrupt
3809  *
3810  * Field Access Macros:
3811  *
3812  */
3813 /*
3814  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2
3815  *
3816  * Masks interrupt
3817  */
3818 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_MASKED 0x0
3819 /*
3820  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2
3821  *
3822  * Enables interrupt
3823  */
3824 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_ENABLED 0x1
3825 
3826 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field. */
3827 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_LSB 18
3828 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field. */
3829 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_MSB 18
3830 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field. */
3831 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_WIDTH 1
3832 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field value. */
3833 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_SET_MSK 0x00040000
3834 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field value. */
3835 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_CLR_MSK 0xfffbffff
3836 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field. */
3837 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_RESET 0x0
3838 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 field value from a register. */
3839 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_GET(value) (((value) & 0x00040000) >> 18)
3840 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 register field value suitable for setting the register. */
3841 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_SET(value) (((value) << 18) & 0x00040000)
3842 
3843 /*
3844  * Field : SDIO_INT_MASK_CARD3
3845  *
3846  * Mask SDIO interrupts
3847  *
3848  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3849  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3850  * masks an interrupt, and 1 enables an interrupt.
3851  *
3852  * In MMC-Ver3.3-only mode, these bits are always 0.
3853  *
3854  * Field Enumeration Values:
3855  *
3856  * Enum | Value | Description
3857  * :------------------------------------------------|:------|:------------------
3858  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_MASKED | 0x0 | Masks interrupt
3859  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_ENABLED | 0x1 | Enables interrupt
3860  *
3861  * Field Access Macros:
3862  *
3863  */
3864 /*
3865  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3
3866  *
3867  * Masks interrupt
3868  */
3869 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_MASKED 0x0
3870 /*
3871  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3
3872  *
3873  * Enables interrupt
3874  */
3875 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_ENABLED 0x1
3876 
3877 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field. */
3878 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_LSB 19
3879 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field. */
3880 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_MSB 19
3881 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field. */
3882 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_WIDTH 1
3883 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field value. */
3884 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_SET_MSK 0x00080000
3885 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field value. */
3886 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_CLR_MSK 0xfff7ffff
3887 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field. */
3888 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_RESET 0x0
3889 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 field value from a register. */
3890 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_GET(value) (((value) & 0x00080000) >> 19)
3891 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 register field value suitable for setting the register. */
3892 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_SET(value) (((value) << 19) & 0x00080000)
3893 
3894 /*
3895  * Field : SDIO_INT_MASK_CARD4
3896  *
3897  * Mask SDIO interrupts
3898  *
3899  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3900  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3901  * masks an interrupt, and 1 enables an interrupt.
3902  *
3903  * In MMC-Ver3.3-only mode, these bits are always 0.
3904  *
3905  * Field Enumeration Values:
3906  *
3907  * Enum | Value | Description
3908  * :------------------------------------------------|:------|:------------------
3909  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_MASKED | 0x0 | Masks interrupt
3910  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_ENABLED | 0x1 | Enables interrupt
3911  *
3912  * Field Access Macros:
3913  *
3914  */
3915 /*
3916  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4
3917  *
3918  * Masks interrupt
3919  */
3920 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_MASKED 0x0
3921 /*
3922  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4
3923  *
3924  * Enables interrupt
3925  */
3926 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_ENABLED 0x1
3927 
3928 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field. */
3929 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_LSB 20
3930 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field. */
3931 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_MSB 20
3932 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field. */
3933 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_WIDTH 1
3934 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field value. */
3935 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_SET_MSK 0x00100000
3936 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field value. */
3937 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_CLR_MSK 0xffefffff
3938 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field. */
3939 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_RESET 0x0
3940 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 field value from a register. */
3941 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_GET(value) (((value) & 0x00100000) >> 20)
3942 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 register field value suitable for setting the register. */
3943 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_SET(value) (((value) << 20) & 0x00100000)
3944 
3945 /*
3946  * Field : SDIO_INT_MASK_CARD5
3947  *
3948  * Mask SDIO interrupts
3949  *
3950  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
3951  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
3952  * masks an interrupt, and 1 enables an interrupt.
3953  *
3954  * In MMC-Ver3.3-only mode, these bits are always 0.
3955  *
3956  * Field Enumeration Values:
3957  *
3958  * Enum | Value | Description
3959  * :------------------------------------------------|:------|:------------------
3960  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_MASKED | 0x0 | Masks interrupt
3961  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_ENABLED | 0x1 | Enables interrupt
3962  *
3963  * Field Access Macros:
3964  *
3965  */
3966 /*
3967  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5
3968  *
3969  * Masks interrupt
3970  */
3971 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_MASKED 0x0
3972 /*
3973  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5
3974  *
3975  * Enables interrupt
3976  */
3977 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_ENABLED 0x1
3978 
3979 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field. */
3980 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_LSB 21
3981 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field. */
3982 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_MSB 21
3983 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field. */
3984 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_WIDTH 1
3985 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field value. */
3986 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_SET_MSK 0x00200000
3987 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field value. */
3988 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_CLR_MSK 0xffdfffff
3989 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field. */
3990 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_RESET 0x0
3991 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 field value from a register. */
3992 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_GET(value) (((value) & 0x00200000) >> 21)
3993 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 register field value suitable for setting the register. */
3994 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_SET(value) (((value) << 21) & 0x00200000)
3995 
3996 /*
3997  * Field : SDIO_INT_MASK_CARD6
3998  *
3999  * Mask SDIO interrupts
4000  *
4001  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4002  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4003  * masks an interrupt, and 1 enables an interrupt.
4004  *
4005  * In MMC-Ver3.3-only mode, these bits are always 0.
4006  *
4007  * Field Enumeration Values:
4008  *
4009  * Enum | Value | Description
4010  * :------------------------------------------------|:------|:------------------
4011  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_MASKED | 0x0 | Masks interrupt
4012  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_ENABLED | 0x1 | Enables interrupt
4013  *
4014  * Field Access Macros:
4015  *
4016  */
4017 /*
4018  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6
4019  *
4020  * Masks interrupt
4021  */
4022 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_MASKED 0x0
4023 /*
4024  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6
4025  *
4026  * Enables interrupt
4027  */
4028 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_ENABLED 0x1
4029 
4030 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field. */
4031 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_LSB 22
4032 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field. */
4033 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_MSB 22
4034 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field. */
4035 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_WIDTH 1
4036 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field value. */
4037 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_SET_MSK 0x00400000
4038 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field value. */
4039 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_CLR_MSK 0xffbfffff
4040 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field. */
4041 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_RESET 0x0
4042 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 field value from a register. */
4043 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_GET(value) (((value) & 0x00400000) >> 22)
4044 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 register field value suitable for setting the register. */
4045 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_SET(value) (((value) << 22) & 0x00400000)
4046 
4047 /*
4048  * Field : SDIO_INT_MASK_CARD7
4049  *
4050  * Mask SDIO interrupts
4051  *
4052  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4053  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4054  * masks an interrupt, and 1 enables an interrupt.
4055  *
4056  * In MMC-Ver3.3-only mode, these bits are always 0.
4057  *
4058  * Field Enumeration Values:
4059  *
4060  * Enum | Value | Description
4061  * :------------------------------------------------|:------|:------------------
4062  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_MASKED | 0x0 | Masks interrupt
4063  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_ENABLED | 0x1 | Enables interrupt
4064  *
4065  * Field Access Macros:
4066  *
4067  */
4068 /*
4069  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7
4070  *
4071  * Masks interrupt
4072  */
4073 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_MASKED 0x0
4074 /*
4075  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7
4076  *
4077  * Enables interrupt
4078  */
4079 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_ENABLED 0x1
4080 
4081 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field. */
4082 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_LSB 23
4083 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field. */
4084 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_MSB 23
4085 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field. */
4086 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_WIDTH 1
4087 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field value. */
4088 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_SET_MSK 0x00800000
4089 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field value. */
4090 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_CLR_MSK 0xff7fffff
4091 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field. */
4092 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_RESET 0x0
4093 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 field value from a register. */
4094 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_GET(value) (((value) & 0x00800000) >> 23)
4095 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 register field value suitable for setting the register. */
4096 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_SET(value) (((value) << 23) & 0x00800000)
4097 
4098 /*
4099  * Field : SDIO_INT_MASK_CARD8
4100  *
4101  * Mask SDIO interrupts
4102  *
4103  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4104  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4105  * masks an interrupt, and 1 enables an interrupt.
4106  *
4107  * In MMC-Ver3.3-only mode, these bits are always 0.
4108  *
4109  * Field Enumeration Values:
4110  *
4111  * Enum | Value | Description
4112  * :------------------------------------------------|:------|:------------------
4113  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_MASKED | 0x0 | Masks interrupt
4114  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_ENABLED | 0x1 | Enables interrupt
4115  *
4116  * Field Access Macros:
4117  *
4118  */
4119 /*
4120  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8
4121  *
4122  * Masks interrupt
4123  */
4124 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_MASKED 0x0
4125 /*
4126  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8
4127  *
4128  * Enables interrupt
4129  */
4130 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_ENABLED 0x1
4131 
4132 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field. */
4133 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_LSB 24
4134 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field. */
4135 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_MSB 24
4136 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field. */
4137 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_WIDTH 1
4138 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field value. */
4139 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_SET_MSK 0x01000000
4140 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field value. */
4141 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_CLR_MSK 0xfeffffff
4142 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field. */
4143 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_RESET 0x0
4144 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 field value from a register. */
4145 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_GET(value) (((value) & 0x01000000) >> 24)
4146 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 register field value suitable for setting the register. */
4147 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_SET(value) (((value) << 24) & 0x01000000)
4148 
4149 /*
4150  * Field : SDIO_INT_MASK_CARD9
4151  *
4152  * Mask SDIO interrupts
4153  *
4154  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4155  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4156  * masks an interrupt, and 1 enables an interrupt.
4157  *
4158  * In MMC-Ver3.3-only mode, these bits are always 0.
4159  *
4160  * Field Enumeration Values:
4161  *
4162  * Enum | Value | Description
4163  * :------------------------------------------------|:------|:------------------
4164  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_MASKED | 0x0 | Masks interrupt
4165  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_ENABLED | 0x1 | Enables interrupt
4166  *
4167  * Field Access Macros:
4168  *
4169  */
4170 /*
4171  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9
4172  *
4173  * Masks interrupt
4174  */
4175 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_MASKED 0x0
4176 /*
4177  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9
4178  *
4179  * Enables interrupt
4180  */
4181 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_ENABLED 0x1
4182 
4183 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field. */
4184 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_LSB 25
4185 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field. */
4186 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_MSB 25
4187 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field. */
4188 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_WIDTH 1
4189 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field value. */
4190 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_SET_MSK 0x02000000
4191 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field value. */
4192 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_CLR_MSK 0xfdffffff
4193 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field. */
4194 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_RESET 0x0
4195 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 field value from a register. */
4196 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_GET(value) (((value) & 0x02000000) >> 25)
4197 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 register field value suitable for setting the register. */
4198 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_SET(value) (((value) << 25) & 0x02000000)
4199 
4200 /*
4201  * Field : SDIO_INT_MASK_CARD10
4202  *
4203  * Mask SDIO interrupts
4204  *
4205  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4206  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4207  * masks an interrupt, and 1 enables an interrupt.
4208  *
4209  * In MMC-Ver3.3-only mode, these bits are always 0.
4210  *
4211  * Field Enumeration Values:
4212  *
4213  * Enum | Value | Description
4214  * :-------------------------------------------------|:------|:------------------
4215  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_MASKED | 0x0 | Masks interrupt
4216  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_ENABLED | 0x1 | Enables interrupt
4217  *
4218  * Field Access Macros:
4219  *
4220  */
4221 /*
4222  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10
4223  *
4224  * Masks interrupt
4225  */
4226 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_MASKED 0x0
4227 /*
4228  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10
4229  *
4230  * Enables interrupt
4231  */
4232 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_ENABLED 0x1
4233 
4234 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field. */
4235 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_LSB 26
4236 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field. */
4237 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_MSB 26
4238 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field. */
4239 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_WIDTH 1
4240 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field value. */
4241 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_SET_MSK 0x04000000
4242 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field value. */
4243 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_CLR_MSK 0xfbffffff
4244 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field. */
4245 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_RESET 0x0
4246 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 field value from a register. */
4247 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_GET(value) (((value) & 0x04000000) >> 26)
4248 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 register field value suitable for setting the register. */
4249 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_SET(value) (((value) << 26) & 0x04000000)
4250 
4251 /*
4252  * Field : SDIO_INT_MASK_CARD11
4253  *
4254  * Mask SDIO interrupts
4255  *
4256  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4257  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4258  * masks an interrupt, and 1 enables an interrupt.
4259  *
4260  * In MMC-Ver3.3-only mode, these bits are always 0.
4261  *
4262  * Field Enumeration Values:
4263  *
4264  * Enum | Value | Description
4265  * :-------------------------------------------------|:------|:------------------
4266  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_MASKED | 0x0 | Masks interrupt
4267  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_ENABLED | 0x1 | Enables interrupt
4268  *
4269  * Field Access Macros:
4270  *
4271  */
4272 /*
4273  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11
4274  *
4275  * Masks interrupt
4276  */
4277 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_MASKED 0x0
4278 /*
4279  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11
4280  *
4281  * Enables interrupt
4282  */
4283 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_ENABLED 0x1
4284 
4285 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field. */
4286 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_LSB 27
4287 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field. */
4288 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_MSB 27
4289 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field. */
4290 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_WIDTH 1
4291 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field value. */
4292 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_SET_MSK 0x08000000
4293 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field value. */
4294 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_CLR_MSK 0xf7ffffff
4295 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field. */
4296 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_RESET 0x0
4297 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 field value from a register. */
4298 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_GET(value) (((value) & 0x08000000) >> 27)
4299 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 register field value suitable for setting the register. */
4300 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_SET(value) (((value) << 27) & 0x08000000)
4301 
4302 /*
4303  * Field : SDIO_INT_MASK_CARD12
4304  *
4305  * Mask SDIO interrupts
4306  *
4307  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4308  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4309  * masks an interrupt, and 1 enables an interrupt.
4310  *
4311  * In MMC-Ver3.3-only mode, these bits are always 0.
4312  *
4313  * Field Enumeration Values:
4314  *
4315  * Enum | Value | Description
4316  * :-------------------------------------------------|:------|:------------------
4317  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_MASKED | 0x0 | Masks interrupt
4318  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_ENABLED | 0x1 | Enables interrupt
4319  *
4320  * Field Access Macros:
4321  *
4322  */
4323 /*
4324  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12
4325  *
4326  * Masks interrupt
4327  */
4328 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_MASKED 0x0
4329 /*
4330  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12
4331  *
4332  * Enables interrupt
4333  */
4334 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_ENABLED 0x1
4335 
4336 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field. */
4337 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_LSB 28
4338 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field. */
4339 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_MSB 28
4340 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field. */
4341 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_WIDTH 1
4342 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field value. */
4343 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_SET_MSK 0x10000000
4344 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field value. */
4345 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_CLR_MSK 0xefffffff
4346 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field. */
4347 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_RESET 0x0
4348 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 field value from a register. */
4349 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_GET(value) (((value) & 0x10000000) >> 28)
4350 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 register field value suitable for setting the register. */
4351 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_SET(value) (((value) << 28) & 0x10000000)
4352 
4353 /*
4354  * Field : SDIO_INT_MASK_CARD13
4355  *
4356  * Mask SDIO interrupts
4357  *
4358  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4359  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4360  * masks an interrupt, and 1 enables an interrupt.
4361  *
4362  * In MMC-Ver3.3-only mode, these bits are always 0.
4363  *
4364  * Field Enumeration Values:
4365  *
4366  * Enum | Value | Description
4367  * :-------------------------------------------------|:------|:------------------
4368  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_MASKED | 0x0 | Masks interrupt
4369  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_ENABLED | 0x1 | Enables interrupt
4370  *
4371  * Field Access Macros:
4372  *
4373  */
4374 /*
4375  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13
4376  *
4377  * Masks interrupt
4378  */
4379 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_MASKED 0x0
4380 /*
4381  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13
4382  *
4383  * Enables interrupt
4384  */
4385 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_ENABLED 0x1
4386 
4387 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field. */
4388 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_LSB 29
4389 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field. */
4390 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_MSB 29
4391 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field. */
4392 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_WIDTH 1
4393 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field value. */
4394 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_SET_MSK 0x20000000
4395 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field value. */
4396 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_CLR_MSK 0xdfffffff
4397 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field. */
4398 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_RESET 0x0
4399 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 field value from a register. */
4400 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_GET(value) (((value) & 0x20000000) >> 29)
4401 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 register field value suitable for setting the register. */
4402 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_SET(value) (((value) << 29) & 0x20000000)
4403 
4404 /*
4405  * Field : SDIO_INT_MASK_CARD14
4406  *
4407  * Mask SDIO interrupts
4408  *
4409  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4410  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4411  * masks an interrupt, and 1 enables an interrupt.
4412  *
4413  * In MMC-Ver3.3-only mode, these bits are always 0.
4414  *
4415  * Field Enumeration Values:
4416  *
4417  * Enum | Value | Description
4418  * :-------------------------------------------------|:------|:------------------
4419  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_MASKED | 0x0 | Masks interrupt
4420  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_ENABLED | 0x1 | Enables interrupt
4421  *
4422  * Field Access Macros:
4423  *
4424  */
4425 /*
4426  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14
4427  *
4428  * Masks interrupt
4429  */
4430 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_MASKED 0x0
4431 /*
4432  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14
4433  *
4434  * Enables interrupt
4435  */
4436 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_ENABLED 0x1
4437 
4438 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field. */
4439 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_LSB 30
4440 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field. */
4441 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_MSB 30
4442 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field. */
4443 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_WIDTH 1
4444 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field value. */
4445 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_SET_MSK 0x40000000
4446 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field value. */
4447 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_CLR_MSK 0xbfffffff
4448 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field. */
4449 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_RESET 0x0
4450 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 field value from a register. */
4451 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_GET(value) (((value) & 0x40000000) >> 30)
4452 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 register field value suitable for setting the register. */
4453 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_SET(value) (((value) << 30) & 0x40000000)
4454 
4455 /*
4456  * Field : SDIO_INT_MASK_CARD15
4457  *
4458  * Mask SDIO interrupts
4459  *
4460  * One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds
4461  * to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0
4462  * masks an interrupt, and 1 enables an interrupt.
4463  *
4464  * In MMC-Ver3.3-only mode, these bits are always 0.
4465  *
4466  * Field Enumeration Values:
4467  *
4468  * Enum | Value | Description
4469  * :-------------------------------------------------|:------|:------------------
4470  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_MASKED | 0x0 | Masks interrupt
4471  * ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_ENABLED | 0x1 | Enables interrupt
4472  *
4473  * Field Access Macros:
4474  *
4475  */
4476 /*
4477  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15
4478  *
4479  * Masks interrupt
4480  */
4481 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_MASKED 0x0
4482 /*
4483  * Enumerated value for register field ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15
4484  *
4485  * Enables interrupt
4486  */
4487 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_ENABLED 0x1
4488 
4489 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field. */
4490 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_LSB 31
4491 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field. */
4492 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_MSB 31
4493 /* The width in bits of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field. */
4494 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_WIDTH 1
4495 /* The mask used to set the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field value. */
4496 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_SET_MSK 0x80000000
4497 /* The mask used to clear the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field value. */
4498 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_CLR_MSK 0x7fffffff
4499 /* The reset value of the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field. */
4500 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_RESET 0x0
4501 /* Extracts the ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 field value from a register. */
4502 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_GET(value) (((value) & 0x80000000) >> 31)
4503 /* Produces a ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 register field value suitable for setting the register. */
4504 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_SET(value) (((value) << 31) & 0x80000000)
4505 
4506 #ifndef __ASSEMBLY__
4507 /*
4508  * WARNING: The C register and register group struct declarations are provided for
4509  * convenience and illustrative purposes. They should, however, be used with
4510  * caution as the C language standard provides no guarantees about the alignment or
4511  * atomicity of device memory accesses. The recommended practice for coding device
4512  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4513  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4514  * alt_write_dword() functions for 64 bit registers.
4515  *
4516  * The struct declaration for register ALT_SDMMC_INTMASK.
4517  */
4518 struct ALT_SDMMC_INTMASK_s
4519 {
4520  volatile uint32_t CD_INT_MASK : 1; /* ALT_SDMMC_INTMASK_CD_INT_MASK */
4521  volatile uint32_t RE_INT_MASK : 1; /* ALT_SDMMC_INTMASK_RE_INT_MASK */
4522  volatile uint32_t CMD_INT_MASK : 1; /* ALT_SDMMC_INTMASK_CMD_INT_MASK */
4523  volatile uint32_t DTO_INT_MASK : 1; /* ALT_SDMMC_INTMASK_DTO_INT_MASK */
4524  volatile uint32_t TXDR_INT_MASK : 1; /* ALT_SDMMC_INTMASK_TXDR_INT_MASK */
4525  volatile uint32_t RXDR_INT_MASK : 1; /* ALT_SDMMC_INTMASK_RXDR_INT_MASK */
4526  volatile uint32_t RCRC_INT_MASK : 1; /* ALT_SDMMC_INTMASK_RCRC_INT_MASK */
4527  volatile uint32_t DCRC_INT_MASK : 1; /* ALT_SDMMC_INTMASK_DCRC_INT_MASK */
4528  volatile uint32_t RTO_INT_MASK : 1; /* ALT_SDMMC_INTMASK_RTO_INT_MASK */
4529  volatile uint32_t DRTO_INT_MASK : 1; /* ALT_SDMMC_INTMASK_DRTO_INT_MASK */
4530  volatile uint32_t HTO_INT_MASK : 1; /* ALT_SDMMC_INTMASK_HTO_INT_MASK */
4531  volatile uint32_t FRUN_INT_MASK : 1; /* ALT_SDMMC_INTMASK_FRUN_INT_MASK */
4532  volatile uint32_t HLE_INT_MASK : 1; /* ALT_SDMMC_INTMASK_HLE_INT_MASK */
4533  volatile uint32_t SBE_BCI_INT_MASK : 1; /* ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK */
4534  volatile uint32_t ACD_INT_MASK : 1; /* ALT_SDMMC_INTMASK_ACD_INT_MASK */
4535  volatile uint32_t EBE_INT_MASK : 1; /* ALT_SDMMC_INTMASK_EBE_INT_MASK */
4536  volatile uint32_t SDIO_INT_MASK_CARD0 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0 */
4537  volatile uint32_t SDIO_INT_MASK_CARD1 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1 */
4538  volatile uint32_t SDIO_INT_MASK_CARD2 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2 */
4539  volatile uint32_t SDIO_INT_MASK_CARD3 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3 */
4540  volatile uint32_t SDIO_INT_MASK_CARD4 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4 */
4541  volatile uint32_t SDIO_INT_MASK_CARD5 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5 */
4542  volatile uint32_t SDIO_INT_MASK_CARD6 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6 */
4543  volatile uint32_t SDIO_INT_MASK_CARD7 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7 */
4544  volatile uint32_t SDIO_INT_MASK_CARD8 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8 */
4545  volatile uint32_t SDIO_INT_MASK_CARD9 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9 */
4546  volatile uint32_t SDIO_INT_MASK_CARD10 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10 */
4547  volatile uint32_t SDIO_INT_MASK_CARD11 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11 */
4548  volatile uint32_t SDIO_INT_MASK_CARD12 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12 */
4549  volatile uint32_t SDIO_INT_MASK_CARD13 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13 */
4550  volatile uint32_t SDIO_INT_MASK_CARD14 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14 */
4551  volatile uint32_t SDIO_INT_MASK_CARD15 : 1; /* ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15 */
4552 };
4553 
4554 /* The typedef declaration for register ALT_SDMMC_INTMASK. */
4555 typedef struct ALT_SDMMC_INTMASK_s ALT_SDMMC_INTMASK_t;
4556 #endif /* __ASSEMBLY__ */
4557 
4558 /* The reset value of the ALT_SDMMC_INTMASK register. */
4559 #define ALT_SDMMC_INTMASK_RESET 0x00000000
4560 /* The byte offset of the ALT_SDMMC_INTMASK register from the beginning of the component. */
4561 #define ALT_SDMMC_INTMASK_OFST 0x24
4562 /* The address of the ALT_SDMMC_INTMASK register. */
4563 #define ALT_SDMMC_INTMASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_INTMASK_OFST))
4564 
4565 /*
4566  * Register : Command Argument Register - CMDARG
4567  *
4568  * Command Argument Register
4569  *
4570  * Register Layout
4571  *
4572  * Bits | Access | Reset | Description
4573  * :-------|:-------|:------|:-------------------------
4574  * [31:0] | RW | 0x0 | ALT_SDMMC_CMDARG_CMD_ARG
4575  *
4576  */
4577 /*
4578  * Field : CMD_ARG
4579  *
4580  * Value indicates command argument to be passed to card
4581  *
4582  * Field Access Macros:
4583  *
4584  */
4585 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
4586 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
4587 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
4588 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
4589 /* The width in bits of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
4590 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
4591 /* The mask used to set the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
4592 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
4593 /* The mask used to clear the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
4594 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
4595 /* The reset value of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
4596 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
4597 /* Extracts the ALT_SDMMC_CMDARG_CMD_ARG field value from a register. */
4598 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
4599 /* Produces a ALT_SDMMC_CMDARG_CMD_ARG register field value suitable for setting the register. */
4600 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
4601 
4602 #ifndef __ASSEMBLY__
4603 /*
4604  * WARNING: The C register and register group struct declarations are provided for
4605  * convenience and illustrative purposes. They should, however, be used with
4606  * caution as the C language standard provides no guarantees about the alignment or
4607  * atomicity of device memory accesses. The recommended practice for coding device
4608  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4609  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4610  * alt_write_dword() functions for 64 bit registers.
4611  *
4612  * The struct declaration for register ALT_SDMMC_CMDARG.
4613  */
4614 struct ALT_SDMMC_CMDARG_s
4615 {
4616  volatile uint32_t CMD_ARG : 32; /* ALT_SDMMC_CMDARG_CMD_ARG */
4617 };
4618 
4619 /* The typedef declaration for register ALT_SDMMC_CMDARG. */
4620 typedef struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
4621 #endif /* __ASSEMBLY__ */
4622 
4623 /* The reset value of the ALT_SDMMC_CMDARG register. */
4624 #define ALT_SDMMC_CMDARG_RESET 0x00000000
4625 /* The byte offset of the ALT_SDMMC_CMDARG register from the beginning of the component. */
4626 #define ALT_SDMMC_CMDARG_OFST 0x28
4627 /* The address of the ALT_SDMMC_CMDARG register. */
4628 #define ALT_SDMMC_CMDARG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CMDARG_OFST))
4629 
4630 /*
4631  * Register : Command Register - CMD
4632  *
4633  * Command Register
4634  *
4635  * Register Layout
4636  *
4637  * Bits | Access | Reset | Description
4638  * :--------|:-------|:------|:------------------------------------------
4639  * [5:0] | RW | 0x0 | ALT_SDMMC_CMD_CMD_INDEX
4640  * [6] | RW | 0x0 | ALT_SDMMC_CMD_RESPONSE_EXPECT
4641  * [7] | RW | 0x0 | ALT_SDMMC_CMD_RESPONSE_LENGTH
4642  * [8] | RW | 0x0 | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
4643  * [9] | RW | 0x0 | ALT_SDMMC_CMD_DATA_EXPECTED
4644  * [10] | RW | 0x0 | ALT_SDMMC_CMD_READ_WRITE
4645  * [11] | RW | 0x0 | ALT_SDMMC_CMD_TRANSFER_MODE
4646  * [12] | RW | 0x0 | ALT_SDMMC_CMD_SEND_AUTO_STOP
4647  * [13] | RW | 0x0 | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
4648  * [14] | RW | 0x0 | ALT_SDMMC_CMD_STOP_ABORT_CMD
4649  * [15] | RW | 0x0 | ALT_SDMMC_CMD_SEND_INITIALIZATION
4650  * [20:16] | RW | 0x0 | ALT_SDMMC_CMD_CARD_NUMBER
4651  * [21] | RW | 0x0 | ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY
4652  * [22] | RW | 0x0 | ALT_SDMMC_CMD_READ_CEATA_DEVICE
4653  * [23] | RW | 0x0 | ALT_SDMMC_CMD_CCS_EXPECTED
4654  * [24] | RW | 0x0 | ALT_SDMMC_CMD_ENABLE_BOOT
4655  * [25] | RW | 0x0 | ALT_SDMMC_CMD_EXPECT_BOOT_ACK
4656  * [26] | RW | 0x0 | ALT_SDMMC_CMD_DISABLE_BOOT
4657  * [27] | RW | 0x0 | ALT_SDMMC_CMD_BOOT_MODE
4658  * [28] | RW | 0x0 | ALT_SDMMC_CMD_VOLT_SWITCH
4659  * [29] | RW | 0x1 | ALT_SDMMC_CMD_USE_HOLD_REG
4660  * [30] | ??? | 0x0 | *UNDEFINED*
4661  * [31] | RW | 0x0 | ALT_SDMMC_CMD_START_CMD
4662  *
4663  */
4664 /*
4665  * Field : CMD_INDEX
4666  *
4667  * Command index
4668  *
4669  * Field Access Macros:
4670  *
4671  */
4672 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
4673 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
4674 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
4675 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
4676 /* The width in bits of the ALT_SDMMC_CMD_CMD_INDEX register field. */
4677 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
4678 /* The mask used to set the ALT_SDMMC_CMD_CMD_INDEX register field value. */
4679 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
4680 /* The mask used to clear the ALT_SDMMC_CMD_CMD_INDEX register field value. */
4681 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
4682 /* The reset value of the ALT_SDMMC_CMD_CMD_INDEX register field. */
4683 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
4684 /* Extracts the ALT_SDMMC_CMD_CMD_INDEX field value from a register. */
4685 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
4686 /* Produces a ALT_SDMMC_CMD_CMD_INDEX register field value suitable for setting the register. */
4687 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
4688 
4689 /*
4690  * Field : RESPONSE_EXPECT
4691  *
4692  * 0-No response expected from card
4693  *
4694  * 1-Response expected from card
4695  *
4696  * Field Enumeration Values:
4697  *
4698  * Enum | Value | Description
4699  * :-----------------------------------------|:------|:-------------------------------
4700  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NO_RESP | 0x0 | No response expected from card
4701  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP_EXP | 0x1 | Response expected from card
4702  *
4703  * Field Access Macros:
4704  *
4705  */
4706 /*
4707  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
4708  *
4709  * No response expected from card
4710  */
4711 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NO_RESP 0x0
4712 /*
4713  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
4714  *
4715  * Response expected from card
4716  */
4717 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP_EXP 0x1
4718 
4719 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
4720 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
4721 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
4722 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
4723 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
4724 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
4725 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
4726 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
4727 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
4728 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
4729 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
4730 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
4731 /* Extracts the ALT_SDMMC_CMD_RESPONSE_EXPECT field value from a register. */
4732 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
4733 /* Produces a ALT_SDMMC_CMD_RESPONSE_EXPECT register field value suitable for setting the register. */
4734 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
4735 
4736 /*
4737  * Field : RESPONSE_LENGTH
4738  *
4739  * 0-Short response expected from card
4740  *
4741  * 1-Long response expected from card
4742  *
4743  * Field Enumeration Values:
4744  *
4745  * Enum | Value | Description
4746  * :-------------------------------------------|:------|:---------------
4747  * ALT_SDMMC_CMD_RESPONSE_LENGTH_E_SHORT_RESP | 0x0 | Short response
4748  * ALT_SDMMC_CMD_RESPONSE_LENGTH_E_LONG_RESP | 0x1 | Long response
4749  *
4750  * Field Access Macros:
4751  *
4752  */
4753 /*
4754  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LENGTH
4755  *
4756  * Short response
4757  */
4758 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_E_SHORT_RESP 0x0
4759 /*
4760  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LENGTH
4761  *
4762  * Long response
4763  */
4764 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_E_LONG_RESP 0x1
4765 
4766 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_LENGTH register field. */
4767 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_LSB 7
4768 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_LENGTH register field. */
4769 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_MSB 7
4770 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_LENGTH register field. */
4771 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_WIDTH 1
4772 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_LENGTH register field value. */
4773 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_SET_MSK 0x00000080
4774 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_LENGTH register field value. */
4775 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_CLR_MSK 0xffffff7f
4776 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_LENGTH register field. */
4777 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_RESET 0x0
4778 /* Extracts the ALT_SDMMC_CMD_RESPONSE_LENGTH field value from a register. */
4779 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_GET(value) (((value) & 0x00000080) >> 7)
4780 /* Produces a ALT_SDMMC_CMD_RESPONSE_LENGTH register field value suitable for setting the register. */
4781 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_SET(value) (((value) << 7) & 0x00000080)
4782 
4783 /*
4784  * Field : CHECK_RESPONSE_CRC
4785  *
4786  * 0-Do not check response CRC
4787  *
4788  * 1-Check response CRC
4789  *
4790  * Some of command responses do not return valid CRC bits. Software should disable
4791  * CRC checks for those commands in order to disable CRC checking by controller.
4792  *
4793  * Field Enumeration Values:
4794  *
4795  * Enum | Value | Description
4796  * :-----------------------------------------|:------|:--------------------------
4797  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_FALSE | 0x0 | Do not check response CRC
4798  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_TRUE | 0x1 | Check response CRC
4799  *
4800  * Field Access Macros:
4801  *
4802  */
4803 /*
4804  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
4805  *
4806  * Do not check response CRC
4807  */
4808 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_FALSE 0x0
4809 /*
4810  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
4811  *
4812  * Check response CRC
4813  */
4814 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_TRUE 0x1
4815 
4816 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
4817 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
4818 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
4819 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
4820 /* The width in bits of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
4821 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
4822 /* The mask used to set the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
4823 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
4824 /* The mask used to clear the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
4825 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
4826 /* The reset value of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
4827 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
4828 /* Extracts the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC field value from a register. */
4829 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
4830 /* Produces a ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value suitable for setting the register. */
4831 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
4832 
4833 /*
4834  * Field : DATA_EXPECTED
4835  *
4836  * 0-No data transfer expected (read/write)
4837  *
4838  * 1-Data transfer expected (read/write)
4839  *
4840  * Field Enumeration Values:
4841  *
4842  * Enum | Value | Description
4843  * :------------------------------------|:------|:--------------------------
4844  * ALT_SDMMC_CMD_DATA_EXPECTED_E_FALSE | 0x0 | No data transfer expected
4845  * ALT_SDMMC_CMD_DATA_EXPECTED_E_TRUE | 0x1 | Data transfer expected
4846  *
4847  * Field Access Macros:
4848  *
4849  */
4850 /*
4851  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
4852  *
4853  * No data transfer expected
4854  */
4855 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_FALSE 0x0
4856 /*
4857  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
4858  *
4859  * Data transfer expected
4860  */
4861 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_TRUE 0x1
4862 
4863 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
4864 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
4865 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
4866 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
4867 /* The width in bits of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
4868 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
4869 /* The mask used to set the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
4870 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
4871 /* The mask used to clear the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
4872 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
4873 /* The reset value of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
4874 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
4875 /* Extracts the ALT_SDMMC_CMD_DATA_EXPECTED field value from a register. */
4876 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
4877 /* Produces a ALT_SDMMC_CMD_DATA_EXPECTED register field value suitable for setting the register. */
4878 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
4879 
4880 /*
4881  * Field : READ_WRITE
4882  *
4883  * 0-Read from card
4884  *
4885  * 1-Write to card
4886  *
4887  * Don't care if no data expected from card.
4888  *
4889  * Field Enumeration Values:
4890  *
4891  * Enum | Value | Description
4892  * :---------------------------------|:------|:---------------
4893  * ALT_SDMMC_CMD_READ_WRITE_E_READ | 0x0 | Read from card
4894  * ALT_SDMMC_CMD_READ_WRITE_E_WRITE | 0x1 | Write to card
4895  *
4896  * Field Access Macros:
4897  *
4898  */
4899 /*
4900  * Enumerated value for register field ALT_SDMMC_CMD_READ_WRITE
4901  *
4902  * Read from card
4903  */
4904 #define ALT_SDMMC_CMD_READ_WRITE_E_READ 0x0
4905 /*
4906  * Enumerated value for register field ALT_SDMMC_CMD_READ_WRITE
4907  *
4908  * Write to card
4909  */
4910 #define ALT_SDMMC_CMD_READ_WRITE_E_WRITE 0x1
4911 
4912 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_READ_WRITE register field. */
4913 #define ALT_SDMMC_CMD_READ_WRITE_LSB 10
4914 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_READ_WRITE register field. */
4915 #define ALT_SDMMC_CMD_READ_WRITE_MSB 10
4916 /* The width in bits of the ALT_SDMMC_CMD_READ_WRITE register field. */
4917 #define ALT_SDMMC_CMD_READ_WRITE_WIDTH 1
4918 /* The mask used to set the ALT_SDMMC_CMD_READ_WRITE register field value. */
4919 #define ALT_SDMMC_CMD_READ_WRITE_SET_MSK 0x00000400
4920 /* The mask used to clear the ALT_SDMMC_CMD_READ_WRITE register field value. */
4921 #define ALT_SDMMC_CMD_READ_WRITE_CLR_MSK 0xfffffbff
4922 /* The reset value of the ALT_SDMMC_CMD_READ_WRITE register field. */
4923 #define ALT_SDMMC_CMD_READ_WRITE_RESET 0x0
4924 /* Extracts the ALT_SDMMC_CMD_READ_WRITE field value from a register. */
4925 #define ALT_SDMMC_CMD_READ_WRITE_GET(value) (((value) & 0x00000400) >> 10)
4926 /* Produces a ALT_SDMMC_CMD_READ_WRITE register field value suitable for setting the register. */
4927 #define ALT_SDMMC_CMD_READ_WRITE_SET(value) (((value) << 10) & 0x00000400)
4928 
4929 /*
4930  * Field : TRANSFER_MODE
4931  *
4932  * 0-Block data transfer command
4933  *
4934  * 1-Stream data transfer command
4935  *
4936  * Don't care if no data expected.
4937  *
4938  * Field Enumeration Values:
4939  *
4940  * Enum | Value | Description
4941  * :-------------------------------------|:------|:-----------------------------
4942  * ALT_SDMMC_CMD_TRANSFER_MODE_E_BLOCK | 0x0 | Block data transfer command
4943  * ALT_SDMMC_CMD_TRANSFER_MODE_E_STREAM | 0x1 | Stream data transfer command
4944  *
4945  * Field Access Macros:
4946  *
4947  */
4948 /*
4949  * Enumerated value for register field ALT_SDMMC_CMD_TRANSFER_MODE
4950  *
4951  * Block data transfer command
4952  */
4953 #define ALT_SDMMC_CMD_TRANSFER_MODE_E_BLOCK 0x0
4954 /*
4955  * Enumerated value for register field ALT_SDMMC_CMD_TRANSFER_MODE
4956  *
4957  * Stream data transfer command
4958  */
4959 #define ALT_SDMMC_CMD_TRANSFER_MODE_E_STREAM 0x1
4960 
4961 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_TRANSFER_MODE register field. */
4962 #define ALT_SDMMC_CMD_TRANSFER_MODE_LSB 11
4963 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_TRANSFER_MODE register field. */
4964 #define ALT_SDMMC_CMD_TRANSFER_MODE_MSB 11
4965 /* The width in bits of the ALT_SDMMC_CMD_TRANSFER_MODE register field. */
4966 #define ALT_SDMMC_CMD_TRANSFER_MODE_WIDTH 1
4967 /* The mask used to set the ALT_SDMMC_CMD_TRANSFER_MODE register field value. */
4968 #define ALT_SDMMC_CMD_TRANSFER_MODE_SET_MSK 0x00000800
4969 /* The mask used to clear the ALT_SDMMC_CMD_TRANSFER_MODE register field value. */
4970 #define ALT_SDMMC_CMD_TRANSFER_MODE_CLR_MSK 0xfffff7ff
4971 /* The reset value of the ALT_SDMMC_CMD_TRANSFER_MODE register field. */
4972 #define ALT_SDMMC_CMD_TRANSFER_MODE_RESET 0x0
4973 /* Extracts the ALT_SDMMC_CMD_TRANSFER_MODE field value from a register. */
4974 #define ALT_SDMMC_CMD_TRANSFER_MODE_GET(value) (((value) & 0x00000800) >> 11)
4975 /* Produces a ALT_SDMMC_CMD_TRANSFER_MODE register field value suitable for setting the register. */
4976 #define ALT_SDMMC_CMD_TRANSFER_MODE_SET(value) (((value) << 11) & 0x00000800)
4977 
4978 /*
4979  * Field : SEND_AUTO_STOP
4980  *
4981  * 0-No stop command sent at end of data transfer
4982  *
4983  * 1-Send stop command at end of data transfer
4984  *
4985  * When set, DWC_mobile_storage sends stop command to SD_MMC_CEATA cards at end of
4986  * data transfer.
4987  *
4988  * * when send_auto_stop bit should be set, since some data
4989  *
4990  * transfers do not need explicit stop commands
4991  *
4992  * * open-ended transfers that software should explicitly send to
4993  *
4994  * stop command
4995  *
4996  * Additionally, when "resume" is sent to resume suspended memory access of
4997  * SD-Combo card bit should be set correctly if suspended data transfer needs
4998  * send_auto_stop.Don't care if no data expected from card.
4999  *
5000  * Field Enumeration Values:
5001  *
5002  * Enum | Value | Description
5003  * :-------------------------------------|:------|:------------------------------------------
5004  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_FALSE | 0x0 | No stop command at end of data transfer
5005  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_TRUE | 0x1 | Send stop command at end of data transfer
5006  *
5007  * Field Access Macros:
5008  *
5009  */
5010 /*
5011  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
5012  *
5013  * No stop command at end of data transfer
5014  */
5015 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_FALSE 0x0
5016 /*
5017  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
5018  *
5019  * Send stop command at end of data transfer
5020  */
5021 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_TRUE 0x1
5022 
5023 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
5024 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
5025 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
5026 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
5027 /* The width in bits of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
5028 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
5029 /* The mask used to set the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
5030 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
5031 /* The mask used to clear the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
5032 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
5033 /* The reset value of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
5034 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
5035 /* Extracts the ALT_SDMMC_CMD_SEND_AUTO_STOP field value from a register. */
5036 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
5037 /* Produces a ALT_SDMMC_CMD_SEND_AUTO_STOP register field value suitable for setting the register. */
5038 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
5039 
5040 /*
5041  * Field : WAIT_PRVDATA_COMPLETE
5042  *
5043  * 0-Send command at once, even if previous data transfer has not
5044  *
5045  * completed
5046  *
5047  * 1-Wait for previous data transfer completion before sending
5048  *
5049  * command
5050  *
5051  * The wait_prvdata_complete = 0 option typically used to query status of card
5052  * during data transfer or to stop current data transfer;card_number should be same
5053  * as in previous command.
5054  *
5055  * Field Enumeration Values:
5056  *
5057  * Enum | Value | Description
5058  * :----------------------------------------------|:------|:-------------------------------------------
5059  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NO_WAIT | 0x0 | Send command at once
5060  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT | 0x1 | Wait for previous data transfer completion
5061  * : | | before sending command
5062  *
5063  * Field Access Macros:
5064  *
5065  */
5066 /*
5067  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
5068  *
5069  * Send command at once
5070  */
5071 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NO_WAIT 0x0
5072 /*
5073  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
5074  *
5075  * Wait for previous data transfer completion before sending command
5076  */
5077 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
5078 
5079 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
5080 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
5081 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
5082 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
5083 /* The width in bits of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
5084 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
5085 /* The mask used to set the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
5086 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
5087 /* The mask used to clear the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
5088 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
5089 /* The reset value of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
5090 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
5091 /* Extracts the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE field value from a register. */
5092 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
5093 /* Produces a ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value suitable for setting the register. */
5094 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
5095 
5096 /*
5097  * Field : STOP_ABORT_CMD
5098  *
5099  * 0-Neither stop nor abort command to stop current data transfer
5100  *
5101  * in progress. If abort is sent to function-number currently
5102  *
5103  * selected or not in data-transfer mode, then bit should be set
5104  *
5105  * to 0.
5106  *
5107  * 1-Stop or abort command intended to stop current data transfer
5108  *
5109  * in progress.
5110  *
5111  * When open-ended or predefined data transfer is in progress, and host issues stop
5112  * or abort command to stop data transfer, bit should be set so that command/data
5113  * state-machines of CIU can return correctly to idle state. This is also
5114  * applicable for Boot mode transfers. To Abort boot mode, this bit should be set
5115  * along with CMD[26] = disable_boot.
5116  *
5117  * Field Enumeration Values:
5118  *
5119  * Enum | Value | Description
5120  * :-------------------------------------|:------|:------------------------------
5121  * ALT_SDMMC_CMD_STOP_ABORT_CMD_E_FALSE | 0x0 | Neither stop no abort command
5122  * ALT_SDMMC_CMD_STOP_ABORT_CMD_E_TRUE | 0x1 | Stop or abort command
5123  *
5124  * Field Access Macros:
5125  *
5126  */
5127 /*
5128  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABORT_CMD
5129  *
5130  * Neither stop no abort command
5131  */
5132 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_E_FALSE 0x0
5133 /*
5134  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABORT_CMD
5135  *
5136  * Stop or abort command
5137  */
5138 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_E_TRUE 0x1
5139 
5140 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_STOP_ABORT_CMD register field. */
5141 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_LSB 14
5142 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_STOP_ABORT_CMD register field. */
5143 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_MSB 14
5144 /* The width in bits of the ALT_SDMMC_CMD_STOP_ABORT_CMD register field. */
5145 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_WIDTH 1
5146 /* The mask used to set the ALT_SDMMC_CMD_STOP_ABORT_CMD register field value. */
5147 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_SET_MSK 0x00004000
5148 /* The mask used to clear the ALT_SDMMC_CMD_STOP_ABORT_CMD register field value. */
5149 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_CLR_MSK 0xffffbfff
5150 /* The reset value of the ALT_SDMMC_CMD_STOP_ABORT_CMD register field. */
5151 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_RESET 0x0
5152 /* Extracts the ALT_SDMMC_CMD_STOP_ABORT_CMD field value from a register. */
5153 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_GET(value) (((value) & 0x00004000) >> 14)
5154 /* Produces a ALT_SDMMC_CMD_STOP_ABORT_CMD register field value suitable for setting the register. */
5155 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_SET(value) (((value) << 14) & 0x00004000)
5156 
5157 /*
5158  * Field : SEND_INITIALIZATION
5159  *
5160  * 0-Do not send initialization sequence (80 clocks of 1) before
5161  *
5162  * sending this command
5163  *
5164  * 1-Send initialization sequence before sending this command
5165  *
5166  * After power on, 80 clocks must be sent to card for initialization before sending
5167  * any commands to card. Bit should be set while sending first command to card so
5168  * that controller will initialize clocks before sending command to card. This bit
5169  * should not be set for either of the boot modes (alternate or mandatory).
5170  *
5171  * Field Enumeration Values:
5172  *
5173  * Enum | Value | Description
5174  * :------------------------------------------|:------|:------------------------------------
5175  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_FALSE | 0x0 | Do not send initialization sequence
5176  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_TRUE | 0x1 | Send initialization sequence
5177  *
5178  * Field Access Macros:
5179  *
5180  */
5181 /*
5182  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
5183  *
5184  * Do not send initialization sequence
5185  */
5186 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_FALSE 0x0
5187 /*
5188  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
5189  *
5190  * Send initialization sequence
5191  */
5192 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_TRUE 0x1
5193 
5194 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
5195 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
5196 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
5197 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
5198 /* The width in bits of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
5199 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
5200 /* The mask used to set the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
5201 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
5202 /* The mask used to clear the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
5203 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
5204 /* The reset value of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
5205 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
5206 /* Extracts the ALT_SDMMC_CMD_SEND_INITIALIZATION field value from a register. */
5207 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
5208 /* Produces a ALT_SDMMC_CMD_SEND_INITIALIZATION register field value suitable for setting the register. */
5209 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
5210 
5211 /*
5212  * Field : CARD_NUMBER
5213  *
5214  * Card number in use. Represents physical slot number of card being
5215  *
5216  * accessed. In MMC-Ver3.3-only mode, up to 30 cards are supported; in SD-only
5217  * mode, up to 16 cards are supported. Registered version of this is reflected on
5218  * dw_dma_card_num and ge_dma_card_num ports, which can be used to create separate
5219  * DMA requests, if needed.
5220  *
5221  * In addition, in SD mode this is used to mux or demux signals from selected card
5222  * because each card is interfaced to
5223  *
5224  * DWC_mobile_storage by separate bus.
5225  *
5226  * Field Access Macros:
5227  *
5228  */
5229 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
5230 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
5231 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
5232 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
5233 /* The width in bits of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
5234 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
5235 /* The mask used to set the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
5236 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
5237 /* The mask used to clear the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
5238 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
5239 /* The reset value of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
5240 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
5241 /* Extracts the ALT_SDMMC_CMD_CARD_NUMBER field value from a register. */
5242 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
5243 /* Produces a ALT_SDMMC_CMD_CARD_NUMBER register field value suitable for setting the register. */
5244 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
5245 
5246 /*
5247  * Field : UPDATE_CLOCK_REGISTERS_ONLY
5248  *
5249  * 0-Normal command sequence
5250  *
5251  * 1-Do not send commands, just update clock register value into
5252  *
5253  * card clock domain
5254  *
5255  * Following register values transferred into card clock domain: CLKDIV, CLRSRC,
5256  * CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-
5257  * frequency mode); provided in order to change clock frequency or stop clock
5258  * without having to send command to cards.During normal command sequence, when
5259  * update_clock_registers_only = 0, following control registers are transferred
5260  * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE,BLKSIZ, BYTCNT. CIU uses new register
5261  * values for new command sequence to card(s).When bit is set, there are no Command
5262  * Done interrupts because no
5263  *
5264  * command is sent to SD_MMC_CEATA cards.
5265  *
5266  * Field Enumeration Values:
5267  *
5268  * Enum | Value | Description
5269  * :--------------------------------------------------|:------|:-------------------------------------------------
5270  * ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_FALSE | 0x0 | Normal command sequence
5271  * ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_TRUE | 0x1 | DO not send commands, just update clock register
5272  *
5273  * Field Access Macros:
5274  *
5275  */
5276 /*
5277  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY
5278  *
5279  * Normal command sequence
5280  */
5281 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_FALSE 0x0
5282 /*
5283  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY
5284  *
5285  * DO not send commands, just update clock register
5286  */
5287 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_TRUE 0x1
5288 
5289 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field. */
5290 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_LSB 21
5291 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field. */
5292 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MSB 21
5293 /* The width in bits of the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field. */
5294 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_WIDTH 1
5295 /* The mask used to set the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field value. */
5296 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SET_MSK 0x00200000
5297 /* The mask used to clear the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field value. */
5298 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_CLR_MSK 0xffdfffff
5299 /* The reset value of the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field. */
5300 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_RESET 0x0
5301 /* Extracts the ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY field value from a register. */
5302 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
5303 /* Produces a ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY register field value suitable for setting the register. */
5304 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SET(value) (((value) << 21) & 0x00200000)
5305 
5306 /*
5307  * Field : READ_CEATA_DEVICE
5308  *
5309  * 0-Host is not performing read access (RW_REG or RW_BLK)
5310  *
5311  * towards CE-ATA device
5312  *
5313  * 1-Host is performing read access (RW_REG or RW_BLK)
5314  *
5315  * towards CE-ATA device
5316  *
5317  * Software should set this bit to indicate that CE-ATA device is being accessed
5318  * for read transfer. This bit is used to disable read data timeout indication
5319  * while performing CE-ATA read transfers.Maximum value of I/O transmission delay
5320  * can be no less than 10 seconds. DWC_mobile_storage should not indicate read data
5321  * timeout while waiting for data from CE-ATA device.
5322  *
5323  * Field Enumeration Values:
5324  *
5325  * Enum | Value | Description
5326  * :------------------------------------------|:------|:--------------------------------
5327  * ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_NO_READ | 0x0 | No read access to CE-ATA device
5328  * ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_READ | 0x1 | Read access to CE-ATA device
5329  *
5330  * Field Access Macros:
5331  *
5332  */
5333 /*
5334  * Enumerated value for register field ALT_SDMMC_CMD_READ_CEATA_DEVICE
5335  *
5336  * No read access to CE-ATA device
5337  */
5338 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_NO_READ 0x0
5339 /*
5340  * Enumerated value for register field ALT_SDMMC_CMD_READ_CEATA_DEVICE
5341  *
5342  * Read access to CE-ATA device
5343  */
5344 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_READ 0x1
5345 
5346 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field. */
5347 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_LSB 22
5348 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field. */
5349 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_MSB 22
5350 /* The width in bits of the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field. */
5351 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_WIDTH 1
5352 /* The mask used to set the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field value. */
5353 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_SET_MSK 0x00400000
5354 /* The mask used to clear the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field value. */
5355 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_CLR_MSK 0xffbfffff
5356 /* The reset value of the ALT_SDMMC_CMD_READ_CEATA_DEVICE register field. */
5357 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_RESET 0x0
5358 /* Extracts the ALT_SDMMC_CMD_READ_CEATA_DEVICE field value from a register. */
5359 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
5360 /* Produces a ALT_SDMMC_CMD_READ_CEATA_DEVICE register field value suitable for setting the register. */
5361 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
5362 
5363 /*
5364  * Field : CCS_EXPECTED
5365  *
5366  * 0-Interrupts are not enabled in CE-ATA device (nIEN = 1 in
5367  *
5368  * ATA control register), or command does not expect CCS
5369  *
5370  * from device
5371  *
5372  * 1-Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK
5373  *
5374  * command expects command completion signal from CE-ATA device
5375  *
5376  * If the command expects Command Completion Signal (CCS) from the CE-ATA device,
5377  * the software should set this control bit.DWC_mobile_storage sets Data Transfer
5378  * Over (DTO) bit in RINTSTS register and generates interrupt to host if Data
5379  * Transfer Over interrupt is not masked.
5380  *
5381  * Field Enumeration Values:
5382  *
5383  * Enum | Value | Description
5384  * :-----------------------------------|:------|:----------------------------------------
5385  * ALT_SDMMC_CMD_CCS_EXPECTED_E_FALSE | 0x0 | Command does not expect CCS from device
5386  * ALT_SDMMC_CMD_CCS_EXPECTED_E_TRUE | 0x1 | Expects CCS from device
5387  *
5388  * Field Access Macros:
5389  *
5390  */
5391 /*
5392  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
5393  *
5394  * Command does not expect CCS from device
5395  */
5396 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_FALSE 0x0
5397 /*
5398  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
5399  *
5400  * Expects CCS from device
5401  */
5402 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_TRUE 0x1
5403 
5404 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
5405 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
5406 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
5407 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
5408 /* The width in bits of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
5409 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
5410 /* The mask used to set the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
5411 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
5412 /* The mask used to clear the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
5413 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
5414 /* The reset value of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
5415 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
5416 /* Extracts the ALT_SDMMC_CMD_CCS_EXPECTED field value from a register. */
5417 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
5418 /* Produces a ALT_SDMMC_CMD_CCS_EXPECTED register field value suitable for setting the register. */
5419 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
5420 
5421 /*
5422  * Field : ENABLE_BOOT
5423  *
5424  * Enable Boot this bit should be set only for mandatory boot mode.
5425  *
5426  * When Software sets this bit along with start_cmd, CIU starts the boot sequence
5427  * for the corresponding card by asserting the CMD line low. Do NOT set
5428  * disable_boot and enable_boot together.
5429  *
5430  * Field Enumeration Values:
5431  *
5432  * Enum | Value | Description
5433  * :----------------------------------|:------|:------------
5434  * ALT_SDMMC_CMD_ENABLE_BOOT_E_FALSE | 0x0 | No boot
5435  * ALT_SDMMC_CMD_ENABLE_BOOT_E_TRUE | 0x1 | Enable boot
5436  *
5437  * Field Access Macros:
5438  *
5439  */
5440 /*
5441  * Enumerated value for register field ALT_SDMMC_CMD_ENABLE_BOOT
5442  *
5443  * No boot
5444  */
5445 #define ALT_SDMMC_CMD_ENABLE_BOOT_E_FALSE 0x0
5446 /*
5447  * Enumerated value for register field ALT_SDMMC_CMD_ENABLE_BOOT
5448  *
5449  * Enable boot
5450  */
5451 #define ALT_SDMMC_CMD_ENABLE_BOOT_E_TRUE 0x1
5452 
5453 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_ENABLE_BOOT register field. */
5454 #define ALT_SDMMC_CMD_ENABLE_BOOT_LSB 24
5455 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_ENABLE_BOOT register field. */
5456 #define ALT_SDMMC_CMD_ENABLE_BOOT_MSB 24
5457 /* The width in bits of the ALT_SDMMC_CMD_ENABLE_BOOT register field. */
5458 #define ALT_SDMMC_CMD_ENABLE_BOOT_WIDTH 1
5459 /* The mask used to set the ALT_SDMMC_CMD_ENABLE_BOOT register field value. */
5460 #define ALT_SDMMC_CMD_ENABLE_BOOT_SET_MSK 0x01000000
5461 /* The mask used to clear the ALT_SDMMC_CMD_ENABLE_BOOT register field value. */
5462 #define ALT_SDMMC_CMD_ENABLE_BOOT_CLR_MSK 0xfeffffff
5463 /* The reset value of the ALT_SDMMC_CMD_ENABLE_BOOT register field. */
5464 #define ALT_SDMMC_CMD_ENABLE_BOOT_RESET 0x0
5465 /* Extracts the ALT_SDMMC_CMD_ENABLE_BOOT field value from a register. */
5466 #define ALT_SDMMC_CMD_ENABLE_BOOT_GET(value) (((value) & 0x01000000) >> 24)
5467 /* Produces a ALT_SDMMC_CMD_ENABLE_BOOT register field value suitable for setting the register. */
5468 #define ALT_SDMMC_CMD_ENABLE_BOOT_SET(value) (((value) << 24) & 0x01000000)
5469 
5470 /*
5471  * Field : EXPECT_BOOT_ACK
5472  *
5473  * Expect Boot Acknowledge. When Software sets this bit along with
5474  *
5475  * enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the
5476  * selected card.
5477  *
5478  * Field Enumeration Values:
5479  *
5480  * Enum | Value | Description
5481  * :--------------------------------------|:------|:----------------------------
5482  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_FALSE | 0x0 | No boot acknowledgement
5483  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_TRUE | 0x1 | Expect boot acknowledgement
5484  *
5485  * Field Access Macros:
5486  *
5487  */
5488 /*
5489  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
5490  *
5491  * No boot acknowledgement
5492  */
5493 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_FALSE 0x0
5494 /*
5495  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
5496  *
5497  * Expect boot acknowledgement
5498  */
5499 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_TRUE 0x1
5500 
5501 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
5502 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
5503 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
5504 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
5505 /* The width in bits of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
5506 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
5507 /* The mask used to set the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
5508 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
5509 /* The mask used to clear the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
5510 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
5511 /* The reset value of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
5512 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
5513 /* Extracts the ALT_SDMMC_CMD_EXPECT_BOOT_ACK field value from a register. */
5514 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
5515 /* Produces a ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value suitable for setting the register. */
5516 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
5517 
5518 /*
5519  * Field : DISABLE_BOOT
5520  *
5521  * Disable Boot. When software sets this bit along with start_cmd, CIU terminates
5522  * the boot operation. Do NOT set disable_boot and enable_boot together.
5523  *
5524  * Field Enumeration Values:
5525  *
5526  * Enum | Value | Description
5527  * :-----------------------------------|:------|:--------------------------
5528  * ALT_SDMMC_CMD_DISABLE_BOOT_E_FALSE | 0x0 | No change
5529  * ALT_SDMMC_CMD_DISABLE_BOOT_E_TRUE | 0x1 | Terminates boot operation
5530  *
5531  * Field Access Macros:
5532  *
5533  */
5534 /*
5535  * Enumerated value for register field ALT_SDMMC_CMD_DISABLE_BOOT
5536  *
5537  * No change
5538  */
5539 #define ALT_SDMMC_CMD_DISABLE_BOOT_E_FALSE 0x0
5540 /*
5541  * Enumerated value for register field ALT_SDMMC_CMD_DISABLE_BOOT
5542  *
5543  * Terminates boot operation
5544  */
5545 #define ALT_SDMMC_CMD_DISABLE_BOOT_E_TRUE 0x1
5546 
5547 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DISABLE_BOOT register field. */
5548 #define ALT_SDMMC_CMD_DISABLE_BOOT_LSB 26
5549 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DISABLE_BOOT register field. */
5550 #define ALT_SDMMC_CMD_DISABLE_BOOT_MSB 26
5551 /* The width in bits of the ALT_SDMMC_CMD_DISABLE_BOOT register field. */
5552 #define ALT_SDMMC_CMD_DISABLE_BOOT_WIDTH 1
5553 /* The mask used to set the ALT_SDMMC_CMD_DISABLE_BOOT register field value. */
5554 #define ALT_SDMMC_CMD_DISABLE_BOOT_SET_MSK 0x04000000
5555 /* The mask used to clear the ALT_SDMMC_CMD_DISABLE_BOOT register field value. */
5556 #define ALT_SDMMC_CMD_DISABLE_BOOT_CLR_MSK 0xfbffffff
5557 /* The reset value of the ALT_SDMMC_CMD_DISABLE_BOOT register field. */
5558 #define ALT_SDMMC_CMD_DISABLE_BOOT_RESET 0x0
5559 /* Extracts the ALT_SDMMC_CMD_DISABLE_BOOT field value from a register. */
5560 #define ALT_SDMMC_CMD_DISABLE_BOOT_GET(value) (((value) & 0x04000000) >> 26)
5561 /* Produces a ALT_SDMMC_CMD_DISABLE_BOOT register field value suitable for setting the register. */
5562 #define ALT_SDMMC_CMD_DISABLE_BOOT_SET(value) (((value) << 26) & 0x04000000)
5563 
5564 /*
5565  * Field : BOOT_MODE
5566  *
5567  * Boot Mode
5568  *
5569  * 0 - Mandatory Boot operation
5570  *
5571  * 1 - Alternate Boot operation
5572  *
5573  * Field Enumeration Values:
5574  *
5575  * Enum | Value | Description
5576  * :------------------------------------|:------|:-------------------------
5577  * ALT_SDMMC_CMD_BOOT_MODE_E_MANDATORY | 0x0 | Mandatory Boot operation
5578  * ALT_SDMMC_CMD_BOOT_MODE_E_ALTERNATE | 0x1 | Alternate boot operation
5579  *
5580  * Field Access Macros:
5581  *
5582  */
5583 /*
5584  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MODE
5585  *
5586  * Mandatory Boot operation
5587  */
5588 #define ALT_SDMMC_CMD_BOOT_MODE_E_MANDATORY 0x0
5589 /*
5590  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MODE
5591  *
5592  * Alternate boot operation
5593  */
5594 #define ALT_SDMMC_CMD_BOOT_MODE_E_ALTERNATE 0x1
5595 
5596 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_BOOT_MODE register field. */
5597 #define ALT_SDMMC_CMD_BOOT_MODE_LSB 27
5598 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_BOOT_MODE register field. */
5599 #define ALT_SDMMC_CMD_BOOT_MODE_MSB 27
5600 /* The width in bits of the ALT_SDMMC_CMD_BOOT_MODE register field. */
5601 #define ALT_SDMMC_CMD_BOOT_MODE_WIDTH 1
5602 /* The mask used to set the ALT_SDMMC_CMD_BOOT_MODE register field value. */
5603 #define ALT_SDMMC_CMD_BOOT_MODE_SET_MSK 0x08000000
5604 /* The mask used to clear the ALT_SDMMC_CMD_BOOT_MODE register field value. */
5605 #define ALT_SDMMC_CMD_BOOT_MODE_CLR_MSK 0xf7ffffff
5606 /* The reset value of the ALT_SDMMC_CMD_BOOT_MODE register field. */
5607 #define ALT_SDMMC_CMD_BOOT_MODE_RESET 0x0
5608 /* Extracts the ALT_SDMMC_CMD_BOOT_MODE field value from a register. */
5609 #define ALT_SDMMC_CMD_BOOT_MODE_GET(value) (((value) & 0x08000000) >> 27)
5610 /* Produces a ALT_SDMMC_CMD_BOOT_MODE register field value suitable for setting the register. */
5611 #define ALT_SDMMC_CMD_BOOT_MODE_SET(value) (((value) << 27) & 0x08000000)
5612 
5613 /*
5614  * Field : VOLT_SWITCH
5615  *
5616  * Voltage switch bit
5617  *
5618  * 0 - No voltage switching
5619  *
5620  * 1 - Voltage switching enabled; must be set for CMD11 only
5621  *
5622  * Field Enumeration Values:
5623  *
5624  * Enum | Value | Description
5625  * :----------------------------------|:------|:--------------------------
5626  * ALT_SDMMC_CMD_VOLT_SWITCH_E_FALSE | 0x0 | No Voltage switching
5627  * ALT_SDMMC_CMD_VOLT_SWITCH_E_TRUE | 0x1 | Voltage switching enabled
5628  *
5629  * Field Access Macros:
5630  *
5631  */
5632 /*
5633  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
5634  *
5635  * No Voltage switching
5636  */
5637 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_FALSE 0x0
5638 /*
5639  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
5640  *
5641  * Voltage switching enabled
5642  */
5643 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_TRUE 0x1
5644 
5645 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
5646 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
5647 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
5648 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
5649 /* The width in bits of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
5650 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
5651 /* The mask used to set the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
5652 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
5653 /* The mask used to clear the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
5654 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
5655 /* The reset value of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
5656 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
5657 /* Extracts the ALT_SDMMC_CMD_VOLT_SWITCH field value from a register. */
5658 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
5659 /* Produces a ALT_SDMMC_CMD_VOLT_SWITCH register field value suitable for setting the register. */
5660 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
5661 
5662 /*
5663  * Field : USE_HOLD_REG
5664  *
5665  * Use Hold Register
5666  *
5667  * 0 - CMD and DATA sent to card bypassing HOLD Register
5668  *
5669  * 1 - CMD and DATA sent to card through the HOLD Register
5670  *
5671  * Field Enumeration Values:
5672  *
5673  * Enum | Value | Description
5674  * :-----------------------------------|:------|:-------------------------------------------
5675  * ALT_SDMMC_CMD_USE_HOLD_REG_E_FALSE | 0x0 | CMD and DATA sent to card bypassing HOLD
5676  * : | | Register
5677  * ALT_SDMMC_CMD_USE_HOLD_REG_E_TRUE | 0x1 | CMD and DATA sent to card through the HOLD
5678  * : | | Register
5679  *
5680  * Field Access Macros:
5681  *
5682  */
5683 /*
5684  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
5685  *
5686  * CMD and DATA sent to card bypassing HOLD Register
5687  */
5688 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_FALSE 0x0
5689 /*
5690  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
5691  *
5692  * CMD and DATA sent to card through the HOLD Register
5693  */
5694 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_TRUE 0x1
5695 
5696 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
5697 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
5698 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
5699 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
5700 /* The width in bits of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
5701 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
5702 /* The mask used to set the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
5703 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
5704 /* The mask used to clear the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
5705 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
5706 /* The reset value of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
5707 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
5708 /* Extracts the ALT_SDMMC_CMD_USE_HOLD_REG field value from a register. */
5709 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
5710 /* Produces a ALT_SDMMC_CMD_USE_HOLD_REG register field value suitable for setting the register. */
5711 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
5712 
5713 /*
5714  * Field : START_CMD
5715  *
5716  * Start command. Once command is taken by CIU, bit is cleared.
5717  *
5718  * When bit is set, host should not attempt to write to any command registers. If
5719  * write is attempted, hardware lock error is set in raw interrupt register.
5720  *
5721  * Once command is sent and response is received from SD_MMC_CEATA cards, Command
5722  * Done bit is set in raw interrupt
5723  *
5724  * register.
5725  *
5726  * Field Enumeration Values:
5727  *
5728  * Enum | Value | Description
5729  * :--------------------------------|:------|:-----------------------------------------------
5730  * ALT_SDMMC_CMD_START_CMD_E_FALSE | 0x0 | Auto cleared, once the command is taken by CIU
5731  * ALT_SDMMC_CMD_START_CMD_E_TRUE | 0x1 | Start command
5732  *
5733  * Field Access Macros:
5734  *
5735  */
5736 /*
5737  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
5738  *
5739  * Auto cleared, once the command is taken by CIU
5740  */
5741 #define ALT_SDMMC_CMD_START_CMD_E_FALSE 0x0
5742 /*
5743  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
5744  *
5745  * Start command
5746  */
5747 #define ALT_SDMMC_CMD_START_CMD_E_TRUE 0x1
5748 
5749 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
5750 #define ALT_SDMMC_CMD_START_CMD_LSB 31
5751 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
5752 #define ALT_SDMMC_CMD_START_CMD_MSB 31
5753 /* The width in bits of the ALT_SDMMC_CMD_START_CMD register field. */
5754 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
5755 /* The mask used to set the ALT_SDMMC_CMD_START_CMD register field value. */
5756 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
5757 /* The mask used to clear the ALT_SDMMC_CMD_START_CMD register field value. */
5758 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
5759 /* The reset value of the ALT_SDMMC_CMD_START_CMD register field. */
5760 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
5761 /* Extracts the ALT_SDMMC_CMD_START_CMD field value from a register. */
5762 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
5763 /* Produces a ALT_SDMMC_CMD_START_CMD register field value suitable for setting the register. */
5764 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
5765 
5766 #ifndef __ASSEMBLY__
5767 /*
5768  * WARNING: The C register and register group struct declarations are provided for
5769  * convenience and illustrative purposes. They should, however, be used with
5770  * caution as the C language standard provides no guarantees about the alignment or
5771  * atomicity of device memory accesses. The recommended practice for coding device
5772  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5773  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5774  * alt_write_dword() functions for 64 bit registers.
5775  *
5776  * The struct declaration for register ALT_SDMMC_CMD.
5777  */
5778 struct ALT_SDMMC_CMD_s
5779 {
5780  volatile uint32_t CMD_INDEX : 6; /* ALT_SDMMC_CMD_CMD_INDEX */
5781  volatile uint32_t RESPONSE_EXPECT : 1; /* ALT_SDMMC_CMD_RESPONSE_EXPECT */
5782  volatile uint32_t RESPONSE_LENGTH : 1; /* ALT_SDMMC_CMD_RESPONSE_LENGTH */
5783  volatile uint32_t CHECK_RESPONSE_CRC : 1; /* ALT_SDMMC_CMD_CHECK_RESPONSE_CRC */
5784  volatile uint32_t DATA_EXPECTED : 1; /* ALT_SDMMC_CMD_DATA_EXPECTED */
5785  volatile uint32_t READ_WRITE : 1; /* ALT_SDMMC_CMD_READ_WRITE */
5786  volatile uint32_t TRANSFER_MODE : 1; /* ALT_SDMMC_CMD_TRANSFER_MODE */
5787  volatile uint32_t SEND_AUTO_STOP : 1; /* ALT_SDMMC_CMD_SEND_AUTO_STOP */
5788  volatile uint32_t WAIT_PRVDATA_COMPLETE : 1; /* ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE */
5789  volatile uint32_t STOP_ABORT_CMD : 1; /* ALT_SDMMC_CMD_STOP_ABORT_CMD */
5790  volatile uint32_t SEND_INITIALIZATION : 1; /* ALT_SDMMC_CMD_SEND_INITIALIZATION */
5791  volatile uint32_t CARD_NUMBER : 5; /* ALT_SDMMC_CMD_CARD_NUMBER */
5792  volatile uint32_t UPDATE_CLOCK_REGISTERS_ONLY : 1; /* ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY */
5793  volatile uint32_t READ_CEATA_DEVICE : 1; /* ALT_SDMMC_CMD_READ_CEATA_DEVICE */
5794  volatile uint32_t CCS_EXPECTED : 1; /* ALT_SDMMC_CMD_CCS_EXPECTED */
5795  volatile uint32_t ENABLE_BOOT : 1; /* ALT_SDMMC_CMD_ENABLE_BOOT */
5796  volatile uint32_t EXPECT_BOOT_ACK : 1; /* ALT_SDMMC_CMD_EXPECT_BOOT_ACK */
5797  volatile uint32_t DISABLE_BOOT : 1; /* ALT_SDMMC_CMD_DISABLE_BOOT */
5798  volatile uint32_t BOOT_MODE : 1; /* ALT_SDMMC_CMD_BOOT_MODE */
5799  volatile uint32_t VOLT_SWITCH : 1; /* ALT_SDMMC_CMD_VOLT_SWITCH */
5800  volatile uint32_t USE_HOLD_REG : 1; /* ALT_SDMMC_CMD_USE_HOLD_REG */
5801  uint32_t : 1; /* *UNDEFINED* */
5802  volatile uint32_t START_CMD : 1; /* ALT_SDMMC_CMD_START_CMD */
5803 };
5804 
5805 /* The typedef declaration for register ALT_SDMMC_CMD. */
5806 typedef struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
5807 #endif /* __ASSEMBLY__ */
5808 
5809 /* The reset value of the ALT_SDMMC_CMD register. */
5810 #define ALT_SDMMC_CMD_RESET 0x20000000
5811 /* The byte offset of the ALT_SDMMC_CMD register from the beginning of the component. */
5812 #define ALT_SDMMC_CMD_OFST 0x2c
5813 /* The address of the ALT_SDMMC_CMD register. */
5814 #define ALT_SDMMC_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CMD_OFST))
5815 
5816 /*
5817  * Register : Response Register 0 - RESP0
5818  *
5819  * Response Register 0
5820  *
5821  * Register Layout
5822  *
5823  * Bits | Access | Reset | Description
5824  * :-------|:-------|:------|:--------------------------
5825  * [31:0] | R | 0x0 | ALT_SDMMC_RESP0_RESPONSE0
5826  *
5827  */
5828 /*
5829  * Field : RESPONSE0
5830  *
5831  * Bit[31:0] of response
5832  *
5833  * Field Access Macros:
5834  *
5835  */
5836 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
5837 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
5838 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
5839 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
5840 /* The width in bits of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
5841 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
5842 /* The mask used to set the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
5843 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
5844 /* The mask used to clear the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
5845 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
5846 /* The reset value of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
5847 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
5848 /* Extracts the ALT_SDMMC_RESP0_RESPONSE0 field value from a register. */
5849 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
5850 /* Produces a ALT_SDMMC_RESP0_RESPONSE0 register field value suitable for setting the register. */
5851 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
5852 
5853 #ifndef __ASSEMBLY__
5854 /*
5855  * WARNING: The C register and register group struct declarations are provided for
5856  * convenience and illustrative purposes. They should, however, be used with
5857  * caution as the C language standard provides no guarantees about the alignment or
5858  * atomicity of device memory accesses. The recommended practice for coding device
5859  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5860  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5861  * alt_write_dword() functions for 64 bit registers.
5862  *
5863  * The struct declaration for register ALT_SDMMC_RESP0.
5864  */
5865 struct ALT_SDMMC_RESP0_s
5866 {
5867  const volatile uint32_t RESPONSE0 : 32; /* ALT_SDMMC_RESP0_RESPONSE0 */
5868 };
5869 
5870 /* The typedef declaration for register ALT_SDMMC_RESP0. */
5871 typedef struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
5872 #endif /* __ASSEMBLY__ */
5873 
5874 /* The reset value of the ALT_SDMMC_RESP0 register. */
5875 #define ALT_SDMMC_RESP0_RESET 0x00000000
5876 /* The byte offset of the ALT_SDMMC_RESP0 register from the beginning of the component. */
5877 #define ALT_SDMMC_RESP0_OFST 0x30
5878 /* The address of the ALT_SDMMC_RESP0 register. */
5879 #define ALT_SDMMC_RESP0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP0_OFST))
5880 
5881 /*
5882  * Register : Response Register 1 - RESP1
5883  *
5884  * Response Register 1
5885  *
5886  * Register Layout
5887  *
5888  * Bits | Access | Reset | Description
5889  * :-------|:-------|:------|:--------------------------
5890  * [31:0] | R | 0x0 | ALT_SDMMC_RESP1_RESPONSE1
5891  *
5892  */
5893 /*
5894  * Field : RESPONSE1
5895  *
5896  * Register represents bit[63:32] of long response.
5897  *
5898  * When CIU sends auto-stop command, then response is saved in register. Response
5899  * for previous command sent by host is still preserved in Response 0 register.
5900  * Additional auto-stop issued only for data transfer commands, and response type
5901  * is always "short" for them.
5902  *
5903  * Field Access Macros:
5904  *
5905  */
5906 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
5907 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
5908 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
5909 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
5910 /* The width in bits of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
5911 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
5912 /* The mask used to set the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
5913 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
5914 /* The mask used to clear the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
5915 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
5916 /* The reset value of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
5917 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
5918 /* Extracts the ALT_SDMMC_RESP1_RESPONSE1 field value from a register. */
5919 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
5920 /* Produces a ALT_SDMMC_RESP1_RESPONSE1 register field value suitable for setting the register. */
5921 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
5922 
5923 #ifndef __ASSEMBLY__
5924 /*
5925  * WARNING: The C register and register group struct declarations are provided for
5926  * convenience and illustrative purposes. They should, however, be used with
5927  * caution as the C language standard provides no guarantees about the alignment or
5928  * atomicity of device memory accesses. The recommended practice for coding device
5929  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5930  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5931  * alt_write_dword() functions for 64 bit registers.
5932  *
5933  * The struct declaration for register ALT_SDMMC_RESP1.
5934  */
5935 struct ALT_SDMMC_RESP1_s
5936 {
5937  const volatile uint32_t RESPONSE1 : 32; /* ALT_SDMMC_RESP1_RESPONSE1 */
5938 };
5939 
5940 /* The typedef declaration for register ALT_SDMMC_RESP1. */
5941 typedef struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
5942 #endif /* __ASSEMBLY__ */
5943 
5944 /* The reset value of the ALT_SDMMC_RESP1 register. */
5945 #define ALT_SDMMC_RESP1_RESET 0x00000000
5946 /* The byte offset of the ALT_SDMMC_RESP1 register from the beginning of the component. */
5947 #define ALT_SDMMC_RESP1_OFST 0x34
5948 /* The address of the ALT_SDMMC_RESP1 register. */
5949 #define ALT_SDMMC_RESP1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP1_OFST))
5950 
5951 /*
5952  * Register : Response Register 2 - RESP2
5953  *
5954  * Response Register 2
5955  *
5956  * Register Layout
5957  *
5958  * Bits | Access | Reset | Description
5959  * :-------|:-------|:------|:--------------------------
5960  * [31:0] | R | 0x0 | ALT_SDMMC_RESP2_RESPONSE2
5961  *
5962  */
5963 /*
5964  * Field : RESPONSE2
5965  *
5966  * Bit[95:64] of long response
5967  *
5968  * Field Access Macros:
5969  *
5970  */
5971 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
5972 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
5973 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
5974 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
5975 /* The width in bits of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
5976 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
5977 /* The mask used to set the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
5978 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
5979 /* The mask used to clear the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
5980 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
5981 /* The reset value of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
5982 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
5983 /* Extracts the ALT_SDMMC_RESP2_RESPONSE2 field value from a register. */
5984 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
5985 /* Produces a ALT_SDMMC_RESP2_RESPONSE2 register field value suitable for setting the register. */
5986 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
5987 
5988 #ifndef __ASSEMBLY__
5989 /*
5990  * WARNING: The C register and register group struct declarations are provided for
5991  * convenience and illustrative purposes. They should, however, be used with
5992  * caution as the C language standard provides no guarantees about the alignment or
5993  * atomicity of device memory accesses. The recommended practice for coding device
5994  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5995  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5996  * alt_write_dword() functions for 64 bit registers.
5997  *
5998  * The struct declaration for register ALT_SDMMC_RESP2.
5999  */
6000 struct ALT_SDMMC_RESP2_s
6001 {
6002  const volatile uint32_t RESPONSE2 : 32; /* ALT_SDMMC_RESP2_RESPONSE2 */
6003 };
6004 
6005 /* The typedef declaration for register ALT_SDMMC_RESP2. */
6006 typedef struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
6007 #endif /* __ASSEMBLY__ */
6008 
6009 /* The reset value of the ALT_SDMMC_RESP2 register. */
6010 #define ALT_SDMMC_RESP2_RESET 0x00000000
6011 /* The byte offset of the ALT_SDMMC_RESP2 register from the beginning of the component. */
6012 #define ALT_SDMMC_RESP2_OFST 0x38
6013 /* The address of the ALT_SDMMC_RESP2 register. */
6014 #define ALT_SDMMC_RESP2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP2_OFST))
6015 
6016 /*
6017  * Register : Response Register 3 - RESP3
6018  *
6019  * Response Register 3
6020  *
6021  * Register Layout
6022  *
6023  * Bits | Access | Reset | Description
6024  * :-------|:-------|:------|:--------------------------
6025  * [31:0] | R | 0x0 | ALT_SDMMC_RESP3_RESPONSE3
6026  *
6027  */
6028 /*
6029  * Field : RESPONSE3
6030  *
6031  * Bit[127:96] of long response
6032  *
6033  * Field Access Macros:
6034  *
6035  */
6036 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
6037 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
6038 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
6039 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
6040 /* The width in bits of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
6041 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
6042 /* The mask used to set the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
6043 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
6044 /* The mask used to clear the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
6045 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
6046 /* The reset value of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
6047 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
6048 /* Extracts the ALT_SDMMC_RESP3_RESPONSE3 field value from a register. */
6049 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
6050 /* Produces a ALT_SDMMC_RESP3_RESPONSE3 register field value suitable for setting the register. */
6051 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
6052 
6053 #ifndef __ASSEMBLY__
6054 /*
6055  * WARNING: The C register and register group struct declarations are provided for
6056  * convenience and illustrative purposes. They should, however, be used with
6057  * caution as the C language standard provides no guarantees about the alignment or
6058  * atomicity of device memory accesses. The recommended practice for coding device
6059  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6060  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6061  * alt_write_dword() functions for 64 bit registers.
6062  *
6063  * The struct declaration for register ALT_SDMMC_RESP3.
6064  */
6065 struct ALT_SDMMC_RESP3_s
6066 {
6067  const volatile uint32_t RESPONSE3 : 32; /* ALT_SDMMC_RESP3_RESPONSE3 */
6068 };
6069 
6070 /* The typedef declaration for register ALT_SDMMC_RESP3. */
6071 typedef struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
6072 #endif /* __ASSEMBLY__ */
6073 
6074 /* The reset value of the ALT_SDMMC_RESP3 register. */
6075 #define ALT_SDMMC_RESP3_RESET 0x00000000
6076 /* The byte offset of the ALT_SDMMC_RESP3 register from the beginning of the component. */
6077 #define ALT_SDMMC_RESP3_OFST 0x3c
6078 /* The address of the ALT_SDMMC_RESP3 register. */
6079 #define ALT_SDMMC_RESP3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP3_OFST))
6080 
6081 /*
6082  * Register : Masked Interrupt Status Register - MINTSTS
6083  *
6084  * Name: Masked Interrupt Status Register
6085  *
6086  * Size: 32 bits
6087  *
6088  * Address Offset: 0x40
6089  *
6090  * Read/write access: read
6091  *
6092  * MISTATS = RIINTSTS and INTMASK
6093  *
6094  * Register Layout
6095  *
6096  * Bits | Access | Reset | Description
6097  * :-----|:-------|:------|:-------------------------------------------------------
6098  * [0] | R | 0x0 | ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT
6099  * [1] | R | 0x0 | ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT
6100  * [2] | R | 0x0 | ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT
6101  * [3] | R | 0x0 | ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT
6102  * [4] | R | 0x0 | ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT
6103  * [5] | R | 0x0 | ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT
6104  * [6] | R | 0x0 | ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT
6105  * [7] | R | 0x0 | ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT
6106  * [8] | R | 0x0 | ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT
6107  * [9] | R | 0x0 | ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT
6108  * [10] | R | 0x0 | ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT
6109  * [11] | R | 0x0 | ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT
6110  * [12] | R | 0x0 | ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT
6111  * [13] | R | 0x0 | ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT
6112  * [14] | R | 0x0 | ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT
6113  * [15] | R | 0x0 | ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT
6114  * [16] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0
6115  * [17] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1
6116  * [18] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2
6117  * [19] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3
6118  * [20] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4
6119  * [21] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5
6120  * [22] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6
6121  * [23] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7
6122  * [24] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8
6123  * [25] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9
6124  * [26] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10
6125  * [27] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11
6126  * [28] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12
6127  * [29] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13
6128  * [30] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14
6129  * [31] | R | 0x0 | ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15
6130  *
6131  */
6132 /*
6133  * Field : CARD_DETECT_INTERRUPT
6134  *
6135  * bit 0 Card detect (CD)
6136  *
6137  * Field Enumeration Values:
6138  *
6139  * Enum | Value | Description
6140  * :---------------------------------------------------|:------|:------------------------------------------------
6141  * ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6142  * ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_ENABLED | 0x1 | CARD DETECT Interrupt enabled only if
6143  * : | | corresponding bit in interrupt mask register is
6144  * : | | set
6145  *
6146  * Field Access Macros:
6147  *
6148  */
6149 /*
6150  * Enumerated value for register field ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT
6151  *
6152  * Interrupt disabled
6153  */
6154 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_DISABLED 0x0
6155 /*
6156  * Enumerated value for register field ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT
6157  *
6158  * CARD DETECT Interrupt enabled only if corresponding bit in interrupt mask
6159  * register is set
6160  */
6161 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_ENABLED 0x1
6162 
6163 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field. */
6164 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_LSB 0
6165 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field. */
6166 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_MSB 0
6167 /* The width in bits of the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field. */
6168 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_WIDTH 1
6169 /* The mask used to set the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field value. */
6170 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_SET_MSK 0x00000001
6171 /* The mask used to clear the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field value. */
6172 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_CLR_MSK 0xfffffffe
6173 /* The reset value of the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field. */
6174 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_RESET 0x0
6175 /* Extracts the ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT field value from a register. */
6176 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_GET(value) (((value) & 0x00000001) >> 0)
6177 /* Produces a ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT register field value suitable for setting the register. */
6178 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_SET(value) (((value) << 0) & 0x00000001)
6179 
6180 /*
6181  * Field : RESPONSE_ERROR_INTERRUPT
6182  *
6183  * bit 1 Response error (RE)
6184  *
6185  * Field Enumeration Values:
6186  *
6187  * Enum | Value | Description
6188  * :------------------------------------------------------|:------|:------------------------------------------------
6189  * ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6190  * ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_ENABLED | 0x1 | Response error Interrupt enabled only if
6191  * : | | corresponding bit in interrupt mask register is
6192  * : | | set
6193  *
6194  * Field Access Macros:
6195  *
6196  */
6197 /*
6198  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT
6199  *
6200  * Interrupt disabled
6201  */
6202 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_DISABLED 0x0
6203 /*
6204  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT
6205  *
6206  * Response error Interrupt enabled only if corresponding bit in interrupt mask
6207  * register is set
6208  */
6209 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_ENABLED 0x1
6210 
6211 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field. */
6212 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_LSB 1
6213 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field. */
6214 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_MSB 1
6215 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field. */
6216 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_WIDTH 1
6217 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field value. */
6218 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_SET_MSK 0x00000002
6219 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field value. */
6220 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_CLR_MSK 0xfffffffd
6221 /* The reset value of the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field. */
6222 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_RESET 0x0
6223 /* Extracts the ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT field value from a register. */
6224 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_GET(value) (((value) & 0x00000002) >> 1)
6225 /* Produces a ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT register field value suitable for setting the register. */
6226 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_SET(value) (((value) << 1) & 0x00000002)
6227 
6228 /*
6229  * Field : COMMAND_DONE_INTERRUPT
6230  *
6231  * bit 2 Command done (CD)
6232  *
6233  * Field Enumeration Values:
6234  *
6235  * Enum | Value | Description
6236  * :----------------------------------------------------|:------|:------------------------------------------------
6237  * ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6238  * ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_ENABLED | 0x1 | Command done Interrupt enabled only if
6239  * : | | corresponding bit in interrupt mask register is
6240  * : | | set
6241  *
6242  * Field Access Macros:
6243  *
6244  */
6245 /*
6246  * Enumerated value for register field ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT
6247  *
6248  * Interrupt disabled
6249  */
6250 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_DISABLED 0x0
6251 /*
6252  * Enumerated value for register field ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT
6253  *
6254  * Command done Interrupt enabled only if corresponding bit in interrupt mask
6255  * register is set
6256  */
6257 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_ENABLED 0x1
6258 
6259 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field. */
6260 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_LSB 2
6261 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field. */
6262 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_MSB 2
6263 /* The width in bits of the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field. */
6264 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_WIDTH 1
6265 /* The mask used to set the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field value. */
6266 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_SET_MSK 0x00000004
6267 /* The mask used to clear the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field value. */
6268 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_CLR_MSK 0xfffffffb
6269 /* The reset value of the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field. */
6270 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_RESET 0x0
6271 /* Extracts the ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT field value from a register. */
6272 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_GET(value) (((value) & 0x00000004) >> 2)
6273 /* Produces a ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT register field value suitable for setting the register. */
6274 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_SET(value) (((value) << 2) & 0x00000004)
6275 
6276 /*
6277  * Field : DATA_TRANSFER_OVER_INTERRUPT
6278  *
6279  * bit 3 Data transfer over (DTO)
6280  *
6281  * Field Enumeration Values:
6282  *
6283  * Enum | Value | Description
6284  * :----------------------------------------------------------|:------|:------------------------------------------------
6285  * ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6286  * ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_ENABLED | 0x1 | Data transfer over Interrupt enabled only if
6287  * : | | corresponding bit in interrupt mask register is
6288  * : | | set
6289  *
6290  * Field Access Macros:
6291  *
6292  */
6293 /*
6294  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT
6295  *
6296  * Interrupt disabled
6297  */
6298 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_DISABLED 0x0
6299 /*
6300  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT
6301  *
6302  * Data transfer over Interrupt enabled only if corresponding bit in interrupt mask
6303  * register is set
6304  */
6305 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_ENABLED 0x1
6306 
6307 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field. */
6308 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_LSB 3
6309 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field. */
6310 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_MSB 3
6311 /* The width in bits of the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field. */
6312 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_WIDTH 1
6313 /* The mask used to set the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field value. */
6314 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_SET_MSK 0x00000008
6315 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field value. */
6316 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_CLR_MSK 0xfffffff7
6317 /* The reset value of the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field. */
6318 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_RESET 0x0
6319 /* Extracts the ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT field value from a register. */
6320 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_GET(value) (((value) & 0x00000008) >> 3)
6321 /* Produces a ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT register field value suitable for setting the register. */
6322 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_SET(value) (((value) << 3) & 0x00000008)
6323 
6324 /*
6325  * Field : TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT
6326  *
6327  * bit 4 Transmit FIFO data request (TXDR)
6328  *
6329  * Field Enumeration Values:
6330  *
6331  * Enum | Value | Description
6332  * :------------------------------------------------------------------|:------|:---------------------------------------------
6333  * ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6334  * ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_ENABLED | 0x1 | Transmit FIFO data request Interrupt enabled
6335  * : | | only if corresponding bit in interrupt mask
6336  * : | | register is set
6337  *
6338  * Field Access Macros:
6339  *
6340  */
6341 /*
6342  * Enumerated value for register field ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT
6343  *
6344  * Interrupt disabled
6345  */
6346 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_DISABLED 0x0
6347 /*
6348  * Enumerated value for register field ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT
6349  *
6350  * Transmit FIFO data request Interrupt enabled only if corresponding bit in
6351  * interrupt mask register is set
6352  */
6353 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_ENABLED 0x1
6354 
6355 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field. */
6356 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_LSB 4
6357 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field. */
6358 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_MSB 4
6359 /* The width in bits of the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field. */
6360 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_WIDTH 1
6361 /* The mask used to set the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field value. */
6362 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_SET_MSK 0x00000010
6363 /* The mask used to clear the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field value. */
6364 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_CLR_MSK 0xffffffef
6365 /* The reset value of the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field. */
6366 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_RESET 0x0
6367 /* Extracts the ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT field value from a register. */
6368 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_GET(value) (((value) & 0x00000010) >> 4)
6369 /* Produces a ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT register field value suitable for setting the register. */
6370 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_SET(value) (((value) << 4) & 0x00000010)
6371 
6372 /*
6373  * Field : RECEIVE_FIFO_DATA_REQUEST_INTERRUPT
6374  *
6375  * bit 5 Receive FIFO data request (RXDR)
6376  *
6377  * Field Enumeration Values:
6378  *
6379  * Enum | Value | Description
6380  * :-----------------------------------------------------------------|:------|:-------------------------------------------------
6381  * ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6382  * ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_ENABLED | 0x1 | Receive FIFO data request Interrupt enabled only
6383  * : | | if corresponding bit in interrupt mask register
6384  * : | | is set
6385  *
6386  * Field Access Macros:
6387  *
6388  */
6389 /*
6390  * Enumerated value for register field ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT
6391  *
6392  * Interrupt disabled
6393  */
6394 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_DISABLED 0x0
6395 /*
6396  * Enumerated value for register field ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT
6397  *
6398  * Receive FIFO data request Interrupt enabled only if corresponding bit in
6399  * interrupt mask register is set
6400  */
6401 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_ENABLED 0x1
6402 
6403 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field. */
6404 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_LSB 5
6405 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field. */
6406 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_MSB 5
6407 /* The width in bits of the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field. */
6408 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_WIDTH 1
6409 /* The mask used to set the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field value. */
6410 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_SET_MSK 0x00000020
6411 /* The mask used to clear the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field value. */
6412 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_CLR_MSK 0xffffffdf
6413 /* The reset value of the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field. */
6414 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_RESET 0x0
6415 /* Extracts the ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT field value from a register. */
6416 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_GET(value) (((value) & 0x00000020) >> 5)
6417 /* Produces a ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT register field value suitable for setting the register. */
6418 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_SET(value) (((value) << 5) & 0x00000020)
6419 
6420 /*
6421  * Field : RESPONSE_CRC_ERROR_INTERRUPT
6422  *
6423  * bit 6 Response CRC error (RCRC)
6424  *
6425  * Field Enumeration Values:
6426  *
6427  * Enum | Value | Description
6428  * :----------------------------------------------------------|:------|:------------------------------------------------
6429  * ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6430  * ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_ENABLED | 0x1 | Response CRC error Interrupt enabled only if
6431  * : | | corresponding bit in interrupt mask register is
6432  * : | | set
6433  *
6434  * Field Access Macros:
6435  *
6436  */
6437 /*
6438  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT
6439  *
6440  * Interrupt disabled
6441  */
6442 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_DISABLED 0x0
6443 /*
6444  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT
6445  *
6446  * Response CRC error Interrupt enabled only if corresponding bit in interrupt mask
6447  * register is set
6448  */
6449 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_ENABLED 0x1
6450 
6451 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field. */
6452 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_LSB 6
6453 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field. */
6454 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_MSB 6
6455 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field. */
6456 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_WIDTH 1
6457 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field value. */
6458 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_SET_MSK 0x00000040
6459 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field value. */
6460 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_CLR_MSK 0xffffffbf
6461 /* The reset value of the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field. */
6462 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_RESET 0x0
6463 /* Extracts the ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT field value from a register. */
6464 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_GET(value) (((value) & 0x00000040) >> 6)
6465 /* Produces a ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT register field value suitable for setting the register. */
6466 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_SET(value) (((value) << 6) & 0x00000040)
6467 
6468 /*
6469  * Field : DATA_CRC_ERROR_INTERRUPT
6470  *
6471  * bit 7 Data CRC error (DCRC)
6472  *
6473  * Field Enumeration Values:
6474  *
6475  * Enum | Value | Description
6476  * :------------------------------------------------------|:------|:------------------------------------------------
6477  * ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6478  * ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_ENABLED | 0x1 | Data CRC error Interrupt enabled only if
6479  * : | | corresponding bit in interrupt mask register is
6480  * : | | set
6481  *
6482  * Field Access Macros:
6483  *
6484  */
6485 /*
6486  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT
6487  *
6488  * Interrupt disabled
6489  */
6490 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_DISABLED 0x0
6491 /*
6492  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT
6493  *
6494  * Data CRC error Interrupt enabled only if corresponding bit in interrupt mask
6495  * register is set
6496  */
6497 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_ENABLED 0x1
6498 
6499 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field. */
6500 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_LSB 7
6501 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field. */
6502 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_MSB 7
6503 /* The width in bits of the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field. */
6504 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_WIDTH 1
6505 /* The mask used to set the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field value. */
6506 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_SET_MSK 0x00000080
6507 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field value. */
6508 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_CLR_MSK 0xffffff7f
6509 /* The reset value of the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field. */
6510 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_RESET 0x0
6511 /* Extracts the ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT field value from a register. */
6512 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_GET(value) (((value) & 0x00000080) >> 7)
6513 /* Produces a ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT register field value suitable for setting the register. */
6514 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_SET(value) (((value) << 7) & 0x00000080)
6515 
6516 /*
6517  * Field : RESPONSE_TIMEOUT_INTERRUPT
6518  *
6519  * bit 8 Response timeout (RTO)
6520  *
6521  * Field Enumeration Values:
6522  *
6523  * Enum | Value | Description
6524  * :--------------------------------------------------------|:------|:------------------------------------------------
6525  * ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6526  * ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_ENABLED | 0x1 | Response timeout Interrupt enabled only if
6527  * : | | corresponding bit in interrupt mask register is
6528  * : | | set
6529  *
6530  * Field Access Macros:
6531  *
6532  */
6533 /*
6534  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT
6535  *
6536  * Interrupt disabled
6537  */
6538 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6539 /*
6540  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT
6541  *
6542  * Response timeout Interrupt enabled only if corresponding bit in interrupt mask
6543  * register is set
6544  */
6545 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6546 
6547 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field. */
6548 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_LSB 8
6549 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field. */
6550 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_MSB 8
6551 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field. */
6552 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_WIDTH 1
6553 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field value. */
6554 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_SET_MSK 0x00000100
6555 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field value. */
6556 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffeff
6557 /* The reset value of the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field. */
6558 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_RESET 0x0
6559 /* Extracts the ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT field value from a register. */
6560 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000100) >> 8)
6561 /* Produces a ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT register field value suitable for setting the register. */
6562 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_SET(value) (((value) << 8) & 0x00000100)
6563 
6564 /*
6565  * Field : DATA_READ_TIMEOUT_INTERRUPT
6566  *
6567  * bit 9 Data read timeout (DRTO)
6568  *
6569  * Field Enumeration Values:
6570  *
6571  * Enum | Value | Description
6572  * :---------------------------------------------------------|:------|:------------------------------------------------
6573  * ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6574  * ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_ENABLED | 0x1 | Data read timeout Interrupt enabled only if
6575  * : | | corresponding bit in interrupt mask register is
6576  * : | | set
6577  *
6578  * Field Access Macros:
6579  *
6580  */
6581 /*
6582  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT
6583  *
6584  * Interrupt disabled
6585  */
6586 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6587 /*
6588  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT
6589  *
6590  * Data read timeout Interrupt enabled only if corresponding bit in interrupt mask
6591  * register is set
6592  */
6593 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6594 
6595 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field. */
6596 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_LSB 9
6597 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field. */
6598 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_MSB 9
6599 /* The width in bits of the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field. */
6600 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_WIDTH 1
6601 /* The mask used to set the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field value. */
6602 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_SET_MSK 0x00000200
6603 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field value. */
6604 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffdff
6605 /* The reset value of the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field. */
6606 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_RESET 0x0
6607 /* Extracts the ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT field value from a register. */
6608 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000200) >> 9)
6609 /* Produces a ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT register field value suitable for setting the register. */
6610 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_SET(value) (((value) << 9) & 0x00000200)
6611 
6612 /*
6613  * Field : HOST_TIMEOUT_INTERRUPT
6614  *
6615  * bit 10 Data starvation by host timeout (HTO)/Volt_switch_int
6616  *
6617  * Field Enumeration Values:
6618  *
6619  * Enum | Value | Description
6620  * :----------------------------------------------------|:------|:-----------------------------------------------
6621  * ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6622  * ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_ENABLED | 0x1 | Data starvation by host timeout Interrupt
6623  * : | | enabled only if corresponding bit in interrupt
6624  * : | | mask register is set
6625  *
6626  * Field Access Macros:
6627  *
6628  */
6629 /*
6630  * Enumerated value for register field ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT
6631  *
6632  * Interrupt disabled
6633  */
6634 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6635 /*
6636  * Enumerated value for register field ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT
6637  *
6638  * Data starvation by host timeout Interrupt enabled only if corresponding bit in
6639  * interrupt mask register is set
6640  */
6641 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6642 
6643 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field. */
6644 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_LSB 10
6645 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field. */
6646 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_MSB 10
6647 /* The width in bits of the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field. */
6648 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_WIDTH 1
6649 /* The mask used to set the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field value. */
6650 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_SET_MSK 0x00000400
6651 /* The mask used to clear the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field value. */
6652 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffbff
6653 /* The reset value of the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field. */
6654 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_RESET 0x0
6655 /* Extracts the ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT field value from a register. */
6656 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000400) >> 10)
6657 /* Produces a ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT register field value suitable for setting the register. */
6658 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_SET(value) (((value) << 10) & 0x00000400)
6659 
6660 /*
6661  * Field : FIFO_UNDER_OVER_RUN_INTERRUPT
6662  *
6663  * bit 11 FIFO underrun/overrun error (FRUN)
6664  *
6665  * Field Enumeration Values:
6666  *
6667  * Enum | Value | Description
6668  * :-----------------------------------------------------------|:------|:----------------------------------------------
6669  * ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6670  * ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_ENABLED | 0x1 | FIFO underrun/overrun error Interrupt enabled
6671  * : | | only if corresponding bit in interrupt mask
6672  * : | | register is set
6673  *
6674  * Field Access Macros:
6675  *
6676  */
6677 /*
6678  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT
6679  *
6680  * Interrupt disabled
6681  */
6682 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_DISABLED 0x0
6683 /*
6684  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT
6685  *
6686  * FIFO underrun/overrun error Interrupt enabled only if corresponding bit in
6687  * interrupt mask register is set
6688  */
6689 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_ENABLED 0x1
6690 
6691 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field. */
6692 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_LSB 11
6693 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field. */
6694 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_MSB 11
6695 /* The width in bits of the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field. */
6696 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_WIDTH 1
6697 /* The mask used to set the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field value. */
6698 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_SET_MSK 0x00000800
6699 /* The mask used to clear the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field value. */
6700 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_CLR_MSK 0xfffff7ff
6701 /* The reset value of the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field. */
6702 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_RESET 0x0
6703 /* Extracts the ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT field value from a register. */
6704 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_GET(value) (((value) & 0x00000800) >> 11)
6705 /* Produces a ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT register field value suitable for setting the register. */
6706 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_SET(value) (((value) << 11) & 0x00000800)
6707 
6708 /*
6709  * Field : HARDWARE_LOCKED_WRITE_INTERRUPT
6710  *
6711  * bit 12 Hardware locked write error (HLE)
6712  *
6713  * Field Enumeration Values:
6714  *
6715  * Enum | Value | Description
6716  * :-------------------------------------------------------------|:------|:-----------------------------------------------
6717  * ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6718  * ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_ENABLED | 0x1 | Hardware locked write error Interrupt enabled
6719  * : | | only if corresponding bit in interrupt mask
6720  * : | | register is set
6721  *
6722  * Field Access Macros:
6723  *
6724  */
6725 /*
6726  * Enumerated value for register field ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT
6727  *
6728  * Interrupt disabled
6729  */
6730 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_DISABLED 0x0
6731 /*
6732  * Enumerated value for register field ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT
6733  *
6734  * Hardware locked write error Interrupt enabled only if corresponding bit in
6735  * interrupt mask register is set
6736  */
6737 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_ENABLED 0x1
6738 
6739 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field. */
6740 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_LSB 12
6741 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field. */
6742 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_MSB 12
6743 /* The width in bits of the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field. */
6744 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_WIDTH 1
6745 /* The mask used to set the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field value. */
6746 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_SET_MSK 0x00001000
6747 /* The mask used to clear the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field value. */
6748 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_CLR_MSK 0xffffefff
6749 /* The reset value of the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field. */
6750 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_RESET 0x0
6751 /* Extracts the ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT field value from a register. */
6752 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_GET(value) (((value) & 0x00001000) >> 12)
6753 /* Produces a ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT register field value suitable for setting the register. */
6754 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_SET(value) (((value) << 12) & 0x00001000)
6755 
6756 /*
6757  * Field : BUSY_COMPLETE_INTERRUPT_INTERRUPT
6758  *
6759  * bit 13 Start Bit Error(SBE)/Busy Complete Interrupt (BCI)
6760  *
6761  * Field Enumeration Values:
6762  *
6763  * Enum | Value | Description
6764  * :---------------------------------------------------------------|:------|:-----------------------------------------------
6765  * ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6766  * ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_ENABLED | 0x1 | Start Bit Error(SBE)/Busy Complete Interrupt
6767  * : | | enabled only if corresponding bit in interrupt
6768  * : | | mask register is set
6769  *
6770  * Field Access Macros:
6771  *
6772  */
6773 /*
6774  * Enumerated value for register field ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT
6775  *
6776  * Interrupt disabled
6777  */
6778 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_DISABLED 0x0
6779 /*
6780  * Enumerated value for register field ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT
6781  *
6782  * Start Bit Error(SBE)/Busy Complete Interrupt enabled only if corresponding bit
6783  * in interrupt mask register is set
6784  */
6785 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_ENABLED 0x1
6786 
6787 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field. */
6788 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_LSB 13
6789 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field. */
6790 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_MSB 13
6791 /* The width in bits of the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field. */
6792 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_WIDTH 1
6793 /* The mask used to set the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field value. */
6794 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_SET_MSK 0x00002000
6795 /* The mask used to clear the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field value. */
6796 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_CLR_MSK 0xffffdfff
6797 /* The reset value of the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field. */
6798 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_RESET 0x0
6799 /* Extracts the ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT field value from a register. */
6800 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_GET(value) (((value) & 0x00002000) >> 13)
6801 /* Produces a ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT register field value suitable for setting the register. */
6802 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_SET(value) (((value) << 13) & 0x00002000)
6803 
6804 /*
6805  * Field : AUTO_COMMAND_DONE_INTERRUPT
6806  *
6807  * bit 14 Auto command done (ACD)
6808  *
6809  * Field Enumeration Values:
6810  *
6811  * Enum | Value | Description
6812  * :---------------------------------------------------------|:------|:------------------------------------------------
6813  * ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6814  * ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_ENABLED | 0x1 | ACD Interrupt enabled only if corresponding bit
6815  * : | | in interrupt mask register is set
6816  *
6817  * Field Access Macros:
6818  *
6819  */
6820 /*
6821  * Enumerated value for register field ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT
6822  *
6823  * Interrupt disabled
6824  */
6825 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_DISABLED 0x0
6826 /*
6827  * Enumerated value for register field ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT
6828  *
6829  * ACD Interrupt enabled only if corresponding bit in interrupt mask register is
6830  * set
6831  */
6832 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_ENABLED 0x1
6833 
6834 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field. */
6835 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_LSB 14
6836 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field. */
6837 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_MSB 14
6838 /* The width in bits of the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field. */
6839 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_WIDTH 1
6840 /* The mask used to set the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field value. */
6841 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_SET_MSK 0x00004000
6842 /* The mask used to clear the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field value. */
6843 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_CLR_MSK 0xffffbfff
6844 /* The reset value of the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field. */
6845 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_RESET 0x0
6846 /* Extracts the ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT field value from a register. */
6847 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_GET(value) (((value) & 0x00004000) >> 14)
6848 /* Produces a ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT register field value suitable for setting the register. */
6849 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_SET(value) (((value) << 14) & 0x00004000)
6850 
6851 /*
6852  * Field : END_BIT_ERROR_INTERRUPT
6853  *
6854  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
6855  *
6856  * bit 15 End-bit error (read)/write no CRC (EBE)
6857  *
6858  * Field Enumeration Values:
6859  *
6860  * Enum | Value | Description
6861  * :-----------------------------------------------------|:------|:-----------------------------------------------
6862  * ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_DISABLED | 0x0 | Interrupt disabled
6863  * ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_ENABLED | 0x1 | End-bit error (read)/write no CRC (EBE)
6864  * : | | Interrupt enabled only if corresponding bit in
6865  * : | | interrupt mask register is set
6866  *
6867  * Field Access Macros:
6868  *
6869  */
6870 /*
6871  * Enumerated value for register field ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT
6872  *
6873  * Interrupt disabled
6874  */
6875 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_DISABLED 0x0
6876 /*
6877  * Enumerated value for register field ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT
6878  *
6879  * End-bit error (read)/write no CRC (EBE) Interrupt enabled only if corresponding
6880  * bit in interrupt mask register is set
6881  */
6882 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_ENABLED 0x1
6883 
6884 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field. */
6885 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_LSB 15
6886 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field. */
6887 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_MSB 15
6888 /* The width in bits of the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field. */
6889 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_WIDTH 1
6890 /* The mask used to set the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field value. */
6891 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_SET_MSK 0x00008000
6892 /* The mask used to clear the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field value. */
6893 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_CLR_MSK 0xffff7fff
6894 /* The reset value of the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field. */
6895 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_RESET 0x0
6896 /* Extracts the ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT field value from a register. */
6897 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_GET(value) (((value) & 0x00008000) >> 15)
6898 /* Produces a ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT register field value suitable for setting the register. */
6899 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_SET(value) (((value) << 15) & 0x00008000)
6900 
6901 /*
6902  * Field : SDIO_INTERRUPT_CARD0
6903  *
6904  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
6905  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
6906  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
6907  * enables interrupt; 0 masks interrupt).
6908  *
6909  * 0-No SDIO interrupt from card
6910  *
6911  * 1-SDIO interrupt from card
6912  *
6913  * In MMC-Ver3.3-only mode, bits always 0.
6914  *
6915  * Field Enumeration Values:
6916  *
6917  * Enum | Value | Description
6918  * :--------------------------------------------------|:------|:----------------------------
6919  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED | 0x0 | No SDIO interrupt from card
6920  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED | 0x1 | SDIO interrupt from card
6921  *
6922  * Field Access Macros:
6923  *
6924  */
6925 /*
6926  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0
6927  *
6928  * No SDIO interrupt from card
6929  */
6930 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED 0x0
6931 /*
6932  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0
6933  *
6934  * SDIO interrupt from card
6935  */
6936 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED 0x1
6937 
6938 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field. */
6939 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_LSB 16
6940 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field. */
6941 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_MSB 16
6942 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field. */
6943 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_WIDTH 1
6944 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field value. */
6945 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_SET_MSK 0x00010000
6946 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field value. */
6947 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_CLR_MSK 0xfffeffff
6948 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field. */
6949 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_RESET 0x0
6950 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 field value from a register. */
6951 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_GET(value) (((value) & 0x00010000) >> 16)
6952 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 register field value suitable for setting the register. */
6953 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_SET(value) (((value) << 16) & 0x00010000)
6954 
6955 /*
6956  * Field : SDIO_INTERRUPT_CARD1
6957  *
6958  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
6959  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
6960  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
6961  * enables interrupt; 0 masks interrupt).
6962  *
6963  * 0-No SDIO interrupt from card
6964  *
6965  * 1-SDIO interrupt from card
6966  *
6967  * In MMC-Ver3.3-only mode, bits always 0.
6968  *
6969  * Field Enumeration Values:
6970  *
6971  * Enum | Value | Description
6972  * :--------------------------------------------------|:------|:----------------------------
6973  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED | 0x0 | No SDIO interrupt from card
6974  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED | 0x1 | SDIO interrupt from card
6975  *
6976  * Field Access Macros:
6977  *
6978  */
6979 /*
6980  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1
6981  *
6982  * No SDIO interrupt from card
6983  */
6984 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED 0x0
6985 /*
6986  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1
6987  *
6988  * SDIO interrupt from card
6989  */
6990 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED 0x1
6991 
6992 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field. */
6993 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_LSB 17
6994 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field. */
6995 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_MSB 17
6996 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field. */
6997 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_WIDTH 1
6998 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field value. */
6999 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_SET_MSK 0x00020000
7000 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field value. */
7001 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_CLR_MSK 0xfffdffff
7002 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field. */
7003 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_RESET 0x0
7004 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 field value from a register. */
7005 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_GET(value) (((value) & 0x00020000) >> 17)
7006 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 register field value suitable for setting the register. */
7007 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_SET(value) (((value) << 17) & 0x00020000)
7008 
7009 /*
7010  * Field : SDIO_INTERRUPT_CARD2
7011  *
7012  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7013  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7014  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7015  * enables interrupt; 0 masks interrupt).
7016  *
7017  * 0-No SDIO interrupt from card
7018  *
7019  * 1-SDIO interrupt from card
7020  *
7021  * In MMC-Ver3.3-only mode, bits always 0.
7022  *
7023  * Field Enumeration Values:
7024  *
7025  * Enum | Value | Description
7026  * :--------------------------------------------------|:------|:----------------------------
7027  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED | 0x0 | No SDIO interrupt from card
7028  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED | 0x1 | SDIO interrupt from card
7029  *
7030  * Field Access Macros:
7031  *
7032  */
7033 /*
7034  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2
7035  *
7036  * No SDIO interrupt from card
7037  */
7038 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED 0x0
7039 /*
7040  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2
7041  *
7042  * SDIO interrupt from card
7043  */
7044 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED 0x1
7045 
7046 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field. */
7047 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_LSB 18
7048 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field. */
7049 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_MSB 18
7050 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field. */
7051 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_WIDTH 1
7052 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field value. */
7053 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_SET_MSK 0x00040000
7054 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field value. */
7055 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_CLR_MSK 0xfffbffff
7056 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field. */
7057 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_RESET 0x0
7058 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 field value from a register. */
7059 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_GET(value) (((value) & 0x00040000) >> 18)
7060 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 register field value suitable for setting the register. */
7061 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_SET(value) (((value) << 18) & 0x00040000)
7062 
7063 /*
7064  * Field : SDIO_INTERRUPT_CARD3
7065  *
7066  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7067  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7068  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7069  * enables interrupt; 0 masks interrupt).
7070  *
7071  * 0-No SDIO interrupt from card
7072  *
7073  * 1-SDIO interrupt from card
7074  *
7075  * In MMC-Ver3.3-only mode, bits always 0.
7076  *
7077  * Field Enumeration Values:
7078  *
7079  * Enum | Value | Description
7080  * :--------------------------------------------------|:------|:----------------------------
7081  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED | 0x0 | No SDIO interrupt from card
7082  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED | 0x1 | SDIO interrupt from card
7083  *
7084  * Field Access Macros:
7085  *
7086  */
7087 /*
7088  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3
7089  *
7090  * No SDIO interrupt from card
7091  */
7092 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED 0x0
7093 /*
7094  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3
7095  *
7096  * SDIO interrupt from card
7097  */
7098 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED 0x1
7099 
7100 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field. */
7101 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_LSB 19
7102 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field. */
7103 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_MSB 19
7104 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field. */
7105 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_WIDTH 1
7106 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field value. */
7107 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_SET_MSK 0x00080000
7108 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field value. */
7109 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_CLR_MSK 0xfff7ffff
7110 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field. */
7111 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_RESET 0x0
7112 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 field value from a register. */
7113 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_GET(value) (((value) & 0x00080000) >> 19)
7114 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 register field value suitable for setting the register. */
7115 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_SET(value) (((value) << 19) & 0x00080000)
7116 
7117 /*
7118  * Field : SDIO_INTERRUPT_CARD4
7119  *
7120  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7121  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7122  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7123  * enables interrupt; 0 masks interrupt).
7124  *
7125  * 0-No SDIO interrupt from card
7126  *
7127  * 1-SDIO interrupt from card
7128  *
7129  * In MMC-Ver3.3-only mode, bits always 0.
7130  *
7131  * Field Enumeration Values:
7132  *
7133  * Enum | Value | Description
7134  * :--------------------------------------------------|:------|:----------------------------
7135  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED | 0x0 | No SDIO interrupt from card
7136  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED | 0x1 | SDIO interrupt from card
7137  *
7138  * Field Access Macros:
7139  *
7140  */
7141 /*
7142  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4
7143  *
7144  * No SDIO interrupt from card
7145  */
7146 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED 0x0
7147 /*
7148  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4
7149  *
7150  * SDIO interrupt from card
7151  */
7152 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED 0x1
7153 
7154 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field. */
7155 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_LSB 20
7156 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field. */
7157 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_MSB 20
7158 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field. */
7159 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_WIDTH 1
7160 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field value. */
7161 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_SET_MSK 0x00100000
7162 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field value. */
7163 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_CLR_MSK 0xffefffff
7164 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field. */
7165 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_RESET 0x0
7166 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 field value from a register. */
7167 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_GET(value) (((value) & 0x00100000) >> 20)
7168 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 register field value suitable for setting the register. */
7169 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_SET(value) (((value) << 20) & 0x00100000)
7170 
7171 /*
7172  * Field : SDIO_INTERRUPT_CARD5
7173  *
7174  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7175  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7176  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7177  * enables interrupt; 0 masks interrupt).
7178  *
7179  * 0-No SDIO interrupt from card
7180  *
7181  * 1-SDIO interrupt from card
7182  *
7183  * In MMC-Ver3.3-only mode, bits always 0.
7184  *
7185  * Field Enumeration Values:
7186  *
7187  * Enum | Value | Description
7188  * :--------------------------------------------------|:------|:----------------------------
7189  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED | 0x0 | No SDIO interrupt from card
7190  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED | 0x1 | SDIO interrupt from card
7191  *
7192  * Field Access Macros:
7193  *
7194  */
7195 /*
7196  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5
7197  *
7198  * No SDIO interrupt from card
7199  */
7200 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED 0x0
7201 /*
7202  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5
7203  *
7204  * SDIO interrupt from card
7205  */
7206 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED 0x1
7207 
7208 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field. */
7209 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_LSB 21
7210 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field. */
7211 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_MSB 21
7212 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field. */
7213 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_WIDTH 1
7214 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field value. */
7215 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_SET_MSK 0x00200000
7216 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field value. */
7217 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_CLR_MSK 0xffdfffff
7218 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field. */
7219 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_RESET 0x0
7220 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 field value from a register. */
7221 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_GET(value) (((value) & 0x00200000) >> 21)
7222 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 register field value suitable for setting the register. */
7223 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_SET(value) (((value) << 21) & 0x00200000)
7224 
7225 /*
7226  * Field : SDIO_INTERRUPT_CARD6
7227  *
7228  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7229  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7230  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7231  * enables interrupt; 0 masks interrupt).
7232  *
7233  * 0-No SDIO interrupt from card
7234  *
7235  * 1-SDIO interrupt from card
7236  *
7237  * In MMC-Ver3.3-only mode, bits always 0.
7238  *
7239  * Field Enumeration Values:
7240  *
7241  * Enum | Value | Description
7242  * :--------------------------------------------------|:------|:----------------------------
7243  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED | 0x0 | No SDIO interrupt from card
7244  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED | 0x1 | SDIO interrupt from card
7245  *
7246  * Field Access Macros:
7247  *
7248  */
7249 /*
7250  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6
7251  *
7252  * No SDIO interrupt from card
7253  */
7254 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED 0x0
7255 /*
7256  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6
7257  *
7258  * SDIO interrupt from card
7259  */
7260 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED 0x1
7261 
7262 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field. */
7263 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_LSB 22
7264 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field. */
7265 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_MSB 22
7266 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field. */
7267 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_WIDTH 1
7268 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field value. */
7269 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_SET_MSK 0x00400000
7270 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field value. */
7271 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_CLR_MSK 0xffbfffff
7272 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field. */
7273 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_RESET 0x0
7274 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 field value from a register. */
7275 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_GET(value) (((value) & 0x00400000) >> 22)
7276 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 register field value suitable for setting the register. */
7277 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_SET(value) (((value) << 22) & 0x00400000)
7278 
7279 /*
7280  * Field : SDIO_INTERRUPT_CARD7
7281  *
7282  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7283  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7284  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7285  * enables interrupt; 0 masks interrupt).
7286  *
7287  * 0-No SDIO interrupt from card
7288  *
7289  * 1-SDIO interrupt from card
7290  *
7291  * In MMC-Ver3.3-only mode, bits always 0.
7292  *
7293  * Field Enumeration Values:
7294  *
7295  * Enum | Value | Description
7296  * :--------------------------------------------------|:------|:----------------------------
7297  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED | 0x0 | No SDIO interrupt from card
7298  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED | 0x1 | SDIO interrupt from card
7299  *
7300  * Field Access Macros:
7301  *
7302  */
7303 /*
7304  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7
7305  *
7306  * No SDIO interrupt from card
7307  */
7308 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED 0x0
7309 /*
7310  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7
7311  *
7312  * SDIO interrupt from card
7313  */
7314 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED 0x1
7315 
7316 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field. */
7317 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_LSB 23
7318 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field. */
7319 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_MSB 23
7320 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field. */
7321 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_WIDTH 1
7322 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field value. */
7323 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_SET_MSK 0x00800000
7324 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field value. */
7325 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_CLR_MSK 0xff7fffff
7326 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field. */
7327 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_RESET 0x0
7328 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 field value from a register. */
7329 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_GET(value) (((value) & 0x00800000) >> 23)
7330 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 register field value suitable for setting the register. */
7331 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_SET(value) (((value) << 23) & 0x00800000)
7332 
7333 /*
7334  * Field : SDIO_INTERRUPT_CARD8
7335  *
7336  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7337  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7338  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7339  * enables interrupt; 0 masks interrupt).
7340  *
7341  * 0-No SDIO interrupt from card
7342  *
7343  * 1-SDIO interrupt from card
7344  *
7345  * In MMC-Ver3.3-only mode, bits always 0.
7346  *
7347  * Field Enumeration Values:
7348  *
7349  * Enum | Value | Description
7350  * :--------------------------------------------------|:------|:----------------------------
7351  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED | 0x0 | No SDIO interrupt from card
7352  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED | 0x1 | SDIO interrupt from card
7353  *
7354  * Field Access Macros:
7355  *
7356  */
7357 /*
7358  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8
7359  *
7360  * No SDIO interrupt from card
7361  */
7362 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED 0x0
7363 /*
7364  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8
7365  *
7366  * SDIO interrupt from card
7367  */
7368 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED 0x1
7369 
7370 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field. */
7371 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_LSB 24
7372 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field. */
7373 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_MSB 24
7374 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field. */
7375 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_WIDTH 1
7376 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field value. */
7377 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_SET_MSK 0x01000000
7378 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field value. */
7379 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_CLR_MSK 0xfeffffff
7380 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field. */
7381 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_RESET 0x0
7382 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 field value from a register. */
7383 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_GET(value) (((value) & 0x01000000) >> 24)
7384 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 register field value suitable for setting the register. */
7385 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_SET(value) (((value) << 24) & 0x01000000)
7386 
7387 /*
7388  * Field : SDIO_INTERRUPT_CARD9
7389  *
7390  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7391  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7392  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7393  * enables interrupt; 0 masks interrupt).
7394  *
7395  * 0-No SDIO interrupt from card
7396  *
7397  * 1-SDIO interrupt from card
7398  *
7399  * In MMC-Ver3.3-only mode, bits always 0.
7400  *
7401  * Field Enumeration Values:
7402  *
7403  * Enum | Value | Description
7404  * :--------------------------------------------------|:------|:----------------------------
7405  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED | 0x0 | No SDIO interrupt from card
7406  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED | 0x1 | SDIO interrupt from card
7407  *
7408  * Field Access Macros:
7409  *
7410  */
7411 /*
7412  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9
7413  *
7414  * No SDIO interrupt from card
7415  */
7416 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED 0x0
7417 /*
7418  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9
7419  *
7420  * SDIO interrupt from card
7421  */
7422 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED 0x1
7423 
7424 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field. */
7425 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_LSB 25
7426 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field. */
7427 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_MSB 25
7428 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field. */
7429 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_WIDTH 1
7430 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field value. */
7431 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_SET_MSK 0x02000000
7432 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field value. */
7433 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_CLR_MSK 0xfdffffff
7434 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field. */
7435 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_RESET 0x0
7436 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 field value from a register. */
7437 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_GET(value) (((value) & 0x02000000) >> 25)
7438 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 register field value suitable for setting the register. */
7439 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_SET(value) (((value) << 25) & 0x02000000)
7440 
7441 /*
7442  * Field : SDIO_INTERRUPT_CARD10
7443  *
7444  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7445  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7446  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7447  * enables interrupt; 0 masks interrupt).
7448  *
7449  * 0-No SDIO interrupt from card
7450  *
7451  * 1-SDIO interrupt from card
7452  *
7453  * In MMC-Ver3.3-only mode, bits always 0.
7454  *
7455  * Field Enumeration Values:
7456  *
7457  * Enum | Value | Description
7458  * :---------------------------------------------------|:------|:----------------------------
7459  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED | 0x0 | No SDIO interrupt from card
7460  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED | 0x1 | SDIO interrupt from card
7461  *
7462  * Field Access Macros:
7463  *
7464  */
7465 /*
7466  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10
7467  *
7468  * No SDIO interrupt from card
7469  */
7470 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED 0x0
7471 /*
7472  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10
7473  *
7474  * SDIO interrupt from card
7475  */
7476 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED 0x1
7477 
7478 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field. */
7479 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_LSB 26
7480 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field. */
7481 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_MSB 26
7482 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field. */
7483 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_WIDTH 1
7484 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field value. */
7485 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_SET_MSK 0x04000000
7486 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field value. */
7487 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_CLR_MSK 0xfbffffff
7488 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field. */
7489 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_RESET 0x0
7490 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 field value from a register. */
7491 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_GET(value) (((value) & 0x04000000) >> 26)
7492 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 register field value suitable for setting the register. */
7493 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_SET(value) (((value) << 26) & 0x04000000)
7494 
7495 /*
7496  * Field : SDIO_INTERRUPT_CARD11
7497  *
7498  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7499  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7500  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7501  * enables interrupt; 0 masks interrupt).
7502  *
7503  * 0-No SDIO interrupt from card
7504  *
7505  * 1-SDIO interrupt from card
7506  *
7507  * In MMC-Ver3.3-only mode, bits always 0.
7508  *
7509  * Field Enumeration Values:
7510  *
7511  * Enum | Value | Description
7512  * :---------------------------------------------------|:------|:----------------------------
7513  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED | 0x0 | No SDIO interrupt from card
7514  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED | 0x1 | SDIO interrupt from card
7515  *
7516  * Field Access Macros:
7517  *
7518  */
7519 /*
7520  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11
7521  *
7522  * No SDIO interrupt from card
7523  */
7524 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED 0x0
7525 /*
7526  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11
7527  *
7528  * SDIO interrupt from card
7529  */
7530 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED 0x1
7531 
7532 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field. */
7533 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_LSB 27
7534 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field. */
7535 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_MSB 27
7536 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field. */
7537 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_WIDTH 1
7538 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field value. */
7539 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_SET_MSK 0x08000000
7540 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field value. */
7541 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_CLR_MSK 0xf7ffffff
7542 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field. */
7543 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_RESET 0x0
7544 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 field value from a register. */
7545 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_GET(value) (((value) & 0x08000000) >> 27)
7546 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 register field value suitable for setting the register. */
7547 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_SET(value) (((value) << 27) & 0x08000000)
7548 
7549 /*
7550  * Field : SDIO_INTERRUPT_CARD12
7551  *
7552  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7553  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7554  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7555  * enables interrupt; 0 masks interrupt).
7556  *
7557  * 0-No SDIO interrupt from card
7558  *
7559  * 1-SDIO interrupt from card
7560  *
7561  * In MMC-Ver3.3-only mode, bits always 0.
7562  *
7563  * Field Enumeration Values:
7564  *
7565  * Enum | Value | Description
7566  * :---------------------------------------------------|:------|:----------------------------
7567  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED | 0x0 | No SDIO interrupt from card
7568  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED | 0x1 | SDIO interrupt from card
7569  *
7570  * Field Access Macros:
7571  *
7572  */
7573 /*
7574  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12
7575  *
7576  * No SDIO interrupt from card
7577  */
7578 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED 0x0
7579 /*
7580  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12
7581  *
7582  * SDIO interrupt from card
7583  */
7584 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED 0x1
7585 
7586 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field. */
7587 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_LSB 28
7588 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field. */
7589 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_MSB 28
7590 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field. */
7591 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_WIDTH 1
7592 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field value. */
7593 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_SET_MSK 0x10000000
7594 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field value. */
7595 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_CLR_MSK 0xefffffff
7596 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field. */
7597 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_RESET 0x0
7598 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 field value from a register. */
7599 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_GET(value) (((value) & 0x10000000) >> 28)
7600 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 register field value suitable for setting the register. */
7601 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_SET(value) (((value) << 28) & 0x10000000)
7602 
7603 /*
7604  * Field : SDIO_INTERRUPT_CARD13
7605  *
7606  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7607  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7608  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7609  * enables interrupt; 0 masks interrupt).
7610  *
7611  * 0-No SDIO interrupt from card
7612  *
7613  * 1-SDIO interrupt from card
7614  *
7615  * In MMC-Ver3.3-only mode, bits always 0.
7616  *
7617  * Field Enumeration Values:
7618  *
7619  * Enum | Value | Description
7620  * :---------------------------------------------------|:------|:----------------------------
7621  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED | 0x0 | No SDIO interrupt from card
7622  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED | 0x1 | SDIO interrupt from card
7623  *
7624  * Field Access Macros:
7625  *
7626  */
7627 /*
7628  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13
7629  *
7630  * No SDIO interrupt from card
7631  */
7632 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED 0x0
7633 /*
7634  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13
7635  *
7636  * SDIO interrupt from card
7637  */
7638 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED 0x1
7639 
7640 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field. */
7641 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_LSB 29
7642 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field. */
7643 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_MSB 29
7644 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field. */
7645 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_WIDTH 1
7646 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field value. */
7647 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_SET_MSK 0x20000000
7648 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field value. */
7649 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_CLR_MSK 0xdfffffff
7650 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field. */
7651 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_RESET 0x0
7652 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 field value from a register. */
7653 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_GET(value) (((value) & 0x20000000) >> 29)
7654 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 register field value suitable for setting the register. */
7655 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_SET(value) (((value) << 29) & 0x20000000)
7656 
7657 /*
7658  * Field : SDIO_INTERRUPT_CARD14
7659  *
7660  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7661  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7662  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7663  * enables interrupt; 0 masks interrupt).
7664  *
7665  * 0-No SDIO interrupt from card
7666  *
7667  * 1-SDIO interrupt from card
7668  *
7669  * In MMC-Ver3.3-only mode, bits always 0.
7670  *
7671  * Field Enumeration Values:
7672  *
7673  * Enum | Value | Description
7674  * :---------------------------------------------------|:------|:----------------------------
7675  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED | 0x0 | No SDIO interrupt from card
7676  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED | 0x1 | SDIO interrupt from card
7677  *
7678  * Field Access Macros:
7679  *
7680  */
7681 /*
7682  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14
7683  *
7684  * No SDIO interrupt from card
7685  */
7686 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED 0x0
7687 /*
7688  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14
7689  *
7690  * SDIO interrupt from card
7691  */
7692 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED 0x1
7693 
7694 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field. */
7695 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_LSB 30
7696 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field. */
7697 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_MSB 30
7698 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field. */
7699 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_WIDTH 1
7700 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field value. */
7701 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_SET_MSK 0x40000000
7702 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field value. */
7703 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_CLR_MSK 0xbfffffff
7704 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field. */
7705 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_RESET 0x0
7706 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 field value from a register. */
7707 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_GET(value) (((value) & 0x40000000) >> 30)
7708 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 register field value suitable for setting the register. */
7709 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_SET(value) (((value) << 30) & 0x40000000)
7710 
7711 /*
7712  * Field : SDIO_INTERRUPT_CARD15
7713  *
7714  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
7715  * Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if
7716  * corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1
7717  * enables interrupt; 0 masks interrupt).
7718  *
7719  * 0-No SDIO interrupt from card
7720  *
7721  * 1-SDIO interrupt from card
7722  *
7723  * In MMC-Ver3.3-only mode, bits always 0.
7724  *
7725  * Field Enumeration Values:
7726  *
7727  * Enum | Value | Description
7728  * :---------------------------------------------------|:------|:----------------------------
7729  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED | 0x0 | No SDIO interrupt from card
7730  * ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED | 0x1 | SDIO interrupt from card
7731  *
7732  * Field Access Macros:
7733  *
7734  */
7735 /*
7736  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15
7737  *
7738  * No SDIO interrupt from card
7739  */
7740 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED 0x0
7741 /*
7742  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15
7743  *
7744  * SDIO interrupt from card
7745  */
7746 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED 0x1
7747 
7748 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field. */
7749 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_LSB 31
7750 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field. */
7751 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_MSB 31
7752 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field. */
7753 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_WIDTH 1
7754 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field value. */
7755 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_SET_MSK 0x80000000
7756 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field value. */
7757 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_CLR_MSK 0x7fffffff
7758 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field. */
7759 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_RESET 0x0
7760 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 field value from a register. */
7761 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_GET(value) (((value) & 0x80000000) >> 31)
7762 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 register field value suitable for setting the register. */
7763 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_SET(value) (((value) << 31) & 0x80000000)
7764 
7765 #ifndef __ASSEMBLY__
7766 /*
7767  * WARNING: The C register and register group struct declarations are provided for
7768  * convenience and illustrative purposes. They should, however, be used with
7769  * caution as the C language standard provides no guarantees about the alignment or
7770  * atomicity of device memory accesses. The recommended practice for coding device
7771  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7772  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7773  * alt_write_dword() functions for 64 bit registers.
7774  *
7775  * The struct declaration for register ALT_SDMMC_MINTSTS.
7776  */
7777 struct ALT_SDMMC_MINTSTS_s
7778 {
7779  const volatile uint32_t CARD_DETECT_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT */
7780  const volatile uint32_t RESPONSE_ERROR_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT */
7781  const volatile uint32_t COMMAND_DONE_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT */
7782  const volatile uint32_t DATA_TRANSFER_OVER_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT */
7783  const volatile uint32_t TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT */
7784  const volatile uint32_t RECEIVE_FIFO_DATA_REQUEST_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT */
7785  const volatile uint32_t RESPONSE_CRC_ERROR_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT */
7786  const volatile uint32_t DATA_CRC_ERROR_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT */
7787  const volatile uint32_t RESPONSE_TIMEOUT_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT */
7788  const volatile uint32_t DATA_READ_TIMEOUT_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT */
7789  const volatile uint32_t HOST_TIMEOUT_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT */
7790  const volatile uint32_t FIFO_UNDER_OVER_RUN_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT */
7791  const volatile uint32_t HARDWARE_LOCKED_WRITE_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT */
7792  const volatile uint32_t BUSY_COMPLETE_INTERRUPT_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT */
7793  const volatile uint32_t AUTO_COMMAND_DONE_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT */
7794  const volatile uint32_t END_BIT_ERROR_INTERRUPT : 1; /* ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT */
7795  const volatile uint32_t SDIO_INTERRUPT_CARD0 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0 */
7796  const volatile uint32_t SDIO_INTERRUPT_CARD1 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1 */
7797  const volatile uint32_t SDIO_INTERRUPT_CARD2 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2 */
7798  const volatile uint32_t SDIO_INTERRUPT_CARD3 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3 */
7799  const volatile uint32_t SDIO_INTERRUPT_CARD4 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4 */
7800  const volatile uint32_t SDIO_INTERRUPT_CARD5 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5 */
7801  const volatile uint32_t SDIO_INTERRUPT_CARD6 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6 */
7802  const volatile uint32_t SDIO_INTERRUPT_CARD7 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7 */
7803  const volatile uint32_t SDIO_INTERRUPT_CARD8 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8 */
7804  const volatile uint32_t SDIO_INTERRUPT_CARD9 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9 */
7805  const volatile uint32_t SDIO_INTERRUPT_CARD10 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10 */
7806  const volatile uint32_t SDIO_INTERRUPT_CARD11 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11 */
7807  const volatile uint32_t SDIO_INTERRUPT_CARD12 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12 */
7808  const volatile uint32_t SDIO_INTERRUPT_CARD13 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13 */
7809  const volatile uint32_t SDIO_INTERRUPT_CARD14 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14 */
7810  const volatile uint32_t SDIO_INTERRUPT_CARD15 : 1; /* ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15 */
7811 };
7812 
7813 /* The typedef declaration for register ALT_SDMMC_MINTSTS. */
7814 typedef struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
7815 #endif /* __ASSEMBLY__ */
7816 
7817 /* The reset value of the ALT_SDMMC_MINTSTS register. */
7818 #define ALT_SDMMC_MINTSTS_RESET 0x00000000
7819 /* The byte offset of the ALT_SDMMC_MINTSTS register from the beginning of the component. */
7820 #define ALT_SDMMC_MINTSTS_OFST 0x40
7821 /* The address of the ALT_SDMMC_MINTSTS register. */
7822 #define ALT_SDMMC_MINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_MINTSTS_OFST))
7823 
7824 /*
7825  * Register : Raw Interrupt Status Register - RINTSTS
7826  *
7827  * Name: Raw Interrupt Status Register
7828  *
7829  * Size: 32 bits
7830  *
7831  * Address Offset: 0x44
7832  *
7833  * Read/write access: write/read
7834  *
7835  * Register Layout
7836  *
7837  * Bits | Access | Reset | Description
7838  * :-----|:-------|:------|:----------------------------------------------------
7839  * [0] | RW | 0x0 | ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS
7840  * [1] | RW | 0x0 | ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS
7841  * [2] | RW | 0x0 | ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS
7842  * [3] | RW | 0x0 | ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS
7843  * [4] | RW | 0x0 | ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS
7844  * [5] | RW | 0x0 | ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS
7845  * [6] | RW | 0x0 | ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS
7846  * [7] | RW | 0x0 | ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS
7847  * [8] | RW | 0x0 | ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS
7848  * [9] | RW | 0x0 | ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS
7849  * [10] | RW | 0x0 | ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS
7850  * [11] | RW | 0x0 | ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS
7851  * [12] | RW | 0x0 | ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS
7852  * [13] | RW | 0x0 | ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS
7853  * [14] | RW | 0x0 | ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS
7854  * [15] | RW | 0x0 | ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS
7855  * [16] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0
7856  * [17] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1
7857  * [18] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2
7858  * [19] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3
7859  * [20] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4
7860  * [21] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5
7861  * [22] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6
7862  * [23] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7
7863  * [24] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8
7864  * [25] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9
7865  * [26] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10
7866  * [27] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11
7867  * [28] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12
7868  * [29] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13
7869  * [30] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14
7870  * [31] | RW | 0x0 | ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15
7871  *
7872  */
7873 /*
7874  * Field : CARD_DETECT_STATUS
7875  *
7876  * bit 0 Card detect (CD)
7877  *
7878  * Field Enumeration Values:
7879  *
7880  * Enum | Value | Description
7881  * :------------------------------------------------|:------|:------------------------------------------------
7882  * ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_DISABLED | 0x0 | Card detect Interrupt is not raised ;STATUS is
7883  * : | | logged regardless of interrupt mask status ,and
7884  * : | | value of '0' write to bit leaves bit intact
7885  * ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_ENABLED | 0x1 | CARD DETECT STATUS of 1 indicates interrupt is
7886  * : | | raised and writes of value 1 to bit clears the
7887  * : | | status bit
7888  *
7889  * Field Access Macros:
7890  *
7891  */
7892 /*
7893  * Enumerated value for register field ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS
7894  *
7895  * Card detect Interrupt is not raised ;STATUS is logged regardless of interrupt
7896  * mask status ,and value of '0' write to bit leaves bit intact
7897  */
7898 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_DISABLED 0x0
7899 /*
7900  * Enumerated value for register field ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS
7901  *
7902  * CARD DETECT STATUS of 1 indicates interrupt is raised and writes of value 1 to
7903  * bit clears the status bit
7904  */
7905 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_ENABLED 0x1
7906 
7907 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field. */
7908 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_LSB 0
7909 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field. */
7910 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_MSB 0
7911 /* The width in bits of the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field. */
7912 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_WIDTH 1
7913 /* The mask used to set the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field value. */
7914 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_SET_MSK 0x00000001
7915 /* The mask used to clear the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field value. */
7916 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_CLR_MSK 0xfffffffe
7917 /* The reset value of the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field. */
7918 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_RESET 0x0
7919 /* Extracts the ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS field value from a register. */
7920 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_GET(value) (((value) & 0x00000001) >> 0)
7921 /* Produces a ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS register field value suitable for setting the register. */
7922 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_SET(value) (((value) << 0) & 0x00000001)
7923 
7924 /*
7925  * Field : RESPONSE_ERROR_STATUS
7926  *
7927  * bit 1 Response error (RE)
7928  *
7929  * Field Enumeration Values:
7930  *
7931  * Enum | Value | Description
7932  * :---------------------------------------------------|:------|:-----------------------------------------------
7933  * ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_DISABLED | 0x0 | RE Interrupt is not raised ;STATUS is logged
7934  * : | | regardless of interrupt mask status ,and value
7935  * : | | of '0' write to bit leaves bit intact
7936  * ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_ENABLED | 0x1 | Response error STATUS of 1 indicates interrupt
7937  * : | | is raised and writes of value 1 to bit clears
7938  * : | | the status bit
7939  *
7940  * Field Access Macros:
7941  *
7942  */
7943 /*
7944  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS
7945  *
7946  * RE Interrupt is not raised ;STATUS is logged regardless of interrupt mask status
7947  * ,and value of '0' write to bit leaves bit intact
7948  */
7949 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_DISABLED 0x0
7950 /*
7951  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS
7952  *
7953  * Response error STATUS of 1 indicates interrupt is raised and writes of value 1
7954  * to bit clears the status bit
7955  */
7956 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_ENABLED 0x1
7957 
7958 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field. */
7959 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_LSB 1
7960 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field. */
7961 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_MSB 1
7962 /* The width in bits of the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field. */
7963 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_WIDTH 1
7964 /* The mask used to set the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field value. */
7965 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_SET_MSK 0x00000002
7966 /* The mask used to clear the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field value. */
7967 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_CLR_MSK 0xfffffffd
7968 /* The reset value of the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field. */
7969 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_RESET 0x0
7970 /* Extracts the ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS field value from a register. */
7971 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_GET(value) (((value) & 0x00000002) >> 1)
7972 /* Produces a ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS register field value suitable for setting the register. */
7973 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_SET(value) (((value) << 1) & 0x00000002)
7974 
7975 /*
7976  * Field : COMMAND_DONE_STATUS
7977  *
7978  * bit 2 Command done (CD)
7979  *
7980  * Field Enumeration Values:
7981  *
7982  * Enum | Value | Description
7983  * :-------------------------------------------------|:------|:------------------------------------------------
7984  * ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_DISABLED | 0x0 | CD Interrupt is not raised ;STATUS is logged
7985  * : | | regardless of interrupt mask status ,and value
7986  * : | | of '0' write to bit leaves bit intact
7987  * ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_ENABLED | 0x1 | Command done STATUS of 1 indicates interrupt is
7988  * : | | raised and writes of value 1 to bit clears the
7989  * : | | status bit
7990  *
7991  * Field Access Macros:
7992  *
7993  */
7994 /*
7995  * Enumerated value for register field ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS
7996  *
7997  * CD Interrupt is not raised ;STATUS is logged regardless of interrupt mask status
7998  * ,and value of '0' write to bit leaves bit intact
7999  */
8000 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_DISABLED 0x0
8001 /*
8002  * Enumerated value for register field ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS
8003  *
8004  * Command done STATUS of 1 indicates interrupt is raised and writes of value 1 to
8005  * bit clears the status bit
8006  */
8007 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_ENABLED 0x1
8008 
8009 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field. */
8010 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_LSB 2
8011 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field. */
8012 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_MSB 2
8013 /* The width in bits of the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field. */
8014 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_WIDTH 1
8015 /* The mask used to set the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field value. */
8016 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_SET_MSK 0x00000004
8017 /* The mask used to clear the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field value. */
8018 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_CLR_MSK 0xfffffffb
8019 /* The reset value of the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field. */
8020 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_RESET 0x0
8021 /* Extracts the ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS field value from a register. */
8022 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_GET(value) (((value) & 0x00000004) >> 2)
8023 /* Produces a ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS register field value suitable for setting the register. */
8024 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_SET(value) (((value) << 2) & 0x00000004)
8025 
8026 /*
8027  * Field : DATA_TRANSFER_OVER_STATUS
8028  *
8029  * bit 3 Data transfer over (DTO)
8030  *
8031  * Field Enumeration Values:
8032  *
8033  * Enum | Value | Description
8034  * :-------------------------------------------------------|:------|:-------------------------------------------------
8035  * ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_DISABLED | 0x0 | DTO Interrupt is not raised ;STATUS is logged
8036  * : | | regardless of interrupt mask status ,and value
8037  * : | | of '0' write to bit leaves bit intact
8038  * ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_ENABLED | 0x1 | Data transfer over STATUS of 1 indicates
8039  * : | | interrupt is raised and writes of value 1 to bit
8040  * : | | clears the status bit
8041  *
8042  * Field Access Macros:
8043  *
8044  */
8045 /*
8046  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS
8047  *
8048  * DTO Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8049  * status ,and value of '0' write to bit leaves bit intact
8050  */
8051 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_DISABLED 0x0
8052 /*
8053  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS
8054  *
8055  * Data transfer over STATUS of 1 indicates interrupt is raised and writes of value
8056  * 1 to bit clears the status bit
8057  */
8058 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_ENABLED 0x1
8059 
8060 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field. */
8061 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_LSB 3
8062 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field. */
8063 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_MSB 3
8064 /* The width in bits of the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field. */
8065 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_WIDTH 1
8066 /* The mask used to set the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field value. */
8067 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_SET_MSK 0x00000008
8068 /* The mask used to clear the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field value. */
8069 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_CLR_MSK 0xfffffff7
8070 /* The reset value of the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field. */
8071 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_RESET 0x0
8072 /* Extracts the ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS field value from a register. */
8073 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_GET(value) (((value) & 0x00000008) >> 3)
8074 /* Produces a ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS register field value suitable for setting the register. */
8075 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_SET(value) (((value) << 3) & 0x00000008)
8076 
8077 /*
8078  * Field : TRANSMIT_RECEIVE_FIFO_DATA_STATUS
8079  *
8080  * bit 4 Transmit FIFO data request (TXDR)
8081  *
8082  * Field Enumeration Values:
8083  *
8084  * Enum | Value | Description
8085  * :---------------------------------------------------------------|:------|:-------------------------------------------------
8086  * ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_DISABLED | 0x0 | TXDR Interrupt is not raised ;STATUS is logged
8087  * : | | regardless of interrupt mask status ,and value
8088  * : | | of '0' write to bit leaves bit intact
8089  * ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_ENABLED | 0x1 | Transmit FIFO data request STATUS of 1 indicates
8090  * : | | interrupt is raised and writes of value 1 to bit
8091  * : | | clears the status bit
8092  *
8093  * Field Access Macros:
8094  *
8095  */
8096 /*
8097  * Enumerated value for register field ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS
8098  *
8099  * TXDR Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8100  * status ,and value of '0' write to bit leaves bit intact
8101  */
8102 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_DISABLED 0x0
8103 /*
8104  * Enumerated value for register field ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS
8105  *
8106  * Transmit FIFO data request STATUS of 1 indicates interrupt is raised and writes
8107  * of value 1 to bit clears the status bit
8108  */
8109 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_ENABLED 0x1
8110 
8111 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field. */
8112 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_LSB 4
8113 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field. */
8114 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_MSB 4
8115 /* The width in bits of the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field. */
8116 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_WIDTH 1
8117 /* The mask used to set the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field value. */
8118 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_SET_MSK 0x00000010
8119 /* The mask used to clear the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field value. */
8120 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_CLR_MSK 0xffffffef
8121 /* The reset value of the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field. */
8122 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_RESET 0x0
8123 /* Extracts the ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS field value from a register. */
8124 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_GET(value) (((value) & 0x00000010) >> 4)
8125 /* Produces a ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS register field value suitable for setting the register. */
8126 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_SET(value) (((value) << 4) & 0x00000010)
8127 
8128 /*
8129  * Field : RECEIVE_FIFO_DATA_REQUEST_STATUS
8130  *
8131  * bit 5 Receive FIFO data request (RXDR)
8132  *
8133  * Field Enumeration Values:
8134  *
8135  * Enum | Value | Description
8136  * :--------------------------------------------------------------|:------|:-------------------------------------------------
8137  * ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_DISABLED | 0x0 | RXDR Interrupt is not raised ;STATUS is logged
8138  * : | | regardless of interrupt mask status ,and value
8139  * : | | of '0' write to bit leaves bit intact
8140  * ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_ENABLED | 0x1 | Receive FIFO data request STATUS of 1 indicates
8141  * : | | interrupt is raised and writes of value 1 to bit
8142  * : | | clears the status bit
8143  *
8144  * Field Access Macros:
8145  *
8146  */
8147 /*
8148  * Enumerated value for register field ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS
8149  *
8150  * RXDR Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8151  * status ,and value of '0' write to bit leaves bit intact
8152  */
8153 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_DISABLED 0x0
8154 /*
8155  * Enumerated value for register field ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS
8156  *
8157  * Receive FIFO data request STATUS of 1 indicates interrupt is raised and writes
8158  * of value 1 to bit clears the status bit
8159  */
8160 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_ENABLED 0x1
8161 
8162 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field. */
8163 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_LSB 5
8164 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field. */
8165 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_MSB 5
8166 /* The width in bits of the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field. */
8167 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_WIDTH 1
8168 /* The mask used to set the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field value. */
8169 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_SET_MSK 0x00000020
8170 /* The mask used to clear the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field value. */
8171 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_CLR_MSK 0xffffffdf
8172 /* The reset value of the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field. */
8173 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_RESET 0x0
8174 /* Extracts the ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS field value from a register. */
8175 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_GET(value) (((value) & 0x00000020) >> 5)
8176 /* Produces a ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS register field value suitable for setting the register. */
8177 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_SET(value) (((value) << 5) & 0x00000020)
8178 
8179 /*
8180  * Field : RESPONSE_CRC_ERROR_STATUS
8181  *
8182  * bit 6 Response CRC error (RCRC)
8183  *
8184  * Field Enumeration Values:
8185  *
8186  * Enum | Value | Description
8187  * :-------------------------------------------------------|:------|:-------------------------------------------------
8188  * ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_DISABLED | 0x0 | RCRC Interrupt is not raised ;STATUS is logged
8189  * : | | regardless of interrupt mask status ,and value
8190  * : | | of '0' write to bit leaves bit intact
8191  * ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_ENABLED | 0x1 | Response CRC error STATUS of 1 indicates
8192  * : | | interrupt is raised and writes of value 1 to bit
8193  * : | | clears the status bit
8194  *
8195  * Field Access Macros:
8196  *
8197  */
8198 /*
8199  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS
8200  *
8201  * RCRC Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8202  * status ,and value of '0' write to bit leaves bit intact
8203  */
8204 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_DISABLED 0x0
8205 /*
8206  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS
8207  *
8208  * Response CRC error STATUS of 1 indicates interrupt is raised and writes of value
8209  * 1 to bit clears the status bit
8210  */
8211 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_ENABLED 0x1
8212 
8213 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field. */
8214 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_LSB 6
8215 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field. */
8216 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_MSB 6
8217 /* The width in bits of the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field. */
8218 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_WIDTH 1
8219 /* The mask used to set the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field value. */
8220 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_SET_MSK 0x00000040
8221 /* The mask used to clear the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field value. */
8222 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_CLR_MSK 0xffffffbf
8223 /* The reset value of the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field. */
8224 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_RESET 0x0
8225 /* Extracts the ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS field value from a register. */
8226 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_GET(value) (((value) & 0x00000040) >> 6)
8227 /* Produces a ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS register field value suitable for setting the register. */
8228 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_SET(value) (((value) << 6) & 0x00000040)
8229 
8230 /*
8231  * Field : DATA_CRC_ERROR_STATUS
8232  *
8233  * bit 7 Data CRC error (DCRC)
8234  *
8235  * Field Enumeration Values:
8236  *
8237  * Enum | Value | Description
8238  * :---------------------------------------------------|:------|:-----------------------------------------------
8239  * ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_DISABLED | 0x0 | DCRC Interrupt is not raised ;STATUS is logged
8240  * : | | regardless of interrupt mask status ,and value
8241  * : | | of '0' write to bit leaves bit intact
8242  * ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_ENABLED | 0x1 | Data CRC error STATUS of 1 indicates interrupt
8243  * : | | is raised and writes of value 1 to bit clears
8244  * : | | the status bit
8245  *
8246  * Field Access Macros:
8247  *
8248  */
8249 /*
8250  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS
8251  *
8252  * DCRC Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8253  * status ,and value of '0' write to bit leaves bit intact
8254  */
8255 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_DISABLED 0x0
8256 /*
8257  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS
8258  *
8259  * Data CRC error STATUS of 1 indicates interrupt is raised and writes of value 1
8260  * to bit clears the status bit
8261  */
8262 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_ENABLED 0x1
8263 
8264 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field. */
8265 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_LSB 7
8266 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field. */
8267 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_MSB 7
8268 /* The width in bits of the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field. */
8269 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_WIDTH 1
8270 /* The mask used to set the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field value. */
8271 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_SET_MSK 0x00000080
8272 /* The mask used to clear the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field value. */
8273 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_CLR_MSK 0xffffff7f
8274 /* The reset value of the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field. */
8275 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_RESET 0x0
8276 /* Extracts the ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS field value from a register. */
8277 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_GET(value) (((value) & 0x00000080) >> 7)
8278 /* Produces a ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS register field value suitable for setting the register. */
8279 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_SET(value) (((value) << 7) & 0x00000080)
8280 
8281 /*
8282  * Field : RESPONSE_TIMEOUT_STATUS
8283  *
8284  * bit 8 Response timeout (RTO)
8285  *
8286  * Field Enumeration Values:
8287  *
8288  * Enum | Value | Description
8289  * :-----------------------------------------------------|:------|:-------------------------------------------------
8290  * ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_DISABLED | 0x0 | RTO Interrupt is not raised ;STATUS is logged
8291  * : | | regardless of interrupt mask status ,and value
8292  * : | | of '0' write to bit leaves bit intact
8293  * ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_ENABLED | 0x1 | Response timeout STATUS of 1 indicates
8294  * : | | interrupt is raised and writes of value 1 to bit
8295  * : | | clears the status bit
8296  *
8297  * Field Access Macros:
8298  *
8299  */
8300 /*
8301  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS
8302  *
8303  * RTO Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8304  * status ,and value of '0' write to bit leaves bit intact
8305  */
8306 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_DISABLED 0x0
8307 /*
8308  * Enumerated value for register field ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS
8309  *
8310  * Response timeout STATUS of 1 indicates interrupt is raised and writes of value
8311  * 1 to bit clears the status bit
8312  */
8313 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_ENABLED 0x1
8314 
8315 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field. */
8316 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_LSB 8
8317 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field. */
8318 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_MSB 8
8319 /* The width in bits of the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field. */
8320 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_WIDTH 1
8321 /* The mask used to set the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field value. */
8322 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_SET_MSK 0x00000100
8323 /* The mask used to clear the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field value. */
8324 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_CLR_MSK 0xfffffeff
8325 /* The reset value of the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field. */
8326 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_RESET 0x0
8327 /* Extracts the ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS field value from a register. */
8328 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_GET(value) (((value) & 0x00000100) >> 8)
8329 /* Produces a ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS register field value suitable for setting the register. */
8330 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_SET(value) (((value) << 8) & 0x00000100)
8331 
8332 /*
8333  * Field : DATA_READ_TIMEOUT_STATUS
8334  *
8335  * bit 9 Data read timeout (DRTO)
8336  *
8337  * Field Enumeration Values:
8338  *
8339  * Enum | Value | Description
8340  * :------------------------------------------------------|:------|:-------------------------------------------------
8341  * ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_DISABLED | 0x0 | DRTO Interrupt is not raised ;STATUS is logged
8342  * : | | regardless of interrupt mask status ,and value
8343  * : | | of '0' write to bit leaves bit intact
8344  * ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_ENABLED | 0x1 | Data read timeout STATUS of 1 indicates
8345  * : | | interrupt is raised and writes of value 1 to bit
8346  * : | | clears the status bit
8347  *
8348  * Field Access Macros:
8349  *
8350  */
8351 /*
8352  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS
8353  *
8354  * DRTO Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8355  * status ,and value of '0' write to bit leaves bit intact
8356  */
8357 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_DISABLED 0x0
8358 /*
8359  * Enumerated value for register field ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS
8360  *
8361  * Data read timeout STATUS of 1 indicates interrupt is raised and writes of value
8362  * 1 to bit clears the status bit
8363  */
8364 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_ENABLED 0x1
8365 
8366 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field. */
8367 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_LSB 9
8368 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field. */
8369 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_MSB 9
8370 /* The width in bits of the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field. */
8371 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_WIDTH 1
8372 /* The mask used to set the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field value. */
8373 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_SET_MSK 0x00000200
8374 /* The mask used to clear the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field value. */
8375 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_CLR_MSK 0xfffffdff
8376 /* The reset value of the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field. */
8377 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_RESET 0x0
8378 /* Extracts the ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS field value from a register. */
8379 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_GET(value) (((value) & 0x00000200) >> 9)
8380 /* Produces a ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS register field value suitable for setting the register. */
8381 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_SET(value) (((value) << 9) & 0x00000200)
8382 
8383 /*
8384  * Field : HOST_TIMEOUT_STATUS
8385  *
8386  * bit 10 Data starvation by host timeout (HTO)/Volt_switch_int
8387  *
8388  * Field Enumeration Values:
8389  *
8390  * Enum | Value | Description
8391  * :-------------------------------------------------|:------|:-----------------------------------------------
8392  * ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_DISABLED | 0x0 | HTO Interrupt is not raised ;STATUS is logged
8393  * : | | regardless of interrupt mask status ,and value
8394  * : | | of '0' write to bit leaves bit intact
8395  * ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_ENABLED | 0x1 | Data starvation by host timeout STATUS of 1
8396  * : | | indicates interrupt is raised and writes of
8397  * : | | value 1 to bit clears the status bit
8398  *
8399  * Field Access Macros:
8400  *
8401  */
8402 /*
8403  * Enumerated value for register field ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS
8404  *
8405  * HTO Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8406  * status ,and value of '0' write to bit leaves bit intact
8407  */
8408 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_DISABLED 0x0
8409 /*
8410  * Enumerated value for register field ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS
8411  *
8412  * Data starvation by host timeout STATUS of 1 indicates interrupt is raised and
8413  * writes of value 1 to bit clears the status bit
8414  */
8415 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_ENABLED 0x1
8416 
8417 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field. */
8418 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_LSB 10
8419 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field. */
8420 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_MSB 10
8421 /* The width in bits of the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field. */
8422 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_WIDTH 1
8423 /* The mask used to set the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field value. */
8424 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_SET_MSK 0x00000400
8425 /* The mask used to clear the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field value. */
8426 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_CLR_MSK 0xfffffbff
8427 /* The reset value of the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field. */
8428 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_RESET 0x0
8429 /* Extracts the ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS field value from a register. */
8430 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_GET(value) (((value) & 0x00000400) >> 10)
8431 /* Produces a ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS register field value suitable for setting the register. */
8432 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_SET(value) (((value) << 10) & 0x00000400)
8433 
8434 /*
8435  * Field : FIFO_UNDER_OVER_RUN_STATUS
8436  *
8437  * bit 11 FIFO underrun/overrun error (FRUN)
8438  *
8439  * Field Enumeration Values:
8440  *
8441  * Enum | Value | Description
8442  * :--------------------------------------------------------|:------|:-----------------------------------------------
8443  * ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_DISABLED | 0x0 | FRUN Interrupt is not raised ;STATUS is logged
8444  * : | | regardless of interrupt mask status ,and value
8445  * : | | of '0' write to bit leaves bit intact
8446  * ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_ENABLED | 0x1 | FIFO underrun/overrun error STATUS of 1
8447  * : | | indicates interrupt is raised and writes of
8448  * : | | value 1 to bit clears the status bit
8449  *
8450  * Field Access Macros:
8451  *
8452  */
8453 /*
8454  * Enumerated value for register field ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS
8455  *
8456  * FRUN Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8457  * status ,and value of '0' write to bit leaves bit intact
8458  */
8459 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_DISABLED 0x0
8460 /*
8461  * Enumerated value for register field ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS
8462  *
8463  * FIFO underrun/overrun error STATUS of 1 indicates interrupt is raised and writes
8464  * of value 1 to bit clears the status bit
8465  */
8466 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_ENABLED 0x1
8467 
8468 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field. */
8469 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_LSB 11
8470 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field. */
8471 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_MSB 11
8472 /* The width in bits of the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field. */
8473 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_WIDTH 1
8474 /* The mask used to set the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field value. */
8475 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_SET_MSK 0x00000800
8476 /* The mask used to clear the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field value. */
8477 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_CLR_MSK 0xfffff7ff
8478 /* The reset value of the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field. */
8479 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_RESET 0x0
8480 /* Extracts the ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS field value from a register. */
8481 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_GET(value) (((value) & 0x00000800) >> 11)
8482 /* Produces a ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS register field value suitable for setting the register. */
8483 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_SET(value) (((value) << 11) & 0x00000800)
8484 
8485 /*
8486  * Field : HARDWARE_LOCKED_WRITE_STATUS
8487  *
8488  * bit 12 Hardware locked write error (HLE)
8489  *
8490  * Field Enumeration Values:
8491  *
8492  * Enum | Value | Description
8493  * :----------------------------------------------------------|:------|:-----------------------------------------------
8494  * ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_DISABLED | 0x0 | HLE Interrupt is not raised ;STATUS is logged
8495  * : | | regardless of interrupt mask status ,and value
8496  * : | | of '0' write to bit leaves bit intact
8497  * ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_ENABLED | 0x1 | Hardware locked write error STATUS of 1
8498  * : | | indicates interrupt is raised and writes of
8499  * : | | value 1 to bit clears the status bit
8500  *
8501  * Field Access Macros:
8502  *
8503  */
8504 /*
8505  * Enumerated value for register field ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS
8506  *
8507  * HLE Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8508  * status ,and value of '0' write to bit leaves bit intact
8509  */
8510 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_DISABLED 0x0
8511 /*
8512  * Enumerated value for register field ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS
8513  *
8514  * Hardware locked write error STATUS of 1 indicates interrupt is raised and
8515  * writes of value 1 to bit clears the status bit
8516  */
8517 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_ENABLED 0x1
8518 
8519 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field. */
8520 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_LSB 12
8521 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field. */
8522 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_MSB 12
8523 /* The width in bits of the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field. */
8524 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_WIDTH 1
8525 /* The mask used to set the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field value. */
8526 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_SET_MSK 0x00001000
8527 /* The mask used to clear the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field value. */
8528 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_CLR_MSK 0xffffefff
8529 /* The reset value of the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field. */
8530 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_RESET 0x0
8531 /* Extracts the ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS field value from a register. */
8532 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_GET(value) (((value) & 0x00001000) >> 12)
8533 /* Produces a ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS register field value suitable for setting the register. */
8534 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_SET(value) (((value) << 12) & 0x00001000)
8535 
8536 /*
8537  * Field : BUSY_COMPLETE_STATUS
8538  *
8539  * bit 13 Start Bit Error(SBE)/Busy Complete STATUS (BCI)
8540  *
8541  * Field Enumeration Values:
8542  *
8543  * Enum | Value | Description
8544  * :--------------------------------------------------|:------|:-----------------------------------------------
8545  * ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_DISABLED | 0x0 | BCI Interrupt is not raised ;STATUS is logged
8546  * : | | regardless of interrupt mask status ,and value
8547  * : | | of '0' write to bit leaves bit intact
8548  * ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_ENABLED | 0x1 | Start Bit Error(SBE)/Busy Complete STATUS of 1
8549  * : | | indicates interrupt is raised and writes of
8550  * : | | value 1 to bit clears the status bit
8551  *
8552  * Field Access Macros:
8553  *
8554  */
8555 /*
8556  * Enumerated value for register field ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS
8557  *
8558  * BCI Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8559  * status ,and value of '0' write to bit leaves bit intact
8560  */
8561 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_DISABLED 0x0
8562 /*
8563  * Enumerated value for register field ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS
8564  *
8565  * Start Bit Error(SBE)/Busy Complete STATUS of 1 indicates interrupt is raised and
8566  * writes of value 1 to bit clears the status bit
8567  */
8568 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_ENABLED 0x1
8569 
8570 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field. */
8571 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_LSB 13
8572 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field. */
8573 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_MSB 13
8574 /* The width in bits of the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field. */
8575 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_WIDTH 1
8576 /* The mask used to set the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field value. */
8577 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_SET_MSK 0x00002000
8578 /* The mask used to clear the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field value. */
8579 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_CLR_MSK 0xffffdfff
8580 /* The reset value of the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field. */
8581 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_RESET 0x0
8582 /* Extracts the ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS field value from a register. */
8583 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_GET(value) (((value) & 0x00002000) >> 13)
8584 /* Produces a ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS register field value suitable for setting the register. */
8585 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_SET(value) (((value) << 13) & 0x00002000)
8586 
8587 /*
8588  * Field : AUTO_COMMAND_DONE_STATUS
8589  *
8590  * bit 14 Auto command done (ACD)
8591  *
8592  * Field Enumeration Values:
8593  *
8594  * Enum | Value | Description
8595  * :------------------------------------------------------|:------|:-----------------------------------------------
8596  * ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_DISABLED | 0x0 | ACD Interrupt is not raised ;STATUS is logged
8597  * : | | regardless of interrupt mask status ,and value
8598  * : | | of '0' write to bit leaves bit intact
8599  * ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_ENABLED | 0x1 | ACD STATUS of 1 indicates interrupt is raised
8600  * : | | and writes of value 1 to bit clears the status
8601  * : | | bit
8602  *
8603  * Field Access Macros:
8604  *
8605  */
8606 /*
8607  * Enumerated value for register field ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS
8608  *
8609  * ACD Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8610  * status ,and value of '0' write to bit leaves bit intact
8611  */
8612 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_DISABLED 0x0
8613 /*
8614  * Enumerated value for register field ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS
8615  *
8616  * ACD STATUS of 1 indicates interrupt is raised and writes of value 1 to bit
8617  * clears the status bit
8618  */
8619 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_ENABLED 0x1
8620 
8621 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field. */
8622 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_LSB 14
8623 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field. */
8624 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_MSB 14
8625 /* The width in bits of the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field. */
8626 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_WIDTH 1
8627 /* The mask used to set the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field value. */
8628 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_SET_MSK 0x00004000
8629 /* The mask used to clear the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field value. */
8630 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_CLR_MSK 0xffffbfff
8631 /* The reset value of the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field. */
8632 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_RESET 0x0
8633 /* Extracts the ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS field value from a register. */
8634 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_GET(value) (((value) & 0x00004000) >> 14)
8635 /* Produces a ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS register field value suitable for setting the register. */
8636 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_SET(value) (((value) << 14) & 0x00004000)
8637 
8638 /*
8639  * Field : END_BIT_ERROR_STATUS
8640  *
8641  * STATUS .
8642  *
8643  * bit 15 End-bit error (read)/write no CRC (EBE)
8644  *
8645  * Field Enumeration Values:
8646  *
8647  * Enum | Value | Description
8648  * :--------------------------------------------------|:------|:-------------------------------------------------
8649  * ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_DISABLED | 0x0 | EBE Interrupt is not raised ;STATUS is logged
8650  * : | | regardless of interrupt mask status ,and value
8651  * : | | of '0' write to bit leaves bit intact
8652  * ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_ENABLED | 0x1 | End-bit error (read)/write no CRC (EBE) STATUS
8653  * : | | of 1 indicates interrupt is raised and writes of
8654  * : | | value 1 to bit clears the status bit
8655  *
8656  * Field Access Macros:
8657  *
8658  */
8659 /*
8660  * Enumerated value for register field ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS
8661  *
8662  * EBE Interrupt is not raised ;STATUS is logged regardless of interrupt mask
8663  * status ,and value of '0' write to bit leaves bit intact
8664  */
8665 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_DISABLED 0x0
8666 /*
8667  * Enumerated value for register field ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS
8668  *
8669  * End-bit error (read)/write no CRC (EBE) STATUS of 1 indicates interrupt is
8670  * raised and writes of value 1 to bit clears the status bit
8671  */
8672 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_ENABLED 0x1
8673 
8674 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field. */
8675 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_LSB 15
8676 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field. */
8677 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_MSB 15
8678 /* The width in bits of the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field. */
8679 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_WIDTH 1
8680 /* The mask used to set the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field value. */
8681 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_SET_MSK 0x00008000
8682 /* The mask used to clear the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field value. */
8683 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_CLR_MSK 0xffff7fff
8684 /* The reset value of the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field. */
8685 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_RESET 0x0
8686 /* Extracts the ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS field value from a register. */
8687 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_GET(value) (((value) & 0x00008000) >> 15)
8688 /* Produces a ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS register field value suitable for setting the register. */
8689 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_SET(value) (((value) << 15) & 0x00008000)
8690 
8691 /*
8692  * Field : SDIO_INTERRUPT_CARD0
8693  *
8694  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8695  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8696  * 1 clears bit and 0 leaves bit intact.
8697  *
8698  * 0-No SDIO interrupt from card
8699  *
8700  * 1-SDIO interrupt from card
8701  *
8702  * In MMC-Ver3.3-only mode, bits always 0.
8703  *
8704  * Bits are logged regardless of interrupt-mask status.
8705  *
8706  * Field Enumeration Values:
8707  *
8708  * Enum | Value | Description
8709  * :--------------------------------------------------|:------|:----------------------------
8710  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED | 0x0 | No SDIO interrupt from card
8711  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED | 0x1 | SDIO interrupt from card
8712  *
8713  * Field Access Macros:
8714  *
8715  */
8716 /*
8717  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0
8718  *
8719  * No SDIO interrupt from card
8720  */
8721 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED 0x0
8722 /*
8723  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0
8724  *
8725  * SDIO interrupt from card
8726  */
8727 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED 0x1
8728 
8729 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field. */
8730 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_LSB 16
8731 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field. */
8732 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_MSB 16
8733 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field. */
8734 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_WIDTH 1
8735 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field value. */
8736 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_SET_MSK 0x00010000
8737 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field value. */
8738 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_CLR_MSK 0xfffeffff
8739 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field. */
8740 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_RESET 0x0
8741 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 field value from a register. */
8742 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_GET(value) (((value) & 0x00010000) >> 16)
8743 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 register field value suitable for setting the register. */
8744 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_SET(value) (((value) << 16) & 0x00010000)
8745 
8746 /*
8747  * Field : SDIO_INTERRUPT_CARD1
8748  *
8749  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8750  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8751  * 1 clears bit and 0 leaves bit intact.
8752  *
8753  * 0-No SDIO interrupt from card
8754  *
8755  * 1-SDIO interrupt from card
8756  *
8757  * In MMC-Ver3.3-only mode, bits always 0.
8758  *
8759  * Bits are logged regardless of interrupt-mask status.
8760  *
8761  * Field Enumeration Values:
8762  *
8763  * Enum | Value | Description
8764  * :--------------------------------------------------|:------|:----------------------------
8765  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED | 0x0 | No SDIO interrupt from card
8766  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED | 0x1 | SDIO interrupt from card
8767  *
8768  * Field Access Macros:
8769  *
8770  */
8771 /*
8772  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1
8773  *
8774  * No SDIO interrupt from card
8775  */
8776 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED 0x0
8777 /*
8778  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1
8779  *
8780  * SDIO interrupt from card
8781  */
8782 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED 0x1
8783 
8784 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field. */
8785 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_LSB 17
8786 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field. */
8787 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_MSB 17
8788 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field. */
8789 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_WIDTH 1
8790 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field value. */
8791 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_SET_MSK 0x00020000
8792 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field value. */
8793 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_CLR_MSK 0xfffdffff
8794 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field. */
8795 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_RESET 0x0
8796 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 field value from a register. */
8797 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_GET(value) (((value) & 0x00020000) >> 17)
8798 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 register field value suitable for setting the register. */
8799 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_SET(value) (((value) << 17) & 0x00020000)
8800 
8801 /*
8802  * Field : SDIO_INTERRUPT_CARD2
8803  *
8804  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8805  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8806  * 1 clears bit and 0 leaves bit intact.
8807  *
8808  * 0-No SDIO interrupt from card
8809  *
8810  * 1-SDIO interrupt from card
8811  *
8812  * In MMC-Ver3.3-only mode, bits always 0.
8813  *
8814  * Bits are logged regardless of interrupt-mask status.
8815  *
8816  * Field Enumeration Values:
8817  *
8818  * Enum | Value | Description
8819  * :--------------------------------------------------|:------|:----------------------------
8820  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED | 0x0 | No SDIO interrupt from card
8821  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED | 0x1 | SDIO interrupt from card
8822  *
8823  * Field Access Macros:
8824  *
8825  */
8826 /*
8827  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2
8828  *
8829  * No SDIO interrupt from card
8830  */
8831 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED 0x0
8832 /*
8833  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2
8834  *
8835  * SDIO interrupt from card
8836  */
8837 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED 0x1
8838 
8839 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field. */
8840 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_LSB 18
8841 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field. */
8842 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_MSB 18
8843 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field. */
8844 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_WIDTH 1
8845 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field value. */
8846 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_SET_MSK 0x00040000
8847 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field value. */
8848 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_CLR_MSK 0xfffbffff
8849 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field. */
8850 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_RESET 0x0
8851 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 field value from a register. */
8852 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_GET(value) (((value) & 0x00040000) >> 18)
8853 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 register field value suitable for setting the register. */
8854 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_SET(value) (((value) << 18) & 0x00040000)
8855 
8856 /*
8857  * Field : SDIO_INTERRUPT_CARD3
8858  *
8859  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8860  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8861  * 1 clears bit and 0 leaves bit intact.
8862  *
8863  * 0-No SDIO interrupt from card
8864  *
8865  * 1-SDIO interrupt from card
8866  *
8867  * In MMC-Ver3.3-only mode, bits always 0.
8868  *
8869  * Bits are logged regardless of interrupt-mask status.
8870  *
8871  * Field Enumeration Values:
8872  *
8873  * Enum | Value | Description
8874  * :--------------------------------------------------|:------|:----------------------------
8875  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED | 0x0 | No SDIO interrupt from card
8876  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED | 0x1 | SDIO interrupt from card
8877  *
8878  * Field Access Macros:
8879  *
8880  */
8881 /*
8882  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3
8883  *
8884  * No SDIO interrupt from card
8885  */
8886 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED 0x0
8887 /*
8888  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3
8889  *
8890  * SDIO interrupt from card
8891  */
8892 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED 0x1
8893 
8894 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field. */
8895 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_LSB 19
8896 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field. */
8897 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_MSB 19
8898 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field. */
8899 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_WIDTH 1
8900 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field value. */
8901 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_SET_MSK 0x00080000
8902 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field value. */
8903 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_CLR_MSK 0xfff7ffff
8904 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field. */
8905 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_RESET 0x0
8906 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 field value from a register. */
8907 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_GET(value) (((value) & 0x00080000) >> 19)
8908 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 register field value suitable for setting the register. */
8909 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_SET(value) (((value) << 19) & 0x00080000)
8910 
8911 /*
8912  * Field : SDIO_INTERRUPT_CARD4
8913  *
8914  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8915  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8916  * 1 clears bit and 0 leaves bit intact.
8917  *
8918  * 0-No SDIO interrupt from card
8919  *
8920  * 1-SDIO interrupt from card
8921  *
8922  * In MMC-Ver3.3-only mode, bits always 0.
8923  *
8924  * Bits are logged regardless of interrupt-mask status.
8925  *
8926  * Field Enumeration Values:
8927  *
8928  * Enum | Value | Description
8929  * :--------------------------------------------------|:------|:----------------------------
8930  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED | 0x0 | No SDIO interrupt from card
8931  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED | 0x1 | SDIO interrupt from card
8932  *
8933  * Field Access Macros:
8934  *
8935  */
8936 /*
8937  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4
8938  *
8939  * No SDIO interrupt from card
8940  */
8941 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED 0x0
8942 /*
8943  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4
8944  *
8945  * SDIO interrupt from card
8946  */
8947 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED 0x1
8948 
8949 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field. */
8950 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_LSB 20
8951 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field. */
8952 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_MSB 20
8953 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field. */
8954 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_WIDTH 1
8955 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field value. */
8956 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_SET_MSK 0x00100000
8957 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field value. */
8958 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_CLR_MSK 0xffefffff
8959 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field. */
8960 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_RESET 0x0
8961 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 field value from a register. */
8962 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_GET(value) (((value) & 0x00100000) >> 20)
8963 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 register field value suitable for setting the register. */
8964 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_SET(value) (((value) << 20) & 0x00100000)
8965 
8966 /*
8967  * Field : SDIO_INTERRUPT_CARD5
8968  *
8969  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
8970  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
8971  * 1 clears bit and 0 leaves bit intact.
8972  *
8973  * 0-No SDIO interrupt from card
8974  *
8975  * 1-SDIO interrupt from card
8976  *
8977  * In MMC-Ver3.3-only mode, bits always 0.
8978  *
8979  * Bits are logged regardless of interrupt-mask status.
8980  *
8981  * Field Enumeration Values:
8982  *
8983  * Enum | Value | Description
8984  * :--------------------------------------------------|:------|:----------------------------
8985  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED | 0x0 | No SDIO interrupt from card
8986  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED | 0x1 | SDIO interrupt from card
8987  *
8988  * Field Access Macros:
8989  *
8990  */
8991 /*
8992  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5
8993  *
8994  * No SDIO interrupt from card
8995  */
8996 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED 0x0
8997 /*
8998  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5
8999  *
9000  * SDIO interrupt from card
9001  */
9002 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED 0x1
9003 
9004 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field. */
9005 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_LSB 21
9006 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field. */
9007 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_MSB 21
9008 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field. */
9009 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_WIDTH 1
9010 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field value. */
9011 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_SET_MSK 0x00200000
9012 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field value. */
9013 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_CLR_MSK 0xffdfffff
9014 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field. */
9015 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_RESET 0x0
9016 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 field value from a register. */
9017 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_GET(value) (((value) & 0x00200000) >> 21)
9018 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 register field value suitable for setting the register. */
9019 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_SET(value) (((value) << 21) & 0x00200000)
9020 
9021 /*
9022  * Field : SDIO_INTERRUPT_CARD6
9023  *
9024  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9025  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9026  * 1 clears bit and 0 leaves bit intact.
9027  *
9028  * 0-No SDIO interrupt from card
9029  *
9030  * 1-SDIO interrupt from card
9031  *
9032  * In MMC-Ver3.3-only mode, bits always 0.
9033  *
9034  * Bits are logged regardless of interrupt-mask status.
9035  *
9036  * Field Enumeration Values:
9037  *
9038  * Enum | Value | Description
9039  * :--------------------------------------------------|:------|:----------------------------
9040  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED | 0x0 | No SDIO interrupt from card
9041  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED | 0x1 | SDIO interrupt from card
9042  *
9043  * Field Access Macros:
9044  *
9045  */
9046 /*
9047  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6
9048  *
9049  * No SDIO interrupt from card
9050  */
9051 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED 0x0
9052 /*
9053  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6
9054  *
9055  * SDIO interrupt from card
9056  */
9057 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED 0x1
9058 
9059 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field. */
9060 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_LSB 22
9061 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field. */
9062 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_MSB 22
9063 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field. */
9064 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_WIDTH 1
9065 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field value. */
9066 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_SET_MSK 0x00400000
9067 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field value. */
9068 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_CLR_MSK 0xffbfffff
9069 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field. */
9070 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_RESET 0x0
9071 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 field value from a register. */
9072 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_GET(value) (((value) & 0x00400000) >> 22)
9073 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 register field value suitable for setting the register. */
9074 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_SET(value) (((value) << 22) & 0x00400000)
9075 
9076 /*
9077  * Field : SDIO_INTERRUPT_CARD7
9078  *
9079  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9080  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9081  * 1 clears bit and 0 leaves bit intact.
9082  *
9083  * 0-No SDIO interrupt from card
9084  *
9085  * 1-SDIO interrupt from card
9086  *
9087  * In MMC-Ver3.3-only mode, bits always 0.
9088  *
9089  * Bits are logged regardless of interrupt-mask status.
9090  *
9091  * Field Enumeration Values:
9092  *
9093  * Enum | Value | Description
9094  * :--------------------------------------------------|:------|:----------------------------
9095  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED | 0x0 | No SDIO interrupt from card
9096  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED | 0x1 | SDIO interrupt from card
9097  *
9098  * Field Access Macros:
9099  *
9100  */
9101 /*
9102  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7
9103  *
9104  * No SDIO interrupt from card
9105  */
9106 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED 0x0
9107 /*
9108  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7
9109  *
9110  * SDIO interrupt from card
9111  */
9112 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED 0x1
9113 
9114 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field. */
9115 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_LSB 23
9116 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field. */
9117 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_MSB 23
9118 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field. */
9119 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_WIDTH 1
9120 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field value. */
9121 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_SET_MSK 0x00800000
9122 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field value. */
9123 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_CLR_MSK 0xff7fffff
9124 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field. */
9125 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_RESET 0x0
9126 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 field value from a register. */
9127 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_GET(value) (((value) & 0x00800000) >> 23)
9128 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 register field value suitable for setting the register. */
9129 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_SET(value) (((value) << 23) & 0x00800000)
9130 
9131 /*
9132  * Field : SDIO_INTERRUPT_CARD8
9133  *
9134  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9135  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9136  * 1 clears bit and 0 leaves bit intact.
9137  *
9138  * 0-No SDIO interrupt from card
9139  *
9140  * 1-SDIO interrupt from card
9141  *
9142  * In MMC-Ver3.3-only mode, bits always 0.
9143  *
9144  * Bits are logged regardless of interrupt-mask status.
9145  *
9146  * Field Enumeration Values:
9147  *
9148  * Enum | Value | Description
9149  * :--------------------------------------------------|:------|:----------------------------
9150  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED | 0x0 | No SDIO interrupt from card
9151  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED | 0x1 | SDIO interrupt from card
9152  *
9153  * Field Access Macros:
9154  *
9155  */
9156 /*
9157  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8
9158  *
9159  * No SDIO interrupt from card
9160  */
9161 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED 0x0
9162 /*
9163  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8
9164  *
9165  * SDIO interrupt from card
9166  */
9167 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED 0x1
9168 
9169 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field. */
9170 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_LSB 24
9171 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field. */
9172 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_MSB 24
9173 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field. */
9174 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_WIDTH 1
9175 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field value. */
9176 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_SET_MSK 0x01000000
9177 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field value. */
9178 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_CLR_MSK 0xfeffffff
9179 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field. */
9180 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_RESET 0x0
9181 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 field value from a register. */
9182 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_GET(value) (((value) & 0x01000000) >> 24)
9183 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 register field value suitable for setting the register. */
9184 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_SET(value) (((value) << 24) & 0x01000000)
9185 
9186 /*
9187  * Field : SDIO_INTERRUPT_CARD9
9188  *
9189  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9190  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9191  * 1 clears bit and 0 leaves bit intact.
9192  *
9193  * 0-No SDIO interrupt from card
9194  *
9195  * 1-SDIO interrupt from card
9196  *
9197  * In MMC-Ver3.3-only mode, bits always 0.
9198  *
9199  * Bits are logged regardless of interrupt-mask status.
9200  *
9201  * Field Enumeration Values:
9202  *
9203  * Enum | Value | Description
9204  * :--------------------------------------------------|:------|:----------------------------
9205  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED | 0x0 | No SDIO interrupt from card
9206  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED | 0x1 | SDIO interrupt from card
9207  *
9208  * Field Access Macros:
9209  *
9210  */
9211 /*
9212  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9
9213  *
9214  * No SDIO interrupt from card
9215  */
9216 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED 0x0
9217 /*
9218  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9
9219  *
9220  * SDIO interrupt from card
9221  */
9222 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED 0x1
9223 
9224 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field. */
9225 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_LSB 25
9226 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field. */
9227 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_MSB 25
9228 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field. */
9229 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_WIDTH 1
9230 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field value. */
9231 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_SET_MSK 0x02000000
9232 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field value. */
9233 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_CLR_MSK 0xfdffffff
9234 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field. */
9235 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_RESET 0x0
9236 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 field value from a register. */
9237 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_GET(value) (((value) & 0x02000000) >> 25)
9238 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 register field value suitable for setting the register. */
9239 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_SET(value) (((value) << 25) & 0x02000000)
9240 
9241 /*
9242  * Field : SDIO_INTERRUPT_CARD10
9243  *
9244  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9245  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9246  * 1 clears bit and 0 leaves bit intact.
9247  *
9248  * 0-No SDIO interrupt from card
9249  *
9250  * 1-SDIO interrupt from card
9251  *
9252  * In MMC-Ver3.3-only mode, bits always 0.
9253  *
9254  * Bits are logged regardless of interrupt-mask status.
9255  *
9256  * Field Enumeration Values:
9257  *
9258  * Enum | Value | Description
9259  * :---------------------------------------------------|:------|:----------------------------
9260  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED | 0x0 | No SDIO interrupt from card
9261  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED | 0x1 | SDIO interrupt from card
9262  *
9263  * Field Access Macros:
9264  *
9265  */
9266 /*
9267  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10
9268  *
9269  * No SDIO interrupt from card
9270  */
9271 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED 0x0
9272 /*
9273  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10
9274  *
9275  * SDIO interrupt from card
9276  */
9277 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED 0x1
9278 
9279 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field. */
9280 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_LSB 26
9281 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field. */
9282 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_MSB 26
9283 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field. */
9284 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_WIDTH 1
9285 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field value. */
9286 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_SET_MSK 0x04000000
9287 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field value. */
9288 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_CLR_MSK 0xfbffffff
9289 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field. */
9290 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_RESET 0x0
9291 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 field value from a register. */
9292 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_GET(value) (((value) & 0x04000000) >> 26)
9293 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 register field value suitable for setting the register. */
9294 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_SET(value) (((value) << 26) & 0x04000000)
9295 
9296 /*
9297  * Field : SDIO_INTERRUPT_CARD11
9298  *
9299  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9300  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9301  * 1 clears bit and 0 leaves bit intact.
9302  *
9303  * 0-No SDIO interrupt from card
9304  *
9305  * 1-SDIO interrupt from card
9306  *
9307  * In MMC-Ver3.3-only mode, bits always 0.
9308  *
9309  * Bits are logged regardless of interrupt-mask status.
9310  *
9311  * Field Enumeration Values:
9312  *
9313  * Enum | Value | Description
9314  * :---------------------------------------------------|:------|:----------------------------
9315  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED | 0x0 | No SDIO interrupt from card
9316  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED | 0x1 | SDIO interrupt from card
9317  *
9318  * Field Access Macros:
9319  *
9320  */
9321 /*
9322  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11
9323  *
9324  * No SDIO interrupt from card
9325  */
9326 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED 0x0
9327 /*
9328  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11
9329  *
9330  * SDIO interrupt from card
9331  */
9332 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED 0x1
9333 
9334 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field. */
9335 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_LSB 27
9336 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field. */
9337 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_MSB 27
9338 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field. */
9339 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_WIDTH 1
9340 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field value. */
9341 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_SET_MSK 0x08000000
9342 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field value. */
9343 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_CLR_MSK 0xf7ffffff
9344 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field. */
9345 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_RESET 0x0
9346 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 field value from a register. */
9347 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_GET(value) (((value) & 0x08000000) >> 27)
9348 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 register field value suitable for setting the register. */
9349 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_SET(value) (((value) << 27) & 0x08000000)
9350 
9351 /*
9352  * Field : SDIO_INTERRUPT_CARD12
9353  *
9354  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9355  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9356  * 1 clears bit and 0 leaves bit intact.
9357  *
9358  * 0-No SDIO interrupt from card
9359  *
9360  * 1-SDIO interrupt from card
9361  *
9362  * In MMC-Ver3.3-only mode, bits always 0.
9363  *
9364  * Bits are logged regardless of interrupt-mask status.
9365  *
9366  * Field Enumeration Values:
9367  *
9368  * Enum | Value | Description
9369  * :---------------------------------------------------|:------|:----------------------------
9370  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED | 0x0 | No SDIO interrupt from card
9371  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED | 0x1 | SDIO interrupt from card
9372  *
9373  * Field Access Macros:
9374  *
9375  */
9376 /*
9377  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12
9378  *
9379  * No SDIO interrupt from card
9380  */
9381 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED 0x0
9382 /*
9383  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12
9384  *
9385  * SDIO interrupt from card
9386  */
9387 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED 0x1
9388 
9389 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field. */
9390 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_LSB 28
9391 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field. */
9392 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_MSB 28
9393 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field. */
9394 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_WIDTH 1
9395 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field value. */
9396 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_SET_MSK 0x10000000
9397 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field value. */
9398 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_CLR_MSK 0xefffffff
9399 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field. */
9400 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_RESET 0x0
9401 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 field value from a register. */
9402 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_GET(value) (((value) & 0x10000000) >> 28)
9403 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 register field value suitable for setting the register. */
9404 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_SET(value) (((value) << 28) & 0x10000000)
9405 
9406 /*
9407  * Field : SDIO_INTERRUPT_CARD13
9408  *
9409  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9410  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9411  * 1 clears bit and 0 leaves bit intact.
9412  *
9413  * 0-No SDIO interrupt from card
9414  *
9415  * 1-SDIO interrupt from card
9416  *
9417  * In MMC-Ver3.3-only mode, bits always 0.
9418  *
9419  * Bits are logged regardless of interrupt-mask status.
9420  *
9421  * Field Enumeration Values:
9422  *
9423  * Enum | Value | Description
9424  * :---------------------------------------------------|:------|:----------------------------
9425  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED | 0x0 | No SDIO interrupt from card
9426  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED | 0x1 | SDIO interrupt from card
9427  *
9428  * Field Access Macros:
9429  *
9430  */
9431 /*
9432  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13
9433  *
9434  * No SDIO interrupt from card
9435  */
9436 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED 0x0
9437 /*
9438  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13
9439  *
9440  * SDIO interrupt from card
9441  */
9442 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED 0x1
9443 
9444 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field. */
9445 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_LSB 29
9446 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field. */
9447 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_MSB 29
9448 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field. */
9449 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_WIDTH 1
9450 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field value. */
9451 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_SET_MSK 0x20000000
9452 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field value. */
9453 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_CLR_MSK 0xdfffffff
9454 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field. */
9455 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_RESET 0x0
9456 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 field value from a register. */
9457 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_GET(value) (((value) & 0x20000000) >> 29)
9458 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 register field value suitable for setting the register. */
9459 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_SET(value) (((value) << 29) & 0x20000000)
9460 
9461 /*
9462  * Field : SDIO_INTERRUPT_CARD14
9463  *
9464  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9465  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9466  * 1 clears bit and 0 leaves bit intact.
9467  *
9468  * 0-No SDIO interrupt from card
9469  *
9470  * 1-SDIO interrupt from card
9471  *
9472  * In MMC-Ver3.3-only mode, bits always 0.
9473  *
9474  * Bits are logged regardless of interrupt-mask status.
9475  *
9476  * Field Enumeration Values:
9477  *
9478  * Enum | Value | Description
9479  * :---------------------------------------------------|:------|:----------------------------
9480  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED | 0x0 | No SDIO interrupt from card
9481  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED | 0x1 | SDIO interrupt from card
9482  *
9483  * Field Access Macros:
9484  *
9485  */
9486 /*
9487  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14
9488  *
9489  * No SDIO interrupt from card
9490  */
9491 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED 0x0
9492 /*
9493  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14
9494  *
9495  * SDIO interrupt from card
9496  */
9497 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED 0x1
9498 
9499 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field. */
9500 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_LSB 30
9501 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field. */
9502 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_MSB 30
9503 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field. */
9504 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_WIDTH 1
9505 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field value. */
9506 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_SET_MSK 0x40000000
9507 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field value. */
9508 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_CLR_MSK 0xbfffffff
9509 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field. */
9510 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_RESET 0x0
9511 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 field value from a register. */
9512 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_GET(value) (((value) & 0x40000000) >> 30)
9513 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 register field value suitable for setting the register. */
9514 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_SET(value) (((value) << 30) & 0x40000000)
9515 
9516 /*
9517  * Field : SDIO_INTERRUPT_CARD15
9518  *
9519  * Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to
9520  * Card[15], and bit[16] is for Card[0]. Writes to these bits clear them. Value of
9521  * 1 clears bit and 0 leaves bit intact.
9522  *
9523  * 0-No SDIO interrupt from card
9524  *
9525  * 1-SDIO interrupt from card
9526  *
9527  * In MMC-Ver3.3-only mode, bits always 0.
9528  *
9529  * Bits are logged regardless of interrupt-mask status.
9530  *
9531  * Field Enumeration Values:
9532  *
9533  * Enum | Value | Description
9534  * :---------------------------------------------------|:------|:----------------------------
9535  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED | 0x0 | No SDIO interrupt from card
9536  * ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED | 0x1 | SDIO interrupt from card
9537  *
9538  * Field Access Macros:
9539  *
9540  */
9541 /*
9542  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15
9543  *
9544  * No SDIO interrupt from card
9545  */
9546 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED 0x0
9547 /*
9548  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15
9549  *
9550  * SDIO interrupt from card
9551  */
9552 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED 0x1
9553 
9554 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field. */
9555 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_LSB 31
9556 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field. */
9557 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_MSB 31
9558 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field. */
9559 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_WIDTH 1
9560 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field value. */
9561 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_SET_MSK 0x80000000
9562 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field value. */
9563 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_CLR_MSK 0x7fffffff
9564 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field. */
9565 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_RESET 0x0
9566 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 field value from a register. */
9567 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_GET(value) (((value) & 0x80000000) >> 31)
9568 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 register field value suitable for setting the register. */
9569 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_SET(value) (((value) << 31) & 0x80000000)
9570 
9571 #ifndef __ASSEMBLY__
9572 /*
9573  * WARNING: The C register and register group struct declarations are provided for
9574  * convenience and illustrative purposes. They should, however, be used with
9575  * caution as the C language standard provides no guarantees about the alignment or
9576  * atomicity of device memory accesses. The recommended practice for coding device
9577  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9578  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9579  * alt_write_dword() functions for 64 bit registers.
9580  *
9581  * The struct declaration for register ALT_SDMMC_RINTSTS.
9582  */
9583 struct ALT_SDMMC_RINTSTS_s
9584 {
9585  volatile uint32_t CARD_DETECT_STATUS : 1; /* ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS */
9586  volatile uint32_t RESPONSE_ERROR_STATUS : 1; /* ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS */
9587  volatile uint32_t COMMAND_DONE_STATUS : 1; /* ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS */
9588  volatile uint32_t DATA_TRANSFER_OVER_STATUS : 1; /* ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS */
9589  volatile uint32_t TRANSMIT_RECEIVE_FIFO_DATA_STATUS : 1; /* ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS */
9590  volatile uint32_t RECEIVE_FIFO_DATA_REQUEST_STATUS : 1; /* ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS */
9591  volatile uint32_t RESPONSE_CRC_ERROR_STATUS : 1; /* ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS */
9592  volatile uint32_t DATA_CRC_ERROR_STATUS : 1; /* ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS */
9593  volatile uint32_t RESPONSE_TIMEOUT_STATUS : 1; /* ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS */
9594  volatile uint32_t DATA_READ_TIMEOUT_STATUS : 1; /* ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS */
9595  volatile uint32_t HOST_TIMEOUT_STATUS : 1; /* ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS */
9596  volatile uint32_t FIFO_UNDER_OVER_RUN_STATUS : 1; /* ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS */
9597  volatile uint32_t HARDWARE_LOCKED_WRITE_STATUS : 1; /* ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS */
9598  volatile uint32_t BUSY_COMPLETE_STATUS : 1; /* ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS */
9599  volatile uint32_t AUTO_COMMAND_DONE_STATUS : 1; /* ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS */
9600  volatile uint32_t END_BIT_ERROR_STATUS : 1; /* ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS */
9601  volatile uint32_t SDIO_INTERRUPT_CARD0 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0 */
9602  volatile uint32_t SDIO_INTERRUPT_CARD1 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1 */
9603  volatile uint32_t SDIO_INTERRUPT_CARD2 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2 */
9604  volatile uint32_t SDIO_INTERRUPT_CARD3 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3 */
9605  volatile uint32_t SDIO_INTERRUPT_CARD4 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4 */
9606  volatile uint32_t SDIO_INTERRUPT_CARD5 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5 */
9607  volatile uint32_t SDIO_INTERRUPT_CARD6 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6 */
9608  volatile uint32_t SDIO_INTERRUPT_CARD7 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7 */
9609  volatile uint32_t SDIO_INTERRUPT_CARD8 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8 */
9610  volatile uint32_t SDIO_INTERRUPT_CARD9 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9 */
9611  volatile uint32_t SDIO_INTERRUPT_CARD10 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10 */
9612  volatile uint32_t SDIO_INTERRUPT_CARD11 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11 */
9613  volatile uint32_t SDIO_INTERRUPT_CARD12 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12 */
9614  volatile uint32_t SDIO_INTERRUPT_CARD13 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13 */
9615  volatile uint32_t SDIO_INTERRUPT_CARD14 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14 */
9616  volatile uint32_t SDIO_INTERRUPT_CARD15 : 1; /* ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15 */
9617 };
9618 
9619 /* The typedef declaration for register ALT_SDMMC_RINTSTS. */
9620 typedef struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
9621 #endif /* __ASSEMBLY__ */
9622 
9623 /* The reset value of the ALT_SDMMC_RINTSTS register. */
9624 #define ALT_SDMMC_RINTSTS_RESET 0x00000000
9625 /* The byte offset of the ALT_SDMMC_RINTSTS register from the beginning of the component. */
9626 #define ALT_SDMMC_RINTSTS_OFST 0x44
9627 /* The address of the ALT_SDMMC_RINTSTS register. */
9628 #define ALT_SDMMC_RINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RINTSTS_OFST))
9629 
9630 /*
9631  * Register : Status Register - STATUS
9632  *
9633  * Name: Status Register
9634  *
9635  * Size: 32 bits
9636  *
9637  * Address Offset: 0x48
9638  *
9639  * Read/write access: read
9640  *
9641  * Register Layout
9642  *
9643  * Bits | Access | Reset | Description
9644  * :--------|:-------|:------|:------------------------------------
9645  * [0] | R | 0x0 | ALT_SDMMC_STATUS_FIFO_RX_WATERMARK
9646  * [1] | R | 0x1 | ALT_SDMMC_STATUS_FIFO_TX_WATERMARK
9647  * [2] | R | 0x1 | ALT_SDMMC_STATUS_FIFO_EMPTY
9648  * [3] | R | 0x0 | ALT_SDMMC_STATUS_FIFO_FULL
9649  * [7:4] | R | 0x0 | ALT_SDMMC_STATUS_COMMAND_FSM_STATES
9650  * [8] | R | 0x1 | ALT_SDMMC_STATUS_DATA_3_STATUS
9651  * [9] | R | 0x0 | ALT_SDMMC_STATUS_DATA_BUSY
9652  * [10] | R | 0x0 | ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY
9653  * [16:11] | R | 0x0 | ALT_SDMMC_STATUS_RESPONSE_INDEX
9654  * [29:17] | R | 0x0 | ALT_SDMMC_STATUS_FIFO_COUNT
9655  * [30] | R | 0x0 | ALT_SDMMC_STATUS_DMA_ACK
9656  * [31] | R | 0x0 | ALT_SDMMC_STATUS_DMA_REQ
9657  *
9658  */
9659 /*
9660  * Field : FIFO_RX_WATERMARK
9661  *
9662  * FIFO reached Receive watermark level; not qualified with data
9663  *
9664  * transfer.
9665  *
9666  * Field Enumeration Values:
9667  *
9668  * Enum | Value | Description
9669  * :-------------------------------------------|:------|:--------------------------
9670  * ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_CLEAR | 0x0 | Not reached RXWMARK level
9671  * ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_SET | 0x1 | Reached RXWMARK level
9672  *
9673  * Field Access Macros:
9674  *
9675  */
9676 /*
9677  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_RX_WATERMARK
9678  *
9679  * Not reached RXWMARK level
9680  */
9681 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_CLEAR 0x0
9682 /*
9683  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_RX_WATERMARK
9684  *
9685  * Reached RXWMARK level
9686  */
9687 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_SET 0x1
9688 
9689 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field. */
9690 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_LSB 0
9691 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field. */
9692 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_MSB 0
9693 /* The width in bits of the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field. */
9694 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_WIDTH 1
9695 /* The mask used to set the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field value. */
9696 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_SET_MSK 0x00000001
9697 /* The mask used to clear the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field value. */
9698 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
9699 /* The reset value of the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field. */
9700 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_RESET 0x0
9701 /* Extracts the ALT_SDMMC_STATUS_FIFO_RX_WATERMARK field value from a register. */
9702 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
9703 /* Produces a ALT_SDMMC_STATUS_FIFO_RX_WATERMARK register field value suitable for setting the register. */
9704 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
9705 
9706 /*
9707  * Field : FIFO_TX_WATERMARK
9708  *
9709  * FIFO reached Transmit watermark level; not qualified with data
9710  *
9711  * transfer.
9712  *
9713  * Field Enumeration Values:
9714  *
9715  * Enum | Value | Description
9716  * :-------------------------------------------|:------|:--------------------------
9717  * ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_CLEAR | 0x0 | Not reached TXWMARK level
9718  * ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_SET | 0x1 | Reached TXWMARK level
9719  *
9720  * Field Access Macros:
9721  *
9722  */
9723 /*
9724  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_TX_WATERMARK
9725  *
9726  * Not reached TXWMARK level
9727  */
9728 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_CLEAR 0x0
9729 /*
9730  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_TX_WATERMARK
9731  *
9732  * Reached TXWMARK level
9733  */
9734 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_SET 0x1
9735 
9736 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field. */
9737 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_LSB 1
9738 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field. */
9739 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_MSB 1
9740 /* The width in bits of the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field. */
9741 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_WIDTH 1
9742 /* The mask used to set the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field value. */
9743 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_SET_MSK 0x00000002
9744 /* The mask used to clear the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field value. */
9745 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
9746 /* The reset value of the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field. */
9747 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_RESET 0x1
9748 /* Extracts the ALT_SDMMC_STATUS_FIFO_TX_WATERMARK field value from a register. */
9749 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
9750 /* Produces a ALT_SDMMC_STATUS_FIFO_TX_WATERMARK register field value suitable for setting the register. */
9751 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
9752 
9753 /*
9754  * Field : FIFO_EMPTY
9755  *
9756  * FIFO is empty status
9757  *
9758  * Field Enumeration Values:
9759  *
9760  * Enum | Value | Description
9761  * :------------------------------------|:------|:------------------
9762  * ALT_SDMMC_STATUS_FIFO_EMPTY_E_CLEAR | 0x0 | FIFO is not empty
9763  * ALT_SDMMC_STATUS_FIFO_EMPTY_E_SET | 0x1 | FIFO is empty
9764  *
9765  * Field Access Macros:
9766  *
9767  */
9768 /*
9769  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_EMPTY
9770  *
9771  * FIFO is not empty
9772  */
9773 #define ALT_SDMMC_STATUS_FIFO_EMPTY_E_CLEAR 0x0
9774 /*
9775  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_EMPTY
9776  *
9777  * FIFO is empty
9778  */
9779 #define ALT_SDMMC_STATUS_FIFO_EMPTY_E_SET 0x1
9780 
9781 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_FIFO_EMPTY register field. */
9782 #define ALT_SDMMC_STATUS_FIFO_EMPTY_LSB 2
9783 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_FIFO_EMPTY register field. */
9784 #define ALT_SDMMC_STATUS_FIFO_EMPTY_MSB 2
9785 /* The width in bits of the ALT_SDMMC_STATUS_FIFO_EMPTY register field. */
9786 #define ALT_SDMMC_STATUS_FIFO_EMPTY_WIDTH 1
9787 /* The mask used to set the ALT_SDMMC_STATUS_FIFO_EMPTY register field value. */
9788 #define ALT_SDMMC_STATUS_FIFO_EMPTY_SET_MSK 0x00000004
9789 /* The mask used to clear the ALT_SDMMC_STATUS_FIFO_EMPTY register field value. */
9790 #define ALT_SDMMC_STATUS_FIFO_EMPTY_CLR_MSK 0xfffffffb
9791 /* The reset value of the ALT_SDMMC_STATUS_FIFO_EMPTY register field. */
9792 #define ALT_SDMMC_STATUS_FIFO_EMPTY_RESET 0x1
9793 /* Extracts the ALT_SDMMC_STATUS_FIFO_EMPTY field value from a register. */
9794 #define ALT_SDMMC_STATUS_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
9795 /* Produces a ALT_SDMMC_STATUS_FIFO_EMPTY register field value suitable for setting the register. */
9796 #define ALT_SDMMC_STATUS_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
9797 
9798 /*
9799  * Field : FIFO_FULL
9800  *
9801  * FIFO is full status
9802  *
9803  * Field Enumeration Values:
9804  *
9805  * Enum | Value | Description
9806  * :-----------------------------------|:------|:-----------------
9807  * ALT_SDMMC_STATUS_FIFO_FULL_E_CLEAR | 0x0 | FIFO is not full
9808  * ALT_SDMMC_STATUS_FIFO_FULL_E_SET | 0x1 | FIFO is full
9809  *
9810  * Field Access Macros:
9811  *
9812  */
9813 /*
9814  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_FULL
9815  *
9816  * FIFO is not full
9817  */
9818 #define ALT_SDMMC_STATUS_FIFO_FULL_E_CLEAR 0x0
9819 /*
9820  * Enumerated value for register field ALT_SDMMC_STATUS_FIFO_FULL
9821  *
9822  * FIFO is full
9823  */
9824 #define ALT_SDMMC_STATUS_FIFO_FULL_E_SET 0x1
9825 
9826 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_FIFO_FULL register field. */
9827 #define ALT_SDMMC_STATUS_FIFO_FULL_LSB 3
9828 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_FIFO_FULL register field. */
9829 #define ALT_SDMMC_STATUS_FIFO_FULL_MSB 3
9830 /* The width in bits of the ALT_SDMMC_STATUS_FIFO_FULL register field. */
9831 #define ALT_SDMMC_STATUS_FIFO_FULL_WIDTH 1
9832 /* The mask used to set the ALT_SDMMC_STATUS_FIFO_FULL register field value. */
9833 #define ALT_SDMMC_STATUS_FIFO_FULL_SET_MSK 0x00000008
9834 /* The mask used to clear the ALT_SDMMC_STATUS_FIFO_FULL register field value. */
9835 #define ALT_SDMMC_STATUS_FIFO_FULL_CLR_MSK 0xfffffff7
9836 /* The reset value of the ALT_SDMMC_STATUS_FIFO_FULL register field. */
9837 #define ALT_SDMMC_STATUS_FIFO_FULL_RESET 0x0
9838 /* Extracts the ALT_SDMMC_STATUS_FIFO_FULL field value from a register. */
9839 #define ALT_SDMMC_STATUS_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
9840 /* Produces a ALT_SDMMC_STATUS_FIFO_FULL register field value suitable for setting the register. */
9841 #define ALT_SDMMC_STATUS_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
9842 
9843 /*
9844  * Field : COMMAND_FSM_STATES
9845  *
9846  * Command FSM states:
9847  *
9848  * 0 Idle
9849  *
9850  * 1 Send init sequence
9851  *
9852  * 2 Tx cmd start bit
9853  *
9854  * 3 Tx cmd tx bit
9855  *
9856  * 4 Tx cmd index + arg
9857  *
9858  * 5 Tx cmd crc7
9859  *
9860  * 6 Tx cmd end bit
9861  *
9862  * 7 Rx resp start bit
9863  *
9864  * 8 Rx resp IRQ response
9865  *
9866  * 9 Rx resp tx bit
9867  *
9868  * 10 Rx resp cmd idx
9869  *
9870  * 11 Rx resp data
9871  *
9872  * 12 Rx resp crc7
9873  *
9874  * 13 Rx resp end bit
9875  *
9876  * 14 Cmd path wait NCC
9877  *
9878  * 15 Wait; CMD-to-response turnaround
9879  *
9880  * NOTE: The command FSM state is represented using 19 bits. The STATUS
9881  * Register(7:4) has 4 bits to represent the command FSM states. Using these 4
9882  * bits, only 16 states can be represented. Thus three states cannot be represented
9883  * in the STATUS(7:4) register. The three states that are not represented in the
9884  * STATUS Register(7:4) are:
9885  *
9886  * * Bit 16 Wait for CCS
9887  *
9888  * * Bit 17 Send CCSD
9889  *
9890  * * Bit 18 Boot Mode
9891  *
9892  * Due to this, while command FSM is in "Wait for CCS state" or "Send CCSD"
9893  * or "Boot Mode", the Status register indicates status as 0 for the bit field
9894  * 7:4.
9895  *
9896  * Field Access Macros:
9897  *
9898  */
9899 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field. */
9900 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_LSB 4
9901 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field. */
9902 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_MSB 7
9903 /* The width in bits of the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field. */
9904 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_WIDTH 4
9905 /* The mask used to set the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field value. */
9906 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_SET_MSK 0x000000f0
9907 /* The mask used to clear the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field value. */
9908 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_CLR_MSK 0xffffff0f
9909 /* The reset value of the ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field. */
9910 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_RESET 0x0
9911 /* Extracts the ALT_SDMMC_STATUS_COMMAND_FSM_STATES field value from a register. */
9912 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
9913 /* Produces a ALT_SDMMC_STATUS_COMMAND_FSM_STATES register field value suitable for setting the register. */
9914 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
9915 
9916 /*
9917  * Field : DATA_3_STATUS
9918  *
9919  * Raw selected card_data[3]; checks whether card is present
9920  *
9921  * 0-card not present
9922  *
9923  * 1-card present
9924  *
9925  * Field Enumeration Values:
9926  *
9927  * Enum | Value | Description
9928  * :--------------------------------------|:------|:------------------
9929  * ALT_SDMMC_STATUS_DATA_3_STATUS_E_LOW | 0x0 | Card not present
9930  * ALT_SDMMC_STATUS_DATA_3_STATUS_E_HIGH | 0x1 | card present
9931  *
9932  * Field Access Macros:
9933  *
9934  */
9935 /*
9936  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_3_STATUS
9937  *
9938  * Card not present
9939  */
9940 #define ALT_SDMMC_STATUS_DATA_3_STATUS_E_LOW 0x0
9941 /*
9942  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_3_STATUS
9943  *
9944  * card present
9945  */
9946 #define ALT_SDMMC_STATUS_DATA_3_STATUS_E_HIGH 0x1
9947 
9948 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_DATA_3_STATUS register field. */
9949 #define ALT_SDMMC_STATUS_DATA_3_STATUS_LSB 8
9950 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_DATA_3_STATUS register field. */
9951 #define ALT_SDMMC_STATUS_DATA_3_STATUS_MSB 8
9952 /* The width in bits of the ALT_SDMMC_STATUS_DATA_3_STATUS register field. */
9953 #define ALT_SDMMC_STATUS_DATA_3_STATUS_WIDTH 1
9954 /* The mask used to set the ALT_SDMMC_STATUS_DATA_3_STATUS register field value. */
9955 #define ALT_SDMMC_STATUS_DATA_3_STATUS_SET_MSK 0x00000100
9956 /* The mask used to clear the ALT_SDMMC_STATUS_DATA_3_STATUS register field value. */
9957 #define ALT_SDMMC_STATUS_DATA_3_STATUS_CLR_MSK 0xfffffeff
9958 /* The reset value of the ALT_SDMMC_STATUS_DATA_3_STATUS register field. */
9959 #define ALT_SDMMC_STATUS_DATA_3_STATUS_RESET 0x1
9960 /* Extracts the ALT_SDMMC_STATUS_DATA_3_STATUS field value from a register. */
9961 #define ALT_SDMMC_STATUS_DATA_3_STATUS_GET(value) (((value) & 0x00000100) >> 8)
9962 /* Produces a ALT_SDMMC_STATUS_DATA_3_STATUS register field value suitable for setting the register. */
9963 #define ALT_SDMMC_STATUS_DATA_3_STATUS_SET(value) (((value) << 8) & 0x00000100)
9964 
9965 /*
9966  * Field : DATA_BUSY
9967  *
9968  * Inverted version of raw selected card_data[0]
9969  *
9970  * 0-card data not busy
9971  *
9972  * 1-card data busy
9973  *
9974  * Field Enumeration Values:
9975  *
9976  * Enum | Value | Description
9977  * :----------------------------------|:------|:--------------------
9978  * ALT_SDMMC_STATUS_DATA_BUSY_E_LOW | 0x0 | Card data not busy
9979  * ALT_SDMMC_STATUS_DATA_BUSY_E_HIGH | 0x1 | card data busy
9980  *
9981  * Field Access Macros:
9982  *
9983  */
9984 /*
9985  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_BUSY
9986  *
9987  * Card data not busy
9988  */
9989 #define ALT_SDMMC_STATUS_DATA_BUSY_E_LOW 0x0
9990 /*
9991  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_BUSY
9992  *
9993  * card data busy
9994  */
9995 #define ALT_SDMMC_STATUS_DATA_BUSY_E_HIGH 0x1
9996 
9997 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_DATA_BUSY register field. */
9998 #define ALT_SDMMC_STATUS_DATA_BUSY_LSB 9
9999 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_DATA_BUSY register field. */
10000 #define ALT_SDMMC_STATUS_DATA_BUSY_MSB 9
10001 /* The width in bits of the ALT_SDMMC_STATUS_DATA_BUSY register field. */
10002 #define ALT_SDMMC_STATUS_DATA_BUSY_WIDTH 1
10003 /* The mask used to set the ALT_SDMMC_STATUS_DATA_BUSY register field value. */
10004 #define ALT_SDMMC_STATUS_DATA_BUSY_SET_MSK 0x00000200
10005 /* The mask used to clear the ALT_SDMMC_STATUS_DATA_BUSY register field value. */
10006 #define ALT_SDMMC_STATUS_DATA_BUSY_CLR_MSK 0xfffffdff
10007 /* The reset value of the ALT_SDMMC_STATUS_DATA_BUSY register field. */
10008 #define ALT_SDMMC_STATUS_DATA_BUSY_RESET 0x0
10009 /* Extracts the ALT_SDMMC_STATUS_DATA_BUSY field value from a register. */
10010 #define ALT_SDMMC_STATUS_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
10011 /* Produces a ALT_SDMMC_STATUS_DATA_BUSY register field value suitable for setting the register. */
10012 #define ALT_SDMMC_STATUS_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
10013 
10014 /*
10015  * Field : DATA_STATE_MC_BUSY
10016  *
10017  * Data transmit or receive state-machine is busy
10018  *
10019  * Field Enumeration Values:
10020  *
10021  * Enum | Value | Description
10022  * :-------------------------------------------|:------|:---------------------------
10023  * ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_LOW | 0x0 | DMA state-machine not busy
10024  * ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_HIGH | 0x1 | DMA state-machine busy
10025  *
10026  * Field Access Macros:
10027  *
10028  */
10029 /*
10030  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY
10031  *
10032  * DMA state-machine not busy
10033  */
10034 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_LOW 0x0
10035 /*
10036  * Enumerated value for register field ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY
10037  *
10038  * DMA state-machine busy
10039  */
10040 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_HIGH 0x1
10041 
10042 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field. */
10043 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_LSB 10
10044 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field. */
10045 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_MSB 10
10046 /* The width in bits of the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field. */
10047 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_WIDTH 1
10048 /* The mask used to set the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field value. */
10049 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
10050 /* The mask used to clear the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field value. */
10051 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
10052 /* The reset value of the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field. */
10053 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_RESET 0x0
10054 /* Extracts the ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY field value from a register. */
10055 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
10056 /* Produces a ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY register field value suitable for setting the register. */
10057 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
10058 
10059 /*
10060  * Field : RESPONSE_INDEX
10061  *
10062  * Index of previous response, including any auto-stop sent by core
10063  *
10064  * Field Access Macros:
10065  *
10066  */
10067 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_RESPONSE_INDEX register field. */
10068 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_LSB 11
10069 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_RESPONSE_INDEX register field. */
10070 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_MSB 16
10071 /* The width in bits of the ALT_SDMMC_STATUS_RESPONSE_INDEX register field. */
10072 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_WIDTH 6
10073 /* The mask used to set the ALT_SDMMC_STATUS_RESPONSE_INDEX register field value. */
10074 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_SET_MSK 0x0001f800
10075 /* The mask used to clear the ALT_SDMMC_STATUS_RESPONSE_INDEX register field value. */
10076 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
10077 /* The reset value of the ALT_SDMMC_STATUS_RESPONSE_INDEX register field. */
10078 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_RESET 0x0
10079 /* Extracts the ALT_SDMMC_STATUS_RESPONSE_INDEX field value from a register. */
10080 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
10081 /* Produces a ALT_SDMMC_STATUS_RESPONSE_INDEX register field value suitable for setting the register. */
10082 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
10083 
10084 /*
10085  * Field : FIFO_COUNT
10086  *
10087  * FIFO count Number of filled locations in FIFO
10088  *
10089  * Field Access Macros:
10090  *
10091  */
10092 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_FIFO_COUNT register field. */
10093 #define ALT_SDMMC_STATUS_FIFO_COUNT_LSB 17
10094 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_FIFO_COUNT register field. */
10095 #define ALT_SDMMC_STATUS_FIFO_COUNT_MSB 29
10096 /* The width in bits of the ALT_SDMMC_STATUS_FIFO_COUNT register field. */
10097 #define ALT_SDMMC_STATUS_FIFO_COUNT_WIDTH 13
10098 /* The mask used to set the ALT_SDMMC_STATUS_FIFO_COUNT register field value. */
10099 #define ALT_SDMMC_STATUS_FIFO_COUNT_SET_MSK 0x3ffe0000
10100 /* The mask used to clear the ALT_SDMMC_STATUS_FIFO_COUNT register field value. */
10101 #define ALT_SDMMC_STATUS_FIFO_COUNT_CLR_MSK 0xc001ffff
10102 /* The reset value of the ALT_SDMMC_STATUS_FIFO_COUNT register field. */
10103 #define ALT_SDMMC_STATUS_FIFO_COUNT_RESET 0x0
10104 /* Extracts the ALT_SDMMC_STATUS_FIFO_COUNT field value from a register. */
10105 #define ALT_SDMMC_STATUS_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
10106 /* Produces a ALT_SDMMC_STATUS_FIFO_COUNT register field value suitable for setting the register. */
10107 #define ALT_SDMMC_STATUS_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
10108 
10109 /*
10110  * Field : DMA_ACK
10111  *
10112  * DMA acknowledge signal state; either dw_dma_ack or
10113  *
10114  * ge_dma_ack, depending on DW-DMA or Generic-DMA selection.
10115  *
10116  * Field Enumeration Values:
10117  *
10118  * Enum | Value | Description
10119  * :--------------------------------|:------|:---------------------
10120  * ALT_SDMMC_STATUS_DMA_ACK_E_LOW | 0x0 | DMA ack not asserted
10121  * ALT_SDMMC_STATUS_DMA_ACK_E_HIGH | 0x1 | DMA ack asserted
10122  *
10123  * Field Access Macros:
10124  *
10125  */
10126 /*
10127  * Enumerated value for register field ALT_SDMMC_STATUS_DMA_ACK
10128  *
10129  * DMA ack not asserted
10130  */
10131 #define ALT_SDMMC_STATUS_DMA_ACK_E_LOW 0x0
10132 /*
10133  * Enumerated value for register field ALT_SDMMC_STATUS_DMA_ACK
10134  *
10135  * DMA ack asserted
10136  */
10137 #define ALT_SDMMC_STATUS_DMA_ACK_E_HIGH 0x1
10138 
10139 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_DMA_ACK register field. */
10140 #define ALT_SDMMC_STATUS_DMA_ACK_LSB 30
10141 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_DMA_ACK register field. */
10142 #define ALT_SDMMC_STATUS_DMA_ACK_MSB 30
10143 /* The width in bits of the ALT_SDMMC_STATUS_DMA_ACK register field. */
10144 #define ALT_SDMMC_STATUS_DMA_ACK_WIDTH 1
10145 /* The mask used to set the ALT_SDMMC_STATUS_DMA_ACK register field value. */
10146 #define ALT_SDMMC_STATUS_DMA_ACK_SET_MSK 0x40000000
10147 /* The mask used to clear the ALT_SDMMC_STATUS_DMA_ACK register field value. */
10148 #define ALT_SDMMC_STATUS_DMA_ACK_CLR_MSK 0xbfffffff
10149 /* The reset value of the ALT_SDMMC_STATUS_DMA_ACK register field. */
10150 #define ALT_SDMMC_STATUS_DMA_ACK_RESET 0x0
10151 /* Extracts the ALT_SDMMC_STATUS_DMA_ACK field value from a register. */
10152 #define ALT_SDMMC_STATUS_DMA_ACK_GET(value) (((value) & 0x40000000) >> 30)
10153 /* Produces a ALT_SDMMC_STATUS_DMA_ACK register field value suitable for setting the register. */
10154 #define ALT_SDMMC_STATUS_DMA_ACK_SET(value) (((value) << 30) & 0x40000000)
10155 
10156 /*
10157  * Field : DMA_REQ
10158  *
10159  * DMA request signal state; either dw_dma_req or ge_dma_req,
10160  *
10161  * depending on DW-DMA or Generic-DMA selection.
10162  *
10163  * Field Enumeration Values:
10164  *
10165  * Enum | Value | Description
10166  * :--------------------------------|:------|:-------------------------
10167  * ALT_SDMMC_STATUS_DMA_REQ_E_LOW | 0x0 | DMA request not asserted
10168  * ALT_SDMMC_STATUS_DMA_REQ_E_HIGH | 0x1 | DMA request asserted
10169  *
10170  * Field Access Macros:
10171  *
10172  */
10173 /*
10174  * Enumerated value for register field ALT_SDMMC_STATUS_DMA_REQ
10175  *
10176  * DMA request not asserted
10177  */
10178 #define ALT_SDMMC_STATUS_DMA_REQ_E_LOW 0x0
10179 /*
10180  * Enumerated value for register field ALT_SDMMC_STATUS_DMA_REQ
10181  *
10182  * DMA request asserted
10183  */
10184 #define ALT_SDMMC_STATUS_DMA_REQ_E_HIGH 0x1
10185 
10186 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STATUS_DMA_REQ register field. */
10187 #define ALT_SDMMC_STATUS_DMA_REQ_LSB 31
10188 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STATUS_DMA_REQ register field. */
10189 #define ALT_SDMMC_STATUS_DMA_REQ_MSB 31
10190 /* The width in bits of the ALT_SDMMC_STATUS_DMA_REQ register field. */
10191 #define ALT_SDMMC_STATUS_DMA_REQ_WIDTH 1
10192 /* The mask used to set the ALT_SDMMC_STATUS_DMA_REQ register field value. */
10193 #define ALT_SDMMC_STATUS_DMA_REQ_SET_MSK 0x80000000
10194 /* The mask used to clear the ALT_SDMMC_STATUS_DMA_REQ register field value. */
10195 #define ALT_SDMMC_STATUS_DMA_REQ_CLR_MSK 0x7fffffff
10196 /* The reset value of the ALT_SDMMC_STATUS_DMA_REQ register field. */
10197 #define ALT_SDMMC_STATUS_DMA_REQ_RESET 0x0
10198 /* Extracts the ALT_SDMMC_STATUS_DMA_REQ field value from a register. */
10199 #define ALT_SDMMC_STATUS_DMA_REQ_GET(value) (((value) & 0x80000000) >> 31)
10200 /* Produces a ALT_SDMMC_STATUS_DMA_REQ register field value suitable for setting the register. */
10201 #define ALT_SDMMC_STATUS_DMA_REQ_SET(value) (((value) << 31) & 0x80000000)
10202 
10203 #ifndef __ASSEMBLY__
10204 /*
10205  * WARNING: The C register and register group struct declarations are provided for
10206  * convenience and illustrative purposes. They should, however, be used with
10207  * caution as the C language standard provides no guarantees about the alignment or
10208  * atomicity of device memory accesses. The recommended practice for coding device
10209  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10210  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10211  * alt_write_dword() functions for 64 bit registers.
10212  *
10213  * The struct declaration for register ALT_SDMMC_STATUS.
10214  */
10215 struct ALT_SDMMC_STATUS_s
10216 {
10217  const volatile uint32_t FIFO_RX_WATERMARK : 1; /* ALT_SDMMC_STATUS_FIFO_RX_WATERMARK */
10218  const volatile uint32_t FIFO_TX_WATERMARK : 1; /* ALT_SDMMC_STATUS_FIFO_TX_WATERMARK */
10219  const volatile uint32_t FIFO_EMPTY : 1; /* ALT_SDMMC_STATUS_FIFO_EMPTY */
10220  const volatile uint32_t FIFO_FULL : 1; /* ALT_SDMMC_STATUS_FIFO_FULL */
10221  const volatile uint32_t COMMAND_FSM_STATES : 4; /* ALT_SDMMC_STATUS_COMMAND_FSM_STATES */
10222  const volatile uint32_t DATA_3_STATUS : 1; /* ALT_SDMMC_STATUS_DATA_3_STATUS */
10223  const volatile uint32_t DATA_BUSY : 1; /* ALT_SDMMC_STATUS_DATA_BUSY */
10224  const volatile uint32_t DATA_STATE_MC_BUSY : 1; /* ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY */
10225  const volatile uint32_t RESPONSE_INDEX : 6; /* ALT_SDMMC_STATUS_RESPONSE_INDEX */
10226  const volatile uint32_t FIFO_COUNT : 13; /* ALT_SDMMC_STATUS_FIFO_COUNT */
10227  const volatile uint32_t DMA_ACK : 1; /* ALT_SDMMC_STATUS_DMA_ACK */
10228  const volatile uint32_t DMA_REQ : 1; /* ALT_SDMMC_STATUS_DMA_REQ */
10229 };
10230 
10231 /* The typedef declaration for register ALT_SDMMC_STATUS. */
10232 typedef struct ALT_SDMMC_STATUS_s ALT_SDMMC_STATUS_t;
10233 #endif /* __ASSEMBLY__ */
10234 
10235 /* The reset value of the ALT_SDMMC_STATUS register. */
10236 #define ALT_SDMMC_STATUS_RESET 0x00000106
10237 /* The byte offset of the ALT_SDMMC_STATUS register from the beginning of the component. */
10238 #define ALT_SDMMC_STATUS_OFST 0x48
10239 /* The address of the ALT_SDMMC_STATUS register. */
10240 #define ALT_SDMMC_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_STATUS_OFST))
10241 
10242 /*
10243  * Register : FIFO Threshold Watermark Register - FIFOTH
10244  *
10245  * Name: FIFO Threshold Watermark Register
10246  *
10247  * Size: 32 bits
10248  *
10249  * Address Offset: 0x4C
10250  *
10251  * Read/write access: write/read
10252  *
10253  * Register Layout
10254  *
10255  * Bits | Access | Reset | Description
10256  * :--------|:-------|:------|:--------------------------------------------------
10257  * [11:0] | RW | 0x0 | ALT_SDMMC_FIFOTH_TX_WMARK
10258  * [15:12] | ??? | 0x0 | *UNDEFINED*
10259  * [27:16] | RW | 0x3ff | ALT_SDMMC_FIFOTH_RX_WMARK
10260  * [30:28] | RW | 0x0 | ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10261  * [31] | ??? | 0x0 | *UNDEFINED*
10262  *
10263  */
10264 /*
10265  * Field : TX_WMark
10266  *
10267  * FIFO threshold watermark level when transmitting data to card.
10268  *
10269  * When FIFO data count is less than or equal to this number,DMA/FIFO request is
10270  * raised. If Interrupt is enabled, then interrupt occurs. During end of packet,
10271  * request or interrupt is generated,regardless of threshold programming.
10272  *
10273  * In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then
10274  * interrupt is generated instead of DMA request. During end of packet, on last
10275  * interrupt, host is responsible for filling FIFO with only required remaining
10276  * bytes (not before FIFO is full or after CIU completes data transfers, because
10277  * FIFO may not be empty).
10278  *
10279  * In DMA mode, at end of packet, if last transfer is less than burst size, DMA
10280  * controller does single cycles until required bytes are transferred.
10281  *
10282  * 12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
10283  *
10284  * Limitation: TX_WMark >= 1;
10285  *
10286  * Recommended: FIFO_DEPTH/2; (means less than or equal to FIFO_DEPTH/2)
10287  *
10288  * Field Access Macros:
10289  *
10290  */
10291 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
10292 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
10293 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
10294 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
10295 /* The width in bits of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
10296 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
10297 /* The mask used to set the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
10298 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
10299 /* The mask used to clear the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
10300 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
10301 /* The reset value of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
10302 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
10303 /* Extracts the ALT_SDMMC_FIFOTH_TX_WMARK field value from a register. */
10304 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
10305 /* Produces a ALT_SDMMC_FIFOTH_TX_WMARK register field value suitable for setting the register. */
10306 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
10307 
10308 /*
10309  * Field : RX_WMark
10310  *
10311  * FIFO threshold watermark level when receiving data to card.
10312  *
10313  * When FIFO data count reaches greater than this number,DMA/FIFO request is
10314  * raised. During end of packet, request is
10315  *
10316  * generated regardless of threshold programming in order to complete any remaining
10317  * data.
10318  *
10319  * In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then
10320  * interrupt is generated instead of DMA request.
10321  *
10322  * During end of packet, interrupt is not generated if threshold programming is
10323  * larger than any remaining data. It is responsibility of host to read remaining
10324  * bytes on seeing Data Transfer Done interrupt.
10325  *
10326  * In DMA mode, at end of packet, even if remaining bytes are less than threshold,
10327  * DMA request does single transfers to flush out any remaining bytes before Data
10328  * Transfer Done interrupt is set.
10329  *
10330  * 12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
10331  *
10332  * Limitation: RX_WMark <= FIFO_DEPTH-2
10333  *
10334  * Recommended: (FIFO_DEPTH/2) - 1; (means greater than (FIFO_DEPTH/2) - 1)
10335  *
10336  * NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at
10337  * the end of packet, even if remaining bytes are less than threshold. In this
10338  * case, there will be some data left in the FIFO. It is the responsibility of the
10339  * application to reset the FIFO after the CCS timeout.
10340  *
10341  * Field Access Macros:
10342  *
10343  */
10344 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
10345 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
10346 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
10347 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
10348 /* The width in bits of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
10349 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
10350 /* The mask used to set the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
10351 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
10352 /* The mask used to clear the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
10353 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
10354 /* The reset value of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
10355 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
10356 /* Extracts the ALT_SDMMC_FIFOTH_RX_WMARK field value from a register. */
10357 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
10358 /* Produces a ALT_SDMMC_FIFOTH_RX_WMARK register field value suitable for setting the register. */
10359 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
10360 
10361 /*
10362  * Field : DW_DMA_Multiple_Transaction_Size
10363  *
10364  * Burst size of multiple transaction; should be programmed same as
10365  *
10366  * DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.
10367  *
10368  * 000 1 transfers
10369  *
10370  * 001 4
10371  *
10372  * 010 8
10373  *
10374  * 011 16
10375  *
10376  * 100 32
10377  *
10378  * 101 64
10379  *
10380  * 110 128
10381  *
10382  * 111 256
10383  *
10384  * The units for transfers is the H_DATA_WIDTH parameter. A single transfer
10385  * (dw_dma_single assertion in case of Non DW DMA interface) would be signalled
10386  * based on this value.
10387  *
10388  * Value should be sub-multiple of (RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and
10389  *
10390  * (FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/H_DATA_WIDTH)
10391  *
10392  * For example, if FIFO_DEPTH = 16,
10393  *
10394  * FDATA_WIDTH == H_DATA_WIDTH
10395  *
10396  * Allowed combinations for MSize and TX_WMark are:
10397  *
10398  * MSize = 1, TX_WMARK = 1-15
10399  *
10400  * MSize = 4, TX_WMark = 8
10401  *
10402  * MSize = 4, TX_WMark = 4
10403  *
10404  * MSize = 4, TX_WMark = 12
10405  *
10406  * MSize = 8, TX_WMark = 8
10407  *
10408  * MSize = 8, TX_WMark = 4
10409  *
10410  * Allowed combinations for MSize and RX_WMark are:
10411  *
10412  * MSize = 1, RX_WMARK = 0-14
10413  *
10414  * MSize = 4, RX_WMark = 3
10415  *
10416  * MSize = 4, RX_WMark = 7
10417  *
10418  * MSize = 4, RX_WMark = 11
10419  *
10420  * MSize = 8, RX_WMark = 7
10421  *
10422  * Recommended:
10423  *
10424  * MSize = 8, TX_WMark = 8, RX_WMark = 7
10425  *
10426  * Field Enumeration Values:
10427  *
10428  * Enum | Value | Description
10429  * :--------------------------------------------------------------|:------|:-------------
10430  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_1 | 0x0 | Burst of 1
10431  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_4 | 0x1 | Burst of 4
10432  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_8 | 0x2 | Burst of 8
10433  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_16 | 0x3 | Burst of 16
10434  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_32 | 0x4 | Burst of 32
10435  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_64 | 0x5 | Burst of 64
10436  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_128 | 0x6 | Burst of 128
10437  * ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_256 | 0x7 | Burst of 256
10438  *
10439  * Field Access Macros:
10440  *
10441  */
10442 /*
10443  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10444  *
10445  * Burst of 1
10446  */
10447 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_1 0x0
10448 /*
10449  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10450  *
10451  * Burst of 4
10452  */
10453 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_4 0x1
10454 /*
10455  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10456  *
10457  * Burst of 8
10458  */
10459 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_8 0x2
10460 /*
10461  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10462  *
10463  * Burst of 16
10464  */
10465 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_16 0x3
10466 /*
10467  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10468  *
10469  * Burst of 32
10470  */
10471 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_32 0x4
10472 /*
10473  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10474  *
10475  * Burst of 64
10476  */
10477 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_64 0x5
10478 /*
10479  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10480  *
10481  * Burst of 128
10482  */
10483 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_128 0x6
10484 /*
10485  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE
10486  *
10487  * Burst of 256
10488  */
10489 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_256 0x7
10490 
10491 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field. */
10492 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_LSB 28
10493 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field. */
10494 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_MSB 30
10495 /* The width in bits of the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field. */
10496 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_WIDTH 3
10497 /* The mask used to set the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field value. */
10498 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_SET_MSK 0x70000000
10499 /* The mask used to clear the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field value. */
10500 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
10501 /* The reset value of the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field. */
10502 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_RESET 0x0
10503 /* Extracts the ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE field value from a register. */
10504 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
10505 /* Produces a ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE register field value suitable for setting the register. */
10506 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
10507 
10508 #ifndef __ASSEMBLY__
10509 /*
10510  * WARNING: The C register and register group struct declarations are provided for
10511  * convenience and illustrative purposes. They should, however, be used with
10512  * caution as the C language standard provides no guarantees about the alignment or
10513  * atomicity of device memory accesses. The recommended practice for coding device
10514  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10515  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10516  * alt_write_dword() functions for 64 bit registers.
10517  *
10518  * The struct declaration for register ALT_SDMMC_FIFOTH.
10519  */
10520 struct ALT_SDMMC_FIFOTH_s
10521 {
10522  volatile uint32_t TX_WMark : 12; /* ALT_SDMMC_FIFOTH_TX_WMARK */
10523  uint32_t : 4; /* *UNDEFINED* */
10524  volatile uint32_t RX_WMark : 12; /* ALT_SDMMC_FIFOTH_RX_WMARK */
10525  volatile uint32_t DW_DMA_Multiple_Transaction_Size : 3; /* ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE */
10526  uint32_t : 1; /* *UNDEFINED* */
10527 };
10528 
10529 /* The typedef declaration for register ALT_SDMMC_FIFOTH. */
10530 typedef struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
10531 #endif /* __ASSEMBLY__ */
10532 
10533 /* The reset value of the ALT_SDMMC_FIFOTH register. */
10534 #define ALT_SDMMC_FIFOTH_RESET 0x03ff0000
10535 /* The byte offset of the ALT_SDMMC_FIFOTH register from the beginning of the component. */
10536 #define ALT_SDMMC_FIFOTH_OFST 0x4c
10537 /* The address of the ALT_SDMMC_FIFOTH register. */
10538 #define ALT_SDMMC_FIFOTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_FIFOTH_OFST))
10539 
10540 /*
10541  * Register : Card Detect Register - CDETECT
10542  *
10543  * Name: Card Detect Register
10544  *
10545  * Size: 32 bits
10546  *
10547  * Address Offset: 0x50
10548  *
10549  * Read/write access: read-only
10550  *
10551  * Register Layout
10552  *
10553  * Bits | Access | Reset | Description
10554  * :-------|:-------|:------|:---------------------------------
10555  * [0] | R | 0x1 | ALT_SDMMC_CDETECT_CARD0_DETECT_N
10556  * [31:1] | ??? | 0x0 | *UNDEFINED*
10557  *
10558  */
10559 /*
10560  * Field : CARD0_DETECT_N
10561  *
10562  * Value on card_detect_n input ports (1 bit per card); read-only bits.0 represents
10563  * presence of card. Only NUM_CARDS number of bits are implemented.
10564  *
10565  * Field Enumeration Values:
10566  *
10567  * Enum | Value | Description
10568  * :----------------------------------------|:------|:-----------------------------------------------
10569  * ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_LOW | 0x0 | low Indicates presence of cards;Only NUM_CARDS
10570  * : | | number of bits are implemented
10571  * ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_HIGH | 0x1 | Card is not present
10572  *
10573  * Field Access Macros:
10574  *
10575  */
10576 /*
10577  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD0_DETECT_N
10578  *
10579  * low Indicates presence of cards;Only NUM_CARDS number of bits are implemented
10580  */
10581 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_LOW 0x0
10582 /*
10583  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD0_DETECT_N
10584  *
10585  * Card is not present
10586  */
10587 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_HIGH 0x1
10588 
10589 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field. */
10590 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_LSB 0
10591 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field. */
10592 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_MSB 0
10593 /* The width in bits of the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field. */
10594 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_WIDTH 1
10595 /* The mask used to set the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field value. */
10596 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_SET_MSK 0x00000001
10597 /* The mask used to clear the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field value. */
10598 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_CLR_MSK 0xfffffffe
10599 /* The reset value of the ALT_SDMMC_CDETECT_CARD0_DETECT_N register field. */
10600 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_RESET 0x1
10601 /* Extracts the ALT_SDMMC_CDETECT_CARD0_DETECT_N field value from a register. */
10602 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
10603 /* Produces a ALT_SDMMC_CDETECT_CARD0_DETECT_N register field value suitable for setting the register. */
10604 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
10605 
10606 #ifndef __ASSEMBLY__
10607 /*
10608  * WARNING: The C register and register group struct declarations are provided for
10609  * convenience and illustrative purposes. They should, however, be used with
10610  * caution as the C language standard provides no guarantees about the alignment or
10611  * atomicity of device memory accesses. The recommended practice for coding device
10612  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10613  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10614  * alt_write_dword() functions for 64 bit registers.
10615  *
10616  * The struct declaration for register ALT_SDMMC_CDETECT.
10617  */
10618 struct ALT_SDMMC_CDETECT_s
10619 {
10620  const volatile uint32_t CARD0_DETECT_N : 1; /* ALT_SDMMC_CDETECT_CARD0_DETECT_N */
10621  uint32_t : 31; /* *UNDEFINED* */
10622 };
10623 
10624 /* The typedef declaration for register ALT_SDMMC_CDETECT. */
10625 typedef struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
10626 #endif /* __ASSEMBLY__ */
10627 
10628 /* The reset value of the ALT_SDMMC_CDETECT register. */
10629 #define ALT_SDMMC_CDETECT_RESET 0x00000001
10630 /* The byte offset of the ALT_SDMMC_CDETECT register from the beginning of the component. */
10631 #define ALT_SDMMC_CDETECT_OFST 0x50
10632 /* The address of the ALT_SDMMC_CDETECT register. */
10633 #define ALT_SDMMC_CDETECT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CDETECT_OFST))
10634 
10635 /*
10636  * Register : Write Protect Register - WRTPRT
10637  *
10638  * Name: Write Protect Register
10639  *
10640  * Size: 32 bits
10641  *
10642  * Address Offset: 0x54
10643  *
10644  * Read/write access: read-only
10645  *
10646  * Register Layout
10647  *
10648  * Bits | Access | Reset | Description
10649  * :-------|:-------|:------|:---------------------------------
10650  * [0] | R | 0x1 | ALT_SDMMC_WRTPRT_WRITE_PROTECT_0
10651  * [31:1] | ??? | 0x0 | *UNDEFINED*
10652  *
10653  */
10654 /*
10655  * Field : WRITE_PROTECT_0
10656  *
10657  * Value on card_write_prt input ports (1 bit per card).
10658  *
10659  * 1 represents write protection. Only NUM_CARDS number of bits are implemented.
10660  *
10661  * Field Enumeration Values:
10662  *
10663  * Enum | Value | Description
10664  * :----------------------------------------|:------|:----------------------------------------------
10665  * ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_LOW | 0x0 | Not write protected ;Only NUM_CARDS number of
10666  * : | | bits are implemented
10667  * ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_HIGH | 0x1 | This represents write protection
10668  *
10669  * Field Access Macros:
10670  *
10671  */
10672 /*
10673  * Enumerated value for register field ALT_SDMMC_WRTPRT_WRITE_PROTECT_0
10674  *
10675  * Not write protected ;Only NUM_CARDS number of bits are implemented
10676  */
10677 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_LOW 0x0
10678 /*
10679  * Enumerated value for register field ALT_SDMMC_WRTPRT_WRITE_PROTECT_0
10680  *
10681  * This represents write protection
10682  */
10683 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_HIGH 0x1
10684 
10685 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field. */
10686 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_LSB 0
10687 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field. */
10688 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_MSB 0
10689 /* The width in bits of the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field. */
10690 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_WIDTH 1
10691 /* The mask used to set the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field value. */
10692 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_SET_MSK 0x00000001
10693 /* The mask used to clear the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field value. */
10694 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_CLR_MSK 0xfffffffe
10695 /* The reset value of the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field. */
10696 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_RESET 0x1
10697 /* Extracts the ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 field value from a register. */
10698 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_GET(value) (((value) & 0x00000001) >> 0)
10699 /* Produces a ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 register field value suitable for setting the register. */
10700 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_SET(value) (((value) << 0) & 0x00000001)
10701 
10702 #ifndef __ASSEMBLY__
10703 /*
10704  * WARNING: The C register and register group struct declarations are provided for
10705  * convenience and illustrative purposes. They should, however, be used with
10706  * caution as the C language standard provides no guarantees about the alignment or
10707  * atomicity of device memory accesses. The recommended practice for coding device
10708  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10709  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10710  * alt_write_dword() functions for 64 bit registers.
10711  *
10712  * The struct declaration for register ALT_SDMMC_WRTPRT.
10713  */
10714 struct ALT_SDMMC_WRTPRT_s
10715 {
10716  const volatile uint32_t WRITE_PROTECT_0 : 1; /* ALT_SDMMC_WRTPRT_WRITE_PROTECT_0 */
10717  uint32_t : 31; /* *UNDEFINED* */
10718 };
10719 
10720 /* The typedef declaration for register ALT_SDMMC_WRTPRT. */
10721 typedef struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
10722 #endif /* __ASSEMBLY__ */
10723 
10724 /* The reset value of the ALT_SDMMC_WRTPRT register. */
10725 #define ALT_SDMMC_WRTPRT_RESET 0x00000001
10726 /* The byte offset of the ALT_SDMMC_WRTPRT register from the beginning of the component. */
10727 #define ALT_SDMMC_WRTPRT_OFST 0x54
10728 /* The address of the ALT_SDMMC_WRTPRT register. */
10729 #define ALT_SDMMC_WRTPRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_WRTPRT_OFST))
10730 
10731 /*
10732  * Register : General Purpose Input/Output Register - GPIO
10733  *
10734  * Name: General Purpose Input/Output Register
10735  *
10736  * Size: 32 bits
10737  *
10738  * Address Offset: 0x58
10739  *
10740  * Read/write access: Partly write/read and partly read-only
10741  *
10742  * Register Layout
10743  *
10744  * Bits | Access | Reset | Description
10745  * :--------|:-------|:------|:-------------------
10746  * [7:0] | R | 0x0 | ALT_SDMMC_GPIO_GPI
10747  * [23:8] | RW | 0x0 | ALT_SDMMC_GPIO_GPO
10748  * [31:24] | ??? | 0x0 | *UNDEFINED*
10749  *
10750  */
10751 /*
10752  * Field : GPI
10753  *
10754  * Value on gpi input ports; this portion of register is read-only. Valid only when
10755  * AREA_OPTIMIZED parameter is 0.
10756  *
10757  * Field Access Macros:
10758  *
10759  */
10760 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_GPIO_GPI register field. */
10761 #define ALT_SDMMC_GPIO_GPI_LSB 0
10762 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_GPIO_GPI register field. */
10763 #define ALT_SDMMC_GPIO_GPI_MSB 7
10764 /* The width in bits of the ALT_SDMMC_GPIO_GPI register field. */
10765 #define ALT_SDMMC_GPIO_GPI_WIDTH 8
10766 /* The mask used to set the ALT_SDMMC_GPIO_GPI register field value. */
10767 #define ALT_SDMMC_GPIO_GPI_SET_MSK 0x000000ff
10768 /* The mask used to clear the ALT_SDMMC_GPIO_GPI register field value. */
10769 #define ALT_SDMMC_GPIO_GPI_CLR_MSK 0xffffff00
10770 /* The reset value of the ALT_SDMMC_GPIO_GPI register field. */
10771 #define ALT_SDMMC_GPIO_GPI_RESET 0x0
10772 /* Extracts the ALT_SDMMC_GPIO_GPI field value from a register. */
10773 #define ALT_SDMMC_GPIO_GPI_GET(value) (((value) & 0x000000ff) >> 0)
10774 /* Produces a ALT_SDMMC_GPIO_GPI register field value suitable for setting the register. */
10775 #define ALT_SDMMC_GPIO_GPI_SET(value) (((value) << 0) & 0x000000ff)
10776 
10777 /*
10778  * Field : GPO
10779  *
10780  * Value needed to be driven to gpo pins; this portion of register is read/write.
10781  * Valid only when AREA_OPTIMIZED parameter is 0.
10782  *
10783  * Field Access Macros:
10784  *
10785  */
10786 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_GPIO_GPO register field. */
10787 #define ALT_SDMMC_GPIO_GPO_LSB 8
10788 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_GPIO_GPO register field. */
10789 #define ALT_SDMMC_GPIO_GPO_MSB 23
10790 /* The width in bits of the ALT_SDMMC_GPIO_GPO register field. */
10791 #define ALT_SDMMC_GPIO_GPO_WIDTH 16
10792 /* The mask used to set the ALT_SDMMC_GPIO_GPO register field value. */
10793 #define ALT_SDMMC_GPIO_GPO_SET_MSK 0x00ffff00
10794 /* The mask used to clear the ALT_SDMMC_GPIO_GPO register field value. */
10795 #define ALT_SDMMC_GPIO_GPO_CLR_MSK 0xff0000ff
10796 /* The reset value of the ALT_SDMMC_GPIO_GPO register field. */
10797 #define ALT_SDMMC_GPIO_GPO_RESET 0x0
10798 /* Extracts the ALT_SDMMC_GPIO_GPO field value from a register. */
10799 #define ALT_SDMMC_GPIO_GPO_GET(value) (((value) & 0x00ffff00) >> 8)
10800 /* Produces a ALT_SDMMC_GPIO_GPO register field value suitable for setting the register. */
10801 #define ALT_SDMMC_GPIO_GPO_SET(value) (((value) << 8) & 0x00ffff00)
10802 
10803 #ifndef __ASSEMBLY__
10804 /*
10805  * WARNING: The C register and register group struct declarations are provided for
10806  * convenience and illustrative purposes. They should, however, be used with
10807  * caution as the C language standard provides no guarantees about the alignment or
10808  * atomicity of device memory accesses. The recommended practice for coding device
10809  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10810  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10811  * alt_write_dword() functions for 64 bit registers.
10812  *
10813  * The struct declaration for register ALT_SDMMC_GPIO.
10814  */
10815 struct ALT_SDMMC_GPIO_s
10816 {
10817  const volatile uint32_t GPI : 8; /* ALT_SDMMC_GPIO_GPI */
10818  volatile uint32_t GPO : 16; /* ALT_SDMMC_GPIO_GPO */
10819  uint32_t : 8; /* *UNDEFINED* */
10820 };
10821 
10822 /* The typedef declaration for register ALT_SDMMC_GPIO. */
10823 typedef struct ALT_SDMMC_GPIO_s ALT_SDMMC_GPIO_t;
10824 #endif /* __ASSEMBLY__ */
10825 
10826 /* The reset value of the ALT_SDMMC_GPIO register. */
10827 #define ALT_SDMMC_GPIO_RESET 0x00000000
10828 /* The byte offset of the ALT_SDMMC_GPIO register from the beginning of the component. */
10829 #define ALT_SDMMC_GPIO_OFST 0x58
10830 /* The address of the ALT_SDMMC_GPIO register. */
10831 #define ALT_SDMMC_GPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_GPIO_OFST))
10832 
10833 /*
10834  * Register : Transferred CIU Card Byte Count Register - TCBCNT
10835  *
10836  * Name: Transferred CIU Card Byte Count Register
10837  *
10838  * Size: 32 bits
10839  *
10840  * Address Offset: 0x5C
10841  *
10842  * Read/write access: read
10843  *
10844  * Register Layout
10845  *
10846  * Bits | Access | Reset | Description
10847  * :-------|:-------|:------|:---------------------------------------
10848  * [31:0] | R | 0x0 | ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT
10849  *
10850  */
10851 /*
10852  * Field : TRANS_CARD_BYTE_COUNT
10853  *
10854  * Number of bytes transferred by CIU unit to card.
10855  *
10856  * In 32-bit or 64-bit AMBA data-bus-width modes, register should be accessed in
10857  * full to avoid read-coherency problems.In 16-bit AMBA data-bus-width mode,
10858  * internal 16-bit coherency register is implemented. User should first read lower
10859  * 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of
10860  * counter are stored in temporary register. When higher 16 bits are read, data
10861  * from temporary register is supplied. Both TCBCNT and TBBCNT share same coherency
10862  * register. When AREA_OPTIMIZED parameter is 1, register should be read only after
10863  * data transfer completes; during data transfer,register returns 0.
10864  *
10865  * Field Access Macros:
10866  *
10867  */
10868 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
10869 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
10870 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
10871 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
10872 /* The width in bits of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
10873 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
10874 /* The mask used to set the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
10875 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
10876 /* The mask used to clear the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
10877 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
10878 /* The reset value of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
10879 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
10880 /* Extracts the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT field value from a register. */
10881 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
10882 /* Produces a ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value suitable for setting the register. */
10883 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
10884 
10885 #ifndef __ASSEMBLY__
10886 /*
10887  * WARNING: The C register and register group struct declarations are provided for
10888  * convenience and illustrative purposes. They should, however, be used with
10889  * caution as the C language standard provides no guarantees about the alignment or
10890  * atomicity of device memory accesses. The recommended practice for coding device
10891  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10892  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10893  * alt_write_dword() functions for 64 bit registers.
10894  *
10895  * The struct declaration for register ALT_SDMMC_TCBCNT.
10896  */
10897 struct ALT_SDMMC_TCBCNT_s
10898 {
10899  const volatile uint32_t TRANS_CARD_BYTE_COUNT : 32; /* ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT */
10900 };
10901 
10902 /* The typedef declaration for register ALT_SDMMC_TCBCNT. */
10903 typedef struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
10904 #endif /* __ASSEMBLY__ */
10905 
10906 /* The reset value of the ALT_SDMMC_TCBCNT register. */
10907 #define ALT_SDMMC_TCBCNT_RESET 0x00000000
10908 /* The byte offset of the ALT_SDMMC_TCBCNT register from the beginning of the component. */
10909 #define ALT_SDMMC_TCBCNT_OFST 0x5c
10910 /* The address of the ALT_SDMMC_TCBCNT register. */
10911 #define ALT_SDMMC_TCBCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TCBCNT_OFST))
10912 
10913 /*
10914  * Register : Transferred Host to BIU-FIFO Byte Count Register - TBBCNT
10915  *
10916  * Name: Transferred Host to BIU-FIFO Byte Count Register
10917  *
10918  * Size: 32 bits
10919  *
10920  * Address Offset: 0x60
10921  *
10922  * Read/write access: read
10923  *
10924  * Register Layout
10925  *
10926  * Bits | Access | Reset | Description
10927  * :-------|:-------|:------|:---------------------------------------
10928  * [31:0] | R | 0x0 | ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT
10929  *
10930  */
10931 /*
10932  * Field : TRANS_FIFO_BYTE_COUNT
10933  *
10934  * Number of bytes transferred between Host/DMA memory and BIU FIFO.
10935  *
10936  * In 32-bit or 64-bit AMBA data-bus-width modes, register should be accessed in
10937  * full to avoid read-coherency problems.In 16-bit AMBA data-bus-width mode,
10938  * internal 16-bit coherency register is implemented. User should first read lower
10939  * 16 bits and then higher 16 bits. When reading lower 16 bits, higher 16 bits of
10940  * counter are stored in temporary register. When higher 16 bits are read, data
10941  * from temporary register is supplied.
10942  *
10943  * Both TCBCNT and TBBCNT share same coherency register.
10944  *
10945  * Field Access Macros:
10946  *
10947  */
10948 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
10949 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
10950 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
10951 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
10952 /* The width in bits of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
10953 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
10954 /* The mask used to set the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
10955 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
10956 /* The mask used to clear the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
10957 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
10958 /* The reset value of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
10959 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
10960 /* Extracts the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT field value from a register. */
10961 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
10962 /* Produces a ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value suitable for setting the register. */
10963 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
10964 
10965 #ifndef __ASSEMBLY__
10966 /*
10967  * WARNING: The C register and register group struct declarations are provided for
10968  * convenience and illustrative purposes. They should, however, be used with
10969  * caution as the C language standard provides no guarantees about the alignment or
10970  * atomicity of device memory accesses. The recommended practice for coding device
10971  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10972  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10973  * alt_write_dword() functions for 64 bit registers.
10974  *
10975  * The struct declaration for register ALT_SDMMC_TBBCNT.
10976  */
10977 struct ALT_SDMMC_TBBCNT_s
10978 {
10979  const volatile uint32_t TRANS_FIFO_BYTE_COUNT : 32; /* ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT */
10980 };
10981 
10982 /* The typedef declaration for register ALT_SDMMC_TBBCNT. */
10983 typedef struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
10984 #endif /* __ASSEMBLY__ */
10985 
10986 /* The reset value of the ALT_SDMMC_TBBCNT register. */
10987 #define ALT_SDMMC_TBBCNT_RESET 0x00000000
10988 /* The byte offset of the ALT_SDMMC_TBBCNT register from the beginning of the component. */
10989 #define ALT_SDMMC_TBBCNT_OFST 0x60
10990 /* The address of the ALT_SDMMC_TBBCNT register. */
10991 #define ALT_SDMMC_TBBCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TBBCNT_OFST))
10992 
10993 /*
10994  * Register : Debounce Count Register - DEBNCE
10995  *
10996  * Name: Debounce Count Register
10997  *
10998  * Size: 32 bits
10999  *
11000  * Address Offset: 0x64
11001  *
11002  * Read/write access: write/read
11003  *
11004  * Register Layout
11005  *
11006  * Bits | Access | Reset | Description
11007  * :--------|:-------|:---------|:--------------------------------
11008  * [23:0] | RW | 0xffffff | ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT
11009  * [31:24] | ??? | 0x0 | *UNDEFINED*
11010  *
11011  */
11012 /*
11013  * Field : DEBOUNCE_COUNT
11014  *
11015  * Number of host clocks (clk) used by debounce filter logic; typical
11016  *
11017  * debounce time is 5-25 ms.
11018  *
11019  * Field Access Macros:
11020  *
11021  */
11022 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
11023 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
11024 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
11025 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
11026 /* The width in bits of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
11027 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
11028 /* The mask used to set the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
11029 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
11030 /* The mask used to clear the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
11031 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
11032 /* The reset value of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
11033 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
11034 /* Extracts the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT field value from a register. */
11035 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
11036 /* Produces a ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value suitable for setting the register. */
11037 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
11038 
11039 #ifndef __ASSEMBLY__
11040 /*
11041  * WARNING: The C register and register group struct declarations are provided for
11042  * convenience and illustrative purposes. They should, however, be used with
11043  * caution as the C language standard provides no guarantees about the alignment or
11044  * atomicity of device memory accesses. The recommended practice for coding device
11045  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11046  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11047  * alt_write_dword() functions for 64 bit registers.
11048  *
11049  * The struct declaration for register ALT_SDMMC_DEBNCE.
11050  */
11051 struct ALT_SDMMC_DEBNCE_s
11052 {
11053  volatile uint32_t DEBOUNCE_COUNT : 24; /* ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT */
11054  uint32_t : 8; /* *UNDEFINED* */
11055 };
11056 
11057 /* The typedef declaration for register ALT_SDMMC_DEBNCE. */
11058 typedef struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
11059 #endif /* __ASSEMBLY__ */
11060 
11061 /* The reset value of the ALT_SDMMC_DEBNCE register. */
11062 #define ALT_SDMMC_DEBNCE_RESET 0x00ffffff
11063 /* The byte offset of the ALT_SDMMC_DEBNCE register from the beginning of the component. */
11064 #define ALT_SDMMC_DEBNCE_OFST 0x64
11065 /* The address of the ALT_SDMMC_DEBNCE register. */
11066 #define ALT_SDMMC_DEBNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DEBNCE_OFST))
11067 
11068 /*
11069  * Register : User ID Register - USRID
11070  *
11071  * Name: User ID Register
11072  *
11073  * Size: 32 bits
11074  *
11075  * Address Offset: 0x68
11076  *
11077  * Read/write access: write/readUser ID Register
11078  *
11079  * Register Layout
11080  *
11081  * Bits | Access | Reset | Description
11082  * :-------|:-------|:----------|:-----------------------
11083  * [31:0] | RW | 0x7967797 | ALT_SDMMC_USRID_USR_ID
11084  *
11085  */
11086 /*
11087  * Field : USR_ID
11088  *
11089  * User identification register; value set by user. Default reset value can be
11090  * picked by user while configuring core before synthesis.
11091  *
11092  * Can also be used as scratch pad register by user.
11093  *
11094  * Field Access Macros:
11095  *
11096  */
11097 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
11098 #define ALT_SDMMC_USRID_USR_ID_LSB 0
11099 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
11100 #define ALT_SDMMC_USRID_USR_ID_MSB 31
11101 /* The width in bits of the ALT_SDMMC_USRID_USR_ID register field. */
11102 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
11103 /* The mask used to set the ALT_SDMMC_USRID_USR_ID register field value. */
11104 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
11105 /* The mask used to clear the ALT_SDMMC_USRID_USR_ID register field value. */
11106 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
11107 /* The reset value of the ALT_SDMMC_USRID_USR_ID register field. */
11108 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
11109 /* Extracts the ALT_SDMMC_USRID_USR_ID field value from a register. */
11110 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
11111 /* Produces a ALT_SDMMC_USRID_USR_ID register field value suitable for setting the register. */
11112 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
11113 
11114 #ifndef __ASSEMBLY__
11115 /*
11116  * WARNING: The C register and register group struct declarations are provided for
11117  * convenience and illustrative purposes. They should, however, be used with
11118  * caution as the C language standard provides no guarantees about the alignment or
11119  * atomicity of device memory accesses. The recommended practice for coding device
11120  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11121  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11122  * alt_write_dword() functions for 64 bit registers.
11123  *
11124  * The struct declaration for register ALT_SDMMC_USRID.
11125  */
11126 struct ALT_SDMMC_USRID_s
11127 {
11128  volatile uint32_t USR_ID : 32; /* ALT_SDMMC_USRID_USR_ID */
11129 };
11130 
11131 /* The typedef declaration for register ALT_SDMMC_USRID. */
11132 typedef struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
11133 #endif /* __ASSEMBLY__ */
11134 
11135 /* The reset value of the ALT_SDMMC_USRID register. */
11136 #define ALT_SDMMC_USRID_RESET 0x07967797
11137 /* The byte offset of the ALT_SDMMC_USRID register from the beginning of the component. */
11138 #define ALT_SDMMC_USRID_OFST 0x68
11139 /* The address of the ALT_SDMMC_USRID register. */
11140 #define ALT_SDMMC_USRID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_USRID_OFST))
11141 
11142 /*
11143  * Register : Version ID Register - VERID
11144  *
11145  * Name: Version ID Register
11146  *
11147  * Size: 32 bits
11148  *
11149  * Address Offset: 0x6C
11150  *
11151  * Read/write access: read
11152  *
11153  * Register Layout
11154  *
11155  * Bits | Access | Reset | Description
11156  * :-------|:-------|:-----------|:-----------------------
11157  * [31:0] | R | 0x5342280a | ALT_SDMMC_VERID_VER_ID
11158  *
11159  */
11160 /*
11161  * Field : VER_ID
11162  *
11163  * Synopsys version identification register; register value is hard-wired.Can be
11164  * read by firmware to support different versions of core.
11165  *
11166  * Field Access Macros:
11167  *
11168  */
11169 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
11170 #define ALT_SDMMC_VERID_VER_ID_LSB 0
11171 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
11172 #define ALT_SDMMC_VERID_VER_ID_MSB 31
11173 /* The width in bits of the ALT_SDMMC_VERID_VER_ID register field. */
11174 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
11175 /* The mask used to set the ALT_SDMMC_VERID_VER_ID register field value. */
11176 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
11177 /* The mask used to clear the ALT_SDMMC_VERID_VER_ID register field value. */
11178 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
11179 /* The reset value of the ALT_SDMMC_VERID_VER_ID register field. */
11180 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342280a
11181 /* Extracts the ALT_SDMMC_VERID_VER_ID field value from a register. */
11182 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
11183 /* Produces a ALT_SDMMC_VERID_VER_ID register field value suitable for setting the register. */
11184 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
11185 
11186 #ifndef __ASSEMBLY__
11187 /*
11188  * WARNING: The C register and register group struct declarations are provided for
11189  * convenience and illustrative purposes. They should, however, be used with
11190  * caution as the C language standard provides no guarantees about the alignment or
11191  * atomicity of device memory accesses. The recommended practice for coding device
11192  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11193  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11194  * alt_write_dword() functions for 64 bit registers.
11195  *
11196  * The struct declaration for register ALT_SDMMC_VERID.
11197  */
11198 struct ALT_SDMMC_VERID_s
11199 {
11200  const volatile uint32_t VER_ID : 32; /* ALT_SDMMC_VERID_VER_ID */
11201 };
11202 
11203 /* The typedef declaration for register ALT_SDMMC_VERID. */
11204 typedef struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
11205 #endif /* __ASSEMBLY__ */
11206 
11207 /* The reset value of the ALT_SDMMC_VERID register. */
11208 #define ALT_SDMMC_VERID_RESET 0x5342280a
11209 /* The byte offset of the ALT_SDMMC_VERID register from the beginning of the component. */
11210 #define ALT_SDMMC_VERID_OFST 0x6c
11211 /* The address of the ALT_SDMMC_VERID register. */
11212 #define ALT_SDMMC_VERID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_VERID_OFST))
11213 
11214 /*
11215  * Register : Hardware Configuration Register - HCON
11216  *
11217  * Name: Hardware Configuration Register
11218  *
11219  * Size: 32 bits
11220  *
11221  * Address Offset: 0x70
11222  *
11223  * Read/Write access: readHardware Configuration Register
11224  *
11225  * Register Layout
11226  *
11227  * Bits | Access | Reset | Description
11228  * :--------|:-------|:------|:---------------------------------
11229  * [0] | R | 0x1 | ALT_SDMMC_HCON_CARD_TYPE
11230  * [5:1] | R | 0x0 | ALT_SDMMC_HCON_NUM_CARD
11231  * [6] | R | 0x0 | ALT_SDMMC_HCON_BUS_TYPE
11232  * [9:7] | R | 0x1 | ALT_SDMMC_HCON_H_DATA_WIDTH
11233  * [15:10] | R | 0xc | ALT_SDMMC_HCON_H_ADDR_WIDTH
11234  * [17:16] | R | 0x0 | ALT_SDMMC_HCON_DMA_IF
11235  * [20:18] | R | 0x1 | ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH
11236  * [21] | R | 0x0 | ALT_SDMMC_HCON_FIFO_RAM_IN
11237  * [22] | R | 0x1 | ALT_SDMMC_HCON_HOLD_REG
11238  * [23] | R | 0x1 | ALT_SDMMC_HCON_FALSE_PATH
11239  * [25:24] | R | 0x0 | ALT_SDMMC_HCON_NUM_CLK_DIC
11240  * [26] | R | 0x0 | ALT_SDMMC_HCON_AREA_OPT
11241  * [27] | R | 0x0 | ALT_SDMMC_HCON_ADDR_CONFIG
11242  * [31:28] | ??? | 0x0 | *UNDEFINED*
11243  *
11244  */
11245 /*
11246  * Field : CARD_TYPE
11247  *
11248  * Card type
11249  *
11250  * Field Enumeration Values:
11251  *
11252  * Enum | Value | Description
11253  * :------------------------------------|:------|:------------
11254  * ALT_SDMMC_HCON_CARD_TYPE_E_MMC_ONLY | 0x0 | MMC Only
11255  * ALT_SDMMC_HCON_CARD_TYPE_E_SDMMC | 0x1 | SD MMC
11256  *
11257  * Field Access Macros:
11258  *
11259  */
11260 /*
11261  * Enumerated value for register field ALT_SDMMC_HCON_CARD_TYPE
11262  *
11263  * MMC Only
11264  */
11265 #define ALT_SDMMC_HCON_CARD_TYPE_E_MMC_ONLY 0x0
11266 /*
11267  * Enumerated value for register field ALT_SDMMC_HCON_CARD_TYPE
11268  *
11269  * SD MMC
11270  */
11271 #define ALT_SDMMC_HCON_CARD_TYPE_E_SDMMC 0x1
11272 
11273 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_CARD_TYPE register field. */
11274 #define ALT_SDMMC_HCON_CARD_TYPE_LSB 0
11275 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_CARD_TYPE register field. */
11276 #define ALT_SDMMC_HCON_CARD_TYPE_MSB 0
11277 /* The width in bits of the ALT_SDMMC_HCON_CARD_TYPE register field. */
11278 #define ALT_SDMMC_HCON_CARD_TYPE_WIDTH 1
11279 /* The mask used to set the ALT_SDMMC_HCON_CARD_TYPE register field value. */
11280 #define ALT_SDMMC_HCON_CARD_TYPE_SET_MSK 0x00000001
11281 /* The mask used to clear the ALT_SDMMC_HCON_CARD_TYPE register field value. */
11282 #define ALT_SDMMC_HCON_CARD_TYPE_CLR_MSK 0xfffffffe
11283 /* The reset value of the ALT_SDMMC_HCON_CARD_TYPE register field. */
11284 #define ALT_SDMMC_HCON_CARD_TYPE_RESET 0x1
11285 /* Extracts the ALT_SDMMC_HCON_CARD_TYPE field value from a register. */
11286 #define ALT_SDMMC_HCON_CARD_TYPE_GET(value) (((value) & 0x00000001) >> 0)
11287 /* Produces a ALT_SDMMC_HCON_CARD_TYPE register field value suitable for setting the register. */
11288 #define ALT_SDMMC_HCON_CARD_TYPE_SET(value) (((value) << 0) & 0x00000001)
11289 
11290 /*
11291  * Field : NUM_CARD
11292  *
11293  * NUM_CARD - 1
11294  *
11295  * Field Access Macros:
11296  *
11297  */
11298 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NUM_CARD register field. */
11299 #define ALT_SDMMC_HCON_NUM_CARD_LSB 1
11300 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NUM_CARD register field. */
11301 #define ALT_SDMMC_HCON_NUM_CARD_MSB 5
11302 /* The width in bits of the ALT_SDMMC_HCON_NUM_CARD register field. */
11303 #define ALT_SDMMC_HCON_NUM_CARD_WIDTH 5
11304 /* The mask used to set the ALT_SDMMC_HCON_NUM_CARD register field value. */
11305 #define ALT_SDMMC_HCON_NUM_CARD_SET_MSK 0x0000003e
11306 /* The mask used to clear the ALT_SDMMC_HCON_NUM_CARD register field value. */
11307 #define ALT_SDMMC_HCON_NUM_CARD_CLR_MSK 0xffffffc1
11308 /* The reset value of the ALT_SDMMC_HCON_NUM_CARD register field. */
11309 #define ALT_SDMMC_HCON_NUM_CARD_RESET 0x0
11310 /* Extracts the ALT_SDMMC_HCON_NUM_CARD field value from a register. */
11311 #define ALT_SDMMC_HCON_NUM_CARD_GET(value) (((value) & 0x0000003e) >> 1)
11312 /* Produces a ALT_SDMMC_HCON_NUM_CARD register field value suitable for setting the register. */
11313 #define ALT_SDMMC_HCON_NUM_CARD_SET(value) (((value) << 1) & 0x0000003e)
11314 
11315 /*
11316  * Field : BUS_TYPE
11317  *
11318  * Bus type
11319  *
11320  * Field Enumeration Values:
11321  *
11322  * Enum | Value | Description
11323  * :------------------------------|:------|:------------
11324  * ALT_SDMMC_HCON_BUS_TYPE_E_APB | 0x0 | APB Bus
11325  * ALT_SDMMC_HCON_BUS_TYPE_E_AHB | 0x1 | AHB bus
11326  *
11327  * Field Access Macros:
11328  *
11329  */
11330 /*
11331  * Enumerated value for register field ALT_SDMMC_HCON_BUS_TYPE
11332  *
11333  * APB Bus
11334  */
11335 #define ALT_SDMMC_HCON_BUS_TYPE_E_APB 0x0
11336 /*
11337  * Enumerated value for register field ALT_SDMMC_HCON_BUS_TYPE
11338  *
11339  * AHB bus
11340  */
11341 #define ALT_SDMMC_HCON_BUS_TYPE_E_AHB 0x1
11342 
11343 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_BUS_TYPE register field. */
11344 #define ALT_SDMMC_HCON_BUS_TYPE_LSB 6
11345 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_BUS_TYPE register field. */
11346 #define ALT_SDMMC_HCON_BUS_TYPE_MSB 6
11347 /* The width in bits of the ALT_SDMMC_HCON_BUS_TYPE register field. */
11348 #define ALT_SDMMC_HCON_BUS_TYPE_WIDTH 1
11349 /* The mask used to set the ALT_SDMMC_HCON_BUS_TYPE register field value. */
11350 #define ALT_SDMMC_HCON_BUS_TYPE_SET_MSK 0x00000040
11351 /* The mask used to clear the ALT_SDMMC_HCON_BUS_TYPE register field value. */
11352 #define ALT_SDMMC_HCON_BUS_TYPE_CLR_MSK 0xffffffbf
11353 /* The reset value of the ALT_SDMMC_HCON_BUS_TYPE register field. */
11354 #define ALT_SDMMC_HCON_BUS_TYPE_RESET 0x0
11355 /* Extracts the ALT_SDMMC_HCON_BUS_TYPE field value from a register. */
11356 #define ALT_SDMMC_HCON_BUS_TYPE_GET(value) (((value) & 0x00000040) >> 6)
11357 /* Produces a ALT_SDMMC_HCON_BUS_TYPE register field value suitable for setting the register. */
11358 #define ALT_SDMMC_HCON_BUS_TYPE_SET(value) (((value) << 6) & 0x00000040)
11359 
11360 /*
11361  * Field : H_DATA_WIDTH
11362  *
11363  * H Data Width
11364  *
11365  * 000 - 16 bits
11366  *
11367  * 001 - 32 bits
11368  *
11369  * 010 - 64 bits
11370  *
11371  * others - reserved
11372  *
11373  * Field Access Macros:
11374  *
11375  */
11376 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_H_DATA_WIDTH register field. */
11377 #define ALT_SDMMC_HCON_H_DATA_WIDTH_LSB 7
11378 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_H_DATA_WIDTH register field. */
11379 #define ALT_SDMMC_HCON_H_DATA_WIDTH_MSB 9
11380 /* The width in bits of the ALT_SDMMC_HCON_H_DATA_WIDTH register field. */
11381 #define ALT_SDMMC_HCON_H_DATA_WIDTH_WIDTH 3
11382 /* The mask used to set the ALT_SDMMC_HCON_H_DATA_WIDTH register field value. */
11383 #define ALT_SDMMC_HCON_H_DATA_WIDTH_SET_MSK 0x00000380
11384 /* The mask used to clear the ALT_SDMMC_HCON_H_DATA_WIDTH register field value. */
11385 #define ALT_SDMMC_HCON_H_DATA_WIDTH_CLR_MSK 0xfffffc7f
11386 /* The reset value of the ALT_SDMMC_HCON_H_DATA_WIDTH register field. */
11387 #define ALT_SDMMC_HCON_H_DATA_WIDTH_RESET 0x1
11388 /* Extracts the ALT_SDMMC_HCON_H_DATA_WIDTH field value from a register. */
11389 #define ALT_SDMMC_HCON_H_DATA_WIDTH_GET(value) (((value) & 0x00000380) >> 7)
11390 /* Produces a ALT_SDMMC_HCON_H_DATA_WIDTH register field value suitable for setting the register. */
11391 #define ALT_SDMMC_HCON_H_DATA_WIDTH_SET(value) (((value) << 7) & 0x00000380)
11392 
11393 /*
11394  * Field : H_ADDR_WIDTH
11395  *
11396  * H Address Width
11397  *
11398  * 00 to 7 reserved
11399  *
11400  * 8 9 bits
11401  *
11402  * 9 10 bits
11403  *
11404  * ...
11405  *
11406  * 31 32 bits
11407  *
11408  * 32 to 63 reserved
11409  *
11410  * Field Access Macros:
11411  *
11412  */
11413 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_H_ADDR_WIDTH register field. */
11414 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_LSB 10
11415 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_H_ADDR_WIDTH register field. */
11416 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_MSB 15
11417 /* The width in bits of the ALT_SDMMC_HCON_H_ADDR_WIDTH register field. */
11418 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_WIDTH 6
11419 /* The mask used to set the ALT_SDMMC_HCON_H_ADDR_WIDTH register field value. */
11420 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_SET_MSK 0x0000fc00
11421 /* The mask used to clear the ALT_SDMMC_HCON_H_ADDR_WIDTH register field value. */
11422 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_CLR_MSK 0xffff03ff
11423 /* The reset value of the ALT_SDMMC_HCON_H_ADDR_WIDTH register field. */
11424 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_RESET 0xc
11425 /* Extracts the ALT_SDMMC_HCON_H_ADDR_WIDTH field value from a register. */
11426 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
11427 /* Produces a ALT_SDMMC_HCON_H_ADDR_WIDTH register field value suitable for setting the register. */
11428 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_SET(value) (((value) << 10) & 0x0000fc00)
11429 
11430 /*
11431  * Field : DMA_IF
11432  *
11433  * DMA Interface
11434  *
11435  * Field Enumeration Values:
11436  *
11437  * Enum | Value | Description
11438  * :--------------------------------|:------|:------------
11439  * ALT_SDMMC_HCON_DMA_IF_E_NONE | 0x0 | None
11440  * ALT_SDMMC_HCON_DMA_IF_E_DW_DMA | 0x1 | DW DMA
11441  * ALT_SDMMC_HCON_DMA_IF_E_GEN_DMA | 0x2 | Generic DMA
11442  * ALT_SDMMC_HCON_DMA_IF_E_NDW_DMA | 0x3 | Non DW DMA
11443  *
11444  * Field Access Macros:
11445  *
11446  */
11447 /*
11448  * Enumerated value for register field ALT_SDMMC_HCON_DMA_IF
11449  *
11450  * None
11451  */
11452 #define ALT_SDMMC_HCON_DMA_IF_E_NONE 0x0
11453 /*
11454  * Enumerated value for register field ALT_SDMMC_HCON_DMA_IF
11455  *
11456  * DW DMA
11457  */
11458 #define ALT_SDMMC_HCON_DMA_IF_E_DW_DMA 0x1
11459 /*
11460  * Enumerated value for register field ALT_SDMMC_HCON_DMA_IF
11461  *
11462  * Generic DMA
11463  */
11464 #define ALT_SDMMC_HCON_DMA_IF_E_GEN_DMA 0x2
11465 /*
11466  * Enumerated value for register field ALT_SDMMC_HCON_DMA_IF
11467  *
11468  * Non DW DMA
11469  */
11470 #define ALT_SDMMC_HCON_DMA_IF_E_NDW_DMA 0x3
11471 
11472 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMA_IF register field. */
11473 #define ALT_SDMMC_HCON_DMA_IF_LSB 16
11474 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMA_IF register field. */
11475 #define ALT_SDMMC_HCON_DMA_IF_MSB 17
11476 /* The width in bits of the ALT_SDMMC_HCON_DMA_IF register field. */
11477 #define ALT_SDMMC_HCON_DMA_IF_WIDTH 2
11478 /* The mask used to set the ALT_SDMMC_HCON_DMA_IF register field value. */
11479 #define ALT_SDMMC_HCON_DMA_IF_SET_MSK 0x00030000
11480 /* The mask used to clear the ALT_SDMMC_HCON_DMA_IF register field value. */
11481 #define ALT_SDMMC_HCON_DMA_IF_CLR_MSK 0xfffcffff
11482 /* The reset value of the ALT_SDMMC_HCON_DMA_IF register field. */
11483 #define ALT_SDMMC_HCON_DMA_IF_RESET 0x0
11484 /* Extracts the ALT_SDMMC_HCON_DMA_IF field value from a register. */
11485 #define ALT_SDMMC_HCON_DMA_IF_GET(value) (((value) & 0x00030000) >> 16)
11486 /* Produces a ALT_SDMMC_HCON_DMA_IF register field value suitable for setting the register. */
11487 #define ALT_SDMMC_HCON_DMA_IF_SET(value) (((value) << 16) & 0x00030000)
11488 
11489 /*
11490  * Field : GE_DMA_DATA_WIDTH
11491  *
11492  * Generic DMA Data Width
11493  *
11494  * 000 - 16 bits
11495  *
11496  * 001 - 32 bits
11497  *
11498  * 010 - 64 bits
11499  *
11500  * others - reserved
11501  *
11502  * Field Access Macros:
11503  *
11504  */
11505 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field. */
11506 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_LSB 18
11507 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field. */
11508 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_MSB 20
11509 /* The width in bits of the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field. */
11510 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_WIDTH 3
11511 /* The mask used to set the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field value. */
11512 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_SET_MSK 0x001c0000
11513 /* The mask used to clear the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field value. */
11514 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_CLR_MSK 0xffe3ffff
11515 /* The reset value of the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field. */
11516 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_RESET 0x1
11517 /* Extracts the ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH field value from a register. */
11518 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_GET(value) (((value) & 0x001c0000) >> 18)
11519 /* Produces a ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH register field value suitable for setting the register. */
11520 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_SET(value) (((value) << 18) & 0x001c0000)
11521 
11522 /*
11523  * Field : FIFO_RAM_IN
11524  *
11525  * FIFO Ram Inside
11526  *
11527  * Field Enumeration Values:
11528  *
11529  * Enum | Value | Description
11530  * :---------------------------------|:------|:------------
11531  * ALT_SDMMC_HCON_FIFO_RAM_IN_E_NO | 0x0 | Outside
11532  * ALT_SDMMC_HCON_FIFO_RAM_IN_E_YES | 0x1 | Inside
11533  *
11534  * Field Access Macros:
11535  *
11536  */
11537 /*
11538  * Enumerated value for register field ALT_SDMMC_HCON_FIFO_RAM_IN
11539  *
11540  * Outside
11541  */
11542 #define ALT_SDMMC_HCON_FIFO_RAM_IN_E_NO 0x0
11543 /*
11544  * Enumerated value for register field ALT_SDMMC_HCON_FIFO_RAM_IN
11545  *
11546  * Inside
11547  */
11548 #define ALT_SDMMC_HCON_FIFO_RAM_IN_E_YES 0x1
11549 
11550 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_FIFO_RAM_IN register field. */
11551 #define ALT_SDMMC_HCON_FIFO_RAM_IN_LSB 21
11552 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_FIFO_RAM_IN register field. */
11553 #define ALT_SDMMC_HCON_FIFO_RAM_IN_MSB 21
11554 /* The width in bits of the ALT_SDMMC_HCON_FIFO_RAM_IN register field. */
11555 #define ALT_SDMMC_HCON_FIFO_RAM_IN_WIDTH 1
11556 /* The mask used to set the ALT_SDMMC_HCON_FIFO_RAM_IN register field value. */
11557 #define ALT_SDMMC_HCON_FIFO_RAM_IN_SET_MSK 0x00200000
11558 /* The mask used to clear the ALT_SDMMC_HCON_FIFO_RAM_IN register field value. */
11559 #define ALT_SDMMC_HCON_FIFO_RAM_IN_CLR_MSK 0xffdfffff
11560 /* The reset value of the ALT_SDMMC_HCON_FIFO_RAM_IN register field. */
11561 #define ALT_SDMMC_HCON_FIFO_RAM_IN_RESET 0x0
11562 /* Extracts the ALT_SDMMC_HCON_FIFO_RAM_IN field value from a register. */
11563 #define ALT_SDMMC_HCON_FIFO_RAM_IN_GET(value) (((value) & 0x00200000) >> 21)
11564 /* Produces a ALT_SDMMC_HCON_FIFO_RAM_IN register field value suitable for setting the register. */
11565 #define ALT_SDMMC_HCON_FIFO_RAM_IN_SET(value) (((value) << 21) & 0x00200000)
11566 
11567 /*
11568  * Field : HOLD_REG
11569  *
11570  * Implement HOLD register
11571  *
11572  * Field Enumeration Values:
11573  *
11574  * Enum | Value | Description
11575  * :------------------------------|:------|:-----------------
11576  * ALT_SDMMC_HCON_HOLD_REG_E_NO | 0x0 | no hold register
11577  * ALT_SDMMC_HCON_HOLD_REG_E_YES | 0x1 | hold register
11578  *
11579  * Field Access Macros:
11580  *
11581  */
11582 /*
11583  * Enumerated value for register field ALT_SDMMC_HCON_HOLD_REG
11584  *
11585  * no hold register
11586  */
11587 #define ALT_SDMMC_HCON_HOLD_REG_E_NO 0x0
11588 /*
11589  * Enumerated value for register field ALT_SDMMC_HCON_HOLD_REG
11590  *
11591  * hold register
11592  */
11593 #define ALT_SDMMC_HCON_HOLD_REG_E_YES 0x1
11594 
11595 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HOLD_REG register field. */
11596 #define ALT_SDMMC_HCON_HOLD_REG_LSB 22
11597 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HOLD_REG register field. */
11598 #define ALT_SDMMC_HCON_HOLD_REG_MSB 22
11599 /* The width in bits of the ALT_SDMMC_HCON_HOLD_REG register field. */
11600 #define ALT_SDMMC_HCON_HOLD_REG_WIDTH 1
11601 /* The mask used to set the ALT_SDMMC_HCON_HOLD_REG register field value. */
11602 #define ALT_SDMMC_HCON_HOLD_REG_SET_MSK 0x00400000
11603 /* The mask used to clear the ALT_SDMMC_HCON_HOLD_REG register field value. */
11604 #define ALT_SDMMC_HCON_HOLD_REG_CLR_MSK 0xffbfffff
11605 /* The reset value of the ALT_SDMMC_HCON_HOLD_REG register field. */
11606 #define ALT_SDMMC_HCON_HOLD_REG_RESET 0x1
11607 /* Extracts the ALT_SDMMC_HCON_HOLD_REG field value from a register. */
11608 #define ALT_SDMMC_HCON_HOLD_REG_GET(value) (((value) & 0x00400000) >> 22)
11609 /* Produces a ALT_SDMMC_HCON_HOLD_REG register field value suitable for setting the register. */
11610 #define ALT_SDMMC_HCON_HOLD_REG_SET(value) (((value) << 22) & 0x00400000)
11611 
11612 /*
11613  * Field : FALSE_PATH
11614  *
11615  * Set Clock False Path
11616  *
11617  * Field Enumeration Values:
11618  *
11619  * Enum | Value | Description
11620  * :--------------------------------|:------|:---------------
11621  * ALT_SDMMC_HCON_FALSE_PATH_E_NO | 0x0 | no false path
11622  * ALT_SDMMC_HCON_FALSE_PATH_E_YES | 0x1 | false path set
11623  *
11624  * Field Access Macros:
11625  *
11626  */
11627 /*
11628  * Enumerated value for register field ALT_SDMMC_HCON_FALSE_PATH
11629  *
11630  * no false path
11631  */
11632 #define ALT_SDMMC_HCON_FALSE_PATH_E_NO 0x0
11633 /*
11634  * Enumerated value for register field ALT_SDMMC_HCON_FALSE_PATH
11635  *
11636  * false path set
11637  */
11638 #define ALT_SDMMC_HCON_FALSE_PATH_E_YES 0x1
11639 
11640 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_FALSE_PATH register field. */
11641 #define ALT_SDMMC_HCON_FALSE_PATH_LSB 23
11642 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_FALSE_PATH register field. */
11643 #define ALT_SDMMC_HCON_FALSE_PATH_MSB 23
11644 /* The width in bits of the ALT_SDMMC_HCON_FALSE_PATH register field. */
11645 #define ALT_SDMMC_HCON_FALSE_PATH_WIDTH 1
11646 /* The mask used to set the ALT_SDMMC_HCON_FALSE_PATH register field value. */
11647 #define ALT_SDMMC_HCON_FALSE_PATH_SET_MSK 0x00800000
11648 /* The mask used to clear the ALT_SDMMC_HCON_FALSE_PATH register field value. */
11649 #define ALT_SDMMC_HCON_FALSE_PATH_CLR_MSK 0xff7fffff
11650 /* The reset value of the ALT_SDMMC_HCON_FALSE_PATH register field. */
11651 #define ALT_SDMMC_HCON_FALSE_PATH_RESET 0x1
11652 /* Extracts the ALT_SDMMC_HCON_FALSE_PATH field value from a register. */
11653 #define ALT_SDMMC_HCON_FALSE_PATH_GET(value) (((value) & 0x00800000) >> 23)
11654 /* Produces a ALT_SDMMC_HCON_FALSE_PATH register field value suitable for setting the register. */
11655 #define ALT_SDMMC_HCON_FALSE_PATH_SET(value) (((value) << 23) & 0x00800000)
11656 
11657 /*
11658  * Field : NUM_CLK_DIC
11659  *
11660  * NUM_CLK_DIVIDER - 1
11661  *
11662  * Field Access Macros:
11663  *
11664  */
11665 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NUM_CLK_DIC register field. */
11666 #define ALT_SDMMC_HCON_NUM_CLK_DIC_LSB 24
11667 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NUM_CLK_DIC register field. */
11668 #define ALT_SDMMC_HCON_NUM_CLK_DIC_MSB 25
11669 /* The width in bits of the ALT_SDMMC_HCON_NUM_CLK_DIC register field. */
11670 #define ALT_SDMMC_HCON_NUM_CLK_DIC_WIDTH 2
11671 /* The mask used to set the ALT_SDMMC_HCON_NUM_CLK_DIC register field value. */
11672 #define ALT_SDMMC_HCON_NUM_CLK_DIC_SET_MSK 0x03000000
11673 /* The mask used to clear the ALT_SDMMC_HCON_NUM_CLK_DIC register field value. */
11674 #define ALT_SDMMC_HCON_NUM_CLK_DIC_CLR_MSK 0xfcffffff
11675 /* The reset value of the ALT_SDMMC_HCON_NUM_CLK_DIC register field. */
11676 #define ALT_SDMMC_HCON_NUM_CLK_DIC_RESET 0x0
11677 /* Extracts the ALT_SDMMC_HCON_NUM_CLK_DIC field value from a register. */
11678 #define ALT_SDMMC_HCON_NUM_CLK_DIC_GET(value) (((value) & 0x03000000) >> 24)
11679 /* Produces a ALT_SDMMC_HCON_NUM_CLK_DIC register field value suitable for setting the register. */
11680 #define ALT_SDMMC_HCON_NUM_CLK_DIC_SET(value) (((value) << 24) & 0x03000000)
11681 
11682 /*
11683  * Field : AREA_OPT
11684  *
11685  * Area Optimization
11686  *
11687  * Field Enumeration Values:
11688  *
11689  * Enum | Value | Description
11690  * :------------------------------|:------|:---------------------
11691  * ALT_SDMMC_HCON_AREA_OPT_E_NO | 0x0 | no area optimization
11692  * ALT_SDMMC_HCON_AREA_OPT_E_YES | 0x1 | Area optimization
11693  *
11694  * Field Access Macros:
11695  *
11696  */
11697 /*
11698  * Enumerated value for register field ALT_SDMMC_HCON_AREA_OPT
11699  *
11700  * no area optimization
11701  */
11702 #define ALT_SDMMC_HCON_AREA_OPT_E_NO 0x0
11703 /*
11704  * Enumerated value for register field ALT_SDMMC_HCON_AREA_OPT
11705  *
11706  * Area optimization
11707  */
11708 #define ALT_SDMMC_HCON_AREA_OPT_E_YES 0x1
11709 
11710 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_AREA_OPT register field. */
11711 #define ALT_SDMMC_HCON_AREA_OPT_LSB 26
11712 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_AREA_OPT register field. */
11713 #define ALT_SDMMC_HCON_AREA_OPT_MSB 26
11714 /* The width in bits of the ALT_SDMMC_HCON_AREA_OPT register field. */
11715 #define ALT_SDMMC_HCON_AREA_OPT_WIDTH 1
11716 /* The mask used to set the ALT_SDMMC_HCON_AREA_OPT register field value. */
11717 #define ALT_SDMMC_HCON_AREA_OPT_SET_MSK 0x04000000
11718 /* The mask used to clear the ALT_SDMMC_HCON_AREA_OPT register field value. */
11719 #define ALT_SDMMC_HCON_AREA_OPT_CLR_MSK 0xfbffffff
11720 /* The reset value of the ALT_SDMMC_HCON_AREA_OPT register field. */
11721 #define ALT_SDMMC_HCON_AREA_OPT_RESET 0x0
11722 /* Extracts the ALT_SDMMC_HCON_AREA_OPT field value from a register. */
11723 #define ALT_SDMMC_HCON_AREA_OPT_GET(value) (((value) & 0x04000000) >> 26)
11724 /* Produces a ALT_SDMMC_HCON_AREA_OPT register field value suitable for setting the register. */
11725 #define ALT_SDMMC_HCON_AREA_OPT_SET(value) (((value) << 26) & 0x04000000)
11726 
11727 /*
11728  * Field : ADDR_CONFIG
11729  *
11730  * Address configuration
11731  *
11732  * Field Enumeration Values:
11733  *
11734  * Enum | Value | Description
11735  * :------------------------------------|:------|:----------------------------
11736  * ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR32 | 0x0 | 32-bit addressing supported
11737  * ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR64 | 0x1 | 64-bit addressing supported
11738  *
11739  * Field Access Macros:
11740  *
11741  */
11742 /*
11743  * Enumerated value for register field ALT_SDMMC_HCON_ADDR_CONFIG
11744  *
11745  * 32-bit addressing supported
11746  */
11747 #define ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR32 0x0
11748 /*
11749  * Enumerated value for register field ALT_SDMMC_HCON_ADDR_CONFIG
11750  *
11751  * 64-bit addressing supported
11752  */
11753 #define ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR64 0x1
11754 
11755 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_ADDR_CONFIG register field. */
11756 #define ALT_SDMMC_HCON_ADDR_CONFIG_LSB 27
11757 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_ADDR_CONFIG register field. */
11758 #define ALT_SDMMC_HCON_ADDR_CONFIG_MSB 27
11759 /* The width in bits of the ALT_SDMMC_HCON_ADDR_CONFIG register field. */
11760 #define ALT_SDMMC_HCON_ADDR_CONFIG_WIDTH 1
11761 /* The mask used to set the ALT_SDMMC_HCON_ADDR_CONFIG register field value. */
11762 #define ALT_SDMMC_HCON_ADDR_CONFIG_SET_MSK 0x08000000
11763 /* The mask used to clear the ALT_SDMMC_HCON_ADDR_CONFIG register field value. */
11764 #define ALT_SDMMC_HCON_ADDR_CONFIG_CLR_MSK 0xf7ffffff
11765 /* The reset value of the ALT_SDMMC_HCON_ADDR_CONFIG register field. */
11766 #define ALT_SDMMC_HCON_ADDR_CONFIG_RESET 0x0
11767 /* Extracts the ALT_SDMMC_HCON_ADDR_CONFIG field value from a register. */
11768 #define ALT_SDMMC_HCON_ADDR_CONFIG_GET(value) (((value) & 0x08000000) >> 27)
11769 /* Produces a ALT_SDMMC_HCON_ADDR_CONFIG register field value suitable for setting the register. */
11770 #define ALT_SDMMC_HCON_ADDR_CONFIG_SET(value) (((value) << 27) & 0x08000000)
11771 
11772 #ifndef __ASSEMBLY__
11773 /*
11774  * WARNING: The C register and register group struct declarations are provided for
11775  * convenience and illustrative purposes. They should, however, be used with
11776  * caution as the C language standard provides no guarantees about the alignment or
11777  * atomicity of device memory accesses. The recommended practice for coding device
11778  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11779  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11780  * alt_write_dword() functions for 64 bit registers.
11781  *
11782  * The struct declaration for register ALT_SDMMC_HCON.
11783  */
11784 struct ALT_SDMMC_HCON_s
11785 {
11786  const volatile uint32_t CARD_TYPE : 1; /* ALT_SDMMC_HCON_CARD_TYPE */
11787  const volatile uint32_t NUM_CARD : 5; /* ALT_SDMMC_HCON_NUM_CARD */
11788  const volatile uint32_t BUS_TYPE : 1; /* ALT_SDMMC_HCON_BUS_TYPE */
11789  const volatile uint32_t H_DATA_WIDTH : 3; /* ALT_SDMMC_HCON_H_DATA_WIDTH */
11790  const volatile uint32_t H_ADDR_WIDTH : 6; /* ALT_SDMMC_HCON_H_ADDR_WIDTH */
11791  const volatile uint32_t DMA_IF : 2; /* ALT_SDMMC_HCON_DMA_IF */
11792  const volatile uint32_t GE_DMA_DATA_WIDTH : 3; /* ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH */
11793  const volatile uint32_t FIFO_RAM_IN : 1; /* ALT_SDMMC_HCON_FIFO_RAM_IN */
11794  const volatile uint32_t HOLD_REG : 1; /* ALT_SDMMC_HCON_HOLD_REG */
11795  const volatile uint32_t FALSE_PATH : 1; /* ALT_SDMMC_HCON_FALSE_PATH */
11796  const volatile uint32_t NUM_CLK_DIC : 2; /* ALT_SDMMC_HCON_NUM_CLK_DIC */
11797  const volatile uint32_t AREA_OPT : 1; /* ALT_SDMMC_HCON_AREA_OPT */
11798  const volatile uint32_t ADDR_CONFIG : 1; /* ALT_SDMMC_HCON_ADDR_CONFIG */
11799  uint32_t : 4; /* *UNDEFINED* */
11800 };
11801 
11802 /* The typedef declaration for register ALT_SDMMC_HCON. */
11803 typedef struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
11804 #endif /* __ASSEMBLY__ */
11805 
11806 /* The reset value of the ALT_SDMMC_HCON register. */
11807 #define ALT_SDMMC_HCON_RESET 0x00c43081
11808 /* The byte offset of the ALT_SDMMC_HCON register from the beginning of the component. */
11809 #define ALT_SDMMC_HCON_OFST 0x70
11810 /* The address of the ALT_SDMMC_HCON register. */
11811 #define ALT_SDMMC_HCON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_HCON_OFST))
11812 
11813 /*
11814  * Register : UHS-1 Register - UHS_REG
11815  *
11816  * Name: UHS-1 Register
11817  *
11818  * Size: 32 bits
11819  *
11820  * Address Offset: 0x74
11821  *
11822  * Read/write access: write/read
11823  *
11824  * Register Layout
11825  *
11826  * Bits | Access | Reset | Description
11827  * :-----|:-------|:------|:------------------------------
11828  * [0] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_0
11829  * [1] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_1
11830  * [2] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_2
11831  * [3] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_3
11832  * [4] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_4
11833  * [5] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_5
11834  * [6] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_6
11835  * [7] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_7
11836  * [8] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_8
11837  * [9] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_9
11838  * [10] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_10
11839  * [11] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_11
11840  * [12] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_12
11841  * [13] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_13
11842  * [14] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_14
11843  * [15] | RW | 0x0 | ALT_SDMMC_UHS_REG_VOLT_REG_15
11844  * [16] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_0
11845  * [17] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_1
11846  * [18] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_2
11847  * [19] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_3
11848  * [20] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_4
11849  * [21] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_5
11850  * [22] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_6
11851  * [23] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_7
11852  * [24] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_8
11853  * [25] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_9
11854  * [26] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_10
11855  * [27] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_11
11856  * [28] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_12
11857  * [29] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_13
11858  * [30] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_14
11859  * [31] | RW | 0x0 | ALT_SDMMC_UHS_REG_DDR_REG_15
11860  *
11861  */
11862 /*
11863  * Field : VOLT_REG_0
11864  *
11865  * High Voltage mode. Determines the voltage fed to the buffers by an
11866  *
11867  * external voltage regulator.
11868  *
11869  * 0 Buffers supplied with 3.3V Vdd
11870  *
11871  * 1 Buffers supplied with 1.8V Vdd
11872  *
11873  * These bits function as the output of the host controller and are fed to an
11874  * external voltage regulator. The voltage regulator must switch the voltage of the
11875  * buffers of a particular card to either 3.3V or 1.8V, depending on the
11876  *
11877  * value programmed in the register.
11878  *
11879  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
11880  *
11881  * operate for 1.8V.
11882  *
11883  * Field Enumeration Values:
11884  *
11885  * Enum | Value | Description
11886  * :-------------------------------------|:------|:-------------------------------
11887  * ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
11888  * ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
11889  *
11890  * Field Access Macros:
11891  *
11892  */
11893 /*
11894  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_0
11895  *
11896  * Buffers supplied with 3.3V Vdd
11897  */
11898 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL33 0x0
11899 /*
11900  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_0
11901  *
11902  * Buffers supplied with 1.8V Vdd
11903  */
11904 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL18 0x1
11905 
11906 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field. */
11907 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_LSB 0
11908 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field. */
11909 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_MSB 0
11910 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field. */
11911 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_WIDTH 1
11912 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field value. */
11913 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_SET_MSK 0x00000001
11914 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field value. */
11915 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_CLR_MSK 0xfffffffe
11916 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_0 register field. */
11917 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_RESET 0x0
11918 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_0 field value from a register. */
11919 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_GET(value) (((value) & 0x00000001) >> 0)
11920 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_0 register field value suitable for setting the register. */
11921 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_SET(value) (((value) << 0) & 0x00000001)
11922 
11923 /*
11924  * Field : VOLT_REG_1
11925  *
11926  * High Voltage mode. Determines the voltage fed to the buffers by an
11927  *
11928  * external voltage regulator.
11929  *
11930  * 0 Buffers supplied with 3.3V Vdd
11931  *
11932  * 1 Buffers supplied with 1.8V Vdd
11933  *
11934  * These bits function as the output of the host controller and are fed to an
11935  * external voltage regulator. The voltage regulator must switch the voltage of the
11936  * buffers of a particular card to either 3.3V or 1.8V, depending on the
11937  *
11938  * value programmed in the register.
11939  *
11940  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
11941  *
11942  * operate for 1.8V.
11943  *
11944  * Field Enumeration Values:
11945  *
11946  * Enum | Value | Description
11947  * :-------------------------------------|:------|:-------------------------------
11948  * ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
11949  * ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
11950  *
11951  * Field Access Macros:
11952  *
11953  */
11954 /*
11955  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_1
11956  *
11957  * Buffers supplied with 3.3V Vdd
11958  */
11959 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL33 0x0
11960 /*
11961  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_1
11962  *
11963  * Buffers supplied with 1.8V Vdd
11964  */
11965 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL18 0x1
11966 
11967 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field. */
11968 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_LSB 1
11969 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field. */
11970 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_MSB 1
11971 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field. */
11972 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_WIDTH 1
11973 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field value. */
11974 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_SET_MSK 0x00000002
11975 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field value. */
11976 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_CLR_MSK 0xfffffffd
11977 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_1 register field. */
11978 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_RESET 0x0
11979 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_1 field value from a register. */
11980 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_GET(value) (((value) & 0x00000002) >> 1)
11981 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_1 register field value suitable for setting the register. */
11982 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_SET(value) (((value) << 1) & 0x00000002)
11983 
11984 /*
11985  * Field : VOLT_REG_2
11986  *
11987  * High Voltage mode. Determines the voltage fed to the buffers by an
11988  *
11989  * external voltage regulator.
11990  *
11991  * 0 Buffers supplied with 3.3V Vdd
11992  *
11993  * 1 Buffers supplied with 1.8V Vdd
11994  *
11995  * These bits function as the output of the host controller and are fed to an
11996  * external voltage regulator. The voltage regulator must switch the voltage of the
11997  * buffers of a particular card to either 3.3V or 1.8V, depending on the
11998  *
11999  * value programmed in the register.
12000  *
12001  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12002  *
12003  * operate for 1.8V.
12004  *
12005  * Field Enumeration Values:
12006  *
12007  * Enum | Value | Description
12008  * :-------------------------------------|:------|:-------------------------------
12009  * ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12010  * ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12011  *
12012  * Field Access Macros:
12013  *
12014  */
12015 /*
12016  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_2
12017  *
12018  * Buffers supplied with 3.3V Vdd
12019  */
12020 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL33 0x0
12021 /*
12022  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_2
12023  *
12024  * Buffers supplied with 1.8V Vdd
12025  */
12026 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL18 0x1
12027 
12028 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field. */
12029 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_LSB 2
12030 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field. */
12031 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_MSB 2
12032 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field. */
12033 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_WIDTH 1
12034 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field value. */
12035 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_SET_MSK 0x00000004
12036 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field value. */
12037 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_CLR_MSK 0xfffffffb
12038 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_2 register field. */
12039 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_RESET 0x0
12040 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_2 field value from a register. */
12041 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_GET(value) (((value) & 0x00000004) >> 2)
12042 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_2 register field value suitable for setting the register. */
12043 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_SET(value) (((value) << 2) & 0x00000004)
12044 
12045 /*
12046  * Field : VOLT_REG_3
12047  *
12048  * High Voltage mode. Determines the voltage fed to the buffers by an
12049  *
12050  * external voltage regulator.
12051  *
12052  * 0 Buffers supplied with 3.3V Vdd
12053  *
12054  * 1 Buffers supplied with 1.8V Vdd
12055  *
12056  * These bits function as the output of the host controller and are fed to an
12057  * external voltage regulator. The voltage regulator must switch the voltage of the
12058  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12059  *
12060  * value programmed in the register.
12061  *
12062  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12063  *
12064  * operate for 1.8V.
12065  *
12066  * Field Enumeration Values:
12067  *
12068  * Enum | Value | Description
12069  * :-------------------------------------|:------|:-------------------------------
12070  * ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12071  * ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12072  *
12073  * Field Access Macros:
12074  *
12075  */
12076 /*
12077  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_3
12078  *
12079  * Buffers supplied with 3.3V Vdd
12080  */
12081 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL33 0x0
12082 /*
12083  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_3
12084  *
12085  * Buffers supplied with 1.8V Vdd
12086  */
12087 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL18 0x1
12088 
12089 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field. */
12090 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_LSB 3
12091 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field. */
12092 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_MSB 3
12093 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field. */
12094 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_WIDTH 1
12095 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field value. */
12096 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_SET_MSK 0x00000008
12097 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field value. */
12098 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_CLR_MSK 0xfffffff7
12099 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_3 register field. */
12100 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_RESET 0x0
12101 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_3 field value from a register. */
12102 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_GET(value) (((value) & 0x00000008) >> 3)
12103 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_3 register field value suitable for setting the register. */
12104 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_SET(value) (((value) << 3) & 0x00000008)
12105 
12106 /*
12107  * Field : VOLT_REG_4
12108  *
12109  * High Voltage mode. Determines the voltage fed to the buffers by an
12110  *
12111  * external voltage regulator.
12112  *
12113  * 0 Buffers supplied with 3.3V Vdd
12114  *
12115  * 1 Buffers supplied with 1.8V Vdd
12116  *
12117  * These bits function as the output of the host controller and are fed to an
12118  * external voltage regulator. The voltage regulator must switch the voltage of the
12119  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12120  *
12121  * value programmed in the register.
12122  *
12123  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12124  *
12125  * operate for 1.8V.
12126  *
12127  * Field Enumeration Values:
12128  *
12129  * Enum | Value | Description
12130  * :-------------------------------------|:------|:-------------------------------
12131  * ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12132  * ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12133  *
12134  * Field Access Macros:
12135  *
12136  */
12137 /*
12138  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_4
12139  *
12140  * Buffers supplied with 3.3V Vdd
12141  */
12142 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL33 0x0
12143 /*
12144  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_4
12145  *
12146  * Buffers supplied with 1.8V Vdd
12147  */
12148 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL18 0x1
12149 
12150 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field. */
12151 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_LSB 4
12152 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field. */
12153 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_MSB 4
12154 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field. */
12155 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_WIDTH 1
12156 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field value. */
12157 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_SET_MSK 0x00000010
12158 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field value. */
12159 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_CLR_MSK 0xffffffef
12160 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_4 register field. */
12161 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_RESET 0x0
12162 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_4 field value from a register. */
12163 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_GET(value) (((value) & 0x00000010) >> 4)
12164 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_4 register field value suitable for setting the register. */
12165 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_SET(value) (((value) << 4) & 0x00000010)
12166 
12167 /*
12168  * Field : VOLT_REG_5
12169  *
12170  * High Voltage mode. Determines the voltage fed to the buffers by an
12171  *
12172  * external voltage regulator.
12173  *
12174  * 0 Buffers supplied with 3.3V Vdd
12175  *
12176  * 1 Buffers supplied with 1.8V Vdd
12177  *
12178  * These bits function as the output of the host controller and are fed to an
12179  * external voltage regulator. The voltage regulator must switch the voltage of the
12180  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12181  *
12182  * value programmed in the register.
12183  *
12184  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12185  *
12186  * operate for 1.8V.
12187  *
12188  * Field Enumeration Values:
12189  *
12190  * Enum | Value | Description
12191  * :-------------------------------------|:------|:-------------------------------
12192  * ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12193  * ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12194  *
12195  * Field Access Macros:
12196  *
12197  */
12198 /*
12199  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_5
12200  *
12201  * Buffers supplied with 3.3V Vdd
12202  */
12203 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL33 0x0
12204 /*
12205  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_5
12206  *
12207  * Buffers supplied with 1.8V Vdd
12208  */
12209 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL18 0x1
12210 
12211 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field. */
12212 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_LSB 5
12213 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field. */
12214 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_MSB 5
12215 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field. */
12216 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_WIDTH 1
12217 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field value. */
12218 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_SET_MSK 0x00000020
12219 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field value. */
12220 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_CLR_MSK 0xffffffdf
12221 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_5 register field. */
12222 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_RESET 0x0
12223 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_5 field value from a register. */
12224 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_GET(value) (((value) & 0x00000020) >> 5)
12225 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_5 register field value suitable for setting the register. */
12226 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_SET(value) (((value) << 5) & 0x00000020)
12227 
12228 /*
12229  * Field : VOLT_REG_6
12230  *
12231  * High Voltage mode. Determines the voltage fed to the buffers by an
12232  *
12233  * external voltage regulator.
12234  *
12235  * 0 Buffers supplied with 3.3V Vdd
12236  *
12237  * 1 Buffers supplied with 1.8V Vdd
12238  *
12239  * These bits function as the output of the host controller and are fed to an
12240  * external voltage regulator. The voltage regulator must switch the voltage of the
12241  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12242  *
12243  * value programmed in the register.
12244  *
12245  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12246  *
12247  * operate for 1.8V.
12248  *
12249  * Field Enumeration Values:
12250  *
12251  * Enum | Value | Description
12252  * :-------------------------------------|:------|:-------------------------------
12253  * ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12254  * ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12255  *
12256  * Field Access Macros:
12257  *
12258  */
12259 /*
12260  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_6
12261  *
12262  * Buffers supplied with 3.3V Vdd
12263  */
12264 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL33 0x0
12265 /*
12266  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_6
12267  *
12268  * Buffers supplied with 1.8V Vdd
12269  */
12270 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL18 0x1
12271 
12272 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field. */
12273 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_LSB 6
12274 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field. */
12275 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_MSB 6
12276 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field. */
12277 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_WIDTH 1
12278 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field value. */
12279 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_SET_MSK 0x00000040
12280 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field value. */
12281 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_CLR_MSK 0xffffffbf
12282 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_6 register field. */
12283 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_RESET 0x0
12284 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_6 field value from a register. */
12285 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_GET(value) (((value) & 0x00000040) >> 6)
12286 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_6 register field value suitable for setting the register. */
12287 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_SET(value) (((value) << 6) & 0x00000040)
12288 
12289 /*
12290  * Field : VOLT_REG_7
12291  *
12292  * High Voltage mode. Determines the voltage fed to the buffers by an
12293  *
12294  * external voltage regulator.
12295  *
12296  * 0 Buffers supplied with 3.3V Vdd
12297  *
12298  * 1 Buffers supplied with 1.8V Vdd
12299  *
12300  * These bits function as the output of the host controller and are fed to an
12301  * external voltage regulator. The voltage regulator must switch the voltage of the
12302  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12303  *
12304  * value programmed in the register.
12305  *
12306  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12307  *
12308  * operate for 1.8V.
12309  *
12310  * Field Enumeration Values:
12311  *
12312  * Enum | Value | Description
12313  * :-------------------------------------|:------|:-------------------------------
12314  * ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12315  * ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12316  *
12317  * Field Access Macros:
12318  *
12319  */
12320 /*
12321  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_7
12322  *
12323  * Buffers supplied with 3.3V Vdd
12324  */
12325 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL33 0x0
12326 /*
12327  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_7
12328  *
12329  * Buffers supplied with 1.8V Vdd
12330  */
12331 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL18 0x1
12332 
12333 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field. */
12334 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_LSB 7
12335 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field. */
12336 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_MSB 7
12337 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field. */
12338 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_WIDTH 1
12339 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field value. */
12340 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_SET_MSK 0x00000080
12341 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field value. */
12342 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_CLR_MSK 0xffffff7f
12343 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_7 register field. */
12344 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_RESET 0x0
12345 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_7 field value from a register. */
12346 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_GET(value) (((value) & 0x00000080) >> 7)
12347 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_7 register field value suitable for setting the register. */
12348 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_SET(value) (((value) << 7) & 0x00000080)
12349 
12350 /*
12351  * Field : VOLT_REG_8
12352  *
12353  * High Voltage mode. Determines the voltage fed to the buffers by an
12354  *
12355  * external voltage regulator.
12356  *
12357  * 0 Buffers supplied with 3.3V Vdd
12358  *
12359  * 1 Buffers supplied with 1.8V Vdd
12360  *
12361  * These bits function as the output of the host controller and are fed to an
12362  * external voltage regulator. The voltage regulator must switch the voltage of the
12363  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12364  *
12365  * value programmed in the register.
12366  *
12367  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12368  *
12369  * operate for 1.8V.
12370  *
12371  * Field Enumeration Values:
12372  *
12373  * Enum | Value | Description
12374  * :-------------------------------------|:------|:-------------------------------
12375  * ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12376  * ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12377  *
12378  * Field Access Macros:
12379  *
12380  */
12381 /*
12382  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_8
12383  *
12384  * Buffers supplied with 3.3V Vdd
12385  */
12386 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL33 0x0
12387 /*
12388  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_8
12389  *
12390  * Buffers supplied with 1.8V Vdd
12391  */
12392 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL18 0x1
12393 
12394 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field. */
12395 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_LSB 8
12396 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field. */
12397 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_MSB 8
12398 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field. */
12399 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_WIDTH 1
12400 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field value. */
12401 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_SET_MSK 0x00000100
12402 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field value. */
12403 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_CLR_MSK 0xfffffeff
12404 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_8 register field. */
12405 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_RESET 0x0
12406 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_8 field value from a register. */
12407 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_GET(value) (((value) & 0x00000100) >> 8)
12408 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_8 register field value suitable for setting the register. */
12409 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_SET(value) (((value) << 8) & 0x00000100)
12410 
12411 /*
12412  * Field : VOLT_REG_9
12413  *
12414  * High Voltage mode. Determines the voltage fed to the buffers by an
12415  *
12416  * external voltage regulator.
12417  *
12418  * 0 Buffers supplied with 3.3V Vdd
12419  *
12420  * 1 Buffers supplied with 1.8V Vdd
12421  *
12422  * These bits function as the output of the host controller and are fed to an
12423  * external voltage regulator. The voltage regulator must switch the voltage of the
12424  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12425  *
12426  * value programmed in the register.
12427  *
12428  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12429  *
12430  * operate for 1.8V.
12431  *
12432  * Field Enumeration Values:
12433  *
12434  * Enum | Value | Description
12435  * :-------------------------------------|:------|:-------------------------------
12436  * ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12437  * ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12438  *
12439  * Field Access Macros:
12440  *
12441  */
12442 /*
12443  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_9
12444  *
12445  * Buffers supplied with 3.3V Vdd
12446  */
12447 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL33 0x0
12448 /*
12449  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_9
12450  *
12451  * Buffers supplied with 1.8V Vdd
12452  */
12453 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL18 0x1
12454 
12455 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field. */
12456 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_LSB 9
12457 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field. */
12458 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_MSB 9
12459 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field. */
12460 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_WIDTH 1
12461 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field value. */
12462 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_SET_MSK 0x00000200
12463 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field value. */
12464 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_CLR_MSK 0xfffffdff
12465 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_9 register field. */
12466 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_RESET 0x0
12467 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_9 field value from a register. */
12468 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_GET(value) (((value) & 0x00000200) >> 9)
12469 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_9 register field value suitable for setting the register. */
12470 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_SET(value) (((value) << 9) & 0x00000200)
12471 
12472 /*
12473  * Field : VOLT_REG_10
12474  *
12475  * High Voltage mode. Determines the voltage fed to the buffers by an
12476  *
12477  * external voltage regulator.
12478  *
12479  * 0 Buffers supplied with 3.3V Vdd
12480  *
12481  * 1 Buffers supplied with 1.8V Vdd
12482  *
12483  * These bits function as the output of the host controller and are fed to an
12484  * external voltage regulator. The voltage regulator must switch the voltage of the
12485  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12486  *
12487  * value programmed in the register.
12488  *
12489  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12490  *
12491  * operate for 1.8V.
12492  *
12493  * Field Enumeration Values:
12494  *
12495  * Enum | Value | Description
12496  * :--------------------------------------|:------|:-------------------------------
12497  * ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12498  * ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12499  *
12500  * Field Access Macros:
12501  *
12502  */
12503 /*
12504  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_10
12505  *
12506  * Buffers supplied with 3.3V Vdd
12507  */
12508 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL33 0x0
12509 /*
12510  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_10
12511  *
12512  * Buffers supplied with 1.8V Vdd
12513  */
12514 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL18 0x1
12515 
12516 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field. */
12517 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_LSB 10
12518 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field. */
12519 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_MSB 10
12520 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field. */
12521 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_WIDTH 1
12522 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field value. */
12523 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_SET_MSK 0x00000400
12524 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field value. */
12525 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_CLR_MSK 0xfffffbff
12526 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_10 register field. */
12527 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_RESET 0x0
12528 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_10 field value from a register. */
12529 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_GET(value) (((value) & 0x00000400) >> 10)
12530 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_10 register field value suitable for setting the register. */
12531 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_SET(value) (((value) << 10) & 0x00000400)
12532 
12533 /*
12534  * Field : VOLT_REG_11
12535  *
12536  * High Voltage mode. Determines the voltage fed to the buffers by an
12537  *
12538  * external voltage regulator.
12539  *
12540  * 0 Buffers supplied with 3.3V Vdd
12541  *
12542  * 1 Buffers supplied with 1.8V Vdd
12543  *
12544  * These bits function as the output of the host controller and are fed to an
12545  * external voltage regulator. The voltage regulator must switch the voltage of the
12546  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12547  *
12548  * value programmed in the register.
12549  *
12550  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12551  *
12552  * operate for 1.8V.
12553  *
12554  * Field Enumeration Values:
12555  *
12556  * Enum | Value | Description
12557  * :--------------------------------------|:------|:-------------------------------
12558  * ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12559  * ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12560  *
12561  * Field Access Macros:
12562  *
12563  */
12564 /*
12565  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_11
12566  *
12567  * Buffers supplied with 3.3V Vdd
12568  */
12569 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL33 0x0
12570 /*
12571  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_11
12572  *
12573  * Buffers supplied with 1.8V Vdd
12574  */
12575 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL18 0x1
12576 
12577 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field. */
12578 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_LSB 11
12579 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field. */
12580 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_MSB 11
12581 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field. */
12582 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_WIDTH 1
12583 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field value. */
12584 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_SET_MSK 0x00000800
12585 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field value. */
12586 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_CLR_MSK 0xfffff7ff
12587 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_11 register field. */
12588 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_RESET 0x0
12589 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_11 field value from a register. */
12590 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_GET(value) (((value) & 0x00000800) >> 11)
12591 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_11 register field value suitable for setting the register. */
12592 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_SET(value) (((value) << 11) & 0x00000800)
12593 
12594 /*
12595  * Field : VOLT_REG_12
12596  *
12597  * High Voltage mode. Determines the voltage fed to the buffers by an
12598  *
12599  * external voltage regulator.
12600  *
12601  * 0 Buffers supplied with 3.3V Vdd
12602  *
12603  * 1 Buffers supplied with 1.8V Vdd
12604  *
12605  * These bits function as the output of the host controller and are fed to an
12606  * external voltage regulator. The voltage regulator must switch the voltage of the
12607  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12608  *
12609  * value programmed in the register.
12610  *
12611  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12612  *
12613  * operate for 1.8V.
12614  *
12615  * Field Enumeration Values:
12616  *
12617  * Enum | Value | Description
12618  * :--------------------------------------|:------|:-------------------------------
12619  * ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12620  * ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12621  *
12622  * Field Access Macros:
12623  *
12624  */
12625 /*
12626  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_12
12627  *
12628  * Buffers supplied with 3.3V Vdd
12629  */
12630 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL33 0x0
12631 /*
12632  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_12
12633  *
12634  * Buffers supplied with 1.8V Vdd
12635  */
12636 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL18 0x1
12637 
12638 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field. */
12639 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_LSB 12
12640 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field. */
12641 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_MSB 12
12642 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field. */
12643 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_WIDTH 1
12644 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field value. */
12645 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_SET_MSK 0x00001000
12646 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field value. */
12647 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_CLR_MSK 0xffffefff
12648 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_12 register field. */
12649 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_RESET 0x0
12650 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_12 field value from a register. */
12651 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_GET(value) (((value) & 0x00001000) >> 12)
12652 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_12 register field value suitable for setting the register. */
12653 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_SET(value) (((value) << 12) & 0x00001000)
12654 
12655 /*
12656  * Field : VOLT_REG_13
12657  *
12658  * High Voltage mode. Determines the voltage fed to the buffers by an
12659  *
12660  * external voltage regulator.
12661  *
12662  * 0 Buffers supplied with 3.3V Vdd
12663  *
12664  * 1 Buffers supplied with 1.8V Vdd
12665  *
12666  * These bits function as the output of the host controller and are fed to an
12667  * external voltage regulator. The voltage regulator must switch the voltage of the
12668  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12669  *
12670  * value programmed in the register.
12671  *
12672  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12673  *
12674  * operate for 1.8V.
12675  *
12676  * Field Enumeration Values:
12677  *
12678  * Enum | Value | Description
12679  * :--------------------------------------|:------|:-------------------------------
12680  * ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12681  * ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12682  *
12683  * Field Access Macros:
12684  *
12685  */
12686 /*
12687  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_13
12688  *
12689  * Buffers supplied with 3.3V Vdd
12690  */
12691 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL33 0x0
12692 /*
12693  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_13
12694  *
12695  * Buffers supplied with 1.8V Vdd
12696  */
12697 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL18 0x1
12698 
12699 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field. */
12700 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_LSB 13
12701 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field. */
12702 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_MSB 13
12703 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field. */
12704 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_WIDTH 1
12705 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field value. */
12706 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_SET_MSK 0x00002000
12707 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field value. */
12708 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_CLR_MSK 0xffffdfff
12709 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_13 register field. */
12710 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_RESET 0x0
12711 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_13 field value from a register. */
12712 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_GET(value) (((value) & 0x00002000) >> 13)
12713 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_13 register field value suitable for setting the register. */
12714 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_SET(value) (((value) << 13) & 0x00002000)
12715 
12716 /*
12717  * Field : VOLT_REG_14
12718  *
12719  * High Voltage mode. Determines the voltage fed to the buffers by an
12720  *
12721  * external voltage regulator.
12722  *
12723  * 0 Buffers supplied with 3.3V Vdd
12724  *
12725  * 1 Buffers supplied with 1.8V Vdd
12726  *
12727  * These bits function as the output of the host controller and are fed to an
12728  * external voltage regulator. The voltage regulator must switch the voltage of the
12729  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12730  *
12731  * value programmed in the register.
12732  *
12733  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12734  *
12735  * operate for 1.8V.
12736  *
12737  * Field Enumeration Values:
12738  *
12739  * Enum | Value | Description
12740  * :--------------------------------------|:------|:-------------------------------
12741  * ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12742  * ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12743  *
12744  * Field Access Macros:
12745  *
12746  */
12747 /*
12748  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_14
12749  *
12750  * Buffers supplied with 3.3V Vdd
12751  */
12752 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL33 0x0
12753 /*
12754  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_14
12755  *
12756  * Buffers supplied with 1.8V Vdd
12757  */
12758 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL18 0x1
12759 
12760 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field. */
12761 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_LSB 14
12762 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field. */
12763 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_MSB 14
12764 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field. */
12765 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_WIDTH 1
12766 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field value. */
12767 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_SET_MSK 0x00004000
12768 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field value. */
12769 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_CLR_MSK 0xffffbfff
12770 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_14 register field. */
12771 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_RESET 0x0
12772 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_14 field value from a register. */
12773 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_GET(value) (((value) & 0x00004000) >> 14)
12774 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_14 register field value suitable for setting the register. */
12775 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_SET(value) (((value) << 14) & 0x00004000)
12776 
12777 /*
12778  * Field : VOLT_REG_15
12779  *
12780  * High Voltage mode. Determines the voltage fed to the buffers by an
12781  *
12782  * external voltage regulator.
12783  *
12784  * 0 Buffers supplied with 3.3V Vdd
12785  *
12786  * 1 Buffers supplied with 1.8V Vdd
12787  *
12788  * These bits function as the output of the host controller and are fed to an
12789  * external voltage regulator. The voltage regulator must switch the voltage of the
12790  * buffers of a particular card to either 3.3V or 1.8V, depending on the
12791  *
12792  * value programmed in the register.
12793  *
12794  * VOLT_REG[0] should be set to 1'b1 for card number 0 in order to make it
12795  *
12796  * operate for 1.8V.
12797  *
12798  * Field Enumeration Values:
12799  *
12800  * Enum | Value | Description
12801  * :--------------------------------------|:------|:-------------------------------
12802  * ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL33 | 0x0 | Buffers supplied with 3.3V Vdd
12803  * ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL18 | 0x1 | Buffers supplied with 1.8V Vdd
12804  *
12805  * Field Access Macros:
12806  *
12807  */
12808 /*
12809  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_15
12810  *
12811  * Buffers supplied with 3.3V Vdd
12812  */
12813 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL33 0x0
12814 /*
12815  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG_15
12816  *
12817  * Buffers supplied with 1.8V Vdd
12818  */
12819 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL18 0x1
12820 
12821 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field. */
12822 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_LSB 15
12823 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field. */
12824 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_MSB 15
12825 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field. */
12826 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_WIDTH 1
12827 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field value. */
12828 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_SET_MSK 0x00008000
12829 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field value. */
12830 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_CLR_MSK 0xffff7fff
12831 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG_15 register field. */
12832 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_RESET 0x0
12833 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG_15 field value from a register. */
12834 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_GET(value) (((value) & 0x00008000) >> 15)
12835 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG_15 register field value suitable for setting the register. */
12836 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_SET(value) (((value) << 15) & 0x00008000)
12837 
12838 /*
12839  * Field : DDR_REG_0
12840  *
12841  * DDR mode. These bits indicate DDR mode of operation to the core for the data
12842  * transfer.
12843  *
12844  * 0 Non-DDR mode
12845  *
12846  * 1 DDR mode
12847  *
12848  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
12849  * so on.
12850  *
12851  * Field Enumeration Values:
12852  *
12853  * Enum | Value | Description
12854  * :---------------------------------------|:------|:--------------------------------------------
12855  * ALT_SDMMC_UHS_REG_DDR_REG_0_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
12856  * ALT_SDMMC_UHS_REG_DDR_REG_0_E_ENABLED | 0x1 | DDR Mode
12857  *
12858  * Field Access Macros:
12859  *
12860  */
12861 /*
12862  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_0
12863  *
12864  * Non DDR Mode;clear these bits in HS400 Mode
12865  */
12866 #define ALT_SDMMC_UHS_REG_DDR_REG_0_E_DISABLED 0x0
12867 /*
12868  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_0
12869  *
12870  * DDR Mode
12871  */
12872 #define ALT_SDMMC_UHS_REG_DDR_REG_0_E_ENABLED 0x1
12873 
12874 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_0 register field. */
12875 #define ALT_SDMMC_UHS_REG_DDR_REG_0_LSB 16
12876 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_0 register field. */
12877 #define ALT_SDMMC_UHS_REG_DDR_REG_0_MSB 16
12878 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_0 register field. */
12879 #define ALT_SDMMC_UHS_REG_DDR_REG_0_WIDTH 1
12880 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_0 register field value. */
12881 #define ALT_SDMMC_UHS_REG_DDR_REG_0_SET_MSK 0x00010000
12882 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_0 register field value. */
12883 #define ALT_SDMMC_UHS_REG_DDR_REG_0_CLR_MSK 0xfffeffff
12884 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_0 register field. */
12885 #define ALT_SDMMC_UHS_REG_DDR_REG_0_RESET 0x0
12886 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_0 field value from a register. */
12887 #define ALT_SDMMC_UHS_REG_DDR_REG_0_GET(value) (((value) & 0x00010000) >> 16)
12888 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_0 register field value suitable for setting the register. */
12889 #define ALT_SDMMC_UHS_REG_DDR_REG_0_SET(value) (((value) << 16) & 0x00010000)
12890 
12891 /*
12892  * Field : DDR_REG_1
12893  *
12894  * DDR mode. These bits indicate DDR mode of operation to the core for the data
12895  * transfer.
12896  *
12897  * 0 Non-DDR mode
12898  *
12899  * 1 DDR mode
12900  *
12901  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
12902  * so on.
12903  *
12904  * Field Enumeration Values:
12905  *
12906  * Enum | Value | Description
12907  * :---------------------------------------|:------|:--------------------------------------------
12908  * ALT_SDMMC_UHS_REG_DDR_REG_1_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
12909  * ALT_SDMMC_UHS_REG_DDR_REG_1_E_ENABLED | 0x1 | DDR Mode
12910  *
12911  * Field Access Macros:
12912  *
12913  */
12914 /*
12915  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_1
12916  *
12917  * Non DDR Mode;clear these bits in HS400 Mode
12918  */
12919 #define ALT_SDMMC_UHS_REG_DDR_REG_1_E_DISABLED 0x0
12920 /*
12921  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_1
12922  *
12923  * DDR Mode
12924  */
12925 #define ALT_SDMMC_UHS_REG_DDR_REG_1_E_ENABLED 0x1
12926 
12927 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_1 register field. */
12928 #define ALT_SDMMC_UHS_REG_DDR_REG_1_LSB 17
12929 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_1 register field. */
12930 #define ALT_SDMMC_UHS_REG_DDR_REG_1_MSB 17
12931 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_1 register field. */
12932 #define ALT_SDMMC_UHS_REG_DDR_REG_1_WIDTH 1
12933 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_1 register field value. */
12934 #define ALT_SDMMC_UHS_REG_DDR_REG_1_SET_MSK 0x00020000
12935 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_1 register field value. */
12936 #define ALT_SDMMC_UHS_REG_DDR_REG_1_CLR_MSK 0xfffdffff
12937 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_1 register field. */
12938 #define ALT_SDMMC_UHS_REG_DDR_REG_1_RESET 0x0
12939 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_1 field value from a register. */
12940 #define ALT_SDMMC_UHS_REG_DDR_REG_1_GET(value) (((value) & 0x00020000) >> 17)
12941 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_1 register field value suitable for setting the register. */
12942 #define ALT_SDMMC_UHS_REG_DDR_REG_1_SET(value) (((value) << 17) & 0x00020000)
12943 
12944 /*
12945  * Field : DDR_REG_2
12946  *
12947  * DDR mode. These bits indicate DDR mode of operation to the core for the data
12948  * transfer.
12949  *
12950  * 0 Non-DDR mode
12951  *
12952  * 1 DDR mode
12953  *
12954  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
12955  * so on.
12956  *
12957  * Field Enumeration Values:
12958  *
12959  * Enum | Value | Description
12960  * :---------------------------------------|:------|:--------------------------------------------
12961  * ALT_SDMMC_UHS_REG_DDR_REG_2_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
12962  * ALT_SDMMC_UHS_REG_DDR_REG_2_E_ENABLED | 0x1 | DDR Mode
12963  *
12964  * Field Access Macros:
12965  *
12966  */
12967 /*
12968  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_2
12969  *
12970  * Non DDR Mode;clear these bits in HS400 Mode
12971  */
12972 #define ALT_SDMMC_UHS_REG_DDR_REG_2_E_DISABLED 0x0
12973 /*
12974  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_2
12975  *
12976  * DDR Mode
12977  */
12978 #define ALT_SDMMC_UHS_REG_DDR_REG_2_E_ENABLED 0x1
12979 
12980 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_2 register field. */
12981 #define ALT_SDMMC_UHS_REG_DDR_REG_2_LSB 18
12982 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_2 register field. */
12983 #define ALT_SDMMC_UHS_REG_DDR_REG_2_MSB 18
12984 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_2 register field. */
12985 #define ALT_SDMMC_UHS_REG_DDR_REG_2_WIDTH 1
12986 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_2 register field value. */
12987 #define ALT_SDMMC_UHS_REG_DDR_REG_2_SET_MSK 0x00040000
12988 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_2 register field value. */
12989 #define ALT_SDMMC_UHS_REG_DDR_REG_2_CLR_MSK 0xfffbffff
12990 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_2 register field. */
12991 #define ALT_SDMMC_UHS_REG_DDR_REG_2_RESET 0x0
12992 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_2 field value from a register. */
12993 #define ALT_SDMMC_UHS_REG_DDR_REG_2_GET(value) (((value) & 0x00040000) >> 18)
12994 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_2 register field value suitable for setting the register. */
12995 #define ALT_SDMMC_UHS_REG_DDR_REG_2_SET(value) (((value) << 18) & 0x00040000)
12996 
12997 /*
12998  * Field : DDR_REG_3
12999  *
13000  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13001  * transfer.
13002  *
13003  * 0 Non-DDR mode
13004  *
13005  * 1 DDR mode
13006  *
13007  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13008  * so on.
13009  *
13010  * Field Enumeration Values:
13011  *
13012  * Enum | Value | Description
13013  * :---------------------------------------|:------|:--------------------------------------------
13014  * ALT_SDMMC_UHS_REG_DDR_REG_3_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13015  * ALT_SDMMC_UHS_REG_DDR_REG_3_E_ENABLED | 0x1 | DDR Mode
13016  *
13017  * Field Access Macros:
13018  *
13019  */
13020 /*
13021  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_3
13022  *
13023  * Non DDR Mode;clear these bits in HS400 Mode
13024  */
13025 #define ALT_SDMMC_UHS_REG_DDR_REG_3_E_DISABLED 0x0
13026 /*
13027  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_3
13028  *
13029  * DDR Mode
13030  */
13031 #define ALT_SDMMC_UHS_REG_DDR_REG_3_E_ENABLED 0x1
13032 
13033 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_3 register field. */
13034 #define ALT_SDMMC_UHS_REG_DDR_REG_3_LSB 19
13035 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_3 register field. */
13036 #define ALT_SDMMC_UHS_REG_DDR_REG_3_MSB 19
13037 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_3 register field. */
13038 #define ALT_SDMMC_UHS_REG_DDR_REG_3_WIDTH 1
13039 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_3 register field value. */
13040 #define ALT_SDMMC_UHS_REG_DDR_REG_3_SET_MSK 0x00080000
13041 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_3 register field value. */
13042 #define ALT_SDMMC_UHS_REG_DDR_REG_3_CLR_MSK 0xfff7ffff
13043 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_3 register field. */
13044 #define ALT_SDMMC_UHS_REG_DDR_REG_3_RESET 0x0
13045 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_3 field value from a register. */
13046 #define ALT_SDMMC_UHS_REG_DDR_REG_3_GET(value) (((value) & 0x00080000) >> 19)
13047 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_3 register field value suitable for setting the register. */
13048 #define ALT_SDMMC_UHS_REG_DDR_REG_3_SET(value) (((value) << 19) & 0x00080000)
13049 
13050 /*
13051  * Field : DDR_REG_4
13052  *
13053  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13054  * transfer.
13055  *
13056  * 0 Non-DDR mode
13057  *
13058  * 1 DDR mode
13059  *
13060  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13061  * so on.
13062  *
13063  * Field Enumeration Values:
13064  *
13065  * Enum | Value | Description
13066  * :---------------------------------------|:------|:--------------------------------------------
13067  * ALT_SDMMC_UHS_REG_DDR_REG_4_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13068  * ALT_SDMMC_UHS_REG_DDR_REG_4_E_ENABLED | 0x1 | DDR Mode
13069  *
13070  * Field Access Macros:
13071  *
13072  */
13073 /*
13074  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_4
13075  *
13076  * Non DDR Mode;clear these bits in HS400 Mode
13077  */
13078 #define ALT_SDMMC_UHS_REG_DDR_REG_4_E_DISABLED 0x0
13079 /*
13080  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_4
13081  *
13082  * DDR Mode
13083  */
13084 #define ALT_SDMMC_UHS_REG_DDR_REG_4_E_ENABLED 0x1
13085 
13086 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_4 register field. */
13087 #define ALT_SDMMC_UHS_REG_DDR_REG_4_LSB 20
13088 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_4 register field. */
13089 #define ALT_SDMMC_UHS_REG_DDR_REG_4_MSB 20
13090 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_4 register field. */
13091 #define ALT_SDMMC_UHS_REG_DDR_REG_4_WIDTH 1
13092 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_4 register field value. */
13093 #define ALT_SDMMC_UHS_REG_DDR_REG_4_SET_MSK 0x00100000
13094 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_4 register field value. */
13095 #define ALT_SDMMC_UHS_REG_DDR_REG_4_CLR_MSK 0xffefffff
13096 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_4 register field. */
13097 #define ALT_SDMMC_UHS_REG_DDR_REG_4_RESET 0x0
13098 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_4 field value from a register. */
13099 #define ALT_SDMMC_UHS_REG_DDR_REG_4_GET(value) (((value) & 0x00100000) >> 20)
13100 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_4 register field value suitable for setting the register. */
13101 #define ALT_SDMMC_UHS_REG_DDR_REG_4_SET(value) (((value) << 20) & 0x00100000)
13102 
13103 /*
13104  * Field : DDR_REG_5
13105  *
13106  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13107  * transfer.
13108  *
13109  * 0 Non-DDR mode
13110  *
13111  * 1 DDR mode
13112  *
13113  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13114  * so on.
13115  *
13116  * Field Enumeration Values:
13117  *
13118  * Enum | Value | Description
13119  * :---------------------------------------|:------|:--------------------------------------------
13120  * ALT_SDMMC_UHS_REG_DDR_REG_5_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13121  * ALT_SDMMC_UHS_REG_DDR_REG_5_E_ENABLED | 0x1 | DDR Mode
13122  *
13123  * Field Access Macros:
13124  *
13125  */
13126 /*
13127  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_5
13128  *
13129  * Non DDR Mode;clear these bits in HS400 Mode
13130  */
13131 #define ALT_SDMMC_UHS_REG_DDR_REG_5_E_DISABLED 0x0
13132 /*
13133  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_5
13134  *
13135  * DDR Mode
13136  */
13137 #define ALT_SDMMC_UHS_REG_DDR_REG_5_E_ENABLED 0x1
13138 
13139 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_5 register field. */
13140 #define ALT_SDMMC_UHS_REG_DDR_REG_5_LSB 21
13141 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_5 register field. */
13142 #define ALT_SDMMC_UHS_REG_DDR_REG_5_MSB 21
13143 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_5 register field. */
13144 #define ALT_SDMMC_UHS_REG_DDR_REG_5_WIDTH 1
13145 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_5 register field value. */
13146 #define ALT_SDMMC_UHS_REG_DDR_REG_5_SET_MSK 0x00200000
13147 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_5 register field value. */
13148 #define ALT_SDMMC_UHS_REG_DDR_REG_5_CLR_MSK 0xffdfffff
13149 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_5 register field. */
13150 #define ALT_SDMMC_UHS_REG_DDR_REG_5_RESET 0x0
13151 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_5 field value from a register. */
13152 #define ALT_SDMMC_UHS_REG_DDR_REG_5_GET(value) (((value) & 0x00200000) >> 21)
13153 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_5 register field value suitable for setting the register. */
13154 #define ALT_SDMMC_UHS_REG_DDR_REG_5_SET(value) (((value) << 21) & 0x00200000)
13155 
13156 /*
13157  * Field : DDR_REG_6
13158  *
13159  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13160  * transfer.
13161  *
13162  * 0 Non-DDR mode
13163  *
13164  * 1 DDR mode
13165  *
13166  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13167  * so on.
13168  *
13169  * Field Enumeration Values:
13170  *
13171  * Enum | Value | Description
13172  * :---------------------------------------|:------|:--------------------------------------------
13173  * ALT_SDMMC_UHS_REG_DDR_REG_6_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13174  * ALT_SDMMC_UHS_REG_DDR_REG_6_E_ENABLED | 0x1 | DDR Mode
13175  *
13176  * Field Access Macros:
13177  *
13178  */
13179 /*
13180  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_6
13181  *
13182  * Non DDR Mode;clear these bits in HS400 Mode
13183  */
13184 #define ALT_SDMMC_UHS_REG_DDR_REG_6_E_DISABLED 0x0
13185 /*
13186  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_6
13187  *
13188  * DDR Mode
13189  */
13190 #define ALT_SDMMC_UHS_REG_DDR_REG_6_E_ENABLED 0x1
13191 
13192 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_6 register field. */
13193 #define ALT_SDMMC_UHS_REG_DDR_REG_6_LSB 22
13194 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_6 register field. */
13195 #define ALT_SDMMC_UHS_REG_DDR_REG_6_MSB 22
13196 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_6 register field. */
13197 #define ALT_SDMMC_UHS_REG_DDR_REG_6_WIDTH 1
13198 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_6 register field value. */
13199 #define ALT_SDMMC_UHS_REG_DDR_REG_6_SET_MSK 0x00400000
13200 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_6 register field value. */
13201 #define ALT_SDMMC_UHS_REG_DDR_REG_6_CLR_MSK 0xffbfffff
13202 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_6 register field. */
13203 #define ALT_SDMMC_UHS_REG_DDR_REG_6_RESET 0x0
13204 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_6 field value from a register. */
13205 #define ALT_SDMMC_UHS_REG_DDR_REG_6_GET(value) (((value) & 0x00400000) >> 22)
13206 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_6 register field value suitable for setting the register. */
13207 #define ALT_SDMMC_UHS_REG_DDR_REG_6_SET(value) (((value) << 22) & 0x00400000)
13208 
13209 /*
13210  * Field : DDR_REG_7
13211  *
13212  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13213  * transfer.
13214  *
13215  * 0 Non-DDR mode
13216  *
13217  * 1 DDR mode
13218  *
13219  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13220  * so on.
13221  *
13222  * Field Enumeration Values:
13223  *
13224  * Enum | Value | Description
13225  * :---------------------------------------|:------|:--------------------------------------------
13226  * ALT_SDMMC_UHS_REG_DDR_REG_7_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13227  * ALT_SDMMC_UHS_REG_DDR_REG_7_E_ENABLED | 0x1 | DDR Mode
13228  *
13229  * Field Access Macros:
13230  *
13231  */
13232 /*
13233  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_7
13234  *
13235  * Non DDR Mode;clear these bits in HS400 Mode
13236  */
13237 #define ALT_SDMMC_UHS_REG_DDR_REG_7_E_DISABLED 0x0
13238 /*
13239  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_7
13240  *
13241  * DDR Mode
13242  */
13243 #define ALT_SDMMC_UHS_REG_DDR_REG_7_E_ENABLED 0x1
13244 
13245 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_7 register field. */
13246 #define ALT_SDMMC_UHS_REG_DDR_REG_7_LSB 23
13247 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_7 register field. */
13248 #define ALT_SDMMC_UHS_REG_DDR_REG_7_MSB 23
13249 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_7 register field. */
13250 #define ALT_SDMMC_UHS_REG_DDR_REG_7_WIDTH 1
13251 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_7 register field value. */
13252 #define ALT_SDMMC_UHS_REG_DDR_REG_7_SET_MSK 0x00800000
13253 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_7 register field value. */
13254 #define ALT_SDMMC_UHS_REG_DDR_REG_7_CLR_MSK 0xff7fffff
13255 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_7 register field. */
13256 #define ALT_SDMMC_UHS_REG_DDR_REG_7_RESET 0x0
13257 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_7 field value from a register. */
13258 #define ALT_SDMMC_UHS_REG_DDR_REG_7_GET(value) (((value) & 0x00800000) >> 23)
13259 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_7 register field value suitable for setting the register. */
13260 #define ALT_SDMMC_UHS_REG_DDR_REG_7_SET(value) (((value) << 23) & 0x00800000)
13261 
13262 /*
13263  * Field : DDR_REG_8
13264  *
13265  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13266  * transfer.
13267  *
13268  * 0 Non-DDR mode
13269  *
13270  * 1 DDR mode
13271  *
13272  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13273  * so on.
13274  *
13275  * Field Enumeration Values:
13276  *
13277  * Enum | Value | Description
13278  * :---------------------------------------|:------|:--------------------------------------------
13279  * ALT_SDMMC_UHS_REG_DDR_REG_8_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13280  * ALT_SDMMC_UHS_REG_DDR_REG_8_E_ENABLED | 0x1 | DDR Mode
13281  *
13282  * Field Access Macros:
13283  *
13284  */
13285 /*
13286  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_8
13287  *
13288  * Non DDR Mode;clear these bits in HS400 Mode
13289  */
13290 #define ALT_SDMMC_UHS_REG_DDR_REG_8_E_DISABLED 0x0
13291 /*
13292  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_8
13293  *
13294  * DDR Mode
13295  */
13296 #define ALT_SDMMC_UHS_REG_DDR_REG_8_E_ENABLED 0x1
13297 
13298 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_8 register field. */
13299 #define ALT_SDMMC_UHS_REG_DDR_REG_8_LSB 24
13300 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_8 register field. */
13301 #define ALT_SDMMC_UHS_REG_DDR_REG_8_MSB 24
13302 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_8 register field. */
13303 #define ALT_SDMMC_UHS_REG_DDR_REG_8_WIDTH 1
13304 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_8 register field value. */
13305 #define ALT_SDMMC_UHS_REG_DDR_REG_8_SET_MSK 0x01000000
13306 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_8 register field value. */
13307 #define ALT_SDMMC_UHS_REG_DDR_REG_8_CLR_MSK 0xfeffffff
13308 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_8 register field. */
13309 #define ALT_SDMMC_UHS_REG_DDR_REG_8_RESET 0x0
13310 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_8 field value from a register. */
13311 #define ALT_SDMMC_UHS_REG_DDR_REG_8_GET(value) (((value) & 0x01000000) >> 24)
13312 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_8 register field value suitable for setting the register. */
13313 #define ALT_SDMMC_UHS_REG_DDR_REG_8_SET(value) (((value) << 24) & 0x01000000)
13314 
13315 /*
13316  * Field : DDR_REG_9
13317  *
13318  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13319  * transfer.
13320  *
13321  * 0 Non-DDR mode
13322  *
13323  * 1 DDR mode
13324  *
13325  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13326  * so on.
13327  *
13328  * Field Enumeration Values:
13329  *
13330  * Enum | Value | Description
13331  * :---------------------------------------|:------|:--------------------------------------------
13332  * ALT_SDMMC_UHS_REG_DDR_REG_9_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13333  * ALT_SDMMC_UHS_REG_DDR_REG_9_E_ENABLED | 0x1 | DDR Mode
13334  *
13335  * Field Access Macros:
13336  *
13337  */
13338 /*
13339  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_9
13340  *
13341  * Non DDR Mode;clear these bits in HS400 Mode
13342  */
13343 #define ALT_SDMMC_UHS_REG_DDR_REG_9_E_DISABLED 0x0
13344 /*
13345  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_9
13346  *
13347  * DDR Mode
13348  */
13349 #define ALT_SDMMC_UHS_REG_DDR_REG_9_E_ENABLED 0x1
13350 
13351 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_9 register field. */
13352 #define ALT_SDMMC_UHS_REG_DDR_REG_9_LSB 25
13353 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_9 register field. */
13354 #define ALT_SDMMC_UHS_REG_DDR_REG_9_MSB 25
13355 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_9 register field. */
13356 #define ALT_SDMMC_UHS_REG_DDR_REG_9_WIDTH 1
13357 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_9 register field value. */
13358 #define ALT_SDMMC_UHS_REG_DDR_REG_9_SET_MSK 0x02000000
13359 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_9 register field value. */
13360 #define ALT_SDMMC_UHS_REG_DDR_REG_9_CLR_MSK 0xfdffffff
13361 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_9 register field. */
13362 #define ALT_SDMMC_UHS_REG_DDR_REG_9_RESET 0x0
13363 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_9 field value from a register. */
13364 #define ALT_SDMMC_UHS_REG_DDR_REG_9_GET(value) (((value) & 0x02000000) >> 25)
13365 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_9 register field value suitable for setting the register. */
13366 #define ALT_SDMMC_UHS_REG_DDR_REG_9_SET(value) (((value) << 25) & 0x02000000)
13367 
13368 /*
13369  * Field : DDR_REG_10
13370  *
13371  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13372  * transfer.
13373  *
13374  * 0 Non-DDR mode
13375  *
13376  * 1 DDR mode
13377  *
13378  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13379  * so on.
13380  *
13381  * Field Enumeration Values:
13382  *
13383  * Enum | Value | Description
13384  * :----------------------------------------|:------|:--------------------------------------------
13385  * ALT_SDMMC_UHS_REG_DDR_REG_10_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13386  * ALT_SDMMC_UHS_REG_DDR_REG_10_E_ENABLED | 0x1 | DDR Mode
13387  *
13388  * Field Access Macros:
13389  *
13390  */
13391 /*
13392  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_10
13393  *
13394  * Non DDR Mode;clear these bits in HS400 Mode
13395  */
13396 #define ALT_SDMMC_UHS_REG_DDR_REG_10_E_DISABLED 0x0
13397 /*
13398  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_10
13399  *
13400  * DDR Mode
13401  */
13402 #define ALT_SDMMC_UHS_REG_DDR_REG_10_E_ENABLED 0x1
13403 
13404 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_10 register field. */
13405 #define ALT_SDMMC_UHS_REG_DDR_REG_10_LSB 26
13406 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_10 register field. */
13407 #define ALT_SDMMC_UHS_REG_DDR_REG_10_MSB 26
13408 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_10 register field. */
13409 #define ALT_SDMMC_UHS_REG_DDR_REG_10_WIDTH 1
13410 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_10 register field value. */
13411 #define ALT_SDMMC_UHS_REG_DDR_REG_10_SET_MSK 0x04000000
13412 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_10 register field value. */
13413 #define ALT_SDMMC_UHS_REG_DDR_REG_10_CLR_MSK 0xfbffffff
13414 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_10 register field. */
13415 #define ALT_SDMMC_UHS_REG_DDR_REG_10_RESET 0x0
13416 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_10 field value from a register. */
13417 #define ALT_SDMMC_UHS_REG_DDR_REG_10_GET(value) (((value) & 0x04000000) >> 26)
13418 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_10 register field value suitable for setting the register. */
13419 #define ALT_SDMMC_UHS_REG_DDR_REG_10_SET(value) (((value) << 26) & 0x04000000)
13420 
13421 /*
13422  * Field : DDR_REG_11
13423  *
13424  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13425  * transfer.
13426  *
13427  * 0 Non-DDR mode
13428  *
13429  * 1 DDR mode
13430  *
13431  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13432  * so on.
13433  *
13434  * Field Enumeration Values:
13435  *
13436  * Enum | Value | Description
13437  * :----------------------------------------|:------|:--------------------------------------------
13438  * ALT_SDMMC_UHS_REG_DDR_REG_11_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13439  * ALT_SDMMC_UHS_REG_DDR_REG_11_E_ENABLED | 0x1 | DDR Mode
13440  *
13441  * Field Access Macros:
13442  *
13443  */
13444 /*
13445  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_11
13446  *
13447  * Non DDR Mode;clear these bits in HS400 Mode
13448  */
13449 #define ALT_SDMMC_UHS_REG_DDR_REG_11_E_DISABLED 0x0
13450 /*
13451  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_11
13452  *
13453  * DDR Mode
13454  */
13455 #define ALT_SDMMC_UHS_REG_DDR_REG_11_E_ENABLED 0x1
13456 
13457 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_11 register field. */
13458 #define ALT_SDMMC_UHS_REG_DDR_REG_11_LSB 27
13459 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_11 register field. */
13460 #define ALT_SDMMC_UHS_REG_DDR_REG_11_MSB 27
13461 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_11 register field. */
13462 #define ALT_SDMMC_UHS_REG_DDR_REG_11_WIDTH 1
13463 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_11 register field value. */
13464 #define ALT_SDMMC_UHS_REG_DDR_REG_11_SET_MSK 0x08000000
13465 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_11 register field value. */
13466 #define ALT_SDMMC_UHS_REG_DDR_REG_11_CLR_MSK 0xf7ffffff
13467 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_11 register field. */
13468 #define ALT_SDMMC_UHS_REG_DDR_REG_11_RESET 0x0
13469 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_11 field value from a register. */
13470 #define ALT_SDMMC_UHS_REG_DDR_REG_11_GET(value) (((value) & 0x08000000) >> 27)
13471 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_11 register field value suitable for setting the register. */
13472 #define ALT_SDMMC_UHS_REG_DDR_REG_11_SET(value) (((value) << 27) & 0x08000000)
13473 
13474 /*
13475  * Field : DDR_REG_12
13476  *
13477  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13478  * transfer.
13479  *
13480  * 0 Non-DDR mode
13481  *
13482  * 1 DDR mode
13483  *
13484  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13485  * so on.
13486  *
13487  * Field Enumeration Values:
13488  *
13489  * Enum | Value | Description
13490  * :----------------------------------------|:------|:--------------------------------------------
13491  * ALT_SDMMC_UHS_REG_DDR_REG_12_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13492  * ALT_SDMMC_UHS_REG_DDR_REG_12_E_ENABLED | 0x1 | DDR Mode
13493  *
13494  * Field Access Macros:
13495  *
13496  */
13497 /*
13498  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_12
13499  *
13500  * Non DDR Mode;clear these bits in HS400 Mode
13501  */
13502 #define ALT_SDMMC_UHS_REG_DDR_REG_12_E_DISABLED 0x0
13503 /*
13504  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_12
13505  *
13506  * DDR Mode
13507  */
13508 #define ALT_SDMMC_UHS_REG_DDR_REG_12_E_ENABLED 0x1
13509 
13510 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_12 register field. */
13511 #define ALT_SDMMC_UHS_REG_DDR_REG_12_LSB 28
13512 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_12 register field. */
13513 #define ALT_SDMMC_UHS_REG_DDR_REG_12_MSB 28
13514 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_12 register field. */
13515 #define ALT_SDMMC_UHS_REG_DDR_REG_12_WIDTH 1
13516 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_12 register field value. */
13517 #define ALT_SDMMC_UHS_REG_DDR_REG_12_SET_MSK 0x10000000
13518 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_12 register field value. */
13519 #define ALT_SDMMC_UHS_REG_DDR_REG_12_CLR_MSK 0xefffffff
13520 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_12 register field. */
13521 #define ALT_SDMMC_UHS_REG_DDR_REG_12_RESET 0x0
13522 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_12 field value from a register. */
13523 #define ALT_SDMMC_UHS_REG_DDR_REG_12_GET(value) (((value) & 0x10000000) >> 28)
13524 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_12 register field value suitable for setting the register. */
13525 #define ALT_SDMMC_UHS_REG_DDR_REG_12_SET(value) (((value) << 28) & 0x10000000)
13526 
13527 /*
13528  * Field : DDR_REG_13
13529  *
13530  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13531  * transfer.
13532  *
13533  * 0 Non-DDR mode
13534  *
13535  * 1 DDR mode
13536  *
13537  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13538  * so on.
13539  *
13540  * Field Enumeration Values:
13541  *
13542  * Enum | Value | Description
13543  * :----------------------------------------|:------|:--------------------------------------------
13544  * ALT_SDMMC_UHS_REG_DDR_REG_13_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13545  * ALT_SDMMC_UHS_REG_DDR_REG_13_E_ENABLED | 0x1 | DDR Mode
13546  *
13547  * Field Access Macros:
13548  *
13549  */
13550 /*
13551  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_13
13552  *
13553  * Non DDR Mode;clear these bits in HS400 Mode
13554  */
13555 #define ALT_SDMMC_UHS_REG_DDR_REG_13_E_DISABLED 0x0
13556 /*
13557  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_13
13558  *
13559  * DDR Mode
13560  */
13561 #define ALT_SDMMC_UHS_REG_DDR_REG_13_E_ENABLED 0x1
13562 
13563 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_13 register field. */
13564 #define ALT_SDMMC_UHS_REG_DDR_REG_13_LSB 29
13565 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_13 register field. */
13566 #define ALT_SDMMC_UHS_REG_DDR_REG_13_MSB 29
13567 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_13 register field. */
13568 #define ALT_SDMMC_UHS_REG_DDR_REG_13_WIDTH 1
13569 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_13 register field value. */
13570 #define ALT_SDMMC_UHS_REG_DDR_REG_13_SET_MSK 0x20000000
13571 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_13 register field value. */
13572 #define ALT_SDMMC_UHS_REG_DDR_REG_13_CLR_MSK 0xdfffffff
13573 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_13 register field. */
13574 #define ALT_SDMMC_UHS_REG_DDR_REG_13_RESET 0x0
13575 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_13 field value from a register. */
13576 #define ALT_SDMMC_UHS_REG_DDR_REG_13_GET(value) (((value) & 0x20000000) >> 29)
13577 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_13 register field value suitable for setting the register. */
13578 #define ALT_SDMMC_UHS_REG_DDR_REG_13_SET(value) (((value) << 29) & 0x20000000)
13579 
13580 /*
13581  * Field : DDR_REG_14
13582  *
13583  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13584  * transfer.
13585  *
13586  * 0 Non-DDR mode
13587  *
13588  * 1 DDR mode
13589  *
13590  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13591  * so on.
13592  *
13593  * Field Enumeration Values:
13594  *
13595  * Enum | Value | Description
13596  * :----------------------------------------|:------|:--------------------------------------------
13597  * ALT_SDMMC_UHS_REG_DDR_REG_14_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13598  * ALT_SDMMC_UHS_REG_DDR_REG_14_E_ENABLED | 0x1 | DDR Mode
13599  *
13600  * Field Access Macros:
13601  *
13602  */
13603 /*
13604  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_14
13605  *
13606  * Non DDR Mode;clear these bits in HS400 Mode
13607  */
13608 #define ALT_SDMMC_UHS_REG_DDR_REG_14_E_DISABLED 0x0
13609 /*
13610  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_14
13611  *
13612  * DDR Mode
13613  */
13614 #define ALT_SDMMC_UHS_REG_DDR_REG_14_E_ENABLED 0x1
13615 
13616 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_14 register field. */
13617 #define ALT_SDMMC_UHS_REG_DDR_REG_14_LSB 30
13618 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_14 register field. */
13619 #define ALT_SDMMC_UHS_REG_DDR_REG_14_MSB 30
13620 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_14 register field. */
13621 #define ALT_SDMMC_UHS_REG_DDR_REG_14_WIDTH 1
13622 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_14 register field value. */
13623 #define ALT_SDMMC_UHS_REG_DDR_REG_14_SET_MSK 0x40000000
13624 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_14 register field value. */
13625 #define ALT_SDMMC_UHS_REG_DDR_REG_14_CLR_MSK 0xbfffffff
13626 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_14 register field. */
13627 #define ALT_SDMMC_UHS_REG_DDR_REG_14_RESET 0x0
13628 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_14 field value from a register. */
13629 #define ALT_SDMMC_UHS_REG_DDR_REG_14_GET(value) (((value) & 0x40000000) >> 30)
13630 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_14 register field value suitable for setting the register. */
13631 #define ALT_SDMMC_UHS_REG_DDR_REG_14_SET(value) (((value) << 30) & 0x40000000)
13632 
13633 /*
13634  * Field : DDR_REG_15
13635  *
13636  * DDR mode. These bits indicate DDR mode of operation to the core for the data
13637  * transfer.
13638  *
13639  * 0 Non-DDR mode
13640  *
13641  * 1 DDR mode
13642  *
13643  * UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and
13644  * so on.
13645  *
13646  * Field Enumeration Values:
13647  *
13648  * Enum | Value | Description
13649  * :----------------------------------------|:------|:--------------------------------------------
13650  * ALT_SDMMC_UHS_REG_DDR_REG_15_E_DISABLED | 0x0 | Non DDR Mode;clear these bits in HS400 Mode
13651  * ALT_SDMMC_UHS_REG_DDR_REG_15_E_ENABLED | 0x1 | DDR Mode
13652  *
13653  * Field Access Macros:
13654  *
13655  */
13656 /*
13657  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_15
13658  *
13659  * Non DDR Mode;clear these bits in HS400 Mode
13660  */
13661 #define ALT_SDMMC_UHS_REG_DDR_REG_15_E_DISABLED 0x0
13662 /*
13663  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG_15
13664  *
13665  * DDR Mode
13666  */
13667 #define ALT_SDMMC_UHS_REG_DDR_REG_15_E_ENABLED 0x1
13668 
13669 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_15 register field. */
13670 #define ALT_SDMMC_UHS_REG_DDR_REG_15_LSB 31
13671 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG_15 register field. */
13672 #define ALT_SDMMC_UHS_REG_DDR_REG_15_MSB 31
13673 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG_15 register field. */
13674 #define ALT_SDMMC_UHS_REG_DDR_REG_15_WIDTH 1
13675 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG_15 register field value. */
13676 #define ALT_SDMMC_UHS_REG_DDR_REG_15_SET_MSK 0x80000000
13677 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG_15 register field value. */
13678 #define ALT_SDMMC_UHS_REG_DDR_REG_15_CLR_MSK 0x7fffffff
13679 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG_15 register field. */
13680 #define ALT_SDMMC_UHS_REG_DDR_REG_15_RESET 0x0
13681 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG_15 field value from a register. */
13682 #define ALT_SDMMC_UHS_REG_DDR_REG_15_GET(value) (((value) & 0x80000000) >> 31)
13683 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG_15 register field value suitable for setting the register. */
13684 #define ALT_SDMMC_UHS_REG_DDR_REG_15_SET(value) (((value) << 31) & 0x80000000)
13685 
13686 #ifndef __ASSEMBLY__
13687 /*
13688  * WARNING: The C register and register group struct declarations are provided for
13689  * convenience and illustrative purposes. They should, however, be used with
13690  * caution as the C language standard provides no guarantees about the alignment or
13691  * atomicity of device memory accesses. The recommended practice for coding device
13692  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13693  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13694  * alt_write_dword() functions for 64 bit registers.
13695  *
13696  * The struct declaration for register ALT_SDMMC_UHS_REG.
13697  */
13698 struct ALT_SDMMC_UHS_REG_s
13699 {
13700  volatile uint32_t VOLT_REG_0 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_0 */
13701  volatile uint32_t VOLT_REG_1 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_1 */
13702  volatile uint32_t VOLT_REG_2 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_2 */
13703  volatile uint32_t VOLT_REG_3 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_3 */
13704  volatile uint32_t VOLT_REG_4 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_4 */
13705  volatile uint32_t VOLT_REG_5 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_5 */
13706  volatile uint32_t VOLT_REG_6 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_6 */
13707  volatile uint32_t VOLT_REG_7 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_7 */
13708  volatile uint32_t VOLT_REG_8 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_8 */
13709  volatile uint32_t VOLT_REG_9 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_9 */
13710  volatile uint32_t VOLT_REG_10 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_10 */
13711  volatile uint32_t VOLT_REG_11 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_11 */
13712  volatile uint32_t VOLT_REG_12 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_12 */
13713  volatile uint32_t VOLT_REG_13 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_13 */
13714  volatile uint32_t VOLT_REG_14 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_14 */
13715  volatile uint32_t VOLT_REG_15 : 1; /* ALT_SDMMC_UHS_REG_VOLT_REG_15 */
13716  volatile uint32_t DDR_REG_0 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_0 */
13717  volatile uint32_t DDR_REG_1 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_1 */
13718  volatile uint32_t DDR_REG_2 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_2 */
13719  volatile uint32_t DDR_REG_3 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_3 */
13720  volatile uint32_t DDR_REG_4 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_4 */
13721  volatile uint32_t DDR_REG_5 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_5 */
13722  volatile uint32_t DDR_REG_6 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_6 */
13723  volatile uint32_t DDR_REG_7 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_7 */
13724  volatile uint32_t DDR_REG_8 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_8 */
13725  volatile uint32_t DDR_REG_9 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_9 */
13726  volatile uint32_t DDR_REG_10 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_10 */
13727  volatile uint32_t DDR_REG_11 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_11 */
13728  volatile uint32_t DDR_REG_12 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_12 */
13729  volatile uint32_t DDR_REG_13 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_13 */
13730  volatile uint32_t DDR_REG_14 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_14 */
13731  volatile uint32_t DDR_REG_15 : 1; /* ALT_SDMMC_UHS_REG_DDR_REG_15 */
13732 };
13733 
13734 /* The typedef declaration for register ALT_SDMMC_UHS_REG. */
13735 typedef struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
13736 #endif /* __ASSEMBLY__ */
13737 
13738 /* The reset value of the ALT_SDMMC_UHS_REG register. */
13739 #define ALT_SDMMC_UHS_REG_RESET 0x00000000
13740 /* The byte offset of the ALT_SDMMC_UHS_REG register from the beginning of the component. */
13741 #define ALT_SDMMC_UHS_REG_OFST 0x74
13742 /* The address of the ALT_SDMMC_UHS_REG register. */
13743 #define ALT_SDMMC_UHS_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_UHS_REG_OFST))
13744 
13745 /*
13746  * Register : Hardware Reset Register - RST_n
13747  *
13748  * Name: H/W Reset
13749  *
13750  * Size: 32 bits
13751  *
13752  * Address Offset: 0x78
13753  *
13754  * Read/write access: write/read
13755  *
13756  * Register Layout
13757  *
13758  * Bits | Access | Reset | Description
13759  * :-------|:-------|:------|:----------------------------
13760  * [0] | RW | 0x1 | ALT_SDMMC_RST_N_CARD0_RESET
13761  * [31:1] | ??? | 0x0 | *UNDEFINED*
13762  *
13763  */
13764 /*
13765  * Field : CARD0_RESET
13766  *
13767  * Hardware reset.
13768  *
13769  * 1 Active mode
13770  *
13771  * 0 Reset
13772  *
13773  * These bits cause the cards to enter pre-idle state, which requires them to be
13774  * re-initialized.
13775  *
13776  * CARD_RESET[0] should be set to 1'b0 to reset card number 0
13777  *
13778  * CARD_RESET[15] should be set to 1'b0 to reset card number 15.
13779  *
13780  * The number of bits implemented is restricted to NUM_CARDS.
13781  *
13782  * Field Enumeration Values:
13783  *
13784  * Enum | Value | Description
13785  * :---------------------------------------|:------|:---------------
13786  * ALT_SDMMC_RST_N_CARD0_RESET_E_ASSERT | 0x0 | Reset
13787  * ALT_SDMMC_RST_N_CARD0_RESET_E_DEASSERT | 0x1 | 1 Active mode
13788  *
13789  * Field Access Macros:
13790  *
13791  */
13792 /*
13793  * Enumerated value for register field ALT_SDMMC_RST_N_CARD0_RESET
13794  *
13795  * Reset
13796  */
13797 #define ALT_SDMMC_RST_N_CARD0_RESET_E_ASSERT 0x0
13798 /*
13799  * Enumerated value for register field ALT_SDMMC_RST_N_CARD0_RESET
13800  *
13801  * 1 Active mode
13802  */
13803 #define ALT_SDMMC_RST_N_CARD0_RESET_E_DEASSERT 0x1
13804 
13805 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RST_N_CARD0_RESET register field. */
13806 #define ALT_SDMMC_RST_N_CARD0_RESET_LSB 0
13807 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RST_N_CARD0_RESET register field. */
13808 #define ALT_SDMMC_RST_N_CARD0_RESET_MSB 0
13809 /* The width in bits of the ALT_SDMMC_RST_N_CARD0_RESET register field. */
13810 #define ALT_SDMMC_RST_N_CARD0_RESET_WIDTH 1
13811 /* The mask used to set the ALT_SDMMC_RST_N_CARD0_RESET register field value. */
13812 #define ALT_SDMMC_RST_N_CARD0_RESET_SET_MSK 0x00000001
13813 /* The mask used to clear the ALT_SDMMC_RST_N_CARD0_RESET register field value. */
13814 #define ALT_SDMMC_RST_N_CARD0_RESET_CLR_MSK 0xfffffffe
13815 /* The reset value of the ALT_SDMMC_RST_N_CARD0_RESET register field. */
13816 #define ALT_SDMMC_RST_N_CARD0_RESET_RESET 0x1
13817 /* Extracts the ALT_SDMMC_RST_N_CARD0_RESET field value from a register. */
13818 #define ALT_SDMMC_RST_N_CARD0_RESET_GET(value) (((value) & 0x00000001) >> 0)
13819 /* Produces a ALT_SDMMC_RST_N_CARD0_RESET register field value suitable for setting the register. */
13820 #define ALT_SDMMC_RST_N_CARD0_RESET_SET(value) (((value) << 0) & 0x00000001)
13821 
13822 #ifndef __ASSEMBLY__
13823 /*
13824  * WARNING: The C register and register group struct declarations are provided for
13825  * convenience and illustrative purposes. They should, however, be used with
13826  * caution as the C language standard provides no guarantees about the alignment or
13827  * atomicity of device memory accesses. The recommended practice for coding device
13828  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13829  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13830  * alt_write_dword() functions for 64 bit registers.
13831  *
13832  * The struct declaration for register ALT_SDMMC_RST_N.
13833  */
13834 struct ALT_SDMMC_RST_N_s
13835 {
13836  volatile uint32_t CARD0_RESET : 1; /* ALT_SDMMC_RST_N_CARD0_RESET */
13837  uint32_t : 31; /* *UNDEFINED* */
13838 };
13839 
13840 /* The typedef declaration for register ALT_SDMMC_RST_N. */
13841 typedef struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
13842 #endif /* __ASSEMBLY__ */
13843 
13844 /* The reset value of the ALT_SDMMC_RST_N register. */
13845 #define ALT_SDMMC_RST_N_RESET 0x00000001
13846 /* The byte offset of the ALT_SDMMC_RST_N register from the beginning of the component. */
13847 #define ALT_SDMMC_RST_N_OFST 0x78
13848 /* The address of the ALT_SDMMC_RST_N register. */
13849 #define ALT_SDMMC_RST_N_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RST_N_OFST))
13850 
13851 /*
13852  * Register : Bus Mode Register - BMOD
13853  *
13854  * Name: Bus Mode Register
13855  *
13856  * Size: 32 bits
13857  *
13858  * Address Offset: 0x80
13859  *
13860  * Read/Write access: read/write
13861  *
13862  * Register Layout
13863  *
13864  * Bits | Access | Reset | Description
13865  * :--------|:-------|:------|:-------------------
13866  * [0] | RW | 0x0 | ALT_SDMMC_BMOD_SWR
13867  * [1] | RW | 0x0 | ALT_SDMMC_BMOD_FB
13868  * [6:2] | RW | 0x0 | ALT_SDMMC_BMOD_DSL
13869  * [7] | RW | 0x0 | ALT_SDMMC_BMOD_DE
13870  * [10:8] | R | 0x0 | ALT_SDMMC_BMOD_PBL
13871  * [31:11] | ??? | 0x0 | *UNDEFINED*
13872  *
13873  */
13874 /*
13875  * Field : SWR
13876  *
13877  * Software Reset.When set,the DMA Controller resets all its internal registers.
13878  *
13879  * SWR is read/write. It is automatically cleared after 1 clock cycle.
13880  *
13881  * Field Enumeration Values:
13882  *
13883  * Enum | Value | Description
13884  * :---------------------------|:------|:---------------------
13885  * ALT_SDMMC_BMOD_SWR_E_FALSE | 0x0 | No change
13886  * ALT_SDMMC_BMOD_SWR_E_TRUE | 0x1 | DMA controller reset
13887  *
13888  * Field Access Macros:
13889  *
13890  */
13891 /*
13892  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
13893  *
13894  * No change
13895  */
13896 #define ALT_SDMMC_BMOD_SWR_E_FALSE 0x0
13897 /*
13898  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
13899  *
13900  * DMA controller reset
13901  */
13902 #define ALT_SDMMC_BMOD_SWR_E_TRUE 0x1
13903 
13904 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_SWR register field. */
13905 #define ALT_SDMMC_BMOD_SWR_LSB 0
13906 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_SWR register field. */
13907 #define ALT_SDMMC_BMOD_SWR_MSB 0
13908 /* The width in bits of the ALT_SDMMC_BMOD_SWR register field. */
13909 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
13910 /* The mask used to set the ALT_SDMMC_BMOD_SWR register field value. */
13911 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
13912 /* The mask used to clear the ALT_SDMMC_BMOD_SWR register field value. */
13913 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
13914 /* The reset value of the ALT_SDMMC_BMOD_SWR register field. */
13915 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
13916 /* Extracts the ALT_SDMMC_BMOD_SWR field value from a register. */
13917 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
13918 /* Produces a ALT_SDMMC_BMOD_SWR register field value suitable for setting the register. */
13919 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
13920 
13921 /*
13922  * Field : FB
13923  *
13924  * Fixed Burst. Controls whether the AHB Master interface performs fixed burst
13925  * transfers or not. When set,the AHB will use only SINGLE, INCR4, INCR8 or
13926  *
13927  * INCR16 during start of normal burst transfers.When reset,the AHB will use SINGLE
13928  * and INCR burst transfer operations.
13929  *
13930  * FB is read/write.
13931  *
13932  * Field Enumeration Values:
13933  *
13934  * Enum | Value | Description
13935  * :--------------------------|:------|:------------------------------------------
13936  * ALT_SDMMC_BMOD_FB_E_FALSE | 0x0 | SINGLE and INCR burst transfer
13937  * ALT_SDMMC_BMOD_FB_E_TRUE | 0x1 | SINGLE, INCR4, INCR8, or INCR16 transfers
13938  *
13939  * Field Access Macros:
13940  *
13941  */
13942 /*
13943  * Enumerated value for register field ALT_SDMMC_BMOD_FB
13944  *
13945  * SINGLE and INCR burst transfer
13946  */
13947 #define ALT_SDMMC_BMOD_FB_E_FALSE 0x0
13948 /*
13949  * Enumerated value for register field ALT_SDMMC_BMOD_FB
13950  *
13951  * SINGLE, INCR4, INCR8, or INCR16 transfers
13952  */
13953 #define ALT_SDMMC_BMOD_FB_E_TRUE 0x1
13954 
13955 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_FB register field. */
13956 #define ALT_SDMMC_BMOD_FB_LSB 1
13957 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_FB register field. */
13958 #define ALT_SDMMC_BMOD_FB_MSB 1
13959 /* The width in bits of the ALT_SDMMC_BMOD_FB register field. */
13960 #define ALT_SDMMC_BMOD_FB_WIDTH 1
13961 /* The mask used to set the ALT_SDMMC_BMOD_FB register field value. */
13962 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
13963 /* The mask used to clear the ALT_SDMMC_BMOD_FB register field value. */
13964 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
13965 /* The reset value of the ALT_SDMMC_BMOD_FB register field. */
13966 #define ALT_SDMMC_BMOD_FB_RESET 0x0
13967 /* Extracts the ALT_SDMMC_BMOD_FB field value from a register. */
13968 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
13969 /* Produces a ALT_SDMMC_BMOD_FB register field value suitable for setting the register. */
13970 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
13971 
13972 /*
13973  * Field : DSL
13974  *
13975  * Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on
13976  * 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable
13977  * only for dual buffer structure.
13978  *
13979  * DSL is read/write.
13980  *
13981  * Field Access Macros:
13982  *
13983  */
13984 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DSL register field. */
13985 #define ALT_SDMMC_BMOD_DSL_LSB 2
13986 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DSL register field. */
13987 #define ALT_SDMMC_BMOD_DSL_MSB 6
13988 /* The width in bits of the ALT_SDMMC_BMOD_DSL register field. */
13989 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
13990 /* The mask used to set the ALT_SDMMC_BMOD_DSL register field value. */
13991 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
13992 /* The mask used to clear the ALT_SDMMC_BMOD_DSL register field value. */
13993 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
13994 /* The reset value of the ALT_SDMMC_BMOD_DSL register field. */
13995 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
13996 /* Extracts the ALT_SDMMC_BMOD_DSL field value from a register. */
13997 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
13998 /* Produces a ALT_SDMMC_BMOD_DSL register field value suitable for setting the register. */
13999 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
14000 
14001 /*
14002  * Field : DE
14003  *
14004  * IDMAC Enable. When set, the IDMAC is enabled.
14005  *
14006  * DE is read/write.
14007  *
14008  * Field Enumeration Values:
14009  *
14010  * Enum | Value | Description
14011  * :-----------------------------|:------|:-------------------------------
14012  * ALT_SDMMC_BMOD_DE_E_DISABLED | 0x0 | IDMAC is disabled
14013  * ALT_SDMMC_BMOD_DE_E_ENABLED | 0x1 | When set, the IDMAC is enabled
14014  *
14015  * Field Access Macros:
14016  *
14017  */
14018 /*
14019  * Enumerated value for register field ALT_SDMMC_BMOD_DE
14020  *
14021  * IDMAC is disabled
14022  */
14023 #define ALT_SDMMC_BMOD_DE_E_DISABLED 0x0
14024 /*
14025  * Enumerated value for register field ALT_SDMMC_BMOD_DE
14026  *
14027  * When set, the IDMAC is enabled
14028  */
14029 #define ALT_SDMMC_BMOD_DE_E_ENABLED 0x1
14030 
14031 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DE register field. */
14032 #define ALT_SDMMC_BMOD_DE_LSB 7
14033 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DE register field. */
14034 #define ALT_SDMMC_BMOD_DE_MSB 7
14035 /* The width in bits of the ALT_SDMMC_BMOD_DE register field. */
14036 #define ALT_SDMMC_BMOD_DE_WIDTH 1
14037 /* The mask used to set the ALT_SDMMC_BMOD_DE register field value. */
14038 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
14039 /* The mask used to clear the ALT_SDMMC_BMOD_DE register field value. */
14040 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
14041 /* The reset value of the ALT_SDMMC_BMOD_DE register field. */
14042 #define ALT_SDMMC_BMOD_DE_RESET 0x0
14043 /* Extracts the ALT_SDMMC_BMOD_DE field value from a register. */
14044 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
14045 /* Produces a ALT_SDMMC_BMOD_DE register field value suitable for setting the register. */
14046 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
14047 
14048 /*
14049  * Field : PBL
14050  *
14051  * Programmable Burst Length. These bits indicate the maximum number of beats to be
14052  * performed in one IDMAC transaction. The IDMAC will always attempt to burst as
14053  * specified in PBL each time it starts a Burst transfer on the host bus. The
14054  * permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the
14055  * mirror of MSIZE of FIFOTH register. In order to change this value, write the
14056  * required value
14057  *
14058  * to FIFOTH register. This is an encode value as follows.
14059  *
14060  * 000 1 transfers
14061  *
14062  * 001 4 transfers
14063  *
14064  * 010 8 transfers
14065  *
14066  * 011 16 transfers
14067  *
14068  * 100 32 transfers
14069  *
14070  * 101 64 transfers
14071  *
14072  * 110 128 transfers
14073  *
14074  * 111 256 transfers
14075  *
14076  * Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH.
14077  *
14078  * PBL is a read-only value and is applicable only for Data Access; it does not
14079  * apply to descriptor accesses.
14080  *
14081  * Field Enumeration Values:
14082  *
14083  * Enum | Value | Description
14084  * :-------------------------------|:------|:-------------
14085  * ALT_SDMMC_BMOD_PBL_E_BURST_1 | 0x0 | Burst of 1
14086  * ALT_SDMMC_BMOD_PBL_E_BURST_4 | 0x1 | Burst of 4
14087  * ALT_SDMMC_BMOD_PBL_E_BURST_8 | 0x2 | Burst of 8
14088  * ALT_SDMMC_BMOD_PBL_E_BURST_16 | 0x3 | Burst of 16
14089  * ALT_SDMMC_BMOD_PBL_E_BURST_32 | 0x4 | Burst of 32
14090  * ALT_SDMMC_BMOD_PBL_E_BURST_64 | 0x5 | Burst of 64
14091  * ALT_SDMMC_BMOD_PBL_E_BURST_128 | 0x6 | Burst of 128
14092  * ALT_SDMMC_BMOD_PBL_E_BURST_256 | 0x7 | Burst of 256
14093  *
14094  * Field Access Macros:
14095  *
14096  */
14097 /*
14098  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14099  *
14100  * Burst of 1
14101  */
14102 #define ALT_SDMMC_BMOD_PBL_E_BURST_1 0x0
14103 /*
14104  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14105  *
14106  * Burst of 4
14107  */
14108 #define ALT_SDMMC_BMOD_PBL_E_BURST_4 0x1
14109 /*
14110  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14111  *
14112  * Burst of 8
14113  */
14114 #define ALT_SDMMC_BMOD_PBL_E_BURST_8 0x2
14115 /*
14116  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14117  *
14118  * Burst of 16
14119  */
14120 #define ALT_SDMMC_BMOD_PBL_E_BURST_16 0x3
14121 /*
14122  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14123  *
14124  * Burst of 32
14125  */
14126 #define ALT_SDMMC_BMOD_PBL_E_BURST_32 0x4
14127 /*
14128  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14129  *
14130  * Burst of 64
14131  */
14132 #define ALT_SDMMC_BMOD_PBL_E_BURST_64 0x5
14133 /*
14134  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14135  *
14136  * Burst of 128
14137  */
14138 #define ALT_SDMMC_BMOD_PBL_E_BURST_128 0x6
14139 /*
14140  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
14141  *
14142  * Burst of 256
14143  */
14144 #define ALT_SDMMC_BMOD_PBL_E_BURST_256 0x7
14145 
14146 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_PBL register field. */
14147 #define ALT_SDMMC_BMOD_PBL_LSB 8
14148 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_PBL register field. */
14149 #define ALT_SDMMC_BMOD_PBL_MSB 10
14150 /* The width in bits of the ALT_SDMMC_BMOD_PBL register field. */
14151 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
14152 /* The mask used to set the ALT_SDMMC_BMOD_PBL register field value. */
14153 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
14154 /* The mask used to clear the ALT_SDMMC_BMOD_PBL register field value. */
14155 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
14156 /* The reset value of the ALT_SDMMC_BMOD_PBL register field. */
14157 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
14158 /* Extracts the ALT_SDMMC_BMOD_PBL field value from a register. */
14159 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
14160 /* Produces a ALT_SDMMC_BMOD_PBL register field value suitable for setting the register. */
14161 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
14162 
14163 #ifndef __ASSEMBLY__
14164 /*
14165  * WARNING: The C register and register group struct declarations are provided for
14166  * convenience and illustrative purposes. They should, however, be used with
14167  * caution as the C language standard provides no guarantees about the alignment or
14168  * atomicity of device memory accesses. The recommended practice for coding device
14169  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14170  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14171  * alt_write_dword() functions for 64 bit registers.
14172  *
14173  * The struct declaration for register ALT_SDMMC_BMOD.
14174  */
14175 struct ALT_SDMMC_BMOD_s
14176 {
14177  volatile uint32_t SWR : 1; /* ALT_SDMMC_BMOD_SWR */
14178  volatile uint32_t FB : 1; /* ALT_SDMMC_BMOD_FB */
14179  volatile uint32_t DSL : 5; /* ALT_SDMMC_BMOD_DSL */
14180  volatile uint32_t DE : 1; /* ALT_SDMMC_BMOD_DE */
14181  const volatile uint32_t PBL : 3; /* ALT_SDMMC_BMOD_PBL */
14182  uint32_t : 21; /* *UNDEFINED* */
14183 };
14184 
14185 /* The typedef declaration for register ALT_SDMMC_BMOD. */
14186 typedef struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
14187 #endif /* __ASSEMBLY__ */
14188 
14189 /* The reset value of the ALT_SDMMC_BMOD register. */
14190 #define ALT_SDMMC_BMOD_RESET 0x00000000
14191 /* The byte offset of the ALT_SDMMC_BMOD register from the beginning of the component. */
14192 #define ALT_SDMMC_BMOD_OFST 0x80
14193 /* The address of the ALT_SDMMC_BMOD register. */
14194 #define ALT_SDMMC_BMOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BMOD_OFST))
14195 
14196 /*
14197  * Register : Poll Demand Register - PLDMND
14198  *
14199  * Name: Poll Demand Register
14200  *
14201  * Size: 32 bits
14202  *
14203  * Address Offset: 0x84
14204  *
14205  * Read/Write access: write
14206  *
14207  * Register Layout
14208  *
14209  * Bits | Access | Reset | Description
14210  * :-------|:-------|:------|:--------------------
14211  * [31:0] | W | 0x0 | ALT_SDMMC_PLDMND_PD
14212  *
14213  */
14214 /*
14215  * Field : PD
14216  *
14217  * Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the
14218  * Suspend state. The host needs to write any value into this register for the
14219  * IDMAC FSM to resume normal
14220  *
14221  * descriptor fetch operation. This is a write only register.
14222  *
14223  * PD bit is write-only.
14224  *
14225  * Field Access Macros:
14226  *
14227  */
14228 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PLDMND_PD register field. */
14229 #define ALT_SDMMC_PLDMND_PD_LSB 0
14230 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PLDMND_PD register field. */
14231 #define ALT_SDMMC_PLDMND_PD_MSB 31
14232 /* The width in bits of the ALT_SDMMC_PLDMND_PD register field. */
14233 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
14234 /* The mask used to set the ALT_SDMMC_PLDMND_PD register field value. */
14235 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
14236 /* The mask used to clear the ALT_SDMMC_PLDMND_PD register field value. */
14237 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
14238 /* The reset value of the ALT_SDMMC_PLDMND_PD register field. */
14239 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
14240 /* Extracts the ALT_SDMMC_PLDMND_PD field value from a register. */
14241 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
14242 /* Produces a ALT_SDMMC_PLDMND_PD register field value suitable for setting the register. */
14243 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
14244 
14245 #ifndef __ASSEMBLY__
14246 /*
14247  * WARNING: The C register and register group struct declarations are provided for
14248  * convenience and illustrative purposes. They should, however, be used with
14249  * caution as the C language standard provides no guarantees about the alignment or
14250  * atomicity of device memory accesses. The recommended practice for coding device
14251  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14252  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14253  * alt_write_dword() functions for 64 bit registers.
14254  *
14255  * The struct declaration for register ALT_SDMMC_PLDMND.
14256  */
14257 struct ALT_SDMMC_PLDMND_s
14258 {
14259  volatile uint32_t PD : 32; /* ALT_SDMMC_PLDMND_PD */
14260 };
14261 
14262 /* The typedef declaration for register ALT_SDMMC_PLDMND. */
14263 typedef struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
14264 #endif /* __ASSEMBLY__ */
14265 
14266 /* The reset value of the ALT_SDMMC_PLDMND register. */
14267 #define ALT_SDMMC_PLDMND_RESET 0x00000000
14268 /* The byte offset of the ALT_SDMMC_PLDMND register from the beginning of the component. */
14269 #define ALT_SDMMC_PLDMND_OFST 0x84
14270 /* The address of the ALT_SDMMC_PLDMND register. */
14271 #define ALT_SDMMC_PLDMND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_PLDMND_OFST))
14272 
14273 /*
14274  * Register : Descriptor List Base Address Register - DBADDR
14275  *
14276  * Name: Descriptor List Base Address Register
14277  *
14278  * Size: 32 bits
14279  *
14280  * Address Offset: 0x88
14281  *
14282  * Read/Write access: read/write
14283  *
14284  * Register Layout
14285  *
14286  * Bits | Access | Reset | Description
14287  * :-------|:-------|:------|:---------------------
14288  * [31:0] | RW | 0x0 | ALT_SDMMC_DBADDR_SDL
14289  *
14290  */
14291 /*
14292  * Field : SDL
14293  *
14294  * Start of Descriptor List. Contains the base address of the First Descriptor.
14295  *
14296  * The LSB bits [0/1/2:0] for 16/32/64-bit bus-width) are ignored and taken as all-
14297  * zero by the IDMAC internally. Hence these LSB bits are read-only.
14298  *
14299  * Field Access Macros:
14300  *
14301  */
14302 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
14303 #define ALT_SDMMC_DBADDR_SDL_LSB 0
14304 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
14305 #define ALT_SDMMC_DBADDR_SDL_MSB 31
14306 /* The width in bits of the ALT_SDMMC_DBADDR_SDL register field. */
14307 #define ALT_SDMMC_DBADDR_SDL_WIDTH 32
14308 /* The mask used to set the ALT_SDMMC_DBADDR_SDL register field value. */
14309 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xffffffff
14310 /* The mask used to clear the ALT_SDMMC_DBADDR_SDL register field value. */
14311 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000000
14312 /* The reset value of the ALT_SDMMC_DBADDR_SDL register field. */
14313 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
14314 /* Extracts the ALT_SDMMC_DBADDR_SDL field value from a register. */
14315 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xffffffff) >> 0)
14316 /* Produces a ALT_SDMMC_DBADDR_SDL register field value suitable for setting the register. */
14317 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 0) & 0xffffffff)
14318 
14319 #ifndef __ASSEMBLY__
14320 /*
14321  * WARNING: The C register and register group struct declarations are provided for
14322  * convenience and illustrative purposes. They should, however, be used with
14323  * caution as the C language standard provides no guarantees about the alignment or
14324  * atomicity of device memory accesses. The recommended practice for coding device
14325  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14326  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14327  * alt_write_dword() functions for 64 bit registers.
14328  *
14329  * The struct declaration for register ALT_SDMMC_DBADDR.
14330  */
14331 struct ALT_SDMMC_DBADDR_s
14332 {
14333  volatile uint32_t SDL : 32; /* ALT_SDMMC_DBADDR_SDL */
14334 };
14335 
14336 /* The typedef declaration for register ALT_SDMMC_DBADDR. */
14337 typedef struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
14338 #endif /* __ASSEMBLY__ */
14339 
14340 /* The reset value of the ALT_SDMMC_DBADDR register. */
14341 #define ALT_SDMMC_DBADDR_RESET 0x00000000
14342 /* The byte offset of the ALT_SDMMC_DBADDR register from the beginning of the component. */
14343 #define ALT_SDMMC_DBADDR_OFST 0x88
14344 /* The address of the ALT_SDMMC_DBADDR register. */
14345 #define ALT_SDMMC_DBADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DBADDR_OFST))
14346 
14347 /*
14348  * Register : Internal DMAC Status Register - IDSTS
14349  *
14350  * Name: Internal DMAC Status Register
14351  *
14352  * Size: 32 bits
14353  *
14354  * Address Offset: 0x8C
14355  *
14356  * Read/Write access: read/write
14357  *
14358  * Register Layout
14359  *
14360  * Bits | Access | Reset | Description
14361  * :--------|:-------|:------|:--------------------
14362  * [0] | RW | 0x0 | ALT_SDMMC_IDSTS_TI
14363  * [1] | RW | 0x0 | ALT_SDMMC_IDSTS_RI
14364  * [2] | RW | 0x0 | ALT_SDMMC_IDSTS_FBE
14365  * [3] | ??? | 0x0 | *UNDEFINED*
14366  * [4] | RW | 0x0 | ALT_SDMMC_IDSTS_DU
14367  * [5] | RW | 0x0 | ALT_SDMMC_IDSTS_CES
14368  * [7:6] | ??? | 0x0 | *UNDEFINED*
14369  * [8] | RW | 0x0 | ALT_SDMMC_IDSTS_NIS
14370  * [9] | RW | 0x0 | ALT_SDMMC_IDSTS_AIS
14371  * [12:10] | R | 0x0 | ALT_SDMMC_IDSTS_EB
14372  * [16:13] | R | 0x0 | ALT_SDMMC_IDSTS_FSM
14373  * [31:17] | ??? | 0x0 | *UNDEFINED*
14374  *
14375  */
14376 /*
14377  * Field : TI
14378  *
14379  * Transmit Interrupt. Indicates that data transmission is finished for a
14380  * descriptor. Writing a '1' clears this bit.
14381  *
14382  * Field Enumeration Values:
14383  *
14384  * Enum | Value | Description
14385  * :---------------------------|:------|:----------------------------
14386  * ALT_SDMMC_IDSTS_TI_E_SET | 0x0 | Transmit Interrupt is set
14387  * ALT_SDMMC_IDSTS_TI_E_CLEAR | 0x1 | Writing a 1 clears this bit
14388  *
14389  * Field Access Macros:
14390  *
14391  */
14392 /*
14393  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
14394  *
14395  * Transmit Interrupt is set
14396  */
14397 #define ALT_SDMMC_IDSTS_TI_E_SET 0x0
14398 /*
14399  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
14400  *
14401  * Writing a 1 clears this bit
14402  */
14403 #define ALT_SDMMC_IDSTS_TI_E_CLEAR 0x1
14404 
14405 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_TI register field. */
14406 #define ALT_SDMMC_IDSTS_TI_LSB 0
14407 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_TI register field. */
14408 #define ALT_SDMMC_IDSTS_TI_MSB 0
14409 /* The width in bits of the ALT_SDMMC_IDSTS_TI register field. */
14410 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
14411 /* The mask used to set the ALT_SDMMC_IDSTS_TI register field value. */
14412 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
14413 /* The mask used to clear the ALT_SDMMC_IDSTS_TI register field value. */
14414 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
14415 /* The reset value of the ALT_SDMMC_IDSTS_TI register field. */
14416 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
14417 /* Extracts the ALT_SDMMC_IDSTS_TI field value from a register. */
14418 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
14419 /* Produces a ALT_SDMMC_IDSTS_TI register field value suitable for setting the register. */
14420 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
14421 
14422 /*
14423  * Field : RI
14424  *
14425  * Receive Interrupt. Indicates the completion of data reception for a descriptor.
14426  * Writing a 1 clears this bit.
14427  *
14428  * Field Enumeration Values:
14429  *
14430  * Enum | Value | Description
14431  * :---------------------------|:------|:----------------------------
14432  * ALT_SDMMC_IDSTS_RI_E_SET | 0x0 | Receive Interrupt is set
14433  * ALT_SDMMC_IDSTS_RI_E_CLEAR | 0x1 | Writing a 1 clears this bit
14434  *
14435  * Field Access Macros:
14436  *
14437  */
14438 /*
14439  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
14440  *
14441  * Receive Interrupt is set
14442  */
14443 #define ALT_SDMMC_IDSTS_RI_E_SET 0x0
14444 /*
14445  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
14446  *
14447  * Writing a 1 clears this bit
14448  */
14449 #define ALT_SDMMC_IDSTS_RI_E_CLEAR 0x1
14450 
14451 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_RI register field. */
14452 #define ALT_SDMMC_IDSTS_RI_LSB 1
14453 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_RI register field. */
14454 #define ALT_SDMMC_IDSTS_RI_MSB 1
14455 /* The width in bits of the ALT_SDMMC_IDSTS_RI register field. */
14456 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
14457 /* The mask used to set the ALT_SDMMC_IDSTS_RI register field value. */
14458 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
14459 /* The mask used to clear the ALT_SDMMC_IDSTS_RI register field value. */
14460 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
14461 /* The reset value of the ALT_SDMMC_IDSTS_RI register field. */
14462 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
14463 /* Extracts the ALT_SDMMC_IDSTS_RI field value from a register. */
14464 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
14465 /* Produces a ALT_SDMMC_IDSTS_RI register field value suitable for setting the register. */
14466 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
14467 
14468 /*
14469  * Field : FBE
14470  *
14471  * Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]).
14472  * When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears
14473  * this bit.
14474  *
14475  * Field Enumeration Values:
14476  *
14477  * Enum | Value | Description
14478  * :----------------------------|:------|:---------------------------------
14479  * ALT_SDMMC_IDSTS_FBE_E_SET | 0x0 | Fatal Bus Error Interrupt is set
14480  * ALT_SDMMC_IDSTS_FBE_E_CLEAR | 0x1 | Writing a 1 clears this bit
14481  *
14482  * Field Access Macros:
14483  *
14484  */
14485 /*
14486  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
14487  *
14488  * Fatal Bus Error Interrupt is set
14489  */
14490 #define ALT_SDMMC_IDSTS_FBE_E_SET 0x0
14491 /*
14492  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
14493  *
14494  * Writing a 1 clears this bit
14495  */
14496 #define ALT_SDMMC_IDSTS_FBE_E_CLEAR 0x1
14497 
14498 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
14499 #define ALT_SDMMC_IDSTS_FBE_LSB 2
14500 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
14501 #define ALT_SDMMC_IDSTS_FBE_MSB 2
14502 /* The width in bits of the ALT_SDMMC_IDSTS_FBE register field. */
14503 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
14504 /* The mask used to set the ALT_SDMMC_IDSTS_FBE register field value. */
14505 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
14506 /* The mask used to clear the ALT_SDMMC_IDSTS_FBE register field value. */
14507 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
14508 /* The reset value of the ALT_SDMMC_IDSTS_FBE register field. */
14509 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
14510 /* Extracts the ALT_SDMMC_IDSTS_FBE field value from a register. */
14511 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
14512 /* Produces a ALT_SDMMC_IDSTS_FBE register field value suitable for setting the register. */
14513 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
14514 
14515 /*
14516  * Field : DU
14517  *
14518  * Descriptor Unavailable Interrupt. This bit is set when the descriptor is
14519  * unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.
14520  *
14521  * Field Enumeration Values:
14522  *
14523  * Enum | Value | Description
14524  * :---------------------------|:------|:----------------------------------------
14525  * ALT_SDMMC_IDSTS_DU_E_SET | 0x0 | Descriptor Unavailable Interrupt is set
14526  * ALT_SDMMC_IDSTS_DU_E_CLEAR | 0x1 | Writing a 1 clears this bit
14527  *
14528  * Field Access Macros:
14529  *
14530  */
14531 /*
14532  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
14533  *
14534  * Descriptor Unavailable Interrupt is set
14535  */
14536 #define ALT_SDMMC_IDSTS_DU_E_SET 0x0
14537 /*
14538  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
14539  *
14540  * Writing a 1 clears this bit
14541  */
14542 #define ALT_SDMMC_IDSTS_DU_E_CLEAR 0x1
14543 
14544 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_DU register field. */
14545 #define ALT_SDMMC_IDSTS_DU_LSB 4
14546 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_DU register field. */
14547 #define ALT_SDMMC_IDSTS_DU_MSB 4
14548 /* The width in bits of the ALT_SDMMC_IDSTS_DU register field. */
14549 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
14550 /* The mask used to set the ALT_SDMMC_IDSTS_DU register field value. */
14551 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
14552 /* The mask used to clear the ALT_SDMMC_IDSTS_DU register field value. */
14553 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
14554 /* The reset value of the ALT_SDMMC_IDSTS_DU register field. */
14555 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
14556 /* Extracts the ALT_SDMMC_IDSTS_DU field value from a register. */
14557 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
14558 /* Produces a ALT_SDMMC_IDSTS_DU register field value suitable for setting the register. */
14559 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
14560 
14561 /*
14562  * Field : CES
14563  *
14564  * Card Error Summary. Indicates the status of the transaction to/from the card;
14565  * also present in RINTSTS. Indicates the logical OR of the following bits:
14566  *
14567  * EBE End Bit Error
14568  *
14569  * RTO Response Timeout/Boot Ack Timeout
14570  *
14571  * RCRC Response CRC
14572  *
14573  * SBE Start Bit Error
14574  *
14575  * DRTO Data Read Timeout/BDS timeout
14576  *
14577  * DCRC Data CRC for Receive
14578  *
14579  * RE Response Error
14580  *
14581  * Writing a 1 clears this bit.
14582  *
14583  * The abort condition of the IDMAC depends on the setting of this CES bit. If the
14584  * CES bit
14585  *
14586  * is enabled, then the IDMAC aborts on a "response error"; however, it will
14587  * not abort if the
14588  *
14589  * CES bit is cleared.
14590  *
14591  * Field Enumeration Values:
14592  *
14593  * Enum | Value | Description
14594  * :----------------------------|:------|:----------------------------
14595  * ALT_SDMMC_IDSTS_CES_E_SET | 0x0 | Card Error Summary is set
14596  * ALT_SDMMC_IDSTS_CES_E_CLEAR | 0x1 | Writing a 1 clears this bit
14597  *
14598  * Field Access Macros:
14599  *
14600  */
14601 /*
14602  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
14603  *
14604  * Card Error Summary is set
14605  */
14606 #define ALT_SDMMC_IDSTS_CES_E_SET 0x0
14607 /*
14608  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
14609  *
14610  * Writing a 1 clears this bit
14611  */
14612 #define ALT_SDMMC_IDSTS_CES_E_CLEAR 0x1
14613 
14614 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_CES register field. */
14615 #define ALT_SDMMC_IDSTS_CES_LSB 5
14616 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_CES register field. */
14617 #define ALT_SDMMC_IDSTS_CES_MSB 5
14618 /* The width in bits of the ALT_SDMMC_IDSTS_CES register field. */
14619 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
14620 /* The mask used to set the ALT_SDMMC_IDSTS_CES register field value. */
14621 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
14622 /* The mask used to clear the ALT_SDMMC_IDSTS_CES register field value. */
14623 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
14624 /* The reset value of the ALT_SDMMC_IDSTS_CES register field. */
14625 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
14626 /* Extracts the ALT_SDMMC_IDSTS_CES field value from a register. */
14627 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
14628 /* Produces a ALT_SDMMC_IDSTS_CES register field value suitable for setting the register. */
14629 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
14630 
14631 /*
14632  * Field : NIS
14633  *
14634  * Normal Interrupt Summary. Logical OR of the following:
14635  *
14636  * IDSTS[0]-Transmit Interrupt
14637  *
14638  * IDSTS[1]-Receive Interrupt
14639  *
14640  * Only unmasked bits affect this bit.
14641  *
14642  * This is a sticky bit and must be cleared each time a corresponding bit that
14643  * causes NIS
14644  *
14645  * to be set is cleared. Writing a 1 clears this bit.
14646  *
14647  * Field Enumeration Values:
14648  *
14649  * Enum | Value | Description
14650  * :----------------------------|:------|:----------------------------------
14651  * ALT_SDMMC_IDSTS_NIS_E_SET | 0x0 | A normal interrupt Summary is set
14652  * ALT_SDMMC_IDSTS_NIS_E_CLEAR | 0x1 | Writing a 1 clears this bit
14653  *
14654  * Field Access Macros:
14655  *
14656  */
14657 /*
14658  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
14659  *
14660  * A normal interrupt Summary is set
14661  */
14662 #define ALT_SDMMC_IDSTS_NIS_E_SET 0x0
14663 /*
14664  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
14665  *
14666  * Writing a 1 clears this bit
14667  */
14668 #define ALT_SDMMC_IDSTS_NIS_E_CLEAR 0x1
14669 
14670 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
14671 #define ALT_SDMMC_IDSTS_NIS_LSB 8
14672 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
14673 #define ALT_SDMMC_IDSTS_NIS_MSB 8
14674 /* The width in bits of the ALT_SDMMC_IDSTS_NIS register field. */
14675 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
14676 /* The mask used to set the ALT_SDMMC_IDSTS_NIS register field value. */
14677 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
14678 /* The mask used to clear the ALT_SDMMC_IDSTS_NIS register field value. */
14679 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
14680 /* The reset value of the ALT_SDMMC_IDSTS_NIS register field. */
14681 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
14682 /* Extracts the ALT_SDMMC_IDSTS_NIS field value from a register. */
14683 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
14684 /* Produces a ALT_SDMMC_IDSTS_NIS register field value suitable for setting the register. */
14685 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
14686 
14687 /*
14688  * Field : AIS
14689  *
14690  * Abnormal Interrupt Summary. Logical OR of the following:
14691  *
14692  * IDSTS[2]-Fatal Bus Interrupt
14693  *
14694  * IDSTS[4]-DU bit Interrupt
14695  *
14696  * Only unmasked bits affect this bit.
14697  *
14698  * This is a sticky bit and must be cleared each time a corresponding bit that
14699  * causes AIS
14700  *
14701  * to be set is cleared. Writing a 1 clears this bit.
14702  *
14703  * Field Enumeration Values:
14704  *
14705  * Enum | Value | Description
14706  * :----------------------------|:------|:------------------------------------
14707  * ALT_SDMMC_IDSTS_AIS_E_SET | 0x0 | A abnormal interrupt Summary is set
14708  * ALT_SDMMC_IDSTS_AIS_E_CLEAR | 0x1 | Writing a 1 clears this bit
14709  *
14710  * Field Access Macros:
14711  *
14712  */
14713 /*
14714  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
14715  *
14716  * A abnormal interrupt Summary is set
14717  */
14718 #define ALT_SDMMC_IDSTS_AIS_E_SET 0x0
14719 /*
14720  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
14721  *
14722  * Writing a 1 clears this bit
14723  */
14724 #define ALT_SDMMC_IDSTS_AIS_E_CLEAR 0x1
14725 
14726 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
14727 #define ALT_SDMMC_IDSTS_AIS_LSB 9
14728 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
14729 #define ALT_SDMMC_IDSTS_AIS_MSB 9
14730 /* The width in bits of the ALT_SDMMC_IDSTS_AIS register field. */
14731 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
14732 /* The mask used to set the ALT_SDMMC_IDSTS_AIS register field value. */
14733 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
14734 /* The mask used to clear the ALT_SDMMC_IDSTS_AIS register field value. */
14735 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
14736 /* The reset value of the ALT_SDMMC_IDSTS_AIS register field. */
14737 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
14738 /* Extracts the ALT_SDMMC_IDSTS_AIS field value from a register. */
14739 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
14740 /* Produces a ALT_SDMMC_IDSTS_AIS register field value suitable for setting the register. */
14741 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
14742 
14743 /*
14744  * Field : EB
14745  *
14746  * Error Bits. Indicates the type of error that caused a Bus Error.
14747  *
14748  * Valid only with Fatal Bus
14749  *
14750  * Error bitIDSTS[2] set. This field does not generate an interrupt.
14751  *
14752  * 3'b001 Host Abort received during transmission
14753  *
14754  * 3'b010 Host Abort received during reception
14755  *
14756  * Others: Reserved
14757  *
14758  * EB is read-only.
14759  *
14760  * Field Access Macros:
14761  *
14762  */
14763 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_EB register field. */
14764 #define ALT_SDMMC_IDSTS_EB_LSB 10
14765 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_EB register field. */
14766 #define ALT_SDMMC_IDSTS_EB_MSB 12
14767 /* The width in bits of the ALT_SDMMC_IDSTS_EB register field. */
14768 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
14769 /* The mask used to set the ALT_SDMMC_IDSTS_EB register field value. */
14770 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
14771 /* The mask used to clear the ALT_SDMMC_IDSTS_EB register field value. */
14772 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
14773 /* The reset value of the ALT_SDMMC_IDSTS_EB register field. */
14774 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
14775 /* Extracts the ALT_SDMMC_IDSTS_EB field value from a register. */
14776 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
14777 /* Produces a ALT_SDMMC_IDSTS_EB register field value suitable for setting the register. */
14778 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
14779 
14780 /*
14781  * Field : FSM
14782  *
14783  * DMAC FSM present state.
14784  *
14785  * 0 DMA_IDLE
14786  *
14787  * 1 DMA_SUSPEND
14788  *
14789  * 2 DESC_RD
14790  *
14791  * 3 DESC_CHK
14792  *
14793  * 4 DMA_RD_REQ_WAIT
14794  *
14795  * 5 DMA_WR_REQ_WAIT
14796  *
14797  * 6 DMA_RD
14798  *
14799  * 7 DMA_WR
14800  *
14801  * 8 DESC_CLOSE
14802  *
14803  * This bit is read-only.
14804  *
14805  * Field Access Macros:
14806  *
14807  */
14808 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
14809 #define ALT_SDMMC_IDSTS_FSM_LSB 13
14810 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
14811 #define ALT_SDMMC_IDSTS_FSM_MSB 16
14812 /* The width in bits of the ALT_SDMMC_IDSTS_FSM register field. */
14813 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
14814 /* The mask used to set the ALT_SDMMC_IDSTS_FSM register field value. */
14815 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
14816 /* The mask used to clear the ALT_SDMMC_IDSTS_FSM register field value. */
14817 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
14818 /* The reset value of the ALT_SDMMC_IDSTS_FSM register field. */
14819 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
14820 /* Extracts the ALT_SDMMC_IDSTS_FSM field value from a register. */
14821 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
14822 /* Produces a ALT_SDMMC_IDSTS_FSM register field value suitable for setting the register. */
14823 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
14824 
14825 #ifndef __ASSEMBLY__
14826 /*
14827  * WARNING: The C register and register group struct declarations are provided for
14828  * convenience and illustrative purposes. They should, however, be used with
14829  * caution as the C language standard provides no guarantees about the alignment or
14830  * atomicity of device memory accesses. The recommended practice for coding device
14831  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
14832  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
14833  * alt_write_dword() functions for 64 bit registers.
14834  *
14835  * The struct declaration for register ALT_SDMMC_IDSTS.
14836  */
14837 struct ALT_SDMMC_IDSTS_s
14838 {
14839  volatile uint32_t TI : 1; /* ALT_SDMMC_IDSTS_TI */
14840  volatile uint32_t RI : 1; /* ALT_SDMMC_IDSTS_RI */
14841  volatile uint32_t FBE : 1; /* ALT_SDMMC_IDSTS_FBE */
14842  uint32_t : 1; /* *UNDEFINED* */
14843  volatile uint32_t DU : 1; /* ALT_SDMMC_IDSTS_DU */
14844  volatile uint32_t CES : 1; /* ALT_SDMMC_IDSTS_CES */
14845  uint32_t : 2; /* *UNDEFINED* */
14846  volatile uint32_t NIS : 1; /* ALT_SDMMC_IDSTS_NIS */
14847  volatile uint32_t AIS : 1; /* ALT_SDMMC_IDSTS_AIS */
14848  const volatile uint32_t EB : 3; /* ALT_SDMMC_IDSTS_EB */
14849  const volatile uint32_t FSM : 4; /* ALT_SDMMC_IDSTS_FSM */
14850  uint32_t : 15; /* *UNDEFINED* */
14851 };
14852 
14853 /* The typedef declaration for register ALT_SDMMC_IDSTS. */
14854 typedef struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
14855 #endif /* __ASSEMBLY__ */
14856 
14857 /* The reset value of the ALT_SDMMC_IDSTS register. */
14858 #define ALT_SDMMC_IDSTS_RESET 0x00000000
14859 /* The byte offset of the ALT_SDMMC_IDSTS register from the beginning of the component. */
14860 #define ALT_SDMMC_IDSTS_OFST 0x8c
14861 /* The address of the ALT_SDMMC_IDSTS register. */
14862 #define ALT_SDMMC_IDSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_IDSTS_OFST))
14863 
14864 /*
14865  * Register : Internal DMAC Interrupt Enable Register - IDINTEN
14866  *
14867  * Name: Internal DMAC Interrupt Enable Register
14868  *
14869  * Size: 32 bits
14870  *
14871  * Address Offset: 0x90
14872  *
14873  * Read/Write access: read/write
14874  *
14875  * Register Layout
14876  *
14877  * Bits | Access | Reset | Description
14878  * :--------|:-------|:------|:----------------------
14879  * [0] | RW | 0x0 | ALT_SDMMC_IDINTEN_TI
14880  * [1] | RW | 0x0 | ALT_SDMMC_IDINTEN_RI
14881  * [2] | RW | 0x0 | ALT_SDMMC_IDINTEN_FBE
14882  * [3] | ??? | 0x0 | *UNDEFINED*
14883  * [4] | RW | 0x0 | ALT_SDMMC_IDINTEN_DU
14884  * [5] | RW | 0x0 | ALT_SDMMC_IDINTEN_CES
14885  * [7:6] | ??? | 0x0 | *UNDEFINED*
14886  * [8] | RW | 0x0 | ALT_SDMMC_IDINTEN_NI
14887  * [9] | RW | 0x0 | ALT_SDMMC_IDINTEN_AI
14888  * [31:10] | ??? | 0x0 | *UNDEFINED*
14889  *
14890  */
14891 /*
14892  * Field : TI
14893  *
14894  * Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable,
14895  * Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.
14896  *
14897  * Field Enumeration Values:
14898  *
14899  * Enum | Value | Description
14900  * :--------------------------------|:------|:-----------------------------------------------
14901  * ALT_SDMMC_IDINTEN_TI_E_DISABLED | 0x0 | Transmit Interrupt is disabled
14902  * ALT_SDMMC_IDINTEN_TI_E_ENABLED | 0x1 | When set with Normal Interrupt Summary Enable,
14903  * : | | Transmit Interrupt is enabled
14904  *
14905  * Field Access Macros:
14906  *
14907  */
14908 /*
14909  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
14910  *
14911  * Transmit Interrupt is disabled
14912  */
14913 #define ALT_SDMMC_IDINTEN_TI_E_DISABLED 0x0
14914 /*
14915  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
14916  *
14917  * When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled
14918  */
14919 #define ALT_SDMMC_IDINTEN_TI_E_ENABLED 0x1
14920 
14921 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
14922 #define ALT_SDMMC_IDINTEN_TI_LSB 0
14923 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
14924 #define ALT_SDMMC_IDINTEN_TI_MSB 0
14925 /* The width in bits of the ALT_SDMMC_IDINTEN_TI register field. */
14926 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
14927 /* The mask used to set the ALT_SDMMC_IDINTEN_TI register field value. */
14928 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
14929 /* The mask used to clear the ALT_SDMMC_IDINTEN_TI register field value. */
14930 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
14931 /* The reset value of the ALT_SDMMC_IDINTEN_TI register field. */
14932 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
14933 /* Extracts the ALT_SDMMC_IDINTEN_TI field value from a register. */
14934 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
14935 /* Produces a ALT_SDMMC_IDINTEN_TI register field value suitable for setting the register. */
14936 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
14937 
14938 /*
14939  * Field : RI
14940  *
14941  * Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
14942  * Interrupt is enabled. When reset, Receive Interrupt is disabled.
14943  *
14944  * Field Enumeration Values:
14945  *
14946  * Enum | Value | Description
14947  * :--------------------------------|:------|:-----------------------------------------------
14948  * ALT_SDMMC_IDINTEN_RI_E_DISABLED | 0x0 | Receive Interrupt is disabled
14949  * ALT_SDMMC_IDINTEN_RI_E_ENABLED | 0x1 | When set with Normal Interrupt Summary Enable,
14950  * : | | Receive Interrupt is enabled
14951  *
14952  * Field Access Macros:
14953  *
14954  */
14955 /*
14956  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
14957  *
14958  * Receive Interrupt is disabled
14959  */
14960 #define ALT_SDMMC_IDINTEN_RI_E_DISABLED 0x0
14961 /*
14962  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
14963  *
14964  * When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled
14965  */
14966 #define ALT_SDMMC_IDINTEN_RI_E_ENABLED 0x1
14967 
14968 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
14969 #define ALT_SDMMC_IDINTEN_RI_LSB 1
14970 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
14971 #define ALT_SDMMC_IDINTEN_RI_MSB 1
14972 /* The width in bits of the ALT_SDMMC_IDINTEN_RI register field. */
14973 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
14974 /* The mask used to set the ALT_SDMMC_IDINTEN_RI register field value. */
14975 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
14976 /* The mask used to clear the ALT_SDMMC_IDINTEN_RI register field value. */
14977 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
14978 /* The reset value of the ALT_SDMMC_IDINTEN_RI register field. */
14979 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
14980 /* Extracts the ALT_SDMMC_IDINTEN_RI field value from a register. */
14981 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
14982 /* Produces a ALT_SDMMC_IDINTEN_RI register field value suitable for setting the register. */
14983 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
14984 
14985 /*
14986  * Field : FBE
14987  *
14988  * Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the
14989  * Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable
14990  * Interrupt is disabled.
14991  *
14992  * Field Enumeration Values:
14993  *
14994  * Enum | Value | Description
14995  * :---------------------------------|:------|:-------------------------------------------------
14996  * ALT_SDMMC_IDINTEN_FBE_E_DISABLED | 0x0 | Fatal Bus Error Enable Interrupt is disabled
14997  * ALT_SDMMC_IDINTEN_FBE_E_ENABLED | 0x1 | When set with Abnormal Interrupt Summary Enable,
14998  * : | | the Fatal Bus Error Interrupt is enabled
14999  *
15000  * Field Access Macros:
15001  *
15002  */
15003 /*
15004  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
15005  *
15006  * Fatal Bus Error Enable Interrupt is disabled
15007  */
15008 #define ALT_SDMMC_IDINTEN_FBE_E_DISABLED 0x0
15009 /*
15010  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
15011  *
15012  * When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt
15013  * is enabled
15014  */
15015 #define ALT_SDMMC_IDINTEN_FBE_E_ENABLED 0x1
15016 
15017 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
15018 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
15019 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
15020 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
15021 /* The width in bits of the ALT_SDMMC_IDINTEN_FBE register field. */
15022 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
15023 /* The mask used to set the ALT_SDMMC_IDINTEN_FBE register field value. */
15024 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
15025 /* The mask used to clear the ALT_SDMMC_IDINTEN_FBE register field value. */
15026 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
15027 /* The reset value of the ALT_SDMMC_IDINTEN_FBE register field. */
15028 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
15029 /* Extracts the ALT_SDMMC_IDINTEN_FBE field value from a register. */
15030 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
15031 /* Produces a ALT_SDMMC_IDINTEN_FBE register field value suitable for setting the register. */
15032 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
15033 
15034 /*
15035  * Field : DU
15036  *
15037  * Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
15038  * Enable, the DU interrupt is enabled.
15039  *
15040  * Field Enumeration Values:
15041  *
15042  * Enum | Value | Description
15043  * :--------------------------------|:------|:-------------------------------------------------
15044  * ALT_SDMMC_IDINTEN_DU_E_DISABLED | 0x0 | The Descriptor Unavailable interrupt is disabled
15045  * ALT_SDMMC_IDINTEN_DU_E_ENABLED | 0x1 | When set along with Abnormal Interrupt Summary
15046  * : | | Enable, the Descriptor Unavailable interrupt is
15047  * : | | enabled
15048  *
15049  * Field Access Macros:
15050  *
15051  */
15052 /*
15053  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
15054  *
15055  * The Descriptor Unavailable interrupt is disabled
15056  */
15057 #define ALT_SDMMC_IDINTEN_DU_E_DISABLED 0x0
15058 /*
15059  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
15060  *
15061  * When set along with Abnormal Interrupt Summary Enable, the Descriptor
15062  * Unavailable interrupt is enabled
15063  */
15064 #define ALT_SDMMC_IDINTEN_DU_E_ENABLED 0x1
15065 
15066 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
15067 #define ALT_SDMMC_IDINTEN_DU_LSB 4
15068 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
15069 #define ALT_SDMMC_IDINTEN_DU_MSB 4
15070 /* The width in bits of the ALT_SDMMC_IDINTEN_DU register field. */
15071 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
15072 /* The mask used to set the ALT_SDMMC_IDINTEN_DU register field value. */
15073 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
15074 /* The mask used to clear the ALT_SDMMC_IDINTEN_DU register field value. */
15075 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
15076 /* The reset value of the ALT_SDMMC_IDINTEN_DU register field. */
15077 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
15078 /* Extracts the ALT_SDMMC_IDINTEN_DU field value from a register. */
15079 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
15080 /* Produces a ALT_SDMMC_IDINTEN_DU register field value suitable for setting the register. */
15081 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
15082 
15083 /*
15084  * Field : CES
15085  *
15086  * Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
15087  * summary.
15088  *
15089  * Field Enumeration Values:
15090  *
15091  * Enum | Value | Description
15092  * :---------------------------------|:------|:---------------------------------------
15093  * ALT_SDMMC_IDINTEN_CES_E_DISABLED | 0x0 | The Card Interrupt summary is disabled
15094  * ALT_SDMMC_IDINTEN_CES_E_ENABLED | 0x1 | The Card Interrupt summary is enabled
15095  *
15096  * Field Access Macros:
15097  *
15098  */
15099 /*
15100  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
15101  *
15102  * The Card Interrupt summary is disabled
15103  */
15104 #define ALT_SDMMC_IDINTEN_CES_E_DISABLED 0x0
15105 /*
15106  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
15107  *
15108  * The Card Interrupt summary is enabled
15109  */
15110 #define ALT_SDMMC_IDINTEN_CES_E_ENABLED 0x1
15111 
15112 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
15113 #define ALT_SDMMC_IDINTEN_CES_LSB 5
15114 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
15115 #define ALT_SDMMC_IDINTEN_CES_MSB 5
15116 /* The width in bits of the ALT_SDMMC_IDINTEN_CES register field. */
15117 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
15118 /* The mask used to set the ALT_SDMMC_IDINTEN_CES register field value. */
15119 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
15120 /* The mask used to clear the ALT_SDMMC_IDINTEN_CES register field value. */
15121 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
15122 /* The reset value of the ALT_SDMMC_IDINTEN_CES register field. */
15123 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
15124 /* Extracts the ALT_SDMMC_IDINTEN_CES field value from a register. */
15125 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
15126 /* Produces a ALT_SDMMC_IDINTEN_CES register field value suitable for setting the register. */
15127 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
15128 
15129 /*
15130  * Field : NI
15131  *
15132  * Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
15133  * reset, a normal interrupt is disabled. This bit enables the following bits:
15134  *
15135  * IDINTEN[0] - Transmit Interrupt
15136  *
15137  * IDINTEN[1] - Receive Interrupt
15138  *
15139  * Field Enumeration Values:
15140  *
15141  * Enum | Value | Description
15142  * :--------------------------------|:------|:-------------------------------
15143  * ALT_SDMMC_IDINTEN_NI_E_DISABLED | 0x0 | A normal interrupt is disabled
15144  * ALT_SDMMC_IDINTEN_NI_E_ENABLED | 0x1 | A normal interrupt is enabled
15145  *
15146  * Field Access Macros:
15147  *
15148  */
15149 /*
15150  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
15151  *
15152  * A normal interrupt is disabled
15153  */
15154 #define ALT_SDMMC_IDINTEN_NI_E_DISABLED 0x0
15155 /*
15156  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
15157  *
15158  * A normal interrupt is enabled
15159  */
15160 #define ALT_SDMMC_IDINTEN_NI_E_ENABLED 0x1
15161 
15162 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
15163 #define ALT_SDMMC_IDINTEN_NI_LSB 8
15164 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
15165 #define ALT_SDMMC_IDINTEN_NI_MSB 8
15166 /* The width in bits of the ALT_SDMMC_IDINTEN_NI register field. */
15167 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
15168 /* The mask used to set the ALT_SDMMC_IDINTEN_NI register field value. */
15169 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
15170 /* The mask used to clear the ALT_SDMMC_IDINTEN_NI register field value. */
15171 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
15172 /* The reset value of the ALT_SDMMC_IDINTEN_NI register field. */
15173 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
15174 /* Extracts the ALT_SDMMC_IDINTEN_NI field value from a register. */
15175 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
15176 /* Produces a ALT_SDMMC_IDINTEN_NI register field value suitable for setting the register. */
15177 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
15178 
15179 /*
15180  * Field : AI
15181  *
15182  * Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled.
15183  * This bit enables the following bits:
15184  *
15185  * IDINTEN[2] - Fatal Bus Error Interrupt
15186  *
15187  * IDINTEN[4] - DU Interrupt
15188  *
15189  * Field Enumeration Values:
15190  *
15191  * Enum | Value | Description
15192  * :--------------------------------|:------|:----------------------------------
15193  * ALT_SDMMC_IDINTEN_AI_E_DISABLED | 0x0 | An abnormal interrupt is disabled
15194  * ALT_SDMMC_IDINTEN_AI_E_ENABLED | 0x1 | An abnormal interrupt is enabled
15195  *
15196  * Field Access Macros:
15197  *
15198  */
15199 /*
15200  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
15201  *
15202  * An abnormal interrupt is disabled
15203  */
15204 #define ALT_SDMMC_IDINTEN_AI_E_DISABLED 0x0
15205 /*
15206  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
15207  *
15208  * An abnormal interrupt is enabled
15209  */
15210 #define ALT_SDMMC_IDINTEN_AI_E_ENABLED 0x1
15211 
15212 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
15213 #define ALT_SDMMC_IDINTEN_AI_LSB 9
15214 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
15215 #define ALT_SDMMC_IDINTEN_AI_MSB 9
15216 /* The width in bits of the ALT_SDMMC_IDINTEN_AI register field. */
15217 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
15218 /* The mask used to set the ALT_SDMMC_IDINTEN_AI register field value. */
15219 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
15220 /* The mask used to clear the ALT_SDMMC_IDINTEN_AI register field value. */
15221 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
15222 /* The reset value of the ALT_SDMMC_IDINTEN_AI register field. */
15223 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
15224 /* Extracts the ALT_SDMMC_IDINTEN_AI field value from a register. */
15225 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
15226 /* Produces a ALT_SDMMC_IDINTEN_AI register field value suitable for setting the register. */
15227 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
15228 
15229 #ifndef __ASSEMBLY__
15230 /*
15231  * WARNING: The C register and register group struct declarations are provided for
15232  * convenience and illustrative purposes. They should, however, be used with
15233  * caution as the C language standard provides no guarantees about the alignment or
15234  * atomicity of device memory accesses. The recommended practice for coding device
15235  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15236  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15237  * alt_write_dword() functions for 64 bit registers.
15238  *
15239  * The struct declaration for register ALT_SDMMC_IDINTEN.
15240  */
15241 struct ALT_SDMMC_IDINTEN_s
15242 {
15243  volatile uint32_t TI : 1; /* ALT_SDMMC_IDINTEN_TI */
15244  volatile uint32_t RI : 1; /* ALT_SDMMC_IDINTEN_RI */
15245  volatile uint32_t FBE : 1; /* ALT_SDMMC_IDINTEN_FBE */
15246  uint32_t : 1; /* *UNDEFINED* */
15247  volatile uint32_t DU : 1; /* ALT_SDMMC_IDINTEN_DU */
15248  volatile uint32_t CES : 1; /* ALT_SDMMC_IDINTEN_CES */
15249  uint32_t : 2; /* *UNDEFINED* */
15250  volatile uint32_t NI : 1; /* ALT_SDMMC_IDINTEN_NI */
15251  volatile uint32_t AI : 1; /* ALT_SDMMC_IDINTEN_AI */
15252  uint32_t : 22; /* *UNDEFINED* */
15253 };
15254 
15255 /* The typedef declaration for register ALT_SDMMC_IDINTEN. */
15256 typedef struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
15257 #endif /* __ASSEMBLY__ */
15258 
15259 /* The reset value of the ALT_SDMMC_IDINTEN register. */
15260 #define ALT_SDMMC_IDINTEN_RESET 0x00000000
15261 /* The byte offset of the ALT_SDMMC_IDINTEN register from the beginning of the component. */
15262 #define ALT_SDMMC_IDINTEN_OFST 0x90
15263 /* The address of the ALT_SDMMC_IDINTEN register. */
15264 #define ALT_SDMMC_IDINTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_IDINTEN_OFST))
15265 
15266 /*
15267  * Register : Current Host Descriptor Address Register - DSCADDR
15268  *
15269  * Name: Current Host Descriptor Address Register
15270  *
15271  * Size: 32 bits
15272  *
15273  * Address Offset: 0x94
15274  *
15275  * Read/Write access: read
15276  *
15277  * Register Layout
15278  *
15279  * Bits | Access | Reset | Description
15280  * :-------|:-------|:------|:----------------------
15281  * [31:0] | R | 0x0 | ALT_SDMMC_DSCADDR_HDA
15282  *
15283  */
15284 /*
15285  * Field : HDA
15286  *
15287  * Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC
15288  * during operation. This register points to the start address of the current
15289  * descriptor read by the IDMAC.
15290  *
15291  * Field Access Macros:
15292  *
15293  */
15294 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
15295 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
15296 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
15297 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
15298 /* The width in bits of the ALT_SDMMC_DSCADDR_HDA register field. */
15299 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
15300 /* The mask used to set the ALT_SDMMC_DSCADDR_HDA register field value. */
15301 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
15302 /* The mask used to clear the ALT_SDMMC_DSCADDR_HDA register field value. */
15303 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
15304 /* The reset value of the ALT_SDMMC_DSCADDR_HDA register field. */
15305 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
15306 /* Extracts the ALT_SDMMC_DSCADDR_HDA field value from a register. */
15307 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
15308 /* Produces a ALT_SDMMC_DSCADDR_HDA register field value suitable for setting the register. */
15309 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
15310 
15311 #ifndef __ASSEMBLY__
15312 /*
15313  * WARNING: The C register and register group struct declarations are provided for
15314  * convenience and illustrative purposes. They should, however, be used with
15315  * caution as the C language standard provides no guarantees about the alignment or
15316  * atomicity of device memory accesses. The recommended practice for coding device
15317  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15318  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15319  * alt_write_dword() functions for 64 bit registers.
15320  *
15321  * The struct declaration for register ALT_SDMMC_DSCADDR.
15322  */
15323 struct ALT_SDMMC_DSCADDR_s
15324 {
15325  const volatile uint32_t HDA : 32; /* ALT_SDMMC_DSCADDR_HDA */
15326 };
15327 
15328 /* The typedef declaration for register ALT_SDMMC_DSCADDR. */
15329 typedef struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
15330 #endif /* __ASSEMBLY__ */
15331 
15332 /* The reset value of the ALT_SDMMC_DSCADDR register. */
15333 #define ALT_SDMMC_DSCADDR_RESET 0x00000000
15334 /* The byte offset of the ALT_SDMMC_DSCADDR register from the beginning of the component. */
15335 #define ALT_SDMMC_DSCADDR_OFST 0x94
15336 /* The address of the ALT_SDMMC_DSCADDR register. */
15337 #define ALT_SDMMC_DSCADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DSCADDR_OFST))
15338 
15339 /*
15340  * Register : Current Buffer Descriptor Address Register - BUFADDR
15341  *
15342  * Name: Current Buffer Descriptor Address Register
15343  *
15344  * Size: 32 bits
15345  *
15346  * Address Offset: 0x98
15347  *
15348  * Read/Write access: read
15349  *
15350  * Register Layout
15351  *
15352  * Bits | Access | Reset | Description
15353  * :-------|:-------|:------|:----------------------
15354  * [31:0] | R | 0x0 | ALT_SDMMC_BUFADDR_HBA
15355  *
15356  */
15357 /*
15358  * Field : HBA
15359  *
15360  * Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during
15361  * operation. This register points to the current Data Buffer Address being
15362  * accessed by the IDMAC.
15363  *
15364  * Field Access Macros:
15365  *
15366  */
15367 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
15368 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
15369 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
15370 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
15371 /* The width in bits of the ALT_SDMMC_BUFADDR_HBA register field. */
15372 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
15373 /* The mask used to set the ALT_SDMMC_BUFADDR_HBA register field value. */
15374 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
15375 /* The mask used to clear the ALT_SDMMC_BUFADDR_HBA register field value. */
15376 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
15377 /* The reset value of the ALT_SDMMC_BUFADDR_HBA register field. */
15378 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
15379 /* Extracts the ALT_SDMMC_BUFADDR_HBA field value from a register. */
15380 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
15381 /* Produces a ALT_SDMMC_BUFADDR_HBA register field value suitable for setting the register. */
15382 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
15383 
15384 #ifndef __ASSEMBLY__
15385 /*
15386  * WARNING: The C register and register group struct declarations are provided for
15387  * convenience and illustrative purposes. They should, however, be used with
15388  * caution as the C language standard provides no guarantees about the alignment or
15389  * atomicity of device memory accesses. The recommended practice for coding device
15390  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15391  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15392  * alt_write_dword() functions for 64 bit registers.
15393  *
15394  * The struct declaration for register ALT_SDMMC_BUFADDR.
15395  */
15396 struct ALT_SDMMC_BUFADDR_s
15397 {
15398  const volatile uint32_t HBA : 32; /* ALT_SDMMC_BUFADDR_HBA */
15399 };
15400 
15401 /* The typedef declaration for register ALT_SDMMC_BUFADDR. */
15402 typedef struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
15403 #endif /* __ASSEMBLY__ */
15404 
15405 /* The reset value of the ALT_SDMMC_BUFADDR register. */
15406 #define ALT_SDMMC_BUFADDR_RESET 0x00000000
15407 /* The byte offset of the ALT_SDMMC_BUFADDR register from the beginning of the component. */
15408 #define ALT_SDMMC_BUFADDR_OFST 0x98
15409 /* The address of the ALT_SDMMC_BUFADDR register. */
15410 #define ALT_SDMMC_BUFADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BUFADDR_OFST))
15411 
15412 /*
15413  * Register : Card Threshold Control Register - CARDTHRCTL
15414  *
15415  * Name: Card Threshold Control Register
15416  *
15417  * Size: 32 bits
15418  *
15419  * Address Offset: 0x100
15420  *
15421  * Read/Write access: read/write
15422  *
15423  * Register Layout
15424  *
15425  * Bits | Access | Reset | Description
15426  * :--------|:-------|:------|:-------------------------------------
15427  * [0] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
15428  * [1] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN
15429  * [2] | R | 0x0 | ALT_SDMMC_CARDTHRCTL_CARDWRTHREN
15430  * [15:3] | ??? | 0x0 | *UNDEFINED*
15431  * [28:16] | RW | 0x0 | ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD
15432  * [31:29] | ??? | 0x0 | *UNDEFINED*
15433  *
15434  */
15435 /*
15436  * Field : CARDRDTHREN
15437  *
15438  * Card Read Threshold Enable
15439  *
15440  * 1'b0 - Card Read Threshold disabled
15441  *
15442  * 1'b1 - Card Read Threshold enabled. Host Controller initiates
15443  *
15444  * Read Transfer only if CardRdThreshold amount of space is
15445  *
15446  * available in receive FIFO.
15447  *
15448  * Field Enumeration Values:
15449  *
15450  * Enum | Value | Description
15451  * :--------------------------------------------|:------|:-----------------------------
15452  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISABLED | 0x0 | Card Read Threshold disabled
15453  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_ENABLED | 0x1 | Card Read Threshold enabled
15454  *
15455  * Field Access Macros:
15456  *
15457  */
15458 /*
15459  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
15460  *
15461  * Card Read Threshold disabled
15462  */
15463 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISABLED 0x0
15464 /*
15465  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
15466  *
15467  * Card Read Threshold enabled
15468  */
15469 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_ENABLED 0x1
15470 
15471 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
15472 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
15473 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
15474 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
15475 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
15476 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
15477 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
15478 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
15479 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
15480 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
15481 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
15482 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
15483 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN field value from a register. */
15484 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
15485 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value suitable for setting the register. */
15486 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
15487 
15488 /*
15489  * Field : BUSY_CLR_INT_EN
15490  *
15491  * Busy Clear Interrupt generation:
15492  *
15493  * 1'b0 - Busy Clear Interrupt disabled
15494  *
15495  * 1'b1 - Busy Clear Interrupt enabled
15496  *
15497  * Note: The application can disable this feature if it does not want to wait for a
15498  * Busy Clear Interrupt. For example, in a multi-card scenario, the application can
15499  * switch to the other card without waiting for a busy to be completed. In such
15500  * cases, the application can use the polling method to determine the status of
15501  * busy. By default this feature is disabled and backward-compatible to the legacy
15502  * drivers where polling is used.
15503  *
15504  * Field Enumeration Values:
15505  *
15506  * Enum | Value | Description
15507  * :------------------------------------------------|:------|:------------------------------
15508  * ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_DISABLED | 0x0 | Busy Clear Interrupt disabled
15509  * ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_ENABLED | 0x1 | Busy Clear Interrupt enabled
15510  *
15511  * Field Access Macros:
15512  *
15513  */
15514 /*
15515  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN
15516  *
15517  * Busy Clear Interrupt disabled
15518  */
15519 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_DISABLED 0x0
15520 /*
15521  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN
15522  *
15523  * Busy Clear Interrupt enabled
15524  */
15525 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_ENABLED 0x1
15526 
15527 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
15528 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_LSB 1
15529 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
15530 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_MSB 1
15531 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
15532 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_WIDTH 1
15533 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value. */
15534 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET_MSK 0x00000002
15535 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value. */
15536 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_CLR_MSK 0xfffffffd
15537 /* The reset value of the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field. */
15538 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_RESET 0x0
15539 /* Extracts the ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN field value from a register. */
15540 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_GET(value) (((value) & 0x00000002) >> 1)
15541 /* Produces a ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN register field value suitable for setting the register. */
15542 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET(value) (((value) << 1) & 0x00000002)
15543 
15544 /*
15545  * Field : CARDWRTHREN
15546  *
15547  * Card Write Threshold Enable
15548  *
15549  * 1'b0 - Card Write Threshold disabled
15550  *
15551  * 1'b1 - Card Write Threshold enabled. Host Controller initiates
15552  *
15553  * Write Transfer only if CardThreshold amount of data is
15554  *
15555  * available in transmit FIFO.
15556  *
15557  * Field Enumeration Values:
15558  *
15559  * Enum | Value | Description
15560  * :--------------------------------------------|:------|:------------------------------
15561  * ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_DISABLED | 0x0 | Card Write Threshold disabled
15562  * ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_ENABLED | 0x1 | Card Write Threshold enabled
15563  *
15564  * Field Access Macros:
15565  *
15566  */
15567 /*
15568  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDWRTHREN
15569  *
15570  * Card Write Threshold disabled
15571  */
15572 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_DISABLED 0x0
15573 /*
15574  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDWRTHREN
15575  *
15576  * Card Write Threshold enabled
15577  */
15578 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_ENABLED 0x1
15579 
15580 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field. */
15581 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_LSB 2
15582 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field. */
15583 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_MSB 2
15584 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field. */
15585 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_WIDTH 1
15586 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field value. */
15587 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_SET_MSK 0x00000004
15588 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field value. */
15589 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_CLR_MSK 0xfffffffb
15590 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field. */
15591 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_RESET 0x0
15592 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDWRTHREN field value from a register. */
15593 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_GET(value) (((value) & 0x00000004) >> 2)
15594 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDWRTHREN register field value suitable for setting the register. */
15595 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_SET(value) (((value) << 2) & 0x00000004)
15596 
15597 /*
15598  * Field : CARDRDTHRESHOLD
15599  *
15600  * Card Read Threshold size; N depends on the FIFO size:
15601  *
15602  * N = 27 FIFO_DEPTH is 128
15603  *
15604  * N = 26 FIFO_DEPTH is 64
15605  *
15606  * N = 25 FIFO_DEPTH is 32
15607  *
15608  * N = 24 FIFO_DEPTH is 16
15609  *
15610  * N = 23 FIFO_DEPTH is 8
15611  *
15612  * Note: The maximum programmable value of Card Read Threshold size is 512.
15613  *
15614  * Field Access Macros:
15615  *
15616  */
15617 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
15618 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
15619 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
15620 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 28
15621 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
15622 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 13
15623 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
15624 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x1fff0000
15625 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
15626 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xe000ffff
15627 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
15628 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
15629 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD field value from a register. */
15630 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x1fff0000) >> 16)
15631 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value suitable for setting the register. */
15632 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x1fff0000)
15633 
15634 #ifndef __ASSEMBLY__
15635 /*
15636  * WARNING: The C register and register group struct declarations are provided for
15637  * convenience and illustrative purposes. They should, however, be used with
15638  * caution as the C language standard provides no guarantees about the alignment or
15639  * atomicity of device memory accesses. The recommended practice for coding device
15640  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
15641  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
15642  * alt_write_dword() functions for 64 bit registers.
15643  *
15644  * The struct declaration for register ALT_SDMMC_CARDTHRCTL.
15645  */
15646 struct ALT_SDMMC_CARDTHRCTL_s
15647 {
15648  volatile uint32_t CARDRDTHREN : 1; /* ALT_SDMMC_CARDTHRCTL_CARDRDTHREN */
15649  volatile uint32_t BUSY_CLR_INT_EN : 1; /* ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN */
15650  const volatile uint32_t CARDWRTHREN : 1; /* ALT_SDMMC_CARDTHRCTL_CARDWRTHREN */
15651  uint32_t : 13; /* *UNDEFINED* */
15652  volatile uint32_t CARDRDTHRESHOLD : 13; /* ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD */
15653  uint32_t : 3; /* *UNDEFINED* */
15654 };
15655 
15656 /* The typedef declaration for register ALT_SDMMC_CARDTHRCTL. */
15657 typedef struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
15658 #endif /* __ASSEMBLY__ */
15659 
15660 /* The reset value of the ALT_SDMMC_CARDTHRCTL register. */
15661 #define ALT_SDMMC_CARDTHRCTL_RESET 0x00000000
15662 /* The byte offset of the ALT_SDMMC_CARDTHRCTL register from the beginning of the component. */
15663 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
15664 /* The address of the ALT_SDMMC_CARDTHRCTL register. */
15665 #define ALT_SDMMC_CARDTHRCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CARDTHRCTL_OFST))
15666 
15667 /*
15668  * Register : Back End Power Register - BACK_END_POWER_R
15669  *
15670  * Name: Back End Power Register
15671  *
15672  * Size: 32 bits
15673  *
15674  * Address Offset: 0x104
15675  *
15676  * Read/Write access: read/write
15677  *
15678  * Register Layout
15679  *
15680  * Bits | Access | Reset | Description
15681  * :--------|:-------|:------|:---------------------------------------------
15682  * [0] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0
15683  * [1] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1
15684  * [2] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2
15685  * [3] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3
15686  * [4] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4
15687  * [5] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5
15688  * [6] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6
15689  * [7] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7
15690  * [8] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8
15691  * [9] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9
15692  * [10] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10
15693  * [11] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11
15694  * [12] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12
15695  * [13] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13
15696  * [14] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14
15697  * [15] | RW | 0x0 | ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15
15698  * [31:16] | ??? | 0x0 | *UNDEFINED*
15699  *
15700  */
15701 /*
15702  * Field : BACK_END_POWER_0
15703  *
15704  * Back end power
15705  *
15706  * 1'b0 Off; Reset
15707  *
15708  * 1'b1 Back-end Power supplied to card application; one pin per
15709  *
15710  * card
15711  *
15712  * Field Enumeration Values:
15713  *
15714  * Enum | Value | Description
15715  * :-------------------------------------------------------|:------|:------------------------
15716  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_DISABLED | 0x0 | Back-end Power off
15717  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_ENABLED | 0x1 | Back-end power supplied
15718  *
15719  * Field Access Macros:
15720  *
15721  */
15722 /*
15723  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0
15724  *
15725  * Back-end Power off
15726  */
15727 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_DISABLED 0x0
15728 /*
15729  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0
15730  *
15731  * Back-end power supplied
15732  */
15733 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_ENABLED 0x1
15734 
15735 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field. */
15736 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_LSB 0
15737 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field. */
15738 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_MSB 0
15739 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field. */
15740 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_WIDTH 1
15741 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field value. */
15742 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_SET_MSK 0x00000001
15743 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field value. */
15744 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_CLR_MSK 0xfffffffe
15745 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field. */
15746 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_RESET 0x0
15747 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 field value from a register. */
15748 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_GET(value) (((value) & 0x00000001) >> 0)
15749 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 register field value suitable for setting the register. */
15750 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_SET(value) (((value) << 0) & 0x00000001)
15751 
15752 /*
15753  * Field : BACK_END_POWER_1
15754  *
15755  * Back end power
15756  *
15757  * 1'b0 Off; Reset
15758  *
15759  * 1'b1 Back-end Power supplied to card application; one pin per
15760  *
15761  * card
15762  *
15763  * Field Enumeration Values:
15764  *
15765  * Enum | Value | Description
15766  * :-------------------------------------------------------|:------|:------------------------
15767  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_DISABLED | 0x0 | Back-end Power off
15768  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_ENABLED | 0x1 | Back-end power supplied
15769  *
15770  * Field Access Macros:
15771  *
15772  */
15773 /*
15774  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1
15775  *
15776  * Back-end Power off
15777  */
15778 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_DISABLED 0x0
15779 /*
15780  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1
15781  *
15782  * Back-end power supplied
15783  */
15784 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_ENABLED 0x1
15785 
15786 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field. */
15787 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_LSB 1
15788 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field. */
15789 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_MSB 1
15790 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field. */
15791 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_WIDTH 1
15792 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field value. */
15793 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_SET_MSK 0x00000002
15794 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field value. */
15795 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_CLR_MSK 0xfffffffd
15796 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field. */
15797 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_RESET 0x0
15798 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 field value from a register. */
15799 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_GET(value) (((value) & 0x00000002) >> 1)
15800 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 register field value suitable for setting the register. */
15801 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_SET(value) (((value) << 1) & 0x00000002)
15802 
15803 /*
15804  * Field : BACK_END_POWER_2
15805  *
15806  * Back end power
15807  *
15808  * 1'b0 Off; Reset
15809  *
15810  * 1'b1 Back-end Power supplied to card application; one pin per
15811  *
15812  * card
15813  *
15814  * Field Enumeration Values:
15815  *
15816  * Enum | Value | Description
15817  * :-------------------------------------------------------|:------|:------------------------
15818  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_DISABLED | 0x0 | Back-end Power off
15819  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_ENABLED | 0x1 | Back-end power supplied
15820  *
15821  * Field Access Macros:
15822  *
15823  */
15824 /*
15825  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2
15826  *
15827  * Back-end Power off
15828  */
15829 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_DISABLED 0x0
15830 /*
15831  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2
15832  *
15833  * Back-end power supplied
15834  */
15835 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_ENABLED 0x1
15836 
15837 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field. */
15838 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_LSB 2
15839 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field. */
15840 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_MSB 2
15841 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field. */
15842 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_WIDTH 1
15843 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field value. */
15844 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_SET_MSK 0x00000004
15845 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field value. */
15846 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_CLR_MSK 0xfffffffb
15847 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field. */
15848 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_RESET 0x0
15849 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 field value from a register. */
15850 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_GET(value) (((value) & 0x00000004) >> 2)
15851 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 register field value suitable for setting the register. */
15852 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_SET(value) (((value) << 2) & 0x00000004)
15853 
15854 /*
15855  * Field : BACK_END_POWER_3
15856  *
15857  * Back end power
15858  *
15859  * 1'b0 Off; Reset
15860  *
15861  * 1'b1 Back-end Power supplied to card application; one pin per
15862  *
15863  * card
15864  *
15865  * Field Enumeration Values:
15866  *
15867  * Enum | Value | Description
15868  * :-------------------------------------------------------|:------|:------------------------
15869  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_DISABLED | 0x0 | Back-end Power off
15870  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_ENABLED | 0x1 | Back-end power supplied
15871  *
15872  * Field Access Macros:
15873  *
15874  */
15875 /*
15876  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3
15877  *
15878  * Back-end Power off
15879  */
15880 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_DISABLED 0x0
15881 /*
15882  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3
15883  *
15884  * Back-end power supplied
15885  */
15886 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_ENABLED 0x1
15887 
15888 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field. */
15889 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_LSB 3
15890 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field. */
15891 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_MSB 3
15892 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field. */
15893 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_WIDTH 1
15894 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field value. */
15895 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_SET_MSK 0x00000008
15896 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field value. */
15897 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_CLR_MSK 0xfffffff7
15898 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field. */
15899 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_RESET 0x0
15900 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 field value from a register. */
15901 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_GET(value) (((value) & 0x00000008) >> 3)
15902 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 register field value suitable for setting the register. */
15903 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_SET(value) (((value) << 3) & 0x00000008)
15904 
15905 /*
15906  * Field : BACK_END_POWER_4
15907  *
15908  * Back end power
15909  *
15910  * 1'b0 Off; Reset
15911  *
15912  * 1'b1 Back-end Power supplied to card application; one pin per
15913  *
15914  * card
15915  *
15916  * Field Enumeration Values:
15917  *
15918  * Enum | Value | Description
15919  * :-------------------------------------------------------|:------|:------------------------
15920  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_DISABLED | 0x0 | Back-end Power off
15921  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_ENABLED | 0x1 | Back-end power supplied
15922  *
15923  * Field Access Macros:
15924  *
15925  */
15926 /*
15927  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4
15928  *
15929  * Back-end Power off
15930  */
15931 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_DISABLED 0x0
15932 /*
15933  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4
15934  *
15935  * Back-end power supplied
15936  */
15937 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_ENABLED 0x1
15938 
15939 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field. */
15940 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_LSB 4
15941 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field. */
15942 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_MSB 4
15943 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field. */
15944 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_WIDTH 1
15945 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field value. */
15946 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_SET_MSK 0x00000010
15947 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field value. */
15948 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_CLR_MSK 0xffffffef
15949 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field. */
15950 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_RESET 0x0
15951 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 field value from a register. */
15952 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_GET(value) (((value) & 0x00000010) >> 4)
15953 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 register field value suitable for setting the register. */
15954 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_SET(value) (((value) << 4) & 0x00000010)
15955 
15956 /*
15957  * Field : BACK_END_POWER_5
15958  *
15959  * Back end power
15960  *
15961  * 1'b0 Off; Reset
15962  *
15963  * 1'b1 Back-end Power supplied to card application; one pin per
15964  *
15965  * card
15966  *
15967  * Field Enumeration Values:
15968  *
15969  * Enum | Value | Description
15970  * :-------------------------------------------------------|:------|:------------------------
15971  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_DISABLED | 0x0 | Back-end Power off
15972  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_ENABLED | 0x1 | Back-end power supplied
15973  *
15974  * Field Access Macros:
15975  *
15976  */
15977 /*
15978  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5
15979  *
15980  * Back-end Power off
15981  */
15982 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_DISABLED 0x0
15983 /*
15984  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5
15985  *
15986  * Back-end power supplied
15987  */
15988 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_ENABLED 0x1
15989 
15990 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field. */
15991 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_LSB 5
15992 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field. */
15993 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_MSB 5
15994 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field. */
15995 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_WIDTH 1
15996 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field value. */
15997 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_SET_MSK 0x00000020
15998 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field value. */
15999 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_CLR_MSK 0xffffffdf
16000 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field. */
16001 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_RESET 0x0
16002 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 field value from a register. */
16003 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_GET(value) (((value) & 0x00000020) >> 5)
16004 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 register field value suitable for setting the register. */
16005 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_SET(value) (((value) << 5) & 0x00000020)
16006 
16007 /*
16008  * Field : BACK_END_POWER_6
16009  *
16010  * Back end power
16011  *
16012  * 1'b0 Off; Reset
16013  *
16014  * 1'b1 Back-end Power supplied to card application; one pin per
16015  *
16016  * card
16017  *
16018  * Field Enumeration Values:
16019  *
16020  * Enum | Value | Description
16021  * :-------------------------------------------------------|:------|:------------------------
16022  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_DISABLED | 0x0 | Back-end Power off
16023  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_ENABLED | 0x1 | Back-end power supplied
16024  *
16025  * Field Access Macros:
16026  *
16027  */
16028 /*
16029  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6
16030  *
16031  * Back-end Power off
16032  */
16033 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_DISABLED 0x0
16034 /*
16035  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6
16036  *
16037  * Back-end power supplied
16038  */
16039 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_ENABLED 0x1
16040 
16041 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field. */
16042 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_LSB 6
16043 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field. */
16044 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_MSB 6
16045 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field. */
16046 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_WIDTH 1
16047 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field value. */
16048 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_SET_MSK 0x00000040
16049 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field value. */
16050 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_CLR_MSK 0xffffffbf
16051 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field. */
16052 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_RESET 0x0
16053 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 field value from a register. */
16054 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_GET(value) (((value) & 0x00000040) >> 6)
16055 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 register field value suitable for setting the register. */
16056 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_SET(value) (((value) << 6) & 0x00000040)
16057 
16058 /*
16059  * Field : BACK_END_POWER_7
16060  *
16061  * Back end power
16062  *
16063  * 1'b0 Off; Reset
16064  *
16065  * 1'b1 Back-end Power supplied to card application; one pin per
16066  *
16067  * card
16068  *
16069  * Field Enumeration Values:
16070  *
16071  * Enum | Value | Description
16072  * :-------------------------------------------------------|:------|:------------------------
16073  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_DISABLED | 0x0 | Back-end Power off
16074  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_ENABLED | 0x1 | Back-end power supplied
16075  *
16076  * Field Access Macros:
16077  *
16078  */
16079 /*
16080  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7
16081  *
16082  * Back-end Power off
16083  */
16084 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_DISABLED 0x0
16085 /*
16086  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7
16087  *
16088  * Back-end power supplied
16089  */
16090 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_ENABLED 0x1
16091 
16092 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field. */
16093 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_LSB 7
16094 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field. */
16095 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_MSB 7
16096 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field. */
16097 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_WIDTH 1
16098 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field value. */
16099 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_SET_MSK 0x00000080
16100 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field value. */
16101 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_CLR_MSK 0xffffff7f
16102 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field. */
16103 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_RESET 0x0
16104 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 field value from a register. */
16105 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_GET(value) (((value) & 0x00000080) >> 7)
16106 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 register field value suitable for setting the register. */
16107 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_SET(value) (((value) << 7) & 0x00000080)
16108 
16109 /*
16110  * Field : BACK_END_POWER_8
16111  *
16112  * Back end power
16113  *
16114  * 1'b0 Off; Reset
16115  *
16116  * 1'b1 Back-end Power supplied to card application; one pin per
16117  *
16118  * card
16119  *
16120  * Field Enumeration Values:
16121  *
16122  * Enum | Value | Description
16123  * :-------------------------------------------------------|:------|:------------------------
16124  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_DISABLED | 0x0 | Back-end Power off
16125  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_ENABLED | 0x1 | Back-end power supplied
16126  *
16127  * Field Access Macros:
16128  *
16129  */
16130 /*
16131  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8
16132  *
16133  * Back-end Power off
16134  */
16135 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_DISABLED 0x0
16136 /*
16137  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8
16138  *
16139  * Back-end power supplied
16140  */
16141 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_ENABLED 0x1
16142 
16143 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field. */
16144 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_LSB 8
16145 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field. */
16146 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_MSB 8
16147 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field. */
16148 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_WIDTH 1
16149 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field value. */
16150 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_SET_MSK 0x00000100
16151 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field value. */
16152 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_CLR_MSK 0xfffffeff
16153 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field. */
16154 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_RESET 0x0
16155 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 field value from a register. */
16156 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_GET(value) (((value) & 0x00000100) >> 8)
16157 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 register field value suitable for setting the register. */
16158 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_SET(value) (((value) << 8) & 0x00000100)
16159 
16160 /*
16161  * Field : BACK_END_POWER_9
16162  *
16163  * Back end power
16164  *
16165  * 1'b0 Off; Reset
16166  *
16167  * 1'b1 Back-end Power supplied to card application; one pin per
16168  *
16169  * card
16170  *
16171  * Field Enumeration Values:
16172  *
16173  * Enum | Value | Description
16174  * :-------------------------------------------------------|:------|:------------------------
16175  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_DISABLED | 0x0 | Back-end Power off
16176  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_ENABLED | 0x1 | Back-end power supplied
16177  *
16178  * Field Access Macros:
16179  *
16180  */
16181 /*
16182  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9
16183  *
16184  * Back-end Power off
16185  */
16186 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_DISABLED 0x0
16187 /*
16188  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9
16189  *
16190  * Back-end power supplied
16191  */
16192 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_ENABLED 0x1
16193 
16194 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field. */
16195 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_LSB 9
16196 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field. */
16197 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_MSB 9
16198 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field. */
16199 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_WIDTH 1
16200 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field value. */
16201 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_SET_MSK 0x00000200
16202 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field value. */
16203 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_CLR_MSK 0xfffffdff
16204 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field. */
16205 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_RESET 0x0
16206 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 field value from a register. */
16207 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_GET(value) (((value) & 0x00000200) >> 9)
16208 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 register field value suitable for setting the register. */
16209 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_SET(value) (((value) << 9) & 0x00000200)
16210 
16211 /*
16212  * Field : BACK_END_POWER_10
16213  *
16214  * Back end power
16215  *
16216  * 1'b0 Off; Reset
16217  *
16218  * 1'b1 Back-end Power supplied to card application; one pin per
16219  *
16220  * card
16221  *
16222  * Field Enumeration Values:
16223  *
16224  * Enum | Value | Description
16225  * :--------------------------------------------------------|:------|:------------------------
16226  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_DISABLED | 0x0 | Back-end Power off
16227  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_ENABLED | 0x1 | Back-end power supplied
16228  *
16229  * Field Access Macros:
16230  *
16231  */
16232 /*
16233  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10
16234  *
16235  * Back-end Power off
16236  */
16237 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_DISABLED 0x0
16238 /*
16239  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10
16240  *
16241  * Back-end power supplied
16242  */
16243 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_ENABLED 0x1
16244 
16245 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field. */
16246 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_LSB 10
16247 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field. */
16248 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_MSB 10
16249 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field. */
16250 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_WIDTH 1
16251 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field value. */
16252 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_SET_MSK 0x00000400
16253 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field value. */
16254 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_CLR_MSK 0xfffffbff
16255 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field. */
16256 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_RESET 0x0
16257 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 field value from a register. */
16258 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_GET(value) (((value) & 0x00000400) >> 10)
16259 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 register field value suitable for setting the register. */
16260 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_SET(value) (((value) << 10) & 0x00000400)
16261 
16262 /*
16263  * Field : BACK_END_POWER_11
16264  *
16265  * Back end power
16266  *
16267  * 1'b0 Off; Reset
16268  *
16269  * 1'b1 Back-end Power supplied to card application; one pin per
16270  *
16271  * card
16272  *
16273  * Field Enumeration Values:
16274  *
16275  * Enum | Value | Description
16276  * :--------------------------------------------------------|:------|:------------------------
16277  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_DISABLED | 0x0 | Back-end Power off
16278  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_ENABLED | 0x1 | Back-end power supplied
16279  *
16280  * Field Access Macros:
16281  *
16282  */
16283 /*
16284  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11
16285  *
16286  * Back-end Power off
16287  */
16288 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_DISABLED 0x0
16289 /*
16290  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11
16291  *
16292  * Back-end power supplied
16293  */
16294 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_ENABLED 0x1
16295 
16296 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field. */
16297 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_LSB 11
16298 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field. */
16299 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_MSB 11
16300 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field. */
16301 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_WIDTH 1
16302 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field value. */
16303 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_SET_MSK 0x00000800
16304 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field value. */
16305 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_CLR_MSK 0xfffff7ff
16306 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field. */
16307 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_RESET 0x0
16308 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 field value from a register. */
16309 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_GET(value) (((value) & 0x00000800) >> 11)
16310 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 register field value suitable for setting the register. */
16311 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_SET(value) (((value) << 11) & 0x00000800)
16312 
16313 /*
16314  * Field : BACK_END_POWER_12
16315  *
16316  * Back end power
16317  *
16318  * 1'b0 Off; Reset
16319  *
16320  * 1'b1 Back-end Power supplied to card application; one pin per
16321  *
16322  * card
16323  *
16324  * Field Enumeration Values:
16325  *
16326  * Enum | Value | Description
16327  * :--------------------------------------------------------|:------|:------------------------
16328  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_DISABLED | 0x0 | Back-end Power off
16329  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_ENABLED | 0x1 | Back-end power supplied
16330  *
16331  * Field Access Macros:
16332  *
16333  */
16334 /*
16335  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12
16336  *
16337  * Back-end Power off
16338  */
16339 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_DISABLED 0x0
16340 /*
16341  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12
16342  *
16343  * Back-end power supplied
16344  */
16345 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_ENABLED 0x1
16346 
16347 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field. */
16348 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_LSB 12
16349 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field. */
16350 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_MSB 12
16351 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field. */
16352 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_WIDTH 1
16353 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field value. */
16354 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_SET_MSK 0x00001000
16355 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field value. */
16356 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_CLR_MSK 0xffffefff
16357 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field. */
16358 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_RESET 0x0
16359 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 field value from a register. */
16360 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_GET(value) (((value) & 0x00001000) >> 12)
16361 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 register field value suitable for setting the register. */
16362 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_SET(value) (((value) << 12) & 0x00001000)
16363 
16364 /*
16365  * Field : BACK_END_POWER_13
16366  *
16367  * Back end power
16368  *
16369  * 1'b0 Off; Reset
16370  *
16371  * 1'b1 Back-end Power supplied to card application; one pin per
16372  *
16373  * card
16374  *
16375  * Field Enumeration Values:
16376  *
16377  * Enum | Value | Description
16378  * :--------------------------------------------------------|:------|:------------------------
16379  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_DISABLED | 0x0 | Back-end Power off
16380  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_ENABLED | 0x1 | Back-end power supplied
16381  *
16382  * Field Access Macros:
16383  *
16384  */
16385 /*
16386  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13
16387  *
16388  * Back-end Power off
16389  */
16390 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_DISABLED 0x0
16391 /*
16392  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13
16393  *
16394  * Back-end power supplied
16395  */
16396 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_ENABLED 0x1
16397 
16398 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field. */
16399 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_LSB 13
16400 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field. */
16401 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_MSB 13
16402 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field. */
16403 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_WIDTH 1
16404 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field value. */
16405 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_SET_MSK 0x00002000
16406 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field value. */
16407 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_CLR_MSK 0xffffdfff
16408 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field. */
16409 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_RESET 0x0
16410 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 field value from a register. */
16411 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_GET(value) (((value) & 0x00002000) >> 13)
16412 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 register field value suitable for setting the register. */
16413 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_SET(value) (((value) << 13) & 0x00002000)
16414 
16415 /*
16416  * Field : BACK_END_POWER_14
16417  *
16418  * Back end power
16419  *
16420  * 1'b0 Off; Reset
16421  *
16422  * 1'b1 Back-end Power supplied to card application; one pin per
16423  *
16424  * card
16425  *
16426  * Field Enumeration Values:
16427  *
16428  * Enum | Value | Description
16429  * :--------------------------------------------------------|:------|:------------------------
16430  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_DISABLED | 0x0 | Back-end Power off
16431  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_ENABLED | 0x1 | Back-end power supplied
16432  *
16433  * Field Access Macros:
16434  *
16435  */
16436 /*
16437  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14
16438  *
16439  * Back-end Power off
16440  */
16441 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_DISABLED 0x0
16442 /*
16443  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14
16444  *
16445  * Back-end power supplied
16446  */
16447 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_ENABLED 0x1
16448 
16449 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field. */
16450 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_LSB 14
16451 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field. */
16452 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_MSB 14
16453 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field. */
16454 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_WIDTH 1
16455 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field value. */
16456 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_SET_MSK 0x00004000
16457 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field value. */
16458 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_CLR_MSK 0xffffbfff
16459 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field. */
16460 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_RESET 0x0
16461 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 field value from a register. */
16462 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_GET(value) (((value) & 0x00004000) >> 14)
16463 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 register field value suitable for setting the register. */
16464 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_SET(value) (((value) << 14) & 0x00004000)
16465 
16466 /*
16467  * Field : BACK_END_POWER_15
16468  *
16469  * Back end power
16470  *
16471  * 1'b0 Off; Reset
16472  *
16473  * 1'b1 Back-end Power supplied to card application; one pin per
16474  *
16475  * card
16476  *
16477  * Field Enumeration Values:
16478  *
16479  * Enum | Value | Description
16480  * :--------------------------------------------------------|:------|:------------------------
16481  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_DISABLED | 0x0 | Back-end Power off
16482  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_ENABLED | 0x1 | Back-end power supplied
16483  *
16484  * Field Access Macros:
16485  *
16486  */
16487 /*
16488  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15
16489  *
16490  * Back-end Power off
16491  */
16492 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_DISABLED 0x0
16493 /*
16494  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15
16495  *
16496  * Back-end power supplied
16497  */
16498 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_ENABLED 0x1
16499 
16500 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field. */
16501 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_LSB 15
16502 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field. */
16503 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_MSB 15
16504 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field. */
16505 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_WIDTH 1
16506 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field value. */
16507 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_SET_MSK 0x00008000
16508 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field value. */
16509 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_CLR_MSK 0xffff7fff
16510 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field. */
16511 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_RESET 0x0
16512 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 field value from a register. */
16513 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_GET(value) (((value) & 0x00008000) >> 15)
16514 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 register field value suitable for setting the register. */
16515 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_SET(value) (((value) << 15) & 0x00008000)
16516 
16517 #ifndef __ASSEMBLY__
16518 /*
16519  * WARNING: The C register and register group struct declarations are provided for
16520  * convenience and illustrative purposes. They should, however, be used with
16521  * caution as the C language standard provides no guarantees about the alignment or
16522  * atomicity of device memory accesses. The recommended practice for coding device
16523  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
16524  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
16525  * alt_write_dword() functions for 64 bit registers.
16526  *
16527  * The struct declaration for register ALT_SDMMC_BACK_END_POWER_R.
16528  */
16529 struct ALT_SDMMC_BACK_END_POWER_R_s
16530 {
16531  volatile uint32_t BACK_END_POWER_0 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0 */
16532  volatile uint32_t BACK_END_POWER_1 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1 */
16533  volatile uint32_t BACK_END_POWER_2 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2 */
16534  volatile uint32_t BACK_END_POWER_3 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3 */
16535  volatile uint32_t BACK_END_POWER_4 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4 */
16536  volatile uint32_t BACK_END_POWER_5 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5 */
16537  volatile uint32_t BACK_END_POWER_6 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6 */
16538  volatile uint32_t BACK_END_POWER_7 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7 */
16539  volatile uint32_t BACK_END_POWER_8 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8 */
16540  volatile uint32_t BACK_END_POWER_9 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9 */
16541  volatile uint32_t BACK_END_POWER_10 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10 */
16542  volatile uint32_t BACK_END_POWER_11 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11 */
16543  volatile uint32_t BACK_END_POWER_12 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12 */
16544  volatile uint32_t BACK_END_POWER_13 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13 */
16545  volatile uint32_t BACK_END_POWER_14 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14 */
16546  volatile uint32_t BACK_END_POWER_15 : 1; /* ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15 */
16547  uint32_t : 16; /* *UNDEFINED* */
16548 };
16549 
16550 /* The typedef declaration for register ALT_SDMMC_BACK_END_POWER_R. */
16551 typedef struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
16552 #endif /* __ASSEMBLY__ */
16553 
16554 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R register. */
16555 #define ALT_SDMMC_BACK_END_POWER_R_RESET 0x00000000
16556 /* The byte offset of the ALT_SDMMC_BACK_END_POWER_R register from the beginning of the component. */
16557 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
16558 /* The address of the ALT_SDMMC_BACK_END_POWER_R register. */
16559 #define ALT_SDMMC_BACK_END_POWER_R_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BACK_END_POWER_R_OFST))
16560 
16561 /*
16562  * Register : UHS Register Extention - UHS_REG_EXT
16563  *
16564  * Name: UHS Register Extention
16565  *
16566  * Size: 32 bits
16567  *
16568  * Address Offset: 0x108
16569  *
16570  * Read/Write access: read/write
16571  *
16572  * Register Layout
16573  *
16574  * Bits | Access | Reset | Description
16575  * :--------|:-------|:------|:------------------------------------------
16576  * [0] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0
16577  * [1] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1
16578  * [2] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2
16579  * [3] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3
16580  * [4] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4
16581  * [5] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5
16582  * [6] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6
16583  * [7] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7
16584  * [8] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8
16585  * [9] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9
16586  * [10] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10
16587  * [11] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11
16588  * [12] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12
16589  * [13] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13
16590  * [14] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14
16591  * [15] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15
16592  * [22:16] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL
16593  * [29:23] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL
16594  * [31:30] | RW | 0x0 | ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL
16595  *
16596  */
16597 /*
16598  * Field : MMC_VOLT_REG_0
16599  *
16600  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16601  *
16602  * with UHS_VOLT_REG to decode output selected voltage.
16603  *
16604  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16605  * selected for the I/O voltage logic.
16606  *
16607  * Host controllers that support only SD standard or standard versions before
16608  * eMMC4.41 do not program MMC_VOLT_REG.
16609  *
16610  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16611  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16612  *
16613  * Field Enumeration Values:
16614  *
16615  * Enum | Value | Description
16616  * :------------------------------------------------|:------|:-------------------
16617  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_DISABLED | 0x0 | 1.2V not supported
16618  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_ENABLED | 0x1 | Support for 1.2V
16619  *
16620  * Field Access Macros:
16621  *
16622  */
16623 /*
16624  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0
16625  *
16626  * 1.2V not supported
16627  */
16628 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_DISABLED 0x0
16629 /*
16630  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0
16631  *
16632  * Support for 1.2V
16633  */
16634 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_ENABLED 0x1
16635 
16636 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field. */
16637 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_LSB 0
16638 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field. */
16639 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_MSB 0
16640 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field. */
16641 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_WIDTH 1
16642 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field value. */
16643 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_SET_MSK 0x00000001
16644 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field value. */
16645 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_CLR_MSK 0xfffffffe
16646 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field. */
16647 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_RESET 0x0
16648 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 field value from a register. */
16649 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_GET(value) (((value) & 0x00000001) >> 0)
16650 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 register field value suitable for setting the register. */
16651 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_SET(value) (((value) << 0) & 0x00000001)
16652 
16653 /*
16654  * Field : MMC_VOLT_REG_1
16655  *
16656  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16657  *
16658  * with UHS_VOLT_REG to decode output selected voltage.
16659  *
16660  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16661  * selected for the I/O voltage logic.
16662  *
16663  * Host controllers that support only SD standard or standard versions before
16664  * eMMC4.41 do not program MMC_VOLT_REG.
16665  *
16666  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16667  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16668  *
16669  * Field Enumeration Values:
16670  *
16671  * Enum | Value | Description
16672  * :------------------------------------------------|:------|:-------------------
16673  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_DISABLED | 0x0 | 1.2V not supported
16674  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_ENABLED | 0x1 | Support for 1.2V
16675  *
16676  * Field Access Macros:
16677  *
16678  */
16679 /*
16680  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1
16681  *
16682  * 1.2V not supported
16683  */
16684 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_DISABLED 0x0
16685 /*
16686  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1
16687  *
16688  * Support for 1.2V
16689  */
16690 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_ENABLED 0x1
16691 
16692 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field. */
16693 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_LSB 1
16694 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field. */
16695 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_MSB 1
16696 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field. */
16697 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_WIDTH 1
16698 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field value. */
16699 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_SET_MSK 0x00000002
16700 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field value. */
16701 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_CLR_MSK 0xfffffffd
16702 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field. */
16703 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_RESET 0x0
16704 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 field value from a register. */
16705 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_GET(value) (((value) & 0x00000002) >> 1)
16706 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 register field value suitable for setting the register. */
16707 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_SET(value) (((value) << 1) & 0x00000002)
16708 
16709 /*
16710  * Field : MMC_VOLT_REG_2
16711  *
16712  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16713  *
16714  * with UHS_VOLT_REG to decode output selected voltage.
16715  *
16716  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16717  * selected for the I/O voltage logic.
16718  *
16719  * Host controllers that support only SD standard or standard versions before
16720  * eMMC4.41 do not program MMC_VOLT_REG.
16721  *
16722  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16723  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16724  *
16725  * Field Enumeration Values:
16726  *
16727  * Enum | Value | Description
16728  * :------------------------------------------------|:------|:-------------------
16729  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_DISABLED | 0x0 | 1.2V not supported
16730  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_ENABLED | 0x1 | Support for 1.2V
16731  *
16732  * Field Access Macros:
16733  *
16734  */
16735 /*
16736  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2
16737  *
16738  * 1.2V not supported
16739  */
16740 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_DISABLED 0x0
16741 /*
16742  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2
16743  *
16744  * Support for 1.2V
16745  */
16746 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_ENABLED 0x1
16747 
16748 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field. */
16749 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_LSB 2
16750 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field. */
16751 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_MSB 2
16752 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field. */
16753 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_WIDTH 1
16754 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field value. */
16755 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_SET_MSK 0x00000004
16756 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field value. */
16757 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_CLR_MSK 0xfffffffb
16758 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field. */
16759 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_RESET 0x0
16760 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 field value from a register. */
16761 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_GET(value) (((value) & 0x00000004) >> 2)
16762 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 register field value suitable for setting the register. */
16763 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_SET(value) (((value) << 2) & 0x00000004)
16764 
16765 /*
16766  * Field : MMC_VOLT_REG_3
16767  *
16768  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16769  *
16770  * with UHS_VOLT_REG to decode output selected voltage.
16771  *
16772  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16773  * selected for the I/O voltage logic.
16774  *
16775  * Host controllers that support only SD standard or standard versions before
16776  * eMMC4.41 do not program MMC_VOLT_REG.
16777  *
16778  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16779  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16780  *
16781  * Field Enumeration Values:
16782  *
16783  * Enum | Value | Description
16784  * :------------------------------------------------|:------|:-------------------
16785  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_DISABLED | 0x0 | 1.2V not supported
16786  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_ENABLED | 0x1 | Support for 1.2V
16787  *
16788  * Field Access Macros:
16789  *
16790  */
16791 /*
16792  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3
16793  *
16794  * 1.2V not supported
16795  */
16796 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_DISABLED 0x0
16797 /*
16798  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3
16799  *
16800  * Support for 1.2V
16801  */
16802 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_ENABLED 0x1
16803 
16804 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field. */
16805 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_LSB 3
16806 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field. */
16807 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_MSB 3
16808 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field. */
16809 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_WIDTH 1
16810 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field value. */
16811 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_SET_MSK 0x00000008
16812 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field value. */
16813 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_CLR_MSK 0xfffffff7
16814 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field. */
16815 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_RESET 0x0
16816 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 field value from a register. */
16817 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_GET(value) (((value) & 0x00000008) >> 3)
16818 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 register field value suitable for setting the register. */
16819 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_SET(value) (((value) << 3) & 0x00000008)
16820 
16821 /*
16822  * Field : MMC_VOLT_REG_4
16823  *
16824  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16825  *
16826  * with UHS_VOLT_REG to decode output selected voltage.
16827  *
16828  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16829  * selected for the I/O voltage logic.
16830  *
16831  * Host controllers that support only SD standard or standard versions before
16832  * eMMC4.41 do not program MMC_VOLT_REG.
16833  *
16834  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16835  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16836  *
16837  * Field Enumeration Values:
16838  *
16839  * Enum | Value | Description
16840  * :------------------------------------------------|:------|:-------------------
16841  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_DISABLED | 0x0 | 1.2V not supported
16842  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_ENABLED | 0x1 | Support for 1.2V
16843  *
16844  * Field Access Macros:
16845  *
16846  */
16847 /*
16848  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4
16849  *
16850  * 1.2V not supported
16851  */
16852 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_DISABLED 0x0
16853 /*
16854  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4
16855  *
16856  * Support for 1.2V
16857  */
16858 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_ENABLED 0x1
16859 
16860 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field. */
16861 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_LSB 4
16862 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field. */
16863 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_MSB 4
16864 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field. */
16865 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_WIDTH 1
16866 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field value. */
16867 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_SET_MSK 0x00000010
16868 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field value. */
16869 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_CLR_MSK 0xffffffef
16870 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field. */
16871 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_RESET 0x0
16872 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 field value from a register. */
16873 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_GET(value) (((value) & 0x00000010) >> 4)
16874 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 register field value suitable for setting the register. */
16875 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_SET(value) (((value) << 4) & 0x00000010)
16876 
16877 /*
16878  * Field : MMC_VOLT_REG_5
16879  *
16880  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16881  *
16882  * with UHS_VOLT_REG to decode output selected voltage.
16883  *
16884  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16885  * selected for the I/O voltage logic.
16886  *
16887  * Host controllers that support only SD standard or standard versions before
16888  * eMMC4.41 do not program MMC_VOLT_REG.
16889  *
16890  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16891  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16892  *
16893  * Field Enumeration Values:
16894  *
16895  * Enum | Value | Description
16896  * :------------------------------------------------|:------|:-------------------
16897  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_DISABLED | 0x0 | 1.2V not supported
16898  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_ENABLED | 0x1 | Support for 1.2V
16899  *
16900  * Field Access Macros:
16901  *
16902  */
16903 /*
16904  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5
16905  *
16906  * 1.2V not supported
16907  */
16908 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_DISABLED 0x0
16909 /*
16910  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5
16911  *
16912  * Support for 1.2V
16913  */
16914 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_ENABLED 0x1
16915 
16916 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field. */
16917 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_LSB 5
16918 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field. */
16919 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_MSB 5
16920 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field. */
16921 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_WIDTH 1
16922 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field value. */
16923 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_SET_MSK 0x00000020
16924 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field value. */
16925 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_CLR_MSK 0xffffffdf
16926 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field. */
16927 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_RESET 0x0
16928 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 field value from a register. */
16929 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_GET(value) (((value) & 0x00000020) >> 5)
16930 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 register field value suitable for setting the register. */
16931 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_SET(value) (((value) << 5) & 0x00000020)
16932 
16933 /*
16934  * Field : MMC_VOLT_REG_6
16935  *
16936  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16937  *
16938  * with UHS_VOLT_REG to decode output selected voltage.
16939  *
16940  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16941  * selected for the I/O voltage logic.
16942  *
16943  * Host controllers that support only SD standard or standard versions before
16944  * eMMC4.41 do not program MMC_VOLT_REG.
16945  *
16946  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
16947  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
16948  *
16949  * Field Enumeration Values:
16950  *
16951  * Enum | Value | Description
16952  * :------------------------------------------------|:------|:-------------------
16953  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_DISABLED | 0x0 | 1.2V not supported
16954  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_ENABLED | 0x1 | Support for 1.2V
16955  *
16956  * Field Access Macros:
16957  *
16958  */
16959 /*
16960  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6
16961  *
16962  * 1.2V not supported
16963  */
16964 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_DISABLED 0x0
16965 /*
16966  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6
16967  *
16968  * Support for 1.2V
16969  */
16970 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_ENABLED 0x1
16971 
16972 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field. */
16973 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_LSB 6
16974 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field. */
16975 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_MSB 6
16976 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field. */
16977 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_WIDTH 1
16978 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field value. */
16979 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_SET_MSK 0x00000040
16980 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field value. */
16981 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_CLR_MSK 0xffffffbf
16982 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field. */
16983 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_RESET 0x0
16984 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 field value from a register. */
16985 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_GET(value) (((value) & 0x00000040) >> 6)
16986 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 register field value suitable for setting the register. */
16987 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_SET(value) (((value) << 6) & 0x00000040)
16988 
16989 /*
16990  * Field : MMC_VOLT_REG_7
16991  *
16992  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
16993  *
16994  * with UHS_VOLT_REG to decode output selected voltage.
16995  *
16996  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
16997  * selected for the I/O voltage logic.
16998  *
16999  * Host controllers that support only SD standard or standard versions before
17000  * eMMC4.41 do not program MMC_VOLT_REG.
17001  *
17002  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17003  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17004  *
17005  * Field Enumeration Values:
17006  *
17007  * Enum | Value | Description
17008  * :------------------------------------------------|:------|:-------------------
17009  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_DISABLED | 0x0 | 1.2V not supported
17010  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_ENABLED | 0x1 | Support for 1.2V
17011  *
17012  * Field Access Macros:
17013  *
17014  */
17015 /*
17016  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7
17017  *
17018  * 1.2V not supported
17019  */
17020 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_DISABLED 0x0
17021 /*
17022  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7
17023  *
17024  * Support for 1.2V
17025  */
17026 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_ENABLED 0x1
17027 
17028 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field. */
17029 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_LSB 7
17030 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field. */
17031 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_MSB 7
17032 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field. */
17033 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_WIDTH 1
17034 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field value. */
17035 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_SET_MSK 0x00000080
17036 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field value. */
17037 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_CLR_MSK 0xffffff7f
17038 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field. */
17039 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_RESET 0x0
17040 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 field value from a register. */
17041 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_GET(value) (((value) & 0x00000080) >> 7)
17042 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 register field value suitable for setting the register. */
17043 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_SET(value) (((value) << 7) & 0x00000080)
17044 
17045 /*
17046  * Field : MMC_VOLT_REG_8
17047  *
17048  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17049  *
17050  * with UHS_VOLT_REG to decode output selected voltage.
17051  *
17052  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17053  * selected for the I/O voltage logic.
17054  *
17055  * Host controllers that support only SD standard or standard versions before
17056  * eMMC4.41 do not program MMC_VOLT_REG.
17057  *
17058  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17059  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17060  *
17061  * Field Enumeration Values:
17062  *
17063  * Enum | Value | Description
17064  * :------------------------------------------------|:------|:-------------------
17065  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_DISABLED | 0x0 | 1.2V not supported
17066  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_ENABLED | 0x1 | Support for 1.2V
17067  *
17068  * Field Access Macros:
17069  *
17070  */
17071 /*
17072  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8
17073  *
17074  * 1.2V not supported
17075  */
17076 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_DISABLED 0x0
17077 /*
17078  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8
17079  *
17080  * Support for 1.2V
17081  */
17082 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_ENABLED 0x1
17083 
17084 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field. */
17085 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_LSB 8
17086 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field. */
17087 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_MSB 8
17088 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field. */
17089 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_WIDTH 1
17090 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field value. */
17091 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_SET_MSK 0x00000100
17092 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field value. */
17093 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_CLR_MSK 0xfffffeff
17094 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field. */
17095 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_RESET 0x0
17096 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 field value from a register. */
17097 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_GET(value) (((value) & 0x00000100) >> 8)
17098 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 register field value suitable for setting the register. */
17099 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_SET(value) (((value) << 8) & 0x00000100)
17100 
17101 /*
17102  * Field : MMC_VOLT_REG_9
17103  *
17104  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17105  *
17106  * with UHS_VOLT_REG to decode output selected voltage.
17107  *
17108  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17109  * selected for the I/O voltage logic.
17110  *
17111  * Host controllers that support only SD standard or standard versions before
17112  * eMMC4.41 do not program MMC_VOLT_REG.
17113  *
17114  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17115  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17116  *
17117  * Field Enumeration Values:
17118  *
17119  * Enum | Value | Description
17120  * :------------------------------------------------|:------|:-------------------
17121  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_DISABLED | 0x0 | 1.2V not supported
17122  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_ENABLED | 0x1 | Support for 1.2V
17123  *
17124  * Field Access Macros:
17125  *
17126  */
17127 /*
17128  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9
17129  *
17130  * 1.2V not supported
17131  */
17132 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_DISABLED 0x0
17133 /*
17134  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9
17135  *
17136  * Support for 1.2V
17137  */
17138 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_ENABLED 0x1
17139 
17140 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field. */
17141 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_LSB 9
17142 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field. */
17143 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_MSB 9
17144 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field. */
17145 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_WIDTH 1
17146 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field value. */
17147 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_SET_MSK 0x00000200
17148 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field value. */
17149 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_CLR_MSK 0xfffffdff
17150 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field. */
17151 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_RESET 0x0
17152 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 field value from a register. */
17153 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_GET(value) (((value) & 0x00000200) >> 9)
17154 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 register field value suitable for setting the register. */
17155 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_SET(value) (((value) << 9) & 0x00000200)
17156 
17157 /*
17158  * Field : MMC_VOLT_REG_10
17159  *
17160  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17161  *
17162  * with UHS_VOLT_REG to decode output selected voltage.
17163  *
17164  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17165  * selected for the I/O voltage logic.
17166  *
17167  * Host controllers that support only SD standard or standard versions before
17168  * eMMC4.41 do not program MMC_VOLT_REG.
17169  *
17170  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17171  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17172  *
17173  * Field Enumeration Values:
17174  *
17175  * Enum | Value | Description
17176  * :-------------------------------------------------|:------|:-------------------
17177  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_DISABLED | 0x0 | 1.2V not supported
17178  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_ENABLED | 0x1 | Support for 1.2V
17179  *
17180  * Field Access Macros:
17181  *
17182  */
17183 /*
17184  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10
17185  *
17186  * 1.2V not supported
17187  */
17188 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_DISABLED 0x0
17189 /*
17190  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10
17191  *
17192  * Support for 1.2V
17193  */
17194 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_ENABLED 0x1
17195 
17196 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field. */
17197 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_LSB 10
17198 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field. */
17199 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_MSB 10
17200 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field. */
17201 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_WIDTH 1
17202 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field value. */
17203 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_SET_MSK 0x00000400
17204 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field value. */
17205 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_CLR_MSK 0xfffffbff
17206 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field. */
17207 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_RESET 0x0
17208 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 field value from a register. */
17209 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_GET(value) (((value) & 0x00000400) >> 10)
17210 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 register field value suitable for setting the register. */
17211 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_SET(value) (((value) << 10) & 0x00000400)
17212 
17213 /*
17214  * Field : MMC_VOLT_REG_11
17215  *
17216  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17217  *
17218  * with UHS_VOLT_REG to decode output selected voltage.
17219  *
17220  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17221  * selected for the I/O voltage logic.
17222  *
17223  * Host controllers that support only SD standard or standard versions before
17224  * eMMC4.41 do not program MMC_VOLT_REG.
17225  *
17226  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17227  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17228  *
17229  * Field Enumeration Values:
17230  *
17231  * Enum | Value | Description
17232  * :-------------------------------------------------|:------|:-------------------
17233  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_DISABLED | 0x0 | 1.2V not supported
17234  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_ENABLED | 0x1 | Support for 1.2V
17235  *
17236  * Field Access Macros:
17237  *
17238  */
17239 /*
17240  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11
17241  *
17242  * 1.2V not supported
17243  */
17244 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_DISABLED 0x0
17245 /*
17246  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11
17247  *
17248  * Support for 1.2V
17249  */
17250 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_ENABLED 0x1
17251 
17252 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field. */
17253 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_LSB 11
17254 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field. */
17255 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_MSB 11
17256 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field. */
17257 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_WIDTH 1
17258 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field value. */
17259 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_SET_MSK 0x00000800
17260 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field value. */
17261 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_CLR_MSK 0xfffff7ff
17262 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field. */
17263 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_RESET 0x0
17264 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 field value from a register. */
17265 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_GET(value) (((value) & 0x00000800) >> 11)
17266 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 register field value suitable for setting the register. */
17267 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_SET(value) (((value) << 11) & 0x00000800)
17268 
17269 /*
17270  * Field : MMC_VOLT_REG_12
17271  *
17272  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17273  *
17274  * with UHS_VOLT_REG to decode output selected voltage.
17275  *
17276  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17277  * selected for the I/O voltage logic.
17278  *
17279  * Host controllers that support only SD standard or standard versions before
17280  * eMMC4.41 do not program MMC_VOLT_REG.
17281  *
17282  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17283  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17284  *
17285  * Field Enumeration Values:
17286  *
17287  * Enum | Value | Description
17288  * :-------------------------------------------------|:------|:-------------------
17289  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_DISABLED | 0x0 | 1.2V not supported
17290  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_ENABLED | 0x1 | Support for 1.2V
17291  *
17292  * Field Access Macros:
17293  *
17294  */
17295 /*
17296  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12
17297  *
17298  * 1.2V not supported
17299  */
17300 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_DISABLED 0x0
17301 /*
17302  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12
17303  *
17304  * Support for 1.2V
17305  */
17306 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_ENABLED 0x1
17307 
17308 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field. */
17309 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_LSB 12
17310 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field. */
17311 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_MSB 12
17312 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field. */
17313 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_WIDTH 1
17314 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field value. */
17315 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_SET_MSK 0x00001000
17316 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field value. */
17317 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_CLR_MSK 0xffffefff
17318 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field. */
17319 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_RESET 0x0
17320 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 field value from a register. */
17321 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_GET(value) (((value) & 0x00001000) >> 12)
17322 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 register field value suitable for setting the register. */
17323 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_SET(value) (((value) << 12) & 0x00001000)
17324 
17325 /*
17326  * Field : MMC_VOLT_REG_13
17327  *
17328  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17329  *
17330  * with UHS_VOLT_REG to decode output selected voltage.
17331  *
17332  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17333  * selected for the I/O voltage logic.
17334  *
17335  * Host controllers that support only SD standard or standard versions before
17336  * eMMC4.41 do not program MMC_VOLT_REG.
17337  *
17338  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17339  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17340  *
17341  * Field Enumeration Values:
17342  *
17343  * Enum | Value | Description
17344  * :-------------------------------------------------|:------|:-------------------
17345  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_DISABLED | 0x0 | 1.2V not supported
17346  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_ENABLED | 0x1 | Support for 1.2V
17347  *
17348  * Field Access Macros:
17349  *
17350  */
17351 /*
17352  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13
17353  *
17354  * 1.2V not supported
17355  */
17356 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_DISABLED 0x0
17357 /*
17358  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13
17359  *
17360  * Support for 1.2V
17361  */
17362 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_ENABLED 0x1
17363 
17364 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field. */
17365 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_LSB 13
17366 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field. */
17367 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_MSB 13
17368 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field. */
17369 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_WIDTH 1
17370 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field value. */
17371 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_SET_MSK 0x00002000
17372 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field value. */
17373 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_CLR_MSK 0xffffdfff
17374 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field. */
17375 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_RESET 0x0
17376 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 field value from a register. */
17377 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_GET(value) (((value) & 0x00002000) >> 13)
17378 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 register field value suitable for setting the register. */
17379 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_SET(value) (((value) << 13) & 0x00002000)
17380 
17381 /*
17382  * Field : MMC_VOLT_REG_14
17383  *
17384  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17385  *
17386  * with UHS_VOLT_REG to decode output selected voltage.
17387  *
17388  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17389  * selected for the I/O voltage logic.
17390  *
17391  * Host controllers that support only SD standard or standard versions before
17392  * eMMC4.41 do not program MMC_VOLT_REG.
17393  *
17394  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17395  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17396  *
17397  * Field Enumeration Values:
17398  *
17399  * Enum | Value | Description
17400  * :-------------------------------------------------|:------|:-------------------
17401  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_DISABLED | 0x0 | 1.2V not supported
17402  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_ENABLED | 0x1 | Support for 1.2V
17403  *
17404  * Field Access Macros:
17405  *
17406  */
17407 /*
17408  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14
17409  *
17410  * 1.2V not supported
17411  */
17412 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_DISABLED 0x0
17413 /*
17414  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14
17415  *
17416  * Support for 1.2V
17417  */
17418 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_ENABLED 0x1
17419 
17420 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field. */
17421 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_LSB 14
17422 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field. */
17423 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_MSB 14
17424 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field. */
17425 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_WIDTH 1
17426 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field value. */
17427 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_SET_MSK 0x00004000
17428 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field value. */
17429 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_CLR_MSK 0xffffbfff
17430 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field. */
17431 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_RESET 0x0
17432 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 field value from a register. */
17433 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_GET(value) (((value) & 0x00004000) >> 14)
17434 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 register field value suitable for setting the register. */
17435 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_SET(value) (((value) << 14) & 0x00004000)
17436 
17437 /*
17438  * Field : MMC_VOLT_REG_15
17439  *
17440  * Support for 1.2V. MMC_VOLT_REG bits; must be read in combination
17441  *
17442  * with UHS_VOLT_REG to decode output selected voltage.
17443  *
17444  * The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination
17445  * selected for the I/O voltage logic.
17446  *
17447  * Host controllers that support only SD standard or standard versions before
17448  * eMMC4.41 do not program MMC_VOLT_REG.
17449  *
17450  * Only host controllers that support all three versions3.3,1.8,1.2 Vcan program
17451  * MMC_VOLT_REG and connect biu_volt_reg_1_2.
17452  *
17453  * Field Enumeration Values:
17454  *
17455  * Enum | Value | Description
17456  * :-------------------------------------------------|:------|:-------------------
17457  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_DISABLED | 0x0 | 1.2V not supported
17458  * ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_ENABLED | 0x1 | Support for 1.2V
17459  *
17460  * Field Access Macros:
17461  *
17462  */
17463 /*
17464  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15
17465  *
17466  * 1.2V not supported
17467  */
17468 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_DISABLED 0x0
17469 /*
17470  * Enumerated value for register field ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15
17471  *
17472  * Support for 1.2V
17473  */
17474 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_ENABLED 0x1
17475 
17476 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field. */
17477 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_LSB 15
17478 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field. */
17479 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_MSB 15
17480 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field. */
17481 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_WIDTH 1
17482 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field value. */
17483 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_SET_MSK 0x00008000
17484 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field value. */
17485 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_CLR_MSK 0xffff7fff
17486 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field. */
17487 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_RESET 0x0
17488 /* Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 field value from a register. */
17489 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_GET(value) (((value) & 0x00008000) >> 15)
17490 /* Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 register field value suitable for setting the register. */
17491 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_SET(value) (((value) << 15) & 0x00008000)
17492 
17493 /*
17494  * Field : CLK_SMPL_PHASE_CTRL
17495  *
17496  * Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs
17497  * to control delay lines and four LSBs to control phase shift; alternatively, use
17498  * only LSBs.
17499  *
17500  * Field Access Macros:
17501  *
17502  */
17503 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field. */
17504 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_LSB 16
17505 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field. */
17506 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_MSB 22
17507 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field. */
17508 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_WIDTH 7
17509 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field value. */
17510 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_SET_MSK 0x007f0000
17511 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field value. */
17512 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_CLR_MSK 0xff80ffff
17513 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field. */
17514 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_RESET 0x0
17515 /* Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL field value from a register. */
17516 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_GET(value) (((value) & 0x007f0000) >> 16)
17517 /* Produces a ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL register field value suitable for setting the register. */
17518 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_SET(value) (((value) << 16) & 0x007f0000)
17519 
17520 /*
17521  * Field : CLK_DRV_PHASE_CTRL
17522  *
17523  * Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to
17524  * control delay lines and four LSBs to control phase shift; alternatively, use
17525  * only LSBs.
17526  *
17527  * Field Access Macros:
17528  *
17529  */
17530 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field. */
17531 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_LSB 23
17532 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field. */
17533 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_MSB 29
17534 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field. */
17535 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_WIDTH 7
17536 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field value. */
17537 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_SET_MSK 0x3f800000
17538 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field value. */
17539 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_CLR_MSK 0xc07fffff
17540 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field. */
17541 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_RESET 0x0
17542 /* Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL field value from a register. */
17543 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_GET(value) (((value) & 0x3f800000) >> 23)
17544 /* Produces a ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL register field value suitable for setting the register. */
17545 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_SET(value) (((value) << 23) & 0x3f800000)
17546 
17547 /*
17548  * Field : EXT_CLK_MUX_CTRL
17549  *
17550  * Input clock control for cclk_in. The MUX controlled by these bits exists outside
17551  * DWC_mobile_storage IP.
17552  *
17553  * Field Access Macros:
17554  *
17555  */
17556 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field. */
17557 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_LSB 30
17558 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field. */
17559 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_MSB 31
17560 /* The width in bits of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field. */
17561 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_WIDTH 2
17562 /* The mask used to set the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field value. */
17563 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_SET_MSK 0xc0000000
17564 /* The mask used to clear the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field value. */
17565 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_CLR_MSK 0x3fffffff
17566 /* The reset value of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field. */
17567 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_RESET 0x0
17568 /* Extracts the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL field value from a register. */
17569 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_GET(value) (((value) & 0xc0000000) >> 30)
17570 /* Produces a ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL register field value suitable for setting the register. */
17571 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_SET(value) (((value) << 30) & 0xc0000000)
17572 
17573 #ifndef __ASSEMBLY__
17574 /*
17575  * WARNING: The C register and register group struct declarations are provided for
17576  * convenience and illustrative purposes. They should, however, be used with
17577  * caution as the C language standard provides no guarantees about the alignment or
17578  * atomicity of device memory accesses. The recommended practice for coding device
17579  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17580  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17581  * alt_write_dword() functions for 64 bit registers.
17582  *
17583  * The struct declaration for register ALT_SDMMC_UHS_REG_EXT.
17584  */
17585 struct ALT_SDMMC_UHS_REG_EXT_s
17586 {
17587  volatile uint32_t MMC_VOLT_REG_0 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0 */
17588  volatile uint32_t MMC_VOLT_REG_1 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1 */
17589  volatile uint32_t MMC_VOLT_REG_2 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2 */
17590  volatile uint32_t MMC_VOLT_REG_3 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3 */
17591  volatile uint32_t MMC_VOLT_REG_4 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4 */
17592  volatile uint32_t MMC_VOLT_REG_5 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5 */
17593  volatile uint32_t MMC_VOLT_REG_6 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6 */
17594  volatile uint32_t MMC_VOLT_REG_7 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7 */
17595  volatile uint32_t MMC_VOLT_REG_8 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8 */
17596  volatile uint32_t MMC_VOLT_REG_9 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9 */
17597  volatile uint32_t MMC_VOLT_REG_10 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10 */
17598  volatile uint32_t MMC_VOLT_REG_11 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11 */
17599  volatile uint32_t MMC_VOLT_REG_12 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12 */
17600  volatile uint32_t MMC_VOLT_REG_13 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13 */
17601  volatile uint32_t MMC_VOLT_REG_14 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14 */
17602  volatile uint32_t MMC_VOLT_REG_15 : 1; /* ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15 */
17603  volatile uint32_t CLK_SMPL_PHASE_CTRL : 7; /* ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL */
17604  volatile uint32_t CLK_DRV_PHASE_CTRL : 7; /* ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL */
17605  volatile uint32_t EXT_CLK_MUX_CTRL : 2; /* ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL */
17606 };
17607 
17608 /* The typedef declaration for register ALT_SDMMC_UHS_REG_EXT. */
17609 typedef struct ALT_SDMMC_UHS_REG_EXT_s ALT_SDMMC_UHS_REG_EXT_t;
17610 #endif /* __ASSEMBLY__ */
17611 
17612 /* The reset value of the ALT_SDMMC_UHS_REG_EXT register. */
17613 #define ALT_SDMMC_UHS_REG_EXT_RESET 0x00000000
17614 /* The byte offset of the ALT_SDMMC_UHS_REG_EXT register from the beginning of the component. */
17615 #define ALT_SDMMC_UHS_REG_EXT_OFST 0x108
17616 /* The address of the ALT_SDMMC_UHS_REG_EXT register. */
17617 #define ALT_SDMMC_UHS_REG_EXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_UHS_REG_EXT_OFST))
17618 
17619 /*
17620  * Register : EMMC DDR Register - EMMC_DDR_REG
17621  *
17622  * Name: EMMC DDR Register
17623  *
17624  * Size: 32 bits
17625  *
17626  * Address Offset: 0x10C
17627  *
17628  * Read/Write access: read/write
17629  *
17630  * Register Layout
17631  *
17632  * Bits | Access | Reset | Description
17633  * :-------|:-------|:------|:----------------------------------------
17634  * [0] | RW | 0x0 | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0
17635  * [30:1] | ??? | 0x0 | *UNDEFINED*
17636  * [31] | R | 0x0 | ALT_SDMMC_EMMC_DDR_REG_HS400_MODE
17637  *
17638  */
17639 /*
17640  * Field : HALF_START_BIT_0
17641  *
17642  * Control for start bit detection mechanism inside
17643  *
17644  * DWC_mobile_storage based on duration of start bit; each bit refers to one slot.
17645  * For eMMC 4.5, start bit can
17646  *
17647  * be:
17648  *
17649  * Full cycle (HALF_START_BIT = 0)
17650  *
17651  * Less than one full cycle (HALF_START_BIT = 1)
17652  *
17653  * Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications.
17654  *
17655  * Note: This bit is not applicable for HS400 mode
17656  *
17657  * Field Enumeration Values:
17658  *
17659  * Enum | Value | Description
17660  * :---------------------------------------------------|:------|:------------------------
17661  * ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_DISABLED | 0x0 | HALF_START_BIT disabled
17662  * ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_ENABLED | 0x1 | HALF_START_BIT enabled
17663  *
17664  * Field Access Macros:
17665  *
17666  */
17667 /*
17668  * Enumerated value for register field ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0
17669  *
17670  * HALF_START_BIT disabled
17671  */
17672 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_DISABLED 0x0
17673 /*
17674  * Enumerated value for register field ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0
17675  *
17676  * HALF_START_BIT enabled
17677  */
17678 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_ENABLED 0x1
17679 
17680 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field. */
17681 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_LSB 0
17682 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field. */
17683 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_MSB 0
17684 /* The width in bits of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field. */
17685 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_WIDTH 1
17686 /* The mask used to set the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field value. */
17687 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_SET_MSK 0x00000001
17688 /* The mask used to clear the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field value. */
17689 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_CLR_MSK 0xfffffffe
17690 /* The reset value of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field. */
17691 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_RESET 0x0
17692 /* Extracts the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 field value from a register. */
17693 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_GET(value) (((value) & 0x00000001) >> 0)
17694 /* Produces a ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 register field value suitable for setting the register. */
17695 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_SET(value) (((value) << 0) & 0x00000001)
17696 
17697 /*
17698  * Field : HS400_MODE
17699  *
17700  * HS400 Mode Enable
17701  *
17702  * 1'b0 - Disable
17703  *
17704  * 1'b1 - Enable
17705  *
17706  * Note: The application is required to set this bit to '1' before initiating any
17707  * data
17708  *
17709  * transfer CMD in HS400 mode. This bit shall be cleared by the host on exiting
17710  * HS400 mode.
17711  *
17712  * In non HS400 mode, this bit shall be set to '0'
17713  *
17714  * Field Enumeration Values:
17715  *
17716  * Enum | Value | Description
17717  * :---------------------------------------------|:------|:--------------------
17718  * ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_DISABLED | 0x0 | HS400 Mode Disabled
17719  * ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_ENABLED | 0x1 | HS400 Mode Enabled
17720  *
17721  * Field Access Macros:
17722  *
17723  */
17724 /*
17725  * Enumerated value for register field ALT_SDMMC_EMMC_DDR_REG_HS400_MODE
17726  *
17727  * HS400 Mode Disabled
17728  */
17729 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_DISABLED 0x0
17730 /*
17731  * Enumerated value for register field ALT_SDMMC_EMMC_DDR_REG_HS400_MODE
17732  *
17733  * HS400 Mode Enabled
17734  */
17735 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_ENABLED 0x1
17736 
17737 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field. */
17738 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_LSB 31
17739 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field. */
17740 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_MSB 31
17741 /* The width in bits of the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field. */
17742 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_WIDTH 1
17743 /* The mask used to set the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field value. */
17744 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_SET_MSK 0x80000000
17745 /* The mask used to clear the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field value. */
17746 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_CLR_MSK 0x7fffffff
17747 /* The reset value of the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field. */
17748 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_RESET 0x0
17749 /* Extracts the ALT_SDMMC_EMMC_DDR_REG_HS400_MODE field value from a register. */
17750 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_GET(value) (((value) & 0x80000000) >> 31)
17751 /* Produces a ALT_SDMMC_EMMC_DDR_REG_HS400_MODE register field value suitable for setting the register. */
17752 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_SET(value) (((value) << 31) & 0x80000000)
17753 
17754 #ifndef __ASSEMBLY__
17755 /*
17756  * WARNING: The C register and register group struct declarations are provided for
17757  * convenience and illustrative purposes. They should, however, be used with
17758  * caution as the C language standard provides no guarantees about the alignment or
17759  * atomicity of device memory accesses. The recommended practice for coding device
17760  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17761  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17762  * alt_write_dword() functions for 64 bit registers.
17763  *
17764  * The struct declaration for register ALT_SDMMC_EMMC_DDR_REG.
17765  */
17766 struct ALT_SDMMC_EMMC_DDR_REG_s
17767 {
17768  volatile uint32_t HALF_START_BIT_0 : 1; /* ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0 */
17769  uint32_t : 30; /* *UNDEFINED* */
17770  const volatile uint32_t HS400_MODE : 1; /* ALT_SDMMC_EMMC_DDR_REG_HS400_MODE */
17771 };
17772 
17773 /* The typedef declaration for register ALT_SDMMC_EMMC_DDR_REG. */
17774 typedef struct ALT_SDMMC_EMMC_DDR_REG_s ALT_SDMMC_EMMC_DDR_REG_t;
17775 #endif /* __ASSEMBLY__ */
17776 
17777 /* The reset value of the ALT_SDMMC_EMMC_DDR_REG register. */
17778 #define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000
17779 /* The byte offset of the ALT_SDMMC_EMMC_DDR_REG register from the beginning of the component. */
17780 #define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c
17781 /* The address of the ALT_SDMMC_EMMC_DDR_REG register. */
17782 #define ALT_SDMMC_EMMC_DDR_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_EMMC_DDR_REG_OFST))
17783 
17784 /*
17785  * Register : Enable Phase Shift Register - ENABLE_SHIFT
17786  *
17787  * Name: Enable Phase Shift Register
17788  *
17789  * Address Offset: 0x110
17790  *
17791  * Read/Write access: read/write
17792  *
17793  * Register Layout
17794  *
17795  * Bits | Access | Reset | Description
17796  * :-------|:-------|:------|:------------------------------------------
17797  * [1:0] | RW | 0x0 | ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0
17798  * [31:2] | ??? | 0x0 | *UNDEFINED*
17799  *
17800  */
17801 /*
17802  * Field : ENABLE_SHIFT_CARD0
17803  *
17804  * Control for the amount of phase shift provided on the default
17805  *
17806  * enables in the design. Two bits are assigned for each card/slot. For example,
17807  * bits[1:0] control slot0 and indicate the following.
17808  *
17809  * 00 Default phase shift
17810  *
17811  * 01 Enables shifted to next immediate positive edge
17812  *
17813  * 10 Enables shifted to next immediate negative edge
17814  *
17815  * 11 Reserved
17816  *
17817  * Field Enumeration Values:
17818  *
17819  * Enum | Value | Description
17820  * :----------------------------------------------------|:------|:------------------------------------------------
17821  * ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_DEFAULT | 0x0 | Default phase shift
17822  * ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_POSEDGE | 0x1 | Enables shifted to next immediate positive edge
17823  * ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_NEGEDGE | 0x2 | Enables shifted to next immediate negative edge
17824  * ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_RSVD | 0x3 | Reserved
17825  *
17826  * Field Access Macros:
17827  *
17828  */
17829 /*
17830  * Enumerated value for register field ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0
17831  *
17832  * Default phase shift
17833  */
17834 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_DEFAULT 0x0
17835 /*
17836  * Enumerated value for register field ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0
17837  *
17838  * Enables shifted to next immediate positive edge
17839  */
17840 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_POSEDGE 0x1
17841 /*
17842  * Enumerated value for register field ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0
17843  *
17844  * Enables shifted to next immediate negative edge
17845  */
17846 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_NEGEDGE 0x2
17847 /*
17848  * Enumerated value for register field ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0
17849  *
17850  * Reserved
17851  */
17852 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_RSVD 0x3
17853 
17854 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field. */
17855 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_LSB 0
17856 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field. */
17857 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_MSB 1
17858 /* The width in bits of the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field. */
17859 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_WIDTH 2
17860 /* The mask used to set the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field value. */
17861 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_SET_MSK 0x00000003
17862 /* The mask used to clear the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field value. */
17863 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_CLR_MSK 0xfffffffc
17864 /* The reset value of the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field. */
17865 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_RESET 0x0
17866 /* Extracts the ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 field value from a register. */
17867 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_GET(value) (((value) & 0x00000003) >> 0)
17868 /* Produces a ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 register field value suitable for setting the register. */
17869 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_SET(value) (((value) << 0) & 0x00000003)
17870 
17871 #ifndef __ASSEMBLY__
17872 /*
17873  * WARNING: The C register and register group struct declarations are provided for
17874  * convenience and illustrative purposes. They should, however, be used with
17875  * caution as the C language standard provides no guarantees about the alignment or
17876  * atomicity of device memory accesses. The recommended practice for coding device
17877  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17878  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17879  * alt_write_dword() functions for 64 bit registers.
17880  *
17881  * The struct declaration for register ALT_SDMMC_ENABLE_SHIFT.
17882  */
17883 struct ALT_SDMMC_ENABLE_SHIFT_s
17884 {
17885  volatile uint32_t ENABLE_SHIFT_CARD0 : 2; /* ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0 */
17886  uint32_t : 30; /* *UNDEFINED* */
17887 };
17888 
17889 /* The typedef declaration for register ALT_SDMMC_ENABLE_SHIFT. */
17890 typedef struct ALT_SDMMC_ENABLE_SHIFT_s ALT_SDMMC_ENABLE_SHIFT_t;
17891 #endif /* __ASSEMBLY__ */
17892 
17893 /* The reset value of the ALT_SDMMC_ENABLE_SHIFT register. */
17894 #define ALT_SDMMC_ENABLE_SHIFT_RESET 0x00000000
17895 /* The byte offset of the ALT_SDMMC_ENABLE_SHIFT register from the beginning of the component. */
17896 #define ALT_SDMMC_ENABLE_SHIFT_OFST 0x110
17897 /* The address of the ALT_SDMMC_ENABLE_SHIFT register. */
17898 #define ALT_SDMMC_ENABLE_SHIFT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_ENABLE_SHIFT_OFST))
17899 
17900 /*
17901  * Register : Data FIFO Access - DATA
17902  *
17903  * Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to
17904  * the data FIFO. More than one address is mapped to data FIFO so that FIFO can be
17905  * accessed using bursts.
17906  *
17907  * Register Layout
17908  *
17909  * Bits | Access | Reset | Description
17910  * :-------|:-------|:--------|:------------
17911  * [31:0] | RW | Unknown | FIFO Data
17912  *
17913  */
17914 /*
17915  * Field : FIFO Data - value
17916  *
17917  * Provides read/write access to data FIFO.
17918  *
17919  * Field Access Macros:
17920  *
17921  */
17922 /* The Least Significant Bit (LSB) position of the SDMMC_DATA_VALUE register field. */
17923 #define SDMMC_DATA_VALUE_LSB 0
17924 /* The Most Significant Bit (MSB) position of the SDMMC_DATA_VALUE register field. */
17925 #define SDMMC_DATA_VALUE_MSB 31
17926 /* The width in bits of the SDMMC_DATA_VALUE register field. */
17927 #define SDMMC_DATA_VALUE_WIDTH 32
17928 /* The mask used to set the SDMMC_DATA_VALUE register field value. */
17929 #define SDMMC_DATA_VALUE_SET_MSK 0xffffffff
17930 /* The mask used to clear the SDMMC_DATA_VALUE register field value. */
17931 #define SDMMC_DATA_VALUE_CLR_MSK 0x00000000
17932 /* The reset value of the SDMMC_DATA_VALUE register field is UNKNOWN. */
17933 #define SDMMC_DATA_VALUE_RESET 0x0
17934 /* Extracts the SDMMC_DATA_VALUE field value from a register. */
17935 #define SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
17936 /* Produces a SDMMC_DATA_VALUE register field value suitable for setting the register. */
17937 #define SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
17938 
17939 #ifndef __ASSEMBLY__
17940 /*
17941  * WARNING: The C register and register group struct declarations are provided for
17942  * convenience and illustrative purposes. They should, however, be used with
17943  * caution as the C language standard provides no guarantees about the alignment or
17944  * atomicity of device memory accesses. The recommended practice for coding device
17945  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17946  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17947  * alt_write_dword() functions for 64 bit registers.
17948  *
17949  * The struct declaration for register SDMMC_DATA.
17950  */
17951 struct SDMMC_DATA_s
17952 {
17953  volatile uint32_t value : 32; /* FIFO Data */
17954 };
17955 
17956 /* The typedef declaration for register SDMMC_DATA. */
17957 typedef struct SDMMC_DATA_s SDMMC_DATA_t;
17958 #endif /* __ASSEMBLY__ */
17959 
17960 /* The reset value of the SDMMC_DATA register. */
17961 #define SDMMC_DATA_RESET 0x00000000
17962 /* The byte offset of the SDMMC_DATA register from the beginning of the component. */
17963 #define SDMMC_DATA_OFST 0x200
17964 /* The address of the SDMMC_DATA register. */
17965 #define SDMMC_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + SDMMC_DATA_OFST))
17966 
17967 #ifndef __ASSEMBLY__
17968 /*
17969  * WARNING: The C register and register group struct declarations are provided for
17970  * convenience and illustrative purposes. They should, however, be used with
17971  * caution as the C language standard provides no guarantees about the alignment or
17972  * atomicity of device memory accesses. The recommended practice for coding device
17973  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
17974  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
17975  * alt_write_dword() functions for 64 bit registers.
17976  *
17977  * The struct declaration for register group ALT_SDMMC.
17978  */
17979 struct ALT_SDMMC_s
17980 {
17981  volatile ALT_SDMMC_CTRL_t CTRL; /* ALT_SDMMC_CTRL */
17982  volatile ALT_SDMMC_PWREN_t PWREN; /* ALT_SDMMC_PWREN */
17983  volatile ALT_SDMMC_CLKDIV_t CLKDIV; /* ALT_SDMMC_CLKDIV */
17984  volatile ALT_SDMMC_CLKSRC_t CLKSRC; /* ALT_SDMMC_CLKSRC */
17985  volatile ALT_SDMMC_CLKENA_t CLKENA; /* ALT_SDMMC_CLKENA */
17986  volatile ALT_SDMMC_TMOUT_t TMOUT; /* ALT_SDMMC_TMOUT */
17987  volatile ALT_SDMMC_CTYPE_t CTYPE; /* ALT_SDMMC_CTYPE */
17988  volatile ALT_SDMMC_BLKSIZ_t BLKSIZ; /* ALT_SDMMC_BLKSIZ */
17989  volatile ALT_SDMMC_BYTCNT_t BYTCNT; /* ALT_SDMMC_BYTCNT */
17990  volatile ALT_SDMMC_INTMASK_t INTMASK; /* ALT_SDMMC_INTMASK */
17991  volatile ALT_SDMMC_CMDARG_t CMDARG; /* ALT_SDMMC_CMDARG */
17992  volatile ALT_SDMMC_CMD_t CMD; /* ALT_SDMMC_CMD */
17993  volatile ALT_SDMMC_RESP0_t RESP0; /* ALT_SDMMC_RESP0 */
17994  volatile ALT_SDMMC_RESP1_t RESP1; /* ALT_SDMMC_RESP1 */
17995  volatile ALT_SDMMC_RESP2_t RESP2; /* ALT_SDMMC_RESP2 */
17996  volatile ALT_SDMMC_RESP3_t RESP3; /* ALT_SDMMC_RESP3 */
17997  volatile ALT_SDMMC_MINTSTS_t MINTSTS; /* ALT_SDMMC_MINTSTS */
17998  volatile ALT_SDMMC_RINTSTS_t RINTSTS; /* ALT_SDMMC_RINTSTS */
17999  volatile ALT_SDMMC_STATUS_t STATUS; /* ALT_SDMMC_STATUS */
18000  volatile ALT_SDMMC_FIFOTH_t FIFOTH; /* ALT_SDMMC_FIFOTH */
18001  volatile ALT_SDMMC_CDETECT_t CDETECT; /* ALT_SDMMC_CDETECT */
18002  volatile ALT_SDMMC_WRTPRT_t WRTPRT; /* ALT_SDMMC_WRTPRT */
18003  volatile ALT_SDMMC_GPIO_t GPIO; /* ALT_SDMMC_GPIO */
18004  volatile ALT_SDMMC_TCBCNT_t TCBCNT; /* ALT_SDMMC_TCBCNT */
18005  volatile ALT_SDMMC_TBBCNT_t TBBCNT; /* ALT_SDMMC_TBBCNT */
18006  volatile ALT_SDMMC_DEBNCE_t DEBNCE; /* ALT_SDMMC_DEBNCE */
18007  volatile ALT_SDMMC_USRID_t USRID; /* ALT_SDMMC_USRID */
18008  volatile ALT_SDMMC_VERID_t VERID; /* ALT_SDMMC_VERID */
18009  volatile ALT_SDMMC_HCON_t HCON; /* ALT_SDMMC_HCON */
18010  volatile ALT_SDMMC_UHS_REG_t UHS_REG; /* ALT_SDMMC_UHS_REG */
18011  volatile ALT_SDMMC_RST_N_t RST_n; /* ALT_SDMMC_RST_N */
18012  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
18013  volatile ALT_SDMMC_BMOD_t BMOD; /* ALT_SDMMC_BMOD */
18014  volatile ALT_SDMMC_PLDMND_t PLDMND; /* ALT_SDMMC_PLDMND */
18015  volatile ALT_SDMMC_DBADDR_t DBADDR; /* ALT_SDMMC_DBADDR */
18016  volatile ALT_SDMMC_IDSTS_t IDSTS; /* ALT_SDMMC_IDSTS */
18017  volatile ALT_SDMMC_IDINTEN_t IDINTEN; /* ALT_SDMMC_IDINTEN */
18018  volatile ALT_SDMMC_DSCADDR_t DSCADDR; /* ALT_SDMMC_DSCADDR */
18019  volatile ALT_SDMMC_BUFADDR_t BUFADDR; /* ALT_SDMMC_BUFADDR */
18020  volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
18021  volatile ALT_SDMMC_CARDTHRCTL_t CARDTHRCTL; /* ALT_SDMMC_CARDTHRCTL */
18022  volatile ALT_SDMMC_BACK_END_POWER_R_t BACK_END_POWER_R; /* ALT_SDMMC_BACK_END_POWER_R */
18023  volatile ALT_SDMMC_UHS_REG_EXT_t UHS_REG_EXT; /* ALT_SDMMC_UHS_REG_EXT */
18024  volatile ALT_SDMMC_EMMC_DDR_REG_t EMMC_DDR_REG; /* ALT_SDMMC_EMMC_DDR_REG */
18025  volatile ALT_SDMMC_ENABLE_SHIFT_t ENABLE_SHIFT; /* ALT_SDMMC_ENABLE_SHIFT */
18026  volatile uint32_t _pad_0x114_0x1ff[59]; /* *UNDEFINED* */
18027  volatile SDMMC_DATA_t DATA; /* SDMMC_DATA */
18028  volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
18029 };
18030 
18031 /* The typedef declaration for register group ALT_SDMMC. */
18032 typedef struct ALT_SDMMC_s ALT_SDMMC_t;
18033 /* The struct declaration for the raw register contents of register group ALT_SDMMC. */
18034 struct ALT_SDMMC_raw_s
18035 {
18036  volatile uint32_t CTRL; /* ALT_SDMMC_CTRL */
18037  volatile uint32_t PWREN; /* ALT_SDMMC_PWREN */
18038  volatile uint32_t CLKDIV; /* ALT_SDMMC_CLKDIV */
18039  volatile uint32_t CLKSRC; /* ALT_SDMMC_CLKSRC */
18040  volatile uint32_t CLKENA; /* ALT_SDMMC_CLKENA */
18041  volatile uint32_t TMOUT; /* ALT_SDMMC_TMOUT */
18042  volatile uint32_t CTYPE; /* ALT_SDMMC_CTYPE */
18043  volatile uint32_t BLKSIZ; /* ALT_SDMMC_BLKSIZ */
18044  volatile uint32_t BYTCNT; /* ALT_SDMMC_BYTCNT */
18045  volatile uint32_t INTMASK; /* ALT_SDMMC_INTMASK */
18046  volatile uint32_t CMDARG; /* ALT_SDMMC_CMDARG */
18047  volatile uint32_t CMD; /* ALT_SDMMC_CMD */
18048  volatile uint32_t RESP0; /* ALT_SDMMC_RESP0 */
18049  volatile uint32_t RESP1; /* ALT_SDMMC_RESP1 */
18050  volatile uint32_t RESP2; /* ALT_SDMMC_RESP2 */
18051  volatile uint32_t RESP3; /* ALT_SDMMC_RESP3 */
18052  volatile uint32_t MINTSTS; /* ALT_SDMMC_MINTSTS */
18053  volatile uint32_t RINTSTS; /* ALT_SDMMC_RINTSTS */
18054  volatile uint32_t STATUS; /* ALT_SDMMC_STATUS */
18055  volatile uint32_t FIFOTH; /* ALT_SDMMC_FIFOTH */
18056  volatile uint32_t CDETECT; /* ALT_SDMMC_CDETECT */
18057  volatile uint32_t WRTPRT; /* ALT_SDMMC_WRTPRT */
18058  volatile uint32_t GPIO; /* ALT_SDMMC_GPIO */
18059  volatile uint32_t TCBCNT; /* ALT_SDMMC_TCBCNT */
18060  volatile uint32_t TBBCNT; /* ALT_SDMMC_TBBCNT */
18061  volatile uint32_t DEBNCE; /* ALT_SDMMC_DEBNCE */
18062  volatile uint32_t USRID; /* ALT_SDMMC_USRID */
18063  volatile uint32_t VERID; /* ALT_SDMMC_VERID */
18064  volatile uint32_t HCON; /* ALT_SDMMC_HCON */
18065  volatile uint32_t UHS_REG; /* ALT_SDMMC_UHS_REG */
18066  volatile uint32_t RST_n; /* ALT_SDMMC_RST_N */
18067  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
18068  volatile uint32_t BMOD; /* ALT_SDMMC_BMOD */
18069  volatile uint32_t PLDMND; /* ALT_SDMMC_PLDMND */
18070  volatile uint32_t DBADDR; /* ALT_SDMMC_DBADDR */
18071  volatile uint32_t IDSTS; /* ALT_SDMMC_IDSTS */
18072  volatile uint32_t IDINTEN; /* ALT_SDMMC_IDINTEN */
18073  volatile uint32_t DSCADDR; /* ALT_SDMMC_DSCADDR */
18074  volatile uint32_t BUFADDR; /* ALT_SDMMC_BUFADDR */
18075  volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
18076  volatile uint32_t CARDTHRCTL; /* ALT_SDMMC_CARDTHRCTL */
18077  volatile uint32_t BACK_END_POWER_R; /* ALT_SDMMC_BACK_END_POWER_R */
18078  volatile uint32_t UHS_REG_EXT; /* ALT_SDMMC_UHS_REG_EXT */
18079  volatile uint32_t EMMC_DDR_REG; /* ALT_SDMMC_EMMC_DDR_REG */
18080  volatile uint32_t ENABLE_SHIFT; /* ALT_SDMMC_ENABLE_SHIFT */
18081  volatile uint32_t _pad_0x114_0x1ff[59]; /* *UNDEFINED* */
18082  volatile uint32_t DATA; /* SDMMC_DATA */
18083  volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
18084 };
18085 
18086 /* The typedef declaration for the raw register contents of register group ALT_SDMMC. */
18087 typedef struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;
18088 #endif /* __ASSEMBLY__ */
18089 
18090 
18091 #ifdef __cplusplus
18092 }
18093 #endif /* __cplusplus */
18094 #endif /* __ALT_SOCAL_SDMMC_H__ */
18095