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20.1
Arria 10 SoC Hardware Manager
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alt_clock_manager.h
Go to the documentation of this file.
1
/******************************************************************************
2
*
3
* Copyright 2013 Altera Corporation. All Rights Reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are met:
7
*
8
* 1. Redistributions of source code must retain the above copyright notice,
9
* this list of conditions and the following disclaimer.
10
*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
12
* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
16
* may be used to endorse or promote products derived from this software without
17
* specific prior written permission.
18
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
31
******************************************************************************/
32
33
/*
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* $Id: //acds/rel/20.1std/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_clock_manager.h#1 $
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*/
36
42
#ifndef __ALT_CLK_MGR_H__
43
#define __ALT_CLK_MGR_H__
44
45
#include "hwlib.h"
46
#include "
alt_clock_group.h
"
47
48
#ifdef __cplusplus
49
extern
"C"
50
{
51
#endif
/* __cplusplus */
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61
/******************************************************************************/
66
typedef
uint32_t
alt_freq_t
;
67
68
/******************************************************************************/
73
typedef
enum
ALT_CLK_e
74
{
75
/* Clock Input Pins */
76
ALT_CLK_IN_PIN_OSC1
,
87
ALT_CLK_IN_PIN_OSC2
,
98
/* FPGA Clock Sources External to HPS */
99
ALT_CLK_F2H_PERIPH_REF,
100
/*<! Alternate clock source from FPGA
101
* for HPS Peripheral PLL. */
102
103
ALT_CLK_F2H_SDRAM_REF,
104
/*<! Alternate clock source from FPGA
105
* for HPS SDRAM PLL. */
106
107
108
/* Other Clock Sources External to HPS */
109
ALT_CLK_IN_PIN_JTAG
,
115
ALT_CLK_IN_PIN_ULPI0
,
122
ALT_CLK_IN_PIN_ULPI1
,
129
ALT_CLK_IN_PIN_EMAC0_RX
,
135
ALT_CLK_IN_PIN_EMAC1_RX
,
142
/* PLLs */
143
ALT_CLK_MAIN_PLL
,
150
ALT_CLK_PERIPHERAL_PLL
,
158
ALT_CLK_SDRAM_PLL
,
165
/* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
166
* directly from the osc_clk_1_HPS pin */
167
ALT_CLK_OSC1
,
177
/* Main Clock Group - The following clocks are derived from the Main PLL. */
178
ALT_CLK_MAIN_PLL_C0
,
181
ALT_CLK_MAIN_PLL_C1
,
184
ALT_CLK_MAIN_PLL_C2
,
187
ALT_CLK_MAIN_PLL_C3
,
190
ALT_CLK_MAIN_PLL_C4
,
193
ALT_CLK_MAIN_PLL_C5
,
196
ALT_CLK_MPU
,
203
ALT_CLK_MPU_L2_RAM
,
208
ALT_CLK_MPU_PERIPH
,
215
ALT_CLK_L3_MAIN
,
221
ALT_CLK_L3_MP
,
226
ALT_CLK_L3_SP
,
231
ALT_CLK_L4_MAIN
,
238
ALT_CLK_L4_MP
,
243
ALT_CLK_L4_SP
,
248
ALT_CLK_DBG_BASE
,
254
ALT_CLK_DBG_AT
,
261
ALT_CLK_DBG_TRACE
,
267
ALT_CLK_DBG_TIMER
,
273
ALT_CLK_DBG
,
280
ALT_CLK_MAIN_QSPI
,
287
ALT_CLK_MAIN_NAND_SDMMC
,
294
ALT_CLK_CFG
,
299
ALT_CLK_H2F_USER0
,
305
/* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
306
ALT_CLK_PERIPHERAL_PLL_C0
,
309
ALT_CLK_PERIPHERAL_PLL_C1
,
312
ALT_CLK_PERIPHERAL_PLL_C2
,
315
ALT_CLK_PERIPHERAL_PLL_C3
,
318
ALT_CLK_PERIPHERAL_PLL_C4
,
321
ALT_CLK_PERIPHERAL_PLL_C5
,
324
ALT_CLK_USB_MP
,
329
ALT_CLK_SPI_M
,
334
ALT_CLK_QSPI
,
339
ALT_CLK_NAND_X
,
345
ALT_CLK_NAND
,
351
ALT_CLK_SDMMC
,
356
ALT_CLK_EMAC0
,
363
ALT_CLK_EMAC1
,
370
ALT_CLK_CAN0
,
376
ALT_CLK_CAN1
,
382
ALT_CLK_GPIO_DB
,
388
ALT_CLK_H2F_USER1
,
396
/* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
397
ALT_CLK_SDRAM_PLL_C0
,
400
ALT_CLK_SDRAM_PLL_C1
,
403
ALT_CLK_SDRAM_PLL_C2
,
406
ALT_CLK_SDRAM_PLL_C3
,
409
ALT_CLK_SDRAM_PLL_C4
,
412
ALT_CLK_SDRAM_PLL_C5
,
415
ALT_CLK_DDR_DQS
,
423
ALT_CLK_DDR_2X_DQS
,
429
ALT_CLK_DDR_DQ
,
435
ALT_CLK_H2F_USER2
,
442
/* Clock Output Pins */
443
ALT_CLK_OUT_PIN_EMAC0_TX
,
449
ALT_CLK_OUT_PIN_EMAC1_TX
,
455
ALT_CLK_OUT_PIN_SDMMC
,
461
ALT_CLK_OUT_PIN_I2C0_SCL
,
467
ALT_CLK_OUT_PIN_I2C1_SCL
,
473
ALT_CLK_OUT_PIN_I2C2_SCL
,
479
ALT_CLK_OUT_PIN_I2C3_SCL
,
485
ALT_CLK_OUT_PIN_SPIM0
,
491
ALT_CLK_OUT_PIN_SPIM1
,
497
ALT_CLK_OUT_PIN_QSPI
,
503
ALT_CLK_UNKNOWN
504
}
ALT_CLK_t
;
505
506
/******************************************************************************/
514
/******************************************************************************/
520
typedef
enum
ALT_CLK_PLL_LOCK_STATUS_e
521
{
522
ALT_MAIN_PLL_LOCK_ACHV
= 0x00000001,
527
ALT_PERIPH_PLL_LOCK_ACHV
= 0x00000002,
532
ALT_SDR_PLL_LOCK_ACHV
= 0x00000004,
537
ALT_MAIN_PLL_LOCK_LOST
= 0x00000008,
542
ALT_PERIPH_PLL_LOCK_LOST
= 0x00000010,
547
ALT_SDR_PLL_LOCK_LOST
= 0x00000020
552
}
ALT_CLK_PLL_LOCK_STATUS_t
;
553
554
/******************************************************************************/
573
ALT_STATUS_CODE
alt_clk_lock_status_clear
(
ALT_CLK_PLL_LOCK_STATUS_t
lock_stat_mask);
574
575
/******************************************************************************/
585
uint32_t
alt_clk_lock_status_get
(
void
);
586
587
/******************************************************************************/
608
ALT_STATUS_CODE
alt_clk_pll_is_locked
(ALT_CLK_t pll);
609
612
/******************************************************************************/
650
/******************************************************************************/
655
typedef
enum
ALT_CLK_SAFE_DOMAIN_e
656
{
661
ALT_CLK_DOMAIN_NORMAL
,
666
ALT_CLK_DOMAIN_DEBUG
667
}
ALT_CLK_SAFE_DOMAIN_t
;
668
669
/******************************************************************************/
679
ALT_STATUS_CODE
alt_clk_safe_mode_clear
(
void
);
680
681
/******************************************************************************/
691
bool
alt_clk_is_in_safe_mode
(
ALT_CLK_SAFE_DOMAIN_t
clk_domain);
692
695
/******************************************************************************/
719
/******************************************************************************/
732
ALT_STATUS_CODE
alt_clk_pll_bypass_disable
(ALT_CLK_t pll);
733
734
/******************************************************************************/
753
ALT_STATUS_CODE
alt_clk_pll_bypass_enable
(ALT_CLK_t pll,
754
bool
use_input_mux);
755
756
/******************************************************************************/
774
ALT_STATUS_CODE
alt_clk_pll_is_bypassed
(ALT_CLK_t pll);
775
778
/******************************************************************************/
823
/******************************************************************************/
838
ALT_STATUS_CODE
alt_clk_clock_disable
(ALT_CLK_t clk);
839
840
/******************************************************************************/
853
ALT_STATUS_CODE
alt_clk_clock_enable
(ALT_CLK_t clk);
854
855
/******************************************************************************/
867
ALT_STATUS_CODE
alt_clk_is_enabled
(ALT_CLK_t clk);
868
871
/******************************************************************************/
918
/******************************************************************************/
935
ALT_CLK_t
alt_clk_source_get
(ALT_CLK_t clk);
936
937
/******************************************************************************/
957
ALT_STATUS_CODE
alt_clk_source_set
(ALT_CLK_t clk,
958
ALT_CLK_t ref_clk);
959
962
/******************************************************************************/
971
/******************************************************************************/
998
ALT_STATUS_CODE
alt_clk_ext_clk_freq_set
(ALT_CLK_t clk,
999
alt_freq_t freq);
1000
1001
/******************************************************************************/
1019
alt_freq_t
alt_clk_ext_clk_freq_get
(ALT_CLK_t clk);
1020
1021
/******************************************************************************/
1026
typedef
struct
ALT_CLK_PLL_CFG_s
1027
{
1028
ALT_CLK_t
ref_clk
;
1029
uint32_t
mult
;
1032
uint32_t
div
;
1035
uint32_t
cntrs
[6];
1038
uint32_t
pshift
[6];
1042
}
ALT_CLK_PLL_CFG_t
;
1043
1044
/******************************************************************************/
1058
ALT_STATUS_CODE
alt_clk_pll_cfg_get
(ALT_CLK_t pll,
1059
ALT_CLK_PLL_CFG_t
* pll_cfg);
1060
1061
/******************************************************************************/
1076
ALT_STATUS_CODE
alt_clk_pll_cfg_set
(ALT_CLK_t pll,
1077
const
ALT_CLK_PLL_CFG_t
* pll_cfg);
1078
1079
/******************************************************************************/
1097
ALT_STATUS_CODE
alt_clk_pll_vco_cfg_get
(ALT_CLK_t pll,
1098
uint32_t* mult,
1099
uint32_t* div);
1100
1101
/******************************************************************************/
1118
ALT_STATUS_CODE
alt_clk_pll_vco_cfg_set
(ALT_CLK_t pll,
1119
uint32_t mult,
1120
uint32_t div);
1121
1122
/******************************************************************************/
1140
ALT_STATUS_CODE
alt_clk_pll_vco_freq_get
(ALT_CLK_t pll,
1141
alt_freq_t* freq);
1142
1143
/******************************************************************************/
1152
uint32_t
alt_clk_pll_guard_band_get
(ALT_CLK_t pll);
1153
1154
/******************************************************************************/
1184
ALT_STATUS_CODE
alt_clk_pll_guard_band_set
(ALT_CLK_t pll,
1185
uint32_t guard_band);
1186
1187
/******************************************************************************/
1210
ALT_STATUS_CODE
alt_clk_divider_get
(ALT_CLK_t clk,
1211
uint32_t* div);
1212
1213
/******************************************************************************/
1238
ALT_STATUS_CODE
alt_clk_divider_set
(ALT_CLK_t clk,
1239
uint32_t div);
1240
1241
/******************************************************************************/
1259
ALT_STATUS_CODE
alt_clk_freq_get
(ALT_CLK_t clk,
1260
alt_freq_t* freq);
1261
1264
/******************************************************************************/
1309
/******************************************************************************/
1331
ALT_STATUS_CODE
alt_clk_irq_disable
(
ALT_CLK_PLL_LOCK_STATUS_t
lock_stat_mask);
1332
1333
/******************************************************************************/
1355
ALT_STATUS_CODE
alt_clk_irq_enable
(
ALT_CLK_PLL_LOCK_STATUS_t
lock_stat_mask);
1356
1359
/******************************************************************************/
1390
/******************************************************************************/
1409
ALT_STATUS_CODE
alt_clk_group_cfg_raw_get
(
ALT_CLK_GRP_t
clk_group,
1410
ALT_CLK_GROUP_RAW_CFG_t
* clk_group_raw_cfg);
1411
1412
/******************************************************************************/
1431
ALT_STATUS_CODE
alt_clk_group_cfg_raw_set
(
const
ALT_CLK_GROUP_RAW_CFG_t
* clk_group_raw_cfg);
1432
1433
/******************************************************************************/
1443
ALT_STATUS_CODE
alt_clk_clkmgr_init
(
void
);
1444
1445
/******************************************************************************/
1453
ALT_STATUS_CODE
alt_clk_clkmgr_uninit
(
void
);
1457
#ifdef __cplusplus
1458
}
1459
1460
#endif
/* __cplusplus */
1461
#endif
/* __ALT_CLK_MGR_H__ */
include
soc_cv_av
alt_clock_manager.h
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