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alt_l2_p310.h
Go to the documentation of this file.
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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/*
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* $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/alt_l2_p310.h#1 $
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*/
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#ifndef __ALT_L2_P310_H__
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#define __ALT_L2_P310_H__
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#include <stdbool.h>
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#include "socal/hps.h"
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#ifdef soc_a10
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#define ALT_MPUL2_OFST ALT_L2_REGS_L2TYPE_ADDR
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#endif
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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/*****************************************************************************
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/ ARM Level 2 Cache Controller L2C-310 Register Interface
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/ These definitions should match the values given in DDI0246H_l2c310_r3p3_trm.pdf
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/ provided by ARM
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*****************************************************************************/
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/* Cache ID Register
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* The Cache ID Registers is a read only register
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31:24] | Implementer | ID of IP provider. Should be 0x41 (ARM)
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* [23:16] | Reserved | SBZ/RAZ
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* [15:10] | Cache ID |
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* [9:6] | Part Number |
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* [5:0] | RTL release |
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* Cache ID Register Address */
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#define ALT_L2_CACHE_ID_OFST 0x000
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#define ALT_L2_CACHE_ID_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
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/* Cache ID Register - Implementer Mask */
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#define ALT_L2_CACHE_ID_IMPLEMENTER_MASK 0xFF000000
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/* Cache ID Register - Cache ID Mask */
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#define ALT_L2_CACHE_ID_CACHE_ID_MASK 0x0000FC00
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/* Cache ID Register - Part Number Mask */
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#define ALT_L2_CACHE_ID_PART_NUMBER_MASK 0x000003C0
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/* Cache ID Register - RTL Relase Mask */
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#define ALT_L2_CACHE_ID_RTL_RELEASE_MASK 0x0000003F
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#define ALT_L2_CACHE_TYPE_OFST 0x004
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#define ALT_L2_CACHE_TYPE_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
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/* The Cache Control Register is a read and write register
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31:1] | Reservered | SBZ/RAZ
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* [0] | L2 Cache Enable | */
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/* Cache Control Register Address */
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#define ALT_L2_CACHE_REG1_CNTRL_OFST 0x100
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#define ALT_L2_CACHE_REG1_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_CNTRL_OFST)
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/* Cache Control Register - Enable */
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#define ALT_L2_CACHE_REG1_CNTRL_DISABLE 0x0
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#define ALT_L2_CACHE_REG1_CNTRL_ENABLE 0x1
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#define ALT_L2_CACHE_REG1_CNTRL_ENABLE_MASK 0x1
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/* Aux Cache Control Register
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* The Aux Cache Control Register is a read and write register
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31] | Reservered | SBZ/RAZ
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* [30] | Early BRESP Enabled |
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* [29] | Inst Prefetch Enable |
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* [28] | Data Prefetch Enable |
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* [27] | N/S Int Access Cntrl |
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* [26] | N/S Lockdown Enable |
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* [25] | Cache Replacement Policy |
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* [24:23] | Force Write Allocate |
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* [22] | Shared Attr Override En |
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* [21] | Parity Enable |
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* [20] | Event Monitor Bus Enable |
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* [19:17] | Way Size |
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* [16] | Associativity |
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* [15:14] | Reserved |
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* [13] | Shared Attribute Inv En |
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* [12] | Exclusive Cache Config |
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* [11] | Store Buffer Dev Limit En |
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* [10] | High Priority for SO En |
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* [9:1] | Reserved |
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* [0] | Full Line of Zero En | */
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/* Aux Cache Control Register Address */
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_OFST 0x104
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_AUX_CNTRL_OFST)
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_EN_MASK 0x40000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_ENABLE 0x40000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_EN_MASK 0x20000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_ENABLE 0x20000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_EN_MASK 0x10000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_ENABLE 0x10000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_MASK 0x08000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_ENABLE 0x08000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_EN_MASK 0x04000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_ENABLE 0x04000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_MASK 0x02000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RANDOM 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RR 0x02000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_MASK 0x01800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_AWCACHE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA0 0x00800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA1 0x01000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_00 0x01800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_EN_MASK 0x00400000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_ENABLE 0x00400000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_EN_MASK 0x00200000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_ENABLE 0x00200000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_EN_MASK 0x00100000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_ENABLE 0x00100000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_MASK 0x000E0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_16KB 0x00020000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_32KB 0x00040000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_64KB 0x00060000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_128KB 0x00080000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_256B 0x000A0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_512KB 0x000C0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_MASK 0x00010000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_8WAY 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_16WAY 0x00010000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_EN_MASK 0x00002000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_ENABLE 0x00002000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_MASK 0x00001000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_ENABLE 0x00001000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_EN_MASK 0x00000800
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_ENABLE 0x00000800
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_EN_MASK 0x00000400
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_ENABLE 0x00000400
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_EN_MASK 0x1
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_ENABLE 0x1
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_DISABLE 0
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/* Tag and Data RAM Latency Control Register
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* The Tag and Data RAM Latency Control Register is a read and write register
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31:11] | Reservered | SBZ/RAZ
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* [10:8] | RAM Write Access Latency |
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* [7] | Reserved |
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* [10:8] | RAM Read Access Latency |
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* [3] | Reserved |
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* [2:0] | RAM Setup Latency | */
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST 0x108
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST)
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_MASK 0x00000700
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_2 0x00000100
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_3 0x00000200
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_4 0x00000300
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_5 0x00000400
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_6 0x00000500
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_7 0x00000600
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_8 0x00000700
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_MASK 0x00000070
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_2 0x00000010
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_3 0x00000020
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_4 0x00000030
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_5 0x00000040
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_6 0x00000050
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_7 0x00000060
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_8 0x00000070
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_MASK 0x00000007
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_2 0x00000001
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_3 0x00000002
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_4 0x00000003
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_5 0x00000004
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_6 0x00000005
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_7 0x00000006
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_8 0x00000007
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_LSB 8
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_LSB 4
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_LSB 0
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_2 0x00000001
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_3 0x00000002
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_4 0x00000003
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_5 0x00000004
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_6 0x00000005
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_7 0x00000006
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_8 0x00000007
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#define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST 0x10C
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#define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST)
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/* Event Counter Control Register
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31:3] | Reservered | SBZ/RAZ
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* [2:1] | Counter Reset |
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* [0] | Event Counter Enable | */
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_OFST 0x200
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT_CNTRL_OFST)
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_MASK 0x00000006
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_0 0x00000002
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_1 0x00000004
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_EN_MASK 1
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/* Enable Counter */
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ENABLE 1
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_DISABLE 0
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264
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/* Event Counter Configuration Registers
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* Bits Field Description
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* :-------|:--------------------------|:-----------------------------------------
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* [31:6] | Reservered | SBZ/RAZ
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* [5:2] | Counter Event Source |
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* [1:0] | Event Counter Interupt En | */
271
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/* Event Counter Configuration Register Addresses */
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#define ALT_L2_CACHE_REG2_EV_CNT1_CFG_OFST 0x204
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#define ALT_L2_CACHE_REG2_EV_CNT1_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT1_CFG_OFST)
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#define ALT_L2_CACHE_REG2_EV_CNT0_CFG_OFST 0x208
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#define ALT_L2_CACHE_REG2_EV_CNT0_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT0_CFG_OFST)
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_MASK 0x0000003C
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DISABLE 0x00000000
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_CO 0x00000004
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRHIT 0x00000008
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRREQ 0x0000000C
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWHIT 0x00000010
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWREQ 0x00000014
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWTREQ 0x00000018
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRHIT 0x0000001C
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRREQ 0x00000020
288
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_WA 0x00000024
289
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IPFALLOC 0x00000028
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFHIT 0x0000002C
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFALLOC 0x00000030
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRRCVD 0x00000034
293
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRCONF 0x00000038
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFRCVD 0x0000003C
295
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_MASK 0x3
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_DISABLED 0
297
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_INC 0x00000001
298
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_OF 0x00000002
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_GEN_DIS 0x00000003
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301
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/* Event Counter Registers */
303
#define ALT_L2_CACHE_REG2_EV_CNT1_OFST 0x20C
304
#define ALT_L2_CACHE_REG2_EV_CNT1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT1_OFST)
305
#define ALT_L2_CACHE_REG2_EV_CNT0_OFST 0x210
306
#define ALT_L2_CACHE_REG2_EV_CNT0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT0_OFST)
307
308
/* Interrupt Registers. The following defines are used for the next several registers
309
* Bits Field Description
310
* :-------|:--------------------------|:-----------------------------------------
311
* [31:9] | Reservered | SBZ/RAZ
312
* [8] | DECERR |
313
* [7] | SLVERR |
314
* [6] | ERRRD |
315
* [5] | ERRRT |
316
* [4] | ERRWD |
317
* [3] | ERRWT |
318
* [2] | PARRD |
319
* [1] | PARRT |
320
* [0] | ECNTR | */
321
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#define ALT_L2_CACHE_REG2_INT_DECERR 0x100
323
#define ALT_L2_CACHE_REG2_INT_SLVERR 0x080
324
#define ALT_L2_CACHE_REG2_INT_ERRRD 0x040
325
#define ALT_L2_CACHE_REG2_INT_ERRRT 0x020
326
#define ALT_L2_CACHE_REG2_INT_ERRWD 0x010
327
#define ALT_L2_CACHE_REG2_INT_ERRWT 0x008
328
#define ALT_L2_CACHE_REG2_INT_PARRD 0x004
329
#define ALT_L2_CACHE_REG2_INT_PARRT 0x002
330
#define ALT_L2_CACHE_REG2_INT_ECNTR 0x001
331
332
/* Interrupt Enable Mask Register
333
* See "Interrupt Registers" above */
334
#define ALT_L2_CACHE_REG2_INT_MASK_OFST 0x214
335
#define ALT_L2_CACHE_REG2_INT_MASK_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_OFST)
336
337
/* Interrupt Status Register (Should be RAW_STATUS & INT_MASK
338
* See "Interrupt Registers" above */
339
#define ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST 0x218
340
#define ALT_L2_CACHE_REG2_INT_MASK_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST)
341
342
/* Interrupt Raw Status Register (Excludes Masks)
343
* See "Interrupt Registers" above */
344
#define ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST 0x21C
345
#define ALT_L2_CACHE_REG2_INT_RAW_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST)
346
347
/* Interrupt Clear Status Register
348
* See "Interrupt Registers" above */
349
#define ALT_L2_CACHE_REG2_INT_CLEAR_OFST 0x220
350
#define ALT_L2_CACHE_REG2_INT_CLEAR_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_CLEAR_OFST)
351
352
/* PA Format
353
* Bits Field Description
354
* :-------|:--------------------------|:-----------------------------------------
355
* [31:12] | Tag |
356
* [11:5] | Index |
357
* [4:1] | Reserved |
358
* [0] | Complete | */
359
360
/* Index or Way Format
361
* Bits Field Description
362
* :-------|:--------------------------|:-----------------------------------------
363
* [31:28] | Way |
364
* [27:12] | Reserved |
365
* [11:5] | Index |
366
* [4:1] | Reserved |
367
* [0] | Complete | */
368
369
/* Way Format
370
* Bits Field Description
371
* :-------|:--------------------------|:-----------------------------------------
372
* [31:16] | Reserved |
373
* [15:0] | Way Bits | */
374
375
/* Cache Sync Register
376
* Bits Field Description
377
* :-------|:--------------------------|:-----------------------------------------
378
* [31:1] | Reserved |
379
* [0] | Complete | */
380
#define ALT_L2_CACHE_REG7_CACHE_SYNC_OFST 0x730
381
#define ALT_L2_CACHE_REG7_CACHE_SYNC_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CACHE_SYNC_OFST)
382
383
/* Invalidate Line by Physical Address
384
* See the "PA Format" above for description of the fields of this register */
385
#define ALT_L2_CACHE_REG7_INV_PA_OFST 0x770
386
#define ALT_L2_CACHE_REG7_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_PA_OFST)
387
388
/* Invalidate Line by Way
389
* See the "Way Format" above for description of the fields of this register */
390
#define ALT_L2_CACHE_REG7_INV_WAY_OFST 0x77C
391
#define ALT_L2_CACHE_REG7_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_WAY_OFST)
392
393
/* Clean Line by Physical Address
394
* See the "PA Format" above for description of the fields of this register */
395
#define ALT_L2_CACHE_REG7_CLEAN_PA_OFST 0x7B0
396
#define ALT_L2_CACHE_REG7_CLEAN_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_PA_OFST)
397
398
/* Clean Line by Set/Way
399
* See the "Index or Way Format" above for a description of the fields of this register */
400
#define ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST 0x7B8
401
#define ALT_L2_CACHE_REG7_CLEAN_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST)
402
403
/* Invalidate Line by Way
404
* See the "Way Format" above for description of the fields of this register */
405
#define ALT_L2_CACHE_REG7_CLEAN_WAY_OFST 0x7BC
406
#define ALT_L2_CACHE_REG7_CLEAN_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_WAY_OFST)
407
408
/* Clean and Invalidate Line by Physical Address
409
* See the "PA Format" above for description of the fields of this register */
410
#define ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST 0x7F0
411
#define ALT_L2_CACHE_REG7_CLEAN_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST)
412
413
/* Clean and Invalidate Line by Set/Way
414
* See the "Index or Way Format" above for a description of the fields of this register */
415
#define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST 0x7F8
416
#define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST)
417
418
/* Invalidate Line by Way
419
* See the "Way Format" above for description of the fields of this register */
420
#define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST 0x7FC
421
#define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST)
422
423
/* Lockdown Registers
424
* The format for each of these lockdown registers is the same
425
* Bits Field Description
426
* :-------|:--------------------------|:-----------------------------------------
427
* [31:16] | Reserved |
428
* [15:0] | Way Bits | */
429
430
431
#define ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X) (0x900 + (X)*0x10)
432
#define ALT_L2_CACHE_REG9_D_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X))
433
434
#define ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X) (0x904 + (X)*0x10)
435
#define ALT_L2_CACHE_REG9_I_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X))
436
437
#define ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST 0x900
438
#define ALT_L2_CACHE_REG9_D_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST)
439
440
#define ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST 0x904
441
#define ALT_L2_CACHE_REG9_I_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST)
442
443
#define ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST 0x908
444
#define ALT_L2_CACHE_REG9_D_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST)
445
446
#define ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST 0x90C
447
#define ALT_L2_CACHE_REG9_I_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST)
448
449
#define ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST 0x910
450
#define ALT_L2_CACHE_REG9_D_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST)
451
452
#define ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST 0x914
453
#define ALT_L2_CACHE_REG9_I_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST)
454
455
#define ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST 0x918
456
#define ALT_L2_CACHE_REG9_D_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST)
457
458
#define ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST 0x91C
459
#define ALT_L2_CACHE_REG9_I_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST)
460
461
#define ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST 0x920
462
#define ALT_L2_CACHE_REG9_D_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST)
463
464
#define ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST 0x924
465
#define ALT_L2_CACHE_REG9_I_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST)
466
467
#define ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST 0x928
468
#define ALT_L2_CACHE_REG9_D_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST)
469
470
#define ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST 0x92C
471
#define ALT_L2_CACHE_REG9_I_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST)
472
473
#define ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST 0x930
474
#define ALT_L2_CACHE_REG9_D_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST)
475
476
#define ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST 0x934
477
#define ALT_L2_CACHE_REG9_I_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST)
478
479
#define ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST 0x938
480
#define ALT_L2_CACHE_REG9_D_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST)
481
482
#define ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST 0x93C
483
#define ALT_L2_CACHE_REG9_I_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST)
484
485
/* Lockdown by Line Enable
486
* Bits Field Description
487
* :-------|:--------------------------|:-----------------------------------------
488
* [31:1] | Reserved |
489
* [0] | Enable | */
490
491
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST 0x950
492
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST)
493
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_MASK 0x00000001
494
#define ALT_L2_CACHE_REG9_LOCK_LINE_ENABLE 0x00000001
495
#define ALT_L2_CACHE_REG9_LOCK_LINE_DISABLE 0
496
497
#define ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST 0x954
498
#define ALT_L2_CACHE_REG9_UNLOCK_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST)
499
500
/* Address Filtering Start Register
501
* The Address Filtering Start Register is a read and write register.
502
* Bits Field Description
503
* :-------|:--------------------------|:-----------------------------------------
504
* [31:20] | address_filtering_start | Address filtering start address for
505
* | | bits [31:20] of the filtering address.
506
* [19:1] | Reserved | SBZ/RAZ
507
* [0] | address_filtering_enable | 0 - address filtering disabled
508
* | | 1 - address filtering enabled. */
509
510
/* Address Filtering Start Register Address */
511
#define ALT_L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
512
#define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_OFST) + ALT_L2_CACHE_ADDR_FILTERING_START_OFST))
513
/* Address Filtering Start Register - Start Value Mask */
514
#define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
515
/* Address Filtering Start Register - Reset Start Address Value (1 MB) */
516
#define ALT_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
517
/* Address Filtering Start Register - Enable Flag Mask */
518
#define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
519
/* Address Filtering Start Register - Reset Enable Flag Value (Enabled) */
520
#define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
521
522
/* Address Filtering End Register
523
* The Address Filtering End Register is a read and write register.
524
* Bits Field Description
525
* :-------|:--------------------------|:-----------------------------------------
526
* [31:20] | address_filtering_end | Address filtering end address for bits
527
* | | [31:20] of the filtering address.
528
* [19:0] | Reserved | SBZ/RAZ */
529
530
/* Address Filtering End Register Address */
531
#define ALT_L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
532
#define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_MPUL2_OFST) + ALT_L2_CACHE_ADDR_FILTERING_END_OFST))
533
/* Address Filtering End Register - End Value Mask */
534
#define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
535
/* Address Filtering End Register - Reset End Address Value (3 GiB) */
536
#define ALT_L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
537
538
#ifdef __cplusplus
539
}
540
#endif
/* __cplusplus */
541
#endif
/* __ALT_L2_P310_H__ */
include
alt_l2_p310.h
Generated on Tue Oct 27 2020 08:37:28 for Hardware Libraries by
1.8.2