35 #ifndef __ALT_SOCAL_NAND_H__
36 #define __ALT_SOCAL_NAND_H__
86 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_LSB 0
88 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_MSB 0
90 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_WIDTH 1
92 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_SET_MSK 0x00000001
94 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_CLR_MSK 0xfffffffe
96 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_RESET 0x0
98 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_GET(value) (((value) & 0x00000001) >> 0)
100 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_SET(value) (((value) << 0) & 0x00000001)
113 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_LSB 1
115 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_MSB 1
117 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_WIDTH 1
119 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_SET_MSK 0x00000002
121 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_CLR_MSK 0xfffffffd
123 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_RESET 0x0
125 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_GET(value) (((value) & 0x00000002) >> 1)
127 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_SET(value) (((value) << 1) & 0x00000002)
140 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_LSB 2
142 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_MSB 2
144 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_WIDTH 1
146 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_SET_MSK 0x00000004
148 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_CLR_MSK 0xfffffffb
150 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_RESET 0x0
152 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_GET(value) (((value) & 0x00000004) >> 2)
154 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_SET(value) (((value) << 2) & 0x00000004)
167 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_LSB 3
169 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_MSB 3
171 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_WIDTH 1
173 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_SET_MSK 0x00000008
175 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_CLR_MSK 0xfffffff7
177 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_RESET 0x0
179 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_GET(value) (((value) & 0x00000008) >> 3)
181 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_SET(value) (((value) << 3) & 0x00000008)
195 struct ALT_NAND_CFG_DEVICE_RESET_s
197 volatile uint32_t bank0 : 1;
198 volatile uint32_t bank1 : 1;
199 volatile uint32_t bank2 : 1;
200 volatile uint32_t bank3 : 1;
205 typedef struct ALT_NAND_CFG_DEVICE_RESET_s ALT_NAND_CFG_DEVICE_RESET_t;
209 #define ALT_NAND_CFG_DEVICE_RESET_RESET 0x00000000
211 #define ALT_NAND_CFG_DEVICE_RESET_OFST 0x0
213 #define ALT_NAND_CFG_DEVICE_RESET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_RESET_OFST))
243 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_LSB 0
245 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_MSB 0
247 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_WIDTH 1
249 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_SET_MSK 0x00000001
251 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
253 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_RESET 0x0
255 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
257 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
271 struct ALT_NAND_CFG_TRANSFER_SPARE_REG_s
273 volatile uint32_t flag : 1;
278 typedef struct ALT_NAND_CFG_TRANSFER_SPARE_REG_s ALT_NAND_CFG_TRANSFER_SPARE_REG_t;
282 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_RESET 0x00000000
284 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_OFST 0x10
286 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TRANSFER_SPARE_REG_OFST))
326 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_LSB 0
328 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_MSB 15
330 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_WIDTH 16
332 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
334 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
336 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_RESET 0x1f4
338 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
340 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
354 struct ALT_NAND_CFG_LOAD_WAIT_CNT_s
356 volatile uint32_t value : 16;
361 typedef struct ALT_NAND_CFG_LOAD_WAIT_CNT_s ALT_NAND_CFG_LOAD_WAIT_CNT_t;
365 #define ALT_NAND_CFG_LOAD_WAIT_CNT_RESET 0x000001f4
367 #define ALT_NAND_CFG_LOAD_WAIT_CNT_OFST 0x20
369 #define ALT_NAND_CFG_LOAD_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_LOAD_WAIT_CNT_OFST))
413 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
415 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
417 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
419 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
421 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
423 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f40
425 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
427 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
441 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
443 volatile uint32_t value : 16;
448 typedef struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
452 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_RESET 0x00001f40
454 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
456 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST))
500 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
502 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
504 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
506 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
508 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
510 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f40
512 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
514 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
528 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
530 volatile uint32_t value : 16;
535 typedef struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
539 #define ALT_NAND_CFG_ERASE_WAIT_CNT_RESET 0x00001f40
541 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
543 #define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST))
573 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
575 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
577 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
579 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
581 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
583 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
585 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
587 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
601 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
603 volatile uint32_t value : 16;
608 typedef struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
612 #define ALT_NAND_CFG_INT_MON_CYCCNT_RESET 0x000001f4
614 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
616 #define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST))
647 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_LSB 0
649 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_MSB 0
651 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_WIDTH 1
653 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_SET_MSK 0x00000001
655 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_CLR_MSK 0xfffffffe
657 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_RESET 0x1
659 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_GET(value) (((value) & 0x00000001) >> 0)
661 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_SET(value) (((value) << 0) & 0x00000001)
676 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_LSB 1
678 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_MSB 1
680 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_WIDTH 1
682 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_SET_MSK 0x00000002
684 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_CLR_MSK 0xfffffffd
686 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_RESET 0x0
688 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_GET(value) (((value) & 0x00000002) >> 1)
690 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_SET(value) (((value) << 1) & 0x00000002)
705 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_LSB 2
707 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_MSB 2
709 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_WIDTH 1
711 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_SET_MSK 0x00000004
713 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_CLR_MSK 0xfffffffb
715 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_RESET 0x0
717 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_GET(value) (((value) & 0x00000004) >> 2)
719 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_SET(value) (((value) << 2) & 0x00000004)
734 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_LSB 3
736 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_MSB 3
738 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_WIDTH 1
740 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_SET_MSK 0x00000008
742 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_CLR_MSK 0xfffffff7
744 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_RESET 0x0
746 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_GET(value) (((value) & 0x00000008) >> 3)
748 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_SET(value) (((value) << 3) & 0x00000008)
762 struct ALT_NAND_CFG_RB_PIN_ENABLED_s
764 volatile uint32_t bank0 : 1;
765 volatile uint32_t bank1 : 1;
766 volatile uint32_t bank2 : 1;
767 volatile uint32_t bank3 : 1;
772 typedef struct ALT_NAND_CFG_RB_PIN_ENABLED_s ALT_NAND_CFG_RB_PIN_ENABLED_t;
776 #define ALT_NAND_CFG_RB_PIN_ENABLED_RESET 0x00000001
778 #define ALT_NAND_CFG_RB_PIN_ENABLED_OFST 0x60
780 #define ALT_NAND_CFG_RB_PIN_ENABLED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RB_PIN_ENABLED_OFST))
808 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_LSB 0
810 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_MSB 0
812 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_WIDTH 1
814 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_SET_MSK 0x00000001
816 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_CLR_MSK 0xfffffffe
818 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_RESET 0x0
820 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_GET(value) (((value) & 0x00000001) >> 0)
822 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_SET(value) (((value) << 0) & 0x00000001)
836 struct ALT_NAND_CFG_MULTIPLANE_OPERATION_s
838 volatile uint32_t flag : 1;
843 typedef struct ALT_NAND_CFG_MULTIPLANE_OPERATION_s ALT_NAND_CFG_MULTIPLANE_OPERATION_t;
847 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_RESET 0x00000000
849 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_OFST 0x70
851 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_OPERATION_OFST))
887 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_LSB 0
889 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_MSB 0
891 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_WIDTH 1
893 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_SET_MSK 0x00000001
895 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_CLR_MSK 0xfffffffe
897 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_RESET 0x0
899 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
901 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
915 struct ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_s
917 volatile uint32_t flag : 1;
922 typedef struct ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_s ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_t;
926 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_RESET 0x00000000
928 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_OFST 0x80
930 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_OFST))
954 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_LSB 0
956 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_MSB 0
958 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_WIDTH 1
960 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_SET_MSK 0x00000001
962 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_CLR_MSK 0xfffffffe
964 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_RESET 0x0
966 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
968 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
982 struct ALT_NAND_CFG_COPYBACK_DISABLE_s
984 volatile uint32_t flag : 1;
989 typedef struct ALT_NAND_CFG_COPYBACK_DISABLE_s ALT_NAND_CFG_COPYBACK_DISABLE_t;
993 #define ALT_NAND_CFG_COPYBACK_DISABLE_RESET 0x00000000
995 #define ALT_NAND_CFG_COPYBACK_DISABLE_OFST 0x90
997 #define ALT_NAND_CFG_COPYBACK_DISABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_COPYBACK_DISABLE_OFST))
1021 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_LSB 0
1023 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_MSB 0
1025 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_WIDTH 1
1027 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_SET_MSK 0x00000001
1029 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_CLR_MSK 0xfffffffe
1031 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_RESET 0x0
1033 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1035 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1037 #ifndef __ASSEMBLY__
1049 struct ALT_NAND_CFG_CACHE_WRITE_ENABLE_s
1051 volatile uint32_t flag : 1;
1056 typedef struct ALT_NAND_CFG_CACHE_WRITE_ENABLE_s ALT_NAND_CFG_CACHE_WRITE_ENABLE_t;
1060 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_RESET 0x00000000
1062 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_OFST 0xa0
1064 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CACHE_WRITE_ENABLE_OFST))
1088 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_LSB 0
1090 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_MSB 0
1092 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_WIDTH 1
1094 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_SET_MSK 0x00000001
1096 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_CLR_MSK 0xfffffffe
1098 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_RESET 0x0
1100 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1102 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1104 #ifndef __ASSEMBLY__
1116 struct ALT_NAND_CFG_CACHE_READ_ENABLE_s
1118 volatile uint32_t flag : 1;
1123 typedef struct ALT_NAND_CFG_CACHE_READ_ENABLE_s ALT_NAND_CFG_CACHE_READ_ENABLE_t;
1127 #define ALT_NAND_CFG_CACHE_READ_ENABLE_RESET 0x00000000
1129 #define ALT_NAND_CFG_CACHE_READ_ENABLE_OFST 0xb0
1131 #define ALT_NAND_CFG_CACHE_READ_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CACHE_READ_ENABLE_OFST))
1157 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_LSB 0
1159 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_MSB 0
1161 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_WIDTH 1
1163 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_SET_MSK 0x00000001
1165 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_CLR_MSK 0xfffffffe
1167 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_RESET 0x1
1169 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1171 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1196 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_LSB 4
1198 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_MSB 15
1200 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_WIDTH 12
1202 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_SET_MSK 0x0000fff0
1204 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_CLR_MSK 0xffff000f
1206 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_RESET 0x0
1208 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_GET(value) (((value) & 0x0000fff0) >> 4)
1210 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_SET(value) (((value) << 4) & 0x0000fff0)
1212 #ifndef __ASSEMBLY__
1224 struct ALT_NAND_CFG_PREFETCH_MODE_s
1226 volatile uint32_t prefetch_en : 1;
1228 volatile uint32_t prefetch_burst_length : 12;
1233 typedef struct ALT_NAND_CFG_PREFETCH_MODE_s ALT_NAND_CFG_PREFETCH_MODE_t;
1237 #define ALT_NAND_CFG_PREFETCH_MODE_RESET 0x00000001
1239 #define ALT_NAND_CFG_PREFETCH_MODE_OFST 0xc0
1241 #define ALT_NAND_CFG_PREFETCH_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PREFETCH_MODE_OFST))
1269 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_LSB 0
1271 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_MSB 0
1273 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_WIDTH 1
1275 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_SET_MSK 0x00000001
1277 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1279 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_RESET 0x0
1281 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1283 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1285 #ifndef __ASSEMBLY__
1297 struct ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_s
1299 volatile uint32_t flag : 1;
1304 typedef struct ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_s ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_t;
1308 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_RESET 0x00000000
1310 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_OFST 0xd0
1312 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_OFST))
1346 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_LSB 0
1348 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_MSB 0
1350 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_WIDTH 1
1352 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_SET_MSK 0x00000001
1354 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_CLR_MSK 0xfffffffe
1356 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_RESET 0x1
1358 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1360 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1362 #ifndef __ASSEMBLY__
1374 struct ALT_NAND_CFG_ECC_ENABLE_s
1376 volatile uint32_t flag : 1;
1381 typedef struct ALT_NAND_CFG_ECC_ENABLE_s ALT_NAND_CFG_ECC_ENABLE_t;
1385 #define ALT_NAND_CFG_ECC_ENABLE_RESET 0x00000001
1387 #define ALT_NAND_CFG_ECC_ENABLE_OFST 0xe0
1389 #define ALT_NAND_CFG_ECC_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ECC_ENABLE_OFST))
1417 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_LSB 0
1419 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_MSB 0
1421 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_WIDTH 1
1423 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_SET_MSK 0x00000001
1425 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_CLR_MSK 0xfffffffe
1427 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_RESET 0x0
1429 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1431 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1444 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_LSB 4
1446 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_MSB 4
1448 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_WIDTH 1
1450 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_SET_MSK 0x00000010
1452 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_CLR_MSK 0xffffffef
1454 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_RESET 0x0
1456 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_GET(value) (((value) & 0x00000010) >> 4)
1458 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_SET(value) (((value) << 4) & 0x00000010)
1471 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_LSB 8
1473 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_MSB 8
1475 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_WIDTH 1
1477 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_SET_MSK 0x00000100
1479 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_CLR_MSK 0xfffffeff
1481 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_RESET 0x0
1483 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_GET(value) (((value) & 0x00000100) >> 8)
1485 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_SET(value) (((value) << 8) & 0x00000100)
1487 #ifndef __ASSEMBLY__
1499 struct ALT_NAND_CFG_GLOBAL_INT_ENABLE_s
1501 volatile uint32_t flag : 1;
1503 volatile uint32_t timeout_disable : 1;
1505 volatile uint32_t error_rpt_disable : 1;
1510 typedef struct ALT_NAND_CFG_GLOBAL_INT_ENABLE_s ALT_NAND_CFG_GLOBAL_INT_ENABLE_t;
1514 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_RESET 0x00000000
1516 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_OFST 0xf0
1518 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_GLOBAL_INT_ENABLE_OFST))
1547 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1549 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1551 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1553 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1555 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1557 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1559 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1561 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1575 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1577 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1579 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1581 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1583 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1585 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1587 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1589 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1591 #ifndef __ASSEMBLY__
1603 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1605 volatile uint32_t we_2_re : 6;
1607 volatile uint32_t twhr2 : 6;
1612 typedef struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1616 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_RESET 0x00001432
1618 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1620 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST))
1649 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1651 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 6
1653 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 7
1655 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000007f
1657 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffff80
1659 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1661 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000007f) >> 0)
1663 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000007f)
1679 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1681 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1683 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1685 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1687 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1689 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1691 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1693 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1695 #ifndef __ASSEMBLY__
1707 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1709 volatile uint32_t addr_2_data : 7;
1711 volatile uint32_t tcwaw : 6;
1716 typedef struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1720 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_RESET 0x00001432
1722 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1724 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST))
1753 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1755 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1757 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1759 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1761 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1763 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1765 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1767 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1769 #ifndef __ASSEMBLY__
1781 struct ALT_NAND_CFG_RE_2_WE_s
1783 volatile uint32_t value : 6;
1788 typedef struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1792 #define ALT_NAND_CFG_RE_2_WE_RESET 0x00000032
1794 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1796 #define ALT_NAND_CFG_RE_2_WE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RE_2_WE_OFST))
1824 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1826 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1828 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1830 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1832 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1834 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1836 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1838 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1840 #ifndef __ASSEMBLY__
1852 struct ALT_NAND_CFG_ACC_CLKS_s
1854 volatile uint32_t value : 4;
1859 typedef struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1863 #define ALT_NAND_CFG_ACC_CLKS_RESET 0x00000000
1865 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1867 #define ALT_NAND_CFG_ACC_CLKS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ACC_CLKS_OFST))
1909 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1911 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1913 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1915 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1917 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1919 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1921 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1923 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1925 #ifndef __ASSEMBLY__
1937 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1939 volatile uint32_t value : 3;
1944 typedef struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1948 #define ALT_NAND_CFG_NUMBER_OF_PLANES_RESET 0x00000000
1950 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1952 #define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST))
1982 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1984 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1986 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1988 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1990 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1992 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1994 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1996 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1998 #ifndef __ASSEMBLY__
2010 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
2012 volatile uint32_t value : 16;
2017 typedef struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
2021 #define ALT_NAND_CFG_PAGES_PER_BLOCK_RESET 0x00000000
2023 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
2025 #define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST))
2057 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
2059 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
2061 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
2063 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
2065 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
2067 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
2069 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
2071 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
2073 #ifndef __ASSEMBLY__
2085 struct ALT_NAND_CFG_DEVICE_WIDTH_s
2087 volatile uint32_t value : 2;
2092 typedef struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
2096 #define ALT_NAND_CFG_DEVICE_WIDTH_RESET 0x00000003
2098 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
2100 #define ALT_NAND_CFG_DEVICE_WIDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_WIDTH_OFST))
2130 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
2132 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
2134 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
2136 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2138 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2140 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
2142 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2144 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2146 #ifndef __ASSEMBLY__
2158 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
2160 volatile uint32_t value : 16;
2165 typedef struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
2169 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_RESET 0x00000000
2171 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
2173 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST))
2203 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
2205 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
2207 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
2209 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2211 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2213 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
2215 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2217 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2219 #ifndef __ASSEMBLY__
2231 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
2233 volatile uint32_t value : 16;
2238 typedef struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
2242 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_RESET 0x00000000
2244 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2246 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST))
2276 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2278 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2280 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2282 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2284 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2286 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2288 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2290 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2303 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4
2305 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4
2307 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1
2309 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010
2311 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef
2313 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0
2315 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4)
2317 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010)
2319 #ifndef __ASSEMBLY__
2331 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2333 volatile uint32_t flag : 1;
2335 volatile uint32_t four : 1;
2340 typedef struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2344 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000
2346 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2348 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST))
2378 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2380 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2382 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2384 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2386 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2388 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2390 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2392 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2394 #ifndef __ASSEMBLY__
2406 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2408 volatile uint32_t flag : 1;
2413 typedef struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2417 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_RESET 0x00000000
2419 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2421 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST))
2462 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2464 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2466 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2468 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2470 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2472 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2474 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2476 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2509 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB 16
2511 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB 31
2513 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH 16
2515 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK 0xffff0000
2517 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK 0x0000ffff
2519 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET 0x0
2521 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value) (((value) & 0xffff0000) >> 16)
2523 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value) (((value) << 16) & 0xffff0000)
2525 #ifndef __ASSEMBLY__
2537 struct ALT_NAND_CFG_ECC_CORRECTION_s
2539 volatile uint32_t value : 8;
2541 volatile uint32_t erase_threshold : 16;
2545 typedef struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2549 #define ALT_NAND_CFG_ECC_CORRECTION_RESET 0x00000008
2551 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2553 #define ALT_NAND_CFG_ECC_CORRECTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ECC_CORRECTION_OFST))
2667 #define ALT_NAND_CFG_READ_MODE_VALUE_LSB 0
2669 #define ALT_NAND_CFG_READ_MODE_VALUE_MSB 3
2671 #define ALT_NAND_CFG_READ_MODE_VALUE_WIDTH 4
2673 #define ALT_NAND_CFG_READ_MODE_VALUE_SET_MSK 0x0000000f
2675 #define ALT_NAND_CFG_READ_MODE_VALUE_CLR_MSK 0xfffffff0
2677 #define ALT_NAND_CFG_READ_MODE_VALUE_RESET 0x0
2679 #define ALT_NAND_CFG_READ_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2681 #define ALT_NAND_CFG_READ_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2683 #ifndef __ASSEMBLY__
2695 struct ALT_NAND_CFG_READ_MODE_s
2697 volatile uint32_t value : 4;
2702 typedef struct ALT_NAND_CFG_READ_MODE_s ALT_NAND_CFG_READ_MODE_t;
2706 #define ALT_NAND_CFG_READ_MODE_RESET 0x00000000
2708 #define ALT_NAND_CFG_READ_MODE_OFST 0x1c0
2710 #define ALT_NAND_CFG_READ_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_READ_MODE_OFST))
2787 #define ALT_NAND_CFG_WRITE_MODE_VALUE_LSB 0
2789 #define ALT_NAND_CFG_WRITE_MODE_VALUE_MSB 3
2791 #define ALT_NAND_CFG_WRITE_MODE_VALUE_WIDTH 4
2793 #define ALT_NAND_CFG_WRITE_MODE_VALUE_SET_MSK 0x0000000f
2795 #define ALT_NAND_CFG_WRITE_MODE_VALUE_CLR_MSK 0xfffffff0
2797 #define ALT_NAND_CFG_WRITE_MODE_VALUE_RESET 0x0
2799 #define ALT_NAND_CFG_WRITE_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2801 #define ALT_NAND_CFG_WRITE_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2803 #ifndef __ASSEMBLY__
2815 struct ALT_NAND_CFG_WRITE_MODE_s
2817 volatile uint32_t value : 4;
2822 typedef struct ALT_NAND_CFG_WRITE_MODE_s ALT_NAND_CFG_WRITE_MODE_t;
2826 #define ALT_NAND_CFG_WRITE_MODE_RESET 0x00000000
2828 #define ALT_NAND_CFG_WRITE_MODE_OFST 0x1d0
2830 #define ALT_NAND_CFG_WRITE_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WRITE_MODE_OFST))
2908 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_LSB 0
2910 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_MSB 3
2912 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_WIDTH 4
2914 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_SET_MSK 0x0000000f
2916 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_CLR_MSK 0xfffffff0
2918 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_RESET 0x0
2920 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2922 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2924 #ifndef __ASSEMBLY__
2936 struct ALT_NAND_CFG_COPYBACK_MODE_s
2938 volatile uint32_t value : 4;
2943 typedef struct ALT_NAND_CFG_COPYBACK_MODE_s ALT_NAND_CFG_COPYBACK_MODE_t;
2947 #define ALT_NAND_CFG_COPYBACK_MODE_RESET 0x00000000
2949 #define ALT_NAND_CFG_COPYBACK_MODE_OFST 0x1e0
2951 #define ALT_NAND_CFG_COPYBACK_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_COPYBACK_MODE_OFST))
2984 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2986 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2988 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2990 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2992 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2994 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2996 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2998 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3000 #ifndef __ASSEMBLY__
3012 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
3014 volatile uint32_t value : 5;
3019 typedef struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
3023 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_RESET 0x00000012
3025 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
3027 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST))
3061 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
3063 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
3065 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
3067 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
3069 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
3071 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
3073 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3075 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3077 #ifndef __ASSEMBLY__
3089 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
3091 volatile uint32_t value : 5;
3096 typedef struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
3100 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_RESET 0x0000000c
3102 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
3104 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST))
3139 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
3141 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
3143 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
3145 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
3147 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
3149 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
3151 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
3153 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
3155 #ifndef __ASSEMBLY__
3167 struct ALT_NAND_CFG_MAX_RD_DELAY_s
3169 volatile uint32_t value : 4;
3174 typedef struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
3178 #define ALT_NAND_CFG_MAX_RD_DELAY_RESET 0x00000000
3180 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
3182 #define ALT_NAND_CFG_MAX_RD_DELAY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MAX_RD_DELAY_OFST))
3223 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
3225 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
3227 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
3229 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
3231 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
3233 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
3235 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3237 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3250 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12
3252 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17
3254 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6
3256 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000
3258 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff
3260 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa
3262 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12)
3264 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000)
3266 #ifndef __ASSEMBLY__
3278 struct ALT_NAND_CFG_CS_SETUP_CNT_s
3280 volatile uint32_t value : 5;
3282 volatile uint32_t twb : 6;
3287 typedef struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
3291 #define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003
3293 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
3295 #define ALT_NAND_CFG_CS_SETUP_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CS_SETUP_CNT_OFST))
3331 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
3333 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
3335 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
3337 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
3339 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
3341 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
3343 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3345 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3347 #ifndef __ASSEMBLY__
3359 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
3361 volatile uint32_t value : 6;
3366 typedef struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
3370 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_RESET 0x00000000
3372 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
3374 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST))
3400 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
3402 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
3404 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
3406 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
3408 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
3410 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
3412 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3414 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3416 #ifndef __ASSEMBLY__
3428 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
3430 volatile uint32_t value : 16;
3435 typedef struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
3439 #define ALT_NAND_CFG_SPARE_AREA_MARKER_RESET 0x0000ffff
3441 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
3443 #define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST))
3469 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
3471 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
3473 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
3475 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
3477 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
3479 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
3481 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
3483 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
3485 #ifndef __ASSEMBLY__
3497 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
3499 volatile uint32_t value : 3;
3504 typedef struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
3508 #define ALT_NAND_CFG_DEVICES_CONNECTED_RESET 0x00000000
3510 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
3512 #define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST))
3553 #define ALT_NAND_CFG_DIE_MASK_VALUE_LSB 0
3555 #define ALT_NAND_CFG_DIE_MASK_VALUE_MSB 15
3557 #define ALT_NAND_CFG_DIE_MASK_VALUE_WIDTH 16
3559 #define ALT_NAND_CFG_DIE_MASK_VALUE_SET_MSK 0x0000ffff
3561 #define ALT_NAND_CFG_DIE_MASK_VALUE_CLR_MSK 0xffff0000
3563 #define ALT_NAND_CFG_DIE_MASK_VALUE_RESET 0x0
3565 #define ALT_NAND_CFG_DIE_MASK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3567 #define ALT_NAND_CFG_DIE_MASK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3569 #ifndef __ASSEMBLY__
3581 struct ALT_NAND_CFG_DIE_MASK_s
3583 volatile uint32_t value : 16;
3588 typedef struct ALT_NAND_CFG_DIE_MASK_s ALT_NAND_CFG_DIE_MASK_t;
3592 #define ALT_NAND_CFG_DIE_MASK_RESET 0x00000000
3594 #define ALT_NAND_CFG_DIE_MASK_OFST 0x260
3596 #define ALT_NAND_CFG_DIE_MASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DIE_MASK_OFST))
3628 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3630 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3632 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3634 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3636 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3638 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3640 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3642 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3644 #ifndef __ASSEMBLY__
3656 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3658 volatile uint32_t value : 16;
3663 typedef struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3667 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_RESET 0x00000001
3669 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3671 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST))
3704 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_LSB 0
3706 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_MSB 0
3708 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_WIDTH 1
3710 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_SET_MSK 0x00000001
3712 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_CLR_MSK 0xfffffffe
3714 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_RESET 0x1
3716 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3718 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3720 #ifndef __ASSEMBLY__
3732 struct ALT_NAND_CFG_WRITE_PROTECT_s
3734 volatile uint32_t flag : 1;
3739 typedef struct ALT_NAND_CFG_WRITE_PROTECT_s ALT_NAND_CFG_WRITE_PROTECT_t;
3743 #define ALT_NAND_CFG_WRITE_PROTECT_RESET 0x00000001
3745 #define ALT_NAND_CFG_WRITE_PROTECT_OFST 0x280
3747 #define ALT_NAND_CFG_WRITE_PROTECT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WRITE_PROTECT_OFST))
3778 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3780 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3782 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3784 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3786 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3788 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3790 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3792 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3794 #ifndef __ASSEMBLY__
3806 struct ALT_NAND_CFG_RE_2_RE_s
3808 volatile uint32_t value : 6;
3813 typedef struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3817 #define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032
3819 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3821 #define ALT_NAND_CFG_RE_2_RE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RE_2_RE_OFST))
3852 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_LSB 0
3854 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_MSB 15
3856 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_WIDTH 16
3858 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_SET_MSK 0x0000ffff
3860 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_CLR_MSK 0xffff0000
3862 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_RESET 0x13b
3864 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3866 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3868 #ifndef __ASSEMBLY__
3880 struct ALT_NAND_CFG_POR_RESET_COUNT_s
3882 volatile uint32_t value : 16;
3887 typedef struct ALT_NAND_CFG_POR_RESET_COUNT_s ALT_NAND_CFG_POR_RESET_COUNT_t;
3891 #define ALT_NAND_CFG_POR_RESET_COUNT_RESET 0x0000013b
3893 #define ALT_NAND_CFG_POR_RESET_COUNT_OFST 0x2a0
3895 #define ALT_NAND_CFG_POR_RESET_COUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_POR_RESET_COUNT_OFST))
3927 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_LSB 0
3929 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_MSB 15
3931 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_WIDTH 16
3933 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_SET_MSK 0x0000ffff
3935 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_CLR_MSK 0xffff0000
3937 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_RESET 0x5b9a
3939 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3941 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3943 #ifndef __ASSEMBLY__
3955 struct ALT_NAND_CFG_WATCHDOG_RESET_COUNT_s
3957 volatile uint32_t value : 16;
3962 typedef struct ALT_NAND_CFG_WATCHDOG_RESET_COUNT_s ALT_NAND_CFG_WATCHDOG_RESET_COUNT_t;
3966 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_RESET 0x00005b9a
3968 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_OFST 0x2b0
3970 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WATCHDOG_RESET_COUNT_OFST))
3972 #ifndef __ASSEMBLY__
3984 struct ALT_NAND_CFG_s
3986 volatile ALT_NAND_CFG_DEVICE_RESET_t device_reset;
3987 volatile uint32_t _pad_0x4_0xf[3];
3988 volatile ALT_NAND_CFG_TRANSFER_SPARE_REG_t transfer_spare_reg;
3989 volatile uint32_t _pad_0x14_0x1f[3];
3990 volatile ALT_NAND_CFG_LOAD_WAIT_CNT_t load_wait_cnt;
3991 volatile uint32_t _pad_0x24_0x2f[3];
3992 volatile ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt;
3993 volatile uint32_t _pad_0x34_0x3f[3];
3994 volatile ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt;
3995 volatile uint32_t _pad_0x44_0x4f[3];
3996 volatile ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt;
3997 volatile uint32_t _pad_0x54_0x5f[3];
3998 volatile ALT_NAND_CFG_RB_PIN_ENABLED_t rb_pin_enabled;
3999 volatile uint32_t _pad_0x64_0x6f[3];
4000 volatile ALT_NAND_CFG_MULTIPLANE_OPERATION_t multiplane_operation;
4001 volatile uint32_t _pad_0x74_0x7f[3];
4002 volatile ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_t multiplane_read_enable;
4003 volatile uint32_t _pad_0x84_0x8f[3];
4004 volatile ALT_NAND_CFG_COPYBACK_DISABLE_t copyback_disable;
4005 volatile uint32_t _pad_0x94_0x9f[3];
4006 volatile ALT_NAND_CFG_CACHE_WRITE_ENABLE_t cache_write_enable;
4007 volatile uint32_t _pad_0xa4_0xaf[3];
4008 volatile ALT_NAND_CFG_CACHE_READ_ENABLE_t cache_read_enable;
4009 volatile uint32_t _pad_0xb4_0xbf[3];
4010 volatile ALT_NAND_CFG_PREFETCH_MODE_t prefetch_mode;
4011 volatile uint32_t _pad_0xc4_0xcf[3];
4012 volatile ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_t chip_enable_dont_care;
4013 volatile uint32_t _pad_0xd4_0xdf[3];
4014 volatile ALT_NAND_CFG_ECC_ENABLE_t ecc_enable;
4015 volatile uint32_t _pad_0xe4_0xef[3];
4016 volatile ALT_NAND_CFG_GLOBAL_INT_ENABLE_t global_int_enable;
4017 volatile uint32_t _pad_0xf4_0xff[3];
4018 volatile ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re;
4019 volatile uint32_t _pad_0x104_0x10f[3];
4020 volatile ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data;
4021 volatile uint32_t _pad_0x114_0x11f[3];
4022 volatile ALT_NAND_CFG_RE_2_WE_t re_2_we;
4023 volatile uint32_t _pad_0x124_0x12f[3];
4024 volatile ALT_NAND_CFG_ACC_CLKS_t acc_clks;
4025 volatile uint32_t _pad_0x134_0x13f[3];
4026 volatile ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes;
4027 volatile uint32_t _pad_0x144_0x14f[3];
4028 volatile ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block;
4029 volatile uint32_t _pad_0x154_0x15f[3];
4030 volatile ALT_NAND_CFG_DEVICE_WIDTH_t device_width;
4031 volatile uint32_t _pad_0x164_0x16f[3];
4032 volatile ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size;
4033 volatile uint32_t _pad_0x174_0x17f[3];
4034 volatile ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size;
4035 volatile uint32_t _pad_0x184_0x18f[3];
4036 volatile ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles;
4037 volatile uint32_t _pad_0x194_0x19f[3];
4038 volatile ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict;
4039 volatile uint32_t _pad_0x1a4_0x1af[3];
4040 volatile ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction;
4041 volatile uint32_t _pad_0x1b4_0x1bf[3];
4042 volatile ALT_NAND_CFG_READ_MODE_t read_mode;
4043 volatile uint32_t _pad_0x1c4_0x1cf[3];
4044 volatile ALT_NAND_CFG_WRITE_MODE_t write_mode;
4045 volatile uint32_t _pad_0x1d4_0x1df[3];
4046 volatile ALT_NAND_CFG_COPYBACK_MODE_t copyback_mode;
4047 volatile uint32_t _pad_0x1e4_0x1ef[3];
4048 volatile ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt;
4049 volatile uint32_t _pad_0x1f4_0x1ff[3];
4050 volatile ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt;
4051 volatile uint32_t _pad_0x204_0x20f[3];
4052 volatile ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay;
4053 volatile uint32_t _pad_0x214_0x21f[3];
4054 volatile ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt;
4055 volatile uint32_t _pad_0x224_0x22f[3];
4056 volatile ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes;
4057 volatile uint32_t _pad_0x234_0x23f[3];
4058 volatile ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker;
4059 volatile uint32_t _pad_0x244_0x24f[3];
4060 volatile ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected;
4061 volatile uint32_t _pad_0x254_0x25f[3];
4062 volatile ALT_NAND_CFG_DIE_MASK_t die_mask;
4063 volatile uint32_t _pad_0x264_0x26f[3];
4064 volatile ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane;
4065 volatile uint32_t _pad_0x274_0x27f[3];
4066 volatile ALT_NAND_CFG_WRITE_PROTECT_t write_protect;
4067 volatile uint32_t _pad_0x284_0x28f[3];
4068 volatile ALT_NAND_CFG_RE_2_RE_t re_2_re;
4069 volatile uint32_t _pad_0x294_0x29f[3];
4070 volatile ALT_NAND_CFG_POR_RESET_COUNT_t por_reset_count;
4071 volatile uint32_t _pad_0x2a4_0x2af[3];
4072 volatile ALT_NAND_CFG_WATCHDOG_RESET_COUNT_t watchdog_reset_count;
4076 typedef struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
4078 struct ALT_NAND_CFG_raw_s
4080 volatile uint32_t device_reset;
4081 volatile uint32_t _pad_0x4_0xf[3];
4082 volatile uint32_t transfer_spare_reg;
4083 volatile uint32_t _pad_0x14_0x1f[3];
4084 volatile uint32_t load_wait_cnt;
4085 volatile uint32_t _pad_0x24_0x2f[3];
4086 volatile uint32_t program_wait_cnt;
4087 volatile uint32_t _pad_0x34_0x3f[3];
4088 volatile uint32_t erase_wait_cnt;
4089 volatile uint32_t _pad_0x44_0x4f[3];
4090 volatile uint32_t int_mon_cyccnt;
4091 volatile uint32_t _pad_0x54_0x5f[3];
4092 volatile uint32_t rb_pin_enabled;
4093 volatile uint32_t _pad_0x64_0x6f[3];
4094 volatile uint32_t multiplane_operation;
4095 volatile uint32_t _pad_0x74_0x7f[3];
4096 volatile uint32_t multiplane_read_enable;
4097 volatile uint32_t _pad_0x84_0x8f[3];
4098 volatile uint32_t copyback_disable;
4099 volatile uint32_t _pad_0x94_0x9f[3];
4100 volatile uint32_t cache_write_enable;
4101 volatile uint32_t _pad_0xa4_0xaf[3];
4102 volatile uint32_t cache_read_enable;
4103 volatile uint32_t _pad_0xb4_0xbf[3];
4104 volatile uint32_t prefetch_mode;
4105 volatile uint32_t _pad_0xc4_0xcf[3];
4106 volatile uint32_t chip_enable_dont_care;
4107 volatile uint32_t _pad_0xd4_0xdf[3];
4108 volatile uint32_t ecc_enable;
4109 volatile uint32_t _pad_0xe4_0xef[3];
4110 volatile uint32_t global_int_enable;
4111 volatile uint32_t _pad_0xf4_0xff[3];
4112 volatile uint32_t twhr2_and_we_2_re;
4113 volatile uint32_t _pad_0x104_0x10f[3];
4114 volatile uint32_t tcwaw_and_addr_2_data;
4115 volatile uint32_t _pad_0x114_0x11f[3];
4116 volatile uint32_t re_2_we;
4117 volatile uint32_t _pad_0x124_0x12f[3];
4118 volatile uint32_t acc_clks;
4119 volatile uint32_t _pad_0x134_0x13f[3];
4120 volatile uint32_t number_of_planes;
4121 volatile uint32_t _pad_0x144_0x14f[3];
4122 volatile uint32_t pages_per_block;
4123 volatile uint32_t _pad_0x154_0x15f[3];
4124 volatile uint32_t device_width;
4125 volatile uint32_t _pad_0x164_0x16f[3];
4126 volatile uint32_t device_main_area_size;
4127 volatile uint32_t _pad_0x174_0x17f[3];
4128 volatile uint32_t device_spare_area_size;
4129 volatile uint32_t _pad_0x184_0x18f[3];
4130 volatile uint32_t two_row_addr_cycles;
4131 volatile uint32_t _pad_0x194_0x19f[3];
4132 volatile uint32_t multiplane_addr_restrict;
4133 volatile uint32_t _pad_0x1a4_0x1af[3];
4134 volatile uint32_t ecc_correction;
4135 volatile uint32_t _pad_0x1b4_0x1bf[3];
4136 volatile uint32_t read_mode;
4137 volatile uint32_t _pad_0x1c4_0x1cf[3];
4138 volatile uint32_t write_mode;
4139 volatile uint32_t _pad_0x1d4_0x1df[3];
4140 volatile uint32_t copyback_mode;
4141 volatile uint32_t _pad_0x1e4_0x1ef[3];
4142 volatile uint32_t rdwr_en_lo_cnt;
4143 volatile uint32_t _pad_0x1f4_0x1ff[3];
4144 volatile uint32_t rdwr_en_hi_cnt;
4145 volatile uint32_t _pad_0x204_0x20f[3];
4146 volatile uint32_t max_rd_delay;
4147 volatile uint32_t _pad_0x214_0x21f[3];
4148 volatile uint32_t cs_setup_cnt;
4149 volatile uint32_t _pad_0x224_0x22f[3];
4150 volatile uint32_t spare_area_skip_bytes;
4151 volatile uint32_t _pad_0x234_0x23f[3];
4152 volatile uint32_t spare_area_marker;
4153 volatile uint32_t _pad_0x244_0x24f[3];
4154 volatile uint32_t devices_connected;
4155 volatile uint32_t _pad_0x254_0x25f[3];
4156 volatile uint32_t die_mask;
4157 volatile uint32_t _pad_0x264_0x26f[3];
4158 volatile uint32_t first_block_of_next_plane;
4159 volatile uint32_t _pad_0x274_0x27f[3];
4160 volatile uint32_t write_protect;
4161 volatile uint32_t _pad_0x284_0x28f[3];
4162 volatile uint32_t re_2_re;
4163 volatile uint32_t _pad_0x294_0x29f[3];
4164 volatile uint32_t por_reset_count;
4165 volatile uint32_t _pad_0x2a4_0x2af[3];
4166 volatile uint32_t watchdog_reset_count;
4170 typedef struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
4203 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
4205 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
4207 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
4209 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
4211 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
4213 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
4215 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4217 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4219 #ifndef __ASSEMBLY__
4231 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
4233 volatile uint32_t value : 8;
4238 typedef struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
4242 #define ALT_NAND_PARAM_MANUFACTURER_ID_RESET 0x00000000
4244 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
4246 #define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST))
4268 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
4270 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
4272 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
4274 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
4276 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
4278 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
4280 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4282 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4284 #ifndef __ASSEMBLY__
4296 struct ALT_NAND_PARAM_DEVICE_ID_s
4298 const volatile uint32_t value : 8;
4303 typedef struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
4307 #define ALT_NAND_PARAM_DEVICE_ID_RESET 0x00000000
4309 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
4311 #define ALT_NAND_PARAM_DEVICE_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_ID_OFST))
4335 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
4337 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
4339 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
4341 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
4343 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
4345 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
4347 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4349 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4351 #ifndef __ASSEMBLY__
4363 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
4365 const volatile uint32_t value : 8;
4370 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
4374 #define ALT_NAND_PARAM_DEVICE_PARAM_0_RESET 0x00000000
4376 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
4378 #define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST))
4402 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
4404 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
4406 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
4408 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
4410 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
4412 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
4414 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4416 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4418 #ifndef __ASSEMBLY__
4430 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
4432 const volatile uint32_t value : 8;
4437 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
4441 #define ALT_NAND_PARAM_DEVICE_PARAM_1_RESET 0x00000000
4443 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
4445 #define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST))
4467 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
4469 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
4471 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
4473 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
4475 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
4477 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
4479 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4481 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4483 #ifndef __ASSEMBLY__
4495 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
4497 const volatile uint32_t value : 8;
4502 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
4506 #define ALT_NAND_PARAM_DEVICE_PARAM_2_RESET 0x00000000
4508 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
4510 #define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST))
4538 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
4540 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
4542 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
4544 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
4546 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
4548 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
4550 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4552 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4554 #ifndef __ASSEMBLY__
4566 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
4568 const volatile uint32_t value : 16;
4573 typedef struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
4577 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_RESET 0x00000000
4579 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
4581 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST))
4609 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
4611 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
4613 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
4615 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
4617 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
4619 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
4621 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4623 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4625 #ifndef __ASSEMBLY__
4637 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
4639 const volatile uint32_t value : 16;
4644 typedef struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
4648 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_RESET 0x00000000
4650 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
4652 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST))
4677 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
4679 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 7
4681 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 8
4683 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x000000ff
4685 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffffff00
4687 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
4689 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4691 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4702 #define ALT_NAND_PARAM_REVISION_MINOR_LSB 8
4704 #define ALT_NAND_PARAM_REVISION_MINOR_MSB 15
4706 #define ALT_NAND_PARAM_REVISION_MINOR_WIDTH 8
4708 #define ALT_NAND_PARAM_REVISION_MINOR_SET_MSK 0x0000ff00
4710 #define ALT_NAND_PARAM_REVISION_MINOR_CLR_MSK 0xffff00ff
4712 #define ALT_NAND_PARAM_REVISION_MINOR_RESET 0x1
4714 #define ALT_NAND_PARAM_REVISION_MINOR_GET(value) (((value) & 0x0000ff00) >> 8)
4716 #define ALT_NAND_PARAM_REVISION_MINOR_SET(value) (((value) << 8) & 0x0000ff00)
4718 #ifndef __ASSEMBLY__
4730 struct ALT_NAND_PARAM_REVISION_s
4732 const volatile uint32_t value : 8;
4733 const volatile uint32_t minor : 8;
4738 typedef struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
4742 #define ALT_NAND_PARAM_REVISION_RESET 0x00000105
4744 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4746 #define ALT_NAND_PARAM_REVISION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_REVISION_OFST))
4798 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_LSB 0
4800 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_MSB 15
4802 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_WIDTH 16
4804 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_SET_MSK 0x0000ffff
4806 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_CLR_MSK 0xffff0000
4808 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_RESET 0x0
4810 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4812 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4814 #ifndef __ASSEMBLY__
4826 struct ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_s
4828 const volatile uint32_t value : 16;
4833 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_s ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_t;
4837 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_RESET 0x00000000
4839 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_OFST 0x80
4841 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_OFST))
4891 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_LSB 0
4893 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_MSB 15
4895 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_WIDTH 16
4897 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_SET_MSK 0x0000ffff
4899 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_CLR_MSK 0xffff0000
4901 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_RESET 0x0
4903 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4905 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4907 #ifndef __ASSEMBLY__
4919 struct ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_s
4921 const volatile uint32_t value : 16;
4926 typedef struct ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_t;
4930 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_RESET 0x00000000
4932 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_OFST 0x90
4934 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_OFST))
4970 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_LSB 0
4972 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_MSB 5
4974 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_WIDTH 6
4976 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_SET_MSK 0x0000003f
4978 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_CLR_MSK 0xffffffc0
4980 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_RESET 0x0
4982 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4984 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4986 #ifndef __ASSEMBLY__
4998 struct ALT_NAND_PARAM_ONFI_TIMING_MODE_s
5000 const volatile uint32_t value : 6;
5005 typedef struct ALT_NAND_PARAM_ONFI_TIMING_MODE_s ALT_NAND_PARAM_ONFI_TIMING_MODE_t;
5009 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_RESET 0x00000000
5011 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_OFST 0xa0
5013 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_TIMING_MODE_OFST))
5049 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_LSB 0
5051 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_MSB 5
5053 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_WIDTH 6
5055 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_SET_MSK 0x0000003f
5057 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_CLR_MSK 0xffffffc0
5059 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_RESET 0x0
5061 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
5063 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
5065 #ifndef __ASSEMBLY__
5077 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_s
5079 const volatile uint32_t value : 6;
5084 typedef struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_t;
5088 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_RESET 0x00000000
5090 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_OFST 0xb0
5092 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_OFST))
5125 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_LSB 0
5127 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_MSB 7
5129 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
5131 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
5133 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
5135 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
5137 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
5139 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
5154 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_LSB 8
5156 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_MSB 8
5158 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
5160 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
5162 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
5164 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
5166 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
5168 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
5187 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_LSB 12
5189 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_MSB 12
5191 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_WIDTH 1
5193 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_SET_MSK 0x00001000
5195 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_CLR_MSK 0xffffefff
5197 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_RESET 0x0
5199 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_GET(value) (((value) & 0x00001000) >> 12)
5201 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_SET(value) (((value) << 12) & 0x00001000)
5217 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_LSB 16
5219 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_MSB 16
5221 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_WIDTH 1
5223 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET_MSK 0x00010000
5225 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_CLR_MSK 0xfffeffff
5227 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_RESET 0x0
5229 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_GET(value) (((value) & 0x00010000) >> 16)
5231 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET(value) (((value) << 16) & 0x00010000)
5249 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_LSB 20
5251 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_MSB 20
5253 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_WIDTH 1
5255 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET_MSK 0x00100000
5257 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_CLR_MSK 0xffefffff
5259 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_RESET 0x0
5261 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_GET(value) (((value) & 0x00100000) >> 20)
5263 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET(value) (((value) << 20) & 0x00100000)
5265 #ifndef __ASSEMBLY__
5277 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_s
5279 const volatile uint32_t no_of_luns : 8;
5280 volatile uint32_t onfi_device : 1;
5282 volatile uint32_t prog_page_reg_clear_enhancement : 1;
5284 volatile uint32_t onfi_jedec_multiplane_erase_seq : 1;
5286 volatile uint32_t ce_reduction_volume_addr_and_change : 1;
5291 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_t;
5295 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_RESET 0x00000000
5297 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_OFST 0xc0
5299 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_OFST))
5327 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_LSB 0
5329 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_MSB 15
5331 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_WIDTH 16
5333 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
5335 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
5337 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_RESET 0x0
5339 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5341 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5343 #ifndef __ASSEMBLY__
5355 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_s
5357 const volatile uint32_t value : 16;
5362 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_t;
5366 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_RESET 0x00000000
5368 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_OFST 0xd0
5370 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_OFST))
5398 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_LSB 0
5400 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_MSB 15
5402 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_WIDTH 16
5404 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
5406 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
5408 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_RESET 0x0
5410 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5412 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5414 #ifndef __ASSEMBLY__
5426 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_s
5428 const volatile uint32_t value : 16;
5433 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_t;
5437 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_RESET 0x00000000
5439 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_OFST 0xe0
5441 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_OFST))
5484 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
5486 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
5488 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
5490 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
5492 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
5494 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x2
5496 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
5498 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
5509 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
5511 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
5513 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
5515 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
5517 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
5519 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
5521 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
5523 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
5534 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
5536 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
5538 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
5540 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
5542 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
5544 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x1
5546 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
5548 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
5559 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
5561 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
5563 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
5565 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
5567 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
5569 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
5571 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
5573 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
5584 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
5586 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
5588 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
5590 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
5592 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
5594 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
5596 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
5598 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
5609 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
5611 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
5613 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
5615 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
5617 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
5619 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
5621 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
5623 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
5634 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
5636 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
5638 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
5640 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
5642 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
5644 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
5646 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
5648 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
5659 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
5661 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
5663 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
5665 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
5667 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
5669 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
5671 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
5673 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
5684 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
5686 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
5688 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
5690 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
5692 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
5694 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
5696 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
5698 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
5700 #ifndef __ASSEMBLY__
5712 struct ALT_NAND_PARAM_FEATURES_s
5714 const volatile uint32_t n_banks : 2;
5716 const volatile uint32_t dma : 1;
5717 const volatile uint32_t cmd_dma : 1;
5718 const volatile uint32_t partition : 1;
5719 const volatile uint32_t xdma_sideband : 1;
5720 const volatile uint32_t gpreg : 1;
5721 const volatile uint32_t index_addr : 1;
5722 const volatile uint32_t dfi_intf : 1;
5723 const volatile uint32_t lba : 1;
5728 typedef struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
5732 #define ALT_NAND_PARAM_FEATURES_RESET 0x000008c2
5734 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
5736 #define ALT_NAND_PARAM_FEATURES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_FEATURES_OFST))
5738 #ifndef __ASSEMBLY__
5750 struct ALT_NAND_PARAM_s
5752 volatile ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id;
5753 volatile uint32_t _pad_0x4_0xf[3];
5754 volatile ALT_NAND_PARAM_DEVICE_ID_t device_id;
5755 volatile uint32_t _pad_0x14_0x1f[3];
5756 volatile ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0;
5757 volatile uint32_t _pad_0x24_0x2f[3];
5758 volatile ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1;
5759 volatile uint32_t _pad_0x34_0x3f[3];
5760 volatile ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2;
5761 volatile uint32_t _pad_0x44_0x4f[3];
5762 volatile ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size;
5763 volatile uint32_t _pad_0x54_0x5f[3];
5764 volatile ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size;
5765 volatile uint32_t _pad_0x64_0x6f[3];
5766 volatile ALT_NAND_PARAM_REVISION_t revision;
5767 volatile uint32_t _pad_0x74_0x7f[3];
5768 volatile ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_t onfi_device_features;
5769 volatile uint32_t _pad_0x84_0x8f[3];
5770 volatile ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_t onfi_optional_commands;
5771 volatile uint32_t _pad_0x94_0x9f[3];
5772 volatile ALT_NAND_PARAM_ONFI_TIMING_MODE_t onfi_timing_mode;
5773 volatile uint32_t _pad_0xa4_0xaf[3];
5774 volatile ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_t onfi_pgm_cache_timing_mode;
5775 volatile uint32_t _pad_0xb4_0xbf[3];
5776 volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_t onfi_device_no_of_luns;
5777 volatile uint32_t _pad_0xc4_0xcf[3];
5778 volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l;
5779 volatile uint32_t _pad_0xd4_0xdf[3];
5780 volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u;
5781 volatile uint32_t _pad_0xe4_0xef[3];
5782 volatile ALT_NAND_PARAM_FEATURES_t features;
5786 typedef struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
5788 struct ALT_NAND_PARAM_raw_s
5790 volatile uint32_t manufacturer_id;
5791 volatile uint32_t _pad_0x4_0xf[3];
5792 volatile uint32_t device_id;
5793 volatile uint32_t _pad_0x14_0x1f[3];
5794 volatile uint32_t device_param_0;
5795 volatile uint32_t _pad_0x24_0x2f[3];
5796 volatile uint32_t device_param_1;
5797 volatile uint32_t _pad_0x34_0x3f[3];
5798 volatile uint32_t device_param_2;
5799 volatile uint32_t _pad_0x44_0x4f[3];
5800 volatile uint32_t logical_page_data_size;
5801 volatile uint32_t _pad_0x54_0x5f[3];
5802 volatile uint32_t logical_page_spare_size;
5803 volatile uint32_t _pad_0x64_0x6f[3];
5804 volatile uint32_t revision;
5805 volatile uint32_t _pad_0x74_0x7f[3];
5806 volatile uint32_t onfi_device_features;
5807 volatile uint32_t _pad_0x84_0x8f[3];
5808 volatile uint32_t onfi_optional_commands;
5809 volatile uint32_t _pad_0x94_0x9f[3];
5810 volatile uint32_t onfi_timing_mode;
5811 volatile uint32_t _pad_0xa4_0xaf[3];
5812 volatile uint32_t onfi_pgm_cache_timing_mode;
5813 volatile uint32_t _pad_0xb4_0xbf[3];
5814 volatile uint32_t onfi_device_no_of_luns;
5815 volatile uint32_t _pad_0xc4_0xcf[3];
5816 volatile uint32_t onfi_device_no_of_blocks_per_lun_l;
5817 volatile uint32_t _pad_0xd4_0xdf[3];
5818 volatile uint32_t onfi_device_no_of_blocks_per_lun_u;
5819 volatile uint32_t _pad_0xe4_0xef[3];
5820 volatile uint32_t features;
5824 typedef struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
5865 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_LSB 0
5867 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_MSB 1
5869 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_WIDTH 2
5871 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_SET_MSK 0x00000003
5873 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_CLR_MSK 0xfffffffc
5875 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_RESET 0x0
5877 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
5879 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_SET(value) (((value) << 0) & 0x00000003)
5891 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_LSB 2
5893 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_MSB 3
5895 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_WIDTH 2
5897 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_SET_MSK 0x0000000c
5899 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_CLR_MSK 0xfffffff3
5901 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_RESET 0x0
5903 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
5905 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
5917 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_LSB 4
5919 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_MSB 5
5921 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_WIDTH 2
5923 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_SET_MSK 0x00000030
5925 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_CLR_MSK 0xffffffcf
5927 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_RESET 0x0
5929 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
5931 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_SET(value) (((value) << 4) & 0x00000030)
5943 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_LSB 6
5945 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_MSB 7
5947 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_WIDTH 2
5949 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_SET_MSK 0x000000c0
5951 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_CLR_MSK 0xffffff3f
5953 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_RESET 0x0
5955 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
5957 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
5959 #ifndef __ASSEMBLY__
5971 struct ALT_NAND_STAT_TRANSFER_MODE_s
5973 const volatile uint32_t value0 : 2;
5974 const volatile uint32_t value1 : 2;
5975 const volatile uint32_t value2 : 2;
5976 const volatile uint32_t value3 : 2;
5981 typedef struct ALT_NAND_STAT_TRANSFER_MODE_s ALT_NAND_STAT_TRANSFER_MODE_t;
5985 #define ALT_NAND_STAT_TRANSFER_MODE_RESET 0x00000000
5987 #define ALT_NAND_STAT_TRANSFER_MODE_OFST 0x0
5989 #define ALT_NAND_STAT_TRANSFER_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_TRANSFER_MODE_OFST))
6029 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_LSB 0
6031 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_MSB 0
6033 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_WIDTH 1
6035 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6037 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6039 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_RESET 0x0
6041 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6043 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6054 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_LSB 2
6056 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_MSB 2
6058 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_WIDTH 1
6060 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_SET_MSK 0x00000004
6062 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6064 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_RESET 0x0
6066 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6068 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6082 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_LSB 3
6084 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_MSB 3
6086 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_WIDTH 1
6088 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_SET_MSK 0x00000008
6090 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_CLR_MSK 0xfffffff7
6092 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_RESET 0x0
6094 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6096 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6111 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_LSB 4
6113 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_MSB 4
6115 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_WIDTH 1
6117 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_SET_MSK 0x00000010
6119 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6121 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_RESET 0x0
6123 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6125 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6140 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_LSB 5
6142 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_MSB 5
6144 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_WIDTH 1
6146 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_SET_MSK 0x00000020
6148 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_CLR_MSK 0xffffffdf
6150 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_RESET 0x0
6152 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6154 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6165 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_LSB 6
6167 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_MSB 6
6169 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_WIDTH 1
6171 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_SET_MSK 0x00000040
6173 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_CLR_MSK 0xffffffbf
6175 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_RESET 0x0
6177 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6179 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
6190 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_LSB 7
6192 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_MSB 7
6194 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_WIDTH 1
6196 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_SET_MSK 0x00000080
6198 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6200 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_RESET 0x0
6202 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6204 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6215 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_LSB 8
6217 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_MSB 8
6219 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_WIDTH 1
6221 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_SET_MSK 0x00000100
6223 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_CLR_MSK 0xfffffeff
6225 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_RESET 0x0
6227 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6229 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6241 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_LSB 9
6243 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_MSB 9
6245 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6247 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6249 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6251 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6253 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6255 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6269 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_LSB 10
6271 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_MSB 10
6273 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_WIDTH 1
6275 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_SET_MSK 0x00000400
6277 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_CLR_MSK 0xfffffbff
6279 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_RESET 0x0
6281 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6283 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6297 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_LSB 11
6299 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_MSB 11
6301 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_WIDTH 1
6303 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_SET_MSK 0x00000800
6305 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6307 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_RESET 0x0
6309 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6311 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6322 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_LSB 12
6324 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_MSB 12
6326 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_WIDTH 1
6328 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_SET_MSK 0x00001000
6330 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_CLR_MSK 0xffffefff
6332 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_RESET 0x0
6334 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6336 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6347 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_LSB 13
6349 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_MSB 13
6351 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_WIDTH 1
6353 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_SET_MSK 0x00002000
6355 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_CLR_MSK 0xffffdfff
6357 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_RESET 0x0
6359 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6361 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6378 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_LSB 14
6380 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_MSB 14
6382 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_WIDTH 1
6384 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_SET_MSK 0x00004000
6386 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6388 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_RESET 0x0
6390 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6392 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6403 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_LSB 15
6405 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_MSB 15
6407 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_WIDTH 1
6409 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_SET_MSK 0x00008000
6411 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6413 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_RESET 0x0
6415 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6417 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6450 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_LSB 16
6452 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_MSB 16
6454 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_WIDTH 1
6456 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_SET_MSK 0x00010000
6458 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_CLR_MSK 0xfffeffff
6460 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_RESET 0x0
6462 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6464 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6466 #ifndef __ASSEMBLY__
6478 struct ALT_NAND_STAT_INTR_STATUS0_s
6480 volatile uint32_t ecc_uncor_err : 1;
6482 volatile uint32_t dma_cmd_comp : 1;
6483 volatile uint32_t time_out : 1;
6484 volatile uint32_t program_fail : 1;
6485 volatile uint32_t erase_fail : 1;
6486 volatile uint32_t load_comp : 1;
6487 volatile uint32_t program_comp : 1;
6488 volatile uint32_t erase_comp : 1;
6489 volatile uint32_t pipe_cpybck_cmd_comp : 1;
6490 volatile uint32_t locked_blk : 1;
6491 volatile uint32_t unsup_cmd : 1;
6492 volatile uint32_t int_act : 1;
6493 volatile uint32_t rst_comp : 1;
6494 volatile uint32_t pipe_cmd_err : 1;
6495 volatile uint32_t page_xfer_inc : 1;
6496 volatile uint32_t erased_page : 1;
6501 typedef struct ALT_NAND_STAT_INTR_STATUS0_s ALT_NAND_STAT_INTR_STATUS0_t;
6505 #define ALT_NAND_STAT_INTR_STATUS0_RESET 0x00000000
6507 #define ALT_NAND_STAT_INTR_STATUS0_OFST 0x10
6509 #define ALT_NAND_STAT_INTR_STATUS0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS0_OFST))
6552 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
6554 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
6556 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
6558 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6560 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6562 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
6564 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6566 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6577 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
6579 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
6581 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
6583 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
6585 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6587 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
6589 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6591 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6605 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
6607 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
6609 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
6611 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
6613 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
6615 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
6617 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6619 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6634 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
6636 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
6638 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
6640 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
6642 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6644 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
6646 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6648 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6663 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
6665 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
6667 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
6669 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
6671 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
6673 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
6675 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6677 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6688 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_LSB 6
6690 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_MSB 6
6692 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_WIDTH 1
6694 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_SET_MSK 0x00000040
6696 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_CLR_MSK 0xffffffbf
6698 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_RESET 0x0
6700 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6702 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
6713 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
6715 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
6717 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
6719 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
6721 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6723 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
6725 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6727 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6738 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
6740 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
6742 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
6744 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
6746 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
6748 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
6750 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6752 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6764 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
6766 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
6768 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6770 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6772 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6774 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6776 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6778 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6792 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
6794 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
6796 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
6798 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
6800 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
6802 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
6804 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6806 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6820 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
6822 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
6824 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
6826 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
6828 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6830 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
6832 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6834 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6845 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
6847 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
6849 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
6851 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
6853 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
6855 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
6857 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6859 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6870 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
6872 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
6874 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
6876 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
6878 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
6880 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
6882 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6884 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6901 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
6903 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
6905 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
6907 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
6909 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6911 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
6913 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6915 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6926 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
6928 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
6930 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
6932 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
6934 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6936 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
6938 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6940 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6973 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_LSB 16
6975 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_MSB 16
6977 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_WIDTH 1
6979 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET_MSK 0x00010000
6981 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_CLR_MSK 0xfffeffff
6983 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_RESET 0x0
6985 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6987 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6989 #ifndef __ASSEMBLY__
7001 struct ALT_NAND_STAT_INTR_EN0_s
7003 volatile uint32_t ecc_uncor_err : 1;
7005 volatile uint32_t dma_cmd_comp : 1;
7006 volatile uint32_t time_out : 1;
7007 volatile uint32_t program_fail : 1;
7008 volatile uint32_t erase_fail : 1;
7009 volatile uint32_t load_comp : 1;
7010 volatile uint32_t program_comp : 1;
7011 volatile uint32_t erase_comp : 1;
7012 volatile uint32_t pipe_cpybck_cmd_comp : 1;
7013 volatile uint32_t locked_blk : 1;
7014 volatile uint32_t unsup_cmd : 1;
7015 volatile uint32_t int_act : 1;
7016 volatile uint32_t rst_comp : 1;
7017 volatile uint32_t pipe_cmd_err : 1;
7018 volatile uint32_t page_xfer_inc : 1;
7019 volatile uint32_t erased_page : 1;
7024 typedef struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
7028 #define ALT_NAND_STAT_INTR_EN0_RESET 0x00002000
7030 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
7032 #define ALT_NAND_STAT_INTR_EN0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN0_OFST))
7058 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
7060 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
7062 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
7064 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
7066 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
7068 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
7070 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
7072 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
7074 #ifndef __ASSEMBLY__
7086 struct ALT_NAND_STAT_PAGE_CNT0_s
7088 const volatile uint32_t value : 8;
7093 typedef struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
7097 #define ALT_NAND_STAT_PAGE_CNT0_RESET 0x00000000
7099 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
7101 #define ALT_NAND_STAT_PAGE_CNT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT0_OFST))
7127 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
7129 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
7131 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
7133 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
7135 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
7137 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
7139 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7141 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7143 #ifndef __ASSEMBLY__
7155 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
7157 const volatile uint32_t value : 16;
7162 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
7166 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_RESET 0x00000000
7168 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
7170 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST))
7196 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
7198 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
7200 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
7202 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
7204 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
7206 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
7208 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7210 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7212 #ifndef __ASSEMBLY__
7224 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
7226 const volatile uint32_t value : 16;
7231 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
7235 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_RESET 0x00000000
7237 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
7239 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST))
7279 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_LSB 0
7281 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_MSB 0
7283 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_WIDTH 1
7285 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7287 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7289 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_RESET 0x0
7291 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7293 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7304 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_LSB 2
7306 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_MSB 2
7308 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_WIDTH 1
7310 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_SET_MSK 0x00000004
7312 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7314 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_RESET 0x0
7316 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7318 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7332 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_LSB 3
7334 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_MSB 3
7336 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_WIDTH 1
7338 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_SET_MSK 0x00000008
7340 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_CLR_MSK 0xfffffff7
7342 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_RESET 0x0
7344 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7346 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7361 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_LSB 4
7363 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_MSB 4
7365 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_WIDTH 1
7367 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_SET_MSK 0x00000010
7369 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7371 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_RESET 0x0
7373 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7375 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7390 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_LSB 5
7392 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_MSB 5
7394 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_WIDTH 1
7396 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_SET_MSK 0x00000020
7398 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_CLR_MSK 0xffffffdf
7400 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_RESET 0x0
7402 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7404 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7415 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_LSB 6
7417 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_MSB 6
7419 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_WIDTH 1
7421 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_SET_MSK 0x00000040
7423 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_CLR_MSK 0xffffffbf
7425 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_RESET 0x0
7427 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7429 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
7440 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_LSB 7
7442 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_MSB 7
7444 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_WIDTH 1
7446 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_SET_MSK 0x00000080
7448 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7450 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_RESET 0x0
7452 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7454 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7465 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_LSB 8
7467 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_MSB 8
7469 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_WIDTH 1
7471 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_SET_MSK 0x00000100
7473 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_CLR_MSK 0xfffffeff
7475 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_RESET 0x0
7477 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7479 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7491 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_LSB 9
7493 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_MSB 9
7495 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7497 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7499 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7501 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7503 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7505 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7519 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_LSB 10
7521 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_MSB 10
7523 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_WIDTH 1
7525 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_SET_MSK 0x00000400
7527 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_CLR_MSK 0xfffffbff
7529 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_RESET 0x0
7531 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7533 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7547 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_LSB 11
7549 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_MSB 11
7551 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_WIDTH 1
7553 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_SET_MSK 0x00000800
7555 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7557 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_RESET 0x0
7559 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7561 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7572 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_LSB 12
7574 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_MSB 12
7576 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_WIDTH 1
7578 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_SET_MSK 0x00001000
7580 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_CLR_MSK 0xffffefff
7582 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_RESET 0x0
7584 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7586 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7598 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_LSB 13
7600 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_MSB 13
7602 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_WIDTH 1
7604 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_SET_MSK 0x00002000
7606 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_CLR_MSK 0xffffdfff
7608 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_RESET 0x0
7610 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7612 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7629 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_LSB 14
7631 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_MSB 14
7633 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_WIDTH 1
7635 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_SET_MSK 0x00004000
7637 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7639 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_RESET 0x0
7641 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7643 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7654 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_LSB 15
7656 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_MSB 15
7658 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_WIDTH 1
7660 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_SET_MSK 0x00008000
7662 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7664 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_RESET 0x0
7666 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7668 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7701 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_LSB 16
7703 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_MSB 16
7705 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_WIDTH 1
7707 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_SET_MSK 0x00010000
7709 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_CLR_MSK 0xfffeffff
7711 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_RESET 0x0
7713 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
7715 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
7717 #ifndef __ASSEMBLY__
7729 struct ALT_NAND_STAT_INTR_STATUS1_s
7731 volatile uint32_t ecc_uncor_err : 1;
7733 volatile uint32_t dma_cmd_comp : 1;
7734 volatile uint32_t time_out : 1;
7735 volatile uint32_t program_fail : 1;
7736 volatile uint32_t erase_fail : 1;
7737 volatile uint32_t load_comp : 1;
7738 volatile uint32_t program_comp : 1;
7739 volatile uint32_t erase_comp : 1;
7740 volatile uint32_t pipe_cpybck_cmd_comp : 1;
7741 volatile uint32_t locked_blk : 1;
7742 volatile uint32_t unsup_cmd : 1;
7743 volatile uint32_t int_act : 1;
7744 volatile uint32_t rst_comp : 1;
7745 volatile uint32_t pipe_cmd_err : 1;
7746 volatile uint32_t page_xfer_inc : 1;
7747 volatile uint32_t erased_page : 1;
7752 typedef struct ALT_NAND_STAT_INTR_STATUS1_s ALT_NAND_STAT_INTR_STATUS1_t;
7756 #define ALT_NAND_STAT_INTR_STATUS1_RESET 0x00000000
7758 #define ALT_NAND_STAT_INTR_STATUS1_OFST 0x60
7760 #define ALT_NAND_STAT_INTR_STATUS1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS1_OFST))
7803 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
7805 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
7807 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
7809 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7811 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7813 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
7815 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7817 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7828 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
7830 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
7832 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
7834 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
7836 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7838 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
7840 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7842 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7856 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
7858 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
7860 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
7862 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
7864 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
7866 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
7868 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7870 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7885 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
7887 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
7889 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
7891 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
7893 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7895 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
7897 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7899 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7914 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
7916 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
7918 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
7920 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
7922 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
7924 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
7926 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7928 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7939 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_LSB 6
7941 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_MSB 6
7943 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_WIDTH 1
7945 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_SET_MSK 0x00000040
7947 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_CLR_MSK 0xffffffbf
7949 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_RESET 0x0
7951 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7953 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
7964 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
7966 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
7968 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
7970 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
7972 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7974 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
7976 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7978 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7989 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
7991 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
7993 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
7995 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
7997 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
7999 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
8001 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8003 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8015 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
8017 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
8019 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8021 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8023 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8025 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8027 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8029 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8043 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
8045 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
8047 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
8049 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
8051 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
8053 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
8055 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8057 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8071 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
8073 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
8075 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
8077 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
8079 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
8081 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
8083 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8085 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8096 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
8098 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
8100 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
8102 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
8104 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
8106 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
8108 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8110 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8121 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
8123 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
8125 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
8127 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
8129 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
8131 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
8133 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8135 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8152 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
8154 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
8156 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
8158 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
8160 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8162 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
8164 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8166 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8177 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
8179 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
8181 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
8183 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
8185 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8187 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
8189 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8191 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8224 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_LSB 16
8226 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_MSB 16
8228 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_WIDTH 1
8230 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET_MSK 0x00010000
8232 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_CLR_MSK 0xfffeffff
8234 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_RESET 0x0
8236 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8238 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8240 #ifndef __ASSEMBLY__
8252 struct ALT_NAND_STAT_INTR_EN1_s
8254 volatile uint32_t ecc_uncor_err : 1;
8256 volatile uint32_t dma_cmd_comp : 1;
8257 volatile uint32_t time_out : 1;
8258 volatile uint32_t program_fail : 1;
8259 volatile uint32_t erase_fail : 1;
8260 volatile uint32_t load_comp : 1;
8261 volatile uint32_t program_comp : 1;
8262 volatile uint32_t erase_comp : 1;
8263 volatile uint32_t pipe_cpybck_cmd_comp : 1;
8264 volatile uint32_t locked_blk : 1;
8265 volatile uint32_t unsup_cmd : 1;
8266 volatile uint32_t int_act : 1;
8267 volatile uint32_t rst_comp : 1;
8268 volatile uint32_t pipe_cmd_err : 1;
8269 volatile uint32_t page_xfer_inc : 1;
8270 volatile uint32_t erased_page : 1;
8275 typedef struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
8279 #define ALT_NAND_STAT_INTR_EN1_RESET 0x00002000
8281 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
8283 #define ALT_NAND_STAT_INTR_EN1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN1_OFST))
8309 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
8311 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
8313 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
8315 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
8317 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
8319 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
8321 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8323 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8325 #ifndef __ASSEMBLY__
8337 struct ALT_NAND_STAT_PAGE_CNT1_s
8339 const volatile uint32_t value : 8;
8344 typedef struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
8348 #define ALT_NAND_STAT_PAGE_CNT1_RESET 0x00000000
8350 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
8352 #define ALT_NAND_STAT_PAGE_CNT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT1_OFST))
8378 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
8380 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
8382 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
8384 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
8386 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
8388 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
8390 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8392 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8394 #ifndef __ASSEMBLY__
8406 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
8408 const volatile uint32_t value : 16;
8413 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
8417 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_RESET 0x00000000
8419 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
8421 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST))
8447 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
8449 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
8451 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
8453 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
8455 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
8457 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
8459 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8461 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8463 #ifndef __ASSEMBLY__
8475 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
8477 const volatile uint32_t value : 16;
8482 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
8486 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_RESET 0x00000000
8488 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
8490 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST))
8530 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_LSB 0
8532 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_MSB 0
8534 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_WIDTH 1
8536 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8538 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8540 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_RESET 0x0
8542 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8544 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8555 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_LSB 2
8557 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_MSB 2
8559 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_WIDTH 1
8561 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_SET_MSK 0x00000004
8563 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8565 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_RESET 0x0
8567 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8569 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8583 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_LSB 3
8585 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_MSB 3
8587 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_WIDTH 1
8589 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_SET_MSK 0x00000008
8591 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_CLR_MSK 0xfffffff7
8593 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_RESET 0x0
8595 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8597 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8612 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_LSB 4
8614 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_MSB 4
8616 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_WIDTH 1
8618 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_SET_MSK 0x00000010
8620 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8622 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_RESET 0x0
8624 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8626 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8641 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_LSB 5
8643 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_MSB 5
8645 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_WIDTH 1
8647 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_SET_MSK 0x00000020
8649 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_CLR_MSK 0xffffffdf
8651 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_RESET 0x0
8653 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8655 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8666 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_LSB 6
8668 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_MSB 6
8670 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_WIDTH 1
8672 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_SET_MSK 0x00000040
8674 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_CLR_MSK 0xffffffbf
8676 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_RESET 0x0
8678 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8680 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
8691 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_LSB 7
8693 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_MSB 7
8695 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_WIDTH 1
8697 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_SET_MSK 0x00000080
8699 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8701 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_RESET 0x0
8703 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8705 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8716 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_LSB 8
8718 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_MSB 8
8720 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_WIDTH 1
8722 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_SET_MSK 0x00000100
8724 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_CLR_MSK 0xfffffeff
8726 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_RESET 0x0
8728 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8730 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8742 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_LSB 9
8744 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_MSB 9
8746 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8748 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8750 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8752 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8754 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8756 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8770 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_LSB 10
8772 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_MSB 10
8774 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_WIDTH 1
8776 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_SET_MSK 0x00000400
8778 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_CLR_MSK 0xfffffbff
8780 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_RESET 0x0
8782 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8784 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8798 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_LSB 11
8800 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_MSB 11
8802 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_WIDTH 1
8804 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_SET_MSK 0x00000800
8806 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_CLR_MSK 0xfffff7ff
8808 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_RESET 0x0
8810 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8812 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8823 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_LSB 12
8825 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_MSB 12
8827 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_WIDTH 1
8829 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_SET_MSK 0x00001000
8831 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_CLR_MSK 0xffffefff
8833 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_RESET 0x0
8835 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8837 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8849 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_LSB 13
8851 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_MSB 13
8853 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_WIDTH 1
8855 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_SET_MSK 0x00002000
8857 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_CLR_MSK 0xffffdfff
8859 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_RESET 0x0
8861 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8863 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8880 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_LSB 14
8882 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_MSB 14
8884 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_WIDTH 1
8886 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_SET_MSK 0x00004000
8888 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8890 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_RESET 0x0
8892 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8894 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8905 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_LSB 15
8907 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_MSB 15
8909 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_WIDTH 1
8911 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_SET_MSK 0x00008000
8913 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8915 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_RESET 0x0
8917 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8919 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8952 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_LSB 16
8954 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_MSB 16
8956 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_WIDTH 1
8958 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_SET_MSK 0x00010000
8960 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_CLR_MSK 0xfffeffff
8962 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_RESET 0x0
8964 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8966 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8968 #ifndef __ASSEMBLY__
8980 struct ALT_NAND_STAT_INTR_STATUS2_s
8982 volatile uint32_t ecc_uncor_err : 1;
8984 volatile uint32_t dma_cmd_comp : 1;
8985 volatile uint32_t time_out : 1;
8986 volatile uint32_t program_fail : 1;
8987 volatile uint32_t erase_fail : 1;
8988 volatile uint32_t load_comp : 1;
8989 volatile uint32_t program_comp : 1;
8990 volatile uint32_t erase_comp : 1;
8991 volatile uint32_t pipe_cpybck_cmd_comp : 1;
8992 volatile uint32_t locked_blk : 1;
8993 volatile uint32_t unsup_cmd : 1;
8994 volatile uint32_t int_act : 1;
8995 volatile uint32_t rst_comp : 1;
8996 volatile uint32_t pipe_cmd_err : 1;
8997 volatile uint32_t page_xfer_inc : 1;
8998 volatile uint32_t erased_page : 1;
9003 typedef struct ALT_NAND_STAT_INTR_STATUS2_s ALT_NAND_STAT_INTR_STATUS2_t;
9007 #define ALT_NAND_STAT_INTR_STATUS2_RESET 0x00000000
9009 #define ALT_NAND_STAT_INTR_STATUS2_OFST 0xb0
9011 #define ALT_NAND_STAT_INTR_STATUS2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS2_OFST))
9054 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
9056 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
9058 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
9060 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
9062 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9064 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
9066 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9068 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9079 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
9081 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
9083 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
9085 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
9087 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9089 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
9091 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9093 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9107 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
9109 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
9111 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
9113 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
9115 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
9117 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
9119 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9121 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9136 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
9138 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
9140 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
9142 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
9144 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
9146 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
9148 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9150 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9165 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
9167 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
9169 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
9171 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
9173 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
9175 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
9177 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9179 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9190 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_LSB 6
9192 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_MSB 6
9194 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_WIDTH 1
9196 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_SET_MSK 0x00000040
9198 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_CLR_MSK 0xffffffbf
9200 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_RESET 0x0
9202 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9204 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
9215 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
9217 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
9219 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
9221 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
9223 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
9225 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
9227 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9229 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9240 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
9242 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
9244 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
9246 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
9248 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
9250 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
9252 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9254 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9266 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
9268 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
9270 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9272 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9274 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9276 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9278 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9280 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9294 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
9296 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
9298 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
9300 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
9302 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
9304 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
9306 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9308 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9322 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
9324 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
9326 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
9328 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
9330 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
9332 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
9334 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9336 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9347 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
9349 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
9351 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
9353 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
9355 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
9357 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
9359 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9361 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9372 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
9374 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
9376 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
9378 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
9380 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
9382 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
9384 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9386 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9403 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
9405 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
9407 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
9409 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
9411 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9413 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
9415 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9417 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9428 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
9430 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
9432 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
9434 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
9436 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9438 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
9440 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9442 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9475 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_LSB 16
9477 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_MSB 16
9479 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_WIDTH 1
9481 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET_MSK 0x00010000
9483 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_CLR_MSK 0xfffeffff
9485 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_RESET 0x0
9487 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9489 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9491 #ifndef __ASSEMBLY__
9503 struct ALT_NAND_STAT_INTR_EN2_s
9505 volatile uint32_t ecc_uncor_err : 1;
9507 volatile uint32_t dma_cmd_comp : 1;
9508 volatile uint32_t time_out : 1;
9509 volatile uint32_t program_fail : 1;
9510 volatile uint32_t erase_fail : 1;
9511 volatile uint32_t load_comp : 1;
9512 volatile uint32_t program_comp : 1;
9513 volatile uint32_t erase_comp : 1;
9514 volatile uint32_t pipe_cpybck_cmd_comp : 1;
9515 volatile uint32_t locked_blk : 1;
9516 volatile uint32_t unsup_cmd : 1;
9517 volatile uint32_t int_act : 1;
9518 volatile uint32_t rst_comp : 1;
9519 volatile uint32_t pipe_cmd_err : 1;
9520 volatile uint32_t page_xfer_inc : 1;
9521 volatile uint32_t erased_page : 1;
9526 typedef struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
9530 #define ALT_NAND_STAT_INTR_EN2_RESET 0x00002000
9532 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
9534 #define ALT_NAND_STAT_INTR_EN2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN2_OFST))
9560 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
9562 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
9564 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
9566 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
9568 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
9570 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
9572 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9574 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9576 #ifndef __ASSEMBLY__
9588 struct ALT_NAND_STAT_PAGE_CNT2_s
9590 const volatile uint32_t value : 8;
9595 typedef struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
9599 #define ALT_NAND_STAT_PAGE_CNT2_RESET 0x00000000
9601 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
9603 #define ALT_NAND_STAT_PAGE_CNT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT2_OFST))
9629 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
9631 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
9633 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
9635 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
9637 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
9639 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
9641 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9643 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9645 #ifndef __ASSEMBLY__
9657 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
9659 const volatile uint32_t value : 16;
9664 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
9668 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_RESET 0x00000000
9670 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
9672 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST))
9698 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
9700 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
9702 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
9704 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
9706 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
9708 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
9710 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9712 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9714 #ifndef __ASSEMBLY__
9726 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
9728 const volatile uint32_t value : 16;
9733 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
9737 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_RESET 0x00000000
9739 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
9741 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST))
9781 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_LSB 0
9783 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_MSB 0
9785 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_WIDTH 1
9787 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_SET_MSK 0x00000001
9789 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9791 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_RESET 0x0
9793 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9795 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9806 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_LSB 2
9808 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_MSB 2
9810 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_WIDTH 1
9812 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_SET_MSK 0x00000004
9814 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9816 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_RESET 0x0
9818 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9820 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9834 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_LSB 3
9836 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_MSB 3
9838 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_WIDTH 1
9840 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_SET_MSK 0x00000008
9842 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_CLR_MSK 0xfffffff7
9844 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_RESET 0x0
9846 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9848 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9863 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_LSB 4
9865 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_MSB 4
9867 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_WIDTH 1
9869 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_SET_MSK 0x00000010
9871 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_CLR_MSK 0xffffffef
9873 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_RESET 0x0
9875 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9877 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9892 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_LSB 5
9894 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_MSB 5
9896 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_WIDTH 1
9898 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_SET_MSK 0x00000020
9900 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_CLR_MSK 0xffffffdf
9902 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_RESET 0x0
9904 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9906 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9917 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_LSB 6
9919 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_MSB 6
9921 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_WIDTH 1
9923 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_SET_MSK 0x00000040
9925 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_CLR_MSK 0xffffffbf
9927 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_RESET 0x0
9929 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9931 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
9942 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_LSB 7
9944 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_MSB 7
9946 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_WIDTH 1
9948 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_SET_MSK 0x00000080
9950 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_CLR_MSK 0xffffff7f
9952 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_RESET 0x0
9954 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9956 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9967 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_LSB 8
9969 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_MSB 8
9971 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_WIDTH 1
9973 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_SET_MSK 0x00000100
9975 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_CLR_MSK 0xfffffeff
9977 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_RESET 0x0
9979 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9981 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9993 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_LSB 9
9995 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_MSB 9
9997 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9999 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10001 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10003 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10005 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10007 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10021 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_LSB 10
10023 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_MSB 10
10025 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_WIDTH 1
10027 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_SET_MSK 0x00000400
10029 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_CLR_MSK 0xfffffbff
10031 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_RESET 0x0
10033 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10035 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10049 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_LSB 11
10051 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_MSB 11
10053 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_WIDTH 1
10055 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_SET_MSK 0x00000800
10057 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10059 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_RESET 0x0
10061 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10063 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10074 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_LSB 12
10076 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_MSB 12
10078 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_WIDTH 1
10080 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_SET_MSK 0x00001000
10082 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_CLR_MSK 0xffffefff
10084 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_RESET 0x0
10086 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10088 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10100 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_LSB 13
10102 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_MSB 13
10104 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_WIDTH 1
10106 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_SET_MSK 0x00002000
10108 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_CLR_MSK 0xffffdfff
10110 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_RESET 0x0
10112 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10114 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10131 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_LSB 14
10133 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_MSB 14
10135 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_WIDTH 1
10137 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_SET_MSK 0x00004000
10139 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10141 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_RESET 0x0
10143 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10145 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10156 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_LSB 15
10158 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_MSB 15
10160 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_WIDTH 1
10162 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_SET_MSK 0x00008000
10164 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10166 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_RESET 0x0
10168 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10170 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10203 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_LSB 16
10205 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_MSB 16
10207 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_WIDTH 1
10209 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_SET_MSK 0x00010000
10211 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_CLR_MSK 0xfffeffff
10213 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_RESET 0x0
10215 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10217 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10219 #ifndef __ASSEMBLY__
10231 struct ALT_NAND_STAT_INTR_STATUS3_s
10233 volatile uint32_t ecc_uncor_err : 1;
10235 volatile uint32_t dma_cmd_comp : 1;
10236 volatile uint32_t time_out : 1;
10237 volatile uint32_t program_fail : 1;
10238 volatile uint32_t erase_fail : 1;
10239 volatile uint32_t load_comp : 1;
10240 volatile uint32_t program_comp : 1;
10241 volatile uint32_t erase_comp : 1;
10242 volatile uint32_t pipe_cpybck_cmd_comp : 1;
10243 volatile uint32_t locked_blk : 1;
10244 volatile uint32_t unsup_cmd : 1;
10245 volatile uint32_t int_act : 1;
10246 volatile uint32_t rst_comp : 1;
10247 volatile uint32_t pipe_cmd_err : 1;
10248 volatile uint32_t page_xfer_inc : 1;
10249 volatile uint32_t erased_page : 1;
10254 typedef struct ALT_NAND_STAT_INTR_STATUS3_s ALT_NAND_STAT_INTR_STATUS3_t;
10258 #define ALT_NAND_STAT_INTR_STATUS3_RESET 0x00000000
10260 #define ALT_NAND_STAT_INTR_STATUS3_OFST 0x100
10262 #define ALT_NAND_STAT_INTR_STATUS3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS3_OFST))
10305 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
10307 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
10309 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
10311 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
10313 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
10315 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
10317 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
10319 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
10330 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
10332 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
10334 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
10336 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
10338 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
10340 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
10342 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
10344 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
10358 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
10360 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
10362 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
10364 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
10366 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
10368 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
10370 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
10372 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
10387 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
10389 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
10391 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
10393 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
10395 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
10397 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
10399 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
10401 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
10416 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
10418 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
10420 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
10422 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
10424 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
10426 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
10428 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
10430 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
10441 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_LSB 6
10443 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_MSB 6
10445 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_WIDTH 1
10447 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_SET_MSK 0x00000040
10449 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_CLR_MSK 0xffffffbf
10451 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_RESET 0x0
10453 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
10455 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
10466 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
10468 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
10470 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
10472 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
10474 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
10476 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
10478 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
10480 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
10491 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
10493 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
10495 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
10497 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
10499 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
10501 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
10503 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
10505 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
10517 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
10519 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
10521 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
10523 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10525 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10527 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10529 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10531 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10545 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
10547 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
10549 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
10551 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
10553 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
10555 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
10557 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10559 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10573 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
10575 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
10577 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
10579 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
10581 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10583 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
10585 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10587 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10598 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
10600 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
10602 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
10604 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
10606 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
10608 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
10610 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10612 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10623 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
10625 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
10627 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
10629 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
10631 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
10633 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
10635 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10637 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10654 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
10656 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
10658 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
10660 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
10662 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10664 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
10666 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10668 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10679 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
10681 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
10683 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
10685 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
10687 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10689 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
10691 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10693 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10726 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_LSB 16
10728 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_MSB 16
10730 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_WIDTH 1
10732 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET_MSK 0x00010000
10734 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_CLR_MSK 0xfffeffff
10736 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_RESET 0x0
10738 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10740 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10742 #ifndef __ASSEMBLY__
10754 struct ALT_NAND_STAT_INTR_EN3_s
10756 volatile uint32_t ecc_uncor_err : 1;
10758 volatile uint32_t dma_cmd_comp : 1;
10759 volatile uint32_t time_out : 1;
10760 volatile uint32_t program_fail : 1;
10761 volatile uint32_t erase_fail : 1;
10762 volatile uint32_t load_comp : 1;
10763 volatile uint32_t program_comp : 1;
10764 volatile uint32_t erase_comp : 1;
10765 volatile uint32_t pipe_cpybck_cmd_comp : 1;
10766 volatile uint32_t locked_blk : 1;
10767 volatile uint32_t unsup_cmd : 1;
10768 volatile uint32_t int_act : 1;
10769 volatile uint32_t rst_comp : 1;
10770 volatile uint32_t pipe_cmd_err : 1;
10771 volatile uint32_t page_xfer_inc : 1;
10772 volatile uint32_t erased_page : 1;
10777 typedef struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
10781 #define ALT_NAND_STAT_INTR_EN3_RESET 0x00002000
10783 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
10785 #define ALT_NAND_STAT_INTR_EN3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN3_OFST))
10811 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
10813 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
10815 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
10817 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
10819 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
10821 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
10823 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
10825 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
10827 #ifndef __ASSEMBLY__
10839 struct ALT_NAND_STAT_PAGE_CNT3_s
10841 const volatile uint32_t value : 8;
10846 typedef struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
10850 #define ALT_NAND_STAT_PAGE_CNT3_RESET 0x00000000
10852 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
10854 #define ALT_NAND_STAT_PAGE_CNT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT3_OFST))
10880 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
10882 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
10884 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
10886 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
10888 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
10890 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
10892 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10894 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10896 #ifndef __ASSEMBLY__
10908 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
10910 const volatile uint32_t value : 16;
10915 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
10919 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_RESET 0x00000000
10921 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
10923 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST))
10949 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
10951 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
10953 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
10955 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
10957 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
10959 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
10961 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10963 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10965 #ifndef __ASSEMBLY__
10977 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
10979 const volatile uint32_t value : 16;
10984 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
10988 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_RESET 0x00000000
10990 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
10992 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST))
10994 #ifndef __ASSEMBLY__
11006 struct ALT_NAND_STAT_s
11009 volatile uint32_t _pad_0x4_0xf[3];
11010 volatile ALT_NAND_STAT_INTR_STATUS0_t intr_status0;
11011 volatile uint32_t _pad_0x14_0x1f[3];
11012 volatile ALT_NAND_STAT_INTR_EN0_t intr_en0;
11013 volatile uint32_t _pad_0x24_0x2f[3];
11014 volatile ALT_NAND_STAT_PAGE_CNT0_t page_cnt0;
11015 volatile uint32_t _pad_0x34_0x3f[3];
11016 volatile ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0;
11017 volatile uint32_t _pad_0x44_0x4f[3];
11018 volatile ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0;
11019 volatile uint32_t _pad_0x54_0x5f[3];
11020 volatile ALT_NAND_STAT_INTR_STATUS1_t intr_status1;
11021 volatile uint32_t _pad_0x64_0x6f[3];
11022 volatile ALT_NAND_STAT_INTR_EN1_t intr_en1;
11023 volatile uint32_t _pad_0x74_0x7f[3];
11024 volatile ALT_NAND_STAT_PAGE_CNT1_t page_cnt1;
11025 volatile uint32_t _pad_0x84_0x8f[3];
11026 volatile ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1;
11027 volatile uint32_t _pad_0x94_0x9f[3];
11028 volatile ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1;
11029 volatile uint32_t _pad_0xa4_0xaf[3];
11030 volatile ALT_NAND_STAT_INTR_STATUS2_t intr_status2;
11031 volatile uint32_t _pad_0xb4_0xbf[3];
11032 volatile ALT_NAND_STAT_INTR_EN2_t intr_en2;
11033 volatile uint32_t _pad_0xc4_0xcf[3];
11034 volatile ALT_NAND_STAT_PAGE_CNT2_t page_cnt2;
11035 volatile uint32_t _pad_0xd4_0xdf[3];
11036 volatile ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2;
11037 volatile uint32_t _pad_0xe4_0xef[3];
11038 volatile ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2;
11039 volatile uint32_t _pad_0xf4_0xff[3];
11040 volatile ALT_NAND_STAT_INTR_STATUS3_t intr_status3;
11041 volatile uint32_t _pad_0x104_0x10f[3];
11042 volatile ALT_NAND_STAT_INTR_EN3_t intr_en3;
11043 volatile uint32_t _pad_0x114_0x11f[3];
11044 volatile ALT_NAND_STAT_PAGE_CNT3_t page_cnt3;
11045 volatile uint32_t _pad_0x124_0x12f[3];
11046 volatile ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3;
11047 volatile uint32_t _pad_0x134_0x13f[3];
11048 volatile ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3;
11052 typedef struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
11054 struct ALT_NAND_STAT_raw_s
11057 volatile uint32_t _pad_0x4_0xf[3];
11058 volatile uint32_t intr_status0;
11059 volatile uint32_t _pad_0x14_0x1f[3];
11060 volatile uint32_t intr_en0;
11061 volatile uint32_t _pad_0x24_0x2f[3];
11062 volatile uint32_t page_cnt0;
11063 volatile uint32_t _pad_0x34_0x3f[3];
11064 volatile uint32_t err_page_addr0;
11065 volatile uint32_t _pad_0x44_0x4f[3];
11066 volatile uint32_t err_block_addr0;
11067 volatile uint32_t _pad_0x54_0x5f[3];
11068 volatile uint32_t intr_status1;
11069 volatile uint32_t _pad_0x64_0x6f[3];
11070 volatile uint32_t intr_en1;
11071 volatile uint32_t _pad_0x74_0x7f[3];
11072 volatile uint32_t page_cnt1;
11073 volatile uint32_t _pad_0x84_0x8f[3];
11074 volatile uint32_t err_page_addr1;
11075 volatile uint32_t _pad_0x94_0x9f[3];
11076 volatile uint32_t err_block_addr1;
11077 volatile uint32_t _pad_0xa4_0xaf[3];
11078 volatile uint32_t intr_status2;
11079 volatile uint32_t _pad_0xb4_0xbf[3];
11080 volatile uint32_t intr_en2;
11081 volatile uint32_t _pad_0xc4_0xcf[3];
11082 volatile uint32_t page_cnt2;
11083 volatile uint32_t _pad_0xd4_0xdf[3];
11084 volatile uint32_t err_page_addr2;
11085 volatile uint32_t _pad_0xe4_0xef[3];
11086 volatile uint32_t err_block_addr2;
11087 volatile uint32_t _pad_0xf4_0xff[3];
11088 volatile uint32_t intr_status3;
11089 volatile uint32_t _pad_0x104_0x10f[3];
11090 volatile uint32_t intr_en3;
11091 volatile uint32_t _pad_0x114_0x11f[3];
11092 volatile uint32_t page_cnt3;
11093 volatile uint32_t _pad_0x124_0x12f[3];
11094 volatile uint32_t err_page_addr3;
11095 volatile uint32_t _pad_0x134_0x13f[3];
11096 volatile uint32_t err_block_addr3;
11100 typedef struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
11145 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
11147 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
11149 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
11151 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
11153 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
11155 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
11157 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
11159 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
11173 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
11175 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
11177 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
11179 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
11181 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
11183 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
11185 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
11187 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
11204 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
11206 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
11208 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
11210 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
11212 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
11214 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
11216 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
11218 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
11232 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
11234 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
11236 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
11238 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
11240 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
11242 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
11244 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
11246 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
11248 #ifndef __ASSEMBLY__
11260 struct ALT_NAND_ECC_ECCCORINFO_B01_s
11262 const volatile uint32_t max_errors_b0 : 7;
11263 const volatile uint32_t uncor_err_b0 : 1;
11264 const volatile uint32_t max_errors_b1 : 7;
11265 const volatile uint32_t uncor_err_b1 : 1;
11270 typedef struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
11274 #define ALT_NAND_ECC_ECCCORINFO_B01_RESET 0x00000000
11276 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
11278 #define ALT_NAND_ECC_ECCCORINFO_B01_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_ECC_ECCCORINFO_B01_OFST))
11315 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
11317 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
11319 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
11321 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
11323 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
11325 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
11327 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
11329 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
11343 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
11345 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
11347 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
11349 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
11351 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
11353 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
11355 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
11357 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
11374 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
11376 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
11378 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
11380 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
11382 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
11384 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
11386 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
11388 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
11402 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
11404 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
11406 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
11408 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
11410 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
11412 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
11414 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
11416 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
11418 #ifndef __ASSEMBLY__
11430 struct ALT_NAND_ECC_ECCCORINFO_B23_s
11432 const volatile uint32_t max_errors_b2 : 7;
11433 const volatile uint32_t uncor_err_b2 : 1;
11434 const volatile uint32_t max_errors_b3 : 7;
11435 const volatile uint32_t uncor_err_b3 : 1;
11440 typedef struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
11444 #define ALT_NAND_ECC_ECCCORINFO_B23_RESET 0x00000000
11446 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
11448 #define ALT_NAND_ECC_ECCCORINFO_B23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_ECC_ECCCORINFO_B23_OFST))
11450 #ifndef __ASSEMBLY__
11462 struct ALT_NAND_ECC_s
11464 volatile ALT_NAND_ECC_ECCCORINFO_B01_t ecccorinfo_b01;
11465 volatile uint32_t _pad_0x4_0xf[3];
11466 volatile ALT_NAND_ECC_ECCCORINFO_B23_t ecccorinfo_b23;
11470 typedef struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
11472 struct ALT_NAND_ECC_raw_s
11474 volatile uint32_t ecccorinfo_b01;
11475 volatile uint32_t _pad_0x4_0xf[3];
11476 volatile uint32_t ecccorinfo_b23;
11480 typedef struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
11512 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_LSB 0
11514 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_MSB 0
11516 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_WIDTH 1
11518 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_SET_MSK 0x00000001
11520 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_CLR_MSK 0xfffffffe
11522 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_RESET 0x0
11524 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
11526 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
11528 #ifndef __ASSEMBLY__
11540 struct ALT_NAND_DMA_DMA_ENABLE_s
11542 volatile uint32_t flag : 1;
11547 typedef struct ALT_NAND_DMA_DMA_ENABLE_s ALT_NAND_DMA_DMA_ENABLE_t;
11551 #define ALT_NAND_DMA_DMA_ENABLE_RESET 0x00000000
11553 #define ALT_NAND_DMA_DMA_ENABLE_OFST 0x0
11555 #define ALT_NAND_DMA_DMA_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_ENABLE_OFST))
11586 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_LSB 0
11588 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_MSB 0
11590 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_WIDTH 1
11592 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_SET_MSK 0x00000001
11594 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_CLR_MSK 0xfffffffe
11596 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_RESET 0x0
11598 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11600 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_SET(value) (((value) << 0) & 0x00000001)
11612 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_LSB 1
11614 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_MSB 1
11616 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_WIDTH 1
11618 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11620 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11622 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_RESET 0x0
11624 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11626 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11638 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_LSB 2
11640 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_MSB 2
11642 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_WIDTH 1
11644 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11646 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11648 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_RESET 0x0
11650 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11652 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11664 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_LSB 3
11666 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_MSB 3
11668 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_WIDTH 1
11670 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11672 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11674 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_RESET 0x0
11676 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11678 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11690 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_LSB 4
11692 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_MSB 4
11694 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_WIDTH 1
11696 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11698 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11700 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_RESET 0x0
11702 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11704 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11715 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_LSB 6
11717 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_MSB 6
11719 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_WIDTH 1
11721 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET_MSK 0x00000040
11723 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11725 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_RESET 0x0
11727 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11729 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11731 #ifndef __ASSEMBLY__
11743 struct ALT_NAND_DMA_DMA_INTR_s
11745 volatile uint32_t target_error : 1;
11746 volatile uint32_t desc_comp_channel0 : 1;
11747 volatile uint32_t desc_comp_channel1 : 1;
11748 volatile uint32_t desc_comp_channel2 : 1;
11749 volatile uint32_t desc_comp_channel3 : 1;
11751 volatile uint32_t cmddma_idle : 1;
11756 typedef struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
11760 #define ALT_NAND_DMA_DMA_INTR_RESET 0x00000000
11762 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
11764 #define ALT_NAND_DMA_DMA_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_INTR_OFST))
11795 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_LSB 0
11797 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_MSB 0
11799 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_WIDTH 1
11801 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_SET_MSK 0x00000001
11803 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_CLR_MSK 0xfffffffe
11805 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_RESET 0x0
11807 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11809 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_SET(value) (((value) << 0) & 0x00000001)
11821 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB 1
11823 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB 1
11825 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH 1
11827 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11829 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11831 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET 0x0
11833 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11835 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11847 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB 2
11849 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB 2
11851 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH 1
11853 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11855 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11857 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET 0x0
11859 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11861 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11873 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB 3
11875 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB 3
11877 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH 1
11879 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11881 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11883 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET 0x0
11885 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11887 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11899 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB 4
11901 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB 4
11903 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH 1
11905 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11907 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11909 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET 0x0
11911 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11913 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11926 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB 6
11928 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB 6
11930 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH 1
11932 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK 0x00000040
11934 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11936 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET 0x0
11938 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11940 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11942 #ifndef __ASSEMBLY__
11954 struct ALT_NAND_DMA_DMA_INTR_EN_s
11956 volatile uint32_t target_error : 1;
11957 volatile uint32_t desc_comp_channel0 : 1;
11958 volatile uint32_t desc_comp_channel1 : 1;
11959 volatile uint32_t desc_comp_channel2 : 1;
11960 volatile uint32_t desc_comp_channel3 : 1;
11962 volatile uint32_t cmddma_idle : 1;
11967 typedef struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
11971 #define ALT_NAND_DMA_DMA_INTR_EN_RESET 0x00000000
11973 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
11975 #define ALT_NAND_DMA_DMA_INTR_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_INTR_EN_OFST))
12000 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_LSB 0
12002 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_MSB 15
12004 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_WIDTH 16
12006 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
12008 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
12010 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_RESET 0x0
12012 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12014 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12016 #ifndef __ASSEMBLY__
12028 struct ALT_NAND_DMA_TARGET_ERR_ADDR_LO_s
12030 const volatile uint32_t value : 16;
12035 typedef struct ALT_NAND_DMA_TARGET_ERR_ADDR_LO_s ALT_NAND_DMA_TARGET_ERR_ADDR_LO_t;
12039 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_RESET 0x00000000
12041 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_OFST 0x40
12043 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_TARGET_ERR_ADDR_LO_OFST))
12068 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_LSB 0
12070 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_MSB 15
12072 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_WIDTH 16
12074 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
12076 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
12078 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_RESET 0x0
12080 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12082 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12084 #ifndef __ASSEMBLY__
12096 struct ALT_NAND_DMA_TARGET_ERR_ADDR_HI_s
12098 const volatile uint32_t value : 16;
12103 typedef struct ALT_NAND_DMA_TARGET_ERR_ADDR_HI_s ALT_NAND_DMA_TARGET_ERR_ADDR_HI_t;
12107 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_RESET 0x00000000
12109 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_OFST 0x50
12111 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_TARGET_ERR_ADDR_HI_OFST))
12138 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_LSB 0
12140 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_MSB 0
12142 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_WIDTH 1
12144 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_SET_MSK 0x00000001
12146 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_CLR_MSK 0xfffffffe
12148 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_RESET 0x0
12150 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12152 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12163 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_LSB 1
12165 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_MSB 1
12167 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_WIDTH 1
12169 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_SET_MSK 0x00000002
12171 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_CLR_MSK 0xfffffffd
12173 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_RESET 0x0
12175 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12177 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12188 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_LSB 2
12190 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_MSB 2
12192 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_WIDTH 1
12194 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_SET_MSK 0x00000004
12196 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_CLR_MSK 0xfffffffb
12198 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_RESET 0x0
12200 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12202 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12213 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_LSB 3
12215 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_MSB 3
12217 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_WIDTH 1
12219 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_SET_MSK 0x00000008
12221 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_CLR_MSK 0xfffffff7
12223 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_RESET 0x0
12225 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12227 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12229 #ifndef __ASSEMBLY__
12241 struct ALT_NAND_DMA_CHNL_ACTIVE_s
12243 const volatile uint32_t channel0 : 1;
12244 const volatile uint32_t channel1 : 1;
12245 const volatile uint32_t channel2 : 1;
12246 const volatile uint32_t channel3 : 1;
12251 typedef struct ALT_NAND_DMA_CHNL_ACTIVE_s ALT_NAND_DMA_CHNL_ACTIVE_t;
12255 #define ALT_NAND_DMA_CHNL_ACTIVE_RESET 0x00000000
12257 #define ALT_NAND_DMA_CHNL_ACTIVE_OFST 0x60
12259 #define ALT_NAND_DMA_CHNL_ACTIVE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CHNL_ACTIVE_OFST))
12298 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_LSB 0
12300 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_MSB 1
12302 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_WIDTH 2
12304 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_SET_MSK 0x00000003
12306 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_CLR_MSK 0xfffffffc
12308 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_RESET 0x1
12310 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
12312 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
12327 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_LSB 4
12329 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_MSB 4
12331 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_WIDTH 1
12333 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_SET_MSK 0x00000010
12335 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_CLR_MSK 0xffffffef
12337 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_RESET 0x0
12339 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
12341 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
12355 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_LSB 8
12357 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_MSB 31
12359 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_WIDTH 24
12361 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_SET_MSK 0xffffff00
12363 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_CLR_MSK 0x000000ff
12365 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_RESET 0x0
12367 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_GET(value) (((value) & 0xffffff00) >> 8)
12369 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_SET(value) (((value) << 8) & 0xffffff00)
12371 #ifndef __ASSEMBLY__
12383 struct ALT_NAND_DMA_FLASH_BURST_LENGTH_s
12385 volatile uint32_t value : 2;
12387 volatile uint32_t continous_burst : 1;
12389 volatile uint32_t polling_sync_counter_value : 24;
12393 typedef struct ALT_NAND_DMA_FLASH_BURST_LENGTH_s ALT_NAND_DMA_FLASH_BURST_LENGTH_t;
12397 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_RESET 0x00000001
12399 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_OFST 0x70
12401 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_FLASH_BURST_LENGTH_OFST))
12431 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_LSB 0
12433 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_MSB 0
12435 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_WIDTH 1
12437 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_SET_MSK 0x00000001
12439 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_CLR_MSK 0xfffffffe
12441 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_RESET 0x0
12443 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
12445 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_SET(value) (((value) << 0) & 0x00000001)
12471 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_LSB 4
12473 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_MSB 4
12475 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_WIDTH 1
12477 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_SET_MSK 0x00000010
12479 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_CLR_MSK 0xffffffef
12481 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_RESET 0x1
12483 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
12485 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
12510 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_LSB 8
12512 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_MSB 8
12514 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_WIDTH 1
12516 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_SET_MSK 0x00000100
12518 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_CLR_MSK 0xfffffeff
12520 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_RESET 0x1
12522 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_GET(value) (((value) & 0x00000100) >> 8)
12524 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_SET(value) (((value) << 8) & 0x00000100)
12526 #ifndef __ASSEMBLY__
12538 struct ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_s
12540 volatile uint32_t chip_interleave_enable : 1;
12542 volatile uint32_t allow_int_reads_within_luns : 1;
12544 volatile uint32_t cmd_dma_error_enable : 1;
12549 typedef struct ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_s ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_t;
12553 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_RESET 0x00000110
12555 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_OFST 0x80
12557 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_OFST))
12590 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_LSB 0
12592 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_MSB 3
12594 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_WIDTH 4
12596 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_SET_MSK 0x0000000f
12598 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_CLR_MSK 0xfffffff0
12600 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_RESET 0x0
12602 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_GET(value) (((value) & 0x0000000f) >> 0)
12604 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_SET(value) (((value) << 0) & 0x0000000f)
12606 #ifndef __ASSEMBLY__
12618 struct ALT_NAND_DMA_RESCAN_BUFFER_FLAG_s
12620 volatile uint32_t flag : 4;
12625 typedef struct ALT_NAND_DMA_RESCAN_BUFFER_FLAG_s ALT_NAND_DMA_RESCAN_BUFFER_FLAG_t;
12629 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_RESET 0x00000000
12631 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_OFST 0x90
12633 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_RESCAN_BUFFER_FLAG_OFST))
12678 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
12680 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
12682 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
12684 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
12686 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
12688 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
12690 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
12692 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
12709 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24
12711 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24
12713 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1
12715 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000
12717 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff
12719 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0
12721 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET(value) (((value) & 0x01000000) >> 24)
12723 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET(value) (((value) << 24) & 0x01000000)
12743 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_LSB 28
12745 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_MSB 28
12747 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_WIDTH 1
12749 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_SET_MSK 0x10000000
12751 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_CLR_MSK 0xefffffff
12753 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_RESET 0x0
12755 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28)
12757 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000)
12759 #ifndef __ASSEMBLY__
12771 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
12773 volatile uint32_t value : 4;
12775 volatile uint32_t update_sync_before_prog_comp : 1;
12777 volatile uint32_t issue_read_before_sync : 1;
12782 typedef struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
12786 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f
12788 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0
12790 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST))
12820 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_LSB 0
12822 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_MSB 15
12824 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_WIDTH 16
12826 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_SET_MSK 0x0000ffff
12828 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_CLR_MSK 0xffff0000
12830 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_RESET 0x7878
12832 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12834 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12836 #ifndef __ASSEMBLY__
12848 struct ALT_NAND_DMA_LUN_STATUS_CMD_s
12850 volatile uint32_t value : 16;
12855 typedef struct ALT_NAND_DMA_LUN_STATUS_CMD_s ALT_NAND_DMA_LUN_STATUS_CMD_t;
12859 #define ALT_NAND_DMA_LUN_STATUS_CMD_RESET 0x00007878
12861 #define ALT_NAND_DMA_LUN_STATUS_CMD_OFST 0xb0
12863 #define ALT_NAND_DMA_LUN_STATUS_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_LUN_STATUS_CMD_OFST))
12891 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0
12893 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0
12895 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1
12897 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001
12899 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe
12901 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0
12903 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12905 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12916 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1
12918 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1
12920 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1
12922 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002
12924 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd
12926 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0
12928 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12930 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12941 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2
12943 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2
12945 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1
12947 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004
12949 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb
12951 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0
12953 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12955 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12966 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3
12968 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3
12970 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1
12972 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008
12974 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7
12976 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0
12978 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12980 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12982 #ifndef __ASSEMBLY__
12994 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
12996 volatile uint32_t channel0 : 1;
12997 volatile uint32_t channel1 : 1;
12998 volatile uint32_t channel2 : 1;
12999 volatile uint32_t channel3 : 1;
13004 typedef struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t;
13008 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000
13010 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0
13012 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST))
13040 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_LSB 0
13042 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_MSB 0
13044 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_WIDTH 1
13046 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET_MSK 0x00000001
13048 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_CLR_MSK 0xfffffffe
13050 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_RESET 0x0
13052 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
13054 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
13065 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_LSB 1
13067 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_MSB 1
13069 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_WIDTH 1
13071 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET_MSK 0x00000002
13073 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_CLR_MSK 0xfffffffd
13075 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_RESET 0x0
13077 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
13079 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
13090 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_LSB 2
13092 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_MSB 2
13094 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_WIDTH 1
13096 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET_MSK 0x00000004
13098 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_CLR_MSK 0xfffffffb
13100 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_RESET 0x0
13102 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
13104 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
13115 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_LSB 3
13117 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_MSB 3
13119 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_WIDTH 1
13121 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET_MSK 0x00000008
13123 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_CLR_MSK 0xfffffff7
13125 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_RESET 0x0
13127 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
13129 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
13131 #ifndef __ASSEMBLY__
13143 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
13145 volatile uint32_t channel0 : 1;
13146 volatile uint32_t channel1 : 1;
13147 volatile uint32_t channel2 : 1;
13148 volatile uint32_t channel3 : 1;
13153 typedef struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t;
13157 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_RESET 0x00000000
13159 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST 0xd0
13161 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST))
13163 #ifndef __ASSEMBLY__
13175 struct ALT_NAND_DMA_s
13177 volatile ALT_NAND_DMA_DMA_ENABLE_t dma_enable;
13178 volatile uint32_t _pad_0x4_0x1f[7];
13179 volatile ALT_NAND_DMA_DMA_INTR_t dma_intr;
13180 volatile uint32_t _pad_0x24_0x2f[3];
13181 volatile ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en;
13182 volatile uint32_t _pad_0x34_0x3f[3];
13183 volatile ALT_NAND_DMA_TARGET_ERR_ADDR_LO_t target_err_addr_lo;
13184 volatile uint32_t _pad_0x44_0x4f[3];
13185 volatile ALT_NAND_DMA_TARGET_ERR_ADDR_HI_t target_err_addr_hi;
13186 volatile uint32_t _pad_0x54_0x5f[3];
13187 volatile ALT_NAND_DMA_CHNL_ACTIVE_t chnl_active;
13188 volatile uint32_t _pad_0x64_0x6f[3];
13189 volatile ALT_NAND_DMA_FLASH_BURST_LENGTH_t flash_burst_length;
13190 volatile uint32_t _pad_0x74_0x7f[3];
13191 volatile ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_t chip_interleave_enable_and_allow_int_reads;
13192 volatile uint32_t _pad_0x84_0x8f[3];
13193 volatile ALT_NAND_DMA_RESCAN_BUFFER_FLAG_t rescan_buffer_flag;
13194 volatile uint32_t _pad_0x94_0x9f[3];
13195 volatile ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun;
13196 volatile uint32_t _pad_0xa4_0xaf[3];
13197 volatile ALT_NAND_DMA_LUN_STATUS_CMD_t lun_status_cmd;
13198 volatile uint32_t _pad_0xb4_0xbf[3];
13199 volatile ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t cmd_dma_channel_error;
13200 volatile uint32_t _pad_0xc4_0xcf[3];
13201 volatile ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t cmd_dma_channel_error_en;
13205 typedef struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
13207 struct ALT_NAND_DMA_raw_s
13209 volatile uint32_t dma_enable;
13210 volatile uint32_t _pad_0x4_0x1f[7];
13211 volatile uint32_t dma_intr;
13212 volatile uint32_t _pad_0x24_0x2f[3];
13213 volatile uint32_t dma_intr_en;
13214 volatile uint32_t _pad_0x34_0x3f[3];
13215 volatile uint32_t target_err_addr_lo;
13216 volatile uint32_t _pad_0x44_0x4f[3];
13217 volatile uint32_t target_err_addr_hi;
13218 volatile uint32_t _pad_0x54_0x5f[3];
13219 volatile uint32_t chnl_active;
13220 volatile uint32_t _pad_0x64_0x6f[3];
13221 volatile uint32_t flash_burst_length;
13222 volatile uint32_t _pad_0x74_0x7f[3];
13223 volatile uint32_t chip_interleave_enable_and_allow_int_reads;
13224 volatile uint32_t _pad_0x84_0x8f[3];
13225 volatile uint32_t rescan_buffer_flag;
13226 volatile uint32_t _pad_0x94_0x9f[3];
13227 volatile uint32_t no_of_blocks_per_lun;
13228 volatile uint32_t _pad_0xa4_0xaf[3];
13229 volatile uint32_t lun_status_cmd;
13230 volatile uint32_t _pad_0xb4_0xbf[3];
13231 volatile uint32_t cmd_dma_channel_error;
13232 volatile uint32_t _pad_0xc4_0xcf[3];
13233 volatile uint32_t cmd_dma_channel_error_en;
13237 typedef struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;