42 #ifndef __ALT_SDRAM_H__
43 #define __ALT_SDRAM_H__
67 ALT_SDR_PORT_FPGA_AXI_R0 = 0,
68 ALT_SDR_PORT_FPGA_AXI_W1 = 1,
69 ALT_SDR_PORT_FPGA_AXI_R2 = 2,
70 ALT_SDR_PORT_FPGA_AXI_W3 = 3,
71 ALT_SDR_PORT_FPGA_AXI_R4 = 4,
72 ALT_SDR_PORT_FPGA_AXI_W5 = 5,
73 ALT_SDR_PORT_L3_AXI_R = 6,
74 ALT_SDR_PORT_MPU_AXI_R = 7,
75 ALT_SDR_PORT_L3_AXI_W = 8,
76 ALT_SDR_PORT_MPU_AXI_W = 9
88 #define ALT_SDR_NUM_PORTS 10
89 #define ALT_SDR_MAX_PRIORITY_WEIGHT 127
90 #define ALT_E_PRIORITY_WEIGHT_TOO_HIGH -32
91 #define ALT_SDR_NUM_PRIORITIES 8
158 #define ALT_SDR_CTL_PROTPORT_DENY_NONE 0
159 #define ALT_SDR_CTL_PROTPORT_DENY_FPGA 0x3F
160 #define ALT_SDR_CTL_PROTPORT_DENY_CPU_READ (1<<7)
161 #define ALT_SDR_CTL_PROTPORT_DENY_CPU_WRITE (1<<9)
162 #define ALT_SDR_CTL_PROTPORT_DENY_L3_READ (1<<6)
163 #define ALT_SDR_CTL_PROTPORT_DENY_L3_WRITE (1<<8)
164 #define ALT_SDR_CTL_PROTPORT_DENY_CPU ALT_SDR_CTL_PROTPORT_DENY_CPU_READ | ALT_SDR_CTL_PROTPORT_DENY_CPU_WRITE
165 #define ALT_SDR_CTL_PROTPORT_DENY_L3 ALT_SDR_CTL_PROTPORT_DENY_L3_READ | ALT_SDR_CTL_PROTPORT_DENY_L3_WRITE
174 ALT_SDR_CTL_RULEID_MIN = 0x000,
175 ALT_SDR_RULEID_L2M0_LO = 0x002,
176 ALT_SDR_RULEID_L2M0_HI = 0x7FA,
177 ALT_SDR_RULEID_DMA_LO = 0x001,
178 ALT_SDR_RULEID_DMA_HI = 0x079,
179 ALT_SDR_RULEID_EMAC0_LO = 0x801,
180 ALT_SDR_RULEID_EMAC0_HI = 0x879,
181 ALT_SDR_RULEID_EMAC1_LO = 0x802,
182 ALT_SDR_RULEID_EMAC1_HI = 0x87A,
183 ALT_SDR_RULEID_USB0 = 0x803,
184 ALT_SDR_RULEID_USB1 = 0x806,
185 ALT_SDR_RULEID_NAND_LO = 0x804,
186 ALT_SDR_RULEID_NAND_HI = 0xFFC,
187 ALT_SDR_RULEID_TMC = 0x800,
188 ALT_SDR_RULEID_DAP = 0x004,
189 ALT_SDR_RULEID_SDMMC = 0x805,
190 ALT_SDR_RULEID_FPGA2SOC_LO = 0x000,
191 ALT_SDR_RULEID_FPGA2SOC_HI = 0x7F8,
192 ALT_SDR_CTL_RULEID_MAX = 0xFFF
206 ALT_SDR_ACCESS_SECURE = 0,
207 ALT_SDR_ACCESS_NONSECURE = 1,
208 ALT_SDR_ACCESS_BOTH = 2
220 ALT_SDR_PORT_MASK_FPGA_AXI_R0 = 1<<3,
221 ALT_SDR_PORT_MASK_FPGA_AXI_W1 = 1<<4,
222 ALT_SDR_PORT_MASK_FPGA_AXI_R2 = 1<<5,
223 ALT_SDR_PORT_MASK_FPGA_AXI_W3 = 1<<6,
224 ALT_SDR_PORT_MASK_FPGA_AXI_R4 = 1<<7,
225 ALT_SDR_PORT_MASK_FPGA_AXI_W5 = 1<<8,
226 ALT_SDR_PORT_MASK_FPGA = 0x01F8,
228 ALT_SDR_PORT_MASK_L3_AXI_R = 1<<9,
229 ALT_SDR_PORT_MASK_L3_AXI_W = 1<<11,
230 ALT_SDR_PORT_MASK_L3 = 0x0A00,
232 ALT_SDR_PORT_MASK_MPU_AXI_R = 1<<10,
233 ALT_SDR_PORT_MASK_MPU_AXI_W = 1<<12,
234 ALT_SDR_PORT_MASK_CPUS = 0x1400,
236 ALT_SDR_PORT_MASK_ALL = 0x1FF8
250 } ALT_SDR_ACCESS_DATA_t;
252 #define ALT_SDR_CTL_PROTRULERDWR_WRITE (1<<5)
254 #define ALT_SDR_MAX_RULE_NUM 19
255 #define ALT_SDR_CTL_RULE_NEW 0xFFFFFFFFu
256 #define ALT_SDR_CTL_RULE_INVALID 0xFFFFFFFEu
258 typedef struct ALT_SDR_RULE_s
266 ALT_SDR_ACCESS_DATA_t AccessPermission;