Hardware Libraries  20.1
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alt_ecc_sdmmc.h
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32 
33 /* Altera - ALT_ECC_SDMMC */
34 
35 #ifndef __ALT_SOCAL_ECC_SDMMC_H__
36 #define __ALT_SOCAL_ECC_SDMMC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_ECC_SDMMC
50  *
51  */
52 /*
53  * Register : IP_REV_ID
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:------------------------------
59  * [15:0] | R | 0x0 | ALT_ECC_SDMMC_IP_REV_ID_SIREV
60  * [31:16] | ??? | 0x0 | *UNDEFINED*
61  *
62  */
63 /*
64  * Field : SIREV
65  *
66  * IP Rev #
67  *
68  * These bits indicate the silicon revision number.
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field. */
74 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_MSB 15
77 /* The width in bits of the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_WIDTH 16
79 /* The mask used to set the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field value. */
80 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 /* The mask used to clear the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 /* The reset value of the ALT_ECC_SDMMC_IP_REV_ID_SIREV register field. */
84 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_RESET 0x0
85 /* Extracts the ALT_ECC_SDMMC_IP_REV_ID_SIREV field value from a register. */
86 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 /* Produces a ALT_ECC_SDMMC_IP_REV_ID_SIREV register field value suitable for setting the register. */
88 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_ECC_SDMMC_IP_REV_ID.
100  */
101 struct ALT_ECC_SDMMC_IP_REV_ID_s
102 {
103  const uint32_t SIREV : 16; /* ALT_ECC_SDMMC_IP_REV_ID_SIREV */
104  uint32_t : 16; /* *UNDEFINED* */
105 };
106 
107 /* The typedef declaration for register ALT_ECC_SDMMC_IP_REV_ID. */
108 typedef volatile struct ALT_ECC_SDMMC_IP_REV_ID_s ALT_ECC_SDMMC_IP_REV_ID_t;
109 #endif /* __ASSEMBLY__ */
110 
111 /* The reset value of the ALT_ECC_SDMMC_IP_REV_ID register. */
112 #define ALT_ECC_SDMMC_IP_REV_ID_RESET 0x00000000
113 /* The byte offset of the ALT_ECC_SDMMC_IP_REV_ID register from the beginning of the component. */
114 #define ALT_ECC_SDMMC_IP_REV_ID_OFST 0x0
115 
116 /*
117  * Register : CTRL
118  *
119  * ECC Control Register
120  *
121  * Register Layout
122  *
123  * Bits | Access | Reset | Description
124  * :--------|:-------|:------|:---------------------------
125  * [0] | RW | 0x0 | ALT_ECC_SDMMC_CTL_ECC_EN
126  * [7:1] | ??? | 0x0 | *UNDEFINED*
127  * [8] | RW | 0x0 | ALT_ECC_SDMMC_CTL_CNT_RSTA
128  * [9] | RW | 0x0 | ALT_ECC_SDMMC_CTL_CNT_RSTB
129  * [15:10] | ??? | 0x0 | *UNDEFINED*
130  * [16] | RW | 0x0 | ALT_ECC_SDMMC_CTL_INITA
131  * [23:17] | ??? | 0x0 | *UNDEFINED*
132  * [24] | RW | 0x0 | ALT_ECC_SDMMC_CTL_INITB
133  * [31:25] | ??? | 0x0 | *UNDEFINED*
134  *
135  */
136 /*
137  * Field : ECC_EN
138  *
139  * Enable for the ECC detection and correction logic.
140  *
141  * Field Access Macros:
142  *
143  */
144 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_CTL_ECC_EN register field. */
145 #define ALT_ECC_SDMMC_CTL_ECC_EN_LSB 0
146 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_CTL_ECC_EN register field. */
147 #define ALT_ECC_SDMMC_CTL_ECC_EN_MSB 0
148 /* The width in bits of the ALT_ECC_SDMMC_CTL_ECC_EN register field. */
149 #define ALT_ECC_SDMMC_CTL_ECC_EN_WIDTH 1
150 /* The mask used to set the ALT_ECC_SDMMC_CTL_ECC_EN register field value. */
151 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET_MSK 0x00000001
152 /* The mask used to clear the ALT_ECC_SDMMC_CTL_ECC_EN register field value. */
153 #define ALT_ECC_SDMMC_CTL_ECC_EN_CLR_MSK 0xfffffffe
154 /* The reset value of the ALT_ECC_SDMMC_CTL_ECC_EN register field. */
155 #define ALT_ECC_SDMMC_CTL_ECC_EN_RESET 0x0
156 /* Extracts the ALT_ECC_SDMMC_CTL_ECC_EN field value from a register. */
157 #define ALT_ECC_SDMMC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
158 /* Produces a ALT_ECC_SDMMC_CTL_ECC_EN register field value suitable for setting the register. */
159 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
160 
161 /*
162  * Field : CNT_RSTA
163  *
164  * Enable to reset internal single-bit error counter A value to zero
165  *
166  * Field Access Macros:
167  *
168  */
169 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_CTL_CNT_RSTA register field. */
170 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_LSB 8
171 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_CTL_CNT_RSTA register field. */
172 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_MSB 8
173 /* The width in bits of the ALT_ECC_SDMMC_CTL_CNT_RSTA register field. */
174 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_WIDTH 1
175 /* The mask used to set the ALT_ECC_SDMMC_CTL_CNT_RSTA register field value. */
176 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET_MSK 0x00000100
177 /* The mask used to clear the ALT_ECC_SDMMC_CTL_CNT_RSTA register field value. */
178 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
179 /* The reset value of the ALT_ECC_SDMMC_CTL_CNT_RSTA register field. */
180 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_RESET 0x0
181 /* Extracts the ALT_ECC_SDMMC_CTL_CNT_RSTA field value from a register. */
182 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
183 /* Produces a ALT_ECC_SDMMC_CTL_CNT_RSTA register field value suitable for setting the register. */
184 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
185 
186 /*
187  * Field : CNT_RSTB
188  *
189  * Enable to reset internal single-bit error counter B value to zero
190  *
191  * Field Access Macros:
192  *
193  */
194 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_CTL_CNT_RSTB register field. */
195 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_LSB 9
196 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_CTL_CNT_RSTB register field. */
197 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_MSB 9
198 /* The width in bits of the ALT_ECC_SDMMC_CTL_CNT_RSTB register field. */
199 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_WIDTH 1
200 /* The mask used to set the ALT_ECC_SDMMC_CTL_CNT_RSTB register field value. */
201 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET_MSK 0x00000200
202 /* The mask used to clear the ALT_ECC_SDMMC_CTL_CNT_RSTB register field value. */
203 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_CLR_MSK 0xfffffdff
204 /* The reset value of the ALT_ECC_SDMMC_CTL_CNT_RSTB register field. */
205 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_RESET 0x0
206 /* Extracts the ALT_ECC_SDMMC_CTL_CNT_RSTB field value from a register. */
207 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_GET(value) (((value) & 0x00000200) >> 9)
208 /* Produces a ALT_ECC_SDMMC_CTL_CNT_RSTB register field value suitable for setting the register. */
209 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET(value) (((value) << 9) & 0x00000200)
210 
211 /*
212  * Field : INITA
213  *
214  * Enable for the hardware memory initialization PORTA.
215  *
216  * Field Access Macros:
217  *
218  */
219 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_CTL_INITA register field. */
220 #define ALT_ECC_SDMMC_CTL_INITA_LSB 16
221 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_CTL_INITA register field. */
222 #define ALT_ECC_SDMMC_CTL_INITA_MSB 16
223 /* The width in bits of the ALT_ECC_SDMMC_CTL_INITA register field. */
224 #define ALT_ECC_SDMMC_CTL_INITA_WIDTH 1
225 /* The mask used to set the ALT_ECC_SDMMC_CTL_INITA register field value. */
226 #define ALT_ECC_SDMMC_CTL_INITA_SET_MSK 0x00010000
227 /* The mask used to clear the ALT_ECC_SDMMC_CTL_INITA register field value. */
228 #define ALT_ECC_SDMMC_CTL_INITA_CLR_MSK 0xfffeffff
229 /* The reset value of the ALT_ECC_SDMMC_CTL_INITA register field. */
230 #define ALT_ECC_SDMMC_CTL_INITA_RESET 0x0
231 /* Extracts the ALT_ECC_SDMMC_CTL_INITA field value from a register. */
232 #define ALT_ECC_SDMMC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
233 /* Produces a ALT_ECC_SDMMC_CTL_INITA register field value suitable for setting the register. */
234 #define ALT_ECC_SDMMC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
235 
236 /*
237  * Field : INITB
238  *
239  * Enable for the hardware memory initialization PORTB.
240  *
241  * Field Access Macros:
242  *
243  */
244 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_CTL_INITB register field. */
245 #define ALT_ECC_SDMMC_CTL_INITB_LSB 24
246 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_CTL_INITB register field. */
247 #define ALT_ECC_SDMMC_CTL_INITB_MSB 24
248 /* The width in bits of the ALT_ECC_SDMMC_CTL_INITB register field. */
249 #define ALT_ECC_SDMMC_CTL_INITB_WIDTH 1
250 /* The mask used to set the ALT_ECC_SDMMC_CTL_INITB register field value. */
251 #define ALT_ECC_SDMMC_CTL_INITB_SET_MSK 0x01000000
252 /* The mask used to clear the ALT_ECC_SDMMC_CTL_INITB register field value. */
253 #define ALT_ECC_SDMMC_CTL_INITB_CLR_MSK 0xfeffffff
254 /* The reset value of the ALT_ECC_SDMMC_CTL_INITB register field. */
255 #define ALT_ECC_SDMMC_CTL_INITB_RESET 0x0
256 /* Extracts the ALT_ECC_SDMMC_CTL_INITB field value from a register. */
257 #define ALT_ECC_SDMMC_CTL_INITB_GET(value) (((value) & 0x01000000) >> 24)
258 /* Produces a ALT_ECC_SDMMC_CTL_INITB register field value suitable for setting the register. */
259 #define ALT_ECC_SDMMC_CTL_INITB_SET(value) (((value) << 24) & 0x01000000)
260 
261 #ifndef __ASSEMBLY__
262 /*
263  * WARNING: The C register and register group struct declarations are provided for
264  * convenience and illustrative purposes. They should, however, be used with
265  * caution as the C language standard provides no guarantees about the alignment or
266  * atomicity of device memory accesses. The recommended practice for writing
267  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
268  * alt_write_word() functions.
269  *
270  * The struct declaration for register ALT_ECC_SDMMC_CTL.
271  */
272 struct ALT_ECC_SDMMC_CTL_s
273 {
274  uint32_t ECC_EN : 1; /* ALT_ECC_SDMMC_CTL_ECC_EN */
275  uint32_t : 7; /* *UNDEFINED* */
276  uint32_t CNT_RSTA : 1; /* ALT_ECC_SDMMC_CTL_CNT_RSTA */
277  uint32_t CNT_RSTB : 1; /* ALT_ECC_SDMMC_CTL_CNT_RSTB */
278  uint32_t : 6; /* *UNDEFINED* */
279  uint32_t INITA : 1; /* ALT_ECC_SDMMC_CTL_INITA */
280  uint32_t : 7; /* *UNDEFINED* */
281  uint32_t INITB : 1; /* ALT_ECC_SDMMC_CTL_INITB */
282  uint32_t : 7; /* *UNDEFINED* */
283 };
284 
285 /* The typedef declaration for register ALT_ECC_SDMMC_CTL. */
286 typedef volatile struct ALT_ECC_SDMMC_CTL_s ALT_ECC_SDMMC_CTL_t;
287 #endif /* __ASSEMBLY__ */
288 
289 /* The reset value of the ALT_ECC_SDMMC_CTL register. */
290 #define ALT_ECC_SDMMC_CTL_RESET 0x00000000
291 /* The byte offset of the ALT_ECC_SDMMC_CTL register from the beginning of the component. */
292 #define ALT_ECC_SDMMC_CTL_OFST 0x8
293 
294 /*
295  * Register : INITSTAT
296  *
297  * This bit is used to set the initialize the memory and ecc to a known value
298  *
299  * Register Layout
300  *
301  * Bits | Access | Reset | Description
302  * :-------|:-------|:------|:-------------------------------------
303  * [0] | RW | 0x0 | ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA
304  * [7:1] | ??? | 0x0 | *UNDEFINED*
305  * [8] | RW | 0x0 | ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB
306  * [31:9] | ??? | 0x0 | *UNDEFINED*
307  *
308  */
309 /*
310  * Field : INITCOMPLETEA
311  *
312  * This bit is used to verify if the hardware memory initialization has completed
313  * PORTB.
314  *
315  * Field Access Macros:
316  *
317  */
318 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field. */
319 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_LSB 0
320 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field. */
321 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_MSB 0
322 /* The width in bits of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field. */
323 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_WIDTH 1
324 /* The mask used to set the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field value. */
325 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
326 /* The mask used to clear the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field value. */
327 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
328 /* The reset value of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field. */
329 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_RESET 0x0
330 /* Extracts the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA field value from a register. */
331 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
332 /* Produces a ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA register field value suitable for setting the register. */
333 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
334 
335 /*
336  * Field : INITCOMPLETEB
337  *
338  * This bit is used to verify if the hardware memory initialization has completed
339  * PORTB.
340  *
341  * Field Access Macros:
342  *
343  */
344 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field. */
345 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_LSB 8
346 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field. */
347 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_MSB 8
348 /* The width in bits of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field. */
349 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_WIDTH 1
350 /* The mask used to set the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field value. */
351 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET_MSK 0x00000100
352 /* The mask used to clear the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field value. */
353 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_CLR_MSK 0xfffffeff
354 /* The reset value of the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field. */
355 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_RESET 0x0
356 /* Extracts the ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB field value from a register. */
357 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_GET(value) (((value) & 0x00000100) >> 8)
358 /* Produces a ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB register field value suitable for setting the register. */
359 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET(value) (((value) << 8) & 0x00000100)
360 
361 #ifndef __ASSEMBLY__
362 /*
363  * WARNING: The C register and register group struct declarations are provided for
364  * convenience and illustrative purposes. They should, however, be used with
365  * caution as the C language standard provides no guarantees about the alignment or
366  * atomicity of device memory accesses. The recommended practice for writing
367  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
368  * alt_write_word() functions.
369  *
370  * The struct declaration for register ALT_ECC_SDMMC_INITSTAT.
371  */
372 struct ALT_ECC_SDMMC_INITSTAT_s
373 {
374  uint32_t INITCOMPLETEA : 1; /* ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA */
375  uint32_t : 7; /* *UNDEFINED* */
376  uint32_t INITCOMPLETEB : 1; /* ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB */
377  uint32_t : 23; /* *UNDEFINED* */
378 };
379 
380 /* The typedef declaration for register ALT_ECC_SDMMC_INITSTAT. */
381 typedef volatile struct ALT_ECC_SDMMC_INITSTAT_s ALT_ECC_SDMMC_INITSTAT_t;
382 #endif /* __ASSEMBLY__ */
383 
384 /* The reset value of the ALT_ECC_SDMMC_INITSTAT register. */
385 #define ALT_ECC_SDMMC_INITSTAT_RESET 0x00000000
386 /* The byte offset of the ALT_ECC_SDMMC_INITSTAT register from the beginning of the component. */
387 #define ALT_ECC_SDMMC_INITSTAT_OFST 0xc
388 
389 /*
390  * Register : ERRINTEN
391  *
392  * Error Interrupt enable
393  *
394  * Register Layout
395  *
396  * Bits | Access | Reset | Description
397  * :-------|:-------|:------|:---------------------------------
398  * [0] | RW | 0x0 | ALT_ECC_SDMMC_ERRINTEN_SERRINTEN
399  * [31:1] | ??? | 0x0 | *UNDEFINED*
400  *
401  */
402 /*
403  * Field : SERRINTEN
404  *
405  * This bit is used to enable the single bit error interrupt of ECC RAM system
406  *
407  * Field Access Macros:
408  *
409  */
410 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field. */
411 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_LSB 0
412 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field. */
413 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_MSB 0
414 /* The width in bits of the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field. */
415 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_WIDTH 1
416 /* The mask used to set the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field value. */
417 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
418 /* The mask used to clear the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field value. */
419 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
420 /* The reset value of the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field. */
421 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_RESET 0x0
422 /* Extracts the ALT_ECC_SDMMC_ERRINTEN_SERRINTEN field value from a register. */
423 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
424 /* Produces a ALT_ECC_SDMMC_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
425 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
426 
427 #ifndef __ASSEMBLY__
428 /*
429  * WARNING: The C register and register group struct declarations are provided for
430  * convenience and illustrative purposes. They should, however, be used with
431  * caution as the C language standard provides no guarantees about the alignment or
432  * atomicity of device memory accesses. The recommended practice for writing
433  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
434  * alt_write_word() functions.
435  *
436  * The struct declaration for register ALT_ECC_SDMMC_ERRINTEN.
437  */
438 struct ALT_ECC_SDMMC_ERRINTEN_s
439 {
440  uint32_t SERRINTEN : 1; /* ALT_ECC_SDMMC_ERRINTEN_SERRINTEN */
441  uint32_t : 31; /* *UNDEFINED* */
442 };
443 
444 /* The typedef declaration for register ALT_ECC_SDMMC_ERRINTEN. */
445 typedef volatile struct ALT_ECC_SDMMC_ERRINTEN_s ALT_ECC_SDMMC_ERRINTEN_t;
446 #endif /* __ASSEMBLY__ */
447 
448 /* The reset value of the ALT_ECC_SDMMC_ERRINTEN register. */
449 #define ALT_ECC_SDMMC_ERRINTEN_RESET 0x00000000
450 /* The byte offset of the ALT_ECC_SDMMC_ERRINTEN register from the beginning of the component. */
451 #define ALT_ECC_SDMMC_ERRINTEN_OFST 0x10
452 
453 /*
454  * Register : ERRINTENS
455  *
456  * Error Interrupt set
457  *
458  * Register Layout
459  *
460  * Bits | Access | Reset | Description
461  * :-------|:-------|:------|:---------------------------------
462  * [0] | RW | 0x0 | ALT_ECC_SDMMC_ERRINTENS_SERRINTS
463  * [31:1] | ??? | 0x0 | *UNDEFINED*
464  *
465  */
466 /*
467  * Field : SERRINTS
468  *
469  * This bit is used to set the single-bit error interrupt bit.
470  *
471  * Field Access Macros:
472  *
473  */
474 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field. */
475 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_LSB 0
476 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field. */
477 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_MSB 0
478 /* The width in bits of the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field. */
479 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_WIDTH 1
480 /* The mask used to set the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field value. */
481 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
482 /* The mask used to clear the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field value. */
483 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
484 /* The reset value of the ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field. */
485 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_RESET 0x0
486 /* Extracts the ALT_ECC_SDMMC_ERRINTENS_SERRINTS field value from a register. */
487 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
488 /* Produces a ALT_ECC_SDMMC_ERRINTENS_SERRINTS register field value suitable for setting the register. */
489 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
490 
491 #ifndef __ASSEMBLY__
492 /*
493  * WARNING: The C register and register group struct declarations are provided for
494  * convenience and illustrative purposes. They should, however, be used with
495  * caution as the C language standard provides no guarantees about the alignment or
496  * atomicity of device memory accesses. The recommended practice for writing
497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
498  * alt_write_word() functions.
499  *
500  * The struct declaration for register ALT_ECC_SDMMC_ERRINTENS.
501  */
502 struct ALT_ECC_SDMMC_ERRINTENS_s
503 {
504  uint32_t SERRINTS : 1; /* ALT_ECC_SDMMC_ERRINTENS_SERRINTS */
505  uint32_t : 31; /* *UNDEFINED* */
506 };
507 
508 /* The typedef declaration for register ALT_ECC_SDMMC_ERRINTENS. */
509 typedef volatile struct ALT_ECC_SDMMC_ERRINTENS_s ALT_ECC_SDMMC_ERRINTENS_t;
510 #endif /* __ASSEMBLY__ */
511 
512 /* The reset value of the ALT_ECC_SDMMC_ERRINTENS register. */
513 #define ALT_ECC_SDMMC_ERRINTENS_RESET 0x00000000
514 /* The byte offset of the ALT_ECC_SDMMC_ERRINTENS register from the beginning of the component. */
515 #define ALT_ECC_SDMMC_ERRINTENS_OFST 0x14
516 
517 /*
518  * Register : ERRINTENR
519  *
520  * Error Interrupt reset.
521  *
522  * Register Layout
523  *
524  * Bits | Access | Reset | Description
525  * :-------|:-------|:------|:---------------------------------
526  * [0] | RW | 0x0 | ALT_ECC_SDMMC_ERRINTENR_SERRINTR
527  * [31:1] | ??? | 0x0 | *UNDEFINED*
528  *
529  */
530 /*
531  * Field : SERRINTR
532  *
533  * This bit is used to reset the single-bit error interrupt bit. o
534  *
535  * Reads reflect SERRINTEN.
536  *
537  * 1'b0: Writing of zero has no effect.
538  *
539  * 1'b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing
540  * a bitwise writing of this feature.
541  *
542  * Field Access Macros:
543  *
544  */
545 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field. */
546 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_LSB 0
547 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field. */
548 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_MSB 0
549 /* The width in bits of the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field. */
550 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_WIDTH 1
551 /* The mask used to set the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field value. */
552 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
553 /* The mask used to clear the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field value. */
554 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
555 /* The reset value of the ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field. */
556 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_RESET 0x0
557 /* Extracts the ALT_ECC_SDMMC_ERRINTENR_SERRINTR field value from a register. */
558 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
559 /* Produces a ALT_ECC_SDMMC_ERRINTENR_SERRINTR register field value suitable for setting the register. */
560 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
561 
562 #ifndef __ASSEMBLY__
563 /*
564  * WARNING: The C register and register group struct declarations are provided for
565  * convenience and illustrative purposes. They should, however, be used with
566  * caution as the C language standard provides no guarantees about the alignment or
567  * atomicity of device memory accesses. The recommended practice for writing
568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
569  * alt_write_word() functions.
570  *
571  * The struct declaration for register ALT_ECC_SDMMC_ERRINTENR.
572  */
573 struct ALT_ECC_SDMMC_ERRINTENR_s
574 {
575  uint32_t SERRINTR : 1; /* ALT_ECC_SDMMC_ERRINTENR_SERRINTR */
576  uint32_t : 31; /* *UNDEFINED* */
577 };
578 
579 /* The typedef declaration for register ALT_ECC_SDMMC_ERRINTENR. */
580 typedef volatile struct ALT_ECC_SDMMC_ERRINTENR_s ALT_ECC_SDMMC_ERRINTENR_t;
581 #endif /* __ASSEMBLY__ */
582 
583 /* The reset value of the ALT_ECC_SDMMC_ERRINTENR register. */
584 #define ALT_ECC_SDMMC_ERRINTENR_RESET 0x00000000
585 /* The byte offset of the ALT_ECC_SDMMC_ERRINTENR register from the beginning of the component. */
586 #define ALT_ECC_SDMMC_ERRINTENR_OFST 0x18
587 
588 /*
589  * Register : INTMODE
590  *
591  * Reads reflect SERRINTEN.
592  *
593  * Register Layout
594  *
595  * Bits | Access | Reset | Description
596  * :--------|:-------|:------|:------------------------------
597  * [0] | RW | 0x0 | ALT_ECC_SDMMC_INTMOD_INTMOD
598  * [7:1] | ??? | 0x0 | *UNDEFINED*
599  * [8] | RW | 0x0 | ALT_ECC_SDMMC_INTMOD_INTONOVF
600  * [15:9] | ??? | 0x0 | *UNDEFINED*
601  * [16] | RW | 0x0 | ALT_ECC_SDMMC_INTMOD_INTONCMP
602  * [31:17] | ??? | 0x0 | *UNDEFINED*
603  *
604  */
605 /*
606  * Field : INTMODE
607  *
608  * Interrupt mode for single-bit errors.
609  *
610  * Field Access Macros:
611  *
612  */
613 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTMOD_INTMOD register field. */
614 #define ALT_ECC_SDMMC_INTMOD_INTMOD_LSB 0
615 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTMOD_INTMOD register field. */
616 #define ALT_ECC_SDMMC_INTMOD_INTMOD_MSB 0
617 /* The width in bits of the ALT_ECC_SDMMC_INTMOD_INTMOD register field. */
618 #define ALT_ECC_SDMMC_INTMOD_INTMOD_WIDTH 1
619 /* The mask used to set the ALT_ECC_SDMMC_INTMOD_INTMOD register field value. */
620 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET_MSK 0x00000001
621 /* The mask used to clear the ALT_ECC_SDMMC_INTMOD_INTMOD register field value. */
622 #define ALT_ECC_SDMMC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
623 /* The reset value of the ALT_ECC_SDMMC_INTMOD_INTMOD register field. */
624 #define ALT_ECC_SDMMC_INTMOD_INTMOD_RESET 0x0
625 /* Extracts the ALT_ECC_SDMMC_INTMOD_INTMOD field value from a register. */
626 #define ALT_ECC_SDMMC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
627 /* Produces a ALT_ECC_SDMMC_INTMOD_INTMOD register field value suitable for setting the register. */
628 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
629 
630 /*
631  * Field : INTONOVF
632  *
633  * Enable interrupt on overflow.
634  *
635  * Field Access Macros:
636  *
637  */
638 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTMOD_INTONOVF register field. */
639 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_LSB 8
640 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTMOD_INTONOVF register field. */
641 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_MSB 8
642 /* The width in bits of the ALT_ECC_SDMMC_INTMOD_INTONOVF register field. */
643 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_WIDTH 1
644 /* The mask used to set the ALT_ECC_SDMMC_INTMOD_INTONOVF register field value. */
645 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET_MSK 0x00000100
646 /* The mask used to clear the ALT_ECC_SDMMC_INTMOD_INTONOVF register field value. */
647 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
648 /* The reset value of the ALT_ECC_SDMMC_INTMOD_INTONOVF register field. */
649 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_RESET 0x0
650 /* Extracts the ALT_ECC_SDMMC_INTMOD_INTONOVF field value from a register. */
651 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
652 /* Produces a ALT_ECC_SDMMC_INTMOD_INTONOVF register field value suitable for setting the register. */
653 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
654 
655 /*
656  * Field : INTONCMP
657  *
658  * Enable interrupt on compare.
659  *
660  * Field Access Macros:
661  *
662  */
663 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTMOD_INTONCMP register field. */
664 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_LSB 16
665 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTMOD_INTONCMP register field. */
666 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_MSB 16
667 /* The width in bits of the ALT_ECC_SDMMC_INTMOD_INTONCMP register field. */
668 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_WIDTH 1
669 /* The mask used to set the ALT_ECC_SDMMC_INTMOD_INTONCMP register field value. */
670 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET_MSK 0x00010000
671 /* The mask used to clear the ALT_ECC_SDMMC_INTMOD_INTONCMP register field value. */
672 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
673 /* The reset value of the ALT_ECC_SDMMC_INTMOD_INTONCMP register field. */
674 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_RESET 0x0
675 /* Extracts the ALT_ECC_SDMMC_INTMOD_INTONCMP field value from a register. */
676 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
677 /* Produces a ALT_ECC_SDMMC_INTMOD_INTONCMP register field value suitable for setting the register. */
678 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
679 
680 #ifndef __ASSEMBLY__
681 /*
682  * WARNING: The C register and register group struct declarations are provided for
683  * convenience and illustrative purposes. They should, however, be used with
684  * caution as the C language standard provides no guarantees about the alignment or
685  * atomicity of device memory accesses. The recommended practice for writing
686  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
687  * alt_write_word() functions.
688  *
689  * The struct declaration for register ALT_ECC_SDMMC_INTMOD.
690  */
691 struct ALT_ECC_SDMMC_INTMOD_s
692 {
693  uint32_t INTMODE : 1; /* ALT_ECC_SDMMC_INTMOD_INTMOD */
694  uint32_t : 7; /* *UNDEFINED* */
695  uint32_t INTONOVF : 1; /* ALT_ECC_SDMMC_INTMOD_INTONOVF */
696  uint32_t : 7; /* *UNDEFINED* */
697  uint32_t INTONCMP : 1; /* ALT_ECC_SDMMC_INTMOD_INTONCMP */
698  uint32_t : 15; /* *UNDEFINED* */
699 };
700 
701 /* The typedef declaration for register ALT_ECC_SDMMC_INTMOD. */
702 typedef volatile struct ALT_ECC_SDMMC_INTMOD_s ALT_ECC_SDMMC_INTMOD_t;
703 #endif /* __ASSEMBLY__ */
704 
705 /* The reset value of the ALT_ECC_SDMMC_INTMOD register. */
706 #define ALT_ECC_SDMMC_INTMOD_RESET 0x00000000
707 /* The byte offset of the ALT_ECC_SDMMC_INTMOD register from the beginning of the component. */
708 #define ALT_ECC_SDMMC_INTMOD_OFST 0x1c
709 
710 /*
711  * Register : INTSTAT
712  *
713  * This bit is used to enable interrupt generation on SERR lookup table overflow.
714  * When all the entries in the table are valid=1 and this is bit is enabled,
715  * serr_req signal will be asserted.
716  *
717  * Register Layout
718  *
719  * Bits | Access | Reset | Description
720  * :--------|:-------|:------|:-------------------------------
721  * [0] | RW | 0x0 | ALT_ECC_SDMMC_INTSTAT_SERRPENA
722  * [7:1] | ??? | 0x0 | *UNDEFINED*
723  * [8] | RW | 0x0 | ALT_ECC_SDMMC_INTSTAT_DERRPENA
724  * [15:9] | ??? | 0x0 | *UNDEFINED*
725  * [16] | RW | 0x0 | ALT_ECC_SDMMC_INTSTAT_SERRPENB
726  * [23:17] | ??? | 0x0 | *UNDEFINED*
727  * [24] | RW | 0x0 | ALT_ECC_SDMMC_INTSTAT_DERRPENB
728  * [31:25] | ??? | 0x0 | *UNDEFINED*
729  *
730  */
731 /*
732  * Field : SERRPENA
733  *
734  * Single-bit error pending for PORTA.
735  *
736  * Field Access Macros:
737  *
738  */
739 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field. */
740 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_LSB 0
741 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field. */
742 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_MSB 0
743 /* The width in bits of the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field. */
744 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_WIDTH 1
745 /* The mask used to set the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field value. */
746 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET_MSK 0x00000001
747 /* The mask used to clear the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field value. */
748 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
749 /* The reset value of the ALT_ECC_SDMMC_INTSTAT_SERRPENA register field. */
750 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_RESET 0x0
751 /* Extracts the ALT_ECC_SDMMC_INTSTAT_SERRPENA field value from a register. */
752 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
753 /* Produces a ALT_ECC_SDMMC_INTSTAT_SERRPENA register field value suitable for setting the register. */
754 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
755 
756 /*
757  * Field : DERRPENA
758  *
759  * Double-bit error pending for PORTA.
760  *
761  * Field Access Macros:
762  *
763  */
764 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field. */
765 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_LSB 8
766 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field. */
767 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_MSB 8
768 /* The width in bits of the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field. */
769 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_WIDTH 1
770 /* The mask used to set the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field value. */
771 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET_MSK 0x00000100
772 /* The mask used to clear the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field value. */
773 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
774 /* The reset value of the ALT_ECC_SDMMC_INTSTAT_DERRPENA register field. */
775 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_RESET 0x0
776 /* Extracts the ALT_ECC_SDMMC_INTSTAT_DERRPENA field value from a register. */
777 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
778 /* Produces a ALT_ECC_SDMMC_INTSTAT_DERRPENA register field value suitable for setting the register. */
779 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
780 
781 /*
782  * Field : SERRPENB
783  *
784  * Single-bit error pending for PORTB.
785  *
786  * Field Access Macros:
787  *
788  */
789 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field. */
790 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_LSB 16
791 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field. */
792 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_MSB 16
793 /* The width in bits of the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field. */
794 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_WIDTH 1
795 /* The mask used to set the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field value. */
796 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET_MSK 0x00010000
797 /* The mask used to clear the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field value. */
798 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_CLR_MSK 0xfffeffff
799 /* The reset value of the ALT_ECC_SDMMC_INTSTAT_SERRPENB register field. */
800 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_RESET 0x0
801 /* Extracts the ALT_ECC_SDMMC_INTSTAT_SERRPENB field value from a register. */
802 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_GET(value) (((value) & 0x00010000) >> 16)
803 /* Produces a ALT_ECC_SDMMC_INTSTAT_SERRPENB register field value suitable for setting the register. */
804 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET(value) (((value) << 16) & 0x00010000)
805 
806 /*
807  * Field : DERRPENB
808  *
809  * Double-bit error pending PORTB.
810  *
811  * Field Access Macros:
812  *
813  */
814 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field. */
815 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_LSB 24
816 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field. */
817 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_MSB 24
818 /* The width in bits of the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field. */
819 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_WIDTH 1
820 /* The mask used to set the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field value. */
821 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET_MSK 0x01000000
822 /* The mask used to clear the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field value. */
823 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_CLR_MSK 0xfeffffff
824 /* The reset value of the ALT_ECC_SDMMC_INTSTAT_DERRPENB register field. */
825 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_RESET 0x0
826 /* Extracts the ALT_ECC_SDMMC_INTSTAT_DERRPENB field value from a register. */
827 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_GET(value) (((value) & 0x01000000) >> 24)
828 /* Produces a ALT_ECC_SDMMC_INTSTAT_DERRPENB register field value suitable for setting the register. */
829 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET(value) (((value) << 24) & 0x01000000)
830 
831 #ifndef __ASSEMBLY__
832 /*
833  * WARNING: The C register and register group struct declarations are provided for
834  * convenience and illustrative purposes. They should, however, be used with
835  * caution as the C language standard provides no guarantees about the alignment or
836  * atomicity of device memory accesses. The recommended practice for writing
837  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
838  * alt_write_word() functions.
839  *
840  * The struct declaration for register ALT_ECC_SDMMC_INTSTAT.
841  */
842 struct ALT_ECC_SDMMC_INTSTAT_s
843 {
844  uint32_t SERRPENA : 1; /* ALT_ECC_SDMMC_INTSTAT_SERRPENA */
845  uint32_t : 7; /* *UNDEFINED* */
846  uint32_t DERRPENA : 1; /* ALT_ECC_SDMMC_INTSTAT_DERRPENA */
847  uint32_t : 7; /* *UNDEFINED* */
848  uint32_t SERRPENB : 1; /* ALT_ECC_SDMMC_INTSTAT_SERRPENB */
849  uint32_t : 7; /* *UNDEFINED* */
850  uint32_t DERRPENB : 1; /* ALT_ECC_SDMMC_INTSTAT_DERRPENB */
851  uint32_t : 7; /* *UNDEFINED* */
852 };
853 
854 /* The typedef declaration for register ALT_ECC_SDMMC_INTSTAT. */
855 typedef volatile struct ALT_ECC_SDMMC_INTSTAT_s ALT_ECC_SDMMC_INTSTAT_t;
856 #endif /* __ASSEMBLY__ */
857 
858 /* The reset value of the ALT_ECC_SDMMC_INTSTAT register. */
859 #define ALT_ECC_SDMMC_INTSTAT_RESET 0x00000000
860 /* The byte offset of the ALT_ECC_SDMMC_INTSTAT register from the beginning of the component. */
861 #define ALT_ECC_SDMMC_INTSTAT_OFST 0x20
862 
863 /*
864  * Register : INTTEST
865  *
866  * This bits is used to test interrupt from ECC RAM to GIC
867  *
868  * Register Layout
869  *
870  * Bits | Access | Reset | Description
871  * :--------|:-------|:------|:-----------------------------
872  * [0] | RW | 0x0 | ALT_ECC_SDMMC_INTTEST_TSERRA
873  * [7:1] | ??? | 0x0 | *UNDEFINED*
874  * [8] | RW | 0x0 | ALT_ECC_SDMMC_INTTEST_TDERRA
875  * [15:9] | ??? | 0x0 | *UNDEFINED*
876  * [16] | RW | 0x0 | ALT_ECC_SDMMC_INTTEST_TSERRB
877  * [23:17] | ??? | 0x0 | *UNDEFINED*
878  * [24] | RW | 0x0 | ALT_ECC_SDMMC_INTTEST_TDERRB
879  * [31:25] | ??? | 0x0 | *UNDEFINED*
880  *
881  */
882 /*
883  * Field : TSERRA
884  *
885  * Test PORTA Single-bit error.
886  *
887  * Field Access Macros:
888  *
889  */
890 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTTEST_TSERRA register field. */
891 #define ALT_ECC_SDMMC_INTTEST_TSERRA_LSB 0
892 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTTEST_TSERRA register field. */
893 #define ALT_ECC_SDMMC_INTTEST_TSERRA_MSB 0
894 /* The width in bits of the ALT_ECC_SDMMC_INTTEST_TSERRA register field. */
895 #define ALT_ECC_SDMMC_INTTEST_TSERRA_WIDTH 1
896 /* The mask used to set the ALT_ECC_SDMMC_INTTEST_TSERRA register field value. */
897 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET_MSK 0x00000001
898 /* The mask used to clear the ALT_ECC_SDMMC_INTTEST_TSERRA register field value. */
899 #define ALT_ECC_SDMMC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
900 /* The reset value of the ALT_ECC_SDMMC_INTTEST_TSERRA register field. */
901 #define ALT_ECC_SDMMC_INTTEST_TSERRA_RESET 0x0
902 /* Extracts the ALT_ECC_SDMMC_INTTEST_TSERRA field value from a register. */
903 #define ALT_ECC_SDMMC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
904 /* Produces a ALT_ECC_SDMMC_INTTEST_TSERRA register field value suitable for setting the register. */
905 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
906 
907 /*
908  * Field : TDERRA
909  *
910  * Test PORTA Double-bit error.
911  *
912  * Field Access Macros:
913  *
914  */
915 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTTEST_TDERRA register field. */
916 #define ALT_ECC_SDMMC_INTTEST_TDERRA_LSB 8
917 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTTEST_TDERRA register field. */
918 #define ALT_ECC_SDMMC_INTTEST_TDERRA_MSB 8
919 /* The width in bits of the ALT_ECC_SDMMC_INTTEST_TDERRA register field. */
920 #define ALT_ECC_SDMMC_INTTEST_TDERRA_WIDTH 1
921 /* The mask used to set the ALT_ECC_SDMMC_INTTEST_TDERRA register field value. */
922 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET_MSK 0x00000100
923 /* The mask used to clear the ALT_ECC_SDMMC_INTTEST_TDERRA register field value. */
924 #define ALT_ECC_SDMMC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
925 /* The reset value of the ALT_ECC_SDMMC_INTTEST_TDERRA register field. */
926 #define ALT_ECC_SDMMC_INTTEST_TDERRA_RESET 0x0
927 /* Extracts the ALT_ECC_SDMMC_INTTEST_TDERRA field value from a register. */
928 #define ALT_ECC_SDMMC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
929 /* Produces a ALT_ECC_SDMMC_INTTEST_TDERRA register field value suitable for setting the register. */
930 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
931 
932 /*
933  * Field : TSERRB
934  *
935  * Test PORTB Single-bit error.
936  *
937  * Field Access Macros:
938  *
939  */
940 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTTEST_TSERRB register field. */
941 #define ALT_ECC_SDMMC_INTTEST_TSERRB_LSB 16
942 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTTEST_TSERRB register field. */
943 #define ALT_ECC_SDMMC_INTTEST_TSERRB_MSB 16
944 /* The width in bits of the ALT_ECC_SDMMC_INTTEST_TSERRB register field. */
945 #define ALT_ECC_SDMMC_INTTEST_TSERRB_WIDTH 1
946 /* The mask used to set the ALT_ECC_SDMMC_INTTEST_TSERRB register field value. */
947 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET_MSK 0x00010000
948 /* The mask used to clear the ALT_ECC_SDMMC_INTTEST_TSERRB register field value. */
949 #define ALT_ECC_SDMMC_INTTEST_TSERRB_CLR_MSK 0xfffeffff
950 /* The reset value of the ALT_ECC_SDMMC_INTTEST_TSERRB register field. */
951 #define ALT_ECC_SDMMC_INTTEST_TSERRB_RESET 0x0
952 /* Extracts the ALT_ECC_SDMMC_INTTEST_TSERRB field value from a register. */
953 #define ALT_ECC_SDMMC_INTTEST_TSERRB_GET(value) (((value) & 0x00010000) >> 16)
954 /* Produces a ALT_ECC_SDMMC_INTTEST_TSERRB register field value suitable for setting the register. */
955 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET(value) (((value) << 16) & 0x00010000)
956 
957 /*
958  * Field : TDERRB
959  *
960  * Test PORTB Double-bit error.
961  *
962  * Field Access Macros:
963  *
964  */
965 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_INTTEST_TDERRB register field. */
966 #define ALT_ECC_SDMMC_INTTEST_TDERRB_LSB 24
967 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_INTTEST_TDERRB register field. */
968 #define ALT_ECC_SDMMC_INTTEST_TDERRB_MSB 24
969 /* The width in bits of the ALT_ECC_SDMMC_INTTEST_TDERRB register field. */
970 #define ALT_ECC_SDMMC_INTTEST_TDERRB_WIDTH 1
971 /* The mask used to set the ALT_ECC_SDMMC_INTTEST_TDERRB register field value. */
972 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET_MSK 0x01000000
973 /* The mask used to clear the ALT_ECC_SDMMC_INTTEST_TDERRB register field value. */
974 #define ALT_ECC_SDMMC_INTTEST_TDERRB_CLR_MSK 0xfeffffff
975 /* The reset value of the ALT_ECC_SDMMC_INTTEST_TDERRB register field. */
976 #define ALT_ECC_SDMMC_INTTEST_TDERRB_RESET 0x0
977 /* Extracts the ALT_ECC_SDMMC_INTTEST_TDERRB field value from a register. */
978 #define ALT_ECC_SDMMC_INTTEST_TDERRB_GET(value) (((value) & 0x01000000) >> 24)
979 /* Produces a ALT_ECC_SDMMC_INTTEST_TDERRB register field value suitable for setting the register. */
980 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET(value) (((value) << 24) & 0x01000000)
981 
982 #ifndef __ASSEMBLY__
983 /*
984  * WARNING: The C register and register group struct declarations are provided for
985  * convenience and illustrative purposes. They should, however, be used with
986  * caution as the C language standard provides no guarantees about the alignment or
987  * atomicity of device memory accesses. The recommended practice for writing
988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
989  * alt_write_word() functions.
990  *
991  * The struct declaration for register ALT_ECC_SDMMC_INTTEST.
992  */
993 struct ALT_ECC_SDMMC_INTTEST_s
994 {
995  uint32_t TSERRA : 1; /* ALT_ECC_SDMMC_INTTEST_TSERRA */
996  uint32_t : 7; /* *UNDEFINED* */
997  uint32_t TDERRA : 1; /* ALT_ECC_SDMMC_INTTEST_TDERRA */
998  uint32_t : 7; /* *UNDEFINED* */
999  uint32_t TSERRB : 1; /* ALT_ECC_SDMMC_INTTEST_TSERRB */
1000  uint32_t : 7; /* *UNDEFINED* */
1001  uint32_t TDERRB : 1; /* ALT_ECC_SDMMC_INTTEST_TDERRB */
1002  uint32_t : 7; /* *UNDEFINED* */
1003 };
1004 
1005 /* The typedef declaration for register ALT_ECC_SDMMC_INTTEST. */
1006 typedef volatile struct ALT_ECC_SDMMC_INTTEST_s ALT_ECC_SDMMC_INTTEST_t;
1007 #endif /* __ASSEMBLY__ */
1008 
1009 /* The reset value of the ALT_ECC_SDMMC_INTTEST register. */
1010 #define ALT_ECC_SDMMC_INTTEST_RESET 0x00000000
1011 /* The byte offset of the ALT_ECC_SDMMC_INTTEST register from the beginning of the component. */
1012 #define ALT_ECC_SDMMC_INTTEST_OFST 0x24
1013 
1014 /*
1015  * Register : MODSTAT
1016  *
1017  * Counter feature status flag
1018  *
1019  * Register Layout
1020  *
1021  * Bits | Access | Reset | Description
1022  * :-------|:-------|:------|:------------------------------
1023  * [0] | RW | 0x0 | ALT_ECC_SDMMC_MODSTAT_CMPFLGA
1024  * [1] | RW | 0x0 | ALT_ECC_SDMMC_MODSTAT_CMPFLGB
1025  * [31:2] | ??? | 0x0 | *UNDEFINED*
1026  *
1027  */
1028 /*
1029  * Field : CMPFLGA
1030  *
1031  * Port A compare status flag
1032  *
1033  * Field Access Macros:
1034  *
1035  */
1036 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field. */
1037 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_LSB 0
1038 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field. */
1039 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_MSB 0
1040 /* The width in bits of the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field. */
1041 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_WIDTH 1
1042 /* The mask used to set the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field value. */
1043 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
1044 /* The mask used to clear the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field value. */
1045 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
1046 /* The reset value of the ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field. */
1047 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_RESET 0x0
1048 /* Extracts the ALT_ECC_SDMMC_MODSTAT_CMPFLGA field value from a register. */
1049 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
1050 /* Produces a ALT_ECC_SDMMC_MODSTAT_CMPFLGA register field value suitable for setting the register. */
1051 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
1052 
1053 /*
1054  * Field : CMPFLGB
1055  *
1056  * Port B compare status flag
1057  *
1058  * Field Access Macros:
1059  *
1060  */
1061 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field. */
1062 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_LSB 1
1063 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field. */
1064 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_MSB 1
1065 /* The width in bits of the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field. */
1066 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_WIDTH 1
1067 /* The mask used to set the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field value. */
1068 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET_MSK 0x00000002
1069 /* The mask used to clear the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field value. */
1070 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_CLR_MSK 0xfffffffd
1071 /* The reset value of the ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field. */
1072 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_RESET 0x0
1073 /* Extracts the ALT_ECC_SDMMC_MODSTAT_CMPFLGB field value from a register. */
1074 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_GET(value) (((value) & 0x00000002) >> 1)
1075 /* Produces a ALT_ECC_SDMMC_MODSTAT_CMPFLGB register field value suitable for setting the register. */
1076 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET(value) (((value) << 1) & 0x00000002)
1077 
1078 #ifndef __ASSEMBLY__
1079 /*
1080  * WARNING: The C register and register group struct declarations are provided for
1081  * convenience and illustrative purposes. They should, however, be used with
1082  * caution as the C language standard provides no guarantees about the alignment or
1083  * atomicity of device memory accesses. The recommended practice for writing
1084  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1085  * alt_write_word() functions.
1086  *
1087  * The struct declaration for register ALT_ECC_SDMMC_MODSTAT.
1088  */
1089 struct ALT_ECC_SDMMC_MODSTAT_s
1090 {
1091  uint32_t CMPFLGA : 1; /* ALT_ECC_SDMMC_MODSTAT_CMPFLGA */
1092  uint32_t CMPFLGB : 1; /* ALT_ECC_SDMMC_MODSTAT_CMPFLGB */
1093  uint32_t : 30; /* *UNDEFINED* */
1094 };
1095 
1096 /* The typedef declaration for register ALT_ECC_SDMMC_MODSTAT. */
1097 typedef volatile struct ALT_ECC_SDMMC_MODSTAT_s ALT_ECC_SDMMC_MODSTAT_t;
1098 #endif /* __ASSEMBLY__ */
1099 
1100 /* The reset value of the ALT_ECC_SDMMC_MODSTAT register. */
1101 #define ALT_ECC_SDMMC_MODSTAT_RESET 0x00000000
1102 /* The byte offset of the ALT_ECC_SDMMC_MODSTAT register from the beginning of the component. */
1103 #define ALT_ECC_SDMMC_MODSTAT_OFST 0x28
1104 
1105 /*
1106  * Register : DERRADDRA
1107  *
1108  * This register shows the address of PORTA current double-bit error. RAM size will
1109  * determine the maximum number of address bits.
1110  *
1111  * Register Layout
1112  *
1113  * Bits | Access | Reset | Description
1114  * :--------|:-------|:------|:-----------------------------
1115  * [9:0] | RW | 0x0 | ALT_ECC_SDMMC_DERRADDRA_ADDR
1116  * [31:10] | ??? | 0x0 | *UNDEFINED*
1117  *
1118  */
1119 /*
1120  * Field : Address
1121  *
1122  * Recent double-bit error address.
1123  *
1124  * Field Access Macros:
1125  *
1126  */
1127 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_DERRADDRA_ADDR register field. */
1128 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_LSB 0
1129 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_DERRADDRA_ADDR register field. */
1130 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_MSB 9
1131 /* The width in bits of the ALT_ECC_SDMMC_DERRADDRA_ADDR register field. */
1132 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_WIDTH 10
1133 /* The mask used to set the ALT_ECC_SDMMC_DERRADDRA_ADDR register field value. */
1134 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET_MSK 0x000003ff
1135 /* The mask used to clear the ALT_ECC_SDMMC_DERRADDRA_ADDR register field value. */
1136 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
1137 /* The reset value of the ALT_ECC_SDMMC_DERRADDRA_ADDR register field. */
1138 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_RESET 0x0
1139 /* Extracts the ALT_ECC_SDMMC_DERRADDRA_ADDR field value from a register. */
1140 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1141 /* Produces a ALT_ECC_SDMMC_DERRADDRA_ADDR register field value suitable for setting the register. */
1142 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1143 
1144 #ifndef __ASSEMBLY__
1145 /*
1146  * WARNING: The C register and register group struct declarations are provided for
1147  * convenience and illustrative purposes. They should, however, be used with
1148  * caution as the C language standard provides no guarantees about the alignment or
1149  * atomicity of device memory accesses. The recommended practice for writing
1150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1151  * alt_write_word() functions.
1152  *
1153  * The struct declaration for register ALT_ECC_SDMMC_DERRADDRA.
1154  */
1155 struct ALT_ECC_SDMMC_DERRADDRA_s
1156 {
1157  uint32_t Address : 10; /* ALT_ECC_SDMMC_DERRADDRA_ADDR */
1158  uint32_t : 22; /* *UNDEFINED* */
1159 };
1160 
1161 /* The typedef declaration for register ALT_ECC_SDMMC_DERRADDRA. */
1162 typedef volatile struct ALT_ECC_SDMMC_DERRADDRA_s ALT_ECC_SDMMC_DERRADDRA_t;
1163 #endif /* __ASSEMBLY__ */
1164 
1165 /* The reset value of the ALT_ECC_SDMMC_DERRADDRA register. */
1166 #define ALT_ECC_SDMMC_DERRADDRA_RESET 0x00000000
1167 /* The byte offset of the ALT_ECC_SDMMC_DERRADDRA register from the beginning of the component. */
1168 #define ALT_ECC_SDMMC_DERRADDRA_OFST 0x2c
1169 
1170 /*
1171  * Register : SERRADDRA
1172  *
1173  * This register shows the address of PORTA current single-bit error. RAM size will
1174  * determine the maximum number of address bits.
1175  *
1176  * Register Layout
1177  *
1178  * Bits | Access | Reset | Description
1179  * :--------|:-------|:------|:-----------------------------
1180  * [9:0] | RW | 0x0 | ALT_ECC_SDMMC_SERRADDRA_ADDR
1181  * [31:10] | ??? | 0x0 | *UNDEFINED*
1182  *
1183  */
1184 /*
1185  * Field : Address
1186  *
1187  * Recent single-bit error address.
1188  *
1189  * Field Access Macros:
1190  *
1191  */
1192 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRADDRA_ADDR register field. */
1193 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_LSB 0
1194 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRADDRA_ADDR register field. */
1195 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_MSB 9
1196 /* The width in bits of the ALT_ECC_SDMMC_SERRADDRA_ADDR register field. */
1197 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_WIDTH 10
1198 /* The mask used to set the ALT_ECC_SDMMC_SERRADDRA_ADDR register field value. */
1199 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET_MSK 0x000003ff
1200 /* The mask used to clear the ALT_ECC_SDMMC_SERRADDRA_ADDR register field value. */
1201 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
1202 /* The reset value of the ALT_ECC_SDMMC_SERRADDRA_ADDR register field. */
1203 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_RESET 0x0
1204 /* Extracts the ALT_ECC_SDMMC_SERRADDRA_ADDR field value from a register. */
1205 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1206 /* Produces a ALT_ECC_SDMMC_SERRADDRA_ADDR register field value suitable for setting the register. */
1207 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1208 
1209 #ifndef __ASSEMBLY__
1210 /*
1211  * WARNING: The C register and register group struct declarations are provided for
1212  * convenience and illustrative purposes. They should, however, be used with
1213  * caution as the C language standard provides no guarantees about the alignment or
1214  * atomicity of device memory accesses. The recommended practice for writing
1215  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1216  * alt_write_word() functions.
1217  *
1218  * The struct declaration for register ALT_ECC_SDMMC_SERRADDRA.
1219  */
1220 struct ALT_ECC_SDMMC_SERRADDRA_s
1221 {
1222  uint32_t Address : 10; /* ALT_ECC_SDMMC_SERRADDRA_ADDR */
1223  uint32_t : 22; /* *UNDEFINED* */
1224 };
1225 
1226 /* The typedef declaration for register ALT_ECC_SDMMC_SERRADDRA. */
1227 typedef volatile struct ALT_ECC_SDMMC_SERRADDRA_s ALT_ECC_SDMMC_SERRADDRA_t;
1228 #endif /* __ASSEMBLY__ */
1229 
1230 /* The reset value of the ALT_ECC_SDMMC_SERRADDRA register. */
1231 #define ALT_ECC_SDMMC_SERRADDRA_RESET 0x00000000
1232 /* The byte offset of the ALT_ECC_SDMMC_SERRADDRA register from the beginning of the component. */
1233 #define ALT_ECC_SDMMC_SERRADDRA_OFST 0x30
1234 
1235 /*
1236  * Register : DERRADDRB
1237  *
1238  * This register shows the address of PORTB current double-bit error. RAM size will
1239  * determine the maximum number of address bits.
1240  *
1241  * Register Layout
1242  *
1243  * Bits | Access | Reset | Description
1244  * :--------|:-------|:------|:-----------------------------
1245  * [9:0] | RW | 0x0 | ALT_ECC_SDMMC_DERRADDRB_ADDR
1246  * [31:10] | ??? | 0x0 | *UNDEFINED*
1247  *
1248  */
1249 /*
1250  * Field : Address
1251  *
1252  * Recent double-bit error address.
1253  *
1254  * Field Access Macros:
1255  *
1256  */
1257 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_DERRADDRB_ADDR register field. */
1258 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_LSB 0
1259 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_DERRADDRB_ADDR register field. */
1260 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_MSB 9
1261 /* The width in bits of the ALT_ECC_SDMMC_DERRADDRB_ADDR register field. */
1262 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_WIDTH 10
1263 /* The mask used to set the ALT_ECC_SDMMC_DERRADDRB_ADDR register field value. */
1264 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET_MSK 0x000003ff
1265 /* The mask used to clear the ALT_ECC_SDMMC_DERRADDRB_ADDR register field value. */
1266 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_CLR_MSK 0xfffffc00
1267 /* The reset value of the ALT_ECC_SDMMC_DERRADDRB_ADDR register field. */
1268 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_RESET 0x0
1269 /* Extracts the ALT_ECC_SDMMC_DERRADDRB_ADDR field value from a register. */
1270 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1271 /* Produces a ALT_ECC_SDMMC_DERRADDRB_ADDR register field value suitable for setting the register. */
1272 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1273 
1274 #ifndef __ASSEMBLY__
1275 /*
1276  * WARNING: The C register and register group struct declarations are provided for
1277  * convenience and illustrative purposes. They should, however, be used with
1278  * caution as the C language standard provides no guarantees about the alignment or
1279  * atomicity of device memory accesses. The recommended practice for writing
1280  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1281  * alt_write_word() functions.
1282  *
1283  * The struct declaration for register ALT_ECC_SDMMC_DERRADDRB.
1284  */
1285 struct ALT_ECC_SDMMC_DERRADDRB_s
1286 {
1287  uint32_t Address : 10; /* ALT_ECC_SDMMC_DERRADDRB_ADDR */
1288  uint32_t : 22; /* *UNDEFINED* */
1289 };
1290 
1291 /* The typedef declaration for register ALT_ECC_SDMMC_DERRADDRB. */
1292 typedef volatile struct ALT_ECC_SDMMC_DERRADDRB_s ALT_ECC_SDMMC_DERRADDRB_t;
1293 #endif /* __ASSEMBLY__ */
1294 
1295 /* The reset value of the ALT_ECC_SDMMC_DERRADDRB register. */
1296 #define ALT_ECC_SDMMC_DERRADDRB_RESET 0x00000000
1297 /* The byte offset of the ALT_ECC_SDMMC_DERRADDRB register from the beginning of the component. */
1298 #define ALT_ECC_SDMMC_DERRADDRB_OFST 0x34
1299 
1300 /*
1301  * Register : SERRADDRB
1302  *
1303  * This register shows the address of PORTB current single-bit error. RAM size will
1304  * determine the maximum number of address bits.
1305  *
1306  * Register Layout
1307  *
1308  * Bits | Access | Reset | Description
1309  * :--------|:-------|:------|:-----------------------------
1310  * [9:0] | RW | 0x0 | ALT_ECC_SDMMC_SERRADDRB_ADDR
1311  * [31:10] | ??? | 0x0 | *UNDEFINED*
1312  *
1313  */
1314 /*
1315  * Field : Address
1316  *
1317  * Recent single-bit error address.
1318  *
1319  * Field Access Macros:
1320  *
1321  */
1322 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRADDRB_ADDR register field. */
1323 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_LSB 0
1324 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRADDRB_ADDR register field. */
1325 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_MSB 9
1326 /* The width in bits of the ALT_ECC_SDMMC_SERRADDRB_ADDR register field. */
1327 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_WIDTH 10
1328 /* The mask used to set the ALT_ECC_SDMMC_SERRADDRB_ADDR register field value. */
1329 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET_MSK 0x000003ff
1330 /* The mask used to clear the ALT_ECC_SDMMC_SERRADDRB_ADDR register field value. */
1331 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_CLR_MSK 0xfffffc00
1332 /* The reset value of the ALT_ECC_SDMMC_SERRADDRB_ADDR register field. */
1333 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_RESET 0x0
1334 /* Extracts the ALT_ECC_SDMMC_SERRADDRB_ADDR field value from a register. */
1335 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1336 /* Produces a ALT_ECC_SDMMC_SERRADDRB_ADDR register field value suitable for setting the register. */
1337 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1338 
1339 #ifndef __ASSEMBLY__
1340 /*
1341  * WARNING: The C register and register group struct declarations are provided for
1342  * convenience and illustrative purposes. They should, however, be used with
1343  * caution as the C language standard provides no guarantees about the alignment or
1344  * atomicity of device memory accesses. The recommended practice for writing
1345  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1346  * alt_write_word() functions.
1347  *
1348  * The struct declaration for register ALT_ECC_SDMMC_SERRADDRB.
1349  */
1350 struct ALT_ECC_SDMMC_SERRADDRB_s
1351 {
1352  uint32_t Address : 10; /* ALT_ECC_SDMMC_SERRADDRB_ADDR */
1353  uint32_t : 22; /* *UNDEFINED* */
1354 };
1355 
1356 /* The typedef declaration for register ALT_ECC_SDMMC_SERRADDRB. */
1357 typedef volatile struct ALT_ECC_SDMMC_SERRADDRB_s ALT_ECC_SDMMC_SERRADDRB_t;
1358 #endif /* __ASSEMBLY__ */
1359 
1360 /* The reset value of the ALT_ECC_SDMMC_SERRADDRB register. */
1361 #define ALT_ECC_SDMMC_SERRADDRB_RESET 0x00000000
1362 /* The byte offset of the ALT_ECC_SDMMC_SERRADDRB register from the beginning of the component. */
1363 #define ALT_ECC_SDMMC_SERRADDRB_OFST 0x38
1364 
1365 /*
1366  * Register : SERRCNTREG
1367  *
1368  * Maximum counter value for single-bit error interrupt
1369  *
1370  * Register Layout
1371  *
1372  * Bits | Access | Reset | Description
1373  * :-------|:-------|:------|:---------------------------------
1374  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_SERRCNTREG_SERRCNT
1375  *
1376  */
1377 /*
1378  * Field : SERRCNT
1379  *
1380  * Counter value
1381  *
1382  * Field Access Macros:
1383  *
1384  */
1385 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field. */
1386 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_LSB 0
1387 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field. */
1388 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_MSB 31
1389 /* The width in bits of the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field. */
1390 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_WIDTH 32
1391 /* The mask used to set the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field value. */
1392 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1393 /* The mask used to clear the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field value. */
1394 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1395 /* The reset value of the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field. */
1396 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_RESET 0x0
1397 /* Extracts the ALT_ECC_SDMMC_SERRCNTREG_SERRCNT field value from a register. */
1398 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1399 /* Produces a ALT_ECC_SDMMC_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
1400 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1401 
1402 #ifndef __ASSEMBLY__
1403 /*
1404  * WARNING: The C register and register group struct declarations are provided for
1405  * convenience and illustrative purposes. They should, however, be used with
1406  * caution as the C language standard provides no guarantees about the alignment or
1407  * atomicity of device memory accesses. The recommended practice for writing
1408  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1409  * alt_write_word() functions.
1410  *
1411  * The struct declaration for register ALT_ECC_SDMMC_SERRCNTREG.
1412  */
1413 struct ALT_ECC_SDMMC_SERRCNTREG_s
1414 {
1415  uint32_t SERRCNT : 32; /* ALT_ECC_SDMMC_SERRCNTREG_SERRCNT */
1416 };
1417 
1418 /* The typedef declaration for register ALT_ECC_SDMMC_SERRCNTREG. */
1419 typedef volatile struct ALT_ECC_SDMMC_SERRCNTREG_s ALT_ECC_SDMMC_SERRCNTREG_t;
1420 #endif /* __ASSEMBLY__ */
1421 
1422 /* The reset value of the ALT_ECC_SDMMC_SERRCNTREG register. */
1423 #define ALT_ECC_SDMMC_SERRCNTREG_RESET 0x00000000
1424 /* The byte offset of the ALT_ECC_SDMMC_SERRCNTREG register from the beginning of the component. */
1425 #define ALT_ECC_SDMMC_SERRCNTREG_OFST 0x3c
1426 
1427 /*
1428  * Register : ECC_Addrbus
1429  *
1430  * MSB bit of address is determined by ADR.
1431  *
1432  * Register Layout
1433  *
1434  * Bits | Access | Reset | Description
1435  * :--------|:-------|:------|:----------------------------------
1436  * [9:0] | RW | 0x0 | ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS
1437  * [31:10] | ??? | 0x0 | *UNDEFINED*
1438  *
1439  */
1440 /*
1441  * Field : ECC_AddrBUS
1442  *
1443  * Address will be driven to RAM to either read or write the data. Address will be
1444  * latched by the RAM when the Enbus is asserted.
1445  *
1446  * Field Access Macros:
1447  *
1448  */
1449 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field. */
1450 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_LSB 0
1451 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field. */
1452 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_MSB 9
1453 /* The width in bits of the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field. */
1454 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1455 /* The mask used to set the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field value. */
1456 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1457 /* The mask used to clear the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field value. */
1458 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1459 /* The reset value of the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field. */
1460 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1461 /* Extracts the ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS field value from a register. */
1462 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1463 /* Produces a ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS register field value suitable for setting the register. */
1464 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1465 
1466 #ifndef __ASSEMBLY__
1467 /*
1468  * WARNING: The C register and register group struct declarations are provided for
1469  * convenience and illustrative purposes. They should, however, be used with
1470  * caution as the C language standard provides no guarantees about the alignment or
1471  * atomicity of device memory accesses. The recommended practice for writing
1472  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1473  * alt_write_word() functions.
1474  *
1475  * The struct declaration for register ALT_ECC_SDMMC_ADDRBUS.
1476  */
1477 struct ALT_ECC_SDMMC_ADDRBUS_s
1478 {
1479  uint32_t ECC_AddrBUS : 10; /* ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS */
1480  uint32_t : 22; /* *UNDEFINED* */
1481 };
1482 
1483 /* The typedef declaration for register ALT_ECC_SDMMC_ADDRBUS. */
1484 typedef volatile struct ALT_ECC_SDMMC_ADDRBUS_s ALT_ECC_SDMMC_ADDRBUS_t;
1485 #endif /* __ASSEMBLY__ */
1486 
1487 /* The reset value of the ALT_ECC_SDMMC_ADDRBUS register. */
1488 #define ALT_ECC_SDMMC_ADDRBUS_RESET 0x00000000
1489 /* The byte offset of the ALT_ECC_SDMMC_ADDRBUS register from the beginning of the component. */
1490 #define ALT_ECC_SDMMC_ADDRBUS_OFST 0x40
1491 /* The address of the ALT_ECC_SDMMC_ADDRBUS register. */
1492 #define ALT_ECC_SDMMC_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ADDRBUS_OFST))
1493 
1494 /*
1495  * Register : ECC_RData0bus
1496  *
1497  * Data will be read to this register field.
1498  *
1499  * Register Layout
1500  *
1501  * Bits | Access | Reset | Description
1502  * :-------|:-------|:------|:-------------------------------------
1503  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS
1504  *
1505  */
1506 /*
1507  * Field : ECC_RDataBUS
1508  *
1509  * ECC_RDataBUS[31:0].
1510  *
1511  * Field Access Macros:
1512  *
1513  */
1514 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field. */
1515 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_LSB 0
1516 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field. */
1517 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_MSB 31
1518 /* The width in bits of the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field. */
1519 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1520 /* The mask used to set the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field value. */
1521 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1522 /* The mask used to clear the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field value. */
1523 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1524 /* The reset value of the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field. */
1525 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1526 /* Extracts the ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS field value from a register. */
1527 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1528 /* Produces a ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS register field value suitable for setting the register. */
1529 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1530 
1531 #ifndef __ASSEMBLY__
1532 /*
1533  * WARNING: The C register and register group struct declarations are provided for
1534  * convenience and illustrative purposes. They should, however, be used with
1535  * caution as the C language standard provides no guarantees about the alignment or
1536  * atomicity of device memory accesses. The recommended practice for writing
1537  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1538  * alt_write_word() functions.
1539  *
1540  * The struct declaration for register ALT_ECC_SDMMC_RDATA0BUS.
1541  */
1542 struct ALT_ECC_SDMMC_RDATA0BUS_s
1543 {
1544  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS */
1545 };
1546 
1547 /* The typedef declaration for register ALT_ECC_SDMMC_RDATA0BUS. */
1548 typedef volatile struct ALT_ECC_SDMMC_RDATA0BUS_s ALT_ECC_SDMMC_RDATA0BUS_t;
1549 #endif /* __ASSEMBLY__ */
1550 
1551 /* The reset value of the ALT_ECC_SDMMC_RDATA0BUS register. */
1552 #define ALT_ECC_SDMMC_RDATA0BUS_RESET 0x00000000
1553 /* The byte offset of the ALT_ECC_SDMMC_RDATA0BUS register from the beginning of the component. */
1554 #define ALT_ECC_SDMMC_RDATA0BUS_OFST 0x44
1555 /* The address of the ALT_ECC_SDMMC_RDATA0BUS register. */
1556 #define ALT_ECC_SDMMC_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA0BUS_OFST))
1557 
1558 /*
1559  * Register : ECC_RData1bus
1560  *
1561  * Data will be read to this register field.
1562  *
1563  * Register Layout
1564  *
1565  * Bits | Access | Reset | Description
1566  * :-------|:-------|:------|:-------------------------------------
1567  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS
1568  *
1569  */
1570 /*
1571  * Field : ECC_RDataBUS
1572  *
1573  * ECC_RDataBUS[63:32].
1574  *
1575  * Field Access Macros:
1576  *
1577  */
1578 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field. */
1579 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_LSB 0
1580 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field. */
1581 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_MSB 31
1582 /* The width in bits of the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field. */
1583 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1584 /* The mask used to set the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field value. */
1585 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1586 /* The mask used to clear the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field value. */
1587 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1588 /* The reset value of the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field. */
1589 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1590 /* Extracts the ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS field value from a register. */
1591 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1592 /* Produces a ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS register field value suitable for setting the register. */
1593 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1594 
1595 #ifndef __ASSEMBLY__
1596 /*
1597  * WARNING: The C register and register group struct declarations are provided for
1598  * convenience and illustrative purposes. They should, however, be used with
1599  * caution as the C language standard provides no guarantees about the alignment or
1600  * atomicity of device memory accesses. The recommended practice for writing
1601  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1602  * alt_write_word() functions.
1603  *
1604  * The struct declaration for register ALT_ECC_SDMMC_RDATA1BUS.
1605  */
1606 struct ALT_ECC_SDMMC_RDATA1BUS_s
1607 {
1608  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS */
1609 };
1610 
1611 /* The typedef declaration for register ALT_ECC_SDMMC_RDATA1BUS. */
1612 typedef volatile struct ALT_ECC_SDMMC_RDATA1BUS_s ALT_ECC_SDMMC_RDATA1BUS_t;
1613 #endif /* __ASSEMBLY__ */
1614 
1615 /* The reset value of the ALT_ECC_SDMMC_RDATA1BUS register. */
1616 #define ALT_ECC_SDMMC_RDATA1BUS_RESET 0x00000000
1617 /* The byte offset of the ALT_ECC_SDMMC_RDATA1BUS register from the beginning of the component. */
1618 #define ALT_ECC_SDMMC_RDATA1BUS_OFST 0x48
1619 /* The address of the ALT_ECC_SDMMC_RDATA1BUS register. */
1620 #define ALT_ECC_SDMMC_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA1BUS_OFST))
1621 
1622 /*
1623  * Register : ECC_RData2bus
1624  *
1625  * Data will be read to this register field.
1626  *
1627  * Register Layout
1628  *
1629  * Bits | Access | Reset | Description
1630  * :-------|:-------|:------|:-------------------------------------
1631  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS
1632  *
1633  */
1634 /*
1635  * Field : ECC_RDataBUS
1636  *
1637  * ECC_RDataBUS[95:64].
1638  *
1639  * Field Access Macros:
1640  *
1641  */
1642 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field. */
1643 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_LSB 0
1644 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field. */
1645 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_MSB 31
1646 /* The width in bits of the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field. */
1647 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1648 /* The mask used to set the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field value. */
1649 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1650 /* The mask used to clear the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field value. */
1651 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1652 /* The reset value of the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field. */
1653 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1654 /* Extracts the ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS field value from a register. */
1655 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1656 /* Produces a ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS register field value suitable for setting the register. */
1657 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1658 
1659 #ifndef __ASSEMBLY__
1660 /*
1661  * WARNING: The C register and register group struct declarations are provided for
1662  * convenience and illustrative purposes. They should, however, be used with
1663  * caution as the C language standard provides no guarantees about the alignment or
1664  * atomicity of device memory accesses. The recommended practice for writing
1665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1666  * alt_write_word() functions.
1667  *
1668  * The struct declaration for register ALT_ECC_SDMMC_RDATA2BUS.
1669  */
1670 struct ALT_ECC_SDMMC_RDATA2BUS_s
1671 {
1672  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS */
1673 };
1674 
1675 /* The typedef declaration for register ALT_ECC_SDMMC_RDATA2BUS. */
1676 typedef volatile struct ALT_ECC_SDMMC_RDATA2BUS_s ALT_ECC_SDMMC_RDATA2BUS_t;
1677 #endif /* __ASSEMBLY__ */
1678 
1679 /* The reset value of the ALT_ECC_SDMMC_RDATA2BUS register. */
1680 #define ALT_ECC_SDMMC_RDATA2BUS_RESET 0x00000000
1681 /* The byte offset of the ALT_ECC_SDMMC_RDATA2BUS register from the beginning of the component. */
1682 #define ALT_ECC_SDMMC_RDATA2BUS_OFST 0x4c
1683 /* The address of the ALT_ECC_SDMMC_RDATA2BUS register. */
1684 #define ALT_ECC_SDMMC_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA2BUS_OFST))
1685 
1686 /*
1687  * Register : ECC_RData3bus
1688  *
1689  * Data will be read to this register field.
1690  *
1691  * Register Layout
1692  *
1693  * Bits | Access | Reset | Description
1694  * :-------|:-------|:------|:-------------------------------------
1695  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS
1696  *
1697  */
1698 /*
1699  * Field : ECC_RDataBUS
1700  *
1701  * ECC_RDataBUS[127-96].
1702  *
1703  * Field Access Macros:
1704  *
1705  */
1706 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field. */
1707 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_LSB 0
1708 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field. */
1709 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_MSB 31
1710 /* The width in bits of the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field. */
1711 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1712 /* The mask used to set the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field value. */
1713 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1714 /* The mask used to clear the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field value. */
1715 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1716 /* The reset value of the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field. */
1717 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1718 /* Extracts the ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS field value from a register. */
1719 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1720 /* Produces a ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS register field value suitable for setting the register. */
1721 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1722 
1723 #ifndef __ASSEMBLY__
1724 /*
1725  * WARNING: The C register and register group struct declarations are provided for
1726  * convenience and illustrative purposes. They should, however, be used with
1727  * caution as the C language standard provides no guarantees about the alignment or
1728  * atomicity of device memory accesses. The recommended practice for writing
1729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1730  * alt_write_word() functions.
1731  *
1732  * The struct declaration for register ALT_ECC_SDMMC_RDATA3BUS.
1733  */
1734 struct ALT_ECC_SDMMC_RDATA3BUS_s
1735 {
1736  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS */
1737 };
1738 
1739 /* The typedef declaration for register ALT_ECC_SDMMC_RDATA3BUS. */
1740 typedef volatile struct ALT_ECC_SDMMC_RDATA3BUS_s ALT_ECC_SDMMC_RDATA3BUS_t;
1741 #endif /* __ASSEMBLY__ */
1742 
1743 /* The reset value of the ALT_ECC_SDMMC_RDATA3BUS register. */
1744 #define ALT_ECC_SDMMC_RDATA3BUS_RESET 0x00000000
1745 /* The byte offset of the ALT_ECC_SDMMC_RDATA3BUS register from the beginning of the component. */
1746 #define ALT_ECC_SDMMC_RDATA3BUS_OFST 0x50
1747 /* The address of the ALT_ECC_SDMMC_RDATA3BUS register. */
1748 #define ALT_ECC_SDMMC_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA3BUS_OFST))
1749 
1750 /*
1751  * Register : ECC_WData0bus
1752  *
1753  * Data from the register will be written to the RAM.
1754  *
1755  * Register Layout
1756  *
1757  * Bits | Access | Reset | Description
1758  * :-------|:-------|:------|:-------------------------------------
1759  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS
1760  *
1761  */
1762 /*
1763  * Field : ECC_WDataBUS
1764  *
1765  * ECC_WDataBUS[31:0].
1766  *
1767  * Field Access Macros:
1768  *
1769  */
1770 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field. */
1771 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_LSB 0
1772 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field. */
1773 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_MSB 31
1774 /* The width in bits of the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field. */
1775 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1776 /* The mask used to set the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field value. */
1777 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1778 /* The mask used to clear the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field value. */
1779 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1780 /* The reset value of the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field. */
1781 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1782 /* Extracts the ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS field value from a register. */
1783 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1784 /* Produces a ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS register field value suitable for setting the register. */
1785 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1786 
1787 #ifndef __ASSEMBLY__
1788 /*
1789  * WARNING: The C register and register group struct declarations are provided for
1790  * convenience and illustrative purposes. They should, however, be used with
1791  * caution as the C language standard provides no guarantees about the alignment or
1792  * atomicity of device memory accesses. The recommended practice for writing
1793  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1794  * alt_write_word() functions.
1795  *
1796  * The struct declaration for register ALT_ECC_SDMMC_WDATA0BUS.
1797  */
1798 struct ALT_ECC_SDMMC_WDATA0BUS_s
1799 {
1800  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS */
1801 };
1802 
1803 /* The typedef declaration for register ALT_ECC_SDMMC_WDATA0BUS. */
1804 typedef volatile struct ALT_ECC_SDMMC_WDATA0BUS_s ALT_ECC_SDMMC_WDATA0BUS_t;
1805 #endif /* __ASSEMBLY__ */
1806 
1807 /* The reset value of the ALT_ECC_SDMMC_WDATA0BUS register. */
1808 #define ALT_ECC_SDMMC_WDATA0BUS_RESET 0x00000000
1809 /* The byte offset of the ALT_ECC_SDMMC_WDATA0BUS register from the beginning of the component. */
1810 #define ALT_ECC_SDMMC_WDATA0BUS_OFST 0x54
1811 /* The address of the ALT_ECC_SDMMC_WDATA0BUS register. */
1812 #define ALT_ECC_SDMMC_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA0BUS_OFST))
1813 
1814 /*
1815  * Register : ECC_WData1bus
1816  *
1817  * Data from the register will be written to the RAM.
1818  *
1819  * Register Layout
1820  *
1821  * Bits | Access | Reset | Description
1822  * :-------|:-------|:------|:-------------------------------------
1823  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS
1824  *
1825  */
1826 /*
1827  * Field : ECC_WDataBUS
1828  *
1829  * ECC_WDataBUS[63:32].
1830  *
1831  * Field Access Macros:
1832  *
1833  */
1834 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field. */
1835 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_LSB 0
1836 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field. */
1837 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_MSB 31
1838 /* The width in bits of the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field. */
1839 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1840 /* The mask used to set the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field value. */
1841 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1842 /* The mask used to clear the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field value. */
1843 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1844 /* The reset value of the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field. */
1845 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1846 /* Extracts the ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS field value from a register. */
1847 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1848 /* Produces a ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS register field value suitable for setting the register. */
1849 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1850 
1851 #ifndef __ASSEMBLY__
1852 /*
1853  * WARNING: The C register and register group struct declarations are provided for
1854  * convenience and illustrative purposes. They should, however, be used with
1855  * caution as the C language standard provides no guarantees about the alignment or
1856  * atomicity of device memory accesses. The recommended practice for writing
1857  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1858  * alt_write_word() functions.
1859  *
1860  * The struct declaration for register ALT_ECC_SDMMC_WDATA1BUS.
1861  */
1862 struct ALT_ECC_SDMMC_WDATA1BUS_s
1863 {
1864  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS */
1865 };
1866 
1867 /* The typedef declaration for register ALT_ECC_SDMMC_WDATA1BUS. */
1868 typedef volatile struct ALT_ECC_SDMMC_WDATA1BUS_s ALT_ECC_SDMMC_WDATA1BUS_t;
1869 #endif /* __ASSEMBLY__ */
1870 
1871 /* The reset value of the ALT_ECC_SDMMC_WDATA1BUS register. */
1872 #define ALT_ECC_SDMMC_WDATA1BUS_RESET 0x00000000
1873 /* The byte offset of the ALT_ECC_SDMMC_WDATA1BUS register from the beginning of the component. */
1874 #define ALT_ECC_SDMMC_WDATA1BUS_OFST 0x58
1875 /* The address of the ALT_ECC_SDMMC_WDATA1BUS register. */
1876 #define ALT_ECC_SDMMC_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA1BUS_OFST))
1877 
1878 /*
1879  * Register : ECC_WData2bus
1880  *
1881  * Data from the register will be written to the RAM.
1882  *
1883  * Register Layout
1884  *
1885  * Bits | Access | Reset | Description
1886  * :-------|:-------|:------|:-------------------------------------
1887  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS
1888  *
1889  */
1890 /*
1891  * Field : ECC_WDataBUS
1892  *
1893  * ECC_WDataBUS[95-64].
1894  *
1895  * Field Access Macros:
1896  *
1897  */
1898 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field. */
1899 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_LSB 0
1900 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field. */
1901 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_MSB 31
1902 /* The width in bits of the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field. */
1903 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1904 /* The mask used to set the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field value. */
1905 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1906 /* The mask used to clear the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field value. */
1907 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1908 /* The reset value of the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field. */
1909 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1910 /* Extracts the ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS field value from a register. */
1911 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1912 /* Produces a ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS register field value suitable for setting the register. */
1913 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1914 
1915 #ifndef __ASSEMBLY__
1916 /*
1917  * WARNING: The C register and register group struct declarations are provided for
1918  * convenience and illustrative purposes. They should, however, be used with
1919  * caution as the C language standard provides no guarantees about the alignment or
1920  * atomicity of device memory accesses. The recommended practice for writing
1921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1922  * alt_write_word() functions.
1923  *
1924  * The struct declaration for register ALT_ECC_SDMMC_WDATA2BUS.
1925  */
1926 struct ALT_ECC_SDMMC_WDATA2BUS_s
1927 {
1928  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS */
1929 };
1930 
1931 /* The typedef declaration for register ALT_ECC_SDMMC_WDATA2BUS. */
1932 typedef volatile struct ALT_ECC_SDMMC_WDATA2BUS_s ALT_ECC_SDMMC_WDATA2BUS_t;
1933 #endif /* __ASSEMBLY__ */
1934 
1935 /* The reset value of the ALT_ECC_SDMMC_WDATA2BUS register. */
1936 #define ALT_ECC_SDMMC_WDATA2BUS_RESET 0x00000000
1937 /* The byte offset of the ALT_ECC_SDMMC_WDATA2BUS register from the beginning of the component. */
1938 #define ALT_ECC_SDMMC_WDATA2BUS_OFST 0x5c
1939 /* The address of the ALT_ECC_SDMMC_WDATA2BUS register. */
1940 #define ALT_ECC_SDMMC_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA2BUS_OFST))
1941 
1942 /*
1943  * Register : ECC_WData3bus
1944  *
1945  * Data from the register will be written to the RAM.
1946  *
1947  * Register Layout
1948  *
1949  * Bits | Access | Reset | Description
1950  * :-------|:-------|:------|:-------------------------------------
1951  * [31:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS
1952  *
1953  */
1954 /*
1955  * Field : ECC_WDataBUS
1956  *
1957  * ECC_WDataBUS[127-96].
1958  *
1959  * Field Access Macros:
1960  *
1961  */
1962 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field. */
1963 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_LSB 0
1964 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field. */
1965 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_MSB 31
1966 /* The width in bits of the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field. */
1967 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1968 /* The mask used to set the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field value. */
1969 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1970 /* The mask used to clear the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field value. */
1971 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1972 /* The reset value of the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field. */
1973 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1974 /* Extracts the ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS field value from a register. */
1975 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1976 /* Produces a ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS register field value suitable for setting the register. */
1977 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1978 
1979 #ifndef __ASSEMBLY__
1980 /*
1981  * WARNING: The C register and register group struct declarations are provided for
1982  * convenience and illustrative purposes. They should, however, be used with
1983  * caution as the C language standard provides no guarantees about the alignment or
1984  * atomicity of device memory accesses. The recommended practice for writing
1985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1986  * alt_write_word() functions.
1987  *
1988  * The struct declaration for register ALT_ECC_SDMMC_WDATA3BUS.
1989  */
1990 struct ALT_ECC_SDMMC_WDATA3BUS_s
1991 {
1992  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS */
1993 };
1994 
1995 /* The typedef declaration for register ALT_ECC_SDMMC_WDATA3BUS. */
1996 typedef volatile struct ALT_ECC_SDMMC_WDATA3BUS_s ALT_ECC_SDMMC_WDATA3BUS_t;
1997 #endif /* __ASSEMBLY__ */
1998 
1999 /* The reset value of the ALT_ECC_SDMMC_WDATA3BUS register. */
2000 #define ALT_ECC_SDMMC_WDATA3BUS_RESET 0x00000000
2001 /* The byte offset of the ALT_ECC_SDMMC_WDATA3BUS register from the beginning of the component. */
2002 #define ALT_ECC_SDMMC_WDATA3BUS_OFST 0x60
2003 /* The address of the ALT_ECC_SDMMC_WDATA3BUS register. */
2004 #define ALT_ECC_SDMMC_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA3BUS_OFST))
2005 
2006 /*
2007  * Register : ECC_RDataecc0bus
2008  *
2009  * The msb bit for the register is configured based on DAT parameter (RAM word
2010  * size). Unimplemented bytes of this register will be reserved.
2011  *
2012  * Register Layout
2013  *
2014  * Bits | Access | Reset | Description
2015  * :--------|:-------|:------|:--------------------------------------------
2016  * [6:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS
2017  * [7] | ??? | 0x0 | *UNDEFINED*
2018  * [14:8] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS
2019  * [15] | ??? | 0x0 | *UNDEFINED*
2020  * [22:16] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS
2021  * [23] | ??? | 0x0 | *UNDEFINED*
2022  * [30:24] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS
2023  * [31] | ??? | 0x0 | *UNDEFINED*
2024  *
2025  */
2026 /*
2027  * Field : ECC_RDataecc0BUS
2028  *
2029  * Eccdata will be read to this register field.
2030  *
2031  * Field Access Macros:
2032  *
2033  */
2034 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2035 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
2036 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2037 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
2038 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2039 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
2040 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
2041 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
2042 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
2043 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
2044 /* The reset value of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
2045 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
2046 /* Extracts the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register. */
2047 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2048 /* Produces a ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register. */
2049 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2050 
2051 /*
2052  * Field : ECC_RDataecc1BUS
2053  *
2054  * Eccdata will be read to this register field.
2055  *
2056  * Field Access Macros:
2057  *
2058  */
2059 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2060 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
2061 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2062 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
2063 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2064 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
2065 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
2066 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
2067 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
2068 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
2069 /* The reset value of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
2070 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
2071 /* Extracts the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register. */
2072 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2073 /* Produces a ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register. */
2074 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2075 
2076 /*
2077  * Field : ECC_RDataecc2BUS
2078  *
2079  * Eccdata will be read to this register field.
2080  *
2081  * Field Access Macros:
2082  *
2083  */
2084 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2085 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
2086 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2087 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
2088 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2089 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
2090 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
2091 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
2092 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
2093 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
2094 /* The reset value of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
2095 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
2096 /* Extracts the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register. */
2097 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2098 /* Produces a ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register. */
2099 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2100 
2101 /*
2102  * Field : ECC_RDataecc3BUS
2103  *
2104  * Eccdata will be read to this register field.
2105  *
2106  * Field Access Macros:
2107  *
2108  */
2109 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2110 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
2111 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2112 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
2113 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2114 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
2115 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
2116 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
2117 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
2118 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
2119 /* The reset value of the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
2120 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
2121 /* Extracts the ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register. */
2122 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2123 /* Produces a ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register. */
2124 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2125 
2126 #ifndef __ASSEMBLY__
2127 /*
2128  * WARNING: The C register and register group struct declarations are provided for
2129  * convenience and illustrative purposes. They should, however, be used with
2130  * caution as the C language standard provides no guarantees about the alignment or
2131  * atomicity of device memory accesses. The recommended practice for writing
2132  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2133  * alt_write_word() functions.
2134  *
2135  * The struct declaration for register ALT_ECC_SDMMC_RDATAECC0BUS.
2136  */
2137 struct ALT_ECC_SDMMC_RDATAECC0BUS_s
2138 {
2139  uint32_t ECC_RDataecc0BUS : 7; /* ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS */
2140  uint32_t : 1; /* *UNDEFINED* */
2141  uint32_t ECC_RDataecc1BUS : 7; /* ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS */
2142  uint32_t : 1; /* *UNDEFINED* */
2143  uint32_t ECC_RDataecc2BUS : 7; /* ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS */
2144  uint32_t : 1; /* *UNDEFINED* */
2145  uint32_t ECC_RDataecc3BUS : 7; /* ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS */
2146  uint32_t : 1; /* *UNDEFINED* */
2147 };
2148 
2149 /* The typedef declaration for register ALT_ECC_SDMMC_RDATAECC0BUS. */
2150 typedef volatile struct ALT_ECC_SDMMC_RDATAECC0BUS_s ALT_ECC_SDMMC_RDATAECC0BUS_t;
2151 #endif /* __ASSEMBLY__ */
2152 
2153 /* The reset value of the ALT_ECC_SDMMC_RDATAECC0BUS register. */
2154 #define ALT_ECC_SDMMC_RDATAECC0BUS_RESET 0x00000000
2155 /* The byte offset of the ALT_ECC_SDMMC_RDATAECC0BUS register from the beginning of the component. */
2156 #define ALT_ECC_SDMMC_RDATAECC0BUS_OFST 0x64
2157 /* The address of the ALT_ECC_SDMMC_RDATAECC0BUS register. */
2158 #define ALT_ECC_SDMMC_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC0BUS_OFST))
2159 
2160 /*
2161  * Register : ECC_RDataecc1bus
2162  *
2163  * The msb bit for the register is configured based on DAT parameter (RAM word
2164  * size). Unimplemented bytes of this register will be reserved.
2165  *
2166  * Register Layout
2167  *
2168  * Bits | Access | Reset | Description
2169  * :--------|:-------|:------|:--------------------------------------------
2170  * [6:0] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS
2171  * [7] | ??? | 0x0 | *UNDEFINED*
2172  * [14:8] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS
2173  * [15] | ??? | 0x0 | *UNDEFINED*
2174  * [22:16] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS
2175  * [23] | ??? | 0x0 | *UNDEFINED*
2176  * [30:24] | RW | 0x0 | ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS
2177  * [31] | ??? | 0x0 | *UNDEFINED*
2178  *
2179  */
2180 /*
2181  * Field : ECC_RDataecc4BUS
2182  *
2183  * Eccdata will be read to this register field.
2184  *
2185  * Field Access Macros:
2186  *
2187  */
2188 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2189 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
2190 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2191 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
2192 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2193 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
2194 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
2195 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
2196 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
2197 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
2198 /* The reset value of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
2199 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
2200 /* Extracts the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS field value from a register. */
2201 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2202 /* Produces a ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value suitable for setting the register. */
2203 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2204 
2205 /*
2206  * Field : ECC_RDataecc5BUS
2207  *
2208  * Eccdata will be read to this register field.
2209  *
2210  * Field Access Macros:
2211  *
2212  */
2213 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2214 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
2215 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2216 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
2217 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2218 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
2219 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
2220 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
2221 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
2222 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
2223 /* The reset value of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
2224 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
2225 /* Extracts the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS field value from a register. */
2226 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2227 /* Produces a ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value suitable for setting the register. */
2228 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2229 
2230 /*
2231  * Field : ECC_RDataecc6BUS
2232  *
2233  * Eccdata will be read to this register field.
2234  *
2235  * Field Access Macros:
2236  *
2237  */
2238 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2239 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
2240 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2241 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
2242 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2243 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
2244 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
2245 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
2246 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
2247 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
2248 /* The reset value of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
2249 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
2250 /* Extracts the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS field value from a register. */
2251 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2252 /* Produces a ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value suitable for setting the register. */
2253 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2254 
2255 /*
2256  * Field : ECC_RDataecc7BUS
2257  *
2258  * Eccdata will be read to this register field.
2259  *
2260  * Field Access Macros:
2261  *
2262  */
2263 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2264 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
2265 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2266 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
2267 /* The width in bits of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2268 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
2269 /* The mask used to set the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
2270 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
2271 /* The mask used to clear the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
2272 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
2273 /* The reset value of the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
2274 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
2275 /* Extracts the ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS field value from a register. */
2276 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2277 /* Produces a ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value suitable for setting the register. */
2278 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2279 
2280 #ifndef __ASSEMBLY__
2281 /*
2282  * WARNING: The C register and register group struct declarations are provided for
2283  * convenience and illustrative purposes. They should, however, be used with
2284  * caution as the C language standard provides no guarantees about the alignment or
2285  * atomicity of device memory accesses. The recommended practice for writing
2286  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2287  * alt_write_word() functions.
2288  *
2289  * The struct declaration for register ALT_ECC_SDMMC_RDATAECC1BUS.
2290  */
2291 struct ALT_ECC_SDMMC_RDATAECC1BUS_s
2292 {
2293  uint32_t ECC_RDataecc4BUS : 7; /* ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS */
2294  uint32_t : 1; /* *UNDEFINED* */
2295  uint32_t ECC_RDataecc5BUS : 7; /* ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS */
2296  uint32_t : 1; /* *UNDEFINED* */
2297  uint32_t ECC_RDataecc6BUS : 7; /* ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS */
2298  uint32_t : 1; /* *UNDEFINED* */
2299  uint32_t ECC_RDataecc7BUS : 7; /* ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS */
2300  uint32_t : 1; /* *UNDEFINED* */
2301 };
2302 
2303 /* The typedef declaration for register ALT_ECC_SDMMC_RDATAECC1BUS. */
2304 typedef volatile struct ALT_ECC_SDMMC_RDATAECC1BUS_s ALT_ECC_SDMMC_RDATAECC1BUS_t;
2305 #endif /* __ASSEMBLY__ */
2306 
2307 /* The reset value of the ALT_ECC_SDMMC_RDATAECC1BUS register. */
2308 #define ALT_ECC_SDMMC_RDATAECC1BUS_RESET 0x00000000
2309 /* The byte offset of the ALT_ECC_SDMMC_RDATAECC1BUS register from the beginning of the component. */
2310 #define ALT_ECC_SDMMC_RDATAECC1BUS_OFST 0x68
2311 /* The address of the ALT_ECC_SDMMC_RDATAECC1BUS register. */
2312 #define ALT_ECC_SDMMC_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC1BUS_OFST))
2313 
2314 /*
2315  * Register : ECC_WDataecc0bus
2316  *
2317  * The msb bit for the register is configured based on DAT parameter (RAM word
2318  * size). Unimplemented bytes of this register will be reserved.
2319  *
2320  * Register Layout
2321  *
2322  * Bits | Access | Reset | Description
2323  * :--------|:-------|:------|:--------------------------------------------
2324  * [6:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS
2325  * [7] | ??? | 0x0 | *UNDEFINED*
2326  * [14:8] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS
2327  * [15] | ??? | 0x0 | *UNDEFINED*
2328  * [22:16] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS
2329  * [23] | ??? | 0x0 | *UNDEFINED*
2330  * [30:24] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS
2331  * [31] | ??? | 0x0 | *UNDEFINED*
2332  *
2333  */
2334 /*
2335  * Field : ECC_WDataecc0BUS
2336  *
2337  * Eccdata from the register will be written to the RAM.
2338  *
2339  * Field Access Macros:
2340  *
2341  */
2342 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2343 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
2344 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2345 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
2346 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2347 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
2348 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2349 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
2350 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2351 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
2352 /* The reset value of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2353 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2354 /* Extracts the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register. */
2355 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2356 /* Produces a ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register. */
2357 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2358 
2359 /*
2360  * Field : ECC_WDataecc1BUS
2361  *
2362  * Eccdata from the register will be written to the RAM.
2363  *
2364  * Field Access Macros:
2365  *
2366  */
2367 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2368 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2369 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2370 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2371 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2372 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2373 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2374 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2375 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2376 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2377 /* The reset value of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2378 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2379 /* Extracts the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register. */
2380 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2381 /* Produces a ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register. */
2382 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2383 
2384 /*
2385  * Field : ECC_WDataecc2BUS
2386  *
2387  * Eccdata from the register will be written to the RAM.
2388  *
2389  * Field Access Macros:
2390  *
2391  */
2392 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2393 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2394 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2395 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2396 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2397 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2398 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2399 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2400 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2401 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2402 /* The reset value of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2403 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2404 /* Extracts the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register. */
2405 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2406 /* Produces a ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register. */
2407 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2408 
2409 /*
2410  * Field : ECC_WDataecc3BUS
2411  *
2412  * Eccdata from the register will be written to the RAM.
2413  *
2414  * Field Access Macros:
2415  *
2416  */
2417 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2418 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2419 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2420 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2421 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2422 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2423 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2424 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2425 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2426 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2427 /* The reset value of the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2428 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2429 /* Extracts the ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register. */
2430 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2431 /* Produces a ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register. */
2432 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2433 
2434 #ifndef __ASSEMBLY__
2435 /*
2436  * WARNING: The C register and register group struct declarations are provided for
2437  * convenience and illustrative purposes. They should, however, be used with
2438  * caution as the C language standard provides no guarantees about the alignment or
2439  * atomicity of device memory accesses. The recommended practice for writing
2440  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2441  * alt_write_word() functions.
2442  *
2443  * The struct declaration for register ALT_ECC_SDMMC_WDATAECC0BUS.
2444  */
2445 struct ALT_ECC_SDMMC_WDATAECC0BUS_s
2446 {
2447  uint32_t ECC_WDataecc0BUS : 7; /* ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS */
2448  uint32_t : 1; /* *UNDEFINED* */
2449  uint32_t ECC_WDataecc1BUS : 7; /* ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS */
2450  uint32_t : 1; /* *UNDEFINED* */
2451  uint32_t ECC_WDataecc2BUS : 7; /* ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS */
2452  uint32_t : 1; /* *UNDEFINED* */
2453  uint32_t ECC_WDataecc3BUS : 7; /* ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS */
2454  uint32_t : 1; /* *UNDEFINED* */
2455 };
2456 
2457 /* The typedef declaration for register ALT_ECC_SDMMC_WDATAECC0BUS. */
2458 typedef volatile struct ALT_ECC_SDMMC_WDATAECC0BUS_s ALT_ECC_SDMMC_WDATAECC0BUS_t;
2459 #endif /* __ASSEMBLY__ */
2460 
2461 /* The reset value of the ALT_ECC_SDMMC_WDATAECC0BUS register. */
2462 #define ALT_ECC_SDMMC_WDATAECC0BUS_RESET 0x00000000
2463 /* The byte offset of the ALT_ECC_SDMMC_WDATAECC0BUS register from the beginning of the component. */
2464 #define ALT_ECC_SDMMC_WDATAECC0BUS_OFST 0x6c
2465 /* The address of the ALT_ECC_SDMMC_WDATAECC0BUS register. */
2466 #define ALT_ECC_SDMMC_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC0BUS_OFST))
2467 
2468 /*
2469  * Register : ECC_WDataecc1bus
2470  *
2471  * The msb bit for the register is configured based on DAT parameter (RAM word
2472  * size). Unimplemented bytes of this register will be reserved.
2473  *
2474  * Register Layout
2475  *
2476  * Bits | Access | Reset | Description
2477  * :--------|:-------|:------|:--------------------------------------------
2478  * [6:0] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS
2479  * [7] | ??? | 0x0 | *UNDEFINED*
2480  * [14:8] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS
2481  * [15] | ??? | 0x0 | *UNDEFINED*
2482  * [22:16] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS
2483  * [23] | ??? | 0x0 | *UNDEFINED*
2484  * [30:24] | RW | 0x0 | ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS
2485  * [31] | ??? | 0x0 | *UNDEFINED*
2486  *
2487  */
2488 /*
2489  * Field : ECC_WDataecc4BUS
2490  *
2491  * Eccdata from the register will be written to the RAM.
2492  *
2493  * Field Access Macros:
2494  *
2495  */
2496 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2497 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2498 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2499 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2500 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2501 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2502 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2503 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2504 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2505 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2506 /* The reset value of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2507 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2508 /* Extracts the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register. */
2509 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2510 /* Produces a ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register. */
2511 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2512 
2513 /*
2514  * Field : ECC_WDataecc5BUS
2515  *
2516  * Eccdata from the register will be written to the RAM.
2517  *
2518  * Field Access Macros:
2519  *
2520  */
2521 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2522 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2523 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2524 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2525 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2526 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2527 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2528 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2529 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2530 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2531 /* The reset value of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2532 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2533 /* Extracts the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register. */
2534 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2535 /* Produces a ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register. */
2536 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2537 
2538 /*
2539  * Field : ECC_WDataecc6BUS
2540  *
2541  * Eccdata from the register will be written to the RAM.
2542  *
2543  * Field Access Macros:
2544  *
2545  */
2546 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2547 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2548 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2549 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2550 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2551 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2552 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2553 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2554 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2555 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2556 /* The reset value of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2557 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2558 /* Extracts the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register. */
2559 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2560 /* Produces a ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register. */
2561 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2562 
2563 /*
2564  * Field : ECC_WDataecc7BUS
2565  *
2566  * Eccdata from the register will be written to the RAM.
2567  *
2568  * Field Access Macros:
2569  *
2570  */
2571 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2572 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2573 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2574 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2575 /* The width in bits of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2576 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2577 /* The mask used to set the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2578 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2579 /* The mask used to clear the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2580 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2581 /* The reset value of the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2582 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2583 /* Extracts the ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register. */
2584 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2585 /* Produces a ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register. */
2586 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2587 
2588 #ifndef __ASSEMBLY__
2589 /*
2590  * WARNING: The C register and register group struct declarations are provided for
2591  * convenience and illustrative purposes. They should, however, be used with
2592  * caution as the C language standard provides no guarantees about the alignment or
2593  * atomicity of device memory accesses. The recommended practice for writing
2594  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2595  * alt_write_word() functions.
2596  *
2597  * The struct declaration for register ALT_ECC_SDMMC_WDATAECC1BUS.
2598  */
2599 struct ALT_ECC_SDMMC_WDATAECC1BUS_s
2600 {
2601  uint32_t ECC_WDataecc4BUS : 7; /* ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS */
2602  uint32_t : 1; /* *UNDEFINED* */
2603  uint32_t ECC_WDataecc5BUS : 7; /* ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS */
2604  uint32_t : 1; /* *UNDEFINED* */
2605  uint32_t ECC_WDataecc6BUS : 7; /* ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS */
2606  uint32_t : 1; /* *UNDEFINED* */
2607  uint32_t ECC_WDataecc7BUS : 7; /* ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS */
2608  uint32_t : 1; /* *UNDEFINED* */
2609 };
2610 
2611 /* The typedef declaration for register ALT_ECC_SDMMC_WDATAECC1BUS. */
2612 typedef volatile struct ALT_ECC_SDMMC_WDATAECC1BUS_s ALT_ECC_SDMMC_WDATAECC1BUS_t;
2613 #endif /* __ASSEMBLY__ */
2614 
2615 /* The reset value of the ALT_ECC_SDMMC_WDATAECC1BUS register. */
2616 #define ALT_ECC_SDMMC_WDATAECC1BUS_RESET 0x00000000
2617 /* The byte offset of the ALT_ECC_SDMMC_WDATAECC1BUS register from the beginning of the component. */
2618 #define ALT_ECC_SDMMC_WDATAECC1BUS_OFST 0x70
2619 /* The address of the ALT_ECC_SDMMC_WDATAECC1BUS register. */
2620 #define ALT_ECC_SDMMC_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC1BUS_OFST))
2621 
2622 /*
2623  * Register : ECC_dbytectrl
2624  *
2625  * Max number of implemented byte enabled is DAT/8
2626  *
2627  * Register Layout
2628  *
2629  * Bits | Access | Reset | Description
2630  * :-------|:-------|:------|:----------------------------
2631  * [0] | RW | 0x0 | ALT_ECC_SDMMC_DBYTECTL_DBEN
2632  * [31:1] | ??? | 0x0 | *UNDEFINED*
2633  *
2634  */
2635 /*
2636  * Field : DBEN
2637  *
2638  * Byte or word enable for access.
2639  *
2640  * Field Access Macros:
2641  *
2642  */
2643 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_DBYTECTL_DBEN register field. */
2644 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_LSB 0
2645 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_DBYTECTL_DBEN register field. */
2646 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_MSB 0
2647 /* The width in bits of the ALT_ECC_SDMMC_DBYTECTL_DBEN register field. */
2648 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_WIDTH 1
2649 /* The mask used to set the ALT_ECC_SDMMC_DBYTECTL_DBEN register field value. */
2650 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET_MSK 0x00000001
2651 /* The mask used to clear the ALT_ECC_SDMMC_DBYTECTL_DBEN register field value. */
2652 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2653 /* The reset value of the ALT_ECC_SDMMC_DBYTECTL_DBEN register field. */
2654 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_RESET 0x0
2655 /* Extracts the ALT_ECC_SDMMC_DBYTECTL_DBEN field value from a register. */
2656 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2657 /* Produces a ALT_ECC_SDMMC_DBYTECTL_DBEN register field value suitable for setting the register. */
2658 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2659 
2660 #ifndef __ASSEMBLY__
2661 /*
2662  * WARNING: The C register and register group struct declarations are provided for
2663  * convenience and illustrative purposes. They should, however, be used with
2664  * caution as the C language standard provides no guarantees about the alignment or
2665  * atomicity of device memory accesses. The recommended practice for writing
2666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2667  * alt_write_word() functions.
2668  *
2669  * The struct declaration for register ALT_ECC_SDMMC_DBYTECTL.
2670  */
2671 struct ALT_ECC_SDMMC_DBYTECTL_s
2672 {
2673  uint32_t DBEN : 1; /* ALT_ECC_SDMMC_DBYTECTL_DBEN */
2674  uint32_t : 31; /* *UNDEFINED* */
2675 };
2676 
2677 /* The typedef declaration for register ALT_ECC_SDMMC_DBYTECTL. */
2678 typedef volatile struct ALT_ECC_SDMMC_DBYTECTL_s ALT_ECC_SDMMC_DBYTECTL_t;
2679 #endif /* __ASSEMBLY__ */
2680 
2681 /* The reset value of the ALT_ECC_SDMMC_DBYTECTL register. */
2682 #define ALT_ECC_SDMMC_DBYTECTL_RESET 0x00000000
2683 /* The byte offset of the ALT_ECC_SDMMC_DBYTECTL register from the beginning of the component. */
2684 #define ALT_ECC_SDMMC_DBYTECTL_OFST 0x74
2685 /* The address of the ALT_ECC_SDMMC_DBYTECTL register. */
2686 #define ALT_ECC_SDMMC_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_DBYTECTL_OFST))
2687 
2688 /*
2689  * Register : ECC_accctrl
2690  *
2691  * These bits determine which byte of data/ecc to write to RAM.
2692  *
2693  * Register Layout
2694  *
2695  * Bits | Access | Reset | Description
2696  * :-------|:-------|:------|:-----------------------------
2697  * [0] | RW | 0x0 | ALT_ECC_SDMMC_ACCCTL_DATAOVR
2698  * [1] | RW | 0x0 | ALT_ECC_SDMMC_ACCCTL_ECCOVR
2699  * [7:2] | ??? | 0x0 | *UNDEFINED*
2700  * [8] | RW | 0x0 | ALT_ECC_SDMMC_ACCCTL_RDWR
2701  * [31:9] | ??? | 0x0 | *UNDEFINED*
2702  *
2703  */
2704 /*
2705  * Field : DATAOVR
2706  *
2707  * RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode
2708  * set by ECC_RW.
2709  *
2710  * 1'b0: Data override disabled.
2711  *
2712  * 1'b1: Data override enabled.
2713  *
2714  * Field Access Macros:
2715  *
2716  */
2717 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field. */
2718 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_LSB 0
2719 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field. */
2720 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_MSB 0
2721 /* The width in bits of the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field. */
2722 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_WIDTH 1
2723 /* The mask used to set the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field value. */
2724 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2725 /* The mask used to clear the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field value. */
2726 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2727 /* The reset value of the ALT_ECC_SDMMC_ACCCTL_DATAOVR register field. */
2728 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_RESET 0x0
2729 /* Extracts the ALT_ECC_SDMMC_ACCCTL_DATAOVR field value from a register. */
2730 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2731 /* Produces a ALT_ECC_SDMMC_ACCCTL_DATAOVR register field value suitable for setting the register. */
2732 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2733 
2734 /*
2735  * Field : ECCOVR
2736  *
2737  * ECC Data Override.
2738  *
2739  * Field Access Macros:
2740  *
2741  */
2742 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field. */
2743 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_LSB 1
2744 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field. */
2745 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_MSB 1
2746 /* The width in bits of the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field. */
2747 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_WIDTH 1
2748 /* The mask used to set the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field value. */
2749 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2750 /* The mask used to clear the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field value. */
2751 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2752 /* The reset value of the ALT_ECC_SDMMC_ACCCTL_ECCOVR register field. */
2753 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_RESET 0x0
2754 /* Extracts the ALT_ECC_SDMMC_ACCCTL_ECCOVR field value from a register. */
2755 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2756 /* Produces a ALT_ECC_SDMMC_ACCCTL_ECCOVR register field value suitable for setting the register. */
2757 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2758 
2759 /*
2760  * Field : RDWR
2761  *
2762  * Control for read/write.
2763  *
2764  * Field Access Macros:
2765  *
2766  */
2767 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_ACCCTL_RDWR register field. */
2768 #define ALT_ECC_SDMMC_ACCCTL_RDWR_LSB 8
2769 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_ACCCTL_RDWR register field. */
2770 #define ALT_ECC_SDMMC_ACCCTL_RDWR_MSB 8
2771 /* The width in bits of the ALT_ECC_SDMMC_ACCCTL_RDWR register field. */
2772 #define ALT_ECC_SDMMC_ACCCTL_RDWR_WIDTH 1
2773 /* The mask used to set the ALT_ECC_SDMMC_ACCCTL_RDWR register field value. */
2774 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET_MSK 0x00000100
2775 /* The mask used to clear the ALT_ECC_SDMMC_ACCCTL_RDWR register field value. */
2776 #define ALT_ECC_SDMMC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2777 /* The reset value of the ALT_ECC_SDMMC_ACCCTL_RDWR register field. */
2778 #define ALT_ECC_SDMMC_ACCCTL_RDWR_RESET 0x0
2779 /* Extracts the ALT_ECC_SDMMC_ACCCTL_RDWR field value from a register. */
2780 #define ALT_ECC_SDMMC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2781 /* Produces a ALT_ECC_SDMMC_ACCCTL_RDWR register field value suitable for setting the register. */
2782 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2783 
2784 #ifndef __ASSEMBLY__
2785 /*
2786  * WARNING: The C register and register group struct declarations are provided for
2787  * convenience and illustrative purposes. They should, however, be used with
2788  * caution as the C language standard provides no guarantees about the alignment or
2789  * atomicity of device memory accesses. The recommended practice for writing
2790  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2791  * alt_write_word() functions.
2792  *
2793  * The struct declaration for register ALT_ECC_SDMMC_ACCCTL.
2794  */
2795 struct ALT_ECC_SDMMC_ACCCTL_s
2796 {
2797  uint32_t DATAOVR : 1; /* ALT_ECC_SDMMC_ACCCTL_DATAOVR */
2798  uint32_t ECCOVR : 1; /* ALT_ECC_SDMMC_ACCCTL_ECCOVR */
2799  uint32_t : 6; /* *UNDEFINED* */
2800  uint32_t RDWR : 1; /* ALT_ECC_SDMMC_ACCCTL_RDWR */
2801  uint32_t : 23; /* *UNDEFINED* */
2802 };
2803 
2804 /* The typedef declaration for register ALT_ECC_SDMMC_ACCCTL. */
2805 typedef volatile struct ALT_ECC_SDMMC_ACCCTL_s ALT_ECC_SDMMC_ACCCTL_t;
2806 #endif /* __ASSEMBLY__ */
2807 
2808 /* The reset value of the ALT_ECC_SDMMC_ACCCTL register. */
2809 #define ALT_ECC_SDMMC_ACCCTL_RESET 0x00000000
2810 /* The byte offset of the ALT_ECC_SDMMC_ACCCTL register from the beginning of the component. */
2811 #define ALT_ECC_SDMMC_ACCCTL_OFST 0x78
2812 /* The address of the ALT_ECC_SDMMC_ACCCTL register. */
2813 #define ALT_ECC_SDMMC_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ACCCTL_OFST))
2814 
2815 /*
2816  * Register : ECC_startacc
2817  *
2818  * These bits determine which byte of data/ecc to write to RAM.
2819  *
2820  * Register Layout
2821  *
2822  * Bits | Access | Reset | Description
2823  * :--------|:-------|:------|:------------------------------
2824  * [0] | RW | 0x0 | ALT_ECC_SDMMC_STARTACC_ENBUSB
2825  * [15:1] | ??? | 0x0 | *UNDEFINED*
2826  * [16] | RW | 0x0 | ALT_ECC_SDMMC_STARTACC_ENBUSA
2827  * [31:17] | ??? | 0x0 | *UNDEFINED*
2828  *
2829  */
2830 /*
2831  * Field : ENBUSB
2832  *
2833  * Start RAM access for PORTB.
2834  *
2835  * Field Access Macros:
2836  *
2837  */
2838 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_STARTACC_ENBUSB register field. */
2839 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_LSB 0
2840 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_STARTACC_ENBUSB register field. */
2841 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_MSB 0
2842 /* The width in bits of the ALT_ECC_SDMMC_STARTACC_ENBUSB register field. */
2843 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_WIDTH 1
2844 /* The mask used to set the ALT_ECC_SDMMC_STARTACC_ENBUSB register field value. */
2845 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET_MSK 0x00000001
2846 /* The mask used to clear the ALT_ECC_SDMMC_STARTACC_ENBUSB register field value. */
2847 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_CLR_MSK 0xfffffffe
2848 /* The reset value of the ALT_ECC_SDMMC_STARTACC_ENBUSB register field. */
2849 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_RESET 0x0
2850 /* Extracts the ALT_ECC_SDMMC_STARTACC_ENBUSB field value from a register. */
2851 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_GET(value) (((value) & 0x00000001) >> 0)
2852 /* Produces a ALT_ECC_SDMMC_STARTACC_ENBUSB register field value suitable for setting the register. */
2853 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET(value) (((value) << 0) & 0x00000001)
2854 
2855 /*
2856  * Field : ENBUSA
2857  *
2858  * Start RAM access for PORTA.
2859  *
2860  * Field Access Macros:
2861  *
2862  */
2863 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_STARTACC_ENBUSA register field. */
2864 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_LSB 16
2865 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_STARTACC_ENBUSA register field. */
2866 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_MSB 16
2867 /* The width in bits of the ALT_ECC_SDMMC_STARTACC_ENBUSA register field. */
2868 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_WIDTH 1
2869 /* The mask used to set the ALT_ECC_SDMMC_STARTACC_ENBUSA register field value. */
2870 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET_MSK 0x00010000
2871 /* The mask used to clear the ALT_ECC_SDMMC_STARTACC_ENBUSA register field value. */
2872 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2873 /* The reset value of the ALT_ECC_SDMMC_STARTACC_ENBUSA register field. */
2874 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_RESET 0x0
2875 /* Extracts the ALT_ECC_SDMMC_STARTACC_ENBUSA field value from a register. */
2876 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2877 /* Produces a ALT_ECC_SDMMC_STARTACC_ENBUSA register field value suitable for setting the register. */
2878 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2879 
2880 #ifndef __ASSEMBLY__
2881 /*
2882  * WARNING: The C register and register group struct declarations are provided for
2883  * convenience and illustrative purposes. They should, however, be used with
2884  * caution as the C language standard provides no guarantees about the alignment or
2885  * atomicity of device memory accesses. The recommended practice for writing
2886  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2887  * alt_write_word() functions.
2888  *
2889  * The struct declaration for register ALT_ECC_SDMMC_STARTACC.
2890  */
2891 struct ALT_ECC_SDMMC_STARTACC_s
2892 {
2893  uint32_t ENBUSB : 1; /* ALT_ECC_SDMMC_STARTACC_ENBUSB */
2894  uint32_t : 15; /* *UNDEFINED* */
2895  uint32_t ENBUSA : 1; /* ALT_ECC_SDMMC_STARTACC_ENBUSA */
2896  uint32_t : 15; /* *UNDEFINED* */
2897 };
2898 
2899 /* The typedef declaration for register ALT_ECC_SDMMC_STARTACC. */
2900 typedef volatile struct ALT_ECC_SDMMC_STARTACC_s ALT_ECC_SDMMC_STARTACC_t;
2901 #endif /* __ASSEMBLY__ */
2902 
2903 /* The reset value of the ALT_ECC_SDMMC_STARTACC register. */
2904 #define ALT_ECC_SDMMC_STARTACC_RESET 0x00000000
2905 /* The byte offset of the ALT_ECC_SDMMC_STARTACC register from the beginning of the component. */
2906 #define ALT_ECC_SDMMC_STARTACC_OFST 0x7c
2907 /* The address of the ALT_ECC_SDMMC_STARTACC register. */
2908 #define ALT_ECC_SDMMC_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_STARTACC_OFST))
2909 
2910 /*
2911  * Register : ECC_wdctrl
2912  *
2913  * Bits to Enable/Disable Watch Dog Timer
2914  *
2915  * Register Layout
2916  *
2917  * Bits | Access | Reset | Description
2918  * :-------|:-------|:------|:-----------------------------
2919  * [0] | RW | 0x0 | ALT_ECC_SDMMC_WDCTL_WDEN_RAM
2920  * [31:1] | ??? | 0x0 | *UNDEFINED*
2921  *
2922  */
2923 /*
2924  * Field : WDEN_RAM
2925  *
2926  * Enable watchdog timeout for OCP register access to IP RAM.
2927  *
2928  * Field Access Macros:
2929  *
2930  */
2931 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field. */
2932 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_LSB 0
2933 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field. */
2934 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_MSB 0
2935 /* The width in bits of the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field. */
2936 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_WIDTH 1
2937 /* The mask used to set the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field value. */
2938 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2939 /* The mask used to clear the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field value. */
2940 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2941 /* The reset value of the ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field. */
2942 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_RESET 0x0
2943 /* Extracts the ALT_ECC_SDMMC_WDCTL_WDEN_RAM field value from a register. */
2944 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2945 /* Produces a ALT_ECC_SDMMC_WDCTL_WDEN_RAM register field value suitable for setting the register. */
2946 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2947 
2948 #ifndef __ASSEMBLY__
2949 /*
2950  * WARNING: The C register and register group struct declarations are provided for
2951  * convenience and illustrative purposes. They should, however, be used with
2952  * caution as the C language standard provides no guarantees about the alignment or
2953  * atomicity of device memory accesses. The recommended practice for writing
2954  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2955  * alt_write_word() functions.
2956  *
2957  * The struct declaration for register ALT_ECC_SDMMC_WDCTL.
2958  */
2959 struct ALT_ECC_SDMMC_WDCTL_s
2960 {
2961  uint32_t WDEN_RAM : 1; /* ALT_ECC_SDMMC_WDCTL_WDEN_RAM */
2962  uint32_t : 31; /* *UNDEFINED* */
2963 };
2964 
2965 /* The typedef declaration for register ALT_ECC_SDMMC_WDCTL. */
2966 typedef volatile struct ALT_ECC_SDMMC_WDCTL_s ALT_ECC_SDMMC_WDCTL_t;
2967 #endif /* __ASSEMBLY__ */
2968 
2969 /* The reset value of the ALT_ECC_SDMMC_WDCTL register. */
2970 #define ALT_ECC_SDMMC_WDCTL_RESET 0x00000000
2971 /* The byte offset of the ALT_ECC_SDMMC_WDCTL register from the beginning of the component. */
2972 #define ALT_ECC_SDMMC_WDCTL_OFST 0x80
2973 /* The address of the ALT_ECC_SDMMC_WDCTL register. */
2974 #define ALT_ECC_SDMMC_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDCTL_OFST))
2975 
2976 /*
2977  * Register : SERRLKUPA0
2978  *
2979  * Single-bit error address in LOOKUP TABLE for PORTA.
2980  *
2981  * Register Layout
2982  *
2983  * Bits | Access | Reset | Description
2984  * :--------|:-------|:------|:-------------------------------
2985  * [9:0] | R | 0x0 | ALT_ECC_SDMMC_SERRLKUPA0_ADDR
2986  * [30:10] | ??? | 0x0 | *UNDEFINED*
2987  * [31] | RW | 0x0 | ALT_ECC_SDMMC_SERRLKUPA0_VALID
2988  *
2989  */
2990 /*
2991  * Field : Address
2992  *
2993  * Recent Single-bit error address.
2994  *
2995  * This register shows the address of the each single-bit error. RAM size will
2996  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
2997  * 30-16 will be reserved and read as zero.
2998  *
2999  * Field Access Macros:
3000  *
3001  */
3002 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field. */
3003 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_LSB 0
3004 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field. */
3005 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_MSB 9
3006 /* The width in bits of the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field. */
3007 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_WIDTH 10
3008 /* The mask used to set the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field value. */
3009 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
3010 /* The mask used to clear the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field value. */
3011 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
3012 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field. */
3013 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_RESET 0x0
3014 /* Extracts the ALT_ECC_SDMMC_SERRLKUPA0_ADDR field value from a register. */
3015 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3016 /* Produces a ALT_ECC_SDMMC_SERRLKUPA0_ADDR register field value suitable for setting the register. */
3017 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3018 
3019 /*
3020  * Field : VALID
3021  *
3022  * Valid flag bit. Valid bit indicates if the address in this register is current
3023  * or stale.
3024  *
3025  * Field Access Macros:
3026  *
3027  */
3028 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field. */
3029 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_LSB 31
3030 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field. */
3031 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_MSB 31
3032 /* The width in bits of the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field. */
3033 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_WIDTH 1
3034 /* The mask used to set the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field value. */
3035 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET_MSK 0x80000000
3036 /* The mask used to clear the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field value. */
3037 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
3038 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPA0_VALID register field. */
3039 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_RESET 0x0
3040 /* Extracts the ALT_ECC_SDMMC_SERRLKUPA0_VALID field value from a register. */
3041 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3042 /* Produces a ALT_ECC_SDMMC_SERRLKUPA0_VALID register field value suitable for setting the register. */
3043 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
3044 
3045 #ifndef __ASSEMBLY__
3046 /*
3047  * WARNING: The C register and register group struct declarations are provided for
3048  * convenience and illustrative purposes. They should, however, be used with
3049  * caution as the C language standard provides no guarantees about the alignment or
3050  * atomicity of device memory accesses. The recommended practice for writing
3051  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3052  * alt_write_word() functions.
3053  *
3054  * The struct declaration for register ALT_ECC_SDMMC_SERRLKUPA0.
3055  */
3056 struct ALT_ECC_SDMMC_SERRLKUPA0_s
3057 {
3058  const uint32_t Address : 10; /* ALT_ECC_SDMMC_SERRLKUPA0_ADDR */
3059  uint32_t : 21; /* *UNDEFINED* */
3060  uint32_t VALID : 1; /* ALT_ECC_SDMMC_SERRLKUPA0_VALID */
3061 };
3062 
3063 /* The typedef declaration for register ALT_ECC_SDMMC_SERRLKUPA0. */
3064 typedef volatile struct ALT_ECC_SDMMC_SERRLKUPA0_s ALT_ECC_SDMMC_SERRLKUPA0_t;
3065 #endif /* __ASSEMBLY__ */
3066 
3067 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPA0 register. */
3068 #define ALT_ECC_SDMMC_SERRLKUPA0_RESET 0x00000000
3069 /* The byte offset of the ALT_ECC_SDMMC_SERRLKUPA0 register from the beginning of the component. */
3070 #define ALT_ECC_SDMMC_SERRLKUPA0_OFST 0x90
3071 
3072 /*
3073  * Register : SERRLKUPB0
3074  *
3075  * Single-bit error address in LOOKUP TABLE for PORTB.
3076  *
3077  * Register Layout
3078  *
3079  * Bits | Access | Reset | Description
3080  * :--------|:-------|:------|:-------------------------------
3081  * [9:0] | R | 0x0 | ALT_ECC_SDMMC_SERRLKUPB0_ADDR
3082  * [30:10] | ??? | 0x0 | *UNDEFINED*
3083  * [31] | RW | 0x0 | ALT_ECC_SDMMC_SERRLKUPB0_VALID
3084  *
3085  */
3086 /*
3087  * Field : Address
3088  *
3089  * Recent Single-bit error address.
3090  *
3091  * This register shows the address of the each single-bit error. RAM size will
3092  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
3093  * 30-16 will be reserved and read as zero.
3094  *
3095  * Field Access Macros:
3096  *
3097  */
3098 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field. */
3099 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_LSB 0
3100 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field. */
3101 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_MSB 9
3102 /* The width in bits of the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field. */
3103 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_WIDTH 10
3104 /* The mask used to set the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field value. */
3105 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET_MSK 0x000003ff
3106 /* The mask used to clear the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field value. */
3107 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_CLR_MSK 0xfffffc00
3108 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field. */
3109 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_RESET 0x0
3110 /* Extracts the ALT_ECC_SDMMC_SERRLKUPB0_ADDR field value from a register. */
3111 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3112 /* Produces a ALT_ECC_SDMMC_SERRLKUPB0_ADDR register field value suitable for setting the register. */
3113 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3114 
3115 /*
3116  * Field : VALID
3117  *
3118  * Valid flag bit. Valid bit indicates if the address in this register is current
3119  * or stale.
3120  *
3121  * Field Access Macros:
3122  *
3123  */
3124 /* The Least Significant Bit (LSB) position of the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field. */
3125 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_LSB 31
3126 /* The Most Significant Bit (MSB) position of the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field. */
3127 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_MSB 31
3128 /* The width in bits of the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field. */
3129 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_WIDTH 1
3130 /* The mask used to set the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field value. */
3131 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET_MSK 0x80000000
3132 /* The mask used to clear the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field value. */
3133 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_CLR_MSK 0x7fffffff
3134 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPB0_VALID register field. */
3135 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_RESET 0x0
3136 /* Extracts the ALT_ECC_SDMMC_SERRLKUPB0_VALID field value from a register. */
3137 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3138 /* Produces a ALT_ECC_SDMMC_SERRLKUPB0_VALID register field value suitable for setting the register. */
3139 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET(value) (((value) << 31) & 0x80000000)
3140 
3141 #ifndef __ASSEMBLY__
3142 /*
3143  * WARNING: The C register and register group struct declarations are provided for
3144  * convenience and illustrative purposes. They should, however, be used with
3145  * caution as the C language standard provides no guarantees about the alignment or
3146  * atomicity of device memory accesses. The recommended practice for writing
3147  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3148  * alt_write_word() functions.
3149  *
3150  * The struct declaration for register ALT_ECC_SDMMC_SERRLKUPB0.
3151  */
3152 struct ALT_ECC_SDMMC_SERRLKUPB0_s
3153 {
3154  const uint32_t Address : 10; /* ALT_ECC_SDMMC_SERRLKUPB0_ADDR */
3155  uint32_t : 21; /* *UNDEFINED* */
3156  uint32_t VALID : 1; /* ALT_ECC_SDMMC_SERRLKUPB0_VALID */
3157 };
3158 
3159 /* The typedef declaration for register ALT_ECC_SDMMC_SERRLKUPB0. */
3160 typedef volatile struct ALT_ECC_SDMMC_SERRLKUPB0_s ALT_ECC_SDMMC_SERRLKUPB0_t;
3161 #endif /* __ASSEMBLY__ */
3162 
3163 /* The reset value of the ALT_ECC_SDMMC_SERRLKUPB0 register. */
3164 #define ALT_ECC_SDMMC_SERRLKUPB0_RESET 0x00000000
3165 /* The byte offset of the ALT_ECC_SDMMC_SERRLKUPB0 register from the beginning of the component. */
3166 #define ALT_ECC_SDMMC_SERRLKUPB0_OFST 0xd0
3167 
3168 #ifndef __ASSEMBLY__
3169 /*
3170  * WARNING: The C register and register group struct declarations are provided for
3171  * convenience and illustrative purposes. They should, however, be used with
3172  * caution as the C language standard provides no guarantees about the alignment or
3173  * atomicity of device memory accesses. The recommended practice for writing
3174  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3175  * alt_write_word() functions.
3176  *
3177  * The struct declaration for register group ALT_ECC_SDMMC.
3178  */
3179 struct ALT_ECC_SDMMC_s
3180 {
3181  ALT_ECC_SDMMC_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_SDMMC_IP_REV_ID */
3182  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
3183  ALT_ECC_SDMMC_CTL_t CTRL; /* ALT_ECC_SDMMC_CTL */
3184  ALT_ECC_SDMMC_INITSTAT_t INITSTAT; /* ALT_ECC_SDMMC_INITSTAT */
3185  ALT_ECC_SDMMC_ERRINTEN_t ERRINTEN; /* ALT_ECC_SDMMC_ERRINTEN */
3186  ALT_ECC_SDMMC_ERRINTENS_t ERRINTENS; /* ALT_ECC_SDMMC_ERRINTENS */
3187  ALT_ECC_SDMMC_ERRINTENR_t ERRINTENR; /* ALT_ECC_SDMMC_ERRINTENR */
3188  ALT_ECC_SDMMC_INTMOD_t INTMODE; /* ALT_ECC_SDMMC_INTMOD */
3189  ALT_ECC_SDMMC_INTSTAT_t INTSTAT; /* ALT_ECC_SDMMC_INTSTAT */
3190  ALT_ECC_SDMMC_INTTEST_t INTTEST; /* ALT_ECC_SDMMC_INTTEST */
3191  ALT_ECC_SDMMC_MODSTAT_t MODSTAT; /* ALT_ECC_SDMMC_MODSTAT */
3192  ALT_ECC_SDMMC_DERRADDRA_t DERRADDRA; /* ALT_ECC_SDMMC_DERRADDRA */
3193  ALT_ECC_SDMMC_SERRADDRA_t SERRADDRA; /* ALT_ECC_SDMMC_SERRADDRA */
3194  ALT_ECC_SDMMC_DERRADDRB_t DERRADDRB; /* ALT_ECC_SDMMC_DERRADDRB */
3195  ALT_ECC_SDMMC_SERRADDRB_t SERRADDRB; /* ALT_ECC_SDMMC_SERRADDRB */
3196  ALT_ECC_SDMMC_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_SDMMC_SERRCNTREG */
3197  ALT_ECC_SDMMC_ADDRBUS_t ECC_Addrbus; /* ALT_ECC_SDMMC_ADDRBUS */
3198  ALT_ECC_SDMMC_RDATA0BUS_t ECC_RData0bus; /* ALT_ECC_SDMMC_RDATA0BUS */
3199  ALT_ECC_SDMMC_RDATA1BUS_t ECC_RData1bus; /* ALT_ECC_SDMMC_RDATA1BUS */
3200  ALT_ECC_SDMMC_RDATA2BUS_t ECC_RData2bus; /* ALT_ECC_SDMMC_RDATA2BUS */
3201  ALT_ECC_SDMMC_RDATA3BUS_t ECC_RData3bus; /* ALT_ECC_SDMMC_RDATA3BUS */
3202  ALT_ECC_SDMMC_WDATA0BUS_t ECC_WData0bus; /* ALT_ECC_SDMMC_WDATA0BUS */
3203  ALT_ECC_SDMMC_WDATA1BUS_t ECC_WData1bus; /* ALT_ECC_SDMMC_WDATA1BUS */
3204  ALT_ECC_SDMMC_WDATA2BUS_t ECC_WData2bus; /* ALT_ECC_SDMMC_WDATA2BUS */
3205  ALT_ECC_SDMMC_WDATA3BUS_t ECC_WData3bus; /* ALT_ECC_SDMMC_WDATA3BUS */
3206  ALT_ECC_SDMMC_RDATAECC0BUS_t ECC_RDataecc0bus; /* ALT_ECC_SDMMC_RDATAECC0BUS */
3207  ALT_ECC_SDMMC_RDATAECC1BUS_t ECC_RDataecc1bus; /* ALT_ECC_SDMMC_RDATAECC1BUS */
3208  ALT_ECC_SDMMC_WDATAECC0BUS_t ECC_WDataecc0bus; /* ALT_ECC_SDMMC_WDATAECC0BUS */
3209  ALT_ECC_SDMMC_WDATAECC1BUS_t ECC_WDataecc1bus; /* ALT_ECC_SDMMC_WDATAECC1BUS */
3210  ALT_ECC_SDMMC_DBYTECTL_t ECC_dbytectrl; /* ALT_ECC_SDMMC_DBYTECTL */
3211  ALT_ECC_SDMMC_ACCCTL_t ECC_accctrl; /* ALT_ECC_SDMMC_ACCCTL */
3212  ALT_ECC_SDMMC_STARTACC_t ECC_startacc; /* ALT_ECC_SDMMC_STARTACC */
3213  ALT_ECC_SDMMC_WDCTL_t ECC_wdctrl; /* ALT_ECC_SDMMC_WDCTL */
3214  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3215  ALT_ECC_SDMMC_SERRLKUPA0_t SERRLKUPA0; /* ALT_ECC_SDMMC_SERRLKUPA0 */
3216  volatile uint32_t _pad_0x94_0xcf[15]; /* *UNDEFINED* */
3217  ALT_ECC_SDMMC_SERRLKUPB0_t SERRLKUPB0; /* ALT_ECC_SDMMC_SERRLKUPB0 */
3218  volatile uint32_t _pad_0xd4_0x400[203]; /* *UNDEFINED* */
3219 };
3220 
3221 /* The typedef declaration for register group ALT_ECC_SDMMC. */
3222 typedef volatile struct ALT_ECC_SDMMC_s ALT_ECC_SDMMC_t;
3223 /* The struct declaration for the raw register contents of register group ALT_ECC_SDMMC. */
3224 struct ALT_ECC_SDMMC_raw_s
3225 {
3226  volatile uint32_t IP_REV_ID; /* ALT_ECC_SDMMC_IP_REV_ID */
3227  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
3228  volatile uint32_t CTRL; /* ALT_ECC_SDMMC_CTL */
3229  volatile uint32_t INITSTAT; /* ALT_ECC_SDMMC_INITSTAT */
3230  volatile uint32_t ERRINTEN; /* ALT_ECC_SDMMC_ERRINTEN */
3231  volatile uint32_t ERRINTENS; /* ALT_ECC_SDMMC_ERRINTENS */
3232  volatile uint32_t ERRINTENR; /* ALT_ECC_SDMMC_ERRINTENR */
3233  volatile uint32_t INTMODE; /* ALT_ECC_SDMMC_INTMOD */
3234  volatile uint32_t INTSTAT; /* ALT_ECC_SDMMC_INTSTAT */
3235  volatile uint32_t INTTEST; /* ALT_ECC_SDMMC_INTTEST */
3236  volatile uint32_t MODSTAT; /* ALT_ECC_SDMMC_MODSTAT */
3237  volatile uint32_t DERRADDRA; /* ALT_ECC_SDMMC_DERRADDRA */
3238  volatile uint32_t SERRADDRA; /* ALT_ECC_SDMMC_SERRADDRA */
3239  volatile uint32_t DERRADDRB; /* ALT_ECC_SDMMC_DERRADDRB */
3240  volatile uint32_t SERRADDRB; /* ALT_ECC_SDMMC_SERRADDRB */
3241  volatile uint32_t SERRCNTREG; /* ALT_ECC_SDMMC_SERRCNTREG */
3242  volatile uint32_t ECC_Addrbus; /* ALT_ECC_SDMMC_ADDRBUS */
3243  volatile uint32_t ECC_RData0bus; /* ALT_ECC_SDMMC_RDATA0BUS */
3244  volatile uint32_t ECC_RData1bus; /* ALT_ECC_SDMMC_RDATA1BUS */
3245  volatile uint32_t ECC_RData2bus; /* ALT_ECC_SDMMC_RDATA2BUS */
3246  volatile uint32_t ECC_RData3bus; /* ALT_ECC_SDMMC_RDATA3BUS */
3247  volatile uint32_t ECC_WData0bus; /* ALT_ECC_SDMMC_WDATA0BUS */
3248  volatile uint32_t ECC_WData1bus; /* ALT_ECC_SDMMC_WDATA1BUS */
3249  volatile uint32_t ECC_WData2bus; /* ALT_ECC_SDMMC_WDATA2BUS */
3250  volatile uint32_t ECC_WData3bus; /* ALT_ECC_SDMMC_WDATA3BUS */
3251  volatile uint32_t ECC_RDataecc0bus; /* ALT_ECC_SDMMC_RDATAECC0BUS */
3252  volatile uint32_t ECC_RDataecc1bus; /* ALT_ECC_SDMMC_RDATAECC1BUS */
3253  volatile uint32_t ECC_WDataecc0bus; /* ALT_ECC_SDMMC_WDATAECC0BUS */
3254  volatile uint32_t ECC_WDataecc1bus; /* ALT_ECC_SDMMC_WDATAECC1BUS */
3255  volatile uint32_t ECC_dbytectrl; /* ALT_ECC_SDMMC_DBYTECTL */
3256  volatile uint32_t ECC_accctrl; /* ALT_ECC_SDMMC_ACCCTL */
3257  volatile uint32_t ECC_startacc; /* ALT_ECC_SDMMC_STARTACC */
3258  volatile uint32_t ECC_wdctrl; /* ALT_ECC_SDMMC_WDCTL */
3259  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
3260  volatile uint32_t SERRLKUPA0; /* ALT_ECC_SDMMC_SERRLKUPA0 */
3261  uint32_t _pad_0x94_0xcf[15]; /* *UNDEFINED* */
3262  volatile uint32_t SERRLKUPB0; /* ALT_ECC_SDMMC_SERRLKUPB0 */
3263  uint32_t _pad_0xd4_0x400[203]; /* *UNDEFINED* */
3264 };
3265 
3266 /* The typedef declaration for the raw register contents of register group ALT_ECC_SDMMC. */
3267 typedef volatile struct ALT_ECC_SDMMC_raw_s ALT_ECC_SDMMC_raw_t;
3268 #endif /* __ASSEMBLY__ */
3269 
3270 
3271 #ifdef __cplusplus
3272 }
3273 #endif /* __cplusplus */
3274 #endif /* __ALT_SOCAL_ECC_SDMMC_H__ */
3275