Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_mpu_registers.h
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32 
33 /*
34  * $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/alt_mpu_registers.h#1 $
35  */
36 
37 #ifndef __ALT_MPUSCU_H__
38 #define __ALT_MPUSCU_H__
39 
40 
41 #ifdef __cplusplus
42 extern "C"
43 {
44 #endif /* __cplusplus */
45 
46 
47 /************************************************************************************************************/
48 /* alt_mpuscu.h */
49 /* */
50 /* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
51 /* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
52 /* */
53 /************************************************************************************************************/
54 
55 #ifndef ALT_HPS_ADDR
56 #define ALT_HPS_ADDR 0x00
57 #endif
58 
59 
60 /* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
61 /* and is the address of the base of the Snoop Control Unit (SCU) */
62 #define ALT_GLOBALTMR_BASE (ALT_MPUSCU_OFST + ALT_GLOBALTMR_MODULE_BASE_OFFSET)
63 #define ALT_CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + ALT_WDOG_TIMER_MODULE_BASE_OFFSET)
64 #define ALT_CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + ALT_CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
65 #define ALT_CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + ALT_INT_CONTROLLER_MODULE_BASE_OFFSET)
66 #define ALT_CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + ALT_INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
67 
68 
69  /* offsets */
70  /* Global Timer offsets */
71 #define ALT_GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
72 #define ALT_GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
73 #define ALT_GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
74 #define ALT_GLOBALTMR_CTRL_REG_OFFSET 0x00000008
75 #define ALT_GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
76 #define ALT_GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
77 #define ALT_GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
78 #define ALT_GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
79 
80  /* Global Timer bitmasks */
81 #define ALT_GLOBALTMR_ENABLE_BIT 0x00000001
82 #define ALT_GLOBALTMR_COMP_ENABLE_BIT 0x00000002
83 #define ALT_GLOBALTMR_INT_ENABLE_BIT 0x00000004
84 #define ALT_GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
85 #define ALT_GLOBALTMR_PS_MASK 0x0000FF00
86 #define ALT_GLOBALTMR_PS_SHIFT 8
87 #define ALT_GLOBALTMR_INT_STATUS_BIT 0x00000001
88 
89  /* Global timer constants */
90 #define ALT_GLOBALTMR_MAX 0xFFFFFFFF
91 #define ALT_GLOBALTMR_PS_MAX 0x000000FF
92 
93 
94  /* Private timer offsets */
95 #define ALT_CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
96 #define ALT_CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
97 #define ALT_CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
98 #define ALT_CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
99 #define ALT_CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
100 
101  /* Private timer bitmasks */
102 #define ALT_CPU_PRIV_TMR_ENABLE 0x00000001
103 #define ALT_CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
104 #define ALT_CPU_PRIV_TMR_INT_EN 0x00000004
105 #define ALT_CPU_PRIV_TMR_PS_MASK 0x0000FF00
106 #define ALT_CPU_PRIV_TMR_PS_SHIFT 8
107 #define ALT_CPU_PRIV_TMR_INT_STATUS 0x00000001
108 
109  /* Private timer constants */
110 #define ALT_CPU_PRIV_TMR_MAX 0xFFFFFFFF
111 #define ALT_CPU_PRIV_TMR_PS_MAX 0x000000FF
112 
113 
114  /* Watchdog timer offsets */
115 #define ALT_WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
116 #define ALT_WDOG_LOAD_REG_OFFSET 0x00000000
117 #define ALT_WDOG_CNTR_REG_OFFSET 0x00000004
118 #define ALT_WDOG_CTRL_REG_OFFSET 0x00000008
119 #define ALT_WDOG_INTSTAT_REG_OFFSET 0x0000000C
120 #define ALT_WDOG_RSTSTAT_REG_OFFSET 0x00000010
121 #define ALT_WDOG_DISABLE_REG_OFFSET 0x00000014
122 
123  /* Watchdog timer bitmasks : */
124  /* Control Register bitmasks */
125 #define ALT_WDOG_TMR_ENABLE 0x00000001
126 #define ALT_WDOG_AUTO_RELOAD 0x00000002
127 #define ALT_WDOG_INT_EN 0x00000004
128 #define ALT_WDOG_WDT_MODE 0x00000008
129 #define ALT_WDOG_PS_MASK 0x0000FF00
130 #define ALT_WDOG_PS_SHIFT 8
131  /* Interrupt Status Register bitmasks */
132 #define ALT_WDOG_INT_STAT_BIT 0x00000001
133  /* Reset Status Register bitmasks */
134 #define ALT_WDOG_RST_STAT_BIT 0x00000001
135 
136  /* Watchdog timer constants */
137 #define ALT_WDOG_TMR_MAX UINT32_MAX
138 #define ALT_WDOG_PS_MAX UINT8_MAX
139 #define ALT_WDOG_DISABLE_VAL0 0x12345678
140 #define ALT_WDOG_DISABLE_VAL1 0x87654321
141 
142 
143 
144  /* Interrupt Manager offsets */
145  /* <Add definitions here> */
146 #define ALT_INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
147 #define ALT_INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
148 #define ALT_INT_DIST_TYPE_REG 0x00000004
149 
150 
151  /* Upper bound of the MPUSCU address space */
152 #define ALT_MPUSCU_MAX 0x00001FFF
153 
154 
155 
156 #ifdef __cplusplus
157 }
158 #endif /* __cplusplus */
159 
160 #endif /* __ALT_MPUSCU_H__ */