35 #ifndef __ALT_SOCAL_ECC_HMC_OCP_H__
36 #define __ALT_SOCAL_ECC_HMC_OCP_H__
74 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_LSB 0
76 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_MSB 15
78 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_WIDTH 16
80 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
82 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
84 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_RESET 0x0
86 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
88 #define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
101 struct ALT_ECC_HMC_OCP_IP_REV_ID_s
108 typedef volatile struct ALT_ECC_HMC_OCP_IP_REV_ID_s ALT_ECC_HMC_OCP_IP_REV_ID_t;
112 #define ALT_ECC_HMC_OCP_IP_REV_ID_RESET 0x00000000
114 #define ALT_ECC_HMC_OCP_IP_REV_ID_OFST 0x0
146 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_LSB 0
148 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_MSB 1
150 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_WIDTH 2
152 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET_MSK 0x00000003
154 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_CLR_MSK 0xfffffffc
156 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_RESET 0x0
158 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_GET(value) (((value) & 0x00000003) >> 0)
160 #define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET(value) (((value) << 0) & 0x00000003)
173 struct ALT_ECC_HMC_OCP_DDRIOCTL_s
175 uint32_t IO_SIZE : 2;
180 typedef volatile struct ALT_ECC_HMC_OCP_DDRIOCTL_s ALT_ECC_HMC_OCP_DDRIOCTL_t;
184 #define ALT_ECC_HMC_OCP_DDRIOCTL_RESET 0x00000000
186 #define ALT_ECC_HMC_OCP_DDRIOCTL_OFST 0x8
216 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_LSB 0
218 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_MSB 0
220 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_WIDTH 1
222 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET_MSK 0x00000001
224 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_CLR_MSK 0xfffffffe
226 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_RESET 0x0
228 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_GET(value) (((value) & 0x00000001) >> 0)
230 #define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET(value) (((value) << 0) & 0x00000001)
243 struct ALT_ECC_HMC_OCP_DDRCALSTAT_s
250 typedef volatile struct ALT_ECC_HMC_OCP_DDRCALSTAT_s ALT_ECC_HMC_OCP_DDRCALSTAT_t;
254 #define ALT_ECC_HMC_OCP_DDRCALSTAT_RESET 0x00000000
256 #define ALT_ECC_HMC_OCP_DDRCALSTAT_OFST 0xc
279 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_LSB 0
281 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_MSB 31
283 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_WIDTH 32
285 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET_MSK 0xffffffff
287 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_CLR_MSK 0x00000000
289 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_RESET 0x0
291 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
293 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET(value) (((value) << 0) & 0xffffffff)
306 struct ALT_ECC_HMC_OCP_MPR_0BEAT1_s
312 typedef volatile struct ALT_ECC_HMC_OCP_MPR_0BEAT1_s ALT_ECC_HMC_OCP_MPR_0BEAT1_t;
316 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_RESET 0x00000000
318 #define ALT_ECC_HMC_OCP_MPR_0BEAT1_OFST 0x10
341 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_LSB 0
343 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_MSB 31
345 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_WIDTH 32
347 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET_MSK 0xffffffff
349 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_CLR_MSK 0x00000000
351 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_RESET 0x0
353 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
355 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET(value) (((value) << 0) & 0xffffffff)
368 struct ALT_ECC_HMC_OCP_MPR_1BEAT1_s
374 typedef volatile struct ALT_ECC_HMC_OCP_MPR_1BEAT1_s ALT_ECC_HMC_OCP_MPR_1BEAT1_t;
378 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_RESET 0x00000000
380 #define ALT_ECC_HMC_OCP_MPR_1BEAT1_OFST 0x14
403 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_LSB 0
405 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_MSB 31
407 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_WIDTH 32
409 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET_MSK 0xffffffff
411 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_CLR_MSK 0x00000000
413 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_RESET 0x0
415 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
417 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET(value) (((value) << 0) & 0xffffffff)
430 struct ALT_ECC_HMC_OCP_MPR_2BEAT1_s
436 typedef volatile struct ALT_ECC_HMC_OCP_MPR_2BEAT1_s ALT_ECC_HMC_OCP_MPR_2BEAT1_t;
440 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_RESET 0x00000000
442 #define ALT_ECC_HMC_OCP_MPR_2BEAT1_OFST 0x18
465 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_LSB 0
467 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_MSB 31
469 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_WIDTH 32
471 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET_MSK 0xffffffff
473 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_CLR_MSK 0x00000000
475 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_RESET 0x0
477 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
479 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET(value) (((value) << 0) & 0xffffffff)
492 struct ALT_ECC_HMC_OCP_MPR_3BEAT1_s
498 typedef volatile struct ALT_ECC_HMC_OCP_MPR_3BEAT1_s ALT_ECC_HMC_OCP_MPR_3BEAT1_t;
502 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_RESET 0x00000000
504 #define ALT_ECC_HMC_OCP_MPR_3BEAT1_OFST 0x1c
527 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_LSB 0
529 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_MSB 31
531 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_WIDTH 32
533 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET_MSK 0xffffffff
535 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_CLR_MSK 0x00000000
537 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_RESET 0x0
539 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
541 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET(value) (((value) << 0) & 0xffffffff)
554 struct ALT_ECC_HMC_OCP_MPR_4BEAT1_s
556 uint32_t MPR128 : 32;
560 typedef volatile struct ALT_ECC_HMC_OCP_MPR_4BEAT1_s ALT_ECC_HMC_OCP_MPR_4BEAT1_t;
564 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_RESET 0x00000000
566 #define ALT_ECC_HMC_OCP_MPR_4BEAT1_OFST 0x20
589 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_LSB 0
591 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_MSB 31
593 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_WIDTH 32
595 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET_MSK 0xffffffff
597 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_CLR_MSK 0x00000000
599 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_RESET 0x0
601 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
603 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET(value) (((value) << 0) & 0xffffffff)
616 struct ALT_ECC_HMC_OCP_MPR_5BEAT1_s
618 uint32_t MPR160 : 32;
622 typedef volatile struct ALT_ECC_HMC_OCP_MPR_5BEAT1_s ALT_ECC_HMC_OCP_MPR_5BEAT1_t;
626 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_RESET 0x00000000
628 #define ALT_ECC_HMC_OCP_MPR_5BEAT1_OFST 0x24
651 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_LSB 0
653 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_MSB 31
655 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_WIDTH 32
657 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET_MSK 0xffffffff
659 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_CLR_MSK 0x00000000
661 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_RESET 0x0
663 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
665 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET(value) (((value) << 0) & 0xffffffff)
678 struct ALT_ECC_HMC_OCP_MPR_6BEAT1_s
680 uint32_t MPR192 : 32;
684 typedef volatile struct ALT_ECC_HMC_OCP_MPR_6BEAT1_s ALT_ECC_HMC_OCP_MPR_6BEAT1_t;
688 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_RESET 0x00000000
690 #define ALT_ECC_HMC_OCP_MPR_6BEAT1_OFST 0x28
713 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_LSB 0
715 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_MSB 31
717 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_WIDTH 32
719 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET_MSK 0xffffffff
721 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_CLR_MSK 0x00000000
723 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_RESET 0x0
725 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
727 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET(value) (((value) << 0) & 0xffffffff)
740 struct ALT_ECC_HMC_OCP_MPR_7BEAT1_s
742 uint32_t MPR224 : 32;
746 typedef volatile struct ALT_ECC_HMC_OCP_MPR_7BEAT1_s ALT_ECC_HMC_OCP_MPR_7BEAT1_t;
750 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_RESET 0x00000000
752 #define ALT_ECC_HMC_OCP_MPR_7BEAT1_OFST 0x2c
775 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_LSB 0
777 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_MSB 31
779 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_WIDTH 32
781 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET_MSK 0xffffffff
783 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_CLR_MSK 0x00000000
785 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_RESET 0x0
787 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
789 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET(value) (((value) << 0) & 0xffffffff)
802 struct ALT_ECC_HMC_OCP_MPR_8BEAT1_s
804 uint32_t MPR256 : 32;
808 typedef volatile struct ALT_ECC_HMC_OCP_MPR_8BEAT1_s ALT_ECC_HMC_OCP_MPR_8BEAT1_t;
812 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_RESET 0x00000000
814 #define ALT_ECC_HMC_OCP_MPR_8BEAT1_OFST 0x30
837 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_LSB 0
839 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_MSB 31
841 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_WIDTH 32
843 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET_MSK 0xffffffff
845 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_CLR_MSK 0x00000000
847 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_RESET 0x0
849 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
851 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET(value) (((value) << 0) & 0xffffffff)
864 struct ALT_ECC_HMC_OCP_MPR_0BEAT2_s
870 typedef volatile struct ALT_ECC_HMC_OCP_MPR_0BEAT2_s ALT_ECC_HMC_OCP_MPR_0BEAT2_t;
874 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_RESET 0x00000000
876 #define ALT_ECC_HMC_OCP_MPR_0BEAT2_OFST 0x34
899 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_LSB 0
901 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_MSB 31
903 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_WIDTH 32
905 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET_MSK 0xffffffff
907 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_CLR_MSK 0x00000000
909 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_RESET 0x0
911 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
913 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET(value) (((value) << 0) & 0xffffffff)
926 struct ALT_ECC_HMC_OCP_MPR_1BEAT2_s
932 typedef volatile struct ALT_ECC_HMC_OCP_MPR_1BEAT2_s ALT_ECC_HMC_OCP_MPR_1BEAT2_t;
936 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_RESET 0x00000000
938 #define ALT_ECC_HMC_OCP_MPR_1BEAT2_OFST 0x38
961 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_LSB 0
963 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_MSB 31
965 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_WIDTH 32
967 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET_MSK 0xffffffff
969 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_CLR_MSK 0x00000000
971 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_RESET 0x0
973 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
975 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET(value) (((value) << 0) & 0xffffffff)
988 struct ALT_ECC_HMC_OCP_MPR_2BEAT2_s
994 typedef volatile struct ALT_ECC_HMC_OCP_MPR_2BEAT2_s ALT_ECC_HMC_OCP_MPR_2BEAT2_t;
998 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_RESET 0x00000000
1000 #define ALT_ECC_HMC_OCP_MPR_2BEAT2_OFST 0x3c
1023 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_LSB 0
1025 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_MSB 31
1027 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_WIDTH 32
1029 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET_MSK 0xffffffff
1031 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_CLR_MSK 0x00000000
1033 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_RESET 0x0
1035 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
1037 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET(value) (((value) << 0) & 0xffffffff)
1039 #ifndef __ASSEMBLY__
1050 struct ALT_ECC_HMC_OCP_MPR_3BEAT2_s
1052 uint32_t MPR96 : 32;
1056 typedef volatile struct ALT_ECC_HMC_OCP_MPR_3BEAT2_s ALT_ECC_HMC_OCP_MPR_3BEAT2_t;
1060 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_RESET 0x00000000
1062 #define ALT_ECC_HMC_OCP_MPR_3BEAT2_OFST 0x40
1085 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_LSB 0
1087 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_MSB 31
1089 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_WIDTH 32
1091 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET_MSK 0xffffffff
1093 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_CLR_MSK 0x00000000
1095 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_RESET 0x0
1097 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
1099 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET(value) (((value) << 0) & 0xffffffff)
1101 #ifndef __ASSEMBLY__
1112 struct ALT_ECC_HMC_OCP_MPR_4BEAT2_s
1114 uint32_t MPR128 : 32;
1118 typedef volatile struct ALT_ECC_HMC_OCP_MPR_4BEAT2_s ALT_ECC_HMC_OCP_MPR_4BEAT2_t;
1122 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_RESET 0x00000000
1124 #define ALT_ECC_HMC_OCP_MPR_4BEAT2_OFST 0x44
1147 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_LSB 0
1149 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_MSB 31
1151 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_WIDTH 32
1153 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET_MSK 0xffffffff
1155 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_CLR_MSK 0x00000000
1157 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_RESET 0x0
1159 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
1161 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET(value) (((value) << 0) & 0xffffffff)
1163 #ifndef __ASSEMBLY__
1174 struct ALT_ECC_HMC_OCP_MPR_5BEAT2_s
1176 uint32_t MPR160 : 32;
1180 typedef volatile struct ALT_ECC_HMC_OCP_MPR_5BEAT2_s ALT_ECC_HMC_OCP_MPR_5BEAT2_t;
1184 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_RESET 0x00000000
1186 #define ALT_ECC_HMC_OCP_MPR_5BEAT2_OFST 0x48
1209 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_LSB 0
1211 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_MSB 31
1213 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_WIDTH 32
1215 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET_MSK 0xffffffff
1217 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_CLR_MSK 0x00000000
1219 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_RESET 0x0
1221 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
1223 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET(value) (((value) << 0) & 0xffffffff)
1225 #ifndef __ASSEMBLY__
1236 struct ALT_ECC_HMC_OCP_MPR_6BEAT2_s
1238 uint32_t MPR192 : 32;
1242 typedef volatile struct ALT_ECC_HMC_OCP_MPR_6BEAT2_s ALT_ECC_HMC_OCP_MPR_6BEAT2_t;
1246 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_RESET 0x00000000
1248 #define ALT_ECC_HMC_OCP_MPR_6BEAT2_OFST 0x4c
1271 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_LSB 0
1273 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_MSB 31
1275 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_WIDTH 32
1277 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET_MSK 0xffffffff
1279 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_CLR_MSK 0x00000000
1281 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_RESET 0x0
1283 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
1285 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET(value) (((value) << 0) & 0xffffffff)
1287 #ifndef __ASSEMBLY__
1298 struct ALT_ECC_HMC_OCP_MPR_7BEAT2_s
1300 uint32_t MPR224 : 32;
1304 typedef volatile struct ALT_ECC_HMC_OCP_MPR_7BEAT2_s ALT_ECC_HMC_OCP_MPR_7BEAT2_t;
1308 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_RESET 0x00000000
1310 #define ALT_ECC_HMC_OCP_MPR_7BEAT2_OFST 0x50
1333 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_LSB 0
1335 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_MSB 31
1337 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_WIDTH 32
1339 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET_MSK 0xffffffff
1341 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_CLR_MSK 0x00000000
1343 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_RESET 0x0
1345 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
1347 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET(value) (((value) << 0) & 0xffffffff)
1349 #ifndef __ASSEMBLY__
1360 struct ALT_ECC_HMC_OCP_MPR_8BEAT2_s
1362 uint32_t MPR256 : 32;
1366 typedef volatile struct ALT_ECC_HMC_OCP_MPR_8BEAT2_s ALT_ECC_HMC_OCP_MPR_8BEAT2_t;
1370 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_RESET 0x00000000
1372 #define ALT_ECC_HMC_OCP_MPR_8BEAT2_OFST 0x54
1396 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_LSB 0
1398 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_MSB 0
1400 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_WIDTH 1
1402 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET_MSK 0x00000001
1404 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_CLR_MSK 0xfffffffe
1406 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_RESET 0x0
1408 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_GET(value) (((value) & 0x00000001) >> 0)
1410 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET(value) (((value) << 0) & 0x00000001)
1412 #ifndef __ASSEMBLY__
1423 struct ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s
1430 typedef volatile struct ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t;
1434 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_RESET 0x00000000
1436 #define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_OFST 0x60
1471 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_LSB 0
1473 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_MSB 0
1475 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_WIDTH 1
1477 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET_MSK 0x00000001
1479 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_CLR_MSK 0xfffffffe
1481 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_RESET 0x0
1483 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
1485 #define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
1500 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_LSB 8
1502 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_MSB 8
1504 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_WIDTH 1
1506 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET_MSK 0x00000100
1508 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_CLR_MSK 0xfffffeff
1510 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_RESET 0x0
1512 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_GET(value) (((value) & 0x00000100) >> 8)
1514 #define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET(value) (((value) << 8) & 0x00000100)
1529 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_LSB 16
1531 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_MSB 16
1533 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_WIDTH 1
1535 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
1537 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_CLR_MSK 0xfffeffff
1539 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_RESET 0x0
1541 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_GET(value) (((value) & 0x00010000) >> 16)
1543 #define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET(value) (((value) << 16) & 0x00010000)
1545 #ifndef __ASSEMBLY__
1556 struct ALT_ECC_HMC_OCP_ECCCTL1_s
1558 uint32_t ECC_EN : 1;
1560 uint32_t CNT_RST : 1;
1562 uint32_t AUTOWB_CNT_RST : 1;
1567 typedef volatile struct ALT_ECC_HMC_OCP_ECCCTL1_s ALT_ECC_HMC_OCP_ECCCTL1_t;
1571 #define ALT_ECC_HMC_OCP_ECCCTL1_RESET 0x00000000
1573 #define ALT_ECC_HMC_OCP_ECCCTL1_OFST 0x100
1611 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_LSB 0
1613 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_MSB 0
1615 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_WIDTH 1
1617 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET_MSK 0x00000001
1619 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_CLR_MSK 0xfffffffe
1621 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_RESET 0x0
1623 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0)
1625 #define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001)
1644 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_LSB 8
1646 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_MSB 8
1648 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_WIDTH 1
1650 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100
1652 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_CLR_MSK 0xfffffeff
1654 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_RESET 0x0
1656 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8)
1658 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100)
1674 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_LSB 16
1676 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_MSB 16
1678 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_WIDTH 1
1680 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
1682 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff
1684 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_RESET 0x0
1686 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16)
1688 #define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000)
1690 #ifndef __ASSEMBLY__
1701 struct ALT_ECC_HMC_OCP_ECCCTL2_s
1703 uint32_t AUTOWB_EN : 1;
1705 uint32_t RMW_EN : 1;
1707 uint32_t OVRW_RB_ECC_EN : 1;
1712 typedef volatile struct ALT_ECC_HMC_OCP_ECCCTL2_s ALT_ECC_HMC_OCP_ECCCTL2_t;
1716 #define ALT_ECC_HMC_OCP_ECCCTL2_RESET 0x00000000
1718 #define ALT_ECC_HMC_OCP_ECCCTL2_OFST 0x104
1749 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_LSB 0
1751 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_MSB 0
1753 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_WIDTH 1
1755 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
1757 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
1759 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_RESET 0x0
1761 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
1763 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
1781 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_LSB 1
1783 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_MSB 1
1785 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_WIDTH 1
1787 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
1789 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_CLR_MSK 0xfffffffd
1791 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_RESET 0x0
1793 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_GET(value) (((value) & 0x00000002) >> 1)
1795 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET(value) (((value) << 1) & 0x00000002)
1815 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_LSB 2
1817 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_MSB 2
1819 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_WIDTH 1
1821 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET_MSK 0x00000004
1823 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_CLR_MSK 0xfffffffb
1825 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_RESET 0x0
1827 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_GET(value) (((value) & 0x00000004) >> 2)
1829 #define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET(value) (((value) << 2) & 0x00000004)
1831 #ifndef __ASSEMBLY__
1842 struct ALT_ECC_HMC_OCP_ERRINTEN_s
1844 uint32_t SERRINTEN : 1;
1845 uint32_t DERRINTEN : 1;
1846 uint32_t HMI_INTREN : 1;
1851 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTEN_s ALT_ECC_HMC_OCP_ERRINTEN_t;
1855 #define ALT_ECC_HMC_OCP_ERRINTEN_RESET 0x00000000
1857 #define ALT_ECC_HMC_OCP_ERRINTEN_OFST 0x110
1891 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_LSB 0
1893 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_MSB 0
1895 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_WIDTH 1
1897 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET_MSK 0x00000001
1899 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
1901 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_RESET 0x0
1903 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
1905 #define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
1924 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_LSB 1
1926 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_MSB 1
1928 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_WIDTH 1
1930 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET_MSK 0x00000002
1932 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_CLR_MSK 0xfffffffd
1934 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_RESET 0x0
1936 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_GET(value) (((value) & 0x00000002) >> 1)
1938 #define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET(value) (((value) << 1) & 0x00000002)
1955 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_LSB 2
1957 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_MSB 2
1959 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_WIDTH 1
1961 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET_MSK 0x00000004
1963 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_CLR_MSK 0xfffffffb
1965 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_RESET 0x0
1967 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_GET(value) (((value) & 0x00000004) >> 2)
1969 #define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET(value) (((value) << 2) & 0x00000004)
1971 #ifndef __ASSEMBLY__
1982 struct ALT_ECC_HMC_OCP_ERRINTENS_s
1984 uint32_t SERRINTS : 1;
1985 uint32_t DERRINTS : 1;
1986 uint32_t HMI_INTRS : 1;
1991 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTENS_s ALT_ECC_HMC_OCP_ERRINTENS_t;
1995 #define ALT_ECC_HMC_OCP_ERRINTENS_RESET 0x00000000
1997 #define ALT_ECC_HMC_OCP_ERRINTENS_OFST 0x114
2031 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_LSB 0
2033 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_MSB 0
2035 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_WIDTH 1
2037 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET_MSK 0x00000001
2039 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
2041 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_RESET 0x0
2043 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
2045 #define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
2064 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_LSB 1
2066 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_MSB 1
2068 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_WIDTH 1
2070 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET_MSK 0x00000002
2072 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_CLR_MSK 0xfffffffd
2074 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_RESET 0x0
2076 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_GET(value) (((value) & 0x00000002) >> 1)
2078 #define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET(value) (((value) << 1) & 0x00000002)
2096 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_LSB 2
2098 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_MSB 2
2100 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_WIDTH 1
2102 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET_MSK 0x00000004
2104 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_CLR_MSK 0xfffffffb
2106 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_RESET 0x0
2108 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_GET(value) (((value) & 0x00000004) >> 2)
2110 #define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET(value) (((value) << 2) & 0x00000004)
2112 #ifndef __ASSEMBLY__
2123 struct ALT_ECC_HMC_OCP_ERRINTENR_s
2125 uint32_t SERRINTR : 1;
2126 uint32_t DERRINTR : 1;
2127 uint32_t HMI_INTRR : 1;
2132 typedef volatile struct ALT_ECC_HMC_OCP_ERRINTENR_s ALT_ECC_HMC_OCP_ERRINTENR_t;
2136 #define ALT_ECC_HMC_OCP_ERRINTENR_RESET 0x00000000
2138 #define ALT_ECC_HMC_OCP_ERRINTENR_OFST 0x118
2172 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_LSB 0
2174 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_MSB 0
2176 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_WIDTH 1
2178 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET_MSK 0x00000001
2180 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_CLR_MSK 0xfffffffe
2182 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_RESET 0x0
2184 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
2186 #define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
2204 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_LSB 8
2206 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_MSB 8
2208 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_WIDTH 1
2210 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET_MSK 0x00000100
2212 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_CLR_MSK 0xfffffeff
2214 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_RESET 0x0
2216 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_GET(value) (((value) & 0x00000100) >> 8)
2218 #define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET(value) (((value) << 8) & 0x00000100)
2236 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_LSB 16
2238 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_MSB 16
2240 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_WIDTH 1
2242 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK 0x00010000
2244 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
2246 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_RESET 0x0
2248 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
2250 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
2268 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_LSB 24
2270 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_MSB 24
2272 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_WIDTH 1
2274 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET_MSK 0x01000000
2276 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_CLR_MSK 0xfeffffff
2278 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_RESET 0x0
2280 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_GET(value) (((value) & 0x01000000) >> 24)
2282 #define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET(value) (((value) << 24) & 0x01000000)
2284 #ifndef __ASSEMBLY__
2295 struct ALT_ECC_HMC_OCP_INTMOD_s
2297 uint32_t INTMODE : 1;
2299 uint32_t EXT_ADDRPARITY_EN : 1;
2301 uint32_t INTONCMP : 1;
2303 uint32_t AFICAL_EN : 1;
2308 typedef volatile struct ALT_ECC_HMC_OCP_INTMOD_s ALT_ECC_HMC_OCP_INTMOD_t;
2312 #define ALT_ECC_HMC_OCP_INTMOD_RESET 0x00000000
2314 #define ALT_ECC_HMC_OCP_INTMOD_OFST 0x11c
2351 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_LSB 0
2353 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_MSB 0
2355 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_WIDTH 1
2357 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001
2359 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
2361 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_RESET 0x0
2363 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
2365 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
2383 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_LSB 1
2385 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_MSB 1
2387 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_WIDTH 1
2389 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002
2391 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd
2393 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_RESET 0x0
2395 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1)
2397 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002)
2415 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_LSB 2
2417 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_MSB 2
2419 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_WIDTH 1
2421 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET_MSK 0x00000004
2423 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb
2425 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_RESET 0x0
2427 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2)
2429 #define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004)
2452 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_LSB 16
2454 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_MSB 16
2456 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_WIDTH 1
2458 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000
2460 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff
2462 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_RESET 0x0
2464 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16)
2466 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000)
2485 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_LSB 17
2487 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_MSB 17
2489 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_WIDTH 1
2491 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000
2493 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff
2495 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_RESET 0x0
2497 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17)
2499 #define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000)
2519 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_LSB 18
2521 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_MSB 18
2523 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_WIDTH 1
2525 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000
2527 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff
2529 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_RESET 0x0
2531 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18)
2533 #define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000)
2535 #ifndef __ASSEMBLY__
2546 struct ALT_ECC_HMC_OCP_INTSTAT_s
2548 uint32_t SERRPENA : 1;
2549 uint32_t DERRPENA : 1;
2550 uint32_t HMI_PENA : 1;
2552 uint32_t ADDRMTCFLG : 1;
2553 uint32_t ADDRPARFLG : 1;
2554 uint32_t DERRBUSFLG : 1;
2559 typedef volatile struct ALT_ECC_HMC_OCP_INTSTAT_s ALT_ECC_HMC_OCP_INTSTAT_t;
2563 #define ALT_ECC_HMC_OCP_INTSTAT_RESET 0x00000000
2565 #define ALT_ECC_HMC_OCP_INTSTAT_OFST 0x120
2601 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_LSB 0
2603 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_MSB 0
2605 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_WIDTH 1
2607 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET_MSK 0x00000001
2609 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_CLR_MSK 0xfffffffe
2611 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_RESET 0x0
2613 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
2615 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
2635 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_LSB 8
2637 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_MSB 8
2639 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_WIDTH 1
2641 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET_MSK 0x00000100
2643 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_CLR_MSK 0xfffffeff
2645 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_RESET 0x0
2647 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
2649 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
2670 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_LSB 16
2672 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_MSB 16
2674 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_WIDTH 1
2676 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET_MSK 0x00010000
2678 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_CLR_MSK 0xfffeffff
2680 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_RESET 0x0
2682 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_GET(value) (((value) & 0x00010000) >> 16)
2684 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET(value) (((value) << 16) & 0x00010000)
2704 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_LSB 24
2706 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_MSB 24
2708 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_WIDTH 1
2710 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET_MSK 0x01000000
2712 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_CLR_MSK 0xfeffffff
2714 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_RESET 0x0
2716 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_GET(value) (((value) & 0x01000000) >> 24)
2718 #define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET(value) (((value) << 24) & 0x01000000)
2720 #ifndef __ASSEMBLY__
2731 struct ALT_ECC_HMC_OCP_DIAGINTTEST_s
2733 uint32_t TSERRA : 1;
2735 uint32_t TDERRA : 1;
2737 uint32_t TADDRMTC : 1;
2739 uint32_t TADDRPAR : 1;
2744 typedef volatile struct ALT_ECC_HMC_OCP_DIAGINTTEST_s ALT_ECC_HMC_OCP_DIAGINTTEST_t;
2748 #define ALT_ECC_HMC_OCP_DIAGINTTEST_RESET 0x00000000
2750 #define ALT_ECC_HMC_OCP_DIAGINTTEST_OFST 0x124
2789 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_LSB 0
2791 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_MSB 0
2793 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_WIDTH 1
2795 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET_MSK 0x00000001
2797 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
2799 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_RESET 0x0
2801 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
2803 #define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
2830 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_LSB 8
2832 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_MSB 8
2834 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_WIDTH 1
2836 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET_MSK 0x00000100
2838 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_CLR_MSK 0xfffffeff
2840 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_RESET 0x0
2842 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_GET(value) (((value) & 0x00000100) >> 8)
2844 #define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET(value) (((value) << 8) & 0x00000100)
2846 #ifndef __ASSEMBLY__
2857 struct ALT_ECC_HMC_OCP_MODSTAT_s
2859 uint32_t CMPFLGA : 1;
2861 uint32_t AUTOWB_DROP_FLG : 1;
2866 typedef volatile struct ALT_ECC_HMC_OCP_MODSTAT_s ALT_ECC_HMC_OCP_MODSTAT_t;
2870 #define ALT_ECC_HMC_OCP_MODSTAT_RESET 0x00000000
2872 #define ALT_ECC_HMC_OCP_MODSTAT_OFST 0x128
2901 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_LSB 0
2903 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_MSB 31
2905 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_WIDTH 32
2907 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET_MSK 0xffffffff
2909 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_CLR_MSK 0x00000000
2911 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_RESET 0x0
2913 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_GET(value) (((value) & 0xffffffff) >> 0)
2915 #define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET(value) (((value) << 0) & 0xffffffff)
2917 #ifndef __ASSEMBLY__
2928 struct ALT_ECC_HMC_OCP_DERRADDRA_s
2930 uint32_t DADDRESS : 32;
2934 typedef volatile struct ALT_ECC_HMC_OCP_DERRADDRA_s ALT_ECC_HMC_OCP_DERRADDRA_t;
2938 #define ALT_ECC_HMC_OCP_DERRADDRA_RESET 0x00000000
2940 #define ALT_ECC_HMC_OCP_DERRADDRA_OFST 0x12c
2967 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_LSB 0
2969 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_MSB 31
2971 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_WIDTH 32
2973 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET_MSK 0xffffffff
2975 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_CLR_MSK 0x00000000
2977 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_RESET 0x0
2979 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_GET(value) (((value) & 0xffffffff) >> 0)
2981 #define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET(value) (((value) << 0) & 0xffffffff)
2983 #ifndef __ASSEMBLY__
2994 struct ALT_ECC_HMC_OCP_SERRADDRA_s
2996 uint32_t SADDRESS : 32;
3000 typedef volatile struct ALT_ECC_HMC_OCP_SERRADDRA_s ALT_ECC_HMC_OCP_SERRADDRA_t;
3004 #define ALT_ECC_HMC_OCP_SERRADDRA_RESET 0x00000000
3006 #define ALT_ECC_HMC_OCP_SERRADDRA_OFST 0x130
3033 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_LSB 0
3035 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_MSB 31
3037 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_WIDTH 32
3039 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET_MSK 0xffffffff
3041 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_CLR_MSK 0x00000000
3043 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_RESET 0x0
3045 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_GET(value) (((value) & 0xffffffff) >> 0)
3047 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET(value) (((value) << 0) & 0xffffffff)
3049 #ifndef __ASSEMBLY__
3060 struct ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s
3062 uint32_t SWBADDRESS : 32;
3066 typedef volatile struct ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t;
3070 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_RESET 0x00000000
3072 #define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_OFST 0x138
3107 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_LSB 0
3109 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_MSB 31
3111 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_WIDTH 32
3113 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
3115 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
3117 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_RESET 0x0
3119 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
3121 #define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
3123 #ifndef __ASSEMBLY__
3134 struct ALT_ECC_HMC_OCP_SERRCNTREG_s
3136 uint32_t SERRCNT : 32;
3140 typedef volatile struct ALT_ECC_HMC_OCP_SERRCNTREG_s ALT_ECC_HMC_OCP_SERRCNTREG_t;
3144 #define ALT_ECC_HMC_OCP_SERRCNTREG_RESET 0x00000000
3146 #define ALT_ECC_HMC_OCP_SERRCNTREG_OFST 0x13c
3181 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_LSB 0
3183 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_MSB 31
3185 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_WIDTH 32
3187 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET_MSK 0xffffffff
3189 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_CLR_MSK 0x00000000
3191 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_RESET 0x1
3193 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_GET(value) (((value) & 0xffffffff) >> 0)
3195 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET(value) (((value) << 0) & 0xffffffff)
3197 #ifndef __ASSEMBLY__
3208 struct ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s
3214 typedef volatile struct ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t;
3218 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_RESET 0x00000001
3220 #define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_OFST 0x140
3246 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_LSB 0
3248 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_MSB 7
3250 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_WIDTH 8
3252 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3254 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3256 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_RESET 0x0
3258 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3260 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3271 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_LSB 8
3273 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_MSB 15
3275 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_WIDTH 8
3277 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3279 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3281 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_RESET 0x0
3283 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3285 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3296 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_LSB 16
3298 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_MSB 23
3300 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_WIDTH 8
3302 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3304 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3306 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_RESET 0x0
3308 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3310 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3321 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_LSB 24
3323 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_MSB 31
3325 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_WIDTH 8
3327 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3329 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3331 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_RESET 0x0
3333 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3335 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3337 #ifndef __ASSEMBLY__
3348 struct ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s
3350 uint32_t ECC0BUS : 8;
3351 uint32_t ECC1BUS : 8;
3352 uint32_t ECC2BUS : 8;
3353 uint32_t ECC3BUS : 8;
3357 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t;
3361 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_RESET 0x00000000
3363 #define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_OFST 0x144
3392 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_LSB 0
3394 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_MSB 7
3396 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_WIDTH 8
3398 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET_MSK 0x000000ff
3400 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_CLR_MSK 0xffffff00
3402 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_RESET 0x0
3404 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3406 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3420 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_LSB 8
3422 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_MSB 15
3424 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_WIDTH 8
3426 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET_MSK 0x0000ff00
3428 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_CLR_MSK 0xffff00ff
3430 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_RESET 0x0
3432 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3434 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3448 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_LSB 16
3450 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_MSB 23
3452 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_WIDTH 8
3454 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET_MSK 0x00ff0000
3456 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_CLR_MSK 0xff00ffff
3458 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_RESET 0x0
3460 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3462 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3476 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_LSB 24
3478 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_MSB 31
3480 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_WIDTH 8
3482 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET_MSK 0xff000000
3484 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_CLR_MSK 0x00ffffff
3486 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_RESET 0x0
3488 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3490 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3492 #ifndef __ASSEMBLY__
3503 struct ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s
3505 uint32_t ECC0BUS : 8;
3506 uint32_t ECC1BUS : 8;
3507 uint32_t ECC2BUS : 8;
3508 uint32_t ECC3BUS : 8;
3512 typedef volatile struct ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t;
3516 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_RESET 0x00000000
3518 #define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_OFST 0x148
3547 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0
3549 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7
3551 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8
3553 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3555 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3557 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0
3559 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3561 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3576 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8
3578 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15
3580 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8
3582 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3584 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3586 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0
3588 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3590 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3605 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16
3607 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23
3609 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8
3611 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3613 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3615 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0
3617 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3619 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3634 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24
3636 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31
3638 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8
3640 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3642 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3644 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0
3646 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3648 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3650 #ifndef __ASSEMBLY__
3661 struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s
3663 uint32_t ECC0BUS : 8;
3664 uint32_t ECC1BUS : 8;
3665 uint32_t ECC2BUS : 8;
3666 uint32_t ECC3BUS : 8;
3670 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t;
3674 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_RESET 0x00000000
3676 #define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_OFST 0x14c
3711 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_LSB 0
3713 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_MSB 0
3715 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_WIDTH 1
3717 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001
3719 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe
3721 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_RESET 0x0
3723 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0)
3725 #define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001)
3746 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_LSB 1
3748 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_MSB 1
3750 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_WIDTH 1
3752 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002
3754 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd
3756 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_RESET 0x0
3758 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1)
3760 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002)
3777 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_LSB 16
3779 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_MSB 16
3781 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_WIDTH 1
3783 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000
3785 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff
3787 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_RESET 0x0
3789 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16)
3791 #define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000)
3793 #ifndef __ASSEMBLY__
3804 struct ALT_ECC_HMC_OCP_ECC_DIAGON_s
3806 uint32_t WRDIAGON : 1;
3807 uint32_t RDDIAGON : 1;
3809 uint32_t ECCDIAGON : 1;
3814 typedef volatile struct ALT_ECC_HMC_OCP_ECC_DIAGON_s ALT_ECC_HMC_OCP_ECC_DIAGON_t;
3818 #define ALT_ECC_HMC_OCP_ECC_DIAGON_RESET 0x00000000
3820 #define ALT_ECC_HMC_OCP_ECC_DIAGON_OFST 0x150
3864 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_LSB 0
3866 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_MSB 0
3868 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_WIDTH 1
3870 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK 0x00000001
3872 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
3874 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_RESET 0x0
3876 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
3878 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
3898 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_LSB 1
3900 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_MSB 1
3902 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_WIDTH 1
3904 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK 0x00000002
3906 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
3908 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_RESET 0x0
3910 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
3912 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
3932 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_LSB 2
3934 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_MSB 2
3936 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_WIDTH 1
3938 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK 0x00000004
3940 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
3942 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_RESET 0x0
3944 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
3946 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
3966 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_LSB 3
3968 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_MSB 3
3970 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_WIDTH 1
3972 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK 0x00000008
3974 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
3976 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_RESET 0x0
3978 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
3980 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
4000 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_LSB 4
4002 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_MSB 4
4004 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH 1
4006 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK 0x00000010
4008 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK 0xffffffef
4010 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_RESET 0x0
4012 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_GET(value) (((value) & 0x00000010) >> 4)
4014 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET(value) (((value) << 4) & 0x00000010)
4034 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_LSB 5
4036 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_MSB 5
4038 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH 1
4040 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK 0x00000020
4042 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK 0xffffffdf
4044 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_RESET 0x0
4046 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_GET(value) (((value) & 0x00000020) >> 5)
4048 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET(value) (((value) << 5) & 0x00000020)
4068 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_LSB 6
4070 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_MSB 6
4072 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH 1
4074 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK 0x00000040
4076 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK 0xffffffbf
4078 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_RESET 0x0
4080 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_GET(value) (((value) & 0x00000040) >> 6)
4082 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET(value) (((value) << 6) & 0x00000040)
4102 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_LSB 7
4104 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_MSB 7
4106 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH 1
4108 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK 0x00000080
4110 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK 0xffffff7f
4112 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_RESET 0x0
4114 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_GET(value) (((value) & 0x00000080) >> 7)
4116 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET(value) (((value) << 7) & 0x00000080)
4136 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_LSB 8
4138 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_MSB 8
4140 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_WIDTH 1
4142 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK 0x00000100
4144 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
4146 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_RESET 0x0
4148 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
4150 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
4170 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_LSB 9
4172 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_MSB 9
4174 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_WIDTH 1
4176 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK 0x00000200
4178 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
4180 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_RESET 0x0
4182 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
4184 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
4204 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_LSB 10
4206 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_MSB 10
4208 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_WIDTH 1
4210 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK 0x00000400
4212 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
4214 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_RESET 0x0
4216 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
4218 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
4238 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_LSB 11
4240 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_MSB 11
4242 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_WIDTH 1
4244 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK 0x00000800
4246 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
4248 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_RESET 0x0
4250 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
4252 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
4254 #ifndef __ASSEMBLY__
4265 struct ALT_ECC_HMC_OCP_ECC_DECSTAT_s
4267 uint32_t DEC0SERRFLG : 1;
4268 uint32_t DEC1SERRFLG : 1;
4269 uint32_t DEC2SERRFLG : 1;
4270 uint32_t DEC3SERRFLG : 1;
4271 uint32_t DEC0ADDRFLG : 1;
4272 uint32_t DEC1ADDRFLG : 1;
4273 uint32_t DEC2ADDRFLG : 1;
4274 uint32_t DEC3ADDRFLG : 1;
4275 uint32_t DEC0DERRFLG : 1;
4276 uint32_t DEC1DERRFLG : 1;
4277 uint32_t DEC2DERRFLG : 1;
4278 uint32_t DEC3DERRFLG : 1;
4283 typedef volatile struct ALT_ECC_HMC_OCP_ECC_DECSTAT_s ALT_ECC_HMC_OCP_ECC_DECSTAT_t;
4287 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_RESET 0x00000000
4289 #define ALT_ECC_HMC_OCP_ECC_DECSTAT_OFST 0x154
4315 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_LSB 0
4317 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_MSB 31
4319 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_WIDTH 32
4321 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET_MSK 0xffffffff
4323 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_CLR_MSK 0x00000000
4325 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_RESET 0x0
4327 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4329 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4331 #ifndef __ASSEMBLY__
4342 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s
4348 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t;
4352 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_RESET 0x00000000
4354 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_OFST 0x160
4380 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_LSB 0
4382 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_MSB 31
4384 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_WIDTH 32
4386 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET_MSK 0xffffffff
4388 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_CLR_MSK 0x00000000
4390 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_RESET 0x0
4392 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4394 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4396 #ifndef __ASSEMBLY__
4407 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s
4413 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t;
4417 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_RESET 0x00000000
4419 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_OFST 0x164
4445 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_LSB 0
4447 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_MSB 31
4449 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_WIDTH 32
4451 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET_MSK 0xffffffff
4453 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_CLR_MSK 0x00000000
4455 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_RESET 0x0
4457 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4459 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4461 #ifndef __ASSEMBLY__
4472 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s
4478 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t;
4482 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_RESET 0x00000000
4484 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_OFST 0x168
4510 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_LSB 0
4512 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_MSB 31
4514 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_WIDTH 32
4516 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET_MSK 0xffffffff
4518 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_CLR_MSK 0x00000000
4520 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_RESET 0x0
4522 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4524 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4526 #ifndef __ASSEMBLY__
4537 struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s
4543 typedef volatile struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t;
4547 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_RESET 0x00000000
4549 #define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_OFST 0x16c
4575 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_LSB 0
4577 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_MSB 7
4579 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_WIDTH 8
4581 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET_MSK 0x000000ff
4583 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_CLR_MSK 0xffffff00
4585 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_RESET 0x0
4587 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4589 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4600 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_LSB 8
4602 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_MSB 15
4604 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_WIDTH 8
4606 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET_MSK 0x0000ff00
4608 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_CLR_MSK 0xffff00ff
4610 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_RESET 0x0
4612 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4614 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4625 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_LSB 16
4627 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_MSB 23
4629 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_WIDTH 8
4631 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET_MSK 0x00ff0000
4633 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_CLR_MSK 0xff00ffff
4635 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_RESET 0x0
4637 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4639 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4650 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_LSB 24
4652 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_MSB 31
4654 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_WIDTH 8
4656 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET_MSK 0xff000000
4658 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_CLR_MSK 0x00ffffff
4660 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_RESET 0x0
4662 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4664 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4666 #ifndef __ASSEMBLY__
4677 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s
4679 uint32_t ECC0BUS : 8;
4680 uint32_t ECC1BUS : 8;
4681 uint32_t ECC2BUS : 8;
4682 uint32_t ECC3BUS : 8;
4686 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t;
4690 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_RESET 0x00000000
4692 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_OFST 0x170
4718 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_LSB 0
4720 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_MSB 7
4722 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_WIDTH 8
4724 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET_MSK 0x000000ff
4726 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_CLR_MSK 0xffffff00
4728 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_RESET 0x0
4730 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4732 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4743 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_LSB 8
4745 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_MSB 15
4747 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_WIDTH 8
4749 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET_MSK 0x0000ff00
4751 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_CLR_MSK 0xffff00ff
4753 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_RESET 0x0
4755 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4757 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4768 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_LSB 16
4770 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_MSB 23
4772 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_WIDTH 8
4774 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET_MSK 0x00ff0000
4776 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_CLR_MSK 0xff00ffff
4778 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_RESET 0x0
4780 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4782 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4793 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_LSB 24
4795 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_MSB 31
4797 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_WIDTH 8
4799 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET_MSK 0xff000000
4801 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_CLR_MSK 0x00ffffff
4803 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_RESET 0x0
4805 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4807 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4809 #ifndef __ASSEMBLY__
4820 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s
4822 uint32_t ECC0BUS : 8;
4823 uint32_t ECC1BUS : 8;
4824 uint32_t ECC2BUS : 8;
4825 uint32_t ECC3BUS : 8;
4829 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t;
4833 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_RESET 0x00000000
4835 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_OFST 0x174
4861 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_LSB 0
4863 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_MSB 7
4865 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_WIDTH 8
4867 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET_MSK 0x000000ff
4869 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_CLR_MSK 0xffffff00
4871 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_RESET 0x0
4873 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4875 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4886 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_LSB 8
4888 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_MSB 15
4890 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_WIDTH 8
4892 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET_MSK 0x0000ff00
4894 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_CLR_MSK 0xffff00ff
4896 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_RESET 0x0
4898 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4900 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4911 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_LSB 16
4913 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_MSB 23
4915 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_WIDTH 8
4917 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET_MSK 0x00ff0000
4919 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_CLR_MSK 0xff00ffff
4921 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_RESET 0x0
4923 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4925 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4936 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_LSB 24
4938 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_MSB 31
4940 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_WIDTH 8
4942 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET_MSK 0xff000000
4944 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_CLR_MSK 0x00ffffff
4946 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_RESET 0x0
4948 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4950 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4952 #ifndef __ASSEMBLY__
4963 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s
4965 uint32_t ECC0BUS : 8;
4966 uint32_t ECC1BUS : 8;
4967 uint32_t ECC2BUS : 8;
4968 uint32_t ECC3BUS : 8;
4972 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t;
4976 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_RESET 0x00000000
4978 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_OFST 0x178
5004 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_LSB 0
5006 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_MSB 7
5008 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_WIDTH 8
5010 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET_MSK 0x000000ff
5012 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_CLR_MSK 0xffffff00
5014 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_RESET 0x0
5016 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
5018 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
5029 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_LSB 8
5031 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_MSB 15
5033 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_WIDTH 8
5035 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET_MSK 0x0000ff00
5037 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_CLR_MSK 0xffff00ff
5039 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_RESET 0x0
5041 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
5043 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
5054 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_LSB 16
5056 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_MSB 23
5058 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_WIDTH 8
5060 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET_MSK 0x00ff0000
5062 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_CLR_MSK 0xff00ffff
5064 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_RESET 0x0
5066 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
5068 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
5079 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_LSB 24
5081 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_MSB 31
5083 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_WIDTH 8
5085 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET_MSK 0xff000000
5087 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_CLR_MSK 0x00ffffff
5089 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_RESET 0x0
5091 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
5093 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
5095 #ifndef __ASSEMBLY__
5106 struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s
5108 uint32_t ECC0BUS : 8;
5109 uint32_t ECC1BUS : 8;
5110 uint32_t ECC2BUS : 8;
5111 uint32_t ECC3BUS : 8;
5115 typedef volatile struct ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t;
5119 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_RESET 0x00000000
5121 #define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_OFST 0x17c
5123 #ifndef __ASSEMBLY__
5134 struct ALT_ECC_HMC_OCP_s
5136 ALT_ECC_HMC_OCP_IP_REV_ID_t IP_REV_ID;
5137 volatile uint32_t _pad_0x4_0x7;
5138 ALT_ECC_HMC_OCP_DDRIOCTL_t DDRIOCTRL;
5139 ALT_ECC_HMC_OCP_DDRCALSTAT_t DDRCALSTAT;
5140 ALT_ECC_HMC_OCP_MPR_0BEAT1_t MPR_0BEAT1;
5141 ALT_ECC_HMC_OCP_MPR_1BEAT1_t MPR_1BEAT1;
5142 ALT_ECC_HMC_OCP_MPR_2BEAT1_t MPR_2BEAT1;
5143 ALT_ECC_HMC_OCP_MPR_3BEAT1_t MPR_3BEAT1;
5144 ALT_ECC_HMC_OCP_MPR_4BEAT1_t MPR_4BEAT1;
5145 ALT_ECC_HMC_OCP_MPR_5BEAT1_t MPR_5BEAT1;
5146 ALT_ECC_HMC_OCP_MPR_6BEAT1_t MPR_6BEAT1;
5147 ALT_ECC_HMC_OCP_MPR_7BEAT1_t MPR_7BEAT1;
5148 ALT_ECC_HMC_OCP_MPR_8BEAT1_t MPR_8BEAT1;
5149 ALT_ECC_HMC_OCP_MPR_0BEAT2_t MPR_0BEAT2;
5150 ALT_ECC_HMC_OCP_MPR_1BEAT2_t MPR_1BEAT2;
5151 ALT_ECC_HMC_OCP_MPR_2BEAT2_t MPR_2BEAT2;
5152 ALT_ECC_HMC_OCP_MPR_3BEAT2_t MPR_3BEAT2;
5153 ALT_ECC_HMC_OCP_MPR_4BEAT2_t MPR_4BEAT2;
5154 ALT_ECC_HMC_OCP_MPR_5BEAT2_t MPR_5BEAT2;
5155 ALT_ECC_HMC_OCP_MPR_6BEAT2_t MPR_6BEAT2;
5156 ALT_ECC_HMC_OCP_MPR_7BEAT2_t MPR_7BEAT2;
5157 ALT_ECC_HMC_OCP_MPR_8BEAT2_t MPR_8BEAT2;
5158 volatile uint32_t _pad_0x58_0x5f[2];
5159 ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t AUTO_PRECHARGE;
5160 volatile uint32_t _pad_0x64_0xff[39];
5161 ALT_ECC_HMC_OCP_ECCCTL1_t ECCCTRL1;
5162 ALT_ECC_HMC_OCP_ECCCTL2_t ECCCTRL2;
5163 volatile uint32_t _pad_0x108_0x10f[2];
5164 ALT_ECC_HMC_OCP_ERRINTEN_t ERRINTEN;
5165 ALT_ECC_HMC_OCP_ERRINTENS_t ERRINTENS;
5166 ALT_ECC_HMC_OCP_ERRINTENR_t ERRINTENR;
5167 ALT_ECC_HMC_OCP_INTMOD_t INTMODE;
5168 ALT_ECC_HMC_OCP_INTSTAT_t INTSTAT;
5169 ALT_ECC_HMC_OCP_DIAGINTTEST_t DIAGINTTEST;
5170 ALT_ECC_HMC_OCP_MODSTAT_t MODSTAT;
5171 ALT_ECC_HMC_OCP_DERRADDRA_t DERRADDRA;
5172 ALT_ECC_HMC_OCP_SERRADDRA_t SERRADDRA;
5173 volatile uint32_t _pad_0x134_0x137;
5174 ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t AUTOWB_CORRADDR;
5175 ALT_ECC_HMC_OCP_SERRCNTREG_t SERRCNTREG;
5176 ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t AUTOWB_DROP_CNTREG;
5177 ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t ECC_REG2WRECCDATABUS;
5178 ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t ECC_RDECCDATA2REGBUS;
5179 ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t ECC_REG2RDECCDATABUS;
5180 ALT_ECC_HMC_OCP_ECC_DIAGON_t ECC_DIAGON;
5181 ALT_ECC_HMC_OCP_ECC_DECSTAT_t ECC_DECSTAT;
5182 volatile uint32_t _pad_0x158_0x15f[2];
5183 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t ECC_ERRGENADDR_0;
5184 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t ECC_ERRGENADDR_1;
5185 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t ECC_ERRGENADDR_2;
5186 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t ECC_ERRGENADDR_3;
5187 ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t ECC_REG2RDDATABUS_BEAT0;
5188 ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t ECC_REG2RDDATABUS_BEAT1;
5189 ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t ECC_REG2RDDATABUS_BEAT2;
5190 ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t ECC_REG2RDDATABUS_BEAT3;
5191 volatile uint32_t _pad_0x180_0x500[224];
5195 typedef volatile struct ALT_ECC_HMC_OCP_s ALT_ECC_HMC_OCP_t;
5197 struct ALT_ECC_HMC_OCP_raw_s
5199 volatile uint32_t IP_REV_ID;
5200 uint32_t _pad_0x4_0x7;
5201 volatile uint32_t DDRIOCTRL;
5202 volatile uint32_t DDRCALSTAT;
5203 volatile uint32_t MPR_0BEAT1;
5204 volatile uint32_t MPR_1BEAT1;
5205 volatile uint32_t MPR_2BEAT1;
5206 volatile uint32_t MPR_3BEAT1;
5207 volatile uint32_t MPR_4BEAT1;
5208 volatile uint32_t MPR_5BEAT1;
5209 volatile uint32_t MPR_6BEAT1;
5210 volatile uint32_t MPR_7BEAT1;
5211 volatile uint32_t MPR_8BEAT1;
5212 volatile uint32_t MPR_0BEAT2;
5213 volatile uint32_t MPR_1BEAT2;
5214 volatile uint32_t MPR_2BEAT2;
5215 volatile uint32_t MPR_3BEAT2;
5216 volatile uint32_t MPR_4BEAT2;
5217 volatile uint32_t MPR_5BEAT2;
5218 volatile uint32_t MPR_6BEAT2;
5219 volatile uint32_t MPR_7BEAT2;
5220 volatile uint32_t MPR_8BEAT2;
5221 uint32_t _pad_0x58_0x5f[2];
5222 volatile uint32_t AUTO_PRECHARGE;
5223 uint32_t _pad_0x64_0xff[39];
5224 volatile uint32_t ECCCTRL1;
5225 volatile uint32_t ECCCTRL2;
5226 uint32_t _pad_0x108_0x10f[2];
5227 volatile uint32_t ERRINTEN;
5228 volatile uint32_t ERRINTENS;
5229 volatile uint32_t ERRINTENR;
5230 volatile uint32_t INTMODE;
5231 volatile uint32_t INTSTAT;
5232 volatile uint32_t DIAGINTTEST;
5233 volatile uint32_t MODSTAT;
5234 volatile uint32_t DERRADDRA;
5235 volatile uint32_t SERRADDRA;
5236 uint32_t _pad_0x134_0x137;
5237 volatile uint32_t AUTOWB_CORRADDR;
5238 volatile uint32_t SERRCNTREG;
5239 volatile uint32_t AUTOWB_DROP_CNTREG;
5240 volatile uint32_t ECC_REG2WRECCDATABUS;
5241 volatile uint32_t ECC_RDECCDATA2REGBUS;
5242 volatile uint32_t ECC_REG2RDECCDATABUS;
5243 volatile uint32_t ECC_DIAGON;
5244 volatile uint32_t ECC_DECSTAT;
5245 uint32_t _pad_0x158_0x15f[2];
5246 volatile uint32_t ECC_ERRGENADDR_0;
5247 volatile uint32_t ECC_ERRGENADDR_1;
5248 volatile uint32_t ECC_ERRGENADDR_2;
5249 volatile uint32_t ECC_ERRGENADDR_3;
5250 volatile uint32_t ECC_REG2RDDATABUS_BEAT0;
5251 volatile uint32_t ECC_REG2RDDATABUS_BEAT1;
5252 volatile uint32_t ECC_REG2RDDATABUS_BEAT2;
5253 volatile uint32_t ECC_REG2RDDATABUS_BEAT3;
5254 uint32_t _pad_0x180_0x500[224];
5258 typedef volatile struct ALT_ECC_HMC_OCP_raw_s ALT_ECC_HMC_OCP_raw_t;