Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_clock_manager.h
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1 /******************************************************************************
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31 ******************************************************************************/
32 
33 /*
34  * $Id: //acds/rel/20.1std/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_clock_manager.h#1 $
35  */
36 
42 #ifndef __ALT_CLK_MGR_H__
43 #define __ALT_CLK_MGR_H__
44 
45 #include "hwlib.h"
46 #include "alt_clock_group.h"
47 
48 #ifdef __cplusplus
49 extern "C"
50 {
51 #endif /* __cplusplus */
52 
61 /******************************************************************************/
66 typedef uint32_t alt_freq_t;
67 
68 /******************************************************************************/
73 typedef enum ALT_CLK_e
74 {
75  /* Clock Input Pins */
98  /* FPGA Clock Sources External to HPS */
99  ALT_CLK_F2H_PERIPH_REF,
100  /*<! Alternate clock source from FPGA
101  * for HPS Peripheral PLL. */
102 
103  ALT_CLK_F2H_SDRAM_REF,
104  /*<! Alternate clock source from FPGA
105  * for HPS SDRAM PLL. */
106 
107 
108  /* Other Clock Sources External to HPS */
142  /* PLLs */
165  /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
166  * directly from the osc_clk_1_HPS pin */
177  /* Main Clock Group - The following clocks are derived from the Main PLL. */
305  /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
396  /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
442  /* Clock Output Pins */
503  ALT_CLK_UNKNOWN
504 } ALT_CLK_t;
505 
506 /******************************************************************************/
514 /******************************************************************************/
521 {
522  ALT_MAIN_PLL_LOCK_ACHV = 0x00000001,
532  ALT_SDR_PLL_LOCK_ACHV = 0x00000004,
537  ALT_MAIN_PLL_LOCK_LOST = 0x00000008,
547  ALT_SDR_PLL_LOCK_LOST = 0x00000020
553 
554 /******************************************************************************/
573 ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
574 
575 /******************************************************************************/
585 uint32_t alt_clk_lock_status_get(void);
586 
587 /******************************************************************************/
608 ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
609 
612 /******************************************************************************/
650 /******************************************************************************/
656 {
668 
669 /******************************************************************************/
679 ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
680 
681 /******************************************************************************/
692 
695 /******************************************************************************/
719 /******************************************************************************/
732 ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
733 
734 /******************************************************************************/
753 ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
754  bool use_input_mux);
755 
756 /******************************************************************************/
774 ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
775 
778 /******************************************************************************/
823 /******************************************************************************/
838 ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
839 
840 /******************************************************************************/
853 ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
854 
855 /******************************************************************************/
867 ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
868 
871 /******************************************************************************/
918 /******************************************************************************/
935 ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
936 
937 /******************************************************************************/
957 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
958  ALT_CLK_t ref_clk);
959 
962 /******************************************************************************/
971 /******************************************************************************/
998 ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
999  alt_freq_t freq);
1000 
1001 /******************************************************************************/
1019 alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
1020 
1021 /******************************************************************************/
1026 typedef struct ALT_CLK_PLL_CFG_s
1027 {
1028  ALT_CLK_t ref_clk;
1029  uint32_t mult;
1032  uint32_t div;
1035  uint32_t cntrs[6];
1038  uint32_t pshift[6];
1043 
1044 /******************************************************************************/
1058 ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
1059  ALT_CLK_PLL_CFG_t* pll_cfg);
1060 
1061 /******************************************************************************/
1076 ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
1077  const ALT_CLK_PLL_CFG_t* pll_cfg);
1078 
1079 /******************************************************************************/
1097 ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
1098  uint32_t* mult,
1099  uint32_t* div);
1100 
1101 /******************************************************************************/
1118 ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
1119  uint32_t mult,
1120  uint32_t div);
1121 
1122 /******************************************************************************/
1140 ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
1141  alt_freq_t* freq);
1142 
1143 /******************************************************************************/
1152 uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
1153 
1154 /******************************************************************************/
1184 ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
1185  uint32_t guard_band);
1186 
1187 /******************************************************************************/
1210 ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
1211  uint32_t* div);
1212 
1213 /******************************************************************************/
1238 ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
1239  uint32_t div);
1240 
1241 /******************************************************************************/
1259 ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
1260  alt_freq_t* freq);
1261 
1264 /******************************************************************************/
1309 /******************************************************************************/
1331 ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1332 
1333 /******************************************************************************/
1355 ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1356 
1359 /******************************************************************************/
1390 /******************************************************************************/
1409 ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
1410  ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1411 
1412 /******************************************************************************/
1431 ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1432 
1433 /******************************************************************************/
1443 ALT_STATUS_CODE alt_clk_clkmgr_init(void);
1444 
1445 /******************************************************************************/
1453 ALT_STATUS_CODE alt_clk_clkmgr_uninit(void);
1457 #ifdef __cplusplus
1458 }
1459 
1460 #endif /* __cplusplus */
1461 #endif /* __ALT_CLK_MGR_H__ */