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alt_spis.h
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32 
33 /* Altera - ALT_SPIS */
34 
35 #ifndef __ALT_SOCAL_SPIS_H__
36 #define __ALT_SOCAL_SPIS_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SPIS
50  *
51  */
52 /*
53  * Register : Control Register 0 - CTRLR0
54  *
55  * Control Register 0:
56  *
57  * This register controls the serial data transfer. It is impossible to
58  *
59  * write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
60  *
61  * is enabled and disabled by writing to the SSIENR register.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :--------|:-------|:------|:----------------------------
67  * [3:0] | R | 0x0 | ALT_SPIS_CTRLR0_DFS
68  * [5:4] | RW | 0x0 | ALT_SPIS_CTRLR0_FRF
69  * [6] | RW | 0x0 | ALT_SPIS_CTRLR0_SCPH
70  * [7] | RW | 0x0 | ALT_SPIS_CTRLR0_SCPOL
71  * [9:8] | RW | 0x0 | ALT_SPIS_CTRLR0_TMOD
72  * [10] | RW | 0x0 | ALT_SPIS_CTRLR0_SLV_OE
73  * [11] | RW | 0x0 | ALT_SPIS_CTRLR0_SRL
74  * [15:12] | RW | 0x0 | ALT_SPIS_CTRLR0_CFS
75  * [20:16] | RW | 0x7 | ALT_SPIS_CTRLR0_DFS_32
76  * [22:21] | R | 0x0 | ALT_SPIS_CTRLR0_SPI_FRF
77  * [31:23] | R | 0x0 | ALT_SPIS_CTRLR0_RSVD_CTRLR0
78  *
79  */
80 /*
81  * Field : DFS
82  *
83  * Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is
84  *
85  * configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this
86  * field
87  *
88  * will not have any effect.
89  *
90  * Selects the data frame length. When the data frame size is programmed to be less
91  * than
92  *
93  * 16 bits, the receive data are automatically right-justified by the receive
94  * logic, with the
95  *
96  * upper bits of the receive FIFO zero-padded.
97  *
98  * You must right-justify transmit data before writing into the transmit FIFO. The
99  * transmit
100  *
101  * logic ignores the upper unused bits when transmitting the data
102  *
103  * Note: When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode
104  * and SPI_FRF is not set to 2'b00.
105  *
106  * DFS value should be multiple of 2 if SPI_FRF = 01, and
107  *
108  * DFS value should be multiple of 4 if SPI_FRF = 10.
109  *
110  * Field Enumeration Values:
111  *
112  * Enum | Value | Description
113  * :-----------------------------------|:------|:----------------------------
114  * ALT_SPIS_CTRLR0_DFS_E_FRAME_04BITS | 0x3 | 04-bit serial data transfer
115  * ALT_SPIS_CTRLR0_DFS_E_FRAME_05BITS | 0x4 | 05-bit serial data transfer
116  * ALT_SPIS_CTRLR0_DFS_E_FRAME_06BITS | 0x5 | 06-bit serial data transfer
117  * ALT_SPIS_CTRLR0_DFS_E_FRAME_07BITS | 0x6 | 07-bit serial data transfer
118  * ALT_SPIS_CTRLR0_DFS_E_FRAME_08BITS | 0x7 | 08-bit serial data transfer
119  * ALT_SPIS_CTRLR0_DFS_E_FRAME_09BITS | 0x8 | 09-bit serial data transfer
120  * ALT_SPIS_CTRLR0_DFS_E_FRAME_10BITS | 0x9 | 10-bit serial data transfer
121  * ALT_SPIS_CTRLR0_DFS_E_FRAME_11BITS | 0xa | 11-bit serial data transfer
122  * ALT_SPIS_CTRLR0_DFS_E_FRAME_12BITS | 0xb | 12-bit serial data transfer
123  * ALT_SPIS_CTRLR0_DFS_E_FRAME_13BITS | 0xc | 13-bit serial data transfer
124  * ALT_SPIS_CTRLR0_DFS_E_FRAME_14BITS | 0xd | 14-bit serial data transfer
125  * ALT_SPIS_CTRLR0_DFS_E_FRAME_15BITS | 0xe | 15-bit serial data transfer
126  * ALT_SPIS_CTRLR0_DFS_E_FRAME_16BITS | 0xf | 16-bit serial data transfer
127  *
128  * Field Access Macros:
129  *
130  */
131 /*
132  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
133  *
134  * 04-bit serial data transfer
135  */
136 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_04BITS 0x3
137 /*
138  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
139  *
140  * 05-bit serial data transfer
141  */
142 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_05BITS 0x4
143 /*
144  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
145  *
146  * 06-bit serial data transfer
147  */
148 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_06BITS 0x5
149 /*
150  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
151  *
152  * 07-bit serial data transfer
153  */
154 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_07BITS 0x6
155 /*
156  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
157  *
158  * 08-bit serial data transfer
159  */
160 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_08BITS 0x7
161 /*
162  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
163  *
164  * 09-bit serial data transfer
165  */
166 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_09BITS 0x8
167 /*
168  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
169  *
170  * 10-bit serial data transfer
171  */
172 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_10BITS 0x9
173 /*
174  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
175  *
176  * 11-bit serial data transfer
177  */
178 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_11BITS 0xa
179 /*
180  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
181  *
182  * 12-bit serial data transfer
183  */
184 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_12BITS 0xb
185 /*
186  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
187  *
188  * 13-bit serial data transfer
189  */
190 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_13BITS 0xc
191 /*
192  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
193  *
194  * 14-bit serial data transfer
195  */
196 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_14BITS 0xd
197 /*
198  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
199  *
200  * 15-bit serial data transfer
201  */
202 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_15BITS 0xe
203 /*
204  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS
205  *
206  * 16-bit serial data transfer
207  */
208 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_16BITS 0xf
209 
210 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_DFS register field. */
211 #define ALT_SPIS_CTRLR0_DFS_LSB 0
212 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_DFS register field. */
213 #define ALT_SPIS_CTRLR0_DFS_MSB 3
214 /* The width in bits of the ALT_SPIS_CTRLR0_DFS register field. */
215 #define ALT_SPIS_CTRLR0_DFS_WIDTH 4
216 /* The mask used to set the ALT_SPIS_CTRLR0_DFS register field value. */
217 #define ALT_SPIS_CTRLR0_DFS_SET_MSK 0x0000000f
218 /* The mask used to clear the ALT_SPIS_CTRLR0_DFS register field value. */
219 #define ALT_SPIS_CTRLR0_DFS_CLR_MSK 0xfffffff0
220 /* The reset value of the ALT_SPIS_CTRLR0_DFS register field. */
221 #define ALT_SPIS_CTRLR0_DFS_RESET 0x0
222 /* Extracts the ALT_SPIS_CTRLR0_DFS field value from a register. */
223 #define ALT_SPIS_CTRLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
224 /* Produces a ALT_SPIS_CTRLR0_DFS register field value suitable for setting the register. */
225 #define ALT_SPIS_CTRLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
226 
227 /*
228  * Field : FRF
229  *
230  * Frame Format.
231  *
232  * Selects which serial protocol transfers the data.
233  *
234  * 00 - Motorola SPI
235  *
236  * 01 - Texas Instruments SSP
237  *
238  * 10 - National Semiconductors Microwire
239  *
240  * 11 - Reserved
241  *
242  * Field Enumeration Values:
243  *
244  * Enum | Value | Description
245  * :------------------------------------|:------|:-----------------------------------
246  * ALT_SPIS_CTRLR0_FRF_E_MOTOROLLA_SPI | 0x0 | Motorolla SPI Frame Format
247  * ALT_SPIS_CTRLR0_FRF_E_TEXAS_SSP | 0x1 | Texas Instruments SSP Frame Format
248  * ALT_SPIS_CTRLR0_FRF_E_NS_MICROWIRE | 0x2 | National Microwire Frame Format
249  *
250  * Field Access Macros:
251  *
252  */
253 /*
254  * Enumerated value for register field ALT_SPIS_CTRLR0_FRF
255  *
256  * Motorolla SPI Frame Format
257  */
258 #define ALT_SPIS_CTRLR0_FRF_E_MOTOROLLA_SPI 0x0
259 /*
260  * Enumerated value for register field ALT_SPIS_CTRLR0_FRF
261  *
262  * Texas Instruments SSP Frame Format
263  */
264 #define ALT_SPIS_CTRLR0_FRF_E_TEXAS_SSP 0x1
265 /*
266  * Enumerated value for register field ALT_SPIS_CTRLR0_FRF
267  *
268  * National Microwire Frame Format
269  */
270 #define ALT_SPIS_CTRLR0_FRF_E_NS_MICROWIRE 0x2
271 
272 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_FRF register field. */
273 #define ALT_SPIS_CTRLR0_FRF_LSB 4
274 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_FRF register field. */
275 #define ALT_SPIS_CTRLR0_FRF_MSB 5
276 /* The width in bits of the ALT_SPIS_CTRLR0_FRF register field. */
277 #define ALT_SPIS_CTRLR0_FRF_WIDTH 2
278 /* The mask used to set the ALT_SPIS_CTRLR0_FRF register field value. */
279 #define ALT_SPIS_CTRLR0_FRF_SET_MSK 0x00000030
280 /* The mask used to clear the ALT_SPIS_CTRLR0_FRF register field value. */
281 #define ALT_SPIS_CTRLR0_FRF_CLR_MSK 0xffffffcf
282 /* The reset value of the ALT_SPIS_CTRLR0_FRF register field. */
283 #define ALT_SPIS_CTRLR0_FRF_RESET 0x0
284 /* Extracts the ALT_SPIS_CTRLR0_FRF field value from a register. */
285 #define ALT_SPIS_CTRLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
286 /* Produces a ALT_SPIS_CTRLR0_FRF register field value suitable for setting the register. */
287 #define ALT_SPIS_CTRLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
288 
289 /*
290  * Field : SCPH
291  *
292  * Serial Clock Phase.
293  *
294  * Valid when the frame format (FRF) is set to Motorola SPI. The serial
295  *
296  * clock phase selects the relationship of the serial clock with the slave
297  *
298  * select signal. When SCPH = 0, data are captured on the first edge of
299  *
300  * the serial clock. When SCPH = 1, the serial clock starts toggling one
301  *
302  * cycle after the slave select line is activated, and data are captured
303  *
304  * on the second edge of the serial clock.
305  *
306  * 0: Serial clock toggles in middle of first data bit
307  *
308  * 1: Serial clock toggles at start of first data bit
309  *
310  * Field Enumeration Values:
311  *
312  * Enum | Value | Description
313  * :----------------------------------|:------|:-------------------------------------
314  * ALT_SPIS_CTRLR0_SCPH_E_MIDDLE_BIT | 0x0 | Clock toggles in middle of first bit
315  * ALT_SPIS_CTRLR0_SCPH_E_START_BIT | 0x1 | Clock toggles at start of first bit
316  *
317  * Field Access Macros:
318  *
319  */
320 /*
321  * Enumerated value for register field ALT_SPIS_CTRLR0_SCPH
322  *
323  * Clock toggles in middle of first bit
324  */
325 #define ALT_SPIS_CTRLR0_SCPH_E_MIDDLE_BIT 0x0
326 /*
327  * Enumerated value for register field ALT_SPIS_CTRLR0_SCPH
328  *
329  * Clock toggles at start of first bit
330  */
331 #define ALT_SPIS_CTRLR0_SCPH_E_START_BIT 0x1
332 
333 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_SCPH register field. */
334 #define ALT_SPIS_CTRLR0_SCPH_LSB 6
335 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_SCPH register field. */
336 #define ALT_SPIS_CTRLR0_SCPH_MSB 6
337 /* The width in bits of the ALT_SPIS_CTRLR0_SCPH register field. */
338 #define ALT_SPIS_CTRLR0_SCPH_WIDTH 1
339 /* The mask used to set the ALT_SPIS_CTRLR0_SCPH register field value. */
340 #define ALT_SPIS_CTRLR0_SCPH_SET_MSK 0x00000040
341 /* The mask used to clear the ALT_SPIS_CTRLR0_SCPH register field value. */
342 #define ALT_SPIS_CTRLR0_SCPH_CLR_MSK 0xffffffbf
343 /* The reset value of the ALT_SPIS_CTRLR0_SCPH register field. */
344 #define ALT_SPIS_CTRLR0_SCPH_RESET 0x0
345 /* Extracts the ALT_SPIS_CTRLR0_SCPH field value from a register. */
346 #define ALT_SPIS_CTRLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
347 /* Produces a ALT_SPIS_CTRLR0_SCPH register field value suitable for setting the register. */
348 #define ALT_SPIS_CTRLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
349 
350 /*
351  * Field : SCPOL
352  *
353  * Serial Clock Polarity.
354  *
355  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select
356  *
357  * the polarity of the inactive serial clock, which is held inactive when
358  *
359  * the DW_apb_ssi master is not actively transferring data on the serial bus.
360  *
361  * 0 - Inactive state of serial clock is low
362  *
363  * 1 - Inactive state of serial clock is high
364  *
365  * Field Enumeration Values:
366  *
367  * Enum | Value | Description
368  * :--------------------------------------|:------|:----------------------------
369  * ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_HIGH | 0x0 | Clock is inactive when high
370  * ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_LOW | 0x1 | Clock is inactive when low
371  *
372  * Field Access Macros:
373  *
374  */
375 /*
376  * Enumerated value for register field ALT_SPIS_CTRLR0_SCPOL
377  *
378  * Clock is inactive when high
379  */
380 #define ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_HIGH 0x0
381 /*
382  * Enumerated value for register field ALT_SPIS_CTRLR0_SCPOL
383  *
384  * Clock is inactive when low
385  */
386 #define ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_LOW 0x1
387 
388 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_SCPOL register field. */
389 #define ALT_SPIS_CTRLR0_SCPOL_LSB 7
390 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_SCPOL register field. */
391 #define ALT_SPIS_CTRLR0_SCPOL_MSB 7
392 /* The width in bits of the ALT_SPIS_CTRLR0_SCPOL register field. */
393 #define ALT_SPIS_CTRLR0_SCPOL_WIDTH 1
394 /* The mask used to set the ALT_SPIS_CTRLR0_SCPOL register field value. */
395 #define ALT_SPIS_CTRLR0_SCPOL_SET_MSK 0x00000080
396 /* The mask used to clear the ALT_SPIS_CTRLR0_SCPOL register field value. */
397 #define ALT_SPIS_CTRLR0_SCPOL_CLR_MSK 0xffffff7f
398 /* The reset value of the ALT_SPIS_CTRLR0_SCPOL register field. */
399 #define ALT_SPIS_CTRLR0_SCPOL_RESET 0x0
400 /* Extracts the ALT_SPIS_CTRLR0_SCPOL field value from a register. */
401 #define ALT_SPIS_CTRLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
402 /* Produces a ALT_SPIS_CTRLR0_SCPOL register field value suitable for setting the register. */
403 #define ALT_SPIS_CTRLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
404 
405 /*
406  * Field : TMOD
407  *
408  * Transfer Mode.
409  *
410  * Selects the mode of transfer for serial communication. This field does
411  *
412  * not affect the transfer duplicity. Only indicates whether the receive or
413  *
414  * transmit data are valid. In transmit-only mode, data received from the
415  *
416  * external device is not valid and is not stored in the receive FIFO memory;
417  *
418  * it is overwritten on the next transfer. In receive-only mode, transmitted
419  *
420  * data are not valid. After the first write to the transmit FIFO, the same
421  *
422  * word is retransmitted for the duration of the transfer. In
423  *
424  * transmit-and-receive mode, both transmit and receive data are valid.
425  *
426  * The transfer continues until the transmit FIFO is empty. Data received
427  *
428  * from the external device are stored into the receive FIFO memory, where
429  *
430  * it can be accessed by the host processor.
431  *
432  * 00 - Transmit & Receive
433  *
434  * 01 - Transmit Only
435  *
436  * 10 - Receive Only
437  *
438  * 11 - EEPROM Read
439  *
440  * When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode and
441  * SPI_FRF is not set to 2'b00.
442  *
443  * There are only two valid combinations:
444  *
445  * 01 Read
446  *
447  * 10 - Write
448  *
449  * Field Enumeration Values:
450  *
451  * Enum | Value | Description
452  * :-----------------------------------|:------|:-------------------
453  * ALT_SPIS_CTRLR0_TMOD_E_TX_AND_RX | 0x0 | Transmit & receive
454  * ALT_SPIS_CTRLR0_TMOD_E_TX_ONLY | 0x1 | Transmit only mode
455  * ALT_SPIS_CTRLR0_TMOD_E_RX_ONLY | 0x2 | Receive only mode
456  * ALT_SPIS_CTRLR0_TMOD_E_EEPROM_READ | 0x3 | EEPROM Read mode
457  *
458  * Field Access Macros:
459  *
460  */
461 /*
462  * Enumerated value for register field ALT_SPIS_CTRLR0_TMOD
463  *
464  * Transmit & receive
465  */
466 #define ALT_SPIS_CTRLR0_TMOD_E_TX_AND_RX 0x0
467 /*
468  * Enumerated value for register field ALT_SPIS_CTRLR0_TMOD
469  *
470  * Transmit only mode
471  */
472 #define ALT_SPIS_CTRLR0_TMOD_E_TX_ONLY 0x1
473 /*
474  * Enumerated value for register field ALT_SPIS_CTRLR0_TMOD
475  *
476  * Receive only mode
477  */
478 #define ALT_SPIS_CTRLR0_TMOD_E_RX_ONLY 0x2
479 /*
480  * Enumerated value for register field ALT_SPIS_CTRLR0_TMOD
481  *
482  * EEPROM Read mode
483  */
484 #define ALT_SPIS_CTRLR0_TMOD_E_EEPROM_READ 0x3
485 
486 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_TMOD register field. */
487 #define ALT_SPIS_CTRLR0_TMOD_LSB 8
488 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_TMOD register field. */
489 #define ALT_SPIS_CTRLR0_TMOD_MSB 9
490 /* The width in bits of the ALT_SPIS_CTRLR0_TMOD register field. */
491 #define ALT_SPIS_CTRLR0_TMOD_WIDTH 2
492 /* The mask used to set the ALT_SPIS_CTRLR0_TMOD register field value. */
493 #define ALT_SPIS_CTRLR0_TMOD_SET_MSK 0x00000300
494 /* The mask used to clear the ALT_SPIS_CTRLR0_TMOD register field value. */
495 #define ALT_SPIS_CTRLR0_TMOD_CLR_MSK 0xfffffcff
496 /* The reset value of the ALT_SPIS_CTRLR0_TMOD register field. */
497 #define ALT_SPIS_CTRLR0_TMOD_RESET 0x0
498 /* Extracts the ALT_SPIS_CTRLR0_TMOD field value from a register. */
499 #define ALT_SPIS_CTRLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
500 /* Produces a ALT_SPIS_CTRLR0_TMOD register field value suitable for setting the register. */
501 #define ALT_SPIS_CTRLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
502 
503 /*
504  * Field : SLV_OE
505  *
506  * Slave Output Enable.
507  *
508  * Relevant only when the DW_apb_ssi is configured as a serial-slave
509  *
510  * device. When configured as a serial master, this bit field has no
511  *
512  * functionality. This bit enables or disables the setting of the
513  *
514  * ssi_oe_n output from the DW_apb_ssi serial slave. When SLV_OE = 1,
515  *
516  * the ssi_oe_n output can never be active. When the ssi_oe_n output
517  *
518  * controls the tri-state buffer on the txd output from the slave, a
519  *
520  * high impedance state is always present on the slave txd output when
521  *
522  * SLV_OE = 1. This is useful when the master transmits in broadcast
523  *
524  * mode (master transmits data to all slave devices). Only one slave
525  *
526  * may respond with data on the master rxd line. This bit is
527  *
528  * enabled after reset and must be disabled by software (when broadcast
529  *
530  * mode is used), if you do not want this device to respond with data.
531  *
532  * 0 - Slave txd is enabled
533  *
534  * 1 - Slave txd is disabled
535  *
536  * Field Enumeration Values:
537  *
538  * Enum | Value | Description
539  * :----------------------------------|:------|:-------------------------
540  * ALT_SPIS_CTRLR0_SLV_OE_E_ENABLED | 0x0 | Slave Output is enabled
541  * ALT_SPIS_CTRLR0_SLV_OE_E_DISABLED | 0x1 | Slave Output is disabled
542  *
543  * Field Access Macros:
544  *
545  */
546 /*
547  * Enumerated value for register field ALT_SPIS_CTRLR0_SLV_OE
548  *
549  * Slave Output is enabled
550  */
551 #define ALT_SPIS_CTRLR0_SLV_OE_E_ENABLED 0x0
552 /*
553  * Enumerated value for register field ALT_SPIS_CTRLR0_SLV_OE
554  *
555  * Slave Output is disabled
556  */
557 #define ALT_SPIS_CTRLR0_SLV_OE_E_DISABLED 0x1
558 
559 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_SLV_OE register field. */
560 #define ALT_SPIS_CTRLR0_SLV_OE_LSB 10
561 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_SLV_OE register field. */
562 #define ALT_SPIS_CTRLR0_SLV_OE_MSB 10
563 /* The width in bits of the ALT_SPIS_CTRLR0_SLV_OE register field. */
564 #define ALT_SPIS_CTRLR0_SLV_OE_WIDTH 1
565 /* The mask used to set the ALT_SPIS_CTRLR0_SLV_OE register field value. */
566 #define ALT_SPIS_CTRLR0_SLV_OE_SET_MSK 0x00000400
567 /* The mask used to clear the ALT_SPIS_CTRLR0_SLV_OE register field value. */
568 #define ALT_SPIS_CTRLR0_SLV_OE_CLR_MSK 0xfffffbff
569 /* The reset value of the ALT_SPIS_CTRLR0_SLV_OE register field. */
570 #define ALT_SPIS_CTRLR0_SLV_OE_RESET 0x0
571 /* Extracts the ALT_SPIS_CTRLR0_SLV_OE field value from a register. */
572 #define ALT_SPIS_CTRLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
573 /* Produces a ALT_SPIS_CTRLR0_SLV_OE register field value suitable for setting the register. */
574 #define ALT_SPIS_CTRLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
575 
576 /*
577  * Field : SRL
578  *
579  * Shift Register Loop. Used for testing purposes only. When internally
580  *
581  * active, connects the transmit shift register output to the receive
582  *
583  * shift register input.
584  *
585  * 0 - Normal Mode Operation
586  *
587  * 1 - Test Mode Operation
588  *
589  * Field Enumeration Values:
590  *
591  * Enum | Value | Description
592  * :-----------------------------------|:------|:---------------------------------------
593  * ALT_SPIS_CTRLR0_SRL_E_NORMAL_MODE | 0x0 | Normal mode operation
594  * ALT_SPIS_CTRLR0_SRL_E_TESTING_MODE | 0x1 | Test mode: Tx & Rx shift reg connected
595  *
596  * Field Access Macros:
597  *
598  */
599 /*
600  * Enumerated value for register field ALT_SPIS_CTRLR0_SRL
601  *
602  * Normal mode operation
603  */
604 #define ALT_SPIS_CTRLR0_SRL_E_NORMAL_MODE 0x0
605 /*
606  * Enumerated value for register field ALT_SPIS_CTRLR0_SRL
607  *
608  * Test mode: Tx & Rx shift reg connected
609  */
610 #define ALT_SPIS_CTRLR0_SRL_E_TESTING_MODE 0x1
611 
612 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_SRL register field. */
613 #define ALT_SPIS_CTRLR0_SRL_LSB 11
614 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_SRL register field. */
615 #define ALT_SPIS_CTRLR0_SRL_MSB 11
616 /* The width in bits of the ALT_SPIS_CTRLR0_SRL register field. */
617 #define ALT_SPIS_CTRLR0_SRL_WIDTH 1
618 /* The mask used to set the ALT_SPIS_CTRLR0_SRL register field value. */
619 #define ALT_SPIS_CTRLR0_SRL_SET_MSK 0x00000800
620 /* The mask used to clear the ALT_SPIS_CTRLR0_SRL register field value. */
621 #define ALT_SPIS_CTRLR0_SRL_CLR_MSK 0xfffff7ff
622 /* The reset value of the ALT_SPIS_CTRLR0_SRL register field. */
623 #define ALT_SPIS_CTRLR0_SRL_RESET 0x0
624 /* Extracts the ALT_SPIS_CTRLR0_SRL field value from a register. */
625 #define ALT_SPIS_CTRLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
626 /* Produces a ALT_SPIS_CTRLR0_SRL register field value suitable for setting the register. */
627 #define ALT_SPIS_CTRLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
628 
629 /*
630  * Field : CFS
631  *
632  * Control Frame Size. Selects the length of the control word for the
633  *
634  * Microwire frame format
635  *
636  * When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode and
637  * SPI_FRF is not set to 2'b00.
638  *
639  * This bit defines Length of Address to be transmitted. Refer Table 4 6 for field
640  * decode.
641  *
642  * Only after this much bits are programmed in to the FIFO the transfer can begin.
643  *
644  * Field Enumeration Values:
645  *
646  * Enum | Value | Description
647  * :----------------------------------|:------|:--------------------
648  * ALT_SPIS_CTRLR0_CFS_E_SIZE_01_BIT | 0x0 | 01-bit Control Word
649  * ALT_SPIS_CTRLR0_CFS_E_SIZE_02_BIT | 0x1 | 02-bit Control Word
650  * ALT_SPIS_CTRLR0_CFS_E_SIZE_03_BIT | 0x2 | 03-bit Control Word
651  * ALT_SPIS_CTRLR0_CFS_E_SIZE_04_BIT | 0x3 | 04-bit Control Word
652  * ALT_SPIS_CTRLR0_CFS_E_SIZE_05_BIT | 0x4 | 05-bit Control Word
653  * ALT_SPIS_CTRLR0_CFS_E_SIZE_06_BIT | 0x5 | 06-bit Control Word
654  * ALT_SPIS_CTRLR0_CFS_E_SIZE_07_BIT | 0x6 | 07-bit Control Word
655  * ALT_SPIS_CTRLR0_CFS_E_SIZE_08_BIT | 0x7 | 08-bit Control Word
656  * ALT_SPIS_CTRLR0_CFS_E_SIZE_09_BIT | 0x8 | 09-bit Control Word
657  * ALT_SPIS_CTRLR0_CFS_E_SIZE_10_BIT | 0x9 | 10-bit Control Word
658  * ALT_SPIS_CTRLR0_CFS_E_SIZE_11_BIT | 0xa | 11-bit Control Word
659  * ALT_SPIS_CTRLR0_CFS_E_SIZE_12_BIT | 0xb | 12-bit Control Word
660  * ALT_SPIS_CTRLR0_CFS_E_SIZE_13_BIT | 0xc | 13-bit Control Word
661  * ALT_SPIS_CTRLR0_CFS_E_SIZE_14_BIT | 0xd | 14-bit Control Word
662  * ALT_SPIS_CTRLR0_CFS_E_SIZE_15_BIT | 0xe | 15-bit Control Word
663  * ALT_SPIS_CTRLR0_CFS_E_SIZE_16_BIT | 0xf | 16-bit Control Word
664  *
665  * Field Access Macros:
666  *
667  */
668 /*
669  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
670  *
671  * 01-bit Control Word
672  */
673 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_01_BIT 0x0
674 /*
675  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
676  *
677  * 02-bit Control Word
678  */
679 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_02_BIT 0x1
680 /*
681  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
682  *
683  * 03-bit Control Word
684  */
685 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_03_BIT 0x2
686 /*
687  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
688  *
689  * 04-bit Control Word
690  */
691 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_04_BIT 0x3
692 /*
693  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
694  *
695  * 05-bit Control Word
696  */
697 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_05_BIT 0x4
698 /*
699  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
700  *
701  * 06-bit Control Word
702  */
703 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_06_BIT 0x5
704 /*
705  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
706  *
707  * 07-bit Control Word
708  */
709 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_07_BIT 0x6
710 /*
711  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
712  *
713  * 08-bit Control Word
714  */
715 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_08_BIT 0x7
716 /*
717  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
718  *
719  * 09-bit Control Word
720  */
721 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_09_BIT 0x8
722 /*
723  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
724  *
725  * 10-bit Control Word
726  */
727 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_10_BIT 0x9
728 /*
729  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
730  *
731  * 11-bit Control Word
732  */
733 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_11_BIT 0xa
734 /*
735  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
736  *
737  * 12-bit Control Word
738  */
739 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_12_BIT 0xb
740 /*
741  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
742  *
743  * 13-bit Control Word
744  */
745 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_13_BIT 0xc
746 /*
747  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
748  *
749  * 14-bit Control Word
750  */
751 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_14_BIT 0xd
752 /*
753  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
754  *
755  * 15-bit Control Word
756  */
757 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_15_BIT 0xe
758 /*
759  * Enumerated value for register field ALT_SPIS_CTRLR0_CFS
760  *
761  * 16-bit Control Word
762  */
763 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_16_BIT 0xf
764 
765 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_CFS register field. */
766 #define ALT_SPIS_CTRLR0_CFS_LSB 12
767 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_CFS register field. */
768 #define ALT_SPIS_CTRLR0_CFS_MSB 15
769 /* The width in bits of the ALT_SPIS_CTRLR0_CFS register field. */
770 #define ALT_SPIS_CTRLR0_CFS_WIDTH 4
771 /* The mask used to set the ALT_SPIS_CTRLR0_CFS register field value. */
772 #define ALT_SPIS_CTRLR0_CFS_SET_MSK 0x0000f000
773 /* The mask used to clear the ALT_SPIS_CTRLR0_CFS register field value. */
774 #define ALT_SPIS_CTRLR0_CFS_CLR_MSK 0xffff0fff
775 /* The reset value of the ALT_SPIS_CTRLR0_CFS register field. */
776 #define ALT_SPIS_CTRLR0_CFS_RESET 0x0
777 /* Extracts the ALT_SPIS_CTRLR0_CFS field value from a register. */
778 #define ALT_SPIS_CTRLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
779 /* Produces a ALT_SPIS_CTRLR0_CFS register field value suitable for setting the register. */
780 #define ALT_SPIS_CTRLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
781 
782 /*
783  * Field : DFS_32
784  *
785  * Data Frame Size in 32-bit transfer size mode.
786  *
787  * Selects the data frame length. When the data frame size is programmed
788  *
789  * to be less than 32 bits, the receive data are automatically
790  *
791  * right-justified by the receive logic, with the upper bits of the receive
792  *
793  * FIFO zero-padded. You must right-justify transmit data before writing
794  *
795  * into the transmit FIFO. The transmit logic ignores the upper unused
796  *
797  * bits when transmitting the data
798  *
799  * Note: When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode
800  * and SPI_FRF is not set to 2'b00.
801  *
802  * DFS value should be multiple of 2 if SPI_FRF = 01, and
803  *
804  * DFS value should be multiple of 4 if SPI_FRF = 10.
805  *
806  * Field Enumeration Values:
807  *
808  * Enum | Value | Description
809  * :--------------------------------------|:------|:-----------------------------
810  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_04BITS | 0x3 | 04- bit serial data transfer
811  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_05BITS | 0x4 | 05- bit serial data transfer
812  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_06BITS | 0x5 | 06- bit serial data transfer
813  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_07BITS | 0x6 | 07- bit serial data transfer
814  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_08BITS | 0x7 | 08- bit serial data transfer
815  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_09BITS | 0x8 | 09- bit serial data transfer
816  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_10BITS | 0x9 | 10- bit serial data transfer
817  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_11BITS | 0xa | 11- bit serial data transfer
818  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_12BITS | 0xb | 12- bit serial data transfer
819  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_13BITS | 0xc | 13- bit serial data transfer
820  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_14BITS | 0xd | 14- bit serial data transfer
821  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_15BITS | 0xe | 15- bit serial data transfer
822  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_16BITS | 0xf | 16- bit serial data transfer
823  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_17BITS | 0x10 | 17- bit serial data transfer
824  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_18BITS | 0x11 | 18- bit serial data transfer
825  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_19BITS | 0x12 | 19- bit serial data transfer
826  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_20BITS | 0x13 | 20- bit serial data transfer
827  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_21BITS | 0x14 | 21- bit serial data transfer
828  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_22BITS | 0x15 | 22- bit serial data transfer
829  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_23BITS | 0x16 | 23- bit serial data transfer
830  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_24BITS | 0x17 | 24- bit serial data transfer
831  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_25BITS | 0x18 | 25- bit serial data transfer
832  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_26BITS | 0x19 | 26- bit serial data transfer
833  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_27BITS | 0x1a | 27- bit serial data transfer
834  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_28BITS | 0x1b | 28- bit serial data transfer
835  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_29BITS | 0x1c | 29- bit serial data transfer
836  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_30BITS | 0x1d | 30- bit serial data transfer
837  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_31BITS | 0x1e | 31- bit serial data transfer
838  * ALT_SPIS_CTRLR0_DFS_32_E_FRAME_32BITS | 0x1f | 32- bit serial data transfer
839  *
840  * Field Access Macros:
841  *
842  */
843 /*
844  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
845  *
846  * 04- bit serial data transfer
847  */
848 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_04BITS 0x3
849 /*
850  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
851  *
852  * 05- bit serial data transfer
853  */
854 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_05BITS 0x4
855 /*
856  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
857  *
858  * 06- bit serial data transfer
859  */
860 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_06BITS 0x5
861 /*
862  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
863  *
864  * 07- bit serial data transfer
865  */
866 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_07BITS 0x6
867 /*
868  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
869  *
870  * 08- bit serial data transfer
871  */
872 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_08BITS 0x7
873 /*
874  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
875  *
876  * 09- bit serial data transfer
877  */
878 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_09BITS 0x8
879 /*
880  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
881  *
882  * 10- bit serial data transfer
883  */
884 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_10BITS 0x9
885 /*
886  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
887  *
888  * 11- bit serial data transfer
889  */
890 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_11BITS 0xa
891 /*
892  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
893  *
894  * 12- bit serial data transfer
895  */
896 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_12BITS 0xb
897 /*
898  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
899  *
900  * 13- bit serial data transfer
901  */
902 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_13BITS 0xc
903 /*
904  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
905  *
906  * 14- bit serial data transfer
907  */
908 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_14BITS 0xd
909 /*
910  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
911  *
912  * 15- bit serial data transfer
913  */
914 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_15BITS 0xe
915 /*
916  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
917  *
918  * 16- bit serial data transfer
919  */
920 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_16BITS 0xf
921 /*
922  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
923  *
924  * 17- bit serial data transfer
925  */
926 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_17BITS 0x10
927 /*
928  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
929  *
930  * 18- bit serial data transfer
931  */
932 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_18BITS 0x11
933 /*
934  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
935  *
936  * 19- bit serial data transfer
937  */
938 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_19BITS 0x12
939 /*
940  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
941  *
942  * 20- bit serial data transfer
943  */
944 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_20BITS 0x13
945 /*
946  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
947  *
948  * 21- bit serial data transfer
949  */
950 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_21BITS 0x14
951 /*
952  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
953  *
954  * 22- bit serial data transfer
955  */
956 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_22BITS 0x15
957 /*
958  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
959  *
960  * 23- bit serial data transfer
961  */
962 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_23BITS 0x16
963 /*
964  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
965  *
966  * 24- bit serial data transfer
967  */
968 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_24BITS 0x17
969 /*
970  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
971  *
972  * 25- bit serial data transfer
973  */
974 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_25BITS 0x18
975 /*
976  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
977  *
978  * 26- bit serial data transfer
979  */
980 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_26BITS 0x19
981 /*
982  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
983  *
984  * 27- bit serial data transfer
985  */
986 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_27BITS 0x1a
987 /*
988  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
989  *
990  * 28- bit serial data transfer
991  */
992 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_28BITS 0x1b
993 /*
994  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
995  *
996  * 29- bit serial data transfer
997  */
998 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_29BITS 0x1c
999 /*
1000  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
1001  *
1002  * 30- bit serial data transfer
1003  */
1004 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_30BITS 0x1d
1005 /*
1006  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
1007  *
1008  * 31- bit serial data transfer
1009  */
1010 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_31BITS 0x1e
1011 /*
1012  * Enumerated value for register field ALT_SPIS_CTRLR0_DFS_32
1013  *
1014  * 32- bit serial data transfer
1015  */
1016 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_32BITS 0x1f
1017 
1018 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_DFS_32 register field. */
1019 #define ALT_SPIS_CTRLR0_DFS_32_LSB 16
1020 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_DFS_32 register field. */
1021 #define ALT_SPIS_CTRLR0_DFS_32_MSB 20
1022 /* The width in bits of the ALT_SPIS_CTRLR0_DFS_32 register field. */
1023 #define ALT_SPIS_CTRLR0_DFS_32_WIDTH 5
1024 /* The mask used to set the ALT_SPIS_CTRLR0_DFS_32 register field value. */
1025 #define ALT_SPIS_CTRLR0_DFS_32_SET_MSK 0x001f0000
1026 /* The mask used to clear the ALT_SPIS_CTRLR0_DFS_32 register field value. */
1027 #define ALT_SPIS_CTRLR0_DFS_32_CLR_MSK 0xffe0ffff
1028 /* The reset value of the ALT_SPIS_CTRLR0_DFS_32 register field. */
1029 #define ALT_SPIS_CTRLR0_DFS_32_RESET 0x7
1030 /* Extracts the ALT_SPIS_CTRLR0_DFS_32 field value from a register. */
1031 #define ALT_SPIS_CTRLR0_DFS_32_GET(value) (((value) & 0x001f0000) >> 16)
1032 /* Produces a ALT_SPIS_CTRLR0_DFS_32 register field value suitable for setting the register. */
1033 #define ALT_SPIS_CTRLR0_DFS_32_SET(value) (((value) << 16) & 0x001f0000)
1034 
1035 /*
1036  * Field : SPI_FRF
1037  *
1038  * SPI Frame Format:
1039  *
1040  * Selects data frame format for Transmitting/Receiving the data
1041  *
1042  * 00 - Standard SPI Format
1043  *
1044  * 01 - Dual SPI Format
1045  *
1046  * 10 - Quad SPI Format
1047  *
1048  * Bits only valid when SSI_SPI_MODE is either set to "Dual" or "Dual/Quad
1049  * Both" mode.
1050  *
1051  * Field Access Macros:
1052  *
1053  */
1054 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_SPI_FRF register field. */
1055 #define ALT_SPIS_CTRLR0_SPI_FRF_LSB 21
1056 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_SPI_FRF register field. */
1057 #define ALT_SPIS_CTRLR0_SPI_FRF_MSB 22
1058 /* The width in bits of the ALT_SPIS_CTRLR0_SPI_FRF register field. */
1059 #define ALT_SPIS_CTRLR0_SPI_FRF_WIDTH 2
1060 /* The mask used to set the ALT_SPIS_CTRLR0_SPI_FRF register field value. */
1061 #define ALT_SPIS_CTRLR0_SPI_FRF_SET_MSK 0x00600000
1062 /* The mask used to clear the ALT_SPIS_CTRLR0_SPI_FRF register field value. */
1063 #define ALT_SPIS_CTRLR0_SPI_FRF_CLR_MSK 0xff9fffff
1064 /* The reset value of the ALT_SPIS_CTRLR0_SPI_FRF register field. */
1065 #define ALT_SPIS_CTRLR0_SPI_FRF_RESET 0x0
1066 /* Extracts the ALT_SPIS_CTRLR0_SPI_FRF field value from a register. */
1067 #define ALT_SPIS_CTRLR0_SPI_FRF_GET(value) (((value) & 0x00600000) >> 21)
1068 /* Produces a ALT_SPIS_CTRLR0_SPI_FRF register field value suitable for setting the register. */
1069 #define ALT_SPIS_CTRLR0_SPI_FRF_SET(value) (((value) << 21) & 0x00600000)
1070 
1071 /*
1072  * Field : RSVD_CTRLR0
1073  *
1074  * Reserved bits - Read Only
1075  *
1076  * Field Access Macros:
1077  *
1078  */
1079 /* The Least Significant Bit (LSB) position of the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field. */
1080 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_LSB 23
1081 /* The Most Significant Bit (MSB) position of the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field. */
1082 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_MSB 31
1083 /* The width in bits of the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field. */
1084 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_WIDTH 9
1085 /* The mask used to set the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field value. */
1086 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_SET_MSK 0xff800000
1087 /* The mask used to clear the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field value. */
1088 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_CLR_MSK 0x007fffff
1089 /* The reset value of the ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field. */
1090 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_RESET 0x0
1091 /* Extracts the ALT_SPIS_CTRLR0_RSVD_CTRLR0 field value from a register. */
1092 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_GET(value) (((value) & 0xff800000) >> 23)
1093 /* Produces a ALT_SPIS_CTRLR0_RSVD_CTRLR0 register field value suitable for setting the register. */
1094 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_SET(value) (((value) << 23) & 0xff800000)
1095 
1096 #ifndef __ASSEMBLY__
1097 /*
1098  * WARNING: The C register and register group struct declarations are provided for
1099  * convenience and illustrative purposes. They should, however, be used with
1100  * caution as the C language standard provides no guarantees about the alignment or
1101  * atomicity of device memory accesses. The recommended practice for coding device
1102  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1103  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1104  * alt_write_dword() functions for 64 bit registers.
1105  *
1106  * The struct declaration for register ALT_SPIS_CTRLR0.
1107  */
1108 struct ALT_SPIS_CTRLR0_s
1109 {
1110  const volatile uint32_t DFS : 4; /* ALT_SPIS_CTRLR0_DFS */
1111  volatile uint32_t FRF : 2; /* ALT_SPIS_CTRLR0_FRF */
1112  volatile uint32_t SCPH : 1; /* ALT_SPIS_CTRLR0_SCPH */
1113  volatile uint32_t SCPOL : 1; /* ALT_SPIS_CTRLR0_SCPOL */
1114  volatile uint32_t TMOD : 2; /* ALT_SPIS_CTRLR0_TMOD */
1115  volatile uint32_t SLV_OE : 1; /* ALT_SPIS_CTRLR0_SLV_OE */
1116  volatile uint32_t SRL : 1; /* ALT_SPIS_CTRLR0_SRL */
1117  volatile uint32_t CFS : 4; /* ALT_SPIS_CTRLR0_CFS */
1118  volatile uint32_t DFS_32 : 5; /* ALT_SPIS_CTRLR0_DFS_32 */
1119  const volatile uint32_t SPI_FRF : 2; /* ALT_SPIS_CTRLR0_SPI_FRF */
1120  const volatile uint32_t RSVD_CTRLR0 : 9; /* ALT_SPIS_CTRLR0_RSVD_CTRLR0 */
1121 };
1122 
1123 /* The typedef declaration for register ALT_SPIS_CTRLR0. */
1124 typedef struct ALT_SPIS_CTRLR0_s ALT_SPIS_CTRLR0_t;
1125 #endif /* __ASSEMBLY__ */
1126 
1127 /* The reset value of the ALT_SPIS_CTRLR0 register. */
1128 #define ALT_SPIS_CTRLR0_RESET 0x00070000
1129 /* The byte offset of the ALT_SPIS_CTRLR0 register from the beginning of the component. */
1130 #define ALT_SPIS_CTRLR0_OFST 0x0
1131 /* The address of the ALT_SPIS_CTRLR0 register. */
1132 #define ALT_SPIS_CTRLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTRLR0_OFST))
1133 
1134 /*
1135  * Register : SSI Enable Register - SSIENR
1136  *
1137  * SSI Enable Register
1138  *
1139  * Register Layout
1140  *
1141  * Bits | Access | Reset | Description
1142  * :-------|:-------|:------|:----------------------------
1143  * [0] | RW | 0x0 | ALT_SPIS_SSIENR_SSI_EN
1144  * [31:1] | R | 0x0 | ALT_SPIS_SSIENR_RSVD_SSIENR
1145  *
1146  */
1147 /*
1148  * Field : SSI_EN
1149  *
1150  * SSI Enable. Enables and disables all DW_apb_ssi operations. When
1151  *
1152  * disabled, all serial transfers are halted immediately. Transmit and
1153  *
1154  * receive FIFO buffers are cleared when the device is disabled. It is
1155  *
1156  * impossible to program some of the DW_apb_ssi control registers when
1157  *
1158  * enabled. When disabled, the ssi_sleep output is set (after delay) to
1159  *
1160  * inform the system that it is safe to remove the ssi_clk, thus saving
1161  *
1162  * power consumption in the system.
1163  *
1164  * Field Enumeration Values:
1165  *
1166  * Enum | Value | Description
1167  * :---------------------------------|:------|:-------------------------
1168  * ALT_SPIS_SSIENR_SSI_EN_E_DISABLE | 0x0 | Disables Serial Transfer
1169  * ALT_SPIS_SSIENR_SSI_EN_E_ENABLED | 0x1 | Enables Serial Transfer
1170  *
1171  * Field Access Macros:
1172  *
1173  */
1174 /*
1175  * Enumerated value for register field ALT_SPIS_SSIENR_SSI_EN
1176  *
1177  * Disables Serial Transfer
1178  */
1179 #define ALT_SPIS_SSIENR_SSI_EN_E_DISABLE 0x0
1180 /*
1181  * Enumerated value for register field ALT_SPIS_SSIENR_SSI_EN
1182  *
1183  * Enables Serial Transfer
1184  */
1185 #define ALT_SPIS_SSIENR_SSI_EN_E_ENABLED 0x1
1186 
1187 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SSIENR_SSI_EN register field. */
1188 #define ALT_SPIS_SSIENR_SSI_EN_LSB 0
1189 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SSIENR_SSI_EN register field. */
1190 #define ALT_SPIS_SSIENR_SSI_EN_MSB 0
1191 /* The width in bits of the ALT_SPIS_SSIENR_SSI_EN register field. */
1192 #define ALT_SPIS_SSIENR_SSI_EN_WIDTH 1
1193 /* The mask used to set the ALT_SPIS_SSIENR_SSI_EN register field value. */
1194 #define ALT_SPIS_SSIENR_SSI_EN_SET_MSK 0x00000001
1195 /* The mask used to clear the ALT_SPIS_SSIENR_SSI_EN register field value. */
1196 #define ALT_SPIS_SSIENR_SSI_EN_CLR_MSK 0xfffffffe
1197 /* The reset value of the ALT_SPIS_SSIENR_SSI_EN register field. */
1198 #define ALT_SPIS_SSIENR_SSI_EN_RESET 0x0
1199 /* Extracts the ALT_SPIS_SSIENR_SSI_EN field value from a register. */
1200 #define ALT_SPIS_SSIENR_SSI_EN_GET(value) (((value) & 0x00000001) >> 0)
1201 /* Produces a ALT_SPIS_SSIENR_SSI_EN register field value suitable for setting the register. */
1202 #define ALT_SPIS_SSIENR_SSI_EN_SET(value) (((value) << 0) & 0x00000001)
1203 
1204 /*
1205  * Field : RSVD_SSIENR
1206  *
1207  * Reserved bits - Read Only
1208  *
1209  * Field Access Macros:
1210  *
1211  */
1212 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SSIENR_RSVD_SSIENR register field. */
1213 #define ALT_SPIS_SSIENR_RSVD_SSIENR_LSB 1
1214 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SSIENR_RSVD_SSIENR register field. */
1215 #define ALT_SPIS_SSIENR_RSVD_SSIENR_MSB 31
1216 /* The width in bits of the ALT_SPIS_SSIENR_RSVD_SSIENR register field. */
1217 #define ALT_SPIS_SSIENR_RSVD_SSIENR_WIDTH 31
1218 /* The mask used to set the ALT_SPIS_SSIENR_RSVD_SSIENR register field value. */
1219 #define ALT_SPIS_SSIENR_RSVD_SSIENR_SET_MSK 0xfffffffe
1220 /* The mask used to clear the ALT_SPIS_SSIENR_RSVD_SSIENR register field value. */
1221 #define ALT_SPIS_SSIENR_RSVD_SSIENR_CLR_MSK 0x00000001
1222 /* The reset value of the ALT_SPIS_SSIENR_RSVD_SSIENR register field. */
1223 #define ALT_SPIS_SSIENR_RSVD_SSIENR_RESET 0x0
1224 /* Extracts the ALT_SPIS_SSIENR_RSVD_SSIENR field value from a register. */
1225 #define ALT_SPIS_SSIENR_RSVD_SSIENR_GET(value) (((value) & 0xfffffffe) >> 1)
1226 /* Produces a ALT_SPIS_SSIENR_RSVD_SSIENR register field value suitable for setting the register. */
1227 #define ALT_SPIS_SSIENR_RSVD_SSIENR_SET(value) (((value) << 1) & 0xfffffffe)
1228 
1229 #ifndef __ASSEMBLY__
1230 /*
1231  * WARNING: The C register and register group struct declarations are provided for
1232  * convenience and illustrative purposes. They should, however, be used with
1233  * caution as the C language standard provides no guarantees about the alignment or
1234  * atomicity of device memory accesses. The recommended practice for coding device
1235  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1236  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1237  * alt_write_dword() functions for 64 bit registers.
1238  *
1239  * The struct declaration for register ALT_SPIS_SSIENR.
1240  */
1241 struct ALT_SPIS_SSIENR_s
1242 {
1243  volatile uint32_t SSI_EN : 1; /* ALT_SPIS_SSIENR_SSI_EN */
1244  const volatile uint32_t RSVD_SSIENR : 31; /* ALT_SPIS_SSIENR_RSVD_SSIENR */
1245 };
1246 
1247 /* The typedef declaration for register ALT_SPIS_SSIENR. */
1248 typedef struct ALT_SPIS_SSIENR_s ALT_SPIS_SSIENR_t;
1249 #endif /* __ASSEMBLY__ */
1250 
1251 /* The reset value of the ALT_SPIS_SSIENR register. */
1252 #define ALT_SPIS_SSIENR_RESET 0x00000000
1253 /* The byte offset of the ALT_SPIS_SSIENR register from the beginning of the component. */
1254 #define ALT_SPIS_SSIENR_OFST 0x8
1255 /* The address of the ALT_SPIS_SSIENR register. */
1256 #define ALT_SPIS_SSIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SSIENR_OFST))
1257 
1258 /*
1259  * Register : Microwire Control Register - MWCR
1260  *
1261  * Microwire Control Register.
1262  *
1263  * This register controls the direction of the data word for the half-duplex
1264  *
1265  * Microwire serial protocol. It is impossible to write to this register
1266  *
1267  * when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
1268  *
1269  * writing to the SSIENR register.
1270  *
1271  * Register Layout
1272  *
1273  * Bits | Access | Reset | Description
1274  * :-------|:-------|:------|:------------------------
1275  * [0] | RW | 0x0 | ALT_SPIS_MWCR_MWMOD
1276  * [1] | RW | 0x0 | ALT_SPIS_MWCR_MDD
1277  * [2] | R | 0x0 | ALT_SPIS_MWCR_RSVD_MHS
1278  * [31:3] | R | 0x0 | ALT_SPIS_MWCR_RSVD_MWCR
1279  *
1280  */
1281 /*
1282  * Field : MWMOD
1283  *
1284  * Microwire Transfer Mode.
1285  *
1286  * Defines whether the Microwire transfer is sequential or non-sequential.
1287  *
1288  * When sequential mode is used, only one control word is needed to
1289  *
1290  * transmit or receive a block of data words. When non-sequential mode is
1291  *
1292  * used, there must be a control word for each data word that is
1293  *
1294  * transmitted or received.
1295  *
1296  * 0: non-sequential transfer
1297  *
1298  * 1: sequential transfer
1299  *
1300  * Field Enumeration Values:
1301  *
1302  * Enum | Value | Description
1303  * :-------------------------------------|:------|:----------------------------------
1304  * ALT_SPIS_MWCR_MWMOD_E_NON_SEQUENTIAL | 0x0 | Non-Sequential Microwire Transfer
1305  * ALT_SPIS_MWCR_MWMOD_E_SEQUENTIAL | 0x1 | Sequential Microwire Transfer
1306  *
1307  * Field Access Macros:
1308  *
1309  */
1310 /*
1311  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
1312  *
1313  * Non-Sequential Microwire Transfer
1314  */
1315 #define ALT_SPIS_MWCR_MWMOD_E_NON_SEQUENTIAL 0x0
1316 /*
1317  * Enumerated value for register field ALT_SPIS_MWCR_MWMOD
1318  *
1319  * Sequential Microwire Transfer
1320  */
1321 #define ALT_SPIS_MWCR_MWMOD_E_SEQUENTIAL 0x1
1322 
1323 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
1324 #define ALT_SPIS_MWCR_MWMOD_LSB 0
1325 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MWMOD register field. */
1326 #define ALT_SPIS_MWCR_MWMOD_MSB 0
1327 /* The width in bits of the ALT_SPIS_MWCR_MWMOD register field. */
1328 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
1329 /* The mask used to set the ALT_SPIS_MWCR_MWMOD register field value. */
1330 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
1331 /* The mask used to clear the ALT_SPIS_MWCR_MWMOD register field value. */
1332 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
1333 /* The reset value of the ALT_SPIS_MWCR_MWMOD register field. */
1334 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
1335 /* Extracts the ALT_SPIS_MWCR_MWMOD field value from a register. */
1336 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
1337 /* Produces a ALT_SPIS_MWCR_MWMOD register field value suitable for setting the register. */
1338 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
1339 
1340 /*
1341  * Field : MDD
1342  *
1343  * Microwire Control.
1344  *
1345  * Defines the direction of the data word when the Microwire serial protocol
1346  *
1347  * is used. When this bit is set to 0, the data word is received by the
1348  *
1349  * DW_apb_ssi MacroCell from the external serial device. When this bit is
1350  *
1351  * set to 1, the data word is transmitted from the DW_apb_ssi MacroCell to
1352  *
1353  * the external serial device.
1354  *
1355  * Field Enumeration Values:
1356  *
1357  * Enum | Value | Description
1358  * :-----------------------------|:------|:-------------------
1359  * ALT_SPIS_MWCR_MDD_E_RECEIVE | 0x0 | SSI receives data
1360  * ALT_SPIS_MWCR_MDD_E_TRANSMIT | 0x1 | SSI transmits data
1361  *
1362  * Field Access Macros:
1363  *
1364  */
1365 /*
1366  * Enumerated value for register field ALT_SPIS_MWCR_MDD
1367  *
1368  * SSI receives data
1369  */
1370 #define ALT_SPIS_MWCR_MDD_E_RECEIVE 0x0
1371 /*
1372  * Enumerated value for register field ALT_SPIS_MWCR_MDD
1373  *
1374  * SSI transmits data
1375  */
1376 #define ALT_SPIS_MWCR_MDD_E_TRANSMIT 0x1
1377 
1378 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_MDD register field. */
1379 #define ALT_SPIS_MWCR_MDD_LSB 1
1380 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_MDD register field. */
1381 #define ALT_SPIS_MWCR_MDD_MSB 1
1382 /* The width in bits of the ALT_SPIS_MWCR_MDD register field. */
1383 #define ALT_SPIS_MWCR_MDD_WIDTH 1
1384 /* The mask used to set the ALT_SPIS_MWCR_MDD register field value. */
1385 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
1386 /* The mask used to clear the ALT_SPIS_MWCR_MDD register field value. */
1387 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
1388 /* The reset value of the ALT_SPIS_MWCR_MDD register field. */
1389 #define ALT_SPIS_MWCR_MDD_RESET 0x0
1390 /* Extracts the ALT_SPIS_MWCR_MDD field value from a register. */
1391 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1392 /* Produces a ALT_SPIS_MWCR_MDD register field value suitable for setting the register. */
1393 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1394 
1395 /*
1396  * Field : RSVD_MHS
1397  *
1398  * Reserved field- read-only
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_RSVD_MHS register field. */
1404 #define ALT_SPIS_MWCR_RSVD_MHS_LSB 2
1405 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_RSVD_MHS register field. */
1406 #define ALT_SPIS_MWCR_RSVD_MHS_MSB 2
1407 /* The width in bits of the ALT_SPIS_MWCR_RSVD_MHS register field. */
1408 #define ALT_SPIS_MWCR_RSVD_MHS_WIDTH 1
1409 /* The mask used to set the ALT_SPIS_MWCR_RSVD_MHS register field value. */
1410 #define ALT_SPIS_MWCR_RSVD_MHS_SET_MSK 0x00000004
1411 /* The mask used to clear the ALT_SPIS_MWCR_RSVD_MHS register field value. */
1412 #define ALT_SPIS_MWCR_RSVD_MHS_CLR_MSK 0xfffffffb
1413 /* The reset value of the ALT_SPIS_MWCR_RSVD_MHS register field. */
1414 #define ALT_SPIS_MWCR_RSVD_MHS_RESET 0x0
1415 /* Extracts the ALT_SPIS_MWCR_RSVD_MHS field value from a register. */
1416 #define ALT_SPIS_MWCR_RSVD_MHS_GET(value) (((value) & 0x00000004) >> 2)
1417 /* Produces a ALT_SPIS_MWCR_RSVD_MHS register field value suitable for setting the register. */
1418 #define ALT_SPIS_MWCR_RSVD_MHS_SET(value) (((value) << 2) & 0x00000004)
1419 
1420 /*
1421  * Field : RSVD_MWCR
1422  *
1423  * Reserved bits - Read Only
1424  *
1425  * Field Access Macros:
1426  *
1427  */
1428 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MWCR_RSVD_MWCR register field. */
1429 #define ALT_SPIS_MWCR_RSVD_MWCR_LSB 3
1430 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MWCR_RSVD_MWCR register field. */
1431 #define ALT_SPIS_MWCR_RSVD_MWCR_MSB 31
1432 /* The width in bits of the ALT_SPIS_MWCR_RSVD_MWCR register field. */
1433 #define ALT_SPIS_MWCR_RSVD_MWCR_WIDTH 29
1434 /* The mask used to set the ALT_SPIS_MWCR_RSVD_MWCR register field value. */
1435 #define ALT_SPIS_MWCR_RSVD_MWCR_SET_MSK 0xfffffff8
1436 /* The mask used to clear the ALT_SPIS_MWCR_RSVD_MWCR register field value. */
1437 #define ALT_SPIS_MWCR_RSVD_MWCR_CLR_MSK 0x00000007
1438 /* The reset value of the ALT_SPIS_MWCR_RSVD_MWCR register field. */
1439 #define ALT_SPIS_MWCR_RSVD_MWCR_RESET 0x0
1440 /* Extracts the ALT_SPIS_MWCR_RSVD_MWCR field value from a register. */
1441 #define ALT_SPIS_MWCR_RSVD_MWCR_GET(value) (((value) & 0xfffffff8) >> 3)
1442 /* Produces a ALT_SPIS_MWCR_RSVD_MWCR register field value suitable for setting the register. */
1443 #define ALT_SPIS_MWCR_RSVD_MWCR_SET(value) (((value) << 3) & 0xfffffff8)
1444 
1445 #ifndef __ASSEMBLY__
1446 /*
1447  * WARNING: The C register and register group struct declarations are provided for
1448  * convenience and illustrative purposes. They should, however, be used with
1449  * caution as the C language standard provides no guarantees about the alignment or
1450  * atomicity of device memory accesses. The recommended practice for coding device
1451  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1452  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1453  * alt_write_dword() functions for 64 bit registers.
1454  *
1455  * The struct declaration for register ALT_SPIS_MWCR.
1456  */
1457 struct ALT_SPIS_MWCR_s
1458 {
1459  volatile uint32_t MWMOD : 1; /* ALT_SPIS_MWCR_MWMOD */
1460  volatile uint32_t MDD : 1; /* ALT_SPIS_MWCR_MDD */
1461  const volatile uint32_t RSVD_MHS : 1; /* ALT_SPIS_MWCR_RSVD_MHS */
1462  const volatile uint32_t RSVD_MWCR : 29; /* ALT_SPIS_MWCR_RSVD_MWCR */
1463 };
1464 
1465 /* The typedef declaration for register ALT_SPIS_MWCR. */
1466 typedef struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
1467 #endif /* __ASSEMBLY__ */
1468 
1469 /* The reset value of the ALT_SPIS_MWCR register. */
1470 #define ALT_SPIS_MWCR_RESET 0x00000000
1471 /* The byte offset of the ALT_SPIS_MWCR register from the beginning of the component. */
1472 #define ALT_SPIS_MWCR_OFST 0xc
1473 /* The address of the ALT_SPIS_MWCR register. */
1474 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
1475 
1476 /*
1477  * Register : Transmit FIFO Threshold Level - TXFTLR
1478  *
1479  * Transmit FIFO Threshold Level.
1480  *
1481  * This register controls the threshold value for the transmit FIFO memory.
1482  *
1483  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1484  *
1485  * Register Layout
1486  *
1487  * Bits | Access | Reset | Description
1488  * :-------|:-------|:------|:----------------------------
1489  * [7:0] | RW | 0x0 | ALT_SPIS_TXFTLR_TFT
1490  * [31:8] | R | 0x0 | ALT_SPIS_TXFTLR_RSVD_TXFTLR
1491  *
1492  */
1493 /*
1494  * Field : TFT
1495  *
1496  * Transmit FIFO Threshold.
1497  *
1498  * Controls the level of entries (or below) at which the transmit FIFO controller
1499  *
1500  * triggers an interrupt. The FIFO depth is configurable in the range 2-256;
1501  *
1502  * this register is sized to the number of address bits needed to access the
1503  *
1504  * FIFO. If you attempt to set this value greater than or equal to the depth
1505  *
1506  * of the FIFO, this field is not written and retains its current value. When
1507  *
1508  * the number of transmit FIFO entries is less than or equal to this value,
1509  *
1510  * the transmit FIFO empty interrupt is triggered.
1511  *
1512  * Field Access Macros:
1513  *
1514  */
1515 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
1516 #define ALT_SPIS_TXFTLR_TFT_LSB 0
1517 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_TFT register field. */
1518 #define ALT_SPIS_TXFTLR_TFT_MSB 7
1519 /* The width in bits of the ALT_SPIS_TXFTLR_TFT register field. */
1520 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
1521 /* The mask used to set the ALT_SPIS_TXFTLR_TFT register field value. */
1522 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
1523 /* The mask used to clear the ALT_SPIS_TXFTLR_TFT register field value. */
1524 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
1525 /* The reset value of the ALT_SPIS_TXFTLR_TFT register field. */
1526 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
1527 /* Extracts the ALT_SPIS_TXFTLR_TFT field value from a register. */
1528 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1529 /* Produces a ALT_SPIS_TXFTLR_TFT register field value suitable for setting the register. */
1530 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1531 
1532 /*
1533  * Field : RSVD_TXFTLR
1534  *
1535  * Reserved bits - Read Only
1536  *
1537  * Field Access Macros:
1538  *
1539  */
1540 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field. */
1541 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_LSB 8
1542 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field. */
1543 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_MSB 31
1544 /* The width in bits of the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field. */
1545 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_WIDTH 24
1546 /* The mask used to set the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field value. */
1547 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_SET_MSK 0xffffff00
1548 /* The mask used to clear the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field value. */
1549 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_CLR_MSK 0x000000ff
1550 /* The reset value of the ALT_SPIS_TXFTLR_RSVD_TXFTLR register field. */
1551 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_RESET 0x0
1552 /* Extracts the ALT_SPIS_TXFTLR_RSVD_TXFTLR field value from a register. */
1553 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1554 /* Produces a ALT_SPIS_TXFTLR_RSVD_TXFTLR register field value suitable for setting the register. */
1555 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1556 
1557 #ifndef __ASSEMBLY__
1558 /*
1559  * WARNING: The C register and register group struct declarations are provided for
1560  * convenience and illustrative purposes. They should, however, be used with
1561  * caution as the C language standard provides no guarantees about the alignment or
1562  * atomicity of device memory accesses. The recommended practice for coding device
1563  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1564  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1565  * alt_write_dword() functions for 64 bit registers.
1566  *
1567  * The struct declaration for register ALT_SPIS_TXFTLR.
1568  */
1569 struct ALT_SPIS_TXFTLR_s
1570 {
1571  volatile uint32_t TFT : 8; /* ALT_SPIS_TXFTLR_TFT */
1572  const volatile uint32_t RSVD_TXFTLR : 24; /* ALT_SPIS_TXFTLR_RSVD_TXFTLR */
1573 };
1574 
1575 /* The typedef declaration for register ALT_SPIS_TXFTLR. */
1576 typedef struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
1577 #endif /* __ASSEMBLY__ */
1578 
1579 /* The reset value of the ALT_SPIS_TXFTLR register. */
1580 #define ALT_SPIS_TXFTLR_RESET 0x00000000
1581 /* The byte offset of the ALT_SPIS_TXFTLR register from the beginning of the component. */
1582 #define ALT_SPIS_TXFTLR_OFST 0x18
1583 /* The address of the ALT_SPIS_TXFTLR register. */
1584 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
1585 
1586 /*
1587  * Register : Receive FIFO Threshold Level - RXFTLR
1588  *
1589  * Receive FIFO Threshold level.
1590  *
1591  * This register controls the threshold value for the receive FIFO memory.
1592  *
1593  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1594  *
1595  * Register Layout
1596  *
1597  * Bits | Access | Reset | Description
1598  * :-------|:-------|:------|:----------------------------
1599  * [7:0] | RW | 0x0 | ALT_SPIS_RXFTLR_RFT
1600  * [31:8] | R | 0x0 | ALT_SPIS_RXFTLR_RSVD_RXFTLR
1601  *
1602  */
1603 /*
1604  * Field : RFT
1605  *
1606  * Receive FIFO Threshold.
1607  *
1608  * Controls the level of entries (or above) at which the receive FIFO
1609  *
1610  * controller triggers an interrupt. The FIFO depth is configurable in
1611  *
1612  * the range 2-256. This register is sized to the number of address bits
1613  *
1614  * needed to access the FIFO. If you attempt to set this value greater
1615  *
1616  * than the depth of the FIFO, this field is not written and retains its
1617  *
1618  * current value. When the number of receive FIFO entries is greater than
1619  *
1620  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
1621  *
1622  * Field Access Macros:
1623  *
1624  */
1625 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
1626 #define ALT_SPIS_RXFTLR_RFT_LSB 0
1627 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFTLR_RFT register field. */
1628 #define ALT_SPIS_RXFTLR_RFT_MSB 7
1629 /* The width in bits of the ALT_SPIS_RXFTLR_RFT register field. */
1630 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
1631 /* The mask used to set the ALT_SPIS_RXFTLR_RFT register field value. */
1632 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
1633 /* The mask used to clear the ALT_SPIS_RXFTLR_RFT register field value. */
1634 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
1635 /* The reset value of the ALT_SPIS_RXFTLR_RFT register field. */
1636 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
1637 /* Extracts the ALT_SPIS_RXFTLR_RFT field value from a register. */
1638 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1639 /* Produces a ALT_SPIS_RXFTLR_RFT register field value suitable for setting the register. */
1640 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1641 
1642 /*
1643  * Field : RSVD_RXFTLR
1644  *
1645  * Reserved bits - Read Only
1646  *
1647  * Field Access Macros:
1648  *
1649  */
1650 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field. */
1651 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_LSB 8
1652 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field. */
1653 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_MSB 31
1654 /* The width in bits of the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field. */
1655 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_WIDTH 24
1656 /* The mask used to set the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field value. */
1657 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_SET_MSK 0xffffff00
1658 /* The mask used to clear the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field value. */
1659 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_CLR_MSK 0x000000ff
1660 /* The reset value of the ALT_SPIS_RXFTLR_RSVD_RXFTLR register field. */
1661 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_RESET 0x0
1662 /* Extracts the ALT_SPIS_RXFTLR_RSVD_RXFTLR field value from a register. */
1663 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1664 /* Produces a ALT_SPIS_RXFTLR_RSVD_RXFTLR register field value suitable for setting the register. */
1665 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1666 
1667 #ifndef __ASSEMBLY__
1668 /*
1669  * WARNING: The C register and register group struct declarations are provided for
1670  * convenience and illustrative purposes. They should, however, be used with
1671  * caution as the C language standard provides no guarantees about the alignment or
1672  * atomicity of device memory accesses. The recommended practice for coding device
1673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1675  * alt_write_dword() functions for 64 bit registers.
1676  *
1677  * The struct declaration for register ALT_SPIS_RXFTLR.
1678  */
1679 struct ALT_SPIS_RXFTLR_s
1680 {
1681  volatile uint32_t RFT : 8; /* ALT_SPIS_RXFTLR_RFT */
1682  const volatile uint32_t RSVD_RXFTLR : 24; /* ALT_SPIS_RXFTLR_RSVD_RXFTLR */
1683 };
1684 
1685 /* The typedef declaration for register ALT_SPIS_RXFTLR. */
1686 typedef struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
1687 #endif /* __ASSEMBLY__ */
1688 
1689 /* The reset value of the ALT_SPIS_RXFTLR register. */
1690 #define ALT_SPIS_RXFTLR_RESET 0x00000000
1691 /* The byte offset of the ALT_SPIS_RXFTLR register from the beginning of the component. */
1692 #define ALT_SPIS_RXFTLR_OFST 0x1c
1693 /* The address of the ALT_SPIS_RXFTLR register. */
1694 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
1695 
1696 /*
1697  * Register : Transmit FIFO Level Register - TXFLR
1698  *
1699  * Transmit FIFO Level Register
1700  *
1701  * Register Layout
1702  *
1703  * Bits | Access | Reset | Description
1704  * :-------|:-------|:------|:--------------------------
1705  * [8:0] | R | 0x0 | ALT_SPIS_TXFLR_TXTFL
1706  * [31:9] | R | 0x0 | ALT_SPIS_TXFLR_RSVD_TXFLR
1707  *
1708  */
1709 /*
1710  * Field : TXTFL
1711  *
1712  * Transmit FIFO Level.
1713  *
1714  * Contains the number of valid data entries in the transmit FIFO.
1715  *
1716  * Field Access Macros:
1717  *
1718  */
1719 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
1720 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
1721 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFLR_TXTFL register field. */
1722 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
1723 /* The width in bits of the ALT_SPIS_TXFLR_TXTFL register field. */
1724 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
1725 /* The mask used to set the ALT_SPIS_TXFLR_TXTFL register field value. */
1726 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
1727 /* The mask used to clear the ALT_SPIS_TXFLR_TXTFL register field value. */
1728 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1729 /* The reset value of the ALT_SPIS_TXFLR_TXTFL register field. */
1730 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
1731 /* Extracts the ALT_SPIS_TXFLR_TXTFL field value from a register. */
1732 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1733 /* Produces a ALT_SPIS_TXFLR_TXTFL register field value suitable for setting the register. */
1734 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1735 
1736 /*
1737  * Field : RSVD_TXFLR
1738  *
1739  * Reserved bits - Read Only
1740  *
1741  * Field Access Macros:
1742  *
1743  */
1744 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXFLR_RSVD_TXFLR register field. */
1745 #define ALT_SPIS_TXFLR_RSVD_TXFLR_LSB 9
1746 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXFLR_RSVD_TXFLR register field. */
1747 #define ALT_SPIS_TXFLR_RSVD_TXFLR_MSB 31
1748 /* The width in bits of the ALT_SPIS_TXFLR_RSVD_TXFLR register field. */
1749 #define ALT_SPIS_TXFLR_RSVD_TXFLR_WIDTH 23
1750 /* The mask used to set the ALT_SPIS_TXFLR_RSVD_TXFLR register field value. */
1751 #define ALT_SPIS_TXFLR_RSVD_TXFLR_SET_MSK 0xfffffe00
1752 /* The mask used to clear the ALT_SPIS_TXFLR_RSVD_TXFLR register field value. */
1753 #define ALT_SPIS_TXFLR_RSVD_TXFLR_CLR_MSK 0x000001ff
1754 /* The reset value of the ALT_SPIS_TXFLR_RSVD_TXFLR register field. */
1755 #define ALT_SPIS_TXFLR_RSVD_TXFLR_RESET 0x0
1756 /* Extracts the ALT_SPIS_TXFLR_RSVD_TXFLR field value from a register. */
1757 #define ALT_SPIS_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
1758 /* Produces a ALT_SPIS_TXFLR_RSVD_TXFLR register field value suitable for setting the register. */
1759 #define ALT_SPIS_TXFLR_RSVD_TXFLR_SET(value) (((value) << 9) & 0xfffffe00)
1760 
1761 #ifndef __ASSEMBLY__
1762 /*
1763  * WARNING: The C register and register group struct declarations are provided for
1764  * convenience and illustrative purposes. They should, however, be used with
1765  * caution as the C language standard provides no guarantees about the alignment or
1766  * atomicity of device memory accesses. The recommended practice for coding device
1767  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1768  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1769  * alt_write_dword() functions for 64 bit registers.
1770  *
1771  * The struct declaration for register ALT_SPIS_TXFLR.
1772  */
1773 struct ALT_SPIS_TXFLR_s
1774 {
1775  const volatile uint32_t TXTFL : 9; /* ALT_SPIS_TXFLR_TXTFL */
1776  const volatile uint32_t RSVD_TXFLR : 23; /* ALT_SPIS_TXFLR_RSVD_TXFLR */
1777 };
1778 
1779 /* The typedef declaration for register ALT_SPIS_TXFLR. */
1780 typedef struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
1781 #endif /* __ASSEMBLY__ */
1782 
1783 /* The reset value of the ALT_SPIS_TXFLR register. */
1784 #define ALT_SPIS_TXFLR_RESET 0x00000000
1785 /* The byte offset of the ALT_SPIS_TXFLR register from the beginning of the component. */
1786 #define ALT_SPIS_TXFLR_OFST 0x20
1787 /* The address of the ALT_SPIS_TXFLR register. */
1788 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
1789 
1790 /*
1791  * Register : Receive FIFO Level Register - RXFLR
1792  *
1793  * Receive FIFO Level Register
1794  *
1795  * Register Layout
1796  *
1797  * Bits | Access | Reset | Description
1798  * :-------|:-------|:------|:--------------------------
1799  * [8:0] | R | 0x0 | ALT_SPIS_RXFLR_RXTFL
1800  * [31:9] | R | 0x0 | ALT_SPIS_RXFLR_RSVD_RXFLR
1801  *
1802  */
1803 /*
1804  * Field : RXTFL
1805  *
1806  * Receive FIFO Level.
1807  *
1808  * Contains the number of valid data entries in the receive FIFO.
1809  *
1810  * Field Access Macros:
1811  *
1812  */
1813 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
1814 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
1815 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFLR_RXTFL register field. */
1816 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
1817 /* The width in bits of the ALT_SPIS_RXFLR_RXTFL register field. */
1818 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
1819 /* The mask used to set the ALT_SPIS_RXFLR_RXTFL register field value. */
1820 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
1821 /* The mask used to clear the ALT_SPIS_RXFLR_RXTFL register field value. */
1822 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1823 /* The reset value of the ALT_SPIS_RXFLR_RXTFL register field. */
1824 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
1825 /* Extracts the ALT_SPIS_RXFLR_RXTFL field value from a register. */
1826 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1827 /* Produces a ALT_SPIS_RXFLR_RXTFL register field value suitable for setting the register. */
1828 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1829 
1830 /*
1831  * Field : RSVD_RXFLR
1832  *
1833  * Reserved bits - Read Only
1834  *
1835  * Field Access Macros:
1836  *
1837  */
1838 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXFLR_RSVD_RXFLR register field. */
1839 #define ALT_SPIS_RXFLR_RSVD_RXFLR_LSB 9
1840 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXFLR_RSVD_RXFLR register field. */
1841 #define ALT_SPIS_RXFLR_RSVD_RXFLR_MSB 31
1842 /* The width in bits of the ALT_SPIS_RXFLR_RSVD_RXFLR register field. */
1843 #define ALT_SPIS_RXFLR_RSVD_RXFLR_WIDTH 23
1844 /* The mask used to set the ALT_SPIS_RXFLR_RSVD_RXFLR register field value. */
1845 #define ALT_SPIS_RXFLR_RSVD_RXFLR_SET_MSK 0xfffffe00
1846 /* The mask used to clear the ALT_SPIS_RXFLR_RSVD_RXFLR register field value. */
1847 #define ALT_SPIS_RXFLR_RSVD_RXFLR_CLR_MSK 0x000001ff
1848 /* The reset value of the ALT_SPIS_RXFLR_RSVD_RXFLR register field. */
1849 #define ALT_SPIS_RXFLR_RSVD_RXFLR_RESET 0x0
1850 /* Extracts the ALT_SPIS_RXFLR_RSVD_RXFLR field value from a register. */
1851 #define ALT_SPIS_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
1852 /* Produces a ALT_SPIS_RXFLR_RSVD_RXFLR register field value suitable for setting the register. */
1853 #define ALT_SPIS_RXFLR_RSVD_RXFLR_SET(value) (((value) << 9) & 0xfffffe00)
1854 
1855 #ifndef __ASSEMBLY__
1856 /*
1857  * WARNING: The C register and register group struct declarations are provided for
1858  * convenience and illustrative purposes. They should, however, be used with
1859  * caution as the C language standard provides no guarantees about the alignment or
1860  * atomicity of device memory accesses. The recommended practice for coding device
1861  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1862  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1863  * alt_write_dword() functions for 64 bit registers.
1864  *
1865  * The struct declaration for register ALT_SPIS_RXFLR.
1866  */
1867 struct ALT_SPIS_RXFLR_s
1868 {
1869  const volatile uint32_t RXTFL : 9; /* ALT_SPIS_RXFLR_RXTFL */
1870  const volatile uint32_t RSVD_RXFLR : 23; /* ALT_SPIS_RXFLR_RSVD_RXFLR */
1871 };
1872 
1873 /* The typedef declaration for register ALT_SPIS_RXFLR. */
1874 typedef struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1875 #endif /* __ASSEMBLY__ */
1876 
1877 /* The reset value of the ALT_SPIS_RXFLR register. */
1878 #define ALT_SPIS_RXFLR_RESET 0x00000000
1879 /* The byte offset of the ALT_SPIS_RXFLR register from the beginning of the component. */
1880 #define ALT_SPIS_RXFLR_OFST 0x24
1881 /* The address of the ALT_SPIS_RXFLR register. */
1882 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1883 
1884 /*
1885  * Register : Status Register - SR
1886  *
1887  * Status Register.
1888  *
1889  * This is a read-only register used to indicate the current transfer status,
1890  *
1891  * FIFO status, and any transmission/reception errors that may have occurred.
1892  *
1893  * The status register may be read at any time. None of the bits in this
1894  *
1895  * register request an interrupt.
1896  *
1897  * Register Layout
1898  *
1899  * Bits | Access | Reset | Description
1900  * :-------|:-------|:------|:----------------------
1901  * [0] | R | 0x0 | ALT_SPIS_SR_BUSY
1902  * [1] | R | 0x1 | ALT_SPIS_SR_TFNF
1903  * [2] | R | 0x1 | ALT_SPIS_SR_TFE
1904  * [3] | R | 0x0 | ALT_SPIS_SR_RFNE
1905  * [4] | R | 0x0 | ALT_SPIS_SR_RFF
1906  * [5] | R | 0x0 | ALT_SPIS_SR_TXE
1907  * [6] | R | 0x0 | ALT_SPIS_SR_RSVD_DCOL
1908  * [31:7] | R | 0x0 | ALT_SPIS_SR_RSVD_SR
1909  *
1910  */
1911 /*
1912  * Field : BUSY
1913  *
1914  * SSI Busy Flag.
1915  *
1916  * When set, indicates that a serial transfer is in progress; when cleared
1917  *
1918  * indicates that the DW_apb_ssi is idle or disabled.
1919  *
1920  * 0 - DW_apb_ssi is idle or disabled
1921  *
1922  * 1 - DW_apb_ssi is actively transferring data
1923  *
1924  * Field Enumeration Values:
1925  *
1926  * Enum | Value | Description
1927  * :----------------------------|:------|:---------------------
1928  * ALT_SPIS_SR_BUSY_E_INACTIVE | 0x0 | SSI is Idle/Disabled
1929  * ALT_SPIS_SR_BUSY_E_ACTIVE | 0x1 | SSI is Active
1930  *
1931  * Field Access Macros:
1932  *
1933  */
1934 /*
1935  * Enumerated value for register field ALT_SPIS_SR_BUSY
1936  *
1937  * SSI is Idle/Disabled
1938  */
1939 #define ALT_SPIS_SR_BUSY_E_INACTIVE 0x0
1940 /*
1941  * Enumerated value for register field ALT_SPIS_SR_BUSY
1942  *
1943  * SSI is Active
1944  */
1945 #define ALT_SPIS_SR_BUSY_E_ACTIVE 0x1
1946 
1947 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_BUSY register field. */
1948 #define ALT_SPIS_SR_BUSY_LSB 0
1949 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_BUSY register field. */
1950 #define ALT_SPIS_SR_BUSY_MSB 0
1951 /* The width in bits of the ALT_SPIS_SR_BUSY register field. */
1952 #define ALT_SPIS_SR_BUSY_WIDTH 1
1953 /* The mask used to set the ALT_SPIS_SR_BUSY register field value. */
1954 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1955 /* The mask used to clear the ALT_SPIS_SR_BUSY register field value. */
1956 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1957 /* The reset value of the ALT_SPIS_SR_BUSY register field. */
1958 #define ALT_SPIS_SR_BUSY_RESET 0x0
1959 /* Extracts the ALT_SPIS_SR_BUSY field value from a register. */
1960 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1961 /* Produces a ALT_SPIS_SR_BUSY register field value suitable for setting the register. */
1962 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1963 
1964 /*
1965  * Field : TFNF
1966  *
1967  * Transmit FIFO Not Full. Set when the transmit FIFO contains one or more
1968  *
1969  * empty locations, and is cleared when the FIFO is full.
1970  *
1971  * 0 - Transmit FIFO is full
1972  *
1973  * 1 - Transmit FIFO is not full
1974  *
1975  * Field Enumeration Values:
1976  *
1977  * Enum | Value | Description
1978  * :----------------------------|:------|:--------------------
1979  * ALT_SPIS_SR_TFNF_E_FULL | 0x0 | Tx FIFO is full
1980  * ALT_SPIS_SR_TFNF_E_NOT_FULL | 0x1 | Tx FIFO is not Full
1981  *
1982  * Field Access Macros:
1983  *
1984  */
1985 /*
1986  * Enumerated value for register field ALT_SPIS_SR_TFNF
1987  *
1988  * Tx FIFO is full
1989  */
1990 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1991 /*
1992  * Enumerated value for register field ALT_SPIS_SR_TFNF
1993  *
1994  * Tx FIFO is not Full
1995  */
1996 #define ALT_SPIS_SR_TFNF_E_NOT_FULL 0x1
1997 
1998 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFNF register field. */
1999 #define ALT_SPIS_SR_TFNF_LSB 1
2000 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFNF register field. */
2001 #define ALT_SPIS_SR_TFNF_MSB 1
2002 /* The width in bits of the ALT_SPIS_SR_TFNF register field. */
2003 #define ALT_SPIS_SR_TFNF_WIDTH 1
2004 /* The mask used to set the ALT_SPIS_SR_TFNF register field value. */
2005 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
2006 /* The mask used to clear the ALT_SPIS_SR_TFNF register field value. */
2007 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
2008 /* The reset value of the ALT_SPIS_SR_TFNF register field. */
2009 #define ALT_SPIS_SR_TFNF_RESET 0x1
2010 /* Extracts the ALT_SPIS_SR_TFNF field value from a register. */
2011 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
2012 /* Produces a ALT_SPIS_SR_TFNF register field value suitable for setting the register. */
2013 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
2014 
2015 /*
2016  * Field : TFE
2017  *
2018  * Transmit FIFO Empty.
2019  *
2020  * When the transmit FIFO is completely empty, this bit is set. When the
2021  *
2022  * transmit FIFO contains one or more valid entries, this bit is cleared.
2023  *
2024  * This bit field does not request an interrupt.
2025  *
2026  * 0 - Transmit FIFO is not empty
2027  *
2028  * 1 - Transmit FIFO is empty
2029  *
2030  * Field Enumeration Values:
2031  *
2032  * Enum | Value | Description
2033  * :----------------------------|:------|:--------------------
2034  * ALT_SPIS_SR_TFE_E_NOT_EMPTY | 0x0 | Tx FIFO is nonempty
2035  * ALT_SPIS_SR_TFE_E_EMPTY | 0x1 | Tx FIFO is empty
2036  *
2037  * Field Access Macros:
2038  *
2039  */
2040 /*
2041  * Enumerated value for register field ALT_SPIS_SR_TFE
2042  *
2043  * Tx FIFO is nonempty
2044  */
2045 #define ALT_SPIS_SR_TFE_E_NOT_EMPTY 0x0
2046 /*
2047  * Enumerated value for register field ALT_SPIS_SR_TFE
2048  *
2049  * Tx FIFO is empty
2050  */
2051 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
2052 
2053 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFE register field. */
2054 #define ALT_SPIS_SR_TFE_LSB 2
2055 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFE register field. */
2056 #define ALT_SPIS_SR_TFE_MSB 2
2057 /* The width in bits of the ALT_SPIS_SR_TFE register field. */
2058 #define ALT_SPIS_SR_TFE_WIDTH 1
2059 /* The mask used to set the ALT_SPIS_SR_TFE register field value. */
2060 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
2061 /* The mask used to clear the ALT_SPIS_SR_TFE register field value. */
2062 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
2063 /* The reset value of the ALT_SPIS_SR_TFE register field. */
2064 #define ALT_SPIS_SR_TFE_RESET 0x1
2065 /* Extracts the ALT_SPIS_SR_TFE field value from a register. */
2066 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
2067 /* Produces a ALT_SPIS_SR_TFE register field value suitable for setting the register. */
2068 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
2069 
2070 /*
2071  * Field : RFNE
2072  *
2073  * Receive FIFO Not Empty.
2074  *
2075  * Set when the receive FIFO contains one or more entries and is cleared
2076  *
2077  * when the receive FIFO is empty. This bit can be polled by software to
2078  *
2079  * completely empty the receive FIFO.
2080  *
2081  * 0 - Receive FIFO is empty
2082  *
2083  * 1 - Receive FIFO is not empty
2084  *
2085  * Field Enumeration Values:
2086  *
2087  * Enum | Value | Description
2088  * :-----------------------------|:------|:--------------------
2089  * ALT_SPIS_SR_RFNE_E_EMPTY | 0x0 | Rx FIFO is empty
2090  * ALT_SPIS_SR_RFNE_E_NOT_EMPTY | 0x1 | Rx FIFO is nonempty
2091  *
2092  * Field Access Macros:
2093  *
2094  */
2095 /*
2096  * Enumerated value for register field ALT_SPIS_SR_RFNE
2097  *
2098  * Rx FIFO is empty
2099  */
2100 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
2101 /*
2102  * Enumerated value for register field ALT_SPIS_SR_RFNE
2103  *
2104  * Rx FIFO is nonempty
2105  */
2106 #define ALT_SPIS_SR_RFNE_E_NOT_EMPTY 0x1
2107 
2108 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFNE register field. */
2109 #define ALT_SPIS_SR_RFNE_LSB 3
2110 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFNE register field. */
2111 #define ALT_SPIS_SR_RFNE_MSB 3
2112 /* The width in bits of the ALT_SPIS_SR_RFNE register field. */
2113 #define ALT_SPIS_SR_RFNE_WIDTH 1
2114 /* The mask used to set the ALT_SPIS_SR_RFNE register field value. */
2115 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
2116 /* The mask used to clear the ALT_SPIS_SR_RFNE register field value. */
2117 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
2118 /* The reset value of the ALT_SPIS_SR_RFNE register field. */
2119 #define ALT_SPIS_SR_RFNE_RESET 0x0
2120 /* Extracts the ALT_SPIS_SR_RFNE field value from a register. */
2121 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
2122 /* Produces a ALT_SPIS_SR_RFNE register field value suitable for setting the register. */
2123 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
2124 
2125 /*
2126  * Field : RFF
2127  *
2128  * Receive FIFO Full. When the receive FIFO is completely full, this bit
2129  *
2130  * is set. When the receive FIFO contains one or more empty location, this
2131  *
2132  * bit is cleared.
2133  *
2134  * 0 - Receive FIFO is not full
2135  *
2136  * 1 - Receive FIFO is full
2137  *
2138  * Field Enumeration Values:
2139  *
2140  * Enum | Value | Description
2141  * :---------------------------|:------|:--------------------
2142  * ALT_SPIS_SR_RFF_E_NOT_FULL | 0x0 | RX FIFO is not full
2143  * ALT_SPIS_SR_RFF_E_FULL | 0x1 | Rx FIFO is full
2144  *
2145  * Field Access Macros:
2146  *
2147  */
2148 /*
2149  * Enumerated value for register field ALT_SPIS_SR_RFF
2150  *
2151  * RX FIFO is not full
2152  */
2153 #define ALT_SPIS_SR_RFF_E_NOT_FULL 0x0
2154 /*
2155  * Enumerated value for register field ALT_SPIS_SR_RFF
2156  *
2157  * Rx FIFO is full
2158  */
2159 #define ALT_SPIS_SR_RFF_E_FULL 0x1
2160 
2161 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFF register field. */
2162 #define ALT_SPIS_SR_RFF_LSB 4
2163 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFF register field. */
2164 #define ALT_SPIS_SR_RFF_MSB 4
2165 /* The width in bits of the ALT_SPIS_SR_RFF register field. */
2166 #define ALT_SPIS_SR_RFF_WIDTH 1
2167 /* The mask used to set the ALT_SPIS_SR_RFF register field value. */
2168 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
2169 /* The mask used to clear the ALT_SPIS_SR_RFF register field value. */
2170 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
2171 /* The reset value of the ALT_SPIS_SR_RFF register field. */
2172 #define ALT_SPIS_SR_RFF_RESET 0x0
2173 /* Extracts the ALT_SPIS_SR_RFF field value from a register. */
2174 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
2175 /* Produces a ALT_SPIS_SR_RFF register field value suitable for setting the register. */
2176 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
2177 
2178 /*
2179  * Field : TXE
2180  *
2181  * Transmission Error.
2182  *
2183  * Set if the transmit FIFO is empty when a transfer is started. This bit can
2184  *
2185  * be set only when the DW_apb_ssi is configured as a slave device. Data from
2186  *
2187  * the previous transmission is resent on the txd line. This bit is cleared
2188  *
2189  * when read.
2190  *
2191  * 0 - No error
2192  *
2193  * 1 - Transmission error
2194  *
2195  * Field Enumeration Values:
2196  *
2197  * Enum | Value | Description
2198  * :---------------------------|:------|:-------------------
2199  * ALT_SPIS_SR_TXE_E_NO_ERROR | 0x0 | No Error Condition
2200  * ALT_SPIS_SR_TXE_E_TX_ERROR | 0x1 | Transmission Error
2201  *
2202  * Field Access Macros:
2203  *
2204  */
2205 /*
2206  * Enumerated value for register field ALT_SPIS_SR_TXE
2207  *
2208  * No Error Condition
2209  */
2210 #define ALT_SPIS_SR_TXE_E_NO_ERROR 0x0
2211 /*
2212  * Enumerated value for register field ALT_SPIS_SR_TXE
2213  *
2214  * Transmission Error
2215  */
2216 #define ALT_SPIS_SR_TXE_E_TX_ERROR 0x1
2217 
2218 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TXE register field. */
2219 #define ALT_SPIS_SR_TXE_LSB 5
2220 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TXE register field. */
2221 #define ALT_SPIS_SR_TXE_MSB 5
2222 /* The width in bits of the ALT_SPIS_SR_TXE register field. */
2223 #define ALT_SPIS_SR_TXE_WIDTH 1
2224 /* The mask used to set the ALT_SPIS_SR_TXE register field value. */
2225 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
2226 /* The mask used to clear the ALT_SPIS_SR_TXE register field value. */
2227 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
2228 /* The reset value of the ALT_SPIS_SR_TXE register field. */
2229 #define ALT_SPIS_SR_TXE_RESET 0x0
2230 /* Extracts the ALT_SPIS_SR_TXE field value from a register. */
2231 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
2232 /* Produces a ALT_SPIS_SR_TXE register field value suitable for setting the register. */
2233 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
2234 
2235 /*
2236  * Field : RSVD_DCOL
2237  *
2238  * Reserved field- read-only
2239  *
2240  * Field Access Macros:
2241  *
2242  */
2243 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RSVD_DCOL register field. */
2244 #define ALT_SPIS_SR_RSVD_DCOL_LSB 6
2245 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RSVD_DCOL register field. */
2246 #define ALT_SPIS_SR_RSVD_DCOL_MSB 6
2247 /* The width in bits of the ALT_SPIS_SR_RSVD_DCOL register field. */
2248 #define ALT_SPIS_SR_RSVD_DCOL_WIDTH 1
2249 /* The mask used to set the ALT_SPIS_SR_RSVD_DCOL register field value. */
2250 #define ALT_SPIS_SR_RSVD_DCOL_SET_MSK 0x00000040
2251 /* The mask used to clear the ALT_SPIS_SR_RSVD_DCOL register field value. */
2252 #define ALT_SPIS_SR_RSVD_DCOL_CLR_MSK 0xffffffbf
2253 /* The reset value of the ALT_SPIS_SR_RSVD_DCOL register field. */
2254 #define ALT_SPIS_SR_RSVD_DCOL_RESET 0x0
2255 /* Extracts the ALT_SPIS_SR_RSVD_DCOL field value from a register. */
2256 #define ALT_SPIS_SR_RSVD_DCOL_GET(value) (((value) & 0x00000040) >> 6)
2257 /* Produces a ALT_SPIS_SR_RSVD_DCOL register field value suitable for setting the register. */
2258 #define ALT_SPIS_SR_RSVD_DCOL_SET(value) (((value) << 6) & 0x00000040)
2259 
2260 /*
2261  * Field : RSVD_SR
2262  *
2263  * Reserved bits - Read Only
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RSVD_SR register field. */
2269 #define ALT_SPIS_SR_RSVD_SR_LSB 7
2270 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RSVD_SR register field. */
2271 #define ALT_SPIS_SR_RSVD_SR_MSB 31
2272 /* The width in bits of the ALT_SPIS_SR_RSVD_SR register field. */
2273 #define ALT_SPIS_SR_RSVD_SR_WIDTH 25
2274 /* The mask used to set the ALT_SPIS_SR_RSVD_SR register field value. */
2275 #define ALT_SPIS_SR_RSVD_SR_SET_MSK 0xffffff80
2276 /* The mask used to clear the ALT_SPIS_SR_RSVD_SR register field value. */
2277 #define ALT_SPIS_SR_RSVD_SR_CLR_MSK 0x0000007f
2278 /* The reset value of the ALT_SPIS_SR_RSVD_SR register field. */
2279 #define ALT_SPIS_SR_RSVD_SR_RESET 0x0
2280 /* Extracts the ALT_SPIS_SR_RSVD_SR field value from a register. */
2281 #define ALT_SPIS_SR_RSVD_SR_GET(value) (((value) & 0xffffff80) >> 7)
2282 /* Produces a ALT_SPIS_SR_RSVD_SR register field value suitable for setting the register. */
2283 #define ALT_SPIS_SR_RSVD_SR_SET(value) (((value) << 7) & 0xffffff80)
2284 
2285 #ifndef __ASSEMBLY__
2286 /*
2287  * WARNING: The C register and register group struct declarations are provided for
2288  * convenience and illustrative purposes. They should, however, be used with
2289  * caution as the C language standard provides no guarantees about the alignment or
2290  * atomicity of device memory accesses. The recommended practice for coding device
2291  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2292  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2293  * alt_write_dword() functions for 64 bit registers.
2294  *
2295  * The struct declaration for register ALT_SPIS_SR.
2296  */
2297 struct ALT_SPIS_SR_s
2298 {
2299  const volatile uint32_t BUSY : 1; /* ALT_SPIS_SR_BUSY */
2300  const volatile uint32_t TFNF : 1; /* ALT_SPIS_SR_TFNF */
2301  const volatile uint32_t TFE : 1; /* ALT_SPIS_SR_TFE */
2302  const volatile uint32_t RFNE : 1; /* ALT_SPIS_SR_RFNE */
2303  const volatile uint32_t RFF : 1; /* ALT_SPIS_SR_RFF */
2304  const volatile uint32_t TXE : 1; /* ALT_SPIS_SR_TXE */
2305  const volatile uint32_t RSVD_DCOL : 1; /* ALT_SPIS_SR_RSVD_DCOL */
2306  const volatile uint32_t RSVD_SR : 25; /* ALT_SPIS_SR_RSVD_SR */
2307 };
2308 
2309 /* The typedef declaration for register ALT_SPIS_SR. */
2310 typedef struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
2311 #endif /* __ASSEMBLY__ */
2312 
2313 /* The reset value of the ALT_SPIS_SR register. */
2314 #define ALT_SPIS_SR_RESET 0x00000006
2315 /* The byte offset of the ALT_SPIS_SR register from the beginning of the component. */
2316 #define ALT_SPIS_SR_OFST 0x28
2317 /* The address of the ALT_SPIS_SR register. */
2318 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
2319 
2320 /*
2321  * Register : Interrupt Mask Register - IMR
2322  *
2323  * Interrupt Mask Register
2324  *
2325  * Register Layout
2326  *
2327  * Bits | Access | Reset | Description
2328  * :-------|:-------|:------|:------------------------
2329  * [0] | RW | 0x1 | ALT_SPIS_IMR_TXEIM
2330  * [1] | RW | 0x1 | ALT_SPIS_IMR_TXOIM
2331  * [2] | RW | 0x1 | ALT_SPIS_IMR_RXUIM
2332  * [3] | RW | 0x1 | ALT_SPIS_IMR_RXOIM
2333  * [4] | RW | 0x1 | ALT_SPIS_IMR_RXFIM
2334  * [5] | R | 0x0 | ALT_SPIS_IMR_RSVD_MSTIM
2335  * [31:6] | R | 0x0 | ALT_SPIS_IMR_RSVD_IMR
2336  *
2337  */
2338 /*
2339  * Field : TXEIM
2340  *
2341  * Transmit FIFO Empty Interrupt Mask
2342  *
2343  * 0 - ssi_txe_intr interrupt is masked
2344  *
2345  * 1 - ssi_txe_intr interrupt is not masked
2346  *
2347  * Field Enumeration Values:
2348  *
2349  * Enum | Value | Description
2350  * :------------------------------|:------|:----------------------------------
2351  * ALT_SPIS_IMR_TXEIM_E_MASKED | 0x0 | TX FIFO Empty Interrupt is masked
2352  * ALT_SPIS_IMR_TXEIM_E_UNMASKED | 0x1 | TX FIFO Empty Interrupt un-masked
2353  *
2354  * Field Access Macros:
2355  *
2356  */
2357 /*
2358  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
2359  *
2360  * TX FIFO Empty Interrupt is masked
2361  */
2362 #define ALT_SPIS_IMR_TXEIM_E_MASKED 0x0
2363 /*
2364  * Enumerated value for register field ALT_SPIS_IMR_TXEIM
2365  *
2366  * TX FIFO Empty Interrupt un-masked
2367  */
2368 #define ALT_SPIS_IMR_TXEIM_E_UNMASKED 0x1
2369 
2370 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXEIM register field. */
2371 #define ALT_SPIS_IMR_TXEIM_LSB 0
2372 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXEIM register field. */
2373 #define ALT_SPIS_IMR_TXEIM_MSB 0
2374 /* The width in bits of the ALT_SPIS_IMR_TXEIM register field. */
2375 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
2376 /* The mask used to set the ALT_SPIS_IMR_TXEIM register field value. */
2377 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
2378 /* The mask used to clear the ALT_SPIS_IMR_TXEIM register field value. */
2379 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
2380 /* The reset value of the ALT_SPIS_IMR_TXEIM register field. */
2381 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
2382 /* Extracts the ALT_SPIS_IMR_TXEIM field value from a register. */
2383 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2384 /* Produces a ALT_SPIS_IMR_TXEIM register field value suitable for setting the register. */
2385 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2386 
2387 /*
2388  * Field : TXOIM
2389  *
2390  * Transmit FIFO Overflow Interrupt Mask
2391  *
2392  * 0 - ssi_txo_intr interrupt is masked
2393  *
2394  * 1 - ssi_txo_intr interrupt is not masked
2395  *
2396  * Field Enumeration Values:
2397  *
2398  * Enum | Value | Description
2399  * :------------------------------|:------|:-------------------------------------
2400  * ALT_SPIS_IMR_TXOIM_E_MASKED | 0x0 | TX FIFO Overflow Interrupt is masked
2401  * ALT_SPIS_IMR_TXOIM_E_UNMASKED | 0x1 | TX FIFO Overflow Interrupt un-masked
2402  *
2403  * Field Access Macros:
2404  *
2405  */
2406 /*
2407  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
2408  *
2409  * TX FIFO Overflow Interrupt is masked
2410  */
2411 #define ALT_SPIS_IMR_TXOIM_E_MASKED 0x0
2412 /*
2413  * Enumerated value for register field ALT_SPIS_IMR_TXOIM
2414  *
2415  * TX FIFO Overflow Interrupt un-masked
2416  */
2417 #define ALT_SPIS_IMR_TXOIM_E_UNMASKED 0x1
2418 
2419 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXOIM register field. */
2420 #define ALT_SPIS_IMR_TXOIM_LSB 1
2421 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXOIM register field. */
2422 #define ALT_SPIS_IMR_TXOIM_MSB 1
2423 /* The width in bits of the ALT_SPIS_IMR_TXOIM register field. */
2424 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
2425 /* The mask used to set the ALT_SPIS_IMR_TXOIM register field value. */
2426 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
2427 /* The mask used to clear the ALT_SPIS_IMR_TXOIM register field value. */
2428 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
2429 /* The reset value of the ALT_SPIS_IMR_TXOIM register field. */
2430 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
2431 /* Extracts the ALT_SPIS_IMR_TXOIM field value from a register. */
2432 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2433 /* Produces a ALT_SPIS_IMR_TXOIM register field value suitable for setting the register. */
2434 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2435 
2436 /*
2437  * Field : RXUIM
2438  *
2439  * Receive FIFO Underflow Interrupt Mask
2440  *
2441  * 0 - ssi_rxu_intr interrupt is masked
2442  *
2443  * 1 - ssi_rxu_intr interrupt is not masked
2444  *
2445  * Field Enumeration Values:
2446  *
2447  * Enum | Value | Description
2448  * :------------------------------|:------|:--------------------------------------
2449  * ALT_SPIS_IMR_RXUIM_E_MASKED | 0x0 | RX FIFO Underflow Interrupt is masked
2450  * ALT_SPIS_IMR_RXUIM_E_UNMASKED | 0x1 | RX FIFO Underflow Interrupt un-masked
2451  *
2452  * Field Access Macros:
2453  *
2454  */
2455 /*
2456  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
2457  *
2458  * RX FIFO Underflow Interrupt is masked
2459  */
2460 #define ALT_SPIS_IMR_RXUIM_E_MASKED 0x0
2461 /*
2462  * Enumerated value for register field ALT_SPIS_IMR_RXUIM
2463  *
2464  * RX FIFO Underflow Interrupt un-masked
2465  */
2466 #define ALT_SPIS_IMR_RXUIM_E_UNMASKED 0x1
2467 
2468 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXUIM register field. */
2469 #define ALT_SPIS_IMR_RXUIM_LSB 2
2470 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXUIM register field. */
2471 #define ALT_SPIS_IMR_RXUIM_MSB 2
2472 /* The width in bits of the ALT_SPIS_IMR_RXUIM register field. */
2473 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
2474 /* The mask used to set the ALT_SPIS_IMR_RXUIM register field value. */
2475 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
2476 /* The mask used to clear the ALT_SPIS_IMR_RXUIM register field value. */
2477 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
2478 /* The reset value of the ALT_SPIS_IMR_RXUIM register field. */
2479 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
2480 /* Extracts the ALT_SPIS_IMR_RXUIM field value from a register. */
2481 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2482 /* Produces a ALT_SPIS_IMR_RXUIM register field value suitable for setting the register. */
2483 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2484 
2485 /*
2486  * Field : RXOIM
2487  *
2488  * Receive FIFO Overflow Interrupt Mask
2489  *
2490  * 0 - ssi_rxo_intr interrupt is masked
2491  *
2492  * 1 - ssi_rxo_intr interrupt is not masked
2493  *
2494  * Field Enumeration Values:
2495  *
2496  * Enum | Value | Description
2497  * :------------------------------|:------|:-------------------------------------
2498  * ALT_SPIS_IMR_RXOIM_E_MASKED | 0x0 | RX FIFO Overflow Interrupt is masked
2499  * ALT_SPIS_IMR_RXOIM_E_UNMASKED | 0x1 | RX FIFO Overflow Interrupt un-masked
2500  *
2501  * Field Access Macros:
2502  *
2503  */
2504 /*
2505  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
2506  *
2507  * RX FIFO Overflow Interrupt is masked
2508  */
2509 #define ALT_SPIS_IMR_RXOIM_E_MASKED 0x0
2510 /*
2511  * Enumerated value for register field ALT_SPIS_IMR_RXOIM
2512  *
2513  * RX FIFO Overflow Interrupt un-masked
2514  */
2515 #define ALT_SPIS_IMR_RXOIM_E_UNMASKED 0x1
2516 
2517 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXOIM register field. */
2518 #define ALT_SPIS_IMR_RXOIM_LSB 3
2519 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXOIM register field. */
2520 #define ALT_SPIS_IMR_RXOIM_MSB 3
2521 /* The width in bits of the ALT_SPIS_IMR_RXOIM register field. */
2522 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
2523 /* The mask used to set the ALT_SPIS_IMR_RXOIM register field value. */
2524 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
2525 /* The mask used to clear the ALT_SPIS_IMR_RXOIM register field value. */
2526 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
2527 /* The reset value of the ALT_SPIS_IMR_RXOIM register field. */
2528 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
2529 /* Extracts the ALT_SPIS_IMR_RXOIM field value from a register. */
2530 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2531 /* Produces a ALT_SPIS_IMR_RXOIM register field value suitable for setting the register. */
2532 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2533 
2534 /*
2535  * Field : RXFIM
2536  *
2537  * Receive FIFO Full Interrupt Mask
2538  *
2539  * 0 - ssi_rxf_intr interrupt is masked
2540  *
2541  * 1 - ssi_rxf_intr interrupt is not masked
2542  *
2543  * Field Enumeration Values:
2544  *
2545  * Enum | Value | Description
2546  * :------------------------------|:------|:---------------------------------
2547  * ALT_SPIS_IMR_RXFIM_E_MASKED | 0x0 | RX FIFO Full Interrupt is masked
2548  * ALT_SPIS_IMR_RXFIM_E_UNMASKED | 0x1 | RX FIFO Full Interrupt un-masked
2549  *
2550  * Field Access Macros:
2551  *
2552  */
2553 /*
2554  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
2555  *
2556  * RX FIFO Full Interrupt is masked
2557  */
2558 #define ALT_SPIS_IMR_RXFIM_E_MASKED 0x0
2559 /*
2560  * Enumerated value for register field ALT_SPIS_IMR_RXFIM
2561  *
2562  * RX FIFO Full Interrupt un-masked
2563  */
2564 #define ALT_SPIS_IMR_RXFIM_E_UNMASKED 0x1
2565 
2566 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXFIM register field. */
2567 #define ALT_SPIS_IMR_RXFIM_LSB 4
2568 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXFIM register field. */
2569 #define ALT_SPIS_IMR_RXFIM_MSB 4
2570 /* The width in bits of the ALT_SPIS_IMR_RXFIM register field. */
2571 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
2572 /* The mask used to set the ALT_SPIS_IMR_RXFIM register field value. */
2573 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
2574 /* The mask used to clear the ALT_SPIS_IMR_RXFIM register field value. */
2575 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
2576 /* The reset value of the ALT_SPIS_IMR_RXFIM register field. */
2577 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
2578 /* Extracts the ALT_SPIS_IMR_RXFIM field value from a register. */
2579 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2580 /* Produces a ALT_SPIS_IMR_RXFIM register field value suitable for setting the register. */
2581 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2582 
2583 /*
2584  * Field : RSVD_MSTIM
2585  *
2586  * Reserved field- read-only
2587  *
2588  * Field Access Macros:
2589  *
2590  */
2591 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RSVD_MSTIM register field. */
2592 #define ALT_SPIS_IMR_RSVD_MSTIM_LSB 5
2593 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RSVD_MSTIM register field. */
2594 #define ALT_SPIS_IMR_RSVD_MSTIM_MSB 5
2595 /* The width in bits of the ALT_SPIS_IMR_RSVD_MSTIM register field. */
2596 #define ALT_SPIS_IMR_RSVD_MSTIM_WIDTH 1
2597 /* The mask used to set the ALT_SPIS_IMR_RSVD_MSTIM register field value. */
2598 #define ALT_SPIS_IMR_RSVD_MSTIM_SET_MSK 0x00000020
2599 /* The mask used to clear the ALT_SPIS_IMR_RSVD_MSTIM register field value. */
2600 #define ALT_SPIS_IMR_RSVD_MSTIM_CLR_MSK 0xffffffdf
2601 /* The reset value of the ALT_SPIS_IMR_RSVD_MSTIM register field. */
2602 #define ALT_SPIS_IMR_RSVD_MSTIM_RESET 0x0
2603 /* Extracts the ALT_SPIS_IMR_RSVD_MSTIM field value from a register. */
2604 #define ALT_SPIS_IMR_RSVD_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
2605 /* Produces a ALT_SPIS_IMR_RSVD_MSTIM register field value suitable for setting the register. */
2606 #define ALT_SPIS_IMR_RSVD_MSTIM_SET(value) (((value) << 5) & 0x00000020)
2607 
2608 /*
2609  * Field : RSVD_IMR
2610  *
2611  * Reserved bits - Read Only
2612  *
2613  * Field Access Macros:
2614  *
2615  */
2616 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RSVD_IMR register field. */
2617 #define ALT_SPIS_IMR_RSVD_IMR_LSB 6
2618 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RSVD_IMR register field. */
2619 #define ALT_SPIS_IMR_RSVD_IMR_MSB 31
2620 /* The width in bits of the ALT_SPIS_IMR_RSVD_IMR register field. */
2621 #define ALT_SPIS_IMR_RSVD_IMR_WIDTH 26
2622 /* The mask used to set the ALT_SPIS_IMR_RSVD_IMR register field value. */
2623 #define ALT_SPIS_IMR_RSVD_IMR_SET_MSK 0xffffffc0
2624 /* The mask used to clear the ALT_SPIS_IMR_RSVD_IMR register field value. */
2625 #define ALT_SPIS_IMR_RSVD_IMR_CLR_MSK 0x0000003f
2626 /* The reset value of the ALT_SPIS_IMR_RSVD_IMR register field. */
2627 #define ALT_SPIS_IMR_RSVD_IMR_RESET 0x0
2628 /* Extracts the ALT_SPIS_IMR_RSVD_IMR field value from a register. */
2629 #define ALT_SPIS_IMR_RSVD_IMR_GET(value) (((value) & 0xffffffc0) >> 6)
2630 /* Produces a ALT_SPIS_IMR_RSVD_IMR register field value suitable for setting the register. */
2631 #define ALT_SPIS_IMR_RSVD_IMR_SET(value) (((value) << 6) & 0xffffffc0)
2632 
2633 #ifndef __ASSEMBLY__
2634 /*
2635  * WARNING: The C register and register group struct declarations are provided for
2636  * convenience and illustrative purposes. They should, however, be used with
2637  * caution as the C language standard provides no guarantees about the alignment or
2638  * atomicity of device memory accesses. The recommended practice for coding device
2639  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2640  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2641  * alt_write_dword() functions for 64 bit registers.
2642  *
2643  * The struct declaration for register ALT_SPIS_IMR.
2644  */
2645 struct ALT_SPIS_IMR_s
2646 {
2647  volatile uint32_t TXEIM : 1; /* ALT_SPIS_IMR_TXEIM */
2648  volatile uint32_t TXOIM : 1; /* ALT_SPIS_IMR_TXOIM */
2649  volatile uint32_t RXUIM : 1; /* ALT_SPIS_IMR_RXUIM */
2650  volatile uint32_t RXOIM : 1; /* ALT_SPIS_IMR_RXOIM */
2651  volatile uint32_t RXFIM : 1; /* ALT_SPIS_IMR_RXFIM */
2652  const volatile uint32_t RSVD_MSTIM : 1; /* ALT_SPIS_IMR_RSVD_MSTIM */
2653  const volatile uint32_t RSVD_IMR : 26; /* ALT_SPIS_IMR_RSVD_IMR */
2654 };
2655 
2656 /* The typedef declaration for register ALT_SPIS_IMR. */
2657 typedef struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
2658 #endif /* __ASSEMBLY__ */
2659 
2660 /* The reset value of the ALT_SPIS_IMR register. */
2661 #define ALT_SPIS_IMR_RESET 0x0000001f
2662 /* The byte offset of the ALT_SPIS_IMR register from the beginning of the component. */
2663 #define ALT_SPIS_IMR_OFST 0x2c
2664 /* The address of the ALT_SPIS_IMR register. */
2665 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
2666 
2667 /*
2668  * Register : Interrupt Status Register - ISR
2669  *
2670  * Interrupt Status Register
2671  *
2672  * Register Layout
2673  *
2674  * Bits | Access | Reset | Description
2675  * :-------|:-------|:------|:------------------------
2676  * [0] | R | 0x0 | ALT_SPIS_ISR_TXEIS
2677  * [1] | R | 0x0 | ALT_SPIS_ISR_TXOIS
2678  * [2] | R | 0x0 | ALT_SPIS_ISR_RXUIS
2679  * [3] | R | 0x0 | ALT_SPIS_ISR_RXOIS
2680  * [4] | R | 0x0 | ALT_SPIS_ISR_RXFIS
2681  * [5] | R | 0x0 | ALT_SPIS_ISR_RSVD_MSTIS
2682  * [31:6] | R | 0x0 | ALT_SPIS_ISR_RSVD_ISR
2683  *
2684  */
2685 /*
2686  * Field : TXEIS
2687  *
2688  * Transmit FIFO Empty Interrupt Status
2689  *
2690  * 0 = ssi_txe_intr interrupt is not active after masking
2691  *
2692  * 1 = ssi_txe_intr interrupt is active after masking
2693  *
2694  * Field Enumeration Values:
2695  *
2696  * Enum | Value | Description
2697  * :------------------------------|:------|:----------------------------------
2698  * ALT_SPIS_ISR_TXEIS_E_INACTIVE | 0x0 | TX FIFO Empty Interrupt nonactive
2699  * ALT_SPIS_ISR_TXEIS_E_ACTIVE | 0x1 | TX FIFO Empty Interrupt is active
2700  *
2701  * Field Access Macros:
2702  *
2703  */
2704 /*
2705  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
2706  *
2707  * TX FIFO Empty Interrupt nonactive
2708  */
2709 #define ALT_SPIS_ISR_TXEIS_E_INACTIVE 0x0
2710 /*
2711  * Enumerated value for register field ALT_SPIS_ISR_TXEIS
2712  *
2713  * TX FIFO Empty Interrupt is active
2714  */
2715 #define ALT_SPIS_ISR_TXEIS_E_ACTIVE 0x1
2716 
2717 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXEIS register field. */
2718 #define ALT_SPIS_ISR_TXEIS_LSB 0
2719 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXEIS register field. */
2720 #define ALT_SPIS_ISR_TXEIS_MSB 0
2721 /* The width in bits of the ALT_SPIS_ISR_TXEIS register field. */
2722 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
2723 /* The mask used to set the ALT_SPIS_ISR_TXEIS register field value. */
2724 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
2725 /* The mask used to clear the ALT_SPIS_ISR_TXEIS register field value. */
2726 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
2727 /* The reset value of the ALT_SPIS_ISR_TXEIS register field. */
2728 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
2729 /* Extracts the ALT_SPIS_ISR_TXEIS field value from a register. */
2730 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2731 /* Produces a ALT_SPIS_ISR_TXEIS register field value suitable for setting the register. */
2732 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2733 
2734 /*
2735  * Field : TXOIS
2736  *
2737  * Transmit FIFO Overflow Interrupt Status
2738  *
2739  * 0 = ssi_txo_intr interrupt is not active after masking
2740  *
2741  * 1 = ssi_txo_intr interrupt is active after masking
2742  *
2743  * Field Enumeration Values:
2744  *
2745  * Enum | Value | Description
2746  * :------------------------------|:------|:-------------------------------------
2747  * ALT_SPIS_ISR_TXOIS_E_INACTIVE | 0x0 | TX FIFO Overflow Interrupt nonactive
2748  * ALT_SPIS_ISR_TXOIS_E_ACTIVE | 0x1 | TX FIFO Overflow Interrupt is active
2749  *
2750  * Field Access Macros:
2751  *
2752  */
2753 /*
2754  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
2755  *
2756  * TX FIFO Overflow Interrupt nonactive
2757  */
2758 #define ALT_SPIS_ISR_TXOIS_E_INACTIVE 0x0
2759 /*
2760  * Enumerated value for register field ALT_SPIS_ISR_TXOIS
2761  *
2762  * TX FIFO Overflow Interrupt is active
2763  */
2764 #define ALT_SPIS_ISR_TXOIS_E_ACTIVE 0x1
2765 
2766 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_TXOIS register field. */
2767 #define ALT_SPIS_ISR_TXOIS_LSB 1
2768 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_TXOIS register field. */
2769 #define ALT_SPIS_ISR_TXOIS_MSB 1
2770 /* The width in bits of the ALT_SPIS_ISR_TXOIS register field. */
2771 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
2772 /* The mask used to set the ALT_SPIS_ISR_TXOIS register field value. */
2773 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
2774 /* The mask used to clear the ALT_SPIS_ISR_TXOIS register field value. */
2775 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
2776 /* The reset value of the ALT_SPIS_ISR_TXOIS register field. */
2777 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
2778 /* Extracts the ALT_SPIS_ISR_TXOIS field value from a register. */
2779 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2780 /* Produces a ALT_SPIS_ISR_TXOIS register field value suitable for setting the register. */
2781 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2782 
2783 /*
2784  * Field : RXUIS
2785  *
2786  * Receive FIFO Underflow Interrupt Status
2787  *
2788  * 0 = ssi_rxu_intr interrupt is not active after masking
2789  *
2790  * 1 = ssi_rxu_intr interrupt is active after masking
2791  *
2792  * Field Enumeration Values:
2793  *
2794  * Enum | Value | Description
2795  * :------------------------------|:------|:--------------------------------------
2796  * ALT_SPIS_ISR_RXUIS_E_INACTIVE | 0x0 | RX FIFO Underflow Interrupt nonactive
2797  * ALT_SPIS_ISR_RXUIS_E_ACTIVE | 0x1 | RX FIFO underflow Interrupt is active
2798  *
2799  * Field Access Macros:
2800  *
2801  */
2802 /*
2803  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
2804  *
2805  * RX FIFO Underflow Interrupt nonactive
2806  */
2807 #define ALT_SPIS_ISR_RXUIS_E_INACTIVE 0x0
2808 /*
2809  * Enumerated value for register field ALT_SPIS_ISR_RXUIS
2810  *
2811  * RX FIFO underflow Interrupt is active
2812  */
2813 #define ALT_SPIS_ISR_RXUIS_E_ACTIVE 0x1
2814 
2815 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXUIS register field. */
2816 #define ALT_SPIS_ISR_RXUIS_LSB 2
2817 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXUIS register field. */
2818 #define ALT_SPIS_ISR_RXUIS_MSB 2
2819 /* The width in bits of the ALT_SPIS_ISR_RXUIS register field. */
2820 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
2821 /* The mask used to set the ALT_SPIS_ISR_RXUIS register field value. */
2822 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
2823 /* The mask used to clear the ALT_SPIS_ISR_RXUIS register field value. */
2824 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
2825 /* The reset value of the ALT_SPIS_ISR_RXUIS register field. */
2826 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
2827 /* Extracts the ALT_SPIS_ISR_RXUIS field value from a register. */
2828 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2829 /* Produces a ALT_SPIS_ISR_RXUIS register field value suitable for setting the register. */
2830 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2831 
2832 /*
2833  * Field : RXOIS
2834  *
2835  * Receive FIFO Overflow Interrupt Status
2836  *
2837  * 0 = ssi_rxo_intr interrupt is not active after masking
2838  *
2839  * 1 = ssi_rxo_intr interrupt is active after masking
2840  *
2841  * Field Enumeration Values:
2842  *
2843  * Enum | Value | Description
2844  * :------------------------------|:------|:-------------------------------------
2845  * ALT_SPIS_ISR_RXOIS_E_INACTIVE | 0x0 | RX FIFO Overflow Interrupt nonactive
2846  * ALT_SPIS_ISR_RXOIS_E_ACTIVE | 0x1 | RX FIFO Overflow Interrupt is active
2847  *
2848  * Field Access Macros:
2849  *
2850  */
2851 /*
2852  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
2853  *
2854  * RX FIFO Overflow Interrupt nonactive
2855  */
2856 #define ALT_SPIS_ISR_RXOIS_E_INACTIVE 0x0
2857 /*
2858  * Enumerated value for register field ALT_SPIS_ISR_RXOIS
2859  *
2860  * RX FIFO Overflow Interrupt is active
2861  */
2862 #define ALT_SPIS_ISR_RXOIS_E_ACTIVE 0x1
2863 
2864 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXOIS register field. */
2865 #define ALT_SPIS_ISR_RXOIS_LSB 3
2866 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXOIS register field. */
2867 #define ALT_SPIS_ISR_RXOIS_MSB 3
2868 /* The width in bits of the ALT_SPIS_ISR_RXOIS register field. */
2869 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
2870 /* The mask used to set the ALT_SPIS_ISR_RXOIS register field value. */
2871 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
2872 /* The mask used to clear the ALT_SPIS_ISR_RXOIS register field value. */
2873 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
2874 /* The reset value of the ALT_SPIS_ISR_RXOIS register field. */
2875 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
2876 /* Extracts the ALT_SPIS_ISR_RXOIS field value from a register. */
2877 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2878 /* Produces a ALT_SPIS_ISR_RXOIS register field value suitable for setting the register. */
2879 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2880 
2881 /*
2882  * Field : RXFIS
2883  *
2884  * Receive FIFO Full Interrupt Status
2885  *
2886  * 0 = ssi_rxf_intr interrupt is not active after masking
2887  *
2888  * 1 = ssi_rxf_intr interrupt is full after masking
2889  *
2890  * Field Enumeration Values:
2891  *
2892  * Enum | Value | Description
2893  * :------------------------------|:------|:---------------------------------
2894  * ALT_SPIS_ISR_RXFIS_E_INACTIVE | 0x0 | RX FIFO Full Interrupt nonactive
2895  * ALT_SPIS_ISR_RXFIS_E_ACTIVE | 0x1 | RX FIFO Full Interrupt is active
2896  *
2897  * Field Access Macros:
2898  *
2899  */
2900 /*
2901  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
2902  *
2903  * RX FIFO Full Interrupt nonactive
2904  */
2905 #define ALT_SPIS_ISR_RXFIS_E_INACTIVE 0x0
2906 /*
2907  * Enumerated value for register field ALT_SPIS_ISR_RXFIS
2908  *
2909  * RX FIFO Full Interrupt is active
2910  */
2911 #define ALT_SPIS_ISR_RXFIS_E_ACTIVE 0x1
2912 
2913 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RXFIS register field. */
2914 #define ALT_SPIS_ISR_RXFIS_LSB 4
2915 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RXFIS register field. */
2916 #define ALT_SPIS_ISR_RXFIS_MSB 4
2917 /* The width in bits of the ALT_SPIS_ISR_RXFIS register field. */
2918 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
2919 /* The mask used to set the ALT_SPIS_ISR_RXFIS register field value. */
2920 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
2921 /* The mask used to clear the ALT_SPIS_ISR_RXFIS register field value. */
2922 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
2923 /* The reset value of the ALT_SPIS_ISR_RXFIS register field. */
2924 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
2925 /* Extracts the ALT_SPIS_ISR_RXFIS field value from a register. */
2926 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2927 /* Produces a ALT_SPIS_ISR_RXFIS register field value suitable for setting the register. */
2928 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2929 
2930 /*
2931  * Field : RSVD_MSTIS
2932  *
2933  * Reserved field- read-only
2934  *
2935  * Field Access Macros:
2936  *
2937  */
2938 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RSVD_MSTIS register field. */
2939 #define ALT_SPIS_ISR_RSVD_MSTIS_LSB 5
2940 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RSVD_MSTIS register field. */
2941 #define ALT_SPIS_ISR_RSVD_MSTIS_MSB 5
2942 /* The width in bits of the ALT_SPIS_ISR_RSVD_MSTIS register field. */
2943 #define ALT_SPIS_ISR_RSVD_MSTIS_WIDTH 1
2944 /* The mask used to set the ALT_SPIS_ISR_RSVD_MSTIS register field value. */
2945 #define ALT_SPIS_ISR_RSVD_MSTIS_SET_MSK 0x00000020
2946 /* The mask used to clear the ALT_SPIS_ISR_RSVD_MSTIS register field value. */
2947 #define ALT_SPIS_ISR_RSVD_MSTIS_CLR_MSK 0xffffffdf
2948 /* The reset value of the ALT_SPIS_ISR_RSVD_MSTIS register field. */
2949 #define ALT_SPIS_ISR_RSVD_MSTIS_RESET 0x0
2950 /* Extracts the ALT_SPIS_ISR_RSVD_MSTIS field value from a register. */
2951 #define ALT_SPIS_ISR_RSVD_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2952 /* Produces a ALT_SPIS_ISR_RSVD_MSTIS register field value suitable for setting the register. */
2953 #define ALT_SPIS_ISR_RSVD_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2954 
2955 /*
2956  * Field : RSVD_ISR
2957  *
2958  * Reserved bits - Read Only
2959  *
2960  * Field Access Macros:
2961  *
2962  */
2963 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ISR_RSVD_ISR register field. */
2964 #define ALT_SPIS_ISR_RSVD_ISR_LSB 6
2965 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ISR_RSVD_ISR register field. */
2966 #define ALT_SPIS_ISR_RSVD_ISR_MSB 31
2967 /* The width in bits of the ALT_SPIS_ISR_RSVD_ISR register field. */
2968 #define ALT_SPIS_ISR_RSVD_ISR_WIDTH 26
2969 /* The mask used to set the ALT_SPIS_ISR_RSVD_ISR register field value. */
2970 #define ALT_SPIS_ISR_RSVD_ISR_SET_MSK 0xffffffc0
2971 /* The mask used to clear the ALT_SPIS_ISR_RSVD_ISR register field value. */
2972 #define ALT_SPIS_ISR_RSVD_ISR_CLR_MSK 0x0000003f
2973 /* The reset value of the ALT_SPIS_ISR_RSVD_ISR register field. */
2974 #define ALT_SPIS_ISR_RSVD_ISR_RESET 0x0
2975 /* Extracts the ALT_SPIS_ISR_RSVD_ISR field value from a register. */
2976 #define ALT_SPIS_ISR_RSVD_ISR_GET(value) (((value) & 0xffffffc0) >> 6)
2977 /* Produces a ALT_SPIS_ISR_RSVD_ISR register field value suitable for setting the register. */
2978 #define ALT_SPIS_ISR_RSVD_ISR_SET(value) (((value) << 6) & 0xffffffc0)
2979 
2980 #ifndef __ASSEMBLY__
2981 /*
2982  * WARNING: The C register and register group struct declarations are provided for
2983  * convenience and illustrative purposes. They should, however, be used with
2984  * caution as the C language standard provides no guarantees about the alignment or
2985  * atomicity of device memory accesses. The recommended practice for coding device
2986  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2987  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2988  * alt_write_dword() functions for 64 bit registers.
2989  *
2990  * The struct declaration for register ALT_SPIS_ISR.
2991  */
2992 struct ALT_SPIS_ISR_s
2993 {
2994  const volatile uint32_t TXEIS : 1; /* ALT_SPIS_ISR_TXEIS */
2995  const volatile uint32_t TXOIS : 1; /* ALT_SPIS_ISR_TXOIS */
2996  const volatile uint32_t RXUIS : 1; /* ALT_SPIS_ISR_RXUIS */
2997  const volatile uint32_t RXOIS : 1; /* ALT_SPIS_ISR_RXOIS */
2998  const volatile uint32_t RXFIS : 1; /* ALT_SPIS_ISR_RXFIS */
2999  const volatile uint32_t RSVD_MSTIS : 1; /* ALT_SPIS_ISR_RSVD_MSTIS */
3000  const volatile uint32_t RSVD_ISR : 26; /* ALT_SPIS_ISR_RSVD_ISR */
3001 };
3002 
3003 /* The typedef declaration for register ALT_SPIS_ISR. */
3004 typedef struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
3005 #endif /* __ASSEMBLY__ */
3006 
3007 /* The reset value of the ALT_SPIS_ISR register. */
3008 #define ALT_SPIS_ISR_RESET 0x00000000
3009 /* The byte offset of the ALT_SPIS_ISR register from the beginning of the component. */
3010 #define ALT_SPIS_ISR_OFST 0x30
3011 /* The address of the ALT_SPIS_ISR register. */
3012 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
3013 
3014 /*
3015  * Register : Raw Interrupt Status Register - RISR
3016  *
3017  * Raw Interrupt Status Register
3018  *
3019  * Register Layout
3020  *
3021  * Bits | Access | Reset | Description
3022  * :-------|:-------|:------|:-------------------------
3023  * [0] | R | 0x0 | ALT_SPIS_RISR_TXEIR
3024  * [1] | R | 0x0 | ALT_SPIS_RISR_TXOIR
3025  * [2] | R | 0x0 | ALT_SPIS_RISR_RXUIR
3026  * [3] | R | 0x0 | ALT_SPIS_RISR_RXOIR
3027  * [4] | R | 0x0 | ALT_SPIS_RISR_RXFIR
3028  * [5] | R | 0x0 | ALT_SPIS_RISR_RSVD_MSTIR
3029  * [31:6] | R | 0x0 | ALT_SPIS_RISR_RSVD_RISR
3030  *
3031  */
3032 /*
3033  * Field : TXEIR
3034  *
3035  * Transmit FIFO Empty Raw Interrupt Status
3036  *
3037  * 0 = ssi_txe_intr interrupt is not active prior to masking
3038  *
3039  * 1 = ssi_txe_intr interrupt is active prior masking
3040  *
3041  * Field Enumeration Values:
3042  *
3043  * Enum | Value | Description
3044  * :-------------------------------|:------|:--------------------------------------
3045  * ALT_SPIS_RISR_TXEIR_E_INACTIVE | 0x0 | Raw TX FIFO Empty Interrupt nonactive
3046  * ALT_SPIS_RISR_TXEIR_E_ACTIVE | 0x1 | Raw TX FIFO Empty Interrupt is active
3047  *
3048  * Field Access Macros:
3049  *
3050  */
3051 /*
3052  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
3053  *
3054  * Raw TX FIFO Empty Interrupt nonactive
3055  */
3056 #define ALT_SPIS_RISR_TXEIR_E_INACTIVE 0x0
3057 /*
3058  * Enumerated value for register field ALT_SPIS_RISR_TXEIR
3059  *
3060  * Raw TX FIFO Empty Interrupt is active
3061  */
3062 #define ALT_SPIS_RISR_TXEIR_E_ACTIVE 0x1
3063 
3064 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXEIR register field. */
3065 #define ALT_SPIS_RISR_TXEIR_LSB 0
3066 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXEIR register field. */
3067 #define ALT_SPIS_RISR_TXEIR_MSB 0
3068 /* The width in bits of the ALT_SPIS_RISR_TXEIR register field. */
3069 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
3070 /* The mask used to set the ALT_SPIS_RISR_TXEIR register field value. */
3071 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
3072 /* The mask used to clear the ALT_SPIS_RISR_TXEIR register field value. */
3073 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
3074 /* The reset value of the ALT_SPIS_RISR_TXEIR register field. */
3075 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
3076 /* Extracts the ALT_SPIS_RISR_TXEIR field value from a register. */
3077 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
3078 /* Produces a ALT_SPIS_RISR_TXEIR register field value suitable for setting the register. */
3079 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
3080 
3081 /*
3082  * Field : TXOIR
3083  *
3084  * Transmit FIFO Overflow Raw Interrupt Status
3085  *
3086  * 0 = ssi_txo_intr interrupt is not active prior to masking
3087  *
3088  * 1 = ssi_txo_intr interrupt is active prior masking
3089  *
3090  * Field Enumeration Values:
3091  *
3092  * Enum | Value | Description
3093  * :-------------------------------|:------|:-----------------------------------------
3094  * ALT_SPIS_RISR_TXOIR_E_INACTIVE | 0x0 | Raw TX FIFO Overflow Interrupt nonactive
3095  * ALT_SPIS_RISR_TXOIR_E_ACTIVE | 0x1 | Raw TX FIFO Overflow Interrupt is active
3096  *
3097  * Field Access Macros:
3098  *
3099  */
3100 /*
3101  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
3102  *
3103  * Raw TX FIFO Overflow Interrupt nonactive
3104  */
3105 #define ALT_SPIS_RISR_TXOIR_E_INACTIVE 0x0
3106 /*
3107  * Enumerated value for register field ALT_SPIS_RISR_TXOIR
3108  *
3109  * Raw TX FIFO Overflow Interrupt is active
3110  */
3111 #define ALT_SPIS_RISR_TXOIR_E_ACTIVE 0x1
3112 
3113 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXOIR register field. */
3114 #define ALT_SPIS_RISR_TXOIR_LSB 1
3115 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXOIR register field. */
3116 #define ALT_SPIS_RISR_TXOIR_MSB 1
3117 /* The width in bits of the ALT_SPIS_RISR_TXOIR register field. */
3118 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
3119 /* The mask used to set the ALT_SPIS_RISR_TXOIR register field value. */
3120 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
3121 /* The mask used to clear the ALT_SPIS_RISR_TXOIR register field value. */
3122 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
3123 /* The reset value of the ALT_SPIS_RISR_TXOIR register field. */
3124 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
3125 /* Extracts the ALT_SPIS_RISR_TXOIR field value from a register. */
3126 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
3127 /* Produces a ALT_SPIS_RISR_TXOIR register field value suitable for setting the register. */
3128 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
3129 
3130 /*
3131  * Field : RXUIR
3132  *
3133  * Receive FIFO Underflow Raw Interrupt Status
3134  *
3135  * 0 = ssi_rxu_intr interrupt is not active prior to masking
3136  *
3137  * 1 = ssi_rxu_intr interrupt is active prior to masking
3138  *
3139  * Field Enumeration Values:
3140  *
3141  * Enum | Value | Description
3142  * :-------------------------------|:------|:------------------------------------------
3143  * ALT_SPIS_RISR_RXUIR_E_INACTIVE | 0x0 | Raw RX FIFO Underflow Interrupt nonactive
3144  * ALT_SPIS_RISR_RXUIR_E_ACTIVE | 0x1 | Raw RX FIFO underflow Interrupt is active
3145  *
3146  * Field Access Macros:
3147  *
3148  */
3149 /*
3150  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
3151  *
3152  * Raw RX FIFO Underflow Interrupt nonactive
3153  */
3154 #define ALT_SPIS_RISR_RXUIR_E_INACTIVE 0x0
3155 /*
3156  * Enumerated value for register field ALT_SPIS_RISR_RXUIR
3157  *
3158  * Raw RX FIFO underflow Interrupt is active
3159  */
3160 #define ALT_SPIS_RISR_RXUIR_E_ACTIVE 0x1
3161 
3162 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXUIR register field. */
3163 #define ALT_SPIS_RISR_RXUIR_LSB 2
3164 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXUIR register field. */
3165 #define ALT_SPIS_RISR_RXUIR_MSB 2
3166 /* The width in bits of the ALT_SPIS_RISR_RXUIR register field. */
3167 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
3168 /* The mask used to set the ALT_SPIS_RISR_RXUIR register field value. */
3169 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
3170 /* The mask used to clear the ALT_SPIS_RISR_RXUIR register field value. */
3171 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
3172 /* The reset value of the ALT_SPIS_RISR_RXUIR register field. */
3173 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
3174 /* Extracts the ALT_SPIS_RISR_RXUIR field value from a register. */
3175 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
3176 /* Produces a ALT_SPIS_RISR_RXUIR register field value suitable for setting the register. */
3177 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
3178 
3179 /*
3180  * Field : RXOIR
3181  *
3182  * Receive FIFO Overflow Raw Interrupt Status
3183  *
3184  * 0 = ssi_rxo_intr interrupt is not active prior to masking
3185  *
3186  * 1 = ssi_rxo_intr interrupt is active prior masking
3187  *
3188  * Field Enumeration Values:
3189  *
3190  * Enum | Value | Description
3191  * :-------------------------------|:------|:-----------------------------------------
3192  * ALT_SPIS_RISR_RXOIR_E_INACTIVE | 0x0 | Raw RX FIFO Overflow Interrupt nonactive
3193  * ALT_SPIS_RISR_RXOIR_E_ACTIVE | 0x1 | Raw RX FIFO Overflow Interrupt is active
3194  *
3195  * Field Access Macros:
3196  *
3197  */
3198 /*
3199  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
3200  *
3201  * Raw RX FIFO Overflow Interrupt nonactive
3202  */
3203 #define ALT_SPIS_RISR_RXOIR_E_INACTIVE 0x0
3204 /*
3205  * Enumerated value for register field ALT_SPIS_RISR_RXOIR
3206  *
3207  * Raw RX FIFO Overflow Interrupt is active
3208  */
3209 #define ALT_SPIS_RISR_RXOIR_E_ACTIVE 0x1
3210 
3211 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXOIR register field. */
3212 #define ALT_SPIS_RISR_RXOIR_LSB 3
3213 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXOIR register field. */
3214 #define ALT_SPIS_RISR_RXOIR_MSB 3
3215 /* The width in bits of the ALT_SPIS_RISR_RXOIR register field. */
3216 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
3217 /* The mask used to set the ALT_SPIS_RISR_RXOIR register field value. */
3218 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
3219 /* The mask used to clear the ALT_SPIS_RISR_RXOIR register field value. */
3220 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
3221 /* The reset value of the ALT_SPIS_RISR_RXOIR register field. */
3222 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
3223 /* Extracts the ALT_SPIS_RISR_RXOIR field value from a register. */
3224 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
3225 /* Produces a ALT_SPIS_RISR_RXOIR register field value suitable for setting the register. */
3226 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
3227 
3228 /*
3229  * Field : RXFIR
3230  *
3231  * Receive FIFO Full Raw Interrupt Status
3232  *
3233  * 0 = ssi_rxf_intr interrupt is not active prior to masking
3234  *
3235  * 1 = ssi_rxf_intr interrupt is active prior to masking
3236  *
3237  * Field Enumeration Values:
3238  *
3239  * Enum | Value | Description
3240  * :-------------------------------|:------|:-------------------------------------
3241  * ALT_SPIS_RISR_RXFIR_E_INACTIVE | 0x0 | Raw RX FIFO Full Interrupt nonactive
3242  * ALT_SPIS_RISR_RXFIR_E_ACTIVE | 0x1 | Raw RX FIFO Full Interrupt is active
3243  *
3244  * Field Access Macros:
3245  *
3246  */
3247 /*
3248  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
3249  *
3250  * Raw RX FIFO Full Interrupt nonactive
3251  */
3252 #define ALT_SPIS_RISR_RXFIR_E_INACTIVE 0x0
3253 /*
3254  * Enumerated value for register field ALT_SPIS_RISR_RXFIR
3255  *
3256  * Raw RX FIFO Full Interrupt is active
3257  */
3258 #define ALT_SPIS_RISR_RXFIR_E_ACTIVE 0x1
3259 
3260 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXFIR register field. */
3261 #define ALT_SPIS_RISR_RXFIR_LSB 4
3262 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXFIR register field. */
3263 #define ALT_SPIS_RISR_RXFIR_MSB 4
3264 /* The width in bits of the ALT_SPIS_RISR_RXFIR register field. */
3265 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
3266 /* The mask used to set the ALT_SPIS_RISR_RXFIR register field value. */
3267 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
3268 /* The mask used to clear the ALT_SPIS_RISR_RXFIR register field value. */
3269 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
3270 /* The reset value of the ALT_SPIS_RISR_RXFIR register field. */
3271 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
3272 /* Extracts the ALT_SPIS_RISR_RXFIR field value from a register. */
3273 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
3274 /* Produces a ALT_SPIS_RISR_RXFIR register field value suitable for setting the register. */
3275 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
3276 
3277 /*
3278  * Field : RSVD_MSTIR
3279  *
3280  * Reserved field- read-only
3281  *
3282  * Field Access Macros:
3283  *
3284  */
3285 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RSVD_MSTIR register field. */
3286 #define ALT_SPIS_RISR_RSVD_MSTIR_LSB 5
3287 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RSVD_MSTIR register field. */
3288 #define ALT_SPIS_RISR_RSVD_MSTIR_MSB 5
3289 /* The width in bits of the ALT_SPIS_RISR_RSVD_MSTIR register field. */
3290 #define ALT_SPIS_RISR_RSVD_MSTIR_WIDTH 1
3291 /* The mask used to set the ALT_SPIS_RISR_RSVD_MSTIR register field value. */
3292 #define ALT_SPIS_RISR_RSVD_MSTIR_SET_MSK 0x00000020
3293 /* The mask used to clear the ALT_SPIS_RISR_RSVD_MSTIR register field value. */
3294 #define ALT_SPIS_RISR_RSVD_MSTIR_CLR_MSK 0xffffffdf
3295 /* The reset value of the ALT_SPIS_RISR_RSVD_MSTIR register field. */
3296 #define ALT_SPIS_RISR_RSVD_MSTIR_RESET 0x0
3297 /* Extracts the ALT_SPIS_RISR_RSVD_MSTIR field value from a register. */
3298 #define ALT_SPIS_RISR_RSVD_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
3299 /* Produces a ALT_SPIS_RISR_RSVD_MSTIR register field value suitable for setting the register. */
3300 #define ALT_SPIS_RISR_RSVD_MSTIR_SET(value) (((value) << 5) & 0x00000020)
3301 
3302 /*
3303  * Field : RSVD_RISR
3304  *
3305  * Reserved bits - Read Only
3306  *
3307  * Field Access Macros:
3308  *
3309  */
3310 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RSVD_RISR register field. */
3311 #define ALT_SPIS_RISR_RSVD_RISR_LSB 6
3312 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RSVD_RISR register field. */
3313 #define ALT_SPIS_RISR_RSVD_RISR_MSB 31
3314 /* The width in bits of the ALT_SPIS_RISR_RSVD_RISR register field. */
3315 #define ALT_SPIS_RISR_RSVD_RISR_WIDTH 26
3316 /* The mask used to set the ALT_SPIS_RISR_RSVD_RISR register field value. */
3317 #define ALT_SPIS_RISR_RSVD_RISR_SET_MSK 0xffffffc0
3318 /* The mask used to clear the ALT_SPIS_RISR_RSVD_RISR register field value. */
3319 #define ALT_SPIS_RISR_RSVD_RISR_CLR_MSK 0x0000003f
3320 /* The reset value of the ALT_SPIS_RISR_RSVD_RISR register field. */
3321 #define ALT_SPIS_RISR_RSVD_RISR_RESET 0x0
3322 /* Extracts the ALT_SPIS_RISR_RSVD_RISR field value from a register. */
3323 #define ALT_SPIS_RISR_RSVD_RISR_GET(value) (((value) & 0xffffffc0) >> 6)
3324 /* Produces a ALT_SPIS_RISR_RSVD_RISR register field value suitable for setting the register. */
3325 #define ALT_SPIS_RISR_RSVD_RISR_SET(value) (((value) << 6) & 0xffffffc0)
3326 
3327 #ifndef __ASSEMBLY__
3328 /*
3329  * WARNING: The C register and register group struct declarations are provided for
3330  * convenience and illustrative purposes. They should, however, be used with
3331  * caution as the C language standard provides no guarantees about the alignment or
3332  * atomicity of device memory accesses. The recommended practice for coding device
3333  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3334  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3335  * alt_write_dword() functions for 64 bit registers.
3336  *
3337  * The struct declaration for register ALT_SPIS_RISR.
3338  */
3339 struct ALT_SPIS_RISR_s
3340 {
3341  const volatile uint32_t TXEIR : 1; /* ALT_SPIS_RISR_TXEIR */
3342  const volatile uint32_t TXOIR : 1; /* ALT_SPIS_RISR_TXOIR */
3343  const volatile uint32_t RXUIR : 1; /* ALT_SPIS_RISR_RXUIR */
3344  const volatile uint32_t RXOIR : 1; /* ALT_SPIS_RISR_RXOIR */
3345  const volatile uint32_t RXFIR : 1; /* ALT_SPIS_RISR_RXFIR */
3346  const volatile uint32_t RSVD_MSTIR : 1; /* ALT_SPIS_RISR_RSVD_MSTIR */
3347  const volatile uint32_t RSVD_RISR : 26; /* ALT_SPIS_RISR_RSVD_RISR */
3348 };
3349 
3350 /* The typedef declaration for register ALT_SPIS_RISR. */
3351 typedef struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
3352 #endif /* __ASSEMBLY__ */
3353 
3354 /* The reset value of the ALT_SPIS_RISR register. */
3355 #define ALT_SPIS_RISR_RESET 0x00000000
3356 /* The byte offset of the ALT_SPIS_RISR register from the beginning of the component. */
3357 #define ALT_SPIS_RISR_OFST 0x34
3358 /* The address of the ALT_SPIS_RISR register. */
3359 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
3360 
3361 /*
3362  * Register : Transmit FIFO Overflow Interrupt Clear Register Register - TXOICR
3363  *
3364  * Transmit FIFO Overflow Interrupt Clear Register
3365  *
3366  * Register Layout
3367  *
3368  * Bits | Access | Reset | Description
3369  * :-------|:-------|:------|:----------------------------
3370  * [0] | R | 0x0 | ALT_SPIS_TXOICR_TXOICR
3371  * [31:1] | R | 0x0 | ALT_SPIS_TXOICR_RSVD_TXOICR
3372  *
3373  */
3374 /*
3375  * Field : TXOICR
3376  *
3377  * Clear Transmit FIFO Overflow Interrupt.
3378  *
3379  * This register reflects the status of the interrupt. A read from this
3380  *
3381  * register clears the ssi_txo_intr interrupt; writing has no effect.
3382  *
3383  * Field Access Macros:
3384  *
3385  */
3386 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
3387 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
3388 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXOICR_TXOICR register field. */
3389 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
3390 /* The width in bits of the ALT_SPIS_TXOICR_TXOICR register field. */
3391 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
3392 /* The mask used to set the ALT_SPIS_TXOICR_TXOICR register field value. */
3393 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
3394 /* The mask used to clear the ALT_SPIS_TXOICR_TXOICR register field value. */
3395 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3396 /* The reset value of the ALT_SPIS_TXOICR_TXOICR register field. */
3397 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
3398 /* Extracts the ALT_SPIS_TXOICR_TXOICR field value from a register. */
3399 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3400 /* Produces a ALT_SPIS_TXOICR_TXOICR register field value suitable for setting the register. */
3401 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3402 
3403 /*
3404  * Field : RSVD_TXOICR
3405  *
3406  * Reserved bits - Read Only
3407  *
3408  * Field Access Macros:
3409  *
3410  */
3411 /* The Least Significant Bit (LSB) position of the ALT_SPIS_TXOICR_RSVD_TXOICR register field. */
3412 #define ALT_SPIS_TXOICR_RSVD_TXOICR_LSB 1
3413 /* The Most Significant Bit (MSB) position of the ALT_SPIS_TXOICR_RSVD_TXOICR register field. */
3414 #define ALT_SPIS_TXOICR_RSVD_TXOICR_MSB 31
3415 /* The width in bits of the ALT_SPIS_TXOICR_RSVD_TXOICR register field. */
3416 #define ALT_SPIS_TXOICR_RSVD_TXOICR_WIDTH 31
3417 /* The mask used to set the ALT_SPIS_TXOICR_RSVD_TXOICR register field value. */
3418 #define ALT_SPIS_TXOICR_RSVD_TXOICR_SET_MSK 0xfffffffe
3419 /* The mask used to clear the ALT_SPIS_TXOICR_RSVD_TXOICR register field value. */
3420 #define ALT_SPIS_TXOICR_RSVD_TXOICR_CLR_MSK 0x00000001
3421 /* The reset value of the ALT_SPIS_TXOICR_RSVD_TXOICR register field. */
3422 #define ALT_SPIS_TXOICR_RSVD_TXOICR_RESET 0x0
3423 /* Extracts the ALT_SPIS_TXOICR_RSVD_TXOICR field value from a register. */
3424 #define ALT_SPIS_TXOICR_RSVD_TXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3425 /* Produces a ALT_SPIS_TXOICR_RSVD_TXOICR register field value suitable for setting the register. */
3426 #define ALT_SPIS_TXOICR_RSVD_TXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3427 
3428 #ifndef __ASSEMBLY__
3429 /*
3430  * WARNING: The C register and register group struct declarations are provided for
3431  * convenience and illustrative purposes. They should, however, be used with
3432  * caution as the C language standard provides no guarantees about the alignment or
3433  * atomicity of device memory accesses. The recommended practice for coding device
3434  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3435  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3436  * alt_write_dword() functions for 64 bit registers.
3437  *
3438  * The struct declaration for register ALT_SPIS_TXOICR.
3439  */
3440 struct ALT_SPIS_TXOICR_s
3441 {
3442  const volatile uint32_t TXOICR : 1; /* ALT_SPIS_TXOICR_TXOICR */
3443  const volatile uint32_t RSVD_TXOICR : 31; /* ALT_SPIS_TXOICR_RSVD_TXOICR */
3444 };
3445 
3446 /* The typedef declaration for register ALT_SPIS_TXOICR. */
3447 typedef struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
3448 #endif /* __ASSEMBLY__ */
3449 
3450 /* The reset value of the ALT_SPIS_TXOICR register. */
3451 #define ALT_SPIS_TXOICR_RESET 0x00000000
3452 /* The byte offset of the ALT_SPIS_TXOICR register from the beginning of the component. */
3453 #define ALT_SPIS_TXOICR_OFST 0x38
3454 /* The address of the ALT_SPIS_TXOICR register. */
3455 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
3456 
3457 /*
3458  * Register : Receive FIFO Overflow Interrupt Clear Register - RXOICR
3459  *
3460  * Receive FIFO Overflow Interrupt Clear Register
3461  *
3462  * Register Layout
3463  *
3464  * Bits | Access | Reset | Description
3465  * :-------|:-------|:------|:----------------------------
3466  * [0] | R | 0x0 | ALT_SPIS_RXOICR_RXOICR
3467  * [31:1] | R | 0x0 | ALT_SPIS_RXOICR_RSVD_RXOICR
3468  *
3469  */
3470 /*
3471  * Field : RXOICR
3472  *
3473  * Clear Receive FIFO Overflow Interrupt.
3474  *
3475  * This register reflects the status of the interrupt. A read from this
3476  *
3477  * register clears the ssi_rxo_intr interrupt; writing has no effect.
3478  *
3479  * Field Access Macros:
3480  *
3481  */
3482 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
3483 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
3484 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXOICR_RXOICR register field. */
3485 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
3486 /* The width in bits of the ALT_SPIS_RXOICR_RXOICR register field. */
3487 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
3488 /* The mask used to set the ALT_SPIS_RXOICR_RXOICR register field value. */
3489 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
3490 /* The mask used to clear the ALT_SPIS_RXOICR_RXOICR register field value. */
3491 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3492 /* The reset value of the ALT_SPIS_RXOICR_RXOICR register field. */
3493 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
3494 /* Extracts the ALT_SPIS_RXOICR_RXOICR field value from a register. */
3495 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3496 /* Produces a ALT_SPIS_RXOICR_RXOICR register field value suitable for setting the register. */
3497 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3498 
3499 /*
3500  * Field : RSVD_RXOICR
3501  *
3502  * Reserved bits - Read Only
3503  *
3504  * Field Access Macros:
3505  *
3506  */
3507 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXOICR_RSVD_RXOICR register field. */
3508 #define ALT_SPIS_RXOICR_RSVD_RXOICR_LSB 1
3509 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXOICR_RSVD_RXOICR register field. */
3510 #define ALT_SPIS_RXOICR_RSVD_RXOICR_MSB 31
3511 /* The width in bits of the ALT_SPIS_RXOICR_RSVD_RXOICR register field. */
3512 #define ALT_SPIS_RXOICR_RSVD_RXOICR_WIDTH 31
3513 /* The mask used to set the ALT_SPIS_RXOICR_RSVD_RXOICR register field value. */
3514 #define ALT_SPIS_RXOICR_RSVD_RXOICR_SET_MSK 0xfffffffe
3515 /* The mask used to clear the ALT_SPIS_RXOICR_RSVD_RXOICR register field value. */
3516 #define ALT_SPIS_RXOICR_RSVD_RXOICR_CLR_MSK 0x00000001
3517 /* The reset value of the ALT_SPIS_RXOICR_RSVD_RXOICR register field. */
3518 #define ALT_SPIS_RXOICR_RSVD_RXOICR_RESET 0x0
3519 /* Extracts the ALT_SPIS_RXOICR_RSVD_RXOICR field value from a register. */
3520 #define ALT_SPIS_RXOICR_RSVD_RXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3521 /* Produces a ALT_SPIS_RXOICR_RSVD_RXOICR register field value suitable for setting the register. */
3522 #define ALT_SPIS_RXOICR_RSVD_RXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3523 
3524 #ifndef __ASSEMBLY__
3525 /*
3526  * WARNING: The C register and register group struct declarations are provided for
3527  * convenience and illustrative purposes. They should, however, be used with
3528  * caution as the C language standard provides no guarantees about the alignment or
3529  * atomicity of device memory accesses. The recommended practice for coding device
3530  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3531  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3532  * alt_write_dword() functions for 64 bit registers.
3533  *
3534  * The struct declaration for register ALT_SPIS_RXOICR.
3535  */
3536 struct ALT_SPIS_RXOICR_s
3537 {
3538  const volatile uint32_t RXOICR : 1; /* ALT_SPIS_RXOICR_RXOICR */
3539  const volatile uint32_t RSVD_RXOICR : 31; /* ALT_SPIS_RXOICR_RSVD_RXOICR */
3540 };
3541 
3542 /* The typedef declaration for register ALT_SPIS_RXOICR. */
3543 typedef struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
3544 #endif /* __ASSEMBLY__ */
3545 
3546 /* The reset value of the ALT_SPIS_RXOICR register. */
3547 #define ALT_SPIS_RXOICR_RESET 0x00000000
3548 /* The byte offset of the ALT_SPIS_RXOICR register from the beginning of the component. */
3549 #define ALT_SPIS_RXOICR_OFST 0x3c
3550 /* The address of the ALT_SPIS_RXOICR register. */
3551 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
3552 
3553 /*
3554  * Register : Receive FIFO Underflow Interrupt Clear Register - RXUICR
3555  *
3556  * Receive FIFO Underflow Interrupt Clear Register
3557  *
3558  * Register Layout
3559  *
3560  * Bits | Access | Reset | Description
3561  * :-------|:-------|:------|:----------------------------
3562  * [0] | R | 0x0 | ALT_SPIS_RXUICR_RXUICR
3563  * [31:1] | R | 0x0 | ALT_SPIS_RXUICR_RSVD_RXUICR
3564  *
3565  */
3566 /*
3567  * Field : RXUICR
3568  *
3569  * Clear Receive FIFO Underflow Interrupt.
3570  *
3571  * This register reflects the status of the interrupt. A read from this
3572  *
3573  * register clears the ssi_rxu_intr interrupt; writing has no effect.
3574  *
3575  * Field Access Macros:
3576  *
3577  */
3578 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
3579 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
3580 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXUICR_RXUICR register field. */
3581 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
3582 /* The width in bits of the ALT_SPIS_RXUICR_RXUICR register field. */
3583 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
3584 /* The mask used to set the ALT_SPIS_RXUICR_RXUICR register field value. */
3585 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
3586 /* The mask used to clear the ALT_SPIS_RXUICR_RXUICR register field value. */
3587 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
3588 /* The reset value of the ALT_SPIS_RXUICR_RXUICR register field. */
3589 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
3590 /* Extracts the ALT_SPIS_RXUICR_RXUICR field value from a register. */
3591 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
3592 /* Produces a ALT_SPIS_RXUICR_RXUICR register field value suitable for setting the register. */
3593 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
3594 
3595 /*
3596  * Field : RSVD_RXUICR
3597  *
3598  * Reserved bits - Read Only
3599  *
3600  * Field Access Macros:
3601  *
3602  */
3603 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RXUICR_RSVD_RXUICR register field. */
3604 #define ALT_SPIS_RXUICR_RSVD_RXUICR_LSB 1
3605 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RXUICR_RSVD_RXUICR register field. */
3606 #define ALT_SPIS_RXUICR_RSVD_RXUICR_MSB 31
3607 /* The width in bits of the ALT_SPIS_RXUICR_RSVD_RXUICR register field. */
3608 #define ALT_SPIS_RXUICR_RSVD_RXUICR_WIDTH 31
3609 /* The mask used to set the ALT_SPIS_RXUICR_RSVD_RXUICR register field value. */
3610 #define ALT_SPIS_RXUICR_RSVD_RXUICR_SET_MSK 0xfffffffe
3611 /* The mask used to clear the ALT_SPIS_RXUICR_RSVD_RXUICR register field value. */
3612 #define ALT_SPIS_RXUICR_RSVD_RXUICR_CLR_MSK 0x00000001
3613 /* The reset value of the ALT_SPIS_RXUICR_RSVD_RXUICR register field. */
3614 #define ALT_SPIS_RXUICR_RSVD_RXUICR_RESET 0x0
3615 /* Extracts the ALT_SPIS_RXUICR_RSVD_RXUICR field value from a register. */
3616 #define ALT_SPIS_RXUICR_RSVD_RXUICR_GET(value) (((value) & 0xfffffffe) >> 1)
3617 /* Produces a ALT_SPIS_RXUICR_RSVD_RXUICR register field value suitable for setting the register. */
3618 #define ALT_SPIS_RXUICR_RSVD_RXUICR_SET(value) (((value) << 1) & 0xfffffffe)
3619 
3620 #ifndef __ASSEMBLY__
3621 /*
3622  * WARNING: The C register and register group struct declarations are provided for
3623  * convenience and illustrative purposes. They should, however, be used with
3624  * caution as the C language standard provides no guarantees about the alignment or
3625  * atomicity of device memory accesses. The recommended practice for coding device
3626  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3627  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3628  * alt_write_dword() functions for 64 bit registers.
3629  *
3630  * The struct declaration for register ALT_SPIS_RXUICR.
3631  */
3632 struct ALT_SPIS_RXUICR_s
3633 {
3634  const volatile uint32_t RXUICR : 1; /* ALT_SPIS_RXUICR_RXUICR */
3635  const volatile uint32_t RSVD_RXUICR : 31; /* ALT_SPIS_RXUICR_RSVD_RXUICR */
3636 };
3637 
3638 /* The typedef declaration for register ALT_SPIS_RXUICR. */
3639 typedef struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
3640 #endif /* __ASSEMBLY__ */
3641 
3642 /* The reset value of the ALT_SPIS_RXUICR register. */
3643 #define ALT_SPIS_RXUICR_RESET 0x00000000
3644 /* The byte offset of the ALT_SPIS_RXUICR register from the beginning of the component. */
3645 #define ALT_SPIS_RXUICR_OFST 0x40
3646 /* The address of the ALT_SPIS_RXUICR register. */
3647 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
3648 
3649 /*
3650  * Register : Multi-Master Interrupt Clear Register - MSTICR
3651  *
3652  * Multi-Master Interrupt Clear Register
3653  *
3654  * Register Layout
3655  *
3656  * Bits | Access | Reset | Description
3657  * :-------|:-------|:------|:----------------------------
3658  * [0] | R | 0x0 | ALT_SPIS_MSTICR_MSTICR
3659  * [31:1] | R | 0x0 | ALT_SPIS_MSTICR_RSVD_MSTICR
3660  *
3661  */
3662 /*
3663  * Field : MSTICR
3664  *
3665  * Clear Multi-Master Contention Interrupt.
3666  *
3667  * This register reflects the status of the interrupt. A read from this
3668  *
3669  * register clears the ssi_mst_intr interrupt; writing has no effect.
3670  *
3671  * Field Access Macros:
3672  *
3673  */
3674 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MSTICR_MSTICR register field. */
3675 #define ALT_SPIS_MSTICR_MSTICR_LSB 0
3676 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MSTICR_MSTICR register field. */
3677 #define ALT_SPIS_MSTICR_MSTICR_MSB 0
3678 /* The width in bits of the ALT_SPIS_MSTICR_MSTICR register field. */
3679 #define ALT_SPIS_MSTICR_MSTICR_WIDTH 1
3680 /* The mask used to set the ALT_SPIS_MSTICR_MSTICR register field value. */
3681 #define ALT_SPIS_MSTICR_MSTICR_SET_MSK 0x00000001
3682 /* The mask used to clear the ALT_SPIS_MSTICR_MSTICR register field value. */
3683 #define ALT_SPIS_MSTICR_MSTICR_CLR_MSK 0xfffffffe
3684 /* The reset value of the ALT_SPIS_MSTICR_MSTICR register field. */
3685 #define ALT_SPIS_MSTICR_MSTICR_RESET 0x0
3686 /* Extracts the ALT_SPIS_MSTICR_MSTICR field value from a register. */
3687 #define ALT_SPIS_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
3688 /* Produces a ALT_SPIS_MSTICR_MSTICR register field value suitable for setting the register. */
3689 #define ALT_SPIS_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
3690 
3691 /*
3692  * Field : RSVD_MSTICR
3693  *
3694  * Reserved bits - Read Only
3695  *
3696  * Field Access Macros:
3697  *
3698  */
3699 /* The Least Significant Bit (LSB) position of the ALT_SPIS_MSTICR_RSVD_MSTICR register field. */
3700 #define ALT_SPIS_MSTICR_RSVD_MSTICR_LSB 1
3701 /* The Most Significant Bit (MSB) position of the ALT_SPIS_MSTICR_RSVD_MSTICR register field. */
3702 #define ALT_SPIS_MSTICR_RSVD_MSTICR_MSB 31
3703 /* The width in bits of the ALT_SPIS_MSTICR_RSVD_MSTICR register field. */
3704 #define ALT_SPIS_MSTICR_RSVD_MSTICR_WIDTH 31
3705 /* The mask used to set the ALT_SPIS_MSTICR_RSVD_MSTICR register field value. */
3706 #define ALT_SPIS_MSTICR_RSVD_MSTICR_SET_MSK 0xfffffffe
3707 /* The mask used to clear the ALT_SPIS_MSTICR_RSVD_MSTICR register field value. */
3708 #define ALT_SPIS_MSTICR_RSVD_MSTICR_CLR_MSK 0x00000001
3709 /* The reset value of the ALT_SPIS_MSTICR_RSVD_MSTICR register field. */
3710 #define ALT_SPIS_MSTICR_RSVD_MSTICR_RESET 0x0
3711 /* Extracts the ALT_SPIS_MSTICR_RSVD_MSTICR field value from a register. */
3712 #define ALT_SPIS_MSTICR_RSVD_MSTICR_GET(value) (((value) & 0xfffffffe) >> 1)
3713 /* Produces a ALT_SPIS_MSTICR_RSVD_MSTICR register field value suitable for setting the register. */
3714 #define ALT_SPIS_MSTICR_RSVD_MSTICR_SET(value) (((value) << 1) & 0xfffffffe)
3715 
3716 #ifndef __ASSEMBLY__
3717 /*
3718  * WARNING: The C register and register group struct declarations are provided for
3719  * convenience and illustrative purposes. They should, however, be used with
3720  * caution as the C language standard provides no guarantees about the alignment or
3721  * atomicity of device memory accesses. The recommended practice for coding device
3722  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3723  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3724  * alt_write_dword() functions for 64 bit registers.
3725  *
3726  * The struct declaration for register ALT_SPIS_MSTICR.
3727  */
3728 struct ALT_SPIS_MSTICR_s
3729 {
3730  const volatile uint32_t MSTICR : 1; /* ALT_SPIS_MSTICR_MSTICR */
3731  const volatile uint32_t RSVD_MSTICR : 31; /* ALT_SPIS_MSTICR_RSVD_MSTICR */
3732 };
3733 
3734 /* The typedef declaration for register ALT_SPIS_MSTICR. */
3735 typedef struct ALT_SPIS_MSTICR_s ALT_SPIS_MSTICR_t;
3736 #endif /* __ASSEMBLY__ */
3737 
3738 /* The reset value of the ALT_SPIS_MSTICR register. */
3739 #define ALT_SPIS_MSTICR_RESET 0x00000000
3740 /* The byte offset of the ALT_SPIS_MSTICR register from the beginning of the component. */
3741 #define ALT_SPIS_MSTICR_OFST 0x44
3742 /* The address of the ALT_SPIS_MSTICR register. */
3743 #define ALT_SPIS_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MSTICR_OFST))
3744 
3745 /*
3746  * Register : Interrupt Clear Register - ICR
3747  *
3748  * Interrupt Clear Register
3749  *
3750  * Register Layout
3751  *
3752  * Bits | Access | Reset | Description
3753  * :-------|:-------|:------|:----------------------
3754  * [0] | R | 0x0 | ALT_SPIS_ICR_ICR
3755  * [31:1] | R | 0x0 | ALT_SPIS_ICR_RSVD_ICR
3756  *
3757  */
3758 /*
3759  * Field : ICR
3760  *
3761  * Clear Interrupts.
3762  *
3763  * This register is set if any of the interrupts below are active. A read
3764  *
3765  * clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr
3766  *
3767  * interrupts. Writing to this register has no effect.
3768  *
3769  * Field Access Macros:
3770  *
3771  */
3772 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ICR_ICR register field. */
3773 #define ALT_SPIS_ICR_ICR_LSB 0
3774 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ICR_ICR register field. */
3775 #define ALT_SPIS_ICR_ICR_MSB 0
3776 /* The width in bits of the ALT_SPIS_ICR_ICR register field. */
3777 #define ALT_SPIS_ICR_ICR_WIDTH 1
3778 /* The mask used to set the ALT_SPIS_ICR_ICR register field value. */
3779 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
3780 /* The mask used to clear the ALT_SPIS_ICR_ICR register field value. */
3781 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
3782 /* The reset value of the ALT_SPIS_ICR_ICR register field. */
3783 #define ALT_SPIS_ICR_ICR_RESET 0x0
3784 /* Extracts the ALT_SPIS_ICR_ICR field value from a register. */
3785 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
3786 /* Produces a ALT_SPIS_ICR_ICR register field value suitable for setting the register. */
3787 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
3788 
3789 /*
3790  * Field : RSVD_ICR
3791  *
3792  * Reserved bits - Read Only
3793  *
3794  * Field Access Macros:
3795  *
3796  */
3797 /* The Least Significant Bit (LSB) position of the ALT_SPIS_ICR_RSVD_ICR register field. */
3798 #define ALT_SPIS_ICR_RSVD_ICR_LSB 1
3799 /* The Most Significant Bit (MSB) position of the ALT_SPIS_ICR_RSVD_ICR register field. */
3800 #define ALT_SPIS_ICR_RSVD_ICR_MSB 31
3801 /* The width in bits of the ALT_SPIS_ICR_RSVD_ICR register field. */
3802 #define ALT_SPIS_ICR_RSVD_ICR_WIDTH 31
3803 /* The mask used to set the ALT_SPIS_ICR_RSVD_ICR register field value. */
3804 #define ALT_SPIS_ICR_RSVD_ICR_SET_MSK 0xfffffffe
3805 /* The mask used to clear the ALT_SPIS_ICR_RSVD_ICR register field value. */
3806 #define ALT_SPIS_ICR_RSVD_ICR_CLR_MSK 0x00000001
3807 /* The reset value of the ALT_SPIS_ICR_RSVD_ICR register field. */
3808 #define ALT_SPIS_ICR_RSVD_ICR_RESET 0x0
3809 /* Extracts the ALT_SPIS_ICR_RSVD_ICR field value from a register. */
3810 #define ALT_SPIS_ICR_RSVD_ICR_GET(value) (((value) & 0xfffffffe) >> 1)
3811 /* Produces a ALT_SPIS_ICR_RSVD_ICR register field value suitable for setting the register. */
3812 #define ALT_SPIS_ICR_RSVD_ICR_SET(value) (((value) << 1) & 0xfffffffe)
3813 
3814 #ifndef __ASSEMBLY__
3815 /*
3816  * WARNING: The C register and register group struct declarations are provided for
3817  * convenience and illustrative purposes. They should, however, be used with
3818  * caution as the C language standard provides no guarantees about the alignment or
3819  * atomicity of device memory accesses. The recommended practice for coding device
3820  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3821  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3822  * alt_write_dword() functions for 64 bit registers.
3823  *
3824  * The struct declaration for register ALT_SPIS_ICR.
3825  */
3826 struct ALT_SPIS_ICR_s
3827 {
3828  const volatile uint32_t ICR : 1; /* ALT_SPIS_ICR_ICR */
3829  const volatile uint32_t RSVD_ICR : 31; /* ALT_SPIS_ICR_RSVD_ICR */
3830 };
3831 
3832 /* The typedef declaration for register ALT_SPIS_ICR. */
3833 typedef struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
3834 #endif /* __ASSEMBLY__ */
3835 
3836 /* The reset value of the ALT_SPIS_ICR register. */
3837 #define ALT_SPIS_ICR_RESET 0x00000000
3838 /* The byte offset of the ALT_SPIS_ICR register from the beginning of the component. */
3839 #define ALT_SPIS_ICR_OFST 0x48
3840 /* The address of the ALT_SPIS_ICR register. */
3841 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
3842 
3843 /*
3844  * Register : DMA Control Register - DMACR
3845  *
3846  * DMA Control Register.
3847  *
3848  * This register is only valid when DW_apb_ssi is configured with a set of
3849  *
3850  * DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
3851  *
3852  * not configured for DMA operation, this register will not exist and writing
3853  *
3854  * to the register's address will have no effect; reading from this register
3855  *
3856  * address will return zero. The register is used to enable the DMA
3857  *
3858  * Controller interface operation.
3859  *
3860  * Register Layout
3861  *
3862  * Bits | Access | Reset | Description
3863  * :-------|:-------|:------|:--------------------------
3864  * [0] | RW | 0x0 | ALT_SPIS_DMACR_RDMAE
3865  * [1] | RW | 0x0 | ALT_SPIS_DMACR_TDMAE
3866  * [31:2] | R | 0x0 | ALT_SPIS_DMACR_RSVD_DMACR
3867  *
3868  */
3869 /*
3870  * Field : RDMAE
3871  *
3872  * Receive DMA Enable.
3873  *
3874  * This bit enables/disables the receive FIFO DMA channel
3875  *
3876  * 0 = Receive DMA disabled
3877  *
3878  * 1 = Receive DMA enabled
3879  *
3880  * Field Enumeration Values:
3881  *
3882  * Enum | Value | Description
3883  * :-------------------------------|:------|:----------------------
3884  * ALT_SPIS_DMACR_RDMAE_E_DISABLE | 0x0 | Recieve DMA Disabled
3885  * ALT_SPIS_DMACR_RDMAE_E_ENABLED | 0x1 | Recieve DMA Enabled
3886  *
3887  * Field Access Macros:
3888  *
3889  */
3890 /*
3891  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
3892  *
3893  * Recieve DMA Disabled
3894  */
3895 #define ALT_SPIS_DMACR_RDMAE_E_DISABLE 0x0
3896 /*
3897  * Enumerated value for register field ALT_SPIS_DMACR_RDMAE
3898  *
3899  * Recieve DMA Enabled
3900  */
3901 #define ALT_SPIS_DMACR_RDMAE_E_ENABLED 0x1
3902 
3903 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
3904 #define ALT_SPIS_DMACR_RDMAE_LSB 0
3905 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_RDMAE register field. */
3906 #define ALT_SPIS_DMACR_RDMAE_MSB 0
3907 /* The width in bits of the ALT_SPIS_DMACR_RDMAE register field. */
3908 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
3909 /* The mask used to set the ALT_SPIS_DMACR_RDMAE register field value. */
3910 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
3911 /* The mask used to clear the ALT_SPIS_DMACR_RDMAE register field value. */
3912 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
3913 /* The reset value of the ALT_SPIS_DMACR_RDMAE register field. */
3914 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
3915 /* Extracts the ALT_SPIS_DMACR_RDMAE field value from a register. */
3916 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3917 /* Produces a ALT_SPIS_DMACR_RDMAE register field value suitable for setting the register. */
3918 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3919 
3920 /*
3921  * Field : TDMAE
3922  *
3923  * Transmit DMA Enable.
3924  *
3925  * This bit enables/disables the transmit FIFO DMA channel.
3926  *
3927  * 0 = Transmit DMA disabled
3928  *
3929  * 1 = Transmit DMA enabled
3930  *
3931  * Field Enumeration Values:
3932  *
3933  * Enum | Value | Description
3934  * :-------------------------------|:------|:-----------------------
3935  * ALT_SPIS_DMACR_TDMAE_E_DISABLE | 0x0 | Transmit DMA Disabled
3936  * ALT_SPIS_DMACR_TDMAE_E_ENABLED | 0x1 | Transmit DMA Enabled
3937  *
3938  * Field Access Macros:
3939  *
3940  */
3941 /*
3942  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
3943  *
3944  * Transmit DMA Disabled
3945  */
3946 #define ALT_SPIS_DMACR_TDMAE_E_DISABLE 0x0
3947 /*
3948  * Enumerated value for register field ALT_SPIS_DMACR_TDMAE
3949  *
3950  * Transmit DMA Enabled
3951  */
3952 #define ALT_SPIS_DMACR_TDMAE_E_ENABLED 0x1
3953 
3954 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
3955 #define ALT_SPIS_DMACR_TDMAE_LSB 1
3956 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_TDMAE register field. */
3957 #define ALT_SPIS_DMACR_TDMAE_MSB 1
3958 /* The width in bits of the ALT_SPIS_DMACR_TDMAE register field. */
3959 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
3960 /* The mask used to set the ALT_SPIS_DMACR_TDMAE register field value. */
3961 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
3962 /* The mask used to clear the ALT_SPIS_DMACR_TDMAE register field value. */
3963 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
3964 /* The reset value of the ALT_SPIS_DMACR_TDMAE register field. */
3965 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
3966 /* Extracts the ALT_SPIS_DMACR_TDMAE field value from a register. */
3967 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3968 /* Produces a ALT_SPIS_DMACR_TDMAE register field value suitable for setting the register. */
3969 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3970 
3971 /*
3972  * Field : RSVD_DMACR
3973  *
3974  * Reserved bits - Read Only
3975  *
3976  * Field Access Macros:
3977  *
3978  */
3979 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMACR_RSVD_DMACR register field. */
3980 #define ALT_SPIS_DMACR_RSVD_DMACR_LSB 2
3981 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMACR_RSVD_DMACR register field. */
3982 #define ALT_SPIS_DMACR_RSVD_DMACR_MSB 31
3983 /* The width in bits of the ALT_SPIS_DMACR_RSVD_DMACR register field. */
3984 #define ALT_SPIS_DMACR_RSVD_DMACR_WIDTH 30
3985 /* The mask used to set the ALT_SPIS_DMACR_RSVD_DMACR register field value. */
3986 #define ALT_SPIS_DMACR_RSVD_DMACR_SET_MSK 0xfffffffc
3987 /* The mask used to clear the ALT_SPIS_DMACR_RSVD_DMACR register field value. */
3988 #define ALT_SPIS_DMACR_RSVD_DMACR_CLR_MSK 0x00000003
3989 /* The reset value of the ALT_SPIS_DMACR_RSVD_DMACR register field. */
3990 #define ALT_SPIS_DMACR_RSVD_DMACR_RESET 0x0
3991 /* Extracts the ALT_SPIS_DMACR_RSVD_DMACR field value from a register. */
3992 #define ALT_SPIS_DMACR_RSVD_DMACR_GET(value) (((value) & 0xfffffffc) >> 2)
3993 /* Produces a ALT_SPIS_DMACR_RSVD_DMACR register field value suitable for setting the register. */
3994 #define ALT_SPIS_DMACR_RSVD_DMACR_SET(value) (((value) << 2) & 0xfffffffc)
3995 
3996 #ifndef __ASSEMBLY__
3997 /*
3998  * WARNING: The C register and register group struct declarations are provided for
3999  * convenience and illustrative purposes. They should, however, be used with
4000  * caution as the C language standard provides no guarantees about the alignment or
4001  * atomicity of device memory accesses. The recommended practice for coding device
4002  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4003  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4004  * alt_write_dword() functions for 64 bit registers.
4005  *
4006  * The struct declaration for register ALT_SPIS_DMACR.
4007  */
4008 struct ALT_SPIS_DMACR_s
4009 {
4010  volatile uint32_t RDMAE : 1; /* ALT_SPIS_DMACR_RDMAE */
4011  volatile uint32_t TDMAE : 1; /* ALT_SPIS_DMACR_TDMAE */
4012  const volatile uint32_t RSVD_DMACR : 30; /* ALT_SPIS_DMACR_RSVD_DMACR */
4013 };
4014 
4015 /* The typedef declaration for register ALT_SPIS_DMACR. */
4016 typedef struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
4017 #endif /* __ASSEMBLY__ */
4018 
4019 /* The reset value of the ALT_SPIS_DMACR register. */
4020 #define ALT_SPIS_DMACR_RESET 0x00000000
4021 /* The byte offset of the ALT_SPIS_DMACR register from the beginning of the component. */
4022 #define ALT_SPIS_DMACR_OFST 0x4c
4023 /* The address of the ALT_SPIS_DMACR register. */
4024 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
4025 
4026 /*
4027  * Register : DMA Transmit Data Level - DMATDLR
4028  *
4029  * DMA Transmit Data Level.
4030  *
4031  * This register is only valid when the DW_apb_ssi is configured with a set
4032  *
4033  * of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
4034  *
4035  * configured for DMA operation, this register will not exist and writing
4036  *
4037  * to its address will have no effect; reading from its address will
4038  *
4039  * return zero.
4040  *
4041  * Register Layout
4042  *
4043  * Bits | Access | Reset | Description
4044  * :-------|:-------|:------|:------------------------------
4045  * [7:0] | RW | 0x0 | ALT_SPIS_DMATDLR_DMATDL
4046  * [31:8] | R | 0x0 | ALT_SPIS_DMATDLR_RSVD_DMATDLR
4047  *
4048  */
4049 /*
4050  * Field : DMATDL
4051  *
4052  * Transmit Data Level.
4053  *
4054  * This bit field controls the level at which a DMA request is made by the
4055  *
4056  * transmit logic. It is equal to the watermark level; that is, the
4057  *
4058  * dma_tx_req signal is generated when the number of valid data entries
4059  *
4060  * in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
4061  *
4062  * Field Access Macros:
4063  *
4064  */
4065 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
4066 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
4067 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMATDLR_DMATDL register field. */
4068 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
4069 /* The width in bits of the ALT_SPIS_DMATDLR_DMATDL register field. */
4070 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
4071 /* The mask used to set the ALT_SPIS_DMATDLR_DMATDL register field value. */
4072 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
4073 /* The mask used to clear the ALT_SPIS_DMATDLR_DMATDL register field value. */
4074 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
4075 /* The reset value of the ALT_SPIS_DMATDLR_DMATDL register field. */
4076 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
4077 /* Extracts the ALT_SPIS_DMATDLR_DMATDL field value from a register. */
4078 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
4079 /* Produces a ALT_SPIS_DMATDLR_DMATDL register field value suitable for setting the register. */
4080 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
4081 
4082 /*
4083  * Field : RSVD_DMATDLR
4084  *
4085  * Reserved bits - Read Only
4086  *
4087  * Field Access Macros:
4088  *
4089  */
4090 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field. */
4091 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_LSB 8
4092 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field. */
4093 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_MSB 31
4094 /* The width in bits of the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field. */
4095 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_WIDTH 24
4096 /* The mask used to set the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field value. */
4097 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_SET_MSK 0xffffff00
4098 /* The mask used to clear the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field value. */
4099 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_CLR_MSK 0x000000ff
4100 /* The reset value of the ALT_SPIS_DMATDLR_RSVD_DMATDLR register field. */
4101 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_RESET 0x0
4102 /* Extracts the ALT_SPIS_DMATDLR_RSVD_DMATDLR field value from a register. */
4103 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_GET(value) (((value) & 0xffffff00) >> 8)
4104 /* Produces a ALT_SPIS_DMATDLR_RSVD_DMATDLR register field value suitable for setting the register. */
4105 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_SET(value) (((value) << 8) & 0xffffff00)
4106 
4107 #ifndef __ASSEMBLY__
4108 /*
4109  * WARNING: The C register and register group struct declarations are provided for
4110  * convenience and illustrative purposes. They should, however, be used with
4111  * caution as the C language standard provides no guarantees about the alignment or
4112  * atomicity of device memory accesses. The recommended practice for coding device
4113  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4114  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4115  * alt_write_dword() functions for 64 bit registers.
4116  *
4117  * The struct declaration for register ALT_SPIS_DMATDLR.
4118  */
4119 struct ALT_SPIS_DMATDLR_s
4120 {
4121  volatile uint32_t DMATDL : 8; /* ALT_SPIS_DMATDLR_DMATDL */
4122  const volatile uint32_t RSVD_DMATDLR : 24; /* ALT_SPIS_DMATDLR_RSVD_DMATDLR */
4123 };
4124 
4125 /* The typedef declaration for register ALT_SPIS_DMATDLR. */
4126 typedef struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
4127 #endif /* __ASSEMBLY__ */
4128 
4129 /* The reset value of the ALT_SPIS_DMATDLR register. */
4130 #define ALT_SPIS_DMATDLR_RESET 0x00000000
4131 /* The byte offset of the ALT_SPIS_DMATDLR register from the beginning of the component. */
4132 #define ALT_SPIS_DMATDLR_OFST 0x50
4133 /* The address of the ALT_SPIS_DMATDLR register. */
4134 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
4135 
4136 /*
4137  * Register : DMA Receive Data Level - DMARDLR
4138  *
4139  * DMA Receive Data Level.
4140  *
4141  * This register is only valid when DW_apb_ssi is configured with a set of
4142  *
4143  * DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
4144  *
4145  * for DMA operation, this register will not exist and writing to its address
4146  *
4147  * will have no effect; reading from its address will return zero.
4148  *
4149  * Register Layout
4150  *
4151  * Bits | Access | Reset | Description
4152  * :-------|:-------|:------|:------------------------------
4153  * [7:0] | RW | 0x0 | ALT_SPIS_DMARDLR_DMARDL
4154  * [31:8] | R | 0x0 | ALT_SPIS_DMARDLR_RSVD_DMARDLR
4155  *
4156  */
4157 /*
4158  * Field : DMARDL
4159  *
4160  * Receive Data Level.
4161  *
4162  * This bit field controls the level at which a DMA request is made by the
4163  *
4164  * receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
4165  *
4166  * generated when the number of valid data entries in the receive FIFO is
4167  *
4168  * equal to or above this field value + 1, and RDMAE=1.
4169  *
4170  * Field Access Macros:
4171  *
4172  */
4173 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
4174 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
4175 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMARDLR_DMARDL register field. */
4176 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
4177 /* The width in bits of the ALT_SPIS_DMARDLR_DMARDL register field. */
4178 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
4179 /* The mask used to set the ALT_SPIS_DMARDLR_DMARDL register field value. */
4180 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
4181 /* The mask used to clear the ALT_SPIS_DMARDLR_DMARDL register field value. */
4182 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
4183 /* The reset value of the ALT_SPIS_DMARDLR_DMARDL register field. */
4184 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
4185 /* Extracts the ALT_SPIS_DMARDLR_DMARDL field value from a register. */
4186 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
4187 /* Produces a ALT_SPIS_DMARDLR_DMARDL register field value suitable for setting the register. */
4188 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
4189 
4190 /*
4191  * Field : RSVD_DMARDLR
4192  *
4193  * Reserved bits - Read Only
4194  *
4195  * Field Access Macros:
4196  *
4197  */
4198 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field. */
4199 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_LSB 8
4200 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field. */
4201 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_MSB 31
4202 /* The width in bits of the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field. */
4203 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_WIDTH 24
4204 /* The mask used to set the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field value. */
4205 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_SET_MSK 0xffffff00
4206 /* The mask used to clear the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field value. */
4207 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_CLR_MSK 0x000000ff
4208 /* The reset value of the ALT_SPIS_DMARDLR_RSVD_DMARDLR register field. */
4209 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_RESET 0x0
4210 /* Extracts the ALT_SPIS_DMARDLR_RSVD_DMARDLR field value from a register. */
4211 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_GET(value) (((value) & 0xffffff00) >> 8)
4212 /* Produces a ALT_SPIS_DMARDLR_RSVD_DMARDLR register field value suitable for setting the register. */
4213 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_SET(value) (((value) << 8) & 0xffffff00)
4214 
4215 #ifndef __ASSEMBLY__
4216 /*
4217  * WARNING: The C register and register group struct declarations are provided for
4218  * convenience and illustrative purposes. They should, however, be used with
4219  * caution as the C language standard provides no guarantees about the alignment or
4220  * atomicity of device memory accesses. The recommended practice for coding device
4221  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4222  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4223  * alt_write_dword() functions for 64 bit registers.
4224  *
4225  * The struct declaration for register ALT_SPIS_DMARDLR.
4226  */
4227 struct ALT_SPIS_DMARDLR_s
4228 {
4229  volatile uint32_t DMARDL : 8; /* ALT_SPIS_DMARDLR_DMARDL */
4230  const volatile uint32_t RSVD_DMARDLR : 24; /* ALT_SPIS_DMARDLR_RSVD_DMARDLR */
4231 };
4232 
4233 /* The typedef declaration for register ALT_SPIS_DMARDLR. */
4234 typedef struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
4235 #endif /* __ASSEMBLY__ */
4236 
4237 /* The reset value of the ALT_SPIS_DMARDLR register. */
4238 #define ALT_SPIS_DMARDLR_RESET 0x00000000
4239 /* The byte offset of the ALT_SPIS_DMARDLR register from the beginning of the component. */
4240 #define ALT_SPIS_DMARDLR_OFST 0x54
4241 /* The address of the ALT_SPIS_DMARDLR register. */
4242 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
4243 
4244 /*
4245  * Register : Identification Register - IDR
4246  *
4247  * Identification Register.
4248  *
4249  * This register contains the peripherals identification code, which is
4250  *
4251  * written into the register at configuration time using coreConsultant.
4252  *
4253  * Register Layout
4254  *
4255  * Bits | Access | Reset | Description
4256  * :-------|:-------|:----------|:--------------------
4257  * [31:0] | R | 0x5510005 | ALT_SPIS_IDR_IDCODE
4258  *
4259  */
4260 /*
4261  * Field : IDCODE
4262  *
4263  * Identification code. The register contains the peripheral's identification code,
4264  * which is written into the register at configuration time using CoreConsultant.
4265  *
4266  * Field Access Macros:
4267  *
4268  */
4269 /* The Least Significant Bit (LSB) position of the ALT_SPIS_IDR_IDCODE register field. */
4270 #define ALT_SPIS_IDR_IDCODE_LSB 0
4271 /* The Most Significant Bit (MSB) position of the ALT_SPIS_IDR_IDCODE register field. */
4272 #define ALT_SPIS_IDR_IDCODE_MSB 31
4273 /* The width in bits of the ALT_SPIS_IDR_IDCODE register field. */
4274 #define ALT_SPIS_IDR_IDCODE_WIDTH 32
4275 /* The mask used to set the ALT_SPIS_IDR_IDCODE register field value. */
4276 #define ALT_SPIS_IDR_IDCODE_SET_MSK 0xffffffff
4277 /* The mask used to clear the ALT_SPIS_IDR_IDCODE register field value. */
4278 #define ALT_SPIS_IDR_IDCODE_CLR_MSK 0x00000000
4279 /* The reset value of the ALT_SPIS_IDR_IDCODE register field. */
4280 #define ALT_SPIS_IDR_IDCODE_RESET 0x5510005
4281 /* Extracts the ALT_SPIS_IDR_IDCODE field value from a register. */
4282 #define ALT_SPIS_IDR_IDCODE_GET(value) (((value) & 0xffffffff) >> 0)
4283 /* Produces a ALT_SPIS_IDR_IDCODE register field value suitable for setting the register. */
4284 #define ALT_SPIS_IDR_IDCODE_SET(value) (((value) << 0) & 0xffffffff)
4285 
4286 #ifndef __ASSEMBLY__
4287 /*
4288  * WARNING: The C register and register group struct declarations are provided for
4289  * convenience and illustrative purposes. They should, however, be used with
4290  * caution as the C language standard provides no guarantees about the alignment or
4291  * atomicity of device memory accesses. The recommended practice for coding device
4292  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4293  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4294  * alt_write_dword() functions for 64 bit registers.
4295  *
4296  * The struct declaration for register ALT_SPIS_IDR.
4297  */
4298 struct ALT_SPIS_IDR_s
4299 {
4300  const volatile uint32_t IDCODE : 32; /* ALT_SPIS_IDR_IDCODE */
4301 };
4302 
4303 /* The typedef declaration for register ALT_SPIS_IDR. */
4304 typedef struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
4305 #endif /* __ASSEMBLY__ */
4306 
4307 /* The reset value of the ALT_SPIS_IDR register. */
4308 #define ALT_SPIS_IDR_RESET 0x05510005
4309 /* The byte offset of the ALT_SPIS_IDR register from the beginning of the component. */
4310 #define ALT_SPIS_IDR_OFST 0x58
4311 /* The address of the ALT_SPIS_IDR register. */
4312 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
4313 
4314 /*
4315  * Register : SSI_VERSION_ID
4316  *
4317  * coreKit Version ID Register
4318  *
4319  * Register Layout
4320  *
4321  * Bits | Access | Reset | Description
4322  * :-------|:-------|:-----------|:-----------------------------------------
4323  * [31:0] | R | 0x3430302a | ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION
4324  *
4325  */
4326 /*
4327  * Field : SSI_COMP_VERSION
4328  *
4329  * Contains the hex representation of the Synopsys component version. Consists of
4330  * ASCII value for each number in the version, followed by *. For example
4331  * 32_30_31_2A represents the version 2.01*.
4332  *
4333  * Field Access Macros:
4334  *
4335  */
4336 /* The Least Significant Bit (LSB) position of the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4337 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0
4338 /* The Most Significant Bit (MSB) position of the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4339 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31
4340 /* The width in bits of the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4341 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_WIDTH 32
4342 /* The mask used to set the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field value. */
4343 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_SET_MSK 0xffffffff
4344 /* The mask used to clear the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field value. */
4345 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_CLR_MSK 0x00000000
4346 /* The reset value of the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4347 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430302a
4348 /* Extracts the ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION field value from a register. */
4349 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
4350 /* Produces a ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION register field value suitable for setting the register. */
4351 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
4352 
4353 #ifndef __ASSEMBLY__
4354 /*
4355  * WARNING: The C register and register group struct declarations are provided for
4356  * convenience and illustrative purposes. They should, however, be used with
4357  * caution as the C language standard provides no guarantees about the alignment or
4358  * atomicity of device memory accesses. The recommended practice for coding device
4359  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4360  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4361  * alt_write_dword() functions for 64 bit registers.
4362  *
4363  * The struct declaration for register ALT_SPIS_SSI_VERSION_ID.
4364  */
4365 struct ALT_SPIS_SSI_VERSION_ID_s
4366 {
4367  const volatile uint32_t SSI_COMP_VERSION : 32; /* ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION */
4368 };
4369 
4370 /* The typedef declaration for register ALT_SPIS_SSI_VERSION_ID. */
4371 typedef struct ALT_SPIS_SSI_VERSION_ID_s ALT_SPIS_SSI_VERSION_ID_t;
4372 #endif /* __ASSEMBLY__ */
4373 
4374 /* The reset value of the ALT_SPIS_SSI_VERSION_ID register. */
4375 #define ALT_SPIS_SSI_VERSION_ID_RESET 0x3430302a
4376 /* The byte offset of the ALT_SPIS_SSI_VERSION_ID register from the beginning of the component. */
4377 #define ALT_SPIS_SSI_VERSION_ID_OFST 0x5c
4378 /* The address of the ALT_SPIS_SSI_VERSION_ID register. */
4379 #define ALT_SPIS_SSI_VERSION_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SSI_VERSION_ID_OFST))
4380 
4381 /*
4382  * Register : DW_apb_ssi Data Register - DR0
4383  *
4384  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4385  * read/write buffer for
4386  *
4387  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4388  * set to 32, then all 32 bits
4389  *
4390  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4391  * register is read, data in the
4392  *
4393  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4394  * transmit FIFO buffer; a write
4395  *
4396  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4397  *
4398  * Register Layout
4399  *
4400  * Bits | Access | Reset | Description
4401  * :-------|:-------|:------|:-----------------
4402  * [31:0] | RW | 0x0 | ALT_SPIS_DR0_DR0
4403  *
4404  */
4405 /*
4406  * Field : dr0
4407  *
4408  * Data Register. When writing to this register, you must right-justify the data.
4409  * Read
4410  *
4411  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4412  *
4413  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4414  * of the
4415  *
4416  * register are valid.
4417  *
4418  * Read = Receive FIFO buffer
4419  *
4420  * Write = Transmit FIFO buffer.
4421  *
4422  * Field Access Macros:
4423  *
4424  */
4425 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR0_DR0 register field. */
4426 #define ALT_SPIS_DR0_DR0_LSB 0
4427 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR0_DR0 register field. */
4428 #define ALT_SPIS_DR0_DR0_MSB 31
4429 /* The width in bits of the ALT_SPIS_DR0_DR0 register field. */
4430 #define ALT_SPIS_DR0_DR0_WIDTH 32
4431 /* The mask used to set the ALT_SPIS_DR0_DR0 register field value. */
4432 #define ALT_SPIS_DR0_DR0_SET_MSK 0xffffffff
4433 /* The mask used to clear the ALT_SPIS_DR0_DR0 register field value. */
4434 #define ALT_SPIS_DR0_DR0_CLR_MSK 0x00000000
4435 /* The reset value of the ALT_SPIS_DR0_DR0 register field. */
4436 #define ALT_SPIS_DR0_DR0_RESET 0x0
4437 /* Extracts the ALT_SPIS_DR0_DR0 field value from a register. */
4438 #define ALT_SPIS_DR0_DR0_GET(value) (((value) & 0xffffffff) >> 0)
4439 /* Produces a ALT_SPIS_DR0_DR0 register field value suitable for setting the register. */
4440 #define ALT_SPIS_DR0_DR0_SET(value) (((value) << 0) & 0xffffffff)
4441 
4442 #ifndef __ASSEMBLY__
4443 /*
4444  * WARNING: The C register and register group struct declarations are provided for
4445  * convenience and illustrative purposes. They should, however, be used with
4446  * caution as the C language standard provides no guarantees about the alignment or
4447  * atomicity of device memory accesses. The recommended practice for coding device
4448  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4449  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4450  * alt_write_dword() functions for 64 bit registers.
4451  *
4452  * The struct declaration for register ALT_SPIS_DR0.
4453  */
4454 struct ALT_SPIS_DR0_s
4455 {
4456  volatile uint32_t dr0 : 32; /* ALT_SPIS_DR0_DR0 */
4457 };
4458 
4459 /* The typedef declaration for register ALT_SPIS_DR0. */
4460 typedef struct ALT_SPIS_DR0_s ALT_SPIS_DR0_t;
4461 #endif /* __ASSEMBLY__ */
4462 
4463 /* The reset value of the ALT_SPIS_DR0 register. */
4464 #define ALT_SPIS_DR0_RESET 0x00000000
4465 /* The byte offset of the ALT_SPIS_DR0 register from the beginning of the component. */
4466 #define ALT_SPIS_DR0_OFST 0x60
4467 /* The address of the ALT_SPIS_DR0 register. */
4468 #define ALT_SPIS_DR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR0_OFST))
4469 
4470 /*
4471  * Register : DW_apb_ssi Data Register - DR1
4472  *
4473  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4474  * read/write buffer for
4475  *
4476  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4477  * set to 32, then all 32 bits
4478  *
4479  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4480  * register is read, data in the
4481  *
4482  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4483  * transmit FIFO buffer; a write
4484  *
4485  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4486  *
4487  * Register Layout
4488  *
4489  * Bits | Access | Reset | Description
4490  * :-------|:-------|:------|:-----------------
4491  * [31:0] | RW | 0x0 | ALT_SPIS_DR1_DR1
4492  *
4493  */
4494 /*
4495  * Field : dr1
4496  *
4497  * Data Register. When writing to this register, you must right-justify the data.
4498  * Read
4499  *
4500  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4501  *
4502  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4503  * of the
4504  *
4505  * register are valid.
4506  *
4507  * Read = Receive FIFO buffer
4508  *
4509  * Write = Transmit FIFO buffer.
4510  *
4511  * Field Access Macros:
4512  *
4513  */
4514 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR1_DR1 register field. */
4515 #define ALT_SPIS_DR1_DR1_LSB 0
4516 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR1_DR1 register field. */
4517 #define ALT_SPIS_DR1_DR1_MSB 31
4518 /* The width in bits of the ALT_SPIS_DR1_DR1 register field. */
4519 #define ALT_SPIS_DR1_DR1_WIDTH 32
4520 /* The mask used to set the ALT_SPIS_DR1_DR1 register field value. */
4521 #define ALT_SPIS_DR1_DR1_SET_MSK 0xffffffff
4522 /* The mask used to clear the ALT_SPIS_DR1_DR1 register field value. */
4523 #define ALT_SPIS_DR1_DR1_CLR_MSK 0x00000000
4524 /* The reset value of the ALT_SPIS_DR1_DR1 register field. */
4525 #define ALT_SPIS_DR1_DR1_RESET 0x0
4526 /* Extracts the ALT_SPIS_DR1_DR1 field value from a register. */
4527 #define ALT_SPIS_DR1_DR1_GET(value) (((value) & 0xffffffff) >> 0)
4528 /* Produces a ALT_SPIS_DR1_DR1 register field value suitable for setting the register. */
4529 #define ALT_SPIS_DR1_DR1_SET(value) (((value) << 0) & 0xffffffff)
4530 
4531 #ifndef __ASSEMBLY__
4532 /*
4533  * WARNING: The C register and register group struct declarations are provided for
4534  * convenience and illustrative purposes. They should, however, be used with
4535  * caution as the C language standard provides no guarantees about the alignment or
4536  * atomicity of device memory accesses. The recommended practice for coding device
4537  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4538  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4539  * alt_write_dword() functions for 64 bit registers.
4540  *
4541  * The struct declaration for register ALT_SPIS_DR1.
4542  */
4543 struct ALT_SPIS_DR1_s
4544 {
4545  volatile uint32_t dr1 : 32; /* ALT_SPIS_DR1_DR1 */
4546 };
4547 
4548 /* The typedef declaration for register ALT_SPIS_DR1. */
4549 typedef struct ALT_SPIS_DR1_s ALT_SPIS_DR1_t;
4550 #endif /* __ASSEMBLY__ */
4551 
4552 /* The reset value of the ALT_SPIS_DR1 register. */
4553 #define ALT_SPIS_DR1_RESET 0x00000000
4554 /* The byte offset of the ALT_SPIS_DR1 register from the beginning of the component. */
4555 #define ALT_SPIS_DR1_OFST 0x64
4556 /* The address of the ALT_SPIS_DR1 register. */
4557 #define ALT_SPIS_DR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR1_OFST))
4558 
4559 /*
4560  * Register : DW_apb_ssi Data Register - DR2
4561  *
4562  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4563  * read/write buffer for
4564  *
4565  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4566  * set to 32, then all 32 bits
4567  *
4568  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4569  * register is read, data in the
4570  *
4571  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4572  * transmit FIFO buffer; a write
4573  *
4574  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4575  *
4576  * Register Layout
4577  *
4578  * Bits | Access | Reset | Description
4579  * :-------|:-------|:------|:-----------------
4580  * [31:0] | RW | 0x0 | ALT_SPIS_DR2_DR2
4581  *
4582  */
4583 /*
4584  * Field : dr2
4585  *
4586  * Data Register. When writing to this register, you must right-justify the data.
4587  * Read
4588  *
4589  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4590  *
4591  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4592  * of the
4593  *
4594  * register are valid.
4595  *
4596  * Read = Receive FIFO buffer
4597  *
4598  * Write = Transmit FIFO buffer.
4599  *
4600  * Field Access Macros:
4601  *
4602  */
4603 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR2_DR2 register field. */
4604 #define ALT_SPIS_DR2_DR2_LSB 0
4605 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR2_DR2 register field. */
4606 #define ALT_SPIS_DR2_DR2_MSB 31
4607 /* The width in bits of the ALT_SPIS_DR2_DR2 register field. */
4608 #define ALT_SPIS_DR2_DR2_WIDTH 32
4609 /* The mask used to set the ALT_SPIS_DR2_DR2 register field value. */
4610 #define ALT_SPIS_DR2_DR2_SET_MSK 0xffffffff
4611 /* The mask used to clear the ALT_SPIS_DR2_DR2 register field value. */
4612 #define ALT_SPIS_DR2_DR2_CLR_MSK 0x00000000
4613 /* The reset value of the ALT_SPIS_DR2_DR2 register field. */
4614 #define ALT_SPIS_DR2_DR2_RESET 0x0
4615 /* Extracts the ALT_SPIS_DR2_DR2 field value from a register. */
4616 #define ALT_SPIS_DR2_DR2_GET(value) (((value) & 0xffffffff) >> 0)
4617 /* Produces a ALT_SPIS_DR2_DR2 register field value suitable for setting the register. */
4618 #define ALT_SPIS_DR2_DR2_SET(value) (((value) << 0) & 0xffffffff)
4619 
4620 #ifndef __ASSEMBLY__
4621 /*
4622  * WARNING: The C register and register group struct declarations are provided for
4623  * convenience and illustrative purposes. They should, however, be used with
4624  * caution as the C language standard provides no guarantees about the alignment or
4625  * atomicity of device memory accesses. The recommended practice for coding device
4626  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4627  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4628  * alt_write_dword() functions for 64 bit registers.
4629  *
4630  * The struct declaration for register ALT_SPIS_DR2.
4631  */
4632 struct ALT_SPIS_DR2_s
4633 {
4634  volatile uint32_t dr2 : 32; /* ALT_SPIS_DR2_DR2 */
4635 };
4636 
4637 /* The typedef declaration for register ALT_SPIS_DR2. */
4638 typedef struct ALT_SPIS_DR2_s ALT_SPIS_DR2_t;
4639 #endif /* __ASSEMBLY__ */
4640 
4641 /* The reset value of the ALT_SPIS_DR2 register. */
4642 #define ALT_SPIS_DR2_RESET 0x00000000
4643 /* The byte offset of the ALT_SPIS_DR2 register from the beginning of the component. */
4644 #define ALT_SPIS_DR2_OFST 0x68
4645 /* The address of the ALT_SPIS_DR2 register. */
4646 #define ALT_SPIS_DR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR2_OFST))
4647 
4648 /*
4649  * Register : DW_apb_ssi Data Register - DR3
4650  *
4651  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4652  * read/write buffer for
4653  *
4654  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4655  * set to 32, then all 32 bits
4656  *
4657  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4658  * register is read, data in the
4659  *
4660  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4661  * transmit FIFO buffer; a write
4662  *
4663  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4664  *
4665  * Register Layout
4666  *
4667  * Bits | Access | Reset | Description
4668  * :-------|:-------|:------|:-----------------
4669  * [31:0] | RW | 0x0 | ALT_SPIS_DR3_DR3
4670  *
4671  */
4672 /*
4673  * Field : dr3
4674  *
4675  * Data Register. When writing to this register, you must right-justify the data.
4676  * Read
4677  *
4678  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4679  *
4680  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4681  * of the
4682  *
4683  * register are valid.
4684  *
4685  * Read = Receive FIFO buffer
4686  *
4687  * Write = Transmit FIFO buffer.
4688  *
4689  * Field Access Macros:
4690  *
4691  */
4692 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR3_DR3 register field. */
4693 #define ALT_SPIS_DR3_DR3_LSB 0
4694 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR3_DR3 register field. */
4695 #define ALT_SPIS_DR3_DR3_MSB 31
4696 /* The width in bits of the ALT_SPIS_DR3_DR3 register field. */
4697 #define ALT_SPIS_DR3_DR3_WIDTH 32
4698 /* The mask used to set the ALT_SPIS_DR3_DR3 register field value. */
4699 #define ALT_SPIS_DR3_DR3_SET_MSK 0xffffffff
4700 /* The mask used to clear the ALT_SPIS_DR3_DR3 register field value. */
4701 #define ALT_SPIS_DR3_DR3_CLR_MSK 0x00000000
4702 /* The reset value of the ALT_SPIS_DR3_DR3 register field. */
4703 #define ALT_SPIS_DR3_DR3_RESET 0x0
4704 /* Extracts the ALT_SPIS_DR3_DR3 field value from a register. */
4705 #define ALT_SPIS_DR3_DR3_GET(value) (((value) & 0xffffffff) >> 0)
4706 /* Produces a ALT_SPIS_DR3_DR3 register field value suitable for setting the register. */
4707 #define ALT_SPIS_DR3_DR3_SET(value) (((value) << 0) & 0xffffffff)
4708 
4709 #ifndef __ASSEMBLY__
4710 /*
4711  * WARNING: The C register and register group struct declarations are provided for
4712  * convenience and illustrative purposes. They should, however, be used with
4713  * caution as the C language standard provides no guarantees about the alignment or
4714  * atomicity of device memory accesses. The recommended practice for coding device
4715  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4716  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4717  * alt_write_dword() functions for 64 bit registers.
4718  *
4719  * The struct declaration for register ALT_SPIS_DR3.
4720  */
4721 struct ALT_SPIS_DR3_s
4722 {
4723  volatile uint32_t dr3 : 32; /* ALT_SPIS_DR3_DR3 */
4724 };
4725 
4726 /* The typedef declaration for register ALT_SPIS_DR3. */
4727 typedef struct ALT_SPIS_DR3_s ALT_SPIS_DR3_t;
4728 #endif /* __ASSEMBLY__ */
4729 
4730 /* The reset value of the ALT_SPIS_DR3 register. */
4731 #define ALT_SPIS_DR3_RESET 0x00000000
4732 /* The byte offset of the ALT_SPIS_DR3 register from the beginning of the component. */
4733 #define ALT_SPIS_DR3_OFST 0x6c
4734 /* The address of the ALT_SPIS_DR3 register. */
4735 #define ALT_SPIS_DR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR3_OFST))
4736 
4737 /*
4738  * Register : DW_apb_ssi Data Register - DR4
4739  *
4740  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4741  * read/write buffer for
4742  *
4743  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4744  * set to 32, then all 32 bits
4745  *
4746  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4747  * register is read, data in the
4748  *
4749  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4750  * transmit FIFO buffer; a write
4751  *
4752  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4753  *
4754  * Register Layout
4755  *
4756  * Bits | Access | Reset | Description
4757  * :-------|:-------|:------|:-----------------
4758  * [31:0] | RW | 0x0 | ALT_SPIS_DR4_DR4
4759  *
4760  */
4761 /*
4762  * Field : dr4
4763  *
4764  * Data Register. When writing to this register, you must right-justify the data.
4765  * Read
4766  *
4767  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4768  *
4769  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4770  * of the
4771  *
4772  * register are valid.
4773  *
4774  * Read = Receive FIFO buffer
4775  *
4776  * Write = Transmit FIFO buffer.
4777  *
4778  * Field Access Macros:
4779  *
4780  */
4781 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR4_DR4 register field. */
4782 #define ALT_SPIS_DR4_DR4_LSB 0
4783 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR4_DR4 register field. */
4784 #define ALT_SPIS_DR4_DR4_MSB 31
4785 /* The width in bits of the ALT_SPIS_DR4_DR4 register field. */
4786 #define ALT_SPIS_DR4_DR4_WIDTH 32
4787 /* The mask used to set the ALT_SPIS_DR4_DR4 register field value. */
4788 #define ALT_SPIS_DR4_DR4_SET_MSK 0xffffffff
4789 /* The mask used to clear the ALT_SPIS_DR4_DR4 register field value. */
4790 #define ALT_SPIS_DR4_DR4_CLR_MSK 0x00000000
4791 /* The reset value of the ALT_SPIS_DR4_DR4 register field. */
4792 #define ALT_SPIS_DR4_DR4_RESET 0x0
4793 /* Extracts the ALT_SPIS_DR4_DR4 field value from a register. */
4794 #define ALT_SPIS_DR4_DR4_GET(value) (((value) & 0xffffffff) >> 0)
4795 /* Produces a ALT_SPIS_DR4_DR4 register field value suitable for setting the register. */
4796 #define ALT_SPIS_DR4_DR4_SET(value) (((value) << 0) & 0xffffffff)
4797 
4798 #ifndef __ASSEMBLY__
4799 /*
4800  * WARNING: The C register and register group struct declarations are provided for
4801  * convenience and illustrative purposes. They should, however, be used with
4802  * caution as the C language standard provides no guarantees about the alignment or
4803  * atomicity of device memory accesses. The recommended practice for coding device
4804  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4805  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4806  * alt_write_dword() functions for 64 bit registers.
4807  *
4808  * The struct declaration for register ALT_SPIS_DR4.
4809  */
4810 struct ALT_SPIS_DR4_s
4811 {
4812  volatile uint32_t dr4 : 32; /* ALT_SPIS_DR4_DR4 */
4813 };
4814 
4815 /* The typedef declaration for register ALT_SPIS_DR4. */
4816 typedef struct ALT_SPIS_DR4_s ALT_SPIS_DR4_t;
4817 #endif /* __ASSEMBLY__ */
4818 
4819 /* The reset value of the ALT_SPIS_DR4 register. */
4820 #define ALT_SPIS_DR4_RESET 0x00000000
4821 /* The byte offset of the ALT_SPIS_DR4 register from the beginning of the component. */
4822 #define ALT_SPIS_DR4_OFST 0x70
4823 /* The address of the ALT_SPIS_DR4 register. */
4824 #define ALT_SPIS_DR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR4_OFST))
4825 
4826 /*
4827  * Register : DW_apb_ssi Data Register - DR5
4828  *
4829  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4830  * read/write buffer for
4831  *
4832  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4833  * set to 32, then all 32 bits
4834  *
4835  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4836  * register is read, data in the
4837  *
4838  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4839  * transmit FIFO buffer; a write
4840  *
4841  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4842  *
4843  * Register Layout
4844  *
4845  * Bits | Access | Reset | Description
4846  * :-------|:-------|:------|:-----------------
4847  * [31:0] | RW | 0x0 | ALT_SPIS_DR5_DR5
4848  *
4849  */
4850 /*
4851  * Field : dr5
4852  *
4853  * Data Register. When writing to this register, you must right-justify the data.
4854  * Read
4855  *
4856  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4857  *
4858  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4859  * of the
4860  *
4861  * register are valid.
4862  *
4863  * Read = Receive FIFO buffer
4864  *
4865  * Write = Transmit FIFO buffer.
4866  *
4867  * Field Access Macros:
4868  *
4869  */
4870 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR5_DR5 register field. */
4871 #define ALT_SPIS_DR5_DR5_LSB 0
4872 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR5_DR5 register field. */
4873 #define ALT_SPIS_DR5_DR5_MSB 31
4874 /* The width in bits of the ALT_SPIS_DR5_DR5 register field. */
4875 #define ALT_SPIS_DR5_DR5_WIDTH 32
4876 /* The mask used to set the ALT_SPIS_DR5_DR5 register field value. */
4877 #define ALT_SPIS_DR5_DR5_SET_MSK 0xffffffff
4878 /* The mask used to clear the ALT_SPIS_DR5_DR5 register field value. */
4879 #define ALT_SPIS_DR5_DR5_CLR_MSK 0x00000000
4880 /* The reset value of the ALT_SPIS_DR5_DR5 register field. */
4881 #define ALT_SPIS_DR5_DR5_RESET 0x0
4882 /* Extracts the ALT_SPIS_DR5_DR5 field value from a register. */
4883 #define ALT_SPIS_DR5_DR5_GET(value) (((value) & 0xffffffff) >> 0)
4884 /* Produces a ALT_SPIS_DR5_DR5 register field value suitable for setting the register. */
4885 #define ALT_SPIS_DR5_DR5_SET(value) (((value) << 0) & 0xffffffff)
4886 
4887 #ifndef __ASSEMBLY__
4888 /*
4889  * WARNING: The C register and register group struct declarations are provided for
4890  * convenience and illustrative purposes. They should, however, be used with
4891  * caution as the C language standard provides no guarantees about the alignment or
4892  * atomicity of device memory accesses. The recommended practice for coding device
4893  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4894  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4895  * alt_write_dword() functions for 64 bit registers.
4896  *
4897  * The struct declaration for register ALT_SPIS_DR5.
4898  */
4899 struct ALT_SPIS_DR5_s
4900 {
4901  volatile uint32_t dr5 : 32; /* ALT_SPIS_DR5_DR5 */
4902 };
4903 
4904 /* The typedef declaration for register ALT_SPIS_DR5. */
4905 typedef struct ALT_SPIS_DR5_s ALT_SPIS_DR5_t;
4906 #endif /* __ASSEMBLY__ */
4907 
4908 /* The reset value of the ALT_SPIS_DR5 register. */
4909 #define ALT_SPIS_DR5_RESET 0x00000000
4910 /* The byte offset of the ALT_SPIS_DR5 register from the beginning of the component. */
4911 #define ALT_SPIS_DR5_OFST 0x74
4912 /* The address of the ALT_SPIS_DR5 register. */
4913 #define ALT_SPIS_DR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR5_OFST))
4914 
4915 /*
4916  * Register : DW_apb_ssi Data Register - DR6
4917  *
4918  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4919  * read/write buffer for
4920  *
4921  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4922  * set to 32, then all 32 bits
4923  *
4924  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4925  * register is read, data in the
4926  *
4927  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4928  * transmit FIFO buffer; a write
4929  *
4930  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4931  *
4932  * Register Layout
4933  *
4934  * Bits | Access | Reset | Description
4935  * :-------|:-------|:------|:-----------------
4936  * [31:0] | RW | 0x0 | ALT_SPIS_DR6_DR6
4937  *
4938  */
4939 /*
4940  * Field : dr6
4941  *
4942  * Data Register. When writing to this register, you must right-justify the data.
4943  * Read
4944  *
4945  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4946  *
4947  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4948  * of the
4949  *
4950  * register are valid.
4951  *
4952  * Read = Receive FIFO buffer
4953  *
4954  * Write = Transmit FIFO buffer.
4955  *
4956  * Field Access Macros:
4957  *
4958  */
4959 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR6_DR6 register field. */
4960 #define ALT_SPIS_DR6_DR6_LSB 0
4961 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR6_DR6 register field. */
4962 #define ALT_SPIS_DR6_DR6_MSB 31
4963 /* The width in bits of the ALT_SPIS_DR6_DR6 register field. */
4964 #define ALT_SPIS_DR6_DR6_WIDTH 32
4965 /* The mask used to set the ALT_SPIS_DR6_DR6 register field value. */
4966 #define ALT_SPIS_DR6_DR6_SET_MSK 0xffffffff
4967 /* The mask used to clear the ALT_SPIS_DR6_DR6 register field value. */
4968 #define ALT_SPIS_DR6_DR6_CLR_MSK 0x00000000
4969 /* The reset value of the ALT_SPIS_DR6_DR6 register field. */
4970 #define ALT_SPIS_DR6_DR6_RESET 0x0
4971 /* Extracts the ALT_SPIS_DR6_DR6 field value from a register. */
4972 #define ALT_SPIS_DR6_DR6_GET(value) (((value) & 0xffffffff) >> 0)
4973 /* Produces a ALT_SPIS_DR6_DR6 register field value suitable for setting the register. */
4974 #define ALT_SPIS_DR6_DR6_SET(value) (((value) << 0) & 0xffffffff)
4975 
4976 #ifndef __ASSEMBLY__
4977 /*
4978  * WARNING: The C register and register group struct declarations are provided for
4979  * convenience and illustrative purposes. They should, however, be used with
4980  * caution as the C language standard provides no guarantees about the alignment or
4981  * atomicity of device memory accesses. The recommended practice for coding device
4982  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4983  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4984  * alt_write_dword() functions for 64 bit registers.
4985  *
4986  * The struct declaration for register ALT_SPIS_DR6.
4987  */
4988 struct ALT_SPIS_DR6_s
4989 {
4990  volatile uint32_t dr6 : 32; /* ALT_SPIS_DR6_DR6 */
4991 };
4992 
4993 /* The typedef declaration for register ALT_SPIS_DR6. */
4994 typedef struct ALT_SPIS_DR6_s ALT_SPIS_DR6_t;
4995 #endif /* __ASSEMBLY__ */
4996 
4997 /* The reset value of the ALT_SPIS_DR6 register. */
4998 #define ALT_SPIS_DR6_RESET 0x00000000
4999 /* The byte offset of the ALT_SPIS_DR6 register from the beginning of the component. */
5000 #define ALT_SPIS_DR6_OFST 0x78
5001 /* The address of the ALT_SPIS_DR6 register. */
5002 #define ALT_SPIS_DR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR6_OFST))
5003 
5004 /*
5005  * Register : DW_apb_ssi Data Register - DR7
5006  *
5007  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5008  * read/write buffer for
5009  *
5010  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5011  * set to 32, then all 32 bits
5012  *
5013  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5014  * register is read, data in the
5015  *
5016  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5017  * transmit FIFO buffer; a write
5018  *
5019  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5020  *
5021  * Register Layout
5022  *
5023  * Bits | Access | Reset | Description
5024  * :-------|:-------|:------|:-----------------
5025  * [31:0] | RW | 0x0 | ALT_SPIS_DR7_DR7
5026  *
5027  */
5028 /*
5029  * Field : dr7
5030  *
5031  * Data Register. When writing to this register, you must right-justify the data.
5032  * Read
5033  *
5034  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5035  *
5036  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5037  * of the
5038  *
5039  * register are valid.
5040  *
5041  * Read = Receive FIFO buffer
5042  *
5043  * Write = Transmit FIFO buffer.
5044  *
5045  * Field Access Macros:
5046  *
5047  */
5048 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR7_DR7 register field. */
5049 #define ALT_SPIS_DR7_DR7_LSB 0
5050 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR7_DR7 register field. */
5051 #define ALT_SPIS_DR7_DR7_MSB 31
5052 /* The width in bits of the ALT_SPIS_DR7_DR7 register field. */
5053 #define ALT_SPIS_DR7_DR7_WIDTH 32
5054 /* The mask used to set the ALT_SPIS_DR7_DR7 register field value. */
5055 #define ALT_SPIS_DR7_DR7_SET_MSK 0xffffffff
5056 /* The mask used to clear the ALT_SPIS_DR7_DR7 register field value. */
5057 #define ALT_SPIS_DR7_DR7_CLR_MSK 0x00000000
5058 /* The reset value of the ALT_SPIS_DR7_DR7 register field. */
5059 #define ALT_SPIS_DR7_DR7_RESET 0x0
5060 /* Extracts the ALT_SPIS_DR7_DR7 field value from a register. */
5061 #define ALT_SPIS_DR7_DR7_GET(value) (((value) & 0xffffffff) >> 0)
5062 /* Produces a ALT_SPIS_DR7_DR7 register field value suitable for setting the register. */
5063 #define ALT_SPIS_DR7_DR7_SET(value) (((value) << 0) & 0xffffffff)
5064 
5065 #ifndef __ASSEMBLY__
5066 /*
5067  * WARNING: The C register and register group struct declarations are provided for
5068  * convenience and illustrative purposes. They should, however, be used with
5069  * caution as the C language standard provides no guarantees about the alignment or
5070  * atomicity of device memory accesses. The recommended practice for coding device
5071  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5072  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5073  * alt_write_dword() functions for 64 bit registers.
5074  *
5075  * The struct declaration for register ALT_SPIS_DR7.
5076  */
5077 struct ALT_SPIS_DR7_s
5078 {
5079  volatile uint32_t dr7 : 32; /* ALT_SPIS_DR7_DR7 */
5080 };
5081 
5082 /* The typedef declaration for register ALT_SPIS_DR7. */
5083 typedef struct ALT_SPIS_DR7_s ALT_SPIS_DR7_t;
5084 #endif /* __ASSEMBLY__ */
5085 
5086 /* The reset value of the ALT_SPIS_DR7 register. */
5087 #define ALT_SPIS_DR7_RESET 0x00000000
5088 /* The byte offset of the ALT_SPIS_DR7 register from the beginning of the component. */
5089 #define ALT_SPIS_DR7_OFST 0x7c
5090 /* The address of the ALT_SPIS_DR7 register. */
5091 #define ALT_SPIS_DR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR7_OFST))
5092 
5093 /*
5094  * Register : DW_apb_ssi Data Register - DR8
5095  *
5096  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5097  * read/write buffer for
5098  *
5099  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5100  * set to 32, then all 32 bits
5101  *
5102  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5103  * register is read, data in the
5104  *
5105  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5106  * transmit FIFO buffer; a write
5107  *
5108  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5109  *
5110  * Register Layout
5111  *
5112  * Bits | Access | Reset | Description
5113  * :-------|:-------|:------|:-----------------
5114  * [31:0] | RW | 0x0 | ALT_SPIS_DR8_DR8
5115  *
5116  */
5117 /*
5118  * Field : dr8
5119  *
5120  * Data Register. When writing to this register, you must right-justify the data.
5121  * Read
5122  *
5123  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5124  *
5125  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5126  * of the
5127  *
5128  * register are valid.
5129  *
5130  * Read = Receive FIFO buffer
5131  *
5132  * Write = Transmit FIFO buffer.
5133  *
5134  * Field Access Macros:
5135  *
5136  */
5137 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR8_DR8 register field. */
5138 #define ALT_SPIS_DR8_DR8_LSB 0
5139 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR8_DR8 register field. */
5140 #define ALT_SPIS_DR8_DR8_MSB 31
5141 /* The width in bits of the ALT_SPIS_DR8_DR8 register field. */
5142 #define ALT_SPIS_DR8_DR8_WIDTH 32
5143 /* The mask used to set the ALT_SPIS_DR8_DR8 register field value. */
5144 #define ALT_SPIS_DR8_DR8_SET_MSK 0xffffffff
5145 /* The mask used to clear the ALT_SPIS_DR8_DR8 register field value. */
5146 #define ALT_SPIS_DR8_DR8_CLR_MSK 0x00000000
5147 /* The reset value of the ALT_SPIS_DR8_DR8 register field. */
5148 #define ALT_SPIS_DR8_DR8_RESET 0x0
5149 /* Extracts the ALT_SPIS_DR8_DR8 field value from a register. */
5150 #define ALT_SPIS_DR8_DR8_GET(value) (((value) & 0xffffffff) >> 0)
5151 /* Produces a ALT_SPIS_DR8_DR8 register field value suitable for setting the register. */
5152 #define ALT_SPIS_DR8_DR8_SET(value) (((value) << 0) & 0xffffffff)
5153 
5154 #ifndef __ASSEMBLY__
5155 /*
5156  * WARNING: The C register and register group struct declarations are provided for
5157  * convenience and illustrative purposes. They should, however, be used with
5158  * caution as the C language standard provides no guarantees about the alignment or
5159  * atomicity of device memory accesses. The recommended practice for coding device
5160  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5161  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5162  * alt_write_dword() functions for 64 bit registers.
5163  *
5164  * The struct declaration for register ALT_SPIS_DR8.
5165  */
5166 struct ALT_SPIS_DR8_s
5167 {
5168  volatile uint32_t dr8 : 32; /* ALT_SPIS_DR8_DR8 */
5169 };
5170 
5171 /* The typedef declaration for register ALT_SPIS_DR8. */
5172 typedef struct ALT_SPIS_DR8_s ALT_SPIS_DR8_t;
5173 #endif /* __ASSEMBLY__ */
5174 
5175 /* The reset value of the ALT_SPIS_DR8 register. */
5176 #define ALT_SPIS_DR8_RESET 0x00000000
5177 /* The byte offset of the ALT_SPIS_DR8 register from the beginning of the component. */
5178 #define ALT_SPIS_DR8_OFST 0x80
5179 /* The address of the ALT_SPIS_DR8 register. */
5180 #define ALT_SPIS_DR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR8_OFST))
5181 
5182 /*
5183  * Register : DW_apb_ssi Data Register - DR9
5184  *
5185  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5186  * read/write buffer for
5187  *
5188  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5189  * set to 32, then all 32 bits
5190  *
5191  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5192  * register is read, data in the
5193  *
5194  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5195  * transmit FIFO buffer; a write
5196  *
5197  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5198  *
5199  * Register Layout
5200  *
5201  * Bits | Access | Reset | Description
5202  * :-------|:-------|:------|:-----------------
5203  * [31:0] | RW | 0x0 | ALT_SPIS_DR9_DR9
5204  *
5205  */
5206 /*
5207  * Field : dr9
5208  *
5209  * Data Register. When writing to this register, you must right-justify the data.
5210  * Read
5211  *
5212  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5213  *
5214  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5215  * of the
5216  *
5217  * register are valid.
5218  *
5219  * Read = Receive FIFO buffer
5220  *
5221  * Write = Transmit FIFO buffer.
5222  *
5223  * Field Access Macros:
5224  *
5225  */
5226 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR9_DR9 register field. */
5227 #define ALT_SPIS_DR9_DR9_LSB 0
5228 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR9_DR9 register field. */
5229 #define ALT_SPIS_DR9_DR9_MSB 31
5230 /* The width in bits of the ALT_SPIS_DR9_DR9 register field. */
5231 #define ALT_SPIS_DR9_DR9_WIDTH 32
5232 /* The mask used to set the ALT_SPIS_DR9_DR9 register field value. */
5233 #define ALT_SPIS_DR9_DR9_SET_MSK 0xffffffff
5234 /* The mask used to clear the ALT_SPIS_DR9_DR9 register field value. */
5235 #define ALT_SPIS_DR9_DR9_CLR_MSK 0x00000000
5236 /* The reset value of the ALT_SPIS_DR9_DR9 register field. */
5237 #define ALT_SPIS_DR9_DR9_RESET 0x0
5238 /* Extracts the ALT_SPIS_DR9_DR9 field value from a register. */
5239 #define ALT_SPIS_DR9_DR9_GET(value) (((value) & 0xffffffff) >> 0)
5240 /* Produces a ALT_SPIS_DR9_DR9 register field value suitable for setting the register. */
5241 #define ALT_SPIS_DR9_DR9_SET(value) (((value) << 0) & 0xffffffff)
5242 
5243 #ifndef __ASSEMBLY__
5244 /*
5245  * WARNING: The C register and register group struct declarations are provided for
5246  * convenience and illustrative purposes. They should, however, be used with
5247  * caution as the C language standard provides no guarantees about the alignment or
5248  * atomicity of device memory accesses. The recommended practice for coding device
5249  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5250  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5251  * alt_write_dword() functions for 64 bit registers.
5252  *
5253  * The struct declaration for register ALT_SPIS_DR9.
5254  */
5255 struct ALT_SPIS_DR9_s
5256 {
5257  volatile uint32_t dr9 : 32; /* ALT_SPIS_DR9_DR9 */
5258 };
5259 
5260 /* The typedef declaration for register ALT_SPIS_DR9. */
5261 typedef struct ALT_SPIS_DR9_s ALT_SPIS_DR9_t;
5262 #endif /* __ASSEMBLY__ */
5263 
5264 /* The reset value of the ALT_SPIS_DR9 register. */
5265 #define ALT_SPIS_DR9_RESET 0x00000000
5266 /* The byte offset of the ALT_SPIS_DR9 register from the beginning of the component. */
5267 #define ALT_SPIS_DR9_OFST 0x84
5268 /* The address of the ALT_SPIS_DR9 register. */
5269 #define ALT_SPIS_DR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR9_OFST))
5270 
5271 /*
5272  * Register : DW_apb_ssi Data Register - DR10
5273  *
5274  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5275  * read/write buffer for
5276  *
5277  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5278  * set to 32, then all 32 bits
5279  *
5280  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5281  * register is read, data in the
5282  *
5283  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5284  * transmit FIFO buffer; a write
5285  *
5286  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5287  *
5288  * Register Layout
5289  *
5290  * Bits | Access | Reset | Description
5291  * :-------|:-------|:------|:-------------------
5292  * [31:0] | RW | 0x0 | ALT_SPIS_DR10_DR10
5293  *
5294  */
5295 /*
5296  * Field : dr10
5297  *
5298  * Data Register. When writing to this register, you must right-justify the data.
5299  * Read
5300  *
5301  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5302  *
5303  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5304  * of the
5305  *
5306  * register are valid.
5307  *
5308  * Read = Receive FIFO buffer
5309  *
5310  * Write = Transmit FIFO buffer.
5311  *
5312  * Field Access Macros:
5313  *
5314  */
5315 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR10_DR10 register field. */
5316 #define ALT_SPIS_DR10_DR10_LSB 0
5317 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR10_DR10 register field. */
5318 #define ALT_SPIS_DR10_DR10_MSB 31
5319 /* The width in bits of the ALT_SPIS_DR10_DR10 register field. */
5320 #define ALT_SPIS_DR10_DR10_WIDTH 32
5321 /* The mask used to set the ALT_SPIS_DR10_DR10 register field value. */
5322 #define ALT_SPIS_DR10_DR10_SET_MSK 0xffffffff
5323 /* The mask used to clear the ALT_SPIS_DR10_DR10 register field value. */
5324 #define ALT_SPIS_DR10_DR10_CLR_MSK 0x00000000
5325 /* The reset value of the ALT_SPIS_DR10_DR10 register field. */
5326 #define ALT_SPIS_DR10_DR10_RESET 0x0
5327 /* Extracts the ALT_SPIS_DR10_DR10 field value from a register. */
5328 #define ALT_SPIS_DR10_DR10_GET(value) (((value) & 0xffffffff) >> 0)
5329 /* Produces a ALT_SPIS_DR10_DR10 register field value suitable for setting the register. */
5330 #define ALT_SPIS_DR10_DR10_SET(value) (((value) << 0) & 0xffffffff)
5331 
5332 #ifndef __ASSEMBLY__
5333 /*
5334  * WARNING: The C register and register group struct declarations are provided for
5335  * convenience and illustrative purposes. They should, however, be used with
5336  * caution as the C language standard provides no guarantees about the alignment or
5337  * atomicity of device memory accesses. The recommended practice for coding device
5338  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5339  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5340  * alt_write_dword() functions for 64 bit registers.
5341  *
5342  * The struct declaration for register ALT_SPIS_DR10.
5343  */
5344 struct ALT_SPIS_DR10_s
5345 {
5346  volatile uint32_t dr10 : 32; /* ALT_SPIS_DR10_DR10 */
5347 };
5348 
5349 /* The typedef declaration for register ALT_SPIS_DR10. */
5350 typedef struct ALT_SPIS_DR10_s ALT_SPIS_DR10_t;
5351 #endif /* __ASSEMBLY__ */
5352 
5353 /* The reset value of the ALT_SPIS_DR10 register. */
5354 #define ALT_SPIS_DR10_RESET 0x00000000
5355 /* The byte offset of the ALT_SPIS_DR10 register from the beginning of the component. */
5356 #define ALT_SPIS_DR10_OFST 0x88
5357 /* The address of the ALT_SPIS_DR10 register. */
5358 #define ALT_SPIS_DR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR10_OFST))
5359 
5360 /*
5361  * Register : DW_apb_ssi Data Register - DR11
5362  *
5363  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5364  * read/write buffer for
5365  *
5366  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5367  * set to 32, then all 32 bits
5368  *
5369  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5370  * register is read, data in the
5371  *
5372  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5373  * transmit FIFO buffer; a write
5374  *
5375  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5376  *
5377  * Register Layout
5378  *
5379  * Bits | Access | Reset | Description
5380  * :-------|:-------|:------|:-------------------
5381  * [31:0] | RW | 0x0 | ALT_SPIS_DR11_DR11
5382  *
5383  */
5384 /*
5385  * Field : dr11
5386  *
5387  * Data Register. When writing to this register, you must right-justify the data.
5388  * Read
5389  *
5390  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5391  *
5392  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5393  * of the
5394  *
5395  * register are valid.
5396  *
5397  * Read = Receive FIFO buffer
5398  *
5399  * Write = Transmit FIFO buffer.
5400  *
5401  * Field Access Macros:
5402  *
5403  */
5404 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR11_DR11 register field. */
5405 #define ALT_SPIS_DR11_DR11_LSB 0
5406 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR11_DR11 register field. */
5407 #define ALT_SPIS_DR11_DR11_MSB 31
5408 /* The width in bits of the ALT_SPIS_DR11_DR11 register field. */
5409 #define ALT_SPIS_DR11_DR11_WIDTH 32
5410 /* The mask used to set the ALT_SPIS_DR11_DR11 register field value. */
5411 #define ALT_SPIS_DR11_DR11_SET_MSK 0xffffffff
5412 /* The mask used to clear the ALT_SPIS_DR11_DR11 register field value. */
5413 #define ALT_SPIS_DR11_DR11_CLR_MSK 0x00000000
5414 /* The reset value of the ALT_SPIS_DR11_DR11 register field. */
5415 #define ALT_SPIS_DR11_DR11_RESET 0x0
5416 /* Extracts the ALT_SPIS_DR11_DR11 field value from a register. */
5417 #define ALT_SPIS_DR11_DR11_GET(value) (((value) & 0xffffffff) >> 0)
5418 /* Produces a ALT_SPIS_DR11_DR11 register field value suitable for setting the register. */
5419 #define ALT_SPIS_DR11_DR11_SET(value) (((value) << 0) & 0xffffffff)
5420 
5421 #ifndef __ASSEMBLY__
5422 /*
5423  * WARNING: The C register and register group struct declarations are provided for
5424  * convenience and illustrative purposes. They should, however, be used with
5425  * caution as the C language standard provides no guarantees about the alignment or
5426  * atomicity of device memory accesses. The recommended practice for coding device
5427  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5428  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5429  * alt_write_dword() functions for 64 bit registers.
5430  *
5431  * The struct declaration for register ALT_SPIS_DR11.
5432  */
5433 struct ALT_SPIS_DR11_s
5434 {
5435  volatile uint32_t dr11 : 32; /* ALT_SPIS_DR11_DR11 */
5436 };
5437 
5438 /* The typedef declaration for register ALT_SPIS_DR11. */
5439 typedef struct ALT_SPIS_DR11_s ALT_SPIS_DR11_t;
5440 #endif /* __ASSEMBLY__ */
5441 
5442 /* The reset value of the ALT_SPIS_DR11 register. */
5443 #define ALT_SPIS_DR11_RESET 0x00000000
5444 /* The byte offset of the ALT_SPIS_DR11 register from the beginning of the component. */
5445 #define ALT_SPIS_DR11_OFST 0x8c
5446 /* The address of the ALT_SPIS_DR11 register. */
5447 #define ALT_SPIS_DR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR11_OFST))
5448 
5449 /*
5450  * Register : DW_apb_ssi Data Register - DR12
5451  *
5452  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5453  * read/write buffer for
5454  *
5455  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5456  * set to 32, then all 32 bits
5457  *
5458  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5459  * register is read, data in the
5460  *
5461  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5462  * transmit FIFO buffer; a write
5463  *
5464  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5465  *
5466  * Register Layout
5467  *
5468  * Bits | Access | Reset | Description
5469  * :-------|:-------|:------|:-------------------
5470  * [31:0] | RW | 0x0 | ALT_SPIS_DR12_DR12
5471  *
5472  */
5473 /*
5474  * Field : dr12
5475  *
5476  * Data Register. When writing to this register, you must right-justify the data.
5477  * Read
5478  *
5479  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5480  *
5481  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5482  * of the
5483  *
5484  * register are valid.
5485  *
5486  * Read = Receive FIFO buffer
5487  *
5488  * Write = Transmit FIFO buffer.
5489  *
5490  * Field Access Macros:
5491  *
5492  */
5493 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR12_DR12 register field. */
5494 #define ALT_SPIS_DR12_DR12_LSB 0
5495 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR12_DR12 register field. */
5496 #define ALT_SPIS_DR12_DR12_MSB 31
5497 /* The width in bits of the ALT_SPIS_DR12_DR12 register field. */
5498 #define ALT_SPIS_DR12_DR12_WIDTH 32
5499 /* The mask used to set the ALT_SPIS_DR12_DR12 register field value. */
5500 #define ALT_SPIS_DR12_DR12_SET_MSK 0xffffffff
5501 /* The mask used to clear the ALT_SPIS_DR12_DR12 register field value. */
5502 #define ALT_SPIS_DR12_DR12_CLR_MSK 0x00000000
5503 /* The reset value of the ALT_SPIS_DR12_DR12 register field. */
5504 #define ALT_SPIS_DR12_DR12_RESET 0x0
5505 /* Extracts the ALT_SPIS_DR12_DR12 field value from a register. */
5506 #define ALT_SPIS_DR12_DR12_GET(value) (((value) & 0xffffffff) >> 0)
5507 /* Produces a ALT_SPIS_DR12_DR12 register field value suitable for setting the register. */
5508 #define ALT_SPIS_DR12_DR12_SET(value) (((value) << 0) & 0xffffffff)
5509 
5510 #ifndef __ASSEMBLY__
5511 /*
5512  * WARNING: The C register and register group struct declarations are provided for
5513  * convenience and illustrative purposes. They should, however, be used with
5514  * caution as the C language standard provides no guarantees about the alignment or
5515  * atomicity of device memory accesses. The recommended practice for coding device
5516  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5517  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5518  * alt_write_dword() functions for 64 bit registers.
5519  *
5520  * The struct declaration for register ALT_SPIS_DR12.
5521  */
5522 struct ALT_SPIS_DR12_s
5523 {
5524  volatile uint32_t dr12 : 32; /* ALT_SPIS_DR12_DR12 */
5525 };
5526 
5527 /* The typedef declaration for register ALT_SPIS_DR12. */
5528 typedef struct ALT_SPIS_DR12_s ALT_SPIS_DR12_t;
5529 #endif /* __ASSEMBLY__ */
5530 
5531 /* The reset value of the ALT_SPIS_DR12 register. */
5532 #define ALT_SPIS_DR12_RESET 0x00000000
5533 /* The byte offset of the ALT_SPIS_DR12 register from the beginning of the component. */
5534 #define ALT_SPIS_DR12_OFST 0x90
5535 /* The address of the ALT_SPIS_DR12 register. */
5536 #define ALT_SPIS_DR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR12_OFST))
5537 
5538 /*
5539  * Register : DW_apb_ssi Data Register - DR13
5540  *
5541  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5542  * read/write buffer for
5543  *
5544  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5545  * set to 32, then all 32 bits
5546  *
5547  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5548  * register is read, data in the
5549  *
5550  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5551  * transmit FIFO buffer; a write
5552  *
5553  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5554  *
5555  * Register Layout
5556  *
5557  * Bits | Access | Reset | Description
5558  * :-------|:-------|:------|:-------------------
5559  * [31:0] | RW | 0x0 | ALT_SPIS_DR13_DR13
5560  *
5561  */
5562 /*
5563  * Field : dr13
5564  *
5565  * Data Register. When writing to this register, you must right-justify the data.
5566  * Read
5567  *
5568  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5569  *
5570  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5571  * of the
5572  *
5573  * register are valid.
5574  *
5575  * Read = Receive FIFO buffer
5576  *
5577  * Write = Transmit FIFO buffer.
5578  *
5579  * Field Access Macros:
5580  *
5581  */
5582 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR13_DR13 register field. */
5583 #define ALT_SPIS_DR13_DR13_LSB 0
5584 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR13_DR13 register field. */
5585 #define ALT_SPIS_DR13_DR13_MSB 31
5586 /* The width in bits of the ALT_SPIS_DR13_DR13 register field. */
5587 #define ALT_SPIS_DR13_DR13_WIDTH 32
5588 /* The mask used to set the ALT_SPIS_DR13_DR13 register field value. */
5589 #define ALT_SPIS_DR13_DR13_SET_MSK 0xffffffff
5590 /* The mask used to clear the ALT_SPIS_DR13_DR13 register field value. */
5591 #define ALT_SPIS_DR13_DR13_CLR_MSK 0x00000000
5592 /* The reset value of the ALT_SPIS_DR13_DR13 register field. */
5593 #define ALT_SPIS_DR13_DR13_RESET 0x0
5594 /* Extracts the ALT_SPIS_DR13_DR13 field value from a register. */
5595 #define ALT_SPIS_DR13_DR13_GET(value) (((value) & 0xffffffff) >> 0)
5596 /* Produces a ALT_SPIS_DR13_DR13 register field value suitable for setting the register. */
5597 #define ALT_SPIS_DR13_DR13_SET(value) (((value) << 0) & 0xffffffff)
5598 
5599 #ifndef __ASSEMBLY__
5600 /*
5601  * WARNING: The C register and register group struct declarations are provided for
5602  * convenience and illustrative purposes. They should, however, be used with
5603  * caution as the C language standard provides no guarantees about the alignment or
5604  * atomicity of device memory accesses. The recommended practice for coding device
5605  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5606  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5607  * alt_write_dword() functions for 64 bit registers.
5608  *
5609  * The struct declaration for register ALT_SPIS_DR13.
5610  */
5611 struct ALT_SPIS_DR13_s
5612 {
5613  volatile uint32_t dr13 : 32; /* ALT_SPIS_DR13_DR13 */
5614 };
5615 
5616 /* The typedef declaration for register ALT_SPIS_DR13. */
5617 typedef struct ALT_SPIS_DR13_s ALT_SPIS_DR13_t;
5618 #endif /* __ASSEMBLY__ */
5619 
5620 /* The reset value of the ALT_SPIS_DR13 register. */
5621 #define ALT_SPIS_DR13_RESET 0x00000000
5622 /* The byte offset of the ALT_SPIS_DR13 register from the beginning of the component. */
5623 #define ALT_SPIS_DR13_OFST 0x94
5624 /* The address of the ALT_SPIS_DR13 register. */
5625 #define ALT_SPIS_DR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR13_OFST))
5626 
5627 /*
5628  * Register : DW_apb_ssi Data Register - DR14
5629  *
5630  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5631  * read/write buffer for
5632  *
5633  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5634  * set to 32, then all 32 bits
5635  *
5636  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5637  * register is read, data in the
5638  *
5639  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5640  * transmit FIFO buffer; a write
5641  *
5642  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5643  *
5644  * Register Layout
5645  *
5646  * Bits | Access | Reset | Description
5647  * :-------|:-------|:------|:-------------------
5648  * [31:0] | RW | 0x0 | ALT_SPIS_DR14_DR14
5649  *
5650  */
5651 /*
5652  * Field : dr14
5653  *
5654  * Data Register. When writing to this register, you must right-justify the data.
5655  * Read
5656  *
5657  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5658  *
5659  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5660  * of the
5661  *
5662  * register are valid.
5663  *
5664  * Read = Receive FIFO buffer
5665  *
5666  * Write = Transmit FIFO buffer.
5667  *
5668  * Field Access Macros:
5669  *
5670  */
5671 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR14_DR14 register field. */
5672 #define ALT_SPIS_DR14_DR14_LSB 0
5673 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR14_DR14 register field. */
5674 #define ALT_SPIS_DR14_DR14_MSB 31
5675 /* The width in bits of the ALT_SPIS_DR14_DR14 register field. */
5676 #define ALT_SPIS_DR14_DR14_WIDTH 32
5677 /* The mask used to set the ALT_SPIS_DR14_DR14 register field value. */
5678 #define ALT_SPIS_DR14_DR14_SET_MSK 0xffffffff
5679 /* The mask used to clear the ALT_SPIS_DR14_DR14 register field value. */
5680 #define ALT_SPIS_DR14_DR14_CLR_MSK 0x00000000
5681 /* The reset value of the ALT_SPIS_DR14_DR14 register field. */
5682 #define ALT_SPIS_DR14_DR14_RESET 0x0
5683 /* Extracts the ALT_SPIS_DR14_DR14 field value from a register. */
5684 #define ALT_SPIS_DR14_DR14_GET(value) (((value) & 0xffffffff) >> 0)
5685 /* Produces a ALT_SPIS_DR14_DR14 register field value suitable for setting the register. */
5686 #define ALT_SPIS_DR14_DR14_SET(value) (((value) << 0) & 0xffffffff)
5687 
5688 #ifndef __ASSEMBLY__
5689 /*
5690  * WARNING: The C register and register group struct declarations are provided for
5691  * convenience and illustrative purposes. They should, however, be used with
5692  * caution as the C language standard provides no guarantees about the alignment or
5693  * atomicity of device memory accesses. The recommended practice for coding device
5694  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5695  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5696  * alt_write_dword() functions for 64 bit registers.
5697  *
5698  * The struct declaration for register ALT_SPIS_DR14.
5699  */
5700 struct ALT_SPIS_DR14_s
5701 {
5702  volatile uint32_t dr14 : 32; /* ALT_SPIS_DR14_DR14 */
5703 };
5704 
5705 /* The typedef declaration for register ALT_SPIS_DR14. */
5706 typedef struct ALT_SPIS_DR14_s ALT_SPIS_DR14_t;
5707 #endif /* __ASSEMBLY__ */
5708 
5709 /* The reset value of the ALT_SPIS_DR14 register. */
5710 #define ALT_SPIS_DR14_RESET 0x00000000
5711 /* The byte offset of the ALT_SPIS_DR14 register from the beginning of the component. */
5712 #define ALT_SPIS_DR14_OFST 0x98
5713 /* The address of the ALT_SPIS_DR14 register. */
5714 #define ALT_SPIS_DR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR14_OFST))
5715 
5716 /*
5717  * Register : DW_apb_ssi Data Register - DR15
5718  *
5719  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5720  * read/write buffer for
5721  *
5722  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5723  * set to 32, then all 32 bits
5724  *
5725  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5726  * register is read, data in the
5727  *
5728  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5729  * transmit FIFO buffer; a write
5730  *
5731  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5732  *
5733  * Register Layout
5734  *
5735  * Bits | Access | Reset | Description
5736  * :-------|:-------|:------|:-------------------
5737  * [31:0] | RW | 0x0 | ALT_SPIS_DR15_DR15
5738  *
5739  */
5740 /*
5741  * Field : dr15
5742  *
5743  * Data Register. When writing to this register, you must right-justify the data.
5744  * Read
5745  *
5746  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5747  *
5748  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5749  * of the
5750  *
5751  * register are valid.
5752  *
5753  * Read = Receive FIFO buffer
5754  *
5755  * Write = Transmit FIFO buffer.
5756  *
5757  * Field Access Macros:
5758  *
5759  */
5760 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR15_DR15 register field. */
5761 #define ALT_SPIS_DR15_DR15_LSB 0
5762 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR15_DR15 register field. */
5763 #define ALT_SPIS_DR15_DR15_MSB 31
5764 /* The width in bits of the ALT_SPIS_DR15_DR15 register field. */
5765 #define ALT_SPIS_DR15_DR15_WIDTH 32
5766 /* The mask used to set the ALT_SPIS_DR15_DR15 register field value. */
5767 #define ALT_SPIS_DR15_DR15_SET_MSK 0xffffffff
5768 /* The mask used to clear the ALT_SPIS_DR15_DR15 register field value. */
5769 #define ALT_SPIS_DR15_DR15_CLR_MSK 0x00000000
5770 /* The reset value of the ALT_SPIS_DR15_DR15 register field. */
5771 #define ALT_SPIS_DR15_DR15_RESET 0x0
5772 /* Extracts the ALT_SPIS_DR15_DR15 field value from a register. */
5773 #define ALT_SPIS_DR15_DR15_GET(value) (((value) & 0xffffffff) >> 0)
5774 /* Produces a ALT_SPIS_DR15_DR15 register field value suitable for setting the register. */
5775 #define ALT_SPIS_DR15_DR15_SET(value) (((value) << 0) & 0xffffffff)
5776 
5777 #ifndef __ASSEMBLY__
5778 /*
5779  * WARNING: The C register and register group struct declarations are provided for
5780  * convenience and illustrative purposes. They should, however, be used with
5781  * caution as the C language standard provides no guarantees about the alignment or
5782  * atomicity of device memory accesses. The recommended practice for coding device
5783  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5784  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5785  * alt_write_dword() functions for 64 bit registers.
5786  *
5787  * The struct declaration for register ALT_SPIS_DR15.
5788  */
5789 struct ALT_SPIS_DR15_s
5790 {
5791  volatile uint32_t dr15 : 32; /* ALT_SPIS_DR15_DR15 */
5792 };
5793 
5794 /* The typedef declaration for register ALT_SPIS_DR15. */
5795 typedef struct ALT_SPIS_DR15_s ALT_SPIS_DR15_t;
5796 #endif /* __ASSEMBLY__ */
5797 
5798 /* The reset value of the ALT_SPIS_DR15 register. */
5799 #define ALT_SPIS_DR15_RESET 0x00000000
5800 /* The byte offset of the ALT_SPIS_DR15 register from the beginning of the component. */
5801 #define ALT_SPIS_DR15_OFST 0x9c
5802 /* The address of the ALT_SPIS_DR15 register. */
5803 #define ALT_SPIS_DR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR15_OFST))
5804 
5805 /*
5806  * Register : DW_apb_ssi Data Register - DR16
5807  *
5808  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5809  * read/write buffer for
5810  *
5811  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5812  * set to 32, then all 32 bits
5813  *
5814  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5815  * register is read, data in the
5816  *
5817  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5818  * transmit FIFO buffer; a write
5819  *
5820  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5821  *
5822  * Register Layout
5823  *
5824  * Bits | Access | Reset | Description
5825  * :-------|:-------|:------|:-------------------
5826  * [31:0] | RW | 0x0 | ALT_SPIS_DR16_DR16
5827  *
5828  */
5829 /*
5830  * Field : dr16
5831  *
5832  * Data Register. When writing to this register, you must right-justify the data.
5833  * Read
5834  *
5835  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5836  *
5837  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5838  * of the
5839  *
5840  * register are valid.
5841  *
5842  * Read = Receive FIFO buffer
5843  *
5844  * Write = Transmit FIFO buffer.
5845  *
5846  * Field Access Macros:
5847  *
5848  */
5849 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR16_DR16 register field. */
5850 #define ALT_SPIS_DR16_DR16_LSB 0
5851 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR16_DR16 register field. */
5852 #define ALT_SPIS_DR16_DR16_MSB 31
5853 /* The width in bits of the ALT_SPIS_DR16_DR16 register field. */
5854 #define ALT_SPIS_DR16_DR16_WIDTH 32
5855 /* The mask used to set the ALT_SPIS_DR16_DR16 register field value. */
5856 #define ALT_SPIS_DR16_DR16_SET_MSK 0xffffffff
5857 /* The mask used to clear the ALT_SPIS_DR16_DR16 register field value. */
5858 #define ALT_SPIS_DR16_DR16_CLR_MSK 0x00000000
5859 /* The reset value of the ALT_SPIS_DR16_DR16 register field. */
5860 #define ALT_SPIS_DR16_DR16_RESET 0x0
5861 /* Extracts the ALT_SPIS_DR16_DR16 field value from a register. */
5862 #define ALT_SPIS_DR16_DR16_GET(value) (((value) & 0xffffffff) >> 0)
5863 /* Produces a ALT_SPIS_DR16_DR16 register field value suitable for setting the register. */
5864 #define ALT_SPIS_DR16_DR16_SET(value) (((value) << 0) & 0xffffffff)
5865 
5866 #ifndef __ASSEMBLY__
5867 /*
5868  * WARNING: The C register and register group struct declarations are provided for
5869  * convenience and illustrative purposes. They should, however, be used with
5870  * caution as the C language standard provides no guarantees about the alignment or
5871  * atomicity of device memory accesses. The recommended practice for coding device
5872  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5873  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5874  * alt_write_dword() functions for 64 bit registers.
5875  *
5876  * The struct declaration for register ALT_SPIS_DR16.
5877  */
5878 struct ALT_SPIS_DR16_s
5879 {
5880  volatile uint32_t dr16 : 32; /* ALT_SPIS_DR16_DR16 */
5881 };
5882 
5883 /* The typedef declaration for register ALT_SPIS_DR16. */
5884 typedef struct ALT_SPIS_DR16_s ALT_SPIS_DR16_t;
5885 #endif /* __ASSEMBLY__ */
5886 
5887 /* The reset value of the ALT_SPIS_DR16 register. */
5888 #define ALT_SPIS_DR16_RESET 0x00000000
5889 /* The byte offset of the ALT_SPIS_DR16 register from the beginning of the component. */
5890 #define ALT_SPIS_DR16_OFST 0xa0
5891 /* The address of the ALT_SPIS_DR16 register. */
5892 #define ALT_SPIS_DR16_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR16_OFST))
5893 
5894 /*
5895  * Register : DW_apb_ssi Data Register - DR17
5896  *
5897  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5898  * read/write buffer for
5899  *
5900  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5901  * set to 32, then all 32 bits
5902  *
5903  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5904  * register is read, data in the
5905  *
5906  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5907  * transmit FIFO buffer; a write
5908  *
5909  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5910  *
5911  * Register Layout
5912  *
5913  * Bits | Access | Reset | Description
5914  * :-------|:-------|:------|:-------------------
5915  * [31:0] | RW | 0x0 | ALT_SPIS_DR17_DR17
5916  *
5917  */
5918 /*
5919  * Field : dr17
5920  *
5921  * Data Register. When writing to this register, you must right-justify the data.
5922  * Read
5923  *
5924  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5925  *
5926  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5927  * of the
5928  *
5929  * register are valid.
5930  *
5931  * Read = Receive FIFO buffer
5932  *
5933  * Write = Transmit FIFO buffer.
5934  *
5935  * Field Access Macros:
5936  *
5937  */
5938 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR17_DR17 register field. */
5939 #define ALT_SPIS_DR17_DR17_LSB 0
5940 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR17_DR17 register field. */
5941 #define ALT_SPIS_DR17_DR17_MSB 31
5942 /* The width in bits of the ALT_SPIS_DR17_DR17 register field. */
5943 #define ALT_SPIS_DR17_DR17_WIDTH 32
5944 /* The mask used to set the ALT_SPIS_DR17_DR17 register field value. */
5945 #define ALT_SPIS_DR17_DR17_SET_MSK 0xffffffff
5946 /* The mask used to clear the ALT_SPIS_DR17_DR17 register field value. */
5947 #define ALT_SPIS_DR17_DR17_CLR_MSK 0x00000000
5948 /* The reset value of the ALT_SPIS_DR17_DR17 register field. */
5949 #define ALT_SPIS_DR17_DR17_RESET 0x0
5950 /* Extracts the ALT_SPIS_DR17_DR17 field value from a register. */
5951 #define ALT_SPIS_DR17_DR17_GET(value) (((value) & 0xffffffff) >> 0)
5952 /* Produces a ALT_SPIS_DR17_DR17 register field value suitable for setting the register. */
5953 #define ALT_SPIS_DR17_DR17_SET(value) (((value) << 0) & 0xffffffff)
5954 
5955 #ifndef __ASSEMBLY__
5956 /*
5957  * WARNING: The C register and register group struct declarations are provided for
5958  * convenience and illustrative purposes. They should, however, be used with
5959  * caution as the C language standard provides no guarantees about the alignment or
5960  * atomicity of device memory accesses. The recommended practice for coding device
5961  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5962  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5963  * alt_write_dword() functions for 64 bit registers.
5964  *
5965  * The struct declaration for register ALT_SPIS_DR17.
5966  */
5967 struct ALT_SPIS_DR17_s
5968 {
5969  volatile uint32_t dr17 : 32; /* ALT_SPIS_DR17_DR17 */
5970 };
5971 
5972 /* The typedef declaration for register ALT_SPIS_DR17. */
5973 typedef struct ALT_SPIS_DR17_s ALT_SPIS_DR17_t;
5974 #endif /* __ASSEMBLY__ */
5975 
5976 /* The reset value of the ALT_SPIS_DR17 register. */
5977 #define ALT_SPIS_DR17_RESET 0x00000000
5978 /* The byte offset of the ALT_SPIS_DR17 register from the beginning of the component. */
5979 #define ALT_SPIS_DR17_OFST 0xa4
5980 /* The address of the ALT_SPIS_DR17 register. */
5981 #define ALT_SPIS_DR17_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR17_OFST))
5982 
5983 /*
5984  * Register : DW_apb_ssi Data Register - DR18
5985  *
5986  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5987  * read/write buffer for
5988  *
5989  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5990  * set to 32, then all 32 bits
5991  *
5992  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5993  * register is read, data in the
5994  *
5995  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5996  * transmit FIFO buffer; a write
5997  *
5998  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5999  *
6000  * Register Layout
6001  *
6002  * Bits | Access | Reset | Description
6003  * :-------|:-------|:------|:-------------------
6004  * [31:0] | RW | 0x0 | ALT_SPIS_DR18_DR18
6005  *
6006  */
6007 /*
6008  * Field : dr18
6009  *
6010  * Data Register. When writing to this register, you must right-justify the data.
6011  * Read
6012  *
6013  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6014  *
6015  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6016  * of the
6017  *
6018  * register are valid.
6019  *
6020  * Read = Receive FIFO buffer
6021  *
6022  * Write = Transmit FIFO buffer.
6023  *
6024  * Field Access Macros:
6025  *
6026  */
6027 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR18_DR18 register field. */
6028 #define ALT_SPIS_DR18_DR18_LSB 0
6029 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR18_DR18 register field. */
6030 #define ALT_SPIS_DR18_DR18_MSB 31
6031 /* The width in bits of the ALT_SPIS_DR18_DR18 register field. */
6032 #define ALT_SPIS_DR18_DR18_WIDTH 32
6033 /* The mask used to set the ALT_SPIS_DR18_DR18 register field value. */
6034 #define ALT_SPIS_DR18_DR18_SET_MSK 0xffffffff
6035 /* The mask used to clear the ALT_SPIS_DR18_DR18 register field value. */
6036 #define ALT_SPIS_DR18_DR18_CLR_MSK 0x00000000
6037 /* The reset value of the ALT_SPIS_DR18_DR18 register field. */
6038 #define ALT_SPIS_DR18_DR18_RESET 0x0
6039 /* Extracts the ALT_SPIS_DR18_DR18 field value from a register. */
6040 #define ALT_SPIS_DR18_DR18_GET(value) (((value) & 0xffffffff) >> 0)
6041 /* Produces a ALT_SPIS_DR18_DR18 register field value suitable for setting the register. */
6042 #define ALT_SPIS_DR18_DR18_SET(value) (((value) << 0) & 0xffffffff)
6043 
6044 #ifndef __ASSEMBLY__
6045 /*
6046  * WARNING: The C register and register group struct declarations are provided for
6047  * convenience and illustrative purposes. They should, however, be used with
6048  * caution as the C language standard provides no guarantees about the alignment or
6049  * atomicity of device memory accesses. The recommended practice for coding device
6050  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6051  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6052  * alt_write_dword() functions for 64 bit registers.
6053  *
6054  * The struct declaration for register ALT_SPIS_DR18.
6055  */
6056 struct ALT_SPIS_DR18_s
6057 {
6058  volatile uint32_t dr18 : 32; /* ALT_SPIS_DR18_DR18 */
6059 };
6060 
6061 /* The typedef declaration for register ALT_SPIS_DR18. */
6062 typedef struct ALT_SPIS_DR18_s ALT_SPIS_DR18_t;
6063 #endif /* __ASSEMBLY__ */
6064 
6065 /* The reset value of the ALT_SPIS_DR18 register. */
6066 #define ALT_SPIS_DR18_RESET 0x00000000
6067 /* The byte offset of the ALT_SPIS_DR18 register from the beginning of the component. */
6068 #define ALT_SPIS_DR18_OFST 0xa8
6069 /* The address of the ALT_SPIS_DR18 register. */
6070 #define ALT_SPIS_DR18_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR18_OFST))
6071 
6072 /*
6073  * Register : DW_apb_ssi Data Register - DR19
6074  *
6075  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6076  * read/write buffer for
6077  *
6078  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6079  * set to 32, then all 32 bits
6080  *
6081  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6082  * register is read, data in the
6083  *
6084  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6085  * transmit FIFO buffer; a write
6086  *
6087  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6088  *
6089  * Register Layout
6090  *
6091  * Bits | Access | Reset | Description
6092  * :-------|:-------|:------|:-------------------
6093  * [31:0] | RW | 0x0 | ALT_SPIS_DR19_DR19
6094  *
6095  */
6096 /*
6097  * Field : dr19
6098  *
6099  * Data Register. When writing to this register, you must right-justify the data.
6100  * Read
6101  *
6102  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6103  *
6104  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6105  * of the
6106  *
6107  * register are valid.
6108  *
6109  * Read = Receive FIFO buffer
6110  *
6111  * Write = Transmit FIFO buffer.
6112  *
6113  * Field Access Macros:
6114  *
6115  */
6116 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR19_DR19 register field. */
6117 #define ALT_SPIS_DR19_DR19_LSB 0
6118 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR19_DR19 register field. */
6119 #define ALT_SPIS_DR19_DR19_MSB 31
6120 /* The width in bits of the ALT_SPIS_DR19_DR19 register field. */
6121 #define ALT_SPIS_DR19_DR19_WIDTH 32
6122 /* The mask used to set the ALT_SPIS_DR19_DR19 register field value. */
6123 #define ALT_SPIS_DR19_DR19_SET_MSK 0xffffffff
6124 /* The mask used to clear the ALT_SPIS_DR19_DR19 register field value. */
6125 #define ALT_SPIS_DR19_DR19_CLR_MSK 0x00000000
6126 /* The reset value of the ALT_SPIS_DR19_DR19 register field. */
6127 #define ALT_SPIS_DR19_DR19_RESET 0x0
6128 /* Extracts the ALT_SPIS_DR19_DR19 field value from a register. */
6129 #define ALT_SPIS_DR19_DR19_GET(value) (((value) & 0xffffffff) >> 0)
6130 /* Produces a ALT_SPIS_DR19_DR19 register field value suitable for setting the register. */
6131 #define ALT_SPIS_DR19_DR19_SET(value) (((value) << 0) & 0xffffffff)
6132 
6133 #ifndef __ASSEMBLY__
6134 /*
6135  * WARNING: The C register and register group struct declarations are provided for
6136  * convenience and illustrative purposes. They should, however, be used with
6137  * caution as the C language standard provides no guarantees about the alignment or
6138  * atomicity of device memory accesses. The recommended practice for coding device
6139  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6140  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6141  * alt_write_dword() functions for 64 bit registers.
6142  *
6143  * The struct declaration for register ALT_SPIS_DR19.
6144  */
6145 struct ALT_SPIS_DR19_s
6146 {
6147  volatile uint32_t dr19 : 32; /* ALT_SPIS_DR19_DR19 */
6148 };
6149 
6150 /* The typedef declaration for register ALT_SPIS_DR19. */
6151 typedef struct ALT_SPIS_DR19_s ALT_SPIS_DR19_t;
6152 #endif /* __ASSEMBLY__ */
6153 
6154 /* The reset value of the ALT_SPIS_DR19 register. */
6155 #define ALT_SPIS_DR19_RESET 0x00000000
6156 /* The byte offset of the ALT_SPIS_DR19 register from the beginning of the component. */
6157 #define ALT_SPIS_DR19_OFST 0xac
6158 /* The address of the ALT_SPIS_DR19 register. */
6159 #define ALT_SPIS_DR19_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR19_OFST))
6160 
6161 /*
6162  * Register : DW_apb_ssi Data Register - DR20
6163  *
6164  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6165  * read/write buffer for
6166  *
6167  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6168  * set to 32, then all 32 bits
6169  *
6170  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6171  * register is read, data in the
6172  *
6173  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6174  * transmit FIFO buffer; a write
6175  *
6176  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6177  *
6178  * Register Layout
6179  *
6180  * Bits | Access | Reset | Description
6181  * :-------|:-------|:------|:-------------------
6182  * [31:0] | RW | 0x0 | ALT_SPIS_DR20_DR20
6183  *
6184  */
6185 /*
6186  * Field : dr20
6187  *
6188  * Data Register. When writing to this register, you must right-justify the data.
6189  * Read
6190  *
6191  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6192  *
6193  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6194  * of the
6195  *
6196  * register are valid.
6197  *
6198  * Read = Receive FIFO buffer
6199  *
6200  * Write = Transmit FIFO buffer.
6201  *
6202  * Field Access Macros:
6203  *
6204  */
6205 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR20_DR20 register field. */
6206 #define ALT_SPIS_DR20_DR20_LSB 0
6207 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR20_DR20 register field. */
6208 #define ALT_SPIS_DR20_DR20_MSB 31
6209 /* The width in bits of the ALT_SPIS_DR20_DR20 register field. */
6210 #define ALT_SPIS_DR20_DR20_WIDTH 32
6211 /* The mask used to set the ALT_SPIS_DR20_DR20 register field value. */
6212 #define ALT_SPIS_DR20_DR20_SET_MSK 0xffffffff
6213 /* The mask used to clear the ALT_SPIS_DR20_DR20 register field value. */
6214 #define ALT_SPIS_DR20_DR20_CLR_MSK 0x00000000
6215 /* The reset value of the ALT_SPIS_DR20_DR20 register field. */
6216 #define ALT_SPIS_DR20_DR20_RESET 0x0
6217 /* Extracts the ALT_SPIS_DR20_DR20 field value from a register. */
6218 #define ALT_SPIS_DR20_DR20_GET(value) (((value) & 0xffffffff) >> 0)
6219 /* Produces a ALT_SPIS_DR20_DR20 register field value suitable for setting the register. */
6220 #define ALT_SPIS_DR20_DR20_SET(value) (((value) << 0) & 0xffffffff)
6221 
6222 #ifndef __ASSEMBLY__
6223 /*
6224  * WARNING: The C register and register group struct declarations are provided for
6225  * convenience and illustrative purposes. They should, however, be used with
6226  * caution as the C language standard provides no guarantees about the alignment or
6227  * atomicity of device memory accesses. The recommended practice for coding device
6228  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6229  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6230  * alt_write_dword() functions for 64 bit registers.
6231  *
6232  * The struct declaration for register ALT_SPIS_DR20.
6233  */
6234 struct ALT_SPIS_DR20_s
6235 {
6236  volatile uint32_t dr20 : 32; /* ALT_SPIS_DR20_DR20 */
6237 };
6238 
6239 /* The typedef declaration for register ALT_SPIS_DR20. */
6240 typedef struct ALT_SPIS_DR20_s ALT_SPIS_DR20_t;
6241 #endif /* __ASSEMBLY__ */
6242 
6243 /* The reset value of the ALT_SPIS_DR20 register. */
6244 #define ALT_SPIS_DR20_RESET 0x00000000
6245 /* The byte offset of the ALT_SPIS_DR20 register from the beginning of the component. */
6246 #define ALT_SPIS_DR20_OFST 0xb0
6247 /* The address of the ALT_SPIS_DR20 register. */
6248 #define ALT_SPIS_DR20_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR20_OFST))
6249 
6250 /*
6251  * Register : DW_apb_ssi Data Register - DR21
6252  *
6253  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6254  * read/write buffer for
6255  *
6256  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6257  * set to 32, then all 32 bits
6258  *
6259  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6260  * register is read, data in the
6261  *
6262  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6263  * transmit FIFO buffer; a write
6264  *
6265  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6266  *
6267  * Register Layout
6268  *
6269  * Bits | Access | Reset | Description
6270  * :-------|:-------|:------|:-------------------
6271  * [31:0] | RW | 0x0 | ALT_SPIS_DR21_DR21
6272  *
6273  */
6274 /*
6275  * Field : dr21
6276  *
6277  * Data Register. When writing to this register, you must right-justify the data.
6278  * Read
6279  *
6280  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6281  *
6282  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6283  * of the
6284  *
6285  * register are valid.
6286  *
6287  * Read = Receive FIFO buffer
6288  *
6289  * Write = Transmit FIFO buffer.
6290  *
6291  * Field Access Macros:
6292  *
6293  */
6294 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR21_DR21 register field. */
6295 #define ALT_SPIS_DR21_DR21_LSB 0
6296 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR21_DR21 register field. */
6297 #define ALT_SPIS_DR21_DR21_MSB 31
6298 /* The width in bits of the ALT_SPIS_DR21_DR21 register field. */
6299 #define ALT_SPIS_DR21_DR21_WIDTH 32
6300 /* The mask used to set the ALT_SPIS_DR21_DR21 register field value. */
6301 #define ALT_SPIS_DR21_DR21_SET_MSK 0xffffffff
6302 /* The mask used to clear the ALT_SPIS_DR21_DR21 register field value. */
6303 #define ALT_SPIS_DR21_DR21_CLR_MSK 0x00000000
6304 /* The reset value of the ALT_SPIS_DR21_DR21 register field. */
6305 #define ALT_SPIS_DR21_DR21_RESET 0x0
6306 /* Extracts the ALT_SPIS_DR21_DR21 field value from a register. */
6307 #define ALT_SPIS_DR21_DR21_GET(value) (((value) & 0xffffffff) >> 0)
6308 /* Produces a ALT_SPIS_DR21_DR21 register field value suitable for setting the register. */
6309 #define ALT_SPIS_DR21_DR21_SET(value) (((value) << 0) & 0xffffffff)
6310 
6311 #ifndef __ASSEMBLY__
6312 /*
6313  * WARNING: The C register and register group struct declarations are provided for
6314  * convenience and illustrative purposes. They should, however, be used with
6315  * caution as the C language standard provides no guarantees about the alignment or
6316  * atomicity of device memory accesses. The recommended practice for coding device
6317  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6318  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6319  * alt_write_dword() functions for 64 bit registers.
6320  *
6321  * The struct declaration for register ALT_SPIS_DR21.
6322  */
6323 struct ALT_SPIS_DR21_s
6324 {
6325  volatile uint32_t dr21 : 32; /* ALT_SPIS_DR21_DR21 */
6326 };
6327 
6328 /* The typedef declaration for register ALT_SPIS_DR21. */
6329 typedef struct ALT_SPIS_DR21_s ALT_SPIS_DR21_t;
6330 #endif /* __ASSEMBLY__ */
6331 
6332 /* The reset value of the ALT_SPIS_DR21 register. */
6333 #define ALT_SPIS_DR21_RESET 0x00000000
6334 /* The byte offset of the ALT_SPIS_DR21 register from the beginning of the component. */
6335 #define ALT_SPIS_DR21_OFST 0xb4
6336 /* The address of the ALT_SPIS_DR21 register. */
6337 #define ALT_SPIS_DR21_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR21_OFST))
6338 
6339 /*
6340  * Register : DW_apb_ssi Data Register - DR22
6341  *
6342  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6343  * read/write buffer for
6344  *
6345  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6346  * set to 32, then all 32 bits
6347  *
6348  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6349  * register is read, data in the
6350  *
6351  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6352  * transmit FIFO buffer; a write
6353  *
6354  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6355  *
6356  * Register Layout
6357  *
6358  * Bits | Access | Reset | Description
6359  * :-------|:-------|:------|:-------------------
6360  * [31:0] | RW | 0x0 | ALT_SPIS_DR22_DR22
6361  *
6362  */
6363 /*
6364  * Field : dr22
6365  *
6366  * Data Register. When writing to this register, you must right-justify the data.
6367  * Read
6368  *
6369  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6370  *
6371  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6372  * of the
6373  *
6374  * register are valid.
6375  *
6376  * Read = Receive FIFO buffer
6377  *
6378  * Write = Transmit FIFO buffer.
6379  *
6380  * Field Access Macros:
6381  *
6382  */
6383 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR22_DR22 register field. */
6384 #define ALT_SPIS_DR22_DR22_LSB 0
6385 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR22_DR22 register field. */
6386 #define ALT_SPIS_DR22_DR22_MSB 31
6387 /* The width in bits of the ALT_SPIS_DR22_DR22 register field. */
6388 #define ALT_SPIS_DR22_DR22_WIDTH 32
6389 /* The mask used to set the ALT_SPIS_DR22_DR22 register field value. */
6390 #define ALT_SPIS_DR22_DR22_SET_MSK 0xffffffff
6391 /* The mask used to clear the ALT_SPIS_DR22_DR22 register field value. */
6392 #define ALT_SPIS_DR22_DR22_CLR_MSK 0x00000000
6393 /* The reset value of the ALT_SPIS_DR22_DR22 register field. */
6394 #define ALT_SPIS_DR22_DR22_RESET 0x0
6395 /* Extracts the ALT_SPIS_DR22_DR22 field value from a register. */
6396 #define ALT_SPIS_DR22_DR22_GET(value) (((value) & 0xffffffff) >> 0)
6397 /* Produces a ALT_SPIS_DR22_DR22 register field value suitable for setting the register. */
6398 #define ALT_SPIS_DR22_DR22_SET(value) (((value) << 0) & 0xffffffff)
6399 
6400 #ifndef __ASSEMBLY__
6401 /*
6402  * WARNING: The C register and register group struct declarations are provided for
6403  * convenience and illustrative purposes. They should, however, be used with
6404  * caution as the C language standard provides no guarantees about the alignment or
6405  * atomicity of device memory accesses. The recommended practice for coding device
6406  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6407  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6408  * alt_write_dword() functions for 64 bit registers.
6409  *
6410  * The struct declaration for register ALT_SPIS_DR22.
6411  */
6412 struct ALT_SPIS_DR22_s
6413 {
6414  volatile uint32_t dr22 : 32; /* ALT_SPIS_DR22_DR22 */
6415 };
6416 
6417 /* The typedef declaration for register ALT_SPIS_DR22. */
6418 typedef struct ALT_SPIS_DR22_s ALT_SPIS_DR22_t;
6419 #endif /* __ASSEMBLY__ */
6420 
6421 /* The reset value of the ALT_SPIS_DR22 register. */
6422 #define ALT_SPIS_DR22_RESET 0x00000000
6423 /* The byte offset of the ALT_SPIS_DR22 register from the beginning of the component. */
6424 #define ALT_SPIS_DR22_OFST 0xb8
6425 /* The address of the ALT_SPIS_DR22 register. */
6426 #define ALT_SPIS_DR22_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR22_OFST))
6427 
6428 /*
6429  * Register : DW_apb_ssi Data Register - DR23
6430  *
6431  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6432  * read/write buffer for
6433  *
6434  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6435  * set to 32, then all 32 bits
6436  *
6437  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6438  * register is read, data in the
6439  *
6440  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6441  * transmit FIFO buffer; a write
6442  *
6443  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6444  *
6445  * Register Layout
6446  *
6447  * Bits | Access | Reset | Description
6448  * :-------|:-------|:------|:-------------------
6449  * [31:0] | RW | 0x0 | ALT_SPIS_DR23_DR23
6450  *
6451  */
6452 /*
6453  * Field : dr23
6454  *
6455  * Data Register. When writing to this register, you must right-justify the data.
6456  * Read
6457  *
6458  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6459  *
6460  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6461  * of the
6462  *
6463  * register are valid.
6464  *
6465  * Read = Receive FIFO buffer
6466  *
6467  * Write = Transmit FIFO buffer.
6468  *
6469  * Field Access Macros:
6470  *
6471  */
6472 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR23_DR23 register field. */
6473 #define ALT_SPIS_DR23_DR23_LSB 0
6474 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR23_DR23 register field. */
6475 #define ALT_SPIS_DR23_DR23_MSB 31
6476 /* The width in bits of the ALT_SPIS_DR23_DR23 register field. */
6477 #define ALT_SPIS_DR23_DR23_WIDTH 32
6478 /* The mask used to set the ALT_SPIS_DR23_DR23 register field value. */
6479 #define ALT_SPIS_DR23_DR23_SET_MSK 0xffffffff
6480 /* The mask used to clear the ALT_SPIS_DR23_DR23 register field value. */
6481 #define ALT_SPIS_DR23_DR23_CLR_MSK 0x00000000
6482 /* The reset value of the ALT_SPIS_DR23_DR23 register field. */
6483 #define ALT_SPIS_DR23_DR23_RESET 0x0
6484 /* Extracts the ALT_SPIS_DR23_DR23 field value from a register. */
6485 #define ALT_SPIS_DR23_DR23_GET(value) (((value) & 0xffffffff) >> 0)
6486 /* Produces a ALT_SPIS_DR23_DR23 register field value suitable for setting the register. */
6487 #define ALT_SPIS_DR23_DR23_SET(value) (((value) << 0) & 0xffffffff)
6488 
6489 #ifndef __ASSEMBLY__
6490 /*
6491  * WARNING: The C register and register group struct declarations are provided for
6492  * convenience and illustrative purposes. They should, however, be used with
6493  * caution as the C language standard provides no guarantees about the alignment or
6494  * atomicity of device memory accesses. The recommended practice for coding device
6495  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6496  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6497  * alt_write_dword() functions for 64 bit registers.
6498  *
6499  * The struct declaration for register ALT_SPIS_DR23.
6500  */
6501 struct ALT_SPIS_DR23_s
6502 {
6503  volatile uint32_t dr23 : 32; /* ALT_SPIS_DR23_DR23 */
6504 };
6505 
6506 /* The typedef declaration for register ALT_SPIS_DR23. */
6507 typedef struct ALT_SPIS_DR23_s ALT_SPIS_DR23_t;
6508 #endif /* __ASSEMBLY__ */
6509 
6510 /* The reset value of the ALT_SPIS_DR23 register. */
6511 #define ALT_SPIS_DR23_RESET 0x00000000
6512 /* The byte offset of the ALT_SPIS_DR23 register from the beginning of the component. */
6513 #define ALT_SPIS_DR23_OFST 0xbc
6514 /* The address of the ALT_SPIS_DR23 register. */
6515 #define ALT_SPIS_DR23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR23_OFST))
6516 
6517 /*
6518  * Register : DW_apb_ssi Data Register - DR24
6519  *
6520  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6521  * read/write buffer for
6522  *
6523  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6524  * set to 32, then all 32 bits
6525  *
6526  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6527  * register is read, data in the
6528  *
6529  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6530  * transmit FIFO buffer; a write
6531  *
6532  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6533  *
6534  * Register Layout
6535  *
6536  * Bits | Access | Reset | Description
6537  * :-------|:-------|:------|:-------------------
6538  * [31:0] | RW | 0x0 | ALT_SPIS_DR24_DR24
6539  *
6540  */
6541 /*
6542  * Field : dr24
6543  *
6544  * Data Register. When writing to this register, you must right-justify the data.
6545  * Read
6546  *
6547  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6548  *
6549  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6550  * of the
6551  *
6552  * register are valid.
6553  *
6554  * Read = Receive FIFO buffer
6555  *
6556  * Write = Transmit FIFO buffer.
6557  *
6558  * Field Access Macros:
6559  *
6560  */
6561 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR24_DR24 register field. */
6562 #define ALT_SPIS_DR24_DR24_LSB 0
6563 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR24_DR24 register field. */
6564 #define ALT_SPIS_DR24_DR24_MSB 31
6565 /* The width in bits of the ALT_SPIS_DR24_DR24 register field. */
6566 #define ALT_SPIS_DR24_DR24_WIDTH 32
6567 /* The mask used to set the ALT_SPIS_DR24_DR24 register field value. */
6568 #define ALT_SPIS_DR24_DR24_SET_MSK 0xffffffff
6569 /* The mask used to clear the ALT_SPIS_DR24_DR24 register field value. */
6570 #define ALT_SPIS_DR24_DR24_CLR_MSK 0x00000000
6571 /* The reset value of the ALT_SPIS_DR24_DR24 register field. */
6572 #define ALT_SPIS_DR24_DR24_RESET 0x0
6573 /* Extracts the ALT_SPIS_DR24_DR24 field value from a register. */
6574 #define ALT_SPIS_DR24_DR24_GET(value) (((value) & 0xffffffff) >> 0)
6575 /* Produces a ALT_SPIS_DR24_DR24 register field value suitable for setting the register. */
6576 #define ALT_SPIS_DR24_DR24_SET(value) (((value) << 0) & 0xffffffff)
6577 
6578 #ifndef __ASSEMBLY__
6579 /*
6580  * WARNING: The C register and register group struct declarations are provided for
6581  * convenience and illustrative purposes. They should, however, be used with
6582  * caution as the C language standard provides no guarantees about the alignment or
6583  * atomicity of device memory accesses. The recommended practice for coding device
6584  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6585  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6586  * alt_write_dword() functions for 64 bit registers.
6587  *
6588  * The struct declaration for register ALT_SPIS_DR24.
6589  */
6590 struct ALT_SPIS_DR24_s
6591 {
6592  volatile uint32_t dr24 : 32; /* ALT_SPIS_DR24_DR24 */
6593 };
6594 
6595 /* The typedef declaration for register ALT_SPIS_DR24. */
6596 typedef struct ALT_SPIS_DR24_s ALT_SPIS_DR24_t;
6597 #endif /* __ASSEMBLY__ */
6598 
6599 /* The reset value of the ALT_SPIS_DR24 register. */
6600 #define ALT_SPIS_DR24_RESET 0x00000000
6601 /* The byte offset of the ALT_SPIS_DR24 register from the beginning of the component. */
6602 #define ALT_SPIS_DR24_OFST 0xc0
6603 /* The address of the ALT_SPIS_DR24 register. */
6604 #define ALT_SPIS_DR24_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR24_OFST))
6605 
6606 /*
6607  * Register : DW_apb_ssi Data Register - DR25
6608  *
6609  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6610  * read/write buffer for
6611  *
6612  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6613  * set to 32, then all 32 bits
6614  *
6615  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6616  * register is read, data in the
6617  *
6618  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6619  * transmit FIFO buffer; a write
6620  *
6621  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6622  *
6623  * Register Layout
6624  *
6625  * Bits | Access | Reset | Description
6626  * :-------|:-------|:------|:-------------------
6627  * [31:0] | RW | 0x0 | ALT_SPIS_DR25_DR25
6628  *
6629  */
6630 /*
6631  * Field : dr25
6632  *
6633  * Data Register. When writing to this register, you must right-justify the data.
6634  * Read
6635  *
6636  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6637  *
6638  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6639  * of the
6640  *
6641  * register are valid.
6642  *
6643  * Read = Receive FIFO buffer
6644  *
6645  * Write = Transmit FIFO buffer.
6646  *
6647  * Field Access Macros:
6648  *
6649  */
6650 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR25_DR25 register field. */
6651 #define ALT_SPIS_DR25_DR25_LSB 0
6652 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR25_DR25 register field. */
6653 #define ALT_SPIS_DR25_DR25_MSB 31
6654 /* The width in bits of the ALT_SPIS_DR25_DR25 register field. */
6655 #define ALT_SPIS_DR25_DR25_WIDTH 32
6656 /* The mask used to set the ALT_SPIS_DR25_DR25 register field value. */
6657 #define ALT_SPIS_DR25_DR25_SET_MSK 0xffffffff
6658 /* The mask used to clear the ALT_SPIS_DR25_DR25 register field value. */
6659 #define ALT_SPIS_DR25_DR25_CLR_MSK 0x00000000
6660 /* The reset value of the ALT_SPIS_DR25_DR25 register field. */
6661 #define ALT_SPIS_DR25_DR25_RESET 0x0
6662 /* Extracts the ALT_SPIS_DR25_DR25 field value from a register. */
6663 #define ALT_SPIS_DR25_DR25_GET(value) (((value) & 0xffffffff) >> 0)
6664 /* Produces a ALT_SPIS_DR25_DR25 register field value suitable for setting the register. */
6665 #define ALT_SPIS_DR25_DR25_SET(value) (((value) << 0) & 0xffffffff)
6666 
6667 #ifndef __ASSEMBLY__
6668 /*
6669  * WARNING: The C register and register group struct declarations are provided for
6670  * convenience and illustrative purposes. They should, however, be used with
6671  * caution as the C language standard provides no guarantees about the alignment or
6672  * atomicity of device memory accesses. The recommended practice for coding device
6673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6675  * alt_write_dword() functions for 64 bit registers.
6676  *
6677  * The struct declaration for register ALT_SPIS_DR25.
6678  */
6679 struct ALT_SPIS_DR25_s
6680 {
6681  volatile uint32_t dr25 : 32; /* ALT_SPIS_DR25_DR25 */
6682 };
6683 
6684 /* The typedef declaration for register ALT_SPIS_DR25. */
6685 typedef struct ALT_SPIS_DR25_s ALT_SPIS_DR25_t;
6686 #endif /* __ASSEMBLY__ */
6687 
6688 /* The reset value of the ALT_SPIS_DR25 register. */
6689 #define ALT_SPIS_DR25_RESET 0x00000000
6690 /* The byte offset of the ALT_SPIS_DR25 register from the beginning of the component. */
6691 #define ALT_SPIS_DR25_OFST 0xc4
6692 /* The address of the ALT_SPIS_DR25 register. */
6693 #define ALT_SPIS_DR25_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR25_OFST))
6694 
6695 /*
6696  * Register : DW_apb_ssi Data Register - DR26
6697  *
6698  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6699  * read/write buffer for
6700  *
6701  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6702  * set to 32, then all 32 bits
6703  *
6704  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6705  * register is read, data in the
6706  *
6707  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6708  * transmit FIFO buffer; a write
6709  *
6710  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6711  *
6712  * Register Layout
6713  *
6714  * Bits | Access | Reset | Description
6715  * :-------|:-------|:------|:-------------------
6716  * [31:0] | RW | 0x0 | ALT_SPIS_DR26_DR26
6717  *
6718  */
6719 /*
6720  * Field : dr26
6721  *
6722  * Data Register. When writing to this register, you must right-justify the data.
6723  * Read
6724  *
6725  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6726  *
6727  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6728  * of the
6729  *
6730  * register are valid.
6731  *
6732  * Read = Receive FIFO buffer
6733  *
6734  * Write = Transmit FIFO buffer.
6735  *
6736  * Field Access Macros:
6737  *
6738  */
6739 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR26_DR26 register field. */
6740 #define ALT_SPIS_DR26_DR26_LSB 0
6741 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR26_DR26 register field. */
6742 #define ALT_SPIS_DR26_DR26_MSB 31
6743 /* The width in bits of the ALT_SPIS_DR26_DR26 register field. */
6744 #define ALT_SPIS_DR26_DR26_WIDTH 32
6745 /* The mask used to set the ALT_SPIS_DR26_DR26 register field value. */
6746 #define ALT_SPIS_DR26_DR26_SET_MSK 0xffffffff
6747 /* The mask used to clear the ALT_SPIS_DR26_DR26 register field value. */
6748 #define ALT_SPIS_DR26_DR26_CLR_MSK 0x00000000
6749 /* The reset value of the ALT_SPIS_DR26_DR26 register field. */
6750 #define ALT_SPIS_DR26_DR26_RESET 0x0
6751 /* Extracts the ALT_SPIS_DR26_DR26 field value from a register. */
6752 #define ALT_SPIS_DR26_DR26_GET(value) (((value) & 0xffffffff) >> 0)
6753 /* Produces a ALT_SPIS_DR26_DR26 register field value suitable for setting the register. */
6754 #define ALT_SPIS_DR26_DR26_SET(value) (((value) << 0) & 0xffffffff)
6755 
6756 #ifndef __ASSEMBLY__
6757 /*
6758  * WARNING: The C register and register group struct declarations are provided for
6759  * convenience and illustrative purposes. They should, however, be used with
6760  * caution as the C language standard provides no guarantees about the alignment or
6761  * atomicity of device memory accesses. The recommended practice for coding device
6762  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6763  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6764  * alt_write_dword() functions for 64 bit registers.
6765  *
6766  * The struct declaration for register ALT_SPIS_DR26.
6767  */
6768 struct ALT_SPIS_DR26_s
6769 {
6770  volatile uint32_t dr26 : 32; /* ALT_SPIS_DR26_DR26 */
6771 };
6772 
6773 /* The typedef declaration for register ALT_SPIS_DR26. */
6774 typedef struct ALT_SPIS_DR26_s ALT_SPIS_DR26_t;
6775 #endif /* __ASSEMBLY__ */
6776 
6777 /* The reset value of the ALT_SPIS_DR26 register. */
6778 #define ALT_SPIS_DR26_RESET 0x00000000
6779 /* The byte offset of the ALT_SPIS_DR26 register from the beginning of the component. */
6780 #define ALT_SPIS_DR26_OFST 0xc8
6781 /* The address of the ALT_SPIS_DR26 register. */
6782 #define ALT_SPIS_DR26_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR26_OFST))
6783 
6784 /*
6785  * Register : DW_apb_ssi Data Register - DR27
6786  *
6787  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6788  * read/write buffer for
6789  *
6790  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6791  * set to 32, then all 32 bits
6792  *
6793  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6794  * register is read, data in the
6795  *
6796  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6797  * transmit FIFO buffer; a write
6798  *
6799  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6800  *
6801  * Register Layout
6802  *
6803  * Bits | Access | Reset | Description
6804  * :-------|:-------|:------|:-------------------
6805  * [31:0] | RW | 0x0 | ALT_SPIS_DR27_DR27
6806  *
6807  */
6808 /*
6809  * Field : dr27
6810  *
6811  * Data Register. When writing to this register, you must right-justify the data.
6812  * Read
6813  *
6814  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6815  *
6816  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6817  * of the
6818  *
6819  * register are valid.
6820  *
6821  * Read = Receive FIFO buffer
6822  *
6823  * Write = Transmit FIFO buffer.
6824  *
6825  * Field Access Macros:
6826  *
6827  */
6828 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR27_DR27 register field. */
6829 #define ALT_SPIS_DR27_DR27_LSB 0
6830 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR27_DR27 register field. */
6831 #define ALT_SPIS_DR27_DR27_MSB 31
6832 /* The width in bits of the ALT_SPIS_DR27_DR27 register field. */
6833 #define ALT_SPIS_DR27_DR27_WIDTH 32
6834 /* The mask used to set the ALT_SPIS_DR27_DR27 register field value. */
6835 #define ALT_SPIS_DR27_DR27_SET_MSK 0xffffffff
6836 /* The mask used to clear the ALT_SPIS_DR27_DR27 register field value. */
6837 #define ALT_SPIS_DR27_DR27_CLR_MSK 0x00000000
6838 /* The reset value of the ALT_SPIS_DR27_DR27 register field. */
6839 #define ALT_SPIS_DR27_DR27_RESET 0x0
6840 /* Extracts the ALT_SPIS_DR27_DR27 field value from a register. */
6841 #define ALT_SPIS_DR27_DR27_GET(value) (((value) & 0xffffffff) >> 0)
6842 /* Produces a ALT_SPIS_DR27_DR27 register field value suitable for setting the register. */
6843 #define ALT_SPIS_DR27_DR27_SET(value) (((value) << 0) & 0xffffffff)
6844 
6845 #ifndef __ASSEMBLY__
6846 /*
6847  * WARNING: The C register and register group struct declarations are provided for
6848  * convenience and illustrative purposes. They should, however, be used with
6849  * caution as the C language standard provides no guarantees about the alignment or
6850  * atomicity of device memory accesses. The recommended practice for coding device
6851  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6852  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6853  * alt_write_dword() functions for 64 bit registers.
6854  *
6855  * The struct declaration for register ALT_SPIS_DR27.
6856  */
6857 struct ALT_SPIS_DR27_s
6858 {
6859  volatile uint32_t dr27 : 32; /* ALT_SPIS_DR27_DR27 */
6860 };
6861 
6862 /* The typedef declaration for register ALT_SPIS_DR27. */
6863 typedef struct ALT_SPIS_DR27_s ALT_SPIS_DR27_t;
6864 #endif /* __ASSEMBLY__ */
6865 
6866 /* The reset value of the ALT_SPIS_DR27 register. */
6867 #define ALT_SPIS_DR27_RESET 0x00000000
6868 /* The byte offset of the ALT_SPIS_DR27 register from the beginning of the component. */
6869 #define ALT_SPIS_DR27_OFST 0xcc
6870 /* The address of the ALT_SPIS_DR27 register. */
6871 #define ALT_SPIS_DR27_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR27_OFST))
6872 
6873 /*
6874  * Register : DW_apb_ssi Data Register - DR28
6875  *
6876  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6877  * read/write buffer for
6878  *
6879  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6880  * set to 32, then all 32 bits
6881  *
6882  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6883  * register is read, data in the
6884  *
6885  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6886  * transmit FIFO buffer; a write
6887  *
6888  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6889  *
6890  * Register Layout
6891  *
6892  * Bits | Access | Reset | Description
6893  * :-------|:-------|:------|:-------------------
6894  * [31:0] | RW | 0x0 | ALT_SPIS_DR28_DR28
6895  *
6896  */
6897 /*
6898  * Field : dr28
6899  *
6900  * Data Register. When writing to this register, you must right-justify the data.
6901  * Read
6902  *
6903  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6904  *
6905  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6906  * of the
6907  *
6908  * register are valid.
6909  *
6910  * Read = Receive FIFO buffer
6911  *
6912  * Write = Transmit FIFO buffer.
6913  *
6914  * Field Access Macros:
6915  *
6916  */
6917 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR28_DR28 register field. */
6918 #define ALT_SPIS_DR28_DR28_LSB 0
6919 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR28_DR28 register field. */
6920 #define ALT_SPIS_DR28_DR28_MSB 31
6921 /* The width in bits of the ALT_SPIS_DR28_DR28 register field. */
6922 #define ALT_SPIS_DR28_DR28_WIDTH 32
6923 /* The mask used to set the ALT_SPIS_DR28_DR28 register field value. */
6924 #define ALT_SPIS_DR28_DR28_SET_MSK 0xffffffff
6925 /* The mask used to clear the ALT_SPIS_DR28_DR28 register field value. */
6926 #define ALT_SPIS_DR28_DR28_CLR_MSK 0x00000000
6927 /* The reset value of the ALT_SPIS_DR28_DR28 register field. */
6928 #define ALT_SPIS_DR28_DR28_RESET 0x0
6929 /* Extracts the ALT_SPIS_DR28_DR28 field value from a register. */
6930 #define ALT_SPIS_DR28_DR28_GET(value) (((value) & 0xffffffff) >> 0)
6931 /* Produces a ALT_SPIS_DR28_DR28 register field value suitable for setting the register. */
6932 #define ALT_SPIS_DR28_DR28_SET(value) (((value) << 0) & 0xffffffff)
6933 
6934 #ifndef __ASSEMBLY__
6935 /*
6936  * WARNING: The C register and register group struct declarations are provided for
6937  * convenience and illustrative purposes. They should, however, be used with
6938  * caution as the C language standard provides no guarantees about the alignment or
6939  * atomicity of device memory accesses. The recommended practice for coding device
6940  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6941  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6942  * alt_write_dword() functions for 64 bit registers.
6943  *
6944  * The struct declaration for register ALT_SPIS_DR28.
6945  */
6946 struct ALT_SPIS_DR28_s
6947 {
6948  volatile uint32_t dr28 : 32; /* ALT_SPIS_DR28_DR28 */
6949 };
6950 
6951 /* The typedef declaration for register ALT_SPIS_DR28. */
6952 typedef struct ALT_SPIS_DR28_s ALT_SPIS_DR28_t;
6953 #endif /* __ASSEMBLY__ */
6954 
6955 /* The reset value of the ALT_SPIS_DR28 register. */
6956 #define ALT_SPIS_DR28_RESET 0x00000000
6957 /* The byte offset of the ALT_SPIS_DR28 register from the beginning of the component. */
6958 #define ALT_SPIS_DR28_OFST 0xd0
6959 /* The address of the ALT_SPIS_DR28 register. */
6960 #define ALT_SPIS_DR28_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR28_OFST))
6961 
6962 /*
6963  * Register : DW_apb_ssi Data Register - DR29
6964  *
6965  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6966  * read/write buffer for
6967  *
6968  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6969  * set to 32, then all 32 bits
6970  *
6971  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6972  * register is read, data in the
6973  *
6974  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6975  * transmit FIFO buffer; a write
6976  *
6977  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6978  *
6979  * Register Layout
6980  *
6981  * Bits | Access | Reset | Description
6982  * :-------|:-------|:------|:-------------------
6983  * [31:0] | RW | 0x0 | ALT_SPIS_DR29_DR29
6984  *
6985  */
6986 /*
6987  * Field : dr29
6988  *
6989  * Data Register. When writing to this register, you must right-justify the data.
6990  * Read
6991  *
6992  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6993  *
6994  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6995  * of the
6996  *
6997  * register are valid.
6998  *
6999  * Read = Receive FIFO buffer
7000  *
7001  * Write = Transmit FIFO buffer.
7002  *
7003  * Field Access Macros:
7004  *
7005  */
7006 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR29_DR29 register field. */
7007 #define ALT_SPIS_DR29_DR29_LSB 0
7008 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR29_DR29 register field. */
7009 #define ALT_SPIS_DR29_DR29_MSB 31
7010 /* The width in bits of the ALT_SPIS_DR29_DR29 register field. */
7011 #define ALT_SPIS_DR29_DR29_WIDTH 32
7012 /* The mask used to set the ALT_SPIS_DR29_DR29 register field value. */
7013 #define ALT_SPIS_DR29_DR29_SET_MSK 0xffffffff
7014 /* The mask used to clear the ALT_SPIS_DR29_DR29 register field value. */
7015 #define ALT_SPIS_DR29_DR29_CLR_MSK 0x00000000
7016 /* The reset value of the ALT_SPIS_DR29_DR29 register field. */
7017 #define ALT_SPIS_DR29_DR29_RESET 0x0
7018 /* Extracts the ALT_SPIS_DR29_DR29 field value from a register. */
7019 #define ALT_SPIS_DR29_DR29_GET(value) (((value) & 0xffffffff) >> 0)
7020 /* Produces a ALT_SPIS_DR29_DR29 register field value suitable for setting the register. */
7021 #define ALT_SPIS_DR29_DR29_SET(value) (((value) << 0) & 0xffffffff)
7022 
7023 #ifndef __ASSEMBLY__
7024 /*
7025  * WARNING: The C register and register group struct declarations are provided for
7026  * convenience and illustrative purposes. They should, however, be used with
7027  * caution as the C language standard provides no guarantees about the alignment or
7028  * atomicity of device memory accesses. The recommended practice for coding device
7029  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7030  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7031  * alt_write_dword() functions for 64 bit registers.
7032  *
7033  * The struct declaration for register ALT_SPIS_DR29.
7034  */
7035 struct ALT_SPIS_DR29_s
7036 {
7037  volatile uint32_t dr29 : 32; /* ALT_SPIS_DR29_DR29 */
7038 };
7039 
7040 /* The typedef declaration for register ALT_SPIS_DR29. */
7041 typedef struct ALT_SPIS_DR29_s ALT_SPIS_DR29_t;
7042 #endif /* __ASSEMBLY__ */
7043 
7044 /* The reset value of the ALT_SPIS_DR29 register. */
7045 #define ALT_SPIS_DR29_RESET 0x00000000
7046 /* The byte offset of the ALT_SPIS_DR29 register from the beginning of the component. */
7047 #define ALT_SPIS_DR29_OFST 0xd4
7048 /* The address of the ALT_SPIS_DR29 register. */
7049 #define ALT_SPIS_DR29_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR29_OFST))
7050 
7051 /*
7052  * Register : DW_apb_ssi Data Register - DR30
7053  *
7054  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7055  * read/write buffer for
7056  *
7057  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7058  * set to 32, then all 32 bits
7059  *
7060  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7061  * register is read, data in the
7062  *
7063  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7064  * transmit FIFO buffer; a write
7065  *
7066  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7067  *
7068  * Register Layout
7069  *
7070  * Bits | Access | Reset | Description
7071  * :-------|:-------|:------|:-------------------
7072  * [31:0] | RW | 0x0 | ALT_SPIS_DR30_DR30
7073  *
7074  */
7075 /*
7076  * Field : dr30
7077  *
7078  * Data Register. When writing to this register, you must right-justify the data.
7079  * Read
7080  *
7081  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7082  *
7083  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7084  * of the
7085  *
7086  * register are valid.
7087  *
7088  * Read = Receive FIFO buffer
7089  *
7090  * Write = Transmit FIFO buffer.
7091  *
7092  * Field Access Macros:
7093  *
7094  */
7095 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR30_DR30 register field. */
7096 #define ALT_SPIS_DR30_DR30_LSB 0
7097 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR30_DR30 register field. */
7098 #define ALT_SPIS_DR30_DR30_MSB 31
7099 /* The width in bits of the ALT_SPIS_DR30_DR30 register field. */
7100 #define ALT_SPIS_DR30_DR30_WIDTH 32
7101 /* The mask used to set the ALT_SPIS_DR30_DR30 register field value. */
7102 #define ALT_SPIS_DR30_DR30_SET_MSK 0xffffffff
7103 /* The mask used to clear the ALT_SPIS_DR30_DR30 register field value. */
7104 #define ALT_SPIS_DR30_DR30_CLR_MSK 0x00000000
7105 /* The reset value of the ALT_SPIS_DR30_DR30 register field. */
7106 #define ALT_SPIS_DR30_DR30_RESET 0x0
7107 /* Extracts the ALT_SPIS_DR30_DR30 field value from a register. */
7108 #define ALT_SPIS_DR30_DR30_GET(value) (((value) & 0xffffffff) >> 0)
7109 /* Produces a ALT_SPIS_DR30_DR30 register field value suitable for setting the register. */
7110 #define ALT_SPIS_DR30_DR30_SET(value) (((value) << 0) & 0xffffffff)
7111 
7112 #ifndef __ASSEMBLY__
7113 /*
7114  * WARNING: The C register and register group struct declarations are provided for
7115  * convenience and illustrative purposes. They should, however, be used with
7116  * caution as the C language standard provides no guarantees about the alignment or
7117  * atomicity of device memory accesses. The recommended practice for coding device
7118  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7119  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7120  * alt_write_dword() functions for 64 bit registers.
7121  *
7122  * The struct declaration for register ALT_SPIS_DR30.
7123  */
7124 struct ALT_SPIS_DR30_s
7125 {
7126  volatile uint32_t dr30 : 32; /* ALT_SPIS_DR30_DR30 */
7127 };
7128 
7129 /* The typedef declaration for register ALT_SPIS_DR30. */
7130 typedef struct ALT_SPIS_DR30_s ALT_SPIS_DR30_t;
7131 #endif /* __ASSEMBLY__ */
7132 
7133 /* The reset value of the ALT_SPIS_DR30 register. */
7134 #define ALT_SPIS_DR30_RESET 0x00000000
7135 /* The byte offset of the ALT_SPIS_DR30 register from the beginning of the component. */
7136 #define ALT_SPIS_DR30_OFST 0xd8
7137 /* The address of the ALT_SPIS_DR30 register. */
7138 #define ALT_SPIS_DR30_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR30_OFST))
7139 
7140 /*
7141  * Register : DW_apb_ssi Data Register - DR31
7142  *
7143  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7144  * read/write buffer for
7145  *
7146  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7147  * set to 32, then all 32 bits
7148  *
7149  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7150  * register is read, data in the
7151  *
7152  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7153  * transmit FIFO buffer; a write
7154  *
7155  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7156  *
7157  * Register Layout
7158  *
7159  * Bits | Access | Reset | Description
7160  * :-------|:-------|:------|:-------------------
7161  * [31:0] | RW | 0x0 | ALT_SPIS_DR31_DR31
7162  *
7163  */
7164 /*
7165  * Field : dr31
7166  *
7167  * Data Register. When writing to this register, you must right-justify the data.
7168  * Read
7169  *
7170  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7171  *
7172  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7173  * of the
7174  *
7175  * register are valid.
7176  *
7177  * Read = Receive FIFO buffer
7178  *
7179  * Write = Transmit FIFO buffer.
7180  *
7181  * Field Access Macros:
7182  *
7183  */
7184 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR31_DR31 register field. */
7185 #define ALT_SPIS_DR31_DR31_LSB 0
7186 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR31_DR31 register field. */
7187 #define ALT_SPIS_DR31_DR31_MSB 31
7188 /* The width in bits of the ALT_SPIS_DR31_DR31 register field. */
7189 #define ALT_SPIS_DR31_DR31_WIDTH 32
7190 /* The mask used to set the ALT_SPIS_DR31_DR31 register field value. */
7191 #define ALT_SPIS_DR31_DR31_SET_MSK 0xffffffff
7192 /* The mask used to clear the ALT_SPIS_DR31_DR31 register field value. */
7193 #define ALT_SPIS_DR31_DR31_CLR_MSK 0x00000000
7194 /* The reset value of the ALT_SPIS_DR31_DR31 register field. */
7195 #define ALT_SPIS_DR31_DR31_RESET 0x0
7196 /* Extracts the ALT_SPIS_DR31_DR31 field value from a register. */
7197 #define ALT_SPIS_DR31_DR31_GET(value) (((value) & 0xffffffff) >> 0)
7198 /* Produces a ALT_SPIS_DR31_DR31 register field value suitable for setting the register. */
7199 #define ALT_SPIS_DR31_DR31_SET(value) (((value) << 0) & 0xffffffff)
7200 
7201 #ifndef __ASSEMBLY__
7202 /*
7203  * WARNING: The C register and register group struct declarations are provided for
7204  * convenience and illustrative purposes. They should, however, be used with
7205  * caution as the C language standard provides no guarantees about the alignment or
7206  * atomicity of device memory accesses. The recommended practice for coding device
7207  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7208  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7209  * alt_write_dword() functions for 64 bit registers.
7210  *
7211  * The struct declaration for register ALT_SPIS_DR31.
7212  */
7213 struct ALT_SPIS_DR31_s
7214 {
7215  volatile uint32_t dr31 : 32; /* ALT_SPIS_DR31_DR31 */
7216 };
7217 
7218 /* The typedef declaration for register ALT_SPIS_DR31. */
7219 typedef struct ALT_SPIS_DR31_s ALT_SPIS_DR31_t;
7220 #endif /* __ASSEMBLY__ */
7221 
7222 /* The reset value of the ALT_SPIS_DR31 register. */
7223 #define ALT_SPIS_DR31_RESET 0x00000000
7224 /* The byte offset of the ALT_SPIS_DR31 register from the beginning of the component. */
7225 #define ALT_SPIS_DR31_OFST 0xdc
7226 /* The address of the ALT_SPIS_DR31 register. */
7227 #define ALT_SPIS_DR31_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR31_OFST))
7228 
7229 /*
7230  * Register : DW_apb_ssi Data Register - DR32
7231  *
7232  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7233  * read/write buffer for
7234  *
7235  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7236  * set to 32, then all 32 bits
7237  *
7238  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7239  * register is read, data in the
7240  *
7241  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7242  * transmit FIFO buffer; a write
7243  *
7244  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7245  *
7246  * Register Layout
7247  *
7248  * Bits | Access | Reset | Description
7249  * :-------|:-------|:------|:-------------------
7250  * [31:0] | RW | 0x0 | ALT_SPIS_DR32_DR32
7251  *
7252  */
7253 /*
7254  * Field : dr32
7255  *
7256  * Data Register. When writing to this register, you must right-justify the data.
7257  * Read
7258  *
7259  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7260  *
7261  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7262  * of the
7263  *
7264  * register are valid.
7265  *
7266  * Read = Receive FIFO buffer
7267  *
7268  * Write = Transmit FIFO buffer.
7269  *
7270  * Field Access Macros:
7271  *
7272  */
7273 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR32_DR32 register field. */
7274 #define ALT_SPIS_DR32_DR32_LSB 0
7275 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR32_DR32 register field. */
7276 #define ALT_SPIS_DR32_DR32_MSB 31
7277 /* The width in bits of the ALT_SPIS_DR32_DR32 register field. */
7278 #define ALT_SPIS_DR32_DR32_WIDTH 32
7279 /* The mask used to set the ALT_SPIS_DR32_DR32 register field value. */
7280 #define ALT_SPIS_DR32_DR32_SET_MSK 0xffffffff
7281 /* The mask used to clear the ALT_SPIS_DR32_DR32 register field value. */
7282 #define ALT_SPIS_DR32_DR32_CLR_MSK 0x00000000
7283 /* The reset value of the ALT_SPIS_DR32_DR32 register field. */
7284 #define ALT_SPIS_DR32_DR32_RESET 0x0
7285 /* Extracts the ALT_SPIS_DR32_DR32 field value from a register. */
7286 #define ALT_SPIS_DR32_DR32_GET(value) (((value) & 0xffffffff) >> 0)
7287 /* Produces a ALT_SPIS_DR32_DR32 register field value suitable for setting the register. */
7288 #define ALT_SPIS_DR32_DR32_SET(value) (((value) << 0) & 0xffffffff)
7289 
7290 #ifndef __ASSEMBLY__
7291 /*
7292  * WARNING: The C register and register group struct declarations are provided for
7293  * convenience and illustrative purposes. They should, however, be used with
7294  * caution as the C language standard provides no guarantees about the alignment or
7295  * atomicity of device memory accesses. The recommended practice for coding device
7296  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7297  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7298  * alt_write_dword() functions for 64 bit registers.
7299  *
7300  * The struct declaration for register ALT_SPIS_DR32.
7301  */
7302 struct ALT_SPIS_DR32_s
7303 {
7304  volatile uint32_t dr32 : 32; /* ALT_SPIS_DR32_DR32 */
7305 };
7306 
7307 /* The typedef declaration for register ALT_SPIS_DR32. */
7308 typedef struct ALT_SPIS_DR32_s ALT_SPIS_DR32_t;
7309 #endif /* __ASSEMBLY__ */
7310 
7311 /* The reset value of the ALT_SPIS_DR32 register. */
7312 #define ALT_SPIS_DR32_RESET 0x00000000
7313 /* The byte offset of the ALT_SPIS_DR32 register from the beginning of the component. */
7314 #define ALT_SPIS_DR32_OFST 0xe0
7315 /* The address of the ALT_SPIS_DR32 register. */
7316 #define ALT_SPIS_DR32_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR32_OFST))
7317 
7318 /*
7319  * Register : DW_apb_ssi Data Register - DR33
7320  *
7321  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7322  * read/write buffer for
7323  *
7324  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7325  * set to 32, then all 32 bits
7326  *
7327  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7328  * register is read, data in the
7329  *
7330  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7331  * transmit FIFO buffer; a write
7332  *
7333  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7334  *
7335  * Register Layout
7336  *
7337  * Bits | Access | Reset | Description
7338  * :-------|:-------|:------|:-------------------
7339  * [31:0] | RW | 0x0 | ALT_SPIS_DR33_DR33
7340  *
7341  */
7342 /*
7343  * Field : dr33
7344  *
7345  * Data Register. When writing to this register, you must right-justify the data.
7346  * Read
7347  *
7348  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7349  *
7350  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7351  * of the
7352  *
7353  * register are valid.
7354  *
7355  * Read = Receive FIFO buffer
7356  *
7357  * Write = Transmit FIFO buffer.
7358  *
7359  * Field Access Macros:
7360  *
7361  */
7362 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR33_DR33 register field. */
7363 #define ALT_SPIS_DR33_DR33_LSB 0
7364 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR33_DR33 register field. */
7365 #define ALT_SPIS_DR33_DR33_MSB 31
7366 /* The width in bits of the ALT_SPIS_DR33_DR33 register field. */
7367 #define ALT_SPIS_DR33_DR33_WIDTH 32
7368 /* The mask used to set the ALT_SPIS_DR33_DR33 register field value. */
7369 #define ALT_SPIS_DR33_DR33_SET_MSK 0xffffffff
7370 /* The mask used to clear the ALT_SPIS_DR33_DR33 register field value. */
7371 #define ALT_SPIS_DR33_DR33_CLR_MSK 0x00000000
7372 /* The reset value of the ALT_SPIS_DR33_DR33 register field. */
7373 #define ALT_SPIS_DR33_DR33_RESET 0x0
7374 /* Extracts the ALT_SPIS_DR33_DR33 field value from a register. */
7375 #define ALT_SPIS_DR33_DR33_GET(value) (((value) & 0xffffffff) >> 0)
7376 /* Produces a ALT_SPIS_DR33_DR33 register field value suitable for setting the register. */
7377 #define ALT_SPIS_DR33_DR33_SET(value) (((value) << 0) & 0xffffffff)
7378 
7379 #ifndef __ASSEMBLY__
7380 /*
7381  * WARNING: The C register and register group struct declarations are provided for
7382  * convenience and illustrative purposes. They should, however, be used with
7383  * caution as the C language standard provides no guarantees about the alignment or
7384  * atomicity of device memory accesses. The recommended practice for coding device
7385  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7386  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7387  * alt_write_dword() functions for 64 bit registers.
7388  *
7389  * The struct declaration for register ALT_SPIS_DR33.
7390  */
7391 struct ALT_SPIS_DR33_s
7392 {
7393  volatile uint32_t dr33 : 32; /* ALT_SPIS_DR33_DR33 */
7394 };
7395 
7396 /* The typedef declaration for register ALT_SPIS_DR33. */
7397 typedef struct ALT_SPIS_DR33_s ALT_SPIS_DR33_t;
7398 #endif /* __ASSEMBLY__ */
7399 
7400 /* The reset value of the ALT_SPIS_DR33 register. */
7401 #define ALT_SPIS_DR33_RESET 0x00000000
7402 /* The byte offset of the ALT_SPIS_DR33 register from the beginning of the component. */
7403 #define ALT_SPIS_DR33_OFST 0xe4
7404 /* The address of the ALT_SPIS_DR33 register. */
7405 #define ALT_SPIS_DR33_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR33_OFST))
7406 
7407 /*
7408  * Register : DW_apb_ssi Data Register - DR34
7409  *
7410  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7411  * read/write buffer for
7412  *
7413  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7414  * set to 32, then all 32 bits
7415  *
7416  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7417  * register is read, data in the
7418  *
7419  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7420  * transmit FIFO buffer; a write
7421  *
7422  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7423  *
7424  * Register Layout
7425  *
7426  * Bits | Access | Reset | Description
7427  * :-------|:-------|:------|:-------------------
7428  * [31:0] | RW | 0x0 | ALT_SPIS_DR34_DR34
7429  *
7430  */
7431 /*
7432  * Field : dr34
7433  *
7434  * Data Register. When writing to this register, you must right-justify the data.
7435  * Read
7436  *
7437  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7438  *
7439  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7440  * of the
7441  *
7442  * register are valid.
7443  *
7444  * Read = Receive FIFO buffer
7445  *
7446  * Write = Transmit FIFO buffer.
7447  *
7448  * Field Access Macros:
7449  *
7450  */
7451 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR34_DR34 register field. */
7452 #define ALT_SPIS_DR34_DR34_LSB 0
7453 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR34_DR34 register field. */
7454 #define ALT_SPIS_DR34_DR34_MSB 31
7455 /* The width in bits of the ALT_SPIS_DR34_DR34 register field. */
7456 #define ALT_SPIS_DR34_DR34_WIDTH 32
7457 /* The mask used to set the ALT_SPIS_DR34_DR34 register field value. */
7458 #define ALT_SPIS_DR34_DR34_SET_MSK 0xffffffff
7459 /* The mask used to clear the ALT_SPIS_DR34_DR34 register field value. */
7460 #define ALT_SPIS_DR34_DR34_CLR_MSK 0x00000000
7461 /* The reset value of the ALT_SPIS_DR34_DR34 register field. */
7462 #define ALT_SPIS_DR34_DR34_RESET 0x0
7463 /* Extracts the ALT_SPIS_DR34_DR34 field value from a register. */
7464 #define ALT_SPIS_DR34_DR34_GET(value) (((value) & 0xffffffff) >> 0)
7465 /* Produces a ALT_SPIS_DR34_DR34 register field value suitable for setting the register. */
7466 #define ALT_SPIS_DR34_DR34_SET(value) (((value) << 0) & 0xffffffff)
7467 
7468 #ifndef __ASSEMBLY__
7469 /*
7470  * WARNING: The C register and register group struct declarations are provided for
7471  * convenience and illustrative purposes. They should, however, be used with
7472  * caution as the C language standard provides no guarantees about the alignment or
7473  * atomicity of device memory accesses. The recommended practice for coding device
7474  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7475  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7476  * alt_write_dword() functions for 64 bit registers.
7477  *
7478  * The struct declaration for register ALT_SPIS_DR34.
7479  */
7480 struct ALT_SPIS_DR34_s
7481 {
7482  volatile uint32_t dr34 : 32; /* ALT_SPIS_DR34_DR34 */
7483 };
7484 
7485 /* The typedef declaration for register ALT_SPIS_DR34. */
7486 typedef struct ALT_SPIS_DR34_s ALT_SPIS_DR34_t;
7487 #endif /* __ASSEMBLY__ */
7488 
7489 /* The reset value of the ALT_SPIS_DR34 register. */
7490 #define ALT_SPIS_DR34_RESET 0x00000000
7491 /* The byte offset of the ALT_SPIS_DR34 register from the beginning of the component. */
7492 #define ALT_SPIS_DR34_OFST 0xe8
7493 /* The address of the ALT_SPIS_DR34 register. */
7494 #define ALT_SPIS_DR34_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR34_OFST))
7495 
7496 /*
7497  * Register : DW_apb_ssi Data Register - DR35
7498  *
7499  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7500  * read/write buffer for
7501  *
7502  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7503  * set to 32, then all 32 bits
7504  *
7505  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7506  * register is read, data in the
7507  *
7508  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7509  * transmit FIFO buffer; a write
7510  *
7511  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7512  *
7513  * Register Layout
7514  *
7515  * Bits | Access | Reset | Description
7516  * :-------|:-------|:------|:-------------------
7517  * [31:0] | RW | 0x0 | ALT_SPIS_DR35_DR35
7518  *
7519  */
7520 /*
7521  * Field : dr35
7522  *
7523  * Data Register. When writing to this register, you must right-justify the data.
7524  * Read
7525  *
7526  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7527  *
7528  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7529  * of the
7530  *
7531  * register are valid.
7532  *
7533  * Read = Receive FIFO buffer
7534  *
7535  * Write = Transmit FIFO buffer.
7536  *
7537  * Field Access Macros:
7538  *
7539  */
7540 /* The Least Significant Bit (LSB) position of the ALT_SPIS_DR35_DR35 register field. */
7541 #define ALT_SPIS_DR35_DR35_LSB 0
7542 /* The Most Significant Bit (MSB) position of the ALT_SPIS_DR35_DR35 register field. */
7543 #define ALT_SPIS_DR35_DR35_MSB 31
7544 /* The width in bits of the ALT_SPIS_DR35_DR35 register field. */
7545 #define ALT_SPIS_DR35_DR35_WIDTH 32
7546 /* The mask used to set the ALT_SPIS_DR35_DR35 register field value. */
7547 #define ALT_SPIS_DR35_DR35_SET_MSK 0xffffffff
7548 /* The mask used to clear the ALT_SPIS_DR35_DR35 register field value. */
7549 #define ALT_SPIS_DR35_DR35_CLR_MSK 0x00000000
7550 /* The reset value of the ALT_SPIS_DR35_DR35 register field. */
7551 #define ALT_SPIS_DR35_DR35_RESET 0x0
7552 /* Extracts the ALT_SPIS_DR35_DR35 field value from a register. */
7553 #define ALT_SPIS_DR35_DR35_GET(value) (((value) & 0xffffffff) >> 0)
7554 /* Produces a ALT_SPIS_DR35_DR35 register field value suitable for setting the register. */
7555 #define ALT_SPIS_DR35_DR35_SET(value) (((value) << 0) & 0xffffffff)
7556 
7557 #ifndef __ASSEMBLY__
7558 /*
7559  * WARNING: The C register and register group struct declarations are provided for
7560  * convenience and illustrative purposes. They should, however, be used with
7561  * caution as the C language standard provides no guarantees about the alignment or
7562  * atomicity of device memory accesses. The recommended practice for coding device
7563  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7564  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7565  * alt_write_dword() functions for 64 bit registers.
7566  *
7567  * The struct declaration for register ALT_SPIS_DR35.
7568  */
7569 struct ALT_SPIS_DR35_s
7570 {
7571  volatile uint32_t dr35 : 32; /* ALT_SPIS_DR35_DR35 */
7572 };
7573 
7574 /* The typedef declaration for register ALT_SPIS_DR35. */
7575 typedef struct ALT_SPIS_DR35_s ALT_SPIS_DR35_t;
7576 #endif /* __ASSEMBLY__ */
7577 
7578 /* The reset value of the ALT_SPIS_DR35 register. */
7579 #define ALT_SPIS_DR35_RESET 0x00000000
7580 /* The byte offset of the ALT_SPIS_DR35 register from the beginning of the component. */
7581 #define ALT_SPIS_DR35_OFST 0xec
7582 /* The address of the ALT_SPIS_DR35 register. */
7583 #define ALT_SPIS_DR35_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR35_OFST))
7584 
7585 /*
7586  * Register : RSVD_1 - Reserved address location - RSVD_1
7587  *
7588  * RSVD_1 - Reserved address location
7589  *
7590  * Register Layout
7591  *
7592  * Bits | Access | Reset | Description
7593  * :-------|:-------|:------|:----------------------
7594  * [31:0] | R | 0x0 | ALT_SPIS_RSVD_1_RSVD1
7595  *
7596  */
7597 /*
7598  * Field : RSVD1
7599  *
7600  * Reserved address location
7601  *
7602  * Field Access Macros:
7603  *
7604  */
7605 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RSVD_1_RSVD1 register field. */
7606 #define ALT_SPIS_RSVD_1_RSVD1_LSB 0
7607 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RSVD_1_RSVD1 register field. */
7608 #define ALT_SPIS_RSVD_1_RSVD1_MSB 31
7609 /* The width in bits of the ALT_SPIS_RSVD_1_RSVD1 register field. */
7610 #define ALT_SPIS_RSVD_1_RSVD1_WIDTH 32
7611 /* The mask used to set the ALT_SPIS_RSVD_1_RSVD1 register field value. */
7612 #define ALT_SPIS_RSVD_1_RSVD1_SET_MSK 0xffffffff
7613 /* The mask used to clear the ALT_SPIS_RSVD_1_RSVD1 register field value. */
7614 #define ALT_SPIS_RSVD_1_RSVD1_CLR_MSK 0x00000000
7615 /* The reset value of the ALT_SPIS_RSVD_1_RSVD1 register field. */
7616 #define ALT_SPIS_RSVD_1_RSVD1_RESET 0x0
7617 /* Extracts the ALT_SPIS_RSVD_1_RSVD1 field value from a register. */
7618 #define ALT_SPIS_RSVD_1_RSVD1_GET(value) (((value) & 0xffffffff) >> 0)
7619 /* Produces a ALT_SPIS_RSVD_1_RSVD1 register field value suitable for setting the register. */
7620 #define ALT_SPIS_RSVD_1_RSVD1_SET(value) (((value) << 0) & 0xffffffff)
7621 
7622 #ifndef __ASSEMBLY__
7623 /*
7624  * WARNING: The C register and register group struct declarations are provided for
7625  * convenience and illustrative purposes. They should, however, be used with
7626  * caution as the C language standard provides no guarantees about the alignment or
7627  * atomicity of device memory accesses. The recommended practice for coding device
7628  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7629  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7630  * alt_write_dword() functions for 64 bit registers.
7631  *
7632  * The struct declaration for register ALT_SPIS_RSVD_1.
7633  */
7634 struct ALT_SPIS_RSVD_1_s
7635 {
7636  const volatile uint32_t RSVD1 : 32; /* ALT_SPIS_RSVD_1_RSVD1 */
7637 };
7638 
7639 /* The typedef declaration for register ALT_SPIS_RSVD_1. */
7640 typedef struct ALT_SPIS_RSVD_1_s ALT_SPIS_RSVD_1_t;
7641 #endif /* __ASSEMBLY__ */
7642 
7643 /* The reset value of the ALT_SPIS_RSVD_1 register. */
7644 #define ALT_SPIS_RSVD_1_RESET 0x00000000
7645 /* The byte offset of the ALT_SPIS_RSVD_1 register from the beginning of the component. */
7646 #define ALT_SPIS_RSVD_1_OFST 0xf8
7647 /* The address of the ALT_SPIS_RSVD_1 register. */
7648 #define ALT_SPIS_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RSVD_1_OFST))
7649 
7650 /*
7651  * Register : RSVD_2 - Reserved address location - RSVD_2
7652  *
7653  * RSVD_2 - Reserved address location
7654  *
7655  * Register Layout
7656  *
7657  * Bits | Access | Reset | Description
7658  * :-------|:-------|:------|:----------------------
7659  * [31:0] | R | 0x0 | ALT_SPIS_RSVD_2_RSVD2
7660  *
7661  */
7662 /*
7663  * Field : RSVD2
7664  *
7665  * Reserved address location
7666  *
7667  * Field Access Macros:
7668  *
7669  */
7670 /* The Least Significant Bit (LSB) position of the ALT_SPIS_RSVD_2_RSVD2 register field. */
7671 #define ALT_SPIS_RSVD_2_RSVD2_LSB 0
7672 /* The Most Significant Bit (MSB) position of the ALT_SPIS_RSVD_2_RSVD2 register field. */
7673 #define ALT_SPIS_RSVD_2_RSVD2_MSB 31
7674 /* The width in bits of the ALT_SPIS_RSVD_2_RSVD2 register field. */
7675 #define ALT_SPIS_RSVD_2_RSVD2_WIDTH 32
7676 /* The mask used to set the ALT_SPIS_RSVD_2_RSVD2 register field value. */
7677 #define ALT_SPIS_RSVD_2_RSVD2_SET_MSK 0xffffffff
7678 /* The mask used to clear the ALT_SPIS_RSVD_2_RSVD2 register field value. */
7679 #define ALT_SPIS_RSVD_2_RSVD2_CLR_MSK 0x00000000
7680 /* The reset value of the ALT_SPIS_RSVD_2_RSVD2 register field. */
7681 #define ALT_SPIS_RSVD_2_RSVD2_RESET 0x0
7682 /* Extracts the ALT_SPIS_RSVD_2_RSVD2 field value from a register. */
7683 #define ALT_SPIS_RSVD_2_RSVD2_GET(value) (((value) & 0xffffffff) >> 0)
7684 /* Produces a ALT_SPIS_RSVD_2_RSVD2 register field value suitable for setting the register. */
7685 #define ALT_SPIS_RSVD_2_RSVD2_SET(value) (((value) << 0) & 0xffffffff)
7686 
7687 #ifndef __ASSEMBLY__
7688 /*
7689  * WARNING: The C register and register group struct declarations are provided for
7690  * convenience and illustrative purposes. They should, however, be used with
7691  * caution as the C language standard provides no guarantees about the alignment or
7692  * atomicity of device memory accesses. The recommended practice for coding device
7693  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7694  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7695  * alt_write_dword() functions for 64 bit registers.
7696  *
7697  * The struct declaration for register ALT_SPIS_RSVD_2.
7698  */
7699 struct ALT_SPIS_RSVD_2_s
7700 {
7701  const volatile uint32_t RSVD2 : 32; /* ALT_SPIS_RSVD_2_RSVD2 */
7702 };
7703 
7704 /* The typedef declaration for register ALT_SPIS_RSVD_2. */
7705 typedef struct ALT_SPIS_RSVD_2_s ALT_SPIS_RSVD_2_t;
7706 #endif /* __ASSEMBLY__ */
7707 
7708 /* The reset value of the ALT_SPIS_RSVD_2 register. */
7709 #define ALT_SPIS_RSVD_2_RESET 0x00000000
7710 /* The byte offset of the ALT_SPIS_RSVD_2 register from the beginning of the component. */
7711 #define ALT_SPIS_RSVD_2_OFST 0xfc
7712 /* The address of the ALT_SPIS_RSVD_2 register. */
7713 #define ALT_SPIS_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RSVD_2_OFST))
7714 
7715 #ifndef __ASSEMBLY__
7716 /*
7717  * WARNING: The C register and register group struct declarations are provided for
7718  * convenience and illustrative purposes. They should, however, be used with
7719  * caution as the C language standard provides no guarantees about the alignment or
7720  * atomicity of device memory accesses. The recommended practice for coding device
7721  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7722  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7723  * alt_write_dword() functions for 64 bit registers.
7724  *
7725  * The struct declaration for register group ALT_SPIS.
7726  */
7727 struct ALT_SPIS_s
7728 {
7729  volatile ALT_SPIS_CTRLR0_t CTRLR0; /* ALT_SPIS_CTRLR0 */
7730  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
7731  volatile ALT_SPIS_SSIENR_t SSIENR; /* ALT_SPIS_SSIENR */
7732  volatile ALT_SPIS_MWCR_t MWCR; /* ALT_SPIS_MWCR */
7733  volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
7734  volatile ALT_SPIS_TXFTLR_t TXFTLR; /* ALT_SPIS_TXFTLR */
7735  volatile ALT_SPIS_RXFTLR_t RXFTLR; /* ALT_SPIS_RXFTLR */
7736  volatile ALT_SPIS_TXFLR_t TXFLR; /* ALT_SPIS_TXFLR */
7737  volatile ALT_SPIS_RXFLR_t RXFLR; /* ALT_SPIS_RXFLR */
7738  volatile ALT_SPIS_SR_t SR; /* ALT_SPIS_SR */
7739  volatile ALT_SPIS_IMR_t IMR; /* ALT_SPIS_IMR */
7740  volatile ALT_SPIS_ISR_t ISR; /* ALT_SPIS_ISR */
7741  volatile ALT_SPIS_RISR_t RISR; /* ALT_SPIS_RISR */
7742  volatile ALT_SPIS_TXOICR_t TXOICR; /* ALT_SPIS_TXOICR */
7743  volatile ALT_SPIS_RXOICR_t RXOICR; /* ALT_SPIS_RXOICR */
7744  volatile ALT_SPIS_RXUICR_t RXUICR; /* ALT_SPIS_RXUICR */
7745  volatile ALT_SPIS_MSTICR_t MSTICR; /* ALT_SPIS_MSTICR */
7746  volatile ALT_SPIS_ICR_t ICR; /* ALT_SPIS_ICR */
7747  volatile ALT_SPIS_DMACR_t DMACR; /* ALT_SPIS_DMACR */
7748  volatile ALT_SPIS_DMATDLR_t DMATDLR; /* ALT_SPIS_DMATDLR */
7749  volatile ALT_SPIS_DMARDLR_t DMARDLR; /* ALT_SPIS_DMARDLR */
7750  volatile ALT_SPIS_IDR_t IDR; /* ALT_SPIS_IDR */
7751  volatile ALT_SPIS_SSI_VERSION_ID_t SSI_VERSION_ID; /* ALT_SPIS_SSI_VERSION_ID */
7752  volatile ALT_SPIS_DR0_t DR0; /* ALT_SPIS_DR0 */
7753  volatile ALT_SPIS_DR1_t DR1; /* ALT_SPIS_DR1 */
7754  volatile ALT_SPIS_DR2_t DR2; /* ALT_SPIS_DR2 */
7755  volatile ALT_SPIS_DR3_t DR3; /* ALT_SPIS_DR3 */
7756  volatile ALT_SPIS_DR4_t DR4; /* ALT_SPIS_DR4 */
7757  volatile ALT_SPIS_DR5_t DR5; /* ALT_SPIS_DR5 */
7758  volatile ALT_SPIS_DR6_t DR6; /* ALT_SPIS_DR6 */
7759  volatile ALT_SPIS_DR7_t DR7; /* ALT_SPIS_DR7 */
7760  volatile ALT_SPIS_DR8_t DR8; /* ALT_SPIS_DR8 */
7761  volatile ALT_SPIS_DR9_t DR9; /* ALT_SPIS_DR9 */
7762  volatile ALT_SPIS_DR10_t DR10; /* ALT_SPIS_DR10 */
7763  volatile ALT_SPIS_DR11_t DR11; /* ALT_SPIS_DR11 */
7764  volatile ALT_SPIS_DR12_t DR12; /* ALT_SPIS_DR12 */
7765  volatile ALT_SPIS_DR13_t DR13; /* ALT_SPIS_DR13 */
7766  volatile ALT_SPIS_DR14_t DR14; /* ALT_SPIS_DR14 */
7767  volatile ALT_SPIS_DR15_t DR15; /* ALT_SPIS_DR15 */
7768  volatile ALT_SPIS_DR16_t DR16; /* ALT_SPIS_DR16 */
7769  volatile ALT_SPIS_DR17_t DR17; /* ALT_SPIS_DR17 */
7770  volatile ALT_SPIS_DR18_t DR18; /* ALT_SPIS_DR18 */
7771  volatile ALT_SPIS_DR19_t DR19; /* ALT_SPIS_DR19 */
7772  volatile ALT_SPIS_DR20_t DR20; /* ALT_SPIS_DR20 */
7773  volatile ALT_SPIS_DR21_t DR21; /* ALT_SPIS_DR21 */
7774  volatile ALT_SPIS_DR22_t DR22; /* ALT_SPIS_DR22 */
7775  volatile ALT_SPIS_DR23_t DR23; /* ALT_SPIS_DR23 */
7776  volatile ALT_SPIS_DR24_t DR24; /* ALT_SPIS_DR24 */
7777  volatile ALT_SPIS_DR25_t DR25; /* ALT_SPIS_DR25 */
7778  volatile ALT_SPIS_DR26_t DR26; /* ALT_SPIS_DR26 */
7779  volatile ALT_SPIS_DR27_t DR27; /* ALT_SPIS_DR27 */
7780  volatile ALT_SPIS_DR28_t DR28; /* ALT_SPIS_DR28 */
7781  volatile ALT_SPIS_DR29_t DR29; /* ALT_SPIS_DR29 */
7782  volatile ALT_SPIS_DR30_t DR30; /* ALT_SPIS_DR30 */
7783  volatile ALT_SPIS_DR31_t DR31; /* ALT_SPIS_DR31 */
7784  volatile ALT_SPIS_DR32_t DR32; /* ALT_SPIS_DR32 */
7785  volatile ALT_SPIS_DR33_t DR33; /* ALT_SPIS_DR33 */
7786  volatile ALT_SPIS_DR34_t DR34; /* ALT_SPIS_DR34 */
7787  volatile ALT_SPIS_DR35_t DR35; /* ALT_SPIS_DR35 */
7788  volatile uint32_t _pad_0xf0_0xf7[2]; /* *UNDEFINED* */
7789  volatile ALT_SPIS_RSVD_1_t RSVD_1; /* ALT_SPIS_RSVD_1 */
7790  volatile ALT_SPIS_RSVD_2_t RSVD_2; /* ALT_SPIS_RSVD_2 */
7791 };
7792 
7793 /* The typedef declaration for register group ALT_SPIS. */
7794 typedef struct ALT_SPIS_s ALT_SPIS_t;
7795 /* The struct declaration for the raw register contents of register group ALT_SPIS. */
7796 struct ALT_SPIS_raw_s
7797 {
7798  volatile uint32_t CTRLR0; /* ALT_SPIS_CTRLR0 */
7799  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
7800  volatile uint32_t SSIENR; /* ALT_SPIS_SSIENR */
7801  volatile uint32_t MWCR; /* ALT_SPIS_MWCR */
7802  volatile uint32_t _pad_0x10_0x17[2]; /* *UNDEFINED* */
7803  volatile uint32_t TXFTLR; /* ALT_SPIS_TXFTLR */
7804  volatile uint32_t RXFTLR; /* ALT_SPIS_RXFTLR */
7805  volatile uint32_t TXFLR; /* ALT_SPIS_TXFLR */
7806  volatile uint32_t RXFLR; /* ALT_SPIS_RXFLR */
7807  volatile uint32_t SR; /* ALT_SPIS_SR */
7808  volatile uint32_t IMR; /* ALT_SPIS_IMR */
7809  volatile uint32_t ISR; /* ALT_SPIS_ISR */
7810  volatile uint32_t RISR; /* ALT_SPIS_RISR */
7811  volatile uint32_t TXOICR; /* ALT_SPIS_TXOICR */
7812  volatile uint32_t RXOICR; /* ALT_SPIS_RXOICR */
7813  volatile uint32_t RXUICR; /* ALT_SPIS_RXUICR */
7814  volatile uint32_t MSTICR; /* ALT_SPIS_MSTICR */
7815  volatile uint32_t ICR; /* ALT_SPIS_ICR */
7816  volatile uint32_t DMACR; /* ALT_SPIS_DMACR */
7817  volatile uint32_t DMATDLR; /* ALT_SPIS_DMATDLR */
7818  volatile uint32_t DMARDLR; /* ALT_SPIS_DMARDLR */
7819  volatile uint32_t IDR; /* ALT_SPIS_IDR */
7820  volatile uint32_t SSI_VERSION_ID; /* ALT_SPIS_SSI_VERSION_ID */
7821  volatile uint32_t DR0; /* ALT_SPIS_DR0 */
7822  volatile uint32_t DR1; /* ALT_SPIS_DR1 */
7823  volatile uint32_t DR2; /* ALT_SPIS_DR2 */
7824  volatile uint32_t DR3; /* ALT_SPIS_DR3 */
7825  volatile uint32_t DR4; /* ALT_SPIS_DR4 */
7826  volatile uint32_t DR5; /* ALT_SPIS_DR5 */
7827  volatile uint32_t DR6; /* ALT_SPIS_DR6 */
7828  volatile uint32_t DR7; /* ALT_SPIS_DR7 */
7829  volatile uint32_t DR8; /* ALT_SPIS_DR8 */
7830  volatile uint32_t DR9; /* ALT_SPIS_DR9 */
7831  volatile uint32_t DR10; /* ALT_SPIS_DR10 */
7832  volatile uint32_t DR11; /* ALT_SPIS_DR11 */
7833  volatile uint32_t DR12; /* ALT_SPIS_DR12 */
7834  volatile uint32_t DR13; /* ALT_SPIS_DR13 */
7835  volatile uint32_t DR14; /* ALT_SPIS_DR14 */
7836  volatile uint32_t DR15; /* ALT_SPIS_DR15 */
7837  volatile uint32_t DR16; /* ALT_SPIS_DR16 */
7838  volatile uint32_t DR17; /* ALT_SPIS_DR17 */
7839  volatile uint32_t DR18; /* ALT_SPIS_DR18 */
7840  volatile uint32_t DR19; /* ALT_SPIS_DR19 */
7841  volatile uint32_t DR20; /* ALT_SPIS_DR20 */
7842  volatile uint32_t DR21; /* ALT_SPIS_DR21 */
7843  volatile uint32_t DR22; /* ALT_SPIS_DR22 */
7844  volatile uint32_t DR23; /* ALT_SPIS_DR23 */
7845  volatile uint32_t DR24; /* ALT_SPIS_DR24 */
7846  volatile uint32_t DR25; /* ALT_SPIS_DR25 */
7847  volatile uint32_t DR26; /* ALT_SPIS_DR26 */
7848  volatile uint32_t DR27; /* ALT_SPIS_DR27 */
7849  volatile uint32_t DR28; /* ALT_SPIS_DR28 */
7850  volatile uint32_t DR29; /* ALT_SPIS_DR29 */
7851  volatile uint32_t DR30; /* ALT_SPIS_DR30 */
7852  volatile uint32_t DR31; /* ALT_SPIS_DR31 */
7853  volatile uint32_t DR32; /* ALT_SPIS_DR32 */
7854  volatile uint32_t DR33; /* ALT_SPIS_DR33 */
7855  volatile uint32_t DR34; /* ALT_SPIS_DR34 */
7856  volatile uint32_t DR35; /* ALT_SPIS_DR35 */
7857  volatile uint32_t _pad_0xf0_0xf7[2]; /* *UNDEFINED* */
7858  volatile uint32_t RSVD_1; /* ALT_SPIS_RSVD_1 */
7859  volatile uint32_t RSVD_2; /* ALT_SPIS_RSVD_2 */
7860 };
7861 
7862 /* The typedef declaration for the raw register contents of register group ALT_SPIS. */
7863 typedef struct ALT_SPIS_raw_s ALT_SPIS_raw_t;
7864 #endif /* __ASSEMBLY__ */
7865 
7866 
7867 #ifdef __cplusplus
7868 }
7869 #endif /* __cplusplus */
7870 #endif /* __ALT_SOCAL_SPIS_H__ */
7871