Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_l4_priv_flt.h
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32 
33 /* Altera - ALT_NOC_L4_PRIV_FLT */
34 
35 #ifndef __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
36 #define __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_L4_PRIV_FLT
50  *
51  */
52 /*
53  * Register : l4_priv
54  *
55  * This register controls access to various Peripherals depending on the privilege
56  * setting. By default, all slaves will be assumed as Privileged. To allow non-
57  * Privileged access to a slave, the corresponding bit for the slave must be set.
58  * Once set, both Privilege and non-Privileged transactions are allowed to the
59  * Slave. Note that the privilege filter only checks for transaction Privilege
60  * level, transaction Security is left to Firewalls. Firewalls therefore may still
61  * block transaction to Peripherals depending on Security configurations.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :-----|:-------|:--------|:------------------------------------------
67  * [0] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG
68  * [1] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA
69  * [2] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA
70  * [3] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG
71  * [4] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG
72  * [5] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE
73  * [6] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE
74  * [7] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0
75  * [8] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1
76  * [9] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0
77  * [10] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1
78  * [11] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0
79  * [12] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1
80  * [13] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2
81  * [14] | RW | Unknown | ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3
82  * [15] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI
83  * [16] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC
84  * [17] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0
85  * [18] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1
86  * [19] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2
87  * [20] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0
88  * [21] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1
89  * [22] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2
90  * [23] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3
91  * [24] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4
92  * [25] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0
93  * [26] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1
94  * [27] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0
95  * [28] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1
96  * [29] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F
97  * [30] | RW | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F
98  * [31] | ??? | Unknown | *UNDEFINED*
99  *
100  */
101 /*
102  * Field : nand_register
103  *
104  * Privilege bit for nand register. When 0, only privileged transactions are
105  * allowed to slave. When 1, both privileged and non-privileged transactions are
106  * allowed to slave
107  *
108  * Field Access Macros:
109  *
110  */
111 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field. */
112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_LSB 0
113 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field. */
114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_MSB 0
115 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field. */
116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_WIDTH 1
117 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value. */
118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET_MSK 0x00000001
119 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value. */
120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_CLR_MSK 0xfffffffe
121 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field. */
122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_RESET 0x0
123 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG field value from a register. */
124 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
125 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value suitable for setting the register. */
126 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
127 
128 /*
129  * Field : nand_data
130  *
131  * Privilege bit for nand_data. When 0, only privileged transactions are allowed to
132  * slave. When 1, both privileged and non-privileged transactions are allowed to
133  * slave
134  *
135  * Field Access Macros:
136  *
137  */
138 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field. */
139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_LSB 1
140 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field. */
141 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_MSB 1
142 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field. */
143 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_WIDTH 1
144 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value. */
145 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET_MSK 0x00000002
146 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value. */
147 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_CLR_MSK 0xfffffffd
148 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field. */
149 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_RESET 0x0
150 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA field value from a register. */
151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
152 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value suitable for setting the register. */
153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
154 
155 /*
156  * Field : qspi_data
157  *
158  * Privilege bit for qspi_data. When 0, only privileged transactions are allowed to
159  * slave. When 1, both privileged and non-privileged transactions are allowed to
160  * slave
161  *
162  * Field Access Macros:
163  *
164  */
165 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field. */
166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_LSB 2
167 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field. */
168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_MSB 2
169 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field. */
170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_WIDTH 1
171 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value. */
172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET_MSK 0x00000004
173 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value. */
174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_CLR_MSK 0xfffffffb
175 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field. */
176 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_RESET 0x0
177 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA field value from a register. */
178 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
179 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value suitable for setting the register. */
180 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
181 
182 /*
183  * Field : usb0_register
184  *
185  * Privilege bit for usb0_register. When 0, only privileged transactions are
186  * allowed to slave. When 1, both privileged and non-privileged transactions are
187  * allowed to slave
188  *
189  * Field Access Macros:
190  *
191  */
192 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field. */
193 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_LSB 3
194 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field. */
195 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_MSB 3
196 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field. */
197 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_WIDTH 1
198 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value. */
199 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET_MSK 0x00000008
200 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value. */
201 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_CLR_MSK 0xfffffff7
202 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field. */
203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_RESET 0x0
204 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG field value from a register. */
205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
206 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value suitable for setting the register. */
207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
208 
209 /*
210  * Field : usb1_register
211  *
212  * Privilege bit for usb1_register. When 0, only privileged transactions are
213  * allowed to slave. When 1, both privileged and non-privileged transactions are
214  * allowed to slave
215  *
216  * Field Access Macros:
217  *
218  */
219 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field. */
220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_LSB 4
221 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field. */
222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_MSB 4
223 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field. */
224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_WIDTH 1
225 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value. */
226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET_MSK 0x00000010
227 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value. */
228 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_CLR_MSK 0xffffffef
229 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field. */
230 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_RESET 0x0
231 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG field value from a register. */
232 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
233 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value suitable for setting the register. */
234 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
235 
236 /*
237  * Field : dma_nonsecure
238  *
239  * Privilege bit for dma_nonsecure. When 0, only privileged transactions are
240  * allowed to slave. When 1, both privileged and non-privileged transactions are
241  * allowed to slave
242  *
243  * Field Access Macros:
244  *
245  */
246 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field. */
247 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_LSB 5
248 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field. */
249 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_MSB 5
250 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field. */
251 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_WIDTH 1
252 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value. */
253 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET_MSK 0x00000020
254 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value. */
255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_CLR_MSK 0xffffffdf
256 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field. */
257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_RESET 0x0
258 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE field value from a register. */
259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
260 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value suitable for setting the register. */
261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
262 
263 /*
264  * Field : dma_secure
265  *
266  * Privilege bit for dma_secure. When 0, only privileged transactions are allowed
267  * to slave. When 1, both privileged and non-privileged transactions are allowed to
268  * slave
269  *
270  * Field Access Macros:
271  *
272  */
273 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field. */
274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_LSB 6
275 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field. */
276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_MSB 6
277 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field. */
278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_WIDTH 1
279 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value. */
280 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET_MSK 0x00000040
281 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value. */
282 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_CLR_MSK 0xffffffbf
283 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field. */
284 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_RESET 0x0
285 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE field value from a register. */
286 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
287 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value suitable for setting the register. */
288 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
289 
290 /*
291  * Field : spi_master0
292  *
293  * Privilege bit for spi_master0. When 0, only privileged transactions are allowed
294  * to slave. When 1, both privileged and non-privileged transactions are allowed to
295  * slave
296  *
297  * Field Access Macros:
298  *
299  */
300 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field. */
301 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_LSB 7
302 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field. */
303 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_MSB 7
304 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field. */
305 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_WIDTH 1
306 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value. */
307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET_MSK 0x00000080
308 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value. */
309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_CLR_MSK 0xffffff7f
310 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field. */
311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_RESET 0x0
312 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 field value from a register. */
313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
314 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value suitable for setting the register. */
315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
316 
317 /*
318  * Field : spi_master1
319  *
320  * Privilege bit for spi_master1. When 0, only privileged transactions are allowed
321  * to slave. When 1, both privileged and non-privileged transactions are allowed to
322  * slave
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field. */
328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_LSB 8
329 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field. */
330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_MSB 8
331 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field. */
332 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_WIDTH 1
333 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value. */
334 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET_MSK 0x00000100
335 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value. */
336 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_CLR_MSK 0xfffffeff
337 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field. */
338 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_RESET 0x0
339 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 field value from a register. */
340 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
341 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value suitable for setting the register. */
342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
343 
344 /*
345  * Field : spi_slave0
346  *
347  * Privilege bit for spi_slave0. When 0, only privileged transactions are allowed
348  * to slave. When 1, both privileged and non-privileged transactions are allowed to
349  * slave
350  *
351  * Field Access Macros:
352  *
353  */
354 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field. */
355 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_LSB 9
356 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field. */
357 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_MSB 9
358 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field. */
359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_WIDTH 1
360 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value. */
361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET_MSK 0x00000200
362 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value. */
363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_CLR_MSK 0xfffffdff
364 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field. */
365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_RESET 0x0
366 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 field value from a register. */
367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
368 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value suitable for setting the register. */
369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
370 
371 /*
372  * Field : spi_slave1
373  *
374  * Privilege bit for spi_slave1. When 0, only privileged transactions are allowed
375  * to slave. When 1, both privileged and non-privileged transactions are allowed to
376  * slave
377  *
378  * Field Access Macros:
379  *
380  */
381 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field. */
382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_LSB 10
383 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field. */
384 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_MSB 10
385 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field. */
386 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_WIDTH 1
387 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value. */
388 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET_MSK 0x00000400
389 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value. */
390 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_CLR_MSK 0xfffffbff
391 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field. */
392 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_RESET 0x0
393 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 field value from a register. */
394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
395 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value suitable for setting the register. */
396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
397 
398 /*
399  * Field : emac0
400  *
401  * Privilege bit for emac0. When 0, only privileged transactions are allowed to
402  * slave. When 1, both privileged and non-privileged transactions are allowed to
403  * slave
404  *
405  * Field Access Macros:
406  *
407  */
408 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field. */
409 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_LSB 11
410 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field. */
411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_MSB 11
412 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field. */
413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_WIDTH 1
414 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value. */
415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET_MSK 0x00000800
416 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value. */
417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_CLR_MSK 0xfffff7ff
418 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field. */
419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_RESET 0x0
420 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 field value from a register. */
421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
422 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value suitable for setting the register. */
423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET(value) (((value) << 11) & 0x00000800)
424 
425 /*
426  * Field : emac1
427  *
428  * Privilege bit for emac1. When 0, only privileged transactions are allowed to
429  * slave. When 1, both privileged and non-privileged transactions are allowed to
430  * slave
431  *
432  * Field Access Macros:
433  *
434  */
435 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field. */
436 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_LSB 12
437 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field. */
438 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_MSB 12
439 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field. */
440 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_WIDTH 1
441 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value. */
442 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET_MSK 0x00001000
443 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value. */
444 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_CLR_MSK 0xffffefff
445 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field. */
446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_RESET 0x0
447 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 field value from a register. */
448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
449 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value suitable for setting the register. */
450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET(value) (((value) << 12) & 0x00001000)
451 
452 /*
453  * Field : emac2
454  *
455  * Privilege bit for emac2. When 0, only privileged transactions are allowed to
456  * slave. When 1, both privileged and non-privileged transactions are allowed to
457  * slave
458  *
459  * Field Access Macros:
460  *
461  */
462 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field. */
463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_LSB 13
464 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field. */
465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_MSB 13
466 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field. */
467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_WIDTH 1
468 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value. */
469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET_MSK 0x00002000
470 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value. */
471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_CLR_MSK 0xffffdfff
472 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field. */
473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_RESET 0x0
474 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 field value from a register. */
475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
476 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value suitable for setting the register. */
477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET(value) (((value) << 13) & 0x00002000)
478 
479 /*
480  * Field : emac3
481  *
482  * Privilege bit for emac3. When 0, only privileged transactions are allowed to
483  * slave. When 1, both privileged and non-privileged transactions are allowed to
484  * slave
485  *
486  * Field Access Macros:
487  *
488  */
489 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field. */
490 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_LSB 14
491 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field. */
492 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_MSB 14
493 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field. */
494 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_WIDTH 1
495 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value. */
496 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET_MSK 0x00004000
497 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value. */
498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_CLR_MSK 0xffffbfff
499 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field is UNKNOWN. */
500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_RESET 0x0
501 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 field value from a register. */
502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
503 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value suitable for setting the register. */
504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET(value) (((value) << 14) & 0x00004000)
505 
506 /*
507  * Field : qspi
508  *
509  * Privilege bit for qspi. When 0, only privileged transactions are allowed to
510  * slave. When 1, both privileged and non-privileged transactions are allowed to
511  * slave
512  *
513  * Field Access Macros:
514  *
515  */
516 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field. */
517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_LSB 15
518 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field. */
519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_MSB 15
520 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field. */
521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_WIDTH 1
522 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value. */
523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET_MSK 0x00008000
524 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value. */
525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_CLR_MSK 0xffff7fff
526 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field. */
527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_RESET 0x0
528 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI field value from a register. */
529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_GET(value) (((value) & 0x00008000) >> 15)
530 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value suitable for setting the register. */
531 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET(value) (((value) << 15) & 0x00008000)
532 
533 /*
534  * Field : sdmmc
535  *
536  * Privilege bit for sdmmc. When 0, only privileged transactions are allowed to
537  * slave. When 1, both privileged and non-privileged transactions are allowed to
538  * slave
539  *
540  * Field Access Macros:
541  *
542  */
543 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field. */
544 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_LSB 16
545 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field. */
546 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_MSB 16
547 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field. */
548 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_WIDTH 1
549 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value. */
550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET_MSK 0x00010000
551 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value. */
552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_CLR_MSK 0xfffeffff
553 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field. */
554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_RESET 0x0
555 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC field value from a register. */
556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
557 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value suitable for setting the register. */
558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET(value) (((value) << 16) & 0x00010000)
559 
560 /*
561  * Field : gpio0
562  *
563  * Privilege bit for gpio0. When 0, only privileged transactions are allowed to
564  * slave. When 1, both privileged and non-privileged transactions are allowed to
565  * slave
566  *
567  * Field Access Macros:
568  *
569  */
570 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field. */
571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_LSB 17
572 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field. */
573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_MSB 17
574 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field. */
575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_WIDTH 1
576 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value. */
577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET_MSK 0x00020000
578 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value. */
579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_CLR_MSK 0xfffdffff
580 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field. */
581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_RESET 0x0
582 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 field value from a register. */
583 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
584 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value suitable for setting the register. */
585 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET(value) (((value) << 17) & 0x00020000)
586 
587 /*
588  * Field : gpio1
589  *
590  * Privilege bit for gpio1. When 0, only privileged transactions are allowed to
591  * slave. When 1, both privileged and non-privileged transactions are allowed to
592  * slave
593  *
594  * Field Access Macros:
595  *
596  */
597 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field. */
598 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_LSB 18
599 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field. */
600 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_MSB 18
601 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field. */
602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_WIDTH 1
603 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value. */
604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET_MSK 0x00040000
605 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value. */
606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_CLR_MSK 0xfffbffff
607 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field. */
608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_RESET 0x0
609 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 field value from a register. */
610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
611 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value suitable for setting the register. */
612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET(value) (((value) << 18) & 0x00040000)
613 
614 /*
615  * Field : gpio2
616  *
617  * Privilege bit for gpio2. When 0, only privileged transactions are allowed to
618  * slave. When 1, both privileged and non-privileged transactions are allowed to
619  * slave
620  *
621  * Field Access Macros:
622  *
623  */
624 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field. */
625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_LSB 19
626 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field. */
627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_MSB 19
628 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field. */
629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_WIDTH 1
630 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value. */
631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET_MSK 0x00080000
632 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value. */
633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_CLR_MSK 0xfff7ffff
634 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field. */
635 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_RESET 0x0
636 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 field value from a register. */
637 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
638 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value suitable for setting the register. */
639 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET(value) (((value) << 19) & 0x00080000)
640 
641 /*
642  * Field : i2c0
643  *
644  * Privilege bit for i2c0. When 0, only privileged transactions are allowed to
645  * slave. When 1, both privileged and non-privileged transactions are allowed to
646  * slave
647  *
648  * Field Access Macros:
649  *
650  */
651 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field. */
652 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_LSB 20
653 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field. */
654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_MSB 20
655 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field. */
656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_WIDTH 1
657 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value. */
658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET_MSK 0x00100000
659 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value. */
660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_CLR_MSK 0xffefffff
661 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field. */
662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_RESET 0x0
663 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 field value from a register. */
664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_GET(value) (((value) & 0x00100000) >> 20)
665 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value suitable for setting the register. */
666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET(value) (((value) << 20) & 0x00100000)
667 
668 /*
669  * Field : i2c1
670  *
671  * Privilege bit for i2c1. When 0, only privileged transactions are allowed to
672  * slave. When 1, both privileged and non-privileged transactions are allowed to
673  * slave
674  *
675  * Field Access Macros:
676  *
677  */
678 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field. */
679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_LSB 21
680 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field. */
681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_MSB 21
682 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field. */
683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_WIDTH 1
684 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value. */
685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET_MSK 0x00200000
686 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value. */
687 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_CLR_MSK 0xffdfffff
688 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field. */
689 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_RESET 0x0
690 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 field value from a register. */
691 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_GET(value) (((value) & 0x00200000) >> 21)
692 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value suitable for setting the register. */
693 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET(value) (((value) << 21) & 0x00200000)
694 
695 /*
696  * Field : i2c2
697  *
698  * Privilege bit for i2c2. When 0, only privileged transactions are allowed to
699  * slave. When 1, both privileged and non-privileged transactions are allowed to
700  * slave
701  *
702  * Field Access Macros:
703  *
704  */
705 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field. */
706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_LSB 22
707 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field. */
708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_MSB 22
709 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field. */
710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_WIDTH 1
711 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value. */
712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET_MSK 0x00400000
713 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value. */
714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_CLR_MSK 0xffbfffff
715 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field. */
716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_RESET 0x0
717 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 field value from a register. */
718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_GET(value) (((value) & 0x00400000) >> 22)
719 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value suitable for setting the register. */
720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET(value) (((value) << 22) & 0x00400000)
721 
722 /*
723  * Field : i2c3
724  *
725  * Privilege bit for i2c3. When 0, only privileged transactions are allowed to
726  * slave. When 1, both privileged and non-privileged transactions are allowed to
727  * slave
728  *
729  * Field Access Macros:
730  *
731  */
732 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field. */
733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_LSB 23
734 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field. */
735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_MSB 23
736 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field. */
737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_WIDTH 1
738 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value. */
739 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET_MSK 0x00800000
740 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value. */
741 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_CLR_MSK 0xff7fffff
742 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field. */
743 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_RESET 0x0
744 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 field value from a register. */
745 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_GET(value) (((value) & 0x00800000) >> 23)
746 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value suitable for setting the register. */
747 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET(value) (((value) << 23) & 0x00800000)
748 
749 /*
750  * Field : i2c4
751  *
752  * Privilege bit for i2c4. When 0, only privileged transactions are allowed to
753  * slave. When 1, both privileged and non-privileged transactions are allowed to
754  * slave
755  *
756  * Field Access Macros:
757  *
758  */
759 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field. */
760 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_LSB 24
761 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field. */
762 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_MSB 24
763 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field. */
764 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_WIDTH 1
765 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value. */
766 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET_MSK 0x01000000
767 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value. */
768 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_CLR_MSK 0xfeffffff
769 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field. */
770 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_RESET 0x0
771 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 field value from a register. */
772 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_GET(value) (((value) & 0x01000000) >> 24)
773 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value suitable for setting the register. */
774 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET(value) (((value) << 24) & 0x01000000)
775 
776 /*
777  * Field : sp_timer0
778  *
779  * Privilege bit for sp_timer0. When 0, only privileged transactions are allowed to
780  * slave. When 1, both privileged and non-privileged transactions are allowed to
781  * slave
782  *
783  * Field Access Macros:
784  *
785  */
786 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field. */
787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_LSB 25
788 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field. */
789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_MSB 25
790 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field. */
791 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_WIDTH 1
792 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value. */
793 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET_MSK 0x02000000
794 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value. */
795 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_CLR_MSK 0xfdffffff
796 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field. */
797 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_RESET 0x0
798 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 field value from a register. */
799 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
800 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value suitable for setting the register. */
801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
802 
803 /*
804  * Field : sp_timer1
805  *
806  * Privilege bit for sp_timer1. When 0, only privileged transactions are allowed to
807  * slave. When 1, both privileged and non-privileged transactions are allowed to
808  * slave
809  *
810  * Field Access Macros:
811  *
812  */
813 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field. */
814 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_LSB 26
815 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field. */
816 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_MSB 26
817 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field. */
818 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_WIDTH 1
819 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value. */
820 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET_MSK 0x04000000
821 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value. */
822 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_CLR_MSK 0xfbffffff
823 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field. */
824 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_RESET 0x0
825 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 field value from a register. */
826 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
827 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value suitable for setting the register. */
828 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
829 
830 /*
831  * Field : uart0
832  *
833  * Privilege bit for uart0. When 0, only privileged transactions are allowed to
834  * slave. When 1, both privileged and non-privileged transactions are allowed to
835  * slave
836  *
837  * Field Access Macros:
838  *
839  */
840 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field. */
841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_LSB 27
842 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field. */
843 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_MSB 27
844 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field. */
845 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_WIDTH 1
846 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value. */
847 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET_MSK 0x08000000
848 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value. */
849 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_CLR_MSK 0xf7ffffff
850 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field. */
851 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_RESET 0x0
852 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 field value from a register. */
853 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_GET(value) (((value) & 0x08000000) >> 27)
854 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value suitable for setting the register. */
855 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET(value) (((value) << 27) & 0x08000000)
856 
857 /*
858  * Field : uart1
859  *
860  * Privilege bit for uart1. When 0, only privileged transactions are allowed to
861  * slave. When 1, both privileged and non-privileged transactions are allowed to
862  * slave
863  *
864  * Field Access Macros:
865  *
866  */
867 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field. */
868 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_LSB 28
869 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field. */
870 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_MSB 28
871 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field. */
872 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_WIDTH 1
873 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value. */
874 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET_MSK 0x10000000
875 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value. */
876 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_CLR_MSK 0xefffffff
877 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field. */
878 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_RESET 0x0
879 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 field value from a register. */
880 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_GET(value) (((value) & 0x10000000) >> 28)
881 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value suitable for setting the register. */
882 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET(value) (((value) << 28) & 0x10000000)
883 
884 /*
885  * Field : lwsoc2fpga
886  *
887  * Privilege bit for Lightweight SOC2FPGA. When 0, only privileged transactions are
888  * allowed to slave. When 1, both privileged and non-privileged transactions are
889  * allowed to slave
890  *
891  * Field Access Macros:
892  *
893  */
894 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field. */
895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_LSB 29
896 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field. */
897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_MSB 29
898 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field. */
899 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_WIDTH 1
900 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value. */
901 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET_MSK 0x20000000
902 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value. */
903 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_CLR_MSK 0xdfffffff
904 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field. */
905 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_RESET 0x0
906 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F field value from a register. */
907 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
908 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value suitable for setting the register. */
909 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET(value) (((value) << 29) & 0x20000000)
910 
911 /*
912  * Field : soc2fpga
913  *
914  * Privilege bit for SOC2FPGA. When 0, only privileged transactions are allowed to
915  * slave. When 1, both privileged and non-privileged transactions are allowed to
916  * slave
917  *
918  * Field Access Macros:
919  *
920  */
921 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field. */
922 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_LSB 30
923 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field. */
924 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_MSB 30
925 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field. */
926 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_WIDTH 1
927 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value. */
928 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET_MSK 0x40000000
929 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value. */
930 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_CLR_MSK 0xbfffffff
931 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field. */
932 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_RESET 0x0
933 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F field value from a register. */
934 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_GET(value) (((value) & 0x40000000) >> 30)
935 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value suitable for setting the register. */
936 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET(value) (((value) << 30) & 0x40000000)
937 
938 #ifndef __ASSEMBLY__
939 /*
940  * WARNING: The C register and register group struct declarations are provided for
941  * convenience and illustrative purposes. They should, however, be used with
942  * caution as the C language standard provides no guarantees about the alignment or
943  * atomicity of device memory accesses. The recommended practice for writing
944  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
945  * alt_write_word() functions.
946  *
947  * The struct declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV.
948  */
949 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_s
950 {
951  uint32_t nand_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG */
952  uint32_t nand_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA */
953  uint32_t qspi_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA */
954  uint32_t usb0_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG */
955  uint32_t usb1_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG */
956  uint32_t dma_nonsecure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE */
957  uint32_t dma_secure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE */
958  uint32_t spi_master0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 */
959  uint32_t spi_master1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 */
960  uint32_t spi_slave0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 */
961  uint32_t spi_slave1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 */
962  uint32_t emac0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 */
963  uint32_t emac1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 */
964  uint32_t emac2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 */
965  uint32_t emac3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 */
966  uint32_t qspi : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI */
967  uint32_t sdmmc : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC */
968  uint32_t gpio0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 */
969  uint32_t gpio1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 */
970  uint32_t gpio2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 */
971  uint32_t i2c0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 */
972  uint32_t i2c1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 */
973  uint32_t i2c2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 */
974  uint32_t i2c3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 */
975  uint32_t i2c4 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 */
976  uint32_t sp_timer0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 */
977  uint32_t sp_timer1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 */
978  uint32_t uart0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 */
979  uint32_t uart1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 */
980  uint32_t lwsoc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F */
981  uint32_t soc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F */
982  uint32_t : 1; /* *UNDEFINED* */
983 };
984 
985 /* The typedef declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV. */
986 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_t;
987 #endif /* __ASSEMBLY__ */
988 
989 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV register. */
990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_RESET 0x00000000
991 /* The byte offset of the ALT_NOC_L4_PRIV_FLT_L4_PRIV register from the beginning of the component. */
992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_OFST 0x0
993 
994 /*
995  * Register : l4_priv_set
996  *
997  * Sets Region Enable field when written with 1
998  *
999  * Register Layout
1000  *
1001  * Bits | Access | Reset | Description
1002  * :-----|:-------|:--------|:----------------------------------------------
1003  * [0] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG
1004  * [1] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA
1005  * [2] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA
1006  * [3] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG
1007  * [4] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG
1008  * [5] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE
1009  * [6] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE
1010  * [7] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0
1011  * [8] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1
1012  * [9] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0
1013  * [10] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1
1014  * [11] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0
1015  * [12] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1
1016  * [13] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2
1017  * [14] | RW | Unknown | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3
1018  * [15] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI
1019  * [16] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC
1020  * [17] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0
1021  * [18] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1
1022  * [19] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2
1023  * [20] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0
1024  * [21] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1
1025  * [22] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2
1026  * [23] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3
1027  * [24] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4
1028  * [25] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0
1029  * [26] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1
1030  * [27] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0
1031  * [28] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1
1032  * [29] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F
1033  * [30] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F
1034  * [31] | ??? | Unknown | *UNDEFINED*
1035  *
1036  */
1037 /*
1038  * Field : nand_register
1039  *
1040  * Privilege bit for nand register. Writing zero has no effect. Writing one will
1041  * set the privilege bit
1042  *
1043  * Field Access Macros:
1044  *
1045  */
1046 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field. */
1047 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_LSB 0
1048 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field. */
1049 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_MSB 0
1050 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field. */
1051 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_WIDTH 1
1052 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field value. */
1053 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET_MSK 0x00000001
1054 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field value. */
1055 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_CLR_MSK 0xfffffffe
1056 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field. */
1057 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_RESET 0x0
1058 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG field value from a register. */
1059 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1060 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG register field value suitable for setting the register. */
1061 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1062 
1063 /*
1064  * Field : nand_data
1065  *
1066  * Privilege bit for nand_data. Writing zero has no effect. Writing one will set
1067  * the privilege bit
1068  *
1069  * Field Access Macros:
1070  *
1071  */
1072 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field. */
1073 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_LSB 1
1074 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field. */
1075 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_MSB 1
1076 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field. */
1077 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_WIDTH 1
1078 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field value. */
1079 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET_MSK 0x00000002
1080 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field value. */
1081 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_CLR_MSK 0xfffffffd
1082 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field. */
1083 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_RESET 0x0
1084 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA field value from a register. */
1085 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1086 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA register field value suitable for setting the register. */
1087 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1088 
1089 /*
1090  * Field : qspi_data
1091  *
1092  * Privilege bit for qspi_data. Writing zero has no effect. Writing one will set
1093  * the privilege bit
1094  *
1095  * Field Access Macros:
1096  *
1097  */
1098 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field. */
1099 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_LSB 2
1100 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field. */
1101 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_MSB 2
1102 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field. */
1103 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_WIDTH 1
1104 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field value. */
1105 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET_MSK 0x00000004
1106 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field value. */
1107 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_CLR_MSK 0xfffffffb
1108 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field. */
1109 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_RESET 0x0
1110 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA field value from a register. */
1111 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
1112 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA register field value suitable for setting the register. */
1113 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
1114 
1115 /*
1116  * Field : usb0_register
1117  *
1118  * Privilege bit for usb0_register. Writing zero has no effect. Writing one will
1119  * set the privilege bit
1120  *
1121  * Field Access Macros:
1122  *
1123  */
1124 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field. */
1125 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_LSB 3
1126 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field. */
1127 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_MSB 3
1128 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field. */
1129 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_WIDTH 1
1130 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field value. */
1131 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET_MSK 0x00000008
1132 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field value. */
1133 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_CLR_MSK 0xfffffff7
1134 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field. */
1135 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_RESET 0x0
1136 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG field value from a register. */
1137 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
1138 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG register field value suitable for setting the register. */
1139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
1140 
1141 /*
1142  * Field : usb1_register
1143  *
1144  * Privilege bit for usb1_register. Writing zero has no effect. Writing one will
1145  * set the privilege bit
1146  *
1147  * Field Access Macros:
1148  *
1149  */
1150 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field. */
1151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_LSB 4
1152 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field. */
1153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_MSB 4
1154 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field. */
1155 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_WIDTH 1
1156 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field value. */
1157 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET_MSK 0x00000010
1158 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field value. */
1159 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_CLR_MSK 0xffffffef
1160 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field. */
1161 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_RESET 0x0
1162 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG field value from a register. */
1163 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
1164 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG register field value suitable for setting the register. */
1165 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
1166 
1167 /*
1168  * Field : dma_nonsecure
1169  *
1170  * Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will
1171  * set the privilege bit
1172  *
1173  * Field Access Macros:
1174  *
1175  */
1176 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field. */
1177 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_LSB 5
1178 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field. */
1179 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_MSB 5
1180 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field. */
1181 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_WIDTH 1
1182 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field value. */
1183 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET_MSK 0x00000020
1184 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field value. */
1185 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_CLR_MSK 0xffffffdf
1186 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field. */
1187 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_RESET 0x0
1188 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE field value from a register. */
1189 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1190 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE register field value suitable for setting the register. */
1191 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1192 
1193 /*
1194  * Field : dma_secure
1195  *
1196  * Privilege bit for dma_secure. Writing zero has no effect. Writing one will set
1197  * the privilege bit
1198  *
1199  * Field Access Macros:
1200  *
1201  */
1202 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field. */
1203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_LSB 6
1204 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field. */
1205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_MSB 6
1206 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field. */
1207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_WIDTH 1
1208 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field value. */
1209 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET_MSK 0x00000040
1210 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field value. */
1211 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_CLR_MSK 0xffffffbf
1212 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field. */
1213 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_RESET 0x0
1214 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE field value from a register. */
1215 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1216 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE register field value suitable for setting the register. */
1217 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1218 
1219 /*
1220  * Field : spi_master0
1221  *
1222  * Privilege bit for spi_master0. Writing zero has no effect. Writing one will set
1223  * the privilege bit
1224  *
1225  * Field Access Macros:
1226  *
1227  */
1228 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field. */
1229 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_LSB 7
1230 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field. */
1231 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_MSB 7
1232 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field. */
1233 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_WIDTH 1
1234 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field value. */
1235 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET_MSK 0x00000080
1236 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field value. */
1237 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_CLR_MSK 0xffffff7f
1238 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field. */
1239 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_RESET 0x0
1240 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 field value from a register. */
1241 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
1242 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 register field value suitable for setting the register. */
1243 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
1244 
1245 /*
1246  * Field : spi_master1
1247  *
1248  * Privilege bit for spi_master1. Writing zero has no effect. Writing one will set
1249  * the privilege bit
1250  *
1251  * Field Access Macros:
1252  *
1253  */
1254 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field. */
1255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_LSB 8
1256 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field. */
1257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_MSB 8
1258 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field. */
1259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_WIDTH 1
1260 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field value. */
1261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET_MSK 0x00000100
1262 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field value. */
1263 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_CLR_MSK 0xfffffeff
1264 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field. */
1265 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_RESET 0x0
1266 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 field value from a register. */
1267 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
1268 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 register field value suitable for setting the register. */
1269 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
1270 
1271 /*
1272  * Field : spi_slave0
1273  *
1274  * Privilege bit for spi_slave0. Writing zero has no effect. Writing one will set
1275  * the privilege bit
1276  *
1277  * Field Access Macros:
1278  *
1279  */
1280 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field. */
1281 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_LSB 9
1282 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field. */
1283 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_MSB 9
1284 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field. */
1285 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_WIDTH 1
1286 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field value. */
1287 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET_MSK 0x00000200
1288 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field value. */
1289 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_CLR_MSK 0xfffffdff
1290 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field. */
1291 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_RESET 0x0
1292 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 field value from a register. */
1293 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
1294 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 register field value suitable for setting the register. */
1295 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
1296 
1297 /*
1298  * Field : spi_slave1
1299  *
1300  * Privilege bit for spi_slave1. Writing zero has no effect. Writing one will set
1301  * the privilege bit
1302  *
1303  * Field Access Macros:
1304  *
1305  */
1306 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field. */
1307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_LSB 10
1308 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field. */
1309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_MSB 10
1310 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field. */
1311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_WIDTH 1
1312 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field value. */
1313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET_MSK 0x00000400
1314 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field value. */
1315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_CLR_MSK 0xfffffbff
1316 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field. */
1317 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_RESET 0x0
1318 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 field value from a register. */
1319 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
1320 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 register field value suitable for setting the register. */
1321 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
1322 
1323 /*
1324  * Field : emac0
1325  *
1326  * Privilege bit for emac0. Writing zero has no effect. Writing one will set the
1327  * privilege bit
1328  *
1329  * Field Access Macros:
1330  *
1331  */
1332 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field. */
1333 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_LSB 11
1334 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field. */
1335 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_MSB 11
1336 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field. */
1337 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_WIDTH 1
1338 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field value. */
1339 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET_MSK 0x00000800
1340 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field value. */
1341 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_CLR_MSK 0xfffff7ff
1342 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field. */
1343 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_RESET 0x0
1344 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 field value from a register. */
1345 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
1346 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 register field value suitable for setting the register. */
1347 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET(value) (((value) << 11) & 0x00000800)
1348 
1349 /*
1350  * Field : emac1
1351  *
1352  * Privilege bit for emac1. Writing zero has no effect. Writing one will set the
1353  * privilege bit
1354  *
1355  * Field Access Macros:
1356  *
1357  */
1358 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field. */
1359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_LSB 12
1360 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field. */
1361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_MSB 12
1362 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field. */
1363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_WIDTH 1
1364 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field value. */
1365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET_MSK 0x00001000
1366 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field value. */
1367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_CLR_MSK 0xffffefff
1368 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field. */
1369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_RESET 0x0
1370 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 field value from a register. */
1371 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
1372 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 register field value suitable for setting the register. */
1373 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET(value) (((value) << 12) & 0x00001000)
1374 
1375 /*
1376  * Field : emac2
1377  *
1378  * Privilege bit for emac2. Writing zero has no effect. Writing one will set the
1379  * privilege bit
1380  *
1381  * Field Access Macros:
1382  *
1383  */
1384 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field. */
1385 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_LSB 13
1386 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field. */
1387 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_MSB 13
1388 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field. */
1389 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_WIDTH 1
1390 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field value. */
1391 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET_MSK 0x00002000
1392 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field value. */
1393 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_CLR_MSK 0xffffdfff
1394 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field. */
1395 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_RESET 0x0
1396 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 field value from a register. */
1397 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
1398 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 register field value suitable for setting the register. */
1399 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET(value) (((value) << 13) & 0x00002000)
1400 
1401 /*
1402  * Field : emac3
1403  *
1404  * Privilege bit for emac3. Writing zero has no effect. Writing one will set the
1405  * privilege bit
1406  *
1407  * Field Access Macros:
1408  *
1409  */
1410 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field. */
1411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_LSB 14
1412 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field. */
1413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_MSB 14
1414 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field. */
1415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_WIDTH 1
1416 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field value. */
1417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET_MSK 0x00004000
1418 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field value. */
1419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_CLR_MSK 0xffffbfff
1420 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field is UNKNOWN. */
1421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_RESET 0x0
1422 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 field value from a register. */
1423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
1424 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 register field value suitable for setting the register. */
1425 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET(value) (((value) << 14) & 0x00004000)
1426 
1427 /*
1428  * Field : qspi
1429  *
1430  * Privilege bit for qspi. Writing zero has no effect. Writing one will set the
1431  * privilege bit
1432  *
1433  * Field Access Macros:
1434  *
1435  */
1436 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field. */
1437 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_LSB 15
1438 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field. */
1439 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_MSB 15
1440 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field. */
1441 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_WIDTH 1
1442 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field value. */
1443 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET_MSK 0x00008000
1444 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field value. */
1445 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_CLR_MSK 0xffff7fff
1446 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field. */
1447 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_RESET 0x0
1448 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI field value from a register. */
1449 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_GET(value) (((value) & 0x00008000) >> 15)
1450 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI register field value suitable for setting the register. */
1451 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET(value) (((value) << 15) & 0x00008000)
1452 
1453 /*
1454  * Field : sdmmc
1455  *
1456  * Privilege bit for sdmmc. Writing zero has no effect. Writing one will set the
1457  * privilege bit
1458  *
1459  * Field Access Macros:
1460  *
1461  */
1462 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field. */
1463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_LSB 16
1464 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field. */
1465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_MSB 16
1466 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field. */
1467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_WIDTH 1
1468 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field value. */
1469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET_MSK 0x00010000
1470 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field value. */
1471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_CLR_MSK 0xfffeffff
1472 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field. */
1473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_RESET 0x0
1474 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC field value from a register. */
1475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
1476 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC register field value suitable for setting the register. */
1477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET(value) (((value) << 16) & 0x00010000)
1478 
1479 /*
1480  * Field : gpio0
1481  *
1482  * Privilege bit for gpio0. Writing zero has no effect. Writing one will set the
1483  * privilege bit
1484  *
1485  * Field Access Macros:
1486  *
1487  */
1488 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field. */
1489 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_LSB 17
1490 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field. */
1491 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_MSB 17
1492 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field. */
1493 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_WIDTH 1
1494 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field value. */
1495 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET_MSK 0x00020000
1496 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field value. */
1497 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_CLR_MSK 0xfffdffff
1498 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field. */
1499 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_RESET 0x0
1500 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 field value from a register. */
1501 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
1502 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 register field value suitable for setting the register. */
1503 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET(value) (((value) << 17) & 0x00020000)
1504 
1505 /*
1506  * Field : gpio1
1507  *
1508  * Privilege bit for gpio1. Writing zero has no effect. Writing one will set the
1509  * privilege bit
1510  *
1511  * Field Access Macros:
1512  *
1513  */
1514 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field. */
1515 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_LSB 18
1516 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field. */
1517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_MSB 18
1518 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field. */
1519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_WIDTH 1
1520 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field value. */
1521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET_MSK 0x00040000
1522 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field value. */
1523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_CLR_MSK 0xfffbffff
1524 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field. */
1525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_RESET 0x0
1526 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 field value from a register. */
1527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
1528 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 register field value suitable for setting the register. */
1529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET(value) (((value) << 18) & 0x00040000)
1530 
1531 /*
1532  * Field : gpio2
1533  *
1534  * Privilege bit for gpio2. Writing zero has no effect. Writing one will set the
1535  * privilege bit
1536  *
1537  * Field Access Macros:
1538  *
1539  */
1540 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field. */
1541 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_LSB 19
1542 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field. */
1543 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_MSB 19
1544 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field. */
1545 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_WIDTH 1
1546 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field value. */
1547 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET_MSK 0x00080000
1548 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field value. */
1549 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_CLR_MSK 0xfff7ffff
1550 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field. */
1551 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_RESET 0x0
1552 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 field value from a register. */
1553 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
1554 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 register field value suitable for setting the register. */
1555 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET(value) (((value) << 19) & 0x00080000)
1556 
1557 /*
1558  * Field : i2c0
1559  *
1560  * Privilege bit for i2c0. Writing zero has no effect. Writing one will set the
1561  * privilege bit
1562  *
1563  * Field Access Macros:
1564  *
1565  */
1566 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field. */
1567 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_LSB 20
1568 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field. */
1569 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_MSB 20
1570 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field. */
1571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_WIDTH 1
1572 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field value. */
1573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET_MSK 0x00100000
1574 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field value. */
1575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_CLR_MSK 0xffefffff
1576 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field. */
1577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_RESET 0x0
1578 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 field value from a register. */
1579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_GET(value) (((value) & 0x00100000) >> 20)
1580 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 register field value suitable for setting the register. */
1581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET(value) (((value) << 20) & 0x00100000)
1582 
1583 /*
1584  * Field : i2c1
1585  *
1586  * Privilege bit for i2c1. Writing zero has no effect. Writing one will set the
1587  * privilege bit
1588  *
1589  * Field Access Macros:
1590  *
1591  */
1592 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field. */
1593 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_LSB 21
1594 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field. */
1595 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_MSB 21
1596 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field. */
1597 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_WIDTH 1
1598 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field value. */
1599 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET_MSK 0x00200000
1600 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field value. */
1601 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_CLR_MSK 0xffdfffff
1602 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field. */
1603 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_RESET 0x0
1604 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 field value from a register. */
1605 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_GET(value) (((value) & 0x00200000) >> 21)
1606 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 register field value suitable for setting the register. */
1607 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET(value) (((value) << 21) & 0x00200000)
1608 
1609 /*
1610  * Field : i2c2
1611  *
1612  * Privilege bit for i2c2. Writing zero has no effect. Writing one will set the
1613  * privilege bit
1614  *
1615  * Field Access Macros:
1616  *
1617  */
1618 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field. */
1619 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_LSB 22
1620 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field. */
1621 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_MSB 22
1622 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field. */
1623 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_WIDTH 1
1624 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field value. */
1625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET_MSK 0x00400000
1626 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field value. */
1627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_CLR_MSK 0xffbfffff
1628 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field. */
1629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_RESET 0x0
1630 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 field value from a register. */
1631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_GET(value) (((value) & 0x00400000) >> 22)
1632 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 register field value suitable for setting the register. */
1633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET(value) (((value) << 22) & 0x00400000)
1634 
1635 /*
1636  * Field : i2c3
1637  *
1638  * Privilege bit for i2c3. Writing zero has no effect. Writing one will set the
1639  * privilege bit
1640  *
1641  * Field Access Macros:
1642  *
1643  */
1644 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field. */
1645 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_LSB 23
1646 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field. */
1647 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_MSB 23
1648 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field. */
1649 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_WIDTH 1
1650 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field value. */
1651 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET_MSK 0x00800000
1652 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field value. */
1653 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_CLR_MSK 0xff7fffff
1654 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field. */
1655 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_RESET 0x0
1656 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 field value from a register. */
1657 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_GET(value) (((value) & 0x00800000) >> 23)
1658 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 register field value suitable for setting the register. */
1659 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET(value) (((value) << 23) & 0x00800000)
1660 
1661 /*
1662  * Field : i2c4
1663  *
1664  * Privilege bit for i2c4. Writing zero has no effect. Writing one will set the
1665  * privilege bit
1666  *
1667  * Field Access Macros:
1668  *
1669  */
1670 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field. */
1671 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_LSB 24
1672 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field. */
1673 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_MSB 24
1674 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field. */
1675 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_WIDTH 1
1676 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field value. */
1677 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET_MSK 0x01000000
1678 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field value. */
1679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_CLR_MSK 0xfeffffff
1680 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field. */
1681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_RESET 0x0
1682 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 field value from a register. */
1683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_GET(value) (((value) & 0x01000000) >> 24)
1684 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 register field value suitable for setting the register. */
1685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET(value) (((value) << 24) & 0x01000000)
1686 
1687 /*
1688  * Field : sp_timer0
1689  *
1690  * Privilege bit for sp_timer0. Writing zero has no effect. Writing one will set
1691  * the privilege bit
1692  *
1693  * Field Access Macros:
1694  *
1695  */
1696 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field. */
1697 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_LSB 25
1698 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field. */
1699 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_MSB 25
1700 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field. */
1701 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_WIDTH 1
1702 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field value. */
1703 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET_MSK 0x02000000
1704 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field value. */
1705 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_CLR_MSK 0xfdffffff
1706 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field. */
1707 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_RESET 0x0
1708 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 field value from a register. */
1709 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
1710 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 register field value suitable for setting the register. */
1711 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
1712 
1713 /*
1714  * Field : sp_timer1
1715  *
1716  * Privilege bit for sp_timer1. Writing zero has no effect. Writing one will set
1717  * the privilege bit
1718  *
1719  * Field Access Macros:
1720  *
1721  */
1722 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field. */
1723 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_LSB 26
1724 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field. */
1725 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_MSB 26
1726 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field. */
1727 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_WIDTH 1
1728 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field value. */
1729 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET_MSK 0x04000000
1730 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field value. */
1731 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_CLR_MSK 0xfbffffff
1732 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field. */
1733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_RESET 0x0
1734 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 field value from a register. */
1735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
1736 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 register field value suitable for setting the register. */
1737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
1738 
1739 /*
1740  * Field : uart0
1741  *
1742  * Privilege bit for uart0. Writing zero has no effect. Writing one will set the
1743  * privilege bit
1744  *
1745  * Field Access Macros:
1746  *
1747  */
1748 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field. */
1749 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_LSB 27
1750 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field. */
1751 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_MSB 27
1752 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field. */
1753 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_WIDTH 1
1754 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field value. */
1755 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET_MSK 0x08000000
1756 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field value. */
1757 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_CLR_MSK 0xf7ffffff
1758 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field. */
1759 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_RESET 0x0
1760 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 field value from a register. */
1761 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_GET(value) (((value) & 0x08000000) >> 27)
1762 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 register field value suitable for setting the register. */
1763 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET(value) (((value) << 27) & 0x08000000)
1764 
1765 /*
1766  * Field : uart1
1767  *
1768  * Privilege bit for uart1. Writing zero has no effect. Writing one will set the
1769  * privilege bit
1770  *
1771  * Field Access Macros:
1772  *
1773  */
1774 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field. */
1775 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_LSB 28
1776 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field. */
1777 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_MSB 28
1778 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field. */
1779 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_WIDTH 1
1780 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field value. */
1781 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET_MSK 0x10000000
1782 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field value. */
1783 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_CLR_MSK 0xefffffff
1784 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field. */
1785 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_RESET 0x0
1786 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 field value from a register. */
1787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_GET(value) (((value) & 0x10000000) >> 28)
1788 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 register field value suitable for setting the register. */
1789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET(value) (((value) << 28) & 0x10000000)
1790 
1791 /*
1792  * Field : lwsoc2fpga
1793  *
1794  * Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one
1795  * will set the privilege bit
1796  *
1797  * Field Access Macros:
1798  *
1799  */
1800 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field. */
1801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_LSB 29
1802 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field. */
1803 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_MSB 29
1804 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field. */
1805 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_WIDTH 1
1806 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field value. */
1807 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET_MSK 0x20000000
1808 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field value. */
1809 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_CLR_MSK 0xdfffffff
1810 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field. */
1811 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_RESET 0x0
1812 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F field value from a register. */
1813 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
1814 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F register field value suitable for setting the register. */
1815 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET(value) (((value) << 29) & 0x20000000)
1816 
1817 /*
1818  * Field : soc2fpga
1819  *
1820  * Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will set the
1821  * privilege bit
1822  *
1823  * Field Access Macros:
1824  *
1825  */
1826 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field. */
1827 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_LSB 30
1828 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field. */
1829 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_MSB 30
1830 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field. */
1831 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_WIDTH 1
1832 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field value. */
1833 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET_MSK 0x40000000
1834 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field value. */
1835 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_CLR_MSK 0xbfffffff
1836 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field. */
1837 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_RESET 0x0
1838 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F field value from a register. */
1839 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_GET(value) (((value) & 0x40000000) >> 30)
1840 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F register field value suitable for setting the register. */
1841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET(value) (((value) << 30) & 0x40000000)
1842 
1843 #ifndef __ASSEMBLY__
1844 /*
1845  * WARNING: The C register and register group struct declarations are provided for
1846  * convenience and illustrative purposes. They should, however, be used with
1847  * caution as the C language standard provides no guarantees about the alignment or
1848  * atomicity of device memory accesses. The recommended practice for writing
1849  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1850  * alt_write_word() functions.
1851  *
1852  * The struct declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET.
1853  */
1854 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_s
1855 {
1856  uint32_t nand_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG */
1857  uint32_t nand_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA */
1858  uint32_t qspi_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA */
1859  uint32_t usb0_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG */
1860  uint32_t usb1_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG */
1861  uint32_t dma_nonsecure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE */
1862  uint32_t dma_secure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE */
1863  uint32_t spi_master0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0 */
1864  uint32_t spi_master1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1 */
1865  uint32_t spi_slave0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0 */
1866  uint32_t spi_slave1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1 */
1867  uint32_t emac0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0 */
1868  uint32_t emac1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1 */
1869  uint32_t emac2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2 */
1870  uint32_t emac3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3 */
1871  uint32_t qspi : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI */
1872  uint32_t sdmmc : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC */
1873  uint32_t gpio0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0 */
1874  uint32_t gpio1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1 */
1875  uint32_t gpio2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2 */
1876  uint32_t i2c0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0 */
1877  uint32_t i2c1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1 */
1878  uint32_t i2c2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2 */
1879  uint32_t i2c3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3 */
1880  uint32_t i2c4 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4 */
1881  uint32_t sp_timer0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0 */
1882  uint32_t sp_timer1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1 */
1883  uint32_t uart0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0 */
1884  uint32_t uart1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1 */
1885  uint32_t lwsoc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F */
1886  uint32_t soc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F */
1887  uint32_t : 1; /* *UNDEFINED* */
1888 };
1889 
1890 /* The typedef declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET. */
1891 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_t;
1892 #endif /* __ASSEMBLY__ */
1893 
1894 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET register. */
1895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_RESET 0x00000000
1896 /* The byte offset of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET register from the beginning of the component. */
1897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_OFST 0x4
1898 
1899 /*
1900  * Register : l4_priv_clear
1901  *
1902  * Clears Region Enable field when written with 1
1903  *
1904  * Register Layout
1905  *
1906  * Bits | Access | Reset | Description
1907  * :-----|:-------|:--------|:----------------------------------------------
1908  * [0] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG
1909  * [1] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA
1910  * [2] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA
1911  * [3] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG
1912  * [4] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG
1913  * [5] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE
1914  * [6] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE
1915  * [7] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0
1916  * [8] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1
1917  * [9] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0
1918  * [10] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1
1919  * [11] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0
1920  * [12] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1
1921  * [13] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2
1922  * [14] | RW | Unknown | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3
1923  * [15] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI
1924  * [16] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC
1925  * [17] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0
1926  * [18] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1
1927  * [19] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2
1928  * [20] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0
1929  * [21] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1
1930  * [22] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2
1931  * [23] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3
1932  * [24] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4
1933  * [25] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0
1934  * [26] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1
1935  * [27] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0
1936  * [28] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1
1937  * [29] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F
1938  * [30] | W | 0x0 | ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F
1939  * [31] | ??? | Unknown | *UNDEFINED*
1940  *
1941  */
1942 /*
1943  * Field : nand_register
1944  *
1945  * Privilege bit for nand register. Writing zero has no effect. Writing one will
1946  * clear the privilege bit
1947  *
1948  * Field Access Macros:
1949  *
1950  */
1951 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field. */
1952 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_LSB 0
1953 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field. */
1954 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_MSB 0
1955 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field. */
1956 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_WIDTH 1
1957 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field value. */
1958 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET_MSK 0x00000001
1959 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field value. */
1960 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_CLR_MSK 0xfffffffe
1961 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field. */
1962 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_RESET 0x0
1963 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG field value from a register. */
1964 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1965 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG register field value suitable for setting the register. */
1966 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1967 
1968 /*
1969  * Field : nand_data
1970  *
1971  * Privilege bit for nand_data. Writing zero has no effect. Writing one will clear
1972  * the privilege bit
1973  *
1974  * Field Access Macros:
1975  *
1976  */
1977 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field. */
1978 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_LSB 1
1979 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field. */
1980 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_MSB 1
1981 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field. */
1982 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_WIDTH 1
1983 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field value. */
1984 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET_MSK 0x00000002
1985 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field value. */
1986 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_CLR_MSK 0xfffffffd
1987 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field. */
1988 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_RESET 0x0
1989 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA field value from a register. */
1990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1991 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA register field value suitable for setting the register. */
1992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1993 
1994 /*
1995  * Field : qspi_data
1996  *
1997  * Privilege bit for qspi_data. Writing zero has no effect. Writing one will clear
1998  * the privilege bit
1999  *
2000  * Field Access Macros:
2001  *
2002  */
2003 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field. */
2004 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_LSB 2
2005 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field. */
2006 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_MSB 2
2007 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field. */
2008 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_WIDTH 1
2009 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field value. */
2010 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET_MSK 0x00000004
2011 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field value. */
2012 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_CLR_MSK 0xfffffffb
2013 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field. */
2014 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_RESET 0x0
2015 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA field value from a register. */
2016 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
2017 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA register field value suitable for setting the register. */
2018 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
2019 
2020 /*
2021  * Field : usb0_register
2022  *
2023  * Privilege bit for usb0_register. Writing zero has no effect. Writing one will
2024  * clear the privilege bit
2025  *
2026  * Field Access Macros:
2027  *
2028  */
2029 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field. */
2030 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_LSB 3
2031 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field. */
2032 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_MSB 3
2033 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field. */
2034 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_WIDTH 1
2035 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field value. */
2036 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET_MSK 0x00000008
2037 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field value. */
2038 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_CLR_MSK 0xfffffff7
2039 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field. */
2040 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_RESET 0x0
2041 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG field value from a register. */
2042 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
2043 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG register field value suitable for setting the register. */
2044 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
2045 
2046 /*
2047  * Field : usb1_register
2048  *
2049  * Privilege bit for usb1_register. Writing zero has no effect. Writing one will
2050  * clear the privilege bit
2051  *
2052  * Field Access Macros:
2053  *
2054  */
2055 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field. */
2056 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_LSB 4
2057 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field. */
2058 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_MSB 4
2059 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field. */
2060 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_WIDTH 1
2061 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field value. */
2062 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET_MSK 0x00000010
2063 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field value. */
2064 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_CLR_MSK 0xffffffef
2065 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field. */
2066 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_RESET 0x0
2067 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG field value from a register. */
2068 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
2069 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG register field value suitable for setting the register. */
2070 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
2071 
2072 /*
2073  * Field : dma_nonsecure
2074  *
2075  * Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will
2076  * clear the privilege bit
2077  *
2078  * Field Access Macros:
2079  *
2080  */
2081 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field. */
2082 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_LSB 5
2083 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field. */
2084 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_MSB 5
2085 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field. */
2086 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_WIDTH 1
2087 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field value. */
2088 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET_MSK 0x00000020
2089 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field value. */
2090 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_CLR_MSK 0xffffffdf
2091 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field. */
2092 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_RESET 0x0
2093 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE field value from a register. */
2094 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
2095 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE register field value suitable for setting the register. */
2096 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
2097 
2098 /*
2099  * Field : dma_secure
2100  *
2101  * Privilege bit for dma_secure. Writing zero has no effect. Writing one will clear
2102  * the privilege bit
2103  *
2104  * Field Access Macros:
2105  *
2106  */
2107 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field. */
2108 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_LSB 6
2109 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field. */
2110 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_MSB 6
2111 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field. */
2112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_WIDTH 1
2113 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field value. */
2114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET_MSK 0x00000040
2115 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field value. */
2116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_CLR_MSK 0xffffffbf
2117 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field. */
2118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_RESET 0x0
2119 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE field value from a register. */
2120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
2121 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE register field value suitable for setting the register. */
2122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
2123 
2124 /*
2125  * Field : spi_master0
2126  *
2127  * Privilege bit for spi_master0. Writing zero has no effect. Writing one will
2128  * clear the privilege bit
2129  *
2130  * Field Access Macros:
2131  *
2132  */
2133 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field. */
2134 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_LSB 7
2135 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field. */
2136 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_MSB 7
2137 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field. */
2138 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_WIDTH 1
2139 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field value. */
2140 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET_MSK 0x00000080
2141 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field value. */
2142 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_CLR_MSK 0xffffff7f
2143 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field. */
2144 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_RESET 0x0
2145 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 field value from a register. */
2146 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
2147 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 register field value suitable for setting the register. */
2148 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
2149 
2150 /*
2151  * Field : spi_master1
2152  *
2153  * Privilege bit for spi_master1. Writing zero has no effect. Writing one will
2154  * clear the privilege bit
2155  *
2156  * Field Access Macros:
2157  *
2158  */
2159 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field. */
2160 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_LSB 8
2161 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field. */
2162 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_MSB 8
2163 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field. */
2164 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_WIDTH 1
2165 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field value. */
2166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET_MSK 0x00000100
2167 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field value. */
2168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_CLR_MSK 0xfffffeff
2169 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field. */
2170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_RESET 0x0
2171 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 field value from a register. */
2172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
2173 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 register field value suitable for setting the register. */
2174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
2175 
2176 /*
2177  * Field : spi_slave0
2178  *
2179  * Privilege bit for spi_slave0. Writing zero has no effect. Writing one will clear
2180  * the privilege bit
2181  *
2182  * Field Access Macros:
2183  *
2184  */
2185 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field. */
2186 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_LSB 9
2187 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field. */
2188 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_MSB 9
2189 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field. */
2190 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_WIDTH 1
2191 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field value. */
2192 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET_MSK 0x00000200
2193 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field value. */
2194 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_CLR_MSK 0xfffffdff
2195 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field. */
2196 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_RESET 0x0
2197 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 field value from a register. */
2198 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
2199 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 register field value suitable for setting the register. */
2200 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
2201 
2202 /*
2203  * Field : spi_slave1
2204  *
2205  * Privilege bit for spi_slave1. Writing zero has no effect. Writing one will clear
2206  * the privilege bit
2207  *
2208  * Field Access Macros:
2209  *
2210  */
2211 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field. */
2212 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_LSB 10
2213 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field. */
2214 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_MSB 10
2215 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field. */
2216 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_WIDTH 1
2217 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field value. */
2218 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET_MSK 0x00000400
2219 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field value. */
2220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_CLR_MSK 0xfffffbff
2221 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field. */
2222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_RESET 0x0
2223 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 field value from a register. */
2224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
2225 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 register field value suitable for setting the register. */
2226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
2227 
2228 /*
2229  * Field : emac0
2230  *
2231  * Privilege bit for emac0. Writing zero has no effect. Writing one will clear the
2232  * privilege bit
2233  *
2234  * Field Access Macros:
2235  *
2236  */
2237 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field. */
2238 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_LSB 11
2239 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field. */
2240 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_MSB 11
2241 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field. */
2242 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_WIDTH 1
2243 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field value. */
2244 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET_MSK 0x00000800
2245 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field value. */
2246 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_CLR_MSK 0xfffff7ff
2247 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field. */
2248 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_RESET 0x0
2249 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 field value from a register. */
2250 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
2251 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 register field value suitable for setting the register. */
2252 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET(value) (((value) << 11) & 0x00000800)
2253 
2254 /*
2255  * Field : emac1
2256  *
2257  * Privilege bit for emac1. Writing zero has no effect. Writing one will clear the
2258  * privilege bit
2259  *
2260  * Field Access Macros:
2261  *
2262  */
2263 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field. */
2264 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_LSB 12
2265 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field. */
2266 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_MSB 12
2267 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field. */
2268 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_WIDTH 1
2269 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field value. */
2270 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET_MSK 0x00001000
2271 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field value. */
2272 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_CLR_MSK 0xffffefff
2273 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field. */
2274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_RESET 0x0
2275 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 field value from a register. */
2276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
2277 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 register field value suitable for setting the register. */
2278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET(value) (((value) << 12) & 0x00001000)
2279 
2280 /*
2281  * Field : emac2
2282  *
2283  * Privilege bit for emac2. Writing zero has no effect. Writing one will clear the
2284  * privilege bit
2285  *
2286  * Field Access Macros:
2287  *
2288  */
2289 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field. */
2290 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_LSB 13
2291 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field. */
2292 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_MSB 13
2293 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field. */
2294 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_WIDTH 1
2295 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field value. */
2296 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET_MSK 0x00002000
2297 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field value. */
2298 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_CLR_MSK 0xffffdfff
2299 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field. */
2300 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_RESET 0x0
2301 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 field value from a register. */
2302 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
2303 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 register field value suitable for setting the register. */
2304 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET(value) (((value) << 13) & 0x00002000)
2305 
2306 /*
2307  * Field : emac3
2308  *
2309  * Privilege bit for emac3. Writing zero has no effect. Writing one will clear the
2310  * privilege bit
2311  *
2312  * Field Access Macros:
2313  *
2314  */
2315 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field. */
2316 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_LSB 14
2317 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field. */
2318 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_MSB 14
2319 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field. */
2320 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_WIDTH 1
2321 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field value. */
2322 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET_MSK 0x00004000
2323 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field value. */
2324 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_CLR_MSK 0xffffbfff
2325 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field is UNKNOWN. */
2326 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_RESET 0x0
2327 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 field value from a register. */
2328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
2329 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 register field value suitable for setting the register. */
2330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET(value) (((value) << 14) & 0x00004000)
2331 
2332 /*
2333  * Field : qspi
2334  *
2335  * Privilege bit for qspi. Writing zero has no effect. Writing one will clear the
2336  * privilege bit
2337  *
2338  * Field Access Macros:
2339  *
2340  */
2341 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field. */
2342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_LSB 15
2343 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field. */
2344 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_MSB 15
2345 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field. */
2346 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_WIDTH 1
2347 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field value. */
2348 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET_MSK 0x00008000
2349 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field value. */
2350 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_CLR_MSK 0xffff7fff
2351 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field. */
2352 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_RESET 0x0
2353 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI field value from a register. */
2354 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_GET(value) (((value) & 0x00008000) >> 15)
2355 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI register field value suitable for setting the register. */
2356 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET(value) (((value) << 15) & 0x00008000)
2357 
2358 /*
2359  * Field : sdmmc
2360  *
2361  * Privilege bit for sdmmc. Writing zero has no effect. Writing one will clear the
2362  * privilege bit
2363  *
2364  * Field Access Macros:
2365  *
2366  */
2367 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field. */
2368 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_LSB 16
2369 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field. */
2370 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_MSB 16
2371 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field. */
2372 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_WIDTH 1
2373 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field value. */
2374 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET_MSK 0x00010000
2375 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field value. */
2376 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_CLR_MSK 0xfffeffff
2377 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field. */
2378 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_RESET 0x0
2379 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC field value from a register. */
2380 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
2381 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC register field value suitable for setting the register. */
2382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET(value) (((value) << 16) & 0x00010000)
2383 
2384 /*
2385  * Field : gpio0
2386  *
2387  * Privilege bit for gpio0. Writing zero has no effect. Writing one will clear the
2388  * privilege bit
2389  *
2390  * Field Access Macros:
2391  *
2392  */
2393 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field. */
2394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_LSB 17
2395 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field. */
2396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_MSB 17
2397 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field. */
2398 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_WIDTH 1
2399 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field value. */
2400 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET_MSK 0x00020000
2401 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field value. */
2402 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_CLR_MSK 0xfffdffff
2403 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field. */
2404 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_RESET 0x0
2405 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 field value from a register. */
2406 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
2407 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 register field value suitable for setting the register. */
2408 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET(value) (((value) << 17) & 0x00020000)
2409 
2410 /*
2411  * Field : gpio1
2412  *
2413  * Privilege bit for gpio1. Writing zero has no effect. Writing one will clear the
2414  * privilege bit
2415  *
2416  * Field Access Macros:
2417  *
2418  */
2419 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field. */
2420 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_LSB 18
2421 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field. */
2422 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_MSB 18
2423 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field. */
2424 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_WIDTH 1
2425 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field value. */
2426 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET_MSK 0x00040000
2427 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field value. */
2428 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_CLR_MSK 0xfffbffff
2429 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field. */
2430 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_RESET 0x0
2431 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 field value from a register. */
2432 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
2433 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 register field value suitable for setting the register. */
2434 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET(value) (((value) << 18) & 0x00040000)
2435 
2436 /*
2437  * Field : gpio2
2438  *
2439  * Privilege bit for gpio2. Writing zero has no effect. Writing one will clear the
2440  * privilege bit
2441  *
2442  * Field Access Macros:
2443  *
2444  */
2445 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field. */
2446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_LSB 19
2447 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field. */
2448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_MSB 19
2449 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field. */
2450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_WIDTH 1
2451 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field value. */
2452 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET_MSK 0x00080000
2453 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field value. */
2454 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_CLR_MSK 0xfff7ffff
2455 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field. */
2456 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_RESET 0x0
2457 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 field value from a register. */
2458 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
2459 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 register field value suitable for setting the register. */
2460 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET(value) (((value) << 19) & 0x00080000)
2461 
2462 /*
2463  * Field : i2c0
2464  *
2465  * Privilege bit for i2c0. Writing zero has no effect. Writing one will clear the
2466  * privilege bit
2467  *
2468  * Field Access Macros:
2469  *
2470  */
2471 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field. */
2472 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_LSB 20
2473 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field. */
2474 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_MSB 20
2475 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field. */
2476 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_WIDTH 1
2477 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field value. */
2478 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET_MSK 0x00100000
2479 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field value. */
2480 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_CLR_MSK 0xffefffff
2481 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field. */
2482 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_RESET 0x0
2483 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 field value from a register. */
2484 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_GET(value) (((value) & 0x00100000) >> 20)
2485 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 register field value suitable for setting the register. */
2486 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET(value) (((value) << 20) & 0x00100000)
2487 
2488 /*
2489  * Field : i2c1
2490  *
2491  * Privilege bit for i2c1. Writing zero has no effect. Writing one will clear the
2492  * privilege bit
2493  *
2494  * Field Access Macros:
2495  *
2496  */
2497 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field. */
2498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_LSB 21
2499 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field. */
2500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_MSB 21
2501 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field. */
2502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_WIDTH 1
2503 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field value. */
2504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET_MSK 0x00200000
2505 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field value. */
2506 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_CLR_MSK 0xffdfffff
2507 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field. */
2508 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_RESET 0x0
2509 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 field value from a register. */
2510 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_GET(value) (((value) & 0x00200000) >> 21)
2511 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 register field value suitable for setting the register. */
2512 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET(value) (((value) << 21) & 0x00200000)
2513 
2514 /*
2515  * Field : i2c2
2516  *
2517  * Privilege bit for i2c2. Writing zero has no effect. Writing one will clear the
2518  * privilege bit
2519  *
2520  * Field Access Macros:
2521  *
2522  */
2523 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field. */
2524 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_LSB 22
2525 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field. */
2526 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_MSB 22
2527 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field. */
2528 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_WIDTH 1
2529 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field value. */
2530 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET_MSK 0x00400000
2531 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field value. */
2532 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_CLR_MSK 0xffbfffff
2533 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field. */
2534 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_RESET 0x0
2535 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 field value from a register. */
2536 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_GET(value) (((value) & 0x00400000) >> 22)
2537 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 register field value suitable for setting the register. */
2538 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET(value) (((value) << 22) & 0x00400000)
2539 
2540 /*
2541  * Field : i2c3
2542  *
2543  * Privilege bit for i2c3. Writing zero has no effect. Writing one will clear the
2544  * privilege bit
2545  *
2546  * Field Access Macros:
2547  *
2548  */
2549 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field. */
2550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_LSB 23
2551 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field. */
2552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_MSB 23
2553 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field. */
2554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_WIDTH 1
2555 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field value. */
2556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET_MSK 0x00800000
2557 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field value. */
2558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_CLR_MSK 0xff7fffff
2559 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field. */
2560 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_RESET 0x0
2561 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 field value from a register. */
2562 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_GET(value) (((value) & 0x00800000) >> 23)
2563 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 register field value suitable for setting the register. */
2564 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET(value) (((value) << 23) & 0x00800000)
2565 
2566 /*
2567  * Field : i2c4
2568  *
2569  * Privilege bit for i2c4. Writing zero has no effect. Writing one will clear the
2570  * privilege bit
2571  *
2572  * Field Access Macros:
2573  *
2574  */
2575 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field. */
2576 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_LSB 24
2577 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field. */
2578 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_MSB 24
2579 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field. */
2580 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_WIDTH 1
2581 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field value. */
2582 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET_MSK 0x01000000
2583 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field value. */
2584 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_CLR_MSK 0xfeffffff
2585 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field. */
2586 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_RESET 0x0
2587 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 field value from a register. */
2588 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_GET(value) (((value) & 0x01000000) >> 24)
2589 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 register field value suitable for setting the register. */
2590 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET(value) (((value) << 24) & 0x01000000)
2591 
2592 /*
2593  * Field : sp_timer0
2594  *
2595  * Privilege bit for sp_timer0. Writing zero has no effect. Writing one will clear
2596  * the privilege bit
2597  *
2598  * Field Access Macros:
2599  *
2600  */
2601 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field. */
2602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_LSB 25
2603 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field. */
2604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_MSB 25
2605 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field. */
2606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_WIDTH 1
2607 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field value. */
2608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET_MSK 0x02000000
2609 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field value. */
2610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_CLR_MSK 0xfdffffff
2611 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field. */
2612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_RESET 0x0
2613 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 field value from a register. */
2614 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
2615 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 register field value suitable for setting the register. */
2616 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
2617 
2618 /*
2619  * Field : sp_timer1
2620  *
2621  * Privilege bit for sp_timer1. Writing zero has no effect. Writing one will clear
2622  * the privilege bit
2623  *
2624  * Field Access Macros:
2625  *
2626  */
2627 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field. */
2628 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_LSB 26
2629 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field. */
2630 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_MSB 26
2631 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field. */
2632 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_WIDTH 1
2633 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field value. */
2634 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET_MSK 0x04000000
2635 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field value. */
2636 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_CLR_MSK 0xfbffffff
2637 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field. */
2638 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_RESET 0x0
2639 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 field value from a register. */
2640 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
2641 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 register field value suitable for setting the register. */
2642 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
2643 
2644 /*
2645  * Field : uart0
2646  *
2647  * Privilege bit for uart0. Writing zero has no effect. Writing one will clear the
2648  * privilege bit
2649  *
2650  * Field Access Macros:
2651  *
2652  */
2653 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field. */
2654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_LSB 27
2655 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field. */
2656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_MSB 27
2657 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field. */
2658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_WIDTH 1
2659 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field value. */
2660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET_MSK 0x08000000
2661 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field value. */
2662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_CLR_MSK 0xf7ffffff
2663 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field. */
2664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_RESET 0x0
2665 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 field value from a register. */
2666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_GET(value) (((value) & 0x08000000) >> 27)
2667 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 register field value suitable for setting the register. */
2668 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET(value) (((value) << 27) & 0x08000000)
2669 
2670 /*
2671  * Field : uart1
2672  *
2673  * Privilege bit for uart1. Writing zero has no effect. Writing one will clear the
2674  * privilege bit
2675  *
2676  * Field Access Macros:
2677  *
2678  */
2679 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field. */
2680 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_LSB 28
2681 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field. */
2682 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_MSB 28
2683 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field. */
2684 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_WIDTH 1
2685 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field value. */
2686 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET_MSK 0x10000000
2687 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field value. */
2688 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_CLR_MSK 0xefffffff
2689 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field. */
2690 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_RESET 0x0
2691 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 field value from a register. */
2692 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_GET(value) (((value) & 0x10000000) >> 28)
2693 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 register field value suitable for setting the register. */
2694 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET(value) (((value) << 28) & 0x10000000)
2695 
2696 /*
2697  * Field : lwsoc2fpga
2698  *
2699  * Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one
2700  * will clear the privilege bit
2701  *
2702  * Field Access Macros:
2703  *
2704  */
2705 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field. */
2706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_LSB 29
2707 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field. */
2708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_MSB 29
2709 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field. */
2710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_WIDTH 1
2711 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field value. */
2712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET_MSK 0x20000000
2713 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field value. */
2714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_CLR_MSK 0xdfffffff
2715 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field. */
2716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_RESET 0x0
2717 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F field value from a register. */
2718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
2719 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F register field value suitable for setting the register. */
2720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET(value) (((value) << 29) & 0x20000000)
2721 
2722 /*
2723  * Field : soc2fpga
2724  *
2725  * Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will clear
2726  * the privilege bit
2727  *
2728  * Field Access Macros:
2729  *
2730  */
2731 /* The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field. */
2732 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_LSB 30
2733 /* The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field. */
2734 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_MSB 30
2735 /* The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field. */
2736 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_WIDTH 1
2737 /* The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field value. */
2738 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET_MSK 0x40000000
2739 /* The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field value. */
2740 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_CLR_MSK 0xbfffffff
2741 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field. */
2742 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_RESET 0x0
2743 /* Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F field value from a register. */
2744 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_GET(value) (((value) & 0x40000000) >> 30)
2745 /* Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F register field value suitable for setting the register. */
2746 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET(value) (((value) << 30) & 0x40000000)
2747 
2748 #ifndef __ASSEMBLY__
2749 /*
2750  * WARNING: The C register and register group struct declarations are provided for
2751  * convenience and illustrative purposes. They should, however, be used with
2752  * caution as the C language standard provides no guarantees about the alignment or
2753  * atomicity of device memory accesses. The recommended practice for writing
2754  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2755  * alt_write_word() functions.
2756  *
2757  * The struct declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR.
2758  */
2759 struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_s
2760 {
2761  uint32_t nand_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG */
2762  uint32_t nand_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA */
2763  uint32_t qspi_data : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA */
2764  uint32_t usb0_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG */
2765  uint32_t usb1_register : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG */
2766  uint32_t dma_nonsecure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE */
2767  uint32_t dma_secure : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE */
2768  uint32_t spi_master0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0 */
2769  uint32_t spi_master1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1 */
2770  uint32_t spi_slave0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0 */
2771  uint32_t spi_slave1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1 */
2772  uint32_t emac0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0 */
2773  uint32_t emac1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1 */
2774  uint32_t emac2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2 */
2775  uint32_t emac3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3 */
2776  uint32_t qspi : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI */
2777  uint32_t sdmmc : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC */
2778  uint32_t gpio0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0 */
2779  uint32_t gpio1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1 */
2780  uint32_t gpio2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2 */
2781  uint32_t i2c0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0 */
2782  uint32_t i2c1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1 */
2783  uint32_t i2c2 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2 */
2784  uint32_t i2c3 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3 */
2785  uint32_t i2c4 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4 */
2786  uint32_t sp_timer0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0 */
2787  uint32_t sp_timer1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1 */
2788  uint32_t uart0 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0 */
2789  uint32_t uart1 : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1 */
2790  uint32_t lwsoc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F */
2791  uint32_t soc2fpga : 1; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F */
2792  uint32_t : 1; /* *UNDEFINED* */
2793 };
2794 
2795 /* The typedef declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR. */
2796 typedef volatile struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_s ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_t;
2797 #endif /* __ASSEMBLY__ */
2798 
2799 /* The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR register. */
2800 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_RESET 0x00000000
2801 /* The byte offset of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR register from the beginning of the component. */
2802 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_OFST 0x8
2803 
2804 #ifndef __ASSEMBLY__
2805 /*
2806  * WARNING: The C register and register group struct declarations are provided for
2807  * convenience and illustrative purposes. They should, however, be used with
2808  * caution as the C language standard provides no guarantees about the alignment or
2809  * atomicity of device memory accesses. The recommended practice for writing
2810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2811  * alt_write_word() functions.
2812  *
2813  * The struct declaration for register group ALT_NOC_L4_PRIV_FLT.
2814  */
2815 struct ALT_NOC_L4_PRIV_FLT_s
2816 {
2817  ALT_NOC_L4_PRIV_FLT_L4_PRIV_t l4_priv; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV */
2818  ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_t l4_priv_set; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET */
2819  ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_t l4_priv_clear; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR */
2820  volatile uint32_t _pad_0xc_0x100[61]; /* *UNDEFINED* */
2821 };
2822 
2823 /* The typedef declaration for register group ALT_NOC_L4_PRIV_FLT. */
2824 typedef volatile struct ALT_NOC_L4_PRIV_FLT_s ALT_NOC_L4_PRIV_FLT_t;
2825 /* The struct declaration for the raw register contents of register group ALT_NOC_L4_PRIV_FLT. */
2826 struct ALT_NOC_L4_PRIV_FLT_raw_s
2827 {
2828  volatile uint32_t l4_priv; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV */
2829  volatile uint32_t l4_priv_set; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET */
2830  volatile uint32_t l4_priv_clear; /* ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR */
2831  uint32_t _pad_0xc_0x100[61]; /* *UNDEFINED* */
2832 };
2833 
2834 /* The typedef declaration for the raw register contents of register group ALT_NOC_L4_PRIV_FLT. */
2835 typedef volatile struct ALT_NOC_L4_PRIV_FLT_raw_s ALT_NOC_L4_PRIV_FLT_raw_t;
2836 #endif /* __ASSEMBLY__ */
2837 
2838 
2839 #ifdef __cplusplus
2840 }
2841 #endif /* __cplusplus */
2842 #endif /* __ALT_SOCAL_NOC_L4_PRIV_FLT_H__ */
2843