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20.1
Arria 10 SoC Hardware Manager
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alt_mpu_registers.h
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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/*
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* $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/alt_mpu_registers.h#1 $
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*/
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#ifndef __ALT_MPUSCU_H__
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#define __ALT_MPUSCU_H__
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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/************************************************************************************************************/
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/* alt_mpuscu.h */
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/* */
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/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
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/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
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/* */
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/************************************************************************************************************/
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#ifndef ALT_HPS_ADDR
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#define ALT_HPS_ADDR 0x00
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#endif
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/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
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/* and is the address of the base of the Snoop Control Unit (SCU) */
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#define ALT_GLOBALTMR_BASE (ALT_MPUSCU_OFST + ALT_GLOBALTMR_MODULE_BASE_OFFSET)
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#define ALT_CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + ALT_WDOG_TIMER_MODULE_BASE_OFFSET)
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#define ALT_CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + ALT_CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
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#define ALT_CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + ALT_INT_CONTROLLER_MODULE_BASE_OFFSET)
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#define ALT_CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + ALT_INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
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/* offsets */
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/* Global Timer offsets */
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#define ALT_GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
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#define ALT_GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
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#define ALT_GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
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#define ALT_GLOBALTMR_CTRL_REG_OFFSET 0x00000008
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#define ALT_GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
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#define ALT_GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
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#define ALT_GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
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#define ALT_GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
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/* Global Timer bitmasks */
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#define ALT_GLOBALTMR_ENABLE_BIT 0x00000001
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#define ALT_GLOBALTMR_COMP_ENABLE_BIT 0x00000002
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#define ALT_GLOBALTMR_INT_ENABLE_BIT 0x00000004
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#define ALT_GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
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#define ALT_GLOBALTMR_PS_MASK 0x0000FF00
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#define ALT_GLOBALTMR_PS_SHIFT 8
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#define ALT_GLOBALTMR_INT_STATUS_BIT 0x00000001
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/* Global timer constants */
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#define ALT_GLOBALTMR_MAX 0xFFFFFFFF
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#define ALT_GLOBALTMR_PS_MAX 0x000000FF
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/* Private timer offsets */
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#define ALT_CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
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#define ALT_CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
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#define ALT_CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
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#define ALT_CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
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#define ALT_CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
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/* Private timer bitmasks */
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#define ALT_CPU_PRIV_TMR_ENABLE 0x00000001
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#define ALT_CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
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#define ALT_CPU_PRIV_TMR_INT_EN 0x00000004
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#define ALT_CPU_PRIV_TMR_PS_MASK 0x0000FF00
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#define ALT_CPU_PRIV_TMR_PS_SHIFT 8
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#define ALT_CPU_PRIV_TMR_INT_STATUS 0x00000001
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/* Private timer constants */
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#define ALT_CPU_PRIV_TMR_MAX 0xFFFFFFFF
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#define ALT_CPU_PRIV_TMR_PS_MAX 0x000000FF
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/* Watchdog timer offsets */
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#define ALT_WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
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#define ALT_WDOG_LOAD_REG_OFFSET 0x00000000
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#define ALT_WDOG_CNTR_REG_OFFSET 0x00000004
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#define ALT_WDOG_CTRL_REG_OFFSET 0x00000008
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#define ALT_WDOG_INTSTAT_REG_OFFSET 0x0000000C
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#define ALT_WDOG_RSTSTAT_REG_OFFSET 0x00000010
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#define ALT_WDOG_DISABLE_REG_OFFSET 0x00000014
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/* Watchdog timer bitmasks : */
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/* Control Register bitmasks */
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#define ALT_WDOG_TMR_ENABLE 0x00000001
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#define ALT_WDOG_AUTO_RELOAD 0x00000002
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#define ALT_WDOG_INT_EN 0x00000004
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#define ALT_WDOG_WDT_MODE 0x00000008
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#define ALT_WDOG_PS_MASK 0x0000FF00
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#define ALT_WDOG_PS_SHIFT 8
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/* Interrupt Status Register bitmasks */
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#define ALT_WDOG_INT_STAT_BIT 0x00000001
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/* Reset Status Register bitmasks */
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#define ALT_WDOG_RST_STAT_BIT 0x00000001
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/* Watchdog timer constants */
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#define ALT_WDOG_TMR_MAX UINT32_MAX
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#define ALT_WDOG_PS_MAX UINT8_MAX
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#define ALT_WDOG_DISABLE_VAL0 0x12345678
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#define ALT_WDOG_DISABLE_VAL1 0x87654321
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/* Interrupt Manager offsets */
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/* <Add definitions here> */
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#define ALT_INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
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#define ALT_INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
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#define ALT_INT_DIST_TYPE_REG 0x00000004
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/* Upper bound of the MPUSCU address space */
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#define ALT_MPUSCU_MAX 0x00001FFF
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#ifdef __cplusplus
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}
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#endif
/* __cplusplus */
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#endif
/* __ALT_MPUSCU_H__ */
include
alt_mpu_registers.h
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