Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_ecc_ocram_ecc.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_ECC_OCRAM_ECC */
34 
35 #ifndef __ALT_SOCAL_ECC_OCRAM_ECC_H__
36 #define __ALT_SOCAL_ECC_OCRAM_ECC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_ECC_OCRAM_ECC
50  *
51  */
52 /*
53  * Register : IP_REV_ID
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:----------------------------------
59  * [15:0] | R | 0x0 | ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV
60  * [31:16] | ??? | 0x0 | *UNDEFINED*
61  *
62  */
63 /*
64  * Field : SIREV
65  *
66  * IP Rev #
67  *
68  * These bits indicate the silicon revision number.
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field. */
74 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_MSB 15
77 /* The width in bits of the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_WIDTH 16
79 /* The mask used to set the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field value. */
80 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 /* The mask used to clear the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 /* The reset value of the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field. */
84 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_RESET 0x0
85 /* Extracts the ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV field value from a register. */
86 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 /* Produces a ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV register field value suitable for setting the register. */
88 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_ECC_OCRAM_ECC_IP_REV_ID.
100  */
101 struct ALT_ECC_OCRAM_ECC_IP_REV_ID_s
102 {
103  const uint32_t SIREV : 16; /* ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV */
104  uint32_t : 16; /* *UNDEFINED* */
105 };
106 
107 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_IP_REV_ID. */
108 typedef volatile struct ALT_ECC_OCRAM_ECC_IP_REV_ID_s ALT_ECC_OCRAM_ECC_IP_REV_ID_t;
109 #endif /* __ASSEMBLY__ */
110 
111 /* The reset value of the ALT_ECC_OCRAM_ECC_IP_REV_ID register. */
112 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_RESET 0x00000000
113 /* The byte offset of the ALT_ECC_OCRAM_ECC_IP_REV_ID register from the beginning of the component. */
114 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_OFST 0x0
115 
116 /*
117  * Register : CTRL
118  *
119  * ECC Control Register
120  *
121  * Register Layout
122  *
123  * Bits | Access | Reset | Description
124  * :--------|:-------|:------|:-------------------------------------
125  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_CTL_ECC_EN
126  * [1] | RW | 0x1 | ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS
127  * [7:2] | ??? | 0x0 | *UNDEFINED*
128  * [8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA
129  * [15:9] | ??? | 0x0 | *UNDEFINED*
130  * [16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_CTL_INITA
131  * [31:17] | ??? | 0x0 | *UNDEFINED*
132  *
133  */
134 /*
135  * Field : ECC_EN
136  *
137  * Enable for the ECC detection and correction logic.
138  *
139  * Field Access Macros:
140  *
141  */
142 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field. */
143 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_LSB 0
144 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field. */
145 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_MSB 0
146 /* The width in bits of the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field. */
147 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_WIDTH 1
148 /* The mask used to set the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field value. */
149 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET_MSK 0x00000001
150 /* The mask used to clear the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field value. */
151 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
152 /* The reset value of the ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field. */
153 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_RESET 0x0
154 /* Extracts the ALT_ECC_OCRAM_ECC_CTL_ECC_EN field value from a register. */
155 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
156 /* Produces a ALT_ECC_OCRAM_ECC_CTL_ECC_EN register field value suitable for setting the register. */
157 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
158 
159 /*
160  * Field : ECC_SLVERR_DIS
161  *
162  * Enable to prevent double-bit ECC error from triggering SLVERR at ONCHIP_RAM AXI
163  * Interface RRESP output.
164  *
165  * Enable = 1'b1
166  *
167  * Disable = 1'b0
168  *
169  * Field Access Macros:
170  *
171  */
172 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field. */
173 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_LSB 1
174 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field. */
175 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_MSB 1
176 /* The width in bits of the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field. */
177 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_WIDTH 1
178 /* The mask used to set the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field value. */
179 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET_MSK 0x00000002
180 /* The mask used to clear the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field value. */
181 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_CLR_MSK 0xfffffffd
182 /* The reset value of the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field. */
183 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_RESET 0x1
184 /* Extracts the ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS field value from a register. */
185 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_GET(value) (((value) & 0x00000002) >> 1)
186 /* Produces a ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS register field value suitable for setting the register. */
187 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET(value) (((value) << 1) & 0x00000002)
188 
189 /*
190  * Field : CNT_RSTA
191  *
192  * Enable to reset internal single-bit error counter A value to zero
193  *
194  * Field Access Macros:
195  *
196  */
197 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field. */
198 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_LSB 8
199 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field. */
200 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_MSB 8
201 /* The width in bits of the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field. */
202 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_WIDTH 1
203 /* The mask used to set the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field value. */
204 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
205 /* The mask used to clear the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field value. */
206 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
207 /* The reset value of the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field. */
208 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_RESET 0x0
209 /* Extracts the ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA field value from a register. */
210 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
211 /* Produces a ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA register field value suitable for setting the register. */
212 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
213 
214 /*
215  * Field : INITA
216  *
217  * Enable for the hardware memory initialization PORTA.
218  *
219  * Field Access Macros:
220  *
221  */
222 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_CTL_INITA register field. */
223 #define ALT_ECC_OCRAM_ECC_CTL_INITA_LSB 16
224 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_CTL_INITA register field. */
225 #define ALT_ECC_OCRAM_ECC_CTL_INITA_MSB 16
226 /* The width in bits of the ALT_ECC_OCRAM_ECC_CTL_INITA register field. */
227 #define ALT_ECC_OCRAM_ECC_CTL_INITA_WIDTH 1
228 /* The mask used to set the ALT_ECC_OCRAM_ECC_CTL_INITA register field value. */
229 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET_MSK 0x00010000
230 /* The mask used to clear the ALT_ECC_OCRAM_ECC_CTL_INITA register field value. */
231 #define ALT_ECC_OCRAM_ECC_CTL_INITA_CLR_MSK 0xfffeffff
232 /* The reset value of the ALT_ECC_OCRAM_ECC_CTL_INITA register field. */
233 #define ALT_ECC_OCRAM_ECC_CTL_INITA_RESET 0x0
234 /* Extracts the ALT_ECC_OCRAM_ECC_CTL_INITA field value from a register. */
235 #define ALT_ECC_OCRAM_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
236 /* Produces a ALT_ECC_OCRAM_ECC_CTL_INITA register field value suitable for setting the register. */
237 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
238 
239 #ifndef __ASSEMBLY__
240 /*
241  * WARNING: The C register and register group struct declarations are provided for
242  * convenience and illustrative purposes. They should, however, be used with
243  * caution as the C language standard provides no guarantees about the alignment or
244  * atomicity of device memory accesses. The recommended practice for writing
245  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
246  * alt_write_word() functions.
247  *
248  * The struct declaration for register ALT_ECC_OCRAM_ECC_CTL.
249  */
250 struct ALT_ECC_OCRAM_ECC_CTL_s
251 {
252  uint32_t ECC_EN : 1; /* ALT_ECC_OCRAM_ECC_CTL_ECC_EN */
253  uint32_t ECC_SLVERR_DIS : 1; /* ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS */
254  uint32_t : 6; /* *UNDEFINED* */
255  uint32_t CNT_RSTA : 1; /* ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA */
256  uint32_t : 7; /* *UNDEFINED* */
257  uint32_t INITA : 1; /* ALT_ECC_OCRAM_ECC_CTL_INITA */
258  uint32_t : 15; /* *UNDEFINED* */
259 };
260 
261 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_CTL. */
262 typedef volatile struct ALT_ECC_OCRAM_ECC_CTL_s ALT_ECC_OCRAM_ECC_CTL_t;
263 #endif /* __ASSEMBLY__ */
264 
265 /* The reset value of the ALT_ECC_OCRAM_ECC_CTL register. */
266 #define ALT_ECC_OCRAM_ECC_CTL_RESET 0x00000002
267 /* The byte offset of the ALT_ECC_OCRAM_ECC_CTL register from the beginning of the component. */
268 #define ALT_ECC_OCRAM_ECC_CTL_OFST 0x8
269 
270 /*
271  * Register : INITSTAT
272  *
273  * This bit is used to set the initialize the memory and ecc to a known value
274  *
275  * Register Layout
276  *
277  * Bits | Access | Reset | Description
278  * :-------|:-------|:------|:-----------------------------------------
279  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA
280  * [31:1] | ??? | 0x0 | *UNDEFINED*
281  *
282  */
283 /*
284  * Field : INITCOMPLETEA
285  *
286  * This bit is used to verify if the hardware memory initialization has completed
287  * PORTB.
288  *
289  * Field Access Macros:
290  *
291  */
292 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field. */
293 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_LSB 0
294 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field. */
295 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_MSB 0
296 /* The width in bits of the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field. */
297 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
298 /* The mask used to set the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field value. */
299 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
300 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field value. */
301 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
302 /* The reset value of the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field. */
303 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
304 /* Extracts the ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA field value from a register. */
305 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
306 /* Produces a ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA register field value suitable for setting the register. */
307 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
308 
309 #ifndef __ASSEMBLY__
310 /*
311  * WARNING: The C register and register group struct declarations are provided for
312  * convenience and illustrative purposes. They should, however, be used with
313  * caution as the C language standard provides no guarantees about the alignment or
314  * atomicity of device memory accesses. The recommended practice for writing
315  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
316  * alt_write_word() functions.
317  *
318  * The struct declaration for register ALT_ECC_OCRAM_ECC_INITSTAT.
319  */
320 struct ALT_ECC_OCRAM_ECC_INITSTAT_s
321 {
322  uint32_t INITCOMPLETEA : 1; /* ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA */
323  uint32_t : 31; /* *UNDEFINED* */
324 };
325 
326 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_INITSTAT. */
327 typedef volatile struct ALT_ECC_OCRAM_ECC_INITSTAT_s ALT_ECC_OCRAM_ECC_INITSTAT_t;
328 #endif /* __ASSEMBLY__ */
329 
330 /* The reset value of the ALT_ECC_OCRAM_ECC_INITSTAT register. */
331 #define ALT_ECC_OCRAM_ECC_INITSTAT_RESET 0x00000000
332 /* The byte offset of the ALT_ECC_OCRAM_ECC_INITSTAT register from the beginning of the component. */
333 #define ALT_ECC_OCRAM_ECC_INITSTAT_OFST 0xc
334 
335 /*
336  * Register : ERRINTEN
337  *
338  * Error Interrupt enable
339  *
340  * Register Layout
341  *
342  * Bits | Access | Reset | Description
343  * :-------|:-------|:------|:-------------------------------------
344  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN
345  * [31:1] | ??? | 0x0 | *UNDEFINED*
346  *
347  */
348 /*
349  * Field : SERRINTEN
350  *
351  * This bit is used to enable the single bit error interrupt of ECC RAM system
352  *
353  * Field Access Macros:
354  *
355  */
356 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field. */
357 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_LSB 0
358 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field. */
359 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_MSB 0
360 /* The width in bits of the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field. */
361 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_WIDTH 1
362 /* The mask used to set the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field value. */
363 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
364 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field value. */
365 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
366 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field. */
367 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_RESET 0x0
368 /* Extracts the ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN field value from a register. */
369 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
370 /* Produces a ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
371 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
372 
373 #ifndef __ASSEMBLY__
374 /*
375  * WARNING: The C register and register group struct declarations are provided for
376  * convenience and illustrative purposes. They should, however, be used with
377  * caution as the C language standard provides no guarantees about the alignment or
378  * atomicity of device memory accesses. The recommended practice for writing
379  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
380  * alt_write_word() functions.
381  *
382  * The struct declaration for register ALT_ECC_OCRAM_ECC_ERRINTEN.
383  */
384 struct ALT_ECC_OCRAM_ECC_ERRINTEN_s
385 {
386  uint32_t SERRINTEN : 1; /* ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN */
387  uint32_t : 31; /* *UNDEFINED* */
388 };
389 
390 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ERRINTEN. */
391 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTEN_s ALT_ECC_OCRAM_ECC_ERRINTEN_t;
392 #endif /* __ASSEMBLY__ */
393 
394 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTEN register. */
395 #define ALT_ECC_OCRAM_ECC_ERRINTEN_RESET 0x00000000
396 /* The byte offset of the ALT_ECC_OCRAM_ECC_ERRINTEN register from the beginning of the component. */
397 #define ALT_ECC_OCRAM_ECC_ERRINTEN_OFST 0x10
398 
399 /*
400  * Register : ERRINTENS
401  *
402  * Error Interrupt set
403  *
404  * Register Layout
405  *
406  * Bits | Access | Reset | Description
407  * :-------|:-------|:------|:-------------------------------------
408  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS
409  * [31:1] | ??? | 0x0 | *UNDEFINED*
410  *
411  */
412 /*
413  * Field : SERRINTS
414  *
415  * This bit is used to set the single-bit error interrupt bit.
416  *
417  * Field Access Macros:
418  *
419  */
420 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field. */
421 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_LSB 0
422 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field. */
423 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_MSB 0
424 /* The width in bits of the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field. */
425 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_WIDTH 1
426 /* The mask used to set the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field value. */
427 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
428 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field value. */
429 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
430 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field. */
431 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_RESET 0x0
432 /* Extracts the ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS field value from a register. */
433 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
434 /* Produces a ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS register field value suitable for setting the register. */
435 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
436 
437 #ifndef __ASSEMBLY__
438 /*
439  * WARNING: The C register and register group struct declarations are provided for
440  * convenience and illustrative purposes. They should, however, be used with
441  * caution as the C language standard provides no guarantees about the alignment or
442  * atomicity of device memory accesses. The recommended practice for writing
443  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
444  * alt_write_word() functions.
445  *
446  * The struct declaration for register ALT_ECC_OCRAM_ECC_ERRINTENS.
447  */
448 struct ALT_ECC_OCRAM_ECC_ERRINTENS_s
449 {
450  uint32_t SERRINTS : 1; /* ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS */
451  uint32_t : 31; /* *UNDEFINED* */
452 };
453 
454 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ERRINTENS. */
455 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTENS_s ALT_ECC_OCRAM_ECC_ERRINTENS_t;
456 #endif /* __ASSEMBLY__ */
457 
458 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTENS register. */
459 #define ALT_ECC_OCRAM_ECC_ERRINTENS_RESET 0x00000000
460 /* The byte offset of the ALT_ECC_OCRAM_ECC_ERRINTENS register from the beginning of the component. */
461 #define ALT_ECC_OCRAM_ECC_ERRINTENS_OFST 0x14
462 
463 /*
464  * Register : ERRINTENR
465  *
466  * Error Interrupt reset.
467  *
468  * Register Layout
469  *
470  * Bits | Access | Reset | Description
471  * :-------|:-------|:------|:-------------------------------------
472  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR
473  * [31:1] | ??? | 0x0 | *UNDEFINED*
474  *
475  */
476 /*
477  * Field : SERRINTR
478  *
479  * This bit is used to reset the single-bit error interrupt bit. o
480  *
481  * Reads reflect SERRINTEN.
482  *
483  * 1'b0: Writing of zero has no effect.
484  *
485  * 1'b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing
486  * a bitwise writing of this feature.
487  *
488  * Field Access Macros:
489  *
490  */
491 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field. */
492 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_LSB 0
493 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field. */
494 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_MSB 0
495 /* The width in bits of the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field. */
496 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_WIDTH 1
497 /* The mask used to set the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field value. */
498 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
499 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field value. */
500 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
501 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field. */
502 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_RESET 0x0
503 /* Extracts the ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR field value from a register. */
504 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
505 /* Produces a ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR register field value suitable for setting the register. */
506 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
507 
508 #ifndef __ASSEMBLY__
509 /*
510  * WARNING: The C register and register group struct declarations are provided for
511  * convenience and illustrative purposes. They should, however, be used with
512  * caution as the C language standard provides no guarantees about the alignment or
513  * atomicity of device memory accesses. The recommended practice for writing
514  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
515  * alt_write_word() functions.
516  *
517  * The struct declaration for register ALT_ECC_OCRAM_ECC_ERRINTENR.
518  */
519 struct ALT_ECC_OCRAM_ECC_ERRINTENR_s
520 {
521  uint32_t SERRINTR : 1; /* ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR */
522  uint32_t : 31; /* *UNDEFINED* */
523 };
524 
525 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ERRINTENR. */
526 typedef volatile struct ALT_ECC_OCRAM_ECC_ERRINTENR_s ALT_ECC_OCRAM_ECC_ERRINTENR_t;
527 #endif /* __ASSEMBLY__ */
528 
529 /* The reset value of the ALT_ECC_OCRAM_ECC_ERRINTENR register. */
530 #define ALT_ECC_OCRAM_ECC_ERRINTENR_RESET 0x00000000
531 /* The byte offset of the ALT_ECC_OCRAM_ECC_ERRINTENR register from the beginning of the component. */
532 #define ALT_ECC_OCRAM_ECC_ERRINTENR_OFST 0x18
533 
534 /*
535  * Register : INTMODE
536  *
537  * Reads reflect SERRINTEN.
538  *
539  * Register Layout
540  *
541  * Bits | Access | Reset | Description
542  * :--------|:-------|:------|:----------------------------------
543  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTMOD_INTMOD
544  * [7:1] | ??? | 0x0 | *UNDEFINED*
545  * [8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF
546  * [15:9] | ??? | 0x0 | *UNDEFINED*
547  * [16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP
548  * [31:17] | ??? | 0x0 | *UNDEFINED*
549  *
550  */
551 /*
552  * Field : INTMODE
553  *
554  * Interrupt mode for single-bit errors.
555  *
556  * Field Access Macros:
557  *
558  */
559 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field. */
560 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_LSB 0
561 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field. */
562 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_MSB 0
563 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field. */
564 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_WIDTH 1
565 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field value. */
566 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
567 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field value. */
568 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
569 /* The reset value of the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field. */
570 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_RESET 0x0
571 /* Extracts the ALT_ECC_OCRAM_ECC_INTMOD_INTMOD field value from a register. */
572 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
573 /* Produces a ALT_ECC_OCRAM_ECC_INTMOD_INTMOD register field value suitable for setting the register. */
574 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
575 
576 /*
577  * Field : INTONOVF
578  *
579  * Enable interrupt on overflow.
580  *
581  * Field Access Macros:
582  *
583  */
584 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field. */
585 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_LSB 8
586 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field. */
587 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_MSB 8
588 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field. */
589 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_WIDTH 1
590 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field value. */
591 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
592 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field value. */
593 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
594 /* The reset value of the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field. */
595 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_RESET 0x0
596 /* Extracts the ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF field value from a register. */
597 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
598 /* Produces a ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF register field value suitable for setting the register. */
599 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
600 
601 /*
602  * Field : INTONCMP
603  *
604  * Enable interrupt on compare.
605  *
606  * Field Access Macros:
607  *
608  */
609 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field. */
610 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_LSB 16
611 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field. */
612 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_MSB 16
613 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field. */
614 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_WIDTH 1
615 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field value. */
616 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
617 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field value. */
618 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
619 /* The reset value of the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field. */
620 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_RESET 0x0
621 /* Extracts the ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP field value from a register. */
622 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
623 /* Produces a ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP register field value suitable for setting the register. */
624 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
625 
626 #ifndef __ASSEMBLY__
627 /*
628  * WARNING: The C register and register group struct declarations are provided for
629  * convenience and illustrative purposes. They should, however, be used with
630  * caution as the C language standard provides no guarantees about the alignment or
631  * atomicity of device memory accesses. The recommended practice for writing
632  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
633  * alt_write_word() functions.
634  *
635  * The struct declaration for register ALT_ECC_OCRAM_ECC_INTMOD.
636  */
637 struct ALT_ECC_OCRAM_ECC_INTMOD_s
638 {
639  uint32_t INTMODE : 1; /* ALT_ECC_OCRAM_ECC_INTMOD_INTMOD */
640  uint32_t : 7; /* *UNDEFINED* */
641  uint32_t INTONOVF : 1; /* ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF */
642  uint32_t : 7; /* *UNDEFINED* */
643  uint32_t INTONCMP : 1; /* ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP */
644  uint32_t : 15; /* *UNDEFINED* */
645 };
646 
647 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_INTMOD. */
648 typedef volatile struct ALT_ECC_OCRAM_ECC_INTMOD_s ALT_ECC_OCRAM_ECC_INTMOD_t;
649 #endif /* __ASSEMBLY__ */
650 
651 /* The reset value of the ALT_ECC_OCRAM_ECC_INTMOD register. */
652 #define ALT_ECC_OCRAM_ECC_INTMOD_RESET 0x00000000
653 /* The byte offset of the ALT_ECC_OCRAM_ECC_INTMOD register from the beginning of the component. */
654 #define ALT_ECC_OCRAM_ECC_INTMOD_OFST 0x1c
655 
656 /*
657  * Register : INTSTAT
658  *
659  * This bit is used to enable interrupt generation on SERR lookup table overflow.
660  * When all the entries in the table are valid=1 and this is bit is enabled,
661  * serr_req signal will be asserted.
662  *
663  * Register Layout
664  *
665  * Bits | Access | Reset | Description
666  * :-------|:-------|:------|:-----------------------------------
667  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA
668  * [7:1] | ??? | 0x0 | *UNDEFINED*
669  * [8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA
670  * [31:9] | ??? | 0x0 | *UNDEFINED*
671  *
672  */
673 /*
674  * Field : SERRPENA
675  *
676  * Single-bit error pending for PORTA.
677  *
678  * Field Access Macros:
679  *
680  */
681 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field. */
682 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_LSB 0
683 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field. */
684 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_MSB 0
685 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field. */
686 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_WIDTH 1
687 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field value. */
688 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
689 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field value. */
690 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
691 /* The reset value of the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field. */
692 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_RESET 0x0
693 /* Extracts the ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA field value from a register. */
694 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
695 /* Produces a ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA register field value suitable for setting the register. */
696 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
697 
698 /*
699  * Field : DERRPENA
700  *
701  * Double-bit error pending for PORTA.
702  *
703  * Field Access Macros:
704  *
705  */
706 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field. */
707 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_LSB 8
708 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field. */
709 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_MSB 8
710 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field. */
711 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_WIDTH 1
712 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field value. */
713 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
714 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field value. */
715 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
716 /* The reset value of the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field. */
717 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_RESET 0x0
718 /* Extracts the ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA field value from a register. */
719 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
720 /* Produces a ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA register field value suitable for setting the register. */
721 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
722 
723 #ifndef __ASSEMBLY__
724 /*
725  * WARNING: The C register and register group struct declarations are provided for
726  * convenience and illustrative purposes. They should, however, be used with
727  * caution as the C language standard provides no guarantees about the alignment or
728  * atomicity of device memory accesses. The recommended practice for writing
729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
730  * alt_write_word() functions.
731  *
732  * The struct declaration for register ALT_ECC_OCRAM_ECC_INTSTAT.
733  */
734 struct ALT_ECC_OCRAM_ECC_INTSTAT_s
735 {
736  uint32_t SERRPENA : 1; /* ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA */
737  uint32_t : 7; /* *UNDEFINED* */
738  uint32_t DERRPENA : 1; /* ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA */
739  uint32_t : 23; /* *UNDEFINED* */
740 };
741 
742 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_INTSTAT. */
743 typedef volatile struct ALT_ECC_OCRAM_ECC_INTSTAT_s ALT_ECC_OCRAM_ECC_INTSTAT_t;
744 #endif /* __ASSEMBLY__ */
745 
746 /* The reset value of the ALT_ECC_OCRAM_ECC_INTSTAT register. */
747 #define ALT_ECC_OCRAM_ECC_INTSTAT_RESET 0x00000000
748 /* The byte offset of the ALT_ECC_OCRAM_ECC_INTSTAT register from the beginning of the component. */
749 #define ALT_ECC_OCRAM_ECC_INTSTAT_OFST 0x20
750 
751 /*
752  * Register : INTTEST
753  *
754  * This bits is used to test interrupt from ECC RAM to GIC
755  *
756  * Register Layout
757  *
758  * Bits | Access | Reset | Description
759  * :-------|:-------|:------|:---------------------------------
760  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTTEST_TSERRA
761  * [7:1] | ??? | 0x0 | *UNDEFINED*
762  * [8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_INTTEST_TDERRA
763  * [31:9] | ??? | 0x0 | *UNDEFINED*
764  *
765  */
766 /*
767  * Field : TSERRA
768  *
769  * Test PORTA Single-bit error.
770  *
771  * Field Access Macros:
772  *
773  */
774 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field. */
775 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_LSB 0
776 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field. */
777 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_MSB 0
778 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field. */
779 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_WIDTH 1
780 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field value. */
781 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
782 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field value. */
783 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
784 /* The reset value of the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field. */
785 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_RESET 0x0
786 /* Extracts the ALT_ECC_OCRAM_ECC_INTTEST_TSERRA field value from a register. */
787 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
788 /* Produces a ALT_ECC_OCRAM_ECC_INTTEST_TSERRA register field value suitable for setting the register. */
789 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
790 
791 /*
792  * Field : TDERRA
793  *
794  * Test PORTA Double-bit error.
795  *
796  * Field Access Macros:
797  *
798  */
799 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field. */
800 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_LSB 8
801 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field. */
802 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_MSB 8
803 /* The width in bits of the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field. */
804 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_WIDTH 1
805 /* The mask used to set the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field value. */
806 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
807 /* The mask used to clear the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field value. */
808 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
809 /* The reset value of the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field. */
810 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_RESET 0x0
811 /* Extracts the ALT_ECC_OCRAM_ECC_INTTEST_TDERRA field value from a register. */
812 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
813 /* Produces a ALT_ECC_OCRAM_ECC_INTTEST_TDERRA register field value suitable for setting the register. */
814 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
815 
816 #ifndef __ASSEMBLY__
817 /*
818  * WARNING: The C register and register group struct declarations are provided for
819  * convenience and illustrative purposes. They should, however, be used with
820  * caution as the C language standard provides no guarantees about the alignment or
821  * atomicity of device memory accesses. The recommended practice for writing
822  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
823  * alt_write_word() functions.
824  *
825  * The struct declaration for register ALT_ECC_OCRAM_ECC_INTTEST.
826  */
827 struct ALT_ECC_OCRAM_ECC_INTTEST_s
828 {
829  uint32_t TSERRA : 1; /* ALT_ECC_OCRAM_ECC_INTTEST_TSERRA */
830  uint32_t : 7; /* *UNDEFINED* */
831  uint32_t TDERRA : 1; /* ALT_ECC_OCRAM_ECC_INTTEST_TDERRA */
832  uint32_t : 23; /* *UNDEFINED* */
833 };
834 
835 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_INTTEST. */
836 typedef volatile struct ALT_ECC_OCRAM_ECC_INTTEST_s ALT_ECC_OCRAM_ECC_INTTEST_t;
837 #endif /* __ASSEMBLY__ */
838 
839 /* The reset value of the ALT_ECC_OCRAM_ECC_INTTEST register. */
840 #define ALT_ECC_OCRAM_ECC_INTTEST_RESET 0x00000000
841 /* The byte offset of the ALT_ECC_OCRAM_ECC_INTTEST register from the beginning of the component. */
842 #define ALT_ECC_OCRAM_ECC_INTTEST_OFST 0x24
843 
844 /*
845  * Register : MODSTAT
846  *
847  * Counter feature status flag
848  *
849  * Register Layout
850  *
851  * Bits | Access | Reset | Description
852  * :-------|:-------|:------|:----------------------------------
853  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA
854  * [31:1] | ??? | 0x0 | *UNDEFINED*
855  *
856  */
857 /*
858  * Field : CMPFLGA
859  *
860  * Port A compare status flag
861  *
862  * Field Access Macros:
863  *
864  */
865 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field. */
866 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_LSB 0
867 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field. */
868 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_MSB 0
869 /* The width in bits of the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field. */
870 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_WIDTH 1
871 /* The mask used to set the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field value. */
872 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
873 /* The mask used to clear the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field value. */
874 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
875 /* The reset value of the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field. */
876 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_RESET 0x0
877 /* Extracts the ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA field value from a register. */
878 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
879 /* Produces a ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA register field value suitable for setting the register. */
880 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
881 
882 #ifndef __ASSEMBLY__
883 /*
884  * WARNING: The C register and register group struct declarations are provided for
885  * convenience and illustrative purposes. They should, however, be used with
886  * caution as the C language standard provides no guarantees about the alignment or
887  * atomicity of device memory accesses. The recommended practice for writing
888  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
889  * alt_write_word() functions.
890  *
891  * The struct declaration for register ALT_ECC_OCRAM_ECC_MODSTAT.
892  */
893 struct ALT_ECC_OCRAM_ECC_MODSTAT_s
894 {
895  uint32_t CMPFLGA : 1; /* ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA */
896  uint32_t : 31; /* *UNDEFINED* */
897 };
898 
899 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_MODSTAT. */
900 typedef volatile struct ALT_ECC_OCRAM_ECC_MODSTAT_s ALT_ECC_OCRAM_ECC_MODSTAT_t;
901 #endif /* __ASSEMBLY__ */
902 
903 /* The reset value of the ALT_ECC_OCRAM_ECC_MODSTAT register. */
904 #define ALT_ECC_OCRAM_ECC_MODSTAT_RESET 0x00000000
905 /* The byte offset of the ALT_ECC_OCRAM_ECC_MODSTAT register from the beginning of the component. */
906 #define ALT_ECC_OCRAM_ECC_MODSTAT_OFST 0x28
907 
908 /*
909  * Register : DERRADDRA
910  *
911  * This register shows the address of PORTA current double-bit error. RAM size will
912  * determine the maximum number of address bits.
913  *
914  * Register Layout
915  *
916  * Bits | Access | Reset | Description
917  * :--------|:-------|:------|:---------------------------------
918  * [14:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR
919  * [31:15] | ??? | 0x0 | *UNDEFINED*
920  *
921  */
922 /*
923  * Field : Address
924  *
925  * Recent double-bit error address.
926  *
927  * Field Access Macros:
928  *
929  */
930 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field. */
931 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_LSB 0
932 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field. */
933 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_MSB 14
934 /* The width in bits of the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field. */
935 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_WIDTH 15
936 /* The mask used to set the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field value. */
937 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET_MSK 0x00007fff
938 /* The mask used to clear the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field value. */
939 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_CLR_MSK 0xffff8000
940 /* The reset value of the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field. */
941 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_RESET 0x0
942 /* Extracts the ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR field value from a register. */
943 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
944 /* Produces a ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR register field value suitable for setting the register. */
945 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
946 
947 #ifndef __ASSEMBLY__
948 /*
949  * WARNING: The C register and register group struct declarations are provided for
950  * convenience and illustrative purposes. They should, however, be used with
951  * caution as the C language standard provides no guarantees about the alignment or
952  * atomicity of device memory accesses. The recommended practice for writing
953  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
954  * alt_write_word() functions.
955  *
956  * The struct declaration for register ALT_ECC_OCRAM_ECC_DERRADDRA.
957  */
958 struct ALT_ECC_OCRAM_ECC_DERRADDRA_s
959 {
960  uint32_t Address : 15; /* ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR */
961  uint32_t : 17; /* *UNDEFINED* */
962 };
963 
964 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_DERRADDRA. */
965 typedef volatile struct ALT_ECC_OCRAM_ECC_DERRADDRA_s ALT_ECC_OCRAM_ECC_DERRADDRA_t;
966 #endif /* __ASSEMBLY__ */
967 
968 /* The reset value of the ALT_ECC_OCRAM_ECC_DERRADDRA register. */
969 #define ALT_ECC_OCRAM_ECC_DERRADDRA_RESET 0x00000000
970 /* The byte offset of the ALT_ECC_OCRAM_ECC_DERRADDRA register from the beginning of the component. */
971 #define ALT_ECC_OCRAM_ECC_DERRADDRA_OFST 0x2c
972 
973 /*
974  * Register : SERRADDRA
975  *
976  * This register shows the address of PORTA current single-bit error. RAM size will
977  * determine the maximum number of address bits.
978  *
979  * Register Layout
980  *
981  * Bits | Access | Reset | Description
982  * :--------|:-------|:------|:---------------------------------
983  * [14:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR
984  * [31:15] | ??? | 0x0 | *UNDEFINED*
985  *
986  */
987 /*
988  * Field : Address
989  *
990  * Recent single-bit error address.
991  *
992  * Field Access Macros:
993  *
994  */
995 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field. */
996 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_LSB 0
997 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field. */
998 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_MSB 14
999 /* The width in bits of the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field. */
1000 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_WIDTH 15
1001 /* The mask used to set the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field value. */
1002 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET_MSK 0x00007fff
1003 /* The mask used to clear the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field value. */
1004 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_CLR_MSK 0xffff8000
1005 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field. */
1006 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_RESET 0x0
1007 /* Extracts the ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR field value from a register. */
1008 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
1009 /* Produces a ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR register field value suitable for setting the register. */
1010 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
1011 
1012 #ifndef __ASSEMBLY__
1013 /*
1014  * WARNING: The C register and register group struct declarations are provided for
1015  * convenience and illustrative purposes. They should, however, be used with
1016  * caution as the C language standard provides no guarantees about the alignment or
1017  * atomicity of device memory accesses. The recommended practice for writing
1018  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1019  * alt_write_word() functions.
1020  *
1021  * The struct declaration for register ALT_ECC_OCRAM_ECC_SERRADDRA.
1022  */
1023 struct ALT_ECC_OCRAM_ECC_SERRADDRA_s
1024 {
1025  uint32_t Address : 15; /* ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR */
1026  uint32_t : 17; /* *UNDEFINED* */
1027 };
1028 
1029 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_SERRADDRA. */
1030 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRADDRA_s ALT_ECC_OCRAM_ECC_SERRADDRA_t;
1031 #endif /* __ASSEMBLY__ */
1032 
1033 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRADDRA register. */
1034 #define ALT_ECC_OCRAM_ECC_SERRADDRA_RESET 0x00000000
1035 /* The byte offset of the ALT_ECC_OCRAM_ECC_SERRADDRA register from the beginning of the component. */
1036 #define ALT_ECC_OCRAM_ECC_SERRADDRA_OFST 0x30
1037 
1038 /*
1039  * Register : SERRCNTREG
1040  *
1041  * Maximum counter value for single-bit error interrupt
1042  *
1043  * Register Layout
1044  *
1045  * Bits | Access | Reset | Description
1046  * :-------|:-------|:------|:-------------------------------------
1047  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT
1048  *
1049  */
1050 /*
1051  * Field : SERRCNT
1052  *
1053  * Counter value
1054  *
1055  * Field Access Macros:
1056  *
1057  */
1058 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field. */
1059 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_LSB 0
1060 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field. */
1061 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_MSB 31
1062 /* The width in bits of the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field. */
1063 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1064 /* The mask used to set the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field value. */
1065 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1066 /* The mask used to clear the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field value. */
1067 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1068 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field. */
1069 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1070 /* Extracts the ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT field value from a register. */
1071 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1072 /* Produces a ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
1073 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1074 
1075 #ifndef __ASSEMBLY__
1076 /*
1077  * WARNING: The C register and register group struct declarations are provided for
1078  * convenience and illustrative purposes. They should, however, be used with
1079  * caution as the C language standard provides no guarantees about the alignment or
1080  * atomicity of device memory accesses. The recommended practice for writing
1081  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1082  * alt_write_word() functions.
1083  *
1084  * The struct declaration for register ALT_ECC_OCRAM_ECC_SERRCNTREG.
1085  */
1086 struct ALT_ECC_OCRAM_ECC_SERRCNTREG_s
1087 {
1088  uint32_t SERRCNT : 32; /* ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT */
1089 };
1090 
1091 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_SERRCNTREG. */
1092 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRCNTREG_s ALT_ECC_OCRAM_ECC_SERRCNTREG_t;
1093 #endif /* __ASSEMBLY__ */
1094 
1095 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRCNTREG register. */
1096 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_RESET 0x00000000
1097 /* The byte offset of the ALT_ECC_OCRAM_ECC_SERRCNTREG register from the beginning of the component. */
1098 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_OFST 0x3c
1099 
1100 /*
1101  * Register : ECC_Addrbus
1102  *
1103  * MSB bit of address is determined by ADR.
1104  *
1105  * Register Layout
1106  *
1107  * Bits | Access | Reset | Description
1108  * :--------|:-------|:------|:------------------------------------------
1109  * [14:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS
1110  * [31:15] | ??? | 0x0 | *UNDEFINED*
1111  *
1112  */
1113 /*
1114  * Field : ECC_AddrBUS
1115  *
1116  * Address will be driven to RAM to either read or write the data. Address will be
1117  * latched by the RAM when the Enbus is asserted.
1118  *
1119  * Field Access Macros:
1120  *
1121  */
1122 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1123 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1124 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1125 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 14
1126 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1127 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 15
1128 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1129 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x00007fff
1130 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1131 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffff8000
1132 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1133 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1134 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS field value from a register. */
1135 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x00007fff) >> 0)
1136 /* Produces a ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value suitable for setting the register. */
1137 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x00007fff)
1138 
1139 #ifndef __ASSEMBLY__
1140 /*
1141  * WARNING: The C register and register group struct declarations are provided for
1142  * convenience and illustrative purposes. They should, however, be used with
1143  * caution as the C language standard provides no guarantees about the alignment or
1144  * atomicity of device memory accesses. The recommended practice for writing
1145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1146  * alt_write_word() functions.
1147  *
1148  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_ADDRBUS.
1149  */
1150 struct ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_s
1151 {
1152  uint32_t ECC_AddrBUS : 15; /* ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS */
1153  uint32_t : 17; /* *UNDEFINED* */
1154 };
1155 
1156 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_ADDRBUS. */
1157 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_s ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_t;
1158 #endif /* __ASSEMBLY__ */
1159 
1160 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS register. */
1161 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_RESET 0x00000000
1162 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_ADDRBUS register from the beginning of the component. */
1163 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_OFST 0x40
1164 
1165 /*
1166  * Register : ECC_RData0bus
1167  *
1168  * Data will be read to this register field.
1169  *
1170  * Register Layout
1171  *
1172  * Bits | Access | Reset | Description
1173  * :-------|:-------|:------|:---------------------------------------------
1174  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS
1175  *
1176  */
1177 /*
1178  * Field : ECC_RDataBUS
1179  *
1180  * ECC_RDataBUS[31:0].
1181  *
1182  * Field Access Macros:
1183  *
1184  */
1185 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1186 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1187 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1188 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1189 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1190 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1191 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
1192 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1193 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
1194 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1195 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1196 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1197 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS field value from a register. */
1198 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1199 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value suitable for setting the register. */
1200 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1201 
1202 #ifndef __ASSEMBLY__
1203 /*
1204  * WARNING: The C register and register group struct declarations are provided for
1205  * convenience and illustrative purposes. They should, however, be used with
1206  * caution as the C language standard provides no guarantees about the alignment or
1207  * atomicity of device memory accesses. The recommended practice for writing
1208  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1209  * alt_write_word() functions.
1210  *
1211  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS.
1212  */
1213 struct ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_s
1214 {
1215  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS */
1216 };
1217 
1218 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS. */
1219 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_t;
1220 #endif /* __ASSEMBLY__ */
1221 
1222 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS register. */
1223 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_RESET 0x00000000
1224 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS register from the beginning of the component. */
1225 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_OFST 0x44
1226 
1227 /*
1228  * Register : ECC_RData1bus
1229  *
1230  * Data will be read to this register field.
1231  *
1232  * Register Layout
1233  *
1234  * Bits | Access | Reset | Description
1235  * :-------|:-------|:------|:---------------------------------------------
1236  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS
1237  *
1238  */
1239 /*
1240  * Field : ECC_RDataBUS
1241  *
1242  * ECC_RDataBUS[63:32].
1243  *
1244  * Field Access Macros:
1245  *
1246  */
1247 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1248 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1249 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1250 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 31
1251 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1252 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1253 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
1254 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1255 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
1256 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1257 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1258 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1259 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS field value from a register. */
1260 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1261 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value suitable for setting the register. */
1262 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1263 
1264 #ifndef __ASSEMBLY__
1265 /*
1266  * WARNING: The C register and register group struct declarations are provided for
1267  * convenience and illustrative purposes. They should, however, be used with
1268  * caution as the C language standard provides no guarantees about the alignment or
1269  * atomicity of device memory accesses. The recommended practice for writing
1270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1271  * alt_write_word() functions.
1272  *
1273  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS.
1274  */
1275 struct ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_s
1276 {
1277  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS */
1278 };
1279 
1280 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS. */
1281 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_t;
1282 #endif /* __ASSEMBLY__ */
1283 
1284 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS register. */
1285 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_RESET 0x00000000
1286 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS register from the beginning of the component. */
1287 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_OFST 0x48
1288 
1289 /*
1290  * Register : ECC_RData2bus
1291  *
1292  * Data will be read to this register field.
1293  *
1294  * Register Layout
1295  *
1296  * Bits | Access | Reset | Description
1297  * :-------|:-------|:------|:---------------------------------------------
1298  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS
1299  *
1300  */
1301 /*
1302  * Field : ECC_RDataBUS
1303  *
1304  * ECC_RDataBUS[95:64].
1305  *
1306  * Field Access Macros:
1307  *
1308  */
1309 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1310 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1311 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1312 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1313 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1314 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1315 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
1316 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1317 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
1318 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1319 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1320 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1321 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS field value from a register. */
1322 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1323 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value suitable for setting the register. */
1324 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1325 
1326 #ifndef __ASSEMBLY__
1327 /*
1328  * WARNING: The C register and register group struct declarations are provided for
1329  * convenience and illustrative purposes. They should, however, be used with
1330  * caution as the C language standard provides no guarantees about the alignment or
1331  * atomicity of device memory accesses. The recommended practice for writing
1332  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1333  * alt_write_word() functions.
1334  *
1335  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS.
1336  */
1337 struct ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_s
1338 {
1339  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS */
1340 };
1341 
1342 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS. */
1343 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_t;
1344 #endif /* __ASSEMBLY__ */
1345 
1346 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS register. */
1347 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_RESET 0x00000000
1348 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS register from the beginning of the component. */
1349 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_OFST 0x4c
1350 
1351 /*
1352  * Register : ECC_RData3bus
1353  *
1354  * Data will be read to this register field.
1355  *
1356  * Register Layout
1357  *
1358  * Bits | Access | Reset | Description
1359  * :-------|:-------|:------|:---------------------------------------------
1360  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS
1361  *
1362  */
1363 /*
1364  * Field : ECC_RDataBUS
1365  *
1366  * ECC_RDataBUS[127-96].
1367  *
1368  * Field Access Macros:
1369  *
1370  */
1371 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1372 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1373 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1374 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1375 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1376 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1377 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
1378 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1379 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
1380 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1381 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1382 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1383 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS field value from a register. */
1384 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1385 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value suitable for setting the register. */
1386 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1387 
1388 #ifndef __ASSEMBLY__
1389 /*
1390  * WARNING: The C register and register group struct declarations are provided for
1391  * convenience and illustrative purposes. They should, however, be used with
1392  * caution as the C language standard provides no guarantees about the alignment or
1393  * atomicity of device memory accesses. The recommended practice for writing
1394  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1395  * alt_write_word() functions.
1396  *
1397  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS.
1398  */
1399 struct ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_s
1400 {
1401  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS */
1402 };
1403 
1404 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS. */
1405 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_t;
1406 #endif /* __ASSEMBLY__ */
1407 
1408 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS register. */
1409 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_RESET 0x00000000
1410 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS register from the beginning of the component. */
1411 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_OFST 0x50
1412 
1413 /*
1414  * Register : ECC_WData0bus
1415  *
1416  * Data from the register will be written to the RAM.
1417  *
1418  * Register Layout
1419  *
1420  * Bits | Access | Reset | Description
1421  * :-------|:-------|:------|:---------------------------------------------
1422  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS
1423  *
1424  */
1425 /*
1426  * Field : ECC_WDataBUS
1427  *
1428  * ECC_WDataBUS[31:0].
1429  *
1430  * Field Access Macros:
1431  *
1432  */
1433 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1434 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1435 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1436 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1437 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1438 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1439 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
1440 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1441 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
1442 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1443 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1444 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1445 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS field value from a register. */
1446 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1447 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value suitable for setting the register. */
1448 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1449 
1450 #ifndef __ASSEMBLY__
1451 /*
1452  * WARNING: The C register and register group struct declarations are provided for
1453  * convenience and illustrative purposes. They should, however, be used with
1454  * caution as the C language standard provides no guarantees about the alignment or
1455  * atomicity of device memory accesses. The recommended practice for writing
1456  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1457  * alt_write_word() functions.
1458  *
1459  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS.
1460  */
1461 struct ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_s
1462 {
1463  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS */
1464 };
1465 
1466 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS. */
1467 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_t;
1468 #endif /* __ASSEMBLY__ */
1469 
1470 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS register. */
1471 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_RESET 0x00000000
1472 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS register from the beginning of the component. */
1473 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_OFST 0x54
1474 
1475 /*
1476  * Register : ECC_WData1bus
1477  *
1478  * Data from the register will be written to the RAM.
1479  *
1480  * Register Layout
1481  *
1482  * Bits | Access | Reset | Description
1483  * :-------|:-------|:------|:---------------------------------------------
1484  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS
1485  *
1486  */
1487 /*
1488  * Field : ECC_WDataBUS
1489  *
1490  * ECC_WDataBUS[63:32].
1491  *
1492  * Field Access Macros:
1493  *
1494  */
1495 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1496 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1497 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1498 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 31
1499 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1500 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1501 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
1502 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1503 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
1504 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1505 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1506 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1507 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS field value from a register. */
1508 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1509 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value suitable for setting the register. */
1510 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1511 
1512 #ifndef __ASSEMBLY__
1513 /*
1514  * WARNING: The C register and register group struct declarations are provided for
1515  * convenience and illustrative purposes. They should, however, be used with
1516  * caution as the C language standard provides no guarantees about the alignment or
1517  * atomicity of device memory accesses. The recommended practice for writing
1518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1519  * alt_write_word() functions.
1520  *
1521  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS.
1522  */
1523 struct ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_s
1524 {
1525  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS */
1526 };
1527 
1528 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS. */
1529 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_t;
1530 #endif /* __ASSEMBLY__ */
1531 
1532 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS register. */
1533 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_RESET 0x00000000
1534 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS register from the beginning of the component. */
1535 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_OFST 0x58
1536 
1537 /*
1538  * Register : ECC_WData2bus
1539  *
1540  * Data from the register will be written to the RAM.
1541  *
1542  * Register Layout
1543  *
1544  * Bits | Access | Reset | Description
1545  * :-------|:-------|:------|:---------------------------------------------
1546  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS
1547  *
1548  */
1549 /*
1550  * Field : ECC_WDataBUS
1551  *
1552  * ECC_WDataBUS[95-64].
1553  *
1554  * Field Access Macros:
1555  *
1556  */
1557 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1558 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1559 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1560 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1561 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1562 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1563 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
1564 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1565 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
1566 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1567 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1568 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1569 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS field value from a register. */
1570 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1571 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value suitable for setting the register. */
1572 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1573 
1574 #ifndef __ASSEMBLY__
1575 /*
1576  * WARNING: The C register and register group struct declarations are provided for
1577  * convenience and illustrative purposes. They should, however, be used with
1578  * caution as the C language standard provides no guarantees about the alignment or
1579  * atomicity of device memory accesses. The recommended practice for writing
1580  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1581  * alt_write_word() functions.
1582  *
1583  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS.
1584  */
1585 struct ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_s
1586 {
1587  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS */
1588 };
1589 
1590 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS. */
1591 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_t;
1592 #endif /* __ASSEMBLY__ */
1593 
1594 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS register. */
1595 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_RESET 0x00000000
1596 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS register from the beginning of the component. */
1597 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_OFST 0x5c
1598 
1599 /*
1600  * Register : ECC_WData3bus
1601  *
1602  * Data from the register will be written to the RAM.
1603  *
1604  * Register Layout
1605  *
1606  * Bits | Access | Reset | Description
1607  * :-------|:-------|:------|:---------------------------------------------
1608  * [31:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS
1609  *
1610  */
1611 /*
1612  * Field : ECC_WDataBUS
1613  *
1614  * ECC_WDataBUS[127-96].
1615  *
1616  * Field Access Macros:
1617  *
1618  */
1619 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1620 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1621 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1622 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1623 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1624 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1625 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
1626 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1627 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
1628 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1629 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1630 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1631 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS field value from a register. */
1632 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1633 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value suitable for setting the register. */
1634 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1635 
1636 #ifndef __ASSEMBLY__
1637 /*
1638  * WARNING: The C register and register group struct declarations are provided for
1639  * convenience and illustrative purposes. They should, however, be used with
1640  * caution as the C language standard provides no guarantees about the alignment or
1641  * atomicity of device memory accesses. The recommended practice for writing
1642  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1643  * alt_write_word() functions.
1644  *
1645  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS.
1646  */
1647 struct ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_s
1648 {
1649  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS */
1650 };
1651 
1652 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS. */
1653 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_t;
1654 #endif /* __ASSEMBLY__ */
1655 
1656 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS register. */
1657 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_RESET 0x00000000
1658 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS register from the beginning of the component. */
1659 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_OFST 0x60
1660 
1661 /*
1662  * Register : ECC_RDataecc0bus
1663  *
1664  * The msb bit for the register is configured based on DAT parameter (RAM word
1665  * size). Unimplemented bytes of this register will be reserved.
1666  *
1667  * Register Layout
1668  *
1669  * Bits | Access | Reset | Description
1670  * :--------|:-------|:------|:----------------------------------------------------
1671  * [4:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS
1672  * [7:5] | ??? | 0x0 | *UNDEFINED*
1673  * [12:8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS
1674  * [15:13] | ??? | 0x0 | *UNDEFINED*
1675  * [20:16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS
1676  * [23:21] | ??? | 0x0 | *UNDEFINED*
1677  * [28:24] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS
1678  * [31:29] | ??? | 0x0 | *UNDEFINED*
1679  *
1680  */
1681 /*
1682  * Field : ECC_RDataecc0BUS
1683  *
1684  * Eccdata will be read to this register field.
1685  *
1686  * Field Access Macros:
1687  *
1688  */
1689 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1690 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1691 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1692 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 4
1693 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1694 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 5
1695 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1696 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000001f
1697 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1698 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffffe0
1699 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1700 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1701 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register. */
1702 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
1703 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register. */
1704 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
1705 
1706 /*
1707  * Field : ECC_RDataecc1BUS
1708  *
1709  * Eccdata will be read to this register field.
1710  *
1711  * Field Access Macros:
1712  *
1713  */
1714 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1715 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1716 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1717 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 12
1718 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1719 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 5
1720 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1721 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00001f00
1722 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1723 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffffe0ff
1724 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1725 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1726 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register. */
1727 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
1728 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register. */
1729 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
1730 
1731 /*
1732  * Field : ECC_RDataecc2BUS
1733  *
1734  * Eccdata will be read to this register field.
1735  *
1736  * Field Access Macros:
1737  *
1738  */
1739 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1740 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1741 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1742 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 20
1743 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1744 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 5
1745 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1746 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x001f0000
1747 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1748 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xffe0ffff
1749 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1750 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1751 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register. */
1752 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
1753 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register. */
1754 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
1755 
1756 /*
1757  * Field : ECC_RDataecc3BUS
1758  *
1759  * Eccdata will be read to this register field.
1760  *
1761  * Field Access Macros:
1762  *
1763  */
1764 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1765 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1766 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1767 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 28
1768 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1769 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 5
1770 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1771 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x1f000000
1772 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1773 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0xe0ffffff
1774 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1775 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1776 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register. */
1777 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
1778 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register. */
1779 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
1780 
1781 #ifndef __ASSEMBLY__
1782 /*
1783  * WARNING: The C register and register group struct declarations are provided for
1784  * convenience and illustrative purposes. They should, however, be used with
1785  * caution as the C language standard provides no guarantees about the alignment or
1786  * atomicity of device memory accesses. The recommended practice for writing
1787  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1788  * alt_write_word() functions.
1789  *
1790  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS.
1791  */
1792 struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_s
1793 {
1794  uint32_t ECC_RDataecc0BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS */
1795  uint32_t : 3; /* *UNDEFINED* */
1796  uint32_t ECC_RDataecc1BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS */
1797  uint32_t : 3; /* *UNDEFINED* */
1798  uint32_t ECC_RDataecc2BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS */
1799  uint32_t : 3; /* *UNDEFINED* */
1800  uint32_t ECC_RDataecc3BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS */
1801  uint32_t : 3; /* *UNDEFINED* */
1802 };
1803 
1804 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS. */
1805 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_t;
1806 #endif /* __ASSEMBLY__ */
1807 
1808 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS register. */
1809 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1810 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS register from the beginning of the component. */
1811 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_OFST 0x64
1812 
1813 /*
1814  * Register : ECC_RDataecc1bus
1815  *
1816  * The msb bit for the register is configured based on DAT parameter (RAM word
1817  * size). Unimplemented bytes of this register will be reserved.
1818  *
1819  * Register Layout
1820  *
1821  * Bits | Access | Reset | Description
1822  * :--------|:-------|:------|:----------------------------------------------------
1823  * [4:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS
1824  * [7:5] | ??? | 0x0 | *UNDEFINED*
1825  * [12:8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS
1826  * [15:13] | ??? | 0x0 | *UNDEFINED*
1827  * [20:16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS
1828  * [23:21] | ??? | 0x0 | *UNDEFINED*
1829  * [28:24] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS
1830  * [31:29] | ??? | 0x0 | *UNDEFINED*
1831  *
1832  */
1833 /*
1834  * Field : ECC_RDataecc4BUS
1835  *
1836  * Eccdata will be read to this register field.
1837  *
1838  * Field Access Macros:
1839  *
1840  */
1841 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1842 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1843 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1844 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 4
1845 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1846 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 5
1847 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1848 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000001f
1849 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1850 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffffe0
1851 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1852 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1853 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS field value from a register. */
1854 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
1855 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value suitable for setting the register. */
1856 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
1857 
1858 /*
1859  * Field : ECC_RDataecc5BUS
1860  *
1861  * Eccdata will be read to this register field.
1862  *
1863  * Field Access Macros:
1864  *
1865  */
1866 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1867 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1868 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1869 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 12
1870 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1871 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 5
1872 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1873 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00001f00
1874 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1875 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffffe0ff
1876 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1877 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1878 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS field value from a register. */
1879 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
1880 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value suitable for setting the register. */
1881 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
1882 
1883 /*
1884  * Field : ECC_RDataecc6BUS
1885  *
1886  * Eccdata will be read to this register field.
1887  *
1888  * Field Access Macros:
1889  *
1890  */
1891 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1892 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1893 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1894 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 20
1895 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1896 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 5
1897 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1898 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x001f0000
1899 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1900 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xffe0ffff
1901 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1902 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1903 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS field value from a register. */
1904 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
1905 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value suitable for setting the register. */
1906 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
1907 
1908 /*
1909  * Field : ECC_RDataecc7BUS
1910  *
1911  * Eccdata will be read to this register field.
1912  *
1913  * Field Access Macros:
1914  *
1915  */
1916 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1917 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1918 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1919 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 28
1920 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1921 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 5
1922 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1923 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x1f000000
1924 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1925 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0xe0ffffff
1926 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1927 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1928 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS field value from a register. */
1929 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
1930 /* Produces a ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value suitable for setting the register. */
1931 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
1932 
1933 #ifndef __ASSEMBLY__
1934 /*
1935  * WARNING: The C register and register group struct declarations are provided for
1936  * convenience and illustrative purposes. They should, however, be used with
1937  * caution as the C language standard provides no guarantees about the alignment or
1938  * atomicity of device memory accesses. The recommended practice for writing
1939  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1940  * alt_write_word() functions.
1941  *
1942  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS.
1943  */
1944 struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_s
1945 {
1946  uint32_t ECC_RDataecc4BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS */
1947  uint32_t : 3; /* *UNDEFINED* */
1948  uint32_t ECC_RDataecc5BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS */
1949  uint32_t : 3; /* *UNDEFINED* */
1950  uint32_t ECC_RDataecc6BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS */
1951  uint32_t : 3; /* *UNDEFINED* */
1952  uint32_t ECC_RDataecc7BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS */
1953  uint32_t : 3; /* *UNDEFINED* */
1954 };
1955 
1956 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS. */
1957 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_s ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_t;
1958 #endif /* __ASSEMBLY__ */
1959 
1960 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS register. */
1961 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1962 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS register from the beginning of the component. */
1963 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_OFST 0x68
1964 
1965 /*
1966  * Register : ECC_WDataecc0bus
1967  *
1968  * The msb bit for the register is configured based on DAT parameter (RAM word
1969  * size). Unimplemented bytes of this register will be reserved.
1970  *
1971  * Register Layout
1972  *
1973  * Bits | Access | Reset | Description
1974  * :--------|:-------|:------|:----------------------------------------------------
1975  * [4:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS
1976  * [7:5] | ??? | 0x0 | *UNDEFINED*
1977  * [12:8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS
1978  * [15:13] | ??? | 0x0 | *UNDEFINED*
1979  * [20:16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS
1980  * [23:21] | ??? | 0x0 | *UNDEFINED*
1981  * [28:24] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS
1982  * [31:29] | ??? | 0x0 | *UNDEFINED*
1983  *
1984  */
1985 /*
1986  * Field : ECC_WDataecc0BUS
1987  *
1988  * Eccdata from the register will be written to the RAM.
1989  *
1990  * Field Access Macros:
1991  *
1992  */
1993 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1994 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1995 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1996 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 4
1997 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1998 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 5
1999 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2000 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000001f
2001 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
2002 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffffe0
2003 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
2004 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2005 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register. */
2006 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
2007 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register. */
2008 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
2009 
2010 /*
2011  * Field : ECC_WDataecc1BUS
2012  *
2013  * Eccdata from the register will be written to the RAM.
2014  *
2015  * Field Access Macros:
2016  *
2017  */
2018 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2019 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2020 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2021 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 12
2022 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2023 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 5
2024 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2025 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00001f00
2026 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
2027 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffffe0ff
2028 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2029 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2030 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register. */
2031 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
2032 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register. */
2033 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
2034 
2035 /*
2036  * Field : ECC_WDataecc2BUS
2037  *
2038  * Eccdata from the register will be written to the RAM.
2039  *
2040  * Field Access Macros:
2041  *
2042  */
2043 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2044 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2045 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2046 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 20
2047 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2048 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 5
2049 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2050 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x001f0000
2051 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2052 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xffe0ffff
2053 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2054 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2055 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register. */
2056 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
2057 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register. */
2058 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
2059 
2060 /*
2061  * Field : ECC_WDataecc3BUS
2062  *
2063  * Eccdata from the register will be written to the RAM.
2064  *
2065  * Field Access Macros:
2066  *
2067  */
2068 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2069 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2070 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2071 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 28
2072 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2073 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 5
2074 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2075 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x1f000000
2076 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2077 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0xe0ffffff
2078 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2079 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2080 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register. */
2081 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
2082 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register. */
2083 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
2084 
2085 #ifndef __ASSEMBLY__
2086 /*
2087  * WARNING: The C register and register group struct declarations are provided for
2088  * convenience and illustrative purposes. They should, however, be used with
2089  * caution as the C language standard provides no guarantees about the alignment or
2090  * atomicity of device memory accesses. The recommended practice for writing
2091  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2092  * alt_write_word() functions.
2093  *
2094  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS.
2095  */
2096 struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s
2097 {
2098  uint32_t ECC_WDataecc0BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS */
2099  uint32_t : 3; /* *UNDEFINED* */
2100  uint32_t ECC_WDataecc1BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS */
2101  uint32_t : 3; /* *UNDEFINED* */
2102  uint32_t ECC_WDataecc2BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS */
2103  uint32_t : 3; /* *UNDEFINED* */
2104  uint32_t ECC_WDataecc3BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS */
2105  uint32_t : 3; /* *UNDEFINED* */
2106 };
2107 
2108 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS. */
2109 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_t;
2110 #endif /* __ASSEMBLY__ */
2111 
2112 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS register. */
2113 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2114 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS register from the beginning of the component. */
2115 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2116 
2117 /*
2118  * Register : ECC_WDataecc1bus
2119  *
2120  * The msb bit for the register is configured based on DAT parameter (RAM word
2121  * size). Unimplemented bytes of this register will be reserved.
2122  *
2123  * Register Layout
2124  *
2125  * Bits | Access | Reset | Description
2126  * :--------|:-------|:------|:----------------------------------------------------
2127  * [4:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS
2128  * [7:5] | ??? | 0x0 | *UNDEFINED*
2129  * [12:8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS
2130  * [15:13] | ??? | 0x0 | *UNDEFINED*
2131  * [20:16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS
2132  * [23:21] | ??? | 0x0 | *UNDEFINED*
2133  * [28:24] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS
2134  * [31:29] | ??? | 0x0 | *UNDEFINED*
2135  *
2136  */
2137 /*
2138  * Field : ECC_WDataecc4BUS
2139  *
2140  * Eccdata from the register will be written to the RAM.
2141  *
2142  * Field Access Macros:
2143  *
2144  */
2145 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2146 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2147 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2148 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 4
2149 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2150 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 5
2151 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2152 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000001f
2153 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2154 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffffe0
2155 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2156 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2157 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register. */
2158 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
2159 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register. */
2160 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
2161 
2162 /*
2163  * Field : ECC_WDataecc5BUS
2164  *
2165  * Eccdata from the register will be written to the RAM.
2166  *
2167  * Field Access Macros:
2168  *
2169  */
2170 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2171 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2172 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2173 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 12
2174 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2175 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 5
2176 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2177 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00001f00
2178 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2179 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffffe0ff
2180 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2181 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2182 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register. */
2183 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
2184 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register. */
2185 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
2186 
2187 /*
2188  * Field : ECC_WDataecc6BUS
2189  *
2190  * Eccdata from the register will be written to the RAM.
2191  *
2192  * Field Access Macros:
2193  *
2194  */
2195 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2196 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2197 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2198 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 20
2199 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2200 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 5
2201 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2202 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x001f0000
2203 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2204 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xffe0ffff
2205 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2206 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2207 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register. */
2208 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
2209 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register. */
2210 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
2211 
2212 /*
2213  * Field : ECC_WDataecc7BUS
2214  *
2215  * Eccdata from the register will be written to the RAM.
2216  *
2217  * Field Access Macros:
2218  *
2219  */
2220 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2221 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2222 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2223 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 28
2224 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2225 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 5
2226 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2227 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x1f000000
2228 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2229 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0xe0ffffff
2230 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2231 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2232 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register. */
2233 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
2234 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register. */
2235 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
2236 
2237 #ifndef __ASSEMBLY__
2238 /*
2239  * WARNING: The C register and register group struct declarations are provided for
2240  * convenience and illustrative purposes. They should, however, be used with
2241  * caution as the C language standard provides no guarantees about the alignment or
2242  * atomicity of device memory accesses. The recommended practice for writing
2243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2244  * alt_write_word() functions.
2245  *
2246  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS.
2247  */
2248 struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_s
2249 {
2250  uint32_t ECC_WDataecc4BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS */
2251  uint32_t : 3; /* *UNDEFINED* */
2252  uint32_t ECC_WDataecc5BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS */
2253  uint32_t : 3; /* *UNDEFINED* */
2254  uint32_t ECC_WDataecc6BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS */
2255  uint32_t : 3; /* *UNDEFINED* */
2256  uint32_t ECC_WDataecc7BUS : 5; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS */
2257  uint32_t : 3; /* *UNDEFINED* */
2258 };
2259 
2260 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS. */
2261 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_s ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_t;
2262 #endif /* __ASSEMBLY__ */
2263 
2264 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS register. */
2265 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2266 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS register from the beginning of the component. */
2267 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_OFST 0x70
2268 
2269 /*
2270  * Register : ECC_dbytectrl
2271  *
2272  * Max number of implemented byte enabled is DAT/8
2273  *
2274  * Register Layout
2275  *
2276  * Bits | Access | Reset | Description
2277  * :-------|:-------|:------|:------------------------------------
2278  * [7:0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN
2279  * [31:8] | ??? | 0x0 | *UNDEFINED*
2280  *
2281  */
2282 /*
2283  * Field : DBEN
2284  *
2285  * Byte or word enable for access.
2286  *
2287  * Field Access Macros:
2288  *
2289  */
2290 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field. */
2291 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_LSB 0
2292 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field. */
2293 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_MSB 7
2294 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field. */
2295 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_WIDTH 8
2296 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field value. */
2297 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x000000ff
2298 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field value. */
2299 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xffffff00
2300 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field. */
2301 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2302 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN field value from a register. */
2303 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x000000ff) >> 0)
2304 /* Produces a ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN register field value suitable for setting the register. */
2305 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x000000ff)
2306 
2307 #ifndef __ASSEMBLY__
2308 /*
2309  * WARNING: The C register and register group struct declarations are provided for
2310  * convenience and illustrative purposes. They should, however, be used with
2311  * caution as the C language standard provides no guarantees about the alignment or
2312  * atomicity of device memory accesses. The recommended practice for writing
2313  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2314  * alt_write_word() functions.
2315  *
2316  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_DBYTECTL.
2317  */
2318 struct ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_s
2319 {
2320  uint32_t DBEN : 8; /* ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN */
2321  uint32_t : 24; /* *UNDEFINED* */
2322 };
2323 
2324 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_DBYTECTL. */
2325 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_s ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_t;
2326 #endif /* __ASSEMBLY__ */
2327 
2328 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL register. */
2329 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_RESET 0x00000000
2330 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_DBYTECTL register from the beginning of the component. */
2331 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_OFST 0x74
2332 
2333 /*
2334  * Register : ECC_accctrl
2335  *
2336  * These bits determine which byte of data/ecc to write to RAM.
2337  *
2338  * Register Layout
2339  *
2340  * Bits | Access | Reset | Description
2341  * :-------|:-------|:------|:-------------------------------------
2342  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR
2343  * [1] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR
2344  * [7:2] | ??? | 0x0 | *UNDEFINED*
2345  * [8] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR
2346  * [31:9] | ??? | 0x0 | *UNDEFINED*
2347  *
2348  */
2349 /*
2350  * Field : DATAOVR
2351  *
2352  * RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode
2353  * set by ECC_RW.
2354  *
2355  * 1'b0: Data override disabled.
2356  *
2357  * 1'b1: Data override enabled.
2358  *
2359  * Field Access Macros:
2360  *
2361  */
2362 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field. */
2363 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2364 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field. */
2365 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2366 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field. */
2367 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2368 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field value. */
2369 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2370 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field value. */
2371 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2372 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field. */
2373 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2374 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR field value from a register. */
2375 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2376 /* Produces a ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR register field value suitable for setting the register. */
2377 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2378 
2379 /*
2380  * Field : ECCOVR
2381  *
2382  * ECC Data Override.
2383  *
2384  * Field Access Macros:
2385  *
2386  */
2387 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field. */
2388 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2389 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field. */
2390 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2391 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field. */
2392 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2393 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field value. */
2394 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2395 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field value. */
2396 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2397 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field. */
2398 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2399 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR field value from a register. */
2400 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2401 /* Produces a ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR register field value suitable for setting the register. */
2402 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2403 
2404 /*
2405  * Field : RDWR
2406  *
2407  * Control for read/write.
2408  *
2409  * Field Access Macros:
2410  *
2411  */
2412 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field. */
2413 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_LSB 8
2414 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field. */
2415 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_MSB 8
2416 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field. */
2417 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2418 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field value. */
2419 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2420 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field value. */
2421 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2422 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field. */
2423 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2424 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR field value from a register. */
2425 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2426 /* Produces a ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR register field value suitable for setting the register. */
2427 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2428 
2429 #ifndef __ASSEMBLY__
2430 /*
2431  * WARNING: The C register and register group struct declarations are provided for
2432  * convenience and illustrative purposes. They should, however, be used with
2433  * caution as the C language standard provides no guarantees about the alignment or
2434  * atomicity of device memory accesses. The recommended practice for writing
2435  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2436  * alt_write_word() functions.
2437  *
2438  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_ACCCTL.
2439  */
2440 struct ALT_ECC_OCRAM_ECC_ECC_ACCCTL_s
2441 {
2442  uint32_t DATAOVR : 1; /* ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR */
2443  uint32_t ECCOVR : 1; /* ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR */
2444  uint32_t : 6; /* *UNDEFINED* */
2445  uint32_t RDWR : 1; /* ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR */
2446  uint32_t : 23; /* *UNDEFINED* */
2447 };
2448 
2449 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_ACCCTL. */
2450 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_ACCCTL_s ALT_ECC_OCRAM_ECC_ECC_ACCCTL_t;
2451 #endif /* __ASSEMBLY__ */
2452 
2453 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL register. */
2454 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RESET 0x00000000
2455 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_ACCCTL register from the beginning of the component. */
2456 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_OFST 0x78
2457 
2458 /*
2459  * Register : ECC_startacc
2460  *
2461  * These bits determine which byte of data/ecc to write to RAM.
2462  *
2463  * Register Layout
2464  *
2465  * Bits | Access | Reset | Description
2466  * :--------|:-------|:------|:--------------------------------------
2467  * [15:0] | ??? | 0x0 | *UNDEFINED*
2468  * [16] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA
2469  * [31:17] | ??? | 0x0 | *UNDEFINED*
2470  *
2471  */
2472 /*
2473  * Field : ENBUSA
2474  *
2475  * Start RAM access for PORTA.
2476  *
2477  * Field Access Macros:
2478  *
2479  */
2480 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field. */
2481 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_LSB 16
2482 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field. */
2483 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_MSB 16
2484 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field. */
2485 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2486 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field value. */
2487 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2488 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field value. */
2489 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2490 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field. */
2491 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2492 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA field value from a register. */
2493 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2494 /* Produces a ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA register field value suitable for setting the register. */
2495 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2496 
2497 #ifndef __ASSEMBLY__
2498 /*
2499  * WARNING: The C register and register group struct declarations are provided for
2500  * convenience and illustrative purposes. They should, however, be used with
2501  * caution as the C language standard provides no guarantees about the alignment or
2502  * atomicity of device memory accesses. The recommended practice for writing
2503  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2504  * alt_write_word() functions.
2505  *
2506  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_STARTACC.
2507  */
2508 struct ALT_ECC_OCRAM_ECC_ECC_STARTACC_s
2509 {
2510  uint32_t : 16; /* *UNDEFINED* */
2511  uint32_t ENBUSA : 1; /* ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA */
2512  uint32_t : 15; /* *UNDEFINED* */
2513 };
2514 
2515 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_STARTACC. */
2516 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_STARTACC_s ALT_ECC_OCRAM_ECC_ECC_STARTACC_t;
2517 #endif /* __ASSEMBLY__ */
2518 
2519 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_STARTACC register. */
2520 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_RESET 0x00000000
2521 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_STARTACC register from the beginning of the component. */
2522 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_OFST 0x7c
2523 
2524 /*
2525  * Register : ECC_wdctrl
2526  *
2527  * Bits to Enable/Disable Watch Dog Timer
2528  *
2529  * Register Layout
2530  *
2531  * Bits | Access | Reset | Description
2532  * :-------|:-------|:------|:-------------------------------------
2533  * [0] | RW | 0x0 | ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM
2534  * [31:1] | ??? | 0x0 | *UNDEFINED*
2535  *
2536  */
2537 /*
2538  * Field : WDEN_RAM
2539  *
2540  * Enable watchdog timeout for OCP register access to IP RAM.
2541  *
2542  * Field Access Macros:
2543  *
2544  */
2545 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field. */
2546 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2547 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field. */
2548 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2549 /* The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field. */
2550 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2551 /* The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field value. */
2552 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2553 /* The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field value. */
2554 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2555 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field. */
2556 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2557 /* Extracts the ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM field value from a register. */
2558 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2559 /* Produces a ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM register field value suitable for setting the register. */
2560 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2561 
2562 #ifndef __ASSEMBLY__
2563 /*
2564  * WARNING: The C register and register group struct declarations are provided for
2565  * convenience and illustrative purposes. They should, however, be used with
2566  * caution as the C language standard provides no guarantees about the alignment or
2567  * atomicity of device memory accesses. The recommended practice for writing
2568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2569  * alt_write_word() functions.
2570  *
2571  * The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDCTL.
2572  */
2573 struct ALT_ECC_OCRAM_ECC_ECC_WDCTL_s
2574 {
2575  uint32_t WDEN_RAM : 1; /* ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM */
2576  uint32_t : 31; /* *UNDEFINED* */
2577 };
2578 
2579 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_ECC_WDCTL. */
2580 typedef volatile struct ALT_ECC_OCRAM_ECC_ECC_WDCTL_s ALT_ECC_OCRAM_ECC_ECC_WDCTL_t;
2581 #endif /* __ASSEMBLY__ */
2582 
2583 /* The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDCTL register. */
2584 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_RESET 0x00000000
2585 /* The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDCTL register from the beginning of the component. */
2586 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_OFST 0x80
2587 
2588 /*
2589  * Register : SERRLKUPA0
2590  *
2591  * Single-bit error address in LOOKUP TABLE for PORTA.
2592  *
2593  * Register Layout
2594  *
2595  * Bits | Access | Reset | Description
2596  * :--------|:-------|:------|:-----------------------------------
2597  * [14:0] | R | 0x0 | ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR
2598  * [30:15] | ??? | 0x0 | *UNDEFINED*
2599  * [31] | RW | 0x0 | ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID
2600  *
2601  */
2602 /*
2603  * Field : Address
2604  *
2605  * Recent Single-bit error address.
2606  *
2607  * This register shows the address of the each single-bit error. RAM size will
2608  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
2609  * 30-16 will be reserved and read as zero.
2610  *
2611  * Field Access Macros:
2612  *
2613  */
2614 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field. */
2615 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_LSB 0
2616 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field. */
2617 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_MSB 14
2618 /* The width in bits of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field. */
2619 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_WIDTH 15
2620 /* The mask used to set the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field value. */
2621 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET_MSK 0x00007fff
2622 /* The mask used to clear the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field value. */
2623 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xffff8000
2624 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field. */
2625 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_RESET 0x0
2626 /* Extracts the ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR field value from a register. */
2627 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
2628 /* Produces a ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR register field value suitable for setting the register. */
2629 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x00007fff)
2630 
2631 /*
2632  * Field : VALID
2633  *
2634  * Valid flag bit. Valid bit indicates if the address in this register is current
2635  * or stale.
2636  *
2637  * Field Access Macros:
2638  *
2639  */
2640 /* The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field. */
2641 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_LSB 31
2642 /* The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field. */
2643 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_MSB 31
2644 /* The width in bits of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field. */
2645 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_WIDTH 1
2646 /* The mask used to set the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field value. */
2647 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2648 /* The mask used to clear the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field value. */
2649 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2650 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field. */
2651 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_RESET 0x0
2652 /* Extracts the ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID field value from a register. */
2653 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2654 /* Produces a ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID register field value suitable for setting the register. */
2655 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2656 
2657 #ifndef __ASSEMBLY__
2658 /*
2659  * WARNING: The C register and register group struct declarations are provided for
2660  * convenience and illustrative purposes. They should, however, be used with
2661  * caution as the C language standard provides no guarantees about the alignment or
2662  * atomicity of device memory accesses. The recommended practice for writing
2663  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2664  * alt_write_word() functions.
2665  *
2666  * The struct declaration for register ALT_ECC_OCRAM_ECC_SERRLKUPA0.
2667  */
2668 struct ALT_ECC_OCRAM_ECC_SERRLKUPA0_s
2669 {
2670  const uint32_t Address : 15; /* ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR */
2671  uint32_t : 16; /* *UNDEFINED* */
2672  uint32_t VALID : 1; /* ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID */
2673 };
2674 
2675 /* The typedef declaration for register ALT_ECC_OCRAM_ECC_SERRLKUPA0. */
2676 typedef volatile struct ALT_ECC_OCRAM_ECC_SERRLKUPA0_s ALT_ECC_OCRAM_ECC_SERRLKUPA0_t;
2677 #endif /* __ASSEMBLY__ */
2678 
2679 /* The reset value of the ALT_ECC_OCRAM_ECC_SERRLKUPA0 register. */
2680 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_RESET 0x00000000
2681 /* The byte offset of the ALT_ECC_OCRAM_ECC_SERRLKUPA0 register from the beginning of the component. */
2682 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_OFST 0x90
2683 
2684 #ifndef __ASSEMBLY__
2685 /*
2686  * WARNING: The C register and register group struct declarations are provided for
2687  * convenience and illustrative purposes. They should, however, be used with
2688  * caution as the C language standard provides no guarantees about the alignment or
2689  * atomicity of device memory accesses. The recommended practice for writing
2690  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2691  * alt_write_word() functions.
2692  *
2693  * The struct declaration for register group ALT_ECC_OCRAM_ECC.
2694  */
2695 struct ALT_ECC_OCRAM_ECC_s
2696 {
2697  ALT_ECC_OCRAM_ECC_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_OCRAM_ECC_IP_REV_ID */
2698  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2699  ALT_ECC_OCRAM_ECC_CTL_t CTRL; /* ALT_ECC_OCRAM_ECC_CTL */
2700  ALT_ECC_OCRAM_ECC_INITSTAT_t INITSTAT; /* ALT_ECC_OCRAM_ECC_INITSTAT */
2701  ALT_ECC_OCRAM_ECC_ERRINTEN_t ERRINTEN; /* ALT_ECC_OCRAM_ECC_ERRINTEN */
2702  ALT_ECC_OCRAM_ECC_ERRINTENS_t ERRINTENS; /* ALT_ECC_OCRAM_ECC_ERRINTENS */
2703  ALT_ECC_OCRAM_ECC_ERRINTENR_t ERRINTENR; /* ALT_ECC_OCRAM_ECC_ERRINTENR */
2704  ALT_ECC_OCRAM_ECC_INTMOD_t INTMODE; /* ALT_ECC_OCRAM_ECC_INTMOD */
2705  ALT_ECC_OCRAM_ECC_INTSTAT_t INTSTAT; /* ALT_ECC_OCRAM_ECC_INTSTAT */
2706  ALT_ECC_OCRAM_ECC_INTTEST_t INTTEST; /* ALT_ECC_OCRAM_ECC_INTTEST */
2707  ALT_ECC_OCRAM_ECC_MODSTAT_t MODSTAT; /* ALT_ECC_OCRAM_ECC_MODSTAT */
2708  ALT_ECC_OCRAM_ECC_DERRADDRA_t DERRADDRA; /* ALT_ECC_OCRAM_ECC_DERRADDRA */
2709  ALT_ECC_OCRAM_ECC_SERRADDRA_t SERRADDRA; /* ALT_ECC_OCRAM_ECC_SERRADDRA */
2710  volatile uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2711  ALT_ECC_OCRAM_ECC_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_OCRAM_ECC_SERRCNTREG */
2712  ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_t ECC_Addrbus; /* ALT_ECC_OCRAM_ECC_ECC_ADDRBUS */
2713  ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_t ECC_RData0bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS */
2714  ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_t ECC_RData1bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS */
2715  ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_t ECC_RData2bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS */
2716  ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_t ECC_RData3bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS */
2717  ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_t ECC_WData0bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS */
2718  ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_t ECC_WData1bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS */
2719  ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_t ECC_WData2bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS */
2720  ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_t ECC_WData3bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS */
2721  ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS */
2722  ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS */
2723  ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS */
2724  ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS */
2725  ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_t ECC_dbytectrl; /* ALT_ECC_OCRAM_ECC_ECC_DBYTECTL */
2726  ALT_ECC_OCRAM_ECC_ECC_ACCCTL_t ECC_accctrl; /* ALT_ECC_OCRAM_ECC_ECC_ACCCTL */
2727  ALT_ECC_OCRAM_ECC_ECC_STARTACC_t ECC_startacc; /* ALT_ECC_OCRAM_ECC_ECC_STARTACC */
2728  ALT_ECC_OCRAM_ECC_ECC_WDCTL_t ECC_wdctrl; /* ALT_ECC_OCRAM_ECC_ECC_WDCTL */
2729  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2730  ALT_ECC_OCRAM_ECC_SERRLKUPA0_t SERRLKUPA0; /* ALT_ECC_OCRAM_ECC_SERRLKUPA0 */
2731  volatile uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2732 };
2733 
2734 /* The typedef declaration for register group ALT_ECC_OCRAM_ECC. */
2735 typedef volatile struct ALT_ECC_OCRAM_ECC_s ALT_ECC_OCRAM_ECC_t;
2736 /* The struct declaration for the raw register contents of register group ALT_ECC_OCRAM_ECC. */
2737 struct ALT_ECC_OCRAM_ECC_raw_s
2738 {
2739  volatile uint32_t IP_REV_ID; /* ALT_ECC_OCRAM_ECC_IP_REV_ID */
2740  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2741  volatile uint32_t CTRL; /* ALT_ECC_OCRAM_ECC_CTL */
2742  volatile uint32_t INITSTAT; /* ALT_ECC_OCRAM_ECC_INITSTAT */
2743  volatile uint32_t ERRINTEN; /* ALT_ECC_OCRAM_ECC_ERRINTEN */
2744  volatile uint32_t ERRINTENS; /* ALT_ECC_OCRAM_ECC_ERRINTENS */
2745  volatile uint32_t ERRINTENR; /* ALT_ECC_OCRAM_ECC_ERRINTENR */
2746  volatile uint32_t INTMODE; /* ALT_ECC_OCRAM_ECC_INTMOD */
2747  volatile uint32_t INTSTAT; /* ALT_ECC_OCRAM_ECC_INTSTAT */
2748  volatile uint32_t INTTEST; /* ALT_ECC_OCRAM_ECC_INTTEST */
2749  volatile uint32_t MODSTAT; /* ALT_ECC_OCRAM_ECC_MODSTAT */
2750  volatile uint32_t DERRADDRA; /* ALT_ECC_OCRAM_ECC_DERRADDRA */
2751  volatile uint32_t SERRADDRA; /* ALT_ECC_OCRAM_ECC_SERRADDRA */
2752  uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2753  volatile uint32_t SERRCNTREG; /* ALT_ECC_OCRAM_ECC_SERRCNTREG */
2754  volatile uint32_t ECC_Addrbus; /* ALT_ECC_OCRAM_ECC_ECC_ADDRBUS */
2755  volatile uint32_t ECC_RData0bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS */
2756  volatile uint32_t ECC_RData1bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS */
2757  volatile uint32_t ECC_RData2bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS */
2758  volatile uint32_t ECC_RData3bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS */
2759  volatile uint32_t ECC_WData0bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS */
2760  volatile uint32_t ECC_WData1bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS */
2761  volatile uint32_t ECC_WData2bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS */
2762  volatile uint32_t ECC_WData3bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS */
2763  volatile uint32_t ECC_RDataecc0bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS */
2764  volatile uint32_t ECC_RDataecc1bus; /* ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS */
2765  volatile uint32_t ECC_WDataecc0bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS */
2766  volatile uint32_t ECC_WDataecc1bus; /* ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS */
2767  volatile uint32_t ECC_dbytectrl; /* ALT_ECC_OCRAM_ECC_ECC_DBYTECTL */
2768  volatile uint32_t ECC_accctrl; /* ALT_ECC_OCRAM_ECC_ECC_ACCCTL */
2769  volatile uint32_t ECC_startacc; /* ALT_ECC_OCRAM_ECC_ECC_STARTACC */
2770  volatile uint32_t ECC_wdctrl; /* ALT_ECC_OCRAM_ECC_ECC_WDCTL */
2771  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2772  volatile uint32_t SERRLKUPA0; /* ALT_ECC_OCRAM_ECC_SERRLKUPA0 */
2773  uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2774 };
2775 
2776 /* The typedef declaration for the raw register contents of register group ALT_ECC_OCRAM_ECC. */
2777 typedef volatile struct ALT_ECC_OCRAM_ECC_raw_s ALT_ECC_OCRAM_ECC_raw_t;
2778 #endif /* __ASSEMBLY__ */
2779 
2780 
2781 #ifdef __cplusplus
2782 }
2783 #endif /* __cplusplus */
2784 #endif /* __ALT_SOCAL_ECC_OCRAM_ECC_H__ */
2785