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alt_ethernet.h
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3  * Copyright 2017 Altera Corporation. All Rights Reserved.
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37 #ifndef __ALT_ETHERNET_H__
38 #define __ALT_ETHERNET_H__
39 
40 #include "hwlib.h"
41 #include "socal/hps.h"
42 #include "socal/alt_emac.h"
43 #include "alt_interrupt.h"
44 
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif /* __cplusplus */
49 
50 #define ETH_RESET_DELAY ((uint32_t)0x000FFFFF)
51 #define NUMBER_OF_TX_DESCRIPTORS 32
52 #define NUMBER_OF_RX_DESCRIPTORS 32
53 #define ETH_BUFFER_SIZE 1536
54 
55 typedef enum
56 {
57  ALT_ETH_RESET = 0,
58  ALT_ETH_SET = 1
59 } alt_eth_set_reset_state_t;
60 
61 typedef enum {
62  ALT_ETH_DISABLE = 0,
63  ALT_ETH_ENABLE = 1
64 } alt_eth_enable_disable_state_t;
65 
66 /* Uncomment the line below when using time stamping and/or IPv4 checksum offload */
67 /*#define USE_ALTERNATE_DESCRIPTOR_SIZE*/
68 
69 /* NOTE: this must be defined for A10 and S10 */
70 #define USE_ENHANCED_DMA_DESCRIPTORS
71 
80 typedef struct
81 {
82  uint32_t status;
84  uint32_t buffer1_addr;
86 #ifdef USE_ALTERNATE_DESCRIPTOR_SIZE
87  uint32_t extended_status; /* Extended status for PTP receive desc */
88  uint32_t reserved1; /* Reserved */
89  uint32_t time_stamp_low; /* Time Stamp Low value for transmit and receive */
90  uint32_t time_stamp_high; /* Time Stamp High value for transmit and receive */
91 #endif
93 
94 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
95 
96 /* Ethernet DMA descriptors registers bits definition */
115 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
116 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000)
117 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000)
118 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000)
119 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000)
120 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000)
121 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
122 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
123 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
124 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
125 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
126 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
127 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000)
128 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
129 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
130 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
131 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
132 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
133 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
134 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
135 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
136 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
137 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
138 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
139 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
140 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
141 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
142 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
143 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
146 /* Bit definition of TDES1 register */
147 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000)
148 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF)
150 /* Bit definition of TDES2 register */
151 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
153 /* Bit definition of TDES3 register */
154 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
156  /*---------------------------------------------------------------------------------------------
157  TDES6 | Transmit Time Stamp Low [31:0] |
158  -----------------------------------------------------------------------------------------------
159  TDES7 | Transmit Time Stamp High [31:0] |
160  ----------------------------------------------------------------------------------------------*/
161 
162 /* Bit definition of TDES6 register */
163  #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
164 
165 /* Bit definition of TDES7 register */
166  #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
167 
181 /* Bit definition of RDES0 register: DMA Rx descriptor status register */
182 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
183 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
184 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
185 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
186 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
187 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
188 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
189 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
190 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
191 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
192 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
193 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
194 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
195 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
196 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
197 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
198 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
199 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
200 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
202 /* Bit definition of RDES1 register */
203 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
204 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000)
205 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000)
206 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000)
207 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF)
209 /* Bit definition of RDES2 register */
210 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
212 /* Bit definition of RDES3 register */
213 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
215 /*---------------------------------------------------------------------------------------------------------------------
216  RDES4 | Reserved[31:15] | Extended Status [14:0] |
217  ---------------------------------------------------------------------------------------------------------------------
218  RDES5 | Reserved[31:0] |
219  ---------------------------------------------------------------------------------------------------------------------
220  RDES6 | Receive Time Stamp Low [31:0] |
221  ---------------------------------------------------------------------------------------------------------------------
222  RDES7 | Receive Time Stamp High [31:0] |
223  --------------------------------------------------------------------------------------------------------------------*/
224 
225 /* Bit definition of RDES4 register */
226 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
227 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
228 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
229 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
230 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
231 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
232 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
233 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
234 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_MANAGE ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
235 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
236 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
237 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
238 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
239 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
240 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
241 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
242 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
243 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
244 
245 /* Bit definition of RDES6 register */
246 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
247 
248 /* Bit definition of RDES7 register */
249 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
250 
251 
252 #else
255 /* Ethernet DMA descriptors registers bits definition */
256 
271 /* Bit definition of TDES0 register: DMA Tx descriptor status register */
272 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
273 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
274 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
275 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
276 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
277 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
278 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
279 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
280 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
281 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
282 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
283 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
284 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
285 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
286 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
287 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
289 /* Bit definition of TDES1 register: DMA Tx descriptor control-size register */
290 #define ETH_DMATXDESC_IC ((uint32_t)0x80000000)
291 #define ETH_DMATXDESC_LS ((uint32_t)0x40000000)
292 #define ETH_DMATXDESC_FS ((uint32_t)0x20000000)
293 #define ETH_DMATXDESC_CIC ((uint32_t)0x18000000)
294 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
295 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x08000000)
296 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x10000000)
297 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x18000000)
298 #define ETH_DMATXDESC_DC ((uint32_t)0x04000000)
299 #define ETH_DMATXDESC_TER ((uint32_t)0x02000000)
300 #define ETH_DMATXDESC_TCH ((uint32_t)0x01000000)
301 #define ETH_DMATXDESC_DP ((uint32_t)0x00800000)
302 #define ETH_DMATXDESC_TTSE ((uint32_t)0x00400000)
303 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x003FF800)
304 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x000007FF)
306 /* Bit definition of TDES2 register */
307 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF)
309 /* Bit definition of TDES3 register */
310 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF)
325 /* Bit definition of RDES0 register: DMA Rx descriptor status register */
326 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
327 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
328 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
329 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
330 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
331 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
332 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
333 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
334 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
335 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
336 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
337 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
338 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
339 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
340 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
341 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
342 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
343 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
344 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
346 /* Bit definition of RDES1 register */
347 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000)
348 #define ETH_DMARXDESC_RER ((uint32_t)0x02000000)
349 #define ETH_DMARXDESC_RCH ((uint32_t)0x01000000)
350 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x003FF800)
351 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x000007FF)
353 /* Bit definition of RDES2 register */
354 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF)
356 /* Bit definition of RDES3 register */
357 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF)
360 #endif /*#ifdef USE_ENHANCED_DMA_DESCRIPTORS*/
361 
362 
363 #ifdef USE_ENHANCED_DMA_DESCRIPTORS
364 
365  /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
366  #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
367 
368  /* ETHERNET DMA Rx descriptors Frame Length Shift */
369  #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
370 
371  /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
372  #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
373 
374 #else
375 
376  /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
377  #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 11
378 
379  /* ETHERNET DMA Rx descriptors Frame Length Shift */
380  #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
381 
382  /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
383  #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 11
384 
385 #endif
386 
387 /******************************************************************************/
399 {
400  uint32_t instance; /* This specifies the EMAC to use */
401  uint32_t tx_current_desc_number;
402  uint32_t rx_current_desc_number;
403  uint32_t rx_processed_desc_number;
404 
405  ALT_INT_INTERRUPT_t irqnum;
406  uint32_t interrupt_mask;
407  uint32_t rxints;
408  uint32_t txints;
409 
410  /* Ethernet packet buffers */
411  uint8_t rx_buf[ETH_BUFFER_SIZE * NUMBER_OF_RX_DESCRIPTORS];
412  uint8_t tx_buf[ETH_BUFFER_SIZE * NUMBER_OF_TX_DESCRIPTORS];
413 
414  /* Descriptor rings */
415  alt_eth_dma_desc_t tx_desc_ring[NUMBER_OF_TX_DESCRIPTORS];
416  alt_eth_dma_desc_t rx_desc_ring[NUMBER_OF_RX_DESCRIPTORS];
418 
419 
420 /******************************************************************************/
428 void alt_eth_delay(volatile uint32_t delay);
429 
430 /******************************************************************************/
438 void alt_eth_reset_mac(uint32_t instance);
439 
440 /******************************************************************************/
449 
450 /******************************************************************************/
459 
460 /******************************************************************************/
473 ALT_STATUS_CODE alt_eth_irq_init(alt_eth_emac_instance_t * emac, alt_int_callback_t callback);
474 
475 /******************************************************************************/
491 void alt_eth_irq_callback(uint32_t icciar, void * context);
492 
493 /******************************************************************************/
504 ALT_STATUS_CODE alt_eth_software_reset(uint32_t instance);
505 
506 /******************************************************************************/
515 void alt_eth_start(uint32_t instance);
516 
517 /******************************************************************************/
526 void alt_eth_stop(uint32_t instance);
527 
528 /******************************************************************************/
547 ALT_STATUS_CODE alt_eth_dma_mac_config(alt_eth_emac_instance_t * emac);
548 
549 /******************************************************************************/
568 ALT_STATUS_CODE alt_eth_send_packet(uint8_t * pkt, uint32_t len, uint32_t first, uint32_t last, alt_eth_emac_instance_t * emac);
569 
570 /******************************************************************************/
587 ALT_STATUS_CODE alt_eth_get_packet(uint8_t * pkt, uint32_t * len, alt_eth_emac_instance_t * emac);
588 
589 /******************************************************************************/
600 void alt_eth_mac_set_tx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
601 
602 /******************************************************************************/
613 void alt_eth_mac_set_rx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
614 
615 /******************************************************************************/
628 void alt_eth_mac_set_bpa_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
629 
630 /******************************************************************************/
642 alt_eth_enable_disable_state_t alt_eth_mac_get_bpa_state(uint32_t instance);
643 
644 /******************************************************************************/
657 void alt_eth_mac_set_irq_reg(uint32_t mac_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance);
658 
659 
660 /******************************************************************************/
672 alt_eth_set_reset_state_t alt_eth_mac_get_mii_link_state(uint32_t instance);
673 
674 /******************************************************************************/
688 alt_eth_set_reset_state_t alt_eth_mac_check_status_reg(uint32_t mac_bit_mask, uint32_t instance);
689 
690 /******************************************************************************/
701 uint32_t alt_eth_mac_get_irq_status_reg(uint32_t instance);
702 
703 /******************************************************************************/
713 void alt_eth_mac_pause_ctrl_frame(uint32_t instance);
714 
715 /******************************************************************************/
727 void alt_eth_mac_set_mac_addr(uint8_t *address, uint32_t instance);
728 
729 /******************************************************************************/
741 void alt_eth_mac_get_mac_addr(uint8_t *address, uint32_t instance);
742 
743 /******************************************************************************/
752 void alt_eth_mac_check_mii_link_status(uint32_t instance);
753 
754 /******************************************************************************/
765 uint32_t alt_eth_dma_get_status_reg(uint32_t instance);
766 
767 /******************************************************************************/
781 alt_eth_set_reset_state_t alt_eth_dma_check_status_reg(uint32_t dma_bit_mask, uint32_t instance);
782 
783 /******************************************************************************/
797 void alt_eth_dma_clear_status_bits(uint32_t dma_bit_mask, uint32_t instance);
798 
799 /******************************************************************************/
809 void alt_eth_dma_flush_tx_fifo(uint32_t instance);
810 
811 /******************************************************************************/
822 alt_eth_set_reset_state_t alt_eth_dma_get_tx_fifo_flush_state(uint32_t instance);
823 
824 /******************************************************************************/
835 void alt_eth_dma_set_tx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
836 
837 /******************************************************************************/
848 void alt_eth_dma_set_rx_state(alt_eth_enable_disable_state_t new_state, uint32_t instance);
849 
850 /******************************************************************************/
863 void alt_eth_dma_set_irq_reg(uint32_t dma_irq_mask, alt_eth_enable_disable_state_t new_state, uint32_t instance);
864 
865 /******************************************************************************/
877 alt_eth_set_reset_state_t alt_eth_dma_check_overflow_counter_reg(uint32_t dma_overflow_mask, uint32_t instance);
878 
879 /******************************************************************************/
888 uint32_t alt_eth_dma_get_curr_tx_desc_addr(uint32_t instance);
889 
890 /******************************************************************************/
899 uint32_t alt_eth_dma_get_curr_rx_desc_addr(uint32_t instance);
900 
901 /******************************************************************************/
910 uint32_t alt_eth_dma_get_curr_tx_buff_addr(uint32_t instance);
911 
912 /******************************************************************************/
921 uint32_t alt_eth_dma_get_curr_rx_buff_addr(uint32_t instance);
922 
923 /******************************************************************************/
932 void alt_eth_dma_set_tx_desc_addr(uint32_t tx_desc_list_addr, uint32_t instance);
933 
934 /******************************************************************************/
943 void alt_eth_dma_set_rx_desc_addr(uint32_t rx_desc_list_addr, uint32_t instance);
944 
945 /******************************************************************************/
953 void alt_eth_dma_resume_dma_tx(uint32_t instance);
954 
955 /******************************************************************************/
963 void alt_eth_dma_resume_dma_rx(uint32_t instance);
964 
965 
967 /* PHY Specific Function Prototypes. */
970 /******************************************************************************/
987 ALT_STATUS_CODE alt_eth_phy_config(uint32_t instance);
988 
989 /******************************************************************************/
1005 ALT_STATUS_CODE alt_eth_phy_reset(uint32_t instance);
1006 
1007 /******************************************************************************/
1030 ALT_STATUS_CODE alt_eth_phy_get_duplex_and_speed(uint32_t * phy_duplex_status, uint32_t * phy_speed, uint32_t instance);
1031 
1032 
1033 #ifdef __cplusplus
1034 }
1035 #endif /* __cplusplus */
1036 
1037 #endif /* __ALT_ETHERNET_H__ */