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alt_spim.h
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32 
33 /* Altera - ALT_SPIM */
34 
35 #ifndef __ALT_SOCAL_SPIM_H__
36 #define __ALT_SOCAL_SPIM_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SPIM
50  *
51  */
52 /*
53  * Register : Control Register 0 - CTRLR0
54  *
55  * Control Register 0:
56  *
57  * This register controls the serial data transfer. It is impossible to
58  *
59  * write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
60  *
61  * is enabled and disabled by writing to the SSIENR register.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :--------|:-------|:------|:----------------------------
67  * [3:0] | R | 0x0 | ALT_SPIM_CTRLR0_DFS
68  * [5:4] | RW | 0x0 | ALT_SPIM_CTRLR0_FRF
69  * [6] | RW | 0x0 | ALT_SPIM_CTRLR0_SCPH
70  * [7] | RW | 0x0 | ALT_SPIM_CTRLR0_SCPOL
71  * [9:8] | RW | 0x0 | ALT_SPIM_CTRLR0_TMOD
72  * [10] | R | 0x0 | ALT_SPIM_CTRLR0_RSVD_SLV_OE
73  * [11] | RW | 0x0 | ALT_SPIM_CTRLR0_SRL
74  * [15:12] | RW | 0x0 | ALT_SPIM_CTRLR0_CFS
75  * [20:16] | RW | 0x7 | ALT_SPIM_CTRLR0_DFS_32
76  * [22:21] | R | 0x0 | ALT_SPIM_CTRLR0_SPI_FRF
77  * [31:23] | R | 0x0 | ALT_SPIM_CTRLR0_RSVD_CTRLR0
78  *
79  */
80 /*
81  * Field : DFS
82  *
83  * Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is
84  *
85  * configured to 16. If SSI_MAX_XFER_SIZE is configured to 32, then writing to this
86  * field
87  *
88  * will not have any effect.
89  *
90  * Selects the data frame length. When the data frame size is programmed to be less
91  * than
92  *
93  * 16 bits, the receive data are automatically right-justified by the receive
94  * logic, with the
95  *
96  * upper bits of the receive FIFO zero-padded.
97  *
98  * You must right-justify transmit data before writing into the transmit FIFO. The
99  * transmit
100  *
101  * logic ignores the upper unused bits when transmitting the data
102  *
103  * Note: When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode
104  * and SPI_FRF is not set to 2'b00.
105  *
106  * DFS value should be multiple of 2 if SPI_FRF = 01, and
107  *
108  * DFS value should be multiple of 4 if SPI_FRF = 10.
109  *
110  * Field Enumeration Values:
111  *
112  * Enum | Value | Description
113  * :-----------------------------------|:------|:----------------------------
114  * ALT_SPIM_CTRLR0_DFS_E_FRAME_04BITS | 0x3 | 04-bit serial data transfer
115  * ALT_SPIM_CTRLR0_DFS_E_FRAME_05BITS | 0x4 | 05-bit serial data transfer
116  * ALT_SPIM_CTRLR0_DFS_E_FRAME_06BITS | 0x5 | 06-bit serial data transfer
117  * ALT_SPIM_CTRLR0_DFS_E_FRAME_07BITS | 0x6 | 07-bit serial data transfer
118  * ALT_SPIM_CTRLR0_DFS_E_FRAME_08BITS | 0x7 | 08-bit serial data transfer
119  * ALT_SPIM_CTRLR0_DFS_E_FRAME_09BITS | 0x8 | 09-bit serial data transfer
120  * ALT_SPIM_CTRLR0_DFS_E_FRAME_10BITS | 0x9 | 10-bit serial data transfer
121  * ALT_SPIM_CTRLR0_DFS_E_FRAME_11BITS | 0xa | 11-bit serial data transfer
122  * ALT_SPIM_CTRLR0_DFS_E_FRAME_12BITS | 0xb | 12-bit serial data transfer
123  * ALT_SPIM_CTRLR0_DFS_E_FRAME_13BITS | 0xc | 13-bit serial data transfer
124  * ALT_SPIM_CTRLR0_DFS_E_FRAME_14BITS | 0xd | 14-bit serial data transfer
125  * ALT_SPIM_CTRLR0_DFS_E_FRAME_15BITS | 0xe | 15-bit serial data transfer
126  * ALT_SPIM_CTRLR0_DFS_E_FRAME_16BITS | 0xf | 16-bit serial data transfer
127  *
128  * Field Access Macros:
129  *
130  */
131 /*
132  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
133  *
134  * 04-bit serial data transfer
135  */
136 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_04BITS 0x3
137 /*
138  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
139  *
140  * 05-bit serial data transfer
141  */
142 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_05BITS 0x4
143 /*
144  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
145  *
146  * 06-bit serial data transfer
147  */
148 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_06BITS 0x5
149 /*
150  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
151  *
152  * 07-bit serial data transfer
153  */
154 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_07BITS 0x6
155 /*
156  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
157  *
158  * 08-bit serial data transfer
159  */
160 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_08BITS 0x7
161 /*
162  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
163  *
164  * 09-bit serial data transfer
165  */
166 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_09BITS 0x8
167 /*
168  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
169  *
170  * 10-bit serial data transfer
171  */
172 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_10BITS 0x9
173 /*
174  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
175  *
176  * 11-bit serial data transfer
177  */
178 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_11BITS 0xa
179 /*
180  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
181  *
182  * 12-bit serial data transfer
183  */
184 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_12BITS 0xb
185 /*
186  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
187  *
188  * 13-bit serial data transfer
189  */
190 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_13BITS 0xc
191 /*
192  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
193  *
194  * 14-bit serial data transfer
195  */
196 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_14BITS 0xd
197 /*
198  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
199  *
200  * 15-bit serial data transfer
201  */
202 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_15BITS 0xe
203 /*
204  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS
205  *
206  * 16-bit serial data transfer
207  */
208 #define ALT_SPIM_CTRLR0_DFS_E_FRAME_16BITS 0xf
209 
210 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_DFS register field. */
211 #define ALT_SPIM_CTRLR0_DFS_LSB 0
212 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_DFS register field. */
213 #define ALT_SPIM_CTRLR0_DFS_MSB 3
214 /* The width in bits of the ALT_SPIM_CTRLR0_DFS register field. */
215 #define ALT_SPIM_CTRLR0_DFS_WIDTH 4
216 /* The mask used to set the ALT_SPIM_CTRLR0_DFS register field value. */
217 #define ALT_SPIM_CTRLR0_DFS_SET_MSK 0x0000000f
218 /* The mask used to clear the ALT_SPIM_CTRLR0_DFS register field value. */
219 #define ALT_SPIM_CTRLR0_DFS_CLR_MSK 0xfffffff0
220 /* The reset value of the ALT_SPIM_CTRLR0_DFS register field. */
221 #define ALT_SPIM_CTRLR0_DFS_RESET 0x0
222 /* Extracts the ALT_SPIM_CTRLR0_DFS field value from a register. */
223 #define ALT_SPIM_CTRLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
224 /* Produces a ALT_SPIM_CTRLR0_DFS register field value suitable for setting the register. */
225 #define ALT_SPIM_CTRLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
226 
227 /*
228  * Field : FRF
229  *
230  * Frame Format.
231  *
232  * Selects which serial protocol transfers the data.
233  *
234  * 00 - Motorola SPI
235  *
236  * 01 - Texas Instruments SSP
237  *
238  * 10 - National Semiconductors Microwire
239  *
240  * 11 - Reserved
241  *
242  * Field Enumeration Values:
243  *
244  * Enum | Value | Description
245  * :------------------------------------|:------|:-----------------------------------
246  * ALT_SPIM_CTRLR0_FRF_E_MOTOROLLA_SPI | 0x0 | Motorolla SPI Frame Format
247  * ALT_SPIM_CTRLR0_FRF_E_TEXAS_SSP | 0x1 | Texas Instruments SSP Frame Format
248  * ALT_SPIM_CTRLR0_FRF_E_NS_MICROWIRE | 0x2 | National Microwire Frame Format
249  *
250  * Field Access Macros:
251  *
252  */
253 /*
254  * Enumerated value for register field ALT_SPIM_CTRLR0_FRF
255  *
256  * Motorolla SPI Frame Format
257  */
258 #define ALT_SPIM_CTRLR0_FRF_E_MOTOROLLA_SPI 0x0
259 /*
260  * Enumerated value for register field ALT_SPIM_CTRLR0_FRF
261  *
262  * Texas Instruments SSP Frame Format
263  */
264 #define ALT_SPIM_CTRLR0_FRF_E_TEXAS_SSP 0x1
265 /*
266  * Enumerated value for register field ALT_SPIM_CTRLR0_FRF
267  *
268  * National Microwire Frame Format
269  */
270 #define ALT_SPIM_CTRLR0_FRF_E_NS_MICROWIRE 0x2
271 
272 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_FRF register field. */
273 #define ALT_SPIM_CTRLR0_FRF_LSB 4
274 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_FRF register field. */
275 #define ALT_SPIM_CTRLR0_FRF_MSB 5
276 /* The width in bits of the ALT_SPIM_CTRLR0_FRF register field. */
277 #define ALT_SPIM_CTRLR0_FRF_WIDTH 2
278 /* The mask used to set the ALT_SPIM_CTRLR0_FRF register field value. */
279 #define ALT_SPIM_CTRLR0_FRF_SET_MSK 0x00000030
280 /* The mask used to clear the ALT_SPIM_CTRLR0_FRF register field value. */
281 #define ALT_SPIM_CTRLR0_FRF_CLR_MSK 0xffffffcf
282 /* The reset value of the ALT_SPIM_CTRLR0_FRF register field. */
283 #define ALT_SPIM_CTRLR0_FRF_RESET 0x0
284 /* Extracts the ALT_SPIM_CTRLR0_FRF field value from a register. */
285 #define ALT_SPIM_CTRLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
286 /* Produces a ALT_SPIM_CTRLR0_FRF register field value suitable for setting the register. */
287 #define ALT_SPIM_CTRLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
288 
289 /*
290  * Field : SCPH
291  *
292  * Serial Clock Phase.
293  *
294  * Valid when the frame format (FRF) is set to Motorola SPI. The serial
295  *
296  * clock phase selects the relationship of the serial clock with the slave
297  *
298  * select signal. When SCPH = 0, data are captured on the first edge of
299  *
300  * the serial clock. When SCPH = 1, the serial clock starts toggling one
301  *
302  * cycle after the slave select line is activated, and data are captured
303  *
304  * on the second edge of the serial clock.
305  *
306  * 0: Serial clock toggles in middle of first data bit
307  *
308  * 1: Serial clock toggles at start of first data bit
309  *
310  * Field Enumeration Values:
311  *
312  * Enum | Value | Description
313  * :----------------------------------|:------|:-------------------------------------
314  * ALT_SPIM_CTRLR0_SCPH_E_MIDDLE_BIT | 0x0 | Clock toggles in middle of first bit
315  * ALT_SPIM_CTRLR0_SCPH_E_START_BIT | 0x1 | Clock toggles at start of first bit
316  *
317  * Field Access Macros:
318  *
319  */
320 /*
321  * Enumerated value for register field ALT_SPIM_CTRLR0_SCPH
322  *
323  * Clock toggles in middle of first bit
324  */
325 #define ALT_SPIM_CTRLR0_SCPH_E_MIDDLE_BIT 0x0
326 /*
327  * Enumerated value for register field ALT_SPIM_CTRLR0_SCPH
328  *
329  * Clock toggles at start of first bit
330  */
331 #define ALT_SPIM_CTRLR0_SCPH_E_START_BIT 0x1
332 
333 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_SCPH register field. */
334 #define ALT_SPIM_CTRLR0_SCPH_LSB 6
335 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_SCPH register field. */
336 #define ALT_SPIM_CTRLR0_SCPH_MSB 6
337 /* The width in bits of the ALT_SPIM_CTRLR0_SCPH register field. */
338 #define ALT_SPIM_CTRLR0_SCPH_WIDTH 1
339 /* The mask used to set the ALT_SPIM_CTRLR0_SCPH register field value. */
340 #define ALT_SPIM_CTRLR0_SCPH_SET_MSK 0x00000040
341 /* The mask used to clear the ALT_SPIM_CTRLR0_SCPH register field value. */
342 #define ALT_SPIM_CTRLR0_SCPH_CLR_MSK 0xffffffbf
343 /* The reset value of the ALT_SPIM_CTRLR0_SCPH register field. */
344 #define ALT_SPIM_CTRLR0_SCPH_RESET 0x0
345 /* Extracts the ALT_SPIM_CTRLR0_SCPH field value from a register. */
346 #define ALT_SPIM_CTRLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
347 /* Produces a ALT_SPIM_CTRLR0_SCPH register field value suitable for setting the register. */
348 #define ALT_SPIM_CTRLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
349 
350 /*
351  * Field : SCPOL
352  *
353  * Serial Clock Polarity.
354  *
355  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select
356  *
357  * the polarity of the inactive serial clock, which is held inactive when
358  *
359  * the DW_apb_ssi master is not actively transferring data on the serial bus.
360  *
361  * 0 - Inactive state of serial clock is low
362  *
363  * 1 - Inactive state of serial clock is high
364  *
365  * Field Enumeration Values:
366  *
367  * Enum | Value | Description
368  * :--------------------------------------|:------|:----------------------------
369  * ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_HIGH | 0x0 | Clock is inactive when high
370  * ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_LOW | 0x1 | Clock is inactive when low
371  *
372  * Field Access Macros:
373  *
374  */
375 /*
376  * Enumerated value for register field ALT_SPIM_CTRLR0_SCPOL
377  *
378  * Clock is inactive when high
379  */
380 #define ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_HIGH 0x0
381 /*
382  * Enumerated value for register field ALT_SPIM_CTRLR0_SCPOL
383  *
384  * Clock is inactive when low
385  */
386 #define ALT_SPIM_CTRLR0_SCPOL_E_INACTIVE_LOW 0x1
387 
388 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_SCPOL register field. */
389 #define ALT_SPIM_CTRLR0_SCPOL_LSB 7
390 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_SCPOL register field. */
391 #define ALT_SPIM_CTRLR0_SCPOL_MSB 7
392 /* The width in bits of the ALT_SPIM_CTRLR0_SCPOL register field. */
393 #define ALT_SPIM_CTRLR0_SCPOL_WIDTH 1
394 /* The mask used to set the ALT_SPIM_CTRLR0_SCPOL register field value. */
395 #define ALT_SPIM_CTRLR0_SCPOL_SET_MSK 0x00000080
396 /* The mask used to clear the ALT_SPIM_CTRLR0_SCPOL register field value. */
397 #define ALT_SPIM_CTRLR0_SCPOL_CLR_MSK 0xffffff7f
398 /* The reset value of the ALT_SPIM_CTRLR0_SCPOL register field. */
399 #define ALT_SPIM_CTRLR0_SCPOL_RESET 0x0
400 /* Extracts the ALT_SPIM_CTRLR0_SCPOL field value from a register. */
401 #define ALT_SPIM_CTRLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
402 /* Produces a ALT_SPIM_CTRLR0_SCPOL register field value suitable for setting the register. */
403 #define ALT_SPIM_CTRLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
404 
405 /*
406  * Field : TMOD
407  *
408  * Transfer Mode.
409  *
410  * Selects the mode of transfer for serial communication. This field does
411  *
412  * not affect the transfer duplicity. Only indicates whether the receive or
413  *
414  * transmit data are valid. In transmit-only mode, data received from the
415  *
416  * external device is not valid and is not stored in the receive FIFO memory;
417  *
418  * it is overwritten on the next transfer. In receive-only mode, transmitted
419  *
420  * data are not valid. After the first write to the transmit FIFO, the same
421  *
422  * word is retransmitted for the duration of the transfer. In
423  *
424  * transmit-and-receive mode, both transmit and receive data are valid.
425  *
426  * The transfer continues until the transmit FIFO is empty. Data received
427  *
428  * from the external device are stored into the receive FIFO memory, where
429  *
430  * it can be accessed by the host processor.
431  *
432  * 00 - Transmit & Receive
433  *
434  * 01 - Transmit Only
435  *
436  * 10 - Receive Only
437  *
438  * 11 - EEPROM Read
439  *
440  * When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode and
441  * SPI_FRF is not set to 2'b00.
442  *
443  * There are only two valid combinations:
444  *
445  * 01 Read
446  *
447  * 10 - Write
448  *
449  * Field Enumeration Values:
450  *
451  * Enum | Value | Description
452  * :-----------------------------------|:------|:-------------------
453  * ALT_SPIM_CTRLR0_TMOD_E_TX_AND_RX | 0x0 | Transmit & receive
454  * ALT_SPIM_CTRLR0_TMOD_E_TX_ONLY | 0x1 | Transmit only mode
455  * ALT_SPIM_CTRLR0_TMOD_E_RX_ONLY | 0x2 | Receive only mode
456  * ALT_SPIM_CTRLR0_TMOD_E_EEPROM_READ | 0x3 | EEPROM Read mode
457  *
458  * Field Access Macros:
459  *
460  */
461 /*
462  * Enumerated value for register field ALT_SPIM_CTRLR0_TMOD
463  *
464  * Transmit & receive
465  */
466 #define ALT_SPIM_CTRLR0_TMOD_E_TX_AND_RX 0x0
467 /*
468  * Enumerated value for register field ALT_SPIM_CTRLR0_TMOD
469  *
470  * Transmit only mode
471  */
472 #define ALT_SPIM_CTRLR0_TMOD_E_TX_ONLY 0x1
473 /*
474  * Enumerated value for register field ALT_SPIM_CTRLR0_TMOD
475  *
476  * Receive only mode
477  */
478 #define ALT_SPIM_CTRLR0_TMOD_E_RX_ONLY 0x2
479 /*
480  * Enumerated value for register field ALT_SPIM_CTRLR0_TMOD
481  *
482  * EEPROM Read mode
483  */
484 #define ALT_SPIM_CTRLR0_TMOD_E_EEPROM_READ 0x3
485 
486 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_TMOD register field. */
487 #define ALT_SPIM_CTRLR0_TMOD_LSB 8
488 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_TMOD register field. */
489 #define ALT_SPIM_CTRLR0_TMOD_MSB 9
490 /* The width in bits of the ALT_SPIM_CTRLR0_TMOD register field. */
491 #define ALT_SPIM_CTRLR0_TMOD_WIDTH 2
492 /* The mask used to set the ALT_SPIM_CTRLR0_TMOD register field value. */
493 #define ALT_SPIM_CTRLR0_TMOD_SET_MSK 0x00000300
494 /* The mask used to clear the ALT_SPIM_CTRLR0_TMOD register field value. */
495 #define ALT_SPIM_CTRLR0_TMOD_CLR_MSK 0xfffffcff
496 /* The reset value of the ALT_SPIM_CTRLR0_TMOD register field. */
497 #define ALT_SPIM_CTRLR0_TMOD_RESET 0x0
498 /* Extracts the ALT_SPIM_CTRLR0_TMOD field value from a register. */
499 #define ALT_SPIM_CTRLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
500 /* Produces a ALT_SPIM_CTRLR0_TMOD register field value suitable for setting the register. */
501 #define ALT_SPIM_CTRLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
502 
503 /*
504  * Field : RSVD_SLV_OE
505  *
506  * Reserved field- Read-only
507  *
508  * Field Access Macros:
509  *
510  */
511 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field. */
512 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_LSB 10
513 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field. */
514 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_MSB 10
515 /* The width in bits of the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field. */
516 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_WIDTH 1
517 /* The mask used to set the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field value. */
518 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_SET_MSK 0x00000400
519 /* The mask used to clear the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field value. */
520 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_CLR_MSK 0xfffffbff
521 /* The reset value of the ALT_SPIM_CTRLR0_RSVD_SLV_OE register field. */
522 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_RESET 0x0
523 /* Extracts the ALT_SPIM_CTRLR0_RSVD_SLV_OE field value from a register. */
524 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
525 /* Produces a ALT_SPIM_CTRLR0_RSVD_SLV_OE register field value suitable for setting the register. */
526 #define ALT_SPIM_CTRLR0_RSVD_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
527 
528 /*
529  * Field : SRL
530  *
531  * Shift Register Loop. Used for testing purposes only. When internally
532  *
533  * active, connects the transmit shift register output to the receive
534  *
535  * shift register input.
536  *
537  * 0 - Normal Mode Operation
538  *
539  * 1 - Test Mode Operation
540  *
541  * Field Enumeration Values:
542  *
543  * Enum | Value | Description
544  * :-----------------------------------|:------|:---------------------------------------
545  * ALT_SPIM_CTRLR0_SRL_E_NORMAL_MODE | 0x0 | Normal mode operation
546  * ALT_SPIM_CTRLR0_SRL_E_TESTING_MODE | 0x1 | Test mode: Tx & Rx shift reg connected
547  *
548  * Field Access Macros:
549  *
550  */
551 /*
552  * Enumerated value for register field ALT_SPIM_CTRLR0_SRL
553  *
554  * Normal mode operation
555  */
556 #define ALT_SPIM_CTRLR0_SRL_E_NORMAL_MODE 0x0
557 /*
558  * Enumerated value for register field ALT_SPIM_CTRLR0_SRL
559  *
560  * Test mode: Tx & Rx shift reg connected
561  */
562 #define ALT_SPIM_CTRLR0_SRL_E_TESTING_MODE 0x1
563 
564 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_SRL register field. */
565 #define ALT_SPIM_CTRLR0_SRL_LSB 11
566 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_SRL register field. */
567 #define ALT_SPIM_CTRLR0_SRL_MSB 11
568 /* The width in bits of the ALT_SPIM_CTRLR0_SRL register field. */
569 #define ALT_SPIM_CTRLR0_SRL_WIDTH 1
570 /* The mask used to set the ALT_SPIM_CTRLR0_SRL register field value. */
571 #define ALT_SPIM_CTRLR0_SRL_SET_MSK 0x00000800
572 /* The mask used to clear the ALT_SPIM_CTRLR0_SRL register field value. */
573 #define ALT_SPIM_CTRLR0_SRL_CLR_MSK 0xfffff7ff
574 /* The reset value of the ALT_SPIM_CTRLR0_SRL register field. */
575 #define ALT_SPIM_CTRLR0_SRL_RESET 0x0
576 /* Extracts the ALT_SPIM_CTRLR0_SRL field value from a register. */
577 #define ALT_SPIM_CTRLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
578 /* Produces a ALT_SPIM_CTRLR0_SRL register field value suitable for setting the register. */
579 #define ALT_SPIM_CTRLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
580 
581 /*
582  * Field : CFS
583  *
584  * Control Frame Size. Selects the length of the control word for the
585  *
586  * Microwire frame format
587  *
588  * When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode and
589  * SPI_FRF is not set to 2'b00.
590  *
591  * This bit defines Length of Address to be transmitted. Refer Table 4 6 for field
592  * decode.
593  *
594  * Only after this much bits are programmed in to the FIFO the transfer can begin.
595  *
596  * Field Enumeration Values:
597  *
598  * Enum | Value | Description
599  * :----------------------------------|:------|:--------------------
600  * ALT_SPIM_CTRLR0_CFS_E_SIZE_01_BIT | 0x0 | 01-bit Control Word
601  * ALT_SPIM_CTRLR0_CFS_E_SIZE_02_BIT | 0x1 | 02-bit Control Word
602  * ALT_SPIM_CTRLR0_CFS_E_SIZE_03_BIT | 0x2 | 03-bit Control Word
603  * ALT_SPIM_CTRLR0_CFS_E_SIZE_04_BIT | 0x3 | 04-bit Control Word
604  * ALT_SPIM_CTRLR0_CFS_E_SIZE_05_BIT | 0x4 | 05-bit Control Word
605  * ALT_SPIM_CTRLR0_CFS_E_SIZE_06_BIT | 0x5 | 06-bit Control Word
606  * ALT_SPIM_CTRLR0_CFS_E_SIZE_07_BIT | 0x6 | 07-bit Control Word
607  * ALT_SPIM_CTRLR0_CFS_E_SIZE_08_BIT | 0x7 | 08-bit Control Word
608  * ALT_SPIM_CTRLR0_CFS_E_SIZE_09_BIT | 0x8 | 09-bit Control Word
609  * ALT_SPIM_CTRLR0_CFS_E_SIZE_10_BIT | 0x9 | 10-bit Control Word
610  * ALT_SPIM_CTRLR0_CFS_E_SIZE_11_BIT | 0xa | 11-bit Control Word
611  * ALT_SPIM_CTRLR0_CFS_E_SIZE_12_BIT | 0xb | 12-bit Control Word
612  * ALT_SPIM_CTRLR0_CFS_E_SIZE_13_BIT | 0xc | 13-bit Control Word
613  * ALT_SPIM_CTRLR0_CFS_E_SIZE_14_BIT | 0xd | 14-bit Control Word
614  * ALT_SPIM_CTRLR0_CFS_E_SIZE_15_BIT | 0xe | 15-bit Control Word
615  * ALT_SPIM_CTRLR0_CFS_E_SIZE_16_BIT | 0xf | 16-bit Control Word
616  *
617  * Field Access Macros:
618  *
619  */
620 /*
621  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
622  *
623  * 01-bit Control Word
624  */
625 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_01_BIT 0x0
626 /*
627  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
628  *
629  * 02-bit Control Word
630  */
631 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_02_BIT 0x1
632 /*
633  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
634  *
635  * 03-bit Control Word
636  */
637 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_03_BIT 0x2
638 /*
639  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
640  *
641  * 04-bit Control Word
642  */
643 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_04_BIT 0x3
644 /*
645  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
646  *
647  * 05-bit Control Word
648  */
649 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_05_BIT 0x4
650 /*
651  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
652  *
653  * 06-bit Control Word
654  */
655 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_06_BIT 0x5
656 /*
657  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
658  *
659  * 07-bit Control Word
660  */
661 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_07_BIT 0x6
662 /*
663  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
664  *
665  * 08-bit Control Word
666  */
667 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_08_BIT 0x7
668 /*
669  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
670  *
671  * 09-bit Control Word
672  */
673 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_09_BIT 0x8
674 /*
675  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
676  *
677  * 10-bit Control Word
678  */
679 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_10_BIT 0x9
680 /*
681  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
682  *
683  * 11-bit Control Word
684  */
685 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_11_BIT 0xa
686 /*
687  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
688  *
689  * 12-bit Control Word
690  */
691 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_12_BIT 0xb
692 /*
693  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
694  *
695  * 13-bit Control Word
696  */
697 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_13_BIT 0xc
698 /*
699  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
700  *
701  * 14-bit Control Word
702  */
703 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_14_BIT 0xd
704 /*
705  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
706  *
707  * 15-bit Control Word
708  */
709 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_15_BIT 0xe
710 /*
711  * Enumerated value for register field ALT_SPIM_CTRLR0_CFS
712  *
713  * 16-bit Control Word
714  */
715 #define ALT_SPIM_CTRLR0_CFS_E_SIZE_16_BIT 0xf
716 
717 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_CFS register field. */
718 #define ALT_SPIM_CTRLR0_CFS_LSB 12
719 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_CFS register field. */
720 #define ALT_SPIM_CTRLR0_CFS_MSB 15
721 /* The width in bits of the ALT_SPIM_CTRLR0_CFS register field. */
722 #define ALT_SPIM_CTRLR0_CFS_WIDTH 4
723 /* The mask used to set the ALT_SPIM_CTRLR0_CFS register field value. */
724 #define ALT_SPIM_CTRLR0_CFS_SET_MSK 0x0000f000
725 /* The mask used to clear the ALT_SPIM_CTRLR0_CFS register field value. */
726 #define ALT_SPIM_CTRLR0_CFS_CLR_MSK 0xffff0fff
727 /* The reset value of the ALT_SPIM_CTRLR0_CFS register field. */
728 #define ALT_SPIM_CTRLR0_CFS_RESET 0x0
729 /* Extracts the ALT_SPIM_CTRLR0_CFS field value from a register. */
730 #define ALT_SPIM_CTRLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
731 /* Produces a ALT_SPIM_CTRLR0_CFS register field value suitable for setting the register. */
732 #define ALT_SPIM_CTRLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
733 
734 /*
735  * Field : DFS_32
736  *
737  * Data Frame Size in 32-bit transfer size mode.
738  *
739  * Selects the data frame length. When the data frame size is programmed
740  *
741  * to be less than 32 bits, the receive data are automatically
742  *
743  * right-justified by the receive logic, with the upper bits of the receive
744  *
745  * FIFO zero-padded. You must right-justify transmit data before writing
746  *
747  * into the transmit FIFO. The transmit logic ignores the upper unused
748  *
749  * bits when transmitting the data
750  *
751  * Note: When SSI_SPI_MODE is either set to "Dual" or "Dual/Quad Both" mode
752  * and SPI_FRF is not set to 2'b00.
753  *
754  * DFS value should be multiple of 2 if SPI_FRF = 01, and
755  *
756  * DFS value should be multiple of 4 if SPI_FRF = 10.
757  *
758  * Field Enumeration Values:
759  *
760  * Enum | Value | Description
761  * :--------------------------------------|:------|:-----------------------------
762  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_04BITS | 0x3 | 04- bit serial data transfer
763  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_05BITS | 0x4 | 05- bit serial data transfer
764  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_06BITS | 0x5 | 06- bit serial data transfer
765  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_07BITS | 0x6 | 07- bit serial data transfer
766  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_08BITS | 0x7 | 08- bit serial data transfer
767  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_09BITS | 0x8 | 09- bit serial data transfer
768  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_10BITS | 0x9 | 10- bit serial data transfer
769  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_11BITS | 0xa | 11- bit serial data transfer
770  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_12BITS | 0xb | 12- bit serial data transfer
771  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_13BITS | 0xc | 13- bit serial data transfer
772  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_14BITS | 0xd | 14- bit serial data transfer
773  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_15BITS | 0xe | 15- bit serial data transfer
774  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_16BITS | 0xf | 16- bit serial data transfer
775  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_17BITS | 0x10 | 17- bit serial data transfer
776  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_18BITS | 0x11 | 18- bit serial data transfer
777  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_19BITS | 0x12 | 19- bit serial data transfer
778  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_20BITS | 0x13 | 20- bit serial data transfer
779  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_21BITS | 0x14 | 21- bit serial data transfer
780  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_22BITS | 0x15 | 22- bit serial data transfer
781  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_23BITS | 0x16 | 23- bit serial data transfer
782  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_24BITS | 0x17 | 24- bit serial data transfer
783  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_25BITS | 0x18 | 25- bit serial data transfer
784  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_26BITS | 0x19 | 26- bit serial data transfer
785  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_27BITS | 0x1a | 27- bit serial data transfer
786  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_28BITS | 0x1b | 28- bit serial data transfer
787  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_29BITS | 0x1c | 29- bit serial data transfer
788  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_30BITS | 0x1d | 30- bit serial data transfer
789  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_31BITS | 0x1e | 31- bit serial data transfer
790  * ALT_SPIM_CTRLR0_DFS_32_E_FRAME_32BITS | 0x1f | 32- bit serial data transfer
791  *
792  * Field Access Macros:
793  *
794  */
795 /*
796  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
797  *
798  * 04- bit serial data transfer
799  */
800 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_04BITS 0x3
801 /*
802  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
803  *
804  * 05- bit serial data transfer
805  */
806 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_05BITS 0x4
807 /*
808  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
809  *
810  * 06- bit serial data transfer
811  */
812 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_06BITS 0x5
813 /*
814  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
815  *
816  * 07- bit serial data transfer
817  */
818 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_07BITS 0x6
819 /*
820  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
821  *
822  * 08- bit serial data transfer
823  */
824 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_08BITS 0x7
825 /*
826  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
827  *
828  * 09- bit serial data transfer
829  */
830 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_09BITS 0x8
831 /*
832  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
833  *
834  * 10- bit serial data transfer
835  */
836 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_10BITS 0x9
837 /*
838  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
839  *
840  * 11- bit serial data transfer
841  */
842 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_11BITS 0xa
843 /*
844  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
845  *
846  * 12- bit serial data transfer
847  */
848 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_12BITS 0xb
849 /*
850  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
851  *
852  * 13- bit serial data transfer
853  */
854 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_13BITS 0xc
855 /*
856  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
857  *
858  * 14- bit serial data transfer
859  */
860 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_14BITS 0xd
861 /*
862  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
863  *
864  * 15- bit serial data transfer
865  */
866 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_15BITS 0xe
867 /*
868  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
869  *
870  * 16- bit serial data transfer
871  */
872 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_16BITS 0xf
873 /*
874  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
875  *
876  * 17- bit serial data transfer
877  */
878 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_17BITS 0x10
879 /*
880  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
881  *
882  * 18- bit serial data transfer
883  */
884 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_18BITS 0x11
885 /*
886  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
887  *
888  * 19- bit serial data transfer
889  */
890 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_19BITS 0x12
891 /*
892  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
893  *
894  * 20- bit serial data transfer
895  */
896 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_20BITS 0x13
897 /*
898  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
899  *
900  * 21- bit serial data transfer
901  */
902 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_21BITS 0x14
903 /*
904  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
905  *
906  * 22- bit serial data transfer
907  */
908 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_22BITS 0x15
909 /*
910  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
911  *
912  * 23- bit serial data transfer
913  */
914 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_23BITS 0x16
915 /*
916  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
917  *
918  * 24- bit serial data transfer
919  */
920 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_24BITS 0x17
921 /*
922  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
923  *
924  * 25- bit serial data transfer
925  */
926 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_25BITS 0x18
927 /*
928  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
929  *
930  * 26- bit serial data transfer
931  */
932 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_26BITS 0x19
933 /*
934  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
935  *
936  * 27- bit serial data transfer
937  */
938 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_27BITS 0x1a
939 /*
940  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
941  *
942  * 28- bit serial data transfer
943  */
944 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_28BITS 0x1b
945 /*
946  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
947  *
948  * 29- bit serial data transfer
949  */
950 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_29BITS 0x1c
951 /*
952  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
953  *
954  * 30- bit serial data transfer
955  */
956 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_30BITS 0x1d
957 /*
958  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
959  *
960  * 31- bit serial data transfer
961  */
962 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_31BITS 0x1e
963 /*
964  * Enumerated value for register field ALT_SPIM_CTRLR0_DFS_32
965  *
966  * 32- bit serial data transfer
967  */
968 #define ALT_SPIM_CTRLR0_DFS_32_E_FRAME_32BITS 0x1f
969 
970 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_DFS_32 register field. */
971 #define ALT_SPIM_CTRLR0_DFS_32_LSB 16
972 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_DFS_32 register field. */
973 #define ALT_SPIM_CTRLR0_DFS_32_MSB 20
974 /* The width in bits of the ALT_SPIM_CTRLR0_DFS_32 register field. */
975 #define ALT_SPIM_CTRLR0_DFS_32_WIDTH 5
976 /* The mask used to set the ALT_SPIM_CTRLR0_DFS_32 register field value. */
977 #define ALT_SPIM_CTRLR0_DFS_32_SET_MSK 0x001f0000
978 /* The mask used to clear the ALT_SPIM_CTRLR0_DFS_32 register field value. */
979 #define ALT_SPIM_CTRLR0_DFS_32_CLR_MSK 0xffe0ffff
980 /* The reset value of the ALT_SPIM_CTRLR0_DFS_32 register field. */
981 #define ALT_SPIM_CTRLR0_DFS_32_RESET 0x7
982 /* Extracts the ALT_SPIM_CTRLR0_DFS_32 field value from a register. */
983 #define ALT_SPIM_CTRLR0_DFS_32_GET(value) (((value) & 0x001f0000) >> 16)
984 /* Produces a ALT_SPIM_CTRLR0_DFS_32 register field value suitable for setting the register. */
985 #define ALT_SPIM_CTRLR0_DFS_32_SET(value) (((value) << 16) & 0x001f0000)
986 
987 /*
988  * Field : SPI_FRF
989  *
990  * SPI Frame Format:
991  *
992  * Selects data frame format for Transmitting/Receiving the data
993  *
994  * 00 - Standard SPI Format
995  *
996  * 01 - Dual SPI Format
997  *
998  * 10 - Quad SPI Format
999  *
1000  * Bits only valid when SSI_SPI_MODE is either set to "Dual" or "Dual/Quad
1001  * Both" mode.
1002  *
1003  * Field Access Macros:
1004  *
1005  */
1006 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_SPI_FRF register field. */
1007 #define ALT_SPIM_CTRLR0_SPI_FRF_LSB 21
1008 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_SPI_FRF register field. */
1009 #define ALT_SPIM_CTRLR0_SPI_FRF_MSB 22
1010 /* The width in bits of the ALT_SPIM_CTRLR0_SPI_FRF register field. */
1011 #define ALT_SPIM_CTRLR0_SPI_FRF_WIDTH 2
1012 /* The mask used to set the ALT_SPIM_CTRLR0_SPI_FRF register field value. */
1013 #define ALT_SPIM_CTRLR0_SPI_FRF_SET_MSK 0x00600000
1014 /* The mask used to clear the ALT_SPIM_CTRLR0_SPI_FRF register field value. */
1015 #define ALT_SPIM_CTRLR0_SPI_FRF_CLR_MSK 0xff9fffff
1016 /* The reset value of the ALT_SPIM_CTRLR0_SPI_FRF register field. */
1017 #define ALT_SPIM_CTRLR0_SPI_FRF_RESET 0x0
1018 /* Extracts the ALT_SPIM_CTRLR0_SPI_FRF field value from a register. */
1019 #define ALT_SPIM_CTRLR0_SPI_FRF_GET(value) (((value) & 0x00600000) >> 21)
1020 /* Produces a ALT_SPIM_CTRLR0_SPI_FRF register field value suitable for setting the register. */
1021 #define ALT_SPIM_CTRLR0_SPI_FRF_SET(value) (((value) << 21) & 0x00600000)
1022 
1023 /*
1024  * Field : RSVD_CTRLR0
1025  *
1026  * Reserved bits - Read Only
1027  *
1028  * Field Access Macros:
1029  *
1030  */
1031 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field. */
1032 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_LSB 23
1033 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field. */
1034 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_MSB 31
1035 /* The width in bits of the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field. */
1036 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_WIDTH 9
1037 /* The mask used to set the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field value. */
1038 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_SET_MSK 0xff800000
1039 /* The mask used to clear the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field value. */
1040 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_CLR_MSK 0x007fffff
1041 /* The reset value of the ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field. */
1042 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_RESET 0x0
1043 /* Extracts the ALT_SPIM_CTRLR0_RSVD_CTRLR0 field value from a register. */
1044 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_GET(value) (((value) & 0xff800000) >> 23)
1045 /* Produces a ALT_SPIM_CTRLR0_RSVD_CTRLR0 register field value suitable for setting the register. */
1046 #define ALT_SPIM_CTRLR0_RSVD_CTRLR0_SET(value) (((value) << 23) & 0xff800000)
1047 
1048 #ifndef __ASSEMBLY__
1049 /*
1050  * WARNING: The C register and register group struct declarations are provided for
1051  * convenience and illustrative purposes. They should, however, be used with
1052  * caution as the C language standard provides no guarantees about the alignment or
1053  * atomicity of device memory accesses. The recommended practice for coding device
1054  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1055  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1056  * alt_write_dword() functions for 64 bit registers.
1057  *
1058  * The struct declaration for register ALT_SPIM_CTRLR0.
1059  */
1060 struct ALT_SPIM_CTRLR0_s
1061 {
1062  const volatile uint32_t DFS : 4; /* ALT_SPIM_CTRLR0_DFS */
1063  volatile uint32_t FRF : 2; /* ALT_SPIM_CTRLR0_FRF */
1064  volatile uint32_t SCPH : 1; /* ALT_SPIM_CTRLR0_SCPH */
1065  volatile uint32_t SCPOL : 1; /* ALT_SPIM_CTRLR0_SCPOL */
1066  volatile uint32_t TMOD : 2; /* ALT_SPIM_CTRLR0_TMOD */
1067  const volatile uint32_t RSVD_SLV_OE : 1; /* ALT_SPIM_CTRLR0_RSVD_SLV_OE */
1068  volatile uint32_t SRL : 1; /* ALT_SPIM_CTRLR0_SRL */
1069  volatile uint32_t CFS : 4; /* ALT_SPIM_CTRLR0_CFS */
1070  volatile uint32_t DFS_32 : 5; /* ALT_SPIM_CTRLR0_DFS_32 */
1071  const volatile uint32_t SPI_FRF : 2; /* ALT_SPIM_CTRLR0_SPI_FRF */
1072  const volatile uint32_t RSVD_CTRLR0 : 9; /* ALT_SPIM_CTRLR0_RSVD_CTRLR0 */
1073 };
1074 
1075 /* The typedef declaration for register ALT_SPIM_CTRLR0. */
1076 typedef struct ALT_SPIM_CTRLR0_s ALT_SPIM_CTRLR0_t;
1077 #endif /* __ASSEMBLY__ */
1078 
1079 /* The reset value of the ALT_SPIM_CTRLR0 register. */
1080 #define ALT_SPIM_CTRLR0_RESET 0x00070000
1081 /* The byte offset of the ALT_SPIM_CTRLR0 register from the beginning of the component. */
1082 #define ALT_SPIM_CTRLR0_OFST 0x0
1083 /* The address of the ALT_SPIM_CTRLR0 register. */
1084 #define ALT_SPIM_CTRLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTRLR0_OFST))
1085 
1086 /*
1087  * Register : Control Register 1 - CTRLR1
1088  *
1089  * Control Register 1
1090  *
1091  * This register exists only when the DW_apb_ssi is configured as a
1092  *
1093  * master device. When the DW_apb_ssi is configured as a serial slave,
1094  *
1095  * writing to this location has no effect; reading from this location
1096  *
1097  * returns 0. Control register 1 controls the end of serial transfers
1098  *
1099  * when in receive-only mode. It is impossible to write to this
1100  *
1101  * register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled
1102  *
1103  * and disabled by writing to the SSIENR register.
1104  *
1105  * Register Layout
1106  *
1107  * Bits | Access | Reset | Description
1108  * :--------|:-------|:------|:----------------------------
1109  * [15:0] | RW | 0x0 | ALT_SPIM_CTRLR1_NDF
1110  * [31:16] | R | 0x0 | ALT_SPIM_CTRLR1_RSVD_CTRLR1
1111  *
1112  */
1113 /*
1114  * Field : NDF
1115  *
1116  * Number of Data Frames.
1117  *
1118  * When TMOD = 10 or TMOD = 11 , this register field sets the number of data frames
1119  * to
1120  *
1121  * be continuously received by the DW_apb_ssi. The DW_apb_ssi continues
1122  *
1123  * to receive serial data until the number of data frames received is
1124  *
1125  * equal to this register value plus 1, which enables you to receive up
1126  *
1127  * to 64 KB of data in a continuous transfer. When the DW_apb_ssi is
1128  *
1129  * configured as a serial slave, the transfer continues for as long as
1130  *
1131  * the slave is selected. Therefore, this register serves no purpose and
1132  *
1133  * is not present when the DW_apb_ssi is configured as a serial slave.
1134  *
1135  * Field Access Macros:
1136  *
1137  */
1138 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR1_NDF register field. */
1139 #define ALT_SPIM_CTRLR1_NDF_LSB 0
1140 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR1_NDF register field. */
1141 #define ALT_SPIM_CTRLR1_NDF_MSB 15
1142 /* The width in bits of the ALT_SPIM_CTRLR1_NDF register field. */
1143 #define ALT_SPIM_CTRLR1_NDF_WIDTH 16
1144 /* The mask used to set the ALT_SPIM_CTRLR1_NDF register field value. */
1145 #define ALT_SPIM_CTRLR1_NDF_SET_MSK 0x0000ffff
1146 /* The mask used to clear the ALT_SPIM_CTRLR1_NDF register field value. */
1147 #define ALT_SPIM_CTRLR1_NDF_CLR_MSK 0xffff0000
1148 /* The reset value of the ALT_SPIM_CTRLR1_NDF register field. */
1149 #define ALT_SPIM_CTRLR1_NDF_RESET 0x0
1150 /* Extracts the ALT_SPIM_CTRLR1_NDF field value from a register. */
1151 #define ALT_SPIM_CTRLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
1152 /* Produces a ALT_SPIM_CTRLR1_NDF register field value suitable for setting the register. */
1153 #define ALT_SPIM_CTRLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
1154 
1155 /*
1156  * Field : RSVD_CTRLR1
1157  *
1158  * Reserved bits - Read Only
1159  *
1160  * Field Access Macros:
1161  *
1162  */
1163 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field. */
1164 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_LSB 16
1165 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field. */
1166 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_MSB 31
1167 /* The width in bits of the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field. */
1168 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_WIDTH 16
1169 /* The mask used to set the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field value. */
1170 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_SET_MSK 0xffff0000
1171 /* The mask used to clear the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field value. */
1172 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_CLR_MSK 0x0000ffff
1173 /* The reset value of the ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field. */
1174 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_RESET 0x0
1175 /* Extracts the ALT_SPIM_CTRLR1_RSVD_CTRLR1 field value from a register. */
1176 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_GET(value) (((value) & 0xffff0000) >> 16)
1177 /* Produces a ALT_SPIM_CTRLR1_RSVD_CTRLR1 register field value suitable for setting the register. */
1178 #define ALT_SPIM_CTRLR1_RSVD_CTRLR1_SET(value) (((value) << 16) & 0xffff0000)
1179 
1180 #ifndef __ASSEMBLY__
1181 /*
1182  * WARNING: The C register and register group struct declarations are provided for
1183  * convenience and illustrative purposes. They should, however, be used with
1184  * caution as the C language standard provides no guarantees about the alignment or
1185  * atomicity of device memory accesses. The recommended practice for coding device
1186  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1187  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1188  * alt_write_dword() functions for 64 bit registers.
1189  *
1190  * The struct declaration for register ALT_SPIM_CTRLR1.
1191  */
1192 struct ALT_SPIM_CTRLR1_s
1193 {
1194  volatile uint32_t NDF : 16; /* ALT_SPIM_CTRLR1_NDF */
1195  const volatile uint32_t RSVD_CTRLR1 : 16; /* ALT_SPIM_CTRLR1_RSVD_CTRLR1 */
1196 };
1197 
1198 /* The typedef declaration for register ALT_SPIM_CTRLR1. */
1199 typedef struct ALT_SPIM_CTRLR1_s ALT_SPIM_CTRLR1_t;
1200 #endif /* __ASSEMBLY__ */
1201 
1202 /* The reset value of the ALT_SPIM_CTRLR1 register. */
1203 #define ALT_SPIM_CTRLR1_RESET 0x00000000
1204 /* The byte offset of the ALT_SPIM_CTRLR1 register from the beginning of the component. */
1205 #define ALT_SPIM_CTRLR1_OFST 0x4
1206 /* The address of the ALT_SPIM_CTRLR1 register. */
1207 #define ALT_SPIM_CTRLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTRLR1_OFST))
1208 
1209 /*
1210  * Register : SSI Enable Register - SSIENR
1211  *
1212  * SSI Enable Register
1213  *
1214  * Register Layout
1215  *
1216  * Bits | Access | Reset | Description
1217  * :-------|:-------|:------|:----------------------------
1218  * [0] | RW | 0x0 | ALT_SPIM_SSIENR_SSI_EN
1219  * [31:1] | R | 0x0 | ALT_SPIM_SSIENR_RSVD_SSIENR
1220  *
1221  */
1222 /*
1223  * Field : SSI_EN
1224  *
1225  * SSI Enable. Enables and disables all DW_apb_ssi operations. When
1226  *
1227  * disabled, all serial transfers are halted immediately. Transmit and
1228  *
1229  * receive FIFO buffers are cleared when the device is disabled. It is
1230  *
1231  * impossible to program some of the DW_apb_ssi control registers when
1232  *
1233  * enabled. When disabled, the ssi_sleep output is set (after delay) to
1234  *
1235  * inform the system that it is safe to remove the ssi_clk, thus saving
1236  *
1237  * power consumption in the system.
1238  *
1239  * Field Enumeration Values:
1240  *
1241  * Enum | Value | Description
1242  * :---------------------------------|:------|:-------------------------
1243  * ALT_SPIM_SSIENR_SSI_EN_E_DISABLE | 0x0 | Disables Serial Transfer
1244  * ALT_SPIM_SSIENR_SSI_EN_E_ENABLED | 0x1 | Enables Serial Transfer
1245  *
1246  * Field Access Macros:
1247  *
1248  */
1249 /*
1250  * Enumerated value for register field ALT_SPIM_SSIENR_SSI_EN
1251  *
1252  * Disables Serial Transfer
1253  */
1254 #define ALT_SPIM_SSIENR_SSI_EN_E_DISABLE 0x0
1255 /*
1256  * Enumerated value for register field ALT_SPIM_SSIENR_SSI_EN
1257  *
1258  * Enables Serial Transfer
1259  */
1260 #define ALT_SPIM_SSIENR_SSI_EN_E_ENABLED 0x1
1261 
1262 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SSIENR_SSI_EN register field. */
1263 #define ALT_SPIM_SSIENR_SSI_EN_LSB 0
1264 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SSIENR_SSI_EN register field. */
1265 #define ALT_SPIM_SSIENR_SSI_EN_MSB 0
1266 /* The width in bits of the ALT_SPIM_SSIENR_SSI_EN register field. */
1267 #define ALT_SPIM_SSIENR_SSI_EN_WIDTH 1
1268 /* The mask used to set the ALT_SPIM_SSIENR_SSI_EN register field value. */
1269 #define ALT_SPIM_SSIENR_SSI_EN_SET_MSK 0x00000001
1270 /* The mask used to clear the ALT_SPIM_SSIENR_SSI_EN register field value. */
1271 #define ALT_SPIM_SSIENR_SSI_EN_CLR_MSK 0xfffffffe
1272 /* The reset value of the ALT_SPIM_SSIENR_SSI_EN register field. */
1273 #define ALT_SPIM_SSIENR_SSI_EN_RESET 0x0
1274 /* Extracts the ALT_SPIM_SSIENR_SSI_EN field value from a register. */
1275 #define ALT_SPIM_SSIENR_SSI_EN_GET(value) (((value) & 0x00000001) >> 0)
1276 /* Produces a ALT_SPIM_SSIENR_SSI_EN register field value suitable for setting the register. */
1277 #define ALT_SPIM_SSIENR_SSI_EN_SET(value) (((value) << 0) & 0x00000001)
1278 
1279 /*
1280  * Field : RSVD_SSIENR
1281  *
1282  * Reserved bits - Read Only
1283  *
1284  * Field Access Macros:
1285  *
1286  */
1287 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SSIENR_RSVD_SSIENR register field. */
1288 #define ALT_SPIM_SSIENR_RSVD_SSIENR_LSB 1
1289 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SSIENR_RSVD_SSIENR register field. */
1290 #define ALT_SPIM_SSIENR_RSVD_SSIENR_MSB 31
1291 /* The width in bits of the ALT_SPIM_SSIENR_RSVD_SSIENR register field. */
1292 #define ALT_SPIM_SSIENR_RSVD_SSIENR_WIDTH 31
1293 /* The mask used to set the ALT_SPIM_SSIENR_RSVD_SSIENR register field value. */
1294 #define ALT_SPIM_SSIENR_RSVD_SSIENR_SET_MSK 0xfffffffe
1295 /* The mask used to clear the ALT_SPIM_SSIENR_RSVD_SSIENR register field value. */
1296 #define ALT_SPIM_SSIENR_RSVD_SSIENR_CLR_MSK 0x00000001
1297 /* The reset value of the ALT_SPIM_SSIENR_RSVD_SSIENR register field. */
1298 #define ALT_SPIM_SSIENR_RSVD_SSIENR_RESET 0x0
1299 /* Extracts the ALT_SPIM_SSIENR_RSVD_SSIENR field value from a register. */
1300 #define ALT_SPIM_SSIENR_RSVD_SSIENR_GET(value) (((value) & 0xfffffffe) >> 1)
1301 /* Produces a ALT_SPIM_SSIENR_RSVD_SSIENR register field value suitable for setting the register. */
1302 #define ALT_SPIM_SSIENR_RSVD_SSIENR_SET(value) (((value) << 1) & 0xfffffffe)
1303 
1304 #ifndef __ASSEMBLY__
1305 /*
1306  * WARNING: The C register and register group struct declarations are provided for
1307  * convenience and illustrative purposes. They should, however, be used with
1308  * caution as the C language standard provides no guarantees about the alignment or
1309  * atomicity of device memory accesses. The recommended practice for coding device
1310  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1311  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1312  * alt_write_dword() functions for 64 bit registers.
1313  *
1314  * The struct declaration for register ALT_SPIM_SSIENR.
1315  */
1316 struct ALT_SPIM_SSIENR_s
1317 {
1318  volatile uint32_t SSI_EN : 1; /* ALT_SPIM_SSIENR_SSI_EN */
1319  const volatile uint32_t RSVD_SSIENR : 31; /* ALT_SPIM_SSIENR_RSVD_SSIENR */
1320 };
1321 
1322 /* The typedef declaration for register ALT_SPIM_SSIENR. */
1323 typedef struct ALT_SPIM_SSIENR_s ALT_SPIM_SSIENR_t;
1324 #endif /* __ASSEMBLY__ */
1325 
1326 /* The reset value of the ALT_SPIM_SSIENR register. */
1327 #define ALT_SPIM_SSIENR_RESET 0x00000000
1328 /* The byte offset of the ALT_SPIM_SSIENR register from the beginning of the component. */
1329 #define ALT_SPIM_SSIENR_OFST 0x8
1330 /* The address of the ALT_SPIM_SSIENR register. */
1331 #define ALT_SPIM_SSIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SSIENR_OFST))
1332 
1333 /*
1334  * Register : Microwire Control Register - MWCR
1335  *
1336  * Microwire Control Register.
1337  *
1338  * This register controls the direction of the data word for the half-duplex
1339  *
1340  * Microwire serial protocol. It is impossible to write to this register
1341  *
1342  * when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
1343  *
1344  * writing to the SSIENR register.
1345  *
1346  * Register Layout
1347  *
1348  * Bits | Access | Reset | Description
1349  * :-------|:-------|:------|:------------------------
1350  * [0] | RW | 0x0 | ALT_SPIM_MWCR_MWMOD
1351  * [1] | RW | 0x0 | ALT_SPIM_MWCR_MDD
1352  * [2] | RW | 0x0 | ALT_SPIM_MWCR_MHS
1353  * [31:3] | R | 0x0 | ALT_SPIM_MWCR_RSVD_MWCR
1354  *
1355  */
1356 /*
1357  * Field : MWMOD
1358  *
1359  * Microwire Transfer Mode.
1360  *
1361  * Defines whether the Microwire transfer is sequential or non-sequential.
1362  *
1363  * When sequential mode is used, only one control word is needed to
1364  *
1365  * transmit or receive a block of data words. When non-sequential mode is
1366  *
1367  * used, there must be a control word for each data word that is
1368  *
1369  * transmitted or received.
1370  *
1371  * 0: non-sequential transfer
1372  *
1373  * 1: sequential transfer
1374  *
1375  * Field Enumeration Values:
1376  *
1377  * Enum | Value | Description
1378  * :-------------------------------------|:------|:----------------------------------
1379  * ALT_SPIM_MWCR_MWMOD_E_NON_SEQUENTIAL | 0x0 | Non-Sequential Microwire Transfer
1380  * ALT_SPIM_MWCR_MWMOD_E_SEQUENTIAL | 0x1 | Sequential Microwire Transfer
1381  *
1382  * Field Access Macros:
1383  *
1384  */
1385 /*
1386  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
1387  *
1388  * Non-Sequential Microwire Transfer
1389  */
1390 #define ALT_SPIM_MWCR_MWMOD_E_NON_SEQUENTIAL 0x0
1391 /*
1392  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
1393  *
1394  * Sequential Microwire Transfer
1395  */
1396 #define ALT_SPIM_MWCR_MWMOD_E_SEQUENTIAL 0x1
1397 
1398 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
1399 #define ALT_SPIM_MWCR_MWMOD_LSB 0
1400 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
1401 #define ALT_SPIM_MWCR_MWMOD_MSB 0
1402 /* The width in bits of the ALT_SPIM_MWCR_MWMOD register field. */
1403 #define ALT_SPIM_MWCR_MWMOD_WIDTH 1
1404 /* The mask used to set the ALT_SPIM_MWCR_MWMOD register field value. */
1405 #define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
1406 /* The mask used to clear the ALT_SPIM_MWCR_MWMOD register field value. */
1407 #define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
1408 /* The reset value of the ALT_SPIM_MWCR_MWMOD register field. */
1409 #define ALT_SPIM_MWCR_MWMOD_RESET 0x0
1410 /* Extracts the ALT_SPIM_MWCR_MWMOD field value from a register. */
1411 #define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
1412 /* Produces a ALT_SPIM_MWCR_MWMOD register field value suitable for setting the register. */
1413 #define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
1414 
1415 /*
1416  * Field : MDD
1417  *
1418  * Microwire Control.
1419  *
1420  * Defines the direction of the data word when the Microwire serial protocol
1421  *
1422  * is used. When this bit is set to 0, the data word is received by the
1423  *
1424  * DW_apb_ssi MacroCell from the external serial device. When this bit is
1425  *
1426  * set to 1, the data word is transmitted from the DW_apb_ssi MacroCell to
1427  *
1428  * the external serial device.
1429  *
1430  * Field Enumeration Values:
1431  *
1432  * Enum | Value | Description
1433  * :-----------------------------|:------|:-------------------
1434  * ALT_SPIM_MWCR_MDD_E_RECEIVE | 0x0 | SSI receives data
1435  * ALT_SPIM_MWCR_MDD_E_TRANSMIT | 0x1 | SSI transmits data
1436  *
1437  * Field Access Macros:
1438  *
1439  */
1440 /*
1441  * Enumerated value for register field ALT_SPIM_MWCR_MDD
1442  *
1443  * SSI receives data
1444  */
1445 #define ALT_SPIM_MWCR_MDD_E_RECEIVE 0x0
1446 /*
1447  * Enumerated value for register field ALT_SPIM_MWCR_MDD
1448  *
1449  * SSI transmits data
1450  */
1451 #define ALT_SPIM_MWCR_MDD_E_TRANSMIT 0x1
1452 
1453 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MDD register field. */
1454 #define ALT_SPIM_MWCR_MDD_LSB 1
1455 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MDD register field. */
1456 #define ALT_SPIM_MWCR_MDD_MSB 1
1457 /* The width in bits of the ALT_SPIM_MWCR_MDD register field. */
1458 #define ALT_SPIM_MWCR_MDD_WIDTH 1
1459 /* The mask used to set the ALT_SPIM_MWCR_MDD register field value. */
1460 #define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
1461 /* The mask used to clear the ALT_SPIM_MWCR_MDD register field value. */
1462 #define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
1463 /* The reset value of the ALT_SPIM_MWCR_MDD register field. */
1464 #define ALT_SPIM_MWCR_MDD_RESET 0x0
1465 /* Extracts the ALT_SPIM_MWCR_MDD field value from a register. */
1466 #define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1467 /* Produces a ALT_SPIM_MWCR_MDD register field value suitable for setting the register. */
1468 #define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1469 
1470 /*
1471  * Field : MHS
1472  *
1473  * Microwire Handshaking.
1474  *
1475  * Relevant only when the DW_apb_ssi is configured as a serial-master device.
1476  *
1477  * When configured as a serial slave, this bit field has no functionality.
1478  *
1479  * Used to enable and disable the busy/ready handshaking interface for the
1480  *
1481  * Microwire protocol. When enabled, the DW_apb_ssi checks for a ready status
1482  *
1483  * from the target slave, after the transfer of the last data/control bit,
1484  *
1485  * before clearing the BUSY status in the SR register.
1486  *
1487  * 0: handshaking interface is disabled
1488  *
1489  * 1: handshaking interface is enabled
1490  *
1491  * Field Enumeration Values:
1492  *
1493  * Enum | Value | Description
1494  * :----------------------------|:------|:------------------------
1495  * ALT_SPIM_MWCR_MHS_E_DISABLE | 0x0 | Disables Handshaking IF
1496  * ALT_SPIM_MWCR_MHS_E_ENABLED | 0x1 | Enables Handshaking IF
1497  *
1498  * Field Access Macros:
1499  *
1500  */
1501 /*
1502  * Enumerated value for register field ALT_SPIM_MWCR_MHS
1503  *
1504  * Disables Handshaking IF
1505  */
1506 #define ALT_SPIM_MWCR_MHS_E_DISABLE 0x0
1507 /*
1508  * Enumerated value for register field ALT_SPIM_MWCR_MHS
1509  *
1510  * Enables Handshaking IF
1511  */
1512 #define ALT_SPIM_MWCR_MHS_E_ENABLED 0x1
1513 
1514 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MHS register field. */
1515 #define ALT_SPIM_MWCR_MHS_LSB 2
1516 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MHS register field. */
1517 #define ALT_SPIM_MWCR_MHS_MSB 2
1518 /* The width in bits of the ALT_SPIM_MWCR_MHS register field. */
1519 #define ALT_SPIM_MWCR_MHS_WIDTH 1
1520 /* The mask used to set the ALT_SPIM_MWCR_MHS register field value. */
1521 #define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
1522 /* The mask used to clear the ALT_SPIM_MWCR_MHS register field value. */
1523 #define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
1524 /* The reset value of the ALT_SPIM_MWCR_MHS register field. */
1525 #define ALT_SPIM_MWCR_MHS_RESET 0x0
1526 /* Extracts the ALT_SPIM_MWCR_MHS field value from a register. */
1527 #define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
1528 /* Produces a ALT_SPIM_MWCR_MHS register field value suitable for setting the register. */
1529 #define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
1530 
1531 /*
1532  * Field : RSVD_MWCR
1533  *
1534  * Reserved bits - Read Only
1535  *
1536  * Field Access Macros:
1537  *
1538  */
1539 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_RSVD_MWCR register field. */
1540 #define ALT_SPIM_MWCR_RSVD_MWCR_LSB 3
1541 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_RSVD_MWCR register field. */
1542 #define ALT_SPIM_MWCR_RSVD_MWCR_MSB 31
1543 /* The width in bits of the ALT_SPIM_MWCR_RSVD_MWCR register field. */
1544 #define ALT_SPIM_MWCR_RSVD_MWCR_WIDTH 29
1545 /* The mask used to set the ALT_SPIM_MWCR_RSVD_MWCR register field value. */
1546 #define ALT_SPIM_MWCR_RSVD_MWCR_SET_MSK 0xfffffff8
1547 /* The mask used to clear the ALT_SPIM_MWCR_RSVD_MWCR register field value. */
1548 #define ALT_SPIM_MWCR_RSVD_MWCR_CLR_MSK 0x00000007
1549 /* The reset value of the ALT_SPIM_MWCR_RSVD_MWCR register field. */
1550 #define ALT_SPIM_MWCR_RSVD_MWCR_RESET 0x0
1551 /* Extracts the ALT_SPIM_MWCR_RSVD_MWCR field value from a register. */
1552 #define ALT_SPIM_MWCR_RSVD_MWCR_GET(value) (((value) & 0xfffffff8) >> 3)
1553 /* Produces a ALT_SPIM_MWCR_RSVD_MWCR register field value suitable for setting the register. */
1554 #define ALT_SPIM_MWCR_RSVD_MWCR_SET(value) (((value) << 3) & 0xfffffff8)
1555 
1556 #ifndef __ASSEMBLY__
1557 /*
1558  * WARNING: The C register and register group struct declarations are provided for
1559  * convenience and illustrative purposes. They should, however, be used with
1560  * caution as the C language standard provides no guarantees about the alignment or
1561  * atomicity of device memory accesses. The recommended practice for coding device
1562  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1563  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1564  * alt_write_dword() functions for 64 bit registers.
1565  *
1566  * The struct declaration for register ALT_SPIM_MWCR.
1567  */
1568 struct ALT_SPIM_MWCR_s
1569 {
1570  volatile uint32_t MWMOD : 1; /* ALT_SPIM_MWCR_MWMOD */
1571  volatile uint32_t MDD : 1; /* ALT_SPIM_MWCR_MDD */
1572  volatile uint32_t MHS : 1; /* ALT_SPIM_MWCR_MHS */
1573  const volatile uint32_t RSVD_MWCR : 29; /* ALT_SPIM_MWCR_RSVD_MWCR */
1574 };
1575 
1576 /* The typedef declaration for register ALT_SPIM_MWCR. */
1577 typedef struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t;
1578 #endif /* __ASSEMBLY__ */
1579 
1580 /* The reset value of the ALT_SPIM_MWCR register. */
1581 #define ALT_SPIM_MWCR_RESET 0x00000000
1582 /* The byte offset of the ALT_SPIM_MWCR register from the beginning of the component. */
1583 #define ALT_SPIM_MWCR_OFST 0xc
1584 /* The address of the ALT_SPIM_MWCR register. */
1585 #define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
1586 
1587 /*
1588  * Register : Slave Enable Register - SER
1589  *
1590  * Slave Enable Register.
1591  *
1592  * This register is valid only when the DW_apb_ssi is configured as a master
1593  *
1594  * device. When the DW_apb_ssi is configured as a serial slave, writing to
1595  *
1596  * this location has no effect; reading from this location returns 0. The
1597  *
1598  * register enables the individual slave select output lines from the
1599  *
1600  * DW_apb_ssi master. Up to 16 slave-select output pins are available on the
1601  *
1602  * DW_apb_ssi master. You cannot write to this register when DW_apb_ssi is
1603  *
1604  * busy and when SSI_EN = 1.
1605  *
1606  * Register Layout
1607  *
1608  * Bits | Access | Reset | Description
1609  * :-------|:-------|:------|:----------------------
1610  * [3:0] | RW | 0x0 | ALT_SPIM_SER_SER
1611  * [31:4] | R | 0x0 | ALT_SPIM_SER_RSVD_SER
1612  *
1613  */
1614 /*
1615  * Field : SER
1616  *
1617  * Slave Select Enable Flag.
1618  *
1619  * Each bit in this register corresponds to a slave select line (ss_x_n)
1620  *
1621  * from the DW_apb_ssi master. When a bit in this register is set (1), the
1622  *
1623  * corresponding slave select line from the master is activated when a
1624  *
1625  * serial transfer begins. It should be noted that setting or clearing bits
1626  *
1627  * in this register have no effect on the corresponding slave select outputs
1628  *
1629  * until a transfer is started. Before beginning a transfer, you should
1630  *
1631  * enable the bit in this register that corresponds to the slave device
1632  *
1633  * with which the master wants to communicate. When not operating in
1634  *
1635  * broadcast mode, only one bit in this field should be set.
1636  *
1637  * 1: Selected
1638  *
1639  * 0: Not Selected
1640  *
1641  * Field Enumeration Values:
1642  *
1643  * Enum | Value | Description
1644  * :--------------------------------|:------|:------------------
1645  * ALT_SPIM_SER_SER_E_NOT_SELECTED | 0x0 | No slave selected
1646  * ALT_SPIM_SER_SER_E_SELECTED | 0x1 | Slave is selected
1647  *
1648  * Field Access Macros:
1649  *
1650  */
1651 /*
1652  * Enumerated value for register field ALT_SPIM_SER_SER
1653  *
1654  * No slave selected
1655  */
1656 #define ALT_SPIM_SER_SER_E_NOT_SELECTED 0x0
1657 /*
1658  * Enumerated value for register field ALT_SPIM_SER_SER
1659  *
1660  * Slave is selected
1661  */
1662 #define ALT_SPIM_SER_SER_E_SELECTED 0x1
1663 
1664 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SER_SER register field. */
1665 #define ALT_SPIM_SER_SER_LSB 0
1666 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SER_SER register field. */
1667 #define ALT_SPIM_SER_SER_MSB 3
1668 /* The width in bits of the ALT_SPIM_SER_SER register field. */
1669 #define ALT_SPIM_SER_SER_WIDTH 4
1670 /* The mask used to set the ALT_SPIM_SER_SER register field value. */
1671 #define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
1672 /* The mask used to clear the ALT_SPIM_SER_SER register field value. */
1673 #define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
1674 /* The reset value of the ALT_SPIM_SER_SER register field. */
1675 #define ALT_SPIM_SER_SER_RESET 0x0
1676 /* Extracts the ALT_SPIM_SER_SER field value from a register. */
1677 #define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
1678 /* Produces a ALT_SPIM_SER_SER register field value suitable for setting the register. */
1679 #define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
1680 
1681 /*
1682  * Field : RSVD_SER
1683  *
1684  * Reserved bits - Read Only
1685  *
1686  * Field Access Macros:
1687  *
1688  */
1689 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SER_RSVD_SER register field. */
1690 #define ALT_SPIM_SER_RSVD_SER_LSB 4
1691 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SER_RSVD_SER register field. */
1692 #define ALT_SPIM_SER_RSVD_SER_MSB 31
1693 /* The width in bits of the ALT_SPIM_SER_RSVD_SER register field. */
1694 #define ALT_SPIM_SER_RSVD_SER_WIDTH 28
1695 /* The mask used to set the ALT_SPIM_SER_RSVD_SER register field value. */
1696 #define ALT_SPIM_SER_RSVD_SER_SET_MSK 0xfffffff0
1697 /* The mask used to clear the ALT_SPIM_SER_RSVD_SER register field value. */
1698 #define ALT_SPIM_SER_RSVD_SER_CLR_MSK 0x0000000f
1699 /* The reset value of the ALT_SPIM_SER_RSVD_SER register field. */
1700 #define ALT_SPIM_SER_RSVD_SER_RESET 0x0
1701 /* Extracts the ALT_SPIM_SER_RSVD_SER field value from a register. */
1702 #define ALT_SPIM_SER_RSVD_SER_GET(value) (((value) & 0xfffffff0) >> 4)
1703 /* Produces a ALT_SPIM_SER_RSVD_SER register field value suitable for setting the register. */
1704 #define ALT_SPIM_SER_RSVD_SER_SET(value) (((value) << 4) & 0xfffffff0)
1705 
1706 #ifndef __ASSEMBLY__
1707 /*
1708  * WARNING: The C register and register group struct declarations are provided for
1709  * convenience and illustrative purposes. They should, however, be used with
1710  * caution as the C language standard provides no guarantees about the alignment or
1711  * atomicity of device memory accesses. The recommended practice for coding device
1712  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1713  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1714  * alt_write_dword() functions for 64 bit registers.
1715  *
1716  * The struct declaration for register ALT_SPIM_SER.
1717  */
1718 struct ALT_SPIM_SER_s
1719 {
1720  volatile uint32_t SER : 4; /* ALT_SPIM_SER_SER */
1721  const volatile uint32_t RSVD_SER : 28; /* ALT_SPIM_SER_RSVD_SER */
1722 };
1723 
1724 /* The typedef declaration for register ALT_SPIM_SER. */
1725 typedef struct ALT_SPIM_SER_s ALT_SPIM_SER_t;
1726 #endif /* __ASSEMBLY__ */
1727 
1728 /* The reset value of the ALT_SPIM_SER register. */
1729 #define ALT_SPIM_SER_RESET 0x00000000
1730 /* The byte offset of the ALT_SPIM_SER register from the beginning of the component. */
1731 #define ALT_SPIM_SER_OFST 0x10
1732 /* The address of the ALT_SPIM_SER register. */
1733 #define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
1734 
1735 /*
1736  * Register : Baud Rate Select - BAUDR
1737  *
1738  * Baud Rate Select.
1739  *
1740  * This register is valid only when the DW_apb_ssi is configured as a master
1741  *
1742  * device. When the DW_apb_ssi is configured as a serial slave, writing to
1743  *
1744  * this location has no effect; reading from this location returns 0. The
1745  *
1746  * register derives the frequency of the serial clock that regulates the data
1747  *
1748  * transfer. The 16-bit field in this register defines the ssi_clk divider
1749  *
1750  * value. It is impossible to write to this register when the DW_apb_ssi is
1751  *
1752  * enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR
1753  *
1754  * register.
1755  *
1756  * Register Layout
1757  *
1758  * Bits | Access | Reset | Description
1759  * :--------|:-------|:------|:--------------------------
1760  * [15:0] | RW | 0x0 | ALT_SPIM_BAUDR_SCKDV
1761  * [31:16] | R | 0x0 | ALT_SPIM_BAUDR_RSVD_BAUDR
1762  *
1763  */
1764 /*
1765  * Field : SCKDV
1766  *
1767  * SSI Clock Divider.
1768  *
1769  * The LSB for this field is always set to 0 and is unaffected by a write
1770  *
1771  * operation, which ensures an even value is held in this register. If the
1772  *
1773  * value is 0, the serial output clock (sclk_out) is disabled. The frequency
1774  *
1775  * of the sclk_out is derived from the following equation:
1776  *
1777  * Fsclk_out = Fssi_clk/SCKDV
1778  *
1779  * where SCKDV is any even value between 2 and 65534. For example:
1780  *
1781  * for Fssi_clk = 3.6864MHz and SCKDV =2
1782  *
1783  * Fsclk_out = 3.6864/2 = 1.8432MHz
1784  *
1785  * Field Access Macros:
1786  *
1787  */
1788 /* The Least Significant Bit (LSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
1789 #define ALT_SPIM_BAUDR_SCKDV_LSB 0
1790 /* The Most Significant Bit (MSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
1791 #define ALT_SPIM_BAUDR_SCKDV_MSB 15
1792 /* The width in bits of the ALT_SPIM_BAUDR_SCKDV register field. */
1793 #define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
1794 /* The mask used to set the ALT_SPIM_BAUDR_SCKDV register field value. */
1795 #define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
1796 /* The mask used to clear the ALT_SPIM_BAUDR_SCKDV register field value. */
1797 #define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
1798 /* The reset value of the ALT_SPIM_BAUDR_SCKDV register field. */
1799 #define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
1800 /* Extracts the ALT_SPIM_BAUDR_SCKDV field value from a register. */
1801 #define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
1802 /* Produces a ALT_SPIM_BAUDR_SCKDV register field value suitable for setting the register. */
1803 #define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
1804 
1805 /*
1806  * Field : RSVD_BAUDR
1807  *
1808  * Reserved bits - Read Only
1809  *
1810  * Field Access Macros:
1811  *
1812  */
1813 /* The Least Significant Bit (LSB) position of the ALT_SPIM_BAUDR_RSVD_BAUDR register field. */
1814 #define ALT_SPIM_BAUDR_RSVD_BAUDR_LSB 16
1815 /* The Most Significant Bit (MSB) position of the ALT_SPIM_BAUDR_RSVD_BAUDR register field. */
1816 #define ALT_SPIM_BAUDR_RSVD_BAUDR_MSB 31
1817 /* The width in bits of the ALT_SPIM_BAUDR_RSVD_BAUDR register field. */
1818 #define ALT_SPIM_BAUDR_RSVD_BAUDR_WIDTH 16
1819 /* The mask used to set the ALT_SPIM_BAUDR_RSVD_BAUDR register field value. */
1820 #define ALT_SPIM_BAUDR_RSVD_BAUDR_SET_MSK 0xffff0000
1821 /* The mask used to clear the ALT_SPIM_BAUDR_RSVD_BAUDR register field value. */
1822 #define ALT_SPIM_BAUDR_RSVD_BAUDR_CLR_MSK 0x0000ffff
1823 /* The reset value of the ALT_SPIM_BAUDR_RSVD_BAUDR register field. */
1824 #define ALT_SPIM_BAUDR_RSVD_BAUDR_RESET 0x0
1825 /* Extracts the ALT_SPIM_BAUDR_RSVD_BAUDR field value from a register. */
1826 #define ALT_SPIM_BAUDR_RSVD_BAUDR_GET(value) (((value) & 0xffff0000) >> 16)
1827 /* Produces a ALT_SPIM_BAUDR_RSVD_BAUDR register field value suitable for setting the register. */
1828 #define ALT_SPIM_BAUDR_RSVD_BAUDR_SET(value) (((value) << 16) & 0xffff0000)
1829 
1830 #ifndef __ASSEMBLY__
1831 /*
1832  * WARNING: The C register and register group struct declarations are provided for
1833  * convenience and illustrative purposes. They should, however, be used with
1834  * caution as the C language standard provides no guarantees about the alignment or
1835  * atomicity of device memory accesses. The recommended practice for coding device
1836  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1837  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1838  * alt_write_dword() functions for 64 bit registers.
1839  *
1840  * The struct declaration for register ALT_SPIM_BAUDR.
1841  */
1842 struct ALT_SPIM_BAUDR_s
1843 {
1844  volatile uint32_t SCKDV : 16; /* ALT_SPIM_BAUDR_SCKDV */
1845  const volatile uint32_t RSVD_BAUDR : 16; /* ALT_SPIM_BAUDR_RSVD_BAUDR */
1846 };
1847 
1848 /* The typedef declaration for register ALT_SPIM_BAUDR. */
1849 typedef struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t;
1850 #endif /* __ASSEMBLY__ */
1851 
1852 /* The reset value of the ALT_SPIM_BAUDR register. */
1853 #define ALT_SPIM_BAUDR_RESET 0x00000000
1854 /* The byte offset of the ALT_SPIM_BAUDR register from the beginning of the component. */
1855 #define ALT_SPIM_BAUDR_OFST 0x14
1856 /* The address of the ALT_SPIM_BAUDR register. */
1857 #define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
1858 
1859 /*
1860  * Register : Transmit FIFO Threshold Level - TXFTLR
1861  *
1862  * Transmit FIFO Threshold Level.
1863  *
1864  * This register controls the threshold value for the transmit FIFO memory.
1865  *
1866  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1867  *
1868  * Register Layout
1869  *
1870  * Bits | Access | Reset | Description
1871  * :-------|:-------|:------|:----------------------------
1872  * [7:0] | RW | 0x0 | ALT_SPIM_TXFTLR_TFT
1873  * [31:8] | R | 0x0 | ALT_SPIM_TXFTLR_RSVD_TXFTLR
1874  *
1875  */
1876 /*
1877  * Field : TFT
1878  *
1879  * Transmit FIFO Threshold.
1880  *
1881  * Controls the level of entries (or below) at which the transmit FIFO controller
1882  *
1883  * triggers an interrupt. The FIFO depth is configurable in the range 2-256;
1884  *
1885  * this register is sized to the number of address bits needed to access the
1886  *
1887  * FIFO. If you attempt to set this value greater than or equal to the depth
1888  *
1889  * of the FIFO, this field is not written and retains its current value. When
1890  *
1891  * the number of transmit FIFO entries is less than or equal to this value,
1892  *
1893  * the transmit FIFO empty interrupt is triggered.
1894  *
1895  * Field Access Macros:
1896  *
1897  */
1898 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1899 #define ALT_SPIM_TXFTLR_TFT_LSB 0
1900 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1901 #define ALT_SPIM_TXFTLR_TFT_MSB 7
1902 /* The width in bits of the ALT_SPIM_TXFTLR_TFT register field. */
1903 #define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1904 /* The mask used to set the ALT_SPIM_TXFTLR_TFT register field value. */
1905 #define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1906 /* The mask used to clear the ALT_SPIM_TXFTLR_TFT register field value. */
1907 #define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1908 /* The reset value of the ALT_SPIM_TXFTLR_TFT register field. */
1909 #define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1910 /* Extracts the ALT_SPIM_TXFTLR_TFT field value from a register. */
1911 #define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1912 /* Produces a ALT_SPIM_TXFTLR_TFT register field value suitable for setting the register. */
1913 #define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1914 
1915 /*
1916  * Field : RSVD_TXFTLR
1917  *
1918  * Reserved bits - Read Only
1919  *
1920  * Field Access Macros:
1921  *
1922  */
1923 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field. */
1924 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_LSB 8
1925 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field. */
1926 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_MSB 31
1927 /* The width in bits of the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field. */
1928 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_WIDTH 24
1929 /* The mask used to set the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field value. */
1930 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_SET_MSK 0xffffff00
1931 /* The mask used to clear the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field value. */
1932 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_CLR_MSK 0x000000ff
1933 /* The reset value of the ALT_SPIM_TXFTLR_RSVD_TXFTLR register field. */
1934 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_RESET 0x0
1935 /* Extracts the ALT_SPIM_TXFTLR_RSVD_TXFTLR field value from a register. */
1936 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1937 /* Produces a ALT_SPIM_TXFTLR_RSVD_TXFTLR register field value suitable for setting the register. */
1938 #define ALT_SPIM_TXFTLR_RSVD_TXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1939 
1940 #ifndef __ASSEMBLY__
1941 /*
1942  * WARNING: The C register and register group struct declarations are provided for
1943  * convenience and illustrative purposes. They should, however, be used with
1944  * caution as the C language standard provides no guarantees about the alignment or
1945  * atomicity of device memory accesses. The recommended practice for coding device
1946  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1947  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1948  * alt_write_dword() functions for 64 bit registers.
1949  *
1950  * The struct declaration for register ALT_SPIM_TXFTLR.
1951  */
1952 struct ALT_SPIM_TXFTLR_s
1953 {
1954  volatile uint32_t TFT : 8; /* ALT_SPIM_TXFTLR_TFT */
1955  const volatile uint32_t RSVD_TXFTLR : 24; /* ALT_SPIM_TXFTLR_RSVD_TXFTLR */
1956 };
1957 
1958 /* The typedef declaration for register ALT_SPIM_TXFTLR. */
1959 typedef struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t;
1960 #endif /* __ASSEMBLY__ */
1961 
1962 /* The reset value of the ALT_SPIM_TXFTLR register. */
1963 #define ALT_SPIM_TXFTLR_RESET 0x00000000
1964 /* The byte offset of the ALT_SPIM_TXFTLR register from the beginning of the component. */
1965 #define ALT_SPIM_TXFTLR_OFST 0x18
1966 /* The address of the ALT_SPIM_TXFTLR register. */
1967 #define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
1968 
1969 /*
1970  * Register : Receive FIFO Threshold Level - RXFTLR
1971  *
1972  * Receive FIFO Threshold level.
1973  *
1974  * This register controls the threshold value for the receive FIFO memory.
1975  *
1976  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1977  *
1978  * Register Layout
1979  *
1980  * Bits | Access | Reset | Description
1981  * :-------|:-------|:------|:----------------------------
1982  * [7:0] | RW | 0x0 | ALT_SPIM_RXFTLR_RFT
1983  * [31:8] | R | 0x0 | ALT_SPIM_RXFTLR_RSVD_RXFTLR
1984  *
1985  */
1986 /*
1987  * Field : RFT
1988  *
1989  * Receive FIFO Threshold.
1990  *
1991  * Controls the level of entries (or above) at which the receive FIFO
1992  *
1993  * controller triggers an interrupt. The FIFO depth is configurable in
1994  *
1995  * the range 2-256. This register is sized to the number of address bits
1996  *
1997  * needed to access the FIFO. If you attempt to set this value greater
1998  *
1999  * than the depth of the FIFO, this field is not written and retains its
2000  *
2001  * current value. When the number of receive FIFO entries is greater than
2002  *
2003  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
2004  *
2005  * Field Access Macros:
2006  *
2007  */
2008 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
2009 #define ALT_SPIM_RXFTLR_RFT_LSB 0
2010 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
2011 #define ALT_SPIM_RXFTLR_RFT_MSB 7
2012 /* The width in bits of the ALT_SPIM_RXFTLR_RFT register field. */
2013 #define ALT_SPIM_RXFTLR_RFT_WIDTH 8
2014 /* The mask used to set the ALT_SPIM_RXFTLR_RFT register field value. */
2015 #define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
2016 /* The mask used to clear the ALT_SPIM_RXFTLR_RFT register field value. */
2017 #define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
2018 /* The reset value of the ALT_SPIM_RXFTLR_RFT register field. */
2019 #define ALT_SPIM_RXFTLR_RFT_RESET 0x0
2020 /* Extracts the ALT_SPIM_RXFTLR_RFT field value from a register. */
2021 #define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
2022 /* Produces a ALT_SPIM_RXFTLR_RFT register field value suitable for setting the register. */
2023 #define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
2024 
2025 /*
2026  * Field : RSVD_RXFTLR
2027  *
2028  * Reserved bits - Read Only
2029  *
2030  * Field Access Macros:
2031  *
2032  */
2033 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field. */
2034 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_LSB 8
2035 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field. */
2036 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_MSB 31
2037 /* The width in bits of the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field. */
2038 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_WIDTH 24
2039 /* The mask used to set the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field value. */
2040 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_SET_MSK 0xffffff00
2041 /* The mask used to clear the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field value. */
2042 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_CLR_MSK 0x000000ff
2043 /* The reset value of the ALT_SPIM_RXFTLR_RSVD_RXFTLR register field. */
2044 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_RESET 0x0
2045 /* Extracts the ALT_SPIM_RXFTLR_RSVD_RXFTLR field value from a register. */
2046 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
2047 /* Produces a ALT_SPIM_RXFTLR_RSVD_RXFTLR register field value suitable for setting the register. */
2048 #define ALT_SPIM_RXFTLR_RSVD_RXFTLR_SET(value) (((value) << 8) & 0xffffff00)
2049 
2050 #ifndef __ASSEMBLY__
2051 /*
2052  * WARNING: The C register and register group struct declarations are provided for
2053  * convenience and illustrative purposes. They should, however, be used with
2054  * caution as the C language standard provides no guarantees about the alignment or
2055  * atomicity of device memory accesses. The recommended practice for coding device
2056  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2057  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2058  * alt_write_dword() functions for 64 bit registers.
2059  *
2060  * The struct declaration for register ALT_SPIM_RXFTLR.
2061  */
2062 struct ALT_SPIM_RXFTLR_s
2063 {
2064  volatile uint32_t RFT : 8; /* ALT_SPIM_RXFTLR_RFT */
2065  const volatile uint32_t RSVD_RXFTLR : 24; /* ALT_SPIM_RXFTLR_RSVD_RXFTLR */
2066 };
2067 
2068 /* The typedef declaration for register ALT_SPIM_RXFTLR. */
2069 typedef struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t;
2070 #endif /* __ASSEMBLY__ */
2071 
2072 /* The reset value of the ALT_SPIM_RXFTLR register. */
2073 #define ALT_SPIM_RXFTLR_RESET 0x00000000
2074 /* The byte offset of the ALT_SPIM_RXFTLR register from the beginning of the component. */
2075 #define ALT_SPIM_RXFTLR_OFST 0x1c
2076 /* The address of the ALT_SPIM_RXFTLR register. */
2077 #define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
2078 
2079 /*
2080  * Register : Transmit FIFO Level Register - TXFLR
2081  *
2082  * Transmit FIFO Level Register
2083  *
2084  * Register Layout
2085  *
2086  * Bits | Access | Reset | Description
2087  * :-------|:-------|:------|:--------------------------
2088  * [8:0] | R | 0x0 | ALT_SPIM_TXFLR_TXTFL
2089  * [31:9] | R | 0x0 | ALT_SPIM_TXFLR_RSVD_TXFLR
2090  *
2091  */
2092 /*
2093  * Field : TXTFL
2094  *
2095  * Transmit FIFO Level.
2096  *
2097  * Contains the number of valid data entries in the transmit FIFO.
2098  *
2099  * Field Access Macros:
2100  *
2101  */
2102 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
2103 #define ALT_SPIM_TXFLR_TXTFL_LSB 0
2104 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
2105 #define ALT_SPIM_TXFLR_TXTFL_MSB 8
2106 /* The width in bits of the ALT_SPIM_TXFLR_TXTFL register field. */
2107 #define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
2108 /* The mask used to set the ALT_SPIM_TXFLR_TXTFL register field value. */
2109 #define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
2110 /* The mask used to clear the ALT_SPIM_TXFLR_TXTFL register field value. */
2111 #define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
2112 /* The reset value of the ALT_SPIM_TXFLR_TXTFL register field. */
2113 #define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
2114 /* Extracts the ALT_SPIM_TXFLR_TXTFL field value from a register. */
2115 #define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
2116 /* Produces a ALT_SPIM_TXFLR_TXTFL register field value suitable for setting the register. */
2117 #define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
2118 
2119 /*
2120  * Field : RSVD_TXFLR
2121  *
2122  * Reserved bits - Read Only
2123  *
2124  * Field Access Macros:
2125  *
2126  */
2127 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFLR_RSVD_TXFLR register field. */
2128 #define ALT_SPIM_TXFLR_RSVD_TXFLR_LSB 9
2129 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFLR_RSVD_TXFLR register field. */
2130 #define ALT_SPIM_TXFLR_RSVD_TXFLR_MSB 31
2131 /* The width in bits of the ALT_SPIM_TXFLR_RSVD_TXFLR register field. */
2132 #define ALT_SPIM_TXFLR_RSVD_TXFLR_WIDTH 23
2133 /* The mask used to set the ALT_SPIM_TXFLR_RSVD_TXFLR register field value. */
2134 #define ALT_SPIM_TXFLR_RSVD_TXFLR_SET_MSK 0xfffffe00
2135 /* The mask used to clear the ALT_SPIM_TXFLR_RSVD_TXFLR register field value. */
2136 #define ALT_SPIM_TXFLR_RSVD_TXFLR_CLR_MSK 0x000001ff
2137 /* The reset value of the ALT_SPIM_TXFLR_RSVD_TXFLR register field. */
2138 #define ALT_SPIM_TXFLR_RSVD_TXFLR_RESET 0x0
2139 /* Extracts the ALT_SPIM_TXFLR_RSVD_TXFLR field value from a register. */
2140 #define ALT_SPIM_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
2141 /* Produces a ALT_SPIM_TXFLR_RSVD_TXFLR register field value suitable for setting the register. */
2142 #define ALT_SPIM_TXFLR_RSVD_TXFLR_SET(value) (((value) << 9) & 0xfffffe00)
2143 
2144 #ifndef __ASSEMBLY__
2145 /*
2146  * WARNING: The C register and register group struct declarations are provided for
2147  * convenience and illustrative purposes. They should, however, be used with
2148  * caution as the C language standard provides no guarantees about the alignment or
2149  * atomicity of device memory accesses. The recommended practice for coding device
2150  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2151  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2152  * alt_write_dword() functions for 64 bit registers.
2153  *
2154  * The struct declaration for register ALT_SPIM_TXFLR.
2155  */
2156 struct ALT_SPIM_TXFLR_s
2157 {
2158  const volatile uint32_t TXTFL : 9; /* ALT_SPIM_TXFLR_TXTFL */
2159  const volatile uint32_t RSVD_TXFLR : 23; /* ALT_SPIM_TXFLR_RSVD_TXFLR */
2160 };
2161 
2162 /* The typedef declaration for register ALT_SPIM_TXFLR. */
2163 typedef struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t;
2164 #endif /* __ASSEMBLY__ */
2165 
2166 /* The reset value of the ALT_SPIM_TXFLR register. */
2167 #define ALT_SPIM_TXFLR_RESET 0x00000000
2168 /* The byte offset of the ALT_SPIM_TXFLR register from the beginning of the component. */
2169 #define ALT_SPIM_TXFLR_OFST 0x20
2170 /* The address of the ALT_SPIM_TXFLR register. */
2171 #define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
2172 
2173 /*
2174  * Register : Receive FIFO Level Register - RXFLR
2175  *
2176  * Receive FIFO Level Register
2177  *
2178  * Register Layout
2179  *
2180  * Bits | Access | Reset | Description
2181  * :-------|:-------|:------|:--------------------------
2182  * [8:0] | R | 0x0 | ALT_SPIM_RXFLR_RXTFL
2183  * [31:9] | R | 0x0 | ALT_SPIM_RXFLR_RSVD_RXFLR
2184  *
2185  */
2186 /*
2187  * Field : RXTFL
2188  *
2189  * Receive FIFO Level.
2190  *
2191  * Contains the number of valid data entries in the receive FIFO.
2192  *
2193  * Field Access Macros:
2194  *
2195  */
2196 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
2197 #define ALT_SPIM_RXFLR_RXTFL_LSB 0
2198 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
2199 #define ALT_SPIM_RXFLR_RXTFL_MSB 8
2200 /* The width in bits of the ALT_SPIM_RXFLR_RXTFL register field. */
2201 #define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
2202 /* The mask used to set the ALT_SPIM_RXFLR_RXTFL register field value. */
2203 #define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
2204 /* The mask used to clear the ALT_SPIM_RXFLR_RXTFL register field value. */
2205 #define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
2206 /* The reset value of the ALT_SPIM_RXFLR_RXTFL register field. */
2207 #define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
2208 /* Extracts the ALT_SPIM_RXFLR_RXTFL field value from a register. */
2209 #define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
2210 /* Produces a ALT_SPIM_RXFLR_RXTFL register field value suitable for setting the register. */
2211 #define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
2212 
2213 /*
2214  * Field : RSVD_RXFLR
2215  *
2216  * Reserved bits - Read Only
2217  *
2218  * Field Access Macros:
2219  *
2220  */
2221 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFLR_RSVD_RXFLR register field. */
2222 #define ALT_SPIM_RXFLR_RSVD_RXFLR_LSB 9
2223 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFLR_RSVD_RXFLR register field. */
2224 #define ALT_SPIM_RXFLR_RSVD_RXFLR_MSB 31
2225 /* The width in bits of the ALT_SPIM_RXFLR_RSVD_RXFLR register field. */
2226 #define ALT_SPIM_RXFLR_RSVD_RXFLR_WIDTH 23
2227 /* The mask used to set the ALT_SPIM_RXFLR_RSVD_RXFLR register field value. */
2228 #define ALT_SPIM_RXFLR_RSVD_RXFLR_SET_MSK 0xfffffe00
2229 /* The mask used to clear the ALT_SPIM_RXFLR_RSVD_RXFLR register field value. */
2230 #define ALT_SPIM_RXFLR_RSVD_RXFLR_CLR_MSK 0x000001ff
2231 /* The reset value of the ALT_SPIM_RXFLR_RSVD_RXFLR register field. */
2232 #define ALT_SPIM_RXFLR_RSVD_RXFLR_RESET 0x0
2233 /* Extracts the ALT_SPIM_RXFLR_RSVD_RXFLR field value from a register. */
2234 #define ALT_SPIM_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
2235 /* Produces a ALT_SPIM_RXFLR_RSVD_RXFLR register field value suitable for setting the register. */
2236 #define ALT_SPIM_RXFLR_RSVD_RXFLR_SET(value) (((value) << 9) & 0xfffffe00)
2237 
2238 #ifndef __ASSEMBLY__
2239 /*
2240  * WARNING: The C register and register group struct declarations are provided for
2241  * convenience and illustrative purposes. They should, however, be used with
2242  * caution as the C language standard provides no guarantees about the alignment or
2243  * atomicity of device memory accesses. The recommended practice for coding device
2244  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2245  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2246  * alt_write_dword() functions for 64 bit registers.
2247  *
2248  * The struct declaration for register ALT_SPIM_RXFLR.
2249  */
2250 struct ALT_SPIM_RXFLR_s
2251 {
2252  const volatile uint32_t RXTFL : 9; /* ALT_SPIM_RXFLR_RXTFL */
2253  const volatile uint32_t RSVD_RXFLR : 23; /* ALT_SPIM_RXFLR_RSVD_RXFLR */
2254 };
2255 
2256 /* The typedef declaration for register ALT_SPIM_RXFLR. */
2257 typedef struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t;
2258 #endif /* __ASSEMBLY__ */
2259 
2260 /* The reset value of the ALT_SPIM_RXFLR register. */
2261 #define ALT_SPIM_RXFLR_RESET 0x00000000
2262 /* The byte offset of the ALT_SPIM_RXFLR register from the beginning of the component. */
2263 #define ALT_SPIM_RXFLR_OFST 0x24
2264 /* The address of the ALT_SPIM_RXFLR register. */
2265 #define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
2266 
2267 /*
2268  * Register : Status Register - SR
2269  *
2270  * Status Register.
2271  *
2272  * This is a read-only register used to indicate the current transfer status,
2273  *
2274  * FIFO status, and any transmission/reception errors that may have occurred.
2275  *
2276  * The status register may be read at any time. None of the bits in this
2277  *
2278  * register request an interrupt.
2279  *
2280  * Register Layout
2281  *
2282  * Bits | Access | Reset | Description
2283  * :-------|:-------|:------|:---------------------
2284  * [0] | R | 0x0 | ALT_SPIM_SR_BUSY
2285  * [1] | R | 0x1 | ALT_SPIM_SR_TFNF
2286  * [2] | R | 0x1 | ALT_SPIM_SR_TFE
2287  * [3] | R | 0x0 | ALT_SPIM_SR_RFNE
2288  * [4] | R | 0x0 | ALT_SPIM_SR_RFF
2289  * [5] | R | 0x0 | ALT_SPIM_SR_RSVD_TXE
2290  * [6] | R | 0x0 | ALT_SPIM_SR_DCOL
2291  * [31:7] | R | 0x0 | ALT_SPIM_SR_RSVD_SR
2292  *
2293  */
2294 /*
2295  * Field : BUSY
2296  *
2297  * SSI Busy Flag.
2298  *
2299  * When set, indicates that a serial transfer is in progress; when cleared
2300  *
2301  * indicates that the DW_apb_ssi is idle or disabled.
2302  *
2303  * 0 - DW_apb_ssi is idle or disabled
2304  *
2305  * 1 - DW_apb_ssi is actively transferring data
2306  *
2307  * Field Enumeration Values:
2308  *
2309  * Enum | Value | Description
2310  * :----------------------------|:------|:---------------------
2311  * ALT_SPIM_SR_BUSY_E_INACTIVE | 0x0 | SSI is Idle/Disabled
2312  * ALT_SPIM_SR_BUSY_E_ACTIVE | 0x1 | SSI is Active
2313  *
2314  * Field Access Macros:
2315  *
2316  */
2317 /*
2318  * Enumerated value for register field ALT_SPIM_SR_BUSY
2319  *
2320  * SSI is Idle/Disabled
2321  */
2322 #define ALT_SPIM_SR_BUSY_E_INACTIVE 0x0
2323 /*
2324  * Enumerated value for register field ALT_SPIM_SR_BUSY
2325  *
2326  * SSI is Active
2327  */
2328 #define ALT_SPIM_SR_BUSY_E_ACTIVE 0x1
2329 
2330 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_BUSY register field. */
2331 #define ALT_SPIM_SR_BUSY_LSB 0
2332 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_BUSY register field. */
2333 #define ALT_SPIM_SR_BUSY_MSB 0
2334 /* The width in bits of the ALT_SPIM_SR_BUSY register field. */
2335 #define ALT_SPIM_SR_BUSY_WIDTH 1
2336 /* The mask used to set the ALT_SPIM_SR_BUSY register field value. */
2337 #define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
2338 /* The mask used to clear the ALT_SPIM_SR_BUSY register field value. */
2339 #define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
2340 /* The reset value of the ALT_SPIM_SR_BUSY register field. */
2341 #define ALT_SPIM_SR_BUSY_RESET 0x0
2342 /* Extracts the ALT_SPIM_SR_BUSY field value from a register. */
2343 #define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
2344 /* Produces a ALT_SPIM_SR_BUSY register field value suitable for setting the register. */
2345 #define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
2346 
2347 /*
2348  * Field : TFNF
2349  *
2350  * Transmit FIFO Not Full. Set when the transmit FIFO contains one or more
2351  *
2352  * empty locations, and is cleared when the FIFO is full.
2353  *
2354  * 0 - Transmit FIFO is full
2355  *
2356  * 1 - Transmit FIFO is not full
2357  *
2358  * Field Enumeration Values:
2359  *
2360  * Enum | Value | Description
2361  * :----------------------------|:------|:--------------------
2362  * ALT_SPIM_SR_TFNF_E_FULL | 0x0 | Tx FIFO is full
2363  * ALT_SPIM_SR_TFNF_E_NOT_FULL | 0x1 | Tx FIFO is not Full
2364  *
2365  * Field Access Macros:
2366  *
2367  */
2368 /*
2369  * Enumerated value for register field ALT_SPIM_SR_TFNF
2370  *
2371  * Tx FIFO is full
2372  */
2373 #define ALT_SPIM_SR_TFNF_E_FULL 0x0
2374 /*
2375  * Enumerated value for register field ALT_SPIM_SR_TFNF
2376  *
2377  * Tx FIFO is not Full
2378  */
2379 #define ALT_SPIM_SR_TFNF_E_NOT_FULL 0x1
2380 
2381 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFNF register field. */
2382 #define ALT_SPIM_SR_TFNF_LSB 1
2383 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFNF register field. */
2384 #define ALT_SPIM_SR_TFNF_MSB 1
2385 /* The width in bits of the ALT_SPIM_SR_TFNF register field. */
2386 #define ALT_SPIM_SR_TFNF_WIDTH 1
2387 /* The mask used to set the ALT_SPIM_SR_TFNF register field value. */
2388 #define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
2389 /* The mask used to clear the ALT_SPIM_SR_TFNF register field value. */
2390 #define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
2391 /* The reset value of the ALT_SPIM_SR_TFNF register field. */
2392 #define ALT_SPIM_SR_TFNF_RESET 0x1
2393 /* Extracts the ALT_SPIM_SR_TFNF field value from a register. */
2394 #define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
2395 /* Produces a ALT_SPIM_SR_TFNF register field value suitable for setting the register. */
2396 #define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
2397 
2398 /*
2399  * Field : TFE
2400  *
2401  * Transmit FIFO Empty.
2402  *
2403  * When the transmit FIFO is completely empty, this bit is set. When the
2404  *
2405  * transmit FIFO contains one or more valid entries, this bit is cleared.
2406  *
2407  * This bit field does not request an interrupt.
2408  *
2409  * 0 - Transmit FIFO is not empty
2410  *
2411  * 1 - Transmit FIFO is empty
2412  *
2413  * Field Enumeration Values:
2414  *
2415  * Enum | Value | Description
2416  * :----------------------------|:------|:--------------------
2417  * ALT_SPIM_SR_TFE_E_NOT_EMPTY | 0x0 | Tx FIFO is nonempty
2418  * ALT_SPIM_SR_TFE_E_EMPTY | 0x1 | Tx FIFO is empty
2419  *
2420  * Field Access Macros:
2421  *
2422  */
2423 /*
2424  * Enumerated value for register field ALT_SPIM_SR_TFE
2425  *
2426  * Tx FIFO is nonempty
2427  */
2428 #define ALT_SPIM_SR_TFE_E_NOT_EMPTY 0x0
2429 /*
2430  * Enumerated value for register field ALT_SPIM_SR_TFE
2431  *
2432  * Tx FIFO is empty
2433  */
2434 #define ALT_SPIM_SR_TFE_E_EMPTY 0x1
2435 
2436 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFE register field. */
2437 #define ALT_SPIM_SR_TFE_LSB 2
2438 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFE register field. */
2439 #define ALT_SPIM_SR_TFE_MSB 2
2440 /* The width in bits of the ALT_SPIM_SR_TFE register field. */
2441 #define ALT_SPIM_SR_TFE_WIDTH 1
2442 /* The mask used to set the ALT_SPIM_SR_TFE register field value. */
2443 #define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
2444 /* The mask used to clear the ALT_SPIM_SR_TFE register field value. */
2445 #define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
2446 /* The reset value of the ALT_SPIM_SR_TFE register field. */
2447 #define ALT_SPIM_SR_TFE_RESET 0x1
2448 /* Extracts the ALT_SPIM_SR_TFE field value from a register. */
2449 #define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
2450 /* Produces a ALT_SPIM_SR_TFE register field value suitable for setting the register. */
2451 #define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
2452 
2453 /*
2454  * Field : RFNE
2455  *
2456  * Receive FIFO Not Empty.
2457  *
2458  * Set when the receive FIFO contains one or more entries and is cleared
2459  *
2460  * when the receive FIFO is empty. This bit can be polled by software to
2461  *
2462  * completely empty the receive FIFO.
2463  *
2464  * 0 - Receive FIFO is empty
2465  *
2466  * 1 - Receive FIFO is not empty
2467  *
2468  * Field Enumeration Values:
2469  *
2470  * Enum | Value | Description
2471  * :-----------------------------|:------|:--------------------
2472  * ALT_SPIM_SR_RFNE_E_EMPTY | 0x0 | Rx FIFO is empty
2473  * ALT_SPIM_SR_RFNE_E_NOT_EMPTY | 0x1 | Rx FIFO is nonempty
2474  *
2475  * Field Access Macros:
2476  *
2477  */
2478 /*
2479  * Enumerated value for register field ALT_SPIM_SR_RFNE
2480  *
2481  * Rx FIFO is empty
2482  */
2483 #define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
2484 /*
2485  * Enumerated value for register field ALT_SPIM_SR_RFNE
2486  *
2487  * Rx FIFO is nonempty
2488  */
2489 #define ALT_SPIM_SR_RFNE_E_NOT_EMPTY 0x1
2490 
2491 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFNE register field. */
2492 #define ALT_SPIM_SR_RFNE_LSB 3
2493 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFNE register field. */
2494 #define ALT_SPIM_SR_RFNE_MSB 3
2495 /* The width in bits of the ALT_SPIM_SR_RFNE register field. */
2496 #define ALT_SPIM_SR_RFNE_WIDTH 1
2497 /* The mask used to set the ALT_SPIM_SR_RFNE register field value. */
2498 #define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
2499 /* The mask used to clear the ALT_SPIM_SR_RFNE register field value. */
2500 #define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
2501 /* The reset value of the ALT_SPIM_SR_RFNE register field. */
2502 #define ALT_SPIM_SR_RFNE_RESET 0x0
2503 /* Extracts the ALT_SPIM_SR_RFNE field value from a register. */
2504 #define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
2505 /* Produces a ALT_SPIM_SR_RFNE register field value suitable for setting the register. */
2506 #define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
2507 
2508 /*
2509  * Field : RFF
2510  *
2511  * Receive FIFO Full. When the receive FIFO is completely full, this bit
2512  *
2513  * is set. When the receive FIFO contains one or more empty location, this
2514  *
2515  * bit is cleared.
2516  *
2517  * 0 - Receive FIFO is not full
2518  *
2519  * 1 - Receive FIFO is full
2520  *
2521  * Field Enumeration Values:
2522  *
2523  * Enum | Value | Description
2524  * :---------------------------|:------|:--------------------
2525  * ALT_SPIM_SR_RFF_E_NOT_FULL | 0x0 | RX FIFO is not full
2526  * ALT_SPIM_SR_RFF_E_FULL | 0x1 | Rx FIFO is full
2527  *
2528  * Field Access Macros:
2529  *
2530  */
2531 /*
2532  * Enumerated value for register field ALT_SPIM_SR_RFF
2533  *
2534  * RX FIFO is not full
2535  */
2536 #define ALT_SPIM_SR_RFF_E_NOT_FULL 0x0
2537 /*
2538  * Enumerated value for register field ALT_SPIM_SR_RFF
2539  *
2540  * Rx FIFO is full
2541  */
2542 #define ALT_SPIM_SR_RFF_E_FULL 0x1
2543 
2544 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFF register field. */
2545 #define ALT_SPIM_SR_RFF_LSB 4
2546 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFF register field. */
2547 #define ALT_SPIM_SR_RFF_MSB 4
2548 /* The width in bits of the ALT_SPIM_SR_RFF register field. */
2549 #define ALT_SPIM_SR_RFF_WIDTH 1
2550 /* The mask used to set the ALT_SPIM_SR_RFF register field value. */
2551 #define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
2552 /* The mask used to clear the ALT_SPIM_SR_RFF register field value. */
2553 #define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
2554 /* The reset value of the ALT_SPIM_SR_RFF register field. */
2555 #define ALT_SPIM_SR_RFF_RESET 0x0
2556 /* Extracts the ALT_SPIM_SR_RFF field value from a register. */
2557 #define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
2558 /* Produces a ALT_SPIM_SR_RFF register field value suitable for setting the register. */
2559 #define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
2560 
2561 /*
2562  * Field : RSVD_TXE
2563  *
2564  * Reserved field- read-only
2565  *
2566  * Field Access Macros:
2567  *
2568  */
2569 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RSVD_TXE register field. */
2570 #define ALT_SPIM_SR_RSVD_TXE_LSB 5
2571 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RSVD_TXE register field. */
2572 #define ALT_SPIM_SR_RSVD_TXE_MSB 5
2573 /* The width in bits of the ALT_SPIM_SR_RSVD_TXE register field. */
2574 #define ALT_SPIM_SR_RSVD_TXE_WIDTH 1
2575 /* The mask used to set the ALT_SPIM_SR_RSVD_TXE register field value. */
2576 #define ALT_SPIM_SR_RSVD_TXE_SET_MSK 0x00000020
2577 /* The mask used to clear the ALT_SPIM_SR_RSVD_TXE register field value. */
2578 #define ALT_SPIM_SR_RSVD_TXE_CLR_MSK 0xffffffdf
2579 /* The reset value of the ALT_SPIM_SR_RSVD_TXE register field. */
2580 #define ALT_SPIM_SR_RSVD_TXE_RESET 0x0
2581 /* Extracts the ALT_SPIM_SR_RSVD_TXE field value from a register. */
2582 #define ALT_SPIM_SR_RSVD_TXE_GET(value) (((value) & 0x00000020) >> 5)
2583 /* Produces a ALT_SPIM_SR_RSVD_TXE register field value suitable for setting the register. */
2584 #define ALT_SPIM_SR_RSVD_TXE_SET(value) (((value) << 5) & 0x00000020)
2585 
2586 /*
2587  * Field : DCOL
2588  *
2589  * Data Collision Error.
2590  *
2591  * Relevant only when the DW_apb_ssi is configured as a master device.
2592  *
2593  * This bit will be set if ss_in_n input is asserted by other master,
2594  *
2595  * when the DW_apb_ssi master is in the middle of the transfer. This informs the
2596  * processor that the
2597  *
2598  * last data transfer was halted before completion. This bit is cleared
2599  *
2600  * when read.
2601  *
2602  * 0 - No error
2603  *
2604  * 1 - Transmit data collision error
2605  *
2606  * Field Enumeration Values:
2607  *
2608  * Enum | Value | Description
2609  * :--------------------------------------|:------|:------------------------
2610  * ALT_SPIM_SR_DCOL_E_NO_ERROR_CONDITION | 0x0 | No Data Error Condition
2611  * ALT_SPIM_SR_DCOL_E_TX_COLLISION_ERROR | 0x1 | TX Data Collision Error
2612  *
2613  * Field Access Macros:
2614  *
2615  */
2616 /*
2617  * Enumerated value for register field ALT_SPIM_SR_DCOL
2618  *
2619  * No Data Error Condition
2620  */
2621 #define ALT_SPIM_SR_DCOL_E_NO_ERROR_CONDITION 0x0
2622 /*
2623  * Enumerated value for register field ALT_SPIM_SR_DCOL
2624  *
2625  * TX Data Collision Error
2626  */
2627 #define ALT_SPIM_SR_DCOL_E_TX_COLLISION_ERROR 0x1
2628 
2629 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_DCOL register field. */
2630 #define ALT_SPIM_SR_DCOL_LSB 6
2631 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_DCOL register field. */
2632 #define ALT_SPIM_SR_DCOL_MSB 6
2633 /* The width in bits of the ALT_SPIM_SR_DCOL register field. */
2634 #define ALT_SPIM_SR_DCOL_WIDTH 1
2635 /* The mask used to set the ALT_SPIM_SR_DCOL register field value. */
2636 #define ALT_SPIM_SR_DCOL_SET_MSK 0x00000040
2637 /* The mask used to clear the ALT_SPIM_SR_DCOL register field value. */
2638 #define ALT_SPIM_SR_DCOL_CLR_MSK 0xffffffbf
2639 /* The reset value of the ALT_SPIM_SR_DCOL register field. */
2640 #define ALT_SPIM_SR_DCOL_RESET 0x0
2641 /* Extracts the ALT_SPIM_SR_DCOL field value from a register. */
2642 #define ALT_SPIM_SR_DCOL_GET(value) (((value) & 0x00000040) >> 6)
2643 /* Produces a ALT_SPIM_SR_DCOL register field value suitable for setting the register. */
2644 #define ALT_SPIM_SR_DCOL_SET(value) (((value) << 6) & 0x00000040)
2645 
2646 /*
2647  * Field : RSVD_SR
2648  *
2649  * Reserved bits - Read Only
2650  *
2651  * Field Access Macros:
2652  *
2653  */
2654 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RSVD_SR register field. */
2655 #define ALT_SPIM_SR_RSVD_SR_LSB 7
2656 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RSVD_SR register field. */
2657 #define ALT_SPIM_SR_RSVD_SR_MSB 31
2658 /* The width in bits of the ALT_SPIM_SR_RSVD_SR register field. */
2659 #define ALT_SPIM_SR_RSVD_SR_WIDTH 25
2660 /* The mask used to set the ALT_SPIM_SR_RSVD_SR register field value. */
2661 #define ALT_SPIM_SR_RSVD_SR_SET_MSK 0xffffff80
2662 /* The mask used to clear the ALT_SPIM_SR_RSVD_SR register field value. */
2663 #define ALT_SPIM_SR_RSVD_SR_CLR_MSK 0x0000007f
2664 /* The reset value of the ALT_SPIM_SR_RSVD_SR register field. */
2665 #define ALT_SPIM_SR_RSVD_SR_RESET 0x0
2666 /* Extracts the ALT_SPIM_SR_RSVD_SR field value from a register. */
2667 #define ALT_SPIM_SR_RSVD_SR_GET(value) (((value) & 0xffffff80) >> 7)
2668 /* Produces a ALT_SPIM_SR_RSVD_SR register field value suitable for setting the register. */
2669 #define ALT_SPIM_SR_RSVD_SR_SET(value) (((value) << 7) & 0xffffff80)
2670 
2671 #ifndef __ASSEMBLY__
2672 /*
2673  * WARNING: The C register and register group struct declarations are provided for
2674  * convenience and illustrative purposes. They should, however, be used with
2675  * caution as the C language standard provides no guarantees about the alignment or
2676  * atomicity of device memory accesses. The recommended practice for coding device
2677  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2678  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2679  * alt_write_dword() functions for 64 bit registers.
2680  *
2681  * The struct declaration for register ALT_SPIM_SR.
2682  */
2683 struct ALT_SPIM_SR_s
2684 {
2685  const volatile uint32_t BUSY : 1; /* ALT_SPIM_SR_BUSY */
2686  const volatile uint32_t TFNF : 1; /* ALT_SPIM_SR_TFNF */
2687  const volatile uint32_t TFE : 1; /* ALT_SPIM_SR_TFE */
2688  const volatile uint32_t RFNE : 1; /* ALT_SPIM_SR_RFNE */
2689  const volatile uint32_t RFF : 1; /* ALT_SPIM_SR_RFF */
2690  const volatile uint32_t RSVD_TXE : 1; /* ALT_SPIM_SR_RSVD_TXE */
2691  const volatile uint32_t DCOL : 1; /* ALT_SPIM_SR_DCOL */
2692  const volatile uint32_t RSVD_SR : 25; /* ALT_SPIM_SR_RSVD_SR */
2693 };
2694 
2695 /* The typedef declaration for register ALT_SPIM_SR. */
2696 typedef struct ALT_SPIM_SR_s ALT_SPIM_SR_t;
2697 #endif /* __ASSEMBLY__ */
2698 
2699 /* The reset value of the ALT_SPIM_SR register. */
2700 #define ALT_SPIM_SR_RESET 0x00000006
2701 /* The byte offset of the ALT_SPIM_SR register from the beginning of the component. */
2702 #define ALT_SPIM_SR_OFST 0x28
2703 /* The address of the ALT_SPIM_SR register. */
2704 #define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
2705 
2706 /*
2707  * Register : Interrupt Mask Register - IMR
2708  *
2709  * Interrupt Mask Register
2710  *
2711  * Register Layout
2712  *
2713  * Bits | Access | Reset | Description
2714  * :-------|:-------|:------|:----------------------
2715  * [0] | RW | 0x1 | ALT_SPIM_IMR_TXEIM
2716  * [1] | RW | 0x1 | ALT_SPIM_IMR_TXOIM
2717  * [2] | RW | 0x1 | ALT_SPIM_IMR_RXUIM
2718  * [3] | RW | 0x1 | ALT_SPIM_IMR_RXOIM
2719  * [4] | RW | 0x1 | ALT_SPIM_IMR_RXFIM
2720  * [5] | RW | 0x1 | ALT_SPIM_IMR_MSTIM
2721  * [31:6] | R | 0x0 | ALT_SPIM_IMR_RSVD_IMR
2722  *
2723  */
2724 /*
2725  * Field : TXEIM
2726  *
2727  * Transmit FIFO Empty Interrupt Mask
2728  *
2729  * 0 - ssi_txe_intr interrupt is masked
2730  *
2731  * 1 - ssi_txe_intr interrupt is not masked
2732  *
2733  * Field Enumeration Values:
2734  *
2735  * Enum | Value | Description
2736  * :------------------------------|:------|:----------------------------------
2737  * ALT_SPIM_IMR_TXEIM_E_MASKED | 0x0 | TX FIFO Empty Interrupt is masked
2738  * ALT_SPIM_IMR_TXEIM_E_UNMASKED | 0x1 | TX FIFO Empty Interrupt un-masked
2739  *
2740  * Field Access Macros:
2741  *
2742  */
2743 /*
2744  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
2745  *
2746  * TX FIFO Empty Interrupt is masked
2747  */
2748 #define ALT_SPIM_IMR_TXEIM_E_MASKED 0x0
2749 /*
2750  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
2751  *
2752  * TX FIFO Empty Interrupt un-masked
2753  */
2754 #define ALT_SPIM_IMR_TXEIM_E_UNMASKED 0x1
2755 
2756 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXEIM register field. */
2757 #define ALT_SPIM_IMR_TXEIM_LSB 0
2758 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXEIM register field. */
2759 #define ALT_SPIM_IMR_TXEIM_MSB 0
2760 /* The width in bits of the ALT_SPIM_IMR_TXEIM register field. */
2761 #define ALT_SPIM_IMR_TXEIM_WIDTH 1
2762 /* The mask used to set the ALT_SPIM_IMR_TXEIM register field value. */
2763 #define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
2764 /* The mask used to clear the ALT_SPIM_IMR_TXEIM register field value. */
2765 #define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
2766 /* The reset value of the ALT_SPIM_IMR_TXEIM register field. */
2767 #define ALT_SPIM_IMR_TXEIM_RESET 0x1
2768 /* Extracts the ALT_SPIM_IMR_TXEIM field value from a register. */
2769 #define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2770 /* Produces a ALT_SPIM_IMR_TXEIM register field value suitable for setting the register. */
2771 #define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2772 
2773 /*
2774  * Field : TXOIM
2775  *
2776  * Transmit FIFO Overflow Interrupt Mask
2777  *
2778  * 0 - ssi_txo_intr interrupt is masked
2779  *
2780  * 1 - ssi_txo_intr interrupt is not masked
2781  *
2782  * Field Enumeration Values:
2783  *
2784  * Enum | Value | Description
2785  * :------------------------------|:------|:-------------------------------------
2786  * ALT_SPIM_IMR_TXOIM_E_MASKED | 0x0 | TX FIFO Overflow Interrupt is masked
2787  * ALT_SPIM_IMR_TXOIM_E_UNMASKED | 0x1 | TX FIFO Overflow Interrupt un-masked
2788  *
2789  * Field Access Macros:
2790  *
2791  */
2792 /*
2793  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
2794  *
2795  * TX FIFO Overflow Interrupt is masked
2796  */
2797 #define ALT_SPIM_IMR_TXOIM_E_MASKED 0x0
2798 /*
2799  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
2800  *
2801  * TX FIFO Overflow Interrupt un-masked
2802  */
2803 #define ALT_SPIM_IMR_TXOIM_E_UNMASKED 0x1
2804 
2805 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXOIM register field. */
2806 #define ALT_SPIM_IMR_TXOIM_LSB 1
2807 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXOIM register field. */
2808 #define ALT_SPIM_IMR_TXOIM_MSB 1
2809 /* The width in bits of the ALT_SPIM_IMR_TXOIM register field. */
2810 #define ALT_SPIM_IMR_TXOIM_WIDTH 1
2811 /* The mask used to set the ALT_SPIM_IMR_TXOIM register field value. */
2812 #define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
2813 /* The mask used to clear the ALT_SPIM_IMR_TXOIM register field value. */
2814 #define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
2815 /* The reset value of the ALT_SPIM_IMR_TXOIM register field. */
2816 #define ALT_SPIM_IMR_TXOIM_RESET 0x1
2817 /* Extracts the ALT_SPIM_IMR_TXOIM field value from a register. */
2818 #define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2819 /* Produces a ALT_SPIM_IMR_TXOIM register field value suitable for setting the register. */
2820 #define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2821 
2822 /*
2823  * Field : RXUIM
2824  *
2825  * Receive FIFO Underflow Interrupt Mask
2826  *
2827  * 0 - ssi_rxu_intr interrupt is masked
2828  *
2829  * 1 - ssi_rxu_intr interrupt is not masked
2830  *
2831  * Field Enumeration Values:
2832  *
2833  * Enum | Value | Description
2834  * :------------------------------|:------|:--------------------------------------
2835  * ALT_SPIM_IMR_RXUIM_E_MASKED | 0x0 | RX FIFO Underflow Interrupt is masked
2836  * ALT_SPIM_IMR_RXUIM_E_UNMASKED | 0x1 | RX FIFO Underflow Interrupt un-masked
2837  *
2838  * Field Access Macros:
2839  *
2840  */
2841 /*
2842  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
2843  *
2844  * RX FIFO Underflow Interrupt is masked
2845  */
2846 #define ALT_SPIM_IMR_RXUIM_E_MASKED 0x0
2847 /*
2848  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
2849  *
2850  * RX FIFO Underflow Interrupt un-masked
2851  */
2852 #define ALT_SPIM_IMR_RXUIM_E_UNMASKED 0x1
2853 
2854 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXUIM register field. */
2855 #define ALT_SPIM_IMR_RXUIM_LSB 2
2856 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXUIM register field. */
2857 #define ALT_SPIM_IMR_RXUIM_MSB 2
2858 /* The width in bits of the ALT_SPIM_IMR_RXUIM register field. */
2859 #define ALT_SPIM_IMR_RXUIM_WIDTH 1
2860 /* The mask used to set the ALT_SPIM_IMR_RXUIM register field value. */
2861 #define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
2862 /* The mask used to clear the ALT_SPIM_IMR_RXUIM register field value. */
2863 #define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
2864 /* The reset value of the ALT_SPIM_IMR_RXUIM register field. */
2865 #define ALT_SPIM_IMR_RXUIM_RESET 0x1
2866 /* Extracts the ALT_SPIM_IMR_RXUIM field value from a register. */
2867 #define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2868 /* Produces a ALT_SPIM_IMR_RXUIM register field value suitable for setting the register. */
2869 #define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2870 
2871 /*
2872  * Field : RXOIM
2873  *
2874  * Receive FIFO Overflow Interrupt Mask
2875  *
2876  * 0 - ssi_rxo_intr interrupt is masked
2877  *
2878  * 1 - ssi_rxo_intr interrupt is not masked
2879  *
2880  * Field Enumeration Values:
2881  *
2882  * Enum | Value | Description
2883  * :------------------------------|:------|:-------------------------------------
2884  * ALT_SPIM_IMR_RXOIM_E_MASKED | 0x0 | RX FIFO Overflow Interrupt is masked
2885  * ALT_SPIM_IMR_RXOIM_E_UNMASKED | 0x1 | RX FIFO Overflow Interrupt un-masked
2886  *
2887  * Field Access Macros:
2888  *
2889  */
2890 /*
2891  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
2892  *
2893  * RX FIFO Overflow Interrupt is masked
2894  */
2895 #define ALT_SPIM_IMR_RXOIM_E_MASKED 0x0
2896 /*
2897  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
2898  *
2899  * RX FIFO Overflow Interrupt un-masked
2900  */
2901 #define ALT_SPIM_IMR_RXOIM_E_UNMASKED 0x1
2902 
2903 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXOIM register field. */
2904 #define ALT_SPIM_IMR_RXOIM_LSB 3
2905 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXOIM register field. */
2906 #define ALT_SPIM_IMR_RXOIM_MSB 3
2907 /* The width in bits of the ALT_SPIM_IMR_RXOIM register field. */
2908 #define ALT_SPIM_IMR_RXOIM_WIDTH 1
2909 /* The mask used to set the ALT_SPIM_IMR_RXOIM register field value. */
2910 #define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
2911 /* The mask used to clear the ALT_SPIM_IMR_RXOIM register field value. */
2912 #define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
2913 /* The reset value of the ALT_SPIM_IMR_RXOIM register field. */
2914 #define ALT_SPIM_IMR_RXOIM_RESET 0x1
2915 /* Extracts the ALT_SPIM_IMR_RXOIM field value from a register. */
2916 #define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2917 /* Produces a ALT_SPIM_IMR_RXOIM register field value suitable for setting the register. */
2918 #define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2919 
2920 /*
2921  * Field : RXFIM
2922  *
2923  * Receive FIFO Full Interrupt Mask
2924  *
2925  * 0 - ssi_rxf_intr interrupt is masked
2926  *
2927  * 1 - ssi_rxf_intr interrupt is not masked
2928  *
2929  * Field Enumeration Values:
2930  *
2931  * Enum | Value | Description
2932  * :------------------------------|:------|:---------------------------------
2933  * ALT_SPIM_IMR_RXFIM_E_MASKED | 0x0 | RX FIFO Full Interrupt is masked
2934  * ALT_SPIM_IMR_RXFIM_E_UNMASKED | 0x1 | RX FIFO Full Interrupt un-masked
2935  *
2936  * Field Access Macros:
2937  *
2938  */
2939 /*
2940  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
2941  *
2942  * RX FIFO Full Interrupt is masked
2943  */
2944 #define ALT_SPIM_IMR_RXFIM_E_MASKED 0x0
2945 /*
2946  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
2947  *
2948  * RX FIFO Full Interrupt un-masked
2949  */
2950 #define ALT_SPIM_IMR_RXFIM_E_UNMASKED 0x1
2951 
2952 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXFIM register field. */
2953 #define ALT_SPIM_IMR_RXFIM_LSB 4
2954 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXFIM register field. */
2955 #define ALT_SPIM_IMR_RXFIM_MSB 4
2956 /* The width in bits of the ALT_SPIM_IMR_RXFIM register field. */
2957 #define ALT_SPIM_IMR_RXFIM_WIDTH 1
2958 /* The mask used to set the ALT_SPIM_IMR_RXFIM register field value. */
2959 #define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
2960 /* The mask used to clear the ALT_SPIM_IMR_RXFIM register field value. */
2961 #define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
2962 /* The reset value of the ALT_SPIM_IMR_RXFIM register field. */
2963 #define ALT_SPIM_IMR_RXFIM_RESET 0x1
2964 /* Extracts the ALT_SPIM_IMR_RXFIM field value from a register. */
2965 #define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2966 /* Produces a ALT_SPIM_IMR_RXFIM register field value suitable for setting the register. */
2967 #define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2968 
2969 /*
2970  * Field : MSTIM
2971  *
2972  * Multi-Master Contention Interrupt Mask. This bit field is not present if
2973  *
2974  * the DW_apb_ssi is configured as a serial-slave device.
2975  *
2976  * 0 - ssi_mst_intr interrupt is masked
2977  *
2978  * 1 - ssi_mst_intr interrupt is not masked
2979  *
2980  * Field Enumeration Values:
2981  *
2982  * Enum | Value | Description
2983  * :------------------------------|:------|:--------------------------------------------
2984  * ALT_SPIM_IMR_MSTIM_E_MASKED | 0x0 | Multi-Master Contention Interrupt is masked
2985  * ALT_SPIM_IMR_MSTIM_E_UNMASKED | 0x1 | Multi-Master Contention Interrupt un-masked
2986  *
2987  * Field Access Macros:
2988  *
2989  */
2990 /*
2991  * Enumerated value for register field ALT_SPIM_IMR_MSTIM
2992  *
2993  * Multi-Master Contention Interrupt is masked
2994  */
2995 #define ALT_SPIM_IMR_MSTIM_E_MASKED 0x0
2996 /*
2997  * Enumerated value for register field ALT_SPIM_IMR_MSTIM
2998  *
2999  * Multi-Master Contention Interrupt un-masked
3000  */
3001 #define ALT_SPIM_IMR_MSTIM_E_UNMASKED 0x1
3002 
3003 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_MSTIM register field. */
3004 #define ALT_SPIM_IMR_MSTIM_LSB 5
3005 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_MSTIM register field. */
3006 #define ALT_SPIM_IMR_MSTIM_MSB 5
3007 /* The width in bits of the ALT_SPIM_IMR_MSTIM register field. */
3008 #define ALT_SPIM_IMR_MSTIM_WIDTH 1
3009 /* The mask used to set the ALT_SPIM_IMR_MSTIM register field value. */
3010 #define ALT_SPIM_IMR_MSTIM_SET_MSK 0x00000020
3011 /* The mask used to clear the ALT_SPIM_IMR_MSTIM register field value. */
3012 #define ALT_SPIM_IMR_MSTIM_CLR_MSK 0xffffffdf
3013 /* The reset value of the ALT_SPIM_IMR_MSTIM register field. */
3014 #define ALT_SPIM_IMR_MSTIM_RESET 0x1
3015 /* Extracts the ALT_SPIM_IMR_MSTIM field value from a register. */
3016 #define ALT_SPIM_IMR_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
3017 /* Produces a ALT_SPIM_IMR_MSTIM register field value suitable for setting the register. */
3018 #define ALT_SPIM_IMR_MSTIM_SET(value) (((value) << 5) & 0x00000020)
3019 
3020 /*
3021  * Field : RSVD_IMR
3022  *
3023  * Reserved bits - Read Only
3024  *
3025  * Field Access Macros:
3026  *
3027  */
3028 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RSVD_IMR register field. */
3029 #define ALT_SPIM_IMR_RSVD_IMR_LSB 6
3030 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RSVD_IMR register field. */
3031 #define ALT_SPIM_IMR_RSVD_IMR_MSB 31
3032 /* The width in bits of the ALT_SPIM_IMR_RSVD_IMR register field. */
3033 #define ALT_SPIM_IMR_RSVD_IMR_WIDTH 26
3034 /* The mask used to set the ALT_SPIM_IMR_RSVD_IMR register field value. */
3035 #define ALT_SPIM_IMR_RSVD_IMR_SET_MSK 0xffffffc0
3036 /* The mask used to clear the ALT_SPIM_IMR_RSVD_IMR register field value. */
3037 #define ALT_SPIM_IMR_RSVD_IMR_CLR_MSK 0x0000003f
3038 /* The reset value of the ALT_SPIM_IMR_RSVD_IMR register field. */
3039 #define ALT_SPIM_IMR_RSVD_IMR_RESET 0x0
3040 /* Extracts the ALT_SPIM_IMR_RSVD_IMR field value from a register. */
3041 #define ALT_SPIM_IMR_RSVD_IMR_GET(value) (((value) & 0xffffffc0) >> 6)
3042 /* Produces a ALT_SPIM_IMR_RSVD_IMR register field value suitable for setting the register. */
3043 #define ALT_SPIM_IMR_RSVD_IMR_SET(value) (((value) << 6) & 0xffffffc0)
3044 
3045 #ifndef __ASSEMBLY__
3046 /*
3047  * WARNING: The C register and register group struct declarations are provided for
3048  * convenience and illustrative purposes. They should, however, be used with
3049  * caution as the C language standard provides no guarantees about the alignment or
3050  * atomicity of device memory accesses. The recommended practice for coding device
3051  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3052  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3053  * alt_write_dword() functions for 64 bit registers.
3054  *
3055  * The struct declaration for register ALT_SPIM_IMR.
3056  */
3057 struct ALT_SPIM_IMR_s
3058 {
3059  volatile uint32_t TXEIM : 1; /* ALT_SPIM_IMR_TXEIM */
3060  volatile uint32_t TXOIM : 1; /* ALT_SPIM_IMR_TXOIM */
3061  volatile uint32_t RXUIM : 1; /* ALT_SPIM_IMR_RXUIM */
3062  volatile uint32_t RXOIM : 1; /* ALT_SPIM_IMR_RXOIM */
3063  volatile uint32_t RXFIM : 1; /* ALT_SPIM_IMR_RXFIM */
3064  volatile uint32_t MSTIM : 1; /* ALT_SPIM_IMR_MSTIM */
3065  const volatile uint32_t RSVD_IMR : 26; /* ALT_SPIM_IMR_RSVD_IMR */
3066 };
3067 
3068 /* The typedef declaration for register ALT_SPIM_IMR. */
3069 typedef struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t;
3070 #endif /* __ASSEMBLY__ */
3071 
3072 /* The reset value of the ALT_SPIM_IMR register. */
3073 #define ALT_SPIM_IMR_RESET 0x0000003f
3074 /* The byte offset of the ALT_SPIM_IMR register from the beginning of the component. */
3075 #define ALT_SPIM_IMR_OFST 0x2c
3076 /* The address of the ALT_SPIM_IMR register. */
3077 #define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
3078 
3079 /*
3080  * Register : Interrupt Status Register - ISR
3081  *
3082  * Interrupt Status Register
3083  *
3084  * Register Layout
3085  *
3086  * Bits | Access | Reset | Description
3087  * :-------|:-------|:------|:----------------------
3088  * [0] | R | 0x0 | ALT_SPIM_ISR_TXEIS
3089  * [1] | R | 0x0 | ALT_SPIM_ISR_TXOIS
3090  * [2] | R | 0x0 | ALT_SPIM_ISR_RXUIS
3091  * [3] | R | 0x0 | ALT_SPIM_ISR_RXOIS
3092  * [4] | R | 0x0 | ALT_SPIM_ISR_RXFIS
3093  * [5] | R | 0x0 | ALT_SPIM_ISR_MSTIS
3094  * [31:6] | R | 0x0 | ALT_SPIM_ISR_RSVD_ISR
3095  *
3096  */
3097 /*
3098  * Field : TXEIS
3099  *
3100  * Transmit FIFO Empty Interrupt Status
3101  *
3102  * 0 = ssi_txe_intr interrupt is not active after masking
3103  *
3104  * 1 = ssi_txe_intr interrupt is active after masking
3105  *
3106  * Field Enumeration Values:
3107  *
3108  * Enum | Value | Description
3109  * :------------------------------|:------|:----------------------------------
3110  * ALT_SPIM_ISR_TXEIS_E_INACTIVE | 0x0 | TX FIFO Empty Interrupt nonactive
3111  * ALT_SPIM_ISR_TXEIS_E_ACTIVE | 0x1 | TX FIFO Empty Interrupt is active
3112  *
3113  * Field Access Macros:
3114  *
3115  */
3116 /*
3117  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
3118  *
3119  * TX FIFO Empty Interrupt nonactive
3120  */
3121 #define ALT_SPIM_ISR_TXEIS_E_INACTIVE 0x0
3122 /*
3123  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
3124  *
3125  * TX FIFO Empty Interrupt is active
3126  */
3127 #define ALT_SPIM_ISR_TXEIS_E_ACTIVE 0x1
3128 
3129 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXEIS register field. */
3130 #define ALT_SPIM_ISR_TXEIS_LSB 0
3131 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXEIS register field. */
3132 #define ALT_SPIM_ISR_TXEIS_MSB 0
3133 /* The width in bits of the ALT_SPIM_ISR_TXEIS register field. */
3134 #define ALT_SPIM_ISR_TXEIS_WIDTH 1
3135 /* The mask used to set the ALT_SPIM_ISR_TXEIS register field value. */
3136 #define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
3137 /* The mask used to clear the ALT_SPIM_ISR_TXEIS register field value. */
3138 #define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
3139 /* The reset value of the ALT_SPIM_ISR_TXEIS register field. */
3140 #define ALT_SPIM_ISR_TXEIS_RESET 0x0
3141 /* Extracts the ALT_SPIM_ISR_TXEIS field value from a register. */
3142 #define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
3143 /* Produces a ALT_SPIM_ISR_TXEIS register field value suitable for setting the register. */
3144 #define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
3145 
3146 /*
3147  * Field : TXOIS
3148  *
3149  * Transmit FIFO Overflow Interrupt Status
3150  *
3151  * 0 = ssi_txo_intr interrupt is not active after masking
3152  *
3153  * 1 = ssi_txo_intr interrupt is active after masking
3154  *
3155  * Field Enumeration Values:
3156  *
3157  * Enum | Value | Description
3158  * :------------------------------|:------|:-------------------------------------
3159  * ALT_SPIM_ISR_TXOIS_E_INACTIVE | 0x0 | TX FIFO Overflow Interrupt nonactive
3160  * ALT_SPIM_ISR_TXOIS_E_ACTIVE | 0x1 | TX FIFO Overflow Interrupt is active
3161  *
3162  * Field Access Macros:
3163  *
3164  */
3165 /*
3166  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
3167  *
3168  * TX FIFO Overflow Interrupt nonactive
3169  */
3170 #define ALT_SPIM_ISR_TXOIS_E_INACTIVE 0x0
3171 /*
3172  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
3173  *
3174  * TX FIFO Overflow Interrupt is active
3175  */
3176 #define ALT_SPIM_ISR_TXOIS_E_ACTIVE 0x1
3177 
3178 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXOIS register field. */
3179 #define ALT_SPIM_ISR_TXOIS_LSB 1
3180 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXOIS register field. */
3181 #define ALT_SPIM_ISR_TXOIS_MSB 1
3182 /* The width in bits of the ALT_SPIM_ISR_TXOIS register field. */
3183 #define ALT_SPIM_ISR_TXOIS_WIDTH 1
3184 /* The mask used to set the ALT_SPIM_ISR_TXOIS register field value. */
3185 #define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
3186 /* The mask used to clear the ALT_SPIM_ISR_TXOIS register field value. */
3187 #define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
3188 /* The reset value of the ALT_SPIM_ISR_TXOIS register field. */
3189 #define ALT_SPIM_ISR_TXOIS_RESET 0x0
3190 /* Extracts the ALT_SPIM_ISR_TXOIS field value from a register. */
3191 #define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
3192 /* Produces a ALT_SPIM_ISR_TXOIS register field value suitable for setting the register. */
3193 #define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
3194 
3195 /*
3196  * Field : RXUIS
3197  *
3198  * Receive FIFO Underflow Interrupt Status
3199  *
3200  * 0 = ssi_rxu_intr interrupt is not active after masking
3201  *
3202  * 1 = ssi_rxu_intr interrupt is active after masking
3203  *
3204  * Field Enumeration Values:
3205  *
3206  * Enum | Value | Description
3207  * :------------------------------|:------|:--------------------------------------
3208  * ALT_SPIM_ISR_RXUIS_E_INACTIVE | 0x0 | RX FIFO Underflow Interrupt nonactive
3209  * ALT_SPIM_ISR_RXUIS_E_ACTIVE | 0x1 | RX FIFO underflow Interrupt is active
3210  *
3211  * Field Access Macros:
3212  *
3213  */
3214 /*
3215  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
3216  *
3217  * RX FIFO Underflow Interrupt nonactive
3218  */
3219 #define ALT_SPIM_ISR_RXUIS_E_INACTIVE 0x0
3220 /*
3221  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
3222  *
3223  * RX FIFO underflow Interrupt is active
3224  */
3225 #define ALT_SPIM_ISR_RXUIS_E_ACTIVE 0x1
3226 
3227 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXUIS register field. */
3228 #define ALT_SPIM_ISR_RXUIS_LSB 2
3229 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXUIS register field. */
3230 #define ALT_SPIM_ISR_RXUIS_MSB 2
3231 /* The width in bits of the ALT_SPIM_ISR_RXUIS register field. */
3232 #define ALT_SPIM_ISR_RXUIS_WIDTH 1
3233 /* The mask used to set the ALT_SPIM_ISR_RXUIS register field value. */
3234 #define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
3235 /* The mask used to clear the ALT_SPIM_ISR_RXUIS register field value. */
3236 #define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
3237 /* The reset value of the ALT_SPIM_ISR_RXUIS register field. */
3238 #define ALT_SPIM_ISR_RXUIS_RESET 0x0
3239 /* Extracts the ALT_SPIM_ISR_RXUIS field value from a register. */
3240 #define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
3241 /* Produces a ALT_SPIM_ISR_RXUIS register field value suitable for setting the register. */
3242 #define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
3243 
3244 /*
3245  * Field : RXOIS
3246  *
3247  * Receive FIFO Overflow Interrupt Status
3248  *
3249  * 0 = ssi_rxo_intr interrupt is not active after masking
3250  *
3251  * 1 = ssi_rxo_intr interrupt is active after masking
3252  *
3253  * Field Enumeration Values:
3254  *
3255  * Enum | Value | Description
3256  * :------------------------------|:------|:-------------------------------------
3257  * ALT_SPIM_ISR_RXOIS_E_INACTIVE | 0x0 | RX FIFO Overflow Interrupt nonactive
3258  * ALT_SPIM_ISR_RXOIS_E_ACTIVE | 0x1 | RX FIFO Overflow Interrupt is active
3259  *
3260  * Field Access Macros:
3261  *
3262  */
3263 /*
3264  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
3265  *
3266  * RX FIFO Overflow Interrupt nonactive
3267  */
3268 #define ALT_SPIM_ISR_RXOIS_E_INACTIVE 0x0
3269 /*
3270  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
3271  *
3272  * RX FIFO Overflow Interrupt is active
3273  */
3274 #define ALT_SPIM_ISR_RXOIS_E_ACTIVE 0x1
3275 
3276 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXOIS register field. */
3277 #define ALT_SPIM_ISR_RXOIS_LSB 3
3278 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXOIS register field. */
3279 #define ALT_SPIM_ISR_RXOIS_MSB 3
3280 /* The width in bits of the ALT_SPIM_ISR_RXOIS register field. */
3281 #define ALT_SPIM_ISR_RXOIS_WIDTH 1
3282 /* The mask used to set the ALT_SPIM_ISR_RXOIS register field value. */
3283 #define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
3284 /* The mask used to clear the ALT_SPIM_ISR_RXOIS register field value. */
3285 #define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
3286 /* The reset value of the ALT_SPIM_ISR_RXOIS register field. */
3287 #define ALT_SPIM_ISR_RXOIS_RESET 0x0
3288 /* Extracts the ALT_SPIM_ISR_RXOIS field value from a register. */
3289 #define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
3290 /* Produces a ALT_SPIM_ISR_RXOIS register field value suitable for setting the register. */
3291 #define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
3292 
3293 /*
3294  * Field : RXFIS
3295  *
3296  * Receive FIFO Full Interrupt Status
3297  *
3298  * 0 = ssi_rxf_intr interrupt is not active after masking
3299  *
3300  * 1 = ssi_rxf_intr interrupt is full after masking
3301  *
3302  * Field Enumeration Values:
3303  *
3304  * Enum | Value | Description
3305  * :------------------------------|:------|:---------------------------------
3306  * ALT_SPIM_ISR_RXFIS_E_INACTIVE | 0x0 | RX FIFO Full Interrupt nonactive
3307  * ALT_SPIM_ISR_RXFIS_E_ACTIVE | 0x1 | RX FIFO Full Interrupt is active
3308  *
3309  * Field Access Macros:
3310  *
3311  */
3312 /*
3313  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
3314  *
3315  * RX FIFO Full Interrupt nonactive
3316  */
3317 #define ALT_SPIM_ISR_RXFIS_E_INACTIVE 0x0
3318 /*
3319  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
3320  *
3321  * RX FIFO Full Interrupt is active
3322  */
3323 #define ALT_SPIM_ISR_RXFIS_E_ACTIVE 0x1
3324 
3325 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXFIS register field. */
3326 #define ALT_SPIM_ISR_RXFIS_LSB 4
3327 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXFIS register field. */
3328 #define ALT_SPIM_ISR_RXFIS_MSB 4
3329 /* The width in bits of the ALT_SPIM_ISR_RXFIS register field. */
3330 #define ALT_SPIM_ISR_RXFIS_WIDTH 1
3331 /* The mask used to set the ALT_SPIM_ISR_RXFIS register field value. */
3332 #define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
3333 /* The mask used to clear the ALT_SPIM_ISR_RXFIS register field value. */
3334 #define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
3335 /* The reset value of the ALT_SPIM_ISR_RXFIS register field. */
3336 #define ALT_SPIM_ISR_RXFIS_RESET 0x0
3337 /* Extracts the ALT_SPIM_ISR_RXFIS field value from a register. */
3338 #define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
3339 /* Produces a ALT_SPIM_ISR_RXFIS register field value suitable for setting the register. */
3340 #define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
3341 
3342 /*
3343  * Field : MSTIS
3344  *
3345  * Multi-Master Contention Interrupt Status. This bit field is not present
3346  *
3347  * if the DW_apb_ssi is configured as a serial-slave device.
3348  *
3349  * 0 = ssi_mst_intr interrupt not active after masking
3350  *
3351  * 1 = ssi_mst_intr interrupt is active after masking
3352  *
3353  * Field Enumeration Values:
3354  *
3355  * Enum | Value | Description
3356  * :------------------------------|:------|:--------------------------------------------
3357  * ALT_SPIM_ISR_MSTIS_E_INACTIVE | 0x0 | Multi-master Contention Interrupt nonactive
3358  * ALT_SPIM_ISR_MSTIS_E_ACTIVE | 0x1 | Multi-master Contention Interrupt is active
3359  *
3360  * Field Access Macros:
3361  *
3362  */
3363 /*
3364  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
3365  *
3366  * Multi-master Contention Interrupt nonactive
3367  */
3368 #define ALT_SPIM_ISR_MSTIS_E_INACTIVE 0x0
3369 /*
3370  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
3371  *
3372  * Multi-master Contention Interrupt is active
3373  */
3374 #define ALT_SPIM_ISR_MSTIS_E_ACTIVE 0x1
3375 
3376 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_MSTIS register field. */
3377 #define ALT_SPIM_ISR_MSTIS_LSB 5
3378 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_MSTIS register field. */
3379 #define ALT_SPIM_ISR_MSTIS_MSB 5
3380 /* The width in bits of the ALT_SPIM_ISR_MSTIS register field. */
3381 #define ALT_SPIM_ISR_MSTIS_WIDTH 1
3382 /* The mask used to set the ALT_SPIM_ISR_MSTIS register field value. */
3383 #define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
3384 /* The mask used to clear the ALT_SPIM_ISR_MSTIS register field value. */
3385 #define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
3386 /* The reset value of the ALT_SPIM_ISR_MSTIS register field. */
3387 #define ALT_SPIM_ISR_MSTIS_RESET 0x0
3388 /* Extracts the ALT_SPIM_ISR_MSTIS field value from a register. */
3389 #define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
3390 /* Produces a ALT_SPIM_ISR_MSTIS register field value suitable for setting the register. */
3391 #define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
3392 
3393 /*
3394  * Field : RSVD_ISR
3395  *
3396  * Reserved bits - Read Only
3397  *
3398  * Field Access Macros:
3399  *
3400  */
3401 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RSVD_ISR register field. */
3402 #define ALT_SPIM_ISR_RSVD_ISR_LSB 6
3403 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RSVD_ISR register field. */
3404 #define ALT_SPIM_ISR_RSVD_ISR_MSB 31
3405 /* The width in bits of the ALT_SPIM_ISR_RSVD_ISR register field. */
3406 #define ALT_SPIM_ISR_RSVD_ISR_WIDTH 26
3407 /* The mask used to set the ALT_SPIM_ISR_RSVD_ISR register field value. */
3408 #define ALT_SPIM_ISR_RSVD_ISR_SET_MSK 0xffffffc0
3409 /* The mask used to clear the ALT_SPIM_ISR_RSVD_ISR register field value. */
3410 #define ALT_SPIM_ISR_RSVD_ISR_CLR_MSK 0x0000003f
3411 /* The reset value of the ALT_SPIM_ISR_RSVD_ISR register field. */
3412 #define ALT_SPIM_ISR_RSVD_ISR_RESET 0x0
3413 /* Extracts the ALT_SPIM_ISR_RSVD_ISR field value from a register. */
3414 #define ALT_SPIM_ISR_RSVD_ISR_GET(value) (((value) & 0xffffffc0) >> 6)
3415 /* Produces a ALT_SPIM_ISR_RSVD_ISR register field value suitable for setting the register. */
3416 #define ALT_SPIM_ISR_RSVD_ISR_SET(value) (((value) << 6) & 0xffffffc0)
3417 
3418 #ifndef __ASSEMBLY__
3419 /*
3420  * WARNING: The C register and register group struct declarations are provided for
3421  * convenience and illustrative purposes. They should, however, be used with
3422  * caution as the C language standard provides no guarantees about the alignment or
3423  * atomicity of device memory accesses. The recommended practice for coding device
3424  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3425  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3426  * alt_write_dword() functions for 64 bit registers.
3427  *
3428  * The struct declaration for register ALT_SPIM_ISR.
3429  */
3430 struct ALT_SPIM_ISR_s
3431 {
3432  const volatile uint32_t TXEIS : 1; /* ALT_SPIM_ISR_TXEIS */
3433  const volatile uint32_t TXOIS : 1; /* ALT_SPIM_ISR_TXOIS */
3434  const volatile uint32_t RXUIS : 1; /* ALT_SPIM_ISR_RXUIS */
3435  const volatile uint32_t RXOIS : 1; /* ALT_SPIM_ISR_RXOIS */
3436  const volatile uint32_t RXFIS : 1; /* ALT_SPIM_ISR_RXFIS */
3437  const volatile uint32_t MSTIS : 1; /* ALT_SPIM_ISR_MSTIS */
3438  const volatile uint32_t RSVD_ISR : 26; /* ALT_SPIM_ISR_RSVD_ISR */
3439 };
3440 
3441 /* The typedef declaration for register ALT_SPIM_ISR. */
3442 typedef struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t;
3443 #endif /* __ASSEMBLY__ */
3444 
3445 /* The reset value of the ALT_SPIM_ISR register. */
3446 #define ALT_SPIM_ISR_RESET 0x00000000
3447 /* The byte offset of the ALT_SPIM_ISR register from the beginning of the component. */
3448 #define ALT_SPIM_ISR_OFST 0x30
3449 /* The address of the ALT_SPIM_ISR register. */
3450 #define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
3451 
3452 /*
3453  * Register : Raw Interrupt Status Register - RISR
3454  *
3455  * Raw Interrupt Status Register
3456  *
3457  * Register Layout
3458  *
3459  * Bits | Access | Reset | Description
3460  * :-------|:-------|:------|:------------------------
3461  * [0] | R | 0x0 | ALT_SPIM_RISR_TXEIR
3462  * [1] | R | 0x0 | ALT_SPIM_RISR_TXOIR
3463  * [2] | R | 0x0 | ALT_SPIM_RISR_RXUIR
3464  * [3] | R | 0x0 | ALT_SPIM_RISR_RXOIR
3465  * [4] | R | 0x0 | ALT_SPIM_RISR_RXFIR
3466  * [5] | R | 0x0 | ALT_SPIM_RISR_MSTIR
3467  * [31:6] | R | 0x0 | ALT_SPIM_RISR_RSVD_RISR
3468  *
3469  */
3470 /*
3471  * Field : TXEIR
3472  *
3473  * Transmit FIFO Empty Raw Interrupt Status
3474  *
3475  * 0 = ssi_txe_intr interrupt is not active prior to masking
3476  *
3477  * 1 = ssi_txe_intr interrupt is active prior masking
3478  *
3479  * Field Enumeration Values:
3480  *
3481  * Enum | Value | Description
3482  * :-------------------------------|:------|:--------------------------------------
3483  * ALT_SPIM_RISR_TXEIR_E_INACTIVE | 0x0 | Raw TX FIFO Empty Interrupt nonactive
3484  * ALT_SPIM_RISR_TXEIR_E_ACTIVE | 0x1 | Raw TX FIFO Empty Interrupt is active
3485  *
3486  * Field Access Macros:
3487  *
3488  */
3489 /*
3490  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
3491  *
3492  * Raw TX FIFO Empty Interrupt nonactive
3493  */
3494 #define ALT_SPIM_RISR_TXEIR_E_INACTIVE 0x0
3495 /*
3496  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
3497  *
3498  * Raw TX FIFO Empty Interrupt is active
3499  */
3500 #define ALT_SPIM_RISR_TXEIR_E_ACTIVE 0x1
3501 
3502 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXEIR register field. */
3503 #define ALT_SPIM_RISR_TXEIR_LSB 0
3504 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXEIR register field. */
3505 #define ALT_SPIM_RISR_TXEIR_MSB 0
3506 /* The width in bits of the ALT_SPIM_RISR_TXEIR register field. */
3507 #define ALT_SPIM_RISR_TXEIR_WIDTH 1
3508 /* The mask used to set the ALT_SPIM_RISR_TXEIR register field value. */
3509 #define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
3510 /* The mask used to clear the ALT_SPIM_RISR_TXEIR register field value. */
3511 #define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
3512 /* The reset value of the ALT_SPIM_RISR_TXEIR register field. */
3513 #define ALT_SPIM_RISR_TXEIR_RESET 0x0
3514 /* Extracts the ALT_SPIM_RISR_TXEIR field value from a register. */
3515 #define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
3516 /* Produces a ALT_SPIM_RISR_TXEIR register field value suitable for setting the register. */
3517 #define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
3518 
3519 /*
3520  * Field : TXOIR
3521  *
3522  * Transmit FIFO Overflow Raw Interrupt Status
3523  *
3524  * 0 = ssi_txo_intr interrupt is not active prior to masking
3525  *
3526  * 1 = ssi_txo_intr interrupt is active prior masking
3527  *
3528  * Field Enumeration Values:
3529  *
3530  * Enum | Value | Description
3531  * :-------------------------------|:------|:-----------------------------------------
3532  * ALT_SPIM_RISR_TXOIR_E_INACTIVE | 0x0 | Raw TX FIFO Overflow Interrupt nonactive
3533  * ALT_SPIM_RISR_TXOIR_E_ACTIVE | 0x1 | Raw TX FIFO Overflow Interrupt is active
3534  *
3535  * Field Access Macros:
3536  *
3537  */
3538 /*
3539  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
3540  *
3541  * Raw TX FIFO Overflow Interrupt nonactive
3542  */
3543 #define ALT_SPIM_RISR_TXOIR_E_INACTIVE 0x0
3544 /*
3545  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
3546  *
3547  * Raw TX FIFO Overflow Interrupt is active
3548  */
3549 #define ALT_SPIM_RISR_TXOIR_E_ACTIVE 0x1
3550 
3551 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXOIR register field. */
3552 #define ALT_SPIM_RISR_TXOIR_LSB 1
3553 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXOIR register field. */
3554 #define ALT_SPIM_RISR_TXOIR_MSB 1
3555 /* The width in bits of the ALT_SPIM_RISR_TXOIR register field. */
3556 #define ALT_SPIM_RISR_TXOIR_WIDTH 1
3557 /* The mask used to set the ALT_SPIM_RISR_TXOIR register field value. */
3558 #define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
3559 /* The mask used to clear the ALT_SPIM_RISR_TXOIR register field value. */
3560 #define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
3561 /* The reset value of the ALT_SPIM_RISR_TXOIR register field. */
3562 #define ALT_SPIM_RISR_TXOIR_RESET 0x0
3563 /* Extracts the ALT_SPIM_RISR_TXOIR field value from a register. */
3564 #define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
3565 /* Produces a ALT_SPIM_RISR_TXOIR register field value suitable for setting the register. */
3566 #define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
3567 
3568 /*
3569  * Field : RXUIR
3570  *
3571  * Receive FIFO Underflow Raw Interrupt Status
3572  *
3573  * 0 = ssi_rxu_intr interrupt is not active prior to masking
3574  *
3575  * 1 = ssi_rxu_intr interrupt is active prior to masking
3576  *
3577  * Field Enumeration Values:
3578  *
3579  * Enum | Value | Description
3580  * :-------------------------------|:------|:------------------------------------------
3581  * ALT_SPIM_RISR_RXUIR_E_INACTIVE | 0x0 | Raw RX FIFO Underflow Interrupt nonactive
3582  * ALT_SPIM_RISR_RXUIR_E_ACTIVE | 0x1 | Raw RX FIFO underflow Interrupt is active
3583  *
3584  * Field Access Macros:
3585  *
3586  */
3587 /*
3588  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
3589  *
3590  * Raw RX FIFO Underflow Interrupt nonactive
3591  */
3592 #define ALT_SPIM_RISR_RXUIR_E_INACTIVE 0x0
3593 /*
3594  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
3595  *
3596  * Raw RX FIFO underflow Interrupt is active
3597  */
3598 #define ALT_SPIM_RISR_RXUIR_E_ACTIVE 0x1
3599 
3600 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXUIR register field. */
3601 #define ALT_SPIM_RISR_RXUIR_LSB 2
3602 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXUIR register field. */
3603 #define ALT_SPIM_RISR_RXUIR_MSB 2
3604 /* The width in bits of the ALT_SPIM_RISR_RXUIR register field. */
3605 #define ALT_SPIM_RISR_RXUIR_WIDTH 1
3606 /* The mask used to set the ALT_SPIM_RISR_RXUIR register field value. */
3607 #define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
3608 /* The mask used to clear the ALT_SPIM_RISR_RXUIR register field value. */
3609 #define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
3610 /* The reset value of the ALT_SPIM_RISR_RXUIR register field. */
3611 #define ALT_SPIM_RISR_RXUIR_RESET 0x0
3612 /* Extracts the ALT_SPIM_RISR_RXUIR field value from a register. */
3613 #define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
3614 /* Produces a ALT_SPIM_RISR_RXUIR register field value suitable for setting the register. */
3615 #define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
3616 
3617 /*
3618  * Field : RXOIR
3619  *
3620  * Receive FIFO Overflow Raw Interrupt Status
3621  *
3622  * 0 = ssi_rxo_intr interrupt is not active prior to masking
3623  *
3624  * 1 = ssi_rxo_intr interrupt is active prior masking
3625  *
3626  * Field Enumeration Values:
3627  *
3628  * Enum | Value | Description
3629  * :-------------------------------|:------|:-----------------------------------------
3630  * ALT_SPIM_RISR_RXOIR_E_INACTIVE | 0x0 | Raw RX FIFO Overflow Interrupt nonactive
3631  * ALT_SPIM_RISR_RXOIR_E_ACTIVE | 0x1 | Raw RX FIFO Overflow Interrupt is active
3632  *
3633  * Field Access Macros:
3634  *
3635  */
3636 /*
3637  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
3638  *
3639  * Raw RX FIFO Overflow Interrupt nonactive
3640  */
3641 #define ALT_SPIM_RISR_RXOIR_E_INACTIVE 0x0
3642 /*
3643  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
3644  *
3645  * Raw RX FIFO Overflow Interrupt is active
3646  */
3647 #define ALT_SPIM_RISR_RXOIR_E_ACTIVE 0x1
3648 
3649 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXOIR register field. */
3650 #define ALT_SPIM_RISR_RXOIR_LSB 3
3651 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXOIR register field. */
3652 #define ALT_SPIM_RISR_RXOIR_MSB 3
3653 /* The width in bits of the ALT_SPIM_RISR_RXOIR register field. */
3654 #define ALT_SPIM_RISR_RXOIR_WIDTH 1
3655 /* The mask used to set the ALT_SPIM_RISR_RXOIR register field value. */
3656 #define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
3657 /* The mask used to clear the ALT_SPIM_RISR_RXOIR register field value. */
3658 #define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
3659 /* The reset value of the ALT_SPIM_RISR_RXOIR register field. */
3660 #define ALT_SPIM_RISR_RXOIR_RESET 0x0
3661 /* Extracts the ALT_SPIM_RISR_RXOIR field value from a register. */
3662 #define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
3663 /* Produces a ALT_SPIM_RISR_RXOIR register field value suitable for setting the register. */
3664 #define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
3665 
3666 /*
3667  * Field : RXFIR
3668  *
3669  * Receive FIFO Full Raw Interrupt Status
3670  *
3671  * 0 = ssi_rxf_intr interrupt is not active prior to masking
3672  *
3673  * 1 = ssi_rxf_intr interrupt is active prior to masking
3674  *
3675  * Field Enumeration Values:
3676  *
3677  * Enum | Value | Description
3678  * :-------------------------------|:------|:-------------------------------------
3679  * ALT_SPIM_RISR_RXFIR_E_INACTIVE | 0x0 | Raw RX FIFO Full Interrupt nonactive
3680  * ALT_SPIM_RISR_RXFIR_E_ACTIVE | 0x1 | Raw RX FIFO Full Interrupt is active
3681  *
3682  * Field Access Macros:
3683  *
3684  */
3685 /*
3686  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
3687  *
3688  * Raw RX FIFO Full Interrupt nonactive
3689  */
3690 #define ALT_SPIM_RISR_RXFIR_E_INACTIVE 0x0
3691 /*
3692  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
3693  *
3694  * Raw RX FIFO Full Interrupt is active
3695  */
3696 #define ALT_SPIM_RISR_RXFIR_E_ACTIVE 0x1
3697 
3698 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXFIR register field. */
3699 #define ALT_SPIM_RISR_RXFIR_LSB 4
3700 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXFIR register field. */
3701 #define ALT_SPIM_RISR_RXFIR_MSB 4
3702 /* The width in bits of the ALT_SPIM_RISR_RXFIR register field. */
3703 #define ALT_SPIM_RISR_RXFIR_WIDTH 1
3704 /* The mask used to set the ALT_SPIM_RISR_RXFIR register field value. */
3705 #define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
3706 /* The mask used to clear the ALT_SPIM_RISR_RXFIR register field value. */
3707 #define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
3708 /* The reset value of the ALT_SPIM_RISR_RXFIR register field. */
3709 #define ALT_SPIM_RISR_RXFIR_RESET 0x0
3710 /* Extracts the ALT_SPIM_RISR_RXFIR field value from a register. */
3711 #define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
3712 /* Produces a ALT_SPIM_RISR_RXFIR register field value suitable for setting the register. */
3713 #define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
3714 
3715 /*
3716  * Field : MSTIR
3717  *
3718  * Multi-Master Contention Raw Interrupt Status.
3719  *
3720  * This bit field is not present if the DW_apb_ssi is configured as a
3721  *
3722  * serial-slave device.
3723  *
3724  * 0 = ssi_mst_intr interrupt is not active prior to masking
3725  *
3726  * 1 = ssi_mst_intr interrupt is active prior masking
3727  *
3728  * Field Enumeration Values:
3729  *
3730  * Enum | Value | Description
3731  * :-------------------------------|:------|:------------------------------------------------
3732  * ALT_SPIM_RISR_MSTIR_E_INACTIVE | 0x0 | Raw Multi-master Contention Interrupt nonactive
3733  * ALT_SPIM_RISR_MSTIR_E_ACTIVE | 0x1 | Raw Multi-master Contention Interrupt is active
3734  *
3735  * Field Access Macros:
3736  *
3737  */
3738 /*
3739  * Enumerated value for register field ALT_SPIM_RISR_MSTIR
3740  *
3741  * Raw Multi-master Contention Interrupt nonactive
3742  */
3743 #define ALT_SPIM_RISR_MSTIR_E_INACTIVE 0x0
3744 /*
3745  * Enumerated value for register field ALT_SPIM_RISR_MSTIR
3746  *
3747  * Raw Multi-master Contention Interrupt is active
3748  */
3749 #define ALT_SPIM_RISR_MSTIR_E_ACTIVE 0x1
3750 
3751 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_MSTIR register field. */
3752 #define ALT_SPIM_RISR_MSTIR_LSB 5
3753 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_MSTIR register field. */
3754 #define ALT_SPIM_RISR_MSTIR_MSB 5
3755 /* The width in bits of the ALT_SPIM_RISR_MSTIR register field. */
3756 #define ALT_SPIM_RISR_MSTIR_WIDTH 1
3757 /* The mask used to set the ALT_SPIM_RISR_MSTIR register field value. */
3758 #define ALT_SPIM_RISR_MSTIR_SET_MSK 0x00000020
3759 /* The mask used to clear the ALT_SPIM_RISR_MSTIR register field value. */
3760 #define ALT_SPIM_RISR_MSTIR_CLR_MSK 0xffffffdf
3761 /* The reset value of the ALT_SPIM_RISR_MSTIR register field. */
3762 #define ALT_SPIM_RISR_MSTIR_RESET 0x0
3763 /* Extracts the ALT_SPIM_RISR_MSTIR field value from a register. */
3764 #define ALT_SPIM_RISR_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
3765 /* Produces a ALT_SPIM_RISR_MSTIR register field value suitable for setting the register. */
3766 #define ALT_SPIM_RISR_MSTIR_SET(value) (((value) << 5) & 0x00000020)
3767 
3768 /*
3769  * Field : RSVD_RISR
3770  *
3771  * Reserved bits - Read Only
3772  *
3773  * Field Access Macros:
3774  *
3775  */
3776 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RSVD_RISR register field. */
3777 #define ALT_SPIM_RISR_RSVD_RISR_LSB 6
3778 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RSVD_RISR register field. */
3779 #define ALT_SPIM_RISR_RSVD_RISR_MSB 31
3780 /* The width in bits of the ALT_SPIM_RISR_RSVD_RISR register field. */
3781 #define ALT_SPIM_RISR_RSVD_RISR_WIDTH 26
3782 /* The mask used to set the ALT_SPIM_RISR_RSVD_RISR register field value. */
3783 #define ALT_SPIM_RISR_RSVD_RISR_SET_MSK 0xffffffc0
3784 /* The mask used to clear the ALT_SPIM_RISR_RSVD_RISR register field value. */
3785 #define ALT_SPIM_RISR_RSVD_RISR_CLR_MSK 0x0000003f
3786 /* The reset value of the ALT_SPIM_RISR_RSVD_RISR register field. */
3787 #define ALT_SPIM_RISR_RSVD_RISR_RESET 0x0
3788 /* Extracts the ALT_SPIM_RISR_RSVD_RISR field value from a register. */
3789 #define ALT_SPIM_RISR_RSVD_RISR_GET(value) (((value) & 0xffffffc0) >> 6)
3790 /* Produces a ALT_SPIM_RISR_RSVD_RISR register field value suitable for setting the register. */
3791 #define ALT_SPIM_RISR_RSVD_RISR_SET(value) (((value) << 6) & 0xffffffc0)
3792 
3793 #ifndef __ASSEMBLY__
3794 /*
3795  * WARNING: The C register and register group struct declarations are provided for
3796  * convenience and illustrative purposes. They should, however, be used with
3797  * caution as the C language standard provides no guarantees about the alignment or
3798  * atomicity of device memory accesses. The recommended practice for coding device
3799  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3800  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3801  * alt_write_dword() functions for 64 bit registers.
3802  *
3803  * The struct declaration for register ALT_SPIM_RISR.
3804  */
3805 struct ALT_SPIM_RISR_s
3806 {
3807  const volatile uint32_t TXEIR : 1; /* ALT_SPIM_RISR_TXEIR */
3808  const volatile uint32_t TXOIR : 1; /* ALT_SPIM_RISR_TXOIR */
3809  const volatile uint32_t RXUIR : 1; /* ALT_SPIM_RISR_RXUIR */
3810  const volatile uint32_t RXOIR : 1; /* ALT_SPIM_RISR_RXOIR */
3811  const volatile uint32_t RXFIR : 1; /* ALT_SPIM_RISR_RXFIR */
3812  const volatile uint32_t MSTIR : 1; /* ALT_SPIM_RISR_MSTIR */
3813  const volatile uint32_t RSVD_RISR : 26; /* ALT_SPIM_RISR_RSVD_RISR */
3814 };
3815 
3816 /* The typedef declaration for register ALT_SPIM_RISR. */
3817 typedef struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t;
3818 #endif /* __ASSEMBLY__ */
3819 
3820 /* The reset value of the ALT_SPIM_RISR register. */
3821 #define ALT_SPIM_RISR_RESET 0x00000000
3822 /* The byte offset of the ALT_SPIM_RISR register from the beginning of the component. */
3823 #define ALT_SPIM_RISR_OFST 0x34
3824 /* The address of the ALT_SPIM_RISR register. */
3825 #define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
3826 
3827 /*
3828  * Register : Transmit FIFO Overflow Interrupt Clear Register Register - TXOICR
3829  *
3830  * Transmit FIFO Overflow Interrupt Clear Register
3831  *
3832  * Register Layout
3833  *
3834  * Bits | Access | Reset | Description
3835  * :-------|:-------|:------|:----------------------------
3836  * [0] | R | 0x0 | ALT_SPIM_TXOICR_TXOICR
3837  * [31:1] | R | 0x0 | ALT_SPIM_TXOICR_RSVD_TXOICR
3838  *
3839  */
3840 /*
3841  * Field : TXOICR
3842  *
3843  * Clear Transmit FIFO Overflow Interrupt.
3844  *
3845  * This register reflects the status of the interrupt. A read from this
3846  *
3847  * register clears the ssi_txo_intr interrupt; writing has no effect.
3848  *
3849  * Field Access Macros:
3850  *
3851  */
3852 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
3853 #define ALT_SPIM_TXOICR_TXOICR_LSB 0
3854 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
3855 #define ALT_SPIM_TXOICR_TXOICR_MSB 0
3856 /* The width in bits of the ALT_SPIM_TXOICR_TXOICR register field. */
3857 #define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
3858 /* The mask used to set the ALT_SPIM_TXOICR_TXOICR register field value. */
3859 #define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
3860 /* The mask used to clear the ALT_SPIM_TXOICR_TXOICR register field value. */
3861 #define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3862 /* The reset value of the ALT_SPIM_TXOICR_TXOICR register field. */
3863 #define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
3864 /* Extracts the ALT_SPIM_TXOICR_TXOICR field value from a register. */
3865 #define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3866 /* Produces a ALT_SPIM_TXOICR_TXOICR register field value suitable for setting the register. */
3867 #define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3868 
3869 /*
3870  * Field : RSVD_TXOICR
3871  *
3872  * Reserved bits - Read Only
3873  *
3874  * Field Access Macros:
3875  *
3876  */
3877 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXOICR_RSVD_TXOICR register field. */
3878 #define ALT_SPIM_TXOICR_RSVD_TXOICR_LSB 1
3879 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXOICR_RSVD_TXOICR register field. */
3880 #define ALT_SPIM_TXOICR_RSVD_TXOICR_MSB 31
3881 /* The width in bits of the ALT_SPIM_TXOICR_RSVD_TXOICR register field. */
3882 #define ALT_SPIM_TXOICR_RSVD_TXOICR_WIDTH 31
3883 /* The mask used to set the ALT_SPIM_TXOICR_RSVD_TXOICR register field value. */
3884 #define ALT_SPIM_TXOICR_RSVD_TXOICR_SET_MSK 0xfffffffe
3885 /* The mask used to clear the ALT_SPIM_TXOICR_RSVD_TXOICR register field value. */
3886 #define ALT_SPIM_TXOICR_RSVD_TXOICR_CLR_MSK 0x00000001
3887 /* The reset value of the ALT_SPIM_TXOICR_RSVD_TXOICR register field. */
3888 #define ALT_SPIM_TXOICR_RSVD_TXOICR_RESET 0x0
3889 /* Extracts the ALT_SPIM_TXOICR_RSVD_TXOICR field value from a register. */
3890 #define ALT_SPIM_TXOICR_RSVD_TXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3891 /* Produces a ALT_SPIM_TXOICR_RSVD_TXOICR register field value suitable for setting the register. */
3892 #define ALT_SPIM_TXOICR_RSVD_TXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3893 
3894 #ifndef __ASSEMBLY__
3895 /*
3896  * WARNING: The C register and register group struct declarations are provided for
3897  * convenience and illustrative purposes. They should, however, be used with
3898  * caution as the C language standard provides no guarantees about the alignment or
3899  * atomicity of device memory accesses. The recommended practice for coding device
3900  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3901  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3902  * alt_write_dword() functions for 64 bit registers.
3903  *
3904  * The struct declaration for register ALT_SPIM_TXOICR.
3905  */
3906 struct ALT_SPIM_TXOICR_s
3907 {
3908  const volatile uint32_t TXOICR : 1; /* ALT_SPIM_TXOICR_TXOICR */
3909  const volatile uint32_t RSVD_TXOICR : 31; /* ALT_SPIM_TXOICR_RSVD_TXOICR */
3910 };
3911 
3912 /* The typedef declaration for register ALT_SPIM_TXOICR. */
3913 typedef struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t;
3914 #endif /* __ASSEMBLY__ */
3915 
3916 /* The reset value of the ALT_SPIM_TXOICR register. */
3917 #define ALT_SPIM_TXOICR_RESET 0x00000000
3918 /* The byte offset of the ALT_SPIM_TXOICR register from the beginning of the component. */
3919 #define ALT_SPIM_TXOICR_OFST 0x38
3920 /* The address of the ALT_SPIM_TXOICR register. */
3921 #define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
3922 
3923 /*
3924  * Register : Receive FIFO Overflow Interrupt Clear Register - RXOICR
3925  *
3926  * Receive FIFO Overflow Interrupt Clear Register
3927  *
3928  * Register Layout
3929  *
3930  * Bits | Access | Reset | Description
3931  * :-------|:-------|:------|:----------------------------
3932  * [0] | R | 0x0 | ALT_SPIM_RXOICR_RXOICR
3933  * [31:1] | R | 0x0 | ALT_SPIM_RXOICR_RSVD_RXOICR
3934  *
3935  */
3936 /*
3937  * Field : RXOICR
3938  *
3939  * Clear Receive FIFO Overflow Interrupt.
3940  *
3941  * This register reflects the status of the interrupt. A read from this
3942  *
3943  * register clears the ssi_rxo_intr interrupt; writing has no effect.
3944  *
3945  * Field Access Macros:
3946  *
3947  */
3948 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
3949 #define ALT_SPIM_RXOICR_RXOICR_LSB 0
3950 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
3951 #define ALT_SPIM_RXOICR_RXOICR_MSB 0
3952 /* The width in bits of the ALT_SPIM_RXOICR_RXOICR register field. */
3953 #define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
3954 /* The mask used to set the ALT_SPIM_RXOICR_RXOICR register field value. */
3955 #define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
3956 /* The mask used to clear the ALT_SPIM_RXOICR_RXOICR register field value. */
3957 #define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3958 /* The reset value of the ALT_SPIM_RXOICR_RXOICR register field. */
3959 #define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
3960 /* Extracts the ALT_SPIM_RXOICR_RXOICR field value from a register. */
3961 #define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3962 /* Produces a ALT_SPIM_RXOICR_RXOICR register field value suitable for setting the register. */
3963 #define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3964 
3965 /*
3966  * Field : RSVD_RXOICR
3967  *
3968  * Reserved bits - Read Only
3969  *
3970  * Field Access Macros:
3971  *
3972  */
3973 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXOICR_RSVD_RXOICR register field. */
3974 #define ALT_SPIM_RXOICR_RSVD_RXOICR_LSB 1
3975 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXOICR_RSVD_RXOICR register field. */
3976 #define ALT_SPIM_RXOICR_RSVD_RXOICR_MSB 31
3977 /* The width in bits of the ALT_SPIM_RXOICR_RSVD_RXOICR register field. */
3978 #define ALT_SPIM_RXOICR_RSVD_RXOICR_WIDTH 31
3979 /* The mask used to set the ALT_SPIM_RXOICR_RSVD_RXOICR register field value. */
3980 #define ALT_SPIM_RXOICR_RSVD_RXOICR_SET_MSK 0xfffffffe
3981 /* The mask used to clear the ALT_SPIM_RXOICR_RSVD_RXOICR register field value. */
3982 #define ALT_SPIM_RXOICR_RSVD_RXOICR_CLR_MSK 0x00000001
3983 /* The reset value of the ALT_SPIM_RXOICR_RSVD_RXOICR register field. */
3984 #define ALT_SPIM_RXOICR_RSVD_RXOICR_RESET 0x0
3985 /* Extracts the ALT_SPIM_RXOICR_RSVD_RXOICR field value from a register. */
3986 #define ALT_SPIM_RXOICR_RSVD_RXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3987 /* Produces a ALT_SPIM_RXOICR_RSVD_RXOICR register field value suitable for setting the register. */
3988 #define ALT_SPIM_RXOICR_RSVD_RXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3989 
3990 #ifndef __ASSEMBLY__
3991 /*
3992  * WARNING: The C register and register group struct declarations are provided for
3993  * convenience and illustrative purposes. They should, however, be used with
3994  * caution as the C language standard provides no guarantees about the alignment or
3995  * atomicity of device memory accesses. The recommended practice for coding device
3996  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3997  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3998  * alt_write_dword() functions for 64 bit registers.
3999  *
4000  * The struct declaration for register ALT_SPIM_RXOICR.
4001  */
4002 struct ALT_SPIM_RXOICR_s
4003 {
4004  const volatile uint32_t RXOICR : 1; /* ALT_SPIM_RXOICR_RXOICR */
4005  const volatile uint32_t RSVD_RXOICR : 31; /* ALT_SPIM_RXOICR_RSVD_RXOICR */
4006 };
4007 
4008 /* The typedef declaration for register ALT_SPIM_RXOICR. */
4009 typedef struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t;
4010 #endif /* __ASSEMBLY__ */
4011 
4012 /* The reset value of the ALT_SPIM_RXOICR register. */
4013 #define ALT_SPIM_RXOICR_RESET 0x00000000
4014 /* The byte offset of the ALT_SPIM_RXOICR register from the beginning of the component. */
4015 #define ALT_SPIM_RXOICR_OFST 0x3c
4016 /* The address of the ALT_SPIM_RXOICR register. */
4017 #define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
4018 
4019 /*
4020  * Register : Receive FIFO Underflow Interrupt Clear Register - RXUICR
4021  *
4022  * Receive FIFO Underflow Interrupt Clear Register
4023  *
4024  * Register Layout
4025  *
4026  * Bits | Access | Reset | Description
4027  * :-------|:-------|:------|:----------------------------
4028  * [0] | R | 0x0 | ALT_SPIM_RXUICR_RXUICR
4029  * [31:1] | R | 0x0 | ALT_SPIM_RXUICR_RSVD_RXUICR
4030  *
4031  */
4032 /*
4033  * Field : RXUICR
4034  *
4035  * Clear Receive FIFO Underflow Interrupt.
4036  *
4037  * This register reflects the status of the interrupt. A read from this
4038  *
4039  * register clears the ssi_rxu_intr interrupt; writing has no effect.
4040  *
4041  * Field Access Macros:
4042  *
4043  */
4044 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
4045 #define ALT_SPIM_RXUICR_RXUICR_LSB 0
4046 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
4047 #define ALT_SPIM_RXUICR_RXUICR_MSB 0
4048 /* The width in bits of the ALT_SPIM_RXUICR_RXUICR register field. */
4049 #define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
4050 /* The mask used to set the ALT_SPIM_RXUICR_RXUICR register field value. */
4051 #define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
4052 /* The mask used to clear the ALT_SPIM_RXUICR_RXUICR register field value. */
4053 #define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
4054 /* The reset value of the ALT_SPIM_RXUICR_RXUICR register field. */
4055 #define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
4056 /* Extracts the ALT_SPIM_RXUICR_RXUICR field value from a register. */
4057 #define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
4058 /* Produces a ALT_SPIM_RXUICR_RXUICR register field value suitable for setting the register. */
4059 #define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
4060 
4061 /*
4062  * Field : RSVD_RXUICR
4063  *
4064  * Reserved bits - Read Only
4065  *
4066  * Field Access Macros:
4067  *
4068  */
4069 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXUICR_RSVD_RXUICR register field. */
4070 #define ALT_SPIM_RXUICR_RSVD_RXUICR_LSB 1
4071 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXUICR_RSVD_RXUICR register field. */
4072 #define ALT_SPIM_RXUICR_RSVD_RXUICR_MSB 31
4073 /* The width in bits of the ALT_SPIM_RXUICR_RSVD_RXUICR register field. */
4074 #define ALT_SPIM_RXUICR_RSVD_RXUICR_WIDTH 31
4075 /* The mask used to set the ALT_SPIM_RXUICR_RSVD_RXUICR register field value. */
4076 #define ALT_SPIM_RXUICR_RSVD_RXUICR_SET_MSK 0xfffffffe
4077 /* The mask used to clear the ALT_SPIM_RXUICR_RSVD_RXUICR register field value. */
4078 #define ALT_SPIM_RXUICR_RSVD_RXUICR_CLR_MSK 0x00000001
4079 /* The reset value of the ALT_SPIM_RXUICR_RSVD_RXUICR register field. */
4080 #define ALT_SPIM_RXUICR_RSVD_RXUICR_RESET 0x0
4081 /* Extracts the ALT_SPIM_RXUICR_RSVD_RXUICR field value from a register. */
4082 #define ALT_SPIM_RXUICR_RSVD_RXUICR_GET(value) (((value) & 0xfffffffe) >> 1)
4083 /* Produces a ALT_SPIM_RXUICR_RSVD_RXUICR register field value suitable for setting the register. */
4084 #define ALT_SPIM_RXUICR_RSVD_RXUICR_SET(value) (((value) << 1) & 0xfffffffe)
4085 
4086 #ifndef __ASSEMBLY__
4087 /*
4088  * WARNING: The C register and register group struct declarations are provided for
4089  * convenience and illustrative purposes. They should, however, be used with
4090  * caution as the C language standard provides no guarantees about the alignment or
4091  * atomicity of device memory accesses. The recommended practice for coding device
4092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4094  * alt_write_dword() functions for 64 bit registers.
4095  *
4096  * The struct declaration for register ALT_SPIM_RXUICR.
4097  */
4098 struct ALT_SPIM_RXUICR_s
4099 {
4100  const volatile uint32_t RXUICR : 1; /* ALT_SPIM_RXUICR_RXUICR */
4101  const volatile uint32_t RSVD_RXUICR : 31; /* ALT_SPIM_RXUICR_RSVD_RXUICR */
4102 };
4103 
4104 /* The typedef declaration for register ALT_SPIM_RXUICR. */
4105 typedef struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t;
4106 #endif /* __ASSEMBLY__ */
4107 
4108 /* The reset value of the ALT_SPIM_RXUICR register. */
4109 #define ALT_SPIM_RXUICR_RESET 0x00000000
4110 /* The byte offset of the ALT_SPIM_RXUICR register from the beginning of the component. */
4111 #define ALT_SPIM_RXUICR_OFST 0x40
4112 /* The address of the ALT_SPIM_RXUICR register. */
4113 #define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
4114 
4115 /*
4116  * Register : Multi-Master Interrupt Clear Register - MSTICR
4117  *
4118  * Multi-Master Interrupt Clear Register
4119  *
4120  * Register Layout
4121  *
4122  * Bits | Access | Reset | Description
4123  * :-------|:-------|:------|:----------------------------
4124  * [0] | R | 0x0 | ALT_SPIM_MSTICR_MSTICR
4125  * [31:1] | R | 0x0 | ALT_SPIM_MSTICR_RSVD_MSTICR
4126  *
4127  */
4128 /*
4129  * Field : MSTICR
4130  *
4131  * Clear Multi-Master Contention Interrupt.
4132  *
4133  * This register reflects the status of the interrupt. A read from this
4134  *
4135  * register clears the ssi_mst_intr interrupt; writing has no effect.
4136  *
4137  * Field Access Macros:
4138  *
4139  */
4140 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MSTICR_MSTICR register field. */
4141 #define ALT_SPIM_MSTICR_MSTICR_LSB 0
4142 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MSTICR_MSTICR register field. */
4143 #define ALT_SPIM_MSTICR_MSTICR_MSB 0
4144 /* The width in bits of the ALT_SPIM_MSTICR_MSTICR register field. */
4145 #define ALT_SPIM_MSTICR_MSTICR_WIDTH 1
4146 /* The mask used to set the ALT_SPIM_MSTICR_MSTICR register field value. */
4147 #define ALT_SPIM_MSTICR_MSTICR_SET_MSK 0x00000001
4148 /* The mask used to clear the ALT_SPIM_MSTICR_MSTICR register field value. */
4149 #define ALT_SPIM_MSTICR_MSTICR_CLR_MSK 0xfffffffe
4150 /* The reset value of the ALT_SPIM_MSTICR_MSTICR register field. */
4151 #define ALT_SPIM_MSTICR_MSTICR_RESET 0x0
4152 /* Extracts the ALT_SPIM_MSTICR_MSTICR field value from a register. */
4153 #define ALT_SPIM_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
4154 /* Produces a ALT_SPIM_MSTICR_MSTICR register field value suitable for setting the register. */
4155 #define ALT_SPIM_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
4156 
4157 /*
4158  * Field : RSVD_MSTICR
4159  *
4160  * Reserved bits - Read Only
4161  *
4162  * Field Access Macros:
4163  *
4164  */
4165 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MSTICR_RSVD_MSTICR register field. */
4166 #define ALT_SPIM_MSTICR_RSVD_MSTICR_LSB 1
4167 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MSTICR_RSVD_MSTICR register field. */
4168 #define ALT_SPIM_MSTICR_RSVD_MSTICR_MSB 31
4169 /* The width in bits of the ALT_SPIM_MSTICR_RSVD_MSTICR register field. */
4170 #define ALT_SPIM_MSTICR_RSVD_MSTICR_WIDTH 31
4171 /* The mask used to set the ALT_SPIM_MSTICR_RSVD_MSTICR register field value. */
4172 #define ALT_SPIM_MSTICR_RSVD_MSTICR_SET_MSK 0xfffffffe
4173 /* The mask used to clear the ALT_SPIM_MSTICR_RSVD_MSTICR register field value. */
4174 #define ALT_SPIM_MSTICR_RSVD_MSTICR_CLR_MSK 0x00000001
4175 /* The reset value of the ALT_SPIM_MSTICR_RSVD_MSTICR register field. */
4176 #define ALT_SPIM_MSTICR_RSVD_MSTICR_RESET 0x0
4177 /* Extracts the ALT_SPIM_MSTICR_RSVD_MSTICR field value from a register. */
4178 #define ALT_SPIM_MSTICR_RSVD_MSTICR_GET(value) (((value) & 0xfffffffe) >> 1)
4179 /* Produces a ALT_SPIM_MSTICR_RSVD_MSTICR register field value suitable for setting the register. */
4180 #define ALT_SPIM_MSTICR_RSVD_MSTICR_SET(value) (((value) << 1) & 0xfffffffe)
4181 
4182 #ifndef __ASSEMBLY__
4183 /*
4184  * WARNING: The C register and register group struct declarations are provided for
4185  * convenience and illustrative purposes. They should, however, be used with
4186  * caution as the C language standard provides no guarantees about the alignment or
4187  * atomicity of device memory accesses. The recommended practice for coding device
4188  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4189  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4190  * alt_write_dword() functions for 64 bit registers.
4191  *
4192  * The struct declaration for register ALT_SPIM_MSTICR.
4193  */
4194 struct ALT_SPIM_MSTICR_s
4195 {
4196  const volatile uint32_t MSTICR : 1; /* ALT_SPIM_MSTICR_MSTICR */
4197  const volatile uint32_t RSVD_MSTICR : 31; /* ALT_SPIM_MSTICR_RSVD_MSTICR */
4198 };
4199 
4200 /* The typedef declaration for register ALT_SPIM_MSTICR. */
4201 typedef struct ALT_SPIM_MSTICR_s ALT_SPIM_MSTICR_t;
4202 #endif /* __ASSEMBLY__ */
4203 
4204 /* The reset value of the ALT_SPIM_MSTICR register. */
4205 #define ALT_SPIM_MSTICR_RESET 0x00000000
4206 /* The byte offset of the ALT_SPIM_MSTICR register from the beginning of the component. */
4207 #define ALT_SPIM_MSTICR_OFST 0x44
4208 /* The address of the ALT_SPIM_MSTICR register. */
4209 #define ALT_SPIM_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MSTICR_OFST))
4210 
4211 /*
4212  * Register : Interrupt Clear Register - ICR
4213  *
4214  * Interrupt Clear Register
4215  *
4216  * Register Layout
4217  *
4218  * Bits | Access | Reset | Description
4219  * :-------|:-------|:------|:----------------------
4220  * [0] | R | 0x0 | ALT_SPIM_ICR_ICR
4221  * [31:1] | R | 0x0 | ALT_SPIM_ICR_RSVD_ICR
4222  *
4223  */
4224 /*
4225  * Field : ICR
4226  *
4227  * Clear Interrupts.
4228  *
4229  * This register is set if any of the interrupts below are active. A read
4230  *
4231  * clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr
4232  *
4233  * interrupts. Writing to this register has no effect.
4234  *
4235  * Field Access Macros:
4236  *
4237  */
4238 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ICR_ICR register field. */
4239 #define ALT_SPIM_ICR_ICR_LSB 0
4240 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ICR_ICR register field. */
4241 #define ALT_SPIM_ICR_ICR_MSB 0
4242 /* The width in bits of the ALT_SPIM_ICR_ICR register field. */
4243 #define ALT_SPIM_ICR_ICR_WIDTH 1
4244 /* The mask used to set the ALT_SPIM_ICR_ICR register field value. */
4245 #define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
4246 /* The mask used to clear the ALT_SPIM_ICR_ICR register field value. */
4247 #define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
4248 /* The reset value of the ALT_SPIM_ICR_ICR register field. */
4249 #define ALT_SPIM_ICR_ICR_RESET 0x0
4250 /* Extracts the ALT_SPIM_ICR_ICR field value from a register. */
4251 #define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
4252 /* Produces a ALT_SPIM_ICR_ICR register field value suitable for setting the register. */
4253 #define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
4254 
4255 /*
4256  * Field : RSVD_ICR
4257  *
4258  * Reserved bits - Read Only
4259  *
4260  * Field Access Macros:
4261  *
4262  */
4263 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ICR_RSVD_ICR register field. */
4264 #define ALT_SPIM_ICR_RSVD_ICR_LSB 1
4265 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ICR_RSVD_ICR register field. */
4266 #define ALT_SPIM_ICR_RSVD_ICR_MSB 31
4267 /* The width in bits of the ALT_SPIM_ICR_RSVD_ICR register field. */
4268 #define ALT_SPIM_ICR_RSVD_ICR_WIDTH 31
4269 /* The mask used to set the ALT_SPIM_ICR_RSVD_ICR register field value. */
4270 #define ALT_SPIM_ICR_RSVD_ICR_SET_MSK 0xfffffffe
4271 /* The mask used to clear the ALT_SPIM_ICR_RSVD_ICR register field value. */
4272 #define ALT_SPIM_ICR_RSVD_ICR_CLR_MSK 0x00000001
4273 /* The reset value of the ALT_SPIM_ICR_RSVD_ICR register field. */
4274 #define ALT_SPIM_ICR_RSVD_ICR_RESET 0x0
4275 /* Extracts the ALT_SPIM_ICR_RSVD_ICR field value from a register. */
4276 #define ALT_SPIM_ICR_RSVD_ICR_GET(value) (((value) & 0xfffffffe) >> 1)
4277 /* Produces a ALT_SPIM_ICR_RSVD_ICR register field value suitable for setting the register. */
4278 #define ALT_SPIM_ICR_RSVD_ICR_SET(value) (((value) << 1) & 0xfffffffe)
4279 
4280 #ifndef __ASSEMBLY__
4281 /*
4282  * WARNING: The C register and register group struct declarations are provided for
4283  * convenience and illustrative purposes. They should, however, be used with
4284  * caution as the C language standard provides no guarantees about the alignment or
4285  * atomicity of device memory accesses. The recommended practice for coding device
4286  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4287  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4288  * alt_write_dword() functions for 64 bit registers.
4289  *
4290  * The struct declaration for register ALT_SPIM_ICR.
4291  */
4292 struct ALT_SPIM_ICR_s
4293 {
4294  const volatile uint32_t ICR : 1; /* ALT_SPIM_ICR_ICR */
4295  const volatile uint32_t RSVD_ICR : 31; /* ALT_SPIM_ICR_RSVD_ICR */
4296 };
4297 
4298 /* The typedef declaration for register ALT_SPIM_ICR. */
4299 typedef struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t;
4300 #endif /* __ASSEMBLY__ */
4301 
4302 /* The reset value of the ALT_SPIM_ICR register. */
4303 #define ALT_SPIM_ICR_RESET 0x00000000
4304 /* The byte offset of the ALT_SPIM_ICR register from the beginning of the component. */
4305 #define ALT_SPIM_ICR_OFST 0x48
4306 /* The address of the ALT_SPIM_ICR register. */
4307 #define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
4308 
4309 /*
4310  * Register : DMA Control Register - DMACR
4311  *
4312  * DMA Control Register.
4313  *
4314  * This register is only valid when DW_apb_ssi is configured with a set of
4315  *
4316  * DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
4317  *
4318  * not configured for DMA operation, this register will not exist and writing
4319  *
4320  * to the register's address will have no effect; reading from this register
4321  *
4322  * address will return zero. The register is used to enable the DMA
4323  *
4324  * Controller interface operation.
4325  *
4326  * Register Layout
4327  *
4328  * Bits | Access | Reset | Description
4329  * :-------|:-------|:------|:--------------------------
4330  * [0] | RW | 0x0 | ALT_SPIM_DMACR_RDMAE
4331  * [1] | RW | 0x0 | ALT_SPIM_DMACR_TDMAE
4332  * [31:2] | R | 0x0 | ALT_SPIM_DMACR_RSVD_DMACR
4333  *
4334  */
4335 /*
4336  * Field : RDMAE
4337  *
4338  * Receive DMA Enable.
4339  *
4340  * This bit enables/disables the receive FIFO DMA channel
4341  *
4342  * 0 = Receive DMA disabled
4343  *
4344  * 1 = Receive DMA enabled
4345  *
4346  * Field Enumeration Values:
4347  *
4348  * Enum | Value | Description
4349  * :-------------------------------|:------|:----------------------
4350  * ALT_SPIM_DMACR_RDMAE_E_DISABLE | 0x0 | Recieve DMA Disabled
4351  * ALT_SPIM_DMACR_RDMAE_E_ENABLED | 0x1 | Recieve DMA Enabled
4352  *
4353  * Field Access Macros:
4354  *
4355  */
4356 /*
4357  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
4358  *
4359  * Recieve DMA Disabled
4360  */
4361 #define ALT_SPIM_DMACR_RDMAE_E_DISABLE 0x0
4362 /*
4363  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
4364  *
4365  * Recieve DMA Enabled
4366  */
4367 #define ALT_SPIM_DMACR_RDMAE_E_ENABLED 0x1
4368 
4369 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
4370 #define ALT_SPIM_DMACR_RDMAE_LSB 0
4371 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
4372 #define ALT_SPIM_DMACR_RDMAE_MSB 0
4373 /* The width in bits of the ALT_SPIM_DMACR_RDMAE register field. */
4374 #define ALT_SPIM_DMACR_RDMAE_WIDTH 1
4375 /* The mask used to set the ALT_SPIM_DMACR_RDMAE register field value. */
4376 #define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
4377 /* The mask used to clear the ALT_SPIM_DMACR_RDMAE register field value. */
4378 #define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
4379 /* The reset value of the ALT_SPIM_DMACR_RDMAE register field. */
4380 #define ALT_SPIM_DMACR_RDMAE_RESET 0x0
4381 /* Extracts the ALT_SPIM_DMACR_RDMAE field value from a register. */
4382 #define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
4383 /* Produces a ALT_SPIM_DMACR_RDMAE register field value suitable for setting the register. */
4384 #define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
4385 
4386 /*
4387  * Field : TDMAE
4388  *
4389  * Transmit DMA Enable.
4390  *
4391  * This bit enables/disables the transmit FIFO DMA channel.
4392  *
4393  * 0 = Transmit DMA disabled
4394  *
4395  * 1 = Transmit DMA enabled
4396  *
4397  * Field Enumeration Values:
4398  *
4399  * Enum | Value | Description
4400  * :-------------------------------|:------|:-----------------------
4401  * ALT_SPIM_DMACR_TDMAE_E_DISABLE | 0x0 | Transmit DMA Disabled
4402  * ALT_SPIM_DMACR_TDMAE_E_ENABLED | 0x1 | Transmit DMA Enabled
4403  *
4404  * Field Access Macros:
4405  *
4406  */
4407 /*
4408  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
4409  *
4410  * Transmit DMA Disabled
4411  */
4412 #define ALT_SPIM_DMACR_TDMAE_E_DISABLE 0x0
4413 /*
4414  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
4415  *
4416  * Transmit DMA Enabled
4417  */
4418 #define ALT_SPIM_DMACR_TDMAE_E_ENABLED 0x1
4419 
4420 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
4421 #define ALT_SPIM_DMACR_TDMAE_LSB 1
4422 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
4423 #define ALT_SPIM_DMACR_TDMAE_MSB 1
4424 /* The width in bits of the ALT_SPIM_DMACR_TDMAE register field. */
4425 #define ALT_SPIM_DMACR_TDMAE_WIDTH 1
4426 /* The mask used to set the ALT_SPIM_DMACR_TDMAE register field value. */
4427 #define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
4428 /* The mask used to clear the ALT_SPIM_DMACR_TDMAE register field value. */
4429 #define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
4430 /* The reset value of the ALT_SPIM_DMACR_TDMAE register field. */
4431 #define ALT_SPIM_DMACR_TDMAE_RESET 0x0
4432 /* Extracts the ALT_SPIM_DMACR_TDMAE field value from a register. */
4433 #define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
4434 /* Produces a ALT_SPIM_DMACR_TDMAE register field value suitable for setting the register. */
4435 #define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
4436 
4437 /*
4438  * Field : RSVD_DMACR
4439  *
4440  * Reserved bits - Read Only
4441  *
4442  * Field Access Macros:
4443  *
4444  */
4445 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_RSVD_DMACR register field. */
4446 #define ALT_SPIM_DMACR_RSVD_DMACR_LSB 2
4447 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_RSVD_DMACR register field. */
4448 #define ALT_SPIM_DMACR_RSVD_DMACR_MSB 31
4449 /* The width in bits of the ALT_SPIM_DMACR_RSVD_DMACR register field. */
4450 #define ALT_SPIM_DMACR_RSVD_DMACR_WIDTH 30
4451 /* The mask used to set the ALT_SPIM_DMACR_RSVD_DMACR register field value. */
4452 #define ALT_SPIM_DMACR_RSVD_DMACR_SET_MSK 0xfffffffc
4453 /* The mask used to clear the ALT_SPIM_DMACR_RSVD_DMACR register field value. */
4454 #define ALT_SPIM_DMACR_RSVD_DMACR_CLR_MSK 0x00000003
4455 /* The reset value of the ALT_SPIM_DMACR_RSVD_DMACR register field. */
4456 #define ALT_SPIM_DMACR_RSVD_DMACR_RESET 0x0
4457 /* Extracts the ALT_SPIM_DMACR_RSVD_DMACR field value from a register. */
4458 #define ALT_SPIM_DMACR_RSVD_DMACR_GET(value) (((value) & 0xfffffffc) >> 2)
4459 /* Produces a ALT_SPIM_DMACR_RSVD_DMACR register field value suitable for setting the register. */
4460 #define ALT_SPIM_DMACR_RSVD_DMACR_SET(value) (((value) << 2) & 0xfffffffc)
4461 
4462 #ifndef __ASSEMBLY__
4463 /*
4464  * WARNING: The C register and register group struct declarations are provided for
4465  * convenience and illustrative purposes. They should, however, be used with
4466  * caution as the C language standard provides no guarantees about the alignment or
4467  * atomicity of device memory accesses. The recommended practice for coding device
4468  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4469  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4470  * alt_write_dword() functions for 64 bit registers.
4471  *
4472  * The struct declaration for register ALT_SPIM_DMACR.
4473  */
4474 struct ALT_SPIM_DMACR_s
4475 {
4476  volatile uint32_t RDMAE : 1; /* ALT_SPIM_DMACR_RDMAE */
4477  volatile uint32_t TDMAE : 1; /* ALT_SPIM_DMACR_TDMAE */
4478  const volatile uint32_t RSVD_DMACR : 30; /* ALT_SPIM_DMACR_RSVD_DMACR */
4479 };
4480 
4481 /* The typedef declaration for register ALT_SPIM_DMACR. */
4482 typedef struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t;
4483 #endif /* __ASSEMBLY__ */
4484 
4485 /* The reset value of the ALT_SPIM_DMACR register. */
4486 #define ALT_SPIM_DMACR_RESET 0x00000000
4487 /* The byte offset of the ALT_SPIM_DMACR register from the beginning of the component. */
4488 #define ALT_SPIM_DMACR_OFST 0x4c
4489 /* The address of the ALT_SPIM_DMACR register. */
4490 #define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
4491 
4492 /*
4493  * Register : DMA Transmit Data Level - DMATDLR
4494  *
4495  * DMA Transmit Data Level.
4496  *
4497  * This register is only valid when the DW_apb_ssi is configured with a set
4498  *
4499  * of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
4500  *
4501  * configured for DMA operation, this register will not exist and writing
4502  *
4503  * to its address will have no effect; reading from its address will
4504  *
4505  * return zero.
4506  *
4507  * Register Layout
4508  *
4509  * Bits | Access | Reset | Description
4510  * :-------|:-------|:------|:------------------------------
4511  * [7:0] | RW | 0x0 | ALT_SPIM_DMATDLR_DMATDL
4512  * [31:8] | R | 0x0 | ALT_SPIM_DMATDLR_RSVD_DMATDLR
4513  *
4514  */
4515 /*
4516  * Field : DMATDL
4517  *
4518  * Transmit Data Level.
4519  *
4520  * This bit field controls the level at which a DMA request is made by the
4521  *
4522  * transmit logic. It is equal to the watermark level; that is, the
4523  *
4524  * dma_tx_req signal is generated when the number of valid data entries
4525  *
4526  * in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
4527  *
4528  * Field Access Macros:
4529  *
4530  */
4531 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
4532 #define ALT_SPIM_DMATDLR_DMATDL_LSB 0
4533 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
4534 #define ALT_SPIM_DMATDLR_DMATDL_MSB 7
4535 /* The width in bits of the ALT_SPIM_DMATDLR_DMATDL register field. */
4536 #define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
4537 /* The mask used to set the ALT_SPIM_DMATDLR_DMATDL register field value. */
4538 #define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
4539 /* The mask used to clear the ALT_SPIM_DMATDLR_DMATDL register field value. */
4540 #define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
4541 /* The reset value of the ALT_SPIM_DMATDLR_DMATDL register field. */
4542 #define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
4543 /* Extracts the ALT_SPIM_DMATDLR_DMATDL field value from a register. */
4544 #define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
4545 /* Produces a ALT_SPIM_DMATDLR_DMATDL register field value suitable for setting the register. */
4546 #define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
4547 
4548 /*
4549  * Field : RSVD_DMATDLR
4550  *
4551  * Reserved bits - Read Only
4552  *
4553  * Field Access Macros:
4554  *
4555  */
4556 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field. */
4557 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_LSB 8
4558 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field. */
4559 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_MSB 31
4560 /* The width in bits of the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field. */
4561 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_WIDTH 24
4562 /* The mask used to set the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field value. */
4563 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_SET_MSK 0xffffff00
4564 /* The mask used to clear the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field value. */
4565 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_CLR_MSK 0x000000ff
4566 /* The reset value of the ALT_SPIM_DMATDLR_RSVD_DMATDLR register field. */
4567 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_RESET 0x0
4568 /* Extracts the ALT_SPIM_DMATDLR_RSVD_DMATDLR field value from a register. */
4569 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_GET(value) (((value) & 0xffffff00) >> 8)
4570 /* Produces a ALT_SPIM_DMATDLR_RSVD_DMATDLR register field value suitable for setting the register. */
4571 #define ALT_SPIM_DMATDLR_RSVD_DMATDLR_SET(value) (((value) << 8) & 0xffffff00)
4572 
4573 #ifndef __ASSEMBLY__
4574 /*
4575  * WARNING: The C register and register group struct declarations are provided for
4576  * convenience and illustrative purposes. They should, however, be used with
4577  * caution as the C language standard provides no guarantees about the alignment or
4578  * atomicity of device memory accesses. The recommended practice for coding device
4579  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4580  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4581  * alt_write_dword() functions for 64 bit registers.
4582  *
4583  * The struct declaration for register ALT_SPIM_DMATDLR.
4584  */
4585 struct ALT_SPIM_DMATDLR_s
4586 {
4587  volatile uint32_t DMATDL : 8; /* ALT_SPIM_DMATDLR_DMATDL */
4588  const volatile uint32_t RSVD_DMATDLR : 24; /* ALT_SPIM_DMATDLR_RSVD_DMATDLR */
4589 };
4590 
4591 /* The typedef declaration for register ALT_SPIM_DMATDLR. */
4592 typedef struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t;
4593 #endif /* __ASSEMBLY__ */
4594 
4595 /* The reset value of the ALT_SPIM_DMATDLR register. */
4596 #define ALT_SPIM_DMATDLR_RESET 0x00000000
4597 /* The byte offset of the ALT_SPIM_DMATDLR register from the beginning of the component. */
4598 #define ALT_SPIM_DMATDLR_OFST 0x50
4599 /* The address of the ALT_SPIM_DMATDLR register. */
4600 #define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
4601 
4602 /*
4603  * Register : DMA Receive Data Level - DMARDLR
4604  *
4605  * DMA Receive Data Level.
4606  *
4607  * This register is only valid when DW_apb_ssi is configured with a set of
4608  *
4609  * DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
4610  *
4611  * for DMA operation, this register will not exist and writing to its address
4612  *
4613  * will have no effect; reading from its address will return zero.
4614  *
4615  * Register Layout
4616  *
4617  * Bits | Access | Reset | Description
4618  * :-------|:-------|:------|:------------------------------
4619  * [7:0] | RW | 0x0 | ALT_SPIM_DMARDLR_DMARDL
4620  * [31:8] | R | 0x0 | ALT_SPIM_DMARDLR_RSVD_DMARDLR
4621  *
4622  */
4623 /*
4624  * Field : DMARDL
4625  *
4626  * Receive Data Level.
4627  *
4628  * This bit field controls the level at which a DMA request is made by the
4629  *
4630  * receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
4631  *
4632  * generated when the number of valid data entries in the receive FIFO is
4633  *
4634  * equal to or above this field value + 1, and RDMAE=1.
4635  *
4636  * Field Access Macros:
4637  *
4638  */
4639 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
4640 #define ALT_SPIM_DMARDLR_DMARDL_LSB 0
4641 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
4642 #define ALT_SPIM_DMARDLR_DMARDL_MSB 7
4643 /* The width in bits of the ALT_SPIM_DMARDLR_DMARDL register field. */
4644 #define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
4645 /* The mask used to set the ALT_SPIM_DMARDLR_DMARDL register field value. */
4646 #define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
4647 /* The mask used to clear the ALT_SPIM_DMARDLR_DMARDL register field value. */
4648 #define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
4649 /* The reset value of the ALT_SPIM_DMARDLR_DMARDL register field. */
4650 #define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
4651 /* Extracts the ALT_SPIM_DMARDLR_DMARDL field value from a register. */
4652 #define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
4653 /* Produces a ALT_SPIM_DMARDLR_DMARDL register field value suitable for setting the register. */
4654 #define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
4655 
4656 /*
4657  * Field : RSVD_DMARDLR
4658  *
4659  * Reserved bits - Read Only
4660  *
4661  * Field Access Macros:
4662  *
4663  */
4664 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field. */
4665 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_LSB 8
4666 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field. */
4667 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_MSB 31
4668 /* The width in bits of the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field. */
4669 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_WIDTH 24
4670 /* The mask used to set the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field value. */
4671 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_SET_MSK 0xffffff00
4672 /* The mask used to clear the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field value. */
4673 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_CLR_MSK 0x000000ff
4674 /* The reset value of the ALT_SPIM_DMARDLR_RSVD_DMARDLR register field. */
4675 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_RESET 0x0
4676 /* Extracts the ALT_SPIM_DMARDLR_RSVD_DMARDLR field value from a register. */
4677 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_GET(value) (((value) & 0xffffff00) >> 8)
4678 /* Produces a ALT_SPIM_DMARDLR_RSVD_DMARDLR register field value suitable for setting the register. */
4679 #define ALT_SPIM_DMARDLR_RSVD_DMARDLR_SET(value) (((value) << 8) & 0xffffff00)
4680 
4681 #ifndef __ASSEMBLY__
4682 /*
4683  * WARNING: The C register and register group struct declarations are provided for
4684  * convenience and illustrative purposes. They should, however, be used with
4685  * caution as the C language standard provides no guarantees about the alignment or
4686  * atomicity of device memory accesses. The recommended practice for coding device
4687  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4688  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4689  * alt_write_dword() functions for 64 bit registers.
4690  *
4691  * The struct declaration for register ALT_SPIM_DMARDLR.
4692  */
4693 struct ALT_SPIM_DMARDLR_s
4694 {
4695  volatile uint32_t DMARDL : 8; /* ALT_SPIM_DMARDLR_DMARDL */
4696  const volatile uint32_t RSVD_DMARDLR : 24; /* ALT_SPIM_DMARDLR_RSVD_DMARDLR */
4697 };
4698 
4699 /* The typedef declaration for register ALT_SPIM_DMARDLR. */
4700 typedef struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t;
4701 #endif /* __ASSEMBLY__ */
4702 
4703 /* The reset value of the ALT_SPIM_DMARDLR register. */
4704 #define ALT_SPIM_DMARDLR_RESET 0x00000000
4705 /* The byte offset of the ALT_SPIM_DMARDLR register from the beginning of the component. */
4706 #define ALT_SPIM_DMARDLR_OFST 0x54
4707 /* The address of the ALT_SPIM_DMARDLR register. */
4708 #define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
4709 
4710 /*
4711  * Register : Identification Register - IDR
4712  *
4713  * Identification Register.
4714  *
4715  * This register contains the peripherals identification code, which is
4716  *
4717  * written into the register at configuration time using coreConsultant.
4718  *
4719  * Register Layout
4720  *
4721  * Bits | Access | Reset | Description
4722  * :-------|:-------|:----------|:--------------------
4723  * [31:0] | R | 0x5510000 | ALT_SPIM_IDR_IDCODE
4724  *
4725  */
4726 /*
4727  * Field : IDCODE
4728  *
4729  * Identification code. The register contains the peripheral's identification code,
4730  * which is written into the register at configuration time using CoreConsultant.
4731  *
4732  * Field Access Macros:
4733  *
4734  */
4735 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IDR_IDCODE register field. */
4736 #define ALT_SPIM_IDR_IDCODE_LSB 0
4737 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IDR_IDCODE register field. */
4738 #define ALT_SPIM_IDR_IDCODE_MSB 31
4739 /* The width in bits of the ALT_SPIM_IDR_IDCODE register field. */
4740 #define ALT_SPIM_IDR_IDCODE_WIDTH 32
4741 /* The mask used to set the ALT_SPIM_IDR_IDCODE register field value. */
4742 #define ALT_SPIM_IDR_IDCODE_SET_MSK 0xffffffff
4743 /* The mask used to clear the ALT_SPIM_IDR_IDCODE register field value. */
4744 #define ALT_SPIM_IDR_IDCODE_CLR_MSK 0x00000000
4745 /* The reset value of the ALT_SPIM_IDR_IDCODE register field. */
4746 #define ALT_SPIM_IDR_IDCODE_RESET 0x5510000
4747 /* Extracts the ALT_SPIM_IDR_IDCODE field value from a register. */
4748 #define ALT_SPIM_IDR_IDCODE_GET(value) (((value) & 0xffffffff) >> 0)
4749 /* Produces a ALT_SPIM_IDR_IDCODE register field value suitable for setting the register. */
4750 #define ALT_SPIM_IDR_IDCODE_SET(value) (((value) << 0) & 0xffffffff)
4751 
4752 #ifndef __ASSEMBLY__
4753 /*
4754  * WARNING: The C register and register group struct declarations are provided for
4755  * convenience and illustrative purposes. They should, however, be used with
4756  * caution as the C language standard provides no guarantees about the alignment or
4757  * atomicity of device memory accesses. The recommended practice for coding device
4758  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4759  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4760  * alt_write_dword() functions for 64 bit registers.
4761  *
4762  * The struct declaration for register ALT_SPIM_IDR.
4763  */
4764 struct ALT_SPIM_IDR_s
4765 {
4766  const volatile uint32_t IDCODE : 32; /* ALT_SPIM_IDR_IDCODE */
4767 };
4768 
4769 /* The typedef declaration for register ALT_SPIM_IDR. */
4770 typedef struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t;
4771 #endif /* __ASSEMBLY__ */
4772 
4773 /* The reset value of the ALT_SPIM_IDR register. */
4774 #define ALT_SPIM_IDR_RESET 0x05510000
4775 /* The byte offset of the ALT_SPIM_IDR register from the beginning of the component. */
4776 #define ALT_SPIM_IDR_OFST 0x58
4777 /* The address of the ALT_SPIM_IDR register. */
4778 #define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
4779 
4780 /*
4781  * Register : SSI_VERSION_ID
4782  *
4783  * coreKit Version ID Register
4784  *
4785  * Register Layout
4786  *
4787  * Bits | Access | Reset | Description
4788  * :-------|:-------|:-----------|:-----------------------------------------
4789  * [31:0] | R | 0x3430302a | ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION
4790  *
4791  */
4792 /*
4793  * Field : SSI_COMP_VERSION
4794  *
4795  * Contains the hex representation of the Synopsys component version. Consists of
4796  * ASCII value for each number in the version, followed by *. For example
4797  * 32_30_31_2A represents the version 2.01*.
4798  *
4799  * Field Access Macros:
4800  *
4801  */
4802 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4803 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0
4804 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4805 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31
4806 /* The width in bits of the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4807 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_WIDTH 32
4808 /* The mask used to set the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field value. */
4809 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_SET_MSK 0xffffffff
4810 /* The mask used to clear the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field value. */
4811 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_CLR_MSK 0x00000000
4812 /* The reset value of the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field. */
4813 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430302a
4814 /* Extracts the ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION field value from a register. */
4815 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
4816 /* Produces a ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION register field value suitable for setting the register. */
4817 #define ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
4818 
4819 #ifndef __ASSEMBLY__
4820 /*
4821  * WARNING: The C register and register group struct declarations are provided for
4822  * convenience and illustrative purposes. They should, however, be used with
4823  * caution as the C language standard provides no guarantees about the alignment or
4824  * atomicity of device memory accesses. The recommended practice for coding device
4825  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4826  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4827  * alt_write_dword() functions for 64 bit registers.
4828  *
4829  * The struct declaration for register ALT_SPIM_SSI_VERSION_ID.
4830  */
4831 struct ALT_SPIM_SSI_VERSION_ID_s
4832 {
4833  const volatile uint32_t SSI_COMP_VERSION : 32; /* ALT_SPIM_SSI_VERSION_ID_SSI_COMP_VERSION */
4834 };
4835 
4836 /* The typedef declaration for register ALT_SPIM_SSI_VERSION_ID. */
4837 typedef struct ALT_SPIM_SSI_VERSION_ID_s ALT_SPIM_SSI_VERSION_ID_t;
4838 #endif /* __ASSEMBLY__ */
4839 
4840 /* The reset value of the ALT_SPIM_SSI_VERSION_ID register. */
4841 #define ALT_SPIM_SSI_VERSION_ID_RESET 0x3430302a
4842 /* The byte offset of the ALT_SPIM_SSI_VERSION_ID register from the beginning of the component. */
4843 #define ALT_SPIM_SSI_VERSION_ID_OFST 0x5c
4844 /* The address of the ALT_SPIM_SSI_VERSION_ID register. */
4845 #define ALT_SPIM_SSI_VERSION_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SSI_VERSION_ID_OFST))
4846 
4847 /*
4848  * Register : DW_apb_ssi Data Register - DR0
4849  *
4850  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4851  * read/write buffer for
4852  *
4853  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4854  * set to 32, then all 32 bits
4855  *
4856  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4857  * register is read, data in the
4858  *
4859  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4860  * transmit FIFO buffer; a write
4861  *
4862  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4863  *
4864  * Register Layout
4865  *
4866  * Bits | Access | Reset | Description
4867  * :-------|:-------|:------|:-----------------
4868  * [31:0] | RW | 0x0 | ALT_SPIM_DR0_DR0
4869  *
4870  */
4871 /*
4872  * Field : dr0
4873  *
4874  * Data Register. When writing to this register, you must right-justify the data.
4875  * Read
4876  *
4877  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4878  *
4879  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4880  * of the
4881  *
4882  * register are valid.
4883  *
4884  * Read = Receive FIFO buffer
4885  *
4886  * Write = Transmit FIFO buffer.
4887  *
4888  * Field Access Macros:
4889  *
4890  */
4891 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR0_DR0 register field. */
4892 #define ALT_SPIM_DR0_DR0_LSB 0
4893 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR0_DR0 register field. */
4894 #define ALT_SPIM_DR0_DR0_MSB 31
4895 /* The width in bits of the ALT_SPIM_DR0_DR0 register field. */
4896 #define ALT_SPIM_DR0_DR0_WIDTH 32
4897 /* The mask used to set the ALT_SPIM_DR0_DR0 register field value. */
4898 #define ALT_SPIM_DR0_DR0_SET_MSK 0xffffffff
4899 /* The mask used to clear the ALT_SPIM_DR0_DR0 register field value. */
4900 #define ALT_SPIM_DR0_DR0_CLR_MSK 0x00000000
4901 /* The reset value of the ALT_SPIM_DR0_DR0 register field. */
4902 #define ALT_SPIM_DR0_DR0_RESET 0x0
4903 /* Extracts the ALT_SPIM_DR0_DR0 field value from a register. */
4904 #define ALT_SPIM_DR0_DR0_GET(value) (((value) & 0xffffffff) >> 0)
4905 /* Produces a ALT_SPIM_DR0_DR0 register field value suitable for setting the register. */
4906 #define ALT_SPIM_DR0_DR0_SET(value) (((value) << 0) & 0xffffffff)
4907 
4908 #ifndef __ASSEMBLY__
4909 /*
4910  * WARNING: The C register and register group struct declarations are provided for
4911  * convenience and illustrative purposes. They should, however, be used with
4912  * caution as the C language standard provides no guarantees about the alignment or
4913  * atomicity of device memory accesses. The recommended practice for coding device
4914  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4915  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4916  * alt_write_dword() functions for 64 bit registers.
4917  *
4918  * The struct declaration for register ALT_SPIM_DR0.
4919  */
4920 struct ALT_SPIM_DR0_s
4921 {
4922  volatile uint32_t dr0 : 32; /* ALT_SPIM_DR0_DR0 */
4923 };
4924 
4925 /* The typedef declaration for register ALT_SPIM_DR0. */
4926 typedef struct ALT_SPIM_DR0_s ALT_SPIM_DR0_t;
4927 #endif /* __ASSEMBLY__ */
4928 
4929 /* The reset value of the ALT_SPIM_DR0 register. */
4930 #define ALT_SPIM_DR0_RESET 0x00000000
4931 /* The byte offset of the ALT_SPIM_DR0 register from the beginning of the component. */
4932 #define ALT_SPIM_DR0_OFST 0x60
4933 /* The address of the ALT_SPIM_DR0 register. */
4934 #define ALT_SPIM_DR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR0_OFST))
4935 
4936 /*
4937  * Register : DW_apb_ssi Data Register - DR1
4938  *
4939  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
4940  * read/write buffer for
4941  *
4942  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
4943  * set to 32, then all 32 bits
4944  *
4945  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
4946  * register is read, data in the
4947  *
4948  * receive FIFO buffer is accessed. When it is written to, data are moved into the
4949  * transmit FIFO buffer; a write
4950  *
4951  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
4952  *
4953  * Register Layout
4954  *
4955  * Bits | Access | Reset | Description
4956  * :-------|:-------|:------|:-----------------
4957  * [31:0] | RW | 0x0 | ALT_SPIM_DR1_DR1
4958  *
4959  */
4960 /*
4961  * Field : dr1
4962  *
4963  * Data Register. When writing to this register, you must right-justify the data.
4964  * Read
4965  *
4966  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
4967  *
4968  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
4969  * of the
4970  *
4971  * register are valid.
4972  *
4973  * Read = Receive FIFO buffer
4974  *
4975  * Write = Transmit FIFO buffer.
4976  *
4977  * Field Access Macros:
4978  *
4979  */
4980 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR1_DR1 register field. */
4981 #define ALT_SPIM_DR1_DR1_LSB 0
4982 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR1_DR1 register field. */
4983 #define ALT_SPIM_DR1_DR1_MSB 31
4984 /* The width in bits of the ALT_SPIM_DR1_DR1 register field. */
4985 #define ALT_SPIM_DR1_DR1_WIDTH 32
4986 /* The mask used to set the ALT_SPIM_DR1_DR1 register field value. */
4987 #define ALT_SPIM_DR1_DR1_SET_MSK 0xffffffff
4988 /* The mask used to clear the ALT_SPIM_DR1_DR1 register field value. */
4989 #define ALT_SPIM_DR1_DR1_CLR_MSK 0x00000000
4990 /* The reset value of the ALT_SPIM_DR1_DR1 register field. */
4991 #define ALT_SPIM_DR1_DR1_RESET 0x0
4992 /* Extracts the ALT_SPIM_DR1_DR1 field value from a register. */
4993 #define ALT_SPIM_DR1_DR1_GET(value) (((value) & 0xffffffff) >> 0)
4994 /* Produces a ALT_SPIM_DR1_DR1 register field value suitable for setting the register. */
4995 #define ALT_SPIM_DR1_DR1_SET(value) (((value) << 0) & 0xffffffff)
4996 
4997 #ifndef __ASSEMBLY__
4998 /*
4999  * WARNING: The C register and register group struct declarations are provided for
5000  * convenience and illustrative purposes. They should, however, be used with
5001  * caution as the C language standard provides no guarantees about the alignment or
5002  * atomicity of device memory accesses. The recommended practice for coding device
5003  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5004  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5005  * alt_write_dword() functions for 64 bit registers.
5006  *
5007  * The struct declaration for register ALT_SPIM_DR1.
5008  */
5009 struct ALT_SPIM_DR1_s
5010 {
5011  volatile uint32_t dr1 : 32; /* ALT_SPIM_DR1_DR1 */
5012 };
5013 
5014 /* The typedef declaration for register ALT_SPIM_DR1. */
5015 typedef struct ALT_SPIM_DR1_s ALT_SPIM_DR1_t;
5016 #endif /* __ASSEMBLY__ */
5017 
5018 /* The reset value of the ALT_SPIM_DR1 register. */
5019 #define ALT_SPIM_DR1_RESET 0x00000000
5020 /* The byte offset of the ALT_SPIM_DR1 register from the beginning of the component. */
5021 #define ALT_SPIM_DR1_OFST 0x64
5022 /* The address of the ALT_SPIM_DR1 register. */
5023 #define ALT_SPIM_DR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR1_OFST))
5024 
5025 /*
5026  * Register : DW_apb_ssi Data Register - DR2
5027  *
5028  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5029  * read/write buffer for
5030  *
5031  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5032  * set to 32, then all 32 bits
5033  *
5034  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5035  * register is read, data in the
5036  *
5037  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5038  * transmit FIFO buffer; a write
5039  *
5040  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5041  *
5042  * Register Layout
5043  *
5044  * Bits | Access | Reset | Description
5045  * :-------|:-------|:------|:-----------------
5046  * [31:0] | RW | 0x0 | ALT_SPIM_DR2_DR2
5047  *
5048  */
5049 /*
5050  * Field : dr2
5051  *
5052  * Data Register. When writing to this register, you must right-justify the data.
5053  * Read
5054  *
5055  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5056  *
5057  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5058  * of the
5059  *
5060  * register are valid.
5061  *
5062  * Read = Receive FIFO buffer
5063  *
5064  * Write = Transmit FIFO buffer.
5065  *
5066  * Field Access Macros:
5067  *
5068  */
5069 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR2_DR2 register field. */
5070 #define ALT_SPIM_DR2_DR2_LSB 0
5071 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR2_DR2 register field. */
5072 #define ALT_SPIM_DR2_DR2_MSB 31
5073 /* The width in bits of the ALT_SPIM_DR2_DR2 register field. */
5074 #define ALT_SPIM_DR2_DR2_WIDTH 32
5075 /* The mask used to set the ALT_SPIM_DR2_DR2 register field value. */
5076 #define ALT_SPIM_DR2_DR2_SET_MSK 0xffffffff
5077 /* The mask used to clear the ALT_SPIM_DR2_DR2 register field value. */
5078 #define ALT_SPIM_DR2_DR2_CLR_MSK 0x00000000
5079 /* The reset value of the ALT_SPIM_DR2_DR2 register field. */
5080 #define ALT_SPIM_DR2_DR2_RESET 0x0
5081 /* Extracts the ALT_SPIM_DR2_DR2 field value from a register. */
5082 #define ALT_SPIM_DR2_DR2_GET(value) (((value) & 0xffffffff) >> 0)
5083 /* Produces a ALT_SPIM_DR2_DR2 register field value suitable for setting the register. */
5084 #define ALT_SPIM_DR2_DR2_SET(value) (((value) << 0) & 0xffffffff)
5085 
5086 #ifndef __ASSEMBLY__
5087 /*
5088  * WARNING: The C register and register group struct declarations are provided for
5089  * convenience and illustrative purposes. They should, however, be used with
5090  * caution as the C language standard provides no guarantees about the alignment or
5091  * atomicity of device memory accesses. The recommended practice for coding device
5092  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5093  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5094  * alt_write_dword() functions for 64 bit registers.
5095  *
5096  * The struct declaration for register ALT_SPIM_DR2.
5097  */
5098 struct ALT_SPIM_DR2_s
5099 {
5100  volatile uint32_t dr2 : 32; /* ALT_SPIM_DR2_DR2 */
5101 };
5102 
5103 /* The typedef declaration for register ALT_SPIM_DR2. */
5104 typedef struct ALT_SPIM_DR2_s ALT_SPIM_DR2_t;
5105 #endif /* __ASSEMBLY__ */
5106 
5107 /* The reset value of the ALT_SPIM_DR2 register. */
5108 #define ALT_SPIM_DR2_RESET 0x00000000
5109 /* The byte offset of the ALT_SPIM_DR2 register from the beginning of the component. */
5110 #define ALT_SPIM_DR2_OFST 0x68
5111 /* The address of the ALT_SPIM_DR2 register. */
5112 #define ALT_SPIM_DR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR2_OFST))
5113 
5114 /*
5115  * Register : DW_apb_ssi Data Register - DR3
5116  *
5117  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5118  * read/write buffer for
5119  *
5120  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5121  * set to 32, then all 32 bits
5122  *
5123  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5124  * register is read, data in the
5125  *
5126  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5127  * transmit FIFO buffer; a write
5128  *
5129  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5130  *
5131  * Register Layout
5132  *
5133  * Bits | Access | Reset | Description
5134  * :-------|:-------|:------|:-----------------
5135  * [31:0] | RW | 0x0 | ALT_SPIM_DR3_DR3
5136  *
5137  */
5138 /*
5139  * Field : dr3
5140  *
5141  * Data Register. When writing to this register, you must right-justify the data.
5142  * Read
5143  *
5144  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5145  *
5146  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5147  * of the
5148  *
5149  * register are valid.
5150  *
5151  * Read = Receive FIFO buffer
5152  *
5153  * Write = Transmit FIFO buffer.
5154  *
5155  * Field Access Macros:
5156  *
5157  */
5158 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR3_DR3 register field. */
5159 #define ALT_SPIM_DR3_DR3_LSB 0
5160 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR3_DR3 register field. */
5161 #define ALT_SPIM_DR3_DR3_MSB 31
5162 /* The width in bits of the ALT_SPIM_DR3_DR3 register field. */
5163 #define ALT_SPIM_DR3_DR3_WIDTH 32
5164 /* The mask used to set the ALT_SPIM_DR3_DR3 register field value. */
5165 #define ALT_SPIM_DR3_DR3_SET_MSK 0xffffffff
5166 /* The mask used to clear the ALT_SPIM_DR3_DR3 register field value. */
5167 #define ALT_SPIM_DR3_DR3_CLR_MSK 0x00000000
5168 /* The reset value of the ALT_SPIM_DR3_DR3 register field. */
5169 #define ALT_SPIM_DR3_DR3_RESET 0x0
5170 /* Extracts the ALT_SPIM_DR3_DR3 field value from a register. */
5171 #define ALT_SPIM_DR3_DR3_GET(value) (((value) & 0xffffffff) >> 0)
5172 /* Produces a ALT_SPIM_DR3_DR3 register field value suitable for setting the register. */
5173 #define ALT_SPIM_DR3_DR3_SET(value) (((value) << 0) & 0xffffffff)
5174 
5175 #ifndef __ASSEMBLY__
5176 /*
5177  * WARNING: The C register and register group struct declarations are provided for
5178  * convenience and illustrative purposes. They should, however, be used with
5179  * caution as the C language standard provides no guarantees about the alignment or
5180  * atomicity of device memory accesses. The recommended practice for coding device
5181  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5182  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5183  * alt_write_dword() functions for 64 bit registers.
5184  *
5185  * The struct declaration for register ALT_SPIM_DR3.
5186  */
5187 struct ALT_SPIM_DR3_s
5188 {
5189  volatile uint32_t dr3 : 32; /* ALT_SPIM_DR3_DR3 */
5190 };
5191 
5192 /* The typedef declaration for register ALT_SPIM_DR3. */
5193 typedef struct ALT_SPIM_DR3_s ALT_SPIM_DR3_t;
5194 #endif /* __ASSEMBLY__ */
5195 
5196 /* The reset value of the ALT_SPIM_DR3 register. */
5197 #define ALT_SPIM_DR3_RESET 0x00000000
5198 /* The byte offset of the ALT_SPIM_DR3 register from the beginning of the component. */
5199 #define ALT_SPIM_DR3_OFST 0x6c
5200 /* The address of the ALT_SPIM_DR3 register. */
5201 #define ALT_SPIM_DR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR3_OFST))
5202 
5203 /*
5204  * Register : DW_apb_ssi Data Register - DR4
5205  *
5206  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5207  * read/write buffer for
5208  *
5209  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5210  * set to 32, then all 32 bits
5211  *
5212  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5213  * register is read, data in the
5214  *
5215  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5216  * transmit FIFO buffer; a write
5217  *
5218  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5219  *
5220  * Register Layout
5221  *
5222  * Bits | Access | Reset | Description
5223  * :-------|:-------|:------|:-----------------
5224  * [31:0] | RW | 0x0 | ALT_SPIM_DR4_DR4
5225  *
5226  */
5227 /*
5228  * Field : dr4
5229  *
5230  * Data Register. When writing to this register, you must right-justify the data.
5231  * Read
5232  *
5233  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5234  *
5235  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5236  * of the
5237  *
5238  * register are valid.
5239  *
5240  * Read = Receive FIFO buffer
5241  *
5242  * Write = Transmit FIFO buffer.
5243  *
5244  * Field Access Macros:
5245  *
5246  */
5247 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR4_DR4 register field. */
5248 #define ALT_SPIM_DR4_DR4_LSB 0
5249 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR4_DR4 register field. */
5250 #define ALT_SPIM_DR4_DR4_MSB 31
5251 /* The width in bits of the ALT_SPIM_DR4_DR4 register field. */
5252 #define ALT_SPIM_DR4_DR4_WIDTH 32
5253 /* The mask used to set the ALT_SPIM_DR4_DR4 register field value. */
5254 #define ALT_SPIM_DR4_DR4_SET_MSK 0xffffffff
5255 /* The mask used to clear the ALT_SPIM_DR4_DR4 register field value. */
5256 #define ALT_SPIM_DR4_DR4_CLR_MSK 0x00000000
5257 /* The reset value of the ALT_SPIM_DR4_DR4 register field. */
5258 #define ALT_SPIM_DR4_DR4_RESET 0x0
5259 /* Extracts the ALT_SPIM_DR4_DR4 field value from a register. */
5260 #define ALT_SPIM_DR4_DR4_GET(value) (((value) & 0xffffffff) >> 0)
5261 /* Produces a ALT_SPIM_DR4_DR4 register field value suitable for setting the register. */
5262 #define ALT_SPIM_DR4_DR4_SET(value) (((value) << 0) & 0xffffffff)
5263 
5264 #ifndef __ASSEMBLY__
5265 /*
5266  * WARNING: The C register and register group struct declarations are provided for
5267  * convenience and illustrative purposes. They should, however, be used with
5268  * caution as the C language standard provides no guarantees about the alignment or
5269  * atomicity of device memory accesses. The recommended practice for coding device
5270  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5271  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5272  * alt_write_dword() functions for 64 bit registers.
5273  *
5274  * The struct declaration for register ALT_SPIM_DR4.
5275  */
5276 struct ALT_SPIM_DR4_s
5277 {
5278  volatile uint32_t dr4 : 32; /* ALT_SPIM_DR4_DR4 */
5279 };
5280 
5281 /* The typedef declaration for register ALT_SPIM_DR4. */
5282 typedef struct ALT_SPIM_DR4_s ALT_SPIM_DR4_t;
5283 #endif /* __ASSEMBLY__ */
5284 
5285 /* The reset value of the ALT_SPIM_DR4 register. */
5286 #define ALT_SPIM_DR4_RESET 0x00000000
5287 /* The byte offset of the ALT_SPIM_DR4 register from the beginning of the component. */
5288 #define ALT_SPIM_DR4_OFST 0x70
5289 /* The address of the ALT_SPIM_DR4 register. */
5290 #define ALT_SPIM_DR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR4_OFST))
5291 
5292 /*
5293  * Register : DW_apb_ssi Data Register - DR5
5294  *
5295  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5296  * read/write buffer for
5297  *
5298  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5299  * set to 32, then all 32 bits
5300  *
5301  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5302  * register is read, data in the
5303  *
5304  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5305  * transmit FIFO buffer; a write
5306  *
5307  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5308  *
5309  * Register Layout
5310  *
5311  * Bits | Access | Reset | Description
5312  * :-------|:-------|:------|:-----------------
5313  * [31:0] | RW | 0x0 | ALT_SPIM_DR5_DR5
5314  *
5315  */
5316 /*
5317  * Field : dr5
5318  *
5319  * Data Register. When writing to this register, you must right-justify the data.
5320  * Read
5321  *
5322  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5323  *
5324  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5325  * of the
5326  *
5327  * register are valid.
5328  *
5329  * Read = Receive FIFO buffer
5330  *
5331  * Write = Transmit FIFO buffer.
5332  *
5333  * Field Access Macros:
5334  *
5335  */
5336 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR5_DR5 register field. */
5337 #define ALT_SPIM_DR5_DR5_LSB 0
5338 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR5_DR5 register field. */
5339 #define ALT_SPIM_DR5_DR5_MSB 31
5340 /* The width in bits of the ALT_SPIM_DR5_DR5 register field. */
5341 #define ALT_SPIM_DR5_DR5_WIDTH 32
5342 /* The mask used to set the ALT_SPIM_DR5_DR5 register field value. */
5343 #define ALT_SPIM_DR5_DR5_SET_MSK 0xffffffff
5344 /* The mask used to clear the ALT_SPIM_DR5_DR5 register field value. */
5345 #define ALT_SPIM_DR5_DR5_CLR_MSK 0x00000000
5346 /* The reset value of the ALT_SPIM_DR5_DR5 register field. */
5347 #define ALT_SPIM_DR5_DR5_RESET 0x0
5348 /* Extracts the ALT_SPIM_DR5_DR5 field value from a register. */
5349 #define ALT_SPIM_DR5_DR5_GET(value) (((value) & 0xffffffff) >> 0)
5350 /* Produces a ALT_SPIM_DR5_DR5 register field value suitable for setting the register. */
5351 #define ALT_SPIM_DR5_DR5_SET(value) (((value) << 0) & 0xffffffff)
5352 
5353 #ifndef __ASSEMBLY__
5354 /*
5355  * WARNING: The C register and register group struct declarations are provided for
5356  * convenience and illustrative purposes. They should, however, be used with
5357  * caution as the C language standard provides no guarantees about the alignment or
5358  * atomicity of device memory accesses. The recommended practice for coding device
5359  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5360  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5361  * alt_write_dword() functions for 64 bit registers.
5362  *
5363  * The struct declaration for register ALT_SPIM_DR5.
5364  */
5365 struct ALT_SPIM_DR5_s
5366 {
5367  volatile uint32_t dr5 : 32; /* ALT_SPIM_DR5_DR5 */
5368 };
5369 
5370 /* The typedef declaration for register ALT_SPIM_DR5. */
5371 typedef struct ALT_SPIM_DR5_s ALT_SPIM_DR5_t;
5372 #endif /* __ASSEMBLY__ */
5373 
5374 /* The reset value of the ALT_SPIM_DR5 register. */
5375 #define ALT_SPIM_DR5_RESET 0x00000000
5376 /* The byte offset of the ALT_SPIM_DR5 register from the beginning of the component. */
5377 #define ALT_SPIM_DR5_OFST 0x74
5378 /* The address of the ALT_SPIM_DR5 register. */
5379 #define ALT_SPIM_DR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR5_OFST))
5380 
5381 /*
5382  * Register : DW_apb_ssi Data Register - DR6
5383  *
5384  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5385  * read/write buffer for
5386  *
5387  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5388  * set to 32, then all 32 bits
5389  *
5390  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5391  * register is read, data in the
5392  *
5393  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5394  * transmit FIFO buffer; a write
5395  *
5396  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5397  *
5398  * Register Layout
5399  *
5400  * Bits | Access | Reset | Description
5401  * :-------|:-------|:------|:-----------------
5402  * [31:0] | RW | 0x0 | ALT_SPIM_DR6_DR6
5403  *
5404  */
5405 /*
5406  * Field : dr6
5407  *
5408  * Data Register. When writing to this register, you must right-justify the data.
5409  * Read
5410  *
5411  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5412  *
5413  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5414  * of the
5415  *
5416  * register are valid.
5417  *
5418  * Read = Receive FIFO buffer
5419  *
5420  * Write = Transmit FIFO buffer.
5421  *
5422  * Field Access Macros:
5423  *
5424  */
5425 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR6_DR6 register field. */
5426 #define ALT_SPIM_DR6_DR6_LSB 0
5427 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR6_DR6 register field. */
5428 #define ALT_SPIM_DR6_DR6_MSB 31
5429 /* The width in bits of the ALT_SPIM_DR6_DR6 register field. */
5430 #define ALT_SPIM_DR6_DR6_WIDTH 32
5431 /* The mask used to set the ALT_SPIM_DR6_DR6 register field value. */
5432 #define ALT_SPIM_DR6_DR6_SET_MSK 0xffffffff
5433 /* The mask used to clear the ALT_SPIM_DR6_DR6 register field value. */
5434 #define ALT_SPIM_DR6_DR6_CLR_MSK 0x00000000
5435 /* The reset value of the ALT_SPIM_DR6_DR6 register field. */
5436 #define ALT_SPIM_DR6_DR6_RESET 0x0
5437 /* Extracts the ALT_SPIM_DR6_DR6 field value from a register. */
5438 #define ALT_SPIM_DR6_DR6_GET(value) (((value) & 0xffffffff) >> 0)
5439 /* Produces a ALT_SPIM_DR6_DR6 register field value suitable for setting the register. */
5440 #define ALT_SPIM_DR6_DR6_SET(value) (((value) << 0) & 0xffffffff)
5441 
5442 #ifndef __ASSEMBLY__
5443 /*
5444  * WARNING: The C register and register group struct declarations are provided for
5445  * convenience and illustrative purposes. They should, however, be used with
5446  * caution as the C language standard provides no guarantees about the alignment or
5447  * atomicity of device memory accesses. The recommended practice for coding device
5448  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5449  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5450  * alt_write_dword() functions for 64 bit registers.
5451  *
5452  * The struct declaration for register ALT_SPIM_DR6.
5453  */
5454 struct ALT_SPIM_DR6_s
5455 {
5456  volatile uint32_t dr6 : 32; /* ALT_SPIM_DR6_DR6 */
5457 };
5458 
5459 /* The typedef declaration for register ALT_SPIM_DR6. */
5460 typedef struct ALT_SPIM_DR6_s ALT_SPIM_DR6_t;
5461 #endif /* __ASSEMBLY__ */
5462 
5463 /* The reset value of the ALT_SPIM_DR6 register. */
5464 #define ALT_SPIM_DR6_RESET 0x00000000
5465 /* The byte offset of the ALT_SPIM_DR6 register from the beginning of the component. */
5466 #define ALT_SPIM_DR6_OFST 0x78
5467 /* The address of the ALT_SPIM_DR6 register. */
5468 #define ALT_SPIM_DR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR6_OFST))
5469 
5470 /*
5471  * Register : DW_apb_ssi Data Register - DR7
5472  *
5473  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5474  * read/write buffer for
5475  *
5476  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5477  * set to 32, then all 32 bits
5478  *
5479  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5480  * register is read, data in the
5481  *
5482  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5483  * transmit FIFO buffer; a write
5484  *
5485  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5486  *
5487  * Register Layout
5488  *
5489  * Bits | Access | Reset | Description
5490  * :-------|:-------|:------|:-----------------
5491  * [31:0] | RW | 0x0 | ALT_SPIM_DR7_DR7
5492  *
5493  */
5494 /*
5495  * Field : dr7
5496  *
5497  * Data Register. When writing to this register, you must right-justify the data.
5498  * Read
5499  *
5500  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5501  *
5502  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5503  * of the
5504  *
5505  * register are valid.
5506  *
5507  * Read = Receive FIFO buffer
5508  *
5509  * Write = Transmit FIFO buffer.
5510  *
5511  * Field Access Macros:
5512  *
5513  */
5514 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR7_DR7 register field. */
5515 #define ALT_SPIM_DR7_DR7_LSB 0
5516 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR7_DR7 register field. */
5517 #define ALT_SPIM_DR7_DR7_MSB 31
5518 /* The width in bits of the ALT_SPIM_DR7_DR7 register field. */
5519 #define ALT_SPIM_DR7_DR7_WIDTH 32
5520 /* The mask used to set the ALT_SPIM_DR7_DR7 register field value. */
5521 #define ALT_SPIM_DR7_DR7_SET_MSK 0xffffffff
5522 /* The mask used to clear the ALT_SPIM_DR7_DR7 register field value. */
5523 #define ALT_SPIM_DR7_DR7_CLR_MSK 0x00000000
5524 /* The reset value of the ALT_SPIM_DR7_DR7 register field. */
5525 #define ALT_SPIM_DR7_DR7_RESET 0x0
5526 /* Extracts the ALT_SPIM_DR7_DR7 field value from a register. */
5527 #define ALT_SPIM_DR7_DR7_GET(value) (((value) & 0xffffffff) >> 0)
5528 /* Produces a ALT_SPIM_DR7_DR7 register field value suitable for setting the register. */
5529 #define ALT_SPIM_DR7_DR7_SET(value) (((value) << 0) & 0xffffffff)
5530 
5531 #ifndef __ASSEMBLY__
5532 /*
5533  * WARNING: The C register and register group struct declarations are provided for
5534  * convenience and illustrative purposes. They should, however, be used with
5535  * caution as the C language standard provides no guarantees about the alignment or
5536  * atomicity of device memory accesses. The recommended practice for coding device
5537  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5538  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5539  * alt_write_dword() functions for 64 bit registers.
5540  *
5541  * The struct declaration for register ALT_SPIM_DR7.
5542  */
5543 struct ALT_SPIM_DR7_s
5544 {
5545  volatile uint32_t dr7 : 32; /* ALT_SPIM_DR7_DR7 */
5546 };
5547 
5548 /* The typedef declaration for register ALT_SPIM_DR7. */
5549 typedef struct ALT_SPIM_DR7_s ALT_SPIM_DR7_t;
5550 #endif /* __ASSEMBLY__ */
5551 
5552 /* The reset value of the ALT_SPIM_DR7 register. */
5553 #define ALT_SPIM_DR7_RESET 0x00000000
5554 /* The byte offset of the ALT_SPIM_DR7 register from the beginning of the component. */
5555 #define ALT_SPIM_DR7_OFST 0x7c
5556 /* The address of the ALT_SPIM_DR7 register. */
5557 #define ALT_SPIM_DR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR7_OFST))
5558 
5559 /*
5560  * Register : DW_apb_ssi Data Register - DR8
5561  *
5562  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5563  * read/write buffer for
5564  *
5565  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5566  * set to 32, then all 32 bits
5567  *
5568  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5569  * register is read, data in the
5570  *
5571  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5572  * transmit FIFO buffer; a write
5573  *
5574  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5575  *
5576  * Register Layout
5577  *
5578  * Bits | Access | Reset | Description
5579  * :-------|:-------|:------|:-----------------
5580  * [31:0] | RW | 0x0 | ALT_SPIM_DR8_DR8
5581  *
5582  */
5583 /*
5584  * Field : dr8
5585  *
5586  * Data Register. When writing to this register, you must right-justify the data.
5587  * Read
5588  *
5589  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5590  *
5591  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5592  * of the
5593  *
5594  * register are valid.
5595  *
5596  * Read = Receive FIFO buffer
5597  *
5598  * Write = Transmit FIFO buffer.
5599  *
5600  * Field Access Macros:
5601  *
5602  */
5603 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR8_DR8 register field. */
5604 #define ALT_SPIM_DR8_DR8_LSB 0
5605 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR8_DR8 register field. */
5606 #define ALT_SPIM_DR8_DR8_MSB 31
5607 /* The width in bits of the ALT_SPIM_DR8_DR8 register field. */
5608 #define ALT_SPIM_DR8_DR8_WIDTH 32
5609 /* The mask used to set the ALT_SPIM_DR8_DR8 register field value. */
5610 #define ALT_SPIM_DR8_DR8_SET_MSK 0xffffffff
5611 /* The mask used to clear the ALT_SPIM_DR8_DR8 register field value. */
5612 #define ALT_SPIM_DR8_DR8_CLR_MSK 0x00000000
5613 /* The reset value of the ALT_SPIM_DR8_DR8 register field. */
5614 #define ALT_SPIM_DR8_DR8_RESET 0x0
5615 /* Extracts the ALT_SPIM_DR8_DR8 field value from a register. */
5616 #define ALT_SPIM_DR8_DR8_GET(value) (((value) & 0xffffffff) >> 0)
5617 /* Produces a ALT_SPIM_DR8_DR8 register field value suitable for setting the register. */
5618 #define ALT_SPIM_DR8_DR8_SET(value) (((value) << 0) & 0xffffffff)
5619 
5620 #ifndef __ASSEMBLY__
5621 /*
5622  * WARNING: The C register and register group struct declarations are provided for
5623  * convenience and illustrative purposes. They should, however, be used with
5624  * caution as the C language standard provides no guarantees about the alignment or
5625  * atomicity of device memory accesses. The recommended practice for coding device
5626  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5627  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5628  * alt_write_dword() functions for 64 bit registers.
5629  *
5630  * The struct declaration for register ALT_SPIM_DR8.
5631  */
5632 struct ALT_SPIM_DR8_s
5633 {
5634  volatile uint32_t dr8 : 32; /* ALT_SPIM_DR8_DR8 */
5635 };
5636 
5637 /* The typedef declaration for register ALT_SPIM_DR8. */
5638 typedef struct ALT_SPIM_DR8_s ALT_SPIM_DR8_t;
5639 #endif /* __ASSEMBLY__ */
5640 
5641 /* The reset value of the ALT_SPIM_DR8 register. */
5642 #define ALT_SPIM_DR8_RESET 0x00000000
5643 /* The byte offset of the ALT_SPIM_DR8 register from the beginning of the component. */
5644 #define ALT_SPIM_DR8_OFST 0x80
5645 /* The address of the ALT_SPIM_DR8 register. */
5646 #define ALT_SPIM_DR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR8_OFST))
5647 
5648 /*
5649  * Register : DW_apb_ssi Data Register - DR9
5650  *
5651  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5652  * read/write buffer for
5653  *
5654  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5655  * set to 32, then all 32 bits
5656  *
5657  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5658  * register is read, data in the
5659  *
5660  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5661  * transmit FIFO buffer; a write
5662  *
5663  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5664  *
5665  * Register Layout
5666  *
5667  * Bits | Access | Reset | Description
5668  * :-------|:-------|:------|:-----------------
5669  * [31:0] | RW | 0x0 | ALT_SPIM_DR9_DR9
5670  *
5671  */
5672 /*
5673  * Field : dr9
5674  *
5675  * Data Register. When writing to this register, you must right-justify the data.
5676  * Read
5677  *
5678  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5679  *
5680  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5681  * of the
5682  *
5683  * register are valid.
5684  *
5685  * Read = Receive FIFO buffer
5686  *
5687  * Write = Transmit FIFO buffer.
5688  *
5689  * Field Access Macros:
5690  *
5691  */
5692 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR9_DR9 register field. */
5693 #define ALT_SPIM_DR9_DR9_LSB 0
5694 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR9_DR9 register field. */
5695 #define ALT_SPIM_DR9_DR9_MSB 31
5696 /* The width in bits of the ALT_SPIM_DR9_DR9 register field. */
5697 #define ALT_SPIM_DR9_DR9_WIDTH 32
5698 /* The mask used to set the ALT_SPIM_DR9_DR9 register field value. */
5699 #define ALT_SPIM_DR9_DR9_SET_MSK 0xffffffff
5700 /* The mask used to clear the ALT_SPIM_DR9_DR9 register field value. */
5701 #define ALT_SPIM_DR9_DR9_CLR_MSK 0x00000000
5702 /* The reset value of the ALT_SPIM_DR9_DR9 register field. */
5703 #define ALT_SPIM_DR9_DR9_RESET 0x0
5704 /* Extracts the ALT_SPIM_DR9_DR9 field value from a register. */
5705 #define ALT_SPIM_DR9_DR9_GET(value) (((value) & 0xffffffff) >> 0)
5706 /* Produces a ALT_SPIM_DR9_DR9 register field value suitable for setting the register. */
5707 #define ALT_SPIM_DR9_DR9_SET(value) (((value) << 0) & 0xffffffff)
5708 
5709 #ifndef __ASSEMBLY__
5710 /*
5711  * WARNING: The C register and register group struct declarations are provided for
5712  * convenience and illustrative purposes. They should, however, be used with
5713  * caution as the C language standard provides no guarantees about the alignment or
5714  * atomicity of device memory accesses. The recommended practice for coding device
5715  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5716  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5717  * alt_write_dword() functions for 64 bit registers.
5718  *
5719  * The struct declaration for register ALT_SPIM_DR9.
5720  */
5721 struct ALT_SPIM_DR9_s
5722 {
5723  volatile uint32_t dr9 : 32; /* ALT_SPIM_DR9_DR9 */
5724 };
5725 
5726 /* The typedef declaration for register ALT_SPIM_DR9. */
5727 typedef struct ALT_SPIM_DR9_s ALT_SPIM_DR9_t;
5728 #endif /* __ASSEMBLY__ */
5729 
5730 /* The reset value of the ALT_SPIM_DR9 register. */
5731 #define ALT_SPIM_DR9_RESET 0x00000000
5732 /* The byte offset of the ALT_SPIM_DR9 register from the beginning of the component. */
5733 #define ALT_SPIM_DR9_OFST 0x84
5734 /* The address of the ALT_SPIM_DR9 register. */
5735 #define ALT_SPIM_DR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR9_OFST))
5736 
5737 /*
5738  * Register : DW_apb_ssi Data Register - DR10
5739  *
5740  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5741  * read/write buffer for
5742  *
5743  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5744  * set to 32, then all 32 bits
5745  *
5746  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5747  * register is read, data in the
5748  *
5749  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5750  * transmit FIFO buffer; a write
5751  *
5752  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5753  *
5754  * Register Layout
5755  *
5756  * Bits | Access | Reset | Description
5757  * :-------|:-------|:------|:-------------------
5758  * [31:0] | RW | 0x0 | ALT_SPIM_DR10_DR10
5759  *
5760  */
5761 /*
5762  * Field : dr10
5763  *
5764  * Data Register. When writing to this register, you must right-justify the data.
5765  * Read
5766  *
5767  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5768  *
5769  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5770  * of the
5771  *
5772  * register are valid.
5773  *
5774  * Read = Receive FIFO buffer
5775  *
5776  * Write = Transmit FIFO buffer.
5777  *
5778  * Field Access Macros:
5779  *
5780  */
5781 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR10_DR10 register field. */
5782 #define ALT_SPIM_DR10_DR10_LSB 0
5783 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR10_DR10 register field. */
5784 #define ALT_SPIM_DR10_DR10_MSB 31
5785 /* The width in bits of the ALT_SPIM_DR10_DR10 register field. */
5786 #define ALT_SPIM_DR10_DR10_WIDTH 32
5787 /* The mask used to set the ALT_SPIM_DR10_DR10 register field value. */
5788 #define ALT_SPIM_DR10_DR10_SET_MSK 0xffffffff
5789 /* The mask used to clear the ALT_SPIM_DR10_DR10 register field value. */
5790 #define ALT_SPIM_DR10_DR10_CLR_MSK 0x00000000
5791 /* The reset value of the ALT_SPIM_DR10_DR10 register field. */
5792 #define ALT_SPIM_DR10_DR10_RESET 0x0
5793 /* Extracts the ALT_SPIM_DR10_DR10 field value from a register. */
5794 #define ALT_SPIM_DR10_DR10_GET(value) (((value) & 0xffffffff) >> 0)
5795 /* Produces a ALT_SPIM_DR10_DR10 register field value suitable for setting the register. */
5796 #define ALT_SPIM_DR10_DR10_SET(value) (((value) << 0) & 0xffffffff)
5797 
5798 #ifndef __ASSEMBLY__
5799 /*
5800  * WARNING: The C register and register group struct declarations are provided for
5801  * convenience and illustrative purposes. They should, however, be used with
5802  * caution as the C language standard provides no guarantees about the alignment or
5803  * atomicity of device memory accesses. The recommended practice for coding device
5804  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5805  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5806  * alt_write_dword() functions for 64 bit registers.
5807  *
5808  * The struct declaration for register ALT_SPIM_DR10.
5809  */
5810 struct ALT_SPIM_DR10_s
5811 {
5812  volatile uint32_t dr10 : 32; /* ALT_SPIM_DR10_DR10 */
5813 };
5814 
5815 /* The typedef declaration for register ALT_SPIM_DR10. */
5816 typedef struct ALT_SPIM_DR10_s ALT_SPIM_DR10_t;
5817 #endif /* __ASSEMBLY__ */
5818 
5819 /* The reset value of the ALT_SPIM_DR10 register. */
5820 #define ALT_SPIM_DR10_RESET 0x00000000
5821 /* The byte offset of the ALT_SPIM_DR10 register from the beginning of the component. */
5822 #define ALT_SPIM_DR10_OFST 0x88
5823 /* The address of the ALT_SPIM_DR10 register. */
5824 #define ALT_SPIM_DR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR10_OFST))
5825 
5826 /*
5827  * Register : DW_apb_ssi Data Register - DR11
5828  *
5829  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5830  * read/write buffer for
5831  *
5832  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5833  * set to 32, then all 32 bits
5834  *
5835  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5836  * register is read, data in the
5837  *
5838  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5839  * transmit FIFO buffer; a write
5840  *
5841  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5842  *
5843  * Register Layout
5844  *
5845  * Bits | Access | Reset | Description
5846  * :-------|:-------|:------|:-------------------
5847  * [31:0] | RW | 0x0 | ALT_SPIM_DR11_DR11
5848  *
5849  */
5850 /*
5851  * Field : dr11
5852  *
5853  * Data Register. When writing to this register, you must right-justify the data.
5854  * Read
5855  *
5856  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5857  *
5858  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5859  * of the
5860  *
5861  * register are valid.
5862  *
5863  * Read = Receive FIFO buffer
5864  *
5865  * Write = Transmit FIFO buffer.
5866  *
5867  * Field Access Macros:
5868  *
5869  */
5870 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR11_DR11 register field. */
5871 #define ALT_SPIM_DR11_DR11_LSB 0
5872 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR11_DR11 register field. */
5873 #define ALT_SPIM_DR11_DR11_MSB 31
5874 /* The width in bits of the ALT_SPIM_DR11_DR11 register field. */
5875 #define ALT_SPIM_DR11_DR11_WIDTH 32
5876 /* The mask used to set the ALT_SPIM_DR11_DR11 register field value. */
5877 #define ALT_SPIM_DR11_DR11_SET_MSK 0xffffffff
5878 /* The mask used to clear the ALT_SPIM_DR11_DR11 register field value. */
5879 #define ALT_SPIM_DR11_DR11_CLR_MSK 0x00000000
5880 /* The reset value of the ALT_SPIM_DR11_DR11 register field. */
5881 #define ALT_SPIM_DR11_DR11_RESET 0x0
5882 /* Extracts the ALT_SPIM_DR11_DR11 field value from a register. */
5883 #define ALT_SPIM_DR11_DR11_GET(value) (((value) & 0xffffffff) >> 0)
5884 /* Produces a ALT_SPIM_DR11_DR11 register field value suitable for setting the register. */
5885 #define ALT_SPIM_DR11_DR11_SET(value) (((value) << 0) & 0xffffffff)
5886 
5887 #ifndef __ASSEMBLY__
5888 /*
5889  * WARNING: The C register and register group struct declarations are provided for
5890  * convenience and illustrative purposes. They should, however, be used with
5891  * caution as the C language standard provides no guarantees about the alignment or
5892  * atomicity of device memory accesses. The recommended practice for coding device
5893  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5894  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5895  * alt_write_dword() functions for 64 bit registers.
5896  *
5897  * The struct declaration for register ALT_SPIM_DR11.
5898  */
5899 struct ALT_SPIM_DR11_s
5900 {
5901  volatile uint32_t dr11 : 32; /* ALT_SPIM_DR11_DR11 */
5902 };
5903 
5904 /* The typedef declaration for register ALT_SPIM_DR11. */
5905 typedef struct ALT_SPIM_DR11_s ALT_SPIM_DR11_t;
5906 #endif /* __ASSEMBLY__ */
5907 
5908 /* The reset value of the ALT_SPIM_DR11 register. */
5909 #define ALT_SPIM_DR11_RESET 0x00000000
5910 /* The byte offset of the ALT_SPIM_DR11 register from the beginning of the component. */
5911 #define ALT_SPIM_DR11_OFST 0x8c
5912 /* The address of the ALT_SPIM_DR11 register. */
5913 #define ALT_SPIM_DR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR11_OFST))
5914 
5915 /*
5916  * Register : DW_apb_ssi Data Register - DR12
5917  *
5918  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
5919  * read/write buffer for
5920  *
5921  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
5922  * set to 32, then all 32 bits
5923  *
5924  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
5925  * register is read, data in the
5926  *
5927  * receive FIFO buffer is accessed. When it is written to, data are moved into the
5928  * transmit FIFO buffer; a write
5929  *
5930  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
5931  *
5932  * Register Layout
5933  *
5934  * Bits | Access | Reset | Description
5935  * :-------|:-------|:------|:-------------------
5936  * [31:0] | RW | 0x0 | ALT_SPIM_DR12_DR12
5937  *
5938  */
5939 /*
5940  * Field : dr12
5941  *
5942  * Data Register. When writing to this register, you must right-justify the data.
5943  * Read
5944  *
5945  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
5946  *
5947  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
5948  * of the
5949  *
5950  * register are valid.
5951  *
5952  * Read = Receive FIFO buffer
5953  *
5954  * Write = Transmit FIFO buffer.
5955  *
5956  * Field Access Macros:
5957  *
5958  */
5959 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR12_DR12 register field. */
5960 #define ALT_SPIM_DR12_DR12_LSB 0
5961 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR12_DR12 register field. */
5962 #define ALT_SPIM_DR12_DR12_MSB 31
5963 /* The width in bits of the ALT_SPIM_DR12_DR12 register field. */
5964 #define ALT_SPIM_DR12_DR12_WIDTH 32
5965 /* The mask used to set the ALT_SPIM_DR12_DR12 register field value. */
5966 #define ALT_SPIM_DR12_DR12_SET_MSK 0xffffffff
5967 /* The mask used to clear the ALT_SPIM_DR12_DR12 register field value. */
5968 #define ALT_SPIM_DR12_DR12_CLR_MSK 0x00000000
5969 /* The reset value of the ALT_SPIM_DR12_DR12 register field. */
5970 #define ALT_SPIM_DR12_DR12_RESET 0x0
5971 /* Extracts the ALT_SPIM_DR12_DR12 field value from a register. */
5972 #define ALT_SPIM_DR12_DR12_GET(value) (((value) & 0xffffffff) >> 0)
5973 /* Produces a ALT_SPIM_DR12_DR12 register field value suitable for setting the register. */
5974 #define ALT_SPIM_DR12_DR12_SET(value) (((value) << 0) & 0xffffffff)
5975 
5976 #ifndef __ASSEMBLY__
5977 /*
5978  * WARNING: The C register and register group struct declarations are provided for
5979  * convenience and illustrative purposes. They should, however, be used with
5980  * caution as the C language standard provides no guarantees about the alignment or
5981  * atomicity of device memory accesses. The recommended practice for coding device
5982  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5983  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5984  * alt_write_dword() functions for 64 bit registers.
5985  *
5986  * The struct declaration for register ALT_SPIM_DR12.
5987  */
5988 struct ALT_SPIM_DR12_s
5989 {
5990  volatile uint32_t dr12 : 32; /* ALT_SPIM_DR12_DR12 */
5991 };
5992 
5993 /* The typedef declaration for register ALT_SPIM_DR12. */
5994 typedef struct ALT_SPIM_DR12_s ALT_SPIM_DR12_t;
5995 #endif /* __ASSEMBLY__ */
5996 
5997 /* The reset value of the ALT_SPIM_DR12 register. */
5998 #define ALT_SPIM_DR12_RESET 0x00000000
5999 /* The byte offset of the ALT_SPIM_DR12 register from the beginning of the component. */
6000 #define ALT_SPIM_DR12_OFST 0x90
6001 /* The address of the ALT_SPIM_DR12 register. */
6002 #define ALT_SPIM_DR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR12_OFST))
6003 
6004 /*
6005  * Register : DW_apb_ssi Data Register - DR13
6006  *
6007  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6008  * read/write buffer for
6009  *
6010  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6011  * set to 32, then all 32 bits
6012  *
6013  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6014  * register is read, data in the
6015  *
6016  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6017  * transmit FIFO buffer; a write
6018  *
6019  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6020  *
6021  * Register Layout
6022  *
6023  * Bits | Access | Reset | Description
6024  * :-------|:-------|:------|:-------------------
6025  * [31:0] | RW | 0x0 | ALT_SPIM_DR13_DR13
6026  *
6027  */
6028 /*
6029  * Field : dr13
6030  *
6031  * Data Register. When writing to this register, you must right-justify the data.
6032  * Read
6033  *
6034  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6035  *
6036  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6037  * of the
6038  *
6039  * register are valid.
6040  *
6041  * Read = Receive FIFO buffer
6042  *
6043  * Write = Transmit FIFO buffer.
6044  *
6045  * Field Access Macros:
6046  *
6047  */
6048 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR13_DR13 register field. */
6049 #define ALT_SPIM_DR13_DR13_LSB 0
6050 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR13_DR13 register field. */
6051 #define ALT_SPIM_DR13_DR13_MSB 31
6052 /* The width in bits of the ALT_SPIM_DR13_DR13 register field. */
6053 #define ALT_SPIM_DR13_DR13_WIDTH 32
6054 /* The mask used to set the ALT_SPIM_DR13_DR13 register field value. */
6055 #define ALT_SPIM_DR13_DR13_SET_MSK 0xffffffff
6056 /* The mask used to clear the ALT_SPIM_DR13_DR13 register field value. */
6057 #define ALT_SPIM_DR13_DR13_CLR_MSK 0x00000000
6058 /* The reset value of the ALT_SPIM_DR13_DR13 register field. */
6059 #define ALT_SPIM_DR13_DR13_RESET 0x0
6060 /* Extracts the ALT_SPIM_DR13_DR13 field value from a register. */
6061 #define ALT_SPIM_DR13_DR13_GET(value) (((value) & 0xffffffff) >> 0)
6062 /* Produces a ALT_SPIM_DR13_DR13 register field value suitable for setting the register. */
6063 #define ALT_SPIM_DR13_DR13_SET(value) (((value) << 0) & 0xffffffff)
6064 
6065 #ifndef __ASSEMBLY__
6066 /*
6067  * WARNING: The C register and register group struct declarations are provided for
6068  * convenience and illustrative purposes. They should, however, be used with
6069  * caution as the C language standard provides no guarantees about the alignment or
6070  * atomicity of device memory accesses. The recommended practice for coding device
6071  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6072  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6073  * alt_write_dword() functions for 64 bit registers.
6074  *
6075  * The struct declaration for register ALT_SPIM_DR13.
6076  */
6077 struct ALT_SPIM_DR13_s
6078 {
6079  volatile uint32_t dr13 : 32; /* ALT_SPIM_DR13_DR13 */
6080 };
6081 
6082 /* The typedef declaration for register ALT_SPIM_DR13. */
6083 typedef struct ALT_SPIM_DR13_s ALT_SPIM_DR13_t;
6084 #endif /* __ASSEMBLY__ */
6085 
6086 /* The reset value of the ALT_SPIM_DR13 register. */
6087 #define ALT_SPIM_DR13_RESET 0x00000000
6088 /* The byte offset of the ALT_SPIM_DR13 register from the beginning of the component. */
6089 #define ALT_SPIM_DR13_OFST 0x94
6090 /* The address of the ALT_SPIM_DR13 register. */
6091 #define ALT_SPIM_DR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR13_OFST))
6092 
6093 /*
6094  * Register : DW_apb_ssi Data Register - DR14
6095  *
6096  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6097  * read/write buffer for
6098  *
6099  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6100  * set to 32, then all 32 bits
6101  *
6102  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6103  * register is read, data in the
6104  *
6105  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6106  * transmit FIFO buffer; a write
6107  *
6108  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6109  *
6110  * Register Layout
6111  *
6112  * Bits | Access | Reset | Description
6113  * :-------|:-------|:------|:-------------------
6114  * [31:0] | RW | 0x0 | ALT_SPIM_DR14_DR14
6115  *
6116  */
6117 /*
6118  * Field : dr14
6119  *
6120  * Data Register. When writing to this register, you must right-justify the data.
6121  * Read
6122  *
6123  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6124  *
6125  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6126  * of the
6127  *
6128  * register are valid.
6129  *
6130  * Read = Receive FIFO buffer
6131  *
6132  * Write = Transmit FIFO buffer.
6133  *
6134  * Field Access Macros:
6135  *
6136  */
6137 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR14_DR14 register field. */
6138 #define ALT_SPIM_DR14_DR14_LSB 0
6139 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR14_DR14 register field. */
6140 #define ALT_SPIM_DR14_DR14_MSB 31
6141 /* The width in bits of the ALT_SPIM_DR14_DR14 register field. */
6142 #define ALT_SPIM_DR14_DR14_WIDTH 32
6143 /* The mask used to set the ALT_SPIM_DR14_DR14 register field value. */
6144 #define ALT_SPIM_DR14_DR14_SET_MSK 0xffffffff
6145 /* The mask used to clear the ALT_SPIM_DR14_DR14 register field value. */
6146 #define ALT_SPIM_DR14_DR14_CLR_MSK 0x00000000
6147 /* The reset value of the ALT_SPIM_DR14_DR14 register field. */
6148 #define ALT_SPIM_DR14_DR14_RESET 0x0
6149 /* Extracts the ALT_SPIM_DR14_DR14 field value from a register. */
6150 #define ALT_SPIM_DR14_DR14_GET(value) (((value) & 0xffffffff) >> 0)
6151 /* Produces a ALT_SPIM_DR14_DR14 register field value suitable for setting the register. */
6152 #define ALT_SPIM_DR14_DR14_SET(value) (((value) << 0) & 0xffffffff)
6153 
6154 #ifndef __ASSEMBLY__
6155 /*
6156  * WARNING: The C register and register group struct declarations are provided for
6157  * convenience and illustrative purposes. They should, however, be used with
6158  * caution as the C language standard provides no guarantees about the alignment or
6159  * atomicity of device memory accesses. The recommended practice for coding device
6160  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6161  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6162  * alt_write_dword() functions for 64 bit registers.
6163  *
6164  * The struct declaration for register ALT_SPIM_DR14.
6165  */
6166 struct ALT_SPIM_DR14_s
6167 {
6168  volatile uint32_t dr14 : 32; /* ALT_SPIM_DR14_DR14 */
6169 };
6170 
6171 /* The typedef declaration for register ALT_SPIM_DR14. */
6172 typedef struct ALT_SPIM_DR14_s ALT_SPIM_DR14_t;
6173 #endif /* __ASSEMBLY__ */
6174 
6175 /* The reset value of the ALT_SPIM_DR14 register. */
6176 #define ALT_SPIM_DR14_RESET 0x00000000
6177 /* The byte offset of the ALT_SPIM_DR14 register from the beginning of the component. */
6178 #define ALT_SPIM_DR14_OFST 0x98
6179 /* The address of the ALT_SPIM_DR14 register. */
6180 #define ALT_SPIM_DR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR14_OFST))
6181 
6182 /*
6183  * Register : DW_apb_ssi Data Register - DR15
6184  *
6185  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6186  * read/write buffer for
6187  *
6188  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6189  * set to 32, then all 32 bits
6190  *
6191  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6192  * register is read, data in the
6193  *
6194  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6195  * transmit FIFO buffer; a write
6196  *
6197  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6198  *
6199  * Register Layout
6200  *
6201  * Bits | Access | Reset | Description
6202  * :-------|:-------|:------|:-------------------
6203  * [31:0] | RW | 0x0 | ALT_SPIM_DR15_DR15
6204  *
6205  */
6206 /*
6207  * Field : dr15
6208  *
6209  * Data Register. When writing to this register, you must right-justify the data.
6210  * Read
6211  *
6212  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6213  *
6214  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6215  * of the
6216  *
6217  * register are valid.
6218  *
6219  * Read = Receive FIFO buffer
6220  *
6221  * Write = Transmit FIFO buffer.
6222  *
6223  * Field Access Macros:
6224  *
6225  */
6226 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR15_DR15 register field. */
6227 #define ALT_SPIM_DR15_DR15_LSB 0
6228 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR15_DR15 register field. */
6229 #define ALT_SPIM_DR15_DR15_MSB 31
6230 /* The width in bits of the ALT_SPIM_DR15_DR15 register field. */
6231 #define ALT_SPIM_DR15_DR15_WIDTH 32
6232 /* The mask used to set the ALT_SPIM_DR15_DR15 register field value. */
6233 #define ALT_SPIM_DR15_DR15_SET_MSK 0xffffffff
6234 /* The mask used to clear the ALT_SPIM_DR15_DR15 register field value. */
6235 #define ALT_SPIM_DR15_DR15_CLR_MSK 0x00000000
6236 /* The reset value of the ALT_SPIM_DR15_DR15 register field. */
6237 #define ALT_SPIM_DR15_DR15_RESET 0x0
6238 /* Extracts the ALT_SPIM_DR15_DR15 field value from a register. */
6239 #define ALT_SPIM_DR15_DR15_GET(value) (((value) & 0xffffffff) >> 0)
6240 /* Produces a ALT_SPIM_DR15_DR15 register field value suitable for setting the register. */
6241 #define ALT_SPIM_DR15_DR15_SET(value) (((value) << 0) & 0xffffffff)
6242 
6243 #ifndef __ASSEMBLY__
6244 /*
6245  * WARNING: The C register and register group struct declarations are provided for
6246  * convenience and illustrative purposes. They should, however, be used with
6247  * caution as the C language standard provides no guarantees about the alignment or
6248  * atomicity of device memory accesses. The recommended practice for coding device
6249  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6250  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6251  * alt_write_dword() functions for 64 bit registers.
6252  *
6253  * The struct declaration for register ALT_SPIM_DR15.
6254  */
6255 struct ALT_SPIM_DR15_s
6256 {
6257  volatile uint32_t dr15 : 32; /* ALT_SPIM_DR15_DR15 */
6258 };
6259 
6260 /* The typedef declaration for register ALT_SPIM_DR15. */
6261 typedef struct ALT_SPIM_DR15_s ALT_SPIM_DR15_t;
6262 #endif /* __ASSEMBLY__ */
6263 
6264 /* The reset value of the ALT_SPIM_DR15 register. */
6265 #define ALT_SPIM_DR15_RESET 0x00000000
6266 /* The byte offset of the ALT_SPIM_DR15 register from the beginning of the component. */
6267 #define ALT_SPIM_DR15_OFST 0x9c
6268 /* The address of the ALT_SPIM_DR15 register. */
6269 #define ALT_SPIM_DR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR15_OFST))
6270 
6271 /*
6272  * Register : DW_apb_ssi Data Register - DR16
6273  *
6274  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6275  * read/write buffer for
6276  *
6277  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6278  * set to 32, then all 32 bits
6279  *
6280  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6281  * register is read, data in the
6282  *
6283  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6284  * transmit FIFO buffer; a write
6285  *
6286  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6287  *
6288  * Register Layout
6289  *
6290  * Bits | Access | Reset | Description
6291  * :-------|:-------|:------|:-------------------
6292  * [31:0] | RW | 0x0 | ALT_SPIM_DR16_DR16
6293  *
6294  */
6295 /*
6296  * Field : dr16
6297  *
6298  * Data Register. When writing to this register, you must right-justify the data.
6299  * Read
6300  *
6301  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6302  *
6303  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6304  * of the
6305  *
6306  * register are valid.
6307  *
6308  * Read = Receive FIFO buffer
6309  *
6310  * Write = Transmit FIFO buffer.
6311  *
6312  * Field Access Macros:
6313  *
6314  */
6315 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR16_DR16 register field. */
6316 #define ALT_SPIM_DR16_DR16_LSB 0
6317 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR16_DR16 register field. */
6318 #define ALT_SPIM_DR16_DR16_MSB 31
6319 /* The width in bits of the ALT_SPIM_DR16_DR16 register field. */
6320 #define ALT_SPIM_DR16_DR16_WIDTH 32
6321 /* The mask used to set the ALT_SPIM_DR16_DR16 register field value. */
6322 #define ALT_SPIM_DR16_DR16_SET_MSK 0xffffffff
6323 /* The mask used to clear the ALT_SPIM_DR16_DR16 register field value. */
6324 #define ALT_SPIM_DR16_DR16_CLR_MSK 0x00000000
6325 /* The reset value of the ALT_SPIM_DR16_DR16 register field. */
6326 #define ALT_SPIM_DR16_DR16_RESET 0x0
6327 /* Extracts the ALT_SPIM_DR16_DR16 field value from a register. */
6328 #define ALT_SPIM_DR16_DR16_GET(value) (((value) & 0xffffffff) >> 0)
6329 /* Produces a ALT_SPIM_DR16_DR16 register field value suitable for setting the register. */
6330 #define ALT_SPIM_DR16_DR16_SET(value) (((value) << 0) & 0xffffffff)
6331 
6332 #ifndef __ASSEMBLY__
6333 /*
6334  * WARNING: The C register and register group struct declarations are provided for
6335  * convenience and illustrative purposes. They should, however, be used with
6336  * caution as the C language standard provides no guarantees about the alignment or
6337  * atomicity of device memory accesses. The recommended practice for coding device
6338  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6339  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6340  * alt_write_dword() functions for 64 bit registers.
6341  *
6342  * The struct declaration for register ALT_SPIM_DR16.
6343  */
6344 struct ALT_SPIM_DR16_s
6345 {
6346  volatile uint32_t dr16 : 32; /* ALT_SPIM_DR16_DR16 */
6347 };
6348 
6349 /* The typedef declaration for register ALT_SPIM_DR16. */
6350 typedef struct ALT_SPIM_DR16_s ALT_SPIM_DR16_t;
6351 #endif /* __ASSEMBLY__ */
6352 
6353 /* The reset value of the ALT_SPIM_DR16 register. */
6354 #define ALT_SPIM_DR16_RESET 0x00000000
6355 /* The byte offset of the ALT_SPIM_DR16 register from the beginning of the component. */
6356 #define ALT_SPIM_DR16_OFST 0xa0
6357 /* The address of the ALT_SPIM_DR16 register. */
6358 #define ALT_SPIM_DR16_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR16_OFST))
6359 
6360 /*
6361  * Register : DW_apb_ssi Data Register - DR17
6362  *
6363  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6364  * read/write buffer for
6365  *
6366  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6367  * set to 32, then all 32 bits
6368  *
6369  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6370  * register is read, data in the
6371  *
6372  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6373  * transmit FIFO buffer; a write
6374  *
6375  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6376  *
6377  * Register Layout
6378  *
6379  * Bits | Access | Reset | Description
6380  * :-------|:-------|:------|:-------------------
6381  * [31:0] | RW | 0x0 | ALT_SPIM_DR17_DR17
6382  *
6383  */
6384 /*
6385  * Field : dr17
6386  *
6387  * Data Register. When writing to this register, you must right-justify the data.
6388  * Read
6389  *
6390  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6391  *
6392  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6393  * of the
6394  *
6395  * register are valid.
6396  *
6397  * Read = Receive FIFO buffer
6398  *
6399  * Write = Transmit FIFO buffer.
6400  *
6401  * Field Access Macros:
6402  *
6403  */
6404 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR17_DR17 register field. */
6405 #define ALT_SPIM_DR17_DR17_LSB 0
6406 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR17_DR17 register field. */
6407 #define ALT_SPIM_DR17_DR17_MSB 31
6408 /* The width in bits of the ALT_SPIM_DR17_DR17 register field. */
6409 #define ALT_SPIM_DR17_DR17_WIDTH 32
6410 /* The mask used to set the ALT_SPIM_DR17_DR17 register field value. */
6411 #define ALT_SPIM_DR17_DR17_SET_MSK 0xffffffff
6412 /* The mask used to clear the ALT_SPIM_DR17_DR17 register field value. */
6413 #define ALT_SPIM_DR17_DR17_CLR_MSK 0x00000000
6414 /* The reset value of the ALT_SPIM_DR17_DR17 register field. */
6415 #define ALT_SPIM_DR17_DR17_RESET 0x0
6416 /* Extracts the ALT_SPIM_DR17_DR17 field value from a register. */
6417 #define ALT_SPIM_DR17_DR17_GET(value) (((value) & 0xffffffff) >> 0)
6418 /* Produces a ALT_SPIM_DR17_DR17 register field value suitable for setting the register. */
6419 #define ALT_SPIM_DR17_DR17_SET(value) (((value) << 0) & 0xffffffff)
6420 
6421 #ifndef __ASSEMBLY__
6422 /*
6423  * WARNING: The C register and register group struct declarations are provided for
6424  * convenience and illustrative purposes. They should, however, be used with
6425  * caution as the C language standard provides no guarantees about the alignment or
6426  * atomicity of device memory accesses. The recommended practice for coding device
6427  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6428  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6429  * alt_write_dword() functions for 64 bit registers.
6430  *
6431  * The struct declaration for register ALT_SPIM_DR17.
6432  */
6433 struct ALT_SPIM_DR17_s
6434 {
6435  volatile uint32_t dr17 : 32; /* ALT_SPIM_DR17_DR17 */
6436 };
6437 
6438 /* The typedef declaration for register ALT_SPIM_DR17. */
6439 typedef struct ALT_SPIM_DR17_s ALT_SPIM_DR17_t;
6440 #endif /* __ASSEMBLY__ */
6441 
6442 /* The reset value of the ALT_SPIM_DR17 register. */
6443 #define ALT_SPIM_DR17_RESET 0x00000000
6444 /* The byte offset of the ALT_SPIM_DR17 register from the beginning of the component. */
6445 #define ALT_SPIM_DR17_OFST 0xa4
6446 /* The address of the ALT_SPIM_DR17 register. */
6447 #define ALT_SPIM_DR17_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR17_OFST))
6448 
6449 /*
6450  * Register : DW_apb_ssi Data Register - DR18
6451  *
6452  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6453  * read/write buffer for
6454  *
6455  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6456  * set to 32, then all 32 bits
6457  *
6458  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6459  * register is read, data in the
6460  *
6461  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6462  * transmit FIFO buffer; a write
6463  *
6464  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6465  *
6466  * Register Layout
6467  *
6468  * Bits | Access | Reset | Description
6469  * :-------|:-------|:------|:-------------------
6470  * [31:0] | RW | 0x0 | ALT_SPIM_DR18_DR18
6471  *
6472  */
6473 /*
6474  * Field : dr18
6475  *
6476  * Data Register. When writing to this register, you must right-justify the data.
6477  * Read
6478  *
6479  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6480  *
6481  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6482  * of the
6483  *
6484  * register are valid.
6485  *
6486  * Read = Receive FIFO buffer
6487  *
6488  * Write = Transmit FIFO buffer.
6489  *
6490  * Field Access Macros:
6491  *
6492  */
6493 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR18_DR18 register field. */
6494 #define ALT_SPIM_DR18_DR18_LSB 0
6495 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR18_DR18 register field. */
6496 #define ALT_SPIM_DR18_DR18_MSB 31
6497 /* The width in bits of the ALT_SPIM_DR18_DR18 register field. */
6498 #define ALT_SPIM_DR18_DR18_WIDTH 32
6499 /* The mask used to set the ALT_SPIM_DR18_DR18 register field value. */
6500 #define ALT_SPIM_DR18_DR18_SET_MSK 0xffffffff
6501 /* The mask used to clear the ALT_SPIM_DR18_DR18 register field value. */
6502 #define ALT_SPIM_DR18_DR18_CLR_MSK 0x00000000
6503 /* The reset value of the ALT_SPIM_DR18_DR18 register field. */
6504 #define ALT_SPIM_DR18_DR18_RESET 0x0
6505 /* Extracts the ALT_SPIM_DR18_DR18 field value from a register. */
6506 #define ALT_SPIM_DR18_DR18_GET(value) (((value) & 0xffffffff) >> 0)
6507 /* Produces a ALT_SPIM_DR18_DR18 register field value suitable for setting the register. */
6508 #define ALT_SPIM_DR18_DR18_SET(value) (((value) << 0) & 0xffffffff)
6509 
6510 #ifndef __ASSEMBLY__
6511 /*
6512  * WARNING: The C register and register group struct declarations are provided for
6513  * convenience and illustrative purposes. They should, however, be used with
6514  * caution as the C language standard provides no guarantees about the alignment or
6515  * atomicity of device memory accesses. The recommended practice for coding device
6516  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6517  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6518  * alt_write_dword() functions for 64 bit registers.
6519  *
6520  * The struct declaration for register ALT_SPIM_DR18.
6521  */
6522 struct ALT_SPIM_DR18_s
6523 {
6524  volatile uint32_t dr18 : 32; /* ALT_SPIM_DR18_DR18 */
6525 };
6526 
6527 /* The typedef declaration for register ALT_SPIM_DR18. */
6528 typedef struct ALT_SPIM_DR18_s ALT_SPIM_DR18_t;
6529 #endif /* __ASSEMBLY__ */
6530 
6531 /* The reset value of the ALT_SPIM_DR18 register. */
6532 #define ALT_SPIM_DR18_RESET 0x00000000
6533 /* The byte offset of the ALT_SPIM_DR18 register from the beginning of the component. */
6534 #define ALT_SPIM_DR18_OFST 0xa8
6535 /* The address of the ALT_SPIM_DR18 register. */
6536 #define ALT_SPIM_DR18_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR18_OFST))
6537 
6538 /*
6539  * Register : DW_apb_ssi Data Register - DR19
6540  *
6541  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6542  * read/write buffer for
6543  *
6544  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6545  * set to 32, then all 32 bits
6546  *
6547  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6548  * register is read, data in the
6549  *
6550  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6551  * transmit FIFO buffer; a write
6552  *
6553  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6554  *
6555  * Register Layout
6556  *
6557  * Bits | Access | Reset | Description
6558  * :-------|:-------|:------|:-------------------
6559  * [31:0] | RW | 0x0 | ALT_SPIM_DR19_DR19
6560  *
6561  */
6562 /*
6563  * Field : dr19
6564  *
6565  * Data Register. When writing to this register, you must right-justify the data.
6566  * Read
6567  *
6568  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6569  *
6570  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6571  * of the
6572  *
6573  * register are valid.
6574  *
6575  * Read = Receive FIFO buffer
6576  *
6577  * Write = Transmit FIFO buffer.
6578  *
6579  * Field Access Macros:
6580  *
6581  */
6582 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR19_DR19 register field. */
6583 #define ALT_SPIM_DR19_DR19_LSB 0
6584 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR19_DR19 register field. */
6585 #define ALT_SPIM_DR19_DR19_MSB 31
6586 /* The width in bits of the ALT_SPIM_DR19_DR19 register field. */
6587 #define ALT_SPIM_DR19_DR19_WIDTH 32
6588 /* The mask used to set the ALT_SPIM_DR19_DR19 register field value. */
6589 #define ALT_SPIM_DR19_DR19_SET_MSK 0xffffffff
6590 /* The mask used to clear the ALT_SPIM_DR19_DR19 register field value. */
6591 #define ALT_SPIM_DR19_DR19_CLR_MSK 0x00000000
6592 /* The reset value of the ALT_SPIM_DR19_DR19 register field. */
6593 #define ALT_SPIM_DR19_DR19_RESET 0x0
6594 /* Extracts the ALT_SPIM_DR19_DR19 field value from a register. */
6595 #define ALT_SPIM_DR19_DR19_GET(value) (((value) & 0xffffffff) >> 0)
6596 /* Produces a ALT_SPIM_DR19_DR19 register field value suitable for setting the register. */
6597 #define ALT_SPIM_DR19_DR19_SET(value) (((value) << 0) & 0xffffffff)
6598 
6599 #ifndef __ASSEMBLY__
6600 /*
6601  * WARNING: The C register and register group struct declarations are provided for
6602  * convenience and illustrative purposes. They should, however, be used with
6603  * caution as the C language standard provides no guarantees about the alignment or
6604  * atomicity of device memory accesses. The recommended practice for coding device
6605  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6606  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6607  * alt_write_dword() functions for 64 bit registers.
6608  *
6609  * The struct declaration for register ALT_SPIM_DR19.
6610  */
6611 struct ALT_SPIM_DR19_s
6612 {
6613  volatile uint32_t dr19 : 32; /* ALT_SPIM_DR19_DR19 */
6614 };
6615 
6616 /* The typedef declaration for register ALT_SPIM_DR19. */
6617 typedef struct ALT_SPIM_DR19_s ALT_SPIM_DR19_t;
6618 #endif /* __ASSEMBLY__ */
6619 
6620 /* The reset value of the ALT_SPIM_DR19 register. */
6621 #define ALT_SPIM_DR19_RESET 0x00000000
6622 /* The byte offset of the ALT_SPIM_DR19 register from the beginning of the component. */
6623 #define ALT_SPIM_DR19_OFST 0xac
6624 /* The address of the ALT_SPIM_DR19 register. */
6625 #define ALT_SPIM_DR19_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR19_OFST))
6626 
6627 /*
6628  * Register : DW_apb_ssi Data Register - DR20
6629  *
6630  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6631  * read/write buffer for
6632  *
6633  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6634  * set to 32, then all 32 bits
6635  *
6636  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6637  * register is read, data in the
6638  *
6639  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6640  * transmit FIFO buffer; a write
6641  *
6642  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6643  *
6644  * Register Layout
6645  *
6646  * Bits | Access | Reset | Description
6647  * :-------|:-------|:------|:-------------------
6648  * [31:0] | RW | 0x0 | ALT_SPIM_DR20_DR20
6649  *
6650  */
6651 /*
6652  * Field : dr20
6653  *
6654  * Data Register. When writing to this register, you must right-justify the data.
6655  * Read
6656  *
6657  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6658  *
6659  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6660  * of the
6661  *
6662  * register are valid.
6663  *
6664  * Read = Receive FIFO buffer
6665  *
6666  * Write = Transmit FIFO buffer.
6667  *
6668  * Field Access Macros:
6669  *
6670  */
6671 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR20_DR20 register field. */
6672 #define ALT_SPIM_DR20_DR20_LSB 0
6673 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR20_DR20 register field. */
6674 #define ALT_SPIM_DR20_DR20_MSB 31
6675 /* The width in bits of the ALT_SPIM_DR20_DR20 register field. */
6676 #define ALT_SPIM_DR20_DR20_WIDTH 32
6677 /* The mask used to set the ALT_SPIM_DR20_DR20 register field value. */
6678 #define ALT_SPIM_DR20_DR20_SET_MSK 0xffffffff
6679 /* The mask used to clear the ALT_SPIM_DR20_DR20 register field value. */
6680 #define ALT_SPIM_DR20_DR20_CLR_MSK 0x00000000
6681 /* The reset value of the ALT_SPIM_DR20_DR20 register field. */
6682 #define ALT_SPIM_DR20_DR20_RESET 0x0
6683 /* Extracts the ALT_SPIM_DR20_DR20 field value from a register. */
6684 #define ALT_SPIM_DR20_DR20_GET(value) (((value) & 0xffffffff) >> 0)
6685 /* Produces a ALT_SPIM_DR20_DR20 register field value suitable for setting the register. */
6686 #define ALT_SPIM_DR20_DR20_SET(value) (((value) << 0) & 0xffffffff)
6687 
6688 #ifndef __ASSEMBLY__
6689 /*
6690  * WARNING: The C register and register group struct declarations are provided for
6691  * convenience and illustrative purposes. They should, however, be used with
6692  * caution as the C language standard provides no guarantees about the alignment or
6693  * atomicity of device memory accesses. The recommended practice for coding device
6694  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6695  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6696  * alt_write_dword() functions for 64 bit registers.
6697  *
6698  * The struct declaration for register ALT_SPIM_DR20.
6699  */
6700 struct ALT_SPIM_DR20_s
6701 {
6702  volatile uint32_t dr20 : 32; /* ALT_SPIM_DR20_DR20 */
6703 };
6704 
6705 /* The typedef declaration for register ALT_SPIM_DR20. */
6706 typedef struct ALT_SPIM_DR20_s ALT_SPIM_DR20_t;
6707 #endif /* __ASSEMBLY__ */
6708 
6709 /* The reset value of the ALT_SPIM_DR20 register. */
6710 #define ALT_SPIM_DR20_RESET 0x00000000
6711 /* The byte offset of the ALT_SPIM_DR20 register from the beginning of the component. */
6712 #define ALT_SPIM_DR20_OFST 0xb0
6713 /* The address of the ALT_SPIM_DR20 register. */
6714 #define ALT_SPIM_DR20_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR20_OFST))
6715 
6716 /*
6717  * Register : DW_apb_ssi Data Register - DR21
6718  *
6719  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6720  * read/write buffer for
6721  *
6722  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6723  * set to 32, then all 32 bits
6724  *
6725  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6726  * register is read, data in the
6727  *
6728  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6729  * transmit FIFO buffer; a write
6730  *
6731  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6732  *
6733  * Register Layout
6734  *
6735  * Bits | Access | Reset | Description
6736  * :-------|:-------|:------|:-------------------
6737  * [31:0] | RW | 0x0 | ALT_SPIM_DR21_DR21
6738  *
6739  */
6740 /*
6741  * Field : dr21
6742  *
6743  * Data Register. When writing to this register, you must right-justify the data.
6744  * Read
6745  *
6746  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6747  *
6748  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6749  * of the
6750  *
6751  * register are valid.
6752  *
6753  * Read = Receive FIFO buffer
6754  *
6755  * Write = Transmit FIFO buffer.
6756  *
6757  * Field Access Macros:
6758  *
6759  */
6760 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR21_DR21 register field. */
6761 #define ALT_SPIM_DR21_DR21_LSB 0
6762 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR21_DR21 register field. */
6763 #define ALT_SPIM_DR21_DR21_MSB 31
6764 /* The width in bits of the ALT_SPIM_DR21_DR21 register field. */
6765 #define ALT_SPIM_DR21_DR21_WIDTH 32
6766 /* The mask used to set the ALT_SPIM_DR21_DR21 register field value. */
6767 #define ALT_SPIM_DR21_DR21_SET_MSK 0xffffffff
6768 /* The mask used to clear the ALT_SPIM_DR21_DR21 register field value. */
6769 #define ALT_SPIM_DR21_DR21_CLR_MSK 0x00000000
6770 /* The reset value of the ALT_SPIM_DR21_DR21 register field. */
6771 #define ALT_SPIM_DR21_DR21_RESET 0x0
6772 /* Extracts the ALT_SPIM_DR21_DR21 field value from a register. */
6773 #define ALT_SPIM_DR21_DR21_GET(value) (((value) & 0xffffffff) >> 0)
6774 /* Produces a ALT_SPIM_DR21_DR21 register field value suitable for setting the register. */
6775 #define ALT_SPIM_DR21_DR21_SET(value) (((value) << 0) & 0xffffffff)
6776 
6777 #ifndef __ASSEMBLY__
6778 /*
6779  * WARNING: The C register and register group struct declarations are provided for
6780  * convenience and illustrative purposes. They should, however, be used with
6781  * caution as the C language standard provides no guarantees about the alignment or
6782  * atomicity of device memory accesses. The recommended practice for coding device
6783  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6784  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6785  * alt_write_dword() functions for 64 bit registers.
6786  *
6787  * The struct declaration for register ALT_SPIM_DR21.
6788  */
6789 struct ALT_SPIM_DR21_s
6790 {
6791  volatile uint32_t dr21 : 32; /* ALT_SPIM_DR21_DR21 */
6792 };
6793 
6794 /* The typedef declaration for register ALT_SPIM_DR21. */
6795 typedef struct ALT_SPIM_DR21_s ALT_SPIM_DR21_t;
6796 #endif /* __ASSEMBLY__ */
6797 
6798 /* The reset value of the ALT_SPIM_DR21 register. */
6799 #define ALT_SPIM_DR21_RESET 0x00000000
6800 /* The byte offset of the ALT_SPIM_DR21 register from the beginning of the component. */
6801 #define ALT_SPIM_DR21_OFST 0xb4
6802 /* The address of the ALT_SPIM_DR21 register. */
6803 #define ALT_SPIM_DR21_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR21_OFST))
6804 
6805 /*
6806  * Register : DW_apb_ssi Data Register - DR22
6807  *
6808  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6809  * read/write buffer for
6810  *
6811  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6812  * set to 32, then all 32 bits
6813  *
6814  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6815  * register is read, data in the
6816  *
6817  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6818  * transmit FIFO buffer; a write
6819  *
6820  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6821  *
6822  * Register Layout
6823  *
6824  * Bits | Access | Reset | Description
6825  * :-------|:-------|:------|:-------------------
6826  * [31:0] | RW | 0x0 | ALT_SPIM_DR22_DR22
6827  *
6828  */
6829 /*
6830  * Field : dr22
6831  *
6832  * Data Register. When writing to this register, you must right-justify the data.
6833  * Read
6834  *
6835  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6836  *
6837  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6838  * of the
6839  *
6840  * register are valid.
6841  *
6842  * Read = Receive FIFO buffer
6843  *
6844  * Write = Transmit FIFO buffer.
6845  *
6846  * Field Access Macros:
6847  *
6848  */
6849 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR22_DR22 register field. */
6850 #define ALT_SPIM_DR22_DR22_LSB 0
6851 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR22_DR22 register field. */
6852 #define ALT_SPIM_DR22_DR22_MSB 31
6853 /* The width in bits of the ALT_SPIM_DR22_DR22 register field. */
6854 #define ALT_SPIM_DR22_DR22_WIDTH 32
6855 /* The mask used to set the ALT_SPIM_DR22_DR22 register field value. */
6856 #define ALT_SPIM_DR22_DR22_SET_MSK 0xffffffff
6857 /* The mask used to clear the ALT_SPIM_DR22_DR22 register field value. */
6858 #define ALT_SPIM_DR22_DR22_CLR_MSK 0x00000000
6859 /* The reset value of the ALT_SPIM_DR22_DR22 register field. */
6860 #define ALT_SPIM_DR22_DR22_RESET 0x0
6861 /* Extracts the ALT_SPIM_DR22_DR22 field value from a register. */
6862 #define ALT_SPIM_DR22_DR22_GET(value) (((value) & 0xffffffff) >> 0)
6863 /* Produces a ALT_SPIM_DR22_DR22 register field value suitable for setting the register. */
6864 #define ALT_SPIM_DR22_DR22_SET(value) (((value) << 0) & 0xffffffff)
6865 
6866 #ifndef __ASSEMBLY__
6867 /*
6868  * WARNING: The C register and register group struct declarations are provided for
6869  * convenience and illustrative purposes. They should, however, be used with
6870  * caution as the C language standard provides no guarantees about the alignment or
6871  * atomicity of device memory accesses. The recommended practice for coding device
6872  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6873  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6874  * alt_write_dword() functions for 64 bit registers.
6875  *
6876  * The struct declaration for register ALT_SPIM_DR22.
6877  */
6878 struct ALT_SPIM_DR22_s
6879 {
6880  volatile uint32_t dr22 : 32; /* ALT_SPIM_DR22_DR22 */
6881 };
6882 
6883 /* The typedef declaration for register ALT_SPIM_DR22. */
6884 typedef struct ALT_SPIM_DR22_s ALT_SPIM_DR22_t;
6885 #endif /* __ASSEMBLY__ */
6886 
6887 /* The reset value of the ALT_SPIM_DR22 register. */
6888 #define ALT_SPIM_DR22_RESET 0x00000000
6889 /* The byte offset of the ALT_SPIM_DR22 register from the beginning of the component. */
6890 #define ALT_SPIM_DR22_OFST 0xb8
6891 /* The address of the ALT_SPIM_DR22 register. */
6892 #define ALT_SPIM_DR22_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR22_OFST))
6893 
6894 /*
6895  * Register : DW_apb_ssi Data Register - DR23
6896  *
6897  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6898  * read/write buffer for
6899  *
6900  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6901  * set to 32, then all 32 bits
6902  *
6903  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6904  * register is read, data in the
6905  *
6906  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6907  * transmit FIFO buffer; a write
6908  *
6909  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6910  *
6911  * Register Layout
6912  *
6913  * Bits | Access | Reset | Description
6914  * :-------|:-------|:------|:-------------------
6915  * [31:0] | RW | 0x0 | ALT_SPIM_DR23_DR23
6916  *
6917  */
6918 /*
6919  * Field : dr23
6920  *
6921  * Data Register. When writing to this register, you must right-justify the data.
6922  * Read
6923  *
6924  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
6925  *
6926  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
6927  * of the
6928  *
6929  * register are valid.
6930  *
6931  * Read = Receive FIFO buffer
6932  *
6933  * Write = Transmit FIFO buffer.
6934  *
6935  * Field Access Macros:
6936  *
6937  */
6938 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR23_DR23 register field. */
6939 #define ALT_SPIM_DR23_DR23_LSB 0
6940 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR23_DR23 register field. */
6941 #define ALT_SPIM_DR23_DR23_MSB 31
6942 /* The width in bits of the ALT_SPIM_DR23_DR23 register field. */
6943 #define ALT_SPIM_DR23_DR23_WIDTH 32
6944 /* The mask used to set the ALT_SPIM_DR23_DR23 register field value. */
6945 #define ALT_SPIM_DR23_DR23_SET_MSK 0xffffffff
6946 /* The mask used to clear the ALT_SPIM_DR23_DR23 register field value. */
6947 #define ALT_SPIM_DR23_DR23_CLR_MSK 0x00000000
6948 /* The reset value of the ALT_SPIM_DR23_DR23 register field. */
6949 #define ALT_SPIM_DR23_DR23_RESET 0x0
6950 /* Extracts the ALT_SPIM_DR23_DR23 field value from a register. */
6951 #define ALT_SPIM_DR23_DR23_GET(value) (((value) & 0xffffffff) >> 0)
6952 /* Produces a ALT_SPIM_DR23_DR23 register field value suitable for setting the register. */
6953 #define ALT_SPIM_DR23_DR23_SET(value) (((value) << 0) & 0xffffffff)
6954 
6955 #ifndef __ASSEMBLY__
6956 /*
6957  * WARNING: The C register and register group struct declarations are provided for
6958  * convenience and illustrative purposes. They should, however, be used with
6959  * caution as the C language standard provides no guarantees about the alignment or
6960  * atomicity of device memory accesses. The recommended practice for coding device
6961  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6962  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6963  * alt_write_dword() functions for 64 bit registers.
6964  *
6965  * The struct declaration for register ALT_SPIM_DR23.
6966  */
6967 struct ALT_SPIM_DR23_s
6968 {
6969  volatile uint32_t dr23 : 32; /* ALT_SPIM_DR23_DR23 */
6970 };
6971 
6972 /* The typedef declaration for register ALT_SPIM_DR23. */
6973 typedef struct ALT_SPIM_DR23_s ALT_SPIM_DR23_t;
6974 #endif /* __ASSEMBLY__ */
6975 
6976 /* The reset value of the ALT_SPIM_DR23 register. */
6977 #define ALT_SPIM_DR23_RESET 0x00000000
6978 /* The byte offset of the ALT_SPIM_DR23 register from the beginning of the component. */
6979 #define ALT_SPIM_DR23_OFST 0xbc
6980 /* The address of the ALT_SPIM_DR23 register. */
6981 #define ALT_SPIM_DR23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR23_OFST))
6982 
6983 /*
6984  * Register : DW_apb_ssi Data Register - DR24
6985  *
6986  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
6987  * read/write buffer for
6988  *
6989  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
6990  * set to 32, then all 32 bits
6991  *
6992  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
6993  * register is read, data in the
6994  *
6995  * receive FIFO buffer is accessed. When it is written to, data are moved into the
6996  * transmit FIFO buffer; a write
6997  *
6998  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
6999  *
7000  * Register Layout
7001  *
7002  * Bits | Access | Reset | Description
7003  * :-------|:-------|:------|:-------------------
7004  * [31:0] | RW | 0x0 | ALT_SPIM_DR24_DR24
7005  *
7006  */
7007 /*
7008  * Field : dr24
7009  *
7010  * Data Register. When writing to this register, you must right-justify the data.
7011  * Read
7012  *
7013  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7014  *
7015  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7016  * of the
7017  *
7018  * register are valid.
7019  *
7020  * Read = Receive FIFO buffer
7021  *
7022  * Write = Transmit FIFO buffer.
7023  *
7024  * Field Access Macros:
7025  *
7026  */
7027 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR24_DR24 register field. */
7028 #define ALT_SPIM_DR24_DR24_LSB 0
7029 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR24_DR24 register field. */
7030 #define ALT_SPIM_DR24_DR24_MSB 31
7031 /* The width in bits of the ALT_SPIM_DR24_DR24 register field. */
7032 #define ALT_SPIM_DR24_DR24_WIDTH 32
7033 /* The mask used to set the ALT_SPIM_DR24_DR24 register field value. */
7034 #define ALT_SPIM_DR24_DR24_SET_MSK 0xffffffff
7035 /* The mask used to clear the ALT_SPIM_DR24_DR24 register field value. */
7036 #define ALT_SPIM_DR24_DR24_CLR_MSK 0x00000000
7037 /* The reset value of the ALT_SPIM_DR24_DR24 register field. */
7038 #define ALT_SPIM_DR24_DR24_RESET 0x0
7039 /* Extracts the ALT_SPIM_DR24_DR24 field value from a register. */
7040 #define ALT_SPIM_DR24_DR24_GET(value) (((value) & 0xffffffff) >> 0)
7041 /* Produces a ALT_SPIM_DR24_DR24 register field value suitable for setting the register. */
7042 #define ALT_SPIM_DR24_DR24_SET(value) (((value) << 0) & 0xffffffff)
7043 
7044 #ifndef __ASSEMBLY__
7045 /*
7046  * WARNING: The C register and register group struct declarations are provided for
7047  * convenience and illustrative purposes. They should, however, be used with
7048  * caution as the C language standard provides no guarantees about the alignment or
7049  * atomicity of device memory accesses. The recommended practice for coding device
7050  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7051  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7052  * alt_write_dword() functions for 64 bit registers.
7053  *
7054  * The struct declaration for register ALT_SPIM_DR24.
7055  */
7056 struct ALT_SPIM_DR24_s
7057 {
7058  volatile uint32_t dr24 : 32; /* ALT_SPIM_DR24_DR24 */
7059 };
7060 
7061 /* The typedef declaration for register ALT_SPIM_DR24. */
7062 typedef struct ALT_SPIM_DR24_s ALT_SPIM_DR24_t;
7063 #endif /* __ASSEMBLY__ */
7064 
7065 /* The reset value of the ALT_SPIM_DR24 register. */
7066 #define ALT_SPIM_DR24_RESET 0x00000000
7067 /* The byte offset of the ALT_SPIM_DR24 register from the beginning of the component. */
7068 #define ALT_SPIM_DR24_OFST 0xc0
7069 /* The address of the ALT_SPIM_DR24 register. */
7070 #define ALT_SPIM_DR24_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR24_OFST))
7071 
7072 /*
7073  * Register : DW_apb_ssi Data Register - DR25
7074  *
7075  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7076  * read/write buffer for
7077  *
7078  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7079  * set to 32, then all 32 bits
7080  *
7081  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7082  * register is read, data in the
7083  *
7084  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7085  * transmit FIFO buffer; a write
7086  *
7087  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7088  *
7089  * Register Layout
7090  *
7091  * Bits | Access | Reset | Description
7092  * :-------|:-------|:------|:-------------------
7093  * [31:0] | RW | 0x0 | ALT_SPIM_DR25_DR25
7094  *
7095  */
7096 /*
7097  * Field : dr25
7098  *
7099  * Data Register. When writing to this register, you must right-justify the data.
7100  * Read
7101  *
7102  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7103  *
7104  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7105  * of the
7106  *
7107  * register are valid.
7108  *
7109  * Read = Receive FIFO buffer
7110  *
7111  * Write = Transmit FIFO buffer.
7112  *
7113  * Field Access Macros:
7114  *
7115  */
7116 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR25_DR25 register field. */
7117 #define ALT_SPIM_DR25_DR25_LSB 0
7118 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR25_DR25 register field. */
7119 #define ALT_SPIM_DR25_DR25_MSB 31
7120 /* The width in bits of the ALT_SPIM_DR25_DR25 register field. */
7121 #define ALT_SPIM_DR25_DR25_WIDTH 32
7122 /* The mask used to set the ALT_SPIM_DR25_DR25 register field value. */
7123 #define ALT_SPIM_DR25_DR25_SET_MSK 0xffffffff
7124 /* The mask used to clear the ALT_SPIM_DR25_DR25 register field value. */
7125 #define ALT_SPIM_DR25_DR25_CLR_MSK 0x00000000
7126 /* The reset value of the ALT_SPIM_DR25_DR25 register field. */
7127 #define ALT_SPIM_DR25_DR25_RESET 0x0
7128 /* Extracts the ALT_SPIM_DR25_DR25 field value from a register. */
7129 #define ALT_SPIM_DR25_DR25_GET(value) (((value) & 0xffffffff) >> 0)
7130 /* Produces a ALT_SPIM_DR25_DR25 register field value suitable for setting the register. */
7131 #define ALT_SPIM_DR25_DR25_SET(value) (((value) << 0) & 0xffffffff)
7132 
7133 #ifndef __ASSEMBLY__
7134 /*
7135  * WARNING: The C register and register group struct declarations are provided for
7136  * convenience and illustrative purposes. They should, however, be used with
7137  * caution as the C language standard provides no guarantees about the alignment or
7138  * atomicity of device memory accesses. The recommended practice for coding device
7139  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7140  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7141  * alt_write_dword() functions for 64 bit registers.
7142  *
7143  * The struct declaration for register ALT_SPIM_DR25.
7144  */
7145 struct ALT_SPIM_DR25_s
7146 {
7147  volatile uint32_t dr25 : 32; /* ALT_SPIM_DR25_DR25 */
7148 };
7149 
7150 /* The typedef declaration for register ALT_SPIM_DR25. */
7151 typedef struct ALT_SPIM_DR25_s ALT_SPIM_DR25_t;
7152 #endif /* __ASSEMBLY__ */
7153 
7154 /* The reset value of the ALT_SPIM_DR25 register. */
7155 #define ALT_SPIM_DR25_RESET 0x00000000
7156 /* The byte offset of the ALT_SPIM_DR25 register from the beginning of the component. */
7157 #define ALT_SPIM_DR25_OFST 0xc4
7158 /* The address of the ALT_SPIM_DR25 register. */
7159 #define ALT_SPIM_DR25_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR25_OFST))
7160 
7161 /*
7162  * Register : DW_apb_ssi Data Register - DR26
7163  *
7164  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7165  * read/write buffer for
7166  *
7167  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7168  * set to 32, then all 32 bits
7169  *
7170  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7171  * register is read, data in the
7172  *
7173  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7174  * transmit FIFO buffer; a write
7175  *
7176  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7177  *
7178  * Register Layout
7179  *
7180  * Bits | Access | Reset | Description
7181  * :-------|:-------|:------|:-------------------
7182  * [31:0] | RW | 0x0 | ALT_SPIM_DR26_DR26
7183  *
7184  */
7185 /*
7186  * Field : dr26
7187  *
7188  * Data Register. When writing to this register, you must right-justify the data.
7189  * Read
7190  *
7191  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7192  *
7193  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7194  * of the
7195  *
7196  * register are valid.
7197  *
7198  * Read = Receive FIFO buffer
7199  *
7200  * Write = Transmit FIFO buffer.
7201  *
7202  * Field Access Macros:
7203  *
7204  */
7205 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR26_DR26 register field. */
7206 #define ALT_SPIM_DR26_DR26_LSB 0
7207 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR26_DR26 register field. */
7208 #define ALT_SPIM_DR26_DR26_MSB 31
7209 /* The width in bits of the ALT_SPIM_DR26_DR26 register field. */
7210 #define ALT_SPIM_DR26_DR26_WIDTH 32
7211 /* The mask used to set the ALT_SPIM_DR26_DR26 register field value. */
7212 #define ALT_SPIM_DR26_DR26_SET_MSK 0xffffffff
7213 /* The mask used to clear the ALT_SPIM_DR26_DR26 register field value. */
7214 #define ALT_SPIM_DR26_DR26_CLR_MSK 0x00000000
7215 /* The reset value of the ALT_SPIM_DR26_DR26 register field. */
7216 #define ALT_SPIM_DR26_DR26_RESET 0x0
7217 /* Extracts the ALT_SPIM_DR26_DR26 field value from a register. */
7218 #define ALT_SPIM_DR26_DR26_GET(value) (((value) & 0xffffffff) >> 0)
7219 /* Produces a ALT_SPIM_DR26_DR26 register field value suitable for setting the register. */
7220 #define ALT_SPIM_DR26_DR26_SET(value) (((value) << 0) & 0xffffffff)
7221 
7222 #ifndef __ASSEMBLY__
7223 /*
7224  * WARNING: The C register and register group struct declarations are provided for
7225  * convenience and illustrative purposes. They should, however, be used with
7226  * caution as the C language standard provides no guarantees about the alignment or
7227  * atomicity of device memory accesses. The recommended practice for coding device
7228  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7229  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7230  * alt_write_dword() functions for 64 bit registers.
7231  *
7232  * The struct declaration for register ALT_SPIM_DR26.
7233  */
7234 struct ALT_SPIM_DR26_s
7235 {
7236  volatile uint32_t dr26 : 32; /* ALT_SPIM_DR26_DR26 */
7237 };
7238 
7239 /* The typedef declaration for register ALT_SPIM_DR26. */
7240 typedef struct ALT_SPIM_DR26_s ALT_SPIM_DR26_t;
7241 #endif /* __ASSEMBLY__ */
7242 
7243 /* The reset value of the ALT_SPIM_DR26 register. */
7244 #define ALT_SPIM_DR26_RESET 0x00000000
7245 /* The byte offset of the ALT_SPIM_DR26 register from the beginning of the component. */
7246 #define ALT_SPIM_DR26_OFST 0xc8
7247 /* The address of the ALT_SPIM_DR26 register. */
7248 #define ALT_SPIM_DR26_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR26_OFST))
7249 
7250 /*
7251  * Register : DW_apb_ssi Data Register - DR27
7252  *
7253  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7254  * read/write buffer for
7255  *
7256  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7257  * set to 32, then all 32 bits
7258  *
7259  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7260  * register is read, data in the
7261  *
7262  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7263  * transmit FIFO buffer; a write
7264  *
7265  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7266  *
7267  * Register Layout
7268  *
7269  * Bits | Access | Reset | Description
7270  * :-------|:-------|:------|:-------------------
7271  * [31:0] | RW | 0x0 | ALT_SPIM_DR27_DR27
7272  *
7273  */
7274 /*
7275  * Field : dr27
7276  *
7277  * Data Register. When writing to this register, you must right-justify the data.
7278  * Read
7279  *
7280  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7281  *
7282  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7283  * of the
7284  *
7285  * register are valid.
7286  *
7287  * Read = Receive FIFO buffer
7288  *
7289  * Write = Transmit FIFO buffer.
7290  *
7291  * Field Access Macros:
7292  *
7293  */
7294 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR27_DR27 register field. */
7295 #define ALT_SPIM_DR27_DR27_LSB 0
7296 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR27_DR27 register field. */
7297 #define ALT_SPIM_DR27_DR27_MSB 31
7298 /* The width in bits of the ALT_SPIM_DR27_DR27 register field. */
7299 #define ALT_SPIM_DR27_DR27_WIDTH 32
7300 /* The mask used to set the ALT_SPIM_DR27_DR27 register field value. */
7301 #define ALT_SPIM_DR27_DR27_SET_MSK 0xffffffff
7302 /* The mask used to clear the ALT_SPIM_DR27_DR27 register field value. */
7303 #define ALT_SPIM_DR27_DR27_CLR_MSK 0x00000000
7304 /* The reset value of the ALT_SPIM_DR27_DR27 register field. */
7305 #define ALT_SPIM_DR27_DR27_RESET 0x0
7306 /* Extracts the ALT_SPIM_DR27_DR27 field value from a register. */
7307 #define ALT_SPIM_DR27_DR27_GET(value) (((value) & 0xffffffff) >> 0)
7308 /* Produces a ALT_SPIM_DR27_DR27 register field value suitable for setting the register. */
7309 #define ALT_SPIM_DR27_DR27_SET(value) (((value) << 0) & 0xffffffff)
7310 
7311 #ifndef __ASSEMBLY__
7312 /*
7313  * WARNING: The C register and register group struct declarations are provided for
7314  * convenience and illustrative purposes. They should, however, be used with
7315  * caution as the C language standard provides no guarantees about the alignment or
7316  * atomicity of device memory accesses. The recommended practice for coding device
7317  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7318  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7319  * alt_write_dword() functions for 64 bit registers.
7320  *
7321  * The struct declaration for register ALT_SPIM_DR27.
7322  */
7323 struct ALT_SPIM_DR27_s
7324 {
7325  volatile uint32_t dr27 : 32; /* ALT_SPIM_DR27_DR27 */
7326 };
7327 
7328 /* The typedef declaration for register ALT_SPIM_DR27. */
7329 typedef struct ALT_SPIM_DR27_s ALT_SPIM_DR27_t;
7330 #endif /* __ASSEMBLY__ */
7331 
7332 /* The reset value of the ALT_SPIM_DR27 register. */
7333 #define ALT_SPIM_DR27_RESET 0x00000000
7334 /* The byte offset of the ALT_SPIM_DR27 register from the beginning of the component. */
7335 #define ALT_SPIM_DR27_OFST 0xcc
7336 /* The address of the ALT_SPIM_DR27 register. */
7337 #define ALT_SPIM_DR27_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR27_OFST))
7338 
7339 /*
7340  * Register : DW_apb_ssi Data Register - DR28
7341  *
7342  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7343  * read/write buffer for
7344  *
7345  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7346  * set to 32, then all 32 bits
7347  *
7348  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7349  * register is read, data in the
7350  *
7351  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7352  * transmit FIFO buffer; a write
7353  *
7354  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7355  *
7356  * Register Layout
7357  *
7358  * Bits | Access | Reset | Description
7359  * :-------|:-------|:------|:-------------------
7360  * [31:0] | RW | 0x0 | ALT_SPIM_DR28_DR28
7361  *
7362  */
7363 /*
7364  * Field : dr28
7365  *
7366  * Data Register. When writing to this register, you must right-justify the data.
7367  * Read
7368  *
7369  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7370  *
7371  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7372  * of the
7373  *
7374  * register are valid.
7375  *
7376  * Read = Receive FIFO buffer
7377  *
7378  * Write = Transmit FIFO buffer.
7379  *
7380  * Field Access Macros:
7381  *
7382  */
7383 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR28_DR28 register field. */
7384 #define ALT_SPIM_DR28_DR28_LSB 0
7385 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR28_DR28 register field. */
7386 #define ALT_SPIM_DR28_DR28_MSB 31
7387 /* The width in bits of the ALT_SPIM_DR28_DR28 register field. */
7388 #define ALT_SPIM_DR28_DR28_WIDTH 32
7389 /* The mask used to set the ALT_SPIM_DR28_DR28 register field value. */
7390 #define ALT_SPIM_DR28_DR28_SET_MSK 0xffffffff
7391 /* The mask used to clear the ALT_SPIM_DR28_DR28 register field value. */
7392 #define ALT_SPIM_DR28_DR28_CLR_MSK 0x00000000
7393 /* The reset value of the ALT_SPIM_DR28_DR28 register field. */
7394 #define ALT_SPIM_DR28_DR28_RESET 0x0
7395 /* Extracts the ALT_SPIM_DR28_DR28 field value from a register. */
7396 #define ALT_SPIM_DR28_DR28_GET(value) (((value) & 0xffffffff) >> 0)
7397 /* Produces a ALT_SPIM_DR28_DR28 register field value suitable for setting the register. */
7398 #define ALT_SPIM_DR28_DR28_SET(value) (((value) << 0) & 0xffffffff)
7399 
7400 #ifndef __ASSEMBLY__
7401 /*
7402  * WARNING: The C register and register group struct declarations are provided for
7403  * convenience and illustrative purposes. They should, however, be used with
7404  * caution as the C language standard provides no guarantees about the alignment or
7405  * atomicity of device memory accesses. The recommended practice for coding device
7406  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7407  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7408  * alt_write_dword() functions for 64 bit registers.
7409  *
7410  * The struct declaration for register ALT_SPIM_DR28.
7411  */
7412 struct ALT_SPIM_DR28_s
7413 {
7414  volatile uint32_t dr28 : 32; /* ALT_SPIM_DR28_DR28 */
7415 };
7416 
7417 /* The typedef declaration for register ALT_SPIM_DR28. */
7418 typedef struct ALT_SPIM_DR28_s ALT_SPIM_DR28_t;
7419 #endif /* __ASSEMBLY__ */
7420 
7421 /* The reset value of the ALT_SPIM_DR28 register. */
7422 #define ALT_SPIM_DR28_RESET 0x00000000
7423 /* The byte offset of the ALT_SPIM_DR28 register from the beginning of the component. */
7424 #define ALT_SPIM_DR28_OFST 0xd0
7425 /* The address of the ALT_SPIM_DR28 register. */
7426 #define ALT_SPIM_DR28_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR28_OFST))
7427 
7428 /*
7429  * Register : DW_apb_ssi Data Register - DR29
7430  *
7431  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7432  * read/write buffer for
7433  *
7434  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7435  * set to 32, then all 32 bits
7436  *
7437  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7438  * register is read, data in the
7439  *
7440  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7441  * transmit FIFO buffer; a write
7442  *
7443  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7444  *
7445  * Register Layout
7446  *
7447  * Bits | Access | Reset | Description
7448  * :-------|:-------|:------|:-------------------
7449  * [31:0] | RW | 0x0 | ALT_SPIM_DR29_DR29
7450  *
7451  */
7452 /*
7453  * Field : dr29
7454  *
7455  * Data Register. When writing to this register, you must right-justify the data.
7456  * Read
7457  *
7458  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7459  *
7460  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7461  * of the
7462  *
7463  * register are valid.
7464  *
7465  * Read = Receive FIFO buffer
7466  *
7467  * Write = Transmit FIFO buffer.
7468  *
7469  * Field Access Macros:
7470  *
7471  */
7472 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR29_DR29 register field. */
7473 #define ALT_SPIM_DR29_DR29_LSB 0
7474 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR29_DR29 register field. */
7475 #define ALT_SPIM_DR29_DR29_MSB 31
7476 /* The width in bits of the ALT_SPIM_DR29_DR29 register field. */
7477 #define ALT_SPIM_DR29_DR29_WIDTH 32
7478 /* The mask used to set the ALT_SPIM_DR29_DR29 register field value. */
7479 #define ALT_SPIM_DR29_DR29_SET_MSK 0xffffffff
7480 /* The mask used to clear the ALT_SPIM_DR29_DR29 register field value. */
7481 #define ALT_SPIM_DR29_DR29_CLR_MSK 0x00000000
7482 /* The reset value of the ALT_SPIM_DR29_DR29 register field. */
7483 #define ALT_SPIM_DR29_DR29_RESET 0x0
7484 /* Extracts the ALT_SPIM_DR29_DR29 field value from a register. */
7485 #define ALT_SPIM_DR29_DR29_GET(value) (((value) & 0xffffffff) >> 0)
7486 /* Produces a ALT_SPIM_DR29_DR29 register field value suitable for setting the register. */
7487 #define ALT_SPIM_DR29_DR29_SET(value) (((value) << 0) & 0xffffffff)
7488 
7489 #ifndef __ASSEMBLY__
7490 /*
7491  * WARNING: The C register and register group struct declarations are provided for
7492  * convenience and illustrative purposes. They should, however, be used with
7493  * caution as the C language standard provides no guarantees about the alignment or
7494  * atomicity of device memory accesses. The recommended practice for coding device
7495  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7496  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7497  * alt_write_dword() functions for 64 bit registers.
7498  *
7499  * The struct declaration for register ALT_SPIM_DR29.
7500  */
7501 struct ALT_SPIM_DR29_s
7502 {
7503  volatile uint32_t dr29 : 32; /* ALT_SPIM_DR29_DR29 */
7504 };
7505 
7506 /* The typedef declaration for register ALT_SPIM_DR29. */
7507 typedef struct ALT_SPIM_DR29_s ALT_SPIM_DR29_t;
7508 #endif /* __ASSEMBLY__ */
7509 
7510 /* The reset value of the ALT_SPIM_DR29 register. */
7511 #define ALT_SPIM_DR29_RESET 0x00000000
7512 /* The byte offset of the ALT_SPIM_DR29 register from the beginning of the component. */
7513 #define ALT_SPIM_DR29_OFST 0xd4
7514 /* The address of the ALT_SPIM_DR29 register. */
7515 #define ALT_SPIM_DR29_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR29_OFST))
7516 
7517 /*
7518  * Register : DW_apb_ssi Data Register - DR30
7519  *
7520  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7521  * read/write buffer for
7522  *
7523  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7524  * set to 32, then all 32 bits
7525  *
7526  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7527  * register is read, data in the
7528  *
7529  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7530  * transmit FIFO buffer; a write
7531  *
7532  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7533  *
7534  * Register Layout
7535  *
7536  * Bits | Access | Reset | Description
7537  * :-------|:-------|:------|:-------------------
7538  * [31:0] | RW | 0x0 | ALT_SPIM_DR30_DR30
7539  *
7540  */
7541 /*
7542  * Field : dr30
7543  *
7544  * Data Register. When writing to this register, you must right-justify the data.
7545  * Read
7546  *
7547  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7548  *
7549  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7550  * of the
7551  *
7552  * register are valid.
7553  *
7554  * Read = Receive FIFO buffer
7555  *
7556  * Write = Transmit FIFO buffer.
7557  *
7558  * Field Access Macros:
7559  *
7560  */
7561 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR30_DR30 register field. */
7562 #define ALT_SPIM_DR30_DR30_LSB 0
7563 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR30_DR30 register field. */
7564 #define ALT_SPIM_DR30_DR30_MSB 31
7565 /* The width in bits of the ALT_SPIM_DR30_DR30 register field. */
7566 #define ALT_SPIM_DR30_DR30_WIDTH 32
7567 /* The mask used to set the ALT_SPIM_DR30_DR30 register field value. */
7568 #define ALT_SPIM_DR30_DR30_SET_MSK 0xffffffff
7569 /* The mask used to clear the ALT_SPIM_DR30_DR30 register field value. */
7570 #define ALT_SPIM_DR30_DR30_CLR_MSK 0x00000000
7571 /* The reset value of the ALT_SPIM_DR30_DR30 register field. */
7572 #define ALT_SPIM_DR30_DR30_RESET 0x0
7573 /* Extracts the ALT_SPIM_DR30_DR30 field value from a register. */
7574 #define ALT_SPIM_DR30_DR30_GET(value) (((value) & 0xffffffff) >> 0)
7575 /* Produces a ALT_SPIM_DR30_DR30 register field value suitable for setting the register. */
7576 #define ALT_SPIM_DR30_DR30_SET(value) (((value) << 0) & 0xffffffff)
7577 
7578 #ifndef __ASSEMBLY__
7579 /*
7580  * WARNING: The C register and register group struct declarations are provided for
7581  * convenience and illustrative purposes. They should, however, be used with
7582  * caution as the C language standard provides no guarantees about the alignment or
7583  * atomicity of device memory accesses. The recommended practice for coding device
7584  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7585  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7586  * alt_write_dword() functions for 64 bit registers.
7587  *
7588  * The struct declaration for register ALT_SPIM_DR30.
7589  */
7590 struct ALT_SPIM_DR30_s
7591 {
7592  volatile uint32_t dr30 : 32; /* ALT_SPIM_DR30_DR30 */
7593 };
7594 
7595 /* The typedef declaration for register ALT_SPIM_DR30. */
7596 typedef struct ALT_SPIM_DR30_s ALT_SPIM_DR30_t;
7597 #endif /* __ASSEMBLY__ */
7598 
7599 /* The reset value of the ALT_SPIM_DR30 register. */
7600 #define ALT_SPIM_DR30_RESET 0x00000000
7601 /* The byte offset of the ALT_SPIM_DR30 register from the beginning of the component. */
7602 #define ALT_SPIM_DR30_OFST 0xd8
7603 /* The address of the ALT_SPIM_DR30 register. */
7604 #define ALT_SPIM_DR30_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR30_OFST))
7605 
7606 /*
7607  * Register : DW_apb_ssi Data Register - DR31
7608  *
7609  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7610  * read/write buffer for
7611  *
7612  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7613  * set to 32, then all 32 bits
7614  *
7615  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7616  * register is read, data in the
7617  *
7618  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7619  * transmit FIFO buffer; a write
7620  *
7621  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7622  *
7623  * Register Layout
7624  *
7625  * Bits | Access | Reset | Description
7626  * :-------|:-------|:------|:-------------------
7627  * [31:0] | RW | 0x0 | ALT_SPIM_DR31_DR31
7628  *
7629  */
7630 /*
7631  * Field : dr31
7632  *
7633  * Data Register. When writing to this register, you must right-justify the data.
7634  * Read
7635  *
7636  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7637  *
7638  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7639  * of the
7640  *
7641  * register are valid.
7642  *
7643  * Read = Receive FIFO buffer
7644  *
7645  * Write = Transmit FIFO buffer.
7646  *
7647  * Field Access Macros:
7648  *
7649  */
7650 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR31_DR31 register field. */
7651 #define ALT_SPIM_DR31_DR31_LSB 0
7652 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR31_DR31 register field. */
7653 #define ALT_SPIM_DR31_DR31_MSB 31
7654 /* The width in bits of the ALT_SPIM_DR31_DR31 register field. */
7655 #define ALT_SPIM_DR31_DR31_WIDTH 32
7656 /* The mask used to set the ALT_SPIM_DR31_DR31 register field value. */
7657 #define ALT_SPIM_DR31_DR31_SET_MSK 0xffffffff
7658 /* The mask used to clear the ALT_SPIM_DR31_DR31 register field value. */
7659 #define ALT_SPIM_DR31_DR31_CLR_MSK 0x00000000
7660 /* The reset value of the ALT_SPIM_DR31_DR31 register field. */
7661 #define ALT_SPIM_DR31_DR31_RESET 0x0
7662 /* Extracts the ALT_SPIM_DR31_DR31 field value from a register. */
7663 #define ALT_SPIM_DR31_DR31_GET(value) (((value) & 0xffffffff) >> 0)
7664 /* Produces a ALT_SPIM_DR31_DR31 register field value suitable for setting the register. */
7665 #define ALT_SPIM_DR31_DR31_SET(value) (((value) << 0) & 0xffffffff)
7666 
7667 #ifndef __ASSEMBLY__
7668 /*
7669  * WARNING: The C register and register group struct declarations are provided for
7670  * convenience and illustrative purposes. They should, however, be used with
7671  * caution as the C language standard provides no guarantees about the alignment or
7672  * atomicity of device memory accesses. The recommended practice for coding device
7673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7675  * alt_write_dword() functions for 64 bit registers.
7676  *
7677  * The struct declaration for register ALT_SPIM_DR31.
7678  */
7679 struct ALT_SPIM_DR31_s
7680 {
7681  volatile uint32_t dr31 : 32; /* ALT_SPIM_DR31_DR31 */
7682 };
7683 
7684 /* The typedef declaration for register ALT_SPIM_DR31. */
7685 typedef struct ALT_SPIM_DR31_s ALT_SPIM_DR31_t;
7686 #endif /* __ASSEMBLY__ */
7687 
7688 /* The reset value of the ALT_SPIM_DR31 register. */
7689 #define ALT_SPIM_DR31_RESET 0x00000000
7690 /* The byte offset of the ALT_SPIM_DR31 register from the beginning of the component. */
7691 #define ALT_SPIM_DR31_OFST 0xdc
7692 /* The address of the ALT_SPIM_DR31 register. */
7693 #define ALT_SPIM_DR31_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR31_OFST))
7694 
7695 /*
7696  * Register : DW_apb_ssi Data Register - DR32
7697  *
7698  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7699  * read/write buffer for
7700  *
7701  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7702  * set to 32, then all 32 bits
7703  *
7704  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7705  * register is read, data in the
7706  *
7707  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7708  * transmit FIFO buffer; a write
7709  *
7710  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7711  *
7712  * Register Layout
7713  *
7714  * Bits | Access | Reset | Description
7715  * :-------|:-------|:------|:-------------------
7716  * [31:0] | RW | 0x0 | ALT_SPIM_DR32_DR32
7717  *
7718  */
7719 /*
7720  * Field : dr32
7721  *
7722  * Data Register. When writing to this register, you must right-justify the data.
7723  * Read
7724  *
7725  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7726  *
7727  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7728  * of the
7729  *
7730  * register are valid.
7731  *
7732  * Read = Receive FIFO buffer
7733  *
7734  * Write = Transmit FIFO buffer.
7735  *
7736  * Field Access Macros:
7737  *
7738  */
7739 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR32_DR32 register field. */
7740 #define ALT_SPIM_DR32_DR32_LSB 0
7741 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR32_DR32 register field. */
7742 #define ALT_SPIM_DR32_DR32_MSB 31
7743 /* The width in bits of the ALT_SPIM_DR32_DR32 register field. */
7744 #define ALT_SPIM_DR32_DR32_WIDTH 32
7745 /* The mask used to set the ALT_SPIM_DR32_DR32 register field value. */
7746 #define ALT_SPIM_DR32_DR32_SET_MSK 0xffffffff
7747 /* The mask used to clear the ALT_SPIM_DR32_DR32 register field value. */
7748 #define ALT_SPIM_DR32_DR32_CLR_MSK 0x00000000
7749 /* The reset value of the ALT_SPIM_DR32_DR32 register field. */
7750 #define ALT_SPIM_DR32_DR32_RESET 0x0
7751 /* Extracts the ALT_SPIM_DR32_DR32 field value from a register. */
7752 #define ALT_SPIM_DR32_DR32_GET(value) (((value) & 0xffffffff) >> 0)
7753 /* Produces a ALT_SPIM_DR32_DR32 register field value suitable for setting the register. */
7754 #define ALT_SPIM_DR32_DR32_SET(value) (((value) << 0) & 0xffffffff)
7755 
7756 #ifndef __ASSEMBLY__
7757 /*
7758  * WARNING: The C register and register group struct declarations are provided for
7759  * convenience and illustrative purposes. They should, however, be used with
7760  * caution as the C language standard provides no guarantees about the alignment or
7761  * atomicity of device memory accesses. The recommended practice for coding device
7762  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7763  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7764  * alt_write_dword() functions for 64 bit registers.
7765  *
7766  * The struct declaration for register ALT_SPIM_DR32.
7767  */
7768 struct ALT_SPIM_DR32_s
7769 {
7770  volatile uint32_t dr32 : 32; /* ALT_SPIM_DR32_DR32 */
7771 };
7772 
7773 /* The typedef declaration for register ALT_SPIM_DR32. */
7774 typedef struct ALT_SPIM_DR32_s ALT_SPIM_DR32_t;
7775 #endif /* __ASSEMBLY__ */
7776 
7777 /* The reset value of the ALT_SPIM_DR32 register. */
7778 #define ALT_SPIM_DR32_RESET 0x00000000
7779 /* The byte offset of the ALT_SPIM_DR32 register from the beginning of the component. */
7780 #define ALT_SPIM_DR32_OFST 0xe0
7781 /* The address of the ALT_SPIM_DR32 register. */
7782 #define ALT_SPIM_DR32_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR32_OFST))
7783 
7784 /*
7785  * Register : DW_apb_ssi Data Register - DR33
7786  *
7787  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7788  * read/write buffer for
7789  *
7790  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7791  * set to 32, then all 32 bits
7792  *
7793  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7794  * register is read, data in the
7795  *
7796  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7797  * transmit FIFO buffer; a write
7798  *
7799  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7800  *
7801  * Register Layout
7802  *
7803  * Bits | Access | Reset | Description
7804  * :-------|:-------|:------|:-------------------
7805  * [31:0] | RW | 0x0 | ALT_SPIM_DR33_DR33
7806  *
7807  */
7808 /*
7809  * Field : dr33
7810  *
7811  * Data Register. When writing to this register, you must right-justify the data.
7812  * Read
7813  *
7814  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7815  *
7816  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7817  * of the
7818  *
7819  * register are valid.
7820  *
7821  * Read = Receive FIFO buffer
7822  *
7823  * Write = Transmit FIFO buffer.
7824  *
7825  * Field Access Macros:
7826  *
7827  */
7828 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR33_DR33 register field. */
7829 #define ALT_SPIM_DR33_DR33_LSB 0
7830 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR33_DR33 register field. */
7831 #define ALT_SPIM_DR33_DR33_MSB 31
7832 /* The width in bits of the ALT_SPIM_DR33_DR33 register field. */
7833 #define ALT_SPIM_DR33_DR33_WIDTH 32
7834 /* The mask used to set the ALT_SPIM_DR33_DR33 register field value. */
7835 #define ALT_SPIM_DR33_DR33_SET_MSK 0xffffffff
7836 /* The mask used to clear the ALT_SPIM_DR33_DR33 register field value. */
7837 #define ALT_SPIM_DR33_DR33_CLR_MSK 0x00000000
7838 /* The reset value of the ALT_SPIM_DR33_DR33 register field. */
7839 #define ALT_SPIM_DR33_DR33_RESET 0x0
7840 /* Extracts the ALT_SPIM_DR33_DR33 field value from a register. */
7841 #define ALT_SPIM_DR33_DR33_GET(value) (((value) & 0xffffffff) >> 0)
7842 /* Produces a ALT_SPIM_DR33_DR33 register field value suitable for setting the register. */
7843 #define ALT_SPIM_DR33_DR33_SET(value) (((value) << 0) & 0xffffffff)
7844 
7845 #ifndef __ASSEMBLY__
7846 /*
7847  * WARNING: The C register and register group struct declarations are provided for
7848  * convenience and illustrative purposes. They should, however, be used with
7849  * caution as the C language standard provides no guarantees about the alignment or
7850  * atomicity of device memory accesses. The recommended practice for coding device
7851  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7852  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7853  * alt_write_dword() functions for 64 bit registers.
7854  *
7855  * The struct declaration for register ALT_SPIM_DR33.
7856  */
7857 struct ALT_SPIM_DR33_s
7858 {
7859  volatile uint32_t dr33 : 32; /* ALT_SPIM_DR33_DR33 */
7860 };
7861 
7862 /* The typedef declaration for register ALT_SPIM_DR33. */
7863 typedef struct ALT_SPIM_DR33_s ALT_SPIM_DR33_t;
7864 #endif /* __ASSEMBLY__ */
7865 
7866 /* The reset value of the ALT_SPIM_DR33 register. */
7867 #define ALT_SPIM_DR33_RESET 0x00000000
7868 /* The byte offset of the ALT_SPIM_DR33 register from the beginning of the component. */
7869 #define ALT_SPIM_DR33_OFST 0xe4
7870 /* The address of the ALT_SPIM_DR33 register. */
7871 #define ALT_SPIM_DR33_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR33_OFST))
7872 
7873 /*
7874  * Register : DW_apb_ssi Data Register - DR34
7875  *
7876  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7877  * read/write buffer for
7878  *
7879  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7880  * set to 32, then all 32 bits
7881  *
7882  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7883  * register is read, data in the
7884  *
7885  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7886  * transmit FIFO buffer; a write
7887  *
7888  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7889  *
7890  * Register Layout
7891  *
7892  * Bits | Access | Reset | Description
7893  * :-------|:-------|:------|:-------------------
7894  * [31:0] | RW | 0x0 | ALT_SPIM_DR34_DR34
7895  *
7896  */
7897 /*
7898  * Field : dr34
7899  *
7900  * Data Register. When writing to this register, you must right-justify the data.
7901  * Read
7902  *
7903  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7904  *
7905  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7906  * of the
7907  *
7908  * register are valid.
7909  *
7910  * Read = Receive FIFO buffer
7911  *
7912  * Write = Transmit FIFO buffer.
7913  *
7914  * Field Access Macros:
7915  *
7916  */
7917 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR34_DR34 register field. */
7918 #define ALT_SPIM_DR34_DR34_LSB 0
7919 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR34_DR34 register field. */
7920 #define ALT_SPIM_DR34_DR34_MSB 31
7921 /* The width in bits of the ALT_SPIM_DR34_DR34 register field. */
7922 #define ALT_SPIM_DR34_DR34_WIDTH 32
7923 /* The mask used to set the ALT_SPIM_DR34_DR34 register field value. */
7924 #define ALT_SPIM_DR34_DR34_SET_MSK 0xffffffff
7925 /* The mask used to clear the ALT_SPIM_DR34_DR34 register field value. */
7926 #define ALT_SPIM_DR34_DR34_CLR_MSK 0x00000000
7927 /* The reset value of the ALT_SPIM_DR34_DR34 register field. */
7928 #define ALT_SPIM_DR34_DR34_RESET 0x0
7929 /* Extracts the ALT_SPIM_DR34_DR34 field value from a register. */
7930 #define ALT_SPIM_DR34_DR34_GET(value) (((value) & 0xffffffff) >> 0)
7931 /* Produces a ALT_SPIM_DR34_DR34 register field value suitable for setting the register. */
7932 #define ALT_SPIM_DR34_DR34_SET(value) (((value) << 0) & 0xffffffff)
7933 
7934 #ifndef __ASSEMBLY__
7935 /*
7936  * WARNING: The C register and register group struct declarations are provided for
7937  * convenience and illustrative purposes. They should, however, be used with
7938  * caution as the C language standard provides no guarantees about the alignment or
7939  * atomicity of device memory accesses. The recommended practice for coding device
7940  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7941  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7942  * alt_write_dword() functions for 64 bit registers.
7943  *
7944  * The struct declaration for register ALT_SPIM_DR34.
7945  */
7946 struct ALT_SPIM_DR34_s
7947 {
7948  volatile uint32_t dr34 : 32; /* ALT_SPIM_DR34_DR34 */
7949 };
7950 
7951 /* The typedef declaration for register ALT_SPIM_DR34. */
7952 typedef struct ALT_SPIM_DR34_s ALT_SPIM_DR34_t;
7953 #endif /* __ASSEMBLY__ */
7954 
7955 /* The reset value of the ALT_SPIM_DR34 register. */
7956 #define ALT_SPIM_DR34_RESET 0x00000000
7957 /* The byte offset of the ALT_SPIM_DR34 register from the beginning of the component. */
7958 #define ALT_SPIM_DR34_OFST 0xe8
7959 /* The address of the ALT_SPIM_DR34 register. */
7960 #define ALT_SPIM_DR34_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR34_OFST))
7961 
7962 /*
7963  * Register : DW_apb_ssi Data Register - DR35
7964  *
7965  * The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE)
7966  * read/write buffer for
7967  *
7968  * the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is
7969  * set to 32, then all 32 bits
7970  *
7971  * are valid, otherwise, only 16 bits ([15:0]) of the register are valid. When the
7972  * register is read, data in the
7973  *
7974  * receive FIFO buffer is accessed. When it is written to, data are moved into the
7975  * transmit FIFO buffer; a write
7976  *
7977  * can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0.
7978  *
7979  * Register Layout
7980  *
7981  * Bits | Access | Reset | Description
7982  * :-------|:-------|:------|:-------------------
7983  * [31:0] | RW | 0x0 | ALT_SPIM_DR35_DR35
7984  *
7985  */
7986 /*
7987  * Field : dr35
7988  *
7989  * Data Register. When writing to this register, you must right-justify the data.
7990  * Read
7991  *
7992  * data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration
7993  *
7994  * parameter is set to 32, all 32 bits are valid. Otherwise, only 16 bits ([15:0])
7995  * of the
7996  *
7997  * register are valid.
7998  *
7999  * Read = Receive FIFO buffer
8000  *
8001  * Write = Transmit FIFO buffer.
8002  *
8003  * Field Access Macros:
8004  *
8005  */
8006 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR35_DR35 register field. */
8007 #define ALT_SPIM_DR35_DR35_LSB 0
8008 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR35_DR35 register field. */
8009 #define ALT_SPIM_DR35_DR35_MSB 31
8010 /* The width in bits of the ALT_SPIM_DR35_DR35 register field. */
8011 #define ALT_SPIM_DR35_DR35_WIDTH 32
8012 /* The mask used to set the ALT_SPIM_DR35_DR35 register field value. */
8013 #define ALT_SPIM_DR35_DR35_SET_MSK 0xffffffff
8014 /* The mask used to clear the ALT_SPIM_DR35_DR35 register field value. */
8015 #define ALT_SPIM_DR35_DR35_CLR_MSK 0x00000000
8016 /* The reset value of the ALT_SPIM_DR35_DR35 register field. */
8017 #define ALT_SPIM_DR35_DR35_RESET 0x0
8018 /* Extracts the ALT_SPIM_DR35_DR35 field value from a register. */
8019 #define ALT_SPIM_DR35_DR35_GET(value) (((value) & 0xffffffff) >> 0)
8020 /* Produces a ALT_SPIM_DR35_DR35 register field value suitable for setting the register. */
8021 #define ALT_SPIM_DR35_DR35_SET(value) (((value) << 0) & 0xffffffff)
8022 
8023 #ifndef __ASSEMBLY__
8024 /*
8025  * WARNING: The C register and register group struct declarations are provided for
8026  * convenience and illustrative purposes. They should, however, be used with
8027  * caution as the C language standard provides no guarantees about the alignment or
8028  * atomicity of device memory accesses. The recommended practice for coding device
8029  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8030  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8031  * alt_write_dword() functions for 64 bit registers.
8032  *
8033  * The struct declaration for register ALT_SPIM_DR35.
8034  */
8035 struct ALT_SPIM_DR35_s
8036 {
8037  volatile uint32_t dr35 : 32; /* ALT_SPIM_DR35_DR35 */
8038 };
8039 
8040 /* The typedef declaration for register ALT_SPIM_DR35. */
8041 typedef struct ALT_SPIM_DR35_s ALT_SPIM_DR35_t;
8042 #endif /* __ASSEMBLY__ */
8043 
8044 /* The reset value of the ALT_SPIM_DR35 register. */
8045 #define ALT_SPIM_DR35_RESET 0x00000000
8046 /* The byte offset of the ALT_SPIM_DR35 register from the beginning of the component. */
8047 #define ALT_SPIM_DR35_OFST 0xec
8048 /* The address of the ALT_SPIM_DR35 register. */
8049 #define ALT_SPIM_DR35_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR35_OFST))
8050 
8051 /*
8052  * Register : RX Sample Delay - RX_SAMPLE_DLY
8053  *
8054  * RX Sample Delay.
8055  *
8056  * This register is only valid when the DW_apb_ssi is configured with rxd
8057  *
8058  * sample delay logic (SSI_HAS_RX_SAMPLE_DELAY==1). When the DW_apb_ssi is
8059  *
8060  * not configured with rxd sample delay logic, this register will not exist
8061  *
8062  * and writing to its address location will have no effect; reading from
8063  *
8064  * its address will return zero. This register control the number of ssi_clk
8065  *
8066  * cycles that are delayed (from the default sample time) before the actual
8067  *
8068  * sample of the rxd input occurs. It is impossible to write to this
8069  *
8070  * register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and
8071  *
8072  * disabled by writing to the SSIENR register.
8073  *
8074  * Register Layout
8075  *
8076  * Bits | Access | Reset | Description
8077  * :-------|:-------|:------|:------------------------------------------
8078  * [7:0] | RW | 0x0 | ALT_SPIM_RX_SAMPLE_DLY_RSD
8079  * [31:8] | R | 0x0 | ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY
8080  *
8081  */
8082 /*
8083  * Field : RSD
8084  *
8085  * Rxd Sample Delay.
8086  *
8087  * This register is used to delay the sample of the rxd input port. Each value
8088  *
8089  * represents a single ssi_clk delay on the sample of rxd. Note; If this register
8090  *
8091  * is programmed with a value that exceeds the depth of the internal shift
8092  *
8093  * registers (SSI_RX_DLY_SR_DEPTH) zero delay will be applied to the rxd sample.
8094  *
8095  * Field Access Macros:
8096  *
8097  */
8098 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SAMPLE_DLY_RSD register field. */
8099 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_LSB 0
8100 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SAMPLE_DLY_RSD register field. */
8101 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_MSB 7
8102 /* The width in bits of the ALT_SPIM_RX_SAMPLE_DLY_RSD register field. */
8103 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_WIDTH 8
8104 /* The mask used to set the ALT_SPIM_RX_SAMPLE_DLY_RSD register field value. */
8105 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_SET_MSK 0x000000ff
8106 /* The mask used to clear the ALT_SPIM_RX_SAMPLE_DLY_RSD register field value. */
8107 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_CLR_MSK 0xffffff00
8108 /* The reset value of the ALT_SPIM_RX_SAMPLE_DLY_RSD register field. */
8109 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_RESET 0x0
8110 /* Extracts the ALT_SPIM_RX_SAMPLE_DLY_RSD field value from a register. */
8111 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_GET(value) (((value) & 0x000000ff) >> 0)
8112 /* Produces a ALT_SPIM_RX_SAMPLE_DLY_RSD register field value suitable for setting the register. */
8113 #define ALT_SPIM_RX_SAMPLE_DLY_RSD_SET(value) (((value) << 0) & 0x000000ff)
8114 
8115 /*
8116  * Field : RSVD_RX_SAMPLE_DLY
8117  *
8118  * Reserved bits - Read Only
8119  *
8120  * Field Access Macros:
8121  *
8122  */
8123 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field. */
8124 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_LSB 8
8125 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field. */
8126 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_MSB 31
8127 /* The width in bits of the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field. */
8128 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_WIDTH 24
8129 /* The mask used to set the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field value. */
8130 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_SET_MSK 0xffffff00
8131 /* The mask used to clear the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field value. */
8132 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_CLR_MSK 0x000000ff
8133 /* The reset value of the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field. */
8134 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_RESET 0x0
8135 /* Extracts the ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY field value from a register. */
8136 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_GET(value) (((value) & 0xffffff00) >> 8)
8137 /* Produces a ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY register field value suitable for setting the register. */
8138 #define ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY_SET(value) (((value) << 8) & 0xffffff00)
8139 
8140 #ifndef __ASSEMBLY__
8141 /*
8142  * WARNING: The C register and register group struct declarations are provided for
8143  * convenience and illustrative purposes. They should, however, be used with
8144  * caution as the C language standard provides no guarantees about the alignment or
8145  * atomicity of device memory accesses. The recommended practice for coding device
8146  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8147  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8148  * alt_write_dword() functions for 64 bit registers.
8149  *
8150  * The struct declaration for register ALT_SPIM_RX_SAMPLE_DLY.
8151  */
8152 struct ALT_SPIM_RX_SAMPLE_DLY_s
8153 {
8154  volatile uint32_t RSD : 8; /* ALT_SPIM_RX_SAMPLE_DLY_RSD */
8155  const volatile uint32_t RSVD_RX_SAMPLE_DLY : 24; /* ALT_SPIM_RX_SAMPLE_DLY_RSVD_RX_SAMPLE_DLY */
8156 };
8157 
8158 /* The typedef declaration for register ALT_SPIM_RX_SAMPLE_DLY. */
8159 typedef struct ALT_SPIM_RX_SAMPLE_DLY_s ALT_SPIM_RX_SAMPLE_DLY_t;
8160 #endif /* __ASSEMBLY__ */
8161 
8162 /* The reset value of the ALT_SPIM_RX_SAMPLE_DLY register. */
8163 #define ALT_SPIM_RX_SAMPLE_DLY_RESET 0x00000000
8164 /* The byte offset of the ALT_SPIM_RX_SAMPLE_DLY register from the beginning of the component. */
8165 #define ALT_SPIM_RX_SAMPLE_DLY_OFST 0xf0
8166 /* The address of the ALT_SPIM_RX_SAMPLE_DLY register. */
8167 #define ALT_SPIM_RX_SAMPLE_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SAMPLE_DLY_OFST))
8168 
8169 /*
8170  * Register : RSVD_1 - Reserved address location - RSVD_1
8171  *
8172  * RSVD_1 - Reserved address location
8173  *
8174  * Register Layout
8175  *
8176  * Bits | Access | Reset | Description
8177  * :-------|:-------|:------|:----------------------
8178  * [31:0] | R | 0x0 | ALT_SPIM_RSVD_1_RSVD1
8179  *
8180  */
8181 /*
8182  * Field : RSVD1
8183  *
8184  * Reserved address location
8185  *
8186  * Field Access Macros:
8187  *
8188  */
8189 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RSVD_1_RSVD1 register field. */
8190 #define ALT_SPIM_RSVD_1_RSVD1_LSB 0
8191 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RSVD_1_RSVD1 register field. */
8192 #define ALT_SPIM_RSVD_1_RSVD1_MSB 31
8193 /* The width in bits of the ALT_SPIM_RSVD_1_RSVD1 register field. */
8194 #define ALT_SPIM_RSVD_1_RSVD1_WIDTH 32
8195 /* The mask used to set the ALT_SPIM_RSVD_1_RSVD1 register field value. */
8196 #define ALT_SPIM_RSVD_1_RSVD1_SET_MSK 0xffffffff
8197 /* The mask used to clear the ALT_SPIM_RSVD_1_RSVD1 register field value. */
8198 #define ALT_SPIM_RSVD_1_RSVD1_CLR_MSK 0x00000000
8199 /* The reset value of the ALT_SPIM_RSVD_1_RSVD1 register field. */
8200 #define ALT_SPIM_RSVD_1_RSVD1_RESET 0x0
8201 /* Extracts the ALT_SPIM_RSVD_1_RSVD1 field value from a register. */
8202 #define ALT_SPIM_RSVD_1_RSVD1_GET(value) (((value) & 0xffffffff) >> 0)
8203 /* Produces a ALT_SPIM_RSVD_1_RSVD1 register field value suitable for setting the register. */
8204 #define ALT_SPIM_RSVD_1_RSVD1_SET(value) (((value) << 0) & 0xffffffff)
8205 
8206 #ifndef __ASSEMBLY__
8207 /*
8208  * WARNING: The C register and register group struct declarations are provided for
8209  * convenience and illustrative purposes. They should, however, be used with
8210  * caution as the C language standard provides no guarantees about the alignment or
8211  * atomicity of device memory accesses. The recommended practice for coding device
8212  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8213  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8214  * alt_write_dword() functions for 64 bit registers.
8215  *
8216  * The struct declaration for register ALT_SPIM_RSVD_1.
8217  */
8218 struct ALT_SPIM_RSVD_1_s
8219 {
8220  const volatile uint32_t RSVD1 : 32; /* ALT_SPIM_RSVD_1_RSVD1 */
8221 };
8222 
8223 /* The typedef declaration for register ALT_SPIM_RSVD_1. */
8224 typedef struct ALT_SPIM_RSVD_1_s ALT_SPIM_RSVD_1_t;
8225 #endif /* __ASSEMBLY__ */
8226 
8227 /* The reset value of the ALT_SPIM_RSVD_1 register. */
8228 #define ALT_SPIM_RSVD_1_RESET 0x00000000
8229 /* The byte offset of the ALT_SPIM_RSVD_1 register from the beginning of the component. */
8230 #define ALT_SPIM_RSVD_1_OFST 0xf8
8231 /* The address of the ALT_SPIM_RSVD_1 register. */
8232 #define ALT_SPIM_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_1_OFST))
8233 
8234 /*
8235  * Register : RSVD_2 - Reserved address location - RSVD_2
8236  *
8237  * RSVD_2 - Reserved address location
8238  *
8239  * Register Layout
8240  *
8241  * Bits | Access | Reset | Description
8242  * :-------|:-------|:------|:----------------------
8243  * [31:0] | R | 0x0 | ALT_SPIM_RSVD_2_RSVD2
8244  *
8245  */
8246 /*
8247  * Field : RSVD2
8248  *
8249  * Reserved address location
8250  *
8251  * Field Access Macros:
8252  *
8253  */
8254 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RSVD_2_RSVD2 register field. */
8255 #define ALT_SPIM_RSVD_2_RSVD2_LSB 0
8256 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RSVD_2_RSVD2 register field. */
8257 #define ALT_SPIM_RSVD_2_RSVD2_MSB 31
8258 /* The width in bits of the ALT_SPIM_RSVD_2_RSVD2 register field. */
8259 #define ALT_SPIM_RSVD_2_RSVD2_WIDTH 32
8260 /* The mask used to set the ALT_SPIM_RSVD_2_RSVD2 register field value. */
8261 #define ALT_SPIM_RSVD_2_RSVD2_SET_MSK 0xffffffff
8262 /* The mask used to clear the ALT_SPIM_RSVD_2_RSVD2 register field value. */
8263 #define ALT_SPIM_RSVD_2_RSVD2_CLR_MSK 0x00000000
8264 /* The reset value of the ALT_SPIM_RSVD_2_RSVD2 register field. */
8265 #define ALT_SPIM_RSVD_2_RSVD2_RESET 0x0
8266 /* Extracts the ALT_SPIM_RSVD_2_RSVD2 field value from a register. */
8267 #define ALT_SPIM_RSVD_2_RSVD2_GET(value) (((value) & 0xffffffff) >> 0)
8268 /* Produces a ALT_SPIM_RSVD_2_RSVD2 register field value suitable for setting the register. */
8269 #define ALT_SPIM_RSVD_2_RSVD2_SET(value) (((value) << 0) & 0xffffffff)
8270 
8271 #ifndef __ASSEMBLY__
8272 /*
8273  * WARNING: The C register and register group struct declarations are provided for
8274  * convenience and illustrative purposes. They should, however, be used with
8275  * caution as the C language standard provides no guarantees about the alignment or
8276  * atomicity of device memory accesses. The recommended practice for coding device
8277  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8278  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8279  * alt_write_dword() functions for 64 bit registers.
8280  *
8281  * The struct declaration for register ALT_SPIM_RSVD_2.
8282  */
8283 struct ALT_SPIM_RSVD_2_s
8284 {
8285  const volatile uint32_t RSVD2 : 32; /* ALT_SPIM_RSVD_2_RSVD2 */
8286 };
8287 
8288 /* The typedef declaration for register ALT_SPIM_RSVD_2. */
8289 typedef struct ALT_SPIM_RSVD_2_s ALT_SPIM_RSVD_2_t;
8290 #endif /* __ASSEMBLY__ */
8291 
8292 /* The reset value of the ALT_SPIM_RSVD_2 register. */
8293 #define ALT_SPIM_RSVD_2_RESET 0x00000000
8294 /* The byte offset of the ALT_SPIM_RSVD_2 register from the beginning of the component. */
8295 #define ALT_SPIM_RSVD_2_OFST 0xfc
8296 /* The address of the ALT_SPIM_RSVD_2 register. */
8297 #define ALT_SPIM_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_2_OFST))
8298 
8299 #ifndef __ASSEMBLY__
8300 /*
8301  * WARNING: The C register and register group struct declarations are provided for
8302  * convenience and illustrative purposes. They should, however, be used with
8303  * caution as the C language standard provides no guarantees about the alignment or
8304  * atomicity of device memory accesses. The recommended practice for coding device
8305  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8306  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8307  * alt_write_dword() functions for 64 bit registers.
8308  *
8309  * The struct declaration for register group ALT_SPIM.
8310  */
8311 struct ALT_SPIM_s
8312 {
8313  volatile ALT_SPIM_CTRLR0_t CTRLR0; /* ALT_SPIM_CTRLR0 */
8314  volatile ALT_SPIM_CTRLR1_t CTRLR1; /* ALT_SPIM_CTRLR1 */
8315  volatile ALT_SPIM_SSIENR_t SSIENR; /* ALT_SPIM_SSIENR */
8316  volatile ALT_SPIM_MWCR_t MWCR; /* ALT_SPIM_MWCR */
8317  volatile ALT_SPIM_SER_t SER; /* ALT_SPIM_SER */
8318  volatile ALT_SPIM_BAUDR_t BAUDR; /* ALT_SPIM_BAUDR */
8319  volatile ALT_SPIM_TXFTLR_t TXFTLR; /* ALT_SPIM_TXFTLR */
8320  volatile ALT_SPIM_RXFTLR_t RXFTLR; /* ALT_SPIM_RXFTLR */
8321  volatile ALT_SPIM_TXFLR_t TXFLR; /* ALT_SPIM_TXFLR */
8322  volatile ALT_SPIM_RXFLR_t RXFLR; /* ALT_SPIM_RXFLR */
8323  volatile ALT_SPIM_SR_t SR; /* ALT_SPIM_SR */
8324  volatile ALT_SPIM_IMR_t IMR; /* ALT_SPIM_IMR */
8325  volatile ALT_SPIM_ISR_t ISR; /* ALT_SPIM_ISR */
8326  volatile ALT_SPIM_RISR_t RISR; /* ALT_SPIM_RISR */
8327  volatile ALT_SPIM_TXOICR_t TXOICR; /* ALT_SPIM_TXOICR */
8328  volatile ALT_SPIM_RXOICR_t RXOICR; /* ALT_SPIM_RXOICR */
8329  volatile ALT_SPIM_RXUICR_t RXUICR; /* ALT_SPIM_RXUICR */
8330  volatile ALT_SPIM_MSTICR_t MSTICR; /* ALT_SPIM_MSTICR */
8331  volatile ALT_SPIM_ICR_t ICR; /* ALT_SPIM_ICR */
8332  volatile ALT_SPIM_DMACR_t DMACR; /* ALT_SPIM_DMACR */
8333  volatile ALT_SPIM_DMATDLR_t DMATDLR; /* ALT_SPIM_DMATDLR */
8334  volatile ALT_SPIM_DMARDLR_t DMARDLR; /* ALT_SPIM_DMARDLR */
8335  volatile ALT_SPIM_IDR_t IDR; /* ALT_SPIM_IDR */
8336  volatile ALT_SPIM_SSI_VERSION_ID_t SSI_VERSION_ID; /* ALT_SPIM_SSI_VERSION_ID */
8337  volatile ALT_SPIM_DR0_t DR0; /* ALT_SPIM_DR0 */
8338  volatile ALT_SPIM_DR1_t DR1; /* ALT_SPIM_DR1 */
8339  volatile ALT_SPIM_DR2_t DR2; /* ALT_SPIM_DR2 */
8340  volatile ALT_SPIM_DR3_t DR3; /* ALT_SPIM_DR3 */
8341  volatile ALT_SPIM_DR4_t DR4; /* ALT_SPIM_DR4 */
8342  volatile ALT_SPIM_DR5_t DR5; /* ALT_SPIM_DR5 */
8343  volatile ALT_SPIM_DR6_t DR6; /* ALT_SPIM_DR6 */
8344  volatile ALT_SPIM_DR7_t DR7; /* ALT_SPIM_DR7 */
8345  volatile ALT_SPIM_DR8_t DR8; /* ALT_SPIM_DR8 */
8346  volatile ALT_SPIM_DR9_t DR9; /* ALT_SPIM_DR9 */
8347  volatile ALT_SPIM_DR10_t DR10; /* ALT_SPIM_DR10 */
8348  volatile ALT_SPIM_DR11_t DR11; /* ALT_SPIM_DR11 */
8349  volatile ALT_SPIM_DR12_t DR12; /* ALT_SPIM_DR12 */
8350  volatile ALT_SPIM_DR13_t DR13; /* ALT_SPIM_DR13 */
8351  volatile ALT_SPIM_DR14_t DR14; /* ALT_SPIM_DR14 */
8352  volatile ALT_SPIM_DR15_t DR15; /* ALT_SPIM_DR15 */
8353  volatile ALT_SPIM_DR16_t DR16; /* ALT_SPIM_DR16 */
8354  volatile ALT_SPIM_DR17_t DR17; /* ALT_SPIM_DR17 */
8355  volatile ALT_SPIM_DR18_t DR18; /* ALT_SPIM_DR18 */
8356  volatile ALT_SPIM_DR19_t DR19; /* ALT_SPIM_DR19 */
8357  volatile ALT_SPIM_DR20_t DR20; /* ALT_SPIM_DR20 */
8358  volatile ALT_SPIM_DR21_t DR21; /* ALT_SPIM_DR21 */
8359  volatile ALT_SPIM_DR22_t DR22; /* ALT_SPIM_DR22 */
8360  volatile ALT_SPIM_DR23_t DR23; /* ALT_SPIM_DR23 */
8361  volatile ALT_SPIM_DR24_t DR24; /* ALT_SPIM_DR24 */
8362  volatile ALT_SPIM_DR25_t DR25; /* ALT_SPIM_DR25 */
8363  volatile ALT_SPIM_DR26_t DR26; /* ALT_SPIM_DR26 */
8364  volatile ALT_SPIM_DR27_t DR27; /* ALT_SPIM_DR27 */
8365  volatile ALT_SPIM_DR28_t DR28; /* ALT_SPIM_DR28 */
8366  volatile ALT_SPIM_DR29_t DR29; /* ALT_SPIM_DR29 */
8367  volatile ALT_SPIM_DR30_t DR30; /* ALT_SPIM_DR30 */
8368  volatile ALT_SPIM_DR31_t DR31; /* ALT_SPIM_DR31 */
8369  volatile ALT_SPIM_DR32_t DR32; /* ALT_SPIM_DR32 */
8370  volatile ALT_SPIM_DR33_t DR33; /* ALT_SPIM_DR33 */
8371  volatile ALT_SPIM_DR34_t DR34; /* ALT_SPIM_DR34 */
8372  volatile ALT_SPIM_DR35_t DR35; /* ALT_SPIM_DR35 */
8373  volatile ALT_SPIM_RX_SAMPLE_DLY_t RX_SAMPLE_DLY; /* ALT_SPIM_RX_SAMPLE_DLY */
8374  volatile uint32_t _pad_0xf4_0xf7; /* *UNDEFINED* */
8375  volatile ALT_SPIM_RSVD_1_t RSVD_1; /* ALT_SPIM_RSVD_1 */
8376  volatile ALT_SPIM_RSVD_2_t RSVD_2; /* ALT_SPIM_RSVD_2 */
8377 };
8378 
8379 /* The typedef declaration for register group ALT_SPIM. */
8380 typedef struct ALT_SPIM_s ALT_SPIM_t;
8381 /* The struct declaration for the raw register contents of register group ALT_SPIM. */
8382 struct ALT_SPIM_raw_s
8383 {
8384  volatile uint32_t CTRLR0; /* ALT_SPIM_CTRLR0 */
8385  volatile uint32_t CTRLR1; /* ALT_SPIM_CTRLR1 */
8386  volatile uint32_t SSIENR; /* ALT_SPIM_SSIENR */
8387  volatile uint32_t MWCR; /* ALT_SPIM_MWCR */
8388  volatile uint32_t SER; /* ALT_SPIM_SER */
8389  volatile uint32_t BAUDR; /* ALT_SPIM_BAUDR */
8390  volatile uint32_t TXFTLR; /* ALT_SPIM_TXFTLR */
8391  volatile uint32_t RXFTLR; /* ALT_SPIM_RXFTLR */
8392  volatile uint32_t TXFLR; /* ALT_SPIM_TXFLR */
8393  volatile uint32_t RXFLR; /* ALT_SPIM_RXFLR */
8394  volatile uint32_t SR; /* ALT_SPIM_SR */
8395  volatile uint32_t IMR; /* ALT_SPIM_IMR */
8396  volatile uint32_t ISR; /* ALT_SPIM_ISR */
8397  volatile uint32_t RISR; /* ALT_SPIM_RISR */
8398  volatile uint32_t TXOICR; /* ALT_SPIM_TXOICR */
8399  volatile uint32_t RXOICR; /* ALT_SPIM_RXOICR */
8400  volatile uint32_t RXUICR; /* ALT_SPIM_RXUICR */
8401  volatile uint32_t MSTICR; /* ALT_SPIM_MSTICR */
8402  volatile uint32_t ICR; /* ALT_SPIM_ICR */
8403  volatile uint32_t DMACR; /* ALT_SPIM_DMACR */
8404  volatile uint32_t DMATDLR; /* ALT_SPIM_DMATDLR */
8405  volatile uint32_t DMARDLR; /* ALT_SPIM_DMARDLR */
8406  volatile uint32_t IDR; /* ALT_SPIM_IDR */
8407  volatile uint32_t SSI_VERSION_ID; /* ALT_SPIM_SSI_VERSION_ID */
8408  volatile uint32_t DR0; /* ALT_SPIM_DR0 */
8409  volatile uint32_t DR1; /* ALT_SPIM_DR1 */
8410  volatile uint32_t DR2; /* ALT_SPIM_DR2 */
8411  volatile uint32_t DR3; /* ALT_SPIM_DR3 */
8412  volatile uint32_t DR4; /* ALT_SPIM_DR4 */
8413  volatile uint32_t DR5; /* ALT_SPIM_DR5 */
8414  volatile uint32_t DR6; /* ALT_SPIM_DR6 */
8415  volatile uint32_t DR7; /* ALT_SPIM_DR7 */
8416  volatile uint32_t DR8; /* ALT_SPIM_DR8 */
8417  volatile uint32_t DR9; /* ALT_SPIM_DR9 */
8418  volatile uint32_t DR10; /* ALT_SPIM_DR10 */
8419  volatile uint32_t DR11; /* ALT_SPIM_DR11 */
8420  volatile uint32_t DR12; /* ALT_SPIM_DR12 */
8421  volatile uint32_t DR13; /* ALT_SPIM_DR13 */
8422  volatile uint32_t DR14; /* ALT_SPIM_DR14 */
8423  volatile uint32_t DR15; /* ALT_SPIM_DR15 */
8424  volatile uint32_t DR16; /* ALT_SPIM_DR16 */
8425  volatile uint32_t DR17; /* ALT_SPIM_DR17 */
8426  volatile uint32_t DR18; /* ALT_SPIM_DR18 */
8427  volatile uint32_t DR19; /* ALT_SPIM_DR19 */
8428  volatile uint32_t DR20; /* ALT_SPIM_DR20 */
8429  volatile uint32_t DR21; /* ALT_SPIM_DR21 */
8430  volatile uint32_t DR22; /* ALT_SPIM_DR22 */
8431  volatile uint32_t DR23; /* ALT_SPIM_DR23 */
8432  volatile uint32_t DR24; /* ALT_SPIM_DR24 */
8433  volatile uint32_t DR25; /* ALT_SPIM_DR25 */
8434  volatile uint32_t DR26; /* ALT_SPIM_DR26 */
8435  volatile uint32_t DR27; /* ALT_SPIM_DR27 */
8436  volatile uint32_t DR28; /* ALT_SPIM_DR28 */
8437  volatile uint32_t DR29; /* ALT_SPIM_DR29 */
8438  volatile uint32_t DR30; /* ALT_SPIM_DR30 */
8439  volatile uint32_t DR31; /* ALT_SPIM_DR31 */
8440  volatile uint32_t DR32; /* ALT_SPIM_DR32 */
8441  volatile uint32_t DR33; /* ALT_SPIM_DR33 */
8442  volatile uint32_t DR34; /* ALT_SPIM_DR34 */
8443  volatile uint32_t DR35; /* ALT_SPIM_DR35 */
8444  volatile uint32_t RX_SAMPLE_DLY; /* ALT_SPIM_RX_SAMPLE_DLY */
8445  volatile uint32_t _pad_0xf4_0xf7; /* *UNDEFINED* */
8446  volatile uint32_t RSVD_1; /* ALT_SPIM_RSVD_1 */
8447  volatile uint32_t RSVD_2; /* ALT_SPIM_RSVD_2 */
8448 };
8449 
8450 /* The typedef declaration for the raw register contents of register group ALT_SPIM. */
8451 typedef struct ALT_SPIM_raw_s ALT_SPIM_raw_t;
8452 #endif /* __ASSEMBLY__ */
8453 
8454 
8455 #ifdef __cplusplus
8456 }
8457 #endif /* __cplusplus */
8458 #endif /* __ALT_SOCAL_SPIM_H__ */
8459