Hardware Libraries  20.1
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alt_tmr.h
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32 
33 /* Altera - ALT_TMR */
34 
35 #ifndef __ALT_SOCAL_TMR_H__
36 #define __ALT_SOCAL_TMR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_TMR
50  *
51  */
52 /*
53  * Register : timer1loadcount
54  *
55  * Name: Timer1 Load Count Register
56  *
57  * Size: 8-32 bits
58  *
59  * Address Offset: 0x00
60  *
61  * Read/Write Access: Read/Write
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :-------|:-------|:------|:--------------------------------
67  * [31:0] | RW | 0x0 | ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT
68  *
69  */
70 /*
71  * Field : timer1loadcount
72  *
73  * Value to be loaded into Timer1. This is the value from which counting
74  *
75  * commences. Any value written to this register is loaded into the associated
76  * timer.
77  *
78  * Field Access Macros:
79  *
80  */
81 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
82 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_LSB 0
83 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
84 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_MSB 31
85 /* The width in bits of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
86 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_WIDTH 32
87 /* The mask used to set the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
88 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET_MSK 0xffffffff
89 /* The mask used to clear the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value. */
90 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_CLR_MSK 0x00000000
91 /* The reset value of the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field. */
92 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_RESET 0x0
93 /* Extracts the ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT field value from a register. */
94 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_GET(value) (((value) & 0xffffffff) >> 0)
95 /* Produces a ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT register field value suitable for setting the register. */
96 #define ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT_SET(value) (((value) << 0) & 0xffffffff)
97 
98 #ifndef __ASSEMBLY__
99 /*
100  * WARNING: The C register and register group struct declarations are provided for
101  * convenience and illustrative purposes. They should, however, be used with
102  * caution as the C language standard provides no guarantees about the alignment or
103  * atomicity of device memory accesses. The recommended practice for writing
104  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
105  * alt_write_word() functions.
106  *
107  * The struct declaration for register ALT_TMR_TMR1LDCOUNT.
108  */
109 struct ALT_TMR_TMR1LDCOUNT_s
110 {
111  uint32_t timer1loadcount : 32; /* ALT_TMR_TMR1LDCOUNT_TMR1LDCOUNT */
112 };
113 
114 /* The typedef declaration for register ALT_TMR_TMR1LDCOUNT. */
115 typedef volatile struct ALT_TMR_TMR1LDCOUNT_s ALT_TMR_TMR1LDCOUNT_t;
116 #endif /* __ASSEMBLY__ */
117 
118 /* The reset value of the ALT_TMR_TMR1LDCOUNT register. */
119 #define ALT_TMR_TMR1LDCOUNT_RESET 0x00000000
120 /* The byte offset of the ALT_TMR_TMR1LDCOUNT register from the beginning of the component. */
121 #define ALT_TMR_TMR1LDCOUNT_OFST 0x0
122 /* The address of the ALT_TMR_TMR1LDCOUNT register. */
123 #define ALT_TMR_TMR1LDCOUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1LDCOUNT_OFST))
124 
125 /*
126  * Register : timer1currentval
127  *
128  * Name: Timer1 Current Value
129  *
130  * Size: 8-32 bits
131  *
132  * Address Offset: 4
133  *
134  * Read/Write Access: Read
135  *
136  * Register Layout
137  *
138  * Bits | Access | Reset | Description
139  * :-------|:-------|:------|:------------------------------
140  * [31:0] | R | 0x0 | ALT_TMR_TMR1CURVAL_TMR1CURVAL
141  *
142  */
143 /*
144  * Field : timer1currentval
145  *
146  * Current Value of Timer1. This register is supported only
147  *
148  * when timer_1_clk is synchronous to pclk. Reading this
149  *
150  * register when using independent clocks results in an
151  *
152  * undefined value.
153  *
154  * Field Access Macros:
155  *
156  */
157 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
158 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_LSB 0
159 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
160 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_MSB 31
161 /* The width in bits of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
162 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_WIDTH 32
163 /* The mask used to set the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
164 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET_MSK 0xffffffff
165 /* The mask used to clear the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value. */
166 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_CLR_MSK 0x00000000
167 /* The reset value of the ALT_TMR_TMR1CURVAL_TMR1CURVAL register field. */
168 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_RESET 0x0
169 /* Extracts the ALT_TMR_TMR1CURVAL_TMR1CURVAL field value from a register. */
170 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_GET(value) (((value) & 0xffffffff) >> 0)
171 /* Produces a ALT_TMR_TMR1CURVAL_TMR1CURVAL register field value suitable for setting the register. */
172 #define ALT_TMR_TMR1CURVAL_TMR1CURVAL_SET(value) (((value) << 0) & 0xffffffff)
173 
174 #ifndef __ASSEMBLY__
175 /*
176  * WARNING: The C register and register group struct declarations are provided for
177  * convenience and illustrative purposes. They should, however, be used with
178  * caution as the C language standard provides no guarantees about the alignment or
179  * atomicity of device memory accesses. The recommended practice for writing
180  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
181  * alt_write_word() functions.
182  *
183  * The struct declaration for register ALT_TMR_TMR1CURVAL.
184  */
185 struct ALT_TMR_TMR1CURVAL_s
186 {
187  const uint32_t timer1currentval : 32; /* ALT_TMR_TMR1CURVAL_TMR1CURVAL */
188 };
189 
190 /* The typedef declaration for register ALT_TMR_TMR1CURVAL. */
191 typedef volatile struct ALT_TMR_TMR1CURVAL_s ALT_TMR_TMR1CURVAL_t;
192 #endif /* __ASSEMBLY__ */
193 
194 /* The reset value of the ALT_TMR_TMR1CURVAL register. */
195 #define ALT_TMR_TMR1CURVAL_RESET 0x00000000
196 /* The byte offset of the ALT_TMR_TMR1CURVAL register from the beginning of the component. */
197 #define ALT_TMR_TMR1CURVAL_OFST 0x4
198 /* The address of the ALT_TMR_TMR1CURVAL register. */
199 #define ALT_TMR_TMR1CURVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CURVAL_OFST))
200 
201 /*
202  * Register : timer1controlreg
203  *
204  * Name: Timer1 Control Register
205  *
206  * Size: 3 bits
207  *
208  * Address Offset: 8
209  *
210  * Read/Write Access: Read/Write
211  *
212  * This register controls enabling, operating mode (free-running or defined-count),
213  * and interrupt mask of
214  *
215  * Timer1. You can program each Timer1ControlReg to enable or disable a specific
216  * timer and to control
217  *
218  * its mode of operation.
219  *
220  * Register Layout
221  *
222  * Bits | Access | Reset | Description
223  * :-------|:-------|:------|:--------------------------------
224  * [0] | RW | 0x0 | ALT_TMR_TMR1CTLREG_TMR1_EN
225  * [1] | RW | 0x0 | ALT_TMR_TMR1CTLREG_TMR1_MOD
226  * [2] | RW | 0x0 | ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
227  * [31:3] | ??? | 0x0 | *UNDEFINED*
228  *
229  */
230 /*
231  * Field : timer1_enable
232  *
233  * Timer enable bit for Timer1.
234  *
235  * 0: disable
236  *
237  * 1: enable
238  *
239  * Field Enumeration Values:
240  *
241  * Enum | Value | Description
242  * :----------------------------------|:------|:----------------
243  * ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD | 0x0 | Timer1 Disabled
244  * ALT_TMR_TMR1CTLREG_TMR1_EN_E_END | 0x1 | Timer1 Enabled
245  *
246  * Field Access Macros:
247  *
248  */
249 /*
250  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
251  *
252  * Timer1 Disabled
253  */
254 #define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD 0x0
255 /*
256  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN
257  *
258  * Timer1 Enabled
259  */
260 #define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END 0x1
261 
262 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
263 #define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB 0
264 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
265 #define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB 0
266 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
267 #define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH 1
268 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
269 #define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK 0x00000001
270 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_EN register field value. */
271 #define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK 0xfffffffe
272 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_EN register field. */
273 #define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET 0x0
274 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_EN field value from a register. */
275 #define ALT_TMR_TMR1CTLREG_TMR1_EN_GET(value) (((value) & 0x00000001) >> 0)
276 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_EN register field value suitable for setting the register. */
277 #define ALT_TMR_TMR1CTLREG_TMR1_EN_SET(value) (((value) << 0) & 0x00000001)
278 
279 /*
280  * Field : timer1_mode
281  *
282  * Timer mode for Timer1.
283  *
284  * 0: free-running mode
285  *
286  * 1: user-defined count mode
287  *
288  * NOTE: You must set the Timer1LoadCount register to all 1s before
289  *
290  * enabling the timer in free-running mode.
291  *
292  * Field Enumeration Values:
293  *
294  * Enum | Value | Description
295  * :--------------------------------------|:------|:------------------------
296  * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN | 0x0 | Free-running mode
297  * ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF | 0x1 | User-defined count mode
298  *
299  * Field Access Macros:
300  *
301  */
302 /*
303  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
304  *
305  * Free-running mode
306  */
307 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN 0x0
308 /*
309  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD
310  *
311  * User-defined count mode
312  */
313 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF 0x1
314 
315 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
316 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB 1
317 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
318 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB 1
319 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
320 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH 1
321 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
322 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK 0x00000002
323 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value. */
324 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK 0xfffffffd
325 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field. */
326 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET 0x0
327 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_MOD field value from a register. */
328 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET(value) (((value) & 0x00000002) >> 1)
329 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_MOD register field value suitable for setting the register. */
330 #define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET(value) (((value) << 1) & 0x00000002)
331 
332 /*
333  * Field : timer1_interrupt_mask
334  *
335  * Timer interrupt mask for Timer1.
336  *
337  * 0: not masked
338  *
339  * 1: masked
340  *
341  * Field Enumeration Values:
342  *
343  * Enum | Value | Description
344  * :-------------------------------------------|:------|:-------------------------------
345  * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED | 0x0 | interrupt not masked (enabled)
346  * ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED | 0x1 | interrupt masked (disabled)
347  *
348  * Field Access Macros:
349  *
350  */
351 /*
352  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
353  *
354  * interrupt not masked (enabled)
355  */
356 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED 0x0
357 /*
358  * Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
359  *
360  * interrupt masked (disabled)
361  */
362 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED 0x1
363 
364 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
365 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB 2
366 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
367 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB 2
368 /* The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
369 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH 1
370 /* The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
371 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK 0x00000004
372 /* The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value. */
373 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK 0xfffffffb
374 /* The reset value of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field. */
375 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET 0x0
376 /* Extracts the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK field value from a register. */
377 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET(value) (((value) & 0x00000004) >> 2)
378 /* Produces a ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value suitable for setting the register. */
379 #define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET(value) (((value) << 2) & 0x00000004)
380 
381 #ifndef __ASSEMBLY__
382 /*
383  * WARNING: The C register and register group struct declarations are provided for
384  * convenience and illustrative purposes. They should, however, be used with
385  * caution as the C language standard provides no guarantees about the alignment or
386  * atomicity of device memory accesses. The recommended practice for writing
387  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
388  * alt_write_word() functions.
389  *
390  * The struct declaration for register ALT_TMR_TMR1CTLREG.
391  */
392 struct ALT_TMR_TMR1CTLREG_s
393 {
394  uint32_t timer1_enable : 1; /* ALT_TMR_TMR1CTLREG_TMR1_EN */
395  uint32_t timer1_mode : 1; /* ALT_TMR_TMR1CTLREG_TMR1_MOD */
396  uint32_t timer1_interrupt_mask : 1; /* ALT_TMR_TMR1CTLREG_TMR1_INT_MSK */
397  uint32_t : 29; /* *UNDEFINED* */
398 };
399 
400 /* The typedef declaration for register ALT_TMR_TMR1CTLREG. */
401 typedef volatile struct ALT_TMR_TMR1CTLREG_s ALT_TMR_TMR1CTLREG_t;
402 #endif /* __ASSEMBLY__ */
403 
404 /* The reset value of the ALT_TMR_TMR1CTLREG register. */
405 #define ALT_TMR_TMR1CTLREG_RESET 0x00000000
406 /* The byte offset of the ALT_TMR_TMR1CTLREG register from the beginning of the component. */
407 #define ALT_TMR_TMR1CTLREG_OFST 0x8
408 /* The address of the ALT_TMR_TMR1CTLREG register. */
409 #define ALT_TMR_TMR1CTLREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST))
410 
411 /*
412  * Register : timer1eoi
413  *
414  * Name: Timer1 End-of-Interrupt Register
415  *
416  * Size: 1 bit
417  *
418  * Address Offset: 12
419  *
420  * Read/Write Access: Read
421  *
422  * Register Layout
423  *
424  * Bits | Access | Reset | Description
425  * :-------|:-------|:------|:------------------------
426  * [0] | R | 0x0 | ALT_TMR_TMR1EOI_TMR1EOI
427  * [31:1] | ??? | 0x0 | *UNDEFINED*
428  *
429  */
430 /*
431  * Field : timer1eoi
432  *
433  * Reading from this register
434  *
435  * returns all zeroes (0) and clears the interrupt from Timer1.
436  *
437  * Field Access Macros:
438  *
439  */
440 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
441 #define ALT_TMR_TMR1EOI_TMR1EOI_LSB 0
442 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
443 #define ALT_TMR_TMR1EOI_TMR1EOI_MSB 0
444 /* The width in bits of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
445 #define ALT_TMR_TMR1EOI_TMR1EOI_WIDTH 1
446 /* The mask used to set the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
447 #define ALT_TMR_TMR1EOI_TMR1EOI_SET_MSK 0x00000001
448 /* The mask used to clear the ALT_TMR_TMR1EOI_TMR1EOI register field value. */
449 #define ALT_TMR_TMR1EOI_TMR1EOI_CLR_MSK 0xfffffffe
450 /* The reset value of the ALT_TMR_TMR1EOI_TMR1EOI register field. */
451 #define ALT_TMR_TMR1EOI_TMR1EOI_RESET 0x0
452 /* Extracts the ALT_TMR_TMR1EOI_TMR1EOI field value from a register. */
453 #define ALT_TMR_TMR1EOI_TMR1EOI_GET(value) (((value) & 0x00000001) >> 0)
454 /* Produces a ALT_TMR_TMR1EOI_TMR1EOI register field value suitable for setting the register. */
455 #define ALT_TMR_TMR1EOI_TMR1EOI_SET(value) (((value) << 0) & 0x00000001)
456 
457 #ifndef __ASSEMBLY__
458 /*
459  * WARNING: The C register and register group struct declarations are provided for
460  * convenience and illustrative purposes. They should, however, be used with
461  * caution as the C language standard provides no guarantees about the alignment or
462  * atomicity of device memory accesses. The recommended practice for writing
463  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
464  * alt_write_word() functions.
465  *
466  * The struct declaration for register ALT_TMR_TMR1EOI.
467  */
468 struct ALT_TMR_TMR1EOI_s
469 {
470  const uint32_t timer1eoi : 1; /* ALT_TMR_TMR1EOI_TMR1EOI */
471  uint32_t : 31; /* *UNDEFINED* */
472 };
473 
474 /* The typedef declaration for register ALT_TMR_TMR1EOI. */
475 typedef volatile struct ALT_TMR_TMR1EOI_s ALT_TMR_TMR1EOI_t;
476 #endif /* __ASSEMBLY__ */
477 
478 /* The reset value of the ALT_TMR_TMR1EOI register. */
479 #define ALT_TMR_TMR1EOI_RESET 0x00000000
480 /* The byte offset of the ALT_TMR_TMR1EOI register from the beginning of the component. */
481 #define ALT_TMR_TMR1EOI_OFST 0xc
482 /* The address of the ALT_TMR_TMR1EOI register. */
483 #define ALT_TMR_TMR1EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1EOI_OFST))
484 
485 /*
486  * Register : timer1intstat
487  *
488  * Name: Timer1 Interrupt Status Register
489  *
490  * Size: 1 bit
491  *
492  * Address Offset: 16
493  *
494  * Read/Write Access: Read
495  *
496  * Register Layout
497  *
498  * Bits | Access | Reset | Description
499  * :-------|:-------|:------|:--------------------------------
500  * [0] | R | 0x0 | ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
501  * [31:1] | ??? | 0x0 | *UNDEFINED*
502  *
503  */
504 /*
505  * Field : timer1intstat
506  *
507  * Contains the interrupt status for Timer1.
508  *
509  * Field Enumeration Values:
510  *
511  * Enum | Value | Description
512  * :----------------------------------------|:------|:-------------------------------
513  * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
514  * ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
515  *
516  * Field Access Macros:
517  *
518  */
519 /*
520  * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
521  *
522  * Timer1 interrupt is not active
523  */
524 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_INACT 0x0
525 /*
526  * Enumerated value for register field ALT_TMR_TMR1INTSTAT_TMR1INTSTAT
527  *
528  * Timer1 interrupt is active
529  */
530 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_E_ACT 0x1
531 
532 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
533 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_LSB 0
534 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
535 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_MSB 0
536 /* The width in bits of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
537 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_WIDTH 1
538 /* The mask used to set the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
539 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET_MSK 0x00000001
540 /* The mask used to clear the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value. */
541 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_CLR_MSK 0xfffffffe
542 /* The reset value of the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field. */
543 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_RESET 0x0
544 /* Extracts the ALT_TMR_TMR1INTSTAT_TMR1INTSTAT field value from a register. */
545 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_GET(value) (((value) & 0x00000001) >> 0)
546 /* Produces a ALT_TMR_TMR1INTSTAT_TMR1INTSTAT register field value suitable for setting the register. */
547 #define ALT_TMR_TMR1INTSTAT_TMR1INTSTAT_SET(value) (((value) << 0) & 0x00000001)
548 
549 #ifndef __ASSEMBLY__
550 /*
551  * WARNING: The C register and register group struct declarations are provided for
552  * convenience and illustrative purposes. They should, however, be used with
553  * caution as the C language standard provides no guarantees about the alignment or
554  * atomicity of device memory accesses. The recommended practice for writing
555  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
556  * alt_write_word() functions.
557  *
558  * The struct declaration for register ALT_TMR_TMR1INTSTAT.
559  */
560 struct ALT_TMR_TMR1INTSTAT_s
561 {
562  const uint32_t timer1intstat : 1; /* ALT_TMR_TMR1INTSTAT_TMR1INTSTAT */
563  uint32_t : 31; /* *UNDEFINED* */
564 };
565 
566 /* The typedef declaration for register ALT_TMR_TMR1INTSTAT. */
567 typedef volatile struct ALT_TMR_TMR1INTSTAT_s ALT_TMR_TMR1INTSTAT_t;
568 #endif /* __ASSEMBLY__ */
569 
570 /* The reset value of the ALT_TMR_TMR1INTSTAT register. */
571 #define ALT_TMR_TMR1INTSTAT_RESET 0x00000000
572 /* The byte offset of the ALT_TMR_TMR1INTSTAT register from the beginning of the component. */
573 #define ALT_TMR_TMR1INTSTAT_OFST 0x10
574 /* The address of the ALT_TMR_TMR1INTSTAT register. */
575 #define ALT_TMR_TMR1INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1INTSTAT_OFST))
576 
577 /*
578  * Register : timersintstat
579  *
580  * Name: Timers Interrupt Status Register
581  *
582  * Size: 1-9 bits
583  *
584  * Address Offset: 0xa0
585  *
586  * Read/Write Access: Read
587  *
588  * Register Layout
589  *
590  * Bits | Access | Reset | Description
591  * :-------|:-------|:------|:--------------------------------
592  * [0] | R | 0x0 | ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
593  * [31:1] | ??? | 0x0 | *UNDEFINED*
594  *
595  */
596 /*
597  * Field : timersintstat
598  *
599  * Contains the interrupt status of all timers in the component. If a bit of
600  *
601  * this register is 0, then the corresponding timer interrupt is not active
602  *
603  * and the corresponding interrupt could be on either the timer_intr bus
604  *
605  * or the timer_intr_n bus, depending on the interrupt polarity you have
606  *
607  * chosen. Similarly, if a bit of this register is 1, then the corresponding
608  *
609  * interrupt bit has been set in the relevant interrupt bus. In both cases,
610  *
611  * the status reported is the status after the interrupt mask has been
612  *
613  * applied. Reading from this register does not clear any active
614  *
615  * interrupts:
616  *
617  * 0 = either timer_intr or timer_intr_n is not active after masking
618  *
619  * 1 = either timer_intr or timer_intr_n is active after masking.
620  *
621  * Field Enumeration Values:
622  *
623  * Enum | Value | Description
624  * :----------------------------------------|:------|:-------------------------
625  * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT | 0x0 | timer_intr is not active
626  * ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT | 0x1 | timer_intr is active
627  *
628  * Field Access Macros:
629  *
630  */
631 /*
632  * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
633  *
634  * timer_intr is not active
635  */
636 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_INACT 0x0
637 /*
638  * Enumerated value for register field ALT_TMR_TMRSINTSTAT_TMRSINTSTAT
639  *
640  * timer_intr is active
641  */
642 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_E_ACT 0x1
643 
644 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
645 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_LSB 0
646 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
647 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_MSB 0
648 /* The width in bits of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
649 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_WIDTH 1
650 /* The mask used to set the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
651 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET_MSK 0x00000001
652 /* The mask used to clear the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value. */
653 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_CLR_MSK 0xfffffffe
654 /* The reset value of the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field. */
655 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_RESET 0x0
656 /* Extracts the ALT_TMR_TMRSINTSTAT_TMRSINTSTAT field value from a register. */
657 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
658 /* Produces a ALT_TMR_TMRSINTSTAT_TMRSINTSTAT register field value suitable for setting the register. */
659 #define ALT_TMR_TMRSINTSTAT_TMRSINTSTAT_SET(value) (((value) << 0) & 0x00000001)
660 
661 #ifndef __ASSEMBLY__
662 /*
663  * WARNING: The C register and register group struct declarations are provided for
664  * convenience and illustrative purposes. They should, however, be used with
665  * caution as the C language standard provides no guarantees about the alignment or
666  * atomicity of device memory accesses. The recommended practice for writing
667  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
668  * alt_write_word() functions.
669  *
670  * The struct declaration for register ALT_TMR_TMRSINTSTAT.
671  */
672 struct ALT_TMR_TMRSINTSTAT_s
673 {
674  const uint32_t timersintstat : 1; /* ALT_TMR_TMRSINTSTAT_TMRSINTSTAT */
675  uint32_t : 31; /* *UNDEFINED* */
676 };
677 
678 /* The typedef declaration for register ALT_TMR_TMRSINTSTAT. */
679 typedef volatile struct ALT_TMR_TMRSINTSTAT_s ALT_TMR_TMRSINTSTAT_t;
680 #endif /* __ASSEMBLY__ */
681 
682 /* The reset value of the ALT_TMR_TMRSINTSTAT register. */
683 #define ALT_TMR_TMRSINTSTAT_RESET 0x00000000
684 /* The byte offset of the ALT_TMR_TMRSINTSTAT register from the beginning of the component. */
685 #define ALT_TMR_TMRSINTSTAT_OFST 0xa0
686 /* The address of the ALT_TMR_TMRSINTSTAT register. */
687 #define ALT_TMR_TMRSINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSINTSTAT_OFST))
688 
689 /*
690  * Register : timerseoi
691  *
692  * Name: Timers End-of-Interrupt Register
693  *
694  * Size: 1-9 bits
695  *
696  * Address Offset: 0xa4
697  *
698  * Read/Write Access: Read
699  *
700  * Register Layout
701  *
702  * Bits | Access | Reset | Description
703  * :-------|:-------|:------|:------------------------
704  * [0] | R | 0x0 | ALT_TMR_TMRSEOI_TMRSEOI
705  * [31:1] | ??? | 0x0 | *UNDEFINED*
706  *
707  */
708 /*
709  * Field : timerseoi
710  *
711  * Reading this register returns all zeroes (0) and clears all active
712  *
713  * interrupts.
714  *
715  * Field Access Macros:
716  *
717  */
718 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
719 #define ALT_TMR_TMRSEOI_TMRSEOI_LSB 0
720 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
721 #define ALT_TMR_TMRSEOI_TMRSEOI_MSB 0
722 /* The width in bits of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
723 #define ALT_TMR_TMRSEOI_TMRSEOI_WIDTH 1
724 /* The mask used to set the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
725 #define ALT_TMR_TMRSEOI_TMRSEOI_SET_MSK 0x00000001
726 /* The mask used to clear the ALT_TMR_TMRSEOI_TMRSEOI register field value. */
727 #define ALT_TMR_TMRSEOI_TMRSEOI_CLR_MSK 0xfffffffe
728 /* The reset value of the ALT_TMR_TMRSEOI_TMRSEOI register field. */
729 #define ALT_TMR_TMRSEOI_TMRSEOI_RESET 0x0
730 /* Extracts the ALT_TMR_TMRSEOI_TMRSEOI field value from a register. */
731 #define ALT_TMR_TMRSEOI_TMRSEOI_GET(value) (((value) & 0x00000001) >> 0)
732 /* Produces a ALT_TMR_TMRSEOI_TMRSEOI register field value suitable for setting the register. */
733 #define ALT_TMR_TMRSEOI_TMRSEOI_SET(value) (((value) << 0) & 0x00000001)
734 
735 #ifndef __ASSEMBLY__
736 /*
737  * WARNING: The C register and register group struct declarations are provided for
738  * convenience and illustrative purposes. They should, however, be used with
739  * caution as the C language standard provides no guarantees about the alignment or
740  * atomicity of device memory accesses. The recommended practice for writing
741  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
742  * alt_write_word() functions.
743  *
744  * The struct declaration for register ALT_TMR_TMRSEOI.
745  */
746 struct ALT_TMR_TMRSEOI_s
747 {
748  const uint32_t timerseoi : 1; /* ALT_TMR_TMRSEOI_TMRSEOI */
749  uint32_t : 31; /* *UNDEFINED* */
750 };
751 
752 /* The typedef declaration for register ALT_TMR_TMRSEOI. */
753 typedef volatile struct ALT_TMR_TMRSEOI_s ALT_TMR_TMRSEOI_t;
754 #endif /* __ASSEMBLY__ */
755 
756 /* The reset value of the ALT_TMR_TMRSEOI register. */
757 #define ALT_TMR_TMRSEOI_RESET 0x00000000
758 /* The byte offset of the ALT_TMR_TMRSEOI register from the beginning of the component. */
759 #define ALT_TMR_TMRSEOI_OFST 0xa4
760 /* The address of the ALT_TMR_TMRSEOI register. */
761 #define ALT_TMR_TMRSEOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSEOI_OFST))
762 
763 /*
764  * Register : timersrawintstat
765  *
766  * Name: Timers Raw Interrupt Status Register
767  *
768  * Size: 1-9 bits
769  *
770  * Address Offset: 0xa8
771  *
772  * Read/Write Access: Read
773  *
774  * Register Layout
775  *
776  * Bits | Access | Reset | Description
777  * :-------|:-------|:------|:--------------------------------------
778  * [0] | R | 0x0 | ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
779  * [31:1] | ??? | 0x0 | *UNDEFINED*
780  *
781  */
782 /*
783  * Field : timersrawintstat
784  *
785  * The register contains the unmasked interrupt status of all timers in
786  *
787  * the component.
788  *
789  * 0 = either timer_intr or timer_intr_n is not active prior to masking
790  *
791  * 1 = either timer_intr or timer_intr_n is active prior to masking.
792  *
793  * Field Enumeration Values:
794  *
795  * Enum | Value | Description
796  * :----------------------------------------------|:------|:-------------------------------
797  * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT | 0x0 | Timer1 interrupt is not active
798  * ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT | 0x1 | Timer1 interrupt is active
799  *
800  * Field Access Macros:
801  *
802  */
803 /*
804  * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
805  *
806  * Timer1 interrupt is not active
807  */
808 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_INACT 0x0
809 /*
810  * Enumerated value for register field ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT
811  *
812  * Timer1 interrupt is active
813  */
814 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_E_ACT 0x1
815 
816 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
817 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_LSB 0
818 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
819 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_MSB 0
820 /* The width in bits of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
821 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_WIDTH 1
822 /* The mask used to set the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
823 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET_MSK 0x00000001
824 /* The mask used to clear the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value. */
825 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_CLR_MSK 0xfffffffe
826 /* The reset value of the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field. */
827 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_RESET 0x0
828 /* Extracts the ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT field value from a register. */
829 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
830 /* Produces a ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT register field value suitable for setting the register. */
831 #define ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT_SET(value) (((value) << 0) & 0x00000001)
832 
833 #ifndef __ASSEMBLY__
834 /*
835  * WARNING: The C register and register group struct declarations are provided for
836  * convenience and illustrative purposes. They should, however, be used with
837  * caution as the C language standard provides no guarantees about the alignment or
838  * atomicity of device memory accesses. The recommended practice for writing
839  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
840  * alt_write_word() functions.
841  *
842  * The struct declaration for register ALT_TMR_TMRSRAWINTSTAT.
843  */
844 struct ALT_TMR_TMRSRAWINTSTAT_s
845 {
846  const uint32_t timersrawintstat : 1; /* ALT_TMR_TMRSRAWINTSTAT_TMRSRAWINTSTAT */
847  uint32_t : 31; /* *UNDEFINED* */
848 };
849 
850 /* The typedef declaration for register ALT_TMR_TMRSRAWINTSTAT. */
851 typedef volatile struct ALT_TMR_TMRSRAWINTSTAT_s ALT_TMR_TMRSRAWINTSTAT_t;
852 #endif /* __ASSEMBLY__ */
853 
854 /* The reset value of the ALT_TMR_TMRSRAWINTSTAT register. */
855 #define ALT_TMR_TMRSRAWINTSTAT_RESET 0x00000000
856 /* The byte offset of the ALT_TMR_TMRSRAWINTSTAT register from the beginning of the component. */
857 #define ALT_TMR_TMRSRAWINTSTAT_OFST 0xa8
858 /* The address of the ALT_TMR_TMRSRAWINTSTAT register. */
859 #define ALT_TMR_TMRSRAWINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSRAWINTSTAT_OFST))
860 
861 /*
862  * Register : timerscompversion
863  *
864  * Name: Timers Component Version
865  *
866  * Size: 32 bits
867  *
868  * Address Offset: 0xac
869  *
870  * Read/Write Access: Read
871  *
872  * Register Layout
873  *
874  * Bits | Access | Reset | Description
875  * :-------|:-------|:-----------|:--------------------------------
876  * [31:0] | R | 0x3230382a | ALT_TMR_TMRSCOMPVER_TMRSCOMPVER
877  *
878  */
879 /*
880  * Field : timerscompversion
881  *
882  * Current revision number of the DW_apb_timers component.
883  *
884  * Field Access Macros:
885  *
886  */
887 /* The Least Significant Bit (LSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
888 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_LSB 0
889 /* The Most Significant Bit (MSB) position of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
890 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_MSB 31
891 /* The width in bits of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
892 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_WIDTH 32
893 /* The mask used to set the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
894 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET_MSK 0xffffffff
895 /* The mask used to clear the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value. */
896 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_CLR_MSK 0x00000000
897 /* The reset value of the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field. */
898 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_RESET 0x3230382a
899 /* Extracts the ALT_TMR_TMRSCOMPVER_TMRSCOMPVER field value from a register. */
900 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_GET(value) (((value) & 0xffffffff) >> 0)
901 /* Produces a ALT_TMR_TMRSCOMPVER_TMRSCOMPVER register field value suitable for setting the register. */
902 #define ALT_TMR_TMRSCOMPVER_TMRSCOMPVER_SET(value) (((value) << 0) & 0xffffffff)
903 
904 #ifndef __ASSEMBLY__
905 /*
906  * WARNING: The C register and register group struct declarations are provided for
907  * convenience and illustrative purposes. They should, however, be used with
908  * caution as the C language standard provides no guarantees about the alignment or
909  * atomicity of device memory accesses. The recommended practice for writing
910  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
911  * alt_write_word() functions.
912  *
913  * The struct declaration for register ALT_TMR_TMRSCOMPVER.
914  */
915 struct ALT_TMR_TMRSCOMPVER_s
916 {
917  const uint32_t timerscompversion : 32; /* ALT_TMR_TMRSCOMPVER_TMRSCOMPVER */
918 };
919 
920 /* The typedef declaration for register ALT_TMR_TMRSCOMPVER. */
921 typedef volatile struct ALT_TMR_TMRSCOMPVER_s ALT_TMR_TMRSCOMPVER_t;
922 #endif /* __ASSEMBLY__ */
923 
924 /* The reset value of the ALT_TMR_TMRSCOMPVER register. */
925 #define ALT_TMR_TMRSCOMPVER_RESET 0x3230382a
926 /* The byte offset of the ALT_TMR_TMRSCOMPVER register from the beginning of the component. */
927 #define ALT_TMR_TMRSCOMPVER_OFST 0xac
928 /* The address of the ALT_TMR_TMRSCOMPVER register. */
929 #define ALT_TMR_TMRSCOMPVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMRSCOMPVER_OFST))
930 
931 #ifndef __ASSEMBLY__
932 /*
933  * WARNING: The C register and register group struct declarations are provided for
934  * convenience and illustrative purposes. They should, however, be used with
935  * caution as the C language standard provides no guarantees about the alignment or
936  * atomicity of device memory accesses. The recommended practice for writing
937  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
938  * alt_write_word() functions.
939  *
940  * The struct declaration for register group ALT_TMR.
941  */
942 struct ALT_TMR_s
943 {
944  ALT_TMR_TMR1LDCOUNT_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
945  ALT_TMR_TMR1CURVAL_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
946  ALT_TMR_TMR1CTLREG_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
947  ALT_TMR_TMR1EOI_t timer1eoi; /* ALT_TMR_TMR1EOI */
948  ALT_TMR_TMR1INTSTAT_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
949  volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
950  ALT_TMR_TMRSINTSTAT_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
951  ALT_TMR_TMRSEOI_t timerseoi; /* ALT_TMR_TMRSEOI */
952  ALT_TMR_TMRSRAWINTSTAT_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
953  ALT_TMR_TMRSCOMPVER_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
954  volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
955 };
956 
957 /* The typedef declaration for register group ALT_TMR. */
958 typedef volatile struct ALT_TMR_s ALT_TMR_t;
959 /* The struct declaration for the raw register contents of register group ALT_TMR. */
960 struct ALT_TMR_raw_s
961 {
962  volatile uint32_t timer1loadcount; /* ALT_TMR_TMR1LDCOUNT */
963  volatile uint32_t timer1currentval; /* ALT_TMR_TMR1CURVAL */
964  volatile uint32_t timer1controlreg; /* ALT_TMR_TMR1CTLREG */
965  volatile uint32_t timer1eoi; /* ALT_TMR_TMR1EOI */
966  volatile uint32_t timer1intstat; /* ALT_TMR_TMR1INTSTAT */
967  uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
968  volatile uint32_t timersintstat; /* ALT_TMR_TMRSINTSTAT */
969  volatile uint32_t timerseoi; /* ALT_TMR_TMRSEOI */
970  volatile uint32_t timersrawintstat; /* ALT_TMR_TMRSRAWINTSTAT */
971  volatile uint32_t timerscompversion; /* ALT_TMR_TMRSCOMPVER */
972  uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
973 };
974 
975 /* The typedef declaration for the raw register contents of register group ALT_TMR. */
976 typedef volatile struct ALT_TMR_raw_s ALT_TMR_raw_t;
977 #endif /* __ASSEMBLY__ */
978 
979 
980 #ifdef __cplusplus
981 }
982 #endif /* __cplusplus */
983 #endif /* __ALT_SOCAL_TMR_H__ */
984