Hardware Libraries  20.1
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alt_eth_phy_ksz9031.h
1 /******************************************************************************
2  *
3  * Copyright 2017 Altera Corporation. All Rights Reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its contributors
16  * may be used to endorse or promote products derived from this software without
17  * specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  ******************************************************************************/
32 
33 #ifndef __ALT_PHY_KSZ9031_H__
34 #define __ALT_PHY_KSZ9031_H__
35 
36 #include "hwlib.h"
37 #include "socal/hps.h"
38 #include "socal/alt_emac.h"
39 
40 #ifdef __cplusplus
41 extern "C"
42 {
43 #endif /* __cplusplus */
44 
45 /******************************************************************************/
46 /* There are 3 functions required to support a phy for use with the Ethernet API.
47  * The format and function of the 3 functions is specified in more detail in alt_ethernet.h.
48  * The 3 functions:
49  * ALT_STATUS_CODE alt_eth_phy_config(uint32_t instance);
50  * ALT_STATUS_CODE alt_eth_phy_reset(uint32_t instance);
51  * ALT_STATUS_CODE alt_eth_phy_get_duplex_and_speed(uint32_t * phy_duplex_status, uint32_t * phy_speed, uint32_t instance);
52  *
53  * To use a phy different than alt_eth_phy_ksz9031.c, simply create a C file containing
54  * the 3 functions and include it in your build instead of the alt_eth_phy_ksz9031.c file.
55 */
56 
57 /* Within a phy, there are some parameters that may change based upon the devkit or board.
58  This file supports the S10 DevKit. The parameters which may change based on board follow: */
59 #ifdef SIMICS
60 #define EMAC0_PHY_ADDRESS (0)
61 #else
62 #define EMAC0_PHY_ADDRESS (4)
63 #endif
64 
65 #define EMAC1_PHY_ADDRESS (0) /* no phy */
66 #define EMAC2_PHY_ADDRESS (0) /* no phy */
67 
68 /* Micrel KSZ9031 Extended registers */
69 #define PHY_CONTROL_PAD_SKEW_REG (4)
70 #define PHY_CONTROL_PAD_SKEW_VALUE (0x70)
71 #define PHY_RX_DATA_PAD_SKEW_REG (5)
72 #define PHY_RX_DATA_PAD_SKEW_VALUE (0x7777)
73 #define PHY_TX_DATA_PAD_SKEW_REG (6)
74 #define PHY_TX_DATA_PAD_SKEW_VALUE (0x0)
75 #define PHY_CLK_PAD_SKEW_REG (8)
76 #define PHY_CLK_PAD_SKEW_VALUE (0x3FC)
77 
78 /* Auto-Negotiation FLP burst transmit timing */
79 #define PHY_MMD_D0_FLP_LO_REG (3)
80 #define PHY_MMD_D0_FLP_16MS_LO (0x1A80)
81 #define PHY_MMD_D0_FLP_HI_REG (4)
82 #define PHY_MMD_D0_FLP_16MS_HI (0x0006)
83 /* End of ksz9031 parameters that may change based on DevKit or Board */
84 /******************************************************************************/
85 
86 
87 /* PHY_Read_write_Timeouts */
88 #define PHY_READ_TO ((uint32_t)0x0004FFFF)
89 #define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
90 
91 /* PHY_Register_address */
92 #define PHY_BCR (0)
93 #define PHY_BSR (1)
94 #define PHY_ID1 (2)
95 #define PHY_ID2 (3)
96 #define PHY_AUTON (4)
97 #define PHY_1GCTL (9)
98 #define PHY_1GSTS (10)
99 #define PHY_CR (31)
101 /* PHY Reset delay */
102 #define PHY_RESET_DELAY ((uint32_t)0x000FFFFF)
103 
104 /* Speed and Duplex mask values */
105 #define PHY_SPEED_10 (0x0010)
106 #define PHY_SPEED_100 (0x0020)
107 #define PHY_SPEED_1000 (0x0040)
108 #define PHY_SPEED_MASK (0x0070)
109 #define PHY_DUPLEX_STATUS (0x0008)
110 
111 /* 1000BASE-T Control register */
112 #define PHYADVERTISE_1000FULL (0x0200) /* Advertise 1000BASE-T full duplex */
113 #define PHYADVERTISE_1000HALF (0x0100) /* Advertise 1000BASE-T half duplex */
114 
115 /* PHY Auto-Negotiation advertisement */
116 #define PHYANA_SEL_MASK (0x1F) /* Link type selector */
117 #define PHYANA_10BASET (1 << 5) /* Advertise 10BASET capability */
118 #define PHYANA_10BASETFD (1 << 6) /* Advertise 10BASET Full duplex capability */
119 #define PHYANA_100BASETX (1 << 7) /* Advertise 100BASETX capability */
120 #define PHYANA_100BASETXFD (1 << 8) /* Advertise 100 BASETX Full duplex capability */
121 #define PHYANA_PAUSE_OP_MASK (3 << 10) /* Advertise PAUSE frame capability */
122 #define PHYANA_REMOTE_FAULT (1 << 13) /* Remote fault detected */
123 
124 /* Data operations */
125 #define PHY_MOD_DATA_NO_POST_INC (0x1)
126 #define PHY_MOD_DATA_POST_INC_RW (0x2)
127 #define PHY_MOD_DATA_POST_INC_W (0x3)
128 
129 #define PHY_MMD_CTRL_REG (0x0d)
130 #define PHY_MMD_REGDATA_REG (0x0e)
131 
132 #define PHY_MMD_DEV_ADDR_02 (2)
133 #define PHY_MMD_DEV_ADDR_00 (0)
134 
135 /* PHY_basic_Control_register */
136 #define PHY_COLLTEST (1 << 7 ) /* Collision test enable */
137 #define PHY_DUPLEX_MODE (1 << 8 ) /* Set Duplex Mode */
138 #define PHY_RESTART_AUTONEGOTIATION (1 << 9 ) /* Restart Auto-Negotiation of Link abilities */
139 #define PHY_POWERDOWN (1 << 11) /* Power-Down switch */
140 #define PHY_AUTONEGOTIATION (1 << 12) /* Auto-Negotiation Enable */
141 #define PHY_SPEEDSEL (1 << 13) /* Link Speed Selection */
142 #define PHY_LOOPBACK (1 << 14) /* Set loopback mode */
143 #define PHY_RESET (1 << 15) /* Do a PHY reset */
144 
146 #define PHY_AUTONEGO_COMPLETE (0x0020)
147 #define PHY_LINKED_STATUS (0x0004)
148 #define PHY_JABBER_DETECTION (0x0002)
149 #define PHY_AUTOCAP (0x0008)
151 /******************************************************************************/
152 
166 ALT_STATUS_CODE alt_eth_phy_write_register(uint32_t emac_instance, uint32_t phy_reg, uint32_t wrval);
167 
168 /******************************************************************************/
183 ALT_STATUS_CODE alt_eth_phy_read_register(uint32_t emac_instance, uint32_t phy_reg, uint32_t * rdval);
184 
185 /******************************************************************************/
202 ALT_STATUS_CODE alt_eth_phy_read_register_extended(uint32_t emac_instance, uint32_t dev_addr, uint32_t phy_reg, uint32_t * rdval);
203 
204 /******************************************************************************/
221 ALT_STATUS_CODE alt_eth_phy_write_register_extended(uint32_t emac_instance, uint32_t dev_addr, uint32_t phy_reg, uint32_t wrval);
222 
223 /******************************************************************************/
236 ALT_STATUS_CODE alt_eth_phy_loopback(uint32_t new_state, uint32_t emac_instance);
237 
238 #ifdef __cplusplus
239 }
240 #endif /* __cplusplus */
241 
242 #endif /* __ALT_PHY_KSZ9031_H__ */