Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
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alt_spi.h File Reference
#include "hwlib.h"
#include "alt_clock_manager.h"
#include "socal/alt_spis.h"
#include "socal/alt_spim.h"
#include "socal/alt_sysmgr.h"
#include "socal/hps.h"
#include "socal/socal.h"

Go to the source code of this file.

Detailed Description

Altera - SPI Flash Controller Module

Data Structures

struct  ALT_SPI_CONFIG_s
 
struct  ALT_SPI_MW_CONFIG_s
 

Macros

#define ALT_SPI_MW_CTL_FRAME_SIZE_MAX   (16)
 
#define ALT_SPI_SLAVE_MASK_ALL   0xF
 
#define ALT_SPI_RXD_SAMPLE_DELAY_MAX   4
 
#define ALT_SPI_RX_FIFO_NUM_ENTRIES   256
 
#define ALT_SPI_TX_FIFO_NUM_ENTRIES   256
 

Typedefs

typedef enum ALT_SPI_CTLR_e ALT_SPI_CTLR_t
 
typedef enum ALT_SPI_FRF_e ALT_SPI_FRF_t
 
typedef enum ALT_SPI_SCPOL_e ALT_SPI_SCPOL_t
 
typedef enum ALT_SPI_SCPH_e ALT_SPI_SCPH_t
 
typedef enum ALT_SPI_DFS_e ALT_SPI_DFS_t
 
typedef enum ALT_SPI_TMOD_e ALT_SPI_TMOD_t
 
typedef enum ALT_SPI_OP_MODE_e ALT_SPI_OP_MODE_t
 
typedef enum ALT_SPI_MW_MODE_e ALT_SPI_MW_MODE_t
 
typedef enum ALT_SPI_SS_e ALT_SPI_SS_t
 
typedef enum ALT_SPI_MW_DIR_e ALT_SPI_MW_DIR_t
 
typedef enum ALT_SPI_STATUS_e ALT_SPI_STATUS_t
 

Enumerations

enum  ALT_SPI_CTLR_e { ALT_SPI_SPIM0 = 0, ALT_SPI_SPIM1 = 1, ALT_SPI_SPIS0 = 2, ALT_SPI_SPIS1 = 3 }
 
enum  ALT_SPI_FRF_e { ALT_SPI_FRF_SPI = 0, ALT_SPI_FRF_SSP = 1, ALT_SPI_FRF_MICROWIRE = 2 }
 
enum  ALT_SPI_SCPOL_e { ALT_SPI_SCPOL_INACTIVE_LOW = 0, ALT_SPI_SCPOL_INACTIVE_HIGH = 1 }
 
enum  ALT_SPI_SCPH_e { ALT_SPI_SCPH_TOGGLE_MIDDLE = 0, ALT_SPI_SCPH_TOGGLE_START = 1 }
 
enum  ALT_SPI_DFS_e {
  ALT_SPI_DFS_4BIT = 3, ALT_SPI_DFS_5BIT = 4, ALT_SPI_DFS_6BIT = 5, ALT_SPI_DFS_7BIT = 6,
  ALT_SPI_DFS_8BIT = 7, ALT_SPI_DFS_9BIT = 8, ALT_SPI_DFS_10BIT = 9, ALT_SPI_DFS_11BIT = 10,
  ALT_SPI_DFS_12BIT = 11, ALT_SPI_DFS_13BIT = 12, ALT_SPI_DFS_14BIT = 13, ALT_SPI_DFS_15BIT = 14,
  ALT_SPI_DFS_16BIT = 15
}
 
enum  ALT_SPI_TMOD_e { ALT_SPI_TMOD_TXRX = 0, ALT_SPI_TMOD_TX = 1, ALT_SPI_TMOD_RX = 2, ALT_SPI_TMOD_EEPROM = 3 }
 
enum  ALT_SPI_OP_MODE_e { ALT_SPI_OP_MODE_SLAVE = 0, ALT_SPI_OP_MODE_MASTER = 1 }
 
enum  ALT_SPI_MW_MODE_e { ALT_SPI_MW_NON_SEQUENTIAL = 0, ALT_SPI_MW_SEQUENTIAL = 1 }
 
enum  ALT_SPI_SS_e { ALT_SPI_SS0 = 1UL << 0, ALT_SPI_SS1 = 1UL << 1, ALT_SPI_SS2 = 1UL << 2, ALT_SPI_SS3 = 1UL << 3 }
 
enum  ALT_SPI_MW_DIR_e { ALT_SPI_MW_DIR_RX = 0, ALT_SPI_MW_DIR_TX = 1 }
 
enum  ALT_SPI_STATUS_e {
  ALT_SPI_STATUS_TXEI = 1UL << 0, ALT_SPI_STATUS_TXOI = 1UL << 1, ALT_SPI_STATUS_RXUI = 1UL << 2, ALT_SPI_STATUS_RXOI = 1UL << 3,
  ALT_SPI_STATUS_RXFI = 1UL << 4, ALT_SPI_STATUS_ALL = 0x1f
}
 

Functions

struct ALT_SPI_CONFIG_s __attribute__ ((aligned(4))) ALT_SPI_CONFIG_t
 
ALT_STATUS_CODE alt_spi_init (const ALT_SPI_CTLR_t spi, ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_reset (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_uninit (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_disable (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_enable (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_is_enabled (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_is_busy (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_config_get (ALT_SPI_DEV_t *spi_dev, ALT_SPI_CONFIG_t *cfg)
 
ALT_STATUS_CODE alt_spi_config_set (ALT_SPI_DEV_t *spi_dev, const ALT_SPI_CONFIG_t *cfg)
 
ALT_STATUS_CODE alt_spi_mw_config_get (ALT_SPI_DEV_t *spi_dev, ALT_SPI_MW_CONFIG_t *cfg)
 
ALT_STATUS_CODE alt_spi_mw_config_set (ALT_SPI_DEV_t *spi_dev, const ALT_SPI_MW_CONFIG_t *cfg)
 
ALT_STATUS_CODE alt_spi_slave_select_disable (ALT_SPI_DEV_t *spi_dev, const uint32_t mask)
 
ALT_STATUS_CODE alt_spi_slave_select_enable (ALT_SPI_DEV_t *spi_dev, const uint32_t mask)
 
ALT_STATUS_CODE alt_spi_divider_get (ALT_SPI_DEV_t *spi_dev, uint32_t *div)
 
ALT_STATUS_CODE alt_spi_divider_set (ALT_SPI_DEV_t *spi_dev, const uint32_t div)
 
ALT_STATUS_CODE alt_spi_speed_get (ALT_SPI_DEV_t *spi_dev, uint32_t *speed_in_hz)
 
ALT_STATUS_CODE alt_spi_speed_set (ALT_SPI_DEV_t *spi_dev, uint32_t speed_in_hz)
 
ALT_STATUS_CODE alt_spi_num_data_frames_get (ALT_SPI_DEV_t *spi_dev, uint32_t *num_data_frames)
 
ALT_STATUS_CODE alt_spi_num_data_frames_set (ALT_SPI_DEV_t *spi_dev, const uint32_t num_data_frames)
 
ALT_STATUS_CODE alt_spi_int_status_get (ALT_SPI_DEV_t *spi_dev, uint32_t *status)
 
ALT_STATUS_CODE alt_spi_int_raw_status_get (ALT_SPI_DEV_t *spi_dev, uint32_t *status)
 
ALT_STATUS_CODE alt_spi_int_clear (ALT_SPI_DEV_t *spi_dev, const uint32_t mask)
 
ALT_STATUS_CODE alt_spi_int_disable (ALT_SPI_DEV_t *spi_dev, const uint32_t mask)
 
ALT_STATUS_CODE alt_spi_int_enable (ALT_SPI_DEV_t *spi_dev, const uint32_t mask)
 
ALT_STATUS_CODE alt_spi_rx_sample_delay_get (ALT_SPI_DEV_t *spi_dev, uint32_t *delay)
 
ALT_STATUS_CODE alt_spi_rx_sample_delay_set (ALT_SPI_DEV_t *spi_dev, const uint32_t delay)
 
ALT_STATUS_CODE alt_spi_rx_fifo_deq (ALT_SPI_DEV_t *spi_dev, uint16_t *data)
 
ALT_STATUS_CODE alt_spi_rx_fifo_is_empty (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_rx_fifo_is_full (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_rx_fifo_level_get (ALT_SPI_DEV_t *spi_dev, uint32_t *num_entries)
 
ALT_STATUS_CODE alt_spi_rx_fifo_threshold_get (ALT_SPI_DEV_t *spi_dev, uint8_t *threshold)
 
ALT_STATUS_CODE alt_spi_rx_fifo_threshold_set (ALT_SPI_DEV_t *spi_dev, const uint8_t threshold)
 
ALT_STATUS_CODE alt_spi_tx_fifo_enq (ALT_SPI_DEV_t *spi_dev, const uint16_t data)
 
ALT_STATUS_CODE alt_spi_tx_fifo_is_empty (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_tx_fifo_is_full (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_tx_fifo_level_get (ALT_SPI_DEV_t *spi_dev, uint32_t *num_entries)
 
ALT_STATUS_CODE alt_spi_tx_fifo_threshold_get (ALT_SPI_DEV_t *spi_dev, uint8_t *threshold)
 
ALT_STATUS_CODE alt_spi_tx_fifo_threshold_set (ALT_SPI_DEV_t *spi_dev, const uint8_t threshold)
 
ALT_STATUS_CODE alt_spi_master_tx_rx_transfer (ALT_SPI_DEV_t *spi_dev, const uint32_t slave_select, const size_t num_frames, const uint16_t *tx_buf, uint16_t *rx_buf)
 
ALT_STATUS_CODE alt_spi_master_tx_transfer (ALT_SPI_DEV_t *spi_dev, const uint32_t slave_select, const size_t num_frames, const uint16_t *tx_buf)
 
ALT_STATUS_CODE alt_spi_master_rx_transfer (ALT_SPI_DEV_t *spi_dev, const uint32_t slave_select, const size_t num_frames, uint16_t *rx_buf)
 
ALT_STATUS_CODE alt_spi_master_eeprom_transfer (ALT_SPI_DEV_t *spi_dev, const uint32_t slave_select, const uint8_t opcode, const uint16_t eeprom_addr, const size_t num_frames, uint16_t *rx_buf)
 
ALT_STATUS_CODE alt_spi_slave_tx_rx_transfer (ALT_SPI_DEV_t *spi_dev, const uint16_t *tx_buf, uint16_t *rx_buf, const size_t buf_len)
 
ALT_STATUS_CODE alt_spi_slave_tx_transfer (ALT_SPI_DEV_t *spi_dev, const uint16_t *tx_buf, const size_t buf_len)
 
ALT_STATUS_CODE alt_spi_slave_rx_transfer (ALT_SPI_DEV_t *spi_dev, uint16_t *rx_buf, const size_t buf_len)
 
ALT_STATUS_CODE alt_spi_dma_tx_disable (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_dma_tx_enable (ALT_SPI_DEV_t *spi_dev, const uint32_t level)
 
ALT_STATUS_CODE alt_spi_dma_rx_disable (ALT_SPI_DEV_t *spi_dev)
 
ALT_STATUS_CODE alt_spi_dma_rx_enable (ALT_SPI_DEV_t *spi_dev, const uint32_t level)
 

Variables

ALT_SPI_DFS_t frame_size
 
ALT_SPI_FRF_t frame_format
 
ALT_SPI_SCPH_t clk_phase
 
ALT_SPI_SCPOL_t clk_polarity
 
ALT_SPI_TMOD_t transfer_mode
 
bool slave_output_enable
 
bool loopback_mode
 
uint32_t ctl_frame_size
 
ALT_SPI_MW_MODE_t mode
 
ALT_SPI_MW_DIR_t dir
 
bool handshake_enabled
 

Variable Documentation

ALT_SPI_DFS_t frame_size

Data Frame Size. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. Valid range 4..16.

ALT_SPI_FRF_t frame_format

Frame Format. Selects which serial protocol transfers the data.

ALT_SPI_SCPH_t clk_phase

Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal.

ALT_SPI_SCPOL_t clk_polarity

Serial Clock Polarity. Only valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock.

ALT_SPI_TMOD_t transfer_mode

Transfer Mode. Selects the mode of transfer for serial communication.

bool slave_output_enable

Slave Output Enable. Relevant only for SPI controller slaves. This data member has no applicability for SPI controller masters. This data member specifies whether the ssi_oe_n output is enabled or disabled from the SPI controller slave. When true, the ssi_oe_n output can never be active. When the ssi_oe_n output controls the tri-state buffer on the txd output from the slave, a high impedance state is always present on the slave txd output when slv_oe = true. This is useful when the master transmits in broadcast mode. Only one slave may respond with data on the master rxd line. This data member is enabled after reset and must be disabled by software (when broadcast mode is used), if you do not want this device to respond with data.

bool loopback_mode

Used for testing purposes only. When true, creates an internal loopback by connecting the transmit shift register output to the receive shift register input. Can be used in both serial- slave and serial-master modes. For SPI controller slaves in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back. For normal operation this data member should be set to false.

uint32_t ctl_frame_size

Control Frame Size. Selects the length of the control word for the Microwire frame format. Valid range 0 <= n <= 16 where n sets the bit field to n - 1.

Transfer Mode. Specifies whether the Microwire transfer is sequential or non-sequential.

Direction. This setting controls the direction of the data word for the half-duplex Microwire serial protocol.

bool handshake_enabled

Microwire handshaking enable flag. Relevant only when the SPI controller is a master. Used to enable and disable the "busy/ready" handshaking interface for the Microwire protocol. When enabled (true), the SPI controller checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the controller busy status.