35 #ifndef __ALTERA_ALT_NAND_H__
36 #define __ALTERA_ALT_NAND_H__
86 #define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
88 #define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
90 #define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
92 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
94 #define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
96 #define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
98 #define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
100 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
112 #define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
114 #define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
116 #define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
118 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
120 #define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
122 #define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
124 #define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
126 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
138 #define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
140 #define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
142 #define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
144 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
146 #define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
148 #define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
150 #define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
152 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
164 #define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
166 #define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
168 #define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
170 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
172 #define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
174 #define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
176 #define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
178 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
191 struct ALT_NAND_CFG_DEVICE_RST_s
201 typedef volatile struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t;
205 #define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
232 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
234 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
236 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
238 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
240 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
242 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
244 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
246 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
259 struct ALT_NAND_CFG_TFR_SPARE_REG_s
266 typedef volatile struct ALT_NAND_CFG_TFR_SPARE_REG_s ALT_NAND_CFG_TFR_SPARE_REG_t;
270 #define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
300 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
302 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
304 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
306 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
308 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
310 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
312 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
314 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
327 struct ALT_NAND_CFG_LD_WAIT_CNT_s
334 typedef volatile struct ALT_NAND_CFG_LD_WAIT_CNT_s ALT_NAND_CFG_LD_WAIT_CNT_t;
338 #define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
369 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
371 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
373 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
375 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
377 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
379 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f4
381 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
383 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
396 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
403 typedef volatile struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
407 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
438 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
440 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
442 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
444 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
446 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
448 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f4
450 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
452 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
465 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
472 typedef volatile struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
476 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
502 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
504 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
506 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
508 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
510 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
512 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
514 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
516 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
529 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
536 typedef volatile struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
540 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
569 #define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
571 #define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
573 #define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
575 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
577 #define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
579 #define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
581 #define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
583 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
596 #define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
598 #define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
600 #define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
602 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
604 #define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
606 #define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
608 #define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
610 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
623 #define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
625 #define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
627 #define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
629 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
631 #define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
633 #define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
635 #define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
637 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
650 #define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
652 #define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
654 #define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
656 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
658 #define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
660 #define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
662 #define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
664 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
677 struct ALT_NAND_CFG_RB_PIN_END_s
687 typedef volatile struct ALT_NAND_CFG_RB_PIN_END_s ALT_NAND_CFG_RB_PIN_END_t;
691 #define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
717 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
719 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
721 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
723 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
725 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
727 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
729 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
731 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
744 struct ALT_NAND_CFG_MULTIPLANE_OP_s
751 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_OP_s ALT_NAND_CFG_MULTIPLANE_OP_t;
755 #define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
785 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
787 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
789 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
791 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
793 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
795 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
797 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
799 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
812 struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s
819 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s ALT_NAND_CFG_MULTIPLANE_RD_EN_t;
823 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
847 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
849 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
851 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
853 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
855 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
857 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
859 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
861 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
874 struct ALT_NAND_CFG_COPYBACK_DIS_s
881 typedef volatile struct ALT_NAND_CFG_COPYBACK_DIS_s ALT_NAND_CFG_COPYBACK_DIS_t;
885 #define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
909 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
911 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
913 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
915 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
917 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
919 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
921 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
923 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
936 struct ALT_NAND_CFG_CACHE_WR_EN_s
943 typedef volatile struct ALT_NAND_CFG_CACHE_WR_EN_s ALT_NAND_CFG_CACHE_WR_EN_t;
947 #define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
971 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
973 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
975 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
977 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
979 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
981 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
983 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
985 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
998 struct ALT_NAND_CFG_CACHE_RD_EN_s
1005 typedef volatile struct ALT_NAND_CFG_CACHE_RD_EN_s ALT_NAND_CFG_CACHE_RD_EN_t;
1009 #define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1035 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1037 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1039 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1041 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1043 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1045 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1047 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1049 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1065 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1067 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1069 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1071 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1073 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1075 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1077 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1079 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1081 #ifndef __ASSEMBLY__
1092 struct ALT_NAND_CFG_PREFETCH_MOD_s
1094 uint32_t prefetch_en : 1;
1096 uint32_t prefetch_burst_length : 12;
1101 typedef volatile struct ALT_NAND_CFG_PREFETCH_MOD_s ALT_NAND_CFG_PREFETCH_MOD_t;
1105 #define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1130 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1132 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1134 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1136 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1138 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1140 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1142 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1144 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1146 #ifndef __ASSEMBLY__
1157 struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
1164 typedef volatile struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s ALT_NAND_CFG_CHIP_EN_DONT_CARE_t;
1168 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1196 #define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1198 #define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1200 #define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1202 #define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1204 #define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1206 #define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1208 #define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1210 #define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1212 #ifndef __ASSEMBLY__
1223 struct ALT_NAND_CFG_ECC_EN_s
1230 typedef volatile struct ALT_NAND_CFG_ECC_EN_s ALT_NAND_CFG_ECC_EN_t;
1234 #define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1262 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1264 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1266 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1268 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1270 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1272 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1274 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1276 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1287 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1289 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1291 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1293 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1295 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1297 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1299 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1301 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1312 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1314 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1316 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1318 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1320 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1322 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1324 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1326 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1328 #ifndef __ASSEMBLY__
1339 struct ALT_NAND_CFG_GLOB_INT_EN_s
1343 uint32_t timeout_disable : 1;
1345 uint32_t error_rpt_disable : 1;
1350 typedef volatile struct ALT_NAND_CFG_GLOB_INT_EN_s ALT_NAND_CFG_GLOB_INT_EN_t;
1354 #define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1381 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1383 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1385 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1387 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1389 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1391 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1393 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1395 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1407 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1409 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1411 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1413 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1415 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1417 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1419 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1421 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1423 #ifndef __ASSEMBLY__
1434 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1436 uint32_t we_2_re : 6;
1443 typedef volatile struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1447 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1474 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1476 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5
1478 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6
1480 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f
1482 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0
1484 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1486 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000003f) >> 0)
1488 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000003f)
1501 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1503 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1505 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1507 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1509 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1511 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1513 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1515 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1517 #ifndef __ASSEMBLY__
1528 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1530 uint32_t addr_2_data : 6;
1537 typedef volatile struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1541 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1568 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1570 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1572 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1574 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1576 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1578 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1580 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1582 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1584 #ifndef __ASSEMBLY__
1595 struct ALT_NAND_CFG_RE_2_WE_s
1602 typedef volatile struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1606 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1632 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1634 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1636 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1638 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1640 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1642 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1644 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1646 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1648 #ifndef __ASSEMBLY__
1659 struct ALT_NAND_CFG_ACC_CLKS_s
1666 typedef volatile struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1670 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1699 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1701 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1703 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1705 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1707 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1709 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1711 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1713 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1715 #ifndef __ASSEMBLY__
1726 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1733 typedef volatile struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1737 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1764 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1766 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1768 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1770 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1772 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1774 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1776 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1778 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1780 #ifndef __ASSEMBLY__
1791 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
1793 uint32_t value : 16;
1798 typedef volatile struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
1802 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1829 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1831 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1833 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1835 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1837 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1839 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1841 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
1843 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
1845 #ifndef __ASSEMBLY__
1856 struct ALT_NAND_CFG_DEVICE_WIDTH_s
1863 typedef volatile struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
1867 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
1894 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
1896 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
1898 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
1900 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1902 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1904 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
1906 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1908 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1910 #ifndef __ASSEMBLY__
1921 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
1923 uint32_t value : 16;
1928 typedef volatile struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
1932 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
1959 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
1961 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
1963 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
1965 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1967 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1969 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
1971 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1973 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1975 #ifndef __ASSEMBLY__
1986 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
1988 uint32_t value : 16;
1993 typedef volatile struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
1997 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2023 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2025 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2027 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2029 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2031 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2033 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2035 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2037 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2039 #ifndef __ASSEMBLY__
2050 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2057 typedef volatile struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2061 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2088 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2090 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2092 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2094 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2096 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2098 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2100 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2102 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2104 #ifndef __ASSEMBLY__
2115 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2122 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2126 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2152 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2154 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2156 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2158 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2160 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2162 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2164 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2166 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2168 #ifndef __ASSEMBLY__
2179 struct ALT_NAND_CFG_ECC_CORRECTION_s
2186 typedef volatile struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2190 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2246 #define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2248 #define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2250 #define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2252 #define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2254 #define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2256 #define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2258 #define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2260 #define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2262 #ifndef __ASSEMBLY__
2273 struct ALT_NAND_CFG_RD_MOD_s
2280 typedef volatile struct ALT_NAND_CFG_RD_MOD_s ALT_NAND_CFG_RD_MOD_t;
2284 #define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2326 #define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2328 #define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2330 #define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2332 #define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2334 #define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2336 #define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2338 #define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2340 #define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2342 #ifndef __ASSEMBLY__
2353 struct ALT_NAND_CFG_WR_MOD_s
2360 typedef volatile struct ALT_NAND_CFG_WR_MOD_s ALT_NAND_CFG_WR_MOD_t;
2364 #define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2406 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2408 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2410 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2412 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2414 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2416 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2418 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2420 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2422 #ifndef __ASSEMBLY__
2433 struct ALT_NAND_CFG_COPYBACK_MOD_s
2440 typedef volatile struct ALT_NAND_CFG_COPYBACK_MOD_s ALT_NAND_CFG_COPYBACK_MOD_t;
2444 #define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2473 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2475 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2477 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2479 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2481 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2483 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2485 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2487 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2489 #ifndef __ASSEMBLY__
2500 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
2507 typedef volatile struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
2511 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2540 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2542 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2544 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2546 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2548 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2550 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2552 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2554 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2556 #ifndef __ASSEMBLY__
2567 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
2574 typedef volatile struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
2578 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
2606 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
2608 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
2610 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
2612 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
2614 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
2616 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
2618 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2620 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2622 #ifndef __ASSEMBLY__
2633 struct ALT_NAND_CFG_MAX_RD_DELAY_s
2640 typedef volatile struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
2644 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
2674 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
2676 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
2678 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
2680 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
2682 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
2684 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
2686 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2688 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2690 #ifndef __ASSEMBLY__
2701 struct ALT_NAND_CFG_CS_SETUP_CNT_s
2708 typedef volatile struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
2712 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
2741 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
2743 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
2745 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
2747 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
2749 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
2751 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
2753 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
2755 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
2757 #ifndef __ASSEMBLY__
2768 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
2775 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
2779 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
2805 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
2807 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
2809 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
2811 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
2813 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
2815 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
2817 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2819 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2821 #ifndef __ASSEMBLY__
2832 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
2834 uint32_t value : 16;
2839 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
2843 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
2868 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
2870 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
2872 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
2874 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
2876 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
2878 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
2880 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
2882 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
2884 #ifndef __ASSEMBLY__
2895 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
2902 typedef volatile struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
2906 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
2935 #define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
2937 #define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 7
2939 #define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 8
2941 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x000000ff
2943 #define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffffff00
2945 #define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
2947 #define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2949 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2951 #ifndef __ASSEMBLY__
2962 struct ALT_NAND_CFG_DIE_MSK_s
2969 typedef volatile struct ALT_NAND_CFG_DIE_MSK_s ALT_NAND_CFG_DIE_MSK_t;
2973 #define ALT_NAND_CFG_DIE_MSK_OFST 0x260
3001 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3003 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3005 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3007 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3009 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3011 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3013 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3015 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3017 #ifndef __ASSEMBLY__
3028 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3030 uint32_t value : 16;
3035 typedef volatile struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3039 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3067 #define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3069 #define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3071 #define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3073 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3075 #define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3077 #define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3079 #define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3081 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3083 #ifndef __ASSEMBLY__
3094 struct ALT_NAND_CFG_WR_PROTECT_s
3101 typedef volatile struct ALT_NAND_CFG_WR_PROTECT_s ALT_NAND_CFG_WR_PROTECT_t;
3105 #define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3132 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3134 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3136 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3138 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3140 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3142 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3144 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3146 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3148 #ifndef __ASSEMBLY__
3159 struct ALT_NAND_CFG_RE_2_RE_s
3166 typedef volatile struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3170 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3197 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3199 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3201 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3203 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3205 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3207 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3209 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3211 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3213 #ifndef __ASSEMBLY__
3224 struct ALT_NAND_CFG_POR_RST_COUNT_s
3226 uint32_t value : 16;
3231 typedef volatile struct ALT_NAND_CFG_POR_RST_COUNT_s ALT_NAND_CFG_POR_RST_COUNT_t;
3235 #define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3262 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3264 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3266 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3268 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3270 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3272 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3274 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3276 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3278 #ifndef __ASSEMBLY__
3289 struct ALT_NAND_CFG_WD_RST_COUNT_s
3291 uint32_t value : 16;
3296 typedef volatile struct ALT_NAND_CFG_WD_RST_COUNT_s ALT_NAND_CFG_WD_RST_COUNT_t;
3300 #define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3302 #ifndef __ASSEMBLY__
3313 struct ALT_NAND_CFG_s
3315 ALT_NAND_CFG_DEVICE_RST_t device_reset;
3316 volatile uint32_t _pad_0x4_0xf[3];
3317 ALT_NAND_CFG_TFR_SPARE_REG_t transfer_spare_reg;
3318 volatile uint32_t _pad_0x14_0x1f[3];
3319 ALT_NAND_CFG_LD_WAIT_CNT_t load_wait_cnt;
3320 volatile uint32_t _pad_0x24_0x2f[3];
3321 ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt;
3322 volatile uint32_t _pad_0x34_0x3f[3];
3323 ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt;
3324 volatile uint32_t _pad_0x44_0x4f[3];
3325 ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt;
3326 volatile uint32_t _pad_0x54_0x5f[3];
3327 ALT_NAND_CFG_RB_PIN_END_t rb_pin_enabled;
3328 volatile uint32_t _pad_0x64_0x6f[3];
3329 ALT_NAND_CFG_MULTIPLANE_OP_t multiplane_operation;
3330 volatile uint32_t _pad_0x74_0x7f[3];
3331 ALT_NAND_CFG_MULTIPLANE_RD_EN_t multiplane_read_enable;
3332 volatile uint32_t _pad_0x84_0x8f[3];
3333 ALT_NAND_CFG_COPYBACK_DIS_t copyback_disable;
3334 volatile uint32_t _pad_0x94_0x9f[3];
3335 ALT_NAND_CFG_CACHE_WR_EN_t cache_write_enable;
3336 volatile uint32_t _pad_0xa4_0xaf[3];
3337 ALT_NAND_CFG_CACHE_RD_EN_t cache_read_enable;
3338 volatile uint32_t _pad_0xb4_0xbf[3];
3339 ALT_NAND_CFG_PREFETCH_MOD_t prefetch_mode;
3340 volatile uint32_t _pad_0xc4_0xcf[3];
3341 ALT_NAND_CFG_CHIP_EN_DONT_CARE_t chip_enable_dont_care;
3342 volatile uint32_t _pad_0xd4_0xdf[3];
3343 ALT_NAND_CFG_ECC_EN_t ecc_enable;
3344 volatile uint32_t _pad_0xe4_0xef[3];
3345 ALT_NAND_CFG_GLOB_INT_EN_t global_int_enable;
3346 volatile uint32_t _pad_0xf4_0xff[3];
3347 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re;
3348 volatile uint32_t _pad_0x104_0x10f[3];
3349 ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data;
3350 volatile uint32_t _pad_0x114_0x11f[3];
3351 ALT_NAND_CFG_RE_2_WE_t re_2_we;
3352 volatile uint32_t _pad_0x124_0x12f[3];
3353 ALT_NAND_CFG_ACC_CLKS_t acc_clks;
3354 volatile uint32_t _pad_0x134_0x13f[3];
3355 ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes;
3356 volatile uint32_t _pad_0x144_0x14f[3];
3357 ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block;
3358 volatile uint32_t _pad_0x154_0x15f[3];
3359 ALT_NAND_CFG_DEVICE_WIDTH_t device_width;
3360 volatile uint32_t _pad_0x164_0x16f[3];
3361 ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size;
3362 volatile uint32_t _pad_0x174_0x17f[3];
3363 ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size;
3364 volatile uint32_t _pad_0x184_0x18f[3];
3365 ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles;
3366 volatile uint32_t _pad_0x194_0x19f[3];
3367 ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict;
3368 volatile uint32_t _pad_0x1a4_0x1af[3];
3369 ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction;
3370 volatile uint32_t _pad_0x1b4_0x1bf[3];
3371 ALT_NAND_CFG_RD_MOD_t read_mode;
3372 volatile uint32_t _pad_0x1c4_0x1cf[3];
3373 ALT_NAND_CFG_WR_MOD_t write_mode;
3374 volatile uint32_t _pad_0x1d4_0x1df[3];
3375 ALT_NAND_CFG_COPYBACK_MOD_t copyback_mode;
3376 volatile uint32_t _pad_0x1e4_0x1ef[3];
3377 ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt;
3378 volatile uint32_t _pad_0x1f4_0x1ff[3];
3379 ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt;
3380 volatile uint32_t _pad_0x204_0x20f[3];
3381 ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay;
3382 volatile uint32_t _pad_0x214_0x21f[3];
3383 ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt;
3384 volatile uint32_t _pad_0x224_0x22f[3];
3385 ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes;
3386 volatile uint32_t _pad_0x234_0x23f[3];
3387 ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker;
3388 volatile uint32_t _pad_0x244_0x24f[3];
3389 ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected;
3390 volatile uint32_t _pad_0x254_0x25f[3];
3391 ALT_NAND_CFG_DIE_MSK_t die_mask;
3392 volatile uint32_t _pad_0x264_0x26f[3];
3393 ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane;
3394 volatile uint32_t _pad_0x274_0x27f[3];
3395 ALT_NAND_CFG_WR_PROTECT_t write_protect;
3396 volatile uint32_t _pad_0x284_0x28f[3];
3397 ALT_NAND_CFG_RE_2_RE_t re_2_re;
3398 volatile uint32_t _pad_0x294_0x29f[3];
3399 ALT_NAND_CFG_POR_RST_COUNT_t por_reset_count;
3400 volatile uint32_t _pad_0x2a4_0x2af[3];
3401 ALT_NAND_CFG_WD_RST_COUNT_t watchdog_reset_count;
3405 typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
3407 struct ALT_NAND_CFG_raw_s
3409 volatile uint32_t device_reset;
3410 uint32_t _pad_0x4_0xf[3];
3411 volatile uint32_t transfer_spare_reg;
3412 uint32_t _pad_0x14_0x1f[3];
3413 volatile uint32_t load_wait_cnt;
3414 uint32_t _pad_0x24_0x2f[3];
3415 volatile uint32_t program_wait_cnt;
3416 uint32_t _pad_0x34_0x3f[3];
3417 volatile uint32_t erase_wait_cnt;
3418 uint32_t _pad_0x44_0x4f[3];
3419 volatile uint32_t int_mon_cyccnt;
3420 uint32_t _pad_0x54_0x5f[3];
3421 volatile uint32_t rb_pin_enabled;
3422 uint32_t _pad_0x64_0x6f[3];
3423 volatile uint32_t multiplane_operation;
3424 uint32_t _pad_0x74_0x7f[3];
3425 volatile uint32_t multiplane_read_enable;
3426 uint32_t _pad_0x84_0x8f[3];
3427 volatile uint32_t copyback_disable;
3428 uint32_t _pad_0x94_0x9f[3];
3429 volatile uint32_t cache_write_enable;
3430 uint32_t _pad_0xa4_0xaf[3];
3431 volatile uint32_t cache_read_enable;
3432 uint32_t _pad_0xb4_0xbf[3];
3433 volatile uint32_t prefetch_mode;
3434 uint32_t _pad_0xc4_0xcf[3];
3435 volatile uint32_t chip_enable_dont_care;
3436 uint32_t _pad_0xd4_0xdf[3];
3437 volatile uint32_t ecc_enable;
3438 uint32_t _pad_0xe4_0xef[3];
3439 volatile uint32_t global_int_enable;
3440 uint32_t _pad_0xf4_0xff[3];
3441 volatile uint32_t twhr2_and_we_2_re;
3442 uint32_t _pad_0x104_0x10f[3];
3443 volatile uint32_t tcwaw_and_addr_2_data;
3444 uint32_t _pad_0x114_0x11f[3];
3445 volatile uint32_t re_2_we;
3446 uint32_t _pad_0x124_0x12f[3];
3447 volatile uint32_t acc_clks;
3448 uint32_t _pad_0x134_0x13f[3];
3449 volatile uint32_t number_of_planes;
3450 uint32_t _pad_0x144_0x14f[3];
3451 volatile uint32_t pages_per_block;
3452 uint32_t _pad_0x154_0x15f[3];
3453 volatile uint32_t device_width;
3454 uint32_t _pad_0x164_0x16f[3];
3455 volatile uint32_t device_main_area_size;
3456 uint32_t _pad_0x174_0x17f[3];
3457 volatile uint32_t device_spare_area_size;
3458 uint32_t _pad_0x184_0x18f[3];
3459 volatile uint32_t two_row_addr_cycles;
3460 uint32_t _pad_0x194_0x19f[3];
3461 volatile uint32_t multiplane_addr_restrict;
3462 uint32_t _pad_0x1a4_0x1af[3];
3463 volatile uint32_t ecc_correction;
3464 uint32_t _pad_0x1b4_0x1bf[3];
3465 volatile uint32_t read_mode;
3466 uint32_t _pad_0x1c4_0x1cf[3];
3467 volatile uint32_t write_mode;
3468 uint32_t _pad_0x1d4_0x1df[3];
3469 volatile uint32_t copyback_mode;
3470 uint32_t _pad_0x1e4_0x1ef[3];
3471 volatile uint32_t rdwr_en_lo_cnt;
3472 uint32_t _pad_0x1f4_0x1ff[3];
3473 volatile uint32_t rdwr_en_hi_cnt;
3474 uint32_t _pad_0x204_0x20f[3];
3475 volatile uint32_t max_rd_delay;
3476 uint32_t _pad_0x214_0x21f[3];
3477 volatile uint32_t cs_setup_cnt;
3478 uint32_t _pad_0x224_0x22f[3];
3479 volatile uint32_t spare_area_skip_bytes;
3480 uint32_t _pad_0x234_0x23f[3];
3481 volatile uint32_t spare_area_marker;
3482 uint32_t _pad_0x244_0x24f[3];
3483 volatile uint32_t devices_connected;
3484 uint32_t _pad_0x254_0x25f[3];
3485 volatile uint32_t die_mask;
3486 uint32_t _pad_0x264_0x26f[3];
3487 volatile uint32_t first_block_of_next_plane;
3488 uint32_t _pad_0x274_0x27f[3];
3489 volatile uint32_t write_protect;
3490 uint32_t _pad_0x284_0x28f[3];
3491 volatile uint32_t re_2_re;
3492 uint32_t _pad_0x294_0x29f[3];
3493 volatile uint32_t por_reset_count;
3494 uint32_t _pad_0x2a4_0x2af[3];
3495 volatile uint32_t watchdog_reset_count;
3499 typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
3531 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
3533 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
3535 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
3537 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
3539 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
3541 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
3543 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3545 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3547 #ifndef __ASSEMBLY__
3558 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
3565 typedef volatile struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
3569 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
3591 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
3593 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
3595 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
3597 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
3599 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
3601 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
3603 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3605 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3607 #ifndef __ASSEMBLY__
3618 struct ALT_NAND_PARAM_DEVICE_ID_s
3620 const uint32_t value : 8;
3625 typedef volatile struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
3629 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
3652 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
3654 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
3656 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
3658 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
3660 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
3662 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
3664 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3666 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3668 #ifndef __ASSEMBLY__
3679 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
3681 const uint32_t value : 8;
3686 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
3690 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
3713 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
3715 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
3717 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
3719 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
3721 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
3723 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
3725 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3727 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3729 #ifndef __ASSEMBLY__
3740 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
3742 const uint32_t value : 8;
3747 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
3751 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
3773 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
3775 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
3777 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
3779 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
3781 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
3783 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
3785 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3787 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3789 #ifndef __ASSEMBLY__
3800 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
3802 const uint32_t value : 8;
3807 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
3811 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
3837 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
3839 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
3841 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
3843 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
3845 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
3847 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
3849 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3851 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3853 #ifndef __ASSEMBLY__
3864 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
3866 const uint32_t value : 16;
3871 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
3875 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
3901 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
3903 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
3905 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
3907 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
3909 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
3911 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
3913 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3915 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3917 #ifndef __ASSEMBLY__
3928 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
3930 const uint32_t value : 16;
3935 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
3939 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
3963 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
3965 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 15
3967 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 16
3969 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x0000ffff
3971 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffff0000
3973 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
3975 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3977 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3979 #ifndef __ASSEMBLY__
3990 struct ALT_NAND_PARAM_REVISION_s
3992 const uint32_t value : 16;
3997 typedef volatile struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
4001 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4032 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4034 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4036 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4038 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4040 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4042 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4044 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4046 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4048 #ifndef __ASSEMBLY__
4059 struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
4061 const uint32_t value : 16;
4066 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s ALT_NAND_PARAM_ONFI_DEV_FEATURES_t;
4070 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4100 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4102 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4104 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4106 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4108 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4110 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4112 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4114 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4116 #ifndef __ASSEMBLY__
4127 struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
4129 const uint32_t value : 16;
4134 typedef volatile struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t;
4138 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4165 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4167 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4169 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4171 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4173 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4175 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4177 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4179 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4181 #ifndef __ASSEMBLY__
4192 struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s
4194 const uint32_t value : 6;
4199 typedef volatile struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s ALT_NAND_PARAM_ONFI_TIMING_MOD_t;
4203 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4230 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4232 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4234 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4236 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4238 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4240 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4242 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4244 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4246 #ifndef __ASSEMBLY__
4257 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
4259 const uint32_t value : 6;
4264 typedef volatile struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t;
4268 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4294 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4296 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4298 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4300 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4302 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4304 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4306 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4308 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4320 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4322 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4324 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4326 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4328 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4330 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4332 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4334 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
4336 #ifndef __ASSEMBLY__
4347 struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
4349 const uint32_t no_of_luns : 8;
4350 uint32_t onfi_device : 1;
4355 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t;
4359 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
4384 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
4386 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
4388 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
4390 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
4392 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
4394 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
4396 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4398 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4400 #ifndef __ASSEMBLY__
4411 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
4413 const uint32_t value : 16;
4418 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t;
4422 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
4447 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
4449 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
4451 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
4453 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
4455 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
4457 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
4459 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4461 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4463 #ifndef __ASSEMBLY__
4474 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
4476 const uint32_t value : 16;
4481 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t;
4485 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
4520 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
4522 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
4524 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
4526 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
4528 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
4530 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x1
4532 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
4534 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
4545 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
4547 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
4549 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
4551 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
4553 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
4555 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
4557 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
4559 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
4570 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
4572 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
4574 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
4576 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
4578 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
4580 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x0
4582 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
4584 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
4595 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
4597 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
4599 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
4601 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
4603 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
4605 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
4607 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
4609 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
4620 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
4622 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
4624 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
4626 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
4628 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
4630 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
4632 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
4634 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
4645 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
4647 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
4649 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
4651 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
4653 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
4655 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
4657 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
4659 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
4670 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
4672 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
4674 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
4676 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
4678 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
4680 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
4682 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
4684 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
4695 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
4697 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
4699 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
4701 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
4703 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
4705 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
4707 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
4709 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
4720 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
4722 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
4724 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
4726 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
4728 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
4730 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
4732 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
4734 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
4736 #ifndef __ASSEMBLY__
4747 struct ALT_NAND_PARAM_FEATURES_s
4749 const uint32_t n_banks : 2;
4751 const uint32_t dma : 1;
4752 const uint32_t cmd_dma : 1;
4753 const uint32_t partition : 1;
4754 const uint32_t xdma_sideband : 1;
4755 const uint32_t gpreg : 1;
4756 const uint32_t index_addr : 1;
4757 const uint32_t dfi_intf : 1;
4758 const uint32_t lba : 1;
4763 typedef volatile struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
4767 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
4769 #ifndef __ASSEMBLY__
4780 struct ALT_NAND_PARAM_s
4782 ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id;
4783 volatile uint32_t _pad_0x4_0xf[3];
4784 ALT_NAND_PARAM_DEVICE_ID_t device_id;
4785 volatile uint32_t _pad_0x14_0x1f[3];
4786 ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0;
4787 volatile uint32_t _pad_0x24_0x2f[3];
4788 ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1;
4789 volatile uint32_t _pad_0x34_0x3f[3];
4790 ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2;
4791 volatile uint32_t _pad_0x44_0x4f[3];
4792 ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size;
4793 volatile uint32_t _pad_0x54_0x5f[3];
4794 ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size;
4795 volatile uint32_t _pad_0x64_0x6f[3];
4796 ALT_NAND_PARAM_REVISION_t revision;
4797 volatile uint32_t _pad_0x74_0x7f[3];
4798 ALT_NAND_PARAM_ONFI_DEV_FEATURES_t onfi_device_features;
4799 volatile uint32_t _pad_0x84_0x8f[3];
4800 ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t onfi_optional_commands;
4801 volatile uint32_t _pad_0x94_0x9f[3];
4802 ALT_NAND_PARAM_ONFI_TIMING_MOD_t onfi_timing_mode;
4803 volatile uint32_t _pad_0xa4_0xaf[3];
4804 ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t onfi_pgm_cache_timing_mode;
4805 volatile uint32_t _pad_0xb4_0xbf[3];
4806 ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t onfi_device_no_of_luns;
4807 volatile uint32_t _pad_0xc4_0xcf[3];
4808 ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l;
4809 volatile uint32_t _pad_0xd4_0xdf[3];
4810 ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u;
4811 volatile uint32_t _pad_0xe4_0xef[3];
4812 ALT_NAND_PARAM_FEATURES_t features;
4816 typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
4818 struct ALT_NAND_PARAM_raw_s
4820 volatile uint32_t manufacturer_id;
4821 uint32_t _pad_0x4_0xf[3];
4822 volatile uint32_t device_id;
4823 uint32_t _pad_0x14_0x1f[3];
4824 volatile uint32_t device_param_0;
4825 uint32_t _pad_0x24_0x2f[3];
4826 volatile uint32_t device_param_1;
4827 uint32_t _pad_0x34_0x3f[3];
4828 volatile uint32_t device_param_2;
4829 uint32_t _pad_0x44_0x4f[3];
4830 volatile uint32_t logical_page_data_size;
4831 uint32_t _pad_0x54_0x5f[3];
4832 volatile uint32_t logical_page_spare_size;
4833 uint32_t _pad_0x64_0x6f[3];
4834 volatile uint32_t revision;
4835 uint32_t _pad_0x74_0x7f[3];
4836 volatile uint32_t onfi_device_features;
4837 uint32_t _pad_0x84_0x8f[3];
4838 volatile uint32_t onfi_optional_commands;
4839 uint32_t _pad_0x94_0x9f[3];
4840 volatile uint32_t onfi_timing_mode;
4841 uint32_t _pad_0xa4_0xaf[3];
4842 volatile uint32_t onfi_pgm_cache_timing_mode;
4843 uint32_t _pad_0xb4_0xbf[3];
4844 volatile uint32_t onfi_device_no_of_luns;
4845 uint32_t _pad_0xc4_0xcf[3];
4846 volatile uint32_t onfi_device_no_of_blocks_per_lun_l;
4847 uint32_t _pad_0xd4_0xdf[3];
4848 volatile uint32_t onfi_device_no_of_blocks_per_lun_u;
4849 uint32_t _pad_0xe4_0xef[3];
4850 volatile uint32_t features;
4854 typedef volatile struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
4892 #define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
4894 #define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
4896 #define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
4898 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
4900 #define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
4902 #define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
4904 #define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
4906 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
4918 #define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
4920 #define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
4922 #define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
4924 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
4926 #define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
4928 #define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
4930 #define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
4932 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
4944 #define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
4946 #define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
4948 #define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
4950 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
4952 #define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
4954 #define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
4956 #define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
4958 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
4970 #define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
4972 #define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
4974 #define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
4976 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
4978 #define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
4980 #define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
4982 #define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
4984 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
4986 #ifndef __ASSEMBLY__
4997 struct ALT_NAND_STAT_TFR_MOD_s
4999 const uint32_t value0 : 2;
5000 const uint32_t value1 : 2;
5001 const uint32_t value2 : 2;
5002 const uint32_t value3 : 2;
5007 typedef volatile struct ALT_NAND_STAT_TFR_MOD_s ALT_NAND_STAT_TFR_MOD_t;
5011 #define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5050 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5052 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5054 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5056 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5058 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5060 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5062 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5064 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5075 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5077 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5079 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5081 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5083 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5085 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5087 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5089 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5101 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5103 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5105 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5107 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5109 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5111 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5113 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5115 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5128 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5130 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5132 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5134 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5136 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5138 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5140 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5142 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5155 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5157 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5159 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5161 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5163 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5165 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5167 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5169 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5180 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5182 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5184 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5186 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5188 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5190 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5192 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5194 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5205 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5207 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5209 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5211 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5213 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5215 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
5217 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5219 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5230 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
5232 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
5234 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
5236 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
5238 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
5240 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
5242 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5244 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5256 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
5258 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
5260 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5262 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5264 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5266 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5268 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5270 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5282 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
5284 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
5286 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
5288 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
5290 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
5292 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
5294 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5296 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5308 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
5310 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
5312 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
5314 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
5316 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5318 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
5320 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5322 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5333 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
5335 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
5337 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
5339 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
5341 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
5343 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
5345 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5347 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5358 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
5360 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
5362 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
5364 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
5366 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
5368 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
5370 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5372 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5385 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
5387 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
5389 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
5391 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
5393 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5395 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
5397 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5399 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5410 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
5412 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
5414 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
5416 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
5418 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5420 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
5422 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5424 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5426 #ifndef __ASSEMBLY__
5437 struct ALT_NAND_STAT_INTR_STAT0_s
5439 uint32_t ecc_uncor_err : 1;
5441 uint32_t dma_cmd_comp : 1;
5442 uint32_t time_out : 1;
5443 uint32_t program_fail : 1;
5444 uint32_t erase_fail : 1;
5445 uint32_t load_comp : 1;
5446 uint32_t program_comp : 1;
5447 uint32_t erase_comp : 1;
5448 uint32_t pipe_cpybck_cmd_comp : 1;
5449 uint32_t locked_blk : 1;
5450 uint32_t unsup_cmd : 1;
5451 uint32_t INT_act : 1;
5452 uint32_t rst_comp : 1;
5453 uint32_t pipe_cmd_err : 1;
5454 uint32_t page_xfer_inc : 1;
5459 typedef volatile struct ALT_NAND_STAT_INTR_STAT0_s ALT_NAND_STAT_INTR_STAT0_t;
5463 #define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
5503 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
5505 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
5507 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
5509 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5511 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5513 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
5515 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5517 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5528 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
5530 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
5532 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
5534 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
5536 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5538 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
5540 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5542 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5554 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
5556 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
5558 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
5560 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
5562 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
5564 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
5566 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5568 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5581 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
5583 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
5585 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
5587 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
5589 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5591 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
5593 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5595 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5608 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
5610 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
5612 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
5614 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
5616 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
5618 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
5620 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5622 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5633 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
5635 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
5637 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
5639 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
5641 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
5643 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
5645 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5647 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5658 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
5660 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
5662 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
5664 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
5666 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5668 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
5670 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5672 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5683 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
5685 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
5687 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
5689 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
5691 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
5693 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
5695 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5697 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5709 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
5711 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
5713 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5715 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5717 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5719 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5721 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5723 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5735 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
5737 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
5739 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
5741 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
5743 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
5745 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
5747 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5749 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5761 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
5763 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
5765 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
5767 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
5769 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5771 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
5773 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5775 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5786 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
5788 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
5790 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
5792 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
5794 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
5796 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
5798 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5800 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5811 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
5813 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
5815 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
5817 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
5819 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
5821 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
5823 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5825 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5838 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
5840 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
5842 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
5844 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
5846 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5848 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
5850 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5852 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5863 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
5865 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
5867 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
5869 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
5871 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5873 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
5875 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5877 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5879 #ifndef __ASSEMBLY__
5890 struct ALT_NAND_STAT_INTR_EN0_s
5892 uint32_t ecc_uncor_err : 1;
5894 uint32_t dma_cmd_comp : 1;
5895 uint32_t time_out : 1;
5896 uint32_t program_fail : 1;
5897 uint32_t erase_fail : 1;
5898 uint32_t load_comp : 1;
5899 uint32_t program_comp : 1;
5900 uint32_t erase_comp : 1;
5901 uint32_t pipe_cpybck_cmd_comp : 1;
5902 uint32_t locked_blk : 1;
5903 uint32_t unsup_cmd : 1;
5904 uint32_t INT_act : 1;
5905 uint32_t rst_comp : 1;
5906 uint32_t pipe_cmd_err : 1;
5907 uint32_t page_xfer_inc : 1;
5912 typedef volatile struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
5916 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
5941 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
5943 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
5945 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
5947 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
5949 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
5951 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
5953 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
5955 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
5957 #ifndef __ASSEMBLY__
5968 struct ALT_NAND_STAT_PAGE_CNT0_s
5970 const uint32_t value : 8;
5975 typedef volatile struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
5979 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
6003 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6005 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6007 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6009 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6011 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6013 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6015 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6017 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6019 #ifndef __ASSEMBLY__
6030 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
6032 const uint32_t value : 16;
6037 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
6041 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6066 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6068 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6070 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6072 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6074 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6076 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6078 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6080 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6082 #ifndef __ASSEMBLY__
6093 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
6095 const uint32_t value : 16;
6100 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
6104 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
6143 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
6145 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
6147 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
6149 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6151 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6153 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
6155 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6157 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6168 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
6170 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
6172 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
6174 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
6176 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6178 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
6180 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6182 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6194 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
6196 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
6198 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
6200 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
6202 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
6204 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
6206 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6208 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6221 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
6223 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
6225 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
6227 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
6229 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6231 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
6233 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6235 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6248 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
6250 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
6252 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
6254 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
6256 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
6258 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
6260 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6262 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6273 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
6275 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
6277 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
6279 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
6281 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
6283 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
6285 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6287 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6298 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
6300 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
6302 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
6304 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
6306 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6308 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
6310 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6312 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6323 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
6325 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
6327 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
6329 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
6331 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
6333 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
6335 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6337 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6349 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
6351 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
6353 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6355 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6357 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6359 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6361 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6363 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6375 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
6377 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
6379 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
6381 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
6383 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
6385 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
6387 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6389 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6401 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
6403 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
6405 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
6407 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
6409 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6411 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
6413 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6415 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6426 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
6428 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
6430 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
6432 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
6434 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
6436 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
6438 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6440 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6452 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
6454 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
6456 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
6458 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
6460 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
6462 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
6464 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6466 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6479 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
6481 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
6483 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
6485 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
6487 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6489 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
6491 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6493 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6504 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
6506 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
6508 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
6510 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
6512 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6514 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
6516 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6518 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6520 #ifndef __ASSEMBLY__
6531 struct ALT_NAND_STAT_INTR_STAT1_s
6533 uint32_t ecc_uncor_err : 1;
6535 uint32_t dma_cmd_comp : 1;
6536 uint32_t time_out : 1;
6537 uint32_t program_fail : 1;
6538 uint32_t erase_fail : 1;
6539 uint32_t load_comp : 1;
6540 uint32_t program_comp : 1;
6541 uint32_t erase_comp : 1;
6542 uint32_t pipe_cpybck_cmd_comp : 1;
6543 uint32_t locked_blk : 1;
6544 uint32_t unsup_cmd : 1;
6545 uint32_t INT_act : 1;
6546 uint32_t rst_comp : 1;
6547 uint32_t pipe_cmd_err : 1;
6548 uint32_t page_xfer_inc : 1;
6553 typedef volatile struct ALT_NAND_STAT_INTR_STAT1_s ALT_NAND_STAT_INTR_STAT1_t;
6557 #define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
6597 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
6599 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
6601 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
6603 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6605 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6607 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
6609 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6611 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6622 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
6624 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
6626 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
6628 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
6630 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6632 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
6634 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6636 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6648 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
6650 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
6652 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
6654 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
6656 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
6658 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
6660 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6662 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6675 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
6677 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
6679 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
6681 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
6683 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6685 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
6687 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6689 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6702 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
6704 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
6706 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
6708 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
6710 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
6712 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
6714 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6716 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6727 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
6729 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
6731 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
6733 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
6735 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
6737 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
6739 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6741 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6752 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
6754 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
6756 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
6758 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
6760 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6762 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
6764 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6766 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6777 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
6779 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
6781 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
6783 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
6785 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
6787 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
6789 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6791 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6803 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
6805 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
6807 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6809 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6811 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6813 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6815 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6817 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6829 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
6831 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
6833 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
6835 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
6837 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
6839 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
6841 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6843 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6855 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
6857 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
6859 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
6861 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
6863 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6865 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
6867 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6869 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6880 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
6882 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
6884 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
6886 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
6888 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
6890 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
6892 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6894 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6905 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
6907 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
6909 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
6911 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
6913 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
6915 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
6917 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6919 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6932 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
6934 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
6936 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
6938 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
6940 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6942 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
6944 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6946 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6957 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
6959 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
6961 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
6963 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
6965 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6967 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
6969 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6971 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6973 #ifndef __ASSEMBLY__
6984 struct ALT_NAND_STAT_INTR_EN1_s
6986 uint32_t ecc_uncor_err : 1;
6988 uint32_t dma_cmd_comp : 1;
6989 uint32_t time_out : 1;
6990 uint32_t program_fail : 1;
6991 uint32_t erase_fail : 1;
6992 uint32_t load_comp : 1;
6993 uint32_t program_comp : 1;
6994 uint32_t erase_comp : 1;
6995 uint32_t pipe_cpybck_cmd_comp : 1;
6996 uint32_t locked_blk : 1;
6997 uint32_t unsup_cmd : 1;
6998 uint32_t INT_act : 1;
6999 uint32_t rst_comp : 1;
7000 uint32_t pipe_cmd_err : 1;
7001 uint32_t page_xfer_inc : 1;
7006 typedef volatile struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
7010 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
7035 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
7037 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
7039 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
7041 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
7043 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
7045 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
7047 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
7049 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
7051 #ifndef __ASSEMBLY__
7062 struct ALT_NAND_STAT_PAGE_CNT1_s
7064 const uint32_t value : 8;
7069 typedef volatile struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
7073 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
7097 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
7099 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
7101 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
7103 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
7105 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
7107 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
7109 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7111 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7113 #ifndef __ASSEMBLY__
7124 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
7126 const uint32_t value : 16;
7131 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
7135 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
7160 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
7162 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
7164 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
7166 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
7168 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
7170 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
7172 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7174 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7176 #ifndef __ASSEMBLY__
7187 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
7189 const uint32_t value : 16;
7194 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
7198 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
7237 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
7239 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
7241 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
7243 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7245 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7247 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
7249 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7251 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7262 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
7264 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
7266 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
7268 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
7270 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7272 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
7274 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7276 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7288 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
7290 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
7292 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
7294 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
7296 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
7298 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
7300 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7302 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7315 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
7317 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
7319 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
7321 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
7323 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7325 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
7327 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7329 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7342 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
7344 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
7346 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
7348 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
7350 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
7352 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
7354 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7356 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7367 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
7369 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
7371 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
7373 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
7375 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
7377 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
7379 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7381 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7392 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
7394 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
7396 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
7398 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
7400 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7402 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
7404 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7406 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7417 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
7419 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
7421 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
7423 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
7425 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
7427 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
7429 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7431 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7443 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
7445 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
7447 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7449 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7451 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7453 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7455 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7457 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7469 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
7471 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
7473 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
7475 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
7477 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
7479 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
7481 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7483 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7495 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
7497 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
7499 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
7501 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
7503 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7505 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
7507 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7509 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7520 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
7522 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
7524 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
7526 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
7528 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
7530 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
7532 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7534 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7546 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
7548 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
7550 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
7552 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
7554 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
7556 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
7558 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7560 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7573 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
7575 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
7577 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
7579 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
7581 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7583 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
7585 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7587 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7598 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
7600 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
7602 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
7604 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
7606 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7608 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
7610 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7612 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7614 #ifndef __ASSEMBLY__
7625 struct ALT_NAND_STAT_INTR_STAT2_s
7627 uint32_t ecc_uncor_err : 1;
7629 uint32_t dma_cmd_comp : 1;
7630 uint32_t time_out : 1;
7631 uint32_t program_fail : 1;
7632 uint32_t erase_fail : 1;
7633 uint32_t load_comp : 1;
7634 uint32_t program_comp : 1;
7635 uint32_t erase_comp : 1;
7636 uint32_t pipe_cpybck_cmd_comp : 1;
7637 uint32_t locked_blk : 1;
7638 uint32_t unsup_cmd : 1;
7639 uint32_t INT_act : 1;
7640 uint32_t rst_comp : 1;
7641 uint32_t pipe_cmd_err : 1;
7642 uint32_t page_xfer_inc : 1;
7647 typedef volatile struct ALT_NAND_STAT_INTR_STAT2_s ALT_NAND_STAT_INTR_STAT2_t;
7651 #define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
7691 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
7693 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
7695 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
7697 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7699 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7701 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
7703 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7705 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7716 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
7718 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
7720 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
7722 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
7724 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7726 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
7728 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7730 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7742 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
7744 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
7746 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
7748 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
7750 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
7752 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
7754 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7756 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7769 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
7771 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
7773 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
7775 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
7777 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7779 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
7781 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7783 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7796 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
7798 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
7800 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
7802 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
7804 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
7806 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
7808 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7810 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7821 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
7823 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
7825 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
7827 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
7829 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
7831 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
7833 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7835 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7846 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
7848 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
7850 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
7852 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
7854 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7856 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
7858 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7860 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7871 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
7873 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
7875 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
7877 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
7879 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
7881 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
7883 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7885 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7897 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
7899 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
7901 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7903 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7905 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7907 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7909 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7911 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7923 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
7925 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
7927 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
7929 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
7931 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
7933 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
7935 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7937 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7949 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
7951 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
7953 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
7955 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
7957 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7959 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
7961 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7963 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7974 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
7976 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
7978 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
7980 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
7982 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
7984 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
7986 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7988 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7999 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
8001 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
8003 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
8005 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
8007 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
8009 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
8011 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8013 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8026 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
8028 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
8030 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
8032 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
8034 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8036 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
8038 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8040 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8051 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
8053 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
8055 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
8057 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
8059 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8061 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
8063 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8065 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8067 #ifndef __ASSEMBLY__
8078 struct ALT_NAND_STAT_INTR_EN2_s
8080 uint32_t ecc_uncor_err : 1;
8082 uint32_t dma_cmd_comp : 1;
8083 uint32_t time_out : 1;
8084 uint32_t program_fail : 1;
8085 uint32_t erase_fail : 1;
8086 uint32_t load_comp : 1;
8087 uint32_t program_comp : 1;
8088 uint32_t erase_comp : 1;
8089 uint32_t pipe_cpybck_cmd_comp : 1;
8090 uint32_t locked_blk : 1;
8091 uint32_t unsup_cmd : 1;
8092 uint32_t INT_act : 1;
8093 uint32_t rst_comp : 1;
8094 uint32_t pipe_cmd_err : 1;
8095 uint32_t page_xfer_inc : 1;
8100 typedef volatile struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
8104 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
8129 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
8131 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
8133 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
8135 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
8137 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
8139 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
8141 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8143 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8145 #ifndef __ASSEMBLY__
8156 struct ALT_NAND_STAT_PAGE_CNT2_s
8158 const uint32_t value : 8;
8163 typedef volatile struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
8167 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
8191 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
8193 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
8195 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
8197 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
8199 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
8201 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
8203 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8205 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8207 #ifndef __ASSEMBLY__
8218 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
8220 const uint32_t value : 16;
8225 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
8229 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
8254 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
8256 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
8258 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
8260 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
8262 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
8264 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
8266 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8268 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8270 #ifndef __ASSEMBLY__
8281 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
8283 const uint32_t value : 16;
8288 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
8292 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
8331 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
8333 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
8335 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
8337 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8339 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8341 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
8343 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8345 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8356 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
8358 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
8360 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
8362 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
8364 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8366 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
8368 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8370 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8382 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
8384 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
8386 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
8388 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
8390 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
8392 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
8394 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8396 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8409 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
8411 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
8413 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
8415 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
8417 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8419 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
8421 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8423 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8436 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
8438 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
8440 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
8442 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
8444 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
8446 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
8448 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8450 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8461 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
8463 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
8465 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
8467 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
8469 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
8471 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
8473 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8475 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8486 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
8488 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
8490 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
8492 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
8494 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8496 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
8498 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8500 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8511 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
8513 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
8515 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
8517 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
8519 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
8521 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
8523 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8525 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8537 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
8539 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
8541 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8543 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8545 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8547 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8549 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8551 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8563 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
8565 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
8567 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
8569 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
8571 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
8573 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
8575 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8577 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8589 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
8591 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
8593 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
8595 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
8597 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
8599 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
8601 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8603 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8614 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
8616 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
8618 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
8620 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
8622 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
8624 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
8626 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8628 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8640 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
8642 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
8644 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
8646 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
8648 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
8650 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
8652 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8654 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8667 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
8669 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
8671 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
8673 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
8675 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8677 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
8679 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8681 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8692 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
8694 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
8696 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
8698 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
8700 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8702 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
8704 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8706 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8708 #ifndef __ASSEMBLY__
8719 struct ALT_NAND_STAT_INTR_STAT3_s
8721 uint32_t ecc_uncor_err : 1;
8723 uint32_t dma_cmd_comp : 1;
8724 uint32_t time_out : 1;
8725 uint32_t program_fail : 1;
8726 uint32_t erase_fail : 1;
8727 uint32_t load_comp : 1;
8728 uint32_t program_comp : 1;
8729 uint32_t erase_comp : 1;
8730 uint32_t pipe_cpybck_cmd_comp : 1;
8731 uint32_t locked_blk : 1;
8732 uint32_t unsup_cmd : 1;
8733 uint32_t INT_act : 1;
8734 uint32_t rst_comp : 1;
8735 uint32_t pipe_cmd_err : 1;
8736 uint32_t page_xfer_inc : 1;
8741 typedef volatile struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t;
8745 #define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
8785 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
8787 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
8789 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
8791 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8793 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8795 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
8797 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8799 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8810 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
8812 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
8814 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
8816 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
8818 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8820 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
8822 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8824 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8836 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
8838 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
8840 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
8842 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
8844 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
8846 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
8848 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8850 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8863 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
8865 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
8867 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
8869 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
8871 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8873 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
8875 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8877 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8890 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
8892 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
8894 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
8896 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
8898 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
8900 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
8902 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8904 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8915 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
8917 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
8919 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
8921 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
8923 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
8925 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
8927 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8929 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8940 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
8942 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
8944 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
8946 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
8948 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8950 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
8952 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8954 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8965 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
8967 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
8969 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
8971 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
8973 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
8975 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
8977 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8979 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8991 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
8993 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
8995 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8997 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8999 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9001 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9003 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9005 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9017 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
9019 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
9021 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
9023 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
9025 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
9027 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
9029 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9031 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9043 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
9045 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
9047 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
9049 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
9051 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9053 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
9055 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9057 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9068 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
9070 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
9072 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
9074 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
9076 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
9078 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
9080 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9082 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9093 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
9095 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
9097 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
9099 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
9101 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
9103 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
9105 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9107 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9120 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
9122 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
9124 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
9126 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
9128 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9130 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
9132 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9134 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9145 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
9147 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
9149 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
9151 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
9153 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9155 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
9157 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9159 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9161 #ifndef __ASSEMBLY__
9172 struct ALT_NAND_STAT_INTR_EN3_s
9174 uint32_t ecc_uncor_err : 1;
9176 uint32_t dma_cmd_comp : 1;
9177 uint32_t time_out : 1;
9178 uint32_t program_fail : 1;
9179 uint32_t erase_fail : 1;
9180 uint32_t load_comp : 1;
9181 uint32_t program_comp : 1;
9182 uint32_t erase_comp : 1;
9183 uint32_t pipe_cpybck_cmd_comp : 1;
9184 uint32_t locked_blk : 1;
9185 uint32_t unsup_cmd : 1;
9186 uint32_t INT_act : 1;
9187 uint32_t rst_comp : 1;
9188 uint32_t pipe_cmd_err : 1;
9189 uint32_t page_xfer_inc : 1;
9194 typedef volatile struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
9198 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
9223 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
9225 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
9227 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
9229 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
9231 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
9233 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
9235 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9237 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9239 #ifndef __ASSEMBLY__
9250 struct ALT_NAND_STAT_PAGE_CNT3_s
9252 const uint32_t value : 8;
9257 typedef volatile struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
9261 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
9285 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
9287 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
9289 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
9291 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
9293 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
9295 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
9297 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9299 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9301 #ifndef __ASSEMBLY__
9312 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
9314 const uint32_t value : 16;
9319 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
9323 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
9348 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
9350 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
9352 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
9354 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
9356 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
9358 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
9360 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9362 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9364 #ifndef __ASSEMBLY__
9375 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
9377 const uint32_t value : 16;
9382 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
9386 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
9388 #ifndef __ASSEMBLY__
9399 struct ALT_NAND_STAT_s
9401 ALT_NAND_STAT_TFR_MOD_t transfer_mode;
9402 volatile uint32_t _pad_0x4_0xf[3];
9403 ALT_NAND_STAT_INTR_STAT0_t intr_status0;
9404 volatile uint32_t _pad_0x14_0x1f[3];
9405 ALT_NAND_STAT_INTR_EN0_t intr_en0;
9406 volatile uint32_t _pad_0x24_0x2f[3];
9407 ALT_NAND_STAT_PAGE_CNT0_t page_cnt0;
9408 volatile uint32_t _pad_0x34_0x3f[3];
9409 ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0;
9410 volatile uint32_t _pad_0x44_0x4f[3];
9411 ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0;
9412 volatile uint32_t _pad_0x54_0x5f[3];
9413 ALT_NAND_STAT_INTR_STAT1_t intr_status1;
9414 volatile uint32_t _pad_0x64_0x6f[3];
9415 ALT_NAND_STAT_INTR_EN1_t intr_en1;
9416 volatile uint32_t _pad_0x74_0x7f[3];
9417 ALT_NAND_STAT_PAGE_CNT1_t page_cnt1;
9418 volatile uint32_t _pad_0x84_0x8f[3];
9419 ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1;
9420 volatile uint32_t _pad_0x94_0x9f[3];
9421 ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1;
9422 volatile uint32_t _pad_0xa4_0xaf[3];
9423 ALT_NAND_STAT_INTR_STAT2_t intr_status2;
9424 volatile uint32_t _pad_0xb4_0xbf[3];
9425 ALT_NAND_STAT_INTR_EN2_t intr_en2;
9426 volatile uint32_t _pad_0xc4_0xcf[3];
9427 ALT_NAND_STAT_PAGE_CNT2_t page_cnt2;
9428 volatile uint32_t _pad_0xd4_0xdf[3];
9429 ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2;
9430 volatile uint32_t _pad_0xe4_0xef[3];
9431 ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2;
9432 volatile uint32_t _pad_0xf4_0xff[3];
9433 ALT_NAND_STAT_INTR_STAT3_t intr_status3;
9434 volatile uint32_t _pad_0x104_0x10f[3];
9435 ALT_NAND_STAT_INTR_EN3_t intr_en3;
9436 volatile uint32_t _pad_0x114_0x11f[3];
9437 ALT_NAND_STAT_PAGE_CNT3_t page_cnt3;
9438 volatile uint32_t _pad_0x124_0x12f[3];
9439 ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3;
9440 volatile uint32_t _pad_0x134_0x13f[3];
9441 ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3;
9445 typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
9447 struct ALT_NAND_STAT_raw_s
9449 volatile uint32_t transfer_mode;
9450 uint32_t _pad_0x4_0xf[3];
9451 volatile uint32_t intr_status0;
9452 uint32_t _pad_0x14_0x1f[3];
9453 volatile uint32_t intr_en0;
9454 uint32_t _pad_0x24_0x2f[3];
9455 volatile uint32_t page_cnt0;
9456 uint32_t _pad_0x34_0x3f[3];
9457 volatile uint32_t err_page_addr0;
9458 uint32_t _pad_0x44_0x4f[3];
9459 volatile uint32_t err_block_addr0;
9460 uint32_t _pad_0x54_0x5f[3];
9461 volatile uint32_t intr_status1;
9462 uint32_t _pad_0x64_0x6f[3];
9463 volatile uint32_t intr_en1;
9464 uint32_t _pad_0x74_0x7f[3];
9465 volatile uint32_t page_cnt1;
9466 uint32_t _pad_0x84_0x8f[3];
9467 volatile uint32_t err_page_addr1;
9468 uint32_t _pad_0x94_0x9f[3];
9469 volatile uint32_t err_block_addr1;
9470 uint32_t _pad_0xa4_0xaf[3];
9471 volatile uint32_t intr_status2;
9472 uint32_t _pad_0xb4_0xbf[3];
9473 volatile uint32_t intr_en2;
9474 uint32_t _pad_0xc4_0xcf[3];
9475 volatile uint32_t page_cnt2;
9476 uint32_t _pad_0xd4_0xdf[3];
9477 volatile uint32_t err_page_addr2;
9478 uint32_t _pad_0xe4_0xef[3];
9479 volatile uint32_t err_block_addr2;
9480 uint32_t _pad_0xf4_0xff[3];
9481 volatile uint32_t intr_status3;
9482 uint32_t _pad_0x104_0x10f[3];
9483 volatile uint32_t intr_en3;
9484 uint32_t _pad_0x114_0x11f[3];
9485 volatile uint32_t page_cnt3;
9486 uint32_t _pad_0x124_0x12f[3];
9487 volatile uint32_t err_page_addr3;
9488 uint32_t _pad_0x134_0x13f[3];
9489 volatile uint32_t err_block_addr3;
9493 typedef volatile struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
9532 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
9534 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
9536 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
9538 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
9540 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
9542 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
9544 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
9546 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
9558 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
9560 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
9562 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
9564 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
9566 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
9568 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
9570 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
9572 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
9585 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
9587 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
9589 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
9591 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
9593 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
9595 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
9597 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
9599 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
9611 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
9613 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
9615 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
9617 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
9619 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
9621 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
9623 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
9625 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
9627 #ifndef __ASSEMBLY__
9638 struct ALT_NAND_ECC_ECCCORINFO_B01_s
9640 const uint32_t max_errors_b0 : 7;
9641 const uint32_t uncor_err_b0 : 1;
9642 const uint32_t max_errors_b1 : 7;
9643 const uint32_t uncor_err_b1 : 1;
9648 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
9652 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
9683 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
9685 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
9687 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
9689 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
9691 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
9693 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
9695 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
9697 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
9709 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
9711 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
9713 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
9715 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
9717 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
9719 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
9721 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
9723 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
9736 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
9738 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
9740 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
9742 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
9744 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
9746 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
9748 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
9750 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
9762 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
9764 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
9766 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
9768 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
9770 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
9772 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
9774 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
9776 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
9778 #ifndef __ASSEMBLY__
9789 struct ALT_NAND_ECC_ECCCORINFO_B23_s
9791 const uint32_t max_errors_b2 : 7;
9792 const uint32_t uncor_err_b2 : 1;
9793 const uint32_t max_errors_b3 : 7;
9794 const uint32_t uncor_err_b3 : 1;
9799 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
9803 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
9805 #ifndef __ASSEMBLY__
9816 struct ALT_NAND_ECC_s
9818 ALT_NAND_ECC_ECCCORINFO_B01_t ECCCorInfo_b01;
9819 volatile uint32_t _pad_0x4_0xf[3];
9820 ALT_NAND_ECC_ECCCORINFO_B23_t ECCCorInfo_b23;
9824 typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
9826 struct ALT_NAND_ECC_raw_s
9828 volatile uint32_t ECCCorInfo_b01;
9829 uint32_t _pad_0x4_0xf[3];
9830 volatile uint32_t ECCCorInfo_b23;
9834 typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
9864 #define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
9866 #define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
9868 #define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
9870 #define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
9872 #define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
9874 #define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
9876 #define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
9878 #define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
9880 #ifndef __ASSEMBLY__
9891 struct ALT_NAND_DMA_DMA_EN_s
9898 typedef volatile struct ALT_NAND_DMA_DMA_EN_s ALT_NAND_DMA_DMA_EN_t;
9902 #define ALT_NAND_DMA_DMA_EN_OFST 0x0
9927 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
9929 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
9931 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
9933 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
9935 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
9937 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
9939 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
9941 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
9943 #ifndef __ASSEMBLY__
9954 struct ALT_NAND_DMA_DMA_INTR_s
9956 uint32_t target_error : 1;
9961 typedef volatile struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
9965 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
9990 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
9992 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
9994 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
9996 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
9998 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
10000 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
10002 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
10004 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
10006 #ifndef __ASSEMBLY__
10017 struct ALT_NAND_DMA_DMA_INTR_EN_s
10019 uint32_t target_error : 1;
10024 typedef volatile struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
10028 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
10053 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
10055 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
10057 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
10059 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
10061 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
10063 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
10065 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10067 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10069 #ifndef __ASSEMBLY__
10080 struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
10082 const uint32_t value : 16;
10087 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s ALT_NAND_DMA_TGT_ERR_ADDR_LO_t;
10091 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
10116 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
10118 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
10120 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
10122 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
10124 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
10126 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
10128 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10130 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10132 #ifndef __ASSEMBLY__
10143 struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
10145 const uint32_t value : 16;
10150 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s ALT_NAND_DMA_TGT_ERR_ADDR_HI_t;
10154 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
10186 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
10188 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
10190 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
10192 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
10194 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
10196 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
10198 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
10200 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
10213 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
10215 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
10217 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
10219 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
10221 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
10223 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
10225 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
10227 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
10238 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_LSB 8
10240 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_MSB 31
10242 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_WIDTH 24
10244 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET_MSK 0xffffff00
10246 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_CLR_MSK 0x000000ff
10248 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_RESET 0x0
10250 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_GET(value) (((value) & 0xffffff00) >> 8)
10252 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET(value) (((value) << 8) & 0xffffff00)
10254 #ifndef __ASSEMBLY__
10265 struct ALT_NAND_DMA_FLSH_BURST_LEN_s
10267 uint32_t value : 2;
10269 uint32_t continous_burst : 1;
10271 uint32_t reserved : 24;
10275 typedef volatile struct ALT_NAND_DMA_FLSH_BURST_LEN_s ALT_NAND_DMA_FLSH_BURST_LEN_t;
10279 #define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
10305 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
10307 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
10309 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
10311 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
10313 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
10315 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
10317 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
10319 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
10336 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
10338 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
10340 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
10342 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
10344 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
10346 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
10348 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
10350 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
10352 #ifndef __ASSEMBLY__
10363 struct ALT_NAND_DMA_INTRLV_s
10365 uint32_t chip_interleave_enable : 1;
10367 uint32_t allow_int_reads_within_luns : 1;
10372 typedef volatile struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t;
10376 #define ALT_NAND_DMA_INTRLV_OFST 0x80
10404 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
10406 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
10408 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
10410 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
10412 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
10414 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
10416 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
10418 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
10420 #ifndef __ASSEMBLY__
10431 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
10433 uint32_t value : 4;
10438 typedef volatile struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
10442 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0x90
10467 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
10469 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
10471 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
10473 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
10475 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
10477 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
10479 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10481 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10483 #ifndef __ASSEMBLY__
10494 struct ALT_NAND_DMA_LUN_STAT_CMD_s
10496 uint32_t value : 16;
10501 typedef volatile struct ALT_NAND_DMA_LUN_STAT_CMD_s ALT_NAND_DMA_LUN_STAT_CMD_t;
10505 #define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xa0
10507 #ifndef __ASSEMBLY__
10518 struct ALT_NAND_DMA_s
10520 ALT_NAND_DMA_DMA_EN_t dma_enable;
10521 volatile uint32_t _pad_0x4_0x1f[7];
10522 ALT_NAND_DMA_DMA_INTR_t dma_intr;
10523 volatile uint32_t _pad_0x24_0x2f[3];
10524 ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en;
10525 volatile uint32_t _pad_0x34_0x3f[3];
10526 ALT_NAND_DMA_TGT_ERR_ADDR_LO_t target_err_addr_lo;
10527 volatile uint32_t _pad_0x44_0x4f[3];
10528 ALT_NAND_DMA_TGT_ERR_ADDR_HI_t target_err_addr_hi;
10529 volatile uint32_t _pad_0x54_0x6f[7];
10530 ALT_NAND_DMA_FLSH_BURST_LEN_t flash_burst_length;
10531 volatile uint32_t _pad_0x74_0x7f[3];
10532 ALT_NAND_DMA_INTRLV_t chip_interleave_enable_and_allow_int_reads;
10533 volatile uint32_t _pad_0x84_0x8f[3];
10534 ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun;
10535 volatile uint32_t _pad_0x94_0x9f[3];
10536 ALT_NAND_DMA_LUN_STAT_CMD_t lun_status_cmd;
10540 typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
10542 struct ALT_NAND_DMA_raw_s
10544 volatile uint32_t dma_enable;
10545 uint32_t _pad_0x4_0x1f[7];
10546 volatile uint32_t dma_intr;
10547 uint32_t _pad_0x24_0x2f[3];
10548 volatile uint32_t dma_intr_en;
10549 uint32_t _pad_0x34_0x3f[3];
10550 volatile uint32_t target_err_addr_lo;
10551 uint32_t _pad_0x44_0x4f[3];
10552 volatile uint32_t target_err_addr_hi;
10553 uint32_t _pad_0x54_0x6f[7];
10554 volatile uint32_t flash_burst_length;
10555 uint32_t _pad_0x74_0x7f[3];
10556 volatile uint32_t chip_interleave_enable_and_allow_int_reads;
10557 uint32_t _pad_0x84_0x8f[3];
10558 volatile uint32_t no_of_blocks_per_lun;
10559 uint32_t _pad_0x94_0x9f[3];
10560 volatile uint32_t lun_status_cmd;
10564 typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;
10568 #ifndef __ASSEMBLY__
10581 ALT_NAND_CFG_t config;
10582 volatile uint32_t _pad_0x2b4_0x2ff[19];
10583 ALT_NAND_PARAM_t param;
10584 volatile uint32_t _pad_0x3f4_0x3ff[3];
10585 ALT_NAND_STAT_t status;
10586 volatile uint32_t _pad_0x544_0x64f[67];
10587 ALT_NAND_ECC_t ecc;
10588 volatile uint32_t _pad_0x664_0x6ff[39];
10589 ALT_NAND_DMA_t dma;
10590 volatile uint32_t _pad_0x7a4_0x800[23];
10594 typedef volatile struct ALT_NAND_s ALT_NAND_t;
10596 struct ALT_NAND_raw_s
10598 ALT_NAND_CFG_raw_t config;
10599 uint32_t _pad_0x2b4_0x2ff[19];
10600 ALT_NAND_PARAM_raw_t param;
10601 uint32_t _pad_0x3f4_0x3ff[3];
10602 ALT_NAND_STAT_raw_t status;
10603 uint32_t _pad_0x544_0x64f[67];
10604 ALT_NAND_ECC_raw_t ecc;
10605 uint32_t _pad_0x664_0x6ff[39];
10606 ALT_NAND_DMA_raw_t dma;
10607 uint32_t _pad_0x7a4_0x800[23];
10611 typedef volatile struct ALT_NAND_raw_s ALT_NAND_raw_t;