Hardware Libraries  20.1
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alt_qspi.h
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32 
33 /* Altera - ALT_QSPI */
34 
35 #ifndef __ALT_SOCAL_QSPI_H__
36 #define __ALT_SOCAL_QSPI_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : QSPI
50  *
51  */
52 /*
53  * Register : QSPI Configuration Register - cfg
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:-------------------------------------------
59  * [0] | RW | 0x0 | QSPI Enable
60  * [1] | RW | 0x0 | Clock polarity outside SPI word
61  * [2] | RW | 0x0 | Select Clock Phase
62  * [6:3] | R | 0x0 | Reserved
63  * [7] | RW | 0x0 | Enable Direct Access Controller
64  * [8] | RW | 0x0 | Legacy IP Mode Enable
65  * [9] | RW | 0x0 | Peripheral select decode
66  * [13:10] | RW | 0x0 | Peripheral Chip Select Lines
67  * [14] | RW | 0x0 | Write Protect Flash Pin
68  * [15] | RW | 0x0 | Enable DMA Peripheral Interface
69  * [16] | RW | 0x0 | Enable AHB Address Re-mapping
70  * [17] | RW | 0x0 | Enter XIP Mode on next READ
71  * [18] | RW | 0x0 | Enter XIP Mode immediately
72  * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor
73  * [30:23] | R | 0x0 | Reserved
74  * [31] | R | 0x1 | Serial interface and QSPI pipeline is IDLE
75  *
76  */
77 /*
78  * Field : QSPI Enable - en
79  *
80  * 0 : disable the QSPI once current transfer of the data word (FF_W) is complete.
81  * 1 : enable the QSPI When spi_enable = 0, all output enables are inactive and all
82  * pins are set to input mode.
83  *
84  * Field Enumeration Values:
85  *
86  * Enum | Value | Description
87  * :--------------------------|:------|:-----------------
88  * ALT_QSPI_CFG_EN_E_DISABLE | 0x0 | Disable the QSPI
89  * ALT_QSPI_CFG_EN_E_ENABLE | 0x1 | Enable the QSPI
90  *
91  * Field Access Macros:
92  *
93  */
94 /*
95  * Enumerated value for register field ALT_QSPI_CFG_EN
96  *
97  * Disable the QSPI
98  */
99 #define ALT_QSPI_CFG_EN_E_DISABLE 0x0
100 /*
101  * Enumerated value for register field ALT_QSPI_CFG_EN
102  *
103  * Enable the QSPI
104  */
105 #define ALT_QSPI_CFG_EN_E_ENABLE 0x1
106 
107 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */
108 #define ALT_QSPI_CFG_EN_LSB 0
109 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */
110 #define ALT_QSPI_CFG_EN_MSB 0
111 /* The width in bits of the ALT_QSPI_CFG_EN register field. */
112 #define ALT_QSPI_CFG_EN_WIDTH 1
113 /* The mask used to set the ALT_QSPI_CFG_EN register field value. */
114 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
115 /* The mask used to clear the ALT_QSPI_CFG_EN register field value. */
116 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
117 /* The reset value of the ALT_QSPI_CFG_EN register field. */
118 #define ALT_QSPI_CFG_EN_RESET 0x0
119 /* Extracts the ALT_QSPI_CFG_EN field value from a register. */
120 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
121 /* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */
122 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
123 
124 /*
125  * Field : Clock polarity outside SPI word - selclkpol
126  *
127  * 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high
128  *
129  * Field Enumeration Values:
130  *
131  * Enum | Value | Description
132  * :------------------------------|:------|:----------------------------
133  * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high
134  * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low
135  *
136  * Field Access Macros:
137  *
138  */
139 /*
140  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
141  *
142  * SPI clock is quiescent high
143  */
144 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
145 /*
146  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
147  *
148  * SPI clock is quiescent low
149  */
150 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
151 
152 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
153 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
154 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
155 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
156 /* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */
157 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
158 /* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */
159 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
160 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */
161 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
162 /* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */
163 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
164 /* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */
165 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
166 /* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */
167 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
168 
169 /*
170  * Field : Select Clock Phase - selclkphase
171  *
172  * Selects whether the clock is in an active or inactive phase outside the SPI
173  * word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive
174  * outside the word
175  *
176  * Field Enumeration Values:
177  *
178  * Enum | Value | Description
179  * :------------------------------------|:------|:---------------------------
180  * ALT_QSPI_CFG_SELCLKPHASE_E_ACTIVE | 0x0 | SPI clock is quiescent low
181  * ALT_QSPI_CFG_SELCLKPHASE_E_INACTIVE | 0x1 | Clock Inactive
182  *
183  * Field Access Macros:
184  *
185  */
186 /*
187  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
188  *
189  * SPI clock is quiescent low
190  */
191 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACTIVE 0x0
192 /*
193  * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
194  *
195  * Clock Inactive
196  */
197 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACTIVE 0x1
198 
199 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
200 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
201 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
202 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
203 /* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */
204 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
205 /* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */
206 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
207 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */
208 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
209 /* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */
210 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
211 /* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */
212 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
213 /* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */
214 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
215 
216 /*
217  * Field : Reserved - config_resv1_fld
218  *
219  * Field Access Macros:
220  *
221  */
222 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field. */
223 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_LSB 3
224 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field. */
225 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_MSB 6
226 /* The width in bits of the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field. */
227 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_WIDTH 4
228 /* The mask used to set the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field value. */
229 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_SET_MSK 0x00000078
230 /* The mask used to clear the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field value. */
231 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_CLR_MSK 0xffffff87
232 /* The reset value of the ALT_QSPI_CFG_CONFIG_RESV1_FLD register field. */
233 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_RESET 0x0
234 /* Extracts the ALT_QSPI_CFG_CONFIG_RESV1_FLD field value from a register. */
235 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_GET(value) (((value) & 0x00000078) >> 3)
236 /* Produces a ALT_QSPI_CFG_CONFIG_RESV1_FLD register field value suitable for setting the register. */
237 #define ALT_QSPI_CFG_CONFIG_RESV1_FLD_SET(value) (((value) << 3) & 0x00000078)
238 
239 /*
240  * Field : Enable Direct Access Controller - endiracc
241  *
242  * 0 : disable the Direct Access Controller once current transfer of the data word
243  * (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct
244  * Access Controller and Indirect Access Controller are both disabled, all AHB
245  * requested are completed with an error response.
246  *
247  * Field Enumeration Values:
248  *
249  * Enum | Value | Description
250  * :--------------------------------|:------|:---------------------------
251  * ALT_QSPI_CFG_ENDIRACC_E_DISABLE | 0x0 | Disable Direct Access Ctrl
252  * ALT_QSPI_CFG_ENDIRACC_E_ENABLE | 0x1 | Enable Direct Access Ctrl
253  *
254  * Field Access Macros:
255  *
256  */
257 /*
258  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
259  *
260  * Disable Direct Access Ctrl
261  */
262 #define ALT_QSPI_CFG_ENDIRACC_E_DISABLE 0x0
263 /*
264  * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
265  *
266  * Enable Direct Access Ctrl
267  */
268 #define ALT_QSPI_CFG_ENDIRACC_E_ENABLE 0x1
269 
270 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
271 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
272 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
273 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
274 /* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */
275 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
276 /* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */
277 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
278 /* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */
279 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
280 /* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */
281 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
282 /* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */
283 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
284 /* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */
285 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
286 
287 /*
288  * Field : Legacy IP Mode Enable - enlegacyip
289  *
290  * 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is
291  * enabled. In this mode, any write to the controller via the AHB interface is
292  * serialized and sent to the FLASH device. Any valid AHB read will pop the
293  * internal RX-FIFO, retrieving data that was forwarded by the external FLASH
294  * device on the SPI lines,4,2 or 1 byte transfers are permitted and controlled via
295  * the HSIZE input.
296  *
297  * Field Enumeration Values:
298  *
299  * Enum | Value | Description
300  * :----------------------------------|:------|:--------------------------------------
301  * ALT_QSPI_CFG_ENLEGACYIP_E_DIMODE | 0x0 | Use Direct/Indirect Access Controller
302  * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMODE | 0x1 | Legacy Mode
303  *
304  * Field Access Macros:
305  *
306  */
307 /*
308  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
309  *
310  * Use Direct/Indirect Access Controller
311  */
312 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMODE 0x0
313 /*
314  * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
315  *
316  * Legacy Mode
317  */
318 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMODE 0x1
319 
320 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
321 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
322 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
323 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
324 /* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */
325 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
326 /* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */
327 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
328 /* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */
329 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
330 /* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */
331 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
332 /* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */
333 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
334 /* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */
335 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
336 
337 /*
338  * Field : Peripheral select decode - perseldec
339  *
340  * 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16
341  * decode (n_ss_out = ss)
342  *
343  * Field Enumeration Values:
344  *
345  * Enum | Value | Description
346  * :----------------------------------|:------|:----------------------------------
347  * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0]
348  * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode
349  *
350  * Field Access Macros:
351  *
352  */
353 /*
354  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
355  *
356  * Selects 1 of 4 qspi_n_ss_out[3:0]
357  */
358 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
359 /*
360  * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
361  *
362  * Select external 4-to-16 decode
363  */
364 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
365 
366 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
367 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
368 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
369 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
370 /* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */
371 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
372 /* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */
373 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
374 /* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */
375 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
376 /* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */
377 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
378 /* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */
379 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
380 /* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */
381 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
382 
383 /*
384  * Field : Peripheral Chip Select Lines - percslines
385  *
386  * Peripheral chip select lines If pdec = 0, ss[3:0] are output thus: ss[3:0]
387  * n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral
388  * selected) else ss[3:0] directly drives n_ss_out[3:0]
389  *
390  * Field Access Macros:
391  *
392  */
393 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
394 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
395 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
396 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
397 /* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */
398 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
399 /* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */
400 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
401 /* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */
402 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
403 /* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */
404 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
405 /* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */
406 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
407 /* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */
408 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
409 
410 /*
411  * Field : Write Protect Flash Pin - wp
412  *
413  * Set to drive the Write Protect pin of the FLASH device. This is resynchronized
414  * to the generated memory clock as necessary.
415  *
416  * Field Enumeration Values:
417  *
418  * Enum | Value | Description
419  * :-----------------------------|:------|:----------------------
420  * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect
421  * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect
422  *
423  * Field Access Macros:
424  *
425  */
426 /*
427  * Enumerated value for register field ALT_QSPI_CFG_WP
428  *
429  * Disable Write Protect
430  */
431 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
432 /*
433  * Enumerated value for register field ALT_QSPI_CFG_WP
434  *
435  * Enable Write Protect
436  */
437 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
438 
439 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */
440 #define ALT_QSPI_CFG_WP_LSB 14
441 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */
442 #define ALT_QSPI_CFG_WP_MSB 14
443 /* The width in bits of the ALT_QSPI_CFG_WP register field. */
444 #define ALT_QSPI_CFG_WP_WIDTH 1
445 /* The mask used to set the ALT_QSPI_CFG_WP register field value. */
446 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
447 /* The mask used to clear the ALT_QSPI_CFG_WP register field value. */
448 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
449 /* The reset value of the ALT_QSPI_CFG_WP register field. */
450 #define ALT_QSPI_CFG_WP_RESET 0x0
451 /* Extracts the ALT_QSPI_CFG_WP field value from a register. */
452 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
453 /* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */
454 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
455 
456 /*
457  * Field : Enable DMA Peripheral Interface - endma
458  *
459  * Set to 1 to enable the DMA handshaking logic. When enabled the QSPI will trigger
460  * DMA transfer requests via the DMA peripheral interface. Set to 0 to disable
461  *
462  * Field Enumeration Values:
463  *
464  * Enum | Value | Description
465  * :-----------------------------|:------|:-----------------
466  * ALT_QSPI_CFG_ENDMA_E_DISABLE | 0x0 | Disable DMA Mode
467  * ALT_QSPI_CFG_ENDMA_E_ENABLE | 0x1 | Enable DMA Mode
468  *
469  * Field Access Macros:
470  *
471  */
472 /*
473  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
474  *
475  * Disable DMA Mode
476  */
477 #define ALT_QSPI_CFG_ENDMA_E_DISABLE 0x0
478 /*
479  * Enumerated value for register field ALT_QSPI_CFG_ENDMA
480  *
481  * Enable DMA Mode
482  */
483 #define ALT_QSPI_CFG_ENDMA_E_ENABLE 0x1
484 
485 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */
486 #define ALT_QSPI_CFG_ENDMA_LSB 15
487 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */
488 #define ALT_QSPI_CFG_ENDMA_MSB 15
489 /* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */
490 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
491 /* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */
492 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
493 /* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */
494 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
495 /* The reset value of the ALT_QSPI_CFG_ENDMA register field. */
496 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
497 /* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */
498 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
499 /* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */
500 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
501 
502 /*
503  * Field : Enable AHB Address Re-mapping - enahbremap
504  *
505  * (Direct Access Mode Only) When set to 1, the incoming AHB address will be
506  * adapted and sent to the FLASH device as (address + N), where N is the value
507  * stored in the remap address register.
508  *
509  * Field Enumeration Values:
510  *
511  * Enum | Value | Description
512  * :----------------------------------|:------|:-----------------------
513  * ALT_QSPI_CFG_ENAHBREMAP_E_DISABLE | 0x0 | Disable AHB Re-mapping
514  * ALT_QSPI_CFG_ENAHBREMAP_E_ENABLE | 0x1 | Enable AHB Re-mapping
515  *
516  * Field Access Macros:
517  *
518  */
519 /*
520  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
521  *
522  * Disable AHB Re-mapping
523  */
524 #define ALT_QSPI_CFG_ENAHBREMAP_E_DISABLE 0x0
525 /*
526  * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
527  *
528  * Enable AHB Re-mapping
529  */
530 #define ALT_QSPI_CFG_ENAHBREMAP_E_ENABLE 0x1
531 
532 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
533 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
534 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
535 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
536 /* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */
537 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
538 /* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */
539 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
540 /* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */
541 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
542 /* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */
543 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
544 /* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */
545 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
546 /* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */
547 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
548 
549 /*
550  * Field : Enter XIP Mode on next READ - enterxipnextrd
551  *
552  * Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit
553  * XIP mode on the next READ instruction. Value=1 : If XIP is disabled, then
554  * setting to ?1? will inform the controller that the device is ready to enter XIP
555  * on the next READ instruction. The controller will therefore send the appropriate
556  * command sequence, including mode bits to cause the device to enter XIP mode. Use
557  * this register after the controller has ensured the FLASH device has been
558  * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit
559  * should be set to 0. This will take effect in the attached device only AFTER the
560  * next READ instruction is executed. Software should therefore ensure that at
561  * least one READ instruction is requested after resetting this bit before it can
562  * be sure XIP mode in the device is exited.
563  *
564  * Field Enumeration Values:
565  *
566  * Enum | Value | Description
567  * :--------------------------------------|:------|:----------------------------------------
568  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DISABLE | 0x0 | Exit XIP Mode on next READ instruction
569  * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_ENABLE | 0x1 | Enter XIP Mode on next READ instruction
570  *
571  * Field Access Macros:
572  *
573  */
574 /*
575  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
576  *
577  * Exit XIP Mode on next READ instruction
578  */
579 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DISABLE 0x0
580 /*
581  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
582  *
583  * Enter XIP Mode on next READ instruction
584  */
585 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_ENABLE 0x1
586 
587 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
588 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
589 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
590 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
591 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
592 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
593 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
594 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
595 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
596 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
597 /* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
598 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
599 /* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */
600 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
601 /* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */
602 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
603 
604 /*
605  * Field : Enter XIP Mode immediately - enterxipimm
606  *
607  * Value=0 : If XIP is enabled, then setting to 0 will cause the controller to exit
608  * XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode
609  * immediately Use this register when the external device wakes up in XIP mode (as
610  * per the contents of its non- volatile configuration register). The controller
611  * will assume the next READ instruction will be passed to the device as an XIP
612  * instruction, and therefore will not require the READ opcode to be transferred.
613  * Note: To exit XIP mode, this bit should be set to 0. This will take effect in
614  * the attached device only after the next READ instruction is executed. Software
615  * therefore should ensure that at least one READ instruction is requested after
616  * resetting this bit in order to be sure that XIP mode is exited.
617  *
618  * Field Enumeration Values:
619  *
620  * Enum | Value | Description
621  * :-----------------------------------|:------|:---------------------------------------
622  * ALT_QSPI_CFG_ENTERXIPIMM_E_DISABLE | 0x0 | Exit XIP Mode on next READ instruction
623  * ALT_QSPI_CFG_ENTERXIPIMM_E_ENABLE | 0x1 | Enter XIP Mode immediately
624  *
625  * Field Access Macros:
626  *
627  */
628 /*
629  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
630  *
631  * Exit XIP Mode on next READ instruction
632  */
633 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DISABLE 0x0
634 /*
635  * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
636  *
637  * Enter XIP Mode immediately
638  */
639 #define ALT_QSPI_CFG_ENTERXIPIMM_E_ENABLE 0x1
640 
641 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
642 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
643 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
644 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
645 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
646 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
647 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
648 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
649 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
650 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
651 /* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
652 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
653 /* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */
654 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
655 /* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */
656 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
657 
658 /*
659  * Field : Master Mode Baud Rate Divisor - bauddiv
660  *
661  * SPI baud rae = (master reference clock) baud_rate_divisor
662  *
663  * Field Enumeration Values:
664  *
665  * Enum | Value | Description
666  * :------------------------------|:------|:-----------------
667  * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2
668  * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4
669  * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6
670  * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8
671  * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10
672  * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12
673  * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14
674  * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16
675  * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18
676  * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20
677  * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22
678  * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24
679  * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26
680  * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28
681  * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30
682  * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32
683  *
684  * Field Access Macros:
685  *
686  */
687 /*
688  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
689  *
690  * Baud Rate Div/2
691  */
692 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
693 /*
694  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
695  *
696  * Baud Rate Div/4
697  */
698 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
699 /*
700  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
701  *
702  * Baud Rate Div/6
703  */
704 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
705 /*
706  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
707  *
708  * Baud Rate Div/8
709  */
710 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
711 /*
712  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
713  *
714  * Baud Rate Div/10
715  */
716 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
717 /*
718  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
719  *
720  * Baud Rate Div/12
721  */
722 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
723 /*
724  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
725  *
726  * Baud Rate Div/14
727  */
728 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
729 /*
730  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
731  *
732  * Baud Rate Div/16
733  */
734 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
735 /*
736  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
737  *
738  * Baud Rate Div/18
739  */
740 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
741 /*
742  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
743  *
744  * Baud Rate Div/20
745  */
746 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
747 /*
748  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
749  *
750  * Baud Rate Div/22
751  */
752 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
753 /*
754  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
755  *
756  * Baud Rate Div/24
757  */
758 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
759 /*
760  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
761  *
762  * Baud Rate Div/26
763  */
764 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
765 /*
766  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
767  *
768  * Baud Rate Div/28
769  */
770 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
771 /*
772  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
773  *
774  * Baud Rate Div/30
775  */
776 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
777 /*
778  * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
779  *
780  * Baud Rate Div/32
781  */
782 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
783 
784 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
785 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
786 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
787 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
788 /* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */
789 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
790 /* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */
791 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
792 /* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */
793 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
794 /* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */
795 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
796 /* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */
797 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
798 /* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */
799 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
800 
801 /*
802  * Field : Reserved - config_resv2_fld
803  *
804  * Field Access Macros:
805  *
806  */
807 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field. */
808 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_LSB 23
809 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field. */
810 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_MSB 30
811 /* The width in bits of the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field. */
812 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_WIDTH 8
813 /* The mask used to set the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field value. */
814 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_SET_MSK 0x7f800000
815 /* The mask used to clear the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field value. */
816 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_CLR_MSK 0x807fffff
817 /* The reset value of the ALT_QSPI_CFG_CONFIG_RESV2_FLD register field. */
818 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_RESET 0x0
819 /* Extracts the ALT_QSPI_CFG_CONFIG_RESV2_FLD field value from a register. */
820 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_GET(value) (((value) & 0x7f800000) >> 23)
821 /* Produces a ALT_QSPI_CFG_CONFIG_RESV2_FLD register field value suitable for setting the register. */
822 #define ALT_QSPI_CFG_CONFIG_RESV2_FLD_SET(value) (((value) << 23) & 0x7f800000)
823 
824 /*
825  * Field : Serial interface and QSPI pipeline is IDLE - idle
826  *
827  * This is a STATUS read-only bit. Note this is a retimed signal, so there will be
828  * some inherent delay on the generation of this status signal.
829  *
830  * Field Enumeration Values:
831  *
832  * Enum | Value | Description
833  * :---------------------------|:------|:--------------
834  * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode
835  * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode
836  *
837  * Field Access Macros:
838  *
839  */
840 /*
841  * Enumerated value for register field ALT_QSPI_CFG_IDLE
842  *
843  * Non-Idle Mode
844  */
845 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
846 /*
847  * Enumerated value for register field ALT_QSPI_CFG_IDLE
848  *
849  * Idle Mode
850  */
851 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
852 
853 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */
854 #define ALT_QSPI_CFG_IDLE_LSB 31
855 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */
856 #define ALT_QSPI_CFG_IDLE_MSB 31
857 /* The width in bits of the ALT_QSPI_CFG_IDLE register field. */
858 #define ALT_QSPI_CFG_IDLE_WIDTH 1
859 /* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */
860 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
861 /* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */
862 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
863 /* The reset value of the ALT_QSPI_CFG_IDLE register field. */
864 #define ALT_QSPI_CFG_IDLE_RESET 0x1
865 /* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */
866 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
867 /* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */
868 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
869 
870 #ifndef __ASSEMBLY__
871 /*
872  * WARNING: The C register and register group struct declarations are provided for
873  * convenience and illustrative purposes. They should, however, be used with
874  * caution as the C language standard provides no guarantees about the alignment or
875  * atomicity of device memory accesses. The recommended practice for coding device
876  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
877  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
878  * alt_write_dword() functions for 64 bit registers.
879  *
880  * The struct declaration for register ALT_QSPI_CFG.
881  */
882 struct ALT_QSPI_CFG_s
883 {
884  volatile uint32_t en : 1; /* QSPI Enable */
885  volatile uint32_t selclkpol : 1; /* Clock polarity outside SPI word */
886  volatile uint32_t selclkphase : 1; /* Select Clock Phase */
887  const volatile uint32_t config_resv1_fld : 4; /* Reserved */
888  volatile uint32_t endiracc : 1; /* Enable Direct Access Controller */
889  volatile uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */
890  volatile uint32_t perseldec : 1; /* Peripheral select decode */
891  volatile uint32_t percslines : 4; /* Peripheral Chip Select Lines */
892  volatile uint32_t wp : 1; /* Write Protect Flash Pin */
893  volatile uint32_t endma : 1; /* Enable DMA Peripheral Interface */
894  volatile uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */
895  volatile uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */
896  volatile uint32_t enterxipimm : 1; /* Enter XIP Mode immediately */
897  volatile uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */
898  const volatile uint32_t config_resv2_fld : 8; /* Reserved */
899  const volatile uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */
900 };
901 
902 /* The typedef declaration for register ALT_QSPI_CFG. */
903 typedef struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
904 #endif /* __ASSEMBLY__ */
905 
906 /* The reset value of the ALT_QSPI_CFG register. */
907 #define ALT_QSPI_CFG_RESET 0x80780000
908 /* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */
909 #define ALT_QSPI_CFG_OFST 0x0
910 /* The address of the ALT_QSPI_CFG register. */
911 #define ALT_QSPI_CFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_CFG_OFST))
912 
913 /*
914  * Register : Device Read Instruction Configuration Register - devrd
915  *
916  * Register Layout
917  *
918  * Bits | Access | Reset | Description
919  * :--------|:-------|:------|:---------------------------------------------
920  * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode
921  * [9:8] | RW | 0x0 | Instruction Type
922  * [11:10] | R | 0x0 | Reserved
923  * [13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes
924  * [15:14] | R | 0x0 | Reserved
925  * [17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes
926  * [19:18] | R | 0x0 | Reserved
927  * [20] | RW | 0x0 | Mode Bit Enable
928  * [23:21] | R | 0x0 | Reserved
929  * [28:24] | RW | 0x0 | Dummy Read Clock Cycles
930  * [31:29] | R | 0x0 | Reserved
931  *
932  */
933 /*
934  * Field : Read Opcode in non-XIP mode - rdopcode
935  *
936  * Read Opcode to use when not in XIP mode
937  *
938  * Field Enumeration Values:
939  *
940  * Enum | Value | Description
941  * :-----------------------------------|:------|:----------------------------
942  * ALT_QSPI_DEVRD_RDOPCODE_E_READ | 0x3 | Read Opcode in Non-XIP mode
943  * ALT_QSPI_DEVRD_RDOPCODE_E_FASTREAD | 0xb | Fast Read in Non-XIP mode
944  *
945  * Field Access Macros:
946  *
947  */
948 /*
949  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
950  *
951  * Read Opcode in Non-XIP mode
952  */
953 #define ALT_QSPI_DEVRD_RDOPCODE_E_READ 0x3
954 /*
955  * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
956  *
957  * Fast Read in Non-XIP mode
958  */
959 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTREAD 0xb
960 
961 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
962 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
963 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
964 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
965 /* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */
966 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
967 /* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */
968 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
969 /* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */
970 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
971 /* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */
972 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
973 /* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */
974 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
975 /* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */
976 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
977 
978 /*
979  * Field : Instruction Type - instwidth
980  *
981  * 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0
982  * only) 1 : Use DIO-SPI mode (Instructions, Address and Data always sent on DQ0
983  * and DQ1) 2 : Use QIO-SPI mode (Instructions, Address and Data always sent on
984  * DQ0, DQ1, DQ2 and DDQ3)
985  *
986  * Field Enumeration Values:
987  *
988  * Enum | Value | Description
989  * :----------------------------------|:------|:-------------------------------------------------
990  * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all
991  * : | | SPI flash devices.
992  * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1.
993  * : | | Supported by all SPI flash devices that support
994  * : | | the Dual SP (DIO-SPI) Protocol.
995  * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and
996  * : | | DQ3. Supported by all SPI flash devices that
997  * : | | support the Quad SP (QIO-SPI) Protocol.
998  *
999  * Field Access Macros:
1000  *
1001  */
1002 /*
1003  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1004  *
1005  * Instruction transferred on DQ0. Supported by all SPI flash devices.
1006  */
1007 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
1008 /*
1009  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1010  *
1011  * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that
1012  * support the Dual SP (DIO-SPI) Protocol.
1013  */
1014 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
1015 /*
1016  * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
1017  *
1018  * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash
1019  * devices that support the Quad SP (QIO-SPI) Protocol.
1020  */
1021 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
1022 
1023 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1024 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
1025 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1026 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
1027 /* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1028 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
1029 /* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
1030 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
1031 /* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
1032 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
1033 /* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
1034 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
1035 /* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */
1036 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
1037 /* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */
1038 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1039 
1040 /*
1041  * Field : Reserved - rd_instr_resv1_fld
1042  *
1043  * Field Access Macros:
1044  *
1045  */
1046 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1047 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10
1048 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1049 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11
1050 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1051 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2
1052 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value. */
1053 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00
1054 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value. */
1055 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff
1056 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field. */
1057 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0
1058 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD field value from a register. */
1059 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10)
1060 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value suitable for setting the register. */
1061 #define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00)
1062 
1063 /*
1064  * Field : Address Transfer Type for Standard SPI modes - addrwidth
1065  *
1066  * 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be
1067  * shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the
1068  * device on DQ0, DQ1, DQ2 and DQ3
1069  *
1070  * Field Enumeration Values:
1071  *
1072  * Enum | Value | Description
1073  * :----------------------------------|:------|:-------------------------------------------------
1074  * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by
1075  * : | | all SPI flash devices
1076  * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1077  * : | | Supported by some SPI flash devices that support
1078  * : | | the Extended SPI Protocol and by all SPI flash
1079  * : | | devices that support the Dual SP (DIO-SPI)
1080  * : | | Protocol.
1081  * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1082  * : | | DQ3. Supported by some SPI flash devices that
1083  * : | | support the Extended SPI Protocol and by all SPI
1084  * : | | flash devices that support the Quad SP (QIO-SPI)
1085  * : | | Protocol.
1086  *
1087  * Field Access Macros:
1088  *
1089  */
1090 /*
1091  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1092  *
1093  * Read address transferred on DQ0. Supported by all SPI flash devices
1094  */
1095 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1096 /*
1097  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1098  *
1099  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1100  * that support the Extended SPI Protocol and by all SPI flash devices that support
1101  * the Dual SP (DIO-SPI) Protocol.
1102  */
1103 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1104 /*
1105  * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
1106  *
1107  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1108  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1109  * support the Quad SP (QIO-SPI) Protocol.
1110  */
1111 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1112 
1113 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1114 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1115 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1116 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1117 /* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1118 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1119 /* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1120 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1121 /* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
1122 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1123 /* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
1124 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1125 /* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */
1126 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1127 /* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */
1128 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1129 
1130 /*
1131  * Field : Reserved - rd_instr_resv2_fld
1132  *
1133  * Field Access Macros:
1134  *
1135  */
1136 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1137 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14
1138 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1139 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15
1140 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1141 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2
1142 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value. */
1143 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1144 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value. */
1145 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1146 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field. */
1147 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0
1148 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD field value from a register. */
1149 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1150 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value suitable for setting the register. */
1151 #define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1152 
1153 /*
1154  * Field : Data Transfer Type for Standard SPI modes - datawidth
1155  *
1156  * 0 : SIO mode data is shifted to the device on DQ0 only and from the device on
1157  * DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0
1158  * and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output
1159  * instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs
1160  * and outputs.
1161  *
1162  * Field Enumeration Values:
1163  *
1164  * Enum | Value | Description
1165  * :----------------------------------|:------|:-------------------------------------------------
1166  * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all
1167  * : | | SPI flash devices
1168  * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1169  * : | | by some SPI flash devices that support the
1170  * : | | Extended SPI Protocol and by all SPI flash
1171  * : | | devices that support the Dual SP (DIO-SPI)
1172  * : | | Protocol.
1173  * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1174  * : | | Supported by some SPI flash devices that support
1175  * : | | the Extended SPI Protocol and by all SPI flash
1176  * : | | devices that support the Quad SP (QIO-SPI)
1177  * : | | Protocol.
1178  *
1179  * Field Access Macros:
1180  *
1181  */
1182 /*
1183  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1184  *
1185  * Read data transferred on DQ0. Supported by all SPI flash devices
1186  */
1187 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1188 /*
1189  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1190  *
1191  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1192  * support the Extended SPI Protocol and by all SPI flash devices that support the
1193  * Dual SP (DIO-SPI) Protocol.
1194  */
1195 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1196 /*
1197  * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
1198  *
1199  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1200  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1201  * support the Quad SP (QIO-SPI) Protocol.
1202  */
1203 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1204 
1205 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1206 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1207 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1208 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1209 /* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1210 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1211 /* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1212 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1213 /* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
1214 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1215 /* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
1216 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1217 /* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */
1218 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1219 /* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */
1220 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1221 
1222 /*
1223  * Field : Reserved - rd_instr_resv3_fld
1224  *
1225  * Field Access Macros:
1226  *
1227  */
1228 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1229 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18
1230 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1231 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19
1232 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1233 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2
1234 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value. */
1235 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000
1236 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value. */
1237 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff
1238 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field. */
1239 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0
1240 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD field value from a register. */
1241 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18)
1242 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value suitable for setting the register. */
1243 #define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000)
1244 
1245 /*
1246  * Field : Mode Bit Enable - enmodebits
1247  *
1248  * Set this field to 1 to ensure that the mode bits as defined in the Mode Bit
1249  * Configuration register are sent following the address bytes.
1250  *
1251  * Field Enumeration Values:
1252  *
1253  * Enum | Value | Description
1254  * :------------------------------------|:------|:-------------------------------
1255  * ALT_QSPI_DEVRD_ENMODEBITS_E_NOORDER | 0x0 | No Order
1256  * ALT_QSPI_DEVRD_ENMODEBITS_E_ORDER | 0x1 | Mode Bits follow address bytes
1257  *
1258  * Field Access Macros:
1259  *
1260  */
1261 /*
1262  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODEBITS
1263  *
1264  * No Order
1265  */
1266 #define ALT_QSPI_DEVRD_ENMODEBITS_E_NOORDER 0x0
1267 /*
1268  * Enumerated value for register field ALT_QSPI_DEVRD_ENMODEBITS
1269  *
1270  * Mode Bits follow address bytes
1271  */
1272 #define ALT_QSPI_DEVRD_ENMODEBITS_E_ORDER 0x1
1273 
1274 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODEBITS register field. */
1275 #define ALT_QSPI_DEVRD_ENMODEBITS_LSB 20
1276 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODEBITS register field. */
1277 #define ALT_QSPI_DEVRD_ENMODEBITS_MSB 20
1278 /* The width in bits of the ALT_QSPI_DEVRD_ENMODEBITS register field. */
1279 #define ALT_QSPI_DEVRD_ENMODEBITS_WIDTH 1
1280 /* The mask used to set the ALT_QSPI_DEVRD_ENMODEBITS register field value. */
1281 #define ALT_QSPI_DEVRD_ENMODEBITS_SET_MSK 0x00100000
1282 /* The mask used to clear the ALT_QSPI_DEVRD_ENMODEBITS register field value. */
1283 #define ALT_QSPI_DEVRD_ENMODEBITS_CLR_MSK 0xffefffff
1284 /* The reset value of the ALT_QSPI_DEVRD_ENMODEBITS register field. */
1285 #define ALT_QSPI_DEVRD_ENMODEBITS_RESET 0x0
1286 /* Extracts the ALT_QSPI_DEVRD_ENMODEBITS field value from a register. */
1287 #define ALT_QSPI_DEVRD_ENMODEBITS_GET(value) (((value) & 0x00100000) >> 20)
1288 /* Produces a ALT_QSPI_DEVRD_ENMODEBITS register field value suitable for setting the register. */
1289 #define ALT_QSPI_DEVRD_ENMODEBITS_SET(value) (((value) << 20) & 0x00100000)
1290 
1291 /*
1292  * Field : Reserved - rd_instr_resv4_fld
1293  *
1294  * Field Access Macros:
1295  *
1296  */
1297 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1298 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21
1299 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1300 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23
1301 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1302 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3
1303 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value. */
1304 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000
1305 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value. */
1306 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff
1307 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field. */
1308 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0
1309 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD field value from a register. */
1310 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21)
1311 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value suitable for setting the register. */
1312 #define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000)
1313 
1314 /*
1315  * Field : Dummy Read Clock Cycles - dummyrdclks
1316  *
1317  * Number of dummy clock cycles required by device for read instruction.
1318  *
1319  * Field Access Macros:
1320  *
1321  */
1322 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1323 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1324 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1325 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1326 /* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1327 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1328 /* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1329 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1330 /* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
1331 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1332 /* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
1333 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1334 /* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */
1335 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1336 /* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */
1337 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1338 
1339 /*
1340  * Field : Reserved - rd_instr_resv5_fld
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1346 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29
1347 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1348 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31
1349 /* The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1350 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3
1351 /* The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value. */
1352 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000
1353 /* The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value. */
1354 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff
1355 /* The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field. */
1356 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0
1357 /* Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD field value from a register. */
1358 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1359 /* Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value suitable for setting the register. */
1360 #define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000)
1361 
1362 #ifndef __ASSEMBLY__
1363 /*
1364  * WARNING: The C register and register group struct declarations are provided for
1365  * convenience and illustrative purposes. They should, however, be used with
1366  * caution as the C language standard provides no guarantees about the alignment or
1367  * atomicity of device memory accesses. The recommended practice for coding device
1368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1370  * alt_write_dword() functions for 64 bit registers.
1371  *
1372  * The struct declaration for register ALT_QSPI_DEVRD.
1373  */
1374 struct ALT_QSPI_DEVRD_s
1375 {
1376  volatile uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */
1377  volatile uint32_t instwidth : 2; /* Instruction Type */
1378  const volatile uint32_t rd_instr_resv1_fld : 2; /* Reserved */
1379  volatile uint32_t addrwidth : 2; /* Address Transfer Type for Standard SPI modes */
1380  const volatile uint32_t rd_instr_resv2_fld : 2; /* Reserved */
1381  volatile uint32_t datawidth : 2; /* Data Transfer Type for Standard SPI modes */
1382  const volatile uint32_t rd_instr_resv3_fld : 2; /* Reserved */
1383  volatile uint32_t enmodebits : 1; /* Mode Bit Enable */
1384  const volatile uint32_t rd_instr_resv4_fld : 3; /* Reserved */
1385  volatile uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */
1386  const volatile uint32_t rd_instr_resv5_fld : 3; /* Reserved */
1387 };
1388 
1389 /* The typedef declaration for register ALT_QSPI_DEVRD. */
1390 typedef struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1391 #endif /* __ASSEMBLY__ */
1392 
1393 /* The reset value of the ALT_QSPI_DEVRD register. */
1394 #define ALT_QSPI_DEVRD_RESET 0x00000003
1395 /* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */
1396 #define ALT_QSPI_DEVRD_OFST 0x4
1397 /* The address of the ALT_QSPI_DEVRD register. */
1398 #define ALT_QSPI_DEVRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVRD_OFST))
1399 
1400 /*
1401  * Register : Device Write Instruction Configuration Register - devwr
1402  *
1403  * Register Layout
1404  *
1405  * Bits | Access | Reset | Description
1406  * :--------|:-------|:------|:---------------------------------------------
1407  * [7:0] | RW | 0x2 | Write Opcode
1408  * [11:8] | R | 0x0 | Reserved
1409  * [13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes
1410  * [15:14] | R | 0x0 | Reserved
1411  * [17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes
1412  * [23:18] | R | 0x0 | Reserved
1413  * [28:24] | RW | 0x0 | Dummy Write Clock Cycles
1414  * [31:29] | R | 0x0 | Reserved
1415  *
1416  */
1417 /*
1418  * Field : Write Opcode - wropcode
1419  *
1420  * Write Opcode
1421  *
1422  * Field Access Macros:
1423  *
1424  */
1425 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1426 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1427 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
1428 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1429 /* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */
1430 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1431 /* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */
1432 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1433 /* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */
1434 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1435 /* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */
1436 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1437 /* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */
1438 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1439 /* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */
1440 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1441 
1442 /*
1443  * Field : Reserved - wr_instr_resv1_fld
1444  *
1445  * Field Access Macros:
1446  *
1447  */
1448 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1449 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8
1450 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1451 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11
1452 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1453 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4
1454 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value. */
1455 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00
1456 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value. */
1457 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff
1458 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field. */
1459 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0
1460 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD field value from a register. */
1461 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8)
1462 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value suitable for setting the register. */
1463 #define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00)
1464 
1465 /*
1466  * Field : Address Transfer Type for Standard SPI modes - addrwidth
1467  *
1468  * 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be
1469  * shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the
1470  * device on DQ0, DQ1, DQ2 and DQ3
1471  *
1472  * Field Enumeration Values:
1473  *
1474  * Enum | Value | Description
1475  * :----------------------------------|:------|:-------------------------------------------------
1476  * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by
1477  * : | | all SPI flash devices
1478  * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
1479  * : | | Supported by some SPI flash devices that support
1480  * : | | the Extended SPI Protocol and by all SPI flash
1481  * : | | devices that support the Dual SP (DIO-SPI)
1482  * : | | Protocol.
1483  * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
1484  * : | | DQ3. Supported by some SPI flash devices that
1485  * : | | support the Extended SPI Protocol and by all SPI
1486  * : | | flash devices that support the Quad SP (QIO-SPI)
1487  * : | | Protocol.
1488  *
1489  * Field Access Macros:
1490  *
1491  */
1492 /*
1493  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1494  *
1495  * Write address transferred on DQ0. Supported by all SPI flash devices
1496  */
1497 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1498 /*
1499  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1500  *
1501  * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
1502  * that support the Extended SPI Protocol and by all SPI flash devices that support
1503  * the Dual SP (DIO-SPI) Protocol.
1504  */
1505 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1506 /*
1507  * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
1508  *
1509  * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1510  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1511  * support the Quad SP (QIO-SPI) Protocol.
1512  */
1513 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1514 
1515 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1516 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1517 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1518 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1519 /* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1520 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1521 /* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1522 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1523 /* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
1524 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1525 /* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
1526 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1527 /* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */
1528 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1529 /* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */
1530 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1531 
1532 /*
1533  * Field : Reserved - wr_instr_resv2_fld
1534  *
1535  * Field Access Macros:
1536  *
1537  */
1538 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1539 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14
1540 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1541 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15
1542 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1543 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2
1544 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value. */
1545 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1546 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value. */
1547 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1548 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field. */
1549 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0
1550 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD field value from a register. */
1551 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1552 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value suitable for setting the register. */
1553 #define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1554 
1555 /*
1556  * Field : Data Transfer Type for Standard SPI modes - datawidth
1557  *
1558  * 0 : SIO mode data is shifted to the device on DQ0 only and from the device on
1559  * DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0
1560  * and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output
1561  * instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs
1562  * and outputs.
1563  *
1564  * Field Enumeration Values:
1565  *
1566  * Enum | Value | Description
1567  * :----------------------------------|:------|:-------------------------------------------------
1568  * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all
1569  * : | | SPI flash devices
1570  * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
1571  * : | | by some SPI flash devices that support the
1572  * : | | Extended SPI Protocol and by all SPI flash
1573  * : | | devices that support the Dual SP (DIO-SPI)
1574  * : | | Protocol.
1575  * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
1576  * : | | Supported by some SPI flash devices that support
1577  * : | | the Extended SPI Protocol and by all SPI flash
1578  * : | | devices that support the Quad SP (QIO-SPI)
1579  * : | | Protocol.
1580  *
1581  * Field Access Macros:
1582  *
1583  */
1584 /*
1585  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1586  *
1587  * Write data transferred on DQ0. Supported by all SPI flash devices
1588  */
1589 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1590 /*
1591  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1592  *
1593  * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
1594  * support the Extended SPI Protocol and by all SPI flash devices that support the
1595  * Dual SP (DIO-SPI) Protocol.
1596  */
1597 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1598 /*
1599  * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
1600  *
1601  * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
1602  * devices that support the Extended SPI Protocol and by all SPI flash devices that
1603  * support the Quad SP (QIO-SPI) Protocol.
1604  */
1605 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1606 
1607 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1608 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1609 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1610 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1611 /* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1612 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1613 /* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1614 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1615 /* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
1616 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1617 /* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
1618 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1619 /* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */
1620 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1621 /* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */
1622 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1623 
1624 /*
1625  * Field : Reserved - wr_instr_resv3_fld
1626  *
1627  * Field Access Macros:
1628  *
1629  */
1630 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1631 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18
1632 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1633 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23
1634 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1635 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6
1636 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value. */
1637 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000
1638 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value. */
1639 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff
1640 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field. */
1641 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0
1642 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD field value from a register. */
1643 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18)
1644 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value suitable for setting the register. */
1645 #define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000)
1646 
1647 /*
1648  * Field : Dummy Write Clock Cycles - dummywrclks
1649  *
1650  * Number of dummy clock cycles required by device for write instruction.
1651  *
1652  * Field Access Macros:
1653  *
1654  */
1655 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1656 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1657 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1658 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1659 /* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1660 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1661 /* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1662 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1663 /* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
1664 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1665 /* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
1666 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1667 /* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */
1668 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1669 /* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */
1670 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1671 
1672 /*
1673  * Field : Reserved - wr_instr_resv4_fld
1674  *
1675  * Field Access Macros:
1676  *
1677  */
1678 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1679 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29
1680 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1681 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31
1682 /* The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1683 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3
1684 /* The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value. */
1685 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000
1686 /* The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value. */
1687 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff
1688 /* The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field. */
1689 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0
1690 /* Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD field value from a register. */
1691 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1692 /* Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value suitable for setting the register. */
1693 #define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000)
1694 
1695 #ifndef __ASSEMBLY__
1696 /*
1697  * WARNING: The C register and register group struct declarations are provided for
1698  * convenience and illustrative purposes. They should, however, be used with
1699  * caution as the C language standard provides no guarantees about the alignment or
1700  * atomicity of device memory accesses. The recommended practice for coding device
1701  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1702  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1703  * alt_write_dword() functions for 64 bit registers.
1704  *
1705  * The struct declaration for register ALT_QSPI_DEVWR.
1706  */
1707 struct ALT_QSPI_DEVWR_s
1708 {
1709  volatile uint32_t wropcode : 8; /* Write Opcode */
1710  const volatile uint32_t wr_instr_resv1_fld : 4; /* Reserved */
1711  volatile uint32_t addrwidth : 2; /* Address Transfer Type for Standard SPI modes */
1712  const volatile uint32_t wr_instr_resv2_fld : 2; /* Reserved */
1713  volatile uint32_t datawidth : 2; /* Data Transfer Type for Standard SPI modes */
1714  const volatile uint32_t wr_instr_resv3_fld : 6; /* Reserved */
1715  volatile uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */
1716  const volatile uint32_t wr_instr_resv4_fld : 3; /* Reserved */
1717 };
1718 
1719 /* The typedef declaration for register ALT_QSPI_DEVWR. */
1720 typedef struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1721 #endif /* __ASSEMBLY__ */
1722 
1723 /* The reset value of the ALT_QSPI_DEVWR register. */
1724 #define ALT_QSPI_DEVWR_RESET 0x00000002
1725 /* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */
1726 #define ALT_QSPI_DEVWR_OFST 0x8
1727 /* The address of the ALT_QSPI_DEVWR register. */
1728 #define ALT_QSPI_DEVWR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVWR_OFST))
1729 
1730 /*
1731  * Register : QSPI Device Delay Register - delay
1732  *
1733  * This register is used to introduce relative delays into the generation of the
1734  * master output signals. All timings are defined in cycles of the SPI REFERENCE
1735  * CLOCK/ext_clk, defined in this table as SPI master ref clock.
1736  *
1737  * Register Layout
1738  *
1739  * Bits | Access | Reset | Description
1740  * :--------|:-------|:------|:-----------------------------------------
1741  * [7:0] | RW | 0x0 | Clock Delay with n_ss_out
1742  * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit
1743  * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation
1744  * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert
1745  *
1746  */
1747 /*
1748  * Field : Clock Delay with n_ss_out - init
1749  *
1750  * Delay in master reference clocks between setting n_ss_out low and first bit
1751  * transfer.
1752  *
1753  * Field Access Macros:
1754  *
1755  */
1756 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */
1757 #define ALT_QSPI_DELAY_INIT_LSB 0
1758 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */
1759 #define ALT_QSPI_DELAY_INIT_MSB 7
1760 /* The width in bits of the ALT_QSPI_DELAY_INIT register field. */
1761 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1762 /* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */
1763 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1764 /* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */
1765 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1766 /* The reset value of the ALT_QSPI_DELAY_INIT register field. */
1767 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1768 /* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */
1769 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1770 /* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */
1771 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1772 
1773 /*
1774  * Field : Clock Delay for Last Transaction Bit - after
1775  *
1776  * Delay in master reference clocks between last bit of current transaction and
1777  * deasserting the device chip select (n_ss_out). By default, the chip select will
1778  * be deasserted on the cycle following the completion of the current transaction.
1779  *
1780  * Field Access Macros:
1781  *
1782  */
1783 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1784 #define ALT_QSPI_DELAY_AFTER_LSB 8
1785 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */
1786 #define ALT_QSPI_DELAY_AFTER_MSB 15
1787 /* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */
1788 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1789 /* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */
1790 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1791 /* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */
1792 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1793 /* The reset value of the ALT_QSPI_DELAY_AFTER register field. */
1794 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1795 /* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */
1796 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1797 /* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */
1798 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1799 
1800 /*
1801  * Field : Clock Delay for Chip Select Deactivation - btwn
1802  *
1803  * Delay in master reference clocks between one chip select being de-activated and
1804  * the activation of another. This is used to ensure a quiet period between the
1805  * selection of two different slaves and requires the transmit FIFO to be empty.
1806  *
1807  * Field Access Macros:
1808  *
1809  */
1810 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1811 #define ALT_QSPI_DELAY_BTWN_LSB 16
1812 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */
1813 #define ALT_QSPI_DELAY_BTWN_MSB 23
1814 /* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */
1815 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1816 /* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */
1817 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1818 /* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */
1819 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1820 /* The reset value of the ALT_QSPI_DELAY_BTWN register field. */
1821 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1822 /* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */
1823 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1824 /* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */
1825 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1826 
1827 /*
1828  * Field : Clock Delay for Chip Select Deassert - nss
1829  *
1830  * Delay in master reference clocks for the length that the master mode chip select
1831  * outputs are de-asserted between transactions. The minimum delay is always SCLK
1832  * period to ensure the chip select is never re-asserted within an SCLK period.
1833  *
1834  * Field Access Macros:
1835  *
1836  */
1837 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */
1838 #define ALT_QSPI_DELAY_NSS_LSB 24
1839 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */
1840 #define ALT_QSPI_DELAY_NSS_MSB 31
1841 /* The width in bits of the ALT_QSPI_DELAY_NSS register field. */
1842 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1843 /* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */
1844 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1845 /* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */
1846 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1847 /* The reset value of the ALT_QSPI_DELAY_NSS register field. */
1848 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1849 /* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */
1850 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1851 /* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */
1852 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1853 
1854 #ifndef __ASSEMBLY__
1855 /*
1856  * WARNING: The C register and register group struct declarations are provided for
1857  * convenience and illustrative purposes. They should, however, be used with
1858  * caution as the C language standard provides no guarantees about the alignment or
1859  * atomicity of device memory accesses. The recommended practice for coding device
1860  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1861  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1862  * alt_write_dword() functions for 64 bit registers.
1863  *
1864  * The struct declaration for register ALT_QSPI_DELAY.
1865  */
1866 struct ALT_QSPI_DELAY_s
1867 {
1868  volatile uint32_t init : 8; /* Clock Delay with n_ss_out */
1869  volatile uint32_t after : 8; /* Clock Delay for Last Transaction Bit */
1870  volatile uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */
1871  volatile uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */
1872 };
1873 
1874 /* The typedef declaration for register ALT_QSPI_DELAY. */
1875 typedef struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1876 #endif /* __ASSEMBLY__ */
1877 
1878 /* The reset value of the ALT_QSPI_DELAY register. */
1879 #define ALT_QSPI_DELAY_RESET 0x00000000
1880 /* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */
1881 #define ALT_QSPI_DELAY_OFST 0xc
1882 /* The address of the ALT_QSPI_DELAY register. */
1883 #define ALT_QSPI_DELAY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DELAY_OFST))
1884 
1885 /*
1886  * Register : Read Data Capture Register - rddatacap
1887  *
1888  * Register Layout
1889  *
1890  * Bits | Access | Reset | Description
1891  * :-------|:-------|:------|:------------
1892  * [0] | RW | 0x1 | Bypass
1893  * [4:1] | RW | 0x0 | Read Delay
1894  * [31:5] | R | 0x0 | Reserved
1895  *
1896  */
1897 /*
1898  * Field : Bypass - byp
1899  *
1900  * Bypass the adapted loopback clock circuit
1901  *
1902  * Field Enumeration Values:
1903  *
1904  * Enum | Value | Description
1905  * :----------------------------------|:------|:------------------------------
1906  * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x0 | Bypass loopback clock circuit
1907  * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x1 | No Bypass
1908  *
1909  * Field Access Macros:
1910  *
1911  */
1912 /*
1913  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1914  *
1915  * Bypass loopback clock circuit
1916  */
1917 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x0
1918 /*
1919  * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
1920  *
1921  * No Bypass
1922  */
1923 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x1
1924 
1925 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1926 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1927 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
1928 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1929 /* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */
1930 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1931 /* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */
1932 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1933 /* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */
1934 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1935 /* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */
1936 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1937 /* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */
1938 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1939 /* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */
1940 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1941 
1942 /*
1943  * Field : Read Delay - delay
1944  *
1945  * Delay the read data capturing logic by the programmed number of ref_clk cycles
1946  *
1947  * Field Access Macros:
1948  *
1949  */
1950 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1951 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1952 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
1953 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1954 /* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */
1955 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1956 /* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */
1957 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1958 /* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */
1959 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1960 /* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */
1961 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1962 /* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */
1963 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1964 /* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */
1965 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1966 
1967 /*
1968  * Field : Reserved - rd_data_resv_fld
1969  *
1970  * Field Access Macros:
1971  *
1972  */
1973 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1974 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_LSB 5
1975 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1976 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_MSB 31
1977 /* The width in bits of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1978 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_WIDTH 27
1979 /* The mask used to set the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value. */
1980 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET_MSK 0xffffffe0
1981 /* The mask used to clear the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value. */
1982 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_CLR_MSK 0x0000001f
1983 /* The reset value of the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field. */
1984 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_RESET 0x0
1985 /* Extracts the ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD field value from a register. */
1986 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_GET(value) (((value) & 0xffffffe0) >> 5)
1987 /* Produces a ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD register field value suitable for setting the register. */
1988 #define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET(value) (((value) << 5) & 0xffffffe0)
1989 
1990 #ifndef __ASSEMBLY__
1991 /*
1992  * WARNING: The C register and register group struct declarations are provided for
1993  * convenience and illustrative purposes. They should, however, be used with
1994  * caution as the C language standard provides no guarantees about the alignment or
1995  * atomicity of device memory accesses. The recommended practice for coding device
1996  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1997  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1998  * alt_write_dword() functions for 64 bit registers.
1999  *
2000  * The struct declaration for register ALT_QSPI_RDDATACAP.
2001  */
2002 struct ALT_QSPI_RDDATACAP_s
2003 {
2004  volatile uint32_t byp : 1; /* Bypass */
2005  volatile uint32_t delay : 4; /* Read Delay */
2006  const volatile uint32_t rd_data_resv_fld : 27; /* Reserved */
2007 };
2008 
2009 /* The typedef declaration for register ALT_QSPI_RDDATACAP. */
2010 typedef struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
2011 #endif /* __ASSEMBLY__ */
2012 
2013 /* The reset value of the ALT_QSPI_RDDATACAP register. */
2014 #define ALT_QSPI_RDDATACAP_RESET 0x00000001
2015 /* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */
2016 #define ALT_QSPI_RDDATACAP_OFST 0x10
2017 /* The address of the ALT_QSPI_RDDATACAP register. */
2018 #define ALT_QSPI_RDDATACAP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_RDDATACAP_OFST))
2019 
2020 /*
2021  * Register : Device Size Configuration Register - devsz
2022  *
2023  * Register Layout
2024  *
2025  * Bits | Access | Reset | Description
2026  * :--------|:-------|:------|:--------------------------------
2027  * [3:0] | RW | 0x2 | Number of address Bytes
2028  * [15:4] | RW | 0x100 | Number of Bytes per Device Page
2029  * [20:16] | RW | 0x10 | Number of Bytes per Block
2030  * [31:21] | R | 0x0 | Reserved
2031  *
2032  */
2033 /*
2034  * Field : Number of address Bytes - numaddrbytes
2035  *
2036  * Number of address bytes. A value of 0 indicates 1 byte.
2037  *
2038  * Field Access Macros:
2039  *
2040  */
2041 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2042 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
2043 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2044 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
2045 /* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2046 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
2047 /* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
2048 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
2049 /* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
2050 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
2051 /* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
2052 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
2053 /* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */
2054 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2055 /* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */
2056 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
2057 
2058 /*
2059  * Field : Number of Bytes per Device Page - bytesperdevicepage
2060  *
2061  * Number of bytes per device page. This is required by the controller for
2062  * performing FLASH writes up to and across page boundaries.
2063  *
2064  * Field Access Macros:
2065  *
2066  */
2067 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2068 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
2069 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2070 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
2071 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2072 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
2073 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
2074 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
2075 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
2076 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
2077 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
2078 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
2079 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */
2080 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
2081 /* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */
2082 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
2083 
2084 /*
2085  * Field : Number of Bytes per Block - bytespersubsector
2086  *
2087  * Number of bytes per Block. This is required by the controller for performing the
2088  * write protection logic. The number of bytes per block must be a power of 2
2089  * number.
2090  *
2091  * Field Access Macros:
2092  *
2093  */
2094 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2095 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
2096 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2097 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
2098 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2099 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
2100 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
2101 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
2102 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
2103 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
2104 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
2105 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
2106 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */
2107 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
2108 /* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */
2109 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
2110 
2111 /*
2112  * Field : Reserved - dev_size_resv_fld
2113  *
2114  * Field Access Macros:
2115  *
2116  */
2117 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2118 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_LSB 21
2119 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2120 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_MSB 31
2121 /* The width in bits of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2122 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_WIDTH 11
2123 /* The mask used to set the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value. */
2124 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET_MSK 0xffe00000
2125 /* The mask used to clear the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value. */
2126 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_CLR_MSK 0x001fffff
2127 /* The reset value of the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field. */
2128 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_RESET 0x0
2129 /* Extracts the ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD field value from a register. */
2130 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_GET(value) (((value) & 0xffe00000) >> 21)
2131 /* Produces a ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD register field value suitable for setting the register. */
2132 #define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET(value) (((value) << 21) & 0xffe00000)
2133 
2134 #ifndef __ASSEMBLY__
2135 /*
2136  * WARNING: The C register and register group struct declarations are provided for
2137  * convenience and illustrative purposes. They should, however, be used with
2138  * caution as the C language standard provides no guarantees about the alignment or
2139  * atomicity of device memory accesses. The recommended practice for coding device
2140  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2141  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2142  * alt_write_dword() functions for 64 bit registers.
2143  *
2144  * The struct declaration for register ALT_QSPI_DEVSZ.
2145  */
2146 struct ALT_QSPI_DEVSZ_s
2147 {
2148  volatile uint32_t numaddrbytes : 4; /* Number of address Bytes */
2149  volatile uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */
2150  volatile uint32_t bytespersubsector : 5; /* Number of Bytes per Block */
2151  const volatile uint32_t dev_size_resv_fld : 11; /* Reserved */
2152 };
2153 
2154 /* The typedef declaration for register ALT_QSPI_DEVSZ. */
2155 typedef struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
2156 #endif /* __ASSEMBLY__ */
2157 
2158 /* The reset value of the ALT_QSPI_DEVSZ register. */
2159 #define ALT_QSPI_DEVSZ_RESET 0x00101002
2160 /* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */
2161 #define ALT_QSPI_DEVSZ_OFST 0x14
2162 /* The address of the ALT_QSPI_DEVSZ register. */
2163 #define ALT_QSPI_DEVSZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DEVSZ_OFST))
2164 
2165 /*
2166  * Register : SRAM Partition Configuration Register - srampart
2167  *
2168  * Register Layout
2169  *
2170  * Bits | Access | Reset | Description
2171  * :--------|:-------|:------|:-----------------------------
2172  * [9:0] | RW | 0x80 | Indirect Read Partition Size
2173  * [31:10] | R | 0x0 | Reserved
2174  *
2175  */
2176 /*
2177  * Field : Indirect Read Partition Size - addr
2178  *
2179  * Defines the size of the indirect read partition in the SRAM, in units of SRAM
2180  * locations. By default, half of the SRAM is reserved for indirect read operation,
2181  * and half for indirect write. The size of this register will scale with the depth
2182  * of the SRAM.
2183  *
2184  * Field Access Macros:
2185  *
2186  */
2187 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
2188 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
2189 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
2190 #define ALT_QSPI_SRAMPART_ADDR_MSB 9
2191 /* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */
2192 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 10
2193 /* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */
2194 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x000003ff
2195 /* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */
2196 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xfffffc00
2197 /* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */
2198 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x80
2199 /* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */
2200 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2201 /* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */
2202 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2203 
2204 /*
2205  * Field : Reserved - resv_fld
2206  *
2207  * Field Access Macros:
2208  *
2209  */
2210 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2211 #define ALT_QSPI_SRAMPART_RESV_FLD_LSB 10
2212 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2213 #define ALT_QSPI_SRAMPART_RESV_FLD_MSB 31
2214 /* The width in bits of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2215 #define ALT_QSPI_SRAMPART_RESV_FLD_WIDTH 22
2216 /* The mask used to set the ALT_QSPI_SRAMPART_RESV_FLD register field value. */
2217 #define ALT_QSPI_SRAMPART_RESV_FLD_SET_MSK 0xfffffc00
2218 /* The mask used to clear the ALT_QSPI_SRAMPART_RESV_FLD register field value. */
2219 #define ALT_QSPI_SRAMPART_RESV_FLD_CLR_MSK 0x000003ff
2220 /* The reset value of the ALT_QSPI_SRAMPART_RESV_FLD register field. */
2221 #define ALT_QSPI_SRAMPART_RESV_FLD_RESET 0x0
2222 /* Extracts the ALT_QSPI_SRAMPART_RESV_FLD field value from a register. */
2223 #define ALT_QSPI_SRAMPART_RESV_FLD_GET(value) (((value) & 0xfffffc00) >> 10)
2224 /* Produces a ALT_QSPI_SRAMPART_RESV_FLD register field value suitable for setting the register. */
2225 #define ALT_QSPI_SRAMPART_RESV_FLD_SET(value) (((value) << 10) & 0xfffffc00)
2226 
2227 #ifndef __ASSEMBLY__
2228 /*
2229  * WARNING: The C register and register group struct declarations are provided for
2230  * convenience and illustrative purposes. They should, however, be used with
2231  * caution as the C language standard provides no guarantees about the alignment or
2232  * atomicity of device memory accesses. The recommended practice for coding device
2233  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2234  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2235  * alt_write_dword() functions for 64 bit registers.
2236  *
2237  * The struct declaration for register ALT_QSPI_SRAMPART.
2238  */
2239 struct ALT_QSPI_SRAMPART_s
2240 {
2241  volatile uint32_t addr : 10; /* Indirect Read Partition Size */
2242  const volatile uint32_t resv_fld : 22; /* Reserved */
2243 };
2244 
2245 /* The typedef declaration for register ALT_QSPI_SRAMPART. */
2246 typedef struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
2247 #endif /* __ASSEMBLY__ */
2248 
2249 /* The reset value of the ALT_QSPI_SRAMPART register. */
2250 #define ALT_QSPI_SRAMPART_RESET 0x00000080
2251 /* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */
2252 #define ALT_QSPI_SRAMPART_OFST 0x18
2253 /* The address of the ALT_QSPI_SRAMPART register. */
2254 #define ALT_QSPI_SRAMPART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_SRAMPART_OFST))
2255 
2256 /*
2257  * Register : Indirect AHB Address Trigger Register - indaddrtrig
2258  *
2259  * Register Layout
2260  *
2261  * Bits | Access | Reset | Description
2262  * :-------|:-------|:------|:----------------
2263  * [31:0] | RW | 0x0 | Trigger Address
2264  *
2265  */
2266 /*
2267  * Field : Trigger Address - addr
2268  *
2269  * This is the base address that will be used by the AHB controller. When the
2270  * incoming AHB read access address matches a range of addresses from this trigger
2271  * address to the trigger address + 15, then the AHB request will be completed by
2272  * fetching data from the Indirect Controllers SRAM.
2273  *
2274  * Field Access Macros:
2275  *
2276  */
2277 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2278 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
2279 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2280 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
2281 /* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2282 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
2283 /* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
2284 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
2285 /* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
2286 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
2287 /* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
2288 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
2289 /* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */
2290 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2291 /* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */
2292 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2293 
2294 #ifndef __ASSEMBLY__
2295 /*
2296  * WARNING: The C register and register group struct declarations are provided for
2297  * convenience and illustrative purposes. They should, however, be used with
2298  * caution as the C language standard provides no guarantees about the alignment or
2299  * atomicity of device memory accesses. The recommended practice for coding device
2300  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2301  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2302  * alt_write_dword() functions for 64 bit registers.
2303  *
2304  * The struct declaration for register ALT_QSPI_INDADDRTRIG.
2305  */
2306 struct ALT_QSPI_INDADDRTRIG_s
2307 {
2308  volatile uint32_t addr : 32; /* Trigger Address */
2309 };
2310 
2311 /* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */
2312 typedef struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
2313 #endif /* __ASSEMBLY__ */
2314 
2315 /* The reset value of the ALT_QSPI_INDADDRTRIG register. */
2316 #define ALT_QSPI_INDADDRTRIG_RESET 0x00000000
2317 /* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */
2318 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
2319 /* The address of the ALT_QSPI_INDADDRTRIG register. */
2320 #define ALT_QSPI_INDADDRTRIG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDADDRTRIG_OFST))
2321 
2322 /*
2323  * Register : DMA Peripheral Configuration Register - dmaper
2324  *
2325  * Register Layout
2326  *
2327  * Bits | Access | Reset | Description
2328  * :--------|:-------|:------|:-----------------------
2329  * [3:0] | RW | 0x0 | Number of Single Bytes
2330  * [7:4] | R | 0x0 | Reserved
2331  * [11:8] | RW | 0x0 | Number of Burst Bytes
2332  * [31:12] | R | 0x0 | Reserved
2333  *
2334  */
2335 /*
2336  * Field : Number of Single Bytes - numsglreqbytes
2337  *
2338  * Number of bytes in a single type request on the DMA peripheral request. A
2339  * programmed value of 0 represents a single byte. This should be setup before
2340  * starting the indirect read or write operation. The actual number of bytes used
2341  * is 2**(value in this register) which will simplify implementation.
2342  *
2343  * Field Access Macros:
2344  *
2345  */
2346 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2347 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
2348 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2349 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
2350 /* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2351 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
2352 /* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
2353 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
2354 /* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
2355 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
2356 /* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
2357 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
2358 /* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */
2359 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2360 /* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */
2361 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
2362 
2363 /*
2364  * Field : Reserved - dma_periph_resv1_fld
2365  *
2366  * Field Access Macros:
2367  *
2368  */
2369 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2370 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_LSB 4
2371 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2372 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_MSB 7
2373 /* The width in bits of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2374 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_WIDTH 4
2375 /* The mask used to set the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value. */
2376 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET_MSK 0x000000f0
2377 /* The mask used to clear the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value. */
2378 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_CLR_MSK 0xffffff0f
2379 /* The reset value of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field. */
2380 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_RESET 0x0
2381 /* Extracts the ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD field value from a register. */
2382 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_GET(value) (((value) & 0x000000f0) >> 4)
2383 /* Produces a ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD register field value suitable for setting the register. */
2384 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET(value) (((value) << 4) & 0x000000f0)
2385 
2386 /*
2387  * Field : Number of Burst Bytes - numburstreqbytes
2388  *
2389  * Number of bytes in a burst type request on the DMA peripheral request. A
2390  * programmed value of 0 represents a single byte. This should be setup before
2391  * starting the indirect read or write operation. The actual number of bytes used
2392  * is 2**(value in this register) which will simplify implementation.
2393  *
2394  * Field Access Macros:
2395  *
2396  */
2397 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2398 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2399 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2400 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2401 /* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2402 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2403 /* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2404 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2405 /* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
2406 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2407 /* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
2408 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2409 /* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */
2410 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2411 /* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */
2412 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2413 
2414 /*
2415  * Field : Reserved - dma_periph_resv2_fld
2416  *
2417  * Field Access Macros:
2418  *
2419  */
2420 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2421 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_LSB 12
2422 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2423 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_MSB 31
2424 /* The width in bits of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2425 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_WIDTH 20
2426 /* The mask used to set the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value. */
2427 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET_MSK 0xfffff000
2428 /* The mask used to clear the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value. */
2429 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_CLR_MSK 0x00000fff
2430 /* The reset value of the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field. */
2431 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_RESET 0x0
2432 /* Extracts the ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD field value from a register. */
2433 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_GET(value) (((value) & 0xfffff000) >> 12)
2434 /* Produces a ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD register field value suitable for setting the register. */
2435 #define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET(value) (((value) << 12) & 0xfffff000)
2436 
2437 #ifndef __ASSEMBLY__
2438 /*
2439  * WARNING: The C register and register group struct declarations are provided for
2440  * convenience and illustrative purposes. They should, however, be used with
2441  * caution as the C language standard provides no guarantees about the alignment or
2442  * atomicity of device memory accesses. The recommended practice for coding device
2443  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2444  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2445  * alt_write_dword() functions for 64 bit registers.
2446  *
2447  * The struct declaration for register ALT_QSPI_DMAPER.
2448  */
2449 struct ALT_QSPI_DMAPER_s
2450 {
2451  volatile uint32_t numsglreqbytes : 4; /* Number of Single Bytes */
2452  const volatile uint32_t dma_periph_resv1_fld : 4; /* Reserved */
2453  volatile uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */
2454  const volatile uint32_t dma_periph_resv2_fld : 20; /* Reserved */
2455 };
2456 
2457 /* The typedef declaration for register ALT_QSPI_DMAPER. */
2458 typedef struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2459 #endif /* __ASSEMBLY__ */
2460 
2461 /* The reset value of the ALT_QSPI_DMAPER register. */
2462 #define ALT_QSPI_DMAPER_RESET 0x00000000
2463 /* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */
2464 #define ALT_QSPI_DMAPER_OFST 0x20
2465 /* The address of the ALT_QSPI_DMAPER register. */
2466 #define ALT_QSPI_DMAPER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_DMAPER_OFST))
2467 
2468 /*
2469  * Register : Remap Address Register - remapaddr
2470  *
2471  * Register Layout
2472  *
2473  * Bits | Access | Reset | Description
2474  * :-------|:-------|:------|:-----------------------
2475  * [31:0] | RW | 0x0 | Remap Address Register
2476  *
2477  */
2478 /*
2479  * Field : Remap Address Register - value
2480  *
2481  * This register is used to remap an incoming AHB address to a different address
2482  * used by the FLASH device.
2483  *
2484  * Field Access Macros:
2485  *
2486  */
2487 /* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2488 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2489 /* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
2490 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2491 /* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */
2492 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2493 /* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */
2494 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2495 /* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */
2496 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2497 /* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */
2498 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2499 /* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */
2500 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2501 /* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */
2502 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2503 
2504 #ifndef __ASSEMBLY__
2505 /*
2506  * WARNING: The C register and register group struct declarations are provided for
2507  * convenience and illustrative purposes. They should, however, be used with
2508  * caution as the C language standard provides no guarantees about the alignment or
2509  * atomicity of device memory accesses. The recommended practice for coding device
2510  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2511  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2512  * alt_write_dword() functions for 64 bit registers.
2513  *
2514  * The struct declaration for register ALT_QSPI_REMAPADDR.
2515  */
2516 struct ALT_QSPI_REMAPADDR_s
2517 {
2518  volatile uint32_t value : 32; /* Remap Address Register */
2519 };
2520 
2521 /* The typedef declaration for register ALT_QSPI_REMAPADDR. */
2522 typedef struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
2523 #endif /* __ASSEMBLY__ */
2524 
2525 /* The reset value of the ALT_QSPI_REMAPADDR register. */
2526 #define ALT_QSPI_REMAPADDR_RESET 0x00000000
2527 /* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */
2528 #define ALT_QSPI_REMAPADDR_OFST 0x24
2529 /* The address of the ALT_QSPI_REMAPADDR register. */
2530 #define ALT_QSPI_REMAPADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_REMAPADDR_OFST))
2531 
2532 /*
2533  * Register : Mode Bit Configuration Register - modebit
2534  *
2535  * Register Layout
2536  *
2537  * Bits | Access | Reset | Description
2538  * :-------|:-------|:------|:------------
2539  * [7:0] | RW | 0x0 | Mode
2540  * [31:8] | R | 0x0 | Reserved
2541  *
2542  */
2543 /*
2544  * Field : Mode - mode
2545  *
2546  * These are the 8 mode bits that are sent to the device following the address
2547  * bytes if mode bit transmission has been enabled.
2548  *
2549  * Field Access Macros:
2550  *
2551  */
2552 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODEBIT_MODE register field. */
2553 #define ALT_QSPI_MODEBIT_MODE_LSB 0
2554 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODEBIT_MODE register field. */
2555 #define ALT_QSPI_MODEBIT_MODE_MSB 7
2556 /* The width in bits of the ALT_QSPI_MODEBIT_MODE register field. */
2557 #define ALT_QSPI_MODEBIT_MODE_WIDTH 8
2558 /* The mask used to set the ALT_QSPI_MODEBIT_MODE register field value. */
2559 #define ALT_QSPI_MODEBIT_MODE_SET_MSK 0x000000ff
2560 /* The mask used to clear the ALT_QSPI_MODEBIT_MODE register field value. */
2561 #define ALT_QSPI_MODEBIT_MODE_CLR_MSK 0xffffff00
2562 /* The reset value of the ALT_QSPI_MODEBIT_MODE register field. */
2563 #define ALT_QSPI_MODEBIT_MODE_RESET 0x0
2564 /* Extracts the ALT_QSPI_MODEBIT_MODE field value from a register. */
2565 #define ALT_QSPI_MODEBIT_MODE_GET(value) (((value) & 0x000000ff) >> 0)
2566 /* Produces a ALT_QSPI_MODEBIT_MODE register field value suitable for setting the register. */
2567 #define ALT_QSPI_MODEBIT_MODE_SET(value) (((value) << 0) & 0x000000ff)
2568 
2569 /*
2570  * Field : Reserved - mode_resv_fld
2571  *
2572  * Field Access Macros:
2573  *
2574  */
2575 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field. */
2576 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_LSB 8
2577 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field. */
2578 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_MSB 31
2579 /* The width in bits of the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field. */
2580 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_WIDTH 24
2581 /* The mask used to set the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field value. */
2582 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_SET_MSK 0xffffff00
2583 /* The mask used to clear the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field value. */
2584 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_CLR_MSK 0x000000ff
2585 /* The reset value of the ALT_QSPI_MODEBIT_MODE_RESV_FLD register field. */
2586 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_RESET 0x0
2587 /* Extracts the ALT_QSPI_MODEBIT_MODE_RESV_FLD field value from a register. */
2588 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2589 /* Produces a ALT_QSPI_MODEBIT_MODE_RESV_FLD register field value suitable for setting the register. */
2590 #define ALT_QSPI_MODEBIT_MODE_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2591 
2592 #ifndef __ASSEMBLY__
2593 /*
2594  * WARNING: The C register and register group struct declarations are provided for
2595  * convenience and illustrative purposes. They should, however, be used with
2596  * caution as the C language standard provides no guarantees about the alignment or
2597  * atomicity of device memory accesses. The recommended practice for coding device
2598  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2599  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2600  * alt_write_dword() functions for 64 bit registers.
2601  *
2602  * The struct declaration for register ALT_QSPI_MODEBIT.
2603  */
2604 struct ALT_QSPI_MODEBIT_s
2605 {
2606  volatile uint32_t mode : 8; /* Mode */
2607  const volatile uint32_t mode_resv_fld : 24; /* Reserved */
2608 };
2609 
2610 /* The typedef declaration for register ALT_QSPI_MODEBIT. */
2611 typedef struct ALT_QSPI_MODEBIT_s ALT_QSPI_MODEBIT_t;
2612 #endif /* __ASSEMBLY__ */
2613 
2614 /* The reset value of the ALT_QSPI_MODEBIT register. */
2615 #define ALT_QSPI_MODEBIT_RESET 0x00000000
2616 /* The byte offset of the ALT_QSPI_MODEBIT register from the beginning of the component. */
2617 #define ALT_QSPI_MODEBIT_OFST 0x28
2618 /* The address of the ALT_QSPI_MODEBIT register. */
2619 #define ALT_QSPI_MODEBIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_MODEBIT_OFST))
2620 
2621 /*
2622  * Register : SRAM Fill Register - sramfill
2623  *
2624  * Register Layout
2625  *
2626  * Bits | Access | Reset | Description
2627  * :--------|:-------|:------|:-------------------------------------------
2628  * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition)
2629  * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition)
2630  *
2631  */
2632 /*
2633  * Field : SRAM Fill Level (Indirect Read Partition) - indrdpart
2634  *
2635  * Identifies the current fill level of the SRAM Indirect Read partition
2636  *
2637  * Field Access Macros:
2638  *
2639  */
2640 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2641 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2642 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2643 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2644 /* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2645 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2646 /* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2647 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2648 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
2649 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2650 /* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
2651 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2652 /* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */
2653 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2654 /* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */
2655 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2656 
2657 /*
2658  * Field : SRAM Fill Level (Indirect Write Partition) - indwrpart
2659  *
2660  * Identifies the current fill level of the SRAM Indirect Write partition
2661  *
2662  * Field Access Macros:
2663  *
2664  */
2665 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2666 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2667 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2668 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2669 /* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2670 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2671 /* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2672 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2673 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
2674 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2675 /* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
2676 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2677 /* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */
2678 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2679 /* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */
2680 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2681 
2682 #ifndef __ASSEMBLY__
2683 /*
2684  * WARNING: The C register and register group struct declarations are provided for
2685  * convenience and illustrative purposes. They should, however, be used with
2686  * caution as the C language standard provides no guarantees about the alignment or
2687  * atomicity of device memory accesses. The recommended practice for coding device
2688  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2689  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2690  * alt_write_dword() functions for 64 bit registers.
2691  *
2692  * The struct declaration for register ALT_QSPI_SRAMFILL.
2693  */
2694 struct ALT_QSPI_SRAMFILL_s
2695 {
2696  const volatile uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition) */
2697  const volatile uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition) */
2698 };
2699 
2700 /* The typedef declaration for register ALT_QSPI_SRAMFILL. */
2701 typedef struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
2702 #endif /* __ASSEMBLY__ */
2703 
2704 /* The reset value of the ALT_QSPI_SRAMFILL register. */
2705 #define ALT_QSPI_SRAMFILL_RESET 0x00000000
2706 /* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */
2707 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2708 /* The address of the ALT_QSPI_SRAMFILL register. */
2709 #define ALT_QSPI_SRAMFILL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_SRAMFILL_OFST))
2710 
2711 /*
2712  * Register : TX Threshold Register - txthresh
2713  *
2714  * Register Layout
2715  *
2716  * Bits | Access | Reset | Description
2717  * :-------|:-------|:------|:------------
2718  * [3:0] | RW | 0x1 | Level
2719  * [31:4] | R | 0x0 | Reserved
2720  *
2721  */
2722 /*
2723  * Field : Level - level
2724  *
2725  * Defines the level at which the small TX FIFO not full interrupt is generated
2726  *
2727  * Field Access Macros:
2728  *
2729  */
2730 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2731 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2732 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2733 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2734 /* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2735 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2736 /* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2737 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2738 /* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */
2739 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2740 /* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */
2741 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2742 /* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */
2743 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2744 /* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */
2745 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2746 
2747 /*
2748  * Field : Reserved - tx_thresh_resv_fld
2749  *
2750  * Field Access Macros:
2751  *
2752  */
2753 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2754 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_LSB 4
2755 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2756 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_MSB 31
2757 /* The width in bits of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2758 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_WIDTH 28
2759 /* The mask used to set the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value. */
2760 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2761 /* The mask used to clear the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value. */
2762 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2763 /* The reset value of the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field. */
2764 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_RESET 0x0
2765 /* Extracts the ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD field value from a register. */
2766 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2767 /* Produces a ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD register field value suitable for setting the register. */
2768 #define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2769 
2770 #ifndef __ASSEMBLY__
2771 /*
2772  * WARNING: The C register and register group struct declarations are provided for
2773  * convenience and illustrative purposes. They should, however, be used with
2774  * caution as the C language standard provides no guarantees about the alignment or
2775  * atomicity of device memory accesses. The recommended practice for coding device
2776  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2777  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2778  * alt_write_dword() functions for 64 bit registers.
2779  *
2780  * The struct declaration for register ALT_QSPI_TXTHRESH.
2781  */
2782 struct ALT_QSPI_TXTHRESH_s
2783 {
2784  volatile uint32_t level : 4; /* Level */
2785  const volatile uint32_t tx_thresh_resv_fld : 28; /* Reserved */
2786 };
2787 
2788 /* The typedef declaration for register ALT_QSPI_TXTHRESH. */
2789 typedef struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
2790 #endif /* __ASSEMBLY__ */
2791 
2792 /* The reset value of the ALT_QSPI_TXTHRESH register. */
2793 #define ALT_QSPI_TXTHRESH_RESET 0x00000001
2794 /* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */
2795 #define ALT_QSPI_TXTHRESH_OFST 0x30
2796 /* The address of the ALT_QSPI_TXTHRESH register. */
2797 #define ALT_QSPI_TXTHRESH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_TXTHRESH_OFST))
2798 
2799 /*
2800  * Register : RX Threshold Register - rxthresh
2801  *
2802  * Device Instruction Configuration Register
2803  *
2804  * Register Layout
2805  *
2806  * Bits | Access | Reset | Description
2807  * :-------|:-------|:------|:------------
2808  * [3:0] | RW | 0x1 | Level
2809  * [31:4] | R | 0x0 | Reserved
2810  *
2811  */
2812 /*
2813  * Field : Level - level
2814  *
2815  * Defines the level at which the small RX FIFO not empty interrupt is generated
2816  *
2817  * Field Access Macros:
2818  *
2819  */
2820 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2821 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2822 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2823 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2824 /* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2825 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2826 /* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2827 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2828 /* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */
2829 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2830 /* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */
2831 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2832 /* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */
2833 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2834 /* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */
2835 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2836 
2837 /*
2838  * Field : Reserved - rx_thresh_resv_fld
2839  *
2840  * Field Access Macros:
2841  *
2842  */
2843 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2844 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_LSB 4
2845 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2846 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_MSB 31
2847 /* The width in bits of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2848 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_WIDTH 28
2849 /* The mask used to set the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value. */
2850 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2851 /* The mask used to clear the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value. */
2852 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2853 /* The reset value of the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field. */
2854 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_RESET 0x0
2855 /* Extracts the ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD field value from a register. */
2856 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2857 /* Produces a ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD register field value suitable for setting the register. */
2858 #define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2859 
2860 #ifndef __ASSEMBLY__
2861 /*
2862  * WARNING: The C register and register group struct declarations are provided for
2863  * convenience and illustrative purposes. They should, however, be used with
2864  * caution as the C language standard provides no guarantees about the alignment or
2865  * atomicity of device memory accesses. The recommended practice for coding device
2866  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2867  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2868  * alt_write_dword() functions for 64 bit registers.
2869  *
2870  * The struct declaration for register ALT_QSPI_RXTHRESH.
2871  */
2872 struct ALT_QSPI_RXTHRESH_s
2873 {
2874  volatile uint32_t level : 4; /* Level */
2875  const volatile uint32_t rx_thresh_resv_fld : 28; /* Reserved */
2876 };
2877 
2878 /* The typedef declaration for register ALT_QSPI_RXTHRESH. */
2879 typedef struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
2880 #endif /* __ASSEMBLY__ */
2881 
2882 /* The reset value of the ALT_QSPI_RXTHRESH register. */
2883 #define ALT_QSPI_RXTHRESH_RESET 0x00000001
2884 /* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */
2885 #define ALT_QSPI_RXTHRESH_OFST 0x34
2886 /* The address of the ALT_QSPI_RXTHRESH register. */
2887 #define ALT_QSPI_RXTHRESH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_RXTHRESH_OFST))
2888 
2889 /*
2890  * Register : Interrupt Status Register - irqstat
2891  *
2892  * The status fields in this register are set when the described event occurs and
2893  * the interrupt is enabled in the mask register. When any of these bit fields are
2894  * set, the interrupt output is asserted high. The fields are each cleared by
2895  * writing a 1 to the field. Note that bit fields 6 thru 10 are only valid when
2896  * legacy SPI mode is active.
2897  *
2898  * Register Layout
2899  *
2900  * Bits | Access | Reset | Description
2901  * :--------|:-------|:------|:---------------------------------
2902  * [0] | RW | 0x0 | Mode M Failure
2903  * [1] | RW | 0x0 | Underflow Detected
2904  * [2] | RW | 0x0 | Indirect Operation Complete
2905  * [3] | RW | 0x0 | Indirect Read Reject
2906  * [4] | RW | 0x0 | Protected Area Write Attempt
2907  * [5] | RW | 0x0 | Illegal AHB Access Detected
2908  * [6] | RW | 0x0 | Transfer Watermark Breach
2909  * [7] | RW | 0x0 | Receive Overflow
2910  * [8] | RW | 0x1 | Small TX FIFO not full
2911  * [9] | RW | 0x0 | Small TX FIFO full
2912  * [10] | RW | 0x0 | Small RX FIFO not empty
2913  * [11] | RW | 0x0 | Small RX FIFO full
2914  * [12] | RW | 0x0 | Indirect Read Partition overflow
2915  * [31:13] | R | 0x0 | Reserved
2916  *
2917  */
2918 /*
2919  * Field : Mode M Failure - mode_m_fail_fld
2920  *
2921  * Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI
2922  * mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These
2923  * conditions will clear the spi_enable bit and disable the SPI. This bit is reset
2924  * only by a system reset and cleared only when this register is read. 0 : no mode
2925  * fault has been detected 1 : a mode fault has occurred
2926  *
2927  * Field Access Macros:
2928  *
2929  */
2930 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field. */
2931 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_LSB 0
2932 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field. */
2933 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_MSB 0
2934 /* The width in bits of the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field. */
2935 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_WIDTH 1
2936 /* The mask used to set the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field value. */
2937 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_SET_MSK 0x00000001
2938 /* The mask used to clear the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field value. */
2939 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_CLR_MSK 0xfffffffe
2940 /* The reset value of the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field. */
2941 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_RESET 0x0
2942 /* Extracts the ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD field value from a register. */
2943 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_GET(value) (((value) & 0x00000001) >> 0)
2944 /* Produces a ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD register field value suitable for setting the register. */
2945 #define ALT_QSPI_IRQSTAT_MODE_M_FAIL_FLD_SET(value) (((value) << 0) & 0x00000001)
2946 
2947 /*
2948  * Field : Underflow Detected - underflowdet
2949  *
2950  * 0 : no underflow has been detected 1 : underflow is detected and an attempt to
2951  * transfer data is made when the small TX FIFO is empty. This may occur when AHB
2952  * write data is being supplied too slowly to keep up with the requested write
2953  * operation This bit is reset only by a system reset and cleared only when the
2954  * register is read.
2955  *
2956  * Field Enumeration Values:
2957  *
2958  * Enum | Value | Description
2959  * :--------------------------------------------|:------|:-------------
2960  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow
2961  * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow
2962  *
2963  * Field Access Macros:
2964  *
2965  */
2966 /*
2967  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2968  *
2969  * No Underflow
2970  */
2971 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2972 /*
2973  * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
2974  *
2975  * Underflow
2976  */
2977 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2978 
2979 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2980 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2981 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2982 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2983 /* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2984 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2985 /* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2986 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2987 /* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
2988 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2989 /* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
2990 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2991 /* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */
2992 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2993 /* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */
2994 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2995 
2996 /*
2997  * Field : Indirect Operation Complete - indopdone
2998  *
2999  * Controller has completed last triggered indirect operation
3000  *
3001  * Field Enumeration Values:
3002  *
3003  * Enum | Value | Description
3004  * :------------------------------------------|:------|:-----------------------------
3005  * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation
3006  * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation
3007  *
3008  * Field Access Macros:
3009  *
3010  */
3011 /*
3012  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
3013  *
3014  * No Indirect Operation
3015  */
3016 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
3017 /*
3018  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
3019  *
3020  * Completed Indirect Operation
3021  */
3022 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
3023 
3024 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
3025 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
3026 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
3027 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
3028 /* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
3029 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
3030 /* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
3031 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
3032 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
3033 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
3034 /* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
3035 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
3036 /* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */
3037 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3038 /* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */
3039 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3040 
3041 /*
3042  * Field : Indirect Read Reject - indrdreject
3043  *
3044  * Indirect operation was requested but could not be accepted. Two indirect
3045  * operations already in storage.
3046  *
3047  * Field Enumeration Values:
3048  *
3049  * Enum | Value | Description
3050  * :---------------------------------------------|:------|:-----------------------------
3051  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation
3052  * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested
3053  *
3054  * Field Access Macros:
3055  *
3056  */
3057 /*
3058  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
3059  *
3060  * No Indirect Operation
3061  */
3062 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
3063 /*
3064  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
3065  *
3066  * Indirect Operation Requested
3067  */
3068 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
3069 
3070 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3071 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
3072 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3073 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
3074 /* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3075 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
3076 /* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
3077 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
3078 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
3079 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
3080 /* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
3081 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
3082 /* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */
3083 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3084 /* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */
3085 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3086 
3087 /*
3088  * Field : Protected Area Write Attempt - protwrattempt
3089  *
3090  * Write to protected area was attempted and rejected.
3091  *
3092  * Field Enumeration Values:
3093  *
3094  * Enum | Value | Description
3095  * :---------------------------------------------|:------|:--------------------------------
3096  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRITEPROT | 0x0 | No Write Attempt
3097  * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRITEPROT | 0x1 | Write Attempt to protected area
3098  *
3099  * Field Access Macros:
3100  *
3101  */
3102 /*
3103  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
3104  *
3105  * No Write Attempt
3106  */
3107 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRITEPROT 0x0
3108 /*
3109  * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
3110  *
3111  * Write Attempt to protected area
3112  */
3113 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRITEPROT 0x1
3114 
3115 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3116 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
3117 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3118 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
3119 /* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3120 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
3121 /* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
3122 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
3123 /* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
3124 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
3125 /* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
3126 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
3127 /* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */
3128 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3129 /* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */
3130 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3131 
3132 /*
3133  * Field : Illegal AHB Access Detected - illegalacc
3134  *
3135  * Illegal AHB access has been detected. AHB wrapping bursts and the use of
3136  * SPLIT/RETRY accesses will cause this error interrupt to trigger.
3137  *
3138  * Field Enumeration Values:
3139  *
3140  * Enum | Value | Description
3141  * :-------------------------------------------|:------|:-----------------------
3142  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt
3143  * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt
3144  *
3145  * Field Access Macros:
3146  *
3147  */
3148 /*
3149  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
3150  *
3151  * No Illegal AHB attempt
3152  */
3153 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
3154 /*
3155  * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
3156  *
3157  * Illegal AHB attempt
3158  */
3159 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
3160 
3161 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3162 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
3163 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3164 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
3165 /* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3166 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
3167 /* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
3168 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
3169 /* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
3170 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
3171 /* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
3172 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
3173 /* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */
3174 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3175 /* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */
3176 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3177 
3178 /*
3179  * Field : Transfer Watermark Breach - indxfrlvl
3180  *
3181  * Indirect Transfer Watermark Level Breached
3182  *
3183  * Field Enumeration Values:
3184  *
3185  * Enum | Value | Description
3186  * :----------------------------------------|:------|:-----------------------
3187  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached
3188  * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached
3189  *
3190  * Field Access Macros:
3191  *
3192  */
3193 /*
3194  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
3195  *
3196  * No water level reached
3197  */
3198 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
3199 /*
3200  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
3201  *
3202  * Water level reached
3203  */
3204 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
3205 
3206 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3207 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
3208 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3209 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
3210 /* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3211 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
3212 /* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
3213 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
3214 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
3215 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
3216 /* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
3217 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
3218 /* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */
3219 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3220 /* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */
3221 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3222 
3223 /*
3224  * Field : Receive Overflow - rxover
3225  *
3226  * This should only occur in Legacy SPI mode. Set if an attempt is made to push the
3227  * RX FIFO when it is full. This bit is reset only by a system reset and cleared
3228  * only when this register is read. If a new push to the RX FIFO occurs coincident
3229  * with a register read this flag will remain set. 0 : no overflow has been
3230  * detected. 1 : an overflow has occurred.
3231  *
3232  * Field Enumeration Values:
3233  *
3234  * Enum | Value | Description
3235  * :------------------------------------|:------|:--------------------
3236  * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow
3237  * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow
3238  *
3239  * Field Access Macros:
3240  *
3241  */
3242 /*
3243  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
3244  *
3245  * No Receive Overflow
3246  */
3247 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
3248 /*
3249  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
3250  *
3251  * Receive Overflow
3252  */
3253 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
3254 
3255 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3256 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
3257 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3258 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
3259 /* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3260 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
3261 /* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */
3262 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
3263 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */
3264 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
3265 /* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */
3266 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
3267 /* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */
3268 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3269 /* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */
3270 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3271 
3272 /*
3273  * Field : Small TX FIFO not full - txthreshcmp
3274  *
3275  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >=
3276  * THRESHOLD entries, 1 : FIFO has less than THRESHOLD entries
3277  *
3278  * Field Enumeration Values:
3279  *
3280  * Enum | Value | Description
3281  * :----------------------------------|:------|:-----------------------------
3282  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries
3283  * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries
3284  *
3285  * Field Access Macros:
3286  *
3287  */
3288 /*
3289  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
3290  *
3291  * FIFO has > TXTHRESH entries
3292  */
3293 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
3294 /*
3295  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
3296  *
3297  * FIFO has <= TXTHRESH entries
3298  */
3299 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
3300 
3301 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3302 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
3303 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3304 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
3305 /* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3306 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
3307 /* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
3308 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
3309 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
3310 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
3311 /* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
3312 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
3313 /* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */
3314 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3315 /* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */
3316 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3317 
3318 /*
3319  * Field : Small TX FIFO full - txfull
3320  *
3321  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full,
3322  * 1 : FIFO is full
3323  *
3324  * Field Enumeration Values:
3325  *
3326  * Enum | Value | Description
3327  * :----------------------------------|:------|:-----------------------
3328  * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full
3329  * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full
3330  *
3331  * Field Access Macros:
3332  *
3333  */
3334 /*
3335  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
3336  *
3337  * Transmit FIFO Not Full
3338  */
3339 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
3340 /*
3341  * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
3342  *
3343  * Transmit FIFO Full
3344  */
3345 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
3346 
3347 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3348 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
3349 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3350 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
3351 /* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3352 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
3353 /* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */
3354 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
3355 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */
3356 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
3357 /* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */
3358 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
3359 /* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */
3360 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3361 /* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */
3362 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3363 
3364 /*
3365  * Field : Small RX FIFO not empty - rxthreshcmp
3366  *
3367  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than
3368  * RX THRESHOLD entries, 1 : FIFO has >= THRESHOLD entries
3369  *
3370  * Field Enumeration Values:
3371  *
3372  * Enum | Value | Description
3373  * :----------------------------------|:------|:-----------------------------
3374  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries
3375  * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries
3376  *
3377  * Field Access Macros:
3378  *
3379  */
3380 /*
3381  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
3382  *
3383  * FIFO has <= RXTHRESH entries
3384  */
3385 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
3386 /*
3387  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
3388  *
3389  * FIFO has > RXTHRESH entries
3390  */
3391 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
3392 
3393 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3394 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
3395 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3396 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
3397 /* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3398 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
3399 /* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
3400 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
3401 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
3402 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
3403 /* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
3404 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
3405 /* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */
3406 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3407 /* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */
3408 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3409 
3410 /*
3411  * Field : Small RX FIFO full - rxfull
3412  *
3413  * Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1
3414  * : FIFO is full
3415  *
3416  * Field Enumeration Values:
3417  *
3418  * Enum | Value | Description
3419  * :----------------------------------|:------|:----------------------
3420  * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full
3421  * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full
3422  *
3423  * Field Access Macros:
3424  *
3425  */
3426 /*
3427  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
3428  *
3429  * Receive FIFO Not Full
3430  */
3431 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
3432 /*
3433  * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
3434  *
3435  * Receive FIFO Full
3436  */
3437 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
3438 
3439 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3440 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
3441 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3442 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
3443 /* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3444 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
3445 /* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */
3446 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
3447 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */
3448 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
3449 /* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */
3450 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
3451 /* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */
3452 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3453 /* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */
3454 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3455 
3456 /*
3457  * Field : Indirect Read Partition overflow - indsramfull
3458  *
3459  * Indirect Read Partition of SRAM is full and unable to immediately complete
3460  * indirect operation
3461  *
3462  * Field Enumeration Values:
3463  *
3464  * Enum | Value | Description
3465  * :---------------------------------------------|:------|:-----------------
3466  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full
3467  * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full
3468  *
3469  * Field Access Macros:
3470  *
3471  */
3472 /*
3473  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
3474  *
3475  * SRAM is not full
3476  */
3477 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
3478 /*
3479  * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
3480  *
3481  * SRAM is full
3482  */
3483 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
3484 
3485 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3486 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
3487 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3488 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
3489 /* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3490 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
3491 /* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
3492 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
3493 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
3494 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
3495 /* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
3496 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
3497 /* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */
3498 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3499 /* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */
3500 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3501 
3502 /*
3503  * Field : Reserved - irq_stat_resv_fld
3504  *
3505  * Field Access Macros:
3506  *
3507  */
3508 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3509 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_LSB 13
3510 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3511 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_MSB 31
3512 /* The width in bits of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3513 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_WIDTH 19
3514 /* The mask used to set the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value. */
3515 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET_MSK 0xffffe000
3516 /* The mask used to clear the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value. */
3517 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_CLR_MSK 0x00001fff
3518 /* The reset value of the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field. */
3519 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_RESET 0x0
3520 /* Extracts the ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD field value from a register. */
3521 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
3522 /* Produces a ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD register field value suitable for setting the register. */
3523 #define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
3524 
3525 #ifndef __ASSEMBLY__
3526 /*
3527  * WARNING: The C register and register group struct declarations are provided for
3528  * convenience and illustrative purposes. They should, however, be used with
3529  * caution as the C language standard provides no guarantees about the alignment or
3530  * atomicity of device memory accesses. The recommended practice for coding device
3531  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3532  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3533  * alt_write_dword() functions for 64 bit registers.
3534  *
3535  * The struct declaration for register ALT_QSPI_IRQSTAT.
3536  */
3537 struct ALT_QSPI_IRQSTAT_s
3538 {
3539  volatile uint32_t mode_m_fail_fld : 1; /* Mode M Failure */
3540  volatile uint32_t underflowdet : 1; /* Underflow Detected */
3541  volatile uint32_t indopdone : 1; /* Indirect Operation Complete */
3542  volatile uint32_t indrdreject : 1; /* Indirect Read Reject */
3543  volatile uint32_t protwrattempt : 1; /* Protected Area Write Attempt */
3544  volatile uint32_t illegalacc : 1; /* Illegal AHB Access Detected */
3545  volatile uint32_t indxfrlvl : 1; /* Transfer Watermark Breach */
3546  volatile uint32_t rxover : 1; /* Receive Overflow */
3547  volatile uint32_t txthreshcmp : 1; /* Small TX FIFO not full */
3548  volatile uint32_t txfull : 1; /* Small TX FIFO full */
3549  volatile uint32_t rxthreshcmp : 1; /* Small RX FIFO not empty */
3550  volatile uint32_t rxfull : 1; /* Small RX FIFO full */
3551  volatile uint32_t indsramfull : 1; /* Indirect Read Partition overflow */
3552  const volatile uint32_t irq_stat_resv_fld : 19; /* Reserved */
3553 };
3554 
3555 /* The typedef declaration for register ALT_QSPI_IRQSTAT. */
3556 typedef struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
3557 #endif /* __ASSEMBLY__ */
3558 
3559 /* The reset value of the ALT_QSPI_IRQSTAT register. */
3560 #define ALT_QSPI_IRQSTAT_RESET 0x00000100
3561 /* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */
3562 #define ALT_QSPI_IRQSTAT_OFST 0x40
3563 /* The address of the ALT_QSPI_IRQSTAT register. */
3564 #define ALT_QSPI_IRQSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_IRQSTAT_OFST))
3565 
3566 /*
3567  * Register : Interrupt Mask - irqmask
3568  *
3569  * 0 : the interrupt for the corresponding interrupt status register bit is
3570  * disabled. 1 : the interrupt for the corresponding interrupt status register bit
3571  * is enabled.
3572  *
3573  * Register Layout
3574  *
3575  * Bits | Access | Reset | Description
3576  * :--------|:-------|:------|:--------------------------------------
3577  * [0] | RW | 0x0 | Mode M Failure Mask
3578  * [1] | RW | 0x0 | Underflow Detected Mask
3579  * [2] | RW | 0x0 | Indirect Complete Mask
3580  * [3] | RW | 0x0 | Indirect Read Reject Mask
3581  * [4] | RW | 0x0 | Protected Area Write Attempt Mask
3582  * [5] | RW | 0x0 | Illegal Access Detected Mask
3583  * [6] | RW | 0x0 | Transfer Watermark Breach Mask
3584  * [7] | RW | 0x0 | Receive Overflow Mask
3585  * [8] | RW | 0x0 | Small TX FIFO not full Mask
3586  * [9] | RW | 0x0 | Small TX FIFO full Mask
3587  * [10] | RW | 0x0 | Small RX FIFO not empty Mask
3588  * [11] | RW | 0x0 | Small RX FIFO full Mask
3589  * [12] | RW | 0x0 | Indirect Read Partition overflow mask
3590  * [31:13] | R | 0x0 | Reserved
3591  *
3592  */
3593 /*
3594  * Field : Mode M Failure Mask - mode_m_fail_mask_fld
3595  *
3596  * Field Access Macros:
3597  *
3598  */
3599 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field. */
3600 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_LSB 0
3601 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field. */
3602 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_MSB 0
3603 /* The width in bits of the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field. */
3604 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_WIDTH 1
3605 /* The mask used to set the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field value. */
3606 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_SET_MSK 0x00000001
3607 /* The mask used to clear the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field value. */
3608 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_CLR_MSK 0xfffffffe
3609 /* The reset value of the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field. */
3610 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_RESET 0x0
3611 /* Extracts the ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD field value from a register. */
3612 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_GET(value) (((value) & 0x00000001) >> 0)
3613 /* Produces a ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD register field value suitable for setting the register. */
3614 #define ALT_QSPI_IRQMASK_MODE_M_FAIL_MASK_FLD_SET(value) (((value) << 0) & 0x00000001)
3615 
3616 /*
3617  * Field : Underflow Detected Mask - underflowdet
3618  *
3619  * Field Enumeration Values:
3620  *
3621  * Enum | Value | Description
3622  * :-----------------------------------------|:------|:-----------------------------
3623  * ALT_QSPI_IRQMASK_UNDERFLOWDET_E_DISABLED | 0x0 | Disable Interrupt by Masking
3624  * ALT_QSPI_IRQMASK_UNDERFLOWDET_E_ENABLED | 0x1 | Enable Interrupt
3625  *
3626  * Field Access Macros:
3627  *
3628  */
3629 /*
3630  * Enumerated value for register field ALT_QSPI_IRQMASK_UNDERFLOWDET
3631  *
3632  * Disable Interrupt by Masking
3633  */
3634 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_E_DISABLED 0x0
3635 /*
3636  * Enumerated value for register field ALT_QSPI_IRQMASK_UNDERFLOWDET
3637  *
3638  * Enable Interrupt
3639  */
3640 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_E_ENABLED 0x1
3641 
3642 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_UNDERFLOWDET register field. */
3643 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_LSB 1
3644 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_UNDERFLOWDET register field. */
3645 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_MSB 1
3646 /* The width in bits of the ALT_QSPI_IRQMASK_UNDERFLOWDET register field. */
3647 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_WIDTH 1
3648 /* The mask used to set the ALT_QSPI_IRQMASK_UNDERFLOWDET register field value. */
3649 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_SET_MSK 0x00000002
3650 /* The mask used to clear the ALT_QSPI_IRQMASK_UNDERFLOWDET register field value. */
3651 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3652 /* The reset value of the ALT_QSPI_IRQMASK_UNDERFLOWDET register field. */
3653 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_RESET 0x0
3654 /* Extracts the ALT_QSPI_IRQMASK_UNDERFLOWDET field value from a register. */
3655 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3656 /* Produces a ALT_QSPI_IRQMASK_UNDERFLOWDET register field value suitable for setting the register. */
3657 #define ALT_QSPI_IRQMASK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3658 
3659 /*
3660  * Field : Indirect Complete Mask - indopdone
3661  *
3662  * Field Enumeration Values:
3663  *
3664  * Enum | Value | Description
3665  * :--------------------------------------|:------|:-----------------------------
3666  * ALT_QSPI_IRQMASK_INDOPDONE_E_DISABLED | 0x0 | Disable Interrupt by Masking
3667  * ALT_QSPI_IRQMASK_INDOPDONE_E_ENABLED | 0x1 | Enable Interrupt
3668  *
3669  * Field Access Macros:
3670  *
3671  */
3672 /*
3673  * Enumerated value for register field ALT_QSPI_IRQMASK_INDOPDONE
3674  *
3675  * Disable Interrupt by Masking
3676  */
3677 #define ALT_QSPI_IRQMASK_INDOPDONE_E_DISABLED 0x0
3678 /*
3679  * Enumerated value for register field ALT_QSPI_IRQMASK_INDOPDONE
3680  *
3681  * Enable Interrupt
3682  */
3683 #define ALT_QSPI_IRQMASK_INDOPDONE_E_ENABLED 0x1
3684 
3685 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_INDOPDONE register field. */
3686 #define ALT_QSPI_IRQMASK_INDOPDONE_LSB 2
3687 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_INDOPDONE register field. */
3688 #define ALT_QSPI_IRQMASK_INDOPDONE_MSB 2
3689 /* The width in bits of the ALT_QSPI_IRQMASK_INDOPDONE register field. */
3690 #define ALT_QSPI_IRQMASK_INDOPDONE_WIDTH 1
3691 /* The mask used to set the ALT_QSPI_IRQMASK_INDOPDONE register field value. */
3692 #define ALT_QSPI_IRQMASK_INDOPDONE_SET_MSK 0x00000004
3693 /* The mask used to clear the ALT_QSPI_IRQMASK_INDOPDONE register field value. */
3694 #define ALT_QSPI_IRQMASK_INDOPDONE_CLR_MSK 0xfffffffb
3695 /* The reset value of the ALT_QSPI_IRQMASK_INDOPDONE register field. */
3696 #define ALT_QSPI_IRQMASK_INDOPDONE_RESET 0x0
3697 /* Extracts the ALT_QSPI_IRQMASK_INDOPDONE field value from a register. */
3698 #define ALT_QSPI_IRQMASK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3699 /* Produces a ALT_QSPI_IRQMASK_INDOPDONE register field value suitable for setting the register. */
3700 #define ALT_QSPI_IRQMASK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3701 
3702 /*
3703  * Field : Indirect Read Reject Mask - indrdreject
3704  *
3705  * Field Enumeration Values:
3706  *
3707  * Enum | Value | Description
3708  * :----------------------------------------|:------|:-----------------------------
3709  * ALT_QSPI_IRQMASK_INDRDREJECT_E_DISABLED | 0x0 | Disable Interrupt by Masking
3710  * ALT_QSPI_IRQMASK_INDRDREJECT_E_ENABLED | 0x1 | Enable Interrupt
3711  *
3712  * Field Access Macros:
3713  *
3714  */
3715 /*
3716  * Enumerated value for register field ALT_QSPI_IRQMASK_INDRDREJECT
3717  *
3718  * Disable Interrupt by Masking
3719  */
3720 #define ALT_QSPI_IRQMASK_INDRDREJECT_E_DISABLED 0x0
3721 /*
3722  * Enumerated value for register field ALT_QSPI_IRQMASK_INDRDREJECT
3723  *
3724  * Enable Interrupt
3725  */
3726 #define ALT_QSPI_IRQMASK_INDRDREJECT_E_ENABLED 0x1
3727 
3728 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_INDRDREJECT register field. */
3729 #define ALT_QSPI_IRQMASK_INDRDREJECT_LSB 3
3730 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_INDRDREJECT register field. */
3731 #define ALT_QSPI_IRQMASK_INDRDREJECT_MSB 3
3732 /* The width in bits of the ALT_QSPI_IRQMASK_INDRDREJECT register field. */
3733 #define ALT_QSPI_IRQMASK_INDRDREJECT_WIDTH 1
3734 /* The mask used to set the ALT_QSPI_IRQMASK_INDRDREJECT register field value. */
3735 #define ALT_QSPI_IRQMASK_INDRDREJECT_SET_MSK 0x00000008
3736 /* The mask used to clear the ALT_QSPI_IRQMASK_INDRDREJECT register field value. */
3737 #define ALT_QSPI_IRQMASK_INDRDREJECT_CLR_MSK 0xfffffff7
3738 /* The reset value of the ALT_QSPI_IRQMASK_INDRDREJECT register field. */
3739 #define ALT_QSPI_IRQMASK_INDRDREJECT_RESET 0x0
3740 /* Extracts the ALT_QSPI_IRQMASK_INDRDREJECT field value from a register. */
3741 #define ALT_QSPI_IRQMASK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3742 /* Produces a ALT_QSPI_IRQMASK_INDRDREJECT register field value suitable for setting the register. */
3743 #define ALT_QSPI_IRQMASK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3744 
3745 /*
3746  * Field : Protected Area Write Attempt Mask - protwrattempt
3747  *
3748  * Field Enumeration Values:
3749  *
3750  * Enum | Value | Description
3751  * :------------------------------------------|:------|:-----------------------------
3752  * ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_DISABLED | 0x0 | Disable Interrupt by Masking
3753  * ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_ENABLED | 0x1 | Enable Interrupt
3754  *
3755  * Field Access Macros:
3756  *
3757  */
3758 /*
3759  * Enumerated value for register field ALT_QSPI_IRQMASK_PROTWRATTEMPT
3760  *
3761  * Disable Interrupt by Masking
3762  */
3763 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_DISABLED 0x0
3764 /*
3765  * Enumerated value for register field ALT_QSPI_IRQMASK_PROTWRATTEMPT
3766  *
3767  * Enable Interrupt
3768  */
3769 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_E_ENABLED 0x1
3770 
3771 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field. */
3772 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_LSB 4
3773 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field. */
3774 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_MSB 4
3775 /* The width in bits of the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field. */
3776 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_WIDTH 1
3777 /* The mask used to set the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field value. */
3778 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_SET_MSK 0x00000010
3779 /* The mask used to clear the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field value. */
3780 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3781 /* The reset value of the ALT_QSPI_IRQMASK_PROTWRATTEMPT register field. */
3782 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_RESET 0x0
3783 /* Extracts the ALT_QSPI_IRQMASK_PROTWRATTEMPT field value from a register. */
3784 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3785 /* Produces a ALT_QSPI_IRQMASK_PROTWRATTEMPT register field value suitable for setting the register. */
3786 #define ALT_QSPI_IRQMASK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3787 
3788 /*
3789  * Field : Illegal Access Detected Mask - illegalacc
3790  *
3791  * Field Enumeration Values:
3792  *
3793  * Enum | Value | Description
3794  * :---------------------------------------|:------|:-----------------------------
3795  * ALT_QSPI_IRQMASK_ILLEGALACC_E_DISABLED | 0x0 | Disable Interrupt by Masking
3796  * ALT_QSPI_IRQMASK_ILLEGALACC_E_ENABLED | 0x1 | Enable Interrupt
3797  *
3798  * Field Access Macros:
3799  *
3800  */
3801 /*
3802  * Enumerated value for register field ALT_QSPI_IRQMASK_ILLEGALACC
3803  *
3804  * Disable Interrupt by Masking
3805  */
3806 #define ALT_QSPI_IRQMASK_ILLEGALACC_E_DISABLED 0x0
3807 /*
3808  * Enumerated value for register field ALT_QSPI_IRQMASK_ILLEGALACC
3809  *
3810  * Enable Interrupt
3811  */
3812 #define ALT_QSPI_IRQMASK_ILLEGALACC_E_ENABLED 0x1
3813 
3814 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_ILLEGALACC register field. */
3815 #define ALT_QSPI_IRQMASK_ILLEGALACC_LSB 5
3816 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_ILLEGALACC register field. */
3817 #define ALT_QSPI_IRQMASK_ILLEGALACC_MSB 5
3818 /* The width in bits of the ALT_QSPI_IRQMASK_ILLEGALACC register field. */
3819 #define ALT_QSPI_IRQMASK_ILLEGALACC_WIDTH 1
3820 /* The mask used to set the ALT_QSPI_IRQMASK_ILLEGALACC register field value. */
3821 #define ALT_QSPI_IRQMASK_ILLEGALACC_SET_MSK 0x00000020
3822 /* The mask used to clear the ALT_QSPI_IRQMASK_ILLEGALACC register field value. */
3823 #define ALT_QSPI_IRQMASK_ILLEGALACC_CLR_MSK 0xffffffdf
3824 /* The reset value of the ALT_QSPI_IRQMASK_ILLEGALACC register field. */
3825 #define ALT_QSPI_IRQMASK_ILLEGALACC_RESET 0x0
3826 /* Extracts the ALT_QSPI_IRQMASK_ILLEGALACC field value from a register. */
3827 #define ALT_QSPI_IRQMASK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3828 /* Produces a ALT_QSPI_IRQMASK_ILLEGALACC register field value suitable for setting the register. */
3829 #define ALT_QSPI_IRQMASK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3830 
3831 /*
3832  * Field : Transfer Watermark Breach Mask - indxfrlvl
3833  *
3834  * Field Enumeration Values:
3835  *
3836  * Enum | Value | Description
3837  * :--------------------------------------|:------|:-----------------------------
3838  * ALT_QSPI_IRQMASK_INDXFRLVL_E_DISABLED | 0x0 | Disable Interrupt by Masking
3839  * ALT_QSPI_IRQMASK_INDXFRLVL_E_ENABLED | 0x1 | Enable Interrupt
3840  *
3841  * Field Access Macros:
3842  *
3843  */
3844 /*
3845  * Enumerated value for register field ALT_QSPI_IRQMASK_INDXFRLVL
3846  *
3847  * Disable Interrupt by Masking
3848  */
3849 #define ALT_QSPI_IRQMASK_INDXFRLVL_E_DISABLED 0x0
3850 /*
3851  * Enumerated value for register field ALT_QSPI_IRQMASK_INDXFRLVL
3852  *
3853  * Enable Interrupt
3854  */
3855 #define ALT_QSPI_IRQMASK_INDXFRLVL_E_ENABLED 0x1
3856 
3857 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_INDXFRLVL register field. */
3858 #define ALT_QSPI_IRQMASK_INDXFRLVL_LSB 6
3859 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_INDXFRLVL register field. */
3860 #define ALT_QSPI_IRQMASK_INDXFRLVL_MSB 6
3861 /* The width in bits of the ALT_QSPI_IRQMASK_INDXFRLVL register field. */
3862 #define ALT_QSPI_IRQMASK_INDXFRLVL_WIDTH 1
3863 /* The mask used to set the ALT_QSPI_IRQMASK_INDXFRLVL register field value. */
3864 #define ALT_QSPI_IRQMASK_INDXFRLVL_SET_MSK 0x00000040
3865 /* The mask used to clear the ALT_QSPI_IRQMASK_INDXFRLVL register field value. */
3866 #define ALT_QSPI_IRQMASK_INDXFRLVL_CLR_MSK 0xffffffbf
3867 /* The reset value of the ALT_QSPI_IRQMASK_INDXFRLVL register field. */
3868 #define ALT_QSPI_IRQMASK_INDXFRLVL_RESET 0x0
3869 /* Extracts the ALT_QSPI_IRQMASK_INDXFRLVL field value from a register. */
3870 #define ALT_QSPI_IRQMASK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3871 /* Produces a ALT_QSPI_IRQMASK_INDXFRLVL register field value suitable for setting the register. */
3872 #define ALT_QSPI_IRQMASK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3873 
3874 /*
3875  * Field : Receive Overflow Mask - rxover
3876  *
3877  * Field Enumeration Values:
3878  *
3879  * Enum | Value | Description
3880  * :-----------------------------------|:------|:-----------------------------
3881  * ALT_QSPI_IRQMASK_RXOVER_E_DISABLED | 0x0 | Disable Interrupt by Masking
3882  * ALT_QSPI_IRQMASK_RXOVER_E_ENABLED | 0x1 | Enable Interrupt
3883  *
3884  * Field Access Macros:
3885  *
3886  */
3887 /*
3888  * Enumerated value for register field ALT_QSPI_IRQMASK_RXOVER
3889  *
3890  * Disable Interrupt by Masking
3891  */
3892 #define ALT_QSPI_IRQMASK_RXOVER_E_DISABLED 0x0
3893 /*
3894  * Enumerated value for register field ALT_QSPI_IRQMASK_RXOVER
3895  *
3896  * Enable Interrupt
3897  */
3898 #define ALT_QSPI_IRQMASK_RXOVER_E_ENABLED 0x1
3899 
3900 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_RXOVER register field. */
3901 #define ALT_QSPI_IRQMASK_RXOVER_LSB 7
3902 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_RXOVER register field. */
3903 #define ALT_QSPI_IRQMASK_RXOVER_MSB 7
3904 /* The width in bits of the ALT_QSPI_IRQMASK_RXOVER register field. */
3905 #define ALT_QSPI_IRQMASK_RXOVER_WIDTH 1
3906 /* The mask used to set the ALT_QSPI_IRQMASK_RXOVER register field value. */
3907 #define ALT_QSPI_IRQMASK_RXOVER_SET_MSK 0x00000080
3908 /* The mask used to clear the ALT_QSPI_IRQMASK_RXOVER register field value. */
3909 #define ALT_QSPI_IRQMASK_RXOVER_CLR_MSK 0xffffff7f
3910 /* The reset value of the ALT_QSPI_IRQMASK_RXOVER register field. */
3911 #define ALT_QSPI_IRQMASK_RXOVER_RESET 0x0
3912 /* Extracts the ALT_QSPI_IRQMASK_RXOVER field value from a register. */
3913 #define ALT_QSPI_IRQMASK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3914 /* Produces a ALT_QSPI_IRQMASK_RXOVER register field value suitable for setting the register. */
3915 #define ALT_QSPI_IRQMASK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3916 
3917 /*
3918  * Field : Small TX FIFO not full Mask - txthreshcmp
3919  *
3920  * Field Enumeration Values:
3921  *
3922  * Enum | Value | Description
3923  * :----------------------------------------|:------|:-----------------------------
3924  * ALT_QSPI_IRQMASK_TXTHRESHCMP_E_DISABLED | 0x0 | Disable Interrupt by Masking
3925  * ALT_QSPI_IRQMASK_TXTHRESHCMP_E_ENABLED | 0x1 | Enable Interrupt
3926  *
3927  * Field Access Macros:
3928  *
3929  */
3930 /*
3931  * Enumerated value for register field ALT_QSPI_IRQMASK_TXTHRESHCMP
3932  *
3933  * Disable Interrupt by Masking
3934  */
3935 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_E_DISABLED 0x0
3936 /*
3937  * Enumerated value for register field ALT_QSPI_IRQMASK_TXTHRESHCMP
3938  *
3939  * Enable Interrupt
3940  */
3941 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_E_ENABLED 0x1
3942 
3943 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_TXTHRESHCMP register field. */
3944 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_LSB 8
3945 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_TXTHRESHCMP register field. */
3946 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_MSB 8
3947 /* The width in bits of the ALT_QSPI_IRQMASK_TXTHRESHCMP register field. */
3948 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_WIDTH 1
3949 /* The mask used to set the ALT_QSPI_IRQMASK_TXTHRESHCMP register field value. */
3950 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_SET_MSK 0x00000100
3951 /* The mask used to clear the ALT_QSPI_IRQMASK_TXTHRESHCMP register field value. */
3952 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3953 /* The reset value of the ALT_QSPI_IRQMASK_TXTHRESHCMP register field. */
3954 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_RESET 0x0
3955 /* Extracts the ALT_QSPI_IRQMASK_TXTHRESHCMP field value from a register. */
3956 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3957 /* Produces a ALT_QSPI_IRQMASK_TXTHRESHCMP register field value suitable for setting the register. */
3958 #define ALT_QSPI_IRQMASK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3959 
3960 /*
3961  * Field : Small TX FIFO full Mask - txfull
3962  *
3963  * Field Enumeration Values:
3964  *
3965  * Enum | Value | Description
3966  * :-----------------------------------|:------|:-----------------------------
3967  * ALT_QSPI_IRQMASK_TXFULL_E_DISABLED | 0x0 | Disable Interrupt by Masking
3968  * ALT_QSPI_IRQMASK_TXFULL_E_ENABLED | 0x1 | Enable Interrupt
3969  *
3970  * Field Access Macros:
3971  *
3972  */
3973 /*
3974  * Enumerated value for register field ALT_QSPI_IRQMASK_TXFULL
3975  *
3976  * Disable Interrupt by Masking
3977  */
3978 #define ALT_QSPI_IRQMASK_TXFULL_E_DISABLED 0x0
3979 /*
3980  * Enumerated value for register field ALT_QSPI_IRQMASK_TXFULL
3981  *
3982  * Enable Interrupt
3983  */
3984 #define ALT_QSPI_IRQMASK_TXFULL_E_ENABLED 0x1
3985 
3986 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_TXFULL register field. */
3987 #define ALT_QSPI_IRQMASK_TXFULL_LSB 9
3988 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_TXFULL register field. */
3989 #define ALT_QSPI_IRQMASK_TXFULL_MSB 9
3990 /* The width in bits of the ALT_QSPI_IRQMASK_TXFULL register field. */
3991 #define ALT_QSPI_IRQMASK_TXFULL_WIDTH 1
3992 /* The mask used to set the ALT_QSPI_IRQMASK_TXFULL register field value. */
3993 #define ALT_QSPI_IRQMASK_TXFULL_SET_MSK 0x00000200
3994 /* The mask used to clear the ALT_QSPI_IRQMASK_TXFULL register field value. */
3995 #define ALT_QSPI_IRQMASK_TXFULL_CLR_MSK 0xfffffdff
3996 /* The reset value of the ALT_QSPI_IRQMASK_TXFULL register field. */
3997 #define ALT_QSPI_IRQMASK_TXFULL_RESET 0x0
3998 /* Extracts the ALT_QSPI_IRQMASK_TXFULL field value from a register. */
3999 #define ALT_QSPI_IRQMASK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
4000 /* Produces a ALT_QSPI_IRQMASK_TXFULL register field value suitable for setting the register. */
4001 #define ALT_QSPI_IRQMASK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
4002 
4003 /*
4004  * Field : Small RX FIFO not empty Mask - rxthreshcmp
4005  *
4006  * Field Enumeration Values:
4007  *
4008  * Enum | Value | Description
4009  * :----------------------------------------|:------|:-----------------------------
4010  * ALT_QSPI_IRQMASK_RXTHRESHCMP_E_DISABLED | 0x0 | Disable Interrupt by Masking
4011  * ALT_QSPI_IRQMASK_RXTHRESHCMP_E_ENABLED | 0x1 | Enable Interrupt
4012  *
4013  * Field Access Macros:
4014  *
4015  */
4016 /*
4017  * Enumerated value for register field ALT_QSPI_IRQMASK_RXTHRESHCMP
4018  *
4019  * Disable Interrupt by Masking
4020  */
4021 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_E_DISABLED 0x0
4022 /*
4023  * Enumerated value for register field ALT_QSPI_IRQMASK_RXTHRESHCMP
4024  *
4025  * Enable Interrupt
4026  */
4027 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_E_ENABLED 0x1
4028 
4029 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_RXTHRESHCMP register field. */
4030 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_LSB 10
4031 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_RXTHRESHCMP register field. */
4032 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_MSB 10
4033 /* The width in bits of the ALT_QSPI_IRQMASK_RXTHRESHCMP register field. */
4034 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_WIDTH 1
4035 /* The mask used to set the ALT_QSPI_IRQMASK_RXTHRESHCMP register field value. */
4036 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_SET_MSK 0x00000400
4037 /* The mask used to clear the ALT_QSPI_IRQMASK_RXTHRESHCMP register field value. */
4038 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_CLR_MSK 0xfffffbff
4039 /* The reset value of the ALT_QSPI_IRQMASK_RXTHRESHCMP register field. */
4040 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_RESET 0x0
4041 /* Extracts the ALT_QSPI_IRQMASK_RXTHRESHCMP field value from a register. */
4042 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
4043 /* Produces a ALT_QSPI_IRQMASK_RXTHRESHCMP register field value suitable for setting the register. */
4044 #define ALT_QSPI_IRQMASK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
4045 
4046 /*
4047  * Field : Small RX FIFO full Mask - rxfull
4048  *
4049  * Field Enumeration Values:
4050  *
4051  * Enum | Value | Description
4052  * :-----------------------------------|:------|:-----------------------------
4053  * ALT_QSPI_IRQMASK_RXFULL_E_DISABLED | 0x0 | Disable Interrupt by Masking
4054  * ALT_QSPI_IRQMASK_RXFULL_E_ENABLED | 0x1 | Enable Interrupt
4055  *
4056  * Field Access Macros:
4057  *
4058  */
4059 /*
4060  * Enumerated value for register field ALT_QSPI_IRQMASK_RXFULL
4061  *
4062  * Disable Interrupt by Masking
4063  */
4064 #define ALT_QSPI_IRQMASK_RXFULL_E_DISABLED 0x0
4065 /*
4066  * Enumerated value for register field ALT_QSPI_IRQMASK_RXFULL
4067  *
4068  * Enable Interrupt
4069  */
4070 #define ALT_QSPI_IRQMASK_RXFULL_E_ENABLED 0x1
4071 
4072 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_RXFULL register field. */
4073 #define ALT_QSPI_IRQMASK_RXFULL_LSB 11
4074 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_RXFULL register field. */
4075 #define ALT_QSPI_IRQMASK_RXFULL_MSB 11
4076 /* The width in bits of the ALT_QSPI_IRQMASK_RXFULL register field. */
4077 #define ALT_QSPI_IRQMASK_RXFULL_WIDTH 1
4078 /* The mask used to set the ALT_QSPI_IRQMASK_RXFULL register field value. */
4079 #define ALT_QSPI_IRQMASK_RXFULL_SET_MSK 0x00000800
4080 /* The mask used to clear the ALT_QSPI_IRQMASK_RXFULL register field value. */
4081 #define ALT_QSPI_IRQMASK_RXFULL_CLR_MSK 0xfffff7ff
4082 /* The reset value of the ALT_QSPI_IRQMASK_RXFULL register field. */
4083 #define ALT_QSPI_IRQMASK_RXFULL_RESET 0x0
4084 /* Extracts the ALT_QSPI_IRQMASK_RXFULL field value from a register. */
4085 #define ALT_QSPI_IRQMASK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
4086 /* Produces a ALT_QSPI_IRQMASK_RXFULL register field value suitable for setting the register. */
4087 #define ALT_QSPI_IRQMASK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
4088 
4089 /*
4090  * Field : Indirect Read Partition overflow mask - indsramfull
4091  *
4092  * Field Enumeration Values:
4093  *
4094  * Enum | Value | Description
4095  * :----------------------------------------|:------|:-----------------------------
4096  * ALT_QSPI_IRQMASK_INDSRAMFULL_E_DISABLED | 0x0 | Disable Interrupt by Masking
4097  * ALT_QSPI_IRQMASK_INDSRAMFULL_E_ENABLED | 0x1 | Enable Interrupt
4098  *
4099  * Field Access Macros:
4100  *
4101  */
4102 /*
4103  * Enumerated value for register field ALT_QSPI_IRQMASK_INDSRAMFULL
4104  *
4105  * Disable Interrupt by Masking
4106  */
4107 #define ALT_QSPI_IRQMASK_INDSRAMFULL_E_DISABLED 0x0
4108 /*
4109  * Enumerated value for register field ALT_QSPI_IRQMASK_INDSRAMFULL
4110  *
4111  * Enable Interrupt
4112  */
4113 #define ALT_QSPI_IRQMASK_INDSRAMFULL_E_ENABLED 0x1
4114 
4115 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_INDSRAMFULL register field. */
4116 #define ALT_QSPI_IRQMASK_INDSRAMFULL_LSB 12
4117 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_INDSRAMFULL register field. */
4118 #define ALT_QSPI_IRQMASK_INDSRAMFULL_MSB 12
4119 /* The width in bits of the ALT_QSPI_IRQMASK_INDSRAMFULL register field. */
4120 #define ALT_QSPI_IRQMASK_INDSRAMFULL_WIDTH 1
4121 /* The mask used to set the ALT_QSPI_IRQMASK_INDSRAMFULL register field value. */
4122 #define ALT_QSPI_IRQMASK_INDSRAMFULL_SET_MSK 0x00001000
4123 /* The mask used to clear the ALT_QSPI_IRQMASK_INDSRAMFULL register field value. */
4124 #define ALT_QSPI_IRQMASK_INDSRAMFULL_CLR_MSK 0xffffefff
4125 /* The reset value of the ALT_QSPI_IRQMASK_INDSRAMFULL register field. */
4126 #define ALT_QSPI_IRQMASK_INDSRAMFULL_RESET 0x0
4127 /* Extracts the ALT_QSPI_IRQMASK_INDSRAMFULL field value from a register. */
4128 #define ALT_QSPI_IRQMASK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
4129 /* Produces a ALT_QSPI_IRQMASK_INDSRAMFULL register field value suitable for setting the register. */
4130 #define ALT_QSPI_IRQMASK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
4131 
4132 /*
4133  * Field : Reserved - irq_mask_resv_fld
4134  *
4135  * Field Access Macros:
4136  *
4137  */
4138 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field. */
4139 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_LSB 13
4140 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field. */
4141 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_MSB 31
4142 /* The width in bits of the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field. */
4143 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_WIDTH 19
4144 /* The mask used to set the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field value. */
4145 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_SET_MSK 0xffffe000
4146 /* The mask used to clear the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field value. */
4147 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_CLR_MSK 0x00001fff
4148 /* The reset value of the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field. */
4149 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_RESET 0x0
4150 /* Extracts the ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD field value from a register. */
4151 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
4152 /* Produces a ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD register field value suitable for setting the register. */
4153 #define ALT_QSPI_IRQMASK_IRQ_MASK_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
4154 
4155 #ifndef __ASSEMBLY__
4156 /*
4157  * WARNING: The C register and register group struct declarations are provided for
4158  * convenience and illustrative purposes. They should, however, be used with
4159  * caution as the C language standard provides no guarantees about the alignment or
4160  * atomicity of device memory accesses. The recommended practice for coding device
4161  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4162  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4163  * alt_write_dword() functions for 64 bit registers.
4164  *
4165  * The struct declaration for register ALT_QSPI_IRQMASK.
4166  */
4167 struct ALT_QSPI_IRQMASK_s
4168 {
4169  volatile uint32_t mode_m_fail_mask_fld : 1; /* Mode M Failure Mask */
4170  volatile uint32_t underflowdet : 1; /* Underflow Detected Mask */
4171  volatile uint32_t indopdone : 1; /* Indirect Complete Mask */
4172  volatile uint32_t indrdreject : 1; /* Indirect Read Reject Mask */
4173  volatile uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */
4174  volatile uint32_t illegalacc : 1; /* Illegal Access Detected Mask */
4175  volatile uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */
4176  volatile uint32_t rxover : 1; /* Receive Overflow Mask */
4177  volatile uint32_t txthreshcmp : 1; /* Small TX FIFO not full Mask */
4178  volatile uint32_t txfull : 1; /* Small TX FIFO full Mask */
4179  volatile uint32_t rxthreshcmp : 1; /* Small RX FIFO not empty Mask */
4180  volatile uint32_t rxfull : 1; /* Small RX FIFO full Mask */
4181  volatile uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */
4182  const volatile uint32_t irq_mask_resv_fld : 19; /* Reserved */
4183 };
4184 
4185 /* The typedef declaration for register ALT_QSPI_IRQMASK. */
4186 typedef struct ALT_QSPI_IRQMASK_s ALT_QSPI_IRQMASK_t;
4187 #endif /* __ASSEMBLY__ */
4188 
4189 /* The reset value of the ALT_QSPI_IRQMASK register. */
4190 #define ALT_QSPI_IRQMASK_RESET 0x00000000
4191 /* The byte offset of the ALT_QSPI_IRQMASK register from the beginning of the component. */
4192 #define ALT_QSPI_IRQMASK_OFST 0x44
4193 /* The address of the ALT_QSPI_IRQMASK register. */
4194 #define ALT_QSPI_IRQMASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_IRQMASK_OFST))
4195 
4196 /*
4197  * Register : Lower Write Protection Register - lowwrprot
4198  *
4199  * Register Layout
4200  *
4201  * Bits | Access | Reset | Description
4202  * :-------|:-------|:------|:-------------
4203  * [31:0] | RW | 0x0 | Block Number
4204  *
4205  */
4206 /*
4207  * Field : Block Number - subsector
4208  *
4209  * The block number that defines the lower block in the range of blocks that is to
4210  * be locked from writing. The definition of a block in terms of number of bytes is
4211  * programmable via the Device Size Configuration register.
4212  *
4213  * Field Access Macros:
4214  *
4215  */
4216 /* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4217 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
4218 /* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4219 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
4220 /* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4221 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
4222 /* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
4223 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4224 /* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
4225 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4226 /* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
4227 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
4228 /* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */
4229 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4230 /* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */
4231 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4232 
4233 #ifndef __ASSEMBLY__
4234 /*
4235  * WARNING: The C register and register group struct declarations are provided for
4236  * convenience and illustrative purposes. They should, however, be used with
4237  * caution as the C language standard provides no guarantees about the alignment or
4238  * atomicity of device memory accesses. The recommended practice for coding device
4239  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4240  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4241  * alt_write_dword() functions for 64 bit registers.
4242  *
4243  * The struct declaration for register ALT_QSPI_LOWWRPROT.
4244  */
4245 struct ALT_QSPI_LOWWRPROT_s
4246 {
4247  volatile uint32_t subsector : 32; /* Block Number */
4248 };
4249 
4250 /* The typedef declaration for register ALT_QSPI_LOWWRPROT. */
4251 typedef struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
4252 #endif /* __ASSEMBLY__ */
4253 
4254 /* The reset value of the ALT_QSPI_LOWWRPROT register. */
4255 #define ALT_QSPI_LOWWRPROT_RESET 0x00000000
4256 /* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */
4257 #define ALT_QSPI_LOWWRPROT_OFST 0x50
4258 /* The address of the ALT_QSPI_LOWWRPROT register. */
4259 #define ALT_QSPI_LOWWRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_LOWWRPROT_OFST))
4260 
4261 /*
4262  * Register : Upper Write Protection Register - uppwrprot
4263  *
4264  * Register Layout
4265  *
4266  * Bits | Access | Reset | Description
4267  * :-------|:-------|:------|:-------------
4268  * [31:0] | RW | 0x0 | Block Number
4269  *
4270  */
4271 /*
4272  * Field : Block Number - subsector
4273  *
4274  * The block number that defines the upper block in the range of blocks that is to
4275  * be locked from writing. The definition of a block in terms of number of bytes is
4276  * programmable via the Device Size Configuration register.
4277  *
4278  * Field Access Macros:
4279  *
4280  */
4281 /* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4282 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
4283 /* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4284 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
4285 /* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4286 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
4287 /* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
4288 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4289 /* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
4290 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4291 /* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
4292 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
4293 /* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */
4294 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4295 /* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */
4296 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4297 
4298 #ifndef __ASSEMBLY__
4299 /*
4300  * WARNING: The C register and register group struct declarations are provided for
4301  * convenience and illustrative purposes. They should, however, be used with
4302  * caution as the C language standard provides no guarantees about the alignment or
4303  * atomicity of device memory accesses. The recommended practice for coding device
4304  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4305  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4306  * alt_write_dword() functions for 64 bit registers.
4307  *
4308  * The struct declaration for register ALT_QSPI_UPPWRPROT.
4309  */
4310 struct ALT_QSPI_UPPWRPROT_s
4311 {
4312  volatile uint32_t subsector : 32; /* Block Number */
4313 };
4314 
4315 /* The typedef declaration for register ALT_QSPI_UPPWRPROT. */
4316 typedef struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
4317 #endif /* __ASSEMBLY__ */
4318 
4319 /* The reset value of the ALT_QSPI_UPPWRPROT register. */
4320 #define ALT_QSPI_UPPWRPROT_RESET 0x00000000
4321 /* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */
4322 #define ALT_QSPI_UPPWRPROT_OFST 0x54
4323 /* The address of the ALT_QSPI_UPPWRPROT register. */
4324 #define ALT_QSPI_UPPWRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_UPPWRPROT_OFST))
4325 
4326 /*
4327  * Register : Write Protection Control Register - wrprot
4328  *
4329  * Register Layout
4330  *
4331  * Bits | Access | Reset | Description
4332  * :-------|:-------|:------|:-------------------------------
4333  * [0] | RW | 0x0 | Write Protection Inversion Bit
4334  * [1] | RW | 0x0 | Write Protection Enable Bit
4335  * [31:2] | R | 0x0 | Reserved
4336  *
4337  */
4338 /*
4339  * Field : Write Protection Inversion Bit - inv
4340  *
4341  * When set to 1, the protection region defined in the lower and upper write
4342  * protection registers is inverted meaning it is the region that the system is
4343  * permitted to write to. When set to 0, the protection region defined in the lower
4344  * and upper write protection registers is the region that the system is not
4345  * permitted to write to.
4346  *
4347  * Field Enumeration Values:
4348  *
4349  * Enum | Value | Description
4350  * :------------------------------|:------|:-------------------------
4351  * ALT_QSPI_WRPROT_INV_E_DISABLE | 0x0 | Write Region not allowed
4352  * ALT_QSPI_WRPROT_INV_E_ENABLE | 0x1 | Write Region allowed
4353  *
4354  * Field Access Macros:
4355  *
4356  */
4357 /*
4358  * Enumerated value for register field ALT_QSPI_WRPROT_INV
4359  *
4360  * Write Region not allowed
4361  */
4362 #define ALT_QSPI_WRPROT_INV_E_DISABLE 0x0
4363 /*
4364  * Enumerated value for register field ALT_QSPI_WRPROT_INV
4365  *
4366  * Write Region allowed
4367  */
4368 #define ALT_QSPI_WRPROT_INV_E_ENABLE 0x1
4369 
4370 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */
4371 #define ALT_QSPI_WRPROT_INV_LSB 0
4372 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */
4373 #define ALT_QSPI_WRPROT_INV_MSB 0
4374 /* The width in bits of the ALT_QSPI_WRPROT_INV register field. */
4375 #define ALT_QSPI_WRPROT_INV_WIDTH 1
4376 /* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */
4377 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
4378 /* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */
4379 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
4380 /* The reset value of the ALT_QSPI_WRPROT_INV register field. */
4381 #define ALT_QSPI_WRPROT_INV_RESET 0x0
4382 /* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */
4383 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
4384 /* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */
4385 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
4386 
4387 /*
4388  * Field : Write Protection Enable Bit - en
4389  *
4390  * When set to 1, any AHB write access with an address within the protection region
4391  * defined in the lower and upper write protection registers is rejected. An AHB
4392  * error response is generated and an interrupt source triggered. When set to 0,
4393  * the protection region is disabled.
4394  *
4395  * Field Enumeration Values:
4396  *
4397  * Enum | Value | Description
4398  * :-----------------------------|:------|:---------------------------
4399  * ALT_QSPI_WRPROT_EN_E_DISABLE | 0x0 | Protection Region Disabled
4400  * ALT_QSPI_WRPROT_EN_E_ENABLE | 0x1 | AHB Write Access rejected
4401  *
4402  * Field Access Macros:
4403  *
4404  */
4405 /*
4406  * Enumerated value for register field ALT_QSPI_WRPROT_EN
4407  *
4408  * Protection Region Disabled
4409  */
4410 #define ALT_QSPI_WRPROT_EN_E_DISABLE 0x0
4411 /*
4412  * Enumerated value for register field ALT_QSPI_WRPROT_EN
4413  *
4414  * AHB Write Access rejected
4415  */
4416 #define ALT_QSPI_WRPROT_EN_E_ENABLE 0x1
4417 
4418 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */
4419 #define ALT_QSPI_WRPROT_EN_LSB 1
4420 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */
4421 #define ALT_QSPI_WRPROT_EN_MSB 1
4422 /* The width in bits of the ALT_QSPI_WRPROT_EN register field. */
4423 #define ALT_QSPI_WRPROT_EN_WIDTH 1
4424 /* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */
4425 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
4426 /* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */
4427 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
4428 /* The reset value of the ALT_QSPI_WRPROT_EN register field. */
4429 #define ALT_QSPI_WRPROT_EN_RESET 0x0
4430 /* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */
4431 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
4432 /* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */
4433 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
4434 
4435 /*
4436  * Field : Reserved - wr_prot_ctrl_resv_fld
4437  *
4438  * Field Access Macros:
4439  *
4440  */
4441 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field. */
4442 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_LSB 2
4443 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field. */
4444 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_MSB 31
4445 /* The width in bits of the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field. */
4446 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_WIDTH 30
4447 /* The mask used to set the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field value. */
4448 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_SET_MSK 0xfffffffc
4449 /* The mask used to clear the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field value. */
4450 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_CLR_MSK 0x00000003
4451 /* The reset value of the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field. */
4452 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_RESET 0x0
4453 /* Extracts the ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD field value from a register. */
4454 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_GET(value) (((value) & 0xfffffffc) >> 2)
4455 /* Produces a ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD register field value suitable for setting the register. */
4456 #define ALT_QSPI_WRPROT_WR_PROT_CTRL_RESV_FLD_SET(value) (((value) << 2) & 0xfffffffc)
4457 
4458 #ifndef __ASSEMBLY__
4459 /*
4460  * WARNING: The C register and register group struct declarations are provided for
4461  * convenience and illustrative purposes. They should, however, be used with
4462  * caution as the C language standard provides no guarantees about the alignment or
4463  * atomicity of device memory accesses. The recommended practice for coding device
4464  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4465  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4466  * alt_write_dword() functions for 64 bit registers.
4467  *
4468  * The struct declaration for register ALT_QSPI_WRPROT.
4469  */
4470 struct ALT_QSPI_WRPROT_s
4471 {
4472  volatile uint32_t inv : 1; /* Write Protection Inversion Bit */
4473  volatile uint32_t en : 1; /* Write Protection Enable Bit */
4474  const volatile uint32_t wr_prot_ctrl_resv_fld : 30; /* Reserved */
4475 };
4476 
4477 /* The typedef declaration for register ALT_QSPI_WRPROT. */
4478 typedef struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
4479 #endif /* __ASSEMBLY__ */
4480 
4481 /* The reset value of the ALT_QSPI_WRPROT register. */
4482 #define ALT_QSPI_WRPROT_RESET 0x00000000
4483 /* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */
4484 #define ALT_QSPI_WRPROT_OFST 0x58
4485 /* The address of the ALT_QSPI_WRPROT register. */
4486 #define ALT_QSPI_WRPROT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_WRPROT_OFST))
4487 
4488 /*
4489  * Register : Indirect Read Transfer Control Register - indrd
4490  *
4491  * Register Layout
4492  *
4493  * Bits | Access | Reset | Description
4494  * :-------|:-------|:------|:--------------------------------
4495  * [0] | W | 0x0 | Start Indirect Read
4496  * [1] | W | 0x0 | Cancel Indirect Read
4497  * [2] | R | 0x0 | Indirect Read Status
4498  * [3] | RW | 0x0 | SRAM Full
4499  * [4] | R | 0x0 | Queued Indirect Read Operations
4500  * [5] | RW | 0x0 | Indirect Completion Status
4501  * [7:6] | R | 0x0 | Completed Indirect Operations
4502  * [31:8] | R | 0x0 | Reserved
4503  *
4504  */
4505 /*
4506  * Field : Start Indirect Read - start
4507  *
4508  * Writing a 1 to this bit will trigger an indirect read operation. The assumption
4509  * is that the indirect start address and the indirect number of bytes register is
4510  * setup before triggering the indirect read operation.
4511  *
4512  * Field Enumeration Values:
4513  *
4514  * Enum | Value | Description
4515  * :--------------------------------|:------|:----------------------
4516  * ALT_QSPI_INDRD_START_E_DISABLED | 0x0 | No Indirect Read
4517  * ALT_QSPI_INDRD_START_E_ENABLED | 0x1 | Trigger Indirect Read
4518  *
4519  * Field Access Macros:
4520  *
4521  */
4522 /*
4523  * Enumerated value for register field ALT_QSPI_INDRD_START
4524  *
4525  * No Indirect Read
4526  */
4527 #define ALT_QSPI_INDRD_START_E_DISABLED 0x0
4528 /*
4529  * Enumerated value for register field ALT_QSPI_INDRD_START
4530  *
4531  * Trigger Indirect Read
4532  */
4533 #define ALT_QSPI_INDRD_START_E_ENABLED 0x1
4534 
4535 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */
4536 #define ALT_QSPI_INDRD_START_LSB 0
4537 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */
4538 #define ALT_QSPI_INDRD_START_MSB 0
4539 /* The width in bits of the ALT_QSPI_INDRD_START register field. */
4540 #define ALT_QSPI_INDRD_START_WIDTH 1
4541 /* The mask used to set the ALT_QSPI_INDRD_START register field value. */
4542 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
4543 /* The mask used to clear the ALT_QSPI_INDRD_START register field value. */
4544 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
4545 /* The reset value of the ALT_QSPI_INDRD_START register field. */
4546 #define ALT_QSPI_INDRD_START_RESET 0x0
4547 /* Extracts the ALT_QSPI_INDRD_START field value from a register. */
4548 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
4549 /* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */
4550 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
4551 
4552 /*
4553  * Field : Cancel Indirect Read - cancel
4554  *
4555  * Writing a 1 to this bit will cancel all ongoing indirect read operations.
4556  *
4557  * Field Enumeration Values:
4558  *
4559  * Enum | Value | Description
4560  * :---------------------------------|:------|:----------------------------
4561  * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read
4562  * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read
4563  *
4564  * Field Access Macros:
4565  *
4566  */
4567 /*
4568  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
4569  *
4570  * Do Not Cancel Indirect Read
4571  */
4572 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
4573 /*
4574  * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
4575  *
4576  * Cancel Indirect Read
4577  */
4578 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
4579 
4580 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
4581 #define ALT_QSPI_INDRD_CANCEL_LSB 1
4582 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
4583 #define ALT_QSPI_INDRD_CANCEL_MSB 1
4584 /* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */
4585 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
4586 /* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */
4587 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
4588 /* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */
4589 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
4590 /* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */
4591 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
4592 /* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */
4593 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4594 /* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */
4595 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4596 
4597 /*
4598  * Field : Indirect Read Status - rd_status
4599  *
4600  * Indirect read operation in progress (status)
4601  *
4602  * Field Enumeration Values:
4603  *
4604  * Enum | Value | Description
4605  * :------------------------------------|:------|:------------------------------
4606  * ALT_QSPI_INDRD_RD_STATUS_E_NOACTION | 0x0 | No read operation in progress
4607  * ALT_QSPI_INDRD_RD_STATUS_E_READOP | 0x1 | Read Operation in progress
4608  *
4609  * Field Access Macros:
4610  *
4611  */
4612 /*
4613  * Enumerated value for register field ALT_QSPI_INDRD_RD_STATUS
4614  *
4615  * No read operation in progress
4616  */
4617 #define ALT_QSPI_INDRD_RD_STATUS_E_NOACTION 0x0
4618 /*
4619  * Enumerated value for register field ALT_QSPI_INDRD_RD_STATUS
4620  *
4621  * Read Operation in progress
4622  */
4623 #define ALT_QSPI_INDRD_RD_STATUS_E_READOP 0x1
4624 
4625 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STATUS register field. */
4626 #define ALT_QSPI_INDRD_RD_STATUS_LSB 2
4627 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STATUS register field. */
4628 #define ALT_QSPI_INDRD_RD_STATUS_MSB 2
4629 /* The width in bits of the ALT_QSPI_INDRD_RD_STATUS register field. */
4630 #define ALT_QSPI_INDRD_RD_STATUS_WIDTH 1
4631 /* The mask used to set the ALT_QSPI_INDRD_RD_STATUS register field value. */
4632 #define ALT_QSPI_INDRD_RD_STATUS_SET_MSK 0x00000004
4633 /* The mask used to clear the ALT_QSPI_INDRD_RD_STATUS register field value. */
4634 #define ALT_QSPI_INDRD_RD_STATUS_CLR_MSK 0xfffffffb
4635 /* The reset value of the ALT_QSPI_INDRD_RD_STATUS register field. */
4636 #define ALT_QSPI_INDRD_RD_STATUS_RESET 0x0
4637 /* Extracts the ALT_QSPI_INDRD_RD_STATUS field value from a register. */
4638 #define ALT_QSPI_INDRD_RD_STATUS_GET(value) (((value) & 0x00000004) >> 2)
4639 /* Produces a ALT_QSPI_INDRD_RD_STATUS register field value suitable for setting the register. */
4640 #define ALT_QSPI_INDRD_RD_STATUS_SET(value) (((value) << 2) & 0x00000004)
4641 
4642 /*
4643  * Field : SRAM Full - sram_full
4644  *
4645  * SRAM full and unable to immediately complete an indirect operation. Write a 1 to
4646  * this field to clear it."; indirect operation (status)
4647  *
4648  * Field Enumeration Values:
4649  *
4650  * Enum | Value | Description
4651  * :------------------------------------|:------|:-----------------------------------
4652  * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full
4653  * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation
4654  *
4655  * Field Access Macros:
4656  *
4657  */
4658 /*
4659  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
4660  *
4661  * SRram Not Full
4662  */
4663 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4664 /*
4665  * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
4666  *
4667  * Sram Full- Cant complete operation
4668  */
4669 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4670 
4671 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4672 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4673 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4674 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4675 /* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4676 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4677 /* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4678 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4679 /* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */
4680 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4681 /* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field. */
4682 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4683 /* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */
4684 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4685 /* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */
4686 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4687 
4688 /*
4689  * Field : Queued Indirect Read Operations - rd_queued
4690  *
4691  * Two indirect read operations have been queued
4692  *
4693  * Field Enumeration Values:
4694  *
4695  * Enum | Value | Description
4696  * :----------------------------------------|:------|:---------------------
4697  * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read
4698  * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read
4699  *
4700  * Field Access Macros:
4701  *
4702  */
4703 /*
4704  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4705  *
4706  * No Queued Read
4707  */
4708 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4709 /*
4710  * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
4711  *
4712  * Queued Indirect Read
4713  */
4714 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4715 
4716 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4717 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4718 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4719 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4720 /* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4721 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4722 /* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4723 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4724 /* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */
4725 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4726 /* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field. */
4727 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4728 /* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */
4729 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4730 /* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */
4731 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4732 
4733 /*
4734  * Field : Indirect Completion Status - ind_ops_done_status
4735  *
4736  * This field is set to 1 when an indirect operation has completed. Write a 1 to
4737  * this field to clear it.
4738  *
4739  * Field Enumeration Values:
4740  *
4741  * Enum | Value | Description
4742  * :----------------------------------------------|:------|:-------------------------------
4743  * ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_NOACTION | 0x0 | Indirect Op Not Complete
4744  * ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_INDCOMP | 0x1 | Indirect Op Complete operation
4745  *
4746  * Field Access Macros:
4747  *
4748  */
4749 /*
4750  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STATUS
4751  *
4752  * Indirect Op Not Complete
4753  */
4754 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_NOACTION 0x0
4755 /*
4756  * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STATUS
4757  *
4758  * Indirect Op Complete operation
4759  */
4760 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_E_INDCOMP 0x1
4761 
4762 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field. */
4763 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_LSB 5
4764 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field. */
4765 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_MSB 5
4766 /* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field. */
4767 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_WIDTH 1
4768 /* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field value. */
4769 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_SET_MSK 0x00000020
4770 /* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field value. */
4771 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_CLR_MSK 0xffffffdf
4772 /* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field. */
4773 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_RESET 0x0
4774 /* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STATUS field value from a register. */
4775 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_GET(value) (((value) & 0x00000020) >> 5)
4776 /* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STATUS register field value suitable for setting the register. */
4777 #define ALT_QSPI_INDRD_IND_OPS_DONE_STATUS_SET(value) (((value) << 5) & 0x00000020)
4778 
4779 /*
4780  * Field : Completed Indirect Operations - num_ind_ops_done
4781  *
4782  * This field contains the number of indirect operations which have been completed.
4783  * This is used in conjunction with the indirect completion status field (bit 5).
4784  * It is incremented by hardware when an indirect operation has completed. Write a
4785  * 1 to bit 5 of this register to decrement it.
4786  *
4787  * Field Access Macros:
4788  *
4789  */
4790 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4791 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4792 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4793 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4794 /* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4795 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4796 /* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4797 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4798 /* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
4799 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4800 /* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
4801 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4802 /* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */
4803 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4804 /* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */
4805 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4806 
4807 /*
4808  * Field : Reserved - indir_rd_xfer_resv_fld
4809  *
4810  * Field Access Macros:
4811  *
4812  */
4813 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4814 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_LSB 8
4815 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4816 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_MSB 31
4817 /* The width in bits of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4818 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_WIDTH 24
4819 /* The mask used to set the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value. */
4820 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET_MSK 0xffffff00
4821 /* The mask used to clear the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value. */
4822 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_CLR_MSK 0x000000ff
4823 /* The reset value of the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field. */
4824 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_RESET 0x0
4825 /* Extracts the ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD field value from a register. */
4826 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
4827 /* Produces a ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD register field value suitable for setting the register. */
4828 #define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
4829 
4830 #ifndef __ASSEMBLY__
4831 /*
4832  * WARNING: The C register and register group struct declarations are provided for
4833  * convenience and illustrative purposes. They should, however, be used with
4834  * caution as the C language standard provides no guarantees about the alignment or
4835  * atomicity of device memory accesses. The recommended practice for coding device
4836  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4837  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4838  * alt_write_dword() functions for 64 bit registers.
4839  *
4840  * The struct declaration for register ALT_QSPI_INDRD.
4841  */
4842 struct ALT_QSPI_INDRD_s
4843 {
4844  volatile uint32_t start : 1; /* Start Indirect Read */
4845  volatile uint32_t cancel : 1; /* Cancel Indirect Read */
4846  const volatile uint32_t rd_status : 1; /* Indirect Read Status */
4847  volatile uint32_t sram_full : 1; /* SRAM Full */
4848  const volatile uint32_t rd_queued : 1; /* Queued Indirect Read Operations */
4849  volatile uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */
4850  const volatile uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */
4851  const volatile uint32_t indir_rd_xfer_resv_fld : 24; /* Reserved */
4852 };
4853 
4854 /* The typedef declaration for register ALT_QSPI_INDRD. */
4855 typedef struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4856 #endif /* __ASSEMBLY__ */
4857 
4858 /* The reset value of the ALT_QSPI_INDRD register. */
4859 #define ALT_QSPI_INDRD_RESET 0x00000000
4860 /* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */
4861 #define ALT_QSPI_INDRD_OFST 0x60
4862 /* The address of the ALT_QSPI_INDRD register. */
4863 #define ALT_QSPI_INDRD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRD_OFST))
4864 
4865 /*
4866  * Register : Indirect Read Transfer Watermark Register - indrdwater
4867  *
4868  * Register Layout
4869  *
4870  * Bits | Access | Reset | Description
4871  * :-------|:-------|:------|:----------------
4872  * [31:0] | RW | 0x0 | Watermark Value
4873  *
4874  */
4875 /*
4876  * Field : Watermark Value - level
4877  *
4878  * This represents the minimum fill level of the SRAM before a DMA peripheral
4879  * access is permitted. When the SRAM fill level passes the watermark, an interrupt
4880  * is also generated. This field can be disabled by writing a value of all zeroes.
4881  *
4882  * Field Access Macros:
4883  *
4884  */
4885 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4886 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4887 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4888 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4889 /* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4890 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4891 /* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4892 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4893 /* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */
4894 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4895 /* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */
4896 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4897 /* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */
4898 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4899 /* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */
4900 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4901 
4902 #ifndef __ASSEMBLY__
4903 /*
4904  * WARNING: The C register and register group struct declarations are provided for
4905  * convenience and illustrative purposes. They should, however, be used with
4906  * caution as the C language standard provides no guarantees about the alignment or
4907  * atomicity of device memory accesses. The recommended practice for coding device
4908  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4909  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4910  * alt_write_dword() functions for 64 bit registers.
4911  *
4912  * The struct declaration for register ALT_QSPI_INDRDWATER.
4913  */
4914 struct ALT_QSPI_INDRDWATER_s
4915 {
4916  volatile uint32_t level : 32; /* Watermark Value */
4917 };
4918 
4919 /* The typedef declaration for register ALT_QSPI_INDRDWATER. */
4920 typedef struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
4921 #endif /* __ASSEMBLY__ */
4922 
4923 /* The reset value of the ALT_QSPI_INDRDWATER register. */
4924 #define ALT_QSPI_INDRDWATER_RESET 0x00000000
4925 /* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */
4926 #define ALT_QSPI_INDRDWATER_OFST 0x64
4927 /* The address of the ALT_QSPI_INDRDWATER register. */
4928 #define ALT_QSPI_INDRDWATER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDWATER_OFST))
4929 
4930 /*
4931  * Register : Indirect Read Transfer Start Address Register - indrdstaddr
4932  *
4933  * Register Layout
4934  *
4935  * Bits | Access | Reset | Description
4936  * :-------|:-------|:------|:-------------------------
4937  * [31:0] | RW | 0x0 | Start of Indirect Access
4938  *
4939  */
4940 /*
4941  * Field : Start of Indirect Access - addr
4942  *
4943  * This is the start address from which the indirect access will commence its READ
4944  * operation.
4945  *
4946  * Field Access Macros:
4947  *
4948  */
4949 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4950 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4951 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4952 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4953 /* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4954 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4955 /* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4956 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4957 /* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
4958 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4959 /* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
4960 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4961 /* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */
4962 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4963 /* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */
4964 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4965 
4966 #ifndef __ASSEMBLY__
4967 /*
4968  * WARNING: The C register and register group struct declarations are provided for
4969  * convenience and illustrative purposes. They should, however, be used with
4970  * caution as the C language standard provides no guarantees about the alignment or
4971  * atomicity of device memory accesses. The recommended practice for coding device
4972  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4973  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4974  * alt_write_dword() functions for 64 bit registers.
4975  *
4976  * The struct declaration for register ALT_QSPI_INDRDSTADDR.
4977  */
4978 struct ALT_QSPI_INDRDSTADDR_s
4979 {
4980  volatile uint32_t addr : 32; /* Start of Indirect Access */
4981 };
4982 
4983 /* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */
4984 typedef struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
4985 #endif /* __ASSEMBLY__ */
4986 
4987 /* The reset value of the ALT_QSPI_INDRDSTADDR register. */
4988 #define ALT_QSPI_INDRDSTADDR_RESET 0x00000000
4989 /* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */
4990 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4991 /* The address of the ALT_QSPI_INDRDSTADDR register. */
4992 #define ALT_QSPI_INDRDSTADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDSTADDR_OFST))
4993 
4994 /*
4995  * Register : Indirect Read Transfer Number Bytes Register - indrdcnt
4996  *
4997  * Register Layout
4998  *
4999  * Bits | Access | Reset | Description
5000  * :-------|:-------|:------|:-------------------------
5001  * [31:0] | RW | 0x0 | Indirect Number of Bytes
5002  *
5003  */
5004 /*
5005  * Field : Indirect Number of Bytes - value
5006  *
5007  * This is the number of bytes that the indirect access will consume. This can be
5008  * bigger than the configured size of SRAM.
5009  *
5010  * Field Access Macros:
5011  *
5012  */
5013 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
5014 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
5015 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
5016 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
5017 /* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */
5018 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
5019 /* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */
5020 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
5021 /* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */
5022 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
5023 /* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */
5024 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
5025 /* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */
5026 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5027 /* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */
5028 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5029 
5030 #ifndef __ASSEMBLY__
5031 /*
5032  * WARNING: The C register and register group struct declarations are provided for
5033  * convenience and illustrative purposes. They should, however, be used with
5034  * caution as the C language standard provides no guarantees about the alignment or
5035  * atomicity of device memory accesses. The recommended practice for coding device
5036  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5037  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5038  * alt_write_dword() functions for 64 bit registers.
5039  *
5040  * The struct declaration for register ALT_QSPI_INDRDCNT.
5041  */
5042 struct ALT_QSPI_INDRDCNT_s
5043 {
5044  volatile uint32_t value : 32; /* Indirect Number of Bytes */
5045 };
5046 
5047 /* The typedef declaration for register ALT_QSPI_INDRDCNT. */
5048 typedef struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
5049 #endif /* __ASSEMBLY__ */
5050 
5051 /* The reset value of the ALT_QSPI_INDRDCNT register. */
5052 #define ALT_QSPI_INDRDCNT_RESET 0x00000000
5053 /* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */
5054 #define ALT_QSPI_INDRDCNT_OFST 0x6c
5055 /* The address of the ALT_QSPI_INDRDCNT register. */
5056 #define ALT_QSPI_INDRDCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDRDCNT_OFST))
5057 
5058 /*
5059  * Register : Indirect Write Transfer Control Register - indwr
5060  *
5061  * Register Layout
5062  *
5063  * Bits | Access | Reset | Description
5064  * :-------|:-------|:------|:---------------------------------
5065  * [0] | W | 0x0 | Start Indirect Write
5066  * [1] | W | 0x0 | Cancel Indirect Write
5067  * [2] | R | 0x0 | Indirect Write Status
5068  * [3] | R | 0x0 | Reserved
5069  * [4] | R | 0x0 | Queued Indirect Write Operations
5070  * [5] | RW | 0x0 | Indirect Completion Status
5071  * [7:6] | R | 0x0 | Completed Indirect Operations
5072  * [31:8] | R | 0x0 | Reserved
5073  *
5074  */
5075 /*
5076  * Field : Start Indirect Write - start
5077  *
5078  * Writing a 1 to this bit will trigger an indirect write operation. The assumption
5079  * is that the indirect start address and the indirect number of bytes register is
5080  * setup before triggering the indirect write operation.
5081  *
5082  * Field Enumeration Values:
5083  *
5084  * Enum | Value | Description
5085  * :--------------------------------|:------|:---------------------------------
5086  * ALT_QSPI_INDWR_START_E_DISABLED | 0x0 | No Action
5087  * ALT_QSPI_INDWR_START_E_ENABLED | 0x1 | Trigger indirect write operation
5088  *
5089  * Field Access Macros:
5090  *
5091  */
5092 /*
5093  * Enumerated value for register field ALT_QSPI_INDWR_START
5094  *
5095  * No Action
5096  */
5097 #define ALT_QSPI_INDWR_START_E_DISABLED 0x0
5098 /*
5099  * Enumerated value for register field ALT_QSPI_INDWR_START
5100  *
5101  * Trigger indirect write operation
5102  */
5103 #define ALT_QSPI_INDWR_START_E_ENABLED 0x1
5104 
5105 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */
5106 #define ALT_QSPI_INDWR_START_LSB 0
5107 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */
5108 #define ALT_QSPI_INDWR_START_MSB 0
5109 /* The width in bits of the ALT_QSPI_INDWR_START register field. */
5110 #define ALT_QSPI_INDWR_START_WIDTH 1
5111 /* The mask used to set the ALT_QSPI_INDWR_START register field value. */
5112 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
5113 /* The mask used to clear the ALT_QSPI_INDWR_START register field value. */
5114 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
5115 /* The reset value of the ALT_QSPI_INDWR_START register field. */
5116 #define ALT_QSPI_INDWR_START_RESET 0x0
5117 /* Extracts the ALT_QSPI_INDWR_START field value from a register. */
5118 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
5119 /* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */
5120 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
5121 
5122 /*
5123  * Field : Cancel Indirect Write - cancel
5124  *
5125  * Writing a 1 to this bit will cancel all ongoing indirect write operations.
5126  *
5127  * Field Enumeration Values:
5128  *
5129  * Enum | Value | Description
5130  * :-----------------------------------|:------|:--------------------------------
5131  * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action
5132  * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation
5133  *
5134  * Field Access Macros:
5135  *
5136  */
5137 /*
5138  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
5139  *
5140  * No Action
5141  */
5142 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
5143 /*
5144  * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
5145  *
5146  * Cancel Indirect write operation
5147  */
5148 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
5149 
5150 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
5151 #define ALT_QSPI_INDWR_CANCEL_LSB 1
5152 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
5153 #define ALT_QSPI_INDWR_CANCEL_MSB 1
5154 /* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */
5155 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
5156 /* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */
5157 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
5158 /* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */
5159 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
5160 /* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */
5161 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
5162 /* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */
5163 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
5164 /* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */
5165 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
5166 
5167 /*
5168  * Field : Indirect Write Status - rdstat
5169  *
5170  * Indirect write operation in progress (status)
5171  *
5172  * Field Enumeration Values:
5173  *
5174  * Enum | Value | Description
5175  * :----------------------------------|:------|:-------------------------
5176  * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action
5177  * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation
5178  *
5179  * Field Access Macros:
5180  *
5181  */
5182 /*
5183  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
5184  *
5185  * No Action
5186  */
5187 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
5188 /*
5189  * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
5190  *
5191  * Indirect write operation
5192  */
5193 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
5194 
5195 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
5196 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
5197 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
5198 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
5199 /* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */
5200 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
5201 /* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */
5202 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
5203 /* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */
5204 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
5205 /* The reset value of the ALT_QSPI_INDWR_RDSTAT register field. */
5206 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
5207 /* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */
5208 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
5209 /* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */
5210 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
5211 
5212 /*
5213  * Field : Reserved - indir_wr_rsvd_fld
5214  *
5215  * Field Access Macros:
5216  *
5217  */
5218 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5219 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_LSB 3
5220 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5221 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_MSB 3
5222 /* The width in bits of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5223 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_WIDTH 1
5224 /* The mask used to set the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value. */
5225 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET_MSK 0x00000008
5226 /* The mask used to clear the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value. */
5227 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_CLR_MSK 0xfffffff7
5228 /* The reset value of the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field. */
5229 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_RESET 0x0
5230 /* Extracts the ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD field value from a register. */
5231 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_GET(value) (((value) & 0x00000008) >> 3)
5232 /* Produces a ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD register field value suitable for setting the register. */
5233 #define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET(value) (((value) << 3) & 0x00000008)
5234 
5235 /*
5236  * Field : Queued Indirect Write Operations - rdqueued
5237  *
5238  * Two indirect write operations have been queued
5239  *
5240  * Field Enumeration Values:
5241  *
5242  * Enum | Value | Description
5243  * :-----------------------------------|:------|:-----------------------------
5244  * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action
5245  * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation
5246  *
5247  * Field Access Macros:
5248  *
5249  */
5250 /*
5251  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
5252  *
5253  * No Action
5254  */
5255 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
5256 /*
5257  * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
5258  *
5259  * Two Indirect write operation
5260  */
5261 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
5262 
5263 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
5264 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
5265 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
5266 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
5267 /* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */
5268 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
5269 /* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */
5270 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
5271 /* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */
5272 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
5273 /* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field. */
5274 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
5275 /* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */
5276 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
5277 /* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */
5278 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
5279 
5280 /*
5281  * Field : Indirect Completion Status - inddone
5282  *
5283  * This field is set to 1 when an indirect operation has completed. Write a 1 to
5284  * this field to clear it.
5285  *
5286  * Field Enumeration Values:
5287  *
5288  * Enum | Value | Description
5289  * :-----------------------------------|:------|:-----------------------------
5290  * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action
5291  * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed
5292  *
5293  * Field Access Macros:
5294  *
5295  */
5296 /*
5297  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
5298  *
5299  * No Action
5300  */
5301 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
5302 /*
5303  * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
5304  *
5305  * Indirect operation completed
5306  */
5307 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
5308 
5309 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
5310 #define ALT_QSPI_INDWR_INDDONE_LSB 5
5311 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
5312 #define ALT_QSPI_INDWR_INDDONE_MSB 5
5313 /* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */
5314 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
5315 /* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */
5316 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
5317 /* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */
5318 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
5319 /* The reset value of the ALT_QSPI_INDWR_INDDONE register field. */
5320 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
5321 /* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */
5322 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
5323 /* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */
5324 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
5325 
5326 /*
5327  * Field : Completed Indirect Operations - indcnt
5328  *
5329  * This field contains the number of indirect operations which have been completed.
5330  * This is used in conjunction with the indirect completion status field (bit 5).
5331  * It is incremented by hardware when an indirect operation has completed. Write a
5332  * 1 to bit 5 of this register to decrement it.
5333  *
5334  * Field Access Macros:
5335  *
5336  */
5337 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
5338 #define ALT_QSPI_INDWR_INDCNT_LSB 6
5339 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
5340 #define ALT_QSPI_INDWR_INDCNT_MSB 7
5341 /* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */
5342 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
5343 /* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */
5344 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
5345 /* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */
5346 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
5347 /* The reset value of the ALT_QSPI_INDWR_INDCNT register field. */
5348 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
5349 /* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */
5350 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
5351 /* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */
5352 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
5353 
5354 /*
5355  * Field : Reserved - indir_wr_xfer_resv2_fld
5356  *
5357  * Field Access Macros:
5358  *
5359  */
5360 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5361 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_LSB 8
5362 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5363 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_MSB 31
5364 /* The width in bits of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5365 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_WIDTH 24
5366 /* The mask used to set the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value. */
5367 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET_MSK 0xffffff00
5368 /* The mask used to clear the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value. */
5369 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_CLR_MSK 0x000000ff
5370 /* The reset value of the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field. */
5371 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_RESET 0x0
5372 /* Extracts the ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD field value from a register. */
5373 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_GET(value) (((value) & 0xffffff00) >> 8)
5374 /* Produces a ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD register field value suitable for setting the register. */
5375 #define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET(value) (((value) << 8) & 0xffffff00)
5376 
5377 #ifndef __ASSEMBLY__
5378 /*
5379  * WARNING: The C register and register group struct declarations are provided for
5380  * convenience and illustrative purposes. They should, however, be used with
5381  * caution as the C language standard provides no guarantees about the alignment or
5382  * atomicity of device memory accesses. The recommended practice for coding device
5383  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5384  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5385  * alt_write_dword() functions for 64 bit registers.
5386  *
5387  * The struct declaration for register ALT_QSPI_INDWR.
5388  */
5389 struct ALT_QSPI_INDWR_s
5390 {
5391  volatile uint32_t start : 1; /* Start Indirect Write */
5392  volatile uint32_t cancel : 1; /* Cancel Indirect Write */
5393  const volatile uint32_t rdstat : 1; /* Indirect Write Status */
5394  const volatile uint32_t indir_wr_rsvd_fld : 1; /* Reserved */
5395  const volatile uint32_t rdqueued : 1; /* Queued Indirect Write Operations */
5396  volatile uint32_t inddone : 1; /* Indirect Completion Status */
5397  const volatile uint32_t indcnt : 2; /* Completed Indirect Operations */
5398  const volatile uint32_t indir_wr_xfer_resv2_fld : 24; /* Reserved */
5399 };
5400 
5401 /* The typedef declaration for register ALT_QSPI_INDWR. */
5402 typedef struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
5403 #endif /* __ASSEMBLY__ */
5404 
5405 /* The reset value of the ALT_QSPI_INDWR register. */
5406 #define ALT_QSPI_INDWR_RESET 0x00000000
5407 /* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */
5408 #define ALT_QSPI_INDWR_OFST 0x70
5409 /* The address of the ALT_QSPI_INDWR register. */
5410 #define ALT_QSPI_INDWR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWR_OFST))
5411 
5412 /*
5413  * Register : Indirect Write Transfer Watermark Register - indwrwater
5414  *
5415  * Register Layout
5416  *
5417  * Bits | Access | Reset | Description
5418  * :-------|:-------|:-----------|:----------------
5419  * [31:0] | RW | 0xffffffff | Watermark Value
5420  *
5421  */
5422 /*
5423  * Field : Watermark Value - level
5424  *
5425  * This represents the maximum fill level of the SRAM before a DMA peripheral
5426  * access is permitted. When the SRAM fill level falls below the watermark, an
5427  * interrupt is also generated. This field can be disabled by writing a value of
5428  * all ones.
5429  *
5430  * Field Access Macros:
5431  *
5432  */
5433 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5434 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
5435 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5436 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
5437 /* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5438 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
5439 /* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */
5440 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
5441 /* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */
5442 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
5443 /* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */
5444 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
5445 /* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */
5446 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
5447 /* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */
5448 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
5449 
5450 #ifndef __ASSEMBLY__
5451 /*
5452  * WARNING: The C register and register group struct declarations are provided for
5453  * convenience and illustrative purposes. They should, however, be used with
5454  * caution as the C language standard provides no guarantees about the alignment or
5455  * atomicity of device memory accesses. The recommended practice for coding device
5456  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5457  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5458  * alt_write_dword() functions for 64 bit registers.
5459  *
5460  * The struct declaration for register ALT_QSPI_INDWRWATER.
5461  */
5462 struct ALT_QSPI_INDWRWATER_s
5463 {
5464  volatile uint32_t level : 32; /* Watermark Value */
5465 };
5466 
5467 /* The typedef declaration for register ALT_QSPI_INDWRWATER. */
5468 typedef struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
5469 #endif /* __ASSEMBLY__ */
5470 
5471 /* The reset value of the ALT_QSPI_INDWRWATER register. */
5472 #define ALT_QSPI_INDWRWATER_RESET 0xffffffff
5473 /* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */
5474 #define ALT_QSPI_INDWRWATER_OFST 0x74
5475 /* The address of the ALT_QSPI_INDWRWATER register. */
5476 #define ALT_QSPI_INDWRWATER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRWATER_OFST))
5477 
5478 /*
5479  * Register : Indirect Write Transfer Start Address Register - indwrstaddr
5480  *
5481  * Register Layout
5482  *
5483  * Bits | Access | Reset | Description
5484  * :-------|:-------|:------|:-------------------------
5485  * [31:0] | RW | 0x0 | Start of Indirect Access
5486  *
5487  */
5488 /*
5489  * Field : Start of Indirect Access - addr
5490  *
5491  * This is the start address from which the indirect access will commence its READ
5492  * operation.
5493  *
5494  * Field Access Macros:
5495  *
5496  */
5497 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5498 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
5499 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5500 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
5501 /* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5502 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
5503 /* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
5504 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
5505 /* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
5506 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
5507 /* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
5508 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
5509 /* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */
5510 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5511 /* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */
5512 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5513 
5514 #ifndef __ASSEMBLY__
5515 /*
5516  * WARNING: The C register and register group struct declarations are provided for
5517  * convenience and illustrative purposes. They should, however, be used with
5518  * caution as the C language standard provides no guarantees about the alignment or
5519  * atomicity of device memory accesses. The recommended practice for coding device
5520  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5521  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5522  * alt_write_dword() functions for 64 bit registers.
5523  *
5524  * The struct declaration for register ALT_QSPI_INDWRSTADDR.
5525  */
5526 struct ALT_QSPI_INDWRSTADDR_s
5527 {
5528  volatile uint32_t addr : 32; /* Start of Indirect Access */
5529 };
5530 
5531 /* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */
5532 typedef struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
5533 #endif /* __ASSEMBLY__ */
5534 
5535 /* The reset value of the ALT_QSPI_INDWRSTADDR register. */
5536 #define ALT_QSPI_INDWRSTADDR_RESET 0x00000000
5537 /* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */
5538 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
5539 /* The address of the ALT_QSPI_INDWRSTADDR register. */
5540 #define ALT_QSPI_INDWRSTADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRSTADDR_OFST))
5541 
5542 /*
5543  * Register : Indirect Write Transfer Number Bytes Register - indwrcnt
5544  *
5545  * Register Layout
5546  *
5547  * Bits | Access | Reset | Description
5548  * :-------|:-------|:------|:-------------------------
5549  * [31:0] | RW | 0x0 | Indirect Number of Bytes
5550  *
5551  */
5552 /*
5553  * Field : Indirect Number of Bytes - value
5554  *
5555  * This is the number of bytes that the indirect access will consume. This can be
5556  * bigger than the configured size of SRAM.
5557  *
5558  * Field Access Macros:
5559  *
5560  */
5561 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
5562 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
5563 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
5564 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
5565 /* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */
5566 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
5567 /* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */
5568 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
5569 /* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */
5570 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
5571 /* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */
5572 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
5573 /* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */
5574 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5575 /* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */
5576 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5577 
5578 #ifndef __ASSEMBLY__
5579 /*
5580  * WARNING: The C register and register group struct declarations are provided for
5581  * convenience and illustrative purposes. They should, however, be used with
5582  * caution as the C language standard provides no guarantees about the alignment or
5583  * atomicity of device memory accesses. The recommended practice for coding device
5584  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5585  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5586  * alt_write_dword() functions for 64 bit registers.
5587  *
5588  * The struct declaration for register ALT_QSPI_INDWRCNT.
5589  */
5590 struct ALT_QSPI_INDWRCNT_s
5591 {
5592  volatile uint32_t value : 32; /* Indirect Number of Bytes */
5593 };
5594 
5595 /* The typedef declaration for register ALT_QSPI_INDWRCNT. */
5596 typedef struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
5597 #endif /* __ASSEMBLY__ */
5598 
5599 /* The reset value of the ALT_QSPI_INDWRCNT register. */
5600 #define ALT_QSPI_INDWRCNT_RESET 0x00000000
5601 /* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */
5602 #define ALT_QSPI_INDWRCNT_OFST 0x7c
5603 /* The address of the ALT_QSPI_INDWRCNT register. */
5604 #define ALT_QSPI_INDWRCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_INDWRCNT_OFST))
5605 
5606 /*
5607  * Register : Flash Command Control Register - flashcmd
5608  *
5609  * Register Layout
5610  *
5611  * Bits | Access | Reset | Description
5612  * :--------|:-------|:------|:---------------------------
5613  * [0] | W | 0x0 | Execute Command
5614  * [1] | R | 0x0 | Command Execution Status
5615  * [6:2] | R | 0x0 | Reserved
5616  * [11:7] | RW | 0x0 | Number of Dummy Bytes
5617  * [14:12] | RW | 0x0 | Number of Write Data Bytes
5618  * [15] | RW | 0x0 | Write Data Enable
5619  * [17:16] | RW | 0x0 | Number of Address Bytes
5620  * [18] | RW | 0x0 | Mode Bit Enable
5621  * [19] | RW | 0x0 | Command Address Enable
5622  * [22:20] | RW | 0x0 | Number of Read Data Bytes
5623  * [23] | RW | 0x0 | Read Data Enable
5624  * [31:24] | RW | 0x0 | Command Opcode
5625  *
5626  */
5627 /*
5628  * Field : Execute Command - execcmd
5629  *
5630  * Execute the command.
5631  *
5632  * Field Enumeration Values:
5633  *
5634  * Enum | Value | Description
5635  * :-------------------------------------|:------|:----------------
5636  * ALT_QSPI_FLASHCMD_EXECCMD_E_NOACTION | 0x0 | No Action
5637  * ALT_QSPI_FLASHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command
5638  *
5639  * Field Access Macros:
5640  *
5641  */
5642 /*
5643  * Enumerated value for register field ALT_QSPI_FLASHCMD_EXECCMD
5644  *
5645  * No Action
5646  */
5647 #define ALT_QSPI_FLASHCMD_EXECCMD_E_NOACTION 0x0
5648 /*
5649  * Enumerated value for register field ALT_QSPI_FLASHCMD_EXECCMD
5650  *
5651  * Execute Command
5652  */
5653 #define ALT_QSPI_FLASHCMD_EXECCMD_E_EXECUTE 0x1
5654 
5655 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_EXECCMD register field. */
5656 #define ALT_QSPI_FLASHCMD_EXECCMD_LSB 0
5657 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_EXECCMD register field. */
5658 #define ALT_QSPI_FLASHCMD_EXECCMD_MSB 0
5659 /* The width in bits of the ALT_QSPI_FLASHCMD_EXECCMD register field. */
5660 #define ALT_QSPI_FLASHCMD_EXECCMD_WIDTH 1
5661 /* The mask used to set the ALT_QSPI_FLASHCMD_EXECCMD register field value. */
5662 #define ALT_QSPI_FLASHCMD_EXECCMD_SET_MSK 0x00000001
5663 /* The mask used to clear the ALT_QSPI_FLASHCMD_EXECCMD register field value. */
5664 #define ALT_QSPI_FLASHCMD_EXECCMD_CLR_MSK 0xfffffffe
5665 /* The reset value of the ALT_QSPI_FLASHCMD_EXECCMD register field. */
5666 #define ALT_QSPI_FLASHCMD_EXECCMD_RESET 0x0
5667 /* Extracts the ALT_QSPI_FLASHCMD_EXECCMD field value from a register. */
5668 #define ALT_QSPI_FLASHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
5669 /* Produces a ALT_QSPI_FLASHCMD_EXECCMD register field value suitable for setting the register. */
5670 #define ALT_QSPI_FLASHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
5671 
5672 /*
5673  * Field : Command Execution Status - cmdexecstat
5674  *
5675  * Command execution in progress.
5676  *
5677  * Field Enumeration Values:
5678  *
5679  * Enum | Value | Description
5680  * :--------------------------------------------|:------|:-------------------------
5681  * ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action
5682  * ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status
5683  *
5684  * Field Access Macros:
5685  *
5686  */
5687 /*
5688  * Enumerated value for register field ALT_QSPI_FLASHCMD_CMDEXECSTAT
5689  *
5690  * No Action
5691  */
5692 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_NOACTION 0x0
5693 /*
5694  * Enumerated value for register field ALT_QSPI_FLASHCMD_CMDEXECSTAT
5695  *
5696  * Command Execution Status
5697  */
5698 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
5699 
5700 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field. */
5701 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_LSB 1
5702 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field. */
5703 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_MSB 1
5704 /* The width in bits of the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field. */
5705 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_WIDTH 1
5706 /* The mask used to set the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field value. */
5707 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_SET_MSK 0x00000002
5708 /* The mask used to clear the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field value. */
5709 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
5710 /* The reset value of the ALT_QSPI_FLASHCMD_CMDEXECSTAT register field. */
5711 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_RESET 0x0
5712 /* Extracts the ALT_QSPI_FLASHCMD_CMDEXECSTAT field value from a register. */
5713 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
5714 /* Produces a ALT_QSPI_FLASHCMD_CMDEXECSTAT register field value suitable for setting the register. */
5715 #define ALT_QSPI_FLASHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
5716 
5717 /*
5718  * Field : Reserved - flash_cmd_cntrl_resv1_fld
5719  *
5720  * Field Access Macros:
5721  *
5722  */
5723 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field. */
5724 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_LSB 2
5725 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field. */
5726 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_MSB 6
5727 /* The width in bits of the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field. */
5728 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_WIDTH 5
5729 /* The mask used to set the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field value. */
5730 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_SET_MSK 0x0000007c
5731 /* The mask used to clear the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field value. */
5732 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_CLR_MSK 0xffffff83
5733 /* The reset value of the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field. */
5734 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_RESET 0x0
5735 /* Extracts the ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD field value from a register. */
5736 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_GET(value) (((value) & 0x0000007c) >> 2)
5737 /* Produces a ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD register field value suitable for setting the register. */
5738 #define ALT_QSPI_FLASHCMD_FLASH_CMD_CNTRL_RESV1_FLD_SET(value) (((value) << 2) & 0x0000007c)
5739 
5740 /*
5741  * Field : Number of Dummy Bytes - numdummybytes
5742  *
5743  * Set to the number of dummy bytes required This should be setup before triggering
5744  * the command via the execute field of this register.
5745  *
5746  * Field Access Macros:
5747  *
5748  */
5749 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field. */
5750 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_LSB 7
5751 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field. */
5752 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_MSB 11
5753 /* The width in bits of the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field. */
5754 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_WIDTH 5
5755 /* The mask used to set the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field value. */
5756 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
5757 /* The mask used to clear the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field value. */
5758 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
5759 /* The reset value of the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field. */
5760 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_RESET 0x0
5761 /* Extracts the ALT_QSPI_FLASHCMD_NUMDUMMYBYTES field value from a register. */
5762 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
5763 /* Produces a ALT_QSPI_FLASHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */
5764 #define ALT_QSPI_FLASHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5765 
5766 /*
5767  * Field : Number of Write Data Bytes - numwrdatabytes
5768  *
5769  * Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for
5770  * 8 bytes.
5771  *
5772  * Field Enumeration Values:
5773  *
5774  * Enum | Value | Description
5775  * :-------------------------------------------|:------|:-------------
5776  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte
5777  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte
5778  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte
5779  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte
5780  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte
5781  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte
5782  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte
5783  * ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte
5784  *
5785  * Field Access Macros:
5786  *
5787  */
5788 /*
5789  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5790  *
5791  * Write 1 Byte
5792  */
5793 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5794 /*
5795  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5796  *
5797  * Write 2 Byte
5798  */
5799 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5800 /*
5801  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5802  *
5803  * Write 3 Byte
5804  */
5805 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5806 /*
5807  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5808  *
5809  * Write 4 Byte
5810  */
5811 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5812 /*
5813  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5814  *
5815  * Write 5 Byte
5816  */
5817 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5818 /*
5819  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5820  *
5821  * Write 6 Byte
5822  */
5823 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5824 /*
5825  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5826  *
5827  * Write 7 Byte
5828  */
5829 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5830 /*
5831  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMWRDATABYTES
5832  *
5833  * Write 8 Byte
5834  */
5835 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5836 
5837 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field. */
5838 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_LSB 12
5839 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field. */
5840 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_MSB 14
5841 /* The width in bits of the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field. */
5842 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_WIDTH 3
5843 /* The mask used to set the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field value. */
5844 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5845 /* The mask used to clear the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field value. */
5846 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5847 /* The reset value of the ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field. */
5848 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_RESET 0x0
5849 /* Extracts the ALT_QSPI_FLASHCMD_NUMWRDATABYTES field value from a register. */
5850 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5851 /* Produces a ALT_QSPI_FLASHCMD_NUMWRDATABYTES register field value suitable for setting the register. */
5852 #define ALT_QSPI_FLASHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5853 
5854 /*
5855  * Field : Write Data Enable - enwrdata
5856  *
5857  * Set to 1 if the command specified in the command opcode field requires write
5858  * data bytes to be sent to the device.
5859  *
5860  * Field Enumeration Values:
5861  *
5862  * Enum | Value | Description
5863  * :-----------------------------------------|:------|:----------------------------------
5864  * ALT_QSPI_FLASHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action
5865  * ALT_QSPI_FLASHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes
5866  *
5867  * Field Access Macros:
5868  *
5869  */
5870 /*
5871  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENWRDATA
5872  *
5873  * No Action
5874  */
5875 #define ALT_QSPI_FLASHCMD_ENWRDATA_E_NOACTION 0x0
5876 /*
5877  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENWRDATA
5878  *
5879  * Command requires write data bytes
5880  */
5881 #define ALT_QSPI_FLASHCMD_ENWRDATA_E_WRDATABYTES 0x1
5882 
5883 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_ENWRDATA register field. */
5884 #define ALT_QSPI_FLASHCMD_ENWRDATA_LSB 15
5885 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_ENWRDATA register field. */
5886 #define ALT_QSPI_FLASHCMD_ENWRDATA_MSB 15
5887 /* The width in bits of the ALT_QSPI_FLASHCMD_ENWRDATA register field. */
5888 #define ALT_QSPI_FLASHCMD_ENWRDATA_WIDTH 1
5889 /* The mask used to set the ALT_QSPI_FLASHCMD_ENWRDATA register field value. */
5890 #define ALT_QSPI_FLASHCMD_ENWRDATA_SET_MSK 0x00008000
5891 /* The mask used to clear the ALT_QSPI_FLASHCMD_ENWRDATA register field value. */
5892 #define ALT_QSPI_FLASHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5893 /* The reset value of the ALT_QSPI_FLASHCMD_ENWRDATA register field. */
5894 #define ALT_QSPI_FLASHCMD_ENWRDATA_RESET 0x0
5895 /* Extracts the ALT_QSPI_FLASHCMD_ENWRDATA field value from a register. */
5896 #define ALT_QSPI_FLASHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5897 /* Produces a ALT_QSPI_FLASHCMD_ENWRDATA register field value suitable for setting the register. */
5898 #define ALT_QSPI_FLASHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5899 
5900 /*
5901  * Field : Number of Address Bytes - numaddrbytes
5902  *
5903  * Set to the number of address bytes required (the address itself is programmed in
5904  * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the
5905  * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address
5906  * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
5907  *
5908  * Field Enumeration Values:
5909  *
5910  * Enum | Value | Description
5911  * :-------------------------------------------|:------|:----------------------
5912  * ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte
5913  * ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes
5914  * ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes
5915  * ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes
5916  *
5917  * Field Access Macros:
5918  *
5919  */
5920 /*
5921  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMADDRBYTES
5922  *
5923  * Write 1 Address Byte
5924  */
5925 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5926 /*
5927  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMADDRBYTES
5928  *
5929  * Write 2 Address Bytes
5930  */
5931 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5932 /*
5933  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMADDRBYTES
5934  *
5935  * Write 3 Address Bytes
5936  */
5937 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5938 /*
5939  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMADDRBYTES
5940  *
5941  * Write 4 Address Bytes
5942  */
5943 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5944 
5945 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field. */
5946 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_LSB 16
5947 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field. */
5948 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_MSB 17
5949 /* The width in bits of the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field. */
5950 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_WIDTH 2
5951 /* The mask used to set the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field value. */
5952 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5953 /* The mask used to clear the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field value. */
5954 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5955 /* The reset value of the ALT_QSPI_FLASHCMD_NUMADDRBYTES register field. */
5956 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_RESET 0x0
5957 /* Extracts the ALT_QSPI_FLASHCMD_NUMADDRBYTES field value from a register. */
5958 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5959 /* Produces a ALT_QSPI_FLASHCMD_NUMADDRBYTES register field value suitable for setting the register. */
5960 #define ALT_QSPI_FLASHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5961 
5962 /*
5963  * Field : Mode Bit Enable - enmodebit
5964  *
5965  * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration
5966  * register are sent following the address bytes.
5967  *
5968  * Field Enumeration Values:
5969  *
5970  * Enum | Value | Description
5971  * :---------------------------------------|:------|:-------------------------------
5972  * ALT_QSPI_FLASHCMD_ENMODEBIT_E_DISABLED | 0x0 | No Action
5973  * ALT_QSPI_FLASHCMD_ENMODEBIT_E_ENABLED | 0x1 | Mode Bit follows address bytes
5974  *
5975  * Field Access Macros:
5976  *
5977  */
5978 /*
5979  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENMODEBIT
5980  *
5981  * No Action
5982  */
5983 #define ALT_QSPI_FLASHCMD_ENMODEBIT_E_DISABLED 0x0
5984 /*
5985  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENMODEBIT
5986  *
5987  * Mode Bit follows address bytes
5988  */
5989 #define ALT_QSPI_FLASHCMD_ENMODEBIT_E_ENABLED 0x1
5990 
5991 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_ENMODEBIT register field. */
5992 #define ALT_QSPI_FLASHCMD_ENMODEBIT_LSB 18
5993 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_ENMODEBIT register field. */
5994 #define ALT_QSPI_FLASHCMD_ENMODEBIT_MSB 18
5995 /* The width in bits of the ALT_QSPI_FLASHCMD_ENMODEBIT register field. */
5996 #define ALT_QSPI_FLASHCMD_ENMODEBIT_WIDTH 1
5997 /* The mask used to set the ALT_QSPI_FLASHCMD_ENMODEBIT register field value. */
5998 #define ALT_QSPI_FLASHCMD_ENMODEBIT_SET_MSK 0x00040000
5999 /* The mask used to clear the ALT_QSPI_FLASHCMD_ENMODEBIT register field value. */
6000 #define ALT_QSPI_FLASHCMD_ENMODEBIT_CLR_MSK 0xfffbffff
6001 /* The reset value of the ALT_QSPI_FLASHCMD_ENMODEBIT register field. */
6002 #define ALT_QSPI_FLASHCMD_ENMODEBIT_RESET 0x0
6003 /* Extracts the ALT_QSPI_FLASHCMD_ENMODEBIT field value from a register. */
6004 #define ALT_QSPI_FLASHCMD_ENMODEBIT_GET(value) (((value) & 0x00040000) >> 18)
6005 /* Produces a ALT_QSPI_FLASHCMD_ENMODEBIT register field value suitable for setting the register. */
6006 #define ALT_QSPI_FLASHCMD_ENMODEBIT_SET(value) (((value) << 18) & 0x00040000)
6007 
6008 /*
6009  * Field : Command Address Enable - encmdaddr
6010  *
6011  * Set to 1 if the command specified in bits 31:24 requires an address. This should
6012  * be setup before triggering the command via writing a 1 to the execute field.
6013  *
6014  * Field Enumeration Values:
6015  *
6016  * Enum | Value | Description
6017  * :---------------------------------------|:------|:---------------------------------------
6018  * ALT_QSPI_FLASHCMD_ENCMDADDR_E_DISABLED | 0x0 | No Action
6019  * ALT_QSPI_FLASHCMD_ENCMDADDR_E_ENABLED | 0x1 | Command in bits 31:24 requires address
6020  *
6021  * Field Access Macros:
6022  *
6023  */
6024 /*
6025  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENCMDADDR
6026  *
6027  * No Action
6028  */
6029 #define ALT_QSPI_FLASHCMD_ENCMDADDR_E_DISABLED 0x0
6030 /*
6031  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENCMDADDR
6032  *
6033  * Command in bits 31:24 requires address
6034  */
6035 #define ALT_QSPI_FLASHCMD_ENCMDADDR_E_ENABLED 0x1
6036 
6037 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_ENCMDADDR register field. */
6038 #define ALT_QSPI_FLASHCMD_ENCMDADDR_LSB 19
6039 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_ENCMDADDR register field. */
6040 #define ALT_QSPI_FLASHCMD_ENCMDADDR_MSB 19
6041 /* The width in bits of the ALT_QSPI_FLASHCMD_ENCMDADDR register field. */
6042 #define ALT_QSPI_FLASHCMD_ENCMDADDR_WIDTH 1
6043 /* The mask used to set the ALT_QSPI_FLASHCMD_ENCMDADDR register field value. */
6044 #define ALT_QSPI_FLASHCMD_ENCMDADDR_SET_MSK 0x00080000
6045 /* The mask used to clear the ALT_QSPI_FLASHCMD_ENCMDADDR register field value. */
6046 #define ALT_QSPI_FLASHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
6047 /* The reset value of the ALT_QSPI_FLASHCMD_ENCMDADDR register field. */
6048 #define ALT_QSPI_FLASHCMD_ENCMDADDR_RESET 0x0
6049 /* Extracts the ALT_QSPI_FLASHCMD_ENCMDADDR field value from a register. */
6050 #define ALT_QSPI_FLASHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
6051 /* Produces a ALT_QSPI_FLASHCMD_ENCMDADDR register field value suitable for setting the register. */
6052 #define ALT_QSPI_FLASHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
6053 
6054 /*
6055  * Field : Number of Read Data Bytes - numrddatabytes
6056  *
6057  * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for
6058  * 8 bytes.
6059  *
6060  * Field Enumeration Values:
6061  *
6062  * Enum | Value | Description
6063  * :-------------------------------------------|:------|:------------
6064  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte
6065  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte
6066  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte
6067  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte
6068  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte
6069  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte
6070  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte
6071  * ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte
6072  *
6073  * Field Access Macros:
6074  *
6075  */
6076 /*
6077  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6078  *
6079  * Read 1 Byte
6080  */
6081 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
6082 /*
6083  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6084  *
6085  * Read 2 Byte
6086  */
6087 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
6088 /*
6089  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6090  *
6091  * Read 3 Byte
6092  */
6093 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
6094 /*
6095  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6096  *
6097  * Read 4 Byte
6098  */
6099 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
6100 /*
6101  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6102  *
6103  * Read 5 Byte
6104  */
6105 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
6106 /*
6107  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6108  *
6109  * Read 6 Byte
6110  */
6111 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
6112 /*
6113  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6114  *
6115  * Read 7 Byte
6116  */
6117 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
6118 /*
6119  * Enumerated value for register field ALT_QSPI_FLASHCMD_NUMRDDATABYTES
6120  *
6121  * Read 8 Byte
6122  */
6123 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
6124 
6125 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field. */
6126 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_LSB 20
6127 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field. */
6128 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_MSB 22
6129 /* The width in bits of the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field. */
6130 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_WIDTH 3
6131 /* The mask used to set the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field value. */
6132 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
6133 /* The mask used to clear the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field value. */
6134 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
6135 /* The reset value of the ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field. */
6136 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_RESET 0x0
6137 /* Extracts the ALT_QSPI_FLASHCMD_NUMRDDATABYTES field value from a register. */
6138 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
6139 /* Produces a ALT_QSPI_FLASHCMD_NUMRDDATABYTES register field value suitable for setting the register. */
6140 #define ALT_QSPI_FLASHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
6141 
6142 /*
6143  * Field : Read Data Enable - enrddata
6144  *
6145  * Set to 1 if the command specified in the command opcode field (bits 31:24)
6146  * requires read data bytes to be received from the device.
6147  *
6148  * Field Enumeration Values:
6149  *
6150  * Enum | Value | Description
6151  * :--------------------------------------|:------|:---------------------------
6152  * ALT_QSPI_FLASHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action
6153  * ALT_QSPI_FLASHCMD_ENRDDATA_E_ENABLE | 0x1 | Command Requires read data
6154  *
6155  * Field Access Macros:
6156  *
6157  */
6158 /*
6159  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENRDDATA
6160  *
6161  * No Action
6162  */
6163 #define ALT_QSPI_FLASHCMD_ENRDDATA_E_NOACTION 0x0
6164 /*
6165  * Enumerated value for register field ALT_QSPI_FLASHCMD_ENRDDATA
6166  *
6167  * Command Requires read data
6168  */
6169 #define ALT_QSPI_FLASHCMD_ENRDDATA_E_ENABLE 0x1
6170 
6171 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_ENRDDATA register field. */
6172 #define ALT_QSPI_FLASHCMD_ENRDDATA_LSB 23
6173 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_ENRDDATA register field. */
6174 #define ALT_QSPI_FLASHCMD_ENRDDATA_MSB 23
6175 /* The width in bits of the ALT_QSPI_FLASHCMD_ENRDDATA register field. */
6176 #define ALT_QSPI_FLASHCMD_ENRDDATA_WIDTH 1
6177 /* The mask used to set the ALT_QSPI_FLASHCMD_ENRDDATA register field value. */
6178 #define ALT_QSPI_FLASHCMD_ENRDDATA_SET_MSK 0x00800000
6179 /* The mask used to clear the ALT_QSPI_FLASHCMD_ENRDDATA register field value. */
6180 #define ALT_QSPI_FLASHCMD_ENRDDATA_CLR_MSK 0xff7fffff
6181 /* The reset value of the ALT_QSPI_FLASHCMD_ENRDDATA register field. */
6182 #define ALT_QSPI_FLASHCMD_ENRDDATA_RESET 0x0
6183 /* Extracts the ALT_QSPI_FLASHCMD_ENRDDATA field value from a register. */
6184 #define ALT_QSPI_FLASHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
6185 /* Produces a ALT_QSPI_FLASHCMD_ENRDDATA register field value suitable for setting the register. */
6186 #define ALT_QSPI_FLASHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
6187 
6188 /*
6189  * Field : Command Opcode - cmdopcode
6190  *
6191  * The command opcode field should be setup before triggering the command. For
6192  * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of
6193  * this register launches the command. NOTE : Using this approach to issue commands
6194  * to the device will make use of the instruction type of the device instruction
6195  * configuration register. If this field is set to 2'b00, then the command opcode,
6196  * command address, command dummy bytes and command data will all be transferred in
6197  * a serial fashion. If this field is set to 2'b01, then the command opcode,
6198  * command address, command dummy bytes and command data will all be transferred in
6199  * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command
6200  * opcode, command address, command dummy bytes and command data will all be
6201  * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
6202  *
6203  * Field Access Macros:
6204  *
6205  */
6206 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMD_CMDOPCODE register field. */
6207 #define ALT_QSPI_FLASHCMD_CMDOPCODE_LSB 24
6208 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMD_CMDOPCODE register field. */
6209 #define ALT_QSPI_FLASHCMD_CMDOPCODE_MSB 31
6210 /* The width in bits of the ALT_QSPI_FLASHCMD_CMDOPCODE register field. */
6211 #define ALT_QSPI_FLASHCMD_CMDOPCODE_WIDTH 8
6212 /* The mask used to set the ALT_QSPI_FLASHCMD_CMDOPCODE register field value. */
6213 #define ALT_QSPI_FLASHCMD_CMDOPCODE_SET_MSK 0xff000000
6214 /* The mask used to clear the ALT_QSPI_FLASHCMD_CMDOPCODE register field value. */
6215 #define ALT_QSPI_FLASHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
6216 /* The reset value of the ALT_QSPI_FLASHCMD_CMDOPCODE register field. */
6217 #define ALT_QSPI_FLASHCMD_CMDOPCODE_RESET 0x0
6218 /* Extracts the ALT_QSPI_FLASHCMD_CMDOPCODE field value from a register. */
6219 #define ALT_QSPI_FLASHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
6220 /* Produces a ALT_QSPI_FLASHCMD_CMDOPCODE register field value suitable for setting the register. */
6221 #define ALT_QSPI_FLASHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
6222 
6223 #ifndef __ASSEMBLY__
6224 /*
6225  * WARNING: The C register and register group struct declarations are provided for
6226  * convenience and illustrative purposes. They should, however, be used with
6227  * caution as the C language standard provides no guarantees about the alignment or
6228  * atomicity of device memory accesses. The recommended practice for coding device
6229  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6230  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6231  * alt_write_dword() functions for 64 bit registers.
6232  *
6233  * The struct declaration for register ALT_QSPI_FLASHCMD.
6234  */
6235 struct ALT_QSPI_FLASHCMD_s
6236 {
6237  volatile uint32_t execcmd : 1; /* Execute Command */
6238  const volatile uint32_t cmdexecstat : 1; /* Command Execution Status */
6239  const volatile uint32_t flash_cmd_cntrl_resv1_fld : 5; /* Reserved */
6240  volatile uint32_t numdummybytes : 5; /* Number of Dummy Bytes */
6241  volatile uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */
6242  volatile uint32_t enwrdata : 1; /* Write Data Enable */
6243  volatile uint32_t numaddrbytes : 2; /* Number of Address Bytes */
6244  volatile uint32_t enmodebit : 1; /* Mode Bit Enable */
6245  volatile uint32_t encmdaddr : 1; /* Command Address Enable */
6246  volatile uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */
6247  volatile uint32_t enrddata : 1; /* Read Data Enable */
6248  volatile uint32_t cmdopcode : 8; /* Command Opcode */
6249 };
6250 
6251 /* The typedef declaration for register ALT_QSPI_FLASHCMD. */
6252 typedef struct ALT_QSPI_FLASHCMD_s ALT_QSPI_FLASHCMD_t;
6253 #endif /* __ASSEMBLY__ */
6254 
6255 /* The reset value of the ALT_QSPI_FLASHCMD register. */
6256 #define ALT_QSPI_FLASHCMD_RESET 0x00000000
6257 /* The byte offset of the ALT_QSPI_FLASHCMD register from the beginning of the component. */
6258 #define ALT_QSPI_FLASHCMD_OFST 0x90
6259 /* The address of the ALT_QSPI_FLASHCMD register. */
6260 #define ALT_QSPI_FLASHCMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMD_OFST))
6261 
6262 /*
6263  * Register : Flash Command Address Registers - flashcmdaddr
6264  *
6265  * Register Layout
6266  *
6267  * Bits | Access | Reset | Description
6268  * :-------|:-------|:------|:----------------
6269  * [31:0] | RW | 0x0 | Command Address
6270  *
6271  */
6272 /*
6273  * Field : Command Address - addr
6274  *
6275  * This should be setup before triggering the command with execute field (bit 0) of
6276  * the Flash Command Control register. It is the address used by the command
6277  * specified in the opcode field (bits 31:24) of the Flash Command Control
6278  * register.
6279  *
6280  * Field Access Macros:
6281  *
6282  */
6283 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMDADDR_ADDR register field. */
6284 #define ALT_QSPI_FLASHCMDADDR_ADDR_LSB 0
6285 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMDADDR_ADDR register field. */
6286 #define ALT_QSPI_FLASHCMDADDR_ADDR_MSB 31
6287 /* The width in bits of the ALT_QSPI_FLASHCMDADDR_ADDR register field. */
6288 #define ALT_QSPI_FLASHCMDADDR_ADDR_WIDTH 32
6289 /* The mask used to set the ALT_QSPI_FLASHCMDADDR_ADDR register field value. */
6290 #define ALT_QSPI_FLASHCMDADDR_ADDR_SET_MSK 0xffffffff
6291 /* The mask used to clear the ALT_QSPI_FLASHCMDADDR_ADDR register field value. */
6292 #define ALT_QSPI_FLASHCMDADDR_ADDR_CLR_MSK 0x00000000
6293 /* The reset value of the ALT_QSPI_FLASHCMDADDR_ADDR register field. */
6294 #define ALT_QSPI_FLASHCMDADDR_ADDR_RESET 0x0
6295 /* Extracts the ALT_QSPI_FLASHCMDADDR_ADDR field value from a register. */
6296 #define ALT_QSPI_FLASHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
6297 /* Produces a ALT_QSPI_FLASHCMDADDR_ADDR register field value suitable for setting the register. */
6298 #define ALT_QSPI_FLASHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
6299 
6300 #ifndef __ASSEMBLY__
6301 /*
6302  * WARNING: The C register and register group struct declarations are provided for
6303  * convenience and illustrative purposes. They should, however, be used with
6304  * caution as the C language standard provides no guarantees about the alignment or
6305  * atomicity of device memory accesses. The recommended practice for coding device
6306  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6307  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6308  * alt_write_dword() functions for 64 bit registers.
6309  *
6310  * The struct declaration for register ALT_QSPI_FLASHCMDADDR.
6311  */
6312 struct ALT_QSPI_FLASHCMDADDR_s
6313 {
6314  volatile uint32_t addr : 32; /* Command Address */
6315 };
6316 
6317 /* The typedef declaration for register ALT_QSPI_FLASHCMDADDR. */
6318 typedef struct ALT_QSPI_FLASHCMDADDR_s ALT_QSPI_FLASHCMDADDR_t;
6319 #endif /* __ASSEMBLY__ */
6320 
6321 /* The reset value of the ALT_QSPI_FLASHCMDADDR register. */
6322 #define ALT_QSPI_FLASHCMDADDR_RESET 0x00000000
6323 /* The byte offset of the ALT_QSPI_FLASHCMDADDR register from the beginning of the component. */
6324 #define ALT_QSPI_FLASHCMDADDR_OFST 0x94
6325 /* The address of the ALT_QSPI_FLASHCMDADDR register. */
6326 #define ALT_QSPI_FLASHCMDADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDADDR_OFST))
6327 
6328 /*
6329  * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo
6330  *
6331  * Register Layout
6332  *
6333  * Bits | Access | Reset | Description
6334  * :-------|:-------|:------|:-------------------------------
6335  * [31:0] | RW | 0x0 | Command Read Data (Lower byte)
6336  *
6337  */
6338 /*
6339  * Field : Command Read Data (Lower byte) - data
6340  *
6341  * This is the data that is returned by the flash device for any status or
6342  * configuration read operation carried out by triggering the event in the control
6343  * register. The register will be valid when the polling bit in the control
6344  * register is low.
6345  *
6346  * Field Access Macros:
6347  *
6348  */
6349 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMDRDDATALO_DATA register field. */
6350 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_LSB 0
6351 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMDRDDATALO_DATA register field. */
6352 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_MSB 31
6353 /* The width in bits of the ALT_QSPI_FLASHCMDRDDATALO_DATA register field. */
6354 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_WIDTH 32
6355 /* The mask used to set the ALT_QSPI_FLASHCMDRDDATALO_DATA register field value. */
6356 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_SET_MSK 0xffffffff
6357 /* The mask used to clear the ALT_QSPI_FLASHCMDRDDATALO_DATA register field value. */
6358 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_CLR_MSK 0x00000000
6359 /* The reset value of the ALT_QSPI_FLASHCMDRDDATALO_DATA register field. */
6360 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_RESET 0x0
6361 /* Extracts the ALT_QSPI_FLASHCMDRDDATALO_DATA field value from a register. */
6362 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6363 /* Produces a ALT_QSPI_FLASHCMDRDDATALO_DATA register field value suitable for setting the register. */
6364 #define ALT_QSPI_FLASHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6365 
6366 #ifndef __ASSEMBLY__
6367 /*
6368  * WARNING: The C register and register group struct declarations are provided for
6369  * convenience and illustrative purposes. They should, however, be used with
6370  * caution as the C language standard provides no guarantees about the alignment or
6371  * atomicity of device memory accesses. The recommended practice for coding device
6372  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6373  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6374  * alt_write_dword() functions for 64 bit registers.
6375  *
6376  * The struct declaration for register ALT_QSPI_FLASHCMDRDDATALO.
6377  */
6378 struct ALT_QSPI_FLASHCMDRDDATALO_s
6379 {
6380  volatile uint32_t data : 32; /* Command Read Data (Lower byte) */
6381 };
6382 
6383 /* The typedef declaration for register ALT_QSPI_FLASHCMDRDDATALO. */
6384 typedef struct ALT_QSPI_FLASHCMDRDDATALO_s ALT_QSPI_FLASHCMDRDDATALO_t;
6385 #endif /* __ASSEMBLY__ */
6386 
6387 /* The reset value of the ALT_QSPI_FLASHCMDRDDATALO register. */
6388 #define ALT_QSPI_FLASHCMDRDDATALO_RESET 0x00000000
6389 /* The byte offset of the ALT_QSPI_FLASHCMDRDDATALO register from the beginning of the component. */
6390 #define ALT_QSPI_FLASHCMDRDDATALO_OFST 0xa0
6391 /* The address of the ALT_QSPI_FLASHCMDRDDATALO register. */
6392 #define ALT_QSPI_FLASHCMDRDDATALO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDRDDATALO_OFST))
6393 
6394 /*
6395  * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup
6396  *
6397  * Device Instruction Configuration Register
6398  *
6399  * Register Layout
6400  *
6401  * Bits | Access | Reset | Description
6402  * :-------|:-------|:------|:-------------------------------
6403  * [31:0] | RW | 0x0 | Command Read Data (Upper byte)
6404  *
6405  */
6406 /*
6407  * Field : Command Read Data (Upper byte) - data
6408  *
6409  * This is the data that is returned by the FLASH device for any status or
6410  * configuration read operation carried out by triggering the event in the control
6411  * register. The register will be valid when the polling bit in the control
6412  * register is low.
6413  *
6414  * Field Access Macros:
6415  *
6416  */
6417 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field. */
6418 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_LSB 0
6419 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field. */
6420 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_MSB 31
6421 /* The width in bits of the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field. */
6422 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_WIDTH 32
6423 /* The mask used to set the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field value. */
6424 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
6425 /* The mask used to clear the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field value. */
6426 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
6427 /* The reset value of the ALT_QSPI_FLASHCMDRDDATAUP_DATA register field. */
6428 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_RESET 0x0
6429 /* Extracts the ALT_QSPI_FLASHCMDRDDATAUP_DATA field value from a register. */
6430 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6431 /* Produces a ALT_QSPI_FLASHCMDRDDATAUP_DATA register field value suitable for setting the register. */
6432 #define ALT_QSPI_FLASHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6433 
6434 #ifndef __ASSEMBLY__
6435 /*
6436  * WARNING: The C register and register group struct declarations are provided for
6437  * convenience and illustrative purposes. They should, however, be used with
6438  * caution as the C language standard provides no guarantees about the alignment or
6439  * atomicity of device memory accesses. The recommended practice for coding device
6440  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6441  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6442  * alt_write_dword() functions for 64 bit registers.
6443  *
6444  * The struct declaration for register ALT_QSPI_FLASHCMDRDDATAUP.
6445  */
6446 struct ALT_QSPI_FLASHCMDRDDATAUP_s
6447 {
6448  volatile uint32_t data : 32; /* Command Read Data (Upper byte) */
6449 };
6450 
6451 /* The typedef declaration for register ALT_QSPI_FLASHCMDRDDATAUP. */
6452 typedef struct ALT_QSPI_FLASHCMDRDDATAUP_s ALT_QSPI_FLASHCMDRDDATAUP_t;
6453 #endif /* __ASSEMBLY__ */
6454 
6455 /* The reset value of the ALT_QSPI_FLASHCMDRDDATAUP register. */
6456 #define ALT_QSPI_FLASHCMDRDDATAUP_RESET 0x00000000
6457 /* The byte offset of the ALT_QSPI_FLASHCMDRDDATAUP register from the beginning of the component. */
6458 #define ALT_QSPI_FLASHCMDRDDATAUP_OFST 0xa4
6459 /* The address of the ALT_QSPI_FLASHCMDRDDATAUP register. */
6460 #define ALT_QSPI_FLASHCMDRDDATAUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDRDDATAUP_OFST))
6461 
6462 /*
6463  * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo
6464  *
6465  * Register Layout
6466  *
6467  * Bits | Access | Reset | Description
6468  * :-------|:-------|:------|:------------------------------
6469  * [31:0] | RW | 0x0 | Command Write Data Lower Byte
6470  *
6471  */
6472 /*
6473  * Field : Command Write Data Lower Byte - data
6474  *
6475  * This is the command write data lower byte. This should be setup before
6476  * triggering the command with execute field (bit 0) of the Flash Command Control
6477  * register. It is the data that is to be written to the flash for any status or
6478  * configuration write operation carried out by triggering the event in the Flash
6479  * Command Control register.
6480  *
6481  * Field Access Macros:
6482  *
6483  */
6484 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMDWRDATALO_DATA register field. */
6485 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_LSB 0
6486 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMDWRDATALO_DATA register field. */
6487 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_MSB 31
6488 /* The width in bits of the ALT_QSPI_FLASHCMDWRDATALO_DATA register field. */
6489 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_WIDTH 32
6490 /* The mask used to set the ALT_QSPI_FLASHCMDWRDATALO_DATA register field value. */
6491 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_SET_MSK 0xffffffff
6492 /* The mask used to clear the ALT_QSPI_FLASHCMDWRDATALO_DATA register field value. */
6493 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_CLR_MSK 0x00000000
6494 /* The reset value of the ALT_QSPI_FLASHCMDWRDATALO_DATA register field. */
6495 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_RESET 0x0
6496 /* Extracts the ALT_QSPI_FLASHCMDWRDATALO_DATA field value from a register. */
6497 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6498 /* Produces a ALT_QSPI_FLASHCMDWRDATALO_DATA register field value suitable for setting the register. */
6499 #define ALT_QSPI_FLASHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6500 
6501 #ifndef __ASSEMBLY__
6502 /*
6503  * WARNING: The C register and register group struct declarations are provided for
6504  * convenience and illustrative purposes. They should, however, be used with
6505  * caution as the C language standard provides no guarantees about the alignment or
6506  * atomicity of device memory accesses. The recommended practice for coding device
6507  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6508  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6509  * alt_write_dword() functions for 64 bit registers.
6510  *
6511  * The struct declaration for register ALT_QSPI_FLASHCMDWRDATALO.
6512  */
6513 struct ALT_QSPI_FLASHCMDWRDATALO_s
6514 {
6515  volatile uint32_t data : 32; /* Command Write Data Lower Byte */
6516 };
6517 
6518 /* The typedef declaration for register ALT_QSPI_FLASHCMDWRDATALO. */
6519 typedef struct ALT_QSPI_FLASHCMDWRDATALO_s ALT_QSPI_FLASHCMDWRDATALO_t;
6520 #endif /* __ASSEMBLY__ */
6521 
6522 /* The reset value of the ALT_QSPI_FLASHCMDWRDATALO register. */
6523 #define ALT_QSPI_FLASHCMDWRDATALO_RESET 0x00000000
6524 /* The byte offset of the ALT_QSPI_FLASHCMDWRDATALO register from the beginning of the component. */
6525 #define ALT_QSPI_FLASHCMDWRDATALO_OFST 0xa8
6526 /* The address of the ALT_QSPI_FLASHCMDWRDATALO register. */
6527 #define ALT_QSPI_FLASHCMDWRDATALO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDWRDATALO_OFST))
6528 
6529 /*
6530  * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup
6531  *
6532  * Register Layout
6533  *
6534  * Bits | Access | Reset | Description
6535  * :-------|:-------|:------|:------------------------------
6536  * [31:0] | RW | 0x0 | Command Write Data Upper Byte
6537  *
6538  */
6539 /*
6540  * Field : Command Write Data Upper Byte - data
6541  *
6542  * This is the command write data upper byte. This should be setup before
6543  * triggering the command with execute field (bit 0) of the Flash Command Control
6544  * register. It is the data that is to be written to the flash for any status or
6545  * configuration write operation carried out by triggering the event in the Flash
6546  * Command Control register.
6547  *
6548  * Field Access Macros:
6549  *
6550  */
6551 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field. */
6552 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_LSB 0
6553 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field. */
6554 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_MSB 31
6555 /* The width in bits of the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field. */
6556 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_WIDTH 32
6557 /* The mask used to set the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field value. */
6558 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
6559 /* The mask used to clear the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field value. */
6560 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
6561 /* The reset value of the ALT_QSPI_FLASHCMDWRDATAUP_DATA register field. */
6562 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_RESET 0x0
6563 /* Extracts the ALT_QSPI_FLASHCMDWRDATAUP_DATA field value from a register. */
6564 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6565 /* Produces a ALT_QSPI_FLASHCMDWRDATAUP_DATA register field value suitable for setting the register. */
6566 #define ALT_QSPI_FLASHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6567 
6568 #ifndef __ASSEMBLY__
6569 /*
6570  * WARNING: The C register and register group struct declarations are provided for
6571  * convenience and illustrative purposes. They should, however, be used with
6572  * caution as the C language standard provides no guarantees about the alignment or
6573  * atomicity of device memory accesses. The recommended practice for coding device
6574  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6575  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6576  * alt_write_dword() functions for 64 bit registers.
6577  *
6578  * The struct declaration for register ALT_QSPI_FLASHCMDWRDATAUP.
6579  */
6580 struct ALT_QSPI_FLASHCMDWRDATAUP_s
6581 {
6582  volatile uint32_t data : 32; /* Command Write Data Upper Byte */
6583 };
6584 
6585 /* The typedef declaration for register ALT_QSPI_FLASHCMDWRDATAUP. */
6586 typedef struct ALT_QSPI_FLASHCMDWRDATAUP_s ALT_QSPI_FLASHCMDWRDATAUP_t;
6587 #endif /* __ASSEMBLY__ */
6588 
6589 /* The reset value of the ALT_QSPI_FLASHCMDWRDATAUP register. */
6590 #define ALT_QSPI_FLASHCMDWRDATAUP_RESET 0x00000000
6591 /* The byte offset of the ALT_QSPI_FLASHCMDWRDATAUP register from the beginning of the component. */
6592 #define ALT_QSPI_FLASHCMDWRDATAUP_OFST 0xac
6593 /* The address of the ALT_QSPI_FLASHCMDWRDATAUP register. */
6594 #define ALT_QSPI_FLASHCMDWRDATAUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_FLASHCMDWRDATAUP_OFST))
6595 
6596 /*
6597  * Register : Module ID Register - moduleid
6598  *
6599  * Register Layout
6600  *
6601  * Bits | Access | Reset | Description
6602  * :--------|:-------|:-------|:-----------------
6603  * [24:0] | R | 0x1001 | Module ID number
6604  * [31:25] | R | 0x0 | Reserved
6605  *
6606  */
6607 /*
6608  * Field : Module ID number - value
6609  *
6610  * Field Access Macros:
6611  *
6612  */
6613 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
6614 #define ALT_QSPI_MODULEID_VALUE_LSB 0
6615 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
6616 #define ALT_QSPI_MODULEID_VALUE_MSB 24
6617 /* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */
6618 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
6619 /* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */
6620 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
6621 /* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */
6622 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
6623 /* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */
6624 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
6625 /* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */
6626 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
6627 /* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */
6628 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
6629 
6630 /*
6631  * Field : Reserved - mod_id_resv_fld
6632  *
6633  * Field Access Macros:
6634  *
6635  */
6636 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6637 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_LSB 25
6638 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6639 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_MSB 31
6640 /* The width in bits of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6641 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_WIDTH 7
6642 /* The mask used to set the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value. */
6643 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET_MSK 0xfe000000
6644 /* The mask used to clear the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value. */
6645 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_CLR_MSK 0x01ffffff
6646 /* The reset value of the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field. */
6647 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_RESET 0x0
6648 /* Extracts the ALT_QSPI_MODULEID_MOD_ID_RESV_FLD field value from a register. */
6649 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_GET(value) (((value) & 0xfe000000) >> 25)
6650 /* Produces a ALT_QSPI_MODULEID_MOD_ID_RESV_FLD register field value suitable for setting the register. */
6651 #define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET(value) (((value) << 25) & 0xfe000000)
6652 
6653 #ifndef __ASSEMBLY__
6654 /*
6655  * WARNING: The C register and register group struct declarations are provided for
6656  * convenience and illustrative purposes. They should, however, be used with
6657  * caution as the C language standard provides no guarantees about the alignment or
6658  * atomicity of device memory accesses. The recommended practice for coding device
6659  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6660  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6661  * alt_write_dword() functions for 64 bit registers.
6662  *
6663  * The struct declaration for register ALT_QSPI_MODULEID.
6664  */
6665 struct ALT_QSPI_MODULEID_s
6666 {
6667  const volatile uint32_t value : 25; /* Module ID number */
6668  const volatile uint32_t mod_id_resv_fld : 7; /* Reserved */
6669 };
6670 
6671 /* The typedef declaration for register ALT_QSPI_MODULEID. */
6672 typedef struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
6673 #endif /* __ASSEMBLY__ */
6674 
6675 /* The reset value of the ALT_QSPI_MODULEID register. */
6676 #define ALT_QSPI_MODULEID_RESET 0x00001001
6677 /* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */
6678 #define ALT_QSPI_MODULEID_OFST 0xfc
6679 /* The address of the ALT_QSPI_MODULEID register. */
6680 #define ALT_QSPI_MODULEID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_QSPI_MODULEID_OFST))
6681 
6682 #ifndef __ASSEMBLY__
6683 /*
6684  * WARNING: The C register and register group struct declarations are provided for
6685  * convenience and illustrative purposes. They should, however, be used with
6686  * caution as the C language standard provides no guarantees about the alignment or
6687  * atomicity of device memory accesses. The recommended practice for coding device
6688  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6689  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6690  * alt_write_dword() functions for 64 bit registers.
6691  *
6692  * The struct declaration for register group ALT_QSPI.
6693  */
6694 struct ALT_QSPI_s
6695 {
6696  volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */
6697  volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */
6698  volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */
6699  volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */
6700  volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */
6701  volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */
6702  volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */
6703  volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
6704  volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */
6705  volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */
6706  volatile ALT_QSPI_MODEBIT_t modebit; /* ALT_QSPI_MODEBIT */
6707  volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */
6708  volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */
6709  volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */
6710  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
6711  volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */
6712  volatile ALT_QSPI_IRQMASK_t irqmask; /* ALT_QSPI_IRQMASK */
6713  volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
6714  volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
6715  volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
6716  volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */
6717  volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
6718  volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */
6719  volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */
6720  volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
6721  volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */
6722  volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */
6723  volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */
6724  volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
6725  volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */
6726  volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
6727  volatile ALT_QSPI_FLASHCMD_t flashcmd; /* ALT_QSPI_FLASHCMD */
6728  volatile ALT_QSPI_FLASHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLASHCMDADDR */
6729  volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
6730  volatile ALT_QSPI_FLASHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLASHCMDRDDATALO */
6731  volatile ALT_QSPI_FLASHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLASHCMDRDDATAUP */
6732  volatile ALT_QSPI_FLASHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLASHCMDWRDATALO */
6733  volatile ALT_QSPI_FLASHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLASHCMDWRDATAUP */
6734  volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
6735  volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */
6736 };
6737 
6738 /* The typedef declaration for register group ALT_QSPI. */
6739 typedef struct ALT_QSPI_s ALT_QSPI_t;
6740 /* The struct declaration for the raw register contents of register group ALT_QSPI. */
6741 struct ALT_QSPI_raw_s
6742 {
6743  volatile uint32_t cfg; /* ALT_QSPI_CFG */
6744  volatile uint32_t devrd; /* ALT_QSPI_DEVRD */
6745  volatile uint32_t devwr; /* ALT_QSPI_DEVWR */
6746  volatile uint32_t delay; /* ALT_QSPI_DELAY */
6747  volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */
6748  volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */
6749  volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */
6750  volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
6751  volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */
6752  volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */
6753  volatile uint32_t modebit; /* ALT_QSPI_MODEBIT */
6754  volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */
6755  volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */
6756  volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */
6757  volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
6758  volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */
6759  volatile uint32_t irqmask; /* ALT_QSPI_IRQMASK */
6760  volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
6761  volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
6762  volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
6763  volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */
6764  volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
6765  volatile uint32_t indrd; /* ALT_QSPI_INDRD */
6766  volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */
6767  volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
6768  volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */
6769  volatile uint32_t indwr; /* ALT_QSPI_INDWR */
6770  volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */
6771  volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
6772  volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */
6773  volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
6774  volatile uint32_t flashcmd; /* ALT_QSPI_FLASHCMD */
6775  volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLASHCMDADDR */
6776  volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
6777  volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLASHCMDRDDATALO */
6778  volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLASHCMDRDDATAUP */
6779  volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLASHCMDWRDATALO */
6780  volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLASHCMDWRDATAUP */
6781  volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
6782  volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */
6783 };
6784 
6785 /* The typedef declaration for the raw register contents of register group ALT_QSPI. */
6786 typedef struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
6787 #endif /* __ASSEMBLY__ */
6788 
6789 
6790 #ifdef __cplusplus
6791 }
6792 #endif /* __cplusplus */
6793 #endif /* __ALT_SOCAL_QSPI_H__ */
6794