Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_spim.h
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32 
33 /* Altera - ALT_SPIM */
34 
35 #ifndef __ALT_SOCAL_SPIM_H__
36 #define __ALT_SOCAL_SPIM_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_SPIM
50  *
51  */
52 /*
53  * Register : ctrlr0
54  *
55  * Control Register 0:
56  *
57  * This register controls the serial data transfer. It is impossible to
58  *
59  * write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
60  *
61  * is enabled and disabled by writing to the SSIENR register.
62  *
63  * Register Layout
64  *
65  * Bits | Access | Reset | Description
66  * :--------|:-------|:------|:---------------------
67  * [3:0] | RW | 0x7 | ALT_SPIM_CTLR0_DFS
68  * [5:4] | RW | 0x0 | ALT_SPIM_CTLR0_FRF
69  * [6] | RW | 0x0 | ALT_SPIM_CTLR0_SCPH
70  * [7] | RW | 0x0 | ALT_SPIM_CTLR0_SCPOL
71  * [9:8] | RW | 0x0 | ALT_SPIM_CTLR0_TMOD
72  * [10] | ??? | 0x0 | *UNDEFINED*
73  * [11] | RW | 0x0 | ALT_SPIM_CTLR0_SRL
74  * [15:12] | RW | 0x0 | ALT_SPIM_CTLR0_CFS
75  * [31:16] | ??? | 0x0 | *UNDEFINED*
76  *
77  */
78 /*
79  * Field : dfs
80  *
81  * Data Frame Size.
82  *
83  * Selects the data frame length. When the data frame size is programmed
84  *
85  * to be less than 16 bits, the receive data are automatically
86  *
87  * right-justified by the receive logic, with the upper bits of the receive
88  *
89  * FIFO zero-padded. You must right-justify transmit data before writing
90  *
91  * into the transmit FIFO. The transmit logic ignores the upper unused
92  *
93  * bits when transmitting the data
94  *
95  * Field Enumeration Values:
96  *
97  * Enum | Value | Description
98  * :--------------------------------|:------|:----------------------------
99  * ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT | 0x3 | 4-bit serial data transfer
100  * ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT | 0x4 | 5-bit serial data transfer
101  * ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT | 0x5 | 6-bit serial data transfer
102  * ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT | 0x6 | 7-bit serial data transfer
103  * ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT | 0x7 | 8-bit serial data transfer
104  * ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT | 0x8 | 9-bit serial data transfer
105  * ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT | 0x9 | 10-bit serial data transfer
106  * ALT_SPIM_CTLR0_DFS_E_WIDTH11BIT | 0xa | 11-bit serial data transfer
107  * ALT_SPIM_CTLR0_DFS_E_WIDTH12BIT | 0xb | 12-bit serial data transfer
108  * ALT_SPIM_CTLR0_DFS_E_WIDTH13BIT | 0xc | 13-bit serial data transfer
109  * ALT_SPIM_CTLR0_DFS_E_WIDTH14BIT | 0xd | 14-bit serial data transfer
110  * ALT_SPIM_CTLR0_DFS_E_WIDTH15BIT | 0xe | 15-bit serial data transfer
111  * ALT_SPIM_CTLR0_DFS_E_WIDTH16BIT | 0xf | 16-bit serial data transfer
112  *
113  * Field Access Macros:
114  *
115  */
116 /*
117  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
118  *
119  * 4-bit serial data transfer
120  */
121 #define ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT 0x3
122 /*
123  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
124  *
125  * 5-bit serial data transfer
126  */
127 #define ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT 0x4
128 /*
129  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
130  *
131  * 6-bit serial data transfer
132  */
133 #define ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT 0x5
134 /*
135  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
136  *
137  * 7-bit serial data transfer
138  */
139 #define ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT 0x6
140 /*
141  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
142  *
143  * 8-bit serial data transfer
144  */
145 #define ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT 0x7
146 /*
147  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
148  *
149  * 9-bit serial data transfer
150  */
151 #define ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT 0x8
152 /*
153  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
154  *
155  * 10-bit serial data transfer
156  */
157 #define ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT 0x9
158 /*
159  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
160  *
161  * 11-bit serial data transfer
162  */
163 #define ALT_SPIM_CTLR0_DFS_E_WIDTH11BIT 0xa
164 /*
165  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
166  *
167  * 12-bit serial data transfer
168  */
169 #define ALT_SPIM_CTLR0_DFS_E_WIDTH12BIT 0xb
170 /*
171  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
172  *
173  * 13-bit serial data transfer
174  */
175 #define ALT_SPIM_CTLR0_DFS_E_WIDTH13BIT 0xc
176 /*
177  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
178  *
179  * 14-bit serial data transfer
180  */
181 #define ALT_SPIM_CTLR0_DFS_E_WIDTH14BIT 0xd
182 /*
183  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
184  *
185  * 15-bit serial data transfer
186  */
187 #define ALT_SPIM_CTLR0_DFS_E_WIDTH15BIT 0xe
188 /*
189  * Enumerated value for register field ALT_SPIM_CTLR0_DFS
190  *
191  * 16-bit serial data transfer
192  */
193 #define ALT_SPIM_CTLR0_DFS_E_WIDTH16BIT 0xf
194 
195 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_DFS register field. */
196 #define ALT_SPIM_CTLR0_DFS_LSB 0
197 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_DFS register field. */
198 #define ALT_SPIM_CTLR0_DFS_MSB 3
199 /* The width in bits of the ALT_SPIM_CTLR0_DFS register field. */
200 #define ALT_SPIM_CTLR0_DFS_WIDTH 4
201 /* The mask used to set the ALT_SPIM_CTLR0_DFS register field value. */
202 #define ALT_SPIM_CTLR0_DFS_SET_MSK 0x0000000f
203 /* The mask used to clear the ALT_SPIM_CTLR0_DFS register field value. */
204 #define ALT_SPIM_CTLR0_DFS_CLR_MSK 0xfffffff0
205 /* The reset value of the ALT_SPIM_CTLR0_DFS register field. */
206 #define ALT_SPIM_CTLR0_DFS_RESET 0x7
207 /* Extracts the ALT_SPIM_CTLR0_DFS field value from a register. */
208 #define ALT_SPIM_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
209 /* Produces a ALT_SPIM_CTLR0_DFS register field value suitable for setting the register. */
210 #define ALT_SPIM_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
211 
212 /*
213  * Field : frf
214  *
215  * Frame Format.
216  *
217  * Selects which serial protocol transfers the data.
218  *
219  * 00 - Motorola SPI
220  *
221  * 01 - Texas Instruments SSP
222  *
223  * 10 - National Semiconductors Microwire
224  *
225  * 11 - Reserved
226  *
227  * Field Enumeration Values:
228  *
229  * Enum | Value | Description
230  * :----------------------------|:------|:------------------------
231  * ALT_SPIM_CTLR0_FRF_E_MOTSPI | 0x0 | Motorola SPI
232  * ALT_SPIM_CTLR0_FRF_E_TISSP | 0x1 | Texas Instruments SSP
233  * ALT_SPIM_CTLR0_FRF_E_NATMW | 0x2 | National Semi Microwire
234  *
235  * Field Access Macros:
236  *
237  */
238 /*
239  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
240  *
241  * Motorola SPI
242  */
243 #define ALT_SPIM_CTLR0_FRF_E_MOTSPI 0x0
244 /*
245  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
246  *
247  * Texas Instruments SSP
248  */
249 #define ALT_SPIM_CTLR0_FRF_E_TISSP 0x1
250 /*
251  * Enumerated value for register field ALT_SPIM_CTLR0_FRF
252  *
253  * National Semi Microwire
254  */
255 #define ALT_SPIM_CTLR0_FRF_E_NATMW 0x2
256 
257 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_FRF register field. */
258 #define ALT_SPIM_CTLR0_FRF_LSB 4
259 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_FRF register field. */
260 #define ALT_SPIM_CTLR0_FRF_MSB 5
261 /* The width in bits of the ALT_SPIM_CTLR0_FRF register field. */
262 #define ALT_SPIM_CTLR0_FRF_WIDTH 2
263 /* The mask used to set the ALT_SPIM_CTLR0_FRF register field value. */
264 #define ALT_SPIM_CTLR0_FRF_SET_MSK 0x00000030
265 /* The mask used to clear the ALT_SPIM_CTLR0_FRF register field value. */
266 #define ALT_SPIM_CTLR0_FRF_CLR_MSK 0xffffffcf
267 /* The reset value of the ALT_SPIM_CTLR0_FRF register field. */
268 #define ALT_SPIM_CTLR0_FRF_RESET 0x0
269 /* Extracts the ALT_SPIM_CTLR0_FRF field value from a register. */
270 #define ALT_SPIM_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
271 /* Produces a ALT_SPIM_CTLR0_FRF register field value suitable for setting the register. */
272 #define ALT_SPIM_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
273 
274 /*
275  * Field : scph
276  *
277  * Serial Clock Phase.
278  *
279  * Valid when the frame format (FRF) is set to Motorola SPI. The serial
280  *
281  * clock phase selects the relationship of the serial clock with the slave
282  *
283  * select signal. When SCPH = 0, data are captured on the first edge of
284  *
285  * the serial clock. When SCPH = 1, the serial clock starts toggling one
286  *
287  * cycle after the slave select line is activated, and data are captured
288  *
289  * on the second edge of the serial clock.
290  *
291  * 0: Serial clock toggles in middle of first data bit
292  *
293  * 1: Serial clock toggles at start of first data bit
294  *
295  * Field Enumeration Values:
296  *
297  * Enum | Value | Description
298  * :-------------------------------|:------|:-------------------------------------------------
299  * ALT_SPIM_CTLR0_SCPH_E_MIDBIT | 0x0 | Serial clock toggles in middle of first data bit
300  * ALT_SPIM_CTLR0_SCPH_E_STARTBIT | 0x1 | Serial clock toggles at start of first data bit
301  *
302  * Field Access Macros:
303  *
304  */
305 /*
306  * Enumerated value for register field ALT_SPIM_CTLR0_SCPH
307  *
308  * Serial clock toggles in middle of first data bit
309  */
310 #define ALT_SPIM_CTLR0_SCPH_E_MIDBIT 0x0
311 /*
312  * Enumerated value for register field ALT_SPIM_CTLR0_SCPH
313  *
314  * Serial clock toggles at start of first data bit
315  */
316 #define ALT_SPIM_CTLR0_SCPH_E_STARTBIT 0x1
317 
318 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPH register field. */
319 #define ALT_SPIM_CTLR0_SCPH_LSB 6
320 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPH register field. */
321 #define ALT_SPIM_CTLR0_SCPH_MSB 6
322 /* The width in bits of the ALT_SPIM_CTLR0_SCPH register field. */
323 #define ALT_SPIM_CTLR0_SCPH_WIDTH 1
324 /* The mask used to set the ALT_SPIM_CTLR0_SCPH register field value. */
325 #define ALT_SPIM_CTLR0_SCPH_SET_MSK 0x00000040
326 /* The mask used to clear the ALT_SPIM_CTLR0_SCPH register field value. */
327 #define ALT_SPIM_CTLR0_SCPH_CLR_MSK 0xffffffbf
328 /* The reset value of the ALT_SPIM_CTLR0_SCPH register field. */
329 #define ALT_SPIM_CTLR0_SCPH_RESET 0x0
330 /* Extracts the ALT_SPIM_CTLR0_SCPH field value from a register. */
331 #define ALT_SPIM_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
332 /* Produces a ALT_SPIM_CTLR0_SCPH register field value suitable for setting the register. */
333 #define ALT_SPIM_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
334 
335 /*
336  * Field : scpol
337  *
338  * Serial Clock Polarity.
339  *
340  * Valid when the frame format (FRF) is set to Motorola SPI. Used to select
341  *
342  * the polarity of the inactive serial clock, which is held inactive when
343  *
344  * the DW_apb_ssi master is not actively transferring data on the serial bus.
345  *
346  * 0 - Inactive state of serial clock is low
347  *
348  * 1 - Inactive state of serial clock is high
349  *
350  * Field Enumeration Values:
351  *
352  * Enum | Value | Description
353  * :---------------------------------|:------|:---------------------------------------
354  * ALT_SPIM_CTLR0_SCPOL_E_INACTLOW | 0x0 | Inactive state of serial clock is low
355  * ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH | 0x1 | Inactive state of serial clock is high
356  *
357  * Field Access Macros:
358  *
359  */
360 /*
361  * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL
362  *
363  * Inactive state of serial clock is low
364  */
365 #define ALT_SPIM_CTLR0_SCPOL_E_INACTLOW 0x0
366 /*
367  * Enumerated value for register field ALT_SPIM_CTLR0_SCPOL
368  *
369  * Inactive state of serial clock is high
370  */
371 #define ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH 0x1
372 
373 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */
374 #define ALT_SPIM_CTLR0_SCPOL_LSB 7
375 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SCPOL register field. */
376 #define ALT_SPIM_CTLR0_SCPOL_MSB 7
377 /* The width in bits of the ALT_SPIM_CTLR0_SCPOL register field. */
378 #define ALT_SPIM_CTLR0_SCPOL_WIDTH 1
379 /* The mask used to set the ALT_SPIM_CTLR0_SCPOL register field value. */
380 #define ALT_SPIM_CTLR0_SCPOL_SET_MSK 0x00000080
381 /* The mask used to clear the ALT_SPIM_CTLR0_SCPOL register field value. */
382 #define ALT_SPIM_CTLR0_SCPOL_CLR_MSK 0xffffff7f
383 /* The reset value of the ALT_SPIM_CTLR0_SCPOL register field. */
384 #define ALT_SPIM_CTLR0_SCPOL_RESET 0x0
385 /* Extracts the ALT_SPIM_CTLR0_SCPOL field value from a register. */
386 #define ALT_SPIM_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
387 /* Produces a ALT_SPIM_CTLR0_SCPOL register field value suitable for setting the register. */
388 #define ALT_SPIM_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
389 
390 /*
391  * Field : tmod
392  *
393  * Transfer Mode.
394  *
395  * Selects the mode of transfer for serial communication. This field does
396  *
397  * not affect the transfer duplicity. Only indicates whether the receive or
398  *
399  * transmit data are valid. In transmit-only mode, data received from the
400  *
401  * external device is not valid and is not stored in the receive FIFO memory;
402  *
403  * it is overwritten on the next transfer. In receive-only mode, transmitted
404  *
405  * data are not valid. After the first write to the transmit FIFO, the same
406  *
407  * word is retransmitted for the duration of the transfer. In
408  *
409  * transmit-and-receive mode, both transmit and receive data are valid.
410  *
411  * The transfer continues until the transmit FIFO is empty. Data received
412  *
413  * from the external device are stored into the receive FIFO memory, where
414  *
415  * it can be accessed by the host processor.
416  *
417  * 00 - Transmit & Receive
418  *
419  * 01 - Transmit Only
420  *
421  * 10 - Receive Only
422  *
423  * 11 - Reserved
424  *
425  * Field Enumeration Values:
426  *
427  * Enum | Value | Description
428  * :-----------------------------|:------|:-----------------------
429  * ALT_SPIM_CTLR0_TMOD_E_TXRX | 0x0 | Transmit & and Receive
430  * ALT_SPIM_CTLR0_TMOD_E_TXONLY | 0x1 | Transmit Only
431  * ALT_SPIM_CTLR0_TMOD_E_RXONLY | 0x2 | Receive Only
432  * ALT_SPIM_CTLR0_TMOD_E_EERD | 0x3 | EEPROM Read
433  *
434  * Field Access Macros:
435  *
436  */
437 /*
438  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
439  *
440  * Transmit & and Receive
441  */
442 #define ALT_SPIM_CTLR0_TMOD_E_TXRX 0x0
443 /*
444  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
445  *
446  * Transmit Only
447  */
448 #define ALT_SPIM_CTLR0_TMOD_E_TXONLY 0x1
449 /*
450  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
451  *
452  * Receive Only
453  */
454 #define ALT_SPIM_CTLR0_TMOD_E_RXONLY 0x2
455 /*
456  * Enumerated value for register field ALT_SPIM_CTLR0_TMOD
457  *
458  * EEPROM Read
459  */
460 #define ALT_SPIM_CTLR0_TMOD_E_EERD 0x3
461 
462 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_TMOD register field. */
463 #define ALT_SPIM_CTLR0_TMOD_LSB 8
464 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_TMOD register field. */
465 #define ALT_SPIM_CTLR0_TMOD_MSB 9
466 /* The width in bits of the ALT_SPIM_CTLR0_TMOD register field. */
467 #define ALT_SPIM_CTLR0_TMOD_WIDTH 2
468 /* The mask used to set the ALT_SPIM_CTLR0_TMOD register field value. */
469 #define ALT_SPIM_CTLR0_TMOD_SET_MSK 0x00000300
470 /* The mask used to clear the ALT_SPIM_CTLR0_TMOD register field value. */
471 #define ALT_SPIM_CTLR0_TMOD_CLR_MSK 0xfffffcff
472 /* The reset value of the ALT_SPIM_CTLR0_TMOD register field. */
473 #define ALT_SPIM_CTLR0_TMOD_RESET 0x0
474 /* Extracts the ALT_SPIM_CTLR0_TMOD field value from a register. */
475 #define ALT_SPIM_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
476 /* Produces a ALT_SPIM_CTLR0_TMOD register field value suitable for setting the register. */
477 #define ALT_SPIM_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
478 
479 /*
480  * Field : srl
481  *
482  * Shift Register Loop. Used for testing purposes only. When internally
483  *
484  * active, connects the transmit shift register output to the receive
485  *
486  * shift register input.
487  *
488  * 0 - Normal Mode Operation
489  *
490  * 1 - Test Mode Operation
491  *
492  * Field Enumeration Values:
493  *
494  * Enum | Value | Description
495  * :-----------------------------|:------|:----------------------
496  * ALT_SPIM_CTLR0_SRL_E_NORMMOD | 0x0 | Normal Mode Operation
497  * ALT_SPIM_CTLR0_SRL_E_TESTMOD | 0x1 | Test Mode Operation
498  *
499  * Field Access Macros:
500  *
501  */
502 /*
503  * Enumerated value for register field ALT_SPIM_CTLR0_SRL
504  *
505  * Normal Mode Operation
506  */
507 #define ALT_SPIM_CTLR0_SRL_E_NORMMOD 0x0
508 /*
509  * Enumerated value for register field ALT_SPIM_CTLR0_SRL
510  *
511  * Test Mode Operation
512  */
513 #define ALT_SPIM_CTLR0_SRL_E_TESTMOD 0x1
514 
515 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_SRL register field. */
516 #define ALT_SPIM_CTLR0_SRL_LSB 11
517 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_SRL register field. */
518 #define ALT_SPIM_CTLR0_SRL_MSB 11
519 /* The width in bits of the ALT_SPIM_CTLR0_SRL register field. */
520 #define ALT_SPIM_CTLR0_SRL_WIDTH 1
521 /* The mask used to set the ALT_SPIM_CTLR0_SRL register field value. */
522 #define ALT_SPIM_CTLR0_SRL_SET_MSK 0x00000800
523 /* The mask used to clear the ALT_SPIM_CTLR0_SRL register field value. */
524 #define ALT_SPIM_CTLR0_SRL_CLR_MSK 0xfffff7ff
525 /* The reset value of the ALT_SPIM_CTLR0_SRL register field. */
526 #define ALT_SPIM_CTLR0_SRL_RESET 0x0
527 /* Extracts the ALT_SPIM_CTLR0_SRL field value from a register. */
528 #define ALT_SPIM_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
529 /* Produces a ALT_SPIM_CTLR0_SRL register field value suitable for setting the register. */
530 #define ALT_SPIM_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
531 
532 /*
533  * Field : cfs
534  *
535  * Control Frame Size. Selects the length of the control word for the
536  *
537  * Microwire frame format
538  *
539  * Field Enumeration Values:
540  *
541  * Enum | Value | Description
542  * :-------------------------------|:------|:--------------------
543  * ALT_SPIM_CTLR0_CFS_E_SIZE1BIT | 0x0 | 1-bit control word
544  * ALT_SPIM_CTLR0_CFS_E_SIZE2BIT | 0x1 | 2-bit control word
545  * ALT_SPIM_CTLR0_CFS_E_SIZE3BIT | 0x2 | 3-bit control word
546  * ALT_SPIM_CTLR0_CFS_E_SIZE4BIT | 0x3 | 4-bit control word
547  * ALT_SPIM_CTLR0_CFS_E_SIZE5BIT | 0x4 | 5-bit control word
548  * ALT_SPIM_CTLR0_CFS_E_SIZE6BIT | 0x05 | 6-bit control word
549  * ALT_SPIM_CTLR0_CFS_E_SIZE7BIT | 0x6 | 7-bit control word
550  * ALT_SPIM_CTLR0_CFS_E_SIZE8BIT | 0x7 | 8-bit control word
551  * ALT_SPIM_CTLR0_CFS_E_SIZE9BIT | 0x8 | 9-bit control word
552  * ALT_SPIM_CTLR0_CFS_E_SIZE10BIT | 0x9 | 10-bit control word
553  * ALT_SPIM_CTLR0_CFS_E_SIZE11BIT | 0xa | 11-bit control word
554  * ALT_SPIM_CTLR0_CFS_E_SIZE12BIT | 0xb | 12-bit control word
555  * ALT_SPIM_CTLR0_CFS_E_SIZE13BIT | 0xc | 13-bit control word
556  * ALT_SPIM_CTLR0_CFS_E_SIZE14BIT | 0xd | 14-bit control word
557  * ALT_SPIM_CTLR0_CFS_E_SIZE15BIT | 0xe | 15-bit control word
558  * ALT_SPIM_CTLR0_CFS_E_SIZE16BIT | 0xf | 16-bit control word
559  *
560  * Field Access Macros:
561  *
562  */
563 /*
564  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
565  *
566  * 1-bit control word
567  */
568 #define ALT_SPIM_CTLR0_CFS_E_SIZE1BIT 0x0
569 /*
570  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
571  *
572  * 2-bit control word
573  */
574 #define ALT_SPIM_CTLR0_CFS_E_SIZE2BIT 0x1
575 /*
576  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
577  *
578  * 3-bit control word
579  */
580 #define ALT_SPIM_CTLR0_CFS_E_SIZE3BIT 0x2
581 /*
582  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
583  *
584  * 4-bit control word
585  */
586 #define ALT_SPIM_CTLR0_CFS_E_SIZE4BIT 0x3
587 /*
588  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
589  *
590  * 5-bit control word
591  */
592 #define ALT_SPIM_CTLR0_CFS_E_SIZE5BIT 0x4
593 /*
594  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
595  *
596  * 6-bit control word
597  */
598 #define ALT_SPIM_CTLR0_CFS_E_SIZE6BIT 0x05
599 /*
600  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
601  *
602  * 7-bit control word
603  */
604 #define ALT_SPIM_CTLR0_CFS_E_SIZE7BIT 0x6
605 /*
606  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
607  *
608  * 8-bit control word
609  */
610 #define ALT_SPIM_CTLR0_CFS_E_SIZE8BIT 0x7
611 /*
612  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
613  *
614  * 9-bit control word
615  */
616 #define ALT_SPIM_CTLR0_CFS_E_SIZE9BIT 0x8
617 /*
618  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
619  *
620  * 10-bit control word
621  */
622 #define ALT_SPIM_CTLR0_CFS_E_SIZE10BIT 0x9
623 /*
624  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
625  *
626  * 11-bit control word
627  */
628 #define ALT_SPIM_CTLR0_CFS_E_SIZE11BIT 0xa
629 /*
630  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
631  *
632  * 12-bit control word
633  */
634 #define ALT_SPIM_CTLR0_CFS_E_SIZE12BIT 0xb
635 /*
636  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
637  *
638  * 13-bit control word
639  */
640 #define ALT_SPIM_CTLR0_CFS_E_SIZE13BIT 0xc
641 /*
642  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
643  *
644  * 14-bit control word
645  */
646 #define ALT_SPIM_CTLR0_CFS_E_SIZE14BIT 0xd
647 /*
648  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
649  *
650  * 15-bit control word
651  */
652 #define ALT_SPIM_CTLR0_CFS_E_SIZE15BIT 0xe
653 /*
654  * Enumerated value for register field ALT_SPIM_CTLR0_CFS
655  *
656  * 16-bit control word
657  */
658 #define ALT_SPIM_CTLR0_CFS_E_SIZE16BIT 0xf
659 
660 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR0_CFS register field. */
661 #define ALT_SPIM_CTLR0_CFS_LSB 12
662 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR0_CFS register field. */
663 #define ALT_SPIM_CTLR0_CFS_MSB 15
664 /* The width in bits of the ALT_SPIM_CTLR0_CFS register field. */
665 #define ALT_SPIM_CTLR0_CFS_WIDTH 4
666 /* The mask used to set the ALT_SPIM_CTLR0_CFS register field value. */
667 #define ALT_SPIM_CTLR0_CFS_SET_MSK 0x0000f000
668 /* The mask used to clear the ALT_SPIM_CTLR0_CFS register field value. */
669 #define ALT_SPIM_CTLR0_CFS_CLR_MSK 0xffff0fff
670 /* The reset value of the ALT_SPIM_CTLR0_CFS register field. */
671 #define ALT_SPIM_CTLR0_CFS_RESET 0x0
672 /* Extracts the ALT_SPIM_CTLR0_CFS field value from a register. */
673 #define ALT_SPIM_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
674 /* Produces a ALT_SPIM_CTLR0_CFS register field value suitable for setting the register. */
675 #define ALT_SPIM_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
676 
677 #ifndef __ASSEMBLY__
678 /*
679  * WARNING: The C register and register group struct declarations are provided for
680  * convenience and illustrative purposes. They should, however, be used with
681  * caution as the C language standard provides no guarantees about the alignment or
682  * atomicity of device memory accesses. The recommended practice for writing
683  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
684  * alt_write_word() functions.
685  *
686  * The struct declaration for register ALT_SPIM_CTLR0.
687  */
688 struct ALT_SPIM_CTLR0_s
689 {
690  uint32_t dfs : 4; /* ALT_SPIM_CTLR0_DFS */
691  uint32_t frf : 2; /* ALT_SPIM_CTLR0_FRF */
692  uint32_t scph : 1; /* ALT_SPIM_CTLR0_SCPH */
693  uint32_t scpol : 1; /* ALT_SPIM_CTLR0_SCPOL */
694  uint32_t tmod : 2; /* ALT_SPIM_CTLR0_TMOD */
695  uint32_t : 1; /* *UNDEFINED* */
696  uint32_t srl : 1; /* ALT_SPIM_CTLR0_SRL */
697  uint32_t cfs : 4; /* ALT_SPIM_CTLR0_CFS */
698  uint32_t : 16; /* *UNDEFINED* */
699 };
700 
701 /* The typedef declaration for register ALT_SPIM_CTLR0. */
702 typedef volatile struct ALT_SPIM_CTLR0_s ALT_SPIM_CTLR0_t;
703 #endif /* __ASSEMBLY__ */
704 
705 /* The reset value of the ALT_SPIM_CTLR0 register. */
706 #define ALT_SPIM_CTLR0_RESET 0x00000007
707 /* The byte offset of the ALT_SPIM_CTLR0 register from the beginning of the component. */
708 #define ALT_SPIM_CTLR0_OFST 0x0
709 /* The address of the ALT_SPIM_CTLR0 register. */
710 #define ALT_SPIM_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR0_OFST))
711 
712 /*
713  * Register : ctrlr1
714  *
715  * Control Register 1
716  *
717  * This register exists only when the DW_apb_ssi is configured as a
718  *
719  * master device. When the DW_apb_ssi is configured as a serial slave,
720  *
721  * writing to this location has no effect; reading from this location
722  *
723  * returns 0. Control register 1 controls the end of serial transfers
724  *
725  * when in receive-only mode. It is impossible to write to this
726  *
727  * register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled
728  *
729  * and disabled by writing to the SSIENR register.
730  *
731  * Register Layout
732  *
733  * Bits | Access | Reset | Description
734  * :--------|:-------|:------|:-------------------
735  * [15:0] | RW | 0x0 | ALT_SPIM_CTLR1_NDF
736  * [31:16] | ??? | 0x0 | *UNDEFINED*
737  *
738  */
739 /*
740  * Field : ndf
741  *
742  * Number of Data Frames.
743  *
744  * When TMOD = 10 or TMOD = 11, this register field sets the number of data frames
745  * to
746  *
747  * be continuously received by the DW_apb_ssi. The DW_apb_ssi continues
748  *
749  * to receive serial data until the number of data frames received is
750  *
751  * equal to this register value plus 1, which enables you to receive up
752  *
753  * to 64 KB of data in a continuous transfer. When the DW_apb_ssi is
754  *
755  * configured as a serial slave, the transfer continues for as long as
756  *
757  * the slave is selected. Therefore, this register serves no purpose and
758  *
759  * is not present when the DW_apb_ssi is configured as a serial slave.
760  *
761  * Field Access Macros:
762  *
763  */
764 /* The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR1_NDF register field. */
765 #define ALT_SPIM_CTLR1_NDF_LSB 0
766 /* The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR1_NDF register field. */
767 #define ALT_SPIM_CTLR1_NDF_MSB 15
768 /* The width in bits of the ALT_SPIM_CTLR1_NDF register field. */
769 #define ALT_SPIM_CTLR1_NDF_WIDTH 16
770 /* The mask used to set the ALT_SPIM_CTLR1_NDF register field value. */
771 #define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff
772 /* The mask used to clear the ALT_SPIM_CTLR1_NDF register field value. */
773 #define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000
774 /* The reset value of the ALT_SPIM_CTLR1_NDF register field. */
775 #define ALT_SPIM_CTLR1_NDF_RESET 0x0
776 /* Extracts the ALT_SPIM_CTLR1_NDF field value from a register. */
777 #define ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
778 /* Produces a ALT_SPIM_CTLR1_NDF register field value suitable for setting the register. */
779 #define ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
780 
781 #ifndef __ASSEMBLY__
782 /*
783  * WARNING: The C register and register group struct declarations are provided for
784  * convenience and illustrative purposes. They should, however, be used with
785  * caution as the C language standard provides no guarantees about the alignment or
786  * atomicity of device memory accesses. The recommended practice for writing
787  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
788  * alt_write_word() functions.
789  *
790  * The struct declaration for register ALT_SPIM_CTLR1.
791  */
792 struct ALT_SPIM_CTLR1_s
793 {
794  uint32_t ndf : 16; /* ALT_SPIM_CTLR1_NDF */
795  uint32_t : 16; /* *UNDEFINED* */
796 };
797 
798 /* The typedef declaration for register ALT_SPIM_CTLR1. */
799 typedef volatile struct ALT_SPIM_CTLR1_s ALT_SPIM_CTLR1_t;
800 #endif /* __ASSEMBLY__ */
801 
802 /* The reset value of the ALT_SPIM_CTLR1 register. */
803 #define ALT_SPIM_CTLR1_RESET 0x00000000
804 /* The byte offset of the ALT_SPIM_CTLR1 register from the beginning of the component. */
805 #define ALT_SPIM_CTLR1_OFST 0x4
806 /* The address of the ALT_SPIM_CTLR1 register. */
807 #define ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST))
808 
809 /*
810  * Register : spienr
811  *
812  * SSI Enable Register
813  *
814  * Register Layout
815  *
816  * Bits | Access | Reset | Description
817  * :-------|:-------|:------|:-----------------------
818  * [0] | RW | 0x0 | ALT_SPIM_SPIENR_SPI_EN
819  * [31:1] | ??? | 0x0 | *UNDEFINED*
820  *
821  */
822 /*
823  * Field : spi_en
824  *
825  * SSI Enable. Enables and disables all DW_apb_ssi operations. When
826  *
827  * disabled, all serial transfers are halted immediately. Transmit and
828  *
829  * receive FIFO buffers are cleared when the device is disabled. It is
830  *
831  * impossible to program some of the DW_apb_ssi control registers when
832  *
833  * enabled. When disabled, the ssi_sleep output is set (after delay) to
834  *
835  * inform the system that it is safe to remove the ssi_clk, thus saving
836  *
837  * power consumption in the system.
838  *
839  * Field Enumeration Values:
840  *
841  * Enum | Value | Description
842  * :------------------------------|:------|:------------------------------------
843  * ALT_SPIM_SPIENR_SPI_EN_E_DISD | 0x0 | Disables serial transfer operations
844  * ALT_SPIM_SPIENR_SPI_EN_E_END | 0x1 | Enables serial transfer operations
845  *
846  * Field Access Macros:
847  *
848  */
849 /*
850  * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN
851  *
852  * Disables serial transfer operations
853  */
854 #define ALT_SPIM_SPIENR_SPI_EN_E_DISD 0x0
855 /*
856  * Enumerated value for register field ALT_SPIM_SPIENR_SPI_EN
857  *
858  * Enables serial transfer operations
859  */
860 #define ALT_SPIM_SPIENR_SPI_EN_E_END 0x1
861 
862 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */
863 #define ALT_SPIM_SPIENR_SPI_EN_LSB 0
864 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SPIENR_SPI_EN register field. */
865 #define ALT_SPIM_SPIENR_SPI_EN_MSB 0
866 /* The width in bits of the ALT_SPIM_SPIENR_SPI_EN register field. */
867 #define ALT_SPIM_SPIENR_SPI_EN_WIDTH 1
868 /* The mask used to set the ALT_SPIM_SPIENR_SPI_EN register field value. */
869 #define ALT_SPIM_SPIENR_SPI_EN_SET_MSK 0x00000001
870 /* The mask used to clear the ALT_SPIM_SPIENR_SPI_EN register field value. */
871 #define ALT_SPIM_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
872 /* The reset value of the ALT_SPIM_SPIENR_SPI_EN register field. */
873 #define ALT_SPIM_SPIENR_SPI_EN_RESET 0x0
874 /* Extracts the ALT_SPIM_SPIENR_SPI_EN field value from a register. */
875 #define ALT_SPIM_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
876 /* Produces a ALT_SPIM_SPIENR_SPI_EN register field value suitable for setting the register. */
877 #define ALT_SPIM_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
878 
879 #ifndef __ASSEMBLY__
880 /*
881  * WARNING: The C register and register group struct declarations are provided for
882  * convenience and illustrative purposes. They should, however, be used with
883  * caution as the C language standard provides no guarantees about the alignment or
884  * atomicity of device memory accesses. The recommended practice for writing
885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
886  * alt_write_word() functions.
887  *
888  * The struct declaration for register ALT_SPIM_SPIENR.
889  */
890 struct ALT_SPIM_SPIENR_s
891 {
892  uint32_t spi_en : 1; /* ALT_SPIM_SPIENR_SPI_EN */
893  uint32_t : 31; /* *UNDEFINED* */
894 };
895 
896 /* The typedef declaration for register ALT_SPIM_SPIENR. */
897 typedef volatile struct ALT_SPIM_SPIENR_s ALT_SPIM_SPIENR_t;
898 #endif /* __ASSEMBLY__ */
899 
900 /* The reset value of the ALT_SPIM_SPIENR register. */
901 #define ALT_SPIM_SPIENR_RESET 0x00000000
902 /* The byte offset of the ALT_SPIM_SPIENR register from the beginning of the component. */
903 #define ALT_SPIM_SPIENR_OFST 0x8
904 /* The address of the ALT_SPIM_SPIENR register. */
905 #define ALT_SPIM_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPIENR_OFST))
906 
907 /*
908  * Register : mwcr
909  *
910  * Microwire Control Register.
911  *
912  * This register controls the direction of the data word for the half-duplex
913  *
914  * Microwire serial protocol. It is impossible to write to this register
915  *
916  * when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
917  *
918  * writing to the SSIENR register.
919  *
920  * Register Layout
921  *
922  * Bits | Access | Reset | Description
923  * :-------|:-------|:------|:--------------------
924  * [0] | RW | 0x0 | ALT_SPIM_MWCR_MWMOD
925  * [1] | RW | 0x0 | ALT_SPIM_MWCR_MDD
926  * [2] | RW | 0x0 | ALT_SPIM_MWCR_MHS
927  * [31:3] | ??? | 0x0 | *UNDEFINED*
928  *
929  */
930 /*
931  * Field : mwmod
932  *
933  * Microwire Transfer Mode.
934  *
935  * Defines whether the Microwire transfer is sequential or non-sequential.
936  *
937  * When sequential mode is used, only one control word is needed to
938  *
939  * transmit or receive a block of data words. When non-sequential mode is
940  *
941  * used, there must be a control word for each data word that is
942  *
943  * transmitted or received.
944  *
945  * 0: non-sequential transfer
946  *
947  * 1: sequential transfer
948  *
949  * Field Enumeration Values:
950  *
951  * Enum | Value | Description
952  * :-----------------------------|:------|:------------------------
953  * ALT_SPIM_MWCR_MWMOD_E_NONSEQ | 0x0 | non-sequential transfer
954  * ALT_SPIM_MWCR_MWMOD_E_SEQ | 0x1 | sequential transfer
955  *
956  * Field Access Macros:
957  *
958  */
959 /*
960  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
961  *
962  * non-sequential transfer
963  */
964 #define ALT_SPIM_MWCR_MWMOD_E_NONSEQ 0x0
965 /*
966  * Enumerated value for register field ALT_SPIM_MWCR_MWMOD
967  *
968  * sequential transfer
969  */
970 #define ALT_SPIM_MWCR_MWMOD_E_SEQ 0x1
971 
972 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
973 #define ALT_SPIM_MWCR_MWMOD_LSB 0
974 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MWMOD register field. */
975 #define ALT_SPIM_MWCR_MWMOD_MSB 0
976 /* The width in bits of the ALT_SPIM_MWCR_MWMOD register field. */
977 #define ALT_SPIM_MWCR_MWMOD_WIDTH 1
978 /* The mask used to set the ALT_SPIM_MWCR_MWMOD register field value. */
979 #define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
980 /* The mask used to clear the ALT_SPIM_MWCR_MWMOD register field value. */
981 #define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
982 /* The reset value of the ALT_SPIM_MWCR_MWMOD register field. */
983 #define ALT_SPIM_MWCR_MWMOD_RESET 0x0
984 /* Extracts the ALT_SPIM_MWCR_MWMOD field value from a register. */
985 #define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
986 /* Produces a ALT_SPIM_MWCR_MWMOD register field value suitable for setting the register. */
987 #define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
988 
989 /*
990  * Field : mdd
991  *
992  * Microwire Control.
993  *
994  * Defines the direction of the data word when the Microwire serial protocol
995  *
996  * is used. When this bit is set to 0, the data word is received by the
997  *
998  * DW_apb_ssi MacroCell from the external serial device. When this bit is
999  *
1000  * set to 1, the data word is transmitted from the DW_apb_ssi MacroCell to
1001  *
1002  * the external serial device.
1003  *
1004  * Field Enumeration Values:
1005  *
1006  * Enum | Value | Description
1007  * :--------------------------|:------|:--------------------------
1008  * ALT_SPIM_MWCR_MDD_E_RXMOD | 0x0 | SPI Master receives data
1009  * ALT_SPIM_MWCR_MDD_E_TXMOD | 0x1 | SPI Master transmits data
1010  *
1011  * Field Access Macros:
1012  *
1013  */
1014 /*
1015  * Enumerated value for register field ALT_SPIM_MWCR_MDD
1016  *
1017  * SPI Master receives data
1018  */
1019 #define ALT_SPIM_MWCR_MDD_E_RXMOD 0x0
1020 /*
1021  * Enumerated value for register field ALT_SPIM_MWCR_MDD
1022  *
1023  * SPI Master transmits data
1024  */
1025 #define ALT_SPIM_MWCR_MDD_E_TXMOD 0x1
1026 
1027 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MDD register field. */
1028 #define ALT_SPIM_MWCR_MDD_LSB 1
1029 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MDD register field. */
1030 #define ALT_SPIM_MWCR_MDD_MSB 1
1031 /* The width in bits of the ALT_SPIM_MWCR_MDD register field. */
1032 #define ALT_SPIM_MWCR_MDD_WIDTH 1
1033 /* The mask used to set the ALT_SPIM_MWCR_MDD register field value. */
1034 #define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
1035 /* The mask used to clear the ALT_SPIM_MWCR_MDD register field value. */
1036 #define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
1037 /* The reset value of the ALT_SPIM_MWCR_MDD register field. */
1038 #define ALT_SPIM_MWCR_MDD_RESET 0x0
1039 /* Extracts the ALT_SPIM_MWCR_MDD field value from a register. */
1040 #define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1041 /* Produces a ALT_SPIM_MWCR_MDD register field value suitable for setting the register. */
1042 #define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1043 
1044 /*
1045  * Field : mhs
1046  *
1047  * Microwire Handshaking.
1048  *
1049  * Relevant only when the DW_apb_ssi is configured as a serial-master device.
1050  *
1051  * When configured as a serial slave, this bit field has no functionality.
1052  *
1053  * Used to enable and disable the busy/ready handshaking interface for the
1054  *
1055  * Microwire protocol. When enabled, the DW_apb_ssi checks for a ready status
1056  *
1057  * from the target slave, after the transfer of the last data/control bit,
1058  *
1059  * before clearing the BUSY status in the SR register.
1060  *
1061  * 0: handshaking interface is disabled
1062  *
1063  * 1: handshaking interface is enabled
1064  *
1065  * Field Enumeration Values:
1066  *
1067  * Enum | Value | Description
1068  * :-------------------------|:------|:----------------------------------
1069  * ALT_SPIM_MWCR_MHS_E_DISD | 0x0 | Handshaking interface is disabled
1070  * ALT_SPIM_MWCR_MHS_E_END | 0x1 | Handshaking interface is enabled
1071  *
1072  * Field Access Macros:
1073  *
1074  */
1075 /*
1076  * Enumerated value for register field ALT_SPIM_MWCR_MHS
1077  *
1078  * Handshaking interface is disabled
1079  */
1080 #define ALT_SPIM_MWCR_MHS_E_DISD 0x0
1081 /*
1082  * Enumerated value for register field ALT_SPIM_MWCR_MHS
1083  *
1084  * Handshaking interface is enabled
1085  */
1086 #define ALT_SPIM_MWCR_MHS_E_END 0x1
1087 
1088 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MWCR_MHS register field. */
1089 #define ALT_SPIM_MWCR_MHS_LSB 2
1090 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MWCR_MHS register field. */
1091 #define ALT_SPIM_MWCR_MHS_MSB 2
1092 /* The width in bits of the ALT_SPIM_MWCR_MHS register field. */
1093 #define ALT_SPIM_MWCR_MHS_WIDTH 1
1094 /* The mask used to set the ALT_SPIM_MWCR_MHS register field value. */
1095 #define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
1096 /* The mask used to clear the ALT_SPIM_MWCR_MHS register field value. */
1097 #define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
1098 /* The reset value of the ALT_SPIM_MWCR_MHS register field. */
1099 #define ALT_SPIM_MWCR_MHS_RESET 0x0
1100 /* Extracts the ALT_SPIM_MWCR_MHS field value from a register. */
1101 #define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
1102 /* Produces a ALT_SPIM_MWCR_MHS register field value suitable for setting the register. */
1103 #define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
1104 
1105 #ifndef __ASSEMBLY__
1106 /*
1107  * WARNING: The C register and register group struct declarations are provided for
1108  * convenience and illustrative purposes. They should, however, be used with
1109  * caution as the C language standard provides no guarantees about the alignment or
1110  * atomicity of device memory accesses. The recommended practice for writing
1111  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1112  * alt_write_word() functions.
1113  *
1114  * The struct declaration for register ALT_SPIM_MWCR.
1115  */
1116 struct ALT_SPIM_MWCR_s
1117 {
1118  uint32_t mwmod : 1; /* ALT_SPIM_MWCR_MWMOD */
1119  uint32_t mdd : 1; /* ALT_SPIM_MWCR_MDD */
1120  uint32_t mhs : 1; /* ALT_SPIM_MWCR_MHS */
1121  uint32_t : 29; /* *UNDEFINED* */
1122 };
1123 
1124 /* The typedef declaration for register ALT_SPIM_MWCR. */
1125 typedef volatile struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t;
1126 #endif /* __ASSEMBLY__ */
1127 
1128 /* The reset value of the ALT_SPIM_MWCR register. */
1129 #define ALT_SPIM_MWCR_RESET 0x00000000
1130 /* The byte offset of the ALT_SPIM_MWCR register from the beginning of the component. */
1131 #define ALT_SPIM_MWCR_OFST 0xc
1132 /* The address of the ALT_SPIM_MWCR register. */
1133 #define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
1134 
1135 /*
1136  * Register : ser
1137  *
1138  * Slave Enable Register.
1139  *
1140  * This register is valid only when the DW_apb_ssi is configured as a master
1141  *
1142  * device. When the DW_apb_ssi is configured as a serial slave, writing to
1143  *
1144  * this location has no effect; reading from this location returns 0. The
1145  *
1146  * register enables the individual slave select output lines from the
1147  *
1148  * DW_apb_ssi master. Up to 16 slave-select output pins are available on the
1149  *
1150  * DW_apb_ssi master. You cannot write to this register when DW_apb_ssi is
1151  *
1152  * busy and when SSI_EN = 1.
1153  *
1154  * Register Layout
1155  *
1156  * Bits | Access | Reset | Description
1157  * :-------|:-------|:------|:-----------------
1158  * [3:0] | RW | 0x0 | ALT_SPIM_SER_SER
1159  * [31:4] | ??? | 0x0 | *UNDEFINED*
1160  *
1161  */
1162 /*
1163  * Field : ser
1164  *
1165  * Slave Select Enable Flag.
1166  *
1167  * Each bit in this register corresponds to a slave select line (ss_x_n])
1168  *
1169  * from the DW_apb_ssi master. When a bit in this register is set (1), the
1170  *
1171  * corresponding slave select line from the master is activated when a
1172  *
1173  * serial transfer begins. It should be noted that setting or clearing bits
1174  *
1175  * in this register have no effect on the corresponding slave select outputs
1176  *
1177  * until a transfer is started. Before beginning a transfer, you should
1178  *
1179  * enable the bit in this register that corresponds to the slave device
1180  *
1181  * with which the master wants to communicate. When not operating in
1182  *
1183  * broadcast mode, only one bit in this field should be set.
1184  *
1185  * 1: Selected
1186  *
1187  * 0: Not Selected
1188  *
1189  * Field Enumeration Values:
1190  *
1191  * Enum | Value | Description
1192  * :-------------------------------|:------|:---------------------
1193  * ALT_SPIM_SER_SER_E_NOTSELECTED | 0x0 | Slave x Not Selected
1194  * ALT_SPIM_SER_SER_E_SELECTED | 0x1 | Slave x Selected
1195  *
1196  * Field Access Macros:
1197  *
1198  */
1199 /*
1200  * Enumerated value for register field ALT_SPIM_SER_SER
1201  *
1202  * Slave x Not Selected
1203  */
1204 #define ALT_SPIM_SER_SER_E_NOTSELECTED 0x0
1205 /*
1206  * Enumerated value for register field ALT_SPIM_SER_SER
1207  *
1208  * Slave x Selected
1209  */
1210 #define ALT_SPIM_SER_SER_E_SELECTED 0x1
1211 
1212 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SER_SER register field. */
1213 #define ALT_SPIM_SER_SER_LSB 0
1214 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SER_SER register field. */
1215 #define ALT_SPIM_SER_SER_MSB 3
1216 /* The width in bits of the ALT_SPIM_SER_SER register field. */
1217 #define ALT_SPIM_SER_SER_WIDTH 4
1218 /* The mask used to set the ALT_SPIM_SER_SER register field value. */
1219 #define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
1220 /* The mask used to clear the ALT_SPIM_SER_SER register field value. */
1221 #define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
1222 /* The reset value of the ALT_SPIM_SER_SER register field. */
1223 #define ALT_SPIM_SER_SER_RESET 0x0
1224 /* Extracts the ALT_SPIM_SER_SER field value from a register. */
1225 #define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
1226 /* Produces a ALT_SPIM_SER_SER register field value suitable for setting the register. */
1227 #define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
1228 
1229 #ifndef __ASSEMBLY__
1230 /*
1231  * WARNING: The C register and register group struct declarations are provided for
1232  * convenience and illustrative purposes. They should, however, be used with
1233  * caution as the C language standard provides no guarantees about the alignment or
1234  * atomicity of device memory accesses. The recommended practice for writing
1235  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1236  * alt_write_word() functions.
1237  *
1238  * The struct declaration for register ALT_SPIM_SER.
1239  */
1240 struct ALT_SPIM_SER_s
1241 {
1242  uint32_t ser : 4; /* ALT_SPIM_SER_SER */
1243  uint32_t : 28; /* *UNDEFINED* */
1244 };
1245 
1246 /* The typedef declaration for register ALT_SPIM_SER. */
1247 typedef volatile struct ALT_SPIM_SER_s ALT_SPIM_SER_t;
1248 #endif /* __ASSEMBLY__ */
1249 
1250 /* The reset value of the ALT_SPIM_SER register. */
1251 #define ALT_SPIM_SER_RESET 0x00000000
1252 /* The byte offset of the ALT_SPIM_SER register from the beginning of the component. */
1253 #define ALT_SPIM_SER_OFST 0x10
1254 /* The address of the ALT_SPIM_SER register. */
1255 #define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
1256 
1257 /*
1258  * Register : baudr
1259  *
1260  * Baud Rate Select.
1261  *
1262  * This register is valid only when the DW_apb_ssi is configured as a master
1263  *
1264  * device. When the DW_apb_ssi is configured as a serial slave, writing to
1265  *
1266  * this location has no effect; reading from this location returns 0. The
1267  *
1268  * register derives the frequency of the serial clock that regulates the data
1269  *
1270  * transfer. The 16-bit field in this register defines the ssi_clk divider
1271  *
1272  * value. It is impossible to write to this register when the DW_apb_ssi is
1273  *
1274  * enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR
1275  *
1276  * register.
1277  *
1278  * Register Layout
1279  *
1280  * Bits | Access | Reset | Description
1281  * :--------|:-------|:------|:---------------------
1282  * [15:0] | RW | 0x0 | ALT_SPIM_BAUDR_SCKDV
1283  * [31:16] | ??? | 0x0 | *UNDEFINED*
1284  *
1285  */
1286 /*
1287  * Field : sckdv
1288  *
1289  * SSI Clock Divider.
1290  *
1291  * The LSB for this field is always set to 0 and is unaffected by a write
1292  *
1293  * operation, which ensures an even value is held in this register. If the
1294  *
1295  * value is 0, the serial output clock (sclk_out) is disabled. The frequency
1296  *
1297  * of the sclk_out is derived from the following equation:
1298  *
1299  * Fsclk_out = Fssi_clk/SCKDV
1300  *
1301  * where SCKDV is any even value between 2 and 65534. For example:
1302  *
1303  * for Fssi_clk = 3.6864MHz and SCKDV =2
1304  *
1305  * Fsclk_out = 3.6864/2 = 1.8432MHz
1306  *
1307  * Field Access Macros:
1308  *
1309  */
1310 /* The Least Significant Bit (LSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
1311 #define ALT_SPIM_BAUDR_SCKDV_LSB 0
1312 /* The Most Significant Bit (MSB) position of the ALT_SPIM_BAUDR_SCKDV register field. */
1313 #define ALT_SPIM_BAUDR_SCKDV_MSB 15
1314 /* The width in bits of the ALT_SPIM_BAUDR_SCKDV register field. */
1315 #define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
1316 /* The mask used to set the ALT_SPIM_BAUDR_SCKDV register field value. */
1317 #define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
1318 /* The mask used to clear the ALT_SPIM_BAUDR_SCKDV register field value. */
1319 #define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
1320 /* The reset value of the ALT_SPIM_BAUDR_SCKDV register field. */
1321 #define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
1322 /* Extracts the ALT_SPIM_BAUDR_SCKDV field value from a register. */
1323 #define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
1324 /* Produces a ALT_SPIM_BAUDR_SCKDV register field value suitable for setting the register. */
1325 #define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
1326 
1327 #ifndef __ASSEMBLY__
1328 /*
1329  * WARNING: The C register and register group struct declarations are provided for
1330  * convenience and illustrative purposes. They should, however, be used with
1331  * caution as the C language standard provides no guarantees about the alignment or
1332  * atomicity of device memory accesses. The recommended practice for writing
1333  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1334  * alt_write_word() functions.
1335  *
1336  * The struct declaration for register ALT_SPIM_BAUDR.
1337  */
1338 struct ALT_SPIM_BAUDR_s
1339 {
1340  uint32_t sckdv : 16; /* ALT_SPIM_BAUDR_SCKDV */
1341  uint32_t : 16; /* *UNDEFINED* */
1342 };
1343 
1344 /* The typedef declaration for register ALT_SPIM_BAUDR. */
1345 typedef volatile struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t;
1346 #endif /* __ASSEMBLY__ */
1347 
1348 /* The reset value of the ALT_SPIM_BAUDR register. */
1349 #define ALT_SPIM_BAUDR_RESET 0x00000000
1350 /* The byte offset of the ALT_SPIM_BAUDR register from the beginning of the component. */
1351 #define ALT_SPIM_BAUDR_OFST 0x14
1352 /* The address of the ALT_SPIM_BAUDR register. */
1353 #define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
1354 
1355 /*
1356  * Register : txftlr
1357  *
1358  * Transmit FIFO Threshold Level.
1359  *
1360  * This register controls the threshold value for the transmit FIFO memory.
1361  *
1362  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1363  *
1364  * Register Layout
1365  *
1366  * Bits | Access | Reset | Description
1367  * :-------|:-------|:------|:--------------------
1368  * [7:0] | RW | 0x0 | ALT_SPIM_TXFTLR_TFT
1369  * [31:8] | ??? | 0x0 | *UNDEFINED*
1370  *
1371  */
1372 /*
1373  * Field : tft
1374  *
1375  * Transmit FIFO Threshold.
1376  *
1377  * Controls the level of entries (or below) at which the transmit FIFO controller
1378  *
1379  * triggers an interrupt. The FIFO depth is configurable in the range 2-256;
1380  *
1381  * this register is sized to the number of address bits needed to access the
1382  *
1383  * FIFO. If you attempt to set this value greater than or equal to the depth
1384  *
1385  * of the FIFO, this field is not written and retains its current value. When
1386  *
1387  * the number of transmit FIFO entries is less than or equal to this value,
1388  *
1389  * the transmit FIFO empty interrupt is triggered.
1390  *
1391  * Field Access Macros:
1392  *
1393  */
1394 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1395 #define ALT_SPIM_TXFTLR_TFT_LSB 0
1396 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFTLR_TFT register field. */
1397 #define ALT_SPIM_TXFTLR_TFT_MSB 7
1398 /* The width in bits of the ALT_SPIM_TXFTLR_TFT register field. */
1399 #define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1400 /* The mask used to set the ALT_SPIM_TXFTLR_TFT register field value. */
1401 #define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1402 /* The mask used to clear the ALT_SPIM_TXFTLR_TFT register field value. */
1403 #define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1404 /* The reset value of the ALT_SPIM_TXFTLR_TFT register field. */
1405 #define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1406 /* Extracts the ALT_SPIM_TXFTLR_TFT field value from a register. */
1407 #define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1408 /* Produces a ALT_SPIM_TXFTLR_TFT register field value suitable for setting the register. */
1409 #define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1410 
1411 #ifndef __ASSEMBLY__
1412 /*
1413  * WARNING: The C register and register group struct declarations are provided for
1414  * convenience and illustrative purposes. They should, however, be used with
1415  * caution as the C language standard provides no guarantees about the alignment or
1416  * atomicity of device memory accesses. The recommended practice for writing
1417  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1418  * alt_write_word() functions.
1419  *
1420  * The struct declaration for register ALT_SPIM_TXFTLR.
1421  */
1422 struct ALT_SPIM_TXFTLR_s
1423 {
1424  uint32_t tft : 8; /* ALT_SPIM_TXFTLR_TFT */
1425  uint32_t : 24; /* *UNDEFINED* */
1426 };
1427 
1428 /* The typedef declaration for register ALT_SPIM_TXFTLR. */
1429 typedef volatile struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t;
1430 #endif /* __ASSEMBLY__ */
1431 
1432 /* The reset value of the ALT_SPIM_TXFTLR register. */
1433 #define ALT_SPIM_TXFTLR_RESET 0x00000000
1434 /* The byte offset of the ALT_SPIM_TXFTLR register from the beginning of the component. */
1435 #define ALT_SPIM_TXFTLR_OFST 0x18
1436 /* The address of the ALT_SPIM_TXFTLR register. */
1437 #define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
1438 
1439 /*
1440  * Register : rxftlr
1441  *
1442  * Receive FIFO Threshold level.
1443  *
1444  * This register controls the threshold value for the receive FIFO memory.
1445  *
1446  * The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
1447  *
1448  * Register Layout
1449  *
1450  * Bits | Access | Reset | Description
1451  * :-------|:-------|:------|:--------------------
1452  * [7:0] | RW | 0x0 | ALT_SPIM_RXFTLR_RFT
1453  * [31:8] | ??? | 0x0 | *UNDEFINED*
1454  *
1455  */
1456 /*
1457  * Field : rft
1458  *
1459  * Receive FIFO Threshold.
1460  *
1461  * Controls the level of entries (or above) at which the receive FIFO
1462  *
1463  * controller triggers an interrupt. The FIFO depth is configurable in
1464  *
1465  * the range 2-256. This register is sized to the number of address bits
1466  *
1467  * needed to access the FIFO. If you attempt to set this value greater
1468  *
1469  * than the depth of the FIFO, this field is not written and retains its
1470  *
1471  * current value. When the number of receive FIFO entries is greater than
1472  *
1473  * or equal to this value + 1, the receive FIFO full interrupt is triggered.
1474  *
1475  * Field Access Macros:
1476  *
1477  */
1478 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
1479 #define ALT_SPIM_RXFTLR_RFT_LSB 0
1480 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFTLR_RFT register field. */
1481 #define ALT_SPIM_RXFTLR_RFT_MSB 7
1482 /* The width in bits of the ALT_SPIM_RXFTLR_RFT register field. */
1483 #define ALT_SPIM_RXFTLR_RFT_WIDTH 8
1484 /* The mask used to set the ALT_SPIM_RXFTLR_RFT register field value. */
1485 #define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
1486 /* The mask used to clear the ALT_SPIM_RXFTLR_RFT register field value. */
1487 #define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
1488 /* The reset value of the ALT_SPIM_RXFTLR_RFT register field. */
1489 #define ALT_SPIM_RXFTLR_RFT_RESET 0x0
1490 /* Extracts the ALT_SPIM_RXFTLR_RFT field value from a register. */
1491 #define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1492 /* Produces a ALT_SPIM_RXFTLR_RFT register field value suitable for setting the register. */
1493 #define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1494 
1495 #ifndef __ASSEMBLY__
1496 /*
1497  * WARNING: The C register and register group struct declarations are provided for
1498  * convenience and illustrative purposes. They should, however, be used with
1499  * caution as the C language standard provides no guarantees about the alignment or
1500  * atomicity of device memory accesses. The recommended practice for writing
1501  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1502  * alt_write_word() functions.
1503  *
1504  * The struct declaration for register ALT_SPIM_RXFTLR.
1505  */
1506 struct ALT_SPIM_RXFTLR_s
1507 {
1508  uint32_t rft : 8; /* ALT_SPIM_RXFTLR_RFT */
1509  uint32_t : 24; /* *UNDEFINED* */
1510 };
1511 
1512 /* The typedef declaration for register ALT_SPIM_RXFTLR. */
1513 typedef volatile struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t;
1514 #endif /* __ASSEMBLY__ */
1515 
1516 /* The reset value of the ALT_SPIM_RXFTLR register. */
1517 #define ALT_SPIM_RXFTLR_RESET 0x00000000
1518 /* The byte offset of the ALT_SPIM_RXFTLR register from the beginning of the component. */
1519 #define ALT_SPIM_RXFTLR_OFST 0x1c
1520 /* The address of the ALT_SPIM_RXFTLR register. */
1521 #define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
1522 
1523 /*
1524  * Register : txflr
1525  *
1526  * Transmit FIFO Level Register
1527  *
1528  * Register Layout
1529  *
1530  * Bits | Access | Reset | Description
1531  * :-------|:-------|:------|:---------------------
1532  * [8:0] | R | 0x0 | ALT_SPIM_TXFLR_TXTFL
1533  * [31:9] | ??? | 0x0 | *UNDEFINED*
1534  *
1535  */
1536 /*
1537  * Field : txtfl
1538  *
1539  * Transmit FIFO Level.
1540  *
1541  * Contains the number of valid data entries in the transmit FIFO.
1542  *
1543  * Field Access Macros:
1544  *
1545  */
1546 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
1547 #define ALT_SPIM_TXFLR_TXTFL_LSB 0
1548 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXFLR_TXTFL register field. */
1549 #define ALT_SPIM_TXFLR_TXTFL_MSB 8
1550 /* The width in bits of the ALT_SPIM_TXFLR_TXTFL register field. */
1551 #define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
1552 /* The mask used to set the ALT_SPIM_TXFLR_TXTFL register field value. */
1553 #define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
1554 /* The mask used to clear the ALT_SPIM_TXFLR_TXTFL register field value. */
1555 #define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1556 /* The reset value of the ALT_SPIM_TXFLR_TXTFL register field. */
1557 #define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
1558 /* Extracts the ALT_SPIM_TXFLR_TXTFL field value from a register. */
1559 #define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1560 /* Produces a ALT_SPIM_TXFLR_TXTFL register field value suitable for setting the register. */
1561 #define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1562 
1563 #ifndef __ASSEMBLY__
1564 /*
1565  * WARNING: The C register and register group struct declarations are provided for
1566  * convenience and illustrative purposes. They should, however, be used with
1567  * caution as the C language standard provides no guarantees about the alignment or
1568  * atomicity of device memory accesses. The recommended practice for writing
1569  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1570  * alt_write_word() functions.
1571  *
1572  * The struct declaration for register ALT_SPIM_TXFLR.
1573  */
1574 struct ALT_SPIM_TXFLR_s
1575 {
1576  const uint32_t txtfl : 9; /* ALT_SPIM_TXFLR_TXTFL */
1577  uint32_t : 23; /* *UNDEFINED* */
1578 };
1579 
1580 /* The typedef declaration for register ALT_SPIM_TXFLR. */
1581 typedef volatile struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t;
1582 #endif /* __ASSEMBLY__ */
1583 
1584 /* The reset value of the ALT_SPIM_TXFLR register. */
1585 #define ALT_SPIM_TXFLR_RESET 0x00000000
1586 /* The byte offset of the ALT_SPIM_TXFLR register from the beginning of the component. */
1587 #define ALT_SPIM_TXFLR_OFST 0x20
1588 /* The address of the ALT_SPIM_TXFLR register. */
1589 #define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
1590 
1591 /*
1592  * Register : rxflr
1593  *
1594  * Receive FIFO Level Register
1595  *
1596  * Register Layout
1597  *
1598  * Bits | Access | Reset | Description
1599  * :-------|:-------|:------|:---------------------
1600  * [8:0] | R | 0x0 | ALT_SPIM_RXFLR_RXTFL
1601  * [31:9] | ??? | 0x0 | *UNDEFINED*
1602  *
1603  */
1604 /*
1605  * Field : rxtfl
1606  *
1607  * Receive FIFO Level.
1608  *
1609  * Contains the number of valid data entries in the receive FIFO.
1610  *
1611  * Field Access Macros:
1612  *
1613  */
1614 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
1615 #define ALT_SPIM_RXFLR_RXTFL_LSB 0
1616 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXFLR_RXTFL register field. */
1617 #define ALT_SPIM_RXFLR_RXTFL_MSB 8
1618 /* The width in bits of the ALT_SPIM_RXFLR_RXTFL register field. */
1619 #define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
1620 /* The mask used to set the ALT_SPIM_RXFLR_RXTFL register field value. */
1621 #define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
1622 /* The mask used to clear the ALT_SPIM_RXFLR_RXTFL register field value. */
1623 #define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1624 /* The reset value of the ALT_SPIM_RXFLR_RXTFL register field. */
1625 #define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
1626 /* Extracts the ALT_SPIM_RXFLR_RXTFL field value from a register. */
1627 #define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1628 /* Produces a ALT_SPIM_RXFLR_RXTFL register field value suitable for setting the register. */
1629 #define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1630 
1631 #ifndef __ASSEMBLY__
1632 /*
1633  * WARNING: The C register and register group struct declarations are provided for
1634  * convenience and illustrative purposes. They should, however, be used with
1635  * caution as the C language standard provides no guarantees about the alignment or
1636  * atomicity of device memory accesses. The recommended practice for writing
1637  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1638  * alt_write_word() functions.
1639  *
1640  * The struct declaration for register ALT_SPIM_RXFLR.
1641  */
1642 struct ALT_SPIM_RXFLR_s
1643 {
1644  const uint32_t rxtfl : 9; /* ALT_SPIM_RXFLR_RXTFL */
1645  uint32_t : 23; /* *UNDEFINED* */
1646 };
1647 
1648 /* The typedef declaration for register ALT_SPIM_RXFLR. */
1649 typedef volatile struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t;
1650 #endif /* __ASSEMBLY__ */
1651 
1652 /* The reset value of the ALT_SPIM_RXFLR register. */
1653 #define ALT_SPIM_RXFLR_RESET 0x00000000
1654 /* The byte offset of the ALT_SPIM_RXFLR register from the beginning of the component. */
1655 #define ALT_SPIM_RXFLR_OFST 0x24
1656 /* The address of the ALT_SPIM_RXFLR register. */
1657 #define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
1658 
1659 /*
1660  * Register : Status Register - sr
1661  *
1662  * This register is used to indicate the current transfer status, FIFO status, and
1663  * any transmission/reception errors that may have occurred. The status register
1664  * may be read at any time. None of the bits in this register request an interrupt.
1665  *
1666  * Register Layout
1667  *
1668  * Bits | Access | Reset | Description
1669  * :-------|:-------|:------|:-----------------------
1670  * [0] | R | 0x0 | SPI Busy Flag
1671  * [1] | R | 0x1 | Transmit FIFO Not Full
1672  * [2] | R | 0x1 | Transmit FIFO Empty
1673  * [3] | R | 0x0 | Receive FIFO Not Empty
1674  * [4] | R | 0x0 | Receive FIFO Full
1675  * [5] | ??? | 0x0 | *UNDEFINED*
1676  * [6] | R | 0x0 | Data Collision Error
1677  * [31:7] | ??? | 0x0 | *UNDEFINED*
1678  *
1679  */
1680 /*
1681  * Field : SPI Busy Flag - busy
1682  *
1683  * Reports the staus of a serial transfer
1684  *
1685  * Field Enumeration Values:
1686  *
1687  * Enum | Value | Description
1688  * :-------------------------|:------|:------------------------------------------
1689  * ALT_SPIM_SR_BUSY_E_INACT | 0x0 | SPI Master is inactive (idle or disabled)
1690  * ALT_SPIM_SR_BUSY_E_ACT | 0x1 | SPI Master is actively transferring data
1691  *
1692  * Field Access Macros:
1693  *
1694  */
1695 /*
1696  * Enumerated value for register field ALT_SPIM_SR_BUSY
1697  *
1698  * SPI Master is inactive (idle or disabled)
1699  */
1700 #define ALT_SPIM_SR_BUSY_E_INACT 0x0
1701 /*
1702  * Enumerated value for register field ALT_SPIM_SR_BUSY
1703  *
1704  * SPI Master is actively transferring data
1705  */
1706 #define ALT_SPIM_SR_BUSY_E_ACT 0x1
1707 
1708 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_BUSY register field. */
1709 #define ALT_SPIM_SR_BUSY_LSB 0
1710 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_BUSY register field. */
1711 #define ALT_SPIM_SR_BUSY_MSB 0
1712 /* The width in bits of the ALT_SPIM_SR_BUSY register field. */
1713 #define ALT_SPIM_SR_BUSY_WIDTH 1
1714 /* The mask used to set the ALT_SPIM_SR_BUSY register field value. */
1715 #define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
1716 /* The mask used to clear the ALT_SPIM_SR_BUSY register field value. */
1717 #define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
1718 /* The reset value of the ALT_SPIM_SR_BUSY register field. */
1719 #define ALT_SPIM_SR_BUSY_RESET 0x0
1720 /* Extracts the ALT_SPIM_SR_BUSY field value from a register. */
1721 #define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1722 /* Produces a ALT_SPIM_SR_BUSY register field value suitable for setting the register. */
1723 #define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1724 
1725 /*
1726  * Field : Transmit FIFO Not Full - tfnf
1727  *
1728  * Reports transmit FIFO condition.
1729  *
1730  * Field Enumeration Values:
1731  *
1732  * Enum | Value | Description
1733  * :---------------------------|:------|:--------------------------
1734  * ALT_SPIM_SR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
1735  * ALT_SPIM_SR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
1736  *
1737  * Field Access Macros:
1738  *
1739  */
1740 /*
1741  * Enumerated value for register field ALT_SPIM_SR_TFNF
1742  *
1743  * Transmit FIFO is full
1744  */
1745 #define ALT_SPIM_SR_TFNF_E_FULL 0x0
1746 /*
1747  * Enumerated value for register field ALT_SPIM_SR_TFNF
1748  *
1749  * Transmit FIFO is not full
1750  */
1751 #define ALT_SPIM_SR_TFNF_E_NOTFULL 0x1
1752 
1753 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFNF register field. */
1754 #define ALT_SPIM_SR_TFNF_LSB 1
1755 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFNF register field. */
1756 #define ALT_SPIM_SR_TFNF_MSB 1
1757 /* The width in bits of the ALT_SPIM_SR_TFNF register field. */
1758 #define ALT_SPIM_SR_TFNF_WIDTH 1
1759 /* The mask used to set the ALT_SPIM_SR_TFNF register field value. */
1760 #define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
1761 /* The mask used to clear the ALT_SPIM_SR_TFNF register field value. */
1762 #define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
1763 /* The reset value of the ALT_SPIM_SR_TFNF register field. */
1764 #define ALT_SPIM_SR_TFNF_RESET 0x1
1765 /* Extracts the ALT_SPIM_SR_TFNF field value from a register. */
1766 #define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1767 /* Produces a ALT_SPIM_SR_TFNF register field value suitable for setting the register. */
1768 #define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1769 
1770 /*
1771  * Field : Transmit FIFO Empty - tfe
1772  *
1773  * Reports transmit FIFO condition.
1774  *
1775  * Field Enumeration Values:
1776  *
1777  * Enum | Value | Description
1778  * :---------------------------|:------|:---------------------------
1779  * ALT_SPIM_SR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
1780  * ALT_SPIM_SR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
1781  *
1782  * Field Access Macros:
1783  *
1784  */
1785 /*
1786  * Enumerated value for register field ALT_SPIM_SR_TFE
1787  *
1788  * Transmit FIFO is not empty
1789  */
1790 #define ALT_SPIM_SR_TFE_E_NOTEMPTY 0x0
1791 /*
1792  * Enumerated value for register field ALT_SPIM_SR_TFE
1793  *
1794  * Transmit FIFO is empty
1795  */
1796 #define ALT_SPIM_SR_TFE_E_EMPTY 0x1
1797 
1798 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_TFE register field. */
1799 #define ALT_SPIM_SR_TFE_LSB 2
1800 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_TFE register field. */
1801 #define ALT_SPIM_SR_TFE_MSB 2
1802 /* The width in bits of the ALT_SPIM_SR_TFE register field. */
1803 #define ALT_SPIM_SR_TFE_WIDTH 1
1804 /* The mask used to set the ALT_SPIM_SR_TFE register field value. */
1805 #define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
1806 /* The mask used to clear the ALT_SPIM_SR_TFE register field value. */
1807 #define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
1808 /* The reset value of the ALT_SPIM_SR_TFE register field. */
1809 #define ALT_SPIM_SR_TFE_RESET 0x1
1810 /* Extracts the ALT_SPIM_SR_TFE field value from a register. */
1811 #define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1812 /* Produces a ALT_SPIM_SR_TFE register field value suitable for setting the register. */
1813 #define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1814 
1815 /*
1816  * Field : Receive FIFO Not Empty - rfne
1817  *
1818  * Reports receive FIFO condition.
1819  *
1820  * Field Enumeration Values:
1821  *
1822  * Enum | Value | Description
1823  * :----------------------------|:------|:--------------------------
1824  * ALT_SPIM_SR_RFNE_E_EMPTY | 0x0 | Receive FIFO is empty
1825  * ALT_SPIM_SR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
1826  *
1827  * Field Access Macros:
1828  *
1829  */
1830 /*
1831  * Enumerated value for register field ALT_SPIM_SR_RFNE
1832  *
1833  * Receive FIFO is empty
1834  */
1835 #define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
1836 /*
1837  * Enumerated value for register field ALT_SPIM_SR_RFNE
1838  *
1839  * Receive FIFO is not empty
1840  */
1841 #define ALT_SPIM_SR_RFNE_E_NOTEMPTY 0x1
1842 
1843 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFNE register field. */
1844 #define ALT_SPIM_SR_RFNE_LSB 3
1845 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFNE register field. */
1846 #define ALT_SPIM_SR_RFNE_MSB 3
1847 /* The width in bits of the ALT_SPIM_SR_RFNE register field. */
1848 #define ALT_SPIM_SR_RFNE_WIDTH 1
1849 /* The mask used to set the ALT_SPIM_SR_RFNE register field value. */
1850 #define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
1851 /* The mask used to clear the ALT_SPIM_SR_RFNE register field value. */
1852 #define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
1853 /* The reset value of the ALT_SPIM_SR_RFNE register field. */
1854 #define ALT_SPIM_SR_RFNE_RESET 0x0
1855 /* Extracts the ALT_SPIM_SR_RFNE field value from a register. */
1856 #define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1857 /* Produces a ALT_SPIM_SR_RFNE register field value suitable for setting the register. */
1858 #define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1859 
1860 /*
1861  * Field : Receive FIFO Full - rff
1862  *
1863  * Reports receive FIFO condition.
1864  *
1865  * Field Enumeration Values:
1866  *
1867  * Enum | Value | Description
1868  * :--------------------------|:------|:-------------------------
1869  * ALT_SPIM_SR_RFF_E_NOTFULL | 0x0 | Receive FIFO is not full
1870  * ALT_SPIM_SR_RFF_E_FULL | 0x1 | Receive FIFO is full
1871  *
1872  * Field Access Macros:
1873  *
1874  */
1875 /*
1876  * Enumerated value for register field ALT_SPIM_SR_RFF
1877  *
1878  * Receive FIFO is not full
1879  */
1880 #define ALT_SPIM_SR_RFF_E_NOTFULL 0x0
1881 /*
1882  * Enumerated value for register field ALT_SPIM_SR_RFF
1883  *
1884  * Receive FIFO is full
1885  */
1886 #define ALT_SPIM_SR_RFF_E_FULL 0x1
1887 
1888 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_RFF register field. */
1889 #define ALT_SPIM_SR_RFF_LSB 4
1890 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_RFF register field. */
1891 #define ALT_SPIM_SR_RFF_MSB 4
1892 /* The width in bits of the ALT_SPIM_SR_RFF register field. */
1893 #define ALT_SPIM_SR_RFF_WIDTH 1
1894 /* The mask used to set the ALT_SPIM_SR_RFF register field value. */
1895 #define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
1896 /* The mask used to clear the ALT_SPIM_SR_RFF register field value. */
1897 #define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
1898 /* The reset value of the ALT_SPIM_SR_RFF register field. */
1899 #define ALT_SPIM_SR_RFF_RESET 0x0
1900 /* Extracts the ALT_SPIM_SR_RFF field value from a register. */
1901 #define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1902 /* Produces a ALT_SPIM_SR_RFF register field value suitable for setting the register. */
1903 #define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1904 
1905 /*
1906  * Field : Data Collision Error - dcol
1907  *
1908  * Relevant only when the DW_apb_ssi is configured as a master device.
1909  *
1910  * This bit is set if the DW_apb_ssi master is actively transmitting when another
1911  * master
1912  *
1913  * selects this device as a slave. This informs the processor that the last data
1914  * transfer was
1915  *
1916  * halted before completion. This bit is cleared when read.
1917  *
1918  * Field Enumeration Values:
1919  *
1920  * Enum | Value | Description
1921  * :---------------------------|:------|:-----------------------------
1922  * ALT_SPIM_SR_DCOL_E_NOERROR | 0x0 | No error
1923  * ALT_SPIM_SR_DCOL_E_ERROR | 0x1 | Trasmit data collision error
1924  *
1925  * Field Access Macros:
1926  *
1927  */
1928 /*
1929  * Enumerated value for register field ALT_SPIM_SR_DCOL
1930  *
1931  * No error
1932  */
1933 #define ALT_SPIM_SR_DCOL_E_NOERROR 0x0
1934 /*
1935  * Enumerated value for register field ALT_SPIM_SR_DCOL
1936  *
1937  * Trasmit data collision error
1938  */
1939 #define ALT_SPIM_SR_DCOL_E_ERROR 0x1
1940 
1941 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SR_DCOL register field. */
1942 #define ALT_SPIM_SR_DCOL_LSB 6
1943 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SR_DCOL register field. */
1944 #define ALT_SPIM_SR_DCOL_MSB 6
1945 /* The width in bits of the ALT_SPIM_SR_DCOL register field. */
1946 #define ALT_SPIM_SR_DCOL_WIDTH 1
1947 /* The mask used to set the ALT_SPIM_SR_DCOL register field value. */
1948 #define ALT_SPIM_SR_DCOL_SET_MSK 0x00000040
1949 /* The mask used to clear the ALT_SPIM_SR_DCOL register field value. */
1950 #define ALT_SPIM_SR_DCOL_CLR_MSK 0xffffffbf
1951 /* The reset value of the ALT_SPIM_SR_DCOL register field. */
1952 #define ALT_SPIM_SR_DCOL_RESET 0x0
1953 /* Extracts the ALT_SPIM_SR_DCOL field value from a register. */
1954 #define ALT_SPIM_SR_DCOL_GET(value) (((value) & 0x00000040) >> 6)
1955 /* Produces a ALT_SPIM_SR_DCOL register field value suitable for setting the register. */
1956 #define ALT_SPIM_SR_DCOL_SET(value) (((value) << 6) & 0x00000040)
1957 
1958 #ifndef __ASSEMBLY__
1959 /*
1960  * WARNING: The C register and register group struct declarations are provided for
1961  * convenience and illustrative purposes. They should, however, be used with
1962  * caution as the C language standard provides no guarantees about the alignment or
1963  * atomicity of device memory accesses. The recommended practice for writing
1964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1965  * alt_write_word() functions.
1966  *
1967  * The struct declaration for register ALT_SPIM_SR.
1968  */
1969 struct ALT_SPIM_SR_s
1970 {
1971  const uint32_t busy : 1; /* SPI Busy Flag */
1972  const uint32_t tfnf : 1; /* Transmit FIFO Not Full */
1973  const uint32_t tfe : 1; /* Transmit FIFO Empty */
1974  const uint32_t rfne : 1; /* Receive FIFO Not Empty */
1975  const uint32_t rff : 1; /* Receive FIFO Full */
1976  uint32_t : 1; /* *UNDEFINED* */
1977  const uint32_t dcol : 1; /* Data Collision Error */
1978  uint32_t : 25; /* *UNDEFINED* */
1979 };
1980 
1981 /* The typedef declaration for register ALT_SPIM_SR. */
1982 typedef volatile struct ALT_SPIM_SR_s ALT_SPIM_SR_t;
1983 #endif /* __ASSEMBLY__ */
1984 
1985 /* The reset value of the ALT_SPIM_SR register. */
1986 #define ALT_SPIM_SR_RESET 0x00000006
1987 /* The byte offset of the ALT_SPIM_SR register from the beginning of the component. */
1988 #define ALT_SPIM_SR_OFST 0x28
1989 /* The address of the ALT_SPIM_SR register. */
1990 #define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
1991 
1992 /*
1993  * Register : imr
1994  *
1995  * Interrupt Mask Register
1996  *
1997  * Register Layout
1998  *
1999  * Bits | Access | Reset | Description
2000  * :-------|:-------|:------|:-------------------
2001  * [0] | RW | 0x1 | ALT_SPIM_IMR_TXEIM
2002  * [1] | RW | 0x1 | ALT_SPIM_IMR_TXOIM
2003  * [2] | RW | 0x1 | ALT_SPIM_IMR_RXUIM
2004  * [3] | RW | 0x1 | ALT_SPIM_IMR_RXOIM
2005  * [4] | RW | 0x1 | ALT_SPIM_IMR_RXFIM
2006  * [5] | RW | 0x1 | ALT_SPIM_IMR_MSTIM
2007  * [31:6] | ??? | 0x0 | *UNDEFINED*
2008  *
2009  */
2010 /*
2011  * Field : txeim
2012  *
2013  * Transmit FIFO Empty Interrupt Mask
2014  *
2015  * 0 - ssi_txe_intr interrupt is masked
2016  *
2017  * 1 - ssi_txe_intr interrupt is not masked
2018  *
2019  * Field Enumeration Values:
2020  *
2021  * Enum | Value | Description
2022  * :---------------------------|:------|:--------------------------------------------
2023  * ALT_SPIM_IMR_TXEIM_E_MSKED | 0x0 | spi_txe_intr interrupt is masked (disabled)
2024  * ALT_SPIM_IMR_TXEIM_E_END | 0x1 | spi_txe_intr interrupt is enabled
2025  *
2026  * Field Access Macros:
2027  *
2028  */
2029 /*
2030  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
2031  *
2032  * spi_txe_intr interrupt is masked (disabled)
2033  */
2034 #define ALT_SPIM_IMR_TXEIM_E_MSKED 0x0
2035 /*
2036  * Enumerated value for register field ALT_SPIM_IMR_TXEIM
2037  *
2038  * spi_txe_intr interrupt is enabled
2039  */
2040 #define ALT_SPIM_IMR_TXEIM_E_END 0x1
2041 
2042 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXEIM register field. */
2043 #define ALT_SPIM_IMR_TXEIM_LSB 0
2044 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXEIM register field. */
2045 #define ALT_SPIM_IMR_TXEIM_MSB 0
2046 /* The width in bits of the ALT_SPIM_IMR_TXEIM register field. */
2047 #define ALT_SPIM_IMR_TXEIM_WIDTH 1
2048 /* The mask used to set the ALT_SPIM_IMR_TXEIM register field value. */
2049 #define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
2050 /* The mask used to clear the ALT_SPIM_IMR_TXEIM register field value. */
2051 #define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
2052 /* The reset value of the ALT_SPIM_IMR_TXEIM register field. */
2053 #define ALT_SPIM_IMR_TXEIM_RESET 0x1
2054 /* Extracts the ALT_SPIM_IMR_TXEIM field value from a register. */
2055 #define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2056 /* Produces a ALT_SPIM_IMR_TXEIM register field value suitable for setting the register. */
2057 #define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2058 
2059 /*
2060  * Field : txoim
2061  *
2062  * Transmit FIFO Overflow Interrupt Mask
2063  *
2064  * 0 - ssi_txo_intr interrupt is masked
2065  *
2066  * 1 - ssi_txo_intr interrupt is not masked
2067  *
2068  * Field Enumeration Values:
2069  *
2070  * Enum | Value | Description
2071  * :---------------------------|:------|:--------------------------------------------
2072  * ALT_SPIM_IMR_TXOIM_E_MSKED | 0x0 | spi_txo_intr interrupt is masked (disabled)
2073  * ALT_SPIM_IMR_TXOIM_E_END | 0x1 | spi_txo_intr interrupt is enabled
2074  *
2075  * Field Access Macros:
2076  *
2077  */
2078 /*
2079  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
2080  *
2081  * spi_txo_intr interrupt is masked (disabled)
2082  */
2083 #define ALT_SPIM_IMR_TXOIM_E_MSKED 0x0
2084 /*
2085  * Enumerated value for register field ALT_SPIM_IMR_TXOIM
2086  *
2087  * spi_txo_intr interrupt is enabled
2088  */
2089 #define ALT_SPIM_IMR_TXOIM_E_END 0x1
2090 
2091 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_TXOIM register field. */
2092 #define ALT_SPIM_IMR_TXOIM_LSB 1
2093 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_TXOIM register field. */
2094 #define ALT_SPIM_IMR_TXOIM_MSB 1
2095 /* The width in bits of the ALT_SPIM_IMR_TXOIM register field. */
2096 #define ALT_SPIM_IMR_TXOIM_WIDTH 1
2097 /* The mask used to set the ALT_SPIM_IMR_TXOIM register field value. */
2098 #define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
2099 /* The mask used to clear the ALT_SPIM_IMR_TXOIM register field value. */
2100 #define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
2101 /* The reset value of the ALT_SPIM_IMR_TXOIM register field. */
2102 #define ALT_SPIM_IMR_TXOIM_RESET 0x1
2103 /* Extracts the ALT_SPIM_IMR_TXOIM field value from a register. */
2104 #define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2105 /* Produces a ALT_SPIM_IMR_TXOIM register field value suitable for setting the register. */
2106 #define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2107 
2108 /*
2109  * Field : rxuim
2110  *
2111  * Receive FIFO Underflow Interrupt Mask
2112  *
2113  * 0 - ssi_rxu_intr interrupt is masked
2114  *
2115  * 1 - ssi_rxu_intr interrupt is not masked
2116  *
2117  * Field Enumeration Values:
2118  *
2119  * Enum | Value | Description
2120  * :---------------------------|:------|:--------------------------------------------
2121  * ALT_SPIM_IMR_RXUIM_E_MSKED | 0x0 | spi_rxu_intr interrupt is masked (disabled)
2122  * ALT_SPIM_IMR_RXUIM_E_END | 0x1 | spi_rxu_intr interrupt is enabled
2123  *
2124  * Field Access Macros:
2125  *
2126  */
2127 /*
2128  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
2129  *
2130  * spi_rxu_intr interrupt is masked (disabled)
2131  */
2132 #define ALT_SPIM_IMR_RXUIM_E_MSKED 0x0
2133 /*
2134  * Enumerated value for register field ALT_SPIM_IMR_RXUIM
2135  *
2136  * spi_rxu_intr interrupt is enabled
2137  */
2138 #define ALT_SPIM_IMR_RXUIM_E_END 0x1
2139 
2140 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXUIM register field. */
2141 #define ALT_SPIM_IMR_RXUIM_LSB 2
2142 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXUIM register field. */
2143 #define ALT_SPIM_IMR_RXUIM_MSB 2
2144 /* The width in bits of the ALT_SPIM_IMR_RXUIM register field. */
2145 #define ALT_SPIM_IMR_RXUIM_WIDTH 1
2146 /* The mask used to set the ALT_SPIM_IMR_RXUIM register field value. */
2147 #define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
2148 /* The mask used to clear the ALT_SPIM_IMR_RXUIM register field value. */
2149 #define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
2150 /* The reset value of the ALT_SPIM_IMR_RXUIM register field. */
2151 #define ALT_SPIM_IMR_RXUIM_RESET 0x1
2152 /* Extracts the ALT_SPIM_IMR_RXUIM field value from a register. */
2153 #define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2154 /* Produces a ALT_SPIM_IMR_RXUIM register field value suitable for setting the register. */
2155 #define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2156 
2157 /*
2158  * Field : rxoim
2159  *
2160  * Receive FIFO Overflow Interrupt Mask
2161  *
2162  * 0 - ssi_rxo_intr interrupt is masked
2163  *
2164  * 1 - ssi_rxo_intr interrupt is not masked
2165  *
2166  * Field Enumeration Values:
2167  *
2168  * Enum | Value | Description
2169  * :---------------------------|:------|:--------------------------------------------
2170  * ALT_SPIM_IMR_RXOIM_E_MSKED | 0x0 | spi_rxo_intr interrupt is masked (disabled)
2171  * ALT_SPIM_IMR_RXOIM_E_END | 0x1 | spi_rxo_intr interrupt is enabled
2172  *
2173  * Field Access Macros:
2174  *
2175  */
2176 /*
2177  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
2178  *
2179  * spi_rxo_intr interrupt is masked (disabled)
2180  */
2181 #define ALT_SPIM_IMR_RXOIM_E_MSKED 0x0
2182 /*
2183  * Enumerated value for register field ALT_SPIM_IMR_RXOIM
2184  *
2185  * spi_rxo_intr interrupt is enabled
2186  */
2187 #define ALT_SPIM_IMR_RXOIM_E_END 0x1
2188 
2189 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXOIM register field. */
2190 #define ALT_SPIM_IMR_RXOIM_LSB 3
2191 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXOIM register field. */
2192 #define ALT_SPIM_IMR_RXOIM_MSB 3
2193 /* The width in bits of the ALT_SPIM_IMR_RXOIM register field. */
2194 #define ALT_SPIM_IMR_RXOIM_WIDTH 1
2195 /* The mask used to set the ALT_SPIM_IMR_RXOIM register field value. */
2196 #define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
2197 /* The mask used to clear the ALT_SPIM_IMR_RXOIM register field value. */
2198 #define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
2199 /* The reset value of the ALT_SPIM_IMR_RXOIM register field. */
2200 #define ALT_SPIM_IMR_RXOIM_RESET 0x1
2201 /* Extracts the ALT_SPIM_IMR_RXOIM field value from a register. */
2202 #define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2203 /* Produces a ALT_SPIM_IMR_RXOIM register field value suitable for setting the register. */
2204 #define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2205 
2206 /*
2207  * Field : rxfim
2208  *
2209  * Receive FIFO Full Interrupt Mask
2210  *
2211  * 0 - ssi_rxf_intr interrupt is masked
2212  *
2213  * 1 - ssi_rxf_intr interrupt is not masked
2214  *
2215  * Field Enumeration Values:
2216  *
2217  * Enum | Value | Description
2218  * :---------------------------|:------|:--------------------------------------------
2219  * ALT_SPIM_IMR_RXFIM_E_MSKED | 0x0 | spi_rxf_intr interrupt is masked (disabled)
2220  * ALT_SPIM_IMR_RXFIM_E_END | 0x1 | spi_rxf_intr interrupt is enabled
2221  *
2222  * Field Access Macros:
2223  *
2224  */
2225 /*
2226  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
2227  *
2228  * spi_rxf_intr interrupt is masked (disabled)
2229  */
2230 #define ALT_SPIM_IMR_RXFIM_E_MSKED 0x0
2231 /*
2232  * Enumerated value for register field ALT_SPIM_IMR_RXFIM
2233  *
2234  * spi_rxf_intr interrupt is enabled
2235  */
2236 #define ALT_SPIM_IMR_RXFIM_E_END 0x1
2237 
2238 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_RXFIM register field. */
2239 #define ALT_SPIM_IMR_RXFIM_LSB 4
2240 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_RXFIM register field. */
2241 #define ALT_SPIM_IMR_RXFIM_MSB 4
2242 /* The width in bits of the ALT_SPIM_IMR_RXFIM register field. */
2243 #define ALT_SPIM_IMR_RXFIM_WIDTH 1
2244 /* The mask used to set the ALT_SPIM_IMR_RXFIM register field value. */
2245 #define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
2246 /* The mask used to clear the ALT_SPIM_IMR_RXFIM register field value. */
2247 #define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
2248 /* The reset value of the ALT_SPIM_IMR_RXFIM register field. */
2249 #define ALT_SPIM_IMR_RXFIM_RESET 0x1
2250 /* Extracts the ALT_SPIM_IMR_RXFIM field value from a register. */
2251 #define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2252 /* Produces a ALT_SPIM_IMR_RXFIM register field value suitable for setting the register. */
2253 #define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2254 
2255 /*
2256  * Field : mstim
2257  *
2258  * Multi-Master Contention Interrupt Mask. This bit field is not present if
2259  *
2260  * the DW_apb_ssi is configured as a serial-slave device.
2261  *
2262  * 0 - ssi_mst_intr interrupt is masked
2263  *
2264  * 1 - ssi_mst_intr interrupt is not masked
2265  *
2266  * Field Access Macros:
2267  *
2268  */
2269 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IMR_MSTIM register field. */
2270 #define ALT_SPIM_IMR_MSTIM_LSB 5
2271 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IMR_MSTIM register field. */
2272 #define ALT_SPIM_IMR_MSTIM_MSB 5
2273 /* The width in bits of the ALT_SPIM_IMR_MSTIM register field. */
2274 #define ALT_SPIM_IMR_MSTIM_WIDTH 1
2275 /* The mask used to set the ALT_SPIM_IMR_MSTIM register field value. */
2276 #define ALT_SPIM_IMR_MSTIM_SET_MSK 0x00000020
2277 /* The mask used to clear the ALT_SPIM_IMR_MSTIM register field value. */
2278 #define ALT_SPIM_IMR_MSTIM_CLR_MSK 0xffffffdf
2279 /* The reset value of the ALT_SPIM_IMR_MSTIM register field. */
2280 #define ALT_SPIM_IMR_MSTIM_RESET 0x1
2281 /* Extracts the ALT_SPIM_IMR_MSTIM field value from a register. */
2282 #define ALT_SPIM_IMR_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
2283 /* Produces a ALT_SPIM_IMR_MSTIM register field value suitable for setting the register. */
2284 #define ALT_SPIM_IMR_MSTIM_SET(value) (((value) << 5) & 0x00000020)
2285 
2286 #ifndef __ASSEMBLY__
2287 /*
2288  * WARNING: The C register and register group struct declarations are provided for
2289  * convenience and illustrative purposes. They should, however, be used with
2290  * caution as the C language standard provides no guarantees about the alignment or
2291  * atomicity of device memory accesses. The recommended practice for writing
2292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2293  * alt_write_word() functions.
2294  *
2295  * The struct declaration for register ALT_SPIM_IMR.
2296  */
2297 struct ALT_SPIM_IMR_s
2298 {
2299  uint32_t txeim : 1; /* ALT_SPIM_IMR_TXEIM */
2300  uint32_t txoim : 1; /* ALT_SPIM_IMR_TXOIM */
2301  uint32_t rxuim : 1; /* ALT_SPIM_IMR_RXUIM */
2302  uint32_t rxoim : 1; /* ALT_SPIM_IMR_RXOIM */
2303  uint32_t rxfim : 1; /* ALT_SPIM_IMR_RXFIM */
2304  uint32_t mstim : 1; /* ALT_SPIM_IMR_MSTIM */
2305  uint32_t : 26; /* *UNDEFINED* */
2306 };
2307 
2308 /* The typedef declaration for register ALT_SPIM_IMR. */
2309 typedef volatile struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t;
2310 #endif /* __ASSEMBLY__ */
2311 
2312 /* The reset value of the ALT_SPIM_IMR register. */
2313 #define ALT_SPIM_IMR_RESET 0x0000003f
2314 /* The byte offset of the ALT_SPIM_IMR register from the beginning of the component. */
2315 #define ALT_SPIM_IMR_OFST 0x2c
2316 /* The address of the ALT_SPIM_IMR register. */
2317 #define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
2318 
2319 /*
2320  * Register : isr
2321  *
2322  * Interrupt Status Register
2323  *
2324  * Register Layout
2325  *
2326  * Bits | Access | Reset | Description
2327  * :-------|:-------|:------|:-------------------
2328  * [0] | R | 0x0 | ALT_SPIM_ISR_TXEIS
2329  * [1] | R | 0x0 | ALT_SPIM_ISR_TXOIS
2330  * [2] | R | 0x0 | ALT_SPIM_ISR_RXUIS
2331  * [3] | R | 0x0 | ALT_SPIM_ISR_RXOIS
2332  * [4] | R | 0x0 | ALT_SPIM_ISR_RXFIS
2333  * [5] | R | 0x0 | ALT_SPIM_ISR_MSTIS
2334  * [31:6] | ??? | 0x0 | *UNDEFINED*
2335  *
2336  */
2337 /*
2338  * Field : txeis
2339  *
2340  * Transmit FIFO Empty Interrupt Status
2341  *
2342  * 0 = ssi_txe_intr interrupt is not active after masking
2343  *
2344  * 1 = ssi_txe_intr interrupt is active after masking
2345  *
2346  * Field Enumeration Values:
2347  *
2348  * Enum | Value | Description
2349  * :---------------------------|:------|:-----------------------------------------------
2350  * ALT_SPIM_ISR_TXEIS_E_INACT | 0x0 | spi_txe_intr interrupt is not active after
2351  * : | | masking
2352  * ALT_SPIM_ISR_TXEIS_E_ACT | 0x1 | spi_txe_intr interrupt is active after masking
2353  *
2354  * Field Access Macros:
2355  *
2356  */
2357 /*
2358  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
2359  *
2360  * spi_txe_intr interrupt is not active after masking
2361  */
2362 #define ALT_SPIM_ISR_TXEIS_E_INACT 0x0
2363 /*
2364  * Enumerated value for register field ALT_SPIM_ISR_TXEIS
2365  *
2366  * spi_txe_intr interrupt is active after masking
2367  */
2368 #define ALT_SPIM_ISR_TXEIS_E_ACT 0x1
2369 
2370 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXEIS register field. */
2371 #define ALT_SPIM_ISR_TXEIS_LSB 0
2372 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXEIS register field. */
2373 #define ALT_SPIM_ISR_TXEIS_MSB 0
2374 /* The width in bits of the ALT_SPIM_ISR_TXEIS register field. */
2375 #define ALT_SPIM_ISR_TXEIS_WIDTH 1
2376 /* The mask used to set the ALT_SPIM_ISR_TXEIS register field value. */
2377 #define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
2378 /* The mask used to clear the ALT_SPIM_ISR_TXEIS register field value. */
2379 #define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
2380 /* The reset value of the ALT_SPIM_ISR_TXEIS register field. */
2381 #define ALT_SPIM_ISR_TXEIS_RESET 0x0
2382 /* Extracts the ALT_SPIM_ISR_TXEIS field value from a register. */
2383 #define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2384 /* Produces a ALT_SPIM_ISR_TXEIS register field value suitable for setting the register. */
2385 #define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2386 
2387 /*
2388  * Field : txois
2389  *
2390  * Transmit FIFO Overflow Interrupt Status
2391  *
2392  * 0 = ssi_txo_intr interrupt is not active after masking
2393  *
2394  * 1 = ssi_txo_intr interrupt is active after masking
2395  *
2396  * Field Enumeration Values:
2397  *
2398  * Enum | Value | Description
2399  * :---------------------------|:------|:-----------------------------------------------
2400  * ALT_SPIM_ISR_TXOIS_E_INACT | 0x0 | spi_txo_intr interrupt is not active after
2401  * : | | masking
2402  * ALT_SPIM_ISR_TXOIS_E_ACT | 0x1 | spi_txo_intr interrupt is active after masking
2403  *
2404  * Field Access Macros:
2405  *
2406  */
2407 /*
2408  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
2409  *
2410  * spi_txo_intr interrupt is not active after masking
2411  */
2412 #define ALT_SPIM_ISR_TXOIS_E_INACT 0x0
2413 /*
2414  * Enumerated value for register field ALT_SPIM_ISR_TXOIS
2415  *
2416  * spi_txo_intr interrupt is active after masking
2417  */
2418 #define ALT_SPIM_ISR_TXOIS_E_ACT 0x1
2419 
2420 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXOIS register field. */
2421 #define ALT_SPIM_ISR_TXOIS_LSB 1
2422 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXOIS register field. */
2423 #define ALT_SPIM_ISR_TXOIS_MSB 1
2424 /* The width in bits of the ALT_SPIM_ISR_TXOIS register field. */
2425 #define ALT_SPIM_ISR_TXOIS_WIDTH 1
2426 /* The mask used to set the ALT_SPIM_ISR_TXOIS register field value. */
2427 #define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
2428 /* The mask used to clear the ALT_SPIM_ISR_TXOIS register field value. */
2429 #define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
2430 /* The reset value of the ALT_SPIM_ISR_TXOIS register field. */
2431 #define ALT_SPIM_ISR_TXOIS_RESET 0x0
2432 /* Extracts the ALT_SPIM_ISR_TXOIS field value from a register. */
2433 #define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2434 /* Produces a ALT_SPIM_ISR_TXOIS register field value suitable for setting the register. */
2435 #define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2436 
2437 /*
2438  * Field : rxuis
2439  *
2440  * Receive FIFO Underflow Interrupt Status
2441  *
2442  * 0 = ssi_rxu_intr interrupt is not active after masking
2443  *
2444  * 1 = ssi_rxu_intr interrupt is active after masking
2445  *
2446  * Field Enumeration Values:
2447  *
2448  * Enum | Value | Description
2449  * :---------------------------|:------|:-----------------------------------------------
2450  * ALT_SPIM_ISR_RXUIS_E_INACT | 0x0 | spi_rxu_intr interrupt is not active after
2451  * : | | masking
2452  * ALT_SPIM_ISR_RXUIS_E_ACT | 0x1 | spi_rxu_intr interrupt is active after masking
2453  *
2454  * Field Access Macros:
2455  *
2456  */
2457 /*
2458  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
2459  *
2460  * spi_rxu_intr interrupt is not active after masking
2461  */
2462 #define ALT_SPIM_ISR_RXUIS_E_INACT 0x0
2463 /*
2464  * Enumerated value for register field ALT_SPIM_ISR_RXUIS
2465  *
2466  * spi_rxu_intr interrupt is active after masking
2467  */
2468 #define ALT_SPIM_ISR_RXUIS_E_ACT 0x1
2469 
2470 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXUIS register field. */
2471 #define ALT_SPIM_ISR_RXUIS_LSB 2
2472 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXUIS register field. */
2473 #define ALT_SPIM_ISR_RXUIS_MSB 2
2474 /* The width in bits of the ALT_SPIM_ISR_RXUIS register field. */
2475 #define ALT_SPIM_ISR_RXUIS_WIDTH 1
2476 /* The mask used to set the ALT_SPIM_ISR_RXUIS register field value. */
2477 #define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
2478 /* The mask used to clear the ALT_SPIM_ISR_RXUIS register field value. */
2479 #define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
2480 /* The reset value of the ALT_SPIM_ISR_RXUIS register field. */
2481 #define ALT_SPIM_ISR_RXUIS_RESET 0x0
2482 /* Extracts the ALT_SPIM_ISR_RXUIS field value from a register. */
2483 #define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2484 /* Produces a ALT_SPIM_ISR_RXUIS register field value suitable for setting the register. */
2485 #define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2486 
2487 /*
2488  * Field : rxois
2489  *
2490  * Receive FIFO Overflow Interrupt Status
2491  *
2492  * 0 = ssi_rxo_intr interrupt is not active after masking
2493  *
2494  * 1 = ssi_rxo_intr interrupt is active after masking
2495  *
2496  * Field Enumeration Values:
2497  *
2498  * Enum | Value | Description
2499  * :---------------------------|:------|:-----------------------------------------------
2500  * ALT_SPIM_ISR_RXOIS_E_INACT | 0x0 | spi_rxo_intr interrupt is not active after
2501  * : | | masking
2502  * ALT_SPIM_ISR_RXOIS_E_ACT | 0x1 | spi_rxo_intr interrupt is active after masking
2503  *
2504  * Field Access Macros:
2505  *
2506  */
2507 /*
2508  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
2509  *
2510  * spi_rxo_intr interrupt is not active after masking
2511  */
2512 #define ALT_SPIM_ISR_RXOIS_E_INACT 0x0
2513 /*
2514  * Enumerated value for register field ALT_SPIM_ISR_RXOIS
2515  *
2516  * spi_rxo_intr interrupt is active after masking
2517  */
2518 #define ALT_SPIM_ISR_RXOIS_E_ACT 0x1
2519 
2520 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXOIS register field. */
2521 #define ALT_SPIM_ISR_RXOIS_LSB 3
2522 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXOIS register field. */
2523 #define ALT_SPIM_ISR_RXOIS_MSB 3
2524 /* The width in bits of the ALT_SPIM_ISR_RXOIS register field. */
2525 #define ALT_SPIM_ISR_RXOIS_WIDTH 1
2526 /* The mask used to set the ALT_SPIM_ISR_RXOIS register field value. */
2527 #define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
2528 /* The mask used to clear the ALT_SPIM_ISR_RXOIS register field value. */
2529 #define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
2530 /* The reset value of the ALT_SPIM_ISR_RXOIS register field. */
2531 #define ALT_SPIM_ISR_RXOIS_RESET 0x0
2532 /* Extracts the ALT_SPIM_ISR_RXOIS field value from a register. */
2533 #define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2534 /* Produces a ALT_SPIM_ISR_RXOIS register field value suitable for setting the register. */
2535 #define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2536 
2537 /*
2538  * Field : rxfis
2539  *
2540  * Receive FIFO Full Interrupt Status
2541  *
2542  * 0 = ssi_rxf_intr interrupt is not active after masking
2543  *
2544  * 1 = ssi_rxf_intr interrupt is full after masking
2545  *
2546  * Field Enumeration Values:
2547  *
2548  * Enum | Value | Description
2549  * :---------------------------|:------|:---------------------------------------------
2550  * ALT_SPIM_ISR_RXFIS_E_INACT | 0x0 | spi_rxf_intr interrupt is not active after
2551  * : | | masking
2552  * ALT_SPIM_ISR_RXFIS_E_ACT | 0x1 | spi_rxf_intr interrupt is full after masking
2553  *
2554  * Field Access Macros:
2555  *
2556  */
2557 /*
2558  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
2559  *
2560  * spi_rxf_intr interrupt is not active after masking
2561  */
2562 #define ALT_SPIM_ISR_RXFIS_E_INACT 0x0
2563 /*
2564  * Enumerated value for register field ALT_SPIM_ISR_RXFIS
2565  *
2566  * spi_rxf_intr interrupt is full after masking
2567  */
2568 #define ALT_SPIM_ISR_RXFIS_E_ACT 0x1
2569 
2570 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXFIS register field. */
2571 #define ALT_SPIM_ISR_RXFIS_LSB 4
2572 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXFIS register field. */
2573 #define ALT_SPIM_ISR_RXFIS_MSB 4
2574 /* The width in bits of the ALT_SPIM_ISR_RXFIS register field. */
2575 #define ALT_SPIM_ISR_RXFIS_WIDTH 1
2576 /* The mask used to set the ALT_SPIM_ISR_RXFIS register field value. */
2577 #define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
2578 /* The mask used to clear the ALT_SPIM_ISR_RXFIS register field value. */
2579 #define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
2580 /* The reset value of the ALT_SPIM_ISR_RXFIS register field. */
2581 #define ALT_SPIM_ISR_RXFIS_RESET 0x0
2582 /* Extracts the ALT_SPIM_ISR_RXFIS field value from a register. */
2583 #define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2584 /* Produces a ALT_SPIM_ISR_RXFIS register field value suitable for setting the register. */
2585 #define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2586 
2587 /*
2588  * Field : mstis
2589  *
2590  * Multi-Master Contention Interrupt Status. This bit field is not present
2591  *
2592  * if the DW_apb_ssi is configured as a serial-slave device.
2593  *
2594  * 0 = ssi_mst_intr interrupt not active after masking
2595  *
2596  * 1 = ssi_mst_intr interrupt is active after masking
2597  *
2598  * Field Enumeration Values:
2599  *
2600  * Enum | Value | Description
2601  * :---------------------------|:------|:--------------------------------------------
2602  * ALT_SPIM_ISR_MSTIS_E_INACT | 0x0 | 0 = ssi_mst_intr interrupt not active after
2603  * : | | masking
2604  * ALT_SPIM_ISR_MSTIS_E_ACT | 0x1 | 1 = ssi_mst_intr interrupt is active after
2605  * : | | masking
2606  *
2607  * Field Access Macros:
2608  *
2609  */
2610 /*
2611  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
2612  *
2613  * 0 = ssi_mst_intr interrupt not active after masking
2614  */
2615 #define ALT_SPIM_ISR_MSTIS_E_INACT 0x0
2616 /*
2617  * Enumerated value for register field ALT_SPIM_ISR_MSTIS
2618  *
2619  * 1 = ssi_mst_intr interrupt is active after masking
2620  */
2621 #define ALT_SPIM_ISR_MSTIS_E_ACT 0x1
2622 
2623 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_MSTIS register field. */
2624 #define ALT_SPIM_ISR_MSTIS_LSB 5
2625 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_MSTIS register field. */
2626 #define ALT_SPIM_ISR_MSTIS_MSB 5
2627 /* The width in bits of the ALT_SPIM_ISR_MSTIS register field. */
2628 #define ALT_SPIM_ISR_MSTIS_WIDTH 1
2629 /* The mask used to set the ALT_SPIM_ISR_MSTIS register field value. */
2630 #define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
2631 /* The mask used to clear the ALT_SPIM_ISR_MSTIS register field value. */
2632 #define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
2633 /* The reset value of the ALT_SPIM_ISR_MSTIS register field. */
2634 #define ALT_SPIM_ISR_MSTIS_RESET 0x0
2635 /* Extracts the ALT_SPIM_ISR_MSTIS field value from a register. */
2636 #define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2637 /* Produces a ALT_SPIM_ISR_MSTIS register field value suitable for setting the register. */
2638 #define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2639 
2640 #ifndef __ASSEMBLY__
2641 /*
2642  * WARNING: The C register and register group struct declarations are provided for
2643  * convenience and illustrative purposes. They should, however, be used with
2644  * caution as the C language standard provides no guarantees about the alignment or
2645  * atomicity of device memory accesses. The recommended practice for writing
2646  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2647  * alt_write_word() functions.
2648  *
2649  * The struct declaration for register ALT_SPIM_ISR.
2650  */
2651 struct ALT_SPIM_ISR_s
2652 {
2653  const uint32_t txeis : 1; /* ALT_SPIM_ISR_TXEIS */
2654  const uint32_t txois : 1; /* ALT_SPIM_ISR_TXOIS */
2655  const uint32_t rxuis : 1; /* ALT_SPIM_ISR_RXUIS */
2656  const uint32_t rxois : 1; /* ALT_SPIM_ISR_RXOIS */
2657  const uint32_t rxfis : 1; /* ALT_SPIM_ISR_RXFIS */
2658  const uint32_t mstis : 1; /* ALT_SPIM_ISR_MSTIS */
2659  uint32_t : 26; /* *UNDEFINED* */
2660 };
2661 
2662 /* The typedef declaration for register ALT_SPIM_ISR. */
2663 typedef volatile struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t;
2664 #endif /* __ASSEMBLY__ */
2665 
2666 /* The reset value of the ALT_SPIM_ISR register. */
2667 #define ALT_SPIM_ISR_RESET 0x00000000
2668 /* The byte offset of the ALT_SPIM_ISR register from the beginning of the component. */
2669 #define ALT_SPIM_ISR_OFST 0x30
2670 /* The address of the ALT_SPIM_ISR register. */
2671 #define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
2672 
2673 /*
2674  * Register : risr
2675  *
2676  * Raw Interrupt StatusRegister
2677  *
2678  * Register Layout
2679  *
2680  * Bits | Access | Reset | Description
2681  * :-------|:-------|:------|:--------------------
2682  * [0] | R | 0x0 | ALT_SPIM_RISR_TXEIR
2683  * [1] | R | 0x0 | ALT_SPIM_RISR_TXOIR
2684  * [2] | R | 0x0 | ALT_SPIM_RISR_RXUIR
2685  * [3] | R | 0x0 | ALT_SPIM_RISR_RXOIR
2686  * [4] | R | 0x0 | ALT_SPIM_RISR_RXFIR
2687  * [5] | R | 0x0 | ALT_SPIM_RISR_MSTIR
2688  * [31:6] | ??? | 0x0 | *UNDEFINED*
2689  *
2690  */
2691 /*
2692  * Field : txeir
2693  *
2694  * Transmit FIFO Empty Raw Interrupt Status
2695  *
2696  * 0 = ssi_txe_intr interrupt is not active prior to masking
2697  *
2698  * 1 = ssi_txe_intr interrupt is active prior masking
2699  *
2700  * Field Enumeration Values:
2701  *
2702  * Enum | Value | Description
2703  * :----------------------------|:------|:-----------------------------------------------
2704  * ALT_SPIM_RISR_TXEIR_E_INACT | 0x0 | spi_txe_intr interrupt is not active prior to
2705  * : | | masking
2706  * ALT_SPIM_RISR_TXEIR_E_ACT | 0x1 | spi_txe_intr interrupt is active prior masking
2707  *
2708  * Field Access Macros:
2709  *
2710  */
2711 /*
2712  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
2713  *
2714  * spi_txe_intr interrupt is not active prior to masking
2715  */
2716 #define ALT_SPIM_RISR_TXEIR_E_INACT 0x0
2717 /*
2718  * Enumerated value for register field ALT_SPIM_RISR_TXEIR
2719  *
2720  * spi_txe_intr interrupt is active prior masking
2721  */
2722 #define ALT_SPIM_RISR_TXEIR_E_ACT 0x1
2723 
2724 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXEIR register field. */
2725 #define ALT_SPIM_RISR_TXEIR_LSB 0
2726 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXEIR register field. */
2727 #define ALT_SPIM_RISR_TXEIR_MSB 0
2728 /* The width in bits of the ALT_SPIM_RISR_TXEIR register field. */
2729 #define ALT_SPIM_RISR_TXEIR_WIDTH 1
2730 /* The mask used to set the ALT_SPIM_RISR_TXEIR register field value. */
2731 #define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
2732 /* The mask used to clear the ALT_SPIM_RISR_TXEIR register field value. */
2733 #define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
2734 /* The reset value of the ALT_SPIM_RISR_TXEIR register field. */
2735 #define ALT_SPIM_RISR_TXEIR_RESET 0x0
2736 /* Extracts the ALT_SPIM_RISR_TXEIR field value from a register. */
2737 #define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2738 /* Produces a ALT_SPIM_RISR_TXEIR register field value suitable for setting the register. */
2739 #define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2740 
2741 /*
2742  * Field : txoir
2743  *
2744  * Transmit FIFO Overflow Raw Interrupt Status
2745  *
2746  * 0 = ssi_txo_intr interrupt is not active prior to masking
2747  *
2748  * 1 = ssi_txo_intr interrupt is active prior masking
2749  *
2750  * Field Enumeration Values:
2751  *
2752  * Enum | Value | Description
2753  * :----------------------------|:------|:-----------------------------------------------
2754  * ALT_SPIM_RISR_TXOIR_E_INACT | 0x0 | spi_txo_intr interrupt is not active prior to
2755  * : | | masking
2756  * ALT_SPIM_RISR_TXOIR_E_ACT | 0x1 | spi_txo_intr interrupt is active prior masking
2757  *
2758  * Field Access Macros:
2759  *
2760  */
2761 /*
2762  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
2763  *
2764  * spi_txo_intr interrupt is not active prior to masking
2765  */
2766 #define ALT_SPIM_RISR_TXOIR_E_INACT 0x0
2767 /*
2768  * Enumerated value for register field ALT_SPIM_RISR_TXOIR
2769  *
2770  * spi_txo_intr interrupt is active prior masking
2771  */
2772 #define ALT_SPIM_RISR_TXOIR_E_ACT 0x1
2773 
2774 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_TXOIR register field. */
2775 #define ALT_SPIM_RISR_TXOIR_LSB 1
2776 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_TXOIR register field. */
2777 #define ALT_SPIM_RISR_TXOIR_MSB 1
2778 /* The width in bits of the ALT_SPIM_RISR_TXOIR register field. */
2779 #define ALT_SPIM_RISR_TXOIR_WIDTH 1
2780 /* The mask used to set the ALT_SPIM_RISR_TXOIR register field value. */
2781 #define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
2782 /* The mask used to clear the ALT_SPIM_RISR_TXOIR register field value. */
2783 #define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
2784 /* The reset value of the ALT_SPIM_RISR_TXOIR register field. */
2785 #define ALT_SPIM_RISR_TXOIR_RESET 0x0
2786 /* Extracts the ALT_SPIM_RISR_TXOIR field value from a register. */
2787 #define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2788 /* Produces a ALT_SPIM_RISR_TXOIR register field value suitable for setting the register. */
2789 #define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2790 
2791 /*
2792  * Field : rxuir
2793  *
2794  * Receive FIFO Underflow Raw Interrupt Status
2795  *
2796  * 0 = ssi_rxu_intr interrupt is not active prior to masking
2797  *
2798  * 1 = ssi_rxu_intr interrupt is active prior to masking
2799  *
2800  * Field Enumeration Values:
2801  *
2802  * Enum | Value | Description
2803  * :----------------------------|:------|:----------------------------------------------
2804  * ALT_SPIM_RISR_RXUIR_E_INACT | 0x0 | spi_rxu_intr interrupt is not active prior to
2805  * : | | masking
2806  * ALT_SPIM_RISR_RXUIR_E_ACT | 0x1 | spi_rxu_intr interrupt is active prior to
2807  * : | | masking
2808  *
2809  * Field Access Macros:
2810  *
2811  */
2812 /*
2813  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
2814  *
2815  * spi_rxu_intr interrupt is not active prior to masking
2816  */
2817 #define ALT_SPIM_RISR_RXUIR_E_INACT 0x0
2818 /*
2819  * Enumerated value for register field ALT_SPIM_RISR_RXUIR
2820  *
2821  * spi_rxu_intr interrupt is active prior to masking
2822  */
2823 #define ALT_SPIM_RISR_RXUIR_E_ACT 0x1
2824 
2825 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXUIR register field. */
2826 #define ALT_SPIM_RISR_RXUIR_LSB 2
2827 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXUIR register field. */
2828 #define ALT_SPIM_RISR_RXUIR_MSB 2
2829 /* The width in bits of the ALT_SPIM_RISR_RXUIR register field. */
2830 #define ALT_SPIM_RISR_RXUIR_WIDTH 1
2831 /* The mask used to set the ALT_SPIM_RISR_RXUIR register field value. */
2832 #define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
2833 /* The mask used to clear the ALT_SPIM_RISR_RXUIR register field value. */
2834 #define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
2835 /* The reset value of the ALT_SPIM_RISR_RXUIR register field. */
2836 #define ALT_SPIM_RISR_RXUIR_RESET 0x0
2837 /* Extracts the ALT_SPIM_RISR_RXUIR field value from a register. */
2838 #define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2839 /* Produces a ALT_SPIM_RISR_RXUIR register field value suitable for setting the register. */
2840 #define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2841 
2842 /*
2843  * Field : rxoir
2844  *
2845  * Receive FIFO Overflow Raw Interrupt Status
2846  *
2847  * 0 = ssi_rxo_intr interrupt is not active prior to masking
2848  *
2849  * 1 = ssi_rxo_intr interrupt is active prior masking
2850  *
2851  * Field Enumeration Values:
2852  *
2853  * Enum | Value | Description
2854  * :-------------------------------|:------|:-----------------------------------------------
2855  * ALT_SPIM_RISR_RXOIR_E_INACTOVE | 0x0 | spi_rxo_intr interrupt is not active prior to
2856  * : | | masking
2857  * ALT_SPIM_RISR_RXOIR_E_ACT | 0x1 | spi_rxo_intr interrupt is active prior masking
2858  *
2859  * Field Access Macros:
2860  *
2861  */
2862 /*
2863  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
2864  *
2865  * spi_rxo_intr interrupt is not active prior to masking
2866  */
2867 #define ALT_SPIM_RISR_RXOIR_E_INACTOVE 0x0
2868 /*
2869  * Enumerated value for register field ALT_SPIM_RISR_RXOIR
2870  *
2871  * spi_rxo_intr interrupt is active prior masking
2872  */
2873 #define ALT_SPIM_RISR_RXOIR_E_ACT 0x1
2874 
2875 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXOIR register field. */
2876 #define ALT_SPIM_RISR_RXOIR_LSB 3
2877 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXOIR register field. */
2878 #define ALT_SPIM_RISR_RXOIR_MSB 3
2879 /* The width in bits of the ALT_SPIM_RISR_RXOIR register field. */
2880 #define ALT_SPIM_RISR_RXOIR_WIDTH 1
2881 /* The mask used to set the ALT_SPIM_RISR_RXOIR register field value. */
2882 #define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
2883 /* The mask used to clear the ALT_SPIM_RISR_RXOIR register field value. */
2884 #define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
2885 /* The reset value of the ALT_SPIM_RISR_RXOIR register field. */
2886 #define ALT_SPIM_RISR_RXOIR_RESET 0x0
2887 /* Extracts the ALT_SPIM_RISR_RXOIR field value from a register. */
2888 #define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2889 /* Produces a ALT_SPIM_RISR_RXOIR register field value suitable for setting the register. */
2890 #define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2891 
2892 /*
2893  * Field : rxfir
2894  *
2895  * Receive FIFO Full Raw Interrupt Status
2896  *
2897  * 0 = ssi_rxf_intr interrupt is not active prior to masking
2898  *
2899  * 1 = ssi_rxf_intr interrupt is active prior to masking
2900  *
2901  * Field Enumeration Values:
2902  *
2903  * Enum | Value | Description
2904  * :----------------------------|:------|:----------------------------------------------
2905  * ALT_SPIM_RISR_RXFIR_E_INACT | 0x0 | spi_rxf_intr interrupt is not active prior to
2906  * : | | masking
2907  * ALT_SPIM_RISR_RXFIR_E_ACT | 0x1 | spi_rxf_intr interrupt is active prior to
2908  * : | | masking
2909  *
2910  * Field Access Macros:
2911  *
2912  */
2913 /*
2914  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
2915  *
2916  * spi_rxf_intr interrupt is not active prior to masking
2917  */
2918 #define ALT_SPIM_RISR_RXFIR_E_INACT 0x0
2919 /*
2920  * Enumerated value for register field ALT_SPIM_RISR_RXFIR
2921  *
2922  * spi_rxf_intr interrupt is active prior to masking
2923  */
2924 #define ALT_SPIM_RISR_RXFIR_E_ACT 0x1
2925 
2926 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_RXFIR register field. */
2927 #define ALT_SPIM_RISR_RXFIR_LSB 4
2928 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_RXFIR register field. */
2929 #define ALT_SPIM_RISR_RXFIR_MSB 4
2930 /* The width in bits of the ALT_SPIM_RISR_RXFIR register field. */
2931 #define ALT_SPIM_RISR_RXFIR_WIDTH 1
2932 /* The mask used to set the ALT_SPIM_RISR_RXFIR register field value. */
2933 #define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
2934 /* The mask used to clear the ALT_SPIM_RISR_RXFIR register field value. */
2935 #define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
2936 /* The reset value of the ALT_SPIM_RISR_RXFIR register field. */
2937 #define ALT_SPIM_RISR_RXFIR_RESET 0x0
2938 /* Extracts the ALT_SPIM_RISR_RXFIR field value from a register. */
2939 #define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2940 /* Produces a ALT_SPIM_RISR_RXFIR register field value suitable for setting the register. */
2941 #define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2942 
2943 /*
2944  * Field : mstir
2945  *
2946  * Multi-Master Contention Raw Interrupt Status.
2947  *
2948  * This bit field is not present if the DW_apb_ssi is configured as a
2949  *
2950  * serial-slave device.
2951  *
2952  * 0 = ssi_mst_intr interrupt is not active prior to masking
2953  *
2954  * 1 = ssi_mst_intr interrupt is active prior masking
2955  *
2956  * Field Access Macros:
2957  *
2958  */
2959 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RISR_MSTIR register field. */
2960 #define ALT_SPIM_RISR_MSTIR_LSB 5
2961 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RISR_MSTIR register field. */
2962 #define ALT_SPIM_RISR_MSTIR_MSB 5
2963 /* The width in bits of the ALT_SPIM_RISR_MSTIR register field. */
2964 #define ALT_SPIM_RISR_MSTIR_WIDTH 1
2965 /* The mask used to set the ALT_SPIM_RISR_MSTIR register field value. */
2966 #define ALT_SPIM_RISR_MSTIR_SET_MSK 0x00000020
2967 /* The mask used to clear the ALT_SPIM_RISR_MSTIR register field value. */
2968 #define ALT_SPIM_RISR_MSTIR_CLR_MSK 0xffffffdf
2969 /* The reset value of the ALT_SPIM_RISR_MSTIR register field. */
2970 #define ALT_SPIM_RISR_MSTIR_RESET 0x0
2971 /* Extracts the ALT_SPIM_RISR_MSTIR field value from a register. */
2972 #define ALT_SPIM_RISR_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
2973 /* Produces a ALT_SPIM_RISR_MSTIR register field value suitable for setting the register. */
2974 #define ALT_SPIM_RISR_MSTIR_SET(value) (((value) << 5) & 0x00000020)
2975 
2976 #ifndef __ASSEMBLY__
2977 /*
2978  * WARNING: The C register and register group struct declarations are provided for
2979  * convenience and illustrative purposes. They should, however, be used with
2980  * caution as the C language standard provides no guarantees about the alignment or
2981  * atomicity of device memory accesses. The recommended practice for writing
2982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2983  * alt_write_word() functions.
2984  *
2985  * The struct declaration for register ALT_SPIM_RISR.
2986  */
2987 struct ALT_SPIM_RISR_s
2988 {
2989  const uint32_t txeir : 1; /* ALT_SPIM_RISR_TXEIR */
2990  const uint32_t txoir : 1; /* ALT_SPIM_RISR_TXOIR */
2991  const uint32_t rxuir : 1; /* ALT_SPIM_RISR_RXUIR */
2992  const uint32_t rxoir : 1; /* ALT_SPIM_RISR_RXOIR */
2993  const uint32_t rxfir : 1; /* ALT_SPIM_RISR_RXFIR */
2994  const uint32_t mstir : 1; /* ALT_SPIM_RISR_MSTIR */
2995  uint32_t : 26; /* *UNDEFINED* */
2996 };
2997 
2998 /* The typedef declaration for register ALT_SPIM_RISR. */
2999 typedef volatile struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t;
3000 #endif /* __ASSEMBLY__ */
3001 
3002 /* The reset value of the ALT_SPIM_RISR register. */
3003 #define ALT_SPIM_RISR_RESET 0x00000000
3004 /* The byte offset of the ALT_SPIM_RISR register from the beginning of the component. */
3005 #define ALT_SPIM_RISR_OFST 0x34
3006 /* The address of the ALT_SPIM_RISR register. */
3007 #define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
3008 
3009 /*
3010  * Register : txoicr
3011  *
3012  * Transmit FIFO Overflow Interrupt Clear Register
3013  *
3014  * Register Layout
3015  *
3016  * Bits | Access | Reset | Description
3017  * :-------|:-------|:------|:-----------------------
3018  * [0] | R | 0x0 | ALT_SPIM_TXOICR_TXOICR
3019  * [31:1] | ??? | 0x0 | *UNDEFINED*
3020  *
3021  */
3022 /*
3023  * Field : txoicr
3024  *
3025  * Clear Transmit FIFO Overflow Interrupt.
3026  *
3027  * This register reflects the status of the interrupt. A read from this
3028  *
3029  * register clears the ssi_txo_intr interrupt; writing has no effect.
3030  *
3031  * Field Access Macros:
3032  *
3033  */
3034 /* The Least Significant Bit (LSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
3035 #define ALT_SPIM_TXOICR_TXOICR_LSB 0
3036 /* The Most Significant Bit (MSB) position of the ALT_SPIM_TXOICR_TXOICR register field. */
3037 #define ALT_SPIM_TXOICR_TXOICR_MSB 0
3038 /* The width in bits of the ALT_SPIM_TXOICR_TXOICR register field. */
3039 #define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
3040 /* The mask used to set the ALT_SPIM_TXOICR_TXOICR register field value. */
3041 #define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
3042 /* The mask used to clear the ALT_SPIM_TXOICR_TXOICR register field value. */
3043 #define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3044 /* The reset value of the ALT_SPIM_TXOICR_TXOICR register field. */
3045 #define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
3046 /* Extracts the ALT_SPIM_TXOICR_TXOICR field value from a register. */
3047 #define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3048 /* Produces a ALT_SPIM_TXOICR_TXOICR register field value suitable for setting the register. */
3049 #define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3050 
3051 #ifndef __ASSEMBLY__
3052 /*
3053  * WARNING: The C register and register group struct declarations are provided for
3054  * convenience and illustrative purposes. They should, however, be used with
3055  * caution as the C language standard provides no guarantees about the alignment or
3056  * atomicity of device memory accesses. The recommended practice for writing
3057  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3058  * alt_write_word() functions.
3059  *
3060  * The struct declaration for register ALT_SPIM_TXOICR.
3061  */
3062 struct ALT_SPIM_TXOICR_s
3063 {
3064  const uint32_t txoicr : 1; /* ALT_SPIM_TXOICR_TXOICR */
3065  uint32_t : 31; /* *UNDEFINED* */
3066 };
3067 
3068 /* The typedef declaration for register ALT_SPIM_TXOICR. */
3069 typedef volatile struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t;
3070 #endif /* __ASSEMBLY__ */
3071 
3072 /* The reset value of the ALT_SPIM_TXOICR register. */
3073 #define ALT_SPIM_TXOICR_RESET 0x00000000
3074 /* The byte offset of the ALT_SPIM_TXOICR register from the beginning of the component. */
3075 #define ALT_SPIM_TXOICR_OFST 0x38
3076 /* The address of the ALT_SPIM_TXOICR register. */
3077 #define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
3078 
3079 /*
3080  * Register : rxoicr
3081  *
3082  * Receive FIFO Overflow Interrupt Clear Register
3083  *
3084  * Register Layout
3085  *
3086  * Bits | Access | Reset | Description
3087  * :-------|:-------|:------|:-----------------------
3088  * [0] | R | 0x0 | ALT_SPIM_RXOICR_RXOICR
3089  * [31:1] | ??? | 0x0 | *UNDEFINED*
3090  *
3091  */
3092 /*
3093  * Field : rxoicr
3094  *
3095  * Clear Receive FIFO Overflow Interrupt.
3096  *
3097  * This register reflects the status of the interrupt. A read from this
3098  *
3099  * register clears the ssi_rxo_intr interrupt; writing has no effect.
3100  *
3101  * Field Access Macros:
3102  *
3103  */
3104 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
3105 #define ALT_SPIM_RXOICR_RXOICR_LSB 0
3106 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXOICR_RXOICR register field. */
3107 #define ALT_SPIM_RXOICR_RXOICR_MSB 0
3108 /* The width in bits of the ALT_SPIM_RXOICR_RXOICR register field. */
3109 #define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
3110 /* The mask used to set the ALT_SPIM_RXOICR_RXOICR register field value. */
3111 #define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
3112 /* The mask used to clear the ALT_SPIM_RXOICR_RXOICR register field value. */
3113 #define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3114 /* The reset value of the ALT_SPIM_RXOICR_RXOICR register field. */
3115 #define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
3116 /* Extracts the ALT_SPIM_RXOICR_RXOICR field value from a register. */
3117 #define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3118 /* Produces a ALT_SPIM_RXOICR_RXOICR register field value suitable for setting the register. */
3119 #define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3120 
3121 #ifndef __ASSEMBLY__
3122 /*
3123  * WARNING: The C register and register group struct declarations are provided for
3124  * convenience and illustrative purposes. They should, however, be used with
3125  * caution as the C language standard provides no guarantees about the alignment or
3126  * atomicity of device memory accesses. The recommended practice for writing
3127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3128  * alt_write_word() functions.
3129  *
3130  * The struct declaration for register ALT_SPIM_RXOICR.
3131  */
3132 struct ALT_SPIM_RXOICR_s
3133 {
3134  const uint32_t rxoicr : 1; /* ALT_SPIM_RXOICR_RXOICR */
3135  uint32_t : 31; /* *UNDEFINED* */
3136 };
3137 
3138 /* The typedef declaration for register ALT_SPIM_RXOICR. */
3139 typedef volatile struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t;
3140 #endif /* __ASSEMBLY__ */
3141 
3142 /* The reset value of the ALT_SPIM_RXOICR register. */
3143 #define ALT_SPIM_RXOICR_RESET 0x00000000
3144 /* The byte offset of the ALT_SPIM_RXOICR register from the beginning of the component. */
3145 #define ALT_SPIM_RXOICR_OFST 0x3c
3146 /* The address of the ALT_SPIM_RXOICR register. */
3147 #define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
3148 
3149 /*
3150  * Register : rxuicr
3151  *
3152  * Receive FIFO Underflow Interrupt Clear Register
3153  *
3154  * Register Layout
3155  *
3156  * Bits | Access | Reset | Description
3157  * :-------|:-------|:------|:-----------------------
3158  * [0] | R | 0x0 | ALT_SPIM_RXUICR_RXUICR
3159  * [31:1] | ??? | 0x0 | *UNDEFINED*
3160  *
3161  */
3162 /*
3163  * Field : rxuicr
3164  *
3165  * Clear Receive FIFO Underflow Interrupt.
3166  *
3167  * This register reflects the status of the interrupt. A read from this
3168  *
3169  * register clears the ssi_rxu_intr interrupt; writing has no effect.
3170  *
3171  * Field Access Macros:
3172  *
3173  */
3174 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
3175 #define ALT_SPIM_RXUICR_RXUICR_LSB 0
3176 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RXUICR_RXUICR register field. */
3177 #define ALT_SPIM_RXUICR_RXUICR_MSB 0
3178 /* The width in bits of the ALT_SPIM_RXUICR_RXUICR register field. */
3179 #define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
3180 /* The mask used to set the ALT_SPIM_RXUICR_RXUICR register field value. */
3181 #define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
3182 /* The mask used to clear the ALT_SPIM_RXUICR_RXUICR register field value. */
3183 #define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
3184 /* The reset value of the ALT_SPIM_RXUICR_RXUICR register field. */
3185 #define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
3186 /* Extracts the ALT_SPIM_RXUICR_RXUICR field value from a register. */
3187 #define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
3188 /* Produces a ALT_SPIM_RXUICR_RXUICR register field value suitable for setting the register. */
3189 #define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
3190 
3191 #ifndef __ASSEMBLY__
3192 /*
3193  * WARNING: The C register and register group struct declarations are provided for
3194  * convenience and illustrative purposes. They should, however, be used with
3195  * caution as the C language standard provides no guarantees about the alignment or
3196  * atomicity of device memory accesses. The recommended practice for writing
3197  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3198  * alt_write_word() functions.
3199  *
3200  * The struct declaration for register ALT_SPIM_RXUICR.
3201  */
3202 struct ALT_SPIM_RXUICR_s
3203 {
3204  const uint32_t rxuicr : 1; /* ALT_SPIM_RXUICR_RXUICR */
3205  uint32_t : 31; /* *UNDEFINED* */
3206 };
3207 
3208 /* The typedef declaration for register ALT_SPIM_RXUICR. */
3209 typedef volatile struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t;
3210 #endif /* __ASSEMBLY__ */
3211 
3212 /* The reset value of the ALT_SPIM_RXUICR register. */
3213 #define ALT_SPIM_RXUICR_RESET 0x00000000
3214 /* The byte offset of the ALT_SPIM_RXUICR register from the beginning of the component. */
3215 #define ALT_SPIM_RXUICR_OFST 0x40
3216 /* The address of the ALT_SPIM_RXUICR register. */
3217 #define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
3218 
3219 /*
3220  * Register : msticr
3221  *
3222  * Multi-Master Interrupt Clear Register
3223  *
3224  * Register Layout
3225  *
3226  * Bits | Access | Reset | Description
3227  * :-------|:-------|:------|:-----------------------
3228  * [0] | R | 0x0 | ALT_SPIM_MSTICR_MSTICR
3229  * [31:1] | ??? | 0x0 | *UNDEFINED*
3230  *
3231  */
3232 /*
3233  * Field : msticr
3234  *
3235  * Clear Multi-Master Contention Interrupt.
3236  *
3237  * This register reflects the status of the interrupt. A read from this
3238  *
3239  * register clears the ssi_mst_intr interrupt; writing has no effect.
3240  *
3241  * Field Access Macros:
3242  *
3243  */
3244 /* The Least Significant Bit (LSB) position of the ALT_SPIM_MSTICR_MSTICR register field. */
3245 #define ALT_SPIM_MSTICR_MSTICR_LSB 0
3246 /* The Most Significant Bit (MSB) position of the ALT_SPIM_MSTICR_MSTICR register field. */
3247 #define ALT_SPIM_MSTICR_MSTICR_MSB 0
3248 /* The width in bits of the ALT_SPIM_MSTICR_MSTICR register field. */
3249 #define ALT_SPIM_MSTICR_MSTICR_WIDTH 1
3250 /* The mask used to set the ALT_SPIM_MSTICR_MSTICR register field value. */
3251 #define ALT_SPIM_MSTICR_MSTICR_SET_MSK 0x00000001
3252 /* The mask used to clear the ALT_SPIM_MSTICR_MSTICR register field value. */
3253 #define ALT_SPIM_MSTICR_MSTICR_CLR_MSK 0xfffffffe
3254 /* The reset value of the ALT_SPIM_MSTICR_MSTICR register field. */
3255 #define ALT_SPIM_MSTICR_MSTICR_RESET 0x0
3256 /* Extracts the ALT_SPIM_MSTICR_MSTICR field value from a register. */
3257 #define ALT_SPIM_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
3258 /* Produces a ALT_SPIM_MSTICR_MSTICR register field value suitable for setting the register. */
3259 #define ALT_SPIM_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
3260 
3261 #ifndef __ASSEMBLY__
3262 /*
3263  * WARNING: The C register and register group struct declarations are provided for
3264  * convenience and illustrative purposes. They should, however, be used with
3265  * caution as the C language standard provides no guarantees about the alignment or
3266  * atomicity of device memory accesses. The recommended practice for writing
3267  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3268  * alt_write_word() functions.
3269  *
3270  * The struct declaration for register ALT_SPIM_MSTICR.
3271  */
3272 struct ALT_SPIM_MSTICR_s
3273 {
3274  const uint32_t msticr : 1; /* ALT_SPIM_MSTICR_MSTICR */
3275  uint32_t : 31; /* *UNDEFINED* */
3276 };
3277 
3278 /* The typedef declaration for register ALT_SPIM_MSTICR. */
3279 typedef volatile struct ALT_SPIM_MSTICR_s ALT_SPIM_MSTICR_t;
3280 #endif /* __ASSEMBLY__ */
3281 
3282 /* The reset value of the ALT_SPIM_MSTICR register. */
3283 #define ALT_SPIM_MSTICR_RESET 0x00000000
3284 /* The byte offset of the ALT_SPIM_MSTICR register from the beginning of the component. */
3285 #define ALT_SPIM_MSTICR_OFST 0x44
3286 /* The address of the ALT_SPIM_MSTICR register. */
3287 #define ALT_SPIM_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MSTICR_OFST))
3288 
3289 /*
3290  * Register : icr
3291  *
3292  * Interrupt Clear Register
3293  *
3294  * Register Layout
3295  *
3296  * Bits | Access | Reset | Description
3297  * :-------|:-------|:------|:-----------------
3298  * [0] | R | 0x0 | ALT_SPIM_ICR_ICR
3299  * [31:1] | ??? | 0x0 | *UNDEFINED*
3300  *
3301  */
3302 /*
3303  * Field : icr
3304  *
3305  * Clear Interrupts.
3306  *
3307  * This register is set if any of the interrupts below are active. A read
3308  *
3309  * clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr
3310  *
3311  * interrupts. Writing to this register has no effect.
3312  *
3313  * Field Access Macros:
3314  *
3315  */
3316 /* The Least Significant Bit (LSB) position of the ALT_SPIM_ICR_ICR register field. */
3317 #define ALT_SPIM_ICR_ICR_LSB 0
3318 /* The Most Significant Bit (MSB) position of the ALT_SPIM_ICR_ICR register field. */
3319 #define ALT_SPIM_ICR_ICR_MSB 0
3320 /* The width in bits of the ALT_SPIM_ICR_ICR register field. */
3321 #define ALT_SPIM_ICR_ICR_WIDTH 1
3322 /* The mask used to set the ALT_SPIM_ICR_ICR register field value. */
3323 #define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
3324 /* The mask used to clear the ALT_SPIM_ICR_ICR register field value. */
3325 #define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
3326 /* The reset value of the ALT_SPIM_ICR_ICR register field. */
3327 #define ALT_SPIM_ICR_ICR_RESET 0x0
3328 /* Extracts the ALT_SPIM_ICR_ICR field value from a register. */
3329 #define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
3330 /* Produces a ALT_SPIM_ICR_ICR register field value suitable for setting the register. */
3331 #define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
3332 
3333 #ifndef __ASSEMBLY__
3334 /*
3335  * WARNING: The C register and register group struct declarations are provided for
3336  * convenience and illustrative purposes. They should, however, be used with
3337  * caution as the C language standard provides no guarantees about the alignment or
3338  * atomicity of device memory accesses. The recommended practice for writing
3339  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3340  * alt_write_word() functions.
3341  *
3342  * The struct declaration for register ALT_SPIM_ICR.
3343  */
3344 struct ALT_SPIM_ICR_s
3345 {
3346  const uint32_t icr : 1; /* ALT_SPIM_ICR_ICR */
3347  uint32_t : 31; /* *UNDEFINED* */
3348 };
3349 
3350 /* The typedef declaration for register ALT_SPIM_ICR. */
3351 typedef volatile struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t;
3352 #endif /* __ASSEMBLY__ */
3353 
3354 /* The reset value of the ALT_SPIM_ICR register. */
3355 #define ALT_SPIM_ICR_RESET 0x00000000
3356 /* The byte offset of the ALT_SPIM_ICR register from the beginning of the component. */
3357 #define ALT_SPIM_ICR_OFST 0x48
3358 /* The address of the ALT_SPIM_ICR register. */
3359 #define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
3360 
3361 /*
3362  * Register : dmacr
3363  *
3364  * DMA Control Register.
3365  *
3366  * This register is only valid when DW_apb_ssi is configured with a set of
3367  *
3368  * DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
3369  *
3370  * not configured for DMA operation, this register will not exist and writing
3371  *
3372  * to the register's address will have no effect; reading from this register
3373  *
3374  * address will return zero. The register is used to enable the DMA
3375  *
3376  * Controller interface operation.
3377  *
3378  * Register Layout
3379  *
3380  * Bits | Access | Reset | Description
3381  * :-------|:-------|:------|:---------------------
3382  * [0] | RW | 0x0 | ALT_SPIM_DMACR_RDMAE
3383  * [1] | RW | 0x0 | ALT_SPIM_DMACR_TDMAE
3384  * [31:2] | ??? | 0x0 | *UNDEFINED*
3385  *
3386  */
3387 /*
3388  * Field : rdmae
3389  *
3390  * Receive DMA Enable.
3391  *
3392  * This bit enables/disables the receive FIFO DMA channel
3393  *
3394  * 0 = Receive DMA disabled
3395  *
3396  * 1 = Receive DMA enabled
3397  *
3398  * Field Enumeration Values:
3399  *
3400  * Enum | Value | Description
3401  * :----------------------------|:------|:---------------------
3402  * ALT_SPIM_DMACR_RDMAE_E_DISD | 0x0 | Receive DMA disabled
3403  * ALT_SPIM_DMACR_RDMAE_E_END | 0x1 | Receive DMA enabled
3404  *
3405  * Field Access Macros:
3406  *
3407  */
3408 /*
3409  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
3410  *
3411  * Receive DMA disabled
3412  */
3413 #define ALT_SPIM_DMACR_RDMAE_E_DISD 0x0
3414 /*
3415  * Enumerated value for register field ALT_SPIM_DMACR_RDMAE
3416  *
3417  * Receive DMA enabled
3418  */
3419 #define ALT_SPIM_DMACR_RDMAE_E_END 0x1
3420 
3421 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
3422 #define ALT_SPIM_DMACR_RDMAE_LSB 0
3423 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_RDMAE register field. */
3424 #define ALT_SPIM_DMACR_RDMAE_MSB 0
3425 /* The width in bits of the ALT_SPIM_DMACR_RDMAE register field. */
3426 #define ALT_SPIM_DMACR_RDMAE_WIDTH 1
3427 /* The mask used to set the ALT_SPIM_DMACR_RDMAE register field value. */
3428 #define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
3429 /* The mask used to clear the ALT_SPIM_DMACR_RDMAE register field value. */
3430 #define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
3431 /* The reset value of the ALT_SPIM_DMACR_RDMAE register field. */
3432 #define ALT_SPIM_DMACR_RDMAE_RESET 0x0
3433 /* Extracts the ALT_SPIM_DMACR_RDMAE field value from a register. */
3434 #define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3435 /* Produces a ALT_SPIM_DMACR_RDMAE register field value suitable for setting the register. */
3436 #define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3437 
3438 /*
3439  * Field : tdmae
3440  *
3441  * Transmit DMA Enable.
3442  *
3443  * This bit enables/disables the transmit FIFO DMA channel.
3444  *
3445  * 0 = Transmit DMA disabled
3446  *
3447  * 1 = Transmit DMA enabled
3448  *
3449  * Field Enumeration Values:
3450  *
3451  * Enum | Value | Description
3452  * :----------------------------|:------|:----------------------
3453  * ALT_SPIM_DMACR_TDMAE_E_DISD | 0x0 | Transmit DMA disabled
3454  * ALT_SPIM_DMACR_TDMAE_E_END | 0x1 | Transmit DMA enabled
3455  *
3456  * Field Access Macros:
3457  *
3458  */
3459 /*
3460  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
3461  *
3462  * Transmit DMA disabled
3463  */
3464 #define ALT_SPIM_DMACR_TDMAE_E_DISD 0x0
3465 /*
3466  * Enumerated value for register field ALT_SPIM_DMACR_TDMAE
3467  *
3468  * Transmit DMA enabled
3469  */
3470 #define ALT_SPIM_DMACR_TDMAE_E_END 0x1
3471 
3472 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
3473 #define ALT_SPIM_DMACR_TDMAE_LSB 1
3474 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMACR_TDMAE register field. */
3475 #define ALT_SPIM_DMACR_TDMAE_MSB 1
3476 /* The width in bits of the ALT_SPIM_DMACR_TDMAE register field. */
3477 #define ALT_SPIM_DMACR_TDMAE_WIDTH 1
3478 /* The mask used to set the ALT_SPIM_DMACR_TDMAE register field value. */
3479 #define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
3480 /* The mask used to clear the ALT_SPIM_DMACR_TDMAE register field value. */
3481 #define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
3482 /* The reset value of the ALT_SPIM_DMACR_TDMAE register field. */
3483 #define ALT_SPIM_DMACR_TDMAE_RESET 0x0
3484 /* Extracts the ALT_SPIM_DMACR_TDMAE field value from a register. */
3485 #define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3486 /* Produces a ALT_SPIM_DMACR_TDMAE register field value suitable for setting the register. */
3487 #define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3488 
3489 #ifndef __ASSEMBLY__
3490 /*
3491  * WARNING: The C register and register group struct declarations are provided for
3492  * convenience and illustrative purposes. They should, however, be used with
3493  * caution as the C language standard provides no guarantees about the alignment or
3494  * atomicity of device memory accesses. The recommended practice for writing
3495  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3496  * alt_write_word() functions.
3497  *
3498  * The struct declaration for register ALT_SPIM_DMACR.
3499  */
3500 struct ALT_SPIM_DMACR_s
3501 {
3502  uint32_t rdmae : 1; /* ALT_SPIM_DMACR_RDMAE */
3503  uint32_t tdmae : 1; /* ALT_SPIM_DMACR_TDMAE */
3504  uint32_t : 30; /* *UNDEFINED* */
3505 };
3506 
3507 /* The typedef declaration for register ALT_SPIM_DMACR. */
3508 typedef volatile struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t;
3509 #endif /* __ASSEMBLY__ */
3510 
3511 /* The reset value of the ALT_SPIM_DMACR register. */
3512 #define ALT_SPIM_DMACR_RESET 0x00000000
3513 /* The byte offset of the ALT_SPIM_DMACR register from the beginning of the component. */
3514 #define ALT_SPIM_DMACR_OFST 0x4c
3515 /* The address of the ALT_SPIM_DMACR register. */
3516 #define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
3517 
3518 /*
3519  * Register : dmatdlr
3520  *
3521  * DMA Transmit Data Level.
3522  *
3523  * This register is only valid when the DW_apb_ssi is configured with a set
3524  *
3525  * of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
3526  *
3527  * configured for DMA operation, this register will not exist and writing
3528  *
3529  * to its address will have no effect; reading from its address will
3530  *
3531  * return zero.
3532  *
3533  * Register Layout
3534  *
3535  * Bits | Access | Reset | Description
3536  * :-------|:-------|:------|:------------------------
3537  * [7:0] | RW | 0x0 | ALT_SPIM_DMATDLR_DMATDL
3538  * [31:8] | ??? | 0x0 | *UNDEFINED*
3539  *
3540  */
3541 /*
3542  * Field : dmatdl
3543  *
3544  * Transmit Data Level.
3545  *
3546  * This bit field controls the level at which a DMA request is made by the
3547  *
3548  * transmit logic. It is equal to the watermark level; that is, the
3549  *
3550  * dma_tx_req signal is generated when the number of valid data entries
3551  *
3552  * in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
3553  *
3554  * Field Access Macros:
3555  *
3556  */
3557 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
3558 #define ALT_SPIM_DMATDLR_DMATDL_LSB 0
3559 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMATDLR_DMATDL register field. */
3560 #define ALT_SPIM_DMATDLR_DMATDL_MSB 7
3561 /* The width in bits of the ALT_SPIM_DMATDLR_DMATDL register field. */
3562 #define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
3563 /* The mask used to set the ALT_SPIM_DMATDLR_DMATDL register field value. */
3564 #define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
3565 /* The mask used to clear the ALT_SPIM_DMATDLR_DMATDL register field value. */
3566 #define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
3567 /* The reset value of the ALT_SPIM_DMATDLR_DMATDL register field. */
3568 #define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
3569 /* Extracts the ALT_SPIM_DMATDLR_DMATDL field value from a register. */
3570 #define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
3571 /* Produces a ALT_SPIM_DMATDLR_DMATDL register field value suitable for setting the register. */
3572 #define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
3573 
3574 #ifndef __ASSEMBLY__
3575 /*
3576  * WARNING: The C register and register group struct declarations are provided for
3577  * convenience and illustrative purposes. They should, however, be used with
3578  * caution as the C language standard provides no guarantees about the alignment or
3579  * atomicity of device memory accesses. The recommended practice for writing
3580  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3581  * alt_write_word() functions.
3582  *
3583  * The struct declaration for register ALT_SPIM_DMATDLR.
3584  */
3585 struct ALT_SPIM_DMATDLR_s
3586 {
3587  uint32_t dmatdl : 8; /* ALT_SPIM_DMATDLR_DMATDL */
3588  uint32_t : 24; /* *UNDEFINED* */
3589 };
3590 
3591 /* The typedef declaration for register ALT_SPIM_DMATDLR. */
3592 typedef volatile struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t;
3593 #endif /* __ASSEMBLY__ */
3594 
3595 /* The reset value of the ALT_SPIM_DMATDLR register. */
3596 #define ALT_SPIM_DMATDLR_RESET 0x00000000
3597 /* The byte offset of the ALT_SPIM_DMATDLR register from the beginning of the component. */
3598 #define ALT_SPIM_DMATDLR_OFST 0x50
3599 /* The address of the ALT_SPIM_DMATDLR register. */
3600 #define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
3601 
3602 /*
3603  * Register : dmardlr
3604  *
3605  * DMA Receive Data Level.
3606  *
3607  * This register is only valid when DW_apb_ssi is configured with a set of
3608  *
3609  * DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
3610  *
3611  * for DMA operation, this register will not exist and writing to its address
3612  *
3613  * will have no effect; reading from its address will return zero.
3614  *
3615  * Register Layout
3616  *
3617  * Bits | Access | Reset | Description
3618  * :-------|:-------|:------|:------------------------
3619  * [7:0] | RW | 0x0 | ALT_SPIM_DMARDLR_DMARDL
3620  * [31:8] | ??? | 0x0 | *UNDEFINED*
3621  *
3622  */
3623 /*
3624  * Field : dmardl
3625  *
3626  * Receive Data Level.
3627  *
3628  * This bit field controls the level at which a DMA request is made by the
3629  *
3630  * receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is
3631  *
3632  * generated when the number of valid data entries in the receive FIFO is
3633  *
3634  * equal to or above this field value + 1, and RDMAE=1.
3635  *
3636  * Field Access Macros:
3637  *
3638  */
3639 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
3640 #define ALT_SPIM_DMARDLR_DMARDL_LSB 0
3641 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DMARDLR_DMARDL register field. */
3642 #define ALT_SPIM_DMARDLR_DMARDL_MSB 7
3643 /* The width in bits of the ALT_SPIM_DMARDLR_DMARDL register field. */
3644 #define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
3645 /* The mask used to set the ALT_SPIM_DMARDLR_DMARDL register field value. */
3646 #define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
3647 /* The mask used to clear the ALT_SPIM_DMARDLR_DMARDL register field value. */
3648 #define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
3649 /* The reset value of the ALT_SPIM_DMARDLR_DMARDL register field. */
3650 #define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
3651 /* Extracts the ALT_SPIM_DMARDLR_DMARDL field value from a register. */
3652 #define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
3653 /* Produces a ALT_SPIM_DMARDLR_DMARDL register field value suitable for setting the register. */
3654 #define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
3655 
3656 #ifndef __ASSEMBLY__
3657 /*
3658  * WARNING: The C register and register group struct declarations are provided for
3659  * convenience and illustrative purposes. They should, however, be used with
3660  * caution as the C language standard provides no guarantees about the alignment or
3661  * atomicity of device memory accesses. The recommended practice for writing
3662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3663  * alt_write_word() functions.
3664  *
3665  * The struct declaration for register ALT_SPIM_DMARDLR.
3666  */
3667 struct ALT_SPIM_DMARDLR_s
3668 {
3669  uint32_t dmardl : 8; /* ALT_SPIM_DMARDLR_DMARDL */
3670  uint32_t : 24; /* *UNDEFINED* */
3671 };
3672 
3673 /* The typedef declaration for register ALT_SPIM_DMARDLR. */
3674 typedef volatile struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t;
3675 #endif /* __ASSEMBLY__ */
3676 
3677 /* The reset value of the ALT_SPIM_DMARDLR register. */
3678 #define ALT_SPIM_DMARDLR_RESET 0x00000000
3679 /* The byte offset of the ALT_SPIM_DMARDLR register from the beginning of the component. */
3680 #define ALT_SPIM_DMARDLR_OFST 0x54
3681 /* The address of the ALT_SPIM_DMARDLR register. */
3682 #define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
3683 
3684 /*
3685  * Register : idr
3686  *
3687  * Identification Register.
3688  *
3689  * This register contains the peripherals identification code, which is
3690  *
3691  * written into the register at configuration time using coreConsultant.
3692  *
3693  * Register Layout
3694  *
3695  * Bits | Access | Reset | Description
3696  * :-------|:-------|:----------|:------------------------
3697  * [31:0] | R | 0x5510000 | Identification Register
3698  *
3699  */
3700 /*
3701  * Field : Identification Register - idr
3702  *
3703  * This register contains the peripherals identification code
3704  *
3705  * Field Access Macros:
3706  *
3707  */
3708 /* The Least Significant Bit (LSB) position of the ALT_SPIM_IDR_IDR register field. */
3709 #define ALT_SPIM_IDR_IDR_LSB 0
3710 /* The Most Significant Bit (MSB) position of the ALT_SPIM_IDR_IDR register field. */
3711 #define ALT_SPIM_IDR_IDR_MSB 31
3712 /* The width in bits of the ALT_SPIM_IDR_IDR register field. */
3713 #define ALT_SPIM_IDR_IDR_WIDTH 32
3714 /* The mask used to set the ALT_SPIM_IDR_IDR register field value. */
3715 #define ALT_SPIM_IDR_IDR_SET_MSK 0xffffffff
3716 /* The mask used to clear the ALT_SPIM_IDR_IDR register field value. */
3717 #define ALT_SPIM_IDR_IDR_CLR_MSK 0x00000000
3718 /* The reset value of the ALT_SPIM_IDR_IDR register field. */
3719 #define ALT_SPIM_IDR_IDR_RESET 0x5510000
3720 /* Extracts the ALT_SPIM_IDR_IDR field value from a register. */
3721 #define ALT_SPIM_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
3722 /* Produces a ALT_SPIM_IDR_IDR register field value suitable for setting the register. */
3723 #define ALT_SPIM_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
3724 
3725 #ifndef __ASSEMBLY__
3726 /*
3727  * WARNING: The C register and register group struct declarations are provided for
3728  * convenience and illustrative purposes. They should, however, be used with
3729  * caution as the C language standard provides no guarantees about the alignment or
3730  * atomicity of device memory accesses. The recommended practice for writing
3731  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3732  * alt_write_word() functions.
3733  *
3734  * The struct declaration for register ALT_SPIM_IDR.
3735  */
3736 struct ALT_SPIM_IDR_s
3737 {
3738  const uint32_t idr : 32; /* Identification Register */
3739 };
3740 
3741 /* The typedef declaration for register ALT_SPIM_IDR. */
3742 typedef volatile struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t;
3743 #endif /* __ASSEMBLY__ */
3744 
3745 /* The reset value of the ALT_SPIM_IDR register. */
3746 #define ALT_SPIM_IDR_RESET 0x05510000
3747 /* The byte offset of the ALT_SPIM_IDR register from the beginning of the component. */
3748 #define ALT_SPIM_IDR_OFST 0x58
3749 /* The address of the ALT_SPIM_IDR register. */
3750 #define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
3751 
3752 /*
3753  * Register : spi_version_id
3754  *
3755  * coreKit Version ID Register
3756  *
3757  * Register Layout
3758  *
3759  * Bits | Access | Reset | Description
3760  * :-------|:-------|:-----------|:----------------
3761  * [31:0] | RW | 0x3332322a | Version ID Code
3762  *
3763  */
3764 /*
3765  * Field : Version ID Code - spi_version_id
3766  *
3767  * Contains the hex representation of the Synopsys component version. Consists of
3768  * ASCII value for each number in the version.
3769  *
3770  * Field Access Macros:
3771  *
3772  */
3773 /* The Least Significant Bit (LSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3774 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_LSB 0
3775 /* The Most Significant Bit (MSB) position of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3776 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_MSB 31
3777 /* The width in bits of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3778 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3779 /* The mask used to set the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */
3780 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3781 /* The mask used to clear the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value. */
3782 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3783 /* The reset value of the ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field. */
3784 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_RESET 0x3332322a
3785 /* Extracts the ALT_SPIM_SPI_VER_ID_SPI_VER_ID field value from a register. */
3786 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3787 /* Produces a ALT_SPIM_SPI_VER_ID_SPI_VER_ID register field value suitable for setting the register. */
3788 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3789 
3790 #ifndef __ASSEMBLY__
3791 /*
3792  * WARNING: The C register and register group struct declarations are provided for
3793  * convenience and illustrative purposes. They should, however, be used with
3794  * caution as the C language standard provides no guarantees about the alignment or
3795  * atomicity of device memory accesses. The recommended practice for writing
3796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3797  * alt_write_word() functions.
3798  *
3799  * The struct declaration for register ALT_SPIM_SPI_VER_ID.
3800  */
3801 struct ALT_SPIM_SPI_VER_ID_s
3802 {
3803  uint32_t spi_version_id : 32; /* Version ID Code */
3804 };
3805 
3806 /* The typedef declaration for register ALT_SPIM_SPI_VER_ID. */
3807 typedef volatile struct ALT_SPIM_SPI_VER_ID_s ALT_SPIM_SPI_VER_ID_t;
3808 #endif /* __ASSEMBLY__ */
3809 
3810 /* The reset value of the ALT_SPIM_SPI_VER_ID register. */
3811 #define ALT_SPIM_SPI_VER_ID_RESET 0x3332322a
3812 /* The byte offset of the ALT_SPIM_SPI_VER_ID register from the beginning of the component. */
3813 #define ALT_SPIM_SPI_VER_ID_OFST 0x5c
3814 /* The address of the ALT_SPIM_SPI_VER_ID register. */
3815 #define ALT_SPIM_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPI_VER_ID_OFST))
3816 
3817 /*
3818  * Register : dr
3819  *
3820  * The DW_apb_ssi data register is a 16-bit read/write buffer for the
3821  *
3822  * transmit/receive FIFOs. When the register is read, data in the receive
3823  *
3824  * FIFO buffer is accessed. When it is written to, data are moved into the
3825  *
3826  * transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are
3827  *
3828  * reset when SSI_EN = 0.
3829  *
3830  * Register Layout
3831  *
3832  * Bits | Access | Reset | Description
3833  * :--------|:-------|:------|:---------------
3834  * [15:0] | RW | 0x0 | ALT_SPIM_DR_DR
3835  * [31:16] | ??? | 0x0 | *UNDEFINED*
3836  *
3837  */
3838 /*
3839  * Field : dr
3840  *
3841  * Data Register.
3842  *
3843  * When writing to this register, you must right-justify the data. Read
3844  *
3845  * data are automatically right-justified.
3846  *
3847  * Read = Receive FIFO buffer
3848  *
3849  * Write = Transmit FIFO buffer
3850  *
3851  * Field Access Macros:
3852  *
3853  */
3854 /* The Least Significant Bit (LSB) position of the ALT_SPIM_DR_DR register field. */
3855 #define ALT_SPIM_DR_DR_LSB 0
3856 /* The Most Significant Bit (MSB) position of the ALT_SPIM_DR_DR register field. */
3857 #define ALT_SPIM_DR_DR_MSB 15
3858 /* The width in bits of the ALT_SPIM_DR_DR register field. */
3859 #define ALT_SPIM_DR_DR_WIDTH 16
3860 /* The mask used to set the ALT_SPIM_DR_DR register field value. */
3861 #define ALT_SPIM_DR_DR_SET_MSK 0x0000ffff
3862 /* The mask used to clear the ALT_SPIM_DR_DR register field value. */
3863 #define ALT_SPIM_DR_DR_CLR_MSK 0xffff0000
3864 /* The reset value of the ALT_SPIM_DR_DR register field. */
3865 #define ALT_SPIM_DR_DR_RESET 0x0
3866 /* Extracts the ALT_SPIM_DR_DR field value from a register. */
3867 #define ALT_SPIM_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3868 /* Produces a ALT_SPIM_DR_DR register field value suitable for setting the register. */
3869 #define ALT_SPIM_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3870 
3871 #ifndef __ASSEMBLY__
3872 /*
3873  * WARNING: The C register and register group struct declarations are provided for
3874  * convenience and illustrative purposes. They should, however, be used with
3875  * caution as the C language standard provides no guarantees about the alignment or
3876  * atomicity of device memory accesses. The recommended practice for writing
3877  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3878  * alt_write_word() functions.
3879  *
3880  * The struct declaration for register ALT_SPIM_DR.
3881  */
3882 struct ALT_SPIM_DR_s
3883 {
3884  uint32_t dr : 16; /* ALT_SPIM_DR_DR */
3885  uint32_t : 16; /* *UNDEFINED* */
3886 };
3887 
3888 /* The typedef declaration for register ALT_SPIM_DR. */
3889 typedef volatile struct ALT_SPIM_DR_s ALT_SPIM_DR_t;
3890 #endif /* __ASSEMBLY__ */
3891 
3892 /* The reset value of the ALT_SPIM_DR register. */
3893 #define ALT_SPIM_DR_RESET 0x00000000
3894 /* The byte offset of the ALT_SPIM_DR register from the beginning of the component. */
3895 #define ALT_SPIM_DR_OFST 0x60
3896 /* The address of the ALT_SPIM_DR register. */
3897 #define ALT_SPIM_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR_OFST))
3898 
3899 /*
3900  * Register : rx_sample_dly
3901  *
3902  * RX Sample Delay.
3903  *
3904  * This register is only valid when the DW_apb_ssi is configured with rxd
3905  *
3906  * sample delay logic (SSI_HAS_RX_SAMPLE_DELAY==1). When the DW_apb_ssi is
3907  *
3908  * not configured with rxd sample delay logic, this register will not exist
3909  *
3910  * and writing to its address location will have no effect; reading from
3911  *
3912  * its address will return zero. This register control the number of ssi_clk
3913  *
3914  * cycles that are delayed (from the default sample time) before the actual
3915  *
3916  * sample of the rxd input occurs. It is impossible to write to this
3917  *
3918  * register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and
3919  *
3920  * disabled by writing to the SSIENR register.
3921  *
3922  * Register Layout
3923  *
3924  * Bits | Access | Reset | Description
3925  * :-------|:-------|:------|:-------------------------
3926  * [7:0] | RW | 0x0 | ALT_SPIM_RX_SMPL_DLY_RSD
3927  * [31:8] | ??? | 0x0 | *UNDEFINED*
3928  *
3929  */
3930 /*
3931  * Field : rsd
3932  *
3933  * Rxd Sample Delay.
3934  *
3935  * This register is used to delay the sample of the rxd input port. Each value
3936  *
3937  * represents a single ssi_clk delay on the sample of rxd. Note; If this register
3938  *
3939  * is programmed with a value that exceeds the depth of the internal shift
3940  *
3941  * registers (SSI_RX_DLY_SR_DEPTH) zero delay will be applied to the rxd sample.
3942  *
3943  * Field Access Macros:
3944  *
3945  */
3946 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3947 #define ALT_SPIM_RX_SMPL_DLY_RSD_LSB 0
3948 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3949 #define ALT_SPIM_RX_SMPL_DLY_RSD_MSB 7
3950 /* The width in bits of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3951 #define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH 8
3952 /* The mask used to set the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */
3953 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK 0x000000ff
3954 /* The mask used to clear the ALT_SPIM_RX_SMPL_DLY_RSD register field value. */
3955 #define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK 0xffffff00
3956 /* The reset value of the ALT_SPIM_RX_SMPL_DLY_RSD register field. */
3957 #define ALT_SPIM_RX_SMPL_DLY_RSD_RESET 0x0
3958 /* Extracts the ALT_SPIM_RX_SMPL_DLY_RSD field value from a register. */
3959 #define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value) (((value) & 0x000000ff) >> 0)
3960 /* Produces a ALT_SPIM_RX_SMPL_DLY_RSD register field value suitable for setting the register. */
3961 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value) (((value) << 0) & 0x000000ff)
3962 
3963 #ifndef __ASSEMBLY__
3964 /*
3965  * WARNING: The C register and register group struct declarations are provided for
3966  * convenience and illustrative purposes. They should, however, be used with
3967  * caution as the C language standard provides no guarantees about the alignment or
3968  * atomicity of device memory accesses. The recommended practice for writing
3969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3970  * alt_write_word() functions.
3971  *
3972  * The struct declaration for register ALT_SPIM_RX_SMPL_DLY.
3973  */
3974 struct ALT_SPIM_RX_SMPL_DLY_s
3975 {
3976  uint32_t rsd : 8; /* ALT_SPIM_RX_SMPL_DLY_RSD */
3977  uint32_t : 24; /* *UNDEFINED* */
3978 };
3979 
3980 /* The typedef declaration for register ALT_SPIM_RX_SMPL_DLY. */
3981 typedef volatile struct ALT_SPIM_RX_SMPL_DLY_s ALT_SPIM_RX_SMPL_DLY_t;
3982 #endif /* __ASSEMBLY__ */
3983 
3984 /* The reset value of the ALT_SPIM_RX_SMPL_DLY register. */
3985 #define ALT_SPIM_RX_SMPL_DLY_RESET 0x00000000
3986 /* The byte offset of the ALT_SPIM_RX_SMPL_DLY register from the beginning of the component. */
3987 #define ALT_SPIM_RX_SMPL_DLY_OFST 0xf0
3988 /* The address of the ALT_SPIM_RX_SMPL_DLY register. */
3989 #define ALT_SPIM_RX_SMPL_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))
3990 
3991 /*
3992  * Register : rsvd_0
3993  *
3994  * RSVD_0 - Reserved address location
3995  *
3996  * Register Layout
3997  *
3998  * Bits | Access | Reset | Description
3999  * :-------|:-------|:------|:------------
4000  * [31:0] | RW | 0x0 | Empty
4001  *
4002  */
4003 /*
4004  * Field : Empty - fld
4005  *
4006  * Placeholder
4007  *
4008  * Field Access Macros:
4009  *
4010  */
4011 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RSVD_0_FLD register field. */
4012 #define ALT_SPIM_RSVD_0_FLD_LSB 0
4013 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RSVD_0_FLD register field. */
4014 #define ALT_SPIM_RSVD_0_FLD_MSB 31
4015 /* The width in bits of the ALT_SPIM_RSVD_0_FLD register field. */
4016 #define ALT_SPIM_RSVD_0_FLD_WIDTH 32
4017 /* The mask used to set the ALT_SPIM_RSVD_0_FLD register field value. */
4018 #define ALT_SPIM_RSVD_0_FLD_SET_MSK 0xffffffff
4019 /* The mask used to clear the ALT_SPIM_RSVD_0_FLD register field value. */
4020 #define ALT_SPIM_RSVD_0_FLD_CLR_MSK 0x00000000
4021 /* The reset value of the ALT_SPIM_RSVD_0_FLD register field. */
4022 #define ALT_SPIM_RSVD_0_FLD_RESET 0x0
4023 /* Extracts the ALT_SPIM_RSVD_0_FLD field value from a register. */
4024 #define ALT_SPIM_RSVD_0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4025 /* Produces a ALT_SPIM_RSVD_0_FLD register field value suitable for setting the register. */
4026 #define ALT_SPIM_RSVD_0_FLD_SET(value) (((value) << 0) & 0xffffffff)
4027 
4028 #ifndef __ASSEMBLY__
4029 /*
4030  * WARNING: The C register and register group struct declarations are provided for
4031  * convenience and illustrative purposes. They should, however, be used with
4032  * caution as the C language standard provides no guarantees about the alignment or
4033  * atomicity of device memory accesses. The recommended practice for writing
4034  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4035  * alt_write_word() functions.
4036  *
4037  * The struct declaration for register ALT_SPIM_RSVD_0.
4038  */
4039 struct ALT_SPIM_RSVD_0_s
4040 {
4041  uint32_t fld : 32; /* Empty */
4042 };
4043 
4044 /* The typedef declaration for register ALT_SPIM_RSVD_0. */
4045 typedef volatile struct ALT_SPIM_RSVD_0_s ALT_SPIM_RSVD_0_t;
4046 #endif /* __ASSEMBLY__ */
4047 
4048 /* The reset value of the ALT_SPIM_RSVD_0 register. */
4049 #define ALT_SPIM_RSVD_0_RESET 0x00000000
4050 /* The byte offset of the ALT_SPIM_RSVD_0 register from the beginning of the component. */
4051 #define ALT_SPIM_RSVD_0_OFST 0xf4
4052 /* The address of the ALT_SPIM_RSVD_0 register. */
4053 #define ALT_SPIM_RSVD_0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_0_OFST))
4054 
4055 /*
4056  * Register : rsvd_1
4057  *
4058  * RSVD_1 - Reserved address location
4059  *
4060  * Register Layout
4061  *
4062  * Bits | Access | Reset | Description
4063  * :-------|:-------|:------|:------------
4064  * [31:0] | RW | 0x0 | Empty
4065  *
4066  */
4067 /*
4068  * Field : Empty - fld
4069  *
4070  * Placeholder
4071  *
4072  * Field Access Macros:
4073  *
4074  */
4075 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RSVD_1_FLD register field. */
4076 #define ALT_SPIM_RSVD_1_FLD_LSB 0
4077 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RSVD_1_FLD register field. */
4078 #define ALT_SPIM_RSVD_1_FLD_MSB 31
4079 /* The width in bits of the ALT_SPIM_RSVD_1_FLD register field. */
4080 #define ALT_SPIM_RSVD_1_FLD_WIDTH 32
4081 /* The mask used to set the ALT_SPIM_RSVD_1_FLD register field value. */
4082 #define ALT_SPIM_RSVD_1_FLD_SET_MSK 0xffffffff
4083 /* The mask used to clear the ALT_SPIM_RSVD_1_FLD register field value. */
4084 #define ALT_SPIM_RSVD_1_FLD_CLR_MSK 0x00000000
4085 /* The reset value of the ALT_SPIM_RSVD_1_FLD register field. */
4086 #define ALT_SPIM_RSVD_1_FLD_RESET 0x0
4087 /* Extracts the ALT_SPIM_RSVD_1_FLD field value from a register. */
4088 #define ALT_SPIM_RSVD_1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4089 /* Produces a ALT_SPIM_RSVD_1_FLD register field value suitable for setting the register. */
4090 #define ALT_SPIM_RSVD_1_FLD_SET(value) (((value) << 0) & 0xffffffff)
4091 
4092 #ifndef __ASSEMBLY__
4093 /*
4094  * WARNING: The C register and register group struct declarations are provided for
4095  * convenience and illustrative purposes. They should, however, be used with
4096  * caution as the C language standard provides no guarantees about the alignment or
4097  * atomicity of device memory accesses. The recommended practice for writing
4098  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4099  * alt_write_word() functions.
4100  *
4101  * The struct declaration for register ALT_SPIM_RSVD_1.
4102  */
4103 struct ALT_SPIM_RSVD_1_s
4104 {
4105  uint32_t fld : 32; /* Empty */
4106 };
4107 
4108 /* The typedef declaration for register ALT_SPIM_RSVD_1. */
4109 typedef volatile struct ALT_SPIM_RSVD_1_s ALT_SPIM_RSVD_1_t;
4110 #endif /* __ASSEMBLY__ */
4111 
4112 /* The reset value of the ALT_SPIM_RSVD_1 register. */
4113 #define ALT_SPIM_RSVD_1_RESET 0x00000000
4114 /* The byte offset of the ALT_SPIM_RSVD_1 register from the beginning of the component. */
4115 #define ALT_SPIM_RSVD_1_OFST 0xf8
4116 /* The address of the ALT_SPIM_RSVD_1 register. */
4117 #define ALT_SPIM_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_1_OFST))
4118 
4119 /*
4120  * Register : rsvd_2
4121  *
4122  * RSVD_2 - Reserved address location
4123  *
4124  * Register Layout
4125  *
4126  * Bits | Access | Reset | Description
4127  * :-------|:-------|:------|:------------
4128  * [31:0] | RW | 0x0 | Empty
4129  *
4130  */
4131 /*
4132  * Field : Empty - fld
4133  *
4134  * Placeholder
4135  *
4136  * Field Access Macros:
4137  *
4138  */
4139 /* The Least Significant Bit (LSB) position of the ALT_SPIM_RSVD_2_FLD register field. */
4140 #define ALT_SPIM_RSVD_2_FLD_LSB 0
4141 /* The Most Significant Bit (MSB) position of the ALT_SPIM_RSVD_2_FLD register field. */
4142 #define ALT_SPIM_RSVD_2_FLD_MSB 31
4143 /* The width in bits of the ALT_SPIM_RSVD_2_FLD register field. */
4144 #define ALT_SPIM_RSVD_2_FLD_WIDTH 32
4145 /* The mask used to set the ALT_SPIM_RSVD_2_FLD register field value. */
4146 #define ALT_SPIM_RSVD_2_FLD_SET_MSK 0xffffffff
4147 /* The mask used to clear the ALT_SPIM_RSVD_2_FLD register field value. */
4148 #define ALT_SPIM_RSVD_2_FLD_CLR_MSK 0x00000000
4149 /* The reset value of the ALT_SPIM_RSVD_2_FLD register field. */
4150 #define ALT_SPIM_RSVD_2_FLD_RESET 0x0
4151 /* Extracts the ALT_SPIM_RSVD_2_FLD field value from a register. */
4152 #define ALT_SPIM_RSVD_2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4153 /* Produces a ALT_SPIM_RSVD_2_FLD register field value suitable for setting the register. */
4154 #define ALT_SPIM_RSVD_2_FLD_SET(value) (((value) << 0) & 0xffffffff)
4155 
4156 #ifndef __ASSEMBLY__
4157 /*
4158  * WARNING: The C register and register group struct declarations are provided for
4159  * convenience and illustrative purposes. They should, however, be used with
4160  * caution as the C language standard provides no guarantees about the alignment or
4161  * atomicity of device memory accesses. The recommended practice for writing
4162  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4163  * alt_write_word() functions.
4164  *
4165  * The struct declaration for register ALT_SPIM_RSVD_2.
4166  */
4167 struct ALT_SPIM_RSVD_2_s
4168 {
4169  uint32_t fld : 32; /* Empty */
4170 };
4171 
4172 /* The typedef declaration for register ALT_SPIM_RSVD_2. */
4173 typedef volatile struct ALT_SPIM_RSVD_2_s ALT_SPIM_RSVD_2_t;
4174 #endif /* __ASSEMBLY__ */
4175 
4176 /* The reset value of the ALT_SPIM_RSVD_2 register. */
4177 #define ALT_SPIM_RSVD_2_RESET 0x00000000
4178 /* The byte offset of the ALT_SPIM_RSVD_2 register from the beginning of the component. */
4179 #define ALT_SPIM_RSVD_2_OFST 0xfc
4180 /* The address of the ALT_SPIM_RSVD_2 register. */
4181 #define ALT_SPIM_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_2_OFST))
4182 
4183 #ifndef __ASSEMBLY__
4184 /*
4185  * WARNING: The C register and register group struct declarations are provided for
4186  * convenience and illustrative purposes. They should, however, be used with
4187  * caution as the C language standard provides no guarantees about the alignment or
4188  * atomicity of device memory accesses. The recommended practice for writing
4189  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4190  * alt_write_word() functions.
4191  *
4192  * The struct declaration for register group ALT_SPIM.
4193  */
4194 struct ALT_SPIM_s
4195 {
4196  ALT_SPIM_CTLR0_t ctrlr0; /* ALT_SPIM_CTLR0 */
4197  ALT_SPIM_CTLR1_t ctrlr1; /* ALT_SPIM_CTLR1 */
4198  ALT_SPIM_SPIENR_t spienr; /* ALT_SPIM_SPIENR */
4199  ALT_SPIM_MWCR_t mwcr; /* ALT_SPIM_MWCR */
4200  ALT_SPIM_SER_t ser; /* ALT_SPIM_SER */
4201  ALT_SPIM_BAUDR_t baudr; /* ALT_SPIM_BAUDR */
4202  ALT_SPIM_TXFTLR_t txftlr; /* ALT_SPIM_TXFTLR */
4203  ALT_SPIM_RXFTLR_t rxftlr; /* ALT_SPIM_RXFTLR */
4204  ALT_SPIM_TXFLR_t txflr; /* ALT_SPIM_TXFLR */
4205  ALT_SPIM_RXFLR_t rxflr; /* ALT_SPIM_RXFLR */
4206  ALT_SPIM_SR_t sr; /* ALT_SPIM_SR */
4207  ALT_SPIM_IMR_t imr; /* ALT_SPIM_IMR */
4208  ALT_SPIM_ISR_t isr; /* ALT_SPIM_ISR */
4209  ALT_SPIM_RISR_t risr; /* ALT_SPIM_RISR */
4210  ALT_SPIM_TXOICR_t txoicr; /* ALT_SPIM_TXOICR */
4211  ALT_SPIM_RXOICR_t rxoicr; /* ALT_SPIM_RXOICR */
4212  ALT_SPIM_RXUICR_t rxuicr; /* ALT_SPIM_RXUICR */
4213  ALT_SPIM_MSTICR_t msticr; /* ALT_SPIM_MSTICR */
4214  ALT_SPIM_ICR_t icr; /* ALT_SPIM_ICR */
4215  ALT_SPIM_DMACR_t dmacr; /* ALT_SPIM_DMACR */
4216  ALT_SPIM_DMATDLR_t dmatdlr; /* ALT_SPIM_DMATDLR */
4217  ALT_SPIM_DMARDLR_t dmardlr; /* ALT_SPIM_DMARDLR */
4218  ALT_SPIM_IDR_t idr; /* ALT_SPIM_IDR */
4219  ALT_SPIM_SPI_VER_ID_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */
4220  ALT_SPIM_DR_t dr; /* ALT_SPIM_DR */
4221  volatile uint32_t _pad_0x64_0xef[35]; /* *UNDEFINED* */
4222  ALT_SPIM_RX_SMPL_DLY_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */
4223  ALT_SPIM_RSVD_0_t rsvd_0; /* ALT_SPIM_RSVD_0 */
4224  ALT_SPIM_RSVD_1_t rsvd_1; /* ALT_SPIM_RSVD_1 */
4225  ALT_SPIM_RSVD_2_t rsvd_2; /* ALT_SPIM_RSVD_2 */
4226 };
4227 
4228 /* The typedef declaration for register group ALT_SPIM. */
4229 typedef volatile struct ALT_SPIM_s ALT_SPIM_t;
4230 /* The struct declaration for the raw register contents of register group ALT_SPIM. */
4231 struct ALT_SPIM_raw_s
4232 {
4233  volatile uint32_t ctrlr0; /* ALT_SPIM_CTLR0 */
4234  volatile uint32_t ctrlr1; /* ALT_SPIM_CTLR1 */
4235  volatile uint32_t spienr; /* ALT_SPIM_SPIENR */
4236  volatile uint32_t mwcr; /* ALT_SPIM_MWCR */
4237  volatile uint32_t ser; /* ALT_SPIM_SER */
4238  volatile uint32_t baudr; /* ALT_SPIM_BAUDR */
4239  volatile uint32_t txftlr; /* ALT_SPIM_TXFTLR */
4240  volatile uint32_t rxftlr; /* ALT_SPIM_RXFTLR */
4241  volatile uint32_t txflr; /* ALT_SPIM_TXFLR */
4242  volatile uint32_t rxflr; /* ALT_SPIM_RXFLR */
4243  volatile uint32_t sr; /* ALT_SPIM_SR */
4244  volatile uint32_t imr; /* ALT_SPIM_IMR */
4245  volatile uint32_t isr; /* ALT_SPIM_ISR */
4246  volatile uint32_t risr; /* ALT_SPIM_RISR */
4247  volatile uint32_t txoicr; /* ALT_SPIM_TXOICR */
4248  volatile uint32_t rxoicr; /* ALT_SPIM_RXOICR */
4249  volatile uint32_t rxuicr; /* ALT_SPIM_RXUICR */
4250  volatile uint32_t msticr; /* ALT_SPIM_MSTICR */
4251  volatile uint32_t icr; /* ALT_SPIM_ICR */
4252  volatile uint32_t dmacr; /* ALT_SPIM_DMACR */
4253  volatile uint32_t dmatdlr; /* ALT_SPIM_DMATDLR */
4254  volatile uint32_t dmardlr; /* ALT_SPIM_DMARDLR */
4255  volatile uint32_t idr; /* ALT_SPIM_IDR */
4256  volatile uint32_t spi_version_id; /* ALT_SPIM_SPI_VER_ID */
4257  volatile uint32_t dr; /* ALT_SPIM_DR */
4258  uint32_t _pad_0x64_0xef[35]; /* *UNDEFINED* */
4259  volatile uint32_t rx_sample_dly; /* ALT_SPIM_RX_SMPL_DLY */
4260  volatile uint32_t rsvd_0; /* ALT_SPIM_RSVD_0 */
4261  volatile uint32_t rsvd_1; /* ALT_SPIM_RSVD_1 */
4262  volatile uint32_t rsvd_2; /* ALT_SPIM_RSVD_2 */
4263 };
4264 
4265 /* The typedef declaration for the raw register contents of register group ALT_SPIM. */
4266 typedef volatile struct ALT_SPIM_raw_s ALT_SPIM_raw_t;
4267 #endif /* __ASSEMBLY__ */
4268 
4269 
4270 #ifdef __cplusplus
4271 }
4272 #endif /* __cplusplus */
4273 #endif /* __ALT_SOCAL_SPIM_H__ */
4274