35 #ifndef __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
81 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_LSB 0
83 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_MSB 0
85 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_WIDTH 1
87 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_SET_MSK 0x00000001
89 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_CLR_MSK 0xfffffffe
91 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_RESET 0x0
93 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
95 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
108 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_LSB 16
110 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_MSB 16
112 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_WIDTH 1
114 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_SET_MSK 0x00010000
116 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
118 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_RESET 0x0
120 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
122 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
135 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_LSB 24
137 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_MSB 24
139 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_WIDTH 1
141 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_SET_MSK 0x01000000
143 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_CLR_MSK 0xfeffffff
145 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_RESET 0x0
147 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
149 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
163 struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
165 volatile uint32_t mpu : 1;
167 volatile uint32_t fpga2soc : 1;
169 volatile uint32_t axi_ap : 1;
174 typedef struct ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t;
178 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_RESET 0x00000000
180 #define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_OFST 0x8
210 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_LSB 0
212 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_MSB 0
214 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_WIDTH 1
216 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_SET_MSK 0x00000001
218 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_CLR_MSK 0xfffffffe
220 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_RESET 0x0
222 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
224 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
237 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_LSB 16
239 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_MSB 16
241 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_WIDTH 1
243 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_SET_MSK 0x00010000
245 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
247 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_RESET 0x0
249 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
251 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
264 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_LSB 24
266 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_MSB 24
268 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_WIDTH 1
270 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_SET_MSK 0x01000000
272 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
274 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_RESET 0x0
276 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
278 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
292 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
294 volatile uint32_t mpu : 1;
296 volatile uint32_t fpga2soc : 1;
298 volatile uint32_t axi_ap : 1;
303 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t;
307 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_RESET 0x00000000
309 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_OFST 0xc
339 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_LSB 0
341 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_MSB 0
343 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_WIDTH 1
345 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_SET_MSK 0x00000001
347 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_CLR_MSK 0xfffffffe
349 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_RESET 0x0
351 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
353 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
366 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_LSB 16
368 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_MSB 16
370 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_WIDTH 1
372 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_SET_MSK 0x00010000
374 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
376 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_RESET 0x0
378 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
380 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
393 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_LSB 24
395 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_MSB 24
397 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_WIDTH 1
399 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_SET_MSK 0x01000000
401 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
403 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_RESET 0x0
405 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
407 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
421 struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
423 volatile uint32_t mpu : 1;
425 volatile uint32_t fpga2soc : 1;
427 volatile uint32_t axi_ap : 1;
432 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t;
436 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_RESET 0x00000000
438 #define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_OFST 0x10
468 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_LSB 0
470 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_MSB 0
472 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_WIDTH 1
474 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_SET_MSK 0x00000001
476 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_CLR_MSK 0xfffffffe
478 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_RESET 0x0
480 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
482 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
495 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_LSB 16
497 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_MSB 16
499 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_WIDTH 1
501 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_SET_MSK 0x00010000
503 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
505 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_RESET 0x0
507 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
509 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
522 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_LSB 24
524 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_MSB 24
526 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_WIDTH 1
528 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_SET_MSK 0x01000000
530 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
532 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_RESET 0x0
534 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
536 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
550 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
552 volatile uint32_t mpu : 1;
554 volatile uint32_t fpga2soc : 1;
556 volatile uint32_t axi_ap : 1;
561 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t;
565 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_RESET 0x00000000
567 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_OFST 0x14
597 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_LSB 0
599 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_MSB 0
601 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_WIDTH 1
603 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_SET_MSK 0x00000001
605 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_CLR_MSK 0xfffffffe
607 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_RESET 0x0
609 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
611 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
624 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_LSB 16
626 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_MSB 16
628 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_WIDTH 1
630 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_SET_MSK 0x00010000
632 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
634 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_RESET 0x0
636 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
638 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
651 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_LSB 24
653 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_MSB 24
655 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_WIDTH 1
657 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_SET_MSK 0x01000000
659 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
661 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_RESET 0x0
663 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
665 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
679 struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
681 volatile uint32_t mpu : 1;
683 volatile uint32_t fpga2soc : 1;
685 volatile uint32_t axi_ap : 1;
690 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t;
694 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_RESET 0x00000000
696 #define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_OFST 0x18
726 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_LSB 0
728 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_MSB 0
730 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_WIDTH 1
732 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_SET_MSK 0x00000001
734 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_CLR_MSK 0xfffffffe
736 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_RESET 0x0
738 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
740 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
753 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_LSB 16
755 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_MSB 16
757 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_WIDTH 1
759 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_SET_MSK 0x00010000
761 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
763 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_RESET 0x0
765 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
767 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
780 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_LSB 24
782 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_MSB 24
784 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_WIDTH 1
786 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_SET_MSK 0x01000000
788 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_CLR_MSK 0xfeffffff
790 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_RESET 0x0
792 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
794 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
808 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
810 volatile uint32_t mpu : 1;
812 volatile uint32_t fpga2soc : 1;
814 volatile uint32_t axi_ap : 1;
819 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t;
823 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_RESET 0x00000000
825 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_OFST 0x1c
855 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_LSB 0
857 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_MSB 0
859 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_WIDTH 1
861 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_SET_MSK 0x00000001
863 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_CLR_MSK 0xfffffffe
865 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_RESET 0x0
867 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
869 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
882 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_LSB 16
884 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_MSB 16
886 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_WIDTH 1
888 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_SET_MSK 0x00010000
890 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
892 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_RESET 0x0
894 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
896 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
909 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_LSB 24
911 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_MSB 24
913 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_WIDTH 1
915 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_SET_MSK 0x01000000
917 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_CLR_MSK 0xfeffffff
919 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_RESET 0x0
921 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
923 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
937 struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
939 volatile uint32_t mpu : 1;
941 volatile uint32_t fpga2soc : 1;
943 volatile uint32_t axi_ap : 1;
948 typedef struct ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t;
952 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_RESET 0x00000000
954 #define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_OFST 0x20
984 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_LSB 0
986 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_MSB 0
988 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_WIDTH 1
990 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_SET_MSK 0x00000001
992 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_CLR_MSK 0xfffffffe
994 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_RESET 0x0
996 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
998 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1011 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_LSB 16
1013 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_MSB 16
1015 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_WIDTH 1
1017 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_SET_MSK 0x00010000
1019 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1021 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_RESET 0x0
1023 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1025 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1038 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_LSB 24
1040 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_MSB 24
1042 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_WIDTH 1
1044 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_SET_MSK 0x01000000
1046 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_CLR_MSK 0xfeffffff
1048 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_RESET 0x0
1050 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1052 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1054 #ifndef __ASSEMBLY__
1066 struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
1068 volatile uint32_t mpu : 1;
1070 volatile uint32_t fpga2soc : 1;
1072 volatile uint32_t axi_ap : 1;
1077 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t;
1081 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_RESET 0x00000000
1083 #define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_OFST 0x2c
1113 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_LSB 0
1115 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_MSB 0
1117 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_WIDTH 1
1119 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_SET_MSK 0x00000001
1121 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_CLR_MSK 0xfffffffe
1123 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_RESET 0x0
1125 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1127 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1140 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_LSB 16
1142 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_MSB 16
1144 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_WIDTH 1
1146 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_SET_MSK 0x00010000
1148 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1150 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_RESET 0x0
1152 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1154 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1167 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_LSB 24
1169 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_MSB 24
1171 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_WIDTH 1
1173 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_SET_MSK 0x01000000
1175 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_CLR_MSK 0xfeffffff
1177 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_RESET 0x0
1179 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1181 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1183 #ifndef __ASSEMBLY__
1195 struct ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_s
1197 volatile uint32_t mpu : 1;
1199 volatile uint32_t fpga2soc : 1;
1201 volatile uint32_t axi_ap : 1;
1206 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_t;
1210 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_RESET 0x00000000
1212 #define ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_OFST 0x30
1242 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_LSB 0
1244 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_MSB 0
1246 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_WIDTH 1
1248 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_SET_MSK 0x00000001
1250 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_CLR_MSK 0xfffffffe
1252 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_RESET 0x0
1254 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1256 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1269 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_LSB 16
1271 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_MSB 16
1273 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_WIDTH 1
1275 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_SET_MSK 0x00010000
1277 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1279 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_RESET 0x0
1281 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1283 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1296 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_LSB 24
1298 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_MSB 24
1300 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_WIDTH 1
1302 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_SET_MSK 0x01000000
1304 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_CLR_MSK 0xfeffffff
1306 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_RESET 0x0
1308 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1310 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1312 #ifndef __ASSEMBLY__
1324 struct ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_s
1326 volatile uint32_t mpu : 1;
1328 volatile uint32_t fpga2soc : 1;
1330 volatile uint32_t axi_ap : 1;
1335 typedef struct ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_s ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_t;
1339 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_RESET 0x00000000
1341 #define ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_OFST 0x34
1371 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_LSB 0
1373 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_MSB 0
1375 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_WIDTH 1
1377 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_SET_MSK 0x00000001
1379 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_CLR_MSK 0xfffffffe
1381 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_RESET 0x0
1383 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1385 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1398 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_LSB 16
1400 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_MSB 16
1402 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_WIDTH 1
1404 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_SET_MSK 0x00010000
1406 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1408 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_RESET 0x0
1410 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1412 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1425 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_LSB 24
1427 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_MSB 24
1429 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_WIDTH 1
1431 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_SET_MSK 0x01000000
1433 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_CLR_MSK 0xfeffffff
1435 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_RESET 0x0
1437 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1439 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1441 #ifndef __ASSEMBLY__
1453 struct ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_s
1455 volatile uint32_t mpu : 1;
1457 volatile uint32_t fpga2soc : 1;
1459 volatile uint32_t axi_ap : 1;
1464 typedef struct ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_s ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_t;
1468 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_RESET 0x00000000
1470 #define ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_OFST 0x38
1500 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_LSB 0
1502 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_MSB 0
1504 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_WIDTH 1
1506 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_SET_MSK 0x00000001
1508 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_CLR_MSK 0xfffffffe
1510 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_RESET 0x0
1512 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1514 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1527 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_LSB 16
1529 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_MSB 16
1531 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_WIDTH 1
1533 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_SET_MSK 0x00010000
1535 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1537 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_RESET 0x0
1539 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1541 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1554 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_LSB 24
1556 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_MSB 24
1558 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_WIDTH 1
1560 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_SET_MSK 0x01000000
1562 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_CLR_MSK 0xfeffffff
1564 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_RESET 0x0
1566 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1568 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1570 #ifndef __ASSEMBLY__
1582 struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
1584 volatile uint32_t mpu : 1;
1586 volatile uint32_t fpga2soc : 1;
1588 volatile uint32_t axi_ap : 1;
1593 typedef struct ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t;
1597 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_RESET 0x00000000
1599 #define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_OFST 0x40
1629 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_LSB 0
1631 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_MSB 0
1633 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_WIDTH 1
1635 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_SET_MSK 0x00000001
1637 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_CLR_MSK 0xfffffffe
1639 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_RESET 0x0
1641 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1643 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1656 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_LSB 16
1658 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_MSB 16
1660 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_WIDTH 1
1662 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_SET_MSK 0x00010000
1664 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1666 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_RESET 0x0
1668 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1670 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1683 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_LSB 24
1685 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_MSB 24
1687 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_WIDTH 1
1689 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_SET_MSK 0x01000000
1691 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_CLR_MSK 0xfeffffff
1693 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_RESET 0x0
1695 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1697 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1699 #ifndef __ASSEMBLY__
1711 struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
1713 volatile uint32_t mpu : 1;
1715 volatile uint32_t fpga2soc : 1;
1717 volatile uint32_t axi_ap : 1;
1722 typedef struct ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t;
1726 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_RESET 0x00000000
1728 #define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_OFST 0x44
1758 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_LSB 0
1760 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_MSB 0
1762 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_WIDTH 1
1764 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_SET_MSK 0x00000001
1766 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_CLR_MSK 0xfffffffe
1768 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_RESET 0x0
1770 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_GET(value) (((value) & 0x00000001) >> 0)
1772 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_SET(value) (((value) << 0) & 0x00000001)
1785 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_LSB 16
1787 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_MSB 16
1789 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_WIDTH 1
1791 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_SET_MSK 0x00010000
1793 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_CLR_MSK 0xfffeffff
1795 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_RESET 0x0
1797 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1799 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1812 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_LSB 24
1814 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_MSB 24
1816 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_WIDTH 1
1818 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_SET_MSK 0x01000000
1820 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_CLR_MSK 0xfeffffff
1822 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_RESET 0x0
1824 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1826 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1828 #ifndef __ASSEMBLY__
1840 struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
1842 volatile uint32_t mpu : 1;
1844 volatile uint32_t fpga2soc : 1;
1846 volatile uint32_t axi_ap : 1;
1851 typedef struct ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t;
1855 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_RESET 0x00000000
1857 #define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_OFST 0x48
1887 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_LSB 0
1889 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_MSB 0
1891 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_WIDTH 1
1893 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_SET_MSK 0x00000001
1895 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_CLR_MSK 0xfffffffe
1897 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_RESET 0x0
1899 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
1901 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
1914 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_LSB 16
1916 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_MSB 16
1918 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_WIDTH 1
1920 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_SET_MSK 0x00010000
1922 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
1924 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_RESET 0x0
1926 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
1928 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
1941 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_LSB 24
1943 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_MSB 24
1945 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_WIDTH 1
1947 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_SET_MSK 0x01000000
1949 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
1951 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_RESET 0x0
1953 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
1955 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
1957 #ifndef __ASSEMBLY__
1969 struct ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_s
1971 volatile uint32_t mpu : 1;
1973 volatile uint32_t fpga2soc : 1;
1975 volatile uint32_t axi_ap : 1;
1980 typedef struct ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_t;
1984 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_RESET 0x00000000
1986 #define ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_OFST 0x4c
2016 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_LSB 0
2018 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_MSB 0
2020 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_WIDTH 1
2022 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_SET_MSK 0x00000001
2024 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_CLR_MSK 0xfffffffe
2026 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_RESET 0x0
2028 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2030 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2043 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_LSB 16
2045 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_MSB 16
2047 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_WIDTH 1
2049 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2051 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2053 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_RESET 0x0
2055 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2057 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2070 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_LSB 24
2072 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_MSB 24
2074 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_WIDTH 1
2076 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_SET_MSK 0x01000000
2078 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2080 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_RESET 0x0
2082 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2084 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2086 #ifndef __ASSEMBLY__
2098 struct ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_s
2100 volatile uint32_t mpu : 1;
2102 volatile uint32_t fpga2soc : 1;
2104 volatile uint32_t axi_ap : 1;
2109 typedef struct ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_t;
2113 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_RESET 0x00000000
2115 #define ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_OFST 0x54
2145 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_LSB 0
2147 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_MSB 0
2149 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_WIDTH 1
2151 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_SET_MSK 0x00000001
2153 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_CLR_MSK 0xfffffffe
2155 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_RESET 0x0
2157 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2159 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2172 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_LSB 16
2174 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_MSB 16
2176 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_WIDTH 1
2178 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2180 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2182 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_RESET 0x0
2184 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2186 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2199 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_LSB 24
2201 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_MSB 24
2203 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_WIDTH 1
2205 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_SET_MSK 0x01000000
2207 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2209 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_RESET 0x0
2211 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2213 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2215 #ifndef __ASSEMBLY__
2227 struct ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_s
2229 volatile uint32_t mpu : 1;
2231 volatile uint32_t fpga2soc : 1;
2233 volatile uint32_t axi_ap : 1;
2238 typedef struct ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_t;
2242 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_RESET 0x00000000
2244 #define ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_OFST 0x58
2274 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_LSB 0
2276 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_MSB 0
2278 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_WIDTH 1
2280 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_SET_MSK 0x00000001
2282 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_CLR_MSK 0xfffffffe
2284 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_RESET 0x0
2286 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2288 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_MPU_SET(value) (((value) << 0) & 0x00000001)
2301 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_LSB 16
2303 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_MSB 16
2305 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_WIDTH 1
2307 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_SET_MSK 0x00010000
2309 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_CLR_MSK 0xfffeffff
2311 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_RESET 0x0
2313 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2315 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2328 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_LSB 24
2330 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_MSB 24
2332 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_WIDTH 1
2334 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_SET_MSK 0x01000000
2336 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_CLR_MSK 0xfeffffff
2338 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_RESET 0x0
2340 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2342 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2344 #ifndef __ASSEMBLY__
2356 struct ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_s
2358 volatile uint32_t mpu : 1;
2360 volatile uint32_t fpga2soc : 1;
2362 volatile uint32_t axi_ap : 1;
2367 typedef struct ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_s ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_t;
2371 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_RESET 0x00000000
2373 #define ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_OFST 0x5c
2405 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_LSB 0
2407 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_MSB 0
2409 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_WIDTH 1
2411 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_SET_MSK 0x00000001
2413 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_CLR_MSK 0xfffffffe
2415 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_RESET 0x0
2417 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2419 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_MPU_SET(value) (((value) << 0) & 0x00000001)
2432 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_LSB 8
2434 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_MSB 8
2436 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_WIDTH 1
2438 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_SET_MSK 0x00000100
2440 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_CLR_MSK 0xfffffeff
2442 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_RESET 0x0
2444 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2446 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_DMA_SET(value) (((value) << 8) & 0x00000100)
2459 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_LSB 16
2461 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_MSB 16
2463 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_WIDTH 1
2465 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_SET_MSK 0x00010000
2467 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_CLR_MSK 0xfffeffff
2469 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_RESET 0x0
2471 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2473 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2486 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_LSB 24
2488 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_MSB 24
2490 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_WIDTH 1
2492 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_SET_MSK 0x01000000
2494 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_CLR_MSK 0xfeffffff
2496 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_RESET 0x0
2498 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2500 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2502 #ifndef __ASSEMBLY__
2514 struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_s
2516 volatile uint32_t mpu : 1;
2518 volatile uint32_t dma : 1;
2520 volatile uint32_t fpga2soc : 1;
2522 volatile uint32_t axi_ap : 1;
2527 typedef struct ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_s ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_t;
2531 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_RESET 0x00000000
2533 #define ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_OFST 0x60
2565 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_LSB 0
2567 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_MSB 0
2569 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_WIDTH 1
2571 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_SET_MSK 0x00000001
2573 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_CLR_MSK 0xfffffffe
2575 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_RESET 0x0
2577 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_GET(value) (((value) & 0x00000001) >> 0)
2579 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_MPU_SET(value) (((value) << 0) & 0x00000001)
2592 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_LSB 8
2594 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_MSB 8
2596 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_WIDTH 1
2598 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_SET_MSK 0x00000100
2600 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_CLR_MSK 0xfffffeff
2602 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_RESET 0x0
2604 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2606 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_DMA_SET(value) (((value) << 8) & 0x00000100)
2619 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_LSB 16
2621 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_MSB 16
2623 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_WIDTH 1
2625 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_SET_MSK 0x00010000
2627 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_CLR_MSK 0xfffeffff
2629 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_RESET 0x0
2631 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2633 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2646 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_LSB 24
2648 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_MSB 24
2650 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_WIDTH 1
2652 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_SET_MSK 0x01000000
2654 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_CLR_MSK 0xfeffffff
2656 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_RESET 0x0
2658 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2660 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2662 #ifndef __ASSEMBLY__
2674 struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_s
2676 volatile uint32_t mpu : 1;
2678 volatile uint32_t dma : 1;
2680 volatile uint32_t fpga2soc : 1;
2682 volatile uint32_t axi_ap : 1;
2687 typedef struct ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_s ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_t;
2691 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_RESET 0x00000000
2693 #define ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_OFST 0x64
2725 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_LSB 0
2727 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_MSB 0
2729 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_WIDTH 1
2731 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_SET_MSK 0x00000001
2733 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_CLR_MSK 0xfffffffe
2735 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_RESET 0x0
2737 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_GET(value) (((value) & 0x00000001) >> 0)
2739 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_MPU_SET(value) (((value) << 0) & 0x00000001)
2752 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_LSB 8
2754 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_MSB 8
2756 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_WIDTH 1
2758 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_SET_MSK 0x00000100
2760 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_CLR_MSK 0xfffffeff
2762 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_RESET 0x0
2764 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2766 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_DMA_SET(value) (((value) << 8) & 0x00000100)
2779 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_LSB 16
2781 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_MSB 16
2783 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_WIDTH 1
2785 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_SET_MSK 0x00010000
2787 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_CLR_MSK 0xfffeffff
2789 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_RESET 0x0
2791 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2793 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2806 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_LSB 24
2808 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_MSB 24
2810 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_WIDTH 1
2812 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_SET_MSK 0x01000000
2814 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_CLR_MSK 0xfeffffff
2816 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_RESET 0x0
2818 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2820 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2822 #ifndef __ASSEMBLY__
2834 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_s
2836 volatile uint32_t mpu : 1;
2838 volatile uint32_t dma : 1;
2840 volatile uint32_t fpga2soc : 1;
2842 volatile uint32_t axi_ap : 1;
2847 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_t;
2851 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_RESET 0x00000000
2853 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_OFST 0x68
2885 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_LSB 0
2887 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_MSB 0
2889 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_WIDTH 1
2891 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_SET_MSK 0x00000001
2893 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_CLR_MSK 0xfffffffe
2895 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_RESET 0x0
2897 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_GET(value) (((value) & 0x00000001) >> 0)
2899 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_MPU_SET(value) (((value) << 0) & 0x00000001)
2912 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_LSB 8
2914 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_MSB 8
2916 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_WIDTH 1
2918 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_SET_MSK 0x00000100
2920 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_CLR_MSK 0xfffffeff
2922 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_RESET 0x0
2924 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2926 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_DMA_SET(value) (((value) << 8) & 0x00000100)
2939 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_LSB 16
2941 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_MSB 16
2943 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_WIDTH 1
2945 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_SET_MSK 0x00010000
2947 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_CLR_MSK 0xfffeffff
2949 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_RESET 0x0
2951 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
2953 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
2966 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_LSB 24
2968 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_MSB 24
2970 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_WIDTH 1
2972 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_SET_MSK 0x01000000
2974 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_CLR_MSK 0xfeffffff
2976 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_RESET 0x0
2978 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
2980 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
2982 #ifndef __ASSEMBLY__
2994 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_s
2996 volatile uint32_t mpu : 1;
2998 volatile uint32_t dma : 1;
3000 volatile uint32_t fpga2soc : 1;
3002 volatile uint32_t axi_ap : 1;
3007 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_t;
3011 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_RESET 0x00000000
3013 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_OFST 0x6c
3045 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_LSB 0
3047 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_MSB 0
3049 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_WIDTH 1
3051 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_SET_MSK 0x00000001
3053 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_CLR_MSK 0xfffffffe
3055 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_RESET 0x0
3057 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_GET(value) (((value) & 0x00000001) >> 0)
3059 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_MPU_SET(value) (((value) << 0) & 0x00000001)
3072 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_LSB 8
3074 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_MSB 8
3076 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_WIDTH 1
3078 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_SET_MSK 0x00000100
3080 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_CLR_MSK 0xfffffeff
3082 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_RESET 0x0
3084 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_GET(value) (((value) & 0x00000100) >> 8)
3086 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_DMA_SET(value) (((value) << 8) & 0x00000100)
3099 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_LSB 16
3101 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_MSB 16
3103 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_WIDTH 1
3105 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_SET_MSK 0x00010000
3107 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_CLR_MSK 0xfffeffff
3109 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_RESET 0x0
3111 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3113 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3126 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_LSB 24
3128 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_MSB 24
3130 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_WIDTH 1
3132 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_SET_MSK 0x01000000
3134 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_CLR_MSK 0xfeffffff
3136 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_RESET 0x0
3138 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3140 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3142 #ifndef __ASSEMBLY__
3154 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_s
3156 volatile uint32_t mpu : 1;
3158 volatile uint32_t dma : 1;
3160 volatile uint32_t fpga2soc : 1;
3162 volatile uint32_t axi_ap : 1;
3167 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_t;
3171 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_RESET 0x00000000
3173 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_OFST 0x70
3205 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_LSB 0
3207 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_MSB 0
3209 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_WIDTH 1
3211 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_SET_MSK 0x00000001
3213 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_CLR_MSK 0xfffffffe
3215 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_RESET 0x0
3217 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_GET(value) (((value) & 0x00000001) >> 0)
3219 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_MPU_SET(value) (((value) << 0) & 0x00000001)
3232 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_LSB 8
3234 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_MSB 8
3236 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_WIDTH 1
3238 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_SET_MSK 0x00000100
3240 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_CLR_MSK 0xfffffeff
3242 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_RESET 0x0
3244 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_GET(value) (((value) & 0x00000100) >> 8)
3246 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_DMA_SET(value) (((value) << 8) & 0x00000100)
3259 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_LSB 16
3261 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_MSB 16
3263 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_WIDTH 1
3265 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_SET_MSK 0x00010000
3267 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_CLR_MSK 0xfffeffff
3269 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_RESET 0x0
3271 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3273 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3286 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_LSB 24
3288 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_MSB 24
3290 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_WIDTH 1
3292 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_SET_MSK 0x01000000
3294 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_CLR_MSK 0xfeffffff
3296 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_RESET 0x0
3298 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3300 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3302 #ifndef __ASSEMBLY__
3314 struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_s
3316 volatile uint32_t mpu : 1;
3318 volatile uint32_t dma : 1;
3320 volatile uint32_t fpga2soc : 1;
3322 volatile uint32_t axi_ap : 1;
3327 typedef struct ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_s ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_t;
3331 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_RESET 0x00000000
3333 #define ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_OFST 0x74
3364 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_LSB 0
3366 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_MSB 0
3368 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_WIDTH 1
3370 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_SET_MSK 0x00000001
3372 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_CLR_MSK 0xfffffffe
3374 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_RESET 0x0
3376 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_GET(value) (((value) & 0x00000001) >> 0)
3378 #define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_SET(value) (((value) << 0) & 0x00000001)
3391 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_LSB 16
3393 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_MSB 16
3395 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_WIDTH 1
3397 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_SET_MSK 0x00010000
3399 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_CLR_MSK 0xfffeffff
3401 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_RESET 0x0
3403 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3405 #define ALT_NOC_FW_L4_SYS_SCR_DAP_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3418 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_LSB 24
3420 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_MSB 24
3422 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_WIDTH 1
3424 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_SET_MSK 0x01000000
3426 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_CLR_MSK 0xfeffffff
3428 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_RESET 0x0
3430 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3432 #define ALT_NOC_FW_L4_SYS_SCR_DAP_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3445 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_LSB 25
3447 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_MSB 25
3449 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_WIDTH 1
3451 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET_MSK 0x02000000
3453 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_CLR_MSK 0xfdffffff
3455 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_RESET 0x0
3457 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_GET(value) (((value) & 0x02000000) >> 25)
3459 #define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET(value) (((value) << 25) & 0x02000000)
3461 #ifndef __ASSEMBLY__
3473 struct ALT_NOC_FW_L4_SYS_SCR_DAP_s
3475 volatile uint32_t mpu : 1;
3477 volatile uint32_t fpga2soc : 1;
3479 volatile uint32_t axi_ap : 1;
3480 volatile uint32_t etr : 1;
3485 typedef struct ALT_NOC_FW_L4_SYS_SCR_DAP_s ALT_NOC_FW_L4_SYS_SCR_DAP_t;
3489 #define ALT_NOC_FW_L4_SYS_SCR_DAP_RESET 0x00000000
3491 #define ALT_NOC_FW_L4_SYS_SCR_DAP_OFST 0x78
3521 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_LSB 0
3523 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_MSB 0
3525 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_WIDTH 1
3527 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_SET_MSK 0x00000001
3529 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_CLR_MSK 0xfffffffe
3531 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_RESET 0x0
3533 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_GET(value) (((value) & 0x00000001) >> 0)
3535 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_MPU_SET(value) (((value) << 0) & 0x00000001)
3548 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_LSB 16
3550 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_MSB 16
3552 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_WIDTH 1
3554 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_SET_MSK 0x00010000
3556 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_CLR_MSK 0xfffeffff
3558 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_RESET 0x0
3560 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3562 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3575 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_LSB 24
3577 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_MSB 24
3579 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_WIDTH 1
3581 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_SET_MSK 0x01000000
3583 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_CLR_MSK 0xfeffffff
3585 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_RESET 0x0
3587 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3589 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3591 #ifndef __ASSEMBLY__
3603 struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_s
3605 volatile uint32_t mpu : 1;
3607 volatile uint32_t fpga2soc : 1;
3609 volatile uint32_t axi_ap : 1;
3614 typedef struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_s ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_t;
3618 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_RESET 0x00000000
3620 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_OFST 0x90
3650 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_LSB 0
3652 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_MSB 0
3654 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_WIDTH 1
3656 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_SET_MSK 0x00000001
3658 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_CLR_MSK 0xfffffffe
3660 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_RESET 0x0
3662 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3664 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_MPU_SET(value) (((value) << 0) & 0x00000001)
3677 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_LSB 16
3679 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_MSB 16
3681 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_WIDTH 1
3683 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_SET_MSK 0x00010000
3685 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_CLR_MSK 0xfffeffff
3687 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_RESET 0x0
3689 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_GET(value) (((value) & 0x00010000) >> 16)
3691 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_FPGA2SOC_SET(value) (((value) << 16) & 0x00010000)
3704 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_LSB 24
3706 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_MSB 24
3708 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_WIDTH 1
3710 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_SET_MSK 0x01000000
3712 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_CLR_MSK 0xfeffffff
3714 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_RESET 0x0
3716 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
3718 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
3720 #ifndef __ASSEMBLY__
3732 struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_s
3734 volatile uint32_t mpu : 1;
3736 volatile uint32_t fpga2soc : 1;
3738 volatile uint32_t axi_ap : 1;
3743 typedef struct ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_s ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_t;
3747 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_RESET 0x00000000
3749 #define ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_OFST 0x94
3751 #ifndef __ASSEMBLY__
3763 struct ALT_NOC_FW_L4_SYS_SCR_s
3765 volatile uint32_t _pad_0x0_0x7[2];
3766 volatile ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t dma_ecc;
3767 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t emac0rx_ecc;
3768 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t emac0tx_ecc;
3769 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t emac1rx_ecc;
3770 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t emac1tx_ecc;
3771 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t emac2rx_ecc;
3772 volatile ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t emac2tx_ecc;
3773 volatile uint32_t _pad_0x24_0x2b[2];
3774 volatile ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t nand_ecc;
3775 volatile ALT_NOC_FW_L4_SYS_SCR_NAND_READ_ECC_t nand_read_ecc;
3776 volatile ALT_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC_t nand_write_ecc;
3777 volatile ALT_NOC_FW_L4_SYS_SCR_OCRAM_ECC_t ocram_ecc;
3778 volatile uint32_t _pad_0x3c_0x3f;
3779 volatile ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t sdmmc_ecc;
3780 volatile ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t usb0_ecc;
3781 volatile ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t usb1_ecc;
3782 volatile ALT_NOC_FW_L4_SYS_SCR_CLOCK_MANAGER_t clock_manager;
3783 volatile uint32_t _pad_0x50_0x53;
3784 volatile ALT_NOC_FW_L4_SYS_SCR_IO_MANAGER_t io_manager;
3785 volatile ALT_NOC_FW_L4_SYS_SCR_RESET_MANAGER_t reset_manager;
3786 volatile ALT_NOC_FW_L4_SYS_SCR_SYSTEM_MANAGER_t system_manager;
3787 volatile ALT_NOC_FW_L4_SYS_SCR_OSC0_TIMER_t osc0_timer;
3788 volatile ALT_NOC_FW_L4_SYS_SCR_OSC1_TIMER_t osc1_timer;
3789 volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG0_t watchdog0;
3790 volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG1_t watchdog1;
3791 volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG2_t watchdog2;
3792 volatile ALT_NOC_FW_L4_SYS_SCR_WATCHDOG3_t watchdog3;
3793 volatile ALT_NOC_FW_L4_SYS_SCR_DAP_t dap;
3794 volatile uint32_t _pad_0x7c_0x8f[5];
3795 volatile ALT_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES_t l4_noc_probes;
3796 volatile ALT_NOC_FW_L4_SYS_SCR_L4_NOC_QOS_t l4_noc_qos;
3797 volatile uint32_t _pad_0x98_0x100[26];
3801 typedef struct ALT_NOC_FW_L4_SYS_SCR_s ALT_NOC_FW_L4_SYS_SCR_t;
3803 struct ALT_NOC_FW_L4_SYS_SCR_raw_s
3805 volatile uint32_t _pad_0x0_0x7[2];
3806 volatile uint32_t dma_ecc;
3807 volatile uint32_t emac0rx_ecc;
3808 volatile uint32_t emac0tx_ecc;
3809 volatile uint32_t emac1rx_ecc;
3810 volatile uint32_t emac1tx_ecc;
3811 volatile uint32_t emac2rx_ecc;
3812 volatile uint32_t emac2tx_ecc;
3813 volatile uint32_t _pad_0x24_0x2b[2];
3814 volatile uint32_t nand_ecc;
3815 volatile uint32_t nand_read_ecc;
3816 volatile uint32_t nand_write_ecc;
3817 volatile uint32_t ocram_ecc;
3818 volatile uint32_t _pad_0x3c_0x3f;
3819 volatile uint32_t sdmmc_ecc;
3820 volatile uint32_t usb0_ecc;
3821 volatile uint32_t usb1_ecc;
3822 volatile uint32_t clock_manager;
3823 volatile uint32_t _pad_0x50_0x53;
3824 volatile uint32_t io_manager;
3825 volatile uint32_t reset_manager;
3826 volatile uint32_t system_manager;
3827 volatile uint32_t osc0_timer;
3828 volatile uint32_t osc1_timer;
3829 volatile uint32_t watchdog0;
3830 volatile uint32_t watchdog1;
3831 volatile uint32_t watchdog2;
3832 volatile uint32_t watchdog3;
3833 volatile uint32_t dap;
3834 volatile uint32_t _pad_0x7c_0x8f[5];
3835 volatile uint32_t l4_noc_probes;
3836 volatile uint32_t l4_noc_qos;
3837 volatile uint32_t _pad_0x98_0x100[26];
3841 typedef struct ALT_NOC_FW_L4_SYS_SCR_raw_s ALT_NOC_FW_L4_SYS_SCR_raw_t;