Hardware Libraries  20.1
Stratix 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_psi.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4 * *
5 * Redistribution and use in source and binary forms, with or without *
6 * modification, are permitted provided that the following conditions are met: *
7 * *
8 * 1. Redistributions of source code must retain the above copyright notice, *
9 * this list of conditions and the following disclaimer. *
10 * *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
12 * this list of conditions and the following disclaimer in the documentation *
13 * and/or other materials provided with the distribution. *
14 * *
15 * 3. Neither the name of the copyright holder nor the names of its contributors *
16 * may be used to endorse or promote products derived from this software without *
17 * specific prior written permission. *
18 * *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29 * POSSIBILITY OF SUCH DAMAGE. *
30 * *
31 ***********************************************************************************/
32 
33 /* Altera - ALT_PSI_PSI_USER */
34 
35 #ifndef __ALT_SOCAL_PSI_H__
36 #define __ALT_SOCAL_PSI_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : PSI_PSI_USER
50  *
51  */
52 /*
53  * Register : LLI_Targ_Svc_PSI_User_TxWidthList
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:--------|:---------------------------------------------------------------
59  * [11:0] | R | 0x201 | ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST
60  * [31:12] | ??? | Unknown | *UNDEFINED*
61  *
62  */
63 /*
64  * Field : TXWIDTHLIST
65  *
66  * Implemented Tx widths
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field. */
72 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field. */
74 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_MSB 11
75 /* The width in bits of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field. */
76 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_WIDTH 12
77 /* The mask used to set the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field value. */
78 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_SET_MSK 0x00000fff
79 /* The mask used to clear the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field value. */
80 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_CLR_MSK 0xfffff000
81 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field. */
82 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_RESET 0x201
83 /* Extracts the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST field value from a register. */
84 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_GET(value) (((value) & 0x00000fff) >> 0)
85 /* Produces a ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST register field value suitable for setting the register. */
86 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST_SET(value) (((value) << 0) & 0x00000fff)
87 
88 #ifndef __ASSEMBLY__
89 /*
90  * WARNING: The C register and register group struct declarations are provided for
91  * convenience and illustrative purposes. They should, however, be used with
92  * caution as the C language standard provides no guarantees about the alignment or
93  * atomicity of device memory accesses. The recommended practice for writing
94  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95  * alt_write_word() functions.
96  *
97  * The struct declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST.
98  */
99 struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_s
100 {
101  const volatile uint32_t TXWIDTHLIST : 12; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_TXWIDTHLIST */
102  uint32_t : 20; /* *UNDEFINED* */
103 };
104 
105 /* The typedef declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST. */
106 typedef struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_s ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_t;
107 #endif /* __ASSEMBLY__ */
108 
109 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST register. */
110 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_RESET 0x00000201
111 /* The byte offset of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST register from the beginning of the component. */
112 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_OFST 0x0
113 
114 /*
115  * Register : LLI_Targ_Svc_PSI_User_RxWidthList
116  *
117  * Register Layout
118  *
119  * Bits | Access | Reset | Description
120  * :--------|:-------|:--------|:---------------------------------------------------------------
121  * [11:0] | R | 0x201 | ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST
122  * [31:12] | ??? | Unknown | *UNDEFINED*
123  *
124  */
125 /*
126  * Field : RXWIDTHLIST
127  *
128  * Implemented Rx widths
129  *
130  * Field Access Macros:
131  *
132  */
133 /* The Least Significant Bit (LSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field. */
134 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_LSB 0
135 /* The Most Significant Bit (MSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field. */
136 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_MSB 11
137 /* The width in bits of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field. */
138 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_WIDTH 12
139 /* The mask used to set the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field value. */
140 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_SET_MSK 0x00000fff
141 /* The mask used to clear the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field value. */
142 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_CLR_MSK 0xfffff000
143 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field. */
144 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_RESET 0x201
145 /* Extracts the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST field value from a register. */
146 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_GET(value) (((value) & 0x00000fff) >> 0)
147 /* Produces a ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST register field value suitable for setting the register. */
148 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST_SET(value) (((value) << 0) & 0x00000fff)
149 
150 #ifndef __ASSEMBLY__
151 /*
152  * WARNING: The C register and register group struct declarations are provided for
153  * convenience and illustrative purposes. They should, however, be used with
154  * caution as the C language standard provides no guarantees about the alignment or
155  * atomicity of device memory accesses. The recommended practice for writing
156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
157  * alt_write_word() functions.
158  *
159  * The struct declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST.
160  */
161 struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_s
162 {
163  const volatile uint32_t RXWIDTHLIST : 12; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RXWIDTHLIST */
164  uint32_t : 20; /* *UNDEFINED* */
165 };
166 
167 /* The typedef declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST. */
168 typedef struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_s ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_t;
169 #endif /* __ASSEMBLY__ */
170 
171 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST register. */
172 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_RESET 0x00000201
173 /* The byte offset of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST register from the beginning of the component. */
174 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_OFST 0x4
175 
176 /*
177  * Register : LLI_Targ_Svc_PSI_User_TxWidth
178  *
179  * Register Layout
180  *
181  * Bits | Access | Reset | Description
182  * :-------|:-------|:--------|:-------------------------------------------------------
183  * [3:0] | RW | 0x0 | ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH
184  * [31:4] | ??? | Unknown | *UNDEFINED*
185  *
186  */
187 /*
188  * Field : TXWIDTH
189  *
190  * Current Tx width
191  *
192  * Field Access Macros:
193  *
194  */
195 /* The Least Significant Bit (LSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field. */
196 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_LSB 0
197 /* The Most Significant Bit (MSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field. */
198 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_MSB 3
199 /* The width in bits of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field. */
200 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_WIDTH 4
201 /* The mask used to set the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field value. */
202 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_SET_MSK 0x0000000f
203 /* The mask used to clear the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field value. */
204 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_CLR_MSK 0xfffffff0
205 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field. */
206 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_RESET 0x0
207 /* Extracts the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH field value from a register. */
208 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
209 /* Produces a ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH register field value suitable for setting the register. */
210 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH_SET(value) (((value) << 0) & 0x0000000f)
211 
212 #ifndef __ASSEMBLY__
213 /*
214  * WARNING: The C register and register group struct declarations are provided for
215  * convenience and illustrative purposes. They should, however, be used with
216  * caution as the C language standard provides no guarantees about the alignment or
217  * atomicity of device memory accesses. The recommended practice for writing
218  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
219  * alt_write_word() functions.
220  *
221  * The struct declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH.
222  */
223 struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_s
224 {
225  volatile uint32_t TXWIDTH : 4; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_TXWIDTH */
226  uint32_t : 28; /* *UNDEFINED* */
227 };
228 
229 /* The typedef declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH. */
230 typedef struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_s ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_t;
231 #endif /* __ASSEMBLY__ */
232 
233 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH register. */
234 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_RESET 0x00000000
235 /* The byte offset of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH register from the beginning of the component. */
236 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_OFST 0x8
237 
238 /*
239  * Register : LLI_Targ_Svc_PSI_User_WidthBusy
240  *
241  * Register Layout
242  *
243  * Bits | Access | Reset | Description
244  * :-------|:-------|:--------|:-----------------------------------------------------------
245  * [0] | R | Unknown | ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY
246  * [31:1] | ??? | Unknown | *UNDEFINED*
247  *
248  */
249 /*
250  * Field : WIDTHBUSY
251  *
252  * Current TxWidth not yet effective on the PSI link
253  *
254  * Field Access Macros:
255  *
256  */
257 /* The Least Significant Bit (LSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field. */
258 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_LSB 0
259 /* The Most Significant Bit (MSB) position of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field. */
260 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_MSB 0
261 /* The width in bits of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field. */
262 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_WIDTH 1
263 /* The mask used to set the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field value. */
264 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_SET_MSK 0x00000001
265 /* The mask used to clear the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field value. */
266 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_CLR_MSK 0xfffffffe
267 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field is UNKNOWN. */
268 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_RESET 0x0
269 /* Extracts the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY field value from a register. */
270 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_GET(value) (((value) & 0x00000001) >> 0)
271 /* Produces a ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY register field value suitable for setting the register. */
272 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY_SET(value) (((value) << 0) & 0x00000001)
273 
274 #ifndef __ASSEMBLY__
275 /*
276  * WARNING: The C register and register group struct declarations are provided for
277  * convenience and illustrative purposes. They should, however, be used with
278  * caution as the C language standard provides no guarantees about the alignment or
279  * atomicity of device memory accesses. The recommended practice for writing
280  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
281  * alt_write_word() functions.
282  *
283  * The struct declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY.
284  */
285 struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_s
286 {
287  const volatile uint32_t WIDTHBUSY : 1; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_WIDTHBUSY */
288  uint32_t : 31; /* *UNDEFINED* */
289 };
290 
291 /* The typedef declaration for register ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY. */
292 typedef struct ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_s ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_t;
293 #endif /* __ASSEMBLY__ */
294 
295 /* The reset value of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY register. */
296 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_RESET 0x00000000
297 /* The byte offset of the ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY register from the beginning of the component. */
298 #define ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_OFST 0xc
299 
300 #ifndef __ASSEMBLY__
301 /*
302  * WARNING: The C register and register group struct declarations are provided for
303  * convenience and illustrative purposes. They should, however, be used with
304  * caution as the C language standard provides no guarantees about the alignment or
305  * atomicity of device memory accesses. The recommended practice for writing
306  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
307  * alt_write_word() functions.
308  *
309  * The struct declaration for register group ALT_PSI_PSI_USER.
310  */
311 struct ALT_PSI_PSI_USER_s
312 {
313  volatile ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST_t LLI_Targ_Svc_PSI_User_TxWidthList; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST */
314  volatile ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST_t LLI_Targ_Svc_PSI_User_RxWidthList; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST */
315  volatile ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH_t LLI_Targ_Svc_PSI_User_TxWidth; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH */
316  volatile ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY_t LLI_Targ_Svc_PSI_User_WidthBusy; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY */
317  volatile uint32_t _pad_0x10_0x400[252]; /* *UNDEFINED* */
318 };
319 
320 /* The typedef declaration for register group ALT_PSI_PSI_USER. */
321 typedef struct ALT_PSI_PSI_USER_s ALT_PSI_PSI_USER_t;
322 /* The struct declaration for the raw register contents of register group ALT_PSI_PSI_USER. */
323 struct ALT_PSI_PSI_USER_raw_s
324 {
325  volatile uint32_t LLI_Targ_Svc_PSI_User_TxWidthList; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTHLIST */
326  volatile uint32_t LLI_Targ_Svc_PSI_User_RxWidthList; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_RXWIDTHLIST */
327  volatile uint32_t LLI_Targ_Svc_PSI_User_TxWidth; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_TXWIDTH */
328  volatile uint32_t LLI_Targ_Svc_PSI_User_WidthBusy; /* ALT_PSI_PSI_USER_LLI_TARG_SVC_PSI_USER_WIDTHBUSY */
329  volatile uint32_t _pad_0x10_0x400[252]; /* *UNDEFINED* */
330 };
331 
332 /* The typedef declaration for the raw register contents of register group ALT_PSI_PSI_USER. */
333 typedef struct ALT_PSI_PSI_USER_raw_s ALT_PSI_PSI_USER_raw_t;
334 #endif /* __ASSEMBLY__ */
335 
336 
337 /*
338  * Component : PSI_LLI_CTRL
339  *
340  */
341 /*
342  * Register : LLI_Targ_Svc_LLI_Ctrl_LL_Initiator_socket_present
343  *
344  * Register Layout
345  *
346  * Bits | Access | Reset | Description
347  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------------
348  * [0] | R | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT
349  * [31:1] | ??? | Unknown | *UNDEFINED*
350  *
351  */
352 /*
353  * Field : LL_INITIATOR_SOCKET_PRESENT
354  *
355  * An Initiator socket is present on the TL_LL_SAP when is at '1'. (Capability)
356  *
357  * Field Access Macros:
358  *
359  */
360 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field. */
361 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_LSB 0
362 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field. */
363 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_MSB 0
364 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field. */
365 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_WIDTH 1
366 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field value. */
367 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_SET_MSK 0x00000001
368 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field value. */
369 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_CLR_MSK 0xfffffffe
370 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field. */
371 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_RESET 0x1
372 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT field value from a register. */
373 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_GET(value) (((value) & 0x00000001) >> 0)
374 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT register field value suitable for setting the register. */
375 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT_SET(value) (((value) << 0) & 0x00000001)
376 
377 #ifndef __ASSEMBLY__
378 /*
379  * WARNING: The C register and register group struct declarations are provided for
380  * convenience and illustrative purposes. They should, however, be used with
381  * caution as the C language standard provides no guarantees about the alignment or
382  * atomicity of device memory accesses. The recommended practice for writing
383  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
384  * alt_write_word() functions.
385  *
386  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT.
387  */
388 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_s
389 {
390  const volatile uint32_t LL_INITIATOR_SOCKET_PRESENT : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_LL_INITIATOR_SOCKET_PRESENT */
391  uint32_t : 31; /* *UNDEFINED* */
392 };
393 
394 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT. */
395 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_t;
396 #endif /* __ASSEMBLY__ */
397 
398 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT register. */
399 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_RESET 0x00000001
400 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT register from the beginning of the component. */
401 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_OFST 0x0
402 
403 /*
404  * Register : LLI_Targ_Svc_LLI_Ctrl_LL_Target_socket_present
405  *
406  * Register Layout
407  *
408  * Bits | Access | Reset | Description
409  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
410  * [0] | R | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT
411  * [31:1] | ??? | Unknown | *UNDEFINED*
412  *
413  */
414 /*
415  * Field : LL_TARGET_SOCKET_PRESENT
416  *
417  * A Target socket is present on the TL_LL_SAP when is at '1'. (Capability)
418  *
419  * Field Access Macros:
420  *
421  */
422 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field. */
423 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_LSB 0
424 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field. */
425 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_MSB 0
426 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field. */
427 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_WIDTH 1
428 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field value. */
429 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_SET_MSK 0x00000001
430 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field value. */
431 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_CLR_MSK 0xfffffffe
432 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field. */
433 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_RESET 0x1
434 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT field value from a register. */
435 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_GET(value) (((value) & 0x00000001) >> 0)
436 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT register field value suitable for setting the register. */
437 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT_SET(value) (((value) << 0) & 0x00000001)
438 
439 #ifndef __ASSEMBLY__
440 /*
441  * WARNING: The C register and register group struct declarations are provided for
442  * convenience and illustrative purposes. They should, however, be used with
443  * caution as the C language standard provides no guarantees about the alignment or
444  * atomicity of device memory accesses. The recommended practice for writing
445  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
446  * alt_write_word() functions.
447  *
448  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT.
449  */
450 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_s
451 {
452  const volatile uint32_t LL_TARGET_SOCKET_PRESENT : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_LL_TARGET_SOCKET_PRESENT */
453  uint32_t : 31; /* *UNDEFINED* */
454 };
455 
456 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT. */
457 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_t;
458 #endif /* __ASSEMBLY__ */
459 
460 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT register. */
461 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_RESET 0x00000001
462 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT register from the beginning of the component. */
463 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_OFST 0x4
464 
465 /*
466  * Register : LLI_Targ_Svc_LLI_Ctrl_BE_Initiator_socket_present
467  *
468  * Register Layout
469  *
470  * Bits | Access | Reset | Description
471  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------------
472  * [0] | R | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT
473  * [31:1] | ??? | Unknown | *UNDEFINED*
474  *
475  */
476 /*
477  * Field : BE_INITIATOR_SOCKET_PRESENT
478  *
479  * An Initiator socket is present on the TL_BE_SAP when is at '1'. (Capability)
480  *
481  * Field Access Macros:
482  *
483  */
484 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field. */
485 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_LSB 0
486 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field. */
487 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_MSB 0
488 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field. */
489 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_WIDTH 1
490 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field value. */
491 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_SET_MSK 0x00000001
492 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field value. */
493 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_CLR_MSK 0xfffffffe
494 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field. */
495 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_RESET 0x1
496 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT field value from a register. */
497 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_GET(value) (((value) & 0x00000001) >> 0)
498 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT register field value suitable for setting the register. */
499 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT_SET(value) (((value) << 0) & 0x00000001)
500 
501 #ifndef __ASSEMBLY__
502 /*
503  * WARNING: The C register and register group struct declarations are provided for
504  * convenience and illustrative purposes. They should, however, be used with
505  * caution as the C language standard provides no guarantees about the alignment or
506  * atomicity of device memory accesses. The recommended practice for writing
507  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
508  * alt_write_word() functions.
509  *
510  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT.
511  */
512 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_s
513 {
514  const volatile uint32_t BE_INITIATOR_SOCKET_PRESENT : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_BE_INITIATOR_SOCKET_PRESENT */
515  uint32_t : 31; /* *UNDEFINED* */
516 };
517 
518 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT. */
519 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_t;
520 #endif /* __ASSEMBLY__ */
521 
522 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT register. */
523 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_RESET 0x00000001
524 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT register from the beginning of the component. */
525 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_OFST 0x8
526 
527 /*
528  * Register : LLI_Targ_Svc_LLI_Ctrl_BE_Target_socket_present
529  *
530  * Register Layout
531  *
532  * Bits | Access | Reset | Description
533  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------
534  * [0] | R | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT
535  * [31:1] | ??? | Unknown | *UNDEFINED*
536  *
537  */
538 /*
539  * Field : BE_TARGET_SOCKET_PRESENT
540  *
541  * A Target socket is present on the TL_BE_SAP when is at '1'. (Capability)
542  *
543  * Field Access Macros:
544  *
545  */
546 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field. */
547 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_LSB 0
548 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field. */
549 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_MSB 0
550 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field. */
551 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_WIDTH 1
552 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field value. */
553 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_SET_MSK 0x00000001
554 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field value. */
555 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_CLR_MSK 0xfffffffe
556 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field. */
557 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_RESET 0x1
558 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT field value from a register. */
559 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_GET(value) (((value) & 0x00000001) >> 0)
560 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT register field value suitable for setting the register. */
561 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT_SET(value) (((value) << 0) & 0x00000001)
562 
563 #ifndef __ASSEMBLY__
564 /*
565  * WARNING: The C register and register group struct declarations are provided for
566  * convenience and illustrative purposes. They should, however, be used with
567  * caution as the C language standard provides no guarantees about the alignment or
568  * atomicity of device memory accesses. The recommended practice for writing
569  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
570  * alt_write_word() functions.
571  *
572  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT.
573  */
574 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_s
575 {
576  const volatile uint32_t BE_TARGET_SOCKET_PRESENT : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_BE_TARGET_SOCKET_PRESENT */
577  uint32_t : 31; /* *UNDEFINED* */
578 };
579 
580 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT. */
581 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_t;
582 #endif /* __ASSEMBLY__ */
583 
584 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT register. */
585 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_RESET 0x00000001
586 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT register from the beginning of the component. */
587 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_OFST 0xc
588 
589 /*
590  * Register : LLI_Targ_Svc_LLI_Ctrl_SVC_Initiator_socket_present
591  *
592  * Register Layout
593  *
594  * Bits | Access | Reset | Description
595  * :-------|:-------|:--------|:-------------------------------------------------------------------------------------------------
596  * [0] | R | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT
597  * [31:1] | ??? | Unknown | *UNDEFINED*
598  *
599  */
600 /*
601  * Field : SVC_INITIATOR_SOCKET_PRESENT
602  *
603  * An Initiator socket is present on the TL_SVC_SAP when is at '1'. (Capability)
604  *
605  * Field Access Macros:
606  *
607  */
608 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field. */
609 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_LSB 0
610 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field. */
611 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_MSB 0
612 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field. */
613 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_WIDTH 1
614 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field value. */
615 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_SET_MSK 0x00000001
616 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field value. */
617 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_CLR_MSK 0xfffffffe
618 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field. */
619 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_RESET 0x1
620 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT field value from a register. */
621 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_GET(value) (((value) & 0x00000001) >> 0)
622 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT register field value suitable for setting the register. */
623 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT_SET(value) (((value) << 0) & 0x00000001)
624 
625 #ifndef __ASSEMBLY__
626 /*
627  * WARNING: The C register and register group struct declarations are provided for
628  * convenience and illustrative purposes. They should, however, be used with
629  * caution as the C language standard provides no guarantees about the alignment or
630  * atomicity of device memory accesses. The recommended practice for writing
631  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
632  * alt_write_word() functions.
633  *
634  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT.
635  */
636 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_s
637 {
638  const volatile uint32_t SVC_INITIATOR_SOCKET_PRESENT : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_SVC_INITIATOR_SOCKET_PRESENT */
639  uint32_t : 31; /* *UNDEFINED* */
640 };
641 
642 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT. */
643 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_t;
644 #endif /* __ASSEMBLY__ */
645 
646 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT register. */
647 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_RESET 0x00000001
648 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT register from the beginning of the component. */
649 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_OFST 0x10
650 
651 /*
652  * Register : LLI_Targ_Svc_LLI_Ctrl_LL_TC_disable
653  *
654  * Register Layout
655  *
656  * Bits | Access | Reset | Description
657  * :-------|:-------|:--------|:-------------------------------------------------------------------
658  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE
659  * [31:1] | ??? | Unknown | *UNDEFINED*
660  *
661  */
662 /*
663  * Field : LL_TC_DISABLE
664  *
665  * Disable the LL traffic class when set the value is set to '1'.
666  *
667  * Field Access Macros:
668  *
669  */
670 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field. */
671 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_LSB 0
672 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field. */
673 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_MSB 0
674 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field. */
675 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_WIDTH 1
676 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field value. */
677 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_SET_MSK 0x00000001
678 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field value. */
679 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_CLR_MSK 0xfffffffe
680 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field. */
681 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_RESET 0x0
682 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE field value from a register. */
683 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_GET(value) (((value) & 0x00000001) >> 0)
684 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE register field value suitable for setting the register. */
685 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE_SET(value) (((value) << 0) & 0x00000001)
686 
687 #ifndef __ASSEMBLY__
688 /*
689  * WARNING: The C register and register group struct declarations are provided for
690  * convenience and illustrative purposes. They should, however, be used with
691  * caution as the C language standard provides no guarantees about the alignment or
692  * atomicity of device memory accesses. The recommended practice for writing
693  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
694  * alt_write_word() functions.
695  *
696  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE.
697  */
698 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_s
699 {
700  volatile uint32_t LL_TC_DISABLE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_LL_TC_DISABLE */
701  uint32_t : 31; /* *UNDEFINED* */
702 };
703 
704 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE. */
705 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_t;
706 #endif /* __ASSEMBLY__ */
707 
708 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE register. */
709 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_RESET 0x00000000
710 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE register from the beginning of the component. */
711 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_OFST 0x100
712 
713 /*
714  * Register : LLI_Targ_Svc_LLI_Ctrl_BE_TC_disable
715  *
716  * Register Layout
717  *
718  * Bits | Access | Reset | Description
719  * :-------|:-------|:--------|:-------------------------------------------------------------------
720  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE
721  * [31:1] | ??? | Unknown | *UNDEFINED*
722  *
723  */
724 /*
725  * Field : BE_TC_DISABLE
726  *
727  * Disable the BE traffic class when set the value is set to '1'.
728  *
729  * Field Access Macros:
730  *
731  */
732 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field. */
733 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_LSB 0
734 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field. */
735 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_MSB 0
736 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field. */
737 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_WIDTH 1
738 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field value. */
739 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_SET_MSK 0x00000001
740 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field value. */
741 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_CLR_MSK 0xfffffffe
742 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field. */
743 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_RESET 0x0
744 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE field value from a register. */
745 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_GET(value) (((value) & 0x00000001) >> 0)
746 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE register field value suitable for setting the register. */
747 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE_SET(value) (((value) << 0) & 0x00000001)
748 
749 #ifndef __ASSEMBLY__
750 /*
751  * WARNING: The C register and register group struct declarations are provided for
752  * convenience and illustrative purposes. They should, however, be used with
753  * caution as the C language standard provides no guarantees about the alignment or
754  * atomicity of device memory accesses. The recommended practice for writing
755  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
756  * alt_write_word() functions.
757  *
758  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE.
759  */
760 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_s
761 {
762  volatile uint32_t BE_TC_DISABLE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_BE_TC_DISABLE */
763  uint32_t : 31; /* *UNDEFINED* */
764 };
765 
766 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE. */
767 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_t;
768 #endif /* __ASSEMBLY__ */
769 
770 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE register. */
771 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_RESET 0x00000000
772 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE register from the beginning of the component. */
773 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_OFST 0x104
774 
775 /*
776  * Register : LLI_Targ_Svc_LLI_Ctrl_CSA_System_Status
777  *
778  * Status of the CSA_System.
779  *
780  * Register Layout
781  *
782  * Bits | Access | Reset | Description
783  * :-------|:-------|:--------|:---------------------------------------------------------------------------------
784  * [0] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED
785  * [1] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE
786  * [2] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL
787  * [3] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED
788  * [4] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION
789  * [31:5] | ??? | Unknown | *UNDEFINED*
790  *
791  */
792 /*
793  * Field : LLI_MOUNTED
794  *
795  * Status of LLI mounted state.
796  *
797  * Field Access Macros:
798  *
799  */
800 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field. */
801 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_LSB 0
802 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field. */
803 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_MSB 0
804 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field. */
805 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_WIDTH 1
806 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field value. */
807 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_SET_MSK 0x00000001
808 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field value. */
809 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_CLR_MSK 0xfffffffe
810 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field. */
811 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_RESET 0x0
812 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED field value from a register. */
813 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_GET(value) (((value) & 0x00000001) >> 0)
814 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED register field value suitable for setting the register. */
815 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED_SET(value) (((value) << 0) & 0x00000001)
816 
817 /*
818  * Field : MASTER_NOT_SLAVE
819  *
820  * Status of the LLI master/slave setting.
821  *
822  * Field Access Macros:
823  *
824  */
825 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field. */
826 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_LSB 1
827 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field. */
828 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_MSB 1
829 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field. */
830 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_WIDTH 1
831 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field value. */
832 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_SET_MSK 0x00000002
833 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field value. */
834 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_CLR_MSK 0xfffffffd
835 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field. */
836 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_RESET 0x0
837 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE field value from a register. */
838 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_GET(value) (((value) & 0x00000002) >> 1)
839 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE register field value suitable for setting the register. */
840 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE_SET(value) (((value) << 1) & 0x00000002)
841 
842 /*
843  * Field : LLI_MOUNT_CTRL
844  *
845  * Status of the LLI mount control.
846  *
847  * Field Access Macros:
848  *
849  */
850 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field. */
851 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_LSB 2
852 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field. */
853 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_MSB 2
854 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field. */
855 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_WIDTH 1
856 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field value. */
857 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_SET_MSK 0x00000004
858 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field value. */
859 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_CLR_MSK 0xfffffffb
860 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field. */
861 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_RESET 0x0
862 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL field value from a register. */
863 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_GET(value) (((value) & 0x00000004) >> 2)
864 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL register field value suitable for setting the register. */
865 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL_SET(value) (((value) << 2) & 0x00000004)
866 
867 /*
868  * Field : RESET_ON_ERROR_DETECTED
869  *
870  * Status of the LLI reset on error detection.
871  *
872  * Field Access Macros:
873  *
874  */
875 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field. */
876 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_LSB 3
877 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field. */
878 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_MSB 3
879 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field. */
880 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_WIDTH 1
881 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field value. */
882 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_SET_MSK 0x00000008
883 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field value. */
884 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_CLR_MSK 0xfffffff7
885 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field. */
886 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_RESET 0x0
887 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED field value from a register. */
888 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_GET(value) (((value) & 0x00000008) >> 3)
889 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED register field value suitable for setting the register. */
890 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED_SET(value) (((value) << 3) & 0x00000008)
891 
892 /*
893  * Field : IPC_STATUS_INDICATION
894  *
895  * Status of the LLI IPC.
896  *
897  * Field Access Macros:
898  *
899  */
900 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field. */
901 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_LSB 4
902 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field. */
903 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_MSB 4
904 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field. */
905 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_WIDTH 1
906 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field value. */
907 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_SET_MSK 0x00000010
908 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field value. */
909 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_CLR_MSK 0xffffffef
910 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field. */
911 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_RESET 0x0
912 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION field value from a register. */
913 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_GET(value) (((value) & 0x00000010) >> 4)
914 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION register field value suitable for setting the register. */
915 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION_SET(value) (((value) << 4) & 0x00000010)
916 
917 #ifndef __ASSEMBLY__
918 /*
919  * WARNING: The C register and register group struct declarations are provided for
920  * convenience and illustrative purposes. They should, however, be used with
921  * caution as the C language standard provides no guarantees about the alignment or
922  * atomicity of device memory accesses. The recommended practice for writing
923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
924  * alt_write_word() functions.
925  *
926  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS.
927  */
928 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_s
929 {
930  const volatile uint32_t LLI_MOUNTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNTED */
931  const volatile uint32_t MASTER_NOT_SLAVE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_MASTER_NOT_SLAVE */
932  const volatile uint32_t LLI_MOUNT_CTRL : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_LLI_MOUNT_CTRL */
933  const volatile uint32_t RESET_ON_ERROR_DETECTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET_ON_ERROR_DETECTED */
934  const volatile uint32_t IPC_STATUS_INDICATION : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_IPC_STATUS_INDICATION */
935  uint32_t : 27; /* *UNDEFINED* */
936 };
937 
938 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS. */
939 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_t;
940 #endif /* __ASSEMBLY__ */
941 
942 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS register. */
943 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_RESET 0x00000000
944 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS register from the beginning of the component. */
945 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_OFST 0x108
946 
947 /*
948  * Register : LLI_Targ_Svc_LLI_Ctrl_CSA_System_Set
949  *
950  * The bit fields of the CSA_System are set by writing a '1' in the desired field
951  * in the CSA_System_Set attribute.
952  *
953  * Register Layout
954  *
955  * Bits | Access | Reset | Description
956  * :-------|:-------|:--------|:------------------------------------------------------------------------------
957  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED
958  * [1] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE
959  * [2] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL
960  * [3] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED
961  * [4] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION
962  * [31:5] | ??? | Unknown | *UNDEFINED*
963  *
964  */
965 /*
966  * Field : LLI_MOUNTED
967  *
968  * Sets LLI_Mounted.
969  *
970  * Field Access Macros:
971  *
972  */
973 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field. */
974 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_LSB 0
975 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field. */
976 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_MSB 0
977 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field. */
978 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_WIDTH 1
979 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field value. */
980 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_SET_MSK 0x00000001
981 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field value. */
982 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_CLR_MSK 0xfffffffe
983 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field. */
984 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_RESET 0x0
985 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED field value from a register. */
986 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_GET(value) (((value) & 0x00000001) >> 0)
987 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED register field value suitable for setting the register. */
988 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED_SET(value) (((value) << 0) & 0x00000001)
989 
990 /*
991  * Field : MASTER_NOT_SLAVE
992  *
993  * Sets Master_Not_Slave.
994  *
995  * Field Access Macros:
996  *
997  */
998 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field. */
999 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_LSB 1
1000 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field. */
1001 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_MSB 1
1002 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field. */
1003 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_WIDTH 1
1004 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field value. */
1005 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_SET_MSK 0x00000002
1006 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field value. */
1007 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_CLR_MSK 0xfffffffd
1008 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field. */
1009 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_RESET 0x0
1010 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE field value from a register. */
1011 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_GET(value) (((value) & 0x00000002) >> 1)
1012 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE register field value suitable for setting the register. */
1013 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE_SET(value) (((value) << 1) & 0x00000002)
1014 
1015 /*
1016  * Field : LLI_MOUNT_CTRL
1017  *
1018  * Sets LLI_Mount_CTRL.
1019  *
1020  * Field Access Macros:
1021  *
1022  */
1023 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field. */
1024 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_LSB 2
1025 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field. */
1026 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_MSB 2
1027 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field. */
1028 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_WIDTH 1
1029 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field value. */
1030 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_SET_MSK 0x00000004
1031 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field value. */
1032 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_CLR_MSK 0xfffffffb
1033 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field. */
1034 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_RESET 0x0
1035 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL field value from a register. */
1036 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_GET(value) (((value) & 0x00000004) >> 2)
1037 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL register field value suitable for setting the register. */
1038 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL_SET(value) (((value) << 2) & 0x00000004)
1039 
1040 /*
1041  * Field : RESET_ON_ERROR_DETECTED
1042  *
1043  * Sets Reset_On_Error_Detected.
1044  *
1045  * Field Access Macros:
1046  *
1047  */
1048 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field. */
1049 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_LSB 3
1050 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field. */
1051 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_MSB 3
1052 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field. */
1053 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_WIDTH 1
1054 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field value. */
1055 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_SET_MSK 0x00000008
1056 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field value. */
1057 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_CLR_MSK 0xfffffff7
1058 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field. */
1059 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_RESET 0x0
1060 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED field value from a register. */
1061 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_GET(value) (((value) & 0x00000008) >> 3)
1062 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED register field value suitable for setting the register. */
1063 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED_SET(value) (((value) << 3) & 0x00000008)
1064 
1065 /*
1066  * Field : IPC_STATUS_INDICATION
1067  *
1068  * Sets IPC_Status_Indication.
1069  *
1070  * Field Access Macros:
1071  *
1072  */
1073 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field. */
1074 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_LSB 4
1075 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field. */
1076 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_MSB 4
1077 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field. */
1078 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_WIDTH 1
1079 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field value. */
1080 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_SET_MSK 0x00000010
1081 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field value. */
1082 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_CLR_MSK 0xffffffef
1083 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field. */
1084 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_RESET 0x0
1085 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION field value from a register. */
1086 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_GET(value) (((value) & 0x00000010) >> 4)
1087 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION register field value suitable for setting the register. */
1088 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION_SET(value) (((value) << 4) & 0x00000010)
1089 
1090 #ifndef __ASSEMBLY__
1091 /*
1092  * WARNING: The C register and register group struct declarations are provided for
1093  * convenience and illustrative purposes. They should, however, be used with
1094  * caution as the C language standard provides no guarantees about the alignment or
1095  * atomicity of device memory accesses. The recommended practice for writing
1096  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1097  * alt_write_word() functions.
1098  *
1099  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET.
1100  */
1101 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_s
1102 {
1103  volatile uint32_t LLI_MOUNTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNTED */
1104  volatile uint32_t MASTER_NOT_SLAVE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_MASTER_NOT_SLAVE */
1105  volatile uint32_t LLI_MOUNT_CTRL : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_LLI_MOUNT_CTRL */
1106  volatile uint32_t RESET_ON_ERROR_DETECTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET_ON_ERROR_DETECTED */
1107  volatile uint32_t IPC_STATUS_INDICATION : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_IPC_STATUS_INDICATION */
1108  uint32_t : 27; /* *UNDEFINED* */
1109 };
1110 
1111 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET. */
1112 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_t;
1113 #endif /* __ASSEMBLY__ */
1114 
1115 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET register. */
1116 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_RESET 0x00000000
1117 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET register from the beginning of the component. */
1118 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_OFST 0x10c
1119 
1120 /*
1121  * Register : LLI_Targ_Svc_LLI_Ctrl_CSA_System_Clear
1122  *
1123  * The bit fields of the CSA_System are cleared by writing a '1' in the desired
1124  * field in the CSA_System_Clear attribute.
1125  *
1126  * Register Layout
1127  *
1128  * Bits | Access | Reset | Description
1129  * :-------|:-------|:--------|:--------------------------------------------------------------------------------
1130  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED
1131  * [1] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE
1132  * [2] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL
1133  * [3] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED
1134  * [4] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION
1135  * [31:5] | ??? | Unknown | *UNDEFINED*
1136  *
1137  */
1138 /*
1139  * Field : LLI_MOUNTED
1140  *
1141  * Clears LLI_Mounted.
1142  *
1143  * Field Access Macros:
1144  *
1145  */
1146 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field. */
1147 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_LSB 0
1148 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field. */
1149 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_MSB 0
1150 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field. */
1151 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_WIDTH 1
1152 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field value. */
1153 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_SET_MSK 0x00000001
1154 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field value. */
1155 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_CLR_MSK 0xfffffffe
1156 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field. */
1157 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_RESET 0x0
1158 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED field value from a register. */
1159 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_GET(value) (((value) & 0x00000001) >> 0)
1160 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED register field value suitable for setting the register. */
1161 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED_SET(value) (((value) << 0) & 0x00000001)
1162 
1163 /*
1164  * Field : MASTER_NOT_SLAVE
1165  *
1166  * Clears Master_Not_Slave.
1167  *
1168  * Field Access Macros:
1169  *
1170  */
1171 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field. */
1172 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_LSB 1
1173 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field. */
1174 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_MSB 1
1175 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field. */
1176 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_WIDTH 1
1177 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field value. */
1178 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_SET_MSK 0x00000002
1179 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field value. */
1180 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_CLR_MSK 0xfffffffd
1181 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field. */
1182 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_RESET 0x0
1183 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE field value from a register. */
1184 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_GET(value) (((value) & 0x00000002) >> 1)
1185 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE register field value suitable for setting the register. */
1186 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE_SET(value) (((value) << 1) & 0x00000002)
1187 
1188 /*
1189  * Field : LLI_MOUNT_CTRL
1190  *
1191  * Clears LLI_Mount_CTRL.
1192  *
1193  * Field Access Macros:
1194  *
1195  */
1196 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field. */
1197 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_LSB 2
1198 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field. */
1199 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_MSB 2
1200 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field. */
1201 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_WIDTH 1
1202 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field value. */
1203 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_SET_MSK 0x00000004
1204 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field value. */
1205 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_CLR_MSK 0xfffffffb
1206 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field. */
1207 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_RESET 0x0
1208 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL field value from a register. */
1209 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_GET(value) (((value) & 0x00000004) >> 2)
1210 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL register field value suitable for setting the register. */
1211 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL_SET(value) (((value) << 2) & 0x00000004)
1212 
1213 /*
1214  * Field : RESET_ON_ERROR_DETECTED
1215  *
1216  * Clears Reset_On_Error_Detected.
1217  *
1218  * Field Access Macros:
1219  *
1220  */
1221 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field. */
1222 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_LSB 3
1223 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field. */
1224 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_MSB 3
1225 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field. */
1226 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_WIDTH 1
1227 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field value. */
1228 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_SET_MSK 0x00000008
1229 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field value. */
1230 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_CLR_MSK 0xfffffff7
1231 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field. */
1232 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_RESET 0x0
1233 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED field value from a register. */
1234 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_GET(value) (((value) & 0x00000008) >> 3)
1235 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED register field value suitable for setting the register. */
1236 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED_SET(value) (((value) << 3) & 0x00000008)
1237 
1238 /*
1239  * Field : IPC_STATUS_INDICATION
1240  *
1241  * Clears IPC_Status_Indication.
1242  *
1243  * Field Access Macros:
1244  *
1245  */
1246 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field. */
1247 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_LSB 4
1248 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field. */
1249 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_MSB 4
1250 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field. */
1251 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_WIDTH 1
1252 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field value. */
1253 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_SET_MSK 0x00000010
1254 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field value. */
1255 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_CLR_MSK 0xffffffef
1256 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field. */
1257 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_RESET 0x0
1258 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION field value from a register. */
1259 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_GET(value) (((value) & 0x00000010) >> 4)
1260 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION register field value suitable for setting the register. */
1261 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION_SET(value) (((value) << 4) & 0x00000010)
1262 
1263 #ifndef __ASSEMBLY__
1264 /*
1265  * WARNING: The C register and register group struct declarations are provided for
1266  * convenience and illustrative purposes. They should, however, be used with
1267  * caution as the C language standard provides no guarantees about the alignment or
1268  * atomicity of device memory accesses. The recommended practice for writing
1269  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1270  * alt_write_word() functions.
1271  *
1272  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR.
1273  */
1274 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_s
1275 {
1276  volatile uint32_t LLI_MOUNTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNTED */
1277  volatile uint32_t MASTER_NOT_SLAVE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_MASTER_NOT_SLAVE */
1278  volatile uint32_t LLI_MOUNT_CTRL : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_LLI_MOUNT_CTRL */
1279  volatile uint32_t RESET_ON_ERROR_DETECTED : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET_ON_ERROR_DETECTED */
1280  volatile uint32_t IPC_STATUS_INDICATION : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_IPC_STATUS_INDICATION */
1281  uint32_t : 27; /* *UNDEFINED* */
1282 };
1283 
1284 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR. */
1285 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_t;
1286 #endif /* __ASSEMBLY__ */
1287 
1288 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR register. */
1289 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_RESET 0x00000000
1290 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR register from the beginning of the component. */
1291 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_OFST 0x110
1292 
1293 /*
1294  * Register : LLI_Targ_Svc_LLI_Ctrl_TL_Address_Mode
1295  *
1296  * Register Layout
1297  *
1298  * Bits | Access | Reset | Description
1299  * :-------|:-------|:--------|:-----------------------------------------------------------------------
1300  * [0] | RW | 0x1 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE
1301  * [31:1] | ??? | Unknown | *UNDEFINED*
1302  *
1303  */
1304 /*
1305  * Field : TL_ADDRESS_MODE
1306  *
1307  * When set to 1, extend the address to 40 bits.
1308  *
1309  * Field Access Macros:
1310  *
1311  */
1312 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field. */
1313 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_LSB 0
1314 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field. */
1315 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_MSB 0
1316 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field. */
1317 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_WIDTH 1
1318 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field value. */
1319 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_SET_MSK 0x00000001
1320 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field value. */
1321 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_CLR_MSK 0xfffffffe
1322 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field. */
1323 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_RESET 0x1
1324 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE field value from a register. */
1325 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_GET(value) (((value) & 0x00000001) >> 0)
1326 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE register field value suitable for setting the register. */
1327 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE_SET(value) (((value) << 0) & 0x00000001)
1328 
1329 #ifndef __ASSEMBLY__
1330 /*
1331  * WARNING: The C register and register group struct declarations are provided for
1332  * convenience and illustrative purposes. They should, however, be used with
1333  * caution as the C language standard provides no guarantees about the alignment or
1334  * atomicity of device memory accesses. The recommended practice for writing
1335  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1336  * alt_write_word() functions.
1337  *
1338  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE.
1339  */
1340 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_s
1341 {
1342  volatile uint32_t TL_ADDRESS_MODE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_TL_ADDRESS_MODE */
1343  uint32_t : 31; /* *UNDEFINED* */
1344 };
1345 
1346 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE. */
1347 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_t;
1348 #endif /* __ASSEMBLY__ */
1349 
1350 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE register. */
1351 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_RESET 0x00000001
1352 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE register from the beginning of the component. */
1353 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_OFST 0x114
1354 
1355 /*
1356  * Register : LLI_Targ_Svc_LLI_Ctrl_LL_PHIT36_enable
1357  *
1358  * Register Layout
1359  *
1360  * Bits | Access | Reset | Description
1361  * :-------|:-------|:--------|:-------------------------------------------------------------------------
1362  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE
1363  * [31:1] | ??? | Unknown | *UNDEFINED*
1364  *
1365  */
1366 /*
1367  * Field : LL_PHIT36_ENABLE
1368  *
1369  * When set to 1, the LLI IP is allowed to generate PHIT-36 from LL TC traffic.
1370  *
1371  * Field Access Macros:
1372  *
1373  */
1374 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field. */
1375 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_LSB 0
1376 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field. */
1377 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_MSB 0
1378 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field. */
1379 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_WIDTH 1
1380 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field value. */
1381 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_SET_MSK 0x00000001
1382 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field value. */
1383 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_CLR_MSK 0xfffffffe
1384 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field. */
1385 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_RESET 0x0
1386 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE field value from a register. */
1387 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
1388 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE register field value suitable for setting the register. */
1389 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE_SET(value) (((value) << 0) & 0x00000001)
1390 
1391 #ifndef __ASSEMBLY__
1392 /*
1393  * WARNING: The C register and register group struct declarations are provided for
1394  * convenience and illustrative purposes. They should, however, be used with
1395  * caution as the C language standard provides no guarantees about the alignment or
1396  * atomicity of device memory accesses. The recommended practice for writing
1397  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1398  * alt_write_word() functions.
1399  *
1400  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE.
1401  */
1402 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_s
1403 {
1404  volatile uint32_t LL_PHIT36_ENABLE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_LL_PHIT36_ENABLE */
1405  uint32_t : 31; /* *UNDEFINED* */
1406 };
1407 
1408 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE. */
1409 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_t;
1410 #endif /* __ASSEMBLY__ */
1411 
1412 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE register. */
1413 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_RESET 0x00000000
1414 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE register from the beginning of the component. */
1415 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_OFST 0x118
1416 
1417 /*
1418  * Register : LLI_Targ_Svc_LLI_Ctrl_BE_PHIT36_enable
1419  *
1420  * Register Layout
1421  *
1422  * Bits | Access | Reset | Description
1423  * :-------|:-------|:--------|:-------------------------------------------------------------------------
1424  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE
1425  * [31:1] | ??? | Unknown | *UNDEFINED*
1426  *
1427  */
1428 /*
1429  * Field : BE_PHIT36_ENABLE
1430  *
1431  * When set to 1, the LLI IP is allowed to generate PHIT-36 from BE TC traffic.
1432  *
1433  * Field Access Macros:
1434  *
1435  */
1436 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field. */
1437 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_LSB 0
1438 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field. */
1439 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_MSB 0
1440 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field. */
1441 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_WIDTH 1
1442 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field value. */
1443 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_SET_MSK 0x00000001
1444 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field value. */
1445 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_CLR_MSK 0xfffffffe
1446 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field. */
1447 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_RESET 0x0
1448 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE field value from a register. */
1449 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
1450 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE register field value suitable for setting the register. */
1451 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE_SET(value) (((value) << 0) & 0x00000001)
1452 
1453 #ifndef __ASSEMBLY__
1454 /*
1455  * WARNING: The C register and register group struct declarations are provided for
1456  * convenience and illustrative purposes. They should, however, be used with
1457  * caution as the C language standard provides no guarantees about the alignment or
1458  * atomicity of device memory accesses. The recommended practice for writing
1459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1460  * alt_write_word() functions.
1461  *
1462  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE.
1463  */
1464 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_s
1465 {
1466  volatile uint32_t BE_PHIT36_ENABLE : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_BE_PHIT36_ENABLE */
1467  uint32_t : 31; /* *UNDEFINED* */
1468 };
1469 
1470 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE. */
1471 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_t;
1472 #endif /* __ASSEMBLY__ */
1473 
1474 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE register. */
1475 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_RESET 0x00000000
1476 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE register from the beginning of the component. */
1477 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_OFST 0x11c
1478 
1479 /*
1480  * Register : LLI_Targ_Svc_LLI_Ctrl_WakeUp_Latency_Bound
1481  *
1482  * Attribute for communicating the Wakeup latency bound.
1483  *
1484  * Register Layout
1485  *
1486  * Bits | Access | Reset | Description
1487  * :--------|:-------|:--------|:-----------------------------------------------------------------------------------------
1488  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND
1489  * [2:1] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE
1490  * [7:3] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED
1491  * [15:8] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE
1492  * [16] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES
1493  * [17] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP
1494  * [18] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP
1495  * [19] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP
1496  * [31:20] | ??? | Unknown | *UNDEFINED*
1497  *
1498  */
1499 /*
1500  * Field : ACTIVATE_WAKEUP_BOUND
1501  *
1502  * Activates the bits [15:1] in the Wake up bound constraint attribute.
1503  *
1504  * Field Access Macros:
1505  *
1506  */
1507 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field. */
1508 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_LSB 0
1509 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field. */
1510 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_MSB 0
1511 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field. */
1512 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_WIDTH 1
1513 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field value. */
1514 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_SET_MSK 0x00000001
1515 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field value. */
1516 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_CLR_MSK 0xfffffffe
1517 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field. */
1518 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_RESET 0x0
1519 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND field value from a register. */
1520 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_GET(value) (((value) & 0x00000001) >> 0)
1521 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND register field value suitable for setting the register. */
1522 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND_SET(value) (((value) << 0) & 0x00000001)
1523 
1524 /*
1525  * Field : WAKE_UP_BOUND_VALUE
1526  *
1527  * Wake up bound Value.
1528  *
1529  * Field Access Macros:
1530  *
1531  */
1532 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field. */
1533 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_LSB 1
1534 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field. */
1535 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_MSB 2
1536 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field. */
1537 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_WIDTH 2
1538 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field value. */
1539 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_SET_MSK 0x00000006
1540 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field value. */
1541 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_CLR_MSK 0xfffffff9
1542 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field. */
1543 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_RESET 0x0
1544 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE field value from a register. */
1545 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_GET(value) (((value) & 0x00000006) >> 1)
1546 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE register field value suitable for setting the register. */
1547 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE_SET(value) (((value) << 1) & 0x00000006)
1548 
1549 /*
1550  * Field : RESERVED
1551  *
1552  * Reserved.
1553  *
1554  * Field Access Macros:
1555  *
1556  */
1557 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field. */
1558 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_LSB 3
1559 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field. */
1560 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_MSB 7
1561 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field. */
1562 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_WIDTH 5
1563 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field value. */
1564 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_SET_MSK 0x000000f8
1565 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field value. */
1566 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_CLR_MSK 0xffffff07
1567 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field. */
1568 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_RESET 0x0
1569 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED field value from a register. */
1570 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_GET(value) (((value) & 0x000000f8) >> 3)
1571 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED register field value suitable for setting the register. */
1572 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED_SET(value) (((value) << 3) & 0x000000f8)
1573 
1574 /*
1575  * Field : PROPRIETARY_WAKE_UP_VALUE
1576  *
1577  * Proprietary Wake up value.
1578  *
1579  * Field Access Macros:
1580  *
1581  */
1582 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field. */
1583 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_LSB 8
1584 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field. */
1585 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_MSB 15
1586 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field. */
1587 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_WIDTH 8
1588 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field value. */
1589 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_SET_MSK 0x0000ff00
1590 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field value. */
1591 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_CLR_MSK 0xffff00ff
1592 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field. */
1593 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_RESET 0x0
1594 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE field value from a register. */
1595 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_GET(value) (((value) & 0x0000ff00) >> 8)
1596 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE register field value suitable for setting the register. */
1597 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE_SET(value) (((value) << 8) & 0x0000ff00)
1598 
1599 /*
1600  * Field : ACTIVATE_RESOURCES
1601  *
1602  * Activates the bits [19:17] in the Wake up bound constraint attribute.
1603  *
1604  * Field Access Macros:
1605  *
1606  */
1607 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field. */
1608 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_LSB 16
1609 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field. */
1610 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_MSB 16
1611 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field. */
1612 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_WIDTH 1
1613 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field value. */
1614 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_SET_MSK 0x00010000
1615 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field value. */
1616 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_CLR_MSK 0xfffeffff
1617 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field. */
1618 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_RESET 0x0
1619 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES field value from a register. */
1620 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_GET(value) (((value) & 0x00010000) >> 16)
1621 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES register field value suitable for setting the register. */
1622 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES_SET(value) (((value) << 16) & 0x00010000)
1623 
1624 /*
1625  * Field : LL_PATH_WAKE_UP
1626  *
1627  * Wake up LL path.
1628  *
1629  * Field Access Macros:
1630  *
1631  */
1632 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field. */
1633 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_LSB 17
1634 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field. */
1635 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_MSB 17
1636 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field. */
1637 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_WIDTH 1
1638 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field value. */
1639 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_SET_MSK 0x00020000
1640 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field value. */
1641 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_CLR_MSK 0xfffdffff
1642 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field. */
1643 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_RESET 0x0
1644 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP field value from a register. */
1645 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_GET(value) (((value) & 0x00020000) >> 17)
1646 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP register field value suitable for setting the register. */
1647 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP_SET(value) (((value) << 17) & 0x00020000)
1648 
1649 /*
1650  * Field : BE_PATH_WAKE_UP
1651  *
1652  * Wake up BE path.
1653  *
1654  * Field Access Macros:
1655  *
1656  */
1657 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field. */
1658 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_LSB 18
1659 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field. */
1660 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_MSB 18
1661 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field. */
1662 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_WIDTH 1
1663 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field value. */
1664 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_SET_MSK 0x00040000
1665 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field value. */
1666 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_CLR_MSK 0xfffbffff
1667 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field. */
1668 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_RESET 0x0
1669 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP field value from a register. */
1670 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_GET(value) (((value) & 0x00040000) >> 18)
1671 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP register field value suitable for setting the register. */
1672 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP_SET(value) (((value) << 18) & 0x00040000)
1673 
1674 /*
1675  * Field : INTERCONNECT_AND_MPU_WAKE_UP
1676  *
1677  * Wake up Interconnect and MPU.
1678  *
1679  * Field Access Macros:
1680  *
1681  */
1682 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field. */
1683 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_LSB 19
1684 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field. */
1685 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_MSB 19
1686 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field. */
1687 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_WIDTH 1
1688 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field value. */
1689 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_SET_MSK 0x00080000
1690 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field value. */
1691 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_CLR_MSK 0xfff7ffff
1692 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field. */
1693 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_RESET 0x0
1694 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP field value from a register. */
1695 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_GET(value) (((value) & 0x00080000) >> 19)
1696 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP register field value suitable for setting the register. */
1697 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP_SET(value) (((value) << 19) & 0x00080000)
1698 
1699 #ifndef __ASSEMBLY__
1700 /*
1701  * WARNING: The C register and register group struct declarations are provided for
1702  * convenience and illustrative purposes. They should, however, be used with
1703  * caution as the C language standard provides no guarantees about the alignment or
1704  * atomicity of device memory accesses. The recommended practice for writing
1705  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1706  * alt_write_word() functions.
1707  *
1708  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND.
1709  */
1710 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_s
1711 {
1712  volatile uint32_t ACTIVATE_WAKEUP_BOUND : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_WAKEUP_BOUND */
1713  volatile uint32_t WAKE_UP_BOUND_VALUE : 2; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_WAKE_UP_BOUND_VALUE */
1714  const volatile uint32_t RESERVED : 5; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESERVED */
1715  volatile uint32_t PROPRIETARY_WAKE_UP_VALUE : 8; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_PROPRIETARY_WAKE_UP_VALUE */
1716  volatile uint32_t ACTIVATE_RESOURCES : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_ACTIVATE_RESOURCES */
1717  volatile uint32_t LL_PATH_WAKE_UP : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_LL_PATH_WAKE_UP */
1718  volatile uint32_t BE_PATH_WAKE_UP : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_BE_PATH_WAKE_UP */
1719  volatile uint32_t INTERCONNECT_AND_MPU_WAKE_UP : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_INTERCONNECT_AND_MPU_WAKE_UP */
1720  uint32_t : 12; /* *UNDEFINED* */
1721 };
1722 
1723 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND. */
1724 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_t;
1725 #endif /* __ASSEMBLY__ */
1726 
1727 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND register. */
1728 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_RESET 0x00000000
1729 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND register from the beginning of the component. */
1730 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_OFST 0x120
1731 
1732 /*
1733  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOff
1734  *
1735  * Attribute requesting powering off a Resource.
1736  *
1737  * Register Layout
1738  *
1739  * Bits | Access | Reset | Description
1740  * :--------|:-------|:--------|:----------------------------------------------------------------------------------------
1741  * [15:0] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED
1742  * [16] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES
1743  * [17] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF
1744  * [18] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF
1745  * [19] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF
1746  * [31:20] | ??? | Unknown | *UNDEFINED*
1747  *
1748  */
1749 /*
1750  * Field : RESERVED
1751  *
1752  * Reserved.
1753  *
1754  * Field Access Macros:
1755  *
1756  */
1757 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field. */
1758 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_LSB 0
1759 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field. */
1760 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_MSB 15
1761 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field. */
1762 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_WIDTH 16
1763 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field value. */
1764 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_SET_MSK 0x0000ffff
1765 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field value. */
1766 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_CLR_MSK 0xffff0000
1767 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field. */
1768 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_RESET 0x0
1769 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED field value from a register. */
1770 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_GET(value) (((value) & 0x0000ffff) >> 0)
1771 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED register field value suitable for setting the register. */
1772 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED_SET(value) (((value) << 0) & 0x0000ffff)
1773 
1774 /*
1775  * Field : ACTIVATE_RESOURCES
1776  *
1777  * deactivates the bits [19:17].
1778  *
1779  * Field Access Macros:
1780  *
1781  */
1782 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field. */
1783 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_LSB 16
1784 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field. */
1785 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_MSB 16
1786 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field. */
1787 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_WIDTH 1
1788 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field value. */
1789 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_SET_MSK 0x00010000
1790 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field value. */
1791 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_CLR_MSK 0xfffeffff
1792 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field. */
1793 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_RESET 0x0
1794 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES field value from a register. */
1795 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_GET(value) (((value) & 0x00010000) >> 16)
1796 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES register field value suitable for setting the register. */
1797 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES_SET(value) (((value) << 16) & 0x00010000)
1798 
1799 /*
1800  * Field : LL_PATH_POWER_OFF
1801  *
1802  * Power off LL path.
1803  *
1804  * Field Access Macros:
1805  *
1806  */
1807 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field. */
1808 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_LSB 17
1809 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field. */
1810 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_MSB 17
1811 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field. */
1812 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_WIDTH 1
1813 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field value. */
1814 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_SET_MSK 0x00020000
1815 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field value. */
1816 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_CLR_MSK 0xfffdffff
1817 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field. */
1818 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_RESET 0x0
1819 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF field value from a register. */
1820 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_GET(value) (((value) & 0x00020000) >> 17)
1821 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF register field value suitable for setting the register. */
1822 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF_SET(value) (((value) << 17) & 0x00020000)
1823 
1824 /*
1825  * Field : BE_PATH_POWER_OFF
1826  *
1827  * Power off BE path.
1828  *
1829  * Field Access Macros:
1830  *
1831  */
1832 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field. */
1833 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_LSB 18
1834 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field. */
1835 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_MSB 18
1836 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field. */
1837 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_WIDTH 1
1838 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field value. */
1839 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_SET_MSK 0x00040000
1840 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field value. */
1841 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_CLR_MSK 0xfffbffff
1842 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field. */
1843 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_RESET 0x0
1844 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF field value from a register. */
1845 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_GET(value) (((value) & 0x00040000) >> 18)
1846 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF register field value suitable for setting the register. */
1847 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF_SET(value) (((value) << 18) & 0x00040000)
1848 
1849 /*
1850  * Field : INTERCONNECT_AND_MPU_POWER_OFF
1851  *
1852  * Power off Interconnect and MPU.
1853  *
1854  * Field Access Macros:
1855  *
1856  */
1857 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field. */
1858 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_LSB 19
1859 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field. */
1860 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_MSB 19
1861 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field. */
1862 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_WIDTH 1
1863 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field value. */
1864 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_SET_MSK 0x00080000
1865 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field value. */
1866 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_CLR_MSK 0xfff7ffff
1867 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field. */
1868 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_RESET 0x0
1869 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF field value from a register. */
1870 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_GET(value) (((value) & 0x00080000) >> 19)
1871 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF register field value suitable for setting the register. */
1872 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF_SET(value) (((value) << 19) & 0x00080000)
1873 
1874 #ifndef __ASSEMBLY__
1875 /*
1876  * WARNING: The C register and register group struct declarations are provided for
1877  * convenience and illustrative purposes. They should, however, be used with
1878  * caution as the C language standard provides no guarantees about the alignment or
1879  * atomicity of device memory accesses. The recommended practice for writing
1880  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1881  * alt_write_word() functions.
1882  *
1883  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF.
1884  */
1885 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_s
1886 {
1887  const volatile uint32_t RESERVED : 16; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESERVED */
1888  volatile uint32_t ACTIVATE_RESOURCES : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_ACTIVATE_RESOURCES */
1889  volatile uint32_t LL_PATH_POWER_OFF : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_LL_PATH_POWER_OFF */
1890  volatile uint32_t BE_PATH_POWER_OFF : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_BE_PATH_POWER_OFF */
1891  volatile uint32_t INTERCONNECT_AND_MPU_POWER_OFF : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_INTERCONNECT_AND_MPU_POWER_OFF */
1892  uint32_t : 12; /* *UNDEFINED* */
1893 };
1894 
1895 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF. */
1896 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_t;
1897 #endif /* __ASSEMBLY__ */
1898 
1899 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF register. */
1900 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_RESET 0x00000000
1901 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF register from the beginning of the component. */
1902 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_OFST 0x124
1903 
1904 /*
1905  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn
1906  *
1907  * Attribute requesting powering on a Resource.
1908  *
1909  * Register Layout
1910  *
1911  * Bits | Access | Reset | Description
1912  * :--------|:-------|:--------|:--------------------------------------------------------------------------------------
1913  * [15:0] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED
1914  * [16] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES
1915  * [17] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON
1916  * [18] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON
1917  * [19] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON
1918  * [31:20] | ??? | Unknown | *UNDEFINED*
1919  *
1920  */
1921 /*
1922  * Field : RESERVED
1923  *
1924  * Reserved.
1925  *
1926  * Field Access Macros:
1927  *
1928  */
1929 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field. */
1930 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_LSB 0
1931 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field. */
1932 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_MSB 15
1933 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field. */
1934 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_WIDTH 16
1935 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field value. */
1936 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_SET_MSK 0x0000ffff
1937 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field value. */
1938 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_CLR_MSK 0xffff0000
1939 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field. */
1940 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_RESET 0x0
1941 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED field value from a register. */
1942 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_GET(value) (((value) & 0x0000ffff) >> 0)
1943 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED register field value suitable for setting the register. */
1944 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED_SET(value) (((value) << 0) & 0x0000ffff)
1945 
1946 /*
1947  * Field : ACTIVATE_RESOURCES
1948  *
1949  * activates the bits [19:17].
1950  *
1951  * Field Access Macros:
1952  *
1953  */
1954 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field. */
1955 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_LSB 16
1956 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field. */
1957 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_MSB 16
1958 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field. */
1959 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_WIDTH 1
1960 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field value. */
1961 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_SET_MSK 0x00010000
1962 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field value. */
1963 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_CLR_MSK 0xfffeffff
1964 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field. */
1965 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_RESET 0x0
1966 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES field value from a register. */
1967 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_GET(value) (((value) & 0x00010000) >> 16)
1968 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES register field value suitable for setting the register. */
1969 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES_SET(value) (((value) << 16) & 0x00010000)
1970 
1971 /*
1972  * Field : LL_PATH_POWER_ON
1973  *
1974  * Power on LL path.
1975  *
1976  * Field Access Macros:
1977  *
1978  */
1979 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field. */
1980 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_LSB 17
1981 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field. */
1982 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_MSB 17
1983 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field. */
1984 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_WIDTH 1
1985 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field value. */
1986 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_SET_MSK 0x00020000
1987 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field value. */
1988 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_CLR_MSK 0xfffdffff
1989 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field. */
1990 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_RESET 0x0
1991 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON field value from a register. */
1992 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_GET(value) (((value) & 0x00020000) >> 17)
1993 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON register field value suitable for setting the register. */
1994 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON_SET(value) (((value) << 17) & 0x00020000)
1995 
1996 /*
1997  * Field : BE_PATH_POWER_ON
1998  *
1999  * Power on BE path.
2000  *
2001  * Field Access Macros:
2002  *
2003  */
2004 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field. */
2005 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_LSB 18
2006 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field. */
2007 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_MSB 18
2008 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field. */
2009 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_WIDTH 1
2010 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field value. */
2011 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_SET_MSK 0x00040000
2012 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field value. */
2013 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_CLR_MSK 0xfffbffff
2014 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field. */
2015 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_RESET 0x0
2016 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON field value from a register. */
2017 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_GET(value) (((value) & 0x00040000) >> 18)
2018 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON register field value suitable for setting the register. */
2019 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON_SET(value) (((value) << 18) & 0x00040000)
2020 
2021 /*
2022  * Field : INTERCONNECT_AND_MPU_POWER_ON
2023  *
2024  * Power on Interconnect and MPU.
2025  *
2026  * Field Access Macros:
2027  *
2028  */
2029 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field. */
2030 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_LSB 19
2031 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field. */
2032 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_MSB 19
2033 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field. */
2034 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_WIDTH 1
2035 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field value. */
2036 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_SET_MSK 0x00080000
2037 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field value. */
2038 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_CLR_MSK 0xfff7ffff
2039 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field. */
2040 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_RESET 0x0
2041 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON field value from a register. */
2042 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_GET(value) (((value) & 0x00080000) >> 19)
2043 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON register field value suitable for setting the register. */
2044 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON_SET(value) (((value) << 19) & 0x00080000)
2045 
2046 #ifndef __ASSEMBLY__
2047 /*
2048  * WARNING: The C register and register group struct declarations are provided for
2049  * convenience and illustrative purposes. They should, however, be used with
2050  * caution as the C language standard provides no guarantees about the alignment or
2051  * atomicity of device memory accesses. The recommended practice for writing
2052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2053  * alt_write_word() functions.
2054  *
2055  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON.
2056  */
2057 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_s
2058 {
2059  const volatile uint32_t RESERVED : 16; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESERVED */
2060  volatile uint32_t ACTIVATE_RESOURCES : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACTIVATE_RESOURCES */
2061  volatile uint32_t LL_PATH_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_LL_PATH_POWER_ON */
2062  volatile uint32_t BE_PATH_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_BE_PATH_POWER_ON */
2063  volatile uint32_t INTERCONNECT_AND_MPU_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_INTERCONNECT_AND_MPU_POWER_ON */
2064  uint32_t : 12; /* *UNDEFINED* */
2065 };
2066 
2067 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON. */
2068 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_t;
2069 #endif /* __ASSEMBLY__ */
2070 
2071 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON register. */
2072 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_RESET 0x00000000
2073 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON register from the beginning of the component. */
2074 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_OFST 0x128
2075 
2076 /*
2077  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Status
2078  *
2079  * Attribute for receiving acknowledge for powering on request for a particular
2080  * request.
2081  *
2082  * Register Layout
2083  *
2084  * Bits | Access | Reset | Description
2085  * :-------|:-------|:--------|:-----------------------------------------------------------------------------------------------------
2086  * [0] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK
2087  * [1] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK
2088  * [2] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK
2089  * [31:3] | ??? | Unknown | *UNDEFINED*
2090  *
2091  */
2092 /*
2093  * Field : LL_PATH_POWER_ON_ACK
2094  *
2095  * Status Ack for request to power on LL path on remote chip.
2096  *
2097  * Field Access Macros:
2098  *
2099  */
2100 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field. */
2101 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_LSB 0
2102 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field. */
2103 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_MSB 0
2104 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field. */
2105 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_WIDTH 1
2106 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field value. */
2107 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_SET_MSK 0x00000001
2108 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field value. */
2109 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffe
2110 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field. */
2111 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_RESET 0x0
2112 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK field value from a register. */
2113 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000001) >> 0)
2114 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2115 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK_SET(value) (((value) << 0) & 0x00000001)
2116 
2117 /*
2118  * Field : BE_PATH_POWER_ON_ACK
2119  *
2120  * Status Ack for request to power on BE path on remote chip.
2121  *
2122  * Field Access Macros:
2123  *
2124  */
2125 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field. */
2126 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_LSB 1
2127 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field. */
2128 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_MSB 1
2129 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field. */
2130 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_WIDTH 1
2131 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field value. */
2132 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_SET_MSK 0x00000002
2133 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field value. */
2134 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffd
2135 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field. */
2136 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_RESET 0x0
2137 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK field value from a register. */
2138 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000002) >> 1)
2139 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2140 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK_SET(value) (((value) << 1) & 0x00000002)
2141 
2142 /*
2143  * Field : INTERCONNECT_AND_MPU_POWER_ON_ACK
2144  *
2145  * Status Ack for request to power on Interconnect and MPU on remote chip.
2146  *
2147  * Field Access Macros:
2148  *
2149  */
2150 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2151 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_LSB 2
2152 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2153 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_MSB 2
2154 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2155 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_WIDTH 1
2156 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2157 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET_MSK 0x00000004
2158 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2159 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_CLR_MSK 0xfffffffb
2160 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2161 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_RESET 0x0
2162 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK field value from a register. */
2163 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_GET(value) (((value) & 0x00000004) >> 2)
2164 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value suitable for setting the register. */
2165 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET(value) (((value) << 2) & 0x00000004)
2166 
2167 #ifndef __ASSEMBLY__
2168 /*
2169  * WARNING: The C register and register group struct declarations are provided for
2170  * convenience and illustrative purposes. They should, however, be used with
2171  * caution as the C language standard provides no guarantees about the alignment or
2172  * atomicity of device memory accesses. The recommended practice for writing
2173  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2174  * alt_write_word() functions.
2175  *
2176  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS.
2177  */
2178 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_s
2179 {
2180  const volatile uint32_t LL_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_LL_PATH_POWER_ON_ACK */
2181  const volatile uint32_t BE_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_BE_PATH_POWER_ON_ACK */
2182  const volatile uint32_t INTERCONNECT_AND_MPU_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_INTERCONNECT_AND_MPU_POWER_ON_ACK */
2183  uint32_t : 29; /* *UNDEFINED* */
2184 };
2185 
2186 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS. */
2187 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_t;
2188 #endif /* __ASSEMBLY__ */
2189 
2190 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS register. */
2191 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_RESET 0x00000000
2192 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS register from the beginning of the component. */
2193 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_OFST 0x12c
2194 
2195 /*
2196  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Set
2197  *
2198  * The bit fields of Resource_PowerOn_Ack are set to '1' by setting the desired bit
2199  * field in Resource_PowerOn_Ack_Set to '1'.
2200  *
2201  * Register Layout
2202  *
2203  * Bits | Access | Reset | Description
2204  * :-------|:-------|:--------|:--------------------------------------------------------------------------------------------------
2205  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK
2206  * [1] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK
2207  * [2] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK
2208  * [31:3] | ??? | Unknown | *UNDEFINED*
2209  *
2210  */
2211 /*
2212  * Field : LL_PATH_POWER_ON_ACK
2213  *
2214  * Set Ack for request to power on LL path on remote chip.
2215  *
2216  * Field Access Macros:
2217  *
2218  */
2219 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field. */
2220 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_LSB 0
2221 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field. */
2222 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_MSB 0
2223 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field. */
2224 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_WIDTH 1
2225 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field value. */
2226 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_SET_MSK 0x00000001
2227 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field value. */
2228 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffe
2229 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field. */
2230 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_RESET 0x0
2231 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK field value from a register. */
2232 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000001) >> 0)
2233 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2234 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK_SET(value) (((value) << 0) & 0x00000001)
2235 
2236 /*
2237  * Field : BE_PATH_POWER_ON_ACK
2238  *
2239  * Set Ack for request to power on BE path on remote chip.
2240  *
2241  * Field Access Macros:
2242  *
2243  */
2244 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field. */
2245 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_LSB 1
2246 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field. */
2247 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_MSB 1
2248 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field. */
2249 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_WIDTH 1
2250 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field value. */
2251 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_SET_MSK 0x00000002
2252 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field value. */
2253 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffd
2254 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field. */
2255 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_RESET 0x0
2256 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK field value from a register. */
2257 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000002) >> 1)
2258 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2259 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK_SET(value) (((value) << 1) & 0x00000002)
2260 
2261 /*
2262  * Field : INTERCONNECT_AND_MPU_POWER_ON_ACK
2263  *
2264  * Set Ack for request to power on Interconnect and MPU on remote chip.
2265  *
2266  * Field Access Macros:
2267  *
2268  */
2269 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2270 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_LSB 2
2271 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2272 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_MSB 2
2273 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2274 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_WIDTH 1
2275 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2276 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET_MSK 0x00000004
2277 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2278 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_CLR_MSK 0xfffffffb
2279 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2280 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_RESET 0x0
2281 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK field value from a register. */
2282 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_GET(value) (((value) & 0x00000004) >> 2)
2283 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value suitable for setting the register. */
2284 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET(value) (((value) << 2) & 0x00000004)
2285 
2286 #ifndef __ASSEMBLY__
2287 /*
2288  * WARNING: The C register and register group struct declarations are provided for
2289  * convenience and illustrative purposes. They should, however, be used with
2290  * caution as the C language standard provides no guarantees about the alignment or
2291  * atomicity of device memory accesses. The recommended practice for writing
2292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2293  * alt_write_word() functions.
2294  *
2295  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET.
2296  */
2297 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_s
2298 {
2299  volatile uint32_t LL_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_LL_PATH_POWER_ON_ACK */
2300  volatile uint32_t BE_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_BE_PATH_POWER_ON_ACK */
2301  volatile uint32_t INTERCONNECT_AND_MPU_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_INTERCONNECT_AND_MPU_POWER_ON_ACK */
2302  uint32_t : 29; /* *UNDEFINED* */
2303 };
2304 
2305 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET. */
2306 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_t;
2307 #endif /* __ASSEMBLY__ */
2308 
2309 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET register. */
2310 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_RESET 0x00000000
2311 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET register from the beginning of the component. */
2312 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_OFST 0x130
2313 
2314 /*
2315  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Clear
2316  *
2317  * The bit fields of Resource_PowerOn_Ack are set to '0' by setting the desired bit
2318  * field in Resource_PowerOn_Ack_Clear to '1'.
2319  *
2320  * Register Layout
2321  *
2322  * Bits | Access | Reset | Description
2323  * :-------|:-------|:--------|:----------------------------------------------------------------------------------------------------
2324  * [0] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK
2325  * [1] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK
2326  * [2] | RW | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK
2327  * [31:3] | ??? | Unknown | *UNDEFINED*
2328  *
2329  */
2330 /*
2331  * Field : LL_PATH_POWER_ON_ACK
2332  *
2333  * Clear Ack for request to power on LL path on remote chip.
2334  *
2335  * Field Access Macros:
2336  *
2337  */
2338 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field. */
2339 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_LSB 0
2340 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field. */
2341 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_MSB 0
2342 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field. */
2343 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_WIDTH 1
2344 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field value. */
2345 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_SET_MSK 0x00000001
2346 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field value. */
2347 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffe
2348 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field. */
2349 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_RESET 0x0
2350 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK field value from a register. */
2351 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000001) >> 0)
2352 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2353 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK_SET(value) (((value) << 0) & 0x00000001)
2354 
2355 /*
2356  * Field : BE_PATH_POWER_ON_ACK
2357  *
2358  * Clear Ack for request to power on BE path on remote chip.
2359  *
2360  * Field Access Macros:
2361  *
2362  */
2363 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field. */
2364 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_LSB 1
2365 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field. */
2366 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_MSB 1
2367 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field. */
2368 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_WIDTH 1
2369 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field value. */
2370 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_SET_MSK 0x00000002
2371 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field value. */
2372 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_CLR_MSK 0xfffffffd
2373 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field. */
2374 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_RESET 0x0
2375 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK field value from a register. */
2376 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_GET(value) (((value) & 0x00000002) >> 1)
2377 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK register field value suitable for setting the register. */
2378 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK_SET(value) (((value) << 1) & 0x00000002)
2379 
2380 /*
2381  * Field : INTERCONNECT_AND_MPU_POWER_ON_ACK
2382  *
2383  * Clear Ack for request to power on Interconnect and MPU on remote chip.
2384  *
2385  * Field Access Macros:
2386  *
2387  */
2388 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2389 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_LSB 2
2390 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2391 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_MSB 2
2392 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2393 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_WIDTH 1
2394 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2395 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET_MSK 0x00000004
2396 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value. */
2397 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_CLR_MSK 0xfffffffb
2398 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field. */
2399 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_RESET 0x0
2400 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK field value from a register. */
2401 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_GET(value) (((value) & 0x00000004) >> 2)
2402 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK register field value suitable for setting the register. */
2403 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK_SET(value) (((value) << 2) & 0x00000004)
2404 
2405 #ifndef __ASSEMBLY__
2406 /*
2407  * WARNING: The C register and register group struct declarations are provided for
2408  * convenience and illustrative purposes. They should, however, be used with
2409  * caution as the C language standard provides no guarantees about the alignment or
2410  * atomicity of device memory accesses. The recommended practice for writing
2411  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2412  * alt_write_word() functions.
2413  *
2414  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR.
2415  */
2416 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_s
2417 {
2418  volatile uint32_t LL_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_LL_PATH_POWER_ON_ACK */
2419  volatile uint32_t BE_PATH_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_BE_PATH_POWER_ON_ACK */
2420  volatile uint32_t INTERCONNECT_AND_MPU_POWER_ON_ACK : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_INTERCONNECT_AND_MPU_POWER_ON_ACK */
2421  uint32_t : 29; /* *UNDEFINED* */
2422 };
2423 
2424 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR. */
2425 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_t;
2426 #endif /* __ASSEMBLY__ */
2427 
2428 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR register. */
2429 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_RESET 0x00000000
2430 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR register from the beginning of the component. */
2431 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_OFST 0x134
2432 
2433 /*
2434  * Register : LLI_Targ_Svc_LLI_Ctrl_Resource_PowerStatus
2435  *
2436  * Get the status resulting from a write operation in the Resource_PowerOff and
2437  * Resource_PowerOn attributes.
2438  *
2439  * Register Layout
2440  *
2441  * Bits | Access | Reset | Description
2442  * :--------|:-------|:--------|:------------------------------------------------------------------------------------------
2443  * [15:0] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED
2444  * [16] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES
2445  * [17] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON
2446  * [18] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON
2447  * [19] | R | 0x0 | ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON
2448  * [31:20] | ??? | Unknown | *UNDEFINED*
2449  *
2450  */
2451 /*
2452  * Field : RESERVED
2453  *
2454  * Reserved.
2455  *
2456  * Field Access Macros:
2457  *
2458  */
2459 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field. */
2460 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_LSB 0
2461 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field. */
2462 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_MSB 15
2463 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field. */
2464 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_WIDTH 16
2465 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field value. */
2466 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_SET_MSK 0x0000ffff
2467 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field value. */
2468 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_CLR_MSK 0xffff0000
2469 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field. */
2470 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_RESET 0x0
2471 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED field value from a register. */
2472 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_GET(value) (((value) & 0x0000ffff) >> 0)
2473 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED register field value suitable for setting the register. */
2474 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED_SET(value) (((value) << 0) & 0x0000ffff)
2475 
2476 /*
2477  * Field : ACTIVATE_RESOURCES
2478  *
2479  * Validity of bits [19:17].
2480  *
2481  * Field Access Macros:
2482  *
2483  */
2484 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field. */
2485 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_LSB 16
2486 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field. */
2487 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_MSB 16
2488 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field. */
2489 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_WIDTH 1
2490 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field value. */
2491 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_SET_MSK 0x00010000
2492 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field value. */
2493 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_CLR_MSK 0xfffeffff
2494 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field. */
2495 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_RESET 0x0
2496 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES field value from a register. */
2497 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_GET(value) (((value) & 0x00010000) >> 16)
2498 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES register field value suitable for setting the register. */
2499 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES_SET(value) (((value) << 16) & 0x00010000)
2500 
2501 /*
2502  * Field : LL_PATH_POWER_ON
2503  *
2504  * Power status LL path.
2505  *
2506  * Field Access Macros:
2507  *
2508  */
2509 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field. */
2510 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_LSB 17
2511 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field. */
2512 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_MSB 17
2513 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field. */
2514 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_WIDTH 1
2515 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field value. */
2516 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_SET_MSK 0x00020000
2517 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field value. */
2518 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_CLR_MSK 0xfffdffff
2519 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field. */
2520 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_RESET 0x0
2521 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON field value from a register. */
2522 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_GET(value) (((value) & 0x00020000) >> 17)
2523 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON register field value suitable for setting the register. */
2524 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON_SET(value) (((value) << 17) & 0x00020000)
2525 
2526 /*
2527  * Field : BE_PATH_POWER_ON
2528  *
2529  * Power status BE path.
2530  *
2531  * Field Access Macros:
2532  *
2533  */
2534 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field. */
2535 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_LSB 18
2536 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field. */
2537 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_MSB 18
2538 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field. */
2539 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_WIDTH 1
2540 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field value. */
2541 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_SET_MSK 0x00040000
2542 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field value. */
2543 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_CLR_MSK 0xfffbffff
2544 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field. */
2545 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_RESET 0x0
2546 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON field value from a register. */
2547 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_GET(value) (((value) & 0x00040000) >> 18)
2548 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON register field value suitable for setting the register. */
2549 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON_SET(value) (((value) << 18) & 0x00040000)
2550 
2551 /*
2552  * Field : INTERCONNECT_AND_MPU_POWER_ON
2553  *
2554  * Power status Interconnect and MPU.
2555  *
2556  * Field Access Macros:
2557  *
2558  */
2559 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field. */
2560 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_LSB 19
2561 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field. */
2562 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_MSB 19
2563 /* The width in bits of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field. */
2564 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_WIDTH 1
2565 /* The mask used to set the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field value. */
2566 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_SET_MSK 0x00080000
2567 /* The mask used to clear the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field value. */
2568 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_CLR_MSK 0xfff7ffff
2569 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field. */
2570 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_RESET 0x0
2571 /* Extracts the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON field value from a register. */
2572 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_GET(value) (((value) & 0x00080000) >> 19)
2573 /* Produces a ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON register field value suitable for setting the register. */
2574 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON_SET(value) (((value) << 19) & 0x00080000)
2575 
2576 #ifndef __ASSEMBLY__
2577 /*
2578  * WARNING: The C register and register group struct declarations are provided for
2579  * convenience and illustrative purposes. They should, however, be used with
2580  * caution as the C language standard provides no guarantees about the alignment or
2581  * atomicity of device memory accesses. The recommended practice for writing
2582  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2583  * alt_write_word() functions.
2584  *
2585  * The struct declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS.
2586  */
2587 struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_s
2588 {
2589  const volatile uint32_t RESERVED : 16; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESERVED */
2590  const volatile uint32_t ACTIVATE_RESOURCES : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_ACTIVATE_RESOURCES */
2591  const volatile uint32_t LL_PATH_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_LL_PATH_POWER_ON */
2592  const volatile uint32_t BE_PATH_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_BE_PATH_POWER_ON */
2593  const volatile uint32_t INTERCONNECT_AND_MPU_POWER_ON : 1; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_INTERCONNECT_AND_MPU_POWER_ON */
2594  uint32_t : 12; /* *UNDEFINED* */
2595 };
2596 
2597 /* The typedef declaration for register ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS. */
2598 typedef struct ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_s ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_t;
2599 #endif /* __ASSEMBLY__ */
2600 
2601 /* The reset value of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS register. */
2602 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_RESET 0x00000000
2603 /* The byte offset of the ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS register from the beginning of the component. */
2604 #define ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_OFST 0x138
2605 
2606 #ifndef __ASSEMBLY__
2607 /*
2608  * WARNING: The C register and register group struct declarations are provided for
2609  * convenience and illustrative purposes. They should, however, be used with
2610  * caution as the C language standard provides no guarantees about the alignment or
2611  * atomicity of device memory accesses. The recommended practice for writing
2612  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2613  * alt_write_word() functions.
2614  *
2615  * The struct declaration for register group ALT_PSI_LLI_CTRL.
2616  */
2617 struct ALT_PSI_LLI_CTRL_s
2618 {
2619  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT_t LLI_Targ_Svc_LLI_Ctrl_LL_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT */
2620  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT_t LLI_Targ_Svc_LLI_Ctrl_LL_Target_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT */
2621  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT_t LLI_Targ_Svc_LLI_Ctrl_BE_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT */
2622  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT_t LLI_Targ_Svc_LLI_Ctrl_BE_Target_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT */
2623  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT_t LLI_Targ_Svc_LLI_Ctrl_SVC_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT */
2624  volatile uint32_t _pad_0x14_0xff[59]; /* *UNDEFINED* */
2625  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE_t LLI_Targ_Svc_LLI_Ctrl_LL_TC_disable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE */
2626  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE_t LLI_Targ_Svc_LLI_Ctrl_BE_TC_disable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE */
2627  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Status; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS */
2628  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Set; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET */
2629  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Clear; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR */
2630  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE_t LLI_Targ_Svc_LLI_Ctrl_TL_Address_Mode; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE */
2631  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE_t LLI_Targ_Svc_LLI_Ctrl_LL_PHIT36_enable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE */
2632  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE_t LLI_Targ_Svc_LLI_Ctrl_BE_PHIT36_enable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE */
2633  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND_t LLI_Targ_Svc_LLI_Ctrl_WakeUp_Latency_Bound; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND */
2634  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOff; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF */
2635  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON */
2636  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Status; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS */
2637  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Set; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET */
2638  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Clear; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR */
2639  volatile ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerStatus; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS */
2640  volatile uint32_t _pad_0x13c_0x800[433]; /* *UNDEFINED* */
2641 };
2642 
2643 /* The typedef declaration for register group ALT_PSI_LLI_CTRL. */
2644 typedef struct ALT_PSI_LLI_CTRL_s ALT_PSI_LLI_CTRL_t;
2645 /* The struct declaration for the raw register contents of register group ALT_PSI_LLI_CTRL. */
2646 struct ALT_PSI_LLI_CTRL_raw_s
2647 {
2648  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_LL_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_INITIATOR_SOCKET_PRESENT */
2649  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_LL_Target_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TARGET_SOCKET_PRESENT */
2650  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_BE_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_INITIATOR_SOCKET_PRESENT */
2651  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_BE_Target_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TARGET_SOCKET_PRESENT */
2652  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_SVC_Initiator_socket_present; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_SVC_INITIATOR_SOCKET_PRESENT */
2653  volatile uint32_t _pad_0x14_0xff[59]; /* *UNDEFINED* */
2654  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_LL_TC_disable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_TC_DISABLE */
2655  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_BE_TC_disable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_TC_DISABLE */
2656  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Status; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_STATUS */
2657  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Set; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_SET */
2658  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_CSA_System_Clear; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_CSA_SYSTEM_CLEAR */
2659  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_TL_Address_Mode; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_TL_ADDRESS_MODE */
2660  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_LL_PHIT36_enable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_LL_PHIT36_ENABLE */
2661  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_BE_PHIT36_enable; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_BE_PHIT36_ENABLE */
2662  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_WakeUp_Latency_Bound; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_WAKEUP_LATENCY_BOUND */
2663  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOff; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWEROFF */
2664  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON */
2665  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Status; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_STATUS */
2666  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Set; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_SET */
2667  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerOn_Ack_Clear; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERON_ACK_CLEAR */
2668  volatile uint32_t LLI_Targ_Svc_LLI_Ctrl_Resource_PowerStatus; /* ALT_PSI_LLI_CTRL_LLI_TARG_SVC_LLI_CTRL_RESOURCE_POWERSTATUS */
2669  volatile uint32_t _pad_0x13c_0x800[433]; /* *UNDEFINED* */
2670 };
2671 
2672 /* The typedef declaration for the raw register contents of register group ALT_PSI_LLI_CTRL. */
2673 typedef struct ALT_PSI_LLI_CTRL_raw_s ALT_PSI_LLI_CTRL_raw_t;
2674 #endif /* __ASSEMBLY__ */
2675 
2676 
2677 /*
2678  * Component : PSI_LLI_USER
2679  *
2680  */
2681 /*
2682  * Register : LLI_Targ_Svc_LLI_User_ArbiterMode
2683  *
2684  * Register Layout
2685  *
2686  * Bits | Access | Reset | Description
2687  * :-------|:-------|:--------|:---------------------------------------------------------------
2688  * [1:0] | RW | 0x1 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE
2689  * [31:2] | ??? | Unknown | *UNDEFINED*
2690  *
2691  */
2692 /*
2693  * Field : ARBITERMODE
2694  *
2695  * This 2 bits register indicates the sub-priority between channels 0 (Low Latency
2696  * requests) and 1 (Low Latency responses). This value must be constant when LLI is
2697  * mounted. Values are: 0 = Fixed priority for channel 0; 1 = Fixed priority for
2698  * channel 1; 2 and 3: Rotating priority.
2699  *
2700  * Field Access Macros:
2701  *
2702  */
2703 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field. */
2704 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_LSB 0
2705 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field. */
2706 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_MSB 1
2707 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field. */
2708 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_WIDTH 2
2709 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field value. */
2710 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_SET_MSK 0x00000003
2711 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field value. */
2712 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_CLR_MSK 0xfffffffc
2713 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field. */
2714 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_RESET 0x1
2715 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE field value from a register. */
2716 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_GET(value) (((value) & 0x00000003) >> 0)
2717 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE register field value suitable for setting the register. */
2718 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE_SET(value) (((value) << 0) & 0x00000003)
2719 
2720 #ifndef __ASSEMBLY__
2721 /*
2722  * WARNING: The C register and register group struct declarations are provided for
2723  * convenience and illustrative purposes. They should, however, be used with
2724  * caution as the C language standard provides no guarantees about the alignment or
2725  * atomicity of device memory accesses. The recommended practice for writing
2726  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2727  * alt_write_word() functions.
2728  *
2729  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE.
2730  */
2731 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_s
2732 {
2733  volatile uint32_t ARBITERMODE : 2; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_ARBITERMODE */
2734  uint32_t : 30; /* *UNDEFINED* */
2735 };
2736 
2737 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE. */
2738 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_t;
2739 #endif /* __ASSEMBLY__ */
2740 
2741 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE register. */
2742 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_RESET 0x00000001
2743 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE register from the beginning of the component. */
2744 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_OFST 0x0
2745 
2746 /*
2747  * Register : LLI_Targ_Svc_LLI_User_CreditDelay
2748  *
2749  * Register Layout
2750  *
2751  * Bits | Access | Reset | Description
2752  * :-------|:-------|:--------|:---------------------------------------------------------------
2753  * [7:0] | RW | 0x0 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY
2754  * [31:8] | ??? | Unknown | *UNDEFINED*
2755  *
2756  */
2757 /*
2758  * Field : CREDITDELAY
2759  *
2760  * This 8 bits register sets the number of inactivity cycles before a low priority
2761  * Credit Frame may be sent.
2762  *
2763  * Field Access Macros:
2764  *
2765  */
2766 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field. */
2767 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_LSB 0
2768 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field. */
2769 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_MSB 7
2770 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field. */
2771 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_WIDTH 8
2772 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field value. */
2773 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_SET_MSK 0x000000ff
2774 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field value. */
2775 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_CLR_MSK 0xffffff00
2776 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field. */
2777 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_RESET 0x0
2778 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY field value from a register. */
2779 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_GET(value) (((value) & 0x000000ff) >> 0)
2780 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY register field value suitable for setting the register. */
2781 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY_SET(value) (((value) << 0) & 0x000000ff)
2782 
2783 #ifndef __ASSEMBLY__
2784 /*
2785  * WARNING: The C register and register group struct declarations are provided for
2786  * convenience and illustrative purposes. They should, however, be used with
2787  * caution as the C language standard provides no guarantees about the alignment or
2788  * atomicity of device memory accesses. The recommended practice for writing
2789  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2790  * alt_write_word() functions.
2791  *
2792  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY.
2793  */
2794 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_s
2795 {
2796  volatile uint32_t CREDITDELAY : 8; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_CREDITDELAY */
2797  uint32_t : 24; /* *UNDEFINED* */
2798 };
2799 
2800 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY. */
2801 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_t;
2802 #endif /* __ASSEMBLY__ */
2803 
2804 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY register. */
2805 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_RESET 0x00000000
2806 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY register from the beginning of the component. */
2807 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_OFST 0x4
2808 
2809 /*
2810  * Register : LLI_Targ_Svc_LLI_User_MaskSystemIrq
2811  *
2812  * Register Layout
2813  *
2814  * Bits | Access | Reset | Description
2815  * :-------|:-------|:--------|:-------------------------------------------------------------------
2816  * [0] | RW | 0x0 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ
2817  * [31:1] | ??? | Unknown | *UNDEFINED*
2818  *
2819  */
2820 /*
2821  * Field : MASKSYSTEMIRQ
2822  *
2823  * Mask vector for LLI DL and TL interrupts on output signal SystemIrqLevel.
2824  *
2825  * Field Access Macros:
2826  *
2827  */
2828 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field. */
2829 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_LSB 0
2830 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field. */
2831 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_MSB 0
2832 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field. */
2833 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_WIDTH 1
2834 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field value. */
2835 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_SET_MSK 0x00000001
2836 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field value. */
2837 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_CLR_MSK 0xfffffffe
2838 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field. */
2839 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_RESET 0x0
2840 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ field value from a register. */
2841 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_GET(value) (((value) & 0x00000001) >> 0)
2842 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ register field value suitable for setting the register. */
2843 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ_SET(value) (((value) << 0) & 0x00000001)
2844 
2845 #ifndef __ASSEMBLY__
2846 /*
2847  * WARNING: The C register and register group struct declarations are provided for
2848  * convenience and illustrative purposes. They should, however, be used with
2849  * caution as the C language standard provides no guarantees about the alignment or
2850  * atomicity of device memory accesses. The recommended practice for writing
2851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2852  * alt_write_word() functions.
2853  *
2854  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ.
2855  */
2856 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_s
2857 {
2858  volatile uint32_t MASKSYSTEMIRQ : 1; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_MASKSYSTEMIRQ */
2859  uint32_t : 31; /* *UNDEFINED* */
2860 };
2861 
2862 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ. */
2863 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_t;
2864 #endif /* __ASSEMBLY__ */
2865 
2866 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ register. */
2867 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_RESET 0x00000000
2868 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ register from the beginning of the component. */
2869 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_OFST 0x8
2870 
2871 /*
2872  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser0
2873  *
2874  * Register Layout
2875  *
2876  * Bits | Access | Reset | Description
2877  * :-------|:-------|:--------|:-------------------------------------------------------------------
2878  * [5:0] | RW | 0x3e | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0
2879  * [31:6] | ??? | Unknown | *UNDEFINED*
2880  *
2881  */
2882 /*
2883  * Field : DATALINKUSER0
2884  *
2885  * This 6 bits register sets the slave interfaces source of the LLI User bit 0.
2886  * When the selected source bit is not implemented or the register value is not
2887  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
2888  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
2889  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
2890  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
2891  *
2892  * 0x3F LLI.User[r] <<= 1.
2893  *
2894  * Field Access Macros:
2895  *
2896  */
2897 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field. */
2898 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_LSB 0
2899 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field. */
2900 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_MSB 5
2901 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field. */
2902 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_WIDTH 6
2903 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field value. */
2904 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_SET_MSK 0x0000003f
2905 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field value. */
2906 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_CLR_MSK 0xffffffc0
2907 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field. */
2908 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_RESET 0x3e
2909 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 field value from a register. */
2910 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_GET(value) (((value) & 0x0000003f) >> 0)
2911 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 register field value suitable for setting the register. */
2912 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0_SET(value) (((value) << 0) & 0x0000003f)
2913 
2914 #ifndef __ASSEMBLY__
2915 /*
2916  * WARNING: The C register and register group struct declarations are provided for
2917  * convenience and illustrative purposes. They should, however, be used with
2918  * caution as the C language standard provides no guarantees about the alignment or
2919  * atomicity of device memory accesses. The recommended practice for writing
2920  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2921  * alt_write_word() functions.
2922  *
2923  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0.
2924  */
2925 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_s
2926 {
2927  volatile uint32_t DATALINKUSER0 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_DATALINKUSER0 */
2928  uint32_t : 26; /* *UNDEFINED* */
2929 };
2930 
2931 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0. */
2932 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_t;
2933 #endif /* __ASSEMBLY__ */
2934 
2935 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0 register. */
2936 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_RESET 0x0000003e
2937 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0 register from the beginning of the component. */
2938 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_OFST 0x80
2939 
2940 /*
2941  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser1
2942  *
2943  * Register Layout
2944  *
2945  * Bits | Access | Reset | Description
2946  * :-------|:-------|:--------|:-------------------------------------------------------------------
2947  * [5:0] | RW | 0x3e | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1
2948  * [31:6] | ??? | Unknown | *UNDEFINED*
2949  *
2950  */
2951 /*
2952  * Field : DATALINKUSER1
2953  *
2954  * This 6 bits register sets the slave interfaces source of the LLI User bit 1.
2955  * When the selected source bit is not implemented or the register value is not
2956  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
2957  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
2958  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
2959  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
2960  *
2961  * 0x3F LLI.User[r] <<= 1.
2962  *
2963  * Field Access Macros:
2964  *
2965  */
2966 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field. */
2967 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_LSB 0
2968 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field. */
2969 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_MSB 5
2970 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field. */
2971 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_WIDTH 6
2972 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field value. */
2973 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_SET_MSK 0x0000003f
2974 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field value. */
2975 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_CLR_MSK 0xffffffc0
2976 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field. */
2977 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_RESET 0x3e
2978 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 field value from a register. */
2979 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_GET(value) (((value) & 0x0000003f) >> 0)
2980 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 register field value suitable for setting the register. */
2981 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1_SET(value) (((value) << 0) & 0x0000003f)
2982 
2983 #ifndef __ASSEMBLY__
2984 /*
2985  * WARNING: The C register and register group struct declarations are provided for
2986  * convenience and illustrative purposes. They should, however, be used with
2987  * caution as the C language standard provides no guarantees about the alignment or
2988  * atomicity of device memory accesses. The recommended practice for writing
2989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2990  * alt_write_word() functions.
2991  *
2992  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1.
2993  */
2994 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_s
2995 {
2996  volatile uint32_t DATALINKUSER1 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_DATALINKUSER1 */
2997  uint32_t : 26; /* *UNDEFINED* */
2998 };
2999 
3000 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1. */
3001 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_t;
3002 #endif /* __ASSEMBLY__ */
3003 
3004 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1 register. */
3005 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_RESET 0x0000003e
3006 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1 register from the beginning of the component. */
3007 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_OFST 0x84
3008 
3009 /*
3010  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser2
3011  *
3012  * Register Layout
3013  *
3014  * Bits | Access | Reset | Description
3015  * :-------|:-------|:--------|:-------------------------------------------------------------------
3016  * [5:0] | RW | 0x3e | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2
3017  * [31:6] | ??? | Unknown | *UNDEFINED*
3018  *
3019  */
3020 /*
3021  * Field : DATALINKUSER2
3022  *
3023  * This 6 bits register sets the slave interfaces source of the LLI User bit 2.
3024  * When the selected source bit is not implemented or the register value is not
3025  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3026  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3027  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3028  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3029  *
3030  * 0x3F LLI.User[r] <<= 1.
3031  *
3032  * Field Access Macros:
3033  *
3034  */
3035 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field. */
3036 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_LSB 0
3037 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field. */
3038 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_MSB 5
3039 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field. */
3040 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_WIDTH 6
3041 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field value. */
3042 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_SET_MSK 0x0000003f
3043 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field value. */
3044 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_CLR_MSK 0xffffffc0
3045 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field. */
3046 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_RESET 0x3e
3047 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 field value from a register. */
3048 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_GET(value) (((value) & 0x0000003f) >> 0)
3049 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 register field value suitable for setting the register. */
3050 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2_SET(value) (((value) << 0) & 0x0000003f)
3051 
3052 #ifndef __ASSEMBLY__
3053 /*
3054  * WARNING: The C register and register group struct declarations are provided for
3055  * convenience and illustrative purposes. They should, however, be used with
3056  * caution as the C language standard provides no guarantees about the alignment or
3057  * atomicity of device memory accesses. The recommended practice for writing
3058  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3059  * alt_write_word() functions.
3060  *
3061  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2.
3062  */
3063 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_s
3064 {
3065  volatile uint32_t DATALINKUSER2 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_DATALINKUSER2 */
3066  uint32_t : 26; /* *UNDEFINED* */
3067 };
3068 
3069 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2. */
3070 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_t;
3071 #endif /* __ASSEMBLY__ */
3072 
3073 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2 register. */
3074 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_RESET 0x0000003e
3075 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2 register from the beginning of the component. */
3076 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_OFST 0x88
3077 
3078 /*
3079  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser3
3080  *
3081  * Register Layout
3082  *
3083  * Bits | Access | Reset | Description
3084  * :-------|:-------|:--------|:-------------------------------------------------------------------
3085  * [5:0] | RW | 0x3e | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3
3086  * [31:6] | ??? | Unknown | *UNDEFINED*
3087  *
3088  */
3089 /*
3090  * Field : DATALINKUSER3
3091  *
3092  * This 6 bits register sets the slave interfaces source of the LLI User bit 3.
3093  * When the selected source bit is not implemented or the register value is not
3094  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3095  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3096  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3097  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3098  *
3099  * 0x3F LLI.User[r] <<= 1.
3100  *
3101  * Field Access Macros:
3102  *
3103  */
3104 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field. */
3105 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_LSB 0
3106 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field. */
3107 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_MSB 5
3108 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field. */
3109 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_WIDTH 6
3110 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field value. */
3111 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_SET_MSK 0x0000003f
3112 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field value. */
3113 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_CLR_MSK 0xffffffc0
3114 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field. */
3115 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_RESET 0x3e
3116 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 field value from a register. */
3117 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_GET(value) (((value) & 0x0000003f) >> 0)
3118 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 register field value suitable for setting the register. */
3119 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3_SET(value) (((value) << 0) & 0x0000003f)
3120 
3121 #ifndef __ASSEMBLY__
3122 /*
3123  * WARNING: The C register and register group struct declarations are provided for
3124  * convenience and illustrative purposes. They should, however, be used with
3125  * caution as the C language standard provides no guarantees about the alignment or
3126  * atomicity of device memory accesses. The recommended practice for writing
3127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3128  * alt_write_word() functions.
3129  *
3130  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3.
3131  */
3132 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_s
3133 {
3134  volatile uint32_t DATALINKUSER3 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_DATALINKUSER3 */
3135  uint32_t : 26; /* *UNDEFINED* */
3136 };
3137 
3138 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3. */
3139 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_t;
3140 #endif /* __ASSEMBLY__ */
3141 
3142 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3 register. */
3143 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_RESET 0x0000003e
3144 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3 register from the beginning of the component. */
3145 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_OFST 0x8c
3146 
3147 /*
3148  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser4
3149  *
3150  * Register Layout
3151  *
3152  * Bits | Access | Reset | Description
3153  * :-------|:-------|:--------|:-------------------------------------------------------------------
3154  * [5:0] | RW | 0x0 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4
3155  * [31:6] | ??? | Unknown | *UNDEFINED*
3156  *
3157  */
3158 /*
3159  * Field : DATALINKUSER4
3160  *
3161  * This 6 bits register sets the slave interfaces source of the LLI User bit 4.
3162  * When the selected source bit is not implemented or the register value is not
3163  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3164  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3165  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3166  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3167  *
3168  * 0x3F LLI.User[r] <<= 1.
3169  *
3170  * Field Access Macros:
3171  *
3172  */
3173 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field. */
3174 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_LSB 0
3175 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field. */
3176 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_MSB 5
3177 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field. */
3178 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_WIDTH 6
3179 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field value. */
3180 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_SET_MSK 0x0000003f
3181 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field value. */
3182 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_CLR_MSK 0xffffffc0
3183 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field. */
3184 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_RESET 0x0
3185 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 field value from a register. */
3186 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_GET(value) (((value) & 0x0000003f) >> 0)
3187 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 register field value suitable for setting the register. */
3188 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4_SET(value) (((value) << 0) & 0x0000003f)
3189 
3190 #ifndef __ASSEMBLY__
3191 /*
3192  * WARNING: The C register and register group struct declarations are provided for
3193  * convenience and illustrative purposes. They should, however, be used with
3194  * caution as the C language standard provides no guarantees about the alignment or
3195  * atomicity of device memory accesses. The recommended practice for writing
3196  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3197  * alt_write_word() functions.
3198  *
3199  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4.
3200  */
3201 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_s
3202 {
3203  volatile uint32_t DATALINKUSER4 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_DATALINKUSER4 */
3204  uint32_t : 26; /* *UNDEFINED* */
3205 };
3206 
3207 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4. */
3208 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_t;
3209 #endif /* __ASSEMBLY__ */
3210 
3211 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4 register. */
3212 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_RESET 0x00000000
3213 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4 register from the beginning of the component. */
3214 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_OFST 0x90
3215 
3216 /*
3217  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser5
3218  *
3219  * Register Layout
3220  *
3221  * Bits | Access | Reset | Description
3222  * :-------|:-------|:--------|:-------------------------------------------------------------------
3223  * [5:0] | RW | 0x1 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5
3224  * [31:6] | ??? | Unknown | *UNDEFINED*
3225  *
3226  */
3227 /*
3228  * Field : DATALINKUSER5
3229  *
3230  * This 6 bits register sets the slave interfaces source of the LLI User bit 5.
3231  * When the selected source bit is not implemented or the register value is not
3232  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3233  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3234  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3235  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3236  *
3237  * 0x3F LLI.User[r] <<= 1.
3238  *
3239  * Field Access Macros:
3240  *
3241  */
3242 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field. */
3243 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_LSB 0
3244 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field. */
3245 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_MSB 5
3246 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field. */
3247 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_WIDTH 6
3248 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field value. */
3249 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_SET_MSK 0x0000003f
3250 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field value. */
3251 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_CLR_MSK 0xffffffc0
3252 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field. */
3253 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_RESET 0x1
3254 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 field value from a register. */
3255 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_GET(value) (((value) & 0x0000003f) >> 0)
3256 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 register field value suitable for setting the register. */
3257 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5_SET(value) (((value) << 0) & 0x0000003f)
3258 
3259 #ifndef __ASSEMBLY__
3260 /*
3261  * WARNING: The C register and register group struct declarations are provided for
3262  * convenience and illustrative purposes. They should, however, be used with
3263  * caution as the C language standard provides no guarantees about the alignment or
3264  * atomicity of device memory accesses. The recommended practice for writing
3265  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3266  * alt_write_word() functions.
3267  *
3268  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5.
3269  */
3270 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_s
3271 {
3272  volatile uint32_t DATALINKUSER5 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_DATALINKUSER5 */
3273  uint32_t : 26; /* *UNDEFINED* */
3274 };
3275 
3276 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5. */
3277 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_t;
3278 #endif /* __ASSEMBLY__ */
3279 
3280 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5 register. */
3281 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_RESET 0x00000001
3282 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5 register from the beginning of the component. */
3283 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_OFST 0x94
3284 
3285 /*
3286  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser6
3287  *
3288  * Register Layout
3289  *
3290  * Bits | Access | Reset | Description
3291  * :-------|:-------|:--------|:-------------------------------------------------------------------
3292  * [5:0] | RW | 0x2 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6
3293  * [31:6] | ??? | Unknown | *UNDEFINED*
3294  *
3295  */
3296 /*
3297  * Field : DATALINKUSER6
3298  *
3299  * This 6 bits register sets the slave interfaces source of the LLI User bit 6.
3300  * When the selected source bit is not implemented or the register value is not
3301  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3302  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3303  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3304  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3305  *
3306  * 0x3F LLI.User[r] <<= 1.
3307  *
3308  * Field Access Macros:
3309  *
3310  */
3311 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field. */
3312 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_LSB 0
3313 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field. */
3314 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_MSB 5
3315 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field. */
3316 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_WIDTH 6
3317 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field value. */
3318 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_SET_MSK 0x0000003f
3319 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field value. */
3320 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_CLR_MSK 0xffffffc0
3321 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field. */
3322 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_RESET 0x2
3323 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 field value from a register. */
3324 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_GET(value) (((value) & 0x0000003f) >> 0)
3325 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 register field value suitable for setting the register. */
3326 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6_SET(value) (((value) << 0) & 0x0000003f)
3327 
3328 #ifndef __ASSEMBLY__
3329 /*
3330  * WARNING: The C register and register group struct declarations are provided for
3331  * convenience and illustrative purposes. They should, however, be used with
3332  * caution as the C language standard provides no guarantees about the alignment or
3333  * atomicity of device memory accesses. The recommended practice for writing
3334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3335  * alt_write_word() functions.
3336  *
3337  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6.
3338  */
3339 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_s
3340 {
3341  volatile uint32_t DATALINKUSER6 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_DATALINKUSER6 */
3342  uint32_t : 26; /* *UNDEFINED* */
3343 };
3344 
3345 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6. */
3346 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_t;
3347 #endif /* __ASSEMBLY__ */
3348 
3349 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6 register. */
3350 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_RESET 0x00000002
3351 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6 register from the beginning of the component. */
3352 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_OFST 0x98
3353 
3354 /*
3355  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser7
3356  *
3357  * Register Layout
3358  *
3359  * Bits | Access | Reset | Description
3360  * :-------|:-------|:--------|:-------------------------------------------------------------------
3361  * [5:0] | RW | 0x3 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7
3362  * [31:6] | ??? | Unknown | *UNDEFINED*
3363  *
3364  */
3365 /*
3366  * Field : DATALINKUSER7
3367  *
3368  * This 6 bits register sets the slave interfaces source of the LLI User bit 7.
3369  * When the selected source bit is not implemented or the register value is not
3370  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3371  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3372  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3373  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3374  *
3375  * 0x3F LLI.User[r] <<= 1.
3376  *
3377  * Field Access Macros:
3378  *
3379  */
3380 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field. */
3381 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_LSB 0
3382 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field. */
3383 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_MSB 5
3384 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field. */
3385 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_WIDTH 6
3386 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field value. */
3387 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_SET_MSK 0x0000003f
3388 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field value. */
3389 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_CLR_MSK 0xffffffc0
3390 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field. */
3391 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_RESET 0x3
3392 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 field value from a register. */
3393 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_GET(value) (((value) & 0x0000003f) >> 0)
3394 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 register field value suitable for setting the register. */
3395 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7_SET(value) (((value) << 0) & 0x0000003f)
3396 
3397 #ifndef __ASSEMBLY__
3398 /*
3399  * WARNING: The C register and register group struct declarations are provided for
3400  * convenience and illustrative purposes. They should, however, be used with
3401  * caution as the C language standard provides no guarantees about the alignment or
3402  * atomicity of device memory accesses. The recommended practice for writing
3403  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3404  * alt_write_word() functions.
3405  *
3406  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7.
3407  */
3408 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_s
3409 {
3410  volatile uint32_t DATALINKUSER7 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_DATALINKUSER7 */
3411  uint32_t : 26; /* *UNDEFINED* */
3412 };
3413 
3414 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7. */
3415 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_t;
3416 #endif /* __ASSEMBLY__ */
3417 
3418 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7 register. */
3419 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_RESET 0x00000003
3420 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7 register from the beginning of the component. */
3421 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_OFST 0x9c
3422 
3423 /*
3424  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser8
3425  *
3426  * Register Layout
3427  *
3428  * Bits | Access | Reset | Description
3429  * :-------|:-------|:--------|:-------------------------------------------------------------------
3430  * [5:0] | RW | 0x4 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8
3431  * [31:6] | ??? | Unknown | *UNDEFINED*
3432  *
3433  */
3434 /*
3435  * Field : DATALINKUSER8
3436  *
3437  * This 6 bits register sets the slave interfaces source of the LLI User bit 8.
3438  * When the selected source bit is not implemented or the register value is not
3439  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3440  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3441  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3442  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3443  *
3444  * 0x3F LLI.User[r] <<= 1.
3445  *
3446  * Field Access Macros:
3447  *
3448  */
3449 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field. */
3450 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_LSB 0
3451 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field. */
3452 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_MSB 5
3453 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field. */
3454 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_WIDTH 6
3455 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field value. */
3456 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_SET_MSK 0x0000003f
3457 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field value. */
3458 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_CLR_MSK 0xffffffc0
3459 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field. */
3460 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_RESET 0x4
3461 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 field value from a register. */
3462 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_GET(value) (((value) & 0x0000003f) >> 0)
3463 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 register field value suitable for setting the register. */
3464 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8_SET(value) (((value) << 0) & 0x0000003f)
3465 
3466 #ifndef __ASSEMBLY__
3467 /*
3468  * WARNING: The C register and register group struct declarations are provided for
3469  * convenience and illustrative purposes. They should, however, be used with
3470  * caution as the C language standard provides no guarantees about the alignment or
3471  * atomicity of device memory accesses. The recommended practice for writing
3472  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3473  * alt_write_word() functions.
3474  *
3475  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8.
3476  */
3477 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_s
3478 {
3479  volatile uint32_t DATALINKUSER8 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_DATALINKUSER8 */
3480  uint32_t : 26; /* *UNDEFINED* */
3481 };
3482 
3483 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8. */
3484 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_t;
3485 #endif /* __ASSEMBLY__ */
3486 
3487 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8 register. */
3488 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_RESET 0x00000004
3489 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8 register from the beginning of the component. */
3490 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_OFST 0xa0
3491 
3492 /*
3493  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser9
3494  *
3495  * Register Layout
3496  *
3497  * Bits | Access | Reset | Description
3498  * :-------|:-------|:--------|:-------------------------------------------------------------------
3499  * [5:0] | RW | 0x5 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9
3500  * [31:6] | ??? | Unknown | *UNDEFINED*
3501  *
3502  */
3503 /*
3504  * Field : DATALINKUSER9
3505  *
3506  * This 6 bits register sets the slave interfaces source of the LLI User bit 9.
3507  * When the selected source bit is not implemented or the register value is not
3508  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3509  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3510  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3511  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3512  *
3513  * 0x3F LLI.User[r] <<= 1.
3514  *
3515  * Field Access Macros:
3516  *
3517  */
3518 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field. */
3519 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_LSB 0
3520 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field. */
3521 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_MSB 5
3522 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field. */
3523 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_WIDTH 6
3524 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field value. */
3525 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_SET_MSK 0x0000003f
3526 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field value. */
3527 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_CLR_MSK 0xffffffc0
3528 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field. */
3529 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_RESET 0x5
3530 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 field value from a register. */
3531 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_GET(value) (((value) & 0x0000003f) >> 0)
3532 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 register field value suitable for setting the register. */
3533 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9_SET(value) (((value) << 0) & 0x0000003f)
3534 
3535 #ifndef __ASSEMBLY__
3536 /*
3537  * WARNING: The C register and register group struct declarations are provided for
3538  * convenience and illustrative purposes. They should, however, be used with
3539  * caution as the C language standard provides no guarantees about the alignment or
3540  * atomicity of device memory accesses. The recommended practice for writing
3541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3542  * alt_write_word() functions.
3543  *
3544  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9.
3545  */
3546 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_s
3547 {
3548  volatile uint32_t DATALINKUSER9 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_DATALINKUSER9 */
3549  uint32_t : 26; /* *UNDEFINED* */
3550 };
3551 
3552 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9. */
3553 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_t;
3554 #endif /* __ASSEMBLY__ */
3555 
3556 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9 register. */
3557 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_RESET 0x00000005
3558 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9 register from the beginning of the component. */
3559 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_OFST 0xa4
3560 
3561 /*
3562  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser10
3563  *
3564  * Register Layout
3565  *
3566  * Bits | Access | Reset | Description
3567  * :-------|:-------|:--------|:---------------------------------------------------------------------
3568  * [5:0] | RW | 0x6 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10
3569  * [31:6] | ??? | Unknown | *UNDEFINED*
3570  *
3571  */
3572 /*
3573  * Field : DATALINKUSER10
3574  *
3575  * This 6 bits register sets the slave interfaces source of the LLI User bit 10.
3576  * When the selected source bit is not implemented or the register value is not
3577  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3578  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3579  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3580  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3581  *
3582  * 0x3F LLI.User[r] <<= 1.
3583  *
3584  * Field Access Macros:
3585  *
3586  */
3587 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field. */
3588 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_LSB 0
3589 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field. */
3590 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_MSB 5
3591 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field. */
3592 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_WIDTH 6
3593 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field value. */
3594 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_SET_MSK 0x0000003f
3595 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field value. */
3596 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_CLR_MSK 0xffffffc0
3597 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field. */
3598 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_RESET 0x6
3599 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 field value from a register. */
3600 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_GET(value) (((value) & 0x0000003f) >> 0)
3601 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 register field value suitable for setting the register. */
3602 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10_SET(value) (((value) << 0) & 0x0000003f)
3603 
3604 #ifndef __ASSEMBLY__
3605 /*
3606  * WARNING: The C register and register group struct declarations are provided for
3607  * convenience and illustrative purposes. They should, however, be used with
3608  * caution as the C language standard provides no guarantees about the alignment or
3609  * atomicity of device memory accesses. The recommended practice for writing
3610  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3611  * alt_write_word() functions.
3612  *
3613  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10.
3614  */
3615 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_s
3616 {
3617  volatile uint32_t DATALINKUSER10 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_DATALINKUSER10 */
3618  uint32_t : 26; /* *UNDEFINED* */
3619 };
3620 
3621 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10. */
3622 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_t;
3623 #endif /* __ASSEMBLY__ */
3624 
3625 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10 register. */
3626 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_RESET 0x00000006
3627 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10 register from the beginning of the component. */
3628 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_OFST 0xa8
3629 
3630 /*
3631  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser11
3632  *
3633  * Register Layout
3634  *
3635  * Bits | Access | Reset | Description
3636  * :-------|:-------|:--------|:---------------------------------------------------------------------
3637  * [5:0] | RW | 0x7 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11
3638  * [31:6] | ??? | Unknown | *UNDEFINED*
3639  *
3640  */
3641 /*
3642  * Field : DATALINKUSER11
3643  *
3644  * This 6 bits register sets the slave interfaces source of the LLI User bit 11.
3645  * When the selected source bit is not implemented or the register value is not
3646  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3647  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3648  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3649  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3650  *
3651  * 0x3F LLI.User[r] <<= 1.
3652  *
3653  * Field Access Macros:
3654  *
3655  */
3656 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field. */
3657 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_LSB 0
3658 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field. */
3659 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_MSB 5
3660 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field. */
3661 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_WIDTH 6
3662 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field value. */
3663 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_SET_MSK 0x0000003f
3664 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field value. */
3665 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_CLR_MSK 0xffffffc0
3666 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field. */
3667 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_RESET 0x7
3668 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 field value from a register. */
3669 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_GET(value) (((value) & 0x0000003f) >> 0)
3670 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 register field value suitable for setting the register. */
3671 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11_SET(value) (((value) << 0) & 0x0000003f)
3672 
3673 #ifndef __ASSEMBLY__
3674 /*
3675  * WARNING: The C register and register group struct declarations are provided for
3676  * convenience and illustrative purposes. They should, however, be used with
3677  * caution as the C language standard provides no guarantees about the alignment or
3678  * atomicity of device memory accesses. The recommended practice for writing
3679  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3680  * alt_write_word() functions.
3681  *
3682  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11.
3683  */
3684 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_s
3685 {
3686  volatile uint32_t DATALINKUSER11 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_DATALINKUSER11 */
3687  uint32_t : 26; /* *UNDEFINED* */
3688 };
3689 
3690 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11. */
3691 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_t;
3692 #endif /* __ASSEMBLY__ */
3693 
3694 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11 register. */
3695 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_RESET 0x00000007
3696 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11 register from the beginning of the component. */
3697 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_OFST 0xac
3698 
3699 /*
3700  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser12
3701  *
3702  * Register Layout
3703  *
3704  * Bits | Access | Reset | Description
3705  * :-------|:-------|:--------|:---------------------------------------------------------------------
3706  * [5:0] | RW | 0x8 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12
3707  * [31:6] | ??? | Unknown | *UNDEFINED*
3708  *
3709  */
3710 /*
3711  * Field : DATALINKUSER12
3712  *
3713  * This 6 bits register sets the slave interfaces source of the LLI User bit 12.
3714  * When the selected source bit is not implemented or the register value is not
3715  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3716  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3717  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3718  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3719  *
3720  * 0x3F LLI.User[r] <<= 1.
3721  *
3722  * Field Access Macros:
3723  *
3724  */
3725 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field. */
3726 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_LSB 0
3727 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field. */
3728 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_MSB 5
3729 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field. */
3730 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_WIDTH 6
3731 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field value. */
3732 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_SET_MSK 0x0000003f
3733 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field value. */
3734 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_CLR_MSK 0xffffffc0
3735 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field. */
3736 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_RESET 0x8
3737 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 field value from a register. */
3738 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_GET(value) (((value) & 0x0000003f) >> 0)
3739 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 register field value suitable for setting the register. */
3740 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12_SET(value) (((value) << 0) & 0x0000003f)
3741 
3742 #ifndef __ASSEMBLY__
3743 /*
3744  * WARNING: The C register and register group struct declarations are provided for
3745  * convenience and illustrative purposes. They should, however, be used with
3746  * caution as the C language standard provides no guarantees about the alignment or
3747  * atomicity of device memory accesses. The recommended practice for writing
3748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3749  * alt_write_word() functions.
3750  *
3751  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12.
3752  */
3753 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_s
3754 {
3755  volatile uint32_t DATALINKUSER12 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_DATALINKUSER12 */
3756  uint32_t : 26; /* *UNDEFINED* */
3757 };
3758 
3759 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12. */
3760 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_t;
3761 #endif /* __ASSEMBLY__ */
3762 
3763 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12 register. */
3764 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_RESET 0x00000008
3765 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12 register from the beginning of the component. */
3766 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_OFST 0xb0
3767 
3768 /*
3769  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser13
3770  *
3771  * Register Layout
3772  *
3773  * Bits | Access | Reset | Description
3774  * :-------|:-------|:--------|:---------------------------------------------------------------------
3775  * [5:0] | RW | 0x9 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13
3776  * [31:6] | ??? | Unknown | *UNDEFINED*
3777  *
3778  */
3779 /*
3780  * Field : DATALINKUSER13
3781  *
3782  * This 6 bits register sets the slave interfaces source of the LLI User bit 13.
3783  * When the selected source bit is not implemented or the register value is not
3784  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3785  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3786  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3787  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3788  *
3789  * 0x3F LLI.User[r] <<= 1.
3790  *
3791  * Field Access Macros:
3792  *
3793  */
3794 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field. */
3795 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_LSB 0
3796 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field. */
3797 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_MSB 5
3798 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field. */
3799 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_WIDTH 6
3800 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field value. */
3801 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_SET_MSK 0x0000003f
3802 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field value. */
3803 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_CLR_MSK 0xffffffc0
3804 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field. */
3805 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_RESET 0x9
3806 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 field value from a register. */
3807 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_GET(value) (((value) & 0x0000003f) >> 0)
3808 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 register field value suitable for setting the register. */
3809 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13_SET(value) (((value) << 0) & 0x0000003f)
3810 
3811 #ifndef __ASSEMBLY__
3812 /*
3813  * WARNING: The C register and register group struct declarations are provided for
3814  * convenience and illustrative purposes. They should, however, be used with
3815  * caution as the C language standard provides no guarantees about the alignment or
3816  * atomicity of device memory accesses. The recommended practice for writing
3817  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3818  * alt_write_word() functions.
3819  *
3820  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13.
3821  */
3822 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_s
3823 {
3824  volatile uint32_t DATALINKUSER13 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_DATALINKUSER13 */
3825  uint32_t : 26; /* *UNDEFINED* */
3826 };
3827 
3828 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13. */
3829 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_t;
3830 #endif /* __ASSEMBLY__ */
3831 
3832 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13 register. */
3833 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_RESET 0x00000009
3834 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13 register from the beginning of the component. */
3835 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_OFST 0xb4
3836 
3837 /*
3838  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser14
3839  *
3840  * Register Layout
3841  *
3842  * Bits | Access | Reset | Description
3843  * :-------|:-------|:--------|:---------------------------------------------------------------------
3844  * [5:0] | RW | 0xa | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14
3845  * [31:6] | ??? | Unknown | *UNDEFINED*
3846  *
3847  */
3848 /*
3849  * Field : DATALINKUSER14
3850  *
3851  * This 6 bits register sets the slave interfaces source of the LLI User bit 14.
3852  * When the selected source bit is not implemented or the register value is not
3853  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3854  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3855  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3856  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3857  *
3858  * 0x3F LLI.User[r] <<= 1.
3859  *
3860  * Field Access Macros:
3861  *
3862  */
3863 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field. */
3864 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_LSB 0
3865 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field. */
3866 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_MSB 5
3867 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field. */
3868 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_WIDTH 6
3869 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field value. */
3870 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_SET_MSK 0x0000003f
3871 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field value. */
3872 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_CLR_MSK 0xffffffc0
3873 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field. */
3874 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_RESET 0xa
3875 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 field value from a register. */
3876 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_GET(value) (((value) & 0x0000003f) >> 0)
3877 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 register field value suitable for setting the register. */
3878 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14_SET(value) (((value) << 0) & 0x0000003f)
3879 
3880 #ifndef __ASSEMBLY__
3881 /*
3882  * WARNING: The C register and register group struct declarations are provided for
3883  * convenience and illustrative purposes. They should, however, be used with
3884  * caution as the C language standard provides no guarantees about the alignment or
3885  * atomicity of device memory accesses. The recommended practice for writing
3886  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3887  * alt_write_word() functions.
3888  *
3889  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14.
3890  */
3891 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_s
3892 {
3893  volatile uint32_t DATALINKUSER14 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_DATALINKUSER14 */
3894  uint32_t : 26; /* *UNDEFINED* */
3895 };
3896 
3897 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14. */
3898 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_t;
3899 #endif /* __ASSEMBLY__ */
3900 
3901 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14 register. */
3902 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_RESET 0x0000000a
3903 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14 register from the beginning of the component. */
3904 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_OFST 0xb8
3905 
3906 /*
3907  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser15
3908  *
3909  * Register Layout
3910  *
3911  * Bits | Access | Reset | Description
3912  * :-------|:-------|:--------|:---------------------------------------------------------------------
3913  * [5:0] | RW | 0xb | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15
3914  * [31:6] | ??? | Unknown | *UNDEFINED*
3915  *
3916  */
3917 /*
3918  * Field : DATALINKUSER15
3919  *
3920  * This 6 bits register sets the slave interfaces source of the LLI User bit 15.
3921  * When the selected source bit is not implemented or the register value is not
3922  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3923  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3924  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3925  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3926  *
3927  * 0x3F LLI.User[r] <<= 1.
3928  *
3929  * Field Access Macros:
3930  *
3931  */
3932 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field. */
3933 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_LSB 0
3934 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field. */
3935 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_MSB 5
3936 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field. */
3937 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_WIDTH 6
3938 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field value. */
3939 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_SET_MSK 0x0000003f
3940 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field value. */
3941 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_CLR_MSK 0xffffffc0
3942 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field. */
3943 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_RESET 0xb
3944 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 field value from a register. */
3945 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_GET(value) (((value) & 0x0000003f) >> 0)
3946 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 register field value suitable for setting the register. */
3947 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15_SET(value) (((value) << 0) & 0x0000003f)
3948 
3949 #ifndef __ASSEMBLY__
3950 /*
3951  * WARNING: The C register and register group struct declarations are provided for
3952  * convenience and illustrative purposes. They should, however, be used with
3953  * caution as the C language standard provides no guarantees about the alignment or
3954  * atomicity of device memory accesses. The recommended practice for writing
3955  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3956  * alt_write_word() functions.
3957  *
3958  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15.
3959  */
3960 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_s
3961 {
3962  volatile uint32_t DATALINKUSER15 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_DATALINKUSER15 */
3963  uint32_t : 26; /* *UNDEFINED* */
3964 };
3965 
3966 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15. */
3967 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_t;
3968 #endif /* __ASSEMBLY__ */
3969 
3970 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15 register. */
3971 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_RESET 0x0000000b
3972 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15 register from the beginning of the component. */
3973 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_OFST 0xbc
3974 
3975 /*
3976  * Register : LLI_Targ_Svc_LLI_User_DataLinkUser16
3977  *
3978  * Register Layout
3979  *
3980  * Bits | Access | Reset | Description
3981  * :-------|:-------|:--------|:---------------------------------------------------------------------
3982  * [5:0] | RW | 0x20 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16
3983  * [31:6] | ??? | Unknown | *UNDEFINED*
3984  *
3985  */
3986 /*
3987  * Field : DATALINKUSER16
3988  *
3989  * This 6 bits register sets the slave interfaces source of the LLI User bit 16.
3990  * When the selected source bit is not implemented or the register value is not
3991  * assigned, the LLI User bit is set to 0. Each register (r) uses the following
3992  * value (v) encoding. 0x00 to 0x1F: LLI.User[r] <<= Req.User[v]; 0x20 to 0x27:
3993  * LLI.User[r] <<= Req.Security[v-0x20]; 0x30 to 0x31: LLI.User[r] <<=
3994  * Req.Urgency[v-0x30]; 0x3E: LLI.User[r] <<= 0
3995  *
3996  * 0x3F LLI.User[r] <<= 1.
3997  *
3998  * Field Access Macros:
3999  *
4000  */
4001 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field. */
4002 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_LSB 0
4003 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field. */
4004 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_MSB 5
4005 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field. */
4006 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_WIDTH 6
4007 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field value. */
4008 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_SET_MSK 0x0000003f
4009 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field value. */
4010 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_CLR_MSK 0xffffffc0
4011 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field. */
4012 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_RESET 0x20
4013 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 field value from a register. */
4014 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_GET(value) (((value) & 0x0000003f) >> 0)
4015 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 register field value suitable for setting the register. */
4016 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16_SET(value) (((value) << 0) & 0x0000003f)
4017 
4018 #ifndef __ASSEMBLY__
4019 /*
4020  * WARNING: The C register and register group struct declarations are provided for
4021  * convenience and illustrative purposes. They should, however, be used with
4022  * caution as the C language standard provides no guarantees about the alignment or
4023  * atomicity of device memory accesses. The recommended practice for writing
4024  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4025  * alt_write_word() functions.
4026  *
4027  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16.
4028  */
4029 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_s
4030 {
4031  volatile uint32_t DATALINKUSER16 : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_DATALINKUSER16 */
4032  uint32_t : 26; /* *UNDEFINED* */
4033 };
4034 
4035 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16. */
4036 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_t;
4037 #endif /* __ASSEMBLY__ */
4038 
4039 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16 register. */
4040 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_RESET 0x00000020
4041 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16 register from the beginning of the component. */
4042 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_OFST 0xc0
4043 
4044 /*
4045  * Register : LLI_Targ_Svc_LLI_User_DataLinkPosted
4046  *
4047  * Register Layout
4048  *
4049  * Bits | Access | Reset | Description
4050  * :-------|:-------|:--------|:---------------------------------------------------------------------
4051  * [5:0] | RW | 0x0 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED
4052  * [31:6] | ??? | Unknown | *UNDEFINED*
4053  *
4054  */
4055 /*
4056  * Field : DATALINKPOSTED
4057  *
4058  * This 6 bits register sets the slave interfaces source of the LLI WRP Opcode, and
4059  * this bit is only significant for Writes. When the selected source bit is not
4060  * implemented or the register value is not assigned, the Non-Posted Opcode is
4061  * used. This register uses the following value (v) encoding: 0x00 to 0x20: LLI.WRP
4062  * <<= Targ.Req.User[v]; 0x3E LLI.WRP <<= 0; 0x3F LLI.WRP <<= 1.
4063  *
4064  * Field Access Macros:
4065  *
4066  */
4067 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field. */
4068 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_LSB 0
4069 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field. */
4070 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_MSB 5
4071 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field. */
4072 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_WIDTH 6
4073 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field value. */
4074 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_SET_MSK 0x0000003f
4075 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field value. */
4076 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_CLR_MSK 0xffffffc0
4077 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field. */
4078 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_RESET 0x0
4079 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED field value from a register. */
4080 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_GET(value) (((value) & 0x0000003f) >> 0)
4081 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED register field value suitable for setting the register. */
4082 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED_SET(value) (((value) << 0) & 0x0000003f)
4083 
4084 #ifndef __ASSEMBLY__
4085 /*
4086  * WARNING: The C register and register group struct declarations are provided for
4087  * convenience and illustrative purposes. They should, however, be used with
4088  * caution as the C language standard provides no guarantees about the alignment or
4089  * atomicity of device memory accesses. The recommended practice for writing
4090  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4091  * alt_write_word() functions.
4092  *
4093  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED.
4094  */
4095 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_s
4096 {
4097  volatile uint32_t DATALINKPOSTED : 6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_DATALINKPOSTED */
4098  uint32_t : 26; /* *UNDEFINED* */
4099 };
4100 
4101 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED. */
4102 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_t;
4103 #endif /* __ASSEMBLY__ */
4104 
4105 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED register. */
4106 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_RESET 0x00000000
4107 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED register from the beginning of the component. */
4108 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_OFST 0xfc
4109 
4110 /*
4111  * Register : LLI_Targ_Svc_LLI_User_GenUser0
4112  *
4113  * Register Layout
4114  *
4115  * Bits | Access | Reset | Description
4116  * :-------|:-------|:--------|:---------------------------------------------------------
4117  * [4:0] | RW | 0x4 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0
4118  * [31:5] | ??? | Unknown | *UNDEFINED*
4119  *
4120  */
4121 /*
4122  * Field : GENUSER0
4123  *
4124  * This 5 bits register sets the source of the corresponding Req.User bit on master
4125  * interfaces. When the register value is not assigned, the User bit is set to 0.
4126  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4127  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4128  * <<= 0; 0x1F: Req.User[r] <<= 1.
4129  *
4130  * Field Access Macros:
4131  *
4132  */
4133 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field. */
4134 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_LSB 0
4135 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field. */
4136 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_MSB 4
4137 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field. */
4138 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_WIDTH 5
4139 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field value. */
4140 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_SET_MSK 0x0000001f
4141 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field value. */
4142 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_CLR_MSK 0xffffffe0
4143 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field. */
4144 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_RESET 0x4
4145 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 field value from a register. */
4146 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_GET(value) (((value) & 0x0000001f) >> 0)
4147 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 register field value suitable for setting the register. */
4148 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0_SET(value) (((value) << 0) & 0x0000001f)
4149 
4150 #ifndef __ASSEMBLY__
4151 /*
4152  * WARNING: The C register and register group struct declarations are provided for
4153  * convenience and illustrative purposes. They should, however, be used with
4154  * caution as the C language standard provides no guarantees about the alignment or
4155  * atomicity of device memory accesses. The recommended practice for writing
4156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4157  * alt_write_word() functions.
4158  *
4159  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0.
4160  */
4161 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_s
4162 {
4163  volatile uint32_t GENUSER0 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_GENUSER0 */
4164  uint32_t : 27; /* *UNDEFINED* */
4165 };
4166 
4167 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0. */
4168 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_t;
4169 #endif /* __ASSEMBLY__ */
4170 
4171 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0 register. */
4172 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_RESET 0x00000004
4173 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0 register from the beginning of the component. */
4174 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_OFST 0x100
4175 
4176 /*
4177  * Register : LLI_Targ_Svc_LLI_User_GenUser1
4178  *
4179  * Register Layout
4180  *
4181  * Bits | Access | Reset | Description
4182  * :-------|:-------|:--------|:---------------------------------------------------------
4183  * [4:0] | RW | 0x5 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1
4184  * [31:5] | ??? | Unknown | *UNDEFINED*
4185  *
4186  */
4187 /*
4188  * Field : GENUSER1
4189  *
4190  * This 5 bits register sets the source of the corresponding Req.User bit on master
4191  * interfaces. When the register value is not assigned, the User bit is set to 0.
4192  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4193  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4194  * <<= 0; 0x1F: Req.User[r] <<= 1.
4195  *
4196  * Field Access Macros:
4197  *
4198  */
4199 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field. */
4200 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_LSB 0
4201 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field. */
4202 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_MSB 4
4203 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field. */
4204 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_WIDTH 5
4205 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field value. */
4206 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_SET_MSK 0x0000001f
4207 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field value. */
4208 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_CLR_MSK 0xffffffe0
4209 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field. */
4210 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_RESET 0x5
4211 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 field value from a register. */
4212 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_GET(value) (((value) & 0x0000001f) >> 0)
4213 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 register field value suitable for setting the register. */
4214 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1_SET(value) (((value) << 0) & 0x0000001f)
4215 
4216 #ifndef __ASSEMBLY__
4217 /*
4218  * WARNING: The C register and register group struct declarations are provided for
4219  * convenience and illustrative purposes. They should, however, be used with
4220  * caution as the C language standard provides no guarantees about the alignment or
4221  * atomicity of device memory accesses. The recommended practice for writing
4222  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4223  * alt_write_word() functions.
4224  *
4225  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1.
4226  */
4227 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_s
4228 {
4229  volatile uint32_t GENUSER1 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_GENUSER1 */
4230  uint32_t : 27; /* *UNDEFINED* */
4231 };
4232 
4233 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1. */
4234 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_t;
4235 #endif /* __ASSEMBLY__ */
4236 
4237 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1 register. */
4238 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_RESET 0x00000005
4239 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1 register from the beginning of the component. */
4240 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_OFST 0x104
4241 
4242 /*
4243  * Register : LLI_Targ_Svc_LLI_User_GenUser2
4244  *
4245  * Register Layout
4246  *
4247  * Bits | Access | Reset | Description
4248  * :-------|:-------|:--------|:---------------------------------------------------------
4249  * [4:0] | RW | 0x6 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2
4250  * [31:5] | ??? | Unknown | *UNDEFINED*
4251  *
4252  */
4253 /*
4254  * Field : GENUSER2
4255  *
4256  * This 5 bits register sets the source of the corresponding Req.User bit on master
4257  * interfaces. When the register value is not assigned, the User bit is set to 0.
4258  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4259  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4260  * <<= 0; 0x1F: Req.User[r] <<= 1.
4261  *
4262  * Field Access Macros:
4263  *
4264  */
4265 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field. */
4266 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_LSB 0
4267 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field. */
4268 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_MSB 4
4269 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field. */
4270 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_WIDTH 5
4271 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field value. */
4272 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_SET_MSK 0x0000001f
4273 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field value. */
4274 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_CLR_MSK 0xffffffe0
4275 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field. */
4276 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_RESET 0x6
4277 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 field value from a register. */
4278 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_GET(value) (((value) & 0x0000001f) >> 0)
4279 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 register field value suitable for setting the register. */
4280 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2_SET(value) (((value) << 0) & 0x0000001f)
4281 
4282 #ifndef __ASSEMBLY__
4283 /*
4284  * WARNING: The C register and register group struct declarations are provided for
4285  * convenience and illustrative purposes. They should, however, be used with
4286  * caution as the C language standard provides no guarantees about the alignment or
4287  * atomicity of device memory accesses. The recommended practice for writing
4288  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4289  * alt_write_word() functions.
4290  *
4291  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2.
4292  */
4293 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_s
4294 {
4295  volatile uint32_t GENUSER2 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_GENUSER2 */
4296  uint32_t : 27; /* *UNDEFINED* */
4297 };
4298 
4299 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2. */
4300 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_t;
4301 #endif /* __ASSEMBLY__ */
4302 
4303 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2 register. */
4304 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_RESET 0x00000006
4305 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2 register from the beginning of the component. */
4306 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_OFST 0x108
4307 
4308 /*
4309  * Register : LLI_Targ_Svc_LLI_User_GenUser3
4310  *
4311  * Register Layout
4312  *
4313  * Bits | Access | Reset | Description
4314  * :-------|:-------|:--------|:---------------------------------------------------------
4315  * [4:0] | RW | 0x7 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3
4316  * [31:5] | ??? | Unknown | *UNDEFINED*
4317  *
4318  */
4319 /*
4320  * Field : GENUSER3
4321  *
4322  * This 5 bits register sets the source of the corresponding Req.User bit on master
4323  * interfaces. When the register value is not assigned, the User bit is set to 0.
4324  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4325  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4326  * <<= 0; 0x1F: Req.User[r] <<= 1.
4327  *
4328  * Field Access Macros:
4329  *
4330  */
4331 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field. */
4332 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_LSB 0
4333 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field. */
4334 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_MSB 4
4335 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field. */
4336 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_WIDTH 5
4337 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field value. */
4338 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_SET_MSK 0x0000001f
4339 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field value. */
4340 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_CLR_MSK 0xffffffe0
4341 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field. */
4342 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_RESET 0x7
4343 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 field value from a register. */
4344 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_GET(value) (((value) & 0x0000001f) >> 0)
4345 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 register field value suitable for setting the register. */
4346 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3_SET(value) (((value) << 0) & 0x0000001f)
4347 
4348 #ifndef __ASSEMBLY__
4349 /*
4350  * WARNING: The C register and register group struct declarations are provided for
4351  * convenience and illustrative purposes. They should, however, be used with
4352  * caution as the C language standard provides no guarantees about the alignment or
4353  * atomicity of device memory accesses. The recommended practice for writing
4354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4355  * alt_write_word() functions.
4356  *
4357  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3.
4358  */
4359 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_s
4360 {
4361  volatile uint32_t GENUSER3 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_GENUSER3 */
4362  uint32_t : 27; /* *UNDEFINED* */
4363 };
4364 
4365 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3. */
4366 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_t;
4367 #endif /* __ASSEMBLY__ */
4368 
4369 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3 register. */
4370 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_RESET 0x00000007
4371 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3 register from the beginning of the component. */
4372 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_OFST 0x10c
4373 
4374 /*
4375  * Register : LLI_Targ_Svc_LLI_User_GenUser4
4376  *
4377  * Register Layout
4378  *
4379  * Bits | Access | Reset | Description
4380  * :-------|:-------|:--------|:---------------------------------------------------------
4381  * [4:0] | RW | 0x8 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4
4382  * [31:5] | ??? | Unknown | *UNDEFINED*
4383  *
4384  */
4385 /*
4386  * Field : GENUSER4
4387  *
4388  * This 5 bits register sets the source of the corresponding Req.User bit on master
4389  * interfaces. When the register value is not assigned, the User bit is set to 0.
4390  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4391  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4392  * <<= 0; 0x1F: Req.User[r] <<= 1.
4393  *
4394  * Field Access Macros:
4395  *
4396  */
4397 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field. */
4398 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_LSB 0
4399 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field. */
4400 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_MSB 4
4401 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field. */
4402 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_WIDTH 5
4403 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field value. */
4404 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_SET_MSK 0x0000001f
4405 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field value. */
4406 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_CLR_MSK 0xffffffe0
4407 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field. */
4408 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_RESET 0x8
4409 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 field value from a register. */
4410 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_GET(value) (((value) & 0x0000001f) >> 0)
4411 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 register field value suitable for setting the register. */
4412 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4_SET(value) (((value) << 0) & 0x0000001f)
4413 
4414 #ifndef __ASSEMBLY__
4415 /*
4416  * WARNING: The C register and register group struct declarations are provided for
4417  * convenience and illustrative purposes. They should, however, be used with
4418  * caution as the C language standard provides no guarantees about the alignment or
4419  * atomicity of device memory accesses. The recommended practice for writing
4420  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4421  * alt_write_word() functions.
4422  *
4423  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4.
4424  */
4425 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_s
4426 {
4427  volatile uint32_t GENUSER4 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_GENUSER4 */
4428  uint32_t : 27; /* *UNDEFINED* */
4429 };
4430 
4431 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4. */
4432 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_t;
4433 #endif /* __ASSEMBLY__ */
4434 
4435 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4 register. */
4436 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_RESET 0x00000008
4437 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4 register from the beginning of the component. */
4438 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_OFST 0x110
4439 
4440 /*
4441  * Register : LLI_Targ_Svc_LLI_User_GenUser5
4442  *
4443  * Register Layout
4444  *
4445  * Bits | Access | Reset | Description
4446  * :-------|:-------|:--------|:---------------------------------------------------------
4447  * [4:0] | RW | 0x9 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5
4448  * [31:5] | ??? | Unknown | *UNDEFINED*
4449  *
4450  */
4451 /*
4452  * Field : GENUSER5
4453  *
4454  * This 5 bits register sets the source of the corresponding Req.User bit on master
4455  * interfaces. When the register value is not assigned, the User bit is set to 0.
4456  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4457  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4458  * <<= 0; 0x1F: Req.User[r] <<= 1.
4459  *
4460  * Field Access Macros:
4461  *
4462  */
4463 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field. */
4464 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_LSB 0
4465 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field. */
4466 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_MSB 4
4467 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field. */
4468 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_WIDTH 5
4469 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field value. */
4470 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_SET_MSK 0x0000001f
4471 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field value. */
4472 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_CLR_MSK 0xffffffe0
4473 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field. */
4474 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_RESET 0x9
4475 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 field value from a register. */
4476 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_GET(value) (((value) & 0x0000001f) >> 0)
4477 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 register field value suitable for setting the register. */
4478 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5_SET(value) (((value) << 0) & 0x0000001f)
4479 
4480 #ifndef __ASSEMBLY__
4481 /*
4482  * WARNING: The C register and register group struct declarations are provided for
4483  * convenience and illustrative purposes. They should, however, be used with
4484  * caution as the C language standard provides no guarantees about the alignment or
4485  * atomicity of device memory accesses. The recommended practice for writing
4486  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4487  * alt_write_word() functions.
4488  *
4489  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5.
4490  */
4491 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_s
4492 {
4493  volatile uint32_t GENUSER5 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_GENUSER5 */
4494  uint32_t : 27; /* *UNDEFINED* */
4495 };
4496 
4497 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5. */
4498 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_t;
4499 #endif /* __ASSEMBLY__ */
4500 
4501 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5 register. */
4502 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_RESET 0x00000009
4503 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5 register from the beginning of the component. */
4504 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_OFST 0x114
4505 
4506 /*
4507  * Register : LLI_Targ_Svc_LLI_User_GenUser6
4508  *
4509  * Register Layout
4510  *
4511  * Bits | Access | Reset | Description
4512  * :-------|:-------|:--------|:---------------------------------------------------------
4513  * [4:0] | RW | 0xa | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6
4514  * [31:5] | ??? | Unknown | *UNDEFINED*
4515  *
4516  */
4517 /*
4518  * Field : GENUSER6
4519  *
4520  * This 5 bits register sets the source of the corresponding Req.User bit on master
4521  * interfaces. When the register value is not assigned, the User bit is set to 0.
4522  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4523  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4524  * <<= 0; 0x1F: Req.User[r] <<= 1.
4525  *
4526  * Field Access Macros:
4527  *
4528  */
4529 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field. */
4530 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_LSB 0
4531 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field. */
4532 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_MSB 4
4533 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field. */
4534 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_WIDTH 5
4535 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field value. */
4536 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_SET_MSK 0x0000001f
4537 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field value. */
4538 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_CLR_MSK 0xffffffe0
4539 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field. */
4540 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_RESET 0xa
4541 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 field value from a register. */
4542 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_GET(value) (((value) & 0x0000001f) >> 0)
4543 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 register field value suitable for setting the register. */
4544 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6_SET(value) (((value) << 0) & 0x0000001f)
4545 
4546 #ifndef __ASSEMBLY__
4547 /*
4548  * WARNING: The C register and register group struct declarations are provided for
4549  * convenience and illustrative purposes. They should, however, be used with
4550  * caution as the C language standard provides no guarantees about the alignment or
4551  * atomicity of device memory accesses. The recommended practice for writing
4552  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4553  * alt_write_word() functions.
4554  *
4555  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6.
4556  */
4557 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_s
4558 {
4559  volatile uint32_t GENUSER6 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_GENUSER6 */
4560  uint32_t : 27; /* *UNDEFINED* */
4561 };
4562 
4563 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6. */
4564 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_t;
4565 #endif /* __ASSEMBLY__ */
4566 
4567 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6 register. */
4568 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_RESET 0x0000000a
4569 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6 register from the beginning of the component. */
4570 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_OFST 0x118
4571 
4572 /*
4573  * Register : LLI_Targ_Svc_LLI_User_GenUser7
4574  *
4575  * Register Layout
4576  *
4577  * Bits | Access | Reset | Description
4578  * :-------|:-------|:--------|:---------------------------------------------------------
4579  * [4:0] | RW | 0xb | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7
4580  * [31:5] | ??? | Unknown | *UNDEFINED*
4581  *
4582  */
4583 /*
4584  * Field : GENUSER7
4585  *
4586  * This 5 bits register sets the source of the corresponding Req.User bit on master
4587  * interfaces. When the register value is not assigned, the User bit is set to 0.
4588  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4589  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4590  * <<= 0; 0x1F: Req.User[r] <<= 1.
4591  *
4592  * Field Access Macros:
4593  *
4594  */
4595 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field. */
4596 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_LSB 0
4597 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field. */
4598 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_MSB 4
4599 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field. */
4600 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_WIDTH 5
4601 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field value. */
4602 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_SET_MSK 0x0000001f
4603 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field value. */
4604 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_CLR_MSK 0xffffffe0
4605 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field. */
4606 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_RESET 0xb
4607 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 field value from a register. */
4608 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_GET(value) (((value) & 0x0000001f) >> 0)
4609 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 register field value suitable for setting the register. */
4610 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7_SET(value) (((value) << 0) & 0x0000001f)
4611 
4612 #ifndef __ASSEMBLY__
4613 /*
4614  * WARNING: The C register and register group struct declarations are provided for
4615  * convenience and illustrative purposes. They should, however, be used with
4616  * caution as the C language standard provides no guarantees about the alignment or
4617  * atomicity of device memory accesses. The recommended practice for writing
4618  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4619  * alt_write_word() functions.
4620  *
4621  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7.
4622  */
4623 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_s
4624 {
4625  volatile uint32_t GENUSER7 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_GENUSER7 */
4626  uint32_t : 27; /* *UNDEFINED* */
4627 };
4628 
4629 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7. */
4630 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_t;
4631 #endif /* __ASSEMBLY__ */
4632 
4633 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7 register. */
4634 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_RESET 0x0000000b
4635 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7 register from the beginning of the component. */
4636 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_OFST 0x11c
4637 
4638 /*
4639  * Register : LLI_Targ_Svc_LLI_User_GenUser8
4640  *
4641  * Register Layout
4642  *
4643  * Bits | Access | Reset | Description
4644  * :-------|:-------|:--------|:---------------------------------------------------------
4645  * [4:0] | RW | 0xc | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8
4646  * [31:5] | ??? | Unknown | *UNDEFINED*
4647  *
4648  */
4649 /*
4650  * Field : GENUSER8
4651  *
4652  * This 5 bits register sets the source of the corresponding Req.User bit on master
4653  * interfaces. When the register value is not assigned, the User bit is set to 0.
4654  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4655  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4656  * <<= 0; 0x1F: Req.User[r] <<= 1.
4657  *
4658  * Field Access Macros:
4659  *
4660  */
4661 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field. */
4662 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_LSB 0
4663 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field. */
4664 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_MSB 4
4665 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field. */
4666 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_WIDTH 5
4667 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field value. */
4668 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_SET_MSK 0x0000001f
4669 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field value. */
4670 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_CLR_MSK 0xffffffe0
4671 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field. */
4672 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_RESET 0xc
4673 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 field value from a register. */
4674 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_GET(value) (((value) & 0x0000001f) >> 0)
4675 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 register field value suitable for setting the register. */
4676 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8_SET(value) (((value) << 0) & 0x0000001f)
4677 
4678 #ifndef __ASSEMBLY__
4679 /*
4680  * WARNING: The C register and register group struct declarations are provided for
4681  * convenience and illustrative purposes. They should, however, be used with
4682  * caution as the C language standard provides no guarantees about the alignment or
4683  * atomicity of device memory accesses. The recommended practice for writing
4684  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4685  * alt_write_word() functions.
4686  *
4687  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8.
4688  */
4689 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_s
4690 {
4691  volatile uint32_t GENUSER8 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_GENUSER8 */
4692  uint32_t : 27; /* *UNDEFINED* */
4693 };
4694 
4695 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8. */
4696 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_t;
4697 #endif /* __ASSEMBLY__ */
4698 
4699 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8 register. */
4700 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_RESET 0x0000000c
4701 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8 register from the beginning of the component. */
4702 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_OFST 0x120
4703 
4704 /*
4705  * Register : LLI_Targ_Svc_LLI_User_GenUser9
4706  *
4707  * Register Layout
4708  *
4709  * Bits | Access | Reset | Description
4710  * :-------|:-------|:--------|:---------------------------------------------------------
4711  * [4:0] | RW | 0xd | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9
4712  * [31:5] | ??? | Unknown | *UNDEFINED*
4713  *
4714  */
4715 /*
4716  * Field : GENUSER9
4717  *
4718  * This 5 bits register sets the source of the corresponding Req.User bit on master
4719  * interfaces. When the register value is not assigned, the User bit is set to 0.
4720  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4721  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4722  * <<= 0; 0x1F: Req.User[r] <<= 1.
4723  *
4724  * Field Access Macros:
4725  *
4726  */
4727 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field. */
4728 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_LSB 0
4729 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field. */
4730 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_MSB 4
4731 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field. */
4732 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_WIDTH 5
4733 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field value. */
4734 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_SET_MSK 0x0000001f
4735 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field value. */
4736 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_CLR_MSK 0xffffffe0
4737 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field. */
4738 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_RESET 0xd
4739 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 field value from a register. */
4740 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_GET(value) (((value) & 0x0000001f) >> 0)
4741 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 register field value suitable for setting the register. */
4742 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9_SET(value) (((value) << 0) & 0x0000001f)
4743 
4744 #ifndef __ASSEMBLY__
4745 /*
4746  * WARNING: The C register and register group struct declarations are provided for
4747  * convenience and illustrative purposes. They should, however, be used with
4748  * caution as the C language standard provides no guarantees about the alignment or
4749  * atomicity of device memory accesses. The recommended practice for writing
4750  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4751  * alt_write_word() functions.
4752  *
4753  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9.
4754  */
4755 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_s
4756 {
4757  volatile uint32_t GENUSER9 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_GENUSER9 */
4758  uint32_t : 27; /* *UNDEFINED* */
4759 };
4760 
4761 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9. */
4762 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_t;
4763 #endif /* __ASSEMBLY__ */
4764 
4765 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9 register. */
4766 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_RESET 0x0000000d
4767 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9 register from the beginning of the component. */
4768 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_OFST 0x124
4769 
4770 /*
4771  * Register : LLI_Targ_Svc_LLI_User_GenUser10
4772  *
4773  * Register Layout
4774  *
4775  * Bits | Access | Reset | Description
4776  * :-------|:-------|:--------|:-----------------------------------------------------------
4777  * [4:0] | RW | 0xe | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10
4778  * [31:5] | ??? | Unknown | *UNDEFINED*
4779  *
4780  */
4781 /*
4782  * Field : GENUSER10
4783  *
4784  * This 5 bits register sets the source of the corresponding Req.User bit on master
4785  * interfaces. When the register value is not assigned, the User bit is set to 0.
4786  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4787  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4788  * <<= 0; 0x1F: Req.User[r] <<= 1.
4789  *
4790  * Field Access Macros:
4791  *
4792  */
4793 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field. */
4794 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_LSB 0
4795 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field. */
4796 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_MSB 4
4797 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field. */
4798 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_WIDTH 5
4799 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field value. */
4800 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_SET_MSK 0x0000001f
4801 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field value. */
4802 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_CLR_MSK 0xffffffe0
4803 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field. */
4804 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_RESET 0xe
4805 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 field value from a register. */
4806 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_GET(value) (((value) & 0x0000001f) >> 0)
4807 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 register field value suitable for setting the register. */
4808 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10_SET(value) (((value) << 0) & 0x0000001f)
4809 
4810 #ifndef __ASSEMBLY__
4811 /*
4812  * WARNING: The C register and register group struct declarations are provided for
4813  * convenience and illustrative purposes. They should, however, be used with
4814  * caution as the C language standard provides no guarantees about the alignment or
4815  * atomicity of device memory accesses. The recommended practice for writing
4816  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4817  * alt_write_word() functions.
4818  *
4819  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10.
4820  */
4821 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_s
4822 {
4823  volatile uint32_t GENUSER10 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_GENUSER10 */
4824  uint32_t : 27; /* *UNDEFINED* */
4825 };
4826 
4827 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10. */
4828 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_t;
4829 #endif /* __ASSEMBLY__ */
4830 
4831 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10 register. */
4832 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_RESET 0x0000000e
4833 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10 register from the beginning of the component. */
4834 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_OFST 0x128
4835 
4836 /*
4837  * Register : LLI_Targ_Svc_LLI_User_GenUser11
4838  *
4839  * Register Layout
4840  *
4841  * Bits | Access | Reset | Description
4842  * :-------|:-------|:--------|:-----------------------------------------------------------
4843  * [4:0] | RW | 0xf | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11
4844  * [31:5] | ??? | Unknown | *UNDEFINED*
4845  *
4846  */
4847 /*
4848  * Field : GENUSER11
4849  *
4850  * This 5 bits register sets the source of the corresponding Req.User bit on master
4851  * interfaces. When the register value is not assigned, the User bit is set to 0.
4852  * Each register (r) uses the following value (v) encoding: 0x00 to 0x010:
4853  * Req.User[r] <<= LLI.User[v]; 0x1D: Req.User[r] <<= LLI.WRP; 0x1E: Req.User[r]
4854  * <<= 0; 0x1F: Req.User[r] <<= 1.
4855  *
4856  * Field Access Macros:
4857  *
4858  */
4859 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field. */
4860 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_LSB 0
4861 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field. */
4862 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_MSB 4
4863 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field. */
4864 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_WIDTH 5
4865 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field value. */
4866 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_SET_MSK 0x0000001f
4867 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field value. */
4868 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_CLR_MSK 0xffffffe0
4869 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field. */
4870 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_RESET 0xf
4871 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 field value from a register. */
4872 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_GET(value) (((value) & 0x0000001f) >> 0)
4873 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 register field value suitable for setting the register. */
4874 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11_SET(value) (((value) << 0) & 0x0000001f)
4875 
4876 #ifndef __ASSEMBLY__
4877 /*
4878  * WARNING: The C register and register group struct declarations are provided for
4879  * convenience and illustrative purposes. They should, however, be used with
4880  * caution as the C language standard provides no guarantees about the alignment or
4881  * atomicity of device memory accesses. The recommended practice for writing
4882  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4883  * alt_write_word() functions.
4884  *
4885  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11.
4886  */
4887 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_s
4888 {
4889  volatile uint32_t GENUSER11 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_GENUSER11 */
4890  uint32_t : 27; /* *UNDEFINED* */
4891 };
4892 
4893 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11. */
4894 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_t;
4895 #endif /* __ASSEMBLY__ */
4896 
4897 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11 register. */
4898 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_RESET 0x0000000f
4899 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11 register from the beginning of the component. */
4900 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_OFST 0x12c
4901 
4902 /*
4903  * Register : LLI_Targ_Svc_LLI_User_GenSecurity0
4904  *
4905  * Register Layout
4906  *
4907  * Bits | Access | Reset | Description
4908  * :-------|:-------|:--------|:-----------------------------------------------------------------
4909  * [4:0] | RW | 0x10 | ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0
4910  * [31:5] | ??? | Unknown | *UNDEFINED*
4911  *
4912  */
4913 /*
4914  * Field : GENSECURITY0
4915  *
4916  * This 5 bits register sets the source of the corresponding Req.Security bit on
4917  * master interfaces. When the register value is not assigned, the Security bit is
4918  * set to 0. Each register (r) uses the following value (v) encoding. 0x00 to 0x10:
4919  * Req.Security[r] <<= LLI.User[v]; 0x1E: Req.Security[r] <<= 0; 0x1F:
4920  * Req.Security[r] <<= 1.
4921  *
4922  * Field Access Macros:
4923  *
4924  */
4925 /* The Least Significant Bit (LSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field. */
4926 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_LSB 0
4927 /* The Most Significant Bit (MSB) position of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field. */
4928 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_MSB 4
4929 /* The width in bits of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field. */
4930 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_WIDTH 5
4931 /* The mask used to set the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field value. */
4932 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_SET_MSK 0x0000001f
4933 /* The mask used to clear the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field value. */
4934 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_CLR_MSK 0xffffffe0
4935 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field. */
4936 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_RESET 0x10
4937 /* Extracts the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 field value from a register. */
4938 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_GET(value) (((value) & 0x0000001f) >> 0)
4939 /* Produces a ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 register field value suitable for setting the register. */
4940 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0_SET(value) (((value) << 0) & 0x0000001f)
4941 
4942 #ifndef __ASSEMBLY__
4943 /*
4944  * WARNING: The C register and register group struct declarations are provided for
4945  * convenience and illustrative purposes. They should, however, be used with
4946  * caution as the C language standard provides no guarantees about the alignment or
4947  * atomicity of device memory accesses. The recommended practice for writing
4948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4949  * alt_write_word() functions.
4950  *
4951  * The struct declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0.
4952  */
4953 struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_s
4954 {
4955  volatile uint32_t GENSECURITY0 : 5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_GENSECURITY0 */
4956  uint32_t : 27; /* *UNDEFINED* */
4957 };
4958 
4959 /* The typedef declaration for register ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0. */
4960 typedef struct ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_s ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_t;
4961 #endif /* __ASSEMBLY__ */
4962 
4963 /* The reset value of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0 register. */
4964 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_RESET 0x00000010
4965 /* The byte offset of the ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0 register from the beginning of the component. */
4966 #define ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_OFST 0x180
4967 
4968 #ifndef __ASSEMBLY__
4969 /*
4970  * WARNING: The C register and register group struct declarations are provided for
4971  * convenience and illustrative purposes. They should, however, be used with
4972  * caution as the C language standard provides no guarantees about the alignment or
4973  * atomicity of device memory accesses. The recommended practice for writing
4974  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4975  * alt_write_word() functions.
4976  *
4977  * The struct declaration for register group ALT_PSI_LLI_USER.
4978  */
4979 struct ALT_PSI_LLI_USER_s
4980 {
4981  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE_t LLI_Targ_Svc_LLI_User_ArbiterMode; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE */
4982  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY_t LLI_Targ_Svc_LLI_User_CreditDelay; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY */
4983  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ_t LLI_Targ_Svc_LLI_User_MaskSystemIrq; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ */
4984  volatile uint32_t _pad_0xc_0x7f[29]; /* *UNDEFINED* */
4985  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0_t LLI_Targ_Svc_LLI_User_DataLinkUser0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0 */
4986  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1_t LLI_Targ_Svc_LLI_User_DataLinkUser1; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1 */
4987  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2_t LLI_Targ_Svc_LLI_User_DataLinkUser2; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2 */
4988  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3_t LLI_Targ_Svc_LLI_User_DataLinkUser3; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3 */
4989  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4_t LLI_Targ_Svc_LLI_User_DataLinkUser4; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4 */
4990  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5_t LLI_Targ_Svc_LLI_User_DataLinkUser5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5 */
4991  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6_t LLI_Targ_Svc_LLI_User_DataLinkUser6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6 */
4992  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7_t LLI_Targ_Svc_LLI_User_DataLinkUser7; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7 */
4993  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8_t LLI_Targ_Svc_LLI_User_DataLinkUser8; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8 */
4994  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9_t LLI_Targ_Svc_LLI_User_DataLinkUser9; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9 */
4995  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10_t LLI_Targ_Svc_LLI_User_DataLinkUser10; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10 */
4996  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11_t LLI_Targ_Svc_LLI_User_DataLinkUser11; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11 */
4997  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12_t LLI_Targ_Svc_LLI_User_DataLinkUser12; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12 */
4998  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13_t LLI_Targ_Svc_LLI_User_DataLinkUser13; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13 */
4999  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14_t LLI_Targ_Svc_LLI_User_DataLinkUser14; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14 */
5000  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15_t LLI_Targ_Svc_LLI_User_DataLinkUser15; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15 */
5001  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16_t LLI_Targ_Svc_LLI_User_DataLinkUser16; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16 */
5002  volatile uint32_t _pad_0xc4_0xfb[14]; /* *UNDEFINED* */
5003  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED_t LLI_Targ_Svc_LLI_User_DataLinkPosted; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED */
5004  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0_t LLI_Targ_Svc_LLI_User_GenUser0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0 */
5005  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1_t LLI_Targ_Svc_LLI_User_GenUser1; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1 */
5006  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2_t LLI_Targ_Svc_LLI_User_GenUser2; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2 */
5007  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3_t LLI_Targ_Svc_LLI_User_GenUser3; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3 */
5008  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4_t LLI_Targ_Svc_LLI_User_GenUser4; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4 */
5009  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5_t LLI_Targ_Svc_LLI_User_GenUser5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5 */
5010  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6_t LLI_Targ_Svc_LLI_User_GenUser6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6 */
5011  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7_t LLI_Targ_Svc_LLI_User_GenUser7; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7 */
5012  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8_t LLI_Targ_Svc_LLI_User_GenUser8; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8 */
5013  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9_t LLI_Targ_Svc_LLI_User_GenUser9; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9 */
5014  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10_t LLI_Targ_Svc_LLI_User_GenUser10; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10 */
5015  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11_t LLI_Targ_Svc_LLI_User_GenUser11; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11 */
5016  volatile uint32_t _pad_0x130_0x17f[20]; /* *UNDEFINED* */
5017  volatile ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0_t LLI_Targ_Svc_LLI_User_GenSecurity0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0 */
5018  volatile uint32_t _pad_0x184_0x1000[927]; /* *UNDEFINED* */
5019 };
5020 
5021 /* The typedef declaration for register group ALT_PSI_LLI_USER. */
5022 typedef struct ALT_PSI_LLI_USER_s ALT_PSI_LLI_USER_t;
5023 /* The struct declaration for the raw register contents of register group ALT_PSI_LLI_USER. */
5024 struct ALT_PSI_LLI_USER_raw_s
5025 {
5026  volatile uint32_t LLI_Targ_Svc_LLI_User_ArbiterMode; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_ARBITERMODE */
5027  volatile uint32_t LLI_Targ_Svc_LLI_User_CreditDelay; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_CREDITDELAY */
5028  volatile uint32_t LLI_Targ_Svc_LLI_User_MaskSystemIrq; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_MASKSYSTEMIRQ */
5029  volatile uint32_t _pad_0xc_0x7f[29]; /* *UNDEFINED* */
5030  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER0 */
5031  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser1; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER1 */
5032  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser2; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER2 */
5033  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser3; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER3 */
5034  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser4; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER4 */
5035  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER5 */
5036  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER6 */
5037  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser7; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER7 */
5038  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser8; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER8 */
5039  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser9; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER9 */
5040  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser10; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER10 */
5041  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser11; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER11 */
5042  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser12; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER12 */
5043  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser13; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER13 */
5044  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser14; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER14 */
5045  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser15; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER15 */
5046  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkUser16; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKUSER16 */
5047  volatile uint32_t _pad_0xc4_0xfb[14]; /* *UNDEFINED* */
5048  volatile uint32_t LLI_Targ_Svc_LLI_User_DataLinkPosted; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_DATALINKPOSTED */
5049  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER0 */
5050  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser1; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER1 */
5051  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser2; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER2 */
5052  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser3; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER3 */
5053  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser4; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER4 */
5054  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser5; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER5 */
5055  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser6; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER6 */
5056  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser7; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER7 */
5057  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser8; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER8 */
5058  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser9; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER9 */
5059  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser10; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER10 */
5060  volatile uint32_t LLI_Targ_Svc_LLI_User_GenUser11; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENUSER11 */
5061  volatile uint32_t _pad_0x130_0x17f[20]; /* *UNDEFINED* */
5062  volatile uint32_t LLI_Targ_Svc_LLI_User_GenSecurity0; /* ALT_PSI_LLI_USER_LLI_TARG_SVC_LLI_USER_GENSECURITY0 */
5063  volatile uint32_t _pad_0x184_0x1000[927]; /* *UNDEFINED* */
5064 };
5065 
5066 /* The typedef declaration for the raw register contents of register group ALT_PSI_LLI_USER. */
5067 typedef struct ALT_PSI_LLI_USER_raw_s ALT_PSI_LLI_USER_raw_t;
5068 #endif /* __ASSEMBLY__ */
5069 
5070 
5071 /*
5072  * Component : PSI_SIG
5073  *
5074  */
5075 /*
5076  * Register : LLI_Targ_Svc_SIG_sig_reg_num
5077  *
5078  * Register Layout
5079  *
5080  * Bits | Access | Reset | Description
5081  * :-------|:-------|:------|:-----------------------------------------------------
5082  * [31:0] | R | 0x20 | ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM
5083  *
5084  */
5085 /*
5086  * Field : SIG_REG_NUM
5087  *
5088  * Number of LLI signal attributes; (Capability)
5089  *
5090  * Field Access Macros:
5091  *
5092  */
5093 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field. */
5094 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_LSB 0
5095 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field. */
5096 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_MSB 31
5097 /* The width in bits of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field. */
5098 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_WIDTH 32
5099 /* The mask used to set the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field value. */
5100 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_SET_MSK 0xffffffff
5101 /* The mask used to clear the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field value. */
5102 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_CLR_MSK 0x00000000
5103 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field. */
5104 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_RESET 0x20
5105 /* Extracts the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM field value from a register. */
5106 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_GET(value) (((value) & 0xffffffff) >> 0)
5107 /* Produces a ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM register field value suitable for setting the register. */
5108 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM_SET(value) (((value) << 0) & 0xffffffff)
5109 
5110 #ifndef __ASSEMBLY__
5111 /*
5112  * WARNING: The C register and register group struct declarations are provided for
5113  * convenience and illustrative purposes. They should, however, be used with
5114  * caution as the C language standard provides no guarantees about the alignment or
5115  * atomicity of device memory accesses. The recommended practice for writing
5116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5117  * alt_write_word() functions.
5118  *
5119  * The struct declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM.
5120  */
5121 struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_s
5122 {
5123  const volatile uint32_t SIG_REG_NUM : 32; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_SIG_REG_NUM */
5124 };
5125 
5126 /* The typedef declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM. */
5127 typedef struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_s ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_t;
5128 #endif /* __ASSEMBLY__ */
5129 
5130 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM register. */
5131 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_RESET 0x00000020
5132 /* The byte offset of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM register from the beginning of the component. */
5133 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_OFST 0x0
5134 
5135 /*
5136  * Register : LLI_Targ_Svc_SIG_Signal_Status
5137  *
5138  * Register Layout
5139  *
5140  * Bits | Access | Reset | Description
5141  * :-------|:-------|:------|:---------------------------------------------------------
5142  * [31:0] | R | 0x0 | ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS
5143  *
5144  */
5145 /*
5146  * Field : SIGNAL_STATUS
5147  *
5148  * Get the status of signals.
5149  *
5150  * Field Access Macros:
5151  *
5152  */
5153 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field. */
5154 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_LSB 0
5155 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field. */
5156 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_MSB 31
5157 /* The width in bits of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field. */
5158 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_WIDTH 32
5159 /* The mask used to set the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field value. */
5160 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_SET_MSK 0xffffffff
5161 /* The mask used to clear the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field value. */
5162 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_CLR_MSK 0x00000000
5163 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field. */
5164 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_RESET 0x0
5165 /* Extracts the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS field value from a register. */
5166 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_GET(value) (((value) & 0xffffffff) >> 0)
5167 /* Produces a ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS register field value suitable for setting the register. */
5168 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS_SET(value) (((value) << 0) & 0xffffffff)
5169 
5170 #ifndef __ASSEMBLY__
5171 /*
5172  * WARNING: The C register and register group struct declarations are provided for
5173  * convenience and illustrative purposes. They should, however, be used with
5174  * caution as the C language standard provides no guarantees about the alignment or
5175  * atomicity of device memory accesses. The recommended practice for writing
5176  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5177  * alt_write_word() functions.
5178  *
5179  * The struct declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS.
5180  */
5181 struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_s
5182 {
5183  const volatile uint32_t SIGNAL_STATUS : 32; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_SIGNAL_STATUS */
5184 };
5185 
5186 /* The typedef declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS. */
5187 typedef struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_s ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_t;
5188 #endif /* __ASSEMBLY__ */
5189 
5190 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS register. */
5191 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_RESET 0x00000000
5192 /* The byte offset of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS register from the beginning of the component. */
5193 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_OFST 0x4
5194 
5195 /*
5196  * Register : LLI_Targ_Svc_SIG_Signal_Set
5197  *
5198  * Register Layout
5199  *
5200  * Bits | Access | Reset | Description
5201  * :-------|:-------|:------|:---------------------------------------------------
5202  * [31:0] | RW | 0x0 | ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET
5203  *
5204  */
5205 /*
5206  * Field : SIGNAL_SET
5207  *
5208  * Sets signals. Writing a bit to '1' sets the corresponding signal; Writing '0'
5209  * has no effect. If read, then returns '0'.
5210  *
5211  * Field Access Macros:
5212  *
5213  */
5214 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field. */
5215 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_LSB 0
5216 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field. */
5217 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_MSB 31
5218 /* The width in bits of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field. */
5219 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_WIDTH 32
5220 /* The mask used to set the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field value. */
5221 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_SET_MSK 0xffffffff
5222 /* The mask used to clear the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field value. */
5223 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_CLR_MSK 0x00000000
5224 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field. */
5225 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_RESET 0x0
5226 /* Extracts the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET field value from a register. */
5227 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_GET(value) (((value) & 0xffffffff) >> 0)
5228 /* Produces a ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET register field value suitable for setting the register. */
5229 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET_SET(value) (((value) << 0) & 0xffffffff)
5230 
5231 #ifndef __ASSEMBLY__
5232 /*
5233  * WARNING: The C register and register group struct declarations are provided for
5234  * convenience and illustrative purposes. They should, however, be used with
5235  * caution as the C language standard provides no guarantees about the alignment or
5236  * atomicity of device memory accesses. The recommended practice for writing
5237  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5238  * alt_write_word() functions.
5239  *
5240  * The struct declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET.
5241  */
5242 struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_s
5243 {
5244  volatile uint32_t SIGNAL_SET : 32; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_SIGNAL_SET */
5245 };
5246 
5247 /* The typedef declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET. */
5248 typedef struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_s ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_t;
5249 #endif /* __ASSEMBLY__ */
5250 
5251 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET register. */
5252 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_RESET 0x00000000
5253 /* The byte offset of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET register from the beginning of the component. */
5254 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_OFST 0x8
5255 
5256 /*
5257  * Register : LLI_Targ_Svc_SIG_Signal_Clear
5258  *
5259  * Register Layout
5260  *
5261  * Bits | Access | Reset | Description
5262  * :-------|:-------|:------|:-------------------------------------------------------
5263  * [31:0] | RW | 0x0 | ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR
5264  *
5265  */
5266 /*
5267  * Field : SIGNAL_CLEAR
5268  *
5269  * Clears signals. Writing a bit to '1' clears the corresponding signal; Writing
5270  * '0' has no effect. If read, then returns '0'.
5271  *
5272  * Field Access Macros:
5273  *
5274  */
5275 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field. */
5276 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_LSB 0
5277 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field. */
5278 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_MSB 31
5279 /* The width in bits of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field. */
5280 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_WIDTH 32
5281 /* The mask used to set the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field value. */
5282 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_SET_MSK 0xffffffff
5283 /* The mask used to clear the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field value. */
5284 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_CLR_MSK 0x00000000
5285 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field. */
5286 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_RESET 0x0
5287 /* Extracts the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR field value from a register. */
5288 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_GET(value) (((value) & 0xffffffff) >> 0)
5289 /* Produces a ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR register field value suitable for setting the register. */
5290 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR_SET(value) (((value) << 0) & 0xffffffff)
5291 
5292 #ifndef __ASSEMBLY__
5293 /*
5294  * WARNING: The C register and register group struct declarations are provided for
5295  * convenience and illustrative purposes. They should, however, be used with
5296  * caution as the C language standard provides no guarantees about the alignment or
5297  * atomicity of device memory accesses. The recommended practice for writing
5298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5299  * alt_write_word() functions.
5300  *
5301  * The struct declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR.
5302  */
5303 struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_s
5304 {
5305  volatile uint32_t SIGNAL_CLEAR : 32; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_SIGNAL_CLEAR */
5306 };
5307 
5308 /* The typedef declaration for register ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR. */
5309 typedef struct ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_s ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_t;
5310 #endif /* __ASSEMBLY__ */
5311 
5312 /* The reset value of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR register. */
5313 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_RESET 0x00000000
5314 /* The byte offset of the ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR register from the beginning of the component. */
5315 #define ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_OFST 0xc
5316 
5317 #ifndef __ASSEMBLY__
5318 /*
5319  * WARNING: The C register and register group struct declarations are provided for
5320  * convenience and illustrative purposes. They should, however, be used with
5321  * caution as the C language standard provides no guarantees about the alignment or
5322  * atomicity of device memory accesses. The recommended practice for writing
5323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5324  * alt_write_word() functions.
5325  *
5326  * The struct declaration for register group ALT_PSI_SIG.
5327  */
5328 struct ALT_PSI_SIG_s
5329 {
5330  volatile ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM_t LLI_Targ_Svc_SIG_sig_reg_num; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM */
5331  volatile ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS_t LLI_Targ_Svc_SIG_Signal_Status; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS */
5332  volatile ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET_t LLI_Targ_Svc_SIG_Signal_Set; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET */
5333  volatile ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR_t LLI_Targ_Svc_SIG_Signal_Clear; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR */
5334  volatile uint32_t _pad_0x10_0x200[124]; /* *UNDEFINED* */
5335 };
5336 
5337 /* The typedef declaration for register group ALT_PSI_SIG. */
5338 typedef struct ALT_PSI_SIG_s ALT_PSI_SIG_t;
5339 /* The struct declaration for the raw register contents of register group ALT_PSI_SIG. */
5340 struct ALT_PSI_SIG_raw_s
5341 {
5342  volatile uint32_t LLI_Targ_Svc_SIG_sig_reg_num; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIG_REG_NUM */
5343  volatile uint32_t LLI_Targ_Svc_SIG_Signal_Status; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_STATUS */
5344  volatile uint32_t LLI_Targ_Svc_SIG_Signal_Set; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_SET */
5345  volatile uint32_t LLI_Targ_Svc_SIG_Signal_Clear; /* ALT_PSI_SIG_LLI_TARG_SVC_SIG_SIGNAL_CLEAR */
5346  volatile uint32_t _pad_0x10_0x200[124]; /* *UNDEFINED* */
5347 };
5348 
5349 /* The typedef declaration for the raw register contents of register group ALT_PSI_SIG. */
5350 typedef struct ALT_PSI_SIG_raw_s ALT_PSI_SIG_raw_t;
5351 #endif /* __ASSEMBLY__ */
5352 
5353 
5354 /*
5355  * Component : PSI_SIG_USER
5356  *
5357  */
5358 /*
5359  * Register : LLI_Targ_Svc_SIG_User_SigIn
5360  *
5361  * Register Layout
5362  *
5363  * Bits | Access | Reset | Description
5364  * :-------|:-------|:--------|:---------------------------------------------------
5365  * [31:0] | R | Unknown | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN
5366  *
5367  */
5368 /*
5369  * Field : SIGIN
5370  *
5371  * Contains the value of the re-synchronized version of the SigIn input.
5372  *
5373  * Field Access Macros:
5374  *
5375  */
5376 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field. */
5377 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_LSB 0
5378 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field. */
5379 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_MSB 31
5380 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field. */
5381 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_WIDTH 32
5382 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field value. */
5383 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_SET_MSK 0xffffffff
5384 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field value. */
5385 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_CLR_MSK 0x00000000
5386 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field is UNKNOWN. */
5387 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_RESET 0x0
5388 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN field value from a register. */
5389 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_GET(value) (((value) & 0xffffffff) >> 0)
5390 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN register field value suitable for setting the register. */
5391 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN_SET(value) (((value) << 0) & 0xffffffff)
5392 
5393 #ifndef __ASSEMBLY__
5394 /*
5395  * WARNING: The C register and register group struct declarations are provided for
5396  * convenience and illustrative purposes. They should, however, be used with
5397  * caution as the C language standard provides no guarantees about the alignment or
5398  * atomicity of device memory accesses. The recommended practice for writing
5399  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5400  * alt_write_word() functions.
5401  *
5402  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN.
5403  */
5404 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_s
5405 {
5406  const volatile uint32_t SIGIN : 32; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_SIGIN */
5407 };
5408 
5409 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN. */
5410 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_t;
5411 #endif /* __ASSEMBLY__ */
5412 
5413 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN register. */
5414 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_RESET 0x00000000
5415 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN register from the beginning of the component. */
5416 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_OFST 0x0
5417 
5418 /*
5419  * Register : LLI_Targ_Svc_SIG_User_PowerCtl
5420  *
5421  * This register controls the Generic Master disconnect.
5422  *
5423  * Register Layout
5424  *
5425  * Bits | Access | Reset | Description
5426  * :-------|:-------|:--------|:--------------------------------------------------------
5427  * [0] | RW | 0x1 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ
5428  * [1] | R | Unknown | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK
5429  * [31:2] | ??? | Unknown | *UNDEFINED*
5430  *
5431  */
5432 /*
5433  * Field : IDLEREQ
5434  *
5435  * Stop Generic Master traffic request.
5436  *
5437  * Field Access Macros:
5438  *
5439  */
5440 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field. */
5441 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_LSB 0
5442 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field. */
5443 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_MSB 0
5444 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field. */
5445 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_WIDTH 1
5446 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field value. */
5447 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_SET_MSK 0x00000001
5448 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field value. */
5449 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_CLR_MSK 0xfffffffe
5450 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field. */
5451 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_RESET 0x1
5452 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ field value from a register. */
5453 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_GET(value) (((value) & 0x00000001) >> 0)
5454 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ register field value suitable for setting the register. */
5455 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ_SET(value) (((value) << 0) & 0x00000001)
5456 
5457 /*
5458  * Field : IDLEACK
5459  *
5460  * Generic Master Stopped.
5461  *
5462  * Field Access Macros:
5463  *
5464  */
5465 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field. */
5466 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_LSB 1
5467 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field. */
5468 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_MSB 1
5469 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field. */
5470 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_WIDTH 1
5471 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field value. */
5472 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_SET_MSK 0x00000002
5473 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field value. */
5474 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_CLR_MSK 0xfffffffd
5475 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field is UNKNOWN. */
5476 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_RESET 0x0
5477 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK field value from a register. */
5478 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_GET(value) (((value) & 0x00000002) >> 1)
5479 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK register field value suitable for setting the register. */
5480 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK_SET(value) (((value) << 1) & 0x00000002)
5481 
5482 #ifndef __ASSEMBLY__
5483 /*
5484  * WARNING: The C register and register group struct declarations are provided for
5485  * convenience and illustrative purposes. They should, however, be used with
5486  * caution as the C language standard provides no guarantees about the alignment or
5487  * atomicity of device memory accesses. The recommended practice for writing
5488  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5489  * alt_write_word() functions.
5490  *
5491  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL.
5492  */
5493 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_s
5494 {
5495  volatile uint32_t IDLEREQ : 1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEREQ */
5496  const volatile uint32_t IDLEACK : 1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_IDLEACK */
5497  uint32_t : 30; /* *UNDEFINED* */
5498 };
5499 
5500 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL. */
5501 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_t;
5502 #endif /* __ASSEMBLY__ */
5503 
5504 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL register. */
5505 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_RESET 0x00000001
5506 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL register from the beginning of the component. */
5507 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_OFST 0x18
5508 
5509 /*
5510  * Register : LLI_Targ_Svc_SIG_User_FaultCtl
5511  *
5512  * This register contains the Status and the Clear of the Fault signal.
5513  *
5514  * Register Layout
5515  *
5516  * Bits | Access | Reset | Description
5517  * :-------|:-------|:--------|:-------------------------------------------------------
5518  * [0] | R | 0x0 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS
5519  * [1] | RW | 0x0 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR
5520  * [31:2] | ??? | Unknown | *UNDEFINED*
5521  *
5522  */
5523 /*
5524  * Field : STATUS
5525  *
5526  * Value of the Fault output signal.
5527  *
5528  * Field Access Macros:
5529  *
5530  */
5531 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field. */
5532 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_LSB 0
5533 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field. */
5534 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_MSB 0
5535 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field. */
5536 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_WIDTH 1
5537 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field value. */
5538 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_SET_MSK 0x00000001
5539 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field value. */
5540 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_CLR_MSK 0xfffffffe
5541 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field. */
5542 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_RESET 0x0
5543 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS field value from a register. */
5544 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_GET(value) (((value) & 0x00000001) >> 0)
5545 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS register field value suitable for setting the register. */
5546 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS_SET(value) (((value) << 0) & 0x00000001)
5547 
5548 /*
5549  * Field : CLR
5550  *
5551  * Clear Fault signal.
5552  *
5553  * Field Access Macros:
5554  *
5555  */
5556 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field. */
5557 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_LSB 1
5558 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field. */
5559 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_MSB 1
5560 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field. */
5561 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_WIDTH 1
5562 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field value. */
5563 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_SET_MSK 0x00000002
5564 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field value. */
5565 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_CLR_MSK 0xfffffffd
5566 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field. */
5567 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_RESET 0x0
5568 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR field value from a register. */
5569 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_GET(value) (((value) & 0x00000002) >> 1)
5570 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR register field value suitable for setting the register. */
5571 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR_SET(value) (((value) << 1) & 0x00000002)
5572 
5573 #ifndef __ASSEMBLY__
5574 /*
5575  * WARNING: The C register and register group struct declarations are provided for
5576  * convenience and illustrative purposes. They should, however, be used with
5577  * caution as the C language standard provides no guarantees about the alignment or
5578  * atomicity of device memory accesses. The recommended practice for writing
5579  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5580  * alt_write_word() functions.
5581  *
5582  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL.
5583  */
5584 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_s
5585 {
5586  const volatile uint32_t STATUS : 1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_STATUS */
5587  volatile uint32_t CLR : 1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_CLR */
5588  uint32_t : 30; /* *UNDEFINED* */
5589 };
5590 
5591 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL. */
5592 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_t;
5593 #endif /* __ASSEMBLY__ */
5594 
5595 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL register. */
5596 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_RESET 0x00000000
5597 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL register from the beginning of the component. */
5598 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_OFST 0x1c
5599 
5600 /*
5601  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc0
5602  *
5603  * Register Layout
5604  *
5605  * Bits | Access | Reset | Description
5606  * :-------|:-------|:--------|:-------------------------------------------------------------
5607  * [5:0] | RW | 0x0 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0
5608  * [31:6] | ??? | Unknown | *UNDEFINED*
5609  *
5610  */
5611 /*
5612  * Field : SIGOUTSRC0
5613  *
5614  * This 6 bits register selects the Signal_Status bit that will be connected to the
5615  * SigOut bit 0. Each register (r) uses the following value (v) encoding. 0x00 to
5616  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5617  *
5618  * Field Access Macros:
5619  *
5620  */
5621 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field. */
5622 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_LSB 0
5623 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field. */
5624 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_MSB 5
5625 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field. */
5626 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_WIDTH 6
5627 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field value. */
5628 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_SET_MSK 0x0000003f
5629 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field value. */
5630 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_CLR_MSK 0xffffffc0
5631 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field. */
5632 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_RESET 0x0
5633 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 field value from a register. */
5634 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_GET(value) (((value) & 0x0000003f) >> 0)
5635 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 register field value suitable for setting the register. */
5636 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0_SET(value) (((value) << 0) & 0x0000003f)
5637 
5638 #ifndef __ASSEMBLY__
5639 /*
5640  * WARNING: The C register and register group struct declarations are provided for
5641  * convenience and illustrative purposes. They should, however, be used with
5642  * caution as the C language standard provides no guarantees about the alignment or
5643  * atomicity of device memory accesses. The recommended practice for writing
5644  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5645  * alt_write_word() functions.
5646  *
5647  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0.
5648  */
5649 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_s
5650 {
5651  volatile uint32_t SIGOUTSRC0 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_SIGOUTSRC0 */
5652  uint32_t : 26; /* *UNDEFINED* */
5653 };
5654 
5655 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0. */
5656 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_t;
5657 #endif /* __ASSEMBLY__ */
5658 
5659 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0 register. */
5660 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_RESET 0x00000000
5661 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0 register from the beginning of the component. */
5662 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_OFST 0x20
5663 
5664 /*
5665  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc1
5666  *
5667  * Register Layout
5668  *
5669  * Bits | Access | Reset | Description
5670  * :-------|:-------|:--------|:-------------------------------------------------------------
5671  * [5:0] | RW | 0x1 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1
5672  * [31:6] | ??? | Unknown | *UNDEFINED*
5673  *
5674  */
5675 /*
5676  * Field : SIGOUTSRC1
5677  *
5678  * This 6 bits register selects the Signal_Status bit that will be connected to the
5679  * SigOut bit 1. Each register (r) uses the following value (v) encoding. 0x00 to
5680  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5681  *
5682  * Field Access Macros:
5683  *
5684  */
5685 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field. */
5686 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_LSB 0
5687 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field. */
5688 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_MSB 5
5689 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field. */
5690 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_WIDTH 6
5691 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field value. */
5692 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_SET_MSK 0x0000003f
5693 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field value. */
5694 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_CLR_MSK 0xffffffc0
5695 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field. */
5696 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_RESET 0x1
5697 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 field value from a register. */
5698 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_GET(value) (((value) & 0x0000003f) >> 0)
5699 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 register field value suitable for setting the register. */
5700 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1_SET(value) (((value) << 0) & 0x0000003f)
5701 
5702 #ifndef __ASSEMBLY__
5703 /*
5704  * WARNING: The C register and register group struct declarations are provided for
5705  * convenience and illustrative purposes. They should, however, be used with
5706  * caution as the C language standard provides no guarantees about the alignment or
5707  * atomicity of device memory accesses. The recommended practice for writing
5708  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5709  * alt_write_word() functions.
5710  *
5711  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1.
5712  */
5713 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_s
5714 {
5715  volatile uint32_t SIGOUTSRC1 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_SIGOUTSRC1 */
5716  uint32_t : 26; /* *UNDEFINED* */
5717 };
5718 
5719 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1. */
5720 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_t;
5721 #endif /* __ASSEMBLY__ */
5722 
5723 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1 register. */
5724 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_RESET 0x00000001
5725 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1 register from the beginning of the component. */
5726 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_OFST 0x24
5727 
5728 /*
5729  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc2
5730  *
5731  * Register Layout
5732  *
5733  * Bits | Access | Reset | Description
5734  * :-------|:-------|:--------|:-------------------------------------------------------------
5735  * [5:0] | RW | 0x2 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2
5736  * [31:6] | ??? | Unknown | *UNDEFINED*
5737  *
5738  */
5739 /*
5740  * Field : SIGOUTSRC2
5741  *
5742  * This 6 bits register selects the Signal_Status bit that will be connected to the
5743  * SigOut bit 2. Each register (r) uses the following value (v) encoding. 0x00 to
5744  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5745  *
5746  * Field Access Macros:
5747  *
5748  */
5749 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field. */
5750 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_LSB 0
5751 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field. */
5752 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_MSB 5
5753 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field. */
5754 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_WIDTH 6
5755 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field value. */
5756 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_SET_MSK 0x0000003f
5757 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field value. */
5758 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_CLR_MSK 0xffffffc0
5759 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field. */
5760 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_RESET 0x2
5761 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 field value from a register. */
5762 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_GET(value) (((value) & 0x0000003f) >> 0)
5763 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 register field value suitable for setting the register. */
5764 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2_SET(value) (((value) << 0) & 0x0000003f)
5765 
5766 #ifndef __ASSEMBLY__
5767 /*
5768  * WARNING: The C register and register group struct declarations are provided for
5769  * convenience and illustrative purposes. They should, however, be used with
5770  * caution as the C language standard provides no guarantees about the alignment or
5771  * atomicity of device memory accesses. The recommended practice for writing
5772  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5773  * alt_write_word() functions.
5774  *
5775  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2.
5776  */
5777 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_s
5778 {
5779  volatile uint32_t SIGOUTSRC2 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_SIGOUTSRC2 */
5780  uint32_t : 26; /* *UNDEFINED* */
5781 };
5782 
5783 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2. */
5784 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_t;
5785 #endif /* __ASSEMBLY__ */
5786 
5787 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2 register. */
5788 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_RESET 0x00000002
5789 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2 register from the beginning of the component. */
5790 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_OFST 0x28
5791 
5792 /*
5793  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc3
5794  *
5795  * Register Layout
5796  *
5797  * Bits | Access | Reset | Description
5798  * :-------|:-------|:--------|:-------------------------------------------------------------
5799  * [5:0] | RW | 0x3 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3
5800  * [31:6] | ??? | Unknown | *UNDEFINED*
5801  *
5802  */
5803 /*
5804  * Field : SIGOUTSRC3
5805  *
5806  * This 6 bits register selects the Signal_Status bit that will be connected to the
5807  * SigOut bit 3. Each register (r) uses the following value (v) encoding. 0x00 to
5808  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5809  *
5810  * Field Access Macros:
5811  *
5812  */
5813 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field. */
5814 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_LSB 0
5815 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field. */
5816 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_MSB 5
5817 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field. */
5818 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_WIDTH 6
5819 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field value. */
5820 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_SET_MSK 0x0000003f
5821 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field value. */
5822 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_CLR_MSK 0xffffffc0
5823 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field. */
5824 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_RESET 0x3
5825 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 field value from a register. */
5826 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_GET(value) (((value) & 0x0000003f) >> 0)
5827 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 register field value suitable for setting the register. */
5828 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3_SET(value) (((value) << 0) & 0x0000003f)
5829 
5830 #ifndef __ASSEMBLY__
5831 /*
5832  * WARNING: The C register and register group struct declarations are provided for
5833  * convenience and illustrative purposes. They should, however, be used with
5834  * caution as the C language standard provides no guarantees about the alignment or
5835  * atomicity of device memory accesses. The recommended practice for writing
5836  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5837  * alt_write_word() functions.
5838  *
5839  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3.
5840  */
5841 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_s
5842 {
5843  volatile uint32_t SIGOUTSRC3 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_SIGOUTSRC3 */
5844  uint32_t : 26; /* *UNDEFINED* */
5845 };
5846 
5847 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3. */
5848 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_t;
5849 #endif /* __ASSEMBLY__ */
5850 
5851 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3 register. */
5852 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_RESET 0x00000003
5853 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3 register from the beginning of the component. */
5854 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_OFST 0x2c
5855 
5856 /*
5857  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc4
5858  *
5859  * Register Layout
5860  *
5861  * Bits | Access | Reset | Description
5862  * :-------|:-------|:--------|:-------------------------------------------------------------
5863  * [5:0] | RW | 0x4 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4
5864  * [31:6] | ??? | Unknown | *UNDEFINED*
5865  *
5866  */
5867 /*
5868  * Field : SIGOUTSRC4
5869  *
5870  * This 6 bits register selects the Signal_Status bit that will be connected to the
5871  * SigOut bit 4. Each register (r) uses the following value (v) encoding. 0x00 to
5872  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5873  *
5874  * Field Access Macros:
5875  *
5876  */
5877 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field. */
5878 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_LSB 0
5879 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field. */
5880 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_MSB 5
5881 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field. */
5882 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_WIDTH 6
5883 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field value. */
5884 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_SET_MSK 0x0000003f
5885 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field value. */
5886 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_CLR_MSK 0xffffffc0
5887 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field. */
5888 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_RESET 0x4
5889 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 field value from a register. */
5890 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_GET(value) (((value) & 0x0000003f) >> 0)
5891 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 register field value suitable for setting the register. */
5892 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4_SET(value) (((value) << 0) & 0x0000003f)
5893 
5894 #ifndef __ASSEMBLY__
5895 /*
5896  * WARNING: The C register and register group struct declarations are provided for
5897  * convenience and illustrative purposes. They should, however, be used with
5898  * caution as the C language standard provides no guarantees about the alignment or
5899  * atomicity of device memory accesses. The recommended practice for writing
5900  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5901  * alt_write_word() functions.
5902  *
5903  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4.
5904  */
5905 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_s
5906 {
5907  volatile uint32_t SIGOUTSRC4 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_SIGOUTSRC4 */
5908  uint32_t : 26; /* *UNDEFINED* */
5909 };
5910 
5911 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4. */
5912 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_t;
5913 #endif /* __ASSEMBLY__ */
5914 
5915 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4 register. */
5916 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_RESET 0x00000004
5917 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4 register from the beginning of the component. */
5918 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_OFST 0x30
5919 
5920 /*
5921  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc5
5922  *
5923  * Register Layout
5924  *
5925  * Bits | Access | Reset | Description
5926  * :-------|:-------|:--------|:-------------------------------------------------------------
5927  * [5:0] | RW | 0x5 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5
5928  * [31:6] | ??? | Unknown | *UNDEFINED*
5929  *
5930  */
5931 /*
5932  * Field : SIGOUTSRC5
5933  *
5934  * This 6 bits register selects the Signal_Status bit that will be connected to the
5935  * SigOut bit 5. Each register (r) uses the following value (v) encoding. 0x00 to
5936  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
5937  *
5938  * Field Access Macros:
5939  *
5940  */
5941 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field. */
5942 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_LSB 0
5943 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field. */
5944 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_MSB 5
5945 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field. */
5946 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_WIDTH 6
5947 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field value. */
5948 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_SET_MSK 0x0000003f
5949 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field value. */
5950 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_CLR_MSK 0xffffffc0
5951 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field. */
5952 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_RESET 0x5
5953 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 field value from a register. */
5954 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_GET(value) (((value) & 0x0000003f) >> 0)
5955 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 register field value suitable for setting the register. */
5956 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5_SET(value) (((value) << 0) & 0x0000003f)
5957 
5958 #ifndef __ASSEMBLY__
5959 /*
5960  * WARNING: The C register and register group struct declarations are provided for
5961  * convenience and illustrative purposes. They should, however, be used with
5962  * caution as the C language standard provides no guarantees about the alignment or
5963  * atomicity of device memory accesses. The recommended practice for writing
5964  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5965  * alt_write_word() functions.
5966  *
5967  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5.
5968  */
5969 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_s
5970 {
5971  volatile uint32_t SIGOUTSRC5 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_SIGOUTSRC5 */
5972  uint32_t : 26; /* *UNDEFINED* */
5973 };
5974 
5975 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5. */
5976 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_t;
5977 #endif /* __ASSEMBLY__ */
5978 
5979 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5 register. */
5980 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_RESET 0x00000005
5981 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5 register from the beginning of the component. */
5982 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_OFST 0x34
5983 
5984 /*
5985  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc6
5986  *
5987  * Register Layout
5988  *
5989  * Bits | Access | Reset | Description
5990  * :-------|:-------|:--------|:-------------------------------------------------------------
5991  * [5:0] | RW | 0x6 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6
5992  * [31:6] | ??? | Unknown | *UNDEFINED*
5993  *
5994  */
5995 /*
5996  * Field : SIGOUTSRC6
5997  *
5998  * This 6 bits register selects the Signal_Status bit that will be connected to the
5999  * SigOut bit 6. Each register (r) uses the following value (v) encoding. 0x00 to
6000  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6001  *
6002  * Field Access Macros:
6003  *
6004  */
6005 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field. */
6006 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_LSB 0
6007 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field. */
6008 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_MSB 5
6009 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field. */
6010 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_WIDTH 6
6011 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field value. */
6012 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_SET_MSK 0x0000003f
6013 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field value. */
6014 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_CLR_MSK 0xffffffc0
6015 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field. */
6016 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_RESET 0x6
6017 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 field value from a register. */
6018 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_GET(value) (((value) & 0x0000003f) >> 0)
6019 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 register field value suitable for setting the register. */
6020 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6_SET(value) (((value) << 0) & 0x0000003f)
6021 
6022 #ifndef __ASSEMBLY__
6023 /*
6024  * WARNING: The C register and register group struct declarations are provided for
6025  * convenience and illustrative purposes. They should, however, be used with
6026  * caution as the C language standard provides no guarantees about the alignment or
6027  * atomicity of device memory accesses. The recommended practice for writing
6028  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6029  * alt_write_word() functions.
6030  *
6031  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6.
6032  */
6033 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_s
6034 {
6035  volatile uint32_t SIGOUTSRC6 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_SIGOUTSRC6 */
6036  uint32_t : 26; /* *UNDEFINED* */
6037 };
6038 
6039 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6. */
6040 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_t;
6041 #endif /* __ASSEMBLY__ */
6042 
6043 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6 register. */
6044 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_RESET 0x00000006
6045 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6 register from the beginning of the component. */
6046 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_OFST 0x38
6047 
6048 /*
6049  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc7
6050  *
6051  * Register Layout
6052  *
6053  * Bits | Access | Reset | Description
6054  * :-------|:-------|:--------|:-------------------------------------------------------------
6055  * [5:0] | RW | 0x7 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7
6056  * [31:6] | ??? | Unknown | *UNDEFINED*
6057  *
6058  */
6059 /*
6060  * Field : SIGOUTSRC7
6061  *
6062  * This 6 bits register selects the Signal_Status bit that will be connected to the
6063  * SigOut bit 7. Each register (r) uses the following value (v) encoding. 0x00 to
6064  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6065  *
6066  * Field Access Macros:
6067  *
6068  */
6069 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field. */
6070 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_LSB 0
6071 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field. */
6072 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_MSB 5
6073 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field. */
6074 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_WIDTH 6
6075 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field value. */
6076 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_SET_MSK 0x0000003f
6077 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field value. */
6078 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_CLR_MSK 0xffffffc0
6079 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field. */
6080 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_RESET 0x7
6081 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 field value from a register. */
6082 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_GET(value) (((value) & 0x0000003f) >> 0)
6083 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 register field value suitable for setting the register. */
6084 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7_SET(value) (((value) << 0) & 0x0000003f)
6085 
6086 #ifndef __ASSEMBLY__
6087 /*
6088  * WARNING: The C register and register group struct declarations are provided for
6089  * convenience and illustrative purposes. They should, however, be used with
6090  * caution as the C language standard provides no guarantees about the alignment or
6091  * atomicity of device memory accesses. The recommended practice for writing
6092  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6093  * alt_write_word() functions.
6094  *
6095  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7.
6096  */
6097 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_s
6098 {
6099  volatile uint32_t SIGOUTSRC7 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_SIGOUTSRC7 */
6100  uint32_t : 26; /* *UNDEFINED* */
6101 };
6102 
6103 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7. */
6104 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_t;
6105 #endif /* __ASSEMBLY__ */
6106 
6107 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7 register. */
6108 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_RESET 0x00000007
6109 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7 register from the beginning of the component. */
6110 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_OFST 0x3c
6111 
6112 /*
6113  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc8
6114  *
6115  * Register Layout
6116  *
6117  * Bits | Access | Reset | Description
6118  * :-------|:-------|:--------|:-------------------------------------------------------------
6119  * [5:0] | RW | 0x8 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8
6120  * [31:6] | ??? | Unknown | *UNDEFINED*
6121  *
6122  */
6123 /*
6124  * Field : SIGOUTSRC8
6125  *
6126  * This 6 bits register selects the Signal_Status bit that will be connected to the
6127  * SigOut bit 8. Each register (r) uses the following value (v) encoding. 0x00 to
6128  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6129  *
6130  * Field Access Macros:
6131  *
6132  */
6133 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field. */
6134 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_LSB 0
6135 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field. */
6136 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_MSB 5
6137 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field. */
6138 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_WIDTH 6
6139 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field value. */
6140 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_SET_MSK 0x0000003f
6141 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field value. */
6142 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_CLR_MSK 0xffffffc0
6143 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field. */
6144 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_RESET 0x8
6145 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 field value from a register. */
6146 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_GET(value) (((value) & 0x0000003f) >> 0)
6147 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 register field value suitable for setting the register. */
6148 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8_SET(value) (((value) << 0) & 0x0000003f)
6149 
6150 #ifndef __ASSEMBLY__
6151 /*
6152  * WARNING: The C register and register group struct declarations are provided for
6153  * convenience and illustrative purposes. They should, however, be used with
6154  * caution as the C language standard provides no guarantees about the alignment or
6155  * atomicity of device memory accesses. The recommended practice for writing
6156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6157  * alt_write_word() functions.
6158  *
6159  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8.
6160  */
6161 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_s
6162 {
6163  volatile uint32_t SIGOUTSRC8 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_SIGOUTSRC8 */
6164  uint32_t : 26; /* *UNDEFINED* */
6165 };
6166 
6167 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8. */
6168 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_t;
6169 #endif /* __ASSEMBLY__ */
6170 
6171 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8 register. */
6172 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_RESET 0x00000008
6173 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8 register from the beginning of the component. */
6174 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_OFST 0x40
6175 
6176 /*
6177  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc9
6178  *
6179  * Register Layout
6180  *
6181  * Bits | Access | Reset | Description
6182  * :-------|:-------|:--------|:-------------------------------------------------------------
6183  * [5:0] | RW | 0x9 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9
6184  * [31:6] | ??? | Unknown | *UNDEFINED*
6185  *
6186  */
6187 /*
6188  * Field : SIGOUTSRC9
6189  *
6190  * This 6 bits register selects the Signal_Status bit that will be connected to the
6191  * SigOut bit 9. Each register (r) uses the following value (v) encoding. 0x00 to
6192  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6193  *
6194  * Field Access Macros:
6195  *
6196  */
6197 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field. */
6198 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_LSB 0
6199 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field. */
6200 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_MSB 5
6201 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field. */
6202 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_WIDTH 6
6203 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field value. */
6204 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_SET_MSK 0x0000003f
6205 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field value. */
6206 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_CLR_MSK 0xffffffc0
6207 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field. */
6208 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_RESET 0x9
6209 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 field value from a register. */
6210 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_GET(value) (((value) & 0x0000003f) >> 0)
6211 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 register field value suitable for setting the register. */
6212 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9_SET(value) (((value) << 0) & 0x0000003f)
6213 
6214 #ifndef __ASSEMBLY__
6215 /*
6216  * WARNING: The C register and register group struct declarations are provided for
6217  * convenience and illustrative purposes. They should, however, be used with
6218  * caution as the C language standard provides no guarantees about the alignment or
6219  * atomicity of device memory accesses. The recommended practice for writing
6220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6221  * alt_write_word() functions.
6222  *
6223  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9.
6224  */
6225 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_s
6226 {
6227  volatile uint32_t SIGOUTSRC9 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_SIGOUTSRC9 */
6228  uint32_t : 26; /* *UNDEFINED* */
6229 };
6230 
6231 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9. */
6232 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_t;
6233 #endif /* __ASSEMBLY__ */
6234 
6235 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9 register. */
6236 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_RESET 0x00000009
6237 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9 register from the beginning of the component. */
6238 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_OFST 0x44
6239 
6240 /*
6241  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc10
6242  *
6243  * Register Layout
6244  *
6245  * Bits | Access | Reset | Description
6246  * :-------|:-------|:--------|:---------------------------------------------------------------
6247  * [5:0] | RW | 0xa | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10
6248  * [31:6] | ??? | Unknown | *UNDEFINED*
6249  *
6250  */
6251 /*
6252  * Field : SIGOUTSRC10
6253  *
6254  * This 6 bits register selects the Signal_Status bit that will be connected to the
6255  * SigOut bit 10. Each register (r) uses the following value (v) encoding. 0x00 to
6256  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6257  *
6258  * Field Access Macros:
6259  *
6260  */
6261 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field. */
6262 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_LSB 0
6263 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field. */
6264 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_MSB 5
6265 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field. */
6266 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_WIDTH 6
6267 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field value. */
6268 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_SET_MSK 0x0000003f
6269 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field value. */
6270 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_CLR_MSK 0xffffffc0
6271 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field. */
6272 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_RESET 0xa
6273 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 field value from a register. */
6274 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_GET(value) (((value) & 0x0000003f) >> 0)
6275 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 register field value suitable for setting the register. */
6276 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10_SET(value) (((value) << 0) & 0x0000003f)
6277 
6278 #ifndef __ASSEMBLY__
6279 /*
6280  * WARNING: The C register and register group struct declarations are provided for
6281  * convenience and illustrative purposes. They should, however, be used with
6282  * caution as the C language standard provides no guarantees about the alignment or
6283  * atomicity of device memory accesses. The recommended practice for writing
6284  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6285  * alt_write_word() functions.
6286  *
6287  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10.
6288  */
6289 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_s
6290 {
6291  volatile uint32_t SIGOUTSRC10 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_SIGOUTSRC10 */
6292  uint32_t : 26; /* *UNDEFINED* */
6293 };
6294 
6295 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10. */
6296 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_t;
6297 #endif /* __ASSEMBLY__ */
6298 
6299 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10 register. */
6300 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_RESET 0x0000000a
6301 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10 register from the beginning of the component. */
6302 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_OFST 0x48
6303 
6304 /*
6305  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc11
6306  *
6307  * Register Layout
6308  *
6309  * Bits | Access | Reset | Description
6310  * :-------|:-------|:--------|:---------------------------------------------------------------
6311  * [5:0] | RW | 0xb | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11
6312  * [31:6] | ??? | Unknown | *UNDEFINED*
6313  *
6314  */
6315 /*
6316  * Field : SIGOUTSRC11
6317  *
6318  * This 6 bits register selects the Signal_Status bit that will be connected to the
6319  * SigOut bit 11. Each register (r) uses the following value (v) encoding. 0x00 to
6320  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6321  *
6322  * Field Access Macros:
6323  *
6324  */
6325 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field. */
6326 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_LSB 0
6327 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field. */
6328 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_MSB 5
6329 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field. */
6330 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_WIDTH 6
6331 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field value. */
6332 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_SET_MSK 0x0000003f
6333 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field value. */
6334 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_CLR_MSK 0xffffffc0
6335 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field. */
6336 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_RESET 0xb
6337 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 field value from a register. */
6338 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_GET(value) (((value) & 0x0000003f) >> 0)
6339 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 register field value suitable for setting the register. */
6340 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11_SET(value) (((value) << 0) & 0x0000003f)
6341 
6342 #ifndef __ASSEMBLY__
6343 /*
6344  * WARNING: The C register and register group struct declarations are provided for
6345  * convenience and illustrative purposes. They should, however, be used with
6346  * caution as the C language standard provides no guarantees about the alignment or
6347  * atomicity of device memory accesses. The recommended practice for writing
6348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6349  * alt_write_word() functions.
6350  *
6351  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11.
6352  */
6353 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_s
6354 {
6355  volatile uint32_t SIGOUTSRC11 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_SIGOUTSRC11 */
6356  uint32_t : 26; /* *UNDEFINED* */
6357 };
6358 
6359 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11. */
6360 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_t;
6361 #endif /* __ASSEMBLY__ */
6362 
6363 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11 register. */
6364 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_RESET 0x0000000b
6365 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11 register from the beginning of the component. */
6366 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_OFST 0x4c
6367 
6368 /*
6369  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc12
6370  *
6371  * Register Layout
6372  *
6373  * Bits | Access | Reset | Description
6374  * :-------|:-------|:--------|:---------------------------------------------------------------
6375  * [5:0] | RW | 0xc | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12
6376  * [31:6] | ??? | Unknown | *UNDEFINED*
6377  *
6378  */
6379 /*
6380  * Field : SIGOUTSRC12
6381  *
6382  * This 6 bits register selects the Signal_Status bit that will be connected to the
6383  * SigOut bit 12. Each register (r) uses the following value (v) encoding. 0x00 to
6384  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6385  *
6386  * Field Access Macros:
6387  *
6388  */
6389 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field. */
6390 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_LSB 0
6391 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field. */
6392 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_MSB 5
6393 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field. */
6394 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_WIDTH 6
6395 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field value. */
6396 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_SET_MSK 0x0000003f
6397 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field value. */
6398 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_CLR_MSK 0xffffffc0
6399 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field. */
6400 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_RESET 0xc
6401 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 field value from a register. */
6402 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_GET(value) (((value) & 0x0000003f) >> 0)
6403 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 register field value suitable for setting the register. */
6404 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12_SET(value) (((value) << 0) & 0x0000003f)
6405 
6406 #ifndef __ASSEMBLY__
6407 /*
6408  * WARNING: The C register and register group struct declarations are provided for
6409  * convenience and illustrative purposes. They should, however, be used with
6410  * caution as the C language standard provides no guarantees about the alignment or
6411  * atomicity of device memory accesses. The recommended practice for writing
6412  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6413  * alt_write_word() functions.
6414  *
6415  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12.
6416  */
6417 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_s
6418 {
6419  volatile uint32_t SIGOUTSRC12 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_SIGOUTSRC12 */
6420  uint32_t : 26; /* *UNDEFINED* */
6421 };
6422 
6423 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12. */
6424 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_t;
6425 #endif /* __ASSEMBLY__ */
6426 
6427 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12 register. */
6428 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_RESET 0x0000000c
6429 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12 register from the beginning of the component. */
6430 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_OFST 0x50
6431 
6432 /*
6433  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc13
6434  *
6435  * Register Layout
6436  *
6437  * Bits | Access | Reset | Description
6438  * :-------|:-------|:--------|:---------------------------------------------------------------
6439  * [5:0] | RW | 0xd | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13
6440  * [31:6] | ??? | Unknown | *UNDEFINED*
6441  *
6442  */
6443 /*
6444  * Field : SIGOUTSRC13
6445  *
6446  * This 6 bits register selects the Signal_Status bit that will be connected to the
6447  * SigOut bit 13. Each register (r) uses the following value (v) encoding. 0x00 to
6448  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6449  *
6450  * Field Access Macros:
6451  *
6452  */
6453 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field. */
6454 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_LSB 0
6455 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field. */
6456 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_MSB 5
6457 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field. */
6458 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_WIDTH 6
6459 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field value. */
6460 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_SET_MSK 0x0000003f
6461 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field value. */
6462 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_CLR_MSK 0xffffffc0
6463 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field. */
6464 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_RESET 0xd
6465 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 field value from a register. */
6466 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_GET(value) (((value) & 0x0000003f) >> 0)
6467 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 register field value suitable for setting the register. */
6468 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13_SET(value) (((value) << 0) & 0x0000003f)
6469 
6470 #ifndef __ASSEMBLY__
6471 /*
6472  * WARNING: The C register and register group struct declarations are provided for
6473  * convenience and illustrative purposes. They should, however, be used with
6474  * caution as the C language standard provides no guarantees about the alignment or
6475  * atomicity of device memory accesses. The recommended practice for writing
6476  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6477  * alt_write_word() functions.
6478  *
6479  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13.
6480  */
6481 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_s
6482 {
6483  volatile uint32_t SIGOUTSRC13 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_SIGOUTSRC13 */
6484  uint32_t : 26; /* *UNDEFINED* */
6485 };
6486 
6487 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13. */
6488 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_t;
6489 #endif /* __ASSEMBLY__ */
6490 
6491 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13 register. */
6492 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_RESET 0x0000000d
6493 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13 register from the beginning of the component. */
6494 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_OFST 0x54
6495 
6496 /*
6497  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc14
6498  *
6499  * Register Layout
6500  *
6501  * Bits | Access | Reset | Description
6502  * :-------|:-------|:--------|:---------------------------------------------------------------
6503  * [5:0] | RW | 0xe | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14
6504  * [31:6] | ??? | Unknown | *UNDEFINED*
6505  *
6506  */
6507 /*
6508  * Field : SIGOUTSRC14
6509  *
6510  * This 6 bits register selects the Signal_Status bit that will be connected to the
6511  * SigOut bit 14. Each register (r) uses the following value (v) encoding. 0x00 to
6512  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6513  *
6514  * Field Access Macros:
6515  *
6516  */
6517 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field. */
6518 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_LSB 0
6519 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field. */
6520 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_MSB 5
6521 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field. */
6522 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_WIDTH 6
6523 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field value. */
6524 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_SET_MSK 0x0000003f
6525 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field value. */
6526 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_CLR_MSK 0xffffffc0
6527 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field. */
6528 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_RESET 0xe
6529 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 field value from a register. */
6530 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_GET(value) (((value) & 0x0000003f) >> 0)
6531 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 register field value suitable for setting the register. */
6532 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14_SET(value) (((value) << 0) & 0x0000003f)
6533 
6534 #ifndef __ASSEMBLY__
6535 /*
6536  * WARNING: The C register and register group struct declarations are provided for
6537  * convenience and illustrative purposes. They should, however, be used with
6538  * caution as the C language standard provides no guarantees about the alignment or
6539  * atomicity of device memory accesses. The recommended practice for writing
6540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6541  * alt_write_word() functions.
6542  *
6543  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14.
6544  */
6545 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_s
6546 {
6547  volatile uint32_t SIGOUTSRC14 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_SIGOUTSRC14 */
6548  uint32_t : 26; /* *UNDEFINED* */
6549 };
6550 
6551 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14. */
6552 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_t;
6553 #endif /* __ASSEMBLY__ */
6554 
6555 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14 register. */
6556 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_RESET 0x0000000e
6557 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14 register from the beginning of the component. */
6558 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_OFST 0x58
6559 
6560 /*
6561  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc15
6562  *
6563  * Register Layout
6564  *
6565  * Bits | Access | Reset | Description
6566  * :-------|:-------|:--------|:---------------------------------------------------------------
6567  * [5:0] | RW | 0xf | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15
6568  * [31:6] | ??? | Unknown | *UNDEFINED*
6569  *
6570  */
6571 /*
6572  * Field : SIGOUTSRC15
6573  *
6574  * This 6 bits register selects the Signal_Status bit that will be connected to the
6575  * SigOut bit 15. Each register (r) uses the following value (v) encoding. 0x00 to
6576  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6577  *
6578  * Field Access Macros:
6579  *
6580  */
6581 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field. */
6582 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_LSB 0
6583 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field. */
6584 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_MSB 5
6585 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field. */
6586 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_WIDTH 6
6587 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field value. */
6588 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_SET_MSK 0x0000003f
6589 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field value. */
6590 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_CLR_MSK 0xffffffc0
6591 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field. */
6592 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_RESET 0xf
6593 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 field value from a register. */
6594 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_GET(value) (((value) & 0x0000003f) >> 0)
6595 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 register field value suitable for setting the register. */
6596 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15_SET(value) (((value) << 0) & 0x0000003f)
6597 
6598 #ifndef __ASSEMBLY__
6599 /*
6600  * WARNING: The C register and register group struct declarations are provided for
6601  * convenience and illustrative purposes. They should, however, be used with
6602  * caution as the C language standard provides no guarantees about the alignment or
6603  * atomicity of device memory accesses. The recommended practice for writing
6604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6605  * alt_write_word() functions.
6606  *
6607  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15.
6608  */
6609 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_s
6610 {
6611  volatile uint32_t SIGOUTSRC15 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_SIGOUTSRC15 */
6612  uint32_t : 26; /* *UNDEFINED* */
6613 };
6614 
6615 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15. */
6616 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_t;
6617 #endif /* __ASSEMBLY__ */
6618 
6619 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15 register. */
6620 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_RESET 0x0000000f
6621 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15 register from the beginning of the component. */
6622 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_OFST 0x5c
6623 
6624 /*
6625  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc16
6626  *
6627  * Register Layout
6628  *
6629  * Bits | Access | Reset | Description
6630  * :-------|:-------|:--------|:---------------------------------------------------------------
6631  * [5:0] | RW | 0x10 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16
6632  * [31:6] | ??? | Unknown | *UNDEFINED*
6633  *
6634  */
6635 /*
6636  * Field : SIGOUTSRC16
6637  *
6638  * This 6 bits register selects the Signal_Status bit that will be connected to the
6639  * SigOut bit 16. Each register (r) uses the following value (v) encoding. 0x00 to
6640  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6641  *
6642  * Field Access Macros:
6643  *
6644  */
6645 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field. */
6646 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_LSB 0
6647 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field. */
6648 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_MSB 5
6649 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field. */
6650 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_WIDTH 6
6651 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field value. */
6652 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_SET_MSK 0x0000003f
6653 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field value. */
6654 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_CLR_MSK 0xffffffc0
6655 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field. */
6656 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_RESET 0x10
6657 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 field value from a register. */
6658 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_GET(value) (((value) & 0x0000003f) >> 0)
6659 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 register field value suitable for setting the register. */
6660 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16_SET(value) (((value) << 0) & 0x0000003f)
6661 
6662 #ifndef __ASSEMBLY__
6663 /*
6664  * WARNING: The C register and register group struct declarations are provided for
6665  * convenience and illustrative purposes. They should, however, be used with
6666  * caution as the C language standard provides no guarantees about the alignment or
6667  * atomicity of device memory accesses. The recommended practice for writing
6668  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6669  * alt_write_word() functions.
6670  *
6671  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16.
6672  */
6673 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_s
6674 {
6675  volatile uint32_t SIGOUTSRC16 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_SIGOUTSRC16 */
6676  uint32_t : 26; /* *UNDEFINED* */
6677 };
6678 
6679 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16. */
6680 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_t;
6681 #endif /* __ASSEMBLY__ */
6682 
6683 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16 register. */
6684 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_RESET 0x00000010
6685 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16 register from the beginning of the component. */
6686 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_OFST 0x60
6687 
6688 /*
6689  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc17
6690  *
6691  * Register Layout
6692  *
6693  * Bits | Access | Reset | Description
6694  * :-------|:-------|:--------|:---------------------------------------------------------------
6695  * [5:0] | RW | 0x11 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17
6696  * [31:6] | ??? | Unknown | *UNDEFINED*
6697  *
6698  */
6699 /*
6700  * Field : SIGOUTSRC17
6701  *
6702  * This 6 bits register selects the Signal_Status bit that will be connected to the
6703  * SigOut bit 17. Each register (r) uses the following value (v) encoding. 0x00 to
6704  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6705  *
6706  * Field Access Macros:
6707  *
6708  */
6709 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field. */
6710 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_LSB 0
6711 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field. */
6712 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_MSB 5
6713 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field. */
6714 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_WIDTH 6
6715 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field value. */
6716 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_SET_MSK 0x0000003f
6717 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field value. */
6718 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_CLR_MSK 0xffffffc0
6719 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field. */
6720 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_RESET 0x11
6721 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 field value from a register. */
6722 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_GET(value) (((value) & 0x0000003f) >> 0)
6723 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 register field value suitable for setting the register. */
6724 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17_SET(value) (((value) << 0) & 0x0000003f)
6725 
6726 #ifndef __ASSEMBLY__
6727 /*
6728  * WARNING: The C register and register group struct declarations are provided for
6729  * convenience and illustrative purposes. They should, however, be used with
6730  * caution as the C language standard provides no guarantees about the alignment or
6731  * atomicity of device memory accesses. The recommended practice for writing
6732  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6733  * alt_write_word() functions.
6734  *
6735  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17.
6736  */
6737 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_s
6738 {
6739  volatile uint32_t SIGOUTSRC17 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_SIGOUTSRC17 */
6740  uint32_t : 26; /* *UNDEFINED* */
6741 };
6742 
6743 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17. */
6744 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_t;
6745 #endif /* __ASSEMBLY__ */
6746 
6747 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17 register. */
6748 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_RESET 0x00000011
6749 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17 register from the beginning of the component. */
6750 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_OFST 0x64
6751 
6752 /*
6753  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc18
6754  *
6755  * Register Layout
6756  *
6757  * Bits | Access | Reset | Description
6758  * :-------|:-------|:--------|:---------------------------------------------------------------
6759  * [5:0] | RW | 0x12 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18
6760  * [31:6] | ??? | Unknown | *UNDEFINED*
6761  *
6762  */
6763 /*
6764  * Field : SIGOUTSRC18
6765  *
6766  * This 6 bits register selects the Signal_Status bit that will be connected to the
6767  * SigOut bit 18. Each register (r) uses the following value (v) encoding. 0x00 to
6768  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6769  *
6770  * Field Access Macros:
6771  *
6772  */
6773 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field. */
6774 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_LSB 0
6775 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field. */
6776 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_MSB 5
6777 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field. */
6778 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_WIDTH 6
6779 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field value. */
6780 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_SET_MSK 0x0000003f
6781 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field value. */
6782 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_CLR_MSK 0xffffffc0
6783 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field. */
6784 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_RESET 0x12
6785 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 field value from a register. */
6786 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_GET(value) (((value) & 0x0000003f) >> 0)
6787 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 register field value suitable for setting the register. */
6788 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18_SET(value) (((value) << 0) & 0x0000003f)
6789 
6790 #ifndef __ASSEMBLY__
6791 /*
6792  * WARNING: The C register and register group struct declarations are provided for
6793  * convenience and illustrative purposes. They should, however, be used with
6794  * caution as the C language standard provides no guarantees about the alignment or
6795  * atomicity of device memory accesses. The recommended practice for writing
6796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6797  * alt_write_word() functions.
6798  *
6799  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18.
6800  */
6801 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_s
6802 {
6803  volatile uint32_t SIGOUTSRC18 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_SIGOUTSRC18 */
6804  uint32_t : 26; /* *UNDEFINED* */
6805 };
6806 
6807 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18. */
6808 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_t;
6809 #endif /* __ASSEMBLY__ */
6810 
6811 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18 register. */
6812 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_RESET 0x00000012
6813 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18 register from the beginning of the component. */
6814 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_OFST 0x68
6815 
6816 /*
6817  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc19
6818  *
6819  * Register Layout
6820  *
6821  * Bits | Access | Reset | Description
6822  * :-------|:-------|:--------|:---------------------------------------------------------------
6823  * [5:0] | RW | 0x13 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19
6824  * [31:6] | ??? | Unknown | *UNDEFINED*
6825  *
6826  */
6827 /*
6828  * Field : SIGOUTSRC19
6829  *
6830  * This 6 bits register selects the Signal_Status bit that will be connected to the
6831  * SigOut bit 19. Each register (r) uses the following value (v) encoding. 0x00 to
6832  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6833  *
6834  * Field Access Macros:
6835  *
6836  */
6837 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field. */
6838 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_LSB 0
6839 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field. */
6840 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_MSB 5
6841 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field. */
6842 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_WIDTH 6
6843 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field value. */
6844 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_SET_MSK 0x0000003f
6845 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field value. */
6846 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_CLR_MSK 0xffffffc0
6847 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field. */
6848 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_RESET 0x13
6849 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 field value from a register. */
6850 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_GET(value) (((value) & 0x0000003f) >> 0)
6851 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 register field value suitable for setting the register. */
6852 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19_SET(value) (((value) << 0) & 0x0000003f)
6853 
6854 #ifndef __ASSEMBLY__
6855 /*
6856  * WARNING: The C register and register group struct declarations are provided for
6857  * convenience and illustrative purposes. They should, however, be used with
6858  * caution as the C language standard provides no guarantees about the alignment or
6859  * atomicity of device memory accesses. The recommended practice for writing
6860  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6861  * alt_write_word() functions.
6862  *
6863  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19.
6864  */
6865 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_s
6866 {
6867  volatile uint32_t SIGOUTSRC19 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_SIGOUTSRC19 */
6868  uint32_t : 26; /* *UNDEFINED* */
6869 };
6870 
6871 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19. */
6872 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_t;
6873 #endif /* __ASSEMBLY__ */
6874 
6875 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19 register. */
6876 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_RESET 0x00000013
6877 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19 register from the beginning of the component. */
6878 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_OFST 0x6c
6879 
6880 /*
6881  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc20
6882  *
6883  * Register Layout
6884  *
6885  * Bits | Access | Reset | Description
6886  * :-------|:-------|:--------|:---------------------------------------------------------------
6887  * [5:0] | RW | 0x14 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20
6888  * [31:6] | ??? | Unknown | *UNDEFINED*
6889  *
6890  */
6891 /*
6892  * Field : SIGOUTSRC20
6893  *
6894  * This 6 bits register selects the Signal_Status bit that will be connected to the
6895  * SigOut bit 20. Each register (r) uses the following value (v) encoding. 0x00 to
6896  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6897  *
6898  * Field Access Macros:
6899  *
6900  */
6901 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field. */
6902 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_LSB 0
6903 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field. */
6904 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_MSB 5
6905 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field. */
6906 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_WIDTH 6
6907 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field value. */
6908 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_SET_MSK 0x0000003f
6909 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field value. */
6910 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_CLR_MSK 0xffffffc0
6911 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field. */
6912 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_RESET 0x14
6913 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 field value from a register. */
6914 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_GET(value) (((value) & 0x0000003f) >> 0)
6915 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 register field value suitable for setting the register. */
6916 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20_SET(value) (((value) << 0) & 0x0000003f)
6917 
6918 #ifndef __ASSEMBLY__
6919 /*
6920  * WARNING: The C register and register group struct declarations are provided for
6921  * convenience and illustrative purposes. They should, however, be used with
6922  * caution as the C language standard provides no guarantees about the alignment or
6923  * atomicity of device memory accesses. The recommended practice for writing
6924  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6925  * alt_write_word() functions.
6926  *
6927  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20.
6928  */
6929 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_s
6930 {
6931  volatile uint32_t SIGOUTSRC20 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_SIGOUTSRC20 */
6932  uint32_t : 26; /* *UNDEFINED* */
6933 };
6934 
6935 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20. */
6936 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_t;
6937 #endif /* __ASSEMBLY__ */
6938 
6939 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20 register. */
6940 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_RESET 0x00000014
6941 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20 register from the beginning of the component. */
6942 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_OFST 0x70
6943 
6944 /*
6945  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc21
6946  *
6947  * Register Layout
6948  *
6949  * Bits | Access | Reset | Description
6950  * :-------|:-------|:--------|:---------------------------------------------------------------
6951  * [5:0] | RW | 0x15 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21
6952  * [31:6] | ??? | Unknown | *UNDEFINED*
6953  *
6954  */
6955 /*
6956  * Field : SIGOUTSRC21
6957  *
6958  * This 6 bits register selects the Signal_Status bit that will be connected to the
6959  * SigOut bit 21. Each register (r) uses the following value (v) encoding. 0x00 to
6960  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
6961  *
6962  * Field Access Macros:
6963  *
6964  */
6965 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field. */
6966 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_LSB 0
6967 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field. */
6968 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_MSB 5
6969 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field. */
6970 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_WIDTH 6
6971 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field value. */
6972 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_SET_MSK 0x0000003f
6973 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field value. */
6974 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_CLR_MSK 0xffffffc0
6975 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field. */
6976 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_RESET 0x15
6977 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 field value from a register. */
6978 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_GET(value) (((value) & 0x0000003f) >> 0)
6979 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 register field value suitable for setting the register. */
6980 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21_SET(value) (((value) << 0) & 0x0000003f)
6981 
6982 #ifndef __ASSEMBLY__
6983 /*
6984  * WARNING: The C register and register group struct declarations are provided for
6985  * convenience and illustrative purposes. They should, however, be used with
6986  * caution as the C language standard provides no guarantees about the alignment or
6987  * atomicity of device memory accesses. The recommended practice for writing
6988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6989  * alt_write_word() functions.
6990  *
6991  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21.
6992  */
6993 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_s
6994 {
6995  volatile uint32_t SIGOUTSRC21 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_SIGOUTSRC21 */
6996  uint32_t : 26; /* *UNDEFINED* */
6997 };
6998 
6999 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21. */
7000 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_t;
7001 #endif /* __ASSEMBLY__ */
7002 
7003 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21 register. */
7004 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_RESET 0x00000015
7005 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21 register from the beginning of the component. */
7006 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_OFST 0x74
7007 
7008 /*
7009  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc22
7010  *
7011  * Register Layout
7012  *
7013  * Bits | Access | Reset | Description
7014  * :-------|:-------|:--------|:---------------------------------------------------------------
7015  * [5:0] | RW | 0x16 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22
7016  * [31:6] | ??? | Unknown | *UNDEFINED*
7017  *
7018  */
7019 /*
7020  * Field : SIGOUTSRC22
7021  *
7022  * This 6 bits register selects the Signal_Status bit that will be connected to the
7023  * SigOut bit 22. Each register (r) uses the following value (v) encoding. 0x00 to
7024  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7025  *
7026  * Field Access Macros:
7027  *
7028  */
7029 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field. */
7030 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_LSB 0
7031 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field. */
7032 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_MSB 5
7033 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field. */
7034 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_WIDTH 6
7035 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field value. */
7036 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_SET_MSK 0x0000003f
7037 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field value. */
7038 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_CLR_MSK 0xffffffc0
7039 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field. */
7040 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_RESET 0x16
7041 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 field value from a register. */
7042 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_GET(value) (((value) & 0x0000003f) >> 0)
7043 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 register field value suitable for setting the register. */
7044 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22_SET(value) (((value) << 0) & 0x0000003f)
7045 
7046 #ifndef __ASSEMBLY__
7047 /*
7048  * WARNING: The C register and register group struct declarations are provided for
7049  * convenience and illustrative purposes. They should, however, be used with
7050  * caution as the C language standard provides no guarantees about the alignment or
7051  * atomicity of device memory accesses. The recommended practice for writing
7052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7053  * alt_write_word() functions.
7054  *
7055  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22.
7056  */
7057 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_s
7058 {
7059  volatile uint32_t SIGOUTSRC22 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_SIGOUTSRC22 */
7060  uint32_t : 26; /* *UNDEFINED* */
7061 };
7062 
7063 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22. */
7064 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_t;
7065 #endif /* __ASSEMBLY__ */
7066 
7067 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22 register. */
7068 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_RESET 0x00000016
7069 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22 register from the beginning of the component. */
7070 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_OFST 0x78
7071 
7072 /*
7073  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc23
7074  *
7075  * Register Layout
7076  *
7077  * Bits | Access | Reset | Description
7078  * :-------|:-------|:--------|:---------------------------------------------------------------
7079  * [5:0] | RW | 0x17 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23
7080  * [31:6] | ??? | Unknown | *UNDEFINED*
7081  *
7082  */
7083 /*
7084  * Field : SIGOUTSRC23
7085  *
7086  * This 6 bits register selects the Signal_Status bit that will be connected to the
7087  * SigOut bit 23. Each register (r) uses the following value (v) encoding. 0x00 to
7088  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7089  *
7090  * Field Access Macros:
7091  *
7092  */
7093 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field. */
7094 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_LSB 0
7095 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field. */
7096 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_MSB 5
7097 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field. */
7098 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_WIDTH 6
7099 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field value. */
7100 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_SET_MSK 0x0000003f
7101 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field value. */
7102 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_CLR_MSK 0xffffffc0
7103 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field. */
7104 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_RESET 0x17
7105 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 field value from a register. */
7106 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_GET(value) (((value) & 0x0000003f) >> 0)
7107 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 register field value suitable for setting the register. */
7108 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23_SET(value) (((value) << 0) & 0x0000003f)
7109 
7110 #ifndef __ASSEMBLY__
7111 /*
7112  * WARNING: The C register and register group struct declarations are provided for
7113  * convenience and illustrative purposes. They should, however, be used with
7114  * caution as the C language standard provides no guarantees about the alignment or
7115  * atomicity of device memory accesses. The recommended practice for writing
7116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7117  * alt_write_word() functions.
7118  *
7119  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23.
7120  */
7121 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_s
7122 {
7123  volatile uint32_t SIGOUTSRC23 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_SIGOUTSRC23 */
7124  uint32_t : 26; /* *UNDEFINED* */
7125 };
7126 
7127 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23. */
7128 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_t;
7129 #endif /* __ASSEMBLY__ */
7130 
7131 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23 register. */
7132 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_RESET 0x00000017
7133 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23 register from the beginning of the component. */
7134 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_OFST 0x7c
7135 
7136 /*
7137  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc24
7138  *
7139  * Register Layout
7140  *
7141  * Bits | Access | Reset | Description
7142  * :-------|:-------|:--------|:---------------------------------------------------------------
7143  * [5:0] | RW | 0x18 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24
7144  * [31:6] | ??? | Unknown | *UNDEFINED*
7145  *
7146  */
7147 /*
7148  * Field : SIGOUTSRC24
7149  *
7150  * This 6 bits register selects the Signal_Status bit that will be connected to the
7151  * SigOut bit 24. Each register (r) uses the following value (v) encoding. 0x00 to
7152  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7153  *
7154  * Field Access Macros:
7155  *
7156  */
7157 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field. */
7158 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_LSB 0
7159 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field. */
7160 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_MSB 5
7161 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field. */
7162 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_WIDTH 6
7163 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field value. */
7164 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_SET_MSK 0x0000003f
7165 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field value. */
7166 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_CLR_MSK 0xffffffc0
7167 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field. */
7168 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_RESET 0x18
7169 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 field value from a register. */
7170 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_GET(value) (((value) & 0x0000003f) >> 0)
7171 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 register field value suitable for setting the register. */
7172 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24_SET(value) (((value) << 0) & 0x0000003f)
7173 
7174 #ifndef __ASSEMBLY__
7175 /*
7176  * WARNING: The C register and register group struct declarations are provided for
7177  * convenience and illustrative purposes. They should, however, be used with
7178  * caution as the C language standard provides no guarantees about the alignment or
7179  * atomicity of device memory accesses. The recommended practice for writing
7180  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7181  * alt_write_word() functions.
7182  *
7183  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24.
7184  */
7185 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_s
7186 {
7187  volatile uint32_t SIGOUTSRC24 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_SIGOUTSRC24 */
7188  uint32_t : 26; /* *UNDEFINED* */
7189 };
7190 
7191 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24. */
7192 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_t;
7193 #endif /* __ASSEMBLY__ */
7194 
7195 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24 register. */
7196 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_RESET 0x00000018
7197 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24 register from the beginning of the component. */
7198 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_OFST 0x80
7199 
7200 /*
7201  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc25
7202  *
7203  * Register Layout
7204  *
7205  * Bits | Access | Reset | Description
7206  * :-------|:-------|:--------|:---------------------------------------------------------------
7207  * [5:0] | RW | 0x19 | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25
7208  * [31:6] | ??? | Unknown | *UNDEFINED*
7209  *
7210  */
7211 /*
7212  * Field : SIGOUTSRC25
7213  *
7214  * This 6 bits register selects the Signal_Status bit that will be connected to the
7215  * SigOut bit 25. Each register (r) uses the following value (v) encoding. 0x00 to
7216  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7217  *
7218  * Field Access Macros:
7219  *
7220  */
7221 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field. */
7222 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_LSB 0
7223 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field. */
7224 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_MSB 5
7225 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field. */
7226 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_WIDTH 6
7227 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field value. */
7228 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_SET_MSK 0x0000003f
7229 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field value. */
7230 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_CLR_MSK 0xffffffc0
7231 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field. */
7232 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_RESET 0x19
7233 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 field value from a register. */
7234 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_GET(value) (((value) & 0x0000003f) >> 0)
7235 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 register field value suitable for setting the register. */
7236 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25_SET(value) (((value) << 0) & 0x0000003f)
7237 
7238 #ifndef __ASSEMBLY__
7239 /*
7240  * WARNING: The C register and register group struct declarations are provided for
7241  * convenience and illustrative purposes. They should, however, be used with
7242  * caution as the C language standard provides no guarantees about the alignment or
7243  * atomicity of device memory accesses. The recommended practice for writing
7244  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7245  * alt_write_word() functions.
7246  *
7247  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25.
7248  */
7249 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_s
7250 {
7251  volatile uint32_t SIGOUTSRC25 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_SIGOUTSRC25 */
7252  uint32_t : 26; /* *UNDEFINED* */
7253 };
7254 
7255 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25. */
7256 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_t;
7257 #endif /* __ASSEMBLY__ */
7258 
7259 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25 register. */
7260 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_RESET 0x00000019
7261 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25 register from the beginning of the component. */
7262 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_OFST 0x84
7263 
7264 /*
7265  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc26
7266  *
7267  * Register Layout
7268  *
7269  * Bits | Access | Reset | Description
7270  * :-------|:-------|:--------|:---------------------------------------------------------------
7271  * [5:0] | RW | 0x1a | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26
7272  * [31:6] | ??? | Unknown | *UNDEFINED*
7273  *
7274  */
7275 /*
7276  * Field : SIGOUTSRC26
7277  *
7278  * This 6 bits register selects the Signal_Status bit that will be connected to the
7279  * SigOut bit 26. Each register (r) uses the following value (v) encoding. 0x00 to
7280  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7281  *
7282  * Field Access Macros:
7283  *
7284  */
7285 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field. */
7286 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_LSB 0
7287 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field. */
7288 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_MSB 5
7289 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field. */
7290 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_WIDTH 6
7291 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field value. */
7292 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_SET_MSK 0x0000003f
7293 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field value. */
7294 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_CLR_MSK 0xffffffc0
7295 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field. */
7296 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_RESET 0x1a
7297 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 field value from a register. */
7298 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_GET(value) (((value) & 0x0000003f) >> 0)
7299 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 register field value suitable for setting the register. */
7300 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26_SET(value) (((value) << 0) & 0x0000003f)
7301 
7302 #ifndef __ASSEMBLY__
7303 /*
7304  * WARNING: The C register and register group struct declarations are provided for
7305  * convenience and illustrative purposes. They should, however, be used with
7306  * caution as the C language standard provides no guarantees about the alignment or
7307  * atomicity of device memory accesses. The recommended practice for writing
7308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7309  * alt_write_word() functions.
7310  *
7311  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26.
7312  */
7313 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_s
7314 {
7315  volatile uint32_t SIGOUTSRC26 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_SIGOUTSRC26 */
7316  uint32_t : 26; /* *UNDEFINED* */
7317 };
7318 
7319 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26. */
7320 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_t;
7321 #endif /* __ASSEMBLY__ */
7322 
7323 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26 register. */
7324 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_RESET 0x0000001a
7325 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26 register from the beginning of the component. */
7326 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_OFST 0x88
7327 
7328 /*
7329  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc27
7330  *
7331  * Register Layout
7332  *
7333  * Bits | Access | Reset | Description
7334  * :-------|:-------|:--------|:---------------------------------------------------------------
7335  * [5:0] | RW | 0x1b | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27
7336  * [31:6] | ??? | Unknown | *UNDEFINED*
7337  *
7338  */
7339 /*
7340  * Field : SIGOUTSRC27
7341  *
7342  * This 6 bits register selects the Signal_Status bit that will be connected to the
7343  * SigOut bit 27. Each register (r) uses the following value (v) encoding. 0x00 to
7344  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7345  *
7346  * Field Access Macros:
7347  *
7348  */
7349 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field. */
7350 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_LSB 0
7351 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field. */
7352 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_MSB 5
7353 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field. */
7354 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_WIDTH 6
7355 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field value. */
7356 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_SET_MSK 0x0000003f
7357 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field value. */
7358 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_CLR_MSK 0xffffffc0
7359 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field. */
7360 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_RESET 0x1b
7361 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 field value from a register. */
7362 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_GET(value) (((value) & 0x0000003f) >> 0)
7363 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 register field value suitable for setting the register. */
7364 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27_SET(value) (((value) << 0) & 0x0000003f)
7365 
7366 #ifndef __ASSEMBLY__
7367 /*
7368  * WARNING: The C register and register group struct declarations are provided for
7369  * convenience and illustrative purposes. They should, however, be used with
7370  * caution as the C language standard provides no guarantees about the alignment or
7371  * atomicity of device memory accesses. The recommended practice for writing
7372  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7373  * alt_write_word() functions.
7374  *
7375  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27.
7376  */
7377 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_s
7378 {
7379  volatile uint32_t SIGOUTSRC27 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_SIGOUTSRC27 */
7380  uint32_t : 26; /* *UNDEFINED* */
7381 };
7382 
7383 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27. */
7384 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_t;
7385 #endif /* __ASSEMBLY__ */
7386 
7387 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27 register. */
7388 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_RESET 0x0000001b
7389 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27 register from the beginning of the component. */
7390 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_OFST 0x8c
7391 
7392 /*
7393  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc28
7394  *
7395  * Register Layout
7396  *
7397  * Bits | Access | Reset | Description
7398  * :-------|:-------|:--------|:---------------------------------------------------------------
7399  * [5:0] | RW | 0x1c | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28
7400  * [31:6] | ??? | Unknown | *UNDEFINED*
7401  *
7402  */
7403 /*
7404  * Field : SIGOUTSRC28
7405  *
7406  * This 6 bits register selects the Signal_Status bit that will be connected to the
7407  * SigOut bit 28. Each register (r) uses the following value (v) encoding. 0x00 to
7408  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7409  *
7410  * Field Access Macros:
7411  *
7412  */
7413 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field. */
7414 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_LSB 0
7415 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field. */
7416 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_MSB 5
7417 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field. */
7418 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_WIDTH 6
7419 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field value. */
7420 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_SET_MSK 0x0000003f
7421 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field value. */
7422 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_CLR_MSK 0xffffffc0
7423 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field. */
7424 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_RESET 0x1c
7425 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 field value from a register. */
7426 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_GET(value) (((value) & 0x0000003f) >> 0)
7427 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 register field value suitable for setting the register. */
7428 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28_SET(value) (((value) << 0) & 0x0000003f)
7429 
7430 #ifndef __ASSEMBLY__
7431 /*
7432  * WARNING: The C register and register group struct declarations are provided for
7433  * convenience and illustrative purposes. They should, however, be used with
7434  * caution as the C language standard provides no guarantees about the alignment or
7435  * atomicity of device memory accesses. The recommended practice for writing
7436  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7437  * alt_write_word() functions.
7438  *
7439  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28.
7440  */
7441 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_s
7442 {
7443  volatile uint32_t SIGOUTSRC28 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_SIGOUTSRC28 */
7444  uint32_t : 26; /* *UNDEFINED* */
7445 };
7446 
7447 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28. */
7448 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_t;
7449 #endif /* __ASSEMBLY__ */
7450 
7451 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28 register. */
7452 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_RESET 0x0000001c
7453 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28 register from the beginning of the component. */
7454 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_OFST 0x90
7455 
7456 /*
7457  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc29
7458  *
7459  * Register Layout
7460  *
7461  * Bits | Access | Reset | Description
7462  * :-------|:-------|:--------|:---------------------------------------------------------------
7463  * [5:0] | RW | 0x1d | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29
7464  * [31:6] | ??? | Unknown | *UNDEFINED*
7465  *
7466  */
7467 /*
7468  * Field : SIGOUTSRC29
7469  *
7470  * This 6 bits register selects the Signal_Status bit that will be connected to the
7471  * SigOut bit 29. Each register (r) uses the following value (v) encoding. 0x00 to
7472  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7473  *
7474  * Field Access Macros:
7475  *
7476  */
7477 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field. */
7478 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_LSB 0
7479 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field. */
7480 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_MSB 5
7481 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field. */
7482 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_WIDTH 6
7483 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field value. */
7484 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_SET_MSK 0x0000003f
7485 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field value. */
7486 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_CLR_MSK 0xffffffc0
7487 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field. */
7488 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_RESET 0x1d
7489 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 field value from a register. */
7490 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_GET(value) (((value) & 0x0000003f) >> 0)
7491 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 register field value suitable for setting the register. */
7492 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29_SET(value) (((value) << 0) & 0x0000003f)
7493 
7494 #ifndef __ASSEMBLY__
7495 /*
7496  * WARNING: The C register and register group struct declarations are provided for
7497  * convenience and illustrative purposes. They should, however, be used with
7498  * caution as the C language standard provides no guarantees about the alignment or
7499  * atomicity of device memory accesses. The recommended practice for writing
7500  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7501  * alt_write_word() functions.
7502  *
7503  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29.
7504  */
7505 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_s
7506 {
7507  volatile uint32_t SIGOUTSRC29 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_SIGOUTSRC29 */
7508  uint32_t : 26; /* *UNDEFINED* */
7509 };
7510 
7511 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29. */
7512 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_t;
7513 #endif /* __ASSEMBLY__ */
7514 
7515 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29 register. */
7516 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_RESET 0x0000001d
7517 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29 register from the beginning of the component. */
7518 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_OFST 0x94
7519 
7520 /*
7521  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc30
7522  *
7523  * Register Layout
7524  *
7525  * Bits | Access | Reset | Description
7526  * :-------|:-------|:--------|:---------------------------------------------------------------
7527  * [5:0] | RW | 0x1e | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30
7528  * [31:6] | ??? | Unknown | *UNDEFINED*
7529  *
7530  */
7531 /*
7532  * Field : SIGOUTSRC30
7533  *
7534  * This 6 bits register selects the Signal_Status bit that will be connected to the
7535  * SigOut bit 30. Each register (r) uses the following value (v) encoding. 0x00 to
7536  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7537  *
7538  * Field Access Macros:
7539  *
7540  */
7541 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field. */
7542 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_LSB 0
7543 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field. */
7544 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_MSB 5
7545 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field. */
7546 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_WIDTH 6
7547 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field value. */
7548 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_SET_MSK 0x0000003f
7549 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field value. */
7550 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_CLR_MSK 0xffffffc0
7551 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field. */
7552 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_RESET 0x1e
7553 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 field value from a register. */
7554 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_GET(value) (((value) & 0x0000003f) >> 0)
7555 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 register field value suitable for setting the register. */
7556 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30_SET(value) (((value) << 0) & 0x0000003f)
7557 
7558 #ifndef __ASSEMBLY__
7559 /*
7560  * WARNING: The C register and register group struct declarations are provided for
7561  * convenience and illustrative purposes. They should, however, be used with
7562  * caution as the C language standard provides no guarantees about the alignment or
7563  * atomicity of device memory accesses. The recommended practice for writing
7564  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7565  * alt_write_word() functions.
7566  *
7567  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30.
7568  */
7569 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_s
7570 {
7571  volatile uint32_t SIGOUTSRC30 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_SIGOUTSRC30 */
7572  uint32_t : 26; /* *UNDEFINED* */
7573 };
7574 
7575 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30. */
7576 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_t;
7577 #endif /* __ASSEMBLY__ */
7578 
7579 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30 register. */
7580 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_RESET 0x0000001e
7581 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30 register from the beginning of the component. */
7582 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_OFST 0x98
7583 
7584 /*
7585  * Register : LLI_Targ_Svc_SIG_User_SigOutSrc31
7586  *
7587  * Register Layout
7588  *
7589  * Bits | Access | Reset | Description
7590  * :-------|:-------|:--------|:---------------------------------------------------------------
7591  * [5:0] | RW | 0x1f | ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31
7592  * [31:6] | ??? | Unknown | *UNDEFINED*
7593  *
7594  */
7595 /*
7596  * Field : SIGOUTSRC31
7597  *
7598  * This 6 bits register selects the Signal_Status bit that will be connected to the
7599  * SigOut bit 31. Each register (r) uses the following value (v) encoding. 0x00 to
7600  * 0x1F: SigOut[r] <<= Signal_Status[v]; 0x20 to 0x3F: SigOut[r] <<= 0;
7601  *
7602  * Field Access Macros:
7603  *
7604  */
7605 /* The Least Significant Bit (LSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field. */
7606 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_LSB 0
7607 /* The Most Significant Bit (MSB) position of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field. */
7608 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_MSB 5
7609 /* The width in bits of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field. */
7610 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_WIDTH 6
7611 /* The mask used to set the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field value. */
7612 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_SET_MSK 0x0000003f
7613 /* The mask used to clear the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field value. */
7614 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_CLR_MSK 0xffffffc0
7615 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field. */
7616 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_RESET 0x1f
7617 /* Extracts the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 field value from a register. */
7618 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_GET(value) (((value) & 0x0000003f) >> 0)
7619 /* Produces a ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 register field value suitable for setting the register. */
7620 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31_SET(value) (((value) << 0) & 0x0000003f)
7621 
7622 #ifndef __ASSEMBLY__
7623 /*
7624  * WARNING: The C register and register group struct declarations are provided for
7625  * convenience and illustrative purposes. They should, however, be used with
7626  * caution as the C language standard provides no guarantees about the alignment or
7627  * atomicity of device memory accesses. The recommended practice for writing
7628  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7629  * alt_write_word() functions.
7630  *
7631  * The struct declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31.
7632  */
7633 struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_s
7634 {
7635  volatile uint32_t SIGOUTSRC31 : 6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_SIGOUTSRC31 */
7636  uint32_t : 26; /* *UNDEFINED* */
7637 };
7638 
7639 /* The typedef declaration for register ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31. */
7640 typedef struct ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_s ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_t;
7641 #endif /* __ASSEMBLY__ */
7642 
7643 /* The reset value of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31 register. */
7644 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_RESET 0x0000001f
7645 /* The byte offset of the ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31 register from the beginning of the component. */
7646 #define ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_OFST 0x9c
7647 
7648 #ifndef __ASSEMBLY__
7649 /*
7650  * WARNING: The C register and register group struct declarations are provided for
7651  * convenience and illustrative purposes. They should, however, be used with
7652  * caution as the C language standard provides no guarantees about the alignment or
7653  * atomicity of device memory accesses. The recommended practice for writing
7654  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7655  * alt_write_word() functions.
7656  *
7657  * The struct declaration for register group ALT_PSI_SIG_USER.
7658  */
7659 struct ALT_PSI_SIG_USER_s
7660 {
7661  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN_t LLI_Targ_Svc_SIG_User_SigIn; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN */
7662  volatile uint32_t _pad_0x4_0x17[5]; /* *UNDEFINED* */
7663  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL_t LLI_Targ_Svc_SIG_User_PowerCtl; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL */
7664  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL_t LLI_Targ_Svc_SIG_User_FaultCtl; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL */
7665  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0_t LLI_Targ_Svc_SIG_User_SigOutSrc0; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0 */
7666  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1_t LLI_Targ_Svc_SIG_User_SigOutSrc1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1 */
7667  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2_t LLI_Targ_Svc_SIG_User_SigOutSrc2; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2 */
7668  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3_t LLI_Targ_Svc_SIG_User_SigOutSrc3; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3 */
7669  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4_t LLI_Targ_Svc_SIG_User_SigOutSrc4; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4 */
7670  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5_t LLI_Targ_Svc_SIG_User_SigOutSrc5; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5 */
7671  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6_t LLI_Targ_Svc_SIG_User_SigOutSrc6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6 */
7672  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7_t LLI_Targ_Svc_SIG_User_SigOutSrc7; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7 */
7673  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8_t LLI_Targ_Svc_SIG_User_SigOutSrc8; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8 */
7674  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9_t LLI_Targ_Svc_SIG_User_SigOutSrc9; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9 */
7675  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10_t LLI_Targ_Svc_SIG_User_SigOutSrc10; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10 */
7676  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11_t LLI_Targ_Svc_SIG_User_SigOutSrc11; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11 */
7677  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12_t LLI_Targ_Svc_SIG_User_SigOutSrc12; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12 */
7678  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13_t LLI_Targ_Svc_SIG_User_SigOutSrc13; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13 */
7679  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14_t LLI_Targ_Svc_SIG_User_SigOutSrc14; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14 */
7680  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15_t LLI_Targ_Svc_SIG_User_SigOutSrc15; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15 */
7681  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16_t LLI_Targ_Svc_SIG_User_SigOutSrc16; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16 */
7682  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17_t LLI_Targ_Svc_SIG_User_SigOutSrc17; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17 */
7683  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18_t LLI_Targ_Svc_SIG_User_SigOutSrc18; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18 */
7684  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19_t LLI_Targ_Svc_SIG_User_SigOutSrc19; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19 */
7685  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20_t LLI_Targ_Svc_SIG_User_SigOutSrc20; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20 */
7686  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21_t LLI_Targ_Svc_SIG_User_SigOutSrc21; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21 */
7687  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22_t LLI_Targ_Svc_SIG_User_SigOutSrc22; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22 */
7688  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23_t LLI_Targ_Svc_SIG_User_SigOutSrc23; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23 */
7689  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24_t LLI_Targ_Svc_SIG_User_SigOutSrc24; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24 */
7690  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25_t LLI_Targ_Svc_SIG_User_SigOutSrc25; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25 */
7691  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26_t LLI_Targ_Svc_SIG_User_SigOutSrc26; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26 */
7692  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27_t LLI_Targ_Svc_SIG_User_SigOutSrc27; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27 */
7693  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28_t LLI_Targ_Svc_SIG_User_SigOutSrc28; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28 */
7694  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29_t LLI_Targ_Svc_SIG_User_SigOutSrc29; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29 */
7695  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30_t LLI_Targ_Svc_SIG_User_SigOutSrc30; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30 */
7696  volatile ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31_t LLI_Targ_Svc_SIG_User_SigOutSrc31; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31 */
7697  volatile uint32_t _pad_0xa0_0x200[88]; /* *UNDEFINED* */
7698 };
7699 
7700 /* The typedef declaration for register group ALT_PSI_SIG_USER. */
7701 typedef struct ALT_PSI_SIG_USER_s ALT_PSI_SIG_USER_t;
7702 /* The struct declaration for the raw register contents of register group ALT_PSI_SIG_USER. */
7703 struct ALT_PSI_SIG_USER_raw_s
7704 {
7705  volatile uint32_t LLI_Targ_Svc_SIG_User_SigIn; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGIN */
7706  volatile uint32_t _pad_0x4_0x17[5]; /* *UNDEFINED* */
7707  volatile uint32_t LLI_Targ_Svc_SIG_User_PowerCtl; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_POWERCTL */
7708  volatile uint32_t LLI_Targ_Svc_SIG_User_FaultCtl; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_FAULTCTL */
7709  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc0; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC0 */
7710  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc1; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC1 */
7711  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc2; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC2 */
7712  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc3; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC3 */
7713  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc4; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC4 */
7714  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc5; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC5 */
7715  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc6; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC6 */
7716  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc7; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC7 */
7717  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc8; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC8 */
7718  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc9; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC9 */
7719  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc10; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC10 */
7720  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc11; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC11 */
7721  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc12; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC12 */
7722  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc13; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC13 */
7723  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc14; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC14 */
7724  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc15; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC15 */
7725  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc16; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC16 */
7726  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc17; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC17 */
7727  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc18; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC18 */
7728  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc19; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC19 */
7729  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc20; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC20 */
7730  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc21; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC21 */
7731  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc22; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC22 */
7732  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc23; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC23 */
7733  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc24; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC24 */
7734  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc25; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC25 */
7735  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc26; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC26 */
7736  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc27; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC27 */
7737  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc28; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC28 */
7738  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc29; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC29 */
7739  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc30; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC30 */
7740  volatile uint32_t LLI_Targ_Svc_SIG_User_SigOutSrc31; /* ALT_PSI_SIG_USER_LLI_TARG_SVC_SIG_USER_SIGOUTSRC31 */
7741  volatile uint32_t _pad_0xa0_0x200[88]; /* *UNDEFINED* */
7742 };
7743 
7744 /* The typedef declaration for the raw register contents of register group ALT_PSI_SIG_USER. */
7745 typedef struct ALT_PSI_SIG_USER_raw_s ALT_PSI_SIG_USER_raw_t;
7746 #endif /* __ASSEMBLY__ */
7747 
7748 
7749 /*
7750  * Component : PSI_DDB
7751  *
7752  */
7753 /*
7754  * Register : LLI_Targ_Svc_DDB_Revision
7755  *
7756  * Register Layout
7757  *
7758  * Bits | Access | Reset | Description
7759  * :-------|:-------|:------|:-----------------------------------------------
7760  * [31:0] | R | 0x10 | ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION
7761  *
7762  */
7763 /*
7764  * Field : REVISION
7765  *
7766  * The revision of the DDB specification supported by this Device encoded as major-
7767  * version * 0x10 + minor-version.
7768  *
7769  * Field Access Macros:
7770  *
7771  */
7772 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field. */
7773 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_LSB 0
7774 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field. */
7775 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_MSB 31
7776 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field. */
7777 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_WIDTH 32
7778 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field value. */
7779 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_SET_MSK 0xffffffff
7780 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field value. */
7781 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_CLR_MSK 0x00000000
7782 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field. */
7783 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_RESET 0x10
7784 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION field value from a register. */
7785 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_GET(value) (((value) & 0xffffffff) >> 0)
7786 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION register field value suitable for setting the register. */
7787 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION_SET(value) (((value) << 0) & 0xffffffff)
7788 
7789 #ifndef __ASSEMBLY__
7790 /*
7791  * WARNING: The C register and register group struct declarations are provided for
7792  * convenience and illustrative purposes. They should, however, be used with
7793  * caution as the C language standard provides no guarantees about the alignment or
7794  * atomicity of device memory accesses. The recommended practice for writing
7795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7796  * alt_write_word() functions.
7797  *
7798  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION.
7799  */
7800 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_s
7801 {
7802  const volatile uint32_t REVISION : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_REVISION */
7803 };
7804 
7805 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION. */
7806 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_t;
7807 #endif /* __ASSEMBLY__ */
7808 
7809 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION register. */
7810 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_RESET 0x00000010
7811 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION register from the beginning of the component. */
7812 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_OFST 0x0
7813 
7814 /*
7815  * Register : LLI_Targ_Svc_DDB_Level
7816  *
7817  * Register Layout
7818  *
7819  * Bits | Access | Reset | Description
7820  * :-------|:-------|:------|:-----------------------------------------
7821  * [31:0] | R | 0x1 | ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL
7822  *
7823  */
7824 /*
7825  * Field : LEVEL
7826  *
7827  * Eight bit field indicating the DDB support: b0: DDB Level 1 supported b1: GET-
7828  * DDB-LEVEL2 Service supported b2: SET-DDB-LEVEL2 Service supported b[7:3]:
7829  * Reserved and shall be 0b00000.
7830  *
7831  * Field Access Macros:
7832  *
7833  */
7834 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field. */
7835 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_LSB 0
7836 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field. */
7837 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_MSB 31
7838 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field. */
7839 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_WIDTH 32
7840 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field value. */
7841 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_SET_MSK 0xffffffff
7842 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field value. */
7843 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_CLR_MSK 0x00000000
7844 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field. */
7845 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_RESET 0x1
7846 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL field value from a register. */
7847 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
7848 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL register field value suitable for setting the register. */
7849 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
7850 
7851 #ifndef __ASSEMBLY__
7852 /*
7853  * WARNING: The C register and register group struct declarations are provided for
7854  * convenience and illustrative purposes. They should, however, be used with
7855  * caution as the C language standard provides no guarantees about the alignment or
7856  * atomicity of device memory accesses. The recommended practice for writing
7857  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7858  * alt_write_word() functions.
7859  *
7860  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL.
7861  */
7862 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_s
7863 {
7864  const volatile uint32_t LEVEL : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_LEVEL */
7865 };
7866 
7867 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL. */
7868 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_t;
7869 #endif /* __ASSEMBLY__ */
7870 
7871 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL register. */
7872 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_RESET 0x00000001
7873 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL register from the beginning of the component. */
7874 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_OFST 0x4
7875 
7876 /*
7877  * Register : LLI_Targ_Svc_DDB_DeviceClass
7878  *
7879  * Register Layout
7880  *
7881  * Bits | Access | Reset | Description
7882  * :-------|:-------|:------|:-----------------------------------------------------
7883  * [31:0] | R | 0x9ff | ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS
7884  *
7885  */
7886 /*
7887  * Field : DEVICECLASS
7888  *
7889  * The device class ID of the Device as specified by the MIPI Alliance [MIPI02].
7890  * The group ID is 0x09 and the class ID is 0xFF for the current specification. The
7891  * class ID from 0x00 to 0xFE are reserved for future needs.
7892  *
7893  * Field Access Macros:
7894  *
7895  */
7896 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field. */
7897 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_LSB 0
7898 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field. */
7899 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_MSB 31
7900 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field. */
7901 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_WIDTH 32
7902 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field value. */
7903 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_SET_MSK 0xffffffff
7904 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field value. */
7905 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_CLR_MSK 0x00000000
7906 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field. */
7907 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_RESET 0x9ff
7908 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS field value from a register. */
7909 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_GET(value) (((value) & 0xffffffff) >> 0)
7910 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS register field value suitable for setting the register. */
7911 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS_SET(value) (((value) << 0) & 0xffffffff)
7912 
7913 #ifndef __ASSEMBLY__
7914 /*
7915  * WARNING: The C register and register group struct declarations are provided for
7916  * convenience and illustrative purposes. They should, however, be used with
7917  * caution as the C language standard provides no guarantees about the alignment or
7918  * atomicity of device memory accesses. The recommended practice for writing
7919  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7920  * alt_write_word() functions.
7921  *
7922  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS.
7923  */
7924 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_s
7925 {
7926  const volatile uint32_t DEVICECLASS : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_DEVICECLASS */
7927 };
7928 
7929 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS. */
7930 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_t;
7931 #endif /* __ASSEMBLY__ */
7932 
7933 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS register. */
7934 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_RESET 0x000009ff
7935 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS register from the beginning of the component. */
7936 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_OFST 0x8
7937 
7938 /*
7939  * Register : LLI_Targ_Svc_DDB_ManufacturerID
7940  *
7941  * Register Layout
7942  *
7943  * Bits | Access | Reset | Description
7944  * :-------|:-------|:------|:-----------------------------------------------------------
7945  * [31:0] | R | 0x0 | ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID
7946  *
7947  */
7948 /*
7949  * Field : MANUFACTURERID
7950  *
7951  * The manufacturer ID of the Device's manufacturer as specified by the MIPI
7952  * Alliance [MIPI02].
7953  *
7954  * Field Access Macros:
7955  *
7956  */
7957 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field. */
7958 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_LSB 0
7959 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field. */
7960 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_MSB 31
7961 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field. */
7962 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_WIDTH 32
7963 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field value. */
7964 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_SET_MSK 0xffffffff
7965 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field value. */
7966 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_CLR_MSK 0x00000000
7967 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field. */
7968 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_RESET 0x0
7969 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID field value from a register. */
7970 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_GET(value) (((value) & 0xffffffff) >> 0)
7971 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID register field value suitable for setting the register. */
7972 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID_SET(value) (((value) << 0) & 0xffffffff)
7973 
7974 #ifndef __ASSEMBLY__
7975 /*
7976  * WARNING: The C register and register group struct declarations are provided for
7977  * convenience and illustrative purposes. They should, however, be used with
7978  * caution as the C language standard provides no guarantees about the alignment or
7979  * atomicity of device memory accesses. The recommended practice for writing
7980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7981  * alt_write_word() functions.
7982  *
7983  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID.
7984  */
7985 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_s
7986 {
7987  const volatile uint32_t MANUFACTURERID : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_MANUFACTURERID */
7988 };
7989 
7990 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID. */
7991 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_t;
7992 #endif /* __ASSEMBLY__ */
7993 
7994 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID register. */
7995 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_RESET 0x00000000
7996 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID register from the beginning of the component. */
7997 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_OFST 0xc
7998 
7999 /*
8000  * Register : LLI_Targ_Svc_DDB_ProductID
8001  *
8002  * Register Layout
8003  *
8004  * Bits | Access | Reset | Description
8005  * :-------|:-------|:------|:-------------------------------------------------
8006  * [31:0] | R | 0x0 | ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID
8007  *
8008  */
8009 /*
8010  * Field : PRODUCTID
8011  *
8012  * The product ID as specified by the Device manufacturer.
8013  *
8014  * Field Access Macros:
8015  *
8016  */
8017 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field. */
8018 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_LSB 0
8019 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field. */
8020 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_MSB 31
8021 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field. */
8022 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_WIDTH 32
8023 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field value. */
8024 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_SET_MSK 0xffffffff
8025 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field value. */
8026 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_CLR_MSK 0x00000000
8027 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field. */
8028 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_RESET 0x0
8029 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID field value from a register. */
8030 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_GET(value) (((value) & 0xffffffff) >> 0)
8031 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID register field value suitable for setting the register. */
8032 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID_SET(value) (((value) << 0) & 0xffffffff)
8033 
8034 #ifndef __ASSEMBLY__
8035 /*
8036  * WARNING: The C register and register group struct declarations are provided for
8037  * convenience and illustrative purposes. They should, however, be used with
8038  * caution as the C language standard provides no guarantees about the alignment or
8039  * atomicity of device memory accesses. The recommended practice for writing
8040  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8041  * alt_write_word() functions.
8042  *
8043  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID.
8044  */
8045 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_s
8046 {
8047  const volatile uint32_t PRODUCTID : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_PRODUCTID */
8048 };
8049 
8050 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID. */
8051 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_t;
8052 #endif /* __ASSEMBLY__ */
8053 
8054 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID register. */
8055 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_RESET 0x00000000
8056 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID register from the beginning of the component. */
8057 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_OFST 0x10
8058 
8059 /*
8060  * Register : LLI_Targ_Svc_DDB_Length
8061  *
8062  * Register Layout
8063  *
8064  * Bits | Access | Reset | Description
8065  * :-------|:-------|:------|:-------------------------------------------
8066  * [31:0] | R | 0x0 | ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH
8067  *
8068  */
8069 /*
8070  * Field : LENGTH
8071  *
8072  * The length of any DDB Level 2 data. For Devices supporting only DDB Level 1, the
8073  * value shall be 0. For Devices supporting DDB Level 2, the value shall be the
8074  * size of the available DDB Level 2 data in bytes.
8075  *
8076  * Field Access Macros:
8077  *
8078  */
8079 /* The Least Significant Bit (LSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field. */
8080 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_LSB 0
8081 /* The Most Significant Bit (MSB) position of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field. */
8082 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_MSB 31
8083 /* The width in bits of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field. */
8084 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_WIDTH 32
8085 /* The mask used to set the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field value. */
8086 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_SET_MSK 0xffffffff
8087 /* The mask used to clear the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field value. */
8088 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_CLR_MSK 0x00000000
8089 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field. */
8090 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_RESET 0x0
8091 /* Extracts the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH field value from a register. */
8092 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_GET(value) (((value) & 0xffffffff) >> 0)
8093 /* Produces a ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH register field value suitable for setting the register. */
8094 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH_SET(value) (((value) << 0) & 0xffffffff)
8095 
8096 #ifndef __ASSEMBLY__
8097 /*
8098  * WARNING: The C register and register group struct declarations are provided for
8099  * convenience and illustrative purposes. They should, however, be used with
8100  * caution as the C language standard provides no guarantees about the alignment or
8101  * atomicity of device memory accesses. The recommended practice for writing
8102  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8103  * alt_write_word() functions.
8104  *
8105  * The struct declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH.
8106  */
8107 struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_s
8108 {
8109  const volatile uint32_t LENGTH : 32; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_LENGTH */
8110 };
8111 
8112 /* The typedef declaration for register ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH. */
8113 typedef struct ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_s ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_t;
8114 #endif /* __ASSEMBLY__ */
8115 
8116 /* The reset value of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH register. */
8117 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_RESET 0x00000000
8118 /* The byte offset of the ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH register from the beginning of the component. */
8119 #define ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_OFST 0x14
8120 
8121 #ifndef __ASSEMBLY__
8122 /*
8123  * WARNING: The C register and register group struct declarations are provided for
8124  * convenience and illustrative purposes. They should, however, be used with
8125  * caution as the C language standard provides no guarantees about the alignment or
8126  * atomicity of device memory accesses. The recommended practice for writing
8127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8128  * alt_write_word() functions.
8129  *
8130  * The struct declaration for register group ALT_PSI_DDB.
8131  */
8132 struct ALT_PSI_DDB_s
8133 {
8134  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION_t LLI_Targ_Svc_DDB_Revision; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION */
8135  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL_t LLI_Targ_Svc_DDB_Level; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL */
8136  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS_t LLI_Targ_Svc_DDB_DeviceClass; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS */
8137  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID_t LLI_Targ_Svc_DDB_ManufacturerID; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID */
8138  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID_t LLI_Targ_Svc_DDB_ProductID; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID */
8139  volatile ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH_t LLI_Targ_Svc_DDB_Length; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH */
8140  volatile uint32_t _pad_0x18_0x400[250]; /* *UNDEFINED* */
8141 };
8142 
8143 /* The typedef declaration for register group ALT_PSI_DDB. */
8144 typedef struct ALT_PSI_DDB_s ALT_PSI_DDB_t;
8145 /* The struct declaration for the raw register contents of register group ALT_PSI_DDB. */
8146 struct ALT_PSI_DDB_raw_s
8147 {
8148  volatile uint32_t LLI_Targ_Svc_DDB_Revision; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_REVISION */
8149  volatile uint32_t LLI_Targ_Svc_DDB_Level; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LEVEL */
8150  volatile uint32_t LLI_Targ_Svc_DDB_DeviceClass; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_DEVICECLASS */
8151  volatile uint32_t LLI_Targ_Svc_DDB_ManufacturerID; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_MANUFACTURERID */
8152  volatile uint32_t LLI_Targ_Svc_DDB_ProductID; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_PRODUCTID */
8153  volatile uint32_t LLI_Targ_Svc_DDB_Length; /* ALT_PSI_DDB_LLI_TARG_SVC_DDB_LENGTH */
8154  volatile uint32_t _pad_0x18_0x400[250]; /* *UNDEFINED* */
8155 };
8156 
8157 /* The typedef declaration for the raw register contents of register group ALT_PSI_DDB. */
8158 typedef struct ALT_PSI_DDB_raw_s ALT_PSI_DDB_raw_t;
8159 #endif /* __ASSEMBLY__ */
8160 
8161 
8162 #ifdef __cplusplus
8163 }
8164 #endif /* __cplusplus */
8165 #endif /* __ALT_SOCAL_PSI_H__ */
8166