35 #ifndef __ALT_SOCAL_RSTMGR_H__
36 #define __ALT_SOCAL_RSTMGR_H__
101 #define ALT_RSTMGR_STAT_SDMCOLDRST_LSB 0
103 #define ALT_RSTMGR_STAT_SDMCOLDRST_MSB 0
105 #define ALT_RSTMGR_STAT_SDMCOLDRST_WIDTH 1
107 #define ALT_RSTMGR_STAT_SDMCOLDRST_SET_MSK 0x00000001
109 #define ALT_RSTMGR_STAT_SDMCOLDRST_CLR_MSK 0xfffffffe
111 #define ALT_RSTMGR_STAT_SDMCOLDRST_RESET 0x0
113 #define ALT_RSTMGR_STAT_SDMCOLDRST_GET(value) (((value) & 0x00000001) >> 0)
115 #define ALT_RSTMGR_STAT_SDMCOLDRST_SET(value) (((value) << 0) & 0x00000001)
126 #define ALT_RSTMGR_STAT_SDMWARMRST_LSB 1
128 #define ALT_RSTMGR_STAT_SDMWARMRST_MSB 1
130 #define ALT_RSTMGR_STAT_SDMWARMRST_WIDTH 1
132 #define ALT_RSTMGR_STAT_SDMWARMRST_SET_MSK 0x00000002
134 #define ALT_RSTMGR_STAT_SDMWARMRST_CLR_MSK 0xfffffffd
136 #define ALT_RSTMGR_STAT_SDMWARMRST_RESET 0x0
138 #define ALT_RSTMGR_STAT_SDMWARMRST_GET(value) (((value) & 0x00000002) >> 1)
140 #define ALT_RSTMGR_STAT_SDMWARMRST_SET(value) (((value) << 1) & 0x00000002)
152 #define ALT_RSTMGR_STAT_SDMLASTPORRST_LSB 2
154 #define ALT_RSTMGR_STAT_SDMLASTPORRST_MSB 2
156 #define ALT_RSTMGR_STAT_SDMLASTPORRST_WIDTH 1
158 #define ALT_RSTMGR_STAT_SDMLASTPORRST_SET_MSK 0x00000004
160 #define ALT_RSTMGR_STAT_SDMLASTPORRST_CLR_MSK 0xfffffffb
162 #define ALT_RSTMGR_STAT_SDMLASTPORRST_RESET 0x1
164 #define ALT_RSTMGR_STAT_SDMLASTPORRST_GET(value) (((value) & 0x00000004) >> 2)
166 #define ALT_RSTMGR_STAT_SDMLASTPORRST_SET(value) (((value) << 2) & 0x00000004)
177 #define ALT_RSTMGR_STAT_MPU0RST_LSB 8
179 #define ALT_RSTMGR_STAT_MPU0RST_MSB 8
181 #define ALT_RSTMGR_STAT_MPU0RST_WIDTH 1
183 #define ALT_RSTMGR_STAT_MPU0RST_SET_MSK 0x00000100
185 #define ALT_RSTMGR_STAT_MPU0RST_CLR_MSK 0xfffffeff
187 #define ALT_RSTMGR_STAT_MPU0RST_RESET 0x0
189 #define ALT_RSTMGR_STAT_MPU0RST_GET(value) (((value) & 0x00000100) >> 8)
191 #define ALT_RSTMGR_STAT_MPU0RST_SET(value) (((value) << 8) & 0x00000100)
202 #define ALT_RSTMGR_STAT_MPU1RST_LSB 9
204 #define ALT_RSTMGR_STAT_MPU1RST_MSB 9
206 #define ALT_RSTMGR_STAT_MPU1RST_WIDTH 1
208 #define ALT_RSTMGR_STAT_MPU1RST_SET_MSK 0x00000200
210 #define ALT_RSTMGR_STAT_MPU1RST_CLR_MSK 0xfffffdff
212 #define ALT_RSTMGR_STAT_MPU1RST_RESET 0x0
214 #define ALT_RSTMGR_STAT_MPU1RST_GET(value) (((value) & 0x00000200) >> 9)
216 #define ALT_RSTMGR_STAT_MPU1RST_SET(value) (((value) << 9) & 0x00000200)
227 #define ALT_RSTMGR_STAT_MPU2RST_LSB 10
229 #define ALT_RSTMGR_STAT_MPU2RST_MSB 10
231 #define ALT_RSTMGR_STAT_MPU2RST_WIDTH 1
233 #define ALT_RSTMGR_STAT_MPU2RST_SET_MSK 0x00000400
235 #define ALT_RSTMGR_STAT_MPU2RST_CLR_MSK 0xfffffbff
237 #define ALT_RSTMGR_STAT_MPU2RST_RESET 0x0
239 #define ALT_RSTMGR_STAT_MPU2RST_GET(value) (((value) & 0x00000400) >> 10)
241 #define ALT_RSTMGR_STAT_MPU2RST_SET(value) (((value) << 10) & 0x00000400)
252 #define ALT_RSTMGR_STAT_MPU3RST_LSB 11
254 #define ALT_RSTMGR_STAT_MPU3RST_MSB 11
256 #define ALT_RSTMGR_STAT_MPU3RST_WIDTH 1
258 #define ALT_RSTMGR_STAT_MPU3RST_SET_MSK 0x00000800
260 #define ALT_RSTMGR_STAT_MPU3RST_CLR_MSK 0xfffff7ff
262 #define ALT_RSTMGR_STAT_MPU3RST_RESET 0x0
264 #define ALT_RSTMGR_STAT_MPU3RST_GET(value) (((value) & 0x00000800) >> 11)
266 #define ALT_RSTMGR_STAT_MPU3RST_SET(value) (((value) << 11) & 0x00000800)
277 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 16
279 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 16
281 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
283 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00010000
285 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xfffeffff
287 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
289 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00010000) >> 16)
291 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 16) & 0x00010000)
302 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 17
304 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 17
306 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
308 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00020000
310 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xfffdffff
312 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
314 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00020000) >> 17)
316 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 17) & 0x00020000)
327 #define ALT_RSTMGR_STAT_L4WD2RST_LSB 18
329 #define ALT_RSTMGR_STAT_L4WD2RST_MSB 18
331 #define ALT_RSTMGR_STAT_L4WD2RST_WIDTH 1
333 #define ALT_RSTMGR_STAT_L4WD2RST_SET_MSK 0x00040000
335 #define ALT_RSTMGR_STAT_L4WD2RST_CLR_MSK 0xfffbffff
337 #define ALT_RSTMGR_STAT_L4WD2RST_RESET 0x0
339 #define ALT_RSTMGR_STAT_L4WD2RST_GET(value) (((value) & 0x00040000) >> 18)
341 #define ALT_RSTMGR_STAT_L4WD2RST_SET(value) (((value) << 18) & 0x00040000)
352 #define ALT_RSTMGR_STAT_L4WD3RST_LSB 19
354 #define ALT_RSTMGR_STAT_L4WD3RST_MSB 19
356 #define ALT_RSTMGR_STAT_L4WD3RST_WIDTH 1
358 #define ALT_RSTMGR_STAT_L4WD3RST_SET_MSK 0x00080000
360 #define ALT_RSTMGR_STAT_L4WD3RST_CLR_MSK 0xfff7ffff
362 #define ALT_RSTMGR_STAT_L4WD3RST_RESET 0x0
364 #define ALT_RSTMGR_STAT_L4WD3RST_GET(value) (((value) & 0x00080000) >> 19)
366 #define ALT_RSTMGR_STAT_L4WD3RST_SET(value) (((value) << 19) & 0x00080000)
378 #define ALT_RSTMGR_STAT_DEBUGRST_LSB 24
380 #define ALT_RSTMGR_STAT_DEBUGRST_MSB 24
382 #define ALT_RSTMGR_STAT_DEBUGRST_WIDTH 1
384 #define ALT_RSTMGR_STAT_DEBUGRST_SET_MSK 0x01000000
386 #define ALT_RSTMGR_STAT_DEBUGRST_CLR_MSK 0xfeffffff
388 #define ALT_RSTMGR_STAT_DEBUGRST_RESET 0x0
390 #define ALT_RSTMGR_STAT_DEBUGRST_GET(value) (((value) & 0x01000000) >> 24)
392 #define ALT_RSTMGR_STAT_DEBUGRST_SET(value) (((value) << 24) & 0x01000000)
404 #define ALT_RSTMGR_STAT_CSDAPRST_LSB 25
406 #define ALT_RSTMGR_STAT_CSDAPRST_MSB 25
408 #define ALT_RSTMGR_STAT_CSDAPRST_WIDTH 1
410 #define ALT_RSTMGR_STAT_CSDAPRST_SET_MSK 0x02000000
412 #define ALT_RSTMGR_STAT_CSDAPRST_CLR_MSK 0xfdffffff
414 #define ALT_RSTMGR_STAT_CSDAPRST_RESET 0x0
416 #define ALT_RSTMGR_STAT_CSDAPRST_GET(value) (((value) & 0x02000000) >> 25)
418 #define ALT_RSTMGR_STAT_CSDAPRST_SET(value) (((value) << 25) & 0x02000000)
432 struct ALT_RSTMGR_STAT_s
434 volatile uint32_t sdmcoldrst : 1;
435 volatile uint32_t sdmwarmrst : 1;
436 volatile uint32_t sdmlastporrst : 1;
438 volatile uint32_t mpu0rst : 1;
439 volatile uint32_t mpu1rst : 1;
440 volatile uint32_t mpu2rst : 1;
441 volatile uint32_t mpu3rst : 1;
443 volatile uint32_t l4wd0rst : 1;
444 volatile uint32_t l4wd1rst : 1;
445 volatile uint32_t l4wd2rst : 1;
446 volatile uint32_t l4wd3rst : 1;
448 volatile uint32_t debugrst : 1;
449 volatile uint32_t csdaprst : 1;
454 typedef struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
458 #define ALT_RSTMGR_STAT_RESET 0x00000004
460 #define ALT_RSTMGR_STAT_OFST 0x0
500 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_LSB 0
502 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_MSB 0
504 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_WIDTH 1
506 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_SET_MSK 0x00000001
508 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_CLR_MSK 0xfffffffe
510 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_RESET 0x0
512 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_GET(value) (((value) & 0x00000001) >> 0)
514 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR0_IRQ_SET(value) (((value) << 0) & 0x00000001)
526 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_LSB 1
528 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_MSB 1
530 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_WIDTH 1
532 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_SET_MSK 0x00000002
534 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_CLR_MSK 0xfffffffd
536 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_RESET 0x0
538 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_GET(value) (((value) & 0x00000002) >> 1)
540 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR1_IRQ_SET(value) (((value) << 1) & 0x00000002)
552 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_LSB 2
554 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_MSB 2
556 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_WIDTH 1
558 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_SET_MSK 0x00000004
560 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_CLR_MSK 0xfffffffb
562 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_RESET 0x0
564 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_GET(value) (((value) & 0x00000004) >> 2)
566 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR2_IRQ_SET(value) (((value) << 2) & 0x00000004)
578 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_LSB 3
580 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_MSB 3
582 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_WIDTH 1
584 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_SET_MSK 0x00000008
586 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_CLR_MSK 0xfffffff7
588 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_RESET 0x0
590 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_GET(value) (((value) & 0x00000008) >> 3)
592 #define ALT_RSTMGR_MPURSTSTAT_CPUPOR3_IRQ_SET(value) (((value) << 3) & 0x00000008)
604 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_LSB 8
606 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_MSB 8
608 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_WIDTH 1
610 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_SET_MSK 0x00000100
612 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_CLR_MSK 0xfffffeff
614 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_RESET 0x0
616 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_GET(value) (((value) & 0x00000100) >> 8)
618 #define ALT_RSTMGR_MPURSTSTAT_CORE0_IRQ_SET(value) (((value) << 8) & 0x00000100)
630 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_LSB 9
632 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_MSB 9
634 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_WIDTH 1
636 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_SET_MSK 0x00000200
638 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_CLR_MSK 0xfffffdff
640 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_RESET 0x0
642 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_GET(value) (((value) & 0x00000200) >> 9)
644 #define ALT_RSTMGR_MPURSTSTAT_CORE1_IRQ_SET(value) (((value) << 9) & 0x00000200)
656 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_LSB 10
658 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_MSB 10
660 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_WIDTH 1
662 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_SET_MSK 0x00000400
664 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_CLR_MSK 0xfffffbff
666 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_RESET 0x0
668 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_GET(value) (((value) & 0x00000400) >> 10)
670 #define ALT_RSTMGR_MPURSTSTAT_CORE2_IRQ_SET(value) (((value) << 10) & 0x00000400)
682 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_LSB 11
684 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_MSB 11
686 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_WIDTH 1
688 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_SET_MSK 0x00000800
690 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_CLR_MSK 0xfffff7ff
692 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_RESET 0x0
694 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_GET(value) (((value) & 0x00000800) >> 11)
696 #define ALT_RSTMGR_MPURSTSTAT_CORE3_IRQ_SET(value) (((value) << 11) & 0x00000800)
710 struct ALT_RSTMGR_MPURSTSTAT_s
712 volatile uint32_t cpupor0_irq : 1;
713 volatile uint32_t cpupor1_irq : 1;
714 volatile uint32_t cpupor2_irq : 1;
715 volatile uint32_t cpupor3_irq : 1;
717 volatile uint32_t core0_irq : 1;
718 volatile uint32_t core1_irq : 1;
719 volatile uint32_t core2_irq : 1;
720 volatile uint32_t core3_irq : 1;
725 typedef struct ALT_RSTMGR_MPURSTSTAT_s ALT_RSTMGR_MPURSTSTAT_t;
729 #define ALT_RSTMGR_MPURSTSTAT_RESET 0x00000000
731 #define ALT_RSTMGR_MPURSTSTAT_OFST 0x4
770 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_LSB 0
772 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_MSB 0
774 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_WIDTH 1
776 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_SET_MSK 0x00000001
778 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_CLR_MSK 0xfffffffe
780 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_RESET 0x0
782 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_GET(value) (((value) & 0x00000001) >> 0)
784 #define ALT_RSTMGR_MISCSTAT_SDRSELFREFTIMEOUT_SET(value) (((value) << 0) & 0x00000001)
797 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_LSB 2
799 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_MSB 2
801 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_WIDTH 1
803 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_SET_MSK 0x00000004
805 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_CLR_MSK 0xfffffffb
807 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_RESET 0x0
809 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_GET(value) (((value) & 0x00000004) >> 2)
811 #define ALT_RSTMGR_MISCSTAT_FPGAHSTIMEOUT_SET(value) (((value) << 2) & 0x00000004)
825 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_LSB 3
827 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_MSB 3
829 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_WIDTH 1
831 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_SET_MSK 0x00000008
833 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_CLR_MSK 0xfffffff7
835 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_RESET 0x0
837 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_GET(value) (((value) & 0x00000008) >> 3)
839 #define ALT_RSTMGR_MISCSTAT_ETRSTALLTIMEOUT_SET(value) (((value) << 3) & 0x00000008)
851 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_LSB 8
853 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_MSB 8
855 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_WIDTH 1
857 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_SET_MSK 0x00000100
859 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_CLR_MSK 0xfffffeff
861 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_RESET 0x0
863 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_GET(value) (((value) & 0x00000100) >> 8)
865 #define ALT_RSTMGR_MISCSTAT_MPUL2FLUSHTIMEOUT_SET(value) (((value) << 8) & 0x00000100)
879 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_LSB 16
881 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_MSB 16
883 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_WIDTH 1
885 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_SET_MSK 0x00010000
887 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_CLR_MSK 0xfffeffff
889 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_RESET 0x0
891 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_GET(value) (((value) & 0x00010000) >> 16)
893 #define ALT_RSTMGR_MISCSTAT_L3NOCDBGTIMEOUT_SET(value) (((value) << 16) & 0x00010000)
907 struct ALT_RSTMGR_MISCSTAT_s
909 volatile uint32_t sdrselfreftimeout : 1;
911 volatile uint32_t fpgahstimeout : 1;
912 volatile uint32_t etrstalltimeout : 1;
914 volatile uint32_t mpul2flushtimeout : 1;
916 volatile uint32_t l3nocdbgtimeout : 1;
921 typedef struct ALT_RSTMGR_MISCSTAT_s ALT_RSTMGR_MISCSTAT_t;
925 #define ALT_RSTMGR_MISCSTAT_RESET 0x00000000
927 #define ALT_RSTMGR_MISCSTAT_OFST 0x8
968 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB 0
970 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB 0
972 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH 1
974 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
976 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK 0xfffffffe
978 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET 0x0
980 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value) (((value) & 0x00000001) >> 0)
982 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value) (((value) << 0) & 0x00000001)
995 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB 2
997 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB 2
999 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH 1
1001 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
1003 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK 0xfffffffb
1005 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET 0x0
1007 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value) (((value) & 0x00000004) >> 2)
1009 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value) (((value) << 2) & 0x00000004)
1025 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB 3
1027 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB 3
1029 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH 1
1031 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
1033 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK 0xfffffff7
1035 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET 0x0
1037 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value) (((value) & 0x00000008) >> 3)
1039 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value) (((value) << 3) & 0x00000008)
1055 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_LSB 8
1057 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_MSB 8
1059 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_WIDTH 1
1061 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_SET_MSK 0x00000100
1063 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_CLR_MSK 0xfffffeff
1065 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_RESET 0x0
1067 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_GET(value) (((value) & 0x00000100) >> 8)
1069 #define ALT_RSTMGR_HDSKEN_L2FLUSHEN_SET(value) (((value) << 8) & 0x00000100)
1085 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_LSB 16
1087 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_MSB 16
1089 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_WIDTH 1
1091 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_SET_MSK 0x00010000
1093 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_CLR_MSK 0xfffeffff
1095 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_RESET 0x0
1097 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_GET(value) (((value) & 0x00010000) >> 16)
1099 #define ALT_RSTMGR_HDSKEN_L3NOC_DBG_SET(value) (((value) << 16) & 0x00010000)
1115 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_LSB 17
1117 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_MSB 17
1119 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_WIDTH 1
1121 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_SET_MSK 0x00020000
1123 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_CLR_MSK 0xfffdffff
1125 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_RESET 0x0
1127 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_GET(value) (((value) & 0x00020000) >> 17)
1129 #define ALT_RSTMGR_HDSKEN_DEBUG_L3NOC_SET(value) (((value) << 17) & 0x00020000)
1131 #ifndef __ASSEMBLY__
1143 struct ALT_RSTMGR_HDSKEN_s
1145 volatile uint32_t sdrselfrefen : 1;
1147 volatile uint32_t fpgahsen : 1;
1148 volatile uint32_t etrstallen : 1;
1150 volatile uint32_t l2flushen : 1;
1152 volatile uint32_t l3noc_dbg : 1;
1153 volatile uint32_t debug_l3noc : 1;
1158 typedef struct ALT_RSTMGR_HDSKEN_s ALT_RSTMGR_HDSKEN_t;
1162 #define ALT_RSTMGR_HDSKEN_RESET 0x00000000
1164 #define ALT_RSTMGR_HDSKEN_OFST 0x10
1207 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0
1209 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0
1211 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1
1213 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001
1215 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe
1217 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0
1219 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0)
1221 #define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001)
1235 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2
1237 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2
1239 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1
1241 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004
1243 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb
1245 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0
1247 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2)
1249 #define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004)
1265 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3
1267 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3
1269 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1
1271 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008
1273 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7
1275 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0
1277 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3)
1279 #define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008)
1294 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_LSB 4
1296 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_MSB 4
1298 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_WIDTH 1
1300 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_SET_MSK 0x00000010
1302 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_CLR_MSK 0xffffffef
1304 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_RESET 0x0
1306 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_GET(value) (((value) & 0x00000010) >> 4)
1308 #define ALT_RSTMGR_HDSKREQ_L3NOC_DBG_REQ_SET(value) (((value) << 4) & 0x00000010)
1325 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_LSB 5
1327 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_MSB 5
1329 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_WIDTH 1
1331 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_SET_MSK 0x00000020
1333 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_CLR_MSK 0xffffffdf
1335 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_RESET 0x0
1337 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_GET(value) (((value) & 0x00000020) >> 5)
1339 #define ALT_RSTMGR_HDSKREQ_DEBUG_L3NOC_REQ_SET(value) (((value) << 5) & 0x00000020)
1341 #ifndef __ASSEMBLY__
1353 struct ALT_RSTMGR_HDSKREQ_s
1355 volatile uint32_t sdrselfrefreq : 1;
1357 volatile uint32_t fpgahsreq : 1;
1358 volatile uint32_t etrstallreq : 1;
1359 volatile uint32_t l3noc_dbg_req : 1;
1360 volatile uint32_t debug_l3noc_req : 1;
1365 typedef struct ALT_RSTMGR_HDSKREQ_s ALT_RSTMGR_HDSKREQ_t;
1369 #define ALT_RSTMGR_HDSKREQ_RESET 0x00000000
1371 #define ALT_RSTMGR_HDSKREQ_OFST 0x14
1410 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB 0
1412 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB 0
1414 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH 1
1416 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK 0x00000001
1418 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK 0xfffffffe
1420 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET 0x0
1422 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value) (((value) & 0x00000001) >> 0)
1424 #define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value) (((value) << 0) & 0x00000001)
1437 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB 2
1439 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB 2
1441 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH 1
1443 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK 0x00000004
1445 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK 0xfffffffb
1447 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET 0x0
1449 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value) (((value) & 0x00000004) >> 2)
1451 #define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value) (((value) << 2) & 0x00000004)
1463 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB 3
1465 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB 3
1467 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH 1
1469 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK 0x00000008
1471 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK 0xfffffff7
1473 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET 0x0
1475 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value) (((value) & 0x00000008) >> 3)
1477 #define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value) (((value) << 3) & 0x00000008)
1494 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_LSB 4
1496 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_MSB 4
1498 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_WIDTH 1
1500 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_SET_MSK 0x00000010
1502 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_CLR_MSK 0xffffffef
1504 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_RESET 0x0
1506 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_GET(value) (((value) & 0x00000010) >> 4)
1508 #define ALT_RSTMGR_HDSKACK_L3NOC_DBG_ACK_SET(value) (((value) << 4) & 0x00000010)
1524 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_LSB 5
1526 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_MSB 5
1528 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_WIDTH 1
1530 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_SET_MSK 0x00000020
1532 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_CLR_MSK 0xffffffdf
1534 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_RESET 0x0
1536 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_GET(value) (((value) & 0x00000020) >> 5)
1538 #define ALT_RSTMGR_HDSKACK_DEBUG_L3NOC_ACK_SET(value) (((value) << 5) & 0x00000020)
1540 #ifndef __ASSEMBLY__
1552 struct ALT_RSTMGR_HDSKACK_s
1554 volatile uint32_t sdrselfreqack : 1;
1556 volatile uint32_t fpgahsack : 1;
1557 volatile uint32_t etrstallack : 1;
1558 volatile uint32_t l3noc_dbg_ack : 1;
1559 volatile uint32_t debug_l3noc_ack : 1;
1564 typedef struct ALT_RSTMGR_HDSKACK_s ALT_RSTMGR_HDSKACK_t;
1568 #define ALT_RSTMGR_HDSKACK_RESET 0x00000000
1570 #define ALT_RSTMGR_HDSKACK_OFST 0x18
1606 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_LSB 0
1608 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_MSB 0
1610 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_WIDTH 1
1612 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_SET_MSK 0x00000001
1614 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_CLR_MSK 0xfffffffe
1616 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_RESET 0x0
1618 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_GET(value) (((value) & 0x00000001) >> 0)
1620 #define ALT_RSTMGR_HDSKSTALL_ETRSTALLWARMRST_SET(value) (((value) << 0) & 0x00000001)
1622 #ifndef __ASSEMBLY__
1634 struct ALT_RSTMGR_HDSKSTALL_s
1636 volatile uint32_t etrstallwarmrst : 1;
1641 typedef struct ALT_RSTMGR_HDSKSTALL_s ALT_RSTMGR_HDSKSTALL_t;
1645 #define ALT_RSTMGR_HDSKSTALL_RESET 0x00000000
1647 #define ALT_RSTMGR_HDSKSTALL_OFST 0x1c
1680 #define ALT_RSTMGR_MPUMODRST_CORE0_LSB 0
1682 #define ALT_RSTMGR_MPUMODRST_CORE0_MSB 0
1684 #define ALT_RSTMGR_MPUMODRST_CORE0_WIDTH 1
1686 #define ALT_RSTMGR_MPUMODRST_CORE0_SET_MSK 0x00000001
1688 #define ALT_RSTMGR_MPUMODRST_CORE0_CLR_MSK 0xfffffffe
1690 #define ALT_RSTMGR_MPUMODRST_CORE0_RESET 0x0
1692 #define ALT_RSTMGR_MPUMODRST_CORE0_GET(value) (((value) & 0x00000001) >> 0)
1694 #define ALT_RSTMGR_MPUMODRST_CORE0_SET(value) (((value) << 0) & 0x00000001)
1705 #define ALT_RSTMGR_MPUMODRST_CORE1_LSB 1
1707 #define ALT_RSTMGR_MPUMODRST_CORE1_MSB 1
1709 #define ALT_RSTMGR_MPUMODRST_CORE1_WIDTH 1
1711 #define ALT_RSTMGR_MPUMODRST_CORE1_SET_MSK 0x00000002
1713 #define ALT_RSTMGR_MPUMODRST_CORE1_CLR_MSK 0xfffffffd
1715 #define ALT_RSTMGR_MPUMODRST_CORE1_RESET 0x0
1717 #define ALT_RSTMGR_MPUMODRST_CORE1_GET(value) (((value) & 0x00000002) >> 1)
1719 #define ALT_RSTMGR_MPUMODRST_CORE1_SET(value) (((value) << 1) & 0x00000002)
1730 #define ALT_RSTMGR_MPUMODRST_CORE2_LSB 2
1732 #define ALT_RSTMGR_MPUMODRST_CORE2_MSB 2
1734 #define ALT_RSTMGR_MPUMODRST_CORE2_WIDTH 1
1736 #define ALT_RSTMGR_MPUMODRST_CORE2_SET_MSK 0x00000004
1738 #define ALT_RSTMGR_MPUMODRST_CORE2_CLR_MSK 0xfffffffb
1740 #define ALT_RSTMGR_MPUMODRST_CORE2_RESET 0x0
1742 #define ALT_RSTMGR_MPUMODRST_CORE2_GET(value) (((value) & 0x00000004) >> 2)
1744 #define ALT_RSTMGR_MPUMODRST_CORE2_SET(value) (((value) << 2) & 0x00000004)
1755 #define ALT_RSTMGR_MPUMODRST_CORE3_LSB 3
1757 #define ALT_RSTMGR_MPUMODRST_CORE3_MSB 3
1759 #define ALT_RSTMGR_MPUMODRST_CORE3_WIDTH 1
1761 #define ALT_RSTMGR_MPUMODRST_CORE3_SET_MSK 0x00000008
1763 #define ALT_RSTMGR_MPUMODRST_CORE3_CLR_MSK 0xfffffff7
1765 #define ALT_RSTMGR_MPUMODRST_CORE3_RESET 0x0
1767 #define ALT_RSTMGR_MPUMODRST_CORE3_GET(value) (((value) & 0x00000008) >> 3)
1769 #define ALT_RSTMGR_MPUMODRST_CORE3_SET(value) (((value) << 3) & 0x00000008)
1771 #ifndef __ASSEMBLY__
1783 struct ALT_RSTMGR_MPUMODRST_s
1785 volatile uint32_t core0 : 1;
1786 volatile uint32_t core1 : 1;
1787 volatile uint32_t core2 : 1;
1788 volatile uint32_t core3 : 1;
1793 typedef struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
1797 #define ALT_RSTMGR_MPUMODRST_RESET 0x00000000
1799 #define ALT_RSTMGR_MPUMODRST_OFST 0x20
1868 #define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0
1870 #define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0
1872 #define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1
1874 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
1876 #define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe
1878 #define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1
1880 #define ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1882 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1893 #define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1
1895 #define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1
1897 #define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1
1899 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
1901 #define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd
1903 #define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1
1905 #define ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1907 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1918 #define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2
1920 #define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2
1922 #define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1
1924 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
1926 #define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb
1928 #define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1
1930 #define ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
1932 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004)
1943 #define ALT_RSTMGR_PER0MODRST_USB0_LSB 3
1945 #define ALT_RSTMGR_PER0MODRST_USB0_MSB 3
1947 #define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1
1949 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
1951 #define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7
1953 #define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1
1955 #define ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3)
1957 #define ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008)
1968 #define ALT_RSTMGR_PER0MODRST_USB1_LSB 4
1970 #define ALT_RSTMGR_PER0MODRST_USB1_MSB 4
1972 #define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1
1974 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
1976 #define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef
1978 #define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1
1980 #define ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4)
1982 #define ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010)
1993 #define ALT_RSTMGR_PER0MODRST_NAND_LSB 5
1995 #define ALT_RSTMGR_PER0MODRST_NAND_MSB 5
1997 #define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1
1999 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
2001 #define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf
2003 #define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1
2005 #define ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5)
2007 #define ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020)
2018 #define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7
2020 #define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7
2022 #define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1
2024 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
2026 #define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f
2028 #define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1
2030 #define ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
2032 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080)
2043 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8
2045 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8
2047 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1
2049 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100
2051 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff
2053 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1
2055 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
2057 #define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
2068 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9
2070 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9
2072 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1
2074 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200
2076 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff
2078 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1
2080 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
2082 #define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
2093 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10
2095 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10
2097 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1
2099 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400
2101 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff
2103 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1
2105 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
2107 #define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
2118 #define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11
2120 #define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11
2122 #define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1
2124 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800
2126 #define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff
2128 #define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1
2130 #define ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
2132 #define ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
2143 #define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12
2145 #define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12
2147 #define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1
2149 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000
2151 #define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff
2153 #define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1
2155 #define ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
2157 #define ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
2168 #define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13
2170 #define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13
2172 #define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1
2174 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000
2176 #define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff
2178 #define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1
2180 #define ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
2182 #define ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
2193 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15
2195 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15
2197 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1
2199 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000
2201 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff
2203 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1
2205 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
2207 #define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
2218 #define ALT_RSTMGR_PER0MODRST_DMA_LSB 16
2220 #define ALT_RSTMGR_PER0MODRST_DMA_MSB 16
2222 #define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1
2224 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
2226 #define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff
2228 #define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1
2230 #define ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16)
2232 #define ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000)
2243 #define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17
2245 #define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17
2247 #define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1
2249 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
2251 #define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff
2253 #define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1
2255 #define ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
2257 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000)
2268 #define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18
2270 #define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18
2272 #define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1
2274 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
2276 #define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff
2278 #define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1
2280 #define ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
2282 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000)
2293 #define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19
2295 #define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19
2297 #define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1
2299 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
2301 #define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff
2303 #define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1
2305 #define ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
2307 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000)
2318 #define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20
2320 #define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20
2322 #define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1
2324 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
2326 #define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff
2328 #define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1
2330 #define ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
2332 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000)
2343 #define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21
2345 #define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21
2347 #define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1
2349 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000
2351 #define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff
2353 #define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1
2355 #define ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
2357 #define ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
2368 #define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22
2370 #define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22
2372 #define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1
2374 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
2376 #define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff
2378 #define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1
2380 #define ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
2382 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
2394 #define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24
2396 #define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24
2398 #define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1
2400 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
2402 #define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff
2404 #define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1
2406 #define ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
2408 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
2420 #define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25
2422 #define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25
2424 #define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1
2426 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
2428 #define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff
2430 #define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1
2432 #define ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
2434 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
2446 #define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26
2448 #define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26
2450 #define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1
2452 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
2454 #define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff
2456 #define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1
2458 #define ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
2460 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
2472 #define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27
2474 #define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27
2476 #define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1
2478 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
2480 #define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff
2482 #define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1
2484 #define ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
2486 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
2498 #define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28
2500 #define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28
2502 #define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1
2504 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
2506 #define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff
2508 #define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1
2510 #define ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
2512 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
2524 #define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29
2526 #define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29
2528 #define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1
2530 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
2532 #define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff
2534 #define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1
2536 #define ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
2538 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
2550 #define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30
2552 #define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30
2554 #define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1
2556 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
2558 #define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff
2560 #define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1
2562 #define ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
2564 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
2576 #define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31
2578 #define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31
2580 #define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1
2582 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
2584 #define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff
2586 #define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1
2588 #define ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
2590 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
2592 #ifndef __ASSEMBLY__
2604 struct ALT_RSTMGR_PER0MODRST_s
2606 volatile uint32_t emac0 : 1;
2607 volatile uint32_t emac1 : 1;
2608 volatile uint32_t emac2 : 1;
2609 volatile uint32_t usb0 : 1;
2610 volatile uint32_t usb1 : 1;
2611 volatile uint32_t nand : 1;
2613 volatile uint32_t sdmmc : 1;
2614 volatile uint32_t emac0ocp : 1;
2615 volatile uint32_t emac1ocp : 1;
2616 volatile uint32_t emac2ocp : 1;
2617 volatile uint32_t usb0ocp : 1;
2618 volatile uint32_t usb1ocp : 1;
2619 volatile uint32_t nandocp : 1;
2621 volatile uint32_t sdmmcocp : 1;
2622 volatile uint32_t dma : 1;
2623 volatile uint32_t spim0 : 1;
2624 volatile uint32_t spim1 : 1;
2625 volatile uint32_t spis0 : 1;
2626 volatile uint32_t spis1 : 1;
2627 volatile uint32_t dmaocp : 1;
2628 volatile uint32_t emacptp : 1;
2630 volatile uint32_t dmaif0 : 1;
2631 volatile uint32_t dmaif1 : 1;
2632 volatile uint32_t dmaif2 : 1;
2633 volatile uint32_t dmaif3 : 1;
2634 volatile uint32_t dmaif4 : 1;
2635 volatile uint32_t dmaif5 : 1;
2636 volatile uint32_t dmaif6 : 1;
2637 volatile uint32_t dmaif7 : 1;
2641 typedef struct ALT_RSTMGR_PER0MODRST_s ALT_RSTMGR_PER0MODRST_t;
2645 #define ALT_RSTMGR_PER0MODRST_RESET 0xffffffff
2647 #define ALT_RSTMGR_PER0MODRST_OFST 0x24
2708 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_LSB 0
2710 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_MSB 0
2712 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_WIDTH 1
2714 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_SET_MSK 0x00000001
2716 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_CLR_MSK 0xfffffffe
2718 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_RESET 0x1
2720 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_GET(value) (((value) & 0x00000001) >> 0)
2722 #define ALT_RSTMGR_PER1MODRST_WATCHDOG0_SET(value) (((value) << 0) & 0x00000001)
2733 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_LSB 1
2735 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_MSB 1
2737 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_WIDTH 1
2739 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_SET_MSK 0x00000002
2741 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_CLR_MSK 0xfffffffd
2743 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_RESET 0x1
2745 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_GET(value) (((value) & 0x00000002) >> 1)
2747 #define ALT_RSTMGR_PER1MODRST_WATCHDOG1_SET(value) (((value) << 1) & 0x00000002)
2758 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_LSB 2
2760 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_MSB 2
2762 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_WIDTH 1
2764 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_SET_MSK 0x00000004
2766 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_CLR_MSK 0xfffffffb
2768 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_RESET 0x1
2770 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_GET(value) (((value) & 0x00000004) >> 2)
2772 #define ALT_RSTMGR_PER1MODRST_WATCHDOG2_SET(value) (((value) << 2) & 0x00000004)
2783 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_LSB 3
2785 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_MSB 3
2787 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_WIDTH 1
2789 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_SET_MSK 0x00000008
2791 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_CLR_MSK 0xfffffff7
2793 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_RESET 0x1
2795 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_GET(value) (((value) & 0x00000008) >> 3)
2797 #define ALT_RSTMGR_PER1MODRST_WATCHDOG3_SET(value) (((value) << 3) & 0x00000008)
2808 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_LSB 4
2810 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_MSB 4
2812 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_WIDTH 1
2814 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_SET_MSK 0x00000010
2816 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_CLR_MSK 0xffffffef
2818 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_RESET 0x1
2820 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_GET(value) (((value) & 0x00000010) >> 4)
2822 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER0_SET(value) (((value) << 4) & 0x00000010)
2833 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_LSB 5
2835 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_MSB 5
2837 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_WIDTH 1
2839 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_SET_MSK 0x00000020
2841 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_CLR_MSK 0xffffffdf
2843 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_RESET 0x1
2845 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_GET(value) (((value) & 0x00000020) >> 5)
2847 #define ALT_RSTMGR_PER1MODRST_L4SYSTIMER1_SET(value) (((value) << 5) & 0x00000020)
2858 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_LSB 6
2860 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_MSB 6
2862 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_WIDTH 1
2864 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_SET_MSK 0x00000040
2866 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_CLR_MSK 0xffffffbf
2868 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_RESET 0x1
2870 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_GET(value) (((value) & 0x00000040) >> 6)
2872 #define ALT_RSTMGR_PER1MODRST_SPTIMER0_SET(value) (((value) << 6) & 0x00000040)
2883 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_LSB 7
2885 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_MSB 7
2887 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_WIDTH 1
2889 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_SET_MSK 0x00000080
2891 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_CLR_MSK 0xffffff7f
2893 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_RESET 0x1
2895 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_GET(value) (((value) & 0x00000080) >> 7)
2897 #define ALT_RSTMGR_PER1MODRST_SPTIMER1_SET(value) (((value) << 7) & 0x00000080)
2908 #define ALT_RSTMGR_PER1MODRST_I2C0_LSB 8
2910 #define ALT_RSTMGR_PER1MODRST_I2C0_MSB 8
2912 #define ALT_RSTMGR_PER1MODRST_I2C0_WIDTH 1
2914 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
2916 #define ALT_RSTMGR_PER1MODRST_I2C0_CLR_MSK 0xfffffeff
2918 #define ALT_RSTMGR_PER1MODRST_I2C0_RESET 0x1
2920 #define ALT_RSTMGR_PER1MODRST_I2C0_GET(value) (((value) & 0x00000100) >> 8)
2922 #define ALT_RSTMGR_PER1MODRST_I2C0_SET(value) (((value) << 8) & 0x00000100)
2933 #define ALT_RSTMGR_PER1MODRST_I2C1_LSB 9
2935 #define ALT_RSTMGR_PER1MODRST_I2C1_MSB 9
2937 #define ALT_RSTMGR_PER1MODRST_I2C1_WIDTH 1
2939 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
2941 #define ALT_RSTMGR_PER1MODRST_I2C1_CLR_MSK 0xfffffdff
2943 #define ALT_RSTMGR_PER1MODRST_I2C1_RESET 0x1
2945 #define ALT_RSTMGR_PER1MODRST_I2C1_GET(value) (((value) & 0x00000200) >> 9)
2947 #define ALT_RSTMGR_PER1MODRST_I2C1_SET(value) (((value) << 9) & 0x00000200)
2958 #define ALT_RSTMGR_PER1MODRST_I2C2_LSB 10
2960 #define ALT_RSTMGR_PER1MODRST_I2C2_MSB 10
2962 #define ALT_RSTMGR_PER1MODRST_I2C2_WIDTH 1
2964 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
2966 #define ALT_RSTMGR_PER1MODRST_I2C2_CLR_MSK 0xfffffbff
2968 #define ALT_RSTMGR_PER1MODRST_I2C2_RESET 0x1
2970 #define ALT_RSTMGR_PER1MODRST_I2C2_GET(value) (((value) & 0x00000400) >> 10)
2972 #define ALT_RSTMGR_PER1MODRST_I2C2_SET(value) (((value) << 10) & 0x00000400)
2983 #define ALT_RSTMGR_PER1MODRST_I2C3_LSB 11
2985 #define ALT_RSTMGR_PER1MODRST_I2C3_MSB 11
2987 #define ALT_RSTMGR_PER1MODRST_I2C3_WIDTH 1
2989 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
2991 #define ALT_RSTMGR_PER1MODRST_I2C3_CLR_MSK 0xfffff7ff
2993 #define ALT_RSTMGR_PER1MODRST_I2C3_RESET 0x1
2995 #define ALT_RSTMGR_PER1MODRST_I2C3_GET(value) (((value) & 0x00000800) >> 11)
2997 #define ALT_RSTMGR_PER1MODRST_I2C3_SET(value) (((value) << 11) & 0x00000800)
3008 #define ALT_RSTMGR_PER1MODRST_I2C4_LSB 12
3010 #define ALT_RSTMGR_PER1MODRST_I2C4_MSB 12
3012 #define ALT_RSTMGR_PER1MODRST_I2C4_WIDTH 1
3014 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
3016 #define ALT_RSTMGR_PER1MODRST_I2C4_CLR_MSK 0xffffefff
3018 #define ALT_RSTMGR_PER1MODRST_I2C4_RESET 0x1
3020 #define ALT_RSTMGR_PER1MODRST_I2C4_GET(value) (((value) & 0x00001000) >> 12)
3022 #define ALT_RSTMGR_PER1MODRST_I2C4_SET(value) (((value) << 12) & 0x00001000)
3033 #define ALT_RSTMGR_PER1MODRST_UART0_LSB 16
3035 #define ALT_RSTMGR_PER1MODRST_UART0_MSB 16
3037 #define ALT_RSTMGR_PER1MODRST_UART0_WIDTH 1
3039 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
3041 #define ALT_RSTMGR_PER1MODRST_UART0_CLR_MSK 0xfffeffff
3043 #define ALT_RSTMGR_PER1MODRST_UART0_RESET 0x1
3045 #define ALT_RSTMGR_PER1MODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
3047 #define ALT_RSTMGR_PER1MODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
3058 #define ALT_RSTMGR_PER1MODRST_UART1_LSB 17
3060 #define ALT_RSTMGR_PER1MODRST_UART1_MSB 17
3062 #define ALT_RSTMGR_PER1MODRST_UART1_WIDTH 1
3064 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
3066 #define ALT_RSTMGR_PER1MODRST_UART1_CLR_MSK 0xfffdffff
3068 #define ALT_RSTMGR_PER1MODRST_UART1_RESET 0x1
3070 #define ALT_RSTMGR_PER1MODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
3072 #define ALT_RSTMGR_PER1MODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
3083 #define ALT_RSTMGR_PER1MODRST_GPIO0_LSB 24
3085 #define ALT_RSTMGR_PER1MODRST_GPIO0_MSB 24
3087 #define ALT_RSTMGR_PER1MODRST_GPIO0_WIDTH 1
3089 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
3091 #define ALT_RSTMGR_PER1MODRST_GPIO0_CLR_MSK 0xfeffffff
3093 #define ALT_RSTMGR_PER1MODRST_GPIO0_RESET 0x1
3095 #define ALT_RSTMGR_PER1MODRST_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
3097 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET(value) (((value) << 24) & 0x01000000)
3108 #define ALT_RSTMGR_PER1MODRST_GPIO1_LSB 25
3110 #define ALT_RSTMGR_PER1MODRST_GPIO1_MSB 25
3112 #define ALT_RSTMGR_PER1MODRST_GPIO1_WIDTH 1
3114 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
3116 #define ALT_RSTMGR_PER1MODRST_GPIO1_CLR_MSK 0xfdffffff
3118 #define ALT_RSTMGR_PER1MODRST_GPIO1_RESET 0x1
3120 #define ALT_RSTMGR_PER1MODRST_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
3122 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET(value) (((value) << 25) & 0x02000000)
3124 #ifndef __ASSEMBLY__
3136 struct ALT_RSTMGR_PER1MODRST_s
3138 volatile uint32_t watchdog0 : 1;
3139 volatile uint32_t watchdog1 : 1;
3140 volatile uint32_t watchdog2 : 1;
3141 volatile uint32_t watchdog3 : 1;
3142 volatile uint32_t l4systimer0 : 1;
3143 volatile uint32_t l4systimer1 : 1;
3144 volatile uint32_t sptimer0 : 1;
3145 volatile uint32_t sptimer1 : 1;
3146 volatile uint32_t i2c0 : 1;
3147 volatile uint32_t i2c1 : 1;
3148 volatile uint32_t i2c2 : 1;
3149 volatile uint32_t i2c3 : 1;
3150 volatile uint32_t i2c4 : 1;
3152 volatile uint32_t uart0 : 1;
3153 volatile uint32_t uart1 : 1;
3155 volatile uint32_t gpio0 : 1;
3156 volatile uint32_t gpio1 : 1;
3161 typedef struct ALT_RSTMGR_PER1MODRST_s ALT_RSTMGR_PER1MODRST_t;
3165 #define ALT_RSTMGR_PER1MODRST_RESET 0xffffffff
3167 #define ALT_RSTMGR_PER1MODRST_OFST 0x28
3212 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_LSB 0
3214 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_MSB 0
3216 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_WIDTH 1
3218 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_SET_MSK 0x00000001
3220 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_CLR_MSK 0xfffffffe
3222 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_RESET 0x1
3224 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
3226 #define ALT_RSTMGR_BRGMODRST_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
3237 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_LSB 1
3239 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_MSB 1
3241 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_WIDTH 1
3243 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_SET_MSK 0x00000002
3245 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_CLR_MSK 0xfffffffd
3247 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_RESET 0x1
3249 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_GET(value) (((value) & 0x00000002) >> 1)
3251 #define ALT_RSTMGR_BRGMODRST_LWHPS2FPGA_SET(value) (((value) << 1) & 0x00000002)
3262 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_LSB 2
3264 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_MSB 2
3266 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_WIDTH 1
3268 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_SET_MSK 0x00000004
3270 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_CLR_MSK 0xfffffffb
3272 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_RESET 0x1
3274 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_GET(value) (((value) & 0x00000004) >> 2)
3276 #define ALT_RSTMGR_BRGMODRST_FPGA2SOC_SET(value) (((value) << 2) & 0x00000004)
3287 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_LSB 3
3289 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_MSB 3
3291 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_WIDTH 1
3293 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
3295 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_CLR_MSK 0xfffffff7
3297 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_RESET 0x1
3299 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3301 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3312 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_LSB 4
3314 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_MSB 4
3316 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_WIDTH 1
3318 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
3320 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_CLR_MSK 0xffffffef
3322 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_RESET 0x1
3324 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3326 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3337 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_LSB 5
3339 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_MSB 5
3341 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_WIDTH 1
3343 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
3345 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_CLR_MSK 0xffffffdf
3347 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_RESET 0x1
3349 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3351 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3362 #define ALT_RSTMGR_BRGMODRST_DDRSCH_LSB 6
3364 #define ALT_RSTMGR_BRGMODRST_DDRSCH_MSB 6
3366 #define ALT_RSTMGR_BRGMODRST_DDRSCH_WIDTH 1
3368 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
3370 #define ALT_RSTMGR_BRGMODRST_DDRSCH_CLR_MSK 0xffffffbf
3372 #define ALT_RSTMGR_BRGMODRST_DDRSCH_RESET 0x1
3374 #define ALT_RSTMGR_BRGMODRST_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3376 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3378 #ifndef __ASSEMBLY__
3390 struct ALT_RSTMGR_BRGMODRST_s
3392 volatile uint32_t soc2fpga : 1;
3393 volatile uint32_t lwhps2fpga : 1;
3394 volatile uint32_t fpga2soc : 1;
3395 volatile uint32_t f2ssdram0 : 1;
3396 volatile uint32_t f2ssdram1 : 1;
3397 volatile uint32_t f2ssdram2 : 1;
3398 volatile uint32_t ddrsch : 1;
3403 typedef struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
3407 #define ALT_RSTMGR_BRGMODRST_RESET 0xffffffff
3409 #define ALT_RSTMGR_BRGMODRST_OFST 0x2c
3443 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_LSB 0
3445 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_MSB 0
3447 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_WIDTH 1
3449 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_SET_MSK 0x00000001
3451 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_CLR_MSK 0xfffffffe
3453 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_RESET 0x0
3455 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_GET(value) (((value) & 0x00000001) >> 0)
3457 #define ALT_RSTMGR_COLDMODRST_CPUPOR0_SET(value) (((value) << 0) & 0x00000001)
3468 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_LSB 1
3470 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_MSB 1
3472 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_WIDTH 1
3474 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_SET_MSK 0x00000002
3476 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_CLR_MSK 0xfffffffd
3478 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_RESET 0x0
3480 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_GET(value) (((value) & 0x00000002) >> 1)
3482 #define ALT_RSTMGR_COLDMODRST_CPUPOR1_SET(value) (((value) << 1) & 0x00000002)
3493 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_LSB 2
3495 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_MSB 2
3497 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_WIDTH 1
3499 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_SET_MSK 0x00000004
3501 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_CLR_MSK 0xfffffffb
3503 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_RESET 0x0
3505 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_GET(value) (((value) & 0x00000004) >> 2)
3507 #define ALT_RSTMGR_COLDMODRST_CPUPOR2_SET(value) (((value) << 2) & 0x00000004)
3518 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_LSB 3
3520 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_MSB 3
3522 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_WIDTH 1
3524 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_SET_MSK 0x00000008
3526 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_CLR_MSK 0xfffffff7
3528 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_RESET 0x0
3530 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_GET(value) (((value) & 0x00000008) >> 3)
3532 #define ALT_RSTMGR_COLDMODRST_CPUPOR3_SET(value) (((value) << 3) & 0x00000008)
3543 #define ALT_RSTMGR_COLDMODRST_L2_LSB 8
3545 #define ALT_RSTMGR_COLDMODRST_L2_MSB 8
3547 #define ALT_RSTMGR_COLDMODRST_L2_WIDTH 1
3549 #define ALT_RSTMGR_COLDMODRST_L2_SET_MSK 0x00000100
3551 #define ALT_RSTMGR_COLDMODRST_L2_CLR_MSK 0xfffffeff
3553 #define ALT_RSTMGR_COLDMODRST_L2_RESET 0x0
3555 #define ALT_RSTMGR_COLDMODRST_L2_GET(value) (((value) & 0x00000100) >> 8)
3557 #define ALT_RSTMGR_COLDMODRST_L2_SET(value) (((value) << 8) & 0x00000100)
3559 #ifndef __ASSEMBLY__
3571 struct ALT_RSTMGR_COLDMODRST_s
3573 volatile uint32_t cpupor0 : 1;
3574 volatile uint32_t cpupor1 : 1;
3575 volatile uint32_t cpupor2 : 1;
3576 volatile uint32_t cpupor3 : 1;
3578 volatile uint32_t l2 : 1;
3583 typedef struct ALT_RSTMGR_COLDMODRST_s ALT_RSTMGR_COLDMODRST_t;
3587 #define ALT_RSTMGR_COLDMODRST_RESET 0x00000000
3589 #define ALT_RSTMGR_COLDMODRST_OFST 0x34
3637 #define ALT_RSTMGR_DBGMODRST_DBG_RST_LSB 0
3639 #define ALT_RSTMGR_DBGMODRST_DBG_RST_MSB 0
3641 #define ALT_RSTMGR_DBGMODRST_DBG_RST_WIDTH 1
3643 #define ALT_RSTMGR_DBGMODRST_DBG_RST_SET_MSK 0x00000001
3645 #define ALT_RSTMGR_DBGMODRST_DBG_RST_CLR_MSK 0xfffffffe
3647 #define ALT_RSTMGR_DBGMODRST_DBG_RST_RESET 0x0
3649 #define ALT_RSTMGR_DBGMODRST_DBG_RST_GET(value) (((value) & 0x00000001) >> 0)
3651 #define ALT_RSTMGR_DBGMODRST_DBG_RST_SET(value) (((value) << 0) & 0x00000001)
3662 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_LSB 1
3664 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_MSB 1
3666 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_WIDTH 1
3668 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_SET_MSK 0x00000002
3670 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_CLR_MSK 0xfffffffd
3672 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_RESET 0x0
3674 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_GET(value) (((value) & 0x00000002) >> 1)
3676 #define ALT_RSTMGR_DBGMODRST_CSDAP_RST_SET(value) (((value) << 1) & 0x00000002)
3678 #ifndef __ASSEMBLY__
3690 struct ALT_RSTMGR_DBGMODRST_s
3692 volatile uint32_t dbg_rst : 1;
3693 volatile uint32_t csdap_rst : 1;
3698 typedef struct ALT_RSTMGR_DBGMODRST_s ALT_RSTMGR_DBGMODRST_t;
3702 #define ALT_RSTMGR_DBGMODRST_RESET 0x00000000
3704 #define ALT_RSTMGR_DBGMODRST_OFST 0x3c
3734 #define ALT_RSTMGR_TAPMODRST_TAP_LSB 0
3736 #define ALT_RSTMGR_TAPMODRST_TAP_MSB 0
3738 #define ALT_RSTMGR_TAPMODRST_TAP_WIDTH 1
3740 #define ALT_RSTMGR_TAPMODRST_TAP_SET_MSK 0x00000001
3742 #define ALT_RSTMGR_TAPMODRST_TAP_CLR_MSK 0xfffffffe
3744 #define ALT_RSTMGR_TAPMODRST_TAP_RESET 0x0
3746 #define ALT_RSTMGR_TAPMODRST_TAP_GET(value) (((value) & 0x00000001) >> 0)
3748 #define ALT_RSTMGR_TAPMODRST_TAP_SET(value) (((value) << 0) & 0x00000001)
3750 #ifndef __ASSEMBLY__
3762 struct ALT_RSTMGR_TAPMODRST_s
3764 volatile uint32_t tap : 1;
3769 typedef struct ALT_RSTMGR_TAPMODRST_s ALT_RSTMGR_TAPMODRST_t;
3773 #define ALT_RSTMGR_TAPMODRST_RESET 0x00000000
3775 #define ALT_RSTMGR_TAPMODRST_OFST 0x40
3811 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_LSB 0
3813 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_MSB 0
3815 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_WIDTH 1
3817 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_SET_MSK 0x00000001
3819 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_CLR_MSK 0xfffffffe
3821 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_RESET 0x1
3823 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_GET(value) (((value) & 0x00000001) >> 0)
3825 #define ALT_RSTMGR_BRGWARMMASK_SOC2FPGA_SET(value) (((value) << 0) & 0x00000001)
3836 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_LSB 1
3838 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_MSB 1
3840 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_WIDTH 1
3842 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_SET_MSK 0x00000002
3844 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_CLR_MSK 0xfffffffd
3846 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_RESET 0x1
3848 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_GET(value) (((value) & 0x00000002) >> 1)
3850 #define ALT_RSTMGR_BRGWARMMASK_LWHPS2FPGA_SET(value) (((value) << 1) & 0x00000002)
3861 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_LSB 2
3863 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_MSB 2
3865 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_WIDTH 1
3867 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_SET_MSK 0x00000004
3869 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_CLR_MSK 0xfffffffb
3871 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_RESET 0x1
3873 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_GET(value) (((value) & 0x00000004) >> 2)
3875 #define ALT_RSTMGR_BRGWARMMASK_FPGA2SOC_SET(value) (((value) << 2) & 0x00000004)
3886 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_LSB 3
3888 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_MSB 3
3890 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_WIDTH 1
3892 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_SET_MSK 0x00000008
3894 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_CLR_MSK 0xfffffff7
3896 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_RESET 0x1
3898 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3900 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3911 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_LSB 4
3913 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_MSB 4
3915 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_WIDTH 1
3917 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_SET_MSK 0x00000010
3919 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_CLR_MSK 0xffffffef
3921 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_RESET 0x1
3923 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3925 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3936 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_LSB 5
3938 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_MSB 5
3940 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_WIDTH 1
3942 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_SET_MSK 0x00000020
3944 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_CLR_MSK 0xffffffdf
3946 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_RESET 0x1
3948 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3950 #define ALT_RSTMGR_BRGWARMMASK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3961 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_LSB 6
3963 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_MSB 6
3965 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_WIDTH 1
3967 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_SET_MSK 0x00000040
3969 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_CLR_MSK 0xffffffbf
3971 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_RESET 0x1
3973 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3975 #define ALT_RSTMGR_BRGWARMMASK_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3977 #ifndef __ASSEMBLY__
3989 struct ALT_RSTMGR_BRGWARMMASK_s
3991 volatile uint32_t soc2fpga : 1;
3992 volatile uint32_t lwhps2fpga : 1;
3993 volatile uint32_t fpga2soc : 1;
3994 volatile uint32_t f2ssdram0 : 1;
3995 volatile uint32_t f2ssdram1 : 1;
3996 volatile uint32_t f2ssdram2 : 1;
3997 volatile uint32_t ddrsch : 1;
4002 typedef struct ALT_RSTMGR_BRGWARMMASK_s ALT_RSTMGR_BRGWARMMASK_t;
4006 #define ALT_RSTMGR_BRGWARMMASK_RESET 0xffffffff
4008 #define ALT_RSTMGR_BRGWARMMASK_OFST 0x4c
4032 #define ALT_RSTMGR_TSTSTA_RSTST_LSB 0
4034 #define ALT_RSTMGR_TSTSTA_RSTST_MSB 4
4036 #define ALT_RSTMGR_TSTSTA_RSTST_WIDTH 5
4038 #define ALT_RSTMGR_TSTSTA_RSTST_SET_MSK 0x0000001f
4040 #define ALT_RSTMGR_TSTSTA_RSTST_CLR_MSK 0xffffffe0
4042 #define ALT_RSTMGR_TSTSTA_RSTST_RESET 0x0
4044 #define ALT_RSTMGR_TSTSTA_RSTST_GET(value) (((value) & 0x0000001f) >> 0)
4046 #define ALT_RSTMGR_TSTSTA_RSTST_SET(value) (((value) << 0) & 0x0000001f)
4048 #ifndef __ASSEMBLY__
4060 struct ALT_RSTMGR_TSTSTA_s
4062 const volatile uint32_t rstst : 5;
4067 typedef struct ALT_RSTMGR_TSTSTA_s ALT_RSTMGR_TSTSTA_t;
4071 #define ALT_RSTMGR_TSTSTA_RESET 0x00000000
4073 #define ALT_RSTMGR_TSTSTA_OFST 0x5c
4100 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_LSB 0
4102 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_MSB 31
4104 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_WIDTH 32
4106 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_SET_MSK 0xffffffff
4108 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_CLR_MSK 0x00000000
4110 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_RESET 0x2800
4112 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4114 #define ALT_RSTMGR_HDSKTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4116 #ifndef __ASSEMBLY__
4128 struct ALT_RSTMGR_HDSKTIMEOUT_s
4130 volatile uint32_t val : 32;
4134 typedef struct ALT_RSTMGR_HDSKTIMEOUT_s ALT_RSTMGR_HDSKTIMEOUT_t;
4138 #define ALT_RSTMGR_HDSKTIMEOUT_RESET 0x00002800
4140 #define ALT_RSTMGR_HDSKTIMEOUT_OFST 0x64
4165 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_LSB 0
4167 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_MSB 31
4169 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_WIDTH 32
4171 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_SET_MSK 0xffffffff
4173 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_CLR_MSK 0x00000000
4175 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_RESET 0x100000
4177 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4179 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4181 #ifndef __ASSEMBLY__
4193 struct ALT_RSTMGR_MPUL2FLUSHTIMEOUT_s
4195 volatile uint32_t val : 32;
4199 typedef struct ALT_RSTMGR_MPUL2FLUSHTIMEOUT_s ALT_RSTMGR_MPUL2FLUSHTIMEOUT_t;
4203 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_RESET 0x00100000
4205 #define ALT_RSTMGR_MPUL2FLUSHTIMEOUT_OFST 0x68
4232 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_LSB 0
4234 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_MSB 31
4236 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_WIDTH 32
4238 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_SET_MSK 0xffffffff
4240 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_CLR_MSK 0x00000000
4242 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_RESET 0x100000
4244 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_GET(value) (((value) & 0xffffffff) >> 0)
4246 #define ALT_RSTMGR_DBGHDSKTIMEOUT_VAL_SET(value) (((value) << 0) & 0xffffffff)
4248 #ifndef __ASSEMBLY__
4260 struct ALT_RSTMGR_DBGHDSKTIMEOUT_s
4262 volatile uint32_t val : 32;
4266 typedef struct ALT_RSTMGR_DBGHDSKTIMEOUT_s ALT_RSTMGR_DBGHDSKTIMEOUT_t;
4270 #define ALT_RSTMGR_DBGHDSKTIMEOUT_RESET 0x00100000
4272 #define ALT_RSTMGR_DBGHDSKTIMEOUT_OFST 0x6c
4301 #define ALT_RSTMGR_OCRAMLOAD_DONE_LSB 0
4303 #define ALT_RSTMGR_OCRAMLOAD_DONE_MSB 0
4305 #define ALT_RSTMGR_OCRAMLOAD_DONE_WIDTH 1
4307 #define ALT_RSTMGR_OCRAMLOAD_DONE_SET_MSK 0x00000001
4309 #define ALT_RSTMGR_OCRAMLOAD_DONE_CLR_MSK 0xfffffffe
4311 #define ALT_RSTMGR_OCRAMLOAD_DONE_RESET 0x0
4313 #define ALT_RSTMGR_OCRAMLOAD_DONE_GET(value) (((value) & 0x00000001) >> 0)
4315 #define ALT_RSTMGR_OCRAMLOAD_DONE_SET(value) (((value) << 0) & 0x00000001)
4317 #ifndef __ASSEMBLY__
4329 struct ALT_RSTMGR_OCRAMLOAD_s
4331 volatile uint32_t done : 1;
4336 typedef struct ALT_RSTMGR_OCRAMLOAD_s ALT_RSTMGR_OCRAMLOAD_t;
4340 #define ALT_RSTMGR_OCRAMLOAD_RESET 0x00000000
4342 #define ALT_RSTMGR_OCRAMLOAD_OFST 0x80
4344 #ifndef __ASSEMBLY__
4358 volatile ALT_RSTMGR_STAT_t stat;
4359 volatile ALT_RSTMGR_MPURSTSTAT_t mpurststat;
4360 volatile ALT_RSTMGR_MISCSTAT_t miscstat;
4361 volatile uint32_t _pad_0xc_0xf;
4362 volatile ALT_RSTMGR_HDSKEN_t hdsken;
4363 volatile ALT_RSTMGR_HDSKREQ_t hdskreq;
4364 volatile ALT_RSTMGR_HDSKACK_t hdskack;
4365 volatile ALT_RSTMGR_HDSKSTALL_t hdskstall;
4366 volatile ALT_RSTMGR_MPUMODRST_t mpumodrst;
4367 volatile ALT_RSTMGR_PER0MODRST_t per0modrst;
4368 volatile ALT_RSTMGR_PER1MODRST_t per1modrst;
4369 volatile ALT_RSTMGR_BRGMODRST_t brgmodrst;
4370 volatile uint32_t _pad_0x30_0x33;
4371 volatile ALT_RSTMGR_COLDMODRST_t coldmodrst;
4372 volatile uint32_t _pad_0x38_0x3b;
4373 volatile ALT_RSTMGR_DBGMODRST_t dbgmodrst;
4374 volatile ALT_RSTMGR_TAPMODRST_t tapmodrst;
4375 volatile uint32_t _pad_0x44_0x4b[2];
4376 volatile ALT_RSTMGR_BRGWARMMASK_t brgwarmmask;
4377 volatile uint32_t _pad_0x50_0x5b[3];
4378 volatile ALT_RSTMGR_TSTSTA_t tststa;
4379 volatile uint32_t _pad_0x60_0x63;
4380 volatile ALT_RSTMGR_HDSKTIMEOUT_t hdsktimeout;
4381 volatile ALT_RSTMGR_MPUL2FLUSHTIMEOUT_t mpul2flushtimeout;
4382 volatile ALT_RSTMGR_DBGHDSKTIMEOUT_t dbghdsktimeout;
4383 volatile uint32_t _pad_0x70_0x7f[4];
4384 volatile ALT_RSTMGR_OCRAMLOAD_t ocramload;
4385 volatile uint32_t _pad_0x84_0x100[31];
4389 typedef struct ALT_RSTMGR_s ALT_RSTMGR_t;
4391 struct ALT_RSTMGR_raw_s
4393 volatile uint32_t stat;
4394 volatile uint32_t mpurststat;
4395 volatile uint32_t miscstat;
4396 volatile uint32_t _pad_0xc_0xf;
4397 volatile uint32_t hdsken;
4398 volatile uint32_t hdskreq;
4399 volatile uint32_t hdskack;
4400 volatile uint32_t hdskstall;
4401 volatile uint32_t mpumodrst;
4402 volatile uint32_t per0modrst;
4403 volatile uint32_t per1modrst;
4404 volatile uint32_t brgmodrst;
4405 volatile uint32_t _pad_0x30_0x33;
4406 volatile uint32_t coldmodrst;
4407 volatile uint32_t _pad_0x38_0x3b;
4408 volatile uint32_t dbgmodrst;
4409 volatile uint32_t tapmodrst;
4410 volatile uint32_t _pad_0x44_0x4b[2];
4411 volatile uint32_t brgwarmmask;
4412 volatile uint32_t _pad_0x50_0x5b[3];
4413 volatile uint32_t tststa;
4414 volatile uint32_t _pad_0x60_0x63;
4415 volatile uint32_t hdsktimeout;
4416 volatile uint32_t mpul2flushtimeout;
4417 volatile uint32_t dbghdsktimeout;
4418 volatile uint32_t _pad_0x70_0x7f[4];
4419 volatile uint32_t ocramload;
4420 volatile uint32_t _pad_0x84_0x100[31];
4424 typedef struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;