Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_mpu_usb0_m_main_qos.h
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32 
33 /* Altera - ALT_NOC_MPU_USB0_M_MAIN_QOS */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_USB0_M_MAIN_QOS_H__
36 #define __ALT_SOCAL_NOC_MPU_USB0_M_MAIN_QOS_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_USB0_M_MAIN_QOS
50  *
51  */
52 /*
53  * Register : usb0_m_I_main_QosGenerator_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:--------------------------------------------
59  * [7:0] | R | 0x4 | ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID
60  * [31:8] | R | 0x69bbc2 | ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_RESET 0x4
83 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_RESET 0x69bbc2
108 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID.
123  */
124 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID. */
131 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_s ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID register. */
135 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_RESET 0x69bbc204
136 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_OFST 0x0
138 
139 /*
140  * Register : usb0_m_I_main_QosGenerator_Id_RevisionId
141  *
142  * Register Layout
143  *
144  * Bits | Access | Reset | Description
145  * :-------|:-------|:--------|:--------------------------------------------
146  * [7:0] | R | 0x0 | ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID
147  * [31:8] | R | 0x129ff | ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID
148  *
149  */
150 /*
151  * Field : USERID
152  *
153  * Field containing a user defined value, not used anywhere inside the IP itself.
154  *
155  * Field Access Macros:
156  *
157  */
158 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field. */
159 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_LSB 0
160 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field. */
161 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_MSB 7
162 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field. */
163 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_WIDTH 8
164 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field value. */
165 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_SET_MSK 0x000000ff
166 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field value. */
167 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_CLR_MSK 0xffffff00
168 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field. */
169 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_RESET 0x0
170 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID field value from a register. */
171 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID register field value suitable for setting the register. */
173 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
175 /*
176  * Field : FLEXNOCID
177  *
178  * Field containing the build revision of the software used to generate the IP HDL
179  * code.
180  *
181  * Field Access Macros:
182  *
183  */
184 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field. */
185 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_LSB 8
186 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_MSB 31
188 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_WIDTH 24
190 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field value. */
191 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field. */
195 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_RESET 0x129ff
196 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID field value from a register. */
197 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID register field value suitable for setting the register. */
199 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 /*
203  * WARNING: The C register and register group struct declarations are provided for
204  * convenience and illustrative purposes. They should, however, be used with
205  * caution as the C language standard provides no guarantees about the alignment or
206  * atomicity of device memory accesses. The recommended practice for writing
207  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
208  * alt_write_word() functions.
209  *
210  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID.
211  */
212 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_s
213 {
214  const uint32_t USERID : 8; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_UID */
215  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_FLEXNOCID */
216 };
217 
218 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID. */
219 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_s ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_t;
220 #endif /* __ASSEMBLY__ */
221 
222 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID register. */
223 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_RESET 0x0129ff00
224 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID register from the beginning of the component. */
225 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_OFST 0x4
226 
227 /*
228  * Register : usb0_m_I_main_QosGenerator_Priority
229  *
230  * Priority register.
231  *
232  * Register Layout
233  *
234  * Bits | Access | Reset | Description
235  * :--------|:-------|:--------|:-------------------------------------
236  * [1:0] | RW | 0x0 | ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0
237  * [7:2] | ??? | Unknown | *UNDEFINED*
238  * [9:8] | RW | 0x1 | ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1
239  * [30:10] | ??? | Unknown | *UNDEFINED*
240  * [31] | R | 0x1 | ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK
241  *
242  */
243 /*
244  * Field : P0
245  *
246  * In Programmable or Bandwidth Limiter mode, the priority level for write
247  * transactions. In Bandwidth Regulator mode, the priority level when the used
248  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
249  * value equal or lower than P1.
250  *
251  * Field Access Macros:
252  *
253  */
254 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field. */
255 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_LSB 0
256 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field. */
257 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_MSB 1
258 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field. */
259 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_WIDTH 2
260 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field value. */
261 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_SET_MSK 0x00000003
262 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field value. */
263 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_CLR_MSK 0xfffffffc
264 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field. */
265 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_RESET 0x0
266 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 field value from a register. */
267 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_GET(value) (((value) & 0x00000003) >> 0)
268 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 register field value suitable for setting the register. */
269 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0_SET(value) (((value) << 0) & 0x00000003)
270 
271 /*
272  * Field : P1
273  *
274  * In Programmable or Bandwidth Limiter mode, the priority level for read
275  * transactions. In Bandwidth regulator mode, the priority level when the used
276  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
277  * value equal or greater than P0.
278  *
279  * Field Access Macros:
280  *
281  */
282 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field. */
283 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_LSB 8
284 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field. */
285 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_MSB 9
286 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field. */
287 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_WIDTH 2
288 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field value. */
289 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_SET_MSK 0x00000300
290 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field value. */
291 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_CLR_MSK 0xfffffcff
292 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field. */
293 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_RESET 0x1
294 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 field value from a register. */
295 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_GET(value) (((value) & 0x00000300) >> 8)
296 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 register field value suitable for setting the register. */
297 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1_SET(value) (((value) << 8) & 0x00000300)
298 
299 /*
300  * Field : MARK
301  *
302  * Backward compatibility marker when 0.
303  *
304  * Field Access Macros:
305  *
306  */
307 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field. */
308 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_LSB 31
309 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field. */
310 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_MSB 31
311 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field. */
312 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_WIDTH 1
313 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field value. */
314 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_SET_MSK 0x80000000
315 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field value. */
316 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_CLR_MSK 0x7fffffff
317 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field. */
318 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_RESET 0x1
319 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK field value from a register. */
320 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_GET(value) (((value) & 0x80000000) >> 31)
321 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK register field value suitable for setting the register. */
322 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK_SET(value) (((value) << 31) & 0x80000000)
323 
324 #ifndef __ASSEMBLY__
325 /*
326  * WARNING: The C register and register group struct declarations are provided for
327  * convenience and illustrative purposes. They should, however, be used with
328  * caution as the C language standard provides no guarantees about the alignment or
329  * atomicity of device memory accesses. The recommended practice for writing
330  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
331  * alt_write_word() functions.
332  *
333  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI.
334  */
335 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_s
336 {
337  uint32_t P0 : 2; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P0 */
338  uint32_t : 6; /* *UNDEFINED* */
339  uint32_t P1 : 2; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_P1 */
340  uint32_t : 21; /* *UNDEFINED* */
341  const uint32_t MARK : 1; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_MARK */
342 };
343 
344 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI. */
345 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_s ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_t;
346 #endif /* __ASSEMBLY__ */
347 
348 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI register. */
349 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_RESET 0x80000100
350 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI register from the beginning of the component. */
351 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_OFST 0x8
352 
353 /*
354  * Register : usb0_m_I_main_QosGenerator_Mode
355  *
356  *
357  * Register Layout
358  *
359  * Bits | Access | Reset | Description
360  * :-------|:-------|:--------|:------------------------------------
361  * [1:0] | RW | 0x3 | ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD
362  * [31:2] | ??? | Unknown | *UNDEFINED*
363  *
364  */
365 /*
366  * Field : MODE
367  *
368  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
369  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
370  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
371  * priority decreases when throughput exceeds a threshold.
372  *
373  * Field Access Macros:
374  *
375  */
376 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field. */
377 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_LSB 0
378 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field. */
379 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_MSB 1
380 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field. */
381 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_WIDTH 2
382 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field value. */
383 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_SET_MSK 0x00000003
384 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field value. */
385 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_CLR_MSK 0xfffffffc
386 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field. */
387 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_RESET 0x3
388 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD field value from a register. */
389 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_GET(value) (((value) & 0x00000003) >> 0)
390 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD register field value suitable for setting the register. */
391 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD_SET(value) (((value) << 0) & 0x00000003)
392 
393 #ifndef __ASSEMBLY__
394 /*
395  * WARNING: The C register and register group struct declarations are provided for
396  * convenience and illustrative purposes. They should, however, be used with
397  * caution as the C language standard provides no guarantees about the alignment or
398  * atomicity of device memory accesses. The recommended practice for writing
399  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
400  * alt_write_word() functions.
401  *
402  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD.
403  */
404 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_s
405 {
406  uint32_t MODE : 2; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_MOD */
407  uint32_t : 30; /* *UNDEFINED* */
408 };
409 
410 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD. */
411 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_s ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_t;
412 #endif /* __ASSEMBLY__ */
413 
414 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD register. */
415 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_RESET 0x00000003
416 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD register from the beginning of the component. */
417 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_OFST 0xc
418 
419 /*
420  * Register : usb0_m_I_main_QosGenerator_Bandwidth
421  *
422  *
423  * Register Layout
424  *
425  * Bits | Access | Reset | Description
426  * :--------|:-------|:--------|:--------------------------------------------
427  * [10:0] | RW | 0x100 | ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH
428  * [31:11] | ??? | Unknown | *UNDEFINED*
429  *
430  */
431 /*
432  * Field : BANDWIDTH
433  *
434  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
435  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
436  * value 0x0052.
437  *
438  * Field Access Macros:
439  *
440  */
441 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field. */
442 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_LSB 0
443 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field. */
444 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_MSB 10
445 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field. */
446 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_WIDTH 11
447 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field value. */
448 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_SET_MSK 0x000007ff
449 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field value. */
450 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_CLR_MSK 0xfffff800
451 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field. */
452 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_RESET 0x100
453 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH field value from a register. */
454 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_GET(value) (((value) & 0x000007ff) >> 0)
455 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH register field value suitable for setting the register. */
456 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x000007ff)
457 
458 #ifndef __ASSEMBLY__
459 /*
460  * WARNING: The C register and register group struct declarations are provided for
461  * convenience and illustrative purposes. They should, however, be used with
462  * caution as the C language standard provides no guarantees about the alignment or
463  * atomicity of device memory accesses. The recommended practice for writing
464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
465  * alt_write_word() functions.
466  *
467  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH.
468  */
469 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_s
470 {
471  uint32_t BANDWIDTH : 11; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_BANDWIDTH */
472  uint32_t : 21; /* *UNDEFINED* */
473 };
474 
475 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH. */
476 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_s ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_t;
477 #endif /* __ASSEMBLY__ */
478 
479 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH register. */
480 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_RESET 0x00000100
481 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH register from the beginning of the component. */
482 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_OFST 0x10
483 
484 /*
485  * Register : usb0_m_I_main_QosGenerator_Saturation
486  *
487  *
488  * Register Layout
489  *
490  * Bits | Access | Reset | Description
491  * :--------|:-------|:--------|:-------------------------------------------
492  * [9:0] | RW | 0x4 | ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION
493  * [31:10] | ??? | Unknown | *UNDEFINED*
494  *
495  */
496 /*
497  * Field : SATURATION
498  *
499  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
500  * in units of 16 bytes. This determines the window of time over which bandwidth is
501  * measured. For example, to measure bandwidth within a 1000 cycle window on a
502  * 64-bit interface is value 0x1F4.
503  *
504  * Field Access Macros:
505  *
506  */
507 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field. */
508 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_LSB 0
509 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field. */
510 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_MSB 9
511 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field. */
512 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_WIDTH 10
513 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field value. */
514 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_SET_MSK 0x000003ff
515 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field value. */
516 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_CLR_MSK 0xfffffc00
517 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field. */
518 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_RESET 0x4
519 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION field value from a register. */
520 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
521 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION register field value suitable for setting the register. */
522 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
523 
524 #ifndef __ASSEMBLY__
525 /*
526  * WARNING: The C register and register group struct declarations are provided for
527  * convenience and illustrative purposes. They should, however, be used with
528  * caution as the C language standard provides no guarantees about the alignment or
529  * atomicity of device memory accesses. The recommended practice for writing
530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
531  * alt_write_word() functions.
532  *
533  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT.
534  */
535 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_s
536 {
537  uint32_t SATURATION : 10; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_SATURATION */
538  uint32_t : 22; /* *UNDEFINED* */
539 };
540 
541 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT. */
542 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_s ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_t;
543 #endif /* __ASSEMBLY__ */
544 
545 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT register. */
546 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_RESET 0x00000004
547 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT register from the beginning of the component. */
548 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_OFST 0x14
549 
550 /*
551  * Register : usb0_m_I_main_QosGenerator_ExtControl
552  *
553  * External inputs control.
554  *
555  * Register Layout
556  *
557  * Bits | Access | Reset | Description
558  * :-------|:-------|:--------|:-----------------------------------------------
559  * [0] | RW | 0x0 | ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN
560  * [1] | RW | 0x0 | ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN
561  * [2] | RW | 0x0 | ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN
562  * [31:3] | ??? | Unknown | *UNDEFINED*
563  *
564  */
565 /*
566  * Field : SOCKETQOSEN
567  *
568  * n/a
569  *
570  * Field Access Macros:
571  *
572  */
573 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
574 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_LSB 0
575 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
576 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_MSB 0
577 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
578 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_WIDTH 1
579 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value. */
580 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_SET_MSK 0x00000001
581 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value. */
582 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_CLR_MSK 0xfffffffe
583 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
584 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_RESET 0x0
585 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN field value from a register. */
586 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
587 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value suitable for setting the register. */
588 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
589 
590 /*
591  * Field : EXTTHREN
592  *
593  * n/a
594  *
595  * Field Access Macros:
596  *
597  */
598 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field. */
599 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_LSB 1
600 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field. */
601 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_MSB 1
602 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field. */
603 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_WIDTH 1
604 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field value. */
605 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_SET_MSK 0x00000002
606 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field value. */
607 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_CLR_MSK 0xfffffffd
608 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field. */
609 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_RESET 0x0
610 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN field value from a register. */
611 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
612 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN register field value suitable for setting the register. */
613 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
614 
615 /*
616  * Field : INTCLKEN
617  *
618  * n/a
619  *
620  * Field Access Macros:
621  *
622  */
623 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field. */
624 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_LSB 2
625 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field. */
626 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_MSB 2
627 /* The width in bits of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field. */
628 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_WIDTH 1
629 /* The mask used to set the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field value. */
630 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_SET_MSK 0x00000004
631 /* The mask used to clear the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field value. */
632 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_CLR_MSK 0xfffffffb
633 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field. */
634 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_RESET 0x0
635 /* Extracts the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN field value from a register. */
636 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
637 /* Produces a ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN register field value suitable for setting the register. */
638 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
639 
640 #ifndef __ASSEMBLY__
641 /*
642  * WARNING: The C register and register group struct declarations are provided for
643  * convenience and illustrative purposes. They should, however, be used with
644  * caution as the C language standard provides no guarantees about the alignment or
645  * atomicity of device memory accesses. The recommended practice for writing
646  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
647  * alt_write_word() functions.
648  *
649  * The struct declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL.
650  */
651 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_s
652 {
653  uint32_t SOCKETQOSEN : 1; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_SOCKETQOSEN */
654  uint32_t EXTTHREN : 1; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_EXTTHREN */
655  uint32_t INTCLKEN : 1; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_INTCLKEN */
656  uint32_t : 29; /* *UNDEFINED* */
657 };
658 
659 /* The typedef declaration for register ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL. */
660 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_s ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_t;
661 #endif /* __ASSEMBLY__ */
662 
663 /* The reset value of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL register. */
664 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_RESET 0x00000000
665 /* The byte offset of the ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL register from the beginning of the component. */
666 #define ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_OFST 0x18
667 
668 #ifndef __ASSEMBLY__
669 /*
670  * WARNING: The C register and register group struct declarations are provided for
671  * convenience and illustrative purposes. They should, however, be used with
672  * caution as the C language standard provides no guarantees about the alignment or
673  * atomicity of device memory accesses. The recommended practice for writing
674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
675  * alt_write_word() functions.
676  *
677  * The struct declaration for register group ALT_NOC_MPU_USB0_M_MAIN_QOS.
678  */
679 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_s
680 {
681  ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID_t usb0_m_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID */
682  ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID_t usb0_m_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID */
683  ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI_t usb0_m_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI */
684  ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD_t usb0_m_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD */
685  ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH_t usb0_m_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH */
686  ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT_t usb0_m_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT */
687  ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL_t usb0_m_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL */
688  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
689 };
690 
691 /* The typedef declaration for register group ALT_NOC_MPU_USB0_M_MAIN_QOS. */
692 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_s ALT_NOC_MPU_USB0_M_MAIN_QOS_t;
693 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_USB0_M_MAIN_QOS. */
694 struct ALT_NOC_MPU_USB0_M_MAIN_QOS_raw_s
695 {
696  volatile uint32_t usb0_m_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_COREID */
697  volatile uint32_t usb0_m_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_REVID */
698  volatile uint32_t usb0_m_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_PRI */
699  volatile uint32_t usb0_m_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_MOD */
700  volatile uint32_t usb0_m_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_BWDTH */
701  volatile uint32_t usb0_m_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_SAT */
702  volatile uint32_t usb0_m_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_USB0_M_MAIN_QOS_EXTCTL */
703  uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
704 };
705 
706 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_USB0_M_MAIN_QOS. */
707 typedef volatile struct ALT_NOC_MPU_USB0_M_MAIN_QOS_raw_s ALT_NOC_MPU_USB0_M_MAIN_QOS_raw_t;
708 #endif /* __ASSEMBLY__ */
709 
710 
711 #ifdef __cplusplus
712 }
713 #endif /* __cplusplus */
714 #endif /* __ALT_SOCAL_NOC_MPU_USB0_M_MAIN_QOS_H__ */
715