Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_mpu_m0_main_qos.h
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32 
33 /* Altera - ALT_NOC_MPU_M0_MAIN_QOS */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_M0_MAIN_QOS_H__
36 #define __ALT_SOCAL_NOC_MPU_M0_MAIN_QOS_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_M0_MAIN_QOS
50  *
51  */
52 /*
53  * Register : mpu_m0_I_main_QosGenerator_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:-------------------------------------
59  * [7:0] | R | 0x4 | ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID
60  * [31:8] | R | 0x30acdd | ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_RESET 0x4
83 /* Extracts the ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_RESET 0x30acdd
108 /* Extracts the ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_COREID.
123  */
124 struct ALT_NOC_MPU_MAIN_QOS_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_MAIN_QOS_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_MAIN_QOS_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_COREID. */
131 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_COREID_s ALT_NOC_MPU_MAIN_QOS_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_COREID register. */
135 #define ALT_NOC_MPU_MAIN_QOS_COREID_RESET 0x30acdd04
136 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_MAIN_QOS_COREID_OFST 0x0
138 /* The address of the ALT_NOC_MPU_MAIN_QOS_COREID register. */
139 #define ALT_NOC_MPU_MAIN_QOS_COREID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_COREID_OFST))
140 
141 /*
142  * Register : mpu_m0_I_main_QosGenerator_Id_RevisionId
143  *
144  * Register Layout
145  *
146  * Bits | Access | Reset | Description
147  * :-------|:-------|:--------|:-------------------------------------
148  * [7:0] | R | 0x0 | ALT_NOC_MPU_MAIN_QOS_REVID_UID
149  * [31:8] | R | 0x129ff | ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID
150  *
151  */
152 /*
153  * Field : USERID
154  *
155  * Field containing a user defined value, not used anywhere inside the IP itself.
156  *
157  * Field Access Macros:
158  *
159  */
160 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field. */
161 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_LSB 0
162 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field. */
163 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_MSB 7
164 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field. */
165 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_WIDTH 8
166 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field value. */
167 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_SET_MSK 0x000000ff
168 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field value. */
169 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_CLR_MSK 0xffffff00
170 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_REVID_UID register field. */
171 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_RESET 0x0
172 /* Extracts the ALT_NOC_MPU_MAIN_QOS_REVID_UID field value from a register. */
173 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
174 /* Produces a ALT_NOC_MPU_MAIN_QOS_REVID_UID register field value suitable for setting the register. */
175 #define ALT_NOC_MPU_MAIN_QOS_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
176 
177 /*
178  * Field : FLEXNOCID
179  *
180  * Field containing the build revision of the software used to generate the IP HDL
181  * code.
182  *
183  * Field Access Macros:
184  *
185  */
186 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_LSB 8
188 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_MSB 31
190 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field. */
191 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_WIDTH 24
192 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_SET_MSK 0xffffff00
194 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field value. */
195 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_CLR_MSK 0x000000ff
196 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field. */
197 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_RESET 0x129ff
198 /* Extracts the ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID field value from a register. */
199 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
200 /* Produces a ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID register field value suitable for setting the register. */
201 #define ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
202 
203 #ifndef __ASSEMBLY__
204 /*
205  * WARNING: The C register and register group struct declarations are provided for
206  * convenience and illustrative purposes. They should, however, be used with
207  * caution as the C language standard provides no guarantees about the alignment or
208  * atomicity of device memory accesses. The recommended practice for writing
209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
210  * alt_write_word() functions.
211  *
212  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_REVID.
213  */
214 struct ALT_NOC_MPU_MAIN_QOS_REVID_s
215 {
216  const uint32_t USERID : 8; /* ALT_NOC_MPU_MAIN_QOS_REVID_UID */
217  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_MAIN_QOS_REVID_FLEXNOCID */
218 };
219 
220 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_REVID. */
221 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_REVID_s ALT_NOC_MPU_MAIN_QOS_REVID_t;
222 #endif /* __ASSEMBLY__ */
223 
224 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_REVID register. */
225 #define ALT_NOC_MPU_MAIN_QOS_REVID_RESET 0x0129ff00
226 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_REVID register from the beginning of the component. */
227 #define ALT_NOC_MPU_MAIN_QOS_REVID_OFST 0x4
228 /* The address of the ALT_NOC_MPU_MAIN_QOS_REVID register. */
229 #define ALT_NOC_MPU_MAIN_QOS_REVID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_REVID_OFST))
230 
231 /*
232  * Register : mpu_m0_I_main_QosGenerator_Priority
233  *
234  * Priority register.
235  *
236  * Register Layout
237  *
238  * Bits | Access | Reset | Description
239  * :--------|:-------|:--------|:------------------------------
240  * [1:0] | RW | 0x2 | ALT_NOC_MPU_MAIN_QOS_PRI_P0
241  * [7:2] | ??? | Unknown | *UNDEFINED*
242  * [9:8] | RW | 0x2 | ALT_NOC_MPU_MAIN_QOS_PRI_P1
243  * [30:10] | ??? | Unknown | *UNDEFINED*
244  * [31] | R | 0x1 | ALT_NOC_MPU_MAIN_QOS_PRI_MARK
245  *
246  */
247 /*
248  * Field : P0
249  *
250  * In Programmable or Bandwidth Limiter mode, the priority level for write
251  * transactions. In Bandwidth Regulator mode, the priority level when the used
252  * throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a
253  * value equal or lower than P1.
254  *
255  * Field Access Macros:
256  *
257  */
258 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field. */
259 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_LSB 0
260 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field. */
261 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_MSB 1
262 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field. */
263 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_WIDTH 2
264 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field value. */
265 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_SET_MSK 0x00000003
266 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field value. */
267 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_CLR_MSK 0xfffffffc
268 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field. */
269 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_RESET 0x2
270 /* Extracts the ALT_NOC_MPU_MAIN_QOS_PRI_P0 field value from a register. */
271 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_GET(value) (((value) & 0x00000003) >> 0)
272 /* Produces a ALT_NOC_MPU_MAIN_QOS_PRI_P0 register field value suitable for setting the register. */
273 #define ALT_NOC_MPU_MAIN_QOS_PRI_P0_SET(value) (((value) << 0) & 0x00000003)
274 
275 /*
276  * Field : P1
277  *
278  * In Programmable or Bandwidth Limiter mode, the priority level for read
279  * transactions. In Bandwidth regulator mode, the priority level when the used
280  * throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a
281  * value equal or greater than P0.
282  *
283  * Field Access Macros:
284  *
285  */
286 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field. */
287 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_LSB 8
288 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field. */
289 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_MSB 9
290 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field. */
291 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_WIDTH 2
292 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field value. */
293 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_SET_MSK 0x00000300
294 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field value. */
295 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_CLR_MSK 0xfffffcff
296 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field. */
297 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_RESET 0x2
298 /* Extracts the ALT_NOC_MPU_MAIN_QOS_PRI_P1 field value from a register. */
299 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_GET(value) (((value) & 0x00000300) >> 8)
300 /* Produces a ALT_NOC_MPU_MAIN_QOS_PRI_P1 register field value suitable for setting the register. */
301 #define ALT_NOC_MPU_MAIN_QOS_PRI_P1_SET(value) (((value) << 8) & 0x00000300)
302 
303 /*
304  * Field : MARK
305  *
306  * Backward compatibility marker when 0.
307  *
308  * Field Access Macros:
309  *
310  */
311 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field. */
312 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_LSB 31
313 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field. */
314 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_MSB 31
315 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field. */
316 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_WIDTH 1
317 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field value. */
318 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_SET_MSK 0x80000000
319 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field value. */
320 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_CLR_MSK 0x7fffffff
321 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field. */
322 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_RESET 0x1
323 /* Extracts the ALT_NOC_MPU_MAIN_QOS_PRI_MARK field value from a register. */
324 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_GET(value) (((value) & 0x80000000) >> 31)
325 /* Produces a ALT_NOC_MPU_MAIN_QOS_PRI_MARK register field value suitable for setting the register. */
326 #define ALT_NOC_MPU_MAIN_QOS_PRI_MARK_SET(value) (((value) << 31) & 0x80000000)
327 
328 #ifndef __ASSEMBLY__
329 /*
330  * WARNING: The C register and register group struct declarations are provided for
331  * convenience and illustrative purposes. They should, however, be used with
332  * caution as the C language standard provides no guarantees about the alignment or
333  * atomicity of device memory accesses. The recommended practice for writing
334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
335  * alt_write_word() functions.
336  *
337  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_PRI.
338  */
339 struct ALT_NOC_MPU_MAIN_QOS_PRI_s
340 {
341  uint32_t P0 : 2; /* ALT_NOC_MPU_MAIN_QOS_PRI_P0 */
342  uint32_t : 6; /* *UNDEFINED* */
343  uint32_t P1 : 2; /* ALT_NOC_MPU_MAIN_QOS_PRI_P1 */
344  uint32_t : 21; /* *UNDEFINED* */
345  const uint32_t MARK : 1; /* ALT_NOC_MPU_MAIN_QOS_PRI_MARK */
346 };
347 
348 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_PRI. */
349 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_PRI_s ALT_NOC_MPU_MAIN_QOS_PRI_t;
350 #endif /* __ASSEMBLY__ */
351 
352 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_PRI register. */
353 #define ALT_NOC_MPU_MAIN_QOS_PRI_RESET 0x80000202
354 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_PRI register from the beginning of the component. */
355 #define ALT_NOC_MPU_MAIN_QOS_PRI_OFST 0x8
356 /* The address of the ALT_NOC_MPU_MAIN_QOS_PRI register. */
357 #define ALT_NOC_MPU_MAIN_QOS_PRI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_PRI_OFST))
358 
359 /*
360  * Register : mpu_m0_I_main_QosGenerator_Mode
361  *
362  *
363  * Register Layout
364  *
365  * Bits | Access | Reset | Description
366  * :-------|:-------|:--------|:-----------------------------
367  * [1:0] | RW | 0x1 | ALT_NOC_MPU_MAIN_QOS_MOD_MOD
368  * [31:2] | ??? | Unknown | *UNDEFINED*
369  *
370  */
371 /*
372  * Field : MODE
373  *
374  * 0 = Programmable mode: a programmed priority is assigned to each read or write,
375  * 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode:
376  * (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode:
377  * priority decreases when throughput exceeds a threshold.
378  *
379  * Field Access Macros:
380  *
381  */
382 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field. */
383 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_LSB 0
384 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field. */
385 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_MSB 1
386 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field. */
387 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_WIDTH 2
388 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field value. */
389 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_SET_MSK 0x00000003
390 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field value. */
391 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_CLR_MSK 0xfffffffc
392 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field. */
393 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_RESET 0x1
394 /* Extracts the ALT_NOC_MPU_MAIN_QOS_MOD_MOD field value from a register. */
395 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_GET(value) (((value) & 0x00000003) >> 0)
396 /* Produces a ALT_NOC_MPU_MAIN_QOS_MOD_MOD register field value suitable for setting the register. */
397 #define ALT_NOC_MPU_MAIN_QOS_MOD_MOD_SET(value) (((value) << 0) & 0x00000003)
398 
399 #ifndef __ASSEMBLY__
400 /*
401  * WARNING: The C register and register group struct declarations are provided for
402  * convenience and illustrative purposes. They should, however, be used with
403  * caution as the C language standard provides no guarantees about the alignment or
404  * atomicity of device memory accesses. The recommended practice for writing
405  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
406  * alt_write_word() functions.
407  *
408  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_MOD.
409  */
410 struct ALT_NOC_MPU_MAIN_QOS_MOD_s
411 {
412  uint32_t MODE : 2; /* ALT_NOC_MPU_MAIN_QOS_MOD_MOD */
413  uint32_t : 30; /* *UNDEFINED* */
414 };
415 
416 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_MOD. */
417 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_MOD_s ALT_NOC_MPU_MAIN_QOS_MOD_t;
418 #endif /* __ASSEMBLY__ */
419 
420 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_MOD register. */
421 #define ALT_NOC_MPU_MAIN_QOS_MOD_RESET 0x00000001
422 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_MOD register from the beginning of the component. */
423 #define ALT_NOC_MPU_MAIN_QOS_MOD_OFST 0xc
424 /* The address of the ALT_NOC_MPU_MAIN_QOS_MOD register. */
425 #define ALT_NOC_MPU_MAIN_QOS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_MOD_OFST))
426 
427 /*
428  * Register : mpu_m0_I_main_QosGenerator_Bandwidth
429  *
430  *
431  * Register Layout
432  *
433  * Bits | Access | Reset | Description
434  * :--------|:-------|:--------|:-------------------------------------
435  * [11:0] | RW | 0x6aa | ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH
436  * [31:12] | ??? | Unknown | *UNDEFINED*
437  *
438  */
439 /*
440  * Field : BANDWIDTH
441  *
442  * In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in
443  * units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is
444  * value 0x0052.
445  *
446  * Field Access Macros:
447  *
448  */
449 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field. */
450 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_LSB 0
451 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field. */
452 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_MSB 11
453 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field. */
454 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_WIDTH 12
455 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field value. */
456 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_SET_MSK 0x00000fff
457 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field value. */
458 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_CLR_MSK 0xfffff000
459 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field. */
460 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_RESET 0x6aa
461 /* Extracts the ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH field value from a register. */
462 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_GET(value) (((value) & 0x00000fff) >> 0)
463 /* Produces a ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH register field value suitable for setting the register. */
464 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH_SET(value) (((value) << 0) & 0x00000fff)
465 
466 #ifndef __ASSEMBLY__
467 /*
468  * WARNING: The C register and register group struct declarations are provided for
469  * convenience and illustrative purposes. They should, however, be used with
470  * caution as the C language standard provides no guarantees about the alignment or
471  * atomicity of device memory accesses. The recommended practice for writing
472  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
473  * alt_write_word() functions.
474  *
475  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_BWDTH.
476  */
477 struct ALT_NOC_MPU_MAIN_QOS_BWDTH_s
478 {
479  uint32_t BANDWIDTH : 12; /* ALT_NOC_MPU_MAIN_QOS_BWDTH_BANDWIDTH */
480  uint32_t : 20; /* *UNDEFINED* */
481 };
482 
483 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_BWDTH. */
484 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_BWDTH_s ALT_NOC_MPU_MAIN_QOS_BWDTH_t;
485 #endif /* __ASSEMBLY__ */
486 
487 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_BWDTH register. */
488 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_RESET 0x000006aa
489 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_BWDTH register from the beginning of the component. */
490 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_OFST 0x10
491 /* The address of the ALT_NOC_MPU_MAIN_QOS_BWDTH register. */
492 #define ALT_NOC_MPU_MAIN_QOS_BWDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_BWDTH_OFST))
493 
494 /*
495  * Register : mpu_m0_I_main_QosGenerator_Saturation
496  *
497  *
498  * Register Layout
499  *
500  * Bits | Access | Reset | Description
501  * :--------|:-------|:--------|:------------------------------------
502  * [9:0] | RW | 0x8 | ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION
503  * [31:10] | ??? | Unknown | *UNDEFINED*
504  *
505  */
506 /*
507  * Field : SATURATION
508  *
509  * In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value,
510  * in units of 16 bytes. This determines the window of time over which bandwidth is
511  * measured. For example, to measure bandwidth within a 1000 cycle window on a
512  * 64-bit interface is value 0x1F4.
513  *
514  * Field Access Macros:
515  *
516  */
517 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field. */
518 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_LSB 0
519 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field. */
520 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_MSB 9
521 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field. */
522 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_WIDTH 10
523 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field value. */
524 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_SET_MSK 0x000003ff
525 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field value. */
526 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_CLR_MSK 0xfffffc00
527 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field. */
528 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_RESET 0x8
529 /* Extracts the ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION field value from a register. */
530 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_GET(value) (((value) & 0x000003ff) >> 0)
531 /* Produces a ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION register field value suitable for setting the register. */
532 #define ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION_SET(value) (((value) << 0) & 0x000003ff)
533 
534 #ifndef __ASSEMBLY__
535 /*
536  * WARNING: The C register and register group struct declarations are provided for
537  * convenience and illustrative purposes. They should, however, be used with
538  * caution as the C language standard provides no guarantees about the alignment or
539  * atomicity of device memory accesses. The recommended practice for writing
540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
541  * alt_write_word() functions.
542  *
543  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_SAT.
544  */
545 struct ALT_NOC_MPU_MAIN_QOS_SAT_s
546 {
547  uint32_t SATURATION : 10; /* ALT_NOC_MPU_MAIN_QOS_SAT_SATURATION */
548  uint32_t : 22; /* *UNDEFINED* */
549 };
550 
551 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_SAT. */
552 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_SAT_s ALT_NOC_MPU_MAIN_QOS_SAT_t;
553 #endif /* __ASSEMBLY__ */
554 
555 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_SAT register. */
556 #define ALT_NOC_MPU_MAIN_QOS_SAT_RESET 0x00000008
557 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_SAT register from the beginning of the component. */
558 #define ALT_NOC_MPU_MAIN_QOS_SAT_OFST 0x14
559 /* The address of the ALT_NOC_MPU_MAIN_QOS_SAT register. */
560 #define ALT_NOC_MPU_MAIN_QOS_SAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_SAT_OFST))
561 
562 /*
563  * Register : mpu_m0_I_main_QosGenerator_ExtControl
564  *
565  * External inputs control.
566  *
567  * Register Layout
568  *
569  * Bits | Access | Reset | Description
570  * :-------|:-------|:--------|:----------------------------------------
571  * [0] | RW | 0x0 | ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN
572  * [1] | RW | 0x0 | ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN
573  * [2] | RW | 0x0 | ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN
574  * [31:3] | ??? | Unknown | *UNDEFINED*
575  *
576  */
577 /*
578  * Field : SOCKETQOSEN
579  *
580  * n/a
581  *
582  * Field Access Macros:
583  *
584  */
585 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
586 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_LSB 0
587 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
588 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_MSB 0
589 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
590 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_WIDTH 1
591 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value. */
592 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_SET_MSK 0x00000001
593 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value. */
594 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_CLR_MSK 0xfffffffe
595 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field. */
596 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_RESET 0x0
597 /* Extracts the ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN field value from a register. */
598 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_GET(value) (((value) & 0x00000001) >> 0)
599 /* Produces a ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN register field value suitable for setting the register. */
600 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN_SET(value) (((value) << 0) & 0x00000001)
601 
602 /*
603  * Field : EXTTHREN
604  *
605  * n/a
606  *
607  * Field Access Macros:
608  *
609  */
610 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field. */
611 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_LSB 1
612 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field. */
613 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_MSB 1
614 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field. */
615 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_WIDTH 1
616 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field value. */
617 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_SET_MSK 0x00000002
618 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field value. */
619 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_CLR_MSK 0xfffffffd
620 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field. */
621 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_RESET 0x0
622 /* Extracts the ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN field value from a register. */
623 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_GET(value) (((value) & 0x00000002) >> 1)
624 /* Produces a ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN register field value suitable for setting the register. */
625 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN_SET(value) (((value) << 1) & 0x00000002)
626 
627 /*
628  * Field : INTCLKEN
629  *
630  * n/a
631  *
632  * Field Access Macros:
633  *
634  */
635 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field. */
636 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_LSB 2
637 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field. */
638 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_MSB 2
639 /* The width in bits of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field. */
640 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_WIDTH 1
641 /* The mask used to set the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field value. */
642 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_SET_MSK 0x00000004
643 /* The mask used to clear the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field value. */
644 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_CLR_MSK 0xfffffffb
645 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field. */
646 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_RESET 0x0
647 /* Extracts the ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN field value from a register. */
648 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_GET(value) (((value) & 0x00000004) >> 2)
649 /* Produces a ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN register field value suitable for setting the register. */
650 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN_SET(value) (((value) << 2) & 0x00000004)
651 
652 #ifndef __ASSEMBLY__
653 /*
654  * WARNING: The C register and register group struct declarations are provided for
655  * convenience and illustrative purposes. They should, however, be used with
656  * caution as the C language standard provides no guarantees about the alignment or
657  * atomicity of device memory accesses. The recommended practice for writing
658  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
659  * alt_write_word() functions.
660  *
661  * The struct declaration for register ALT_NOC_MPU_MAIN_QOS_EXTCTL.
662  */
663 struct ALT_NOC_MPU_MAIN_QOS_EXTCTL_s
664 {
665  uint32_t SOCKETQOSEN : 1; /* ALT_NOC_MPU_MAIN_QOS_EXTCTL_SOCKETQOSEN */
666  uint32_t EXTTHREN : 1; /* ALT_NOC_MPU_MAIN_QOS_EXTCTL_EXTTHREN */
667  uint32_t INTCLKEN : 1; /* ALT_NOC_MPU_MAIN_QOS_EXTCTL_INTCLKEN */
668  uint32_t : 29; /* *UNDEFINED* */
669 };
670 
671 /* The typedef declaration for register ALT_NOC_MPU_MAIN_QOS_EXTCTL. */
672 typedef volatile struct ALT_NOC_MPU_MAIN_QOS_EXTCTL_s ALT_NOC_MPU_MAIN_QOS_EXTCTL_t;
673 #endif /* __ASSEMBLY__ */
674 
675 /* The reset value of the ALT_NOC_MPU_MAIN_QOS_EXTCTL register. */
676 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_RESET 0x00000000
677 /* The byte offset of the ALT_NOC_MPU_MAIN_QOS_EXTCTL register from the beginning of the component. */
678 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_OFST 0x18
679 /* The address of the ALT_NOC_MPU_MAIN_QOS_EXTCTL register. */
680 #define ALT_NOC_MPU_MAIN_QOS_EXTCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_MAIN_QOS_EXTCTL_OFST))
681 
682 #ifndef __ASSEMBLY__
683 /*
684  * WARNING: The C register and register group struct declarations are provided for
685  * convenience and illustrative purposes. They should, however, be used with
686  * caution as the C language standard provides no guarantees about the alignment or
687  * atomicity of device memory accesses. The recommended practice for writing
688  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
689  * alt_write_word() functions.
690  *
691  * The struct declaration for register group ALT_NOC_MPU_M0_MAIN_QOS.
692  */
693 struct ALT_NOC_MPU_M0_MAIN_QOS_s
694 {
695  ALT_NOC_MPU_MAIN_QOS_COREID_t mpu_m0_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_MAIN_QOS_COREID */
696  ALT_NOC_MPU_MAIN_QOS_REVID_t mpu_m0_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_MAIN_QOS_REVID */
697  ALT_NOC_MPU_MAIN_QOS_PRI_t mpu_m0_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_MAIN_QOS_PRI */
698  ALT_NOC_MPU_MAIN_QOS_MOD_t mpu_m0_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_MAIN_QOS_MOD */
699  ALT_NOC_MPU_MAIN_QOS_BWDTH_t mpu_m0_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_MAIN_QOS_BWDTH */
700  ALT_NOC_MPU_MAIN_QOS_SAT_t mpu_m0_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_MAIN_QOS_SAT */
701  ALT_NOC_MPU_MAIN_QOS_EXTCTL_t mpu_m0_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_MAIN_QOS_EXTCTL */
702  volatile uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
703 };
704 
705 /* The typedef declaration for register group ALT_NOC_MPU_M0_MAIN_QOS. */
706 typedef volatile struct ALT_NOC_MPU_M0_MAIN_QOS_s ALT_NOC_MPU_M0_MAIN_QOS_t;
707 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_M0_MAIN_QOS. */
708 struct ALT_NOC_MPU_M0_MAIN_QOS_raw_s
709 {
710  volatile uint32_t mpu_m0_I_main_QosGenerator_Id_CoreId; /* ALT_NOC_MPU_MAIN_QOS_COREID */
711  volatile uint32_t mpu_m0_I_main_QosGenerator_Id_RevisionId; /* ALT_NOC_MPU_MAIN_QOS_REVID */
712  volatile uint32_t mpu_m0_I_main_QosGenerator_Priority; /* ALT_NOC_MPU_MAIN_QOS_PRI */
713  volatile uint32_t mpu_m0_I_main_QosGenerator_Mode; /* ALT_NOC_MPU_MAIN_QOS_MOD */
714  volatile uint32_t mpu_m0_I_main_QosGenerator_Bandwidth; /* ALT_NOC_MPU_MAIN_QOS_BWDTH */
715  volatile uint32_t mpu_m0_I_main_QosGenerator_Saturation; /* ALT_NOC_MPU_MAIN_QOS_SAT */
716  volatile uint32_t mpu_m0_I_main_QosGenerator_ExtControl; /* ALT_NOC_MPU_MAIN_QOS_EXTCTL */
717  uint32_t _pad_0x1c_0x80[25]; /* *UNDEFINED* */
718 };
719 
720 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_M0_MAIN_QOS. */
721 typedef volatile struct ALT_NOC_MPU_M0_MAIN_QOS_raw_s ALT_NOC_MPU_M0_MAIN_QOS_raw_t;
722 #endif /* __ASSEMBLY__ */
723 
724 
725 #ifdef __cplusplus
726 }
727 #endif /* __cplusplus */
728 #endif /* __ALT_SOCAL_NOC_MPU_M0_MAIN_QOS_H__ */
729