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alt_emac.h
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32 
33 /* Altera - ALT_EMAC */
34 
35 #ifndef __ALTERA_ALT_EMAC_H__
36 #define __ALTERA_ALT_EMAC_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : EMAC Module - ALT_EMAC
45  * EMAC Module
46  *
47  * Registers in the EMAC module.
48  *
49  */
50 /*
51  * Register Group : GMAC Register Group - ALT_EMAC_GMAC
52  * GMAC Register Group
53  *
54  * GMAC Register Group
55  *
56  */
57 /*
58  * Register : Register 0 (MAC Configuration Register) - MAC_Configuration
59  *
60  * The MAC Configuration register establishes receive and transmit operating modes.
61  *
62  * Register Layout
63  *
64  * Bits | Access | Reset | Description
65  * :--------|:-------|:------|:------------------------------------------------
66  * [1:0] | RW | 0x0 | Preamble Length for Transmit Frames
67  * [2] | RW | 0x0 | Receiver Enable
68  * [3] | RW | 0x0 | Transmitter Enable
69  * [4] | RW | 0x0 | Deferral Check
70  * [6:5] | RW | 0x0 | Back-Off Limit
71  * [7] | RW | 0x0 | Automatic Pad or CRC Stripping
72  * [8] | RW | 0x0 | Link Up or Down
73  * [9] | RW | 0x0 | Disable Retry
74  * [10] | RW | 0x0 | Checksum Offload
75  * [11] | RW | 0x0 | Duplex Mode
76  * [12] | RW | 0x0 | Loopback Mode
77  * [13] | RW | 0x0 | Disable Receive Own
78  * [14] | RW | 0x0 | Speed
79  * [15] | RW | 0x0 | Port Select
80  * [16] | RW | 0x0 | Disable Carrier Sense During Transmission
81  * [19:17] | RW | 0x0 | Inter-Frame Gap
82  * [20] | RW | 0x0 | Jumbo Frame Enable
83  * [21] | RW | 0x0 | Frame Burst Enable
84  * [22] | RW | 0x0 | Jabber Disable
85  * [23] | RW | 0x0 | Watchdog Disable
86  * [24] | RW | 0x0 | Transmit Configuration in RGMII, SGMII, or SMII
87  * [25] | RW | 0x0 | CRC Stripping of Type Frames
88  * [26] | ??? | 0x0 | *UNDEFINED*
89  * [27] | RW | 0x0 | IEEE 802.3as support for 2K packets Enable
90  * [31:28] | ??? | 0x0 | *UNDEFINED*
91  *
92  */
93 /*
94  * Field : Preamble Length for Transmit Frames - prelen
95  *
96  * These bits control the number of preamble bytes that are added to the beginning
97  * of every Transmit frame. The preamble reduction occurs only when the MAC is
98  * operating
99  *
100  * Field Enumeration Values:
101  *
102  * Enum | Value | Description
103  * :-------------------------------------------|:------|:-----------------
104  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES | 0x0 | Preamble 7 Bytes
105  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES | 0x1 | Preamble 5 Bytes
106  * ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES | 0x2 | Preamble 3 Bytes
107  *
108  * Field Access Macros:
109  *
110  */
111 /*
112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
113  *
114  * Preamble 7 Bytes
115  */
116 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES 0x0
117 /*
118  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
119  *
120  * Preamble 5 Bytes
121  */
122 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES 0x1
123 /*
124  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
125  *
126  * Preamble 3 Bytes
127  */
128 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES 0x2
129 
130 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
131 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB 0
132 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
133 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB 1
134 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
135 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH 2
136 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
137 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK 0x00000003
138 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
139 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK 0xfffffffc
140 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
141 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET 0x0
142 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register. */
143 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value) (((value) & 0x00000003) >> 0)
144 /* Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register. */
145 #define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value) (((value) << 0) & 0x00000003)
146 
147 /*
148  * Field : Receiver Enable - re
149  *
150  * When this bit is set, the receiver state machine of the MAC is enabled for
151  * receiving frames from the GMII or MII. When this bit is reset, the MAC receive
152  * state machine is disabled after the completion of the reception of the current
153  * frame, and does not receive any further frames from the GMII or MII.
154  *
155  * Field Enumeration Values:
156  *
157  * Enum | Value | Description
158  * :--------------------------------|:------|:-----------------------------------
159  * ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD | 0x0 | MAC receive state machine disabled
160  * ALT_EMAC_GMAC_MAC_CFG_RE_E_END | 0x1 | MAC receive state machine enabled
161  *
162  * Field Access Macros:
163  *
164  */
165 /*
166  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
167  *
168  * MAC receive state machine disabled
169  */
170 #define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD 0x0
171 /*
172  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
173  *
174  * MAC receive state machine enabled
175  */
176 #define ALT_EMAC_GMAC_MAC_CFG_RE_E_END 0x1
177 
178 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
179 #define ALT_EMAC_GMAC_MAC_CFG_RE_LSB 2
180 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
181 #define ALT_EMAC_GMAC_MAC_CFG_RE_MSB 2
182 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
183 #define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH 1
184 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
185 #define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK 0x00000004
186 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
187 #define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK 0xfffffffb
188 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
189 #define ALT_EMAC_GMAC_MAC_CFG_RE_RESET 0x0
190 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register. */
191 #define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value) (((value) & 0x00000004) >> 2)
192 /* Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register. */
193 #define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value) (((value) << 2) & 0x00000004)
194 
195 /*
196  * Field : Transmitter Enable - te
197  *
198  * When this bit is set, the transmit state machine of the MAC is enabled for
199  * transmission on the GMII or MII. When this bit is reset, the MAC transmit state
200  * machine is disabled after the completion of the transmission of the current
201  * frame, and does not transmit any further frames.
202  *
203  * Field Enumeration Values:
204  *
205  * Enum | Value | Description
206  * :--------------------------------|:------|:------------------------------------
207  * ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD | 0x0 | MAC transmit state machine disabled
208  * ALT_EMAC_GMAC_MAC_CFG_TE_E_END | 0x1 | MAC transmit state machine disabled
209  *
210  * Field Access Macros:
211  *
212  */
213 /*
214  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
215  *
216  * MAC transmit state machine disabled
217  */
218 #define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD 0x0
219 /*
220  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
221  *
222  * MAC transmit state machine disabled
223  */
224 #define ALT_EMAC_GMAC_MAC_CFG_TE_E_END 0x1
225 
226 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
227 #define ALT_EMAC_GMAC_MAC_CFG_TE_LSB 3
228 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
229 #define ALT_EMAC_GMAC_MAC_CFG_TE_MSB 3
230 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
231 #define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH 1
232 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
233 #define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK 0x00000008
234 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
235 #define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK 0xfffffff7
236 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
237 #define ALT_EMAC_GMAC_MAC_CFG_TE_RESET 0x0
238 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register. */
239 #define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value) (((value) & 0x00000008) >> 3)
240 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register. */
241 #define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value) (((value) << 3) & 0x00000008)
242 
243 /*
244  * Field : Deferral Check - dc
245  *
246  * When this bit is set, the deferral check function is enabled in the MAC. The MAC
247  * issues a Frame Abort status, along with the excessive deferral error bit set in
248  * the transmit frame status, when the transmit state machine is deferred for more
249  * than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for
250  * 1000 Mbps operation, or if the Jumbo frame mode is enabled in the 10 or 100 Mbps
251  * mode, the threshold for deferral is 155,680 bits times. Deferral begins when the
252  * transmitter is ready to transmit, but is prevented because of an active carrier
253  * sense signal (CRS) on GMII or MII. Defer time is not cumulative. When the
254  * transmitter defers for 10,000 bit times, it transmits, collides, backs off, and
255  * then defers again after completion of back-off. The deferral timer resets to 0
256  * and restarts.
257  *
258  * When this bit is reset, the deferral check function is disabled and the MAC
259  * defers until the CRS signal goes inactive. This bit is applicable only in the
260  * half-duplex mode.
261  *
262  * Field Enumeration Values:
263  *
264  * Enum | Value | Description
265  * :--------------------------------|:------|:------------------------
266  * ALT_EMAC_GMAC_MAC_CFG_DC_E_END | 0x1 | Deferral Check Enabled
267  * ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD | 0x0 | Deferral Check Disabled
268  *
269  * Field Access Macros:
270  *
271  */
272 /*
273  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
274  *
275  * Deferral Check Enabled
276  */
277 #define ALT_EMAC_GMAC_MAC_CFG_DC_E_END 0x1
278 /*
279  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
280  *
281  * Deferral Check Disabled
282  */
283 #define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD 0x0
284 
285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
286 #define ALT_EMAC_GMAC_MAC_CFG_DC_LSB 4
287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
288 #define ALT_EMAC_GMAC_MAC_CFG_DC_MSB 4
289 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
290 #define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH 1
291 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
292 #define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK 0x00000010
293 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
294 #define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK 0xffffffef
295 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
296 #define ALT_EMAC_GMAC_MAC_CFG_DC_RESET 0x0
297 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register. */
298 #define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value) (((value) & 0x00000010) >> 4)
299 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register. */
300 #define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value) (((value) << 4) & 0x00000010)
301 
302 /*
303  * Field : Back-Off Limit - bl
304  *
305  * The Back-Off limit determines the random integer number (r) of slot time delays
306  * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the
307  * MAC waits before rescheduling a transmission attempt during retries after a
308  * collision. This bit is applicable only in the half-duplex mode.
309  *
310  * * 00: k = min (n, 10)
311  *
312  * * 01: k = min (n, 8)
313  *
314  * * 10: k = min (n, 4)
315  *
316  * * 11: k = min (n, 1)
317  *
318  * where <i> n </i>= retransmission attempt. The random integer <i> r </i> takes
319  * the value in the
320  *
321  * range 0 <= r < kth power of 2
322  *
323  * Field Enumeration Values:
324  *
325  * Enum | Value | Description
326  * :---------------------------------------|:------|:----------------
327  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 | 0x0 | k = min (n, 10)
328  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 | 0x1 | k = min (n, 8)
329  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 | 0x2 | k = min (n, 4)
330  * ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 | 0x3 | k = min (n, 1)
331  *
332  * Field Access Macros:
333  *
334  */
335 /*
336  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
337  *
338  * k = min (n, 10)
339  */
340 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 0x0
341 /*
342  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
343  *
344  * k = min (n, 8)
345  */
346 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 0x1
347 /*
348  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
349  *
350  * k = min (n, 4)
351  */
352 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 0x2
353 /*
354  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
355  *
356  * k = min (n, 1)
357  */
358 #define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 0x3
359 
360 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
361 #define ALT_EMAC_GMAC_MAC_CFG_BL_LSB 5
362 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
363 #define ALT_EMAC_GMAC_MAC_CFG_BL_MSB 6
364 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
365 #define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH 2
366 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
367 #define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK 0x00000060
368 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
369 #define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK 0xffffff9f
370 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
371 #define ALT_EMAC_GMAC_MAC_CFG_BL_RESET 0x0
372 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register. */
373 #define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value) (((value) & 0x00000060) >> 5)
374 /* Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register. */
375 #define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value) (((value) << 5) & 0x00000060)
376 
377 /*
378  * Field : Automatic Pad or CRC Stripping - acs
379  *
380  * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames
381  * only if the value of the length field is less than 1,536 bytes. All received
382  * frames with length field greater than or equal to 1,536 bytes are passed to the
383  * application without stripping the Pad or FCS field.
384  *
385  * When this bit is reset, the MAC passes all incoming frames, without modifying
386  * them, to the Host.
387  *
388  * Field Enumeration Values:
389  *
390  * Enum | Value | Description
391  * :---------------------------------|:------|:------------------------------------
392  * ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD | 0x0 | Disable Automatic Pad CRC Stripping
393  * ALT_EMAC_GMAC_MAC_CFG_ACS_E_END | 0x1 | Enable Automatic Pad CRC Stripping
394  *
395  * Field Access Macros:
396  *
397  */
398 /*
399  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
400  *
401  * Disable Automatic Pad CRC Stripping
402  */
403 #define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD 0x0
404 /*
405  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
406  *
407  * Enable Automatic Pad CRC Stripping
408  */
409 #define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END 0x1
410 
411 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
412 #define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB 7
413 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
414 #define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB 7
415 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
416 #define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH 1
417 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
418 #define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK 0x00000080
419 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
420 #define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK 0xffffff7f
421 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
422 #define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET 0x0
423 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register. */
424 #define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value) (((value) & 0x00000080) >> 7)
425 /* Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register. */
426 #define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value) (((value) << 7) & 0x00000080)
427 
428 /*
429  * Field : Link Up or Down - lud
430  *
431  * This bit indicates whether the link is up or down during the transmission of
432  * configuration in the RGMII, SGMII, or SMII interface
433  *
434  * Field Enumeration Values:
435  *
436  * Enum | Value | Description
437  * :---------------------------------|:------|:------------
438  * ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD | 0x0 | Link Down
439  * ALT_EMAC_GMAC_MAC_CFG_LUD_E_END | 0x1 | Link Up
440  *
441  * Field Access Macros:
442  *
443  */
444 /*
445  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
446  *
447  * Link Down
448  */
449 #define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD 0x0
450 /*
451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
452  *
453  * Link Up
454  */
455 #define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END 0x1
456 
457 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
458 #define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB 8
459 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
460 #define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB 8
461 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
462 #define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH 1
463 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
464 #define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK 0x00000100
465 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
466 #define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK 0xfffffeff
467 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
468 #define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET 0x0
469 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register. */
470 #define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value) (((value) & 0x00000100) >> 8)
471 /* Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register. */
472 #define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value) (((value) << 8) & 0x00000100)
473 
474 /*
475  * Field : Disable Retry - dr
476  *
477  * When this bit is set, the MAC attempts only one transmission. When a collision
478  * occurs on the GMII or MII interface, the MAC ignores the current frame
479  * transmission and reports a Frame Abort with excessive collision error in the
480  * transmit frame status.
481  *
482  * When this bit is reset, the MAC attempts retries based on the settings of the BL
483  * field (Bits [6:5]). This bit is applicable only in the half-duplex mode.
484  *
485  * Field Enumeration Values:
486  *
487  * Enum | Value | Description
488  * :--------------------------------|:------|:----------------------------------
489  * ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD | 0x1 | MAC attempts one transmission
490  * ALT_EMAC_GMAC_MAC_CFG_DR_E_END | 0x0 | MAC attempts retries per bl Field
491  *
492  * Field Access Macros:
493  *
494  */
495 /*
496  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
497  *
498  * MAC attempts one transmission
499  */
500 #define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD 0x1
501 /*
502  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
503  *
504  * MAC attempts retries per bl Field
505  */
506 #define ALT_EMAC_GMAC_MAC_CFG_DR_E_END 0x0
507 
508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
509 #define ALT_EMAC_GMAC_MAC_CFG_DR_LSB 9
510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
511 #define ALT_EMAC_GMAC_MAC_CFG_DR_MSB 9
512 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
513 #define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH 1
514 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
515 #define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK 0x00000200
516 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
517 #define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK 0xfffffdff
518 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
519 #define ALT_EMAC_GMAC_MAC_CFG_DR_RESET 0x0
520 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register. */
521 #define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value) (((value) & 0x00000200) >> 9)
522 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register. */
523 #define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value) (((value) << 9) & 0x00000200)
524 
525 /*
526  * Field : Checksum Offload - ipc
527  *
528  * When this bit is set, the MAC calculates the 16-bit ones complement of the ones
529  * complement sum of all received Ethernet frame payloads. It also checks whether
530  * the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the
531  * received Ethernet frame) is correct for the received frame and gives the status
532  * in the receive status word. The MAC also appends the 16-bit checksum calculated
533  * for the IP header datagram payload (bytes after the IPv4 header) and appends it
534  * to the Ethernet frame transferred to the application (when Type 2 COE is
535  * deselected).
536  *
537  * When this bit is reset, this function is disabled.
538  *
539  * When Type 2 COE is selected, this bit, when set, enables the IPv4 header
540  * checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking.
541  * When this bit is reset, the COE function in the receiver is disabled and the
542  * corresponding PCE and IP HCE status bits are always cleared.
543  *
544  * Field Enumeration Values:
545  *
546  * Enum | Value | Description
547  * :---------------------------------|:------|:------------------
548  * ALT_EMAC_GMAC_MAC_CFG_IPC_E_END | 0x1 | Checksum Enabled
549  * ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD | 0x0 | Checksum Disabled
550  *
551  * Field Access Macros:
552  *
553  */
554 /*
555  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
556  *
557  * Checksum Enabled
558  */
559 #define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END 0x1
560 /*
561  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
562  *
563  * Checksum Disabled
564  */
565 #define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD 0x0
566 
567 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
568 #define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB 10
569 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
570 #define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB 10
571 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
572 #define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH 1
573 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
574 #define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK 0x00000400
575 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
576 #define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK 0xfffffbff
577 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
578 #define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET 0x0
579 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register. */
580 #define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value) (((value) & 0x00000400) >> 10)
581 /* Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register. */
582 #define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value) (((value) << 10) & 0x00000400)
583 
584 /*
585  * Field : Duplex Mode - dm
586  *
587  * When this bit is set, the MAC operates in the full-duplex mode where it can
588  * transmit and receive simultaneously.
589  *
590  * Field Enumeration Values:
591  *
592  * Enum | Value | Description
593  * :--------------------------------|:------|:-------------------------
594  * ALT_EMAC_GMAC_MAC_CFG_DM_E_END | 0x1 | MAC Full Duplex Enabled
595  * ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD | 0x0 | MAC Full Duplex Disabled
596  *
597  * Field Access Macros:
598  *
599  */
600 /*
601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
602  *
603  * MAC Full Duplex Enabled
604  */
605 #define ALT_EMAC_GMAC_MAC_CFG_DM_E_END 0x1
606 /*
607  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
608  *
609  * MAC Full Duplex Disabled
610  */
611 #define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD 0x0
612 
613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
614 #define ALT_EMAC_GMAC_MAC_CFG_DM_LSB 11
615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
616 #define ALT_EMAC_GMAC_MAC_CFG_DM_MSB 11
617 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
618 #define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH 1
619 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
620 #define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK 0x00000800
621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
622 #define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK 0xfffff7ff
623 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
624 #define ALT_EMAC_GMAC_MAC_CFG_DM_RESET 0x0
625 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register. */
626 #define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value) (((value) & 0x00000800) >> 11)
627 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register. */
628 #define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value) (((value) << 11) & 0x00000800)
629 
630 /*
631  * Field : Loopback Mode - lm
632  *
633  * When this bit is set, the MAC operates in the loopback mode at GMII or MII. The
634  * (G)MII Receive clock input is required for the loopback to work properly,
635  * because the Transmit clock is not looped-back internally.
636  *
637  * Field Enumeration Values:
638  *
639  * Enum | Value | Description
640  * :--------------------------------|:------|:------------------
641  * ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD | 0x0 | Disable Loop Back
642  * ALT_EMAC_GMAC_MAC_CFG_LM_E_END | 0x1 | Enable Loop Back
643  *
644  * Field Access Macros:
645  *
646  */
647 /*
648  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
649  *
650  * Disable Loop Back
651  */
652 #define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD 0x0
653 /*
654  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
655  *
656  * Enable Loop Back
657  */
658 #define ALT_EMAC_GMAC_MAC_CFG_LM_E_END 0x1
659 
660 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
661 #define ALT_EMAC_GMAC_MAC_CFG_LM_LSB 12
662 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
663 #define ALT_EMAC_GMAC_MAC_CFG_LM_MSB 12
664 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
665 #define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH 1
666 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
667 #define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK 0x00001000
668 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
669 #define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK 0xffffefff
670 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
671 #define ALT_EMAC_GMAC_MAC_CFG_LM_RESET 0x0
672 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register. */
673 #define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value) (((value) & 0x00001000) >> 12)
674 /* Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register. */
675 #define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value) (((value) << 12) & 0x00001000)
676 
677 /*
678  * Field : Disable Receive Own - do
679  *
680  * When this bit is set, the MAC disables the reception of frames when the
681  * gmii_txen_o is asserted in the half-duplex mode.
682  *
683  * When this bit is reset, the MAC receives all packets that are given by the PHY
684  * while transmitting.
685  *
686  * This bit is not applicable if the MAC is operating in the full-duplex mode.
687  *
688  * Field Enumeration Values:
689  *
690  * Enum | Value | Description
691  * :--------------------------------|:------|:---------------------------------
692  * ALT_EMAC_GMAC_MAC_CFG_DO_E_END | 0x0 | MAC Enables Reception of Frames
693  * ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD | 0x1 | MAC Disables Reception of Frames
694  *
695  * Field Access Macros:
696  *
697  */
698 /*
699  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
700  *
701  * MAC Enables Reception of Frames
702  */
703 #define ALT_EMAC_GMAC_MAC_CFG_DO_E_END 0x0
704 /*
705  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
706  *
707  * MAC Disables Reception of Frames
708  */
709 #define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD 0x1
710 
711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
712 #define ALT_EMAC_GMAC_MAC_CFG_DO_LSB 13
713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
714 #define ALT_EMAC_GMAC_MAC_CFG_DO_MSB 13
715 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
716 #define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH 1
717 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
718 #define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK 0x00002000
719 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
720 #define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK 0xffffdfff
721 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
722 #define ALT_EMAC_GMAC_MAC_CFG_DO_RESET 0x0
723 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register. */
724 #define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value) (((value) & 0x00002000) >> 13)
725 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register. */
726 #define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value) (((value) << 13) & 0x00002000)
727 
728 /*
729  * Field : Speed - fes
730  *
731  * This bit selects the speed in the RMII/RGMII interface:
732  *
733  * * 0: 10 Mbps
734  *
735  * * 1: 100 Mbps
736  *
737  * This bit generates link speed encoding when TC (Bit 24) is set in the RGMII,
738  * SMII, or SGMII mode.
739  *
740  * Field Enumeration Values:
741  *
742  * Enum | Value | Description
743  * :-------------------------------------|:------|:-----------------
744  * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 | 0x0 | Speed = 10 Mbps
745  * ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 | 0x1 | Speed = 100 Mbps
746  *
747  * Field Access Macros:
748  *
749  */
750 /*
751  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
752  *
753  * Speed = 10 Mbps
754  */
755 #define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 0x0
756 /*
757  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
758  *
759  * Speed = 100 Mbps
760  */
761 #define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 0x1
762 
763 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
764 #define ALT_EMAC_GMAC_MAC_CFG_FES_LSB 14
765 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
766 #define ALT_EMAC_GMAC_MAC_CFG_FES_MSB 14
767 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
768 #define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH 1
769 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
770 #define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK 0x00004000
771 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
772 #define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK 0xffffbfff
773 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
774 #define ALT_EMAC_GMAC_MAC_CFG_FES_RESET 0x0
775 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register. */
776 #define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value) (((value) & 0x00004000) >> 14)
777 /* Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register. */
778 #define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value) (((value) << 14) & 0x00004000)
779 
780 /*
781  * Field : Port Select - ps
782  *
783  * This bit selects between GMII and MII
784  *
785  * Field Enumeration Values:
786  *
787  * Enum | Value | Description
788  * :---------------------------------------|:------|:----------------
789  * ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL | 0x0 | GMII 1000 Mbps
790  * ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL | 0x1 | MII 10/100 Mbps
791  *
792  * Field Access Macros:
793  *
794  */
795 /*
796  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
797  *
798  * GMII 1000 Mbps
799  */
800 #define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL 0x0
801 /*
802  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
803  *
804  * MII 10/100 Mbps
805  */
806 #define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL 0x1
807 
808 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
809 #define ALT_EMAC_GMAC_MAC_CFG_PS_LSB 15
810 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
811 #define ALT_EMAC_GMAC_MAC_CFG_PS_MSB 15
812 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
813 #define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH 1
814 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
815 #define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK 0x00008000
816 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
817 #define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK 0xffff7fff
818 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
819 #define ALT_EMAC_GMAC_MAC_CFG_PS_RESET 0x0
820 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register. */
821 #define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value) (((value) & 0x00008000) >> 15)
822 /* Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register. */
823 #define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value) (((value) << 15) & 0x00008000)
824 
825 /*
826  * Field : Disable Carrier Sense During Transmission - dcrs
827  *
828  * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal
829  * during frame transmission in the half-duplex mode. This request results in no
830  * errors generated because of Loss of Carrier or No Carrier during such
831  * transmission. When this bit is low, the MAC transmitter generates such errors
832  * because of Carrier Sense and can even abort the transmissions.
833  *
834  * Field Enumeration Values:
835  *
836  * Enum | Value | Description
837  * :----------------------------------|:------|:---------------------------------
838  * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD | 0x0 | MAC Tx Gen. Err. No Carrier
839  * ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END | 0x1 | MAC Tx Ignores (G)MII Crs Signal
840  *
841  * Field Access Macros:
842  *
843  */
844 /*
845  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
846  *
847  * MAC Tx Gen. Err. No Carrier
848  */
849 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD 0x0
850 /*
851  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
852  *
853  * MAC Tx Ignores (G)MII Crs Signal
854  */
855 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END 0x1
856 
857 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
858 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB 16
859 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
860 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB 16
861 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
862 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH 1
863 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
864 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK 0x00010000
865 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
866 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK 0xfffeffff
867 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
868 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET 0x0
869 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register. */
870 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value) (((value) & 0x00010000) >> 16)
871 /* Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register. */
872 #define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value) (((value) << 16) & 0x00010000)
873 
874 /*
875  * Field : Inter-Frame Gap - ifg
876  *
877  * These bits control the minimum IFG between frames during transmission.
878  *
879  * In the half-duplex mode, the minimum IFG can be configured only for 64 bit times
880  * (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum
881  * IFG supported is 80 bit times (and above).
882  *
883  * Field Enumeration Values:
884  *
885  * Enum | Value | Description
886  * :------------------------------------------|:------|:-----------------------------
887  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES | 0x0 | Inter Frame Gap 96 bit times
888  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES | 0x1 | Inter Frame Gap 88 bit times
889  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES | 0x2 | Inter Frame Gap 80 bit times
890  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES | 0x3 | Inter Frame Gap 72 bit times
891  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES | 0x4 | Inter Frame Gap 64 bit times
892  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES | 0x5 | Inter Frame Gap 56 bit times
893  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES | 0x6 | Inter Frame Gap 48 bit times
894  * ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES | 0x7 | Inter Frame Gap 40 bit times
895  *
896  * Field Access Macros:
897  *
898  */
899 /*
900  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
901  *
902  * Inter Frame Gap 96 bit times
903  */
904 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES 0x0
905 /*
906  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
907  *
908  * Inter Frame Gap 88 bit times
909  */
910 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES 0x1
911 /*
912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
913  *
914  * Inter Frame Gap 80 bit times
915  */
916 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES 0x2
917 /*
918  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
919  *
920  * Inter Frame Gap 72 bit times
921  */
922 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES 0x3
923 /*
924  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
925  *
926  * Inter Frame Gap 64 bit times
927  */
928 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES 0x4
929 /*
930  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
931  *
932  * Inter Frame Gap 56 bit times
933  */
934 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES 0x5
935 /*
936  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
937  *
938  * Inter Frame Gap 48 bit times
939  */
940 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES 0x6
941 /*
942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
943  *
944  * Inter Frame Gap 40 bit times
945  */
946 #define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES 0x7
947 
948 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
949 #define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB 17
950 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
951 #define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB 19
952 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
953 #define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH 3
954 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
955 #define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK 0x000e0000
956 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
957 #define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK 0xfff1ffff
958 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
959 #define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET 0x0
960 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register. */
961 #define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value) (((value) & 0x000e0000) >> 17)
962 /* Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register. */
963 #define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value) (((value) << 17) & 0x000e0000)
964 
965 /*
966  * Field : Jumbo Frame Enable - je
967  *
968  * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes
969  * for VLAN tagged frames) without reporting a giant frame error in the receive
970  * frame status.
971  *
972  * Field Enumeration Values:
973  *
974  * Enum | Value | Description
975  * :--------------------------------|:------|:-------------------------
976  * ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD | 0x0 | Report Jumbo Frame Error
977  * ALT_EMAC_GMAC_MAC_CFG_JE_E_END | 0x1 | Ignore Jumbo Frame Error
978  *
979  * Field Access Macros:
980  *
981  */
982 /*
983  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
984  *
985  * Report Jumbo Frame Error
986  */
987 #define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD 0x0
988 /*
989  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
990  *
991  * Ignore Jumbo Frame Error
992  */
993 #define ALT_EMAC_GMAC_MAC_CFG_JE_E_END 0x1
994 
995 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
996 #define ALT_EMAC_GMAC_MAC_CFG_JE_LSB 20
997 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
998 #define ALT_EMAC_GMAC_MAC_CFG_JE_MSB 20
999 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1000 #define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH 1
1001 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
1002 #define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK 0x00100000
1003 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
1004 #define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK 0xffefffff
1005 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
1006 #define ALT_EMAC_GMAC_MAC_CFG_JE_RESET 0x0
1007 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register. */
1008 #define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value) (((value) & 0x00100000) >> 20)
1009 /* Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register. */
1010 #define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value) (((value) << 20) & 0x00100000)
1011 
1012 /*
1013  * Field : Frame Burst Enable - be
1014  *
1015  * When this bit is set, the MAC allows frame bursting during transmission in the
1016  * GMII half-duplex mode.
1017  *
1018  * Field Enumeration Values:
1019  *
1020  * Enum | Value | Description
1021  * :--------------------------------|:------|:-----------------------
1022  * ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD | 0x0 | Frame Burst Enable OFF
1023  * ALT_EMAC_GMAC_MAC_CFG_BE_E_END | 0x1 | Frame Burst Enable ON
1024  *
1025  * Field Access Macros:
1026  *
1027  */
1028 /*
1029  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
1030  *
1031  * Frame Burst Enable OFF
1032  */
1033 #define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD 0x0
1034 /*
1035  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
1036  *
1037  * Frame Burst Enable ON
1038  */
1039 #define ALT_EMAC_GMAC_MAC_CFG_BE_E_END 0x1
1040 
1041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1042 #define ALT_EMAC_GMAC_MAC_CFG_BE_LSB 21
1043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1044 #define ALT_EMAC_GMAC_MAC_CFG_BE_MSB 21
1045 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1046 #define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH 1
1047 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
1048 #define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK 0x00200000
1049 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
1050 #define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK 0xffdfffff
1051 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
1052 #define ALT_EMAC_GMAC_MAC_CFG_BE_RESET 0x0
1053 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register. */
1054 #define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value) (((value) & 0x00200000) >> 21)
1055 /* Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register. */
1056 #define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value) (((value) << 21) & 0x00200000)
1057 
1058 /*
1059  * Field : Jabber Disable - jd
1060  *
1061  * When this bit is set, the MAC disables the jabber timer on the transmitter. The
1062  * MAC can transfer frames of up to 16,384 bytes.
1063  *
1064  * When this bit is reset, the MAC cuts off the transmitter if the application
1065  * sends out more than 2,048 bytes of data (10,240 if JE is set high) during
1066  * transmission.
1067  *
1068  * Field Enumeration Values:
1069  *
1070  * Enum | Value | Description
1071  * :--------------------------------|:------|:-----------------------
1072  * ALT_EMAC_GMAC_MAC_CFG_JD_E_END | 0x0 | MAC cuts off TX > 2048
1073  * ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD | 0x1 | Jabber Timer Disabled
1074  *
1075  * Field Access Macros:
1076  *
1077  */
1078 /*
1079  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
1080  *
1081  * MAC cuts off TX > 2048
1082  */
1083 #define ALT_EMAC_GMAC_MAC_CFG_JD_E_END 0x0
1084 /*
1085  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
1086  *
1087  * Jabber Timer Disabled
1088  */
1089 #define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD 0x1
1090 
1091 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1092 #define ALT_EMAC_GMAC_MAC_CFG_JD_LSB 22
1093 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1094 #define ALT_EMAC_GMAC_MAC_CFG_JD_MSB 22
1095 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1096 #define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH 1
1097 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
1098 #define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK 0x00400000
1099 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
1100 #define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK 0xffbfffff
1101 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
1102 #define ALT_EMAC_GMAC_MAC_CFG_JD_RESET 0x0
1103 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register. */
1104 #define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value) (((value) & 0x00400000) >> 22)
1105 /* Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register. */
1106 #define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value) (((value) << 22) & 0x00400000)
1107 
1108 /*
1109  * Field : Watchdog Disable - wd
1110  *
1111  * When this bit is set, the MAC disables the watchdog timer on the receiver. The
1112  * MAC can receive frames of up to 16,384 bytes.
1113  *
1114  * When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if
1115  * JE is set high) of the frame being received. The MAC cuts off any bytes received
1116  * after 2,048 bytes.
1117  *
1118  * Field Enumeration Values:
1119  *
1120  * Enum | Value | Description
1121  * :--------------------------------|:------|:------------------------------
1122  * ALT_EMAC_GMAC_MAC_CFG_WD_E_END | 0x0 | Enable MAC cutoff > 2048Bytes
1123  * ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD | 0x1 | Disable Watchdog
1124  *
1125  * Field Access Macros:
1126  *
1127  */
1128 /*
1129  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
1130  *
1131  * Enable MAC cutoff > 2048Bytes
1132  */
1133 #define ALT_EMAC_GMAC_MAC_CFG_WD_E_END 0x0
1134 /*
1135  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
1136  *
1137  * Disable Watchdog
1138  */
1139 #define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD 0x1
1140 
1141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1142 #define ALT_EMAC_GMAC_MAC_CFG_WD_LSB 23
1143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1144 #define ALT_EMAC_GMAC_MAC_CFG_WD_MSB 23
1145 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1146 #define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH 1
1147 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
1148 #define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK 0x00800000
1149 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
1150 #define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK 0xff7fffff
1151 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
1152 #define ALT_EMAC_GMAC_MAC_CFG_WD_RESET 0x0
1153 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register. */
1154 #define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value) (((value) & 0x00800000) >> 23)
1155 /* Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register. */
1156 #define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value) (((value) << 23) & 0x00800000)
1157 
1158 /*
1159  * Field : Transmit Configuration in RGMII, SGMII, or SMII - tc
1160  *
1161  * When set, this bit enables the transmission of duplex mode, link speed, and link
1162  * up or down information to the PHY in the RGMII. When this bit is reset, no such
1163  * information is driven to the PHY.
1164  *
1165  * Field Enumeration Values:
1166  *
1167  * Enum | Value | Description
1168  * :--------------------------------|:------|:-------------------------------
1169  * ALT_EMAC_GMAC_MAC_CFG_TC_E_END | 0x1 | Enables Transmission of duplex
1170  * ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD | 0x0 | Disables Transmission to Phy
1171  *
1172  * Field Access Macros:
1173  *
1174  */
1175 /*
1176  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
1177  *
1178  * Enables Transmission of duplex
1179  */
1180 #define ALT_EMAC_GMAC_MAC_CFG_TC_E_END 0x1
1181 /*
1182  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
1183  *
1184  * Disables Transmission to Phy
1185  */
1186 #define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD 0x0
1187 
1188 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1189 #define ALT_EMAC_GMAC_MAC_CFG_TC_LSB 24
1190 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1191 #define ALT_EMAC_GMAC_MAC_CFG_TC_MSB 24
1192 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1193 #define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH 1
1194 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
1195 #define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK 0x01000000
1196 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
1197 #define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK 0xfeffffff
1198 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
1199 #define ALT_EMAC_GMAC_MAC_CFG_TC_RESET 0x0
1200 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register. */
1201 #define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value) (((value) & 0x01000000) >> 24)
1202 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register. */
1203 #define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value) (((value) << 24) & 0x01000000)
1204 
1205 /*
1206  * Field : CRC Stripping of Type Frames - cst
1207  *
1208  * When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater
1209  * than 0x0600) are stripped and dropped before forwarding the frame to the
1210  * application. This function is not valid when the IP Checksum Engine (Type 1) is
1211  * enabled in the MAC receiver.
1212  *
1213  * Field Enumeration Values:
1214  *
1215  * Enum | Value | Description
1216  * :---------------------------------|:------|:-----------------------
1217  * ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD | 0x0 | Strip Ether Frames Off
1218  * ALT_EMAC_GMAC_MAC_CFG_CST_E_END | 0x1 | Strip Ether Frames On
1219  *
1220  * Field Access Macros:
1221  *
1222  */
1223 /*
1224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
1225  *
1226  * Strip Ether Frames Off
1227  */
1228 #define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD 0x0
1229 /*
1230  * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
1231  *
1232  * Strip Ether Frames On
1233  */
1234 #define ALT_EMAC_GMAC_MAC_CFG_CST_E_END 0x1
1235 
1236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1237 #define ALT_EMAC_GMAC_MAC_CFG_CST_LSB 25
1238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1239 #define ALT_EMAC_GMAC_MAC_CFG_CST_MSB 25
1240 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1241 #define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH 1
1242 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
1243 #define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK 0x02000000
1244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
1245 #define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK 0xfdffffff
1246 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
1247 #define ALT_EMAC_GMAC_MAC_CFG_CST_RESET 0x0
1248 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register. */
1249 #define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value) (((value) & 0x02000000) >> 25)
1250 /* Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register. */
1251 #define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value) (((value) << 25) & 0x02000000)
1252 
1253 /*
1254  * Field : IEEE 802.3as support for 2K packets Enable - twokpe
1255  *
1256  * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal
1257  * packets. When Bit 20 (Jumbo Enable) is not set, the MAC considers all received
1258  * frames of size more than 2K bytes as Giant frames.
1259  *
1260  * When this bit is reset and Bit 20 (Jumbo Enable) is not set, the MAC considers
1261  * all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as
1262  * Giant frames.
1263  *
1264  * When Bit 20 (Jumbo Enable) is set, setting this bit has no effect on Giant Frame
1265  * status.
1266  *
1267  * Field Access Macros:
1268  *
1269  */
1270 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1271 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB 27
1272 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1273 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB 27
1274 /* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1275 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH 1
1276 /* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
1277 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK 0x08000000
1278 /* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
1279 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK 0xf7ffffff
1280 /* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
1281 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET 0x0
1282 /* Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register. */
1283 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value) (((value) & 0x08000000) >> 27)
1284 /* Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register. */
1285 #define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value) (((value) << 27) & 0x08000000)
1286 
1287 #ifndef __ASSEMBLY__
1288 /*
1289  * WARNING: The C register and register group struct declarations are provided for
1290  * convenience and illustrative purposes. They should, however, be used with
1291  * caution as the C language standard provides no guarantees about the alignment or
1292  * atomicity of device memory accesses. The recommended practice for writing
1293  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1294  * alt_write_word() functions.
1295  *
1296  * The struct declaration for register ALT_EMAC_GMAC_MAC_CFG.
1297  */
1298 struct ALT_EMAC_GMAC_MAC_CFG_s
1299 {
1300  uint32_t prelen : 2; /* Preamble Length for Transmit Frames */
1301  uint32_t re : 1; /* Receiver Enable */
1302  uint32_t te : 1; /* Transmitter Enable */
1303  uint32_t dc : 1; /* Deferral Check */
1304  uint32_t bl : 2; /* Back-Off Limit */
1305  uint32_t acs : 1; /* Automatic Pad or CRC Stripping */
1306  uint32_t lud : 1; /* Link Up or Down */
1307  uint32_t dr : 1; /* Disable Retry */
1308  uint32_t ipc : 1; /* Checksum Offload */
1309  uint32_t dm : 1; /* Duplex Mode */
1310  uint32_t lm : 1; /* Loopback Mode */
1311  uint32_t do_ : 1; /* Disable Receive Own */
1312  uint32_t fes : 1; /* Speed */
1313  uint32_t ps : 1; /* Port Select */
1314  uint32_t dcrs : 1; /* Disable Carrier Sense During Transmission */
1315  uint32_t ifg : 3; /* Inter-Frame Gap */
1316  uint32_t je : 1; /* Jumbo Frame Enable */
1317  uint32_t be : 1; /* Frame Burst Enable */
1318  uint32_t jd : 1; /* Jabber Disable */
1319  uint32_t wd : 1; /* Watchdog Disable */
1320  uint32_t tc : 1; /* Transmit Configuration in RGMII, SGMII, or SMII */
1321  uint32_t cst : 1; /* CRC Stripping of Type Frames */
1322  uint32_t : 1; /* *UNDEFINED* */
1323  uint32_t twokpe : 1; /* IEEE 802.3as support for 2K packets Enable */
1324  uint32_t : 4; /* *UNDEFINED* */
1325 };
1326 
1327 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG. */
1328 typedef volatile struct ALT_EMAC_GMAC_MAC_CFG_s ALT_EMAC_GMAC_MAC_CFG_t;
1329 #endif /* __ASSEMBLY__ */
1330 
1331 /* The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component. */
1332 #define ALT_EMAC_GMAC_MAC_CFG_OFST 0x0
1333 /* The address of the ALT_EMAC_GMAC_MAC_CFG register. */
1334 #define ALT_EMAC_GMAC_MAC_CFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))
1335 
1336 /*
1337  * Register : Register 1 (MAC Frame Filter) - MAC_Frame_Filter
1338  *
1339  * The MAC Frame Filter register contains the filter controls for receiving frames.
1340  * Some of the controls from this register go to the address check block of the
1341  * MAC, which performs the first level of address filtering. The second level of
1342  * filtering is performed on the incoming frame, based on other controls such as
1343  * Pass Bad Frames and Pass Control Frames.
1344  *
1345  * Register Layout
1346  *
1347  * Bits | Access | Reset | Description
1348  * :--------|:-------|:------|:----------------------------------
1349  * [0] | RW | 0x0 | Promiscuous Mode
1350  * [1] | RW | 0x0 | Hash Unicast
1351  * [2] | RW | 0x0 | Hash Multicast
1352  * [3] | RW | 0x0 | DA Inverse Filtering
1353  * [4] | RW | 0x0 | Pass All Multicast
1354  * [5] | RW | 0x0 | Disable Broadcast Frames
1355  * [7:6] | RW | 0x0 | Pass Control Frames
1356  * [8] | RW | 0x0 | SA Inverse Filtering
1357  * [9] | RW | 0x0 | Source Address Filter Enable
1358  * [10] | RW | 0x0 | Hash or Perfect Filter
1359  * [15:11] | ??? | 0x0 | *UNDEFINED*
1360  * [16] | RW | 0x0 | VLAN Tag Filter Enable
1361  * [19:17] | ??? | 0x0 | *UNDEFINED*
1362  * [20] | RW | 0x0 | Layer 3 and Layer 4 Filter Enable
1363  * [21] | RW | 0x0 | Drop non-TCP/UDP over IP Frames
1364  * [30:22] | ??? | 0x0 | *UNDEFINED*
1365  * [31] | RW | 0x0 | Receive All
1366  *
1367  */
1368 /*
1369  * Field : Promiscuous Mode - pr
1370  *
1371  * When this bit is set, the Address Filter block passes all incoming frames
1372  * regardless of its destination or source address. The SA or DA Filter Fails
1373  * status bits of the Receive Status Word are always cleared when PR is set.
1374  *
1375  * Field Enumeration Values:
1376  *
1377  * Enum | Value | Description
1378  * :------------------------------------|:------|:---------------------------
1379  * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END | 0x1 | All Incoming Frames Passed
1380  * ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD | 0x0 | Clear SA DA Status Bits
1381  *
1382  * Field Access Macros:
1383  *
1384  */
1385 /*
1386  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
1387  *
1388  * All Incoming Frames Passed
1389  */
1390 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END 0x1
1391 /*
1392  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
1393  *
1394  * Clear SA DA Status Bits
1395  */
1396 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD 0x0
1397 
1398 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1399 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB 0
1400 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1401 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB 0
1402 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1403 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH 1
1404 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
1405 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK 0x00000001
1406 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
1407 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK 0xfffffffe
1408 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
1409 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET 0x0
1410 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PR field value from a register. */
1411 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET(value) (((value) & 0x00000001) >> 0)
1412 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value suitable for setting the register. */
1413 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET(value) (((value) << 0) & 0x00000001)
1414 
1415 /*
1416  * Field : Hash Unicast - huc
1417  *
1418  * When set, MAC performs destination address filtering of unicast frames according
1419  * to the hash table.
1420  *
1421  * When reset, the MAC performs a perfect destination address filtering for unicast
1422  * frames, that is, it compares the DA field with the values programmed in DA
1423  * registers.
1424  *
1425  * Field Enumeration Values:
1426  *
1427  * Enum | Value | Description
1428  * :-------------------------------------|:------|:----------------------------
1429  * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END | 0x1 | MAC Filters with Hash Table
1430  * ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD | 0x0 | MAC Filters with Compare
1431  *
1432  * Field Access Macros:
1433  *
1434  */
1435 /*
1436  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
1437  *
1438  * MAC Filters with Hash Table
1439  */
1440 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END 0x1
1441 /*
1442  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
1443  *
1444  * MAC Filters with Compare
1445  */
1446 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD 0x0
1447 
1448 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1449 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB 1
1450 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1451 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB 1
1452 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1453 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH 1
1454 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
1455 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK 0x00000002
1456 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
1457 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK 0xfffffffd
1458 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
1459 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET 0x0
1460 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC field value from a register. */
1461 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET(value) (((value) & 0x00000002) >> 1)
1462 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value suitable for setting the register. */
1463 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET(value) (((value) << 1) & 0x00000002)
1464 
1465 /*
1466  * Field : Hash Multicast - hmc
1467  *
1468  * When set, MAC performs destination address filtering of received multicast
1469  * frames according to the hash table.
1470  *
1471  * When reset, the MAC performs a perfect destination address filtering for
1472  * multicast frames, that is, it compares the DA field with the values programmed
1473  * in DA registers.
1474  *
1475  * Field Enumeration Values:
1476  *
1477  * Enum | Value | Description
1478  * :-------------------------------------|:------|:----------------------------
1479  * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD | 0x0 | MAC Filters with Hash Table
1480  * ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END | 0x1 | MAC Filters with Compare
1481  *
1482  * Field Access Macros:
1483  *
1484  */
1485 /*
1486  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
1487  *
1488  * MAC Filters with Hash Table
1489  */
1490 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD 0x0
1491 /*
1492  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
1493  *
1494  * MAC Filters with Compare
1495  */
1496 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END 0x1
1497 
1498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1499 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB 2
1500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1501 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB 2
1502 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1503 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH 1
1504 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
1505 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK 0x00000004
1506 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
1507 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK 0xfffffffb
1508 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
1509 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET 0x0
1510 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC field value from a register. */
1511 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET(value) (((value) & 0x00000004) >> 2)
1512 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value suitable for setting the register. */
1513 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET(value) (((value) << 2) & 0x00000004)
1514 
1515 /*
1516  * Field : DA Inverse Filtering - daif
1517  *
1518  * When this bit is set, the Address Check block operates in inverse filtering mode
1519  * for the DA address comparison for both unicast and multicast frames.
1520  *
1521  * When reset, normal filtering of frames is performed.
1522  *
1523  * Field Enumeration Values:
1524  *
1525  * Enum | Value | Description
1526  * :--------------------------------------|:------|:-----------------------------------
1527  * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD | 0x0 | Normal Inverse Filter
1528  * ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END | 0x1 | Address Check Block Inverse Filter
1529  *
1530  * Field Access Macros:
1531  *
1532  */
1533 /*
1534  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
1535  *
1536  * Normal Inverse Filter
1537  */
1538 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD 0x0
1539 /*
1540  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
1541  *
1542  * Address Check Block Inverse Filter
1543  */
1544 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END 0x1
1545 
1546 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1547 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB 3
1548 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1549 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB 3
1550 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1551 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH 1
1552 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
1553 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK 0x00000008
1554 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
1555 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK 0xfffffff7
1556 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
1557 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET 0x0
1558 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF field value from a register. */
1559 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET(value) (((value) & 0x00000008) >> 3)
1560 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value suitable for setting the register. */
1561 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET(value) (((value) << 3) & 0x00000008)
1562 
1563 /*
1564  * Field : Pass All Multicast - pm
1565  *
1566  * When set, this bit indicates that all received frames with a multicast
1567  * destination address (first bit in the destination address field is '1') are
1568  * passed.
1569  *
1570  * When reset, filtering of multicast frame depends on HMC bit.
1571  *
1572  * Field Enumeration Values:
1573  *
1574  * Enum | Value | Description
1575  * :------------------------------------|:------|:---------------------------
1576  * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD | 0x0 | Allows Filter of MC Frames
1577  * ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END | 0x1 | All Rcvd MC Frames Pass
1578  *
1579  * Field Access Macros:
1580  *
1581  */
1582 /*
1583  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
1584  *
1585  * Allows Filter of MC Frames
1586  */
1587 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD 0x0
1588 /*
1589  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
1590  *
1591  * All Rcvd MC Frames Pass
1592  */
1593 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END 0x1
1594 
1595 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1596 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB 4
1597 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1598 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB 4
1599 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1600 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH 1
1601 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
1602 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK 0x00000010
1603 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
1604 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK 0xffffffef
1605 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
1606 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET 0x0
1607 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PM field value from a register. */
1608 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET(value) (((value) & 0x00000010) >> 4)
1609 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value suitable for setting the register. */
1610 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET(value) (((value) << 4) & 0x00000010)
1611 
1612 /*
1613  * Field : Disable Broadcast Frames - dbf
1614  *
1615  * When this bit is set, the AFM block filters all incoming broadcast frames. In
1616  * addition, it overrides all other filter settings.
1617  *
1618  * When this bit is reset, the AFM block passes all received broadcast frames.
1619  *
1620  * Field Enumeration Values:
1621  *
1622  * Enum | Value | Description
1623  * :-------------------------------------|:------|:----------------------------
1624  * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD | 0x0 | Pass All Broadcast Frames
1625  * ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END | 0x1 | Filter All Broadcast Frames
1626  *
1627  * Field Access Macros:
1628  *
1629  */
1630 /*
1631  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
1632  *
1633  * Pass All Broadcast Frames
1634  */
1635 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD 0x0
1636 /*
1637  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
1638  *
1639  * Filter All Broadcast Frames
1640  */
1641 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END 0x1
1642 
1643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1644 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB 5
1645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1646 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB 5
1647 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1648 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH 1
1649 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
1650 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK 0x00000020
1651 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
1652 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK 0xffffffdf
1653 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
1654 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET 0x0
1655 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF field value from a register. */
1656 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET(value) (((value) & 0x00000020) >> 5)
1657 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value suitable for setting the register. */
1658 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET(value) (((value) << 5) & 0x00000020)
1659 
1660 /*
1661  * Field : Pass Control Frames - pcf
1662  *
1663  * These bits control the forwarding of all control frames (including unicast and
1664  * multicast PAUSE frames).
1665  *
1666  * * 00: MAC filters all control frames from reaching the application.
1667  *
1668  * * 01: MAC forwards all control frames except PAUSE control frames to application
1669  * even if they fail the Address filter.
1670  *
1671  * * 10: MAC forwards all control frames to application even if they fail the
1672  * Address Filter.
1673  *
1674  * * 11: MAC forwards control frames that pass the Address Filter.
1675  *
1676  * The following conditions should be true for the PAUSE control frames processing:
1677  *
1678  * * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by
1679  * setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
1680  *
1681  * * Condition 2: The destination address (DA) of the received frame matches the
1682  * special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register
1683  * 6 (Flow Control Register) is set.
1684  *
1685  * * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE
1686  * field is 0x0001.
1687  *
1688  * This field should be set to 01 only when the Condition 1 is true, that is, the
1689  * MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled.
1690  * Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is
1691  * false, the PAUSE frames are considered as generic control frames. Therefore, to
1692  * pass all control frames (including PAUSE control frames) when the full-duplex
1693  * mode and flow control is not enabled, you should set the PCF field to 10 or 11
1694  * (as required by the application).
1695  *
1696  * Field Enumeration Values:
1697  *
1698  * Enum | Value | Description
1699  * :---------------------------------------------|:------|:----------------------------------------------
1700  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR | 0x0 | MAC filters all control frames
1701  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE | 0x1 | MAC forwards all control frames except PAUSE
1702  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL | 0x2 | MAC forwards all control frames fail addrflt
1703  * ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS | 0x3 | MAC forwards control frames that pass addrflt
1704  *
1705  * Field Access Macros:
1706  *
1707  */
1708 /*
1709  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1710  *
1711  * MAC filters all control frames
1712  */
1713 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR 0x0
1714 /*
1715  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1716  *
1717  * MAC forwards all control frames except PAUSE
1718  */
1719 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE 0x1
1720 /*
1721  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1722  *
1723  * MAC forwards all control frames fail addrflt
1724  */
1725 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL 0x2
1726 /*
1727  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
1728  *
1729  * MAC forwards control frames that pass addrflt
1730  */
1731 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS 0x3
1732 
1733 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1734 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB 6
1735 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1736 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB 7
1737 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1738 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH 2
1739 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
1740 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK 0x000000c0
1741 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
1742 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK 0xffffff3f
1743 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
1744 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET 0x0
1745 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF field value from a register. */
1746 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET(value) (((value) & 0x000000c0) >> 6)
1747 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value suitable for setting the register. */
1748 #define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET(value) (((value) << 6) & 0x000000c0)
1749 
1750 /*
1751  * Field : SA Inverse Filtering - saif
1752  *
1753  * When this bit is set, the Address Check block operates in inverse filtering mode
1754  * for the SA address comparison. The frames whose SA matches the SA registers are
1755  * marked as failing the SA Address filter.
1756  *
1757  * When this bit is reset, frames whose SA does not match the SA registers are
1758  * marked as failing the SA Address filter.
1759  *
1760  * Field Enumeration Values:
1761  *
1762  * Enum | Value | Description
1763  * :--------------------------------------|:------|:----------------
1764  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD | 0x0 | SA Nomatch Fail
1765  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END | 0x1 | SA Match Fail
1766  *
1767  * Field Access Macros:
1768  *
1769  */
1770 /*
1771  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
1772  *
1773  * SA Nomatch Fail
1774  */
1775 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD 0x0
1776 /*
1777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
1778  *
1779  * SA Match Fail
1780  */
1781 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END 0x1
1782 
1783 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1784 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB 8
1785 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1786 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB 8
1787 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1788 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH 1
1789 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
1790 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK 0x00000100
1791 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
1792 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK 0xfffffeff
1793 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
1794 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET 0x0
1795 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF field value from a register. */
1796 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET(value) (((value) & 0x00000100) >> 8)
1797 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value suitable for setting the register. */
1798 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET(value) (((value) << 8) & 0x00000100)
1799 
1800 /*
1801  * Field : Source Address Filter Enable - saf
1802  *
1803  * When this bit is set, the MAC compares the SA field of the received frames with
1804  * the values programmed in the enabled SA registers. If the comparison matches,
1805  * then the SA Match bit of RxStatus Word is set high. When this bit is set high
1806  * and the SA filter fails, the MAC drops the frame.
1807  *
1808  * When this bit is reset, the MAC forwards the received frame to the application
1809  * and with the updated SA Match bit of the RxStatus depending on the SA address
1810  * comparison.
1811  *
1812  * Field Enumeration Values:
1813  *
1814  * Enum | Value | Description
1815  * :-------------------------------------|:------|:--------------
1816  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD | 0x0 | SA Filter Off
1817  * ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END | 0x1 | SA Filter On
1818  *
1819  * Field Access Macros:
1820  *
1821  */
1822 /*
1823  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
1824  *
1825  * SA Filter Off
1826  */
1827 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD 0x0
1828 /*
1829  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
1830  *
1831  * SA Filter On
1832  */
1833 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END 0x1
1834 
1835 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
1836 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB 9
1837 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
1838 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB 9
1839 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
1840 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH 1
1841 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
1842 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK 0x00000200
1843 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
1844 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK 0xfffffdff
1845 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
1846 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET 0x0
1847 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF field value from a register. */
1848 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET(value) (((value) & 0x00000200) >> 9)
1849 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value suitable for setting the register. */
1850 #define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET(value) (((value) << 9) & 0x00000200)
1851 
1852 /*
1853  * Field : Hash or Perfect Filter - hpf
1854  *
1855  * When this bit is set, it configures the address filter to pass a frame if it
1856  * matches either the perfect filtering or the hash filtering as set by the HMC or
1857  * HUC bits.
1858  *
1859  * When this bit is low and the HUC or HMC bit is set, the frame is passed only if
1860  * it matches the Hash filter.
1861  *
1862  * Field Enumeration Values:
1863  *
1864  * Enum | Value | Description
1865  * :-------------------------------------|:------|:---------------------------
1866  * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD | 0x0 | Hash or Perfect Filter off
1867  * ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END | 0x1 | Hash or Perfect Filter on
1868  *
1869  * Field Access Macros:
1870  *
1871  */
1872 /*
1873  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
1874  *
1875  * Hash or Perfect Filter off
1876  */
1877 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD 0x0
1878 /*
1879  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
1880  *
1881  * Hash or Perfect Filter on
1882  */
1883 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END 0x1
1884 
1885 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
1886 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB 10
1887 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
1888 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB 10
1889 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
1890 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH 1
1891 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
1892 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK 0x00000400
1893 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
1894 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK 0xfffffbff
1895 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
1896 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET 0x0
1897 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF field value from a register. */
1898 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET(value) (((value) & 0x00000400) >> 10)
1899 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value suitable for setting the register. */
1900 #define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET(value) (((value) << 10) & 0x00000400)
1901 
1902 /*
1903  * Field : VLAN Tag Filter Enable - vtfe
1904  *
1905  * When set, this bit enables the MAC to drop VLAN tagged frames that do not match
1906  * the VLAN Tag comparison.
1907  *
1908  * When reset, the MAC forwards all frames irrespective of the match status of the
1909  * VLAN Tag.
1910  *
1911  * Field Enumeration Values:
1912  *
1913  * Enum | Value | Description
1914  * :----------------------------------------|:------|:----------------------------------------------
1915  * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP | 0x0 | Forward all frames irrespective of the match
1916  * : | | status of the VLAN tag
1917  * ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP | 0x1 | Drop VLAN tagged frames that do not match the
1918  * : | | VLAN Tag comparison
1919  *
1920  * Field Access Macros:
1921  *
1922  */
1923 /*
1924  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
1925  *
1926  * Forward all frames irrespective of the match status of the VLAN tag
1927  */
1928 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP 0x0
1929 /*
1930  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
1931  *
1932  * Drop VLAN tagged frames that do not match the VLAN Tag comparison
1933  */
1934 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP 0x1
1935 
1936 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
1937 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB 16
1938 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
1939 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB 16
1940 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
1941 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH 1
1942 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
1943 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK 0x00010000
1944 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
1945 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK 0xfffeffff
1946 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
1947 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET 0x0
1948 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE field value from a register. */
1949 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET(value) (((value) & 0x00010000) >> 16)
1950 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value suitable for setting the register. */
1951 #define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET(value) (((value) << 16) & 0x00010000)
1952 
1953 /*
1954  * Field : Layer 3 and Layer 4 Filter Enable - ipfe
1955  *
1956  * When set, this bit enables the MAC to drop frames that do not match the enabled
1957  * Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for
1958  * matching, this bit does not have any effect.
1959  *
1960  * When reset, the MAC forwards all frames irrespective of the match status of the
1961  * Layer 3 and Layer 4 filters.
1962  *
1963  * Field Enumeration Values:
1964  *
1965  * Enum | Value | Description
1966  * :----------------------------------------|:------|:------------------------------------------------
1967  * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP | 0x0 | Forward all frames irrespective of the match
1968  * : | | status of Layer 3 and Layer 4 filters
1969  * ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP | 0x1 | Drop frames that do not match the enabled Layer
1970  * : | | 3 and Layer 4 filters
1971  *
1972  * Field Access Macros:
1973  *
1974  */
1975 /*
1976  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
1977  *
1978  * Forward all frames irrespective of the match status of Layer 3 and Layer 4
1979  * filters
1980  */
1981 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP 0x0
1982 /*
1983  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
1984  *
1985  * Drop frames that do not match the enabled Layer 3 and Layer 4 filters
1986  */
1987 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP 0x1
1988 
1989 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
1990 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB 20
1991 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
1992 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB 20
1993 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
1994 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH 1
1995 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
1996 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK 0x00100000
1997 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
1998 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK 0xffefffff
1999 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
2000 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET 0x0
2001 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE field value from a register. */
2002 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET(value) (((value) & 0x00100000) >> 20)
2003 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value suitable for setting the register. */
2004 #define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET(value) (((value) << 20) & 0x00100000)
2005 
2006 /*
2007  * Field : Drop non-TCP/UDP over IP Frames - dntu
2008  *
2009  * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames.
2010  * The MAC forward only those frames that are processed by the Layer 4 filter.
2011  *
2012  * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP
2013  * frames.
2014  *
2015  * Field Enumeration Values:
2016  *
2017  * Enum | Value | Description
2018  * :----------------------------------------|:------|:------------------------------------------
2019  * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP | 0x0 | Forward all non-TCP or UDP over IP frames
2020  * ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP | 0x1 | Drop non-TCP or UDP over IP frames
2021  *
2022  * Field Access Macros:
2023  *
2024  */
2025 /*
2026  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
2027  *
2028  * Forward all non-TCP or UDP over IP frames
2029  */
2030 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP 0x0
2031 /*
2032  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
2033  *
2034  * Drop non-TCP or UDP over IP frames
2035  */
2036 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP 0x1
2037 
2038 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2039 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB 21
2040 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2041 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB 21
2042 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2043 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH 1
2044 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
2045 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK 0x00200000
2046 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
2047 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK 0xffdfffff
2048 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
2049 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET 0x0
2050 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU field value from a register. */
2051 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET(value) (((value) & 0x00200000) >> 21)
2052 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value suitable for setting the register. */
2053 #define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET(value) (((value) << 21) & 0x00200000)
2054 
2055 /*
2056  * Field : Receive All - ra
2057  *
2058  * When this bit is set, the MAC Receiver block passes all received frames,
2059  * irrespective of whether they pass the address filter or not, to the Application.
2060  * The result of the SA or DA filtering is updated (pass or fail) in the
2061  * corresponding bits in the Receive Status Word.
2062  *
2063  * When this bit is reset, the Receiver block passes only those frames to the
2064  * Application that pass the SA or DA address filter.
2065  *
2066  * Field Enumeration Values:
2067  *
2068  * Enum | Value | Description
2069  * :------------------------------------|:------|:----------------
2070  * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD | 0x0 | Receive All off
2071  * ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END | 0x1 | Receive All On
2072  *
2073  * Field Access Macros:
2074  *
2075  */
2076 /*
2077  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
2078  *
2079  * Receive All off
2080  */
2081 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD 0x0
2082 /*
2083  * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
2084  *
2085  * Receive All On
2086  */
2087 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END 0x1
2088 
2089 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2090 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB 31
2091 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2092 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB 31
2093 /* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2094 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH 1
2095 /* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
2096 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK 0x80000000
2097 /* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
2098 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK 0x7fffffff
2099 /* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
2100 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET 0x0
2101 /* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RA field value from a register. */
2102 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET(value) (((value) & 0x80000000) >> 31)
2103 /* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value suitable for setting the register. */
2104 #define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET(value) (((value) << 31) & 0x80000000)
2105 
2106 #ifndef __ASSEMBLY__
2107 /*
2108  * WARNING: The C register and register group struct declarations are provided for
2109  * convenience and illustrative purposes. They should, however, be used with
2110  * caution as the C language standard provides no guarantees about the alignment or
2111  * atomicity of device memory accesses. The recommended practice for writing
2112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2113  * alt_write_word() functions.
2114  *
2115  * The struct declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT.
2116  */
2117 struct ALT_EMAC_GMAC_MAC_FRM_FLT_s
2118 {
2119  uint32_t pr : 1; /* Promiscuous Mode */
2120  uint32_t huc : 1; /* Hash Unicast */
2121  uint32_t hmc : 1; /* Hash Multicast */
2122  uint32_t daif : 1; /* DA Inverse Filtering */
2123  uint32_t pm : 1; /* Pass All Multicast */
2124  uint32_t dbf : 1; /* Disable Broadcast Frames */
2125  uint32_t pcf : 2; /* Pass Control Frames */
2126  uint32_t saif : 1; /* SA Inverse Filtering */
2127  uint32_t saf : 1; /* Source Address Filter Enable */
2128  uint32_t hpf : 1; /* Hash or Perfect Filter */
2129  uint32_t : 5; /* *UNDEFINED* */
2130  uint32_t vtfe : 1; /* VLAN Tag Filter Enable */
2131  uint32_t : 3; /* *UNDEFINED* */
2132  uint32_t ipfe : 1; /* Layer 3 and Layer 4 Filter Enable */
2133  uint32_t dntu : 1; /* Drop non-TCP/UDP over IP Frames */
2134  uint32_t : 9; /* *UNDEFINED* */
2135  uint32_t ra : 1; /* Receive All */
2136 };
2137 
2138 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT. */
2139 typedef volatile struct ALT_EMAC_GMAC_MAC_FRM_FLT_s ALT_EMAC_GMAC_MAC_FRM_FLT_t;
2140 #endif /* __ASSEMBLY__ */
2141 
2142 /* The byte offset of the ALT_EMAC_GMAC_MAC_FRM_FLT register from the beginning of the component. */
2143 #define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST 0x4
2144 /* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register. */
2145 #define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST))
2146 
2147 /*
2148  * Register : Register 4 (GMII Address Register) - GMII_Address
2149  *
2150  * The GMII Address register controls the management cycles to the external PHY
2151  * through the management interface.
2152  *
2153  * Register Layout
2154  *
2155  * Bits | Access | Reset | Description
2156  * :--------|:-------|:------|:-----------------------
2157  * [0] | RW | 0x0 | GMII Busy
2158  * [1] | RW | 0x0 | GMII Write
2159  * [5:2] | RW | 0x0 | CSR Clock Range
2160  * [10:6] | RW | 0x0 | GMII Register
2161  * [15:11] | RW | 0x0 | Physical Layer Address
2162  * [31:16] | ??? | 0x0 | *UNDEFINED*
2163  *
2164  */
2165 /*
2166  * Field : GMII Busy - gb
2167  *
2168  * This bit should read logic 0 before writing to Register 4 and Register 5. During
2169  * a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate
2170  * that a Read or Write access is in progress.
2171  *
2172  * The Register 5 is invalid until this bit is cleared by the MAC. Therefore,
2173  * Register 5 (GMII Data) should be kept valid until the MAC clears this bit during
2174  * a PHY Write operation. Similarly for a read operation, the contents of Register
2175  * 5 are not valid until this bit is cleared.
2176  *
2177  * The subsequent read or write operation should happen only after the previous
2178  * operation is complete. Because there is no acknowledgment from the PHY to MAC
2179  * after a read or write operation is completed, there is no change in the
2180  * functionality of this bit even when the PHY is not present.
2181  *
2182  * Field Enumeration Values:
2183  *
2184  * Enum | Value | Description
2185  * :----------------------------------|:------|:------------
2186  * ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD | 0x0 | Not Busy
2187  * ALT_EMAC_GMAC_GMII_ADDR_GB_E_END | 0x1 | Busy
2188  *
2189  * Field Access Macros:
2190  *
2191  */
2192 /*
2193  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
2194  *
2195  * Not Busy
2196  */
2197 #define ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD 0x0
2198 /*
2199  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
2200  *
2201  * Busy
2202  */
2203 #define ALT_EMAC_GMAC_GMII_ADDR_GB_E_END 0x1
2204 
2205 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2206 #define ALT_EMAC_GMAC_GMII_ADDR_GB_LSB 0
2207 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2208 #define ALT_EMAC_GMAC_GMII_ADDR_GB_MSB 0
2209 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2210 #define ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH 1
2211 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
2212 #define ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001
2213 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
2214 #define ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK 0xfffffffe
2215 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
2216 #define ALT_EMAC_GMAC_GMII_ADDR_GB_RESET 0x0
2217 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GB field value from a register. */
2218 #define ALT_EMAC_GMAC_GMII_ADDR_GB_GET(value) (((value) & 0x00000001) >> 0)
2219 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GB register field value suitable for setting the register. */
2220 #define ALT_EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001)
2221 
2222 /*
2223  * Field : GMII Write - gw
2224  *
2225  * When set, this bit indicates to the PHY or RevMII that this is a Write operation
2226  * using the GMII Data register. If this bit is not set, it indicates that this is
2227  * a Read operation, that is, placing the data in the GMII Data register.
2228  *
2229  * Field Enumeration Values:
2230  *
2231  * Enum | Value | Description
2232  * :----------------------------------|:------|:---------------------
2233  * ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD | 0x0 | Gmii Write Operation
2234  * ALT_EMAC_GMAC_GMII_ADDR_GW_E_END | 0x1 | Gmii Read Operation
2235  *
2236  * Field Access Macros:
2237  *
2238  */
2239 /*
2240  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
2241  *
2242  * Gmii Write Operation
2243  */
2244 #define ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD 0x0
2245 /*
2246  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
2247  *
2248  * Gmii Read Operation
2249  */
2250 #define ALT_EMAC_GMAC_GMII_ADDR_GW_E_END 0x1
2251 
2252 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2253 #define ALT_EMAC_GMAC_GMII_ADDR_GW_LSB 1
2254 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2255 #define ALT_EMAC_GMAC_GMII_ADDR_GW_MSB 1
2256 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2257 #define ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH 1
2258 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
2259 #define ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002
2260 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
2261 #define ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd
2262 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
2263 #define ALT_EMAC_GMAC_GMII_ADDR_GW_RESET 0x0
2264 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GW field value from a register. */
2265 #define ALT_EMAC_GMAC_GMII_ADDR_GW_GET(value) (((value) & 0x00000002) >> 1)
2266 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GW register field value suitable for setting the register. */
2267 #define ALT_EMAC_GMAC_GMII_ADDR_GW_SET(value) (((value) << 1) & 0x00000002)
2268 
2269 /*
2270  * Field : CSR Clock Range - cr
2271  *
2272  * The CSR Clock Range selection determines the frequency of the MDC clock
2273  * according to the l3_sp_clk frequency used in your design. The suggested range of
2274  * l3_sp_clk frequency applicable for each value (when Bit[5] = 0) ensures that the
2275  * MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.
2276  *
2277  * When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
2278  * 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower
2279  * value. For example, when l3_sp_clk is of 100 MHz frequency and you program these
2280  * bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the
2281  * limit of IEEE 802.3 specified range. Only use the values larger than 7 if the
2282  * interfacing chips support faster MDC clocks.
2283  *
2284  * Field Enumeration Values:
2285  *
2286  * Enum | Value | Description
2287  * :----------------------------------------|:------|:-------------------------------------------------
2288  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 | 0x0 | l3_sp_clk 60-100Mhz and MDC clock =
2289  * : | | l3_sp_clk/42
2290  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 | 0x1 | l3_sp_clk 100-150Mhz and MDC clock =
2291  * : | | l3_sp_clk/62
2292  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 | 0x2 | l3_sp_clk 25-35Mhz and MDC clock = l3_sp_clk/16
2293  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 | 0x3 | l3_sp_clk 35-60Mhz and MDC clock = l3_sp_clk/26
2294  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 | 0x4 | l3_sp_clk 150-250Mhz and MDC clock =
2295  * : | | l3_sp_clk/102
2296  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 | 0x5 | l3_sp_clk 250-300Mhz and MDC clock =
2297  * : | | l3_sp_clk/124
2298  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 | 0x8 | l3_sp_clk/4
2299  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 | 0x9 | l3_sp_clk/6
2300  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 | 0xa | l3_sp_clk/8
2301  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 | 0xb | l3_sp_clk/10
2302  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 | 0xc | l3_sp_clk/12
2303  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 | 0xd | l3_sp_clk/14
2304  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN | 0xe | l3_sp_clk/16
2305  * ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 | 0xf | l3_sp_clk/18
2306  *
2307  * Field Access Macros:
2308  *
2309  */
2310 /*
2311  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2312  *
2313  * l3_sp_clk 60-100Mhz and MDC clock = l3_sp_clk/42
2314  */
2315 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 0x0
2316 /*
2317  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2318  *
2319  * l3_sp_clk 100-150Mhz and MDC clock = l3_sp_clk/62
2320  */
2321 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 0x1
2322 /*
2323  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2324  *
2325  * l3_sp_clk 25-35Mhz and MDC clock = l3_sp_clk/16
2326  */
2327 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 0x2
2328 /*
2329  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2330  *
2331  * l3_sp_clk 35-60Mhz and MDC clock = l3_sp_clk/26
2332  */
2333 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 0x3
2334 /*
2335  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2336  *
2337  * l3_sp_clk 150-250Mhz and MDC clock = l3_sp_clk/102
2338  */
2339 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4
2340 /*
2341  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2342  *
2343  * l3_sp_clk 250-300Mhz and MDC clock = l3_sp_clk/124
2344  */
2345 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 0x5
2346 /*
2347  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2348  *
2349  * l3_sp_clk/4
2350  */
2351 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 0x8
2352 /*
2353  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2354  *
2355  * l3_sp_clk/6
2356  */
2357 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 0x9
2358 /*
2359  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2360  *
2361  * l3_sp_clk/8
2362  */
2363 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 0xa
2364 /*
2365  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2366  *
2367  * l3_sp_clk/10
2368  */
2369 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 0xb
2370 /*
2371  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2372  *
2373  * l3_sp_clk/12
2374  */
2375 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 0xc
2376 /*
2377  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2378  *
2379  * l3_sp_clk/14
2380  */
2381 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 0xd
2382 /*
2383  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2384  *
2385  * l3_sp_clk/16
2386  */
2387 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe
2388 /*
2389  * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
2390  *
2391  * l3_sp_clk/18
2392  */
2393 #define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 0xf
2394 
2395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2396 #define ALT_EMAC_GMAC_GMII_ADDR_CR_LSB 2
2397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2398 #define ALT_EMAC_GMAC_GMII_ADDR_CR_MSB 5
2399 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2400 #define ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH 4
2401 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
2402 #define ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK 0x0000003c
2403 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
2404 #define ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK 0xffffffc3
2405 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
2406 #define ALT_EMAC_GMAC_GMII_ADDR_CR_RESET 0x0
2407 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_CR field value from a register. */
2408 #define ALT_EMAC_GMAC_GMII_ADDR_CR_GET(value) (((value) & 0x0000003c) >> 2)
2409 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_CR register field value suitable for setting the register. */
2410 #define ALT_EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c)
2411 
2412 /*
2413  * Field : GMII Register - gr
2414  *
2415  * These bits select the desired GMII register in the selected PHY device.
2416  *
2417  * For RevMII, these bits select the desired CSR register in the RevMII Registers
2418  * set.
2419  *
2420  * Field Access Macros:
2421  *
2422  */
2423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2424 #define ALT_EMAC_GMAC_GMII_ADDR_GR_LSB 6
2425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2426 #define ALT_EMAC_GMAC_GMII_ADDR_GR_MSB 10
2427 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2428 #define ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH 5
2429 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
2430 #define ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK 0x000007c0
2431 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
2432 #define ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK 0xfffff83f
2433 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
2434 #define ALT_EMAC_GMAC_GMII_ADDR_GR_RESET 0x0
2435 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GR field value from a register. */
2436 #define ALT_EMAC_GMAC_GMII_ADDR_GR_GET(value) (((value) & 0x000007c0) >> 6)
2437 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_GR register field value suitable for setting the register. */
2438 #define ALT_EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0)
2439 
2440 /*
2441  * Field : Physical Layer Address - pa
2442  *
2443  * This field indicates which of the 32 possible PHY devices are being accessed.
2444  *
2445  * For RevMII, this field gives the PHY Address of the RevMII block.
2446  *
2447  * Field Access Macros:
2448  *
2449  */
2450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2451 #define ALT_EMAC_GMAC_GMII_ADDR_PA_LSB 11
2452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2453 #define ALT_EMAC_GMAC_GMII_ADDR_PA_MSB 15
2454 /* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2455 #define ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH 5
2456 /* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
2457 #define ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK 0x0000f800
2458 /* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
2459 #define ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK 0xffff07ff
2460 /* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
2461 #define ALT_EMAC_GMAC_GMII_ADDR_PA_RESET 0x0
2462 /* Extracts the ALT_EMAC_GMAC_GMII_ADDR_PA field value from a register. */
2463 #define ALT_EMAC_GMAC_GMII_ADDR_PA_GET(value) (((value) & 0x0000f800) >> 11)
2464 /* Produces a ALT_EMAC_GMAC_GMII_ADDR_PA register field value suitable for setting the register. */
2465 #define ALT_EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800)
2466 
2467 #ifndef __ASSEMBLY__
2468 /*
2469  * WARNING: The C register and register group struct declarations are provided for
2470  * convenience and illustrative purposes. They should, however, be used with
2471  * caution as the C language standard provides no guarantees about the alignment or
2472  * atomicity of device memory accesses. The recommended practice for writing
2473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2474  * alt_write_word() functions.
2475  *
2476  * The struct declaration for register ALT_EMAC_GMAC_GMII_ADDR.
2477  */
2478 struct ALT_EMAC_GMAC_GMII_ADDR_s
2479 {
2480  uint32_t gb : 1; /* GMII Busy */
2481  uint32_t gw : 1; /* GMII Write */
2482  uint32_t cr : 4; /* CSR Clock Range */
2483  uint32_t gr : 5; /* GMII Register */
2484  uint32_t pa : 5; /* Physical Layer Address */
2485  uint32_t : 16; /* *UNDEFINED* */
2486 };
2487 
2488 /* The typedef declaration for register ALT_EMAC_GMAC_GMII_ADDR. */
2489 typedef volatile struct ALT_EMAC_GMAC_GMII_ADDR_s ALT_EMAC_GMAC_GMII_ADDR_t;
2490 #endif /* __ASSEMBLY__ */
2491 
2492 /* The byte offset of the ALT_EMAC_GMAC_GMII_ADDR register from the beginning of the component. */
2493 #define ALT_EMAC_GMAC_GMII_ADDR_OFST 0x10
2494 /* The address of the ALT_EMAC_GMAC_GMII_ADDR register. */
2495 #define ALT_EMAC_GMAC_GMII_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST))
2496 
2497 /*
2498  * Register : Register 5 (GMII Data Register) - GMII_Data
2499  *
2500  * The GMII Data register stores Write data to be written to the PHY register
2501  * located at the address specified in Register 4 (GMII Address Register). This
2502  * register also stores the Read data from the PHY register located at the address
2503  * specified by Register 4.
2504  *
2505  * Register Layout
2506  *
2507  * Bits | Access | Reset | Description
2508  * :--------|:-------|:------|:------------
2509  * [15:0] | RW | 0x0 | GMII Data
2510  * [31:16] | ??? | 0x0 | *UNDEFINED*
2511  *
2512  */
2513 /*
2514  * Field : GMII Data - gd
2515  *
2516  * This field contains the 16-bit data value read from the PHY or RevMII after a
2517  * Management Read operation or the 16-bit data value to be written to the PHY or
2518  * RevMII before a Management Write operation.
2519  *
2520  * Field Access Macros:
2521  *
2522  */
2523 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2524 #define ALT_EMAC_GMAC_GMII_DATA_GD_LSB 0
2525 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2526 #define ALT_EMAC_GMAC_GMII_DATA_GD_MSB 15
2527 /* The width in bits of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2528 #define ALT_EMAC_GMAC_GMII_DATA_GD_WIDTH 16
2529 /* The mask used to set the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
2530 #define ALT_EMAC_GMAC_GMII_DATA_GD_SET_MSK 0x0000ffff
2531 /* The mask used to clear the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
2532 #define ALT_EMAC_GMAC_GMII_DATA_GD_CLR_MSK 0xffff0000
2533 /* The reset value of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
2534 #define ALT_EMAC_GMAC_GMII_DATA_GD_RESET 0x0
2535 /* Extracts the ALT_EMAC_GMAC_GMII_DATA_GD field value from a register. */
2536 #define ALT_EMAC_GMAC_GMII_DATA_GD_GET(value) (((value) & 0x0000ffff) >> 0)
2537 /* Produces a ALT_EMAC_GMAC_GMII_DATA_GD register field value suitable for setting the register. */
2538 #define ALT_EMAC_GMAC_GMII_DATA_GD_SET(value) (((value) << 0) & 0x0000ffff)
2539 
2540 #ifndef __ASSEMBLY__
2541 /*
2542  * WARNING: The C register and register group struct declarations are provided for
2543  * convenience and illustrative purposes. They should, however, be used with
2544  * caution as the C language standard provides no guarantees about the alignment or
2545  * atomicity of device memory accesses. The recommended practice for writing
2546  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2547  * alt_write_word() functions.
2548  *
2549  * The struct declaration for register ALT_EMAC_GMAC_GMII_DATA.
2550  */
2551 struct ALT_EMAC_GMAC_GMII_DATA_s
2552 {
2553  uint32_t gd : 16; /* GMII Data */
2554  uint32_t : 16; /* *UNDEFINED* */
2555 };
2556 
2557 /* The typedef declaration for register ALT_EMAC_GMAC_GMII_DATA. */
2558 typedef volatile struct ALT_EMAC_GMAC_GMII_DATA_s ALT_EMAC_GMAC_GMII_DATA_t;
2559 #endif /* __ASSEMBLY__ */
2560 
2561 /* The byte offset of the ALT_EMAC_GMAC_GMII_DATA register from the beginning of the component. */
2562 #define ALT_EMAC_GMAC_GMII_DATA_OFST 0x14
2563 /* The address of the ALT_EMAC_GMAC_GMII_DATA register. */
2564 #define ALT_EMAC_GMAC_GMII_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_DATA_OFST))
2565 
2566 /*
2567  * Register : Register 6 (Flow Control Register) - Flow_Control
2568  *
2569  * The Flow Control register controls the generation and reception of the Control
2570  * (Pause Command) frames by the MAC's Flow control block. A Write to a register
2571  * with the Busy bit set to '1' triggers the Flow Control block to generate a Pause
2572  * Control frame. The fields of the control frame are selected as specified in the
2573  * 802.3x specification, and the Pause Time value from this register is used in the
2574  * Pause Time field of the control frame. The Busy bit remains set until the
2575  * control frame is transferred onto the cable. The Host must make sure that the
2576  * Busy bit is cleared before writing to the register.
2577  *
2578  * Register Layout
2579  *
2580  * Bits | Access | Reset | Description
2581  * :--------|:-------|:------|:-------------------------------------------
2582  * [0] | RW | 0x0 | Flow Control Busy or Backpressure Activate
2583  * [1] | RW | 0x0 | Transmit Flow Control Enable
2584  * [2] | RW | 0x0 | Receive Flow Control Enable
2585  * [3] | RW | 0x0 | Unicast Pause Frame Detect
2586  * [5:4] | RW | 0x0 | Pause Low Threshold
2587  * [6] | ??? | 0x0 | *UNDEFINED*
2588  * [7] | RW | 0x0 | Disable Zero-Quanta Pause
2589  * [15:8] | ??? | 0x0 | *UNDEFINED*
2590  * [31:16] | RW | 0x0 | Pause Time
2591  *
2592  */
2593 /*
2594  * Field : Flow Control Busy or Backpressure Activate - fca_bpa
2595  *
2596  * This bit initiates a Pause Control frame in the full-duplex mode and activates
2597  * the backpressure function in the half-duplex mode if the TFE bit is set.
2598  *
2599  * In the full-duplex mode, this bit should be read as 1'b0 before writing to the
2600  * Flow Control register. To initiate a Pause control frame, the Application must
2601  * set this bit to 1'b1. During a transfer of the Control Frame, this bit continues
2602  * to be set to signify that a frame transmission is in progress. After the
2603  * completion of Pause control frame transmission, the MAC resets this bit to 1'b0.
2604  * The Flow Control register should not be written to until this bit is cleared.
2605  *
2606  * In the half-duplex mode, when this bit is set (and TFE is set), then
2607  * backpressure is asserted by the MAC. During backpressure, when the MAC receives
2608  * a new frame, the transmitter starts sending a JAM pattern resulting in a
2609  * collision. This control register bit is logically ORed with the mti_flowctrl_i
2610  * input signal for the backpressure function. When the MAC is configured for the
2611  * full-duplex mode, the BPA is automatically disabled.
2612  *
2613  * Field Enumeration Values:
2614  *
2615  * Enum | Value | Description
2616  * :--------------------------------------|:------|:------------------------------
2617  * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD | 0x0 | Pause Ctrl Frame and BPA off
2618  * ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END | 0x1 | Init Pause Ctrl Frame and BPA
2619  *
2620  * Field Access Macros:
2621  *
2622  */
2623 /*
2624  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
2625  *
2626  * Pause Ctrl Frame and BPA off
2627  */
2628 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD 0x0
2629 /*
2630  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
2631  *
2632  * Init Pause Ctrl Frame and BPA
2633  */
2634 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END 0x1
2635 
2636 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
2637 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB 0
2638 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
2639 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB 0
2640 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
2641 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH 1
2642 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
2643 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK 0x00000001
2644 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
2645 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK 0xfffffffe
2646 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
2647 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET 0x0
2648 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register. */
2649 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value) (((value) & 0x00000001) >> 0)
2650 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register. */
2651 #define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value) (((value) << 0) & 0x00000001)
2652 
2653 /*
2654  * Field : Transmit Flow Control Enable - tfe
2655  *
2656  * In the full-duplex mode, when this bit is set, the MAC enables the flow control
2657  * operation to transmit Pause frames. When this bit is reset, the flow control
2658  * operation in the MAC is disabled, and the MAC does not transmit any Pause
2659  * frames.
2660  *
2661  * In half-duplex mode, when this bit is set, the MAC enables the back-pressure
2662  * operation. When this bit is reset, the back-pressure feature is disabled.
2663  *
2664  * Field Enumeration Values:
2665  *
2666  * Enum | Value | Description
2667  * :----------------------------------|:------|:------------------------------
2668  * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD | 0x0 | Transmit Flow Control Disable
2669  * ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END | 0x1 | Transmit Flow Control Enable
2670  *
2671  * Field Access Macros:
2672  *
2673  */
2674 /*
2675  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
2676  *
2677  * Transmit Flow Control Disable
2678  */
2679 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD 0x0
2680 /*
2681  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
2682  *
2683  * Transmit Flow Control Enable
2684  */
2685 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END 0x1
2686 
2687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
2688 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB 1
2689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
2690 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB 1
2691 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
2692 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH 1
2693 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
2694 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK 0x00000002
2695 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
2696 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK 0xfffffffd
2697 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
2698 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET 0x0
2699 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register. */
2700 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value) (((value) & 0x00000002) >> 1)
2701 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register. */
2702 #define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value) (((value) << 1) & 0x00000002)
2703 
2704 /*
2705  * Field : Receive Flow Control Enable - rfe
2706  *
2707  * When this bit is set, the MAC decodes the received Pause frame and disables its
2708  * transmitter for a specified (Pause) time. When this bit is reset, the decode
2709  * function of the Pause frame is disabled.
2710  *
2711  * Field Enumeration Values:
2712  *
2713  * Enum | Value | Description
2714  * :----------------------------------|:------|:-------------------------------------
2715  * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD | 0x0 | Decode Func. of Pause Frame Disabled
2716  * ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END | 0x1 | MAC decodes the received Pause
2717  *
2718  * Field Access Macros:
2719  *
2720  */
2721 /*
2722  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
2723  *
2724  * Decode Func. of Pause Frame Disabled
2725  */
2726 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD 0x0
2727 /*
2728  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
2729  *
2730  * MAC decodes the received Pause
2731  */
2732 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END 0x1
2733 
2734 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
2735 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB 2
2736 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
2737 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB 2
2738 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
2739 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH 1
2740 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
2741 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK 0x00000004
2742 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
2743 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK 0xfffffffb
2744 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
2745 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET 0x0
2746 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register. */
2747 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value) (((value) & 0x00000004) >> 2)
2748 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register. */
2749 #define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value) (((value) << 2) & 0x00000004)
2750 
2751 /*
2752  * Field : Unicast Pause Frame Detect - up
2753  *
2754  * When this bit is set, then in addition to the detecting Pause frames with the
2755  * unique multicast address, the MAC detects the Pause frames with the station's
2756  * unicast address specified in the MAC Address0 High Register and MAC Address0 Low
2757  * Register. When this bit is reset, the MAC detects only a Pause frame with the
2758  * unique multicast address specified in the 802.3x standard.
2759  *
2760  * Field Enumeration Values:
2761  *
2762  * Enum | Value | Description
2763  * :---------------------------------|:------|:------------------------------
2764  * ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD | 0x0 | MAC Detects Pause MCA
2765  * ALT_EMAC_GMAC_FLOW_CTL_UP_E_END | 0x1 | MAC Detects Pause MCA and UCA
2766  *
2767  * Field Access Macros:
2768  *
2769  */
2770 /*
2771  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
2772  *
2773  * MAC Detects Pause MCA
2774  */
2775 #define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD 0x0
2776 /*
2777  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
2778  *
2779  * MAC Detects Pause MCA and UCA
2780  */
2781 #define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END 0x1
2782 
2783 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
2784 #define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB 3
2785 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
2786 #define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB 3
2787 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
2788 #define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH 1
2789 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
2790 #define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK 0x00000008
2791 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
2792 #define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK 0xfffffff7
2793 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
2794 #define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET 0x0
2795 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register. */
2796 #define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value) (((value) & 0x00000008) >> 3)
2797 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register. */
2798 #define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value) (((value) << 3) & 0x00000008)
2799 
2800 /*
2801  * Field : Pause Low Threshold - plt
2802  *
2803  * This field configures the threshold of the PAUSE timer at which the input flow
2804  * control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic
2805  * retransmission of PAUSE Frame.
2806  *
2807  * The threshold values should be always less than the Pause Time configured in
2808  * Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a
2809  * second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is
2810  * asserted at 228 (256 - 28) slot times after the first PAUSE frame is
2811  * transmitted.
2812  *
2813  * The slot time is defined as the time taken to transmit 512 bits (64 bytes) on
2814  * the GMII or MII interface.
2815  *
2816  * Field Enumeration Values:
2817  *
2818  * Enum | Value | Description
2819  * :-------------------------------------------|:------|:----------------------------
2820  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 | 0x0 | Pause time - 4 slot times
2821  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 | 0x1 | Pause time - 28 slot times
2822  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 | 0x2 | Pause time - 144 slot times
2823  * ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 | 0x3 | Pause time - 256 slot times
2824  *
2825  * Field Access Macros:
2826  *
2827  */
2828 /*
2829  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
2830  *
2831  * Pause time - 4 slot times
2832  */
2833 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 0x0
2834 /*
2835  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
2836  *
2837  * Pause time - 28 slot times
2838  */
2839 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 0x1
2840 /*
2841  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
2842  *
2843  * Pause time - 144 slot times
2844  */
2845 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 0x2
2846 /*
2847  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
2848  *
2849  * Pause time - 256 slot times
2850  */
2851 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 0x3
2852 
2853 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
2854 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB 4
2855 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
2856 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB 5
2857 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
2858 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH 2
2859 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
2860 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK 0x00000030
2861 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
2862 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK 0xffffffcf
2863 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
2864 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET 0x0
2865 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register. */
2866 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value) (((value) & 0x00000030) >> 4)
2867 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register. */
2868 #define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value) (((value) << 4) & 0x00000030)
2869 
2870 /*
2871  * Field : Disable Zero-Quanta Pause - dzpq
2872  *
2873  * When this bit is set, it disables the automatic generation of the Zero-Quanta
2874  * Pause Control frames on the de-assertion of the flow-control signal from the
2875  * FIFO layer (MTL or external sideband flow control signal
2876  * sbd_flowctrl_i/mti_flowctrl_i).
2877  *
2878  * When this bit is reset, normal operation with automatic Zero-Quanta Pause
2879  * Control frame generation is enabled.
2880  *
2881  * Field Enumeration Values:
2882  *
2883  * Enum | Value | Description
2884  * :-----------------------------------|:------|:---------------------------------------
2885  * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END | 0x1 | Disable Auto Gen. of Zero-Quanta Pause
2886  * ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD | 0x0 | Enable Auto Gen. of Zero-Quanta Pause
2887  *
2888  * Field Access Macros:
2889  *
2890  */
2891 /*
2892  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
2893  *
2894  * Disable Auto Gen. of Zero-Quanta Pause
2895  */
2896 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END 0x1
2897 /*
2898  * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
2899  *
2900  * Enable Auto Gen. of Zero-Quanta Pause
2901  */
2902 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD 0x0
2903 
2904 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
2905 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB 7
2906 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
2907 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB 7
2908 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
2909 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH 1
2910 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
2911 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK 0x00000080
2912 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
2913 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK 0xffffff7f
2914 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
2915 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET 0x0
2916 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register. */
2917 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value) (((value) & 0x00000080) >> 7)
2918 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register. */
2919 #define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value) (((value) << 7) & 0x00000080)
2920 
2921 /*
2922  * Field : Pause Time - pt
2923  *
2924  * This field holds the value to be used in the Pause Time field in the transmit
2925  * control frame. Because the Pause Time bits are double-synchronized to the (G)MII
2926  * clock domain, then consecutive writes to this register should be performed only
2927  * after at least four clock cycles in the destination clock domain.
2928  *
2929  * Field Access Macros:
2930  *
2931  */
2932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
2933 #define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB 16
2934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
2935 #define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB 31
2936 /* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
2937 #define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH 16
2938 /* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
2939 #define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK 0xffff0000
2940 /* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
2941 #define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK 0x0000ffff
2942 /* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
2943 #define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET 0x0
2944 /* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register. */
2945 #define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value) (((value) & 0xffff0000) >> 16)
2946 /* Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register. */
2947 #define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value) (((value) << 16) & 0xffff0000)
2948 
2949 #ifndef __ASSEMBLY__
2950 /*
2951  * WARNING: The C register and register group struct declarations are provided for
2952  * convenience and illustrative purposes. They should, however, be used with
2953  * caution as the C language standard provides no guarantees about the alignment or
2954  * atomicity of device memory accesses. The recommended practice for writing
2955  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2956  * alt_write_word() functions.
2957  *
2958  * The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL.
2959  */
2960 struct ALT_EMAC_GMAC_FLOW_CTL_s
2961 {
2962  uint32_t fca_bpa : 1; /* Flow Control Busy or Backpressure Activate */
2963  uint32_t tfe : 1; /* Transmit Flow Control Enable */
2964  uint32_t rfe : 1; /* Receive Flow Control Enable */
2965  uint32_t up : 1; /* Unicast Pause Frame Detect */
2966  uint32_t plt : 2; /* Pause Low Threshold */
2967  uint32_t : 1; /* *UNDEFINED* */
2968  uint32_t dzpq : 1; /* Disable Zero-Quanta Pause */
2969  uint32_t : 8; /* *UNDEFINED* */
2970  uint32_t pt : 16; /* Pause Time */
2971 };
2972 
2973 /* The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL. */
2974 typedef volatile struct ALT_EMAC_GMAC_FLOW_CTL_s ALT_EMAC_GMAC_FLOW_CTL_t;
2975 #endif /* __ASSEMBLY__ */
2976 
2977 /* The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component. */
2978 #define ALT_EMAC_GMAC_FLOW_CTL_OFST 0x18
2979 /* The address of the ALT_EMAC_GMAC_FLOW_CTL register. */
2980 #define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))
2981 
2982 /*
2983  * Register : Register 7 (VLAN Tag Register) - VLAN_Tag
2984  *
2985  * The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN
2986  * frames. The MAC compares the 13th and 14th bytes of the receiving frame
2987  * (Length/Type) with 16'h8100, and the following two bytes are compared with the
2988  * VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive
2989  * frame status. The legal length of the frame is increased from 1,518 bytes to
2990  * 1,522 bytes.
2991  *
2992  * Because the VLAN Tag register is double-synchronized to the (G)MII clock domain,
2993  * then consecutive writes to these register should be performed only after at
2994  * least four clock cycles in the destination clock domain.
2995  *
2996  * Register Layout
2997  *
2998  * Bits | Access | Reset | Description
2999  * :--------|:-------|:------|:---------------------------------------
3000  * [15:0] | RW | 0x0 | VLAN Tag Identifier for Receive Frames
3001  * [16] | RW | 0x0 | Enable 12-Bit VLAN Tag Comparison
3002  * [17] | RW | 0x0 | VLAN Tag Inverse Match Enable
3003  * [18] | RW | 0x0 | Enable S-VLAN
3004  * [19] | RW | 0x0 | VLAN Tag Hash Table Match Enable
3005  * [31:20] | ??? | 0x0 | *UNDEFINED*
3006  *
3007  */
3008 /*
3009  * Field : VLAN Tag Identifier for Receive Frames - vl
3010  *
3011  * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is
3012  * compared to the 15th and 16th bytes of the frames being received for VLAN
3013  * frames. The following list describes the bits of this field:
3014  *
3015  * * Bits [15:13]: User Priority
3016  *
3017  * * Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
3018  *
3019  * * Bits[11:0]: VLAN tag's VLAN Identifier (VID) field
3020  *
3021  * When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.
3022  *
3023  * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the
3024  * fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a
3025  * Type field value of 0x8100 or 0x88a8 as VLAN frames.
3026  *
3027  * Field Access Macros:
3028  *
3029  */
3030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3031 #define ALT_EMAC_GMAC_VLAN_TAG_VL_LSB 0
3032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3033 #define ALT_EMAC_GMAC_VLAN_TAG_VL_MSB 15
3034 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3035 #define ALT_EMAC_GMAC_VLAN_TAG_VL_WIDTH 16
3036 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
3037 #define ALT_EMAC_GMAC_VLAN_TAG_VL_SET_MSK 0x0000ffff
3038 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
3039 #define ALT_EMAC_GMAC_VLAN_TAG_VL_CLR_MSK 0xffff0000
3040 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
3041 #define ALT_EMAC_GMAC_VLAN_TAG_VL_RESET 0x0
3042 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VL field value from a register. */
3043 #define ALT_EMAC_GMAC_VLAN_TAG_VL_GET(value) (((value) & 0x0000ffff) >> 0)
3044 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VL register field value suitable for setting the register. */
3045 #define ALT_EMAC_GMAC_VLAN_TAG_VL_SET(value) (((value) << 0) & 0x0000ffff)
3046 
3047 /*
3048  * Field : Enable 12-Bit VLAN Tag Comparison - etv
3049  *
3050  * When this bit is set, a 12-bit VLAN identifier is used for comparing and
3051  * filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are
3052  * compared with the corresponding field in the received VLAN-tagged frame.
3053  * Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are
3054  * used for hash-based VLAN filtering.
3055  *
3056  * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received
3057  * VLAN frame are used for comparison and VLAN hash filtering.
3058  *
3059  * Field Enumeration Values:
3060  *
3061  * Enum | Value | Description
3062  * :----------------------------------|:------|:--------------------------------
3063  * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD | 0x0 | Disable 12-Bit VLAN Tag Compare
3064  * ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END | 0x1 | Enable 12-Bit VLAN Tag Compare
3065  *
3066  * Field Access Macros:
3067  *
3068  */
3069 /*
3070  * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
3071  *
3072  * Disable 12-Bit VLAN Tag Compare
3073  */
3074 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD 0x0
3075 /*
3076  * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
3077  *
3078  * Enable 12-Bit VLAN Tag Compare
3079  */
3080 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END 0x1
3081 
3082 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3083 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_LSB 16
3084 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3085 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_MSB 16
3086 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3087 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_WIDTH 1
3088 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
3089 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET_MSK 0x00010000
3090 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
3091 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_CLR_MSK 0xfffeffff
3092 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
3093 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_RESET 0x0
3094 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ETV field value from a register. */
3095 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_GET(value) (((value) & 0x00010000) >> 16)
3096 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_ETV register field value suitable for setting the register. */
3097 #define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET(value) (((value) << 16) & 0x00010000)
3098 
3099 /*
3100  * Field : VLAN Tag Inverse Match Enable - vtim
3101  *
3102  * When set, this bit enables the VLAN Tag inverse matching. The frames that do not
3103  * have matching VLAN Tag are marked as matched.
3104  *
3105  * When reset, this bit enables the VLAN Tag perfect matching. The frames with
3106  * matched VLAN Tag are marked as matched.
3107  *
3108  * Field Access Macros:
3109  *
3110  */
3111 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3112 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_LSB 17
3113 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3114 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_MSB 17
3115 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3116 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_WIDTH 1
3117 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
3118 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET_MSK 0x00020000
3119 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
3120 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_CLR_MSK 0xfffdffff
3121 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
3122 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_RESET 0x0
3123 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTIM field value from a register. */
3124 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_GET(value) (((value) & 0x00020000) >> 17)
3125 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value suitable for setting the register. */
3126 #define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET(value) (((value) << 17) & 0x00020000)
3127 
3128 /*
3129  * Field : Enable S-VLAN - esvl
3130  *
3131  * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN
3132  * (Type = 0x88A8) frames as valid VLAN tagged frames.
3133  *
3134  * Field Access Macros:
3135  *
3136  */
3137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3138 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_LSB 18
3139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3140 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_MSB 18
3141 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3142 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_WIDTH 1
3143 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
3144 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET_MSK 0x00040000
3145 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
3146 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_CLR_MSK 0xfffbffff
3147 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
3148 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_RESET 0x0
3149 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ESVL field value from a register. */
3150 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_GET(value) (((value) & 0x00040000) >> 18)
3151 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value suitable for setting the register. */
3152 #define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET(value) (((value) << 18) & 0x00040000)
3153 
3154 /*
3155  * Field : VLAN Tag Hash Table Match Enable - vthm
3156  *
3157  * When set, the most significant four bits of the VLAN tag's CRC are used to index
3158  * the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN
3159  * Hash Table register, corresponding to the index, indicates that the frame
3160  * matched the VLAN hash table.
3161  *
3162  * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used
3163  * for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used
3164  * for comparison.
3165  *
3166  * When reset, the VLAN Hash Match operation is not performed.
3167  *
3168  * Field Access Macros:
3169  *
3170  */
3171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3172 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_LSB 19
3173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3174 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_MSB 19
3175 /* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3176 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_WIDTH 1
3177 /* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
3178 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET_MSK 0x00080000
3179 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
3180 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_CLR_MSK 0xfff7ffff
3181 /* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
3182 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_RESET 0x0
3183 /* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTHM field value from a register. */
3184 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_GET(value) (((value) & 0x00080000) >> 19)
3185 /* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value suitable for setting the register. */
3186 #define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET(value) (((value) << 19) & 0x00080000)
3187 
3188 #ifndef __ASSEMBLY__
3189 /*
3190  * WARNING: The C register and register group struct declarations are provided for
3191  * convenience and illustrative purposes. They should, however, be used with
3192  * caution as the C language standard provides no guarantees about the alignment or
3193  * atomicity of device memory accesses. The recommended practice for writing
3194  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3195  * alt_write_word() functions.
3196  *
3197  * The struct declaration for register ALT_EMAC_GMAC_VLAN_TAG.
3198  */
3199 struct ALT_EMAC_GMAC_VLAN_TAG_s
3200 {
3201  uint32_t vl : 16; /* VLAN Tag Identifier for Receive Frames */
3202  uint32_t etv : 1; /* Enable 12-Bit VLAN Tag Comparison */
3203  uint32_t vtim : 1; /* VLAN Tag Inverse Match Enable */
3204  uint32_t esvl : 1; /* Enable S-VLAN */
3205  uint32_t vthm : 1; /* VLAN Tag Hash Table Match Enable */
3206  uint32_t : 12; /* *UNDEFINED* */
3207 };
3208 
3209 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_TAG. */
3210 typedef volatile struct ALT_EMAC_GMAC_VLAN_TAG_s ALT_EMAC_GMAC_VLAN_TAG_t;
3211 #endif /* __ASSEMBLY__ */
3212 
3213 /* The byte offset of the ALT_EMAC_GMAC_VLAN_TAG register from the beginning of the component. */
3214 #define ALT_EMAC_GMAC_VLAN_TAG_OFST 0x1c
3215 /* The address of the ALT_EMAC_GMAC_VLAN_TAG register. */
3216 #define ALT_EMAC_GMAC_VLAN_TAG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_TAG_OFST))
3217 
3218 /*
3219  * Register : Register 8 (Version Register) - Version
3220  *
3221  * The Version registers identifies the version of the EMAC. This register contains
3222  * two bytes: one specified by Synopsys to identify the core release number, and
3223  * the other specified by Altera.
3224  *
3225  * Register Layout
3226  *
3227  * Bits | Access | Reset | Description
3228  * :--------|:-------|:------|:--------------------------
3229  * [7:0] | R | 0x37 | ALT_EMAC_GMAC_VER_SNPSVER
3230  * [15:8] | R | 0x10 | ALT_EMAC_GMAC_VER_USERVER
3231  * [31:16] | ??? | 0x0 | *UNDEFINED*
3232  *
3233  */
3234 /*
3235  * Field : snpsver
3236  *
3237  * Synopsys-defined Version (3.7)
3238  *
3239  * Field Access Macros:
3240  *
3241  */
3242 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3243 #define ALT_EMAC_GMAC_VER_SNPSVER_LSB 0
3244 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3245 #define ALT_EMAC_GMAC_VER_SNPSVER_MSB 7
3246 /* The width in bits of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3247 #define ALT_EMAC_GMAC_VER_SNPSVER_WIDTH 8
3248 /* The mask used to set the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
3249 #define ALT_EMAC_GMAC_VER_SNPSVER_SET_MSK 0x000000ff
3250 /* The mask used to clear the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
3251 #define ALT_EMAC_GMAC_VER_SNPSVER_CLR_MSK 0xffffff00
3252 /* The reset value of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
3253 #define ALT_EMAC_GMAC_VER_SNPSVER_RESET 0x37
3254 /* Extracts the ALT_EMAC_GMAC_VER_SNPSVER field value from a register. */
3255 #define ALT_EMAC_GMAC_VER_SNPSVER_GET(value) (((value) & 0x000000ff) >> 0)
3256 /* Produces a ALT_EMAC_GMAC_VER_SNPSVER register field value suitable for setting the register. */
3257 #define ALT_EMAC_GMAC_VER_SNPSVER_SET(value) (((value) << 0) & 0x000000ff)
3258 
3259 /*
3260  * Field : userver
3261  *
3262  * Altera-defined Version
3263  *
3264  * Field Access Macros:
3265  *
3266  */
3267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
3268 #define ALT_EMAC_GMAC_VER_USERVER_LSB 8
3269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
3270 #define ALT_EMAC_GMAC_VER_USERVER_MSB 15
3271 /* The width in bits of the ALT_EMAC_GMAC_VER_USERVER register field. */
3272 #define ALT_EMAC_GMAC_VER_USERVER_WIDTH 8
3273 /* The mask used to set the ALT_EMAC_GMAC_VER_USERVER register field value. */
3274 #define ALT_EMAC_GMAC_VER_USERVER_SET_MSK 0x0000ff00
3275 /* The mask used to clear the ALT_EMAC_GMAC_VER_USERVER register field value. */
3276 #define ALT_EMAC_GMAC_VER_USERVER_CLR_MSK 0xffff00ff
3277 /* The reset value of the ALT_EMAC_GMAC_VER_USERVER register field. */
3278 #define ALT_EMAC_GMAC_VER_USERVER_RESET 0x10
3279 /* Extracts the ALT_EMAC_GMAC_VER_USERVER field value from a register. */
3280 #define ALT_EMAC_GMAC_VER_USERVER_GET(value) (((value) & 0x0000ff00) >> 8)
3281 /* Produces a ALT_EMAC_GMAC_VER_USERVER register field value suitable for setting the register. */
3282 #define ALT_EMAC_GMAC_VER_USERVER_SET(value) (((value) << 8) & 0x0000ff00)
3283 
3284 #ifndef __ASSEMBLY__
3285 /*
3286  * WARNING: The C register and register group struct declarations are provided for
3287  * convenience and illustrative purposes. They should, however, be used with
3288  * caution as the C language standard provides no guarantees about the alignment or
3289  * atomicity of device memory accesses. The recommended practice for writing
3290  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3291  * alt_write_word() functions.
3292  *
3293  * The struct declaration for register ALT_EMAC_GMAC_VER.
3294  */
3295 struct ALT_EMAC_GMAC_VER_s
3296 {
3297  const uint32_t snpsver : 8; /* ALT_EMAC_GMAC_VER_SNPSVER */
3298  const uint32_t userver : 8; /* ALT_EMAC_GMAC_VER_USERVER */
3299  uint32_t : 16; /* *UNDEFINED* */
3300 };
3301 
3302 /* The typedef declaration for register ALT_EMAC_GMAC_VER. */
3303 typedef volatile struct ALT_EMAC_GMAC_VER_s ALT_EMAC_GMAC_VER_t;
3304 #endif /* __ASSEMBLY__ */
3305 
3306 /* The byte offset of the ALT_EMAC_GMAC_VER register from the beginning of the component. */
3307 #define ALT_EMAC_GMAC_VER_OFST 0x20
3308 /* The address of the ALT_EMAC_GMAC_VER register. */
3309 #define ALT_EMAC_GMAC_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VER_OFST))
3310 
3311 /*
3312  * Register : Register 9 (Debug Register) - Debug
3313  *
3314  * The Debug register gives the status of all main blocks of the transmit and
3315  * receive data-paths and the FIFOs. An all-zero status indicates that the MAC is
3316  * in idle state (and FIFOs are empty) and no activity is going on in the data-
3317  * paths.
3318  *
3319  * Register Layout
3320  *
3321  * Bits | Access | Reset | Description
3322  * :--------|:-------|:------|:------------------------------------------------
3323  * [0] | R | 0x0 | MAC GMII or MII Receive Protocol Engine Status
3324  * [2:1] | R | 0x0 | MAC Receive Frame Controller FIFO Status
3325  * [3] | ??? | 0x0 | *UNDEFINED*
3326  * [4] | R | 0x0 | MTL Rx FIFO Write Controller Active Status
3327  * [6:5] | R | 0x0 | MTL Rx FIFO Read Controller State
3328  * [7] | ??? | 0x0 | *UNDEFINED*
3329  * [9:8] | R | 0x0 | MTL Rx FIFO Fill-level Status
3330  * [15:10] | ??? | 0x0 | *UNDEFINED*
3331  * [16] | R | 0x0 | MAC GMII or MII Transmit Protocol Engine Status
3332  * [18:17] | R | 0x0 | MAC Transmit Frame Controller Status
3333  * [19] | R | 0x0 | MAC transmitter in PAUSE
3334  * [21:20] | R | 0x0 | MTL Tx FIFO Read Controller Status
3335  * [22] | R | 0x0 | MTL Tx FIFO Write Controller Active Status
3336  * [23] | ??? | 0x0 | *UNDEFINED*
3337  * [24] | R | 0x0 | MTL Tx FIFO Not Empty Status
3338  * [25] | R | 0x0 | MTL TxStatus FIFO Full Status
3339  * [31:26] | ??? | 0x0 | *UNDEFINED*
3340  *
3341  */
3342 /*
3343  * Field : MAC GMII or MII Receive Protocol Engine Status - rpests
3344  *
3345  * When high, this bit indicates that the MAC GMII or MII receive protocol engine
3346  * is actively receiving data and not in IDLE state.
3347  *
3348  * Field Enumeration Values:
3349  *
3350  * Enum | Value | Description
3351  * :---------------------------------|:------|:-----------------------
3352  * ALT_EMAC_GMAC_DBG_RPESTS_E_INACT | 0x0 | Idle State
3353  * ALT_EMAC_GMAC_DBG_RPESTS_E_ACT | 0x1 | Protocol Engine Active
3354  *
3355  * Field Access Macros:
3356  *
3357  */
3358 /*
3359  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
3360  *
3361  * Idle State
3362  */
3363 #define ALT_EMAC_GMAC_DBG_RPESTS_E_INACT 0x0
3364 /*
3365  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
3366  *
3367  * Protocol Engine Active
3368  */
3369 #define ALT_EMAC_GMAC_DBG_RPESTS_E_ACT 0x1
3370 
3371 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3372 #define ALT_EMAC_GMAC_DBG_RPESTS_LSB 0
3373 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3374 #define ALT_EMAC_GMAC_DBG_RPESTS_MSB 0
3375 /* The width in bits of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3376 #define ALT_EMAC_GMAC_DBG_RPESTS_WIDTH 1
3377 /* The mask used to set the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
3378 #define ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK 0x00000001
3379 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
3380 #define ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK 0xfffffffe
3381 /* The reset value of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
3382 #define ALT_EMAC_GMAC_DBG_RPESTS_RESET 0x0
3383 /* Extracts the ALT_EMAC_GMAC_DBG_RPESTS field value from a register. */
3384 #define ALT_EMAC_GMAC_DBG_RPESTS_GET(value) (((value) & 0x00000001) >> 0)
3385 /* Produces a ALT_EMAC_GMAC_DBG_RPESTS register field value suitable for setting the register. */
3386 #define ALT_EMAC_GMAC_DBG_RPESTS_SET(value) (((value) << 0) & 0x00000001)
3387 
3388 /*
3389  * Field : MAC Receive Frame Controller FIFO Status - rfcfcsts
3390  *
3391  * When high, this field indicates the active state of the small FIFO Read and
3392  * Write controllers of the MAC Receive Frame Controller Module.
3393  *
3394  * Field Enumeration Values:
3395  *
3396  * Enum | Value | Description
3397  * :-----------------------------------|:------|:-------------------------------------
3398  * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT | 0x0 | Disable Active State FIFO Read Write
3399  * ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT | 0x1 | Enable Active State FIFO Read Write
3400  *
3401  * Field Access Macros:
3402  *
3403  */
3404 /*
3405  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
3406  *
3407  * Disable Active State FIFO Read Write
3408  */
3409 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT 0x0
3410 /*
3411  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
3412  *
3413  * Enable Active State FIFO Read Write
3414  */
3415 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT 0x1
3416 
3417 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3418 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB 1
3419 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3420 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB 2
3421 /* The width in bits of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3422 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH 2
3423 /* The mask used to set the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
3424 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK 0x00000006
3425 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
3426 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK 0xfffffff9
3427 /* The reset value of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
3428 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET 0x0
3429 /* Extracts the ALT_EMAC_GMAC_DBG_RFCFCSTS field value from a register. */
3430 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_GET(value) (((value) & 0x00000006) >> 1)
3431 /* Produces a ALT_EMAC_GMAC_DBG_RFCFCSTS register field value suitable for setting the register. */
3432 #define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET(value) (((value) << 1) & 0x00000006)
3433 
3434 /*
3435  * Field : MTL Rx FIFO Write Controller Active Status - rwcsts
3436  *
3437  * When high, this bit indicates that the MTL Rx FIFO Write Controller is active
3438  * and is transferring a received frame to the FIFO.
3439  *
3440  * Field Enumeration Values:
3441  *
3442  * Enum | Value | Description
3443  * :---------------------------------|:------|:-----------------------------------------
3444  * ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT | 0x0 | MTL Rx Fifo Controller Non-Active Status
3445  * ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT | 0x1 | MTL Rx Fifo Controller Active Status
3446  *
3447  * Field Access Macros:
3448  *
3449  */
3450 /*
3451  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
3452  *
3453  * MTL Rx Fifo Controller Non-Active Status
3454  */
3455 #define ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT 0x0
3456 /*
3457  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
3458  *
3459  * MTL Rx Fifo Controller Active Status
3460  */
3461 #define ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT 0x1
3462 
3463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
3464 #define ALT_EMAC_GMAC_DBG_RWCSTS_LSB 4
3465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
3466 #define ALT_EMAC_GMAC_DBG_RWCSTS_MSB 4
3467 /* The width in bits of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
3468 #define ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH 1
3469 /* The mask used to set the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
3470 #define ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK 0x00000010
3471 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
3472 #define ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK 0xffffffef
3473 /* The reset value of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
3474 #define ALT_EMAC_GMAC_DBG_RWCSTS_RESET 0x0
3475 /* Extracts the ALT_EMAC_GMAC_DBG_RWCSTS field value from a register. */
3476 #define ALT_EMAC_GMAC_DBG_RWCSTS_GET(value) (((value) & 0x00000010) >> 4)
3477 /* Produces a ALT_EMAC_GMAC_DBG_RWCSTS register field value suitable for setting the register. */
3478 #define ALT_EMAC_GMAC_DBG_RWCSTS_SET(value) (((value) << 4) & 0x00000010)
3479 
3480 /*
3481  * Field : MTL Rx FIFO Read Controller State - rrcsts
3482  *
3483  * This field gives the state of the Rx FIFO read Controller
3484  *
3485  * Field Enumeration Values:
3486  *
3487  * Enum | Value | Description
3488  * :-------------------------------------|:------|:------------------------------------
3489  * ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE | 0x0 | IDLE State
3490  * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA | 0x1 | Reading Frame Data
3491  * ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT | 0x2 | Reading Frame Status (or timestamp)
3492  * ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS | 0x3 | Flushing Frame Data and Status
3493  *
3494  * Field Access Macros:
3495  *
3496  */
3497 /*
3498  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
3499  *
3500  * IDLE State
3501  */
3502 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE 0x0
3503 /*
3504  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
3505  *
3506  * Reading Frame Data
3507  */
3508 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA 0x1
3509 /*
3510  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
3511  *
3512  * Reading Frame Status (or timestamp)
3513  */
3514 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT 0x2
3515 /*
3516  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
3517  *
3518  * Flushing Frame Data and Status
3519  */
3520 #define ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS 0x3
3521 
3522 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
3523 #define ALT_EMAC_GMAC_DBG_RRCSTS_LSB 5
3524 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
3525 #define ALT_EMAC_GMAC_DBG_RRCSTS_MSB 6
3526 /* The width in bits of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
3527 #define ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH 2
3528 /* The mask used to set the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
3529 #define ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK 0x00000060
3530 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
3531 #define ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK 0xffffff9f
3532 /* The reset value of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
3533 #define ALT_EMAC_GMAC_DBG_RRCSTS_RESET 0x0
3534 /* Extracts the ALT_EMAC_GMAC_DBG_RRCSTS field value from a register. */
3535 #define ALT_EMAC_GMAC_DBG_RRCSTS_GET(value) (((value) & 0x00000060) >> 5)
3536 /* Produces a ALT_EMAC_GMAC_DBG_RRCSTS register field value suitable for setting the register. */
3537 #define ALT_EMAC_GMAC_DBG_RRCSTS_SET(value) (((value) << 5) & 0x00000060)
3538 
3539 /*
3540  * Field : MTL Rx FIFO Fill-level Status - rxfsts
3541  *
3542  * This field gives the status of the fill-level of the Rx FIFO.
3543  *
3544  * Field Enumeration Values:
3545  *
3546  * Enum | Value | Description
3547  * :----------------------------------------|:------|:-------------------------------------------------
3548  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY | 0x0 | Rx FIFO Empty
3549  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL | 0x1 | Rx FIFO fill-level below flow-control deactivate
3550  * : | | thres.
3551  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL | 0x2 | Rx FIFO fill-level above flow-control activate
3552  * : | | thres.
3553  * ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL | 0x3 | Rx FIFO Full
3554  *
3555  * Field Access Macros:
3556  *
3557  */
3558 /*
3559  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
3560  *
3561  * Rx FIFO Empty
3562  */
3563 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY 0x0
3564 /*
3565  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
3566  *
3567  * Rx FIFO fill-level below flow-control deactivate thres.
3568  */
3569 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1
3570 /*
3571  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
3572  *
3573  * Rx FIFO fill-level above flow-control activate thres.
3574  */
3575 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL 0x2
3576 /*
3577  * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
3578  *
3579  * Rx FIFO Full
3580  */
3581 #define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL 0x3
3582 
3583 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
3584 #define ALT_EMAC_GMAC_DBG_RXFSTS_LSB 8
3585 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
3586 #define ALT_EMAC_GMAC_DBG_RXFSTS_MSB 9
3587 /* The width in bits of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
3588 #define ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH 2
3589 /* The mask used to set the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
3590 #define ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK 0x00000300
3591 /* The mask used to clear the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
3592 #define ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK 0xfffffcff
3593 /* The reset value of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
3594 #define ALT_EMAC_GMAC_DBG_RXFSTS_RESET 0x0
3595 /* Extracts the ALT_EMAC_GMAC_DBG_RXFSTS field value from a register. */
3596 #define ALT_EMAC_GMAC_DBG_RXFSTS_GET(value) (((value) & 0x00000300) >> 8)
3597 /* Produces a ALT_EMAC_GMAC_DBG_RXFSTS register field value suitable for setting the register. */
3598 #define ALT_EMAC_GMAC_DBG_RXFSTS_SET(value) (((value) << 8) & 0x00000300)
3599 
3600 /*
3601  * Field : MAC GMII or MII Transmit Protocol Engine Status - tpests
3602  *
3603  * When high, this bit indicates that the MAC GMII or MII transmit protocol engine
3604  * is actively transmitting data and is not in the IDLE state.
3605  *
3606  * Field Enumeration Values:
3607  *
3608  * Enum | Value | Description
3609  * :--------------------------------|:------|:---------------------------
3610  * ALT_EMAC_GMAC_DBG_TPESTS_E_DISD | 0x0 | Idle State
3611  * ALT_EMAC_GMAC_DBG_TPESTS_E_END | 0x1 | Actively Transmitting Data
3612  *
3613  * Field Access Macros:
3614  *
3615  */
3616 /*
3617  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
3618  *
3619  * Idle State
3620  */
3621 #define ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0
3622 /*
3623  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
3624  *
3625  * Actively Transmitting Data
3626  */
3627 #define ALT_EMAC_GMAC_DBG_TPESTS_E_END 0x1
3628 
3629 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
3630 #define ALT_EMAC_GMAC_DBG_TPESTS_LSB 16
3631 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
3632 #define ALT_EMAC_GMAC_DBG_TPESTS_MSB 16
3633 /* The width in bits of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
3634 #define ALT_EMAC_GMAC_DBG_TPESTS_WIDTH 1
3635 /* The mask used to set the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
3636 #define ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK 0x00010000
3637 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
3638 #define ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK 0xfffeffff
3639 /* The reset value of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
3640 #define ALT_EMAC_GMAC_DBG_TPESTS_RESET 0x0
3641 /* Extracts the ALT_EMAC_GMAC_DBG_TPESTS field value from a register. */
3642 #define ALT_EMAC_GMAC_DBG_TPESTS_GET(value) (((value) & 0x00010000) >> 16)
3643 /* Produces a ALT_EMAC_GMAC_DBG_TPESTS register field value suitable for setting the register. */
3644 #define ALT_EMAC_GMAC_DBG_TPESTS_SET(value) (((value) << 16) & 0x00010000)
3645 
3646 /*
3647  * Field : MAC Transmit Frame Controller Status - tfcsts
3648  *
3649  * This field indicates the state of the MAC Transmit Frame Controller block
3650  *
3651  * Field Enumeration Values:
3652  *
3653  * Enum | Value | Description
3654  * :-----------------------------------|:------|:---------------------------
3655  * ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE | 0x0 | Idle State
3656  * ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG | 0x1 | Waiting Prev. State or IFG
3657  * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE | 0x2 | Generating Tx Pause
3658  * ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM | 0x3 | Tx Input Frame
3659  *
3660  * Field Access Macros:
3661  *
3662  */
3663 /*
3664  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
3665  *
3666  * Idle State
3667  */
3668 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE 0x0
3669 /*
3670  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
3671  *
3672  * Waiting Prev. State or IFG
3673  */
3674 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG 0x1
3675 /*
3676  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
3677  *
3678  * Generating Tx Pause
3679  */
3680 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE 0x2
3681 /*
3682  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
3683  *
3684  * Tx Input Frame
3685  */
3686 #define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM 0x3
3687 
3688 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
3689 #define ALT_EMAC_GMAC_DBG_TFCSTS_LSB 17
3690 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
3691 #define ALT_EMAC_GMAC_DBG_TFCSTS_MSB 18
3692 /* The width in bits of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
3693 #define ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH 2
3694 /* The mask used to set the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
3695 #define ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK 0x00060000
3696 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
3697 #define ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK 0xfff9ffff
3698 /* The reset value of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
3699 #define ALT_EMAC_GMAC_DBG_TFCSTS_RESET 0x0
3700 /* Extracts the ALT_EMAC_GMAC_DBG_TFCSTS field value from a register. */
3701 #define ALT_EMAC_GMAC_DBG_TFCSTS_GET(value) (((value) & 0x00060000) >> 17)
3702 /* Produces a ALT_EMAC_GMAC_DBG_TFCSTS register field value suitable for setting the register. */
3703 #define ALT_EMAC_GMAC_DBG_TFCSTS_SET(value) (((value) << 17) & 0x00060000)
3704 
3705 /*
3706  * Field : MAC transmitter in PAUSE - txpaused
3707  *
3708  * When high, this bit indicates that the MAC transmitter is in the PAUSE condition
3709  * (in the full-duplex only mode) and hence does not schedule any frame for
3710  * transmission.
3711  *
3712  * Field Enumeration Values:
3713  *
3714  * Enum | Value | Description
3715  * :---------------------------------|:------|:--------------------------------
3716  * ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS | 0x0 | MAC Transmitter Pause Disabled
3717  * ALT_EMAC_GMAC_DBG_TXPAUSED_E_END | 0x1 | MAC Transmitter Pause Condition
3718  *
3719  * Field Access Macros:
3720  *
3721  */
3722 /*
3723  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
3724  *
3725  * MAC Transmitter Pause Disabled
3726  */
3727 #define ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS 0x0
3728 /*
3729  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
3730  *
3731  * MAC Transmitter Pause Condition
3732  */
3733 #define ALT_EMAC_GMAC_DBG_TXPAUSED_E_END 0x1
3734 
3735 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
3736 #define ALT_EMAC_GMAC_DBG_TXPAUSED_LSB 19
3737 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
3738 #define ALT_EMAC_GMAC_DBG_TXPAUSED_MSB 19
3739 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
3740 #define ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH 1
3741 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
3742 #define ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK 0x00080000
3743 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
3744 #define ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK 0xfff7ffff
3745 /* The reset value of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
3746 #define ALT_EMAC_GMAC_DBG_TXPAUSED_RESET 0x0
3747 /* Extracts the ALT_EMAC_GMAC_DBG_TXPAUSED field value from a register. */
3748 #define ALT_EMAC_GMAC_DBG_TXPAUSED_GET(value) (((value) & 0x00080000) >> 19)
3749 /* Produces a ALT_EMAC_GMAC_DBG_TXPAUSED register field value suitable for setting the register. */
3750 #define ALT_EMAC_GMAC_DBG_TXPAUSED_SET(value) (((value) << 19) & 0x00080000)
3751 
3752 /*
3753  * Field : MTL Tx FIFO Read Controller Status - trcsts
3754  *
3755  * This field indicates the state of the Tx FIFO Read Controller
3756  *
3757  * Field Enumeration Values:
3758  *
3759  * Enum | Value | Description
3760  * :--------------------------------------|:------|:-------------------------------------------------
3761  * ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE | 0x0 | Idle State
3762  * ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE | 0x1 | Read State (transferring data to the MAC
3763  * : | | transmitter)
3764  * ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT | 0x2 | Waiting for TxStatus from the MAC transmitter
3765  * ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT | 0x3 | Writing the received TxStatus or flushing the Tx
3766  * : | | FIFO
3767  *
3768  * Field Access Macros:
3769  *
3770  */
3771 /*
3772  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
3773  *
3774  * Idle State
3775  */
3776 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE 0x0
3777 /*
3778  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
3779  *
3780  * Read State (transferring data to the MAC transmitter)
3781  */
3782 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE 0x1
3783 /*
3784  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
3785  *
3786  * Waiting for TxStatus from the MAC transmitter
3787  */
3788 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT 0x2
3789 /*
3790  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
3791  *
3792  * Writing the received TxStatus or flushing the Tx FIFO
3793  */
3794 #define ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT 0x3
3795 
3796 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
3797 #define ALT_EMAC_GMAC_DBG_TRCSTS_LSB 20
3798 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
3799 #define ALT_EMAC_GMAC_DBG_TRCSTS_MSB 21
3800 /* The width in bits of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
3801 #define ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH 2
3802 /* The mask used to set the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
3803 #define ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK 0x00300000
3804 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
3805 #define ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK 0xffcfffff
3806 /* The reset value of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
3807 #define ALT_EMAC_GMAC_DBG_TRCSTS_RESET 0x0
3808 /* Extracts the ALT_EMAC_GMAC_DBG_TRCSTS field value from a register. */
3809 #define ALT_EMAC_GMAC_DBG_TRCSTS_GET(value) (((value) & 0x00300000) >> 20)
3810 /* Produces a ALT_EMAC_GMAC_DBG_TRCSTS register field value suitable for setting the register. */
3811 #define ALT_EMAC_GMAC_DBG_TRCSTS_SET(value) (((value) << 20) & 0x00300000)
3812 
3813 /*
3814  * Field : MTL Tx FIFO Write Controller Active Status - twcsts
3815  *
3816  * When high, this bit indicates that the MTL Tx FIFO Write Controller is active
3817  * and transferring data to the Tx FIFO.
3818  *
3819  * Field Enumeration Values:
3820  *
3821  * Enum | Value | Description
3822  * :---------------------------------|:------|:----------------------------
3823  * ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT | 0x0 | Tx FIFO Write Ctrl Inactive
3824  * ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT | 0x1 | Tx FIFO Write Ctrl Active
3825  *
3826  * Field Access Macros:
3827  *
3828  */
3829 /*
3830  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
3831  *
3832  * Tx FIFO Write Ctrl Inactive
3833  */
3834 #define ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT 0x0
3835 /*
3836  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
3837  *
3838  * Tx FIFO Write Ctrl Active
3839  */
3840 #define ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT 0x1
3841 
3842 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
3843 #define ALT_EMAC_GMAC_DBG_TWCSTS_LSB 22
3844 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
3845 #define ALT_EMAC_GMAC_DBG_TWCSTS_MSB 22
3846 /* The width in bits of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
3847 #define ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH 1
3848 /* The mask used to set the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
3849 #define ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK 0x00400000
3850 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
3851 #define ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK 0xffbfffff
3852 /* The reset value of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
3853 #define ALT_EMAC_GMAC_DBG_TWCSTS_RESET 0x0
3854 /* Extracts the ALT_EMAC_GMAC_DBG_TWCSTS field value from a register. */
3855 #define ALT_EMAC_GMAC_DBG_TWCSTS_GET(value) (((value) & 0x00400000) >> 22)
3856 /* Produces a ALT_EMAC_GMAC_DBG_TWCSTS register field value suitable for setting the register. */
3857 #define ALT_EMAC_GMAC_DBG_TWCSTS_SET(value) (((value) << 22) & 0x00400000)
3858 
3859 /*
3860  * Field : MTL Tx FIFO Not Empty Status - txfsts
3861  *
3862  * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is
3863  * left for transmission.
3864  *
3865  * Field Enumeration Values:
3866  *
3867  * Enum | Value | Description
3868  * :---------------------------------|:------|:----------------------
3869  * ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT | 0x0 | MTL Tx FIFO Empty
3870  * ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT | 0x1 | MTL Tx FIFO Not Empty
3871  *
3872  * Field Access Macros:
3873  *
3874  */
3875 /*
3876  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
3877  *
3878  * MTL Tx FIFO Empty
3879  */
3880 #define ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT 0x0
3881 /*
3882  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
3883  *
3884  * MTL Tx FIFO Not Empty
3885  */
3886 #define ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT 0x1
3887 
3888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
3889 #define ALT_EMAC_GMAC_DBG_TXFSTS_LSB 24
3890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
3891 #define ALT_EMAC_GMAC_DBG_TXFSTS_MSB 24
3892 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
3893 #define ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH 1
3894 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
3895 #define ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK 0x01000000
3896 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
3897 #define ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK 0xfeffffff
3898 /* The reset value of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
3899 #define ALT_EMAC_GMAC_DBG_TXFSTS_RESET 0x0
3900 /* Extracts the ALT_EMAC_GMAC_DBG_TXFSTS field value from a register. */
3901 #define ALT_EMAC_GMAC_DBG_TXFSTS_GET(value) (((value) & 0x01000000) >> 24)
3902 /* Produces a ALT_EMAC_GMAC_DBG_TXFSTS register field value suitable for setting the register. */
3903 #define ALT_EMAC_GMAC_DBG_TXFSTS_SET(value) (((value) << 24) & 0x01000000)
3904 
3905 /*
3906  * Field : MTL TxStatus FIFO Full Status - txstsfsts
3907  *
3908  * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the
3909  * MTL cannot accept any more frames for transmission.
3910  *
3911  * Field Enumeration Values:
3912  *
3913  * Enum | Value | Description
3914  * :------------------------------------|:------|:----------------------------------
3915  * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT | 0x0 | MTL TxStatus FIFO Not Full Status
3916  * ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT | 0x1 | MTL TxStatus FIFO Full Status
3917  *
3918  * Field Access Macros:
3919  *
3920  */
3921 /*
3922  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
3923  *
3924  * MTL TxStatus FIFO Not Full Status
3925  */
3926 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0
3927 /*
3928  * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
3929  *
3930  * MTL TxStatus FIFO Full Status
3931  */
3932 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT 0x1
3933 
3934 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
3935 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB 25
3936 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
3937 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB 25
3938 /* The width in bits of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
3939 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH 1
3940 /* The mask used to set the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
3941 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK 0x02000000
3942 /* The mask used to clear the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
3943 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK 0xfdffffff
3944 /* The reset value of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
3945 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET 0x0
3946 /* Extracts the ALT_EMAC_GMAC_DBG_TXSTSFSTS field value from a register. */
3947 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET(value) (((value) & 0x02000000) >> 25)
3948 /* Produces a ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value suitable for setting the register. */
3949 #define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET(value) (((value) << 25) & 0x02000000)
3950 
3951 #ifndef __ASSEMBLY__
3952 /*
3953  * WARNING: The C register and register group struct declarations are provided for
3954  * convenience and illustrative purposes. They should, however, be used with
3955  * caution as the C language standard provides no guarantees about the alignment or
3956  * atomicity of device memory accesses. The recommended practice for writing
3957  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3958  * alt_write_word() functions.
3959  *
3960  * The struct declaration for register ALT_EMAC_GMAC_DBG.
3961  */
3962 struct ALT_EMAC_GMAC_DBG_s
3963 {
3964  const uint32_t rpests : 1; /* MAC GMII or MII Receive Protocol Engine Status */
3965  const uint32_t rfcfcsts : 2; /* MAC Receive Frame Controller FIFO Status */
3966  uint32_t : 1; /* *UNDEFINED* */
3967  const uint32_t rwcsts : 1; /* MTL Rx FIFO Write Controller Active Status */
3968  const uint32_t rrcsts : 2; /* MTL Rx FIFO Read Controller State */
3969  uint32_t : 1; /* *UNDEFINED* */
3970  const uint32_t rxfsts : 2; /* MTL Rx FIFO Fill-level Status */
3971  uint32_t : 6; /* *UNDEFINED* */
3972  const uint32_t tpests : 1; /* MAC GMII or MII Transmit Protocol Engine Status */
3973  const uint32_t tfcsts : 2; /* MAC Transmit Frame Controller Status */
3974  const uint32_t txpaused : 1; /* MAC transmitter in PAUSE */
3975  const uint32_t trcsts : 2; /* MTL Tx FIFO Read Controller Status */
3976  const uint32_t twcsts : 1; /* MTL Tx FIFO Write Controller Active Status */
3977  uint32_t : 1; /* *UNDEFINED* */
3978  const uint32_t txfsts : 1; /* MTL Tx FIFO Not Empty Status */
3979  const uint32_t txstsfsts : 1; /* MTL TxStatus FIFO Full Status */
3980  uint32_t : 6; /* *UNDEFINED* */
3981 };
3982 
3983 /* The typedef declaration for register ALT_EMAC_GMAC_DBG. */
3984 typedef volatile struct ALT_EMAC_GMAC_DBG_s ALT_EMAC_GMAC_DBG_t;
3985 #endif /* __ASSEMBLY__ */
3986 
3987 /* The byte offset of the ALT_EMAC_GMAC_DBG register from the beginning of the component. */
3988 #define ALT_EMAC_GMAC_DBG_OFST 0x24
3989 /* The address of the ALT_EMAC_GMAC_DBG register. */
3990 #define ALT_EMAC_GMAC_DBG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST))
3991 
3992 /*
3993  * Register : Register 12 (LPI Control and Status Register) - LPI_Control_Status
3994  *
3995  * The LPI Control and Status Register controls the LPI functions and provides the
3996  * LPI interrupt status. The status bits are cleared when this register is read.
3997  *
3998  * Register Layout
3999  *
4000  * Bits | Access | Reset | Description
4001  * :--------|:-------|:------|:-----------------------
4002  * [0] | R | 0x0 | Transmit LPI Entry
4003  * [1] | R | 0x0 | Transmit LPI Exit
4004  * [2] | R | 0x0 | Receive LPI Entry
4005  * [3] | R | 0x0 | Receive LPI Exit
4006  * [7:4] | ??? | 0x0 | *UNDEFINED*
4007  * [8] | R | 0x0 | Transmit LPI State
4008  * [9] | R | 0x0 | Receive LPI State
4009  * [15:10] | ??? | 0x0 | *UNDEFINED*
4010  * [16] | RW | 0x0 | LPI Enable
4011  * [17] | RW | 0x0 | PHY Link Status
4012  * [18] | RW | 0x0 | PHY Link Status Enable
4013  * [19] | RW | 0x0 | LPI TX Automate
4014  * [31:20] | ??? | 0x0 | *UNDEFINED*
4015  *
4016  */
4017 /*
4018  * Field : Transmit LPI Entry - tlpien
4019  *
4020  * When set, this bit indicates that the MAC Transmitter has entered the LPI state
4021  * because of the setting of the LPIEN bit. This bit is cleared by a read into this
4022  * register.
4023  *
4024  * Field Enumeration Values:
4025  *
4026  * Enum | Value | Description
4027  * :------------------------------------------|:------|:----------------------------------
4028  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT | 0x0 | MAC Transmitter Not in LPI State
4029  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT | 0x1 | MAC Transmitter Entered LPI State
4030  *
4031  * Field Access Macros:
4032  *
4033  */
4034 /*
4035  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
4036  *
4037  * MAC Transmitter Not in LPI State
4038  */
4039 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0
4040 /*
4041  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
4042  *
4043  * MAC Transmitter Entered LPI State
4044  */
4045 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1
4046 
4047 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4048 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB 0
4049 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4050 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB 0
4051 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4052 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH 1
4053 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
4054 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK 0x00000001
4055 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
4056 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK 0xfffffffe
4057 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
4058 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET 0x0
4059 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register. */
4060 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value) (((value) & 0x00000001) >> 0)
4061 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register. */
4062 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value) (((value) << 0) & 0x00000001)
4063 
4064 /*
4065  * Field : Transmit LPI Exit - tlpiex
4066  *
4067  * When set, this bit indicates that the MAC transmitter has exited the LPI state
4068  * after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This
4069  * bit is cleared by a read into this register.
4070  *
4071  * Field Enumeration Values:
4072  *
4073  * Enum | Value | Description
4074  * :------------------------------------------|:------|:---------------------------------
4075  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT | 0x0 | MAC Transmitter Non LPI State
4076  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT | 0x1 | MAC Transmitter Exited LPI State
4077  *
4078  * Field Access Macros:
4079  *
4080  */
4081 /*
4082  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
4083  *
4084  * MAC Transmitter Non LPI State
4085  */
4086 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0
4087 /*
4088  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
4089  *
4090  * MAC Transmitter Exited LPI State
4091  */
4092 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1
4093 
4094 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4095 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB 1
4096 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4097 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB 1
4098 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4099 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH 1
4100 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
4101 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK 0x00000002
4102 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
4103 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK 0xfffffffd
4104 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
4105 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET 0x0
4106 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register. */
4107 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value) (((value) & 0x00000002) >> 1)
4108 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register. */
4109 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value) (((value) << 1) & 0x00000002)
4110 
4111 /*
4112  * Field : Receive LPI Entry - rlpien
4113  *
4114  * When set, this bit indicates that the MAC Receiver has received an LPI pattern
4115  * and entered the LPI state. This bit is cleared by a read into this register.
4116  *
4117  * Note:
4118  *
4119  * This bit may not get set if the MAC stops receiving the LPI pattern for a very
4120  * short duration, such as, less than 3 clock cycles of l3_sp_clk.
4121  *
4122  * Field Enumeration Values:
4123  *
4124  * Enum | Value | Description
4125  * :------------------------------------------|:------|:------------------------------
4126  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT | 0x0 | MAC Receiver Not In LPI State
4127  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT | 0x1 | MAC Receiver In LPI State
4128  *
4129  * Field Access Macros:
4130  *
4131  */
4132 /*
4133  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
4134  *
4135  * MAC Receiver Not In LPI State
4136  */
4137 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0
4138 /*
4139  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
4140  *
4141  * MAC Receiver In LPI State
4142  */
4143 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1
4144 
4145 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4146 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB 2
4147 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4148 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB 2
4149 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4150 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH 1
4151 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
4152 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK 0x00000004
4153 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
4154 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK 0xfffffffb
4155 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
4156 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET 0x0
4157 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register. */
4158 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value) (((value) & 0x00000004) >> 2)
4159 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register. */
4160 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value) (((value) << 2) & 0x00000004)
4161 
4162 /*
4163  * Field : Receive LPI Exit - rlpiex
4164  *
4165  * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI
4166  * pattern on the GMII or MII interface, exited the LPI state, and resumed the
4167  * normal reception. This bit is cleared by a read into this register.
4168  *
4169  * Note:
4170  *
4171  * This bit may not get set if the MAC stops receiving the LPI pattern for a very
4172  * short duration, such as, less than 3 clock cycles of l3_sp_clk.
4173  *
4174  * Field Enumeration Values:
4175  *
4176  * Enum | Value | Description
4177  * :------------------------------------------|:------|:--------------------------------------
4178  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT | 0x0 | MAC RX receiving LPI Patterns
4179  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT | 0x1 | MAC RX Stopped receiving LPI Patterns
4180  *
4181  * Field Access Macros:
4182  *
4183  */
4184 /*
4185  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
4186  *
4187  * MAC RX receiving LPI Patterns
4188  */
4189 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0
4190 /*
4191  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
4192  *
4193  * MAC RX Stopped receiving LPI Patterns
4194  */
4195 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1
4196 
4197 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4198 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB 3
4199 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4200 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB 3
4201 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4202 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH 1
4203 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
4204 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK 0x00000008
4205 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
4206 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK 0xfffffff7
4207 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
4208 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET 0x0
4209 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register. */
4210 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value) (((value) & 0x00000008) >> 3)
4211 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register. */
4212 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value) (((value) << 3) & 0x00000008)
4213 
4214 /*
4215  * Field : Transmit LPI State - tlpist
4216  *
4217  * When set, this bit indicates that the MAC is transmitting the LPI pattern on the
4218  * GMII or MII interface.
4219  *
4220  * Field Enumeration Values:
4221  *
4222  * Enum | Value | Description
4223  * :------------------------------------------|:------|:-----------------------------
4224  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT | 0x0 | MAC Transmitting LPI Pattern
4225  * ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT | 0x1 | MAC Transmitting LPI Pattern
4226  *
4227  * Field Access Macros:
4228  *
4229  */
4230 /*
4231  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
4232  *
4233  * MAC Transmitting LPI Pattern
4234  */
4235 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0
4236 /*
4237  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
4238  *
4239  * MAC Transmitting LPI Pattern
4240  */
4241 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1
4242 
4243 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4244 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB 8
4245 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4246 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB 8
4247 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4248 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH 1
4249 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
4250 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK 0x00000100
4251 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
4252 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK 0xfffffeff
4253 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
4254 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET 0x0
4255 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register. */
4256 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value) (((value) & 0x00000100) >> 8)
4257 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register. */
4258 #define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value) (((value) << 8) & 0x00000100)
4259 
4260 /*
4261  * Field : Receive LPI State - rlpist
4262  *
4263  * When set, this bit indicates that the MAC is receiving the LPI pattern on the
4264  * GMII or MII interface.
4265  *
4266  * Field Enumeration Values:
4267  *
4268  * Enum | Value | Description
4269  * :------------------------------------------|:------|:---------------------------------
4270  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT | 0x0 | MAC is not receiving LPI Pattern
4271  * ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT | 0x1 | MAC receiving LPI Pattern
4272  *
4273  * Field Access Macros:
4274  *
4275  */
4276 /*
4277  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
4278  *
4279  * MAC is not receiving LPI Pattern
4280  */
4281 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0
4282 /*
4283  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
4284  *
4285  * MAC receiving LPI Pattern
4286  */
4287 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1
4288 
4289 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4290 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB 9
4291 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4292 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB 9
4293 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4294 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH 1
4295 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
4296 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK 0x00000200
4297 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
4298 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK 0xfffffdff
4299 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
4300 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET 0x0
4301 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register. */
4302 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value) (((value) & 0x00000200) >> 9)
4303 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register. */
4304 #define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value) (((value) << 9) & 0x00000200)
4305 
4306 /*
4307  * Field : LPI Enable - lpien
4308  *
4309  * When set, this bit instructs the MAC Transmitter to enter the LPI state. When
4310  * reset, this bit instructs the MAC to exit the LPI state and resume normal
4311  * transmission.
4312  *
4313  * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state
4314  * because of the arrival of a new packet for transmission.
4315  *
4316  * Field Enumeration Values:
4317  *
4318  * Enum | Value | Description
4319  * :----------------------------------------|:------|:---------------------------------
4320  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD | 0x0 | MAC Transmitter exit LPI State
4321  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END | 0x1 | MAC Transmitter enters LPI State
4322  *
4323  * Field Access Macros:
4324  *
4325  */
4326 /*
4327  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
4328  *
4329  * MAC Transmitter exit LPI State
4330  */
4331 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0
4332 /*
4333  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
4334  *
4335  * MAC Transmitter enters LPI State
4336  */
4337 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1
4338 
4339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
4340 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB 16
4341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
4342 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB 16
4343 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
4344 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH 1
4345 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
4346 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK 0x00010000
4347 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
4348 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK 0xfffeffff
4349 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
4350 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET 0x0
4351 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register. */
4352 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value) (((value) & 0x00010000) >> 16)
4353 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register. */
4354 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value) (((value) << 16) & 0x00010000)
4355 
4356 /*
4357  * Field : PHY Link Status - pls
4358  *
4359  * This bit indicates the link status of the PHY. The MAC Transmitter asserts the
4360  * LPI pattern only when the link status is up (okay) at least for the time
4361  * indicated by the LPI LS TIMER.
4362  *
4363  * When set, the link is considered to be okay (up) and when reset, the link is
4364  * considered to be down.
4365  *
4366  * Field Enumeration Values:
4367  *
4368  * Enum | Value | Description
4369  * :--------------------------------------|:------|:---------------
4370  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD | 0x0 | Link Down
4371  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END | 0x1 | Link Up (okay)
4372  *
4373  * Field Access Macros:
4374  *
4375  */
4376 /*
4377  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
4378  *
4379  * Link Down
4380  */
4381 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0
4382 /*
4383  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
4384  *
4385  * Link Up (okay)
4386  */
4387 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1
4388 
4389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
4390 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB 17
4391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
4392 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB 17
4393 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
4394 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH 1
4395 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
4396 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK 0x00020000
4397 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
4398 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK 0xfffdffff
4399 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
4400 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET 0x0
4401 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register. */
4402 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value) (((value) & 0x00020000) >> 17)
4403 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register. */
4404 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value) (((value) << 17) & 0x00020000)
4405 
4406 /*
4407  * Field : PHY Link Status Enable - plsen
4408  *
4409  * This bit enables the link status received on the RGMII receive paths to be used
4410  * for activating the LPI LS TIMER.
4411  *
4412  * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII
4413  * Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared,
4414  * the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.
4415  *
4416  * Field Enumeration Values:
4417  *
4418  * Enum | Value | Description
4419  * :----------------------------------------|:------|:-----------------------------
4420  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD | 0x0 | MAC Ignores Link Status Bits
4421  * ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END | 0x1 | MAC Uses Link Status Bits
4422  *
4423  * Field Access Macros:
4424  *
4425  */
4426 /*
4427  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
4428  *
4429  * MAC Ignores Link Status Bits
4430  */
4431 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0
4432 /*
4433  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
4434  *
4435  * MAC Uses Link Status Bits
4436  */
4437 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1
4438 
4439 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
4440 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB 18
4441 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
4442 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB 18
4443 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
4444 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH 1
4445 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
4446 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK 0x00040000
4447 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
4448 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK 0xfffbffff
4449 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
4450 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET 0x0
4451 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register. */
4452 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value) (((value) & 0x00040000) >> 18)
4453 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register. */
4454 #define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value) (((value) << 18) & 0x00040000)
4455 
4456 /*
4457  * Field : LPI TX Automate - lpitxa
4458  *
4459  * This bit controls the behavior of the MAC when it is entering or coming out of
4460  * the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE
4461  * configuration in which the Tx clock gating is done during the LPI mode.
4462  *
4463  * If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only
4464  * after all outstanding frames (in the core) and pending frames (in the
4465  * application interface) have been transmitted. The MAC comes out of the LPI mode
4466  * when the application sends any frame for transmission or the application issues
4467  * a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit
4468  * when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6
4469  * (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the
4470  * LPI mode.
4471  *
4472  * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it
4473  * is entering or coming out of the LPI mode.
4474  *
4475  * Field Enumeration Values:
4476  *
4477  * Enum | Value | Description
4478  * :-----------------------------------------|:------|:-------------------------
4479  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD | 0x0 | LPI TX Automate Disabled
4480  * ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END | 0x1 | LPI TX Automate Enabled
4481  *
4482  * Field Access Macros:
4483  *
4484  */
4485 /*
4486  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
4487  *
4488  * LPI TX Automate Disabled
4489  */
4490 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0
4491 /*
4492  * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
4493  *
4494  * LPI TX Automate Enabled
4495  */
4496 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1
4497 
4498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
4499 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB 19
4500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
4501 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB 19
4502 /* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
4503 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH 1
4504 /* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
4505 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK 0x00080000
4506 /* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
4507 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK 0xfff7ffff
4508 /* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
4509 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET 0x0
4510 /* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register. */
4511 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value) (((value) & 0x00080000) >> 19)
4512 /* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register. */
4513 #define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value) (((value) << 19) & 0x00080000)
4514 
4515 #ifndef __ASSEMBLY__
4516 /*
4517  * WARNING: The C register and register group struct declarations are provided for
4518  * convenience and illustrative purposes. They should, however, be used with
4519  * caution as the C language standard provides no guarantees about the alignment or
4520  * atomicity of device memory accesses. The recommended practice for writing
4521  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4522  * alt_write_word() functions.
4523  *
4524  * The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.
4525  */
4526 struct ALT_EMAC_GMAC_LPI_CTL_STAT_s
4527 {
4528  const uint32_t tlpien : 1; /* Transmit LPI Entry */
4529  const uint32_t tlpiex : 1; /* Transmit LPI Exit */
4530  const uint32_t rlpien : 1; /* Receive LPI Entry */
4531  const uint32_t rlpiex : 1; /* Receive LPI Exit */
4532  uint32_t : 4; /* *UNDEFINED* */
4533  const uint32_t tlpist : 1; /* Transmit LPI State */
4534  const uint32_t rlpist : 1; /* Receive LPI State */
4535  uint32_t : 6; /* *UNDEFINED* */
4536  uint32_t lpien : 1; /* LPI Enable */
4537  uint32_t pls : 1; /* PHY Link Status */
4538  uint32_t plsen : 1; /* PHY Link Status Enable */
4539  uint32_t lpitxa : 1; /* LPI TX Automate */
4540  uint32_t : 12; /* *UNDEFINED* */
4541 };
4542 
4543 /* The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT. */
4544 typedef volatile struct ALT_EMAC_GMAC_LPI_CTL_STAT_s ALT_EMAC_GMAC_LPI_CTL_STAT_t;
4545 #endif /* __ASSEMBLY__ */
4546 
4547 /* The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component. */
4548 #define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST 0x30
4549 /* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register. */
4550 #define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST))
4551 
4552 /*
4553  * Register : Register 13 (LPI Timers Control Register) - LPI_Timers_Control
4554  *
4555  * The LPI Timers Control register controls the timeout values in the LPI states.
4556  * It specifies the time for which the MAC transmits the LPI pattern and also the
4557  * time for which the MAC waits before resuming the normal transmission.
4558  *
4559  * Register Layout
4560  *
4561  * Bits | Access | Reset | Description
4562  * :--------|:-------|:------|:-------------
4563  * [15:0] | RW | 0x0 | LPI TW Timer
4564  * [25:16] | RW | 0x3e8 | LPI LS Timer
4565  * [31:26] | ??? | 0x0 | *UNDEFINED*
4566  *
4567  */
4568 /*
4569  * Field : LPI TW Timer - twt
4570  *
4571  * This field specifies the minimum time (in microseconds) for which the MAC waits
4572  * after it stops transmitting the LPI pattern to the PHY and before it resumes the
4573  * normal transmission. The TLPIEX status bit is set after the expiry of this
4574  * timer.
4575  *
4576  * Field Access Macros:
4577  *
4578  */
4579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
4580 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB 0
4581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
4582 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB 15
4583 /* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
4584 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH 16
4585 /* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
4586 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK 0x0000ffff
4587 /* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
4588 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK 0xffff0000
4589 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
4590 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET 0x0
4591 /* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT field value from a register. */
4592 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET(value) (((value) & 0x0000ffff) >> 0)
4593 /* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value suitable for setting the register. */
4594 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET(value) (((value) << 0) & 0x0000ffff)
4595 
4596 /*
4597  * Field : LPI LS Timer - lst
4598  *
4599  * This field specifies the minimum time (in milliseconds) for which the link
4600  * status from the PHY should be up (OKAY) before the LPI pattern can be
4601  * transmitted to the PHY. The MAC does not transmit the LPI pattern even when the
4602  * LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count.
4603  * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE
4604  * standard.
4605  *
4606  * Field Access Macros:
4607  *
4608  */
4609 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
4610 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB 16
4611 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
4612 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB 25
4613 /* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
4614 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH 10
4615 /* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
4616 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK 0x03ff0000
4617 /* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
4618 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK 0xfc00ffff
4619 /* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
4620 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET 0x3e8
4621 /* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST field value from a register. */
4622 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET(value) (((value) & 0x03ff0000) >> 16)
4623 /* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value suitable for setting the register. */
4624 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET(value) (((value) << 16) & 0x03ff0000)
4625 
4626 #ifndef __ASSEMBLY__
4627 /*
4628  * WARNING: The C register and register group struct declarations are provided for
4629  * convenience and illustrative purposes. They should, however, be used with
4630  * caution as the C language standard provides no guarantees about the alignment or
4631  * atomicity of device memory accesses. The recommended practice for writing
4632  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4633  * alt_write_word() functions.
4634  *
4635  * The struct declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL.
4636  */
4637 struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s
4638 {
4639  uint32_t twt : 16; /* LPI TW Timer */
4640  uint32_t lst : 10; /* LPI LS Timer */
4641  uint32_t : 6; /* *UNDEFINED* */
4642 };
4643 
4644 /* The typedef declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL. */
4645 typedef volatile struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s ALT_EMAC_GMAC_LPI_TMRS_CTL_t;
4646 #endif /* __ASSEMBLY__ */
4647 
4648 /* The byte offset of the ALT_EMAC_GMAC_LPI_TMRS_CTL register from the beginning of the component. */
4649 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST 0x34
4650 /* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register. */
4651 #define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST))
4652 
4653 /*
4654  * Register : Register 14 (Interrupt Register) - Interrupt_Status
4655  *
4656  * The Interrupt Status register identifies the events in the MAC that can generate
4657  * interrupt. All interrupt events are generated only when the corresponding
4658  * optional feature is enabled.
4659  *
4660  * Register Layout
4661  *
4662  * Bits | Access | Reset | Description
4663  * :--------|:-------|:------|:----------------------------------------------
4664  * [0] | R | 0x0 | RGMII or SMII Interrupt Status
4665  * [1] | R | 0x0 | PCS Link Status Changed
4666  * [2] | R | 0x0 | PCS Auto-Negotiation Complete
4667  * [3] | ??? | 0x0 | *UNDEFINED*
4668  * [4] | R | 0x0 | MMC Interrupt Status
4669  * [5] | R | 0x0 | MMC Receive Interrupt Status
4670  * [6] | R | 0x0 | MMC Transmit Interrupt Status
4671  * [7] | R | 0x0 | MMC Receive Checksum Offload Interrupt Status
4672  * [8] | ??? | 0x0 | *UNDEFINED*
4673  * [9] | R | 0x0 | Timestamp Interrupt Status
4674  * [10] | R | 0x0 | LPI Interrupt Status
4675  * [31:11] | ??? | 0x0 | *UNDEFINED*
4676  *
4677  */
4678 /*
4679  * Field : RGMII or SMII Interrupt Status - rgsmiiis
4680  *
4681  * This bit is set because of any change in value of the Link Status of RGMII or
4682  * SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This
4683  * bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status
4684  * Register.
4685  *
4686  * Field Enumeration Values:
4687  *
4688  * Enum | Value | Description
4689  * :----------------------------------------|:------|:---------------
4690  * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT | 0x0 | Link No Change
4691  * ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT | 0x1 | Link Change
4692  *
4693  * Field Access Macros:
4694  *
4695  */
4696 /*
4697  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
4698  *
4699  * Link No Change
4700  */
4701 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT 0x0
4702 /*
4703  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
4704  *
4705  * Link Change
4706  */
4707 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT 0x1
4708 
4709 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
4710 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB 0
4711 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
4712 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB 0
4713 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
4714 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH 1
4715 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
4716 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK 0x00000001
4717 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
4718 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK 0xfffffffe
4719 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
4720 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET 0x0
4721 /* Extracts the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS field value from a register. */
4722 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET(value) (((value) & 0x00000001) >> 0)
4723 /* Produces a ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value suitable for setting the register. */
4724 #define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET(value) (((value) << 0) & 0x00000001)
4725 
4726 /*
4727  * Field : PCS Link Status Changed - pcslchgis
4728  *
4729  * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII
4730  * PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared
4731  * when you perform a read operation on the AN Status register.
4732  *
4733  * This bit is valid only when you select the SGMII PHY interface during operation.
4734  *
4735  * Field Access Macros:
4736  *
4737  */
4738 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
4739 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB 1
4740 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
4741 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB 1
4742 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
4743 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH 1
4744 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
4745 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK 0x00000002
4746 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
4747 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK 0xfffffffd
4748 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
4749 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET 0x0
4750 /* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS field value from a register. */
4751 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET(value) (((value) & 0x00000002) >> 1)
4752 /* Produces a ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value suitable for setting the register. */
4753 #define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET(value) (((value) << 1) & 0x00000002)
4754 
4755 /*
4756  * Field : PCS Auto-Negotiation Complete - pcsancis
4757  *
4758  * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or
4759  * SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is
4760  * cleared when you perform a read operation to the AN Status register.
4761  *
4762  * This bit is valid only when you select the SGMII PHY interface during operation.
4763  *
4764  * Field Access Macros:
4765  *
4766  */
4767 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
4768 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB 2
4769 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
4770 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB 2
4771 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
4772 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH 1
4773 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
4774 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK 0x00000004
4775 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
4776 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK 0xfffffffb
4777 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
4778 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET 0x0
4779 /* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSANCIS field value from a register. */
4780 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET(value) (((value) & 0x00000004) >> 2)
4781 /* Produces a ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value suitable for setting the register. */
4782 #define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET(value) (((value) << 2) & 0x00000004)
4783 
4784 /*
4785  * Field : MMC Interrupt Status - mmcis
4786  *
4787  * This bit is set high when any of the Bits [7:5] is set high and cleared only
4788  * when all of these bits are low.
4789  *
4790  * Field Enumeration Values:
4791  *
4792  * Enum | Value | Description
4793  * :-------------------------------------|:------|:------------------------------
4794  * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT | 0x0 | MMC Interrupt Status Disabled
4795  * ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT | 0x1 | MMC Interrupt Status Enabled
4796  *
4797  * Field Access Macros:
4798  *
4799  */
4800 /*
4801  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
4802  *
4803  * MMC Interrupt Status Disabled
4804  */
4805 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT 0x0
4806 /*
4807  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
4808  *
4809  * MMC Interrupt Status Enabled
4810  */
4811 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT 0x1
4812 
4813 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
4814 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB 4
4815 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
4816 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB 4
4817 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
4818 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH 1
4819 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
4820 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK 0x00000010
4821 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
4822 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK 0xffffffef
4823 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
4824 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET 0x0
4825 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCIS field value from a register. */
4826 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET(value) (((value) & 0x00000010) >> 4)
4827 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCIS register field value suitable for setting the register. */
4828 #define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET(value) (((value) << 4) & 0x00000010)
4829 
4830 /*
4831  * Field : MMC Receive Interrupt Status - mmcrxis
4832  *
4833  * This bit is set high when an interrupt is generated in the MMC Receive Interrupt
4834  * Register. This bit is cleared when all the bits in this interrupt register are
4835  * cleared.
4836  *
4837  * Field Enumeration Values:
4838  *
4839  * Enum | Value | Description
4840  * :--------------------------------------|:------|:--------------------------------------
4841  * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD | 0x0 | MMC Receive Interrupt Status Disabled
4842  * ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END | 0x1 | MMC Receive Interrupt Status Enabled
4843  *
4844  * Field Access Macros:
4845  *
4846  */
4847 /*
4848  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
4849  *
4850  * MMC Receive Interrupt Status Disabled
4851  */
4852 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD 0x0
4853 /*
4854  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
4855  *
4856  * MMC Receive Interrupt Status Enabled
4857  */
4858 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END 0x1
4859 
4860 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
4861 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB 5
4862 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
4863 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB 5
4864 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
4865 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH 1
4866 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
4867 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK 0x00000020
4868 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
4869 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK 0xffffffdf
4870 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
4871 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET 0x0
4872 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIS field value from a register. */
4873 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET(value) (((value) & 0x00000020) >> 5)
4874 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value suitable for setting the register. */
4875 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET(value) (((value) << 5) & 0x00000020)
4876 
4877 /*
4878  * Field : MMC Transmit Interrupt Status - mmctxis
4879  *
4880  * This bit is set high when an interrupt is generated in the MMC Transmit
4881  * Interrupt Register. This bit is cleared when all the bits in this interrupt
4882  * register are cleared.
4883  *
4884  * Field Enumeration Values:
4885  *
4886  * Enum | Value | Description
4887  * :---------------------------------------|:------|:---------------------------------------
4888  * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT | 0x0 | MMC Transmit Interrupt Status Disabled
4889  * ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT | 0x1 | MMC Transmit Interrupt Status Enabled
4890  *
4891  * Field Access Macros:
4892  *
4893  */
4894 /*
4895  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
4896  *
4897  * MMC Transmit Interrupt Status Disabled
4898  */
4899 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT 0x0
4900 /*
4901  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
4902  *
4903  * MMC Transmit Interrupt Status Enabled
4904  */
4905 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT 0x1
4906 
4907 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
4908 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB 6
4909 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
4910 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB 6
4911 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
4912 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH 1
4913 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
4914 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK 0x00000040
4915 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
4916 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK 0xffffffbf
4917 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
4918 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET 0x0
4919 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCTXIS field value from a register. */
4920 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET(value) (((value) & 0x00000040) >> 6)
4921 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value suitable for setting the register. */
4922 #define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET(value) (((value) << 6) & 0x00000040)
4923 
4924 /*
4925  * Field : MMC Receive Checksum Offload Interrupt Status - mmcrxipis
4926  *
4927  * This bit is set high when an interrupt is generated in the MMC Receive Checksum
4928  * Offload Interrupt Register. This bit is cleared when all the bits in this
4929  * interrupt register are cleared.
4930  *
4931  * Field Enumeration Values:
4932  *
4933  * Enum | Value | Description
4934  * :-----------------------------------------|:------|:----------------------------------------------
4935  * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT | 0x0 | MMC Receive Checksum Offload Interrupt Status
4936  * : | | Disabled
4937  * ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT | 0x1 | MMC Receive Checksum Offload Interrupt Status
4938  * : | | Enabled
4939  *
4940  * Field Access Macros:
4941  *
4942  */
4943 /*
4944  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
4945  *
4946  * MMC Receive Checksum Offload Interrupt Status Disabled
4947  */
4948 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT 0x0
4949 /*
4950  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
4951  *
4952  * MMC Receive Checksum Offload Interrupt Status Enabled
4953  */
4954 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT 0x1
4955 
4956 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
4957 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB 7
4958 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
4959 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB 7
4960 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
4961 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH 1
4962 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
4963 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK 0x00000080
4964 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
4965 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK 0xffffff7f
4966 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
4967 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET 0x0
4968 /* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS field value from a register. */
4969 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET(value) (((value) & 0x00000080) >> 7)
4970 /* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value suitable for setting the register. */
4971 #define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET(value) (((value) << 7) & 0x00000080)
4972 
4973 /*
4974  * Field : Timestamp Interrupt Status - tsis
4975  *
4976  * This bit is set when any of the following conditions is true:
4977  *
4978  * * The system time value equals or exceeds the value specified in the Target Time
4979  * High and Low registers.
4980  *
4981  * * There is an overflow in the seconds register.
4982  *
4983  * * The Auxiliary snapshot trigger is asserted.
4984  *
4985  * This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status
4986  * Register).
4987  *
4988  * When set, this bit indicates that the system time value is equal to or exceeds
4989  * the value specified in the Target Time registers. In this mode, this bit is
4990  * cleared after the completion of the read of this bit. In all other modes, this
4991  * bit is reserved.
4992  *
4993  * Field Enumeration Values:
4994  *
4995  * Enum | Value | Description
4996  * :------------------------------------|:------|:------------------------------------
4997  * ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT | 0x0 | Timestamp Interrupt Status Disabled
4998  * ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT | 0x1 | Timestamp Interrupt Status Enabled
4999  *
5000  * Field Access Macros:
5001  *
5002  */
5003 /*
5004  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
5005  *
5006  * Timestamp Interrupt Status Disabled
5007  */
5008 #define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT 0x0
5009 /*
5010  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
5011  *
5012  * Timestamp Interrupt Status Enabled
5013  */
5014 #define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT 0x1
5015 
5016 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5017 #define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB 9
5018 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5019 #define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB 9
5020 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5021 #define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH 1
5022 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
5023 #define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK 0x00000200
5024 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
5025 #define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK 0xfffffdff
5026 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
5027 #define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET 0x0
5028 /* Extracts the ALT_EMAC_GMAC_INT_STAT_TSIS field value from a register. */
5029 #define ALT_EMAC_GMAC_INT_STAT_TSIS_GET(value) (((value) & 0x00000200) >> 9)
5030 /* Produces a ALT_EMAC_GMAC_INT_STAT_TSIS register field value suitable for setting the register. */
5031 #define ALT_EMAC_GMAC_INT_STAT_TSIS_SET(value) (((value) << 9) & 0x00000200)
5032 
5033 /*
5034  * Field : LPI Interrupt Status - lpiis
5035  *
5036  * This bit is set for any LPI state entry or exit in the MAC Transmitter or
5037  * Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and
5038  * Status Register). In all other modes, this bit is reserved.
5039  *
5040  * Field Enumeration Values:
5041  *
5042  * Enum | Value | Description
5043  * :-------------------------------------|:------|:------------------------------
5044  * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT | 0x0 | LPI Interrupt Status Disabled
5045  * ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT | 0x1 | LPI Interrupt Status Enabled
5046  *
5047  * Field Access Macros:
5048  *
5049  */
5050 /*
5051  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
5052  *
5053  * LPI Interrupt Status Disabled
5054  */
5055 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT 0x0
5056 /*
5057  * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
5058  *
5059  * LPI Interrupt Status Enabled
5060  */
5061 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT 0x1
5062 
5063 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5064 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB 10
5065 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5066 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB 10
5067 /* The width in bits of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5068 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH 1
5069 /* The mask used to set the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
5070 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK 0x00000400
5071 /* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
5072 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK 0xfffffbff
5073 /* The reset value of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
5074 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET 0x0
5075 /* Extracts the ALT_EMAC_GMAC_INT_STAT_LPIIS field value from a register. */
5076 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET(value) (((value) & 0x00000400) >> 10)
5077 /* Produces a ALT_EMAC_GMAC_INT_STAT_LPIIS register field value suitable for setting the register. */
5078 #define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET(value) (((value) << 10) & 0x00000400)
5079 
5080 #ifndef __ASSEMBLY__
5081 /*
5082  * WARNING: The C register and register group struct declarations are provided for
5083  * convenience and illustrative purposes. They should, however, be used with
5084  * caution as the C language standard provides no guarantees about the alignment or
5085  * atomicity of device memory accesses. The recommended practice for writing
5086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5087  * alt_write_word() functions.
5088  *
5089  * The struct declaration for register ALT_EMAC_GMAC_INT_STAT.
5090  */
5091 struct ALT_EMAC_GMAC_INT_STAT_s
5092 {
5093  const uint32_t rgsmiiis : 1; /* RGMII or SMII Interrupt Status */
5094  const uint32_t pcslchgis : 1; /* PCS Link Status Changed */
5095  const uint32_t pcsancis : 1; /* PCS Auto-Negotiation Complete */
5096  uint32_t : 1; /* *UNDEFINED* */
5097  const uint32_t mmcis : 1; /* MMC Interrupt Status */
5098  const uint32_t mmcrxis : 1; /* MMC Receive Interrupt Status */
5099  const uint32_t mmctxis : 1; /* MMC Transmit Interrupt Status */
5100  const uint32_t mmcrxipis : 1; /* MMC Receive Checksum Offload Interrupt Status */
5101  uint32_t : 1; /* *UNDEFINED* */
5102  const uint32_t tsis : 1; /* Timestamp Interrupt Status */
5103  const uint32_t lpiis : 1; /* LPI Interrupt Status */
5104  uint32_t : 21; /* *UNDEFINED* */
5105 };
5106 
5107 /* The typedef declaration for register ALT_EMAC_GMAC_INT_STAT. */
5108 typedef volatile struct ALT_EMAC_GMAC_INT_STAT_s ALT_EMAC_GMAC_INT_STAT_t;
5109 #endif /* __ASSEMBLY__ */
5110 
5111 /* The byte offset of the ALT_EMAC_GMAC_INT_STAT register from the beginning of the component. */
5112 #define ALT_EMAC_GMAC_INT_STAT_OFST 0x38
5113 /* The address of the ALT_EMAC_GMAC_INT_STAT register. */
5114 #define ALT_EMAC_GMAC_INT_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST))
5115 
5116 /*
5117  * Register : Register 15 (Interrupt Mask Register) - Interrupt_Mask
5118  *
5119  * The Interrupt Mask Register bits enable you to mask the interrupt signal because
5120  * of the corresponding event in the Interrupt Status Register. The interrupt
5121  * signal is sbd_intr_o.
5122  *
5123  * Register Layout
5124  *
5125  * Bits | Access | Reset | Description
5126  * :--------|:-------|:------|:---------------------------------
5127  * [0] | RW | 0x0 | RGMII or SMII Interrupt Mask
5128  * [1] | R | 0x0 | PCS Link Status Interrupt Mask
5129  * [2] | R | 0x0 | PCS AN Completion Interrupt Mask
5130  * [8:3] | ??? | 0x0 | *UNDEFINED*
5131  * [9] | RW | 0x0 | Timestamp Interrupt Mask
5132  * [10] | RW | 0x0 | LPI Interrupt Mask
5133  * [31:11] | ??? | 0x0 | *UNDEFINED*
5134  *
5135  */
5136 /*
5137  * Field : RGMII or SMII Interrupt Mask - rgsmiiim
5138  *
5139  * When set, this bit disables the assertion of the interrupt signal because of the
5140  * setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt
5141  * Status Register).
5142  *
5143  * Field Enumeration Values:
5144  *
5145  * Enum | Value | Description
5146  * :--------------------------------------|:------|:-------------------------------------
5147  * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD | 0x0 | RGMII or SMII Interrupt Mask Disable
5148  * ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END | 0x1 | RGMII or SMII Interrupt Mask Enable
5149  *
5150  * Field Access Macros:
5151  *
5152  */
5153 /*
5154  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
5155  *
5156  * RGMII or SMII Interrupt Mask Disable
5157  */
5158 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD 0x0
5159 /*
5160  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
5161  *
5162  * RGMII or SMII Interrupt Mask Enable
5163  */
5164 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END 0x1
5165 
5166 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
5167 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB 0
5168 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
5169 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB 0
5170 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
5171 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH 1
5172 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
5173 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK 0x00000001
5174 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
5175 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK 0xfffffffe
5176 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
5177 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET 0x0
5178 /* Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register. */
5179 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value) (((value) & 0x00000001) >> 0)
5180 /* Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register. */
5181 #define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value) (((value) << 0) & 0x00000001)
5182 
5183 /*
5184  * Field : PCS Link Status Interrupt Mask - pcslchgim
5185  *
5186  * When set, this bit disables the assertion of the interrupt signal because of the
5187  * setting of the PCS Link-status changed bit in Register 14 (Interrupt Status
5188  * Register).
5189  *
5190  * Field Access Macros:
5191  *
5192  */
5193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
5194 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB 1
5195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
5196 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB 1
5197 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
5198 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH 1
5199 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
5200 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK 0x00000002
5201 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
5202 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK 0xfffffffd
5203 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
5204 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET 0x0
5205 /* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register. */
5206 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value) (((value) & 0x00000002) >> 1)
5207 /* Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register. */
5208 #define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value) (((value) << 1) & 0x00000002)
5209 
5210 /*
5211  * Field : PCS AN Completion Interrupt Mask - pcsancim
5212  *
5213  * When set, this bit disables the assertion of the interrupt signal because of the
5214  * setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status
5215  * Register).
5216  *
5217  * Field Access Macros:
5218  *
5219  */
5220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
5221 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB 2
5222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
5223 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB 2
5224 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
5225 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH 1
5226 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
5227 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK 0x00000004
5228 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
5229 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK 0xfffffffb
5230 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
5231 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET 0x0
5232 /* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register. */
5233 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value) (((value) & 0x00000004) >> 2)
5234 /* Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register. */
5235 #define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value) (((value) << 2) & 0x00000004)
5236 
5237 /*
5238  * Field : Timestamp Interrupt Mask - tsim
5239  *
5240  * When set, this bit disables the assertion of the interrupt signal because of the
5241  * setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status
5242  * Register).
5243  *
5244  * Field Enumeration Values:
5245  *
5246  * Enum | Value | Description
5247  * :----------------------------------|:------|:----------------------------------
5248  * ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD | 0x0 | Timestamp Interrupt Mask Disabled
5249  * ALT_EMAC_GMAC_INT_MSK_TSIM_E_END | 0x1 | Timestamp Interrupt Mask Enabled
5250  *
5251  * Field Access Macros:
5252  *
5253  */
5254 /*
5255  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
5256  *
5257  * Timestamp Interrupt Mask Disabled
5258  */
5259 #define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD 0x0
5260 /*
5261  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
5262  *
5263  * Timestamp Interrupt Mask Enabled
5264  */
5265 #define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END 0x1
5266 
5267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
5268 #define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB 9
5269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
5270 #define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB 9
5271 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
5272 #define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH 1
5273 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
5274 #define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK 0x00000200
5275 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
5276 #define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK 0xfffffdff
5277 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
5278 #define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET 0x0
5279 /* Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register. */
5280 #define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value) (((value) & 0x00000200) >> 9)
5281 /* Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register. */
5282 #define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value) (((value) << 9) & 0x00000200)
5283 
5284 /*
5285  * Field : LPI Interrupt Mask - lpiim
5286  *
5287  * When set, this bit disables the assertion of the interrupt signal because of the
5288  * setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status
5289  * Register).
5290  *
5291  * Field Enumeration Values:
5292  *
5293  * Enum | Value | Description
5294  * :-----------------------------------|:------|:----------------------------
5295  * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD | 0x0 | LPI Interrupt Mask Disabled
5296  * ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END | 0x1 | LPI Interrupt Mask Enabled
5297  *
5298  * Field Access Macros:
5299  *
5300  */
5301 /*
5302  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
5303  *
5304  * LPI Interrupt Mask Disabled
5305  */
5306 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD 0x0
5307 /*
5308  * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
5309  *
5310  * LPI Interrupt Mask Enabled
5311  */
5312 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END 0x1
5313 
5314 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
5315 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB 10
5316 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
5317 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB 10
5318 /* The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
5319 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH 1
5320 /* The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
5321 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK 0x00000400
5322 /* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
5323 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK 0xfffffbff
5324 /* The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
5325 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET 0x0
5326 /* Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register. */
5327 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value) (((value) & 0x00000400) >> 10)
5328 /* Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register. */
5329 #define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value) (((value) << 10) & 0x00000400)
5330 
5331 #ifndef __ASSEMBLY__
5332 /*
5333  * WARNING: The C register and register group struct declarations are provided for
5334  * convenience and illustrative purposes. They should, however, be used with
5335  * caution as the C language standard provides no guarantees about the alignment or
5336  * atomicity of device memory accesses. The recommended practice for writing
5337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5338  * alt_write_word() functions.
5339  *
5340  * The struct declaration for register ALT_EMAC_GMAC_INT_MSK.
5341  */
5342 struct ALT_EMAC_GMAC_INT_MSK_s
5343 {
5344  uint32_t rgsmiiim : 1; /* RGMII or SMII Interrupt Mask */
5345  const uint32_t pcslchgim : 1; /* PCS Link Status Interrupt Mask */
5346  const uint32_t pcsancim : 1; /* PCS AN Completion Interrupt Mask */
5347  uint32_t : 6; /* *UNDEFINED* */
5348  uint32_t tsim : 1; /* Timestamp Interrupt Mask */
5349  uint32_t lpiim : 1; /* LPI Interrupt Mask */
5350  uint32_t : 21; /* *UNDEFINED* */
5351 };
5352 
5353 /* The typedef declaration for register ALT_EMAC_GMAC_INT_MSK. */
5354 typedef volatile struct ALT_EMAC_GMAC_INT_MSK_s ALT_EMAC_GMAC_INT_MSK_t;
5355 #endif /* __ASSEMBLY__ */
5356 
5357 /* The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component. */
5358 #define ALT_EMAC_GMAC_INT_MSK_OFST 0x3c
5359 /* The address of the ALT_EMAC_GMAC_INT_MSK register. */
5360 #define ALT_EMAC_GMAC_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))
5361 
5362 /*
5363  * Register : Register 16 (MAC Address0 High Register) - MAC_Address0_High
5364  *
5365  * The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC
5366  * address of the station. The first DA byte that is received on the (G)MII
5367  * interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low
5368  * register. For example, if 0x112233445566 is received (0x11 in lane 0 of the
5369  * first column) on the (G)MII as the destination address, then the MacAddress0
5370  * Register [47:0] is compared with 0x665544332211.
5371  *
5372  * Because the MAC address registers are double-synchronized to the (G)MII clock
5373  * domains, then the synchronization is triggered only when Bits[31:24] (in little-
5374  * endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register
5375  * are written. For proper synchronization updates, the consecutive writes to this
5376  * Address Low Register should be performed after at least four clock cycles in the
5377  * destination clock domain.
5378  *
5379  * Register Layout
5380  *
5381  * Bits | Access | Reset | Description
5382  * :--------|:-------|:-------|:---------------------
5383  * [15:0] | RW | 0xffff | MAC Address0 [47:32]
5384  * [30:16] | ??? | 0x0 | *UNDEFINED*
5385  * [31] | R | 0x1 | Address Enable
5386  *
5387  */
5388 /*
5389  * Field : MAC Address0 [47:32] - addrhi
5390  *
5391  * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.
5392  * The MAC uses this field for filtering the received frames and inserting the MAC
5393  * address in the Transmit Flow Control (PAUSE) Frames.
5394  *
5395  * Field Access Macros:
5396  *
5397  */
5398 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
5399 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_LSB 0
5400 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
5401 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_MSB 15
5402 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
5403 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_WIDTH 16
5404 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
5405 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET_MSK 0x0000ffff
5406 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
5407 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_CLR_MSK 0xffff0000
5408 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
5409 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_RESET 0xffff
5410 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI field value from a register. */
5411 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
5412 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value suitable for setting the register. */
5413 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
5414 
5415 /*
5416  * Field : Address Enable - ae
5417  *
5418  * This bit is always set to 1.
5419  *
5420  * Field Access Macros:
5421  *
5422  */
5423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
5424 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_LSB 31
5425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
5426 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_MSB 31
5427 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
5428 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_WIDTH 1
5429 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
5430 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET_MSK 0x80000000
5431 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
5432 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_CLR_MSK 0x7fffffff
5433 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
5434 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_RESET 0x1
5435 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE field value from a register. */
5436 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
5437 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value suitable for setting the register. */
5438 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
5439 
5440 #ifndef __ASSEMBLY__
5441 /*
5442  * WARNING: The C register and register group struct declarations are provided for
5443  * convenience and illustrative purposes. They should, however, be used with
5444  * caution as the C language standard provides no guarantees about the alignment or
5445  * atomicity of device memory accesses. The recommended practice for writing
5446  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5447  * alt_write_word() functions.
5448  *
5449  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH.
5450  */
5451 struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s
5452 {
5453  uint32_t addrhi : 16; /* MAC Address0 [47:32] */
5454  uint32_t : 15; /* *UNDEFINED* */
5455  const uint32_t ae : 1; /* Address Enable */
5456 };
5457 
5458 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH. */
5459 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t;
5460 #endif /* __ASSEMBLY__ */
5461 
5462 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register from the beginning of the component. */
5463 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST 0x40
5464 /* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register. */
5465 #define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST))
5466 
5467 /*
5468  * Register : Register 17 (MAC Address0 Low Register) - MAC_Address0_Low
5469  *
5470  * The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC
5471  * address of the station.
5472  *
5473  * Register Layout
5474  *
5475  * Bits | Access | Reset | Description
5476  * :-------|:-------|:-----------|:--------------------
5477  * [31:0] | RW | 0xffffffff | MAC Address0 [31:0]
5478  *
5479  */
5480 /*
5481  * Field : MAC Address0 [31:0] - addrlo
5482  *
5483  * This field contains the lower 32 bits of the first 6-byte MAC address. This is
5484  * used by the MAC for filtering the received frames and inserting the MAC address
5485  * in the Transmit Flow Control (PAUSE) Frames.
5486  *
5487  * Field Access Macros:
5488  *
5489  */
5490 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
5491 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_LSB 0
5492 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
5493 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_MSB 31
5494 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
5495 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_WIDTH 32
5496 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
5497 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET_MSK 0xffffffff
5498 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
5499 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_CLR_MSK 0x00000000
5500 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
5501 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_RESET 0xffffffff
5502 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO field value from a register. */
5503 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
5504 /* Produces a ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value suitable for setting the register. */
5505 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
5506 
5507 #ifndef __ASSEMBLY__
5508 /*
5509  * WARNING: The C register and register group struct declarations are provided for
5510  * convenience and illustrative purposes. They should, however, be used with
5511  * caution as the C language standard provides no guarantees about the alignment or
5512  * atomicity of device memory accesses. The recommended practice for writing
5513  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5514  * alt_write_word() functions.
5515  *
5516  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW.
5517  */
5518 struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s
5519 {
5520  uint32_t addrlo : 32; /* MAC Address0 [31:0] */
5521 };
5522 
5523 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW. */
5524 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s ALT_EMAC_GMAC_MAC_ADDR0_LOW_t;
5525 #endif /* __ASSEMBLY__ */
5526 
5527 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register from the beginning of the component. */
5528 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST 0x44
5529 /* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register. */
5530 #define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST))
5531 
5532 /*
5533  * Register : Register 18 (MAC Address1 High Register) - MAC_Address1_High
5534  *
5535  * The MAC Address1 High register holds the upper 16 bits of the 2nd 6-byte MAC
5536  * address of the station. Because the MAC address registers are configured to be
5537  * double-synchronized to the (G)MII clock domains, the synchronization is
5538  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
5539  * endian mode) of the MAC Address1 Low Register are written. For proper
5540  * synchronization updates, the consecutive writes to this Address Low Register
5541  * should be performed after at least four clock cycles in the destination clock
5542  * domain.
5543  *
5544  * Note that all MAC Address High registers (except MAC Address0 High) have the
5545  * same format.
5546  *
5547  * Register Layout
5548  *
5549  * Bits | Access | Reset | Description
5550  * :--------|:-------|:-------|:---------------------
5551  * [15:0] | RW | 0xffff | MAC Address1 [47:32]
5552  * [23:16] | ??? | 0x0 | *UNDEFINED*
5553  * [24] | RW | 0x0 | Mask Byte Control
5554  * [25] | RW | 0x0 | Mask Byte Control
5555  * [26] | RW | 0x0 | Mask Byte Control
5556  * [27] | RW | 0x0 | Mask Byte Control
5557  * [28] | RW | 0x0 | Mask Byte Control
5558  * [29] | RW | 0x0 | Mask Byte Control
5559  * [30] | RW | 0x0 | Source Address
5560  * [31] | RW | 0x0 | Address Enable
5561  *
5562  */
5563 /*
5564  * Field : MAC Address1 [47:32] - addrhi
5565  *
5566  * This field contains the upper 16 bits (47:32) of the 2nd 6-byte MAC address.
5567  *
5568  * Field Access Macros:
5569  *
5570  */
5571 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
5572 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_LSB 0
5573 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
5574 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_MSB 15
5575 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
5576 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_WIDTH 16
5577 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
5578 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET_MSK 0x0000ffff
5579 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
5580 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_CLR_MSK 0xffff0000
5581 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
5582 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_RESET 0xffff
5583 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI field value from a register. */
5584 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
5585 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value suitable for setting the register. */
5586 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
5587 
5588 /*
5589  * Field : Mask Byte Control - mbc_0
5590  *
5591  * This array of bits are mask control bits for comparison of each of the MAC
5592  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5593  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5594  * bit controls the masking of the bytes. You can filter a group of addresses
5595  * (known as group address filtering) by masking one or more bytes of the address.
5596  *
5597  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5598  *
5599  * Field Enumeration Values:
5600  *
5601  * Enum | Value | Description
5602  * :---------------------------------------------|:------|:------------------------------------
5603  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5604  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5605  *
5606  * Field Access Macros:
5607  *
5608  */
5609 /*
5610  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
5611  *
5612  * Byte is unmasked (i.e. is compared)
5613  */
5614 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED 0x0
5615 /*
5616  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
5617  *
5618  * Byte is masked (i.e. not compared)
5619  */
5620 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED 0x1
5621 
5622 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
5623 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_LSB 24
5624 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
5625 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_MSB 24
5626 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
5627 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_WIDTH 1
5628 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
5629 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET_MSK 0x01000000
5630 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
5631 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_CLR_MSK 0xfeffffff
5632 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
5633 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_RESET 0x0
5634 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 field value from a register. */
5635 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
5636 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value suitable for setting the register. */
5637 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
5638 
5639 /*
5640  * Field : Mask Byte Control - mbc_1
5641  *
5642  * This array of bits are mask control bits for comparison of each of the MAC
5643  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5644  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5645  * bit controls the masking of the bytes. You can filter a group of addresses
5646  * (known as group address filtering) by masking one or more bytes of the address.
5647  *
5648  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5649  *
5650  * Field Enumeration Values:
5651  *
5652  * Enum | Value | Description
5653  * :---------------------------------------------|:------|:------------------------------------
5654  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5655  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5656  *
5657  * Field Access Macros:
5658  *
5659  */
5660 /*
5661  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
5662  *
5663  * Byte is unmasked (i.e. is compared)
5664  */
5665 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED 0x0
5666 /*
5667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
5668  *
5669  * Byte is masked (i.e. not compared)
5670  */
5671 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED 0x1
5672 
5673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
5674 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_LSB 25
5675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
5676 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_MSB 25
5677 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
5678 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_WIDTH 1
5679 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
5680 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET_MSK 0x02000000
5681 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
5682 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_CLR_MSK 0xfdffffff
5683 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
5684 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_RESET 0x0
5685 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 field value from a register. */
5686 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
5687 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value suitable for setting the register. */
5688 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
5689 
5690 /*
5691  * Field : Mask Byte Control - mbc_2
5692  *
5693  * This array of bits are mask control bits for comparison of each of the MAC
5694  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5695  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5696  * bit controls the masking of the bytes. You can filter a group of addresses
5697  * (known as group address filtering) by masking one or more bytes of the address.
5698  *
5699  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5700  *
5701  * Field Enumeration Values:
5702  *
5703  * Enum | Value | Description
5704  * :---------------------------------------------|:------|:------------------------------------
5705  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5706  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5707  *
5708  * Field Access Macros:
5709  *
5710  */
5711 /*
5712  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
5713  *
5714  * Byte is unmasked (i.e. is compared)
5715  */
5716 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED 0x0
5717 /*
5718  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
5719  *
5720  * Byte is masked (i.e. not compared)
5721  */
5722 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED 0x1
5723 
5724 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
5725 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_LSB 26
5726 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
5727 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_MSB 26
5728 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
5729 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_WIDTH 1
5730 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
5731 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET_MSK 0x04000000
5732 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
5733 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_CLR_MSK 0xfbffffff
5734 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
5735 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_RESET 0x0
5736 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 field value from a register. */
5737 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
5738 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value suitable for setting the register. */
5739 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
5740 
5741 /*
5742  * Field : Mask Byte Control - mbc_3
5743  *
5744  * This array of bits are mask control bits for comparison of each of the MAC
5745  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5746  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5747  * bit controls the masking of the bytes. You can filter a group of addresses
5748  * (known as group address filtering) by masking one or more bytes of the address.
5749  *
5750  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5751  *
5752  * Field Enumeration Values:
5753  *
5754  * Enum | Value | Description
5755  * :---------------------------------------------|:------|:------------------------------------
5756  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5757  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5758  *
5759  * Field Access Macros:
5760  *
5761  */
5762 /*
5763  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
5764  *
5765  * Byte is unmasked (i.e. is compared)
5766  */
5767 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED 0x0
5768 /*
5769  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
5770  *
5771  * Byte is masked (i.e. not compared)
5772  */
5773 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED 0x1
5774 
5775 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
5776 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_LSB 27
5777 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
5778 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_MSB 27
5779 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
5780 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_WIDTH 1
5781 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
5782 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET_MSK 0x08000000
5783 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
5784 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_CLR_MSK 0xf7ffffff
5785 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
5786 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_RESET 0x0
5787 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 field value from a register. */
5788 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
5789 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value suitable for setting the register. */
5790 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
5791 
5792 /*
5793  * Field : Mask Byte Control - mbc_4
5794  *
5795  * This array of bits are mask control bits for comparison of each of the MAC
5796  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5797  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5798  * bit controls the masking of the bytes. You can filter a group of addresses
5799  * (known as group address filtering) by masking one or more bytes of the address.
5800  *
5801  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5802  *
5803  * Field Enumeration Values:
5804  *
5805  * Enum | Value | Description
5806  * :---------------------------------------------|:------|:------------------------------------
5807  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5808  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5809  *
5810  * Field Access Macros:
5811  *
5812  */
5813 /*
5814  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
5815  *
5816  * Byte is unmasked (i.e. is compared)
5817  */
5818 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED 0x0
5819 /*
5820  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
5821  *
5822  * Byte is masked (i.e. not compared)
5823  */
5824 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED 0x1
5825 
5826 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
5827 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_LSB 28
5828 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
5829 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_MSB 28
5830 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
5831 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_WIDTH 1
5832 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
5833 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET_MSK 0x10000000
5834 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
5835 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_CLR_MSK 0xefffffff
5836 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
5837 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_RESET 0x0
5838 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 field value from a register. */
5839 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
5840 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value suitable for setting the register. */
5841 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
5842 
5843 /*
5844  * Field : Mask Byte Control - mbc_5
5845  *
5846  * This array of bits are mask control bits for comparison of each of the MAC
5847  * Address bytes. When masked, the MAC does not compare the corresponding byte of
5848  * received DA or SA with the contents of MAC Address1 high and low registers. Each
5849  * bit controls the masking of the bytes. You can filter a group of addresses
5850  * (known as group address filtering) by masking one or more bytes of the address.
5851  *
5852  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
5853  *
5854  * Field Enumeration Values:
5855  *
5856  * Enum | Value | Description
5857  * :---------------------------------------------|:------|:------------------------------------
5858  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
5859  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
5860  *
5861  * Field Access Macros:
5862  *
5863  */
5864 /*
5865  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
5866  *
5867  * Byte is unmasked (i.e. is compared)
5868  */
5869 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED 0x0
5870 /*
5871  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
5872  *
5873  * Byte is masked (i.e. not compared)
5874  */
5875 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED 0x1
5876 
5877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
5878 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_LSB 29
5879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
5880 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_MSB 29
5881 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
5882 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_WIDTH 1
5883 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
5884 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET_MSK 0x20000000
5885 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
5886 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_CLR_MSK 0xdfffffff
5887 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
5888 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_RESET 0x0
5889 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 field value from a register. */
5890 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
5891 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value suitable for setting the register. */
5892 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
5893 
5894 /*
5895  * Field : Source Address - sa
5896  *
5897  * When this bit is enabled, the MAC Address1[47:0] is used to compare with the SA
5898  * fields of the received frame. When this bit is disabled, the MAC Address1[47:0]
5899  * is used to compare with the DA fields of the received frame.
5900  *
5901  * Field Enumeration Values:
5902  *
5903  * Enum | Value | Description
5904  * :---------------------------------------|:------|:-----------------------------
5905  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
5906  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END | 0x1 | MAC address compare enabled
5907  *
5908  * Field Access Macros:
5909  *
5910  */
5911 /*
5912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
5913  *
5914  * MAC address compare disabled
5915  */
5916 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD 0x0
5917 /*
5918  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
5919  *
5920  * MAC address compare enabled
5921  */
5922 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END 0x1
5923 
5924 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
5925 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_LSB 30
5926 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
5927 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_MSB 30
5928 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
5929 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_WIDTH 1
5930 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
5931 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET_MSK 0x40000000
5932 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
5933 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_CLR_MSK 0xbfffffff
5934 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
5935 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_RESET 0x0
5936 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA field value from a register. */
5937 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
5938 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value suitable for setting the register. */
5939 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
5940 
5941 /*
5942  * Field : Address Enable - ae
5943  *
5944  * When this bit is enabled, the address filter block uses the 2nd MAC address for
5945  * perfect filtering. When this bit is disabled, the address filter block ignores
5946  * the address for filtering.
5947  *
5948  * Field Enumeration Values:
5949  *
5950  * Enum | Value | Description
5951  * :---------------------------------------|:------|:--------------------------------------
5952  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
5953  * ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
5954  *
5955  * Field Access Macros:
5956  *
5957  */
5958 /*
5959  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
5960  *
5961  * Second MAC address filtering disabled
5962  */
5963 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD 0x0
5964 /*
5965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
5966  *
5967  * Second MAC address filtering enabled
5968  */
5969 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END 0x1
5970 
5971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
5972 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_LSB 31
5973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
5974 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_MSB 31
5975 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
5976 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_WIDTH 1
5977 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
5978 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET_MSK 0x80000000
5979 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
5980 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_CLR_MSK 0x7fffffff
5981 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
5982 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_RESET 0x0
5983 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE field value from a register. */
5984 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
5985 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value suitable for setting the register. */
5986 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
5987 
5988 #ifndef __ASSEMBLY__
5989 /*
5990  * WARNING: The C register and register group struct declarations are provided for
5991  * convenience and illustrative purposes. They should, however, be used with
5992  * caution as the C language standard provides no guarantees about the alignment or
5993  * atomicity of device memory accesses. The recommended practice for writing
5994  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5995  * alt_write_word() functions.
5996  *
5997  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH.
5998  */
5999 struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s
6000 {
6001  uint32_t addrhi : 16; /* MAC Address1 [47:32] */
6002  uint32_t : 8; /* *UNDEFINED* */
6003  uint32_t mbc_0 : 1; /* Mask Byte Control */
6004  uint32_t mbc_1 : 1; /* Mask Byte Control */
6005  uint32_t mbc_2 : 1; /* Mask Byte Control */
6006  uint32_t mbc_3 : 1; /* Mask Byte Control */
6007  uint32_t mbc_4 : 1; /* Mask Byte Control */
6008  uint32_t mbc_5 : 1; /* Mask Byte Control */
6009  uint32_t sa : 1; /* Source Address */
6010  uint32_t ae : 1; /* Address Enable */
6011 };
6012 
6013 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH. */
6014 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t;
6015 #endif /* __ASSEMBLY__ */
6016 
6017 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register from the beginning of the component. */
6018 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST 0x48
6019 /* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register. */
6020 #define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST))
6021 
6022 /*
6023  * Register : Register 19 (MAC Address1 Low Register) - MAC_Address1_Low
6024  *
6025  * The MAC Address1 Low register holds the lower 32 bits of the 2nd 6-byte MAC
6026  * address of the station.
6027  *
6028  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
6029  * format.
6030  *
6031  * Register Layout
6032  *
6033  * Bits | Access | Reset | Description
6034  * :-------|:-------|:-----------|:--------------------
6035  * [31:0] | RW | 0xffffffff | MAC Address1 [31:0]
6036  *
6037  */
6038 /*
6039  * Field : MAC Address1 [31:0] - addrlo
6040  *
6041  * This field contains the lower 32 bits of the 2nd 6-byte MAC address. The content
6042  * of this field is undefined until loaded by software after the initialization
6043  * process.
6044  *
6045  * Field Access Macros:
6046  *
6047  */
6048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
6049 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_LSB 0
6050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
6051 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_MSB 31
6052 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
6053 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_WIDTH 32
6054 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
6055 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET_MSK 0xffffffff
6056 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
6057 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_CLR_MSK 0x00000000
6058 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
6059 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_RESET 0xffffffff
6060 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO field value from a register. */
6061 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
6062 /* Produces a ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value suitable for setting the register. */
6063 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
6064 
6065 #ifndef __ASSEMBLY__
6066 /*
6067  * WARNING: The C register and register group struct declarations are provided for
6068  * convenience and illustrative purposes. They should, however, be used with
6069  * caution as the C language standard provides no guarantees about the alignment or
6070  * atomicity of device memory accesses. The recommended practice for writing
6071  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6072  * alt_write_word() functions.
6073  *
6074  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW.
6075  */
6076 struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s
6077 {
6078  uint32_t addrlo : 32; /* MAC Address1 [31:0] */
6079 };
6080 
6081 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW. */
6082 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s ALT_EMAC_GMAC_MAC_ADDR1_LOW_t;
6083 #endif /* __ASSEMBLY__ */
6084 
6085 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register from the beginning of the component. */
6086 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST 0x4c
6087 /* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register. */
6088 #define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST))
6089 
6090 /*
6091  * Register : Register 20 (MAC Address2 High Register) - MAC_Address2_High
6092  *
6093  * The MAC Address2 High register holds the upper 16 bits of the 3rd 6-byte MAC
6094  * address of the station. Because the MAC address registers are configured to be
6095  * double-synchronized to the (G)MII clock domains, the synchronization is
6096  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
6097  * endian mode) of the MAC Address2 Low Register are written. For proper
6098  * synchronization updates, the consecutive writes to this Address Low Register
6099  * should be performed after at least four clock cycles in the destination clock
6100  * domain.
6101  *
6102  * Note that all MAC Address High registers (except MAC Address0 High) have the
6103  * same format.
6104  *
6105  * Register Layout
6106  *
6107  * Bits | Access | Reset | Description
6108  * :--------|:-------|:-------|:---------------------
6109  * [15:0] | RW | 0xffff | MAC Address2 [47:32]
6110  * [23:16] | ??? | 0x0 | *UNDEFINED*
6111  * [24] | RW | 0x0 | Mask Byte Control
6112  * [25] | RW | 0x0 | Mask Byte Control
6113  * [26] | RW | 0x0 | Mask Byte Control
6114  * [27] | RW | 0x0 | Mask Byte Control
6115  * [28] | RW | 0x0 | Mask Byte Control
6116  * [29] | RW | 0x0 | Mask Byte Control
6117  * [30] | RW | 0x0 | Source Address
6118  * [31] | RW | 0x0 | Address Enable
6119  *
6120  */
6121 /*
6122  * Field : MAC Address2 [47:32] - addrhi
6123  *
6124  * This field contains the upper 16 bits (47:32) of the 3rd 6-byte MAC address.
6125  *
6126  * Field Access Macros:
6127  *
6128  */
6129 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
6130 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_LSB 0
6131 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
6132 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_MSB 15
6133 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
6134 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_WIDTH 16
6135 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
6136 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET_MSK 0x0000ffff
6137 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
6138 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_CLR_MSK 0xffff0000
6139 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
6140 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_RESET 0xffff
6141 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI field value from a register. */
6142 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
6143 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value suitable for setting the register. */
6144 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
6145 
6146 /*
6147  * Field : Mask Byte Control - mbc_0
6148  *
6149  * This array of bits are mask control bits for comparison of each of the MAC
6150  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6151  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6152  * bit controls the masking of the bytes. You can filter a group of addresses
6153  * (known as group address filtering) by masking one or more bytes of the address.
6154  *
6155  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6156  *
6157  * Field Enumeration Values:
6158  *
6159  * Enum | Value | Description
6160  * :---------------------------------------------|:------|:------------------------------------
6161  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6162  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6163  *
6164  * Field Access Macros:
6165  *
6166  */
6167 /*
6168  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
6169  *
6170  * Byte is unmasked (i.e. is compared)
6171  */
6172 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED 0x0
6173 /*
6174  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
6175  *
6176  * Byte is masked (i.e. not compared)
6177  */
6178 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED 0x1
6179 
6180 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
6181 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_LSB 24
6182 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
6183 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_MSB 24
6184 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
6185 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_WIDTH 1
6186 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
6187 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET_MSK 0x01000000
6188 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
6189 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_CLR_MSK 0xfeffffff
6190 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
6191 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_RESET 0x0
6192 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 field value from a register. */
6193 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
6194 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value suitable for setting the register. */
6195 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
6196 
6197 /*
6198  * Field : Mask Byte Control - mbc_1
6199  *
6200  * This array of bits are mask control bits for comparison of each of the MAC
6201  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6202  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6203  * bit controls the masking of the bytes. You can filter a group of addresses
6204  * (known as group address filtering) by masking one or more bytes of the address.
6205  *
6206  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6207  *
6208  * Field Enumeration Values:
6209  *
6210  * Enum | Value | Description
6211  * :---------------------------------------------|:------|:------------------------------------
6212  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6213  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6214  *
6215  * Field Access Macros:
6216  *
6217  */
6218 /*
6219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
6220  *
6221  * Byte is unmasked (i.e. is compared)
6222  */
6223 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED 0x0
6224 /*
6225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
6226  *
6227  * Byte is masked (i.e. not compared)
6228  */
6229 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED 0x1
6230 
6231 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
6232 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_LSB 25
6233 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
6234 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_MSB 25
6235 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
6236 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_WIDTH 1
6237 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
6238 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET_MSK 0x02000000
6239 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
6240 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_CLR_MSK 0xfdffffff
6241 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
6242 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_RESET 0x0
6243 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 field value from a register. */
6244 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
6245 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value suitable for setting the register. */
6246 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
6247 
6248 /*
6249  * Field : Mask Byte Control - mbc_2
6250  *
6251  * This array of bits are mask control bits for comparison of each of the MAC
6252  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6253  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6254  * bit controls the masking of the bytes. You can filter a group of addresses
6255  * (known as group address filtering) by masking one or more bytes of the address.
6256  *
6257  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6258  *
6259  * Field Enumeration Values:
6260  *
6261  * Enum | Value | Description
6262  * :---------------------------------------------|:------|:------------------------------------
6263  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6264  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6265  *
6266  * Field Access Macros:
6267  *
6268  */
6269 /*
6270  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
6271  *
6272  * Byte is unmasked (i.e. is compared)
6273  */
6274 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED 0x0
6275 /*
6276  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
6277  *
6278  * Byte is masked (i.e. not compared)
6279  */
6280 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED 0x1
6281 
6282 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
6283 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_LSB 26
6284 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
6285 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_MSB 26
6286 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
6287 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_WIDTH 1
6288 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
6289 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET_MSK 0x04000000
6290 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
6291 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_CLR_MSK 0xfbffffff
6292 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
6293 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_RESET 0x0
6294 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 field value from a register. */
6295 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
6296 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value suitable for setting the register. */
6297 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
6298 
6299 /*
6300  * Field : Mask Byte Control - mbc_3
6301  *
6302  * This array of bits are mask control bits for comparison of each of the MAC
6303  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6304  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6305  * bit controls the masking of the bytes. You can filter a group of addresses
6306  * (known as group address filtering) by masking one or more bytes of the address.
6307  *
6308  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6309  *
6310  * Field Enumeration Values:
6311  *
6312  * Enum | Value | Description
6313  * :---------------------------------------------|:------|:------------------------------------
6314  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6315  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6316  *
6317  * Field Access Macros:
6318  *
6319  */
6320 /*
6321  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
6322  *
6323  * Byte is unmasked (i.e. is compared)
6324  */
6325 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED 0x0
6326 /*
6327  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
6328  *
6329  * Byte is masked (i.e. not compared)
6330  */
6331 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED 0x1
6332 
6333 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
6334 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_LSB 27
6335 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
6336 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_MSB 27
6337 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
6338 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_WIDTH 1
6339 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
6340 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET_MSK 0x08000000
6341 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
6342 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_CLR_MSK 0xf7ffffff
6343 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
6344 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_RESET 0x0
6345 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 field value from a register. */
6346 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
6347 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value suitable for setting the register. */
6348 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
6349 
6350 /*
6351  * Field : Mask Byte Control - mbc_4
6352  *
6353  * This array of bits are mask control bits for comparison of each of the MAC
6354  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6355  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6356  * bit controls the masking of the bytes. You can filter a group of addresses
6357  * (known as group address filtering) by masking one or more bytes of the address.
6358  *
6359  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6360  *
6361  * Field Enumeration Values:
6362  *
6363  * Enum | Value | Description
6364  * :---------------------------------------------|:------|:------------------------------------
6365  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6366  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6367  *
6368  * Field Access Macros:
6369  *
6370  */
6371 /*
6372  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
6373  *
6374  * Byte is unmasked (i.e. is compared)
6375  */
6376 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED 0x0
6377 /*
6378  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
6379  *
6380  * Byte is masked (i.e. not compared)
6381  */
6382 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED 0x1
6383 
6384 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
6385 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_LSB 28
6386 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
6387 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_MSB 28
6388 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
6389 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_WIDTH 1
6390 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
6391 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET_MSK 0x10000000
6392 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
6393 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_CLR_MSK 0xefffffff
6394 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
6395 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_RESET 0x0
6396 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 field value from a register. */
6397 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
6398 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value suitable for setting the register. */
6399 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
6400 
6401 /*
6402  * Field : Mask Byte Control - mbc_5
6403  *
6404  * This array of bits are mask control bits for comparison of each of the MAC
6405  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6406  * received DA or SA with the contents of MAC Address2 high and low registers. Each
6407  * bit controls the masking of the bytes. You can filter a group of addresses
6408  * (known as group address filtering) by masking one or more bytes of the address.
6409  *
6410  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6411  *
6412  * Field Enumeration Values:
6413  *
6414  * Enum | Value | Description
6415  * :---------------------------------------------|:------|:------------------------------------
6416  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6417  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6418  *
6419  * Field Access Macros:
6420  *
6421  */
6422 /*
6423  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
6424  *
6425  * Byte is unmasked (i.e. is compared)
6426  */
6427 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED 0x0
6428 /*
6429  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
6430  *
6431  * Byte is masked (i.e. not compared)
6432  */
6433 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED 0x1
6434 
6435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
6436 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_LSB 29
6437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
6438 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_MSB 29
6439 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
6440 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_WIDTH 1
6441 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
6442 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET_MSK 0x20000000
6443 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
6444 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_CLR_MSK 0xdfffffff
6445 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
6446 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_RESET 0x0
6447 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 field value from a register. */
6448 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
6449 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value suitable for setting the register. */
6450 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
6451 
6452 /*
6453  * Field : Source Address - sa
6454  *
6455  * When this bit is enabled, the MAC Address2[47:0] is used to compare with the SA
6456  * fields of the received frame. When this bit is disabled, the MAC Address2[47:0]
6457  * is used to compare with the DA fields of the received frame.
6458  *
6459  * Field Enumeration Values:
6460  *
6461  * Enum | Value | Description
6462  * :---------------------------------------|:------|:-----------------------------
6463  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
6464  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END | 0x1 | MAC address compare enabled
6465  *
6466  * Field Access Macros:
6467  *
6468  */
6469 /*
6470  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
6471  *
6472  * MAC address compare disabled
6473  */
6474 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD 0x0
6475 /*
6476  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
6477  *
6478  * MAC address compare enabled
6479  */
6480 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END 0x1
6481 
6482 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
6483 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_LSB 30
6484 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
6485 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_MSB 30
6486 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
6487 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_WIDTH 1
6488 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
6489 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET_MSK 0x40000000
6490 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
6491 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_CLR_MSK 0xbfffffff
6492 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
6493 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_RESET 0x0
6494 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA field value from a register. */
6495 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
6496 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value suitable for setting the register. */
6497 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
6498 
6499 /*
6500  * Field : Address Enable - ae
6501  *
6502  * When this bit is enabled, the address filter block uses the 3rd MAC address for
6503  * perfect filtering. When this bit is disabled, the address filter block ignores
6504  * the address for filtering.
6505  *
6506  * Field Enumeration Values:
6507  *
6508  * Enum | Value | Description
6509  * :---------------------------------------|:------|:--------------------------------------
6510  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
6511  * ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
6512  *
6513  * Field Access Macros:
6514  *
6515  */
6516 /*
6517  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
6518  *
6519  * Second MAC address filtering disabled
6520  */
6521 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD 0x0
6522 /*
6523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
6524  *
6525  * Second MAC address filtering enabled
6526  */
6527 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END 0x1
6528 
6529 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
6530 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_LSB 31
6531 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
6532 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_MSB 31
6533 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
6534 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_WIDTH 1
6535 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
6536 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET_MSK 0x80000000
6537 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
6538 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_CLR_MSK 0x7fffffff
6539 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
6540 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_RESET 0x0
6541 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE field value from a register. */
6542 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
6543 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value suitable for setting the register. */
6544 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
6545 
6546 #ifndef __ASSEMBLY__
6547 /*
6548  * WARNING: The C register and register group struct declarations are provided for
6549  * convenience and illustrative purposes. They should, however, be used with
6550  * caution as the C language standard provides no guarantees about the alignment or
6551  * atomicity of device memory accesses. The recommended practice for writing
6552  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6553  * alt_write_word() functions.
6554  *
6555  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH.
6556  */
6557 struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s
6558 {
6559  uint32_t addrhi : 16; /* MAC Address2 [47:32] */
6560  uint32_t : 8; /* *UNDEFINED* */
6561  uint32_t mbc_0 : 1; /* Mask Byte Control */
6562  uint32_t mbc_1 : 1; /* Mask Byte Control */
6563  uint32_t mbc_2 : 1; /* Mask Byte Control */
6564  uint32_t mbc_3 : 1; /* Mask Byte Control */
6565  uint32_t mbc_4 : 1; /* Mask Byte Control */
6566  uint32_t mbc_5 : 1; /* Mask Byte Control */
6567  uint32_t sa : 1; /* Source Address */
6568  uint32_t ae : 1; /* Address Enable */
6569 };
6570 
6571 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH. */
6572 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t;
6573 #endif /* __ASSEMBLY__ */
6574 
6575 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register from the beginning of the component. */
6576 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST 0x50
6577 /* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register. */
6578 #define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST))
6579 
6580 /*
6581  * Register : Register 21 (MAC Address2 Low Register) - MAC_Address2_Low
6582  *
6583  * The MAC Address2 Low register holds the lower 32 bits of the 3rd 6-byte MAC
6584  * address of the station.
6585  *
6586  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
6587  * format.
6588  *
6589  * Register Layout
6590  *
6591  * Bits | Access | Reset | Description
6592  * :-------|:-------|:-----------|:--------------------
6593  * [31:0] | RW | 0xffffffff | MAC Address2 [31:0]
6594  *
6595  */
6596 /*
6597  * Field : MAC Address2 [31:0] - addrlo
6598  *
6599  * This field contains the lower 32 bits of the 3rd 6-byte MAC address. The content
6600  * of this field is undefined until loaded by software after the initialization
6601  * process.
6602  *
6603  * Field Access Macros:
6604  *
6605  */
6606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
6607 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_LSB 0
6608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
6609 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_MSB 31
6610 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
6611 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_WIDTH 32
6612 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
6613 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET_MSK 0xffffffff
6614 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
6615 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_CLR_MSK 0x00000000
6616 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
6617 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_RESET 0xffffffff
6618 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO field value from a register. */
6619 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
6620 /* Produces a ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value suitable for setting the register. */
6621 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
6622 
6623 #ifndef __ASSEMBLY__
6624 /*
6625  * WARNING: The C register and register group struct declarations are provided for
6626  * convenience and illustrative purposes. They should, however, be used with
6627  * caution as the C language standard provides no guarantees about the alignment or
6628  * atomicity of device memory accesses. The recommended practice for writing
6629  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6630  * alt_write_word() functions.
6631  *
6632  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW.
6633  */
6634 struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s
6635 {
6636  uint32_t addrlo : 32; /* MAC Address2 [31:0] */
6637 };
6638 
6639 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW. */
6640 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s ALT_EMAC_GMAC_MAC_ADDR2_LOW_t;
6641 #endif /* __ASSEMBLY__ */
6642 
6643 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register from the beginning of the component. */
6644 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST 0x54
6645 /* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register. */
6646 #define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST))
6647 
6648 /*
6649  * Register : Register 22 (MAC Address3 High Register) - MAC_Address3_High
6650  *
6651  * The MAC Address3 High register holds the upper 16 bits of the 4th 6-byte MAC
6652  * address of the station. Because the MAC address registers are configured to be
6653  * double-synchronized to the (G)MII clock domains, the synchronization is
6654  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
6655  * endian mode) of the MAC Address3 Low Register are written. For proper
6656  * synchronization updates, the consecutive writes to this Address Low Register
6657  * should be performed after at least four clock cycles in the destination clock
6658  * domain.
6659  *
6660  * Note that all MAC Address High registers (except MAC Address0 High) have the
6661  * same format.
6662  *
6663  * Register Layout
6664  *
6665  * Bits | Access | Reset | Description
6666  * :--------|:-------|:-------|:---------------------
6667  * [15:0] | RW | 0xffff | MAC Address3 [47:32]
6668  * [23:16] | ??? | 0x0 | *UNDEFINED*
6669  * [24] | RW | 0x0 | Mask Byte Control
6670  * [25] | RW | 0x0 | Mask Byte Control
6671  * [26] | RW | 0x0 | Mask Byte Control
6672  * [27] | RW | 0x0 | Mask Byte Control
6673  * [28] | RW | 0x0 | Mask Byte Control
6674  * [29] | RW | 0x0 | Mask Byte Control
6675  * [30] | RW | 0x0 | Source Address
6676  * [31] | RW | 0x0 | Address Enable
6677  *
6678  */
6679 /*
6680  * Field : MAC Address3 [47:32] - addrhi
6681  *
6682  * This field contains the upper 16 bits (47:32) of the 4th 6-byte MAC address.
6683  *
6684  * Field Access Macros:
6685  *
6686  */
6687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
6688 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_LSB 0
6689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
6690 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_MSB 15
6691 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
6692 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_WIDTH 16
6693 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
6694 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET_MSK 0x0000ffff
6695 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
6696 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_CLR_MSK 0xffff0000
6697 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
6698 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_RESET 0xffff
6699 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI field value from a register. */
6700 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
6701 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value suitable for setting the register. */
6702 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
6703 
6704 /*
6705  * Field : Mask Byte Control - mbc_0
6706  *
6707  * This array of bits are mask control bits for comparison of each of the MAC
6708  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6709  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6710  * bit controls the masking of the bytes. You can filter a group of addresses
6711  * (known as group address filtering) by masking one or more bytes of the address.
6712  *
6713  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6714  *
6715  * Field Enumeration Values:
6716  *
6717  * Enum | Value | Description
6718  * :---------------------------------------------|:------|:------------------------------------
6719  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6720  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6721  *
6722  * Field Access Macros:
6723  *
6724  */
6725 /*
6726  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
6727  *
6728  * Byte is unmasked (i.e. is compared)
6729  */
6730 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED 0x0
6731 /*
6732  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
6733  *
6734  * Byte is masked (i.e. not compared)
6735  */
6736 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED 0x1
6737 
6738 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
6739 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_LSB 24
6740 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
6741 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_MSB 24
6742 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
6743 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_WIDTH 1
6744 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
6745 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET_MSK 0x01000000
6746 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
6747 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_CLR_MSK 0xfeffffff
6748 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
6749 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_RESET 0x0
6750 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 field value from a register. */
6751 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
6752 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value suitable for setting the register. */
6753 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
6754 
6755 /*
6756  * Field : Mask Byte Control - mbc_1
6757  *
6758  * This array of bits are mask control bits for comparison of each of the MAC
6759  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6760  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6761  * bit controls the masking of the bytes. You can filter a group of addresses
6762  * (known as group address filtering) by masking one or more bytes of the address.
6763  *
6764  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6765  *
6766  * Field Enumeration Values:
6767  *
6768  * Enum | Value | Description
6769  * :---------------------------------------------|:------|:------------------------------------
6770  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6771  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6772  *
6773  * Field Access Macros:
6774  *
6775  */
6776 /*
6777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
6778  *
6779  * Byte is unmasked (i.e. is compared)
6780  */
6781 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED 0x0
6782 /*
6783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
6784  *
6785  * Byte is masked (i.e. not compared)
6786  */
6787 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED 0x1
6788 
6789 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
6790 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_LSB 25
6791 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
6792 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_MSB 25
6793 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
6794 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_WIDTH 1
6795 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
6796 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET_MSK 0x02000000
6797 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
6798 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_CLR_MSK 0xfdffffff
6799 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
6800 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_RESET 0x0
6801 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 field value from a register. */
6802 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
6803 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value suitable for setting the register. */
6804 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
6805 
6806 /*
6807  * Field : Mask Byte Control - mbc_2
6808  *
6809  * This array of bits are mask control bits for comparison of each of the MAC
6810  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6811  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6812  * bit controls the masking of the bytes. You can filter a group of addresses
6813  * (known as group address filtering) by masking one or more bytes of the address.
6814  *
6815  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6816  *
6817  * Field Enumeration Values:
6818  *
6819  * Enum | Value | Description
6820  * :---------------------------------------------|:------|:------------------------------------
6821  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6822  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6823  *
6824  * Field Access Macros:
6825  *
6826  */
6827 /*
6828  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
6829  *
6830  * Byte is unmasked (i.e. is compared)
6831  */
6832 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED 0x0
6833 /*
6834  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
6835  *
6836  * Byte is masked (i.e. not compared)
6837  */
6838 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED 0x1
6839 
6840 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
6841 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_LSB 26
6842 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
6843 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_MSB 26
6844 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
6845 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_WIDTH 1
6846 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
6847 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET_MSK 0x04000000
6848 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
6849 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_CLR_MSK 0xfbffffff
6850 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
6851 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_RESET 0x0
6852 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 field value from a register. */
6853 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
6854 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value suitable for setting the register. */
6855 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
6856 
6857 /*
6858  * Field : Mask Byte Control - mbc_3
6859  *
6860  * This array of bits are mask control bits for comparison of each of the MAC
6861  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6862  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6863  * bit controls the masking of the bytes. You can filter a group of addresses
6864  * (known as group address filtering) by masking one or more bytes of the address.
6865  *
6866  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6867  *
6868  * Field Enumeration Values:
6869  *
6870  * Enum | Value | Description
6871  * :---------------------------------------------|:------|:------------------------------------
6872  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6873  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6874  *
6875  * Field Access Macros:
6876  *
6877  */
6878 /*
6879  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
6880  *
6881  * Byte is unmasked (i.e. is compared)
6882  */
6883 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED 0x0
6884 /*
6885  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
6886  *
6887  * Byte is masked (i.e. not compared)
6888  */
6889 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED 0x1
6890 
6891 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
6892 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_LSB 27
6893 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
6894 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_MSB 27
6895 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
6896 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_WIDTH 1
6897 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
6898 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET_MSK 0x08000000
6899 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
6900 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_CLR_MSK 0xf7ffffff
6901 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
6902 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_RESET 0x0
6903 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 field value from a register. */
6904 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
6905 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value suitable for setting the register. */
6906 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
6907 
6908 /*
6909  * Field : Mask Byte Control - mbc_4
6910  *
6911  * This array of bits are mask control bits for comparison of each of the MAC
6912  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6913  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6914  * bit controls the masking of the bytes. You can filter a group of addresses
6915  * (known as group address filtering) by masking one or more bytes of the address.
6916  *
6917  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6918  *
6919  * Field Enumeration Values:
6920  *
6921  * Enum | Value | Description
6922  * :---------------------------------------------|:------|:------------------------------------
6923  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6924  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6925  *
6926  * Field Access Macros:
6927  *
6928  */
6929 /*
6930  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
6931  *
6932  * Byte is unmasked (i.e. is compared)
6933  */
6934 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED 0x0
6935 /*
6936  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
6937  *
6938  * Byte is masked (i.e. not compared)
6939  */
6940 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED 0x1
6941 
6942 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
6943 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_LSB 28
6944 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
6945 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_MSB 28
6946 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
6947 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_WIDTH 1
6948 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
6949 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET_MSK 0x10000000
6950 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
6951 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_CLR_MSK 0xefffffff
6952 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
6953 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_RESET 0x0
6954 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 field value from a register. */
6955 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
6956 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value suitable for setting the register. */
6957 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
6958 
6959 /*
6960  * Field : Mask Byte Control - mbc_5
6961  *
6962  * This array of bits are mask control bits for comparison of each of the MAC
6963  * Address bytes. When masked, the MAC does not compare the corresponding byte of
6964  * received DA or SA with the contents of MAC Address3 high and low registers. Each
6965  * bit controls the masking of the bytes. You can filter a group of addresses
6966  * (known as group address filtering) by masking one or more bytes of the address.
6967  *
6968  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
6969  *
6970  * Field Enumeration Values:
6971  *
6972  * Enum | Value | Description
6973  * :---------------------------------------------|:------|:------------------------------------
6974  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
6975  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
6976  *
6977  * Field Access Macros:
6978  *
6979  */
6980 /*
6981  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
6982  *
6983  * Byte is unmasked (i.e. is compared)
6984  */
6985 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED 0x0
6986 /*
6987  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
6988  *
6989  * Byte is masked (i.e. not compared)
6990  */
6991 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED 0x1
6992 
6993 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
6994 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_LSB 29
6995 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
6996 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_MSB 29
6997 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
6998 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_WIDTH 1
6999 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
7000 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET_MSK 0x20000000
7001 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
7002 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_CLR_MSK 0xdfffffff
7003 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
7004 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_RESET 0x0
7005 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 field value from a register. */
7006 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
7007 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value suitable for setting the register. */
7008 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
7009 
7010 /*
7011  * Field : Source Address - sa
7012  *
7013  * When this bit is enabled, the MAC Address3[47:0] is used to compare with the SA
7014  * fields of the received frame. When this bit is disabled, the MAC Address3[47:0]
7015  * is used to compare with the DA fields of the received frame.
7016  *
7017  * Field Enumeration Values:
7018  *
7019  * Enum | Value | Description
7020  * :---------------------------------------|:------|:-----------------------------
7021  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
7022  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END | 0x1 | MAC address compare enabled
7023  *
7024  * Field Access Macros:
7025  *
7026  */
7027 /*
7028  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
7029  *
7030  * MAC address compare disabled
7031  */
7032 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD 0x0
7033 /*
7034  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
7035  *
7036  * MAC address compare enabled
7037  */
7038 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END 0x1
7039 
7040 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
7041 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_LSB 30
7042 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
7043 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_MSB 30
7044 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
7045 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_WIDTH 1
7046 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
7047 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET_MSK 0x40000000
7048 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
7049 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_CLR_MSK 0xbfffffff
7050 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
7051 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_RESET 0x0
7052 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA field value from a register. */
7053 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
7054 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value suitable for setting the register. */
7055 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
7056 
7057 /*
7058  * Field : Address Enable - ae
7059  *
7060  * When this bit is enabled, the address filter block uses the 4th MAC address for
7061  * perfect filtering. When this bit is disabled, the address filter block ignores
7062  * the address for filtering.
7063  *
7064  * Field Enumeration Values:
7065  *
7066  * Enum | Value | Description
7067  * :---------------------------------------|:------|:--------------------------------------
7068  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
7069  * ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
7070  *
7071  * Field Access Macros:
7072  *
7073  */
7074 /*
7075  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
7076  *
7077  * Second MAC address filtering disabled
7078  */
7079 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD 0x0
7080 /*
7081  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
7082  *
7083  * Second MAC address filtering enabled
7084  */
7085 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END 0x1
7086 
7087 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
7088 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_LSB 31
7089 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
7090 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_MSB 31
7091 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
7092 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_WIDTH 1
7093 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
7094 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET_MSK 0x80000000
7095 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
7096 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_CLR_MSK 0x7fffffff
7097 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
7098 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_RESET 0x0
7099 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE field value from a register. */
7100 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
7101 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value suitable for setting the register. */
7102 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
7103 
7104 #ifndef __ASSEMBLY__
7105 /*
7106  * WARNING: The C register and register group struct declarations are provided for
7107  * convenience and illustrative purposes. They should, however, be used with
7108  * caution as the C language standard provides no guarantees about the alignment or
7109  * atomicity of device memory accesses. The recommended practice for writing
7110  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7111  * alt_write_word() functions.
7112  *
7113  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH.
7114  */
7115 struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s
7116 {
7117  uint32_t addrhi : 16; /* MAC Address3 [47:32] */
7118  uint32_t : 8; /* *UNDEFINED* */
7119  uint32_t mbc_0 : 1; /* Mask Byte Control */
7120  uint32_t mbc_1 : 1; /* Mask Byte Control */
7121  uint32_t mbc_2 : 1; /* Mask Byte Control */
7122  uint32_t mbc_3 : 1; /* Mask Byte Control */
7123  uint32_t mbc_4 : 1; /* Mask Byte Control */
7124  uint32_t mbc_5 : 1; /* Mask Byte Control */
7125  uint32_t sa : 1; /* Source Address */
7126  uint32_t ae : 1; /* Address Enable */
7127 };
7128 
7129 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH. */
7130 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t;
7131 #endif /* __ASSEMBLY__ */
7132 
7133 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register from the beginning of the component. */
7134 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST 0x58
7135 /* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register. */
7136 #define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST))
7137 
7138 /*
7139  * Register : Register 23 (MAC Address3 Low Register) - MAC_Address3_Low
7140  *
7141  * The MAC Address3 Low register holds the lower 32 bits of the 4th 6-byte MAC
7142  * address of the station.
7143  *
7144  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
7145  * format.
7146  *
7147  * Register Layout
7148  *
7149  * Bits | Access | Reset | Description
7150  * :-------|:-------|:-----------|:--------------------
7151  * [31:0] | RW | 0xffffffff | MAC Address3 [31:0]
7152  *
7153  */
7154 /*
7155  * Field : MAC Address3 [31:0] - addrlo
7156  *
7157  * This field contains the lower 32 bits of the 4th 6-byte MAC address. The content
7158  * of this field is undefined until loaded by software after the initialization
7159  * process.
7160  *
7161  * Field Access Macros:
7162  *
7163  */
7164 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
7165 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_LSB 0
7166 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
7167 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_MSB 31
7168 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
7169 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_WIDTH 32
7170 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
7171 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET_MSK 0xffffffff
7172 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
7173 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_CLR_MSK 0x00000000
7174 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
7175 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_RESET 0xffffffff
7176 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO field value from a register. */
7177 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
7178 /* Produces a ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value suitable for setting the register. */
7179 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
7180 
7181 #ifndef __ASSEMBLY__
7182 /*
7183  * WARNING: The C register and register group struct declarations are provided for
7184  * convenience and illustrative purposes. They should, however, be used with
7185  * caution as the C language standard provides no guarantees about the alignment or
7186  * atomicity of device memory accesses. The recommended practice for writing
7187  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7188  * alt_write_word() functions.
7189  *
7190  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW.
7191  */
7192 struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s
7193 {
7194  uint32_t addrlo : 32; /* MAC Address3 [31:0] */
7195 };
7196 
7197 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW. */
7198 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s ALT_EMAC_GMAC_MAC_ADDR3_LOW_t;
7199 #endif /* __ASSEMBLY__ */
7200 
7201 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register from the beginning of the component. */
7202 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST 0x5c
7203 /* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register. */
7204 #define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST))
7205 
7206 /*
7207  * Register : Register 24 (MAC Address4 High Register) - MAC_Address4_High
7208  *
7209  * The MAC Address4 High register holds the upper 16 bits of the 5th 6-byte MAC
7210  * address of the station. Because the MAC address registers are configured to be
7211  * double-synchronized to the (G)MII clock domains, the synchronization is
7212  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
7213  * endian mode) of the MAC Address4 Low Register are written. For proper
7214  * synchronization updates, the consecutive writes to this Address Low Register
7215  * should be performed after at least four clock cycles in the destination clock
7216  * domain.
7217  *
7218  * Note that all MAC Address High registers (except MAC Address0 High) have the
7219  * same format.
7220  *
7221  * Register Layout
7222  *
7223  * Bits | Access | Reset | Description
7224  * :--------|:-------|:-------|:---------------------
7225  * [15:0] | RW | 0xffff | MAC Address4 [47:32]
7226  * [23:16] | ??? | 0x0 | *UNDEFINED*
7227  * [24] | RW | 0x0 | Mask Byte Control
7228  * [25] | RW | 0x0 | Mask Byte Control
7229  * [26] | RW | 0x0 | Mask Byte Control
7230  * [27] | RW | 0x0 | Mask Byte Control
7231  * [28] | RW | 0x0 | Mask Byte Control
7232  * [29] | RW | 0x0 | Mask Byte Control
7233  * [30] | RW | 0x0 | Source Address
7234  * [31] | RW | 0x0 | Address Enable
7235  *
7236  */
7237 /*
7238  * Field : MAC Address4 [47:32] - addrhi
7239  *
7240  * This field contains the upper 16 bits (47:32) of the 5th 6-byte MAC address.
7241  *
7242  * Field Access Macros:
7243  *
7244  */
7245 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
7246 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_LSB 0
7247 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
7248 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_MSB 15
7249 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
7250 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_WIDTH 16
7251 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
7252 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET_MSK 0x0000ffff
7253 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
7254 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_CLR_MSK 0xffff0000
7255 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
7256 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_RESET 0xffff
7257 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI field value from a register. */
7258 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
7259 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value suitable for setting the register. */
7260 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
7261 
7262 /*
7263  * Field : Mask Byte Control - mbc_0
7264  *
7265  * This array of bits are mask control bits for comparison of each of the MAC
7266  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7267  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7268  * bit controls the masking of the bytes. You can filter a group of addresses
7269  * (known as group address filtering) by masking one or more bytes of the address.
7270  *
7271  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7272  *
7273  * Field Enumeration Values:
7274  *
7275  * Enum | Value | Description
7276  * :---------------------------------------------|:------|:------------------------------------
7277  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7278  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7279  *
7280  * Field Access Macros:
7281  *
7282  */
7283 /*
7284  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
7285  *
7286  * Byte is unmasked (i.e. is compared)
7287  */
7288 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED 0x0
7289 /*
7290  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
7291  *
7292  * Byte is masked (i.e. not compared)
7293  */
7294 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED 0x1
7295 
7296 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
7297 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_LSB 24
7298 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
7299 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_MSB 24
7300 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
7301 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_WIDTH 1
7302 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
7303 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET_MSK 0x01000000
7304 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
7305 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_CLR_MSK 0xfeffffff
7306 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
7307 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_RESET 0x0
7308 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 field value from a register. */
7309 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
7310 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value suitable for setting the register. */
7311 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
7312 
7313 /*
7314  * Field : Mask Byte Control - mbc_1
7315  *
7316  * This array of bits are mask control bits for comparison of each of the MAC
7317  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7318  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7319  * bit controls the masking of the bytes. You can filter a group of addresses
7320  * (known as group address filtering) by masking one or more bytes of the address.
7321  *
7322  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7323  *
7324  * Field Enumeration Values:
7325  *
7326  * Enum | Value | Description
7327  * :---------------------------------------------|:------|:------------------------------------
7328  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7329  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7330  *
7331  * Field Access Macros:
7332  *
7333  */
7334 /*
7335  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
7336  *
7337  * Byte is unmasked (i.e. is compared)
7338  */
7339 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED 0x0
7340 /*
7341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
7342  *
7343  * Byte is masked (i.e. not compared)
7344  */
7345 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED 0x1
7346 
7347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
7348 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_LSB 25
7349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
7350 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_MSB 25
7351 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
7352 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_WIDTH 1
7353 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
7354 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET_MSK 0x02000000
7355 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
7356 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_CLR_MSK 0xfdffffff
7357 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
7358 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_RESET 0x0
7359 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 field value from a register. */
7360 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
7361 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value suitable for setting the register. */
7362 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
7363 
7364 /*
7365  * Field : Mask Byte Control - mbc_2
7366  *
7367  * This array of bits are mask control bits for comparison of each of the MAC
7368  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7369  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7370  * bit controls the masking of the bytes. You can filter a group of addresses
7371  * (known as group address filtering) by masking one or more bytes of the address.
7372  *
7373  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7374  *
7375  * Field Enumeration Values:
7376  *
7377  * Enum | Value | Description
7378  * :---------------------------------------------|:------|:------------------------------------
7379  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7380  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7381  *
7382  * Field Access Macros:
7383  *
7384  */
7385 /*
7386  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
7387  *
7388  * Byte is unmasked (i.e. is compared)
7389  */
7390 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED 0x0
7391 /*
7392  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
7393  *
7394  * Byte is masked (i.e. not compared)
7395  */
7396 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED 0x1
7397 
7398 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
7399 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_LSB 26
7400 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
7401 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_MSB 26
7402 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
7403 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_WIDTH 1
7404 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
7405 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET_MSK 0x04000000
7406 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
7407 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_CLR_MSK 0xfbffffff
7408 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
7409 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_RESET 0x0
7410 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 field value from a register. */
7411 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
7412 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value suitable for setting the register. */
7413 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
7414 
7415 /*
7416  * Field : Mask Byte Control - mbc_3
7417  *
7418  * This array of bits are mask control bits for comparison of each of the MAC
7419  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7420  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7421  * bit controls the masking of the bytes. You can filter a group of addresses
7422  * (known as group address filtering) by masking one or more bytes of the address.
7423  *
7424  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7425  *
7426  * Field Enumeration Values:
7427  *
7428  * Enum | Value | Description
7429  * :---------------------------------------------|:------|:------------------------------------
7430  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7431  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7432  *
7433  * Field Access Macros:
7434  *
7435  */
7436 /*
7437  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
7438  *
7439  * Byte is unmasked (i.e. is compared)
7440  */
7441 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED 0x0
7442 /*
7443  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
7444  *
7445  * Byte is masked (i.e. not compared)
7446  */
7447 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED 0x1
7448 
7449 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
7450 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_LSB 27
7451 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
7452 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_MSB 27
7453 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
7454 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_WIDTH 1
7455 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
7456 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET_MSK 0x08000000
7457 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
7458 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_CLR_MSK 0xf7ffffff
7459 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
7460 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_RESET 0x0
7461 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 field value from a register. */
7462 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
7463 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value suitable for setting the register. */
7464 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
7465 
7466 /*
7467  * Field : Mask Byte Control - mbc_4
7468  *
7469  * This array of bits are mask control bits for comparison of each of the MAC
7470  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7471  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7472  * bit controls the masking of the bytes. You can filter a group of addresses
7473  * (known as group address filtering) by masking one or more bytes of the address.
7474  *
7475  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7476  *
7477  * Field Enumeration Values:
7478  *
7479  * Enum | Value | Description
7480  * :---------------------------------------------|:------|:------------------------------------
7481  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7482  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7483  *
7484  * Field Access Macros:
7485  *
7486  */
7487 /*
7488  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
7489  *
7490  * Byte is unmasked (i.e. is compared)
7491  */
7492 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED 0x0
7493 /*
7494  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
7495  *
7496  * Byte is masked (i.e. not compared)
7497  */
7498 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED 0x1
7499 
7500 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
7501 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_LSB 28
7502 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
7503 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_MSB 28
7504 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
7505 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_WIDTH 1
7506 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
7507 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET_MSK 0x10000000
7508 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
7509 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_CLR_MSK 0xefffffff
7510 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
7511 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_RESET 0x0
7512 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 field value from a register. */
7513 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
7514 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value suitable for setting the register. */
7515 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
7516 
7517 /*
7518  * Field : Mask Byte Control - mbc_5
7519  *
7520  * This array of bits are mask control bits for comparison of each of the MAC
7521  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7522  * received DA or SA with the contents of MAC Address4 high and low registers. Each
7523  * bit controls the masking of the bytes. You can filter a group of addresses
7524  * (known as group address filtering) by masking one or more bytes of the address.
7525  *
7526  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7527  *
7528  * Field Enumeration Values:
7529  *
7530  * Enum | Value | Description
7531  * :---------------------------------------------|:------|:------------------------------------
7532  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7533  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7534  *
7535  * Field Access Macros:
7536  *
7537  */
7538 /*
7539  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
7540  *
7541  * Byte is unmasked (i.e. is compared)
7542  */
7543 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED 0x0
7544 /*
7545  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
7546  *
7547  * Byte is masked (i.e. not compared)
7548  */
7549 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED 0x1
7550 
7551 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
7552 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_LSB 29
7553 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
7554 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_MSB 29
7555 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
7556 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_WIDTH 1
7557 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
7558 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET_MSK 0x20000000
7559 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
7560 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_CLR_MSK 0xdfffffff
7561 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
7562 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_RESET 0x0
7563 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 field value from a register. */
7564 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
7565 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value suitable for setting the register. */
7566 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
7567 
7568 /*
7569  * Field : Source Address - sa
7570  *
7571  * When this bit is enabled, the MAC Address4[47:0] is used to compare with the SA
7572  * fields of the received frame. When this bit is disabled, the MAC Address4[47:0]
7573  * is used to compare with the DA fields of the received frame.
7574  *
7575  * Field Enumeration Values:
7576  *
7577  * Enum | Value | Description
7578  * :---------------------------------------|:------|:-----------------------------
7579  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
7580  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END | 0x1 | MAC address compare enabled
7581  *
7582  * Field Access Macros:
7583  *
7584  */
7585 /*
7586  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
7587  *
7588  * MAC address compare disabled
7589  */
7590 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD 0x0
7591 /*
7592  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
7593  *
7594  * MAC address compare enabled
7595  */
7596 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END 0x1
7597 
7598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
7599 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_LSB 30
7600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
7601 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_MSB 30
7602 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
7603 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_WIDTH 1
7604 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
7605 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET_MSK 0x40000000
7606 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
7607 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_CLR_MSK 0xbfffffff
7608 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
7609 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_RESET 0x0
7610 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA field value from a register. */
7611 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
7612 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value suitable for setting the register. */
7613 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
7614 
7615 /*
7616  * Field : Address Enable - ae
7617  *
7618  * When this bit is enabled, the address filter block uses the 5th MAC address for
7619  * perfect filtering. When this bit is disabled, the address filter block ignores
7620  * the address for filtering.
7621  *
7622  * Field Enumeration Values:
7623  *
7624  * Enum | Value | Description
7625  * :---------------------------------------|:------|:--------------------------------------
7626  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
7627  * ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
7628  *
7629  * Field Access Macros:
7630  *
7631  */
7632 /*
7633  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
7634  *
7635  * Second MAC address filtering disabled
7636  */
7637 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD 0x0
7638 /*
7639  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
7640  *
7641  * Second MAC address filtering enabled
7642  */
7643 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END 0x1
7644 
7645 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
7646 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_LSB 31
7647 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
7648 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_MSB 31
7649 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
7650 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_WIDTH 1
7651 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
7652 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET_MSK 0x80000000
7653 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
7654 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_CLR_MSK 0x7fffffff
7655 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
7656 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_RESET 0x0
7657 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE field value from a register. */
7658 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
7659 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value suitable for setting the register. */
7660 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
7661 
7662 #ifndef __ASSEMBLY__
7663 /*
7664  * WARNING: The C register and register group struct declarations are provided for
7665  * convenience and illustrative purposes. They should, however, be used with
7666  * caution as the C language standard provides no guarantees about the alignment or
7667  * atomicity of device memory accesses. The recommended practice for writing
7668  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7669  * alt_write_word() functions.
7670  *
7671  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH.
7672  */
7673 struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s
7674 {
7675  uint32_t addrhi : 16; /* MAC Address4 [47:32] */
7676  uint32_t : 8; /* *UNDEFINED* */
7677  uint32_t mbc_0 : 1; /* Mask Byte Control */
7678  uint32_t mbc_1 : 1; /* Mask Byte Control */
7679  uint32_t mbc_2 : 1; /* Mask Byte Control */
7680  uint32_t mbc_3 : 1; /* Mask Byte Control */
7681  uint32_t mbc_4 : 1; /* Mask Byte Control */
7682  uint32_t mbc_5 : 1; /* Mask Byte Control */
7683  uint32_t sa : 1; /* Source Address */
7684  uint32_t ae : 1; /* Address Enable */
7685 };
7686 
7687 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH. */
7688 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t;
7689 #endif /* __ASSEMBLY__ */
7690 
7691 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register from the beginning of the component. */
7692 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST 0x60
7693 /* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register. */
7694 #define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST))
7695 
7696 /*
7697  * Register : Register 25 (MAC Address4 Low Register) - MAC_Address4_Low
7698  *
7699  * The MAC Address4 Low register holds the lower 32 bits of the 5th 6-byte MAC
7700  * address of the station.
7701  *
7702  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
7703  * format.
7704  *
7705  * Register Layout
7706  *
7707  * Bits | Access | Reset | Description
7708  * :-------|:-------|:-----------|:--------------------
7709  * [31:0] | RW | 0xffffffff | MAC Address4 [31:0]
7710  *
7711  */
7712 /*
7713  * Field : MAC Address4 [31:0] - addrlo
7714  *
7715  * This field contains the lower 32 bits of the 5th 6-byte MAC address. The content
7716  * of this field is undefined until loaded by software after the initialization
7717  * process.
7718  *
7719  * Field Access Macros:
7720  *
7721  */
7722 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
7723 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_LSB 0
7724 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
7725 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_MSB 31
7726 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
7727 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_WIDTH 32
7728 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
7729 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET_MSK 0xffffffff
7730 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
7731 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_CLR_MSK 0x00000000
7732 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
7733 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_RESET 0xffffffff
7734 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO field value from a register. */
7735 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
7736 /* Produces a ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value suitable for setting the register. */
7737 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
7738 
7739 #ifndef __ASSEMBLY__
7740 /*
7741  * WARNING: The C register and register group struct declarations are provided for
7742  * convenience and illustrative purposes. They should, however, be used with
7743  * caution as the C language standard provides no guarantees about the alignment or
7744  * atomicity of device memory accesses. The recommended practice for writing
7745  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7746  * alt_write_word() functions.
7747  *
7748  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW.
7749  */
7750 struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s
7751 {
7752  uint32_t addrlo : 32; /* MAC Address4 [31:0] */
7753 };
7754 
7755 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW. */
7756 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s ALT_EMAC_GMAC_MAC_ADDR4_LOW_t;
7757 #endif /* __ASSEMBLY__ */
7758 
7759 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register from the beginning of the component. */
7760 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST 0x64
7761 /* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register. */
7762 #define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST))
7763 
7764 /*
7765  * Register : Register 26 (MAC Address5 High Register) - MAC_Address5_High
7766  *
7767  * The MAC Address5 High register holds the upper 16 bits of the 6th 6-byte MAC
7768  * address of the station. Because the MAC address registers are configured to be
7769  * double-synchronized to the (G)MII clock domains, the synchronization is
7770  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
7771  * endian mode) of the MAC Address5 Low Register are written. For proper
7772  * synchronization updates, the consecutive writes to this Address Low Register
7773  * should be performed after at least four clock cycles in the destination clock
7774  * domain.
7775  *
7776  * Note that all MAC Address High registers (except MAC Address0 High) have the
7777  * same format.
7778  *
7779  * Register Layout
7780  *
7781  * Bits | Access | Reset | Description
7782  * :--------|:-------|:-------|:---------------------
7783  * [15:0] | RW | 0xffff | MAC Address5 [47:32]
7784  * [23:16] | ??? | 0x0 | *UNDEFINED*
7785  * [24] | RW | 0x0 | Mask Byte Control
7786  * [25] | RW | 0x0 | Mask Byte Control
7787  * [26] | RW | 0x0 | Mask Byte Control
7788  * [27] | RW | 0x0 | Mask Byte Control
7789  * [28] | RW | 0x0 | Mask Byte Control
7790  * [29] | RW | 0x0 | Mask Byte Control
7791  * [30] | RW | 0x0 | Source Address
7792  * [31] | RW | 0x0 | Address Enable
7793  *
7794  */
7795 /*
7796  * Field : MAC Address5 [47:32] - addrhi
7797  *
7798  * This field contains the upper 16 bits (47:32) of the 6th 6-byte MAC address.
7799  *
7800  * Field Access Macros:
7801  *
7802  */
7803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
7804 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_LSB 0
7805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
7806 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_MSB 15
7807 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
7808 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_WIDTH 16
7809 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
7810 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET_MSK 0x0000ffff
7811 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
7812 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_CLR_MSK 0xffff0000
7813 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
7814 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_RESET 0xffff
7815 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI field value from a register. */
7816 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
7817 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value suitable for setting the register. */
7818 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
7819 
7820 /*
7821  * Field : Mask Byte Control - mbc_0
7822  *
7823  * This array of bits are mask control bits for comparison of each of the MAC
7824  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7825  * received DA or SA with the contents of MAC Address5 high and low registers. Each
7826  * bit controls the masking of the bytes. You can filter a group of addresses
7827  * (known as group address filtering) by masking one or more bytes of the address.
7828  *
7829  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7830  *
7831  * Field Enumeration Values:
7832  *
7833  * Enum | Value | Description
7834  * :---------------------------------------------|:------|:------------------------------------
7835  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7836  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7837  *
7838  * Field Access Macros:
7839  *
7840  */
7841 /*
7842  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
7843  *
7844  * Byte is unmasked (i.e. is compared)
7845  */
7846 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED 0x0
7847 /*
7848  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
7849  *
7850  * Byte is masked (i.e. not compared)
7851  */
7852 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED 0x1
7853 
7854 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
7855 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_LSB 24
7856 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
7857 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_MSB 24
7858 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
7859 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_WIDTH 1
7860 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
7861 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET_MSK 0x01000000
7862 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
7863 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_CLR_MSK 0xfeffffff
7864 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
7865 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_RESET 0x0
7866 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 field value from a register. */
7867 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
7868 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value suitable for setting the register. */
7869 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
7870 
7871 /*
7872  * Field : Mask Byte Control - mbc_1
7873  *
7874  * This array of bits are mask control bits for comparison of each of the MAC
7875  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7876  * received DA or SA with the contents of MAC Address5 high and low registers. Each
7877  * bit controls the masking of the bytes. You can filter a group of addresses
7878  * (known as group address filtering) by masking one or more bytes of the address.
7879  *
7880  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7881  *
7882  * Field Enumeration Values:
7883  *
7884  * Enum | Value | Description
7885  * :---------------------------------------------|:------|:------------------------------------
7886  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7887  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7888  *
7889  * Field Access Macros:
7890  *
7891  */
7892 /*
7893  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
7894  *
7895  * Byte is unmasked (i.e. is compared)
7896  */
7897 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED 0x0
7898 /*
7899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
7900  *
7901  * Byte is masked (i.e. not compared)
7902  */
7903 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED 0x1
7904 
7905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
7906 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_LSB 25
7907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
7908 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_MSB 25
7909 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
7910 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_WIDTH 1
7911 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
7912 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET_MSK 0x02000000
7913 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
7914 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_CLR_MSK 0xfdffffff
7915 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
7916 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_RESET 0x0
7917 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 field value from a register. */
7918 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
7919 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value suitable for setting the register. */
7920 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
7921 
7922 /*
7923  * Field : Mask Byte Control - mbc_2
7924  *
7925  * This array of bits are mask control bits for comparison of each of the MAC
7926  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7927  * received DA or SA with the contents of MAC Address5 high and low registers. Each
7928  * bit controls the masking of the bytes. You can filter a group of addresses
7929  * (known as group address filtering) by masking one or more bytes of the address.
7930  *
7931  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7932  *
7933  * Field Enumeration Values:
7934  *
7935  * Enum | Value | Description
7936  * :---------------------------------------------|:------|:------------------------------------
7937  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7938  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7939  *
7940  * Field Access Macros:
7941  *
7942  */
7943 /*
7944  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
7945  *
7946  * Byte is unmasked (i.e. is compared)
7947  */
7948 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED 0x0
7949 /*
7950  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
7951  *
7952  * Byte is masked (i.e. not compared)
7953  */
7954 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED 0x1
7955 
7956 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
7957 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_LSB 26
7958 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
7959 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_MSB 26
7960 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
7961 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_WIDTH 1
7962 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
7963 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET_MSK 0x04000000
7964 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
7965 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_CLR_MSK 0xfbffffff
7966 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
7967 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_RESET 0x0
7968 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 field value from a register. */
7969 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
7970 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value suitable for setting the register. */
7971 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
7972 
7973 /*
7974  * Field : Mask Byte Control - mbc_3
7975  *
7976  * This array of bits are mask control bits for comparison of each of the MAC
7977  * Address bytes. When masked, the MAC does not compare the corresponding byte of
7978  * received DA or SA with the contents of MAC Address5 high and low registers. Each
7979  * bit controls the masking of the bytes. You can filter a group of addresses
7980  * (known as group address filtering) by masking one or more bytes of the address.
7981  *
7982  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
7983  *
7984  * Field Enumeration Values:
7985  *
7986  * Enum | Value | Description
7987  * :---------------------------------------------|:------|:------------------------------------
7988  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
7989  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
7990  *
7991  * Field Access Macros:
7992  *
7993  */
7994 /*
7995  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
7996  *
7997  * Byte is unmasked (i.e. is compared)
7998  */
7999 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED 0x0
8000 /*
8001  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
8002  *
8003  * Byte is masked (i.e. not compared)
8004  */
8005 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED 0x1
8006 
8007 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
8008 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_LSB 27
8009 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
8010 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_MSB 27
8011 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
8012 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_WIDTH 1
8013 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
8014 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET_MSK 0x08000000
8015 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
8016 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_CLR_MSK 0xf7ffffff
8017 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
8018 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_RESET 0x0
8019 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 field value from a register. */
8020 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
8021 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value suitable for setting the register. */
8022 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
8023 
8024 /*
8025  * Field : Mask Byte Control - mbc_4
8026  *
8027  * This array of bits are mask control bits for comparison of each of the MAC
8028  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8029  * received DA or SA with the contents of MAC Address5 high and low registers. Each
8030  * bit controls the masking of the bytes. You can filter a group of addresses
8031  * (known as group address filtering) by masking one or more bytes of the address.
8032  *
8033  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8034  *
8035  * Field Enumeration Values:
8036  *
8037  * Enum | Value | Description
8038  * :---------------------------------------------|:------|:------------------------------------
8039  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8040  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8041  *
8042  * Field Access Macros:
8043  *
8044  */
8045 /*
8046  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
8047  *
8048  * Byte is unmasked (i.e. is compared)
8049  */
8050 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED 0x0
8051 /*
8052  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
8053  *
8054  * Byte is masked (i.e. not compared)
8055  */
8056 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED 0x1
8057 
8058 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
8059 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_LSB 28
8060 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
8061 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_MSB 28
8062 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
8063 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_WIDTH 1
8064 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
8065 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET_MSK 0x10000000
8066 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
8067 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_CLR_MSK 0xefffffff
8068 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
8069 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_RESET 0x0
8070 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 field value from a register. */
8071 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
8072 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value suitable for setting the register. */
8073 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
8074 
8075 /*
8076  * Field : Mask Byte Control - mbc_5
8077  *
8078  * This array of bits are mask control bits for comparison of each of the MAC
8079  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8080  * received DA or SA with the contents of MAC Address5 high and low registers. Each
8081  * bit controls the masking of the bytes. You can filter a group of addresses
8082  * (known as group address filtering) by masking one or more bytes of the address.
8083  *
8084  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8085  *
8086  * Field Enumeration Values:
8087  *
8088  * Enum | Value | Description
8089  * :---------------------------------------------|:------|:------------------------------------
8090  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8091  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8092  *
8093  * Field Access Macros:
8094  *
8095  */
8096 /*
8097  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
8098  *
8099  * Byte is unmasked (i.e. is compared)
8100  */
8101 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED 0x0
8102 /*
8103  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
8104  *
8105  * Byte is masked (i.e. not compared)
8106  */
8107 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED 0x1
8108 
8109 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
8110 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_LSB 29
8111 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
8112 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_MSB 29
8113 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
8114 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_WIDTH 1
8115 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
8116 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET_MSK 0x20000000
8117 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
8118 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_CLR_MSK 0xdfffffff
8119 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
8120 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_RESET 0x0
8121 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 field value from a register. */
8122 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
8123 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value suitable for setting the register. */
8124 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
8125 
8126 /*
8127  * Field : Source Address - sa
8128  *
8129  * When this bit is enabled, the MAC Address5[47:0] is used to compare with the SA
8130  * fields of the received frame. When this bit is disabled, the MAC Address5[47:0]
8131  * is used to compare with the DA fields of the received frame.
8132  *
8133  * Field Enumeration Values:
8134  *
8135  * Enum | Value | Description
8136  * :---------------------------------------|:------|:-----------------------------
8137  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
8138  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END | 0x1 | MAC address compare enabled
8139  *
8140  * Field Access Macros:
8141  *
8142  */
8143 /*
8144  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
8145  *
8146  * MAC address compare disabled
8147  */
8148 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD 0x0
8149 /*
8150  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
8151  *
8152  * MAC address compare enabled
8153  */
8154 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END 0x1
8155 
8156 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
8157 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_LSB 30
8158 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
8159 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_MSB 30
8160 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
8161 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_WIDTH 1
8162 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
8163 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET_MSK 0x40000000
8164 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
8165 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_CLR_MSK 0xbfffffff
8166 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
8167 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_RESET 0x0
8168 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA field value from a register. */
8169 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
8170 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value suitable for setting the register. */
8171 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
8172 
8173 /*
8174  * Field : Address Enable - ae
8175  *
8176  * When this bit is enabled, the address filter block uses the 6th MAC address for
8177  * perfect filtering. When this bit is disabled, the address filter block ignores
8178  * the address for filtering.
8179  *
8180  * Field Enumeration Values:
8181  *
8182  * Enum | Value | Description
8183  * :---------------------------------------|:------|:--------------------------------------
8184  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
8185  * ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
8186  *
8187  * Field Access Macros:
8188  *
8189  */
8190 /*
8191  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
8192  *
8193  * Second MAC address filtering disabled
8194  */
8195 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD 0x0
8196 /*
8197  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
8198  *
8199  * Second MAC address filtering enabled
8200  */
8201 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END 0x1
8202 
8203 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
8204 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_LSB 31
8205 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
8206 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_MSB 31
8207 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
8208 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_WIDTH 1
8209 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
8210 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET_MSK 0x80000000
8211 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
8212 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_CLR_MSK 0x7fffffff
8213 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
8214 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_RESET 0x0
8215 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE field value from a register. */
8216 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
8217 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value suitable for setting the register. */
8218 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
8219 
8220 #ifndef __ASSEMBLY__
8221 /*
8222  * WARNING: The C register and register group struct declarations are provided for
8223  * convenience and illustrative purposes. They should, however, be used with
8224  * caution as the C language standard provides no guarantees about the alignment or
8225  * atomicity of device memory accesses. The recommended practice for writing
8226  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8227  * alt_write_word() functions.
8228  *
8229  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH.
8230  */
8231 struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s
8232 {
8233  uint32_t addrhi : 16; /* MAC Address5 [47:32] */
8234  uint32_t : 8; /* *UNDEFINED* */
8235  uint32_t mbc_0 : 1; /* Mask Byte Control */
8236  uint32_t mbc_1 : 1; /* Mask Byte Control */
8237  uint32_t mbc_2 : 1; /* Mask Byte Control */
8238  uint32_t mbc_3 : 1; /* Mask Byte Control */
8239  uint32_t mbc_4 : 1; /* Mask Byte Control */
8240  uint32_t mbc_5 : 1; /* Mask Byte Control */
8241  uint32_t sa : 1; /* Source Address */
8242  uint32_t ae : 1; /* Address Enable */
8243 };
8244 
8245 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH. */
8246 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t;
8247 #endif /* __ASSEMBLY__ */
8248 
8249 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register from the beginning of the component. */
8250 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST 0x68
8251 /* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register. */
8252 #define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST))
8253 
8254 /*
8255  * Register : Register 27 (MAC Address5 Low Register) - MAC_Address5_Low
8256  *
8257  * The MAC Address5 Low register holds the lower 32 bits of the 6th 6-byte MAC
8258  * address of the station.
8259  *
8260  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
8261  * format.
8262  *
8263  * Register Layout
8264  *
8265  * Bits | Access | Reset | Description
8266  * :-------|:-------|:-----------|:--------------------
8267  * [31:0] | RW | 0xffffffff | MAC Address5 [31:0]
8268  *
8269  */
8270 /*
8271  * Field : MAC Address5 [31:0] - addrlo
8272  *
8273  * This field contains the lower 32 bits of the 6th 6-byte MAC address. The content
8274  * of this field is undefined until loaded by software after the initialization
8275  * process.
8276  *
8277  * Field Access Macros:
8278  *
8279  */
8280 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
8281 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_LSB 0
8282 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
8283 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_MSB 31
8284 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
8285 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_WIDTH 32
8286 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
8287 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET_MSK 0xffffffff
8288 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
8289 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_CLR_MSK 0x00000000
8290 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
8291 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_RESET 0xffffffff
8292 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO field value from a register. */
8293 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
8294 /* Produces a ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value suitable for setting the register. */
8295 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
8296 
8297 #ifndef __ASSEMBLY__
8298 /*
8299  * WARNING: The C register and register group struct declarations are provided for
8300  * convenience and illustrative purposes. They should, however, be used with
8301  * caution as the C language standard provides no guarantees about the alignment or
8302  * atomicity of device memory accesses. The recommended practice for writing
8303  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8304  * alt_write_word() functions.
8305  *
8306  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW.
8307  */
8308 struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s
8309 {
8310  uint32_t addrlo : 32; /* MAC Address5 [31:0] */
8311 };
8312 
8313 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW. */
8314 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s ALT_EMAC_GMAC_MAC_ADDR5_LOW_t;
8315 #endif /* __ASSEMBLY__ */
8316 
8317 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register from the beginning of the component. */
8318 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST 0x6c
8319 /* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register. */
8320 #define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST))
8321 
8322 /*
8323  * Register : Register 28 (MAC Address6 High Register) - MAC_Address6_High
8324  *
8325  * The MAC Address6 High register holds the upper 16 bits of the 7th 6-byte MAC
8326  * address of the station. Because the MAC address registers are configured to be
8327  * double-synchronized to the (G)MII clock domains, the synchronization is
8328  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
8329  * endian mode) of the MAC Address6 Low Register are written. For proper
8330  * synchronization updates, the consecutive writes to this Address Low Register
8331  * should be performed after at least four clock cycles in the destination clock
8332  * domain.
8333  *
8334  * Note that all MAC Address High registers (except MAC Address0 High) have the
8335  * same format.
8336  *
8337  * Register Layout
8338  *
8339  * Bits | Access | Reset | Description
8340  * :--------|:-------|:-------|:---------------------
8341  * [15:0] | RW | 0xffff | MAC Address6 [47:32]
8342  * [23:16] | ??? | 0x0 | *UNDEFINED*
8343  * [24] | RW | 0x0 | Mask Byte Control
8344  * [25] | RW | 0x0 | Mask Byte Control
8345  * [26] | RW | 0x0 | Mask Byte Control
8346  * [27] | RW | 0x0 | Mask Byte Control
8347  * [28] | RW | 0x0 | Mask Byte Control
8348  * [29] | RW | 0x0 | Mask Byte Control
8349  * [30] | RW | 0x0 | Source Address
8350  * [31] | RW | 0x0 | Address Enable
8351  *
8352  */
8353 /*
8354  * Field : MAC Address6 [47:32] - addrhi
8355  *
8356  * This field contains the upper 16 bits (47:32) of the 7th 6-byte MAC address.
8357  *
8358  * Field Access Macros:
8359  *
8360  */
8361 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
8362 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_LSB 0
8363 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
8364 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_MSB 15
8365 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
8366 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_WIDTH 16
8367 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
8368 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET_MSK 0x0000ffff
8369 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
8370 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_CLR_MSK 0xffff0000
8371 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
8372 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_RESET 0xffff
8373 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI field value from a register. */
8374 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
8375 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value suitable for setting the register. */
8376 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
8377 
8378 /*
8379  * Field : Mask Byte Control - mbc_0
8380  *
8381  * This array of bits are mask control bits for comparison of each of the MAC
8382  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8383  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8384  * bit controls the masking of the bytes. You can filter a group of addresses
8385  * (known as group address filtering) by masking one or more bytes of the address.
8386  *
8387  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8388  *
8389  * Field Enumeration Values:
8390  *
8391  * Enum | Value | Description
8392  * :---------------------------------------------|:------|:------------------------------------
8393  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8394  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8395  *
8396  * Field Access Macros:
8397  *
8398  */
8399 /*
8400  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
8401  *
8402  * Byte is unmasked (i.e. is compared)
8403  */
8404 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED 0x0
8405 /*
8406  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
8407  *
8408  * Byte is masked (i.e. not compared)
8409  */
8410 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED 0x1
8411 
8412 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
8413 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_LSB 24
8414 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
8415 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_MSB 24
8416 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
8417 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_WIDTH 1
8418 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
8419 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET_MSK 0x01000000
8420 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
8421 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_CLR_MSK 0xfeffffff
8422 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
8423 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_RESET 0x0
8424 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 field value from a register. */
8425 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
8426 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value suitable for setting the register. */
8427 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
8428 
8429 /*
8430  * Field : Mask Byte Control - mbc_1
8431  *
8432  * This array of bits are mask control bits for comparison of each of the MAC
8433  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8434  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8435  * bit controls the masking of the bytes. You can filter a group of addresses
8436  * (known as group address filtering) by masking one or more bytes of the address.
8437  *
8438  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8439  *
8440  * Field Enumeration Values:
8441  *
8442  * Enum | Value | Description
8443  * :---------------------------------------------|:------|:------------------------------------
8444  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8445  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8446  *
8447  * Field Access Macros:
8448  *
8449  */
8450 /*
8451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
8452  *
8453  * Byte is unmasked (i.e. is compared)
8454  */
8455 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED 0x0
8456 /*
8457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
8458  *
8459  * Byte is masked (i.e. not compared)
8460  */
8461 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED 0x1
8462 
8463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
8464 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_LSB 25
8465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
8466 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_MSB 25
8467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
8468 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_WIDTH 1
8469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
8470 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET_MSK 0x02000000
8471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
8472 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_CLR_MSK 0xfdffffff
8473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
8474 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_RESET 0x0
8475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 field value from a register. */
8476 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
8477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value suitable for setting the register. */
8478 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
8479 
8480 /*
8481  * Field : Mask Byte Control - mbc_2
8482  *
8483  * This array of bits are mask control bits for comparison of each of the MAC
8484  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8485  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8486  * bit controls the masking of the bytes. You can filter a group of addresses
8487  * (known as group address filtering) by masking one or more bytes of the address.
8488  *
8489  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8490  *
8491  * Field Enumeration Values:
8492  *
8493  * Enum | Value | Description
8494  * :---------------------------------------------|:------|:------------------------------------
8495  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8496  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8497  *
8498  * Field Access Macros:
8499  *
8500  */
8501 /*
8502  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
8503  *
8504  * Byte is unmasked (i.e. is compared)
8505  */
8506 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED 0x0
8507 /*
8508  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
8509  *
8510  * Byte is masked (i.e. not compared)
8511  */
8512 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED 0x1
8513 
8514 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
8515 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_LSB 26
8516 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
8517 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_MSB 26
8518 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
8519 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_WIDTH 1
8520 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
8521 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET_MSK 0x04000000
8522 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
8523 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_CLR_MSK 0xfbffffff
8524 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
8525 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_RESET 0x0
8526 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 field value from a register. */
8527 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
8528 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value suitable for setting the register. */
8529 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
8530 
8531 /*
8532  * Field : Mask Byte Control - mbc_3
8533  *
8534  * This array of bits are mask control bits for comparison of each of the MAC
8535  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8536  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8537  * bit controls the masking of the bytes. You can filter a group of addresses
8538  * (known as group address filtering) by masking one or more bytes of the address.
8539  *
8540  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8541  *
8542  * Field Enumeration Values:
8543  *
8544  * Enum | Value | Description
8545  * :---------------------------------------------|:------|:------------------------------------
8546  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8547  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8548  *
8549  * Field Access Macros:
8550  *
8551  */
8552 /*
8553  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
8554  *
8555  * Byte is unmasked (i.e. is compared)
8556  */
8557 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED 0x0
8558 /*
8559  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
8560  *
8561  * Byte is masked (i.e. not compared)
8562  */
8563 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED 0x1
8564 
8565 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
8566 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_LSB 27
8567 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
8568 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_MSB 27
8569 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
8570 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_WIDTH 1
8571 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
8572 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET_MSK 0x08000000
8573 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
8574 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_CLR_MSK 0xf7ffffff
8575 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
8576 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_RESET 0x0
8577 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 field value from a register. */
8578 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
8579 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value suitable for setting the register. */
8580 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
8581 
8582 /*
8583  * Field : Mask Byte Control - mbc_4
8584  *
8585  * This array of bits are mask control bits for comparison of each of the MAC
8586  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8587  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8588  * bit controls the masking of the bytes. You can filter a group of addresses
8589  * (known as group address filtering) by masking one or more bytes of the address.
8590  *
8591  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8592  *
8593  * Field Enumeration Values:
8594  *
8595  * Enum | Value | Description
8596  * :---------------------------------------------|:------|:------------------------------------
8597  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8598  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8599  *
8600  * Field Access Macros:
8601  *
8602  */
8603 /*
8604  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
8605  *
8606  * Byte is unmasked (i.e. is compared)
8607  */
8608 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED 0x0
8609 /*
8610  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
8611  *
8612  * Byte is masked (i.e. not compared)
8613  */
8614 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED 0x1
8615 
8616 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
8617 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_LSB 28
8618 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
8619 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_MSB 28
8620 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
8621 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_WIDTH 1
8622 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
8623 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET_MSK 0x10000000
8624 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
8625 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_CLR_MSK 0xefffffff
8626 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
8627 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_RESET 0x0
8628 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 field value from a register. */
8629 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
8630 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value suitable for setting the register. */
8631 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
8632 
8633 /*
8634  * Field : Mask Byte Control - mbc_5
8635  *
8636  * This array of bits are mask control bits for comparison of each of the MAC
8637  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8638  * received DA or SA with the contents of MAC Address6 high and low registers. Each
8639  * bit controls the masking of the bytes. You can filter a group of addresses
8640  * (known as group address filtering) by masking one or more bytes of the address.
8641  *
8642  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8643  *
8644  * Field Enumeration Values:
8645  *
8646  * Enum | Value | Description
8647  * :---------------------------------------------|:------|:------------------------------------
8648  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8649  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8650  *
8651  * Field Access Macros:
8652  *
8653  */
8654 /*
8655  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
8656  *
8657  * Byte is unmasked (i.e. is compared)
8658  */
8659 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED 0x0
8660 /*
8661  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
8662  *
8663  * Byte is masked (i.e. not compared)
8664  */
8665 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED 0x1
8666 
8667 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
8668 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_LSB 29
8669 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
8670 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_MSB 29
8671 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
8672 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_WIDTH 1
8673 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
8674 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET_MSK 0x20000000
8675 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
8676 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_CLR_MSK 0xdfffffff
8677 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
8678 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_RESET 0x0
8679 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 field value from a register. */
8680 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
8681 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value suitable for setting the register. */
8682 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
8683 
8684 /*
8685  * Field : Source Address - sa
8686  *
8687  * When this bit is enabled, the MAC Address6[47:0] is used to compare with the SA
8688  * fields of the received frame. When this bit is disabled, the MAC Address6[47:0]
8689  * is used to compare with the DA fields of the received frame.
8690  *
8691  * Field Enumeration Values:
8692  *
8693  * Enum | Value | Description
8694  * :---------------------------------------|:------|:-----------------------------
8695  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
8696  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END | 0x1 | MAC address compare enabled
8697  *
8698  * Field Access Macros:
8699  *
8700  */
8701 /*
8702  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
8703  *
8704  * MAC address compare disabled
8705  */
8706 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD 0x0
8707 /*
8708  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
8709  *
8710  * MAC address compare enabled
8711  */
8712 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END 0x1
8713 
8714 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
8715 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_LSB 30
8716 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
8717 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_MSB 30
8718 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
8719 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_WIDTH 1
8720 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
8721 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET_MSK 0x40000000
8722 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
8723 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_CLR_MSK 0xbfffffff
8724 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
8725 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_RESET 0x0
8726 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA field value from a register. */
8727 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
8728 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value suitable for setting the register. */
8729 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
8730 
8731 /*
8732  * Field : Address Enable - ae
8733  *
8734  * When this bit is enabled, the address filter block uses the 7th MAC address for
8735  * perfect filtering. When this bit is disabled, the address filter block ignores
8736  * the address for filtering.
8737  *
8738  * Field Enumeration Values:
8739  *
8740  * Enum | Value | Description
8741  * :---------------------------------------|:------|:--------------------------------------
8742  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
8743  * ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
8744  *
8745  * Field Access Macros:
8746  *
8747  */
8748 /*
8749  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
8750  *
8751  * Second MAC address filtering disabled
8752  */
8753 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD 0x0
8754 /*
8755  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
8756  *
8757  * Second MAC address filtering enabled
8758  */
8759 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END 0x1
8760 
8761 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
8762 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_LSB 31
8763 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
8764 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_MSB 31
8765 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
8766 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_WIDTH 1
8767 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
8768 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET_MSK 0x80000000
8769 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
8770 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_CLR_MSK 0x7fffffff
8771 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
8772 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_RESET 0x0
8773 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE field value from a register. */
8774 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
8775 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value suitable for setting the register. */
8776 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
8777 
8778 #ifndef __ASSEMBLY__
8779 /*
8780  * WARNING: The C register and register group struct declarations are provided for
8781  * convenience and illustrative purposes. They should, however, be used with
8782  * caution as the C language standard provides no guarantees about the alignment or
8783  * atomicity of device memory accesses. The recommended practice for writing
8784  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8785  * alt_write_word() functions.
8786  *
8787  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH.
8788  */
8789 struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s
8790 {
8791  uint32_t addrhi : 16; /* MAC Address6 [47:32] */
8792  uint32_t : 8; /* *UNDEFINED* */
8793  uint32_t mbc_0 : 1; /* Mask Byte Control */
8794  uint32_t mbc_1 : 1; /* Mask Byte Control */
8795  uint32_t mbc_2 : 1; /* Mask Byte Control */
8796  uint32_t mbc_3 : 1; /* Mask Byte Control */
8797  uint32_t mbc_4 : 1; /* Mask Byte Control */
8798  uint32_t mbc_5 : 1; /* Mask Byte Control */
8799  uint32_t sa : 1; /* Source Address */
8800  uint32_t ae : 1; /* Address Enable */
8801 };
8802 
8803 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH. */
8804 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t;
8805 #endif /* __ASSEMBLY__ */
8806 
8807 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register from the beginning of the component. */
8808 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST 0x70
8809 /* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register. */
8810 #define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST))
8811 
8812 /*
8813  * Register : Register 29 (MAC Address6 Low Register) - MAC_Address6_Low
8814  *
8815  * The MAC Address6 Low register holds the lower 32 bits of the 7th 6-byte MAC
8816  * address of the station.
8817  *
8818  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
8819  * format.
8820  *
8821  * Register Layout
8822  *
8823  * Bits | Access | Reset | Description
8824  * :-------|:-------|:-----------|:--------------------
8825  * [31:0] | RW | 0xffffffff | MAC Address6 [31:0]
8826  *
8827  */
8828 /*
8829  * Field : MAC Address6 [31:0] - addrlo
8830  *
8831  * This field contains the lower 32 bits of the 7th 6-byte MAC address. The content
8832  * of this field is undefined until loaded by software after the initialization
8833  * process.
8834  *
8835  * Field Access Macros:
8836  *
8837  */
8838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
8839 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_LSB 0
8840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
8841 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_MSB 31
8842 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
8843 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_WIDTH 32
8844 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
8845 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET_MSK 0xffffffff
8846 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
8847 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_CLR_MSK 0x00000000
8848 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
8849 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_RESET 0xffffffff
8850 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO field value from a register. */
8851 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
8852 /* Produces a ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value suitable for setting the register. */
8853 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
8854 
8855 #ifndef __ASSEMBLY__
8856 /*
8857  * WARNING: The C register and register group struct declarations are provided for
8858  * convenience and illustrative purposes. They should, however, be used with
8859  * caution as the C language standard provides no guarantees about the alignment or
8860  * atomicity of device memory accesses. The recommended practice for writing
8861  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8862  * alt_write_word() functions.
8863  *
8864  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW.
8865  */
8866 struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s
8867 {
8868  uint32_t addrlo : 32; /* MAC Address6 [31:0] */
8869 };
8870 
8871 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW. */
8872 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s ALT_EMAC_GMAC_MAC_ADDR6_LOW_t;
8873 #endif /* __ASSEMBLY__ */
8874 
8875 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register from the beginning of the component. */
8876 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST 0x74
8877 /* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register. */
8878 #define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST))
8879 
8880 /*
8881  * Register : Register 30 (MAC Address7 High Register) - MAC_Address7_High
8882  *
8883  * The MAC Address7 High register holds the upper 16 bits of the 8th 6-byte MAC
8884  * address of the station. Because the MAC address registers are configured to be
8885  * double-synchronized to the (G)MII clock domains, the synchronization is
8886  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
8887  * endian mode) of the MAC Address7 Low Register are written. For proper
8888  * synchronization updates, the consecutive writes to this Address Low Register
8889  * should be performed after at least four clock cycles in the destination clock
8890  * domain.
8891  *
8892  * Note that all MAC Address High registers (except MAC Address0 High) have the
8893  * same format.
8894  *
8895  * Register Layout
8896  *
8897  * Bits | Access | Reset | Description
8898  * :--------|:-------|:-------|:---------------------
8899  * [15:0] | RW | 0xffff | MAC Address7 [47:32]
8900  * [23:16] | ??? | 0x0 | *UNDEFINED*
8901  * [24] | RW | 0x0 | Mask Byte Control
8902  * [25] | RW | 0x0 | Mask Byte Control
8903  * [26] | RW | 0x0 | Mask Byte Control
8904  * [27] | RW | 0x0 | Mask Byte Control
8905  * [28] | RW | 0x0 | Mask Byte Control
8906  * [29] | RW | 0x0 | Mask Byte Control
8907  * [30] | RW | 0x0 | Source Address
8908  * [31] | RW | 0x0 | Address Enable
8909  *
8910  */
8911 /*
8912  * Field : MAC Address7 [47:32] - addrhi
8913  *
8914  * This field contains the upper 16 bits (47:32) of the 8th 6-byte MAC address.
8915  *
8916  * Field Access Macros:
8917  *
8918  */
8919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
8920 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_LSB 0
8921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
8922 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_MSB 15
8923 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
8924 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_WIDTH 16
8925 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
8926 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET_MSK 0x0000ffff
8927 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
8928 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_CLR_MSK 0xffff0000
8929 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
8930 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_RESET 0xffff
8931 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI field value from a register. */
8932 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
8933 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value suitable for setting the register. */
8934 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
8935 
8936 /*
8937  * Field : Mask Byte Control - mbc_0
8938  *
8939  * This array of bits are mask control bits for comparison of each of the MAC
8940  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8941  * received DA or SA with the contents of MAC Address7 high and low registers. Each
8942  * bit controls the masking of the bytes. You can filter a group of addresses
8943  * (known as group address filtering) by masking one or more bytes of the address.
8944  *
8945  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8946  *
8947  * Field Enumeration Values:
8948  *
8949  * Enum | Value | Description
8950  * :---------------------------------------------|:------|:------------------------------------
8951  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
8952  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
8953  *
8954  * Field Access Macros:
8955  *
8956  */
8957 /*
8958  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
8959  *
8960  * Byte is unmasked (i.e. is compared)
8961  */
8962 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED 0x0
8963 /*
8964  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
8965  *
8966  * Byte is masked (i.e. not compared)
8967  */
8968 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED 0x1
8969 
8970 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
8971 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_LSB 24
8972 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
8973 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_MSB 24
8974 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
8975 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_WIDTH 1
8976 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
8977 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET_MSK 0x01000000
8978 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
8979 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_CLR_MSK 0xfeffffff
8980 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
8981 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_RESET 0x0
8982 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 field value from a register. */
8983 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
8984 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value suitable for setting the register. */
8985 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
8986 
8987 /*
8988  * Field : Mask Byte Control - mbc_1
8989  *
8990  * This array of bits are mask control bits for comparison of each of the MAC
8991  * Address bytes. When masked, the MAC does not compare the corresponding byte of
8992  * received DA or SA with the contents of MAC Address7 high and low registers. Each
8993  * bit controls the masking of the bytes. You can filter a group of addresses
8994  * (known as group address filtering) by masking one or more bytes of the address.
8995  *
8996  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
8997  *
8998  * Field Enumeration Values:
8999  *
9000  * Enum | Value | Description
9001  * :---------------------------------------------|:------|:------------------------------------
9002  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9003  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9004  *
9005  * Field Access Macros:
9006  *
9007  */
9008 /*
9009  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
9010  *
9011  * Byte is unmasked (i.e. is compared)
9012  */
9013 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED 0x0
9014 /*
9015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
9016  *
9017  * Byte is masked (i.e. not compared)
9018  */
9019 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED 0x1
9020 
9021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
9022 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_LSB 25
9023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
9024 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_MSB 25
9025 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
9026 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_WIDTH 1
9027 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
9028 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET_MSK 0x02000000
9029 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
9030 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_CLR_MSK 0xfdffffff
9031 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
9032 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_RESET 0x0
9033 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 field value from a register. */
9034 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
9035 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value suitable for setting the register. */
9036 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
9037 
9038 /*
9039  * Field : Mask Byte Control - mbc_2
9040  *
9041  * This array of bits are mask control bits for comparison of each of the MAC
9042  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9043  * received DA or SA with the contents of MAC Address7 high and low registers. Each
9044  * bit controls the masking of the bytes. You can filter a group of addresses
9045  * (known as group address filtering) by masking one or more bytes of the address.
9046  *
9047  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9048  *
9049  * Field Enumeration Values:
9050  *
9051  * Enum | Value | Description
9052  * :---------------------------------------------|:------|:------------------------------------
9053  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9054  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9055  *
9056  * Field Access Macros:
9057  *
9058  */
9059 /*
9060  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
9061  *
9062  * Byte is unmasked (i.e. is compared)
9063  */
9064 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED 0x0
9065 /*
9066  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
9067  *
9068  * Byte is masked (i.e. not compared)
9069  */
9070 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED 0x1
9071 
9072 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
9073 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_LSB 26
9074 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
9075 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_MSB 26
9076 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
9077 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_WIDTH 1
9078 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
9079 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET_MSK 0x04000000
9080 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
9081 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_CLR_MSK 0xfbffffff
9082 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
9083 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_RESET 0x0
9084 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 field value from a register. */
9085 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
9086 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value suitable for setting the register. */
9087 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
9088 
9089 /*
9090  * Field : Mask Byte Control - mbc_3
9091  *
9092  * This array of bits are mask control bits for comparison of each of the MAC
9093  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9094  * received DA or SA with the contents of MAC Address7 high and low registers. Each
9095  * bit controls the masking of the bytes. You can filter a group of addresses
9096  * (known as group address filtering) by masking one or more bytes of the address.
9097  *
9098  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9099  *
9100  * Field Enumeration Values:
9101  *
9102  * Enum | Value | Description
9103  * :---------------------------------------------|:------|:------------------------------------
9104  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9105  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9106  *
9107  * Field Access Macros:
9108  *
9109  */
9110 /*
9111  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
9112  *
9113  * Byte is unmasked (i.e. is compared)
9114  */
9115 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED 0x0
9116 /*
9117  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
9118  *
9119  * Byte is masked (i.e. not compared)
9120  */
9121 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED 0x1
9122 
9123 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
9124 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_LSB 27
9125 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
9126 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_MSB 27
9127 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
9128 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_WIDTH 1
9129 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
9130 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET_MSK 0x08000000
9131 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
9132 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_CLR_MSK 0xf7ffffff
9133 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
9134 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_RESET 0x0
9135 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 field value from a register. */
9136 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
9137 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value suitable for setting the register. */
9138 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
9139 
9140 /*
9141  * Field : Mask Byte Control - mbc_4
9142  *
9143  * This array of bits are mask control bits for comparison of each of the MAC
9144  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9145  * received DA or SA with the contents of MAC Address7 high and low registers. Each
9146  * bit controls the masking of the bytes. You can filter a group of addresses
9147  * (known as group address filtering) by masking one or more bytes of the address.
9148  *
9149  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9150  *
9151  * Field Enumeration Values:
9152  *
9153  * Enum | Value | Description
9154  * :---------------------------------------------|:------|:------------------------------------
9155  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9156  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9157  *
9158  * Field Access Macros:
9159  *
9160  */
9161 /*
9162  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
9163  *
9164  * Byte is unmasked (i.e. is compared)
9165  */
9166 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED 0x0
9167 /*
9168  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
9169  *
9170  * Byte is masked (i.e. not compared)
9171  */
9172 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED 0x1
9173 
9174 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
9175 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_LSB 28
9176 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
9177 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_MSB 28
9178 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
9179 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_WIDTH 1
9180 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
9181 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET_MSK 0x10000000
9182 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
9183 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_CLR_MSK 0xefffffff
9184 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
9185 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_RESET 0x0
9186 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 field value from a register. */
9187 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
9188 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value suitable for setting the register. */
9189 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
9190 
9191 /*
9192  * Field : Mask Byte Control - mbc_5
9193  *
9194  * This array of bits are mask control bits for comparison of each of the MAC
9195  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9196  * received DA or SA with the contents of MAC Address7 high and low registers. Each
9197  * bit controls the masking of the bytes. You can filter a group of addresses
9198  * (known as group address filtering) by masking one or more bytes of the address.
9199  *
9200  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9201  *
9202  * Field Enumeration Values:
9203  *
9204  * Enum | Value | Description
9205  * :---------------------------------------------|:------|:------------------------------------
9206  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9207  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9208  *
9209  * Field Access Macros:
9210  *
9211  */
9212 /*
9213  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
9214  *
9215  * Byte is unmasked (i.e. is compared)
9216  */
9217 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED 0x0
9218 /*
9219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
9220  *
9221  * Byte is masked (i.e. not compared)
9222  */
9223 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED 0x1
9224 
9225 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
9226 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_LSB 29
9227 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
9228 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_MSB 29
9229 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
9230 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_WIDTH 1
9231 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
9232 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET_MSK 0x20000000
9233 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
9234 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_CLR_MSK 0xdfffffff
9235 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
9236 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_RESET 0x0
9237 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 field value from a register. */
9238 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
9239 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value suitable for setting the register. */
9240 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
9241 
9242 /*
9243  * Field : Source Address - sa
9244  *
9245  * When this bit is enabled, the MAC Address7[47:0] is used to compare with the SA
9246  * fields of the received frame. When this bit is disabled, the MAC Address7[47:0]
9247  * is used to compare with the DA fields of the received frame.
9248  *
9249  * Field Enumeration Values:
9250  *
9251  * Enum | Value | Description
9252  * :---------------------------------------|:------|:-----------------------------
9253  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
9254  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END | 0x1 | MAC address compare enabled
9255  *
9256  * Field Access Macros:
9257  *
9258  */
9259 /*
9260  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
9261  *
9262  * MAC address compare disabled
9263  */
9264 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD 0x0
9265 /*
9266  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
9267  *
9268  * MAC address compare enabled
9269  */
9270 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END 0x1
9271 
9272 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
9273 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_LSB 30
9274 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
9275 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_MSB 30
9276 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
9277 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_WIDTH 1
9278 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
9279 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET_MSK 0x40000000
9280 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
9281 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_CLR_MSK 0xbfffffff
9282 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
9283 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_RESET 0x0
9284 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA field value from a register. */
9285 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
9286 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value suitable for setting the register. */
9287 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
9288 
9289 /*
9290  * Field : Address Enable - ae
9291  *
9292  * When this bit is enabled, the address filter block uses the 8th MAC address for
9293  * perfect filtering. When this bit is disabled, the address filter block ignores
9294  * the address for filtering.
9295  *
9296  * Field Enumeration Values:
9297  *
9298  * Enum | Value | Description
9299  * :---------------------------------------|:------|:--------------------------------------
9300  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
9301  * ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
9302  *
9303  * Field Access Macros:
9304  *
9305  */
9306 /*
9307  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
9308  *
9309  * Second MAC address filtering disabled
9310  */
9311 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD 0x0
9312 /*
9313  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
9314  *
9315  * Second MAC address filtering enabled
9316  */
9317 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END 0x1
9318 
9319 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
9320 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_LSB 31
9321 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
9322 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_MSB 31
9323 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
9324 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_WIDTH 1
9325 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
9326 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET_MSK 0x80000000
9327 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
9328 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_CLR_MSK 0x7fffffff
9329 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
9330 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_RESET 0x0
9331 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE field value from a register. */
9332 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
9333 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value suitable for setting the register. */
9334 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
9335 
9336 #ifndef __ASSEMBLY__
9337 /*
9338  * WARNING: The C register and register group struct declarations are provided for
9339  * convenience and illustrative purposes. They should, however, be used with
9340  * caution as the C language standard provides no guarantees about the alignment or
9341  * atomicity of device memory accesses. The recommended practice for writing
9342  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9343  * alt_write_word() functions.
9344  *
9345  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH.
9346  */
9347 struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s
9348 {
9349  uint32_t addrhi : 16; /* MAC Address7 [47:32] */
9350  uint32_t : 8; /* *UNDEFINED* */
9351  uint32_t mbc_0 : 1; /* Mask Byte Control */
9352  uint32_t mbc_1 : 1; /* Mask Byte Control */
9353  uint32_t mbc_2 : 1; /* Mask Byte Control */
9354  uint32_t mbc_3 : 1; /* Mask Byte Control */
9355  uint32_t mbc_4 : 1; /* Mask Byte Control */
9356  uint32_t mbc_5 : 1; /* Mask Byte Control */
9357  uint32_t sa : 1; /* Source Address */
9358  uint32_t ae : 1; /* Address Enable */
9359 };
9360 
9361 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH. */
9362 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t;
9363 #endif /* __ASSEMBLY__ */
9364 
9365 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register from the beginning of the component. */
9366 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST 0x78
9367 /* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register. */
9368 #define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST))
9369 
9370 /*
9371  * Register : Register 31 (MAC Address7 Low Register) - MAC_Address7_Low
9372  *
9373  * The MAC Address7 Low register holds the lower 32 bits of the 8th 6-byte MAC
9374  * address of the station.
9375  *
9376  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
9377  * format.
9378  *
9379  * Register Layout
9380  *
9381  * Bits | Access | Reset | Description
9382  * :-------|:-------|:-----------|:--------------------
9383  * [31:0] | RW | 0xffffffff | MAC Address7 [31:0]
9384  *
9385  */
9386 /*
9387  * Field : MAC Address7 [31:0] - addrlo
9388  *
9389  * This field contains the lower 32 bits of the 8th 6-byte MAC address. The content
9390  * of this field is undefined until loaded by software after the initialization
9391  * process.
9392  *
9393  * Field Access Macros:
9394  *
9395  */
9396 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
9397 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_LSB 0
9398 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
9399 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_MSB 31
9400 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
9401 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_WIDTH 32
9402 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
9403 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET_MSK 0xffffffff
9404 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
9405 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_CLR_MSK 0x00000000
9406 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
9407 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_RESET 0xffffffff
9408 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO field value from a register. */
9409 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
9410 /* Produces a ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value suitable for setting the register. */
9411 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
9412 
9413 #ifndef __ASSEMBLY__
9414 /*
9415  * WARNING: The C register and register group struct declarations are provided for
9416  * convenience and illustrative purposes. They should, however, be used with
9417  * caution as the C language standard provides no guarantees about the alignment or
9418  * atomicity of device memory accesses. The recommended practice for writing
9419  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9420  * alt_write_word() functions.
9421  *
9422  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW.
9423  */
9424 struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s
9425 {
9426  uint32_t addrlo : 32; /* MAC Address7 [31:0] */
9427 };
9428 
9429 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW. */
9430 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s ALT_EMAC_GMAC_MAC_ADDR7_LOW_t;
9431 #endif /* __ASSEMBLY__ */
9432 
9433 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register from the beginning of the component. */
9434 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST 0x7c
9435 /* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register. */
9436 #define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST))
9437 
9438 /*
9439  * Register : Register 32 (MAC Address8 High Register) - MAC_Address8_High
9440  *
9441  * The MAC Address8 High register holds the upper 16 bits of the 9th 6-byte MAC
9442  * address of the station. Because the MAC address registers are configured to be
9443  * double-synchronized to the (G)MII clock domains, the synchronization is
9444  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
9445  * endian mode) of the MAC Address8 Low Register are written. For proper
9446  * synchronization updates, the consecutive writes to this Address Low Register
9447  * should be performed after at least four clock cycles in the destination clock
9448  * domain.
9449  *
9450  * Note that all MAC Address High registers (except MAC Address0 High) have the
9451  * same format.
9452  *
9453  * Register Layout
9454  *
9455  * Bits | Access | Reset | Description
9456  * :--------|:-------|:-------|:---------------------
9457  * [15:0] | RW | 0xffff | MAC Address8 [47:32]
9458  * [23:16] | ??? | 0x0 | *UNDEFINED*
9459  * [24] | RW | 0x0 | Mask Byte Control
9460  * [25] | RW | 0x0 | Mask Byte Control
9461  * [26] | RW | 0x0 | Mask Byte Control
9462  * [27] | RW | 0x0 | Mask Byte Control
9463  * [28] | RW | 0x0 | Mask Byte Control
9464  * [29] | RW | 0x0 | Mask Byte Control
9465  * [30] | RW | 0x0 | Source Address
9466  * [31] | RW | 0x0 | Address Enable
9467  *
9468  */
9469 /*
9470  * Field : MAC Address8 [47:32] - addrhi
9471  *
9472  * This field contains the upper 16 bits (47:32) of the 9th 6-byte MAC address.
9473  *
9474  * Field Access Macros:
9475  *
9476  */
9477 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
9478 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_LSB 0
9479 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
9480 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_MSB 15
9481 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
9482 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_WIDTH 16
9483 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
9484 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET_MSK 0x0000ffff
9485 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
9486 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_CLR_MSK 0xffff0000
9487 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
9488 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_RESET 0xffff
9489 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI field value from a register. */
9490 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
9491 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value suitable for setting the register. */
9492 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
9493 
9494 /*
9495  * Field : Mask Byte Control - mbc_0
9496  *
9497  * This array of bits are mask control bits for comparison of each of the MAC
9498  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9499  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9500  * bit controls the masking of the bytes. You can filter a group of addresses
9501  * (known as group address filtering) by masking one or more bytes of the address.
9502  *
9503  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9504  *
9505  * Field Enumeration Values:
9506  *
9507  * Enum | Value | Description
9508  * :---------------------------------------------|:------|:------------------------------------
9509  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9510  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9511  *
9512  * Field Access Macros:
9513  *
9514  */
9515 /*
9516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
9517  *
9518  * Byte is unmasked (i.e. is compared)
9519  */
9520 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED 0x0
9521 /*
9522  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
9523  *
9524  * Byte is masked (i.e. not compared)
9525  */
9526 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED 0x1
9527 
9528 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
9529 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_LSB 24
9530 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
9531 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_MSB 24
9532 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
9533 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_WIDTH 1
9534 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
9535 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET_MSK 0x01000000
9536 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
9537 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_CLR_MSK 0xfeffffff
9538 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
9539 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_RESET 0x0
9540 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 field value from a register. */
9541 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
9542 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value suitable for setting the register. */
9543 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
9544 
9545 /*
9546  * Field : Mask Byte Control - mbc_1
9547  *
9548  * This array of bits are mask control bits for comparison of each of the MAC
9549  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9550  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9551  * bit controls the masking of the bytes. You can filter a group of addresses
9552  * (known as group address filtering) by masking one or more bytes of the address.
9553  *
9554  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9555  *
9556  * Field Enumeration Values:
9557  *
9558  * Enum | Value | Description
9559  * :---------------------------------------------|:------|:------------------------------------
9560  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9561  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9562  *
9563  * Field Access Macros:
9564  *
9565  */
9566 /*
9567  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
9568  *
9569  * Byte is unmasked (i.e. is compared)
9570  */
9571 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED 0x0
9572 /*
9573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
9574  *
9575  * Byte is masked (i.e. not compared)
9576  */
9577 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED 0x1
9578 
9579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
9580 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_LSB 25
9581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
9582 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_MSB 25
9583 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
9584 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_WIDTH 1
9585 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
9586 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET_MSK 0x02000000
9587 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
9588 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_CLR_MSK 0xfdffffff
9589 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
9590 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_RESET 0x0
9591 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 field value from a register. */
9592 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
9593 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value suitable for setting the register. */
9594 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
9595 
9596 /*
9597  * Field : Mask Byte Control - mbc_2
9598  *
9599  * This array of bits are mask control bits for comparison of each of the MAC
9600  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9601  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9602  * bit controls the masking of the bytes. You can filter a group of addresses
9603  * (known as group address filtering) by masking one or more bytes of the address.
9604  *
9605  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9606  *
9607  * Field Enumeration Values:
9608  *
9609  * Enum | Value | Description
9610  * :---------------------------------------------|:------|:------------------------------------
9611  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9612  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9613  *
9614  * Field Access Macros:
9615  *
9616  */
9617 /*
9618  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
9619  *
9620  * Byte is unmasked (i.e. is compared)
9621  */
9622 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED 0x0
9623 /*
9624  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
9625  *
9626  * Byte is masked (i.e. not compared)
9627  */
9628 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED 0x1
9629 
9630 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
9631 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_LSB 26
9632 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
9633 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_MSB 26
9634 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
9635 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_WIDTH 1
9636 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
9637 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET_MSK 0x04000000
9638 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
9639 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_CLR_MSK 0xfbffffff
9640 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
9641 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_RESET 0x0
9642 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 field value from a register. */
9643 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
9644 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value suitable for setting the register. */
9645 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
9646 
9647 /*
9648  * Field : Mask Byte Control - mbc_3
9649  *
9650  * This array of bits are mask control bits for comparison of each of the MAC
9651  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9652  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9653  * bit controls the masking of the bytes. You can filter a group of addresses
9654  * (known as group address filtering) by masking one or more bytes of the address.
9655  *
9656  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9657  *
9658  * Field Enumeration Values:
9659  *
9660  * Enum | Value | Description
9661  * :---------------------------------------------|:------|:------------------------------------
9662  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9663  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9664  *
9665  * Field Access Macros:
9666  *
9667  */
9668 /*
9669  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
9670  *
9671  * Byte is unmasked (i.e. is compared)
9672  */
9673 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED 0x0
9674 /*
9675  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
9676  *
9677  * Byte is masked (i.e. not compared)
9678  */
9679 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED 0x1
9680 
9681 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
9682 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_LSB 27
9683 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
9684 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_MSB 27
9685 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
9686 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_WIDTH 1
9687 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
9688 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET_MSK 0x08000000
9689 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
9690 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_CLR_MSK 0xf7ffffff
9691 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
9692 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_RESET 0x0
9693 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 field value from a register. */
9694 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
9695 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value suitable for setting the register. */
9696 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
9697 
9698 /*
9699  * Field : Mask Byte Control - mbc_4
9700  *
9701  * This array of bits are mask control bits for comparison of each of the MAC
9702  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9703  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9704  * bit controls the masking of the bytes. You can filter a group of addresses
9705  * (known as group address filtering) by masking one or more bytes of the address.
9706  *
9707  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9708  *
9709  * Field Enumeration Values:
9710  *
9711  * Enum | Value | Description
9712  * :---------------------------------------------|:------|:------------------------------------
9713  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9714  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9715  *
9716  * Field Access Macros:
9717  *
9718  */
9719 /*
9720  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
9721  *
9722  * Byte is unmasked (i.e. is compared)
9723  */
9724 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED 0x0
9725 /*
9726  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
9727  *
9728  * Byte is masked (i.e. not compared)
9729  */
9730 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED 0x1
9731 
9732 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
9733 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_LSB 28
9734 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
9735 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_MSB 28
9736 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
9737 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_WIDTH 1
9738 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
9739 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET_MSK 0x10000000
9740 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
9741 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_CLR_MSK 0xefffffff
9742 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
9743 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_RESET 0x0
9744 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 field value from a register. */
9745 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
9746 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value suitable for setting the register. */
9747 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
9748 
9749 /*
9750  * Field : Mask Byte Control - mbc_5
9751  *
9752  * This array of bits are mask control bits for comparison of each of the MAC
9753  * Address bytes. When masked, the MAC does not compare the corresponding byte of
9754  * received DA or SA with the contents of MAC Address8 high and low registers. Each
9755  * bit controls the masking of the bytes. You can filter a group of addresses
9756  * (known as group address filtering) by masking one or more bytes of the address.
9757  *
9758  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
9759  *
9760  * Field Enumeration Values:
9761  *
9762  * Enum | Value | Description
9763  * :---------------------------------------------|:------|:------------------------------------
9764  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
9765  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
9766  *
9767  * Field Access Macros:
9768  *
9769  */
9770 /*
9771  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
9772  *
9773  * Byte is unmasked (i.e. is compared)
9774  */
9775 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED 0x0
9776 /*
9777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
9778  *
9779  * Byte is masked (i.e. not compared)
9780  */
9781 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED 0x1
9782 
9783 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
9784 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_LSB 29
9785 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
9786 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_MSB 29
9787 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
9788 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_WIDTH 1
9789 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
9790 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET_MSK 0x20000000
9791 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
9792 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_CLR_MSK 0xdfffffff
9793 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
9794 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_RESET 0x0
9795 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 field value from a register. */
9796 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
9797 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value suitable for setting the register. */
9798 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
9799 
9800 /*
9801  * Field : Source Address - sa
9802  *
9803  * When this bit is enabled, the MAC Address8[47:0] is used to compare with the SA
9804  * fields of the received frame. When this bit is disabled, the MAC Address8[47:0]
9805  * is used to compare with the DA fields of the received frame.
9806  *
9807  * Field Enumeration Values:
9808  *
9809  * Enum | Value | Description
9810  * :---------------------------------------|:------|:-----------------------------
9811  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
9812  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END | 0x1 | MAC address compare enabled
9813  *
9814  * Field Access Macros:
9815  *
9816  */
9817 /*
9818  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
9819  *
9820  * MAC address compare disabled
9821  */
9822 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD 0x0
9823 /*
9824  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
9825  *
9826  * MAC address compare enabled
9827  */
9828 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END 0x1
9829 
9830 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
9831 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_LSB 30
9832 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
9833 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_MSB 30
9834 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
9835 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_WIDTH 1
9836 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
9837 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET_MSK 0x40000000
9838 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
9839 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_CLR_MSK 0xbfffffff
9840 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
9841 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_RESET 0x0
9842 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA field value from a register. */
9843 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
9844 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value suitable for setting the register. */
9845 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
9846 
9847 /*
9848  * Field : Address Enable - ae
9849  *
9850  * When this bit is enabled, the address filter block uses the 9th MAC address for
9851  * perfect filtering. When this bit is disabled, the address filter block ignores
9852  * the address for filtering.
9853  *
9854  * Field Enumeration Values:
9855  *
9856  * Enum | Value | Description
9857  * :---------------------------------------|:------|:--------------------------------------
9858  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
9859  * ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
9860  *
9861  * Field Access Macros:
9862  *
9863  */
9864 /*
9865  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
9866  *
9867  * Second MAC address filtering disabled
9868  */
9869 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD 0x0
9870 /*
9871  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
9872  *
9873  * Second MAC address filtering enabled
9874  */
9875 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END 0x1
9876 
9877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
9878 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_LSB 31
9879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
9880 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_MSB 31
9881 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
9882 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_WIDTH 1
9883 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
9884 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET_MSK 0x80000000
9885 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
9886 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_CLR_MSK 0x7fffffff
9887 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
9888 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_RESET 0x0
9889 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE field value from a register. */
9890 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
9891 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value suitable for setting the register. */
9892 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
9893 
9894 #ifndef __ASSEMBLY__
9895 /*
9896  * WARNING: The C register and register group struct declarations are provided for
9897  * convenience and illustrative purposes. They should, however, be used with
9898  * caution as the C language standard provides no guarantees about the alignment or
9899  * atomicity of device memory accesses. The recommended practice for writing
9900  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9901  * alt_write_word() functions.
9902  *
9903  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH.
9904  */
9905 struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s
9906 {
9907  uint32_t addrhi : 16; /* MAC Address8 [47:32] */
9908  uint32_t : 8; /* *UNDEFINED* */
9909  uint32_t mbc_0 : 1; /* Mask Byte Control */
9910  uint32_t mbc_1 : 1; /* Mask Byte Control */
9911  uint32_t mbc_2 : 1; /* Mask Byte Control */
9912  uint32_t mbc_3 : 1; /* Mask Byte Control */
9913  uint32_t mbc_4 : 1; /* Mask Byte Control */
9914  uint32_t mbc_5 : 1; /* Mask Byte Control */
9915  uint32_t sa : 1; /* Source Address */
9916  uint32_t ae : 1; /* Address Enable */
9917 };
9918 
9919 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH. */
9920 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t;
9921 #endif /* __ASSEMBLY__ */
9922 
9923 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register from the beginning of the component. */
9924 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST 0x80
9925 /* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register. */
9926 #define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST))
9927 
9928 /*
9929  * Register : Register 33 (MAC Address8 Low Register) - MAC_Address8_Low
9930  *
9931  * The MAC Address8 Low register holds the lower 32 bits of the 9th 6-byte MAC
9932  * address of the station.
9933  *
9934  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
9935  * format.
9936  *
9937  * Register Layout
9938  *
9939  * Bits | Access | Reset | Description
9940  * :-------|:-------|:-----------|:--------------------
9941  * [31:0] | RW | 0xffffffff | MAC Address8 [31:0]
9942  *
9943  */
9944 /*
9945  * Field : MAC Address8 [31:0] - addrlo
9946  *
9947  * This field contains the lower 32 bits of the 9th 6-byte MAC address. The content
9948  * of this field is undefined until loaded by software after the initialization
9949  * process.
9950  *
9951  * Field Access Macros:
9952  *
9953  */
9954 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
9955 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_LSB 0
9956 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
9957 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_MSB 31
9958 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
9959 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_WIDTH 32
9960 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
9961 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET_MSK 0xffffffff
9962 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
9963 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_CLR_MSK 0x00000000
9964 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
9965 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_RESET 0xffffffff
9966 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO field value from a register. */
9967 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
9968 /* Produces a ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value suitable for setting the register. */
9969 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
9970 
9971 #ifndef __ASSEMBLY__
9972 /*
9973  * WARNING: The C register and register group struct declarations are provided for
9974  * convenience and illustrative purposes. They should, however, be used with
9975  * caution as the C language standard provides no guarantees about the alignment or
9976  * atomicity of device memory accesses. The recommended practice for writing
9977  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9978  * alt_write_word() functions.
9979  *
9980  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW.
9981  */
9982 struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s
9983 {
9984  uint32_t addrlo : 32; /* MAC Address8 [31:0] */
9985 };
9986 
9987 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW. */
9988 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s ALT_EMAC_GMAC_MAC_ADDR8_LOW_t;
9989 #endif /* __ASSEMBLY__ */
9990 
9991 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register from the beginning of the component. */
9992 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST 0x84
9993 /* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register. */
9994 #define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST))
9995 
9996 /*
9997  * Register : Register 34 (MAC Address9 High Register) - MAC_Address9_High
9998  *
9999  * The MAC Address9 High register holds the upper 16 bits of the 10th 6-byte MAC
10000  * address of the station. Because the MAC address registers are configured to be
10001  * double-synchronized to the (G)MII clock domains, the synchronization is
10002  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
10003  * endian mode) of the MAC Address9 Low Register are written. For proper
10004  * synchronization updates, the consecutive writes to this Address Low Register
10005  * should be performed after at least four clock cycles in the destination clock
10006  * domain.
10007  *
10008  * Note that all MAC Address High registers (except MAC Address0 High) have the
10009  * same format.
10010  *
10011  * Register Layout
10012  *
10013  * Bits | Access | Reset | Description
10014  * :--------|:-------|:-------|:---------------------
10015  * [15:0] | RW | 0xffff | MAC Address9 [47:32]
10016  * [23:16] | ??? | 0x0 | *UNDEFINED*
10017  * [24] | RW | 0x0 | Mask Byte Control
10018  * [25] | RW | 0x0 | Mask Byte Control
10019  * [26] | RW | 0x0 | Mask Byte Control
10020  * [27] | RW | 0x0 | Mask Byte Control
10021  * [28] | RW | 0x0 | Mask Byte Control
10022  * [29] | RW | 0x0 | Mask Byte Control
10023  * [30] | RW | 0x0 | Source Address
10024  * [31] | RW | 0x0 | Address Enable
10025  *
10026  */
10027 /*
10028  * Field : MAC Address9 [47:32] - addrhi
10029  *
10030  * This field contains the upper 16 bits (47:32) of the 10th 6-byte MAC address.
10031  *
10032  * Field Access Macros:
10033  *
10034  */
10035 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
10036 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_LSB 0
10037 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
10038 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_MSB 15
10039 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
10040 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_WIDTH 16
10041 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
10042 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET_MSK 0x0000ffff
10043 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
10044 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_CLR_MSK 0xffff0000
10045 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
10046 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_RESET 0xffff
10047 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI field value from a register. */
10048 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
10049 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value suitable for setting the register. */
10050 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
10051 
10052 /*
10053  * Field : Mask Byte Control - mbc_0
10054  *
10055  * This array of bits are mask control bits for comparison of each of the MAC
10056  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10057  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10058  * bit controls the masking of the bytes. You can filter a group of addresses
10059  * (known as group address filtering) by masking one or more bytes of the address.
10060  *
10061  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10062  *
10063  * Field Enumeration Values:
10064  *
10065  * Enum | Value | Description
10066  * :---------------------------------------------|:------|:------------------------------------
10067  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10068  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10069  *
10070  * Field Access Macros:
10071  *
10072  */
10073 /*
10074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
10075  *
10076  * Byte is unmasked (i.e. is compared)
10077  */
10078 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED 0x0
10079 /*
10080  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
10081  *
10082  * Byte is masked (i.e. not compared)
10083  */
10084 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED 0x1
10085 
10086 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
10087 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_LSB 24
10088 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
10089 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_MSB 24
10090 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
10091 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_WIDTH 1
10092 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
10093 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET_MSK 0x01000000
10094 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
10095 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_CLR_MSK 0xfeffffff
10096 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
10097 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_RESET 0x0
10098 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 field value from a register. */
10099 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
10100 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value suitable for setting the register. */
10101 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
10102 
10103 /*
10104  * Field : Mask Byte Control - mbc_1
10105  *
10106  * This array of bits are mask control bits for comparison of each of the MAC
10107  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10108  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10109  * bit controls the masking of the bytes. You can filter a group of addresses
10110  * (known as group address filtering) by masking one or more bytes of the address.
10111  *
10112  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10113  *
10114  * Field Enumeration Values:
10115  *
10116  * Enum | Value | Description
10117  * :---------------------------------------------|:------|:------------------------------------
10118  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10119  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10120  *
10121  * Field Access Macros:
10122  *
10123  */
10124 /*
10125  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
10126  *
10127  * Byte is unmasked (i.e. is compared)
10128  */
10129 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED 0x0
10130 /*
10131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
10132  *
10133  * Byte is masked (i.e. not compared)
10134  */
10135 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED 0x1
10136 
10137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
10138 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_LSB 25
10139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
10140 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_MSB 25
10141 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
10142 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_WIDTH 1
10143 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
10144 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET_MSK 0x02000000
10145 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
10146 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_CLR_MSK 0xfdffffff
10147 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
10148 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_RESET 0x0
10149 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 field value from a register. */
10150 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
10151 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value suitable for setting the register. */
10152 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
10153 
10154 /*
10155  * Field : Mask Byte Control - mbc_2
10156  *
10157  * This array of bits are mask control bits for comparison of each of the MAC
10158  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10159  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10160  * bit controls the masking of the bytes. You can filter a group of addresses
10161  * (known as group address filtering) by masking one or more bytes of the address.
10162  *
10163  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10164  *
10165  * Field Enumeration Values:
10166  *
10167  * Enum | Value | Description
10168  * :---------------------------------------------|:------|:------------------------------------
10169  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10170  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10171  *
10172  * Field Access Macros:
10173  *
10174  */
10175 /*
10176  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
10177  *
10178  * Byte is unmasked (i.e. is compared)
10179  */
10180 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED 0x0
10181 /*
10182  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
10183  *
10184  * Byte is masked (i.e. not compared)
10185  */
10186 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED 0x1
10187 
10188 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
10189 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_LSB 26
10190 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
10191 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_MSB 26
10192 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
10193 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_WIDTH 1
10194 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
10195 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET_MSK 0x04000000
10196 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
10197 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_CLR_MSK 0xfbffffff
10198 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
10199 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_RESET 0x0
10200 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 field value from a register. */
10201 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
10202 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value suitable for setting the register. */
10203 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
10204 
10205 /*
10206  * Field : Mask Byte Control - mbc_3
10207  *
10208  * This array of bits are mask control bits for comparison of each of the MAC
10209  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10210  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10211  * bit controls the masking of the bytes. You can filter a group of addresses
10212  * (known as group address filtering) by masking one or more bytes of the address.
10213  *
10214  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10215  *
10216  * Field Enumeration Values:
10217  *
10218  * Enum | Value | Description
10219  * :---------------------------------------------|:------|:------------------------------------
10220  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10221  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10222  *
10223  * Field Access Macros:
10224  *
10225  */
10226 /*
10227  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
10228  *
10229  * Byte is unmasked (i.e. is compared)
10230  */
10231 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED 0x0
10232 /*
10233  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
10234  *
10235  * Byte is masked (i.e. not compared)
10236  */
10237 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED 0x1
10238 
10239 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
10240 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_LSB 27
10241 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
10242 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_MSB 27
10243 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
10244 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_WIDTH 1
10245 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
10246 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET_MSK 0x08000000
10247 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
10248 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_CLR_MSK 0xf7ffffff
10249 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
10250 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_RESET 0x0
10251 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 field value from a register. */
10252 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
10253 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value suitable for setting the register. */
10254 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
10255 
10256 /*
10257  * Field : Mask Byte Control - mbc_4
10258  *
10259  * This array of bits are mask control bits for comparison of each of the MAC
10260  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10261  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10262  * bit controls the masking of the bytes. You can filter a group of addresses
10263  * (known as group address filtering) by masking one or more bytes of the address.
10264  *
10265  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10266  *
10267  * Field Enumeration Values:
10268  *
10269  * Enum | Value | Description
10270  * :---------------------------------------------|:------|:------------------------------------
10271  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10272  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10273  *
10274  * Field Access Macros:
10275  *
10276  */
10277 /*
10278  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
10279  *
10280  * Byte is unmasked (i.e. is compared)
10281  */
10282 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED 0x0
10283 /*
10284  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
10285  *
10286  * Byte is masked (i.e. not compared)
10287  */
10288 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED 0x1
10289 
10290 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
10291 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_LSB 28
10292 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
10293 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_MSB 28
10294 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
10295 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_WIDTH 1
10296 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
10297 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET_MSK 0x10000000
10298 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
10299 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_CLR_MSK 0xefffffff
10300 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
10301 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_RESET 0x0
10302 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 field value from a register. */
10303 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
10304 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value suitable for setting the register. */
10305 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
10306 
10307 /*
10308  * Field : Mask Byte Control - mbc_5
10309  *
10310  * This array of bits are mask control bits for comparison of each of the MAC
10311  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10312  * received DA or SA with the contents of MAC Address9 high and low registers. Each
10313  * bit controls the masking of the bytes. You can filter a group of addresses
10314  * (known as group address filtering) by masking one or more bytes of the address.
10315  *
10316  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10317  *
10318  * Field Enumeration Values:
10319  *
10320  * Enum | Value | Description
10321  * :---------------------------------------------|:------|:------------------------------------
10322  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10323  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10324  *
10325  * Field Access Macros:
10326  *
10327  */
10328 /*
10329  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
10330  *
10331  * Byte is unmasked (i.e. is compared)
10332  */
10333 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED 0x0
10334 /*
10335  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
10336  *
10337  * Byte is masked (i.e. not compared)
10338  */
10339 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED 0x1
10340 
10341 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
10342 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_LSB 29
10343 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
10344 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_MSB 29
10345 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
10346 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_WIDTH 1
10347 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
10348 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET_MSK 0x20000000
10349 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
10350 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_CLR_MSK 0xdfffffff
10351 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
10352 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_RESET 0x0
10353 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 field value from a register. */
10354 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
10355 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value suitable for setting the register. */
10356 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
10357 
10358 /*
10359  * Field : Source Address - sa
10360  *
10361  * When this bit is enabled, the MAC Address9[47:0] is used to compare with the SA
10362  * fields of the received frame. When this bit is disabled, the MAC Address9[47:0]
10363  * is used to compare with the DA fields of the received frame.
10364  *
10365  * Field Enumeration Values:
10366  *
10367  * Enum | Value | Description
10368  * :---------------------------------------|:------|:-----------------------------
10369  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
10370  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END | 0x1 | MAC address compare enabled
10371  *
10372  * Field Access Macros:
10373  *
10374  */
10375 /*
10376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
10377  *
10378  * MAC address compare disabled
10379  */
10380 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD 0x0
10381 /*
10382  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
10383  *
10384  * MAC address compare enabled
10385  */
10386 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END 0x1
10387 
10388 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
10389 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_LSB 30
10390 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
10391 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_MSB 30
10392 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
10393 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_WIDTH 1
10394 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
10395 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET_MSK 0x40000000
10396 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
10397 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_CLR_MSK 0xbfffffff
10398 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
10399 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_RESET 0x0
10400 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA field value from a register. */
10401 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
10402 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value suitable for setting the register. */
10403 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
10404 
10405 /*
10406  * Field : Address Enable - ae
10407  *
10408  * When this bit is enabled, the address filter block uses the 10th MAC address for
10409  * perfect filtering. When this bit is disabled, the address filter block ignores
10410  * the address for filtering.
10411  *
10412  * Field Enumeration Values:
10413  *
10414  * Enum | Value | Description
10415  * :---------------------------------------|:------|:--------------------------------------
10416  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
10417  * ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
10418  *
10419  * Field Access Macros:
10420  *
10421  */
10422 /*
10423  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
10424  *
10425  * Second MAC address filtering disabled
10426  */
10427 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD 0x0
10428 /*
10429  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
10430  *
10431  * Second MAC address filtering enabled
10432  */
10433 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END 0x1
10434 
10435 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
10436 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_LSB 31
10437 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
10438 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_MSB 31
10439 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
10440 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_WIDTH 1
10441 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
10442 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET_MSK 0x80000000
10443 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
10444 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_CLR_MSK 0x7fffffff
10445 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
10446 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_RESET 0x0
10447 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE field value from a register. */
10448 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
10449 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value suitable for setting the register. */
10450 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
10451 
10452 #ifndef __ASSEMBLY__
10453 /*
10454  * WARNING: The C register and register group struct declarations are provided for
10455  * convenience and illustrative purposes. They should, however, be used with
10456  * caution as the C language standard provides no guarantees about the alignment or
10457  * atomicity of device memory accesses. The recommended practice for writing
10458  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10459  * alt_write_word() functions.
10460  *
10461  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH.
10462  */
10463 struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s
10464 {
10465  uint32_t addrhi : 16; /* MAC Address9 [47:32] */
10466  uint32_t : 8; /* *UNDEFINED* */
10467  uint32_t mbc_0 : 1; /* Mask Byte Control */
10468  uint32_t mbc_1 : 1; /* Mask Byte Control */
10469  uint32_t mbc_2 : 1; /* Mask Byte Control */
10470  uint32_t mbc_3 : 1; /* Mask Byte Control */
10471  uint32_t mbc_4 : 1; /* Mask Byte Control */
10472  uint32_t mbc_5 : 1; /* Mask Byte Control */
10473  uint32_t sa : 1; /* Source Address */
10474  uint32_t ae : 1; /* Address Enable */
10475 };
10476 
10477 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH. */
10478 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t;
10479 #endif /* __ASSEMBLY__ */
10480 
10481 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register from the beginning of the component. */
10482 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST 0x88
10483 /* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register. */
10484 #define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST))
10485 
10486 /*
10487  * Register : Register 35 (MAC Address9 Low Register) - MAC_Address9_Low
10488  *
10489  * The MAC Address9 Low register holds the lower 32 bits of the 10th 6-byte MAC
10490  * address of the station.
10491  *
10492  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
10493  * format.
10494  *
10495  * Register Layout
10496  *
10497  * Bits | Access | Reset | Description
10498  * :-------|:-------|:-----------|:--------------------
10499  * [31:0] | RW | 0xffffffff | MAC Address9 [31:0]
10500  *
10501  */
10502 /*
10503  * Field : MAC Address9 [31:0] - addrlo
10504  *
10505  * This field contains the lower 32 bits of the 10th 6-byte MAC address. The
10506  * content of this field is undefined until loaded by software after the
10507  * initialization process.
10508  *
10509  * Field Access Macros:
10510  *
10511  */
10512 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
10513 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_LSB 0
10514 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
10515 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_MSB 31
10516 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
10517 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_WIDTH 32
10518 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
10519 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET_MSK 0xffffffff
10520 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
10521 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_CLR_MSK 0x00000000
10522 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
10523 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_RESET 0xffffffff
10524 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO field value from a register. */
10525 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
10526 /* Produces a ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value suitable for setting the register. */
10527 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
10528 
10529 #ifndef __ASSEMBLY__
10530 /*
10531  * WARNING: The C register and register group struct declarations are provided for
10532  * convenience and illustrative purposes. They should, however, be used with
10533  * caution as the C language standard provides no guarantees about the alignment or
10534  * atomicity of device memory accesses. The recommended practice for writing
10535  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10536  * alt_write_word() functions.
10537  *
10538  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW.
10539  */
10540 struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s
10541 {
10542  uint32_t addrlo : 32; /* MAC Address9 [31:0] */
10543 };
10544 
10545 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW. */
10546 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s ALT_EMAC_GMAC_MAC_ADDR9_LOW_t;
10547 #endif /* __ASSEMBLY__ */
10548 
10549 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register from the beginning of the component. */
10550 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST 0x8c
10551 /* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register. */
10552 #define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST))
10553 
10554 /*
10555  * Register : Register 36 (MAC Address10 High Register) - MAC_Address10_High
10556  *
10557  * The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC
10558  * address of the station. Because the MAC address registers are configured to be
10559  * double-synchronized to the (G)MII clock domains, the synchronization is
10560  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
10561  * endian mode) of the MAC Address10 Low Register are written. For proper
10562  * synchronization updates, the consecutive writes to this Address Low Register
10563  * should be performed after at least four clock cycles in the destination clock
10564  * domain.
10565  *
10566  * Note that all MAC Address High registers (except MAC Address0 High) have the
10567  * same format.
10568  *
10569  * Register Layout
10570  *
10571  * Bits | Access | Reset | Description
10572  * :--------|:-------|:-------|:----------------------
10573  * [15:0] | RW | 0xffff | MAC Address10 [47:32]
10574  * [23:16] | ??? | 0x0 | *UNDEFINED*
10575  * [24] | RW | 0x0 | Mask Byte Control
10576  * [25] | RW | 0x0 | Mask Byte Control
10577  * [26] | RW | 0x0 | Mask Byte Control
10578  * [27] | RW | 0x0 | Mask Byte Control
10579  * [28] | RW | 0x0 | Mask Byte Control
10580  * [29] | RW | 0x0 | Mask Byte Control
10581  * [30] | RW | 0x0 | Source Address
10582  * [31] | RW | 0x0 | Address Enable
10583  *
10584  */
10585 /*
10586  * Field : MAC Address10 [47:32] - addrhi
10587  *
10588  * This field contains the upper 16 bits (47:32) of the 11th 6-byte MAC address.
10589  *
10590  * Field Access Macros:
10591  *
10592  */
10593 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
10594 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_LSB 0
10595 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
10596 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_MSB 15
10597 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
10598 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_WIDTH 16
10599 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
10600 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET_MSK 0x0000ffff
10601 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
10602 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_CLR_MSK 0xffff0000
10603 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
10604 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_RESET 0xffff
10605 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI field value from a register. */
10606 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
10607 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value suitable for setting the register. */
10608 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
10609 
10610 /*
10611  * Field : Mask Byte Control - mbc_0
10612  *
10613  * This array of bits are mask control bits for comparison of each of the MAC
10614  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10615  * received DA or SA with the contents of MAC Address10 high and low registers.
10616  * Each bit controls the masking of the bytes. You can filter a group of addresses
10617  * (known as group address filtering) by masking one or more bytes of the address.
10618  *
10619  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10620  *
10621  * Field Enumeration Values:
10622  *
10623  * Enum | Value | Description
10624  * :----------------------------------------------|:------|:------------------------------------
10625  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10626  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10627  *
10628  * Field Access Macros:
10629  *
10630  */
10631 /*
10632  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
10633  *
10634  * Byte is unmasked (i.e. is compared)
10635  */
10636 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED 0x0
10637 /*
10638  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
10639  *
10640  * Byte is masked (i.e. not compared)
10641  */
10642 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED 0x1
10643 
10644 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
10645 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_LSB 24
10646 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
10647 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_MSB 24
10648 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
10649 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_WIDTH 1
10650 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
10651 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET_MSK 0x01000000
10652 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
10653 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_CLR_MSK 0xfeffffff
10654 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
10655 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_RESET 0x0
10656 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 field value from a register. */
10657 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
10658 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value suitable for setting the register. */
10659 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
10660 
10661 /*
10662  * Field : Mask Byte Control - mbc_1
10663  *
10664  * This array of bits are mask control bits for comparison of each of the MAC
10665  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10666  * received DA or SA with the contents of MAC Address10 high and low registers.
10667  * Each bit controls the masking of the bytes. You can filter a group of addresses
10668  * (known as group address filtering) by masking one or more bytes of the address.
10669  *
10670  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10671  *
10672  * Field Enumeration Values:
10673  *
10674  * Enum | Value | Description
10675  * :----------------------------------------------|:------|:------------------------------------
10676  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10677  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10678  *
10679  * Field Access Macros:
10680  *
10681  */
10682 /*
10683  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
10684  *
10685  * Byte is unmasked (i.e. is compared)
10686  */
10687 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED 0x0
10688 /*
10689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
10690  *
10691  * Byte is masked (i.e. not compared)
10692  */
10693 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED 0x1
10694 
10695 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
10696 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_LSB 25
10697 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
10698 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_MSB 25
10699 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
10700 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_WIDTH 1
10701 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
10702 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET_MSK 0x02000000
10703 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
10704 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_CLR_MSK 0xfdffffff
10705 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
10706 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_RESET 0x0
10707 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 field value from a register. */
10708 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
10709 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value suitable for setting the register. */
10710 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
10711 
10712 /*
10713  * Field : Mask Byte Control - mbc_2
10714  *
10715  * This array of bits are mask control bits for comparison of each of the MAC
10716  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10717  * received DA or SA with the contents of MAC Address10 high and low registers.
10718  * Each bit controls the masking of the bytes. You can filter a group of addresses
10719  * (known as group address filtering) by masking one or more bytes of the address.
10720  *
10721  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10722  *
10723  * Field Enumeration Values:
10724  *
10725  * Enum | Value | Description
10726  * :----------------------------------------------|:------|:------------------------------------
10727  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10728  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10729  *
10730  * Field Access Macros:
10731  *
10732  */
10733 /*
10734  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
10735  *
10736  * Byte is unmasked (i.e. is compared)
10737  */
10738 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED 0x0
10739 /*
10740  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
10741  *
10742  * Byte is masked (i.e. not compared)
10743  */
10744 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED 0x1
10745 
10746 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
10747 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_LSB 26
10748 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
10749 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_MSB 26
10750 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
10751 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_WIDTH 1
10752 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
10753 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET_MSK 0x04000000
10754 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
10755 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_CLR_MSK 0xfbffffff
10756 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
10757 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_RESET 0x0
10758 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 field value from a register. */
10759 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
10760 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value suitable for setting the register. */
10761 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
10762 
10763 /*
10764  * Field : Mask Byte Control - mbc_3
10765  *
10766  * This array of bits are mask control bits for comparison of each of the MAC
10767  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10768  * received DA or SA with the contents of MAC Address10 high and low registers.
10769  * Each bit controls the masking of the bytes. You can filter a group of addresses
10770  * (known as group address filtering) by masking one or more bytes of the address.
10771  *
10772  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10773  *
10774  * Field Enumeration Values:
10775  *
10776  * Enum | Value | Description
10777  * :----------------------------------------------|:------|:------------------------------------
10778  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10779  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10780  *
10781  * Field Access Macros:
10782  *
10783  */
10784 /*
10785  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
10786  *
10787  * Byte is unmasked (i.e. is compared)
10788  */
10789 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED 0x0
10790 /*
10791  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
10792  *
10793  * Byte is masked (i.e. not compared)
10794  */
10795 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED 0x1
10796 
10797 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
10798 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_LSB 27
10799 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
10800 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_MSB 27
10801 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
10802 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_WIDTH 1
10803 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
10804 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET_MSK 0x08000000
10805 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
10806 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_CLR_MSK 0xf7ffffff
10807 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
10808 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_RESET 0x0
10809 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 field value from a register. */
10810 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
10811 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value suitable for setting the register. */
10812 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
10813 
10814 /*
10815  * Field : Mask Byte Control - mbc_4
10816  *
10817  * This array of bits are mask control bits for comparison of each of the MAC
10818  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10819  * received DA or SA with the contents of MAC Address10 high and low registers.
10820  * Each bit controls the masking of the bytes. You can filter a group of addresses
10821  * (known as group address filtering) by masking one or more bytes of the address.
10822  *
10823  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10824  *
10825  * Field Enumeration Values:
10826  *
10827  * Enum | Value | Description
10828  * :----------------------------------------------|:------|:------------------------------------
10829  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10830  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10831  *
10832  * Field Access Macros:
10833  *
10834  */
10835 /*
10836  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
10837  *
10838  * Byte is unmasked (i.e. is compared)
10839  */
10840 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED 0x0
10841 /*
10842  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
10843  *
10844  * Byte is masked (i.e. not compared)
10845  */
10846 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED 0x1
10847 
10848 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
10849 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_LSB 28
10850 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
10851 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_MSB 28
10852 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
10853 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_WIDTH 1
10854 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
10855 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET_MSK 0x10000000
10856 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
10857 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_CLR_MSK 0xefffffff
10858 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
10859 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_RESET 0x0
10860 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 field value from a register. */
10861 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
10862 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value suitable for setting the register. */
10863 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
10864 
10865 /*
10866  * Field : Mask Byte Control - mbc_5
10867  *
10868  * This array of bits are mask control bits for comparison of each of the MAC
10869  * Address bytes. When masked, the MAC does not compare the corresponding byte of
10870  * received DA or SA with the contents of MAC Address10 high and low registers.
10871  * Each bit controls the masking of the bytes. You can filter a group of addresses
10872  * (known as group address filtering) by masking one or more bytes of the address.
10873  *
10874  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
10875  *
10876  * Field Enumeration Values:
10877  *
10878  * Enum | Value | Description
10879  * :----------------------------------------------|:------|:------------------------------------
10880  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
10881  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
10882  *
10883  * Field Access Macros:
10884  *
10885  */
10886 /*
10887  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
10888  *
10889  * Byte is unmasked (i.e. is compared)
10890  */
10891 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED 0x0
10892 /*
10893  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
10894  *
10895  * Byte is masked (i.e. not compared)
10896  */
10897 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED 0x1
10898 
10899 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
10900 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_LSB 29
10901 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
10902 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_MSB 29
10903 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
10904 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_WIDTH 1
10905 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
10906 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET_MSK 0x20000000
10907 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
10908 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_CLR_MSK 0xdfffffff
10909 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
10910 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_RESET 0x0
10911 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 field value from a register. */
10912 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
10913 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value suitable for setting the register. */
10914 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
10915 
10916 /*
10917  * Field : Source Address - sa
10918  *
10919  * When this bit is enabled, the MAC Address10[47:0] is used to compare with the SA
10920  * fields of the received frame. When this bit is disabled, the MAC Address10[47:0]
10921  * is used to compare with the DA fields of the received frame.
10922  *
10923  * Field Enumeration Values:
10924  *
10925  * Enum | Value | Description
10926  * :----------------------------------------|:------|:-----------------------------
10927  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
10928  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END | 0x1 | MAC address compare enabled
10929  *
10930  * Field Access Macros:
10931  *
10932  */
10933 /*
10934  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
10935  *
10936  * MAC address compare disabled
10937  */
10938 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD 0x0
10939 /*
10940  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
10941  *
10942  * MAC address compare enabled
10943  */
10944 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END 0x1
10945 
10946 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
10947 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_LSB 30
10948 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
10949 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_MSB 30
10950 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
10951 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_WIDTH 1
10952 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
10953 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET_MSK 0x40000000
10954 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
10955 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_CLR_MSK 0xbfffffff
10956 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
10957 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_RESET 0x0
10958 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA field value from a register. */
10959 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
10960 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value suitable for setting the register. */
10961 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
10962 
10963 /*
10964  * Field : Address Enable - ae
10965  *
10966  * When this bit is enabled, the address filter block uses the 11th MAC address for
10967  * perfect filtering. When this bit is disabled, the address filter block ignores
10968  * the address for filtering.
10969  *
10970  * Field Enumeration Values:
10971  *
10972  * Enum | Value | Description
10973  * :----------------------------------------|:------|:--------------------------------------
10974  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
10975  * ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
10976  *
10977  * Field Access Macros:
10978  *
10979  */
10980 /*
10981  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
10982  *
10983  * Second MAC address filtering disabled
10984  */
10985 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD 0x0
10986 /*
10987  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
10988  *
10989  * Second MAC address filtering enabled
10990  */
10991 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END 0x1
10992 
10993 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
10994 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_LSB 31
10995 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
10996 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_MSB 31
10997 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
10998 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_WIDTH 1
10999 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
11000 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET_MSK 0x80000000
11001 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
11002 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_CLR_MSK 0x7fffffff
11003 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
11004 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_RESET 0x0
11005 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE field value from a register. */
11006 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
11007 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value suitable for setting the register. */
11008 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
11009 
11010 #ifndef __ASSEMBLY__
11011 /*
11012  * WARNING: The C register and register group struct declarations are provided for
11013  * convenience and illustrative purposes. They should, however, be used with
11014  * caution as the C language standard provides no guarantees about the alignment or
11015  * atomicity of device memory accesses. The recommended practice for writing
11016  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11017  * alt_write_word() functions.
11018  *
11019  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH.
11020  */
11021 struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s
11022 {
11023  uint32_t addrhi : 16; /* MAC Address10 [47:32] */
11024  uint32_t : 8; /* *UNDEFINED* */
11025  uint32_t mbc_0 : 1; /* Mask Byte Control */
11026  uint32_t mbc_1 : 1; /* Mask Byte Control */
11027  uint32_t mbc_2 : 1; /* Mask Byte Control */
11028  uint32_t mbc_3 : 1; /* Mask Byte Control */
11029  uint32_t mbc_4 : 1; /* Mask Byte Control */
11030  uint32_t mbc_5 : 1; /* Mask Byte Control */
11031  uint32_t sa : 1; /* Source Address */
11032  uint32_t ae : 1; /* Address Enable */
11033 };
11034 
11035 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH. */
11036 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t;
11037 #endif /* __ASSEMBLY__ */
11038 
11039 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register from the beginning of the component. */
11040 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST 0x90
11041 /* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register. */
11042 #define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST))
11043 
11044 /*
11045  * Register : Register 37 (MAC Address10 Low Register) - MAC_Address10_Low
11046  *
11047  * The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC
11048  * address of the station.
11049  *
11050  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
11051  * format.
11052  *
11053  * Register Layout
11054  *
11055  * Bits | Access | Reset | Description
11056  * :-------|:-------|:-----------|:---------------------
11057  * [31:0] | RW | 0xffffffff | MAC Address10 [31:0]
11058  *
11059  */
11060 /*
11061  * Field : MAC Address10 [31:0] - addrlo
11062  *
11063  * This field contains the lower 32 bits of the 11th 6-byte MAC address. The
11064  * content of this field is undefined until loaded by software after the
11065  * initialization process.
11066  *
11067  * Field Access Macros:
11068  *
11069  */
11070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
11071 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_LSB 0
11072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
11073 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_MSB 31
11074 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
11075 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_WIDTH 32
11076 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
11077 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET_MSK 0xffffffff
11078 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
11079 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_CLR_MSK 0x00000000
11080 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
11081 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_RESET 0xffffffff
11082 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO field value from a register. */
11083 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
11084 /* Produces a ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value suitable for setting the register. */
11085 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
11086 
11087 #ifndef __ASSEMBLY__
11088 /*
11089  * WARNING: The C register and register group struct declarations are provided for
11090  * convenience and illustrative purposes. They should, however, be used with
11091  * caution as the C language standard provides no guarantees about the alignment or
11092  * atomicity of device memory accesses. The recommended practice for writing
11093  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11094  * alt_write_word() functions.
11095  *
11096  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW.
11097  */
11098 struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s
11099 {
11100  uint32_t addrlo : 32; /* MAC Address10 [31:0] */
11101 };
11102 
11103 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW. */
11104 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s ALT_EMAC_GMAC_MAC_ADDR10_LOW_t;
11105 #endif /* __ASSEMBLY__ */
11106 
11107 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register from the beginning of the component. */
11108 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST 0x94
11109 /* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register. */
11110 #define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST))
11111 
11112 /*
11113  * Register : Register 38 (MAC Address11 High Register) - MAC_Address11_High
11114  *
11115  * The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC
11116  * address of the station. Because the MAC address registers are configured to be
11117  * double-synchronized to the (G)MII clock domains, the synchronization is
11118  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
11119  * endian mode) of the MAC Address11 Low Register are written. For proper
11120  * synchronization updates, the consecutive writes to this Address Low Register
11121  * should be performed after at least four clock cycles in the destination clock
11122  * domain.
11123  *
11124  * Note that all MAC Address High registers (except MAC Address0 High) have the
11125  * same format.
11126  *
11127  * Register Layout
11128  *
11129  * Bits | Access | Reset | Description
11130  * :--------|:-------|:-------|:----------------------
11131  * [15:0] | RW | 0xffff | MAC Address11 [47:32]
11132  * [23:16] | ??? | 0x0 | *UNDEFINED*
11133  * [24] | RW | 0x0 | Mask Byte Control
11134  * [25] | RW | 0x0 | Mask Byte Control
11135  * [26] | RW | 0x0 | Mask Byte Control
11136  * [27] | RW | 0x0 | Mask Byte Control
11137  * [28] | RW | 0x0 | Mask Byte Control
11138  * [29] | RW | 0x0 | Mask Byte Control
11139  * [30] | RW | 0x0 | Source Address
11140  * [31] | RW | 0x0 | Address Enable
11141  *
11142  */
11143 /*
11144  * Field : MAC Address11 [47:32] - addrhi
11145  *
11146  * This field contains the upper 16 bits (47:32) of the 12th 6-byte MAC address.
11147  *
11148  * Field Access Macros:
11149  *
11150  */
11151 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
11152 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_LSB 0
11153 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
11154 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_MSB 15
11155 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
11156 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_WIDTH 16
11157 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
11158 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET_MSK 0x0000ffff
11159 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
11160 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_CLR_MSK 0xffff0000
11161 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
11162 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_RESET 0xffff
11163 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI field value from a register. */
11164 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
11165 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value suitable for setting the register. */
11166 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
11167 
11168 /*
11169  * Field : Mask Byte Control - mbc_0
11170  *
11171  * This array of bits are mask control bits for comparison of each of the MAC
11172  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11173  * received DA or SA with the contents of MAC Address11 high and low registers.
11174  * Each bit controls the masking of the bytes. You can filter a group of addresses
11175  * (known as group address filtering) by masking one or more bytes of the address.
11176  *
11177  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11178  *
11179  * Field Enumeration Values:
11180  *
11181  * Enum | Value | Description
11182  * :----------------------------------------------|:------|:------------------------------------
11183  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11184  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11185  *
11186  * Field Access Macros:
11187  *
11188  */
11189 /*
11190  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
11191  *
11192  * Byte is unmasked (i.e. is compared)
11193  */
11194 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED 0x0
11195 /*
11196  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
11197  *
11198  * Byte is masked (i.e. not compared)
11199  */
11200 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED 0x1
11201 
11202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
11203 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_LSB 24
11204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
11205 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_MSB 24
11206 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
11207 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_WIDTH 1
11208 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
11209 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET_MSK 0x01000000
11210 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
11211 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_CLR_MSK 0xfeffffff
11212 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
11213 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_RESET 0x0
11214 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 field value from a register. */
11215 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
11216 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value suitable for setting the register. */
11217 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
11218 
11219 /*
11220  * Field : Mask Byte Control - mbc_1
11221  *
11222  * This array of bits are mask control bits for comparison of each of the MAC
11223  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11224  * received DA or SA with the contents of MAC Address11 high and low registers.
11225  * Each bit controls the masking of the bytes. You can filter a group of addresses
11226  * (known as group address filtering) by masking one or more bytes of the address.
11227  *
11228  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11229  *
11230  * Field Enumeration Values:
11231  *
11232  * Enum | Value | Description
11233  * :----------------------------------------------|:------|:------------------------------------
11234  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11235  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11236  *
11237  * Field Access Macros:
11238  *
11239  */
11240 /*
11241  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
11242  *
11243  * Byte is unmasked (i.e. is compared)
11244  */
11245 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED 0x0
11246 /*
11247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
11248  *
11249  * Byte is masked (i.e. not compared)
11250  */
11251 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED 0x1
11252 
11253 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
11254 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_LSB 25
11255 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
11256 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_MSB 25
11257 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
11258 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_WIDTH 1
11259 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
11260 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET_MSK 0x02000000
11261 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
11262 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_CLR_MSK 0xfdffffff
11263 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
11264 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_RESET 0x0
11265 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 field value from a register. */
11266 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
11267 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value suitable for setting the register. */
11268 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
11269 
11270 /*
11271  * Field : Mask Byte Control - mbc_2
11272  *
11273  * This array of bits are mask control bits for comparison of each of the MAC
11274  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11275  * received DA or SA with the contents of MAC Address11 high and low registers.
11276  * Each bit controls the masking of the bytes. You can filter a group of addresses
11277  * (known as group address filtering) by masking one or more bytes of the address.
11278  *
11279  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11280  *
11281  * Field Enumeration Values:
11282  *
11283  * Enum | Value | Description
11284  * :----------------------------------------------|:------|:------------------------------------
11285  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11286  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11287  *
11288  * Field Access Macros:
11289  *
11290  */
11291 /*
11292  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
11293  *
11294  * Byte is unmasked (i.e. is compared)
11295  */
11296 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED 0x0
11297 /*
11298  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
11299  *
11300  * Byte is masked (i.e. not compared)
11301  */
11302 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED 0x1
11303 
11304 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
11305 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_LSB 26
11306 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
11307 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_MSB 26
11308 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
11309 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_WIDTH 1
11310 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
11311 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET_MSK 0x04000000
11312 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
11313 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_CLR_MSK 0xfbffffff
11314 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
11315 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_RESET 0x0
11316 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 field value from a register. */
11317 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
11318 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value suitable for setting the register. */
11319 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
11320 
11321 /*
11322  * Field : Mask Byte Control - mbc_3
11323  *
11324  * This array of bits are mask control bits for comparison of each of the MAC
11325  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11326  * received DA or SA with the contents of MAC Address11 high and low registers.
11327  * Each bit controls the masking of the bytes. You can filter a group of addresses
11328  * (known as group address filtering) by masking one or more bytes of the address.
11329  *
11330  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11331  *
11332  * Field Enumeration Values:
11333  *
11334  * Enum | Value | Description
11335  * :----------------------------------------------|:------|:------------------------------------
11336  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11337  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11338  *
11339  * Field Access Macros:
11340  *
11341  */
11342 /*
11343  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
11344  *
11345  * Byte is unmasked (i.e. is compared)
11346  */
11347 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED 0x0
11348 /*
11349  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
11350  *
11351  * Byte is masked (i.e. not compared)
11352  */
11353 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED 0x1
11354 
11355 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
11356 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_LSB 27
11357 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
11358 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_MSB 27
11359 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
11360 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_WIDTH 1
11361 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
11362 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET_MSK 0x08000000
11363 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
11364 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_CLR_MSK 0xf7ffffff
11365 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
11366 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_RESET 0x0
11367 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 field value from a register. */
11368 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
11369 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value suitable for setting the register. */
11370 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
11371 
11372 /*
11373  * Field : Mask Byte Control - mbc_4
11374  *
11375  * This array of bits are mask control bits for comparison of each of the MAC
11376  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11377  * received DA or SA with the contents of MAC Address11 high and low registers.
11378  * Each bit controls the masking of the bytes. You can filter a group of addresses
11379  * (known as group address filtering) by masking one or more bytes of the address.
11380  *
11381  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11382  *
11383  * Field Enumeration Values:
11384  *
11385  * Enum | Value | Description
11386  * :----------------------------------------------|:------|:------------------------------------
11387  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11388  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11389  *
11390  * Field Access Macros:
11391  *
11392  */
11393 /*
11394  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
11395  *
11396  * Byte is unmasked (i.e. is compared)
11397  */
11398 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED 0x0
11399 /*
11400  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
11401  *
11402  * Byte is masked (i.e. not compared)
11403  */
11404 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED 0x1
11405 
11406 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
11407 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_LSB 28
11408 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
11409 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_MSB 28
11410 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
11411 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_WIDTH 1
11412 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
11413 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET_MSK 0x10000000
11414 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
11415 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_CLR_MSK 0xefffffff
11416 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
11417 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_RESET 0x0
11418 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 field value from a register. */
11419 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
11420 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value suitable for setting the register. */
11421 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
11422 
11423 /*
11424  * Field : Mask Byte Control - mbc_5
11425  *
11426  * This array of bits are mask control bits for comparison of each of the MAC
11427  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11428  * received DA or SA with the contents of MAC Address11 high and low registers.
11429  * Each bit controls the masking of the bytes. You can filter a group of addresses
11430  * (known as group address filtering) by masking one or more bytes of the address.
11431  *
11432  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11433  *
11434  * Field Enumeration Values:
11435  *
11436  * Enum | Value | Description
11437  * :----------------------------------------------|:------|:------------------------------------
11438  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11439  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11440  *
11441  * Field Access Macros:
11442  *
11443  */
11444 /*
11445  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
11446  *
11447  * Byte is unmasked (i.e. is compared)
11448  */
11449 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED 0x0
11450 /*
11451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
11452  *
11453  * Byte is masked (i.e. not compared)
11454  */
11455 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED 0x1
11456 
11457 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
11458 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_LSB 29
11459 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
11460 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_MSB 29
11461 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
11462 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_WIDTH 1
11463 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
11464 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET_MSK 0x20000000
11465 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
11466 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_CLR_MSK 0xdfffffff
11467 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
11468 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_RESET 0x0
11469 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 field value from a register. */
11470 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
11471 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value suitable for setting the register. */
11472 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
11473 
11474 /*
11475  * Field : Source Address - sa
11476  *
11477  * When this bit is enabled, the MAC Address11[47:0] is used to compare with the SA
11478  * fields of the received frame. When this bit is disabled, the MAC Address11[47:0]
11479  * is used to compare with the DA fields of the received frame.
11480  *
11481  * Field Enumeration Values:
11482  *
11483  * Enum | Value | Description
11484  * :----------------------------------------|:------|:-----------------------------
11485  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
11486  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END | 0x1 | MAC address compare enabled
11487  *
11488  * Field Access Macros:
11489  *
11490  */
11491 /*
11492  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
11493  *
11494  * MAC address compare disabled
11495  */
11496 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD 0x0
11497 /*
11498  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
11499  *
11500  * MAC address compare enabled
11501  */
11502 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END 0x1
11503 
11504 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
11505 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_LSB 30
11506 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
11507 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_MSB 30
11508 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
11509 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_WIDTH 1
11510 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
11511 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET_MSK 0x40000000
11512 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
11513 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_CLR_MSK 0xbfffffff
11514 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
11515 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_RESET 0x0
11516 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA field value from a register. */
11517 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
11518 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value suitable for setting the register. */
11519 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
11520 
11521 /*
11522  * Field : Address Enable - ae
11523  *
11524  * When this bit is enabled, the address filter block uses the 12th MAC address for
11525  * perfect filtering. When this bit is disabled, the address filter block ignores
11526  * the address for filtering.
11527  *
11528  * Field Enumeration Values:
11529  *
11530  * Enum | Value | Description
11531  * :----------------------------------------|:------|:--------------------------------------
11532  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
11533  * ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
11534  *
11535  * Field Access Macros:
11536  *
11537  */
11538 /*
11539  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
11540  *
11541  * Second MAC address filtering disabled
11542  */
11543 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD 0x0
11544 /*
11545  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
11546  *
11547  * Second MAC address filtering enabled
11548  */
11549 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END 0x1
11550 
11551 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
11552 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_LSB 31
11553 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
11554 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_MSB 31
11555 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
11556 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_WIDTH 1
11557 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
11558 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET_MSK 0x80000000
11559 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
11560 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_CLR_MSK 0x7fffffff
11561 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
11562 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_RESET 0x0
11563 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE field value from a register. */
11564 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
11565 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value suitable for setting the register. */
11566 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
11567 
11568 #ifndef __ASSEMBLY__
11569 /*
11570  * WARNING: The C register and register group struct declarations are provided for
11571  * convenience and illustrative purposes. They should, however, be used with
11572  * caution as the C language standard provides no guarantees about the alignment or
11573  * atomicity of device memory accesses. The recommended practice for writing
11574  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11575  * alt_write_word() functions.
11576  *
11577  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH.
11578  */
11579 struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s
11580 {
11581  uint32_t addrhi : 16; /* MAC Address11 [47:32] */
11582  uint32_t : 8; /* *UNDEFINED* */
11583  uint32_t mbc_0 : 1; /* Mask Byte Control */
11584  uint32_t mbc_1 : 1; /* Mask Byte Control */
11585  uint32_t mbc_2 : 1; /* Mask Byte Control */
11586  uint32_t mbc_3 : 1; /* Mask Byte Control */
11587  uint32_t mbc_4 : 1; /* Mask Byte Control */
11588  uint32_t mbc_5 : 1; /* Mask Byte Control */
11589  uint32_t sa : 1; /* Source Address */
11590  uint32_t ae : 1; /* Address Enable */
11591 };
11592 
11593 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH. */
11594 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t;
11595 #endif /* __ASSEMBLY__ */
11596 
11597 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register from the beginning of the component. */
11598 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST 0x98
11599 /* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register. */
11600 #define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST))
11601 
11602 /*
11603  * Register : Register 39 (MAC Address11 Low Register) - MAC_Address11_Low
11604  *
11605  * The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC
11606  * address of the station.
11607  *
11608  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
11609  * format.
11610  *
11611  * Register Layout
11612  *
11613  * Bits | Access | Reset | Description
11614  * :-------|:-------|:-----------|:---------------------
11615  * [31:0] | RW | 0xffffffff | MAC Address11 [31:0]
11616  *
11617  */
11618 /*
11619  * Field : MAC Address11 [31:0] - addrlo
11620  *
11621  * This field contains the lower 32 bits of the 12th 6-byte MAC address. The
11622  * content of this field is undefined until loaded by software after the
11623  * initialization process.
11624  *
11625  * Field Access Macros:
11626  *
11627  */
11628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
11629 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_LSB 0
11630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
11631 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_MSB 31
11632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
11633 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_WIDTH 32
11634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
11635 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET_MSK 0xffffffff
11636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
11637 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_CLR_MSK 0x00000000
11638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
11639 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_RESET 0xffffffff
11640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO field value from a register. */
11641 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
11642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value suitable for setting the register. */
11643 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
11644 
11645 #ifndef __ASSEMBLY__
11646 /*
11647  * WARNING: The C register and register group struct declarations are provided for
11648  * convenience and illustrative purposes. They should, however, be used with
11649  * caution as the C language standard provides no guarantees about the alignment or
11650  * atomicity of device memory accesses. The recommended practice for writing
11651  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11652  * alt_write_word() functions.
11653  *
11654  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW.
11655  */
11656 struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s
11657 {
11658  uint32_t addrlo : 32; /* MAC Address11 [31:0] */
11659 };
11660 
11661 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW. */
11662 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s ALT_EMAC_GMAC_MAC_ADDR11_LOW_t;
11663 #endif /* __ASSEMBLY__ */
11664 
11665 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register from the beginning of the component. */
11666 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST 0x9c
11667 /* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register. */
11668 #define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST))
11669 
11670 /*
11671  * Register : Register 40 (MAC Address12 High Register) - MAC_Address12_High
11672  *
11673  * The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC
11674  * address of the station. Because the MAC address registers are configured to be
11675  * double-synchronized to the (G)MII clock domains, the synchronization is
11676  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
11677  * endian mode) of the MAC Address12 Low Register are written. For proper
11678  * synchronization updates, the consecutive writes to this Address Low Register
11679  * should be performed after at least four clock cycles in the destination clock
11680  * domain.
11681  *
11682  * Note that all MAC Address High registers (except MAC Address0 High) have the
11683  * same format.
11684  *
11685  * Register Layout
11686  *
11687  * Bits | Access | Reset | Description
11688  * :--------|:-------|:-------|:----------------------
11689  * [15:0] | RW | 0xffff | MAC Address12 [47:32]
11690  * [23:16] | ??? | 0x0 | *UNDEFINED*
11691  * [24] | RW | 0x0 | Mask Byte Control
11692  * [25] | RW | 0x0 | Mask Byte Control
11693  * [26] | RW | 0x0 | Mask Byte Control
11694  * [27] | RW | 0x0 | Mask Byte Control
11695  * [28] | RW | 0x0 | Mask Byte Control
11696  * [29] | RW | 0x0 | Mask Byte Control
11697  * [30] | RW | 0x0 | Source Address
11698  * [31] | RW | 0x0 | Address Enable
11699  *
11700  */
11701 /*
11702  * Field : MAC Address12 [47:32] - addrhi
11703  *
11704  * This field contains the upper 16 bits (47:32) of the 13th 6-byte MAC address.
11705  *
11706  * Field Access Macros:
11707  *
11708  */
11709 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
11710 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_LSB 0
11711 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
11712 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_MSB 15
11713 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
11714 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_WIDTH 16
11715 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
11716 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET_MSK 0x0000ffff
11717 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
11718 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_CLR_MSK 0xffff0000
11719 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
11720 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_RESET 0xffff
11721 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI field value from a register. */
11722 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
11723 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value suitable for setting the register. */
11724 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
11725 
11726 /*
11727  * Field : Mask Byte Control - mbc_0
11728  *
11729  * This array of bits are mask control bits for comparison of each of the MAC
11730  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11731  * received DA or SA with the contents of MAC Address12 high and low registers.
11732  * Each bit controls the masking of the bytes. You can filter a group of addresses
11733  * (known as group address filtering) by masking one or more bytes of the address.
11734  *
11735  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11736  *
11737  * Field Enumeration Values:
11738  *
11739  * Enum | Value | Description
11740  * :----------------------------------------------|:------|:------------------------------------
11741  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11742  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11743  *
11744  * Field Access Macros:
11745  *
11746  */
11747 /*
11748  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
11749  *
11750  * Byte is unmasked (i.e. is compared)
11751  */
11752 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED 0x0
11753 /*
11754  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
11755  *
11756  * Byte is masked (i.e. not compared)
11757  */
11758 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED 0x1
11759 
11760 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
11761 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_LSB 24
11762 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
11763 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_MSB 24
11764 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
11765 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_WIDTH 1
11766 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
11767 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET_MSK 0x01000000
11768 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
11769 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_CLR_MSK 0xfeffffff
11770 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
11771 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_RESET 0x0
11772 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 field value from a register. */
11773 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
11774 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value suitable for setting the register. */
11775 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
11776 
11777 /*
11778  * Field : Mask Byte Control - mbc_1
11779  *
11780  * This array of bits are mask control bits for comparison of each of the MAC
11781  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11782  * received DA or SA with the contents of MAC Address12 high and low registers.
11783  * Each bit controls the masking of the bytes. You can filter a group of addresses
11784  * (known as group address filtering) by masking one or more bytes of the address.
11785  *
11786  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11787  *
11788  * Field Enumeration Values:
11789  *
11790  * Enum | Value | Description
11791  * :----------------------------------------------|:------|:------------------------------------
11792  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11793  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11794  *
11795  * Field Access Macros:
11796  *
11797  */
11798 /*
11799  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
11800  *
11801  * Byte is unmasked (i.e. is compared)
11802  */
11803 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED 0x0
11804 /*
11805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
11806  *
11807  * Byte is masked (i.e. not compared)
11808  */
11809 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED 0x1
11810 
11811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
11812 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_LSB 25
11813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
11814 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_MSB 25
11815 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
11816 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_WIDTH 1
11817 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
11818 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET_MSK 0x02000000
11819 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
11820 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_CLR_MSK 0xfdffffff
11821 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
11822 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_RESET 0x0
11823 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 field value from a register. */
11824 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
11825 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value suitable for setting the register. */
11826 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
11827 
11828 /*
11829  * Field : Mask Byte Control - mbc_2
11830  *
11831  * This array of bits are mask control bits for comparison of each of the MAC
11832  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11833  * received DA or SA with the contents of MAC Address12 high and low registers.
11834  * Each bit controls the masking of the bytes. You can filter a group of addresses
11835  * (known as group address filtering) by masking one or more bytes of the address.
11836  *
11837  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11838  *
11839  * Field Enumeration Values:
11840  *
11841  * Enum | Value | Description
11842  * :----------------------------------------------|:------|:------------------------------------
11843  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11844  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11845  *
11846  * Field Access Macros:
11847  *
11848  */
11849 /*
11850  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
11851  *
11852  * Byte is unmasked (i.e. is compared)
11853  */
11854 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED 0x0
11855 /*
11856  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
11857  *
11858  * Byte is masked (i.e. not compared)
11859  */
11860 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED 0x1
11861 
11862 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
11863 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_LSB 26
11864 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
11865 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_MSB 26
11866 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
11867 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_WIDTH 1
11868 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
11869 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET_MSK 0x04000000
11870 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
11871 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_CLR_MSK 0xfbffffff
11872 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
11873 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_RESET 0x0
11874 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 field value from a register. */
11875 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
11876 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value suitable for setting the register. */
11877 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
11878 
11879 /*
11880  * Field : Mask Byte Control - mbc_3
11881  *
11882  * This array of bits are mask control bits for comparison of each of the MAC
11883  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11884  * received DA or SA with the contents of MAC Address12 high and low registers.
11885  * Each bit controls the masking of the bytes. You can filter a group of addresses
11886  * (known as group address filtering) by masking one or more bytes of the address.
11887  *
11888  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11889  *
11890  * Field Enumeration Values:
11891  *
11892  * Enum | Value | Description
11893  * :----------------------------------------------|:------|:------------------------------------
11894  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11895  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11896  *
11897  * Field Access Macros:
11898  *
11899  */
11900 /*
11901  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
11902  *
11903  * Byte is unmasked (i.e. is compared)
11904  */
11905 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED 0x0
11906 /*
11907  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
11908  *
11909  * Byte is masked (i.e. not compared)
11910  */
11911 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED 0x1
11912 
11913 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
11914 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_LSB 27
11915 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
11916 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_MSB 27
11917 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
11918 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_WIDTH 1
11919 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
11920 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET_MSK 0x08000000
11921 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
11922 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_CLR_MSK 0xf7ffffff
11923 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
11924 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_RESET 0x0
11925 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 field value from a register. */
11926 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
11927 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value suitable for setting the register. */
11928 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
11929 
11930 /*
11931  * Field : Mask Byte Control - mbc_4
11932  *
11933  * This array of bits are mask control bits for comparison of each of the MAC
11934  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11935  * received DA or SA with the contents of MAC Address12 high and low registers.
11936  * Each bit controls the masking of the bytes. You can filter a group of addresses
11937  * (known as group address filtering) by masking one or more bytes of the address.
11938  *
11939  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11940  *
11941  * Field Enumeration Values:
11942  *
11943  * Enum | Value | Description
11944  * :----------------------------------------------|:------|:------------------------------------
11945  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11946  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11947  *
11948  * Field Access Macros:
11949  *
11950  */
11951 /*
11952  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
11953  *
11954  * Byte is unmasked (i.e. is compared)
11955  */
11956 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED 0x0
11957 /*
11958  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
11959  *
11960  * Byte is masked (i.e. not compared)
11961  */
11962 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED 0x1
11963 
11964 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
11965 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_LSB 28
11966 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
11967 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_MSB 28
11968 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
11969 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_WIDTH 1
11970 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
11971 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET_MSK 0x10000000
11972 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
11973 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_CLR_MSK 0xefffffff
11974 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
11975 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_RESET 0x0
11976 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 field value from a register. */
11977 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
11978 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value suitable for setting the register. */
11979 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
11980 
11981 /*
11982  * Field : Mask Byte Control - mbc_5
11983  *
11984  * This array of bits are mask control bits for comparison of each of the MAC
11985  * Address bytes. When masked, the MAC does not compare the corresponding byte of
11986  * received DA or SA with the contents of MAC Address12 high and low registers.
11987  * Each bit controls the masking of the bytes. You can filter a group of addresses
11988  * (known as group address filtering) by masking one or more bytes of the address.
11989  *
11990  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
11991  *
11992  * Field Enumeration Values:
11993  *
11994  * Enum | Value | Description
11995  * :----------------------------------------------|:------|:------------------------------------
11996  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
11997  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
11998  *
11999  * Field Access Macros:
12000  *
12001  */
12002 /*
12003  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
12004  *
12005  * Byte is unmasked (i.e. is compared)
12006  */
12007 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED 0x0
12008 /*
12009  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
12010  *
12011  * Byte is masked (i.e. not compared)
12012  */
12013 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED 0x1
12014 
12015 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
12016 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_LSB 29
12017 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
12018 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_MSB 29
12019 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
12020 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_WIDTH 1
12021 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
12022 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET_MSK 0x20000000
12023 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
12024 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_CLR_MSK 0xdfffffff
12025 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
12026 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_RESET 0x0
12027 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 field value from a register. */
12028 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
12029 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value suitable for setting the register. */
12030 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
12031 
12032 /*
12033  * Field : Source Address - sa
12034  *
12035  * When this bit is enabled, the MAC Address12[47:0] is used to compare with the SA
12036  * fields of the received frame. When this bit is disabled, the MAC Address12[47:0]
12037  * is used to compare with the DA fields of the received frame.
12038  *
12039  * Field Enumeration Values:
12040  *
12041  * Enum | Value | Description
12042  * :----------------------------------------|:------|:-----------------------------
12043  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
12044  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END | 0x1 | MAC address compare enabled
12045  *
12046  * Field Access Macros:
12047  *
12048  */
12049 /*
12050  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
12051  *
12052  * MAC address compare disabled
12053  */
12054 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD 0x0
12055 /*
12056  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
12057  *
12058  * MAC address compare enabled
12059  */
12060 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END 0x1
12061 
12062 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
12063 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_LSB 30
12064 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
12065 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_MSB 30
12066 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
12067 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_WIDTH 1
12068 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
12069 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET_MSK 0x40000000
12070 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
12071 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_CLR_MSK 0xbfffffff
12072 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
12073 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_RESET 0x0
12074 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA field value from a register. */
12075 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
12076 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value suitable for setting the register. */
12077 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
12078 
12079 /*
12080  * Field : Address Enable - ae
12081  *
12082  * When this bit is enabled, the address filter block uses the 13th MAC address for
12083  * perfect filtering. When this bit is disabled, the address filter block ignores
12084  * the address for filtering.
12085  *
12086  * Field Enumeration Values:
12087  *
12088  * Enum | Value | Description
12089  * :----------------------------------------|:------|:--------------------------------------
12090  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
12091  * ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
12092  *
12093  * Field Access Macros:
12094  *
12095  */
12096 /*
12097  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
12098  *
12099  * Second MAC address filtering disabled
12100  */
12101 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD 0x0
12102 /*
12103  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
12104  *
12105  * Second MAC address filtering enabled
12106  */
12107 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END 0x1
12108 
12109 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
12110 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_LSB 31
12111 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
12112 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_MSB 31
12113 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
12114 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_WIDTH 1
12115 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
12116 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET_MSK 0x80000000
12117 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
12118 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_CLR_MSK 0x7fffffff
12119 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
12120 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_RESET 0x0
12121 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE field value from a register. */
12122 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
12123 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value suitable for setting the register. */
12124 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
12125 
12126 #ifndef __ASSEMBLY__
12127 /*
12128  * WARNING: The C register and register group struct declarations are provided for
12129  * convenience and illustrative purposes. They should, however, be used with
12130  * caution as the C language standard provides no guarantees about the alignment or
12131  * atomicity of device memory accesses. The recommended practice for writing
12132  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12133  * alt_write_word() functions.
12134  *
12135  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH.
12136  */
12137 struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s
12138 {
12139  uint32_t addrhi : 16; /* MAC Address12 [47:32] */
12140  uint32_t : 8; /* *UNDEFINED* */
12141  uint32_t mbc_0 : 1; /* Mask Byte Control */
12142  uint32_t mbc_1 : 1; /* Mask Byte Control */
12143  uint32_t mbc_2 : 1; /* Mask Byte Control */
12144  uint32_t mbc_3 : 1; /* Mask Byte Control */
12145  uint32_t mbc_4 : 1; /* Mask Byte Control */
12146  uint32_t mbc_5 : 1; /* Mask Byte Control */
12147  uint32_t sa : 1; /* Source Address */
12148  uint32_t ae : 1; /* Address Enable */
12149 };
12150 
12151 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH. */
12152 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t;
12153 #endif /* __ASSEMBLY__ */
12154 
12155 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register from the beginning of the component. */
12156 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST 0xa0
12157 /* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register. */
12158 #define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST))
12159 
12160 /*
12161  * Register : Register 41 (MAC Address12 Low Register) - MAC_Address12_Low
12162  *
12163  * The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC
12164  * address of the station.
12165  *
12166  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
12167  * format.
12168  *
12169  * Register Layout
12170  *
12171  * Bits | Access | Reset | Description
12172  * :-------|:-------|:-----------|:---------------------
12173  * [31:0] | RW | 0xffffffff | MAC Address12 [31:0]
12174  *
12175  */
12176 /*
12177  * Field : MAC Address12 [31:0] - addrlo
12178  *
12179  * This field contains the lower 32 bits of the 13th 6-byte MAC address. The
12180  * content of this field is undefined until loaded by software after the
12181  * initialization process.
12182  *
12183  * Field Access Macros:
12184  *
12185  */
12186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
12187 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_LSB 0
12188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
12189 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_MSB 31
12190 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
12191 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_WIDTH 32
12192 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
12193 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET_MSK 0xffffffff
12194 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
12195 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_CLR_MSK 0x00000000
12196 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
12197 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_RESET 0xffffffff
12198 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO field value from a register. */
12199 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
12200 /* Produces a ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value suitable for setting the register. */
12201 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
12202 
12203 #ifndef __ASSEMBLY__
12204 /*
12205  * WARNING: The C register and register group struct declarations are provided for
12206  * convenience and illustrative purposes. They should, however, be used with
12207  * caution as the C language standard provides no guarantees about the alignment or
12208  * atomicity of device memory accesses. The recommended practice for writing
12209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12210  * alt_write_word() functions.
12211  *
12212  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW.
12213  */
12214 struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s
12215 {
12216  uint32_t addrlo : 32; /* MAC Address12 [31:0] */
12217 };
12218 
12219 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW. */
12220 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s ALT_EMAC_GMAC_MAC_ADDR12_LOW_t;
12221 #endif /* __ASSEMBLY__ */
12222 
12223 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register from the beginning of the component. */
12224 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST 0xa4
12225 /* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register. */
12226 #define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST))
12227 
12228 /*
12229  * Register : Register 42 (MAC Address13 High Register) - MAC_Address13_High
12230  *
12231  * The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC
12232  * address of the station. Because the MAC address registers are configured to be
12233  * double-synchronized to the (G)MII clock domains, the synchronization is
12234  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
12235  * endian mode) of the MAC Address13 Low Register are written. For proper
12236  * synchronization updates, the consecutive writes to this Address Low Register
12237  * should be performed after at least four clock cycles in the destination clock
12238  * domain.
12239  *
12240  * Note that all MAC Address High registers (except MAC Address0 High) have the
12241  * same format.
12242  *
12243  * Register Layout
12244  *
12245  * Bits | Access | Reset | Description
12246  * :--------|:-------|:-------|:----------------------
12247  * [15:0] | RW | 0xffff | MAC Address13 [47:32]
12248  * [23:16] | ??? | 0x0 | *UNDEFINED*
12249  * [24] | RW | 0x0 | Mask Byte Control
12250  * [25] | RW | 0x0 | Mask Byte Control
12251  * [26] | RW | 0x0 | Mask Byte Control
12252  * [27] | RW | 0x0 | Mask Byte Control
12253  * [28] | RW | 0x0 | Mask Byte Control
12254  * [29] | RW | 0x0 | Mask Byte Control
12255  * [30] | RW | 0x0 | Source Address
12256  * [31] | RW | 0x0 | Address Enable
12257  *
12258  */
12259 /*
12260  * Field : MAC Address13 [47:32] - addrhi
12261  *
12262  * This field contains the upper 16 bits (47:32) of the 14th 6-byte MAC address.
12263  *
12264  * Field Access Macros:
12265  *
12266  */
12267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
12268 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_LSB 0
12269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
12270 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_MSB 15
12271 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
12272 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_WIDTH 16
12273 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
12274 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET_MSK 0x0000ffff
12275 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
12276 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_CLR_MSK 0xffff0000
12277 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
12278 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_RESET 0xffff
12279 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI field value from a register. */
12280 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
12281 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value suitable for setting the register. */
12282 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
12283 
12284 /*
12285  * Field : Mask Byte Control - mbc_0
12286  *
12287  * This array of bits are mask control bits for comparison of each of the MAC
12288  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12289  * received DA or SA with the contents of MAC Address13 high and low registers.
12290  * Each bit controls the masking of the bytes. You can filter a group of addresses
12291  * (known as group address filtering) by masking one or more bytes of the address.
12292  *
12293  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12294  *
12295  * Field Enumeration Values:
12296  *
12297  * Enum | Value | Description
12298  * :----------------------------------------------|:------|:------------------------------------
12299  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12300  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12301  *
12302  * Field Access Macros:
12303  *
12304  */
12305 /*
12306  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
12307  *
12308  * Byte is unmasked (i.e. is compared)
12309  */
12310 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED 0x0
12311 /*
12312  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
12313  *
12314  * Byte is masked (i.e. not compared)
12315  */
12316 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED 0x1
12317 
12318 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
12319 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_LSB 24
12320 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
12321 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_MSB 24
12322 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
12323 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_WIDTH 1
12324 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
12325 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET_MSK 0x01000000
12326 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
12327 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_CLR_MSK 0xfeffffff
12328 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
12329 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_RESET 0x0
12330 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 field value from a register. */
12331 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
12332 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value suitable for setting the register. */
12333 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
12334 
12335 /*
12336  * Field : Mask Byte Control - mbc_1
12337  *
12338  * This array of bits are mask control bits for comparison of each of the MAC
12339  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12340  * received DA or SA with the contents of MAC Address13 high and low registers.
12341  * Each bit controls the masking of the bytes. You can filter a group of addresses
12342  * (known as group address filtering) by masking one or more bytes of the address.
12343  *
12344  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12345  *
12346  * Field Enumeration Values:
12347  *
12348  * Enum | Value | Description
12349  * :----------------------------------------------|:------|:------------------------------------
12350  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12351  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12352  *
12353  * Field Access Macros:
12354  *
12355  */
12356 /*
12357  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
12358  *
12359  * Byte is unmasked (i.e. is compared)
12360  */
12361 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED 0x0
12362 /*
12363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
12364  *
12365  * Byte is masked (i.e. not compared)
12366  */
12367 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED 0x1
12368 
12369 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
12370 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_LSB 25
12371 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
12372 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_MSB 25
12373 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
12374 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_WIDTH 1
12375 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
12376 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET_MSK 0x02000000
12377 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
12378 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_CLR_MSK 0xfdffffff
12379 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
12380 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_RESET 0x0
12381 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 field value from a register. */
12382 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
12383 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value suitable for setting the register. */
12384 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
12385 
12386 /*
12387  * Field : Mask Byte Control - mbc_2
12388  *
12389  * This array of bits are mask control bits for comparison of each of the MAC
12390  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12391  * received DA or SA with the contents of MAC Address13 high and low registers.
12392  * Each bit controls the masking of the bytes. You can filter a group of addresses
12393  * (known as group address filtering) by masking one or more bytes of the address.
12394  *
12395  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12396  *
12397  * Field Enumeration Values:
12398  *
12399  * Enum | Value | Description
12400  * :----------------------------------------------|:------|:------------------------------------
12401  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12402  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12403  *
12404  * Field Access Macros:
12405  *
12406  */
12407 /*
12408  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
12409  *
12410  * Byte is unmasked (i.e. is compared)
12411  */
12412 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED 0x0
12413 /*
12414  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
12415  *
12416  * Byte is masked (i.e. not compared)
12417  */
12418 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED 0x1
12419 
12420 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
12421 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_LSB 26
12422 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
12423 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_MSB 26
12424 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
12425 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_WIDTH 1
12426 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
12427 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET_MSK 0x04000000
12428 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
12429 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_CLR_MSK 0xfbffffff
12430 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
12431 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_RESET 0x0
12432 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 field value from a register. */
12433 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
12434 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value suitable for setting the register. */
12435 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
12436 
12437 /*
12438  * Field : Mask Byte Control - mbc_3
12439  *
12440  * This array of bits are mask control bits for comparison of each of the MAC
12441  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12442  * received DA or SA with the contents of MAC Address13 high and low registers.
12443  * Each bit controls the masking of the bytes. You can filter a group of addresses
12444  * (known as group address filtering) by masking one or more bytes of the address.
12445  *
12446  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12447  *
12448  * Field Enumeration Values:
12449  *
12450  * Enum | Value | Description
12451  * :----------------------------------------------|:------|:------------------------------------
12452  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12453  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12454  *
12455  * Field Access Macros:
12456  *
12457  */
12458 /*
12459  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
12460  *
12461  * Byte is unmasked (i.e. is compared)
12462  */
12463 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED 0x0
12464 /*
12465  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
12466  *
12467  * Byte is masked (i.e. not compared)
12468  */
12469 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED 0x1
12470 
12471 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
12472 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_LSB 27
12473 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
12474 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_MSB 27
12475 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
12476 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_WIDTH 1
12477 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
12478 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET_MSK 0x08000000
12479 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
12480 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_CLR_MSK 0xf7ffffff
12481 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
12482 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_RESET 0x0
12483 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 field value from a register. */
12484 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
12485 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value suitable for setting the register. */
12486 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
12487 
12488 /*
12489  * Field : Mask Byte Control - mbc_4
12490  *
12491  * This array of bits are mask control bits for comparison of each of the MAC
12492  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12493  * received DA or SA with the contents of MAC Address13 high and low registers.
12494  * Each bit controls the masking of the bytes. You can filter a group of addresses
12495  * (known as group address filtering) by masking one or more bytes of the address.
12496  *
12497  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12498  *
12499  * Field Enumeration Values:
12500  *
12501  * Enum | Value | Description
12502  * :----------------------------------------------|:------|:------------------------------------
12503  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12504  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12505  *
12506  * Field Access Macros:
12507  *
12508  */
12509 /*
12510  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
12511  *
12512  * Byte is unmasked (i.e. is compared)
12513  */
12514 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED 0x0
12515 /*
12516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
12517  *
12518  * Byte is masked (i.e. not compared)
12519  */
12520 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED 0x1
12521 
12522 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
12523 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_LSB 28
12524 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
12525 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_MSB 28
12526 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
12527 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_WIDTH 1
12528 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
12529 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET_MSK 0x10000000
12530 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
12531 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_CLR_MSK 0xefffffff
12532 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
12533 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_RESET 0x0
12534 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 field value from a register. */
12535 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
12536 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value suitable for setting the register. */
12537 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
12538 
12539 /*
12540  * Field : Mask Byte Control - mbc_5
12541  *
12542  * This array of bits are mask control bits for comparison of each of the MAC
12543  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12544  * received DA or SA with the contents of MAC Address13 high and low registers.
12545  * Each bit controls the masking of the bytes. You can filter a group of addresses
12546  * (known as group address filtering) by masking one or more bytes of the address.
12547  *
12548  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12549  *
12550  * Field Enumeration Values:
12551  *
12552  * Enum | Value | Description
12553  * :----------------------------------------------|:------|:------------------------------------
12554  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12555  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12556  *
12557  * Field Access Macros:
12558  *
12559  */
12560 /*
12561  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
12562  *
12563  * Byte is unmasked (i.e. is compared)
12564  */
12565 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED 0x0
12566 /*
12567  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
12568  *
12569  * Byte is masked (i.e. not compared)
12570  */
12571 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED 0x1
12572 
12573 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
12574 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_LSB 29
12575 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
12576 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_MSB 29
12577 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
12578 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_WIDTH 1
12579 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
12580 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET_MSK 0x20000000
12581 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
12582 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_CLR_MSK 0xdfffffff
12583 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
12584 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_RESET 0x0
12585 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 field value from a register. */
12586 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
12587 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value suitable for setting the register. */
12588 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
12589 
12590 /*
12591  * Field : Source Address - sa
12592  *
12593  * When this bit is enabled, the MAC Address13[47:0] is used to compare with the SA
12594  * fields of the received frame. When this bit is disabled, the MAC Address13[47:0]
12595  * is used to compare with the DA fields of the received frame.
12596  *
12597  * Field Enumeration Values:
12598  *
12599  * Enum | Value | Description
12600  * :----------------------------------------|:------|:-----------------------------
12601  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
12602  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END | 0x1 | MAC address compare enabled
12603  *
12604  * Field Access Macros:
12605  *
12606  */
12607 /*
12608  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
12609  *
12610  * MAC address compare disabled
12611  */
12612 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD 0x0
12613 /*
12614  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
12615  *
12616  * MAC address compare enabled
12617  */
12618 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END 0x1
12619 
12620 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
12621 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_LSB 30
12622 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
12623 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_MSB 30
12624 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
12625 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_WIDTH 1
12626 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
12627 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET_MSK 0x40000000
12628 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
12629 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_CLR_MSK 0xbfffffff
12630 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
12631 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_RESET 0x0
12632 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA field value from a register. */
12633 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
12634 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value suitable for setting the register. */
12635 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
12636 
12637 /*
12638  * Field : Address Enable - ae
12639  *
12640  * When this bit is enabled, the address filter block uses the 14th MAC address for
12641  * perfect filtering. When this bit is disabled, the address filter block ignores
12642  * the address for filtering.
12643  *
12644  * Field Enumeration Values:
12645  *
12646  * Enum | Value | Description
12647  * :----------------------------------------|:------|:--------------------------------------
12648  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
12649  * ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
12650  *
12651  * Field Access Macros:
12652  *
12653  */
12654 /*
12655  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
12656  *
12657  * Second MAC address filtering disabled
12658  */
12659 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD 0x0
12660 /*
12661  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
12662  *
12663  * Second MAC address filtering enabled
12664  */
12665 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END 0x1
12666 
12667 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
12668 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_LSB 31
12669 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
12670 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_MSB 31
12671 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
12672 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_WIDTH 1
12673 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
12674 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET_MSK 0x80000000
12675 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
12676 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_CLR_MSK 0x7fffffff
12677 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
12678 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_RESET 0x0
12679 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE field value from a register. */
12680 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
12681 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value suitable for setting the register. */
12682 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
12683 
12684 #ifndef __ASSEMBLY__
12685 /*
12686  * WARNING: The C register and register group struct declarations are provided for
12687  * convenience and illustrative purposes. They should, however, be used with
12688  * caution as the C language standard provides no guarantees about the alignment or
12689  * atomicity of device memory accesses. The recommended practice for writing
12690  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12691  * alt_write_word() functions.
12692  *
12693  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH.
12694  */
12695 struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s
12696 {
12697  uint32_t addrhi : 16; /* MAC Address13 [47:32] */
12698  uint32_t : 8; /* *UNDEFINED* */
12699  uint32_t mbc_0 : 1; /* Mask Byte Control */
12700  uint32_t mbc_1 : 1; /* Mask Byte Control */
12701  uint32_t mbc_2 : 1; /* Mask Byte Control */
12702  uint32_t mbc_3 : 1; /* Mask Byte Control */
12703  uint32_t mbc_4 : 1; /* Mask Byte Control */
12704  uint32_t mbc_5 : 1; /* Mask Byte Control */
12705  uint32_t sa : 1; /* Source Address */
12706  uint32_t ae : 1; /* Address Enable */
12707 };
12708 
12709 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH. */
12710 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t;
12711 #endif /* __ASSEMBLY__ */
12712 
12713 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register from the beginning of the component. */
12714 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST 0xa8
12715 /* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register. */
12716 #define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST))
12717 
12718 /*
12719  * Register : Register 43 (MAC Address13 Low Register) - MAC_Address13_Low
12720  *
12721  * The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC
12722  * address of the station.
12723  *
12724  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
12725  * format.
12726  *
12727  * Register Layout
12728  *
12729  * Bits | Access | Reset | Description
12730  * :-------|:-------|:-----------|:---------------------
12731  * [31:0] | RW | 0xffffffff | MAC Address13 [31:0]
12732  *
12733  */
12734 /*
12735  * Field : MAC Address13 [31:0] - addrlo
12736  *
12737  * This field contains the lower 32 bits of the 14th 6-byte MAC address. The
12738  * content of this field is undefined until loaded by software after the
12739  * initialization process.
12740  *
12741  * Field Access Macros:
12742  *
12743  */
12744 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
12745 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_LSB 0
12746 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
12747 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_MSB 31
12748 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
12749 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_WIDTH 32
12750 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
12751 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET_MSK 0xffffffff
12752 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
12753 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_CLR_MSK 0x00000000
12754 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
12755 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_RESET 0xffffffff
12756 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO field value from a register. */
12757 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
12758 /* Produces a ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value suitable for setting the register. */
12759 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
12760 
12761 #ifndef __ASSEMBLY__
12762 /*
12763  * WARNING: The C register and register group struct declarations are provided for
12764  * convenience and illustrative purposes. They should, however, be used with
12765  * caution as the C language standard provides no guarantees about the alignment or
12766  * atomicity of device memory accesses. The recommended practice for writing
12767  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12768  * alt_write_word() functions.
12769  *
12770  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW.
12771  */
12772 struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s
12773 {
12774  uint32_t addrlo : 32; /* MAC Address13 [31:0] */
12775 };
12776 
12777 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW. */
12778 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s ALT_EMAC_GMAC_MAC_ADDR13_LOW_t;
12779 #endif /* __ASSEMBLY__ */
12780 
12781 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register from the beginning of the component. */
12782 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST 0xac
12783 /* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register. */
12784 #define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST))
12785 
12786 /*
12787  * Register : Register 44 (MAC Address14 High Register) - MAC_Address14_High
12788  *
12789  * The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC
12790  * address of the station. Because the MAC address registers are configured to be
12791  * double-synchronized to the (G)MII clock domains, the synchronization is
12792  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
12793  * endian mode) of the MAC Address14 Low Register are written. For proper
12794  * synchronization updates, the consecutive writes to this Address Low Register
12795  * should be performed after at least four clock cycles in the destination clock
12796  * domain.
12797  *
12798  * Note that all MAC Address High registers (except MAC Address0 High) have the
12799  * same format.
12800  *
12801  * Register Layout
12802  *
12803  * Bits | Access | Reset | Description
12804  * :--------|:-------|:-------|:----------------------
12805  * [15:0] | RW | 0xffff | MAC Address14 [47:32]
12806  * [23:16] | ??? | 0x0 | *UNDEFINED*
12807  * [24] | RW | 0x0 | Mask Byte Control
12808  * [25] | RW | 0x0 | Mask Byte Control
12809  * [26] | RW | 0x0 | Mask Byte Control
12810  * [27] | RW | 0x0 | Mask Byte Control
12811  * [28] | RW | 0x0 | Mask Byte Control
12812  * [29] | RW | 0x0 | Mask Byte Control
12813  * [30] | RW | 0x0 | Source Address
12814  * [31] | RW | 0x0 | Address Enable
12815  *
12816  */
12817 /*
12818  * Field : MAC Address14 [47:32] - addrhi
12819  *
12820  * This field contains the upper 16 bits (47:32) of the 15th 6-byte MAC address.
12821  *
12822  * Field Access Macros:
12823  *
12824  */
12825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
12826 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_LSB 0
12827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
12828 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_MSB 15
12829 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
12830 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_WIDTH 16
12831 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
12832 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET_MSK 0x0000ffff
12833 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
12834 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_CLR_MSK 0xffff0000
12835 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
12836 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_RESET 0xffff
12837 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI field value from a register. */
12838 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
12839 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value suitable for setting the register. */
12840 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
12841 
12842 /*
12843  * Field : Mask Byte Control - mbc_0
12844  *
12845  * This array of bits are mask control bits for comparison of each of the MAC
12846  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12847  * received DA or SA with the contents of MAC Address14 high and low registers.
12848  * Each bit controls the masking of the bytes. You can filter a group of addresses
12849  * (known as group address filtering) by masking one or more bytes of the address.
12850  *
12851  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12852  *
12853  * Field Enumeration Values:
12854  *
12855  * Enum | Value | Description
12856  * :----------------------------------------------|:------|:------------------------------------
12857  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12858  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12859  *
12860  * Field Access Macros:
12861  *
12862  */
12863 /*
12864  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
12865  *
12866  * Byte is unmasked (i.e. is compared)
12867  */
12868 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED 0x0
12869 /*
12870  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
12871  *
12872  * Byte is masked (i.e. not compared)
12873  */
12874 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED 0x1
12875 
12876 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
12877 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_LSB 24
12878 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
12879 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_MSB 24
12880 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
12881 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_WIDTH 1
12882 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
12883 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET_MSK 0x01000000
12884 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
12885 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_CLR_MSK 0xfeffffff
12886 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
12887 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_RESET 0x0
12888 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 field value from a register. */
12889 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
12890 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value suitable for setting the register. */
12891 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
12892 
12893 /*
12894  * Field : Mask Byte Control - mbc_1
12895  *
12896  * This array of bits are mask control bits for comparison of each of the MAC
12897  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12898  * received DA or SA with the contents of MAC Address14 high and low registers.
12899  * Each bit controls the masking of the bytes. You can filter a group of addresses
12900  * (known as group address filtering) by masking one or more bytes of the address.
12901  *
12902  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12903  *
12904  * Field Enumeration Values:
12905  *
12906  * Enum | Value | Description
12907  * :----------------------------------------------|:------|:------------------------------------
12908  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12909  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12910  *
12911  * Field Access Macros:
12912  *
12913  */
12914 /*
12915  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
12916  *
12917  * Byte is unmasked (i.e. is compared)
12918  */
12919 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED 0x0
12920 /*
12921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
12922  *
12923  * Byte is masked (i.e. not compared)
12924  */
12925 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED 0x1
12926 
12927 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
12928 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_LSB 25
12929 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
12930 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_MSB 25
12931 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
12932 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_WIDTH 1
12933 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
12934 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET_MSK 0x02000000
12935 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
12936 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_CLR_MSK 0xfdffffff
12937 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
12938 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_RESET 0x0
12939 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 field value from a register. */
12940 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
12941 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value suitable for setting the register. */
12942 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
12943 
12944 /*
12945  * Field : Mask Byte Control - mbc_2
12946  *
12947  * This array of bits are mask control bits for comparison of each of the MAC
12948  * Address bytes. When masked, the MAC does not compare the corresponding byte of
12949  * received DA or SA with the contents of MAC Address14 high and low registers.
12950  * Each bit controls the masking of the bytes. You can filter a group of addresses
12951  * (known as group address filtering) by masking one or more bytes of the address.
12952  *
12953  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
12954  *
12955  * Field Enumeration Values:
12956  *
12957  * Enum | Value | Description
12958  * :----------------------------------------------|:------|:------------------------------------
12959  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
12960  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
12961  *
12962  * Field Access Macros:
12963  *
12964  */
12965 /*
12966  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
12967  *
12968  * Byte is unmasked (i.e. is compared)
12969  */
12970 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED 0x0
12971 /*
12972  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
12973  *
12974  * Byte is masked (i.e. not compared)
12975  */
12976 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED 0x1
12977 
12978 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
12979 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_LSB 26
12980 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
12981 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_MSB 26
12982 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
12983 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_WIDTH 1
12984 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
12985 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET_MSK 0x04000000
12986 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
12987 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_CLR_MSK 0xfbffffff
12988 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
12989 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_RESET 0x0
12990 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 field value from a register. */
12991 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
12992 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value suitable for setting the register. */
12993 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
12994 
12995 /*
12996  * Field : Mask Byte Control - mbc_3
12997  *
12998  * This array of bits are mask control bits for comparison of each of the MAC
12999  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13000  * received DA or SA with the contents of MAC Address14 high and low registers.
13001  * Each bit controls the masking of the bytes. You can filter a group of addresses
13002  * (known as group address filtering) by masking one or more bytes of the address.
13003  *
13004  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13005  *
13006  * Field Enumeration Values:
13007  *
13008  * Enum | Value | Description
13009  * :----------------------------------------------|:------|:------------------------------------
13010  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13011  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13012  *
13013  * Field Access Macros:
13014  *
13015  */
13016 /*
13017  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
13018  *
13019  * Byte is unmasked (i.e. is compared)
13020  */
13021 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED 0x0
13022 /*
13023  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
13024  *
13025  * Byte is masked (i.e. not compared)
13026  */
13027 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED 0x1
13028 
13029 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
13030 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_LSB 27
13031 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
13032 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_MSB 27
13033 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
13034 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_WIDTH 1
13035 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
13036 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET_MSK 0x08000000
13037 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
13038 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_CLR_MSK 0xf7ffffff
13039 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
13040 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_RESET 0x0
13041 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 field value from a register. */
13042 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
13043 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value suitable for setting the register. */
13044 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
13045 
13046 /*
13047  * Field : Mask Byte Control - mbc_4
13048  *
13049  * This array of bits are mask control bits for comparison of each of the MAC
13050  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13051  * received DA or SA with the contents of MAC Address14 high and low registers.
13052  * Each bit controls the masking of the bytes. You can filter a group of addresses
13053  * (known as group address filtering) by masking one or more bytes of the address.
13054  *
13055  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13056  *
13057  * Field Enumeration Values:
13058  *
13059  * Enum | Value | Description
13060  * :----------------------------------------------|:------|:------------------------------------
13061  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13062  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13063  *
13064  * Field Access Macros:
13065  *
13066  */
13067 /*
13068  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
13069  *
13070  * Byte is unmasked (i.e. is compared)
13071  */
13072 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED 0x0
13073 /*
13074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
13075  *
13076  * Byte is masked (i.e. not compared)
13077  */
13078 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED 0x1
13079 
13080 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
13081 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_LSB 28
13082 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
13083 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_MSB 28
13084 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
13085 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_WIDTH 1
13086 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
13087 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET_MSK 0x10000000
13088 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
13089 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_CLR_MSK 0xefffffff
13090 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
13091 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_RESET 0x0
13092 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 field value from a register. */
13093 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
13094 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value suitable for setting the register. */
13095 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
13096 
13097 /*
13098  * Field : Mask Byte Control - mbc_5
13099  *
13100  * This array of bits are mask control bits for comparison of each of the MAC
13101  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13102  * received DA or SA with the contents of MAC Address14 high and low registers.
13103  * Each bit controls the masking of the bytes. You can filter a group of addresses
13104  * (known as group address filtering) by masking one or more bytes of the address.
13105  *
13106  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13107  *
13108  * Field Enumeration Values:
13109  *
13110  * Enum | Value | Description
13111  * :----------------------------------------------|:------|:------------------------------------
13112  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13113  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13114  *
13115  * Field Access Macros:
13116  *
13117  */
13118 /*
13119  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
13120  *
13121  * Byte is unmasked (i.e. is compared)
13122  */
13123 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED 0x0
13124 /*
13125  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
13126  *
13127  * Byte is masked (i.e. not compared)
13128  */
13129 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED 0x1
13130 
13131 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
13132 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_LSB 29
13133 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
13134 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_MSB 29
13135 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
13136 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_WIDTH 1
13137 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
13138 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET_MSK 0x20000000
13139 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
13140 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_CLR_MSK 0xdfffffff
13141 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
13142 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_RESET 0x0
13143 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 field value from a register. */
13144 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
13145 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value suitable for setting the register. */
13146 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
13147 
13148 /*
13149  * Field : Source Address - sa
13150  *
13151  * When this bit is enabled, the MAC Address14[47:0] is used to compare with the SA
13152  * fields of the received frame. When this bit is disabled, the MAC Address14[47:0]
13153  * is used to compare with the DA fields of the received frame.
13154  *
13155  * Field Enumeration Values:
13156  *
13157  * Enum | Value | Description
13158  * :----------------------------------------|:------|:-----------------------------
13159  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
13160  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END | 0x1 | MAC address compare enabled
13161  *
13162  * Field Access Macros:
13163  *
13164  */
13165 /*
13166  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
13167  *
13168  * MAC address compare disabled
13169  */
13170 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD 0x0
13171 /*
13172  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
13173  *
13174  * MAC address compare enabled
13175  */
13176 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END 0x1
13177 
13178 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
13179 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_LSB 30
13180 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
13181 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_MSB 30
13182 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
13183 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_WIDTH 1
13184 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
13185 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET_MSK 0x40000000
13186 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
13187 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_CLR_MSK 0xbfffffff
13188 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
13189 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_RESET 0x0
13190 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA field value from a register. */
13191 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
13192 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value suitable for setting the register. */
13193 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
13194 
13195 /*
13196  * Field : Address Enable - ae
13197  *
13198  * When this bit is enabled, the address filter block uses the 15th MAC address for
13199  * perfect filtering. When this bit is disabled, the address filter block ignores
13200  * the address for filtering.
13201  *
13202  * Field Enumeration Values:
13203  *
13204  * Enum | Value | Description
13205  * :----------------------------------------|:------|:--------------------------------------
13206  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
13207  * ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
13208  *
13209  * Field Access Macros:
13210  *
13211  */
13212 /*
13213  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
13214  *
13215  * Second MAC address filtering disabled
13216  */
13217 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD 0x0
13218 /*
13219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
13220  *
13221  * Second MAC address filtering enabled
13222  */
13223 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END 0x1
13224 
13225 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
13226 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_LSB 31
13227 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
13228 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_MSB 31
13229 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
13230 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_WIDTH 1
13231 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
13232 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET_MSK 0x80000000
13233 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
13234 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_CLR_MSK 0x7fffffff
13235 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
13236 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_RESET 0x0
13237 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE field value from a register. */
13238 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
13239 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value suitable for setting the register. */
13240 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
13241 
13242 #ifndef __ASSEMBLY__
13243 /*
13244  * WARNING: The C register and register group struct declarations are provided for
13245  * convenience and illustrative purposes. They should, however, be used with
13246  * caution as the C language standard provides no guarantees about the alignment or
13247  * atomicity of device memory accesses. The recommended practice for writing
13248  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13249  * alt_write_word() functions.
13250  *
13251  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH.
13252  */
13253 struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s
13254 {
13255  uint32_t addrhi : 16; /* MAC Address14 [47:32] */
13256  uint32_t : 8; /* *UNDEFINED* */
13257  uint32_t mbc_0 : 1; /* Mask Byte Control */
13258  uint32_t mbc_1 : 1; /* Mask Byte Control */
13259  uint32_t mbc_2 : 1; /* Mask Byte Control */
13260  uint32_t mbc_3 : 1; /* Mask Byte Control */
13261  uint32_t mbc_4 : 1; /* Mask Byte Control */
13262  uint32_t mbc_5 : 1; /* Mask Byte Control */
13263  uint32_t sa : 1; /* Source Address */
13264  uint32_t ae : 1; /* Address Enable */
13265 };
13266 
13267 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH. */
13268 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t;
13269 #endif /* __ASSEMBLY__ */
13270 
13271 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register from the beginning of the component. */
13272 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST 0xb0
13273 /* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register. */
13274 #define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST))
13275 
13276 /*
13277  * Register : Register 45 (MAC Address14 Low Register) - MAC_Address14_Low
13278  *
13279  * The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC
13280  * address of the station.
13281  *
13282  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
13283  * format.
13284  *
13285  * Register Layout
13286  *
13287  * Bits | Access | Reset | Description
13288  * :-------|:-------|:-----------|:---------------------
13289  * [31:0] | RW | 0xffffffff | MAC Address14 [31:0]
13290  *
13291  */
13292 /*
13293  * Field : MAC Address14 [31:0] - addrlo
13294  *
13295  * This field contains the lower 32 bits of the 15th 6-byte MAC address. The
13296  * content of this field is undefined until loaded by software after the
13297  * initialization process.
13298  *
13299  * Field Access Macros:
13300  *
13301  */
13302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
13303 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_LSB 0
13304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
13305 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_MSB 31
13306 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
13307 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_WIDTH 32
13308 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
13309 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET_MSK 0xffffffff
13310 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
13311 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_CLR_MSK 0x00000000
13312 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
13313 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_RESET 0xffffffff
13314 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO field value from a register. */
13315 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
13316 /* Produces a ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value suitable for setting the register. */
13317 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
13318 
13319 #ifndef __ASSEMBLY__
13320 /*
13321  * WARNING: The C register and register group struct declarations are provided for
13322  * convenience and illustrative purposes. They should, however, be used with
13323  * caution as the C language standard provides no guarantees about the alignment or
13324  * atomicity of device memory accesses. The recommended practice for writing
13325  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13326  * alt_write_word() functions.
13327  *
13328  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW.
13329  */
13330 struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s
13331 {
13332  uint32_t addrlo : 32; /* MAC Address14 [31:0] */
13333 };
13334 
13335 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW. */
13336 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s ALT_EMAC_GMAC_MAC_ADDR14_LOW_t;
13337 #endif /* __ASSEMBLY__ */
13338 
13339 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register from the beginning of the component. */
13340 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST 0xb4
13341 /* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register. */
13342 #define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST))
13343 
13344 /*
13345  * Register : Register 46 (MAC Address15 High Register) - MAC_Address15_High
13346  *
13347  * The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC
13348  * address of the station. Because the MAC address registers are configured to be
13349  * double-synchronized to the (G)MII clock domains, the synchronization is
13350  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
13351  * endian mode) of the MAC Address15 Low Register are written. For proper
13352  * synchronization updates, the consecutive writes to this Address Low Register
13353  * should be performed after at least four clock cycles in the destination clock
13354  * domain.
13355  *
13356  * Note that all MAC Address High registers (except MAC Address0 High) have the
13357  * same format.
13358  *
13359  * Register Layout
13360  *
13361  * Bits | Access | Reset | Description
13362  * :--------|:-------|:-------|:----------------------
13363  * [15:0] | RW | 0xffff | MAC Address15 [47:32]
13364  * [23:16] | ??? | 0x0 | *UNDEFINED*
13365  * [24] | RW | 0x0 | Mask Byte Control
13366  * [25] | RW | 0x0 | Mask Byte Control
13367  * [26] | RW | 0x0 | Mask Byte Control
13368  * [27] | RW | 0x0 | Mask Byte Control
13369  * [28] | RW | 0x0 | Mask Byte Control
13370  * [29] | RW | 0x0 | Mask Byte Control
13371  * [30] | RW | 0x0 | Source Address
13372  * [31] | RW | 0x0 | Address Enable
13373  *
13374  */
13375 /*
13376  * Field : MAC Address15 [47:32] - addrhi
13377  *
13378  * This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address.
13379  *
13380  * Field Access Macros:
13381  *
13382  */
13383 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
13384 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_LSB 0
13385 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
13386 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_MSB 15
13387 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
13388 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_WIDTH 16
13389 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
13390 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET_MSK 0x0000ffff
13391 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
13392 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_CLR_MSK 0xffff0000
13393 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
13394 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_RESET 0xffff
13395 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI field value from a register. */
13396 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
13397 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value suitable for setting the register. */
13398 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
13399 
13400 /*
13401  * Field : Mask Byte Control - mbc_0
13402  *
13403  * This array of bits are mask control bits for comparison of each of the MAC
13404  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13405  * received DA or SA with the contents of MAC Address15 high and low registers.
13406  * Each bit controls the masking of the bytes. You can filter a group of addresses
13407  * (known as group address filtering) by masking one or more bytes of the address.
13408  *
13409  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13410  *
13411  * Field Enumeration Values:
13412  *
13413  * Enum | Value | Description
13414  * :----------------------------------------------|:------|:------------------------------------
13415  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13416  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13417  *
13418  * Field Access Macros:
13419  *
13420  */
13421 /*
13422  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
13423  *
13424  * Byte is unmasked (i.e. is compared)
13425  */
13426 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED 0x0
13427 /*
13428  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
13429  *
13430  * Byte is masked (i.e. not compared)
13431  */
13432 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED 0x1
13433 
13434 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
13435 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_LSB 24
13436 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
13437 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_MSB 24
13438 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
13439 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_WIDTH 1
13440 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
13441 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET_MSK 0x01000000
13442 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
13443 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_CLR_MSK 0xfeffffff
13444 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
13445 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_RESET 0x0
13446 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 field value from a register. */
13447 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
13448 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value suitable for setting the register. */
13449 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
13450 
13451 /*
13452  * Field : Mask Byte Control - mbc_1
13453  *
13454  * This array of bits are mask control bits for comparison of each of the MAC
13455  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13456  * received DA or SA with the contents of MAC Address15 high and low registers.
13457  * Each bit controls the masking of the bytes. You can filter a group of addresses
13458  * (known as group address filtering) by masking one or more bytes of the address.
13459  *
13460  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13461  *
13462  * Field Enumeration Values:
13463  *
13464  * Enum | Value | Description
13465  * :----------------------------------------------|:------|:------------------------------------
13466  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13467  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13468  *
13469  * Field Access Macros:
13470  *
13471  */
13472 /*
13473  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
13474  *
13475  * Byte is unmasked (i.e. is compared)
13476  */
13477 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED 0x0
13478 /*
13479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
13480  *
13481  * Byte is masked (i.e. not compared)
13482  */
13483 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED 0x1
13484 
13485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
13486 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_LSB 25
13487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
13488 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_MSB 25
13489 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
13490 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_WIDTH 1
13491 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
13492 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET_MSK 0x02000000
13493 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
13494 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_CLR_MSK 0xfdffffff
13495 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
13496 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_RESET 0x0
13497 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 field value from a register. */
13498 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
13499 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value suitable for setting the register. */
13500 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
13501 
13502 /*
13503  * Field : Mask Byte Control - mbc_2
13504  *
13505  * This array of bits are mask control bits for comparison of each of the MAC
13506  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13507  * received DA or SA with the contents of MAC Address15 high and low registers.
13508  * Each bit controls the masking of the bytes. You can filter a group of addresses
13509  * (known as group address filtering) by masking one or more bytes of the address.
13510  *
13511  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13512  *
13513  * Field Enumeration Values:
13514  *
13515  * Enum | Value | Description
13516  * :----------------------------------------------|:------|:------------------------------------
13517  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13518  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13519  *
13520  * Field Access Macros:
13521  *
13522  */
13523 /*
13524  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
13525  *
13526  * Byte is unmasked (i.e. is compared)
13527  */
13528 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED 0x0
13529 /*
13530  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
13531  *
13532  * Byte is masked (i.e. not compared)
13533  */
13534 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED 0x1
13535 
13536 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
13537 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_LSB 26
13538 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
13539 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_MSB 26
13540 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
13541 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_WIDTH 1
13542 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
13543 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET_MSK 0x04000000
13544 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
13545 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_CLR_MSK 0xfbffffff
13546 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
13547 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_RESET 0x0
13548 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 field value from a register. */
13549 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
13550 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value suitable for setting the register. */
13551 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
13552 
13553 /*
13554  * Field : Mask Byte Control - mbc_3
13555  *
13556  * This array of bits are mask control bits for comparison of each of the MAC
13557  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13558  * received DA or SA with the contents of MAC Address15 high and low registers.
13559  * Each bit controls the masking of the bytes. You can filter a group of addresses
13560  * (known as group address filtering) by masking one or more bytes of the address.
13561  *
13562  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13563  *
13564  * Field Enumeration Values:
13565  *
13566  * Enum | Value | Description
13567  * :----------------------------------------------|:------|:------------------------------------
13568  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13569  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13570  *
13571  * Field Access Macros:
13572  *
13573  */
13574 /*
13575  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
13576  *
13577  * Byte is unmasked (i.e. is compared)
13578  */
13579 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED 0x0
13580 /*
13581  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
13582  *
13583  * Byte is masked (i.e. not compared)
13584  */
13585 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED 0x1
13586 
13587 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
13588 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_LSB 27
13589 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
13590 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_MSB 27
13591 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
13592 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_WIDTH 1
13593 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
13594 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET_MSK 0x08000000
13595 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
13596 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_CLR_MSK 0xf7ffffff
13597 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
13598 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_RESET 0x0
13599 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 field value from a register. */
13600 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
13601 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value suitable for setting the register. */
13602 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
13603 
13604 /*
13605  * Field : Mask Byte Control - mbc_4
13606  *
13607  * This array of bits are mask control bits for comparison of each of the MAC
13608  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13609  * received DA or SA with the contents of MAC Address15 high and low registers.
13610  * Each bit controls the masking of the bytes. You can filter a group of addresses
13611  * (known as group address filtering) by masking one or more bytes of the address.
13612  *
13613  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13614  *
13615  * Field Enumeration Values:
13616  *
13617  * Enum | Value | Description
13618  * :----------------------------------------------|:------|:------------------------------------
13619  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13620  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13621  *
13622  * Field Access Macros:
13623  *
13624  */
13625 /*
13626  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
13627  *
13628  * Byte is unmasked (i.e. is compared)
13629  */
13630 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED 0x0
13631 /*
13632  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
13633  *
13634  * Byte is masked (i.e. not compared)
13635  */
13636 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED 0x1
13637 
13638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
13639 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_LSB 28
13640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
13641 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_MSB 28
13642 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
13643 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_WIDTH 1
13644 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
13645 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET_MSK 0x10000000
13646 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
13647 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_CLR_MSK 0xefffffff
13648 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
13649 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_RESET 0x0
13650 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 field value from a register. */
13651 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
13652 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value suitable for setting the register. */
13653 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
13654 
13655 /*
13656  * Field : Mask Byte Control - mbc_5
13657  *
13658  * This array of bits are mask control bits for comparison of each of the MAC
13659  * Address bytes. When masked, the MAC does not compare the corresponding byte of
13660  * received DA or SA with the contents of MAC Address15 high and low registers.
13661  * Each bit controls the masking of the bytes. You can filter a group of addresses
13662  * (known as group address filtering) by masking one or more bytes of the address.
13663  *
13664  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
13665  *
13666  * Field Enumeration Values:
13667  *
13668  * Enum | Value | Description
13669  * :----------------------------------------------|:------|:------------------------------------
13670  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
13671  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
13672  *
13673  * Field Access Macros:
13674  *
13675  */
13676 /*
13677  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
13678  *
13679  * Byte is unmasked (i.e. is compared)
13680  */
13681 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED 0x0
13682 /*
13683  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
13684  *
13685  * Byte is masked (i.e. not compared)
13686  */
13687 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED 0x1
13688 
13689 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
13690 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_LSB 29
13691 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
13692 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_MSB 29
13693 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
13694 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_WIDTH 1
13695 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
13696 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET_MSK 0x20000000
13697 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
13698 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_CLR_MSK 0xdfffffff
13699 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
13700 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_RESET 0x0
13701 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 field value from a register. */
13702 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
13703 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value suitable for setting the register. */
13704 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
13705 
13706 /*
13707  * Field : Source Address - sa
13708  *
13709  * When this bit is enabled, the MAC Address15[47:0] is used to compare with the SA
13710  * fields of the received frame. When this bit is disabled, the MAC Address15[47:0]
13711  * is used to compare with the DA fields of the received frame.
13712  *
13713  * Field Enumeration Values:
13714  *
13715  * Enum | Value | Description
13716  * :----------------------------------------|:------|:-----------------------------
13717  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
13718  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END | 0x1 | MAC address compare enabled
13719  *
13720  * Field Access Macros:
13721  *
13722  */
13723 /*
13724  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
13725  *
13726  * MAC address compare disabled
13727  */
13728 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD 0x0
13729 /*
13730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
13731  *
13732  * MAC address compare enabled
13733  */
13734 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END 0x1
13735 
13736 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
13737 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_LSB 30
13738 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
13739 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_MSB 30
13740 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
13741 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_WIDTH 1
13742 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
13743 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET_MSK 0x40000000
13744 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
13745 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_CLR_MSK 0xbfffffff
13746 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
13747 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_RESET 0x0
13748 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA field value from a register. */
13749 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
13750 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value suitable for setting the register. */
13751 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
13752 
13753 /*
13754  * Field : Address Enable - ae
13755  *
13756  * When this bit is enabled, the address filter block uses the 16th MAC address for
13757  * perfect filtering. When this bit is disabled, the address filter block ignores
13758  * the address for filtering.
13759  *
13760  * Field Enumeration Values:
13761  *
13762  * Enum | Value | Description
13763  * :----------------------------------------|:------|:--------------------------------------
13764  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
13765  * ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
13766  *
13767  * Field Access Macros:
13768  *
13769  */
13770 /*
13771  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
13772  *
13773  * Second MAC address filtering disabled
13774  */
13775 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD 0x0
13776 /*
13777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
13778  *
13779  * Second MAC address filtering enabled
13780  */
13781 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END 0x1
13782 
13783 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
13784 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_LSB 31
13785 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
13786 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_MSB 31
13787 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
13788 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_WIDTH 1
13789 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
13790 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET_MSK 0x80000000
13791 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
13792 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_CLR_MSK 0x7fffffff
13793 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
13794 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_RESET 0x0
13795 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE field value from a register. */
13796 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
13797 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value suitable for setting the register. */
13798 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
13799 
13800 #ifndef __ASSEMBLY__
13801 /*
13802  * WARNING: The C register and register group struct declarations are provided for
13803  * convenience and illustrative purposes. They should, however, be used with
13804  * caution as the C language standard provides no guarantees about the alignment or
13805  * atomicity of device memory accesses. The recommended practice for writing
13806  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13807  * alt_write_word() functions.
13808  *
13809  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH.
13810  */
13811 struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s
13812 {
13813  uint32_t addrhi : 16; /* MAC Address15 [47:32] */
13814  uint32_t : 8; /* *UNDEFINED* */
13815  uint32_t mbc_0 : 1; /* Mask Byte Control */
13816  uint32_t mbc_1 : 1; /* Mask Byte Control */
13817  uint32_t mbc_2 : 1; /* Mask Byte Control */
13818  uint32_t mbc_3 : 1; /* Mask Byte Control */
13819  uint32_t mbc_4 : 1; /* Mask Byte Control */
13820  uint32_t mbc_5 : 1; /* Mask Byte Control */
13821  uint32_t sa : 1; /* Source Address */
13822  uint32_t ae : 1; /* Address Enable */
13823 };
13824 
13825 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH. */
13826 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t;
13827 #endif /* __ASSEMBLY__ */
13828 
13829 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register from the beginning of the component. */
13830 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST 0xb8
13831 /* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register. */
13832 #define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST))
13833 
13834 /*
13835  * Register : Register 47 (MAC Address15 Low Register) - MAC_Address15_Low
13836  *
13837  * The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC
13838  * address of the station.
13839  *
13840  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
13841  * format.
13842  *
13843  * Register Layout
13844  *
13845  * Bits | Access | Reset | Description
13846  * :-------|:-------|:-----------|:---------------------
13847  * [31:0] | RW | 0xffffffff | MAC Address15 [31:0]
13848  *
13849  */
13850 /*
13851  * Field : MAC Address15 [31:0] - addrlo
13852  *
13853  * This field contains the lower 32 bits of the 16th 6-byte MAC address. The
13854  * content of this field is undefined until loaded by software after the
13855  * initialization process.
13856  *
13857  * Field Access Macros:
13858  *
13859  */
13860 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
13861 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_LSB 0
13862 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
13863 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_MSB 31
13864 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
13865 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_WIDTH 32
13866 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
13867 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET_MSK 0xffffffff
13868 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
13869 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_CLR_MSK 0x00000000
13870 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
13871 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_RESET 0xffffffff
13872 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO field value from a register. */
13873 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
13874 /* Produces a ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value suitable for setting the register. */
13875 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
13876 
13877 #ifndef __ASSEMBLY__
13878 /*
13879  * WARNING: The C register and register group struct declarations are provided for
13880  * convenience and illustrative purposes. They should, however, be used with
13881  * caution as the C language standard provides no guarantees about the alignment or
13882  * atomicity of device memory accesses. The recommended practice for writing
13883  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13884  * alt_write_word() functions.
13885  *
13886  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW.
13887  */
13888 struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s
13889 {
13890  uint32_t addrlo : 32; /* MAC Address15 [31:0] */
13891 };
13892 
13893 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW. */
13894 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s ALT_EMAC_GMAC_MAC_ADDR15_LOW_t;
13895 #endif /* __ASSEMBLY__ */
13896 
13897 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register from the beginning of the component. */
13898 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST 0xbc
13899 /* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register. */
13900 #define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST))
13901 
13902 /*
13903  * Register : Register 54 (SGMII/RGMII/SMII Status Register) - SGMII_RGMII_SMII_Control_Status
13904  *
13905  * The SGMII/RGMII/SMII Status register indicates the status signals received by
13906  * the RGMII interface (selected at reset) from the PHY.
13907  *
13908  * Register Layout
13909  *
13910  * Bits | Access | Reset | Description
13911  * :-------|:-------|:------|:------------
13912  * [0] | R | 0x0 | Link Mode
13913  * [2:1] | R | 0x0 | Link Speed
13914  * [3] | R | 0x0 | Link Status
13915  * [31:4] | ??? | 0x0 | *UNDEFINED*
13916  *
13917  */
13918 /*
13919  * Field : Link Mode - lnkmod
13920  *
13921  * This bit indicates the current mode of operation of the link
13922  *
13923  * Field Enumeration Values:
13924  *
13925  * Enum | Value | Description
13926  * :--------------------------------------------|:------|:------------
13927  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP | 0x0 | Half Duplex
13928  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP | 0x1 | Full Duplex
13929  *
13930  * Field Access Macros:
13931  *
13932  */
13933 /*
13934  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
13935  *
13936  * Half Duplex
13937  */
13938 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP 0x0
13939 /*
13940  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
13941  *
13942  * Full Duplex
13943  */
13944 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP 0x1
13945 
13946 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
13947 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB 0
13948 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
13949 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB 0
13950 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
13951 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH 1
13952 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
13953 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK 0x00000001
13954 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
13955 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK 0xfffffffe
13956 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
13957 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET 0x0
13958 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD field value from a register. */
13959 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) (((value) & 0x00000001) >> 0)
13960 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value suitable for setting the register. */
13961 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET(value) (((value) << 0) & 0x00000001)
13962 
13963 /*
13964  * Field : Link Speed - lnkspeed
13965  *
13966  * This bit indicates the current speed of the link. Bit 2 is reserved when the MAC
13967  * is configured for the SMII PHY interface.
13968  *
13969  * Field Enumeration Values:
13970  *
13971  * Enum | Value | Description
13972  * :------------------------------------------------------|:------|:------------------
13973  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ | 0x0 | Link Speed 2.5MHz
13974  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ | 0x1 | Link Speed 25MHz
13975  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ | 0x2 | Link Speed 125MHz
13976  *
13977  * Field Access Macros:
13978  *
13979  */
13980 /*
13981  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
13982  *
13983  * Link Speed 2.5MHz
13984  */
13985 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ 0x0
13986 /*
13987  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
13988  *
13989  * Link Speed 25MHz
13990  */
13991 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ 0x1
13992 /*
13993  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
13994  *
13995  * Link Speed 125MHz
13996  */
13997 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ 0x2
13998 
13999 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
14000 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB 1
14001 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
14002 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB 2
14003 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
14004 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH 2
14005 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
14006 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK 0x00000006
14007 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
14008 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK 0xfffffff9
14009 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
14010 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET 0x0
14011 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED field value from a register. */
14012 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value) & 0x00000006) >> 1)
14013 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value suitable for setting the register. */
14014 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET(value) (((value) << 1) & 0x00000006)
14015 
14016 /*
14017  * Field : Link Status - lnksts
14018  *
14019  * This bit indicates whether the link is up (1'b1) or down (1'b0).
14020  *
14021  * Field Enumeration Values:
14022  *
14023  * Enum | Value | Description
14024  * :---------------------------------------------|:------|:------------
14025  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN | 0x0 | Linkdown
14026  * ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP | 0x1 | Linkup
14027  *
14028  * Field Access Macros:
14029  *
14030  */
14031 /*
14032  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
14033  *
14034  * Linkdown
14035  */
14036 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN 0x0
14037 /*
14038  * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
14039  *
14040  * Linkup
14041  */
14042 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP 0x1
14043 
14044 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
14045 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB 3
14046 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
14047 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB 3
14048 /* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
14049 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH 1
14050 /* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
14051 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK 0x00000008
14052 /* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
14053 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK 0xfffffff7
14054 /* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
14055 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET 0x0
14056 /* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS field value from a register. */
14057 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value) & 0x00000008) >> 3)
14058 /* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value suitable for setting the register. */
14059 #define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET(value) (((value) << 3) & 0x00000008)
14060 
14061 #ifndef __ASSEMBLY__
14062 /*
14063  * WARNING: The C register and register group struct declarations are provided for
14064  * convenience and illustrative purposes. They should, however, be used with
14065  * caution as the C language standard provides no guarantees about the alignment or
14066  * atomicity of device memory accesses. The recommended practice for writing
14067  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14068  * alt_write_word() functions.
14069  *
14070  * The struct declaration for register ALT_EMAC_GMAC_MII_CTL_STAT.
14071  */
14072 struct ALT_EMAC_GMAC_MII_CTL_STAT_s
14073 {
14074  const uint32_t lnkmod : 1; /* Link Mode */
14075  const uint32_t lnkspeed : 2; /* Link Speed */
14076  const uint32_t lnksts : 1; /* Link Status */
14077  uint32_t : 28; /* *UNDEFINED* */
14078 };
14079 
14080 /* The typedef declaration for register ALT_EMAC_GMAC_MII_CTL_STAT. */
14081 typedef volatile struct ALT_EMAC_GMAC_MII_CTL_STAT_s ALT_EMAC_GMAC_MII_CTL_STAT_t;
14082 #endif /* __ASSEMBLY__ */
14083 
14084 /* The byte offset of the ALT_EMAC_GMAC_MII_CTL_STAT register from the beginning of the component. */
14085 #define ALT_EMAC_GMAC_MII_CTL_STAT_OFST 0xd8
14086 /* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register. */
14087 #define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST))
14088 
14089 /*
14090  * Register : Register 64 (MMC Control Register) - MMC_Control
14091  *
14092  * The MMC Control register establishes the operating mode of the management
14093  * counters.
14094  *
14095  * Note:
14096  *
14097  * The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset).
14098  * Therefore, when the Software tries to set both bits in the same write cycle, all
14099  * counters are cleared and the bit 4 is not set.
14100  *
14101  * Register Layout
14102  *
14103  * Bits | Access | Reset | Description
14104  * :-------|:-------|:------|:-------------------------------------------------
14105  * [0] | RW | 0x0 | Counters Reset
14106  * [1] | RW | 0x0 | Counters Stop Rollover
14107  * [2] | RW | 0x0 | Reset on Read
14108  * [3] | RW | 0x0 | MMC Counter Freeze
14109  * [4] | RW | 0x0 | Counters Preset
14110  * [5] | RW | 0x0 | Full-Half Preset
14111  * [7:6] | ??? | 0x0 | *UNDEFINED*
14112  * [8] | RW | 0x0 | Update MMC Counters for Dropped Broadcast Frames
14113  * [31:9] | ??? | 0x0 | *UNDEFINED*
14114  *
14115  */
14116 /*
14117  * Field : Counters Reset - cntrst
14118  *
14119  * When this bit is set, all counters are reset. This bit is cleared automatically
14120  * after one clock cycle.
14121  *
14122  * Field Enumeration Values:
14123  *
14124  * Enum | Value | Description
14125  * :------------------------------------|:------|:---------------------------------
14126  * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD | 0x0 | Auto cleared after 1 clock cycle
14127  * ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END | 0x1 | All Counters Reset
14128  *
14129  * Field Access Macros:
14130  *
14131  */
14132 /*
14133  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
14134  *
14135  * Auto cleared after 1 clock cycle
14136  */
14137 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0
14138 /*
14139  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
14140  *
14141  * All Counters Reset
14142  */
14143 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END 0x1
14144 
14145 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
14146 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB 0
14147 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
14148 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB 0
14149 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
14150 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH 1
14151 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
14152 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK 0x00000001
14153 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
14154 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK 0xfffffffe
14155 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
14156 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET 0x0
14157 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTRST field value from a register. */
14158 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET(value) (((value) & 0x00000001) >> 0)
14159 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value suitable for setting the register. */
14160 #define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET(value) (((value) << 0) & 0x00000001)
14161 
14162 /*
14163  * Field : Counters Stop Rollover - cntstopro
14164  *
14165  * When this bit is set, after reaching maximum value, the counter does not roll
14166  * over to zero.
14167  *
14168  * Field Enumeration Values:
14169  *
14170  * Enum | Value | Description
14171  * :---------------------------------------|:------|:---------------------------
14172  * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD | 0x0 | Counter Roll Over
14173  * ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END | 0x1 | Counter does not Roll Over
14174  *
14175  * Field Access Macros:
14176  *
14177  */
14178 /*
14179  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
14180  *
14181  * Counter Roll Over
14182  */
14183 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD 0x0
14184 /*
14185  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
14186  *
14187  * Counter does not Roll Over
14188  */
14189 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END 0x1
14190 
14191 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
14192 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB 1
14193 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
14194 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB 1
14195 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
14196 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH 1
14197 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
14198 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK 0x00000002
14199 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
14200 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK 0xfffffffd
14201 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
14202 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET 0x0
14203 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO field value from a register. */
14204 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET(value) (((value) & 0x00000002) >> 1)
14205 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value suitable for setting the register. */
14206 #define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET(value) (((value) << 1) & 0x00000002)
14207 
14208 /*
14209  * Field : Reset on Read - rstonrd
14210  *
14211  * When this bit is set, the MMC counters are reset to zero after Read (self-
14212  * clearing after reset). The counters are cleared when the least significant byte
14213  * lane (bits[7:0]) is read.
14214  *
14215  * Field Enumeration Values:
14216  *
14217  * Enum | Value | Description
14218  * :-------------------------------------|:------|:--------------------
14219  * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD | 0x0 | No reset after read
14220  * ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END | 0x1 | Reset after read
14221  *
14222  * Field Access Macros:
14223  *
14224  */
14225 /*
14226  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
14227  *
14228  * No reset after read
14229  */
14230 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD 0x0
14231 /*
14232  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
14233  *
14234  * Reset after read
14235  */
14236 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END 0x1
14237 
14238 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
14239 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB 2
14240 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
14241 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB 2
14242 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
14243 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH 1
14244 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
14245 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK 0x00000004
14246 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
14247 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK 0xfffffffb
14248 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
14249 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET 0x0
14250 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSTONRD field value from a register. */
14251 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET(value) (((value) & 0x00000004) >> 2)
14252 /* Produces a ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value suitable for setting the register. */
14253 #define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET(value) (((value) << 2) & 0x00000004)
14254 
14255 /*
14256  * Field : MMC Counter Freeze - cntfreez
14257  *
14258  * When this bit is set, it freezes all MMC counters to their current value. Until
14259  * this bit is reset to 0, no MMC counter is updated because of any transmitted or
14260  * received frame. If any MMC counter is read with the Reset on Read bit set, then
14261  * that counter is also cleared in this mode.
14262  *
14263  * Field Enumeration Values:
14264  *
14265  * Enum | Value | Description
14266  * :--------------------------------------|:------|:-------------------------------------
14267  * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD | 0x0 | Update MMC Counters
14268  * ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END | 0x1 | Freeze MMC counters to current value
14269  *
14270  * Field Access Macros:
14271  *
14272  */
14273 /*
14274  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
14275  *
14276  * Update MMC Counters
14277  */
14278 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD 0x0
14279 /*
14280  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
14281  *
14282  * Freeze MMC counters to current value
14283  */
14284 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END 0x1
14285 
14286 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
14287 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB 3
14288 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
14289 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB 3
14290 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
14291 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH 1
14292 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
14293 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK 0x00000008
14294 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
14295 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK 0xfffffff7
14296 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
14297 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET 0x0
14298 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ field value from a register. */
14299 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET(value) (((value) & 0x00000008) >> 3)
14300 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value suitable for setting the register. */
14301 #define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET(value) (((value) << 3) & 0x00000008)
14302 
14303 /*
14304  * Field : Counters Preset - cntprst
14305  *
14306  * When this bit is set, all counters are initialized or preset to almost full or
14307  * almost half according to bit 5. This bit is cleared automatically after 1 clock
14308  * cycle. This bit, along with bit 5, is useful for debugging and testing the
14309  * assertion of interrupts because of MMC counter becoming half-full or full.
14310  *
14311  * Field Enumeration Values:
14312  *
14313  * Enum | Value | Description
14314  * :-------------------------------------|:------|:---------------------------------------
14315  * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD | 0x0 | Counters not preset
14316  * ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END | 0x1 | Counters preset to full or almost full
14317  *
14318  * Field Access Macros:
14319  *
14320  */
14321 /*
14322  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
14323  *
14324  * Counters not preset
14325  */
14326 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD 0x0
14327 /*
14328  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
14329  *
14330  * Counters preset to full or almost full
14331  */
14332 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END 0x1
14333 
14334 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
14335 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB 4
14336 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
14337 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB 4
14338 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
14339 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH 1
14340 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
14341 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK 0x00000010
14342 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
14343 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK 0xffffffef
14344 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
14345 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET 0x0
14346 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRST field value from a register. */
14347 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET(value) (((value) & 0x00000010) >> 4)
14348 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value suitable for setting the register. */
14349 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET(value) (((value) << 4) & 0x00000010)
14350 
14351 /*
14352  * Field : Full-Half Preset - cntprstlvl
14353  *
14354  * When low and bit 4 is set, all MMC counters get preset to almost-half value. All
14355  * octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters
14356  * gets preset to 0x7FFF_FFF0 (half - 16).
14357  *
14358  * When this bit is high and bit 4 is set, all MMC counters get preset to almost-
14359  * full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and
14360  * all frame-counters gets preset to 0xFFFF_FFF0 (full - 16).
14361  *
14362  * For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the
14363  * respective octet and frame counters. Similarly, the almost-full preset values
14364  * for the 16-bit counters are 0xF800 and 0xFFF0.
14365  *
14366  * Field Enumeration Values:
14367  *
14368  * Enum | Value | Description
14369  * :----------------------------------------------|:------|:-----------------------------------
14370  * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF | 0x0 | Preset All Counters to almost-half
14371  * ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL | 0x1 | Present All Counters almost-full
14372  *
14373  * Field Access Macros:
14374  *
14375  */
14376 /*
14377  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
14378  *
14379  * Preset All Counters to almost-half
14380  */
14381 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF 0x0
14382 /*
14383  * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
14384  *
14385  * Present All Counters almost-full
14386  */
14387 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL 0x1
14388 
14389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
14390 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB 5
14391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
14392 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB 5
14393 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
14394 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH 1
14395 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
14396 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK 0x00000020
14397 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
14398 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK 0xffffffdf
14399 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
14400 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET 0x0
14401 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL field value from a register. */
14402 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET(value) (((value) & 0x00000020) >> 5)
14403 /* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value suitable for setting the register. */
14404 #define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET(value) (((value) << 5) & 0x00000020)
14405 
14406 /*
14407  * Field : Update MMC Counters for Dropped Broadcast Frames - ucdbc
14408  *
14409  * When set, this bit enables MAC to update all the related MMC Counters for
14410  * Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of
14411  * MAC Filter Register at offset 0x0004.
14412  *
14413  * When reset, MMC Counters are not updated for dropped Broadcast frames.
14414  *
14415  * Field Access Macros:
14416  *
14417  */
14418 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
14419 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB 8
14420 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
14421 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB 8
14422 /* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
14423 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH 1
14424 /* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
14425 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK 0x00000100
14426 /* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
14427 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK 0xfffffeff
14428 /* The reset value of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
14429 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET 0x0
14430 /* Extracts the ALT_EMAC_GMAC_MMC_CTL_UCDBC field value from a register. */
14431 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET(value) (((value) & 0x00000100) >> 8)
14432 /* Produces a ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value suitable for setting the register. */
14433 #define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET(value) (((value) << 8) & 0x00000100)
14434 
14435 #ifndef __ASSEMBLY__
14436 /*
14437  * WARNING: The C register and register group struct declarations are provided for
14438  * convenience and illustrative purposes. They should, however, be used with
14439  * caution as the C language standard provides no guarantees about the alignment or
14440  * atomicity of device memory accesses. The recommended practice for writing
14441  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14442  * alt_write_word() functions.
14443  *
14444  * The struct declaration for register ALT_EMAC_GMAC_MMC_CTL.
14445  */
14446 struct ALT_EMAC_GMAC_MMC_CTL_s
14447 {
14448  uint32_t cntrst : 1; /* Counters Reset */
14449  uint32_t cntstopro : 1; /* Counters Stop Rollover */
14450  uint32_t rstonrd : 1; /* Reset on Read */
14451  uint32_t cntfreez : 1; /* MMC Counter Freeze */
14452  uint32_t cntprst : 1; /* Counters Preset */
14453  uint32_t cntprstlvl : 1; /* Full-Half Preset */
14454  uint32_t : 2; /* *UNDEFINED* */
14455  uint32_t ucdbc : 1; /* Update MMC Counters for Dropped Broadcast Frames */
14456  uint32_t : 23; /* *UNDEFINED* */
14457 };
14458 
14459 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_CTL. */
14460 typedef volatile struct ALT_EMAC_GMAC_MMC_CTL_s ALT_EMAC_GMAC_MMC_CTL_t;
14461 #endif /* __ASSEMBLY__ */
14462 
14463 /* The byte offset of the ALT_EMAC_GMAC_MMC_CTL register from the beginning of the component. */
14464 #define ALT_EMAC_GMAC_MMC_CTL_OFST 0x100
14465 /* The address of the ALT_EMAC_GMAC_MMC_CTL register. */
14466 #define ALT_EMAC_GMAC_MMC_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST))
14467 
14468 /*
14469  * Register : Register 65 (MMC Receive Interrupt Register) - MMC_Receive_Interrupt
14470  *
14471  * The MMC Receive Interrupt register maintains the interrupts that are generated
14472  * when the following happens:
14473  *
14474  * * Receive statistic counters reach half of their maximum values (0x8000_0000 for
14475  * 32-bit counter and 0x8000 for 16-bit counter).
14476  *
14477  * * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit
14478  * counter and 0xFFFF for 16-bit counter).
14479  *
14480  * When the Counter Stop Rollover is set, then interrupts are set but the counter
14481  * remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide
14482  * register. An interrupt bit is cleared when the respective MMC counter that
14483  * caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the
14484  * respective counter must be read in order to clear the interrupt bit.
14485  *
14486  * Register Layout
14487  *
14488  * Bits | Access | Reset | Description
14489  * :--------|:-------|:------|:--------------------------------------------------------------------------
14490  * [0] | R | 0x0 | MMC Receive Good Bad Frame Counter Interrupt Status
14491  * [1] | R | 0x0 | MMC Receive Good Bad Octet Counter Interrupt Status
14492  * [2] | R | 0x0 | MMC Receive Good Octet Counter Interrupt Status.
14493  * [3] | R | 0x0 | MMC Receive Broadcast Good Frame Counter Interrupt Status.
14494  * [4] | R | 0x0 | MMC Receive Multicast Good Frame Counter Interrupt Status
14495  * [5] | R | 0x0 | MMC Receive CRC Error Frame Counter Interrupt Status
14496  * [6] | R | 0x0 | MMC Receive Alignment Error Frame Counter Interrupt Status
14497  * [7] | R | 0x0 | MMC Receive Runt Frame Counter Interrupt Status
14498  * [8] | R | 0x0 | MMC Receive Jabber Error Frame Counter Interrupt Status
14499  * [9] | R | 0x0 | MMC Receive Undersize Good Frame Counter Interrupt Status
14500  * [10] | R | 0x0 | MMC Receive Oversize Good Frame Counter Interrupt Status
14501  * [11] | R | 0x0 | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
14502  * [12] | R | 0x0 | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
14503  * [13] | R | 0x0 | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
14504  * [14] | R | 0x0 | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
14505  * [15] | R | 0x0 | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
14506  * [16] | R | 0x0 | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
14507  * [17] | R | 0x0 | MMC Receive Unicast Good Frame Counter Interrupt Status
14508  * [18] | R | 0x0 | MMC Receive Length Error Frame Counter Interrupt Status
14509  * [19] | R | 0x0 | MMC Receive Out Of Range Error Frame Counter Interrupt Status
14510  * [20] | R | 0x0 | MMC Receive Pause Frame Counter Interrupt Status
14511  * [21] | R | 0x0 | MMC Receive FIFO Overflow Frame Counter Interrupt Status
14512  * [22] | R | 0x0 | MMC Receive VLAN Good Bad Frame Counter Interrupt Status
14513  * [23] | R | 0x0 | MMC Receive Watchdog Error Frame Counter Interrupt Status
14514  * [24] | R | 0x0 | MMC Receive Error Frame Counter Interrupt Status
14515  * [25] | R | 0x0 | MMC Receive Control Frame Counter Interrupt Status
14516  * [31:26] | ??? | 0x0 | *UNDEFINED*
14517  *
14518  */
14519 /*
14520  * Field : MMC Receive Good Bad Frame Counter Interrupt Status - rxgbfrmis
14521  *
14522  * This bit is set when the rxframecount_bg counter reaches half of the maximum
14523  * value or the maximum value.
14524  *
14525  * Field Enumeration Values:
14526  *
14527  * Enum | Value | Description
14528  * :----------------------------------------------|:------|:-----------------------------------
14529  * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF | 0x0 | Preset All Counters to almost-half
14530  * ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL | 0x1 | Present All Counters almost-full
14531  *
14532  * Field Access Macros:
14533  *
14534  */
14535 /*
14536  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
14537  *
14538  * Preset All Counters to almost-half
14539  */
14540 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF 0x0
14541 /*
14542  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
14543  *
14544  * Present All Counters almost-full
14545  */
14546 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL 0x1
14547 
14548 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
14549 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB 0
14550 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
14551 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB 0
14552 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
14553 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH 1
14554 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
14555 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK 0x00000001
14556 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
14557 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK 0xfffffffe
14558 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
14559 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET 0x0
14560 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS field value from a register. */
14561 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET(value) (((value) & 0x00000001) >> 0)
14562 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value suitable for setting the register. */
14563 #define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET(value) (((value) << 0) & 0x00000001)
14564 
14565 /*
14566  * Field : MMC Receive Good Bad Octet Counter Interrupt Status - rxgboctis
14567  *
14568  * This bit is set when the rxoctetcount_bg counter reaches half of the maximum
14569  * value or the maximum value.
14570  *
14571  * Field Enumeration Values:
14572  *
14573  * Enum | Value | Description
14574  * :-----------------------------------------|:------|:----------------------------
14575  * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT | 0x0 | Rxoctetcount_bg < half max
14576  * ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT | 0x1 | Rxoctetcount_bg >= half max
14577  *
14578  * Field Access Macros:
14579  *
14580  */
14581 /*
14582  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
14583  *
14584  * Rxoctetcount_bg < half max
14585  */
14586 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT 0x0
14587 /*
14588  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
14589  *
14590  * Rxoctetcount_bg >= half max
14591  */
14592 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT 0x1
14593 
14594 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
14595 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB 1
14596 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
14597 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB 1
14598 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
14599 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH 1
14600 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
14601 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK 0x00000002
14602 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
14603 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK 0xfffffffd
14604 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
14605 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET 0x0
14606 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS field value from a register. */
14607 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET(value) (((value) & 0x00000002) >> 1)
14608 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value suitable for setting the register. */
14609 #define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET(value) (((value) << 1) & 0x00000002)
14610 
14611 /*
14612  * Field : MMC Receive Good Octet Counter Interrupt Status. - rxgoctis
14613  *
14614  * This bit is set when the rxoctetcount_g counter reaches half of the maximum
14615  * value or the maximum value.
14616  *
14617  * Field Enumeration Values:
14618  *
14619  * Enum | Value | Description
14620  * :----------------------------------------|:------|:---------------------------
14621  * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT | 0x0 | Rxoctetcount_g < half max
14622  * ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT | 0x1 | Rxoctetcount_g >= half max
14623  *
14624  * Field Access Macros:
14625  *
14626  */
14627 /*
14628  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
14629  *
14630  * Rxoctetcount_g < half max
14631  */
14632 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT 0x0
14633 /*
14634  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
14635  *
14636  * Rxoctetcount_g >= half max
14637  */
14638 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT 0x1
14639 
14640 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
14641 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB 2
14642 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
14643 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB 2
14644 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
14645 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH 1
14646 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
14647 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK 0x00000004
14648 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
14649 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK 0xfffffffb
14650 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
14651 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET 0x0
14652 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS field value from a register. */
14653 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET(value) (((value) & 0x00000004) >> 2)
14654 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value suitable for setting the register. */
14655 #define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET(value) (((value) << 2) & 0x00000004)
14656 
14657 /*
14658  * Field : MMC Receive Broadcast Good Frame Counter Interrupt Status. - rxbcgfis
14659  *
14660  * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum
14661  * value or the maximum value.
14662  *
14663  * Field Access Macros:
14664  *
14665  */
14666 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
14667 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB 3
14668 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
14669 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB 3
14670 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
14671 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH 1
14672 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
14673 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK 0x00000008
14674 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
14675 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK 0xfffffff7
14676 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
14677 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET 0x0
14678 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS field value from a register. */
14679 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET(value) (((value) & 0x00000008) >> 3)
14680 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value suitable for setting the register. */
14681 #define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET(value) (((value) << 3) & 0x00000008)
14682 
14683 /*
14684  * Field : MMC Receive Multicast Good Frame Counter Interrupt Status - rxmcgfis
14685  *
14686  * This bit is set when the rxmulticastframes_g counter reaches half of the maximum
14687  * value or the maximum value.
14688  *
14689  * Field Enumeration Values:
14690  *
14691  * Enum | Value | Description
14692  * :----------------------------------------|:------|:--------------------------------
14693  * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT | 0x0 | rxbroadcastframes_g < half max
14694  * ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT | 0x1 | rxbroadcastframes_g >= half max
14695  *
14696  * Field Access Macros:
14697  *
14698  */
14699 /*
14700  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
14701  *
14702  * rxbroadcastframes_g < half max
14703  */
14704 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT 0x0
14705 /*
14706  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
14707  *
14708  * rxbroadcastframes_g >= half max
14709  */
14710 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT 0x1
14711 
14712 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
14713 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB 4
14714 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
14715 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB 4
14716 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
14717 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH 1
14718 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
14719 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK 0x00000010
14720 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
14721 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK 0xffffffef
14722 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
14723 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET 0x0
14724 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS field value from a register. */
14725 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET(value) (((value) & 0x00000010) >> 4)
14726 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value suitable for setting the register. */
14727 #define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET(value) (((value) << 4) & 0x00000010)
14728 
14729 /*
14730  * Field : MMC Receive CRC Error Frame Counter Interrupt Status - rxcrcerfis
14731  *
14732  * This bit is set when the rxcrcerror counter reaches half of the maximum value or
14733  * the maximum value.
14734  *
14735  * Field Enumeration Values:
14736  *
14737  * Enum | Value | Description
14738  * :------------------------------------------|:------|:-----------------------
14739  * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT | 0x0 | rxcrcerror < half max
14740  * ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT | 0x1 | rxcrcerror >= half max
14741  *
14742  * Field Access Macros:
14743  *
14744  */
14745 /*
14746  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
14747  *
14748  * rxcrcerror < half max
14749  */
14750 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT 0x0
14751 /*
14752  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
14753  *
14754  * rxcrcerror >= half max
14755  */
14756 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT 0x1
14757 
14758 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
14759 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB 5
14760 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
14761 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB 5
14762 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
14763 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH 1
14764 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
14765 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK 0x00000020
14766 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
14767 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK 0xffffffdf
14768 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
14769 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET 0x0
14770 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS field value from a register. */
14771 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET(value) (((value) & 0x00000020) >> 5)
14772 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value suitable for setting the register. */
14773 #define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET(value) (((value) << 5) & 0x00000020)
14774 
14775 /*
14776  * Field : MMC Receive Alignment Error Frame Counter Interrupt Status - rxalgnerfis
14777  *
14778  * This bit is set when the rxalignmenterror counter reaches half of the maximum
14779  * value or the maximum value.
14780  *
14781  * Field Enumeration Values:
14782  *
14783  * Enum | Value | Description
14784  * :-------------------------------------------|:------|:-----------------------------
14785  * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT | 0x0 | rxalignmenterror < half max
14786  * ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT | 0x1 | rxalignmenterror >= half max
14787  *
14788  * Field Access Macros:
14789  *
14790  */
14791 /*
14792  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
14793  *
14794  * rxalignmenterror < half max
14795  */
14796 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT 0x0
14797 /*
14798  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
14799  *
14800  * rxalignmenterror >= half max
14801  */
14802 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT 0x1
14803 
14804 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
14805 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB 6
14806 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
14807 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB 6
14808 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
14809 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH 1
14810 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
14811 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK 0x00000040
14812 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
14813 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK 0xffffffbf
14814 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
14815 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET 0x0
14816 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS field value from a register. */
14817 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET(value) (((value) & 0x00000040) >> 6)
14818 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value suitable for setting the register. */
14819 #define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET(value) (((value) << 6) & 0x00000040)
14820 
14821 /*
14822  * Field : MMC Receive Runt Frame Counter Interrupt Status - rxruntfis
14823  *
14824  * This bit is set when the rxrunterror counter reaches half of the maximum value
14825  * or the maximum value.
14826  *
14827  * Field Enumeration Values:
14828  *
14829  * Enum | Value | Description
14830  * :-----------------------------------------|:------|:------------------------
14831  * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT | 0x0 | rxrunterror < half max
14832  * ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT | 0x1 | rxrunterror >= half max
14833  *
14834  * Field Access Macros:
14835  *
14836  */
14837 /*
14838  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
14839  *
14840  * rxrunterror < half max
14841  */
14842 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT 0x0
14843 /*
14844  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
14845  *
14846  * rxrunterror >= half max
14847  */
14848 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT 0x1
14849 
14850 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
14851 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB 7
14852 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
14853 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB 7
14854 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
14855 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH 1
14856 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
14857 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK 0x00000080
14858 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
14859 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK 0xffffff7f
14860 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
14861 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET 0x0
14862 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS field value from a register. */
14863 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET(value) (((value) & 0x00000080) >> 7)
14864 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value suitable for setting the register. */
14865 #define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET(value) (((value) << 7) & 0x00000080)
14866 
14867 /*
14868  * Field : MMC Receive Jabber Error Frame Counter Interrupt Status - rxjaberfis
14869  *
14870  * This bit is set when the rxjabbererror counter reaches half of the maximum value
14871  * or the maximum value.
14872  *
14873  * Field Enumeration Values:
14874  *
14875  * Enum | Value | Description
14876  * :------------------------------------------|:------|:--------------------------
14877  * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT | 0x0 | rxjabbererror < half max
14878  * ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT | 0x1 | rxjabbererror >= half max
14879  *
14880  * Field Access Macros:
14881  *
14882  */
14883 /*
14884  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
14885  *
14886  * rxjabbererror < half max
14887  */
14888 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT 0x0
14889 /*
14890  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
14891  *
14892  * rxjabbererror >= half max
14893  */
14894 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT 0x1
14895 
14896 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
14897 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB 8
14898 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
14899 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB 8
14900 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
14901 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH 1
14902 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
14903 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK 0x00000100
14904 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
14905 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK 0xfffffeff
14906 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
14907 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET 0x0
14908 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS field value from a register. */
14909 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET(value) (((value) & 0x00000100) >> 8)
14910 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value suitable for setting the register. */
14911 #define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET(value) (((value) << 8) & 0x00000100)
14912 
14913 /*
14914  * Field : MMC Receive Undersize Good Frame Counter Interrupt Status - rxusizegfis
14915  *
14916  * This bit is set when the rxundersize_g counter reaches half of the maximum value
14917  * or the maximum value.
14918  *
14919  * Field Enumeration Values:
14920  *
14921  * Enum | Value | Description
14922  * :-------------------------------------------|:------|:--------------------------
14923  * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT | 0x0 | rxundersize_g < half max
14924  * ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT | 0x1 | rxundersize_g >= half max
14925  *
14926  * Field Access Macros:
14927  *
14928  */
14929 /*
14930  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
14931  *
14932  * rxundersize_g < half max
14933  */
14934 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT 0x0
14935 /*
14936  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
14937  *
14938  * rxundersize_g >= half max
14939  */
14940 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT 0x1
14941 
14942 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
14943 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB 9
14944 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
14945 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB 9
14946 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
14947 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH 1
14948 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
14949 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK 0x00000200
14950 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
14951 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK 0xfffffdff
14952 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
14953 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET 0x0
14954 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS field value from a register. */
14955 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET(value) (((value) & 0x00000200) >> 9)
14956 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value suitable for setting the register. */
14957 #define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET(value) (((value) << 9) & 0x00000200)
14958 
14959 /*
14960  * Field : MMC Receive Oversize Good Frame Counter Interrupt Status - rxosizegfis
14961  *
14962  * This bit is set when the rxoversize_g counter reaches half of the maximum value
14963  * or the maximum value.
14964  *
14965  * Field Enumeration Values:
14966  *
14967  * Enum | Value | Description
14968  * :-------------------------------------------|:------|:--------------------------
14969  * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT | 0x0 | rxoversize_g < half max
14970  * ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT | 0x1 | rxoversize_g >= half max
14971  *
14972  * Field Access Macros:
14973  *
14974  */
14975 /*
14976  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
14977  *
14978  * rxoversize_g < half max
14979  */
14980 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT 0x0
14981 /*
14982  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
14983  *
14984  * rxoversize_g >= half max
14985  */
14986 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT 0x1
14987 
14988 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
14989 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB 10
14990 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
14991 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB 10
14992 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
14993 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH 1
14994 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
14995 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK 0x00000400
14996 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
14997 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK 0xfffffbff
14998 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
14999 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET 0x0
15000 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS field value from a register. */
15001 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET(value) (((value) & 0x00000400) >> 10)
15002 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value suitable for setting the register. */
15003 #define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET(value) (((value) << 10) & 0x00000400)
15004 
15005 /*
15006  * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - rx64octgbfis
15007  *
15008  * This bit is set when the rx64octets_gb counter reaches half of the maximum value
15009  * or the maximum value.
15010  *
15011  * Field Enumeration Values:
15012  *
15013  * Enum | Value | Description
15014  * :--------------------------------------------|:------|:---------------------------
15015  * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT | 0x0 | rx64octets_gb < half max
15016  * ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT | 0x1 | rx64octets_gb >= half max
15017  *
15018  * Field Access Macros:
15019  *
15020  */
15021 /*
15022  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
15023  *
15024  * rx64octets_gb < half max
15025  */
15026 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT 0x0
15027 /*
15028  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
15029  *
15030  * rx64octets_gb >= half max
15031  */
15032 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT 0x1
15033 
15034 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
15035 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB 11
15036 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
15037 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB 11
15038 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
15039 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH 1
15040 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
15041 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK 0x00000800
15042 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
15043 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK 0xfffff7ff
15044 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
15045 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET 0x0
15046 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS field value from a register. */
15047 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000800) >> 11)
15048 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value suitable for setting the register. */
15049 #define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET(value) (((value) << 11) & 0x00000800)
15050 
15051 /*
15052  * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - rx65t127octgbfis
15053  *
15054  * This is set when the rx65to127octets_gb counter reaches half of the maximum
15055  * value or the maximum value.
15056  *
15057  * Field Enumeration Values:
15058  *
15059  * Enum | Value | Description
15060  * :------------------------------------------------|:------|:--------------------------------
15061  * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT | 0x0 | rx65to127octets_gb < half max
15062  * ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT | 0x1 | rx65to127octets_gb >= half max
15063  *
15064  * Field Access Macros:
15065  *
15066  */
15067 /*
15068  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
15069  *
15070  * rx65to127octets_gb < half max
15071  */
15072 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT 0x0
15073 /*
15074  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
15075  *
15076  * rx65to127octets_gb >= half max
15077  */
15078 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT 0x1
15079 
15080 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
15081 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB 12
15082 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
15083 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB 12
15084 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
15085 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH 1
15086 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
15087 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK 0x00001000
15088 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
15089 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK 0xffffefff
15090 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
15091 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET 0x0
15092 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS field value from a register. */
15093 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00001000) >> 12)
15094 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
15095 #define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET(value) (((value) << 12) & 0x00001000)
15096 
15097 /*
15098  * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - rx128t255octgbfis
15099  *
15100  * This bit is set when the rx128to255octets_gb counter reaches half of the maximum
15101  * value or the maximum value.
15102  *
15103  * Field Enumeration Values:
15104  *
15105  * Enum | Value | Description
15106  * :-------------------------------------------------|:------|:---------------------------------
15107  * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT | 0x0 | rx128to255octets_gb < half max
15108  * ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT | 0x1 | rx128to255octets_gb >= half max
15109  *
15110  * Field Access Macros:
15111  *
15112  */
15113 /*
15114  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
15115  *
15116  * rx128to255octets_gb < half max
15117  */
15118 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT 0x0
15119 /*
15120  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
15121  *
15122  * rx128to255octets_gb >= half max
15123  */
15124 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT 0x1
15125 
15126 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
15127 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB 13
15128 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
15129 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB 13
15130 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
15131 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH 1
15132 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
15133 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK 0x00002000
15134 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
15135 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK 0xffffdfff
15136 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
15137 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET 0x0
15138 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS field value from a register. */
15139 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00002000) >> 13)
15140 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
15141 #define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET(value) (((value) << 13) & 0x00002000)
15142 
15143 /*
15144  * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - rx256t511octgbfis
15145  *
15146  * This bit is set when the rx256to511octets_gb counter reaches half of the maximum
15147  * value or the maximum value.
15148  *
15149  * Field Enumeration Values:
15150  *
15151  * Enum | Value | Description
15152  * :-------------------------------------------------|:------|:---------------------------------
15153  * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT | 0x0 | rx256to511octets_gb < half max
15154  * ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT | 0x1 | rx256to511octets_gb >= half max
15155  *
15156  * Field Access Macros:
15157  *
15158  */
15159 /*
15160  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
15161  *
15162  * rx256to511octets_gb < half max
15163  */
15164 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT 0x0
15165 /*
15166  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
15167  *
15168  * rx256to511octets_gb >= half max
15169  */
15170 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT 0x1
15171 
15172 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
15173 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB 14
15174 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
15175 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB 14
15176 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
15177 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH 1
15178 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
15179 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK 0x00004000
15180 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
15181 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK 0xffffbfff
15182 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
15183 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET 0x0
15184 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS field value from a register. */
15185 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00004000) >> 14)
15186 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
15187 #define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET(value) (((value) << 14) & 0x00004000)
15188 
15189 /*
15190  * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - rx512t1023octgbfis
15191  *
15192  * This bit is set when the rx512to1023octets_gb counter reaches half of the
15193  * maximum value or the maximum value.
15194  *
15195  * Field Enumeration Values:
15196  *
15197  * Enum | Value | Description
15198  * :--------------------------------------------------|:------|:----------------------------------
15199  * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT | 0x0 | rx512to1023octets_gb < half max
15200  * ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT | 0x1 | rx512to1023octets_gb >= half max
15201  *
15202  * Field Access Macros:
15203  *
15204  */
15205 /*
15206  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
15207  *
15208  * rx512to1023octets_gb < half max
15209  */
15210 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT 0x0
15211 /*
15212  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
15213  *
15214  * rx512to1023octets_gb >= half max
15215  */
15216 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT 0x1
15217 
15218 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
15219 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB 15
15220 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
15221 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB 15
15222 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
15223 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH 1
15224 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
15225 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK 0x00008000
15226 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
15227 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK 0xffff7fff
15228 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
15229 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET 0x0
15230 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS field value from a register. */
15231 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00008000) >> 15)
15232 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
15233 #define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET(value) (((value) << 15) & 0x00008000)
15234 
15235 /*
15236  * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - rx1024tmaxoctgbfis
15237  *
15238  * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the
15239  * maximum value or the maximum value.
15240  *
15241  * Field Enumeration Values:
15242  *
15243  * Enum | Value | Description
15244  * :--------------------------------------------------|:------|:----------------------------------
15245  * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 | rx1024tomaxoctets_gb < half max
15246  * ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 | rx1024tomaxoctets_gb >= half max
15247  *
15248  * Field Access Macros:
15249  *
15250  */
15251 /*
15252  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
15253  *
15254  * rx1024tomaxoctets_gb < half max
15255  */
15256 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT 0x0
15257 /*
15258  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
15259  *
15260  * rx1024tomaxoctets_gb >= half max
15261  */
15262 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT 0x1
15263 
15264 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
15265 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB 16
15266 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
15267 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB 16
15268 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
15269 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH 1
15270 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
15271 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00010000
15272 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
15273 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffeffff
15274 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
15275 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET 0x0
15276 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS field value from a register. */
15277 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00010000) >> 16)
15278 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
15279 #define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 16) & 0x00010000)
15280 
15281 /*
15282  * Field : MMC Receive Unicast Good Frame Counter Interrupt Status - rxucgfis
15283  *
15284  * This bit is set when the rxunicastframes_gb counter reaches half of the maximum
15285  * value or the maximum value.
15286  *
15287  * Field Enumeration Values:
15288  *
15289  * Enum | Value | Description
15290  * :----------------------------------------|:------|:----------------------------------
15291  * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT | 0x0 | rx1024tomaxoctets_gb < half max
15292  * ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT | 0x1 | rx1024tomaxoctets_gb >= half max
15293  *
15294  * Field Access Macros:
15295  *
15296  */
15297 /*
15298  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
15299  *
15300  * rx1024tomaxoctets_gb < half max
15301  */
15302 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT 0x0
15303 /*
15304  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
15305  *
15306  * rx1024tomaxoctets_gb >= half max
15307  */
15308 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT 0x1
15309 
15310 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
15311 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB 17
15312 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
15313 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB 17
15314 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
15315 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH 1
15316 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
15317 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK 0x00020000
15318 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
15319 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK 0xfffdffff
15320 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
15321 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET 0x0
15322 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS field value from a register. */
15323 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET(value) (((value) & 0x00020000) >> 17)
15324 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value suitable for setting the register. */
15325 #define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET(value) (((value) << 17) & 0x00020000)
15326 
15327 /*
15328  * Field : MMC Receive Length Error Frame Counter Interrupt Status - rxlenerfis
15329  *
15330  * This bit is set when the rxlengtherror counter reaches half of the maximum value
15331  * or the maximum value.
15332  *
15333  * Field Enumeration Values:
15334  *
15335  * Enum | Value | Description
15336  * :------------------------------------------|:------|:---------------------------
15337  * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT | 0x0 | rxlengtherror < half max
15338  * ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT | 0x1 | rxlengtherror >= half max
15339  *
15340  * Field Access Macros:
15341  *
15342  */
15343 /*
15344  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
15345  *
15346  * rxlengtherror < half max
15347  */
15348 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT 0x0
15349 /*
15350  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
15351  *
15352  * rxlengtherror >= half max
15353  */
15354 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT 0x1
15355 
15356 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
15357 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB 18
15358 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
15359 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB 18
15360 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
15361 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH 1
15362 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
15363 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK 0x00040000
15364 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
15365 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK 0xfffbffff
15366 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
15367 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET 0x0
15368 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS field value from a register. */
15369 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET(value) (((value) & 0x00040000) >> 18)
15370 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value suitable for setting the register. */
15371 #define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET(value) (((value) << 18) & 0x00040000)
15372 
15373 /*
15374  * Field : MMC Receive Out Of Range Error Frame Counter Interrupt Status - rxorangefis
15375  *
15376  * This bit is set when the rxoutofrangetype counter reaches half of the maximum
15377  * value or the maximum value.
15378  *
15379  * Field Enumeration Values:
15380  *
15381  * Enum | Value | Description
15382  * :-------------------------------------------|:------|:------------------------------
15383  * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT | 0x0 | rxoutofrangetype < half max
15384  * ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT | 0x1 | rxoutofrangetype >= half max
15385  *
15386  * Field Access Macros:
15387  *
15388  */
15389 /*
15390  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
15391  *
15392  * rxoutofrangetype < half max
15393  */
15394 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT 0x0
15395 /*
15396  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
15397  *
15398  * rxoutofrangetype >= half max
15399  */
15400 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT 0x1
15401 
15402 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
15403 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB 19
15404 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
15405 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB 19
15406 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
15407 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH 1
15408 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
15409 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK 0x00080000
15410 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
15411 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK 0xfff7ffff
15412 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
15413 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET 0x0
15414 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS field value from a register. */
15415 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET(value) (((value) & 0x00080000) >> 19)
15416 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value suitable for setting the register. */
15417 #define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET(value) (((value) << 19) & 0x00080000)
15418 
15419 /*
15420  * Field : MMC Receive Pause Frame Counter Interrupt Status - rxpausfis
15421  *
15422  * This bit is set when the rxpauseframe counter reaches half of the maximum value
15423  * or the maximum value.
15424  *
15425  * Field Enumeration Values:
15426  *
15427  * Enum | Value | Description
15428  * :-----------------------------------------|:------|:--------------------------
15429  * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT | 0x0 | rxpauseframe < half max
15430  * ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT | 0x1 | rxpauseframe >= half max
15431  *
15432  * Field Access Macros:
15433  *
15434  */
15435 /*
15436  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
15437  *
15438  * rxpauseframe < half max
15439  */
15440 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT 0x0
15441 /*
15442  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
15443  *
15444  * rxpauseframe >= half max
15445  */
15446 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT 0x1
15447 
15448 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
15449 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB 20
15450 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
15451 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB 20
15452 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
15453 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH 1
15454 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
15455 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK 0x00100000
15456 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
15457 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK 0xffefffff
15458 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
15459 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET 0x0
15460 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS field value from a register. */
15461 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET(value) (((value) & 0x00100000) >> 20)
15462 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value suitable for setting the register. */
15463 #define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET(value) (((value) << 20) & 0x00100000)
15464 
15465 /*
15466  * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Status - rxfovfis
15467  *
15468  * This bit is set when the rxfifooverflow counter reaches half of the maximum
15469  * value or the maximum value.
15470  *
15471  * Field Enumeration Values:
15472  *
15473  * Enum | Value | Description
15474  * :----------------------------------------|:------|:----------------------------
15475  * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT | 0x0 | rxfifooverflow < half max
15476  * ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT | 0x1 | rxfifooverflow >= half max
15477  *
15478  * Field Access Macros:
15479  *
15480  */
15481 /*
15482  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
15483  *
15484  * rxfifooverflow < half max
15485  */
15486 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT 0x0
15487 /*
15488  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
15489  *
15490  * rxfifooverflow >= half max
15491  */
15492 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT 0x1
15493 
15494 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
15495 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB 21
15496 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
15497 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB 21
15498 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
15499 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH 1
15500 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
15501 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK 0x00200000
15502 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
15503 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK 0xffdfffff
15504 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
15505 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET 0x0
15506 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS field value from a register. */
15507 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET(value) (((value) & 0x00200000) >> 21)
15508 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value suitable for setting the register. */
15509 #define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET(value) (((value) << 21) & 0x00200000)
15510 
15511 /*
15512  * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Status - rxvlangbfis
15513  *
15514  * This bit is set when the rxvlanframes_gb counter reaches half of the maximum
15515  * value or the maximum value.
15516  *
15517  * Field Enumeration Values:
15518  *
15519  * Enum | Value | Description
15520  * :-------------------------------------------|:------|:-----------------------------
15521  * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT | 0x0 | rxvlanframes_gb < half max
15522  * ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT | 0x1 | rxvlanframes_gb >= half max
15523  *
15524  * Field Access Macros:
15525  *
15526  */
15527 /*
15528  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
15529  *
15530  * rxvlanframes_gb < half max
15531  */
15532 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT 0x0
15533 /*
15534  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
15535  *
15536  * rxvlanframes_gb >= half max
15537  */
15538 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT 0x1
15539 
15540 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
15541 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB 22
15542 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
15543 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB 22
15544 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
15545 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH 1
15546 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
15547 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK 0x00400000
15548 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
15549 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK 0xffbfffff
15550 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
15551 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET 0x0
15552 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS field value from a register. */
15553 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET(value) (((value) & 0x00400000) >> 22)
15554 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value suitable for setting the register. */
15555 #define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET(value) (((value) << 22) & 0x00400000)
15556 
15557 /*
15558  * Field : MMC Receive Watchdog Error Frame Counter Interrupt Status - rxwdogfis
15559  *
15560  * This bit is set when the rxwatchdogerror counter reaches half of the maximum
15561  * value or the maximum value.
15562  *
15563  * Field Enumeration Values:
15564  *
15565  * Enum | Value | Description
15566  * :-----------------------------------------|:------|:-----------------------------
15567  * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT | 0x0 | rxwatchdogerror < half max
15568  * ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT | 0x1 | rxwatchdogerror >= half max
15569  *
15570  * Field Access Macros:
15571  *
15572  */
15573 /*
15574  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
15575  *
15576  * rxwatchdogerror < half max
15577  */
15578 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT 0x0
15579 /*
15580  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
15581  *
15582  * rxwatchdogerror >= half max
15583  */
15584 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT 0x1
15585 
15586 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
15587 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB 23
15588 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
15589 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB 23
15590 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
15591 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH 1
15592 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
15593 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK 0x00800000
15594 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
15595 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK 0xff7fffff
15596 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
15597 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET 0x0
15598 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS field value from a register. */
15599 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET(value) (((value) & 0x00800000) >> 23)
15600 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value suitable for setting the register. */
15601 #define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET(value) (((value) << 23) & 0x00800000)
15602 
15603 /*
15604  * Field : MMC Receive Error Frame Counter Interrupt Status - rxrcverrfis
15605  *
15606  * This bit is set when the rxrcverror counter reaches half of the maximum value or
15607  * the maximum value.
15608  *
15609  * Field Access Macros:
15610  *
15611  */
15612 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
15613 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB 24
15614 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
15615 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB 24
15616 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
15617 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH 1
15618 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
15619 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK 0x01000000
15620 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
15621 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK 0xfeffffff
15622 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
15623 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET 0x0
15624 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS field value from a register. */
15625 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET(value) (((value) & 0x01000000) >> 24)
15626 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value suitable for setting the register. */
15627 #define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET(value) (((value) << 24) & 0x01000000)
15628 
15629 /*
15630  * Field : MMC Receive Control Frame Counter Interrupt Status - rxctrlfis
15631  *
15632  * This bit is set when the rxctrlframes_g counter reaches half of the maximum
15633  * value or the maximum value.
15634  *
15635  * Field Access Macros:
15636  *
15637  */
15638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
15639 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB 25
15640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
15641 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB 25
15642 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
15643 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH 1
15644 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
15645 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK 0x02000000
15646 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
15647 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK 0xfdffffff
15648 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
15649 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET 0x0
15650 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS field value from a register. */
15651 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET(value) (((value) & 0x02000000) >> 25)
15652 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value suitable for setting the register. */
15653 #define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET(value) (((value) << 25) & 0x02000000)
15654 
15655 #ifndef __ASSEMBLY__
15656 /*
15657  * WARNING: The C register and register group struct declarations are provided for
15658  * convenience and illustrative purposes. They should, however, be used with
15659  * caution as the C language standard provides no guarantees about the alignment or
15660  * atomicity of device memory accesses. The recommended practice for writing
15661  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15662  * alt_write_word() functions.
15663  *
15664  * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT.
15665  */
15666 struct ALT_EMAC_GMAC_MMC_RX_INT_s
15667 {
15668  const uint32_t rxgbfrmis : 1; /* MMC Receive Good Bad Frame Counter Interrupt Status */
15669  const uint32_t rxgboctis : 1; /* MMC Receive Good Bad Octet Counter Interrupt Status */
15670  const uint32_t rxgoctis : 1; /* MMC Receive Good Octet Counter Interrupt Status. */
15671  const uint32_t rxbcgfis : 1; /* MMC Receive Broadcast Good Frame Counter Interrupt Status. */
15672  const uint32_t rxmcgfis : 1; /* MMC Receive Multicast Good Frame Counter Interrupt Status */
15673  const uint32_t rxcrcerfis : 1; /* MMC Receive CRC Error Frame Counter Interrupt Status */
15674  const uint32_t rxalgnerfis : 1; /* MMC Receive Alignment Error Frame Counter Interrupt Status */
15675  const uint32_t rxruntfis : 1; /* MMC Receive Runt Frame Counter Interrupt Status */
15676  const uint32_t rxjaberfis : 1; /* MMC Receive Jabber Error Frame Counter Interrupt Status */
15677  const uint32_t rxusizegfis : 1; /* MMC Receive Undersize Good Frame Counter Interrupt Status */
15678  const uint32_t rxosizegfis : 1; /* MMC Receive Oversize Good Frame Counter Interrupt Status */
15679  const uint32_t rx64octgbfis : 1; /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status */
15680  const uint32_t rx65t127octgbfis : 1; /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status */
15681  const uint32_t rx128t255octgbfis : 1; /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status */
15682  const uint32_t rx256t511octgbfis : 1; /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status */
15683  const uint32_t rx512t1023octgbfis : 1; /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */
15684  const uint32_t rx1024tmaxoctgbfis : 1; /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */
15685  const uint32_t rxucgfis : 1; /* MMC Receive Unicast Good Frame Counter Interrupt Status */
15686  const uint32_t rxlenerfis : 1; /* MMC Receive Length Error Frame Counter Interrupt Status */
15687  const uint32_t rxorangefis : 1; /* MMC Receive Out Of Range Error Frame Counter Interrupt Status */
15688  const uint32_t rxpausfis : 1; /* MMC Receive Pause Frame Counter Interrupt Status */
15689  const uint32_t rxfovfis : 1; /* MMC Receive FIFO Overflow Frame Counter Interrupt Status */
15690  const uint32_t rxvlangbfis : 1; /* MMC Receive VLAN Good Bad Frame Counter Interrupt Status */
15691  const uint32_t rxwdogfis : 1; /* MMC Receive Watchdog Error Frame Counter Interrupt Status */
15692  const uint32_t rxrcverrfis : 1; /* MMC Receive Error Frame Counter Interrupt Status */
15693  const uint32_t rxctrlfis : 1; /* MMC Receive Control Frame Counter Interrupt Status */
15694  uint32_t : 6; /* *UNDEFINED* */
15695 };
15696 
15697 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT. */
15698 typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_s ALT_EMAC_GMAC_MMC_RX_INT_t;
15699 #endif /* __ASSEMBLY__ */
15700 
15701 /* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT register from the beginning of the component. */
15702 #define ALT_EMAC_GMAC_MMC_RX_INT_OFST 0x104
15703 /* The address of the ALT_EMAC_GMAC_MMC_RX_INT register. */
15704 #define ALT_EMAC_GMAC_MMC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST))
15705 
15706 /*
15707  * Register : Register 66 (MMC Transmit Interrupt Register) - MMC_Transmit_Interrupt
15708  *
15709  * The MMC Transmit Interrupt register maintains the interrupts generated when
15710  * transmit statistic counters reach half of their maximum values (0x8000_0000 for
15711  * 32-bit counter and 0x8000 for 16-bit counter), and the maximum values
15712  * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
15713  * Stop Rollover is set, then interrupts are set but the counter remains at all-
15714  * ones. The MMC Transmit Interrupt register is a 32-bit wide register. An
15715  * interrupt bit is cleared when the respective MMC counter that caused the
15716  * interrupt is read. The least significant byte lane (Bits[7:0]) of the respective
15717  * counter must be read in order to clear the interrupt bit.
15718  *
15719  * Register Layout
15720  *
15721  * Bits | Access | Reset | Description
15722  * :--------|:-------|:------|:---------------------------------------------------------------------------
15723  * [0] | R | 0x0 | MMC Transmit Good Bad Octet Counter Interrupt Status
15724  * [1] | R | 0x0 | MMC Transmit Good Bad Frame Counter Interrupt Status
15725  * [2] | R | 0x0 | MMC Transmit Broadcast Good Frame Counter Interrupt Status
15726  * [3] | R | 0x0 | MMC Transmit Multicast Good Frame Counter Interrupt Status
15727  * [4] | R | 0x0 | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status.
15728  * [5] | R | 0x0 | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status
15729  * [6] | R | 0x0 | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status
15730  * [7] | R | 0x0 | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status
15731  * [8] | R | 0x0 | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
15732  * [9] | R | 0x0 | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
15733  * [10] | R | 0x0 | MMC Transmit Unicast Good Bad Frame Counter Interrupt Status
15734  * [11] | R | 0x0 | MMC Transmit Multicast Good Bad Frame Counter Interrupt Status
15735  * [12] | R | 0x0 | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status
15736  * [13] | R | 0x0 | MMC Transmit Underflow Error Frame Counter Interrupt Status
15737  * [14] | R | 0x0 | MMC Transmit Single Collision Good Frame Counter Interrupt Status
15738  * [15] | R | 0x0 | MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
15739  * [16] | R | 0x0 | MMC Transmit Deferred Frame Counter Interrupt Status
15740  * [17] | R | 0x0 | MMC Transmit Late Collision Frame Counter Interrupt Status
15741  * [18] | R | 0x0 | MMC Transmit Excessive Collision Frame Counter Interrupt Status
15742  * [19] | R | 0x0 | MMC Transmit Carrier Error Frame Counter Interrupt Status
15743  * [20] | R | 0x0 | MMC Transmit Good Octet Counter Interrupt Status
15744  * [21] | R | 0x0 | MMC Transmit Good Frame Counter Interrupt Status
15745  * [22] | R | 0x0 | MMC Transmit Excessive Deferral Frame Counter Interrupt Status
15746  * [23] | R | 0x0 | MMC Transmit Pause Frame Counter Interrupt Status
15747  * [24] | R | 0x0 | MMC Transmit VLAN Good Frame Counter Interrupt Status
15748  * [25] | R | 0x0 | MMC Transmit Oversize Good Frame Counter Interrupt Status
15749  * [31:26] | ??? | 0x0 | *UNDEFINED*
15750  *
15751  */
15752 /*
15753  * Field : MMC Transmit Good Bad Octet Counter Interrupt Status - txgboctis
15754  *
15755  * This bit is set when the txoctetcount_gb counter reaches half of the maximum
15756  * value or the maximum value.
15757  *
15758  * Field Enumeration Values:
15759  *
15760  * Enum | Value | Description
15761  * :-----------------------------------------|:------|:-----------------------------
15762  * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT | 0x0 | txoctetcount_gb < half max
15763  * ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT | 0x1 | txoctetcount_gb >= half max
15764  *
15765  * Field Access Macros:
15766  *
15767  */
15768 /*
15769  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
15770  *
15771  * txoctetcount_gb < half max
15772  */
15773 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT 0x0
15774 /*
15775  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
15776  *
15777  * txoctetcount_gb >= half max
15778  */
15779 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT 0x1
15780 
15781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
15782 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB 0
15783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
15784 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB 0
15785 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
15786 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH 1
15787 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
15788 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK 0x00000001
15789 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
15790 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK 0xfffffffe
15791 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
15792 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET 0x0
15793 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS field value from a register. */
15794 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET(value) (((value) & 0x00000001) >> 0)
15795 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value suitable for setting the register. */
15796 #define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET(value) (((value) << 0) & 0x00000001)
15797 
15798 /*
15799  * Field : MMC Transmit Good Bad Frame Counter Interrupt Status - txgbfrmis
15800  *
15801  * This bit is set when the txframecount_gb counter reaches half of the maximum
15802  * value or the maximum value.
15803  *
15804  * Field Enumeration Values:
15805  *
15806  * Enum | Value | Description
15807  * :-----------------------------------------|:------|:-----------------------------
15808  * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT | 0x0 | txframecount_gb < half max
15809  * ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT | 0x1 | txframecount_gb >= half max
15810  *
15811  * Field Access Macros:
15812  *
15813  */
15814 /*
15815  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
15816  *
15817  * txframecount_gb < half max
15818  */
15819 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT 0x0
15820 /*
15821  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
15822  *
15823  * txframecount_gb >= half max
15824  */
15825 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT 0x1
15826 
15827 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
15828 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB 1
15829 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
15830 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB 1
15831 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
15832 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH 1
15833 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
15834 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK 0x00000002
15835 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
15836 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK 0xfffffffd
15837 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
15838 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET 0x0
15839 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS field value from a register. */
15840 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET(value) (((value) & 0x00000002) >> 1)
15841 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value suitable for setting the register. */
15842 #define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET(value) (((value) << 1) & 0x00000002)
15843 
15844 /*
15845  * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Status - txbcgfis
15846  *
15847  * This bit is set when the txbroadcastframes_g counter reaches half of the maximum
15848  * value or the maximum value.
15849  *
15850  * Field Enumeration Values:
15851  *
15852  * Enum | Value | Description
15853  * :----------------------------------------|:------|:---------------------------------
15854  * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT | 0x0 | txbroadcastframes_g < half max
15855  * ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT | 0x1 | txbroadcastframes_g >= half max
15856  *
15857  * Field Access Macros:
15858  *
15859  */
15860 /*
15861  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
15862  *
15863  * txbroadcastframes_g < half max
15864  */
15865 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0
15866 /*
15867  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
15868  *
15869  * txbroadcastframes_g >= half max
15870  */
15871 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT 0x1
15872 
15873 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
15874 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB 2
15875 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
15876 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB 2
15877 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
15878 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH 1
15879 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
15880 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK 0x00000004
15881 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
15882 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK 0xfffffffb
15883 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
15884 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET 0x0
15885 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS field value from a register. */
15886 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET(value) (((value) & 0x00000004) >> 2)
15887 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value suitable for setting the register. */
15888 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET(value) (((value) << 2) & 0x00000004)
15889 
15890 /*
15891  * Field : MMC Transmit Multicast Good Frame Counter Interrupt Status - txmcgfis
15892  *
15893  * This bit is set when the txmulticastframes_g counter reaches half of the maximum
15894  * value or the maximum value.
15895  *
15896  * Field Enumeration Values:
15897  *
15898  * Enum | Value | Description
15899  * :----------------------------------------|:------|:---------------------------------
15900  * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT | 0x0 | txmulticastframes_g < half max
15901  * ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT | 0x1 | txmulticastframes_g >= half max
15902  *
15903  * Field Access Macros:
15904  *
15905  */
15906 /*
15907  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
15908  *
15909  * txmulticastframes_g < half max
15910  */
15911 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0
15912 /*
15913  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
15914  *
15915  * txmulticastframes_g >= half max
15916  */
15917 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT 0x1
15918 
15919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
15920 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB 3
15921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
15922 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB 3
15923 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
15924 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH 1
15925 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
15926 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK 0x00000008
15927 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
15928 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK 0xfffffff7
15929 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
15930 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET 0x0
15931 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS field value from a register. */
15932 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET(value) (((value) & 0x00000008) >> 3)
15933 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value suitable for setting the register. */
15934 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET(value) (((value) << 3) & 0x00000008)
15935 
15936 /*
15937  * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. - tx64octgbfis
15938  *
15939  * This bit is set when the tx64octets_gb counter reaches half of the maximum value
15940  * or the maximum value.
15941  *
15942  * Field Enumeration Values:
15943  *
15944  * Enum | Value | Description
15945  * :-------------------------------------------|:------|:---------------------------
15946  * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD | 0x0 | tx64octets_gb < half max
15947  * ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END | 0x1 | tx64octets_gb >= half max
15948  *
15949  * Field Access Macros:
15950  *
15951  */
15952 /*
15953  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
15954  *
15955  * tx64octets_gb < half max
15956  */
15957 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD 0x0
15958 /*
15959  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
15960  *
15961  * tx64octets_gb >= half max
15962  */
15963 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END 0x1
15964 
15965 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
15966 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB 4
15967 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
15968 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB 4
15969 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
15970 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH 1
15971 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
15972 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK 0x00000010
15973 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
15974 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK 0xffffffef
15975 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
15976 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET 0x0
15977 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS field value from a register. */
15978 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000010) >> 4)
15979 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value suitable for setting the register. */
15980 #define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET(value) (((value) << 4) & 0x00000010)
15981 
15982 /*
15983  * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - tx65t127octgbfis
15984  *
15985  * This bit is set when the tx65to127octets_gb counter reaches half of the maximum
15986  * value or the maximum value.
15987  *
15988  * Field Enumeration Values:
15989  *
15990  * Enum | Value | Description
15991  * :------------------------------------------------|:------|:--------------------------------
15992  * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT | 0x0 | tx65to127octets_gb < half max
15993  * ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT | 0x1 | tx65to127octets_gb >= half max
15994  *
15995  * Field Access Macros:
15996  *
15997  */
15998 /*
15999  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
16000  *
16001  * tx65to127octets_gb < half max
16002  */
16003 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0
16004 /*
16005  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
16006  *
16007  * tx65to127octets_gb >= half max
16008  */
16009 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT 0x1
16010 
16011 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
16012 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB 5
16013 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
16014 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB 5
16015 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
16016 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH 1
16017 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
16018 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK 0x00000020
16019 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
16020 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK 0xffffffdf
16021 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
16022 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET 0x0
16023 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS field value from a register. */
16024 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00000020) >> 5)
16025 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
16026 #define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET(value) (((value) << 5) & 0x00000020)
16027 
16028 /*
16029  * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - tx128t255octgbfis
16030  *
16031  * This bit is set when the tx128to255octets_gb counter reaches half of the maximum
16032  * value or the maximum value.
16033  *
16034  * Field Enumeration Values:
16035  *
16036  * Enum | Value | Description
16037  * :-------------------------------------------------|:------|:---------------------------------
16038  * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT | 0x0 | tx128to255octets_gb < half max
16039  * ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT | 0x1 | tx128to255octets_gb >= half max
16040  *
16041  * Field Access Macros:
16042  *
16043  */
16044 /*
16045  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
16046  *
16047  * tx128to255octets_gb < half max
16048  */
16049 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT 0x0
16050 /*
16051  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
16052  *
16053  * tx128to255octets_gb >= half max
16054  */
16055 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT 0x1
16056 
16057 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
16058 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB 6
16059 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
16060 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB 6
16061 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
16062 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH 1
16063 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
16064 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK 0x00000040
16065 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
16066 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK 0xffffffbf
16067 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
16068 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET 0x0
16069 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS field value from a register. */
16070 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00000040) >> 6)
16071 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
16072 #define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET(value) (((value) << 6) & 0x00000040)
16073 
16074 /*
16075  * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - tx256t511octgbfis
16076  *
16077  * This bit is set when the tx256to511octets_gb counter reaches half of the maximum
16078  * value or the maximum value.
16079  *
16080  * Field Enumeration Values:
16081  *
16082  * Enum | Value | Description
16083  * :-------------------------------------------------|:------|:---------------------------------
16084  * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT | 0x0 | tx256to511octets_gb < half max
16085  * ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT | 0x1 | tx256to511octets_gb >= half max
16086  *
16087  * Field Access Macros:
16088  *
16089  */
16090 /*
16091  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
16092  *
16093  * tx256to511octets_gb < half max
16094  */
16095 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT 0x0
16096 /*
16097  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
16098  *
16099  * tx256to511octets_gb >= half max
16100  */
16101 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT 0x1
16102 
16103 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
16104 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB 7
16105 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
16106 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB 7
16107 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
16108 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH 1
16109 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
16110 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK 0x00000080
16111 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
16112 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK 0xffffff7f
16113 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
16114 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET 0x0
16115 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS field value from a register. */
16116 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00000080) >> 7)
16117 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
16118 #define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET(value) (((value) << 7) & 0x00000080)
16119 
16120 /*
16121  * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - tx512t1023octgbfis
16122  *
16123  * This bit is set when the tx512to1023octets_gb counter reaches half of the
16124  * maximum value or the maximum value.
16125  *
16126  * Field Enumeration Values:
16127  *
16128  * Enum | Value | Description
16129  * :--------------------------------------------------|:------|:----------------------------------
16130  * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT | 0x0 | tx512to1023octets_gb < half max
16131  * ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT | 0x1 | tx512to1023octets_gb >= half max
16132  *
16133  * Field Access Macros:
16134  *
16135  */
16136 /*
16137  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
16138  *
16139  * tx512to1023octets_gb < half max
16140  */
16141 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT 0x0
16142 /*
16143  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
16144  *
16145  * tx512to1023octets_gb >= half max
16146  */
16147 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT 0x1
16148 
16149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
16150 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB 8
16151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
16152 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB 8
16153 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
16154 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH 1
16155 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
16156 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK 0x00000100
16157 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
16158 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK 0xfffffeff
16159 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
16160 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET 0x0
16161 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS field value from a register. */
16162 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00000100) >> 8)
16163 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
16164 #define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET(value) (((value) << 8) & 0x00000100)
16165 
16166 /*
16167  * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - tx1024tmaxoctgbfis
16168  *
16169  * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the
16170  * maximum value or the maximum value.
16171  *
16172  * Field Enumeration Values:
16173  *
16174  * Enum | Value | Description
16175  * :--------------------------------------------------|:------|:-----------------------------------
16176  * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 | tx1024tomaxoctets_gb < half max
16177  * ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 | tx1024tomaxoctets_gb >= half max
16178  *
16179  * Field Access Macros:
16180  *
16181  */
16182 /*
16183  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
16184  *
16185  * tx1024tomaxoctets_gb < half max
16186  */
16187 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT 0x0
16188 /*
16189  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
16190  *
16191  * tx1024tomaxoctets_gb >= half max
16192  */
16193 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT 0x1
16194 
16195 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
16196 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB 9
16197 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
16198 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB 9
16199 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
16200 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH 1
16201 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
16202 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00000200
16203 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
16204 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffffdff
16205 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
16206 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET 0x0
16207 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS field value from a register. */
16208 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00000200) >> 9)
16209 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
16210 #define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 9) & 0x00000200)
16211 
16212 /*
16213  * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - txucgbfis
16214  *
16215  * This bit is set when the txunicastframes_gb counter reaches half of the maximum
16216  * value or the maximum value.
16217  *
16218  * Field Enumeration Values:
16219  *
16220  * Enum | Value | Description
16221  * :-----------------------------------------|:------|:---------------------------------
16222  * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT | 0x0 | txunicastframes_bb < half max
16223  * ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT | 0x1 | txunicastframes_bb >= half max
16224  *
16225  * Field Access Macros:
16226  *
16227  */
16228 /*
16229  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
16230  *
16231  * txunicastframes_bb < half max
16232  */
16233 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT 0x0
16234 /*
16235  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
16236  *
16237  * txunicastframes_bb >= half max
16238  */
16239 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT 0x1
16240 
16241 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
16242 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB 10
16243 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
16244 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB 10
16245 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
16246 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH 1
16247 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
16248 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK 0x00000400
16249 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
16250 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK 0xfffffbff
16251 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
16252 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET 0x0
16253 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS field value from a register. */
16254 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET(value) (((value) & 0x00000400) >> 10)
16255 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value suitable for setting the register. */
16256 #define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET(value) (((value) << 10) & 0x00000400)
16257 
16258 /*
16259  * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - txmcgbfis
16260  *
16261  * This bit is set when the txmulticastframes_gb counter reaches half of the
16262  * maximum value or the maximum value.
16263  *
16264  * Field Enumeration Values:
16265  *
16266  * Enum | Value | Description
16267  * :-----------------------------------------|:------|:-----------------------------------
16268  * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT | 0x0 | txmulticastframes_gb < half max
16269  * ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT | 0x1 | txmulticastframes_gb >= half max
16270  *
16271  * Field Access Macros:
16272  *
16273  */
16274 /*
16275  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
16276  *
16277  * txmulticastframes_gb < half max
16278  */
16279 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT 0x0
16280 /*
16281  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
16282  *
16283  * txmulticastframes_gb >= half max
16284  */
16285 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT 0x1
16286 
16287 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
16288 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB 11
16289 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
16290 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB 11
16291 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
16292 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH 1
16293 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
16294 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK 0x00000800
16295 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
16296 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK 0xfffff7ff
16297 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
16298 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET 0x0
16299 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS field value from a register. */
16300 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET(value) (((value) & 0x00000800) >> 11)
16301 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value suitable for setting the register. */
16302 #define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET(value) (((value) << 11) & 0x00000800)
16303 
16304 /*
16305  * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - txbcgbfis
16306  *
16307  * This bit is set when the txbroadcastframes_gb counter reaches half of the
16308  * maximum value or the maximum value.
16309  *
16310  * Field Enumeration Values:
16311  *
16312  * Enum | Value | Description
16313  * :----------------------------------------|:------|:-----------------------------------
16314  * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD | 0x0 | txbroadcastframes_gb < half max
16315  * ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END | 0x1 | txbroadcastframes_gb >= half max
16316  *
16317  * Field Access Macros:
16318  *
16319  */
16320 /*
16321  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
16322  *
16323  * txbroadcastframes_gb < half max
16324  */
16325 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0
16326 /*
16327  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
16328  *
16329  * txbroadcastframes_gb >= half max
16330  */
16331 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END 0x1
16332 
16333 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
16334 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB 12
16335 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
16336 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB 12
16337 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
16338 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH 1
16339 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
16340 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK 0x00001000
16341 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
16342 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK 0xffffefff
16343 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
16344 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET 0x0
16345 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS field value from a register. */
16346 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET(value) (((value) & 0x00001000) >> 12)
16347 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value suitable for setting the register. */
16348 #define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET(value) (((value) << 12) & 0x00001000)
16349 
16350 /*
16351  * Field : MMC Transmit Underflow Error Frame Counter Interrupt Status - txuflowerfis
16352  *
16353  * This bit is set when the txunderflowerror counter reaches half of the maximum
16354  * value or the maximum value.
16355  *
16356  * Field Enumeration Values:
16357  *
16358  * Enum | Value | Description
16359  * :-------------------------------------------|:------|:---------------------------------------
16360  * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD | 0x0 | txunderflowerror counter < half max
16361  * ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END | 0x1 | txunderflowerror counter >= half max
16362  *
16363  * Field Access Macros:
16364  *
16365  */
16366 /*
16367  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
16368  *
16369  * txunderflowerror counter < half max
16370  */
16371 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD 0x0
16372 /*
16373  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
16374  *
16375  * txunderflowerror counter >= half max
16376  */
16377 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END 0x1
16378 
16379 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
16380 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB 13
16381 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
16382 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB 13
16383 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
16384 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH 1
16385 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
16386 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK 0x00002000
16387 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
16388 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK 0xffffdfff
16389 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
16390 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET 0x0
16391 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS field value from a register. */
16392 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET(value) (((value) & 0x00002000) >> 13)
16393 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value suitable for setting the register. */
16394 #define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET(value) (((value) << 13) & 0x00002000)
16395 
16396 /*
16397  * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Status - txscolgfis
16398  *
16399  * This bit is set when the txsinglecol_g counter reaches half of the maximum value
16400  * or the maximum value.
16401  *
16402  * Field Enumeration Values:
16403  *
16404  * Enum | Value | Description
16405  * :-----------------------------------------|:------|:------------------------------------
16406  * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD | 0x0 | txsinglecol_g counter < half max
16407  * ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END | 0x1 | txsinglecol_g counter >= half max
16408  *
16409  * Field Access Macros:
16410  *
16411  */
16412 /*
16413  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
16414  *
16415  * txsinglecol_g counter < half max
16416  */
16417 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD 0x0
16418 /*
16419  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
16420  *
16421  * txsinglecol_g counter >= half max
16422  */
16423 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END 0x1
16424 
16425 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
16426 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB 14
16427 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
16428 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB 14
16429 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
16430 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH 1
16431 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
16432 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK 0x00004000
16433 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
16434 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK 0xffffbfff
16435 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
16436 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET 0x0
16437 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS field value from a register. */
16438 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET(value) (((value) & 0x00004000) >> 14)
16439 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value suitable for setting the register. */
16440 #define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET(value) (((value) << 14) & 0x00004000)
16441 
16442 /*
16443  * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - txmcolgfis
16444  *
16445  * This bit is set when the txmulticol_g counter reaches half of the maximum value
16446  * or the maximum value.
16447  *
16448  * Field Enumeration Values:
16449  *
16450  * Enum | Value | Description
16451  * :-----------------------------------------|:------|:-----------------------------------
16452  * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD | 0x0 | txmulticol_g counter < half max
16453  * ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END | 0x1 | txmulticol_g counter >= half max
16454  *
16455  * Field Access Macros:
16456  *
16457  */
16458 /*
16459  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
16460  *
16461  * txmulticol_g counter < half max
16462  */
16463 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD 0x0
16464 /*
16465  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
16466  *
16467  * txmulticol_g counter >= half max
16468  */
16469 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END 0x1
16470 
16471 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
16472 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB 15
16473 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
16474 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB 15
16475 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
16476 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH 1
16477 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
16478 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK 0x00008000
16479 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
16480 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK 0xffff7fff
16481 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
16482 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET 0x0
16483 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS field value from a register. */
16484 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET(value) (((value) & 0x00008000) >> 15)
16485 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value suitable for setting the register. */
16486 #define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET(value) (((value) << 15) & 0x00008000)
16487 
16488 /*
16489  * Field : MMC Transmit Deferred Frame Counter Interrupt Status - txdeffis
16490  *
16491  * This bit is set when the txdeferred counter reaches half of the maximum value or
16492  * the maximum value.
16493  *
16494  * Field Enumeration Values:
16495  *
16496  * Enum | Value | Description
16497  * :---------------------------------------|:------|:---------------------------------
16498  * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD | 0x0 | txdeferred counter < half max
16499  * ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END | 0x1 | txdeferred counter >= half max
16500  *
16501  * Field Access Macros:
16502  *
16503  */
16504 /*
16505  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
16506  *
16507  * txdeferred counter < half max
16508  */
16509 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD 0x0
16510 /*
16511  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
16512  *
16513  * txdeferred counter >= half max
16514  */
16515 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END 0x1
16516 
16517 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
16518 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB 16
16519 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
16520 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB 16
16521 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
16522 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH 1
16523 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
16524 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK 0x00010000
16525 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
16526 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK 0xfffeffff
16527 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
16528 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET 0x0
16529 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS field value from a register. */
16530 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET(value) (((value) & 0x00010000) >> 16)
16531 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value suitable for setting the register. */
16532 #define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET(value) (((value) << 16) & 0x00010000)
16533 
16534 /*
16535  * Field : MMC Transmit Late Collision Frame Counter Interrupt Status - txlatcolfis
16536  *
16537  * This bit is set when the txlatecol counter reaches half of the maximum value or
16538  * the maximum value.
16539  *
16540  * Field Enumeration Values:
16541  *
16542  * Enum | Value | Description
16543  * :------------------------------------------|:------|:--------------------------------
16544  * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD | 0x0 | txlatecol counter < half max
16545  * ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END | 0x1 | txlatecol counter >= half max
16546  *
16547  * Field Access Macros:
16548  *
16549  */
16550 /*
16551  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
16552  *
16553  * txlatecol counter < half max
16554  */
16555 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD 0x0
16556 /*
16557  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
16558  *
16559  * txlatecol counter >= half max
16560  */
16561 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END 0x1
16562 
16563 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
16564 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB 17
16565 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
16566 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB 17
16567 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
16568 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH 1
16569 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
16570 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK 0x00020000
16571 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
16572 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK 0xfffdffff
16573 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
16574 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET 0x0
16575 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS field value from a register. */
16576 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET(value) (((value) & 0x00020000) >> 17)
16577 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value suitable for setting the register. */
16578 #define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET(value) (((value) << 17) & 0x00020000)
16579 
16580 /*
16581  * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Status - txexcolfis
16582  *
16583  * This bit is set when the txexcesscol counter reaches half of the maximum value
16584  * or the maximum value.
16585  *
16586  * Field Enumeration Values:
16587  *
16588  * Enum | Value | Description
16589  * :-----------------------------------------|:------|:---------------------------------
16590  * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD | 0x0 | txexesscol counter < half max
16591  * ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END | 0x1 | txexesscol counter >= half max
16592  *
16593  * Field Access Macros:
16594  *
16595  */
16596 /*
16597  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
16598  *
16599  * txexesscol counter < half max
16600  */
16601 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD 0x0
16602 /*
16603  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
16604  *
16605  * txexesscol counter >= half max
16606  */
16607 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END 0x1
16608 
16609 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
16610 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB 18
16611 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
16612 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB 18
16613 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
16614 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH 1
16615 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
16616 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK 0x00040000
16617 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
16618 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK 0xfffbffff
16619 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
16620 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET 0x0
16621 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS field value from a register. */
16622 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET(value) (((value) & 0x00040000) >> 18)
16623 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value suitable for setting the register. */
16624 #define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET(value) (((value) << 18) & 0x00040000)
16625 
16626 /*
16627  * Field : MMC Transmit Carrier Error Frame Counter Interrupt Status - txcarerfis
16628  *
16629  * This bit is set when the txcarriererror counter reaches half of the maximum
16630  * value or the maximum value.
16631  *
16632  * Field Enumeration Values:
16633  *
16634  * Enum | Value | Description
16635  * :-----------------------------------------|:------|:-------------------------------------
16636  * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD | 0x0 | txcarriererror counter < half max
16637  * ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END | 0x1 | txcarriererror counter >= half max
16638  *
16639  * Field Access Macros:
16640  *
16641  */
16642 /*
16643  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
16644  *
16645  * txcarriererror counter < half max
16646  */
16647 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD 0x0
16648 /*
16649  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
16650  *
16651  * txcarriererror counter >= half max
16652  */
16653 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END 0x1
16654 
16655 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
16656 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB 19
16657 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
16658 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB 19
16659 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
16660 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH 1
16661 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
16662 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK 0x00080000
16663 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
16664 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK 0xfff7ffff
16665 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
16666 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET 0x0
16667 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS field value from a register. */
16668 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET(value) (((value) & 0x00080000) >> 19)
16669 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value suitable for setting the register. */
16670 #define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET(value) (((value) << 19) & 0x00080000)
16671 
16672 /*
16673  * Field : MMC Transmit Good Octet Counter Interrupt Status - txgoctis
16674  *
16675  * This bit is set when the txoctetcount_g counter reaches half of the maximum
16676  * value or the maximum value.
16677  *
16678  * Field Enumeration Values:
16679  *
16680  * Enum | Value | Description
16681  * :---------------------------------------|:------|:-------------------------------------
16682  * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD | 0x0 | txoctetcount_g counter < half max
16683  * ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END | 0x1 | txoctetcount_g counter >= half max
16684  *
16685  * Field Access Macros:
16686  *
16687  */
16688 /*
16689  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
16690  *
16691  * txoctetcount_g counter < half max
16692  */
16693 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD 0x0
16694 /*
16695  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
16696  *
16697  * txoctetcount_g counter >= half max
16698  */
16699 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END 0x1
16700 
16701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
16702 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB 20
16703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
16704 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB 20
16705 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
16706 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH 1
16707 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
16708 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK 0x00100000
16709 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
16710 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK 0xffefffff
16711 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
16712 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET 0x0
16713 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS field value from a register. */
16714 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET(value) (((value) & 0x00100000) >> 20)
16715 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value suitable for setting the register. */
16716 #define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET(value) (((value) << 20) & 0x00100000)
16717 
16718 /*
16719  * Field : MMC Transmit Good Frame Counter Interrupt Status - txgfrmis
16720  *
16721  * This bit is set when the txframecount_g counter reaches half of the maximum
16722  * value or the maximum value.
16723  *
16724  * Field Enumeration Values:
16725  *
16726  * Enum | Value | Description
16727  * :---------------------------------------|:------|:-------------------------------------
16728  * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD | 0x0 | txframecount_g counter < half max
16729  * ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END | 0x1 | txframecount_g counter >= half max
16730  *
16731  * Field Access Macros:
16732  *
16733  */
16734 /*
16735  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
16736  *
16737  * txframecount_g counter < half max
16738  */
16739 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD 0x0
16740 /*
16741  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
16742  *
16743  * txframecount_g counter >= half max
16744  */
16745 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END 0x1
16746 
16747 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
16748 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB 21
16749 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
16750 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB 21
16751 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
16752 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH 1
16753 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
16754 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK 0x00200000
16755 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
16756 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK 0xffdfffff
16757 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
16758 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET 0x0
16759 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS field value from a register. */
16760 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET(value) (((value) & 0x00200000) >> 21)
16761 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value suitable for setting the register. */
16762 #define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET(value) (((value) << 21) & 0x00200000)
16763 
16764 /*
16765  * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Status - txexdeffis
16766  *
16767  * This bit is set when the txexcessdef counter reaches half of the maximum value
16768  * or the maximum value.
16769  *
16770  * Field Enumeration Values:
16771  *
16772  * Enum | Value | Description
16773  * :-----------------------------------------|:------|:-----------------------------------
16774  * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD | 0x0 | txoexcessdef counter < half max
16775  * ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END | 0x1 | txoexcessdef counter >= half max
16776  *
16777  * Field Access Macros:
16778  *
16779  */
16780 /*
16781  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
16782  *
16783  * txoexcessdef counter < half max
16784  */
16785 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD 0x0
16786 /*
16787  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
16788  *
16789  * txoexcessdef counter >= half max
16790  */
16791 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END 0x1
16792 
16793 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
16794 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB 22
16795 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
16796 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB 22
16797 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
16798 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH 1
16799 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
16800 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK 0x00400000
16801 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
16802 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK 0xffbfffff
16803 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
16804 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET 0x0
16805 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS field value from a register. */
16806 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET(value) (((value) & 0x00400000) >> 22)
16807 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value suitable for setting the register. */
16808 #define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET(value) (((value) << 22) & 0x00400000)
16809 
16810 /*
16811  * Field : MMC Transmit Pause Frame Counter Interrupt Status - txpausfis
16812  *
16813  * This bit is set when the txpauseframeserror counter reaches half of the maximum
16814  * value or the maximum value.
16815  *
16816  * Field Enumeration Values:
16817  *
16818  * Enum | Value | Description
16819  * :----------------------------------------|:------|:-----------------------------------------
16820  * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD | 0x0 | txpauseframeserror counter < half max
16821  * ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END | 0x1 | txpauseframeserror counter >= half max
16822  *
16823  * Field Access Macros:
16824  *
16825  */
16826 /*
16827  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
16828  *
16829  * txpauseframeserror counter < half max
16830  */
16831 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0
16832 /*
16833  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
16834  *
16835  * txpauseframeserror counter >= half max
16836  */
16837 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END 0x1
16838 
16839 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
16840 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB 23
16841 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
16842 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB 23
16843 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
16844 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH 1
16845 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
16846 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK 0x00800000
16847 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
16848 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK 0xff7fffff
16849 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
16850 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET 0x0
16851 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS field value from a register. */
16852 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET(value) (((value) & 0x00800000) >> 23)
16853 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value suitable for setting the register. */
16854 #define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET(value) (((value) << 23) & 0x00800000)
16855 
16856 /*
16857  * Field : MMC Transmit VLAN Good Frame Counter Interrupt Status - txvlangfis
16858  *
16859  * This bit is set when the txvlanframes_g counter reaches half of the maximum
16860  * value or the maximum value.
16861  *
16862  * Field Enumeration Values:
16863  *
16864  * Enum | Value | Description
16865  * :-----------------------------------------|:------|:-------------------------------------
16866  * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD | 0x0 | txvlanframes_g counter < half max
16867  * ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END | 0x1 | txvlanframes_g counter >= half max
16868  *
16869  * Field Access Macros:
16870  *
16871  */
16872 /*
16873  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
16874  *
16875  * txvlanframes_g counter < half max
16876  */
16877 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD 0x0
16878 /*
16879  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
16880  *
16881  * txvlanframes_g counter >= half max
16882  */
16883 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END 0x1
16884 
16885 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
16886 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB 24
16887 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
16888 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB 24
16889 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
16890 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH 1
16891 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
16892 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK 0x01000000
16893 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
16894 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK 0xfeffffff
16895 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
16896 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET 0x0
16897 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS field value from a register. */
16898 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET(value) (((value) & 0x01000000) >> 24)
16899 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value suitable for setting the register. */
16900 #define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET(value) (((value) << 24) & 0x01000000)
16901 
16902 /*
16903  * Field : MMC Transmit Oversize Good Frame Counter Interrupt Status - txosizegfis
16904  *
16905  * This bit is set when the txoversize_g counter reaches half of the maximum value
16906  * or the maximum value.
16907  *
16908  * Field Access Macros:
16909  *
16910  */
16911 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
16912 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB 25
16913 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
16914 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB 25
16915 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
16916 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH 1
16917 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
16918 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK 0x02000000
16919 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
16920 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK 0xfdffffff
16921 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
16922 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET 0x0
16923 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS field value from a register. */
16924 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET(value) (((value) & 0x02000000) >> 25)
16925 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value suitable for setting the register. */
16926 #define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET(value) (((value) << 25) & 0x02000000)
16927 
16928 #ifndef __ASSEMBLY__
16929 /*
16930  * WARNING: The C register and register group struct declarations are provided for
16931  * convenience and illustrative purposes. They should, however, be used with
16932  * caution as the C language standard provides no guarantees about the alignment or
16933  * atomicity of device memory accesses. The recommended practice for writing
16934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16935  * alt_write_word() functions.
16936  *
16937  * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT.
16938  */
16939 struct ALT_EMAC_GMAC_MMC_TX_INT_s
16940 {
16941  const uint32_t txgboctis : 1; /* MMC Transmit Good Bad Octet Counter Interrupt Status */
16942  const uint32_t txgbfrmis : 1; /* MMC Transmit Good Bad Frame Counter Interrupt Status */
16943  const uint32_t txbcgfis : 1; /* MMC Transmit Broadcast Good Frame Counter Interrupt Status */
16944  const uint32_t txmcgfis : 1; /* MMC Transmit Multicast Good Frame Counter Interrupt Status */
16945  const uint32_t tx64octgbfis : 1; /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. */
16946  const uint32_t tx65t127octgbfis : 1; /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status */
16947  const uint32_t tx128t255octgbfis : 1; /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status */
16948  const uint32_t tx256t511octgbfis : 1; /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status */
16949  const uint32_t tx512t1023octgbfis : 1; /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */
16950  const uint32_t tx1024tmaxoctgbfis : 1; /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */
16951  const uint32_t txucgbfis : 1; /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Status */
16952  const uint32_t txmcgbfis : 1; /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Status */
16953  const uint32_t txbcgbfis : 1; /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status */
16954  const uint32_t txuflowerfis : 1; /* MMC Transmit Underflow Error Frame Counter Interrupt Status */
16955  const uint32_t txscolgfis : 1; /* MMC Transmit Single Collision Good Frame Counter Interrupt Status */
16956  const uint32_t txmcolgfis : 1; /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Status */
16957  const uint32_t txdeffis : 1; /* MMC Transmit Deferred Frame Counter Interrupt Status */
16958  const uint32_t txlatcolfis : 1; /* MMC Transmit Late Collision Frame Counter Interrupt Status */
16959  const uint32_t txexcolfis : 1; /* MMC Transmit Excessive Collision Frame Counter Interrupt Status */
16960  const uint32_t txcarerfis : 1; /* MMC Transmit Carrier Error Frame Counter Interrupt Status */
16961  const uint32_t txgoctis : 1; /* MMC Transmit Good Octet Counter Interrupt Status */
16962  const uint32_t txgfrmis : 1; /* MMC Transmit Good Frame Counter Interrupt Status */
16963  const uint32_t txexdeffis : 1; /* MMC Transmit Excessive Deferral Frame Counter Interrupt Status */
16964  const uint32_t txpausfis : 1; /* MMC Transmit Pause Frame Counter Interrupt Status */
16965  const uint32_t txvlangfis : 1; /* MMC Transmit VLAN Good Frame Counter Interrupt Status */
16966  const uint32_t txosizegfis : 1; /* MMC Transmit Oversize Good Frame Counter Interrupt Status */
16967  uint32_t : 6; /* *UNDEFINED* */
16968 };
16969 
16970 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT. */
16971 typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_s ALT_EMAC_GMAC_MMC_TX_INT_t;
16972 #endif /* __ASSEMBLY__ */
16973 
16974 /* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT register from the beginning of the component. */
16975 #define ALT_EMAC_GMAC_MMC_TX_INT_OFST 0x108
16976 /* The address of the ALT_EMAC_GMAC_MMC_TX_INT register. */
16977 #define ALT_EMAC_GMAC_MMC_TX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST))
16978 
16979 /*
16980  * Register : Register 67 (MMC Receive Interrupt Mask Register) - MMC_Receive_Interrupt_Mask
16981  *
16982  * The MMC Receive Interrupt Mask register maintains the masks for the interrupts
16983  * generated when the receive statistic counters reach half of their maximum value,
16984  * or maximum value. This register is 32-bits wide.
16985  *
16986  * Register Layout
16987  *
16988  * Bits | Access | Reset | Description
16989  * :--------|:-------|:------|:------------------------------------------------------------------------
16990  * [0] | RW | 0x0 | MMC Receive Good Bad Frame Counter Interrupt Mask
16991  * [1] | RW | 0x0 | MMC Receive Good Bad Octet Counter Interrupt Mask
16992  * [2] | RW | 0x0 | MMC Receive Good Octet Counter Interrupt Mask
16993  * [3] | RW | 0x0 | MMC Receive Broadcast Good Frame Counter Interrupt Mask
16994  * [4] | RW | 0x0 | MMC Receive Multicast Good Frame Counter Interrupt Mask
16995  * [5] | RW | 0x0 | MMC Receive CRC Error Frame Counter Interrupt Mask
16996  * [6] | RW | 0x0 | MMC Receive Alignment Error Frame Counter Interrupt Mask
16997  * [7] | RW | 0x0 | MMC Receive Runt Frame Counter Interrupt Mask
16998  * [8] | RW | 0x0 | MMC Receive Jabber Error Frame Counter Interrupt Mask
16999  * [9] | RW | 0x0 | MMC Receive Undersize Good Frame Counter Interrupt Mask
17000  * [10] | RW | 0x0 | MMC Receive Oversize Good Frame Counter Interrupt Mask
17001  * [11] | RW | 0x0 | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask
17002  * [12] | RW | 0x0 | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
17003  * [13] | RW | 0x0 | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
17004  * [14] | RW | 0x0 | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
17005  * [15] | RW | 0x0 | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
17006  * [16] | RW | 0x0 | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
17007  * [17] | RW | 0x0 | MMC Receive Unicast Good Frame Counter Interrupt Mask
17008  * [18] | RW | 0x0 | MMC Receive Length Error Frame Counter Interrupt Mask
17009  * [19] | RW | 0x0 | MMC Receive Out Of Range Error Frame Counter Interrupt Mask
17010  * [20] | RW | 0x0 | MMC Receive Pause Frame Counter Interrupt Mask
17011  * [21] | RW | 0x0 | MMC Receive FIFO Overflow Frame Counter Interrupt Mask
17012  * [22] | RW | 0x0 | MMC Receive VLAN Good Bad Frame Counter Interrupt Mask
17013  * [23] | RW | 0x0 | MMC Receive Watchdog Error Frame Counter Interrupt Mask
17014  * [24] | RW | 0x0 | MMC Receive Error Frame Counter Interrupt Mask
17015  * [25] | RW | 0x0 | MMC Receive Control Frame Counter Interrupt Mask
17016  * [31:26] | ??? | 0x0 | *UNDEFINED*
17017  *
17018  */
17019 /*
17020  * Field : MMC Receive Good Bad Frame Counter Interrupt Mask - rxgbfrmim
17021  *
17022  * Setting this bit masks the interrupt when the rxframecount_gb counter reaches
17023  * half of the maximum value or the maximum value.
17024  *
17025  * Field Enumeration Values:
17026  *
17027  * Enum | Value | Description
17028  * :-------------------------------------------------|:------|:---------------------------
17029  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 | counter < half max
17030  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 | counter >= half max or max
17031  *
17032  * Field Access Macros:
17033  *
17034  */
17035 /*
17036  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
17037  *
17038  * counter < half max
17039  */
17040 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0
17041 /*
17042  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
17043  *
17044  * counter >= half max or max
17045  */
17046 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR 0x1
17047 
17048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
17049 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB 0
17050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
17051 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB 0
17052 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
17053 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH 1
17054 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
17055 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK 0x00000001
17056 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
17057 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffe
17058 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
17059 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET 0x0
17060 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM field value from a register. */
17061 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000001) >> 0)
17062 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
17063 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET(value) (((value) << 0) & 0x00000001)
17064 
17065 /*
17066  * Field : MMC Receive Good Bad Octet Counter Interrupt Mask - rxgboctim
17067  *
17068  * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches
17069  * half of the maximum value or the maximum value.
17070  *
17071  * Field Enumeration Values:
17072  *
17073  * Enum | Value | Description
17074  * :-------------------------------------------------|:------|:---------------------------
17075  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 | counter < half max
17076  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 | counter >= half max or max
17077  *
17078  * Field Access Macros:
17079  *
17080  */
17081 /*
17082  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
17083  *
17084  * counter < half max
17085  */
17086 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0
17087 /*
17088  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
17089  *
17090  * counter >= half max or max
17091  */
17092 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR 0x1
17093 
17094 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
17095 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB 1
17096 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
17097 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB 1
17098 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
17099 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH 1
17100 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
17101 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK 0x00000002
17102 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
17103 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffd
17104 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
17105 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET 0x0
17106 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM field value from a register. */
17107 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000002) >> 1)
17108 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
17109 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET(value) (((value) << 1) & 0x00000002)
17110 
17111 /*
17112  * Field : MMC Receive Good Octet Counter Interrupt Mask - rxgoctim
17113  *
17114  * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches
17115  * half of the maximum value or the maximum value.
17116  *
17117  * Field Enumeration Values:
17118  *
17119  * Enum | Value | Description
17120  * :------------------------------------------------|:------|:---------------------------
17121  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 | counter < half max
17122  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 | counter >= half max or max
17123  *
17124  * Field Access Macros:
17125  *
17126  */
17127 /*
17128  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
17129  *
17130  * counter < half max
17131  */
17132 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
17133 /*
17134  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
17135  *
17136  * counter >= half max or max
17137  */
17138 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR 0x1
17139 
17140 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
17141 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB 2
17142 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
17143 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB 2
17144 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
17145 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH 1
17146 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
17147 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK 0x00000004
17148 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
17149 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK 0xfffffffb
17150 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
17151 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET 0x0
17152 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM field value from a register. */
17153 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00000004) >> 2)
17154 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value suitable for setting the register. */
17155 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET(value) (((value) << 2) & 0x00000004)
17156 
17157 /*
17158  * Field : MMC Receive Broadcast Good Frame Counter Interrupt Mask - rxbcgfim
17159  *
17160  * Setting this bit masks the interrupt when the rxbroadcastframes_g counter
17161  * reaches half of the maximum value or the maximum value.
17162  *
17163  * Field Enumeration Values:
17164  *
17165  * Enum | Value | Description
17166  * :------------------------------------------------|:------|:---------------------------
17167  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 | counter < half max
17168  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 | counter >= half max or max
17169  *
17170  * Field Access Macros:
17171  *
17172  */
17173 /*
17174  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
17175  *
17176  * counter < half max
17177  */
17178 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
17179 /*
17180  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
17181  *
17182  * counter >= half max or max
17183  */
17184 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR 0x1
17185 
17186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
17187 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB 3
17188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
17189 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB 3
17190 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
17191 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH 1
17192 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
17193 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK 0x00000008
17194 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
17195 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK 0xfffffff7
17196 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
17197 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET 0x0
17198 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM field value from a register. */
17199 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000008) >> 3)
17200 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value suitable for setting the register. */
17201 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET(value) (((value) << 3) & 0x00000008)
17202 
17203 /*
17204  * Field : MMC Receive Multicast Good Frame Counter Interrupt Mask - rxmcgfim
17205  *
17206  * Setting this bit masks the interrupt when the rxmulticastframes_g counter
17207  * reaches half of the maximum value or the maximum value.
17208  *
17209  * Field Enumeration Values:
17210  *
17211  * Enum | Value | Description
17212  * :------------------------------------------------|:------|:---------------------------
17213  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 | counter < half max
17214  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 | counter >= half max or max
17215  *
17216  * Field Access Macros:
17217  *
17218  */
17219 /*
17220  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
17221  *
17222  * counter < half max
17223  */
17224 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
17225 /*
17226  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
17227  *
17228  * counter >= half max or max
17229  */
17230 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR 0x1
17231 
17232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
17233 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB 4
17234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
17235 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB 4
17236 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
17237 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH 1
17238 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
17239 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK 0x00000010
17240 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
17241 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK 0xffffffef
17242 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
17243 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET 0x0
17244 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM field value from a register. */
17245 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000010) >> 4)
17246 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value suitable for setting the register. */
17247 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET(value) (((value) << 4) & 0x00000010)
17248 
17249 /*
17250  * Field : MMC Receive CRC Error Frame Counter Interrupt Mask - rxcrcerfim
17251  *
17252  * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of
17253  * the maximum value or the maximum value.
17254  *
17255  * Field Enumeration Values:
17256  *
17257  * Enum | Value | Description
17258  * :--------------------------------------------------|:------|:---------------------------
17259  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR | 0x0 | counter < half max
17260  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR | 0x1 | counter >= half max or max
17261  *
17262  * Field Access Macros:
17263  *
17264  */
17265 /*
17266  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
17267  *
17268  * counter < half max
17269  */
17270 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR 0x0
17271 /*
17272  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
17273  *
17274  * counter >= half max or max
17275  */
17276 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR 0x1
17277 
17278 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
17279 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB 5
17280 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
17281 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB 5
17282 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
17283 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH 1
17284 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
17285 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK 0x00000020
17286 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
17287 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK 0xffffffdf
17288 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
17289 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET 0x0
17290 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM field value from a register. */
17291 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET(value) (((value) & 0x00000020) >> 5)
17292 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value suitable for setting the register. */
17293 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET(value) (((value) << 5) & 0x00000020)
17294 
17295 /*
17296  * Field : MMC Receive Alignment Error Frame Counter Interrupt Mask - rxalgnerfim
17297  *
17298  * Setting this bit masks the interrupt when the rxalignmenterror counter reaches
17299  * half of the maximum value or the maximum value.
17300  *
17301  * Field Enumeration Values:
17302  *
17303  * Enum | Value | Description
17304  * :---------------------------------------------------|:------|:---------------------------
17305  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR | 0x0 | counter < half max
17306  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR | 0x1 | counter >= half max or max
17307  *
17308  * Field Access Macros:
17309  *
17310  */
17311 /*
17312  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
17313  *
17314  * counter < half max
17315  */
17316 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR 0x0
17317 /*
17318  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
17319  *
17320  * counter >= half max or max
17321  */
17322 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR 0x1
17323 
17324 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
17325 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB 6
17326 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
17327 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB 6
17328 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
17329 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH 1
17330 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
17331 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK 0x00000040
17332 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
17333 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK 0xffffffbf
17334 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
17335 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET 0x0
17336 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM field value from a register. */
17337 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET(value) (((value) & 0x00000040) >> 6)
17338 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value suitable for setting the register. */
17339 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET(value) (((value) << 6) & 0x00000040)
17340 
17341 /*
17342  * Field : MMC Receive Runt Frame Counter Interrupt Mask - rxruntfim
17343  *
17344  * Setting this bit masks the interrupt when the rxrunterror counter reaches half
17345  * of the maximum value or the maximum value.
17346  *
17347  * Field Enumeration Values:
17348  *
17349  * Enum | Value | Description
17350  * :-------------------------------------------------|:------|:---------------------------
17351  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR | 0x0 | counter < half max
17352  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR | 0x1 | counter >= half max or max
17353  *
17354  * Field Access Macros:
17355  *
17356  */
17357 /*
17358  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
17359  *
17360  * counter < half max
17361  */
17362 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR 0x0
17363 /*
17364  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
17365  *
17366  * counter >= half max or max
17367  */
17368 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR 0x1
17369 
17370 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
17371 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB 7
17372 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
17373 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB 7
17374 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
17375 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH 1
17376 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
17377 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK 0x00000080
17378 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
17379 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK 0xffffff7f
17380 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
17381 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET 0x0
17382 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM field value from a register. */
17383 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET(value) (((value) & 0x00000080) >> 7)
17384 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value suitable for setting the register. */
17385 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET(value) (((value) << 7) & 0x00000080)
17386 
17387 /*
17388  * Field : MMC Receive Jabber Error Frame Counter Interrupt Mask - rxjaberfim
17389  *
17390  * Setting this bit masks the interrupt when the rxjabbererror counter reaches half
17391  * of the maximum value or the maximum value.
17392  *
17393  * Field Enumeration Values:
17394  *
17395  * Enum | Value | Description
17396  * :--------------------------------------------------|:------|:---------------------------
17397  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR | 0x0 | counter < half max
17398  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR | 0x1 | counter >= half max or max
17399  *
17400  * Field Access Macros:
17401  *
17402  */
17403 /*
17404  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
17405  *
17406  * counter < half max
17407  */
17408 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR 0x0
17409 /*
17410  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
17411  *
17412  * counter >= half max or max
17413  */
17414 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR 0x1
17415 
17416 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
17417 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB 8
17418 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
17419 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB 8
17420 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
17421 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH 1
17422 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
17423 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK 0x00000100
17424 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
17425 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK 0xfffffeff
17426 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
17427 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET 0x0
17428 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM field value from a register. */
17429 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET(value) (((value) & 0x00000100) >> 8)
17430 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value suitable for setting the register. */
17431 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET(value) (((value) << 8) & 0x00000100)
17432 
17433 /*
17434  * Field : MMC Receive Undersize Good Frame Counter Interrupt Mask - rxusizegfim
17435  *
17436  * Setting this bit masks the interrupt when the rxundersize_g counter reaches half
17437  * of the maximum value or the maximum value.
17438  *
17439  * Field Enumeration Values:
17440  *
17441  * Enum | Value | Description
17442  * :---------------------------------------------------|:------|:---------------------------
17443  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max
17444  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max
17445  *
17446  * Field Access Macros:
17447  *
17448  */
17449 /*
17450  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
17451  *
17452  * counter < half max
17453  */
17454 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR 0x0
17455 /*
17456  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
17457  *
17458  * counter >= half max or max
17459  */
17460 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR 0x1
17461 
17462 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
17463 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB 9
17464 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
17465 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB 9
17466 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
17467 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH 1
17468 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
17469 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK 0x00000200
17470 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
17471 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK 0xfffffdff
17472 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
17473 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET 0x0
17474 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM field value from a register. */
17475 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET(value) (((value) & 0x00000200) >> 9)
17476 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value suitable for setting the register. */
17477 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET(value) (((value) << 9) & 0x00000200)
17478 
17479 /*
17480  * Field : MMC Receive Oversize Good Frame Counter Interrupt Mask - rxosizegfim
17481  *
17482  * Setting this bit masks the interrupt when the rxoversize_g counter reaches half
17483  * of the maximum value or the maximum value.
17484  *
17485  * Field Enumeration Values:
17486  *
17487  * Enum | Value | Description
17488  * :---------------------------------------------------|:------|:---------------------------
17489  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max
17490  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max
17491  *
17492  * Field Access Macros:
17493  *
17494  */
17495 /*
17496  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
17497  *
17498  * counter < half max
17499  */
17500 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0
17501 /*
17502  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
17503  *
17504  * counter >= half max or max
17505  */
17506 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1
17507 
17508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
17509 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB 10
17510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
17511 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB 10
17512 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
17513 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH 1
17514 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
17515 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK 0x00000400
17516 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
17517 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfffffbff
17518 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
17519 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET 0x0
17520 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM field value from a register. */
17521 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x00000400) >> 10)
17522 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
17523 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 10) & 0x00000400)
17524 
17525 /*
17526  * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - rx64octgbfim
17527  *
17528  * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half
17529  * of the maximum value or the maximum value.
17530  *
17531  * Field Enumeration Values:
17532  *
17533  * Enum | Value | Description
17534  * :----------------------------------------------------|:------|:---------------------------
17535  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17536  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17537  *
17538  * Field Access Macros:
17539  *
17540  */
17541 /*
17542  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
17543  *
17544  * counter < half max
17545  */
17546 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
17547 /*
17548  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
17549  *
17550  * counter >= half max or max
17551  */
17552 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1
17553 
17554 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
17555 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB 11
17556 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
17557 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB 11
17558 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
17559 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH 1
17560 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
17561 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000800
17562 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
17563 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK 0xfffff7ff
17564 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
17565 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET 0x0
17566 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM field value from a register. */
17567 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000800) >> 11)
17568 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
17569 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 11) & 0x00000800)
17570 
17571 /*
17572  * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - rx65t127octgbfim
17573  *
17574  * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches
17575  * half of the maximum value or the maximum value.
17576  *
17577  * Field Enumeration Values:
17578  *
17579  * Enum | Value | Description
17580  * :--------------------------------------------------------|:------|:---------------------------
17581  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17582  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17583  *
17584  * Field Access Macros:
17585  *
17586  */
17587 /*
17588  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
17589  *
17590  * counter < half max
17591  */
17592 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
17593 /*
17594  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
17595  *
17596  * counter >= half max or max
17597  */
17598 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1
17599 
17600 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
17601 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB 12
17602 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
17603 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB 12
17604 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
17605 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH 1
17606 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
17607 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00001000
17608 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
17609 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffefff
17610 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
17611 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET 0x0
17612 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM field value from a register. */
17613 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00001000) >> 12)
17614 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
17615 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 12) & 0x00001000)
17616 
17617 /*
17618  * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - rx128t255octgbfim
17619  *
17620  * Setting this bit masks the interrupt when the rx128to255octets_gb counter
17621  * reaches half of the maximum value or the maximum value.
17622  *
17623  * Field Enumeration Values:
17624  *
17625  * Enum | Value | Description
17626  * :---------------------------------------------------------|:------|:---------------------------
17627  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17628  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17629  *
17630  * Field Access Macros:
17631  *
17632  */
17633 /*
17634  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
17635  *
17636  * counter < half max
17637  */
17638 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0
17639 /*
17640  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
17641  *
17642  * counter >= half max or max
17643  */
17644 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1
17645 
17646 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
17647 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB 13
17648 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
17649 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB 13
17650 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
17651 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH 1
17652 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
17653 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00002000
17654 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
17655 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffdfff
17656 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
17657 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET 0x0
17658 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM field value from a register. */
17659 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00002000) >> 13)
17660 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
17661 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 13) & 0x00002000)
17662 
17663 /*
17664  * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - rx256t511octgbfim
17665  *
17666  * Setting this bit masks the interrupt when the rx256to511octets_gb counter
17667  * reaches half of the maximum value or the maximum value.
17668  *
17669  * Field Enumeration Values:
17670  *
17671  * Enum | Value | Description
17672  * :---------------------------------------------------------|:------|:---------------------------
17673  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17674  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17675  *
17676  * Field Access Macros:
17677  *
17678  */
17679 /*
17680  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
17681  *
17682  * counter < half max
17683  */
17684 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0
17685 /*
17686  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
17687  *
17688  * counter >= half max or max
17689  */
17690 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1
17691 
17692 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
17693 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB 14
17694 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
17695 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB 14
17696 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
17697 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH 1
17698 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
17699 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00004000
17700 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
17701 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffbfff
17702 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
17703 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET 0x0
17704 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM field value from a register. */
17705 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00004000) >> 14)
17706 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
17707 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 14) & 0x00004000)
17708 
17709 /*
17710  * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - rx512t1023octgbfim
17711  *
17712  * Setting this bit masks the interrupt when the rx512to1023octets_gb counter
17713  * reaches half of the maximum value or the maximum value.
17714  *
17715  * Field Enumeration Values:
17716  *
17717  * Enum | Value | Description
17718  * :----------------------------------------------------------|:------|:---------------------------
17719  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17720  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17721  *
17722  * Field Access Macros:
17723  *
17724  */
17725 /*
17726  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
17727  *
17728  * counter < half max
17729  */
17730 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0
17731 /*
17732  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
17733  *
17734  * counter >= half max or max
17735  */
17736 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1
17737 
17738 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
17739 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB 15
17740 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
17741 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB 15
17742 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
17743 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH 1
17744 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
17745 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00008000
17746 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
17747 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xffff7fff
17748 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
17749 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET 0x0
17750 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM field value from a register. */
17751 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00008000) >> 15)
17752 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
17753 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 15) & 0x00008000)
17754 
17755 /*
17756  * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - rx1024tmaxoctgbfim
17757  *
17758  * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter
17759  * reaches half of the maximum value or the maximum value.
17760  *
17761  * Field Enumeration Values:
17762  *
17763  * Enum | Value | Description
17764  * :----------------------------------------------------------|:------|:---------------------------
17765  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
17766  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
17767  *
17768  * Field Access Macros:
17769  *
17770  */
17771 /*
17772  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
17773  *
17774  * counter < half max
17775  */
17776 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0
17777 /*
17778  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
17779  *
17780  * counter >= half max or max
17781  */
17782 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1
17783 
17784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
17785 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB 16
17786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
17787 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB 16
17788 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
17789 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1
17790 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
17791 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00010000
17792 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
17793 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffeffff
17794 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
17795 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0
17796 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
17797 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00010000) >> 16)
17798 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
17799 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 16) & 0x00010000)
17800 
17801 /*
17802  * Field : MMC Receive Unicast Good Frame Counter Interrupt Mask - rxucgfim
17803  *
17804  * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches
17805  * half of the maximum value or the maximum value.
17806  *
17807  * Field Enumeration Values:
17808  *
17809  * Enum | Value | Description
17810  * :------------------------------------------------|:------|:---------------------------
17811  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR | 0x0 | counter < half max
17812  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR | 0x1 | counter >= half max or max
17813  *
17814  * Field Access Macros:
17815  *
17816  */
17817 /*
17818  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
17819  *
17820  * counter < half max
17821  */
17822 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0
17823 /*
17824  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
17825  *
17826  * counter >= half max or max
17827  */
17828 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR 0x1
17829 
17830 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
17831 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB 17
17832 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
17833 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB 17
17834 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
17835 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH 1
17836 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
17837 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK 0x00020000
17838 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
17839 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK 0xfffdffff
17840 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
17841 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET 0x0
17842 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM field value from a register. */
17843 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET(value) (((value) & 0x00020000) >> 17)
17844 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value suitable for setting the register. */
17845 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET(value) (((value) << 17) & 0x00020000)
17846 
17847 /*
17848  * Field : MMC Receive Length Error Frame Counter Interrupt Mask - rxlenerfim
17849  *
17850  * Setting this bit masks the interrupt when the rxlengtherror counter reaches half
17851  * of the maximum value or the maximum value.
17852  *
17853  * Field Enumeration Values:
17854  *
17855  * Enum | Value | Description
17856  * :--------------------------------------------------|:------|:---------------------------
17857  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR | 0x0 | counter < half max
17858  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR | 0x1 | counter >= half max or max
17859  *
17860  * Field Access Macros:
17861  *
17862  */
17863 /*
17864  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
17865  *
17866  * counter < half max
17867  */
17868 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR 0x0
17869 /*
17870  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
17871  *
17872  * counter >= half max or max
17873  */
17874 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR 0x1
17875 
17876 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
17877 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB 18
17878 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
17879 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB 18
17880 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
17881 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH 1
17882 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
17883 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK 0x00040000
17884 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
17885 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK 0xfffbffff
17886 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
17887 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET 0x0
17888 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM field value from a register. */
17889 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET(value) (((value) & 0x00040000) >> 18)
17890 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value suitable for setting the register. */
17891 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET(value) (((value) << 18) & 0x00040000)
17892 
17893 /*
17894  * Field : MMC Receive Out Of Range Error Frame Counter Interrupt Mask - rxorangefim
17895  *
17896  * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches
17897  * half of the maximum value or the maximum value.
17898  *
17899  * Field Enumeration Values:
17900  *
17901  * Enum | Value | Description
17902  * :---------------------------------------------------|:------|:---------------------------
17903  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR | 0x0 | counter < half max
17904  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR | 0x1 | counter >= half max or max
17905  *
17906  * Field Access Macros:
17907  *
17908  */
17909 /*
17910  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
17911  *
17912  * counter < half max
17913  */
17914 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR 0x0
17915 /*
17916  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
17917  *
17918  * counter >= half max or max
17919  */
17920 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR 0x1
17921 
17922 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
17923 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB 19
17924 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
17925 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB 19
17926 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
17927 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH 1
17928 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
17929 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK 0x00080000
17930 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
17931 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK 0xfff7ffff
17932 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
17933 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET 0x0
17934 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM field value from a register. */
17935 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET(value) (((value) & 0x00080000) >> 19)
17936 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value suitable for setting the register. */
17937 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET(value) (((value) << 19) & 0x00080000)
17938 
17939 /*
17940  * Field : MMC Receive Pause Frame Counter Interrupt Mask - rxpausfim
17941  *
17942  * Setting this bit masks the interrupt when the rxpauseframes counter reaches half
17943  * of the maximum value or the maximum value.
17944  *
17945  * Field Enumeration Values:
17946  *
17947  * Enum | Value | Description
17948  * :-------------------------------------------------|:------|:---------------------------
17949  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 | counter < half max
17950  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 | counter >= half max or max
17951  *
17952  * Field Access Macros:
17953  *
17954  */
17955 /*
17956  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
17957  *
17958  * counter < half max
17959  */
17960 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0
17961 /*
17962  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
17963  *
17964  * counter >= half max or max
17965  */
17966 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR 0x1
17967 
17968 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
17969 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB 20
17970 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
17971 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB 20
17972 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
17973 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH 1
17974 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
17975 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK 0x00100000
17976 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
17977 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK 0xffefffff
17978 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
17979 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET 0x0
17980 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM field value from a register. */
17981 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00100000) >> 20)
17982 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
17983 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET(value) (((value) << 20) & 0x00100000)
17984 
17985 /*
17986  * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Mask - rxfovfim
17987  *
17988  * Setting this bit masks the interrupt when the rxfifooverflow counter reaches
17989  * half of the maximum value or the maximum value.
17990  *
17991  * Field Enumeration Values:
17992  *
17993  * Enum | Value | Description
17994  * :------------------------------------------------|:------|:---------------------------
17995  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR | 0x0 | counter < half max
17996  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR | 0x1 | counter >= half max or max
17997  *
17998  * Field Access Macros:
17999  *
18000  */
18001 /*
18002  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
18003  *
18004  * counter < half max
18005  */
18006 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0
18007 /*
18008  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
18009  *
18010  * counter >= half max or max
18011  */
18012 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR 0x1
18013 
18014 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
18015 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB 21
18016 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
18017 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB 21
18018 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
18019 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH 1
18020 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
18021 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK 0x00200000
18022 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
18023 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK 0xffdfffff
18024 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
18025 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET 0x0
18026 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM field value from a register. */
18027 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET(value) (((value) & 0x00200000) >> 21)
18028 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value suitable for setting the register. */
18029 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET(value) (((value) << 21) & 0x00200000)
18030 
18031 /*
18032  * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - rxvlangbfim
18033  *
18034  * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches
18035  * half of the maximum value or the maximum value.
18036  *
18037  * Field Enumeration Values:
18038  *
18039  * Enum | Value | Description
18040  * :---------------------------------------------------|:------|:---------------------------
18041  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18042  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18043  *
18044  * Field Access Macros:
18045  *
18046  */
18047 /*
18048  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
18049  *
18050  * counter < half max
18051  */
18052 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR 0x0
18053 /*
18054  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
18055  *
18056  * counter >= half max or max
18057  */
18058 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR 0x1
18059 
18060 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
18061 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB 22
18062 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
18063 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB 22
18064 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
18065 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH 1
18066 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
18067 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK 0x00400000
18068 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
18069 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK 0xffbfffff
18070 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
18071 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET 0x0
18072 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM field value from a register. */
18073 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET(value) (((value) & 0x00400000) >> 22)
18074 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value suitable for setting the register. */
18075 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET(value) (((value) << 22) & 0x00400000)
18076 
18077 /*
18078  * Field : MMC Receive Watchdog Error Frame Counter Interrupt Mask - rxwdogfim
18079  *
18080  * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of
18081  * the maximum value or the maximum value.
18082  *
18083  * Field Enumeration Values:
18084  *
18085  * Enum | Value | Description
18086  * :-------------------------------------------------|:------|:---------------------------
18087  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR | 0x0 | counter < half max
18088  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR | 0x1 | counter >= half max or max
18089  *
18090  * Field Access Macros:
18091  *
18092  */
18093 /*
18094  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
18095  *
18096  * counter < half max
18097  */
18098 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR 0x0
18099 /*
18100  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
18101  *
18102  * counter >= half max or max
18103  */
18104 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR 0x1
18105 
18106 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
18107 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB 23
18108 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
18109 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB 23
18110 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
18111 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH 1
18112 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
18113 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK 0x00800000
18114 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
18115 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK 0xff7fffff
18116 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
18117 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET 0x0
18118 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM field value from a register. */
18119 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET(value) (((value) & 0x00800000) >> 23)
18120 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value suitable for setting the register. */
18121 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET(value) (((value) << 23) & 0x00800000)
18122 
18123 /*
18124  * Field : MMC Receive Error Frame Counter Interrupt Mask - rxrcverrfim
18125  *
18126  * Setting this bit masks the interrupt when the rxrcverror error counter reaches
18127  * half the maximum value, and also when it reaches the maximum value.
18128  *
18129  * Field Enumeration Values:
18130  *
18131  * Enum | Value | Description
18132  * :---------------------------------------------------|:------|:---------------------------
18133  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR | 0x0 | counter < half max
18134  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR | 0x1 | counter >= half max or max
18135  *
18136  * Field Access Macros:
18137  *
18138  */
18139 /*
18140  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
18141  *
18142  * counter < half max
18143  */
18144 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR 0x0
18145 /*
18146  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
18147  *
18148  * counter >= half max or max
18149  */
18150 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR 0x1
18151 
18152 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
18153 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB 24
18154 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
18155 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB 24
18156 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
18157 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH 1
18158 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
18159 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK 0x01000000
18160 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
18161 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK 0xfeffffff
18162 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
18163 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET 0x0
18164 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM field value from a register. */
18165 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET(value) (((value) & 0x01000000) >> 24)
18166 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value suitable for setting the register. */
18167 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET(value) (((value) << 24) & 0x01000000)
18168 
18169 /*
18170  * Field : MMC Receive Control Frame Counter Interrupt Mask - rxctrlfim
18171  *
18172  * Setting this bit masks the interrupt when the rxctrlframes counter reaches half
18173  * the maximum value, and also when it reaches the maximum value.
18174  *
18175  * Field Enumeration Values:
18176  *
18177  * Enum | Value | Description
18178  * :------------------------------------------------|:------|:---------------------------
18179  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR | 0x0 | counter < half max
18180  * ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR | 0x1 | counter >= half max or max
18181  *
18182  * Field Access Macros:
18183  *
18184  */
18185 /*
18186  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
18187  *
18188  * counter < half max
18189  */
18190 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0
18191 /*
18192  * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
18193  *
18194  * counter >= half max or max
18195  */
18196 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR 0x1
18197 
18198 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
18199 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB 25
18200 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
18201 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB 25
18202 /* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
18203 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH 1
18204 /* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
18205 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK 0x02000000
18206 /* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
18207 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK 0xfdffffff
18208 /* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
18209 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET 0x0
18210 /* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM field value from a register. */
18211 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET(value) (((value) & 0x02000000) >> 25)
18212 /* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value suitable for setting the register. */
18213 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET(value) (((value) << 25) & 0x02000000)
18214 
18215 #ifndef __ASSEMBLY__
18216 /*
18217  * WARNING: The C register and register group struct declarations are provided for
18218  * convenience and illustrative purposes. They should, however, be used with
18219  * caution as the C language standard provides no guarantees about the alignment or
18220  * atomicity of device memory accesses. The recommended practice for writing
18221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18222  * alt_write_word() functions.
18223  *
18224  * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK.
18225  */
18226 struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s
18227 {
18228  uint32_t rxgbfrmim : 1; /* MMC Receive Good Bad Frame Counter Interrupt Mask */
18229  uint32_t rxgboctim : 1; /* MMC Receive Good Bad Octet Counter Interrupt Mask */
18230  uint32_t rxgoctim : 1; /* MMC Receive Good Octet Counter Interrupt Mask */
18231  uint32_t rxbcgfim : 1; /* MMC Receive Broadcast Good Frame Counter Interrupt Mask */
18232  uint32_t rxmcgfim : 1; /* MMC Receive Multicast Good Frame Counter Interrupt Mask */
18233  uint32_t rxcrcerfim : 1; /* MMC Receive CRC Error Frame Counter Interrupt Mask */
18234  uint32_t rxalgnerfim : 1; /* MMC Receive Alignment Error Frame Counter Interrupt Mask */
18235  uint32_t rxruntfim : 1; /* MMC Receive Runt Frame Counter Interrupt Mask */
18236  uint32_t rxjaberfim : 1; /* MMC Receive Jabber Error Frame Counter Interrupt Mask */
18237  uint32_t rxusizegfim : 1; /* MMC Receive Undersize Good Frame Counter Interrupt Mask */
18238  uint32_t rxosizegfim : 1; /* MMC Receive Oversize Good Frame Counter Interrupt Mask */
18239  uint32_t rx64octgbfim : 1; /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask */
18240  uint32_t rx65t127octgbfim : 1; /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */
18241  uint32_t rx128t255octgbfim : 1; /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */
18242  uint32_t rx256t511octgbfim : 1; /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */
18243  uint32_t rx512t1023octgbfim : 1; /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */
18244  uint32_t rx1024tmaxoctgbfim : 1; /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */
18245  uint32_t rxucgfim : 1; /* MMC Receive Unicast Good Frame Counter Interrupt Mask */
18246  uint32_t rxlenerfim : 1; /* MMC Receive Length Error Frame Counter Interrupt Mask */
18247  uint32_t rxorangefim : 1; /* MMC Receive Out Of Range Error Frame Counter Interrupt Mask */
18248  uint32_t rxpausfim : 1; /* MMC Receive Pause Frame Counter Interrupt Mask */
18249  uint32_t rxfovfim : 1; /* MMC Receive FIFO Overflow Frame Counter Interrupt Mask */
18250  uint32_t rxvlangbfim : 1; /* MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */
18251  uint32_t rxwdogfim : 1; /* MMC Receive Watchdog Error Frame Counter Interrupt Mask */
18252  uint32_t rxrcverrfim : 1; /* MMC Receive Error Frame Counter Interrupt Mask */
18253  uint32_t rxctrlfim : 1; /* MMC Receive Control Frame Counter Interrupt Mask */
18254  uint32_t : 6; /* *UNDEFINED* */
18255 };
18256 
18257 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK. */
18258 typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_RX_INT_MSK_t;
18259 #endif /* __ASSEMBLY__ */
18260 
18261 /* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register from the beginning of the component. */
18262 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST 0x10c
18263 /* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register. */
18264 #define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST))
18265 
18266 /*
18267  * Register : Register 68 (MMC Transmit Interrupt Mask Register) - MMC_Transmit_Interrupt_Mask
18268  *
18269  * The MMC Transmit Interrupt Mask register maintains the masks for the interrupts
18270  * generated when the transmit statistic counters reach half of their maximum value
18271  * or maximum value. This register is 32-bits wide.
18272  *
18273  * Register Layout
18274  *
18275  * Bits | Access | Reset | Description
18276  * :--------|:-------|:------|:-------------------------------------------------------------------------
18277  * [0] | RW | 0x0 | MMC Transmit Good Bad Octet Counter Interrupt Mask
18278  * [1] | RW | 0x0 | MMC Transmit Good Bad Frame Counter Interrupt Mask
18279  * [2] | RW | 0x0 | MMC Transmit Broadcast Good Frame Counter Interrupt Mask
18280  * [3] | RW | 0x0 | MMC Transmit Multicast Good Frame Counter Interrupt Mask
18281  * [4] | RW | 0x0 | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
18282  * [5] | RW | 0x0 | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
18283  * [6] | RW | 0x0 | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
18284  * [7] | RW | 0x0 | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
18285  * [8] | RW | 0x0 | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
18286  * [9] | RW | 0x0 | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
18287  * [10] | RW | 0x0 | MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask
18288  * [11] | RW | 0x0 | MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
18289  * [12] | RW | 0x0 | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
18290  * [13] | RW | 0x0 | MMC Transmit Underflow Error Frame Counter Interrupt Mask
18291  * [14] | RW | 0x0 | MMC Transmit Single Collision Good Frame Counter Interrupt Mask
18292  * [15] | RW | 0x0 | MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
18293  * [16] | RW | 0x0 | MMC Transmit Deferred Frame Counter Interrupt Mask
18294  * [17] | RW | 0x0 | MMC Transmit Late Collision Frame Counter Interrupt Mask
18295  * [18] | RW | 0x0 | MMC Transmit Excessive Collision Frame Counter Interrupt Mask
18296  * [19] | RW | 0x0 | MMC Transmit Carrier Error Frame Counter Interrupt Mask
18297  * [20] | RW | 0x0 | MMC Transmit Good Octet Counter Interrupt Mask
18298  * [21] | RW | 0x0 | MMC Transmit Good Frame Counter Interrupt Mask
18299  * [22] | RW | 0x0 | MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
18300  * [23] | RW | 0x0 | MMC Transmit Pause Frame Counter Interrupt Mask
18301  * [24] | RW | 0x0 | MMC Transmit VLAN Good Frame Counter Interrupt Mask
18302  * [25] | RW | 0x0 | MMC Transmit Oversize Good Frame Counter Interrupt Mask
18303  * [31:26] | ??? | 0x0 | *UNDEFINED*
18304  *
18305  */
18306 /*
18307  * Field : MMC Transmit Good Bad Octet Counter Interrupt Mask - txgboctim
18308  *
18309  * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches
18310  * half of the maximum value or the maximum value.
18311  *
18312  * Field Enumeration Values:
18313  *
18314  * Enum | Value | Description
18315  * :-------------------------------------------------|:------|:---------------------------
18316  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 | counter < half max
18317  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 | counter >= half max or max
18318  *
18319  * Field Access Macros:
18320  *
18321  */
18322 /*
18323  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
18324  *
18325  * counter < half max
18326  */
18327 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0
18328 /*
18329  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
18330  *
18331  * counter >= half max or max
18332  */
18333 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR 0x1
18334 
18335 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
18336 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB 0
18337 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
18338 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB 0
18339 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
18340 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH 1
18341 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
18342 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK 0x00000001
18343 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
18344 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffe
18345 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
18346 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET 0x0
18347 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM field value from a register. */
18348 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000001) >> 0)
18349 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
18350 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET(value) (((value) << 0) & 0x00000001)
18351 
18352 /*
18353  * Field : MMC Transmit Good Bad Frame Counter Interrupt Mask - txgbfrmim
18354  *
18355  * Setting this bit masks the interrupt when the txframecount_gb counter reaches
18356  * half of the maximum value or the maximum value.
18357  *
18358  * Field Enumeration Values:
18359  *
18360  * Enum | Value | Description
18361  * :-------------------------------------------------|:------|:---------------------------
18362  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 | counter < half max
18363  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 | counter >= half max or max
18364  *
18365  * Field Access Macros:
18366  *
18367  */
18368 /*
18369  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
18370  *
18371  * counter < half max
18372  */
18373 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0
18374 /*
18375  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
18376  *
18377  * counter >= half max or max
18378  */
18379 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR 0x1
18380 
18381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
18382 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB 1
18383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
18384 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB 1
18385 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
18386 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH 1
18387 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
18388 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK 0x00000002
18389 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
18390 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffd
18391 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
18392 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET 0x0
18393 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM field value from a register. */
18394 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000002) >> 1)
18395 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
18396 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET(value) (((value) << 1) & 0x00000002)
18397 
18398 /*
18399  * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Mask - txbcgfim
18400  *
18401  * Setting this bit masks the interrupt when the txbroadcastframes_g counter
18402  * reaches half of the maximum value or the maximum value.
18403  *
18404  * Field Enumeration Values:
18405  *
18406  * Enum | Value | Description
18407  * :------------------------------------------------|:------|:---------------------------
18408  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 | counter < half max
18409  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 | counter >= half max or max
18410  *
18411  * Field Access Macros:
18412  *
18413  */
18414 /*
18415  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
18416  *
18417  * counter < half max
18418  */
18419 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
18420 /*
18421  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
18422  *
18423  * counter >= half max or max
18424  */
18425 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR 0x1
18426 
18427 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
18428 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB 2
18429 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
18430 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB 2
18431 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
18432 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH 1
18433 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
18434 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK 0x00000004
18435 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
18436 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK 0xfffffffb
18437 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
18438 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET 0x0
18439 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM field value from a register. */
18440 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000004) >> 2)
18441 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value suitable for setting the register. */
18442 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET(value) (((value) << 2) & 0x00000004)
18443 
18444 /*
18445  * Field : MMC Transmit Multicast Good Frame Counter Interrupt Mask - txmcgfim
18446  *
18447  * Setting this bit masks the interrupt when the txmulticastframes_g counter
18448  * reaches half of the maximum value or the maximum value.
18449  *
18450  * Field Enumeration Values:
18451  *
18452  * Enum | Value | Description
18453  * :------------------------------------------------|:------|:---------------------------
18454  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 | counter < half max
18455  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 | counter >= half max or max
18456  *
18457  * Field Access Macros:
18458  *
18459  */
18460 /*
18461  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
18462  *
18463  * counter < half max
18464  */
18465 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
18466 /*
18467  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
18468  *
18469  * counter >= half max or max
18470  */
18471 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR 0x1
18472 
18473 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
18474 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB 3
18475 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
18476 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB 3
18477 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
18478 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH 1
18479 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
18480 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK 0x00000008
18481 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
18482 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK 0xfffffff7
18483 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
18484 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET 0x0
18485 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM field value from a register. */
18486 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000008) >> 3)
18487 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value suitable for setting the register. */
18488 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET(value) (((value) << 3) & 0x00000008)
18489 
18490 /*
18491  * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - tx64octgbfim
18492  *
18493  * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half
18494  * of the maximum value or the maximum value.
18495  *
18496  * Field Enumeration Values:
18497  *
18498  * Enum | Value | Description
18499  * :----------------------------------------------------|:------|:---------------------------
18500  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18501  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18502  *
18503  * Field Access Macros:
18504  *
18505  */
18506 /*
18507  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
18508  *
18509  * counter < half max
18510  */
18511 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
18512 /*
18513  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
18514  *
18515  * counter >= half max or max
18516  */
18517 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1
18518 
18519 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
18520 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB 4
18521 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
18522 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB 4
18523 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
18524 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH 1
18525 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
18526 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000010
18527 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
18528 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK 0xffffffef
18529 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
18530 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET 0x0
18531 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM field value from a register. */
18532 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000010) >> 4)
18533 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
18534 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 4) & 0x00000010)
18535 
18536 /*
18537  * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - tx65t127octgbfim
18538  *
18539  * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches
18540  * half of the maximum value or the maximum value.
18541  *
18542  * Field Enumeration Values:
18543  *
18544  * Enum | Value | Description
18545  * :--------------------------------------------------------|:------|:---------------------------
18546  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18547  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18548  *
18549  * Field Access Macros:
18550  *
18551  */
18552 /*
18553  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
18554  *
18555  * counter < half max
18556  */
18557 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
18558 /*
18559  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
18560  *
18561  * counter >= half max or max
18562  */
18563 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1
18564 
18565 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
18566 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB 5
18567 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
18568 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB 5
18569 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
18570 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH 1
18571 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
18572 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00000020
18573 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
18574 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffffdf
18575 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
18576 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET 0x0
18577 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM field value from a register. */
18578 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00000020) >> 5)
18579 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
18580 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 5) & 0x00000020)
18581 
18582 /*
18583  * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - tx128t255octgbfim
18584  *
18585  * Setting this bit masks the interrupt when the tx128to255octets_gb counter
18586  * reaches half of the maximum value or the maximum value.
18587  *
18588  * Field Enumeration Values:
18589  *
18590  * Enum | Value | Description
18591  * :---------------------------------------------------------|:------|:---------------------------
18592  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18593  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18594  *
18595  * Field Access Macros:
18596  *
18597  */
18598 /*
18599  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
18600  *
18601  * counter < half max
18602  */
18603 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0
18604 /*
18605  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
18606  *
18607  * counter >= half max or max
18608  */
18609 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1
18610 
18611 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
18612 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB 6
18613 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
18614 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB 6
18615 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
18616 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH 1
18617 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
18618 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00000040
18619 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
18620 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffffbf
18621 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
18622 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET 0x0
18623 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM field value from a register. */
18624 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00000040) >> 6)
18625 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
18626 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 6) & 0x00000040)
18627 
18628 /*
18629  * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - tx256t511octgbfim
18630  *
18631  * Setting this bit masks the interrupt when the tx256to511octets_gb counter
18632  * reaches half of the maximum value or the maximum value.
18633  *
18634  * Field Enumeration Values:
18635  *
18636  * Enum | Value | Description
18637  * :---------------------------------------------------------|:------|:---------------------------
18638  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18639  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18640  *
18641  * Field Access Macros:
18642  *
18643  */
18644 /*
18645  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
18646  *
18647  * counter < half max
18648  */
18649 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0
18650 /*
18651  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
18652  *
18653  * counter >= half max or max
18654  */
18655 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1
18656 
18657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
18658 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB 7
18659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
18660 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB 7
18661 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
18662 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH 1
18663 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
18664 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00000080
18665 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
18666 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffff7f
18667 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
18668 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET 0x0
18669 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM field value from a register. */
18670 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00000080) >> 7)
18671 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
18672 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 7) & 0x00000080)
18673 
18674 /*
18675  * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - tx512t1023octgbfim
18676  *
18677  * Setting this bit masks the interrupt when the tx512to1023octets_gb counter
18678  * reaches half of the maximum value or the maximum value.
18679  *
18680  * Field Enumeration Values:
18681  *
18682  * Enum | Value | Description
18683  * :----------------------------------------------------------|:------|:---------------------------
18684  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18685  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18686  *
18687  * Field Access Macros:
18688  *
18689  */
18690 /*
18691  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
18692  *
18693  * counter < half max
18694  */
18695 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0
18696 /*
18697  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
18698  *
18699  * counter >= half max or max
18700  */
18701 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1
18702 
18703 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
18704 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB 8
18705 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
18706 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB 8
18707 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
18708 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH 1
18709 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
18710 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00000100
18711 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
18712 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xfffffeff
18713 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
18714 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET 0x0
18715 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM field value from a register. */
18716 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00000100) >> 8)
18717 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
18718 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 8) & 0x00000100)
18719 
18720 /*
18721  * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - tx1024tmaxoctgbfim
18722  *
18723  * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter
18724  * reaches half of the maximum value or the maximum value.
18725  *
18726  * Field Enumeration Values:
18727  *
18728  * Enum | Value | Description
18729  * :----------------------------------------------------------|:------|:---------------------------
18730  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18731  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18732  *
18733  * Field Access Macros:
18734  *
18735  */
18736 /*
18737  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
18738  *
18739  * counter < half max
18740  */
18741 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0
18742 /*
18743  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
18744  *
18745  * counter >= half max or max
18746  */
18747 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1
18748 
18749 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
18750 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB 9
18751 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
18752 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB 9
18753 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
18754 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1
18755 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
18756 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00000200
18757 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
18758 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffffdff
18759 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
18760 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0
18761 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
18762 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00000200) >> 9)
18763 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
18764 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 9) & 0x00000200)
18765 
18766 /*
18767  * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - txucgbfim
18768  *
18769  * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches
18770  * half of the maximum value or the maximum value.
18771  *
18772  * Field Enumeration Values:
18773  *
18774  * Enum | Value | Description
18775  * :-------------------------------------------------|:------|:---------------------------
18776  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18777  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18778  *
18779  * Field Access Macros:
18780  *
18781  */
18782 /*
18783  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
18784  *
18785  * counter < half max
18786  */
18787 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR 0x0
18788 /*
18789  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
18790  *
18791  * counter >= half max or max
18792  */
18793 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR 0x1
18794 
18795 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
18796 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB 10
18797 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
18798 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB 10
18799 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
18800 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH 1
18801 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
18802 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK 0x00000400
18803 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
18804 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK 0xfffffbff
18805 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
18806 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET 0x0
18807 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM field value from a register. */
18808 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET(value) (((value) & 0x00000400) >> 10)
18809 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value suitable for setting the register. */
18810 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET(value) (((value) << 10) & 0x00000400)
18811 
18812 /*
18813  * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - txmcgbfim
18814  *
18815  * Setting this bit masks the interrupt when the txmulticastframes_gb counter
18816  * reaches half of the maximum value or the maximum value.
18817  *
18818  * Field Enumeration Values:
18819  *
18820  * Enum | Value | Description
18821  * :-------------------------------------------------|:------|:---------------------------
18822  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18823  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18824  *
18825  * Field Access Macros:
18826  *
18827  */
18828 /*
18829  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
18830  *
18831  * counter < half max
18832  */
18833 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR 0x0
18834 /*
18835  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
18836  *
18837  * counter >= half max or max
18838  */
18839 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR 0x1
18840 
18841 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
18842 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB 11
18843 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
18844 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB 11
18845 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
18846 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH 1
18847 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
18848 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK 0x00000800
18849 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
18850 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK 0xfffff7ff
18851 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
18852 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET 0x0
18853 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM field value from a register. */
18854 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET(value) (((value) & 0x00000800) >> 11)
18855 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value suitable for setting the register. */
18856 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET(value) (((value) << 11) & 0x00000800)
18857 
18858 /*
18859  * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - txbcgbfim
18860  *
18861  * Setting this bit masks the interrupt when the txbroadcastframes_gb counter
18862  * reaches half of the maximum value or the maximum value.
18863  *
18864  * Field Enumeration Values:
18865  *
18866  * Enum | Value | Description
18867  * :-------------------------------------------------|:------|:---------------------------
18868  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR | 0x0 | counter < half max
18869  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR | 0x1 | counter >= half max or max
18870  *
18871  * Field Access Macros:
18872  *
18873  */
18874 /*
18875  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
18876  *
18877  * counter < half max
18878  */
18879 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR 0x0
18880 /*
18881  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
18882  *
18883  * counter >= half max or max
18884  */
18885 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR 0x1
18886 
18887 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
18888 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB 12
18889 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
18890 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB 12
18891 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
18892 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH 1
18893 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
18894 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK 0x00001000
18895 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
18896 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK 0xffffefff
18897 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
18898 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET 0x0
18899 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM field value from a register. */
18900 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET(value) (((value) & 0x00001000) >> 12)
18901 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value suitable for setting the register. */
18902 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET(value) (((value) << 12) & 0x00001000)
18903 
18904 /*
18905  * Field : MMC Transmit Underflow Error Frame Counter Interrupt Mask - txuflowerfim
18906  *
18907  * Setting this bit masks the interrupt when the txunderflowerror counter reaches
18908  * half of the maximum value or the maximum value.
18909  *
18910  * Field Enumeration Values:
18911  *
18912  * Enum | Value | Description
18913  * :----------------------------------------------------|:------|:---------------------------
18914  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR | 0x0 | counter < half max
18915  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR | 0x1 | counter >= half max or max
18916  *
18917  * Field Access Macros:
18918  *
18919  */
18920 /*
18921  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
18922  *
18923  * counter < half max
18924  */
18925 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR 0x0
18926 /*
18927  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
18928  *
18929  * counter >= half max or max
18930  */
18931 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR 0x1
18932 
18933 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
18934 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB 13
18935 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
18936 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB 13
18937 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
18938 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH 1
18939 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
18940 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK 0x00002000
18941 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
18942 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK 0xffffdfff
18943 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
18944 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET 0x0
18945 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM field value from a register. */
18946 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET(value) (((value) & 0x00002000) >> 13)
18947 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value suitable for setting the register. */
18948 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET(value) (((value) << 13) & 0x00002000)
18949 
18950 /*
18951  * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Mask - txscolgfim
18952  *
18953  * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half
18954  * of the maximum value or the maximum value.
18955  *
18956  * Field Enumeration Values:
18957  *
18958  * Enum | Value | Description
18959  * :--------------------------------------------------|:------|:---------------------------
18960  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR | 0x0 | counter < half max
18961  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR | 0x1 | counter >= half max or max
18962  *
18963  * Field Access Macros:
18964  *
18965  */
18966 /*
18967  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
18968  *
18969  * counter < half max
18970  */
18971 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR 0x0
18972 /*
18973  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
18974  *
18975  * counter >= half max or max
18976  */
18977 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR 0x1
18978 
18979 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
18980 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB 14
18981 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
18982 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB 14
18983 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
18984 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH 1
18985 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
18986 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK 0x00004000
18987 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
18988 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK 0xffffbfff
18989 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
18990 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET 0x0
18991 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM field value from a register. */
18992 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET(value) (((value) & 0x00004000) >> 14)
18993 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value suitable for setting the register. */
18994 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET(value) (((value) << 14) & 0x00004000)
18995 
18996 /*
18997  * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - txmcolgfim
18998  *
18999  * Setting this bit masks the interrupt when the txmulticol_g counter reaches half
19000  * of the maximum value or the maximum value.
19001  *
19002  * Field Enumeration Values:
19003  *
19004  * Enum | Value | Description
19005  * :--------------------------------------------------|:------|:---------------------------
19006  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR | 0x0 | counter < half max
19007  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR | 0x1 | counter >= half max or max
19008  *
19009  * Field Access Macros:
19010  *
19011  */
19012 /*
19013  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
19014  *
19015  * counter < half max
19016  */
19017 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR 0x0
19018 /*
19019  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
19020  *
19021  * counter >= half max or max
19022  */
19023 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR 0x1
19024 
19025 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
19026 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB 15
19027 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
19028 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB 15
19029 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
19030 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH 1
19031 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
19032 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK 0x00008000
19033 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
19034 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK 0xffff7fff
19035 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
19036 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET 0x0
19037 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM field value from a register. */
19038 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET(value) (((value) & 0x00008000) >> 15)
19039 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value suitable for setting the register. */
19040 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET(value) (((value) << 15) & 0x00008000)
19041 
19042 /*
19043  * Field : MMC Transmit Deferred Frame Counter Interrupt Mask - txdeffim
19044  *
19045  * Setting this bit masks the interrupt when the txdeferred counter reaches half of
19046  * the maximum value or the maximum value.
19047  *
19048  * Field Enumeration Values:
19049  *
19050  * Enum | Value | Description
19051  * :------------------------------------------------|:------|:---------------------------
19052  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR | 0x0 | counter < half max
19053  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR | 0x1 | counter >= half max or max
19054  *
19055  * Field Access Macros:
19056  *
19057  */
19058 /*
19059  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
19060  *
19061  * counter < half max
19062  */
19063 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR 0x0
19064 /*
19065  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
19066  *
19067  * counter >= half max or max
19068  */
19069 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR 0x1
19070 
19071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
19072 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB 16
19073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
19074 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB 16
19075 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
19076 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH 1
19077 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
19078 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK 0x00010000
19079 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
19080 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK 0xfffeffff
19081 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
19082 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET 0x0
19083 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM field value from a register. */
19084 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET(value) (((value) & 0x00010000) >> 16)
19085 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value suitable for setting the register. */
19086 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET(value) (((value) << 16) & 0x00010000)
19087 
19088 /*
19089  * Field : MMC Transmit Late Collision Frame Counter Interrupt Mask - txlatcolfim
19090  *
19091  * Setting this bit masks the interrupt when the txlatecol counter reaches half of
19092  * the maximum value or the maximum value.
19093  *
19094  * Field Enumeration Values:
19095  *
19096  * Enum | Value | Description
19097  * :---------------------------------------------------|:------|:---------------------------
19098  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR | 0x0 | counter < half max
19099  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR | 0x1 | counter >= half max or max
19100  *
19101  * Field Access Macros:
19102  *
19103  */
19104 /*
19105  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
19106  *
19107  * counter < half max
19108  */
19109 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR 0x0
19110 /*
19111  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
19112  *
19113  * counter >= half max or max
19114  */
19115 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR 0x1
19116 
19117 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
19118 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB 17
19119 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
19120 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB 17
19121 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
19122 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH 1
19123 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
19124 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK 0x00020000
19125 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
19126 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK 0xfffdffff
19127 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
19128 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET 0x0
19129 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM field value from a register. */
19130 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET(value) (((value) & 0x00020000) >> 17)
19131 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value suitable for setting the register. */
19132 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET(value) (((value) << 17) & 0x00020000)
19133 
19134 /*
19135  * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Mask - txexcolfim
19136  *
19137  * Setting this bit masks the interrupt when the txexcesscol counter reaches half
19138  * of the maximum value or the maximum value.
19139  *
19140  * Field Enumeration Values:
19141  *
19142  * Enum | Value | Description
19143  * :--------------------------------------------------|:------|:---------------------------
19144  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR | 0x0 | counter < half max
19145  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR | 0x1 | counter >= half max or max
19146  *
19147  * Field Access Macros:
19148  *
19149  */
19150 /*
19151  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
19152  *
19153  * counter < half max
19154  */
19155 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR 0x0
19156 /*
19157  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
19158  *
19159  * counter >= half max or max
19160  */
19161 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR 0x1
19162 
19163 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
19164 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB 18
19165 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
19166 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB 18
19167 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
19168 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH 1
19169 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
19170 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK 0x00040000
19171 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
19172 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK 0xfffbffff
19173 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
19174 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET 0x0
19175 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM field value from a register. */
19176 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET(value) (((value) & 0x00040000) >> 18)
19177 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value suitable for setting the register. */
19178 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET(value) (((value) << 18) & 0x00040000)
19179 
19180 /*
19181  * Field : MMC Transmit Carrier Error Frame Counter Interrupt Mask - txcarerfim
19182  *
19183  * Setting this bit masks the interrupt when the txcarriererror counter reaches
19184  * half of the maximum value or the maximum value.
19185  *
19186  * Field Enumeration Values:
19187  *
19188  * Enum | Value | Description
19189  * :--------------------------------------------------|:------|:---------------------------
19190  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR | 0x0 | counter < half max
19191  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR | 0x1 | counter >= half max or max
19192  *
19193  * Field Access Macros:
19194  *
19195  */
19196 /*
19197  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
19198  *
19199  * counter < half max
19200  */
19201 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR 0x0
19202 /*
19203  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
19204  *
19205  * counter >= half max or max
19206  */
19207 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR 0x1
19208 
19209 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
19210 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB 19
19211 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
19212 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB 19
19213 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
19214 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH 1
19215 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
19216 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK 0x00080000
19217 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
19218 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK 0xfff7ffff
19219 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
19220 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET 0x0
19221 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM field value from a register. */
19222 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET(value) (((value) & 0x00080000) >> 19)
19223 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value suitable for setting the register. */
19224 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET(value) (((value) << 19) & 0x00080000)
19225 
19226 /*
19227  * Field : MMC Transmit Good Octet Counter Interrupt Mask - txgoctim
19228  *
19229  * Setting this bit masks the interrupt when the txoctetcount_g counter reaches
19230  * half of the maximum value or the maximum value.
19231  *
19232  * Field Enumeration Values:
19233  *
19234  * Enum | Value | Description
19235  * :------------------------------------------------|:------|:---------------------------
19236  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 | counter < half max
19237  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 | counter >= half max or max
19238  *
19239  * Field Access Macros:
19240  *
19241  */
19242 /*
19243  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
19244  *
19245  * counter < half max
19246  */
19247 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
19248 /*
19249  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
19250  *
19251  * counter >= half max or max
19252  */
19253 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR 0x1
19254 
19255 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
19256 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB 20
19257 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
19258 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB 20
19259 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
19260 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH 1
19261 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
19262 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK 0x00100000
19263 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
19264 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK 0xffefffff
19265 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
19266 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET 0x0
19267 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM field value from a register. */
19268 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00100000) >> 20)
19269 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value suitable for setting the register. */
19270 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET(value) (((value) << 20) & 0x00100000)
19271 
19272 /*
19273  * Field : MMC Transmit Good Frame Counter Interrupt Mask - txgfrmim
19274  *
19275  * Setting this bit masks the interrupt when the txframecount_g counter reaches
19276  * half of the maximum value or the maximum value.
19277  *
19278  * Field Enumeration Values:
19279  *
19280  * Enum | Value | Description
19281  * :------------------------------------------------|:------|:---------------------------
19282  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR | 0x0 | counter < half max
19283  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR | 0x1 | counter >= half max or max
19284  *
19285  * Field Access Macros:
19286  *
19287  */
19288 /*
19289  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
19290  *
19291  * counter < half max
19292  */
19293 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR 0x0
19294 /*
19295  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
19296  *
19297  * counter >= half max or max
19298  */
19299 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR 0x1
19300 
19301 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
19302 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB 21
19303 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
19304 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB 21
19305 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
19306 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH 1
19307 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
19308 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK 0x00200000
19309 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
19310 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK 0xffdfffff
19311 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
19312 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET 0x0
19313 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM field value from a register. */
19314 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET(value) (((value) & 0x00200000) >> 21)
19315 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value suitable for setting the register. */
19316 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET(value) (((value) << 21) & 0x00200000)
19317 
19318 /*
19319  * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - txexdeffim
19320  *
19321  * Setting this bit masks the interrupt when the txexcessdef counter reaches half
19322  * of the maximum value or the maximum value.
19323  *
19324  * Field Enumeration Values:
19325  *
19326  * Enum | Value | Description
19327  * :--------------------------------------------------|:------|:---------------------------
19328  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR | 0x0 | counter < half max
19329  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR | 0x1 | counter >= half max or max
19330  *
19331  * Field Access Macros:
19332  *
19333  */
19334 /*
19335  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
19336  *
19337  * counter < half max
19338  */
19339 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR 0x0
19340 /*
19341  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
19342  *
19343  * counter >= half max or max
19344  */
19345 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR 0x1
19346 
19347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
19348 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB 22
19349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
19350 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB 22
19351 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
19352 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH 1
19353 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
19354 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK 0x00400000
19355 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
19356 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK 0xffbfffff
19357 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
19358 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET 0x0
19359 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM field value from a register. */
19360 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET(value) (((value) & 0x00400000) >> 22)
19361 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value suitable for setting the register. */
19362 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET(value) (((value) << 22) & 0x00400000)
19363 
19364 /*
19365  * Field : MMC Transmit Pause Frame Counter Interrupt Mask - txpausfim
19366  *
19367  * Setting this bit masks the interrupt when the txpauseframes counter reaches half
19368  * of the maximum value or the maximum value.
19369  *
19370  * Field Enumeration Values:
19371  *
19372  * Enum | Value | Description
19373  * :-------------------------------------------------|:------|:---------------------------
19374  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 | counter < half max
19375  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 | counter >= half max or max
19376  *
19377  * Field Access Macros:
19378  *
19379  */
19380 /*
19381  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
19382  *
19383  * counter < half max
19384  */
19385 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0
19386 /*
19387  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
19388  *
19389  * counter >= half max or max
19390  */
19391 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR 0x1
19392 
19393 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
19394 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB 23
19395 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
19396 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB 23
19397 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
19398 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH 1
19399 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
19400 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK 0x00800000
19401 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
19402 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK 0xff7fffff
19403 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
19404 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET 0x0
19405 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM field value from a register. */
19406 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00800000) >> 23)
19407 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
19408 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET(value) (((value) << 23) & 0x00800000)
19409 
19410 /*
19411  * Field : MMC Transmit VLAN Good Frame Counter Interrupt Mask - txvlangfim
19412  *
19413  * Setting this bit masks the interrupt when the txvlanframes_g counter reaches
19414  * half of the maximum value or the maximum value.
19415  *
19416  * Field Enumeration Values:
19417  *
19418  * Enum | Value | Description
19419  * :--------------------------------------------------|:------|:---------------------------
19420  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR | 0x0 | counter < half max
19421  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR | 0x1 | counter >= half max or max
19422  *
19423  * Field Access Macros:
19424  *
19425  */
19426 /*
19427  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
19428  *
19429  * counter < half max
19430  */
19431 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR 0x0
19432 /*
19433  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
19434  *
19435  * counter >= half max or max
19436  */
19437 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR 0x1
19438 
19439 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
19440 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB 24
19441 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
19442 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB 24
19443 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
19444 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH 1
19445 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
19446 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK 0x01000000
19447 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
19448 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK 0xfeffffff
19449 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
19450 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET 0x0
19451 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM field value from a register. */
19452 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET(value) (((value) & 0x01000000) >> 24)
19453 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value suitable for setting the register. */
19454 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET(value) (((value) << 24) & 0x01000000)
19455 
19456 /*
19457  * Field : MMC Transmit Oversize Good Frame Counter Interrupt Mask - txosizegfim
19458  *
19459  * Setting this bit masks the interrupt when the txoversize_g counter reaches half
19460  * of the maximum value or the maximum value.
19461  *
19462  * Field Enumeration Values:
19463  *
19464  * Enum | Value | Description
19465  * :---------------------------------------------------|:------|:---------------------------
19466  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 | counter < half max
19467  * ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 | counter >= half max or max
19468  *
19469  * Field Access Macros:
19470  *
19471  */
19472 /*
19473  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
19474  *
19475  * counter < half max
19476  */
19477 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0
19478 /*
19479  * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
19480  *
19481  * counter >= half max or max
19482  */
19483 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1
19484 
19485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
19486 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB 25
19487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
19488 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB 25
19489 /* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
19490 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH 1
19491 /* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
19492 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK 0x02000000
19493 /* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
19494 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfdffffff
19495 /* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
19496 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET 0x0
19497 /* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM field value from a register. */
19498 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x02000000) >> 25)
19499 /* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
19500 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 25) & 0x02000000)
19501 
19502 #ifndef __ASSEMBLY__
19503 /*
19504  * WARNING: The C register and register group struct declarations are provided for
19505  * convenience and illustrative purposes. They should, however, be used with
19506  * caution as the C language standard provides no guarantees about the alignment or
19507  * atomicity of device memory accesses. The recommended practice for writing
19508  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19509  * alt_write_word() functions.
19510  *
19511  * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK.
19512  */
19513 struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s
19514 {
19515  uint32_t txgboctim : 1; /* MMC Transmit Good Bad Octet Counter Interrupt Mask */
19516  uint32_t txgbfrmim : 1; /* MMC Transmit Good Bad Frame Counter Interrupt Mask */
19517  uint32_t txbcgfim : 1; /* MMC Transmit Broadcast Good Frame Counter Interrupt Mask */
19518  uint32_t txmcgfim : 1; /* MMC Transmit Multicast Good Frame Counter Interrupt Mask */
19519  uint32_t tx64octgbfim : 1; /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask */
19520  uint32_t tx65t127octgbfim : 1; /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */
19521  uint32_t tx128t255octgbfim : 1; /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */
19522  uint32_t tx256t511octgbfim : 1; /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */
19523  uint32_t tx512t1023octgbfim : 1; /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */
19524  uint32_t tx1024tmaxoctgbfim : 1; /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */
19525  uint32_t txucgbfim : 1; /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask */
19526  uint32_t txmcgbfim : 1; /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask */
19527  uint32_t txbcgbfim : 1; /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask */
19528  uint32_t txuflowerfim : 1; /* MMC Transmit Underflow Error Frame Counter Interrupt Mask */
19529  uint32_t txscolgfim : 1; /* MMC Transmit Single Collision Good Frame Counter Interrupt Mask */
19530  uint32_t txmcolgfim : 1; /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask */
19531  uint32_t txdeffim : 1; /* MMC Transmit Deferred Frame Counter Interrupt Mask */
19532  uint32_t txlatcolfim : 1; /* MMC Transmit Late Collision Frame Counter Interrupt Mask */
19533  uint32_t txexcolfim : 1; /* MMC Transmit Excessive Collision Frame Counter Interrupt Mask */
19534  uint32_t txcarerfim : 1; /* MMC Transmit Carrier Error Frame Counter Interrupt Mask */
19535  uint32_t txgoctim : 1; /* MMC Transmit Good Octet Counter Interrupt Mask */
19536  uint32_t txgfrmim : 1; /* MMC Transmit Good Frame Counter Interrupt Mask */
19537  uint32_t txexdeffim : 1; /* MMC Transmit Excessive Deferral Frame Counter Interrupt Mask */
19538  uint32_t txpausfim : 1; /* MMC Transmit Pause Frame Counter Interrupt Mask */
19539  uint32_t txvlangfim : 1; /* MMC Transmit VLAN Good Frame Counter Interrupt Mask */
19540  uint32_t txosizegfim : 1; /* MMC Transmit Oversize Good Frame Counter Interrupt Mask */
19541  uint32_t : 6; /* *UNDEFINED* */
19542 };
19543 
19544 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK. */
19545 typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s ALT_EMAC_GMAC_MMC_TX_INT_MSK_t;
19546 #endif /* __ASSEMBLY__ */
19547 
19548 /* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register from the beginning of the component. */
19549 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST 0x110
19550 /* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register. */
19551 #define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST))
19552 
19553 /*
19554  * Register : Register 69 (txoctetcount_gb Register) - txoctetcount_gb
19555  *
19556  * Number of bytes transmitted, exclusive of preamble and retried bytes, in good
19557  * and bad frames
19558  *
19559  * Register Layout
19560  *
19561  * Bits | Access | Reset | Description
19562  * :-------|:-------|:------|:----------------
19563  * [31:0] | R | 0x0 | txoctetcount_gb
19564  *
19565  */
19566 /*
19567  * Field : txoctetcount_gb - cnt
19568  *
19569  * Number of bytes transmitted, exclusive of preamble and retried bytes, in good
19570  * and bad frames
19571  *
19572  * Field Access Macros:
19573  *
19574  */
19575 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
19576 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_LSB 0
19577 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
19578 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_MSB 31
19579 /* The width in bits of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
19580 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_WIDTH 32
19581 /* The mask used to set the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
19582 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff
19583 /* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
19584 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000
19585 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
19586 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_RESET 0x0
19587 /* Extracts the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT field value from a register. */
19588 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19589 /* Produces a ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
19590 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
19591 
19592 #ifndef __ASSEMBLY__
19593 /*
19594  * WARNING: The C register and register group struct declarations are provided for
19595  * convenience and illustrative purposes. They should, however, be used with
19596  * caution as the C language standard provides no guarantees about the alignment or
19597  * atomicity of device memory accesses. The recommended practice for writing
19598  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19599  * alt_write_word() functions.
19600  *
19601  * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB.
19602  */
19603 struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s
19604 {
19605  const uint32_t cnt : 32; /* txoctetcount_gb */
19606 };
19607 
19608 /* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB. */
19609 typedef volatile struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t;
19610 #endif /* __ASSEMBLY__ */
19611 
19612 /* The byte offset of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register from the beginning of the component. */
19613 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST 0x114
19614 /* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register. */
19615 #define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST))
19616 
19617 /*
19618  * Register : Register 70 (txframecount_gb Register) - txframecount_gb
19619  *
19620  * Number of good and bad frames transmitted, exclusive of retried frames
19621  *
19622  * Register Layout
19623  *
19624  * Bits | Access | Reset | Description
19625  * :-------|:-------|:------|:----------------
19626  * [31:0] | R | 0x0 | txframecount_gb
19627  *
19628  */
19629 /*
19630  * Field : txframecount_gb - cnt
19631  *
19632  * Number of good and bad frames transmitted, exclusive of retried frames
19633  *
19634  * Field Access Macros:
19635  *
19636  */
19637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
19638 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_LSB 0
19639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
19640 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_MSB 31
19641 /* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
19642 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_WIDTH 32
19643 /* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
19644 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff
19645 /* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
19646 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000
19647 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
19648 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_RESET 0x0
19649 /* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT field value from a register. */
19650 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19651 /* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
19652 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
19653 
19654 #ifndef __ASSEMBLY__
19655 /*
19656  * WARNING: The C register and register group struct declarations are provided for
19657  * convenience and illustrative purposes. They should, however, be used with
19658  * caution as the C language standard provides no guarantees about the alignment or
19659  * atomicity of device memory accesses. The recommended practice for writing
19660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19661  * alt_write_word() functions.
19662  *
19663  * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB.
19664  */
19665 struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s
19666 {
19667  const uint32_t cnt : 32; /* txframecount_gb */
19668 };
19669 
19670 /* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB. */
19671 typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s ALT_EMAC_GMAC_TXFRMCOUNT_GB_t;
19672 #endif /* __ASSEMBLY__ */
19673 
19674 /* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register from the beginning of the component. */
19675 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST 0x118
19676 /* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register. */
19677 #define ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST))
19678 
19679 /*
19680  * Register : Register 71 (txbroadcastframes_g Register) - txbroadcastframes_g
19681  *
19682  * Number of good broadcast frames transmitted
19683  *
19684  * Register Layout
19685  *
19686  * Bits | Access | Reset | Description
19687  * :-------|:-------|:------|:--------------------
19688  * [31:0] | R | 0x0 | txbroadcastframes_g
19689  *
19690  */
19691 /*
19692  * Field : txbroadcastframes_g - cnt
19693  *
19694  * Number of good broadcast frames transmitted
19695  *
19696  * Field Access Macros:
19697  *
19698  */
19699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
19700 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_LSB 0
19701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
19702 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_MSB 31
19703 /* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
19704 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_WIDTH 32
19705 /* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
19706 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET_MSK 0xffffffff
19707 /* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
19708 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_CLR_MSK 0x00000000
19709 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
19710 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_RESET 0x0
19711 /* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT field value from a register. */
19712 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19713 /* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value suitable for setting the register. */
19714 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
19715 
19716 #ifndef __ASSEMBLY__
19717 /*
19718  * WARNING: The C register and register group struct declarations are provided for
19719  * convenience and illustrative purposes. They should, however, be used with
19720  * caution as the C language standard provides no guarantees about the alignment or
19721  * atomicity of device memory accesses. The recommended practice for writing
19722  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19723  * alt_write_word() functions.
19724  *
19725  * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G.
19726  */
19727 struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s
19728 {
19729  const uint32_t cnt : 32; /* txbroadcastframes_g */
19730 };
19731 
19732 /* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G. */
19733 typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s ALT_EMAC_GMAC_TXBCASTFRMS_G_t;
19734 #endif /* __ASSEMBLY__ */
19735 
19736 /* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_G register from the beginning of the component. */
19737 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST 0x11c
19738 /* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register. */
19739 #define ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST))
19740 
19741 /*
19742  * Register : Register 72 (txmulticastframes_g Register) - txmulticastframes_g
19743  *
19744  * Number of good multicast frames transmitted
19745  *
19746  * Register Layout
19747  *
19748  * Bits | Access | Reset | Description
19749  * :-------|:-------|:------|:--------------------
19750  * [31:0] | R | 0x0 | txmulticastframes_g
19751  *
19752  */
19753 /*
19754  * Field : txmulticastframes_g - cnt
19755  *
19756  * Number of good multicast frames transmitted
19757  *
19758  * Field Access Macros:
19759  *
19760  */
19761 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
19762 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_LSB 0
19763 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
19764 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_MSB 31
19765 /* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
19766 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_WIDTH 32
19767 /* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
19768 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET_MSK 0xffffffff
19769 /* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
19770 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_CLR_MSK 0x00000000
19771 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
19772 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_RESET 0x0
19773 /* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT field value from a register. */
19774 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19775 /* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value suitable for setting the register. */
19776 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
19777 
19778 #ifndef __ASSEMBLY__
19779 /*
19780  * WARNING: The C register and register group struct declarations are provided for
19781  * convenience and illustrative purposes. They should, however, be used with
19782  * caution as the C language standard provides no guarantees about the alignment or
19783  * atomicity of device memory accesses. The recommended practice for writing
19784  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19785  * alt_write_word() functions.
19786  *
19787  * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G.
19788  */
19789 struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s
19790 {
19791  const uint32_t cnt : 32; /* txmulticastframes_g */
19792 };
19793 
19794 /* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G. */
19795 typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s ALT_EMAC_GMAC_TXMCASTFRMS_G_t;
19796 #endif /* __ASSEMBLY__ */
19797 
19798 /* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_G register from the beginning of the component. */
19799 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST 0x120
19800 /* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register. */
19801 #define ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST))
19802 
19803 /*
19804  * Register : Register 73 (tx64octets_gb Register) - tx64octets_gb
19805  *
19806  * Number of good and bad frames transmitted with length 64 bytes, exclusive of
19807  * preamble and retried frames
19808  *
19809  * Register Layout
19810  *
19811  * Bits | Access | Reset | Description
19812  * :-------|:-------|:------|:--------------
19813  * [31:0] | R | 0x0 | tx64octets_gb
19814  *
19815  */
19816 /*
19817  * Field : tx64octets_gb - cnt
19818  *
19819  * Number of good and bad frames transmitted with length 64 bytes, exclusive of
19820  * preamble and retried frames
19821  *
19822  * Field Access Macros:
19823  *
19824  */
19825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
19826 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_LSB 0
19827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
19828 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_MSB 31
19829 /* The width in bits of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
19830 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_WIDTH 32
19831 /* The mask used to set the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
19832 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET_MSK 0xffffffff
19833 /* The mask used to clear the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
19834 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_CLR_MSK 0x00000000
19835 /* The reset value of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
19836 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_RESET 0x0
19837 /* Extracts the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT field value from a register. */
19838 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19839 /* Produces a ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value suitable for setting the register. */
19840 #define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
19841 
19842 #ifndef __ASSEMBLY__
19843 /*
19844  * WARNING: The C register and register group struct declarations are provided for
19845  * convenience and illustrative purposes. They should, however, be used with
19846  * caution as the C language standard provides no guarantees about the alignment or
19847  * atomicity of device memory accesses. The recommended practice for writing
19848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19849  * alt_write_word() functions.
19850  *
19851  * The struct declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB.
19852  */
19853 struct ALT_EMAC_GMAC_TX64OCTETS_GB_s
19854 {
19855  const uint32_t cnt : 32; /* tx64octets_gb */
19856 };
19857 
19858 /* The typedef declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB. */
19859 typedef volatile struct ALT_EMAC_GMAC_TX64OCTETS_GB_s ALT_EMAC_GMAC_TX64OCTETS_GB_t;
19860 #endif /* __ASSEMBLY__ */
19861 
19862 /* The byte offset of the ALT_EMAC_GMAC_TX64OCTETS_GB register from the beginning of the component. */
19863 #define ALT_EMAC_GMAC_TX64OCTETS_GB_OFST 0x124
19864 /* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register. */
19865 #define ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX64OCTETS_GB_OFST))
19866 
19867 /*
19868  * Register : Register 74 (tx65to127octets_gb Register) - tx65to127octets_gb
19869  *
19870  * Number of good and bad frames transmitted with length between 65 and 127
19871  * (inclusive) bytes, exclusive of preamble and retried frames
19872  *
19873  * Register Layout
19874  *
19875  * Bits | Access | Reset | Description
19876  * :-------|:-------|:------|:-------------------
19877  * [31:0] | R | 0x0 | tx65to127octets_gb
19878  *
19879  */
19880 /*
19881  * Field : tx65to127octets_gb - cnt
19882  *
19883  * Number of good and bad frames transmitted with length between 65 and 127
19884  * (inclusive) bytes, exclusive of preamble and retried frames
19885  *
19886  * Field Access Macros:
19887  *
19888  */
19889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
19890 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_LSB 0
19891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
19892 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_MSB 31
19893 /* The width in bits of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
19894 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_WIDTH 32
19895 /* The mask used to set the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
19896 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff
19897 /* The mask used to clear the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
19898 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000
19899 /* The reset value of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
19900 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_RESET 0x0
19901 /* Extracts the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT field value from a register. */
19902 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19903 /* Produces a ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
19904 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
19905 
19906 #ifndef __ASSEMBLY__
19907 /*
19908  * WARNING: The C register and register group struct declarations are provided for
19909  * convenience and illustrative purposes. They should, however, be used with
19910  * caution as the C language standard provides no guarantees about the alignment or
19911  * atomicity of device memory accesses. The recommended practice for writing
19912  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19913  * alt_write_word() functions.
19914  *
19915  * The struct declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB.
19916  */
19917 struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s
19918 {
19919  const uint32_t cnt : 32; /* tx65to127octets_gb */
19920 };
19921 
19922 /* The typedef declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB. */
19923 typedef volatile struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t;
19924 #endif /* __ASSEMBLY__ */
19925 
19926 /* The byte offset of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register from the beginning of the component. */
19927 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST 0x128
19928 /* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register. */
19929 #define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST))
19930 
19931 /*
19932  * Register : Register 75 (tx128to255octets_gb Register) - tx128to255octets_gb
19933  *
19934  * Number of good and bad frames transmitted with length between 128 and 255
19935  * (inclusive) bytes, exclusive of preamble and retried frames
19936  *
19937  * Register Layout
19938  *
19939  * Bits | Access | Reset | Description
19940  * :-------|:-------|:------|:--------------------
19941  * [31:0] | R | 0x0 | tx128to255octets_gb
19942  *
19943  */
19944 /*
19945  * Field : tx128to255octets_gb - cnt
19946  *
19947  * Number of good and bad frames transmitted with length between 128 and 255
19948  * (inclusive) bytes, exclusive of preamble and retried frames
19949  *
19950  * Field Access Macros:
19951  *
19952  */
19953 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
19954 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_LSB 0
19955 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
19956 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_MSB 31
19957 /* The width in bits of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
19958 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_WIDTH 32
19959 /* The mask used to set the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
19960 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff
19961 /* The mask used to clear the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
19962 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000
19963 /* The reset value of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
19964 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_RESET 0x0
19965 /* Extracts the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT field value from a register. */
19966 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
19967 /* Produces a ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
19968 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
19969 
19970 #ifndef __ASSEMBLY__
19971 /*
19972  * WARNING: The C register and register group struct declarations are provided for
19973  * convenience and illustrative purposes. They should, however, be used with
19974  * caution as the C language standard provides no guarantees about the alignment or
19975  * atomicity of device memory accesses. The recommended practice for writing
19976  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19977  * alt_write_word() functions.
19978  *
19979  * The struct declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB.
19980  */
19981 struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s
19982 {
19983  const uint32_t cnt : 32; /* tx128to255octets_gb */
19984 };
19985 
19986 /* The typedef declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB. */
19987 typedef volatile struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t;
19988 #endif /* __ASSEMBLY__ */
19989 
19990 /* The byte offset of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register from the beginning of the component. */
19991 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST 0x12c
19992 /* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register. */
19993 #define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST))
19994 
19995 /*
19996  * Register : Register 76 (tx256to511octets_gb Register) - tx256to511octets_gb
19997  *
19998  * Number of good and bad frames transmitted with length between 256 and 511
19999  * (inclusive) bytes, exclusive of preamble and retried frames
20000  *
20001  * Register Layout
20002  *
20003  * Bits | Access | Reset | Description
20004  * :-------|:-------|:------|:--------------------
20005  * [31:0] | R | 0x0 | tx256to511octets_gb
20006  *
20007  */
20008 /*
20009  * Field : tx256to511octets_gb - cnt
20010  *
20011  * Number of good and bad frames transmitted with length between 256 and 511
20012  * (inclusive) bytes, exclusive of preamble and retried frames
20013  *
20014  * Field Access Macros:
20015  *
20016  */
20017 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
20018 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_LSB 0
20019 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
20020 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_MSB 31
20021 /* The width in bits of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
20022 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_WIDTH 32
20023 /* The mask used to set the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
20024 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff
20025 /* The mask used to clear the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
20026 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000
20027 /* The reset value of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
20028 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_RESET 0x0
20029 /* Extracts the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT field value from a register. */
20030 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20031 /* Produces a ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
20032 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20033 
20034 #ifndef __ASSEMBLY__
20035 /*
20036  * WARNING: The C register and register group struct declarations are provided for
20037  * convenience and illustrative purposes. They should, however, be used with
20038  * caution as the C language standard provides no guarantees about the alignment or
20039  * atomicity of device memory accesses. The recommended practice for writing
20040  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20041  * alt_write_word() functions.
20042  *
20043  * The struct declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB.
20044  */
20045 struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s
20046 {
20047  const uint32_t cnt : 32; /* tx256to511octets_gb */
20048 };
20049 
20050 /* The typedef declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB. */
20051 typedef volatile struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t;
20052 #endif /* __ASSEMBLY__ */
20053 
20054 /* The byte offset of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register from the beginning of the component. */
20055 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST 0x130
20056 /* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register. */
20057 #define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST))
20058 
20059 /*
20060  * Register : Register 77 (tx512to1023octets_gb Register) - tx512to1023octets_gb
20061  *
20062  * Number of good and bad frames transmitted with length between 512 and 1,023
20063  * (inclusive) bytes, exclusive of preamble and retried frames
20064  *
20065  * Register Layout
20066  *
20067  * Bits | Access | Reset | Description
20068  * :-------|:-------|:------|:---------------------
20069  * [31:0] | R | 0x0 | tx512to1023octets_gb
20070  *
20071  */
20072 /*
20073  * Field : tx512to1023octets_gb - cnt
20074  *
20075  * Number of good and bad frames transmitted with length between 512 and 1,023
20076  * (inclusive) bytes, exclusive of preamble and retried frames
20077  *
20078  * Field Access Macros:
20079  *
20080  */
20081 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
20082 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_LSB 0
20083 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
20084 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_MSB 31
20085 /* The width in bits of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
20086 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_WIDTH 32
20087 /* The mask used to set the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
20088 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff
20089 /* The mask used to clear the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
20090 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000
20091 /* The reset value of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
20092 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_RESET 0x0
20093 /* Extracts the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT field value from a register. */
20094 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20095 /* Produces a ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
20096 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20097 
20098 #ifndef __ASSEMBLY__
20099 /*
20100  * WARNING: The C register and register group struct declarations are provided for
20101  * convenience and illustrative purposes. They should, however, be used with
20102  * caution as the C language standard provides no guarantees about the alignment or
20103  * atomicity of device memory accesses. The recommended practice for writing
20104  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20105  * alt_write_word() functions.
20106  *
20107  * The struct declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB.
20108  */
20109 struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s
20110 {
20111  const uint32_t cnt : 32; /* tx512to1023octets_gb */
20112 };
20113 
20114 /* The typedef declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB. */
20115 typedef volatile struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t;
20116 #endif /* __ASSEMBLY__ */
20117 
20118 /* The byte offset of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register from the beginning of the component. */
20119 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST 0x134
20120 /* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register. */
20121 #define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST))
20122 
20123 /*
20124  * Register : Register 78 (tx1024tomaxoctets_gb Register) - tx1024tomaxoctets_gb
20125  *
20126  * Number of good and bad frames transmitted with length between 1,024 and maxsize
20127  * (inclusive) bytes, exclusive of preamble and retried frames
20128  *
20129  * Register Layout
20130  *
20131  * Bits | Access | Reset | Description
20132  * :-------|:-------|:------|:---------------------
20133  * [31:0] | R | 0x0 | tx1024tomaxoctets_gb
20134  *
20135  */
20136 /*
20137  * Field : tx1024tomaxoctets_gb - cnt
20138  *
20139  * Number of good and bad frames transmitted with length between 1,024 and maxsize
20140  * (inclusive) bytes, exclusive of preamble and retried frames
20141  *
20142  * Field Access Macros:
20143  *
20144  */
20145 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
20146 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_LSB 0
20147 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
20148 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_MSB 31
20149 /* The width in bits of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
20150 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_WIDTH 32
20151 /* The mask used to set the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
20152 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff
20153 /* The mask used to clear the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
20154 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000
20155 /* The reset value of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
20156 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_RESET 0x0
20157 /* Extracts the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT field value from a register. */
20158 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20159 /* Produces a ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
20160 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20161 
20162 #ifndef __ASSEMBLY__
20163 /*
20164  * WARNING: The C register and register group struct declarations are provided for
20165  * convenience and illustrative purposes. They should, however, be used with
20166  * caution as the C language standard provides no guarantees about the alignment or
20167  * atomicity of device memory accesses. The recommended practice for writing
20168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20169  * alt_write_word() functions.
20170  *
20171  * The struct declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB.
20172  */
20173 struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s
20174 {
20175  const uint32_t cnt : 32; /* tx1024tomaxoctets_gb */
20176 };
20177 
20178 /* The typedef declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB. */
20179 typedef volatile struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t;
20180 #endif /* __ASSEMBLY__ */
20181 
20182 /* The byte offset of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register from the beginning of the component. */
20183 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST 0x138
20184 /* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register. */
20185 #define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST))
20186 
20187 /*
20188  * Register : Register 79 (txunicastframes_gb Register) - txunicastframes_gb
20189  *
20190  * Number of good and bad unicast frames transmitted
20191  *
20192  * Register Layout
20193  *
20194  * Bits | Access | Reset | Description
20195  * :-------|:-------|:------|:-------------------
20196  * [31:0] | R | 0x0 | txunicastframes_gb
20197  *
20198  */
20199 /*
20200  * Field : txunicastframes_gb - cnt
20201  *
20202  * Number of good and bad unicast frames transmitted
20203  *
20204  * Field Access Macros:
20205  *
20206  */
20207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
20208 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_LSB 0
20209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
20210 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_MSB 31
20211 /* The width in bits of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
20212 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_WIDTH 32
20213 /* The mask used to set the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
20214 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET_MSK 0xffffffff
20215 /* The mask used to clear the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
20216 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_CLR_MSK 0x00000000
20217 /* The reset value of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
20218 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_RESET 0x0
20219 /* Extracts the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT field value from a register. */
20220 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20221 /* Produces a ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value suitable for setting the register. */
20222 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20223 
20224 #ifndef __ASSEMBLY__
20225 /*
20226  * WARNING: The C register and register group struct declarations are provided for
20227  * convenience and illustrative purposes. They should, however, be used with
20228  * caution as the C language standard provides no guarantees about the alignment or
20229  * atomicity of device memory accesses. The recommended practice for writing
20230  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20231  * alt_write_word() functions.
20232  *
20233  * The struct declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB.
20234  */
20235 struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s
20236 {
20237  const uint32_t cnt : 32; /* txunicastframes_gb */
20238 };
20239 
20240 /* The typedef declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB. */
20241 typedef volatile struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t;
20242 #endif /* __ASSEMBLY__ */
20243 
20244 /* The byte offset of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register from the beginning of the component. */
20245 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST 0x13c
20246 /* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register. */
20247 #define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST))
20248 
20249 /*
20250  * Register : Register 80 (txmulticastframes_gb Register) - txmulticastframes_gb
20251  *
20252  * Number of good and bad multicast frames transmitted
20253  *
20254  * Register Layout
20255  *
20256  * Bits | Access | Reset | Description
20257  * :-------|:-------|:------|:---------------------
20258  * [31:0] | R | 0x0 | txmulticastframes_gb
20259  *
20260  */
20261 /*
20262  * Field : txmulticastframes_gb - cnt
20263  *
20264  * Number of good and bad multicast frames transmitted
20265  *
20266  * Field Access Macros:
20267  *
20268  */
20269 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
20270 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_LSB 0
20271 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
20272 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_MSB 31
20273 /* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
20274 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_WIDTH 32
20275 /* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
20276 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET_MSK 0xffffffff
20277 /* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
20278 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_CLR_MSK 0x00000000
20279 /* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
20280 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_RESET 0x0
20281 /* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT field value from a register. */
20282 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20283 /* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value suitable for setting the register. */
20284 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20285 
20286 #ifndef __ASSEMBLY__
20287 /*
20288  * WARNING: The C register and register group struct declarations are provided for
20289  * convenience and illustrative purposes. They should, however, be used with
20290  * caution as the C language standard provides no guarantees about the alignment or
20291  * atomicity of device memory accesses. The recommended practice for writing
20292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20293  * alt_write_word() functions.
20294  *
20295  * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB.
20296  */
20297 struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s
20298 {
20299  const uint32_t cnt : 32; /* txmulticastframes_gb */
20300 };
20301 
20302 /* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB. */
20303 typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s ALT_EMAC_GMAC_TXMCASTFRMS_GB_t;
20304 #endif /* __ASSEMBLY__ */
20305 
20306 /* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register from the beginning of the component. */
20307 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST 0x140
20308 /* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register. */
20309 #define ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST))
20310 
20311 /*
20312  * Register : Register 81 (txbroadcastframes_gb Register) - txbroadcastframes_gb
20313  *
20314  * Number of good and bad broadcast frames transmitted
20315  *
20316  * Register Layout
20317  *
20318  * Bits | Access | Reset | Description
20319  * :-------|:-------|:------|:---------------------
20320  * [31:0] | R | 0x0 | txbroadcastframes_gb
20321  *
20322  */
20323 /*
20324  * Field : txbroadcastframes_gb - cnt
20325  *
20326  * Number of good and bad broadcast frames transmitted
20327  *
20328  * Field Access Macros:
20329  *
20330  */
20331 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
20332 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_LSB 0
20333 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
20334 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_MSB 31
20335 /* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
20336 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_WIDTH 32
20337 /* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
20338 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET_MSK 0xffffffff
20339 /* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
20340 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_CLR_MSK 0x00000000
20341 /* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
20342 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_RESET 0x0
20343 /* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT field value from a register. */
20344 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20345 /* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value suitable for setting the register. */
20346 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
20347 
20348 #ifndef __ASSEMBLY__
20349 /*
20350  * WARNING: The C register and register group struct declarations are provided for
20351  * convenience and illustrative purposes. They should, however, be used with
20352  * caution as the C language standard provides no guarantees about the alignment or
20353  * atomicity of device memory accesses. The recommended practice for writing
20354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20355  * alt_write_word() functions.
20356  *
20357  * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB.
20358  */
20359 struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s
20360 {
20361  const uint32_t cnt : 32; /* txbroadcastframes_gb */
20362 };
20363 
20364 /* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB. */
20365 typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s ALT_EMAC_GMAC_TXBCASTFRMS_GB_t;
20366 #endif /* __ASSEMBLY__ */
20367 
20368 /* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register from the beginning of the component. */
20369 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST 0x144
20370 /* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register. */
20371 #define ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST))
20372 
20373 /*
20374  * Register : Register 82 (txunderflowerror Register) - txunderflowerror
20375  *
20376  * Number of frames aborted due to frame underflow error
20377  *
20378  * Register Layout
20379  *
20380  * Bits | Access | Reset | Description
20381  * :-------|:-------|:------|:-----------------
20382  * [31:0] | R | 0x0 | txunderflowerror
20383  *
20384  */
20385 /*
20386  * Field : txunderflowerror - cnt
20387  *
20388  * Number of frames aborted due to frame underflow error
20389  *
20390  * Field Access Macros:
20391  *
20392  */
20393 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
20394 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_LSB 0
20395 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
20396 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_MSB 31
20397 /* The width in bits of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
20398 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_WIDTH 32
20399 /* The mask used to set the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
20400 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET_MSK 0xffffffff
20401 /* The mask used to clear the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
20402 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_CLR_MSK 0x00000000
20403 /* The reset value of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
20404 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_RESET 0x0
20405 /* Extracts the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT field value from a register. */
20406 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20407 /* Produces a ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value suitable for setting the register. */
20408 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
20409 
20410 #ifndef __ASSEMBLY__
20411 /*
20412  * WARNING: The C register and register group struct declarations are provided for
20413  * convenience and illustrative purposes. They should, however, be used with
20414  * caution as the C language standard provides no guarantees about the alignment or
20415  * atomicity of device memory accesses. The recommended practice for writing
20416  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20417  * alt_write_word() functions.
20418  *
20419  * The struct declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR.
20420  */
20421 struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s
20422 {
20423  const uint32_t cnt : 32; /* txunderflowerror */
20424 };
20425 
20426 /* The typedef declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR. */
20427 typedef volatile struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s ALT_EMAC_GMAC_TXUNDERFLOWERROR_t;
20428 #endif /* __ASSEMBLY__ */
20429 
20430 /* The byte offset of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register from the beginning of the component. */
20431 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST 0x148
20432 /* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register. */
20433 #define ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST))
20434 
20435 /*
20436  * Register : Register 83 (txsinglecol_g Register) - txsinglecol_g
20437  *
20438  * Number of successfully transmitted frames after a single collision in Half-
20439  * duplex mode
20440  *
20441  * Register Layout
20442  *
20443  * Bits | Access | Reset | Description
20444  * :-------|:-------|:------|:--------------
20445  * [31:0] | R | 0x0 | txsinglecol_g
20446  *
20447  */
20448 /*
20449  * Field : txsinglecol_g - cnt
20450  *
20451  * Number of successfully transmitted frames after a single collision in Half-
20452  * duplex mode
20453  *
20454  * Field Access Macros:
20455  *
20456  */
20457 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
20458 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_LSB 0
20459 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
20460 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_MSB 31
20461 /* The width in bits of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
20462 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_WIDTH 32
20463 /* The mask used to set the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
20464 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET_MSK 0xffffffff
20465 /* The mask used to clear the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
20466 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_CLR_MSK 0x00000000
20467 /* The reset value of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
20468 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_RESET 0x0
20469 /* Extracts the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT field value from a register. */
20470 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20471 /* Produces a ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value suitable for setting the register. */
20472 #define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
20473 
20474 #ifndef __ASSEMBLY__
20475 /*
20476  * WARNING: The C register and register group struct declarations are provided for
20477  * convenience and illustrative purposes. They should, however, be used with
20478  * caution as the C language standard provides no guarantees about the alignment or
20479  * atomicity of device memory accesses. The recommended practice for writing
20480  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20481  * alt_write_word() functions.
20482  *
20483  * The struct declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G.
20484  */
20485 struct ALT_EMAC_GMAC_TXSINGLECOL_G_s
20486 {
20487  const uint32_t cnt : 32; /* txsinglecol_g */
20488 };
20489 
20490 /* The typedef declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G. */
20491 typedef volatile struct ALT_EMAC_GMAC_TXSINGLECOL_G_s ALT_EMAC_GMAC_TXSINGLECOL_G_t;
20492 #endif /* __ASSEMBLY__ */
20493 
20494 /* The byte offset of the ALT_EMAC_GMAC_TXSINGLECOL_G register from the beginning of the component. */
20495 #define ALT_EMAC_GMAC_TXSINGLECOL_G_OFST 0x14c
20496 /* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register. */
20497 #define ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXSINGLECOL_G_OFST))
20498 
20499 /*
20500  * Register : Register 84 (txmulticol_g Register) - txmulticol_g
20501  *
20502  * Number of successfully transmitted frames after more than a single collision in
20503  * Half-duplex mode
20504  *
20505  * Register Layout
20506  *
20507  * Bits | Access | Reset | Description
20508  * :-------|:-------|:------|:-------------
20509  * [31:0] | R | 0x0 | txmulticol_g
20510  *
20511  */
20512 /*
20513  * Field : txmulticol_g - cnt
20514  *
20515  * Number of successfully transmitted frames after more than a single collision in
20516  * Half-duplex mode
20517  *
20518  * Field Access Macros:
20519  *
20520  */
20521 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
20522 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_LSB 0
20523 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
20524 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_MSB 31
20525 /* The width in bits of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
20526 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_WIDTH 32
20527 /* The mask used to set the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
20528 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET_MSK 0xffffffff
20529 /* The mask used to clear the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
20530 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_CLR_MSK 0x00000000
20531 /* The reset value of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
20532 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_RESET 0x0
20533 /* Extracts the ALT_EMAC_GMAC_TXMULTICOL_G_CNT field value from a register. */
20534 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20535 /* Produces a ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value suitable for setting the register. */
20536 #define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
20537 
20538 #ifndef __ASSEMBLY__
20539 /*
20540  * WARNING: The C register and register group struct declarations are provided for
20541  * convenience and illustrative purposes. They should, however, be used with
20542  * caution as the C language standard provides no guarantees about the alignment or
20543  * atomicity of device memory accesses. The recommended practice for writing
20544  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20545  * alt_write_word() functions.
20546  *
20547  * The struct declaration for register ALT_EMAC_GMAC_TXMULTICOL_G.
20548  */
20549 struct ALT_EMAC_GMAC_TXMULTICOL_G_s
20550 {
20551  const uint32_t cnt : 32; /* txmulticol_g */
20552 };
20553 
20554 /* The typedef declaration for register ALT_EMAC_GMAC_TXMULTICOL_G. */
20555 typedef volatile struct ALT_EMAC_GMAC_TXMULTICOL_G_s ALT_EMAC_GMAC_TXMULTICOL_G_t;
20556 #endif /* __ASSEMBLY__ */
20557 
20558 /* The byte offset of the ALT_EMAC_GMAC_TXMULTICOL_G register from the beginning of the component. */
20559 #define ALT_EMAC_GMAC_TXMULTICOL_G_OFST 0x150
20560 /* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register. */
20561 #define ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMULTICOL_G_OFST))
20562 
20563 /*
20564  * Register : Register 85 (txdeferred Register) - txdeferred
20565  *
20566  * Number of successfully transmitted frames after a deferral in Halfduplex mode
20567  *
20568  * Register Layout
20569  *
20570  * Bits | Access | Reset | Description
20571  * :-------|:-------|:------|:------------
20572  * [31:0] | R | 0x0 | txdeferred
20573  *
20574  */
20575 /*
20576  * Field : txdeferred - cnt
20577  *
20578  * Number of successfully transmitted frames after a deferral in Halfduplex mode
20579  *
20580  * Field Access Macros:
20581  *
20582  */
20583 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
20584 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_LSB 0
20585 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
20586 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_MSB 31
20587 /* The width in bits of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
20588 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_WIDTH 32
20589 /* The mask used to set the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
20590 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET_MSK 0xffffffff
20591 /* The mask used to clear the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
20592 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_CLR_MSK 0x00000000
20593 /* The reset value of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
20594 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_RESET 0x0
20595 /* Extracts the ALT_EMAC_GMAC_TXDEFERRED_CNT field value from a register. */
20596 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20597 /* Produces a ALT_EMAC_GMAC_TXDEFERRED_CNT register field value suitable for setting the register. */
20598 #define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET(value) (((value) << 0) & 0xffffffff)
20599 
20600 #ifndef __ASSEMBLY__
20601 /*
20602  * WARNING: The C register and register group struct declarations are provided for
20603  * convenience and illustrative purposes. They should, however, be used with
20604  * caution as the C language standard provides no guarantees about the alignment or
20605  * atomicity of device memory accesses. The recommended practice for writing
20606  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20607  * alt_write_word() functions.
20608  *
20609  * The struct declaration for register ALT_EMAC_GMAC_TXDEFERRED.
20610  */
20611 struct ALT_EMAC_GMAC_TXDEFERRED_s
20612 {
20613  const uint32_t cnt : 32; /* txdeferred */
20614 };
20615 
20616 /* The typedef declaration for register ALT_EMAC_GMAC_TXDEFERRED. */
20617 typedef volatile struct ALT_EMAC_GMAC_TXDEFERRED_s ALT_EMAC_GMAC_TXDEFERRED_t;
20618 #endif /* __ASSEMBLY__ */
20619 
20620 /* The byte offset of the ALT_EMAC_GMAC_TXDEFERRED register from the beginning of the component. */
20621 #define ALT_EMAC_GMAC_TXDEFERRED_OFST 0x154
20622 /* The address of the ALT_EMAC_GMAC_TXDEFERRED register. */
20623 #define ALT_EMAC_GMAC_TXDEFERRED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXDEFERRED_OFST))
20624 
20625 /*
20626  * Register : Register 86 (txlatecol Register) - txlatecol
20627  *
20628  * Number of frames aborted due to late collision error
20629  *
20630  * Register Layout
20631  *
20632  * Bits | Access | Reset | Description
20633  * :-------|:-------|:------|:------------
20634  * [31:0] | R | 0x0 | txlatecol
20635  *
20636  */
20637 /*
20638  * Field : txlatecol - cnt
20639  *
20640  * Number of frames aborted due to late collision error
20641  *
20642  * Field Access Macros:
20643  *
20644  */
20645 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
20646 #define ALT_EMAC_GMAC_TXLATECOL_CNT_LSB 0
20647 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
20648 #define ALT_EMAC_GMAC_TXLATECOL_CNT_MSB 31
20649 /* The width in bits of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
20650 #define ALT_EMAC_GMAC_TXLATECOL_CNT_WIDTH 32
20651 /* The mask used to set the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
20652 #define ALT_EMAC_GMAC_TXLATECOL_CNT_SET_MSK 0xffffffff
20653 /* The mask used to clear the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
20654 #define ALT_EMAC_GMAC_TXLATECOL_CNT_CLR_MSK 0x00000000
20655 /* The reset value of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
20656 #define ALT_EMAC_GMAC_TXLATECOL_CNT_RESET 0x0
20657 /* Extracts the ALT_EMAC_GMAC_TXLATECOL_CNT field value from a register. */
20658 #define ALT_EMAC_GMAC_TXLATECOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20659 /* Produces a ALT_EMAC_GMAC_TXLATECOL_CNT register field value suitable for setting the register. */
20660 #define ALT_EMAC_GMAC_TXLATECOL_CNT_SET(value) (((value) << 0) & 0xffffffff)
20661 
20662 #ifndef __ASSEMBLY__
20663 /*
20664  * WARNING: The C register and register group struct declarations are provided for
20665  * convenience and illustrative purposes. They should, however, be used with
20666  * caution as the C language standard provides no guarantees about the alignment or
20667  * atomicity of device memory accesses. The recommended practice for writing
20668  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20669  * alt_write_word() functions.
20670  *
20671  * The struct declaration for register ALT_EMAC_GMAC_TXLATECOL.
20672  */
20673 struct ALT_EMAC_GMAC_TXLATECOL_s
20674 {
20675  const uint32_t cnt : 32; /* txlatecol */
20676 };
20677 
20678 /* The typedef declaration for register ALT_EMAC_GMAC_TXLATECOL. */
20679 typedef volatile struct ALT_EMAC_GMAC_TXLATECOL_s ALT_EMAC_GMAC_TXLATECOL_t;
20680 #endif /* __ASSEMBLY__ */
20681 
20682 /* The byte offset of the ALT_EMAC_GMAC_TXLATECOL register from the beginning of the component. */
20683 #define ALT_EMAC_GMAC_TXLATECOL_OFST 0x158
20684 /* The address of the ALT_EMAC_GMAC_TXLATECOL register. */
20685 #define ALT_EMAC_GMAC_TXLATECOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXLATECOL_OFST))
20686 
20687 /*
20688  * Register : Register 87 (txexesscol Register) - txexesscol
20689  *
20690  * Number of frames aborted due to excessive (16) collision errors
20691  *
20692  * Register Layout
20693  *
20694  * Bits | Access | Reset | Description
20695  * :-------|:-------|:------|:------------
20696  * [31:0] | R | 0x0 | txexesscol
20697  *
20698  */
20699 /*
20700  * Field : txexesscol - cnt
20701  *
20702  * Number of frames aborted due to excessive (16) collision errors
20703  *
20704  * Field Access Macros:
20705  *
20706  */
20707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
20708 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_LSB 0
20709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
20710 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_MSB 31
20711 /* The width in bits of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
20712 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_WIDTH 32
20713 /* The mask used to set the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
20714 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET_MSK 0xffffffff
20715 /* The mask used to clear the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
20716 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_CLR_MSK 0x00000000
20717 /* The reset value of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
20718 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_RESET 0x0
20719 /* Extracts the ALT_EMAC_GMAC_TXEXESSCOL_CNT field value from a register. */
20720 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20721 /* Produces a ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value suitable for setting the register. */
20722 #define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET(value) (((value) << 0) & 0xffffffff)
20723 
20724 #ifndef __ASSEMBLY__
20725 /*
20726  * WARNING: The C register and register group struct declarations are provided for
20727  * convenience and illustrative purposes. They should, however, be used with
20728  * caution as the C language standard provides no guarantees about the alignment or
20729  * atomicity of device memory accesses. The recommended practice for writing
20730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20731  * alt_write_word() functions.
20732  *
20733  * The struct declaration for register ALT_EMAC_GMAC_TXEXESSCOL.
20734  */
20735 struct ALT_EMAC_GMAC_TXEXESSCOL_s
20736 {
20737  const uint32_t cnt : 32; /* txexesscol */
20738 };
20739 
20740 /* The typedef declaration for register ALT_EMAC_GMAC_TXEXESSCOL. */
20741 typedef volatile struct ALT_EMAC_GMAC_TXEXESSCOL_s ALT_EMAC_GMAC_TXEXESSCOL_t;
20742 #endif /* __ASSEMBLY__ */
20743 
20744 /* The byte offset of the ALT_EMAC_GMAC_TXEXESSCOL register from the beginning of the component. */
20745 #define ALT_EMAC_GMAC_TXEXESSCOL_OFST 0x15c
20746 /* The address of the ALT_EMAC_GMAC_TXEXESSCOL register. */
20747 #define ALT_EMAC_GMAC_TXEXESSCOL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXESSCOL_OFST))
20748 
20749 /*
20750  * Register : Register 88 (txcarriererror Register) - txcarriererr
20751  *
20752  * Number of frames aborted due to carrier sense error (no carrier or loss of
20753  * carrier)
20754  *
20755  * Register Layout
20756  *
20757  * Bits | Access | Reset | Description
20758  * :-------|:-------|:------|:---------------
20759  * [31:0] | R | 0x0 | txcarriererror
20760  *
20761  */
20762 /*
20763  * Field : txcarriererror - cnt
20764  *
20765  * Number of frames aborted due to carrier sense error (no carrier or loss of
20766  * carrier)
20767  *
20768  * Field Access Macros:
20769  *
20770  */
20771 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
20772 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_LSB 0
20773 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
20774 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_MSB 31
20775 /* The width in bits of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
20776 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_WIDTH 32
20777 /* The mask used to set the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
20778 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET_MSK 0xffffffff
20779 /* The mask used to clear the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
20780 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_CLR_MSK 0x00000000
20781 /* The reset value of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
20782 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_RESET 0x0
20783 /* Extracts the ALT_EMAC_GMAC_TXCARRIERERR_CNT field value from a register. */
20784 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20785 /* Produces a ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value suitable for setting the register. */
20786 #define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET(value) (((value) << 0) & 0xffffffff)
20787 
20788 #ifndef __ASSEMBLY__
20789 /*
20790  * WARNING: The C register and register group struct declarations are provided for
20791  * convenience and illustrative purposes. They should, however, be used with
20792  * caution as the C language standard provides no guarantees about the alignment or
20793  * atomicity of device memory accesses. The recommended practice for writing
20794  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20795  * alt_write_word() functions.
20796  *
20797  * The struct declaration for register ALT_EMAC_GMAC_TXCARRIERERR.
20798  */
20799 struct ALT_EMAC_GMAC_TXCARRIERERR_s
20800 {
20801  const uint32_t cnt : 32; /* txcarriererror */
20802 };
20803 
20804 /* The typedef declaration for register ALT_EMAC_GMAC_TXCARRIERERR. */
20805 typedef volatile struct ALT_EMAC_GMAC_TXCARRIERERR_s ALT_EMAC_GMAC_TXCARRIERERR_t;
20806 #endif /* __ASSEMBLY__ */
20807 
20808 /* The byte offset of the ALT_EMAC_GMAC_TXCARRIERERR register from the beginning of the component. */
20809 #define ALT_EMAC_GMAC_TXCARRIERERR_OFST 0x160
20810 /* The address of the ALT_EMAC_GMAC_TXCARRIERERR register. */
20811 #define ALT_EMAC_GMAC_TXCARRIERERR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXCARRIERERR_OFST))
20812 
20813 /*
20814  * Register : Register 89 (txoctetcount_g Register) - txoctetcnt
20815  *
20816  * Number of bytes transmitted, exclusive of preamble, in good frames only
20817  *
20818  * Register Layout
20819  *
20820  * Bits | Access | Reset | Description
20821  * :-------|:-------|:------|:---------------
20822  * [31:0] | R | 0x0 | txoctetcount_g
20823  *
20824  */
20825 /*
20826  * Field : txoctetcount_g - txoctetcount_g
20827  *
20828  * Number of bytes transmitted, exclusive of preamble, in good frames only
20829  *
20830  * Field Access Macros:
20831  *
20832  */
20833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
20834 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_LSB 0
20835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
20836 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_MSB 31
20837 /* The width in bits of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
20838 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_WIDTH 32
20839 /* The mask used to set the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
20840 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET_MSK 0xffffffff
20841 /* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
20842 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_CLR_MSK 0x00000000
20843 /* The reset value of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
20844 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_RESET 0x0
20845 /* Extracts the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G field value from a register. */
20846 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_GET(value) (((value) & 0xffffffff) >> 0)
20847 /* Produces a ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value suitable for setting the register. */
20848 #define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET(value) (((value) << 0) & 0xffffffff)
20849 
20850 #ifndef __ASSEMBLY__
20851 /*
20852  * WARNING: The C register and register group struct declarations are provided for
20853  * convenience and illustrative purposes. They should, however, be used with
20854  * caution as the C language standard provides no guarantees about the alignment or
20855  * atomicity of device memory accesses. The recommended practice for writing
20856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20857  * alt_write_word() functions.
20858  *
20859  * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCNT.
20860  */
20861 struct ALT_EMAC_GMAC_TXOCTETCNT_s
20862 {
20863  const uint32_t txoctetcount_g : 32; /* txoctetcount_g */
20864 };
20865 
20866 /* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCNT. */
20867 typedef volatile struct ALT_EMAC_GMAC_TXOCTETCNT_s ALT_EMAC_GMAC_TXOCTETCNT_t;
20868 #endif /* __ASSEMBLY__ */
20869 
20870 /* The byte offset of the ALT_EMAC_GMAC_TXOCTETCNT register from the beginning of the component. */
20871 #define ALT_EMAC_GMAC_TXOCTETCNT_OFST 0x164
20872 /* The address of the ALT_EMAC_GMAC_TXOCTETCNT register. */
20873 #define ALT_EMAC_GMAC_TXOCTETCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCNT_OFST))
20874 
20875 /*
20876  * Register : Register 90 (txframecount_g Register) - txframecount_g
20877  *
20878  * Number of good frames transmitted
20879  *
20880  * Register Layout
20881  *
20882  * Bits | Access | Reset | Description
20883  * :-------|:-------|:------|:---------------
20884  * [31:0] | R | 0x0 | txframecount_g
20885  *
20886  */
20887 /*
20888  * Field : txframecount_g - cnt
20889  *
20890  * Number of good frames transmitted
20891  *
20892  * Field Access Macros:
20893  *
20894  */
20895 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
20896 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_LSB 0
20897 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
20898 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_MSB 31
20899 /* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
20900 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_WIDTH 32
20901 /* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
20902 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET_MSK 0xffffffff
20903 /* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
20904 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_CLR_MSK 0x00000000
20905 /* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
20906 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_RESET 0x0
20907 /* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT field value from a register. */
20908 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20909 /* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value suitable for setting the register. */
20910 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
20911 
20912 #ifndef __ASSEMBLY__
20913 /*
20914  * WARNING: The C register and register group struct declarations are provided for
20915  * convenience and illustrative purposes. They should, however, be used with
20916  * caution as the C language standard provides no guarantees about the alignment or
20917  * atomicity of device memory accesses. The recommended practice for writing
20918  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20919  * alt_write_word() functions.
20920  *
20921  * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G.
20922  */
20923 struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s
20924 {
20925  const uint32_t cnt : 32; /* txframecount_g */
20926 };
20927 
20928 /* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G. */
20929 typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s ALT_EMAC_GMAC_TXFRMCOUNT_G_t;
20930 #endif /* __ASSEMBLY__ */
20931 
20932 /* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_G register from the beginning of the component. */
20933 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST 0x168
20934 /* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register. */
20935 #define ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST))
20936 
20937 /*
20938  * Register : Register 91 (txexcessdef Register) - txexcessdef
20939  *
20940  * Number of frames aborted due to excessive deferral error (deferred for more than
20941  * two max-sized frame times)
20942  *
20943  * Register Layout
20944  *
20945  * Bits | Access | Reset | Description
20946  * :-------|:-------|:------|:------------
20947  * [31:0] | R | 0x0 | txexcessdef
20948  *
20949  */
20950 /*
20951  * Field : txexcessdef - cnt
20952  *
20953  * Number of frames aborted due to excessive deferral error (deferred for more than
20954  * two max-sized frame times)
20955  *
20956  * Field Access Macros:
20957  *
20958  */
20959 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
20960 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_LSB 0
20961 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
20962 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_MSB 31
20963 /* The width in bits of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
20964 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_WIDTH 32
20965 /* The mask used to set the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
20966 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET_MSK 0xffffffff
20967 /* The mask used to clear the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
20968 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_CLR_MSK 0x00000000
20969 /* The reset value of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
20970 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_RESET 0x0
20971 /* Extracts the ALT_EMAC_GMAC_TXEXCESSDEF_CNT field value from a register. */
20972 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
20973 /* Produces a ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value suitable for setting the register. */
20974 #define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET(value) (((value) << 0) & 0xffffffff)
20975 
20976 #ifndef __ASSEMBLY__
20977 /*
20978  * WARNING: The C register and register group struct declarations are provided for
20979  * convenience and illustrative purposes. They should, however, be used with
20980  * caution as the C language standard provides no guarantees about the alignment or
20981  * atomicity of device memory accesses. The recommended practice for writing
20982  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20983  * alt_write_word() functions.
20984  *
20985  * The struct declaration for register ALT_EMAC_GMAC_TXEXCESSDEF.
20986  */
20987 struct ALT_EMAC_GMAC_TXEXCESSDEF_s
20988 {
20989  const uint32_t cnt : 32; /* txexcessdef */
20990 };
20991 
20992 /* The typedef declaration for register ALT_EMAC_GMAC_TXEXCESSDEF. */
20993 typedef volatile struct ALT_EMAC_GMAC_TXEXCESSDEF_s ALT_EMAC_GMAC_TXEXCESSDEF_t;
20994 #endif /* __ASSEMBLY__ */
20995 
20996 /* The byte offset of the ALT_EMAC_GMAC_TXEXCESSDEF register from the beginning of the component. */
20997 #define ALT_EMAC_GMAC_TXEXCESSDEF_OFST 0x16c
20998 /* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register. */
20999 #define ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXCESSDEF_OFST))
21000 
21001 /*
21002  * Register : Register 92 (txpauseframes Register) - txpauseframes
21003  *
21004  * Number of good PAUSE frames transmitted
21005  *
21006  * Register Layout
21007  *
21008  * Bits | Access | Reset | Description
21009  * :-------|:-------|:------|:--------------
21010  * [31:0] | R | 0x0 | txpauseframes
21011  *
21012  */
21013 /*
21014  * Field : txpauseframes - cnt
21015  *
21016  * Number of good PAUSE frames transmitted
21017  *
21018  * Field Access Macros:
21019  *
21020  */
21021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
21022 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_LSB 0
21023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
21024 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_MSB 31
21025 /* The width in bits of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
21026 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_WIDTH 32
21027 /* The mask used to set the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
21028 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET_MSK 0xffffffff
21029 /* The mask used to clear the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
21030 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_CLR_MSK 0x00000000
21031 /* The reset value of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
21032 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_RESET 0x0
21033 /* Extracts the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT field value from a register. */
21034 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21035 /* Produces a ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value suitable for setting the register. */
21036 #define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
21037 
21038 #ifndef __ASSEMBLY__
21039 /*
21040  * WARNING: The C register and register group struct declarations are provided for
21041  * convenience and illustrative purposes. They should, however, be used with
21042  * caution as the C language standard provides no guarantees about the alignment or
21043  * atomicity of device memory accesses. The recommended practice for writing
21044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21045  * alt_write_word() functions.
21046  *
21047  * The struct declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS.
21048  */
21049 struct ALT_EMAC_GMAC_TXPAUSEFRMS_s
21050 {
21051  const uint32_t cnt : 32; /* txpauseframes */
21052 };
21053 
21054 /* The typedef declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS. */
21055 typedef volatile struct ALT_EMAC_GMAC_TXPAUSEFRMS_s ALT_EMAC_GMAC_TXPAUSEFRMS_t;
21056 #endif /* __ASSEMBLY__ */
21057 
21058 /* The byte offset of the ALT_EMAC_GMAC_TXPAUSEFRMS register from the beginning of the component. */
21059 #define ALT_EMAC_GMAC_TXPAUSEFRMS_OFST 0x170
21060 /* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register. */
21061 #define ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXPAUSEFRMS_OFST))
21062 
21063 /*
21064  * Register : Register 93 (txvlanframes_g Register) - txvlanframes_g
21065  *
21066  * Number of good VLAN frames transmitted, exclusive of retried frames
21067  *
21068  * Register Layout
21069  *
21070  * Bits | Access | Reset | Description
21071  * :-------|:-------|:------|:---------------
21072  * [31:0] | R | 0x0 | txvlanframes_g
21073  *
21074  */
21075 /*
21076  * Field : txvlanframes_g - cnt
21077  *
21078  * Number of good VLAN frames transmitted, exclusive of retried frames
21079  *
21080  * Field Access Macros:
21081  *
21082  */
21083 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
21084 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_LSB 0
21085 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
21086 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_MSB 31
21087 /* The width in bits of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
21088 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_WIDTH 32
21089 /* The mask used to set the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
21090 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET_MSK 0xffffffff
21091 /* The mask used to clear the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
21092 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_CLR_MSK 0x00000000
21093 /* The reset value of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
21094 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_RESET 0x0
21095 /* Extracts the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT field value from a register. */
21096 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21097 /* Produces a ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value suitable for setting the register. */
21098 #define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21099 
21100 #ifndef __ASSEMBLY__
21101 /*
21102  * WARNING: The C register and register group struct declarations are provided for
21103  * convenience and illustrative purposes. They should, however, be used with
21104  * caution as the C language standard provides no guarantees about the alignment or
21105  * atomicity of device memory accesses. The recommended practice for writing
21106  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21107  * alt_write_word() functions.
21108  *
21109  * The struct declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G.
21110  */
21111 struct ALT_EMAC_GMAC_TXVLANFRMS_G_s
21112 {
21113  const uint32_t cnt : 32; /* txvlanframes_g */
21114 };
21115 
21116 /* The typedef declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G. */
21117 typedef volatile struct ALT_EMAC_GMAC_TXVLANFRMS_G_s ALT_EMAC_GMAC_TXVLANFRMS_G_t;
21118 #endif /* __ASSEMBLY__ */
21119 
21120 /* The byte offset of the ALT_EMAC_GMAC_TXVLANFRMS_G register from the beginning of the component. */
21121 #define ALT_EMAC_GMAC_TXVLANFRMS_G_OFST 0x174
21122 /* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register. */
21123 #define ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXVLANFRMS_G_OFST))
21124 
21125 /*
21126  * Register : Register 94 (txoversize_g Register) - txoversize_g
21127  *
21128  * Number of good and bad frames received
21129  *
21130  * Register Layout
21131  *
21132  * Bits | Access | Reset | Description
21133  * :-------|:-------|:------|:-------------
21134  * [31:0] | R | 0x0 | txoversize_g
21135  *
21136  */
21137 /*
21138  * Field : txoversize_g - cnt
21139  *
21140  * Number of good and bad frames received
21141  *
21142  * Field Access Macros:
21143  *
21144  */
21145 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
21146 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_LSB 0
21147 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
21148 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_MSB 31
21149 /* The width in bits of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
21150 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_WIDTH 32
21151 /* The mask used to set the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
21152 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET_MSK 0xffffffff
21153 /* The mask used to clear the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
21154 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_CLR_MSK 0x00000000
21155 /* The reset value of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
21156 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_RESET 0x0
21157 /* Extracts the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT field value from a register. */
21158 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21159 /* Produces a ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value suitable for setting the register. */
21160 #define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21161 
21162 #ifndef __ASSEMBLY__
21163 /*
21164  * WARNING: The C register and register group struct declarations are provided for
21165  * convenience and illustrative purposes. They should, however, be used with
21166  * caution as the C language standard provides no guarantees about the alignment or
21167  * atomicity of device memory accesses. The recommended practice for writing
21168  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21169  * alt_write_word() functions.
21170  *
21171  * The struct declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G.
21172  */
21173 struct ALT_EMAC_GMAC_TXOVERSIZE_G_s
21174 {
21175  const uint32_t cnt : 32; /* txoversize_g */
21176 };
21177 
21178 /* The typedef declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G. */
21179 typedef volatile struct ALT_EMAC_GMAC_TXOVERSIZE_G_s ALT_EMAC_GMAC_TXOVERSIZE_G_t;
21180 #endif /* __ASSEMBLY__ */
21181 
21182 /* The byte offset of the ALT_EMAC_GMAC_TXOVERSIZE_G register from the beginning of the component. */
21183 #define ALT_EMAC_GMAC_TXOVERSIZE_G_OFST 0x178
21184 /* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register. */
21185 #define ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOVERSIZE_G_OFST))
21186 
21187 /*
21188  * Register : Register 95 (rxframecount_gb Register) - rxframecount_gb
21189  *
21190  * Number of good and bad frames received
21191  *
21192  * Register Layout
21193  *
21194  * Bits | Access | Reset | Description
21195  * :-------|:-------|:------|:--------------------------------
21196  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT
21197  *
21198  */
21199 /*
21200  * Field : cnt
21201  *
21202  * Number of good and bad frames received
21203  *
21204  * Field Access Macros:
21205  *
21206  */
21207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
21208 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_LSB 0
21209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
21210 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_MSB 31
21211 /* The width in bits of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
21212 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_WIDTH 32
21213 /* The mask used to set the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
21214 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET_MSK 0xffffffff
21215 /* The mask used to clear the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
21216 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_CLR_MSK 0x00000000
21217 /* The reset value of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
21218 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_RESET 0x0
21219 /* Extracts the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT field value from a register. */
21220 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21221 /* Produces a ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
21222 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21223 
21224 #ifndef __ASSEMBLY__
21225 /*
21226  * WARNING: The C register and register group struct declarations are provided for
21227  * convenience and illustrative purposes. They should, however, be used with
21228  * caution as the C language standard provides no guarantees about the alignment or
21229  * atomicity of device memory accesses. The recommended practice for writing
21230  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21231  * alt_write_word() functions.
21232  *
21233  * The struct declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB.
21234  */
21235 struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s
21236 {
21237  const uint32_t cnt : 32; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT */
21238 };
21239 
21240 /* The typedef declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB. */
21241 typedef volatile struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s ALT_EMAC_GMAC_RXFRMCOUNT_GB_t;
21242 #endif /* __ASSEMBLY__ */
21243 
21244 /* The byte offset of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register from the beginning of the component. */
21245 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST 0x180
21246 /* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register. */
21247 #define ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST))
21248 
21249 /*
21250  * Register : Register 97 (rxoctetcount_gb Register) - rxoctetcount_gb
21251  *
21252  * Number of bytes received, exclusive of preamble, in good and bad frames
21253  *
21254  * Register Layout
21255  *
21256  * Bits | Access | Reset | Description
21257  * :-------|:-------|:------|:----------------
21258  * [31:0] | R | 0x0 | rxoctetcount_gb
21259  *
21260  */
21261 /*
21262  * Field : rxoctetcount_gb - cnt
21263  *
21264  * Number of bytes received, exclusive of preamble, in good and bad frames
21265  *
21266  * Field Access Macros:
21267  *
21268  */
21269 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
21270 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_LSB 0
21271 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
21272 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_MSB 31
21273 /* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
21274 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_WIDTH 32
21275 /* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
21276 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET_MSK 0xffffffff
21277 /* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
21278 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_CLR_MSK 0x00000000
21279 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
21280 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_RESET 0x0
21281 /* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT field value from a register. */
21282 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21283 /* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
21284 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21285 
21286 #ifndef __ASSEMBLY__
21287 /*
21288  * WARNING: The C register and register group struct declarations are provided for
21289  * convenience and illustrative purposes. They should, however, be used with
21290  * caution as the C language standard provides no guarantees about the alignment or
21291  * atomicity of device memory accesses. The recommended practice for writing
21292  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21293  * alt_write_word() functions.
21294  *
21295  * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB.
21296  */
21297 struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s
21298 {
21299  const uint32_t cnt : 32; /* rxoctetcount_gb */
21300 };
21301 
21302 /* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB. */
21303 typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t;
21304 #endif /* __ASSEMBLY__ */
21305 
21306 /* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register from the beginning of the component. */
21307 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST 0x184
21308 /* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register. */
21309 #define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST))
21310 
21311 /*
21312  * Register : Register 98 (rxoctetcount_g Register) - rxoctetcount_g
21313  *
21314  * Number of bytes received, exclusive of preamble, only in good frames
21315  *
21316  * Register Layout
21317  *
21318  * Bits | Access | Reset | Description
21319  * :-------|:-------|:------|:---------------
21320  * [31:0] | R | 0x0 | rxoctetcount_g
21321  *
21322  */
21323 /*
21324  * Field : rxoctetcount_g - cnt
21325  *
21326  * Number of bytes received, exclusive of preamble, only in good frames
21327  *
21328  * Field Access Macros:
21329  *
21330  */
21331 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
21332 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_LSB 0
21333 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
21334 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_MSB 31
21335 /* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
21336 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_WIDTH 32
21337 /* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
21338 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET_MSK 0xffffffff
21339 /* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
21340 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_CLR_MSK 0x00000000
21341 /* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
21342 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_RESET 0x0
21343 /* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT field value from a register. */
21344 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21345 /* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value suitable for setting the register. */
21346 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21347 
21348 #ifndef __ASSEMBLY__
21349 /*
21350  * WARNING: The C register and register group struct declarations are provided for
21351  * convenience and illustrative purposes. They should, however, be used with
21352  * caution as the C language standard provides no guarantees about the alignment or
21353  * atomicity of device memory accesses. The recommended practice for writing
21354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21355  * alt_write_word() functions.
21356  *
21357  * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G.
21358  */
21359 struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s
21360 {
21361  const uint32_t cnt : 32; /* rxoctetcount_g */
21362 };
21363 
21364 /* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G. */
21365 typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s ALT_EMAC_GMAC_RXOCTETCOUNT_G_t;
21366 #endif /* __ASSEMBLY__ */
21367 
21368 /* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register from the beginning of the component. */
21369 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST 0x188
21370 /* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register. */
21371 #define ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST))
21372 
21373 /*
21374  * Register : Register 99 (rxbroadcastframes_g Register) - rxbroadcastframes_g
21375  *
21376  * Number of good broadcast frames received
21377  *
21378  * Register Layout
21379  *
21380  * Bits | Access | Reset | Description
21381  * :-------|:-------|:------|:--------------------
21382  * [31:0] | R | 0x0 | rxbroadcastframes_g
21383  *
21384  */
21385 /*
21386  * Field : rxbroadcastframes_g - cnt
21387  *
21388  * Number of good broadcast frames received
21389  *
21390  * Field Access Macros:
21391  *
21392  */
21393 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
21394 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_LSB 0
21395 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
21396 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_MSB 31
21397 /* The width in bits of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
21398 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_WIDTH 32
21399 /* The mask used to set the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
21400 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET_MSK 0xffffffff
21401 /* The mask used to clear the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
21402 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_CLR_MSK 0x00000000
21403 /* The reset value of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
21404 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_RESET 0x0
21405 /* Extracts the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT field value from a register. */
21406 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21407 /* Produces a ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value suitable for setting the register. */
21408 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21409 
21410 #ifndef __ASSEMBLY__
21411 /*
21412  * WARNING: The C register and register group struct declarations are provided for
21413  * convenience and illustrative purposes. They should, however, be used with
21414  * caution as the C language standard provides no guarantees about the alignment or
21415  * atomicity of device memory accesses. The recommended practice for writing
21416  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21417  * alt_write_word() functions.
21418  *
21419  * The struct declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G.
21420  */
21421 struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s
21422 {
21423  const uint32_t cnt : 32; /* rxbroadcastframes_g */
21424 };
21425 
21426 /* The typedef declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G. */
21427 typedef volatile struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s ALT_EMAC_GMAC_RXBCASTFRMS_G_t;
21428 #endif /* __ASSEMBLY__ */
21429 
21430 /* The byte offset of the ALT_EMAC_GMAC_RXBCASTFRMS_G register from the beginning of the component. */
21431 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST 0x18c
21432 /* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register. */
21433 #define ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST))
21434 
21435 /*
21436  * Register : Register 100 (rxmulticastframes_g Register) - rxmulticastframes_g
21437  *
21438  * Number of good multicast frames received
21439  *
21440  * Register Layout
21441  *
21442  * Bits | Access | Reset | Description
21443  * :-------|:-------|:------|:--------------------
21444  * [31:0] | R | 0x0 | rxmulticastframes_g
21445  *
21446  */
21447 /*
21448  * Field : rxmulticastframes_g - cnt
21449  *
21450  * Number of good multicast frames received
21451  *
21452  * Field Access Macros:
21453  *
21454  */
21455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
21456 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_LSB 0
21457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
21458 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_MSB 31
21459 /* The width in bits of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
21460 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_WIDTH 32
21461 /* The mask used to set the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
21462 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET_MSK 0xffffffff
21463 /* The mask used to clear the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
21464 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_CLR_MSK 0x00000000
21465 /* The reset value of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
21466 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_RESET 0x0
21467 /* Extracts the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT field value from a register. */
21468 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21469 /* Produces a ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value suitable for setting the register. */
21470 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21471 
21472 #ifndef __ASSEMBLY__
21473 /*
21474  * WARNING: The C register and register group struct declarations are provided for
21475  * convenience and illustrative purposes. They should, however, be used with
21476  * caution as the C language standard provides no guarantees about the alignment or
21477  * atomicity of device memory accesses. The recommended practice for writing
21478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21479  * alt_write_word() functions.
21480  *
21481  * The struct declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G.
21482  */
21483 struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s
21484 {
21485  const uint32_t cnt : 32; /* rxmulticastframes_g */
21486 };
21487 
21488 /* The typedef declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G. */
21489 typedef volatile struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s ALT_EMAC_GMAC_RXMCASTFRMS_G_t;
21490 #endif /* __ASSEMBLY__ */
21491 
21492 /* The byte offset of the ALT_EMAC_GMAC_RXMCASTFRMS_G register from the beginning of the component. */
21493 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST 0x190
21494 /* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register. */
21495 #define ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST))
21496 
21497 /*
21498  * Register : Register 101 (rxcrcerror Register) - rxcrcerror
21499  *
21500  * Number of frames received with CRC error
21501  *
21502  * Register Layout
21503  *
21504  * Bits | Access | Reset | Description
21505  * :-------|:-------|:------|:------------
21506  * [31:0] | R | 0x0 | rxcrcerror
21507  *
21508  */
21509 /*
21510  * Field : rxcrcerror - cnt
21511  *
21512  * Number of frames received with CRC error
21513  *
21514  * Field Access Macros:
21515  *
21516  */
21517 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
21518 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_LSB 0
21519 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
21520 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_MSB 31
21521 /* The width in bits of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
21522 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_WIDTH 32
21523 /* The mask used to set the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
21524 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET_MSK 0xffffffff
21525 /* The mask used to clear the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
21526 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_CLR_MSK 0x00000000
21527 /* The reset value of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
21528 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_RESET 0x0
21529 /* Extracts the ALT_EMAC_GMAC_RXCRCERROR_CNT field value from a register. */
21530 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21531 /* Produces a ALT_EMAC_GMAC_RXCRCERROR_CNT register field value suitable for setting the register. */
21532 #define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
21533 
21534 #ifndef __ASSEMBLY__
21535 /*
21536  * WARNING: The C register and register group struct declarations are provided for
21537  * convenience and illustrative purposes. They should, however, be used with
21538  * caution as the C language standard provides no guarantees about the alignment or
21539  * atomicity of device memory accesses. The recommended practice for writing
21540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21541  * alt_write_word() functions.
21542  *
21543  * The struct declaration for register ALT_EMAC_GMAC_RXCRCERROR.
21544  */
21545 struct ALT_EMAC_GMAC_RXCRCERROR_s
21546 {
21547  const uint32_t cnt : 32; /* rxcrcerror */
21548 };
21549 
21550 /* The typedef declaration for register ALT_EMAC_GMAC_RXCRCERROR. */
21551 typedef volatile struct ALT_EMAC_GMAC_RXCRCERROR_s ALT_EMAC_GMAC_RXCRCERROR_t;
21552 #endif /* __ASSEMBLY__ */
21553 
21554 /* The byte offset of the ALT_EMAC_GMAC_RXCRCERROR register from the beginning of the component. */
21555 #define ALT_EMAC_GMAC_RXCRCERROR_OFST 0x194
21556 /* The address of the ALT_EMAC_GMAC_RXCRCERROR register. */
21557 #define ALT_EMAC_GMAC_RXCRCERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCRCERROR_OFST))
21558 
21559 /*
21560  * Register : Register 102 (rxalignmenterror Register) - rxalignmenterror
21561  *
21562  * Number of frames received with alignment (dribble) error. Valid only in 10/100
21563  * mode
21564  *
21565  * Register Layout
21566  *
21567  * Bits | Access | Reset | Description
21568  * :-------|:-------|:------|:-----------------
21569  * [31:0] | R | 0x0 | rxalignmenterror
21570  *
21571  */
21572 /*
21573  * Field : rxalignmenterror - cnt
21574  *
21575  * Number of frames received with alignment (dribble) error. Valid only in 10/100
21576  * mode
21577  *
21578  * Field Access Macros:
21579  *
21580  */
21581 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
21582 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_LSB 0
21583 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
21584 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_MSB 31
21585 /* The width in bits of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
21586 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_WIDTH 32
21587 /* The mask used to set the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
21588 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET_MSK 0xffffffff
21589 /* The mask used to clear the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
21590 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_CLR_MSK 0x00000000
21591 /* The reset value of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
21592 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_RESET 0x0
21593 /* Extracts the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT field value from a register. */
21594 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21595 /* Produces a ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value suitable for setting the register. */
21596 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
21597 
21598 #ifndef __ASSEMBLY__
21599 /*
21600  * WARNING: The C register and register group struct declarations are provided for
21601  * convenience and illustrative purposes. They should, however, be used with
21602  * caution as the C language standard provides no guarantees about the alignment or
21603  * atomicity of device memory accesses. The recommended practice for writing
21604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21605  * alt_write_word() functions.
21606  *
21607  * The struct declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR.
21608  */
21609 struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s
21610 {
21611  const uint32_t cnt : 32; /* rxalignmenterror */
21612 };
21613 
21614 /* The typedef declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR. */
21615 typedef volatile struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s ALT_EMAC_GMAC_RXALIGNMENTERROR_t;
21616 #endif /* __ASSEMBLY__ */
21617 
21618 /* The byte offset of the ALT_EMAC_GMAC_RXALIGNMENTERROR register from the beginning of the component. */
21619 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST 0x198
21620 /* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register. */
21621 #define ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST))
21622 
21623 /*
21624  * Register : Register 103 (rxrunterror Register) - rxrunterror
21625  *
21626  * Number of frames received with runt (<64 bytes and CRC error) error
21627  *
21628  * Register Layout
21629  *
21630  * Bits | Access | Reset | Description
21631  * :-------|:-------|:------|:------------
21632  * [31:0] | R | 0x0 | rxrunterror
21633  *
21634  */
21635 /*
21636  * Field : rxrunterror - cnt
21637  *
21638  * Number of frames received with runt (<64 bytes and CRC error) error
21639  *
21640  * Field Access Macros:
21641  *
21642  */
21643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
21644 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_LSB 0
21645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
21646 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_MSB 31
21647 /* The width in bits of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
21648 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_WIDTH 32
21649 /* The mask used to set the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
21650 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET_MSK 0xffffffff
21651 /* The mask used to clear the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
21652 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_CLR_MSK 0x00000000
21653 /* The reset value of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
21654 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_RESET 0x0
21655 /* Extracts the ALT_EMAC_GMAC_RXRUNTERROR_CNT field value from a register. */
21656 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21657 /* Produces a ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value suitable for setting the register. */
21658 #define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
21659 
21660 #ifndef __ASSEMBLY__
21661 /*
21662  * WARNING: The C register and register group struct declarations are provided for
21663  * convenience and illustrative purposes. They should, however, be used with
21664  * caution as the C language standard provides no guarantees about the alignment or
21665  * atomicity of device memory accesses. The recommended practice for writing
21666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21667  * alt_write_word() functions.
21668  *
21669  * The struct declaration for register ALT_EMAC_GMAC_RXRUNTERROR.
21670  */
21671 struct ALT_EMAC_GMAC_RXRUNTERROR_s
21672 {
21673  const uint32_t cnt : 32; /* rxrunterror */
21674 };
21675 
21676 /* The typedef declaration for register ALT_EMAC_GMAC_RXRUNTERROR. */
21677 typedef volatile struct ALT_EMAC_GMAC_RXRUNTERROR_s ALT_EMAC_GMAC_RXRUNTERROR_t;
21678 #endif /* __ASSEMBLY__ */
21679 
21680 /* The byte offset of the ALT_EMAC_GMAC_RXRUNTERROR register from the beginning of the component. */
21681 #define ALT_EMAC_GMAC_RXRUNTERROR_OFST 0x19c
21682 /* The address of the ALT_EMAC_GMAC_RXRUNTERROR register. */
21683 #define ALT_EMAC_GMAC_RXRUNTERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRUNTERROR_OFST))
21684 
21685 /*
21686  * Register : Register 104 (rxjabbererror Register) - rxjabbererror
21687  *
21688  * Number of giant frames received with length (including CRC) greater than 1,518
21689  * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is
21690  * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged)
21691  * are considered as giant frames
21692  *
21693  * Register Layout
21694  *
21695  * Bits | Access | Reset | Description
21696  * :-------|:-------|:------|:--------------
21697  * [31:0] | R | 0x0 | rxjabbererror
21698  *
21699  */
21700 /*
21701  * Field : rxjabbererror - cnt
21702  *
21703  * Number of giant frames received with length (including CRC) greater than 1,518
21704  * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is
21705  * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged)
21706  * are considered as giant frames
21707  *
21708  * Field Access Macros:
21709  *
21710  */
21711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
21712 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_LSB 0
21713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
21714 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_MSB 31
21715 /* The width in bits of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
21716 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_WIDTH 32
21717 /* The mask used to set the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
21718 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET_MSK 0xffffffff
21719 /* The mask used to clear the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
21720 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_CLR_MSK 0x00000000
21721 /* The reset value of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
21722 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_RESET 0x0
21723 /* Extracts the ALT_EMAC_GMAC_RXJABBERERROR_CNT field value from a register. */
21724 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21725 /* Produces a ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value suitable for setting the register. */
21726 #define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
21727 
21728 #ifndef __ASSEMBLY__
21729 /*
21730  * WARNING: The C register and register group struct declarations are provided for
21731  * convenience and illustrative purposes. They should, however, be used with
21732  * caution as the C language standard provides no guarantees about the alignment or
21733  * atomicity of device memory accesses. The recommended practice for writing
21734  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21735  * alt_write_word() functions.
21736  *
21737  * The struct declaration for register ALT_EMAC_GMAC_RXJABBERERROR.
21738  */
21739 struct ALT_EMAC_GMAC_RXJABBERERROR_s
21740 {
21741  const uint32_t cnt : 32; /* rxjabbererror */
21742 };
21743 
21744 /* The typedef declaration for register ALT_EMAC_GMAC_RXJABBERERROR. */
21745 typedef volatile struct ALT_EMAC_GMAC_RXJABBERERROR_s ALT_EMAC_GMAC_RXJABBERERROR_t;
21746 #endif /* __ASSEMBLY__ */
21747 
21748 /* The byte offset of the ALT_EMAC_GMAC_RXJABBERERROR register from the beginning of the component. */
21749 #define ALT_EMAC_GMAC_RXJABBERERROR_OFST 0x1a0
21750 /* The address of the ALT_EMAC_GMAC_RXJABBERERROR register. */
21751 #define ALT_EMAC_GMAC_RXJABBERERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXJABBERERROR_OFST))
21752 
21753 /*
21754  * Register : Register 105 (rxundersize_g Register) - rxundersize_g
21755  *
21756  * Number of frames received with length less than 64 bytes, without any errors
21757  *
21758  * Register Layout
21759  *
21760  * Bits | Access | Reset | Description
21761  * :-------|:-------|:------|:--------------
21762  * [31:0] | R | 0x0 | rxundersize_g
21763  *
21764  */
21765 /*
21766  * Field : rxundersize_g - cnt
21767  *
21768  * Number of frames received with length less than 64 bytes, without any errors
21769  *
21770  * Field Access Macros:
21771  *
21772  */
21773 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
21774 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_LSB 0
21775 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
21776 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_MSB 31
21777 /* The width in bits of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
21778 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_WIDTH 32
21779 /* The mask used to set the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
21780 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET_MSK 0xffffffff
21781 /* The mask used to clear the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
21782 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_CLR_MSK 0x00000000
21783 /* The reset value of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
21784 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_RESET 0x0
21785 /* Extracts the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT field value from a register. */
21786 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21787 /* Produces a ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value suitable for setting the register. */
21788 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21789 
21790 #ifndef __ASSEMBLY__
21791 /*
21792  * WARNING: The C register and register group struct declarations are provided for
21793  * convenience and illustrative purposes. They should, however, be used with
21794  * caution as the C language standard provides no guarantees about the alignment or
21795  * atomicity of device memory accesses. The recommended practice for writing
21796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21797  * alt_write_word() functions.
21798  *
21799  * The struct declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G.
21800  */
21801 struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s
21802 {
21803  const uint32_t cnt : 32; /* rxundersize_g */
21804 };
21805 
21806 /* The typedef declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G. */
21807 typedef volatile struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s ALT_EMAC_GMAC_RXUNDERSIZE_G_t;
21808 #endif /* __ASSEMBLY__ */
21809 
21810 /* The byte offset of the ALT_EMAC_GMAC_RXUNDERSIZE_G register from the beginning of the component. */
21811 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST 0x1a4
21812 /* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register. */
21813 #define ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST))
21814 
21815 /*
21816  * Register : Register 106 (rxoversize_g Register) - rxoversize_g
21817  *
21818  * Number of frames received with length greater than the maxsize (1,518 or 1,522
21819  * for VLAN tagged frames), without errors
21820  *
21821  * Register Layout
21822  *
21823  * Bits | Access | Reset | Description
21824  * :-------|:-------|:------|:-------------
21825  * [31:0] | R | 0x0 | rxoversize_g
21826  *
21827  */
21828 /*
21829  * Field : rxoversize_g - cnt
21830  *
21831  * Number of frames received with length greater than the maxsize (1,518 or 1,522
21832  * for VLAN tagged frames), without errors
21833  *
21834  * Field Access Macros:
21835  *
21836  */
21837 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
21838 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_LSB 0
21839 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
21840 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_MSB 31
21841 /* The width in bits of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
21842 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_WIDTH 32
21843 /* The mask used to set the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
21844 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET_MSK 0xffffffff
21845 /* The mask used to clear the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
21846 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_CLR_MSK 0x00000000
21847 /* The reset value of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
21848 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_RESET 0x0
21849 /* Extracts the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT field value from a register. */
21850 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21851 /* Produces a ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value suitable for setting the register. */
21852 #define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
21853 
21854 #ifndef __ASSEMBLY__
21855 /*
21856  * WARNING: The C register and register group struct declarations are provided for
21857  * convenience and illustrative purposes. They should, however, be used with
21858  * caution as the C language standard provides no guarantees about the alignment or
21859  * atomicity of device memory accesses. The recommended practice for writing
21860  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21861  * alt_write_word() functions.
21862  *
21863  * The struct declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G.
21864  */
21865 struct ALT_EMAC_GMAC_RXOVERSIZE_G_s
21866 {
21867  const uint32_t cnt : 32; /* rxoversize_g */
21868 };
21869 
21870 /* The typedef declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G. */
21871 typedef volatile struct ALT_EMAC_GMAC_RXOVERSIZE_G_s ALT_EMAC_GMAC_RXOVERSIZE_G_t;
21872 #endif /* __ASSEMBLY__ */
21873 
21874 /* The byte offset of the ALT_EMAC_GMAC_RXOVERSIZE_G register from the beginning of the component. */
21875 #define ALT_EMAC_GMAC_RXOVERSIZE_G_OFST 0x1a8
21876 /* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register. */
21877 #define ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOVERSIZE_G_OFST))
21878 
21879 /*
21880  * Register : Register 107 (rx64octets_gb Register) - rx64octets_gb
21881  *
21882  * Number of good and bad frames received with length 64 bytes, exclusive of
21883  * preamble
21884  *
21885  * Register Layout
21886  *
21887  * Bits | Access | Reset | Description
21888  * :-------|:-------|:------|:--------------
21889  * [31:0] | R | 0x0 | rx64octets_gb
21890  *
21891  */
21892 /*
21893  * Field : rx64octets_gb - cnt
21894  *
21895  * Number of good and bad frames received with length 64 bytes, exclusive of
21896  * preamble
21897  *
21898  * Field Access Macros:
21899  *
21900  */
21901 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
21902 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_LSB 0
21903 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
21904 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_MSB 31
21905 /* The width in bits of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
21906 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_WIDTH 32
21907 /* The mask used to set the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
21908 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET_MSK 0xffffffff
21909 /* The mask used to clear the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
21910 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_CLR_MSK 0x00000000
21911 /* The reset value of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
21912 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_RESET 0x0
21913 /* Extracts the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT field value from a register. */
21914 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21915 /* Produces a ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value suitable for setting the register. */
21916 #define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21917 
21918 #ifndef __ASSEMBLY__
21919 /*
21920  * WARNING: The C register and register group struct declarations are provided for
21921  * convenience and illustrative purposes. They should, however, be used with
21922  * caution as the C language standard provides no guarantees about the alignment or
21923  * atomicity of device memory accesses. The recommended practice for writing
21924  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21925  * alt_write_word() functions.
21926  *
21927  * The struct declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB.
21928  */
21929 struct ALT_EMAC_GMAC_RX64OCTETS_GB_s
21930 {
21931  const uint32_t cnt : 32; /* rx64octets_gb */
21932 };
21933 
21934 /* The typedef declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB. */
21935 typedef volatile struct ALT_EMAC_GMAC_RX64OCTETS_GB_s ALT_EMAC_GMAC_RX64OCTETS_GB_t;
21936 #endif /* __ASSEMBLY__ */
21937 
21938 /* The byte offset of the ALT_EMAC_GMAC_RX64OCTETS_GB register from the beginning of the component. */
21939 #define ALT_EMAC_GMAC_RX64OCTETS_GB_OFST 0x1ac
21940 /* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register. */
21941 #define ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX64OCTETS_GB_OFST))
21942 
21943 /*
21944  * Register : Register 108 (rx65to127octets_gb Register) - rx65to127octets_gb
21945  *
21946  * Number of good and bad frames received with length between 65 and 127
21947  * (inclusive) bytes, exclusive of preamble
21948  *
21949  * Register Layout
21950  *
21951  * Bits | Access | Reset | Description
21952  * :-------|:-------|:------|:-------------------
21953  * [31:0] | R | 0x0 | rx65to127octets_gb
21954  *
21955  */
21956 /*
21957  * Field : rx65to127octets_gb - cnt
21958  *
21959  * Number of good and bad frames received with length between 65 and 127
21960  * (inclusive) bytes, exclusive of preamble
21961  *
21962  * Field Access Macros:
21963  *
21964  */
21965 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
21966 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_LSB 0
21967 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
21968 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_MSB 31
21969 /* The width in bits of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
21970 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_WIDTH 32
21971 /* The mask used to set the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
21972 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET_MSK 0xffffffff
21973 /* The mask used to clear the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
21974 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_CLR_MSK 0x00000000
21975 /* The reset value of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
21976 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_RESET 0x0
21977 /* Extracts the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT field value from a register. */
21978 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
21979 /* Produces a ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
21980 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
21981 
21982 #ifndef __ASSEMBLY__
21983 /*
21984  * WARNING: The C register and register group struct declarations are provided for
21985  * convenience and illustrative purposes. They should, however, be used with
21986  * caution as the C language standard provides no guarantees about the alignment or
21987  * atomicity of device memory accesses. The recommended practice for writing
21988  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21989  * alt_write_word() functions.
21990  *
21991  * The struct declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB.
21992  */
21993 struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s
21994 {
21995  const uint32_t cnt : 32; /* rx65to127octets_gb */
21996 };
21997 
21998 /* The typedef declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB. */
21999 typedef volatile struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t;
22000 #endif /* __ASSEMBLY__ */
22001 
22002 /* The byte offset of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register from the beginning of the component. */
22003 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST 0x1b0
22004 /* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register. */
22005 #define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST))
22006 
22007 /*
22008  * Register : Register 109 (rx128to255octets_gb Register) - rx128to255octets_gb
22009  *
22010  * Number of good and bad frames received with length between 128 and 255
22011  * (inclusive) bytes, exclusive of preamble
22012  *
22013  * Register Layout
22014  *
22015  * Bits | Access | Reset | Description
22016  * :-------|:-------|:------|:--------------------
22017  * [31:0] | R | 0x0 | rx128to255octets_gb
22018  *
22019  */
22020 /*
22021  * Field : rx128to255octets_gb - cnt
22022  *
22023  * Number of good and bad frames received with length between 128 and 255
22024  * (inclusive) bytes, exclusive of preamble
22025  *
22026  * Field Access Macros:
22027  *
22028  */
22029 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
22030 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_LSB 0
22031 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
22032 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_MSB 31
22033 /* The width in bits of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
22034 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_WIDTH 32
22035 /* The mask used to set the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
22036 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET_MSK 0xffffffff
22037 /* The mask used to clear the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
22038 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_CLR_MSK 0x00000000
22039 /* The reset value of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
22040 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_RESET 0x0
22041 /* Extracts the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT field value from a register. */
22042 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22043 /* Produces a ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
22044 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22045 
22046 #ifndef __ASSEMBLY__
22047 /*
22048  * WARNING: The C register and register group struct declarations are provided for
22049  * convenience and illustrative purposes. They should, however, be used with
22050  * caution as the C language standard provides no guarantees about the alignment or
22051  * atomicity of device memory accesses. The recommended practice for writing
22052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22053  * alt_write_word() functions.
22054  *
22055  * The struct declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB.
22056  */
22057 struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s
22058 {
22059  const uint32_t cnt : 32; /* rx128to255octets_gb */
22060 };
22061 
22062 /* The typedef declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB. */
22063 typedef volatile struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t;
22064 #endif /* __ASSEMBLY__ */
22065 
22066 /* The byte offset of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register from the beginning of the component. */
22067 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST 0x1b4
22068 /* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register. */
22069 #define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST))
22070 
22071 /*
22072  * Register : Register 110 (rx256to511octets_gb Register) - rx256to511octets_gb
22073  *
22074  * Number of good and bad frames received with length between 256 and 511
22075  * (inclusive) bytes, exclusive of preamble
22076  *
22077  * Register Layout
22078  *
22079  * Bits | Access | Reset | Description
22080  * :-------|:-------|:------|:--------------------
22081  * [31:0] | R | 0x0 | rx256to511octets_gb
22082  *
22083  */
22084 /*
22085  * Field : rx256to511octets_gb - cnt
22086  *
22087  * Number of good and bad frames received with length between 256 and 511
22088  * (inclusive) bytes, exclusive of preamble
22089  *
22090  * Field Access Macros:
22091  *
22092  */
22093 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
22094 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_LSB 0
22095 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
22096 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_MSB 31
22097 /* The width in bits of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
22098 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_WIDTH 32
22099 /* The mask used to set the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
22100 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET_MSK 0xffffffff
22101 /* The mask used to clear the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
22102 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_CLR_MSK 0x00000000
22103 /* The reset value of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
22104 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_RESET 0x0
22105 /* Extracts the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT field value from a register. */
22106 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22107 /* Produces a ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
22108 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22109 
22110 #ifndef __ASSEMBLY__
22111 /*
22112  * WARNING: The C register and register group struct declarations are provided for
22113  * convenience and illustrative purposes. They should, however, be used with
22114  * caution as the C language standard provides no guarantees about the alignment or
22115  * atomicity of device memory accesses. The recommended practice for writing
22116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22117  * alt_write_word() functions.
22118  *
22119  * The struct declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB.
22120  */
22121 struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s
22122 {
22123  const uint32_t cnt : 32; /* rx256to511octets_gb */
22124 };
22125 
22126 /* The typedef declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB. */
22127 typedef volatile struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t;
22128 #endif /* __ASSEMBLY__ */
22129 
22130 /* The byte offset of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register from the beginning of the component. */
22131 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST 0x1b8
22132 /* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register. */
22133 #define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST))
22134 
22135 /*
22136  * Register : Register 111 (rx512to1023octets_gb Register) - rx512to1023octets_gb
22137  *
22138  * Number of good and bad frames received with length between 512 and 1,023
22139  * (inclusive) bytes, exclusive of preamble
22140  *
22141  * Register Layout
22142  *
22143  * Bits | Access | Reset | Description
22144  * :-------|:-------|:------|:---------------------
22145  * [31:0] | R | 0x0 | rx512to1023octets_gb
22146  *
22147  */
22148 /*
22149  * Field : rx512to1023octets_gb - cnt
22150  *
22151  * Number of good and bad frames received with length between 512 and 1,023
22152  * (inclusive) bytes, exclusive of preamble
22153  *
22154  * Field Access Macros:
22155  *
22156  */
22157 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
22158 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_LSB 0
22159 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
22160 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_MSB 31
22161 /* The width in bits of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
22162 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_WIDTH 32
22163 /* The mask used to set the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
22164 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET_MSK 0xffffffff
22165 /* The mask used to clear the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
22166 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_CLR_MSK 0x00000000
22167 /* The reset value of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
22168 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_RESET 0x0
22169 /* Extracts the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT field value from a register. */
22170 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22171 /* Produces a ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
22172 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22173 
22174 #ifndef __ASSEMBLY__
22175 /*
22176  * WARNING: The C register and register group struct declarations are provided for
22177  * convenience and illustrative purposes. They should, however, be used with
22178  * caution as the C language standard provides no guarantees about the alignment or
22179  * atomicity of device memory accesses. The recommended practice for writing
22180  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22181  * alt_write_word() functions.
22182  *
22183  * The struct declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB.
22184  */
22185 struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s
22186 {
22187  const uint32_t cnt : 32; /* rx512to1023octets_gb */
22188 };
22189 
22190 /* The typedef declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB. */
22191 typedef volatile struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t;
22192 #endif /* __ASSEMBLY__ */
22193 
22194 /* The byte offset of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register from the beginning of the component. */
22195 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST 0x1bc
22196 /* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register. */
22197 #define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST))
22198 
22199 /*
22200  * Register : Register 112 (rx1024tomaxoctets_gb Register) - rx1024tomaxoctets_gb
22201  *
22202  * Number of good and bad frames received with length between 1,024 and maxsize
22203  * (inclusive) bytes, exclusive of preamble and retried frames
22204  *
22205  * Register Layout
22206  *
22207  * Bits | Access | Reset | Description
22208  * :-------|:-------|:------|:---------------------
22209  * [31:0] | R | 0x0 | rx1024tomaxoctets_gb
22210  *
22211  */
22212 /*
22213  * Field : rx1024tomaxoctets_gb - cnt
22214  *
22215  * Number of good and bad frames received with length between 1,024 and maxsize
22216  * (inclusive) bytes, exclusive of preamble and retried frames
22217  *
22218  * Field Access Macros:
22219  *
22220  */
22221 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
22222 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_LSB 0
22223 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
22224 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_MSB 31
22225 /* The width in bits of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
22226 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_WIDTH 32
22227 /* The mask used to set the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
22228 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET_MSK 0xffffffff
22229 /* The mask used to clear the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
22230 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_CLR_MSK 0x00000000
22231 /* The reset value of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
22232 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_RESET 0x0
22233 /* Extracts the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT field value from a register. */
22234 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22235 /* Produces a ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
22236 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22237 
22238 #ifndef __ASSEMBLY__
22239 /*
22240  * WARNING: The C register and register group struct declarations are provided for
22241  * convenience and illustrative purposes. They should, however, be used with
22242  * caution as the C language standard provides no guarantees about the alignment or
22243  * atomicity of device memory accesses. The recommended practice for writing
22244  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22245  * alt_write_word() functions.
22246  *
22247  * The struct declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB.
22248  */
22249 struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s
22250 {
22251  const uint32_t cnt : 32; /* rx1024tomaxoctets_gb */
22252 };
22253 
22254 /* The typedef declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB. */
22255 typedef volatile struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t;
22256 #endif /* __ASSEMBLY__ */
22257 
22258 /* The byte offset of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register from the beginning of the component. */
22259 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST 0x1c0
22260 /* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register. */
22261 #define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST))
22262 
22263 /*
22264  * Register : Register 113 (rxunicastframes_g Register) - rxunicastframes_g
22265  *
22266  * Number of good unicast frames received
22267  *
22268  * Register Layout
22269  *
22270  * Bits | Access | Reset | Description
22271  * :-------|:-------|:------|:------------------
22272  * [31:0] | R | 0x0 | rxunicastframes_g
22273  *
22274  */
22275 /*
22276  * Field : rxunicastframes_g - cnt
22277  *
22278  * Number of good unicast frames received
22279  *
22280  * Field Access Macros:
22281  *
22282  */
22283 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
22284 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_LSB 0
22285 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
22286 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_MSB 31
22287 /* The width in bits of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
22288 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_WIDTH 32
22289 /* The mask used to set the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
22290 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET_MSK 0xffffffff
22291 /* The mask used to clear the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
22292 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_CLR_MSK 0x00000000
22293 /* The reset value of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
22294 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_RESET 0x0
22295 /* Extracts the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT field value from a register. */
22296 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22297 /* Produces a ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value suitable for setting the register. */
22298 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
22299 
22300 #ifndef __ASSEMBLY__
22301 /*
22302  * WARNING: The C register and register group struct declarations are provided for
22303  * convenience and illustrative purposes. They should, however, be used with
22304  * caution as the C language standard provides no guarantees about the alignment or
22305  * atomicity of device memory accesses. The recommended practice for writing
22306  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22307  * alt_write_word() functions.
22308  *
22309  * The struct declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G.
22310  */
22311 struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s
22312 {
22313  const uint32_t cnt : 32; /* rxunicastframes_g */
22314 };
22315 
22316 /* The typedef declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G. */
22317 typedef volatile struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s ALT_EMAC_GMAC_RXUNICASTFRMS_G_t;
22318 #endif /* __ASSEMBLY__ */
22319 
22320 /* The byte offset of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register from the beginning of the component. */
22321 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST 0x1c4
22322 /* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register. */
22323 #define ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST))
22324 
22325 /*
22326  * Register : Register 114 (rxlengtherror Register) - rxlengtherror
22327  *
22328  * Number of frames received with length error (length type field not equal to
22329  * frame size), for all frames with valid length field
22330  *
22331  * Register Layout
22332  *
22333  * Bits | Access | Reset | Description
22334  * :-------|:-------|:------|:--------------
22335  * [31:0] | R | 0x0 | rxlengtherror
22336  *
22337  */
22338 /*
22339  * Field : rxlengtherror - cnt
22340  *
22341  * Number of frames received with length error (length type field not equal to
22342  * frame size), for all frames with valid length field
22343  *
22344  * Field Access Macros:
22345  *
22346  */
22347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
22348 #define ALT_EMAC_GMAC_RXLENERROR_CNT_LSB 0
22349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
22350 #define ALT_EMAC_GMAC_RXLENERROR_CNT_MSB 31
22351 /* The width in bits of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
22352 #define ALT_EMAC_GMAC_RXLENERROR_CNT_WIDTH 32
22353 /* The mask used to set the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
22354 #define ALT_EMAC_GMAC_RXLENERROR_CNT_SET_MSK 0xffffffff
22355 /* The mask used to clear the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
22356 #define ALT_EMAC_GMAC_RXLENERROR_CNT_CLR_MSK 0x00000000
22357 /* The reset value of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
22358 #define ALT_EMAC_GMAC_RXLENERROR_CNT_RESET 0x0
22359 /* Extracts the ALT_EMAC_GMAC_RXLENERROR_CNT field value from a register. */
22360 #define ALT_EMAC_GMAC_RXLENERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22361 /* Produces a ALT_EMAC_GMAC_RXLENERROR_CNT register field value suitable for setting the register. */
22362 #define ALT_EMAC_GMAC_RXLENERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
22363 
22364 #ifndef __ASSEMBLY__
22365 /*
22366  * WARNING: The C register and register group struct declarations are provided for
22367  * convenience and illustrative purposes. They should, however, be used with
22368  * caution as the C language standard provides no guarantees about the alignment or
22369  * atomicity of device memory accesses. The recommended practice for writing
22370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22371  * alt_write_word() functions.
22372  *
22373  * The struct declaration for register ALT_EMAC_GMAC_RXLENERROR.
22374  */
22375 struct ALT_EMAC_GMAC_RXLENERROR_s
22376 {
22377  const uint32_t cnt : 32; /* rxlengtherror */
22378 };
22379 
22380 /* The typedef declaration for register ALT_EMAC_GMAC_RXLENERROR. */
22381 typedef volatile struct ALT_EMAC_GMAC_RXLENERROR_s ALT_EMAC_GMAC_RXLENERROR_t;
22382 #endif /* __ASSEMBLY__ */
22383 
22384 /* The byte offset of the ALT_EMAC_GMAC_RXLENERROR register from the beginning of the component. */
22385 #define ALT_EMAC_GMAC_RXLENERROR_OFST 0x1c8
22386 /* The address of the ALT_EMAC_GMAC_RXLENERROR register. */
22387 #define ALT_EMAC_GMAC_RXLENERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXLENERROR_OFST))
22388 
22389 /*
22390  * Register : Register 115 (rxoutofrangetype Register) - rxoutofrangetype
22391  *
22392  * Number of frames received with length field not equal to the valid frame size
22393  * (greater than 1,500 but less than 1,536)
22394  *
22395  * Register Layout
22396  *
22397  * Bits | Access | Reset | Description
22398  * :-------|:-------|:------|:-----------------
22399  * [31:0] | R | 0x0 | rxoutofrangetype
22400  *
22401  */
22402 /*
22403  * Field : rxoutofrangetype - cnt
22404  *
22405  * Number of frames received with length field not equal to the valid frame size
22406  * (greater than 1,500 but less than 1,536)
22407  *
22408  * Field Access Macros:
22409  *
22410  */
22411 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
22412 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_LSB 0
22413 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
22414 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_MSB 31
22415 /* The width in bits of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
22416 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_WIDTH 32
22417 /* The mask used to set the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
22418 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET_MSK 0xffffffff
22419 /* The mask used to clear the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
22420 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_CLR_MSK 0x00000000
22421 /* The reset value of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
22422 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_RESET 0x0
22423 /* Extracts the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT field value from a register. */
22424 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22425 /* Produces a ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value suitable for setting the register. */
22426 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET(value) (((value) << 0) & 0xffffffff)
22427 
22428 #ifndef __ASSEMBLY__
22429 /*
22430  * WARNING: The C register and register group struct declarations are provided for
22431  * convenience and illustrative purposes. They should, however, be used with
22432  * caution as the C language standard provides no guarantees about the alignment or
22433  * atomicity of device memory accesses. The recommended practice for writing
22434  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22435  * alt_write_word() functions.
22436  *
22437  * The struct declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE.
22438  */
22439 struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s
22440 {
22441  const uint32_t cnt : 32; /* rxoutofrangetype */
22442 };
22443 
22444 /* The typedef declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE. */
22445 typedef volatile struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t;
22446 #endif /* __ASSEMBLY__ */
22447 
22448 /* The byte offset of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register from the beginning of the component. */
22449 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST 0x1cc
22450 /* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register. */
22451 #define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST))
22452 
22453 /*
22454  * Register : Register 116 (rxpauseframes Register) - rxpauseframes
22455  *
22456  * Number of good and valid PAUSE frames received
22457  *
22458  * Register Layout
22459  *
22460  * Bits | Access | Reset | Description
22461  * :-------|:-------|:------|:--------------
22462  * [31:0] | R | 0x0 | rxpauseframes
22463  *
22464  */
22465 /*
22466  * Field : rxpauseframes - cnt
22467  *
22468  * Number of good and valid PAUSE frames received
22469  *
22470  * Field Access Macros:
22471  *
22472  */
22473 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
22474 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_LSB 0
22475 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
22476 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_MSB 31
22477 /* The width in bits of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
22478 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_WIDTH 32
22479 /* The mask used to set the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
22480 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET_MSK 0xffffffff
22481 /* The mask used to clear the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
22482 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_CLR_MSK 0x00000000
22483 /* The reset value of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
22484 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_RESET 0x0
22485 /* Extracts the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT field value from a register. */
22486 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22487 /* Produces a ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value suitable for setting the register. */
22488 #define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
22489 
22490 #ifndef __ASSEMBLY__
22491 /*
22492  * WARNING: The C register and register group struct declarations are provided for
22493  * convenience and illustrative purposes. They should, however, be used with
22494  * caution as the C language standard provides no guarantees about the alignment or
22495  * atomicity of device memory accesses. The recommended practice for writing
22496  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22497  * alt_write_word() functions.
22498  *
22499  * The struct declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS.
22500  */
22501 struct ALT_EMAC_GMAC_RXPAUSEFRMS_s
22502 {
22503  const uint32_t cnt : 32; /* rxpauseframes */
22504 };
22505 
22506 /* The typedef declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS. */
22507 typedef volatile struct ALT_EMAC_GMAC_RXPAUSEFRMS_s ALT_EMAC_GMAC_RXPAUSEFRMS_t;
22508 #endif /* __ASSEMBLY__ */
22509 
22510 /* The byte offset of the ALT_EMAC_GMAC_RXPAUSEFRMS register from the beginning of the component. */
22511 #define ALT_EMAC_GMAC_RXPAUSEFRMS_OFST 0x1d0
22512 /* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register. */
22513 #define ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXPAUSEFRMS_OFST))
22514 
22515 /*
22516  * Register : Register 117 (rxfifooverflow Register) - rxfifooverflow
22517  *
22518  * Number of missed received frames due to FIFO overflow
22519  *
22520  * Register Layout
22521  *
22522  * Bits | Access | Reset | Description
22523  * :-------|:-------|:------|:---------------
22524  * [31:0] | R | 0x0 | rxfifooverflow
22525  *
22526  */
22527 /*
22528  * Field : rxfifooverflow - cnt
22529  *
22530  * Number of missed received frames due to FIFO overflow
22531  *
22532  * Field Access Macros:
22533  *
22534  */
22535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
22536 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_LSB 0
22537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
22538 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_MSB 31
22539 /* The width in bits of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
22540 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_WIDTH 32
22541 /* The mask used to set the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
22542 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET_MSK 0xffffffff
22543 /* The mask used to clear the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
22544 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_CLR_MSK 0x00000000
22545 /* The reset value of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
22546 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_RESET 0x0
22547 /* Extracts the ALT_EMAC_GMAC_RXFIFOOVF_CNT field value from a register. */
22548 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22549 /* Produces a ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value suitable for setting the register. */
22550 #define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET(value) (((value) << 0) & 0xffffffff)
22551 
22552 #ifndef __ASSEMBLY__
22553 /*
22554  * WARNING: The C register and register group struct declarations are provided for
22555  * convenience and illustrative purposes. They should, however, be used with
22556  * caution as the C language standard provides no guarantees about the alignment or
22557  * atomicity of device memory accesses. The recommended practice for writing
22558  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22559  * alt_write_word() functions.
22560  *
22561  * The struct declaration for register ALT_EMAC_GMAC_RXFIFOOVF.
22562  */
22563 struct ALT_EMAC_GMAC_RXFIFOOVF_s
22564 {
22565  const uint32_t cnt : 32; /* rxfifooverflow */
22566 };
22567 
22568 /* The typedef declaration for register ALT_EMAC_GMAC_RXFIFOOVF. */
22569 typedef volatile struct ALT_EMAC_GMAC_RXFIFOOVF_s ALT_EMAC_GMAC_RXFIFOOVF_t;
22570 #endif /* __ASSEMBLY__ */
22571 
22572 /* The byte offset of the ALT_EMAC_GMAC_RXFIFOOVF register from the beginning of the component. */
22573 #define ALT_EMAC_GMAC_RXFIFOOVF_OFST 0x1d4
22574 /* The address of the ALT_EMAC_GMAC_RXFIFOOVF register. */
22575 #define ALT_EMAC_GMAC_RXFIFOOVF_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFIFOOVF_OFST))
22576 
22577 /*
22578  * Register : Register 118 (rxvlanframes_gb Register) - rxvlanframes_gb
22579  *
22580  * Number of good and bad VLAN frames received
22581  *
22582  * Register Layout
22583  *
22584  * Bits | Access | Reset | Description
22585  * :-------|:-------|:------|:----------------
22586  * [31:0] | R | 0x0 | rxvlanframes_gb
22587  *
22588  */
22589 /*
22590  * Field : rxvlanframes_gb - cnt
22591  *
22592  * Number of good and bad VLAN frames received
22593  *
22594  * Field Access Macros:
22595  *
22596  */
22597 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
22598 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_LSB 0
22599 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
22600 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_MSB 31
22601 /* The width in bits of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
22602 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_WIDTH 32
22603 /* The mask used to set the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
22604 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET_MSK 0xffffffff
22605 /* The mask used to clear the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
22606 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_CLR_MSK 0x00000000
22607 /* The reset value of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
22608 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_RESET 0x0
22609 /* Extracts the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT field value from a register. */
22610 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22611 /* Produces a ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value suitable for setting the register. */
22612 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)
22613 
22614 #ifndef __ASSEMBLY__
22615 /*
22616  * WARNING: The C register and register group struct declarations are provided for
22617  * convenience and illustrative purposes. They should, however, be used with
22618  * caution as the C language standard provides no guarantees about the alignment or
22619  * atomicity of device memory accesses. The recommended practice for writing
22620  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22621  * alt_write_word() functions.
22622  *
22623  * The struct declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB.
22624  */
22625 struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s
22626 {
22627  const uint32_t cnt : 32; /* rxvlanframes_gb */
22628 };
22629 
22630 /* The typedef declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB. */
22631 typedef volatile struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s ALT_EMAC_GMAC_RXVLANFRMS_GB_t;
22632 #endif /* __ASSEMBLY__ */
22633 
22634 /* The byte offset of the ALT_EMAC_GMAC_RXVLANFRMS_GB register from the beginning of the component. */
22635 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST 0x1d8
22636 /* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register. */
22637 #define ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST))
22638 
22639 /*
22640  * Register : Register 119 (rxwatchdogerror Register) - rxwatchdogerror
22641  *
22642  * Number of frames received with error due to watchdog timeout error (frames with
22643  * a data load larger than 2,048 bytes)
22644  *
22645  * Register Layout
22646  *
22647  * Bits | Access | Reset | Description
22648  * :-------|:-------|:------|:----------------
22649  * [31:0] | R | 0x0 | rxwatchdogerror
22650  *
22651  */
22652 /*
22653  * Field : rxwatchdogerror - cnt
22654  *
22655  * Number of frames received with error due to watchdog timeout error (frames with
22656  * a data load larger than 2,048 bytes)
22657  *
22658  * Field Access Macros:
22659  *
22660  */
22661 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
22662 #define ALT_EMAC_GMAC_RXWDERROR_CNT_LSB 0
22663 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
22664 #define ALT_EMAC_GMAC_RXWDERROR_CNT_MSB 31
22665 /* The width in bits of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
22666 #define ALT_EMAC_GMAC_RXWDERROR_CNT_WIDTH 32
22667 /* The mask used to set the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
22668 #define ALT_EMAC_GMAC_RXWDERROR_CNT_SET_MSK 0xffffffff
22669 /* The mask used to clear the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
22670 #define ALT_EMAC_GMAC_RXWDERROR_CNT_CLR_MSK 0x00000000
22671 /* The reset value of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
22672 #define ALT_EMAC_GMAC_RXWDERROR_CNT_RESET 0x0
22673 /* Extracts the ALT_EMAC_GMAC_RXWDERROR_CNT field value from a register. */
22674 #define ALT_EMAC_GMAC_RXWDERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22675 /* Produces a ALT_EMAC_GMAC_RXWDERROR_CNT register field value suitable for setting the register. */
22676 #define ALT_EMAC_GMAC_RXWDERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
22677 
22678 #ifndef __ASSEMBLY__
22679 /*
22680  * WARNING: The C register and register group struct declarations are provided for
22681  * convenience and illustrative purposes. They should, however, be used with
22682  * caution as the C language standard provides no guarantees about the alignment or
22683  * atomicity of device memory accesses. The recommended practice for writing
22684  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22685  * alt_write_word() functions.
22686  *
22687  * The struct declaration for register ALT_EMAC_GMAC_RXWDERROR.
22688  */
22689 struct ALT_EMAC_GMAC_RXWDERROR_s
22690 {
22691  const uint32_t cnt : 32; /* rxwatchdogerror */
22692 };
22693 
22694 /* The typedef declaration for register ALT_EMAC_GMAC_RXWDERROR. */
22695 typedef volatile struct ALT_EMAC_GMAC_RXWDERROR_s ALT_EMAC_GMAC_RXWDERROR_t;
22696 #endif /* __ASSEMBLY__ */
22697 
22698 /* The byte offset of the ALT_EMAC_GMAC_RXWDERROR register from the beginning of the component. */
22699 #define ALT_EMAC_GMAC_RXWDERROR_OFST 0x1dc
22700 /* The address of the ALT_EMAC_GMAC_RXWDERROR register. */
22701 #define ALT_EMAC_GMAC_RXWDERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXWDERROR_OFST))
22702 
22703 /*
22704  * Register : Register 120 (rxrcverror Register) - rxrcverror
22705  *
22706  * Number of frames received with Receive error or Frame Extension error on the
22707  * GMII or MII interface.
22708  *
22709  * Register Layout
22710  *
22711  * Bits | Access | Reset | Description
22712  * :-------|:-------|:------|:------------
22713  * [31:0] | R | 0x0 | rxrcverror
22714  *
22715  */
22716 /*
22717  * Field : rxrcverror - cnt
22718  *
22719  * Number of frames received with Receive error or Frame Extension error on the
22720  * GMII or MII interface.
22721  *
22722  * Field Access Macros:
22723  *
22724  */
22725 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
22726 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_LSB 0
22727 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
22728 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_MSB 31
22729 /* The width in bits of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
22730 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_WIDTH 32
22731 /* The mask used to set the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
22732 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET_MSK 0xffffffff
22733 /* The mask used to clear the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
22734 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_CLR_MSK 0x00000000
22735 /* The reset value of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
22736 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_RESET 0x0
22737 /* Extracts the ALT_EMAC_GMAC_RXRCVERROR_CNT field value from a register. */
22738 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22739 /* Produces a ALT_EMAC_GMAC_RXRCVERROR_CNT register field value suitable for setting the register. */
22740 #define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)
22741 
22742 #ifndef __ASSEMBLY__
22743 /*
22744  * WARNING: The C register and register group struct declarations are provided for
22745  * convenience and illustrative purposes. They should, however, be used with
22746  * caution as the C language standard provides no guarantees about the alignment or
22747  * atomicity of device memory accesses. The recommended practice for writing
22748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22749  * alt_write_word() functions.
22750  *
22751  * The struct declaration for register ALT_EMAC_GMAC_RXRCVERROR.
22752  */
22753 struct ALT_EMAC_GMAC_RXRCVERROR_s
22754 {
22755  const uint32_t cnt : 32; /* rxrcverror */
22756 };
22757 
22758 /* The typedef declaration for register ALT_EMAC_GMAC_RXRCVERROR. */
22759 typedef volatile struct ALT_EMAC_GMAC_RXRCVERROR_s ALT_EMAC_GMAC_RXRCVERROR_t;
22760 #endif /* __ASSEMBLY__ */
22761 
22762 /* The byte offset of the ALT_EMAC_GMAC_RXRCVERROR register from the beginning of the component. */
22763 #define ALT_EMAC_GMAC_RXRCVERROR_OFST 0x1e0
22764 /* The address of the ALT_EMAC_GMAC_RXRCVERROR register. */
22765 #define ALT_EMAC_GMAC_RXRCVERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRCVERROR_OFST))
22766 
22767 /*
22768  * Register : Register 121 (rxctrlframes_g Register) - rxctrlframes_g
22769  *
22770  * Number of received good control frames.
22771  *
22772  * Register Layout
22773  *
22774  * Bits | Access | Reset | Description
22775  * :-------|:-------|:------|:---------------
22776  * [31:0] | R | 0x0 | rxctrlframes_g
22777  *
22778  */
22779 /*
22780  * Field : rxctrlframes_g - cnt
22781  *
22782  * Number of received good control frames.
22783  *
22784  * Field Access Macros:
22785  *
22786  */
22787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
22788 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_LSB 0
22789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
22790 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_MSB 31
22791 /* The width in bits of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
22792 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_WIDTH 32
22793 /* The mask used to set the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
22794 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET_MSK 0xffffffff
22795 /* The mask used to clear the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
22796 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_CLR_MSK 0x00000000
22797 /* The reset value of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
22798 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_RESET 0x0
22799 /* Extracts the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT field value from a register. */
22800 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
22801 /* Produces a ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value suitable for setting the register. */
22802 #define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)
22803 
22804 #ifndef __ASSEMBLY__
22805 /*
22806  * WARNING: The C register and register group struct declarations are provided for
22807  * convenience and illustrative purposes. They should, however, be used with
22808  * caution as the C language standard provides no guarantees about the alignment or
22809  * atomicity of device memory accesses. The recommended practice for writing
22810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22811  * alt_write_word() functions.
22812  *
22813  * The struct declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G.
22814  */
22815 struct ALT_EMAC_GMAC_RXCTLFRMS_G_s
22816 {
22817  const uint32_t cnt : 32; /* rxctrlframes_g */
22818 };
22819 
22820 /* The typedef declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G. */
22821 typedef volatile struct ALT_EMAC_GMAC_RXCTLFRMS_G_s ALT_EMAC_GMAC_RXCTLFRMS_G_t;
22822 #endif /* __ASSEMBLY__ */
22823 
22824 /* The byte offset of the ALT_EMAC_GMAC_RXCTLFRMS_G register from the beginning of the component. */
22825 #define ALT_EMAC_GMAC_RXCTLFRMS_G_OFST 0x1e4
22826 /* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register. */
22827 #define ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCTLFRMS_G_OFST))
22828 
22829 /*
22830  * Register : Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) - MMC_IPC_Receive_Interrupt_Mask
22831  *
22832  * This register maintains the mask for the interrupt generated from the receive
22833  * IPC statistic
22834  *
22835  * counters.
22836  *
22837  * Register Layout
22838  *
22839  * Bits | Access | Reset | Description
22840  * :--------|:-------|:------|:--------------------------------------------------------------------
22841  * [0] | RW | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Mask
22842  * [1] | RW | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
22843  * [2] | RW | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
22844  * [3] | RW | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
22845  * [4] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
22846  * [5] | RW | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Mask
22847  * [6] | RW | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
22848  * [7] | RW | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
22849  * [8] | RW | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Mask
22850  * [9] | RW | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Mask
22851  * [10] | RW | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Mask
22852  * [11] | RW | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Mask
22853  * [12] | RW | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Mask
22854  * [13] | RW | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Mask
22855  * [15:14] | ??? | 0x0 | *UNDEFINED*
22856  * [16] | RW | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Mask
22857  * [17] | RW | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
22858  * [18] | RW | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
22859  * [19] | RW | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
22860  * [20] | RW | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
22861  * [21] | RW | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Mask
22862  * [22] | RW | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
22863  * [23] | RW | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
22864  * [24] | RW | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Mask
22865  * [25] | RW | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Mask
22866  * [26] | RW | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Mask
22867  * [27] | RW | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Mask
22868  * [28] | RW | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Mask
22869  * [29] | RW | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Mask
22870  * [31:30] | ??? | 0x0 | *UNDEFINED*
22871  *
22872  */
22873 /*
22874  * Field : MMC Receive IPV4 Good Frame Counter Interrupt Mask - rxipv4gfim
22875  *
22876  * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches
22877  * half of the maximum value or the maximum value.
22878  *
22879  * Field Enumeration Values:
22880  *
22881  * Enum | Value | Description
22882  * :------------------------------------------------------|:------|:-----------------------------
22883  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR | 0x0 | counter < half max
22884  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR | 0x1 | counter >= half max or max
22885  *
22886  * Field Access Macros:
22887  *
22888  */
22889 /*
22890  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
22891  *
22892  * counter < half max
22893  */
22894 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR 0x0
22895 /*
22896  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
22897  *
22898  * counter >= half max or max
22899  */
22900 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR 0x1
22901 
22902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
22903 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB 0
22904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
22905 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB 0
22906 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
22907 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH 1
22908 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
22909 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK 0x00000001
22910 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
22911 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK 0xfffffffe
22912 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
22913 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET 0x0
22914 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM field value from a register. */
22915 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET(value) (((value) & 0x00000001) >> 0)
22916 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value suitable for setting the register. */
22917 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET(value) (((value) << 0) & 0x00000001)
22918 
22919 /*
22920  * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - rxipv4herfim
22921  *
22922  * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches
22923  * half of the maximum value or the maximum value.
22924  *
22925  * Field Enumeration Values:
22926  *
22927  * Enum | Value | Description
22928  * :--------------------------------------------------------|:------|:-----------------------------
22929  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR | 0x0 | counter < half max
22930  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR | 0x1 | counter >= half max or max
22931  *
22932  * Field Access Macros:
22933  *
22934  */
22935 /*
22936  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
22937  *
22938  * counter < half max
22939  */
22940 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR 0x0
22941 /*
22942  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
22943  *
22944  * counter >= half max or max
22945  */
22946 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR 0x1
22947 
22948 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
22949 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB 1
22950 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
22951 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB 1
22952 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
22953 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH 1
22954 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
22955 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK 0x00000002
22956 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
22957 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK 0xfffffffd
22958 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
22959 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET 0x0
22960 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM field value from a register. */
22961 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET(value) (((value) & 0x00000002) >> 1)
22962 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value suitable for setting the register. */
22963 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET(value) (((value) << 1) & 0x00000002)
22964 
22965 /*
22966  * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - rxipv4nopayfim
22967  *
22968  * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches
22969  * half of the maximum value or the maximum value.
22970  *
22971  * Field Enumeration Values:
22972  *
22973  * Enum | Value | Description
22974  * :----------------------------------------------------------|:------|:-----------------------------
22975  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR | 0x0 | counter < half max
22976  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR | 0x1 | counter >= half max or max
22977  *
22978  * Field Access Macros:
22979  *
22980  */
22981 /*
22982  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
22983  *
22984  * counter < half max
22985  */
22986 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR 0x0
22987 /*
22988  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
22989  *
22990  * counter >= half max or max
22991  */
22992 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR 0x1
22993 
22994 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
22995 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB 2
22996 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
22997 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB 2
22998 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
22999 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH 1
23000 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
23001 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK 0x00000004
23002 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
23003 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK 0xfffffffb
23004 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
23005 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET 0x0
23006 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM field value from a register. */
23007 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET(value) (((value) & 0x00000004) >> 2)
23008 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value suitable for setting the register. */
23009 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET(value) (((value) << 2) & 0x00000004)
23010 
23011 /*
23012  * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - rxipv4fragfim
23013  *
23014  * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches
23015  * half of the maximum value or the maximum value.
23016  *
23017  * Field Enumeration Values:
23018  *
23019  * Enum | Value | Description
23020  * :---------------------------------------------------------|:------|:-----------------------------
23021  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR | 0x0 | counter < half max
23022  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR | 0x1 | counter >= half max or max
23023  *
23024  * Field Access Macros:
23025  *
23026  */
23027 /*
23028  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
23029  *
23030  * counter < half max
23031  */
23032 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR 0x0
23033 /*
23034  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
23035  *
23036  * counter >= half max or max
23037  */
23038 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR 0x1
23039 
23040 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
23041 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB 3
23042 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
23043 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB 3
23044 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
23045 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH 1
23046 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
23047 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK 0x00000008
23048 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
23049 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK 0xfffffff7
23050 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
23051 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET 0x0
23052 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM field value from a register. */
23053 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET(value) (((value) & 0x00000008) >> 3)
23054 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value suitable for setting the register. */
23055 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET(value) (((value) << 3) & 0x00000008)
23056 
23057 /*
23058  * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - rxipv4udsblfim
23059  *
23060  * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches
23061  * half of the maximum value or the maximum value.
23062  *
23063  * Field Enumeration Values:
23064  *
23065  * Enum | Value | Description
23066  * :----------------------------------------------------------|:------|:-----------------------------
23067  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR | 0x0 | counter < half max
23068  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR | 0x1 | counter >= half max or max
23069  *
23070  * Field Access Macros:
23071  *
23072  */
23073 /*
23074  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
23075  *
23076  * counter < half max
23077  */
23078 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR 0x0
23079 /*
23080  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
23081  *
23082  * counter >= half max or max
23083  */
23084 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR 0x1
23085 
23086 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
23087 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB 4
23088 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
23089 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB 4
23090 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
23091 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH 1
23092 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
23093 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK 0x00000010
23094 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
23095 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK 0xffffffef
23096 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
23097 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET 0x0
23098 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM field value from a register. */
23099 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET(value) (((value) & 0x00000010) >> 4)
23100 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value suitable for setting the register. */
23101 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET(value) (((value) << 4) & 0x00000010)
23102 
23103 /*
23104  * Field : MMC Receive IPV6 Good Frame Counter Interrupt Mask - rxipv6gfim
23105  *
23106  * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches
23107  * half of the maximum value or the maximum value.
23108  *
23109  * Field Enumeration Values:
23110  *
23111  * Enum | Value | Description
23112  * :------------------------------------------------------|:------|:-----------------------------
23113  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR | 0x0 | counter < half max
23114  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR | 0x1 | counter >= half max or max
23115  *
23116  * Field Access Macros:
23117  *
23118  */
23119 /*
23120  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
23121  *
23122  * counter < half max
23123  */
23124 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR 0x0
23125 /*
23126  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
23127  *
23128  * counter >= half max or max
23129  */
23130 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR 0x1
23131 
23132 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
23133 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB 5
23134 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
23135 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB 5
23136 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
23137 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH 1
23138 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
23139 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK 0x00000020
23140 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
23141 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK 0xffffffdf
23142 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
23143 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET 0x0
23144 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM field value from a register. */
23145 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET(value) (((value) & 0x00000020) >> 5)
23146 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value suitable for setting the register. */
23147 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET(value) (((value) << 5) & 0x00000020)
23148 
23149 /*
23150  * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - rxipv6herfim
23151  *
23152  * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches
23153  * half of the maximum value or the maximum value.
23154  *
23155  * Field Enumeration Values:
23156  *
23157  * Enum | Value | Description
23158  * :--------------------------------------------------------|:------|:-----------------------------
23159  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR | 0x0 | counter < half max
23160  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR | 0x1 | counter >= half max or max
23161  *
23162  * Field Access Macros:
23163  *
23164  */
23165 /*
23166  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
23167  *
23168  * counter < half max
23169  */
23170 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR 0x0
23171 /*
23172  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
23173  *
23174  * counter >= half max or max
23175  */
23176 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR 0x1
23177 
23178 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
23179 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB 6
23180 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
23181 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB 6
23182 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
23183 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH 1
23184 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
23185 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK 0x00000040
23186 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
23187 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK 0xffffffbf
23188 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
23189 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET 0x0
23190 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM field value from a register. */
23191 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET(value) (((value) & 0x00000040) >> 6)
23192 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value suitable for setting the register. */
23193 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET(value) (((value) << 6) & 0x00000040)
23194 
23195 /*
23196  * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - rxipv6nopayfim
23197  *
23198  * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches
23199  * half of the maximum value or the maximum value.
23200  *
23201  * Field Enumeration Values:
23202  *
23203  * Enum | Value | Description
23204  * :----------------------------------------------------------|:------|:-----------------------------
23205  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR | 0x0 | counter < half max
23206  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR | 0x1 | counter >= half max or max
23207  *
23208  * Field Access Macros:
23209  *
23210  */
23211 /*
23212  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
23213  *
23214  * counter < half max
23215  */
23216 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR 0x0
23217 /*
23218  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
23219  *
23220  * counter >= half max or max
23221  */
23222 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR 0x1
23223 
23224 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
23225 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB 7
23226 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
23227 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB 7
23228 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
23229 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH 1
23230 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
23231 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK 0x00000080
23232 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
23233 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK 0xffffff7f
23234 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
23235 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET 0x0
23236 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM field value from a register. */
23237 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET(value) (((value) & 0x00000080) >> 7)
23238 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value suitable for setting the register. */
23239 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET(value) (((value) << 7) & 0x00000080)
23240 
23241 /*
23242  * Field : MMC Receive UDP Good Frame Counter Interrupt Mask - rxudpgfim
23243  *
23244  * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half
23245  * of the maximum value or the maximum value.
23246  *
23247  * Field Enumeration Values:
23248  *
23249  * Enum | Value | Description
23250  * :-----------------------------------------------------|:------|:-----------------------------
23251  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR | 0x0 | counter < half max
23252  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR | 0x1 | counter >= half max or max
23253  *
23254  * Field Access Macros:
23255  *
23256  */
23257 /*
23258  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
23259  *
23260  * counter < half max
23261  */
23262 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR 0x0
23263 /*
23264  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
23265  *
23266  * counter >= half max or max
23267  */
23268 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR 0x1
23269 
23270 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
23271 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB 8
23272 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
23273 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB 8
23274 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
23275 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH 1
23276 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
23277 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK 0x00000100
23278 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
23279 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK 0xfffffeff
23280 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
23281 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET 0x0
23282 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM field value from a register. */
23283 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET(value) (((value) & 0x00000100) >> 8)
23284 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value suitable for setting the register. */
23285 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET(value) (((value) << 8) & 0x00000100)
23286 
23287 /*
23288  * Field : MMC Receive UDP Error Frame Counter Interrupt Mask - rxudperfim
23289  *
23290  * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches
23291  * half of the maximum value or the maximum value.
23292  *
23293  * Field Enumeration Values:
23294  *
23295  * Enum | Value | Description
23296  * :------------------------------------------------------|:------|:-----------------------------
23297  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR | 0x0 | counter < half max
23298  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR | 0x1 | counter >= half max or max
23299  *
23300  * Field Access Macros:
23301  *
23302  */
23303 /*
23304  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
23305  *
23306  * counter < half max
23307  */
23308 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR 0x0
23309 /*
23310  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
23311  *
23312  * counter >= half max or max
23313  */
23314 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR 0x1
23315 
23316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
23317 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB 9
23318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
23319 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB 9
23320 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
23321 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH 1
23322 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
23323 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK 0x00000200
23324 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
23325 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK 0xfffffdff
23326 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
23327 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET 0x0
23328 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM field value from a register. */
23329 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET(value) (((value) & 0x00000200) >> 9)
23330 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value suitable for setting the register. */
23331 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET(value) (((value) << 9) & 0x00000200)
23332 
23333 /*
23334  * Field : MMC Receive TCP Good Frame Counter Interrupt Mask - rxtcpgfim
23335  *
23336  * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half
23337  * of the maximum value or the maximum value.
23338  *
23339  * Field Enumeration Values:
23340  *
23341  * Enum | Value | Description
23342  * :-----------------------------------------------------|:------|:-----------------------------
23343  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR | 0x0 | counter < half max
23344  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR | 0x1 | counter >= half max or max
23345  *
23346  * Field Access Macros:
23347  *
23348  */
23349 /*
23350  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
23351  *
23352  * counter < half max
23353  */
23354 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR 0x0
23355 /*
23356  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
23357  *
23358  * counter >= half max or max
23359  */
23360 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR 0x1
23361 
23362 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
23363 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB 10
23364 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
23365 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB 10
23366 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
23367 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH 1
23368 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
23369 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK 0x00000400
23370 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
23371 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK 0xfffffbff
23372 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
23373 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET 0x0
23374 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM field value from a register. */
23375 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET(value) (((value) & 0x00000400) >> 10)
23376 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value suitable for setting the register. */
23377 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET(value) (((value) << 10) & 0x00000400)
23378 
23379 /*
23380  * Field : MMC Receive TCP Error Frame Counter Interrupt Mask - rxtcperfim
23381  *
23382  * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches
23383  * half of the maximum value or the maximum value.
23384  *
23385  * Field Enumeration Values:
23386  *
23387  * Enum | Value | Description
23388  * :------------------------------------------------------|:------|:-----------------------------
23389  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR | 0x0 | counter < half max
23390  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR | 0x1 | counter >= half max or max
23391  *
23392  * Field Access Macros:
23393  *
23394  */
23395 /*
23396  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
23397  *
23398  * counter < half max
23399  */
23400 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR 0x0
23401 /*
23402  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
23403  *
23404  * counter >= half max or max
23405  */
23406 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR 0x1
23407 
23408 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
23409 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB 11
23410 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
23411 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB 11
23412 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
23413 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH 1
23414 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
23415 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK 0x00000800
23416 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
23417 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK 0xfffff7ff
23418 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
23419 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET 0x0
23420 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM field value from a register. */
23421 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET(value) (((value) & 0x00000800) >> 11)
23422 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value suitable for setting the register. */
23423 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET(value) (((value) << 11) & 0x00000800)
23424 
23425 /*
23426  * Field : MMC Receive ICMP Good Frame Counter Interrupt Mask - rxicmpgfim
23427  *
23428  * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches
23429  * half of the maximum value or the maximum value.
23430  *
23431  * Field Enumeration Values:
23432  *
23433  * Enum | Value | Description
23434  * :------------------------------------------------------|:------|:-----------------------------
23435  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR | 0x0 | counter < half max
23436  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR | 0x1 | counter >= half max or max
23437  *
23438  * Field Access Macros:
23439  *
23440  */
23441 /*
23442  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
23443  *
23444  * counter < half max
23445  */
23446 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR 0x0
23447 /*
23448  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
23449  *
23450  * counter >= half max or max
23451  */
23452 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR 0x1
23453 
23454 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
23455 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB 12
23456 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
23457 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB 12
23458 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
23459 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH 1
23460 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
23461 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK 0x00001000
23462 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
23463 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK 0xffffefff
23464 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
23465 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET 0x0
23466 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM field value from a register. */
23467 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET(value) (((value) & 0x00001000) >> 12)
23468 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value suitable for setting the register. */
23469 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET(value) (((value) << 12) & 0x00001000)
23470 
23471 /*
23472  * Field : MMC Receive ICMP Error Frame Counter Interrupt Mask - rxicmperfim
23473  *
23474  * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches
23475  * half of the maximum value or the maximum value.
23476  *
23477  * Field Enumeration Values:
23478  *
23479  * Enum | Value | Description
23480  * :-------------------------------------------------------|:------|:-----------------------------
23481  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR | 0x0 | counter < half max
23482  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR | 0x1 | counter >= half max or max
23483  *
23484  * Field Access Macros:
23485  *
23486  */
23487 /*
23488  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
23489  *
23490  * counter < half max
23491  */
23492 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR 0x0
23493 /*
23494  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
23495  *
23496  * counter >= half max or max
23497  */
23498 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR 0x1
23499 
23500 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
23501 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB 13
23502 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
23503 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB 13
23504 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
23505 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH 1
23506 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
23507 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK 0x00002000
23508 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
23509 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK 0xffffdfff
23510 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
23511 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET 0x0
23512 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM field value from a register. */
23513 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET(value) (((value) & 0x00002000) >> 13)
23514 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value suitable for setting the register. */
23515 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET(value) (((value) << 13) & 0x00002000)
23516 
23517 /*
23518  * Field : MMC Receive IPV4 Good Octet Counter Interrupt Mask - rxipv4goim
23519  *
23520  * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches
23521  * half of the maximum value or the maximum value.
23522  *
23523  * Field Enumeration Values:
23524  *
23525  * Enum | Value | Description
23526  * :------------------------------------------------------|:------|:-----------------------------
23527  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR | 0x0 | counter < half max
23528  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR | 0x1 | counter >= half max or max
23529  *
23530  * Field Access Macros:
23531  *
23532  */
23533 /*
23534  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
23535  *
23536  * counter < half max
23537  */
23538 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR 0x0
23539 /*
23540  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
23541  *
23542  * counter >= half max or max
23543  */
23544 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR 0x1
23545 
23546 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
23547 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB 16
23548 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
23549 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB 16
23550 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
23551 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH 1
23552 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
23553 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK 0x00010000
23554 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
23555 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK 0xfffeffff
23556 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
23557 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET 0x0
23558 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM field value from a register. */
23559 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET(value) (((value) & 0x00010000) >> 16)
23560 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value suitable for setting the register. */
23561 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET(value) (((value) << 16) & 0x00010000)
23562 
23563 /*
23564  * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - rxipv4heroim
23565  *
23566  * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter
23567  * reaches half of the maximum value or the maximum value.
23568  *
23569  * Field Enumeration Values:
23570  *
23571  * Enum | Value | Description
23572  * :--------------------------------------------------------|:------|:-----------------------------
23573  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR | 0x0 | counter < half max
23574  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR | 0x1 | counter >= half max or max
23575  *
23576  * Field Access Macros:
23577  *
23578  */
23579 /*
23580  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
23581  *
23582  * counter < half max
23583  */
23584 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR 0x0
23585 /*
23586  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
23587  *
23588  * counter >= half max or max
23589  */
23590 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR 0x1
23591 
23592 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
23593 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB 17
23594 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
23595 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB 17
23596 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
23597 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH 1
23598 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
23599 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK 0x00020000
23600 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
23601 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK 0xfffdffff
23602 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
23603 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET 0x0
23604 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM field value from a register. */
23605 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET(value) (((value) & 0x00020000) >> 17)
23606 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value suitable for setting the register. */
23607 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET(value) (((value) << 17) & 0x00020000)
23608 
23609 /*
23610  * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - rxipv4nopayoim
23611  *
23612  * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter
23613  * reaches half of the maximum value or the maximum value.
23614  *
23615  * Field Enumeration Values:
23616  *
23617  * Enum | Value | Description
23618  * :----------------------------------------------------------|:------|:-----------------------------
23619  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR | 0x0 | counter < half max
23620  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR | 0x1 | counter >= half max or max
23621  *
23622  * Field Access Macros:
23623  *
23624  */
23625 /*
23626  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
23627  *
23628  * counter < half max
23629  */
23630 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR 0x0
23631 /*
23632  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
23633  *
23634  * counter >= half max or max
23635  */
23636 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR 0x1
23637 
23638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
23639 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB 18
23640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
23641 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB 18
23642 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
23643 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH 1
23644 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
23645 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK 0x00040000
23646 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
23647 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK 0xfffbffff
23648 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
23649 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET 0x0
23650 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM field value from a register. */
23651 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET(value) (((value) & 0x00040000) >> 18)
23652 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value suitable for setting the register. */
23653 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET(value) (((value) << 18) & 0x00040000)
23654 
23655 /*
23656  * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - rxipv4fragoim
23657  *
23658  * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches
23659  * half of the maximum value or the maximum value.
23660  *
23661  * Field Enumeration Values:
23662  *
23663  * Enum | Value | Description
23664  * :---------------------------------------------------------|:------|:-----------------------------
23665  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR | 0x0 | counter < half max
23666  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR | 0x1 | counter >= half max or max
23667  *
23668  * Field Access Macros:
23669  *
23670  */
23671 /*
23672  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
23673  *
23674  * counter < half max
23675  */
23676 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR 0x0
23677 /*
23678  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
23679  *
23680  * counter >= half max or max
23681  */
23682 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR 0x1
23683 
23684 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
23685 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB 19
23686 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
23687 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB 19
23688 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
23689 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH 1
23690 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
23691 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK 0x00080000
23692 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
23693 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK 0xfff7ffff
23694 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
23695 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET 0x0
23696 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM field value from a register. */
23697 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET(value) (((value) & 0x00080000) >> 19)
23698 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value suitable for setting the register. */
23699 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET(value) (((value) << 19) & 0x00080000)
23700 
23701 /*
23702  * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - rxipv4udsbloim
23703  *
23704  * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter
23705  * reaches half of the maximum value or the maximum value.
23706  *
23707  * Field Enumeration Values:
23708  *
23709  * Enum | Value | Description
23710  * :----------------------------------------------------------|:------|:-----------------------------
23711  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR | 0x0 | counter < half max
23712  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR | 0x1 | counter >= half max or max
23713  *
23714  * Field Access Macros:
23715  *
23716  */
23717 /*
23718  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
23719  *
23720  * counter < half max
23721  */
23722 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR 0x0
23723 /*
23724  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
23725  *
23726  * counter >= half max or max
23727  */
23728 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR 0x1
23729 
23730 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
23731 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB 20
23732 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
23733 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB 20
23734 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
23735 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH 1
23736 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
23737 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK 0x00100000
23738 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
23739 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK 0xffefffff
23740 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
23741 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET 0x0
23742 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM field value from a register. */
23743 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET(value) (((value) & 0x00100000) >> 20)
23744 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value suitable for setting the register. */
23745 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET(value) (((value) << 20) & 0x00100000)
23746 
23747 /*
23748  * Field : MMC Receive IPV6 Good Octet Counter Interrupt Mask - rxipv6goim
23749  *
23750  * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches
23751  * half of the maximum value or the maximum value.
23752  *
23753  * Field Enumeration Values:
23754  *
23755  * Enum | Value | Description
23756  * :------------------------------------------------------|:------|:-----------------------------
23757  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR | 0x0 | counter < half max
23758  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR | 0x1 | counter >= half max or max
23759  *
23760  * Field Access Macros:
23761  *
23762  */
23763 /*
23764  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
23765  *
23766  * counter < half max
23767  */
23768 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR 0x0
23769 /*
23770  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
23771  *
23772  * counter >= half max or max
23773  */
23774 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR 0x1
23775 
23776 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
23777 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB 21
23778 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
23779 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB 21
23780 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
23781 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH 1
23782 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
23783 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK 0x00200000
23784 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
23785 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK 0xffdfffff
23786 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
23787 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET 0x0
23788 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM field value from a register. */
23789 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET(value) (((value) & 0x00200000) >> 21)
23790 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value suitable for setting the register. */
23791 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET(value) (((value) << 21) & 0x00200000)
23792 
23793 /*
23794  * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - rxipv6heroim
23795  *
23796  * Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches
23797  * half of the maximum value or the maximum value.
23798  *
23799  * Field Enumeration Values:
23800  *
23801  * Enum | Value | Description
23802  * :--------------------------------------------------------|:------|:-----------------------------
23803  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR | 0x0 | counter < half max
23804  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR | 0x1 | counter >= half max or max
23805  *
23806  * Field Access Macros:
23807  *
23808  */
23809 /*
23810  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
23811  *
23812  * counter < half max
23813  */
23814 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR 0x0
23815 /*
23816  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
23817  *
23818  * counter >= half max or max
23819  */
23820 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR 0x1
23821 
23822 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
23823 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB 22
23824 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
23825 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB 22
23826 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
23827 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH 1
23828 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
23829 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK 0x00400000
23830 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
23831 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK 0xffbfffff
23832 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
23833 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET 0x0
23834 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM field value from a register. */
23835 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET(value) (((value) & 0x00400000) >> 22)
23836 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value suitable for setting the register. */
23837 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET(value) (((value) << 22) & 0x00400000)
23838 
23839 /*
23840  * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - rxipv6nopayoim
23841  *
23842  * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter
23843  * reaches half of the maximum value or the maximum value.
23844  *
23845  * Field Enumeration Values:
23846  *
23847  * Enum | Value | Description
23848  * :----------------------------------------------------------|:------|:-----------------------------
23849  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR | 0x0 | counter < half max
23850  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR | 0x1 | counter >= half max or max
23851  *
23852  * Field Access Macros:
23853  *
23854  */
23855 /*
23856  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
23857  *
23858  * counter < half max
23859  */
23860 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR 0x0
23861 /*
23862  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
23863  *
23864  * counter >= half max or max
23865  */
23866 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR 0x1
23867 
23868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
23869 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB 23
23870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
23871 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB 23
23872 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
23873 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH 1
23874 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
23875 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK 0x00800000
23876 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
23877 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK 0xff7fffff
23878 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
23879 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET 0x0
23880 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM field value from a register. */
23881 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET(value) (((value) & 0x00800000) >> 23)
23882 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value suitable for setting the register. */
23883 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET(value) (((value) << 23) & 0x00800000)
23884 
23885 /*
23886  * Field : MMC Receive UDP Good Octet Counter Interrupt Mask - rxudpgoim
23887  *
23888  * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches
23889  * half of the maximum value or the maximum value.
23890  *
23891  * Field Enumeration Values:
23892  *
23893  * Enum | Value | Description
23894  * :-----------------------------------------------------|:------|:-----------------------------
23895  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR | 0x0 | counter < half max
23896  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR | 0x1 | counter >= half max or max
23897  *
23898  * Field Access Macros:
23899  *
23900  */
23901 /*
23902  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
23903  *
23904  * counter < half max
23905  */
23906 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR 0x0
23907 /*
23908  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
23909  *
23910  * counter >= half max or max
23911  */
23912 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR 0x1
23913 
23914 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
23915 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB 24
23916 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
23917 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB 24
23918 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
23919 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH 1
23920 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
23921 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK 0x01000000
23922 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
23923 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK 0xfeffffff
23924 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
23925 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET 0x0
23926 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM field value from a register. */
23927 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET(value) (((value) & 0x01000000) >> 24)
23928 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value suitable for setting the register. */
23929 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET(value) (((value) << 24) & 0x01000000)
23930 
23931 /*
23932  * Field : MMC Receive UDP Error Octet Counter Interrupt Mask - rxudperoim
23933  *
23934  * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches
23935  * half of the maximum value or the maximum value.
23936  *
23937  * Field Enumeration Values:
23938  *
23939  * Enum | Value | Description
23940  * :------------------------------------------------------|:------|:-----------------------------
23941  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR | 0x0 | counter < half max
23942  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR | 0x1 | counter >= half max or max
23943  *
23944  * Field Access Macros:
23945  *
23946  */
23947 /*
23948  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
23949  *
23950  * counter < half max
23951  */
23952 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR 0x0
23953 /*
23954  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
23955  *
23956  * counter >= half max or max
23957  */
23958 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR 0x1
23959 
23960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
23961 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB 25
23962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
23963 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB 25
23964 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
23965 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH 1
23966 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
23967 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK 0x02000000
23968 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
23969 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK 0xfdffffff
23970 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
23971 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET 0x0
23972 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM field value from a register. */
23973 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET(value) (((value) & 0x02000000) >> 25)
23974 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value suitable for setting the register. */
23975 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET(value) (((value) << 25) & 0x02000000)
23976 
23977 /*
23978  * Field : MMC Receive TCP Good Octet Counter Interrupt Mask - rxtcpgoim
23979  *
23980  * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches
23981  * half of the maximum value or the maximum value.
23982  *
23983  * Field Enumeration Values:
23984  *
23985  * Enum | Value | Description
23986  * :-----------------------------------------------------|:------|:-----------------------------
23987  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR | 0x0 | counter < half max
23988  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR | 0x1 | counter >= half max or max
23989  *
23990  * Field Access Macros:
23991  *
23992  */
23993 /*
23994  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
23995  *
23996  * counter < half max
23997  */
23998 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR 0x0
23999 /*
24000  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
24001  *
24002  * counter >= half max or max
24003  */
24004 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR 0x1
24005 
24006 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
24007 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB 26
24008 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
24009 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB 26
24010 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
24011 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH 1
24012 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
24013 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK 0x04000000
24014 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
24015 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK 0xfbffffff
24016 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
24017 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET 0x0
24018 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM field value from a register. */
24019 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET(value) (((value) & 0x04000000) >> 26)
24020 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value suitable for setting the register. */
24021 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET(value) (((value) << 26) & 0x04000000)
24022 
24023 /*
24024  * Field : MMC Receive TCP Error Octet Counter Interrupt Mask - rxtcperoim
24025  *
24026  * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches
24027  * half of the maximum value or the maximum value.
24028  *
24029  * Field Enumeration Values:
24030  *
24031  * Enum | Value | Description
24032  * :------------------------------------------------------|:------|:-----------------------------
24033  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR | 0x0 | counter < half max
24034  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR | 0x1 | counter >= half max or max
24035  *
24036  * Field Access Macros:
24037  *
24038  */
24039 /*
24040  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
24041  *
24042  * counter < half max
24043  */
24044 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR 0x0
24045 /*
24046  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
24047  *
24048  * counter >= half max or max
24049  */
24050 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR 0x1
24051 
24052 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
24053 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB 27
24054 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
24055 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB 27
24056 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
24057 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH 1
24058 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
24059 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK 0x08000000
24060 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
24061 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK 0xf7ffffff
24062 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
24063 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET 0x0
24064 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM field value from a register. */
24065 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET(value) (((value) & 0x08000000) >> 27)
24066 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value suitable for setting the register. */
24067 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET(value) (((value) << 27) & 0x08000000)
24068 
24069 /*
24070  * Field : MMC Receive ICMP Good Octet Counter Interrupt Mask - rxicmpgoim
24071  *
24072  * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches
24073  * half of the maximum value or the maximum value.
24074  *
24075  * Field Enumeration Values:
24076  *
24077  * Enum | Value | Description
24078  * :------------------------------------------------------|:------|:-----------------------------
24079  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR | 0x0 | counter < half max
24080  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR | 0x1 | counter >= half max or max
24081  *
24082  * Field Access Macros:
24083  *
24084  */
24085 /*
24086  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
24087  *
24088  * counter < half max
24089  */
24090 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR 0x0
24091 /*
24092  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
24093  *
24094  * counter >= half max or max
24095  */
24096 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR 0x1
24097 
24098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
24099 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB 28
24100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
24101 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB 28
24102 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
24103 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH 1
24104 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
24105 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK 0x10000000
24106 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
24107 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK 0xefffffff
24108 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
24109 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET 0x0
24110 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM field value from a register. */
24111 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET(value) (((value) & 0x10000000) >> 28)
24112 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value suitable for setting the register. */
24113 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET(value) (((value) << 28) & 0x10000000)
24114 
24115 /*
24116  * Field : MMC Receive ICMP Error Octet Counter Interrupt Mask - rxicmperoim
24117  *
24118  * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches
24119  * half of the maximum value or the maximum value.
24120  *
24121  * Field Enumeration Values:
24122  *
24123  * Enum | Value | Description
24124  * :-------------------------------------------------------|:------|:-----------------------------
24125  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR | 0x0 | counter < half max
24126  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR | 0x1 | counter >= half max or max
24127  *
24128  * Field Access Macros:
24129  *
24130  */
24131 /*
24132  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
24133  *
24134  * counter < half max
24135  */
24136 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR 0x0
24137 /*
24138  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
24139  *
24140  * counter >= half max or max
24141  */
24142 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR 0x1
24143 
24144 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
24145 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB 29
24146 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
24147 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB 29
24148 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
24149 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH 1
24150 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
24151 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK 0x20000000
24152 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
24153 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK 0xdfffffff
24154 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
24155 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET 0x0
24156 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM field value from a register. */
24157 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET(value) (((value) & 0x20000000) >> 29)
24158 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value suitable for setting the register. */
24159 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET(value) (((value) << 29) & 0x20000000)
24160 
24161 #ifndef __ASSEMBLY__
24162 /*
24163  * WARNING: The C register and register group struct declarations are provided for
24164  * convenience and illustrative purposes. They should, however, be used with
24165  * caution as the C language standard provides no guarantees about the alignment or
24166  * atomicity of device memory accesses. The recommended practice for writing
24167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24168  * alt_write_word() functions.
24169  *
24170  * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK.
24171  */
24172 struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s
24173 {
24174  uint32_t rxipv4gfim : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Mask */
24175  uint32_t rxipv4herfim : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Mask */
24176  uint32_t rxipv4nopayfim : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Mask */
24177  uint32_t rxipv4fragfim : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask */
24178  uint32_t rxipv4udsblfim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask */
24179  uint32_t rxipv6gfim : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Mask */
24180  uint32_t rxipv6herfim : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Mask */
24181  uint32_t rxipv6nopayfim : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Mask */
24182  uint32_t rxudpgfim : 1; /* MMC Receive UDP Good Frame Counter Interrupt Mask */
24183  uint32_t rxudperfim : 1; /* MMC Receive UDP Error Frame Counter Interrupt Mask */
24184  uint32_t rxtcpgfim : 1; /* MMC Receive TCP Good Frame Counter Interrupt Mask */
24185  uint32_t rxtcperfim : 1; /* MMC Receive TCP Error Frame Counter Interrupt Mask */
24186  uint32_t rxicmpgfim : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Mask */
24187  uint32_t rxicmperfim : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Mask */
24188  uint32_t : 2; /* *UNDEFINED* */
24189  uint32_t rxipv4goim : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Mask */
24190  uint32_t rxipv4heroim : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Mask */
24191  uint32_t rxipv4nopayoim : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Mask */
24192  uint32_t rxipv4fragoim : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask */
24193  uint32_t rxipv4udsbloim : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask */
24194  uint32_t rxipv6goim : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Mask */
24195  uint32_t rxipv6heroim : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Mask */
24196  uint32_t rxipv6nopayoim : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Mask */
24197  uint32_t rxudpgoim : 1; /* MMC Receive UDP Good Octet Counter Interrupt Mask */
24198  uint32_t rxudperoim : 1; /* MMC Receive UDP Error Octet Counter Interrupt Mask */
24199  uint32_t rxtcpgoim : 1; /* MMC Receive TCP Good Octet Counter Interrupt Mask */
24200  uint32_t rxtcperoim : 1; /* MMC Receive TCP Error Octet Counter Interrupt Mask */
24201  uint32_t rxicmpgoim : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Mask */
24202  uint32_t rxicmperoim : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Mask */
24203  uint32_t : 2; /* *UNDEFINED* */
24204 };
24205 
24206 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK. */
24207 typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t;
24208 #endif /* __ASSEMBLY__ */
24209 
24210 /* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register from the beginning of the component. */
24211 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST 0x200
24212 /* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register. */
24213 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST))
24214 
24215 /*
24216  * Register : Register 130 (MMC Receive Checksum Offload Interrupt Register) - MMC_IPC_Receive_Interrupt
24217  *
24218  * This register maintains the interrupts generated when receive IPC statistic
24219  * counters reach half their maximum values (0x8000_0000 for 32-bit counter and
24220  * 0x8000 for 16-bit counter), and when they cross their maximum values
24221  * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
24222  * Stop Rollover is set, then interrupts are set but the counter remains at all-
24223  * ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When
24224  * the MMC IPC counter that caused the interrupt is read, its corresponding
24225  * interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0])
24226  * must be read to clear the interrupt bit.
24227  *
24228  * Register Layout
24229  *
24230  * Bits | Access | Reset | Description
24231  * :--------|:-------|:------|:----------------------------------------------------------------------
24232  * [0] | R | 0x0 | MMC Receive IPV4 Good Frame Counter Interrupt Status
24233  * [1] | R | 0x0 | MMC Receive IPV4 Header Error Frame Counter Interrupt Status
24234  * [2] | R | 0x0 | MMC Receive IPV4 No Payload Frame Counter Interrupt Status
24235  * [3] | R | 0x0 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Status
24236  * [4] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status
24237  * [5] | R | 0x0 | MMC Receive IPV6 Good Frame Counter Interrupt Status
24238  * [6] | R | 0x0 | MMC Receive IPV6 Header Error Frame Counter Interrupt Status
24239  * [7] | R | 0x0 | MMC Receive IPV6 No Payload Frame Counter Interrupt Status
24240  * [8] | R | 0x0 | MMC Receive UDP Good Frame Counter Interrupt Status
24241  * [9] | R | 0x0 | MMC Receive UDP Error Frame Counter Interrupt Status
24242  * [10] | R | 0x0 | MMC Receive TCP Good Frame Counter Interrupt Status
24243  * [11] | R | 0x0 | MMC Receive TCP Error Frame Counter Interrupt Status
24244  * [12] | R | 0x0 | MMC Receive ICMP Good Frame Counter Interrupt Status
24245  * [13] | R | 0x0 | MMC Receive ICMP Error Frame Counter Interrupt Status
24246  * [15:14] | ??? | 0x0 | *UNDEFINED*
24247  * [16] | R | 0x0 | MMC Receive IPV4 Good Octet Counter Interrupt Status
24248  * [17] | R | 0x0 | MMC Receive IPV4 Header Error Octet Counter Interrupt Status
24249  * [18] | R | 0x0 | MMC Receive IPV4 No Payload Octet Counter Interrupt Status
24250  * [19] | R | 0x0 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Status
24251  * [20] | R | 0x0 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status
24252  * [21] | R | 0x0 | MMC Receive IPV6 Good Octet Counter Interrupt Status
24253  * [22] | R | 0x0 | MMC Receive IPV6 Header Error Octet Counter Interrupt Status
24254  * [23] | R | 0x0 | MMC Receive IPV6 No Payload Octet Counter Interrupt Status
24255  * [24] | R | 0x0 | MMC Receive UDP Good Octet Counter Interrupt Status
24256  * [25] | R | 0x0 | MMC Receive UDP Error Octet Counter Interrupt Status
24257  * [26] | R | 0x0 | MMC Receive TCP Good Octet Counter Interrupt Status
24258  * [27] | R | 0x0 | MMC Receive TCP Error Octet Counter Interrupt Status
24259  * [28] | R | 0x0 | MMC Receive ICMP Good Octet Counter Interrupt Status
24260  * [29] | R | 0x0 | MMC Receive ICMP Error Octet Counter Interrupt Status
24261  * [31:30] | ??? | 0x0 | *UNDEFINED*
24262  *
24263  */
24264 /*
24265  * Field : MMC Receive IPV4 Good Frame Counter Interrupt Status - rxipv4gfis
24266  *
24267  * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum
24268  * value or the maximum value.
24269  *
24270  * Field Enumeration Values:
24271  *
24272  * Enum | Value | Description
24273  * :-----------------------------------------------|:------|:-----------------------------
24274  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT | 0x0 | counter < half max
24275  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR | 0x1 | counter >= half max or max
24276  *
24277  * Field Access Macros:
24278  *
24279  */
24280 /*
24281  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
24282  *
24283  * counter < half max
24284  */
24285 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT 0x0
24286 /*
24287  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
24288  *
24289  * counter >= half max or max
24290  */
24291 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR 0x1
24292 
24293 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
24294 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_LSB 0
24295 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
24296 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_MSB 0
24297 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
24298 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_WIDTH 1
24299 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
24300 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET_MSK 0x00000001
24301 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
24302 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_CLR_MSK 0xfffffffe
24303 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
24304 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_RESET 0x0
24305 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS field value from a register. */
24306 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_GET(value) (((value) & 0x00000001) >> 0)
24307 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value suitable for setting the register. */
24308 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET(value) (((value) << 0) & 0x00000001)
24309 
24310 /*
24311  * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Status - rxipv4herfis
24312  *
24313  * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum
24314  * value or the maximum value.
24315  *
24316  * Field Enumeration Values:
24317  *
24318  * Enum | Value | Description
24319  * :-------------------------------------------------|:------|:-----------------------------
24320  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT | 0x0 | counter < half max
24321  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR | 0x1 | counter >= half max or max
24322  *
24323  * Field Access Macros:
24324  *
24325  */
24326 /*
24327  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
24328  *
24329  * counter < half max
24330  */
24331 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT 0x0
24332 /*
24333  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
24334  *
24335  * counter >= half max or max
24336  */
24337 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR 0x1
24338 
24339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
24340 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB 1
24341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
24342 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB 1
24343 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
24344 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH 1
24345 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
24346 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK 0x00000002
24347 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
24348 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK 0xfffffffd
24349 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
24350 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET 0x0
24351 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS field value from a register. */
24352 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET(value) (((value) & 0x00000002) >> 1)
24353 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value suitable for setting the register. */
24354 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET(value) (((value) << 1) & 0x00000002)
24355 
24356 /*
24357  * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Status - rxipv4nopayfis
24358  *
24359  * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum
24360  * value or the maximum value.
24361  *
24362  * Field Enumeration Values:
24363  *
24364  * Enum | Value | Description
24365  * :---------------------------------------------------|:------|:-----------------------------
24366  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT | 0x0 | counter < half max
24367  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR | 0x1 | counter >= half max or max
24368  *
24369  * Field Access Macros:
24370  *
24371  */
24372 /*
24373  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
24374  *
24375  * counter < half max
24376  */
24377 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT 0x0
24378 /*
24379  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
24380  *
24381  * counter >= half max or max
24382  */
24383 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR 0x1
24384 
24385 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
24386 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB 2
24387 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
24388 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB 2
24389 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
24390 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH 1
24391 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
24392 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK 0x00000004
24393 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
24394 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK 0xfffffffb
24395 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
24396 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET 0x0
24397 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS field value from a register. */
24398 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET(value) (((value) & 0x00000004) >> 2)
24399 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value suitable for setting the register. */
24400 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET(value) (((value) << 2) & 0x00000004)
24401 
24402 /*
24403  * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - rxipv4fragfis
24404  *
24405  * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum
24406  * value or the maximum value.
24407  *
24408  * Field Enumeration Values:
24409  *
24410  * Enum | Value | Description
24411  * :--------------------------------------------------|:------|:-----------------------------
24412  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT | 0x0 | counter < half max
24413  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR | 0x1 | counter >= half max or max
24414  *
24415  * Field Access Macros:
24416  *
24417  */
24418 /*
24419  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
24420  *
24421  * counter < half max
24422  */
24423 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT 0x0
24424 /*
24425  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
24426  *
24427  * counter >= half max or max
24428  */
24429 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR 0x1
24430 
24431 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
24432 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB 3
24433 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
24434 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB 3
24435 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
24436 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH 1
24437 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
24438 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK 0x00000008
24439 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
24440 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK 0xfffffff7
24441 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
24442 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET 0x0
24443 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS field value from a register. */
24444 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET(value) (((value) & 0x00000008) >> 3)
24445 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value suitable for setting the register. */
24446 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET(value) (((value) << 3) & 0x00000008)
24447 
24448 /*
24449  * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - rxipv4udsblfis
24450  *
24451  * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum
24452  * value or the maximum value.
24453  *
24454  * Field Enumeration Values:
24455  *
24456  * Enum | Value | Description
24457  * :---------------------------------------------------|:------|:-----------------------------
24458  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT | 0x0 | counter < half max
24459  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR | 0x1 | counter >= half max or max
24460  *
24461  * Field Access Macros:
24462  *
24463  */
24464 /*
24465  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
24466  *
24467  * counter < half max
24468  */
24469 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT 0x0
24470 /*
24471  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
24472  *
24473  * counter >= half max or max
24474  */
24475 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR 0x1
24476 
24477 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
24478 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB 4
24479 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
24480 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB 4
24481 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
24482 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH 1
24483 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
24484 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK 0x00000010
24485 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
24486 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK 0xffffffef
24487 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
24488 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET 0x0
24489 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS field value from a register. */
24490 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET(value) (((value) & 0x00000010) >> 4)
24491 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value suitable for setting the register. */
24492 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET(value) (((value) << 4) & 0x00000010)
24493 
24494 /*
24495  * Field : MMC Receive IPV6 Good Frame Counter Interrupt Status - rxipv6gfis
24496  *
24497  * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum
24498  * value or the maximum value.
24499  *
24500  * Field Enumeration Values:
24501  *
24502  * Enum | Value | Description
24503  * :-----------------------------------------------|:------|:-----------------------------
24504  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT | 0x0 | counter < half max
24505  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR | 0x1 | counter >= half max or max
24506  *
24507  * Field Access Macros:
24508  *
24509  */
24510 /*
24511  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
24512  *
24513  * counter < half max
24514  */
24515 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT 0x0
24516 /*
24517  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
24518  *
24519  * counter >= half max or max
24520  */
24521 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR 0x1
24522 
24523 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
24524 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB 5
24525 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
24526 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB 5
24527 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
24528 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH 1
24529 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
24530 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK 0x00000020
24531 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
24532 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK 0xffffffdf
24533 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
24534 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET 0x0
24535 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS field value from a register. */
24536 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET(value) (((value) & 0x00000020) >> 5)
24537 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value suitable for setting the register. */
24538 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET(value) (((value) << 5) & 0x00000020)
24539 
24540 /*
24541  * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Status - rxipv6herfis
24542  *
24543  * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum
24544  * value or the maximum value.
24545  *
24546  * Field Enumeration Values:
24547  *
24548  * Enum | Value | Description
24549  * :-------------------------------------------------|:------|:-----------------------------
24550  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT | 0x0 | counter < half max
24551  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR | 0x1 | counter >= half max or max
24552  *
24553  * Field Access Macros:
24554  *
24555  */
24556 /*
24557  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
24558  *
24559  * counter < half max
24560  */
24561 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT 0x0
24562 /*
24563  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
24564  *
24565  * counter >= half max or max
24566  */
24567 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR 0x1
24568 
24569 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
24570 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB 6
24571 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
24572 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB 6
24573 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
24574 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH 1
24575 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
24576 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK 0x00000040
24577 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
24578 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK 0xffffffbf
24579 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
24580 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET 0x0
24581 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS field value from a register. */
24582 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET(value) (((value) & 0x00000040) >> 6)
24583 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value suitable for setting the register. */
24584 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET(value) (((value) << 6) & 0x00000040)
24585 
24586 /*
24587  * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Status - rxipv6nopayfis
24588  *
24589  * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum
24590  * value or the maximum value.
24591  *
24592  * Field Enumeration Values:
24593  *
24594  * Enum | Value | Description
24595  * :---------------------------------------------------|:------|:-----------------------------
24596  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT | 0x0 | counter < half max
24597  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR | 0x1 | counter >= half max or max
24598  *
24599  * Field Access Macros:
24600  *
24601  */
24602 /*
24603  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
24604  *
24605  * counter < half max
24606  */
24607 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT 0x0
24608 /*
24609  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
24610  *
24611  * counter >= half max or max
24612  */
24613 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR 0x1
24614 
24615 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
24616 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB 7
24617 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
24618 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB 7
24619 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
24620 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH 1
24621 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
24622 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK 0x00000080
24623 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
24624 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK 0xffffff7f
24625 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
24626 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET 0x0
24627 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS field value from a register. */
24628 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET(value) (((value) & 0x00000080) >> 7)
24629 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value suitable for setting the register. */
24630 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET(value) (((value) << 7) & 0x00000080)
24631 
24632 /*
24633  * Field : MMC Receive UDP Good Frame Counter Interrupt Status - rxudpgfis
24634  *
24635  * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value
24636  * or the maximum value.
24637  *
24638  * Field Enumeration Values:
24639  *
24640  * Enum | Value | Description
24641  * :----------------------------------------------|:------|:-----------------------------
24642  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT | 0x0 | counter < half max
24643  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR | 0x1 | counter >= half max or max
24644  *
24645  * Field Access Macros:
24646  *
24647  */
24648 /*
24649  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
24650  *
24651  * counter < half max
24652  */
24653 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT 0x0
24654 /*
24655  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
24656  *
24657  * counter >= half max or max
24658  */
24659 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR 0x1
24660 
24661 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
24662 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB 8
24663 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
24664 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB 8
24665 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
24666 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH 1
24667 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
24668 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK 0x00000100
24669 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
24670 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK 0xfffffeff
24671 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
24672 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET 0x0
24673 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS field value from a register. */
24674 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET(value) (((value) & 0x00000100) >> 8)
24675 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value suitable for setting the register. */
24676 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET(value) (((value) << 8) & 0x00000100)
24677 
24678 /*
24679  * Field : MMC Receive UDP Error Frame Counter Interrupt Status - rxudperfis
24680  *
24681  * This bit is set when the rxudp_err_frms counter reaches half of the maximum
24682  * value or the maximum value.
24683  *
24684  * Field Enumeration Values:
24685  *
24686  * Enum | Value | Description
24687  * :-----------------------------------------------|:------|:-----------------------------
24688  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT | 0x0 | counter < half max
24689  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR | 0x1 | counter >= half max or max
24690  *
24691  * Field Access Macros:
24692  *
24693  */
24694 /*
24695  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
24696  *
24697  * counter < half max
24698  */
24699 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT 0x0
24700 /*
24701  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
24702  *
24703  * counter >= half max or max
24704  */
24705 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR 0x1
24706 
24707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
24708 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB 9
24709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
24710 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB 9
24711 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
24712 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH 1
24713 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
24714 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK 0x00000200
24715 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
24716 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK 0xfffffdff
24717 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
24718 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET 0x0
24719 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS field value from a register. */
24720 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET(value) (((value) & 0x00000200) >> 9)
24721 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value suitable for setting the register. */
24722 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET(value) (((value) << 9) & 0x00000200)
24723 
24724 /*
24725  * Field : MMC Receive TCP Good Frame Counter Interrupt Status - rxtcpgfis
24726  *
24727  * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value
24728  * or the maximum value.
24729  *
24730  * Field Enumeration Values:
24731  *
24732  * Enum | Value | Description
24733  * :----------------------------------------------|:------|:-----------------------------
24734  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT | 0x0 | counter < half max
24735  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR | 0x1 | counter >= half max or max
24736  *
24737  * Field Access Macros:
24738  *
24739  */
24740 /*
24741  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
24742  *
24743  * counter < half max
24744  */
24745 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT 0x0
24746 /*
24747  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
24748  *
24749  * counter >= half max or max
24750  */
24751 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR 0x1
24752 
24753 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
24754 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB 10
24755 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
24756 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB 10
24757 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
24758 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH 1
24759 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
24760 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK 0x00000400
24761 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
24762 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK 0xfffffbff
24763 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
24764 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET 0x0
24765 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS field value from a register. */
24766 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET(value) (((value) & 0x00000400) >> 10)
24767 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value suitable for setting the register. */
24768 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET(value) (((value) << 10) & 0x00000400)
24769 
24770 /*
24771  * Field : MMC Receive TCP Error Frame Counter Interrupt Status - rxtcperfis
24772  *
24773  * This bit is set when the rxtcp_err_frms counter reaches half of the maximum
24774  * value or the maximum value.
24775  *
24776  * Field Enumeration Values:
24777  *
24778  * Enum | Value | Description
24779  * :-----------------------------------------------|:------|:-----------------------------
24780  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT | 0x0 | counter < half max
24781  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR | 0x1 | counter >= half max or max
24782  *
24783  * Field Access Macros:
24784  *
24785  */
24786 /*
24787  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
24788  *
24789  * counter < half max
24790  */
24791 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT 0x0
24792 /*
24793  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
24794  *
24795  * counter >= half max or max
24796  */
24797 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR 0x1
24798 
24799 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
24800 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB 11
24801 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
24802 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB 11
24803 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
24804 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH 1
24805 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
24806 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK 0x00000800
24807 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
24808 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK 0xfffff7ff
24809 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
24810 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET 0x0
24811 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS field value from a register. */
24812 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET(value) (((value) & 0x00000800) >> 11)
24813 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value suitable for setting the register. */
24814 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET(value) (((value) << 11) & 0x00000800)
24815 
24816 /*
24817  * Field : MMC Receive ICMP Good Frame Counter Interrupt Status - rxicmpgfis
24818  *
24819  * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum
24820  * value or the maximum value.
24821  *
24822  * Field Enumeration Values:
24823  *
24824  * Enum | Value | Description
24825  * :-----------------------------------------------|:------|:-----------------------------
24826  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT | 0x0 | counter < half max
24827  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR | 0x1 | counter >= half max or max
24828  *
24829  * Field Access Macros:
24830  *
24831  */
24832 /*
24833  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
24834  *
24835  * counter < half max
24836  */
24837 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT 0x0
24838 /*
24839  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
24840  *
24841  * counter >= half max or max
24842  */
24843 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR 0x1
24844 
24845 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
24846 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB 12
24847 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
24848 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB 12
24849 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
24850 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH 1
24851 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
24852 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK 0x00001000
24853 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
24854 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK 0xffffefff
24855 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
24856 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET 0x0
24857 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS field value from a register. */
24858 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET(value) (((value) & 0x00001000) >> 12)
24859 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value suitable for setting the register. */
24860 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET(value) (((value) << 12) & 0x00001000)
24861 
24862 /*
24863  * Field : MMC Receive ICMP Error Frame Counter Interrupt Status - rxicmperfis
24864  *
24865  * This bit is set when the rxicmp_err_frms counter reaches half of the maximum
24866  * value or the maximum value.
24867  *
24868  * Field Enumeration Values:
24869  *
24870  * Enum | Value | Description
24871  * :------------------------------------------------|:------|:-----------------------------
24872  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT | 0x0 | counter < half max
24873  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR | 0x1 | counter >= half max or max
24874  *
24875  * Field Access Macros:
24876  *
24877  */
24878 /*
24879  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
24880  *
24881  * counter < half max
24882  */
24883 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT 0x0
24884 /*
24885  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
24886  *
24887  * counter >= half max or max
24888  */
24889 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1
24890 
24891 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
24892 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB 13
24893 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
24894 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB 13
24895 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
24896 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH 1
24897 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
24898 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK 0x00002000
24899 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
24900 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK 0xffffdfff
24901 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
24902 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET 0x0
24903 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS field value from a register. */
24904 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET(value) (((value) & 0x00002000) >> 13)
24905 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value suitable for setting the register. */
24906 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET(value) (((value) << 13) & 0x00002000)
24907 
24908 /*
24909  * Field : MMC Receive IPV4 Good Octet Counter Interrupt Status - rxipv4gois
24910  *
24911  * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum
24912  * value or the maximum value.
24913  *
24914  * Field Enumeration Values:
24915  *
24916  * Enum | Value | Description
24917  * :-----------------------------------------------|:------|:-----------------------------
24918  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT | 0x0 | counter < half max
24919  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR | 0x1 | counter >= half max or max
24920  *
24921  * Field Access Macros:
24922  *
24923  */
24924 /*
24925  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
24926  *
24927  * counter < half max
24928  */
24929 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT 0x0
24930 /*
24931  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
24932  *
24933  * counter >= half max or max
24934  */
24935 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR 0x1
24936 
24937 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
24938 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB 16
24939 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
24940 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB 16
24941 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
24942 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH 1
24943 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
24944 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK 0x00010000
24945 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
24946 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK 0xfffeffff
24947 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
24948 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET 0x0
24949 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS field value from a register. */
24950 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET(value) (((value) & 0x00010000) >> 16)
24951 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value suitable for setting the register. */
24952 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET(value) (((value) << 16) & 0x00010000)
24953 
24954 /*
24955  * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Status - rxipv4herois
24956  *
24957  * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the
24958  * maximum value or the maximum value.
24959  *
24960  * Field Enumeration Values:
24961  *
24962  * Enum | Value | Description
24963  * :-------------------------------------------------|:------|:-----------------------------
24964  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT | 0x0 | counter < half max
24965  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR | 0x1 | counter >= half max or max
24966  *
24967  * Field Access Macros:
24968  *
24969  */
24970 /*
24971  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
24972  *
24973  * counter < half max
24974  */
24975 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT 0x0
24976 /*
24977  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
24978  *
24979  * counter >= half max or max
24980  */
24981 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR 0x1
24982 
24983 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
24984 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB 17
24985 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
24986 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB 17
24987 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
24988 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH 1
24989 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
24990 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK 0x00020000
24991 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
24992 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK 0xfffdffff
24993 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
24994 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET 0x0
24995 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS field value from a register. */
24996 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET(value) (((value) & 0x00020000) >> 17)
24997 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value suitable for setting the register. */
24998 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET(value) (((value) << 17) & 0x00020000)
24999 
25000 /*
25001  * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Status - rxipv4nopayois
25002  *
25003  * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum
25004  * value or the maximum value.
25005  *
25006  * Field Enumeration Values:
25007  *
25008  * Enum | Value | Description
25009  * :---------------------------------------------------|:------|:-----------------------------
25010  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT | 0x0 | counter < half max
25011  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR | 0x1 | counter >= half max or max
25012  *
25013  * Field Access Macros:
25014  *
25015  */
25016 /*
25017  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
25018  *
25019  * counter < half max
25020  */
25021 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT 0x0
25022 /*
25023  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
25024  *
25025  * counter >= half max or max
25026  */
25027 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR 0x1
25028 
25029 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
25030 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB 18
25031 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
25032 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB 18
25033 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
25034 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH 1
25035 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
25036 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK 0x00040000
25037 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
25038 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK 0xfffbffff
25039 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
25040 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET 0x0
25041 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS field value from a register. */
25042 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET(value) (((value) & 0x00040000) >> 18)
25043 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value suitable for setting the register. */
25044 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET(value) (((value) << 18) & 0x00040000)
25045 
25046 /*
25047  * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - rxipv4fragois
25048  *
25049  * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum
25050  * value or the maximum value.
25051  *
25052  * Field Enumeration Values:
25053  *
25054  * Enum | Value | Description
25055  * :--------------------------------------------------|:------|:-----------------------------
25056  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT | 0x0 | counter < half max
25057  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR | 0x1 | counter >= half max or max
25058  *
25059  * Field Access Macros:
25060  *
25061  */
25062 /*
25063  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
25064  *
25065  * counter < half max
25066  */
25067 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT 0x0
25068 /*
25069  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
25070  *
25071  * counter >= half max or max
25072  */
25073 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR 0x1
25074 
25075 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
25076 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB 19
25077 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
25078 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB 19
25079 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
25080 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH 1
25081 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
25082 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK 0x00080000
25083 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
25084 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK 0xfff7ffff
25085 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
25086 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET 0x0
25087 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS field value from a register. */
25088 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET(value) (((value) & 0x00080000) >> 19)
25089 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value suitable for setting the register. */
25090 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET(value) (((value) << 19) & 0x00080000)
25091 
25092 /*
25093  * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - rxipv4udsblois
25094  *
25095  * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum
25096  * value or the maximum value.
25097  *
25098  * Field Enumeration Values:
25099  *
25100  * Enum | Value | Description
25101  * :---------------------------------------------------|:------|:-----------------------------
25102  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT | 0x0 | counter < half max
25103  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR | 0x1 | counter >= half max or max
25104  *
25105  * Field Access Macros:
25106  *
25107  */
25108 /*
25109  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
25110  *
25111  * counter < half max
25112  */
25113 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT 0x0
25114 /*
25115  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
25116  *
25117  * counter >= half max or max
25118  */
25119 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR 0x1
25120 
25121 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
25122 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB 20
25123 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
25124 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB 20
25125 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
25126 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH 1
25127 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
25128 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK 0x00100000
25129 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
25130 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK 0xffefffff
25131 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
25132 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET 0x0
25133 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS field value from a register. */
25134 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET(value) (((value) & 0x00100000) >> 20)
25135 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value suitable for setting the register. */
25136 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET(value) (((value) << 20) & 0x00100000)
25137 
25138 /*
25139  * Field : MMC Receive IPV6 Good Octet Counter Interrupt Status - rxipv6gois
25140  *
25141  * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum
25142  * value or the maximum value.
25143  *
25144  * Field Enumeration Values:
25145  *
25146  * Enum | Value | Description
25147  * :-----------------------------------------------|:------|:-----------------------------
25148  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT | 0x0 | counter < half max
25149  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR | 0x1 | counter >= half max or max
25150  *
25151  * Field Access Macros:
25152  *
25153  */
25154 /*
25155  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
25156  *
25157  * counter < half max
25158  */
25159 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT 0x0
25160 /*
25161  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
25162  *
25163  * counter >= half max or max
25164  */
25165 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR 0x1
25166 
25167 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
25168 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB 21
25169 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
25170 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB 21
25171 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
25172 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH 1
25173 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
25174 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK 0x00200000
25175 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
25176 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK 0xffdfffff
25177 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
25178 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET 0x0
25179 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS field value from a register. */
25180 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET(value) (((value) & 0x00200000) >> 21)
25181 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value suitable for setting the register. */
25182 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET(value) (((value) << 21) & 0x00200000)
25183 
25184 /*
25185  * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Status - rxipv6herois
25186  *
25187  * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the
25188  * maximum value or the maximum value.
25189  *
25190  * Field Enumeration Values:
25191  *
25192  * Enum | Value | Description
25193  * :-------------------------------------------------|:------|:-----------------------------
25194  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT | 0x0 | counter < half max
25195  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR | 0x1 | counter >= half max or max
25196  *
25197  * Field Access Macros:
25198  *
25199  */
25200 /*
25201  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
25202  *
25203  * counter < half max
25204  */
25205 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT 0x0
25206 /*
25207  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
25208  *
25209  * counter >= half max or max
25210  */
25211 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR 0x1
25212 
25213 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
25214 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB 22
25215 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
25216 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB 22
25217 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
25218 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH 1
25219 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
25220 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK 0x00400000
25221 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
25222 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK 0xffbfffff
25223 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
25224 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET 0x0
25225 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS field value from a register. */
25226 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET(value) (((value) & 0x00400000) >> 22)
25227 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value suitable for setting the register. */
25228 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET(value) (((value) << 22) & 0x00400000)
25229 
25230 /*
25231  * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Status - rxipv6nopayois
25232  *
25233  * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum
25234  * value or the maximum value.
25235  *
25236  * Field Enumeration Values:
25237  *
25238  * Enum | Value | Description
25239  * :---------------------------------------------------|:------|:-----------------------------
25240  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT | 0x0 | counter < half max
25241  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR | 0x1 | counter >= half max or max
25242  *
25243  * Field Access Macros:
25244  *
25245  */
25246 /*
25247  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
25248  *
25249  * counter < half max
25250  */
25251 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT 0x0
25252 /*
25253  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
25254  *
25255  * counter >= half max or max
25256  */
25257 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR 0x1
25258 
25259 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
25260 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB 23
25261 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
25262 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB 23
25263 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
25264 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH 1
25265 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
25266 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK 0x00800000
25267 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
25268 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK 0xff7fffff
25269 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
25270 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET 0x0
25271 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS field value from a register. */
25272 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET(value) (((value) & 0x00800000) >> 23)
25273 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value suitable for setting the register. */
25274 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET(value) (((value) << 23) & 0x00800000)
25275 
25276 /*
25277  * Field : MMC Receive UDP Good Octet Counter Interrupt Status - rxudpgois
25278  *
25279  * This bit is set when the rxudp_gd_octets counter reaches half of the maximum
25280  * value or the maximum value.
25281  *
25282  * Field Enumeration Values:
25283  *
25284  * Enum | Value | Description
25285  * :----------------------------------------------|:------|:-----------------------------
25286  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT | 0x0 | counter < half max
25287  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR | 0x1 | counter >= half max or max
25288  *
25289  * Field Access Macros:
25290  *
25291  */
25292 /*
25293  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
25294  *
25295  * counter < half max
25296  */
25297 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT 0x0
25298 /*
25299  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
25300  *
25301  * counter >= half max or max
25302  */
25303 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR 0x1
25304 
25305 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
25306 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB 24
25307 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
25308 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB 24
25309 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
25310 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH 1
25311 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
25312 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK 0x01000000
25313 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
25314 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK 0xfeffffff
25315 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
25316 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET 0x0
25317 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS field value from a register. */
25318 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET(value) (((value) & 0x01000000) >> 24)
25319 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value suitable for setting the register. */
25320 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET(value) (((value) << 24) & 0x01000000)
25321 
25322 /*
25323  * Field : MMC Receive UDP Error Octet Counter Interrupt Status - rxudperois
25324  *
25325  * This bit is set when the rxudp_err_octets counter reaches half the maximum value
25326  * or the maximum value.
25327  *
25328  * Field Enumeration Values:
25329  *
25330  * Enum | Value | Description
25331  * :-----------------------------------------------|:------|:-----------------------------
25332  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT | 0x0 | counter < half max
25333  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR | 0x1 | counter >= half max or max
25334  *
25335  * Field Access Macros:
25336  *
25337  */
25338 /*
25339  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
25340  *
25341  * counter < half max
25342  */
25343 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT 0x0
25344 /*
25345  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
25346  *
25347  * counter >= half max or max
25348  */
25349 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR 0x1
25350 
25351 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
25352 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB 25
25353 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
25354 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB 25
25355 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
25356 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH 1
25357 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
25358 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK 0x02000000
25359 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
25360 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK 0xfdffffff
25361 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
25362 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET 0x0
25363 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS field value from a register. */
25364 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET(value) (((value) & 0x02000000) >> 25)
25365 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value suitable for setting the register. */
25366 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET(value) (((value) << 25) & 0x02000000)
25367 
25368 /*
25369  * Field : MMC Receive TCP Good Octet Counter Interrupt Status - rxtcpgois
25370  *
25371  * This bit is set when the rxtcp_gd_octets counter reaches half the maximum value
25372  * or the maximum value.
25373  *
25374  * Field Enumeration Values:
25375  *
25376  * Enum | Value | Description
25377  * :----------------------------------------------|:------|:-----------------------------
25378  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT | 0x0 | counter < half max
25379  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR | 0x1 | counter >= half max or max
25380  *
25381  * Field Access Macros:
25382  *
25383  */
25384 /*
25385  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
25386  *
25387  * counter < half max
25388  */
25389 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT 0x0
25390 /*
25391  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
25392  *
25393  * counter >= half max or max
25394  */
25395 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR 0x1
25396 
25397 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
25398 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB 26
25399 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
25400 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB 26
25401 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
25402 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH 1
25403 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
25404 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK 0x04000000
25405 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
25406 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK 0xfbffffff
25407 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
25408 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET 0x0
25409 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS field value from a register. */
25410 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET(value) (((value) & 0x04000000) >> 26)
25411 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value suitable for setting the register. */
25412 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET(value) (((value) << 26) & 0x04000000)
25413 
25414 /*
25415  * Field : MMC Receive TCP Error Octet Counter Interrupt Status - rxtcperois
25416  *
25417  * This bit is set when the rxtcp_err_octets counter reaches half of the maximum
25418  * value or the maximum value.
25419  *
25420  * Field Enumeration Values:
25421  *
25422  * Enum | Value | Description
25423  * :-----------------------------------------------|:------|:-----------------------------
25424  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT | 0x0 | counter < half max
25425  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR | 0x1 | counter >= half max or max
25426  *
25427  * Field Access Macros:
25428  *
25429  */
25430 /*
25431  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
25432  *
25433  * counter < half max
25434  */
25435 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT 0x0
25436 /*
25437  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
25438  *
25439  * counter >= half max or max
25440  */
25441 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR 0x1
25442 
25443 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
25444 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB 27
25445 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
25446 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB 27
25447 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
25448 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH 1
25449 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
25450 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK 0x08000000
25451 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
25452 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK 0xf7ffffff
25453 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
25454 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET 0x0
25455 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS field value from a register. */
25456 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET(value) (((value) & 0x08000000) >> 27)
25457 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value suitable for setting the register. */
25458 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET(value) (((value) << 27) & 0x08000000)
25459 
25460 /*
25461  * Field : MMC Receive ICMP Good Octet Counter Interrupt Status - rxicmpgois
25462  *
25463  * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum
25464  * value or the maximum value.
25465  *
25466  * Field Enumeration Values:
25467  *
25468  * Enum | Value | Description
25469  * :-----------------------------------------------|:------|:-----------------------------
25470  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT | 0x0 | counter < half max
25471  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR | 0x1 | counter >= half max or max
25472  *
25473  * Field Access Macros:
25474  *
25475  */
25476 /*
25477  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
25478  *
25479  * counter < half max
25480  */
25481 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT 0x0
25482 /*
25483  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
25484  *
25485  * counter >= half max or max
25486  */
25487 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR 0x1
25488 
25489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
25490 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB 28
25491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
25492 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB 28
25493 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
25494 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH 1
25495 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
25496 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK 0x10000000
25497 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
25498 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK 0xefffffff
25499 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
25500 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET 0x0
25501 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS field value from a register. */
25502 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET(value) (((value) & 0x10000000) >> 28)
25503 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value suitable for setting the register. */
25504 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET(value) (((value) << 28) & 0x10000000)
25505 
25506 /*
25507  * Field : MMC Receive ICMP Error Octet Counter Interrupt Status - rxicmperois
25508  *
25509  * This bit is set when the rxicmp_err_octets counter reaches half of the maximum
25510  * value or the maximum value.
25511  *
25512  * Field Enumeration Values:
25513  *
25514  * Enum | Value | Description
25515  * :------------------------------------------------|:------|:-----------------------------
25516  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT | 0x0 | counter < half max
25517  * ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR | 0x1 | counter >= half max or max
25518  *
25519  * Field Access Macros:
25520  *
25521  */
25522 /*
25523  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
25524  *
25525  * counter < half max
25526  */
25527 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT 0x0
25528 /*
25529  * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
25530  *
25531  * counter >= half max or max
25532  */
25533 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1
25534 
25535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
25536 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB 29
25537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
25538 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB 29
25539 /* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
25540 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH 1
25541 /* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
25542 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK 0x20000000
25543 /* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
25544 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK 0xdfffffff
25545 /* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
25546 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET 0x0
25547 /* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS field value from a register. */
25548 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET(value) (((value) & 0x20000000) >> 29)
25549 /* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value suitable for setting the register. */
25550 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET(value) (((value) << 29) & 0x20000000)
25551 
25552 #ifndef __ASSEMBLY__
25553 /*
25554  * WARNING: The C register and register group struct declarations are provided for
25555  * convenience and illustrative purposes. They should, however, be used with
25556  * caution as the C language standard provides no guarantees about the alignment or
25557  * atomicity of device memory accesses. The recommended practice for writing
25558  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25559  * alt_write_word() functions.
25560  *
25561  * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT.
25562  */
25563 struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s
25564 {
25565  const uint32_t rxipv4gfis : 1; /* MMC Receive IPV4 Good Frame Counter Interrupt Status */
25566  const uint32_t rxipv4herfis : 1; /* MMC Receive IPV4 Header Error Frame Counter Interrupt Status */
25567  const uint32_t rxipv4nopayfis : 1; /* MMC Receive IPV4 No Payload Frame Counter Interrupt Status */
25568  const uint32_t rxipv4fragfis : 1; /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Status */
25569  const uint32_t rxipv4udsblfis : 1; /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status */
25570  const uint32_t rxipv6gfis : 1; /* MMC Receive IPV6 Good Frame Counter Interrupt Status */
25571  const uint32_t rxipv6herfis : 1; /* MMC Receive IPV6 Header Error Frame Counter Interrupt Status */
25572  const uint32_t rxipv6nopayfis : 1; /* MMC Receive IPV6 No Payload Frame Counter Interrupt Status */
25573  const uint32_t rxudpgfis : 1; /* MMC Receive UDP Good Frame Counter Interrupt Status */
25574  const uint32_t rxudperfis : 1; /* MMC Receive UDP Error Frame Counter Interrupt Status */
25575  const uint32_t rxtcpgfis : 1; /* MMC Receive TCP Good Frame Counter Interrupt Status */
25576  const uint32_t rxtcperfis : 1; /* MMC Receive TCP Error Frame Counter Interrupt Status */
25577  const uint32_t rxicmpgfis : 1; /* MMC Receive ICMP Good Frame Counter Interrupt Status */
25578  const uint32_t rxicmperfis : 1; /* MMC Receive ICMP Error Frame Counter Interrupt Status */
25579  uint32_t : 2; /* *UNDEFINED* */
25580  const uint32_t rxipv4gois : 1; /* MMC Receive IPV4 Good Octet Counter Interrupt Status */
25581  const uint32_t rxipv4herois : 1; /* MMC Receive IPV4 Header Error Octet Counter Interrupt Status */
25582  const uint32_t rxipv4nopayois : 1; /* MMC Receive IPV4 No Payload Octet Counter Interrupt Status */
25583  const uint32_t rxipv4fragois : 1; /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Status */
25584  const uint32_t rxipv4udsblois : 1; /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status */
25585  const uint32_t rxipv6gois : 1; /* MMC Receive IPV6 Good Octet Counter Interrupt Status */
25586  const uint32_t rxipv6herois : 1; /* MMC Receive IPV6 Header Error Octet Counter Interrupt Status */
25587  const uint32_t rxipv6nopayois : 1; /* MMC Receive IPV6 No Payload Octet Counter Interrupt Status */
25588  const uint32_t rxudpgois : 1; /* MMC Receive UDP Good Octet Counter Interrupt Status */
25589  const uint32_t rxudperois : 1; /* MMC Receive UDP Error Octet Counter Interrupt Status */
25590  const uint32_t rxtcpgois : 1; /* MMC Receive TCP Good Octet Counter Interrupt Status */
25591  const uint32_t rxtcperois : 1; /* MMC Receive TCP Error Octet Counter Interrupt Status */
25592  const uint32_t rxicmpgois : 1; /* MMC Receive ICMP Good Octet Counter Interrupt Status */
25593  const uint32_t rxicmperois : 1; /* MMC Receive ICMP Error Octet Counter Interrupt Status */
25594  uint32_t : 2; /* *UNDEFINED* */
25595 };
25596 
25597 /* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT. */
25598 typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_t;
25599 #endif /* __ASSEMBLY__ */
25600 
25601 /* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register from the beginning of the component. */
25602 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST 0x208
25603 /* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register. */
25604 #define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST))
25605 
25606 /*
25607  * Register : Register 132 (rxipv4_gd_frms Register) - rxipv4_gd_frms
25608  *
25609  * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
25610  *
25611  * Register Layout
25612  *
25613  * Bits | Access | Reset | Description
25614  * :-------|:-------|:------|:---------------
25615  * [31:0] | R | 0x0 | rxipv4_gd_frms
25616  *
25617  */
25618 /*
25619  * Field : rxipv4_gd_frms - cnt
25620  *
25621  * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
25622  *
25623  * Field Access Macros:
25624  *
25625  */
25626 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
25627 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_LSB 0
25628 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
25629 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_MSB 31
25630 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
25631 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_WIDTH 32
25632 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
25633 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET_MSK 0xffffffff
25634 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
25635 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_CLR_MSK 0x00000000
25636 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
25637 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_RESET 0x0
25638 /* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT field value from a register. */
25639 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25640 /* Produces a ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value suitable for setting the register. */
25641 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25642 
25643 #ifndef __ASSEMBLY__
25644 /*
25645  * WARNING: The C register and register group struct declarations are provided for
25646  * convenience and illustrative purposes. They should, however, be used with
25647  * caution as the C language standard provides no guarantees about the alignment or
25648  * atomicity of device memory accesses. The recommended practice for writing
25649  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25650  * alt_write_word() functions.
25651  *
25652  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS.
25653  */
25654 struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s
25655 {
25656  const uint32_t cnt : 32; /* rxipv4_gd_frms */
25657 };
25658 
25659 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS. */
25660 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t;
25661 #endif /* __ASSEMBLY__ */
25662 
25663 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register from the beginning of the component. */
25664 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST 0x210
25665 /* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register. */
25666 #define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST))
25667 
25668 /*
25669  * Register : Register 133 (rxipv4_hdrerr_frms Register) - rxipv4_hdrerr_frms
25670  *
25671  * Number of IPv4 datagrams received with header (checksum, length, or version
25672  * mismatch) errors
25673  *
25674  * Register Layout
25675  *
25676  * Bits | Access | Reset | Description
25677  * :-------|:-------|:------|:-------------------
25678  * [31:0] | R | 0x0 | rxipv4_hdrerr_frms
25679  *
25680  */
25681 /*
25682  * Field : rxipv4_hdrerr_frms - cnt
25683  *
25684  * Number of IPv4 datagrams received with header (checksum, length, or version
25685  * mismatch) errors
25686  *
25687  * Field Access Macros:
25688  *
25689  */
25690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
25691 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_LSB 0
25692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
25693 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_MSB 31
25694 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
25695 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_WIDTH 32
25696 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
25697 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET_MSK 0xffffffff
25698 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
25699 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_CLR_MSK 0x00000000
25700 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
25701 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_RESET 0x0
25702 /* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT field value from a register. */
25703 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25704 /* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value suitable for setting the register. */
25705 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25706 
25707 #ifndef __ASSEMBLY__
25708 /*
25709  * WARNING: The C register and register group struct declarations are provided for
25710  * convenience and illustrative purposes. They should, however, be used with
25711  * caution as the C language standard provides no guarantees about the alignment or
25712  * atomicity of device memory accesses. The recommended practice for writing
25713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25714  * alt_write_word() functions.
25715  *
25716  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS.
25717  */
25718 struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s
25719 {
25720  const uint32_t cnt : 32; /* rxipv4_hdrerr_frms */
25721 };
25722 
25723 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS. */
25724 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t;
25725 #endif /* __ASSEMBLY__ */
25726 
25727 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register from the beginning of the component. */
25728 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST 0x214
25729 /* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register. */
25730 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST))
25731 
25732 /*
25733  * Register : Register 134 (rxipv4_nopay_frms Register) - rxipv4_nopay_frms
25734  *
25735  * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
25736  * payload processed by the Checksum engine
25737  *
25738  * Register Layout
25739  *
25740  * Bits | Access | Reset | Description
25741  * :-------|:-------|:------|:------------------
25742  * [31:0] | R | 0x0 | rxipv4_nopay_frms
25743  *
25744  */
25745 /*
25746  * Field : rxipv4_nopay_frms - cnt
25747  *
25748  * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
25749  * payload processed by the Checksum engine
25750  *
25751  * Field Access Macros:
25752  *
25753  */
25754 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
25755 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_LSB 0
25756 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
25757 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_MSB 31
25758 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
25759 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_WIDTH 32
25760 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
25761 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET_MSK 0xffffffff
25762 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
25763 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_CLR_MSK 0x00000000
25764 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
25765 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_RESET 0x0
25766 /* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT field value from a register. */
25767 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25768 /* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value suitable for setting the register. */
25769 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25770 
25771 #ifndef __ASSEMBLY__
25772 /*
25773  * WARNING: The C register and register group struct declarations are provided for
25774  * convenience and illustrative purposes. They should, however, be used with
25775  * caution as the C language standard provides no guarantees about the alignment or
25776  * atomicity of device memory accesses. The recommended practice for writing
25777  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25778  * alt_write_word() functions.
25779  *
25780  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS.
25781  */
25782 struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s
25783 {
25784  const uint32_t cnt : 32; /* rxipv4_nopay_frms */
25785 };
25786 
25787 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS. */
25788 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t;
25789 #endif /* __ASSEMBLY__ */
25790 
25791 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register from the beginning of the component. */
25792 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST 0x218
25793 /* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register. */
25794 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST))
25795 
25796 /*
25797  * Register : Register 135 (rxipv4_frag_frms Register) - rxipv4_frag_frms
25798  *
25799  * Number of good IPv4 datagrams with fragmentation
25800  *
25801  * Register Layout
25802  *
25803  * Bits | Access | Reset | Description
25804  * :-------|:-------|:------|:-----------------
25805  * [31:0] | R | 0x0 | rxipv4_frag_frms
25806  *
25807  */
25808 /*
25809  * Field : rxipv4_frag_frms - cnt
25810  *
25811  * Number of good IPv4 datagrams with fragmentation
25812  *
25813  * Field Access Macros:
25814  *
25815  */
25816 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
25817 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_LSB 0
25818 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
25819 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_MSB 31
25820 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
25821 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_WIDTH 32
25822 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
25823 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET_MSK 0xffffffff
25824 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
25825 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_CLR_MSK 0x00000000
25826 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
25827 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_RESET 0x0
25828 /* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT field value from a register. */
25829 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25830 /* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value suitable for setting the register. */
25831 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25832 
25833 #ifndef __ASSEMBLY__
25834 /*
25835  * WARNING: The C register and register group struct declarations are provided for
25836  * convenience and illustrative purposes. They should, however, be used with
25837  * caution as the C language standard provides no guarantees about the alignment or
25838  * atomicity of device memory accesses. The recommended practice for writing
25839  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25840  * alt_write_word() functions.
25841  *
25842  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS.
25843  */
25844 struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s
25845 {
25846  const uint32_t cnt : 32; /* rxipv4_frag_frms */
25847 };
25848 
25849 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS. */
25850 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t;
25851 #endif /* __ASSEMBLY__ */
25852 
25853 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register from the beginning of the component. */
25854 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST 0x21c
25855 /* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register. */
25856 #define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST))
25857 
25858 /*
25859  * Register : Register 136 (rxipv4_udsbl_frms Register) - rxipv4_udsbl_frms
25860  *
25861  * Number of good IPv4 datagrams received that had a UDP payload with checksum
25862  * disabled
25863  *
25864  * Register Layout
25865  *
25866  * Bits | Access | Reset | Description
25867  * :-------|:-------|:------|:------------------
25868  * [31:0] | R | 0x0 | rxipv4_udsbl_frms
25869  *
25870  */
25871 /*
25872  * Field : rxipv4_udsbl_frms - cnt
25873  *
25874  * Number of good IPv4 datagrams received that had a UDP payload with checksum
25875  * disabled
25876  *
25877  * Field Access Macros:
25878  *
25879  */
25880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
25881 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_LSB 0
25882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
25883 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_MSB 31
25884 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
25885 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_WIDTH 32
25886 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
25887 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET_MSK 0xffffffff
25888 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
25889 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_CLR_MSK 0x00000000
25890 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
25891 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_RESET 0x0
25892 /* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT field value from a register. */
25893 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25894 /* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value suitable for setting the register. */
25895 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25896 
25897 #ifndef __ASSEMBLY__
25898 /*
25899  * WARNING: The C register and register group struct declarations are provided for
25900  * convenience and illustrative purposes. They should, however, be used with
25901  * caution as the C language standard provides no guarantees about the alignment or
25902  * atomicity of device memory accesses. The recommended practice for writing
25903  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25904  * alt_write_word() functions.
25905  *
25906  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS.
25907  */
25908 struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s
25909 {
25910  const uint32_t cnt : 32; /* rxipv4_udsbl_frms */
25911 };
25912 
25913 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS. */
25914 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t;
25915 #endif /* __ASSEMBLY__ */
25916 
25917 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register from the beginning of the component. */
25918 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST 0x220
25919 /* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register. */
25920 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST))
25921 
25922 /*
25923  * Register : Register 137 (rxipv6_gd_frms Register) - rxipv6_gd_frms
25924  *
25925  * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
25926  *
25927  * Register Layout
25928  *
25929  * Bits | Access | Reset | Description
25930  * :-------|:-------|:------|:---------------
25931  * [31:0] | R | 0x0 | rxipv6_gd_frms
25932  *
25933  */
25934 /*
25935  * Field : rxipv6_gd_frms - cnt
25936  *
25937  * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
25938  *
25939  * Field Access Macros:
25940  *
25941  */
25942 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
25943 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_LSB 0
25944 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
25945 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_MSB 31
25946 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
25947 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_WIDTH 32
25948 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
25949 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET_MSK 0xffffffff
25950 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
25951 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_CLR_MSK 0x00000000
25952 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
25953 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_RESET 0x0
25954 /* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT field value from a register. */
25955 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
25956 /* Produces a ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value suitable for setting the register. */
25957 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
25958 
25959 #ifndef __ASSEMBLY__
25960 /*
25961  * WARNING: The C register and register group struct declarations are provided for
25962  * convenience and illustrative purposes. They should, however, be used with
25963  * caution as the C language standard provides no guarantees about the alignment or
25964  * atomicity of device memory accesses. The recommended practice for writing
25965  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
25966  * alt_write_word() functions.
25967  *
25968  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS.
25969  */
25970 struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s
25971 {
25972  const uint32_t cnt : 32; /* rxipv6_gd_frms */
25973 };
25974 
25975 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS. */
25976 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t;
25977 #endif /* __ASSEMBLY__ */
25978 
25979 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register from the beginning of the component. */
25980 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST 0x224
25981 /* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register. */
25982 #define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST))
25983 
25984 /*
25985  * Register : Register 138 (rxipv6_hdrerr_frms Register) - rxipv6_hdrerr_frms
25986  *
25987  * Number of IPv6 datagrams received with header errors (length or version
25988  * mismatch)
25989  *
25990  * Register Layout
25991  *
25992  * Bits | Access | Reset | Description
25993  * :-------|:-------|:------|:-------------------
25994  * [31:0] | R | 0x0 | rxipv6_hdrerr_frms
25995  *
25996  */
25997 /*
25998  * Field : rxipv6_hdrerr_frms - cnt
25999  *
26000  * Number of IPv6 datagrams received with header errors (length or version
26001  * mismatch)
26002  *
26003  * Field Access Macros:
26004  *
26005  */
26006 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
26007 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_LSB 0
26008 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
26009 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_MSB 31
26010 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
26011 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_WIDTH 32
26012 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
26013 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET_MSK 0xffffffff
26014 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
26015 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_CLR_MSK 0x00000000
26016 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
26017 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_RESET 0x0
26018 /* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT field value from a register. */
26019 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26020 /* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value suitable for setting the register. */
26021 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26022 
26023 #ifndef __ASSEMBLY__
26024 /*
26025  * WARNING: The C register and register group struct declarations are provided for
26026  * convenience and illustrative purposes. They should, however, be used with
26027  * caution as the C language standard provides no guarantees about the alignment or
26028  * atomicity of device memory accesses. The recommended practice for writing
26029  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26030  * alt_write_word() functions.
26031  *
26032  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS.
26033  */
26034 struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s
26035 {
26036  const uint32_t cnt : 32; /* rxipv6_hdrerr_frms */
26037 };
26038 
26039 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS. */
26040 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t;
26041 #endif /* __ASSEMBLY__ */
26042 
26043 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register from the beginning of the component. */
26044 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST 0x228
26045 /* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register. */
26046 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST))
26047 
26048 /*
26049  * Register : Register 139 (rxipv6_nopay_frms) - rxipv6_nopay_frms
26050  *
26051  * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
26052  * payload. This includes all IPv6 datagrams with fragmentation or security
26053  * extension headers
26054  *
26055  * Register Layout
26056  *
26057  * Bits | Access | Reset | Description
26058  * :-------|:-------|:------|:------------------
26059  * [31:0] | R | 0x0 | rxipv6_nopay_frms
26060  *
26061  */
26062 /*
26063  * Field : rxipv6_nopay_frms - cnt
26064  *
26065  * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
26066  * payload. This includes all IPv6 datagrams with fragmentation or security
26067  * extension headers
26068  *
26069  * Field Access Macros:
26070  *
26071  */
26072 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
26073 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_LSB 0
26074 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
26075 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_MSB 31
26076 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
26077 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_WIDTH 32
26078 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
26079 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET_MSK 0xffffffff
26080 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
26081 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_CLR_MSK 0x00000000
26082 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
26083 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_RESET 0x0
26084 /* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT field value from a register. */
26085 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26086 /* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value suitable for setting the register. */
26087 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26088 
26089 #ifndef __ASSEMBLY__
26090 /*
26091  * WARNING: The C register and register group struct declarations are provided for
26092  * convenience and illustrative purposes. They should, however, be used with
26093  * caution as the C language standard provides no guarantees about the alignment or
26094  * atomicity of device memory accesses. The recommended practice for writing
26095  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26096  * alt_write_word() functions.
26097  *
26098  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS.
26099  */
26100 struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s
26101 {
26102  const uint32_t cnt : 32; /* rxipv6_nopay_frms */
26103 };
26104 
26105 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS. */
26106 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t;
26107 #endif /* __ASSEMBLY__ */
26108 
26109 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register from the beginning of the component. */
26110 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST 0x22c
26111 /* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register. */
26112 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST))
26113 
26114 /*
26115  * Register : Register 140 (rxudp_gd_frms Register) - rxudp_gd_frms
26116  *
26117  * Number of good IP datagrams with a good UDP payload. This counter is not updated
26118  * when the counter is incremented
26119  *
26120  * Register Layout
26121  *
26122  * Bits | Access | Reset | Description
26123  * :-------|:-------|:------|:--------------
26124  * [31:0] | R | 0x0 | rxudp_gd_frms
26125  *
26126  */
26127 /*
26128  * Field : rxudp_gd_frms - cnt
26129  *
26130  * Number of good IP datagrams with a good UDP payload. This counter is not updated
26131  * when the counter is incremented
26132  *
26133  * Field Access Macros:
26134  *
26135  */
26136 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
26137 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_LSB 0
26138 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
26139 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_MSB 31
26140 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
26141 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_WIDTH 32
26142 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
26143 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET_MSK 0xffffffff
26144 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
26145 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_CLR_MSK 0x00000000
26146 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
26147 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_RESET 0x0
26148 /* Extracts the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT field value from a register. */
26149 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26150 /* Produces a ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value suitable for setting the register. */
26151 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26152 
26153 #ifndef __ASSEMBLY__
26154 /*
26155  * WARNING: The C register and register group struct declarations are provided for
26156  * convenience and illustrative purposes. They should, however, be used with
26157  * caution as the C language standard provides no guarantees about the alignment or
26158  * atomicity of device memory accesses. The recommended practice for writing
26159  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26160  * alt_write_word() functions.
26161  *
26162  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS.
26163  */
26164 struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s
26165 {
26166  const uint32_t cnt : 32; /* rxudp_gd_frms */
26167 };
26168 
26169 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS. */
26170 typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s ALT_EMAC_GMAC_RXUDP_GD_FRMS_t;
26171 #endif /* __ASSEMBLY__ */
26172 
26173 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register from the beginning of the component. */
26174 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST 0x230
26175 /* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register. */
26176 #define ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST))
26177 
26178 /*
26179  * Register : Register 141 (rxudp_err_frms Register) - rxudp_err_frms
26180  *
26181  * Number of good IP datagrams whose UDP payload has a checksum error
26182  *
26183  * Register Layout
26184  *
26185  * Bits | Access | Reset | Description
26186  * :-------|:-------|:------|:---------------
26187  * [31:0] | R | 0x0 | rxudp_err_frms
26188  *
26189  */
26190 /*
26191  * Field : rxudp_err_frms - cnt
26192  *
26193  * Number of good IP datagrams whose UDP payload has a checksum error
26194  *
26195  * Field Access Macros:
26196  *
26197  */
26198 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
26199 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_LSB 0
26200 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
26201 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_MSB 31
26202 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
26203 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_WIDTH 32
26204 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
26205 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET_MSK 0xffffffff
26206 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
26207 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_CLR_MSK 0x00000000
26208 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
26209 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_RESET 0x0
26210 /* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT field value from a register. */
26211 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26212 /* Produces a ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value suitable for setting the register. */
26213 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26214 
26215 #ifndef __ASSEMBLY__
26216 /*
26217  * WARNING: The C register and register group struct declarations are provided for
26218  * convenience and illustrative purposes. They should, however, be used with
26219  * caution as the C language standard provides no guarantees about the alignment or
26220  * atomicity of device memory accesses. The recommended practice for writing
26221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26222  * alt_write_word() functions.
26223  *
26224  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS.
26225  */
26226 struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s
26227 {
26228  const uint32_t cnt : 32; /* rxudp_err_frms */
26229 };
26230 
26231 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS. */
26232 typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t;
26233 #endif /* __ASSEMBLY__ */
26234 
26235 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register from the beginning of the component. */
26236 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST 0x234
26237 /* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register. */
26238 #define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST))
26239 
26240 /*
26241  * Register : Register 142 (rxtcp_gd_frms Register) - rxtcp_gd_frms
26242  *
26243  * Number of good IP datagrams with a good TCP payload
26244  *
26245  * Register Layout
26246  *
26247  * Bits | Access | Reset | Description
26248  * :-------|:-------|:------|:-----------------------
26249  * [31:0] | R | 0x0 | rxtcp_gd_frms Register
26250  *
26251  */
26252 /*
26253  * Field : rxtcp_gd_frms Register - cnt
26254  *
26255  * Number of good IP datagrams with a good TCP payload
26256  *
26257  * Field Access Macros:
26258  *
26259  */
26260 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
26261 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_LSB 0
26262 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
26263 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_MSB 31
26264 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
26265 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_WIDTH 32
26266 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
26267 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET_MSK 0xffffffff
26268 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
26269 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_CLR_MSK 0x00000000
26270 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
26271 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_RESET 0x0
26272 /* Extracts the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT field value from a register. */
26273 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26274 /* Produces a ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value suitable for setting the register. */
26275 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26276 
26277 #ifndef __ASSEMBLY__
26278 /*
26279  * WARNING: The C register and register group struct declarations are provided for
26280  * convenience and illustrative purposes. They should, however, be used with
26281  * caution as the C language standard provides no guarantees about the alignment or
26282  * atomicity of device memory accesses. The recommended practice for writing
26283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26284  * alt_write_word() functions.
26285  *
26286  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS.
26287  */
26288 struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s
26289 {
26290  const uint32_t cnt : 32; /* rxtcp_gd_frms Register */
26291 };
26292 
26293 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS. */
26294 typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s ALT_EMAC_GMAC_RXTCP_GD_FRMS_t;
26295 #endif /* __ASSEMBLY__ */
26296 
26297 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register from the beginning of the component. */
26298 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST 0x238
26299 /* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register. */
26300 #define ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST))
26301 
26302 /*
26303  * Register : Register 143 (rxtcp_err_frms Register) - rxtcp_err_frms
26304  *
26305  * Number of good IP datagrams whose TCP payload has a checksum error
26306  *
26307  * Register Layout
26308  *
26309  * Bits | Access | Reset | Description
26310  * :-------|:-------|:------|:---------------
26311  * [31:0] | R | 0x0 | rxtcp_err_frms
26312  *
26313  */
26314 /*
26315  * Field : rxtcp_err_frms - cnt
26316  *
26317  * Number of good IP datagrams whose TCP payload has a checksum error
26318  *
26319  * Field Access Macros:
26320  *
26321  */
26322 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
26323 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_LSB 0
26324 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
26325 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_MSB 31
26326 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
26327 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_WIDTH 32
26328 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
26329 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET_MSK 0xffffffff
26330 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
26331 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_CLR_MSK 0x00000000
26332 /* The reset value of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
26333 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_RESET 0x0
26334 /* Extracts the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT field value from a register. */
26335 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26336 /* Produces a ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value suitable for setting the register. */
26337 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26338 
26339 #ifndef __ASSEMBLY__
26340 /*
26341  * WARNING: The C register and register group struct declarations are provided for
26342  * convenience and illustrative purposes. They should, however, be used with
26343  * caution as the C language standard provides no guarantees about the alignment or
26344  * atomicity of device memory accesses. The recommended practice for writing
26345  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26346  * alt_write_word() functions.
26347  *
26348  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS.
26349  */
26350 struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s
26351 {
26352  const uint32_t cnt : 32; /* rxtcp_err_frms */
26353 };
26354 
26355 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS. */
26356 typedef volatile struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t;
26357 #endif /* __ASSEMBLY__ */
26358 
26359 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register from the beginning of the component. */
26360 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST 0x23c
26361 /* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register. */
26362 #define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST))
26363 
26364 /*
26365  * Register : Register 144 (rxicmp_gd_frms Register) - rxicmp_gd_frms
26366  *
26367  * Number of good IP datagrams with a good ICMP payload
26368  *
26369  * Register Layout
26370  *
26371  * Bits | Access | Reset | Description
26372  * :-------|:-------|:------|:---------------
26373  * [31:0] | R | 0x0 | rxicmp_gd_frms
26374  *
26375  */
26376 /*
26377  * Field : rxicmp_gd_frms - cnt
26378  *
26379  * Number of good IP datagrams with a good ICMP payload
26380  *
26381  * Field Access Macros:
26382  *
26383  */
26384 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
26385 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_LSB 0
26386 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
26387 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_MSB 31
26388 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
26389 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_WIDTH 32
26390 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
26391 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET_MSK 0xffffffff
26392 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
26393 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_CLR_MSK 0x00000000
26394 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
26395 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_RESET 0x0
26396 /* Extracts the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT field value from a register. */
26397 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26398 /* Produces a ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value suitable for setting the register. */
26399 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26400 
26401 #ifndef __ASSEMBLY__
26402 /*
26403  * WARNING: The C register and register group struct declarations are provided for
26404  * convenience and illustrative purposes. They should, however, be used with
26405  * caution as the C language standard provides no guarantees about the alignment or
26406  * atomicity of device memory accesses. The recommended practice for writing
26407  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26408  * alt_write_word() functions.
26409  *
26410  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS.
26411  */
26412 struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s
26413 {
26414  const uint32_t cnt : 32; /* rxicmp_gd_frms */
26415 };
26416 
26417 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS. */
26418 typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s ALT_EMAC_GMAC_RXICMP_GD_FRMS_t;
26419 #endif /* __ASSEMBLY__ */
26420 
26421 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register from the beginning of the component. */
26422 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST 0x240
26423 /* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register. */
26424 #define ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST))
26425 
26426 /*
26427  * Register : Register 145 (rxicmp_err_frms Register) - rxicmp_err_frms
26428  *
26429  * Number of good IP datagrams whose ICMP payload has a checksum error
26430  *
26431  * Register Layout
26432  *
26433  * Bits | Access | Reset | Description
26434  * :-------|:-------|:------|:----------------
26435  * [31:0] | R | 0x0 | rxicmp_err_frms
26436  *
26437  */
26438 /*
26439  * Field : rxicmp_err_frms - cnt
26440  *
26441  * Number of good IP datagrams whose ICMP payload has a checksum error
26442  *
26443  * Field Access Macros:
26444  *
26445  */
26446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
26447 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_LSB 0
26448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
26449 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_MSB 31
26450 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
26451 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_WIDTH 32
26452 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
26453 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET_MSK 0xffffffff
26454 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
26455 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_CLR_MSK 0x00000000
26456 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
26457 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_RESET 0x0
26458 /* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT field value from a register. */
26459 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26460 /* Produces a ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value suitable for setting the register. */
26461 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26462 
26463 #ifndef __ASSEMBLY__
26464 /*
26465  * WARNING: The C register and register group struct declarations are provided for
26466  * convenience and illustrative purposes. They should, however, be used with
26467  * caution as the C language standard provides no guarantees about the alignment or
26468  * atomicity of device memory accesses. The recommended practice for writing
26469  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26470  * alt_write_word() functions.
26471  *
26472  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS.
26473  */
26474 struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s
26475 {
26476  const uint32_t cnt : 32; /* rxicmp_err_frms */
26477 };
26478 
26479 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS. */
26480 typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t;
26481 #endif /* __ASSEMBLY__ */
26482 
26483 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register from the beginning of the component. */
26484 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST 0x244
26485 /* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register. */
26486 #define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST))
26487 
26488 /*
26489  * Register : Register 148 (rxipv4_gd_octets Register) - rxipv4_gd_octets
26490  *
26491  * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
26492  * data
26493  *
26494  * Register Layout
26495  *
26496  * Bits | Access | Reset | Description
26497  * :-------|:-------|:------|:-----------------
26498  * [31:0] | R | 0x0 | rxipv4_gd_octets
26499  *
26500  */
26501 /*
26502  * Field : rxipv4_gd_octets - cnt
26503  *
26504  * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
26505  * data
26506  *
26507  * Field Access Macros:
26508  *
26509  */
26510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
26511 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_LSB 0
26512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
26513 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_MSB 31
26514 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
26515 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_WIDTH 32
26516 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
26517 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET_MSK 0xffffffff
26518 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
26519 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_CLR_MSK 0x00000000
26520 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
26521 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_RESET 0x0
26522 /* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT field value from a register. */
26523 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26524 /* Produces a ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value suitable for setting the register. */
26525 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26526 
26527 #ifndef __ASSEMBLY__
26528 /*
26529  * WARNING: The C register and register group struct declarations are provided for
26530  * convenience and illustrative purposes. They should, however, be used with
26531  * caution as the C language standard provides no guarantees about the alignment or
26532  * atomicity of device memory accesses. The recommended practice for writing
26533  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26534  * alt_write_word() functions.
26535  *
26536  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS.
26537  */
26538 struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s
26539 {
26540  const uint32_t cnt : 32; /* rxipv4_gd_octets */
26541 };
26542 
26543 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS. */
26544 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t;
26545 #endif /* __ASSEMBLY__ */
26546 
26547 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register from the beginning of the component. */
26548 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST 0x250
26549 /* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register. */
26550 #define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST))
26551 
26552 /*
26553  * Register : Register 149 (rxipv4_hdrerr_octets) - rxipv4_hdrerr_octets
26554  *
26555  * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
26556  * version mismatch). The value in the Length field of IPv4 header is used to
26557  * update this counter
26558  *
26559  * Register Layout
26560  *
26561  * Bits | Access | Reset | Description
26562  * :-------|:-------|:------|:------------------------------
26563  * [31:0] | R | 0x0 | rxipv4_hdrerr_octets Register
26564  *
26565  */
26566 /*
26567  * Field : rxipv4_hdrerr_octets Register - cnt
26568  *
26569  * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
26570  * version mismatch). The value in the Length field of IPv4 header is used to
26571  * update this counter
26572  *
26573  * Field Access Macros:
26574  *
26575  */
26576 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
26577 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_LSB 0
26578 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
26579 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_MSB 31
26580 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
26581 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_WIDTH 32
26582 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
26583 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff
26584 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
26585 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000
26586 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
26587 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_RESET 0x0
26588 /* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT field value from a register. */
26589 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26590 /* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
26591 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26592 
26593 #ifndef __ASSEMBLY__
26594 /*
26595  * WARNING: The C register and register group struct declarations are provided for
26596  * convenience and illustrative purposes. They should, however, be used with
26597  * caution as the C language standard provides no guarantees about the alignment or
26598  * atomicity of device memory accesses. The recommended practice for writing
26599  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26600  * alt_write_word() functions.
26601  *
26602  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS.
26603  */
26604 struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s
26605 {
26606  const uint32_t cnt : 32; /* rxipv4_hdrerr_octets Register */
26607 };
26608 
26609 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS. */
26610 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t;
26611 #endif /* __ASSEMBLY__ */
26612 
26613 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register from the beginning of the component. */
26614 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST 0x254
26615 /* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register. */
26616 #define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST))
26617 
26618 /*
26619  * Register : Register 150 (rxipv4_nopay_octets Register) - rxipv4_nopay_octets
26620  *
26621  * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
26622  * payload. The value in the IPv4 headers Length field is used to update this
26623  * counter
26624  *
26625  * Register Layout
26626  *
26627  * Bits | Access | Reset | Description
26628  * :-------|:-------|:------|:--------------------
26629  * [31:0] | R | 0x0 | rxipv4_nopay_octets
26630  *
26631  */
26632 /*
26633  * Field : rxipv4_nopay_octets - cnt
26634  *
26635  * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
26636  * payload. The value in the IPv4 headers Length field is used to update this
26637  * counter
26638  *
26639  * Field Access Macros:
26640  *
26641  */
26642 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
26643 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_LSB 0
26644 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
26645 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_MSB 31
26646 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
26647 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_WIDTH 32
26648 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
26649 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff
26650 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
26651 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000
26652 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
26653 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_RESET 0x0
26654 /* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT field value from a register. */
26655 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26656 /* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
26657 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26658 
26659 #ifndef __ASSEMBLY__
26660 /*
26661  * WARNING: The C register and register group struct declarations are provided for
26662  * convenience and illustrative purposes. They should, however, be used with
26663  * caution as the C language standard provides no guarantees about the alignment or
26664  * atomicity of device memory accesses. The recommended practice for writing
26665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26666  * alt_write_word() functions.
26667  *
26668  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS.
26669  */
26670 struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s
26671 {
26672  const uint32_t cnt : 32; /* rxipv4_nopay_octets */
26673 };
26674 
26675 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS. */
26676 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t;
26677 #endif /* __ASSEMBLY__ */
26678 
26679 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register from the beginning of the component. */
26680 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST 0x258
26681 /* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register. */
26682 #define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST))
26683 
26684 /*
26685  * Register : Register 151 (rxipv4_frag_octets Register) - rxipv4_frag_octets
26686  *
26687  * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
26688  * headers Length field is used to update this counter
26689  *
26690  * Register Layout
26691  *
26692  * Bits | Access | Reset | Description
26693  * :-------|:-------|:------|:-------------------
26694  * [31:0] | R | 0x0 | rxipv4_frag_octets
26695  *
26696  */
26697 /*
26698  * Field : rxipv4_frag_octets - cnt
26699  *
26700  * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
26701  * headers Length field is used to update this counter
26702  *
26703  * Field Access Macros:
26704  *
26705  */
26706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
26707 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_LSB 0
26708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
26709 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_MSB 31
26710 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
26711 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_WIDTH 32
26712 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
26713 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET_MSK 0xffffffff
26714 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
26715 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_CLR_MSK 0x00000000
26716 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
26717 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_RESET 0x0
26718 /* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT field value from a register. */
26719 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26720 /* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value suitable for setting the register. */
26721 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26722 
26723 #ifndef __ASSEMBLY__
26724 /*
26725  * WARNING: The C register and register group struct declarations are provided for
26726  * convenience and illustrative purposes. They should, however, be used with
26727  * caution as the C language standard provides no guarantees about the alignment or
26728  * atomicity of device memory accesses. The recommended practice for writing
26729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26730  * alt_write_word() functions.
26731  *
26732  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS.
26733  */
26734 struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s
26735 {
26736  const uint32_t cnt : 32; /* rxipv4_frag_octets */
26737 };
26738 
26739 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS. */
26740 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t;
26741 #endif /* __ASSEMBLY__ */
26742 
26743 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register from the beginning of the component. */
26744 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST 0x25c
26745 /* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register. */
26746 #define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST))
26747 
26748 /*
26749  * Register : Register 152 (rxipv4_udsbl_octets Register) - rxipv4_udsbl_octets
26750  *
26751  * Number of bytes received in a UDP segment that had the UDP checksum disabled.
26752  * This counter does not count IP Header bytes
26753  *
26754  * Register Layout
26755  *
26756  * Bits | Access | Reset | Description
26757  * :-------|:-------|:------|:--------------------
26758  * [31:0] | R | 0x0 | rxipv4_udsbl_octets
26759  *
26760  */
26761 /*
26762  * Field : rxipv4_udsbl_octets - cnt
26763  *
26764  * Number of bytes received in a UDP segment that had the UDP checksum disabled.
26765  * This counter does not count IP Header bytes
26766  *
26767  * Field Access Macros:
26768  *
26769  */
26770 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
26771 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_LSB 0
26772 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
26773 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_MSB 31
26774 /* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
26775 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_WIDTH 32
26776 /* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
26777 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET_MSK 0xffffffff
26778 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
26779 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_CLR_MSK 0x00000000
26780 /* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
26781 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_RESET 0x0
26782 /* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT field value from a register. */
26783 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26784 /* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value suitable for setting the register. */
26785 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26786 
26787 #ifndef __ASSEMBLY__
26788 /*
26789  * WARNING: The C register and register group struct declarations are provided for
26790  * convenience and illustrative purposes. They should, however, be used with
26791  * caution as the C language standard provides no guarantees about the alignment or
26792  * atomicity of device memory accesses. The recommended practice for writing
26793  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26794  * alt_write_word() functions.
26795  *
26796  * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS.
26797  */
26798 struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s
26799 {
26800  const uint32_t cnt : 32; /* rxipv4_udsbl_octets */
26801 };
26802 
26803 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS. */
26804 typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t;
26805 #endif /* __ASSEMBLY__ */
26806 
26807 /* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register from the beginning of the component. */
26808 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST 0x260
26809 /* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register. */
26810 #define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST))
26811 
26812 /*
26813  * Register : Register 153 (rxipv6_gd_octets Register) - rxipv6_gd_octets
26814  *
26815  * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
26816  * data
26817  *
26818  * Register Layout
26819  *
26820  * Bits | Access | Reset | Description
26821  * :-------|:-------|:------|:-----------------
26822  * [31:0] | R | 0x0 | rxipv6_gd_octets
26823  *
26824  */
26825 /*
26826  * Field : rxipv6_gd_octets - cnt
26827  *
26828  * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
26829  * data
26830  *
26831  * Field Access Macros:
26832  *
26833  */
26834 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
26835 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_LSB 0
26836 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
26837 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_MSB 31
26838 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
26839 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_WIDTH 32
26840 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
26841 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET_MSK 0xffffffff
26842 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
26843 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_CLR_MSK 0x00000000
26844 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
26845 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_RESET 0x0
26846 /* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT field value from a register. */
26847 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26848 /* Produces a ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value suitable for setting the register. */
26849 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26850 
26851 #ifndef __ASSEMBLY__
26852 /*
26853  * WARNING: The C register and register group struct declarations are provided for
26854  * convenience and illustrative purposes. They should, however, be used with
26855  * caution as the C language standard provides no guarantees about the alignment or
26856  * atomicity of device memory accesses. The recommended practice for writing
26857  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26858  * alt_write_word() functions.
26859  *
26860  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS.
26861  */
26862 struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s
26863 {
26864  const uint32_t cnt : 32; /* rxipv6_gd_octets */
26865 };
26866 
26867 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS. */
26868 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t;
26869 #endif /* __ASSEMBLY__ */
26870 
26871 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register from the beginning of the component. */
26872 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST 0x264
26873 /* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register. */
26874 #define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST))
26875 
26876 /*
26877  * Register : Register 154 (rxipv6_hdrerr_octets Register) - rxipv6_hdrerr_octets
26878  *
26879  * Number of bytes received in IPv6 datagrams with header errors (length, version
26880  * mismatch). The value in the IPv6 headers Length field is used to update this
26881  * counter
26882  *
26883  * Register Layout
26884  *
26885  * Bits | Access | Reset | Description
26886  * :-------|:-------|:------|:---------------------
26887  * [31:0] | R | 0x0 | rxipv6_hdrerr_octets
26888  *
26889  */
26890 /*
26891  * Field : rxipv6_hdrerr_octets - cnt
26892  *
26893  * Number of bytes received in IPv6 datagrams with header errors (length, version
26894  * mismatch). The value in the IPv6 headers Length field is used to update this
26895  * counter
26896  *
26897  * Field Access Macros:
26898  *
26899  */
26900 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
26901 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_LSB 0
26902 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
26903 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_MSB 31
26904 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
26905 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_WIDTH 32
26906 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
26907 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET_MSK 0xffffffff
26908 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
26909 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_CLR_MSK 0x00000000
26910 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
26911 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_RESET 0x0
26912 /* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT field value from a register. */
26913 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26914 /* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
26915 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26916 
26917 #ifndef __ASSEMBLY__
26918 /*
26919  * WARNING: The C register and register group struct declarations are provided for
26920  * convenience and illustrative purposes. They should, however, be used with
26921  * caution as the C language standard provides no guarantees about the alignment or
26922  * atomicity of device memory accesses. The recommended practice for writing
26923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26924  * alt_write_word() functions.
26925  *
26926  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS.
26927  */
26928 struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s
26929 {
26930  const uint32_t cnt : 32; /* rxipv6_hdrerr_octets */
26931 };
26932 
26933 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS. */
26934 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t;
26935 #endif /* __ASSEMBLY__ */
26936 
26937 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register from the beginning of the component. */
26938 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST 0x268
26939 /* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register. */
26940 #define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST))
26941 
26942 /*
26943  * Register : Register 155 (rxipv6_nopay_octets Register) - rxipv6_nopay_octets
26944  *
26945  * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
26946  * payload. The value in the IPv6 headers Length field is used to update this
26947  * counter
26948  *
26949  * Register Layout
26950  *
26951  * Bits | Access | Reset | Description
26952  * :-------|:-------|:------|:--------------------
26953  * [31:0] | R | 0x0 | rxipv6_nopay_octets
26954  *
26955  */
26956 /*
26957  * Field : rxipv6_nopay_octets - cnt
26958  *
26959  * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
26960  * payload. The value in the IPv6 headers Length field is used to update this
26961  * counter
26962  *
26963  * Field Access Macros:
26964  *
26965  */
26966 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
26967 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_LSB 0
26968 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
26969 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_MSB 31
26970 /* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
26971 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_WIDTH 32
26972 /* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
26973 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET_MSK 0xffffffff
26974 /* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
26975 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_CLR_MSK 0x00000000
26976 /* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
26977 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_RESET 0x0
26978 /* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT field value from a register. */
26979 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
26980 /* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
26981 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
26982 
26983 #ifndef __ASSEMBLY__
26984 /*
26985  * WARNING: The C register and register group struct declarations are provided for
26986  * convenience and illustrative purposes. They should, however, be used with
26987  * caution as the C language standard provides no guarantees about the alignment or
26988  * atomicity of device memory accesses. The recommended practice for writing
26989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
26990  * alt_write_word() functions.
26991  *
26992  * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS.
26993  */
26994 struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s
26995 {
26996  const uint32_t cnt : 32; /* rxipv6_nopay_octets */
26997 };
26998 
26999 /* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS. */
27000 typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t;
27001 #endif /* __ASSEMBLY__ */
27002 
27003 /* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register from the beginning of the component. */
27004 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST 0x26c
27005 /* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register. */
27006 #define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST))
27007 
27008 /*
27009  * Register : Register 156 (rxudp_gd_octets Register) - rxudp_gd_octets
27010  *
27011  * Number of bytes received in a good UDP segment. This counter does not count IP
27012  * header bytes
27013  *
27014  * Register Layout
27015  *
27016  * Bits | Access | Reset | Description
27017  * :-------|:-------|:------|:----------------
27018  * [31:0] | R | 0x0 | rxudp_gd_octets
27019  *
27020  */
27021 /*
27022  * Field : rxudp_gd_octets - cnt
27023  *
27024  * Number of bytes received in a good UDP segment. This counter does not count IP
27025  * header bytes
27026  *
27027  * Field Access Macros:
27028  *
27029  */
27030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
27031 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_LSB 0
27032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
27033 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_MSB 31
27034 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
27035 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_WIDTH 32
27036 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
27037 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET_MSK 0xffffffff
27038 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
27039 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_CLR_MSK 0x00000000
27040 /* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
27041 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_RESET 0x0
27042 /* Extracts the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT field value from a register. */
27043 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27044 /* Produces a ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value suitable for setting the register. */
27045 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27046 
27047 #ifndef __ASSEMBLY__
27048 /*
27049  * WARNING: The C register and register group struct declarations are provided for
27050  * convenience and illustrative purposes. They should, however, be used with
27051  * caution as the C language standard provides no guarantees about the alignment or
27052  * atomicity of device memory accesses. The recommended practice for writing
27053  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27054  * alt_write_word() functions.
27055  *
27056  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS.
27057  */
27058 struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s
27059 {
27060  const uint32_t cnt : 32; /* rxudp_gd_octets */
27061 };
27062 
27063 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS. */
27064 typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t;
27065 #endif /* __ASSEMBLY__ */
27066 
27067 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register from the beginning of the component. */
27068 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST 0x270
27069 /* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register. */
27070 #define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST))
27071 
27072 /*
27073  * Register : Register 157 (rxudp_err_octets Register) - rxudp_err_octets
27074  *
27075  * Number of bytes received in a UDP segment that had checksum errors
27076  *
27077  * Register Layout
27078  *
27079  * Bits | Access | Reset | Description
27080  * :-------|:-------|:------|:-----------------
27081  * [31:0] | R | 0x0 | rxudp_err_octets
27082  *
27083  */
27084 /*
27085  * Field : rxudp_err_octets - cnt
27086  *
27087  * Number of bytes received in a UDP segment that had checksum errors
27088  *
27089  * Field Access Macros:
27090  *
27091  */
27092 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
27093 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_LSB 0
27094 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
27095 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_MSB 31
27096 /* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
27097 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_WIDTH 32
27098 /* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
27099 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET_MSK 0xffffffff
27100 /* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
27101 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_CLR_MSK 0x00000000
27102 /* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
27103 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_RESET 0x0
27104 /* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT field value from a register. */
27105 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27106 /* Produces a ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value suitable for setting the register. */
27107 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27108 
27109 #ifndef __ASSEMBLY__
27110 /*
27111  * WARNING: The C register and register group struct declarations are provided for
27112  * convenience and illustrative purposes. They should, however, be used with
27113  * caution as the C language standard provides no guarantees about the alignment or
27114  * atomicity of device memory accesses. The recommended practice for writing
27115  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27116  * alt_write_word() functions.
27117  *
27118  * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS.
27119  */
27120 struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s
27121 {
27122  const uint32_t cnt : 32; /* rxudp_err_octets */
27123 };
27124 
27125 /* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS. */
27126 typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t;
27127 #endif /* __ASSEMBLY__ */
27128 
27129 /* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register from the beginning of the component. */
27130 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST 0x274
27131 /* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register. */
27132 #define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST))
27133 
27134 /*
27135  * Register : Register 158 (rxtcp_gd_octets Register) - rxtcp_gd_octets
27136  *
27137  * Number of bytes received in a good TCP segment
27138  *
27139  * Register Layout
27140  *
27141  * Bits | Access | Reset | Description
27142  * :-------|:-------|:------|:----------------
27143  * [31:0] | R | 0x0 | rxtcp_gd_octets
27144  *
27145  */
27146 /*
27147  * Field : rxtcp_gd_octets - cnt
27148  *
27149  * Number of bytes received in a good TCP segment
27150  *
27151  * Field Access Macros:
27152  *
27153  */
27154 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
27155 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_LSB 0
27156 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
27157 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_MSB 31
27158 /* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
27159 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_WIDTH 32
27160 /* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
27161 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET_MSK 0xffffffff
27162 /* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
27163 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_CLR_MSK 0x00000000
27164 /* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
27165 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_RESET 0x0
27166 /* Extracts the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT field value from a register. */
27167 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27168 /* Produces a ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value suitable for setting the register. */
27169 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27170 
27171 #ifndef __ASSEMBLY__
27172 /*
27173  * WARNING: The C register and register group struct declarations are provided for
27174  * convenience and illustrative purposes. They should, however, be used with
27175  * caution as the C language standard provides no guarantees about the alignment or
27176  * atomicity of device memory accesses. The recommended practice for writing
27177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27178  * alt_write_word() functions.
27179  *
27180  * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS.
27181  */
27182 struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s
27183 {
27184  const uint32_t cnt : 32; /* rxtcp_gd_octets */
27185 };
27186 
27187 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS. */
27188 typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t;
27189 #endif /* __ASSEMBLY__ */
27190 
27191 /* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register from the beginning of the component. */
27192 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST 0x278
27193 /* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register. */
27194 #define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST))
27195 
27196 /*
27197  * Register : Register 159 (rxtcp_err_octets Register) - rxtcperroctets
27198  *
27199  * Number of bytes received in a TCP segment with checksum errors
27200  *
27201  * Register Layout
27202  *
27203  * Bits | Access | Reset | Description
27204  * :-------|:-------|:------|:-----------------
27205  * [31:0] | R | 0x0 | rxtcp_err_octets
27206  *
27207  */
27208 /*
27209  * Field : rxtcp_err_octets - rxtcp_err_octets
27210  *
27211  * Number of bytes received in a TCP segment with checksum errors
27212  *
27213  * Field Access Macros:
27214  *
27215  */
27216 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
27217 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_LSB 0
27218 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
27219 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_MSB 31
27220 /* The width in bits of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
27221 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_WIDTH 32
27222 /* The mask used to set the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
27223 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET_MSK 0xffffffff
27224 /* The mask used to clear the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
27225 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_CLR_MSK 0x00000000
27226 /* The reset value of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
27227 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_RESET 0x0
27228 /* Extracts the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS field value from a register. */
27229 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_GET(value) (((value) & 0xffffffff) >> 0)
27230 /* Produces a ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value suitable for setting the register. */
27231 #define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET(value) (((value) << 0) & 0xffffffff)
27232 
27233 #ifndef __ASSEMBLY__
27234 /*
27235  * WARNING: The C register and register group struct declarations are provided for
27236  * convenience and illustrative purposes. They should, however, be used with
27237  * caution as the C language standard provides no guarantees about the alignment or
27238  * atomicity of device memory accesses. The recommended practice for writing
27239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27240  * alt_write_word() functions.
27241  *
27242  * The struct declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS.
27243  */
27244 struct ALT_EMAC_GMAC_RXTCPERROCTETS_s
27245 {
27246  const uint32_t rxtcp_err_octets : 32; /* rxtcp_err_octets */
27247 };
27248 
27249 /* The typedef declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS. */
27250 typedef volatile struct ALT_EMAC_GMAC_RXTCPERROCTETS_s ALT_EMAC_GMAC_RXTCPERROCTETS_t;
27251 #endif /* __ASSEMBLY__ */
27252 
27253 /* The byte offset of the ALT_EMAC_GMAC_RXTCPERROCTETS register from the beginning of the component. */
27254 #define ALT_EMAC_GMAC_RXTCPERROCTETS_OFST 0x27c
27255 /* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register. */
27256 #define ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCPERROCTETS_OFST))
27257 
27258 /*
27259  * Register : Register 160 (rxicmp_gd_octets Register) - rxicmp_gd_octets
27260  *
27261  * Number of bytes received in a good ICMP segment
27262  *
27263  * Register Layout
27264  *
27265  * Bits | Access | Reset | Description
27266  * :-------|:-------|:------|:-----------------
27267  * [31:0] | R | 0x0 | rxicmp_gd_octets
27268  *
27269  */
27270 /*
27271  * Field : rxicmp_gd_octets - cnt
27272  *
27273  * Number of bytes received in a good ICMP segment
27274  *
27275  * Field Access Macros:
27276  *
27277  */
27278 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
27279 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_LSB 0
27280 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
27281 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_MSB 31
27282 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
27283 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_WIDTH 32
27284 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
27285 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET_MSK 0xffffffff
27286 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
27287 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_CLR_MSK 0x00000000
27288 /* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
27289 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_RESET 0x0
27290 /* Extracts the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT field value from a register. */
27291 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27292 /* Produces a ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value suitable for setting the register. */
27293 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27294 
27295 #ifndef __ASSEMBLY__
27296 /*
27297  * WARNING: The C register and register group struct declarations are provided for
27298  * convenience and illustrative purposes. They should, however, be used with
27299  * caution as the C language standard provides no guarantees about the alignment or
27300  * atomicity of device memory accesses. The recommended practice for writing
27301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27302  * alt_write_word() functions.
27303  *
27304  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS.
27305  */
27306 struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s
27307 {
27308  const uint32_t cnt : 32; /* rxicmp_gd_octets */
27309 };
27310 
27311 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS. */
27312 typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t;
27313 #endif /* __ASSEMBLY__ */
27314 
27315 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register from the beginning of the component. */
27316 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST 0x280
27317 /* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register. */
27318 #define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST))
27319 
27320 /*
27321  * Register : Register 161 (rxicmp_err_octets Register) - rxicmp_err_octets
27322  *
27323  * Number of bytes received in an ICMP segment with checksum errors
27324  *
27325  * Register Layout
27326  *
27327  * Bits | Access | Reset | Description
27328  * :-------|:-------|:------|:------------------
27329  * [31:0] | R | 0x0 | rxicmp_err_octets
27330  *
27331  */
27332 /*
27333  * Field : rxicmp_err_octets - cnt
27334  *
27335  * Number of bytes received in an ICMP segment with checksum errors
27336  *
27337  * Field Access Macros:
27338  *
27339  */
27340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
27341 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_LSB 0
27342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
27343 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_MSB 31
27344 /* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
27345 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_WIDTH 32
27346 /* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
27347 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET_MSK 0xffffffff
27348 /* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
27349 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_CLR_MSK 0x00000000
27350 /* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
27351 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_RESET 0x0
27352 /* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT field value from a register. */
27353 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
27354 /* Produces a ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value suitable for setting the register. */
27355 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)
27356 
27357 #ifndef __ASSEMBLY__
27358 /*
27359  * WARNING: The C register and register group struct declarations are provided for
27360  * convenience and illustrative purposes. They should, however, be used with
27361  * caution as the C language standard provides no guarantees about the alignment or
27362  * atomicity of device memory accesses. The recommended practice for writing
27363  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27364  * alt_write_word() functions.
27365  *
27366  * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS.
27367  */
27368 struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s
27369 {
27370  const uint32_t cnt : 32; /* rxicmp_err_octets */
27371 };
27372 
27373 /* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS. */
27374 typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t;
27375 #endif /* __ASSEMBLY__ */
27376 
27377 /* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register from the beginning of the component. */
27378 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST 0x284
27379 /* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register. */
27380 #define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST))
27381 
27382 /*
27383  * Register : Register 256 (Layer 3 and Layer 4 Control Register 0) - L3_L4_Control0
27384  *
27385  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
27386  *
27387  * Register Layout
27388  *
27389  * Bits | Access | Reset | Description
27390  * :--------|:-------|:------|:----------------------------------------------
27391  * [0] | RW | 0x0 | Layer 3 Protocol Enable
27392  * [1] | ??? | 0x0 | *UNDEFINED*
27393  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
27394  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
27395  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
27396  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
27397  * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match
27398  * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match
27399  * [16] | RW | 0x0 | Layer 4 Protocol Enable
27400  * [17] | ??? | 0x0 | *UNDEFINED*
27401  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
27402  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
27403  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
27404  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
27405  * [31:22] | ??? | 0x0 | *UNDEFINED*
27406  *
27407  */
27408 /*
27409  * Field : Layer 3 Protocol Enable - l3pen0
27410  *
27411  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
27412  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
27413  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
27414  * frames.
27415  *
27416  * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high.
27417  *
27418  * Field Access Macros:
27419  *
27420  */
27421 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
27422 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB 0
27423 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
27424 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB 0
27425 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
27426 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH 1
27427 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
27428 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK 0x00000001
27429 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
27430 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK 0xfffffffe
27431 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
27432 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET 0x0
27433 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 field value from a register. */
27434 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET(value) (((value) & 0x00000001) >> 0)
27435 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value suitable for setting the register. */
27436 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET(value) (((value) << 0) & 0x00000001)
27437 
27438 /*
27439  * Field : Layer 3 IP SA Match Enable - l3sam0
27440  *
27441  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
27442  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
27443  * for matching.
27444  *
27445  * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4
27446  * (L3DAM0) because either IPv6 SA or DA can be checked for filtering.
27447  *
27448  * Field Access Macros:
27449  *
27450  */
27451 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
27452 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB 2
27453 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
27454 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB 2
27455 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
27456 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH 1
27457 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
27458 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK 0x00000004
27459 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
27460 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK 0xfffffffb
27461 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
27462 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET 0x0
27463 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 field value from a register. */
27464 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET(value) (((value) & 0x00000004) >> 2)
27465 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value suitable for setting the register. */
27466 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET(value) (((value) << 2) & 0x00000004)
27467 
27468 /*
27469  * Field : Layer 3 IP SA Inverse Match Enable - l3saim0
27470  *
27471  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
27472  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
27473  * Address field is enabled for perfect matching.
27474  *
27475  * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high.
27476  *
27477  * Field Access Macros:
27478  *
27479  */
27480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
27481 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB 3
27482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
27483 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB 3
27484 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
27485 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH 1
27486 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
27487 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK 0x00000008
27488 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
27489 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK 0xfffffff7
27490 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
27491 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET 0x0
27492 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 field value from a register. */
27493 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET(value) (((value) & 0x00000008) >> 3)
27494 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value suitable for setting the register. */
27495 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET(value) (((value) << 3) & 0x00000008)
27496 
27497 /*
27498  * Field : Layer 3 IP DA Match Enable - l3dam0
27499  *
27500  * When set, this bit indicates that Layer 3 IP Destination Address field is
27501  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
27502  * Address field for matching.
27503  *
27504  * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2
27505  * (L3SAM0) because either IPv6 DA or SA can be checked for filtering.
27506  *
27507  * Field Access Macros:
27508  *
27509  */
27510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
27511 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB 4
27512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
27513 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB 4
27514 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
27515 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH 1
27516 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
27517 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK 0x00000010
27518 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
27519 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK 0xffffffef
27520 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
27521 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET 0x0
27522 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 field value from a register. */
27523 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET(value) (((value) & 0x00000010) >> 4)
27524 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value suitable for setting the register. */
27525 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET(value) (((value) << 4) & 0x00000010)
27526 
27527 /*
27528  * Field : Layer 3 IP DA Inverse Match Enable - l3daim0
27529  *
27530  * When set, this bit indicates that the Layer 3 IP Destination Address field is
27531  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
27532  * Destination Address field is enabled for perfect matching.
27533  *
27534  * This bit is valid and applicable only when Bit 4 (L3DAM0) is set high.
27535  *
27536  * Field Access Macros:
27537  *
27538  */
27539 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
27540 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB 5
27541 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
27542 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB 5
27543 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
27544 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH 1
27545 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
27546 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK 0x00000020
27547 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
27548 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK 0xffffffdf
27549 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
27550 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET 0x0
27551 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 field value from a register. */
27552 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET(value) (((value) & 0x00000020) >> 5)
27553 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value suitable for setting the register. */
27554 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET(value) (((value) << 5) & 0x00000020)
27555 
27556 /*
27557  * Field : Layer 3 IP SA Higher Bits Match - l3hsbm0
27558  *
27559  * IPv4 Frames:
27560  *
27561  * This field contains the number of lower bits of IP Source Address that are
27562  * masked for matching in the IPv4 frames. The following list describes the values
27563  * of this field:
27564  *
27565  * * 0: No bits are masked.
27566  *
27567  * * 1: LSb[0] is masked.
27568  *
27569  * * 2: Two LSbs [1:0] are masked.
27570  *
27571  * * ...
27572  *
27573  * * 31: All bits except MSb are masked.
27574  *
27575  * IPv6 Frames:
27576  *
27577  * This field contains Bits [4:0] of the field that indicates the number of higher
27578  * bits of IP Source or Destination Address matched in the IPv6 frames.
27579  *
27580  * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
27581  *
27582  * Field Access Macros:
27583  *
27584  */
27585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
27586 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB 6
27587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
27588 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB 10
27589 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
27590 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH 5
27591 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
27592 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK 0x000007c0
27593 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
27594 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK 0xfffff83f
27595 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
27596 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET 0x0
27597 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 field value from a register. */
27598 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET(value) (((value) & 0x000007c0) >> 6)
27599 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value suitable for setting the register. */
27600 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET(value) (((value) << 6) & 0x000007c0)
27601 
27602 /*
27603  * Field : Layer 3 IP DA Higher Bits Match - l3hdbm0
27604  *
27605  * IPv4 Frames:
27606  *
27607  * This field contains the number of higher bits of IP Destination Address that are
27608  * matched in the IPv4 frames. The following list describes the values of this
27609  * field:
27610  *
27611  * * 0: No bits are masked.
27612  *
27613  * * 1: LSb[0] is masked.
27614  *
27615  * * 2: Two LSbs [1:0] are masked.
27616  *
27617  * * ...
27618  *
27619  * * 31: All bits except MSb are masked.
27620  *
27621  * IPv6 Frames:
27622  *
27623  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate
27624  * the number of lower bits of IP Source or Destination Address that are masked in
27625  * the IPv6 frames. The following list describes the concatenated values of the
27626  * L3HDBM0[1:0] and L3HSBM0 bits:
27627  *
27628  * * 0: No bits are masked.
27629  *
27630  * * 1: LSb[0] is masked.
27631  *
27632  * * 2: Two LSbs [1:0] are masked.
27633  *
27634  * * ...
27635  *
27636  * * 127: All bits except MSb are masked.
27637  *
27638  * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
27639  *
27640  * Field Access Macros:
27641  *
27642  */
27643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
27644 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB 11
27645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
27646 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB 15
27647 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
27648 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH 5
27649 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
27650 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK 0x0000f800
27651 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
27652 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK 0xffff07ff
27653 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
27654 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET 0x0
27655 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 field value from a register. */
27656 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET(value) (((value) & 0x0000f800) >> 11)
27657 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value suitable for setting the register. */
27658 #define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET(value) (((value) << 11) & 0x0000f800)
27659 
27660 /*
27661  * Field : Layer 4 Protocol Enable - l4pen0
27662  *
27663  * When set, this bit indicates that the Source and Destination Port number fields
27664  * for UDP frames are used for matching. When reset, this bit indicates that the
27665  * Source and Destination Port number fields for TCP frames are used for matching.
27666  *
27667  * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high.
27668  *
27669  * Field Access Macros:
27670  *
27671  */
27672 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
27673 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB 16
27674 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
27675 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB 16
27676 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
27677 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH 1
27678 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
27679 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK 0x00010000
27680 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
27681 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK 0xfffeffff
27682 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
27683 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET 0x0
27684 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 field value from a register. */
27685 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET(value) (((value) & 0x00010000) >> 16)
27686 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value suitable for setting the register. */
27687 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET(value) (((value) << 16) & 0x00010000)
27688 
27689 /*
27690  * Field : Layer 4 Source Port Match Enable - l4spm0
27691  *
27692  * When set, this bit indicates that the Layer 4 Source Port number field is
27693  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
27694  * field for matching.
27695  *
27696  * Field Access Macros:
27697  *
27698  */
27699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
27700 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB 18
27701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
27702 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB 18
27703 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
27704 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH 1
27705 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
27706 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK 0x00040000
27707 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
27708 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK 0xfffbffff
27709 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
27710 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET 0x0
27711 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 field value from a register. */
27712 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET(value) (((value) & 0x00040000) >> 18)
27713 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value suitable for setting the register. */
27714 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET(value) (((value) << 18) & 0x00040000)
27715 
27716 /*
27717  * Field : Layer 4 Source Port Inverse Match Enable - l4spim0
27718  *
27719  * When set, this bit indicates that the Layer 4 Source Port number field is
27720  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
27721  * Source Port number field is enabled for perfect matching.
27722  *
27723  * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high.
27724  *
27725  * Field Access Macros:
27726  *
27727  */
27728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
27729 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB 19
27730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
27731 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB 19
27732 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
27733 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH 1
27734 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
27735 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK 0x00080000
27736 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
27737 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK 0xfff7ffff
27738 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
27739 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET 0x0
27740 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 field value from a register. */
27741 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET(value) (((value) & 0x00080000) >> 19)
27742 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value suitable for setting the register. */
27743 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET(value) (((value) << 19) & 0x00080000)
27744 
27745 /*
27746  * Field : Layer 4 Destination Port Match Enable - l4dpm0
27747  *
27748  * When set, this bit indicates that the Layer 4 Destination Port number field is
27749  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
27750  * number field for matching.
27751  *
27752  * Field Access Macros:
27753  *
27754  */
27755 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
27756 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB 20
27757 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
27758 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB 20
27759 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
27760 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH 1
27761 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
27762 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK 0x00100000
27763 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
27764 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK 0xffefffff
27765 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
27766 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET 0x0
27767 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 field value from a register. */
27768 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET(value) (((value) & 0x00100000) >> 20)
27769 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value suitable for setting the register. */
27770 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET(value) (((value) << 20) & 0x00100000)
27771 
27772 /*
27773  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim0
27774  *
27775  * When set, this bit indicates that the Layer 4 Destination Port number field is
27776  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
27777  * Destination Port number field is enabled for perfect matching.
27778  *
27779  * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
27780  *
27781  * Field Access Macros:
27782  *
27783  */
27784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
27785 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB 21
27786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
27787 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB 21
27788 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
27789 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH 1
27790 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
27791 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK 0x00200000
27792 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
27793 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK 0xffdfffff
27794 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
27795 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET 0x0
27796 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 field value from a register. */
27797 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET(value) (((value) & 0x00200000) >> 21)
27798 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value suitable for setting the register. */
27799 #define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET(value) (((value) << 21) & 0x00200000)
27800 
27801 #ifndef __ASSEMBLY__
27802 /*
27803  * WARNING: The C register and register group struct declarations are provided for
27804  * convenience and illustrative purposes. They should, however, be used with
27805  * caution as the C language standard provides no guarantees about the alignment or
27806  * atomicity of device memory accesses. The recommended practice for writing
27807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27808  * alt_write_word() functions.
27809  *
27810  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL0.
27811  */
27812 struct ALT_EMAC_GMAC_L3_L4_CTL0_s
27813 {
27814  uint32_t l3pen0 : 1; /* Layer 3 Protocol Enable */
27815  uint32_t : 1; /* *UNDEFINED* */
27816  uint32_t l3sam0 : 1; /* Layer 3 IP SA Match Enable */
27817  uint32_t l3saim0 : 1; /* Layer 3 IP SA Inverse Match Enable */
27818  uint32_t l3dam0 : 1; /* Layer 3 IP DA Match Enable */
27819  uint32_t l3daim0 : 1; /* Layer 3 IP DA Inverse Match Enable */
27820  uint32_t l3hsbm0 : 5; /* Layer 3 IP SA Higher Bits Match */
27821  uint32_t l3hdbm0 : 5; /* Layer 3 IP DA Higher Bits Match */
27822  uint32_t l4pen0 : 1; /* Layer 4 Protocol Enable */
27823  uint32_t : 1; /* *UNDEFINED* */
27824  uint32_t l4spm0 : 1; /* Layer 4 Source Port Match Enable */
27825  uint32_t l4spim0 : 1; /* Layer 4 Source Port Inverse Match Enable */
27826  uint32_t l4dpm0 : 1; /* Layer 4 Destination Port Match Enable */
27827  uint32_t l4dpim0 : 1; /* Layer 4 Destination Port Inverse Match Enable */
27828  uint32_t : 10; /* *UNDEFINED* */
27829 };
27830 
27831 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL0. */
27832 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL0_s ALT_EMAC_GMAC_L3_L4_CTL0_t;
27833 #endif /* __ASSEMBLY__ */
27834 
27835 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL0 register from the beginning of the component. */
27836 #define ALT_EMAC_GMAC_L3_L4_CTL0_OFST 0x400
27837 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register. */
27838 #define ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST))
27839 
27840 /*
27841  * Register : Register 257 (Layer 4 Address Register 0) - Layer4_Address0
27842  *
27843  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
27844  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
27845  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
27846  * Layer 4 Address Registers are written. For proper synchronization updates, you
27847  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
27848  * Registers after at least four clock cycles delay of the destination clock.
27849  *
27850  * Register Layout
27851  *
27852  * Bits | Access | Reset | Description
27853  * :--------|:-------|:------|:--------------------------------------
27854  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
27855  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
27856  *
27857  */
27858 /*
27859  * Field : Layer 4 Source Port Number Field - l4sp0
27860  *
27861  * Layer 4 Source Port Number Field
27862  *
27863  * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
27864  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
27865  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
27866  *
27867  * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
27868  * Layer 4 Control Register 0), this field contains the value to be matched with
27869  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
27870  *
27871  * Field Access Macros:
27872  *
27873  */
27874 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
27875 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB 0
27876 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
27877 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB 15
27878 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
27879 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH 16
27880 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
27881 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK 0x0000ffff
27882 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
27883 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK 0xffff0000
27884 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
27885 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET 0x0
27886 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 field value from a register. */
27887 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET(value) (((value) & 0x0000ffff) >> 0)
27888 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value suitable for setting the register. */
27889 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET(value) (((value) << 0) & 0x0000ffff)
27890 
27891 /*
27892  * Field : Layer 4 Destination Port Number Field - l4dp0
27893  *
27894  * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
27895  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
27896  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
27897  *
27898  * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
27899  * Layer 4 Control Register 0), this field contains the value to be matched with
27900  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
27901  *
27902  * Field Access Macros:
27903  *
27904  */
27905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
27906 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB 16
27907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
27908 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB 31
27909 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
27910 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH 16
27911 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
27912 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK 0xffff0000
27913 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
27914 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK 0x0000ffff
27915 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
27916 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET 0x0
27917 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 field value from a register. */
27918 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET(value) (((value) & 0xffff0000) >> 16)
27919 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value suitable for setting the register. */
27920 #define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET(value) (((value) << 16) & 0xffff0000)
27921 
27922 #ifndef __ASSEMBLY__
27923 /*
27924  * WARNING: The C register and register group struct declarations are provided for
27925  * convenience and illustrative purposes. They should, however, be used with
27926  * caution as the C language standard provides no guarantees about the alignment or
27927  * atomicity of device memory accesses. The recommended practice for writing
27928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
27929  * alt_write_word() functions.
27930  *
27931  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR0.
27932  */
27933 struct ALT_EMAC_GMAC_LYR4_ADDR0_s
27934 {
27935  uint32_t l4sp0 : 16; /* Layer 4 Source Port Number Field */
27936  uint32_t l4dp0 : 16; /* Layer 4 Destination Port Number Field */
27937 };
27938 
27939 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR0. */
27940 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR0_s ALT_EMAC_GMAC_LYR4_ADDR0_t;
27941 #endif /* __ASSEMBLY__ */
27942 
27943 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR0 register from the beginning of the component. */
27944 #define ALT_EMAC_GMAC_LYR4_ADDR0_OFST 0x404
27945 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register. */
27946 #define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST))
27947 
27948 /*
27949  * Register : Register 260 (Layer 3 Address 0 Register 0) - Layer3_Addr0_Reg0
27950  *
27951  * For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source
27952  * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
27953  * Address or Destination Address field.
27954  *
27955  * Register Layout
27956  *
27957  * Bits | Access | Reset | Description
27958  * :-------|:-------|:------|:------------------------
27959  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
27960  *
27961  */
27962 /*
27963  * Field : Layer 3 Address 0 Field - l3a00
27964  *
27965  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
27966  * Layer 4 Control Register 0), this field contains the value to be matched with
27967  * Bits[31:0] of the IP Source Address field in the IPv6 frames.
27968  *
27969  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
27970  * Layer 4 Control Register 0), this field contains the value to be matched with
27971  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
27972  *
27973  * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3
27974  * and Layer 4 Control Register 0), this field contains the value to be matched
27975  * with the IP Source Address field in the IPv4 frames.
27976  *
27977  * Field Access Macros:
27978  *
27979  */
27980 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
27981 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB 0
27982 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
27983 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB 31
27984 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
27985 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH 32
27986 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
27987 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK 0xffffffff
27988 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
27989 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK 0x00000000
27990 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
27991 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET 0x0
27992 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 field value from a register. */
27993 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET(value) (((value) & 0xffffffff) >> 0)
27994 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value suitable for setting the register. */
27995 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET(value) (((value) << 0) & 0xffffffff)
27996 
27997 #ifndef __ASSEMBLY__
27998 /*
27999  * WARNING: The C register and register group struct declarations are provided for
28000  * convenience and illustrative purposes. They should, however, be used with
28001  * caution as the C language standard provides no guarantees about the alignment or
28002  * atomicity of device memory accesses. The recommended practice for writing
28003  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28004  * alt_write_word() functions.
28005  *
28006  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0.
28007  */
28008 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s
28009 {
28010  uint32_t l3a00 : 32; /* Layer 3 Address 0 Field */
28011 };
28012 
28013 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0. */
28014 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t;
28015 #endif /* __ASSEMBLY__ */
28016 
28017 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register from the beginning of the component. */
28018 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST 0x410
28019 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register. */
28020 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST))
28021 
28022 /*
28023  * Register : Register 261 (Layer 3 Address 1 Register 0) - Layer3_Addr1_Reg0
28024  *
28025  * For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP
28026  * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
28027  * 128-bit IP Source Address or Destination Address field.
28028  *
28029  * Register Layout
28030  *
28031  * Bits | Access | Reset | Description
28032  * :-------|:-------|:------|:------------------------
28033  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
28034  *
28035  */
28036 /*
28037  * Field : Layer 3 Address 1 Field - l3a10
28038  *
28039  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
28040  * Layer 4 Control Register 0), this field contains the value to be matched with
28041  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
28042  *
28043  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
28044  * Layer 4 Control Register 0), this field contains the value to be matched with
28045  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
28046  *
28047  * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3
28048  * and Layer 4 Control Register 0), this field contains the value to be matched
28049  * with the IP Destination Address field in the IPv4 frames.
28050  *
28051  * Field Access Macros:
28052  *
28053  */
28054 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
28055 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_LSB 0
28056 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
28057 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_MSB 31
28058 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
28059 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_WIDTH 32
28060 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
28061 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET_MSK 0xffffffff
28062 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
28063 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_CLR_MSK 0x00000000
28064 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
28065 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_RESET 0x0
28066 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 field value from a register. */
28067 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_GET(value) (((value) & 0xffffffff) >> 0)
28068 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value suitable for setting the register. */
28069 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET(value) (((value) << 0) & 0xffffffff)
28070 
28071 #ifndef __ASSEMBLY__
28072 /*
28073  * WARNING: The C register and register group struct declarations are provided for
28074  * convenience and illustrative purposes. They should, however, be used with
28075  * caution as the C language standard provides no guarantees about the alignment or
28076  * atomicity of device memory accesses. The recommended practice for writing
28077  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28078  * alt_write_word() functions.
28079  *
28080  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0.
28081  */
28082 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s
28083 {
28084  uint32_t l3a10 : 32; /* Layer 3 Address 1 Field */
28085 };
28086 
28087 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0. */
28088 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t;
28089 #endif /* __ASSEMBLY__ */
28090 
28091 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register from the beginning of the component. */
28092 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST 0x414
28093 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register. */
28094 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST))
28095 
28096 /*
28097  * Register : Register 262 (Layer 3 Address 2 Register 0) - Layer3_Addr2_Reg0
28098  *
28099  * For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames,
28100  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
28101  * field.
28102  *
28103  * Register Layout
28104  *
28105  * Bits | Access | Reset | Description
28106  * :-------|:-------|:------|:------------------------
28107  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
28108  *
28109  */
28110 /*
28111  * Field : Layer 3 Address 2 Field - l3a20
28112  *
28113  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
28114  * Layer 4 Control Register 0), this field contains the value to be matched with
28115  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
28116  *
28117  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
28118  * Layer 4 Control Register 0), this field contains value to be matched with Bits
28119  * [95:64] of the IP Destination Address field in the IPv6 frames.
28120  *
28121  * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
28122  * Register 0), this register is not used.
28123  *
28124  * Field Access Macros:
28125  *
28126  */
28127 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
28128 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_LSB 0
28129 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
28130 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_MSB 31
28131 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
28132 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_WIDTH 32
28133 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
28134 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET_MSK 0xffffffff
28135 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
28136 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_CLR_MSK 0x00000000
28137 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
28138 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_RESET 0x0
28139 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 field value from a register. */
28140 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_GET(value) (((value) & 0xffffffff) >> 0)
28141 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value suitable for setting the register. */
28142 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET(value) (((value) << 0) & 0xffffffff)
28143 
28144 #ifndef __ASSEMBLY__
28145 /*
28146  * WARNING: The C register and register group struct declarations are provided for
28147  * convenience and illustrative purposes. They should, however, be used with
28148  * caution as the C language standard provides no guarantees about the alignment or
28149  * atomicity of device memory accesses. The recommended practice for writing
28150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28151  * alt_write_word() functions.
28152  *
28153  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0.
28154  */
28155 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s
28156 {
28157  uint32_t l3a20 : 32; /* Layer 3 Address 2 Field */
28158 };
28159 
28160 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0. */
28161 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t;
28162 #endif /* __ASSEMBLY__ */
28163 
28164 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register from the beginning of the component. */
28165 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST 0x418
28166 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register. */
28167 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST))
28168 
28169 /*
28170  * Register : Register 263 (Layer 3 Address 3 Register 0) - Layer3_Addr3_Reg0
28171  *
28172  * For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames,
28173  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
28174  * Address field.
28175  *
28176  * Register Layout
28177  *
28178  * Bits | Access | Reset | Description
28179  * :-------|:-------|:------|:------------------------
28180  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
28181  *
28182  */
28183 /*
28184  * Field : Layer 3 Address 3 Field - l3a30
28185  *
28186  * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
28187  * Layer 4 Control Register 0), this field contains the value to be matched with
28188  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
28189  *
28190  * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
28191  * Layer 4 Control Register 0), this field contains the value to be matched with
28192  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
28193  *
28194  * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
28195  * Register 0), this register is not used.
28196  *
28197  * Field Access Macros:
28198  *
28199  */
28200 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
28201 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_LSB 0
28202 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
28203 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_MSB 31
28204 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
28205 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_WIDTH 32
28206 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
28207 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET_MSK 0xffffffff
28208 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
28209 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_CLR_MSK 0x00000000
28210 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
28211 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_RESET 0x0
28212 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 field value from a register. */
28213 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_GET(value) (((value) & 0xffffffff) >> 0)
28214 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value suitable for setting the register. */
28215 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET(value) (((value) << 0) & 0xffffffff)
28216 
28217 #ifndef __ASSEMBLY__
28218 /*
28219  * WARNING: The C register and register group struct declarations are provided for
28220  * convenience and illustrative purposes. They should, however, be used with
28221  * caution as the C language standard provides no guarantees about the alignment or
28222  * atomicity of device memory accesses. The recommended practice for writing
28223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28224  * alt_write_word() functions.
28225  *
28226  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0.
28227  */
28228 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s
28229 {
28230  uint32_t l3a30 : 32; /* Layer 3 Address 3 Field */
28231 };
28232 
28233 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0. */
28234 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t;
28235 #endif /* __ASSEMBLY__ */
28236 
28237 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register from the beginning of the component. */
28238 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST 0x41c
28239 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register. */
28240 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST))
28241 
28242 /*
28243  * Register : Register 268 (Layer 3 and Layer 4 Control Register 1) - L3_L4_Control1
28244  *
28245  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
28246  *
28247  * Register Layout
28248  *
28249  * Bits | Access | Reset | Description
28250  * :--------|:-------|:------|:----------------------------------------------
28251  * [0] | RW | 0x0 | Layer 3 Protocol Enable
28252  * [1] | ??? | 0x0 | *UNDEFINED*
28253  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
28254  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
28255  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
28256  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
28257  * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match
28258  * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match
28259  * [16] | RW | 0x0 | Layer 4 Protocol Enable
28260  * [17] | ??? | 0x0 | *UNDEFINED*
28261  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
28262  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
28263  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
28264  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
28265  * [31:22] | ??? | 0x0 | *UNDEFINED*
28266  *
28267  */
28268 /*
28269  * Field : Layer 3 Protocol Enable - l3pen1
28270  *
28271  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
28272  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
28273  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
28274  * frames.
28275  *
28276  * The Layer 3 matching is done only when either L3SAM1 or L3DAM1 bit is set high.
28277  *
28278  * Field Access Macros:
28279  *
28280  */
28281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
28282 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_LSB 0
28283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
28284 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_MSB 0
28285 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
28286 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_WIDTH 1
28287 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
28288 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET_MSK 0x00000001
28289 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
28290 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_CLR_MSK 0xfffffffe
28291 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
28292 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_RESET 0x0
28293 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 field value from a register. */
28294 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_GET(value) (((value) & 0x00000001) >> 0)
28295 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value suitable for setting the register. */
28296 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET(value) (((value) << 0) & 0x00000001)
28297 
28298 /*
28299  * Field : Layer 3 IP SA Match Enable - l3sam1
28300  *
28301  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
28302  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
28303  * for matching.
28304  *
28305  * Note: When Bit 0 (L3PEN1) is set, you should set either this bit or Bit 4
28306  * (L3DAM1) because either IPv6 SA or DA can be checked for filtering.
28307  *
28308  * Field Access Macros:
28309  *
28310  */
28311 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
28312 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_LSB 2
28313 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
28314 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_MSB 2
28315 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
28316 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_WIDTH 1
28317 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
28318 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET_MSK 0x00000004
28319 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
28320 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_CLR_MSK 0xfffffffb
28321 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
28322 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_RESET 0x0
28323 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 field value from a register. */
28324 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_GET(value) (((value) & 0x00000004) >> 2)
28325 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value suitable for setting the register. */
28326 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET(value) (((value) << 2) & 0x00000004)
28327 
28328 /*
28329  * Field : Layer 3 IP SA Inverse Match Enable - l3saim1
28330  *
28331  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
28332  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
28333  * Address field is enabled for perfect matching.
28334  *
28335  * This bit is valid and applicable only when Bit 2 (L3SAM1) is set high.
28336  *
28337  * Field Access Macros:
28338  *
28339  */
28340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
28341 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_LSB 3
28342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
28343 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_MSB 3
28344 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
28345 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_WIDTH 1
28346 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
28347 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET_MSK 0x00000008
28348 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
28349 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_CLR_MSK 0xfffffff7
28350 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
28351 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_RESET 0x0
28352 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 field value from a register. */
28353 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_GET(value) (((value) & 0x00000008) >> 3)
28354 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value suitable for setting the register. */
28355 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET(value) (((value) << 3) & 0x00000008)
28356 
28357 /*
28358  * Field : Layer 3 IP DA Match Enable - l3dam1
28359  *
28360  * When set, this bit indicates that Layer 3 IP Destination Address field is
28361  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
28362  * Address field for matching.
28363  *
28364  * Note: When Bit 1 (L3PEN1) is set, you should set either this bit or Bit 2
28365  * (L3SAM1) because either IPv6 DA or SA can be checked for filtering.
28366  *
28367  * Field Access Macros:
28368  *
28369  */
28370 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
28371 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_LSB 4
28372 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
28373 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_MSB 4
28374 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
28375 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_WIDTH 1
28376 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
28377 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET_MSK 0x00000010
28378 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
28379 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_CLR_MSK 0xffffffef
28380 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
28381 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_RESET 0x0
28382 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 field value from a register. */
28383 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_GET(value) (((value) & 0x00000010) >> 4)
28384 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value suitable for setting the register. */
28385 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET(value) (((value) << 4) & 0x00000010)
28386 
28387 /*
28388  * Field : Layer 3 IP DA Inverse Match Enable - l3daim1
28389  *
28390  * When set, this bit indicates that the Layer 3 IP Destination Address field is
28391  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
28392  * Destination Address field is enabled for perfect matching.
28393  *
28394  * This bit is valid and applicable only when Bit 4 (L3DAM1) is set high.
28395  *
28396  * Field Access Macros:
28397  *
28398  */
28399 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
28400 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_LSB 5
28401 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
28402 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_MSB 5
28403 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
28404 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_WIDTH 1
28405 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
28406 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET_MSK 0x00000020
28407 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
28408 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_CLR_MSK 0xffffffdf
28409 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
28410 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_RESET 0x0
28411 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 field value from a register. */
28412 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_GET(value) (((value) & 0x00000020) >> 5)
28413 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value suitable for setting the register. */
28414 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET(value) (((value) << 5) & 0x00000020)
28415 
28416 /*
28417  * Field : Layer 3 IP SA Higher Bits Match - l3hsbm1
28418  *
28419  * IPv4 Frames:
28420  *
28421  * This field contains the number of lower bits of IP Source Address that are
28422  * masked for matching in the IPv4 frames. The following list describes the values
28423  * of this field:
28424  *
28425  * * 0: No bits are masked.
28426  *
28427  * * 1: LSb[0] is masked.
28428  *
28429  * * 2: Two LSbs [1:0] are masked.
28430  *
28431  * * ...
28432  *
28433  * * 31: All bits except MSb are masked.
28434  *
28435  * IPv6 Frames:
28436  *
28437  * This field contains Bits [4:0] of the field that indicates the number of higher
28438  * bits of IP Source or Destination Address matched in the IPv6 frames.
28439  *
28440  * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
28441  *
28442  * Field Access Macros:
28443  *
28444  */
28445 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
28446 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_LSB 6
28447 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
28448 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_MSB 10
28449 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
28450 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_WIDTH 5
28451 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
28452 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET_MSK 0x000007c0
28453 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
28454 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_CLR_MSK 0xfffff83f
28455 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
28456 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_RESET 0x0
28457 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 field value from a register. */
28458 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_GET(value) (((value) & 0x000007c0) >> 6)
28459 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value suitable for setting the register. */
28460 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET(value) (((value) << 6) & 0x000007c0)
28461 
28462 /*
28463  * Field : Layer 3 IP DA Higher Bits Match - l3hdbm1
28464  *
28465  * IPv4 Frames:
28466  *
28467  * This field contains the number of higher bits of IP Destination Address that are
28468  * matched in the IPv4 frames. The following list describes the values of this
28469  * field:
28470  *
28471  * * 0: No bits are masked.
28472  *
28473  * * 1: LSb[0] is masked.
28474  *
28475  * * 2: Two LSbs [1:0] are masked.
28476  *
28477  * * ...
28478  *
28479  * * 31: All bits except MSb are masked.
28480  *
28481  * IPv6 Frames:
28482  *
28483  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM1, which indicate
28484  * the number of lower bits of IP Source or Destination Address that are masked in
28485  * the IPv6 frames. The following list describes the concatenated values of the
28486  * L3HDBM1[1:0] and L3HSBM1 bits:
28487  *
28488  * * 0: No bits are masked.
28489  *
28490  * * 1: LSb[0] is masked.
28491  *
28492  * * 2: Two LSbs [1:0] are masked.
28493  *
28494  * * ...
28495  *
28496  * * 127: All bits except MSb are masked.
28497  *
28498  * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
28499  *
28500  * Field Access Macros:
28501  *
28502  */
28503 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
28504 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_LSB 11
28505 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
28506 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_MSB 15
28507 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
28508 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_WIDTH 5
28509 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
28510 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET_MSK 0x0000f800
28511 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
28512 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_CLR_MSK 0xffff07ff
28513 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
28514 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_RESET 0x0
28515 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 field value from a register. */
28516 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_GET(value) (((value) & 0x0000f800) >> 11)
28517 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value suitable for setting the register. */
28518 #define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET(value) (((value) << 11) & 0x0000f800)
28519 
28520 /*
28521  * Field : Layer 4 Protocol Enable - l4pen1
28522  *
28523  * When set, this bit indicates that the Source and Destination Port number fields
28524  * for UDP frames are used for matching. When reset, this bit indicates that the
28525  * Source and Destination Port number fields for TCP frames are used for matching.
28526  *
28527  * The Layer 4 matching is done only when either L4SPM1 or L4DPM1 bit is set high.
28528  *
28529  * Field Access Macros:
28530  *
28531  */
28532 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
28533 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_LSB 16
28534 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
28535 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_MSB 16
28536 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
28537 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_WIDTH 1
28538 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
28539 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET_MSK 0x00010000
28540 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
28541 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_CLR_MSK 0xfffeffff
28542 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
28543 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_RESET 0x0
28544 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 field value from a register. */
28545 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_GET(value) (((value) & 0x00010000) >> 16)
28546 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value suitable for setting the register. */
28547 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET(value) (((value) << 16) & 0x00010000)
28548 
28549 /*
28550  * Field : Layer 4 Source Port Match Enable - l4spm1
28551  *
28552  * When set, this bit indicates that the Layer 4 Source Port number field is
28553  * enabled for matching.
28554  *
28555  * When reset, the MAC ignores the Layer 4 Source Port number field for matching.
28556  *
28557  * Field Access Macros:
28558  *
28559  */
28560 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
28561 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_LSB 18
28562 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
28563 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_MSB 18
28564 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
28565 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_WIDTH 1
28566 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
28567 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET_MSK 0x00040000
28568 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
28569 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_CLR_MSK 0xfffbffff
28570 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
28571 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_RESET 0x0
28572 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 field value from a register. */
28573 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_GET(value) (((value) & 0x00040000) >> 18)
28574 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value suitable for setting the register. */
28575 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET(value) (((value) << 18) & 0x00040000)
28576 
28577 /*
28578  * Field : Layer 4 Source Port Inverse Match Enable - l4spim1
28579  *
28580  * When set, this bit indicates that the Layer 4 Source Port number field is
28581  * enabled for inverse matching.
28582  *
28583  * When reset, this bit indicates that the Layer 4 Source Port number field is
28584  * enabled for perfect matching.
28585  *
28586  * This bit is valid and applicable only when Bit 18 (L4SPM1) is set high.
28587  *
28588  * Field Access Macros:
28589  *
28590  */
28591 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
28592 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_LSB 19
28593 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
28594 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_MSB 19
28595 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
28596 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_WIDTH 1
28597 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
28598 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET_MSK 0x00080000
28599 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
28600 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_CLR_MSK 0xfff7ffff
28601 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
28602 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_RESET 0x0
28603 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 field value from a register. */
28604 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_GET(value) (((value) & 0x00080000) >> 19)
28605 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value suitable for setting the register. */
28606 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET(value) (((value) << 19) & 0x00080000)
28607 
28608 /*
28609  * Field : Layer 4 Destination Port Match Enable - l4dpm1
28610  *
28611  * When set, this bit indicates that the Layer 4 Destination Port number field is
28612  * enabled for matching.
28613  *
28614  * When reset, the MAC ignores the Layer 4 Destination Port number field for
28615  * matching.
28616  *
28617  * Field Access Macros:
28618  *
28619  */
28620 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
28621 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_LSB 20
28622 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
28623 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_MSB 20
28624 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
28625 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_WIDTH 1
28626 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
28627 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET_MSK 0x00100000
28628 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
28629 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_CLR_MSK 0xffefffff
28630 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
28631 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_RESET 0x0
28632 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 field value from a register. */
28633 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_GET(value) (((value) & 0x00100000) >> 20)
28634 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value suitable for setting the register. */
28635 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET(value) (((value) << 20) & 0x00100000)
28636 
28637 /*
28638  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim1
28639  *
28640  * When set, this bit indicates that the Layer 4 Destination Port number field is
28641  * enabled for inverse matching.
28642  *
28643  * When reset, this bit indicates that the Layer 4 Destination Port number field is
28644  * enabled for perfect matching.
28645  *
28646  * This bit is valid and applicable only when Bit 20 (L4DPM1) is set high.
28647  *
28648  * Field Access Macros:
28649  *
28650  */
28651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
28652 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_LSB 21
28653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
28654 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_MSB 21
28655 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
28656 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_WIDTH 1
28657 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
28658 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET_MSK 0x00200000
28659 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
28660 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_CLR_MSK 0xffdfffff
28661 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
28662 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_RESET 0x0
28663 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 field value from a register. */
28664 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_GET(value) (((value) & 0x00200000) >> 21)
28665 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value suitable for setting the register. */
28666 #define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET(value) (((value) << 21) & 0x00200000)
28667 
28668 #ifndef __ASSEMBLY__
28669 /*
28670  * WARNING: The C register and register group struct declarations are provided for
28671  * convenience and illustrative purposes. They should, however, be used with
28672  * caution as the C language standard provides no guarantees about the alignment or
28673  * atomicity of device memory accesses. The recommended practice for writing
28674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28675  * alt_write_word() functions.
28676  *
28677  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL1.
28678  */
28679 struct ALT_EMAC_GMAC_L3_L4_CTL1_s
28680 {
28681  uint32_t l3pen1 : 1; /* Layer 3 Protocol Enable */
28682  uint32_t : 1; /* *UNDEFINED* */
28683  uint32_t l3sam1 : 1; /* Layer 3 IP SA Match Enable */
28684  uint32_t l3saim1 : 1; /* Layer 3 IP SA Inverse Match Enable */
28685  uint32_t l3dam1 : 1; /* Layer 3 IP DA Match Enable */
28686  uint32_t l3daim1 : 1; /* Layer 3 IP DA Inverse Match Enable */
28687  uint32_t l3hsbm1 : 5; /* Layer 3 IP SA Higher Bits Match */
28688  uint32_t l3hdbm1 : 5; /* Layer 3 IP DA Higher Bits Match */
28689  uint32_t l4pen1 : 1; /* Layer 4 Protocol Enable */
28690  uint32_t : 1; /* *UNDEFINED* */
28691  uint32_t l4spm1 : 1; /* Layer 4 Source Port Match Enable */
28692  uint32_t l4spim1 : 1; /* Layer 4 Source Port Inverse Match Enable */
28693  uint32_t l4dpm1 : 1; /* Layer 4 Destination Port Match Enable */
28694  uint32_t l4dpim1 : 1; /* Layer 4 Destination Port Inverse Match Enable */
28695  uint32_t : 10; /* *UNDEFINED* */
28696 };
28697 
28698 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL1. */
28699 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL1_s ALT_EMAC_GMAC_L3_L4_CTL1_t;
28700 #endif /* __ASSEMBLY__ */
28701 
28702 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL1 register from the beginning of the component. */
28703 #define ALT_EMAC_GMAC_L3_L4_CTL1_OFST 0x430
28704 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register. */
28705 #define ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL1_OFST))
28706 
28707 /*
28708  * Register : Register 269 (Layer 4 Address Register 1) - Layer4_Address1
28709  *
28710  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
28711  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
28712  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
28713  * Layer 4 Address Registers are written. For proper synchronization updates, you
28714  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
28715  * Registers after at least four clock cycles delay of the destination clock.
28716  *
28717  * Register Layout
28718  *
28719  * Bits | Access | Reset | Description
28720  * :--------|:-------|:------|:--------------------------------------
28721  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
28722  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
28723  *
28724  */
28725 /*
28726  * Field : Layer 4 Source Port Number Field - l4sp1
28727  *
28728  * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
28729  * 3 and Layer 4 Control Register 1), this field contains the value to be matched
28730  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
28731  *
28732  * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
28733  * Layer 4 Control Register 1), this field contains the value to be matched with
28734  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
28735  *
28736  * Field Access Macros:
28737  *
28738  */
28739 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
28740 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_LSB 0
28741 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
28742 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_MSB 15
28743 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
28744 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_WIDTH 16
28745 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
28746 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET_MSK 0x0000ffff
28747 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
28748 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_CLR_MSK 0xffff0000
28749 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
28750 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_RESET 0x0
28751 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 field value from a register. */
28752 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_GET(value) (((value) & 0x0000ffff) >> 0)
28753 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value suitable for setting the register. */
28754 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET(value) (((value) << 0) & 0x0000ffff)
28755 
28756 /*
28757  * Field : Layer 4 Destination Port Number Field - l4dp1
28758  *
28759  * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
28760  * 3 and Layer 4 Control Register 0), this field contains the value to be matched
28761  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
28762  *
28763  * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
28764  * Layer 4 Control Register 1), this field contains the value to be matched with
28765  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
28766  *
28767  * Field Access Macros:
28768  *
28769  */
28770 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
28771 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_LSB 16
28772 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
28773 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_MSB 31
28774 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
28775 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_WIDTH 16
28776 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
28777 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET_MSK 0xffff0000
28778 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
28779 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_CLR_MSK 0x0000ffff
28780 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
28781 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_RESET 0x0
28782 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 field value from a register. */
28783 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_GET(value) (((value) & 0xffff0000) >> 16)
28784 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value suitable for setting the register. */
28785 #define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET(value) (((value) << 16) & 0xffff0000)
28786 
28787 #ifndef __ASSEMBLY__
28788 /*
28789  * WARNING: The C register and register group struct declarations are provided for
28790  * convenience and illustrative purposes. They should, however, be used with
28791  * caution as the C language standard provides no guarantees about the alignment or
28792  * atomicity of device memory accesses. The recommended practice for writing
28793  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28794  * alt_write_word() functions.
28795  *
28796  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR1.
28797  */
28798 struct ALT_EMAC_GMAC_LYR4_ADDR1_s
28799 {
28800  uint32_t l4sp1 : 16; /* Layer 4 Source Port Number Field */
28801  uint32_t l4dp1 : 16; /* Layer 4 Destination Port Number Field */
28802 };
28803 
28804 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR1. */
28805 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR1_s ALT_EMAC_GMAC_LYR4_ADDR1_t;
28806 #endif /* __ASSEMBLY__ */
28807 
28808 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR1 register from the beginning of the component. */
28809 #define ALT_EMAC_GMAC_LYR4_ADDR1_OFST 0x434
28810 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register. */
28811 #define ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR1_OFST))
28812 
28813 /*
28814  * Register : Register 272 (Layer 3 Address 0 Register 1) - Layer3_Addr0_Reg1
28815  *
28816  * For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source
28817  * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
28818  * Address or Destination Address field.
28819  *
28820  * Register Layout
28821  *
28822  * Bits | Access | Reset | Description
28823  * :-------|:-------|:------|:------------------------
28824  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
28825  *
28826  */
28827 /*
28828  * Field : Layer 3 Address 0 Field - l3a01
28829  *
28830  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
28831  * Layer 4 Control Register 1), this field contains the value to be matched with
28832  * Bits[31:0] of the IP Source Address field in the IPv6 frames.
28833  *
28834  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
28835  * Layer 4 Control Register 1), this field contains the value to be matched with
28836  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
28837  *
28838  * When Bit 0 (L3PEN1) is reset and Bit 2 (L3SAM1) is set in Register 268 (Layer 3
28839  * and Layer 4 Control Register 1), this field contains the value to be matched
28840  * with the IP Source Address field in the IPv4 frames.
28841  *
28842  * Field Access Macros:
28843  *
28844  */
28845 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
28846 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_LSB 0
28847 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
28848 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_MSB 31
28849 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
28850 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_WIDTH 32
28851 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
28852 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET_MSK 0xffffffff
28853 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
28854 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_CLR_MSK 0x00000000
28855 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
28856 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_RESET 0x0
28857 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 field value from a register. */
28858 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_GET(value) (((value) & 0xffffffff) >> 0)
28859 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value suitable for setting the register. */
28860 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET(value) (((value) << 0) & 0xffffffff)
28861 
28862 #ifndef __ASSEMBLY__
28863 /*
28864  * WARNING: The C register and register group struct declarations are provided for
28865  * convenience and illustrative purposes. They should, however, be used with
28866  * caution as the C language standard provides no guarantees about the alignment or
28867  * atomicity of device memory accesses. The recommended practice for writing
28868  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28869  * alt_write_word() functions.
28870  *
28871  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1.
28872  */
28873 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s
28874 {
28875  uint32_t l3a01 : 32; /* Layer 3 Address 0 Field */
28876 };
28877 
28878 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1. */
28879 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t;
28880 #endif /* __ASSEMBLY__ */
28881 
28882 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register from the beginning of the component. */
28883 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST 0x440
28884 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register. */
28885 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST))
28886 
28887 /*
28888  * Register : Register 273 (Layer 3 Address 1 Register 1) - Layer3_Addr1_Reg1
28889  *
28890  * For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP
28891  * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
28892  * 128-bit IP Source Address or Destination Address field
28893  *
28894  * Register Layout
28895  *
28896  * Bits | Access | Reset | Description
28897  * :-------|:-------|:------|:------------------------
28898  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
28899  *
28900  */
28901 /*
28902  * Field : Layer 3 Address 1 Field - l3a11
28903  *
28904  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
28905  * Layer 4 Control Register 1), this field contains the value to be matched with
28906  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
28907  *
28908  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
28909  * Layer 4 Control Register 1), this field contains the value to be matched with
28910  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
28911  *
28912  * When Bit 0 (L3PEN1) is reset and Bit 4 (L3DAM1) is set in Register 268 (Layer 3
28913  * and Layer 4 Control Register 1), this field contains the value to be matched
28914  * with the IP Destination Address field in the IPv4 frames.
28915  *
28916  * Field Access Macros:
28917  *
28918  */
28919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
28920 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_LSB 0
28921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
28922 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_MSB 31
28923 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
28924 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_WIDTH 32
28925 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
28926 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET_MSK 0xffffffff
28927 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
28928 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_CLR_MSK 0x00000000
28929 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
28930 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_RESET 0x0
28931 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 field value from a register. */
28932 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_GET(value) (((value) & 0xffffffff) >> 0)
28933 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value suitable for setting the register. */
28934 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET(value) (((value) << 0) & 0xffffffff)
28935 
28936 #ifndef __ASSEMBLY__
28937 /*
28938  * WARNING: The C register and register group struct declarations are provided for
28939  * convenience and illustrative purposes. They should, however, be used with
28940  * caution as the C language standard provides no guarantees about the alignment or
28941  * atomicity of device memory accesses. The recommended practice for writing
28942  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
28943  * alt_write_word() functions.
28944  *
28945  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1.
28946  */
28947 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s
28948 {
28949  uint32_t l3a11 : 32; /* Layer 3 Address 1 Field */
28950 };
28951 
28952 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1. */
28953 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t;
28954 #endif /* __ASSEMBLY__ */
28955 
28956 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register from the beginning of the component. */
28957 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST 0x444
28958 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register. */
28959 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST))
28960 
28961 /*
28962  * Register : Register 274 (Layer 3 Address 2 Register 1) - Layer3_Addr2_Reg1
28963  *
28964  * For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames,
28965  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
28966  * field.
28967  *
28968  * Register Layout
28969  *
28970  * Bits | Access | Reset | Description
28971  * :-------|:-------|:------|:------------------------
28972  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
28973  *
28974  */
28975 /*
28976  * Field : Layer 3 Address 2 Field - l3a21
28977  *
28978  * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
28979  * Layer 4 Control Register 1), this field contains the value to be matched with
28980  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
28981  *
28982  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
28983  * Layer 4 Control Register 1), this field contains value to be matched with Bits
28984  * [95:64] of the IP Destination Address field in the IPv6 frames.
28985  *
28986  * Field Access Macros:
28987  *
28988  */
28989 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
28990 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_LSB 0
28991 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
28992 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_MSB 31
28993 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
28994 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_WIDTH 32
28995 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
28996 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET_MSK 0xffffffff
28997 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
28998 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_CLR_MSK 0x00000000
28999 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
29000 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_RESET 0x0
29001 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 field value from a register. */
29002 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_GET(value) (((value) & 0xffffffff) >> 0)
29003 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value suitable for setting the register. */
29004 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET(value) (((value) << 0) & 0xffffffff)
29005 
29006 #ifndef __ASSEMBLY__
29007 /*
29008  * WARNING: The C register and register group struct declarations are provided for
29009  * convenience and illustrative purposes. They should, however, be used with
29010  * caution as the C language standard provides no guarantees about the alignment or
29011  * atomicity of device memory accesses. The recommended practice for writing
29012  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29013  * alt_write_word() functions.
29014  *
29015  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1.
29016  */
29017 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s
29018 {
29019  uint32_t l3a21 : 32; /* Layer 3 Address 2 Field */
29020 };
29021 
29022 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1. */
29023 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t;
29024 #endif /* __ASSEMBLY__ */
29025 
29026 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register from the beginning of the component. */
29027 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST 0x448
29028 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register. */
29029 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST))
29030 
29031 /*
29032  * Register : Register 275 (Layer 3 Address 3 Register 1) - Layer3_Addr3_Reg1
29033  *
29034  * For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames,
29035  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
29036  * Address field.
29037  *
29038  * Register Layout
29039  *
29040  * Bits | Access | Reset | Description
29041  * :-------|:-------|:------|:------------------------
29042  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
29043  *
29044  */
29045 /*
29046  * Field : Layer 3 Address 3 Field - l3a31
29047  *
29048  * When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
29049  * Layer 4 Control Register 1), this field contains the value to be matched with
29050  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
29051  *
29052  * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
29053  * Layer 4 Control Register 1), this field contains the value to be matched with
29054  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
29055  *
29056  * When Bit 0 (L3PEN1) is reset in Register 268 (Layer 3 and Layer 4 Control
29057  * Register 1), this register is not used.
29058  *
29059  * Field Access Macros:
29060  *
29061  */
29062 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
29063 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_LSB 0
29064 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
29065 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_MSB 31
29066 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
29067 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_WIDTH 32
29068 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
29069 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET_MSK 0xffffffff
29070 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
29071 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_CLR_MSK 0x00000000
29072 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
29073 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_RESET 0x0
29074 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 field value from a register. */
29075 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_GET(value) (((value) & 0xffffffff) >> 0)
29076 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value suitable for setting the register. */
29077 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET(value) (((value) << 0) & 0xffffffff)
29078 
29079 #ifndef __ASSEMBLY__
29080 /*
29081  * WARNING: The C register and register group struct declarations are provided for
29082  * convenience and illustrative purposes. They should, however, be used with
29083  * caution as the C language standard provides no guarantees about the alignment or
29084  * atomicity of device memory accesses. The recommended practice for writing
29085  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29086  * alt_write_word() functions.
29087  *
29088  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1.
29089  */
29090 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s
29091 {
29092  uint32_t l3a31 : 32; /* Layer 3 Address 3 Field */
29093 };
29094 
29095 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1. */
29096 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t;
29097 #endif /* __ASSEMBLY__ */
29098 
29099 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register from the beginning of the component. */
29100 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST 0x44c
29101 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register. */
29102 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST))
29103 
29104 /*
29105  * Register : Register 280 (Layer 3 and Layer 4 Control Register 2) - L3_L4_Control2
29106  *
29107  * This register controls the operations of the filter 2 of Layer 3 and Layer 4.
29108  *
29109  * Register Layout
29110  *
29111  * Bits | Access | Reset | Description
29112  * :--------|:-------|:------|:----------------------------------------------
29113  * [0] | RW | 0x0 | Layer 3 Protocol Enable
29114  * [1] | ??? | 0x0 | *UNDEFINED*
29115  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
29116  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
29117  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
29118  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
29119  * [10:6] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2
29120  * [15:11] | RW | 0x0 | Layer 3 IP DA Higher Bits Match
29121  * [16] | RW | 0x0 | Layer 4 Protocol Enable
29122  * [17] | ??? | 0x0 | *UNDEFINED*
29123  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
29124  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
29125  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
29126  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
29127  * [31:22] | ??? | 0x0 | *UNDEFINED*
29128  *
29129  */
29130 /*
29131  * Field : Layer 3 Protocol Enable - l3pen2
29132  *
29133  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
29134  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
29135  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
29136  * frames.
29137  *
29138  * The Layer 3 matching is done only when either L3SAM2 or L3DAM2 bit is set high.
29139  *
29140  * Field Access Macros:
29141  *
29142  */
29143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
29144 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB 0
29145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
29146 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB 0
29147 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
29148 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH 1
29149 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
29150 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK 0x00000001
29151 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
29152 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK 0xfffffffe
29153 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
29154 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET 0x0
29155 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 field value from a register. */
29156 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET(value) (((value) & 0x00000001) >> 0)
29157 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value suitable for setting the register. */
29158 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET(value) (((value) << 0) & 0x00000001)
29159 
29160 /*
29161  * Field : Layer 3 IP SA Match Enable - l3sam2
29162  *
29163  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
29164  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
29165  * for matching.
29166  *
29167  * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 4
29168  * (L3DAM2) because either IPv6 SA or DA can be checked for filtering.
29169  *
29170  * Field Access Macros:
29171  *
29172  */
29173 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
29174 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB 2
29175 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
29176 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB 2
29177 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
29178 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH 1
29179 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
29180 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK 0x00000004
29181 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
29182 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK 0xfffffffb
29183 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
29184 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET 0x0
29185 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 field value from a register. */
29186 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET(value) (((value) & 0x00000004) >> 2)
29187 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value suitable for setting the register. */
29188 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET(value) (((value) << 2) & 0x00000004)
29189 
29190 /*
29191  * Field : Layer 3 IP SA Inverse Match Enable - l3saim2
29192  *
29193  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
29194  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
29195  * Address field is enabled for perfect matching.
29196  *
29197  * This bit is valid and applicable only when Bit 2 (L3SAM2) is set high.
29198  *
29199  * Field Access Macros:
29200  *
29201  */
29202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
29203 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB 3
29204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
29205 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB 3
29206 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
29207 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH 1
29208 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
29209 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK 0x00000008
29210 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
29211 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK 0xfffffff7
29212 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
29213 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET 0x0
29214 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 field value from a register. */
29215 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET(value) (((value) & 0x00000008) >> 3)
29216 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value suitable for setting the register. */
29217 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET(value) (((value) << 3) & 0x00000008)
29218 
29219 /*
29220  * Field : Layer 3 IP DA Match Enable - l3dam2
29221  *
29222  * When set, this bit indicates that Layer 3 IP Destination Address field is
29223  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
29224  * Address field for matching.
29225  *
29226  * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 2
29227  * (L3SAM2) because either IPv6 DA or SA can be checked for filtering.
29228  *
29229  * Field Access Macros:
29230  *
29231  */
29232 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
29233 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB 4
29234 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
29235 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB 4
29236 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
29237 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH 1
29238 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
29239 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK 0x00000010
29240 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
29241 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK 0xffffffef
29242 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
29243 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET 0x0
29244 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 field value from a register. */
29245 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET(value) (((value) & 0x00000010) >> 4)
29246 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value suitable for setting the register. */
29247 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET(value) (((value) << 4) & 0x00000010)
29248 
29249 /*
29250  * Field : Layer 3 IP DA Inverse Match Enable - l3daim2
29251  *
29252  * When set, this bit indicates that the Layer 3 IP Destination Address field is
29253  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
29254  * Destination Address field is enabled for perfect matching.
29255  *
29256  * This bit is valid and applicable only when Bit 4 (L3DAM2) is set high.
29257  *
29258  * Field Access Macros:
29259  *
29260  */
29261 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
29262 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB 5
29263 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
29264 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB 5
29265 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
29266 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH 1
29267 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
29268 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK 0x00000020
29269 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
29270 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK 0xffffffdf
29271 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
29272 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET 0x0
29273 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 field value from a register. */
29274 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET(value) (((value) & 0x00000020) >> 5)
29275 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value suitable for setting the register. */
29276 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET(value) (((value) << 5) & 0x00000020)
29277 
29278 /*
29279  * Field : l3hsbm2
29280  *
29281  * Layer 3 IP SA Higher Bits Match
29282  *
29283  * IPv4 Frames:
29284  *
29285  * This field contains the number of lower bits of IP Source Address that are
29286  * masked for matching in the IPv4 frames. The following list describes the values
29287  * of this field:
29288  *
29289  * * 0: No bits are masked.
29290  *
29291  * * 1: LSb[0] is masked.
29292  *
29293  * * 2: Two LSbs [1:0] are masked.
29294  *
29295  * * ...
29296  *
29297  * * 31: All bits except MSb are masked.
29298  *
29299  * IPv6 Frames:
29300  *
29301  * This field contains Bits [4:0] of the field that indicates the number of higher
29302  * bits of IP Source or Destination Address matched in the IPv6 frames.
29303  *
29304  * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
29305  *
29306  * Field Access Macros:
29307  *
29308  */
29309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
29310 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB 6
29311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
29312 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB 10
29313 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
29314 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH 5
29315 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
29316 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK 0x000007c0
29317 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
29318 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK 0xfffff83f
29319 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
29320 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET 0x0
29321 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 field value from a register. */
29322 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET(value) (((value) & 0x000007c0) >> 6)
29323 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value suitable for setting the register. */
29324 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET(value) (((value) << 6) & 0x000007c0)
29325 
29326 /*
29327  * Field : Layer 3 IP DA Higher Bits Match - l3hdbm2
29328  *
29329  * IPv4 Frames:
29330  *
29331  * This field contains the number of higher bits of IP Destination Address that are
29332  * matched in the IPv4 frames. The following list describes the values of this
29333  * field:
29334  *
29335  * * 0: No bits are masked.
29336  *
29337  * * 1: LSb[0] is masked.
29338  *
29339  * * 2: Two LSbs [1:0] are masked.
29340  *
29341  * * ...
29342  *
29343  * * 31: All bits except MSb are masked.
29344  *
29345  * IPv6 Frames:
29346  *
29347  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM2, which indicate
29348  * the number of lower bits of IP Source or Destination Address that are masked in
29349  * the IPv6 frames. The following list describes the concatenated values of the
29350  * L3HDBM2[1:0] and L3HSBM2 bits:
29351  *
29352  * * 0: No bits are masked.
29353  *
29354  * * 1: LSb[0] is masked.
29355  *
29356  * * 2: Two LSbs [1:0] are masked.
29357  *
29358  * * ...
29359  *
29360  * * 127: All bits except MSb are masked.
29361  *
29362  * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
29363  *
29364  * Field Access Macros:
29365  *
29366  */
29367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
29368 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB 11
29369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
29370 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB 15
29371 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
29372 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH 5
29373 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
29374 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK 0x0000f800
29375 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
29376 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK 0xffff07ff
29377 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
29378 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET 0x0
29379 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 field value from a register. */
29380 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET(value) (((value) & 0x0000f800) >> 11)
29381 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value suitable for setting the register. */
29382 #define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET(value) (((value) << 11) & 0x0000f800)
29383 
29384 /*
29385  * Field : Layer 4 Protocol Enable - l4pen2
29386  *
29387  * When set, this bit indicates that the Source and Destination Port number fields
29388  * for UDP frames are used for matching. When reset, this bit indicates that the
29389  * Source and Destination Port number fields for TCP frames are used for matching.
29390  *
29391  * The Layer 4 matching is done only when either L4SPM2 or L4DPM2 bit is set high.
29392  *
29393  * Field Access Macros:
29394  *
29395  */
29396 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
29397 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB 16
29398 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
29399 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB 16
29400 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
29401 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH 1
29402 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
29403 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK 0x00010000
29404 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
29405 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK 0xfffeffff
29406 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
29407 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET 0x0
29408 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 field value from a register. */
29409 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET(value) (((value) & 0x00010000) >> 16)
29410 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value suitable for setting the register. */
29411 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET(value) (((value) << 16) & 0x00010000)
29412 
29413 /*
29414  * Field : Layer 4 Source Port Match Enable - l4spm2
29415  *
29416  * When set, this bit indicates that the Layer 4 Source Port number field is
29417  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
29418  * field for matching.
29419  *
29420  * Field Access Macros:
29421  *
29422  */
29423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
29424 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB 18
29425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
29426 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB 18
29427 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
29428 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH 1
29429 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
29430 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK 0x00040000
29431 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
29432 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK 0xfffbffff
29433 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
29434 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET 0x0
29435 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 field value from a register. */
29436 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET(value) (((value) & 0x00040000) >> 18)
29437 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value suitable for setting the register. */
29438 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET(value) (((value) << 18) & 0x00040000)
29439 
29440 /*
29441  * Field : Layer 4 Source Port Inverse Match Enable - l4spim2
29442  *
29443  * When set, this bit indicates that the Layer 4 Source Port number field is
29444  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
29445  * Source Port number field is enabled for perfect matching.
29446  *
29447  * This bit is valid and applicable only when Bit 18 (L4SPM2) is set high.
29448  *
29449  * Field Access Macros:
29450  *
29451  */
29452 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
29453 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB 19
29454 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
29455 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB 19
29456 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
29457 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH 1
29458 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
29459 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK 0x00080000
29460 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
29461 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK 0xfff7ffff
29462 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
29463 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET 0x0
29464 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 field value from a register. */
29465 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET(value) (((value) & 0x00080000) >> 19)
29466 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value suitable for setting the register. */
29467 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET(value) (((value) << 19) & 0x00080000)
29468 
29469 /*
29470  * Field : Layer 4 Destination Port Match Enable - l4dpm2
29471  *
29472  * When set, this bit indicates that the Layer 4 Destination Port number field is
29473  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
29474  * number field for matching.
29475  *
29476  * Field Access Macros:
29477  *
29478  */
29479 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
29480 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB 20
29481 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
29482 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB 20
29483 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
29484 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH 1
29485 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
29486 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK 0x00100000
29487 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
29488 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK 0xffefffff
29489 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
29490 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET 0x0
29491 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 field value from a register. */
29492 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET(value) (((value) & 0x00100000) >> 20)
29493 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value suitable for setting the register. */
29494 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET(value) (((value) << 20) & 0x00100000)
29495 
29496 /*
29497  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim2
29498  *
29499  * When set, this bit indicates that the Layer 4 Destination Port number field is
29500  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
29501  * Destination Port number field is enabled for perfect matching.
29502  *
29503  * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
29504  *
29505  * Field Access Macros:
29506  *
29507  */
29508 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
29509 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB 21
29510 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
29511 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB 21
29512 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
29513 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH 1
29514 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
29515 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK 0x00200000
29516 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
29517 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK 0xffdfffff
29518 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
29519 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET 0x0
29520 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 field value from a register. */
29521 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET(value) (((value) & 0x00200000) >> 21)
29522 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value suitable for setting the register. */
29523 #define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET(value) (((value) << 21) & 0x00200000)
29524 
29525 #ifndef __ASSEMBLY__
29526 /*
29527  * WARNING: The C register and register group struct declarations are provided for
29528  * convenience and illustrative purposes. They should, however, be used with
29529  * caution as the C language standard provides no guarantees about the alignment or
29530  * atomicity of device memory accesses. The recommended practice for writing
29531  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29532  * alt_write_word() functions.
29533  *
29534  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL2.
29535  */
29536 struct ALT_EMAC_GMAC_L3_L4_CTL2_s
29537 {
29538  uint32_t l3pen2 : 1; /* Layer 3 Protocol Enable */
29539  uint32_t : 1; /* *UNDEFINED* */
29540  uint32_t l3sam2 : 1; /* Layer 3 IP SA Match Enable */
29541  uint32_t l3saim2 : 1; /* Layer 3 IP SA Inverse Match Enable */
29542  uint32_t l3dam2 : 1; /* Layer 3 IP DA Match Enable */
29543  uint32_t l3daim2 : 1; /* Layer 3 IP DA Inverse Match Enable */
29544  uint32_t l3hsbm2 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 */
29545  uint32_t l3hdbm2 : 5; /* Layer 3 IP DA Higher Bits Match */
29546  uint32_t l4pen2 : 1; /* Layer 4 Protocol Enable */
29547  uint32_t : 1; /* *UNDEFINED* */
29548  uint32_t l4spm2 : 1; /* Layer 4 Source Port Match Enable */
29549  uint32_t l4spim2 : 1; /* Layer 4 Source Port Inverse Match Enable */
29550  uint32_t l4dpm2 : 1; /* Layer 4 Destination Port Match Enable */
29551  uint32_t l4dpim2 : 1; /* Layer 4 Destination Port Inverse Match Enable */
29552  uint32_t : 10; /* *UNDEFINED* */
29553 };
29554 
29555 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL2. */
29556 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL2_s ALT_EMAC_GMAC_L3_L4_CTL2_t;
29557 #endif /* __ASSEMBLY__ */
29558 
29559 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL2 register from the beginning of the component. */
29560 #define ALT_EMAC_GMAC_L3_L4_CTL2_OFST 0x460
29561 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register. */
29562 #define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST))
29563 
29564 /*
29565  * Register : Register 281 (Layer 4 Address Register 2) - Layer4_Address2
29566  *
29567  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
29568  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
29569  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
29570  * Layer 4 Address Registers are written. For proper synchronization updates, you
29571  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
29572  * Registers after at least four clock cycles delay of the destination clock.
29573  *
29574  * Register Layout
29575  *
29576  * Bits | Access | Reset | Description
29577  * :--------|:-------|:------|:--------------------------------------
29578  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
29579  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
29580  *
29581  */
29582 /*
29583  * Field : Layer 4 Source Port Number Field - l4sp2
29584  *
29585  * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
29586  * 3 and Layer 4 Control Register 2), this field contains the value to be matched
29587  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
29588  *
29589  * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
29590  * Layer 4 Control Register 2), this field contains the value to be matched with
29591  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
29592  *
29593  * Field Access Macros:
29594  *
29595  */
29596 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
29597 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_LSB 0
29598 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
29599 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_MSB 15
29600 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
29601 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_WIDTH 16
29602 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
29603 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET_MSK 0x0000ffff
29604 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
29605 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_CLR_MSK 0xffff0000
29606 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
29607 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_RESET 0x0
29608 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 field value from a register. */
29609 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_GET(value) (((value) & 0x0000ffff) >> 0)
29610 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value suitable for setting the register. */
29611 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET(value) (((value) << 0) & 0x0000ffff)
29612 
29613 /*
29614  * Field : Layer 4 Destination Port Number Field - l4dp2
29615  *
29616  * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
29617  * 3 and Layer 4 Control Register 2), this field contains the value to be matched
29618  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
29619  *
29620  * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
29621  * Layer 4 Control Register 2), this field contains the value to be matched with
29622  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
29623  *
29624  * Field Access Macros:
29625  *
29626  */
29627 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
29628 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_LSB 16
29629 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
29630 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_MSB 31
29631 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
29632 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_WIDTH 16
29633 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
29634 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET_MSK 0xffff0000
29635 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
29636 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_CLR_MSK 0x0000ffff
29637 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
29638 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_RESET 0x0
29639 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 field value from a register. */
29640 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_GET(value) (((value) & 0xffff0000) >> 16)
29641 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value suitable for setting the register. */
29642 #define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET(value) (((value) << 16) & 0xffff0000)
29643 
29644 #ifndef __ASSEMBLY__
29645 /*
29646  * WARNING: The C register and register group struct declarations are provided for
29647  * convenience and illustrative purposes. They should, however, be used with
29648  * caution as the C language standard provides no guarantees about the alignment or
29649  * atomicity of device memory accesses. The recommended practice for writing
29650  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29651  * alt_write_word() functions.
29652  *
29653  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR2.
29654  */
29655 struct ALT_EMAC_GMAC_LYR4_ADDR2_s
29656 {
29657  uint32_t l4sp2 : 16; /* Layer 4 Source Port Number Field */
29658  uint32_t l4dp2 : 16; /* Layer 4 Destination Port Number Field */
29659 };
29660 
29661 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR2. */
29662 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR2_s ALT_EMAC_GMAC_LYR4_ADDR2_t;
29663 #endif /* __ASSEMBLY__ */
29664 
29665 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR2 register from the beginning of the component. */
29666 #define ALT_EMAC_GMAC_LYR4_ADDR2_OFST 0x464
29667 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register. */
29668 #define ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR2_OFST))
29669 
29670 /*
29671  * Register : Register 284 (Layer 3 Address 0 Register 2) - Layer3_Addr0_Reg2
29672  *
29673  * For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source
29674  * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
29675  * Address or Destination Address field.
29676  *
29677  * Register Layout
29678  *
29679  * Bits | Access | Reset | Description
29680  * :-------|:-------|:------|:------------------------
29681  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
29682  *
29683  */
29684 /*
29685  * Field : Layer 3 Address 0 Field - l3a02
29686  *
29687  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
29688  * Layer 4 Control Register 2), this field contains the value to be matched with
29689  * Bits [31:0] of the IP Source Address field in the IPv6 frames.
29690  *
29691  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
29692  * Layer 4 Control Register 2), this field contains the value to be matched with
29693  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
29694  *
29695  * When Bit 0 (L3PEN2) is reset and Bit 2 (L3SAM2) is set in Register 280 (Layer 3
29696  * and Layer 4 Control Register 2), this field contains the value to be matched
29697  * with the IP Source Address field in the IPv4 frames.
29698  *
29699  * Field Access Macros:
29700  *
29701  */
29702 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
29703 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_LSB 0
29704 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
29705 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_MSB 31
29706 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
29707 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_WIDTH 32
29708 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
29709 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET_MSK 0xffffffff
29710 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
29711 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_CLR_MSK 0x00000000
29712 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
29713 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_RESET 0x0
29714 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 field value from a register. */
29715 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_GET(value) (((value) & 0xffffffff) >> 0)
29716 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value suitable for setting the register. */
29717 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET(value) (((value) << 0) & 0xffffffff)
29718 
29719 #ifndef __ASSEMBLY__
29720 /*
29721  * WARNING: The C register and register group struct declarations are provided for
29722  * convenience and illustrative purposes. They should, however, be used with
29723  * caution as the C language standard provides no guarantees about the alignment or
29724  * atomicity of device memory accesses. The recommended practice for writing
29725  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29726  * alt_write_word() functions.
29727  *
29728  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2.
29729  */
29730 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s
29731 {
29732  uint32_t l3a02 : 32; /* Layer 3 Address 0 Field */
29733 };
29734 
29735 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2. */
29736 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t;
29737 #endif /* __ASSEMBLY__ */
29738 
29739 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register from the beginning of the component. */
29740 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST 0x470
29741 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register. */
29742 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST))
29743 
29744 /*
29745  * Register : Register 285 (Layer 3 Address 1 Register 2) - Layer3_Addr1_Reg2
29746  *
29747  * For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP
29748  * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
29749  * 128-bit IP Source Address or Destination Address field.
29750  *
29751  * Register Layout
29752  *
29753  * Bits | Access | Reset | Description
29754  * :-------|:-------|:------|:------------------------
29755  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
29756  *
29757  */
29758 /*
29759  * Field : Layer 3 Address 1 Field - l3a12
29760  *
29761  * Layer 3 Address 1 Field
29762  *
29763  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
29764  * Layer 4 Control Register 2), this field contains the value to be matched with
29765  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
29766  *
29767  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
29768  * Layer 4 Control Register 2), this field contains the value to be matched with
29769  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
29770  *
29771  * When Bit 0 (L3PEN2) is reset and Bit 4 (L3DAM2) is set in Register 280 (Layer 3
29772  * and Layer 4 Control Register 2), this field contains the value to be matched
29773  * with the IP Destination Address field in the IPv4 frames.
29774  *
29775  * Field Access Macros:
29776  *
29777  */
29778 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
29779 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_LSB 0
29780 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
29781 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_MSB 31
29782 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
29783 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_WIDTH 32
29784 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
29785 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET_MSK 0xffffffff
29786 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
29787 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_CLR_MSK 0x00000000
29788 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
29789 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_RESET 0x0
29790 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 field value from a register. */
29791 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_GET(value) (((value) & 0xffffffff) >> 0)
29792 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value suitable for setting the register. */
29793 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET(value) (((value) << 0) & 0xffffffff)
29794 
29795 #ifndef __ASSEMBLY__
29796 /*
29797  * WARNING: The C register and register group struct declarations are provided for
29798  * convenience and illustrative purposes. They should, however, be used with
29799  * caution as the C language standard provides no guarantees about the alignment or
29800  * atomicity of device memory accesses. The recommended practice for writing
29801  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29802  * alt_write_word() functions.
29803  *
29804  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2.
29805  */
29806 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s
29807 {
29808  uint32_t l3a12 : 32; /* Layer 3 Address 1 Field */
29809 };
29810 
29811 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2. */
29812 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t;
29813 #endif /* __ASSEMBLY__ */
29814 
29815 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register from the beginning of the component. */
29816 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST 0x474
29817 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register. */
29818 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST))
29819 
29820 /*
29821  * Register : Register 286 (Layer 3 Address 2 Register 2) - Layer3_Addr2_Reg2
29822  *
29823  * For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames,
29824  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
29825  * field.
29826  *
29827  * Register Layout
29828  *
29829  * Bits | Access | Reset | Description
29830  * :-------|:-------|:------|:------------------------
29831  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
29832  *
29833  */
29834 /*
29835  * Field : Layer 3 Address 2 Field - l3a22
29836  *
29837  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
29838  * Layer 4 Control Register 2), this field contains the value to be matched with
29839  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
29840  *
29841  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and
29842  * Layer 4 Control Register 2), this field contains value to be matched with Bits
29843  * [95:64] of the IP Destination Address field in the IPv6 frames.
29844  *
29845  * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
29846  * Register 2), this register is not used.
29847  *
29848  * Field Access Macros:
29849  *
29850  */
29851 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
29852 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_LSB 0
29853 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
29854 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_MSB 31
29855 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
29856 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_WIDTH 32
29857 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
29858 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET_MSK 0xffffffff
29859 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
29860 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_CLR_MSK 0x00000000
29861 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
29862 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_RESET 0x0
29863 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 field value from a register. */
29864 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_GET(value) (((value) & 0xffffffff) >> 0)
29865 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value suitable for setting the register. */
29866 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET(value) (((value) << 0) & 0xffffffff)
29867 
29868 #ifndef __ASSEMBLY__
29869 /*
29870  * WARNING: The C register and register group struct declarations are provided for
29871  * convenience and illustrative purposes. They should, however, be used with
29872  * caution as the C language standard provides no guarantees about the alignment or
29873  * atomicity of device memory accesses. The recommended practice for writing
29874  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29875  * alt_write_word() functions.
29876  *
29877  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2.
29878  */
29879 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s
29880 {
29881  uint32_t l3a22 : 32; /* Layer 3 Address 2 Field */
29882 };
29883 
29884 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2. */
29885 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t;
29886 #endif /* __ASSEMBLY__ */
29887 
29888 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register from the beginning of the component. */
29889 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST 0x478
29890 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register. */
29891 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST))
29892 
29893 /*
29894  * Register : Register 287 (Layer 3 Address 3 Register 2) - Layer3_Addr3_Reg2
29895  *
29896  * For IPv4 frames, the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames,
29897  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
29898  * Address field.
29899  *
29900  * Register Layout
29901  *
29902  * Bits | Access | Reset | Description
29903  * :-------|:-------|:------|:------------------------
29904  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
29905  *
29906  */
29907 /*
29908  * Field : Layer 3 Address 3 Field - l3a32
29909  *
29910  * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
29911  * Layer 4 Control Register 2), this field contains the value to be matched with
29912  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
29913  *
29914  * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
29915  * Layer 4 Control Register 2), this field contains the value to be matched with
29916  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
29917  *
29918  * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
29919  * Register 2), this register is not used.
29920  *
29921  * Field Access Macros:
29922  *
29923  */
29924 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
29925 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_LSB 0
29926 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
29927 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_MSB 31
29928 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
29929 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_WIDTH 32
29930 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
29931 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET_MSK 0xffffffff
29932 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
29933 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_CLR_MSK 0x00000000
29934 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
29935 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_RESET 0x0
29936 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 field value from a register. */
29937 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_GET(value) (((value) & 0xffffffff) >> 0)
29938 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value suitable for setting the register. */
29939 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET(value) (((value) << 0) & 0xffffffff)
29940 
29941 #ifndef __ASSEMBLY__
29942 /*
29943  * WARNING: The C register and register group struct declarations are provided for
29944  * convenience and illustrative purposes. They should, however, be used with
29945  * caution as the C language standard provides no guarantees about the alignment or
29946  * atomicity of device memory accesses. The recommended practice for writing
29947  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
29948  * alt_write_word() functions.
29949  *
29950  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2.
29951  */
29952 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s
29953 {
29954  uint32_t l3a32 : 32; /* Layer 3 Address 3 Field */
29955 };
29956 
29957 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2. */
29958 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t;
29959 #endif /* __ASSEMBLY__ */
29960 
29961 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register from the beginning of the component. */
29962 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST 0x47c
29963 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register. */
29964 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST))
29965 
29966 /*
29967  * Register : Register 292 (Layer 3 and Layer 4 Control Register 3) - L3_L4_Control3
29968  *
29969  * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
29970  *
29971  * Register Layout
29972  *
29973  * Bits | Access | Reset | Description
29974  * :--------|:-------|:------|:----------------------------------------------
29975  * [0] | RW | 0x0 | Layer 3 Protocol Enable
29976  * [1] | ??? | 0x0 | *UNDEFINED*
29977  * [2] | RW | 0x0 | Layer 3 IP SA Match Enable
29978  * [3] | RW | 0x0 | Layer 3 IP SA Inverse Match Enable
29979  * [4] | RW | 0x0 | Layer 3 IP DA Match Enable
29980  * [5] | RW | 0x0 | Layer 3 IP DA Inverse Match Enable
29981  * [10:6] | RW | 0x0 | Layer 3 IP SA Higher Bits Match
29982  * [15:11] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3
29983  * [16] | RW | 0x0 | Layer 4 Protocol Enable
29984  * [17] | ??? | 0x0 | *UNDEFINED*
29985  * [18] | RW | 0x0 | Layer 4 Source Port Match Enable
29986  * [19] | RW | 0x0 | Layer 4 Source Port Inverse Match Enable
29987  * [20] | RW | 0x0 | Layer 4 Destination Port Match Enable
29988  * [21] | RW | 0x0 | Layer 4 Destination Port Inverse Match Enable
29989  * [31:22] | ??? | 0x0 | *UNDEFINED*
29990  *
29991  */
29992 /*
29993  * Field : Layer 3 Protocol Enable - l3pen3
29994  *
29995  * When set, this bit indicates that the Layer 3 IP Source or Destination Address
29996  * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
29997  * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
29998  * frames.
29999  *
30000  * The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high.
30001  *
30002  * Field Access Macros:
30003  *
30004  */
30005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
30006 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB 0
30007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
30008 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB 0
30009 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
30010 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH 1
30011 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
30012 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK 0x00000001
30013 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
30014 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK 0xfffffffe
30015 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
30016 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET 0x0
30017 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 field value from a register. */
30018 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET(value) (((value) & 0x00000001) >> 0)
30019 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value suitable for setting the register. */
30020 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET(value) (((value) << 0) & 0x00000001)
30021 
30022 /*
30023  * Field : Layer 3 IP SA Match Enable - l3sam3
30024  *
30025  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
30026  * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
30027  * for matching.
30028  *
30029  * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4
30030  * (L3DAM3) because either IPv6 SA or DA can be checked for filtering.
30031  *
30032  * Field Access Macros:
30033  *
30034  */
30035 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
30036 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB 2
30037 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
30038 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB 2
30039 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
30040 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH 1
30041 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
30042 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK 0x00000004
30043 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
30044 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK 0xfffffffb
30045 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
30046 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET 0x0
30047 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 field value from a register. */
30048 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET(value) (((value) & 0x00000004) >> 2)
30049 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value suitable for setting the register. */
30050 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET(value) (((value) << 2) & 0x00000004)
30051 
30052 /*
30053  * Field : Layer 3 IP SA Inverse Match Enable - l3saim3
30054  *
30055  * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
30056  * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
30057  * Address field is enabled for perfect matching.
30058  *
30059  * This bit is valid and applicable only when Bit 2 (L3SAM3) is set high.
30060  *
30061  * Field Access Macros:
30062  *
30063  */
30064 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
30065 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB 3
30066 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
30067 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB 3
30068 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
30069 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH 1
30070 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
30071 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK 0x00000008
30072 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
30073 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK 0xfffffff7
30074 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
30075 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET 0x0
30076 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 field value from a register. */
30077 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET(value) (((value) & 0x00000008) >> 3)
30078 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value suitable for setting the register. */
30079 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET(value) (((value) << 3) & 0x00000008)
30080 
30081 /*
30082  * Field : Layer 3 IP DA Match Enable - l3dam3
30083  *
30084  * When set, this bit indicates that Layer 3 IP Destination Address field is
30085  * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
30086  * Address field for matching.
30087  *
30088  * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2
30089  * (L3SAM3) because either IPv6 DA or SA can be checked for filtering.
30090  *
30091  * Field Access Macros:
30092  *
30093  */
30094 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
30095 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB 4
30096 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
30097 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB 4
30098 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
30099 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH 1
30100 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
30101 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK 0x00000010
30102 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
30103 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK 0xffffffef
30104 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
30105 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET 0x0
30106 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 field value from a register. */
30107 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET(value) (((value) & 0x00000010) >> 4)
30108 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value suitable for setting the register. */
30109 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET(value) (((value) << 4) & 0x00000010)
30110 
30111 /*
30112  * Field : Layer 3 IP DA Inverse Match Enable - l3daim3
30113  *
30114  * When set, this bit indicates that the Layer 3 IP Destination Address field is
30115  * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
30116  * Destination Address field is enabled for perfect matching.
30117  *
30118  * This bit is valid and applicable only when Bit 4 (L3DAM3) is set high.
30119  *
30120  * Field Access Macros:
30121  *
30122  */
30123 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
30124 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB 5
30125 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
30126 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB 5
30127 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
30128 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH 1
30129 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
30130 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK 0x00000020
30131 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
30132 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK 0xffffffdf
30133 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
30134 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET 0x0
30135 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 field value from a register. */
30136 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET(value) (((value) & 0x00000020) >> 5)
30137 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value suitable for setting the register. */
30138 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET(value) (((value) << 5) & 0x00000020)
30139 
30140 /*
30141  * Field : Layer 3 IP SA Higher Bits Match - l3hsbm3
30142  *
30143  * IPv4 Frames:
30144  *
30145  * This field contains the number of lower bits of IP Source Address that are
30146  * masked for matching in the IPv4 frames. The following list describes the values
30147  * of this field:
30148  *
30149  * * 0: No bits are masked.
30150  *
30151  * * 1: LSb[0] is masked.
30152  *
30153  * * 2: Two LSbs [1:0] are masked.
30154  *
30155  * * ...
30156  *
30157  * * 31: All bits except MSb are masked.
30158  *
30159  * IPv6 Frames:
30160  *
30161  * This field contains Bits [4:0] of the field that indicates the number of higher
30162  * bits of IP Source or Destination Address matched in the IPv6 frames.
30163  *
30164  * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
30165  *
30166  * Field Access Macros:
30167  *
30168  */
30169 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
30170 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB 6
30171 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
30172 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB 10
30173 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
30174 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH 5
30175 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
30176 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK 0x000007c0
30177 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
30178 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK 0xfffff83f
30179 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
30180 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET 0x0
30181 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 field value from a register. */
30182 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET(value) (((value) & 0x000007c0) >> 6)
30183 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value suitable for setting the register. */
30184 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET(value) (((value) << 6) & 0x000007c0)
30185 
30186 /*
30187  * Field : l3hdbm3
30188  *
30189  * Layer 3 IP DA Higher Bits Match
30190  *
30191  * IPv4 Frames:
30192  *
30193  * This field contains the number of higher bits of IP Destination Address that are
30194  * matched in the IPv4 frames. The following list describes the values of this
30195  * field:
30196  *
30197  * * 0: No bits are masked.
30198  *
30199  * * 1: LSb[0] is masked.
30200  *
30201  * * 2: Two LSbs [1:0] are masked.
30202  *
30203  * * ...
30204  *
30205  * * 31: All bits except MSb are masked.
30206  *
30207  * IPv6 Frames:
30208  *
30209  * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate
30210  * the number of lower bits of IP Source or Destination Address that are masked in
30211  * the IPv6 frames. The following list describes the concatenated values of the
30212  * L3HDBM3[1:0] and L3HSBM3 bits:
30213  *
30214  * * 0: No bits are masked.
30215  *
30216  * * 1: LSb[0] is masked.
30217  *
30218  * * 2: Two LSbs [1:0] are masked.
30219  *
30220  * * ...
30221  *
30222  * * 127: All bits except MSb are masked.
30223  *
30224  * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
30225  *
30226  * Field Access Macros:
30227  *
30228  */
30229 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
30230 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB 11
30231 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
30232 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB 15
30233 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
30234 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH 5
30235 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
30236 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK 0x0000f800
30237 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
30238 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK 0xffff07ff
30239 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
30240 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET 0x0
30241 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 field value from a register. */
30242 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET(value) (((value) & 0x0000f800) >> 11)
30243 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value suitable for setting the register. */
30244 #define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET(value) (((value) << 11) & 0x0000f800)
30245 
30246 /*
30247  * Field : Layer 4 Protocol Enable - l4pen3
30248  *
30249  * When set, this bit indicates that the Source and Destination Port number fields
30250  * for UDP frames are used for matching. When reset, this bit indicates that the
30251  * Source and Destination Port number fields for TCP frames are used for matching.
30252  *
30253  * The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high.
30254  *
30255  * Field Access Macros:
30256  *
30257  */
30258 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
30259 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB 16
30260 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
30261 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB 16
30262 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
30263 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH 1
30264 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
30265 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK 0x00010000
30266 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
30267 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK 0xfffeffff
30268 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
30269 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET 0x0
30270 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 field value from a register. */
30271 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET(value) (((value) & 0x00010000) >> 16)
30272 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value suitable for setting the register. */
30273 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET(value) (((value) << 16) & 0x00010000)
30274 
30275 /*
30276  * Field : Layer 4 Source Port Match Enable - l4spm3
30277  *
30278  * When set, this bit indicates that the Layer 4 Source Port number field is
30279  * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
30280  * field for matching.
30281  *
30282  * Field Access Macros:
30283  *
30284  */
30285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
30286 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB 18
30287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
30288 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB 18
30289 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
30290 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH 1
30291 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
30292 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK 0x00040000
30293 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
30294 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK 0xfffbffff
30295 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
30296 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET 0x0
30297 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 field value from a register. */
30298 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET(value) (((value) & 0x00040000) >> 18)
30299 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value suitable for setting the register. */
30300 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET(value) (((value) << 18) & 0x00040000)
30301 
30302 /*
30303  * Field : Layer 4 Source Port Inverse Match Enable - l4spim3
30304  *
30305  * When set, this bit indicates that the Layer 4 Source Port number field is
30306  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
30307  * Source Port number field is enabled for perfect matching.
30308  *
30309  * This bit is valid and applicable only when Bit 18 (L4SPM3) is set high.
30310  *
30311  * Field Access Macros:
30312  *
30313  */
30314 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
30315 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB 19
30316 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
30317 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB 19
30318 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
30319 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH 1
30320 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
30321 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK 0x00080000
30322 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
30323 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK 0xfff7ffff
30324 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
30325 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET 0x0
30326 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 field value from a register. */
30327 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET(value) (((value) & 0x00080000) >> 19)
30328 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value suitable for setting the register. */
30329 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET(value) (((value) << 19) & 0x00080000)
30330 
30331 /*
30332  * Field : Layer 4 Destination Port Match Enable - l4dpm3
30333  *
30334  * When set, this bit indicates that the Layer 4 Destination Port number field is
30335  * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
30336  * number field for matching.
30337  *
30338  * Field Access Macros:
30339  *
30340  */
30341 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
30342 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB 20
30343 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
30344 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB 20
30345 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
30346 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH 1
30347 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
30348 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK 0x00100000
30349 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
30350 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK 0xffefffff
30351 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
30352 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET 0x0
30353 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 field value from a register. */
30354 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET(value) (((value) & 0x00100000) >> 20)
30355 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value suitable for setting the register. */
30356 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET(value) (((value) << 20) & 0x00100000)
30357 
30358 /*
30359  * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim3
30360  *
30361  * When set, this bit indicates that the Layer 4 Destination Port number field is
30362  * enabled for inverse matching. When reset, this bit indicates that the Layer 4
30363  * Destination Port number field is enabled for perfect matching.
30364  *
30365  * This bit is valid and applicable only when Bit 20 (L4DPM3) is set high.
30366  *
30367  * Field Access Macros:
30368  *
30369  */
30370 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
30371 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB 21
30372 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
30373 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB 21
30374 /* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
30375 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH 1
30376 /* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
30377 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK 0x00200000
30378 /* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
30379 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK 0xffdfffff
30380 /* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
30381 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET 0x0
30382 /* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 field value from a register. */
30383 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET(value) (((value) & 0x00200000) >> 21)
30384 /* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value suitable for setting the register. */
30385 #define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET(value) (((value) << 21) & 0x00200000)
30386 
30387 #ifndef __ASSEMBLY__
30388 /*
30389  * WARNING: The C register and register group struct declarations are provided for
30390  * convenience and illustrative purposes. They should, however, be used with
30391  * caution as the C language standard provides no guarantees about the alignment or
30392  * atomicity of device memory accesses. The recommended practice for writing
30393  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30394  * alt_write_word() functions.
30395  *
30396  * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL3.
30397  */
30398 struct ALT_EMAC_GMAC_L3_L4_CTL3_s
30399 {
30400  uint32_t l3pen3 : 1; /* Layer 3 Protocol Enable */
30401  uint32_t : 1; /* *UNDEFINED* */
30402  uint32_t l3sam3 : 1; /* Layer 3 IP SA Match Enable */
30403  uint32_t l3saim3 : 1; /* Layer 3 IP SA Inverse Match Enable */
30404  uint32_t l3dam3 : 1; /* Layer 3 IP DA Match Enable */
30405  uint32_t l3daim3 : 1; /* Layer 3 IP DA Inverse Match Enable */
30406  uint32_t l3hsbm3 : 5; /* Layer 3 IP SA Higher Bits Match */
30407  uint32_t l3hdbm3 : 5; /* ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 */
30408  uint32_t l4pen3 : 1; /* Layer 4 Protocol Enable */
30409  uint32_t : 1; /* *UNDEFINED* */
30410  uint32_t l4spm3 : 1; /* Layer 4 Source Port Match Enable */
30411  uint32_t l4spim3 : 1; /* Layer 4 Source Port Inverse Match Enable */
30412  uint32_t l4dpm3 : 1; /* Layer 4 Destination Port Match Enable */
30413  uint32_t l4dpim3 : 1; /* Layer 4 Destination Port Inverse Match Enable */
30414  uint32_t : 10; /* *UNDEFINED* */
30415 };
30416 
30417 /* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL3. */
30418 typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL3_s ALT_EMAC_GMAC_L3_L4_CTL3_t;
30419 #endif /* __ASSEMBLY__ */
30420 
30421 /* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL3 register from the beginning of the component. */
30422 #define ALT_EMAC_GMAC_L3_L4_CTL3_OFST 0x490
30423 /* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register. */
30424 #define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST))
30425 
30426 /*
30427  * Register : Register 293 (Layer 4 Address Register 3) - Layer4_Address3
30428  *
30429  * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
30430  * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
30431  * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
30432  * Layer 4 Address Registers are written. For proper synchronization updates, you
30433  * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
30434  * Registers after at least four clock cycles delay of the destination clock.
30435  *
30436  * Register Layout
30437  *
30438  * Bits | Access | Reset | Description
30439  * :--------|:-------|:------|:--------------------------------------
30440  * [15:0] | RW | 0x0 | Layer 4 Source Port Number Field
30441  * [31:16] | RW | 0x0 | Layer 4 Destination Port Number Field
30442  *
30443  */
30444 /*
30445  * Field : Layer 4 Source Port Number Field - l4sp3
30446  *
30447  * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
30448  * 3 and Layer 4 Control Register 3), this field contains the value to be matched
30449  * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
30450  *
30451  * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
30452  * Layer 4 Control Register 3), this field contains the value to be matched with
30453  * the UDP Source Port Number field in the IPv4 or IPv6 frames.
30454  *
30455  * Field Access Macros:
30456  *
30457  */
30458 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
30459 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_LSB 0
30460 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
30461 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_MSB 15
30462 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
30463 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_WIDTH 16
30464 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
30465 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET_MSK 0x0000ffff
30466 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
30467 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_CLR_MSK 0xffff0000
30468 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
30469 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_RESET 0x0
30470 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 field value from a register. */
30471 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_GET(value) (((value) & 0x0000ffff) >> 0)
30472 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value suitable for setting the register. */
30473 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET(value) (((value) << 0) & 0x0000ffff)
30474 
30475 /*
30476  * Field : Layer 4 Destination Port Number Field - l4dp3
30477  *
30478  * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
30479  * 3 and Layer 4 Control Register 3), this field contains the value to be matched
30480  * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
30481  *
30482  * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
30483  * Layer 4 Control Register 3), this field contains the value to be matched with
30484  * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
30485  *
30486  * Field Access Macros:
30487  *
30488  */
30489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
30490 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_LSB 16
30491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
30492 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_MSB 31
30493 /* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
30494 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_WIDTH 16
30495 /* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
30496 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET_MSK 0xffff0000
30497 /* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
30498 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_CLR_MSK 0x0000ffff
30499 /* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
30500 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_RESET 0x0
30501 /* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 field value from a register. */
30502 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_GET(value) (((value) & 0xffff0000) >> 16)
30503 /* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value suitable for setting the register. */
30504 #define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET(value) (((value) << 16) & 0xffff0000)
30505 
30506 #ifndef __ASSEMBLY__
30507 /*
30508  * WARNING: The C register and register group struct declarations are provided for
30509  * convenience and illustrative purposes. They should, however, be used with
30510  * caution as the C language standard provides no guarantees about the alignment or
30511  * atomicity of device memory accesses. The recommended practice for writing
30512  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30513  * alt_write_word() functions.
30514  *
30515  * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR3.
30516  */
30517 struct ALT_EMAC_GMAC_LYR4_ADDR3_s
30518 {
30519  uint32_t l4sp3 : 16; /* Layer 4 Source Port Number Field */
30520  uint32_t l4dp3 : 16; /* Layer 4 Destination Port Number Field */
30521 };
30522 
30523 /* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR3. */
30524 typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR3_s ALT_EMAC_GMAC_LYR4_ADDR3_t;
30525 #endif /* __ASSEMBLY__ */
30526 
30527 /* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR3 register from the beginning of the component. */
30528 #define ALT_EMAC_GMAC_LYR4_ADDR3_OFST 0x494
30529 /* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register. */
30530 #define ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR3_OFST))
30531 
30532 /*
30533  * Register : Register 296 (Layer 3 Address 0 Register 3) - Layer3_Addr0_Reg3
30534  *
30535  * For IPv4 frames, the Layer 3 Address 0 Register 3 contains the 32-bit IP Source
30536  * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
30537  * Address or Destination Address field.
30538  *
30539  * Register Layout
30540  *
30541  * Bits | Access | Reset | Description
30542  * :-------|:-------|:------|:------------------------
30543  * [31:0] | RW | 0x0 | Layer 3 Address 0 Field
30544  *
30545  */
30546 /*
30547  * Field : Layer 3 Address 0 Field - l3a03
30548  *
30549  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
30550  * Layer 4 Control Register 3), this field contains the value to be matched with
30551  * Bits [31:0] of the IP Source Address field in the IPv6 frames.
30552  *
30553  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
30554  * Layer 4 Control Register 3), this field contains the value to be matched with
30555  * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
30556  *
30557  * When Bit 0 (L3PEN3) is reset and Bit 2 (L3SAM3) is set in Register 292 (Layer 3
30558  * and Layer 4 Control Register 3), this field contains the value to be matched
30559  * with the IP Source Address field in the IPv4 frames.
30560  *
30561  * Field Access Macros:
30562  *
30563  */
30564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
30565 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_LSB 0
30566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
30567 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_MSB 31
30568 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
30569 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_WIDTH 32
30570 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
30571 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET_MSK 0xffffffff
30572 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
30573 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_CLR_MSK 0x00000000
30574 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
30575 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_RESET 0x0
30576 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 field value from a register. */
30577 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_GET(value) (((value) & 0xffffffff) >> 0)
30578 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value suitable for setting the register. */
30579 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET(value) (((value) << 0) & 0xffffffff)
30580 
30581 #ifndef __ASSEMBLY__
30582 /*
30583  * WARNING: The C register and register group struct declarations are provided for
30584  * convenience and illustrative purposes. They should, however, be used with
30585  * caution as the C language standard provides no guarantees about the alignment or
30586  * atomicity of device memory accesses. The recommended practice for writing
30587  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30588  * alt_write_word() functions.
30589  *
30590  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3.
30591  */
30592 struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s
30593 {
30594  uint32_t l3a03 : 32; /* Layer 3 Address 0 Field */
30595 };
30596 
30597 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3. */
30598 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t;
30599 #endif /* __ASSEMBLY__ */
30600 
30601 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register from the beginning of the component. */
30602 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST 0x4a0
30603 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register. */
30604 #define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST))
30605 
30606 /*
30607  * Register : Register 297 (Layer 3 Address 1 Register 3) - Layer3_Addr1_Reg3
30608  *
30609  * For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP
30610  * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
30611  * 128-bit IP Source Address or Destination Address field.
30612  *
30613  * Register Layout
30614  *
30615  * Bits | Access | Reset | Description
30616  * :-------|:-------|:------|:------------------------
30617  * [31:0] | RW | 0x0 | Layer 3 Address 1 Field
30618  *
30619  */
30620 /*
30621  * Field : Layer 3 Address 1 Field - l3a13
30622  *
30623  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
30624  * Layer 4 Control Register 3), this field contains the value to be matched with
30625  * Bits [63:32] of the IP Source Address field in the IPv6 frames.
30626  *
30627  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
30628  * Layer 4 Control Register 3), this field contains the value to be matched with
30629  * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
30630  *
30631  * When Bit 0 (L3PEN3) is reset and Bit 4 (L3DAM3) is set in Register 292 (Layer 3
30632  * and Layer 4 Control Register 3), this field contains the value to be matched
30633  * with the IP Destination Address field in the IPv4 frames.
30634  *
30635  * Field Access Macros:
30636  *
30637  */
30638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
30639 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_LSB 0
30640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
30641 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_MSB 31
30642 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
30643 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_WIDTH 32
30644 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
30645 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET_MSK 0xffffffff
30646 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
30647 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_CLR_MSK 0x00000000
30648 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
30649 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_RESET 0x0
30650 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 field value from a register. */
30651 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_GET(value) (((value) & 0xffffffff) >> 0)
30652 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value suitable for setting the register. */
30653 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET(value) (((value) << 0) & 0xffffffff)
30654 
30655 #ifndef __ASSEMBLY__
30656 /*
30657  * WARNING: The C register and register group struct declarations are provided for
30658  * convenience and illustrative purposes. They should, however, be used with
30659  * caution as the C language standard provides no guarantees about the alignment or
30660  * atomicity of device memory accesses. The recommended practice for writing
30661  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30662  * alt_write_word() functions.
30663  *
30664  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3.
30665  */
30666 struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s
30667 {
30668  uint32_t l3a13 : 32; /* Layer 3 Address 1 Field */
30669 };
30670 
30671 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3. */
30672 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t;
30673 #endif /* __ASSEMBLY__ */
30674 
30675 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register from the beginning of the component. */
30676 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST 0x4a4
30677 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register. */
30678 #define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST))
30679 
30680 /*
30681  * Register : Register 298 (Layer 3 Address 2 Register 3) - Layer3_Addr2_Reg3
30682  *
30683  * For IPv4 frames, the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames,
30684  * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
30685  * field.
30686  *
30687  * Register Layout
30688  *
30689  * Bits | Access | Reset | Description
30690  * :-------|:-------|:------|:------------------------
30691  * [31:0] | RW | 0x0 | Layer 3 Address 2 Field
30692  *
30693  */
30694 /*
30695  * Field : Layer 3 Address 2 Field - l3a23
30696  *
30697  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
30698  * Layer 4 Control Register 3), this field contains the value to be matched with
30699  * Bits [95:64] of the IP Source Address field in the IPv6 frames.
30700  *
30701  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
30702  * Layer 4 Control Register 3), this field contains value to be matched with Bits
30703  * [95:64] of the IP Destination Address field in the IPv6 frames.
30704  *
30705  * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
30706  * Register 3), this register is not used.
30707  *
30708  * Field Access Macros:
30709  *
30710  */
30711 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
30712 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_LSB 0
30713 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
30714 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_MSB 31
30715 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
30716 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_WIDTH 32
30717 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
30718 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET_MSK 0xffffffff
30719 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
30720 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_CLR_MSK 0x00000000
30721 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
30722 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_RESET 0x0
30723 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 field value from a register. */
30724 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_GET(value) (((value) & 0xffffffff) >> 0)
30725 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value suitable for setting the register. */
30726 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET(value) (((value) << 0) & 0xffffffff)
30727 
30728 #ifndef __ASSEMBLY__
30729 /*
30730  * WARNING: The C register and register group struct declarations are provided for
30731  * convenience and illustrative purposes. They should, however, be used with
30732  * caution as the C language standard provides no guarantees about the alignment or
30733  * atomicity of device memory accesses. The recommended practice for writing
30734  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30735  * alt_write_word() functions.
30736  *
30737  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3.
30738  */
30739 struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s
30740 {
30741  uint32_t l3a23 : 32; /* Layer 3 Address 2 Field */
30742 };
30743 
30744 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3. */
30745 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t;
30746 #endif /* __ASSEMBLY__ */
30747 
30748 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register from the beginning of the component. */
30749 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST 0x4a8
30750 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register. */
30751 #define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST))
30752 
30753 /*
30754  * Register : Register 299 (Layer 3 Address 3 Register 3) - Layer3_Addr3_Reg3
30755  *
30756  * For IPv4 frames, the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames,
30757  * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
30758  * Address field.
30759  *
30760  * Register Layout
30761  *
30762  * Bits | Access | Reset | Description
30763  * :-------|:-------|:------|:------------------------
30764  * [31:0] | RW | 0x0 | Layer 3 Address 3 Field
30765  *
30766  */
30767 /*
30768  * Field : Layer 3 Address 3 Field - l3a33
30769  *
30770  * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
30771  * Layer 4 Control Register 3), this field contains the value to be matched with
30772  * Bits [127:96] of the IP Source Address field in the IPv6 frames.
30773  *
30774  * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
30775  * Layer 4 Control Register 3), this field contains the value to be matched with
30776  * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
30777  *
30778  * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
30779  * Register 3), this register is not used.
30780  *
30781  * Field Access Macros:
30782  *
30783  */
30784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
30785 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_LSB 0
30786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
30787 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_MSB 31
30788 /* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
30789 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_WIDTH 32
30790 /* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
30791 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET_MSK 0xffffffff
30792 /* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
30793 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_CLR_MSK 0x00000000
30794 /* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
30795 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_RESET 0x0
30796 /* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 field value from a register. */
30797 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_GET(value) (((value) & 0xffffffff) >> 0)
30798 /* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value suitable for setting the register. */
30799 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET(value) (((value) << 0) & 0xffffffff)
30800 
30801 #ifndef __ASSEMBLY__
30802 /*
30803  * WARNING: The C register and register group struct declarations are provided for
30804  * convenience and illustrative purposes. They should, however, be used with
30805  * caution as the C language standard provides no guarantees about the alignment or
30806  * atomicity of device memory accesses. The recommended practice for writing
30807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30808  * alt_write_word() functions.
30809  *
30810  * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3.
30811  */
30812 struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s
30813 {
30814  uint32_t l3a33 : 32; /* Layer 3 Address 3 Field */
30815 };
30816 
30817 /* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3. */
30818 typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t;
30819 #endif /* __ASSEMBLY__ */
30820 
30821 /* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register from the beginning of the component. */
30822 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST 0x4ac
30823 /* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register. */
30824 #define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST))
30825 
30826 /*
30827  * Register : Register 320 (Hash Table Register 0) - Hash_Table_Reg0
30828  *
30829  * This register contains the first 32 bits of the hash table.
30830  *
30831  * The 256-bit Hash table is used for group address filtering. For hash filtering,
30832  * the content of the destination address in the incoming frame is passed through
30833  * the CRC logic and the upper eight bits of the CRC register are used to index the
30834  * content of the Hash table. The most significant bits determines the register to
30835  * be used (Hash Table Register X), and the least significant five bits determine
30836  * the bit within the register. For example, a hash value of 8b'10111111 selects
30837  * Bit 31 of the Hash Table Register 5.
30838  *
30839  * The hash value of the destination address is calculated in the following way:
30840  *
30841  * 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the
30842  * steps to calculate CRC32).
30843  *
30844  * 2. Perform bitwise reversal for the value obtained in Step 1.
30845  *
30846  * 3. Take the upper 8 bits from the value obtained in Step 2.
30847  *
30848  * If the corresponding bit value of the register is 1'b1, the frame is accepted.
30849  * Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register
30850  * 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the
30851  * multicast hash values.
30852  *
30853  * Because the Hash Table register is double-synchronized to the (G)MII clock
30854  * domain, the synchronization is triggered only when Bits[31:24] (in little-endian
30855  * mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers
30856  * are written.
30857  *
30858  * Note: Because of double-synchronization, consecutive writes to this register
30859  * should be performed after at least four clock cycles in the destination clock
30860  * domain.
30861  *
30862  * Register Layout
30863  *
30864  * Bits | Access | Reset | Description
30865  * :-------|:-------|:------|:----------------------------
30866  * [31:0] | RW | 0x0 | First 32 bits of Hash Table
30867  *
30868  */
30869 /*
30870  * Field : First 32 bits of Hash Table - ht31t0
30871  *
30872  * This field contains the first 32 Bits (31:0) of the Hash table.
30873  *
30874  * Field Access Macros:
30875  *
30876  */
30877 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
30878 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB 0
30879 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
30880 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB 31
30881 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
30882 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH 32
30883 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
30884 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK 0xffffffff
30885 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
30886 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK 0x00000000
30887 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
30888 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET 0x0
30889 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 field value from a register. */
30890 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET(value) (((value) & 0xffffffff) >> 0)
30891 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value suitable for setting the register. */
30892 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET(value) (((value) << 0) & 0xffffffff)
30893 
30894 #ifndef __ASSEMBLY__
30895 /*
30896  * WARNING: The C register and register group struct declarations are provided for
30897  * convenience and illustrative purposes. They should, however, be used with
30898  * caution as the C language standard provides no guarantees about the alignment or
30899  * atomicity of device memory accesses. The recommended practice for writing
30900  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30901  * alt_write_word() functions.
30902  *
30903  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0.
30904  */
30905 struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s
30906 {
30907  uint32_t ht31t0 : 32; /* First 32 bits of Hash Table */
30908 };
30909 
30910 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0. */
30911 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s ALT_EMAC_GMAC_HASH_TABLE_REG0_t;
30912 #endif /* __ASSEMBLY__ */
30913 
30914 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register from the beginning of the component. */
30915 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST 0x500
30916 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register. */
30917 #define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST))
30918 
30919 /*
30920  * Register : Register 321 (Hash Table Register 1) - Hash_Table_Reg1
30921  *
30922  * This register contains the second 32 bits of the hash table.
30923  *
30924  * Register Layout
30925  *
30926  * Bits | Access | Reset | Description
30927  * :-------|:-------|:------|:-----------------------------
30928  * [31:0] | RW | 0x0 | Second 32 bits of Hash Table
30929  *
30930  */
30931 /*
30932  * Field : Second 32 bits of Hash Table - ht63t32
30933  *
30934  * This field contains the second 32 Bits (63:32) of the Hash table.
30935  *
30936  * Field Access Macros:
30937  *
30938  */
30939 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
30940 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_LSB 0
30941 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
30942 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_MSB 31
30943 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
30944 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_WIDTH 32
30945 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
30946 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET_MSK 0xffffffff
30947 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
30948 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_CLR_MSK 0x00000000
30949 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
30950 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_RESET 0x0
30951 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 field value from a register. */
30952 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_GET(value) (((value) & 0xffffffff) >> 0)
30953 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value suitable for setting the register. */
30954 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET(value) (((value) << 0) & 0xffffffff)
30955 
30956 #ifndef __ASSEMBLY__
30957 /*
30958  * WARNING: The C register and register group struct declarations are provided for
30959  * convenience and illustrative purposes. They should, however, be used with
30960  * caution as the C language standard provides no guarantees about the alignment or
30961  * atomicity of device memory accesses. The recommended practice for writing
30962  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
30963  * alt_write_word() functions.
30964  *
30965  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1.
30966  */
30967 struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s
30968 {
30969  uint32_t ht63t32 : 32; /* Second 32 bits of Hash Table */
30970 };
30971 
30972 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1. */
30973 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s ALT_EMAC_GMAC_HASH_TABLE_REG1_t;
30974 #endif /* __ASSEMBLY__ */
30975 
30976 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register from the beginning of the component. */
30977 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST 0x504
30978 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register. */
30979 #define ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST))
30980 
30981 /*
30982  * Register : Register 322 (Hash Table Register 2) - Hash_Table_Reg2
30983  *
30984  * This register contains the third 32 bits of the hash table.
30985  *
30986  * Register Layout
30987  *
30988  * Bits | Access | Reset | Description
30989  * :-------|:-------|:------|:----------------------------
30990  * [31:0] | RW | 0x0 | Third 32 bits of Hash Table
30991  *
30992  */
30993 /*
30994  * Field : Third 32 bits of Hash Table - ht95t64
30995  *
30996  * This field contains the third 32 Bits (95:64) of the Hash table.
30997  *
30998  * Field Access Macros:
30999  *
31000  */
31001 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
31002 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_LSB 0
31003 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
31004 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_MSB 31
31005 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
31006 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_WIDTH 32
31007 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
31008 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET_MSK 0xffffffff
31009 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
31010 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_CLR_MSK 0x00000000
31011 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
31012 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_RESET 0x0
31013 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 field value from a register. */
31014 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_GET(value) (((value) & 0xffffffff) >> 0)
31015 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value suitable for setting the register. */
31016 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET(value) (((value) << 0) & 0xffffffff)
31017 
31018 #ifndef __ASSEMBLY__
31019 /*
31020  * WARNING: The C register and register group struct declarations are provided for
31021  * convenience and illustrative purposes. They should, however, be used with
31022  * caution as the C language standard provides no guarantees about the alignment or
31023  * atomicity of device memory accesses. The recommended practice for writing
31024  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31025  * alt_write_word() functions.
31026  *
31027  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2.
31028  */
31029 struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s
31030 {
31031  uint32_t ht95t64 : 32; /* Third 32 bits of Hash Table */
31032 };
31033 
31034 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2. */
31035 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s ALT_EMAC_GMAC_HASH_TABLE_REG2_t;
31036 #endif /* __ASSEMBLY__ */
31037 
31038 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register from the beginning of the component. */
31039 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST 0x508
31040 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register. */
31041 #define ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST))
31042 
31043 /*
31044  * Register : Register 323 (Hash Table Register 3) - Hash_Table_Reg3
31045  *
31046  * This register contains the fourth 32 bits of the hash table.
31047  *
31048  * Register Layout
31049  *
31050  * Bits | Access | Reset | Description
31051  * :-------|:-------|:------|:-----------------------------
31052  * [31:0] | RW | 0x0 | Fourth 32 bits of Hash Table
31053  *
31054  */
31055 /*
31056  * Field : Fourth 32 bits of Hash Table - ht127t96
31057  *
31058  * This field contains the fourth 32 Bits (127:96) of the Hash table.
31059  *
31060  * Field Access Macros:
31061  *
31062  */
31063 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
31064 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_LSB 0
31065 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
31066 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_MSB 31
31067 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
31068 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_WIDTH 32
31069 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
31070 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET_MSK 0xffffffff
31071 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
31072 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_CLR_MSK 0x00000000
31073 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
31074 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_RESET 0x0
31075 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 field value from a register. */
31076 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_GET(value) (((value) & 0xffffffff) >> 0)
31077 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value suitable for setting the register. */
31078 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET(value) (((value) << 0) & 0xffffffff)
31079 
31080 #ifndef __ASSEMBLY__
31081 /*
31082  * WARNING: The C register and register group struct declarations are provided for
31083  * convenience and illustrative purposes. They should, however, be used with
31084  * caution as the C language standard provides no guarantees about the alignment or
31085  * atomicity of device memory accesses. The recommended practice for writing
31086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31087  * alt_write_word() functions.
31088  *
31089  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3.
31090  */
31091 struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s
31092 {
31093  uint32_t ht127t96 : 32; /* Fourth 32 bits of Hash Table */
31094 };
31095 
31096 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3. */
31097 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s ALT_EMAC_GMAC_HASH_TABLE_REG3_t;
31098 #endif /* __ASSEMBLY__ */
31099 
31100 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register from the beginning of the component. */
31101 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST 0x50c
31102 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register. */
31103 #define ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST))
31104 
31105 /*
31106  * Register : Register 324 (Hash Table Register 4) - Hash_Table_Reg4
31107  *
31108  * This register contains the fifth 32 bits of the hash table.
31109  *
31110  * Register Layout
31111  *
31112  * Bits | Access | Reset | Description
31113  * :-------|:-------|:------|:----------------------------
31114  * [31:0] | RW | 0x0 | Fifth 32 bits of Hash Table
31115  *
31116  */
31117 /*
31118  * Field : Fifth 32 bits of Hash Table - ht159t128
31119  *
31120  * This field contains the fifth 32 Bits (159:128) of the Hash table.
31121  *
31122  * Field Access Macros:
31123  *
31124  */
31125 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
31126 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_LSB 0
31127 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
31128 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_MSB 31
31129 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
31130 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_WIDTH 32
31131 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
31132 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET_MSK 0xffffffff
31133 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
31134 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_CLR_MSK 0x00000000
31135 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
31136 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_RESET 0x0
31137 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 field value from a register. */
31138 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_GET(value) (((value) & 0xffffffff) >> 0)
31139 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value suitable for setting the register. */
31140 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET(value) (((value) << 0) & 0xffffffff)
31141 
31142 #ifndef __ASSEMBLY__
31143 /*
31144  * WARNING: The C register and register group struct declarations are provided for
31145  * convenience and illustrative purposes. They should, however, be used with
31146  * caution as the C language standard provides no guarantees about the alignment or
31147  * atomicity of device memory accesses. The recommended practice for writing
31148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31149  * alt_write_word() functions.
31150  *
31151  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4.
31152  */
31153 struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s
31154 {
31155  uint32_t ht159t128 : 32; /* Fifth 32 bits of Hash Table */
31156 };
31157 
31158 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4. */
31159 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s ALT_EMAC_GMAC_HASH_TABLE_REG4_t;
31160 #endif /* __ASSEMBLY__ */
31161 
31162 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register from the beginning of the component. */
31163 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST 0x510
31164 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register. */
31165 #define ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST))
31166 
31167 /*
31168  * Register : Register 325 (Hash Table Register 5) - Hash_Table_Reg5
31169  *
31170  * This register contains the sixth 32 bits of the hash table.
31171  *
31172  * Register Layout
31173  *
31174  * Bits | Access | Reset | Description
31175  * :-------|:-------|:------|:----------------------------
31176  * [31:0] | RW | 0x0 | Sixth 32 bits of Hash Table
31177  *
31178  */
31179 /*
31180  * Field : Sixth 32 bits of Hash Table - ht191t160
31181  *
31182  * This field contains the sixth 32 Bits (191:160) of the Hash table.
31183  *
31184  * Field Access Macros:
31185  *
31186  */
31187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
31188 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_LSB 0
31189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
31190 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_MSB 31
31191 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
31192 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_WIDTH 32
31193 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
31194 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET_MSK 0xffffffff
31195 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
31196 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_CLR_MSK 0x00000000
31197 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
31198 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_RESET 0x0
31199 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 field value from a register. */
31200 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_GET(value) (((value) & 0xffffffff) >> 0)
31201 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value suitable for setting the register. */
31202 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET(value) (((value) << 0) & 0xffffffff)
31203 
31204 #ifndef __ASSEMBLY__
31205 /*
31206  * WARNING: The C register and register group struct declarations are provided for
31207  * convenience and illustrative purposes. They should, however, be used with
31208  * caution as the C language standard provides no guarantees about the alignment or
31209  * atomicity of device memory accesses. The recommended practice for writing
31210  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31211  * alt_write_word() functions.
31212  *
31213  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5.
31214  */
31215 struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s
31216 {
31217  uint32_t ht191t160 : 32; /* Sixth 32 bits of Hash Table */
31218 };
31219 
31220 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5. */
31221 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s ALT_EMAC_GMAC_HASH_TABLE_REG5_t;
31222 #endif /* __ASSEMBLY__ */
31223 
31224 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register from the beginning of the component. */
31225 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST 0x514
31226 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register. */
31227 #define ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST))
31228 
31229 /*
31230  * Register : Register 326 (Hash Table Register 6) - Hash_Table_Reg6
31231  *
31232  * This register contains the seventh 32 bits of the hash table.
31233  *
31234  * Register Layout
31235  *
31236  * Bits | Access | Reset | Description
31237  * :-------|:-------|:------|:------------------------------
31238  * [31:0] | RW | 0x0 | Seventh 32 bits of Hash Table
31239  *
31240  */
31241 /*
31242  * Field : Seventh 32 bits of Hash Table - ht223t196
31243  *
31244  * This field contains the seventh 32 Bits (223:196) of the Hash table.
31245  *
31246  * Field Access Macros:
31247  *
31248  */
31249 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
31250 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_LSB 0
31251 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
31252 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_MSB 31
31253 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
31254 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_WIDTH 32
31255 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
31256 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET_MSK 0xffffffff
31257 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
31258 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_CLR_MSK 0x00000000
31259 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
31260 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_RESET 0x0
31261 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 field value from a register. */
31262 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_GET(value) (((value) & 0xffffffff) >> 0)
31263 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value suitable for setting the register. */
31264 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET(value) (((value) << 0) & 0xffffffff)
31265 
31266 #ifndef __ASSEMBLY__
31267 /*
31268  * WARNING: The C register and register group struct declarations are provided for
31269  * convenience and illustrative purposes. They should, however, be used with
31270  * caution as the C language standard provides no guarantees about the alignment or
31271  * atomicity of device memory accesses. The recommended practice for writing
31272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31273  * alt_write_word() functions.
31274  *
31275  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6.
31276  */
31277 struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s
31278 {
31279  uint32_t ht223t196 : 32; /* Seventh 32 bits of Hash Table */
31280 };
31281 
31282 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6. */
31283 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s ALT_EMAC_GMAC_HASH_TABLE_REG6_t;
31284 #endif /* __ASSEMBLY__ */
31285 
31286 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register from the beginning of the component. */
31287 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST 0x518
31288 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register. */
31289 #define ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST))
31290 
31291 /*
31292  * Register : Register 327 (Hash Table Register 7) - Hash_Table_Reg7
31293  *
31294  * This register contains the eighth 32 bits of the hash table.
31295  *
31296  * Register Layout
31297  *
31298  * Bits | Access | Reset | Description
31299  * :-------|:-------|:------|:-----------------------------
31300  * [31:0] | RW | 0x0 | Eighth 32 bits of Hash Table
31301  *
31302  */
31303 /*
31304  * Field : Eighth 32 bits of Hash Table - ht255t224
31305  *
31306  * This field contains the eighth 32 Bits (255:224) of the Hash table.
31307  *
31308  * Field Access Macros:
31309  *
31310  */
31311 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
31312 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_LSB 0
31313 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
31314 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_MSB 31
31315 /* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
31316 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_WIDTH 32
31317 /* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
31318 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET_MSK 0xffffffff
31319 /* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
31320 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_CLR_MSK 0x00000000
31321 /* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
31322 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_RESET 0x0
31323 /* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 field value from a register. */
31324 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_GET(value) (((value) & 0xffffffff) >> 0)
31325 /* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value suitable for setting the register. */
31326 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET(value) (((value) << 0) & 0xffffffff)
31327 
31328 #ifndef __ASSEMBLY__
31329 /*
31330  * WARNING: The C register and register group struct declarations are provided for
31331  * convenience and illustrative purposes. They should, however, be used with
31332  * caution as the C language standard provides no guarantees about the alignment or
31333  * atomicity of device memory accesses. The recommended practice for writing
31334  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31335  * alt_write_word() functions.
31336  *
31337  * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7.
31338  */
31339 struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s
31340 {
31341  uint32_t ht255t224 : 32; /* Eighth 32 bits of Hash Table */
31342 };
31343 
31344 /* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7. */
31345 typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s ALT_EMAC_GMAC_HASH_TABLE_REG7_t;
31346 #endif /* __ASSEMBLY__ */
31347 
31348 /* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register from the beginning of the component. */
31349 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST 0x51c
31350 /* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register. */
31351 #define ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST))
31352 
31353 /*
31354  * Register : Register 353 (VLAN Tag Inclusion or Replacement Register) - VLAN_Incl_Reg
31355  *
31356  * The VLAN Tag Inclusion or Replacement register contains the VLAN tag for
31357  * insertion or replacement in the transmit frames.
31358  *
31359  * Register Layout
31360  *
31361  * Bits | Access | Reset | Description
31362  * :--------|:-------|:--------|:------------------------------------
31363  * [15:0] | RW | Unknown | VLAN Tag for Transmit Frames
31364  * [17:16] | RW | Unknown | VLAN Tag Control in Transmit Frames
31365  * [18] | RW | Unknown | VLAN Priority Control
31366  * [19] | RW | Unknown | C-VLAN or S-VLAN
31367  * [31:20] | ??? | 0x0 | *UNDEFINED*
31368  *
31369  */
31370 /*
31371  * Field : VLAN Tag for Transmit Frames - vlt
31372  *
31373  * This field contains the value of the VLAN tag to be inserted or replaced. The
31374  * value must only be changed when the transmit lines are inactive or during the
31375  * initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI,
31376  * and Bits[11:0] are the VLAN tag's VID field.
31377  *
31378  * Field Access Macros:
31379  *
31380  */
31381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
31382 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_LSB 0
31383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
31384 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_MSB 15
31385 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
31386 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_WIDTH 16
31387 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
31388 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET_MSK 0x0000ffff
31389 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
31390 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_CLR_MSK 0xffff0000
31391 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field is UNKNOWN. */
31392 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_RESET 0x0
31393 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT field value from a register. */
31394 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_GET(value) (((value) & 0x0000ffff) >> 0)
31395 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value suitable for setting the register. */
31396 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET(value) (((value) << 0) & 0x0000ffff)
31397 
31398 /*
31399  * Field : VLAN Tag Control in Transmit Frames - vlc
31400  *
31401  * * 2'b00: No VLAN tag deletion, insertion, or replacement
31402  *
31403  * * 2'b01: VLAN tag deletion
31404  *
31405  * The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16)
31406  * of all transmitted frames with VLAN tags.
31407  *
31408  * * 2'b10: VLAN tag insertion
31409  *
31410  * The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type
31411  * value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all
31412  * transmitted frames, irrespective of whether they already have a VLAN tag.
31413  *
31414  * * 2'b11: VLAN tag replacement
31415  *
31416  * The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames
31417  * (Bytes 13 and 14 are 0x8100/0x88a8).
31418  *
31419  * Note: Changes to this field take effect only on the start of a frame. If you
31420  * write this register field when a frame is being transmitted, only the subsequent
31421  * frame can use the updated value, that is, the current frame does not use the
31422  * updated value.
31423  *
31424  * Field Access Macros:
31425  *
31426  */
31427 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
31428 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_LSB 16
31429 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
31430 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_MSB 17
31431 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
31432 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_WIDTH 2
31433 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
31434 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET_MSK 0x00030000
31435 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
31436 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_CLR_MSK 0xfffcffff
31437 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field is UNKNOWN. */
31438 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_RESET 0x0
31439 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC field value from a register. */
31440 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_GET(value) (((value) & 0x00030000) >> 16)
31441 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value suitable for setting the register. */
31442 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET(value) (((value) << 16) & 0x00030000)
31443 
31444 /*
31445  * Field : VLAN Priority Control - vlp
31446  *
31447  * When this bit is set, the control Bits [17:16] are used for VLAN deletion,
31448  * insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control
31449  * input is used, and Bits [17:16] are ignored.
31450  *
31451  * Field Access Macros:
31452  *
31453  */
31454 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
31455 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_LSB 18
31456 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
31457 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_MSB 18
31458 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
31459 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_WIDTH 1
31460 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
31461 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET_MSK 0x00040000
31462 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
31463 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_CLR_MSK 0xfffbffff
31464 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field is UNKNOWN. */
31465 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_RESET 0x0
31466 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP field value from a register. */
31467 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_GET(value) (((value) & 0x00040000) >> 18)
31468 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value suitable for setting the register. */
31469 #define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET(value) (((value) << 18) & 0x00040000)
31470 
31471 /*
31472  * Field : C-VLAN or S-VLAN - csvl
31473  *
31474  * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th
31475  * and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type
31476  * (0x8100) is inserted or replaced in the transmitted frames.
31477  *
31478  * Field Access Macros:
31479  *
31480  */
31481 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
31482 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_LSB 19
31483 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
31484 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_MSB 19
31485 /* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
31486 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_WIDTH 1
31487 /* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
31488 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET_MSK 0x00080000
31489 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
31490 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_CLR_MSK 0xfff7ffff
31491 /* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field is UNKNOWN. */
31492 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_RESET 0x0
31493 /* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL field value from a register. */
31494 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_GET(value) (((value) & 0x00080000) >> 19)
31495 /* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value suitable for setting the register. */
31496 #define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET(value) (((value) << 19) & 0x00080000)
31497 
31498 #ifndef __ASSEMBLY__
31499 /*
31500  * WARNING: The C register and register group struct declarations are provided for
31501  * convenience and illustrative purposes. They should, however, be used with
31502  * caution as the C language standard provides no guarantees about the alignment or
31503  * atomicity of device memory accesses. The recommended practice for writing
31504  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31505  * alt_write_word() functions.
31506  *
31507  * The struct declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG.
31508  */
31509 struct ALT_EMAC_GMAC_VLAN_INCL_REG_s
31510 {
31511  uint32_t vlt : 16; /* VLAN Tag for Transmit Frames */
31512  uint32_t vlc : 2; /* VLAN Tag Control in Transmit Frames */
31513  uint32_t vlp : 1; /* VLAN Priority Control */
31514  uint32_t csvl : 1; /* C-VLAN or S-VLAN */
31515  uint32_t : 12; /* *UNDEFINED* */
31516 };
31517 
31518 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG. */
31519 typedef volatile struct ALT_EMAC_GMAC_VLAN_INCL_REG_s ALT_EMAC_GMAC_VLAN_INCL_REG_t;
31520 #endif /* __ASSEMBLY__ */
31521 
31522 /* The byte offset of the ALT_EMAC_GMAC_VLAN_INCL_REG register from the beginning of the component. */
31523 #define ALT_EMAC_GMAC_VLAN_INCL_REG_OFST 0x584
31524 /* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register. */
31525 #define ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_INCL_REG_OFST))
31526 
31527 /*
31528  * Register : Register 354 (VLAN Hash Table Register) - VLAN_Hash_Table_Reg
31529  *
31530  * The 16-bit Hash table is used for group address filtering based on VLAN tag when
31531  * Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the
31532  * content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN
31533  * Tag Register) in the incoming frame is passed through the CRC logic and the
31534  * upper four bits of the calculated CRC are used to index the contents of the VLAN
31535  * Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash
31536  * table.
31537  *
31538  * The hash value of the destination address is calculated in the following way:
31539  *
31540  * 1. Calculate the 32-bit CRC for the VLAN tag or ID (See IEEE 802.3, Section
31541  * 3.2.8 for the steps to calculate CRC32).
31542  *
31543  * 2. Perform bitwise reversal for the value obtained in Step 1.
31544  *
31545  * 3. Take the upper four bits from the value obtained in Step 2.
31546  *
31547  * If the corresponding bit value of the register is 1'b1, the frame is accepted.
31548  * Otherwise, it is rejected. Because the Hash Table register is double-
31549  * synchronized to the (G)MII clock domain, the synchronization is triggered only
31550  * when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of
31551  * this register are written.
31552  *
31553  * Notes:
31554  *
31555  * * Because of double-synchronization, consecutive writes to this register should
31556  * be performed after at least four clock cycles in the destination clock domain.
31557  *
31558  * Register Layout
31559  *
31560  * Bits | Access | Reset | Description
31561  * :--------|:-------|:------|:----------------
31562  * [15:0] | RW | 0x0 | VLAN Hash Table
31563  * [31:16] | ??? | 0x0 | *UNDEFINED*
31564  *
31565  */
31566 /*
31567  * Field : VLAN Hash Table - vlht
31568  *
31569  * This field contains the 16-bit VLAN Hash Table.
31570  *
31571  * Field Access Macros:
31572  *
31573  */
31574 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
31575 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_LSB 0
31576 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
31577 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_MSB 15
31578 /* The width in bits of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
31579 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_WIDTH 16
31580 /* The mask used to set the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
31581 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET_MSK 0x0000ffff
31582 /* The mask used to clear the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
31583 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_CLR_MSK 0xffff0000
31584 /* The reset value of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
31585 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_RESET 0x0
31586 /* Extracts the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT field value from a register. */
31587 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_GET(value) (((value) & 0x0000ffff) >> 0)
31588 /* Produces a ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value suitable for setting the register. */
31589 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET(value) (((value) << 0) & 0x0000ffff)
31590 
31591 #ifndef __ASSEMBLY__
31592 /*
31593  * WARNING: The C register and register group struct declarations are provided for
31594  * convenience and illustrative purposes. They should, however, be used with
31595  * caution as the C language standard provides no guarantees about the alignment or
31596  * atomicity of device memory accesses. The recommended practice for writing
31597  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
31598  * alt_write_word() functions.
31599  *
31600  * The struct declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG.
31601  */
31602 struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s
31603 {
31604  uint32_t vlht : 16; /* VLAN Hash Table */
31605  uint32_t : 16; /* *UNDEFINED* */
31606 };
31607 
31608 /* The typedef declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG. */
31609 typedef volatile struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t;
31610 #endif /* __ASSEMBLY__ */
31611 
31612 /* The byte offset of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register from the beginning of the component. */
31613 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST 0x588
31614 /* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register. */
31615 #define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST))
31616 
31617 /*
31618  * Register : Register 448 (Timestamp Control Register) - Timestamp_Control
31619  *
31620  * This register controls the operation of the System Time generator and the
31621  * processing of PTP packets for timestamping in the Receiver.
31622  *
31623  * Register Layout
31624  *
31625  * Bits | Access | Reset | Description
31626  * :--------|:-------|:------|:---------------------------------------------------
31627  * [0] | RW | 0x0 | Timestamp Enable
31628  * [1] | RW | 0x0 | Timestamp Fine or Coarse Update
31629  * [2] | RW | 0x0 | Timestamp Initialize
31630  * [3] | RW | 0x0 | Timestamp Update
31631  * [4] | RW | 0x0 | Timestamp Interrupt Trigger Enable
31632  * [5] | RW | 0x0 | Addend Reg Update
31633  * [7:6] | ??? | 0x0 | *UNDEFINED*
31634  * [8] | RW | 0x0 | Enable Timestamp for All Frames
31635  * [9] | RW | 0x0 | Timestamp Digital or Binary Rollover Control
31636  * [10] | RW | 0x0 | Enable PTP packet Processing for Version 2 Format
31637  * [11] | RW | 0x0 | Enable Processing of PTP over Ethernet Frames
31638  * [12] | RW | 0x0 | Enable Processing of PTP Frames Sent Over IPv6-UDP
31639  * [13] | RW | 0x1 | Enable Processing of PTP Frames Sent over IPv4-UDP
31640  * [14] | RW | 0x0 | Enable Timestamp Snapshot for Event Messages
31641  * [15] | RW | 0x0 | Enable Snapshot for Messages Relevant to Master
31642  * [17:16] | RW | 0x0 | Select PTP packets for Taking Snapshots
31643  * [18] | RW | 0x0 | Enable MAC address for PTP Frame Filtering
31644  * [23:19] | ??? | 0x0 | *UNDEFINED*
31645  * [24] | RW | 0x0 | Auxiliary Snapshot FIFO Clear
31646  * [25] | RW | 0x0 | Auxiliary Snapshot 0 Enable
31647  * [31:26] | ??? | 0x0 | *UNDEFINED*
31648  *
31649  */
31650 /*
31651  * Field : Timestamp Enable - tsena
31652  *
31653  * When set, the timestamp is added for the transmit and receive frames. When
31654  * disabled, timestamp is not added for the transmit and receive frames and the
31655  * Timestamp Generator is also suspended. You need to initialize the Timestamp
31656  * (system time) after enabling this mode.
31657  *
31658  * On the receive side, the MAC processes the 1588 frames only if this bit is set.
31659  *
31660  * Field Enumeration Values:
31661  *
31662  * Enum | Value | Description
31663  * :----------------------------------|:------|:-----------------------------------------
31664  * ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS | 0x0 | Timestamp not added
31665  * ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS | 0x1 | Timestamp added for transmit and receive
31666  *
31667  * Field Access Macros:
31668  *
31669  */
31670 /*
31671  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
31672  *
31673  * Timestamp not added
31674  */
31675 #define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0
31676 /*
31677  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
31678  *
31679  * Timestamp added for transmit and receive
31680  */
31681 #define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1
31682 
31683 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
31684 #define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB 0
31685 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
31686 #define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB 0
31687 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
31688 #define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH 1
31689 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
31690 #define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK 0x00000001
31691 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
31692 #define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK 0xfffffffe
31693 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
31694 #define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET 0x0
31695 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register. */
31696 #define ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value) (((value) & 0x00000001) >> 0)
31697 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register. */
31698 #define ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value) (((value) << 0) & 0x00000001)
31699 
31700 /*
31701  * Field : Timestamp Fine or Coarse Update - tscfupdt
31702  *
31703  * When set, this bit indicates that the system times update should be done using
31704  * the fine update method. When reset, it indicates the system timestamp update
31705  * should be done using the Coarse method.
31706  *
31707  * Field Enumeration Values:
31708  *
31709  * Enum | Value | Description
31710  * :------------------------------------------|:------|:-----------------
31711  * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE | 0x0 | Timestamp Coarse
31712  * ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE | 0x1 | Timestamp Fine
31713  *
31714  * Field Access Macros:
31715  *
31716  */
31717 /*
31718  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
31719  *
31720  * Timestamp Coarse
31721  */
31722 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0
31723 /*
31724  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
31725  *
31726  * Timestamp Fine
31727  */
31728 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1
31729 
31730 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
31731 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB 1
31732 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
31733 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB 1
31734 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
31735 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH 1
31736 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
31737 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK 0x00000002
31738 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
31739 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK 0xfffffffd
31740 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
31741 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET 0x0
31742 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register. */
31743 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value) (((value) & 0x00000002) >> 1)
31744 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register. */
31745 #define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value) (((value) << 1) & 0x00000002)
31746 
31747 /*
31748  * Field : Timestamp Initialize - tsinit
31749  *
31750  * When set, the system time is initialized (overwritten) with the value specified
31751  * in the Register 452 (System Time - Seconds Update Register) and Register 453
31752  * (System Time - Nanoseconds Update Register).
31753  *
31754  * This bit should be read zero before updating it. This bit is reset when the
31755  * initialization is complete. The Timestamp Higher Word register can only be
31756  * initialized.
31757  *
31758  * Field Enumeration Values:
31759  *
31760  * Enum | Value | Description
31761  * :----------------------------------------|:------|:-------------------------------------------------
31762  * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT | 0x0 | Timestamp not initialized (overwritten) by
31763  * : | | values in Register 452 and Register 453
31764  * ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT | 0x1 | Timestamp initialized (overwritten) by values in
31765  * : | | Register 452 and Register 453
31766  *
31767  * Field Access Macros:
31768  *
31769  */
31770 /*
31771  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
31772  *
31773  * Timestamp not initialized (overwritten) by values in Register 452 and Register
31774  * 453
31775  */
31776 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0
31777 /*
31778  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
31779  *
31780  * Timestamp initialized (overwritten) by values in Register 452 and Register 453
31781  */
31782 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1
31783 
31784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
31785 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB 2
31786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
31787 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB 2
31788 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
31789 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH 1
31790 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
31791 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK 0x00000004
31792 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
31793 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK 0xfffffffb
31794 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
31795 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET 0x0
31796 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register. */
31797 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value) (((value) & 0x00000004) >> 2)
31798 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register. */
31799 #define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value) (((value) << 2) & 0x00000004)
31800 
31801 /*
31802  * Field : Timestamp Update - tsupdt
31803  *
31804  * When set, the system time is updated (added or subtracted) with the value
31805  * specified in Register 452 (System Time - Seconds Update Register) and Register
31806  * 453 (System Time - Nanoseconds Update Register).
31807  *
31808  * This bit should be read zero before updating it. This bit is reset when the
31809  * update is completed in hardware. The Timestamp Higher Word register is not
31810  * updated.
31811  *
31812  * Field Enumeration Values:
31813  *
31814  * Enum | Value | Description
31815  * :-------------------------------------------|:------|:-------------------------------------------------
31816  * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED | 0x0 | Timestamp not updated (added or subtracted) with
31817  * : | | values in Register 452 and Register 453
31818  * ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED | 0x1 | Timestamp updated (added or subtracted) with
31819  * : | | values in Register 452 and Register 453
31820  *
31821  * Field Access Macros:
31822  *
31823  */
31824 /*
31825  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
31826  *
31827  * Timestamp not updated (added or subtracted) with values in Register 452 and
31828  * Register 453
31829  */
31830 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0
31831 /*
31832  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
31833  *
31834  * Timestamp updated (added or subtracted) with values in Register 452 and Register
31835  * 453
31836  */
31837 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1
31838 
31839 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
31840 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB 3
31841 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
31842 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB 3
31843 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
31844 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH 1
31845 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
31846 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK 0x00000008
31847 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
31848 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK 0xfffffff7
31849 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
31850 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET 0x0
31851 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register. */
31852 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value) (((value) & 0x00000008) >> 3)
31853 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register. */
31854 #define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value) (((value) << 3) & 0x00000008)
31855 
31856 /*
31857  * Field : Timestamp Interrupt Trigger Enable - tstrig
31858  *
31859  * When set, the timestamp interrupt is generated when the System Time becomes
31860  * greater than the value written in the Target Time register. This bit is reset
31861  * after the generation of the Timestamp Trigger Interrupt.
31862  *
31863  * Field Enumeration Values:
31864  *
31865  * Enum | Value | Description
31866  * :------------------------------------------------|:------|:------------------------
31867  * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN | 0x0 | Timestamp not generated
31868  * ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN | 0x1 | Timestamp generated
31869  *
31870  * Field Access Macros:
31871  *
31872  */
31873 /*
31874  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
31875  *
31876  * Timestamp not generated
31877  */
31878 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0
31879 /*
31880  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
31881  *
31882  * Timestamp generated
31883  */
31884 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1
31885 
31886 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
31887 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB 4
31888 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
31889 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB 4
31890 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
31891 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH 1
31892 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
31893 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK 0x00000010
31894 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
31895 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK 0xffffffef
31896 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
31897 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET 0x0
31898 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register. */
31899 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value) (((value) & 0x00000010) >> 4)
31900 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register. */
31901 #define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value) (((value) << 4) & 0x00000010)
31902 
31903 /*
31904  * Field : Addend Reg Update - tsaddreg
31905  *
31906  * When set, the content of the Timestamp Addend register is updated in the PTP
31907  * block for fine correction. This is cleared when the update is completed. This
31908  * register bit should be zero before setting it.
31909  *
31910  * Field Enumeration Values:
31911  *
31912  * Enum | Value | Description
31913  * :----------------------------------------------------|:------|:-----------------------------------------
31914  * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED | 0x0 | Timestamp Addend register is not updated
31915  * ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED | 0x1 | Timestamp Addend register is updated
31916  *
31917  * Field Access Macros:
31918  *
31919  */
31920 /*
31921  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
31922  *
31923  * Timestamp Addend register is not updated
31924  */
31925 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0
31926 /*
31927  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
31928  *
31929  * Timestamp Addend register is updated
31930  */
31931 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1
31932 
31933 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
31934 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB 5
31935 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
31936 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB 5
31937 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
31938 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH 1
31939 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
31940 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK 0x00000020
31941 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
31942 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK 0xffffffdf
31943 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
31944 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET 0x0
31945 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register. */
31946 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value) (((value) & 0x00000020) >> 5)
31947 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register. */
31948 #define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value) (((value) << 5) & 0x00000020)
31949 
31950 /*
31951  * Field : Enable Timestamp for All Frames - tsenall
31952  *
31953  * When set, the timestamp snapshot is enabled for all frames received by the MAC.
31954  *
31955  * Field Enumeration Values:
31956  *
31957  * Enum | Value | Description
31958  * :------------------------------------|:------|:----------------------------
31959  * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD | 0x0 | Timestamp snapshot disabled
31960  * ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END | 0x1 | Timestamp snapshot enabled
31961  *
31962  * Field Access Macros:
31963  *
31964  */
31965 /*
31966  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
31967  *
31968  * Timestamp snapshot disabled
31969  */
31970 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0
31971 /*
31972  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
31973  *
31974  * Timestamp snapshot enabled
31975  */
31976 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1
31977 
31978 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
31979 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB 8
31980 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
31981 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB 8
31982 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
31983 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH 1
31984 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
31985 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK 0x00000100
31986 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
31987 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK 0xfffffeff
31988 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
31989 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET 0x0
31990 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register. */
31991 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value) (((value) & 0x00000100) >> 8)
31992 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register. */
31993 #define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value) (((value) << 8) & 0x00000100)
31994 
31995 /*
31996  * Field : Timestamp Digital or Binary Rollover Control - tsctrlssr
31997  *
31998  * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that
31999  * is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When
32000  * reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second
32001  * increment has to be programmed correctly depending on the PTP reference clock
32002  * frequency and the value of this bit.
32003  *
32004  * Field Enumeration Values:
32005  *
32006  * Enum | Value | Description
32007  * :--------------------------------------------------|:------|:-------------------------------------------------
32008  * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX | 0x0 | Timestamp Low register rolls over at 0x7FFF_FFFF
32009  * ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS | 0x1 | Timestamp Low register rolls over at 1ns
32010  *
32011  * Field Access Macros:
32012  *
32013  */
32014 /*
32015  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
32016  *
32017  * Timestamp Low register rolls over at 0x7FFF_FFFF
32018  */
32019 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0
32020 /*
32021  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
32022  *
32023  * Timestamp Low register rolls over at 1ns
32024  */
32025 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1
32026 
32027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
32028 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB 9
32029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
32030 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB 9
32031 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
32032 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH 1
32033 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
32034 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK 0x00000200
32035 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
32036 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK 0xfffffdff
32037 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
32038 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET 0x0
32039 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register. */
32040 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value) (((value) & 0x00000200) >> 9)
32041 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register. */
32042 #define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value) (((value) << 9) & 0x00000200)
32043 
32044 /*
32045  * Field : Enable PTP packet Processing for Version 2 Format - tsver2ena
32046  *
32047  * When set, the PTP packets are processed using the 1588 version 2 format.
32048  * Otherwise, the PTP packets are processed using the version 1 format.
32049  *
32050  * Field Enumeration Values:
32051  *
32052  * Enum | Value | Description
32053  * :-----------------------------------------------|:------|:-------------------------------------------------
32054  * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 | 0x0 | PTP packets processed with 1588 version 1 format
32055  * ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 | 0x1 | PTP packets processed with 1588 version 2 format
32056  *
32057  * Field Access Macros:
32058  *
32059  */
32060 /*
32061  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
32062  *
32063  * PTP packets processed with 1588 version 1 format
32064  */
32065 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0
32066 /*
32067  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
32068  *
32069  * PTP packets processed with 1588 version 2 format
32070  */
32071 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1
32072 
32073 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
32074 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB 10
32075 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
32076 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB 10
32077 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
32078 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH 1
32079 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
32080 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK 0x00000400
32081 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
32082 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK 0xfffffbff
32083 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
32084 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET 0x0
32085 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register. */
32086 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value) (((value) & 0x00000400) >> 10)
32087 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register. */
32088 #define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value) (((value) << 10) & 0x00000400)
32089 
32090 /*
32091  * Field : Enable Processing of PTP over Ethernet Frames - tsipena
32092  *
32093  * When set, the MAC receiver processes the PTP packets encapsulated directly in
32094  * the Ethernet frames. When this bit is clear, the MAC ignores the PTP over
32095  * Ethernet packets.
32096  *
32097  * Field Enumeration Values:
32098  *
32099  * Enum | Value | Description
32100  * :----------------------------------------------|:------|:---------------------------------------------
32101  * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in Ethernet frames
32102  * ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP | 0x1 | Process PTP packets in Ethernet frames
32103  *
32104  * Field Access Macros:
32105  *
32106  */
32107 /*
32108  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
32109  *
32110  * Don't process PTP packets in Ethernet frames
32111  */
32112 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0
32113 /*
32114  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
32115  *
32116  * Process PTP packets in Ethernet frames
32117  */
32118 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1
32119 
32120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
32121 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB 11
32122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
32123 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB 11
32124 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
32125 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH 1
32126 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
32127 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK 0x00000800
32128 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
32129 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK 0xfffff7ff
32130 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
32131 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET 0x0
32132 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register. */
32133 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value) (((value) & 0x00000800) >> 11)
32134 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register. */
32135 #define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value) (((value) << 11) & 0x00000800)
32136 
32137 /*
32138  * Field : Enable Processing of PTP Frames Sent Over IPv6-UDP - tsipv6ena
32139  *
32140  * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6
32141  * packets. When this bit is clear, the MAC ignores the PTP transported over UDP-
32142  * IPv6 packets.
32143  *
32144  * Field Enumeration Values:
32145  *
32146  * Enum | Value | Description
32147  * :------------------------------------------------|:------|:-------------------------------------------
32148  * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in UDP over IPv6
32149  * ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP | 0x1 | Process PTP packets in UDP over IPv6
32150  *
32151  * Field Access Macros:
32152  *
32153  */
32154 /*
32155  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
32156  *
32157  * Don't process PTP packets in UDP over IPv6
32158  */
32159 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0
32160 /*
32161  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
32162  *
32163  * Process PTP packets in UDP over IPv6
32164  */
32165 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1
32166 
32167 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
32168 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB 12
32169 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
32170 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB 12
32171 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
32172 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH 1
32173 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
32174 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK 0x00001000
32175 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
32176 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK 0xffffefff
32177 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
32178 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET 0x0
32179 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register. */
32180 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value) (((value) & 0x00001000) >> 12)
32181 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register. */
32182 #define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value) (((value) << 12) & 0x00001000)
32183 
32184 /*
32185  * Field : Enable Processing of PTP Frames Sent over IPv4-UDP - tsipv4ena
32186  *
32187  * When set, the MAC receiver processes the PTP packets encapsulated in UDP over
32188  * IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over
32189  * UDP-IPv4 packets. This bit is set by default.
32190  *
32191  * Field Enumeration Values:
32192  *
32193  * Enum | Value | Description
32194  * :------------------------------------------------|:------|:-------------------------------------------
32195  * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP | 0x0 | Don't process PTP packets in UDP over IPv4
32196  * ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP | 0x1 | Process PTP packets in UDP over IPv4
32197  *
32198  * Field Access Macros:
32199  *
32200  */
32201 /*
32202  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
32203  *
32204  * Don't process PTP packets in UDP over IPv4
32205  */
32206 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0
32207 /*
32208  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
32209  *
32210  * Process PTP packets in UDP over IPv4
32211  */
32212 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1
32213 
32214 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
32215 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB 13
32216 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
32217 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB 13
32218 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
32219 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH 1
32220 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
32221 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK 0x00002000
32222 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
32223 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK 0xffffdfff
32224 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
32225 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET 0x1
32226 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register. */
32227 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value) (((value) & 0x00002000) >> 13)
32228 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register. */
32229 #define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value) (((value) << 13) & 0x00002000)
32230 
32231 /*
32232  * Field : Enable Timestamp Snapshot for Event Messages - tsevntena
32233  *
32234  * When set, the timestamp snapshot is taken only for event messages (SYNC,
32235  * Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for
32236  * all messages except Announce, Management, and Signaling.
32237  *
32238  * Field Enumeration Values:
32239  *
32240  * Enum | Value | Description
32241  * :--------------------------------------|:------|:-----------------------------------------------
32242  * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD | 0x0 | Timestamp snapshot disabled for event messages
32243  * ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END | 0x1 | Timestamp snapshot only for event messages
32244  *
32245  * Field Access Macros:
32246  *
32247  */
32248 /*
32249  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
32250  *
32251  * Timestamp snapshot disabled for event messages
32252  */
32253 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0
32254 /*
32255  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
32256  *
32257  * Timestamp snapshot only for event messages
32258  */
32259 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1
32260 
32261 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
32262 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB 14
32263 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
32264 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB 14
32265 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
32266 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH 1
32267 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
32268 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK 0x00004000
32269 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
32270 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK 0xffffbfff
32271 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
32272 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET 0x0
32273 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register. */
32274 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value) (((value) & 0x00004000) >> 14)
32275 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register. */
32276 #define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value) (((value) << 14) & 0x00004000)
32277 
32278 /*
32279  * Field : Enable Snapshot for Messages Relevant to Master - tsmstrena
32280  *
32281  * When set, the snapshot is taken only for the messages relevant to the master
32282  * node. Otherwise, the snapshot is taken for the messages relevant to the slave
32283  * node.
32284  *
32285  * Field Enumeration Values:
32286  *
32287  * Enum | Value | Description
32288  * :-------------------------------------|:------|:-----------------------------------------------
32289  * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV | 0x0 | Timestamp snapshot taken for messages relevant
32290  * : | | to slave node
32291  * ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST | 0x1 | Timestamp snapshot taken for messages relevant
32292  * : | | to master node
32293  *
32294  * Field Access Macros:
32295  *
32296  */
32297 /*
32298  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
32299  *
32300  * Timestamp snapshot taken for messages relevant to slave node
32301  */
32302 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0
32303 /*
32304  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
32305  *
32306  * Timestamp snapshot taken for messages relevant to master node
32307  */
32308 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1
32309 
32310 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
32311 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB 15
32312 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
32313 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB 15
32314 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
32315 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH 1
32316 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
32317 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK 0x00008000
32318 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
32319 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK 0xffff7fff
32320 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
32321 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET 0x0
32322 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register. */
32323 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value) (((value) & 0x00008000) >> 15)
32324 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register. */
32325 #define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value) (((value) << 15) & 0x00008000)
32326 
32327 /*
32328  * Field : Select PTP packets for Taking Snapshots - snaptypsel
32329  *
32330  * These bits along with Bits 15 and 14 decide the set of PTP packet types for
32331  * which snapshot needs to be taken.
32332  *
32333  * Field Access Macros:
32334  *
32335  */
32336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
32337 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB 16
32338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
32339 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB 17
32340 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
32341 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH 2
32342 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
32343 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK 0x00030000
32344 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
32345 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK 0xfffcffff
32346 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
32347 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET 0x0
32348 /* Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register. */
32349 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value) (((value) & 0x00030000) >> 16)
32350 /* Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register. */
32351 #define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value) (((value) << 16) & 0x00030000)
32352 
32353 /*
32354  * Field : Enable MAC address for PTP Frame Filtering - tsenmacaddr
32355  *
32356  * When set, the DA MAC address (that matches any MAC Address register) is used to
32357  * filter the PTP frames when PTP is directly sent over Ethernet.
32358  *
32359  * Field Enumeration Values:
32360  *
32361  * Enum | Value | Description
32362  * :----------------------------------------|:------|:-----------------------------------------
32363  * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD | 0x0 | DA MAC address doesn't filter PTP frames
32364  * ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END | 0x1 | DA MAC address filters PTP frames
32365  *
32366  * Field Access Macros:
32367  *
32368  */
32369 /*
32370  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
32371  *
32372  * DA MAC address doesn't filter PTP frames
32373  */
32374 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0
32375 /*
32376  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
32377  *
32378  * DA MAC address filters PTP frames
32379  */
32380 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1
32381 
32382 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
32383 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB 18
32384 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
32385 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB 18
32386 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
32387 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH 1
32388 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
32389 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK 0x00040000
32390 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
32391 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK 0xfffbffff
32392 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
32393 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET 0x0
32394 /* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register. */
32395 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value) (((value) & 0x00040000) >> 18)
32396 /* Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register. */
32397 #define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value) (((value) << 18) & 0x00040000)
32398 
32399 /*
32400  * Field : Auxiliary Snapshot FIFO Clear - atsfc
32401  *
32402  * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is
32403  * cleared when the pointers are reset and the FIFO is empty. When this bit is
32404  * high, auxiliary snapshots get stored in the FIFO.
32405  *
32406  * Field Enumeration Values:
32407  *
32408  * Enum | Value | Description
32409  * :----------------------------------|:------|:---------------------------------------------
32410  * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD | 0x0 | Don't reset Auxiliary Snapshot FIFO pointers
32411  * ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END | 0x1 | Reset Auxiliary Snapshot FIFO pointers
32412  *
32413  * Field Access Macros:
32414  *
32415  */
32416 /*
32417  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
32418  *
32419  * Don't reset Auxiliary Snapshot FIFO pointers
32420  */
32421 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0
32422 /*
32423  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
32424  *
32425  * Reset Auxiliary Snapshot FIFO pointers
32426  */
32427 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1
32428 
32429 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
32430 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB 24
32431 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
32432 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB 24
32433 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
32434 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH 1
32435 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
32436 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK 0x01000000
32437 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
32438 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK 0xfeffffff
32439 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
32440 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET 0x0
32441 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register. */
32442 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value) (((value) & 0x01000000) >> 24)
32443 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register. */
32444 #define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value) (((value) << 24) & 0x01000000)
32445 
32446 /*
32447  * Field : Auxiliary Snapshot 0 Enable - atsen0
32448  *
32449  * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is
32450  * set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When
32451  * this bit is reset, the events on this input are ignored.
32452  *
32453  * Field Enumeration Values:
32454  *
32455  * Enum | Value | Description
32456  * :-----------------------------------|:------|:-------------------------------------------------
32457  * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD | 0x0 | Auxiliary snapshot of event on ptp_aux_trig_i[0]
32458  * : | | input is disabled.
32459  * ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END | 0x1 | Auxiliary snapshot of event on ptp_aux_trig_i[0]
32460  * : | | input is enabled.
32461  *
32462  * Field Access Macros:
32463  *
32464  */
32465 /*
32466  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
32467  *
32468  * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is disabled.
32469  */
32470 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0
32471 /*
32472  * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
32473  *
32474  * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled.
32475  */
32476 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1
32477 
32478 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
32479 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB 25
32480 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
32481 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB 25
32482 /* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
32483 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH 1
32484 /* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
32485 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK 0x02000000
32486 /* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
32487 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK 0xfdffffff
32488 /* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
32489 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET 0x0
32490 /* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register. */
32491 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value) (((value) & 0x02000000) >> 25)
32492 /* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register. */
32493 #define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value) (((value) << 25) & 0x02000000)
32494 
32495 #ifndef __ASSEMBLY__
32496 /*
32497  * WARNING: The C register and register group struct declarations are provided for
32498  * convenience and illustrative purposes. They should, however, be used with
32499  * caution as the C language standard provides no guarantees about the alignment or
32500  * atomicity of device memory accesses. The recommended practice for writing
32501  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32502  * alt_write_word() functions.
32503  *
32504  * The struct declaration for register ALT_EMAC_GMAC_TS_CTL.
32505  */
32506 struct ALT_EMAC_GMAC_TS_CTL_s
32507 {
32508  uint32_t tsena : 1; /* Timestamp Enable */
32509  uint32_t tscfupdt : 1; /* Timestamp Fine or Coarse Update */
32510  uint32_t tsinit : 1; /* Timestamp Initialize */
32511  uint32_t tsupdt : 1; /* Timestamp Update */
32512  uint32_t tstrig : 1; /* Timestamp Interrupt Trigger Enable */
32513  uint32_t tsaddreg : 1; /* Addend Reg Update */
32514  uint32_t : 2; /* *UNDEFINED* */
32515  uint32_t tsenall : 1; /* Enable Timestamp for All Frames */
32516  uint32_t tsctrlssr : 1; /* Timestamp Digital or Binary Rollover Control */
32517  uint32_t tsver2ena : 1; /* Enable PTP packet Processing for Version 2 Format */
32518  uint32_t tsipena : 1; /* Enable Processing of PTP over Ethernet Frames */
32519  uint32_t tsipv6ena : 1; /* Enable Processing of PTP Frames Sent Over IPv6-UDP */
32520  uint32_t tsipv4ena : 1; /* Enable Processing of PTP Frames Sent over IPv4-UDP */
32521  uint32_t tsevntena : 1; /* Enable Timestamp Snapshot for Event Messages */
32522  uint32_t tsmstrena : 1; /* Enable Snapshot for Messages Relevant to Master */
32523  uint32_t snaptypsel : 2; /* Select PTP packets for Taking Snapshots */
32524  uint32_t tsenmacaddr : 1; /* Enable MAC address for PTP Frame Filtering */
32525  uint32_t : 5; /* *UNDEFINED* */
32526  uint32_t atsfc : 1; /* Auxiliary Snapshot FIFO Clear */
32527  uint32_t atsen0 : 1; /* Auxiliary Snapshot 0 Enable */
32528  uint32_t : 6; /* *UNDEFINED* */
32529 };
32530 
32531 /* The typedef declaration for register ALT_EMAC_GMAC_TS_CTL. */
32532 typedef volatile struct ALT_EMAC_GMAC_TS_CTL_s ALT_EMAC_GMAC_TS_CTL_t;
32533 #endif /* __ASSEMBLY__ */
32534 
32535 /* The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component. */
32536 #define ALT_EMAC_GMAC_TS_CTL_OFST 0x700
32537 /* The address of the ALT_EMAC_GMAC_TS_CTL register. */
32538 #define ALT_EMAC_GMAC_TS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST))
32539 
32540 /*
32541  * Register : Register 449 (Sub-Second Increment Register) - Sub_Second_Increment
32542  *
32543  * In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this
32544  * register is added to the system time every clock cycle of clk_ptp_ref_i. In the
32545  * Fine Update mode, the value in this register is added to the system time
32546  * whenever the Accumulator gets an overflow.
32547  *
32548  * Register Layout
32549  *
32550  * Bits | Access | Reset | Description
32551  * :-------|:-------|:------|:---------------------------
32552  * [7:0] | RW | 0x0 | Sub-second Increment Value
32553  * [31:8] | ??? | 0x0 | *UNDEFINED*
32554  *
32555  */
32556 /*
32557  * Field : Sub-second Increment Value - ssinc
32558  *
32559  * The value programmed in this field is accumulated every clock cycle (of
32560  * clk_ptp_i) with the contents of the sub-second register. For example, when PTP
32561  * clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System
32562  * Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set). When
32563  * TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In
32564  * this case, you should program a value of 43 (0x2B) that is derived by
32565  * 20ns/0.465.
32566  *
32567  * Field Access Macros:
32568  *
32569  */
32570 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
32571 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB 0
32572 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
32573 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB 7
32574 /* The width in bits of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
32575 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH 8
32576 /* The mask used to set the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
32577 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK 0x000000ff
32578 /* The mask used to clear the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
32579 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK 0xffffff00
32580 /* The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
32581 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET 0x0
32582 /* Extracts the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC field value from a register. */
32583 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET(value) (((value) & 0x000000ff) >> 0)
32584 /* Produces a ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value suitable for setting the register. */
32585 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET(value) (((value) << 0) & 0x000000ff)
32586 
32587 #ifndef __ASSEMBLY__
32588 /*
32589  * WARNING: The C register and register group struct declarations are provided for
32590  * convenience and illustrative purposes. They should, however, be used with
32591  * caution as the C language standard provides no guarantees about the alignment or
32592  * atomicity of device memory accesses. The recommended practice for writing
32593  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32594  * alt_write_word() functions.
32595  *
32596  * The struct declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT.
32597  */
32598 struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s
32599 {
32600  uint32_t ssinc : 8; /* Sub-second Increment Value */
32601  uint32_t : 24; /* *UNDEFINED* */
32602 };
32603 
32604 /* The typedef declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT. */
32605 typedef volatile struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t;
32606 #endif /* __ASSEMBLY__ */
32607 
32608 /* The byte offset of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register from the beginning of the component. */
32609 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST 0x704
32610 /* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register. */
32611 #define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST))
32612 
32613 /*
32614  * Register : Register 450 (System Time - Seconds Register) - System_Time_Seconds
32615  *
32616  * The System Time -Seconds register, along with System-TimeNanoseconds register,
32617  * indicates the current value of the system time maintained by the MAC. Though it
32618  * is updated on a continuous basis, there is some delay from the actual time
32619  * because of clock domain transfer latencies (from clk_ptp_ref_i to l3_sp_clk).
32620  *
32621  * Register Layout
32622  *
32623  * Bits | Access | Reset | Description
32624  * :-------|:-------|:------|:-----------------
32625  * [31:0] | R | 0x0 | Timestamp Second
32626  *
32627  */
32628 /*
32629  * Field : Timestamp Second - tss
32630  *
32631  * The value in this field indicates the current value in seconds of the System
32632  * Time maintained by the MAC.
32633  *
32634  * Field Access Macros:
32635  *
32636  */
32637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
32638 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_LSB 0
32639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
32640 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_MSB 31
32641 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
32642 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_WIDTH 32
32643 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
32644 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET_MSK 0xffffffff
32645 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
32646 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_CLR_MSK 0x00000000
32647 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
32648 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_RESET 0x0
32649 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS field value from a register. */
32650 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_GET(value) (((value) & 0xffffffff) >> 0)
32651 /* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value suitable for setting the register. */
32652 #define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET(value) (((value) << 0) & 0xffffffff)
32653 
32654 #ifndef __ASSEMBLY__
32655 /*
32656  * WARNING: The C register and register group struct declarations are provided for
32657  * convenience and illustrative purposes. They should, however, be used with
32658  * caution as the C language standard provides no guarantees about the alignment or
32659  * atomicity of device memory accesses. The recommended practice for writing
32660  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32661  * alt_write_word() functions.
32662  *
32663  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS.
32664  */
32665 struct ALT_EMAC_GMAC_SYS_TIME_SECS_s
32666 {
32667  const uint32_t tss : 32; /* Timestamp Second */
32668 };
32669 
32670 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS. */
32671 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_s ALT_EMAC_GMAC_SYS_TIME_SECS_t;
32672 #endif /* __ASSEMBLY__ */
32673 
32674 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS register from the beginning of the component. */
32675 #define ALT_EMAC_GMAC_SYS_TIME_SECS_OFST 0x708
32676 /* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register. */
32677 #define ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_OFST))
32678 
32679 /*
32680  * Register : Register 451 (System Time - Nanoseconds Register) - System_Time_Nanoseconds
32681  *
32682  * The value in this field has the sub second representation of time, with an
32683  * accuracy of 0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the
32684  * maximum value is 0x3B9A_C9FF, after which it rolls-over to zero.
32685  *
32686  * Register Layout
32687  *
32688  * Bits | Access | Reset | Description
32689  * :-------|:-------|:------|:----------------------
32690  * [30:0] | R | 0x0 | Timestamp Sub Seconds
32691  * [31] | ??? | 0x0 | *UNDEFINED*
32692  *
32693  */
32694 /*
32695  * Field : Timestamp Sub Seconds - tsss
32696  *
32697  * The value in this field has the sub second representation of time, with an
32698  * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
32699  * Control Register), each bit represents 1 ns and the maximum value is
32700  * 0x3B9A_C9FF, after which it rolls-over to zero.
32701  *
32702  * Field Access Macros:
32703  *
32704  */
32705 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
32706 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_LSB 0
32707 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
32708 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_MSB 30
32709 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
32710 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_WIDTH 31
32711 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
32712 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET_MSK 0x7fffffff
32713 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
32714 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_CLR_MSK 0x80000000
32715 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
32716 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_RESET 0x0
32717 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS field value from a register. */
32718 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
32719 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value suitable for setting the register. */
32720 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET(value) (((value) << 0) & 0x7fffffff)
32721 
32722 #ifndef __ASSEMBLY__
32723 /*
32724  * WARNING: The C register and register group struct declarations are provided for
32725  * convenience and illustrative purposes. They should, however, be used with
32726  * caution as the C language standard provides no guarantees about the alignment or
32727  * atomicity of device memory accesses. The recommended practice for writing
32728  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32729  * alt_write_word() functions.
32730  *
32731  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS.
32732  */
32733 struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s
32734 {
32735  const uint32_t tsss : 31; /* Timestamp Sub Seconds */
32736  uint32_t : 1; /* *UNDEFINED* */
32737 };
32738 
32739 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS. */
32740 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t;
32741 #endif /* __ASSEMBLY__ */
32742 
32743 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register from the beginning of the component. */
32744 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST 0x70c
32745 /* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register. */
32746 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST))
32747 
32748 /*
32749  * Register : Register 452 (System Time - Seconds Update Register) - System_Time_Seconds_Update
32750  *
32751  * The System Time - Seconds Update register, along with the System Time -
32752  * Nanoseconds Update register, initializes or updates the system time maintained
32753  * by the MAC. You must write both of these registers before setting the TSINIT or
32754  * TSUPDT bits in the Timestamp Control register.
32755  *
32756  * Register Layout
32757  *
32758  * Bits | Access | Reset | Description
32759  * :-------|:-------|:------|:-----------------
32760  * [31:0] | RW | 0x0 | Timestamp Second
32761  *
32762  */
32763 /*
32764  * Field : Timestamp Second - tss
32765  *
32766  * The value in this field indicates the time in seconds to be initialized or added
32767  * to the system time.
32768  *
32769  * Field Access Macros:
32770  *
32771  */
32772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
32773 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_LSB 0
32774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
32775 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_MSB 31
32776 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
32777 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_WIDTH 32
32778 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
32779 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET_MSK 0xffffffff
32780 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
32781 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_CLR_MSK 0x00000000
32782 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
32783 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_RESET 0x0
32784 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS field value from a register. */
32785 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_GET(value) (((value) & 0xffffffff) >> 0)
32786 /* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value suitable for setting the register. */
32787 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET(value) (((value) << 0) & 0xffffffff)
32788 
32789 #ifndef __ASSEMBLY__
32790 /*
32791  * WARNING: The C register and register group struct declarations are provided for
32792  * convenience and illustrative purposes. They should, however, be used with
32793  * caution as the C language standard provides no guarantees about the alignment or
32794  * atomicity of device memory accesses. The recommended practice for writing
32795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32796  * alt_write_word() functions.
32797  *
32798  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE.
32799  */
32800 struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s
32801 {
32802  uint32_t tss : 32; /* Timestamp Second */
32803 };
32804 
32805 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE. */
32806 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t;
32807 #endif /* __ASSEMBLY__ */
32808 
32809 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register from the beginning of the component. */
32810 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST 0x710
32811 /* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register. */
32812 #define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST))
32813 
32814 /*
32815  * Register : Register 453 (System Time - Nanoseconds Update Register) - System_Time_Nanoseconds_Update
32816  *
32817  * Update system time
32818  *
32819  * Register Layout
32820  *
32821  * Bits | Access | Reset | Description
32822  * :-------|:-------|:------|:---------------------
32823  * [30:0] | RW | 0x0 | Timestamp Sub Second
32824  * [31] | RW | 0x0 | Add or subtract time
32825  *
32826  */
32827 /*
32828  * Field : Timestamp Sub Second - tsss
32829  *
32830  * The value in this field has the sub second representation of time, with an
32831  * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
32832  * Control Register), each bit represents 1 ns and the programmed value should not
32833  * exceed 0x3B9A_C9FF.
32834  *
32835  * Field Access Macros:
32836  *
32837  */
32838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
32839 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_LSB 0
32840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
32841 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_MSB 30
32842 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
32843 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_WIDTH 31
32844 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
32845 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET_MSK 0x7fffffff
32846 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
32847 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_CLR_MSK 0x80000000
32848 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
32849 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_RESET 0x0
32850 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS field value from a register. */
32851 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
32852 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value suitable for setting the register. */
32853 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET(value) (((value) << 0) & 0x7fffffff)
32854 
32855 /*
32856  * Field : Add or subtract time - addsub
32857  *
32858  * When this bit is set, the time value is subtracted with the contents of the
32859  * update register. When this bit is reset, the time value is added with the
32860  * contents of the update register.
32861  *
32862  * Field Enumeration Values:
32863  *
32864  * Enum | Value | Description
32865  * :-----------------------------------------------------|:------|:----------------------------------
32866  * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD | 0x0 | Add Time Value from update reg
32867  * ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END | 0x1 | Subtract Time Value of update reg
32868  *
32869  * Field Access Macros:
32870  *
32871  */
32872 /*
32873  * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
32874  *
32875  * Add Time Value from update reg
32876  */
32877 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD 0x0
32878 /*
32879  * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
32880  *
32881  * Subtract Time Value of update reg
32882  */
32883 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END 0x1
32884 
32885 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
32886 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_LSB 31
32887 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
32888 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_MSB 31
32889 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
32890 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_WIDTH 1
32891 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
32892 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET_MSK 0x80000000
32893 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
32894 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_CLR_MSK 0x7fffffff
32895 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
32896 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_RESET 0x0
32897 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB field value from a register. */
32898 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_GET(value) (((value) & 0x80000000) >> 31)
32899 /* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value suitable for setting the register. */
32900 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET(value) (((value) << 31) & 0x80000000)
32901 
32902 #ifndef __ASSEMBLY__
32903 /*
32904  * WARNING: The C register and register group struct declarations are provided for
32905  * convenience and illustrative purposes. They should, however, be used with
32906  * caution as the C language standard provides no guarantees about the alignment or
32907  * atomicity of device memory accesses. The recommended practice for writing
32908  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32909  * alt_write_word() functions.
32910  *
32911  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE.
32912  */
32913 struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s
32914 {
32915  uint32_t tsss : 31; /* Timestamp Sub Second */
32916  uint32_t addsub : 1; /* Add or subtract time */
32917 };
32918 
32919 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE. */
32920 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t;
32921 #endif /* __ASSEMBLY__ */
32922 
32923 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register from the beginning of the component. */
32924 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST 0x714
32925 /* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register. */
32926 #define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST))
32927 
32928 /*
32929  * Register : Register 454 (Timestamp Addend Register) - Timestamp_Addend
32930  *
32931  * This register value is used only when the system time is configured for Fine
32932  * Update mode (TSCFUPDT bit in Register 448). This register content is added to a
32933  * 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time
32934  * is updated whenever the accumulator overflows.
32935  *
32936  * Register Layout
32937  *
32938  * Bits | Access | Reset | Description
32939  * :-------|:-------|:------|:--------------------------
32940  * [31:0] | RW | 0x0 | Timestamp Addend Register
32941  *
32942  */
32943 /*
32944  * Field : Timestamp Addend Register - tsar
32945  *
32946  * This field indicates the 32-bit time value to be added to the Accumulator
32947  * register to achieve time synchronization.
32948  *
32949  * Field Access Macros:
32950  *
32951  */
32952 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
32953 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_LSB 0
32954 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
32955 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_MSB 31
32956 /* The width in bits of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
32957 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_WIDTH 32
32958 /* The mask used to set the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
32959 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET_MSK 0xffffffff
32960 /* The mask used to clear the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
32961 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_CLR_MSK 0x00000000
32962 /* The reset value of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
32963 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_RESET 0x0
32964 /* Extracts the ALT_EMAC_GMAC_TS_ADDEND_TSAR field value from a register. */
32965 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_GET(value) (((value) & 0xffffffff) >> 0)
32966 /* Produces a ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value suitable for setting the register. */
32967 #define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET(value) (((value) << 0) & 0xffffffff)
32968 
32969 #ifndef __ASSEMBLY__
32970 /*
32971  * WARNING: The C register and register group struct declarations are provided for
32972  * convenience and illustrative purposes. They should, however, be used with
32973  * caution as the C language standard provides no guarantees about the alignment or
32974  * atomicity of device memory accesses. The recommended practice for writing
32975  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
32976  * alt_write_word() functions.
32977  *
32978  * The struct declaration for register ALT_EMAC_GMAC_TS_ADDEND.
32979  */
32980 struct ALT_EMAC_GMAC_TS_ADDEND_s
32981 {
32982  uint32_t tsar : 32; /* Timestamp Addend Register */
32983 };
32984 
32985 /* The typedef declaration for register ALT_EMAC_GMAC_TS_ADDEND. */
32986 typedef volatile struct ALT_EMAC_GMAC_TS_ADDEND_s ALT_EMAC_GMAC_TS_ADDEND_t;
32987 #endif /* __ASSEMBLY__ */
32988 
32989 /* The byte offset of the ALT_EMAC_GMAC_TS_ADDEND register from the beginning of the component. */
32990 #define ALT_EMAC_GMAC_TS_ADDEND_OFST 0x718
32991 /* The address of the ALT_EMAC_GMAC_TS_ADDEND register. */
32992 #define ALT_EMAC_GMAC_TS_ADDEND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_ADDEND_OFST))
32993 
32994 /*
32995  * Register : Register 455 (Target Time Seconds Register) - Target_Time_Seconds
32996  *
32997  * The Target Time Seconds register, along with Target Time Nanoseconds register,
32998  * is used to schedule an interrupt event (Register 458[1] when Advanced
32999  * Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the
33000  * system time exceeds the value programmed in these registers.
33001  *
33002  * Register Layout
33003  *
33004  * Bits | Access | Reset | Description
33005  * :-------|:-------|:------|:-----------------------------
33006  * [31:0] | RW | 0x0 | Target Time Seconds Register
33007  *
33008  */
33009 /*
33010  * Field : Target Time Seconds Register - tstr
33011  *
33012  * This register stores the time in seconds. When the timestamp value matches or
33013  * exceeds both Target Timestamp registers, then based on Bits [6:5] of Register
33014  * 459 (PPS Control Register), the MAC starts or stops the PPS signal output and
33015  * generates an interrupt (if enabled).
33016  *
33017  * Field Access Macros:
33018  *
33019  */
33020 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
33021 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_LSB 0
33022 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
33023 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_MSB 31
33024 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
33025 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_WIDTH 32
33026 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
33027 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET_MSK 0xffffffff
33028 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
33029 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_CLR_MSK 0x00000000
33030 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
33031 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_RESET 0x0
33032 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR field value from a register. */
33033 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_GET(value) (((value) & 0xffffffff) >> 0)
33034 /* Produces a ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value suitable for setting the register. */
33035 #define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET(value) (((value) << 0) & 0xffffffff)
33036 
33037 #ifndef __ASSEMBLY__
33038 /*
33039  * WARNING: The C register and register group struct declarations are provided for
33040  * convenience and illustrative purposes. They should, however, be used with
33041  * caution as the C language standard provides no guarantees about the alignment or
33042  * atomicity of device memory accesses. The recommended practice for writing
33043  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33044  * alt_write_word() functions.
33045  *
33046  * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS.
33047  */
33048 struct ALT_EMAC_GMAC_TGT_TIME_SECS_s
33049 {
33050  uint32_t tstr : 32; /* Target Time Seconds Register */
33051 };
33052 
33053 /* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS. */
33054 typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_SECS_s ALT_EMAC_GMAC_TGT_TIME_SECS_t;
33055 #endif /* __ASSEMBLY__ */
33056 
33057 /* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_SECS register from the beginning of the component. */
33058 #define ALT_EMAC_GMAC_TGT_TIME_SECS_OFST 0x71c
33059 /* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register. */
33060 #define ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_SECS_OFST))
33061 
33062 /*
33063  * Register : Register 456 (Target Time Nanoseconds Register) - Target_Time_Nanoseconds
33064  *
33065  * Target time
33066  *
33067  * Register Layout
33068  *
33069  * Bits | Access | Reset | Description
33070  * :-------|:-------|:------|:------------------------------
33071  * [30:0] | RW | 0x0 | Target Timestamp Low Register
33072  * [31] | R | 0x0 | Target Time Register Busy
33073  *
33074  */
33075 /*
33076  * Field : Target Timestamp Low Register - ttslo
33077  *
33078  * This register stores the time in (signed) nanoseconds. When the value of the
33079  * timestamp matches the both Target Timestamp registers, then based on the
33080  * TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC
33081  * starts or stops the PPS signal output and generates an interrupt (if enabled).
33082  *
33083  * This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp
33084  * control register. The actual start or stop time of the PPS signal output may
33085  * have an error margin up to one unit of sub-second increment value.
33086  *
33087  * Field Access Macros:
33088  *
33089  */
33090 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
33091 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB 0
33092 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
33093 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB 30
33094 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
33095 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH 31
33096 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
33097 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK 0x7fffffff
33098 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
33099 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK 0x80000000
33100 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
33101 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET 0x0
33102 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO field value from a register. */
33103 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
33104 /* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value suitable for setting the register. */
33105 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET(value) (((value) << 0) & 0x7fffffff)
33106 
33107 /*
33108  * Field : Target Time Register Busy - trgtbusy
33109  *
33110  * The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS
33111  * Control Register) is programmed to 010 or 011. Programming the PPSCMD field to
33112  * 010 or 011, instructs the MAC to synchronize the Target Time Registers to the
33113  * PTP clock domain.
33114  *
33115  * The MAC clears this bit after synchronizing the Target Time Registers to the PTP
33116  * clock domain The application must not update the Target Time Registers when this
33117  * bit is read as 1. Otherwise, the synchronization of the previous programmed time
33118  * gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second
33119  * Output feature is not selected.
33120  *
33121  * Field Access Macros:
33122  *
33123  */
33124 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
33125 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB 31
33126 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
33127 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB 31
33128 /* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
33129 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH 1
33130 /* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
33131 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK 0x80000000
33132 /* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
33133 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK 0x7fffffff
33134 /* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
33135 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET 0x0
33136 /* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY field value from a register. */
33137 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET(value) (((value) & 0x80000000) >> 31)
33138 /* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value suitable for setting the register. */
33139 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET(value) (((value) << 31) & 0x80000000)
33140 
33141 #ifndef __ASSEMBLY__
33142 /*
33143  * WARNING: The C register and register group struct declarations are provided for
33144  * convenience and illustrative purposes. They should, however, be used with
33145  * caution as the C language standard provides no guarantees about the alignment or
33146  * atomicity of device memory accesses. The recommended practice for writing
33147  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33148  * alt_write_word() functions.
33149  *
33150  * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS.
33151  */
33152 struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s
33153 {
33154  uint32_t ttslo : 31; /* Target Timestamp Low Register */
33155  const uint32_t trgtbusy : 1; /* Target Time Register Busy */
33156 };
33157 
33158 /* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS. */
33159 typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t;
33160 #endif /* __ASSEMBLY__ */
33161 
33162 /* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register from the beginning of the component. */
33163 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST 0x720
33164 /* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register. */
33165 #define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST))
33166 
33167 /*
33168  * Register : Register 457 (System Time - Higher Word Seconds Register) - System_Time_Higher_Word_Seconds
33169  *
33170  * System time higher word
33171  *
33172  * Register Layout
33173  *
33174  * Bits | Access | Reset | Description
33175  * :--------|:-------|:------|:-------------------------------
33176  * [15:0] | RW | 0x0 | Timestamp Higher Word Register
33177  * [31:16] | ??? | 0x0 | *UNDEFINED*
33178  *
33179  */
33180 /*
33181  * Field : Timestamp Higher Word Register - tshwr
33182  *
33183  * This field contains the most significant 16-bits of the timestamp seconds value.
33184  * The register is directly written to initialize the value. This register is
33185  * incremented when there is an overflow from the 32-bits of the System Time -
33186  * Seconds register.
33187  *
33188  * Field Access Macros:
33189  *
33190  */
33191 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
33192 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_LSB 0
33193 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
33194 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_MSB 15
33195 /* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
33196 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_WIDTH 16
33197 /* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
33198 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET_MSK 0x0000ffff
33199 /* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
33200 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_CLR_MSK 0xffff0000
33201 /* The reset value of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
33202 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_RESET 0x0
33203 /* Extracts the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR field value from a register. */
33204 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_GET(value) (((value) & 0x0000ffff) >> 0)
33205 /* Produces a ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value suitable for setting the register. */
33206 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET(value) (((value) << 0) & 0x0000ffff)
33207 
33208 #ifndef __ASSEMBLY__
33209 /*
33210  * WARNING: The C register and register group struct declarations are provided for
33211  * convenience and illustrative purposes. They should, however, be used with
33212  * caution as the C language standard provides no guarantees about the alignment or
33213  * atomicity of device memory accesses. The recommended practice for writing
33214  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33215  * alt_write_word() functions.
33216  *
33217  * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS.
33218  */
33219 struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s
33220 {
33221  uint32_t tshwr : 16; /* Timestamp Higher Word Register */
33222  uint32_t : 16; /* *UNDEFINED* */
33223 };
33224 
33225 /* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS. */
33226 typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t;
33227 #endif /* __ASSEMBLY__ */
33228 
33229 /* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register from the beginning of the component. */
33230 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST 0x724
33231 /* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register. */
33232 #define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST))
33233 
33234 /*
33235  * Register : Register 458 (Timestamp Status Register) - Timestamp_Status
33236  *
33237  * Timestamp status. All bits except Bits[27:25] get cleared when the host reads
33238  * this register.
33239  *
33240  * Register Layout
33241  *
33242  * Bits | Access | Reset | Description
33243  * :--------|:-------|:------|:------------------------------------------------
33244  * [0] | R | 0x0 | Timestamp Seconds Overflow
33245  * [1] | R | 0x0 | Timestamp Target Time Reached
33246  * [2] | R | 0x0 | Auxiliary Timestamp Trigger Snapshot
33247  * [3] | R | 0x0 | Timestamp Target Time Error
33248  * [15:4] | ??? | 0x0 | *UNDEFINED*
33249  * [19:16] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Identifier
33250  * [23:20] | ??? | 0x0 | *UNDEFINED*
33251  * [24] | R | 0x0 | Auxiliary Timestamp Snapshot Trigger Missed
33252  * [29:25] | R | 0x0 | Number of Auxiliary Timestamp Snapshots
33253  * [31:30] | ??? | 0x0 | *UNDEFINED*
33254  *
33255  */
33256 /*
33257  * Field : Timestamp Seconds Overflow - tssovf
33258  *
33259  * When set, this bit indicates that the seconds value of the timestamp (when
33260  * supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
33261  *
33262  * Field Enumeration Values:
33263  *
33264  * Enum | Value | Description
33265  * :-----------------------------------|:------|:-----------------
33266  * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST | 0x0 | No Overflow
33267  * ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET | 0x1 | Seconds Overflow
33268  *
33269  * Field Access Macros:
33270  *
33271  */
33272 /*
33273  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
33274  *
33275  * No Overflow
33276  */
33277 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST 0x0
33278 /*
33279  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
33280  *
33281  * Seconds Overflow
33282  */
33283 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET 0x1
33284 
33285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
33286 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_LSB 0
33287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
33288 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_MSB 0
33289 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
33290 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_WIDTH 1
33291 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
33292 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET_MSK 0x00000001
33293 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
33294 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_CLR_MSK 0xfffffffe
33295 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
33296 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_RESET 0x0
33297 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSSOVF field value from a register. */
33298 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_GET(value) (((value) & 0x00000001) >> 0)
33299 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value suitable for setting the register. */
33300 #define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET(value) (((value) << 0) & 0x00000001)
33301 
33302 /*
33303  * Field : Timestamp Target Time Reached - tstargt
33304  *
33305  * When set, this bit indicates that the value of system time is greater or equal
33306  * to the value specified in the Register 455 (Target Time Seconds Register) and
33307  * Register 456 (Target Time Nanoseconds Register).
33308  *
33309  * Field Enumeration Values:
33310  *
33311  * Enum | Value | Description
33312  * :------------------------------------|:------|:------------------------------------
33313  * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST | 0x0 | System Time
33314  * ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET | 0x1 | System Time is >= Reg455 and Reg456
33315  *
33316  * Field Access Macros:
33317  *
33318  */
33319 /*
33320  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
33321  *
33322  * System Time
33323  */
33324 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST 0x0
33325 /*
33326  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
33327  *
33328  * System Time is >= Reg455 and Reg456
33329  */
33330 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET 0x1
33331 
33332 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
33333 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_LSB 1
33334 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
33335 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_MSB 1
33336 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
33337 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_WIDTH 1
33338 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
33339 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET_MSK 0x00000002
33340 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
33341 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_CLR_MSK 0xfffffffd
33342 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
33343 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_RESET 0x0
33344 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTARGT field value from a register. */
33345 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_GET(value) (((value) & 0x00000002) >> 1)
33346 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value suitable for setting the register. */
33347 #define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET(value) (((value) << 1) & 0x00000002)
33348 
33349 /*
33350  * Field : Auxiliary Timestamp Trigger Snapshot - auxtstrig
33351  *
33352  * This bit is set high when the auxiliary snapshot is written to the FIFO.
33353  *
33354  * Field Enumeration Values:
33355  *
33356  * Enum | Value | Description
33357  * :--------------------------------------|:------|:------------------------------------
33358  * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST | 0x0 | System Time
33359  * ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET | 0x1 | System Time is >= Reg455 and Reg456
33360  *
33361  * Field Access Macros:
33362  *
33363  */
33364 /*
33365  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
33366  *
33367  * System Time
33368  */
33369 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST 0x0
33370 /*
33371  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
33372  *
33373  * System Time is >= Reg455 and Reg456
33374  */
33375 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET 0x1
33376 
33377 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
33378 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_LSB 2
33379 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
33380 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_MSB 2
33381 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
33382 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_WIDTH 1
33383 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
33384 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET_MSK 0x00000004
33385 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
33386 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_CLR_MSK 0xfffffffb
33387 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
33388 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_RESET 0x0
33389 /* Extracts the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG field value from a register. */
33390 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_GET(value) (((value) & 0x00000004) >> 2)
33391 /* Produces a ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value suitable for setting the register. */
33392 #define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET(value) (((value) << 2) & 0x00000004)
33393 
33394 /*
33395  * Field : Timestamp Target Time Error - tstrgterr
33396  *
33397  * This bit is set when the target time, being programmed in Target Time Registers,
33398  * is already elapsed. This bit is cleared when read by the application.
33399  *
33400  * Field Enumeration Values:
33401  *
33402  * Enum | Value | Description
33403  * :--------------------------------------|:------|:---------------------------------------
33404  * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST | 0x0 | When Read resets
33405  * ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET | 0x1 | Target Time Elapsed -Reg455 and Reg456
33406  *
33407  * Field Access Macros:
33408  *
33409  */
33410 /*
33411  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
33412  *
33413  * When Read resets
33414  */
33415 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST 0x0
33416 /*
33417  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
33418  *
33419  * Target Time Elapsed -Reg455 and Reg456
33420  */
33421 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET 0x1
33422 
33423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
33424 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_LSB 3
33425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
33426 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_MSB 3
33427 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
33428 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_WIDTH 1
33429 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
33430 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET_MSK 0x00000008
33431 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
33432 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_CLR_MSK 0xfffffff7
33433 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
33434 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_RESET 0x0
33435 /* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR field value from a register. */
33436 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_GET(value) (((value) & 0x00000008) >> 3)
33437 /* Produces a ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value suitable for setting the register. */
33438 #define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET(value) (((value) << 3) & 0x00000008)
33439 
33440 /*
33441  * Field : Auxiliary Timestamp Snapshot Trigger Identifier - atsstn
33442  *
33443  * These bits identify the Auxiliary trigger inputs for which the timestamp
33444  * available in the Auxiliary Snapshot Register is applicable. When more than one
33445  * bit is set at the same time, it means that corresponding auxiliary triggers were
33446  * sampled at the same clock. These bits are applicable only if the number of
33447  * Auxiliary snapshots is more than one. One bit is assigned for each trigger as
33448  * shown in the following list:
33449  *
33450  * * Bit 16: Auxiliary trigger 0
33451  *
33452  * * Bit 17: Auxiliary trigger 1
33453  *
33454  * * Bit 18: Auxiliary trigger 2
33455  *
33456  * * Bit 19: Auxiliary trigger 3
33457  *
33458  * The software can read this register to find the triggers that are set when the
33459  * timestamp is taken.
33460  *
33461  * Field Access Macros:
33462  *
33463  */
33464 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
33465 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_LSB 16
33466 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
33467 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_MSB 19
33468 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
33469 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_WIDTH 4
33470 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
33471 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET_MSK 0x000f0000
33472 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
33473 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_CLR_MSK 0xfff0ffff
33474 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
33475 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_RESET 0x0
33476 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTN field value from a register. */
33477 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_GET(value) (((value) & 0x000f0000) >> 16)
33478 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value suitable for setting the register. */
33479 #define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET(value) (((value) << 16) & 0x000f0000)
33480 
33481 /*
33482  * Field : Auxiliary Timestamp Snapshot Trigger Missed - atsstm
33483  *
33484  * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external
33485  * trigger was set. This indicates that the latest snapshot is not stored in the
33486  * FIFO.
33487  *
33488  * Field Enumeration Values:
33489  *
33490  * Enum | Value | Description
33491  * :---------------------------------------|:------|:----------------------------
33492  * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL | 0x0 | Not Active
33493  * ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL | 0x1 | Aux timestamp snapshot full
33494  *
33495  * Field Access Macros:
33496  *
33497  */
33498 /*
33499  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
33500  *
33501  * Not Active
33502  */
33503 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL 0x0
33504 /*
33505  * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
33506  *
33507  * Aux timestamp snapshot full
33508  */
33509 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL 0x1
33510 
33511 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
33512 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_LSB 24
33513 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
33514 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_MSB 24
33515 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
33516 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_WIDTH 1
33517 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
33518 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET_MSK 0x01000000
33519 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
33520 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_CLR_MSK 0xfeffffff
33521 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
33522 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_RESET 0x0
33523 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTM field value from a register. */
33524 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_GET(value) (((value) & 0x01000000) >> 24)
33525 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value suitable for setting the register. */
33526 #define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET(value) (((value) << 24) & 0x01000000)
33527 
33528 /*
33529  * Field : Number of Auxiliary Timestamp Snapshots - atsns
33530  *
33531  * This field indicates the number of Snapshots available in the FIFO. A value of
33532  * 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO
33533  * is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO
33534  * clear bit is set.
33535  *
33536  * Field Access Macros:
33537  *
33538  */
33539 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
33540 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_LSB 25
33541 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
33542 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_MSB 29
33543 /* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
33544 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_WIDTH 5
33545 /* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
33546 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET_MSK 0x3e000000
33547 /* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
33548 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_CLR_MSK 0xc1ffffff
33549 /* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
33550 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_RESET 0x0
33551 /* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSNS field value from a register. */
33552 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_GET(value) (((value) & 0x3e000000) >> 25)
33553 /* Produces a ALT_EMAC_GMAC_TS_STAT_ATSNS register field value suitable for setting the register. */
33554 #define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET(value) (((value) << 25) & 0x3e000000)
33555 
33556 #ifndef __ASSEMBLY__
33557 /*
33558  * WARNING: The C register and register group struct declarations are provided for
33559  * convenience and illustrative purposes. They should, however, be used with
33560  * caution as the C language standard provides no guarantees about the alignment or
33561  * atomicity of device memory accesses. The recommended practice for writing
33562  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33563  * alt_write_word() functions.
33564  *
33565  * The struct declaration for register ALT_EMAC_GMAC_TS_STAT.
33566  */
33567 struct ALT_EMAC_GMAC_TS_STAT_s
33568 {
33569  const uint32_t tssovf : 1; /* Timestamp Seconds Overflow */
33570  const uint32_t tstargt : 1; /* Timestamp Target Time Reached */
33571  const uint32_t auxtstrig : 1; /* Auxiliary Timestamp Trigger Snapshot */
33572  const uint32_t tstrgterr : 1; /* Timestamp Target Time Error */
33573  uint32_t : 12; /* *UNDEFINED* */
33574  const uint32_t atsstn : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
33575  uint32_t : 4; /* *UNDEFINED* */
33576  const uint32_t atsstm : 1; /* Auxiliary Timestamp Snapshot Trigger Missed */
33577  const uint32_t atsns : 5; /* Number of Auxiliary Timestamp Snapshots */
33578  uint32_t : 2; /* *UNDEFINED* */
33579 };
33580 
33581 /* The typedef declaration for register ALT_EMAC_GMAC_TS_STAT. */
33582 typedef volatile struct ALT_EMAC_GMAC_TS_STAT_s ALT_EMAC_GMAC_TS_STAT_t;
33583 #endif /* __ASSEMBLY__ */
33584 
33585 /* The byte offset of the ALT_EMAC_GMAC_TS_STAT register from the beginning of the component. */
33586 #define ALT_EMAC_GMAC_TS_STAT_OFST 0x728
33587 /* The address of the ALT_EMAC_GMAC_TS_STAT register. */
33588 #define ALT_EMAC_GMAC_TS_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_STAT_OFST))
33589 
33590 /*
33591  * Register : Register 459 (PPS Control Register) - PPS_Control
33592  *
33593  * Controls timestamp Pulse-Per-Second output
33594  *
33595  * Register Layout
33596  *
33597  * Bits | Access | Reset | Description
33598  * :-------|:-------|:------|:------------------------------------------
33599  * [3:0] | RW | 0x0 | PPSCTRL0 or PPSCMD0
33600  * [4] | RW | 0x0 | Flexible PPS Output Mode Enable
33601  * [6:5] | RW | 0x0 | Target Time Register Mode for PPS0 Output
33602  * [31:7] | ??? | 0x0 | *UNDEFINED*
33603  *
33604  */
33605 /*
33606  * Field : PPSCTRL0 or PPSCMD0 - ppsctrl_ppscmd
33607  *
33608  * PPSCTRL0: PPS0 Output Frequency Control
33609  *
33610  * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The
33611  * default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width
33612  * clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a
33613  * generated clock of following frequencies:
33614  *
33615  * * 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz.
33616  *
33617  * * 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz.
33618  *
33619  * * 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz.
33620  *
33621  * * 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz.
33622  *
33623  * * ...
33624  *
33625  * * 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384
33626  * KHz.
33627  *
33628  * Note:
33629  *
33630  * In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50
33631  * percent with these frequencies.
33632  *
33633  * In the digital rollover mode, the PPS output frequency is an average number. The
33634  * actual clock is of different frequency that gets synchronized every second. For
33635  * example:
33636  *
33637  * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high
33638  * period of 463 ms
33639  *
33640  * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of:
33641  *
33642  * * One clock of 50 percent duty cycle and 537 ms period
33643  *
33644  * * Second clock of 463 ms period (268 ms low and 195 ms high)
33645  *
33646  * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of:
33647  *
33648  * * Three clocks of 50 percent duty cycle and 268 ms period
33649  *
33650  * * Fourth clock of 195 ms period (134 ms low and 61 ms high)
33651  *
33652  * This behavior is because of the non-linear toggling of bits in the digital
33653  * rollover mode in Register 451 (System Time - Nanoseconds Register).
33654  *
33655  * Flexible PPS0 Output (ptp_pps_o[0]) Control
33656  *
33657  * Programming these bits with a non-zero value instructs the MAC to initiate an
33658  * event. Once the command is transferred or synchronized to the PTP clock domain,
33659  * these bits get cleared automatically. The Software should ensure that these bits
33660  * are programmed only when they are all-zero. The following list describes the
33661  * values of PPSCMD0:
33662  *
33663  * - 0000: No Command
33664  *
33665  * - 0001: START Single Pulse
33666  *
33667  * This command generates single pulse rising at the start point defined in Target
33668  * Time Registers (register 455 and 456) and of a duration defined in the PPS0
33669  * Width Register.
33670  *
33671  * - 0010: START Pulse Train
33672  *
33673  * This command generates the train of pulses rising at the start point defined in
33674  * the Target Time Registers and of a duration defined in the PPS0 Width Register
33675  * and repeated at interval defined in the PPS Interval Register. By default, the
33676  * PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or
33677  * 'STOP Pulse Train immediately' commands.
33678  *
33679  * - 0011: Cancel START
33680  *
33681  * This command cancels the START Single Pulse and START Pulse Train commands if
33682  * the system time has not crossed the programmed start time.
33683  *
33684  * - 0100: STOP Pulse train at time
33685  *
33686  * This command stops the train of pulses initiated by the START Pulse Train
33687  * command (PPSCMD = 0010) after the time programmed in the Target Time registers
33688  * elapses.
33689  *
33690  * - 0101: STOP Pulse Train immediately
33691  *
33692  * This command immediately stops the train of pulses initiated by the START Pulse
33693  * Train command (PPSCMD = 0010).
33694  *
33695  * - 0110: Cancel STOP Pulse train
33696  *
33697  * This command cancels the STOP pulse train at time command if the programmed stop
33698  * time has not elapsed. The PPS pulse train becomes free-running on the successful
33699  * execution of this command.
33700  *
33701  * - 0111-1111: Reserved
33702  *
33703  * Field Access Macros:
33704  *
33705  */
33706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
33707 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB 0
33708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
33709 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB 3
33710 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
33711 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH 4
33712 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
33713 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK 0x0000000f
33714 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
33715 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK 0xfffffff0
33716 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
33717 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET 0x0
33718 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD field value from a register. */
33719 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET(value) (((value) & 0x0000000f) >> 0)
33720 /* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value suitable for setting the register. */
33721 #define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET(value) (((value) << 0) & 0x0000000f)
33722 
33723 /*
33724  * Field : Flexible PPS Output Mode Enable - ppsen0
33725  *
33726  * When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set
33727  * high, Bits[3:0] function as PPSCMD.
33728  *
33729  * Field Enumeration Values:
33730  *
33731  * Enum | Value | Description
33732  * :--------------------------------------|:------|:-------------------------------
33733  * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL | 0x0 | Bits[3:0] function as ppsctrl0
33734  * ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD | 0x1 | Bits[3:0] function as ppscmd
33735  *
33736  * Field Access Macros:
33737  *
33738  */
33739 /*
33740  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
33741  *
33742  * Bits[3:0] function as ppsctrl0
33743  */
33744 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL 0x0
33745 /*
33746  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
33747  *
33748  * Bits[3:0] function as ppscmd
33749  */
33750 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD 0x1
33751 
33752 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
33753 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB 4
33754 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
33755 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB 4
33756 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
33757 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH 1
33758 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
33759 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK 0x00000010
33760 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
33761 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK 0xffffffef
33762 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
33763 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET 0x0
33764 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 field value from a register. */
33765 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET(value) (((value) & 0x00000010) >> 4)
33766 /* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value suitable for setting the register. */
33767 #define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET(value) (((value) << 4) & 0x00000010)
33768 
33769 /*
33770  * Field : Target Time Register Mode for PPS0 Output - trgtmodsel0
33771  *
33772  * This field indicates the Target Time registers (register 455 and 456) mode for
33773  * PPS0 output signal
33774  *
33775  * Field Enumeration Values:
33776  *
33777  * Enum | Value | Description
33778  * :--------------------------------------------------|:------|:---------------------------------------------
33779  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY | 0x0 | Target Time regs generate interrupt event.
33780  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 | 0x2 | Target Time gen. interr event and sig pps0
33781  * ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER | 0x3 | Target Time No inter just start and stop sig
33782  * : | | pps0
33783  *
33784  * Field Access Macros:
33785  *
33786  */
33787 /*
33788  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
33789  *
33790  * Target Time regs generate interrupt event.
33791  */
33792 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY 0x0
33793 /*
33794  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
33795  *
33796  * Target Time gen. interr event and sig pps0
33797  */
33798 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 0x2
33799 /*
33800  * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
33801  *
33802  * Target Time No inter just start and stop sig pps0
33803  */
33804 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER 0x3
33805 
33806 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
33807 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB 5
33808 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
33809 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB 6
33810 /* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
33811 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH 2
33812 /* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
33813 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK 0x00000060
33814 /* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
33815 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK 0xffffff9f
33816 /* The reset value of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
33817 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET 0x0
33818 /* Extracts the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 field value from a register. */
33819 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET(value) (((value) & 0x00000060) >> 5)
33820 /* Produces a ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value suitable for setting the register. */
33821 #define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET(value) (((value) << 5) & 0x00000060)
33822 
33823 #ifndef __ASSEMBLY__
33824 /*
33825  * WARNING: The C register and register group struct declarations are provided for
33826  * convenience and illustrative purposes. They should, however, be used with
33827  * caution as the C language standard provides no guarantees about the alignment or
33828  * atomicity of device memory accesses. The recommended practice for writing
33829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33830  * alt_write_word() functions.
33831  *
33832  * The struct declaration for register ALT_EMAC_GMAC_PPS_CTL.
33833  */
33834 struct ALT_EMAC_GMAC_PPS_CTL_s
33835 {
33836  uint32_t ppsctrl_ppscmd : 4; /* PPSCTRL0 or PPSCMD0 */
33837  uint32_t ppsen0 : 1; /* Flexible PPS Output Mode Enable */
33838  uint32_t trgtmodsel0 : 2; /* Target Time Register Mode for PPS0 Output */
33839  uint32_t : 25; /* *UNDEFINED* */
33840 };
33841 
33842 /* The typedef declaration for register ALT_EMAC_GMAC_PPS_CTL. */
33843 typedef volatile struct ALT_EMAC_GMAC_PPS_CTL_s ALT_EMAC_GMAC_PPS_CTL_t;
33844 #endif /* __ASSEMBLY__ */
33845 
33846 /* The byte offset of the ALT_EMAC_GMAC_PPS_CTL register from the beginning of the component. */
33847 #define ALT_EMAC_GMAC_PPS_CTL_OFST 0x72c
33848 /* The address of the ALT_EMAC_GMAC_PPS_CTL register. */
33849 #define ALT_EMAC_GMAC_PPS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST))
33850 
33851 /*
33852  * Register : Register 460 (Auxiliary Timestamp - Nanoseconds Register) - Auxiliary_Timestamp_Nanoseconds
33853  *
33854  * This register, along with Register 461 (Auxiliary Timestamp Seconds Register),
33855  * gives the 64-bit timestamp stored as auxiliary snapshot. The two registers
33856  * together form the read port of a 64-bit wide FIFO with a depth of 16. Multiple
33857  * snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status
33858  * register indicate the fill-level of this FIFO. The top of the FIFO is removed
33859  * only when the last byte of Register 461 (Auxiliary Timestamp - Seconds Register)
33860  * is read. In the little-endian mode, this means when Bits[31:24] are read. In
33861  * big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461
33862  * (Auxiliary Timestamp - Seconds Register).
33863  *
33864  * Register Layout
33865  *
33866  * Bits | Access | Reset | Description
33867  * :-------|:-------|:------|:--------------------------------------
33868  * [30:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO
33869  * [31] | ??? | 0x0 | *UNDEFINED*
33870  *
33871  */
33872 /*
33873  * Field : auxtslo
33874  *
33875  * Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp.
33876  *
33877  * Field Access Macros:
33878  *
33879  */
33880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
33881 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_LSB 0
33882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
33883 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_MSB 30
33884 /* The width in bits of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
33885 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_WIDTH 31
33886 /* The mask used to set the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
33887 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET_MSK 0x7fffffff
33888 /* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
33889 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_CLR_MSK 0x80000000
33890 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
33891 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_RESET 0x0
33892 /* Extracts the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO field value from a register. */
33893 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
33894 /* Produces a ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value suitable for setting the register. */
33895 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET(value) (((value) << 0) & 0x7fffffff)
33896 
33897 #ifndef __ASSEMBLY__
33898 /*
33899  * WARNING: The C register and register group struct declarations are provided for
33900  * convenience and illustrative purposes. They should, however, be used with
33901  * caution as the C language standard provides no guarantees about the alignment or
33902  * atomicity of device memory accesses. The recommended practice for writing
33903  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33904  * alt_write_word() functions.
33905  *
33906  * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS.
33907  */
33908 struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s
33909 {
33910  const uint32_t auxtslo : 31; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO */
33911  uint32_t : 1; /* *UNDEFINED* */
33912 };
33913 
33914 /* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS. */
33915 typedef volatile struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s ALT_EMAC_GMAC_AUX_TS_NANOSECS_t;
33916 #endif /* __ASSEMBLY__ */
33917 
33918 /* The byte offset of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register from the beginning of the component. */
33919 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST 0x730
33920 /* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register. */
33921 #define ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST))
33922 
33923 /*
33924  * Register : Register 461 (Auxiliary Timestamp - Seconds Register) - Auxiliary_Timestamp_Seconds
33925  *
33926  * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
33927  *
33928  * Register Layout
33929  *
33930  * Bits | Access | Reset | Description
33931  * :-------|:-------|:------|:----------------------------------
33932  * [31:0] | R | 0x0 | ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI
33933  *
33934  */
33935 /*
33936  * Field : auxtshi
33937  *
33938  * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
33939  *
33940  * Field Access Macros:
33941  *
33942  */
33943 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
33944 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_LSB 0
33945 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
33946 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_MSB 31
33947 /* The width in bits of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
33948 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_WIDTH 32
33949 /* The mask used to set the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
33950 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET_MSK 0xffffffff
33951 /* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
33952 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_CLR_MSK 0x00000000
33953 /* The reset value of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
33954 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_RESET 0x0
33955 /* Extracts the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI field value from a register. */
33956 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_GET(value) (((value) & 0xffffffff) >> 0)
33957 /* Produces a ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value suitable for setting the register. */
33958 #define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET(value) (((value) << 0) & 0xffffffff)
33959 
33960 #ifndef __ASSEMBLY__
33961 /*
33962  * WARNING: The C register and register group struct declarations are provided for
33963  * convenience and illustrative purposes. They should, however, be used with
33964  * caution as the C language standard provides no guarantees about the alignment or
33965  * atomicity of device memory accesses. The recommended practice for writing
33966  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
33967  * alt_write_word() functions.
33968  *
33969  * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_SECS.
33970  */
33971 struct ALT_EMAC_GMAC_AUX_TS_SECS_s
33972 {
33973  const uint32_t auxtshi : 32; /* ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI */
33974 };
33975 
33976 /* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_SECS. */
33977 typedef volatile struct ALT_EMAC_GMAC_AUX_TS_SECS_s ALT_EMAC_GMAC_AUX_TS_SECS_t;
33978 #endif /* __ASSEMBLY__ */
33979 
33980 /* The byte offset of the ALT_EMAC_GMAC_AUX_TS_SECS register from the beginning of the component. */
33981 #define ALT_EMAC_GMAC_AUX_TS_SECS_OFST 0x734
33982 /* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register. */
33983 #define ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_SECS_OFST))
33984 
33985 /*
33986  * Register : Register 472 (PPS0 Interval Register) - PPS0_Interval
33987  *
33988  * The PPS0 Interval register contains the number of units of sub-second increment
33989  * value between the rising edges of PPS0 signal output (ptp_pps_o[0]).
33990  *
33991  * Register Layout
33992  *
33993  * Bits | Access | Reset | Description
33994  * :-------|:-------|:------|:----------------------------
33995  * [31:0] | RW | 0x0 | PPS0 Output Signal Interval
33996  *
33997  */
33998 /*
33999  * Field : PPS0 Output Signal Interval - ppsint
34000  *
34001  * These bits store the interval between the rising edges of PPS0 signal output in
34002  * terms of units of sub-second increment value.
34003  *
34004  * You need to program one value less than the required interval. For example, if
34005  * the PTP reference clock is 50 MHz (period of 20ns), and desired interval between
34006  * rising edges of PPS0 signal output is 100ns (that is, five units of sub-second
34007  * increment value), then you should program value 4 (5 -1) in this register.
34008  *
34009  * Field Access Macros:
34010  *
34011  */
34012 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
34013 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB 0
34014 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
34015 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB 31
34016 /* The width in bits of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
34017 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH 32
34018 /* The mask used to set the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
34019 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK 0xffffffff
34020 /* The mask used to clear the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
34021 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK 0x00000000
34022 /* The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
34023 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET 0x0
34024 /* Extracts the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT field value from a register. */
34025 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET(value) (((value) & 0xffffffff) >> 0)
34026 /* Produces a ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value suitable for setting the register. */
34027 #define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET(value) (((value) << 0) & 0xffffffff)
34028 
34029 #ifndef __ASSEMBLY__
34030 /*
34031  * WARNING: The C register and register group struct declarations are provided for
34032  * convenience and illustrative purposes. They should, however, be used with
34033  * caution as the C language standard provides no guarantees about the alignment or
34034  * atomicity of device memory accesses. The recommended practice for writing
34035  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34036  * alt_write_word() functions.
34037  *
34038  * The struct declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL.
34039  */
34040 struct ALT_EMAC_GMAC_PPS0_INTERVAL_s
34041 {
34042  uint32_t ppsint : 32; /* PPS0 Output Signal Interval */
34043 };
34044 
34045 /* The typedef declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL. */
34046 typedef volatile struct ALT_EMAC_GMAC_PPS0_INTERVAL_s ALT_EMAC_GMAC_PPS0_INTERVAL_t;
34047 #endif /* __ASSEMBLY__ */
34048 
34049 /* The byte offset of the ALT_EMAC_GMAC_PPS0_INTERVAL register from the beginning of the component. */
34050 #define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST 0x760
34051 /* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register. */
34052 #define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST))
34053 
34054 /*
34055  * Register : Register 473 (PPS0 Width Register) - PPS0_Width
34056  *
34057  * The PPS0 Width register contains the number of units of sub-second increment
34058  * value between the rising and corresponding falling edges of the PPS0 signal
34059  * output (ptp_pps_o[0]).
34060  *
34061  * Register Layout
34062  *
34063  * Bits | Access | Reset | Description
34064  * :-------|:-------|:------|:-------------------------
34065  * [31:0] | RW | 0x0 | PPS0 Output Signal Width
34066  *
34067  */
34068 /*
34069  * Field : PPS0 Output Signal Width - ppswidth
34070  *
34071  * These bits store the width between the rising edge and corresponding falling
34072  * edge of the PPS0 signal output in terms of units of sub-second increment value.
34073  *
34074  * You need to program one value less than the required interval. For example, if
34075  * PTP reference clock is 50 MHz (period of 20ns), and desired width between the
34076  * rising and corresponding falling edges of PPS0 signal output is 80ns (that is,
34077  * four units of sub-second increment value), then you should program value 3 (4-1)
34078  * in this register.
34079  *
34080  * Note:
34081  *
34082  * The value programmed in this register must be lesser than the value programmed
34083  * in Register 472 (PPS0 Interval Register).
34084  *
34085  * Field Access Macros:
34086  *
34087  */
34088 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
34089 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_LSB 0
34090 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
34091 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_MSB 31
34092 /* The width in bits of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
34093 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_WIDTH 32
34094 /* The mask used to set the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
34095 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET_MSK 0xffffffff
34096 /* The mask used to clear the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
34097 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_CLR_MSK 0x00000000
34098 /* The reset value of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
34099 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_RESET 0x0
34100 /* Extracts the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH field value from a register. */
34101 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_GET(value) (((value) & 0xffffffff) >> 0)
34102 /* Produces a ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value suitable for setting the register. */
34103 #define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET(value) (((value) << 0) & 0xffffffff)
34104 
34105 #ifndef __ASSEMBLY__
34106 /*
34107  * WARNING: The C register and register group struct declarations are provided for
34108  * convenience and illustrative purposes. They should, however, be used with
34109  * caution as the C language standard provides no guarantees about the alignment or
34110  * atomicity of device memory accesses. The recommended practice for writing
34111  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34112  * alt_write_word() functions.
34113  *
34114  * The struct declaration for register ALT_EMAC_GMAC_PPS0_WIDTH.
34115  */
34116 struct ALT_EMAC_GMAC_PPS0_WIDTH_s
34117 {
34118  uint32_t ppswidth : 32; /* PPS0 Output Signal Width */
34119 };
34120 
34121 /* The typedef declaration for register ALT_EMAC_GMAC_PPS0_WIDTH. */
34122 typedef volatile struct ALT_EMAC_GMAC_PPS0_WIDTH_s ALT_EMAC_GMAC_PPS0_WIDTH_t;
34123 #endif /* __ASSEMBLY__ */
34124 
34125 /* The byte offset of the ALT_EMAC_GMAC_PPS0_WIDTH register from the beginning of the component. */
34126 #define ALT_EMAC_GMAC_PPS0_WIDTH_OFST 0x764
34127 /* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register. */
34128 #define ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_WIDTH_OFST))
34129 
34130 /*
34131  * Register : Register 512 (MAC Address16 High Register) - MAC_Address16_High
34132  *
34133  * The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC
34134  * address of the station. Because the MAC address registers are configured to be
34135  * double-synchronized to the (G)MII clock domains, the synchronization is
34136  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
34137  * endian mode) of the MAC Address16 Low Register are written. For proper
34138  * synchronization updates, the consecutive writes to this Address Low Register
34139  * should be performed after at least four clock cycles in the destination clock
34140  * domain.
34141  *
34142  * Note that all MAC Address High registers (except MAC Address0 High) have the
34143  * same format.
34144  *
34145  * Register Layout
34146  *
34147  * Bits | Access | Reset | Description
34148  * :--------|:-------|:-------|:----------------------
34149  * [15:0] | RW | 0xffff | MAC Address16 [47:32]
34150  * [23:16] | ??? | 0x0 | *UNDEFINED*
34151  * [24] | RW | 0x0 | Mask Byte Control
34152  * [25] | RW | 0x0 | Mask Byte Control
34153  * [26] | RW | 0x0 | Mask Byte Control
34154  * [27] | RW | 0x0 | Mask Byte Control
34155  * [28] | RW | 0x0 | Mask Byte Control
34156  * [29] | RW | 0x0 | Mask Byte Control
34157  * [30] | RW | 0x0 | Source Address
34158  * [31] | RW | 0x0 | Address Enable
34159  *
34160  */
34161 /*
34162  * Field : MAC Address16 [47:32] - addrhi
34163  *
34164  * This field contains the upper 16 bits (47:32) of the 17th 6-byte MAC address.
34165  *
34166  * Field Access Macros:
34167  *
34168  */
34169 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
34170 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_LSB 0
34171 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
34172 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_MSB 15
34173 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
34174 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_WIDTH 16
34175 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
34176 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET_MSK 0x0000ffff
34177 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
34178 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_CLR_MSK 0xffff0000
34179 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
34180 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_RESET 0xffff
34181 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI field value from a register. */
34182 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
34183 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value suitable for setting the register. */
34184 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
34185 
34186 /*
34187  * Field : Mask Byte Control - mbc_0
34188  *
34189  * This array of bits are mask control bits for comparison of each of the MAC
34190  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34191  * received DA or SA with the contents of MAC Address16 high and low registers.
34192  * Each bit controls the masking of the bytes. You can filter a group of addresses
34193  * (known as group address filtering) by masking one or more bytes of the address.
34194  *
34195  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34196  *
34197  * Field Enumeration Values:
34198  *
34199  * Enum | Value | Description
34200  * :----------------------------------------------|:------|:------------------------------------
34201  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34202  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34203  *
34204  * Field Access Macros:
34205  *
34206  */
34207 /*
34208  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
34209  *
34210  * Byte is unmasked (i.e. is compared)
34211  */
34212 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED 0x0
34213 /*
34214  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
34215  *
34216  * Byte is masked (i.e. not compared)
34217  */
34218 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED 0x1
34219 
34220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
34221 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_LSB 24
34222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
34223 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_MSB 24
34224 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
34225 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_WIDTH 1
34226 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
34227 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET_MSK 0x01000000
34228 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
34229 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_CLR_MSK 0xfeffffff
34230 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
34231 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_RESET 0x0
34232 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 field value from a register. */
34233 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
34234 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value suitable for setting the register. */
34235 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
34236 
34237 /*
34238  * Field : Mask Byte Control - mbc_1
34239  *
34240  * This array of bits are mask control bits for comparison of each of the MAC
34241  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34242  * received DA or SA with the contents of MAC Address16 high and low registers.
34243  * Each bit controls the masking of the bytes. You can filter a group of addresses
34244  * (known as group address filtering) by masking one or more bytes of the address.
34245  *
34246  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34247  *
34248  * Field Enumeration Values:
34249  *
34250  * Enum | Value | Description
34251  * :----------------------------------------------|:------|:------------------------------------
34252  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34253  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34254  *
34255  * Field Access Macros:
34256  *
34257  */
34258 /*
34259  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
34260  *
34261  * Byte is unmasked (i.e. is compared)
34262  */
34263 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED 0x0
34264 /*
34265  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
34266  *
34267  * Byte is masked (i.e. not compared)
34268  */
34269 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED 0x1
34270 
34271 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
34272 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_LSB 25
34273 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
34274 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_MSB 25
34275 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
34276 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_WIDTH 1
34277 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
34278 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET_MSK 0x02000000
34279 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
34280 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_CLR_MSK 0xfdffffff
34281 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
34282 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_RESET 0x0
34283 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 field value from a register. */
34284 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
34285 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value suitable for setting the register. */
34286 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
34287 
34288 /*
34289  * Field : Mask Byte Control - mbc_2
34290  *
34291  * This array of bits are mask control bits for comparison of each of the MAC
34292  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34293  * received DA or SA with the contents of MAC Address16 high and low registers.
34294  * Each bit controls the masking of the bytes. You can filter a group of addresses
34295  * (known as group address filtering) by masking one or more bytes of the address.
34296  *
34297  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34298  *
34299  * Field Enumeration Values:
34300  *
34301  * Enum | Value | Description
34302  * :----------------------------------------------|:------|:------------------------------------
34303  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34304  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34305  *
34306  * Field Access Macros:
34307  *
34308  */
34309 /*
34310  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
34311  *
34312  * Byte is unmasked (i.e. is compared)
34313  */
34314 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED 0x0
34315 /*
34316  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
34317  *
34318  * Byte is masked (i.e. not compared)
34319  */
34320 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED 0x1
34321 
34322 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
34323 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_LSB 26
34324 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
34325 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_MSB 26
34326 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
34327 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_WIDTH 1
34328 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
34329 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET_MSK 0x04000000
34330 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
34331 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_CLR_MSK 0xfbffffff
34332 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
34333 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_RESET 0x0
34334 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 field value from a register. */
34335 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
34336 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value suitable for setting the register. */
34337 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
34338 
34339 /*
34340  * Field : Mask Byte Control - mbc_3
34341  *
34342  * This array of bits are mask control bits for comparison of each of the MAC
34343  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34344  * received DA or SA with the contents of MAC Address16 high and low registers.
34345  * Each bit controls the masking of the bytes. You can filter a group of addresses
34346  * (known as group address filtering) by masking one or more bytes of the address.
34347  *
34348  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34349  *
34350  * Field Enumeration Values:
34351  *
34352  * Enum | Value | Description
34353  * :----------------------------------------------|:------|:------------------------------------
34354  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34355  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34356  *
34357  * Field Access Macros:
34358  *
34359  */
34360 /*
34361  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
34362  *
34363  * Byte is unmasked (i.e. is compared)
34364  */
34365 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED 0x0
34366 /*
34367  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
34368  *
34369  * Byte is masked (i.e. not compared)
34370  */
34371 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED 0x1
34372 
34373 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
34374 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_LSB 27
34375 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
34376 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_MSB 27
34377 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
34378 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_WIDTH 1
34379 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
34380 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET_MSK 0x08000000
34381 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
34382 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_CLR_MSK 0xf7ffffff
34383 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
34384 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_RESET 0x0
34385 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 field value from a register. */
34386 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
34387 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value suitable for setting the register. */
34388 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
34389 
34390 /*
34391  * Field : Mask Byte Control - mbc_4
34392  *
34393  * This array of bits are mask control bits for comparison of each of the MAC
34394  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34395  * received DA or SA with the contents of MAC Address16 high and low registers.
34396  * Each bit controls the masking of the bytes. You can filter a group of addresses
34397  * (known as group address filtering) by masking one or more bytes of the address.
34398  *
34399  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34400  *
34401  * Field Enumeration Values:
34402  *
34403  * Enum | Value | Description
34404  * :----------------------------------------------|:------|:------------------------------------
34405  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34406  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34407  *
34408  * Field Access Macros:
34409  *
34410  */
34411 /*
34412  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
34413  *
34414  * Byte is unmasked (i.e. is compared)
34415  */
34416 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED 0x0
34417 /*
34418  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
34419  *
34420  * Byte is masked (i.e. not compared)
34421  */
34422 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED 0x1
34423 
34424 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
34425 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_LSB 28
34426 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
34427 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_MSB 28
34428 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
34429 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_WIDTH 1
34430 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
34431 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET_MSK 0x10000000
34432 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
34433 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_CLR_MSK 0xefffffff
34434 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
34435 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_RESET 0x0
34436 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 field value from a register. */
34437 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
34438 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value suitable for setting the register. */
34439 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
34440 
34441 /*
34442  * Field : Mask Byte Control - mbc_5
34443  *
34444  * This array of bits are mask control bits for comparison of each of the MAC
34445  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34446  * received DA or SA with the contents of MAC Address16 high and low registers.
34447  * Each bit controls the masking of the bytes. You can filter a group of addresses
34448  * (known as group address filtering) by masking one or more bytes of the address.
34449  *
34450  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34451  *
34452  * Field Enumeration Values:
34453  *
34454  * Enum | Value | Description
34455  * :----------------------------------------------|:------|:------------------------------------
34456  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34457  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34458  *
34459  * Field Access Macros:
34460  *
34461  */
34462 /*
34463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
34464  *
34465  * Byte is unmasked (i.e. is compared)
34466  */
34467 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED 0x0
34468 /*
34469  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
34470  *
34471  * Byte is masked (i.e. not compared)
34472  */
34473 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED 0x1
34474 
34475 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
34476 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_LSB 29
34477 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
34478 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_MSB 29
34479 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
34480 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_WIDTH 1
34481 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
34482 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET_MSK 0x20000000
34483 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
34484 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_CLR_MSK 0xdfffffff
34485 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
34486 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_RESET 0x0
34487 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 field value from a register. */
34488 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
34489 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value suitable for setting the register. */
34490 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
34491 
34492 /*
34493  * Field : Source Address - sa
34494  *
34495  * When this bit is enabled, the MAC Address16[47:0] is used to compare with the SA
34496  * fields of the received frame. When this bit is disabled, the MAC Address16[47:0]
34497  * is used to compare with the DA fields of the received frame.
34498  *
34499  * Field Enumeration Values:
34500  *
34501  * Enum | Value | Description
34502  * :----------------------------------------|:------|:-----------------------------
34503  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
34504  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END | 0x1 | MAC address compare enabled
34505  *
34506  * Field Access Macros:
34507  *
34508  */
34509 /*
34510  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
34511  *
34512  * MAC address compare disabled
34513  */
34514 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD 0x0
34515 /*
34516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
34517  *
34518  * MAC address compare enabled
34519  */
34520 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END 0x1
34521 
34522 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
34523 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_LSB 30
34524 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
34525 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_MSB 30
34526 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
34527 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_WIDTH 1
34528 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
34529 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET_MSK 0x40000000
34530 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
34531 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_CLR_MSK 0xbfffffff
34532 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
34533 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_RESET 0x0
34534 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA field value from a register. */
34535 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
34536 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value suitable for setting the register. */
34537 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
34538 
34539 /*
34540  * Field : Address Enable - ae
34541  *
34542  * When this bit is enabled, the address filter block uses the 17th MAC address for
34543  * perfect filtering. When this bit is disabled, the address filter block ignores
34544  * the address for filtering.
34545  *
34546  * Field Enumeration Values:
34547  *
34548  * Enum | Value | Description
34549  * :----------------------------------------|:------|:--------------------------------------
34550  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
34551  * ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
34552  *
34553  * Field Access Macros:
34554  *
34555  */
34556 /*
34557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
34558  *
34559  * Second MAC address filtering disabled
34560  */
34561 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD 0x0
34562 /*
34563  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
34564  *
34565  * Second MAC address filtering enabled
34566  */
34567 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END 0x1
34568 
34569 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
34570 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_LSB 31
34571 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
34572 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_MSB 31
34573 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
34574 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_WIDTH 1
34575 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
34576 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET_MSK 0x80000000
34577 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
34578 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_CLR_MSK 0x7fffffff
34579 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
34580 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_RESET 0x0
34581 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE field value from a register. */
34582 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
34583 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value suitable for setting the register. */
34584 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
34585 
34586 #ifndef __ASSEMBLY__
34587 /*
34588  * WARNING: The C register and register group struct declarations are provided for
34589  * convenience and illustrative purposes. They should, however, be used with
34590  * caution as the C language standard provides no guarantees about the alignment or
34591  * atomicity of device memory accesses. The recommended practice for writing
34592  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34593  * alt_write_word() functions.
34594  *
34595  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH.
34596  */
34597 struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s
34598 {
34599  uint32_t addrhi : 16; /* MAC Address16 [47:32] */
34600  uint32_t : 8; /* *UNDEFINED* */
34601  uint32_t mbc_0 : 1; /* Mask Byte Control */
34602  uint32_t mbc_1 : 1; /* Mask Byte Control */
34603  uint32_t mbc_2 : 1; /* Mask Byte Control */
34604  uint32_t mbc_3 : 1; /* Mask Byte Control */
34605  uint32_t mbc_4 : 1; /* Mask Byte Control */
34606  uint32_t mbc_5 : 1; /* Mask Byte Control */
34607  uint32_t sa : 1; /* Source Address */
34608  uint32_t ae : 1; /* Address Enable */
34609 };
34610 
34611 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH. */
34612 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t;
34613 #endif /* __ASSEMBLY__ */
34614 
34615 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register from the beginning of the component. */
34616 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST 0x800
34617 /* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register. */
34618 #define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST))
34619 
34620 /*
34621  * Register : Register 513 (MAC Address16 Low Register) - MAC_Address16_Low
34622  *
34623  * The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC
34624  * address of the station.
34625  *
34626  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
34627  * format.
34628  *
34629  * Register Layout
34630  *
34631  * Bits | Access | Reset | Description
34632  * :-------|:-------|:-----------|:---------------------
34633  * [31:0] | RW | 0xffffffff | MAC Address16 [31:0]
34634  *
34635  */
34636 /*
34637  * Field : MAC Address16 [31:0] - addrlo
34638  *
34639  * This field contains the lower 32 bits of the 17th 6-byte MAC address. The
34640  * content of this field is undefined until loaded by software after the
34641  * initialization process.
34642  *
34643  * Field Access Macros:
34644  *
34645  */
34646 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
34647 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_LSB 0
34648 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
34649 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_MSB 31
34650 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
34651 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_WIDTH 32
34652 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
34653 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET_MSK 0xffffffff
34654 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
34655 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_CLR_MSK 0x00000000
34656 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
34657 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_RESET 0xffffffff
34658 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO field value from a register. */
34659 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
34660 /* Produces a ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value suitable for setting the register. */
34661 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
34662 
34663 #ifndef __ASSEMBLY__
34664 /*
34665  * WARNING: The C register and register group struct declarations are provided for
34666  * convenience and illustrative purposes. They should, however, be used with
34667  * caution as the C language standard provides no guarantees about the alignment or
34668  * atomicity of device memory accesses. The recommended practice for writing
34669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
34670  * alt_write_word() functions.
34671  *
34672  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW.
34673  */
34674 struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s
34675 {
34676  uint32_t addrlo : 32; /* MAC Address16 [31:0] */
34677 };
34678 
34679 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW. */
34680 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s ALT_EMAC_GMAC_MAC_ADDR16_LOW_t;
34681 #endif /* __ASSEMBLY__ */
34682 
34683 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register from the beginning of the component. */
34684 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST 0x804
34685 /* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register. */
34686 #define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST))
34687 
34688 /*
34689  * Register : Register 514 (MAC Address17 High Register) - MAC_Address17_High
34690  *
34691  * The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC
34692  * address of the station. Because the MAC address registers are configured to be
34693  * double-synchronized to the (G)MII clock domains, the synchronization is
34694  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
34695  * endian mode) of the MAC Address17 Low Register are written. For proper
34696  * synchronization updates, the consecutive writes to this Address Low Register
34697  * should be performed after at least four clock cycles in the destination clock
34698  * domain.
34699  *
34700  * Note that all MAC Address High registers (except MAC Address0 High) have the
34701  * same format.
34702  *
34703  * Register Layout
34704  *
34705  * Bits | Access | Reset | Description
34706  * :--------|:-------|:-------|:----------------------
34707  * [15:0] | RW | 0xffff | MAC Address17 [47:32]
34708  * [23:16] | ??? | 0x0 | *UNDEFINED*
34709  * [24] | RW | 0x0 | Mask Byte Control
34710  * [25] | RW | 0x0 | Mask Byte Control
34711  * [26] | RW | 0x0 | Mask Byte Control
34712  * [27] | RW | 0x0 | Mask Byte Control
34713  * [28] | RW | 0x0 | Mask Byte Control
34714  * [29] | RW | 0x0 | Mask Byte Control
34715  * [30] | RW | 0x0 | Source Address
34716  * [31] | RW | 0x0 | Address Enable
34717  *
34718  */
34719 /*
34720  * Field : MAC Address17 [47:32] - addrhi
34721  *
34722  * This field contains the upper 16 bits (47:32) of the 18th 6-byte MAC address.
34723  *
34724  * Field Access Macros:
34725  *
34726  */
34727 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
34728 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_LSB 0
34729 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
34730 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_MSB 15
34731 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
34732 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_WIDTH 16
34733 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
34734 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET_MSK 0x0000ffff
34735 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
34736 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_CLR_MSK 0xffff0000
34737 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
34738 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_RESET 0xffff
34739 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI field value from a register. */
34740 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
34741 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value suitable for setting the register. */
34742 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
34743 
34744 /*
34745  * Field : Mask Byte Control - mbc_0
34746  *
34747  * This array of bits are mask control bits for comparison of each of the MAC
34748  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34749  * received DA or SA with the contents of MAC Address17 high and low registers.
34750  * Each bit controls the masking of the bytes. You can filter a group of addresses
34751  * (known as group address filtering) by masking one or more bytes of the address.
34752  *
34753  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34754  *
34755  * Field Enumeration Values:
34756  *
34757  * Enum | Value | Description
34758  * :----------------------------------------------|:------|:------------------------------------
34759  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34760  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34761  *
34762  * Field Access Macros:
34763  *
34764  */
34765 /*
34766  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
34767  *
34768  * Byte is unmasked (i.e. is compared)
34769  */
34770 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED 0x0
34771 /*
34772  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
34773  *
34774  * Byte is masked (i.e. not compared)
34775  */
34776 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED 0x1
34777 
34778 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
34779 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_LSB 24
34780 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
34781 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_MSB 24
34782 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
34783 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_WIDTH 1
34784 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
34785 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET_MSK 0x01000000
34786 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
34787 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_CLR_MSK 0xfeffffff
34788 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
34789 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_RESET 0x0
34790 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 field value from a register. */
34791 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
34792 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value suitable for setting the register. */
34793 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
34794 
34795 /*
34796  * Field : Mask Byte Control - mbc_1
34797  *
34798  * This array of bits are mask control bits for comparison of each of the MAC
34799  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34800  * received DA or SA with the contents of MAC Address17 high and low registers.
34801  * Each bit controls the masking of the bytes. You can filter a group of addresses
34802  * (known as group address filtering) by masking one or more bytes of the address.
34803  *
34804  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34805  *
34806  * Field Enumeration Values:
34807  *
34808  * Enum | Value | Description
34809  * :----------------------------------------------|:------|:------------------------------------
34810  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34811  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34812  *
34813  * Field Access Macros:
34814  *
34815  */
34816 /*
34817  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
34818  *
34819  * Byte is unmasked (i.e. is compared)
34820  */
34821 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED 0x0
34822 /*
34823  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
34824  *
34825  * Byte is masked (i.e. not compared)
34826  */
34827 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED 0x1
34828 
34829 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
34830 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_LSB 25
34831 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
34832 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_MSB 25
34833 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
34834 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_WIDTH 1
34835 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
34836 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET_MSK 0x02000000
34837 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
34838 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_CLR_MSK 0xfdffffff
34839 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
34840 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_RESET 0x0
34841 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 field value from a register. */
34842 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
34843 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value suitable for setting the register. */
34844 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
34845 
34846 /*
34847  * Field : Mask Byte Control - mbc_2
34848  *
34849  * This array of bits are mask control bits for comparison of each of the MAC
34850  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34851  * received DA or SA with the contents of MAC Address17 high and low registers.
34852  * Each bit controls the masking of the bytes. You can filter a group of addresses
34853  * (known as group address filtering) by masking one or more bytes of the address.
34854  *
34855  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34856  *
34857  * Field Enumeration Values:
34858  *
34859  * Enum | Value | Description
34860  * :----------------------------------------------|:------|:------------------------------------
34861  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34862  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34863  *
34864  * Field Access Macros:
34865  *
34866  */
34867 /*
34868  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
34869  *
34870  * Byte is unmasked (i.e. is compared)
34871  */
34872 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED 0x0
34873 /*
34874  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
34875  *
34876  * Byte is masked (i.e. not compared)
34877  */
34878 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED 0x1
34879 
34880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
34881 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_LSB 26
34882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
34883 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_MSB 26
34884 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
34885 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_WIDTH 1
34886 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
34887 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET_MSK 0x04000000
34888 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
34889 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_CLR_MSK 0xfbffffff
34890 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
34891 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_RESET 0x0
34892 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 field value from a register. */
34893 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
34894 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value suitable for setting the register. */
34895 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
34896 
34897 /*
34898  * Field : Mask Byte Control - mbc_3
34899  *
34900  * This array of bits are mask control bits for comparison of each of the MAC
34901  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34902  * received DA or SA with the contents of MAC Address17 high and low registers.
34903  * Each bit controls the masking of the bytes. You can filter a group of addresses
34904  * (known as group address filtering) by masking one or more bytes of the address.
34905  *
34906  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34907  *
34908  * Field Enumeration Values:
34909  *
34910  * Enum | Value | Description
34911  * :----------------------------------------------|:------|:------------------------------------
34912  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34913  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34914  *
34915  * Field Access Macros:
34916  *
34917  */
34918 /*
34919  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
34920  *
34921  * Byte is unmasked (i.e. is compared)
34922  */
34923 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED 0x0
34924 /*
34925  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
34926  *
34927  * Byte is masked (i.e. not compared)
34928  */
34929 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED 0x1
34930 
34931 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
34932 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_LSB 27
34933 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
34934 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_MSB 27
34935 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
34936 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_WIDTH 1
34937 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
34938 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET_MSK 0x08000000
34939 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
34940 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_CLR_MSK 0xf7ffffff
34941 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
34942 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_RESET 0x0
34943 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 field value from a register. */
34944 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
34945 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value suitable for setting the register. */
34946 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
34947 
34948 /*
34949  * Field : Mask Byte Control - mbc_4
34950  *
34951  * This array of bits are mask control bits for comparison of each of the MAC
34952  * Address bytes. When masked, the MAC does not compare the corresponding byte of
34953  * received DA or SA with the contents of MAC Address17 high and low registers.
34954  * Each bit controls the masking of the bytes. You can filter a group of addresses
34955  * (known as group address filtering) by masking one or more bytes of the address.
34956  *
34957  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
34958  *
34959  * Field Enumeration Values:
34960  *
34961  * Enum | Value | Description
34962  * :----------------------------------------------|:------|:------------------------------------
34963  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
34964  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
34965  *
34966  * Field Access Macros:
34967  *
34968  */
34969 /*
34970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
34971  *
34972  * Byte is unmasked (i.e. is compared)
34973  */
34974 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED 0x0
34975 /*
34976  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
34977  *
34978  * Byte is masked (i.e. not compared)
34979  */
34980 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED 0x1
34981 
34982 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
34983 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_LSB 28
34984 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
34985 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_MSB 28
34986 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
34987 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_WIDTH 1
34988 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
34989 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET_MSK 0x10000000
34990 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
34991 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_CLR_MSK 0xefffffff
34992 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
34993 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_RESET 0x0
34994 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 field value from a register. */
34995 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
34996 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value suitable for setting the register. */
34997 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
34998 
34999 /*
35000  * Field : Mask Byte Control - mbc_5
35001  *
35002  * This array of bits are mask control bits for comparison of each of the MAC
35003  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35004  * received DA or SA with the contents of MAC Address17 high and low registers.
35005  * Each bit controls the masking of the bytes. You can filter a group of addresses
35006  * (known as group address filtering) by masking one or more bytes of the address.
35007  *
35008  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35009  *
35010  * Field Enumeration Values:
35011  *
35012  * Enum | Value | Description
35013  * :----------------------------------------------|:------|:------------------------------------
35014  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35015  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35016  *
35017  * Field Access Macros:
35018  *
35019  */
35020 /*
35021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
35022  *
35023  * Byte is unmasked (i.e. is compared)
35024  */
35025 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED 0x0
35026 /*
35027  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
35028  *
35029  * Byte is masked (i.e. not compared)
35030  */
35031 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED 0x1
35032 
35033 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
35034 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_LSB 29
35035 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
35036 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_MSB 29
35037 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
35038 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_WIDTH 1
35039 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
35040 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET_MSK 0x20000000
35041 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
35042 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_CLR_MSK 0xdfffffff
35043 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
35044 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_RESET 0x0
35045 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 field value from a register. */
35046 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
35047 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value suitable for setting the register. */
35048 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
35049 
35050 /*
35051  * Field : Source Address - sa
35052  *
35053  * When this bit is enabled, the MAC Address17[47:0] is used to compare with the SA
35054  * fields of the received frame. When this bit is disabled, the MAC Address17[47:0]
35055  * is used to compare with the DA fields of the received frame.
35056  *
35057  * Field Enumeration Values:
35058  *
35059  * Enum | Value | Description
35060  * :----------------------------------------|:------|:-----------------------------
35061  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
35062  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END | 0x1 | MAC address compare enabled
35063  *
35064  * Field Access Macros:
35065  *
35066  */
35067 /*
35068  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
35069  *
35070  * MAC address compare disabled
35071  */
35072 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD 0x0
35073 /*
35074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
35075  *
35076  * MAC address compare enabled
35077  */
35078 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END 0x1
35079 
35080 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
35081 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_LSB 30
35082 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
35083 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_MSB 30
35084 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
35085 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_WIDTH 1
35086 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
35087 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET_MSK 0x40000000
35088 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
35089 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_CLR_MSK 0xbfffffff
35090 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
35091 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_RESET 0x0
35092 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA field value from a register. */
35093 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
35094 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value suitable for setting the register. */
35095 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
35096 
35097 /*
35098  * Field : Address Enable - ae
35099  *
35100  * When this bit is enabled, the address filter block uses the 18th MAC address for
35101  * perfect filtering. When this bit is disabled, the address filter block ignores
35102  * the address for filtering.
35103  *
35104  * Field Enumeration Values:
35105  *
35106  * Enum | Value | Description
35107  * :----------------------------------------|:------|:--------------------------------------
35108  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
35109  * ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
35110  *
35111  * Field Access Macros:
35112  *
35113  */
35114 /*
35115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
35116  *
35117  * Second MAC address filtering disabled
35118  */
35119 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD 0x0
35120 /*
35121  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
35122  *
35123  * Second MAC address filtering enabled
35124  */
35125 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END 0x1
35126 
35127 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
35128 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_LSB 31
35129 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
35130 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_MSB 31
35131 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
35132 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_WIDTH 1
35133 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
35134 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET_MSK 0x80000000
35135 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
35136 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_CLR_MSK 0x7fffffff
35137 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
35138 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_RESET 0x0
35139 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE field value from a register. */
35140 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
35141 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value suitable for setting the register. */
35142 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
35143 
35144 #ifndef __ASSEMBLY__
35145 /*
35146  * WARNING: The C register and register group struct declarations are provided for
35147  * convenience and illustrative purposes. They should, however, be used with
35148  * caution as the C language standard provides no guarantees about the alignment or
35149  * atomicity of device memory accesses. The recommended practice for writing
35150  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35151  * alt_write_word() functions.
35152  *
35153  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH.
35154  */
35155 struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s
35156 {
35157  uint32_t addrhi : 16; /* MAC Address17 [47:32] */
35158  uint32_t : 8; /* *UNDEFINED* */
35159  uint32_t mbc_0 : 1; /* Mask Byte Control */
35160  uint32_t mbc_1 : 1; /* Mask Byte Control */
35161  uint32_t mbc_2 : 1; /* Mask Byte Control */
35162  uint32_t mbc_3 : 1; /* Mask Byte Control */
35163  uint32_t mbc_4 : 1; /* Mask Byte Control */
35164  uint32_t mbc_5 : 1; /* Mask Byte Control */
35165  uint32_t sa : 1; /* Source Address */
35166  uint32_t ae : 1; /* Address Enable */
35167 };
35168 
35169 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH. */
35170 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t;
35171 #endif /* __ASSEMBLY__ */
35172 
35173 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register from the beginning of the component. */
35174 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST 0x808
35175 /* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register. */
35176 #define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST))
35177 
35178 /*
35179  * Register : Register 515 (MAC Address17 Low Register) - MAC_Address17_Low
35180  *
35181  * The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC
35182  * address of the station.
35183  *
35184  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
35185  * format.
35186  *
35187  * Register Layout
35188  *
35189  * Bits | Access | Reset | Description
35190  * :-------|:-------|:-----------|:---------------------
35191  * [31:0] | RW | 0xffffffff | MAC Address17 [31:0]
35192  *
35193  */
35194 /*
35195  * Field : MAC Address17 [31:0] - addrlo
35196  *
35197  * This field contains the lower 32 bits of the 18th 6-byte MAC address. The
35198  * content of this field is undefined until loaded by software after the
35199  * initialization process.
35200  *
35201  * Field Access Macros:
35202  *
35203  */
35204 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
35205 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_LSB 0
35206 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
35207 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_MSB 31
35208 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
35209 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_WIDTH 32
35210 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
35211 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET_MSK 0xffffffff
35212 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
35213 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_CLR_MSK 0x00000000
35214 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
35215 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_RESET 0xffffffff
35216 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO field value from a register. */
35217 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
35218 /* Produces a ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value suitable for setting the register. */
35219 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
35220 
35221 #ifndef __ASSEMBLY__
35222 /*
35223  * WARNING: The C register and register group struct declarations are provided for
35224  * convenience and illustrative purposes. They should, however, be used with
35225  * caution as the C language standard provides no guarantees about the alignment or
35226  * atomicity of device memory accesses. The recommended practice for writing
35227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35228  * alt_write_word() functions.
35229  *
35230  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW.
35231  */
35232 struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s
35233 {
35234  uint32_t addrlo : 32; /* MAC Address17 [31:0] */
35235 };
35236 
35237 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW. */
35238 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s ALT_EMAC_GMAC_MAC_ADDR17_LOW_t;
35239 #endif /* __ASSEMBLY__ */
35240 
35241 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register from the beginning of the component. */
35242 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST 0x80c
35243 /* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register. */
35244 #define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST))
35245 
35246 /*
35247  * Register : Register 516 (MAC Address18 High Register) - MAC_Address18_High
35248  *
35249  * The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC
35250  * address of the station. Because the MAC address registers are configured to be
35251  * double-synchronized to the (G)MII clock domains, the synchronization is
35252  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
35253  * endian mode) of the MAC Address18 Low Register are written. For proper
35254  * synchronization updates, the consecutive writes to this Address Low Register
35255  * should be performed after at least four clock cycles in the destination clock
35256  * domain.
35257  *
35258  * Note that all MAC Address High registers (except MAC Address0 High) have the
35259  * same format.
35260  *
35261  * Register Layout
35262  *
35263  * Bits | Access | Reset | Description
35264  * :--------|:-------|:-------|:----------------------
35265  * [15:0] | RW | 0xffff | MAC Address18 [47:32]
35266  * [23:16] | ??? | 0x0 | *UNDEFINED*
35267  * [24] | RW | 0x0 | Mask Byte Control
35268  * [25] | RW | 0x0 | Mask Byte Control
35269  * [26] | RW | 0x0 | Mask Byte Control
35270  * [27] | RW | 0x0 | Mask Byte Control
35271  * [28] | RW | 0x0 | Mask Byte Control
35272  * [29] | RW | 0x0 | Mask Byte Control
35273  * [30] | RW | 0x0 | Source Address
35274  * [31] | RW | 0x0 | Address Enable
35275  *
35276  */
35277 /*
35278  * Field : MAC Address18 [47:32] - addrhi
35279  *
35280  * This field contains the upper 16 bits (47:32) of the 19th 6-byte MAC address.
35281  *
35282  * Field Access Macros:
35283  *
35284  */
35285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
35286 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_LSB 0
35287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
35288 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_MSB 15
35289 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
35290 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_WIDTH 16
35291 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
35292 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET_MSK 0x0000ffff
35293 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
35294 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_CLR_MSK 0xffff0000
35295 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
35296 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_RESET 0xffff
35297 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI field value from a register. */
35298 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
35299 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value suitable for setting the register. */
35300 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
35301 
35302 /*
35303  * Field : Mask Byte Control - mbc_0
35304  *
35305  * This array of bits are mask control bits for comparison of each of the MAC
35306  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35307  * received DA or SA with the contents of MAC Address18 high and low registers.
35308  * Each bit controls the masking of the bytes. You can filter a group of addresses
35309  * (known as group address filtering) by masking one or more bytes of the address.
35310  *
35311  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35312  *
35313  * Field Enumeration Values:
35314  *
35315  * Enum | Value | Description
35316  * :----------------------------------------------|:------|:------------------------------------
35317  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35318  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35319  *
35320  * Field Access Macros:
35321  *
35322  */
35323 /*
35324  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
35325  *
35326  * Byte is unmasked (i.e. is compared)
35327  */
35328 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED 0x0
35329 /*
35330  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
35331  *
35332  * Byte is masked (i.e. not compared)
35333  */
35334 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED 0x1
35335 
35336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
35337 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_LSB 24
35338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
35339 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_MSB 24
35340 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
35341 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_WIDTH 1
35342 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
35343 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET_MSK 0x01000000
35344 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
35345 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_CLR_MSK 0xfeffffff
35346 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
35347 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_RESET 0x0
35348 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 field value from a register. */
35349 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
35350 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value suitable for setting the register. */
35351 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
35352 
35353 /*
35354  * Field : Mask Byte Control - mbc_1
35355  *
35356  * This array of bits are mask control bits for comparison of each of the MAC
35357  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35358  * received DA or SA with the contents of MAC Address18 high and low registers.
35359  * Each bit controls the masking of the bytes. You can filter a group of addresses
35360  * (known as group address filtering) by masking one or more bytes of the address.
35361  *
35362  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35363  *
35364  * Field Enumeration Values:
35365  *
35366  * Enum | Value | Description
35367  * :----------------------------------------------|:------|:------------------------------------
35368  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35369  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35370  *
35371  * Field Access Macros:
35372  *
35373  */
35374 /*
35375  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
35376  *
35377  * Byte is unmasked (i.e. is compared)
35378  */
35379 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED 0x0
35380 /*
35381  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
35382  *
35383  * Byte is masked (i.e. not compared)
35384  */
35385 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED 0x1
35386 
35387 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
35388 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_LSB 25
35389 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
35390 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_MSB 25
35391 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
35392 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_WIDTH 1
35393 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
35394 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET_MSK 0x02000000
35395 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
35396 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_CLR_MSK 0xfdffffff
35397 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
35398 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_RESET 0x0
35399 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 field value from a register. */
35400 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
35401 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value suitable for setting the register. */
35402 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
35403 
35404 /*
35405  * Field : Mask Byte Control - mbc_2
35406  *
35407  * This array of bits are mask control bits for comparison of each of the MAC
35408  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35409  * received DA or SA with the contents of MAC Address18 high and low registers.
35410  * Each bit controls the masking of the bytes. You can filter a group of addresses
35411  * (known as group address filtering) by masking one or more bytes of the address.
35412  *
35413  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35414  *
35415  * Field Enumeration Values:
35416  *
35417  * Enum | Value | Description
35418  * :----------------------------------------------|:------|:------------------------------------
35419  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35420  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35421  *
35422  * Field Access Macros:
35423  *
35424  */
35425 /*
35426  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
35427  *
35428  * Byte is unmasked (i.e. is compared)
35429  */
35430 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED 0x0
35431 /*
35432  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
35433  *
35434  * Byte is masked (i.e. not compared)
35435  */
35436 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED 0x1
35437 
35438 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
35439 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_LSB 26
35440 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
35441 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_MSB 26
35442 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
35443 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_WIDTH 1
35444 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
35445 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET_MSK 0x04000000
35446 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
35447 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_CLR_MSK 0xfbffffff
35448 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
35449 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_RESET 0x0
35450 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 field value from a register. */
35451 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
35452 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value suitable for setting the register. */
35453 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
35454 
35455 /*
35456  * Field : Mask Byte Control - mbc_3
35457  *
35458  * This array of bits are mask control bits for comparison of each of the MAC
35459  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35460  * received DA or SA with the contents of MAC Address18 high and low registers.
35461  * Each bit controls the masking of the bytes. You can filter a group of addresses
35462  * (known as group address filtering) by masking one or more bytes of the address.
35463  *
35464  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35465  *
35466  * Field Enumeration Values:
35467  *
35468  * Enum | Value | Description
35469  * :----------------------------------------------|:------|:------------------------------------
35470  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35471  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35472  *
35473  * Field Access Macros:
35474  *
35475  */
35476 /*
35477  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
35478  *
35479  * Byte is unmasked (i.e. is compared)
35480  */
35481 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED 0x0
35482 /*
35483  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
35484  *
35485  * Byte is masked (i.e. not compared)
35486  */
35487 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED 0x1
35488 
35489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
35490 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_LSB 27
35491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
35492 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_MSB 27
35493 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
35494 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_WIDTH 1
35495 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
35496 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET_MSK 0x08000000
35497 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
35498 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_CLR_MSK 0xf7ffffff
35499 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
35500 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_RESET 0x0
35501 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 field value from a register. */
35502 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
35503 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value suitable for setting the register. */
35504 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
35505 
35506 /*
35507  * Field : Mask Byte Control - mbc_4
35508  *
35509  * This array of bits are mask control bits for comparison of each of the MAC
35510  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35511  * received DA or SA with the contents of MAC Address18 high and low registers.
35512  * Each bit controls the masking of the bytes. You can filter a group of addresses
35513  * (known as group address filtering) by masking one or more bytes of the address.
35514  *
35515  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35516  *
35517  * Field Enumeration Values:
35518  *
35519  * Enum | Value | Description
35520  * :----------------------------------------------|:------|:------------------------------------
35521  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35522  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35523  *
35524  * Field Access Macros:
35525  *
35526  */
35527 /*
35528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
35529  *
35530  * Byte is unmasked (i.e. is compared)
35531  */
35532 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED 0x0
35533 /*
35534  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
35535  *
35536  * Byte is masked (i.e. not compared)
35537  */
35538 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED 0x1
35539 
35540 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
35541 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_LSB 28
35542 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
35543 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_MSB 28
35544 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
35545 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_WIDTH 1
35546 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
35547 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET_MSK 0x10000000
35548 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
35549 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_CLR_MSK 0xefffffff
35550 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
35551 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_RESET 0x0
35552 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 field value from a register. */
35553 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
35554 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value suitable for setting the register. */
35555 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
35556 
35557 /*
35558  * Field : Mask Byte Control - mbc_5
35559  *
35560  * This array of bits are mask control bits for comparison of each of the MAC
35561  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35562  * received DA or SA with the contents of MAC Address18 high and low registers.
35563  * Each bit controls the masking of the bytes. You can filter a group of addresses
35564  * (known as group address filtering) by masking one or more bytes of the address.
35565  *
35566  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35567  *
35568  * Field Enumeration Values:
35569  *
35570  * Enum | Value | Description
35571  * :----------------------------------------------|:------|:------------------------------------
35572  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35573  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35574  *
35575  * Field Access Macros:
35576  *
35577  */
35578 /*
35579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
35580  *
35581  * Byte is unmasked (i.e. is compared)
35582  */
35583 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED 0x0
35584 /*
35585  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
35586  *
35587  * Byte is masked (i.e. not compared)
35588  */
35589 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED 0x1
35590 
35591 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
35592 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_LSB 29
35593 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
35594 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_MSB 29
35595 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
35596 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_WIDTH 1
35597 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
35598 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET_MSK 0x20000000
35599 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
35600 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_CLR_MSK 0xdfffffff
35601 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
35602 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_RESET 0x0
35603 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 field value from a register. */
35604 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
35605 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value suitable for setting the register. */
35606 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
35607 
35608 /*
35609  * Field : Source Address - sa
35610  *
35611  * When this bit is enabled, the MAC Address18[47:0] is used to compare with the SA
35612  * fields of the received frame. When this bit is disabled, the MAC Address18[47:0]
35613  * is used to compare with the DA fields of the received frame.
35614  *
35615  * Field Enumeration Values:
35616  *
35617  * Enum | Value | Description
35618  * :----------------------------------------|:------|:-----------------------------
35619  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
35620  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END | 0x1 | MAC address compare enabled
35621  *
35622  * Field Access Macros:
35623  *
35624  */
35625 /*
35626  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
35627  *
35628  * MAC address compare disabled
35629  */
35630 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD 0x0
35631 /*
35632  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
35633  *
35634  * MAC address compare enabled
35635  */
35636 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END 0x1
35637 
35638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
35639 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_LSB 30
35640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
35641 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_MSB 30
35642 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
35643 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_WIDTH 1
35644 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
35645 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET_MSK 0x40000000
35646 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
35647 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_CLR_MSK 0xbfffffff
35648 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
35649 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_RESET 0x0
35650 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA field value from a register. */
35651 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
35652 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value suitable for setting the register. */
35653 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
35654 
35655 /*
35656  * Field : Address Enable - ae
35657  *
35658  * When this bit is enabled, the address filter block uses the 19th MAC address for
35659  * perfect filtering. When this bit is disabled, the address filter block ignores
35660  * the address for filtering.
35661  *
35662  * Field Enumeration Values:
35663  *
35664  * Enum | Value | Description
35665  * :----------------------------------------|:------|:--------------------------------------
35666  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
35667  * ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
35668  *
35669  * Field Access Macros:
35670  *
35671  */
35672 /*
35673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
35674  *
35675  * Second MAC address filtering disabled
35676  */
35677 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD 0x0
35678 /*
35679  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
35680  *
35681  * Second MAC address filtering enabled
35682  */
35683 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END 0x1
35684 
35685 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
35686 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_LSB 31
35687 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
35688 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_MSB 31
35689 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
35690 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_WIDTH 1
35691 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
35692 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET_MSK 0x80000000
35693 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
35694 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_CLR_MSK 0x7fffffff
35695 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
35696 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_RESET 0x0
35697 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE field value from a register. */
35698 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
35699 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value suitable for setting the register. */
35700 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
35701 
35702 #ifndef __ASSEMBLY__
35703 /*
35704  * WARNING: The C register and register group struct declarations are provided for
35705  * convenience and illustrative purposes. They should, however, be used with
35706  * caution as the C language standard provides no guarantees about the alignment or
35707  * atomicity of device memory accesses. The recommended practice for writing
35708  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35709  * alt_write_word() functions.
35710  *
35711  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH.
35712  */
35713 struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s
35714 {
35715  uint32_t addrhi : 16; /* MAC Address18 [47:32] */
35716  uint32_t : 8; /* *UNDEFINED* */
35717  uint32_t mbc_0 : 1; /* Mask Byte Control */
35718  uint32_t mbc_1 : 1; /* Mask Byte Control */
35719  uint32_t mbc_2 : 1; /* Mask Byte Control */
35720  uint32_t mbc_3 : 1; /* Mask Byte Control */
35721  uint32_t mbc_4 : 1; /* Mask Byte Control */
35722  uint32_t mbc_5 : 1; /* Mask Byte Control */
35723  uint32_t sa : 1; /* Source Address */
35724  uint32_t ae : 1; /* Address Enable */
35725 };
35726 
35727 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH. */
35728 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t;
35729 #endif /* __ASSEMBLY__ */
35730 
35731 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register from the beginning of the component. */
35732 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST 0x810
35733 /* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register. */
35734 #define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST))
35735 
35736 /*
35737  * Register : Register 517 (MAC Address18 Low Register) - MAC_Address18_Low
35738  *
35739  * The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC
35740  * address of the station.
35741  *
35742  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
35743  * format.
35744  *
35745  * Register Layout
35746  *
35747  * Bits | Access | Reset | Description
35748  * :-------|:-------|:-----------|:---------------------
35749  * [31:0] | RW | 0xffffffff | MAC Address18 [31:0]
35750  *
35751  */
35752 /*
35753  * Field : MAC Address18 [31:0] - addrlo
35754  *
35755  * This field contains the lower 32 bits of the 19th 6-byte MAC address. The
35756  * content of this field is undefined until loaded by software after the
35757  * initialization process.
35758  *
35759  * Field Access Macros:
35760  *
35761  */
35762 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
35763 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_LSB 0
35764 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
35765 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_MSB 31
35766 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
35767 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_WIDTH 32
35768 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
35769 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET_MSK 0xffffffff
35770 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
35771 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_CLR_MSK 0x00000000
35772 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
35773 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_RESET 0xffffffff
35774 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO field value from a register. */
35775 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
35776 /* Produces a ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value suitable for setting the register. */
35777 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
35778 
35779 #ifndef __ASSEMBLY__
35780 /*
35781  * WARNING: The C register and register group struct declarations are provided for
35782  * convenience and illustrative purposes. They should, however, be used with
35783  * caution as the C language standard provides no guarantees about the alignment or
35784  * atomicity of device memory accesses. The recommended practice for writing
35785  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
35786  * alt_write_word() functions.
35787  *
35788  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW.
35789  */
35790 struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s
35791 {
35792  uint32_t addrlo : 32; /* MAC Address18 [31:0] */
35793 };
35794 
35795 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW. */
35796 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s ALT_EMAC_GMAC_MAC_ADDR18_LOW_t;
35797 #endif /* __ASSEMBLY__ */
35798 
35799 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register from the beginning of the component. */
35800 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST 0x814
35801 /* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register. */
35802 #define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST))
35803 
35804 /*
35805  * Register : Register 518 (MAC Address19 High Register) - MAC_Address19_High
35806  *
35807  * The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC
35808  * address of the station. Because the MAC address registers are configured to be
35809  * double-synchronized to the (G)MII clock domains, the synchronization is
35810  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
35811  * endian mode) of the MAC Address19 Low Register are written. For proper
35812  * synchronization updates, the consecutive writes to this Address Low Register
35813  * should be performed after at least four clock cycles in the destination clock
35814  * domain.
35815  *
35816  * Note that all MAC Address High registers (except MAC Address0 High) have the
35817  * same format.
35818  *
35819  * Register Layout
35820  *
35821  * Bits | Access | Reset | Description
35822  * :--------|:-------|:-------|:----------------------
35823  * [15:0] | RW | 0xffff | MAC Address19 [47:32]
35824  * [23:16] | ??? | 0x0 | *UNDEFINED*
35825  * [24] | RW | 0x0 | Mask Byte Control
35826  * [25] | RW | 0x0 | Mask Byte Control
35827  * [26] | RW | 0x0 | Mask Byte Control
35828  * [27] | RW | 0x0 | Mask Byte Control
35829  * [28] | RW | 0x0 | Mask Byte Control
35830  * [29] | RW | 0x0 | Mask Byte Control
35831  * [30] | RW | 0x0 | Source Address
35832  * [31] | RW | 0x0 | Address Enable
35833  *
35834  */
35835 /*
35836  * Field : MAC Address19 [47:32] - addrhi
35837  *
35838  * This field contains the upper 16 bits (47:32) of the 20th 6-byte MAC address.
35839  *
35840  * Field Access Macros:
35841  *
35842  */
35843 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
35844 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_LSB 0
35845 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
35846 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_MSB 15
35847 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
35848 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_WIDTH 16
35849 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
35850 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET_MSK 0x0000ffff
35851 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
35852 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_CLR_MSK 0xffff0000
35853 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
35854 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_RESET 0xffff
35855 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI field value from a register. */
35856 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
35857 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value suitable for setting the register. */
35858 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
35859 
35860 /*
35861  * Field : Mask Byte Control - mbc_0
35862  *
35863  * This array of bits are mask control bits for comparison of each of the MAC
35864  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35865  * received DA or SA with the contents of MAC Address19 high and low registers.
35866  * Each bit controls the masking of the bytes. You can filter a group of addresses
35867  * (known as group address filtering) by masking one or more bytes of the address.
35868  *
35869  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35870  *
35871  * Field Enumeration Values:
35872  *
35873  * Enum | Value | Description
35874  * :----------------------------------------------|:------|:------------------------------------
35875  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35876  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35877  *
35878  * Field Access Macros:
35879  *
35880  */
35881 /*
35882  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
35883  *
35884  * Byte is unmasked (i.e. is compared)
35885  */
35886 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED 0x0
35887 /*
35888  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
35889  *
35890  * Byte is masked (i.e. not compared)
35891  */
35892 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED 0x1
35893 
35894 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
35895 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_LSB 24
35896 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
35897 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_MSB 24
35898 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
35899 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_WIDTH 1
35900 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
35901 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET_MSK 0x01000000
35902 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
35903 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_CLR_MSK 0xfeffffff
35904 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
35905 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_RESET 0x0
35906 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 field value from a register. */
35907 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
35908 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value suitable for setting the register. */
35909 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
35910 
35911 /*
35912  * Field : Mask Byte Control - mbc_1
35913  *
35914  * This array of bits are mask control bits for comparison of each of the MAC
35915  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35916  * received DA or SA with the contents of MAC Address19 high and low registers.
35917  * Each bit controls the masking of the bytes. You can filter a group of addresses
35918  * (known as group address filtering) by masking one or more bytes of the address.
35919  *
35920  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35921  *
35922  * Field Enumeration Values:
35923  *
35924  * Enum | Value | Description
35925  * :----------------------------------------------|:------|:------------------------------------
35926  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35927  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35928  *
35929  * Field Access Macros:
35930  *
35931  */
35932 /*
35933  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
35934  *
35935  * Byte is unmasked (i.e. is compared)
35936  */
35937 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED 0x0
35938 /*
35939  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
35940  *
35941  * Byte is masked (i.e. not compared)
35942  */
35943 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED 0x1
35944 
35945 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
35946 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_LSB 25
35947 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
35948 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_MSB 25
35949 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
35950 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_WIDTH 1
35951 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
35952 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET_MSK 0x02000000
35953 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
35954 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_CLR_MSK 0xfdffffff
35955 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
35956 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_RESET 0x0
35957 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 field value from a register. */
35958 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
35959 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value suitable for setting the register. */
35960 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
35961 
35962 /*
35963  * Field : Mask Byte Control - mbc_2
35964  *
35965  * This array of bits are mask control bits for comparison of each of the MAC
35966  * Address bytes. When masked, the MAC does not compare the corresponding byte of
35967  * received DA or SA with the contents of MAC Address19 high and low registers.
35968  * Each bit controls the masking of the bytes. You can filter a group of addresses
35969  * (known as group address filtering) by masking one or more bytes of the address.
35970  *
35971  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
35972  *
35973  * Field Enumeration Values:
35974  *
35975  * Enum | Value | Description
35976  * :----------------------------------------------|:------|:------------------------------------
35977  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
35978  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
35979  *
35980  * Field Access Macros:
35981  *
35982  */
35983 /*
35984  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
35985  *
35986  * Byte is unmasked (i.e. is compared)
35987  */
35988 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED 0x0
35989 /*
35990  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
35991  *
35992  * Byte is masked (i.e. not compared)
35993  */
35994 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED 0x1
35995 
35996 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
35997 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_LSB 26
35998 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
35999 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_MSB 26
36000 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
36001 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_WIDTH 1
36002 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
36003 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET_MSK 0x04000000
36004 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
36005 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_CLR_MSK 0xfbffffff
36006 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
36007 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_RESET 0x0
36008 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 field value from a register. */
36009 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
36010 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value suitable for setting the register. */
36011 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
36012 
36013 /*
36014  * Field : Mask Byte Control - mbc_3
36015  *
36016  * This array of bits are mask control bits for comparison of each of the MAC
36017  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36018  * received DA or SA with the contents of MAC Address19 high and low registers.
36019  * Each bit controls the masking of the bytes. You can filter a group of addresses
36020  * (known as group address filtering) by masking one or more bytes of the address.
36021  *
36022  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36023  *
36024  * Field Enumeration Values:
36025  *
36026  * Enum | Value | Description
36027  * :----------------------------------------------|:------|:------------------------------------
36028  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36029  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36030  *
36031  * Field Access Macros:
36032  *
36033  */
36034 /*
36035  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
36036  *
36037  * Byte is unmasked (i.e. is compared)
36038  */
36039 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED 0x0
36040 /*
36041  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
36042  *
36043  * Byte is masked (i.e. not compared)
36044  */
36045 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED 0x1
36046 
36047 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
36048 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_LSB 27
36049 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
36050 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_MSB 27
36051 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
36052 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_WIDTH 1
36053 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
36054 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET_MSK 0x08000000
36055 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
36056 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_CLR_MSK 0xf7ffffff
36057 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
36058 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_RESET 0x0
36059 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 field value from a register. */
36060 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
36061 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value suitable for setting the register. */
36062 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
36063 
36064 /*
36065  * Field : Mask Byte Control - mbc_4
36066  *
36067  * This array of bits are mask control bits for comparison of each of the MAC
36068  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36069  * received DA or SA with the contents of MAC Address19 high and low registers.
36070  * Each bit controls the masking of the bytes. You can filter a group of addresses
36071  * (known as group address filtering) by masking one or more bytes of the address.
36072  *
36073  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36074  *
36075  * Field Enumeration Values:
36076  *
36077  * Enum | Value | Description
36078  * :----------------------------------------------|:------|:------------------------------------
36079  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36080  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36081  *
36082  * Field Access Macros:
36083  *
36084  */
36085 /*
36086  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
36087  *
36088  * Byte is unmasked (i.e. is compared)
36089  */
36090 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED 0x0
36091 /*
36092  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
36093  *
36094  * Byte is masked (i.e. not compared)
36095  */
36096 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED 0x1
36097 
36098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
36099 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_LSB 28
36100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
36101 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_MSB 28
36102 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
36103 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_WIDTH 1
36104 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
36105 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET_MSK 0x10000000
36106 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
36107 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_CLR_MSK 0xefffffff
36108 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
36109 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_RESET 0x0
36110 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 field value from a register. */
36111 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
36112 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value suitable for setting the register. */
36113 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
36114 
36115 /*
36116  * Field : Mask Byte Control - mbc_5
36117  *
36118  * This array of bits are mask control bits for comparison of each of the MAC
36119  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36120  * received DA or SA with the contents of MAC Address19 high and low registers.
36121  * Each bit controls the masking of the bytes. You can filter a group of addresses
36122  * (known as group address filtering) by masking one or more bytes of the address.
36123  *
36124  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36125  *
36126  * Field Enumeration Values:
36127  *
36128  * Enum | Value | Description
36129  * :----------------------------------------------|:------|:------------------------------------
36130  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36131  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36132  *
36133  * Field Access Macros:
36134  *
36135  */
36136 /*
36137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
36138  *
36139  * Byte is unmasked (i.e. is compared)
36140  */
36141 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED 0x0
36142 /*
36143  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
36144  *
36145  * Byte is masked (i.e. not compared)
36146  */
36147 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED 0x1
36148 
36149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
36150 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_LSB 29
36151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
36152 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_MSB 29
36153 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
36154 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_WIDTH 1
36155 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
36156 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET_MSK 0x20000000
36157 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
36158 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_CLR_MSK 0xdfffffff
36159 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
36160 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_RESET 0x0
36161 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 field value from a register. */
36162 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
36163 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value suitable for setting the register. */
36164 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
36165 
36166 /*
36167  * Field : Source Address - sa
36168  *
36169  * When this bit is enabled, the MAC Address19[47:0] is used to compare with the SA
36170  * fields of the received frame. When this bit is disabled, the MAC Address19[47:0]
36171  * is used to compare with the DA fields of the received frame.
36172  *
36173  * Field Enumeration Values:
36174  *
36175  * Enum | Value | Description
36176  * :----------------------------------------|:------|:-----------------------------
36177  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
36178  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END | 0x1 | MAC address compare enabled
36179  *
36180  * Field Access Macros:
36181  *
36182  */
36183 /*
36184  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
36185  *
36186  * MAC address compare disabled
36187  */
36188 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD 0x0
36189 /*
36190  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
36191  *
36192  * MAC address compare enabled
36193  */
36194 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END 0x1
36195 
36196 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
36197 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_LSB 30
36198 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
36199 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_MSB 30
36200 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
36201 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_WIDTH 1
36202 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
36203 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET_MSK 0x40000000
36204 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
36205 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_CLR_MSK 0xbfffffff
36206 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
36207 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_RESET 0x0
36208 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA field value from a register. */
36209 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
36210 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value suitable for setting the register. */
36211 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
36212 
36213 /*
36214  * Field : Address Enable - ae
36215  *
36216  * When this bit is enabled, the address filter block uses the 20th MAC address for
36217  * perfect filtering. When this bit is disabled, the address filter block ignores
36218  * the address for filtering.
36219  *
36220  * Field Enumeration Values:
36221  *
36222  * Enum | Value | Description
36223  * :----------------------------------------|:------|:--------------------------------------
36224  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
36225  * ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
36226  *
36227  * Field Access Macros:
36228  *
36229  */
36230 /*
36231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
36232  *
36233  * Second MAC address filtering disabled
36234  */
36235 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD 0x0
36236 /*
36237  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
36238  *
36239  * Second MAC address filtering enabled
36240  */
36241 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END 0x1
36242 
36243 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
36244 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_LSB 31
36245 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
36246 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_MSB 31
36247 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
36248 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_WIDTH 1
36249 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
36250 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET_MSK 0x80000000
36251 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
36252 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_CLR_MSK 0x7fffffff
36253 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
36254 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_RESET 0x0
36255 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE field value from a register. */
36256 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
36257 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value suitable for setting the register. */
36258 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
36259 
36260 #ifndef __ASSEMBLY__
36261 /*
36262  * WARNING: The C register and register group struct declarations are provided for
36263  * convenience and illustrative purposes. They should, however, be used with
36264  * caution as the C language standard provides no guarantees about the alignment or
36265  * atomicity of device memory accesses. The recommended practice for writing
36266  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36267  * alt_write_word() functions.
36268  *
36269  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH.
36270  */
36271 struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s
36272 {
36273  uint32_t addrhi : 16; /* MAC Address19 [47:32] */
36274  uint32_t : 8; /* *UNDEFINED* */
36275  uint32_t mbc_0 : 1; /* Mask Byte Control */
36276  uint32_t mbc_1 : 1; /* Mask Byte Control */
36277  uint32_t mbc_2 : 1; /* Mask Byte Control */
36278  uint32_t mbc_3 : 1; /* Mask Byte Control */
36279  uint32_t mbc_4 : 1; /* Mask Byte Control */
36280  uint32_t mbc_5 : 1; /* Mask Byte Control */
36281  uint32_t sa : 1; /* Source Address */
36282  uint32_t ae : 1; /* Address Enable */
36283 };
36284 
36285 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH. */
36286 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t;
36287 #endif /* __ASSEMBLY__ */
36288 
36289 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register from the beginning of the component. */
36290 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST 0x818
36291 /* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register. */
36292 #define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST))
36293 
36294 /*
36295  * Register : Register 519 (MAC Address19 Low Register) - MAC_Address19_Low
36296  *
36297  * The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC
36298  * address of the station.
36299  *
36300  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
36301  * format.
36302  *
36303  * Register Layout
36304  *
36305  * Bits | Access | Reset | Description
36306  * :-------|:-------|:-----------|:---------------------
36307  * [31:0] | RW | 0xffffffff | MAC Address19 [31:0]
36308  *
36309  */
36310 /*
36311  * Field : MAC Address19 [31:0] - addrlo
36312  *
36313  * This field contains the lower 32 bits of the 20th 6-byte MAC address. The
36314  * content of this field is undefined until loaded by software after the
36315  * initialization process.
36316  *
36317  * Field Access Macros:
36318  *
36319  */
36320 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
36321 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_LSB 0
36322 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
36323 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_MSB 31
36324 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
36325 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_WIDTH 32
36326 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
36327 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET_MSK 0xffffffff
36328 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
36329 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_CLR_MSK 0x00000000
36330 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
36331 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_RESET 0xffffffff
36332 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO field value from a register. */
36333 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
36334 /* Produces a ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value suitable for setting the register. */
36335 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
36336 
36337 #ifndef __ASSEMBLY__
36338 /*
36339  * WARNING: The C register and register group struct declarations are provided for
36340  * convenience and illustrative purposes. They should, however, be used with
36341  * caution as the C language standard provides no guarantees about the alignment or
36342  * atomicity of device memory accesses. The recommended practice for writing
36343  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36344  * alt_write_word() functions.
36345  *
36346  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW.
36347  */
36348 struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s
36349 {
36350  uint32_t addrlo : 32; /* MAC Address19 [31:0] */
36351 };
36352 
36353 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW. */
36354 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s ALT_EMAC_GMAC_MAC_ADDR19_LOW_t;
36355 #endif /* __ASSEMBLY__ */
36356 
36357 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register from the beginning of the component. */
36358 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST 0x81c
36359 /* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register. */
36360 #define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST))
36361 
36362 /*
36363  * Register : Register 520 (MAC Address20 High Register) - MAC_Address20_High
36364  *
36365  * The MAC Address20 High register holds the upper 16 bits of the 21th 6-byte MAC
36366  * address of the station. Because the MAC address registers are configured to be
36367  * double-synchronized to the (G)MII clock domains, the synchronization is
36368  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
36369  * endian mode) of the MAC Address20 Low Register are written. For proper
36370  * synchronization updates, the consecutive writes to this Address Low Register
36371  * should be performed after at least four clock cycles in the destination clock
36372  * domain.
36373  *
36374  * Note that all MAC Address High registers (except MAC Address0 High) have the
36375  * same format.
36376  *
36377  * Register Layout
36378  *
36379  * Bits | Access | Reset | Description
36380  * :--------|:-------|:-------|:----------------------
36381  * [15:0] | RW | 0xffff | MAC Address20 [47:32]
36382  * [23:16] | ??? | 0x0 | *UNDEFINED*
36383  * [24] | RW | 0x0 | Mask Byte Control
36384  * [25] | RW | 0x0 | Mask Byte Control
36385  * [26] | RW | 0x0 | Mask Byte Control
36386  * [27] | RW | 0x0 | Mask Byte Control
36387  * [28] | RW | 0x0 | Mask Byte Control
36388  * [29] | RW | 0x0 | Mask Byte Control
36389  * [30] | RW | 0x0 | Source Address
36390  * [31] | RW | 0x0 | Address Enable
36391  *
36392  */
36393 /*
36394  * Field : MAC Address20 [47:32] - addrhi
36395  *
36396  * This field contains the upper 16 bits (47:32) of the 21th 6-byte MAC address.
36397  *
36398  * Field Access Macros:
36399  *
36400  */
36401 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
36402 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_LSB 0
36403 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
36404 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_MSB 15
36405 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
36406 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_WIDTH 16
36407 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
36408 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET_MSK 0x0000ffff
36409 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
36410 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_CLR_MSK 0xffff0000
36411 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
36412 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_RESET 0xffff
36413 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI field value from a register. */
36414 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
36415 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value suitable for setting the register. */
36416 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
36417 
36418 /*
36419  * Field : Mask Byte Control - mbc_0
36420  *
36421  * This array of bits are mask control bits for comparison of each of the MAC
36422  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36423  * received DA or SA with the contents of MAC Address20 high and low registers.
36424  * Each bit controls the masking of the bytes. You can filter a group of addresses
36425  * (known as group address filtering) by masking one or more bytes of the address.
36426  *
36427  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36428  *
36429  * Field Enumeration Values:
36430  *
36431  * Enum | Value | Description
36432  * :----------------------------------------------|:------|:------------------------------------
36433  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36434  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36435  *
36436  * Field Access Macros:
36437  *
36438  */
36439 /*
36440  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
36441  *
36442  * Byte is unmasked (i.e. is compared)
36443  */
36444 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED 0x0
36445 /*
36446  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
36447  *
36448  * Byte is masked (i.e. not compared)
36449  */
36450 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED 0x1
36451 
36452 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
36453 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_LSB 24
36454 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
36455 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_MSB 24
36456 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
36457 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_WIDTH 1
36458 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
36459 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET_MSK 0x01000000
36460 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
36461 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_CLR_MSK 0xfeffffff
36462 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
36463 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_RESET 0x0
36464 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 field value from a register. */
36465 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
36466 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value suitable for setting the register. */
36467 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
36468 
36469 /*
36470  * Field : Mask Byte Control - mbc_1
36471  *
36472  * This array of bits are mask control bits for comparison of each of the MAC
36473  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36474  * received DA or SA with the contents of MAC Address20 high and low registers.
36475  * Each bit controls the masking of the bytes. You can filter a group of addresses
36476  * (known as group address filtering) by masking one or more bytes of the address.
36477  *
36478  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36479  *
36480  * Field Enumeration Values:
36481  *
36482  * Enum | Value | Description
36483  * :----------------------------------------------|:------|:------------------------------------
36484  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36485  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36486  *
36487  * Field Access Macros:
36488  *
36489  */
36490 /*
36491  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
36492  *
36493  * Byte is unmasked (i.e. is compared)
36494  */
36495 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED 0x0
36496 /*
36497  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
36498  *
36499  * Byte is masked (i.e. not compared)
36500  */
36501 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED 0x1
36502 
36503 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
36504 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_LSB 25
36505 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
36506 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_MSB 25
36507 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
36508 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_WIDTH 1
36509 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
36510 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET_MSK 0x02000000
36511 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
36512 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_CLR_MSK 0xfdffffff
36513 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
36514 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_RESET 0x0
36515 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 field value from a register. */
36516 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
36517 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value suitable for setting the register. */
36518 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
36519 
36520 /*
36521  * Field : Mask Byte Control - mbc_2
36522  *
36523  * This array of bits are mask control bits for comparison of each of the MAC
36524  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36525  * received DA or SA with the contents of MAC Address20 high and low registers.
36526  * Each bit controls the masking of the bytes. You can filter a group of addresses
36527  * (known as group address filtering) by masking one or more bytes of the address.
36528  *
36529  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36530  *
36531  * Field Enumeration Values:
36532  *
36533  * Enum | Value | Description
36534  * :----------------------------------------------|:------|:------------------------------------
36535  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36536  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36537  *
36538  * Field Access Macros:
36539  *
36540  */
36541 /*
36542  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
36543  *
36544  * Byte is unmasked (i.e. is compared)
36545  */
36546 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED 0x0
36547 /*
36548  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
36549  *
36550  * Byte is masked (i.e. not compared)
36551  */
36552 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED 0x1
36553 
36554 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
36555 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_LSB 26
36556 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
36557 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_MSB 26
36558 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
36559 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_WIDTH 1
36560 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
36561 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET_MSK 0x04000000
36562 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
36563 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_CLR_MSK 0xfbffffff
36564 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
36565 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_RESET 0x0
36566 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 field value from a register. */
36567 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
36568 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value suitable for setting the register. */
36569 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
36570 
36571 /*
36572  * Field : Mask Byte Control - mbc_3
36573  *
36574  * This array of bits are mask control bits for comparison of each of the MAC
36575  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36576  * received DA or SA with the contents of MAC Address20 high and low registers.
36577  * Each bit controls the masking of the bytes. You can filter a group of addresses
36578  * (known as group address filtering) by masking one or more bytes of the address.
36579  *
36580  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36581  *
36582  * Field Enumeration Values:
36583  *
36584  * Enum | Value | Description
36585  * :----------------------------------------------|:------|:------------------------------------
36586  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36587  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36588  *
36589  * Field Access Macros:
36590  *
36591  */
36592 /*
36593  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
36594  *
36595  * Byte is unmasked (i.e. is compared)
36596  */
36597 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED 0x0
36598 /*
36599  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
36600  *
36601  * Byte is masked (i.e. not compared)
36602  */
36603 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED 0x1
36604 
36605 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
36606 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_LSB 27
36607 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
36608 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_MSB 27
36609 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
36610 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_WIDTH 1
36611 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
36612 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET_MSK 0x08000000
36613 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
36614 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_CLR_MSK 0xf7ffffff
36615 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
36616 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_RESET 0x0
36617 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 field value from a register. */
36618 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
36619 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value suitable for setting the register. */
36620 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
36621 
36622 /*
36623  * Field : Mask Byte Control - mbc_4
36624  *
36625  * This array of bits are mask control bits for comparison of each of the MAC
36626  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36627  * received DA or SA with the contents of MAC Address20 high and low registers.
36628  * Each bit controls the masking of the bytes. You can filter a group of addresses
36629  * (known as group address filtering) by masking one or more bytes of the address.
36630  *
36631  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36632  *
36633  * Field Enumeration Values:
36634  *
36635  * Enum | Value | Description
36636  * :----------------------------------------------|:------|:------------------------------------
36637  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36638  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36639  *
36640  * Field Access Macros:
36641  *
36642  */
36643 /*
36644  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
36645  *
36646  * Byte is unmasked (i.e. is compared)
36647  */
36648 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED 0x0
36649 /*
36650  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
36651  *
36652  * Byte is masked (i.e. not compared)
36653  */
36654 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED 0x1
36655 
36656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
36657 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_LSB 28
36658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
36659 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_MSB 28
36660 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
36661 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_WIDTH 1
36662 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
36663 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET_MSK 0x10000000
36664 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
36665 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_CLR_MSK 0xefffffff
36666 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
36667 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_RESET 0x0
36668 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 field value from a register. */
36669 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
36670 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value suitable for setting the register. */
36671 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
36672 
36673 /*
36674  * Field : Mask Byte Control - mbc_5
36675  *
36676  * This array of bits are mask control bits for comparison of each of the MAC
36677  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36678  * received DA or SA with the contents of MAC Address20 high and low registers.
36679  * Each bit controls the masking of the bytes. You can filter a group of addresses
36680  * (known as group address filtering) by masking one or more bytes of the address.
36681  *
36682  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36683  *
36684  * Field Enumeration Values:
36685  *
36686  * Enum | Value | Description
36687  * :----------------------------------------------|:------|:------------------------------------
36688  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36689  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36690  *
36691  * Field Access Macros:
36692  *
36693  */
36694 /*
36695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
36696  *
36697  * Byte is unmasked (i.e. is compared)
36698  */
36699 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED 0x0
36700 /*
36701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
36702  *
36703  * Byte is masked (i.e. not compared)
36704  */
36705 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED 0x1
36706 
36707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
36708 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_LSB 29
36709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
36710 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_MSB 29
36711 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
36712 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_WIDTH 1
36713 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
36714 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET_MSK 0x20000000
36715 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
36716 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_CLR_MSK 0xdfffffff
36717 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
36718 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_RESET 0x0
36719 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 field value from a register. */
36720 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
36721 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value suitable for setting the register. */
36722 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
36723 
36724 /*
36725  * Field : Source Address - sa
36726  *
36727  * When this bit is enabled, the MAC Address20[47:0] is used to compare with the SA
36728  * fields of the received frame. When this bit is disabled, the MAC Address20[47:0]
36729  * is used to compare with the DA fields of the received frame.
36730  *
36731  * Field Enumeration Values:
36732  *
36733  * Enum | Value | Description
36734  * :----------------------------------------|:------|:-----------------------------
36735  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
36736  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END | 0x1 | MAC address compare enabled
36737  *
36738  * Field Access Macros:
36739  *
36740  */
36741 /*
36742  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
36743  *
36744  * MAC address compare disabled
36745  */
36746 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD 0x0
36747 /*
36748  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
36749  *
36750  * MAC address compare enabled
36751  */
36752 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END 0x1
36753 
36754 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
36755 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_LSB 30
36756 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
36757 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_MSB 30
36758 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
36759 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_WIDTH 1
36760 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
36761 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET_MSK 0x40000000
36762 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
36763 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_CLR_MSK 0xbfffffff
36764 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
36765 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_RESET 0x0
36766 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA field value from a register. */
36767 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
36768 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value suitable for setting the register. */
36769 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
36770 
36771 /*
36772  * Field : Address Enable - ae
36773  *
36774  * When this bit is enabled, the address filter block uses the 21th MAC address for
36775  * perfect filtering. When this bit is disabled, the address filter block ignores
36776  * the address for filtering.
36777  *
36778  * Field Enumeration Values:
36779  *
36780  * Enum | Value | Description
36781  * :----------------------------------------|:------|:--------------------------------------
36782  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
36783  * ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
36784  *
36785  * Field Access Macros:
36786  *
36787  */
36788 /*
36789  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
36790  *
36791  * Second MAC address filtering disabled
36792  */
36793 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD 0x0
36794 /*
36795  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
36796  *
36797  * Second MAC address filtering enabled
36798  */
36799 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END 0x1
36800 
36801 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
36802 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_LSB 31
36803 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
36804 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_MSB 31
36805 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
36806 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_WIDTH 1
36807 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
36808 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET_MSK 0x80000000
36809 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
36810 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_CLR_MSK 0x7fffffff
36811 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
36812 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_RESET 0x0
36813 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE field value from a register. */
36814 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
36815 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value suitable for setting the register. */
36816 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
36817 
36818 #ifndef __ASSEMBLY__
36819 /*
36820  * WARNING: The C register and register group struct declarations are provided for
36821  * convenience and illustrative purposes. They should, however, be used with
36822  * caution as the C language standard provides no guarantees about the alignment or
36823  * atomicity of device memory accesses. The recommended practice for writing
36824  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36825  * alt_write_word() functions.
36826  *
36827  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH.
36828  */
36829 struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s
36830 {
36831  uint32_t addrhi : 16; /* MAC Address20 [47:32] */
36832  uint32_t : 8; /* *UNDEFINED* */
36833  uint32_t mbc_0 : 1; /* Mask Byte Control */
36834  uint32_t mbc_1 : 1; /* Mask Byte Control */
36835  uint32_t mbc_2 : 1; /* Mask Byte Control */
36836  uint32_t mbc_3 : 1; /* Mask Byte Control */
36837  uint32_t mbc_4 : 1; /* Mask Byte Control */
36838  uint32_t mbc_5 : 1; /* Mask Byte Control */
36839  uint32_t sa : 1; /* Source Address */
36840  uint32_t ae : 1; /* Address Enable */
36841 };
36842 
36843 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH. */
36844 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t;
36845 #endif /* __ASSEMBLY__ */
36846 
36847 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register from the beginning of the component. */
36848 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST 0x820
36849 /* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register. */
36850 #define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST))
36851 
36852 /*
36853  * Register : Register 521 (MAC Address20 Low Register) - MAC_Address20_Low
36854  *
36855  * The MAC Address20 Low register holds the lower 32 bits of the 21th 6-byte MAC
36856  * address of the station.
36857  *
36858  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
36859  * format.
36860  *
36861  * Register Layout
36862  *
36863  * Bits | Access | Reset | Description
36864  * :-------|:-------|:-----------|:---------------------
36865  * [31:0] | RW | 0xffffffff | MAC Address20 [31:0]
36866  *
36867  */
36868 /*
36869  * Field : MAC Address20 [31:0] - addrlo
36870  *
36871  * This field contains the lower 32 bits of the 21th 6-byte MAC address. The
36872  * content of this field is undefined until loaded by software after the
36873  * initialization process.
36874  *
36875  * Field Access Macros:
36876  *
36877  */
36878 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
36879 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_LSB 0
36880 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
36881 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_MSB 31
36882 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
36883 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_WIDTH 32
36884 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
36885 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET_MSK 0xffffffff
36886 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
36887 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_CLR_MSK 0x00000000
36888 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
36889 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_RESET 0xffffffff
36890 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO field value from a register. */
36891 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
36892 /* Produces a ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value suitable for setting the register. */
36893 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
36894 
36895 #ifndef __ASSEMBLY__
36896 /*
36897  * WARNING: The C register and register group struct declarations are provided for
36898  * convenience and illustrative purposes. They should, however, be used with
36899  * caution as the C language standard provides no guarantees about the alignment or
36900  * atomicity of device memory accesses. The recommended practice for writing
36901  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
36902  * alt_write_word() functions.
36903  *
36904  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW.
36905  */
36906 struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s
36907 {
36908  uint32_t addrlo : 32; /* MAC Address20 [31:0] */
36909 };
36910 
36911 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW. */
36912 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s ALT_EMAC_GMAC_MAC_ADDR20_LOW_t;
36913 #endif /* __ASSEMBLY__ */
36914 
36915 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register from the beginning of the component. */
36916 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST 0x824
36917 /* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register. */
36918 #define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST))
36919 
36920 /*
36921  * Register : Register 522 (MAC Address21 High Register) - MAC_Address21_High
36922  *
36923  * The MAC Address21 High register holds the upper 16 bits of the 22th 6-byte MAC
36924  * address of the station. Because the MAC address registers are configured to be
36925  * double-synchronized to the (G)MII clock domains, the synchronization is
36926  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
36927  * endian mode) of the MAC Address21 Low Register are written. For proper
36928  * synchronization updates, the consecutive writes to this Address Low Register
36929  * should be performed after at least four clock cycles in the destination clock
36930  * domain.
36931  *
36932  * Note that all MAC Address High registers (except MAC Address0 High) have the
36933  * same format.
36934  *
36935  * Register Layout
36936  *
36937  * Bits | Access | Reset | Description
36938  * :--------|:-------|:-------|:----------------------
36939  * [15:0] | RW | 0xffff | MAC Address21 [47:32]
36940  * [23:16] | ??? | 0x0 | *UNDEFINED*
36941  * [24] | RW | 0x0 | Mask Byte Control
36942  * [25] | RW | 0x0 | Mask Byte Control
36943  * [26] | RW | 0x0 | Mask Byte Control
36944  * [27] | RW | 0x0 | Mask Byte Control
36945  * [28] | RW | 0x0 | Mask Byte Control
36946  * [29] | RW | 0x0 | Mask Byte Control
36947  * [30] | RW | 0x0 | Source Address
36948  * [31] | RW | 0x0 | Address Enable
36949  *
36950  */
36951 /*
36952  * Field : MAC Address21 [47:32] - addrhi
36953  *
36954  * This field contains the upper 16 bits (47:32) of the 22th 6-byte MAC address.
36955  *
36956  * Field Access Macros:
36957  *
36958  */
36959 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
36960 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_LSB 0
36961 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
36962 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_MSB 15
36963 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
36964 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_WIDTH 16
36965 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
36966 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET_MSK 0x0000ffff
36967 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
36968 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_CLR_MSK 0xffff0000
36969 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
36970 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_RESET 0xffff
36971 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI field value from a register. */
36972 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
36973 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value suitable for setting the register. */
36974 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
36975 
36976 /*
36977  * Field : Mask Byte Control - mbc_0
36978  *
36979  * This array of bits are mask control bits for comparison of each of the MAC
36980  * Address bytes. When masked, the MAC does not compare the corresponding byte of
36981  * received DA or SA with the contents of MAC Address21 high and low registers.
36982  * Each bit controls the masking of the bytes. You can filter a group of addresses
36983  * (known as group address filtering) by masking one or more bytes of the address.
36984  *
36985  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
36986  *
36987  * Field Enumeration Values:
36988  *
36989  * Enum | Value | Description
36990  * :----------------------------------------------|:------|:------------------------------------
36991  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
36992  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
36993  *
36994  * Field Access Macros:
36995  *
36996  */
36997 /*
36998  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
36999  *
37000  * Byte is unmasked (i.e. is compared)
37001  */
37002 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED 0x0
37003 /*
37004  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
37005  *
37006  * Byte is masked (i.e. not compared)
37007  */
37008 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED 0x1
37009 
37010 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
37011 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_LSB 24
37012 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
37013 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_MSB 24
37014 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
37015 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_WIDTH 1
37016 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
37017 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET_MSK 0x01000000
37018 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
37019 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_CLR_MSK 0xfeffffff
37020 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
37021 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_RESET 0x0
37022 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 field value from a register. */
37023 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
37024 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value suitable for setting the register. */
37025 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
37026 
37027 /*
37028  * Field : Mask Byte Control - mbc_1
37029  *
37030  * This array of bits are mask control bits for comparison of each of the MAC
37031  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37032  * received DA or SA with the contents of MAC Address21 high and low registers.
37033  * Each bit controls the masking of the bytes. You can filter a group of addresses
37034  * (known as group address filtering) by masking one or more bytes of the address.
37035  *
37036  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37037  *
37038  * Field Enumeration Values:
37039  *
37040  * Enum | Value | Description
37041  * :----------------------------------------------|:------|:------------------------------------
37042  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37043  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37044  *
37045  * Field Access Macros:
37046  *
37047  */
37048 /*
37049  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
37050  *
37051  * Byte is unmasked (i.e. is compared)
37052  */
37053 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED 0x0
37054 /*
37055  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
37056  *
37057  * Byte is masked (i.e. not compared)
37058  */
37059 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED 0x1
37060 
37061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
37062 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_LSB 25
37063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
37064 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_MSB 25
37065 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
37066 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_WIDTH 1
37067 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
37068 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET_MSK 0x02000000
37069 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
37070 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_CLR_MSK 0xfdffffff
37071 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
37072 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_RESET 0x0
37073 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 field value from a register. */
37074 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
37075 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value suitable for setting the register. */
37076 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
37077 
37078 /*
37079  * Field : Mask Byte Control - mbc_2
37080  *
37081  * This array of bits are mask control bits for comparison of each of the MAC
37082  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37083  * received DA or SA with the contents of MAC Address21 high and low registers.
37084  * Each bit controls the masking of the bytes. You can filter a group of addresses
37085  * (known as group address filtering) by masking one or more bytes of the address.
37086  *
37087  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37088  *
37089  * Field Enumeration Values:
37090  *
37091  * Enum | Value | Description
37092  * :----------------------------------------------|:------|:------------------------------------
37093  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37094  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37095  *
37096  * Field Access Macros:
37097  *
37098  */
37099 /*
37100  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
37101  *
37102  * Byte is unmasked (i.e. is compared)
37103  */
37104 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED 0x0
37105 /*
37106  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
37107  *
37108  * Byte is masked (i.e. not compared)
37109  */
37110 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED 0x1
37111 
37112 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
37113 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_LSB 26
37114 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
37115 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_MSB 26
37116 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
37117 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_WIDTH 1
37118 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
37119 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET_MSK 0x04000000
37120 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
37121 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_CLR_MSK 0xfbffffff
37122 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
37123 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_RESET 0x0
37124 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 field value from a register. */
37125 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
37126 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value suitable for setting the register. */
37127 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
37128 
37129 /*
37130  * Field : Mask Byte Control - mbc_3
37131  *
37132  * This array of bits are mask control bits for comparison of each of the MAC
37133  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37134  * received DA or SA with the contents of MAC Address21 high and low registers.
37135  * Each bit controls the masking of the bytes. You can filter a group of addresses
37136  * (known as group address filtering) by masking one or more bytes of the address.
37137  *
37138  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37139  *
37140  * Field Enumeration Values:
37141  *
37142  * Enum | Value | Description
37143  * :----------------------------------------------|:------|:------------------------------------
37144  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37145  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37146  *
37147  * Field Access Macros:
37148  *
37149  */
37150 /*
37151  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
37152  *
37153  * Byte is unmasked (i.e. is compared)
37154  */
37155 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED 0x0
37156 /*
37157  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
37158  *
37159  * Byte is masked (i.e. not compared)
37160  */
37161 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED 0x1
37162 
37163 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
37164 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_LSB 27
37165 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
37166 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_MSB 27
37167 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
37168 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_WIDTH 1
37169 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
37170 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET_MSK 0x08000000
37171 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
37172 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_CLR_MSK 0xf7ffffff
37173 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
37174 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_RESET 0x0
37175 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 field value from a register. */
37176 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
37177 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value suitable for setting the register. */
37178 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
37179 
37180 /*
37181  * Field : Mask Byte Control - mbc_4
37182  *
37183  * This array of bits are mask control bits for comparison of each of the MAC
37184  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37185  * received DA or SA with the contents of MAC Address21 high and low registers.
37186  * Each bit controls the masking of the bytes. You can filter a group of addresses
37187  * (known as group address filtering) by masking one or more bytes of the address.
37188  *
37189  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37190  *
37191  * Field Enumeration Values:
37192  *
37193  * Enum | Value | Description
37194  * :----------------------------------------------|:------|:------------------------------------
37195  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37196  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37197  *
37198  * Field Access Macros:
37199  *
37200  */
37201 /*
37202  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
37203  *
37204  * Byte is unmasked (i.e. is compared)
37205  */
37206 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED 0x0
37207 /*
37208  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
37209  *
37210  * Byte is masked (i.e. not compared)
37211  */
37212 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED 0x1
37213 
37214 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
37215 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_LSB 28
37216 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
37217 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_MSB 28
37218 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
37219 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_WIDTH 1
37220 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
37221 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET_MSK 0x10000000
37222 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
37223 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_CLR_MSK 0xefffffff
37224 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
37225 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_RESET 0x0
37226 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 field value from a register. */
37227 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
37228 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value suitable for setting the register. */
37229 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
37230 
37231 /*
37232  * Field : Mask Byte Control - mbc_5
37233  *
37234  * This array of bits are mask control bits for comparison of each of the MAC
37235  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37236  * received DA or SA with the contents of MAC Address21 high and low registers.
37237  * Each bit controls the masking of the bytes. You can filter a group of addresses
37238  * (known as group address filtering) by masking one or more bytes of the address.
37239  *
37240  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37241  *
37242  * Field Enumeration Values:
37243  *
37244  * Enum | Value | Description
37245  * :----------------------------------------------|:------|:------------------------------------
37246  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37247  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37248  *
37249  * Field Access Macros:
37250  *
37251  */
37252 /*
37253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
37254  *
37255  * Byte is unmasked (i.e. is compared)
37256  */
37257 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED 0x0
37258 /*
37259  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
37260  *
37261  * Byte is masked (i.e. not compared)
37262  */
37263 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED 0x1
37264 
37265 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
37266 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_LSB 29
37267 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
37268 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_MSB 29
37269 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
37270 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_WIDTH 1
37271 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
37272 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET_MSK 0x20000000
37273 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
37274 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_CLR_MSK 0xdfffffff
37275 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
37276 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_RESET 0x0
37277 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 field value from a register. */
37278 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
37279 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value suitable for setting the register. */
37280 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
37281 
37282 /*
37283  * Field : Source Address - sa
37284  *
37285  * When this bit is enabled, the MAC Address21[47:0] is used to compare with the SA
37286  * fields of the received frame. When this bit is disabled, the MAC Address21[47:0]
37287  * is used to compare with the DA fields of the received frame.
37288  *
37289  * Field Enumeration Values:
37290  *
37291  * Enum | Value | Description
37292  * :----------------------------------------|:------|:-----------------------------
37293  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
37294  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END | 0x1 | MAC address compare enabled
37295  *
37296  * Field Access Macros:
37297  *
37298  */
37299 /*
37300  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
37301  *
37302  * MAC address compare disabled
37303  */
37304 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD 0x0
37305 /*
37306  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
37307  *
37308  * MAC address compare enabled
37309  */
37310 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END 0x1
37311 
37312 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
37313 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_LSB 30
37314 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
37315 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_MSB 30
37316 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
37317 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_WIDTH 1
37318 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
37319 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET_MSK 0x40000000
37320 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
37321 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_CLR_MSK 0xbfffffff
37322 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
37323 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_RESET 0x0
37324 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA field value from a register. */
37325 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
37326 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value suitable for setting the register. */
37327 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
37328 
37329 /*
37330  * Field : Address Enable - ae
37331  *
37332  * When this bit is enabled, the address filter block uses the 22th MAC address for
37333  * perfect filtering. When this bit is disabled, the address filter block ignores
37334  * the address for filtering.
37335  *
37336  * Field Enumeration Values:
37337  *
37338  * Enum | Value | Description
37339  * :----------------------------------------|:------|:--------------------------------------
37340  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
37341  * ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
37342  *
37343  * Field Access Macros:
37344  *
37345  */
37346 /*
37347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
37348  *
37349  * Second MAC address filtering disabled
37350  */
37351 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD 0x0
37352 /*
37353  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
37354  *
37355  * Second MAC address filtering enabled
37356  */
37357 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END 0x1
37358 
37359 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
37360 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_LSB 31
37361 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
37362 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_MSB 31
37363 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
37364 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_WIDTH 1
37365 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
37366 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET_MSK 0x80000000
37367 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
37368 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_CLR_MSK 0x7fffffff
37369 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
37370 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_RESET 0x0
37371 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE field value from a register. */
37372 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
37373 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value suitable for setting the register. */
37374 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
37375 
37376 #ifndef __ASSEMBLY__
37377 /*
37378  * WARNING: The C register and register group struct declarations are provided for
37379  * convenience and illustrative purposes. They should, however, be used with
37380  * caution as the C language standard provides no guarantees about the alignment or
37381  * atomicity of device memory accesses. The recommended practice for writing
37382  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37383  * alt_write_word() functions.
37384  *
37385  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH.
37386  */
37387 struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s
37388 {
37389  uint32_t addrhi : 16; /* MAC Address21 [47:32] */
37390  uint32_t : 8; /* *UNDEFINED* */
37391  uint32_t mbc_0 : 1; /* Mask Byte Control */
37392  uint32_t mbc_1 : 1; /* Mask Byte Control */
37393  uint32_t mbc_2 : 1; /* Mask Byte Control */
37394  uint32_t mbc_3 : 1; /* Mask Byte Control */
37395  uint32_t mbc_4 : 1; /* Mask Byte Control */
37396  uint32_t mbc_5 : 1; /* Mask Byte Control */
37397  uint32_t sa : 1; /* Source Address */
37398  uint32_t ae : 1; /* Address Enable */
37399 };
37400 
37401 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH. */
37402 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t;
37403 #endif /* __ASSEMBLY__ */
37404 
37405 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register from the beginning of the component. */
37406 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST 0x828
37407 /* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register. */
37408 #define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST))
37409 
37410 /*
37411  * Register : Register 523 (MAC Address21 Low Register) - MAC_Address21_Low
37412  *
37413  * The MAC Address21 Low register holds the lower 32 bits of the 22th 6-byte MAC
37414  * address of the station.
37415  *
37416  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
37417  * format.
37418  *
37419  * Register Layout
37420  *
37421  * Bits | Access | Reset | Description
37422  * :-------|:-------|:-----------|:---------------------
37423  * [31:0] | RW | 0xffffffff | MAC Address21 [31:0]
37424  *
37425  */
37426 /*
37427  * Field : MAC Address21 [31:0] - addrlo
37428  *
37429  * This field contains the lower 32 bits of the 22th 6-byte MAC address. The
37430  * content of this field is undefined until loaded by software after the
37431  * initialization process.
37432  *
37433  * Field Access Macros:
37434  *
37435  */
37436 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
37437 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_LSB 0
37438 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
37439 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_MSB 31
37440 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
37441 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_WIDTH 32
37442 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
37443 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET_MSK 0xffffffff
37444 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
37445 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_CLR_MSK 0x00000000
37446 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
37447 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_RESET 0xffffffff
37448 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO field value from a register. */
37449 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
37450 /* Produces a ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value suitable for setting the register. */
37451 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
37452 
37453 #ifndef __ASSEMBLY__
37454 /*
37455  * WARNING: The C register and register group struct declarations are provided for
37456  * convenience and illustrative purposes. They should, however, be used with
37457  * caution as the C language standard provides no guarantees about the alignment or
37458  * atomicity of device memory accesses. The recommended practice for writing
37459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37460  * alt_write_word() functions.
37461  *
37462  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW.
37463  */
37464 struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s
37465 {
37466  uint32_t addrlo : 32; /* MAC Address21 [31:0] */
37467 };
37468 
37469 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW. */
37470 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s ALT_EMAC_GMAC_MAC_ADDR21_LOW_t;
37471 #endif /* __ASSEMBLY__ */
37472 
37473 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register from the beginning of the component. */
37474 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST 0x82c
37475 /* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register. */
37476 #define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST))
37477 
37478 /*
37479  * Register : Register 524 (MAC Address22 High Register) - MAC_Address22_High
37480  *
37481  * The MAC Address22 High register holds the upper 16 bits of the 23th 6-byte MAC
37482  * address of the station. Because the MAC address registers are configured to be
37483  * double-synchronized to the (G)MII clock domains, the synchronization is
37484  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
37485  * endian mode) of the MAC Address22 Low Register are written. For proper
37486  * synchronization updates, the consecutive writes to this Address Low Register
37487  * should be performed after at least four clock cycles in the destination clock
37488  * domain.
37489  *
37490  * Note that all MAC Address High registers (except MAC Address0 High) have the
37491  * same format.
37492  *
37493  * Register Layout
37494  *
37495  * Bits | Access | Reset | Description
37496  * :--------|:-------|:-------|:----------------------
37497  * [15:0] | RW | 0xffff | MAC Address22 [47:32]
37498  * [23:16] | ??? | 0x0 | *UNDEFINED*
37499  * [24] | RW | 0x0 | Mask Byte Control
37500  * [25] | RW | 0x0 | Mask Byte Control
37501  * [26] | RW | 0x0 | Mask Byte Control
37502  * [27] | RW | 0x0 | Mask Byte Control
37503  * [28] | RW | 0x0 | Mask Byte Control
37504  * [29] | RW | 0x0 | Mask Byte Control
37505  * [30] | RW | 0x0 | Source Address
37506  * [31] | RW | 0x0 | Address Enable
37507  *
37508  */
37509 /*
37510  * Field : MAC Address22 [47:32] - addrhi
37511  *
37512  * This field contains the upper 16 bits (47:32) of the 23th 6-byte MAC address.
37513  *
37514  * Field Access Macros:
37515  *
37516  */
37517 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
37518 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_LSB 0
37519 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
37520 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_MSB 15
37521 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
37522 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_WIDTH 16
37523 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
37524 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET_MSK 0x0000ffff
37525 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
37526 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_CLR_MSK 0xffff0000
37527 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
37528 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_RESET 0xffff
37529 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI field value from a register. */
37530 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
37531 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value suitable for setting the register. */
37532 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
37533 
37534 /*
37535  * Field : Mask Byte Control - mbc_0
37536  *
37537  * This array of bits are mask control bits for comparison of each of the MAC
37538  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37539  * received DA or SA with the contents of MAC Address22 high and low registers.
37540  * Each bit controls the masking of the bytes. You can filter a group of addresses
37541  * (known as group address filtering) by masking one or more bytes of the address.
37542  *
37543  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37544  *
37545  * Field Enumeration Values:
37546  *
37547  * Enum | Value | Description
37548  * :----------------------------------------------|:------|:------------------------------------
37549  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37550  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37551  *
37552  * Field Access Macros:
37553  *
37554  */
37555 /*
37556  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
37557  *
37558  * Byte is unmasked (i.e. is compared)
37559  */
37560 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED 0x0
37561 /*
37562  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
37563  *
37564  * Byte is masked (i.e. not compared)
37565  */
37566 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED 0x1
37567 
37568 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
37569 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_LSB 24
37570 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
37571 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_MSB 24
37572 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
37573 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_WIDTH 1
37574 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
37575 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET_MSK 0x01000000
37576 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
37577 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_CLR_MSK 0xfeffffff
37578 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
37579 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_RESET 0x0
37580 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 field value from a register. */
37581 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
37582 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value suitable for setting the register. */
37583 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
37584 
37585 /*
37586  * Field : Mask Byte Control - mbc_1
37587  *
37588  * This array of bits are mask control bits for comparison of each of the MAC
37589  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37590  * received DA or SA with the contents of MAC Address22 high and low registers.
37591  * Each bit controls the masking of the bytes. You can filter a group of addresses
37592  * (known as group address filtering) by masking one or more bytes of the address.
37593  *
37594  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37595  *
37596  * Field Enumeration Values:
37597  *
37598  * Enum | Value | Description
37599  * :----------------------------------------------|:------|:------------------------------------
37600  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37601  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37602  *
37603  * Field Access Macros:
37604  *
37605  */
37606 /*
37607  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
37608  *
37609  * Byte is unmasked (i.e. is compared)
37610  */
37611 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED 0x0
37612 /*
37613  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
37614  *
37615  * Byte is masked (i.e. not compared)
37616  */
37617 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED 0x1
37618 
37619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
37620 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_LSB 25
37621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
37622 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_MSB 25
37623 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
37624 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_WIDTH 1
37625 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
37626 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET_MSK 0x02000000
37627 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
37628 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_CLR_MSK 0xfdffffff
37629 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
37630 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_RESET 0x0
37631 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 field value from a register. */
37632 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
37633 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value suitable for setting the register. */
37634 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
37635 
37636 /*
37637  * Field : Mask Byte Control - mbc_2
37638  *
37639  * This array of bits are mask control bits for comparison of each of the MAC
37640  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37641  * received DA or SA with the contents of MAC Address22 high and low registers.
37642  * Each bit controls the masking of the bytes. You can filter a group of addresses
37643  * (known as group address filtering) by masking one or more bytes of the address.
37644  *
37645  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37646  *
37647  * Field Enumeration Values:
37648  *
37649  * Enum | Value | Description
37650  * :----------------------------------------------|:------|:------------------------------------
37651  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37652  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37653  *
37654  * Field Access Macros:
37655  *
37656  */
37657 /*
37658  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
37659  *
37660  * Byte is unmasked (i.e. is compared)
37661  */
37662 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED 0x0
37663 /*
37664  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
37665  *
37666  * Byte is masked (i.e. not compared)
37667  */
37668 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED 0x1
37669 
37670 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
37671 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_LSB 26
37672 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
37673 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_MSB 26
37674 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
37675 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_WIDTH 1
37676 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
37677 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET_MSK 0x04000000
37678 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
37679 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_CLR_MSK 0xfbffffff
37680 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
37681 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_RESET 0x0
37682 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 field value from a register. */
37683 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
37684 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value suitable for setting the register. */
37685 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
37686 
37687 /*
37688  * Field : Mask Byte Control - mbc_3
37689  *
37690  * This array of bits are mask control bits for comparison of each of the MAC
37691  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37692  * received DA or SA with the contents of MAC Address22 high and low registers.
37693  * Each bit controls the masking of the bytes. You can filter a group of addresses
37694  * (known as group address filtering) by masking one or more bytes of the address.
37695  *
37696  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37697  *
37698  * Field Enumeration Values:
37699  *
37700  * Enum | Value | Description
37701  * :----------------------------------------------|:------|:------------------------------------
37702  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37703  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37704  *
37705  * Field Access Macros:
37706  *
37707  */
37708 /*
37709  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
37710  *
37711  * Byte is unmasked (i.e. is compared)
37712  */
37713 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED 0x0
37714 /*
37715  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
37716  *
37717  * Byte is masked (i.e. not compared)
37718  */
37719 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED 0x1
37720 
37721 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
37722 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_LSB 27
37723 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
37724 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_MSB 27
37725 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
37726 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_WIDTH 1
37727 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
37728 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET_MSK 0x08000000
37729 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
37730 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_CLR_MSK 0xf7ffffff
37731 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
37732 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_RESET 0x0
37733 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 field value from a register. */
37734 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
37735 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value suitable for setting the register. */
37736 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
37737 
37738 /*
37739  * Field : Mask Byte Control - mbc_4
37740  *
37741  * This array of bits are mask control bits for comparison of each of the MAC
37742  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37743  * received DA or SA with the contents of MAC Address22 high and low registers.
37744  * Each bit controls the masking of the bytes. You can filter a group of addresses
37745  * (known as group address filtering) by masking one or more bytes of the address.
37746  *
37747  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37748  *
37749  * Field Enumeration Values:
37750  *
37751  * Enum | Value | Description
37752  * :----------------------------------------------|:------|:------------------------------------
37753  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37754  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37755  *
37756  * Field Access Macros:
37757  *
37758  */
37759 /*
37760  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
37761  *
37762  * Byte is unmasked (i.e. is compared)
37763  */
37764 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED 0x0
37765 /*
37766  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
37767  *
37768  * Byte is masked (i.e. not compared)
37769  */
37770 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED 0x1
37771 
37772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
37773 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_LSB 28
37774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
37775 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_MSB 28
37776 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
37777 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_WIDTH 1
37778 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
37779 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET_MSK 0x10000000
37780 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
37781 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_CLR_MSK 0xefffffff
37782 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
37783 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_RESET 0x0
37784 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 field value from a register. */
37785 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
37786 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value suitable for setting the register. */
37787 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
37788 
37789 /*
37790  * Field : Mask Byte Control - mbc_5
37791  *
37792  * This array of bits are mask control bits for comparison of each of the MAC
37793  * Address bytes. When masked, the MAC does not compare the corresponding byte of
37794  * received DA or SA with the contents of MAC Address22 high and low registers.
37795  * Each bit controls the masking of the bytes. You can filter a group of addresses
37796  * (known as group address filtering) by masking one or more bytes of the address.
37797  *
37798  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
37799  *
37800  * Field Enumeration Values:
37801  *
37802  * Enum | Value | Description
37803  * :----------------------------------------------|:------|:------------------------------------
37804  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
37805  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
37806  *
37807  * Field Access Macros:
37808  *
37809  */
37810 /*
37811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
37812  *
37813  * Byte is unmasked (i.e. is compared)
37814  */
37815 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED 0x0
37816 /*
37817  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
37818  *
37819  * Byte is masked (i.e. not compared)
37820  */
37821 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED 0x1
37822 
37823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
37824 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_LSB 29
37825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
37826 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_MSB 29
37827 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
37828 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_WIDTH 1
37829 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
37830 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET_MSK 0x20000000
37831 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
37832 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_CLR_MSK 0xdfffffff
37833 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
37834 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_RESET 0x0
37835 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 field value from a register. */
37836 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
37837 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value suitable for setting the register. */
37838 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
37839 
37840 /*
37841  * Field : Source Address - sa
37842  *
37843  * When this bit is enabled, the MAC Address22[47:0] is used to compare with the SA
37844  * fields of the received frame. When this bit is disabled, the MAC Address22[47:0]
37845  * is used to compare with the DA fields of the received frame.
37846  *
37847  * Field Enumeration Values:
37848  *
37849  * Enum | Value | Description
37850  * :----------------------------------------|:------|:-----------------------------
37851  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
37852  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END | 0x1 | MAC address compare enabled
37853  *
37854  * Field Access Macros:
37855  *
37856  */
37857 /*
37858  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
37859  *
37860  * MAC address compare disabled
37861  */
37862 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD 0x0
37863 /*
37864  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
37865  *
37866  * MAC address compare enabled
37867  */
37868 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END 0x1
37869 
37870 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
37871 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_LSB 30
37872 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
37873 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_MSB 30
37874 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
37875 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_WIDTH 1
37876 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
37877 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET_MSK 0x40000000
37878 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
37879 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_CLR_MSK 0xbfffffff
37880 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
37881 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_RESET 0x0
37882 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA field value from a register. */
37883 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
37884 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value suitable for setting the register. */
37885 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
37886 
37887 /*
37888  * Field : Address Enable - ae
37889  *
37890  * When this bit is enabled, the address filter block uses the 23th MAC address for
37891  * perfect filtering. When this bit is disabled, the address filter block ignores
37892  * the address for filtering.
37893  *
37894  * Field Enumeration Values:
37895  *
37896  * Enum | Value | Description
37897  * :----------------------------------------|:------|:--------------------------------------
37898  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
37899  * ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
37900  *
37901  * Field Access Macros:
37902  *
37903  */
37904 /*
37905  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
37906  *
37907  * Second MAC address filtering disabled
37908  */
37909 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD 0x0
37910 /*
37911  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
37912  *
37913  * Second MAC address filtering enabled
37914  */
37915 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END 0x1
37916 
37917 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
37918 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_LSB 31
37919 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
37920 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_MSB 31
37921 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
37922 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_WIDTH 1
37923 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
37924 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET_MSK 0x80000000
37925 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
37926 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_CLR_MSK 0x7fffffff
37927 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
37928 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_RESET 0x0
37929 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE field value from a register. */
37930 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
37931 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value suitable for setting the register. */
37932 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
37933 
37934 #ifndef __ASSEMBLY__
37935 /*
37936  * WARNING: The C register and register group struct declarations are provided for
37937  * convenience and illustrative purposes. They should, however, be used with
37938  * caution as the C language standard provides no guarantees about the alignment or
37939  * atomicity of device memory accesses. The recommended practice for writing
37940  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
37941  * alt_write_word() functions.
37942  *
37943  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH.
37944  */
37945 struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s
37946 {
37947  uint32_t addrhi : 16; /* MAC Address22 [47:32] */
37948  uint32_t : 8; /* *UNDEFINED* */
37949  uint32_t mbc_0 : 1; /* Mask Byte Control */
37950  uint32_t mbc_1 : 1; /* Mask Byte Control */
37951  uint32_t mbc_2 : 1; /* Mask Byte Control */
37952  uint32_t mbc_3 : 1; /* Mask Byte Control */
37953  uint32_t mbc_4 : 1; /* Mask Byte Control */
37954  uint32_t mbc_5 : 1; /* Mask Byte Control */
37955  uint32_t sa : 1; /* Source Address */
37956  uint32_t ae : 1; /* Address Enable */
37957 };
37958 
37959 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH. */
37960 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t;
37961 #endif /* __ASSEMBLY__ */
37962 
37963 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register from the beginning of the component. */
37964 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST 0x830
37965 /* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register. */
37966 #define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST))
37967 
37968 /*
37969  * Register : Register 525 (MAC Address22 Low Register) - MAC_Address22_Low
37970  *
37971  * The MAC Address22 Low register holds the lower 32 bits of the 23th 6-byte MAC
37972  * address of the station.
37973  *
37974  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
37975  * format.
37976  *
37977  * Register Layout
37978  *
37979  * Bits | Access | Reset | Description
37980  * :-------|:-------|:-----------|:---------------------
37981  * [31:0] | RW | 0xffffffff | MAC Address22 [31:0]
37982  *
37983  */
37984 /*
37985  * Field : MAC Address22 [31:0] - addrlo
37986  *
37987  * This field contains the lower 32 bits of the 23th 6-byte MAC address. The
37988  * content of this field is undefined until loaded by software after the
37989  * initialization process.
37990  *
37991  * Field Access Macros:
37992  *
37993  */
37994 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
37995 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_LSB 0
37996 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
37997 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_MSB 31
37998 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
37999 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_WIDTH 32
38000 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
38001 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET_MSK 0xffffffff
38002 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
38003 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_CLR_MSK 0x00000000
38004 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
38005 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_RESET 0xffffffff
38006 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO field value from a register. */
38007 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
38008 /* Produces a ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value suitable for setting the register. */
38009 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
38010 
38011 #ifndef __ASSEMBLY__
38012 /*
38013  * WARNING: The C register and register group struct declarations are provided for
38014  * convenience and illustrative purposes. They should, however, be used with
38015  * caution as the C language standard provides no guarantees about the alignment or
38016  * atomicity of device memory accesses. The recommended practice for writing
38017  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38018  * alt_write_word() functions.
38019  *
38020  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW.
38021  */
38022 struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s
38023 {
38024  uint32_t addrlo : 32; /* MAC Address22 [31:0] */
38025 };
38026 
38027 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW. */
38028 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s ALT_EMAC_GMAC_MAC_ADDR22_LOW_t;
38029 #endif /* __ASSEMBLY__ */
38030 
38031 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register from the beginning of the component. */
38032 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST 0x834
38033 /* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register. */
38034 #define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST))
38035 
38036 /*
38037  * Register : Register 526 (MAC Address23 High Register) - MAC_Address23_High
38038  *
38039  * The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC
38040  * address of the station. Because the MAC address registers are configured to be
38041  * double-synchronized to the (G)MII clock domains, the synchronization is
38042  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
38043  * endian mode) of the MAC Address23 Low Register are written. For proper
38044  * synchronization updates, the consecutive writes to this Address Low Register
38045  * should be performed after at least four clock cycles in the destination clock
38046  * domain.
38047  *
38048  * Note that all MAC Address High registers (except MAC Address0 High) have the
38049  * same format.
38050  *
38051  * Register Layout
38052  *
38053  * Bits | Access | Reset | Description
38054  * :--------|:-------|:-------|:----------------------
38055  * [15:0] | RW | 0xffff | MAC Address23 [47:32]
38056  * [23:16] | ??? | 0x0 | *UNDEFINED*
38057  * [24] | RW | 0x0 | Mask Byte Control
38058  * [25] | RW | 0x0 | Mask Byte Control
38059  * [26] | RW | 0x0 | Mask Byte Control
38060  * [27] | RW | 0x0 | Mask Byte Control
38061  * [28] | RW | 0x0 | Mask Byte Control
38062  * [29] | RW | 0x0 | Mask Byte Control
38063  * [30] | RW | 0x0 | Source Address
38064  * [31] | RW | 0x0 | Address Enable
38065  *
38066  */
38067 /*
38068  * Field : MAC Address23 [47:32] - addrhi
38069  *
38070  * This field contains the upper 16 bits (47:32) of the 24th 6-byte MAC address.
38071  *
38072  * Field Access Macros:
38073  *
38074  */
38075 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
38076 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_LSB 0
38077 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
38078 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_MSB 15
38079 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
38080 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_WIDTH 16
38081 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
38082 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET_MSK 0x0000ffff
38083 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
38084 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_CLR_MSK 0xffff0000
38085 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
38086 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_RESET 0xffff
38087 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI field value from a register. */
38088 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
38089 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value suitable for setting the register. */
38090 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
38091 
38092 /*
38093  * Field : Mask Byte Control - mbc_0
38094  *
38095  * This array of bits are mask control bits for comparison of each of the MAC
38096  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38097  * received DA or SA with the contents of MAC Address23 high and low registers.
38098  * Each bit controls the masking of the bytes. You can filter a group of addresses
38099  * (known as group address filtering) by masking one or more bytes of the address.
38100  *
38101  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38102  *
38103  * Field Enumeration Values:
38104  *
38105  * Enum | Value | Description
38106  * :----------------------------------------------|:------|:------------------------------------
38107  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38108  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38109  *
38110  * Field Access Macros:
38111  *
38112  */
38113 /*
38114  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
38115  *
38116  * Byte is unmasked (i.e. is compared)
38117  */
38118 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED 0x0
38119 /*
38120  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
38121  *
38122  * Byte is masked (i.e. not compared)
38123  */
38124 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED 0x1
38125 
38126 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
38127 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_LSB 24
38128 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
38129 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_MSB 24
38130 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
38131 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_WIDTH 1
38132 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
38133 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET_MSK 0x01000000
38134 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
38135 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_CLR_MSK 0xfeffffff
38136 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
38137 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_RESET 0x0
38138 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 field value from a register. */
38139 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
38140 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value suitable for setting the register. */
38141 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
38142 
38143 /*
38144  * Field : Mask Byte Control - mbc_1
38145  *
38146  * This array of bits are mask control bits for comparison of each of the MAC
38147  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38148  * received DA or SA with the contents of MAC Address23 high and low registers.
38149  * Each bit controls the masking of the bytes. You can filter a group of addresses
38150  * (known as group address filtering) by masking one or more bytes of the address.
38151  *
38152  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38153  *
38154  * Field Enumeration Values:
38155  *
38156  * Enum | Value | Description
38157  * :----------------------------------------------|:------|:------------------------------------
38158  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38159  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38160  *
38161  * Field Access Macros:
38162  *
38163  */
38164 /*
38165  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
38166  *
38167  * Byte is unmasked (i.e. is compared)
38168  */
38169 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED 0x0
38170 /*
38171  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
38172  *
38173  * Byte is masked (i.e. not compared)
38174  */
38175 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED 0x1
38176 
38177 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
38178 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_LSB 25
38179 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
38180 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_MSB 25
38181 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
38182 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_WIDTH 1
38183 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
38184 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET_MSK 0x02000000
38185 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
38186 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_CLR_MSK 0xfdffffff
38187 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
38188 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_RESET 0x0
38189 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 field value from a register. */
38190 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
38191 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value suitable for setting the register. */
38192 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
38193 
38194 /*
38195  * Field : Mask Byte Control - mbc_2
38196  *
38197  * This array of bits are mask control bits for comparison of each of the MAC
38198  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38199  * received DA or SA with the contents of MAC Address23 high and low registers.
38200  * Each bit controls the masking of the bytes. You can filter a group of addresses
38201  * (known as group address filtering) by masking one or more bytes of the address.
38202  *
38203  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38204  *
38205  * Field Enumeration Values:
38206  *
38207  * Enum | Value | Description
38208  * :----------------------------------------------|:------|:------------------------------------
38209  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38210  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38211  *
38212  * Field Access Macros:
38213  *
38214  */
38215 /*
38216  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
38217  *
38218  * Byte is unmasked (i.e. is compared)
38219  */
38220 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED 0x0
38221 /*
38222  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
38223  *
38224  * Byte is masked (i.e. not compared)
38225  */
38226 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED 0x1
38227 
38228 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
38229 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_LSB 26
38230 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
38231 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_MSB 26
38232 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
38233 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_WIDTH 1
38234 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
38235 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET_MSK 0x04000000
38236 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
38237 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_CLR_MSK 0xfbffffff
38238 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
38239 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_RESET 0x0
38240 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 field value from a register. */
38241 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
38242 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value suitable for setting the register. */
38243 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
38244 
38245 /*
38246  * Field : Mask Byte Control - mbc_3
38247  *
38248  * This array of bits are mask control bits for comparison of each of the MAC
38249  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38250  * received DA or SA with the contents of MAC Address23 high and low registers.
38251  * Each bit controls the masking of the bytes. You can filter a group of addresses
38252  * (known as group address filtering) by masking one or more bytes of the address.
38253  *
38254  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38255  *
38256  * Field Enumeration Values:
38257  *
38258  * Enum | Value | Description
38259  * :----------------------------------------------|:------|:------------------------------------
38260  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38261  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38262  *
38263  * Field Access Macros:
38264  *
38265  */
38266 /*
38267  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
38268  *
38269  * Byte is unmasked (i.e. is compared)
38270  */
38271 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED 0x0
38272 /*
38273  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
38274  *
38275  * Byte is masked (i.e. not compared)
38276  */
38277 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED 0x1
38278 
38279 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
38280 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_LSB 27
38281 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
38282 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_MSB 27
38283 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
38284 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_WIDTH 1
38285 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
38286 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET_MSK 0x08000000
38287 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
38288 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_CLR_MSK 0xf7ffffff
38289 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
38290 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_RESET 0x0
38291 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 field value from a register. */
38292 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
38293 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value suitable for setting the register. */
38294 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
38295 
38296 /*
38297  * Field : Mask Byte Control - mbc_4
38298  *
38299  * This array of bits are mask control bits for comparison of each of the MAC
38300  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38301  * received DA or SA with the contents of MAC Address23 high and low registers.
38302  * Each bit controls the masking of the bytes. You can filter a group of addresses
38303  * (known as group address filtering) by masking one or more bytes of the address.
38304  *
38305  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38306  *
38307  * Field Enumeration Values:
38308  *
38309  * Enum | Value | Description
38310  * :----------------------------------------------|:------|:------------------------------------
38311  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38312  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38313  *
38314  * Field Access Macros:
38315  *
38316  */
38317 /*
38318  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
38319  *
38320  * Byte is unmasked (i.e. is compared)
38321  */
38322 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED 0x0
38323 /*
38324  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
38325  *
38326  * Byte is masked (i.e. not compared)
38327  */
38328 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED 0x1
38329 
38330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
38331 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_LSB 28
38332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
38333 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_MSB 28
38334 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
38335 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_WIDTH 1
38336 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
38337 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET_MSK 0x10000000
38338 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
38339 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_CLR_MSK 0xefffffff
38340 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
38341 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_RESET 0x0
38342 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 field value from a register. */
38343 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
38344 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value suitable for setting the register. */
38345 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
38346 
38347 /*
38348  * Field : Mask Byte Control - mbc_5
38349  *
38350  * This array of bits are mask control bits for comparison of each of the MAC
38351  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38352  * received DA or SA with the contents of MAC Address23 high and low registers.
38353  * Each bit controls the masking of the bytes. You can filter a group of addresses
38354  * (known as group address filtering) by masking one or more bytes of the address.
38355  *
38356  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38357  *
38358  * Field Enumeration Values:
38359  *
38360  * Enum | Value | Description
38361  * :----------------------------------------------|:------|:------------------------------------
38362  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38363  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38364  *
38365  * Field Access Macros:
38366  *
38367  */
38368 /*
38369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
38370  *
38371  * Byte is unmasked (i.e. is compared)
38372  */
38373 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED 0x0
38374 /*
38375  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
38376  *
38377  * Byte is masked (i.e. not compared)
38378  */
38379 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED 0x1
38380 
38381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
38382 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_LSB 29
38383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
38384 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_MSB 29
38385 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
38386 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_WIDTH 1
38387 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
38388 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET_MSK 0x20000000
38389 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
38390 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_CLR_MSK 0xdfffffff
38391 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
38392 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_RESET 0x0
38393 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 field value from a register. */
38394 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
38395 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value suitable for setting the register. */
38396 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
38397 
38398 /*
38399  * Field : Source Address - sa
38400  *
38401  * When this bit is enabled, the MAC Address23[47:0] is used to compare with the SA
38402  * fields of the received frame. When this bit is disabled, the MAC Address23[47:0]
38403  * is used to compare with the DA fields of the received frame.
38404  *
38405  * Field Enumeration Values:
38406  *
38407  * Enum | Value | Description
38408  * :----------------------------------------|:------|:-----------------------------
38409  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
38410  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END | 0x1 | MAC address compare enabled
38411  *
38412  * Field Access Macros:
38413  *
38414  */
38415 /*
38416  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
38417  *
38418  * MAC address compare disabled
38419  */
38420 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD 0x0
38421 /*
38422  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
38423  *
38424  * MAC address compare enabled
38425  */
38426 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END 0x1
38427 
38428 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
38429 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_LSB 30
38430 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
38431 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_MSB 30
38432 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
38433 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_WIDTH 1
38434 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
38435 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET_MSK 0x40000000
38436 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
38437 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_CLR_MSK 0xbfffffff
38438 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
38439 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_RESET 0x0
38440 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA field value from a register. */
38441 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
38442 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value suitable for setting the register. */
38443 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
38444 
38445 /*
38446  * Field : Address Enable - ae
38447  *
38448  * When this bit is enabled, the address filter block uses the 24th MAC address for
38449  * perfect filtering. When this bit is disabled, the address filter block ignores
38450  * the address for filtering.
38451  *
38452  * Field Enumeration Values:
38453  *
38454  * Enum | Value | Description
38455  * :----------------------------------------|:------|:--------------------------------------
38456  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
38457  * ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
38458  *
38459  * Field Access Macros:
38460  *
38461  */
38462 /*
38463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
38464  *
38465  * Second MAC address filtering disabled
38466  */
38467 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD 0x0
38468 /*
38469  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
38470  *
38471  * Second MAC address filtering enabled
38472  */
38473 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END 0x1
38474 
38475 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
38476 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_LSB 31
38477 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
38478 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_MSB 31
38479 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
38480 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_WIDTH 1
38481 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
38482 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET_MSK 0x80000000
38483 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
38484 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_CLR_MSK 0x7fffffff
38485 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
38486 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_RESET 0x0
38487 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE field value from a register. */
38488 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
38489 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value suitable for setting the register. */
38490 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
38491 
38492 #ifndef __ASSEMBLY__
38493 /*
38494  * WARNING: The C register and register group struct declarations are provided for
38495  * convenience and illustrative purposes. They should, however, be used with
38496  * caution as the C language standard provides no guarantees about the alignment or
38497  * atomicity of device memory accesses. The recommended practice for writing
38498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38499  * alt_write_word() functions.
38500  *
38501  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH.
38502  */
38503 struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s
38504 {
38505  uint32_t addrhi : 16; /* MAC Address23 [47:32] */
38506  uint32_t : 8; /* *UNDEFINED* */
38507  uint32_t mbc_0 : 1; /* Mask Byte Control */
38508  uint32_t mbc_1 : 1; /* Mask Byte Control */
38509  uint32_t mbc_2 : 1; /* Mask Byte Control */
38510  uint32_t mbc_3 : 1; /* Mask Byte Control */
38511  uint32_t mbc_4 : 1; /* Mask Byte Control */
38512  uint32_t mbc_5 : 1; /* Mask Byte Control */
38513  uint32_t sa : 1; /* Source Address */
38514  uint32_t ae : 1; /* Address Enable */
38515 };
38516 
38517 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH. */
38518 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t;
38519 #endif /* __ASSEMBLY__ */
38520 
38521 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register from the beginning of the component. */
38522 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST 0x838
38523 /* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register. */
38524 #define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST))
38525 
38526 /*
38527  * Register : Register 527 (MAC Address23 Low Register) - MAC_Address23_Low
38528  *
38529  * The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC
38530  * address of the station.
38531  *
38532  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
38533  * format.
38534  *
38535  * Register Layout
38536  *
38537  * Bits | Access | Reset | Description
38538  * :-------|:-------|:-----------|:---------------------
38539  * [31:0] | RW | 0xffffffff | MAC Address23 [31:0]
38540  *
38541  */
38542 /*
38543  * Field : MAC Address23 [31:0] - addrlo
38544  *
38545  * This field contains the lower 32 bits of the 24th 6-byte MAC address. The
38546  * content of this field is undefined until loaded by software after the
38547  * initialization process.
38548  *
38549  * Field Access Macros:
38550  *
38551  */
38552 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
38553 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_LSB 0
38554 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
38555 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_MSB 31
38556 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
38557 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_WIDTH 32
38558 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
38559 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET_MSK 0xffffffff
38560 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
38561 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_CLR_MSK 0x00000000
38562 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
38563 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_RESET 0xffffffff
38564 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO field value from a register. */
38565 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
38566 /* Produces a ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value suitable for setting the register. */
38567 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
38568 
38569 #ifndef __ASSEMBLY__
38570 /*
38571  * WARNING: The C register and register group struct declarations are provided for
38572  * convenience and illustrative purposes. They should, however, be used with
38573  * caution as the C language standard provides no guarantees about the alignment or
38574  * atomicity of device memory accesses. The recommended practice for writing
38575  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
38576  * alt_write_word() functions.
38577  *
38578  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW.
38579  */
38580 struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s
38581 {
38582  uint32_t addrlo : 32; /* MAC Address23 [31:0] */
38583 };
38584 
38585 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW. */
38586 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s ALT_EMAC_GMAC_MAC_ADDR23_LOW_t;
38587 #endif /* __ASSEMBLY__ */
38588 
38589 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register from the beginning of the component. */
38590 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST 0x83c
38591 /* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register. */
38592 #define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST))
38593 
38594 /*
38595  * Register : Register 528 (MAC Address24 High Register) - MAC_Address24_High
38596  *
38597  * The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC
38598  * address of the station. Because the MAC address registers are configured to be
38599  * double-synchronized to the (G)MII clock domains, the synchronization is
38600  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
38601  * endian mode) of the MAC Address24 Low Register are written. For proper
38602  * synchronization updates, the consecutive writes to this Address Low Register
38603  * should be performed after at least four clock cycles in the destination clock
38604  * domain.
38605  *
38606  * Note that all MAC Address High registers (except MAC Address0 High) have the
38607  * same format.
38608  *
38609  * Register Layout
38610  *
38611  * Bits | Access | Reset | Description
38612  * :--------|:-------|:-------|:----------------------
38613  * [15:0] | RW | 0xffff | MAC Address24 [47:32]
38614  * [23:16] | ??? | 0x0 | *UNDEFINED*
38615  * [24] | RW | 0x0 | Mask Byte Control
38616  * [25] | RW | 0x0 | Mask Byte Control
38617  * [26] | RW | 0x0 | Mask Byte Control
38618  * [27] | RW | 0x0 | Mask Byte Control
38619  * [28] | RW | 0x0 | Mask Byte Control
38620  * [29] | RW | 0x0 | Mask Byte Control
38621  * [30] | RW | 0x0 | Source Address
38622  * [31] | RW | 0x0 | Address Enable
38623  *
38624  */
38625 /*
38626  * Field : MAC Address24 [47:32] - addrhi
38627  *
38628  * This field contains the upper 16 bits (47:32) of the 25th 6-byte MAC address.
38629  *
38630  * Field Access Macros:
38631  *
38632  */
38633 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
38634 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_LSB 0
38635 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
38636 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_MSB 15
38637 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
38638 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_WIDTH 16
38639 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
38640 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET_MSK 0x0000ffff
38641 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
38642 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_CLR_MSK 0xffff0000
38643 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
38644 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_RESET 0xffff
38645 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI field value from a register. */
38646 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
38647 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value suitable for setting the register. */
38648 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
38649 
38650 /*
38651  * Field : Mask Byte Control - mbc_0
38652  *
38653  * This array of bits are mask control bits for comparison of each of the MAC
38654  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38655  * received DA or SA with the contents of MAC Address24 high and low registers.
38656  * Each bit controls the masking of the bytes. You can filter a group of addresses
38657  * (known as group address filtering) by masking one or more bytes of the address.
38658  *
38659  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38660  *
38661  * Field Enumeration Values:
38662  *
38663  * Enum | Value | Description
38664  * :----------------------------------------------|:------|:------------------------------------
38665  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38666  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38667  *
38668  * Field Access Macros:
38669  *
38670  */
38671 /*
38672  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
38673  *
38674  * Byte is unmasked (i.e. is compared)
38675  */
38676 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED 0x0
38677 /*
38678  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
38679  *
38680  * Byte is masked (i.e. not compared)
38681  */
38682 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED 0x1
38683 
38684 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
38685 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_LSB 24
38686 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
38687 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_MSB 24
38688 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
38689 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_WIDTH 1
38690 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
38691 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET_MSK 0x01000000
38692 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
38693 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_CLR_MSK 0xfeffffff
38694 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
38695 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_RESET 0x0
38696 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 field value from a register. */
38697 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
38698 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value suitable for setting the register. */
38699 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
38700 
38701 /*
38702  * Field : Mask Byte Control - mbc_1
38703  *
38704  * This array of bits are mask control bits for comparison of each of the MAC
38705  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38706  * received DA or SA with the contents of MAC Address24 high and low registers.
38707  * Each bit controls the masking of the bytes. You can filter a group of addresses
38708  * (known as group address filtering) by masking one or more bytes of the address.
38709  *
38710  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38711  *
38712  * Field Enumeration Values:
38713  *
38714  * Enum | Value | Description
38715  * :----------------------------------------------|:------|:------------------------------------
38716  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38717  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38718  *
38719  * Field Access Macros:
38720  *
38721  */
38722 /*
38723  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
38724  *
38725  * Byte is unmasked (i.e. is compared)
38726  */
38727 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED 0x0
38728 /*
38729  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
38730  *
38731  * Byte is masked (i.e. not compared)
38732  */
38733 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED 0x1
38734 
38735 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
38736 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_LSB 25
38737 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
38738 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_MSB 25
38739 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
38740 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_WIDTH 1
38741 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
38742 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET_MSK 0x02000000
38743 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
38744 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_CLR_MSK 0xfdffffff
38745 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
38746 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_RESET 0x0
38747 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 field value from a register. */
38748 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
38749 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value suitable for setting the register. */
38750 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
38751 
38752 /*
38753  * Field : Mask Byte Control - mbc_2
38754  *
38755  * This array of bits are mask control bits for comparison of each of the MAC
38756  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38757  * received DA or SA with the contents of MAC Address24 high and low registers.
38758  * Each bit controls the masking of the bytes. You can filter a group of addresses
38759  * (known as group address filtering) by masking one or more bytes of the address.
38760  *
38761  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38762  *
38763  * Field Enumeration Values:
38764  *
38765  * Enum | Value | Description
38766  * :----------------------------------------------|:------|:------------------------------------
38767  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38768  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38769  *
38770  * Field Access Macros:
38771  *
38772  */
38773 /*
38774  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
38775  *
38776  * Byte is unmasked (i.e. is compared)
38777  */
38778 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED 0x0
38779 /*
38780  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
38781  *
38782  * Byte is masked (i.e. not compared)
38783  */
38784 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED 0x1
38785 
38786 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
38787 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_LSB 26
38788 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
38789 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_MSB 26
38790 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
38791 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_WIDTH 1
38792 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
38793 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET_MSK 0x04000000
38794 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
38795 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_CLR_MSK 0xfbffffff
38796 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
38797 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_RESET 0x0
38798 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 field value from a register. */
38799 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
38800 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value suitable for setting the register. */
38801 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
38802 
38803 /*
38804  * Field : Mask Byte Control - mbc_3
38805  *
38806  * This array of bits are mask control bits for comparison of each of the MAC
38807  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38808  * received DA or SA with the contents of MAC Address24 high and low registers.
38809  * Each bit controls the masking of the bytes. You can filter a group of addresses
38810  * (known as group address filtering) by masking one or more bytes of the address.
38811  *
38812  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38813  *
38814  * Field Enumeration Values:
38815  *
38816  * Enum | Value | Description
38817  * :----------------------------------------------|:------|:------------------------------------
38818  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38819  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38820  *
38821  * Field Access Macros:
38822  *
38823  */
38824 /*
38825  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
38826  *
38827  * Byte is unmasked (i.e. is compared)
38828  */
38829 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED 0x0
38830 /*
38831  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
38832  *
38833  * Byte is masked (i.e. not compared)
38834  */
38835 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED 0x1
38836 
38837 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
38838 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_LSB 27
38839 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
38840 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_MSB 27
38841 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
38842 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_WIDTH 1
38843 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
38844 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET_MSK 0x08000000
38845 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
38846 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_CLR_MSK 0xf7ffffff
38847 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
38848 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_RESET 0x0
38849 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 field value from a register. */
38850 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
38851 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value suitable for setting the register. */
38852 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
38853 
38854 /*
38855  * Field : Mask Byte Control - mbc_4
38856  *
38857  * This array of bits are mask control bits for comparison of each of the MAC
38858  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38859  * received DA or SA with the contents of MAC Address24 high and low registers.
38860  * Each bit controls the masking of the bytes. You can filter a group of addresses
38861  * (known as group address filtering) by masking one or more bytes of the address.
38862  *
38863  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38864  *
38865  * Field Enumeration Values:
38866  *
38867  * Enum | Value | Description
38868  * :----------------------------------------------|:------|:------------------------------------
38869  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38870  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38871  *
38872  * Field Access Macros:
38873  *
38874  */
38875 /*
38876  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
38877  *
38878  * Byte is unmasked (i.e. is compared)
38879  */
38880 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED 0x0
38881 /*
38882  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
38883  *
38884  * Byte is masked (i.e. not compared)
38885  */
38886 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED 0x1
38887 
38888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
38889 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_LSB 28
38890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
38891 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_MSB 28
38892 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
38893 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_WIDTH 1
38894 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
38895 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET_MSK 0x10000000
38896 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
38897 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_CLR_MSK 0xefffffff
38898 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
38899 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_RESET 0x0
38900 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 field value from a register. */
38901 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
38902 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value suitable for setting the register. */
38903 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
38904 
38905 /*
38906  * Field : Mask Byte Control - mbc_5
38907  *
38908  * This array of bits are mask control bits for comparison of each of the MAC
38909  * Address bytes. When masked, the MAC does not compare the corresponding byte of
38910  * received DA or SA with the contents of MAC Address24 high and low registers.
38911  * Each bit controls the masking of the bytes. You can filter a group of addresses
38912  * (known as group address filtering) by masking one or more bytes of the address.
38913  *
38914  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
38915  *
38916  * Field Enumeration Values:
38917  *
38918  * Enum | Value | Description
38919  * :----------------------------------------------|:------|:------------------------------------
38920  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
38921  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
38922  *
38923  * Field Access Macros:
38924  *
38925  */
38926 /*
38927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
38928  *
38929  * Byte is unmasked (i.e. is compared)
38930  */
38931 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED 0x0
38932 /*
38933  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
38934  *
38935  * Byte is masked (i.e. not compared)
38936  */
38937 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED 0x1
38938 
38939 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
38940 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_LSB 29
38941 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
38942 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_MSB 29
38943 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
38944 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_WIDTH 1
38945 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
38946 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET_MSK 0x20000000
38947 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
38948 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_CLR_MSK 0xdfffffff
38949 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
38950 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_RESET 0x0
38951 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 field value from a register. */
38952 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
38953 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value suitable for setting the register. */
38954 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
38955 
38956 /*
38957  * Field : Source Address - sa
38958  *
38959  * When this bit is enabled, the MAC Address24[47:0] is used to compare with the SA
38960  * fields of the received frame. When this bit is disabled, the MAC Address24[47:0]
38961  * is used to compare with the DA fields of the received frame.
38962  *
38963  * Field Enumeration Values:
38964  *
38965  * Enum | Value | Description
38966  * :----------------------------------------|:------|:-----------------------------
38967  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
38968  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END | 0x1 | MAC address compare enabled
38969  *
38970  * Field Access Macros:
38971  *
38972  */
38973 /*
38974  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
38975  *
38976  * MAC address compare disabled
38977  */
38978 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD 0x0
38979 /*
38980  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
38981  *
38982  * MAC address compare enabled
38983  */
38984 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END 0x1
38985 
38986 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
38987 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_LSB 30
38988 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
38989 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_MSB 30
38990 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
38991 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_WIDTH 1
38992 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
38993 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET_MSK 0x40000000
38994 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
38995 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_CLR_MSK 0xbfffffff
38996 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
38997 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_RESET 0x0
38998 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA field value from a register. */
38999 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
39000 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value suitable for setting the register. */
39001 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
39002 
39003 /*
39004  * Field : Address Enable - ae
39005  *
39006  * When this bit is enabled, the address filter block uses the 25th MAC address for
39007  * perfect filtering. When this bit is disabled, the address filter block ignores
39008  * the address for filtering.
39009  *
39010  * Field Enumeration Values:
39011  *
39012  * Enum | Value | Description
39013  * :----------------------------------------|:------|:--------------------------------------
39014  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
39015  * ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
39016  *
39017  * Field Access Macros:
39018  *
39019  */
39020 /*
39021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
39022  *
39023  * Second MAC address filtering disabled
39024  */
39025 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD 0x0
39026 /*
39027  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
39028  *
39029  * Second MAC address filtering enabled
39030  */
39031 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END 0x1
39032 
39033 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
39034 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_LSB 31
39035 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
39036 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_MSB 31
39037 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
39038 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_WIDTH 1
39039 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
39040 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET_MSK 0x80000000
39041 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
39042 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_CLR_MSK 0x7fffffff
39043 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
39044 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_RESET 0x0
39045 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE field value from a register. */
39046 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
39047 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value suitable for setting the register. */
39048 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
39049 
39050 #ifndef __ASSEMBLY__
39051 /*
39052  * WARNING: The C register and register group struct declarations are provided for
39053  * convenience and illustrative purposes. They should, however, be used with
39054  * caution as the C language standard provides no guarantees about the alignment or
39055  * atomicity of device memory accesses. The recommended practice for writing
39056  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39057  * alt_write_word() functions.
39058  *
39059  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH.
39060  */
39061 struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s
39062 {
39063  uint32_t addrhi : 16; /* MAC Address24 [47:32] */
39064  uint32_t : 8; /* *UNDEFINED* */
39065  uint32_t mbc_0 : 1; /* Mask Byte Control */
39066  uint32_t mbc_1 : 1; /* Mask Byte Control */
39067  uint32_t mbc_2 : 1; /* Mask Byte Control */
39068  uint32_t mbc_3 : 1; /* Mask Byte Control */
39069  uint32_t mbc_4 : 1; /* Mask Byte Control */
39070  uint32_t mbc_5 : 1; /* Mask Byte Control */
39071  uint32_t sa : 1; /* Source Address */
39072  uint32_t ae : 1; /* Address Enable */
39073 };
39074 
39075 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH. */
39076 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t;
39077 #endif /* __ASSEMBLY__ */
39078 
39079 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register from the beginning of the component. */
39080 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST 0x840
39081 /* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register. */
39082 #define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST))
39083 
39084 /*
39085  * Register : Register 529 (MAC Address24 Low Register) - MAC_Address24_Low
39086  *
39087  * The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC
39088  * address of the station.
39089  *
39090  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
39091  * format.
39092  *
39093  * Register Layout
39094  *
39095  * Bits | Access | Reset | Description
39096  * :-------|:-------|:-----------|:---------------------
39097  * [31:0] | RW | 0xffffffff | MAC Address24 [31:0]
39098  *
39099  */
39100 /*
39101  * Field : MAC Address24 [31:0] - addrlo
39102  *
39103  * This field contains the lower 32 bits of the 25th 6-byte MAC address. The
39104  * content of this field is undefined until loaded by software after the
39105  * initialization process.
39106  *
39107  * Field Access Macros:
39108  *
39109  */
39110 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
39111 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_LSB 0
39112 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
39113 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_MSB 31
39114 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
39115 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_WIDTH 32
39116 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
39117 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET_MSK 0xffffffff
39118 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
39119 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_CLR_MSK 0x00000000
39120 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
39121 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_RESET 0xffffffff
39122 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO field value from a register. */
39123 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
39124 /* Produces a ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value suitable for setting the register. */
39125 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
39126 
39127 #ifndef __ASSEMBLY__
39128 /*
39129  * WARNING: The C register and register group struct declarations are provided for
39130  * convenience and illustrative purposes. They should, however, be used with
39131  * caution as the C language standard provides no guarantees about the alignment or
39132  * atomicity of device memory accesses. The recommended practice for writing
39133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39134  * alt_write_word() functions.
39135  *
39136  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW.
39137  */
39138 struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s
39139 {
39140  uint32_t addrlo : 32; /* MAC Address24 [31:0] */
39141 };
39142 
39143 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW. */
39144 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s ALT_EMAC_GMAC_MAC_ADDR24_LOW_t;
39145 #endif /* __ASSEMBLY__ */
39146 
39147 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register from the beginning of the component. */
39148 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST 0x844
39149 /* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register. */
39150 #define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST))
39151 
39152 /*
39153  * Register : Register 530 (MAC Address25 High Register) - MAC_Address25_High
39154  *
39155  * The MAC Address25 High register holds the upper 16 bits of the 26th 6-byte MAC
39156  * address of the station. Because the MAC address registers are configured to be
39157  * double-synchronized to the (G)MII clock domains, the synchronization is
39158  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
39159  * endian mode) of the MAC Address25 Low Register are written. For proper
39160  * synchronization updates, the consecutive writes to this Address Low Register
39161  * should be performed after at least four clock cycles in the destination clock
39162  * domain.
39163  *
39164  * Note that all MAC Address High registers (except MAC Address0 High) have the
39165  * same format.
39166  *
39167  * Register Layout
39168  *
39169  * Bits | Access | Reset | Description
39170  * :--------|:-------|:-------|:----------------------
39171  * [15:0] | RW | 0xffff | MAC Address25 [47:32]
39172  * [23:16] | ??? | 0x0 | *UNDEFINED*
39173  * [24] | RW | 0x0 | Mask Byte Control
39174  * [25] | RW | 0x0 | Mask Byte Control
39175  * [26] | RW | 0x0 | Mask Byte Control
39176  * [27] | RW | 0x0 | Mask Byte Control
39177  * [28] | RW | 0x0 | Mask Byte Control
39178  * [29] | RW | 0x0 | Mask Byte Control
39179  * [30] | RW | 0x0 | Source Address
39180  * [31] | RW | 0x0 | Address Enable
39181  *
39182  */
39183 /*
39184  * Field : MAC Address25 [47:32] - addrhi
39185  *
39186  * This field contains the upper 16 bits (47:32) of the 26th 6-byte MAC address.
39187  *
39188  * Field Access Macros:
39189  *
39190  */
39191 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
39192 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_LSB 0
39193 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
39194 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_MSB 15
39195 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
39196 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_WIDTH 16
39197 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
39198 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET_MSK 0x0000ffff
39199 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
39200 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_CLR_MSK 0xffff0000
39201 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
39202 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_RESET 0xffff
39203 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI field value from a register. */
39204 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
39205 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value suitable for setting the register. */
39206 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
39207 
39208 /*
39209  * Field : Mask Byte Control - mbc_0
39210  *
39211  * This array of bits are mask control bits for comparison of each of the MAC
39212  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39213  * received DA or SA with the contents of MAC Address25 high and low registers.
39214  * Each bit controls the masking of the bytes. You can filter a group of addresses
39215  * (known as group address filtering) by masking one or more bytes of the address.
39216  *
39217  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39218  *
39219  * Field Enumeration Values:
39220  *
39221  * Enum | Value | Description
39222  * :----------------------------------------------|:------|:------------------------------------
39223  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39224  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39225  *
39226  * Field Access Macros:
39227  *
39228  */
39229 /*
39230  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
39231  *
39232  * Byte is unmasked (i.e. is compared)
39233  */
39234 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED 0x0
39235 /*
39236  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
39237  *
39238  * Byte is masked (i.e. not compared)
39239  */
39240 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED 0x1
39241 
39242 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
39243 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_LSB 24
39244 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
39245 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_MSB 24
39246 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
39247 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_WIDTH 1
39248 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
39249 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET_MSK 0x01000000
39250 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
39251 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_CLR_MSK 0xfeffffff
39252 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
39253 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_RESET 0x0
39254 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 field value from a register. */
39255 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
39256 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value suitable for setting the register. */
39257 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
39258 
39259 /*
39260  * Field : Mask Byte Control - mbc_1
39261  *
39262  * This array of bits are mask control bits for comparison of each of the MAC
39263  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39264  * received DA or SA with the contents of MAC Address25 high and low registers.
39265  * Each bit controls the masking of the bytes. You can filter a group of addresses
39266  * (known as group address filtering) by masking one or more bytes of the address.
39267  *
39268  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39269  *
39270  * Field Enumeration Values:
39271  *
39272  * Enum | Value | Description
39273  * :----------------------------------------------|:------|:------------------------------------
39274  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39275  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39276  *
39277  * Field Access Macros:
39278  *
39279  */
39280 /*
39281  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
39282  *
39283  * Byte is unmasked (i.e. is compared)
39284  */
39285 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED 0x0
39286 /*
39287  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
39288  *
39289  * Byte is masked (i.e. not compared)
39290  */
39291 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED 0x1
39292 
39293 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
39294 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_LSB 25
39295 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
39296 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_MSB 25
39297 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
39298 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_WIDTH 1
39299 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
39300 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET_MSK 0x02000000
39301 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
39302 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_CLR_MSK 0xfdffffff
39303 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
39304 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_RESET 0x0
39305 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 field value from a register. */
39306 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
39307 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value suitable for setting the register. */
39308 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
39309 
39310 /*
39311  * Field : Mask Byte Control - mbc_2
39312  *
39313  * This array of bits are mask control bits for comparison of each of the MAC
39314  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39315  * received DA or SA with the contents of MAC Address25 high and low registers.
39316  * Each bit controls the masking of the bytes. You can filter a group of addresses
39317  * (known as group address filtering) by masking one or more bytes of the address.
39318  *
39319  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39320  *
39321  * Field Enumeration Values:
39322  *
39323  * Enum | Value | Description
39324  * :----------------------------------------------|:------|:------------------------------------
39325  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39326  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39327  *
39328  * Field Access Macros:
39329  *
39330  */
39331 /*
39332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
39333  *
39334  * Byte is unmasked (i.e. is compared)
39335  */
39336 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED 0x0
39337 /*
39338  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
39339  *
39340  * Byte is masked (i.e. not compared)
39341  */
39342 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED 0x1
39343 
39344 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
39345 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_LSB 26
39346 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
39347 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_MSB 26
39348 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
39349 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_WIDTH 1
39350 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
39351 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET_MSK 0x04000000
39352 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
39353 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_CLR_MSK 0xfbffffff
39354 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
39355 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_RESET 0x0
39356 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 field value from a register. */
39357 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
39358 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value suitable for setting the register. */
39359 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
39360 
39361 /*
39362  * Field : Mask Byte Control - mbc_3
39363  *
39364  * This array of bits are mask control bits for comparison of each of the MAC
39365  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39366  * received DA or SA with the contents of MAC Address25 high and low registers.
39367  * Each bit controls the masking of the bytes. You can filter a group of addresses
39368  * (known as group address filtering) by masking one or more bytes of the address.
39369  *
39370  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39371  *
39372  * Field Enumeration Values:
39373  *
39374  * Enum | Value | Description
39375  * :----------------------------------------------|:------|:------------------------------------
39376  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39377  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39378  *
39379  * Field Access Macros:
39380  *
39381  */
39382 /*
39383  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
39384  *
39385  * Byte is unmasked (i.e. is compared)
39386  */
39387 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED 0x0
39388 /*
39389  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
39390  *
39391  * Byte is masked (i.e. not compared)
39392  */
39393 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED 0x1
39394 
39395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
39396 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_LSB 27
39397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
39398 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_MSB 27
39399 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
39400 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_WIDTH 1
39401 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
39402 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET_MSK 0x08000000
39403 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
39404 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_CLR_MSK 0xf7ffffff
39405 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
39406 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_RESET 0x0
39407 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 field value from a register. */
39408 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
39409 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value suitable for setting the register. */
39410 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
39411 
39412 /*
39413  * Field : Mask Byte Control - mbc_4
39414  *
39415  * This array of bits are mask control bits for comparison of each of the MAC
39416  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39417  * received DA or SA with the contents of MAC Address25 high and low registers.
39418  * Each bit controls the masking of the bytes. You can filter a group of addresses
39419  * (known as group address filtering) by masking one or more bytes of the address.
39420  *
39421  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39422  *
39423  * Field Enumeration Values:
39424  *
39425  * Enum | Value | Description
39426  * :----------------------------------------------|:------|:------------------------------------
39427  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39428  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39429  *
39430  * Field Access Macros:
39431  *
39432  */
39433 /*
39434  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
39435  *
39436  * Byte is unmasked (i.e. is compared)
39437  */
39438 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED 0x0
39439 /*
39440  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
39441  *
39442  * Byte is masked (i.e. not compared)
39443  */
39444 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED 0x1
39445 
39446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
39447 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_LSB 28
39448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
39449 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_MSB 28
39450 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
39451 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_WIDTH 1
39452 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
39453 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET_MSK 0x10000000
39454 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
39455 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_CLR_MSK 0xefffffff
39456 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
39457 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_RESET 0x0
39458 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 field value from a register. */
39459 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
39460 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value suitable for setting the register. */
39461 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
39462 
39463 /*
39464  * Field : Mask Byte Control - mbc_5
39465  *
39466  * This array of bits are mask control bits for comparison of each of the MAC
39467  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39468  * received DA or SA with the contents of MAC Address25 high and low registers.
39469  * Each bit controls the masking of the bytes. You can filter a group of addresses
39470  * (known as group address filtering) by masking one or more bytes of the address.
39471  *
39472  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39473  *
39474  * Field Enumeration Values:
39475  *
39476  * Enum | Value | Description
39477  * :----------------------------------------------|:------|:------------------------------------
39478  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39479  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39480  *
39481  * Field Access Macros:
39482  *
39483  */
39484 /*
39485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
39486  *
39487  * Byte is unmasked (i.e. is compared)
39488  */
39489 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED 0x0
39490 /*
39491  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
39492  *
39493  * Byte is masked (i.e. not compared)
39494  */
39495 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED 0x1
39496 
39497 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
39498 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_LSB 29
39499 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
39500 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_MSB 29
39501 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
39502 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_WIDTH 1
39503 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
39504 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET_MSK 0x20000000
39505 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
39506 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_CLR_MSK 0xdfffffff
39507 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
39508 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_RESET 0x0
39509 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 field value from a register. */
39510 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
39511 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value suitable for setting the register. */
39512 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
39513 
39514 /*
39515  * Field : Source Address - sa
39516  *
39517  * When this bit is enabled, the MAC Address25[47:0] is used to compare with the SA
39518  * fields of the received frame. When this bit is disabled, the MAC Address25[47:0]
39519  * is used to compare with the DA fields of the received frame.
39520  *
39521  * Field Enumeration Values:
39522  *
39523  * Enum | Value | Description
39524  * :----------------------------------------|:------|:-----------------------------
39525  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
39526  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END | 0x1 | MAC address compare enabled
39527  *
39528  * Field Access Macros:
39529  *
39530  */
39531 /*
39532  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
39533  *
39534  * MAC address compare disabled
39535  */
39536 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD 0x0
39537 /*
39538  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
39539  *
39540  * MAC address compare enabled
39541  */
39542 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END 0x1
39543 
39544 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
39545 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_LSB 30
39546 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
39547 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_MSB 30
39548 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
39549 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_WIDTH 1
39550 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
39551 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET_MSK 0x40000000
39552 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
39553 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_CLR_MSK 0xbfffffff
39554 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
39555 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_RESET 0x0
39556 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA field value from a register. */
39557 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
39558 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value suitable for setting the register. */
39559 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
39560 
39561 /*
39562  * Field : Address Enable - ae
39563  *
39564  * When this bit is enabled, the address filter block uses the 26th MAC address for
39565  * perfect filtering. When this bit is disabled, the address filter block ignores
39566  * the address for filtering.
39567  *
39568  * Field Enumeration Values:
39569  *
39570  * Enum | Value | Description
39571  * :----------------------------------------|:------|:--------------------------------------
39572  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
39573  * ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
39574  *
39575  * Field Access Macros:
39576  *
39577  */
39578 /*
39579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
39580  *
39581  * Second MAC address filtering disabled
39582  */
39583 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD 0x0
39584 /*
39585  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
39586  *
39587  * Second MAC address filtering enabled
39588  */
39589 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END 0x1
39590 
39591 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
39592 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_LSB 31
39593 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
39594 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_MSB 31
39595 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
39596 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_WIDTH 1
39597 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
39598 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET_MSK 0x80000000
39599 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
39600 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_CLR_MSK 0x7fffffff
39601 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
39602 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_RESET 0x0
39603 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE field value from a register. */
39604 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
39605 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value suitable for setting the register. */
39606 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
39607 
39608 #ifndef __ASSEMBLY__
39609 /*
39610  * WARNING: The C register and register group struct declarations are provided for
39611  * convenience and illustrative purposes. They should, however, be used with
39612  * caution as the C language standard provides no guarantees about the alignment or
39613  * atomicity of device memory accesses. The recommended practice for writing
39614  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39615  * alt_write_word() functions.
39616  *
39617  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH.
39618  */
39619 struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s
39620 {
39621  uint32_t addrhi : 16; /* MAC Address25 [47:32] */
39622  uint32_t : 8; /* *UNDEFINED* */
39623  uint32_t mbc_0 : 1; /* Mask Byte Control */
39624  uint32_t mbc_1 : 1; /* Mask Byte Control */
39625  uint32_t mbc_2 : 1; /* Mask Byte Control */
39626  uint32_t mbc_3 : 1; /* Mask Byte Control */
39627  uint32_t mbc_4 : 1; /* Mask Byte Control */
39628  uint32_t mbc_5 : 1; /* Mask Byte Control */
39629  uint32_t sa : 1; /* Source Address */
39630  uint32_t ae : 1; /* Address Enable */
39631 };
39632 
39633 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH. */
39634 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t;
39635 #endif /* __ASSEMBLY__ */
39636 
39637 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register from the beginning of the component. */
39638 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST 0x848
39639 /* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register. */
39640 #define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST))
39641 
39642 /*
39643  * Register : Register 531 (MAC Address25 Low Register) - MAC_Address25_Low
39644  *
39645  * The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC
39646  * address of the station.
39647  *
39648  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
39649  * format.
39650  *
39651  * Register Layout
39652  *
39653  * Bits | Access | Reset | Description
39654  * :-------|:-------|:-----------|:---------------------
39655  * [31:0] | RW | 0xffffffff | MAC Address25 [31:0]
39656  *
39657  */
39658 /*
39659  * Field : MAC Address25 [31:0] - addrlo
39660  *
39661  * This field contains the lower 32 bits of the 26th 6-byte MAC address. The
39662  * content of this field is undefined until loaded by software after the
39663  * initialization process.
39664  *
39665  * Field Access Macros:
39666  *
39667  */
39668 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
39669 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_LSB 0
39670 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
39671 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_MSB 31
39672 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
39673 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_WIDTH 32
39674 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
39675 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET_MSK 0xffffffff
39676 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
39677 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_CLR_MSK 0x00000000
39678 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
39679 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_RESET 0xffffffff
39680 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO field value from a register. */
39681 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
39682 /* Produces a ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value suitable for setting the register. */
39683 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
39684 
39685 #ifndef __ASSEMBLY__
39686 /*
39687  * WARNING: The C register and register group struct declarations are provided for
39688  * convenience and illustrative purposes. They should, however, be used with
39689  * caution as the C language standard provides no guarantees about the alignment or
39690  * atomicity of device memory accesses. The recommended practice for writing
39691  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
39692  * alt_write_word() functions.
39693  *
39694  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW.
39695  */
39696 struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s
39697 {
39698  uint32_t addrlo : 32; /* MAC Address25 [31:0] */
39699 };
39700 
39701 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW. */
39702 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s ALT_EMAC_GMAC_MAC_ADDR25_LOW_t;
39703 #endif /* __ASSEMBLY__ */
39704 
39705 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register from the beginning of the component. */
39706 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST 0x84c
39707 /* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register. */
39708 #define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST))
39709 
39710 /*
39711  * Register : Register 532 (MAC Address26 High Register) - MAC_Address26_High
39712  *
39713  * The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC
39714  * address of the station. Because the MAC address registers are configured to be
39715  * double-synchronized to the (G)MII clock domains, the synchronization is
39716  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
39717  * endian mode) of the MAC Address26 Low Register are written. For proper
39718  * synchronization updates, the consecutive writes to this Address Low Register
39719  * should be performed after at least four clock cycles in the destination clock
39720  * domain.
39721  *
39722  * Note that all MAC Address High registers (except MAC Address0 High) have the
39723  * same format.
39724  *
39725  * Register Layout
39726  *
39727  * Bits | Access | Reset | Description
39728  * :--------|:-------|:-------|:----------------------
39729  * [15:0] | RW | 0xffff | MAC Address26 [47:32]
39730  * [23:16] | ??? | 0x0 | *UNDEFINED*
39731  * [24] | RW | 0x0 | Mask Byte Control
39732  * [25] | RW | 0x0 | Mask Byte Control
39733  * [26] | RW | 0x0 | Mask Byte Control
39734  * [27] | RW | 0x0 | Mask Byte Control
39735  * [28] | RW | 0x0 | Mask Byte Control
39736  * [29] | RW | 0x0 | Mask Byte Control
39737  * [30] | RW | 0x0 | Source Address
39738  * [31] | RW | 0x0 | Address Enable
39739  *
39740  */
39741 /*
39742  * Field : MAC Address26 [47:32] - addrhi
39743  *
39744  * This field contains the upper 16 bits (47:32) of the 27th 6-byte MAC address.
39745  *
39746  * Field Access Macros:
39747  *
39748  */
39749 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
39750 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_LSB 0
39751 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
39752 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_MSB 15
39753 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
39754 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_WIDTH 16
39755 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
39756 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET_MSK 0x0000ffff
39757 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
39758 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_CLR_MSK 0xffff0000
39759 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
39760 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_RESET 0xffff
39761 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI field value from a register. */
39762 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
39763 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value suitable for setting the register. */
39764 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
39765 
39766 /*
39767  * Field : Mask Byte Control - mbc_0
39768  *
39769  * This array of bits are mask control bits for comparison of each of the MAC
39770  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39771  * received DA or SA with the contents of MAC Address26 high and low registers.
39772  * Each bit controls the masking of the bytes. You can filter a group of addresses
39773  * (known as group address filtering) by masking one or more bytes of the address.
39774  *
39775  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39776  *
39777  * Field Enumeration Values:
39778  *
39779  * Enum | Value | Description
39780  * :----------------------------------------------|:------|:------------------------------------
39781  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39782  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39783  *
39784  * Field Access Macros:
39785  *
39786  */
39787 /*
39788  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
39789  *
39790  * Byte is unmasked (i.e. is compared)
39791  */
39792 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED 0x0
39793 /*
39794  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
39795  *
39796  * Byte is masked (i.e. not compared)
39797  */
39798 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED 0x1
39799 
39800 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
39801 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_LSB 24
39802 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
39803 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_MSB 24
39804 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
39805 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_WIDTH 1
39806 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
39807 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET_MSK 0x01000000
39808 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
39809 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_CLR_MSK 0xfeffffff
39810 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
39811 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_RESET 0x0
39812 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 field value from a register. */
39813 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
39814 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value suitable for setting the register. */
39815 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
39816 
39817 /*
39818  * Field : Mask Byte Control - mbc_1
39819  *
39820  * This array of bits are mask control bits for comparison of each of the MAC
39821  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39822  * received DA or SA with the contents of MAC Address26 high and low registers.
39823  * Each bit controls the masking of the bytes. You can filter a group of addresses
39824  * (known as group address filtering) by masking one or more bytes of the address.
39825  *
39826  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39827  *
39828  * Field Enumeration Values:
39829  *
39830  * Enum | Value | Description
39831  * :----------------------------------------------|:------|:------------------------------------
39832  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39833  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39834  *
39835  * Field Access Macros:
39836  *
39837  */
39838 /*
39839  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
39840  *
39841  * Byte is unmasked (i.e. is compared)
39842  */
39843 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED 0x0
39844 /*
39845  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
39846  *
39847  * Byte is masked (i.e. not compared)
39848  */
39849 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED 0x1
39850 
39851 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
39852 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_LSB 25
39853 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
39854 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_MSB 25
39855 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
39856 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_WIDTH 1
39857 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
39858 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET_MSK 0x02000000
39859 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
39860 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_CLR_MSK 0xfdffffff
39861 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
39862 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_RESET 0x0
39863 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 field value from a register. */
39864 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
39865 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value suitable for setting the register. */
39866 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
39867 
39868 /*
39869  * Field : Mask Byte Control - mbc_2
39870  *
39871  * This array of bits are mask control bits for comparison of each of the MAC
39872  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39873  * received DA or SA with the contents of MAC Address26 high and low registers.
39874  * Each bit controls the masking of the bytes. You can filter a group of addresses
39875  * (known as group address filtering) by masking one or more bytes of the address.
39876  *
39877  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39878  *
39879  * Field Enumeration Values:
39880  *
39881  * Enum | Value | Description
39882  * :----------------------------------------------|:------|:------------------------------------
39883  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39884  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39885  *
39886  * Field Access Macros:
39887  *
39888  */
39889 /*
39890  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
39891  *
39892  * Byte is unmasked (i.e. is compared)
39893  */
39894 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED 0x0
39895 /*
39896  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
39897  *
39898  * Byte is masked (i.e. not compared)
39899  */
39900 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED 0x1
39901 
39902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
39903 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_LSB 26
39904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
39905 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_MSB 26
39906 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
39907 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_WIDTH 1
39908 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
39909 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET_MSK 0x04000000
39910 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
39911 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_CLR_MSK 0xfbffffff
39912 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
39913 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_RESET 0x0
39914 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 field value from a register. */
39915 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
39916 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value suitable for setting the register. */
39917 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
39918 
39919 /*
39920  * Field : Mask Byte Control - mbc_3
39921  *
39922  * This array of bits are mask control bits for comparison of each of the MAC
39923  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39924  * received DA or SA with the contents of MAC Address26 high and low registers.
39925  * Each bit controls the masking of the bytes. You can filter a group of addresses
39926  * (known as group address filtering) by masking one or more bytes of the address.
39927  *
39928  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39929  *
39930  * Field Enumeration Values:
39931  *
39932  * Enum | Value | Description
39933  * :----------------------------------------------|:------|:------------------------------------
39934  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39935  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39936  *
39937  * Field Access Macros:
39938  *
39939  */
39940 /*
39941  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
39942  *
39943  * Byte is unmasked (i.e. is compared)
39944  */
39945 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED 0x0
39946 /*
39947  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
39948  *
39949  * Byte is masked (i.e. not compared)
39950  */
39951 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED 0x1
39952 
39953 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
39954 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_LSB 27
39955 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
39956 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_MSB 27
39957 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
39958 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_WIDTH 1
39959 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
39960 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET_MSK 0x08000000
39961 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
39962 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_CLR_MSK 0xf7ffffff
39963 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
39964 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_RESET 0x0
39965 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 field value from a register. */
39966 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
39967 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value suitable for setting the register. */
39968 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
39969 
39970 /*
39971  * Field : Mask Byte Control - mbc_4
39972  *
39973  * This array of bits are mask control bits for comparison of each of the MAC
39974  * Address bytes. When masked, the MAC does not compare the corresponding byte of
39975  * received DA or SA with the contents of MAC Address26 high and low registers.
39976  * Each bit controls the masking of the bytes. You can filter a group of addresses
39977  * (known as group address filtering) by masking one or more bytes of the address.
39978  *
39979  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
39980  *
39981  * Field Enumeration Values:
39982  *
39983  * Enum | Value | Description
39984  * :----------------------------------------------|:------|:------------------------------------
39985  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
39986  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
39987  *
39988  * Field Access Macros:
39989  *
39990  */
39991 /*
39992  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
39993  *
39994  * Byte is unmasked (i.e. is compared)
39995  */
39996 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED 0x0
39997 /*
39998  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
39999  *
40000  * Byte is masked (i.e. not compared)
40001  */
40002 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED 0x1
40003 
40004 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
40005 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_LSB 28
40006 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
40007 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_MSB 28
40008 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
40009 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_WIDTH 1
40010 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
40011 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET_MSK 0x10000000
40012 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
40013 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_CLR_MSK 0xefffffff
40014 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
40015 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_RESET 0x0
40016 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 field value from a register. */
40017 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
40018 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value suitable for setting the register. */
40019 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
40020 
40021 /*
40022  * Field : Mask Byte Control - mbc_5
40023  *
40024  * This array of bits are mask control bits for comparison of each of the MAC
40025  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40026  * received DA or SA with the contents of MAC Address26 high and low registers.
40027  * Each bit controls the masking of the bytes. You can filter a group of addresses
40028  * (known as group address filtering) by masking one or more bytes of the address.
40029  *
40030  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40031  *
40032  * Field Enumeration Values:
40033  *
40034  * Enum | Value | Description
40035  * :----------------------------------------------|:------|:------------------------------------
40036  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40037  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40038  *
40039  * Field Access Macros:
40040  *
40041  */
40042 /*
40043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
40044  *
40045  * Byte is unmasked (i.e. is compared)
40046  */
40047 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED 0x0
40048 /*
40049  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
40050  *
40051  * Byte is masked (i.e. not compared)
40052  */
40053 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED 0x1
40054 
40055 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
40056 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_LSB 29
40057 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
40058 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_MSB 29
40059 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
40060 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_WIDTH 1
40061 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
40062 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET_MSK 0x20000000
40063 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
40064 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_CLR_MSK 0xdfffffff
40065 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
40066 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_RESET 0x0
40067 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 field value from a register. */
40068 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
40069 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value suitable for setting the register. */
40070 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
40071 
40072 /*
40073  * Field : Source Address - sa
40074  *
40075  * When this bit is enabled, the MAC Address26[47:0] is used to compare with the SA
40076  * fields of the received frame. When this bit is disabled, the MAC Address26[47:0]
40077  * is used to compare with the DA fields of the received frame.
40078  *
40079  * Field Enumeration Values:
40080  *
40081  * Enum | Value | Description
40082  * :----------------------------------------|:------|:-----------------------------
40083  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
40084  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END | 0x1 | MAC address compare enabled
40085  *
40086  * Field Access Macros:
40087  *
40088  */
40089 /*
40090  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
40091  *
40092  * MAC address compare disabled
40093  */
40094 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD 0x0
40095 /*
40096  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
40097  *
40098  * MAC address compare enabled
40099  */
40100 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END 0x1
40101 
40102 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
40103 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_LSB 30
40104 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
40105 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_MSB 30
40106 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
40107 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_WIDTH 1
40108 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
40109 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET_MSK 0x40000000
40110 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
40111 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_CLR_MSK 0xbfffffff
40112 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
40113 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_RESET 0x0
40114 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA field value from a register. */
40115 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
40116 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value suitable for setting the register. */
40117 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
40118 
40119 /*
40120  * Field : Address Enable - ae
40121  *
40122  * When this bit is enabled, the address filter block uses the 27th MAC address for
40123  * perfect filtering. When this bit is disabled, the address filter block ignores
40124  * the address for filtering.
40125  *
40126  * Field Enumeration Values:
40127  *
40128  * Enum | Value | Description
40129  * :----------------------------------------|:------|:--------------------------------------
40130  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
40131  * ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
40132  *
40133  * Field Access Macros:
40134  *
40135  */
40136 /*
40137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
40138  *
40139  * Second MAC address filtering disabled
40140  */
40141 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD 0x0
40142 /*
40143  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
40144  *
40145  * Second MAC address filtering enabled
40146  */
40147 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END 0x1
40148 
40149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
40150 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_LSB 31
40151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
40152 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_MSB 31
40153 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
40154 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_WIDTH 1
40155 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
40156 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET_MSK 0x80000000
40157 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
40158 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_CLR_MSK 0x7fffffff
40159 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
40160 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_RESET 0x0
40161 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE field value from a register. */
40162 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
40163 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value suitable for setting the register. */
40164 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
40165 
40166 #ifndef __ASSEMBLY__
40167 /*
40168  * WARNING: The C register and register group struct declarations are provided for
40169  * convenience and illustrative purposes. They should, however, be used with
40170  * caution as the C language standard provides no guarantees about the alignment or
40171  * atomicity of device memory accesses. The recommended practice for writing
40172  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40173  * alt_write_word() functions.
40174  *
40175  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH.
40176  */
40177 struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s
40178 {
40179  uint32_t addrhi : 16; /* MAC Address26 [47:32] */
40180  uint32_t : 8; /* *UNDEFINED* */
40181  uint32_t mbc_0 : 1; /* Mask Byte Control */
40182  uint32_t mbc_1 : 1; /* Mask Byte Control */
40183  uint32_t mbc_2 : 1; /* Mask Byte Control */
40184  uint32_t mbc_3 : 1; /* Mask Byte Control */
40185  uint32_t mbc_4 : 1; /* Mask Byte Control */
40186  uint32_t mbc_5 : 1; /* Mask Byte Control */
40187  uint32_t sa : 1; /* Source Address */
40188  uint32_t ae : 1; /* Address Enable */
40189 };
40190 
40191 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH. */
40192 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t;
40193 #endif /* __ASSEMBLY__ */
40194 
40195 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register from the beginning of the component. */
40196 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST 0x850
40197 /* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register. */
40198 #define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST))
40199 
40200 /*
40201  * Register : Register 533 (MAC Address26 Low Register) - MAC_Address26_Low
40202  *
40203  * The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC
40204  * address of the station.
40205  *
40206  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
40207  * format.
40208  *
40209  * Register Layout
40210  *
40211  * Bits | Access | Reset | Description
40212  * :-------|:-------|:-----------|:---------------------
40213  * [31:0] | RW | 0xffffffff | MAC Address26 [31:0]
40214  *
40215  */
40216 /*
40217  * Field : MAC Address26 [31:0] - addrlo
40218  *
40219  * This field contains the lower 32 bits of the 27th 6-byte MAC address. The
40220  * content of this field is undefined until loaded by software after the
40221  * initialization process.
40222  *
40223  * Field Access Macros:
40224  *
40225  */
40226 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
40227 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_LSB 0
40228 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
40229 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_MSB 31
40230 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
40231 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_WIDTH 32
40232 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
40233 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET_MSK 0xffffffff
40234 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
40235 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_CLR_MSK 0x00000000
40236 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
40237 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_RESET 0xffffffff
40238 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO field value from a register. */
40239 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
40240 /* Produces a ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value suitable for setting the register. */
40241 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
40242 
40243 #ifndef __ASSEMBLY__
40244 /*
40245  * WARNING: The C register and register group struct declarations are provided for
40246  * convenience and illustrative purposes. They should, however, be used with
40247  * caution as the C language standard provides no guarantees about the alignment or
40248  * atomicity of device memory accesses. The recommended practice for writing
40249  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40250  * alt_write_word() functions.
40251  *
40252  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW.
40253  */
40254 struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s
40255 {
40256  uint32_t addrlo : 32; /* MAC Address26 [31:0] */
40257 };
40258 
40259 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW. */
40260 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s ALT_EMAC_GMAC_MAC_ADDR26_LOW_t;
40261 #endif /* __ASSEMBLY__ */
40262 
40263 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register from the beginning of the component. */
40264 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST 0x854
40265 /* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register. */
40266 #define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST))
40267 
40268 /*
40269  * Register : Register 534 (MAC Address27 High Register) - MAC_Address27_High
40270  *
40271  * The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC
40272  * address of the station. Because the MAC address registers are configured to be
40273  * double-synchronized to the (G)MII clock domains, the synchronization is
40274  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
40275  * endian mode) of the MAC Address27 Low Register are written. For proper
40276  * synchronization updates, the consecutive writes to this Address Low Register
40277  * should be performed after at least four clock cycles in the destination clock
40278  * domain.
40279  *
40280  * Note that all MAC Address High registers (except MAC Address0 High) have the
40281  * same format.
40282  *
40283  * Register Layout
40284  *
40285  * Bits | Access | Reset | Description
40286  * :--------|:-------|:-------|:----------------------
40287  * [15:0] | RW | 0xffff | MAC Address27 [47:32]
40288  * [23:16] | ??? | 0x0 | *UNDEFINED*
40289  * [24] | RW | 0x0 | Mask Byte Control
40290  * [25] | RW | 0x0 | Mask Byte Control
40291  * [26] | RW | 0x0 | Mask Byte Control
40292  * [27] | RW | 0x0 | Mask Byte Control
40293  * [28] | RW | 0x0 | Mask Byte Control
40294  * [29] | RW | 0x0 | Mask Byte Control
40295  * [30] | RW | 0x0 | Source Address
40296  * [31] | RW | 0x0 | Address Enable
40297  *
40298  */
40299 /*
40300  * Field : MAC Address27 [47:32] - addrhi
40301  *
40302  * This field contains the upper 16 bits (47:32) of the 28th 6-byte MAC address.
40303  *
40304  * Field Access Macros:
40305  *
40306  */
40307 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
40308 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_LSB 0
40309 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
40310 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_MSB 15
40311 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
40312 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_WIDTH 16
40313 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
40314 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET_MSK 0x0000ffff
40315 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
40316 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_CLR_MSK 0xffff0000
40317 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
40318 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_RESET 0xffff
40319 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI field value from a register. */
40320 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
40321 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value suitable for setting the register. */
40322 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
40323 
40324 /*
40325  * Field : Mask Byte Control - mbc_0
40326  *
40327  * This array of bits are mask control bits for comparison of each of the MAC
40328  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40329  * received DA or SA with the contents of MAC Address27 high and low registers.
40330  * Each bit controls the masking of the bytes. You can filter a group of addresses
40331  * (known as group address filtering) by masking one or more bytes of the address.
40332  *
40333  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40334  *
40335  * Field Enumeration Values:
40336  *
40337  * Enum | Value | Description
40338  * :----------------------------------------------|:------|:------------------------------------
40339  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40340  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40341  *
40342  * Field Access Macros:
40343  *
40344  */
40345 /*
40346  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
40347  *
40348  * Byte is unmasked (i.e. is compared)
40349  */
40350 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED 0x0
40351 /*
40352  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
40353  *
40354  * Byte is masked (i.e. not compared)
40355  */
40356 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED 0x1
40357 
40358 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
40359 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_LSB 24
40360 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
40361 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_MSB 24
40362 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
40363 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_WIDTH 1
40364 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
40365 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET_MSK 0x01000000
40366 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
40367 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_CLR_MSK 0xfeffffff
40368 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
40369 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_RESET 0x0
40370 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 field value from a register. */
40371 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
40372 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value suitable for setting the register. */
40373 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
40374 
40375 /*
40376  * Field : Mask Byte Control - mbc_1
40377  *
40378  * This array of bits are mask control bits for comparison of each of the MAC
40379  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40380  * received DA or SA with the contents of MAC Address27 high and low registers.
40381  * Each bit controls the masking of the bytes. You can filter a group of addresses
40382  * (known as group address filtering) by masking one or more bytes of the address.
40383  *
40384  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40385  *
40386  * Field Enumeration Values:
40387  *
40388  * Enum | Value | Description
40389  * :----------------------------------------------|:------|:------------------------------------
40390  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40391  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40392  *
40393  * Field Access Macros:
40394  *
40395  */
40396 /*
40397  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
40398  *
40399  * Byte is unmasked (i.e. is compared)
40400  */
40401 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED 0x0
40402 /*
40403  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
40404  *
40405  * Byte is masked (i.e. not compared)
40406  */
40407 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED 0x1
40408 
40409 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
40410 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_LSB 25
40411 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
40412 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_MSB 25
40413 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
40414 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_WIDTH 1
40415 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
40416 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET_MSK 0x02000000
40417 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
40418 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_CLR_MSK 0xfdffffff
40419 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
40420 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_RESET 0x0
40421 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 field value from a register. */
40422 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
40423 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value suitable for setting the register. */
40424 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
40425 
40426 /*
40427  * Field : Mask Byte Control - mbc_2
40428  *
40429  * This array of bits are mask control bits for comparison of each of the MAC
40430  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40431  * received DA or SA with the contents of MAC Address27 high and low registers.
40432  * Each bit controls the masking of the bytes. You can filter a group of addresses
40433  * (known as group address filtering) by masking one or more bytes of the address.
40434  *
40435  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40436  *
40437  * Field Enumeration Values:
40438  *
40439  * Enum | Value | Description
40440  * :----------------------------------------------|:------|:------------------------------------
40441  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40442  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40443  *
40444  * Field Access Macros:
40445  *
40446  */
40447 /*
40448  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
40449  *
40450  * Byte is unmasked (i.e. is compared)
40451  */
40452 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED 0x0
40453 /*
40454  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
40455  *
40456  * Byte is masked (i.e. not compared)
40457  */
40458 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED 0x1
40459 
40460 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
40461 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_LSB 26
40462 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
40463 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_MSB 26
40464 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
40465 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_WIDTH 1
40466 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
40467 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET_MSK 0x04000000
40468 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
40469 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_CLR_MSK 0xfbffffff
40470 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
40471 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_RESET 0x0
40472 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 field value from a register. */
40473 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
40474 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value suitable for setting the register. */
40475 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
40476 
40477 /*
40478  * Field : Mask Byte Control - mbc_3
40479  *
40480  * This array of bits are mask control bits for comparison of each of the MAC
40481  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40482  * received DA or SA with the contents of MAC Address27 high and low registers.
40483  * Each bit controls the masking of the bytes. You can filter a group of addresses
40484  * (known as group address filtering) by masking one or more bytes of the address.
40485  *
40486  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40487  *
40488  * Field Enumeration Values:
40489  *
40490  * Enum | Value | Description
40491  * :----------------------------------------------|:------|:------------------------------------
40492  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40493  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40494  *
40495  * Field Access Macros:
40496  *
40497  */
40498 /*
40499  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
40500  *
40501  * Byte is unmasked (i.e. is compared)
40502  */
40503 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED 0x0
40504 /*
40505  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
40506  *
40507  * Byte is masked (i.e. not compared)
40508  */
40509 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED 0x1
40510 
40511 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
40512 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_LSB 27
40513 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
40514 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_MSB 27
40515 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
40516 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_WIDTH 1
40517 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
40518 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET_MSK 0x08000000
40519 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
40520 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_CLR_MSK 0xf7ffffff
40521 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
40522 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_RESET 0x0
40523 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 field value from a register. */
40524 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
40525 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value suitable for setting the register. */
40526 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
40527 
40528 /*
40529  * Field : Mask Byte Control - mbc_4
40530  *
40531  * This array of bits are mask control bits for comparison of each of the MAC
40532  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40533  * received DA or SA with the contents of MAC Address27 high and low registers.
40534  * Each bit controls the masking of the bytes. You can filter a group of addresses
40535  * (known as group address filtering) by masking one or more bytes of the address.
40536  *
40537  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40538  *
40539  * Field Enumeration Values:
40540  *
40541  * Enum | Value | Description
40542  * :----------------------------------------------|:------|:------------------------------------
40543  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40544  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40545  *
40546  * Field Access Macros:
40547  *
40548  */
40549 /*
40550  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
40551  *
40552  * Byte is unmasked (i.e. is compared)
40553  */
40554 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED 0x0
40555 /*
40556  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
40557  *
40558  * Byte is masked (i.e. not compared)
40559  */
40560 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED 0x1
40561 
40562 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
40563 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_LSB 28
40564 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
40565 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_MSB 28
40566 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
40567 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_WIDTH 1
40568 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
40569 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET_MSK 0x10000000
40570 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
40571 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_CLR_MSK 0xefffffff
40572 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
40573 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_RESET 0x0
40574 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 field value from a register. */
40575 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
40576 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value suitable for setting the register. */
40577 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
40578 
40579 /*
40580  * Field : Mask Byte Control - mbc_5
40581  *
40582  * This array of bits are mask control bits for comparison of each of the MAC
40583  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40584  * received DA or SA with the contents of MAC Address27 high and low registers.
40585  * Each bit controls the masking of the bytes. You can filter a group of addresses
40586  * (known as group address filtering) by masking one or more bytes of the address.
40587  *
40588  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40589  *
40590  * Field Enumeration Values:
40591  *
40592  * Enum | Value | Description
40593  * :----------------------------------------------|:------|:------------------------------------
40594  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40595  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40596  *
40597  * Field Access Macros:
40598  *
40599  */
40600 /*
40601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
40602  *
40603  * Byte is unmasked (i.e. is compared)
40604  */
40605 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED 0x0
40606 /*
40607  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
40608  *
40609  * Byte is masked (i.e. not compared)
40610  */
40611 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED 0x1
40612 
40613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
40614 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_LSB 29
40615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
40616 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_MSB 29
40617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
40618 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_WIDTH 1
40619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
40620 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET_MSK 0x20000000
40621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
40622 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_CLR_MSK 0xdfffffff
40623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
40624 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_RESET 0x0
40625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 field value from a register. */
40626 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
40627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value suitable for setting the register. */
40628 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
40629 
40630 /*
40631  * Field : Source Address - sa
40632  *
40633  * When this bit is enabled, the MAC Address27[47:0] is used to compare with the SA
40634  * fields of the received frame. When this bit is disabled, the MAC Address27[47:0]
40635  * is used to compare with the DA fields of the received frame.
40636  *
40637  * Field Enumeration Values:
40638  *
40639  * Enum | Value | Description
40640  * :----------------------------------------|:------|:-----------------------------
40641  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
40642  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END | 0x1 | MAC address compare enabled
40643  *
40644  * Field Access Macros:
40645  *
40646  */
40647 /*
40648  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
40649  *
40650  * MAC address compare disabled
40651  */
40652 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD 0x0
40653 /*
40654  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
40655  *
40656  * MAC address compare enabled
40657  */
40658 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END 0x1
40659 
40660 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
40661 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_LSB 30
40662 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
40663 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_MSB 30
40664 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
40665 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_WIDTH 1
40666 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
40667 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET_MSK 0x40000000
40668 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
40669 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_CLR_MSK 0xbfffffff
40670 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
40671 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_RESET 0x0
40672 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA field value from a register. */
40673 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
40674 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value suitable for setting the register. */
40675 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
40676 
40677 /*
40678  * Field : Address Enable - ae
40679  *
40680  * When this bit is enabled, the address filter block uses the 28th MAC address for
40681  * perfect filtering. When this bit is disabled, the address filter block ignores
40682  * the address for filtering.
40683  *
40684  * Field Enumeration Values:
40685  *
40686  * Enum | Value | Description
40687  * :----------------------------------------|:------|:--------------------------------------
40688  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
40689  * ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
40690  *
40691  * Field Access Macros:
40692  *
40693  */
40694 /*
40695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
40696  *
40697  * Second MAC address filtering disabled
40698  */
40699 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD 0x0
40700 /*
40701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
40702  *
40703  * Second MAC address filtering enabled
40704  */
40705 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END 0x1
40706 
40707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
40708 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_LSB 31
40709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
40710 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_MSB 31
40711 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
40712 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_WIDTH 1
40713 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
40714 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET_MSK 0x80000000
40715 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
40716 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_CLR_MSK 0x7fffffff
40717 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
40718 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_RESET 0x0
40719 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE field value from a register. */
40720 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
40721 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value suitable for setting the register. */
40722 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
40723 
40724 #ifndef __ASSEMBLY__
40725 /*
40726  * WARNING: The C register and register group struct declarations are provided for
40727  * convenience and illustrative purposes. They should, however, be used with
40728  * caution as the C language standard provides no guarantees about the alignment or
40729  * atomicity of device memory accesses. The recommended practice for writing
40730  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40731  * alt_write_word() functions.
40732  *
40733  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH.
40734  */
40735 struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s
40736 {
40737  uint32_t addrhi : 16; /* MAC Address27 [47:32] */
40738  uint32_t : 8; /* *UNDEFINED* */
40739  uint32_t mbc_0 : 1; /* Mask Byte Control */
40740  uint32_t mbc_1 : 1; /* Mask Byte Control */
40741  uint32_t mbc_2 : 1; /* Mask Byte Control */
40742  uint32_t mbc_3 : 1; /* Mask Byte Control */
40743  uint32_t mbc_4 : 1; /* Mask Byte Control */
40744  uint32_t mbc_5 : 1; /* Mask Byte Control */
40745  uint32_t sa : 1; /* Source Address */
40746  uint32_t ae : 1; /* Address Enable */
40747 };
40748 
40749 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH. */
40750 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t;
40751 #endif /* __ASSEMBLY__ */
40752 
40753 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register from the beginning of the component. */
40754 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST 0x858
40755 /* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register. */
40756 #define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST))
40757 
40758 /*
40759  * Register : Register 535 (MAC Address27 Low Register) - MAC_Address27_Low
40760  *
40761  * The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC
40762  * address of the station.
40763  *
40764  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
40765  * format.
40766  *
40767  * Register Layout
40768  *
40769  * Bits | Access | Reset | Description
40770  * :-------|:-------|:-----------|:---------------------
40771  * [31:0] | RW | 0xffffffff | MAC Address27 [31:0]
40772  *
40773  */
40774 /*
40775  * Field : MAC Address27 [31:0] - addrlo
40776  *
40777  * This field contains the lower 32 bits of the 28th 6-byte MAC address. The
40778  * content of this field is undefined until loaded by software after the
40779  * initialization process.
40780  *
40781  * Field Access Macros:
40782  *
40783  */
40784 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
40785 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_LSB 0
40786 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
40787 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_MSB 31
40788 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
40789 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_WIDTH 32
40790 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
40791 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET_MSK 0xffffffff
40792 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
40793 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_CLR_MSK 0x00000000
40794 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
40795 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_RESET 0xffffffff
40796 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO field value from a register. */
40797 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
40798 /* Produces a ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value suitable for setting the register. */
40799 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
40800 
40801 #ifndef __ASSEMBLY__
40802 /*
40803  * WARNING: The C register and register group struct declarations are provided for
40804  * convenience and illustrative purposes. They should, however, be used with
40805  * caution as the C language standard provides no guarantees about the alignment or
40806  * atomicity of device memory accesses. The recommended practice for writing
40807  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
40808  * alt_write_word() functions.
40809  *
40810  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW.
40811  */
40812 struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s
40813 {
40814  uint32_t addrlo : 32; /* MAC Address27 [31:0] */
40815 };
40816 
40817 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW. */
40818 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s ALT_EMAC_GMAC_MAC_ADDR27_LOW_t;
40819 #endif /* __ASSEMBLY__ */
40820 
40821 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register from the beginning of the component. */
40822 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST 0x85c
40823 /* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register. */
40824 #define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST))
40825 
40826 /*
40827  * Register : Register 536 (MAC Address28 High Register) - MAC_Address28_High
40828  *
40829  * The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC
40830  * address of the station. Because the MAC address registers are configured to be
40831  * double-synchronized to the (G)MII clock domains, the synchronization is
40832  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
40833  * endian mode) of the MAC Address28 Low Register are written. For proper
40834  * synchronization updates, the consecutive writes to this Address Low Register
40835  * should be performed after at least four clock cycles in the destination clock
40836  * domain.
40837  *
40838  * Note that all MAC Address High registers (except MAC Address0 High) have the
40839  * same format.
40840  *
40841  * Register Layout
40842  *
40843  * Bits | Access | Reset | Description
40844  * :--------|:-------|:-------|:----------------------
40845  * [15:0] | RW | 0xffff | MAC Address28 [47:32]
40846  * [23:16] | ??? | 0x0 | *UNDEFINED*
40847  * [24] | RW | 0x0 | Mask Byte Control
40848  * [25] | RW | 0x0 | Mask Byte Control
40849  * [26] | RW | 0x0 | Mask Byte Control
40850  * [27] | RW | 0x0 | Mask Byte Control
40851  * [28] | RW | 0x0 | Mask Byte Control
40852  * [29] | RW | 0x0 | Mask Byte Control
40853  * [30] | RW | 0x0 | Source Address
40854  * [31] | RW | 0x0 | Address Enable
40855  *
40856  */
40857 /*
40858  * Field : MAC Address28 [47:32] - addrhi
40859  *
40860  * This field contains the upper 16 bits (47:32) of the 29th 6-byte MAC address.
40861  *
40862  * Field Access Macros:
40863  *
40864  */
40865 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
40866 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_LSB 0
40867 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
40868 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_MSB 15
40869 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
40870 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_WIDTH 16
40871 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
40872 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET_MSK 0x0000ffff
40873 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
40874 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_CLR_MSK 0xffff0000
40875 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
40876 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_RESET 0xffff
40877 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI field value from a register. */
40878 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
40879 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value suitable for setting the register. */
40880 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
40881 
40882 /*
40883  * Field : Mask Byte Control - mbc_0
40884  *
40885  * This array of bits are mask control bits for comparison of each of the MAC
40886  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40887  * received DA or SA with the contents of MAC Address28 high and low registers.
40888  * Each bit controls the masking of the bytes. You can filter a group of addresses
40889  * (known as group address filtering) by masking one or more bytes of the address.
40890  *
40891  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40892  *
40893  * Field Enumeration Values:
40894  *
40895  * Enum | Value | Description
40896  * :----------------------------------------------|:------|:------------------------------------
40897  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40898  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40899  *
40900  * Field Access Macros:
40901  *
40902  */
40903 /*
40904  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
40905  *
40906  * Byte is unmasked (i.e. is compared)
40907  */
40908 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED 0x0
40909 /*
40910  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
40911  *
40912  * Byte is masked (i.e. not compared)
40913  */
40914 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED 0x1
40915 
40916 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
40917 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_LSB 24
40918 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
40919 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_MSB 24
40920 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
40921 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_WIDTH 1
40922 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
40923 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET_MSK 0x01000000
40924 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
40925 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_CLR_MSK 0xfeffffff
40926 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
40927 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_RESET 0x0
40928 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 field value from a register. */
40929 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
40930 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value suitable for setting the register. */
40931 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
40932 
40933 /*
40934  * Field : Mask Byte Control - mbc_1
40935  *
40936  * This array of bits are mask control bits for comparison of each of the MAC
40937  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40938  * received DA or SA with the contents of MAC Address28 high and low registers.
40939  * Each bit controls the masking of the bytes. You can filter a group of addresses
40940  * (known as group address filtering) by masking one or more bytes of the address.
40941  *
40942  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40943  *
40944  * Field Enumeration Values:
40945  *
40946  * Enum | Value | Description
40947  * :----------------------------------------------|:------|:------------------------------------
40948  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
40949  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
40950  *
40951  * Field Access Macros:
40952  *
40953  */
40954 /*
40955  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
40956  *
40957  * Byte is unmasked (i.e. is compared)
40958  */
40959 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED 0x0
40960 /*
40961  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
40962  *
40963  * Byte is masked (i.e. not compared)
40964  */
40965 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED 0x1
40966 
40967 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
40968 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_LSB 25
40969 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
40970 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_MSB 25
40971 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
40972 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_WIDTH 1
40973 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
40974 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET_MSK 0x02000000
40975 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
40976 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_CLR_MSK 0xfdffffff
40977 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
40978 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_RESET 0x0
40979 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 field value from a register. */
40980 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
40981 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value suitable for setting the register. */
40982 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
40983 
40984 /*
40985  * Field : Mask Byte Control - mbc_2
40986  *
40987  * This array of bits are mask control bits for comparison of each of the MAC
40988  * Address bytes. When masked, the MAC does not compare the corresponding byte of
40989  * received DA or SA with the contents of MAC Address28 high and low registers.
40990  * Each bit controls the masking of the bytes. You can filter a group of addresses
40991  * (known as group address filtering) by masking one or more bytes of the address.
40992  *
40993  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
40994  *
40995  * Field Enumeration Values:
40996  *
40997  * Enum | Value | Description
40998  * :----------------------------------------------|:------|:------------------------------------
40999  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41000  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41001  *
41002  * Field Access Macros:
41003  *
41004  */
41005 /*
41006  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
41007  *
41008  * Byte is unmasked (i.e. is compared)
41009  */
41010 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED 0x0
41011 /*
41012  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
41013  *
41014  * Byte is masked (i.e. not compared)
41015  */
41016 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED 0x1
41017 
41018 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
41019 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_LSB 26
41020 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
41021 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_MSB 26
41022 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
41023 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_WIDTH 1
41024 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
41025 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET_MSK 0x04000000
41026 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
41027 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_CLR_MSK 0xfbffffff
41028 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
41029 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_RESET 0x0
41030 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 field value from a register. */
41031 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
41032 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value suitable for setting the register. */
41033 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
41034 
41035 /*
41036  * Field : Mask Byte Control - mbc_3
41037  *
41038  * This array of bits are mask control bits for comparison of each of the MAC
41039  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41040  * received DA or SA with the contents of MAC Address28 high and low registers.
41041  * Each bit controls the masking of the bytes. You can filter a group of addresses
41042  * (known as group address filtering) by masking one or more bytes of the address.
41043  *
41044  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41045  *
41046  * Field Enumeration Values:
41047  *
41048  * Enum | Value | Description
41049  * :----------------------------------------------|:------|:------------------------------------
41050  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41051  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41052  *
41053  * Field Access Macros:
41054  *
41055  */
41056 /*
41057  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
41058  *
41059  * Byte is unmasked (i.e. is compared)
41060  */
41061 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED 0x0
41062 /*
41063  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
41064  *
41065  * Byte is masked (i.e. not compared)
41066  */
41067 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED 0x1
41068 
41069 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
41070 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_LSB 27
41071 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
41072 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_MSB 27
41073 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
41074 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_WIDTH 1
41075 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
41076 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET_MSK 0x08000000
41077 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
41078 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_CLR_MSK 0xf7ffffff
41079 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
41080 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_RESET 0x0
41081 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 field value from a register. */
41082 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
41083 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value suitable for setting the register. */
41084 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
41085 
41086 /*
41087  * Field : Mask Byte Control - mbc_4
41088  *
41089  * This array of bits are mask control bits for comparison of each of the MAC
41090  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41091  * received DA or SA with the contents of MAC Address28 high and low registers.
41092  * Each bit controls the masking of the bytes. You can filter a group of addresses
41093  * (known as group address filtering) by masking one or more bytes of the address.
41094  *
41095  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41096  *
41097  * Field Enumeration Values:
41098  *
41099  * Enum | Value | Description
41100  * :----------------------------------------------|:------|:------------------------------------
41101  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41102  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41103  *
41104  * Field Access Macros:
41105  *
41106  */
41107 /*
41108  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
41109  *
41110  * Byte is unmasked (i.e. is compared)
41111  */
41112 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED 0x0
41113 /*
41114  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
41115  *
41116  * Byte is masked (i.e. not compared)
41117  */
41118 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED 0x1
41119 
41120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
41121 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_LSB 28
41122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
41123 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_MSB 28
41124 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
41125 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_WIDTH 1
41126 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
41127 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET_MSK 0x10000000
41128 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
41129 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_CLR_MSK 0xefffffff
41130 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
41131 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_RESET 0x0
41132 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 field value from a register. */
41133 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
41134 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value suitable for setting the register. */
41135 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
41136 
41137 /*
41138  * Field : Mask Byte Control - mbc_5
41139  *
41140  * This array of bits are mask control bits for comparison of each of the MAC
41141  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41142  * received DA or SA with the contents of MAC Address28 high and low registers.
41143  * Each bit controls the masking of the bytes. You can filter a group of addresses
41144  * (known as group address filtering) by masking one or more bytes of the address.
41145  *
41146  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41147  *
41148  * Field Enumeration Values:
41149  *
41150  * Enum | Value | Description
41151  * :----------------------------------------------|:------|:------------------------------------
41152  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41153  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41154  *
41155  * Field Access Macros:
41156  *
41157  */
41158 /*
41159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
41160  *
41161  * Byte is unmasked (i.e. is compared)
41162  */
41163 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED 0x0
41164 /*
41165  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
41166  *
41167  * Byte is masked (i.e. not compared)
41168  */
41169 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED 0x1
41170 
41171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
41172 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_LSB 29
41173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
41174 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_MSB 29
41175 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
41176 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_WIDTH 1
41177 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
41178 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET_MSK 0x20000000
41179 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
41180 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_CLR_MSK 0xdfffffff
41181 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
41182 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_RESET 0x0
41183 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 field value from a register. */
41184 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
41185 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value suitable for setting the register. */
41186 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
41187 
41188 /*
41189  * Field : Source Address - sa
41190  *
41191  * When this bit is enabled, the MAC Address28[47:0] is used to compare with the SA
41192  * fields of the received frame. When this bit is disabled, the MAC Address28[47:0]
41193  * is used to compare with the DA fields of the received frame.
41194  *
41195  * Field Enumeration Values:
41196  *
41197  * Enum | Value | Description
41198  * :----------------------------------------|:------|:-----------------------------
41199  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
41200  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END | 0x1 | MAC address compare enabled
41201  *
41202  * Field Access Macros:
41203  *
41204  */
41205 /*
41206  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
41207  *
41208  * MAC address compare disabled
41209  */
41210 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD 0x0
41211 /*
41212  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
41213  *
41214  * MAC address compare enabled
41215  */
41216 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END 0x1
41217 
41218 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
41219 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_LSB 30
41220 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
41221 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_MSB 30
41222 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
41223 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_WIDTH 1
41224 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
41225 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET_MSK 0x40000000
41226 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
41227 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_CLR_MSK 0xbfffffff
41228 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
41229 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_RESET 0x0
41230 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA field value from a register. */
41231 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
41232 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value suitable for setting the register. */
41233 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
41234 
41235 /*
41236  * Field : Address Enable - ae
41237  *
41238  * When this bit is enabled, the address filter block uses the 29th MAC address for
41239  * perfect filtering. When this bit is disabled, the address filter block ignores
41240  * the address for filtering.
41241  *
41242  * Field Enumeration Values:
41243  *
41244  * Enum | Value | Description
41245  * :----------------------------------------|:------|:--------------------------------------
41246  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
41247  * ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
41248  *
41249  * Field Access Macros:
41250  *
41251  */
41252 /*
41253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
41254  *
41255  * Second MAC address filtering disabled
41256  */
41257 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD 0x0
41258 /*
41259  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
41260  *
41261  * Second MAC address filtering enabled
41262  */
41263 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END 0x1
41264 
41265 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
41266 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_LSB 31
41267 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
41268 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_MSB 31
41269 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
41270 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_WIDTH 1
41271 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
41272 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET_MSK 0x80000000
41273 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
41274 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_CLR_MSK 0x7fffffff
41275 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
41276 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_RESET 0x0
41277 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE field value from a register. */
41278 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
41279 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value suitable for setting the register. */
41280 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
41281 
41282 #ifndef __ASSEMBLY__
41283 /*
41284  * WARNING: The C register and register group struct declarations are provided for
41285  * convenience and illustrative purposes. They should, however, be used with
41286  * caution as the C language standard provides no guarantees about the alignment or
41287  * atomicity of device memory accesses. The recommended practice for writing
41288  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41289  * alt_write_word() functions.
41290  *
41291  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH.
41292  */
41293 struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s
41294 {
41295  uint32_t addrhi : 16; /* MAC Address28 [47:32] */
41296  uint32_t : 8; /* *UNDEFINED* */
41297  uint32_t mbc_0 : 1; /* Mask Byte Control */
41298  uint32_t mbc_1 : 1; /* Mask Byte Control */
41299  uint32_t mbc_2 : 1; /* Mask Byte Control */
41300  uint32_t mbc_3 : 1; /* Mask Byte Control */
41301  uint32_t mbc_4 : 1; /* Mask Byte Control */
41302  uint32_t mbc_5 : 1; /* Mask Byte Control */
41303  uint32_t sa : 1; /* Source Address */
41304  uint32_t ae : 1; /* Address Enable */
41305 };
41306 
41307 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH. */
41308 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t;
41309 #endif /* __ASSEMBLY__ */
41310 
41311 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register from the beginning of the component. */
41312 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST 0x860
41313 /* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register. */
41314 #define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST))
41315 
41316 /*
41317  * Register : Register 537 (MAC Address28 Low Register) - MAC_Address28_Low
41318  *
41319  * The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC
41320  * address of the station.
41321  *
41322  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
41323  * format.
41324  *
41325  * Register Layout
41326  *
41327  * Bits | Access | Reset | Description
41328  * :-------|:-------|:-----------|:---------------------
41329  * [31:0] | RW | 0xffffffff | MAC Address28 [31:0]
41330  *
41331  */
41332 /*
41333  * Field : MAC Address28 [31:0] - addrlo
41334  *
41335  * This field contains the lower 32 bits of the 29th 6-byte MAC address. The
41336  * content of this field is undefined until loaded by software after the
41337  * initialization process.
41338  *
41339  * Field Access Macros:
41340  *
41341  */
41342 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
41343 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_LSB 0
41344 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
41345 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_MSB 31
41346 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
41347 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_WIDTH 32
41348 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
41349 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET_MSK 0xffffffff
41350 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
41351 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_CLR_MSK 0x00000000
41352 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
41353 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_RESET 0xffffffff
41354 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO field value from a register. */
41355 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
41356 /* Produces a ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value suitable for setting the register. */
41357 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
41358 
41359 #ifndef __ASSEMBLY__
41360 /*
41361  * WARNING: The C register and register group struct declarations are provided for
41362  * convenience and illustrative purposes. They should, however, be used with
41363  * caution as the C language standard provides no guarantees about the alignment or
41364  * atomicity of device memory accesses. The recommended practice for writing
41365  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41366  * alt_write_word() functions.
41367  *
41368  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW.
41369  */
41370 struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s
41371 {
41372  uint32_t addrlo : 32; /* MAC Address28 [31:0] */
41373 };
41374 
41375 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW. */
41376 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s ALT_EMAC_GMAC_MAC_ADDR28_LOW_t;
41377 #endif /* __ASSEMBLY__ */
41378 
41379 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register from the beginning of the component. */
41380 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST 0x864
41381 /* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register. */
41382 #define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST))
41383 
41384 /*
41385  * Register : Register 538 (MAC Address29 High Register) - MAC_Address29_High
41386  *
41387  * The MAC Address29 High register holds the upper 16 bits of the 30th 6-byte MAC
41388  * address of the station. Because the MAC address registers are configured to be
41389  * double-synchronized to the (G)MII clock domains, the synchronization is
41390  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
41391  * endian mode) of the MAC Address29 Low Register are written. For proper
41392  * synchronization updates, the consecutive writes to this Address Low Register
41393  * should be performed after at least four clock cycles in the destination clock
41394  * domain.
41395  *
41396  * Note that all MAC Address High registers (except MAC Address0 High) have the
41397  * same format.
41398  *
41399  * Register Layout
41400  *
41401  * Bits | Access | Reset | Description
41402  * :--------|:-------|:-------|:----------------------
41403  * [15:0] | RW | 0xffff | MAC Address29 [47:32]
41404  * [23:16] | ??? | 0x0 | *UNDEFINED*
41405  * [24] | RW | 0x0 | Mask Byte Control
41406  * [25] | RW | 0x0 | Mask Byte Control
41407  * [26] | RW | 0x0 | Mask Byte Control
41408  * [27] | RW | 0x0 | Mask Byte Control
41409  * [28] | RW | 0x0 | Mask Byte Control
41410  * [29] | RW | 0x0 | Mask Byte Control
41411  * [30] | RW | 0x0 | Source Address
41412  * [31] | RW | 0x0 | Address Enable
41413  *
41414  */
41415 /*
41416  * Field : MAC Address29 [47:32] - addrhi
41417  *
41418  * This field contains the upper 16 bits (47:32) of the 30th 6-byte MAC address.
41419  *
41420  * Field Access Macros:
41421  *
41422  */
41423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
41424 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_LSB 0
41425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
41426 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_MSB 15
41427 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
41428 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_WIDTH 16
41429 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
41430 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET_MSK 0x0000ffff
41431 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
41432 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_CLR_MSK 0xffff0000
41433 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
41434 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_RESET 0xffff
41435 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI field value from a register. */
41436 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
41437 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value suitable for setting the register. */
41438 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
41439 
41440 /*
41441  * Field : Mask Byte Control - mbc_0
41442  *
41443  * This array of bits are mask control bits for comparison of each of the MAC
41444  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41445  * received DA or SA with the contents of MAC Address29 high and low registers.
41446  * Each bit controls the masking of the bytes. You can filter a group of addresses
41447  * (known as group address filtering) by masking one or more bytes of the address.
41448  *
41449  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41450  *
41451  * Field Enumeration Values:
41452  *
41453  * Enum | Value | Description
41454  * :----------------------------------------------|:------|:------------------------------------
41455  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41456  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41457  *
41458  * Field Access Macros:
41459  *
41460  */
41461 /*
41462  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
41463  *
41464  * Byte is unmasked (i.e. is compared)
41465  */
41466 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED 0x0
41467 /*
41468  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
41469  *
41470  * Byte is masked (i.e. not compared)
41471  */
41472 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED 0x1
41473 
41474 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
41475 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_LSB 24
41476 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
41477 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_MSB 24
41478 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
41479 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_WIDTH 1
41480 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
41481 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET_MSK 0x01000000
41482 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
41483 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_CLR_MSK 0xfeffffff
41484 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
41485 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_RESET 0x0
41486 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 field value from a register. */
41487 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
41488 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value suitable for setting the register. */
41489 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
41490 
41491 /*
41492  * Field : Mask Byte Control - mbc_1
41493  *
41494  * This array of bits are mask control bits for comparison of each of the MAC
41495  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41496  * received DA or SA with the contents of MAC Address29 high and low registers.
41497  * Each bit controls the masking of the bytes. You can filter a group of addresses
41498  * (known as group address filtering) by masking one or more bytes of the address.
41499  *
41500  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41501  *
41502  * Field Enumeration Values:
41503  *
41504  * Enum | Value | Description
41505  * :----------------------------------------------|:------|:------------------------------------
41506  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41507  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41508  *
41509  * Field Access Macros:
41510  *
41511  */
41512 /*
41513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
41514  *
41515  * Byte is unmasked (i.e. is compared)
41516  */
41517 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED 0x0
41518 /*
41519  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
41520  *
41521  * Byte is masked (i.e. not compared)
41522  */
41523 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED 0x1
41524 
41525 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
41526 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_LSB 25
41527 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
41528 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_MSB 25
41529 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
41530 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_WIDTH 1
41531 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
41532 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET_MSK 0x02000000
41533 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
41534 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_CLR_MSK 0xfdffffff
41535 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
41536 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_RESET 0x0
41537 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 field value from a register. */
41538 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
41539 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value suitable for setting the register. */
41540 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
41541 
41542 /*
41543  * Field : Mask Byte Control - mbc_2
41544  *
41545  * This array of bits are mask control bits for comparison of each of the MAC
41546  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41547  * received DA or SA with the contents of MAC Address29 high and low registers.
41548  * Each bit controls the masking of the bytes. You can filter a group of addresses
41549  * (known as group address filtering) by masking one or more bytes of the address.
41550  *
41551  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41552  *
41553  * Field Enumeration Values:
41554  *
41555  * Enum | Value | Description
41556  * :----------------------------------------------|:------|:------------------------------------
41557  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41558  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41559  *
41560  * Field Access Macros:
41561  *
41562  */
41563 /*
41564  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
41565  *
41566  * Byte is unmasked (i.e. is compared)
41567  */
41568 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED 0x0
41569 /*
41570  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
41571  *
41572  * Byte is masked (i.e. not compared)
41573  */
41574 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED 0x1
41575 
41576 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
41577 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_LSB 26
41578 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
41579 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_MSB 26
41580 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
41581 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_WIDTH 1
41582 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
41583 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET_MSK 0x04000000
41584 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
41585 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_CLR_MSK 0xfbffffff
41586 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
41587 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_RESET 0x0
41588 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 field value from a register. */
41589 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
41590 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value suitable for setting the register. */
41591 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
41592 
41593 /*
41594  * Field : Mask Byte Control - mbc_3
41595  *
41596  * This array of bits are mask control bits for comparison of each of the MAC
41597  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41598  * received DA or SA with the contents of MAC Address29 high and low registers.
41599  * Each bit controls the masking of the bytes. You can filter a group of addresses
41600  * (known as group address filtering) by masking one or more bytes of the address.
41601  *
41602  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41603  *
41604  * Field Enumeration Values:
41605  *
41606  * Enum | Value | Description
41607  * :----------------------------------------------|:------|:------------------------------------
41608  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41609  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41610  *
41611  * Field Access Macros:
41612  *
41613  */
41614 /*
41615  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
41616  *
41617  * Byte is unmasked (i.e. is compared)
41618  */
41619 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED 0x0
41620 /*
41621  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
41622  *
41623  * Byte is masked (i.e. not compared)
41624  */
41625 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED 0x1
41626 
41627 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
41628 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_LSB 27
41629 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
41630 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_MSB 27
41631 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
41632 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_WIDTH 1
41633 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
41634 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET_MSK 0x08000000
41635 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
41636 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_CLR_MSK 0xf7ffffff
41637 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
41638 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_RESET 0x0
41639 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 field value from a register. */
41640 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
41641 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value suitable for setting the register. */
41642 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
41643 
41644 /*
41645  * Field : Mask Byte Control - mbc_4
41646  *
41647  * This array of bits are mask control bits for comparison of each of the MAC
41648  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41649  * received DA or SA with the contents of MAC Address29 high and low registers.
41650  * Each bit controls the masking of the bytes. You can filter a group of addresses
41651  * (known as group address filtering) by masking one or more bytes of the address.
41652  *
41653  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41654  *
41655  * Field Enumeration Values:
41656  *
41657  * Enum | Value | Description
41658  * :----------------------------------------------|:------|:------------------------------------
41659  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41660  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41661  *
41662  * Field Access Macros:
41663  *
41664  */
41665 /*
41666  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
41667  *
41668  * Byte is unmasked (i.e. is compared)
41669  */
41670 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED 0x0
41671 /*
41672  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
41673  *
41674  * Byte is masked (i.e. not compared)
41675  */
41676 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED 0x1
41677 
41678 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
41679 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_LSB 28
41680 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
41681 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_MSB 28
41682 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
41683 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_WIDTH 1
41684 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
41685 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET_MSK 0x10000000
41686 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
41687 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_CLR_MSK 0xefffffff
41688 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
41689 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_RESET 0x0
41690 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 field value from a register. */
41691 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
41692 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value suitable for setting the register. */
41693 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
41694 
41695 /*
41696  * Field : Mask Byte Control - mbc_5
41697  *
41698  * This array of bits are mask control bits for comparison of each of the MAC
41699  * Address bytes. When masked, the MAC does not compare the corresponding byte of
41700  * received DA or SA with the contents of MAC Address29 high and low registers.
41701  * Each bit controls the masking of the bytes. You can filter a group of addresses
41702  * (known as group address filtering) by masking one or more bytes of the address.
41703  *
41704  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
41705  *
41706  * Field Enumeration Values:
41707  *
41708  * Enum | Value | Description
41709  * :----------------------------------------------|:------|:------------------------------------
41710  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
41711  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
41712  *
41713  * Field Access Macros:
41714  *
41715  */
41716 /*
41717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
41718  *
41719  * Byte is unmasked (i.e. is compared)
41720  */
41721 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED 0x0
41722 /*
41723  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
41724  *
41725  * Byte is masked (i.e. not compared)
41726  */
41727 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED 0x1
41728 
41729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
41730 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_LSB 29
41731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
41732 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_MSB 29
41733 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
41734 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_WIDTH 1
41735 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
41736 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET_MSK 0x20000000
41737 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
41738 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_CLR_MSK 0xdfffffff
41739 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
41740 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_RESET 0x0
41741 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 field value from a register. */
41742 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
41743 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value suitable for setting the register. */
41744 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
41745 
41746 /*
41747  * Field : Source Address - sa
41748  *
41749  * When this bit is enabled, the MAC Address29[47:0] is used to compare with the SA
41750  * fields of the received frame. When this bit is disabled, the MAC Address29[47:0]
41751  * is used to compare with the DA fields of the received frame.
41752  *
41753  * Field Enumeration Values:
41754  *
41755  * Enum | Value | Description
41756  * :----------------------------------------|:------|:-----------------------------
41757  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
41758  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END | 0x1 | MAC address compare enabled
41759  *
41760  * Field Access Macros:
41761  *
41762  */
41763 /*
41764  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
41765  *
41766  * MAC address compare disabled
41767  */
41768 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD 0x0
41769 /*
41770  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
41771  *
41772  * MAC address compare enabled
41773  */
41774 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END 0x1
41775 
41776 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
41777 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_LSB 30
41778 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
41779 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_MSB 30
41780 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
41781 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_WIDTH 1
41782 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
41783 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET_MSK 0x40000000
41784 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
41785 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_CLR_MSK 0xbfffffff
41786 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
41787 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_RESET 0x0
41788 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA field value from a register. */
41789 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
41790 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value suitable for setting the register. */
41791 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
41792 
41793 /*
41794  * Field : Address Enable - ae
41795  *
41796  * When this bit is enabled, the address filter block uses the 30th MAC address for
41797  * perfect filtering. When this bit is disabled, the address filter block ignores
41798  * the address for filtering.
41799  *
41800  * Field Enumeration Values:
41801  *
41802  * Enum | Value | Description
41803  * :----------------------------------------|:------|:--------------------------------------
41804  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
41805  * ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
41806  *
41807  * Field Access Macros:
41808  *
41809  */
41810 /*
41811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
41812  *
41813  * Second MAC address filtering disabled
41814  */
41815 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD 0x0
41816 /*
41817  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
41818  *
41819  * Second MAC address filtering enabled
41820  */
41821 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END 0x1
41822 
41823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
41824 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_LSB 31
41825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
41826 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_MSB 31
41827 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
41828 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_WIDTH 1
41829 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
41830 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET_MSK 0x80000000
41831 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
41832 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_CLR_MSK 0x7fffffff
41833 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
41834 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_RESET 0x0
41835 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE field value from a register. */
41836 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
41837 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value suitable for setting the register. */
41838 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
41839 
41840 #ifndef __ASSEMBLY__
41841 /*
41842  * WARNING: The C register and register group struct declarations are provided for
41843  * convenience and illustrative purposes. They should, however, be used with
41844  * caution as the C language standard provides no guarantees about the alignment or
41845  * atomicity of device memory accesses. The recommended practice for writing
41846  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41847  * alt_write_word() functions.
41848  *
41849  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH.
41850  */
41851 struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s
41852 {
41853  uint32_t addrhi : 16; /* MAC Address29 [47:32] */
41854  uint32_t : 8; /* *UNDEFINED* */
41855  uint32_t mbc_0 : 1; /* Mask Byte Control */
41856  uint32_t mbc_1 : 1; /* Mask Byte Control */
41857  uint32_t mbc_2 : 1; /* Mask Byte Control */
41858  uint32_t mbc_3 : 1; /* Mask Byte Control */
41859  uint32_t mbc_4 : 1; /* Mask Byte Control */
41860  uint32_t mbc_5 : 1; /* Mask Byte Control */
41861  uint32_t sa : 1; /* Source Address */
41862  uint32_t ae : 1; /* Address Enable */
41863 };
41864 
41865 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH. */
41866 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t;
41867 #endif /* __ASSEMBLY__ */
41868 
41869 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register from the beginning of the component. */
41870 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST 0x868
41871 /* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register. */
41872 #define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST))
41873 
41874 /*
41875  * Register : Register 539 (MAC Address29 Low Register) - MAC_Address29_Low
41876  *
41877  * The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC
41878  * address of the station.
41879  *
41880  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
41881  * format.
41882  *
41883  * Register Layout
41884  *
41885  * Bits | Access | Reset | Description
41886  * :-------|:-------|:-----------|:---------------------
41887  * [31:0] | RW | 0xffffffff | MAC Address29 [31:0]
41888  *
41889  */
41890 /*
41891  * Field : MAC Address29 [31:0] - addrlo
41892  *
41893  * This field contains the lower 32 bits of the 30th 6-byte MAC address. The
41894  * content of this field is undefined until loaded by software after the
41895  * initialization process.
41896  *
41897  * Field Access Macros:
41898  *
41899  */
41900 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
41901 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_LSB 0
41902 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
41903 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_MSB 31
41904 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
41905 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_WIDTH 32
41906 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
41907 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET_MSK 0xffffffff
41908 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
41909 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_CLR_MSK 0x00000000
41910 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
41911 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_RESET 0xffffffff
41912 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO field value from a register. */
41913 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
41914 /* Produces a ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value suitable for setting the register. */
41915 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
41916 
41917 #ifndef __ASSEMBLY__
41918 /*
41919  * WARNING: The C register and register group struct declarations are provided for
41920  * convenience and illustrative purposes. They should, however, be used with
41921  * caution as the C language standard provides no guarantees about the alignment or
41922  * atomicity of device memory accesses. The recommended practice for writing
41923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
41924  * alt_write_word() functions.
41925  *
41926  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW.
41927  */
41928 struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s
41929 {
41930  uint32_t addrlo : 32; /* MAC Address29 [31:0] */
41931 };
41932 
41933 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW. */
41934 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s ALT_EMAC_GMAC_MAC_ADDR29_LOW_t;
41935 #endif /* __ASSEMBLY__ */
41936 
41937 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register from the beginning of the component. */
41938 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST 0x86c
41939 /* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register. */
41940 #define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST))
41941 
41942 /*
41943  * Register : Register 540 (MAC Address30 High Register) - MAC_Address30_High
41944  *
41945  * The MAC Address30 High register holds the upper 16 bits of the 31th 6-byte MAC
41946  * address of the station. Because the MAC address registers are configured to be
41947  * double-synchronized to the (G)MII clock domains, the synchronization is
41948  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
41949  * endian mode) of the MAC Address30 Low Register are written. For proper
41950  * synchronization updates, the consecutive writes to this Address Low Register
41951  * should be performed after at least four clock cycles in the destination clock
41952  * domain.
41953  *
41954  * Note that all MAC Address High registers (except MAC Address0 High) have the
41955  * same format.
41956  *
41957  * Register Layout
41958  *
41959  * Bits | Access | Reset | Description
41960  * :--------|:-------|:-------|:----------------------
41961  * [15:0] | RW | 0xffff | MAC Address30 [47:32]
41962  * [23:16] | ??? | 0x0 | *UNDEFINED*
41963  * [24] | RW | 0x0 | Mask Byte Control
41964  * [25] | RW | 0x0 | Mask Byte Control
41965  * [26] | RW | 0x0 | Mask Byte Control
41966  * [27] | RW | 0x0 | Mask Byte Control
41967  * [28] | RW | 0x0 | Mask Byte Control
41968  * [29] | RW | 0x0 | Mask Byte Control
41969  * [30] | RW | 0x0 | Source Address
41970  * [31] | RW | 0x0 | Address Enable
41971  *
41972  */
41973 /*
41974  * Field : MAC Address30 [47:32] - addrhi
41975  *
41976  * This field contains the upper 16 bits (47:32) of the 31th 6-byte MAC address.
41977  *
41978  * Field Access Macros:
41979  *
41980  */
41981 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
41982 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_LSB 0
41983 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
41984 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_MSB 15
41985 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
41986 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_WIDTH 16
41987 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
41988 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET_MSK 0x0000ffff
41989 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
41990 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_CLR_MSK 0xffff0000
41991 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
41992 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_RESET 0xffff
41993 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI field value from a register. */
41994 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
41995 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value suitable for setting the register. */
41996 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
41997 
41998 /*
41999  * Field : Mask Byte Control - mbc_0
42000  *
42001  * This array of bits are mask control bits for comparison of each of the MAC
42002  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42003  * received DA or SA with the contents of MAC Address30 high and low registers.
42004  * Each bit controls the masking of the bytes. You can filter a group of addresses
42005  * (known as group address filtering) by masking one or more bytes of the address.
42006  *
42007  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42008  *
42009  * Field Enumeration Values:
42010  *
42011  * Enum | Value | Description
42012  * :----------------------------------------------|:------|:------------------------------------
42013  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42014  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42015  *
42016  * Field Access Macros:
42017  *
42018  */
42019 /*
42020  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
42021  *
42022  * Byte is unmasked (i.e. is compared)
42023  */
42024 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED 0x0
42025 /*
42026  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
42027  *
42028  * Byte is masked (i.e. not compared)
42029  */
42030 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED 0x1
42031 
42032 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
42033 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_LSB 24
42034 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
42035 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_MSB 24
42036 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
42037 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_WIDTH 1
42038 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
42039 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET_MSK 0x01000000
42040 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
42041 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_CLR_MSK 0xfeffffff
42042 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
42043 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_RESET 0x0
42044 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 field value from a register. */
42045 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
42046 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value suitable for setting the register. */
42047 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
42048 
42049 /*
42050  * Field : Mask Byte Control - mbc_1
42051  *
42052  * This array of bits are mask control bits for comparison of each of the MAC
42053  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42054  * received DA or SA with the contents of MAC Address30 high and low registers.
42055  * Each bit controls the masking of the bytes. You can filter a group of addresses
42056  * (known as group address filtering) by masking one or more bytes of the address.
42057  *
42058  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42059  *
42060  * Field Enumeration Values:
42061  *
42062  * Enum | Value | Description
42063  * :----------------------------------------------|:------|:------------------------------------
42064  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42065  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42066  *
42067  * Field Access Macros:
42068  *
42069  */
42070 /*
42071  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
42072  *
42073  * Byte is unmasked (i.e. is compared)
42074  */
42075 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED 0x0
42076 /*
42077  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
42078  *
42079  * Byte is masked (i.e. not compared)
42080  */
42081 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED 0x1
42082 
42083 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
42084 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_LSB 25
42085 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
42086 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_MSB 25
42087 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
42088 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_WIDTH 1
42089 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
42090 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET_MSK 0x02000000
42091 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
42092 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_CLR_MSK 0xfdffffff
42093 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
42094 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_RESET 0x0
42095 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 field value from a register. */
42096 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
42097 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value suitable for setting the register. */
42098 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
42099 
42100 /*
42101  * Field : Mask Byte Control - mbc_2
42102  *
42103  * This array of bits are mask control bits for comparison of each of the MAC
42104  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42105  * received DA or SA with the contents of MAC Address30 high and low registers.
42106  * Each bit controls the masking of the bytes. You can filter a group of addresses
42107  * (known as group address filtering) by masking one or more bytes of the address.
42108  *
42109  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42110  *
42111  * Field Enumeration Values:
42112  *
42113  * Enum | Value | Description
42114  * :----------------------------------------------|:------|:------------------------------------
42115  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42116  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42117  *
42118  * Field Access Macros:
42119  *
42120  */
42121 /*
42122  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
42123  *
42124  * Byte is unmasked (i.e. is compared)
42125  */
42126 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED 0x0
42127 /*
42128  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
42129  *
42130  * Byte is masked (i.e. not compared)
42131  */
42132 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED 0x1
42133 
42134 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
42135 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_LSB 26
42136 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
42137 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_MSB 26
42138 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
42139 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_WIDTH 1
42140 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
42141 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET_MSK 0x04000000
42142 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
42143 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_CLR_MSK 0xfbffffff
42144 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
42145 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_RESET 0x0
42146 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 field value from a register. */
42147 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
42148 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value suitable for setting the register. */
42149 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
42150 
42151 /*
42152  * Field : Mask Byte Control - mbc_3
42153  *
42154  * This array of bits are mask control bits for comparison of each of the MAC
42155  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42156  * received DA or SA with the contents of MAC Address30 high and low registers.
42157  * Each bit controls the masking of the bytes. You can filter a group of addresses
42158  * (known as group address filtering) by masking one or more bytes of the address.
42159  *
42160  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42161  *
42162  * Field Enumeration Values:
42163  *
42164  * Enum | Value | Description
42165  * :----------------------------------------------|:------|:------------------------------------
42166  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42167  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42168  *
42169  * Field Access Macros:
42170  *
42171  */
42172 /*
42173  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
42174  *
42175  * Byte is unmasked (i.e. is compared)
42176  */
42177 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED 0x0
42178 /*
42179  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
42180  *
42181  * Byte is masked (i.e. not compared)
42182  */
42183 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED 0x1
42184 
42185 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
42186 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_LSB 27
42187 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
42188 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_MSB 27
42189 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
42190 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_WIDTH 1
42191 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
42192 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET_MSK 0x08000000
42193 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
42194 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_CLR_MSK 0xf7ffffff
42195 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
42196 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_RESET 0x0
42197 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 field value from a register. */
42198 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
42199 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value suitable for setting the register. */
42200 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
42201 
42202 /*
42203  * Field : Mask Byte Control - mbc_4
42204  *
42205  * This array of bits are mask control bits for comparison of each of the MAC
42206  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42207  * received DA or SA with the contents of MAC Address30 high and low registers.
42208  * Each bit controls the masking of the bytes. You can filter a group of addresses
42209  * (known as group address filtering) by masking one or more bytes of the address.
42210  *
42211  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42212  *
42213  * Field Enumeration Values:
42214  *
42215  * Enum | Value | Description
42216  * :----------------------------------------------|:------|:------------------------------------
42217  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42218  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42219  *
42220  * Field Access Macros:
42221  *
42222  */
42223 /*
42224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
42225  *
42226  * Byte is unmasked (i.e. is compared)
42227  */
42228 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED 0x0
42229 /*
42230  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
42231  *
42232  * Byte is masked (i.e. not compared)
42233  */
42234 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED 0x1
42235 
42236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
42237 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_LSB 28
42238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
42239 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_MSB 28
42240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
42241 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_WIDTH 1
42242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
42243 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET_MSK 0x10000000
42244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
42245 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_CLR_MSK 0xefffffff
42246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
42247 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_RESET 0x0
42248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 field value from a register. */
42249 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
42250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value suitable for setting the register. */
42251 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
42252 
42253 /*
42254  * Field : Mask Byte Control - mbc_5
42255  *
42256  * This array of bits are mask control bits for comparison of each of the MAC
42257  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42258  * received DA or SA with the contents of MAC Address30 high and low registers.
42259  * Each bit controls the masking of the bytes. You can filter a group of addresses
42260  * (known as group address filtering) by masking one or more bytes of the address.
42261  *
42262  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42263  *
42264  * Field Enumeration Values:
42265  *
42266  * Enum | Value | Description
42267  * :----------------------------------------------|:------|:------------------------------------
42268  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42269  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42270  *
42271  * Field Access Macros:
42272  *
42273  */
42274 /*
42275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
42276  *
42277  * Byte is unmasked (i.e. is compared)
42278  */
42279 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED 0x0
42280 /*
42281  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
42282  *
42283  * Byte is masked (i.e. not compared)
42284  */
42285 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED 0x1
42286 
42287 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
42288 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_LSB 29
42289 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
42290 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_MSB 29
42291 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
42292 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_WIDTH 1
42293 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
42294 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET_MSK 0x20000000
42295 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
42296 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_CLR_MSK 0xdfffffff
42297 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
42298 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_RESET 0x0
42299 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 field value from a register. */
42300 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
42301 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value suitable for setting the register. */
42302 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
42303 
42304 /*
42305  * Field : Source Address - sa
42306  *
42307  * When this bit is enabled, the MAC Address30[47:0] is used to compare with the SA
42308  * fields of the received frame. When this bit is disabled, the MAC Address30[47:0]
42309  * is used to compare with the DA fields of the received frame.
42310  *
42311  * Field Enumeration Values:
42312  *
42313  * Enum | Value | Description
42314  * :----------------------------------------|:------|:-----------------------------
42315  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
42316  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END | 0x1 | MAC address compare enabled
42317  *
42318  * Field Access Macros:
42319  *
42320  */
42321 /*
42322  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
42323  *
42324  * MAC address compare disabled
42325  */
42326 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD 0x0
42327 /*
42328  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
42329  *
42330  * MAC address compare enabled
42331  */
42332 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END 0x1
42333 
42334 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
42335 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_LSB 30
42336 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
42337 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_MSB 30
42338 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
42339 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_WIDTH 1
42340 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
42341 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET_MSK 0x40000000
42342 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
42343 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_CLR_MSK 0xbfffffff
42344 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
42345 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_RESET 0x0
42346 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA field value from a register. */
42347 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
42348 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value suitable for setting the register. */
42349 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
42350 
42351 /*
42352  * Field : Address Enable - ae
42353  *
42354  * When this bit is enabled, the address filter block uses the 31th MAC address for
42355  * perfect filtering. When this bit is disabled, the address filter block ignores
42356  * the address for filtering.
42357  *
42358  * Field Enumeration Values:
42359  *
42360  * Enum | Value | Description
42361  * :----------------------------------------|:------|:--------------------------------------
42362  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
42363  * ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
42364  *
42365  * Field Access Macros:
42366  *
42367  */
42368 /*
42369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
42370  *
42371  * Second MAC address filtering disabled
42372  */
42373 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD 0x0
42374 /*
42375  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
42376  *
42377  * Second MAC address filtering enabled
42378  */
42379 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END 0x1
42380 
42381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
42382 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_LSB 31
42383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
42384 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_MSB 31
42385 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
42386 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_WIDTH 1
42387 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
42388 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET_MSK 0x80000000
42389 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
42390 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_CLR_MSK 0x7fffffff
42391 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
42392 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_RESET 0x0
42393 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE field value from a register. */
42394 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
42395 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value suitable for setting the register. */
42396 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
42397 
42398 #ifndef __ASSEMBLY__
42399 /*
42400  * WARNING: The C register and register group struct declarations are provided for
42401  * convenience and illustrative purposes. They should, however, be used with
42402  * caution as the C language standard provides no guarantees about the alignment or
42403  * atomicity of device memory accesses. The recommended practice for writing
42404  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42405  * alt_write_word() functions.
42406  *
42407  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH.
42408  */
42409 struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s
42410 {
42411  uint32_t addrhi : 16; /* MAC Address30 [47:32] */
42412  uint32_t : 8; /* *UNDEFINED* */
42413  uint32_t mbc_0 : 1; /* Mask Byte Control */
42414  uint32_t mbc_1 : 1; /* Mask Byte Control */
42415  uint32_t mbc_2 : 1; /* Mask Byte Control */
42416  uint32_t mbc_3 : 1; /* Mask Byte Control */
42417  uint32_t mbc_4 : 1; /* Mask Byte Control */
42418  uint32_t mbc_5 : 1; /* Mask Byte Control */
42419  uint32_t sa : 1; /* Source Address */
42420  uint32_t ae : 1; /* Address Enable */
42421 };
42422 
42423 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH. */
42424 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t;
42425 #endif /* __ASSEMBLY__ */
42426 
42427 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register from the beginning of the component. */
42428 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST 0x870
42429 /* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register. */
42430 #define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST))
42431 
42432 /*
42433  * Register : Register 541 (MAC Address30 Low Register) - MAC_Address30_Low
42434  *
42435  * The MAC Address30 Low register holds the lower 32 bits of the 31th 6-byte MAC
42436  * address of the station.
42437  *
42438  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
42439  * format.
42440  *
42441  * Register Layout
42442  *
42443  * Bits | Access | Reset | Description
42444  * :-------|:-------|:-----------|:---------------------
42445  * [31:0] | RW | 0xffffffff | MAC Address30 [31:0]
42446  *
42447  */
42448 /*
42449  * Field : MAC Address30 [31:0] - addrlo
42450  *
42451  * This field contains the lower 32 bits of the 31th 6-byte MAC address. The
42452  * content of this field is undefined until loaded by software after the
42453  * initialization process.
42454  *
42455  * Field Access Macros:
42456  *
42457  */
42458 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
42459 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_LSB 0
42460 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
42461 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_MSB 31
42462 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
42463 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_WIDTH 32
42464 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
42465 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET_MSK 0xffffffff
42466 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
42467 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_CLR_MSK 0x00000000
42468 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
42469 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_RESET 0xffffffff
42470 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO field value from a register. */
42471 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
42472 /* Produces a ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value suitable for setting the register. */
42473 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
42474 
42475 #ifndef __ASSEMBLY__
42476 /*
42477  * WARNING: The C register and register group struct declarations are provided for
42478  * convenience and illustrative purposes. They should, however, be used with
42479  * caution as the C language standard provides no guarantees about the alignment or
42480  * atomicity of device memory accesses. The recommended practice for writing
42481  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42482  * alt_write_word() functions.
42483  *
42484  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW.
42485  */
42486 struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s
42487 {
42488  uint32_t addrlo : 32; /* MAC Address30 [31:0] */
42489 };
42490 
42491 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW. */
42492 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s ALT_EMAC_GMAC_MAC_ADDR30_LOW_t;
42493 #endif /* __ASSEMBLY__ */
42494 
42495 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register from the beginning of the component. */
42496 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST 0x874
42497 /* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register. */
42498 #define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST))
42499 
42500 /*
42501  * Register : Register 542 (MAC Address31 High Register) - MAC_Address31_High
42502  *
42503  * The MAC Address31 High register holds the upper 16 bits of the 32th 6-byte MAC
42504  * address of the station. Because the MAC address registers are configured to be
42505  * double-synchronized to the (G)MII clock domains, the synchronization is
42506  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
42507  * endian mode) of the MAC Address31 Low Register are written. For proper
42508  * synchronization updates, the consecutive writes to this Address Low Register
42509  * should be performed after at least four clock cycles in the destination clock
42510  * domain.
42511  *
42512  * Note that all MAC Address High registers (except MAC Address0 High) have the
42513  * same format.
42514  *
42515  * Register Layout
42516  *
42517  * Bits | Access | Reset | Description
42518  * :--------|:-------|:-------|:----------------------
42519  * [15:0] | RW | 0xffff | MAC Address31 [47:32]
42520  * [23:16] | ??? | 0x0 | *UNDEFINED*
42521  * [24] | RW | 0x0 | Mask Byte Control
42522  * [25] | RW | 0x0 | Mask Byte Control
42523  * [26] | RW | 0x0 | Mask Byte Control
42524  * [27] | RW | 0x0 | Mask Byte Control
42525  * [28] | RW | 0x0 | Mask Byte Control
42526  * [29] | RW | 0x0 | Mask Byte Control
42527  * [30] | RW | 0x0 | Source Address
42528  * [31] | RW | 0x0 | Address Enable
42529  *
42530  */
42531 /*
42532  * Field : MAC Address31 [47:32] - addrhi
42533  *
42534  * This field contains the upper 16 bits (47:32) of the 32th 6-byte MAC address.
42535  *
42536  * Field Access Macros:
42537  *
42538  */
42539 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
42540 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_LSB 0
42541 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
42542 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_MSB 15
42543 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
42544 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_WIDTH 16
42545 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
42546 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET_MSK 0x0000ffff
42547 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
42548 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_CLR_MSK 0xffff0000
42549 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
42550 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_RESET 0xffff
42551 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI field value from a register. */
42552 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
42553 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value suitable for setting the register. */
42554 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
42555 
42556 /*
42557  * Field : Mask Byte Control - mbc_0
42558  *
42559  * This array of bits are mask control bits for comparison of each of the MAC
42560  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42561  * received DA or SA with the contents of MAC Address31 high and low registers.
42562  * Each bit controls the masking of the bytes. You can filter a group of addresses
42563  * (known as group address filtering) by masking one or more bytes of the address.
42564  *
42565  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42566  *
42567  * Field Enumeration Values:
42568  *
42569  * Enum | Value | Description
42570  * :----------------------------------------------|:------|:------------------------------------
42571  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42572  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42573  *
42574  * Field Access Macros:
42575  *
42576  */
42577 /*
42578  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
42579  *
42580  * Byte is unmasked (i.e. is compared)
42581  */
42582 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED 0x0
42583 /*
42584  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
42585  *
42586  * Byte is masked (i.e. not compared)
42587  */
42588 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED 0x1
42589 
42590 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
42591 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_LSB 24
42592 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
42593 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_MSB 24
42594 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
42595 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_WIDTH 1
42596 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
42597 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET_MSK 0x01000000
42598 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
42599 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_CLR_MSK 0xfeffffff
42600 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
42601 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_RESET 0x0
42602 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 field value from a register. */
42603 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
42604 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value suitable for setting the register. */
42605 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
42606 
42607 /*
42608  * Field : Mask Byte Control - mbc_1
42609  *
42610  * This array of bits are mask control bits for comparison of each of the MAC
42611  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42612  * received DA or SA with the contents of MAC Address31 high and low registers.
42613  * Each bit controls the masking of the bytes. You can filter a group of addresses
42614  * (known as group address filtering) by masking one or more bytes of the address.
42615  *
42616  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42617  *
42618  * Field Enumeration Values:
42619  *
42620  * Enum | Value | Description
42621  * :----------------------------------------------|:------|:------------------------------------
42622  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42623  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42624  *
42625  * Field Access Macros:
42626  *
42627  */
42628 /*
42629  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
42630  *
42631  * Byte is unmasked (i.e. is compared)
42632  */
42633 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED 0x0
42634 /*
42635  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
42636  *
42637  * Byte is masked (i.e. not compared)
42638  */
42639 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED 0x1
42640 
42641 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
42642 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_LSB 25
42643 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
42644 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_MSB 25
42645 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
42646 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_WIDTH 1
42647 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
42648 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET_MSK 0x02000000
42649 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
42650 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_CLR_MSK 0xfdffffff
42651 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
42652 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_RESET 0x0
42653 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 field value from a register. */
42654 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
42655 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value suitable for setting the register. */
42656 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
42657 
42658 /*
42659  * Field : Mask Byte Control - mbc_2
42660  *
42661  * This array of bits are mask control bits for comparison of each of the MAC
42662  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42663  * received DA or SA with the contents of MAC Address31 high and low registers.
42664  * Each bit controls the masking of the bytes. You can filter a group of addresses
42665  * (known as group address filtering) by masking one or more bytes of the address.
42666  *
42667  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42668  *
42669  * Field Enumeration Values:
42670  *
42671  * Enum | Value | Description
42672  * :----------------------------------------------|:------|:------------------------------------
42673  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42674  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42675  *
42676  * Field Access Macros:
42677  *
42678  */
42679 /*
42680  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
42681  *
42682  * Byte is unmasked (i.e. is compared)
42683  */
42684 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED 0x0
42685 /*
42686  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
42687  *
42688  * Byte is masked (i.e. not compared)
42689  */
42690 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED 0x1
42691 
42692 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
42693 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_LSB 26
42694 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
42695 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_MSB 26
42696 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
42697 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_WIDTH 1
42698 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
42699 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET_MSK 0x04000000
42700 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
42701 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_CLR_MSK 0xfbffffff
42702 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
42703 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_RESET 0x0
42704 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 field value from a register. */
42705 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
42706 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value suitable for setting the register. */
42707 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
42708 
42709 /*
42710  * Field : Mask Byte Control - mbc_3
42711  *
42712  * This array of bits are mask control bits for comparison of each of the MAC
42713  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42714  * received DA or SA with the contents of MAC Address31 high and low registers.
42715  * Each bit controls the masking of the bytes. You can filter a group of addresses
42716  * (known as group address filtering) by masking one or more bytes of the address.
42717  *
42718  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42719  *
42720  * Field Enumeration Values:
42721  *
42722  * Enum | Value | Description
42723  * :----------------------------------------------|:------|:------------------------------------
42724  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42725  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42726  *
42727  * Field Access Macros:
42728  *
42729  */
42730 /*
42731  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
42732  *
42733  * Byte is unmasked (i.e. is compared)
42734  */
42735 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED 0x0
42736 /*
42737  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
42738  *
42739  * Byte is masked (i.e. not compared)
42740  */
42741 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED 0x1
42742 
42743 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
42744 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_LSB 27
42745 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
42746 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_MSB 27
42747 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
42748 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_WIDTH 1
42749 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
42750 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET_MSK 0x08000000
42751 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
42752 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_CLR_MSK 0xf7ffffff
42753 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
42754 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_RESET 0x0
42755 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 field value from a register. */
42756 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
42757 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value suitable for setting the register. */
42758 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
42759 
42760 /*
42761  * Field : Mask Byte Control - mbc_4
42762  *
42763  * This array of bits are mask control bits for comparison of each of the MAC
42764  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42765  * received DA or SA with the contents of MAC Address31 high and low registers.
42766  * Each bit controls the masking of the bytes. You can filter a group of addresses
42767  * (known as group address filtering) by masking one or more bytes of the address.
42768  *
42769  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42770  *
42771  * Field Enumeration Values:
42772  *
42773  * Enum | Value | Description
42774  * :----------------------------------------------|:------|:------------------------------------
42775  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42776  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42777  *
42778  * Field Access Macros:
42779  *
42780  */
42781 /*
42782  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
42783  *
42784  * Byte is unmasked (i.e. is compared)
42785  */
42786 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED 0x0
42787 /*
42788  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
42789  *
42790  * Byte is masked (i.e. not compared)
42791  */
42792 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED 0x1
42793 
42794 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
42795 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_LSB 28
42796 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
42797 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_MSB 28
42798 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
42799 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_WIDTH 1
42800 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
42801 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET_MSK 0x10000000
42802 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
42803 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_CLR_MSK 0xefffffff
42804 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
42805 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_RESET 0x0
42806 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 field value from a register. */
42807 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
42808 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value suitable for setting the register. */
42809 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
42810 
42811 /*
42812  * Field : Mask Byte Control - mbc_5
42813  *
42814  * This array of bits are mask control bits for comparison of each of the MAC
42815  * Address bytes. When masked, the MAC does not compare the corresponding byte of
42816  * received DA or SA with the contents of MAC Address31 high and low registers.
42817  * Each bit controls the masking of the bytes. You can filter a group of addresses
42818  * (known as group address filtering) by masking one or more bytes of the address.
42819  *
42820  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
42821  *
42822  * Field Enumeration Values:
42823  *
42824  * Enum | Value | Description
42825  * :----------------------------------------------|:------|:------------------------------------
42826  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
42827  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
42828  *
42829  * Field Access Macros:
42830  *
42831  */
42832 /*
42833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
42834  *
42835  * Byte is unmasked (i.e. is compared)
42836  */
42837 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED 0x0
42838 /*
42839  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
42840  *
42841  * Byte is masked (i.e. not compared)
42842  */
42843 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED 0x1
42844 
42845 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
42846 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_LSB 29
42847 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
42848 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_MSB 29
42849 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
42850 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_WIDTH 1
42851 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
42852 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET_MSK 0x20000000
42853 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
42854 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_CLR_MSK 0xdfffffff
42855 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
42856 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_RESET 0x0
42857 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 field value from a register. */
42858 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
42859 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value suitable for setting the register. */
42860 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
42861 
42862 /*
42863  * Field : Source Address - sa
42864  *
42865  * When this bit is enabled, the MAC Address31[47:0] is used to compare with the SA
42866  * fields of the received frame. When this bit is disabled, the MAC Address31[47:0]
42867  * is used to compare with the DA fields of the received frame.
42868  *
42869  * Field Enumeration Values:
42870  *
42871  * Enum | Value | Description
42872  * :----------------------------------------|:------|:-----------------------------
42873  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
42874  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END | 0x1 | MAC address compare enabled
42875  *
42876  * Field Access Macros:
42877  *
42878  */
42879 /*
42880  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
42881  *
42882  * MAC address compare disabled
42883  */
42884 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD 0x0
42885 /*
42886  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
42887  *
42888  * MAC address compare enabled
42889  */
42890 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END 0x1
42891 
42892 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
42893 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_LSB 30
42894 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
42895 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_MSB 30
42896 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
42897 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_WIDTH 1
42898 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
42899 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET_MSK 0x40000000
42900 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
42901 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_CLR_MSK 0xbfffffff
42902 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
42903 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_RESET 0x0
42904 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA field value from a register. */
42905 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
42906 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value suitable for setting the register. */
42907 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
42908 
42909 /*
42910  * Field : Address Enable - ae
42911  *
42912  * When this bit is enabled, the address filter block uses the 32th MAC address for
42913  * perfect filtering. When this bit is disabled, the address filter block ignores
42914  * the address for filtering.
42915  *
42916  * Field Enumeration Values:
42917  *
42918  * Enum | Value | Description
42919  * :----------------------------------------|:------|:--------------------------------------
42920  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
42921  * ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
42922  *
42923  * Field Access Macros:
42924  *
42925  */
42926 /*
42927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
42928  *
42929  * Second MAC address filtering disabled
42930  */
42931 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD 0x0
42932 /*
42933  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
42934  *
42935  * Second MAC address filtering enabled
42936  */
42937 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END 0x1
42938 
42939 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
42940 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_LSB 31
42941 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
42942 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_MSB 31
42943 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
42944 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_WIDTH 1
42945 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
42946 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET_MSK 0x80000000
42947 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
42948 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_CLR_MSK 0x7fffffff
42949 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
42950 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_RESET 0x0
42951 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE field value from a register. */
42952 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
42953 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value suitable for setting the register. */
42954 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
42955 
42956 #ifndef __ASSEMBLY__
42957 /*
42958  * WARNING: The C register and register group struct declarations are provided for
42959  * convenience and illustrative purposes. They should, however, be used with
42960  * caution as the C language standard provides no guarantees about the alignment or
42961  * atomicity of device memory accesses. The recommended practice for writing
42962  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
42963  * alt_write_word() functions.
42964  *
42965  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH.
42966  */
42967 struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s
42968 {
42969  uint32_t addrhi : 16; /* MAC Address31 [47:32] */
42970  uint32_t : 8; /* *UNDEFINED* */
42971  uint32_t mbc_0 : 1; /* Mask Byte Control */
42972  uint32_t mbc_1 : 1; /* Mask Byte Control */
42973  uint32_t mbc_2 : 1; /* Mask Byte Control */
42974  uint32_t mbc_3 : 1; /* Mask Byte Control */
42975  uint32_t mbc_4 : 1; /* Mask Byte Control */
42976  uint32_t mbc_5 : 1; /* Mask Byte Control */
42977  uint32_t sa : 1; /* Source Address */
42978  uint32_t ae : 1; /* Address Enable */
42979 };
42980 
42981 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH. */
42982 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t;
42983 #endif /* __ASSEMBLY__ */
42984 
42985 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register from the beginning of the component. */
42986 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST 0x878
42987 /* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register. */
42988 #define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST))
42989 
42990 /*
42991  * Register : Register 543 (MAC Address31 Low Register) - MAC_Address31_Low
42992  *
42993  * The MAC Address31 Low register holds the lower 32 bits of the 32th 6-byte MAC
42994  * address of the station.
42995  *
42996  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
42997  * format.
42998  *
42999  * Register Layout
43000  *
43001  * Bits | Access | Reset | Description
43002  * :-------|:-------|:-----------|:---------------------
43003  * [31:0] | RW | 0xffffffff | MAC Address31 [31:0]
43004  *
43005  */
43006 /*
43007  * Field : MAC Address31 [31:0] - addrlo
43008  *
43009  * This field contains the lower 32 bits of the 32th 6-byte MAC address. The
43010  * content of this field is undefined until loaded by software after the
43011  * initialization process.
43012  *
43013  * Field Access Macros:
43014  *
43015  */
43016 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
43017 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_LSB 0
43018 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
43019 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_MSB 31
43020 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
43021 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_WIDTH 32
43022 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
43023 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET_MSK 0xffffffff
43024 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
43025 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_CLR_MSK 0x00000000
43026 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
43027 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_RESET 0xffffffff
43028 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO field value from a register. */
43029 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
43030 /* Produces a ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value suitable for setting the register. */
43031 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
43032 
43033 #ifndef __ASSEMBLY__
43034 /*
43035  * WARNING: The C register and register group struct declarations are provided for
43036  * convenience and illustrative purposes. They should, however, be used with
43037  * caution as the C language standard provides no guarantees about the alignment or
43038  * atomicity of device memory accesses. The recommended practice for writing
43039  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43040  * alt_write_word() functions.
43041  *
43042  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW.
43043  */
43044 struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s
43045 {
43046  uint32_t addrlo : 32; /* MAC Address31 [31:0] */
43047 };
43048 
43049 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW. */
43050 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s ALT_EMAC_GMAC_MAC_ADDR31_LOW_t;
43051 #endif /* __ASSEMBLY__ */
43052 
43053 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register from the beginning of the component. */
43054 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST 0x87c
43055 /* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register. */
43056 #define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST))
43057 
43058 /*
43059  * Register : Register 544 (MAC Address32 High Register) - MAC_Address32_High
43060  *
43061  * The MAC Address32 High register holds the upper 16 bits of the 33th 6-byte MAC
43062  * address of the station. Because the MAC address registers are configured to be
43063  * double-synchronized to the (G)MII clock domains, the synchronization is
43064  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
43065  * endian mode) of the MAC Address32 Low Register are written. For proper
43066  * synchronization updates, the consecutive writes to this Address Low Register
43067  * should be performed after at least four clock cycles in the destination clock
43068  * domain.
43069  *
43070  * Note that all MAC Address High registers (except MAC Address0 High) have the
43071  * same format.
43072  *
43073  * Register Layout
43074  *
43075  * Bits | Access | Reset | Description
43076  * :--------|:-------|:-------|:----------------------
43077  * [15:0] | RW | 0xffff | MAC Address32 [47:32]
43078  * [23:16] | ??? | 0x0 | *UNDEFINED*
43079  * [24] | RW | 0x0 | Mask Byte Control
43080  * [25] | RW | 0x0 | Mask Byte Control
43081  * [26] | RW | 0x0 | Mask Byte Control
43082  * [27] | RW | 0x0 | Mask Byte Control
43083  * [28] | RW | 0x0 | Mask Byte Control
43084  * [29] | RW | 0x0 | Mask Byte Control
43085  * [30] | RW | 0x0 | Source Address
43086  * [31] | RW | 0x0 | Address Enable
43087  *
43088  */
43089 /*
43090  * Field : MAC Address32 [47:32] - addrhi
43091  *
43092  * This field contains the upper 16 bits (47:32) of the 33th 6-byte MAC address.
43093  *
43094  * Field Access Macros:
43095  *
43096  */
43097 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
43098 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_LSB 0
43099 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
43100 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_MSB 15
43101 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
43102 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_WIDTH 16
43103 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
43104 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET_MSK 0x0000ffff
43105 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
43106 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_CLR_MSK 0xffff0000
43107 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
43108 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_RESET 0xffff
43109 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI field value from a register. */
43110 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
43111 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value suitable for setting the register. */
43112 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
43113 
43114 /*
43115  * Field : Mask Byte Control - mbc_0
43116  *
43117  * This array of bits are mask control bits for comparison of each of the MAC
43118  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43119  * received DA or SA with the contents of MAC Address32 high and low registers.
43120  * Each bit controls the masking of the bytes. You can filter a group of addresses
43121  * (known as group address filtering) by masking one or more bytes of the address.
43122  *
43123  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43124  *
43125  * Field Enumeration Values:
43126  *
43127  * Enum | Value | Description
43128  * :----------------------------------------------|:------|:------------------------------------
43129  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43130  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43131  *
43132  * Field Access Macros:
43133  *
43134  */
43135 /*
43136  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0
43137  *
43138  * Byte is unmasked (i.e. is compared)
43139  */
43140 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED 0x0
43141 /*
43142  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0
43143  *
43144  * Byte is masked (i.e. not compared)
43145  */
43146 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED 0x1
43147 
43148 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
43149 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_LSB 24
43150 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
43151 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_MSB 24
43152 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
43153 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_WIDTH 1
43154 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */
43155 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET_MSK 0x01000000
43156 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */
43157 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_CLR_MSK 0xfeffffff
43158 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
43159 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_RESET 0x0
43160 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 field value from a register. */
43161 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
43162 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value suitable for setting the register. */
43163 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
43164 
43165 /*
43166  * Field : Mask Byte Control - mbc_1
43167  *
43168  * This array of bits are mask control bits for comparison of each of the MAC
43169  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43170  * received DA or SA with the contents of MAC Address32 high and low registers.
43171  * Each bit controls the masking of the bytes. You can filter a group of addresses
43172  * (known as group address filtering) by masking one or more bytes of the address.
43173  *
43174  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43175  *
43176  * Field Enumeration Values:
43177  *
43178  * Enum | Value | Description
43179  * :----------------------------------------------|:------|:------------------------------------
43180  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43181  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43182  *
43183  * Field Access Macros:
43184  *
43185  */
43186 /*
43187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1
43188  *
43189  * Byte is unmasked (i.e. is compared)
43190  */
43191 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED 0x0
43192 /*
43193  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1
43194  *
43195  * Byte is masked (i.e. not compared)
43196  */
43197 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED 0x1
43198 
43199 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
43200 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_LSB 25
43201 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
43202 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_MSB 25
43203 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
43204 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_WIDTH 1
43205 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */
43206 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET_MSK 0x02000000
43207 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */
43208 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_CLR_MSK 0xfdffffff
43209 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
43210 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_RESET 0x0
43211 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 field value from a register. */
43212 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
43213 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value suitable for setting the register. */
43214 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
43215 
43216 /*
43217  * Field : Mask Byte Control - mbc_2
43218  *
43219  * This array of bits are mask control bits for comparison of each of the MAC
43220  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43221  * received DA or SA with the contents of MAC Address32 high and low registers.
43222  * Each bit controls the masking of the bytes. You can filter a group of addresses
43223  * (known as group address filtering) by masking one or more bytes of the address.
43224  *
43225  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43226  *
43227  * Field Enumeration Values:
43228  *
43229  * Enum | Value | Description
43230  * :----------------------------------------------|:------|:------------------------------------
43231  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43232  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43233  *
43234  * Field Access Macros:
43235  *
43236  */
43237 /*
43238  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2
43239  *
43240  * Byte is unmasked (i.e. is compared)
43241  */
43242 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED 0x0
43243 /*
43244  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2
43245  *
43246  * Byte is masked (i.e. not compared)
43247  */
43248 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED 0x1
43249 
43250 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
43251 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_LSB 26
43252 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
43253 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_MSB 26
43254 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
43255 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_WIDTH 1
43256 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */
43257 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET_MSK 0x04000000
43258 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */
43259 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_CLR_MSK 0xfbffffff
43260 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
43261 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_RESET 0x0
43262 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 field value from a register. */
43263 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
43264 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value suitable for setting the register. */
43265 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
43266 
43267 /*
43268  * Field : Mask Byte Control - mbc_3
43269  *
43270  * This array of bits are mask control bits for comparison of each of the MAC
43271  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43272  * received DA or SA with the contents of MAC Address32 high and low registers.
43273  * Each bit controls the masking of the bytes. You can filter a group of addresses
43274  * (known as group address filtering) by masking one or more bytes of the address.
43275  *
43276  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43277  *
43278  * Field Enumeration Values:
43279  *
43280  * Enum | Value | Description
43281  * :----------------------------------------------|:------|:------------------------------------
43282  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43283  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43284  *
43285  * Field Access Macros:
43286  *
43287  */
43288 /*
43289  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3
43290  *
43291  * Byte is unmasked (i.e. is compared)
43292  */
43293 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED 0x0
43294 /*
43295  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3
43296  *
43297  * Byte is masked (i.e. not compared)
43298  */
43299 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED 0x1
43300 
43301 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
43302 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_LSB 27
43303 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
43304 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_MSB 27
43305 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
43306 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_WIDTH 1
43307 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */
43308 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET_MSK 0x08000000
43309 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */
43310 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_CLR_MSK 0xf7ffffff
43311 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
43312 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_RESET 0x0
43313 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 field value from a register. */
43314 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
43315 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value suitable for setting the register. */
43316 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
43317 
43318 /*
43319  * Field : Mask Byte Control - mbc_4
43320  *
43321  * This array of bits are mask control bits for comparison of each of the MAC
43322  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43323  * received DA or SA with the contents of MAC Address32 high and low registers.
43324  * Each bit controls the masking of the bytes. You can filter a group of addresses
43325  * (known as group address filtering) by masking one or more bytes of the address.
43326  *
43327  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43328  *
43329  * Field Enumeration Values:
43330  *
43331  * Enum | Value | Description
43332  * :----------------------------------------------|:------|:------------------------------------
43333  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43334  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43335  *
43336  * Field Access Macros:
43337  *
43338  */
43339 /*
43340  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4
43341  *
43342  * Byte is unmasked (i.e. is compared)
43343  */
43344 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED 0x0
43345 /*
43346  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4
43347  *
43348  * Byte is masked (i.e. not compared)
43349  */
43350 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED 0x1
43351 
43352 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
43353 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_LSB 28
43354 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
43355 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_MSB 28
43356 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
43357 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_WIDTH 1
43358 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */
43359 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET_MSK 0x10000000
43360 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */
43361 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_CLR_MSK 0xefffffff
43362 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
43363 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_RESET 0x0
43364 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 field value from a register. */
43365 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
43366 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value suitable for setting the register. */
43367 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
43368 
43369 /*
43370  * Field : Mask Byte Control - mbc_5
43371  *
43372  * This array of bits are mask control bits for comparison of each of the MAC
43373  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43374  * received DA or SA with the contents of MAC Address32 high and low registers.
43375  * Each bit controls the masking of the bytes. You can filter a group of addresses
43376  * (known as group address filtering) by masking one or more bytes of the address.
43377  *
43378  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43379  *
43380  * Field Enumeration Values:
43381  *
43382  * Enum | Value | Description
43383  * :----------------------------------------------|:------|:------------------------------------
43384  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43385  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43386  *
43387  * Field Access Macros:
43388  *
43389  */
43390 /*
43391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5
43392  *
43393  * Byte is unmasked (i.e. is compared)
43394  */
43395 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED 0x0
43396 /*
43397  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5
43398  *
43399  * Byte is masked (i.e. not compared)
43400  */
43401 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED 0x1
43402 
43403 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
43404 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_LSB 29
43405 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
43406 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_MSB 29
43407 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
43408 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_WIDTH 1
43409 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */
43410 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET_MSK 0x20000000
43411 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */
43412 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_CLR_MSK 0xdfffffff
43413 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
43414 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_RESET 0x0
43415 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 field value from a register. */
43416 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
43417 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value suitable for setting the register. */
43418 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
43419 
43420 /*
43421  * Field : Source Address - sa
43422  *
43423  * When this bit is enabled, the MAC Address32[47:0] is used to compare with the SA
43424  * fields of the received frame. When this bit is disabled, the MAC Address32[47:0]
43425  * is used to compare with the DA fields of the received frame.
43426  *
43427  * Field Enumeration Values:
43428  *
43429  * Enum | Value | Description
43430  * :----------------------------------------|:------|:-----------------------------
43431  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
43432  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END | 0x1 | MAC address compare enabled
43433  *
43434  * Field Access Macros:
43435  *
43436  */
43437 /*
43438  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA
43439  *
43440  * MAC address compare disabled
43441  */
43442 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD 0x0
43443 /*
43444  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA
43445  *
43446  * MAC address compare enabled
43447  */
43448 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END 0x1
43449 
43450 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
43451 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_LSB 30
43452 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
43453 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_MSB 30
43454 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
43455 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_WIDTH 1
43456 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */
43457 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET_MSK 0x40000000
43458 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */
43459 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_CLR_MSK 0xbfffffff
43460 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
43461 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_RESET 0x0
43462 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA field value from a register. */
43463 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
43464 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value suitable for setting the register. */
43465 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
43466 
43467 /*
43468  * Field : Address Enable - ae
43469  *
43470  * When this bit is enabled, the address filter block uses the 33th MAC address for
43471  * perfect filtering. When this bit is disabled, the address filter block ignores
43472  * the address for filtering.
43473  *
43474  * Field Enumeration Values:
43475  *
43476  * Enum | Value | Description
43477  * :----------------------------------------|:------|:--------------------------------------
43478  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
43479  * ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
43480  *
43481  * Field Access Macros:
43482  *
43483  */
43484 /*
43485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
43486  *
43487  * Second MAC address filtering disabled
43488  */
43489 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD 0x0
43490 /*
43491  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
43492  *
43493  * Second MAC address filtering enabled
43494  */
43495 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END 0x1
43496 
43497 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
43498 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_LSB 31
43499 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
43500 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_MSB 31
43501 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
43502 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_WIDTH 1
43503 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
43504 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET_MSK 0x80000000
43505 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
43506 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_CLR_MSK 0x7fffffff
43507 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
43508 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_RESET 0x0
43509 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE field value from a register. */
43510 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
43511 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value suitable for setting the register. */
43512 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
43513 
43514 #ifndef __ASSEMBLY__
43515 /*
43516  * WARNING: The C register and register group struct declarations are provided for
43517  * convenience and illustrative purposes. They should, however, be used with
43518  * caution as the C language standard provides no guarantees about the alignment or
43519  * atomicity of device memory accesses. The recommended practice for writing
43520  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43521  * alt_write_word() functions.
43522  *
43523  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH.
43524  */
43525 struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s
43526 {
43527  uint32_t addrhi : 16; /* MAC Address32 [47:32] */
43528  uint32_t : 8; /* *UNDEFINED* */
43529  uint32_t mbc_0 : 1; /* Mask Byte Control */
43530  uint32_t mbc_1 : 1; /* Mask Byte Control */
43531  uint32_t mbc_2 : 1; /* Mask Byte Control */
43532  uint32_t mbc_3 : 1; /* Mask Byte Control */
43533  uint32_t mbc_4 : 1; /* Mask Byte Control */
43534  uint32_t mbc_5 : 1; /* Mask Byte Control */
43535  uint32_t sa : 1; /* Source Address */
43536  uint32_t ae : 1; /* Address Enable */
43537 };
43538 
43539 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH. */
43540 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t;
43541 #endif /* __ASSEMBLY__ */
43542 
43543 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register from the beginning of the component. */
43544 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST 0x880
43545 /* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register. */
43546 #define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST))
43547 
43548 /*
43549  * Register : Register 545 (MAC Address32 Low Register) - MAC_Address32_Low
43550  *
43551  * The MAC Address32 Low register holds the lower 32 bits of the 33th 6-byte MAC
43552  * address of the station.
43553  *
43554  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
43555  * format.
43556  *
43557  * Register Layout
43558  *
43559  * Bits | Access | Reset | Description
43560  * :-------|:-------|:-----------|:---------------------
43561  * [31:0] | RW | 0xffffffff | MAC Address32 [31:0]
43562  *
43563  */
43564 /*
43565  * Field : MAC Address32 [31:0] - addrlo
43566  *
43567  * This field contains the lower 32 bits of the 33th 6-byte MAC address. The
43568  * content of this field is undefined until loaded by software after the
43569  * initialization process.
43570  *
43571  * Field Access Macros:
43572  *
43573  */
43574 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
43575 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_LSB 0
43576 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
43577 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_MSB 31
43578 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
43579 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_WIDTH 32
43580 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
43581 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET_MSK 0xffffffff
43582 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
43583 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_CLR_MSK 0x00000000
43584 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
43585 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_RESET 0xffffffff
43586 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO field value from a register. */
43587 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
43588 /* Produces a ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value suitable for setting the register. */
43589 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
43590 
43591 #ifndef __ASSEMBLY__
43592 /*
43593  * WARNING: The C register and register group struct declarations are provided for
43594  * convenience and illustrative purposes. They should, however, be used with
43595  * caution as the C language standard provides no guarantees about the alignment or
43596  * atomicity of device memory accesses. The recommended practice for writing
43597  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
43598  * alt_write_word() functions.
43599  *
43600  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW.
43601  */
43602 struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s
43603 {
43604  uint32_t addrlo : 32; /* MAC Address32 [31:0] */
43605 };
43606 
43607 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW. */
43608 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s ALT_EMAC_GMAC_MAC_ADDR32_LOW_t;
43609 #endif /* __ASSEMBLY__ */
43610 
43611 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register from the beginning of the component. */
43612 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST 0x884
43613 /* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register. */
43614 #define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST))
43615 
43616 /*
43617  * Register : Register 546 (MAC Address33 High Register) - MAC_Address33_High
43618  *
43619  * The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC
43620  * address of the station. Because the MAC address registers are configured to be
43621  * double-synchronized to the (G)MII clock domains, the synchronization is
43622  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
43623  * endian mode) of the MAC Address33 Low Register are written. For proper
43624  * synchronization updates, the consecutive writes to this Address Low Register
43625  * should be performed after at least four clock cycles in the destination clock
43626  * domain.
43627  *
43628  * Note that all MAC Address High registers (except MAC Address0 High) have the
43629  * same format.
43630  *
43631  * Register Layout
43632  *
43633  * Bits | Access | Reset | Description
43634  * :--------|:-------|:-------|:----------------------
43635  * [15:0] | RW | 0xffff | MAC Address33 [47:32]
43636  * [23:16] | ??? | 0x0 | *UNDEFINED*
43637  * [24] | RW | 0x0 | Mask Byte Control
43638  * [25] | RW | 0x0 | Mask Byte Control
43639  * [26] | RW | 0x0 | Mask Byte Control
43640  * [27] | RW | 0x0 | Mask Byte Control
43641  * [28] | RW | 0x0 | Mask Byte Control
43642  * [29] | RW | 0x0 | Mask Byte Control
43643  * [30] | RW | 0x0 | Source Address
43644  * [31] | RW | 0x0 | Address Enable
43645  *
43646  */
43647 /*
43648  * Field : MAC Address33 [47:32] - addrhi
43649  *
43650  * This field contains the upper 16 bits (47:32) of the 34th 6-byte MAC address.
43651  *
43652  * Field Access Macros:
43653  *
43654  */
43655 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
43656 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_LSB 0
43657 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
43658 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_MSB 15
43659 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
43660 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_WIDTH 16
43661 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
43662 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET_MSK 0x0000ffff
43663 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
43664 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_CLR_MSK 0xffff0000
43665 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
43666 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_RESET 0xffff
43667 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI field value from a register. */
43668 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
43669 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value suitable for setting the register. */
43670 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
43671 
43672 /*
43673  * Field : Mask Byte Control - mbc_0
43674  *
43675  * This array of bits are mask control bits for comparison of each of the MAC
43676  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43677  * received DA or SA with the contents of MAC Address33 high and low registers.
43678  * Each bit controls the masking of the bytes. You can filter a group of addresses
43679  * (known as group address filtering) by masking one or more bytes of the address.
43680  *
43681  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43682  *
43683  * Field Enumeration Values:
43684  *
43685  * Enum | Value | Description
43686  * :----------------------------------------------|:------|:------------------------------------
43687  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43688  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43689  *
43690  * Field Access Macros:
43691  *
43692  */
43693 /*
43694  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0
43695  *
43696  * Byte is unmasked (i.e. is compared)
43697  */
43698 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED 0x0
43699 /*
43700  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0
43701  *
43702  * Byte is masked (i.e. not compared)
43703  */
43704 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED 0x1
43705 
43706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
43707 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_LSB 24
43708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
43709 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_MSB 24
43710 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
43711 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_WIDTH 1
43712 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */
43713 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET_MSK 0x01000000
43714 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */
43715 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_CLR_MSK 0xfeffffff
43716 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
43717 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_RESET 0x0
43718 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 field value from a register. */
43719 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
43720 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value suitable for setting the register. */
43721 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
43722 
43723 /*
43724  * Field : Mask Byte Control - mbc_1
43725  *
43726  * This array of bits are mask control bits for comparison of each of the MAC
43727  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43728  * received DA or SA with the contents of MAC Address33 high and low registers.
43729  * Each bit controls the masking of the bytes. You can filter a group of addresses
43730  * (known as group address filtering) by masking one or more bytes of the address.
43731  *
43732  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43733  *
43734  * Field Enumeration Values:
43735  *
43736  * Enum | Value | Description
43737  * :----------------------------------------------|:------|:------------------------------------
43738  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43739  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43740  *
43741  * Field Access Macros:
43742  *
43743  */
43744 /*
43745  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1
43746  *
43747  * Byte is unmasked (i.e. is compared)
43748  */
43749 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED 0x0
43750 /*
43751  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1
43752  *
43753  * Byte is masked (i.e. not compared)
43754  */
43755 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED 0x1
43756 
43757 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
43758 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_LSB 25
43759 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
43760 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_MSB 25
43761 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
43762 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_WIDTH 1
43763 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */
43764 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET_MSK 0x02000000
43765 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */
43766 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_CLR_MSK 0xfdffffff
43767 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
43768 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_RESET 0x0
43769 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 field value from a register. */
43770 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
43771 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value suitable for setting the register. */
43772 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
43773 
43774 /*
43775  * Field : Mask Byte Control - mbc_2
43776  *
43777  * This array of bits are mask control bits for comparison of each of the MAC
43778  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43779  * received DA or SA with the contents of MAC Address33 high and low registers.
43780  * Each bit controls the masking of the bytes. You can filter a group of addresses
43781  * (known as group address filtering) by masking one or more bytes of the address.
43782  *
43783  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43784  *
43785  * Field Enumeration Values:
43786  *
43787  * Enum | Value | Description
43788  * :----------------------------------------------|:------|:------------------------------------
43789  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43790  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43791  *
43792  * Field Access Macros:
43793  *
43794  */
43795 /*
43796  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2
43797  *
43798  * Byte is unmasked (i.e. is compared)
43799  */
43800 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED 0x0
43801 /*
43802  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2
43803  *
43804  * Byte is masked (i.e. not compared)
43805  */
43806 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED 0x1
43807 
43808 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
43809 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_LSB 26
43810 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
43811 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_MSB 26
43812 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
43813 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_WIDTH 1
43814 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */
43815 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET_MSK 0x04000000
43816 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */
43817 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_CLR_MSK 0xfbffffff
43818 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
43819 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_RESET 0x0
43820 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 field value from a register. */
43821 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
43822 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value suitable for setting the register. */
43823 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
43824 
43825 /*
43826  * Field : Mask Byte Control - mbc_3
43827  *
43828  * This array of bits are mask control bits for comparison of each of the MAC
43829  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43830  * received DA or SA with the contents of MAC Address33 high and low registers.
43831  * Each bit controls the masking of the bytes. You can filter a group of addresses
43832  * (known as group address filtering) by masking one or more bytes of the address.
43833  *
43834  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43835  *
43836  * Field Enumeration Values:
43837  *
43838  * Enum | Value | Description
43839  * :----------------------------------------------|:------|:------------------------------------
43840  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43841  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43842  *
43843  * Field Access Macros:
43844  *
43845  */
43846 /*
43847  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3
43848  *
43849  * Byte is unmasked (i.e. is compared)
43850  */
43851 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED 0x0
43852 /*
43853  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3
43854  *
43855  * Byte is masked (i.e. not compared)
43856  */
43857 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED 0x1
43858 
43859 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
43860 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_LSB 27
43861 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
43862 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_MSB 27
43863 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
43864 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_WIDTH 1
43865 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */
43866 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET_MSK 0x08000000
43867 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */
43868 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_CLR_MSK 0xf7ffffff
43869 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
43870 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_RESET 0x0
43871 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 field value from a register. */
43872 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
43873 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value suitable for setting the register. */
43874 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
43875 
43876 /*
43877  * Field : Mask Byte Control - mbc_4
43878  *
43879  * This array of bits are mask control bits for comparison of each of the MAC
43880  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43881  * received DA or SA with the contents of MAC Address33 high and low registers.
43882  * Each bit controls the masking of the bytes. You can filter a group of addresses
43883  * (known as group address filtering) by masking one or more bytes of the address.
43884  *
43885  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43886  *
43887  * Field Enumeration Values:
43888  *
43889  * Enum | Value | Description
43890  * :----------------------------------------------|:------|:------------------------------------
43891  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43892  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43893  *
43894  * Field Access Macros:
43895  *
43896  */
43897 /*
43898  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4
43899  *
43900  * Byte is unmasked (i.e. is compared)
43901  */
43902 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED 0x0
43903 /*
43904  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4
43905  *
43906  * Byte is masked (i.e. not compared)
43907  */
43908 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED 0x1
43909 
43910 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
43911 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_LSB 28
43912 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
43913 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_MSB 28
43914 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
43915 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_WIDTH 1
43916 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */
43917 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET_MSK 0x10000000
43918 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */
43919 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_CLR_MSK 0xefffffff
43920 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
43921 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_RESET 0x0
43922 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 field value from a register. */
43923 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
43924 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value suitable for setting the register. */
43925 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
43926 
43927 /*
43928  * Field : Mask Byte Control - mbc_5
43929  *
43930  * This array of bits are mask control bits for comparison of each of the MAC
43931  * Address bytes. When masked, the MAC does not compare the corresponding byte of
43932  * received DA or SA with the contents of MAC Address33 high and low registers.
43933  * Each bit controls the masking of the bytes. You can filter a group of addresses
43934  * (known as group address filtering) by masking one or more bytes of the address.
43935  *
43936  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
43937  *
43938  * Field Enumeration Values:
43939  *
43940  * Enum | Value | Description
43941  * :----------------------------------------------|:------|:------------------------------------
43942  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
43943  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
43944  *
43945  * Field Access Macros:
43946  *
43947  */
43948 /*
43949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5
43950  *
43951  * Byte is unmasked (i.e. is compared)
43952  */
43953 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED 0x0
43954 /*
43955  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5
43956  *
43957  * Byte is masked (i.e. not compared)
43958  */
43959 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED 0x1
43960 
43961 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
43962 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_LSB 29
43963 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
43964 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_MSB 29
43965 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
43966 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_WIDTH 1
43967 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */
43968 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET_MSK 0x20000000
43969 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */
43970 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_CLR_MSK 0xdfffffff
43971 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
43972 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_RESET 0x0
43973 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 field value from a register. */
43974 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
43975 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value suitable for setting the register. */
43976 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
43977 
43978 /*
43979  * Field : Source Address - sa
43980  *
43981  * When this bit is enabled, the MAC Address33[47:0] is used to compare with the SA
43982  * fields of the received frame. When this bit is disabled, the MAC Address33[47:0]
43983  * is used to compare with the DA fields of the received frame.
43984  *
43985  * Field Enumeration Values:
43986  *
43987  * Enum | Value | Description
43988  * :----------------------------------------|:------|:-----------------------------
43989  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
43990  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END | 0x1 | MAC address compare enabled
43991  *
43992  * Field Access Macros:
43993  *
43994  */
43995 /*
43996  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA
43997  *
43998  * MAC address compare disabled
43999  */
44000 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD 0x0
44001 /*
44002  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA
44003  *
44004  * MAC address compare enabled
44005  */
44006 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END 0x1
44007 
44008 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
44009 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_LSB 30
44010 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
44011 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_MSB 30
44012 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
44013 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_WIDTH 1
44014 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */
44015 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET_MSK 0x40000000
44016 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */
44017 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_CLR_MSK 0xbfffffff
44018 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
44019 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_RESET 0x0
44020 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA field value from a register. */
44021 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
44022 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value suitable for setting the register. */
44023 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
44024 
44025 /*
44026  * Field : Address Enable - ae
44027  *
44028  * When this bit is enabled, the address filter block uses the 34th MAC address for
44029  * perfect filtering. When this bit is disabled, the address filter block ignores
44030  * the address for filtering.
44031  *
44032  * Field Enumeration Values:
44033  *
44034  * Enum | Value | Description
44035  * :----------------------------------------|:------|:--------------------------------------
44036  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
44037  * ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
44038  *
44039  * Field Access Macros:
44040  *
44041  */
44042 /*
44043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
44044  *
44045  * Second MAC address filtering disabled
44046  */
44047 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD 0x0
44048 /*
44049  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
44050  *
44051  * Second MAC address filtering enabled
44052  */
44053 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END 0x1
44054 
44055 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
44056 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_LSB 31
44057 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
44058 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_MSB 31
44059 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
44060 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_WIDTH 1
44061 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
44062 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET_MSK 0x80000000
44063 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
44064 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_CLR_MSK 0x7fffffff
44065 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
44066 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_RESET 0x0
44067 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE field value from a register. */
44068 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
44069 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value suitable for setting the register. */
44070 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
44071 
44072 #ifndef __ASSEMBLY__
44073 /*
44074  * WARNING: The C register and register group struct declarations are provided for
44075  * convenience and illustrative purposes. They should, however, be used with
44076  * caution as the C language standard provides no guarantees about the alignment or
44077  * atomicity of device memory accesses. The recommended practice for writing
44078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44079  * alt_write_word() functions.
44080  *
44081  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH.
44082  */
44083 struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s
44084 {
44085  uint32_t addrhi : 16; /* MAC Address33 [47:32] */
44086  uint32_t : 8; /* *UNDEFINED* */
44087  uint32_t mbc_0 : 1; /* Mask Byte Control */
44088  uint32_t mbc_1 : 1; /* Mask Byte Control */
44089  uint32_t mbc_2 : 1; /* Mask Byte Control */
44090  uint32_t mbc_3 : 1; /* Mask Byte Control */
44091  uint32_t mbc_4 : 1; /* Mask Byte Control */
44092  uint32_t mbc_5 : 1; /* Mask Byte Control */
44093  uint32_t sa : 1; /* Source Address */
44094  uint32_t ae : 1; /* Address Enable */
44095 };
44096 
44097 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH. */
44098 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t;
44099 #endif /* __ASSEMBLY__ */
44100 
44101 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register from the beginning of the component. */
44102 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST 0x888
44103 /* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register. */
44104 #define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST))
44105 
44106 /*
44107  * Register : Register 547 (MAC Address33 Low Register) - MAC_Address33_Low
44108  *
44109  * The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC
44110  * address of the station.
44111  *
44112  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
44113  * format.
44114  *
44115  * Register Layout
44116  *
44117  * Bits | Access | Reset | Description
44118  * :-------|:-------|:-----------|:---------------------
44119  * [31:0] | RW | 0xffffffff | MAC Address33 [31:0]
44120  *
44121  */
44122 /*
44123  * Field : MAC Address33 [31:0] - addrlo
44124  *
44125  * This field contains the lower 32 bits of the 34th 6-byte MAC address. The
44126  * content of this field is undefined until loaded by software after the
44127  * initialization process.
44128  *
44129  * Field Access Macros:
44130  *
44131  */
44132 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
44133 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_LSB 0
44134 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
44135 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_MSB 31
44136 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
44137 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_WIDTH 32
44138 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
44139 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET_MSK 0xffffffff
44140 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
44141 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_CLR_MSK 0x00000000
44142 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
44143 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_RESET 0xffffffff
44144 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO field value from a register. */
44145 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
44146 /* Produces a ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value suitable for setting the register. */
44147 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
44148 
44149 #ifndef __ASSEMBLY__
44150 /*
44151  * WARNING: The C register and register group struct declarations are provided for
44152  * convenience and illustrative purposes. They should, however, be used with
44153  * caution as the C language standard provides no guarantees about the alignment or
44154  * atomicity of device memory accesses. The recommended practice for writing
44155  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44156  * alt_write_word() functions.
44157  *
44158  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW.
44159  */
44160 struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s
44161 {
44162  uint32_t addrlo : 32; /* MAC Address33 [31:0] */
44163 };
44164 
44165 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW. */
44166 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s ALT_EMAC_GMAC_MAC_ADDR33_LOW_t;
44167 #endif /* __ASSEMBLY__ */
44168 
44169 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register from the beginning of the component. */
44170 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST 0x88c
44171 /* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register. */
44172 #define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST))
44173 
44174 /*
44175  * Register : Register 548 (MAC Address34 High Register) - MAC_Address34_High
44176  *
44177  * The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC
44178  * address of the station. Because the MAC address registers are configured to be
44179  * double-synchronized to the (G)MII clock domains, the synchronization is
44180  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
44181  * endian mode) of the MAC Address34 Low Register are written. For proper
44182  * synchronization updates, the consecutive writes to this Address Low Register
44183  * should be performed after at least four clock cycles in the destination clock
44184  * domain.
44185  *
44186  * Note that all MAC Address High registers (except MAC Address0 High) have the
44187  * same format.
44188  *
44189  * Register Layout
44190  *
44191  * Bits | Access | Reset | Description
44192  * :--------|:-------|:-------|:----------------------
44193  * [15:0] | RW | 0xffff | MAC Address34 [47:32]
44194  * [23:16] | ??? | 0x0 | *UNDEFINED*
44195  * [24] | RW | 0x0 | Mask Byte Control
44196  * [25] | RW | 0x0 | Mask Byte Control
44197  * [26] | RW | 0x0 | Mask Byte Control
44198  * [27] | RW | 0x0 | Mask Byte Control
44199  * [28] | RW | 0x0 | Mask Byte Control
44200  * [29] | RW | 0x0 | Mask Byte Control
44201  * [30] | RW | 0x0 | Source Address
44202  * [31] | RW | 0x0 | Address Enable
44203  *
44204  */
44205 /*
44206  * Field : MAC Address34 [47:32] - addrhi
44207  *
44208  * This field contains the upper 16 bits (47:32) of the 35th 6-byte MAC address.
44209  *
44210  * Field Access Macros:
44211  *
44212  */
44213 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
44214 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_LSB 0
44215 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
44216 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_MSB 15
44217 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
44218 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_WIDTH 16
44219 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
44220 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET_MSK 0x0000ffff
44221 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
44222 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_CLR_MSK 0xffff0000
44223 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
44224 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_RESET 0xffff
44225 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI field value from a register. */
44226 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
44227 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value suitable for setting the register. */
44228 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
44229 
44230 /*
44231  * Field : Mask Byte Control - mbc_0
44232  *
44233  * This array of bits are mask control bits for comparison of each of the MAC
44234  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44235  * received DA or SA with the contents of MAC Address34 high and low registers.
44236  * Each bit controls the masking of the bytes. You can filter a group of addresses
44237  * (known as group address filtering) by masking one or more bytes of the address.
44238  *
44239  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44240  *
44241  * Field Enumeration Values:
44242  *
44243  * Enum | Value | Description
44244  * :----------------------------------------------|:------|:------------------------------------
44245  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44246  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44247  *
44248  * Field Access Macros:
44249  *
44250  */
44251 /*
44252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0
44253  *
44254  * Byte is unmasked (i.e. is compared)
44255  */
44256 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED 0x0
44257 /*
44258  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0
44259  *
44260  * Byte is masked (i.e. not compared)
44261  */
44262 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED 0x1
44263 
44264 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
44265 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_LSB 24
44266 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
44267 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_MSB 24
44268 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
44269 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_WIDTH 1
44270 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */
44271 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET_MSK 0x01000000
44272 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */
44273 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_CLR_MSK 0xfeffffff
44274 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
44275 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_RESET 0x0
44276 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 field value from a register. */
44277 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
44278 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value suitable for setting the register. */
44279 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
44280 
44281 /*
44282  * Field : Mask Byte Control - mbc_1
44283  *
44284  * This array of bits are mask control bits for comparison of each of the MAC
44285  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44286  * received DA or SA with the contents of MAC Address34 high and low registers.
44287  * Each bit controls the masking of the bytes. You can filter a group of addresses
44288  * (known as group address filtering) by masking one or more bytes of the address.
44289  *
44290  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44291  *
44292  * Field Enumeration Values:
44293  *
44294  * Enum | Value | Description
44295  * :----------------------------------------------|:------|:------------------------------------
44296  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44297  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44298  *
44299  * Field Access Macros:
44300  *
44301  */
44302 /*
44303  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1
44304  *
44305  * Byte is unmasked (i.e. is compared)
44306  */
44307 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED 0x0
44308 /*
44309  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1
44310  *
44311  * Byte is masked (i.e. not compared)
44312  */
44313 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED 0x1
44314 
44315 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
44316 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_LSB 25
44317 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
44318 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_MSB 25
44319 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
44320 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_WIDTH 1
44321 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */
44322 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET_MSK 0x02000000
44323 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */
44324 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_CLR_MSK 0xfdffffff
44325 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
44326 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_RESET 0x0
44327 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 field value from a register. */
44328 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
44329 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value suitable for setting the register. */
44330 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
44331 
44332 /*
44333  * Field : Mask Byte Control - mbc_2
44334  *
44335  * This array of bits are mask control bits for comparison of each of the MAC
44336  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44337  * received DA or SA with the contents of MAC Address34 high and low registers.
44338  * Each bit controls the masking of the bytes. You can filter a group of addresses
44339  * (known as group address filtering) by masking one or more bytes of the address.
44340  *
44341  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44342  *
44343  * Field Enumeration Values:
44344  *
44345  * Enum | Value | Description
44346  * :----------------------------------------------|:------|:------------------------------------
44347  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44348  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44349  *
44350  * Field Access Macros:
44351  *
44352  */
44353 /*
44354  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2
44355  *
44356  * Byte is unmasked (i.e. is compared)
44357  */
44358 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED 0x0
44359 /*
44360  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2
44361  *
44362  * Byte is masked (i.e. not compared)
44363  */
44364 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED 0x1
44365 
44366 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
44367 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_LSB 26
44368 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
44369 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_MSB 26
44370 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
44371 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_WIDTH 1
44372 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */
44373 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET_MSK 0x04000000
44374 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */
44375 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_CLR_MSK 0xfbffffff
44376 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
44377 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_RESET 0x0
44378 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 field value from a register. */
44379 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
44380 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value suitable for setting the register. */
44381 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
44382 
44383 /*
44384  * Field : Mask Byte Control - mbc_3
44385  *
44386  * This array of bits are mask control bits for comparison of each of the MAC
44387  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44388  * received DA or SA with the contents of MAC Address34 high and low registers.
44389  * Each bit controls the masking of the bytes. You can filter a group of addresses
44390  * (known as group address filtering) by masking one or more bytes of the address.
44391  *
44392  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44393  *
44394  * Field Enumeration Values:
44395  *
44396  * Enum | Value | Description
44397  * :----------------------------------------------|:------|:------------------------------------
44398  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44399  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44400  *
44401  * Field Access Macros:
44402  *
44403  */
44404 /*
44405  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3
44406  *
44407  * Byte is unmasked (i.e. is compared)
44408  */
44409 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED 0x0
44410 /*
44411  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3
44412  *
44413  * Byte is masked (i.e. not compared)
44414  */
44415 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED 0x1
44416 
44417 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
44418 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_LSB 27
44419 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
44420 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_MSB 27
44421 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
44422 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_WIDTH 1
44423 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */
44424 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET_MSK 0x08000000
44425 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */
44426 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_CLR_MSK 0xf7ffffff
44427 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
44428 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_RESET 0x0
44429 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 field value from a register. */
44430 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
44431 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value suitable for setting the register. */
44432 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
44433 
44434 /*
44435  * Field : Mask Byte Control - mbc_4
44436  *
44437  * This array of bits are mask control bits for comparison of each of the MAC
44438  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44439  * received DA or SA with the contents of MAC Address34 high and low registers.
44440  * Each bit controls the masking of the bytes. You can filter a group of addresses
44441  * (known as group address filtering) by masking one or more bytes of the address.
44442  *
44443  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44444  *
44445  * Field Enumeration Values:
44446  *
44447  * Enum | Value | Description
44448  * :----------------------------------------------|:------|:------------------------------------
44449  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44450  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44451  *
44452  * Field Access Macros:
44453  *
44454  */
44455 /*
44456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4
44457  *
44458  * Byte is unmasked (i.e. is compared)
44459  */
44460 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED 0x0
44461 /*
44462  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4
44463  *
44464  * Byte is masked (i.e. not compared)
44465  */
44466 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED 0x1
44467 
44468 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
44469 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_LSB 28
44470 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
44471 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_MSB 28
44472 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
44473 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_WIDTH 1
44474 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */
44475 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET_MSK 0x10000000
44476 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */
44477 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_CLR_MSK 0xefffffff
44478 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
44479 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_RESET 0x0
44480 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 field value from a register. */
44481 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
44482 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value suitable for setting the register. */
44483 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
44484 
44485 /*
44486  * Field : Mask Byte Control - mbc_5
44487  *
44488  * This array of bits are mask control bits for comparison of each of the MAC
44489  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44490  * received DA or SA with the contents of MAC Address34 high and low registers.
44491  * Each bit controls the masking of the bytes. You can filter a group of addresses
44492  * (known as group address filtering) by masking one or more bytes of the address.
44493  *
44494  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44495  *
44496  * Field Enumeration Values:
44497  *
44498  * Enum | Value | Description
44499  * :----------------------------------------------|:------|:------------------------------------
44500  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44501  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44502  *
44503  * Field Access Macros:
44504  *
44505  */
44506 /*
44507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5
44508  *
44509  * Byte is unmasked (i.e. is compared)
44510  */
44511 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED 0x0
44512 /*
44513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5
44514  *
44515  * Byte is masked (i.e. not compared)
44516  */
44517 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED 0x1
44518 
44519 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
44520 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_LSB 29
44521 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
44522 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_MSB 29
44523 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
44524 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_WIDTH 1
44525 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */
44526 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET_MSK 0x20000000
44527 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */
44528 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_CLR_MSK 0xdfffffff
44529 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
44530 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_RESET 0x0
44531 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 field value from a register. */
44532 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
44533 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value suitable for setting the register. */
44534 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
44535 
44536 /*
44537  * Field : Source Address - sa
44538  *
44539  * When this bit is enabled, the MAC Address34[47:0] is used to compare with the SA
44540  * fields of the received frame. When this bit is disabled, the MAC Address34[47:0]
44541  * is used to compare with the DA fields of the received frame.
44542  *
44543  * Field Enumeration Values:
44544  *
44545  * Enum | Value | Description
44546  * :----------------------------------------|:------|:-----------------------------
44547  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
44548  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END | 0x1 | MAC address compare enabled
44549  *
44550  * Field Access Macros:
44551  *
44552  */
44553 /*
44554  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA
44555  *
44556  * MAC address compare disabled
44557  */
44558 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD 0x0
44559 /*
44560  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA
44561  *
44562  * MAC address compare enabled
44563  */
44564 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END 0x1
44565 
44566 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
44567 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_LSB 30
44568 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
44569 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_MSB 30
44570 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
44571 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_WIDTH 1
44572 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */
44573 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET_MSK 0x40000000
44574 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */
44575 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_CLR_MSK 0xbfffffff
44576 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
44577 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_RESET 0x0
44578 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA field value from a register. */
44579 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
44580 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value suitable for setting the register. */
44581 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
44582 
44583 /*
44584  * Field : Address Enable - ae
44585  *
44586  * When this bit is enabled, the address filter block uses the 35th MAC address for
44587  * perfect filtering. When this bit is disabled, the address filter block ignores
44588  * the address for filtering.
44589  *
44590  * Field Enumeration Values:
44591  *
44592  * Enum | Value | Description
44593  * :----------------------------------------|:------|:--------------------------------------
44594  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
44595  * ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
44596  *
44597  * Field Access Macros:
44598  *
44599  */
44600 /*
44601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
44602  *
44603  * Second MAC address filtering disabled
44604  */
44605 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD 0x0
44606 /*
44607  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
44608  *
44609  * Second MAC address filtering enabled
44610  */
44611 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END 0x1
44612 
44613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
44614 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_LSB 31
44615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
44616 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_MSB 31
44617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
44618 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_WIDTH 1
44619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
44620 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET_MSK 0x80000000
44621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
44622 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_CLR_MSK 0x7fffffff
44623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
44624 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_RESET 0x0
44625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE field value from a register. */
44626 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
44627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value suitable for setting the register. */
44628 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
44629 
44630 #ifndef __ASSEMBLY__
44631 /*
44632  * WARNING: The C register and register group struct declarations are provided for
44633  * convenience and illustrative purposes. They should, however, be used with
44634  * caution as the C language standard provides no guarantees about the alignment or
44635  * atomicity of device memory accesses. The recommended practice for writing
44636  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44637  * alt_write_word() functions.
44638  *
44639  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH.
44640  */
44641 struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s
44642 {
44643  uint32_t addrhi : 16; /* MAC Address34 [47:32] */
44644  uint32_t : 8; /* *UNDEFINED* */
44645  uint32_t mbc_0 : 1; /* Mask Byte Control */
44646  uint32_t mbc_1 : 1; /* Mask Byte Control */
44647  uint32_t mbc_2 : 1; /* Mask Byte Control */
44648  uint32_t mbc_3 : 1; /* Mask Byte Control */
44649  uint32_t mbc_4 : 1; /* Mask Byte Control */
44650  uint32_t mbc_5 : 1; /* Mask Byte Control */
44651  uint32_t sa : 1; /* Source Address */
44652  uint32_t ae : 1; /* Address Enable */
44653 };
44654 
44655 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH. */
44656 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t;
44657 #endif /* __ASSEMBLY__ */
44658 
44659 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register from the beginning of the component. */
44660 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST 0x890
44661 /* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register. */
44662 #define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST))
44663 
44664 /*
44665  * Register : Register 549 (MAC Address34 Low Register) - MAC_Address34_Low
44666  *
44667  * The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC
44668  * address of the station.
44669  *
44670  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
44671  * format.
44672  *
44673  * Register Layout
44674  *
44675  * Bits | Access | Reset | Description
44676  * :-------|:-------|:-----------|:---------------------
44677  * [31:0] | RW | 0xffffffff | MAC Address34 [31:0]
44678  *
44679  */
44680 /*
44681  * Field : MAC Address34 [31:0] - addrlo
44682  *
44683  * This field contains the lower 32 bits of the 35th 6-byte MAC address. The
44684  * content of this field is undefined until loaded by software after the
44685  * initialization process.
44686  *
44687  * Field Access Macros:
44688  *
44689  */
44690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
44691 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_LSB 0
44692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
44693 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_MSB 31
44694 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
44695 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_WIDTH 32
44696 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
44697 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET_MSK 0xffffffff
44698 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
44699 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_CLR_MSK 0x00000000
44700 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
44701 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_RESET 0xffffffff
44702 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO field value from a register. */
44703 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
44704 /* Produces a ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value suitable for setting the register. */
44705 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
44706 
44707 #ifndef __ASSEMBLY__
44708 /*
44709  * WARNING: The C register and register group struct declarations are provided for
44710  * convenience and illustrative purposes. They should, however, be used with
44711  * caution as the C language standard provides no guarantees about the alignment or
44712  * atomicity of device memory accesses. The recommended practice for writing
44713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
44714  * alt_write_word() functions.
44715  *
44716  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW.
44717  */
44718 struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s
44719 {
44720  uint32_t addrlo : 32; /* MAC Address34 [31:0] */
44721 };
44722 
44723 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW. */
44724 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s ALT_EMAC_GMAC_MAC_ADDR34_LOW_t;
44725 #endif /* __ASSEMBLY__ */
44726 
44727 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register from the beginning of the component. */
44728 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST 0x894
44729 /* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register. */
44730 #define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST))
44731 
44732 /*
44733  * Register : Register 550 (MAC Address35 High Register) - MAC_Address35_High
44734  *
44735  * The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC
44736  * address of the station. Because the MAC address registers are configured to be
44737  * double-synchronized to the (G)MII clock domains, the synchronization is
44738  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
44739  * endian mode) of the MAC Address35 Low Register are written. For proper
44740  * synchronization updates, the consecutive writes to this Address Low Register
44741  * should be performed after at least four clock cycles in the destination clock
44742  * domain.
44743  *
44744  * Note that all MAC Address High registers (except MAC Address0 High) have the
44745  * same format.
44746  *
44747  * Register Layout
44748  *
44749  * Bits | Access | Reset | Description
44750  * :--------|:-------|:-------|:----------------------
44751  * [15:0] | RW | 0xffff | MAC Address35 [47:32]
44752  * [23:16] | ??? | 0x0 | *UNDEFINED*
44753  * [24] | RW | 0x0 | Mask Byte Control
44754  * [25] | RW | 0x0 | Mask Byte Control
44755  * [26] | RW | 0x0 | Mask Byte Control
44756  * [27] | RW | 0x0 | Mask Byte Control
44757  * [28] | RW | 0x0 | Mask Byte Control
44758  * [29] | RW | 0x0 | Mask Byte Control
44759  * [30] | RW | 0x0 | Source Address
44760  * [31] | RW | 0x0 | Address Enable
44761  *
44762  */
44763 /*
44764  * Field : MAC Address35 [47:32] - addrhi
44765  *
44766  * This field contains the upper 16 bits (47:32) of the 36th 6-byte MAC address.
44767  *
44768  * Field Access Macros:
44769  *
44770  */
44771 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
44772 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_LSB 0
44773 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
44774 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_MSB 15
44775 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
44776 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_WIDTH 16
44777 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
44778 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET_MSK 0x0000ffff
44779 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
44780 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_CLR_MSK 0xffff0000
44781 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
44782 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_RESET 0xffff
44783 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI field value from a register. */
44784 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
44785 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value suitable for setting the register. */
44786 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
44787 
44788 /*
44789  * Field : Mask Byte Control - mbc_0
44790  *
44791  * This array of bits are mask control bits for comparison of each of the MAC
44792  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44793  * received DA or SA with the contents of MAC Address35 high and low registers.
44794  * Each bit controls the masking of the bytes. You can filter a group of addresses
44795  * (known as group address filtering) by masking one or more bytes of the address.
44796  *
44797  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44798  *
44799  * Field Enumeration Values:
44800  *
44801  * Enum | Value | Description
44802  * :----------------------------------------------|:------|:------------------------------------
44803  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44804  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44805  *
44806  * Field Access Macros:
44807  *
44808  */
44809 /*
44810  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0
44811  *
44812  * Byte is unmasked (i.e. is compared)
44813  */
44814 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED 0x0
44815 /*
44816  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0
44817  *
44818  * Byte is masked (i.e. not compared)
44819  */
44820 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED 0x1
44821 
44822 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
44823 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_LSB 24
44824 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
44825 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_MSB 24
44826 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
44827 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_WIDTH 1
44828 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */
44829 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET_MSK 0x01000000
44830 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */
44831 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_CLR_MSK 0xfeffffff
44832 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
44833 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_RESET 0x0
44834 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 field value from a register. */
44835 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
44836 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value suitable for setting the register. */
44837 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
44838 
44839 /*
44840  * Field : Mask Byte Control - mbc_1
44841  *
44842  * This array of bits are mask control bits for comparison of each of the MAC
44843  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44844  * received DA or SA with the contents of MAC Address35 high and low registers.
44845  * Each bit controls the masking of the bytes. You can filter a group of addresses
44846  * (known as group address filtering) by masking one or more bytes of the address.
44847  *
44848  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44849  *
44850  * Field Enumeration Values:
44851  *
44852  * Enum | Value | Description
44853  * :----------------------------------------------|:------|:------------------------------------
44854  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44855  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44856  *
44857  * Field Access Macros:
44858  *
44859  */
44860 /*
44861  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1
44862  *
44863  * Byte is unmasked (i.e. is compared)
44864  */
44865 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED 0x0
44866 /*
44867  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1
44868  *
44869  * Byte is masked (i.e. not compared)
44870  */
44871 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED 0x1
44872 
44873 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
44874 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_LSB 25
44875 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
44876 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_MSB 25
44877 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
44878 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_WIDTH 1
44879 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */
44880 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET_MSK 0x02000000
44881 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */
44882 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_CLR_MSK 0xfdffffff
44883 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
44884 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_RESET 0x0
44885 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 field value from a register. */
44886 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
44887 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value suitable for setting the register. */
44888 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
44889 
44890 /*
44891  * Field : Mask Byte Control - mbc_2
44892  *
44893  * This array of bits are mask control bits for comparison of each of the MAC
44894  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44895  * received DA or SA with the contents of MAC Address35 high and low registers.
44896  * Each bit controls the masking of the bytes. You can filter a group of addresses
44897  * (known as group address filtering) by masking one or more bytes of the address.
44898  *
44899  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44900  *
44901  * Field Enumeration Values:
44902  *
44903  * Enum | Value | Description
44904  * :----------------------------------------------|:------|:------------------------------------
44905  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44906  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44907  *
44908  * Field Access Macros:
44909  *
44910  */
44911 /*
44912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2
44913  *
44914  * Byte is unmasked (i.e. is compared)
44915  */
44916 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED 0x0
44917 /*
44918  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2
44919  *
44920  * Byte is masked (i.e. not compared)
44921  */
44922 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED 0x1
44923 
44924 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
44925 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_LSB 26
44926 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
44927 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_MSB 26
44928 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
44929 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_WIDTH 1
44930 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */
44931 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET_MSK 0x04000000
44932 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */
44933 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_CLR_MSK 0xfbffffff
44934 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
44935 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_RESET 0x0
44936 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 field value from a register. */
44937 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
44938 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value suitable for setting the register. */
44939 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
44940 
44941 /*
44942  * Field : Mask Byte Control - mbc_3
44943  *
44944  * This array of bits are mask control bits for comparison of each of the MAC
44945  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44946  * received DA or SA with the contents of MAC Address35 high and low registers.
44947  * Each bit controls the masking of the bytes. You can filter a group of addresses
44948  * (known as group address filtering) by masking one or more bytes of the address.
44949  *
44950  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
44951  *
44952  * Field Enumeration Values:
44953  *
44954  * Enum | Value | Description
44955  * :----------------------------------------------|:------|:------------------------------------
44956  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
44957  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
44958  *
44959  * Field Access Macros:
44960  *
44961  */
44962 /*
44963  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3
44964  *
44965  * Byte is unmasked (i.e. is compared)
44966  */
44967 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED 0x0
44968 /*
44969  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3
44970  *
44971  * Byte is masked (i.e. not compared)
44972  */
44973 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED 0x1
44974 
44975 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
44976 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_LSB 27
44977 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
44978 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_MSB 27
44979 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
44980 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_WIDTH 1
44981 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */
44982 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET_MSK 0x08000000
44983 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */
44984 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_CLR_MSK 0xf7ffffff
44985 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
44986 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_RESET 0x0
44987 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 field value from a register. */
44988 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
44989 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value suitable for setting the register. */
44990 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
44991 
44992 /*
44993  * Field : Mask Byte Control - mbc_4
44994  *
44995  * This array of bits are mask control bits for comparison of each of the MAC
44996  * Address bytes. When masked, the MAC does not compare the corresponding byte of
44997  * received DA or SA with the contents of MAC Address35 high and low registers.
44998  * Each bit controls the masking of the bytes. You can filter a group of addresses
44999  * (known as group address filtering) by masking one or more bytes of the address.
45000  *
45001  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45002  *
45003  * Field Enumeration Values:
45004  *
45005  * Enum | Value | Description
45006  * :----------------------------------------------|:------|:------------------------------------
45007  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45008  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45009  *
45010  * Field Access Macros:
45011  *
45012  */
45013 /*
45014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4
45015  *
45016  * Byte is unmasked (i.e. is compared)
45017  */
45018 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED 0x0
45019 /*
45020  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4
45021  *
45022  * Byte is masked (i.e. not compared)
45023  */
45024 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED 0x1
45025 
45026 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
45027 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_LSB 28
45028 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
45029 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_MSB 28
45030 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
45031 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_WIDTH 1
45032 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */
45033 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET_MSK 0x10000000
45034 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */
45035 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_CLR_MSK 0xefffffff
45036 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
45037 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_RESET 0x0
45038 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 field value from a register. */
45039 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
45040 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value suitable for setting the register. */
45041 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
45042 
45043 /*
45044  * Field : Mask Byte Control - mbc_5
45045  *
45046  * This array of bits are mask control bits for comparison of each of the MAC
45047  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45048  * received DA or SA with the contents of MAC Address35 high and low registers.
45049  * Each bit controls the masking of the bytes. You can filter a group of addresses
45050  * (known as group address filtering) by masking one or more bytes of the address.
45051  *
45052  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45053  *
45054  * Field Enumeration Values:
45055  *
45056  * Enum | Value | Description
45057  * :----------------------------------------------|:------|:------------------------------------
45058  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45059  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45060  *
45061  * Field Access Macros:
45062  *
45063  */
45064 /*
45065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5
45066  *
45067  * Byte is unmasked (i.e. is compared)
45068  */
45069 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED 0x0
45070 /*
45071  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5
45072  *
45073  * Byte is masked (i.e. not compared)
45074  */
45075 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED 0x1
45076 
45077 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
45078 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_LSB 29
45079 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
45080 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_MSB 29
45081 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
45082 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_WIDTH 1
45083 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */
45084 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET_MSK 0x20000000
45085 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */
45086 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_CLR_MSK 0xdfffffff
45087 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
45088 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_RESET 0x0
45089 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 field value from a register. */
45090 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
45091 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value suitable for setting the register. */
45092 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
45093 
45094 /*
45095  * Field : Source Address - sa
45096  *
45097  * When this bit is enabled, the MAC Address35[47:0] is used to compare with the SA
45098  * fields of the received frame. When this bit is disabled, the MAC Address35[47:0]
45099  * is used to compare with the DA fields of the received frame.
45100  *
45101  * Field Enumeration Values:
45102  *
45103  * Enum | Value | Description
45104  * :----------------------------------------|:------|:-----------------------------
45105  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
45106  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END | 0x1 | MAC address compare enabled
45107  *
45108  * Field Access Macros:
45109  *
45110  */
45111 /*
45112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA
45113  *
45114  * MAC address compare disabled
45115  */
45116 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD 0x0
45117 /*
45118  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA
45119  *
45120  * MAC address compare enabled
45121  */
45122 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END 0x1
45123 
45124 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
45125 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_LSB 30
45126 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
45127 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_MSB 30
45128 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
45129 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_WIDTH 1
45130 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */
45131 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET_MSK 0x40000000
45132 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */
45133 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_CLR_MSK 0xbfffffff
45134 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
45135 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_RESET 0x0
45136 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA field value from a register. */
45137 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
45138 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value suitable for setting the register. */
45139 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
45140 
45141 /*
45142  * Field : Address Enable - ae
45143  *
45144  * When this bit is enabled, the address filter block uses the 36th MAC address for
45145  * perfect filtering. When this bit is disabled, the address filter block ignores
45146  * the address for filtering.
45147  *
45148  * Field Enumeration Values:
45149  *
45150  * Enum | Value | Description
45151  * :----------------------------------------|:------|:--------------------------------------
45152  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
45153  * ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
45154  *
45155  * Field Access Macros:
45156  *
45157  */
45158 /*
45159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
45160  *
45161  * Second MAC address filtering disabled
45162  */
45163 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD 0x0
45164 /*
45165  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
45166  *
45167  * Second MAC address filtering enabled
45168  */
45169 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END 0x1
45170 
45171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
45172 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_LSB 31
45173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
45174 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_MSB 31
45175 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
45176 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_WIDTH 1
45177 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
45178 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET_MSK 0x80000000
45179 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
45180 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_CLR_MSK 0x7fffffff
45181 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
45182 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_RESET 0x0
45183 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE field value from a register. */
45184 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
45185 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value suitable for setting the register. */
45186 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
45187 
45188 #ifndef __ASSEMBLY__
45189 /*
45190  * WARNING: The C register and register group struct declarations are provided for
45191  * convenience and illustrative purposes. They should, however, be used with
45192  * caution as the C language standard provides no guarantees about the alignment or
45193  * atomicity of device memory accesses. The recommended practice for writing
45194  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45195  * alt_write_word() functions.
45196  *
45197  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH.
45198  */
45199 struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s
45200 {
45201  uint32_t addrhi : 16; /* MAC Address35 [47:32] */
45202  uint32_t : 8; /* *UNDEFINED* */
45203  uint32_t mbc_0 : 1; /* Mask Byte Control */
45204  uint32_t mbc_1 : 1; /* Mask Byte Control */
45205  uint32_t mbc_2 : 1; /* Mask Byte Control */
45206  uint32_t mbc_3 : 1; /* Mask Byte Control */
45207  uint32_t mbc_4 : 1; /* Mask Byte Control */
45208  uint32_t mbc_5 : 1; /* Mask Byte Control */
45209  uint32_t sa : 1; /* Source Address */
45210  uint32_t ae : 1; /* Address Enable */
45211 };
45212 
45213 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH. */
45214 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t;
45215 #endif /* __ASSEMBLY__ */
45216 
45217 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register from the beginning of the component. */
45218 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST 0x898
45219 /* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register. */
45220 #define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST))
45221 
45222 /*
45223  * Register : Register 551 (MAC Address35 Low Register) - MAC_Address35_Low
45224  *
45225  * The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC
45226  * address of the station.
45227  *
45228  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
45229  * format.
45230  *
45231  * Register Layout
45232  *
45233  * Bits | Access | Reset | Description
45234  * :-------|:-------|:-----------|:---------------------
45235  * [31:0] | RW | 0xffffffff | MAC Address35 [31:0]
45236  *
45237  */
45238 /*
45239  * Field : MAC Address35 [31:0] - addrlo
45240  *
45241  * This field contains the lower 32 bits of the 36th 6-byte MAC address. The
45242  * content of this field is undefined until loaded by software after the
45243  * initialization process.
45244  *
45245  * Field Access Macros:
45246  *
45247  */
45248 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
45249 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_LSB 0
45250 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
45251 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_MSB 31
45252 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
45253 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_WIDTH 32
45254 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
45255 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET_MSK 0xffffffff
45256 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
45257 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_CLR_MSK 0x00000000
45258 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
45259 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_RESET 0xffffffff
45260 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO field value from a register. */
45261 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
45262 /* Produces a ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value suitable for setting the register. */
45263 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
45264 
45265 #ifndef __ASSEMBLY__
45266 /*
45267  * WARNING: The C register and register group struct declarations are provided for
45268  * convenience and illustrative purposes. They should, however, be used with
45269  * caution as the C language standard provides no guarantees about the alignment or
45270  * atomicity of device memory accesses. The recommended practice for writing
45271  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45272  * alt_write_word() functions.
45273  *
45274  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW.
45275  */
45276 struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s
45277 {
45278  uint32_t addrlo : 32; /* MAC Address35 [31:0] */
45279 };
45280 
45281 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW. */
45282 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s ALT_EMAC_GMAC_MAC_ADDR35_LOW_t;
45283 #endif /* __ASSEMBLY__ */
45284 
45285 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register from the beginning of the component. */
45286 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST 0x89c
45287 /* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register. */
45288 #define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST))
45289 
45290 /*
45291  * Register : Register 552 (MAC Address36 High Register) - MAC_Address36_High
45292  *
45293  * The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC
45294  * address of the station. Because the MAC address registers are configured to be
45295  * double-synchronized to the (G)MII clock domains, the synchronization is
45296  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
45297  * endian mode) of the MAC Address36 Low Register are written. For proper
45298  * synchronization updates, the consecutive writes to this Address Low Register
45299  * should be performed after at least four clock cycles in the destination clock
45300  * domain.
45301  *
45302  * Note that all MAC Address High registers (except MAC Address0 High) have the
45303  * same format.
45304  *
45305  * Register Layout
45306  *
45307  * Bits | Access | Reset | Description
45308  * :--------|:-------|:-------|:----------------------
45309  * [15:0] | RW | 0xffff | MAC Address36 [47:32]
45310  * [23:16] | ??? | 0x0 | *UNDEFINED*
45311  * [24] | RW | 0x0 | Mask Byte Control
45312  * [25] | RW | 0x0 | Mask Byte Control
45313  * [26] | RW | 0x0 | Mask Byte Control
45314  * [27] | RW | 0x0 | Mask Byte Control
45315  * [28] | RW | 0x0 | Mask Byte Control
45316  * [29] | RW | 0x0 | Mask Byte Control
45317  * [30] | RW | 0x0 | Source Address
45318  * [31] | RW | 0x0 | Address Enable
45319  *
45320  */
45321 /*
45322  * Field : MAC Address36 [47:32] - addrhi
45323  *
45324  * This field contains the upper 16 bits (47:32) of the 37th 6-byte MAC address.
45325  *
45326  * Field Access Macros:
45327  *
45328  */
45329 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
45330 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_LSB 0
45331 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
45332 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_MSB 15
45333 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
45334 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_WIDTH 16
45335 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
45336 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET_MSK 0x0000ffff
45337 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
45338 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_CLR_MSK 0xffff0000
45339 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
45340 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_RESET 0xffff
45341 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI field value from a register. */
45342 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
45343 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value suitable for setting the register. */
45344 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
45345 
45346 /*
45347  * Field : Mask Byte Control - mbc_0
45348  *
45349  * This array of bits are mask control bits for comparison of each of the MAC
45350  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45351  * received DA or SA with the contents of MAC Address36 high and low registers.
45352  * Each bit controls the masking of the bytes. You can filter a group of addresses
45353  * (known as group address filtering) by masking one or more bytes of the address.
45354  *
45355  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45356  *
45357  * Field Enumeration Values:
45358  *
45359  * Enum | Value | Description
45360  * :----------------------------------------------|:------|:------------------------------------
45361  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45362  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45363  *
45364  * Field Access Macros:
45365  *
45366  */
45367 /*
45368  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0
45369  *
45370  * Byte is unmasked (i.e. is compared)
45371  */
45372 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED 0x0
45373 /*
45374  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0
45375  *
45376  * Byte is masked (i.e. not compared)
45377  */
45378 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED 0x1
45379 
45380 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
45381 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_LSB 24
45382 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
45383 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_MSB 24
45384 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
45385 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_WIDTH 1
45386 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */
45387 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET_MSK 0x01000000
45388 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */
45389 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_CLR_MSK 0xfeffffff
45390 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
45391 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_RESET 0x0
45392 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 field value from a register. */
45393 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
45394 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value suitable for setting the register. */
45395 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
45396 
45397 /*
45398  * Field : Mask Byte Control - mbc_1
45399  *
45400  * This array of bits are mask control bits for comparison of each of the MAC
45401  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45402  * received DA or SA with the contents of MAC Address36 high and low registers.
45403  * Each bit controls the masking of the bytes. You can filter a group of addresses
45404  * (known as group address filtering) by masking one or more bytes of the address.
45405  *
45406  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45407  *
45408  * Field Enumeration Values:
45409  *
45410  * Enum | Value | Description
45411  * :----------------------------------------------|:------|:------------------------------------
45412  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45413  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45414  *
45415  * Field Access Macros:
45416  *
45417  */
45418 /*
45419  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1
45420  *
45421  * Byte is unmasked (i.e. is compared)
45422  */
45423 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED 0x0
45424 /*
45425  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1
45426  *
45427  * Byte is masked (i.e. not compared)
45428  */
45429 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED 0x1
45430 
45431 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
45432 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_LSB 25
45433 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
45434 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_MSB 25
45435 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
45436 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_WIDTH 1
45437 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */
45438 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET_MSK 0x02000000
45439 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */
45440 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_CLR_MSK 0xfdffffff
45441 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
45442 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_RESET 0x0
45443 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 field value from a register. */
45444 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
45445 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value suitable for setting the register. */
45446 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
45447 
45448 /*
45449  * Field : Mask Byte Control - mbc_2
45450  *
45451  * This array of bits are mask control bits for comparison of each of the MAC
45452  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45453  * received DA or SA with the contents of MAC Address36 high and low registers.
45454  * Each bit controls the masking of the bytes. You can filter a group of addresses
45455  * (known as group address filtering) by masking one or more bytes of the address.
45456  *
45457  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45458  *
45459  * Field Enumeration Values:
45460  *
45461  * Enum | Value | Description
45462  * :----------------------------------------------|:------|:------------------------------------
45463  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45464  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45465  *
45466  * Field Access Macros:
45467  *
45468  */
45469 /*
45470  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2
45471  *
45472  * Byte is unmasked (i.e. is compared)
45473  */
45474 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED 0x0
45475 /*
45476  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2
45477  *
45478  * Byte is masked (i.e. not compared)
45479  */
45480 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED 0x1
45481 
45482 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
45483 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_LSB 26
45484 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
45485 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_MSB 26
45486 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
45487 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_WIDTH 1
45488 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */
45489 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET_MSK 0x04000000
45490 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */
45491 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_CLR_MSK 0xfbffffff
45492 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
45493 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_RESET 0x0
45494 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 field value from a register. */
45495 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
45496 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value suitable for setting the register. */
45497 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
45498 
45499 /*
45500  * Field : Mask Byte Control - mbc_3
45501  *
45502  * This array of bits are mask control bits for comparison of each of the MAC
45503  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45504  * received DA or SA with the contents of MAC Address36 high and low registers.
45505  * Each bit controls the masking of the bytes. You can filter a group of addresses
45506  * (known as group address filtering) by masking one or more bytes of the address.
45507  *
45508  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45509  *
45510  * Field Enumeration Values:
45511  *
45512  * Enum | Value | Description
45513  * :----------------------------------------------|:------|:------------------------------------
45514  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45515  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45516  *
45517  * Field Access Macros:
45518  *
45519  */
45520 /*
45521  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3
45522  *
45523  * Byte is unmasked (i.e. is compared)
45524  */
45525 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED 0x0
45526 /*
45527  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3
45528  *
45529  * Byte is masked (i.e. not compared)
45530  */
45531 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED 0x1
45532 
45533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
45534 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_LSB 27
45535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
45536 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_MSB 27
45537 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
45538 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_WIDTH 1
45539 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */
45540 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET_MSK 0x08000000
45541 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */
45542 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_CLR_MSK 0xf7ffffff
45543 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
45544 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_RESET 0x0
45545 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 field value from a register. */
45546 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
45547 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value suitable for setting the register. */
45548 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
45549 
45550 /*
45551  * Field : Mask Byte Control - mbc_4
45552  *
45553  * This array of bits are mask control bits for comparison of each of the MAC
45554  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45555  * received DA or SA with the contents of MAC Address36 high and low registers.
45556  * Each bit controls the masking of the bytes. You can filter a group of addresses
45557  * (known as group address filtering) by masking one or more bytes of the address.
45558  *
45559  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45560  *
45561  * Field Enumeration Values:
45562  *
45563  * Enum | Value | Description
45564  * :----------------------------------------------|:------|:------------------------------------
45565  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45566  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45567  *
45568  * Field Access Macros:
45569  *
45570  */
45571 /*
45572  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4
45573  *
45574  * Byte is unmasked (i.e. is compared)
45575  */
45576 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED 0x0
45577 /*
45578  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4
45579  *
45580  * Byte is masked (i.e. not compared)
45581  */
45582 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED 0x1
45583 
45584 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
45585 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_LSB 28
45586 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
45587 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_MSB 28
45588 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
45589 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_WIDTH 1
45590 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */
45591 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET_MSK 0x10000000
45592 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */
45593 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_CLR_MSK 0xefffffff
45594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
45595 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_RESET 0x0
45596 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 field value from a register. */
45597 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
45598 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value suitable for setting the register. */
45599 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
45600 
45601 /*
45602  * Field : Mask Byte Control - mbc_5
45603  *
45604  * This array of bits are mask control bits for comparison of each of the MAC
45605  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45606  * received DA or SA with the contents of MAC Address36 high and low registers.
45607  * Each bit controls the masking of the bytes. You can filter a group of addresses
45608  * (known as group address filtering) by masking one or more bytes of the address.
45609  *
45610  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45611  *
45612  * Field Enumeration Values:
45613  *
45614  * Enum | Value | Description
45615  * :----------------------------------------------|:------|:------------------------------------
45616  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45617  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45618  *
45619  * Field Access Macros:
45620  *
45621  */
45622 /*
45623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5
45624  *
45625  * Byte is unmasked (i.e. is compared)
45626  */
45627 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED 0x0
45628 /*
45629  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5
45630  *
45631  * Byte is masked (i.e. not compared)
45632  */
45633 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED 0x1
45634 
45635 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
45636 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_LSB 29
45637 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
45638 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_MSB 29
45639 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
45640 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_WIDTH 1
45641 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */
45642 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET_MSK 0x20000000
45643 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */
45644 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_CLR_MSK 0xdfffffff
45645 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
45646 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_RESET 0x0
45647 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 field value from a register. */
45648 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
45649 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value suitable for setting the register. */
45650 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
45651 
45652 /*
45653  * Field : Source Address - sa
45654  *
45655  * When this bit is enabled, the MAC Address36[47:0] is used to compare with the SA
45656  * fields of the received frame. When this bit is disabled, the MAC Address36[47:0]
45657  * is used to compare with the DA fields of the received frame.
45658  *
45659  * Field Enumeration Values:
45660  *
45661  * Enum | Value | Description
45662  * :----------------------------------------|:------|:-----------------------------
45663  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
45664  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END | 0x1 | MAC address compare enabled
45665  *
45666  * Field Access Macros:
45667  *
45668  */
45669 /*
45670  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA
45671  *
45672  * MAC address compare disabled
45673  */
45674 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD 0x0
45675 /*
45676  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA
45677  *
45678  * MAC address compare enabled
45679  */
45680 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END 0x1
45681 
45682 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
45683 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_LSB 30
45684 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
45685 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_MSB 30
45686 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
45687 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_WIDTH 1
45688 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */
45689 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET_MSK 0x40000000
45690 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */
45691 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_CLR_MSK 0xbfffffff
45692 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
45693 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_RESET 0x0
45694 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA field value from a register. */
45695 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
45696 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value suitable for setting the register. */
45697 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
45698 
45699 /*
45700  * Field : Address Enable - ae
45701  *
45702  * When this bit is enabled, the address filter block uses the 37th MAC address for
45703  * perfect filtering. When this bit is disabled, the address filter block ignores
45704  * the address for filtering.
45705  *
45706  * Field Enumeration Values:
45707  *
45708  * Enum | Value | Description
45709  * :----------------------------------------|:------|:--------------------------------------
45710  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
45711  * ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
45712  *
45713  * Field Access Macros:
45714  *
45715  */
45716 /*
45717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
45718  *
45719  * Second MAC address filtering disabled
45720  */
45721 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD 0x0
45722 /*
45723  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
45724  *
45725  * Second MAC address filtering enabled
45726  */
45727 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END 0x1
45728 
45729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
45730 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_LSB 31
45731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
45732 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_MSB 31
45733 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
45734 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_WIDTH 1
45735 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
45736 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET_MSK 0x80000000
45737 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
45738 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_CLR_MSK 0x7fffffff
45739 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
45740 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_RESET 0x0
45741 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE field value from a register. */
45742 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
45743 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value suitable for setting the register. */
45744 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
45745 
45746 #ifndef __ASSEMBLY__
45747 /*
45748  * WARNING: The C register and register group struct declarations are provided for
45749  * convenience and illustrative purposes. They should, however, be used with
45750  * caution as the C language standard provides no guarantees about the alignment or
45751  * atomicity of device memory accesses. The recommended practice for writing
45752  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45753  * alt_write_word() functions.
45754  *
45755  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH.
45756  */
45757 struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s
45758 {
45759  uint32_t addrhi : 16; /* MAC Address36 [47:32] */
45760  uint32_t : 8; /* *UNDEFINED* */
45761  uint32_t mbc_0 : 1; /* Mask Byte Control */
45762  uint32_t mbc_1 : 1; /* Mask Byte Control */
45763  uint32_t mbc_2 : 1; /* Mask Byte Control */
45764  uint32_t mbc_3 : 1; /* Mask Byte Control */
45765  uint32_t mbc_4 : 1; /* Mask Byte Control */
45766  uint32_t mbc_5 : 1; /* Mask Byte Control */
45767  uint32_t sa : 1; /* Source Address */
45768  uint32_t ae : 1; /* Address Enable */
45769 };
45770 
45771 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH. */
45772 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t;
45773 #endif /* __ASSEMBLY__ */
45774 
45775 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register from the beginning of the component. */
45776 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST 0x8a0
45777 /* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register. */
45778 #define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST))
45779 
45780 /*
45781  * Register : Register 553 (MAC Address36 Low Register) - MAC_Address36_Low
45782  *
45783  * The MAC Address36 Low register holds the lower 32 bits of the 37th 6-byte MAC
45784  * address of the station.
45785  *
45786  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
45787  * format.
45788  *
45789  * Register Layout
45790  *
45791  * Bits | Access | Reset | Description
45792  * :-------|:-------|:-----------|:---------------------
45793  * [31:0] | RW | 0xffffffff | MAC Address36 [31:0]
45794  *
45795  */
45796 /*
45797  * Field : MAC Address36 [31:0] - addrlo
45798  *
45799  * This field contains the lower 32 bits of the 37th 6-byte MAC address. The
45800  * content of this field is undefined until loaded by software after the
45801  * initialization process.
45802  *
45803  * Field Access Macros:
45804  *
45805  */
45806 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
45807 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_LSB 0
45808 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
45809 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_MSB 31
45810 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
45811 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_WIDTH 32
45812 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
45813 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET_MSK 0xffffffff
45814 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
45815 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_CLR_MSK 0x00000000
45816 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
45817 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_RESET 0xffffffff
45818 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO field value from a register. */
45819 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
45820 /* Produces a ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value suitable for setting the register. */
45821 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
45822 
45823 #ifndef __ASSEMBLY__
45824 /*
45825  * WARNING: The C register and register group struct declarations are provided for
45826  * convenience and illustrative purposes. They should, however, be used with
45827  * caution as the C language standard provides no guarantees about the alignment or
45828  * atomicity of device memory accesses. The recommended practice for writing
45829  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
45830  * alt_write_word() functions.
45831  *
45832  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW.
45833  */
45834 struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s
45835 {
45836  uint32_t addrlo : 32; /* MAC Address36 [31:0] */
45837 };
45838 
45839 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW. */
45840 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s ALT_EMAC_GMAC_MAC_ADDR36_LOW_t;
45841 #endif /* __ASSEMBLY__ */
45842 
45843 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register from the beginning of the component. */
45844 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST 0x8a4
45845 /* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register. */
45846 #define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST))
45847 
45848 /*
45849  * Register : Register 554 (MAC Address37 High Register) - MAC_Address37_High
45850  *
45851  * The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC
45852  * address of the station. Because the MAC address registers are configured to be
45853  * double-synchronized to the (G)MII clock domains, the synchronization is
45854  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
45855  * endian mode) of the MAC Address37 Low Register are written. For proper
45856  * synchronization updates, the consecutive writes to this Address Low Register
45857  * should be performed after at least four clock cycles in the destination clock
45858  * domain.
45859  *
45860  * Note that all MAC Address High registers (except MAC Address0 High) have the
45861  * same format.
45862  *
45863  * Register Layout
45864  *
45865  * Bits | Access | Reset | Description
45866  * :--------|:-------|:-------|:----------------------
45867  * [15:0] | RW | 0xffff | MAC Address37 [47:32]
45868  * [23:16] | ??? | 0x0 | *UNDEFINED*
45869  * [24] | RW | 0x0 | Mask Byte Control
45870  * [25] | RW | 0x0 | Mask Byte Control
45871  * [26] | RW | 0x0 | Mask Byte Control
45872  * [27] | RW | 0x0 | Mask Byte Control
45873  * [28] | RW | 0x0 | Mask Byte Control
45874  * [29] | RW | 0x0 | Mask Byte Control
45875  * [30] | RW | 0x0 | Source Address
45876  * [31] | RW | 0x0 | Address Enable
45877  *
45878  */
45879 /*
45880  * Field : MAC Address37 [47:32] - addrhi
45881  *
45882  * This field contains the upper 16 bits (47:32) of the 38th 6-byte MAC address.
45883  *
45884  * Field Access Macros:
45885  *
45886  */
45887 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
45888 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_LSB 0
45889 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
45890 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_MSB 15
45891 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
45892 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_WIDTH 16
45893 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
45894 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET_MSK 0x0000ffff
45895 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
45896 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_CLR_MSK 0xffff0000
45897 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
45898 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_RESET 0xffff
45899 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI field value from a register. */
45900 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
45901 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value suitable for setting the register. */
45902 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
45903 
45904 /*
45905  * Field : Mask Byte Control - mbc_0
45906  *
45907  * This array of bits are mask control bits for comparison of each of the MAC
45908  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45909  * received DA or SA with the contents of MAC Address37 high and low registers.
45910  * Each bit controls the masking of the bytes. You can filter a group of addresses
45911  * (known as group address filtering) by masking one or more bytes of the address.
45912  *
45913  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45914  *
45915  * Field Enumeration Values:
45916  *
45917  * Enum | Value | Description
45918  * :----------------------------------------------|:------|:------------------------------------
45919  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45920  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45921  *
45922  * Field Access Macros:
45923  *
45924  */
45925 /*
45926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0
45927  *
45928  * Byte is unmasked (i.e. is compared)
45929  */
45930 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED 0x0
45931 /*
45932  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0
45933  *
45934  * Byte is masked (i.e. not compared)
45935  */
45936 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED 0x1
45937 
45938 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
45939 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_LSB 24
45940 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
45941 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_MSB 24
45942 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
45943 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_WIDTH 1
45944 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */
45945 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET_MSK 0x01000000
45946 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */
45947 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_CLR_MSK 0xfeffffff
45948 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
45949 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_RESET 0x0
45950 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 field value from a register. */
45951 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
45952 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value suitable for setting the register. */
45953 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
45954 
45955 /*
45956  * Field : Mask Byte Control - mbc_1
45957  *
45958  * This array of bits are mask control bits for comparison of each of the MAC
45959  * Address bytes. When masked, the MAC does not compare the corresponding byte of
45960  * received DA or SA with the contents of MAC Address37 high and low registers.
45961  * Each bit controls the masking of the bytes. You can filter a group of addresses
45962  * (known as group address filtering) by masking one or more bytes of the address.
45963  *
45964  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
45965  *
45966  * Field Enumeration Values:
45967  *
45968  * Enum | Value | Description
45969  * :----------------------------------------------|:------|:------------------------------------
45970  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
45971  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
45972  *
45973  * Field Access Macros:
45974  *
45975  */
45976 /*
45977  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1
45978  *
45979  * Byte is unmasked (i.e. is compared)
45980  */
45981 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED 0x0
45982 /*
45983  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1
45984  *
45985  * Byte is masked (i.e. not compared)
45986  */
45987 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED 0x1
45988 
45989 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
45990 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_LSB 25
45991 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
45992 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_MSB 25
45993 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
45994 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_WIDTH 1
45995 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */
45996 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET_MSK 0x02000000
45997 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */
45998 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_CLR_MSK 0xfdffffff
45999 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
46000 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_RESET 0x0
46001 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 field value from a register. */
46002 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
46003 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value suitable for setting the register. */
46004 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
46005 
46006 /*
46007  * Field : Mask Byte Control - mbc_2
46008  *
46009  * This array of bits are mask control bits for comparison of each of the MAC
46010  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46011  * received DA or SA with the contents of MAC Address37 high and low registers.
46012  * Each bit controls the masking of the bytes. You can filter a group of addresses
46013  * (known as group address filtering) by masking one or more bytes of the address.
46014  *
46015  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46016  *
46017  * Field Enumeration Values:
46018  *
46019  * Enum | Value | Description
46020  * :----------------------------------------------|:------|:------------------------------------
46021  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46022  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46023  *
46024  * Field Access Macros:
46025  *
46026  */
46027 /*
46028  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2
46029  *
46030  * Byte is unmasked (i.e. is compared)
46031  */
46032 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED 0x0
46033 /*
46034  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2
46035  *
46036  * Byte is masked (i.e. not compared)
46037  */
46038 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED 0x1
46039 
46040 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
46041 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_LSB 26
46042 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
46043 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_MSB 26
46044 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
46045 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_WIDTH 1
46046 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */
46047 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET_MSK 0x04000000
46048 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */
46049 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_CLR_MSK 0xfbffffff
46050 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
46051 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_RESET 0x0
46052 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 field value from a register. */
46053 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
46054 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value suitable for setting the register. */
46055 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
46056 
46057 /*
46058  * Field : Mask Byte Control - mbc_3
46059  *
46060  * This array of bits are mask control bits for comparison of each of the MAC
46061  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46062  * received DA or SA with the contents of MAC Address37 high and low registers.
46063  * Each bit controls the masking of the bytes. You can filter a group of addresses
46064  * (known as group address filtering) by masking one or more bytes of the address.
46065  *
46066  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46067  *
46068  * Field Enumeration Values:
46069  *
46070  * Enum | Value | Description
46071  * :----------------------------------------------|:------|:------------------------------------
46072  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46073  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46074  *
46075  * Field Access Macros:
46076  *
46077  */
46078 /*
46079  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3
46080  *
46081  * Byte is unmasked (i.e. is compared)
46082  */
46083 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED 0x0
46084 /*
46085  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3
46086  *
46087  * Byte is masked (i.e. not compared)
46088  */
46089 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED 0x1
46090 
46091 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
46092 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_LSB 27
46093 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
46094 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_MSB 27
46095 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
46096 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_WIDTH 1
46097 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */
46098 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET_MSK 0x08000000
46099 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */
46100 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_CLR_MSK 0xf7ffffff
46101 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
46102 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_RESET 0x0
46103 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 field value from a register. */
46104 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
46105 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value suitable for setting the register. */
46106 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
46107 
46108 /*
46109  * Field : Mask Byte Control - mbc_4
46110  *
46111  * This array of bits are mask control bits for comparison of each of the MAC
46112  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46113  * received DA or SA with the contents of MAC Address37 high and low registers.
46114  * Each bit controls the masking of the bytes. You can filter a group of addresses
46115  * (known as group address filtering) by masking one or more bytes of the address.
46116  *
46117  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46118  *
46119  * Field Enumeration Values:
46120  *
46121  * Enum | Value | Description
46122  * :----------------------------------------------|:------|:------------------------------------
46123  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46124  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46125  *
46126  * Field Access Macros:
46127  *
46128  */
46129 /*
46130  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4
46131  *
46132  * Byte is unmasked (i.e. is compared)
46133  */
46134 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED 0x0
46135 /*
46136  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4
46137  *
46138  * Byte is masked (i.e. not compared)
46139  */
46140 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED 0x1
46141 
46142 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
46143 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_LSB 28
46144 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
46145 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_MSB 28
46146 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
46147 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_WIDTH 1
46148 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */
46149 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET_MSK 0x10000000
46150 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */
46151 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_CLR_MSK 0xefffffff
46152 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
46153 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_RESET 0x0
46154 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 field value from a register. */
46155 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
46156 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value suitable for setting the register. */
46157 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
46158 
46159 /*
46160  * Field : Mask Byte Control - mbc_5
46161  *
46162  * This array of bits are mask control bits for comparison of each of the MAC
46163  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46164  * received DA or SA with the contents of MAC Address37 high and low registers.
46165  * Each bit controls the masking of the bytes. You can filter a group of addresses
46166  * (known as group address filtering) by masking one or more bytes of the address.
46167  *
46168  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46169  *
46170  * Field Enumeration Values:
46171  *
46172  * Enum | Value | Description
46173  * :----------------------------------------------|:------|:------------------------------------
46174  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46175  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46176  *
46177  * Field Access Macros:
46178  *
46179  */
46180 /*
46181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5
46182  *
46183  * Byte is unmasked (i.e. is compared)
46184  */
46185 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED 0x0
46186 /*
46187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5
46188  *
46189  * Byte is masked (i.e. not compared)
46190  */
46191 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED 0x1
46192 
46193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
46194 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_LSB 29
46195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
46196 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_MSB 29
46197 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
46198 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_WIDTH 1
46199 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */
46200 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET_MSK 0x20000000
46201 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */
46202 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_CLR_MSK 0xdfffffff
46203 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
46204 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_RESET 0x0
46205 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 field value from a register. */
46206 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
46207 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value suitable for setting the register. */
46208 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
46209 
46210 /*
46211  * Field : Source Address - sa
46212  *
46213  * When this bit is enabled, the MAC Address37[47:0] is used to compare with the SA
46214  * fields of the received frame. When this bit is disabled, the MAC Address37[47:0]
46215  * is used to compare with the DA fields of the received frame.
46216  *
46217  * Field Enumeration Values:
46218  *
46219  * Enum | Value | Description
46220  * :----------------------------------------|:------|:-----------------------------
46221  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
46222  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END | 0x1 | MAC address compare enabled
46223  *
46224  * Field Access Macros:
46225  *
46226  */
46227 /*
46228  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA
46229  *
46230  * MAC address compare disabled
46231  */
46232 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD 0x0
46233 /*
46234  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA
46235  *
46236  * MAC address compare enabled
46237  */
46238 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END 0x1
46239 
46240 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
46241 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_LSB 30
46242 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
46243 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_MSB 30
46244 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
46245 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_WIDTH 1
46246 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */
46247 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET_MSK 0x40000000
46248 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */
46249 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_CLR_MSK 0xbfffffff
46250 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
46251 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_RESET 0x0
46252 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA field value from a register. */
46253 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
46254 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value suitable for setting the register. */
46255 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
46256 
46257 /*
46258  * Field : Address Enable - ae
46259  *
46260  * When this bit is enabled, the address filter block uses the 38th MAC address for
46261  * perfect filtering. When this bit is disabled, the address filter block ignores
46262  * the address for filtering.
46263  *
46264  * Field Enumeration Values:
46265  *
46266  * Enum | Value | Description
46267  * :----------------------------------------|:------|:--------------------------------------
46268  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
46269  * ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
46270  *
46271  * Field Access Macros:
46272  *
46273  */
46274 /*
46275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
46276  *
46277  * Second MAC address filtering disabled
46278  */
46279 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD 0x0
46280 /*
46281  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
46282  *
46283  * Second MAC address filtering enabled
46284  */
46285 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END 0x1
46286 
46287 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
46288 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_LSB 31
46289 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
46290 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_MSB 31
46291 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
46292 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_WIDTH 1
46293 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
46294 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET_MSK 0x80000000
46295 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
46296 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_CLR_MSK 0x7fffffff
46297 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
46298 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_RESET 0x0
46299 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE field value from a register. */
46300 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46301 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value suitable for setting the register. */
46302 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46303 
46304 #ifndef __ASSEMBLY__
46305 /*
46306  * WARNING: The C register and register group struct declarations are provided for
46307  * convenience and illustrative purposes. They should, however, be used with
46308  * caution as the C language standard provides no guarantees about the alignment or
46309  * atomicity of device memory accesses. The recommended practice for writing
46310  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46311  * alt_write_word() functions.
46312  *
46313  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH.
46314  */
46315 struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s
46316 {
46317  uint32_t addrhi : 16; /* MAC Address37 [47:32] */
46318  uint32_t : 8; /* *UNDEFINED* */
46319  uint32_t mbc_0 : 1; /* Mask Byte Control */
46320  uint32_t mbc_1 : 1; /* Mask Byte Control */
46321  uint32_t mbc_2 : 1; /* Mask Byte Control */
46322  uint32_t mbc_3 : 1; /* Mask Byte Control */
46323  uint32_t mbc_4 : 1; /* Mask Byte Control */
46324  uint32_t mbc_5 : 1; /* Mask Byte Control */
46325  uint32_t sa : 1; /* Source Address */
46326  uint32_t ae : 1; /* Address Enable */
46327 };
46328 
46329 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH. */
46330 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t;
46331 #endif /* __ASSEMBLY__ */
46332 
46333 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register from the beginning of the component. */
46334 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST 0x8a8
46335 /* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register. */
46336 #define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST))
46337 
46338 /*
46339  * Register : Register 555 (MAC Address37 Low Register) - MAC_Address37_Low
46340  *
46341  * The MAC Address37 Low register holds the lower 32 bits of the 38th 6-byte MAC
46342  * address of the station.
46343  *
46344  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
46345  * format.
46346  *
46347  * Register Layout
46348  *
46349  * Bits | Access | Reset | Description
46350  * :-------|:-------|:-----------|:---------------------
46351  * [31:0] | RW | 0xffffffff | MAC Address37 [31:0]
46352  *
46353  */
46354 /*
46355  * Field : MAC Address37 [31:0] - addrlo
46356  *
46357  * This field contains the lower 32 bits of the 38th 6-byte MAC address. The
46358  * content of this field is undefined until loaded by software after the
46359  * initialization process.
46360  *
46361  * Field Access Macros:
46362  *
46363  */
46364 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
46365 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_LSB 0
46366 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
46367 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_MSB 31
46368 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
46369 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_WIDTH 32
46370 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
46371 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET_MSK 0xffffffff
46372 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
46373 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_CLR_MSK 0x00000000
46374 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
46375 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_RESET 0xffffffff
46376 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO field value from a register. */
46377 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46378 /* Produces a ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value suitable for setting the register. */
46379 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46380 
46381 #ifndef __ASSEMBLY__
46382 /*
46383  * WARNING: The C register and register group struct declarations are provided for
46384  * convenience and illustrative purposes. They should, however, be used with
46385  * caution as the C language standard provides no guarantees about the alignment or
46386  * atomicity of device memory accesses. The recommended practice for writing
46387  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46388  * alt_write_word() functions.
46389  *
46390  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW.
46391  */
46392 struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s
46393 {
46394  uint32_t addrlo : 32; /* MAC Address37 [31:0] */
46395 };
46396 
46397 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW. */
46398 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s ALT_EMAC_GMAC_MAC_ADDR37_LOW_t;
46399 #endif /* __ASSEMBLY__ */
46400 
46401 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register from the beginning of the component. */
46402 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST 0x8ac
46403 /* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register. */
46404 #define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST))
46405 
46406 /*
46407  * Register : Register 556 (MAC Address38 High Register) - MAC_Address38_High
46408  *
46409  * The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC
46410  * address of the station. Because the MAC address registers are configured to be
46411  * double-synchronized to the (G)MII clock domains, the synchronization is
46412  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
46413  * endian mode) of the MAC Address38 Low Register are written. For proper
46414  * synchronization updates, the consecutive writes to this Address Low Register
46415  * should be performed after at least four clock cycles in the destination clock
46416  * domain.
46417  *
46418  * Note that all MAC Address High registers (except MAC Address0 High) have the
46419  * same format.
46420  *
46421  * Register Layout
46422  *
46423  * Bits | Access | Reset | Description
46424  * :--------|:-------|:-------|:----------------------
46425  * [15:0] | RW | 0xffff | MAC Address38 [47:32]
46426  * [23:16] | ??? | 0x0 | *UNDEFINED*
46427  * [24] | RW | 0x0 | Mask Byte Control
46428  * [25] | RW | 0x0 | Mask Byte Control
46429  * [26] | RW | 0x0 | Mask Byte Control
46430  * [27] | RW | 0x0 | Mask Byte Control
46431  * [28] | RW | 0x0 | Mask Byte Control
46432  * [29] | RW | 0x0 | Mask Byte Control
46433  * [30] | RW | 0x0 | Source Address
46434  * [31] | RW | 0x0 | Address Enable
46435  *
46436  */
46437 /*
46438  * Field : MAC Address38 [47:32] - addrhi
46439  *
46440  * This field contains the upper 16 bits (47:32) of the 39th 6-byte MAC address.
46441  *
46442  * Field Access Macros:
46443  *
46444  */
46445 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
46446 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_LSB 0
46447 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
46448 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_MSB 15
46449 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
46450 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_WIDTH 16
46451 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
46452 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET_MSK 0x0000ffff
46453 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
46454 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_CLR_MSK 0xffff0000
46455 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
46456 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_RESET 0xffff
46457 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI field value from a register. */
46458 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
46459 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value suitable for setting the register. */
46460 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
46461 
46462 /*
46463  * Field : Mask Byte Control - mbc_0
46464  *
46465  * This array of bits are mask control bits for comparison of each of the MAC
46466  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46467  * received DA or SA with the contents of MAC Address38 high and low registers.
46468  * Each bit controls the masking of the bytes. You can filter a group of addresses
46469  * (known as group address filtering) by masking one or more bytes of the address.
46470  *
46471  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46472  *
46473  * Field Enumeration Values:
46474  *
46475  * Enum | Value | Description
46476  * :----------------------------------------------|:------|:------------------------------------
46477  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46478  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46479  *
46480  * Field Access Macros:
46481  *
46482  */
46483 /*
46484  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0
46485  *
46486  * Byte is unmasked (i.e. is compared)
46487  */
46488 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED 0x0
46489 /*
46490  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0
46491  *
46492  * Byte is masked (i.e. not compared)
46493  */
46494 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED 0x1
46495 
46496 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
46497 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_LSB 24
46498 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
46499 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_MSB 24
46500 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
46501 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_WIDTH 1
46502 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */
46503 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET_MSK 0x01000000
46504 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */
46505 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_CLR_MSK 0xfeffffff
46506 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
46507 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_RESET 0x0
46508 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 field value from a register. */
46509 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
46510 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value suitable for setting the register. */
46511 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
46512 
46513 /*
46514  * Field : Mask Byte Control - mbc_1
46515  *
46516  * This array of bits are mask control bits for comparison of each of the MAC
46517  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46518  * received DA or SA with the contents of MAC Address38 high and low registers.
46519  * Each bit controls the masking of the bytes. You can filter a group of addresses
46520  * (known as group address filtering) by masking one or more bytes of the address.
46521  *
46522  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46523  *
46524  * Field Enumeration Values:
46525  *
46526  * Enum | Value | Description
46527  * :----------------------------------------------|:------|:------------------------------------
46528  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46529  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46530  *
46531  * Field Access Macros:
46532  *
46533  */
46534 /*
46535  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1
46536  *
46537  * Byte is unmasked (i.e. is compared)
46538  */
46539 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED 0x0
46540 /*
46541  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1
46542  *
46543  * Byte is masked (i.e. not compared)
46544  */
46545 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED 0x1
46546 
46547 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
46548 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_LSB 25
46549 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
46550 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_MSB 25
46551 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
46552 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_WIDTH 1
46553 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */
46554 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET_MSK 0x02000000
46555 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */
46556 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_CLR_MSK 0xfdffffff
46557 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
46558 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_RESET 0x0
46559 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 field value from a register. */
46560 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
46561 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value suitable for setting the register. */
46562 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
46563 
46564 /*
46565  * Field : Mask Byte Control - mbc_2
46566  *
46567  * This array of bits are mask control bits for comparison of each of the MAC
46568  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46569  * received DA or SA with the contents of MAC Address38 high and low registers.
46570  * Each bit controls the masking of the bytes. You can filter a group of addresses
46571  * (known as group address filtering) by masking one or more bytes of the address.
46572  *
46573  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46574  *
46575  * Field Enumeration Values:
46576  *
46577  * Enum | Value | Description
46578  * :----------------------------------------------|:------|:------------------------------------
46579  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46580  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46581  *
46582  * Field Access Macros:
46583  *
46584  */
46585 /*
46586  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2
46587  *
46588  * Byte is unmasked (i.e. is compared)
46589  */
46590 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED 0x0
46591 /*
46592  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2
46593  *
46594  * Byte is masked (i.e. not compared)
46595  */
46596 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED 0x1
46597 
46598 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
46599 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_LSB 26
46600 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
46601 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_MSB 26
46602 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
46603 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_WIDTH 1
46604 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */
46605 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET_MSK 0x04000000
46606 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */
46607 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_CLR_MSK 0xfbffffff
46608 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
46609 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_RESET 0x0
46610 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 field value from a register. */
46611 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
46612 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value suitable for setting the register. */
46613 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
46614 
46615 /*
46616  * Field : Mask Byte Control - mbc_3
46617  *
46618  * This array of bits are mask control bits for comparison of each of the MAC
46619  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46620  * received DA or SA with the contents of MAC Address38 high and low registers.
46621  * Each bit controls the masking of the bytes. You can filter a group of addresses
46622  * (known as group address filtering) by masking one or more bytes of the address.
46623  *
46624  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46625  *
46626  * Field Enumeration Values:
46627  *
46628  * Enum | Value | Description
46629  * :----------------------------------------------|:------|:------------------------------------
46630  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46631  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46632  *
46633  * Field Access Macros:
46634  *
46635  */
46636 /*
46637  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3
46638  *
46639  * Byte is unmasked (i.e. is compared)
46640  */
46641 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED 0x0
46642 /*
46643  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3
46644  *
46645  * Byte is masked (i.e. not compared)
46646  */
46647 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED 0x1
46648 
46649 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
46650 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_LSB 27
46651 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
46652 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_MSB 27
46653 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
46654 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_WIDTH 1
46655 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */
46656 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET_MSK 0x08000000
46657 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */
46658 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_CLR_MSK 0xf7ffffff
46659 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
46660 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_RESET 0x0
46661 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 field value from a register. */
46662 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
46663 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value suitable for setting the register. */
46664 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
46665 
46666 /*
46667  * Field : Mask Byte Control - mbc_4
46668  *
46669  * This array of bits are mask control bits for comparison of each of the MAC
46670  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46671  * received DA or SA with the contents of MAC Address38 high and low registers.
46672  * Each bit controls the masking of the bytes. You can filter a group of addresses
46673  * (known as group address filtering) by masking one or more bytes of the address.
46674  *
46675  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46676  *
46677  * Field Enumeration Values:
46678  *
46679  * Enum | Value | Description
46680  * :----------------------------------------------|:------|:------------------------------------
46681  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46682  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46683  *
46684  * Field Access Macros:
46685  *
46686  */
46687 /*
46688  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4
46689  *
46690  * Byte is unmasked (i.e. is compared)
46691  */
46692 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED 0x0
46693 /*
46694  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4
46695  *
46696  * Byte is masked (i.e. not compared)
46697  */
46698 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED 0x1
46699 
46700 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
46701 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_LSB 28
46702 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
46703 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_MSB 28
46704 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
46705 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_WIDTH 1
46706 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */
46707 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET_MSK 0x10000000
46708 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */
46709 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_CLR_MSK 0xefffffff
46710 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
46711 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_RESET 0x0
46712 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 field value from a register. */
46713 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
46714 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value suitable for setting the register. */
46715 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
46716 
46717 /*
46718  * Field : Mask Byte Control - mbc_5
46719  *
46720  * This array of bits are mask control bits for comparison of each of the MAC
46721  * Address bytes. When masked, the MAC does not compare the corresponding byte of
46722  * received DA or SA with the contents of MAC Address38 high and low registers.
46723  * Each bit controls the masking of the bytes. You can filter a group of addresses
46724  * (known as group address filtering) by masking one or more bytes of the address.
46725  *
46726  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
46727  *
46728  * Field Enumeration Values:
46729  *
46730  * Enum | Value | Description
46731  * :----------------------------------------------|:------|:------------------------------------
46732  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
46733  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
46734  *
46735  * Field Access Macros:
46736  *
46737  */
46738 /*
46739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5
46740  *
46741  * Byte is unmasked (i.e. is compared)
46742  */
46743 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED 0x0
46744 /*
46745  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5
46746  *
46747  * Byte is masked (i.e. not compared)
46748  */
46749 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED 0x1
46750 
46751 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
46752 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_LSB 29
46753 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
46754 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_MSB 29
46755 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
46756 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_WIDTH 1
46757 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */
46758 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET_MSK 0x20000000
46759 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */
46760 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_CLR_MSK 0xdfffffff
46761 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
46762 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_RESET 0x0
46763 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 field value from a register. */
46764 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
46765 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value suitable for setting the register. */
46766 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
46767 
46768 /*
46769  * Field : Source Address - sa
46770  *
46771  * When this bit is enabled, the MAC Address38[47:0] is used to compare with the SA
46772  * fields of the received frame. When this bit is disabled, the MAC Address38[47:0]
46773  * is used to compare with the DA fields of the received frame.
46774  *
46775  * Field Enumeration Values:
46776  *
46777  * Enum | Value | Description
46778  * :----------------------------------------|:------|:-----------------------------
46779  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
46780  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END | 0x1 | MAC address compare enabled
46781  *
46782  * Field Access Macros:
46783  *
46784  */
46785 /*
46786  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA
46787  *
46788  * MAC address compare disabled
46789  */
46790 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD 0x0
46791 /*
46792  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA
46793  *
46794  * MAC address compare enabled
46795  */
46796 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END 0x1
46797 
46798 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
46799 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_LSB 30
46800 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
46801 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_MSB 30
46802 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
46803 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_WIDTH 1
46804 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */
46805 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET_MSK 0x40000000
46806 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */
46807 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_CLR_MSK 0xbfffffff
46808 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
46809 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_RESET 0x0
46810 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA field value from a register. */
46811 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
46812 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value suitable for setting the register. */
46813 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
46814 
46815 /*
46816  * Field : Address Enable - ae
46817  *
46818  * When this bit is enabled, the address filter block uses the 39th MAC address for
46819  * perfect filtering. When this bit is disabled, the address filter block ignores
46820  * the address for filtering.
46821  *
46822  * Field Enumeration Values:
46823  *
46824  * Enum | Value | Description
46825  * :----------------------------------------|:------|:--------------------------------------
46826  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
46827  * ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
46828  *
46829  * Field Access Macros:
46830  *
46831  */
46832 /*
46833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
46834  *
46835  * Second MAC address filtering disabled
46836  */
46837 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD 0x0
46838 /*
46839  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
46840  *
46841  * Second MAC address filtering enabled
46842  */
46843 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END 0x1
46844 
46845 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
46846 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_LSB 31
46847 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
46848 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_MSB 31
46849 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
46850 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_WIDTH 1
46851 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
46852 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET_MSK 0x80000000
46853 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
46854 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_CLR_MSK 0x7fffffff
46855 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
46856 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_RESET 0x0
46857 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE field value from a register. */
46858 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
46859 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value suitable for setting the register. */
46860 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
46861 
46862 #ifndef __ASSEMBLY__
46863 /*
46864  * WARNING: The C register and register group struct declarations are provided for
46865  * convenience and illustrative purposes. They should, however, be used with
46866  * caution as the C language standard provides no guarantees about the alignment or
46867  * atomicity of device memory accesses. The recommended practice for writing
46868  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46869  * alt_write_word() functions.
46870  *
46871  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH.
46872  */
46873 struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s
46874 {
46875  uint32_t addrhi : 16; /* MAC Address38 [47:32] */
46876  uint32_t : 8; /* *UNDEFINED* */
46877  uint32_t mbc_0 : 1; /* Mask Byte Control */
46878  uint32_t mbc_1 : 1; /* Mask Byte Control */
46879  uint32_t mbc_2 : 1; /* Mask Byte Control */
46880  uint32_t mbc_3 : 1; /* Mask Byte Control */
46881  uint32_t mbc_4 : 1; /* Mask Byte Control */
46882  uint32_t mbc_5 : 1; /* Mask Byte Control */
46883  uint32_t sa : 1; /* Source Address */
46884  uint32_t ae : 1; /* Address Enable */
46885 };
46886 
46887 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH. */
46888 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t;
46889 #endif /* __ASSEMBLY__ */
46890 
46891 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register from the beginning of the component. */
46892 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST 0x8b0
46893 /* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register. */
46894 #define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST))
46895 
46896 /*
46897  * Register : Register 557 (MAC Address38 Low Register) - MAC_Address38_Low
46898  *
46899  * The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC
46900  * address of the station.
46901  *
46902  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
46903  * format.
46904  *
46905  * Register Layout
46906  *
46907  * Bits | Access | Reset | Description
46908  * :-------|:-------|:-----------|:---------------------
46909  * [31:0] | RW | 0xffffffff | MAC Address38 [31:0]
46910  *
46911  */
46912 /*
46913  * Field : MAC Address38 [31:0] - addrlo
46914  *
46915  * This field contains the lower 32 bits of the 39th 6-byte MAC address. The
46916  * content of this field is undefined until loaded by software after the
46917  * initialization process.
46918  *
46919  * Field Access Macros:
46920  *
46921  */
46922 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
46923 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_LSB 0
46924 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
46925 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_MSB 31
46926 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
46927 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_WIDTH 32
46928 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
46929 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET_MSK 0xffffffff
46930 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
46931 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_CLR_MSK 0x00000000
46932 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
46933 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_RESET 0xffffffff
46934 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO field value from a register. */
46935 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
46936 /* Produces a ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value suitable for setting the register. */
46937 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
46938 
46939 #ifndef __ASSEMBLY__
46940 /*
46941  * WARNING: The C register and register group struct declarations are provided for
46942  * convenience and illustrative purposes. They should, however, be used with
46943  * caution as the C language standard provides no guarantees about the alignment or
46944  * atomicity of device memory accesses. The recommended practice for writing
46945  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
46946  * alt_write_word() functions.
46947  *
46948  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW.
46949  */
46950 struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s
46951 {
46952  uint32_t addrlo : 32; /* MAC Address38 [31:0] */
46953 };
46954 
46955 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW. */
46956 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s ALT_EMAC_GMAC_MAC_ADDR38_LOW_t;
46957 #endif /* __ASSEMBLY__ */
46958 
46959 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register from the beginning of the component. */
46960 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST 0x8b4
46961 /* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register. */
46962 #define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST))
46963 
46964 /*
46965  * Register : Register 558 (MAC Address39 High Register) - MAC_Address39_High
46966  *
46967  * The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC
46968  * address of the station. Because the MAC address registers are configured to be
46969  * double-synchronized to the (G)MII clock domains, the synchronization is
46970  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
46971  * endian mode) of the MAC Address39 Low Register are written. For proper
46972  * synchronization updates, the consecutive writes to this Address Low Register
46973  * should be performed after at least four clock cycles in the destination clock
46974  * domain.
46975  *
46976  * Note that all MAC Address High registers (except MAC Address0 High) have the
46977  * same format.
46978  *
46979  * Register Layout
46980  *
46981  * Bits | Access | Reset | Description
46982  * :--------|:-------|:-------|:----------------------
46983  * [15:0] | RW | 0xffff | MAC Address39 [47:32]
46984  * [23:16] | ??? | 0x0 | *UNDEFINED*
46985  * [24] | RW | 0x0 | Mask Byte Control
46986  * [25] | RW | 0x0 | Mask Byte Control
46987  * [26] | RW | 0x0 | Mask Byte Control
46988  * [27] | RW | 0x0 | Mask Byte Control
46989  * [28] | RW | 0x0 | Mask Byte Control
46990  * [29] | RW | 0x0 | Mask Byte Control
46991  * [30] | RW | 0x0 | Source Address
46992  * [31] | RW | 0x0 | Address Enable
46993  *
46994  */
46995 /*
46996  * Field : MAC Address39 [47:32] - addrhi
46997  *
46998  * This field contains the upper 16 bits (47:32) of the 40th 6-byte MAC address.
46999  *
47000  * Field Access Macros:
47001  *
47002  */
47003 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47004 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_LSB 0
47005 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47006 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_MSB 15
47007 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47008 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_WIDTH 16
47009 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
47010 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET_MSK 0x0000ffff
47011 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
47012 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_CLR_MSK 0xffff0000
47013 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
47014 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_RESET 0xffff
47015 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI field value from a register. */
47016 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47017 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value suitable for setting the register. */
47018 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47019 
47020 /*
47021  * Field : Mask Byte Control - mbc_0
47022  *
47023  * This array of bits are mask control bits for comparison of each of the MAC
47024  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47025  * received DA or SA with the contents of MAC Address39 high and low registers.
47026  * Each bit controls the masking of the bytes. You can filter a group of addresses
47027  * (known as group address filtering) by masking one or more bytes of the address.
47028  *
47029  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47030  *
47031  * Field Enumeration Values:
47032  *
47033  * Enum | Value | Description
47034  * :----------------------------------------------|:------|:------------------------------------
47035  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47036  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47037  *
47038  * Field Access Macros:
47039  *
47040  */
47041 /*
47042  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0
47043  *
47044  * Byte is unmasked (i.e. is compared)
47045  */
47046 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED 0x0
47047 /*
47048  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0
47049  *
47050  * Byte is masked (i.e. not compared)
47051  */
47052 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED 0x1
47053 
47054 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
47055 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_LSB 24
47056 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
47057 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_MSB 24
47058 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
47059 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_WIDTH 1
47060 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */
47061 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET_MSK 0x01000000
47062 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */
47063 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_CLR_MSK 0xfeffffff
47064 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
47065 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_RESET 0x0
47066 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 field value from a register. */
47067 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
47068 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value suitable for setting the register. */
47069 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
47070 
47071 /*
47072  * Field : Mask Byte Control - mbc_1
47073  *
47074  * This array of bits are mask control bits for comparison of each of the MAC
47075  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47076  * received DA or SA with the contents of MAC Address39 high and low registers.
47077  * Each bit controls the masking of the bytes. You can filter a group of addresses
47078  * (known as group address filtering) by masking one or more bytes of the address.
47079  *
47080  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47081  *
47082  * Field Enumeration Values:
47083  *
47084  * Enum | Value | Description
47085  * :----------------------------------------------|:------|:------------------------------------
47086  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47087  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47088  *
47089  * Field Access Macros:
47090  *
47091  */
47092 /*
47093  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1
47094  *
47095  * Byte is unmasked (i.e. is compared)
47096  */
47097 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED 0x0
47098 /*
47099  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1
47100  *
47101  * Byte is masked (i.e. not compared)
47102  */
47103 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED 0x1
47104 
47105 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
47106 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_LSB 25
47107 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
47108 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_MSB 25
47109 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
47110 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_WIDTH 1
47111 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */
47112 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET_MSK 0x02000000
47113 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */
47114 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_CLR_MSK 0xfdffffff
47115 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
47116 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_RESET 0x0
47117 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 field value from a register. */
47118 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
47119 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value suitable for setting the register. */
47120 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
47121 
47122 /*
47123  * Field : Mask Byte Control - mbc_2
47124  *
47125  * This array of bits are mask control bits for comparison of each of the MAC
47126  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47127  * received DA or SA with the contents of MAC Address39 high and low registers.
47128  * Each bit controls the masking of the bytes. You can filter a group of addresses
47129  * (known as group address filtering) by masking one or more bytes of the address.
47130  *
47131  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47132  *
47133  * Field Enumeration Values:
47134  *
47135  * Enum | Value | Description
47136  * :----------------------------------------------|:------|:------------------------------------
47137  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47138  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47139  *
47140  * Field Access Macros:
47141  *
47142  */
47143 /*
47144  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2
47145  *
47146  * Byte is unmasked (i.e. is compared)
47147  */
47148 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED 0x0
47149 /*
47150  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2
47151  *
47152  * Byte is masked (i.e. not compared)
47153  */
47154 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED 0x1
47155 
47156 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
47157 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_LSB 26
47158 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
47159 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_MSB 26
47160 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
47161 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_WIDTH 1
47162 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */
47163 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET_MSK 0x04000000
47164 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */
47165 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_CLR_MSK 0xfbffffff
47166 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
47167 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_RESET 0x0
47168 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 field value from a register. */
47169 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
47170 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value suitable for setting the register. */
47171 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
47172 
47173 /*
47174  * Field : Mask Byte Control - mbc_3
47175  *
47176  * This array of bits are mask control bits for comparison of each of the MAC
47177  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47178  * received DA or SA with the contents of MAC Address39 high and low registers.
47179  * Each bit controls the masking of the bytes. You can filter a group of addresses
47180  * (known as group address filtering) by masking one or more bytes of the address.
47181  *
47182  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47183  *
47184  * Field Enumeration Values:
47185  *
47186  * Enum | Value | Description
47187  * :----------------------------------------------|:------|:------------------------------------
47188  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47189  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47190  *
47191  * Field Access Macros:
47192  *
47193  */
47194 /*
47195  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3
47196  *
47197  * Byte is unmasked (i.e. is compared)
47198  */
47199 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED 0x0
47200 /*
47201  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3
47202  *
47203  * Byte is masked (i.e. not compared)
47204  */
47205 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED 0x1
47206 
47207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
47208 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_LSB 27
47209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
47210 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_MSB 27
47211 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
47212 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_WIDTH 1
47213 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */
47214 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET_MSK 0x08000000
47215 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */
47216 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_CLR_MSK 0xf7ffffff
47217 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
47218 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_RESET 0x0
47219 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 field value from a register. */
47220 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
47221 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value suitable for setting the register. */
47222 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
47223 
47224 /*
47225  * Field : Mask Byte Control - mbc_4
47226  *
47227  * This array of bits are mask control bits for comparison of each of the MAC
47228  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47229  * received DA or SA with the contents of MAC Address39 high and low registers.
47230  * Each bit controls the masking of the bytes. You can filter a group of addresses
47231  * (known as group address filtering) by masking one or more bytes of the address.
47232  *
47233  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47234  *
47235  * Field Enumeration Values:
47236  *
47237  * Enum | Value | Description
47238  * :----------------------------------------------|:------|:------------------------------------
47239  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47240  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47241  *
47242  * Field Access Macros:
47243  *
47244  */
47245 /*
47246  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4
47247  *
47248  * Byte is unmasked (i.e. is compared)
47249  */
47250 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED 0x0
47251 /*
47252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4
47253  *
47254  * Byte is masked (i.e. not compared)
47255  */
47256 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED 0x1
47257 
47258 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
47259 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_LSB 28
47260 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
47261 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_MSB 28
47262 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
47263 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_WIDTH 1
47264 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */
47265 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET_MSK 0x10000000
47266 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */
47267 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_CLR_MSK 0xefffffff
47268 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
47269 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_RESET 0x0
47270 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 field value from a register. */
47271 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
47272 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value suitable for setting the register. */
47273 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
47274 
47275 /*
47276  * Field : Mask Byte Control - mbc_5
47277  *
47278  * This array of bits are mask control bits for comparison of each of the MAC
47279  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47280  * received DA or SA with the contents of MAC Address39 high and low registers.
47281  * Each bit controls the masking of the bytes. You can filter a group of addresses
47282  * (known as group address filtering) by masking one or more bytes of the address.
47283  *
47284  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47285  *
47286  * Field Enumeration Values:
47287  *
47288  * Enum | Value | Description
47289  * :----------------------------------------------|:------|:------------------------------------
47290  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47291  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47292  *
47293  * Field Access Macros:
47294  *
47295  */
47296 /*
47297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5
47298  *
47299  * Byte is unmasked (i.e. is compared)
47300  */
47301 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED 0x0
47302 /*
47303  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5
47304  *
47305  * Byte is masked (i.e. not compared)
47306  */
47307 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED 0x1
47308 
47309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
47310 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_LSB 29
47311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
47312 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_MSB 29
47313 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
47314 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_WIDTH 1
47315 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */
47316 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET_MSK 0x20000000
47317 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */
47318 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_CLR_MSK 0xdfffffff
47319 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
47320 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_RESET 0x0
47321 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 field value from a register. */
47322 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
47323 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value suitable for setting the register. */
47324 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
47325 
47326 /*
47327  * Field : Source Address - sa
47328  *
47329  * When this bit is enabled, the MAC Address39[47:0] is used to compare with the SA
47330  * fields of the received frame. When this bit is disabled, the MAC Address39[47:0]
47331  * is used to compare with the DA fields of the received frame.
47332  *
47333  * Field Enumeration Values:
47334  *
47335  * Enum | Value | Description
47336  * :----------------------------------------|:------|:-----------------------------
47337  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
47338  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END | 0x1 | MAC address compare enabled
47339  *
47340  * Field Access Macros:
47341  *
47342  */
47343 /*
47344  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA
47345  *
47346  * MAC address compare disabled
47347  */
47348 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD 0x0
47349 /*
47350  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA
47351  *
47352  * MAC address compare enabled
47353  */
47354 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END 0x1
47355 
47356 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
47357 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_LSB 30
47358 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
47359 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_MSB 30
47360 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
47361 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_WIDTH 1
47362 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */
47363 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET_MSK 0x40000000
47364 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */
47365 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_CLR_MSK 0xbfffffff
47366 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
47367 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_RESET 0x0
47368 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA field value from a register. */
47369 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
47370 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value suitable for setting the register. */
47371 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
47372 
47373 /*
47374  * Field : Address Enable - ae
47375  *
47376  * When this bit is enabled, the address filter block uses the 40th MAC address for
47377  * perfect filtering. When this bit is disabled, the address filter block ignores
47378  * the address for filtering.
47379  *
47380  * Field Enumeration Values:
47381  *
47382  * Enum | Value | Description
47383  * :----------------------------------------|:------|:--------------------------------------
47384  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
47385  * ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
47386  *
47387  * Field Access Macros:
47388  *
47389  */
47390 /*
47391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
47392  *
47393  * Second MAC address filtering disabled
47394  */
47395 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD 0x0
47396 /*
47397  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
47398  *
47399  * Second MAC address filtering enabled
47400  */
47401 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END 0x1
47402 
47403 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47404 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_LSB 31
47405 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47406 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_MSB 31
47407 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47408 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_WIDTH 1
47409 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
47410 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET_MSK 0x80000000
47411 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
47412 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_CLR_MSK 0x7fffffff
47413 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
47414 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_RESET 0x0
47415 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE field value from a register. */
47416 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47417 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value suitable for setting the register. */
47418 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47419 
47420 #ifndef __ASSEMBLY__
47421 /*
47422  * WARNING: The C register and register group struct declarations are provided for
47423  * convenience and illustrative purposes. They should, however, be used with
47424  * caution as the C language standard provides no guarantees about the alignment or
47425  * atomicity of device memory accesses. The recommended practice for writing
47426  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47427  * alt_write_word() functions.
47428  *
47429  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH.
47430  */
47431 struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s
47432 {
47433  uint32_t addrhi : 16; /* MAC Address39 [47:32] */
47434  uint32_t : 8; /* *UNDEFINED* */
47435  uint32_t mbc_0 : 1; /* Mask Byte Control */
47436  uint32_t mbc_1 : 1; /* Mask Byte Control */
47437  uint32_t mbc_2 : 1; /* Mask Byte Control */
47438  uint32_t mbc_3 : 1; /* Mask Byte Control */
47439  uint32_t mbc_4 : 1; /* Mask Byte Control */
47440  uint32_t mbc_5 : 1; /* Mask Byte Control */
47441  uint32_t sa : 1; /* Source Address */
47442  uint32_t ae : 1; /* Address Enable */
47443 };
47444 
47445 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH. */
47446 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t;
47447 #endif /* __ASSEMBLY__ */
47448 
47449 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register from the beginning of the component. */
47450 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST 0x8b8
47451 /* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register. */
47452 #define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST))
47453 
47454 /*
47455  * Register : Register 559 (MAC Address39 Low Register) - MAC_Address39_Low
47456  *
47457  * The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC
47458  * address of the station.
47459  *
47460  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
47461  * format.
47462  *
47463  * Register Layout
47464  *
47465  * Bits | Access | Reset | Description
47466  * :-------|:-------|:-----------|:---------------------
47467  * [31:0] | RW | 0xffffffff | MAC Address39 [31:0]
47468  *
47469  */
47470 /*
47471  * Field : MAC Address39 [31:0] - addrlo
47472  *
47473  * This field contains the lower 32 bits of the 40th 6-byte MAC address. The
47474  * content of this field is undefined until loaded by software after the
47475  * initialization process.
47476  *
47477  * Field Access Macros:
47478  *
47479  */
47480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47481 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_LSB 0
47482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47483 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_MSB 31
47484 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47485 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_WIDTH 32
47486 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
47487 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET_MSK 0xffffffff
47488 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
47489 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_CLR_MSK 0x00000000
47490 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
47491 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_RESET 0xffffffff
47492 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO field value from a register. */
47493 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
47494 /* Produces a ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value suitable for setting the register. */
47495 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
47496 
47497 #ifndef __ASSEMBLY__
47498 /*
47499  * WARNING: The C register and register group struct declarations are provided for
47500  * convenience and illustrative purposes. They should, however, be used with
47501  * caution as the C language standard provides no guarantees about the alignment or
47502  * atomicity of device memory accesses. The recommended practice for writing
47503  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47504  * alt_write_word() functions.
47505  *
47506  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW.
47507  */
47508 struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s
47509 {
47510  uint32_t addrlo : 32; /* MAC Address39 [31:0] */
47511 };
47512 
47513 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW. */
47514 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s ALT_EMAC_GMAC_MAC_ADDR39_LOW_t;
47515 #endif /* __ASSEMBLY__ */
47516 
47517 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register from the beginning of the component. */
47518 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST 0x8bc
47519 /* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register. */
47520 #define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST))
47521 
47522 /*
47523  * Register : Register 560 (MAC Address40 High Register) - MAC_Address40_High
47524  *
47525  * The MAC Address40 High register holds the upper 16 bits of the 41th 6-byte MAC
47526  * address of the station. Because the MAC address registers are configured to be
47527  * double-synchronized to the (G)MII clock domains, the synchronization is
47528  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
47529  * endian mode) of the MAC Address40 Low Register are written. For proper
47530  * synchronization updates, the consecutive writes to this Address Low Register
47531  * should be performed after at least four clock cycles in the destination clock
47532  * domain.
47533  *
47534  * Note that all MAC Address High registers (except MAC Address0 High) have the
47535  * same format.
47536  *
47537  * Register Layout
47538  *
47539  * Bits | Access | Reset | Description
47540  * :--------|:-------|:-------|:----------------------
47541  * [15:0] | RW | 0xffff | MAC Address40 [47:32]
47542  * [23:16] | ??? | 0x0 | *UNDEFINED*
47543  * [24] | RW | 0x0 | Mask Byte Control
47544  * [25] | RW | 0x0 | Mask Byte Control
47545  * [26] | RW | 0x0 | Mask Byte Control
47546  * [27] | RW | 0x0 | Mask Byte Control
47547  * [28] | RW | 0x0 | Mask Byte Control
47548  * [29] | RW | 0x0 | Mask Byte Control
47549  * [30] | RW | 0x0 | Source Address
47550  * [31] | RW | 0x0 | Address Enable
47551  *
47552  */
47553 /*
47554  * Field : MAC Address40 [47:32] - addrhi
47555  *
47556  * This field contains the upper 16 bits (47:32) of the 41th 6-byte MAC address.
47557  *
47558  * Field Access Macros:
47559  *
47560  */
47561 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
47562 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_LSB 0
47563 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
47564 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_MSB 15
47565 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
47566 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_WIDTH 16
47567 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
47568 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET_MSK 0x0000ffff
47569 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
47570 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_CLR_MSK 0xffff0000
47571 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
47572 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_RESET 0xffff
47573 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI field value from a register. */
47574 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
47575 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value suitable for setting the register. */
47576 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
47577 
47578 /*
47579  * Field : Mask Byte Control - mbc_0
47580  *
47581  * This array of bits are mask control bits for comparison of each of the MAC
47582  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47583  * received DA or SA with the contents of MAC Address40 high and low registers.
47584  * Each bit controls the masking of the bytes. You can filter a group of addresses
47585  * (known as group address filtering) by masking one or more bytes of the address.
47586  *
47587  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47588  *
47589  * Field Enumeration Values:
47590  *
47591  * Enum | Value | Description
47592  * :----------------------------------------------|:------|:------------------------------------
47593  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47594  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47595  *
47596  * Field Access Macros:
47597  *
47598  */
47599 /*
47600  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0
47601  *
47602  * Byte is unmasked (i.e. is compared)
47603  */
47604 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED 0x0
47605 /*
47606  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0
47607  *
47608  * Byte is masked (i.e. not compared)
47609  */
47610 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED 0x1
47611 
47612 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
47613 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_LSB 24
47614 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
47615 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_MSB 24
47616 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
47617 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_WIDTH 1
47618 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */
47619 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET_MSK 0x01000000
47620 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */
47621 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_CLR_MSK 0xfeffffff
47622 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
47623 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_RESET 0x0
47624 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 field value from a register. */
47625 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
47626 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value suitable for setting the register. */
47627 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
47628 
47629 /*
47630  * Field : Mask Byte Control - mbc_1
47631  *
47632  * This array of bits are mask control bits for comparison of each of the MAC
47633  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47634  * received DA or SA with the contents of MAC Address40 high and low registers.
47635  * Each bit controls the masking of the bytes. You can filter a group of addresses
47636  * (known as group address filtering) by masking one or more bytes of the address.
47637  *
47638  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47639  *
47640  * Field Enumeration Values:
47641  *
47642  * Enum | Value | Description
47643  * :----------------------------------------------|:------|:------------------------------------
47644  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47645  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47646  *
47647  * Field Access Macros:
47648  *
47649  */
47650 /*
47651  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1
47652  *
47653  * Byte is unmasked (i.e. is compared)
47654  */
47655 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED 0x0
47656 /*
47657  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1
47658  *
47659  * Byte is masked (i.e. not compared)
47660  */
47661 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED 0x1
47662 
47663 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
47664 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_LSB 25
47665 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
47666 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_MSB 25
47667 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
47668 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_WIDTH 1
47669 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */
47670 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET_MSK 0x02000000
47671 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */
47672 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_CLR_MSK 0xfdffffff
47673 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
47674 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_RESET 0x0
47675 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 field value from a register. */
47676 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
47677 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value suitable for setting the register. */
47678 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
47679 
47680 /*
47681  * Field : Mask Byte Control - mbc_2
47682  *
47683  * This array of bits are mask control bits for comparison of each of the MAC
47684  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47685  * received DA or SA with the contents of MAC Address40 high and low registers.
47686  * Each bit controls the masking of the bytes. You can filter a group of addresses
47687  * (known as group address filtering) by masking one or more bytes of the address.
47688  *
47689  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47690  *
47691  * Field Enumeration Values:
47692  *
47693  * Enum | Value | Description
47694  * :----------------------------------------------|:------|:------------------------------------
47695  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47696  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47697  *
47698  * Field Access Macros:
47699  *
47700  */
47701 /*
47702  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2
47703  *
47704  * Byte is unmasked (i.e. is compared)
47705  */
47706 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED 0x0
47707 /*
47708  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2
47709  *
47710  * Byte is masked (i.e. not compared)
47711  */
47712 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED 0x1
47713 
47714 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
47715 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_LSB 26
47716 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
47717 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_MSB 26
47718 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
47719 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_WIDTH 1
47720 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */
47721 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET_MSK 0x04000000
47722 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */
47723 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_CLR_MSK 0xfbffffff
47724 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
47725 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_RESET 0x0
47726 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 field value from a register. */
47727 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
47728 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value suitable for setting the register. */
47729 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
47730 
47731 /*
47732  * Field : Mask Byte Control - mbc_3
47733  *
47734  * This array of bits are mask control bits for comparison of each of the MAC
47735  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47736  * received DA or SA with the contents of MAC Address40 high and low registers.
47737  * Each bit controls the masking of the bytes. You can filter a group of addresses
47738  * (known as group address filtering) by masking one or more bytes of the address.
47739  *
47740  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47741  *
47742  * Field Enumeration Values:
47743  *
47744  * Enum | Value | Description
47745  * :----------------------------------------------|:------|:------------------------------------
47746  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47747  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47748  *
47749  * Field Access Macros:
47750  *
47751  */
47752 /*
47753  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3
47754  *
47755  * Byte is unmasked (i.e. is compared)
47756  */
47757 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED 0x0
47758 /*
47759  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3
47760  *
47761  * Byte is masked (i.e. not compared)
47762  */
47763 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED 0x1
47764 
47765 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
47766 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_LSB 27
47767 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
47768 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_MSB 27
47769 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
47770 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_WIDTH 1
47771 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */
47772 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET_MSK 0x08000000
47773 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */
47774 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_CLR_MSK 0xf7ffffff
47775 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
47776 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_RESET 0x0
47777 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 field value from a register. */
47778 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
47779 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value suitable for setting the register. */
47780 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
47781 
47782 /*
47783  * Field : Mask Byte Control - mbc_4
47784  *
47785  * This array of bits are mask control bits for comparison of each of the MAC
47786  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47787  * received DA or SA with the contents of MAC Address40 high and low registers.
47788  * Each bit controls the masking of the bytes. You can filter a group of addresses
47789  * (known as group address filtering) by masking one or more bytes of the address.
47790  *
47791  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47792  *
47793  * Field Enumeration Values:
47794  *
47795  * Enum | Value | Description
47796  * :----------------------------------------------|:------|:------------------------------------
47797  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47798  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47799  *
47800  * Field Access Macros:
47801  *
47802  */
47803 /*
47804  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4
47805  *
47806  * Byte is unmasked (i.e. is compared)
47807  */
47808 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED 0x0
47809 /*
47810  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4
47811  *
47812  * Byte is masked (i.e. not compared)
47813  */
47814 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED 0x1
47815 
47816 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
47817 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_LSB 28
47818 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
47819 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_MSB 28
47820 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
47821 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_WIDTH 1
47822 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */
47823 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET_MSK 0x10000000
47824 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */
47825 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_CLR_MSK 0xefffffff
47826 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
47827 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_RESET 0x0
47828 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 field value from a register. */
47829 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
47830 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value suitable for setting the register. */
47831 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
47832 
47833 /*
47834  * Field : Mask Byte Control - mbc_5
47835  *
47836  * This array of bits are mask control bits for comparison of each of the MAC
47837  * Address bytes. When masked, the MAC does not compare the corresponding byte of
47838  * received DA or SA with the contents of MAC Address40 high and low registers.
47839  * Each bit controls the masking of the bytes. You can filter a group of addresses
47840  * (known as group address filtering) by masking one or more bytes of the address.
47841  *
47842  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
47843  *
47844  * Field Enumeration Values:
47845  *
47846  * Enum | Value | Description
47847  * :----------------------------------------------|:------|:------------------------------------
47848  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
47849  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
47850  *
47851  * Field Access Macros:
47852  *
47853  */
47854 /*
47855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5
47856  *
47857  * Byte is unmasked (i.e. is compared)
47858  */
47859 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED 0x0
47860 /*
47861  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5
47862  *
47863  * Byte is masked (i.e. not compared)
47864  */
47865 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED 0x1
47866 
47867 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
47868 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_LSB 29
47869 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
47870 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_MSB 29
47871 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
47872 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_WIDTH 1
47873 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */
47874 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET_MSK 0x20000000
47875 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */
47876 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_CLR_MSK 0xdfffffff
47877 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
47878 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_RESET 0x0
47879 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 field value from a register. */
47880 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
47881 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value suitable for setting the register. */
47882 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
47883 
47884 /*
47885  * Field : Source Address - sa
47886  *
47887  * When this bit is enabled, the MAC Address40[47:0] is used to compare with the SA
47888  * fields of the received frame. When this bit is disabled, the MAC Address40[47:0]
47889  * is used to compare with the DA fields of the received frame.
47890  *
47891  * Field Enumeration Values:
47892  *
47893  * Enum | Value | Description
47894  * :----------------------------------------|:------|:-----------------------------
47895  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
47896  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END | 0x1 | MAC address compare enabled
47897  *
47898  * Field Access Macros:
47899  *
47900  */
47901 /*
47902  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA
47903  *
47904  * MAC address compare disabled
47905  */
47906 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD 0x0
47907 /*
47908  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA
47909  *
47910  * MAC address compare enabled
47911  */
47912 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END 0x1
47913 
47914 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
47915 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_LSB 30
47916 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
47917 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_MSB 30
47918 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
47919 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_WIDTH 1
47920 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */
47921 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET_MSK 0x40000000
47922 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */
47923 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_CLR_MSK 0xbfffffff
47924 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
47925 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_RESET 0x0
47926 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA field value from a register. */
47927 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
47928 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value suitable for setting the register. */
47929 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
47930 
47931 /*
47932  * Field : Address Enable - ae
47933  *
47934  * When this bit is enabled, the address filter block uses the 41th MAC address for
47935  * perfect filtering. When this bit is disabled, the address filter block ignores
47936  * the address for filtering.
47937  *
47938  * Field Enumeration Values:
47939  *
47940  * Enum | Value | Description
47941  * :----------------------------------------|:------|:--------------------------------------
47942  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
47943  * ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
47944  *
47945  * Field Access Macros:
47946  *
47947  */
47948 /*
47949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
47950  *
47951  * Second MAC address filtering disabled
47952  */
47953 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD 0x0
47954 /*
47955  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
47956  *
47957  * Second MAC address filtering enabled
47958  */
47959 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END 0x1
47960 
47961 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
47962 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_LSB 31
47963 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
47964 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_MSB 31
47965 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
47966 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_WIDTH 1
47967 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
47968 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET_MSK 0x80000000
47969 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
47970 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_CLR_MSK 0x7fffffff
47971 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
47972 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_RESET 0x0
47973 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE field value from a register. */
47974 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
47975 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value suitable for setting the register. */
47976 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
47977 
47978 #ifndef __ASSEMBLY__
47979 /*
47980  * WARNING: The C register and register group struct declarations are provided for
47981  * convenience and illustrative purposes. They should, however, be used with
47982  * caution as the C language standard provides no guarantees about the alignment or
47983  * atomicity of device memory accesses. The recommended practice for writing
47984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
47985  * alt_write_word() functions.
47986  *
47987  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH.
47988  */
47989 struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s
47990 {
47991  uint32_t addrhi : 16; /* MAC Address40 [47:32] */
47992  uint32_t : 8; /* *UNDEFINED* */
47993  uint32_t mbc_0 : 1; /* Mask Byte Control */
47994  uint32_t mbc_1 : 1; /* Mask Byte Control */
47995  uint32_t mbc_2 : 1; /* Mask Byte Control */
47996  uint32_t mbc_3 : 1; /* Mask Byte Control */
47997  uint32_t mbc_4 : 1; /* Mask Byte Control */
47998  uint32_t mbc_5 : 1; /* Mask Byte Control */
47999  uint32_t sa : 1; /* Source Address */
48000  uint32_t ae : 1; /* Address Enable */
48001 };
48002 
48003 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH. */
48004 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t;
48005 #endif /* __ASSEMBLY__ */
48006 
48007 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register from the beginning of the component. */
48008 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST 0x8c0
48009 /* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register. */
48010 #define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST))
48011 
48012 /*
48013  * Register : Register 561 (MAC Address40 Low Register) - MAC_Address40_Low
48014  *
48015  * The MAC Address40 Low register holds the lower 32 bits of the 41th 6-byte MAC
48016  * address of the station.
48017  *
48018  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
48019  * format.
48020  *
48021  * Register Layout
48022  *
48023  * Bits | Access | Reset | Description
48024  * :-------|:-------|:-----------|:---------------------
48025  * [31:0] | RW | 0xffffffff | MAC Address40 [31:0]
48026  *
48027  */
48028 /*
48029  * Field : MAC Address40 [31:0] - addrlo
48030  *
48031  * This field contains the lower 32 bits of the 41th 6-byte MAC address. The
48032  * content of this field is undefined until loaded by software after the
48033  * initialization process.
48034  *
48035  * Field Access Macros:
48036  *
48037  */
48038 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48039 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_LSB 0
48040 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48041 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_MSB 31
48042 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48043 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_WIDTH 32
48044 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
48045 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET_MSK 0xffffffff
48046 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
48047 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_CLR_MSK 0x00000000
48048 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
48049 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_RESET 0xffffffff
48050 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO field value from a register. */
48051 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48052 /* Produces a ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value suitable for setting the register. */
48053 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48054 
48055 #ifndef __ASSEMBLY__
48056 /*
48057  * WARNING: The C register and register group struct declarations are provided for
48058  * convenience and illustrative purposes. They should, however, be used with
48059  * caution as the C language standard provides no guarantees about the alignment or
48060  * atomicity of device memory accesses. The recommended practice for writing
48061  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48062  * alt_write_word() functions.
48063  *
48064  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW.
48065  */
48066 struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s
48067 {
48068  uint32_t addrlo : 32; /* MAC Address40 [31:0] */
48069 };
48070 
48071 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW. */
48072 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s ALT_EMAC_GMAC_MAC_ADDR40_LOW_t;
48073 #endif /* __ASSEMBLY__ */
48074 
48075 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register from the beginning of the component. */
48076 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST 0x8c4
48077 /* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register. */
48078 #define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST))
48079 
48080 /*
48081  * Register : Register 562 (MAC Address41 High Register) - MAC_Address41_High
48082  *
48083  * The MAC Address41 High register holds the upper 16 bits of the 42th 6-byte MAC
48084  * address of the station. Because the MAC address registers are configured to be
48085  * double-synchronized to the (G)MII clock domains, the synchronization is
48086  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
48087  * endian mode) of the MAC Address41 Low Register are written. For proper
48088  * synchronization updates, the consecutive writes to this Address Low Register
48089  * should be performed after at least four clock cycles in the destination clock
48090  * domain.
48091  *
48092  * Note that all MAC Address High registers (except MAC Address0 High) have the
48093  * same format.
48094  *
48095  * Register Layout
48096  *
48097  * Bits | Access | Reset | Description
48098  * :--------|:-------|:-------|:----------------------
48099  * [15:0] | RW | 0xffff | MAC Address41 [47:32]
48100  * [23:16] | ??? | 0x0 | *UNDEFINED*
48101  * [24] | RW | 0x0 | Mask Byte Control
48102  * [25] | RW | 0x0 | Mask Byte Control
48103  * [26] | RW | 0x0 | Mask Byte Control
48104  * [27] | RW | 0x0 | Mask Byte Control
48105  * [28] | RW | 0x0 | Mask Byte Control
48106  * [29] | RW | 0x0 | Mask Byte Control
48107  * [30] | RW | 0x0 | Source Address
48108  * [31] | RW | 0x0 | Address Enable
48109  *
48110  */
48111 /*
48112  * Field : MAC Address41 [47:32] - addrhi
48113  *
48114  * This field contains the upper 16 bits (47:32) of the 42th 6-byte MAC address.
48115  *
48116  * Field Access Macros:
48117  *
48118  */
48119 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48120 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_LSB 0
48121 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48122 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_MSB 15
48123 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48124 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_WIDTH 16
48125 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
48126 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET_MSK 0x0000ffff
48127 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
48128 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_CLR_MSK 0xffff0000
48129 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
48130 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_RESET 0xffff
48131 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI field value from a register. */
48132 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48133 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value suitable for setting the register. */
48134 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48135 
48136 /*
48137  * Field : Mask Byte Control - mbc_0
48138  *
48139  * This array of bits are mask control bits for comparison of each of the MAC
48140  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48141  * received DA or SA with the contents of MAC Address41 high and low registers.
48142  * Each bit controls the masking of the bytes. You can filter a group of addresses
48143  * (known as group address filtering) by masking one or more bytes of the address.
48144  *
48145  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48146  *
48147  * Field Enumeration Values:
48148  *
48149  * Enum | Value | Description
48150  * :----------------------------------------------|:------|:------------------------------------
48151  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48152  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48153  *
48154  * Field Access Macros:
48155  *
48156  */
48157 /*
48158  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0
48159  *
48160  * Byte is unmasked (i.e. is compared)
48161  */
48162 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED 0x0
48163 /*
48164  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0
48165  *
48166  * Byte is masked (i.e. not compared)
48167  */
48168 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED 0x1
48169 
48170 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
48171 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_LSB 24
48172 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
48173 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_MSB 24
48174 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
48175 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_WIDTH 1
48176 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */
48177 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET_MSK 0x01000000
48178 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */
48179 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_CLR_MSK 0xfeffffff
48180 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
48181 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_RESET 0x0
48182 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 field value from a register. */
48183 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
48184 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value suitable for setting the register. */
48185 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
48186 
48187 /*
48188  * Field : Mask Byte Control - mbc_1
48189  *
48190  * This array of bits are mask control bits for comparison of each of the MAC
48191  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48192  * received DA or SA with the contents of MAC Address41 high and low registers.
48193  * Each bit controls the masking of the bytes. You can filter a group of addresses
48194  * (known as group address filtering) by masking one or more bytes of the address.
48195  *
48196  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48197  *
48198  * Field Enumeration Values:
48199  *
48200  * Enum | Value | Description
48201  * :----------------------------------------------|:------|:------------------------------------
48202  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48203  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48204  *
48205  * Field Access Macros:
48206  *
48207  */
48208 /*
48209  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1
48210  *
48211  * Byte is unmasked (i.e. is compared)
48212  */
48213 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED 0x0
48214 /*
48215  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1
48216  *
48217  * Byte is masked (i.e. not compared)
48218  */
48219 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED 0x1
48220 
48221 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
48222 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_LSB 25
48223 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
48224 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_MSB 25
48225 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
48226 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_WIDTH 1
48227 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */
48228 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET_MSK 0x02000000
48229 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */
48230 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_CLR_MSK 0xfdffffff
48231 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
48232 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_RESET 0x0
48233 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 field value from a register. */
48234 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
48235 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value suitable for setting the register. */
48236 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
48237 
48238 /*
48239  * Field : Mask Byte Control - mbc_2
48240  *
48241  * This array of bits are mask control bits for comparison of each of the MAC
48242  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48243  * received DA or SA with the contents of MAC Address41 high and low registers.
48244  * Each bit controls the masking of the bytes. You can filter a group of addresses
48245  * (known as group address filtering) by masking one or more bytes of the address.
48246  *
48247  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48248  *
48249  * Field Enumeration Values:
48250  *
48251  * Enum | Value | Description
48252  * :----------------------------------------------|:------|:------------------------------------
48253  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48254  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48255  *
48256  * Field Access Macros:
48257  *
48258  */
48259 /*
48260  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2
48261  *
48262  * Byte is unmasked (i.e. is compared)
48263  */
48264 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED 0x0
48265 /*
48266  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2
48267  *
48268  * Byte is masked (i.e. not compared)
48269  */
48270 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED 0x1
48271 
48272 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
48273 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_LSB 26
48274 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
48275 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_MSB 26
48276 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
48277 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_WIDTH 1
48278 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */
48279 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET_MSK 0x04000000
48280 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */
48281 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_CLR_MSK 0xfbffffff
48282 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
48283 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_RESET 0x0
48284 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 field value from a register. */
48285 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
48286 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value suitable for setting the register. */
48287 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
48288 
48289 /*
48290  * Field : Mask Byte Control - mbc_3
48291  *
48292  * This array of bits are mask control bits for comparison of each of the MAC
48293  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48294  * received DA or SA with the contents of MAC Address41 high and low registers.
48295  * Each bit controls the masking of the bytes. You can filter a group of addresses
48296  * (known as group address filtering) by masking one or more bytes of the address.
48297  *
48298  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48299  *
48300  * Field Enumeration Values:
48301  *
48302  * Enum | Value | Description
48303  * :----------------------------------------------|:------|:------------------------------------
48304  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48305  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48306  *
48307  * Field Access Macros:
48308  *
48309  */
48310 /*
48311  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3
48312  *
48313  * Byte is unmasked (i.e. is compared)
48314  */
48315 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED 0x0
48316 /*
48317  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3
48318  *
48319  * Byte is masked (i.e. not compared)
48320  */
48321 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED 0x1
48322 
48323 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
48324 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_LSB 27
48325 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
48326 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_MSB 27
48327 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
48328 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_WIDTH 1
48329 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */
48330 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET_MSK 0x08000000
48331 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */
48332 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_CLR_MSK 0xf7ffffff
48333 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
48334 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_RESET 0x0
48335 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 field value from a register. */
48336 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
48337 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value suitable for setting the register. */
48338 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
48339 
48340 /*
48341  * Field : Mask Byte Control - mbc_4
48342  *
48343  * This array of bits are mask control bits for comparison of each of the MAC
48344  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48345  * received DA or SA with the contents of MAC Address41 high and low registers.
48346  * Each bit controls the masking of the bytes. You can filter a group of addresses
48347  * (known as group address filtering) by masking one or more bytes of the address.
48348  *
48349  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48350  *
48351  * Field Enumeration Values:
48352  *
48353  * Enum | Value | Description
48354  * :----------------------------------------------|:------|:------------------------------------
48355  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48356  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48357  *
48358  * Field Access Macros:
48359  *
48360  */
48361 /*
48362  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4
48363  *
48364  * Byte is unmasked (i.e. is compared)
48365  */
48366 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED 0x0
48367 /*
48368  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4
48369  *
48370  * Byte is masked (i.e. not compared)
48371  */
48372 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED 0x1
48373 
48374 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
48375 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_LSB 28
48376 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
48377 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_MSB 28
48378 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
48379 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_WIDTH 1
48380 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */
48381 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET_MSK 0x10000000
48382 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */
48383 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_CLR_MSK 0xefffffff
48384 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
48385 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_RESET 0x0
48386 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 field value from a register. */
48387 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
48388 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value suitable for setting the register. */
48389 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
48390 
48391 /*
48392  * Field : Mask Byte Control - mbc_5
48393  *
48394  * This array of bits are mask control bits for comparison of each of the MAC
48395  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48396  * received DA or SA with the contents of MAC Address41 high and low registers.
48397  * Each bit controls the masking of the bytes. You can filter a group of addresses
48398  * (known as group address filtering) by masking one or more bytes of the address.
48399  *
48400  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48401  *
48402  * Field Enumeration Values:
48403  *
48404  * Enum | Value | Description
48405  * :----------------------------------------------|:------|:------------------------------------
48406  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48407  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48408  *
48409  * Field Access Macros:
48410  *
48411  */
48412 /*
48413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5
48414  *
48415  * Byte is unmasked (i.e. is compared)
48416  */
48417 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED 0x0
48418 /*
48419  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5
48420  *
48421  * Byte is masked (i.e. not compared)
48422  */
48423 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED 0x1
48424 
48425 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
48426 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_LSB 29
48427 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
48428 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_MSB 29
48429 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
48430 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_WIDTH 1
48431 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */
48432 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET_MSK 0x20000000
48433 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */
48434 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_CLR_MSK 0xdfffffff
48435 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
48436 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_RESET 0x0
48437 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 field value from a register. */
48438 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
48439 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value suitable for setting the register. */
48440 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
48441 
48442 /*
48443  * Field : Source Address - sa
48444  *
48445  * When this bit is enabled, the MAC Address41[47:0] is used to compare with the SA
48446  * fields of the received frame. When this bit is disabled, the MAC Address41[47:0]
48447  * is used to compare with the DA fields of the received frame.
48448  *
48449  * Field Enumeration Values:
48450  *
48451  * Enum | Value | Description
48452  * :----------------------------------------|:------|:-----------------------------
48453  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
48454  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END | 0x1 | MAC address compare enabled
48455  *
48456  * Field Access Macros:
48457  *
48458  */
48459 /*
48460  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA
48461  *
48462  * MAC address compare disabled
48463  */
48464 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD 0x0
48465 /*
48466  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA
48467  *
48468  * MAC address compare enabled
48469  */
48470 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END 0x1
48471 
48472 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
48473 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_LSB 30
48474 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
48475 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_MSB 30
48476 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
48477 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_WIDTH 1
48478 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */
48479 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET_MSK 0x40000000
48480 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */
48481 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_CLR_MSK 0xbfffffff
48482 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
48483 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_RESET 0x0
48484 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA field value from a register. */
48485 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
48486 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value suitable for setting the register. */
48487 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
48488 
48489 /*
48490  * Field : Address Enable - ae
48491  *
48492  * When this bit is enabled, the address filter block uses the 42th MAC address for
48493  * perfect filtering. When this bit is disabled, the address filter block ignores
48494  * the address for filtering.
48495  *
48496  * Field Enumeration Values:
48497  *
48498  * Enum | Value | Description
48499  * :----------------------------------------|:------|:--------------------------------------
48500  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
48501  * ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
48502  *
48503  * Field Access Macros:
48504  *
48505  */
48506 /*
48507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
48508  *
48509  * Second MAC address filtering disabled
48510  */
48511 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD 0x0
48512 /*
48513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
48514  *
48515  * Second MAC address filtering enabled
48516  */
48517 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END 0x1
48518 
48519 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48520 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_LSB 31
48521 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48522 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_MSB 31
48523 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48524 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_WIDTH 1
48525 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
48526 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET_MSK 0x80000000
48527 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
48528 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_CLR_MSK 0x7fffffff
48529 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
48530 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_RESET 0x0
48531 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE field value from a register. */
48532 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
48533 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value suitable for setting the register. */
48534 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
48535 
48536 #ifndef __ASSEMBLY__
48537 /*
48538  * WARNING: The C register and register group struct declarations are provided for
48539  * convenience and illustrative purposes. They should, however, be used with
48540  * caution as the C language standard provides no guarantees about the alignment or
48541  * atomicity of device memory accesses. The recommended practice for writing
48542  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48543  * alt_write_word() functions.
48544  *
48545  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH.
48546  */
48547 struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s
48548 {
48549  uint32_t addrhi : 16; /* MAC Address41 [47:32] */
48550  uint32_t : 8; /* *UNDEFINED* */
48551  uint32_t mbc_0 : 1; /* Mask Byte Control */
48552  uint32_t mbc_1 : 1; /* Mask Byte Control */
48553  uint32_t mbc_2 : 1; /* Mask Byte Control */
48554  uint32_t mbc_3 : 1; /* Mask Byte Control */
48555  uint32_t mbc_4 : 1; /* Mask Byte Control */
48556  uint32_t mbc_5 : 1; /* Mask Byte Control */
48557  uint32_t sa : 1; /* Source Address */
48558  uint32_t ae : 1; /* Address Enable */
48559 };
48560 
48561 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH. */
48562 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t;
48563 #endif /* __ASSEMBLY__ */
48564 
48565 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register from the beginning of the component. */
48566 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST 0x8c8
48567 /* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register. */
48568 #define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST))
48569 
48570 /*
48571  * Register : Register 563 (MAC Address41 Low Register) - MAC_Address41_Low
48572  *
48573  * The MAC Address41 Low register holds the lower 32 bits of the 42th 6-byte MAC
48574  * address of the station.
48575  *
48576  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
48577  * format.
48578  *
48579  * Register Layout
48580  *
48581  * Bits | Access | Reset | Description
48582  * :-------|:-------|:-----------|:---------------------
48583  * [31:0] | RW | 0xffffffff | MAC Address41 [31:0]
48584  *
48585  */
48586 /*
48587  * Field : MAC Address41 [31:0] - addrlo
48588  *
48589  * This field contains the lower 32 bits of the 42th 6-byte MAC address. The
48590  * content of this field is undefined until loaded by software after the
48591  * initialization process.
48592  *
48593  * Field Access Macros:
48594  *
48595  */
48596 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48597 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_LSB 0
48598 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48599 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_MSB 31
48600 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48601 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_WIDTH 32
48602 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
48603 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET_MSK 0xffffffff
48604 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
48605 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_CLR_MSK 0x00000000
48606 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
48607 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_RESET 0xffffffff
48608 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO field value from a register. */
48609 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
48610 /* Produces a ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value suitable for setting the register. */
48611 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
48612 
48613 #ifndef __ASSEMBLY__
48614 /*
48615  * WARNING: The C register and register group struct declarations are provided for
48616  * convenience and illustrative purposes. They should, however, be used with
48617  * caution as the C language standard provides no guarantees about the alignment or
48618  * atomicity of device memory accesses. The recommended practice for writing
48619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
48620  * alt_write_word() functions.
48621  *
48622  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW.
48623  */
48624 struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s
48625 {
48626  uint32_t addrlo : 32; /* MAC Address41 [31:0] */
48627 };
48628 
48629 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW. */
48630 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s ALT_EMAC_GMAC_MAC_ADDR41_LOW_t;
48631 #endif /* __ASSEMBLY__ */
48632 
48633 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register from the beginning of the component. */
48634 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST 0x8cc
48635 /* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register. */
48636 #define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST))
48637 
48638 /*
48639  * Register : Register 564 (MAC Address42 High Register) - MAC_Address42_High
48640  *
48641  * The MAC Address42 High register holds the upper 16 bits of the 43th 6-byte MAC
48642  * address of the station. Because the MAC address registers are configured to be
48643  * double-synchronized to the (G)MII clock domains, the synchronization is
48644  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
48645  * endian mode) of the MAC Address42 Low Register are written. For proper
48646  * synchronization updates, the consecutive writes to this Address Low Register
48647  * should be performed after at least four clock cycles in the destination clock
48648  * domain.
48649  *
48650  * Note that all MAC Address High registers (except MAC Address0 High) have the
48651  * same format.
48652  *
48653  * Register Layout
48654  *
48655  * Bits | Access | Reset | Description
48656  * :--------|:-------|:-------|:----------------------
48657  * [15:0] | RW | 0xffff | MAC Address42 [47:32]
48658  * [23:16] | ??? | 0x0 | *UNDEFINED*
48659  * [24] | RW | 0x0 | Mask Byte Control
48660  * [25] | RW | 0x0 | Mask Byte Control
48661  * [26] | RW | 0x0 | Mask Byte Control
48662  * [27] | RW | 0x0 | Mask Byte Control
48663  * [28] | RW | 0x0 | Mask Byte Control
48664  * [29] | RW | 0x0 | Mask Byte Control
48665  * [30] | RW | 0x0 | Source Address
48666  * [31] | RW | 0x0 | Address Enable
48667  *
48668  */
48669 /*
48670  * Field : MAC Address42 [47:32] - addrhi
48671  *
48672  * This field contains the upper 16 bits (47:32) of the 43th 6-byte MAC address.
48673  *
48674  * Field Access Macros:
48675  *
48676  */
48677 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48678 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_LSB 0
48679 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48680 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_MSB 15
48681 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48682 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_WIDTH 16
48683 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
48684 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET_MSK 0x0000ffff
48685 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
48686 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_CLR_MSK 0xffff0000
48687 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
48688 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_RESET 0xffff
48689 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI field value from a register. */
48690 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
48691 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value suitable for setting the register. */
48692 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
48693 
48694 /*
48695  * Field : Mask Byte Control - mbc_0
48696  *
48697  * This array of bits are mask control bits for comparison of each of the MAC
48698  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48699  * received DA or SA with the contents of MAC Address42 high and low registers.
48700  * Each bit controls the masking of the bytes. You can filter a group of addresses
48701  * (known as group address filtering) by masking one or more bytes of the address.
48702  *
48703  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48704  *
48705  * Field Enumeration Values:
48706  *
48707  * Enum | Value | Description
48708  * :----------------------------------------------|:------|:------------------------------------
48709  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48710  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48711  *
48712  * Field Access Macros:
48713  *
48714  */
48715 /*
48716  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0
48717  *
48718  * Byte is unmasked (i.e. is compared)
48719  */
48720 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED 0x0
48721 /*
48722  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0
48723  *
48724  * Byte is masked (i.e. not compared)
48725  */
48726 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED 0x1
48727 
48728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
48729 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_LSB 24
48730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
48731 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_MSB 24
48732 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
48733 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_WIDTH 1
48734 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */
48735 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET_MSK 0x01000000
48736 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */
48737 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_CLR_MSK 0xfeffffff
48738 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
48739 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_RESET 0x0
48740 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 field value from a register. */
48741 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
48742 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value suitable for setting the register. */
48743 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
48744 
48745 /*
48746  * Field : Mask Byte Control - mbc_1
48747  *
48748  * This array of bits are mask control bits for comparison of each of the MAC
48749  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48750  * received DA or SA with the contents of MAC Address42 high and low registers.
48751  * Each bit controls the masking of the bytes. You can filter a group of addresses
48752  * (known as group address filtering) by masking one or more bytes of the address.
48753  *
48754  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48755  *
48756  * Field Enumeration Values:
48757  *
48758  * Enum | Value | Description
48759  * :----------------------------------------------|:------|:------------------------------------
48760  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48761  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48762  *
48763  * Field Access Macros:
48764  *
48765  */
48766 /*
48767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1
48768  *
48769  * Byte is unmasked (i.e. is compared)
48770  */
48771 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED 0x0
48772 /*
48773  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1
48774  *
48775  * Byte is masked (i.e. not compared)
48776  */
48777 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED 0x1
48778 
48779 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
48780 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_LSB 25
48781 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
48782 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_MSB 25
48783 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
48784 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_WIDTH 1
48785 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */
48786 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET_MSK 0x02000000
48787 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */
48788 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_CLR_MSK 0xfdffffff
48789 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
48790 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_RESET 0x0
48791 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 field value from a register. */
48792 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
48793 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value suitable for setting the register. */
48794 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
48795 
48796 /*
48797  * Field : Mask Byte Control - mbc_2
48798  *
48799  * This array of bits are mask control bits for comparison of each of the MAC
48800  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48801  * received DA or SA with the contents of MAC Address42 high and low registers.
48802  * Each bit controls the masking of the bytes. You can filter a group of addresses
48803  * (known as group address filtering) by masking one or more bytes of the address.
48804  *
48805  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48806  *
48807  * Field Enumeration Values:
48808  *
48809  * Enum | Value | Description
48810  * :----------------------------------------------|:------|:------------------------------------
48811  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48812  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48813  *
48814  * Field Access Macros:
48815  *
48816  */
48817 /*
48818  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2
48819  *
48820  * Byte is unmasked (i.e. is compared)
48821  */
48822 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED 0x0
48823 /*
48824  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2
48825  *
48826  * Byte is masked (i.e. not compared)
48827  */
48828 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED 0x1
48829 
48830 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
48831 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_LSB 26
48832 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
48833 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_MSB 26
48834 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
48835 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_WIDTH 1
48836 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */
48837 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET_MSK 0x04000000
48838 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */
48839 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_CLR_MSK 0xfbffffff
48840 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
48841 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_RESET 0x0
48842 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 field value from a register. */
48843 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
48844 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value suitable for setting the register. */
48845 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
48846 
48847 /*
48848  * Field : Mask Byte Control - mbc_3
48849  *
48850  * This array of bits are mask control bits for comparison of each of the MAC
48851  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48852  * received DA or SA with the contents of MAC Address42 high and low registers.
48853  * Each bit controls the masking of the bytes. You can filter a group of addresses
48854  * (known as group address filtering) by masking one or more bytes of the address.
48855  *
48856  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48857  *
48858  * Field Enumeration Values:
48859  *
48860  * Enum | Value | Description
48861  * :----------------------------------------------|:------|:------------------------------------
48862  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48863  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48864  *
48865  * Field Access Macros:
48866  *
48867  */
48868 /*
48869  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3
48870  *
48871  * Byte is unmasked (i.e. is compared)
48872  */
48873 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED 0x0
48874 /*
48875  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3
48876  *
48877  * Byte is masked (i.e. not compared)
48878  */
48879 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED 0x1
48880 
48881 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
48882 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_LSB 27
48883 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
48884 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_MSB 27
48885 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
48886 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_WIDTH 1
48887 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */
48888 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET_MSK 0x08000000
48889 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */
48890 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_CLR_MSK 0xf7ffffff
48891 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
48892 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_RESET 0x0
48893 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 field value from a register. */
48894 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
48895 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value suitable for setting the register. */
48896 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
48897 
48898 /*
48899  * Field : Mask Byte Control - mbc_4
48900  *
48901  * This array of bits are mask control bits for comparison of each of the MAC
48902  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48903  * received DA or SA with the contents of MAC Address42 high and low registers.
48904  * Each bit controls the masking of the bytes. You can filter a group of addresses
48905  * (known as group address filtering) by masking one or more bytes of the address.
48906  *
48907  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48908  *
48909  * Field Enumeration Values:
48910  *
48911  * Enum | Value | Description
48912  * :----------------------------------------------|:------|:------------------------------------
48913  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48914  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48915  *
48916  * Field Access Macros:
48917  *
48918  */
48919 /*
48920  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4
48921  *
48922  * Byte is unmasked (i.e. is compared)
48923  */
48924 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED 0x0
48925 /*
48926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4
48927  *
48928  * Byte is masked (i.e. not compared)
48929  */
48930 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED 0x1
48931 
48932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
48933 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_LSB 28
48934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
48935 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_MSB 28
48936 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
48937 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_WIDTH 1
48938 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */
48939 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET_MSK 0x10000000
48940 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */
48941 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_CLR_MSK 0xefffffff
48942 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
48943 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_RESET 0x0
48944 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 field value from a register. */
48945 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
48946 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value suitable for setting the register. */
48947 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
48948 
48949 /*
48950  * Field : Mask Byte Control - mbc_5
48951  *
48952  * This array of bits are mask control bits for comparison of each of the MAC
48953  * Address bytes. When masked, the MAC does not compare the corresponding byte of
48954  * received DA or SA with the contents of MAC Address42 high and low registers.
48955  * Each bit controls the masking of the bytes. You can filter a group of addresses
48956  * (known as group address filtering) by masking one or more bytes of the address.
48957  *
48958  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
48959  *
48960  * Field Enumeration Values:
48961  *
48962  * Enum | Value | Description
48963  * :----------------------------------------------|:------|:------------------------------------
48964  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
48965  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
48966  *
48967  * Field Access Macros:
48968  *
48969  */
48970 /*
48971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5
48972  *
48973  * Byte is unmasked (i.e. is compared)
48974  */
48975 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED 0x0
48976 /*
48977  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5
48978  *
48979  * Byte is masked (i.e. not compared)
48980  */
48981 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED 0x1
48982 
48983 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
48984 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_LSB 29
48985 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
48986 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_MSB 29
48987 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
48988 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_WIDTH 1
48989 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */
48990 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET_MSK 0x20000000
48991 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */
48992 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_CLR_MSK 0xdfffffff
48993 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
48994 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_RESET 0x0
48995 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 field value from a register. */
48996 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
48997 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value suitable for setting the register. */
48998 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
48999 
49000 /*
49001  * Field : Source Address - sa
49002  *
49003  * When this bit is enabled, the MAC Address42[47:0] is used to compare with the SA
49004  * fields of the received frame. When this bit is disabled, the MAC Address42[47:0]
49005  * is used to compare with the DA fields of the received frame.
49006  *
49007  * Field Enumeration Values:
49008  *
49009  * Enum | Value | Description
49010  * :----------------------------------------|:------|:-----------------------------
49011  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
49012  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END | 0x1 | MAC address compare enabled
49013  *
49014  * Field Access Macros:
49015  *
49016  */
49017 /*
49018  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA
49019  *
49020  * MAC address compare disabled
49021  */
49022 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD 0x0
49023 /*
49024  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA
49025  *
49026  * MAC address compare enabled
49027  */
49028 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END 0x1
49029 
49030 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
49031 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_LSB 30
49032 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
49033 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_MSB 30
49034 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
49035 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_WIDTH 1
49036 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */
49037 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET_MSK 0x40000000
49038 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */
49039 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_CLR_MSK 0xbfffffff
49040 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
49041 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_RESET 0x0
49042 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA field value from a register. */
49043 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
49044 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value suitable for setting the register. */
49045 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
49046 
49047 /*
49048  * Field : Address Enable - ae
49049  *
49050  * When this bit is enabled, the address filter block uses the 43th MAC address for
49051  * perfect filtering. When this bit is disabled, the address filter block ignores
49052  * the address for filtering.
49053  *
49054  * Field Enumeration Values:
49055  *
49056  * Enum | Value | Description
49057  * :----------------------------------------|:------|:--------------------------------------
49058  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
49059  * ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
49060  *
49061  * Field Access Macros:
49062  *
49063  */
49064 /*
49065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
49066  *
49067  * Second MAC address filtering disabled
49068  */
49069 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD 0x0
49070 /*
49071  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
49072  *
49073  * Second MAC address filtering enabled
49074  */
49075 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END 0x1
49076 
49077 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
49078 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_LSB 31
49079 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
49080 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_MSB 31
49081 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
49082 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_WIDTH 1
49083 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
49084 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET_MSK 0x80000000
49085 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
49086 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_CLR_MSK 0x7fffffff
49087 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
49088 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_RESET 0x0
49089 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE field value from a register. */
49090 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49091 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value suitable for setting the register. */
49092 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49093 
49094 #ifndef __ASSEMBLY__
49095 /*
49096  * WARNING: The C register and register group struct declarations are provided for
49097  * convenience and illustrative purposes. They should, however, be used with
49098  * caution as the C language standard provides no guarantees about the alignment or
49099  * atomicity of device memory accesses. The recommended practice for writing
49100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49101  * alt_write_word() functions.
49102  *
49103  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH.
49104  */
49105 struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s
49106 {
49107  uint32_t addrhi : 16; /* MAC Address42 [47:32] */
49108  uint32_t : 8; /* *UNDEFINED* */
49109  uint32_t mbc_0 : 1; /* Mask Byte Control */
49110  uint32_t mbc_1 : 1; /* Mask Byte Control */
49111  uint32_t mbc_2 : 1; /* Mask Byte Control */
49112  uint32_t mbc_3 : 1; /* Mask Byte Control */
49113  uint32_t mbc_4 : 1; /* Mask Byte Control */
49114  uint32_t mbc_5 : 1; /* Mask Byte Control */
49115  uint32_t sa : 1; /* Source Address */
49116  uint32_t ae : 1; /* Address Enable */
49117 };
49118 
49119 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH. */
49120 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t;
49121 #endif /* __ASSEMBLY__ */
49122 
49123 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register from the beginning of the component. */
49124 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST 0x8d0
49125 /* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register. */
49126 #define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST))
49127 
49128 /*
49129  * Register : Register 565 (MAC Address42 Low Register) - MAC_Address42_Low
49130  *
49131  * The MAC Address42 Low register holds the lower 32 bits of the 43th 6-byte MAC
49132  * address of the station.
49133  *
49134  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
49135  * format.
49136  *
49137  * Register Layout
49138  *
49139  * Bits | Access | Reset | Description
49140  * :-------|:-------|:-----------|:---------------------
49141  * [31:0] | RW | 0xffffffff | MAC Address42 [31:0]
49142  *
49143  */
49144 /*
49145  * Field : MAC Address42 [31:0] - addrlo
49146  *
49147  * This field contains the lower 32 bits of the 43th 6-byte MAC address. The
49148  * content of this field is undefined until loaded by software after the
49149  * initialization process.
49150  *
49151  * Field Access Macros:
49152  *
49153  */
49154 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
49155 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_LSB 0
49156 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
49157 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_MSB 31
49158 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
49159 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_WIDTH 32
49160 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
49161 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET_MSK 0xffffffff
49162 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
49163 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_CLR_MSK 0x00000000
49164 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
49165 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_RESET 0xffffffff
49166 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO field value from a register. */
49167 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49168 /* Produces a ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value suitable for setting the register. */
49169 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49170 
49171 #ifndef __ASSEMBLY__
49172 /*
49173  * WARNING: The C register and register group struct declarations are provided for
49174  * convenience and illustrative purposes. They should, however, be used with
49175  * caution as the C language standard provides no guarantees about the alignment or
49176  * atomicity of device memory accesses. The recommended practice for writing
49177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49178  * alt_write_word() functions.
49179  *
49180  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW.
49181  */
49182 struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s
49183 {
49184  uint32_t addrlo : 32; /* MAC Address42 [31:0] */
49185 };
49186 
49187 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW. */
49188 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s ALT_EMAC_GMAC_MAC_ADDR42_LOW_t;
49189 #endif /* __ASSEMBLY__ */
49190 
49191 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register from the beginning of the component. */
49192 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST 0x8d4
49193 /* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register. */
49194 #define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST))
49195 
49196 /*
49197  * Register : Register 566 (MAC Address43 High Register) - MAC_Address43_High
49198  *
49199  * The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC
49200  * address of the station. Because the MAC address registers are configured to be
49201  * double-synchronized to the (G)MII clock domains, the synchronization is
49202  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
49203  * endian mode) of the MAC Address43 Low Register are written. For proper
49204  * synchronization updates, the consecutive writes to this Address Low Register
49205  * should be performed after at least four clock cycles in the destination clock
49206  * domain.
49207  *
49208  * Note that all MAC Address High registers (except MAC Address0 High) have the
49209  * same format.
49210  *
49211  * Register Layout
49212  *
49213  * Bits | Access | Reset | Description
49214  * :--------|:-------|:-------|:----------------------
49215  * [15:0] | RW | 0xffff | MAC Address43 [47:32]
49216  * [23:16] | ??? | 0x0 | *UNDEFINED*
49217  * [24] | RW | 0x0 | Mask Byte Control
49218  * [25] | RW | 0x0 | Mask Byte Control
49219  * [26] | RW | 0x0 | Mask Byte Control
49220  * [27] | RW | 0x0 | Mask Byte Control
49221  * [28] | RW | 0x0 | Mask Byte Control
49222  * [29] | RW | 0x0 | Mask Byte Control
49223  * [30] | RW | 0x0 | Source Address
49224  * [31] | RW | 0x0 | Address Enable
49225  *
49226  */
49227 /*
49228  * Field : MAC Address43 [47:32] - addrhi
49229  *
49230  * This field contains the upper 16 bits (47:32) of the 44th 6-byte MAC address.
49231  *
49232  * Field Access Macros:
49233  *
49234  */
49235 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
49236 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_LSB 0
49237 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
49238 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_MSB 15
49239 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
49240 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_WIDTH 16
49241 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
49242 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET_MSK 0x0000ffff
49243 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
49244 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_CLR_MSK 0xffff0000
49245 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
49246 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_RESET 0xffff
49247 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI field value from a register. */
49248 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49249 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value suitable for setting the register. */
49250 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49251 
49252 /*
49253  * Field : Mask Byte Control - mbc_0
49254  *
49255  * This array of bits are mask control bits for comparison of each of the MAC
49256  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49257  * received DA or SA with the contents of MAC Address43 high and low registers.
49258  * Each bit controls the masking of the bytes. You can filter a group of addresses
49259  * (known as group address filtering) by masking one or more bytes of the address.
49260  *
49261  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49262  *
49263  * Field Enumeration Values:
49264  *
49265  * Enum | Value | Description
49266  * :----------------------------------------------|:------|:------------------------------------
49267  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49268  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49269  *
49270  * Field Access Macros:
49271  *
49272  */
49273 /*
49274  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0
49275  *
49276  * Byte is unmasked (i.e. is compared)
49277  */
49278 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED 0x0
49279 /*
49280  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0
49281  *
49282  * Byte is masked (i.e. not compared)
49283  */
49284 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED 0x1
49285 
49286 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
49287 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_LSB 24
49288 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
49289 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_MSB 24
49290 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
49291 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_WIDTH 1
49292 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */
49293 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET_MSK 0x01000000
49294 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */
49295 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_CLR_MSK 0xfeffffff
49296 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
49297 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_RESET 0x0
49298 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 field value from a register. */
49299 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
49300 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value suitable for setting the register. */
49301 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
49302 
49303 /*
49304  * Field : Mask Byte Control - mbc_1
49305  *
49306  * This array of bits are mask control bits for comparison of each of the MAC
49307  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49308  * received DA or SA with the contents of MAC Address43 high and low registers.
49309  * Each bit controls the masking of the bytes. You can filter a group of addresses
49310  * (known as group address filtering) by masking one or more bytes of the address.
49311  *
49312  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49313  *
49314  * Field Enumeration Values:
49315  *
49316  * Enum | Value | Description
49317  * :----------------------------------------------|:------|:------------------------------------
49318  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49319  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49320  *
49321  * Field Access Macros:
49322  *
49323  */
49324 /*
49325  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1
49326  *
49327  * Byte is unmasked (i.e. is compared)
49328  */
49329 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED 0x0
49330 /*
49331  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1
49332  *
49333  * Byte is masked (i.e. not compared)
49334  */
49335 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED 0x1
49336 
49337 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
49338 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_LSB 25
49339 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
49340 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_MSB 25
49341 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
49342 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_WIDTH 1
49343 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */
49344 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET_MSK 0x02000000
49345 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */
49346 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_CLR_MSK 0xfdffffff
49347 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
49348 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_RESET 0x0
49349 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 field value from a register. */
49350 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
49351 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value suitable for setting the register. */
49352 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
49353 
49354 /*
49355  * Field : Mask Byte Control - mbc_2
49356  *
49357  * This array of bits are mask control bits for comparison of each of the MAC
49358  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49359  * received DA or SA with the contents of MAC Address43 high and low registers.
49360  * Each bit controls the masking of the bytes. You can filter a group of addresses
49361  * (known as group address filtering) by masking one or more bytes of the address.
49362  *
49363  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49364  *
49365  * Field Enumeration Values:
49366  *
49367  * Enum | Value | Description
49368  * :----------------------------------------------|:------|:------------------------------------
49369  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49370  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49371  *
49372  * Field Access Macros:
49373  *
49374  */
49375 /*
49376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2
49377  *
49378  * Byte is unmasked (i.e. is compared)
49379  */
49380 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED 0x0
49381 /*
49382  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2
49383  *
49384  * Byte is masked (i.e. not compared)
49385  */
49386 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED 0x1
49387 
49388 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
49389 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_LSB 26
49390 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
49391 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_MSB 26
49392 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
49393 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_WIDTH 1
49394 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */
49395 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET_MSK 0x04000000
49396 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */
49397 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_CLR_MSK 0xfbffffff
49398 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
49399 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_RESET 0x0
49400 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 field value from a register. */
49401 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
49402 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value suitable for setting the register. */
49403 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
49404 
49405 /*
49406  * Field : Mask Byte Control - mbc_3
49407  *
49408  * This array of bits are mask control bits for comparison of each of the MAC
49409  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49410  * received DA or SA with the contents of MAC Address43 high and low registers.
49411  * Each bit controls the masking of the bytes. You can filter a group of addresses
49412  * (known as group address filtering) by masking one or more bytes of the address.
49413  *
49414  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49415  *
49416  * Field Enumeration Values:
49417  *
49418  * Enum | Value | Description
49419  * :----------------------------------------------|:------|:------------------------------------
49420  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49421  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49422  *
49423  * Field Access Macros:
49424  *
49425  */
49426 /*
49427  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3
49428  *
49429  * Byte is unmasked (i.e. is compared)
49430  */
49431 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED 0x0
49432 /*
49433  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3
49434  *
49435  * Byte is masked (i.e. not compared)
49436  */
49437 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED 0x1
49438 
49439 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
49440 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_LSB 27
49441 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
49442 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_MSB 27
49443 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
49444 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_WIDTH 1
49445 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */
49446 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET_MSK 0x08000000
49447 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */
49448 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_CLR_MSK 0xf7ffffff
49449 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
49450 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_RESET 0x0
49451 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 field value from a register. */
49452 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
49453 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value suitable for setting the register. */
49454 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
49455 
49456 /*
49457  * Field : Mask Byte Control - mbc_4
49458  *
49459  * This array of bits are mask control bits for comparison of each of the MAC
49460  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49461  * received DA or SA with the contents of MAC Address43 high and low registers.
49462  * Each bit controls the masking of the bytes. You can filter a group of addresses
49463  * (known as group address filtering) by masking one or more bytes of the address.
49464  *
49465  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49466  *
49467  * Field Enumeration Values:
49468  *
49469  * Enum | Value | Description
49470  * :----------------------------------------------|:------|:------------------------------------
49471  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49472  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49473  *
49474  * Field Access Macros:
49475  *
49476  */
49477 /*
49478  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4
49479  *
49480  * Byte is unmasked (i.e. is compared)
49481  */
49482 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED 0x0
49483 /*
49484  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4
49485  *
49486  * Byte is masked (i.e. not compared)
49487  */
49488 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED 0x1
49489 
49490 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
49491 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_LSB 28
49492 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
49493 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_MSB 28
49494 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
49495 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_WIDTH 1
49496 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */
49497 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET_MSK 0x10000000
49498 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */
49499 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_CLR_MSK 0xefffffff
49500 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
49501 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_RESET 0x0
49502 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 field value from a register. */
49503 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
49504 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value suitable for setting the register. */
49505 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
49506 
49507 /*
49508  * Field : Mask Byte Control - mbc_5
49509  *
49510  * This array of bits are mask control bits for comparison of each of the MAC
49511  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49512  * received DA or SA with the contents of MAC Address43 high and low registers.
49513  * Each bit controls the masking of the bytes. You can filter a group of addresses
49514  * (known as group address filtering) by masking one or more bytes of the address.
49515  *
49516  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49517  *
49518  * Field Enumeration Values:
49519  *
49520  * Enum | Value | Description
49521  * :----------------------------------------------|:------|:------------------------------------
49522  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49523  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49524  *
49525  * Field Access Macros:
49526  *
49527  */
49528 /*
49529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5
49530  *
49531  * Byte is unmasked (i.e. is compared)
49532  */
49533 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED 0x0
49534 /*
49535  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5
49536  *
49537  * Byte is masked (i.e. not compared)
49538  */
49539 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED 0x1
49540 
49541 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
49542 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_LSB 29
49543 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
49544 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_MSB 29
49545 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
49546 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_WIDTH 1
49547 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */
49548 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET_MSK 0x20000000
49549 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */
49550 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_CLR_MSK 0xdfffffff
49551 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
49552 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_RESET 0x0
49553 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 field value from a register. */
49554 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
49555 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value suitable for setting the register. */
49556 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
49557 
49558 /*
49559  * Field : Source Address - sa
49560  *
49561  * When this bit is enabled, the MAC Address43[47:0] is used to compare with the SA
49562  * fields of the received frame. When this bit is disabled, the MAC Address43[47:0]
49563  * is used to compare with the DA fields of the received frame.
49564  *
49565  * Field Enumeration Values:
49566  *
49567  * Enum | Value | Description
49568  * :----------------------------------------|:------|:-----------------------------
49569  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
49570  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END | 0x1 | MAC address compare enabled
49571  *
49572  * Field Access Macros:
49573  *
49574  */
49575 /*
49576  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA
49577  *
49578  * MAC address compare disabled
49579  */
49580 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD 0x0
49581 /*
49582  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA
49583  *
49584  * MAC address compare enabled
49585  */
49586 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END 0x1
49587 
49588 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
49589 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_LSB 30
49590 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
49591 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_MSB 30
49592 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
49593 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_WIDTH 1
49594 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */
49595 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET_MSK 0x40000000
49596 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */
49597 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_CLR_MSK 0xbfffffff
49598 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
49599 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_RESET 0x0
49600 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA field value from a register. */
49601 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
49602 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value suitable for setting the register. */
49603 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
49604 
49605 /*
49606  * Field : Address Enable - ae
49607  *
49608  * When this bit is enabled, the address filter block uses the 44th MAC address for
49609  * perfect filtering. When this bit is disabled, the address filter block ignores
49610  * the address for filtering.
49611  *
49612  * Field Enumeration Values:
49613  *
49614  * Enum | Value | Description
49615  * :----------------------------------------|:------|:--------------------------------------
49616  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
49617  * ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
49618  *
49619  * Field Access Macros:
49620  *
49621  */
49622 /*
49623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
49624  *
49625  * Second MAC address filtering disabled
49626  */
49627 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD 0x0
49628 /*
49629  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
49630  *
49631  * Second MAC address filtering enabled
49632  */
49633 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END 0x1
49634 
49635 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
49636 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_LSB 31
49637 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
49638 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_MSB 31
49639 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
49640 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_WIDTH 1
49641 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
49642 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET_MSK 0x80000000
49643 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
49644 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_CLR_MSK 0x7fffffff
49645 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
49646 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_RESET 0x0
49647 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE field value from a register. */
49648 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
49649 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value suitable for setting the register. */
49650 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
49651 
49652 #ifndef __ASSEMBLY__
49653 /*
49654  * WARNING: The C register and register group struct declarations are provided for
49655  * convenience and illustrative purposes. They should, however, be used with
49656  * caution as the C language standard provides no guarantees about the alignment or
49657  * atomicity of device memory accesses. The recommended practice for writing
49658  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49659  * alt_write_word() functions.
49660  *
49661  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH.
49662  */
49663 struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s
49664 {
49665  uint32_t addrhi : 16; /* MAC Address43 [47:32] */
49666  uint32_t : 8; /* *UNDEFINED* */
49667  uint32_t mbc_0 : 1; /* Mask Byte Control */
49668  uint32_t mbc_1 : 1; /* Mask Byte Control */
49669  uint32_t mbc_2 : 1; /* Mask Byte Control */
49670  uint32_t mbc_3 : 1; /* Mask Byte Control */
49671  uint32_t mbc_4 : 1; /* Mask Byte Control */
49672  uint32_t mbc_5 : 1; /* Mask Byte Control */
49673  uint32_t sa : 1; /* Source Address */
49674  uint32_t ae : 1; /* Address Enable */
49675 };
49676 
49677 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH. */
49678 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t;
49679 #endif /* __ASSEMBLY__ */
49680 
49681 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register from the beginning of the component. */
49682 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST 0x8d8
49683 /* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register. */
49684 #define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST))
49685 
49686 /*
49687  * Register : Register 567 (MAC Address43 Low Register) - MAC_Address43_Low
49688  *
49689  * The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC
49690  * address of the station.
49691  *
49692  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
49693  * format.
49694  *
49695  * Register Layout
49696  *
49697  * Bits | Access | Reset | Description
49698  * :-------|:-------|:-----------|:---------------------
49699  * [31:0] | RW | 0xffffffff | MAC Address43 [31:0]
49700  *
49701  */
49702 /*
49703  * Field : MAC Address43 [31:0] - addrlo
49704  *
49705  * This field contains the lower 32 bits of the 44th 6-byte MAC address. The
49706  * content of this field is undefined until loaded by software after the
49707  * initialization process.
49708  *
49709  * Field Access Macros:
49710  *
49711  */
49712 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
49713 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_LSB 0
49714 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
49715 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_MSB 31
49716 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
49717 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_WIDTH 32
49718 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
49719 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET_MSK 0xffffffff
49720 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
49721 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_CLR_MSK 0x00000000
49722 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
49723 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_RESET 0xffffffff
49724 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO field value from a register. */
49725 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
49726 /* Produces a ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value suitable for setting the register. */
49727 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
49728 
49729 #ifndef __ASSEMBLY__
49730 /*
49731  * WARNING: The C register and register group struct declarations are provided for
49732  * convenience and illustrative purposes. They should, however, be used with
49733  * caution as the C language standard provides no guarantees about the alignment or
49734  * atomicity of device memory accesses. The recommended practice for writing
49735  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
49736  * alt_write_word() functions.
49737  *
49738  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW.
49739  */
49740 struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s
49741 {
49742  uint32_t addrlo : 32; /* MAC Address43 [31:0] */
49743 };
49744 
49745 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW. */
49746 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s ALT_EMAC_GMAC_MAC_ADDR43_LOW_t;
49747 #endif /* __ASSEMBLY__ */
49748 
49749 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register from the beginning of the component. */
49750 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST 0x8dc
49751 /* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register. */
49752 #define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST))
49753 
49754 /*
49755  * Register : Register 568 (MAC Address44 High Register) - MAC_Address44_High
49756  *
49757  * The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC
49758  * address of the station. Because the MAC address registers are configured to be
49759  * double-synchronized to the (G)MII clock domains, the synchronization is
49760  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
49761  * endian mode) of the MAC Address44 Low Register are written. For proper
49762  * synchronization updates, the consecutive writes to this Address Low Register
49763  * should be performed after at least four clock cycles in the destination clock
49764  * domain.
49765  *
49766  * Note that all MAC Address High registers (except MAC Address0 High) have the
49767  * same format.
49768  *
49769  * Register Layout
49770  *
49771  * Bits | Access | Reset | Description
49772  * :--------|:-------|:-------|:----------------------
49773  * [15:0] | RW | 0xffff | MAC Address44 [47:32]
49774  * [23:16] | ??? | 0x0 | *UNDEFINED*
49775  * [24] | RW | 0x0 | Mask Byte Control
49776  * [25] | RW | 0x0 | Mask Byte Control
49777  * [26] | RW | 0x0 | Mask Byte Control
49778  * [27] | RW | 0x0 | Mask Byte Control
49779  * [28] | RW | 0x0 | Mask Byte Control
49780  * [29] | RW | 0x0 | Mask Byte Control
49781  * [30] | RW | 0x0 | Source Address
49782  * [31] | RW | 0x0 | Address Enable
49783  *
49784  */
49785 /*
49786  * Field : MAC Address44 [47:32] - addrhi
49787  *
49788  * This field contains the upper 16 bits (47:32) of the 45th 6-byte MAC address.
49789  *
49790  * Field Access Macros:
49791  *
49792  */
49793 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
49794 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_LSB 0
49795 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
49796 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_MSB 15
49797 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
49798 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_WIDTH 16
49799 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
49800 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET_MSK 0x0000ffff
49801 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
49802 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_CLR_MSK 0xffff0000
49803 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
49804 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_RESET 0xffff
49805 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI field value from a register. */
49806 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
49807 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value suitable for setting the register. */
49808 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
49809 
49810 /*
49811  * Field : Mask Byte Control - mbc_0
49812  *
49813  * This array of bits are mask control bits for comparison of each of the MAC
49814  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49815  * received DA or SA with the contents of MAC Address44 high and low registers.
49816  * Each bit controls the masking of the bytes. You can filter a group of addresses
49817  * (known as group address filtering) by masking one or more bytes of the address.
49818  *
49819  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49820  *
49821  * Field Enumeration Values:
49822  *
49823  * Enum | Value | Description
49824  * :----------------------------------------------|:------|:------------------------------------
49825  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49826  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49827  *
49828  * Field Access Macros:
49829  *
49830  */
49831 /*
49832  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0
49833  *
49834  * Byte is unmasked (i.e. is compared)
49835  */
49836 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED 0x0
49837 /*
49838  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0
49839  *
49840  * Byte is masked (i.e. not compared)
49841  */
49842 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED 0x1
49843 
49844 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
49845 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_LSB 24
49846 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
49847 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_MSB 24
49848 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
49849 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_WIDTH 1
49850 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */
49851 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET_MSK 0x01000000
49852 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */
49853 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_CLR_MSK 0xfeffffff
49854 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
49855 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_RESET 0x0
49856 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 field value from a register. */
49857 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
49858 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value suitable for setting the register. */
49859 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
49860 
49861 /*
49862  * Field : Mask Byte Control - mbc_1
49863  *
49864  * This array of bits are mask control bits for comparison of each of the MAC
49865  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49866  * received DA or SA with the contents of MAC Address44 high and low registers.
49867  * Each bit controls the masking of the bytes. You can filter a group of addresses
49868  * (known as group address filtering) by masking one or more bytes of the address.
49869  *
49870  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49871  *
49872  * Field Enumeration Values:
49873  *
49874  * Enum | Value | Description
49875  * :----------------------------------------------|:------|:------------------------------------
49876  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49877  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49878  *
49879  * Field Access Macros:
49880  *
49881  */
49882 /*
49883  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1
49884  *
49885  * Byte is unmasked (i.e. is compared)
49886  */
49887 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED 0x0
49888 /*
49889  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1
49890  *
49891  * Byte is masked (i.e. not compared)
49892  */
49893 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED 0x1
49894 
49895 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
49896 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_LSB 25
49897 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
49898 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_MSB 25
49899 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
49900 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_WIDTH 1
49901 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */
49902 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET_MSK 0x02000000
49903 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */
49904 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_CLR_MSK 0xfdffffff
49905 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
49906 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_RESET 0x0
49907 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 field value from a register. */
49908 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
49909 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value suitable for setting the register. */
49910 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
49911 
49912 /*
49913  * Field : Mask Byte Control - mbc_2
49914  *
49915  * This array of bits are mask control bits for comparison of each of the MAC
49916  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49917  * received DA or SA with the contents of MAC Address44 high and low registers.
49918  * Each bit controls the masking of the bytes. You can filter a group of addresses
49919  * (known as group address filtering) by masking one or more bytes of the address.
49920  *
49921  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49922  *
49923  * Field Enumeration Values:
49924  *
49925  * Enum | Value | Description
49926  * :----------------------------------------------|:------|:------------------------------------
49927  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49928  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49929  *
49930  * Field Access Macros:
49931  *
49932  */
49933 /*
49934  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2
49935  *
49936  * Byte is unmasked (i.e. is compared)
49937  */
49938 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED 0x0
49939 /*
49940  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2
49941  *
49942  * Byte is masked (i.e. not compared)
49943  */
49944 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED 0x1
49945 
49946 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
49947 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_LSB 26
49948 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
49949 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_MSB 26
49950 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
49951 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_WIDTH 1
49952 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */
49953 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET_MSK 0x04000000
49954 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */
49955 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_CLR_MSK 0xfbffffff
49956 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
49957 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_RESET 0x0
49958 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 field value from a register. */
49959 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
49960 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value suitable for setting the register. */
49961 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
49962 
49963 /*
49964  * Field : Mask Byte Control - mbc_3
49965  *
49966  * This array of bits are mask control bits for comparison of each of the MAC
49967  * Address bytes. When masked, the MAC does not compare the corresponding byte of
49968  * received DA or SA with the contents of MAC Address44 high and low registers.
49969  * Each bit controls the masking of the bytes. You can filter a group of addresses
49970  * (known as group address filtering) by masking one or more bytes of the address.
49971  *
49972  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
49973  *
49974  * Field Enumeration Values:
49975  *
49976  * Enum | Value | Description
49977  * :----------------------------------------------|:------|:------------------------------------
49978  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
49979  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
49980  *
49981  * Field Access Macros:
49982  *
49983  */
49984 /*
49985  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3
49986  *
49987  * Byte is unmasked (i.e. is compared)
49988  */
49989 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED 0x0
49990 /*
49991  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3
49992  *
49993  * Byte is masked (i.e. not compared)
49994  */
49995 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED 0x1
49996 
49997 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
49998 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_LSB 27
49999 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
50000 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_MSB 27
50001 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
50002 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_WIDTH 1
50003 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */
50004 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET_MSK 0x08000000
50005 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */
50006 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_CLR_MSK 0xf7ffffff
50007 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
50008 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_RESET 0x0
50009 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 field value from a register. */
50010 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
50011 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value suitable for setting the register. */
50012 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
50013 
50014 /*
50015  * Field : Mask Byte Control - mbc_4
50016  *
50017  * This array of bits are mask control bits for comparison of each of the MAC
50018  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50019  * received DA or SA with the contents of MAC Address44 high and low registers.
50020  * Each bit controls the masking of the bytes. You can filter a group of addresses
50021  * (known as group address filtering) by masking one or more bytes of the address.
50022  *
50023  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50024  *
50025  * Field Enumeration Values:
50026  *
50027  * Enum | Value | Description
50028  * :----------------------------------------------|:------|:------------------------------------
50029  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50030  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50031  *
50032  * Field Access Macros:
50033  *
50034  */
50035 /*
50036  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4
50037  *
50038  * Byte is unmasked (i.e. is compared)
50039  */
50040 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED 0x0
50041 /*
50042  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4
50043  *
50044  * Byte is masked (i.e. not compared)
50045  */
50046 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED 0x1
50047 
50048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
50049 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_LSB 28
50050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
50051 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_MSB 28
50052 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
50053 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_WIDTH 1
50054 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */
50055 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET_MSK 0x10000000
50056 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */
50057 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_CLR_MSK 0xefffffff
50058 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
50059 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_RESET 0x0
50060 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 field value from a register. */
50061 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
50062 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value suitable for setting the register. */
50063 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
50064 
50065 /*
50066  * Field : Mask Byte Control - mbc_5
50067  *
50068  * This array of bits are mask control bits for comparison of each of the MAC
50069  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50070  * received DA or SA with the contents of MAC Address44 high and low registers.
50071  * Each bit controls the masking of the bytes. You can filter a group of addresses
50072  * (known as group address filtering) by masking one or more bytes of the address.
50073  *
50074  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50075  *
50076  * Field Enumeration Values:
50077  *
50078  * Enum | Value | Description
50079  * :----------------------------------------------|:------|:------------------------------------
50080  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50081  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50082  *
50083  * Field Access Macros:
50084  *
50085  */
50086 /*
50087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5
50088  *
50089  * Byte is unmasked (i.e. is compared)
50090  */
50091 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED 0x0
50092 /*
50093  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5
50094  *
50095  * Byte is masked (i.e. not compared)
50096  */
50097 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED 0x1
50098 
50099 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
50100 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_LSB 29
50101 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
50102 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_MSB 29
50103 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
50104 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_WIDTH 1
50105 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */
50106 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET_MSK 0x20000000
50107 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */
50108 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_CLR_MSK 0xdfffffff
50109 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
50110 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_RESET 0x0
50111 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 field value from a register. */
50112 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
50113 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value suitable for setting the register. */
50114 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
50115 
50116 /*
50117  * Field : Source Address - sa
50118  *
50119  * When this bit is enabled, the MAC Address44[47:0] is used to compare with the SA
50120  * fields of the received frame. When this bit is disabled, the MAC Address44[47:0]
50121  * is used to compare with the DA fields of the received frame.
50122  *
50123  * Field Enumeration Values:
50124  *
50125  * Enum | Value | Description
50126  * :----------------------------------------|:------|:-----------------------------
50127  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
50128  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END | 0x1 | MAC address compare enabled
50129  *
50130  * Field Access Macros:
50131  *
50132  */
50133 /*
50134  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA
50135  *
50136  * MAC address compare disabled
50137  */
50138 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD 0x0
50139 /*
50140  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA
50141  *
50142  * MAC address compare enabled
50143  */
50144 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END 0x1
50145 
50146 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
50147 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_LSB 30
50148 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
50149 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_MSB 30
50150 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
50151 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_WIDTH 1
50152 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */
50153 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET_MSK 0x40000000
50154 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */
50155 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_CLR_MSK 0xbfffffff
50156 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
50157 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_RESET 0x0
50158 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA field value from a register. */
50159 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
50160 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value suitable for setting the register. */
50161 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
50162 
50163 /*
50164  * Field : Address Enable - ae
50165  *
50166  * When this bit is enabled, the address filter block uses the 45th MAC address for
50167  * perfect filtering. When this bit is disabled, the address filter block ignores
50168  * the address for filtering.
50169  *
50170  * Field Enumeration Values:
50171  *
50172  * Enum | Value | Description
50173  * :----------------------------------------|:------|:--------------------------------------
50174  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
50175  * ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
50176  *
50177  * Field Access Macros:
50178  *
50179  */
50180 /*
50181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
50182  *
50183  * Second MAC address filtering disabled
50184  */
50185 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD 0x0
50186 /*
50187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
50188  *
50189  * Second MAC address filtering enabled
50190  */
50191 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END 0x1
50192 
50193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
50194 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_LSB 31
50195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
50196 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_MSB 31
50197 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
50198 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_WIDTH 1
50199 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
50200 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET_MSK 0x80000000
50201 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
50202 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_CLR_MSK 0x7fffffff
50203 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
50204 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_RESET 0x0
50205 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE field value from a register. */
50206 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50207 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value suitable for setting the register. */
50208 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50209 
50210 #ifndef __ASSEMBLY__
50211 /*
50212  * WARNING: The C register and register group struct declarations are provided for
50213  * convenience and illustrative purposes. They should, however, be used with
50214  * caution as the C language standard provides no guarantees about the alignment or
50215  * atomicity of device memory accesses. The recommended practice for writing
50216  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50217  * alt_write_word() functions.
50218  *
50219  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH.
50220  */
50221 struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s
50222 {
50223  uint32_t addrhi : 16; /* MAC Address44 [47:32] */
50224  uint32_t : 8; /* *UNDEFINED* */
50225  uint32_t mbc_0 : 1; /* Mask Byte Control */
50226  uint32_t mbc_1 : 1; /* Mask Byte Control */
50227  uint32_t mbc_2 : 1; /* Mask Byte Control */
50228  uint32_t mbc_3 : 1; /* Mask Byte Control */
50229  uint32_t mbc_4 : 1; /* Mask Byte Control */
50230  uint32_t mbc_5 : 1; /* Mask Byte Control */
50231  uint32_t sa : 1; /* Source Address */
50232  uint32_t ae : 1; /* Address Enable */
50233 };
50234 
50235 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH. */
50236 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t;
50237 #endif /* __ASSEMBLY__ */
50238 
50239 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register from the beginning of the component. */
50240 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST 0x8e0
50241 /* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register. */
50242 #define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST))
50243 
50244 /*
50245  * Register : Register 569 (MAC Address44 Low Register) - MAC_Address44_Low
50246  *
50247  * The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC
50248  * address of the station.
50249  *
50250  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
50251  * format.
50252  *
50253  * Register Layout
50254  *
50255  * Bits | Access | Reset | Description
50256  * :-------|:-------|:-----------|:---------------------
50257  * [31:0] | RW | 0xffffffff | MAC Address44 [31:0]
50258  *
50259  */
50260 /*
50261  * Field : MAC Address44 [31:0] - addrlo
50262  *
50263  * This field contains the lower 32 bits of the 45th 6-byte MAC address. The
50264  * content of this field is undefined until loaded by software after the
50265  * initialization process.
50266  *
50267  * Field Access Macros:
50268  *
50269  */
50270 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
50271 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_LSB 0
50272 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
50273 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_MSB 31
50274 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
50275 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_WIDTH 32
50276 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
50277 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET_MSK 0xffffffff
50278 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
50279 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_CLR_MSK 0x00000000
50280 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
50281 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_RESET 0xffffffff
50282 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO field value from a register. */
50283 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50284 /* Produces a ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value suitable for setting the register. */
50285 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50286 
50287 #ifndef __ASSEMBLY__
50288 /*
50289  * WARNING: The C register and register group struct declarations are provided for
50290  * convenience and illustrative purposes. They should, however, be used with
50291  * caution as the C language standard provides no guarantees about the alignment or
50292  * atomicity of device memory accesses. The recommended practice for writing
50293  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50294  * alt_write_word() functions.
50295  *
50296  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW.
50297  */
50298 struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s
50299 {
50300  uint32_t addrlo : 32; /* MAC Address44 [31:0] */
50301 };
50302 
50303 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW. */
50304 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s ALT_EMAC_GMAC_MAC_ADDR44_LOW_t;
50305 #endif /* __ASSEMBLY__ */
50306 
50307 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register from the beginning of the component. */
50308 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST 0x8e4
50309 /* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register. */
50310 #define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST))
50311 
50312 /*
50313  * Register : Register 570 (MAC Address45 High Register) - MAC_Address45_High
50314  *
50315  * The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC
50316  * address of the station. Because the MAC address registers are configured to be
50317  * double-synchronized to the (G)MII clock domains, the synchronization is
50318  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
50319  * endian mode) of the MAC Address45 Low Register are written. For proper
50320  * synchronization updates, the consecutive writes to this Address Low Register
50321  * should be performed after at least four clock cycles in the destination clock
50322  * domain.
50323  *
50324  * Note that all MAC Address High registers (except MAC Address0 High) have the
50325  * same format.
50326  *
50327  * Register Layout
50328  *
50329  * Bits | Access | Reset | Description
50330  * :--------|:-------|:-------|:----------------------
50331  * [15:0] | RW | 0xffff | MAC Address45 [47:32]
50332  * [23:16] | ??? | 0x0 | *UNDEFINED*
50333  * [24] | RW | 0x0 | Mask Byte Control
50334  * [25] | RW | 0x0 | Mask Byte Control
50335  * [26] | RW | 0x0 | Mask Byte Control
50336  * [27] | RW | 0x0 | Mask Byte Control
50337  * [28] | RW | 0x0 | Mask Byte Control
50338  * [29] | RW | 0x0 | Mask Byte Control
50339  * [30] | RW | 0x0 | Source Address
50340  * [31] | RW | 0x0 | Address Enable
50341  *
50342  */
50343 /*
50344  * Field : MAC Address45 [47:32] - addrhi
50345  *
50346  * This field contains the upper 16 bits (47:32) of the 46th 6-byte MAC address.
50347  *
50348  * Field Access Macros:
50349  *
50350  */
50351 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
50352 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_LSB 0
50353 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
50354 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_MSB 15
50355 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
50356 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_WIDTH 16
50357 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
50358 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET_MSK 0x0000ffff
50359 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
50360 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_CLR_MSK 0xffff0000
50361 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
50362 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_RESET 0xffff
50363 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI field value from a register. */
50364 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50365 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value suitable for setting the register. */
50366 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50367 
50368 /*
50369  * Field : Mask Byte Control - mbc_0
50370  *
50371  * This array of bits are mask control bits for comparison of each of the MAC
50372  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50373  * received DA or SA with the contents of MAC Address45 high and low registers.
50374  * Each bit controls the masking of the bytes. You can filter a group of addresses
50375  * (known as group address filtering) by masking one or more bytes of the address.
50376  *
50377  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50378  *
50379  * Field Enumeration Values:
50380  *
50381  * Enum | Value | Description
50382  * :----------------------------------------------|:------|:------------------------------------
50383  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50384  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50385  *
50386  * Field Access Macros:
50387  *
50388  */
50389 /*
50390  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0
50391  *
50392  * Byte is unmasked (i.e. is compared)
50393  */
50394 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED 0x0
50395 /*
50396  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0
50397  *
50398  * Byte is masked (i.e. not compared)
50399  */
50400 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED 0x1
50401 
50402 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
50403 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_LSB 24
50404 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
50405 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_MSB 24
50406 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
50407 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_WIDTH 1
50408 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */
50409 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET_MSK 0x01000000
50410 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */
50411 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_CLR_MSK 0xfeffffff
50412 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
50413 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_RESET 0x0
50414 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 field value from a register. */
50415 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
50416 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value suitable for setting the register. */
50417 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
50418 
50419 /*
50420  * Field : Mask Byte Control - mbc_1
50421  *
50422  * This array of bits are mask control bits for comparison of each of the MAC
50423  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50424  * received DA or SA with the contents of MAC Address45 high and low registers.
50425  * Each bit controls the masking of the bytes. You can filter a group of addresses
50426  * (known as group address filtering) by masking one or more bytes of the address.
50427  *
50428  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50429  *
50430  * Field Enumeration Values:
50431  *
50432  * Enum | Value | Description
50433  * :----------------------------------------------|:------|:------------------------------------
50434  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50435  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50436  *
50437  * Field Access Macros:
50438  *
50439  */
50440 /*
50441  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1
50442  *
50443  * Byte is unmasked (i.e. is compared)
50444  */
50445 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED 0x0
50446 /*
50447  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1
50448  *
50449  * Byte is masked (i.e. not compared)
50450  */
50451 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED 0x1
50452 
50453 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
50454 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_LSB 25
50455 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
50456 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_MSB 25
50457 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
50458 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_WIDTH 1
50459 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */
50460 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET_MSK 0x02000000
50461 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */
50462 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_CLR_MSK 0xfdffffff
50463 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
50464 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_RESET 0x0
50465 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 field value from a register. */
50466 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
50467 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value suitable for setting the register. */
50468 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
50469 
50470 /*
50471  * Field : Mask Byte Control - mbc_2
50472  *
50473  * This array of bits are mask control bits for comparison of each of the MAC
50474  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50475  * received DA or SA with the contents of MAC Address45 high and low registers.
50476  * Each bit controls the masking of the bytes. You can filter a group of addresses
50477  * (known as group address filtering) by masking one or more bytes of the address.
50478  *
50479  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50480  *
50481  * Field Enumeration Values:
50482  *
50483  * Enum | Value | Description
50484  * :----------------------------------------------|:------|:------------------------------------
50485  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50486  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50487  *
50488  * Field Access Macros:
50489  *
50490  */
50491 /*
50492  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2
50493  *
50494  * Byte is unmasked (i.e. is compared)
50495  */
50496 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED 0x0
50497 /*
50498  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2
50499  *
50500  * Byte is masked (i.e. not compared)
50501  */
50502 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED 0x1
50503 
50504 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
50505 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_LSB 26
50506 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
50507 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_MSB 26
50508 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
50509 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_WIDTH 1
50510 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */
50511 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET_MSK 0x04000000
50512 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */
50513 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_CLR_MSK 0xfbffffff
50514 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
50515 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_RESET 0x0
50516 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 field value from a register. */
50517 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
50518 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value suitable for setting the register. */
50519 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
50520 
50521 /*
50522  * Field : Mask Byte Control - mbc_3
50523  *
50524  * This array of bits are mask control bits for comparison of each of the MAC
50525  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50526  * received DA or SA with the contents of MAC Address45 high and low registers.
50527  * Each bit controls the masking of the bytes. You can filter a group of addresses
50528  * (known as group address filtering) by masking one or more bytes of the address.
50529  *
50530  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50531  *
50532  * Field Enumeration Values:
50533  *
50534  * Enum | Value | Description
50535  * :----------------------------------------------|:------|:------------------------------------
50536  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50537  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50538  *
50539  * Field Access Macros:
50540  *
50541  */
50542 /*
50543  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3
50544  *
50545  * Byte is unmasked (i.e. is compared)
50546  */
50547 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED 0x0
50548 /*
50549  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3
50550  *
50551  * Byte is masked (i.e. not compared)
50552  */
50553 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED 0x1
50554 
50555 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
50556 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_LSB 27
50557 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
50558 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_MSB 27
50559 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
50560 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_WIDTH 1
50561 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */
50562 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET_MSK 0x08000000
50563 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */
50564 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_CLR_MSK 0xf7ffffff
50565 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
50566 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_RESET 0x0
50567 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 field value from a register. */
50568 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
50569 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value suitable for setting the register. */
50570 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
50571 
50572 /*
50573  * Field : Mask Byte Control - mbc_4
50574  *
50575  * This array of bits are mask control bits for comparison of each of the MAC
50576  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50577  * received DA or SA with the contents of MAC Address45 high and low registers.
50578  * Each bit controls the masking of the bytes. You can filter a group of addresses
50579  * (known as group address filtering) by masking one or more bytes of the address.
50580  *
50581  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50582  *
50583  * Field Enumeration Values:
50584  *
50585  * Enum | Value | Description
50586  * :----------------------------------------------|:------|:------------------------------------
50587  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50588  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50589  *
50590  * Field Access Macros:
50591  *
50592  */
50593 /*
50594  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4
50595  *
50596  * Byte is unmasked (i.e. is compared)
50597  */
50598 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED 0x0
50599 /*
50600  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4
50601  *
50602  * Byte is masked (i.e. not compared)
50603  */
50604 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED 0x1
50605 
50606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
50607 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_LSB 28
50608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
50609 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_MSB 28
50610 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
50611 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_WIDTH 1
50612 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */
50613 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET_MSK 0x10000000
50614 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */
50615 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_CLR_MSK 0xefffffff
50616 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
50617 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_RESET 0x0
50618 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 field value from a register. */
50619 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
50620 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value suitable for setting the register. */
50621 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
50622 
50623 /*
50624  * Field : Mask Byte Control - mbc_5
50625  *
50626  * This array of bits are mask control bits for comparison of each of the MAC
50627  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50628  * received DA or SA with the contents of MAC Address45 high and low registers.
50629  * Each bit controls the masking of the bytes. You can filter a group of addresses
50630  * (known as group address filtering) by masking one or more bytes of the address.
50631  *
50632  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50633  *
50634  * Field Enumeration Values:
50635  *
50636  * Enum | Value | Description
50637  * :----------------------------------------------|:------|:------------------------------------
50638  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50639  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50640  *
50641  * Field Access Macros:
50642  *
50643  */
50644 /*
50645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5
50646  *
50647  * Byte is unmasked (i.e. is compared)
50648  */
50649 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED 0x0
50650 /*
50651  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5
50652  *
50653  * Byte is masked (i.e. not compared)
50654  */
50655 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED 0x1
50656 
50657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
50658 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_LSB 29
50659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
50660 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_MSB 29
50661 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
50662 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_WIDTH 1
50663 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */
50664 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET_MSK 0x20000000
50665 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */
50666 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_CLR_MSK 0xdfffffff
50667 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
50668 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_RESET 0x0
50669 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 field value from a register. */
50670 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
50671 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value suitable for setting the register. */
50672 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
50673 
50674 /*
50675  * Field : Source Address - sa
50676  *
50677  * When this bit is enabled, the MAC Address45[47:0] is used to compare with the SA
50678  * fields of the received frame. When this bit is disabled, the MAC Address45[47:0]
50679  * is used to compare with the DA fields of the received frame.
50680  *
50681  * Field Enumeration Values:
50682  *
50683  * Enum | Value | Description
50684  * :----------------------------------------|:------|:-----------------------------
50685  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
50686  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END | 0x1 | MAC address compare enabled
50687  *
50688  * Field Access Macros:
50689  *
50690  */
50691 /*
50692  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA
50693  *
50694  * MAC address compare disabled
50695  */
50696 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD 0x0
50697 /*
50698  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA
50699  *
50700  * MAC address compare enabled
50701  */
50702 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END 0x1
50703 
50704 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
50705 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_LSB 30
50706 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
50707 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_MSB 30
50708 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
50709 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_WIDTH 1
50710 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */
50711 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET_MSK 0x40000000
50712 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */
50713 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_CLR_MSK 0xbfffffff
50714 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
50715 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_RESET 0x0
50716 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA field value from a register. */
50717 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
50718 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value suitable for setting the register. */
50719 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
50720 
50721 /*
50722  * Field : Address Enable - ae
50723  *
50724  * When this bit is enabled, the address filter block uses the 46th MAC address for
50725  * perfect filtering. When this bit is disabled, the address filter block ignores
50726  * the address for filtering.
50727  *
50728  * Field Enumeration Values:
50729  *
50730  * Enum | Value | Description
50731  * :----------------------------------------|:------|:--------------------------------------
50732  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
50733  * ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
50734  *
50735  * Field Access Macros:
50736  *
50737  */
50738 /*
50739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
50740  *
50741  * Second MAC address filtering disabled
50742  */
50743 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD 0x0
50744 /*
50745  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
50746  *
50747  * Second MAC address filtering enabled
50748  */
50749 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END 0x1
50750 
50751 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
50752 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_LSB 31
50753 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
50754 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_MSB 31
50755 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
50756 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_WIDTH 1
50757 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
50758 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET_MSK 0x80000000
50759 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
50760 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_CLR_MSK 0x7fffffff
50761 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
50762 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_RESET 0x0
50763 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE field value from a register. */
50764 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
50765 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value suitable for setting the register. */
50766 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
50767 
50768 #ifndef __ASSEMBLY__
50769 /*
50770  * WARNING: The C register and register group struct declarations are provided for
50771  * convenience and illustrative purposes. They should, however, be used with
50772  * caution as the C language standard provides no guarantees about the alignment or
50773  * atomicity of device memory accesses. The recommended practice for writing
50774  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50775  * alt_write_word() functions.
50776  *
50777  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH.
50778  */
50779 struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s
50780 {
50781  uint32_t addrhi : 16; /* MAC Address45 [47:32] */
50782  uint32_t : 8; /* *UNDEFINED* */
50783  uint32_t mbc_0 : 1; /* Mask Byte Control */
50784  uint32_t mbc_1 : 1; /* Mask Byte Control */
50785  uint32_t mbc_2 : 1; /* Mask Byte Control */
50786  uint32_t mbc_3 : 1; /* Mask Byte Control */
50787  uint32_t mbc_4 : 1; /* Mask Byte Control */
50788  uint32_t mbc_5 : 1; /* Mask Byte Control */
50789  uint32_t sa : 1; /* Source Address */
50790  uint32_t ae : 1; /* Address Enable */
50791 };
50792 
50793 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH. */
50794 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t;
50795 #endif /* __ASSEMBLY__ */
50796 
50797 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register from the beginning of the component. */
50798 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST 0x8e8
50799 /* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register. */
50800 #define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST))
50801 
50802 /*
50803  * Register : Register 571 (MAC Address45 Low Register) - MAC_Address45_Low
50804  *
50805  * The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC
50806  * address of the station.
50807  *
50808  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
50809  * format.
50810  *
50811  * Register Layout
50812  *
50813  * Bits | Access | Reset | Description
50814  * :-------|:-------|:-----------|:---------------------
50815  * [31:0] | RW | 0xffffffff | MAC Address45 [31:0]
50816  *
50817  */
50818 /*
50819  * Field : MAC Address45 [31:0] - addrlo
50820  *
50821  * This field contains the lower 32 bits of the 46th 6-byte MAC address. The
50822  * content of this field is undefined until loaded by software after the
50823  * initialization process.
50824  *
50825  * Field Access Macros:
50826  *
50827  */
50828 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
50829 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_LSB 0
50830 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
50831 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_MSB 31
50832 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
50833 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_WIDTH 32
50834 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
50835 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET_MSK 0xffffffff
50836 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
50837 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_CLR_MSK 0x00000000
50838 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
50839 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_RESET 0xffffffff
50840 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO field value from a register. */
50841 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
50842 /* Produces a ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value suitable for setting the register. */
50843 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
50844 
50845 #ifndef __ASSEMBLY__
50846 /*
50847  * WARNING: The C register and register group struct declarations are provided for
50848  * convenience and illustrative purposes. They should, however, be used with
50849  * caution as the C language standard provides no guarantees about the alignment or
50850  * atomicity of device memory accesses. The recommended practice for writing
50851  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
50852  * alt_write_word() functions.
50853  *
50854  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW.
50855  */
50856 struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s
50857 {
50858  uint32_t addrlo : 32; /* MAC Address45 [31:0] */
50859 };
50860 
50861 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW. */
50862 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s ALT_EMAC_GMAC_MAC_ADDR45_LOW_t;
50863 #endif /* __ASSEMBLY__ */
50864 
50865 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register from the beginning of the component. */
50866 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST 0x8ec
50867 /* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register. */
50868 #define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST))
50869 
50870 /*
50871  * Register : Register 572 (MAC Address46 High Register) - MAC_Address46_High
50872  *
50873  * The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC
50874  * address of the station. Because the MAC address registers are configured to be
50875  * double-synchronized to the (G)MII clock domains, the synchronization is
50876  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
50877  * endian mode) of the MAC Address46 Low Register are written. For proper
50878  * synchronization updates, the consecutive writes to this Address Low Register
50879  * should be performed after at least four clock cycles in the destination clock
50880  * domain.
50881  *
50882  * Note that all MAC Address High registers (except MAC Address0 High) have the
50883  * same format.
50884  *
50885  * Register Layout
50886  *
50887  * Bits | Access | Reset | Description
50888  * :--------|:-------|:-------|:----------------------
50889  * [15:0] | RW | 0xffff | MAC Address46 [47:32]
50890  * [23:16] | ??? | 0x0 | *UNDEFINED*
50891  * [24] | RW | 0x0 | Mask Byte Control
50892  * [25] | RW | 0x0 | Mask Byte Control
50893  * [26] | RW | 0x0 | Mask Byte Control
50894  * [27] | RW | 0x0 | Mask Byte Control
50895  * [28] | RW | 0x0 | Mask Byte Control
50896  * [29] | RW | 0x0 | Mask Byte Control
50897  * [30] | RW | 0x0 | Source Address
50898  * [31] | RW | 0x0 | Address Enable
50899  *
50900  */
50901 /*
50902  * Field : MAC Address46 [47:32] - addrhi
50903  *
50904  * This field contains the upper 16 bits (47:32) of the 47th 6-byte MAC address.
50905  *
50906  * Field Access Macros:
50907  *
50908  */
50909 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
50910 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_LSB 0
50911 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
50912 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_MSB 15
50913 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
50914 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_WIDTH 16
50915 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
50916 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET_MSK 0x0000ffff
50917 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
50918 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_CLR_MSK 0xffff0000
50919 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
50920 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_RESET 0xffff
50921 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI field value from a register. */
50922 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
50923 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value suitable for setting the register. */
50924 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
50925 
50926 /*
50927  * Field : Mask Byte Control - mbc_0
50928  *
50929  * This array of bits are mask control bits for comparison of each of the MAC
50930  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50931  * received DA or SA with the contents of MAC Address46 high and low registers.
50932  * Each bit controls the masking of the bytes. You can filter a group of addresses
50933  * (known as group address filtering) by masking one or more bytes of the address.
50934  *
50935  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50936  *
50937  * Field Enumeration Values:
50938  *
50939  * Enum | Value | Description
50940  * :----------------------------------------------|:------|:------------------------------------
50941  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50942  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50943  *
50944  * Field Access Macros:
50945  *
50946  */
50947 /*
50948  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0
50949  *
50950  * Byte is unmasked (i.e. is compared)
50951  */
50952 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED 0x0
50953 /*
50954  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0
50955  *
50956  * Byte is masked (i.e. not compared)
50957  */
50958 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED 0x1
50959 
50960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
50961 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_LSB 24
50962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
50963 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_MSB 24
50964 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
50965 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_WIDTH 1
50966 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */
50967 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET_MSK 0x01000000
50968 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */
50969 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_CLR_MSK 0xfeffffff
50970 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
50971 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_RESET 0x0
50972 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 field value from a register. */
50973 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
50974 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value suitable for setting the register. */
50975 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
50976 
50977 /*
50978  * Field : Mask Byte Control - mbc_1
50979  *
50980  * This array of bits are mask control bits for comparison of each of the MAC
50981  * Address bytes. When masked, the MAC does not compare the corresponding byte of
50982  * received DA or SA with the contents of MAC Address46 high and low registers.
50983  * Each bit controls the masking of the bytes. You can filter a group of addresses
50984  * (known as group address filtering) by masking one or more bytes of the address.
50985  *
50986  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
50987  *
50988  * Field Enumeration Values:
50989  *
50990  * Enum | Value | Description
50991  * :----------------------------------------------|:------|:------------------------------------
50992  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
50993  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
50994  *
50995  * Field Access Macros:
50996  *
50997  */
50998 /*
50999  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1
51000  *
51001  * Byte is unmasked (i.e. is compared)
51002  */
51003 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED 0x0
51004 /*
51005  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1
51006  *
51007  * Byte is masked (i.e. not compared)
51008  */
51009 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED 0x1
51010 
51011 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
51012 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_LSB 25
51013 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
51014 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_MSB 25
51015 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
51016 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_WIDTH 1
51017 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */
51018 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET_MSK 0x02000000
51019 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */
51020 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_CLR_MSK 0xfdffffff
51021 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
51022 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_RESET 0x0
51023 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 field value from a register. */
51024 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
51025 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value suitable for setting the register. */
51026 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
51027 
51028 /*
51029  * Field : Mask Byte Control - mbc_2
51030  *
51031  * This array of bits are mask control bits for comparison of each of the MAC
51032  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51033  * received DA or SA with the contents of MAC Address46 high and low registers.
51034  * Each bit controls the masking of the bytes. You can filter a group of addresses
51035  * (known as group address filtering) by masking one or more bytes of the address.
51036  *
51037  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51038  *
51039  * Field Enumeration Values:
51040  *
51041  * Enum | Value | Description
51042  * :----------------------------------------------|:------|:------------------------------------
51043  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51044  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51045  *
51046  * Field Access Macros:
51047  *
51048  */
51049 /*
51050  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2
51051  *
51052  * Byte is unmasked (i.e. is compared)
51053  */
51054 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED 0x0
51055 /*
51056  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2
51057  *
51058  * Byte is masked (i.e. not compared)
51059  */
51060 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED 0x1
51061 
51062 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
51063 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_LSB 26
51064 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
51065 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_MSB 26
51066 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
51067 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_WIDTH 1
51068 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */
51069 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET_MSK 0x04000000
51070 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */
51071 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_CLR_MSK 0xfbffffff
51072 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
51073 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_RESET 0x0
51074 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 field value from a register. */
51075 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
51076 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value suitable for setting the register. */
51077 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
51078 
51079 /*
51080  * Field : Mask Byte Control - mbc_3
51081  *
51082  * This array of bits are mask control bits for comparison of each of the MAC
51083  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51084  * received DA or SA with the contents of MAC Address46 high and low registers.
51085  * Each bit controls the masking of the bytes. You can filter a group of addresses
51086  * (known as group address filtering) by masking one or more bytes of the address.
51087  *
51088  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51089  *
51090  * Field Enumeration Values:
51091  *
51092  * Enum | Value | Description
51093  * :----------------------------------------------|:------|:------------------------------------
51094  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51095  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51096  *
51097  * Field Access Macros:
51098  *
51099  */
51100 /*
51101  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3
51102  *
51103  * Byte is unmasked (i.e. is compared)
51104  */
51105 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED 0x0
51106 /*
51107  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3
51108  *
51109  * Byte is masked (i.e. not compared)
51110  */
51111 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED 0x1
51112 
51113 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
51114 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_LSB 27
51115 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
51116 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_MSB 27
51117 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
51118 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_WIDTH 1
51119 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */
51120 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET_MSK 0x08000000
51121 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */
51122 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_CLR_MSK 0xf7ffffff
51123 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
51124 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_RESET 0x0
51125 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 field value from a register. */
51126 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
51127 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value suitable for setting the register. */
51128 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
51129 
51130 /*
51131  * Field : Mask Byte Control - mbc_4
51132  *
51133  * This array of bits are mask control bits for comparison of each of the MAC
51134  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51135  * received DA or SA with the contents of MAC Address46 high and low registers.
51136  * Each bit controls the masking of the bytes. You can filter a group of addresses
51137  * (known as group address filtering) by masking one or more bytes of the address.
51138  *
51139  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51140  *
51141  * Field Enumeration Values:
51142  *
51143  * Enum | Value | Description
51144  * :----------------------------------------------|:------|:------------------------------------
51145  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51146  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51147  *
51148  * Field Access Macros:
51149  *
51150  */
51151 /*
51152  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4
51153  *
51154  * Byte is unmasked (i.e. is compared)
51155  */
51156 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED 0x0
51157 /*
51158  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4
51159  *
51160  * Byte is masked (i.e. not compared)
51161  */
51162 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED 0x1
51163 
51164 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
51165 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_LSB 28
51166 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
51167 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_MSB 28
51168 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
51169 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_WIDTH 1
51170 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */
51171 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET_MSK 0x10000000
51172 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */
51173 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_CLR_MSK 0xefffffff
51174 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
51175 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_RESET 0x0
51176 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 field value from a register. */
51177 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
51178 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value suitable for setting the register. */
51179 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
51180 
51181 /*
51182  * Field : Mask Byte Control - mbc_5
51183  *
51184  * This array of bits are mask control bits for comparison of each of the MAC
51185  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51186  * received DA or SA with the contents of MAC Address46 high and low registers.
51187  * Each bit controls the masking of the bytes. You can filter a group of addresses
51188  * (known as group address filtering) by masking one or more bytes of the address.
51189  *
51190  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51191  *
51192  * Field Enumeration Values:
51193  *
51194  * Enum | Value | Description
51195  * :----------------------------------------------|:------|:------------------------------------
51196  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51197  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51198  *
51199  * Field Access Macros:
51200  *
51201  */
51202 /*
51203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5
51204  *
51205  * Byte is unmasked (i.e. is compared)
51206  */
51207 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED 0x0
51208 /*
51209  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5
51210  *
51211  * Byte is masked (i.e. not compared)
51212  */
51213 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED 0x1
51214 
51215 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
51216 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_LSB 29
51217 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
51218 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_MSB 29
51219 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
51220 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_WIDTH 1
51221 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */
51222 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET_MSK 0x20000000
51223 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */
51224 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_CLR_MSK 0xdfffffff
51225 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
51226 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_RESET 0x0
51227 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 field value from a register. */
51228 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
51229 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value suitable for setting the register. */
51230 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
51231 
51232 /*
51233  * Field : Source Address - sa
51234  *
51235  * When this bit is enabled, the MAC Address46[47:0] is used to compare with the SA
51236  * fields of the received frame. When this bit is disabled, the MAC Address46[47:0]
51237  * is used to compare with the DA fields of the received frame.
51238  *
51239  * Field Enumeration Values:
51240  *
51241  * Enum | Value | Description
51242  * :----------------------------------------|:------|:-----------------------------
51243  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
51244  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END | 0x1 | MAC address compare enabled
51245  *
51246  * Field Access Macros:
51247  *
51248  */
51249 /*
51250  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA
51251  *
51252  * MAC address compare disabled
51253  */
51254 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD 0x0
51255 /*
51256  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA
51257  *
51258  * MAC address compare enabled
51259  */
51260 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END 0x1
51261 
51262 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
51263 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_LSB 30
51264 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
51265 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_MSB 30
51266 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
51267 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_WIDTH 1
51268 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */
51269 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET_MSK 0x40000000
51270 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */
51271 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_CLR_MSK 0xbfffffff
51272 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
51273 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_RESET 0x0
51274 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA field value from a register. */
51275 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
51276 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value suitable for setting the register. */
51277 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
51278 
51279 /*
51280  * Field : Address Enable - ae
51281  *
51282  * When this bit is enabled, the address filter block uses the 47th MAC address for
51283  * perfect filtering. When this bit is disabled, the address filter block ignores
51284  * the address for filtering.
51285  *
51286  * Field Enumeration Values:
51287  *
51288  * Enum | Value | Description
51289  * :----------------------------------------|:------|:--------------------------------------
51290  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
51291  * ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
51292  *
51293  * Field Access Macros:
51294  *
51295  */
51296 /*
51297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
51298  *
51299  * Second MAC address filtering disabled
51300  */
51301 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD 0x0
51302 /*
51303  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
51304  *
51305  * Second MAC address filtering enabled
51306  */
51307 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END 0x1
51308 
51309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
51310 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_LSB 31
51311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
51312 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_MSB 31
51313 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
51314 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_WIDTH 1
51315 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
51316 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET_MSK 0x80000000
51317 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
51318 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_CLR_MSK 0x7fffffff
51319 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
51320 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_RESET 0x0
51321 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE field value from a register. */
51322 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51323 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value suitable for setting the register. */
51324 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51325 
51326 #ifndef __ASSEMBLY__
51327 /*
51328  * WARNING: The C register and register group struct declarations are provided for
51329  * convenience and illustrative purposes. They should, however, be used with
51330  * caution as the C language standard provides no guarantees about the alignment or
51331  * atomicity of device memory accesses. The recommended practice for writing
51332  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51333  * alt_write_word() functions.
51334  *
51335  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH.
51336  */
51337 struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s
51338 {
51339  uint32_t addrhi : 16; /* MAC Address46 [47:32] */
51340  uint32_t : 8; /* *UNDEFINED* */
51341  uint32_t mbc_0 : 1; /* Mask Byte Control */
51342  uint32_t mbc_1 : 1; /* Mask Byte Control */
51343  uint32_t mbc_2 : 1; /* Mask Byte Control */
51344  uint32_t mbc_3 : 1; /* Mask Byte Control */
51345  uint32_t mbc_4 : 1; /* Mask Byte Control */
51346  uint32_t mbc_5 : 1; /* Mask Byte Control */
51347  uint32_t sa : 1; /* Source Address */
51348  uint32_t ae : 1; /* Address Enable */
51349 };
51350 
51351 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH. */
51352 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t;
51353 #endif /* __ASSEMBLY__ */
51354 
51355 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register from the beginning of the component. */
51356 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST 0x8f0
51357 /* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register. */
51358 #define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST))
51359 
51360 /*
51361  * Register : Register 573 (MAC Address46 Low Register) - MAC_Address46_Low
51362  *
51363  * The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC
51364  * address of the station.
51365  *
51366  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
51367  * format.
51368  *
51369  * Register Layout
51370  *
51371  * Bits | Access | Reset | Description
51372  * :-------|:-------|:-----------|:---------------------
51373  * [31:0] | RW | 0xffffffff | MAC Address46 [31:0]
51374  *
51375  */
51376 /*
51377  * Field : MAC Address46 [31:0] - addrlo
51378  *
51379  * This field contains the lower 32 bits of the 47th 6-byte MAC address. The
51380  * content of this field is undefined until loaded by software after the
51381  * initialization process.
51382  *
51383  * Field Access Macros:
51384  *
51385  */
51386 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
51387 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_LSB 0
51388 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
51389 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_MSB 31
51390 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
51391 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_WIDTH 32
51392 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
51393 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET_MSK 0xffffffff
51394 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
51395 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_CLR_MSK 0x00000000
51396 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
51397 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_RESET 0xffffffff
51398 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO field value from a register. */
51399 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51400 /* Produces a ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value suitable for setting the register. */
51401 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51402 
51403 #ifndef __ASSEMBLY__
51404 /*
51405  * WARNING: The C register and register group struct declarations are provided for
51406  * convenience and illustrative purposes. They should, however, be used with
51407  * caution as the C language standard provides no guarantees about the alignment or
51408  * atomicity of device memory accesses. The recommended practice for writing
51409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51410  * alt_write_word() functions.
51411  *
51412  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW.
51413  */
51414 struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s
51415 {
51416  uint32_t addrlo : 32; /* MAC Address46 [31:0] */
51417 };
51418 
51419 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW. */
51420 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s ALT_EMAC_GMAC_MAC_ADDR46_LOW_t;
51421 #endif /* __ASSEMBLY__ */
51422 
51423 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register from the beginning of the component. */
51424 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST 0x8f4
51425 /* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register. */
51426 #define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST))
51427 
51428 /*
51429  * Register : Register 574 (MAC Address47 High Register) - MAC_Address47_High
51430  *
51431  * The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC
51432  * address of the station. Because the MAC address registers are configured to be
51433  * double-synchronized to the (G)MII clock domains, the synchronization is
51434  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
51435  * endian mode) of the MAC Address47 Low Register are written. For proper
51436  * synchronization updates, the consecutive writes to this Address Low Register
51437  * should be performed after at least four clock cycles in the destination clock
51438  * domain.
51439  *
51440  * Note that all MAC Address High registers (except MAC Address0 High) have the
51441  * same format.
51442  *
51443  * Register Layout
51444  *
51445  * Bits | Access | Reset | Description
51446  * :--------|:-------|:-------|:----------------------
51447  * [15:0] | RW | 0xffff | MAC Address47 [47:32]
51448  * [23:16] | ??? | 0x0 | *UNDEFINED*
51449  * [24] | RW | 0x0 | Mask Byte Control
51450  * [25] | RW | 0x0 | Mask Byte Control
51451  * [26] | RW | 0x0 | Mask Byte Control
51452  * [27] | RW | 0x0 | Mask Byte Control
51453  * [28] | RW | 0x0 | Mask Byte Control
51454  * [29] | RW | 0x0 | Mask Byte Control
51455  * [30] | RW | 0x0 | Source Address
51456  * [31] | RW | 0x0 | Address Enable
51457  *
51458  */
51459 /*
51460  * Field : MAC Address47 [47:32] - addrhi
51461  *
51462  * This field contains the upper 16 bits (47:32) of the 48th 6-byte MAC address.
51463  *
51464  * Field Access Macros:
51465  *
51466  */
51467 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
51468 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_LSB 0
51469 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
51470 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_MSB 15
51471 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
51472 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_WIDTH 16
51473 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
51474 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET_MSK 0x0000ffff
51475 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
51476 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_CLR_MSK 0xffff0000
51477 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
51478 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_RESET 0xffff
51479 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI field value from a register. */
51480 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
51481 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value suitable for setting the register. */
51482 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
51483 
51484 /*
51485  * Field : Mask Byte Control - mbc_0
51486  *
51487  * This array of bits are mask control bits for comparison of each of the MAC
51488  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51489  * received DA or SA with the contents of MAC Address47 high and low registers.
51490  * Each bit controls the masking of the bytes. You can filter a group of addresses
51491  * (known as group address filtering) by masking one or more bytes of the address.
51492  *
51493  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51494  *
51495  * Field Enumeration Values:
51496  *
51497  * Enum | Value | Description
51498  * :----------------------------------------------|:------|:------------------------------------
51499  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51500  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51501  *
51502  * Field Access Macros:
51503  *
51504  */
51505 /*
51506  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0
51507  *
51508  * Byte is unmasked (i.e. is compared)
51509  */
51510 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED 0x0
51511 /*
51512  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0
51513  *
51514  * Byte is masked (i.e. not compared)
51515  */
51516 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED 0x1
51517 
51518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
51519 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_LSB 24
51520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
51521 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_MSB 24
51522 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
51523 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_WIDTH 1
51524 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */
51525 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET_MSK 0x01000000
51526 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */
51527 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_CLR_MSK 0xfeffffff
51528 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
51529 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_RESET 0x0
51530 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 field value from a register. */
51531 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
51532 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value suitable for setting the register. */
51533 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
51534 
51535 /*
51536  * Field : Mask Byte Control - mbc_1
51537  *
51538  * This array of bits are mask control bits for comparison of each of the MAC
51539  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51540  * received DA or SA with the contents of MAC Address47 high and low registers.
51541  * Each bit controls the masking of the bytes. You can filter a group of addresses
51542  * (known as group address filtering) by masking one or more bytes of the address.
51543  *
51544  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51545  *
51546  * Field Enumeration Values:
51547  *
51548  * Enum | Value | Description
51549  * :----------------------------------------------|:------|:------------------------------------
51550  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51551  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51552  *
51553  * Field Access Macros:
51554  *
51555  */
51556 /*
51557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1
51558  *
51559  * Byte is unmasked (i.e. is compared)
51560  */
51561 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED 0x0
51562 /*
51563  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1
51564  *
51565  * Byte is masked (i.e. not compared)
51566  */
51567 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED 0x1
51568 
51569 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
51570 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_LSB 25
51571 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
51572 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_MSB 25
51573 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
51574 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_WIDTH 1
51575 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */
51576 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET_MSK 0x02000000
51577 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */
51578 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_CLR_MSK 0xfdffffff
51579 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
51580 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_RESET 0x0
51581 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 field value from a register. */
51582 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
51583 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value suitable for setting the register. */
51584 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
51585 
51586 /*
51587  * Field : Mask Byte Control - mbc_2
51588  *
51589  * This array of bits are mask control bits for comparison of each of the MAC
51590  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51591  * received DA or SA with the contents of MAC Address47 high and low registers.
51592  * Each bit controls the masking of the bytes. You can filter a group of addresses
51593  * (known as group address filtering) by masking one or more bytes of the address.
51594  *
51595  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51596  *
51597  * Field Enumeration Values:
51598  *
51599  * Enum | Value | Description
51600  * :----------------------------------------------|:------|:------------------------------------
51601  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51602  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51603  *
51604  * Field Access Macros:
51605  *
51606  */
51607 /*
51608  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2
51609  *
51610  * Byte is unmasked (i.e. is compared)
51611  */
51612 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED 0x0
51613 /*
51614  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2
51615  *
51616  * Byte is masked (i.e. not compared)
51617  */
51618 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED 0x1
51619 
51620 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
51621 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_LSB 26
51622 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
51623 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_MSB 26
51624 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
51625 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_WIDTH 1
51626 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */
51627 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET_MSK 0x04000000
51628 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */
51629 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_CLR_MSK 0xfbffffff
51630 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
51631 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_RESET 0x0
51632 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 field value from a register. */
51633 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
51634 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value suitable for setting the register. */
51635 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
51636 
51637 /*
51638  * Field : Mask Byte Control - mbc_3
51639  *
51640  * This array of bits are mask control bits for comparison of each of the MAC
51641  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51642  * received DA or SA with the contents of MAC Address47 high and low registers.
51643  * Each bit controls the masking of the bytes. You can filter a group of addresses
51644  * (known as group address filtering) by masking one or more bytes of the address.
51645  *
51646  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51647  *
51648  * Field Enumeration Values:
51649  *
51650  * Enum | Value | Description
51651  * :----------------------------------------------|:------|:------------------------------------
51652  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51653  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51654  *
51655  * Field Access Macros:
51656  *
51657  */
51658 /*
51659  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3
51660  *
51661  * Byte is unmasked (i.e. is compared)
51662  */
51663 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED 0x0
51664 /*
51665  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3
51666  *
51667  * Byte is masked (i.e. not compared)
51668  */
51669 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED 0x1
51670 
51671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
51672 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_LSB 27
51673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
51674 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_MSB 27
51675 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
51676 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_WIDTH 1
51677 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */
51678 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET_MSK 0x08000000
51679 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */
51680 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_CLR_MSK 0xf7ffffff
51681 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
51682 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_RESET 0x0
51683 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 field value from a register. */
51684 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
51685 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value suitable for setting the register. */
51686 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
51687 
51688 /*
51689  * Field : Mask Byte Control - mbc_4
51690  *
51691  * This array of bits are mask control bits for comparison of each of the MAC
51692  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51693  * received DA or SA with the contents of MAC Address47 high and low registers.
51694  * Each bit controls the masking of the bytes. You can filter a group of addresses
51695  * (known as group address filtering) by masking one or more bytes of the address.
51696  *
51697  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51698  *
51699  * Field Enumeration Values:
51700  *
51701  * Enum | Value | Description
51702  * :----------------------------------------------|:------|:------------------------------------
51703  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51704  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51705  *
51706  * Field Access Macros:
51707  *
51708  */
51709 /*
51710  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4
51711  *
51712  * Byte is unmasked (i.e. is compared)
51713  */
51714 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED 0x0
51715 /*
51716  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4
51717  *
51718  * Byte is masked (i.e. not compared)
51719  */
51720 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED 0x1
51721 
51722 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
51723 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_LSB 28
51724 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
51725 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_MSB 28
51726 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
51727 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_WIDTH 1
51728 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */
51729 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET_MSK 0x10000000
51730 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */
51731 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_CLR_MSK 0xefffffff
51732 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
51733 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_RESET 0x0
51734 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 field value from a register. */
51735 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
51736 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value suitable for setting the register. */
51737 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
51738 
51739 /*
51740  * Field : Mask Byte Control - mbc_5
51741  *
51742  * This array of bits are mask control bits for comparison of each of the MAC
51743  * Address bytes. When masked, the MAC does not compare the corresponding byte of
51744  * received DA or SA with the contents of MAC Address47 high and low registers.
51745  * Each bit controls the masking of the bytes. You can filter a group of addresses
51746  * (known as group address filtering) by masking one or more bytes of the address.
51747  *
51748  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
51749  *
51750  * Field Enumeration Values:
51751  *
51752  * Enum | Value | Description
51753  * :----------------------------------------------|:------|:------------------------------------
51754  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
51755  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
51756  *
51757  * Field Access Macros:
51758  *
51759  */
51760 /*
51761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5
51762  *
51763  * Byte is unmasked (i.e. is compared)
51764  */
51765 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED 0x0
51766 /*
51767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5
51768  *
51769  * Byte is masked (i.e. not compared)
51770  */
51771 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED 0x1
51772 
51773 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
51774 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_LSB 29
51775 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
51776 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_MSB 29
51777 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
51778 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_WIDTH 1
51779 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */
51780 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET_MSK 0x20000000
51781 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */
51782 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_CLR_MSK 0xdfffffff
51783 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
51784 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_RESET 0x0
51785 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 field value from a register. */
51786 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
51787 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value suitable for setting the register. */
51788 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
51789 
51790 /*
51791  * Field : Source Address - sa
51792  *
51793  * When this bit is enabled, the MAC Address47[47:0] is used to compare with the SA
51794  * fields of the received frame. When this bit is disabled, the MAC Address47[47:0]
51795  * is used to compare with the DA fields of the received frame.
51796  *
51797  * Field Enumeration Values:
51798  *
51799  * Enum | Value | Description
51800  * :----------------------------------------|:------|:-----------------------------
51801  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
51802  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END | 0x1 | MAC address compare enabled
51803  *
51804  * Field Access Macros:
51805  *
51806  */
51807 /*
51808  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA
51809  *
51810  * MAC address compare disabled
51811  */
51812 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD 0x0
51813 /*
51814  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA
51815  *
51816  * MAC address compare enabled
51817  */
51818 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END 0x1
51819 
51820 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
51821 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_LSB 30
51822 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
51823 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_MSB 30
51824 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
51825 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_WIDTH 1
51826 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */
51827 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET_MSK 0x40000000
51828 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */
51829 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_CLR_MSK 0xbfffffff
51830 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
51831 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_RESET 0x0
51832 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA field value from a register. */
51833 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
51834 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value suitable for setting the register. */
51835 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
51836 
51837 /*
51838  * Field : Address Enable - ae
51839  *
51840  * When this bit is enabled, the address filter block uses the 48th MAC address for
51841  * perfect filtering. When this bit is disabled, the address filter block ignores
51842  * the address for filtering.
51843  *
51844  * Field Enumeration Values:
51845  *
51846  * Enum | Value | Description
51847  * :----------------------------------------|:------|:--------------------------------------
51848  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
51849  * ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
51850  *
51851  * Field Access Macros:
51852  *
51853  */
51854 /*
51855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
51856  *
51857  * Second MAC address filtering disabled
51858  */
51859 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD 0x0
51860 /*
51861  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
51862  *
51863  * Second MAC address filtering enabled
51864  */
51865 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END 0x1
51866 
51867 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
51868 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_LSB 31
51869 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
51870 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_MSB 31
51871 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
51872 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_WIDTH 1
51873 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
51874 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET_MSK 0x80000000
51875 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
51876 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_CLR_MSK 0x7fffffff
51877 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
51878 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_RESET 0x0
51879 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE field value from a register. */
51880 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
51881 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value suitable for setting the register. */
51882 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
51883 
51884 #ifndef __ASSEMBLY__
51885 /*
51886  * WARNING: The C register and register group struct declarations are provided for
51887  * convenience and illustrative purposes. They should, however, be used with
51888  * caution as the C language standard provides no guarantees about the alignment or
51889  * atomicity of device memory accesses. The recommended practice for writing
51890  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51891  * alt_write_word() functions.
51892  *
51893  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH.
51894  */
51895 struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s
51896 {
51897  uint32_t addrhi : 16; /* MAC Address47 [47:32] */
51898  uint32_t : 8; /* *UNDEFINED* */
51899  uint32_t mbc_0 : 1; /* Mask Byte Control */
51900  uint32_t mbc_1 : 1; /* Mask Byte Control */
51901  uint32_t mbc_2 : 1; /* Mask Byte Control */
51902  uint32_t mbc_3 : 1; /* Mask Byte Control */
51903  uint32_t mbc_4 : 1; /* Mask Byte Control */
51904  uint32_t mbc_5 : 1; /* Mask Byte Control */
51905  uint32_t sa : 1; /* Source Address */
51906  uint32_t ae : 1; /* Address Enable */
51907 };
51908 
51909 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH. */
51910 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t;
51911 #endif /* __ASSEMBLY__ */
51912 
51913 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register from the beginning of the component. */
51914 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST 0x8f8
51915 /* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register. */
51916 #define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST))
51917 
51918 /*
51919  * Register : Register 575 (MAC Address47 Low Register) - MAC_Address47_Low
51920  *
51921  * The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC
51922  * address of the station.
51923  *
51924  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
51925  * format.
51926  *
51927  * Register Layout
51928  *
51929  * Bits | Access | Reset | Description
51930  * :-------|:-------|:-----------|:---------------------
51931  * [31:0] | RW | 0xffffffff | MAC Address47 [31:0]
51932  *
51933  */
51934 /*
51935  * Field : MAC Address47 [31:0] - addrlo
51936  *
51937  * This field contains the lower 32 bits of the 48th 6-byte MAC address. The
51938  * content of this field is undefined until loaded by software after the
51939  * initialization process.
51940  *
51941  * Field Access Macros:
51942  *
51943  */
51944 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
51945 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_LSB 0
51946 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
51947 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_MSB 31
51948 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
51949 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_WIDTH 32
51950 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
51951 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET_MSK 0xffffffff
51952 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
51953 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_CLR_MSK 0x00000000
51954 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
51955 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_RESET 0xffffffff
51956 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO field value from a register. */
51957 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
51958 /* Produces a ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value suitable for setting the register. */
51959 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
51960 
51961 #ifndef __ASSEMBLY__
51962 /*
51963  * WARNING: The C register and register group struct declarations are provided for
51964  * convenience and illustrative purposes. They should, however, be used with
51965  * caution as the C language standard provides no guarantees about the alignment or
51966  * atomicity of device memory accesses. The recommended practice for writing
51967  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
51968  * alt_write_word() functions.
51969  *
51970  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW.
51971  */
51972 struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s
51973 {
51974  uint32_t addrlo : 32; /* MAC Address47 [31:0] */
51975 };
51976 
51977 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW. */
51978 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s ALT_EMAC_GMAC_MAC_ADDR47_LOW_t;
51979 #endif /* __ASSEMBLY__ */
51980 
51981 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register from the beginning of the component. */
51982 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST 0x8fc
51983 /* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register. */
51984 #define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST))
51985 
51986 /*
51987  * Register : Register 576 (MAC Address48 High Register) - MAC_Address48_High
51988  *
51989  * The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC
51990  * address of the station. Because the MAC address registers are configured to be
51991  * double-synchronized to the (G)MII clock domains, the synchronization is
51992  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
51993  * endian mode) of the MAC Address48 Low Register are written. For proper
51994  * synchronization updates, the consecutive writes to this Address Low Register
51995  * should be performed after at least four clock cycles in the destination clock
51996  * domain.
51997  *
51998  * Note that all MAC Address High registers (except MAC Address0 High) have the
51999  * same format.
52000  *
52001  * Register Layout
52002  *
52003  * Bits | Access | Reset | Description
52004  * :--------|:-------|:-------|:----------------------
52005  * [15:0] | RW | 0xffff | MAC Address48 [47:32]
52006  * [23:16] | ??? | 0x0 | *UNDEFINED*
52007  * [24] | RW | 0x0 | Mask Byte Control
52008  * [25] | RW | 0x0 | Mask Byte Control
52009  * [26] | RW | 0x0 | Mask Byte Control
52010  * [27] | RW | 0x0 | Mask Byte Control
52011  * [28] | RW | 0x0 | Mask Byte Control
52012  * [29] | RW | 0x0 | Mask Byte Control
52013  * [30] | RW | 0x0 | Source Address
52014  * [31] | RW | 0x0 | Address Enable
52015  *
52016  */
52017 /*
52018  * Field : MAC Address48 [47:32] - addrhi
52019  *
52020  * This field contains the upper 16 bits (47:32) of the 49th 6-byte MAC address.
52021  *
52022  * Field Access Macros:
52023  *
52024  */
52025 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
52026 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_LSB 0
52027 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
52028 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_MSB 15
52029 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
52030 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_WIDTH 16
52031 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
52032 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET_MSK 0x0000ffff
52033 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
52034 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_CLR_MSK 0xffff0000
52035 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
52036 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_RESET 0xffff
52037 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI field value from a register. */
52038 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52039 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value suitable for setting the register. */
52040 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52041 
52042 /*
52043  * Field : Mask Byte Control - mbc_0
52044  *
52045  * This array of bits are mask control bits for comparison of each of the MAC
52046  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52047  * received DA or SA with the contents of MAC Address48 high and low registers.
52048  * Each bit controls the masking of the bytes. You can filter a group of addresses
52049  * (known as group address filtering) by masking one or more bytes of the address.
52050  *
52051  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52052  *
52053  * Field Enumeration Values:
52054  *
52055  * Enum | Value | Description
52056  * :----------------------------------------------|:------|:------------------------------------
52057  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52058  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52059  *
52060  * Field Access Macros:
52061  *
52062  */
52063 /*
52064  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0
52065  *
52066  * Byte is unmasked (i.e. is compared)
52067  */
52068 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED 0x0
52069 /*
52070  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0
52071  *
52072  * Byte is masked (i.e. not compared)
52073  */
52074 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED 0x1
52075 
52076 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
52077 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_LSB 24
52078 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
52079 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_MSB 24
52080 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
52081 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_WIDTH 1
52082 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */
52083 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET_MSK 0x01000000
52084 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */
52085 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_CLR_MSK 0xfeffffff
52086 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
52087 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_RESET 0x0
52088 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 field value from a register. */
52089 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
52090 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value suitable for setting the register. */
52091 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
52092 
52093 /*
52094  * Field : Mask Byte Control - mbc_1
52095  *
52096  * This array of bits are mask control bits for comparison of each of the MAC
52097  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52098  * received DA or SA with the contents of MAC Address48 high and low registers.
52099  * Each bit controls the masking of the bytes. You can filter a group of addresses
52100  * (known as group address filtering) by masking one or more bytes of the address.
52101  *
52102  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52103  *
52104  * Field Enumeration Values:
52105  *
52106  * Enum | Value | Description
52107  * :----------------------------------------------|:------|:------------------------------------
52108  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52109  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52110  *
52111  * Field Access Macros:
52112  *
52113  */
52114 /*
52115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1
52116  *
52117  * Byte is unmasked (i.e. is compared)
52118  */
52119 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED 0x0
52120 /*
52121  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1
52122  *
52123  * Byte is masked (i.e. not compared)
52124  */
52125 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED 0x1
52126 
52127 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
52128 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_LSB 25
52129 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
52130 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_MSB 25
52131 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
52132 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_WIDTH 1
52133 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */
52134 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET_MSK 0x02000000
52135 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */
52136 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_CLR_MSK 0xfdffffff
52137 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
52138 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_RESET 0x0
52139 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 field value from a register. */
52140 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
52141 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value suitable for setting the register. */
52142 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
52143 
52144 /*
52145  * Field : Mask Byte Control - mbc_2
52146  *
52147  * This array of bits are mask control bits for comparison of each of the MAC
52148  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52149  * received DA or SA with the contents of MAC Address48 high and low registers.
52150  * Each bit controls the masking of the bytes. You can filter a group of addresses
52151  * (known as group address filtering) by masking one or more bytes of the address.
52152  *
52153  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52154  *
52155  * Field Enumeration Values:
52156  *
52157  * Enum | Value | Description
52158  * :----------------------------------------------|:------|:------------------------------------
52159  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52160  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52161  *
52162  * Field Access Macros:
52163  *
52164  */
52165 /*
52166  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2
52167  *
52168  * Byte is unmasked (i.e. is compared)
52169  */
52170 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED 0x0
52171 /*
52172  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2
52173  *
52174  * Byte is masked (i.e. not compared)
52175  */
52176 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED 0x1
52177 
52178 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
52179 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_LSB 26
52180 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
52181 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_MSB 26
52182 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
52183 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_WIDTH 1
52184 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */
52185 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET_MSK 0x04000000
52186 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */
52187 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_CLR_MSK 0xfbffffff
52188 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
52189 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_RESET 0x0
52190 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 field value from a register. */
52191 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
52192 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value suitable for setting the register. */
52193 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
52194 
52195 /*
52196  * Field : Mask Byte Control - mbc_3
52197  *
52198  * This array of bits are mask control bits for comparison of each of the MAC
52199  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52200  * received DA or SA with the contents of MAC Address48 high and low registers.
52201  * Each bit controls the masking of the bytes. You can filter a group of addresses
52202  * (known as group address filtering) by masking one or more bytes of the address.
52203  *
52204  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52205  *
52206  * Field Enumeration Values:
52207  *
52208  * Enum | Value | Description
52209  * :----------------------------------------------|:------|:------------------------------------
52210  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52211  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52212  *
52213  * Field Access Macros:
52214  *
52215  */
52216 /*
52217  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3
52218  *
52219  * Byte is unmasked (i.e. is compared)
52220  */
52221 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED 0x0
52222 /*
52223  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3
52224  *
52225  * Byte is masked (i.e. not compared)
52226  */
52227 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED 0x1
52228 
52229 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
52230 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_LSB 27
52231 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
52232 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_MSB 27
52233 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
52234 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_WIDTH 1
52235 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */
52236 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET_MSK 0x08000000
52237 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */
52238 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_CLR_MSK 0xf7ffffff
52239 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
52240 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_RESET 0x0
52241 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 field value from a register. */
52242 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
52243 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value suitable for setting the register. */
52244 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
52245 
52246 /*
52247  * Field : Mask Byte Control - mbc_4
52248  *
52249  * This array of bits are mask control bits for comparison of each of the MAC
52250  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52251  * received DA or SA with the contents of MAC Address48 high and low registers.
52252  * Each bit controls the masking of the bytes. You can filter a group of addresses
52253  * (known as group address filtering) by masking one or more bytes of the address.
52254  *
52255  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52256  *
52257  * Field Enumeration Values:
52258  *
52259  * Enum | Value | Description
52260  * :----------------------------------------------|:------|:------------------------------------
52261  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52262  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52263  *
52264  * Field Access Macros:
52265  *
52266  */
52267 /*
52268  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4
52269  *
52270  * Byte is unmasked (i.e. is compared)
52271  */
52272 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED 0x0
52273 /*
52274  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4
52275  *
52276  * Byte is masked (i.e. not compared)
52277  */
52278 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED 0x1
52279 
52280 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
52281 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_LSB 28
52282 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
52283 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_MSB 28
52284 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
52285 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_WIDTH 1
52286 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */
52287 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET_MSK 0x10000000
52288 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */
52289 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_CLR_MSK 0xefffffff
52290 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
52291 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_RESET 0x0
52292 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 field value from a register. */
52293 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
52294 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value suitable for setting the register. */
52295 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
52296 
52297 /*
52298  * Field : Mask Byte Control - mbc_5
52299  *
52300  * This array of bits are mask control bits for comparison of each of the MAC
52301  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52302  * received DA or SA with the contents of MAC Address48 high and low registers.
52303  * Each bit controls the masking of the bytes. You can filter a group of addresses
52304  * (known as group address filtering) by masking one or more bytes of the address.
52305  *
52306  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52307  *
52308  * Field Enumeration Values:
52309  *
52310  * Enum | Value | Description
52311  * :----------------------------------------------|:------|:------------------------------------
52312  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52313  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52314  *
52315  * Field Access Macros:
52316  *
52317  */
52318 /*
52319  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5
52320  *
52321  * Byte is unmasked (i.e. is compared)
52322  */
52323 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED 0x0
52324 /*
52325  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5
52326  *
52327  * Byte is masked (i.e. not compared)
52328  */
52329 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED 0x1
52330 
52331 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
52332 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_LSB 29
52333 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
52334 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_MSB 29
52335 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
52336 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_WIDTH 1
52337 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */
52338 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET_MSK 0x20000000
52339 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */
52340 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_CLR_MSK 0xdfffffff
52341 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
52342 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_RESET 0x0
52343 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 field value from a register. */
52344 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
52345 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value suitable for setting the register. */
52346 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
52347 
52348 /*
52349  * Field : Source Address - sa
52350  *
52351  * When this bit is enabled, the MAC Address48[47:0] is used to compare with the SA
52352  * fields of the received frame. When this bit is disabled, the MAC Address48[47:0]
52353  * is used to compare with the DA fields of the received frame.
52354  *
52355  * Field Enumeration Values:
52356  *
52357  * Enum | Value | Description
52358  * :----------------------------------------|:------|:-----------------------------
52359  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
52360  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END | 0x1 | MAC address compare enabled
52361  *
52362  * Field Access Macros:
52363  *
52364  */
52365 /*
52366  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA
52367  *
52368  * MAC address compare disabled
52369  */
52370 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD 0x0
52371 /*
52372  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA
52373  *
52374  * MAC address compare enabled
52375  */
52376 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END 0x1
52377 
52378 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
52379 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_LSB 30
52380 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
52381 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_MSB 30
52382 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
52383 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_WIDTH 1
52384 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */
52385 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET_MSK 0x40000000
52386 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */
52387 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_CLR_MSK 0xbfffffff
52388 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
52389 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_RESET 0x0
52390 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA field value from a register. */
52391 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
52392 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value suitable for setting the register. */
52393 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
52394 
52395 /*
52396  * Field : Address Enable - ae
52397  *
52398  * When this bit is enabled, the address filter block uses the 49th MAC address for
52399  * perfect filtering. When this bit is disabled, the address filter block ignores
52400  * the address for filtering.
52401  *
52402  * Field Enumeration Values:
52403  *
52404  * Enum | Value | Description
52405  * :----------------------------------------|:------|:--------------------------------------
52406  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
52407  * ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
52408  *
52409  * Field Access Macros:
52410  *
52411  */
52412 /*
52413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
52414  *
52415  * Second MAC address filtering disabled
52416  */
52417 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD 0x0
52418 /*
52419  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
52420  *
52421  * Second MAC address filtering enabled
52422  */
52423 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END 0x1
52424 
52425 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
52426 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_LSB 31
52427 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
52428 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_MSB 31
52429 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
52430 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_WIDTH 1
52431 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
52432 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET_MSK 0x80000000
52433 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
52434 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_CLR_MSK 0x7fffffff
52435 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
52436 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_RESET 0x0
52437 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE field value from a register. */
52438 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52439 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value suitable for setting the register. */
52440 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52441 
52442 #ifndef __ASSEMBLY__
52443 /*
52444  * WARNING: The C register and register group struct declarations are provided for
52445  * convenience and illustrative purposes. They should, however, be used with
52446  * caution as the C language standard provides no guarantees about the alignment or
52447  * atomicity of device memory accesses. The recommended practice for writing
52448  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52449  * alt_write_word() functions.
52450  *
52451  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH.
52452  */
52453 struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s
52454 {
52455  uint32_t addrhi : 16; /* MAC Address48 [47:32] */
52456  uint32_t : 8; /* *UNDEFINED* */
52457  uint32_t mbc_0 : 1; /* Mask Byte Control */
52458  uint32_t mbc_1 : 1; /* Mask Byte Control */
52459  uint32_t mbc_2 : 1; /* Mask Byte Control */
52460  uint32_t mbc_3 : 1; /* Mask Byte Control */
52461  uint32_t mbc_4 : 1; /* Mask Byte Control */
52462  uint32_t mbc_5 : 1; /* Mask Byte Control */
52463  uint32_t sa : 1; /* Source Address */
52464  uint32_t ae : 1; /* Address Enable */
52465 };
52466 
52467 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH. */
52468 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t;
52469 #endif /* __ASSEMBLY__ */
52470 
52471 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register from the beginning of the component. */
52472 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST 0x900
52473 /* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register. */
52474 #define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST))
52475 
52476 /*
52477  * Register : Register 577 (MAC Address48 Low Register) - MAC_Address48_Low
52478  *
52479  * The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC
52480  * address of the station.
52481  *
52482  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
52483  * format.
52484  *
52485  * Register Layout
52486  *
52487  * Bits | Access | Reset | Description
52488  * :-------|:-------|:-----------|:---------------------
52489  * [31:0] | RW | 0xffffffff | MAC Address48 [31:0]
52490  *
52491  */
52492 /*
52493  * Field : MAC Address48 [31:0] - addrlo
52494  *
52495  * This field contains the lower 32 bits of the 49th 6-byte MAC address. The
52496  * content of this field is undefined until loaded by software after the
52497  * initialization process.
52498  *
52499  * Field Access Macros:
52500  *
52501  */
52502 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
52503 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_LSB 0
52504 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
52505 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_MSB 31
52506 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
52507 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_WIDTH 32
52508 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
52509 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET_MSK 0xffffffff
52510 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
52511 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_CLR_MSK 0x00000000
52512 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
52513 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_RESET 0xffffffff
52514 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO field value from a register. */
52515 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
52516 /* Produces a ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value suitable for setting the register. */
52517 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
52518 
52519 #ifndef __ASSEMBLY__
52520 /*
52521  * WARNING: The C register and register group struct declarations are provided for
52522  * convenience and illustrative purposes. They should, however, be used with
52523  * caution as the C language standard provides no guarantees about the alignment or
52524  * atomicity of device memory accesses. The recommended practice for writing
52525  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
52526  * alt_write_word() functions.
52527  *
52528  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW.
52529  */
52530 struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s
52531 {
52532  uint32_t addrlo : 32; /* MAC Address48 [31:0] */
52533 };
52534 
52535 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW. */
52536 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s ALT_EMAC_GMAC_MAC_ADDR48_LOW_t;
52537 #endif /* __ASSEMBLY__ */
52538 
52539 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register from the beginning of the component. */
52540 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST 0x904
52541 /* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register. */
52542 #define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST))
52543 
52544 /*
52545  * Register : Register 578 (MAC Address49 High Register) - MAC_Address49_High
52546  *
52547  * The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC
52548  * address of the station. Because the MAC address registers are configured to be
52549  * double-synchronized to the (G)MII clock domains, the synchronization is
52550  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
52551  * endian mode) of the MAC Address49 Low Register are written. For proper
52552  * synchronization updates, the consecutive writes to this Address Low Register
52553  * should be performed after at least four clock cycles in the destination clock
52554  * domain.
52555  *
52556  * Note that all MAC Address High registers (except MAC Address0 High) have the
52557  * same format.
52558  *
52559  * Register Layout
52560  *
52561  * Bits | Access | Reset | Description
52562  * :--------|:-------|:-------|:----------------------
52563  * [15:0] | RW | 0xffff | MAC Address49 [47:32]
52564  * [23:16] | ??? | 0x0 | *UNDEFINED*
52565  * [24] | RW | 0x0 | Mask Byte Control
52566  * [25] | RW | 0x0 | Mask Byte Control
52567  * [26] | RW | 0x0 | Mask Byte Control
52568  * [27] | RW | 0x0 | Mask Byte Control
52569  * [28] | RW | 0x0 | Mask Byte Control
52570  * [29] | RW | 0x0 | Mask Byte Control
52571  * [30] | RW | 0x0 | Source Address
52572  * [31] | RW | 0x0 | Address Enable
52573  *
52574  */
52575 /*
52576  * Field : MAC Address49 [47:32] - addrhi
52577  *
52578  * This field contains the upper 16 bits (47:32) of the 50th 6-byte MAC address.
52579  *
52580  * Field Access Macros:
52581  *
52582  */
52583 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
52584 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_LSB 0
52585 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
52586 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_MSB 15
52587 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
52588 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_WIDTH 16
52589 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
52590 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET_MSK 0x0000ffff
52591 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
52592 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_CLR_MSK 0xffff0000
52593 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
52594 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_RESET 0xffff
52595 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI field value from a register. */
52596 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
52597 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value suitable for setting the register. */
52598 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
52599 
52600 /*
52601  * Field : Mask Byte Control - mbc_0
52602  *
52603  * This array of bits are mask control bits for comparison of each of the MAC
52604  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52605  * received DA or SA with the contents of MAC Address49 high and low registers.
52606  * Each bit controls the masking of the bytes. You can filter a group of addresses
52607  * (known as group address filtering) by masking one or more bytes of the address.
52608  *
52609  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52610  *
52611  * Field Enumeration Values:
52612  *
52613  * Enum | Value | Description
52614  * :----------------------------------------------|:------|:------------------------------------
52615  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52616  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52617  *
52618  * Field Access Macros:
52619  *
52620  */
52621 /*
52622  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0
52623  *
52624  * Byte is unmasked (i.e. is compared)
52625  */
52626 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED 0x0
52627 /*
52628  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0
52629  *
52630  * Byte is masked (i.e. not compared)
52631  */
52632 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED 0x1
52633 
52634 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
52635 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_LSB 24
52636 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
52637 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_MSB 24
52638 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
52639 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_WIDTH 1
52640 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */
52641 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET_MSK 0x01000000
52642 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */
52643 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_CLR_MSK 0xfeffffff
52644 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
52645 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_RESET 0x0
52646 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 field value from a register. */
52647 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
52648 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value suitable for setting the register. */
52649 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
52650 
52651 /*
52652  * Field : Mask Byte Control - mbc_1
52653  *
52654  * This array of bits are mask control bits for comparison of each of the MAC
52655  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52656  * received DA or SA with the contents of MAC Address49 high and low registers.
52657  * Each bit controls the masking of the bytes. You can filter a group of addresses
52658  * (known as group address filtering) by masking one or more bytes of the address.
52659  *
52660  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52661  *
52662  * Field Enumeration Values:
52663  *
52664  * Enum | Value | Description
52665  * :----------------------------------------------|:------|:------------------------------------
52666  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52667  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52668  *
52669  * Field Access Macros:
52670  *
52671  */
52672 /*
52673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1
52674  *
52675  * Byte is unmasked (i.e. is compared)
52676  */
52677 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED 0x0
52678 /*
52679  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1
52680  *
52681  * Byte is masked (i.e. not compared)
52682  */
52683 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED 0x1
52684 
52685 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
52686 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_LSB 25
52687 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
52688 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_MSB 25
52689 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
52690 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_WIDTH 1
52691 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */
52692 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET_MSK 0x02000000
52693 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */
52694 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_CLR_MSK 0xfdffffff
52695 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
52696 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_RESET 0x0
52697 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 field value from a register. */
52698 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
52699 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value suitable for setting the register. */
52700 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
52701 
52702 /*
52703  * Field : Mask Byte Control - mbc_2
52704  *
52705  * This array of bits are mask control bits for comparison of each of the MAC
52706  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52707  * received DA or SA with the contents of MAC Address49 high and low registers.
52708  * Each bit controls the masking of the bytes. You can filter a group of addresses
52709  * (known as group address filtering) by masking one or more bytes of the address.
52710  *
52711  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52712  *
52713  * Field Enumeration Values:
52714  *
52715  * Enum | Value | Description
52716  * :----------------------------------------------|:------|:------------------------------------
52717  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52718  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52719  *
52720  * Field Access Macros:
52721  *
52722  */
52723 /*
52724  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2
52725  *
52726  * Byte is unmasked (i.e. is compared)
52727  */
52728 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED 0x0
52729 /*
52730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2
52731  *
52732  * Byte is masked (i.e. not compared)
52733  */
52734 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED 0x1
52735 
52736 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
52737 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_LSB 26
52738 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
52739 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_MSB 26
52740 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
52741 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_WIDTH 1
52742 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */
52743 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET_MSK 0x04000000
52744 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */
52745 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_CLR_MSK 0xfbffffff
52746 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
52747 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_RESET 0x0
52748 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 field value from a register. */
52749 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
52750 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value suitable for setting the register. */
52751 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
52752 
52753 /*
52754  * Field : Mask Byte Control - mbc_3
52755  *
52756  * This array of bits are mask control bits for comparison of each of the MAC
52757  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52758  * received DA or SA with the contents of MAC Address49 high and low registers.
52759  * Each bit controls the masking of the bytes. You can filter a group of addresses
52760  * (known as group address filtering) by masking one or more bytes of the address.
52761  *
52762  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52763  *
52764  * Field Enumeration Values:
52765  *
52766  * Enum | Value | Description
52767  * :----------------------------------------------|:------|:------------------------------------
52768  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52769  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52770  *
52771  * Field Access Macros:
52772  *
52773  */
52774 /*
52775  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3
52776  *
52777  * Byte is unmasked (i.e. is compared)
52778  */
52779 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED 0x0
52780 /*
52781  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3
52782  *
52783  * Byte is masked (i.e. not compared)
52784  */
52785 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED 0x1
52786 
52787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
52788 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_LSB 27
52789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
52790 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_MSB 27
52791 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
52792 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_WIDTH 1
52793 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */
52794 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET_MSK 0x08000000
52795 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */
52796 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_CLR_MSK 0xf7ffffff
52797 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
52798 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_RESET 0x0
52799 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 field value from a register. */
52800 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
52801 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value suitable for setting the register. */
52802 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
52803 
52804 /*
52805  * Field : Mask Byte Control - mbc_4
52806  *
52807  * This array of bits are mask control bits for comparison of each of the MAC
52808  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52809  * received DA or SA with the contents of MAC Address49 high and low registers.
52810  * Each bit controls the masking of the bytes. You can filter a group of addresses
52811  * (known as group address filtering) by masking one or more bytes of the address.
52812  *
52813  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52814  *
52815  * Field Enumeration Values:
52816  *
52817  * Enum | Value | Description
52818  * :----------------------------------------------|:------|:------------------------------------
52819  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52820  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52821  *
52822  * Field Access Macros:
52823  *
52824  */
52825 /*
52826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4
52827  *
52828  * Byte is unmasked (i.e. is compared)
52829  */
52830 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED 0x0
52831 /*
52832  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4
52833  *
52834  * Byte is masked (i.e. not compared)
52835  */
52836 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED 0x1
52837 
52838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
52839 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_LSB 28
52840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
52841 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_MSB 28
52842 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
52843 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_WIDTH 1
52844 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */
52845 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET_MSK 0x10000000
52846 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */
52847 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_CLR_MSK 0xefffffff
52848 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
52849 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_RESET 0x0
52850 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 field value from a register. */
52851 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
52852 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value suitable for setting the register. */
52853 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
52854 
52855 /*
52856  * Field : Mask Byte Control - mbc_5
52857  *
52858  * This array of bits are mask control bits for comparison of each of the MAC
52859  * Address bytes. When masked, the MAC does not compare the corresponding byte of
52860  * received DA or SA with the contents of MAC Address49 high and low registers.
52861  * Each bit controls the masking of the bytes. You can filter a group of addresses
52862  * (known as group address filtering) by masking one or more bytes of the address.
52863  *
52864  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
52865  *
52866  * Field Enumeration Values:
52867  *
52868  * Enum | Value | Description
52869  * :----------------------------------------------|:------|:------------------------------------
52870  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
52871  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
52872  *
52873  * Field Access Macros:
52874  *
52875  */
52876 /*
52877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5
52878  *
52879  * Byte is unmasked (i.e. is compared)
52880  */
52881 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED 0x0
52882 /*
52883  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5
52884  *
52885  * Byte is masked (i.e. not compared)
52886  */
52887 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED 0x1
52888 
52889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
52890 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_LSB 29
52891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
52892 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_MSB 29
52893 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
52894 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_WIDTH 1
52895 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */
52896 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET_MSK 0x20000000
52897 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */
52898 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_CLR_MSK 0xdfffffff
52899 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
52900 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_RESET 0x0
52901 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 field value from a register. */
52902 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
52903 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value suitable for setting the register. */
52904 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
52905 
52906 /*
52907  * Field : Source Address - sa
52908  *
52909  * When this bit is enabled, the MAC Address49[47:0] is used to compare with the SA
52910  * fields of the received frame. When this bit is disabled, the MAC Address49[47:0]
52911  * is used to compare with the DA fields of the received frame.
52912  *
52913  * Field Enumeration Values:
52914  *
52915  * Enum | Value | Description
52916  * :----------------------------------------|:------|:-----------------------------
52917  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
52918  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END | 0x1 | MAC address compare enabled
52919  *
52920  * Field Access Macros:
52921  *
52922  */
52923 /*
52924  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA
52925  *
52926  * MAC address compare disabled
52927  */
52928 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD 0x0
52929 /*
52930  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA
52931  *
52932  * MAC address compare enabled
52933  */
52934 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END 0x1
52935 
52936 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
52937 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_LSB 30
52938 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
52939 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_MSB 30
52940 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
52941 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_WIDTH 1
52942 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */
52943 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET_MSK 0x40000000
52944 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */
52945 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_CLR_MSK 0xbfffffff
52946 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
52947 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_RESET 0x0
52948 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA field value from a register. */
52949 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
52950 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value suitable for setting the register. */
52951 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
52952 
52953 /*
52954  * Field : Address Enable - ae
52955  *
52956  * When this bit is enabled, the address filter block uses the 50th MAC address for
52957  * perfect filtering. When this bit is disabled, the address filter block ignores
52958  * the address for filtering.
52959  *
52960  * Field Enumeration Values:
52961  *
52962  * Enum | Value | Description
52963  * :----------------------------------------|:------|:--------------------------------------
52964  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
52965  * ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
52966  *
52967  * Field Access Macros:
52968  *
52969  */
52970 /*
52971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
52972  *
52973  * Second MAC address filtering disabled
52974  */
52975 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD 0x0
52976 /*
52977  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
52978  *
52979  * Second MAC address filtering enabled
52980  */
52981 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END 0x1
52982 
52983 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
52984 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_LSB 31
52985 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
52986 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_MSB 31
52987 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
52988 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_WIDTH 1
52989 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
52990 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET_MSK 0x80000000
52991 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
52992 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_CLR_MSK 0x7fffffff
52993 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
52994 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_RESET 0x0
52995 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE field value from a register. */
52996 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
52997 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value suitable for setting the register. */
52998 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
52999 
53000 #ifndef __ASSEMBLY__
53001 /*
53002  * WARNING: The C register and register group struct declarations are provided for
53003  * convenience and illustrative purposes. They should, however, be used with
53004  * caution as the C language standard provides no guarantees about the alignment or
53005  * atomicity of device memory accesses. The recommended practice for writing
53006  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53007  * alt_write_word() functions.
53008  *
53009  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH.
53010  */
53011 struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s
53012 {
53013  uint32_t addrhi : 16; /* MAC Address49 [47:32] */
53014  uint32_t : 8; /* *UNDEFINED* */
53015  uint32_t mbc_0 : 1; /* Mask Byte Control */
53016  uint32_t mbc_1 : 1; /* Mask Byte Control */
53017  uint32_t mbc_2 : 1; /* Mask Byte Control */
53018  uint32_t mbc_3 : 1; /* Mask Byte Control */
53019  uint32_t mbc_4 : 1; /* Mask Byte Control */
53020  uint32_t mbc_5 : 1; /* Mask Byte Control */
53021  uint32_t sa : 1; /* Source Address */
53022  uint32_t ae : 1; /* Address Enable */
53023 };
53024 
53025 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH. */
53026 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t;
53027 #endif /* __ASSEMBLY__ */
53028 
53029 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register from the beginning of the component. */
53030 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST 0x908
53031 /* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register. */
53032 #define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST))
53033 
53034 /*
53035  * Register : Register 579 (MAC Address49 Low Register) - MAC_Address49_Low
53036  *
53037  * The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC
53038  * address of the station.
53039  *
53040  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
53041  * format.
53042  *
53043  * Register Layout
53044  *
53045  * Bits | Access | Reset | Description
53046  * :-------|:-------|:-----------|:---------------------
53047  * [31:0] | RW | 0xffffffff | MAC Address49 [31:0]
53048  *
53049  */
53050 /*
53051  * Field : MAC Address49 [31:0] - addrlo
53052  *
53053  * This field contains the lower 32 bits of the 50th 6-byte MAC address. The
53054  * content of this field is undefined until loaded by software after the
53055  * initialization process.
53056  *
53057  * Field Access Macros:
53058  *
53059  */
53060 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
53061 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_LSB 0
53062 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
53063 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_MSB 31
53064 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
53065 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_WIDTH 32
53066 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
53067 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET_MSK 0xffffffff
53068 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
53069 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_CLR_MSK 0x00000000
53070 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
53071 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_RESET 0xffffffff
53072 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO field value from a register. */
53073 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53074 /* Produces a ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value suitable for setting the register. */
53075 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53076 
53077 #ifndef __ASSEMBLY__
53078 /*
53079  * WARNING: The C register and register group struct declarations are provided for
53080  * convenience and illustrative purposes. They should, however, be used with
53081  * caution as the C language standard provides no guarantees about the alignment or
53082  * atomicity of device memory accesses. The recommended practice for writing
53083  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53084  * alt_write_word() functions.
53085  *
53086  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW.
53087  */
53088 struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s
53089 {
53090  uint32_t addrlo : 32; /* MAC Address49 [31:0] */
53091 };
53092 
53093 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW. */
53094 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s ALT_EMAC_GMAC_MAC_ADDR49_LOW_t;
53095 #endif /* __ASSEMBLY__ */
53096 
53097 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register from the beginning of the component. */
53098 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST 0x90c
53099 /* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register. */
53100 #define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST))
53101 
53102 /*
53103  * Register : Register 580 (MAC Address50 High Register) - MAC_Address50_High
53104  *
53105  * The MAC Address50 High register holds the upper 16 bits of the 51th 6-byte MAC
53106  * address of the station. Because the MAC address registers are configured to be
53107  * double-synchronized to the (G)MII clock domains, the synchronization is
53108  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
53109  * endian mode) of the MAC Address50 Low Register are written. For proper
53110  * synchronization updates, the consecutive writes to this Address Low Register
53111  * should be performed after at least four clock cycles in the destination clock
53112  * domain.
53113  *
53114  * Note that all MAC Address High registers (except MAC Address0 High) have the
53115  * same format.
53116  *
53117  * Register Layout
53118  *
53119  * Bits | Access | Reset | Description
53120  * :--------|:-------|:-------|:----------------------
53121  * [15:0] | RW | 0xffff | MAC Address50 [47:32]
53122  * [23:16] | ??? | 0x0 | *UNDEFINED*
53123  * [24] | RW | 0x0 | Mask Byte Control
53124  * [25] | RW | 0x0 | Mask Byte Control
53125  * [26] | RW | 0x0 | Mask Byte Control
53126  * [27] | RW | 0x0 | Mask Byte Control
53127  * [28] | RW | 0x0 | Mask Byte Control
53128  * [29] | RW | 0x0 | Mask Byte Control
53129  * [30] | RW | 0x0 | Source Address
53130  * [31] | RW | 0x0 | Address Enable
53131  *
53132  */
53133 /*
53134  * Field : MAC Address50 [47:32] - addrhi
53135  *
53136  * This field contains the upper 16 bits (47:32) of the 51th 6-byte MAC address.
53137  *
53138  * Field Access Macros:
53139  *
53140  */
53141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
53142 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_LSB 0
53143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
53144 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_MSB 15
53145 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
53146 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_WIDTH 16
53147 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
53148 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET_MSK 0x0000ffff
53149 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
53150 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_CLR_MSK 0xffff0000
53151 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
53152 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_RESET 0xffff
53153 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI field value from a register. */
53154 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53155 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value suitable for setting the register. */
53156 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53157 
53158 /*
53159  * Field : Mask Byte Control - mbc_0
53160  *
53161  * This array of bits are mask control bits for comparison of each of the MAC
53162  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53163  * received DA or SA with the contents of MAC Address50 high and low registers.
53164  * Each bit controls the masking of the bytes. You can filter a group of addresses
53165  * (known as group address filtering) by masking one or more bytes of the address.
53166  *
53167  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53168  *
53169  * Field Enumeration Values:
53170  *
53171  * Enum | Value | Description
53172  * :----------------------------------------------|:------|:------------------------------------
53173  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53174  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53175  *
53176  * Field Access Macros:
53177  *
53178  */
53179 /*
53180  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0
53181  *
53182  * Byte is unmasked (i.e. is compared)
53183  */
53184 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED 0x0
53185 /*
53186  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0
53187  *
53188  * Byte is masked (i.e. not compared)
53189  */
53190 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED 0x1
53191 
53192 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
53193 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_LSB 24
53194 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
53195 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_MSB 24
53196 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
53197 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_WIDTH 1
53198 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */
53199 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET_MSK 0x01000000
53200 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */
53201 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_CLR_MSK 0xfeffffff
53202 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
53203 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_RESET 0x0
53204 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 field value from a register. */
53205 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
53206 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value suitable for setting the register. */
53207 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
53208 
53209 /*
53210  * Field : Mask Byte Control - mbc_1
53211  *
53212  * This array of bits are mask control bits for comparison of each of the MAC
53213  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53214  * received DA or SA with the contents of MAC Address50 high and low registers.
53215  * Each bit controls the masking of the bytes. You can filter a group of addresses
53216  * (known as group address filtering) by masking one or more bytes of the address.
53217  *
53218  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53219  *
53220  * Field Enumeration Values:
53221  *
53222  * Enum | Value | Description
53223  * :----------------------------------------------|:------|:------------------------------------
53224  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53225  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53226  *
53227  * Field Access Macros:
53228  *
53229  */
53230 /*
53231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1
53232  *
53233  * Byte is unmasked (i.e. is compared)
53234  */
53235 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED 0x0
53236 /*
53237  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1
53238  *
53239  * Byte is masked (i.e. not compared)
53240  */
53241 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED 0x1
53242 
53243 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
53244 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_LSB 25
53245 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
53246 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_MSB 25
53247 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
53248 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_WIDTH 1
53249 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */
53250 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET_MSK 0x02000000
53251 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */
53252 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_CLR_MSK 0xfdffffff
53253 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
53254 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_RESET 0x0
53255 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 field value from a register. */
53256 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
53257 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value suitable for setting the register. */
53258 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
53259 
53260 /*
53261  * Field : Mask Byte Control - mbc_2
53262  *
53263  * This array of bits are mask control bits for comparison of each of the MAC
53264  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53265  * received DA or SA with the contents of MAC Address50 high and low registers.
53266  * Each bit controls the masking of the bytes. You can filter a group of addresses
53267  * (known as group address filtering) by masking one or more bytes of the address.
53268  *
53269  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53270  *
53271  * Field Enumeration Values:
53272  *
53273  * Enum | Value | Description
53274  * :----------------------------------------------|:------|:------------------------------------
53275  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53276  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53277  *
53278  * Field Access Macros:
53279  *
53280  */
53281 /*
53282  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2
53283  *
53284  * Byte is unmasked (i.e. is compared)
53285  */
53286 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED 0x0
53287 /*
53288  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2
53289  *
53290  * Byte is masked (i.e. not compared)
53291  */
53292 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED 0x1
53293 
53294 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
53295 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_LSB 26
53296 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
53297 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_MSB 26
53298 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
53299 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_WIDTH 1
53300 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */
53301 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET_MSK 0x04000000
53302 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */
53303 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_CLR_MSK 0xfbffffff
53304 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
53305 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_RESET 0x0
53306 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 field value from a register. */
53307 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
53308 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value suitable for setting the register. */
53309 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
53310 
53311 /*
53312  * Field : Mask Byte Control - mbc_3
53313  *
53314  * This array of bits are mask control bits for comparison of each of the MAC
53315  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53316  * received DA or SA with the contents of MAC Address50 high and low registers.
53317  * Each bit controls the masking of the bytes. You can filter a group of addresses
53318  * (known as group address filtering) by masking one or more bytes of the address.
53319  *
53320  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53321  *
53322  * Field Enumeration Values:
53323  *
53324  * Enum | Value | Description
53325  * :----------------------------------------------|:------|:------------------------------------
53326  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53327  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53328  *
53329  * Field Access Macros:
53330  *
53331  */
53332 /*
53333  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3
53334  *
53335  * Byte is unmasked (i.e. is compared)
53336  */
53337 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED 0x0
53338 /*
53339  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3
53340  *
53341  * Byte is masked (i.e. not compared)
53342  */
53343 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED 0x1
53344 
53345 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
53346 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_LSB 27
53347 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
53348 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_MSB 27
53349 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
53350 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_WIDTH 1
53351 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */
53352 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET_MSK 0x08000000
53353 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */
53354 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_CLR_MSK 0xf7ffffff
53355 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
53356 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_RESET 0x0
53357 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 field value from a register. */
53358 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
53359 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value suitable for setting the register. */
53360 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
53361 
53362 /*
53363  * Field : Mask Byte Control - mbc_4
53364  *
53365  * This array of bits are mask control bits for comparison of each of the MAC
53366  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53367  * received DA or SA with the contents of MAC Address50 high and low registers.
53368  * Each bit controls the masking of the bytes. You can filter a group of addresses
53369  * (known as group address filtering) by masking one or more bytes of the address.
53370  *
53371  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53372  *
53373  * Field Enumeration Values:
53374  *
53375  * Enum | Value | Description
53376  * :----------------------------------------------|:------|:------------------------------------
53377  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53378  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53379  *
53380  * Field Access Macros:
53381  *
53382  */
53383 /*
53384  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4
53385  *
53386  * Byte is unmasked (i.e. is compared)
53387  */
53388 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED 0x0
53389 /*
53390  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4
53391  *
53392  * Byte is masked (i.e. not compared)
53393  */
53394 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED 0x1
53395 
53396 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
53397 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_LSB 28
53398 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
53399 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_MSB 28
53400 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
53401 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_WIDTH 1
53402 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */
53403 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET_MSK 0x10000000
53404 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */
53405 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_CLR_MSK 0xefffffff
53406 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
53407 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_RESET 0x0
53408 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 field value from a register. */
53409 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
53410 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value suitable for setting the register. */
53411 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
53412 
53413 /*
53414  * Field : Mask Byte Control - mbc_5
53415  *
53416  * This array of bits are mask control bits for comparison of each of the MAC
53417  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53418  * received DA or SA with the contents of MAC Address50 high and low registers.
53419  * Each bit controls the masking of the bytes. You can filter a group of addresses
53420  * (known as group address filtering) by masking one or more bytes of the address.
53421  *
53422  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53423  *
53424  * Field Enumeration Values:
53425  *
53426  * Enum | Value | Description
53427  * :----------------------------------------------|:------|:------------------------------------
53428  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53429  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53430  *
53431  * Field Access Macros:
53432  *
53433  */
53434 /*
53435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5
53436  *
53437  * Byte is unmasked (i.e. is compared)
53438  */
53439 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED 0x0
53440 /*
53441  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5
53442  *
53443  * Byte is masked (i.e. not compared)
53444  */
53445 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED 0x1
53446 
53447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
53448 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_LSB 29
53449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
53450 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_MSB 29
53451 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
53452 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_WIDTH 1
53453 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */
53454 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET_MSK 0x20000000
53455 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */
53456 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_CLR_MSK 0xdfffffff
53457 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
53458 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_RESET 0x0
53459 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 field value from a register. */
53460 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
53461 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value suitable for setting the register. */
53462 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
53463 
53464 /*
53465  * Field : Source Address - sa
53466  *
53467  * When this bit is enabled, the MAC Address50[47:0] is used to compare with the SA
53468  * fields of the received frame. When this bit is disabled, the MAC Address50[47:0]
53469  * is used to compare with the DA fields of the received frame.
53470  *
53471  * Field Enumeration Values:
53472  *
53473  * Enum | Value | Description
53474  * :----------------------------------------|:------|:-----------------------------
53475  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
53476  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END | 0x1 | MAC address compare enabled
53477  *
53478  * Field Access Macros:
53479  *
53480  */
53481 /*
53482  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA
53483  *
53484  * MAC address compare disabled
53485  */
53486 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD 0x0
53487 /*
53488  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA
53489  *
53490  * MAC address compare enabled
53491  */
53492 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END 0x1
53493 
53494 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
53495 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_LSB 30
53496 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
53497 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_MSB 30
53498 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
53499 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_WIDTH 1
53500 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */
53501 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET_MSK 0x40000000
53502 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */
53503 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_CLR_MSK 0xbfffffff
53504 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
53505 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_RESET 0x0
53506 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA field value from a register. */
53507 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
53508 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value suitable for setting the register. */
53509 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
53510 
53511 /*
53512  * Field : Address Enable - ae
53513  *
53514  * When this bit is enabled, the address filter block uses the 51th MAC address for
53515  * perfect filtering. When this bit is disabled, the address filter block ignores
53516  * the address for filtering.
53517  *
53518  * Field Enumeration Values:
53519  *
53520  * Enum | Value | Description
53521  * :----------------------------------------|:------|:--------------------------------------
53522  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
53523  * ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
53524  *
53525  * Field Access Macros:
53526  *
53527  */
53528 /*
53529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
53530  *
53531  * Second MAC address filtering disabled
53532  */
53533 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD 0x0
53534 /*
53535  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
53536  *
53537  * Second MAC address filtering enabled
53538  */
53539 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END 0x1
53540 
53541 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
53542 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_LSB 31
53543 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
53544 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_MSB 31
53545 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
53546 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_WIDTH 1
53547 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
53548 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET_MSK 0x80000000
53549 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
53550 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_CLR_MSK 0x7fffffff
53551 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
53552 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_RESET 0x0
53553 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE field value from a register. */
53554 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
53555 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value suitable for setting the register. */
53556 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
53557 
53558 #ifndef __ASSEMBLY__
53559 /*
53560  * WARNING: The C register and register group struct declarations are provided for
53561  * convenience and illustrative purposes. They should, however, be used with
53562  * caution as the C language standard provides no guarantees about the alignment or
53563  * atomicity of device memory accesses. The recommended practice for writing
53564  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53565  * alt_write_word() functions.
53566  *
53567  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH.
53568  */
53569 struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s
53570 {
53571  uint32_t addrhi : 16; /* MAC Address50 [47:32] */
53572  uint32_t : 8; /* *UNDEFINED* */
53573  uint32_t mbc_0 : 1; /* Mask Byte Control */
53574  uint32_t mbc_1 : 1; /* Mask Byte Control */
53575  uint32_t mbc_2 : 1; /* Mask Byte Control */
53576  uint32_t mbc_3 : 1; /* Mask Byte Control */
53577  uint32_t mbc_4 : 1; /* Mask Byte Control */
53578  uint32_t mbc_5 : 1; /* Mask Byte Control */
53579  uint32_t sa : 1; /* Source Address */
53580  uint32_t ae : 1; /* Address Enable */
53581 };
53582 
53583 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH. */
53584 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t;
53585 #endif /* __ASSEMBLY__ */
53586 
53587 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register from the beginning of the component. */
53588 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST 0x910
53589 /* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register. */
53590 #define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST))
53591 
53592 /*
53593  * Register : Register 581 (MAC Address50 Low Register) - MAC_Address50_Low
53594  *
53595  * The MAC Address50 Low register holds the lower 32 bits of the 51th 6-byte MAC
53596  * address of the station.
53597  *
53598  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
53599  * format.
53600  *
53601  * Register Layout
53602  *
53603  * Bits | Access | Reset | Description
53604  * :-------|:-------|:-----------|:---------------------
53605  * [31:0] | RW | 0xffffffff | MAC Address50 [31:0]
53606  *
53607  */
53608 /*
53609  * Field : MAC Address50 [31:0] - addrlo
53610  *
53611  * This field contains the lower 32 bits of the 51th 6-byte MAC address. The
53612  * content of this field is undefined until loaded by software after the
53613  * initialization process.
53614  *
53615  * Field Access Macros:
53616  *
53617  */
53618 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
53619 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_LSB 0
53620 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
53621 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_MSB 31
53622 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
53623 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_WIDTH 32
53624 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
53625 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET_MSK 0xffffffff
53626 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
53627 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_CLR_MSK 0x00000000
53628 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
53629 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_RESET 0xffffffff
53630 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO field value from a register. */
53631 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
53632 /* Produces a ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value suitable for setting the register. */
53633 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
53634 
53635 #ifndef __ASSEMBLY__
53636 /*
53637  * WARNING: The C register and register group struct declarations are provided for
53638  * convenience and illustrative purposes. They should, however, be used with
53639  * caution as the C language standard provides no guarantees about the alignment or
53640  * atomicity of device memory accesses. The recommended practice for writing
53641  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
53642  * alt_write_word() functions.
53643  *
53644  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW.
53645  */
53646 struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s
53647 {
53648  uint32_t addrlo : 32; /* MAC Address50 [31:0] */
53649 };
53650 
53651 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW. */
53652 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s ALT_EMAC_GMAC_MAC_ADDR50_LOW_t;
53653 #endif /* __ASSEMBLY__ */
53654 
53655 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register from the beginning of the component. */
53656 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST 0x914
53657 /* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register. */
53658 #define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST))
53659 
53660 /*
53661  * Register : Register 582 (MAC Address51 High Register) - MAC_Address51_High
53662  *
53663  * The MAC Address51 High register holds the upper 16 bits of the 52th 6-byte MAC
53664  * address of the station. Because the MAC address registers are configured to be
53665  * double-synchronized to the (G)MII clock domains, the synchronization is
53666  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
53667  * endian mode) of the MAC Address51 Low Register are written. For proper
53668  * synchronization updates, the consecutive writes to this Address Low Register
53669  * should be performed after at least four clock cycles in the destination clock
53670  * domain.
53671  *
53672  * Note that all MAC Address High registers (except MAC Address0 High) have the
53673  * same format.
53674  *
53675  * Register Layout
53676  *
53677  * Bits | Access | Reset | Description
53678  * :--------|:-------|:-------|:----------------------
53679  * [15:0] | RW | 0xffff | MAC Address51 [47:32]
53680  * [23:16] | ??? | 0x0 | *UNDEFINED*
53681  * [24] | RW | 0x0 | Mask Byte Control
53682  * [25] | RW | 0x0 | Mask Byte Control
53683  * [26] | RW | 0x0 | Mask Byte Control
53684  * [27] | RW | 0x0 | Mask Byte Control
53685  * [28] | RW | 0x0 | Mask Byte Control
53686  * [29] | RW | 0x0 | Mask Byte Control
53687  * [30] | RW | 0x0 | Source Address
53688  * [31] | RW | 0x0 | Address Enable
53689  *
53690  */
53691 /*
53692  * Field : MAC Address51 [47:32] - addrhi
53693  *
53694  * This field contains the upper 16 bits (47:32) of the 52th 6-byte MAC address.
53695  *
53696  * Field Access Macros:
53697  *
53698  */
53699 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
53700 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_LSB 0
53701 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
53702 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_MSB 15
53703 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
53704 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_WIDTH 16
53705 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
53706 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET_MSK 0x0000ffff
53707 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
53708 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_CLR_MSK 0xffff0000
53709 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
53710 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_RESET 0xffff
53711 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI field value from a register. */
53712 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
53713 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value suitable for setting the register. */
53714 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
53715 
53716 /*
53717  * Field : Mask Byte Control - mbc_0
53718  *
53719  * This array of bits are mask control bits for comparison of each of the MAC
53720  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53721  * received DA or SA with the contents of MAC Address51 high and low registers.
53722  * Each bit controls the masking of the bytes. You can filter a group of addresses
53723  * (known as group address filtering) by masking one or more bytes of the address.
53724  *
53725  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53726  *
53727  * Field Enumeration Values:
53728  *
53729  * Enum | Value | Description
53730  * :----------------------------------------------|:------|:------------------------------------
53731  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53732  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53733  *
53734  * Field Access Macros:
53735  *
53736  */
53737 /*
53738  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0
53739  *
53740  * Byte is unmasked (i.e. is compared)
53741  */
53742 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED 0x0
53743 /*
53744  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0
53745  *
53746  * Byte is masked (i.e. not compared)
53747  */
53748 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED 0x1
53749 
53750 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
53751 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_LSB 24
53752 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
53753 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_MSB 24
53754 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
53755 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_WIDTH 1
53756 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */
53757 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET_MSK 0x01000000
53758 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */
53759 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_CLR_MSK 0xfeffffff
53760 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
53761 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_RESET 0x0
53762 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 field value from a register. */
53763 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
53764 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value suitable for setting the register. */
53765 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
53766 
53767 /*
53768  * Field : Mask Byte Control - mbc_1
53769  *
53770  * This array of bits are mask control bits for comparison of each of the MAC
53771  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53772  * received DA or SA with the contents of MAC Address51 high and low registers.
53773  * Each bit controls the masking of the bytes. You can filter a group of addresses
53774  * (known as group address filtering) by masking one or more bytes of the address.
53775  *
53776  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53777  *
53778  * Field Enumeration Values:
53779  *
53780  * Enum | Value | Description
53781  * :----------------------------------------------|:------|:------------------------------------
53782  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53783  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53784  *
53785  * Field Access Macros:
53786  *
53787  */
53788 /*
53789  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1
53790  *
53791  * Byte is unmasked (i.e. is compared)
53792  */
53793 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED 0x0
53794 /*
53795  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1
53796  *
53797  * Byte is masked (i.e. not compared)
53798  */
53799 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED 0x1
53800 
53801 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
53802 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_LSB 25
53803 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
53804 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_MSB 25
53805 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
53806 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_WIDTH 1
53807 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */
53808 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET_MSK 0x02000000
53809 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */
53810 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_CLR_MSK 0xfdffffff
53811 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
53812 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_RESET 0x0
53813 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 field value from a register. */
53814 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
53815 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value suitable for setting the register. */
53816 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
53817 
53818 /*
53819  * Field : Mask Byte Control - mbc_2
53820  *
53821  * This array of bits are mask control bits for comparison of each of the MAC
53822  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53823  * received DA or SA with the contents of MAC Address51 high and low registers.
53824  * Each bit controls the masking of the bytes. You can filter a group of addresses
53825  * (known as group address filtering) by masking one or more bytes of the address.
53826  *
53827  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53828  *
53829  * Field Enumeration Values:
53830  *
53831  * Enum | Value | Description
53832  * :----------------------------------------------|:------|:------------------------------------
53833  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53834  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53835  *
53836  * Field Access Macros:
53837  *
53838  */
53839 /*
53840  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2
53841  *
53842  * Byte is unmasked (i.e. is compared)
53843  */
53844 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED 0x0
53845 /*
53846  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2
53847  *
53848  * Byte is masked (i.e. not compared)
53849  */
53850 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED 0x1
53851 
53852 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
53853 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_LSB 26
53854 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
53855 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_MSB 26
53856 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
53857 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_WIDTH 1
53858 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */
53859 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET_MSK 0x04000000
53860 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */
53861 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_CLR_MSK 0xfbffffff
53862 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
53863 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_RESET 0x0
53864 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 field value from a register. */
53865 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
53866 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value suitable for setting the register. */
53867 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
53868 
53869 /*
53870  * Field : Mask Byte Control - mbc_3
53871  *
53872  * This array of bits are mask control bits for comparison of each of the MAC
53873  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53874  * received DA or SA with the contents of MAC Address51 high and low registers.
53875  * Each bit controls the masking of the bytes. You can filter a group of addresses
53876  * (known as group address filtering) by masking one or more bytes of the address.
53877  *
53878  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53879  *
53880  * Field Enumeration Values:
53881  *
53882  * Enum | Value | Description
53883  * :----------------------------------------------|:------|:------------------------------------
53884  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53885  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53886  *
53887  * Field Access Macros:
53888  *
53889  */
53890 /*
53891  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3
53892  *
53893  * Byte is unmasked (i.e. is compared)
53894  */
53895 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED 0x0
53896 /*
53897  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3
53898  *
53899  * Byte is masked (i.e. not compared)
53900  */
53901 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED 0x1
53902 
53903 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
53904 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_LSB 27
53905 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
53906 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_MSB 27
53907 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
53908 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_WIDTH 1
53909 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */
53910 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET_MSK 0x08000000
53911 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */
53912 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_CLR_MSK 0xf7ffffff
53913 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
53914 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_RESET 0x0
53915 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 field value from a register. */
53916 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
53917 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value suitable for setting the register. */
53918 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
53919 
53920 /*
53921  * Field : Mask Byte Control - mbc_4
53922  *
53923  * This array of bits are mask control bits for comparison of each of the MAC
53924  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53925  * received DA or SA with the contents of MAC Address51 high and low registers.
53926  * Each bit controls the masking of the bytes. You can filter a group of addresses
53927  * (known as group address filtering) by masking one or more bytes of the address.
53928  *
53929  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53930  *
53931  * Field Enumeration Values:
53932  *
53933  * Enum | Value | Description
53934  * :----------------------------------------------|:------|:------------------------------------
53935  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53936  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53937  *
53938  * Field Access Macros:
53939  *
53940  */
53941 /*
53942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4
53943  *
53944  * Byte is unmasked (i.e. is compared)
53945  */
53946 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED 0x0
53947 /*
53948  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4
53949  *
53950  * Byte is masked (i.e. not compared)
53951  */
53952 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED 0x1
53953 
53954 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
53955 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_LSB 28
53956 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
53957 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_MSB 28
53958 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
53959 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_WIDTH 1
53960 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */
53961 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET_MSK 0x10000000
53962 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */
53963 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_CLR_MSK 0xefffffff
53964 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
53965 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_RESET 0x0
53966 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 field value from a register. */
53967 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
53968 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value suitable for setting the register. */
53969 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
53970 
53971 /*
53972  * Field : Mask Byte Control - mbc_5
53973  *
53974  * This array of bits are mask control bits for comparison of each of the MAC
53975  * Address bytes. When masked, the MAC does not compare the corresponding byte of
53976  * received DA or SA with the contents of MAC Address51 high and low registers.
53977  * Each bit controls the masking of the bytes. You can filter a group of addresses
53978  * (known as group address filtering) by masking one or more bytes of the address.
53979  *
53980  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
53981  *
53982  * Field Enumeration Values:
53983  *
53984  * Enum | Value | Description
53985  * :----------------------------------------------|:------|:------------------------------------
53986  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
53987  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
53988  *
53989  * Field Access Macros:
53990  *
53991  */
53992 /*
53993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5
53994  *
53995  * Byte is unmasked (i.e. is compared)
53996  */
53997 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED 0x0
53998 /*
53999  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5
54000  *
54001  * Byte is masked (i.e. not compared)
54002  */
54003 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED 0x1
54004 
54005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
54006 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_LSB 29
54007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
54008 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_MSB 29
54009 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
54010 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_WIDTH 1
54011 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */
54012 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET_MSK 0x20000000
54013 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */
54014 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_CLR_MSK 0xdfffffff
54015 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
54016 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_RESET 0x0
54017 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 field value from a register. */
54018 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
54019 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value suitable for setting the register. */
54020 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
54021 
54022 /*
54023  * Field : Source Address - sa
54024  *
54025  * When this bit is enabled, the MAC Address51[47:0] is used to compare with the SA
54026  * fields of the received frame. When this bit is disabled, the MAC Address51[47:0]
54027  * is used to compare with the DA fields of the received frame.
54028  *
54029  * Field Enumeration Values:
54030  *
54031  * Enum | Value | Description
54032  * :----------------------------------------|:------|:-----------------------------
54033  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
54034  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END | 0x1 | MAC address compare enabled
54035  *
54036  * Field Access Macros:
54037  *
54038  */
54039 /*
54040  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA
54041  *
54042  * MAC address compare disabled
54043  */
54044 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD 0x0
54045 /*
54046  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA
54047  *
54048  * MAC address compare enabled
54049  */
54050 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END 0x1
54051 
54052 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
54053 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_LSB 30
54054 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
54055 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_MSB 30
54056 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
54057 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_WIDTH 1
54058 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */
54059 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET_MSK 0x40000000
54060 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */
54061 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_CLR_MSK 0xbfffffff
54062 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
54063 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_RESET 0x0
54064 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA field value from a register. */
54065 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
54066 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value suitable for setting the register. */
54067 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
54068 
54069 /*
54070  * Field : Address Enable - ae
54071  *
54072  * When this bit is enabled, the address filter block uses the 52th MAC address for
54073  * perfect filtering. When this bit is disabled, the address filter block ignores
54074  * the address for filtering.
54075  *
54076  * Field Enumeration Values:
54077  *
54078  * Enum | Value | Description
54079  * :----------------------------------------|:------|:--------------------------------------
54080  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
54081  * ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
54082  *
54083  * Field Access Macros:
54084  *
54085  */
54086 /*
54087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
54088  *
54089  * Second MAC address filtering disabled
54090  */
54091 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD 0x0
54092 /*
54093  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
54094  *
54095  * Second MAC address filtering enabled
54096  */
54097 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END 0x1
54098 
54099 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
54100 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_LSB 31
54101 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
54102 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_MSB 31
54103 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
54104 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_WIDTH 1
54105 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
54106 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET_MSK 0x80000000
54107 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
54108 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_CLR_MSK 0x7fffffff
54109 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
54110 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_RESET 0x0
54111 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE field value from a register. */
54112 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54113 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value suitable for setting the register. */
54114 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54115 
54116 #ifndef __ASSEMBLY__
54117 /*
54118  * WARNING: The C register and register group struct declarations are provided for
54119  * convenience and illustrative purposes. They should, however, be used with
54120  * caution as the C language standard provides no guarantees about the alignment or
54121  * atomicity of device memory accesses. The recommended practice for writing
54122  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54123  * alt_write_word() functions.
54124  *
54125  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH.
54126  */
54127 struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s
54128 {
54129  uint32_t addrhi : 16; /* MAC Address51 [47:32] */
54130  uint32_t : 8; /* *UNDEFINED* */
54131  uint32_t mbc_0 : 1; /* Mask Byte Control */
54132  uint32_t mbc_1 : 1; /* Mask Byte Control */
54133  uint32_t mbc_2 : 1; /* Mask Byte Control */
54134  uint32_t mbc_3 : 1; /* Mask Byte Control */
54135  uint32_t mbc_4 : 1; /* Mask Byte Control */
54136  uint32_t mbc_5 : 1; /* Mask Byte Control */
54137  uint32_t sa : 1; /* Source Address */
54138  uint32_t ae : 1; /* Address Enable */
54139 };
54140 
54141 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH. */
54142 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t;
54143 #endif /* __ASSEMBLY__ */
54144 
54145 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register from the beginning of the component. */
54146 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST 0x918
54147 /* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register. */
54148 #define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST))
54149 
54150 /*
54151  * Register : Register 583 (MAC Address51 Low Register) - MAC_Address51_Low
54152  *
54153  * The MAC Address51 Low register holds the lower 32 bits of the 52th 6-byte MAC
54154  * address of the station.
54155  *
54156  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
54157  * format.
54158  *
54159  * Register Layout
54160  *
54161  * Bits | Access | Reset | Description
54162  * :-------|:-------|:-----------|:---------------------
54163  * [31:0] | RW | 0xffffffff | MAC Address51 [31:0]
54164  *
54165  */
54166 /*
54167  * Field : MAC Address51 [31:0] - addrlo
54168  *
54169  * This field contains the lower 32 bits of the 52th 6-byte MAC address. The
54170  * content of this field is undefined until loaded by software after the
54171  * initialization process.
54172  *
54173  * Field Access Macros:
54174  *
54175  */
54176 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
54177 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_LSB 0
54178 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
54179 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_MSB 31
54180 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
54181 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_WIDTH 32
54182 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
54183 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET_MSK 0xffffffff
54184 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
54185 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_CLR_MSK 0x00000000
54186 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
54187 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_RESET 0xffffffff
54188 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO field value from a register. */
54189 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54190 /* Produces a ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value suitable for setting the register. */
54191 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54192 
54193 #ifndef __ASSEMBLY__
54194 /*
54195  * WARNING: The C register and register group struct declarations are provided for
54196  * convenience and illustrative purposes. They should, however, be used with
54197  * caution as the C language standard provides no guarantees about the alignment or
54198  * atomicity of device memory accesses. The recommended practice for writing
54199  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54200  * alt_write_word() functions.
54201  *
54202  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW.
54203  */
54204 struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s
54205 {
54206  uint32_t addrlo : 32; /* MAC Address51 [31:0] */
54207 };
54208 
54209 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW. */
54210 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s ALT_EMAC_GMAC_MAC_ADDR51_LOW_t;
54211 #endif /* __ASSEMBLY__ */
54212 
54213 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register from the beginning of the component. */
54214 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST 0x91c
54215 /* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register. */
54216 #define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST))
54217 
54218 /*
54219  * Register : Register 584 (MAC Address52 High Register) - MAC_Address52_High
54220  *
54221  * The MAC Address52 High register holds the upper 16 bits of the 53th 6-byte MAC
54222  * address of the station. Because the MAC address registers are configured to be
54223  * double-synchronized to the (G)MII clock domains, the synchronization is
54224  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
54225  * endian mode) of the MAC Address52 Low Register are written. For proper
54226  * synchronization updates, the consecutive writes to this Address Low Register
54227  * should be performed after at least four clock cycles in the destination clock
54228  * domain.
54229  *
54230  * Note that all MAC Address High registers (except MAC Address0 High) have the
54231  * same format.
54232  *
54233  * Register Layout
54234  *
54235  * Bits | Access | Reset | Description
54236  * :--------|:-------|:-------|:----------------------
54237  * [15:0] | RW | 0xffff | MAC Address52 [47:32]
54238  * [23:16] | ??? | 0x0 | *UNDEFINED*
54239  * [24] | RW | 0x0 | Mask Byte Control
54240  * [25] | RW | 0x0 | Mask Byte Control
54241  * [26] | RW | 0x0 | Mask Byte Control
54242  * [27] | RW | 0x0 | Mask Byte Control
54243  * [28] | RW | 0x0 | Mask Byte Control
54244  * [29] | RW | 0x0 | Mask Byte Control
54245  * [30] | RW | 0x0 | Source Address
54246  * [31] | RW | 0x0 | Address Enable
54247  *
54248  */
54249 /*
54250  * Field : MAC Address52 [47:32] - addrhi
54251  *
54252  * This field contains the upper 16 bits (47:32) of the 53th 6-byte MAC address.
54253  *
54254  * Field Access Macros:
54255  *
54256  */
54257 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
54258 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_LSB 0
54259 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
54260 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_MSB 15
54261 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
54262 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_WIDTH 16
54263 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
54264 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET_MSK 0x0000ffff
54265 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
54266 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_CLR_MSK 0xffff0000
54267 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
54268 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_RESET 0xffff
54269 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI field value from a register. */
54270 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54271 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value suitable for setting the register. */
54272 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54273 
54274 /*
54275  * Field : Mask Byte Control - mbc_0
54276  *
54277  * This array of bits are mask control bits for comparison of each of the MAC
54278  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54279  * received DA or SA with the contents of MAC Address52 high and low registers.
54280  * Each bit controls the masking of the bytes. You can filter a group of addresses
54281  * (known as group address filtering) by masking one or more bytes of the address.
54282  *
54283  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54284  *
54285  * Field Enumeration Values:
54286  *
54287  * Enum | Value | Description
54288  * :----------------------------------------------|:------|:------------------------------------
54289  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54290  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54291  *
54292  * Field Access Macros:
54293  *
54294  */
54295 /*
54296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0
54297  *
54298  * Byte is unmasked (i.e. is compared)
54299  */
54300 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED 0x0
54301 /*
54302  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0
54303  *
54304  * Byte is masked (i.e. not compared)
54305  */
54306 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED 0x1
54307 
54308 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
54309 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_LSB 24
54310 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
54311 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_MSB 24
54312 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
54313 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_WIDTH 1
54314 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */
54315 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET_MSK 0x01000000
54316 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */
54317 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_CLR_MSK 0xfeffffff
54318 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
54319 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_RESET 0x0
54320 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 field value from a register. */
54321 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
54322 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value suitable for setting the register. */
54323 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
54324 
54325 /*
54326  * Field : Mask Byte Control - mbc_1
54327  *
54328  * This array of bits are mask control bits for comparison of each of the MAC
54329  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54330  * received DA or SA with the contents of MAC Address52 high and low registers.
54331  * Each bit controls the masking of the bytes. You can filter a group of addresses
54332  * (known as group address filtering) by masking one or more bytes of the address.
54333  *
54334  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54335  *
54336  * Field Enumeration Values:
54337  *
54338  * Enum | Value | Description
54339  * :----------------------------------------------|:------|:------------------------------------
54340  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54341  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54342  *
54343  * Field Access Macros:
54344  *
54345  */
54346 /*
54347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1
54348  *
54349  * Byte is unmasked (i.e. is compared)
54350  */
54351 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED 0x0
54352 /*
54353  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1
54354  *
54355  * Byte is masked (i.e. not compared)
54356  */
54357 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED 0x1
54358 
54359 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
54360 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_LSB 25
54361 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
54362 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_MSB 25
54363 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
54364 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_WIDTH 1
54365 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */
54366 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET_MSK 0x02000000
54367 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */
54368 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_CLR_MSK 0xfdffffff
54369 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
54370 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_RESET 0x0
54371 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 field value from a register. */
54372 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
54373 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value suitable for setting the register. */
54374 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
54375 
54376 /*
54377  * Field : Mask Byte Control - mbc_2
54378  *
54379  * This array of bits are mask control bits for comparison of each of the MAC
54380  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54381  * received DA or SA with the contents of MAC Address52 high and low registers.
54382  * Each bit controls the masking of the bytes. You can filter a group of addresses
54383  * (known as group address filtering) by masking one or more bytes of the address.
54384  *
54385  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54386  *
54387  * Field Enumeration Values:
54388  *
54389  * Enum | Value | Description
54390  * :----------------------------------------------|:------|:------------------------------------
54391  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54392  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54393  *
54394  * Field Access Macros:
54395  *
54396  */
54397 /*
54398  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2
54399  *
54400  * Byte is unmasked (i.e. is compared)
54401  */
54402 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED 0x0
54403 /*
54404  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2
54405  *
54406  * Byte is masked (i.e. not compared)
54407  */
54408 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED 0x1
54409 
54410 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
54411 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_LSB 26
54412 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
54413 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_MSB 26
54414 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
54415 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_WIDTH 1
54416 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */
54417 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET_MSK 0x04000000
54418 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */
54419 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_CLR_MSK 0xfbffffff
54420 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
54421 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_RESET 0x0
54422 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 field value from a register. */
54423 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
54424 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value suitable for setting the register. */
54425 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
54426 
54427 /*
54428  * Field : Mask Byte Control - mbc_3
54429  *
54430  * This array of bits are mask control bits for comparison of each of the MAC
54431  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54432  * received DA or SA with the contents of MAC Address52 high and low registers.
54433  * Each bit controls the masking of the bytes. You can filter a group of addresses
54434  * (known as group address filtering) by masking one or more bytes of the address.
54435  *
54436  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54437  *
54438  * Field Enumeration Values:
54439  *
54440  * Enum | Value | Description
54441  * :----------------------------------------------|:------|:------------------------------------
54442  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54443  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54444  *
54445  * Field Access Macros:
54446  *
54447  */
54448 /*
54449  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3
54450  *
54451  * Byte is unmasked (i.e. is compared)
54452  */
54453 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED 0x0
54454 /*
54455  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3
54456  *
54457  * Byte is masked (i.e. not compared)
54458  */
54459 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED 0x1
54460 
54461 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
54462 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_LSB 27
54463 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
54464 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_MSB 27
54465 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
54466 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_WIDTH 1
54467 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */
54468 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET_MSK 0x08000000
54469 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */
54470 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_CLR_MSK 0xf7ffffff
54471 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
54472 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_RESET 0x0
54473 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 field value from a register. */
54474 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
54475 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value suitable for setting the register. */
54476 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
54477 
54478 /*
54479  * Field : Mask Byte Control - mbc_4
54480  *
54481  * This array of bits are mask control bits for comparison of each of the MAC
54482  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54483  * received DA or SA with the contents of MAC Address52 high and low registers.
54484  * Each bit controls the masking of the bytes. You can filter a group of addresses
54485  * (known as group address filtering) by masking one or more bytes of the address.
54486  *
54487  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54488  *
54489  * Field Enumeration Values:
54490  *
54491  * Enum | Value | Description
54492  * :----------------------------------------------|:------|:------------------------------------
54493  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54494  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54495  *
54496  * Field Access Macros:
54497  *
54498  */
54499 /*
54500  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4
54501  *
54502  * Byte is unmasked (i.e. is compared)
54503  */
54504 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED 0x0
54505 /*
54506  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4
54507  *
54508  * Byte is masked (i.e. not compared)
54509  */
54510 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED 0x1
54511 
54512 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
54513 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_LSB 28
54514 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
54515 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_MSB 28
54516 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
54517 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_WIDTH 1
54518 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */
54519 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET_MSK 0x10000000
54520 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */
54521 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_CLR_MSK 0xefffffff
54522 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
54523 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_RESET 0x0
54524 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 field value from a register. */
54525 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
54526 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value suitable for setting the register. */
54527 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
54528 
54529 /*
54530  * Field : Mask Byte Control - mbc_5
54531  *
54532  * This array of bits are mask control bits for comparison of each of the MAC
54533  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54534  * received DA or SA with the contents of MAC Address52 high and low registers.
54535  * Each bit controls the masking of the bytes. You can filter a group of addresses
54536  * (known as group address filtering) by masking one or more bytes of the address.
54537  *
54538  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54539  *
54540  * Field Enumeration Values:
54541  *
54542  * Enum | Value | Description
54543  * :----------------------------------------------|:------|:------------------------------------
54544  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54545  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54546  *
54547  * Field Access Macros:
54548  *
54549  */
54550 /*
54551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5
54552  *
54553  * Byte is unmasked (i.e. is compared)
54554  */
54555 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED 0x0
54556 /*
54557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5
54558  *
54559  * Byte is masked (i.e. not compared)
54560  */
54561 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED 0x1
54562 
54563 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
54564 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_LSB 29
54565 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
54566 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_MSB 29
54567 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
54568 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_WIDTH 1
54569 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */
54570 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET_MSK 0x20000000
54571 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */
54572 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_CLR_MSK 0xdfffffff
54573 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
54574 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_RESET 0x0
54575 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 field value from a register. */
54576 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
54577 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value suitable for setting the register. */
54578 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
54579 
54580 /*
54581  * Field : Source Address - sa
54582  *
54583  * When this bit is enabled, the MAC Address52[47:0] is used to compare with the SA
54584  * fields of the received frame. When this bit is disabled, the MAC Address52[47:0]
54585  * is used to compare with the DA fields of the received frame.
54586  *
54587  * Field Enumeration Values:
54588  *
54589  * Enum | Value | Description
54590  * :----------------------------------------|:------|:-----------------------------
54591  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
54592  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END | 0x1 | MAC address compare enabled
54593  *
54594  * Field Access Macros:
54595  *
54596  */
54597 /*
54598  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA
54599  *
54600  * MAC address compare disabled
54601  */
54602 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD 0x0
54603 /*
54604  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA
54605  *
54606  * MAC address compare enabled
54607  */
54608 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END 0x1
54609 
54610 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
54611 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_LSB 30
54612 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
54613 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_MSB 30
54614 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
54615 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_WIDTH 1
54616 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */
54617 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET_MSK 0x40000000
54618 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */
54619 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_CLR_MSK 0xbfffffff
54620 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
54621 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_RESET 0x0
54622 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA field value from a register. */
54623 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
54624 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value suitable for setting the register. */
54625 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
54626 
54627 /*
54628  * Field : Address Enable - ae
54629  *
54630  * When this bit is enabled, the address filter block uses the 53th MAC address for
54631  * perfect filtering. When this bit is disabled, the address filter block ignores
54632  * the address for filtering.
54633  *
54634  * Field Enumeration Values:
54635  *
54636  * Enum | Value | Description
54637  * :----------------------------------------|:------|:--------------------------------------
54638  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
54639  * ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
54640  *
54641  * Field Access Macros:
54642  *
54643  */
54644 /*
54645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
54646  *
54647  * Second MAC address filtering disabled
54648  */
54649 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD 0x0
54650 /*
54651  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
54652  *
54653  * Second MAC address filtering enabled
54654  */
54655 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END 0x1
54656 
54657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
54658 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_LSB 31
54659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
54660 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_MSB 31
54661 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
54662 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_WIDTH 1
54663 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
54664 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET_MSK 0x80000000
54665 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
54666 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_CLR_MSK 0x7fffffff
54667 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
54668 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_RESET 0x0
54669 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE field value from a register. */
54670 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
54671 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value suitable for setting the register. */
54672 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
54673 
54674 #ifndef __ASSEMBLY__
54675 /*
54676  * WARNING: The C register and register group struct declarations are provided for
54677  * convenience and illustrative purposes. They should, however, be used with
54678  * caution as the C language standard provides no guarantees about the alignment or
54679  * atomicity of device memory accesses. The recommended practice for writing
54680  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54681  * alt_write_word() functions.
54682  *
54683  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH.
54684  */
54685 struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s
54686 {
54687  uint32_t addrhi : 16; /* MAC Address52 [47:32] */
54688  uint32_t : 8; /* *UNDEFINED* */
54689  uint32_t mbc_0 : 1; /* Mask Byte Control */
54690  uint32_t mbc_1 : 1; /* Mask Byte Control */
54691  uint32_t mbc_2 : 1; /* Mask Byte Control */
54692  uint32_t mbc_3 : 1; /* Mask Byte Control */
54693  uint32_t mbc_4 : 1; /* Mask Byte Control */
54694  uint32_t mbc_5 : 1; /* Mask Byte Control */
54695  uint32_t sa : 1; /* Source Address */
54696  uint32_t ae : 1; /* Address Enable */
54697 };
54698 
54699 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH. */
54700 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t;
54701 #endif /* __ASSEMBLY__ */
54702 
54703 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register from the beginning of the component. */
54704 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST 0x920
54705 /* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register. */
54706 #define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST))
54707 
54708 /*
54709  * Register : Register 585 (MAC Address52 Low Register) - MAC_Address52_Low
54710  *
54711  * The MAC Address52 Low register holds the lower 32 bits of the 53th 6-byte MAC
54712  * address of the station.
54713  *
54714  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
54715  * format.
54716  *
54717  * Register Layout
54718  *
54719  * Bits | Access | Reset | Description
54720  * :-------|:-------|:-----------|:---------------------
54721  * [31:0] | RW | 0xffffffff | MAC Address52 [31:0]
54722  *
54723  */
54724 /*
54725  * Field : MAC Address52 [31:0] - addrlo
54726  *
54727  * This field contains the lower 32 bits of the 53th 6-byte MAC address. The
54728  * content of this field is undefined until loaded by software after the
54729  * initialization process.
54730  *
54731  * Field Access Macros:
54732  *
54733  */
54734 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
54735 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_LSB 0
54736 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
54737 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_MSB 31
54738 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
54739 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_WIDTH 32
54740 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
54741 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET_MSK 0xffffffff
54742 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
54743 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_CLR_MSK 0x00000000
54744 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
54745 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_RESET 0xffffffff
54746 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO field value from a register. */
54747 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
54748 /* Produces a ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value suitable for setting the register. */
54749 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
54750 
54751 #ifndef __ASSEMBLY__
54752 /*
54753  * WARNING: The C register and register group struct declarations are provided for
54754  * convenience and illustrative purposes. They should, however, be used with
54755  * caution as the C language standard provides no guarantees about the alignment or
54756  * atomicity of device memory accesses. The recommended practice for writing
54757  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
54758  * alt_write_word() functions.
54759  *
54760  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW.
54761  */
54762 struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s
54763 {
54764  uint32_t addrlo : 32; /* MAC Address52 [31:0] */
54765 };
54766 
54767 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW. */
54768 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s ALT_EMAC_GMAC_MAC_ADDR52_LOW_t;
54769 #endif /* __ASSEMBLY__ */
54770 
54771 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register from the beginning of the component. */
54772 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST 0x924
54773 /* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register. */
54774 #define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST))
54775 
54776 /*
54777  * Register : Register 586 (MAC Address53 High Register) - MAC_Address53_High
54778  *
54779  * The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC
54780  * address of the station. Because the MAC address registers are configured to be
54781  * double-synchronized to the (G)MII clock domains, the synchronization is
54782  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
54783  * endian mode) of the MAC Address53 Low Register are written. For proper
54784  * synchronization updates, the consecutive writes to this Address Low Register
54785  * should be performed after at least four clock cycles in the destination clock
54786  * domain.
54787  *
54788  * Note that all MAC Address High registers (except MAC Address0 High) have the
54789  * same format.
54790  *
54791  * Register Layout
54792  *
54793  * Bits | Access | Reset | Description
54794  * :--------|:-------|:-------|:----------------------
54795  * [15:0] | RW | 0xffff | MAC Address53 [47:32]
54796  * [23:16] | ??? | 0x0 | *UNDEFINED*
54797  * [24] | RW | 0x0 | Mask Byte Control
54798  * [25] | RW | 0x0 | Mask Byte Control
54799  * [26] | RW | 0x0 | Mask Byte Control
54800  * [27] | RW | 0x0 | Mask Byte Control
54801  * [28] | RW | 0x0 | Mask Byte Control
54802  * [29] | RW | 0x0 | Mask Byte Control
54803  * [30] | RW | 0x0 | Source Address
54804  * [31] | RW | 0x0 | Address Enable
54805  *
54806  */
54807 /*
54808  * Field : MAC Address53 [47:32] - addrhi
54809  *
54810  * This field contains the upper 16 bits (47:32) of the 54th 6-byte MAC address.
54811  *
54812  * Field Access Macros:
54813  *
54814  */
54815 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
54816 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_LSB 0
54817 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
54818 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_MSB 15
54819 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
54820 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_WIDTH 16
54821 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
54822 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET_MSK 0x0000ffff
54823 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
54824 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_CLR_MSK 0xffff0000
54825 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
54826 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_RESET 0xffff
54827 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI field value from a register. */
54828 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
54829 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value suitable for setting the register. */
54830 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
54831 
54832 /*
54833  * Field : Mask Byte Control - mbc_0
54834  *
54835  * This array of bits are mask control bits for comparison of each of the MAC
54836  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54837  * received DA or SA with the contents of MAC Address53 high and low registers.
54838  * Each bit controls the masking of the bytes. You can filter a group of addresses
54839  * (known as group address filtering) by masking one or more bytes of the address.
54840  *
54841  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54842  *
54843  * Field Enumeration Values:
54844  *
54845  * Enum | Value | Description
54846  * :----------------------------------------------|:------|:------------------------------------
54847  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54848  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54849  *
54850  * Field Access Macros:
54851  *
54852  */
54853 /*
54854  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0
54855  *
54856  * Byte is unmasked (i.e. is compared)
54857  */
54858 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED 0x0
54859 /*
54860  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0
54861  *
54862  * Byte is masked (i.e. not compared)
54863  */
54864 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED 0x1
54865 
54866 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
54867 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_LSB 24
54868 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
54869 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_MSB 24
54870 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
54871 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_WIDTH 1
54872 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */
54873 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET_MSK 0x01000000
54874 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */
54875 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_CLR_MSK 0xfeffffff
54876 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
54877 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_RESET 0x0
54878 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 field value from a register. */
54879 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
54880 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value suitable for setting the register. */
54881 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
54882 
54883 /*
54884  * Field : Mask Byte Control - mbc_1
54885  *
54886  * This array of bits are mask control bits for comparison of each of the MAC
54887  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54888  * received DA or SA with the contents of MAC Address53 high and low registers.
54889  * Each bit controls the masking of the bytes. You can filter a group of addresses
54890  * (known as group address filtering) by masking one or more bytes of the address.
54891  *
54892  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54893  *
54894  * Field Enumeration Values:
54895  *
54896  * Enum | Value | Description
54897  * :----------------------------------------------|:------|:------------------------------------
54898  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54899  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54900  *
54901  * Field Access Macros:
54902  *
54903  */
54904 /*
54905  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1
54906  *
54907  * Byte is unmasked (i.e. is compared)
54908  */
54909 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED 0x0
54910 /*
54911  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1
54912  *
54913  * Byte is masked (i.e. not compared)
54914  */
54915 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED 0x1
54916 
54917 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
54918 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_LSB 25
54919 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
54920 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_MSB 25
54921 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
54922 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_WIDTH 1
54923 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */
54924 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET_MSK 0x02000000
54925 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */
54926 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_CLR_MSK 0xfdffffff
54927 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
54928 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_RESET 0x0
54929 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 field value from a register. */
54930 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
54931 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value suitable for setting the register. */
54932 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
54933 
54934 /*
54935  * Field : Mask Byte Control - mbc_2
54936  *
54937  * This array of bits are mask control bits for comparison of each of the MAC
54938  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54939  * received DA or SA with the contents of MAC Address53 high and low registers.
54940  * Each bit controls the masking of the bytes. You can filter a group of addresses
54941  * (known as group address filtering) by masking one or more bytes of the address.
54942  *
54943  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54944  *
54945  * Field Enumeration Values:
54946  *
54947  * Enum | Value | Description
54948  * :----------------------------------------------|:------|:------------------------------------
54949  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
54950  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
54951  *
54952  * Field Access Macros:
54953  *
54954  */
54955 /*
54956  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2
54957  *
54958  * Byte is unmasked (i.e. is compared)
54959  */
54960 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED 0x0
54961 /*
54962  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2
54963  *
54964  * Byte is masked (i.e. not compared)
54965  */
54966 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED 0x1
54967 
54968 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
54969 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_LSB 26
54970 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
54971 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_MSB 26
54972 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
54973 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_WIDTH 1
54974 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */
54975 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET_MSK 0x04000000
54976 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */
54977 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_CLR_MSK 0xfbffffff
54978 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
54979 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_RESET 0x0
54980 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 field value from a register. */
54981 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
54982 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value suitable for setting the register. */
54983 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
54984 
54985 /*
54986  * Field : Mask Byte Control - mbc_3
54987  *
54988  * This array of bits are mask control bits for comparison of each of the MAC
54989  * Address bytes. When masked, the MAC does not compare the corresponding byte of
54990  * received DA or SA with the contents of MAC Address53 high and low registers.
54991  * Each bit controls the masking of the bytes. You can filter a group of addresses
54992  * (known as group address filtering) by masking one or more bytes of the address.
54993  *
54994  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
54995  *
54996  * Field Enumeration Values:
54997  *
54998  * Enum | Value | Description
54999  * :----------------------------------------------|:------|:------------------------------------
55000  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55001  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55002  *
55003  * Field Access Macros:
55004  *
55005  */
55006 /*
55007  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3
55008  *
55009  * Byte is unmasked (i.e. is compared)
55010  */
55011 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED 0x0
55012 /*
55013  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3
55014  *
55015  * Byte is masked (i.e. not compared)
55016  */
55017 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED 0x1
55018 
55019 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
55020 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_LSB 27
55021 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
55022 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_MSB 27
55023 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
55024 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_WIDTH 1
55025 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */
55026 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET_MSK 0x08000000
55027 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */
55028 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_CLR_MSK 0xf7ffffff
55029 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
55030 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_RESET 0x0
55031 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 field value from a register. */
55032 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
55033 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value suitable for setting the register. */
55034 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
55035 
55036 /*
55037  * Field : Mask Byte Control - mbc_4
55038  *
55039  * This array of bits are mask control bits for comparison of each of the MAC
55040  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55041  * received DA or SA with the contents of MAC Address53 high and low registers.
55042  * Each bit controls the masking of the bytes. You can filter a group of addresses
55043  * (known as group address filtering) by masking one or more bytes of the address.
55044  *
55045  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55046  *
55047  * Field Enumeration Values:
55048  *
55049  * Enum | Value | Description
55050  * :----------------------------------------------|:------|:------------------------------------
55051  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55052  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55053  *
55054  * Field Access Macros:
55055  *
55056  */
55057 /*
55058  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4
55059  *
55060  * Byte is unmasked (i.e. is compared)
55061  */
55062 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED 0x0
55063 /*
55064  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4
55065  *
55066  * Byte is masked (i.e. not compared)
55067  */
55068 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED 0x1
55069 
55070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
55071 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_LSB 28
55072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
55073 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_MSB 28
55074 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
55075 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_WIDTH 1
55076 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */
55077 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET_MSK 0x10000000
55078 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */
55079 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_CLR_MSK 0xefffffff
55080 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
55081 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_RESET 0x0
55082 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 field value from a register. */
55083 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
55084 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value suitable for setting the register. */
55085 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
55086 
55087 /*
55088  * Field : Mask Byte Control - mbc_5
55089  *
55090  * This array of bits are mask control bits for comparison of each of the MAC
55091  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55092  * received DA or SA with the contents of MAC Address53 high and low registers.
55093  * Each bit controls the masking of the bytes. You can filter a group of addresses
55094  * (known as group address filtering) by masking one or more bytes of the address.
55095  *
55096  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55097  *
55098  * Field Enumeration Values:
55099  *
55100  * Enum | Value | Description
55101  * :----------------------------------------------|:------|:------------------------------------
55102  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55103  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55104  *
55105  * Field Access Macros:
55106  *
55107  */
55108 /*
55109  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5
55110  *
55111  * Byte is unmasked (i.e. is compared)
55112  */
55113 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED 0x0
55114 /*
55115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5
55116  *
55117  * Byte is masked (i.e. not compared)
55118  */
55119 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED 0x1
55120 
55121 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
55122 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_LSB 29
55123 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
55124 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_MSB 29
55125 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
55126 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_WIDTH 1
55127 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */
55128 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET_MSK 0x20000000
55129 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */
55130 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_CLR_MSK 0xdfffffff
55131 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
55132 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_RESET 0x0
55133 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 field value from a register. */
55134 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
55135 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value suitable for setting the register. */
55136 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
55137 
55138 /*
55139  * Field : Source Address - sa
55140  *
55141  * When this bit is enabled, the MAC Address53[47:0] is used to compare with the SA
55142  * fields of the received frame. When this bit is disabled, the MAC Address53[47:0]
55143  * is used to compare with the DA fields of the received frame.
55144  *
55145  * Field Enumeration Values:
55146  *
55147  * Enum | Value | Description
55148  * :----------------------------------------|:------|:-----------------------------
55149  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
55150  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END | 0x1 | MAC address compare enabled
55151  *
55152  * Field Access Macros:
55153  *
55154  */
55155 /*
55156  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA
55157  *
55158  * MAC address compare disabled
55159  */
55160 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD 0x0
55161 /*
55162  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA
55163  *
55164  * MAC address compare enabled
55165  */
55166 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END 0x1
55167 
55168 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
55169 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_LSB 30
55170 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
55171 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_MSB 30
55172 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
55173 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_WIDTH 1
55174 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */
55175 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET_MSK 0x40000000
55176 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */
55177 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_CLR_MSK 0xbfffffff
55178 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
55179 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_RESET 0x0
55180 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA field value from a register. */
55181 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
55182 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value suitable for setting the register. */
55183 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
55184 
55185 /*
55186  * Field : Address Enable - ae
55187  *
55188  * When this bit is enabled, the address filter block uses the 54th MAC address for
55189  * perfect filtering. When this bit is disabled, the address filter block ignores
55190  * the address for filtering.
55191  *
55192  * Field Enumeration Values:
55193  *
55194  * Enum | Value | Description
55195  * :----------------------------------------|:------|:--------------------------------------
55196  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
55197  * ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
55198  *
55199  * Field Access Macros:
55200  *
55201  */
55202 /*
55203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
55204  *
55205  * Second MAC address filtering disabled
55206  */
55207 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD 0x0
55208 /*
55209  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
55210  *
55211  * Second MAC address filtering enabled
55212  */
55213 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END 0x1
55214 
55215 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
55216 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_LSB 31
55217 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
55218 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_MSB 31
55219 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
55220 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_WIDTH 1
55221 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
55222 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET_MSK 0x80000000
55223 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
55224 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_CLR_MSK 0x7fffffff
55225 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
55226 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_RESET 0x0
55227 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE field value from a register. */
55228 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55229 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value suitable for setting the register. */
55230 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55231 
55232 #ifndef __ASSEMBLY__
55233 /*
55234  * WARNING: The C register and register group struct declarations are provided for
55235  * convenience and illustrative purposes. They should, however, be used with
55236  * caution as the C language standard provides no guarantees about the alignment or
55237  * atomicity of device memory accesses. The recommended practice for writing
55238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55239  * alt_write_word() functions.
55240  *
55241  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH.
55242  */
55243 struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s
55244 {
55245  uint32_t addrhi : 16; /* MAC Address53 [47:32] */
55246  uint32_t : 8; /* *UNDEFINED* */
55247  uint32_t mbc_0 : 1; /* Mask Byte Control */
55248  uint32_t mbc_1 : 1; /* Mask Byte Control */
55249  uint32_t mbc_2 : 1; /* Mask Byte Control */
55250  uint32_t mbc_3 : 1; /* Mask Byte Control */
55251  uint32_t mbc_4 : 1; /* Mask Byte Control */
55252  uint32_t mbc_5 : 1; /* Mask Byte Control */
55253  uint32_t sa : 1; /* Source Address */
55254  uint32_t ae : 1; /* Address Enable */
55255 };
55256 
55257 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH. */
55258 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t;
55259 #endif /* __ASSEMBLY__ */
55260 
55261 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register from the beginning of the component. */
55262 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST 0x928
55263 /* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register. */
55264 #define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST))
55265 
55266 /*
55267  * Register : Register 587 (MAC Address53 Low Register) - MAC_Address53_Low
55268  *
55269  * The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC
55270  * address of the station.
55271  *
55272  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
55273  * format.
55274  *
55275  * Register Layout
55276  *
55277  * Bits | Access | Reset | Description
55278  * :-------|:-------|:-----------|:---------------------
55279  * [31:0] | RW | 0xffffffff | MAC Address53 [31:0]
55280  *
55281  */
55282 /*
55283  * Field : MAC Address53 [31:0] - addrlo
55284  *
55285  * This field contains the lower 32 bits of the 54th 6-byte MAC address. The
55286  * content of this field is undefined until loaded by software after the
55287  * initialization process.
55288  *
55289  * Field Access Macros:
55290  *
55291  */
55292 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
55293 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_LSB 0
55294 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
55295 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_MSB 31
55296 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
55297 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_WIDTH 32
55298 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
55299 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET_MSK 0xffffffff
55300 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
55301 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_CLR_MSK 0x00000000
55302 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
55303 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_RESET 0xffffffff
55304 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO field value from a register. */
55305 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55306 /* Produces a ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value suitable for setting the register. */
55307 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55308 
55309 #ifndef __ASSEMBLY__
55310 /*
55311  * WARNING: The C register and register group struct declarations are provided for
55312  * convenience and illustrative purposes. They should, however, be used with
55313  * caution as the C language standard provides no guarantees about the alignment or
55314  * atomicity of device memory accesses. The recommended practice for writing
55315  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55316  * alt_write_word() functions.
55317  *
55318  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW.
55319  */
55320 struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s
55321 {
55322  uint32_t addrlo : 32; /* MAC Address53 [31:0] */
55323 };
55324 
55325 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW. */
55326 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s ALT_EMAC_GMAC_MAC_ADDR53_LOW_t;
55327 #endif /* __ASSEMBLY__ */
55328 
55329 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register from the beginning of the component. */
55330 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST 0x92c
55331 /* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register. */
55332 #define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST))
55333 
55334 /*
55335  * Register : Register 588 (MAC Address54 High Register) - MAC_Address54_High
55336  *
55337  * The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC
55338  * address of the station. Because the MAC address registers are configured to be
55339  * double-synchronized to the (G)MII clock domains, the synchronization is
55340  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
55341  * endian mode) of the MAC Address54 Low Register are written. For proper
55342  * synchronization updates, the consecutive writes to this Address Low Register
55343  * should be performed after at least four clock cycles in the destination clock
55344  * domain.
55345  *
55346  * Note that all MAC Address High registers (except MAC Address0 High) have the
55347  * same format.
55348  *
55349  * Register Layout
55350  *
55351  * Bits | Access | Reset | Description
55352  * :--------|:-------|:-------|:----------------------
55353  * [15:0] | RW | 0xffff | MAC Address54 [47:32]
55354  * [23:16] | ??? | 0x0 | *UNDEFINED*
55355  * [24] | RW | 0x0 | Mask Byte Control
55356  * [25] | RW | 0x0 | Mask Byte Control
55357  * [26] | RW | 0x0 | Mask Byte Control
55358  * [27] | RW | 0x0 | Mask Byte Control
55359  * [28] | RW | 0x0 | Mask Byte Control
55360  * [29] | RW | 0x0 | Mask Byte Control
55361  * [30] | RW | 0x0 | Source Address
55362  * [31] | RW | 0x0 | Address Enable
55363  *
55364  */
55365 /*
55366  * Field : MAC Address54 [47:32] - addrhi
55367  *
55368  * This field contains the upper 16 bits (47:32) of the 55th 6-byte MAC address.
55369  *
55370  * Field Access Macros:
55371  *
55372  */
55373 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
55374 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_LSB 0
55375 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
55376 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_MSB 15
55377 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
55378 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_WIDTH 16
55379 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
55380 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET_MSK 0x0000ffff
55381 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
55382 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_CLR_MSK 0xffff0000
55383 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
55384 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_RESET 0xffff
55385 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI field value from a register. */
55386 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55387 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value suitable for setting the register. */
55388 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55389 
55390 /*
55391  * Field : Mask Byte Control - mbc_0
55392  *
55393  * This array of bits are mask control bits for comparison of each of the MAC
55394  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55395  * received DA or SA with the contents of MAC Address54 high and low registers.
55396  * Each bit controls the masking of the bytes. You can filter a group of addresses
55397  * (known as group address filtering) by masking one or more bytes of the address.
55398  *
55399  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55400  *
55401  * Field Enumeration Values:
55402  *
55403  * Enum | Value | Description
55404  * :----------------------------------------------|:------|:------------------------------------
55405  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55406  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55407  *
55408  * Field Access Macros:
55409  *
55410  */
55411 /*
55412  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0
55413  *
55414  * Byte is unmasked (i.e. is compared)
55415  */
55416 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED 0x0
55417 /*
55418  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0
55419  *
55420  * Byte is masked (i.e. not compared)
55421  */
55422 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED 0x1
55423 
55424 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
55425 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_LSB 24
55426 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
55427 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_MSB 24
55428 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
55429 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_WIDTH 1
55430 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */
55431 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET_MSK 0x01000000
55432 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */
55433 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_CLR_MSK 0xfeffffff
55434 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
55435 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_RESET 0x0
55436 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 field value from a register. */
55437 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
55438 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value suitable for setting the register. */
55439 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
55440 
55441 /*
55442  * Field : Mask Byte Control - mbc_1
55443  *
55444  * This array of bits are mask control bits for comparison of each of the MAC
55445  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55446  * received DA or SA with the contents of MAC Address54 high and low registers.
55447  * Each bit controls the masking of the bytes. You can filter a group of addresses
55448  * (known as group address filtering) by masking one or more bytes of the address.
55449  *
55450  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55451  *
55452  * Field Enumeration Values:
55453  *
55454  * Enum | Value | Description
55455  * :----------------------------------------------|:------|:------------------------------------
55456  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55457  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55458  *
55459  * Field Access Macros:
55460  *
55461  */
55462 /*
55463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1
55464  *
55465  * Byte is unmasked (i.e. is compared)
55466  */
55467 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED 0x0
55468 /*
55469  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1
55470  *
55471  * Byte is masked (i.e. not compared)
55472  */
55473 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED 0x1
55474 
55475 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
55476 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_LSB 25
55477 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
55478 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_MSB 25
55479 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
55480 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_WIDTH 1
55481 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */
55482 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET_MSK 0x02000000
55483 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */
55484 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_CLR_MSK 0xfdffffff
55485 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
55486 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_RESET 0x0
55487 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 field value from a register. */
55488 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
55489 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value suitable for setting the register. */
55490 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
55491 
55492 /*
55493  * Field : Mask Byte Control - mbc_2
55494  *
55495  * This array of bits are mask control bits for comparison of each of the MAC
55496  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55497  * received DA or SA with the contents of MAC Address54 high and low registers.
55498  * Each bit controls the masking of the bytes. You can filter a group of addresses
55499  * (known as group address filtering) by masking one or more bytes of the address.
55500  *
55501  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55502  *
55503  * Field Enumeration Values:
55504  *
55505  * Enum | Value | Description
55506  * :----------------------------------------------|:------|:------------------------------------
55507  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55508  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55509  *
55510  * Field Access Macros:
55511  *
55512  */
55513 /*
55514  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2
55515  *
55516  * Byte is unmasked (i.e. is compared)
55517  */
55518 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED 0x0
55519 /*
55520  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2
55521  *
55522  * Byte is masked (i.e. not compared)
55523  */
55524 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED 0x1
55525 
55526 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
55527 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_LSB 26
55528 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
55529 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_MSB 26
55530 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
55531 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_WIDTH 1
55532 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */
55533 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET_MSK 0x04000000
55534 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */
55535 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_CLR_MSK 0xfbffffff
55536 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
55537 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_RESET 0x0
55538 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 field value from a register. */
55539 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
55540 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value suitable for setting the register. */
55541 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
55542 
55543 /*
55544  * Field : Mask Byte Control - mbc_3
55545  *
55546  * This array of bits are mask control bits for comparison of each of the MAC
55547  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55548  * received DA or SA with the contents of MAC Address54 high and low registers.
55549  * Each bit controls the masking of the bytes. You can filter a group of addresses
55550  * (known as group address filtering) by masking one or more bytes of the address.
55551  *
55552  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55553  *
55554  * Field Enumeration Values:
55555  *
55556  * Enum | Value | Description
55557  * :----------------------------------------------|:------|:------------------------------------
55558  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55559  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55560  *
55561  * Field Access Macros:
55562  *
55563  */
55564 /*
55565  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3
55566  *
55567  * Byte is unmasked (i.e. is compared)
55568  */
55569 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED 0x0
55570 /*
55571  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3
55572  *
55573  * Byte is masked (i.e. not compared)
55574  */
55575 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED 0x1
55576 
55577 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
55578 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_LSB 27
55579 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
55580 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_MSB 27
55581 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
55582 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_WIDTH 1
55583 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */
55584 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET_MSK 0x08000000
55585 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */
55586 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_CLR_MSK 0xf7ffffff
55587 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
55588 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_RESET 0x0
55589 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 field value from a register. */
55590 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
55591 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value suitable for setting the register. */
55592 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
55593 
55594 /*
55595  * Field : Mask Byte Control - mbc_4
55596  *
55597  * This array of bits are mask control bits for comparison of each of the MAC
55598  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55599  * received DA or SA with the contents of MAC Address54 high and low registers.
55600  * Each bit controls the masking of the bytes. You can filter a group of addresses
55601  * (known as group address filtering) by masking one or more bytes of the address.
55602  *
55603  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55604  *
55605  * Field Enumeration Values:
55606  *
55607  * Enum | Value | Description
55608  * :----------------------------------------------|:------|:------------------------------------
55609  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55610  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55611  *
55612  * Field Access Macros:
55613  *
55614  */
55615 /*
55616  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4
55617  *
55618  * Byte is unmasked (i.e. is compared)
55619  */
55620 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED 0x0
55621 /*
55622  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4
55623  *
55624  * Byte is masked (i.e. not compared)
55625  */
55626 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED 0x1
55627 
55628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
55629 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_LSB 28
55630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
55631 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_MSB 28
55632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
55633 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_WIDTH 1
55634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */
55635 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET_MSK 0x10000000
55636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */
55637 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_CLR_MSK 0xefffffff
55638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
55639 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_RESET 0x0
55640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 field value from a register. */
55641 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
55642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value suitable for setting the register. */
55643 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
55644 
55645 /*
55646  * Field : Mask Byte Control - mbc_5
55647  *
55648  * This array of bits are mask control bits for comparison of each of the MAC
55649  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55650  * received DA or SA with the contents of MAC Address54 high and low registers.
55651  * Each bit controls the masking of the bytes. You can filter a group of addresses
55652  * (known as group address filtering) by masking one or more bytes of the address.
55653  *
55654  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55655  *
55656  * Field Enumeration Values:
55657  *
55658  * Enum | Value | Description
55659  * :----------------------------------------------|:------|:------------------------------------
55660  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55661  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55662  *
55663  * Field Access Macros:
55664  *
55665  */
55666 /*
55667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5
55668  *
55669  * Byte is unmasked (i.e. is compared)
55670  */
55671 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED 0x0
55672 /*
55673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5
55674  *
55675  * Byte is masked (i.e. not compared)
55676  */
55677 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED 0x1
55678 
55679 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
55680 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_LSB 29
55681 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
55682 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_MSB 29
55683 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
55684 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_WIDTH 1
55685 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */
55686 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET_MSK 0x20000000
55687 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */
55688 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_CLR_MSK 0xdfffffff
55689 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
55690 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_RESET 0x0
55691 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 field value from a register. */
55692 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
55693 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value suitable for setting the register. */
55694 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
55695 
55696 /*
55697  * Field : Source Address - sa
55698  *
55699  * When this bit is enabled, the MAC Address54[47:0] is used to compare with the SA
55700  * fields of the received frame. When this bit is disabled, the MAC Address54[47:0]
55701  * is used to compare with the DA fields of the received frame.
55702  *
55703  * Field Enumeration Values:
55704  *
55705  * Enum | Value | Description
55706  * :----------------------------------------|:------|:-----------------------------
55707  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
55708  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END | 0x1 | MAC address compare enabled
55709  *
55710  * Field Access Macros:
55711  *
55712  */
55713 /*
55714  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA
55715  *
55716  * MAC address compare disabled
55717  */
55718 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD 0x0
55719 /*
55720  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA
55721  *
55722  * MAC address compare enabled
55723  */
55724 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END 0x1
55725 
55726 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
55727 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_LSB 30
55728 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
55729 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_MSB 30
55730 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
55731 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_WIDTH 1
55732 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */
55733 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET_MSK 0x40000000
55734 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */
55735 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_CLR_MSK 0xbfffffff
55736 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
55737 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_RESET 0x0
55738 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA field value from a register. */
55739 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
55740 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value suitable for setting the register. */
55741 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
55742 
55743 /*
55744  * Field : Address Enable - ae
55745  *
55746  * When this bit is enabled, the address filter block uses the 55th MAC address for
55747  * perfect filtering. When this bit is disabled, the address filter block ignores
55748  * the address for filtering.
55749  *
55750  * Field Enumeration Values:
55751  *
55752  * Enum | Value | Description
55753  * :----------------------------------------|:------|:--------------------------------------
55754  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
55755  * ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
55756  *
55757  * Field Access Macros:
55758  *
55759  */
55760 /*
55761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
55762  *
55763  * Second MAC address filtering disabled
55764  */
55765 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD 0x0
55766 /*
55767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
55768  *
55769  * Second MAC address filtering enabled
55770  */
55771 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END 0x1
55772 
55773 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
55774 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_LSB 31
55775 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
55776 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_MSB 31
55777 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
55778 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_WIDTH 1
55779 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
55780 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET_MSK 0x80000000
55781 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
55782 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_CLR_MSK 0x7fffffff
55783 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
55784 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_RESET 0x0
55785 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE field value from a register. */
55786 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
55787 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value suitable for setting the register. */
55788 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
55789 
55790 #ifndef __ASSEMBLY__
55791 /*
55792  * WARNING: The C register and register group struct declarations are provided for
55793  * convenience and illustrative purposes. They should, however, be used with
55794  * caution as the C language standard provides no guarantees about the alignment or
55795  * atomicity of device memory accesses. The recommended practice for writing
55796  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55797  * alt_write_word() functions.
55798  *
55799  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH.
55800  */
55801 struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s
55802 {
55803  uint32_t addrhi : 16; /* MAC Address54 [47:32] */
55804  uint32_t : 8; /* *UNDEFINED* */
55805  uint32_t mbc_0 : 1; /* Mask Byte Control */
55806  uint32_t mbc_1 : 1; /* Mask Byte Control */
55807  uint32_t mbc_2 : 1; /* Mask Byte Control */
55808  uint32_t mbc_3 : 1; /* Mask Byte Control */
55809  uint32_t mbc_4 : 1; /* Mask Byte Control */
55810  uint32_t mbc_5 : 1; /* Mask Byte Control */
55811  uint32_t sa : 1; /* Source Address */
55812  uint32_t ae : 1; /* Address Enable */
55813 };
55814 
55815 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH. */
55816 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t;
55817 #endif /* __ASSEMBLY__ */
55818 
55819 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register from the beginning of the component. */
55820 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST 0x930
55821 /* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register. */
55822 #define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST))
55823 
55824 /*
55825  * Register : Register 589 (MAC Address54 Low Register) - MAC_Address54_Low
55826  *
55827  * The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC
55828  * address of the station.
55829  *
55830  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
55831  * format.
55832  *
55833  * Register Layout
55834  *
55835  * Bits | Access | Reset | Description
55836  * :-------|:-------|:-----------|:---------------------
55837  * [31:0] | RW | 0xffffffff | MAC Address54 [31:0]
55838  *
55839  */
55840 /*
55841  * Field : MAC Address54 [31:0] - addrlo
55842  *
55843  * This field contains the lower 32 bits of the 55th 6-byte MAC address. The
55844  * content of this field is undefined until loaded by software after the
55845  * initialization process.
55846  *
55847  * Field Access Macros:
55848  *
55849  */
55850 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
55851 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_LSB 0
55852 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
55853 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_MSB 31
55854 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
55855 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_WIDTH 32
55856 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
55857 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET_MSK 0xffffffff
55858 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
55859 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_CLR_MSK 0x00000000
55860 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
55861 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_RESET 0xffffffff
55862 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO field value from a register. */
55863 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
55864 /* Produces a ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value suitable for setting the register. */
55865 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
55866 
55867 #ifndef __ASSEMBLY__
55868 /*
55869  * WARNING: The C register and register group struct declarations are provided for
55870  * convenience and illustrative purposes. They should, however, be used with
55871  * caution as the C language standard provides no guarantees about the alignment or
55872  * atomicity of device memory accesses. The recommended practice for writing
55873  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
55874  * alt_write_word() functions.
55875  *
55876  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW.
55877  */
55878 struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s
55879 {
55880  uint32_t addrlo : 32; /* MAC Address54 [31:0] */
55881 };
55882 
55883 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW. */
55884 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s ALT_EMAC_GMAC_MAC_ADDR54_LOW_t;
55885 #endif /* __ASSEMBLY__ */
55886 
55887 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register from the beginning of the component. */
55888 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST 0x934
55889 /* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register. */
55890 #define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST))
55891 
55892 /*
55893  * Register : Register 590 (MAC Address55 High Register) - MAC_Address55_High
55894  *
55895  * The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC
55896  * address of the station. Because the MAC address registers are configured to be
55897  * double-synchronized to the (G)MII clock domains, the synchronization is
55898  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
55899  * endian mode) of the MAC Address55 Low Register are written. For proper
55900  * synchronization updates, the consecutive writes to this Address Low Register
55901  * should be performed after at least four clock cycles in the destination clock
55902  * domain.
55903  *
55904  * Note that all MAC Address High registers (except MAC Address0 High) have the
55905  * same format.
55906  *
55907  * Register Layout
55908  *
55909  * Bits | Access | Reset | Description
55910  * :--------|:-------|:-------|:----------------------
55911  * [15:0] | RW | 0xffff | MAC Address55 [47:32]
55912  * [23:16] | ??? | 0x0 | *UNDEFINED*
55913  * [24] | RW | 0x0 | Mask Byte Control
55914  * [25] | RW | 0x0 | Mask Byte Control
55915  * [26] | RW | 0x0 | Mask Byte Control
55916  * [27] | RW | 0x0 | Mask Byte Control
55917  * [28] | RW | 0x0 | Mask Byte Control
55918  * [29] | RW | 0x0 | Mask Byte Control
55919  * [30] | RW | 0x0 | Source Address
55920  * [31] | RW | 0x0 | Address Enable
55921  *
55922  */
55923 /*
55924  * Field : MAC Address55 [47:32] - addrhi
55925  *
55926  * This field contains the upper 16 bits (47:32) of the 56th 6-byte MAC address.
55927  *
55928  * Field Access Macros:
55929  *
55930  */
55931 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
55932 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_LSB 0
55933 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
55934 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_MSB 15
55935 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
55936 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_WIDTH 16
55937 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
55938 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET_MSK 0x0000ffff
55939 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
55940 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_CLR_MSK 0xffff0000
55941 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
55942 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_RESET 0xffff
55943 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI field value from a register. */
55944 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
55945 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value suitable for setting the register. */
55946 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
55947 
55948 /*
55949  * Field : Mask Byte Control - mbc_0
55950  *
55951  * This array of bits are mask control bits for comparison of each of the MAC
55952  * Address bytes. When masked, the MAC does not compare the corresponding byte of
55953  * received DA or SA with the contents of MAC Address55 high and low registers.
55954  * Each bit controls the masking of the bytes. You can filter a group of addresses
55955  * (known as group address filtering) by masking one or more bytes of the address.
55956  *
55957  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
55958  *
55959  * Field Enumeration Values:
55960  *
55961  * Enum | Value | Description
55962  * :----------------------------------------------|:------|:------------------------------------
55963  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
55964  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
55965  *
55966  * Field Access Macros:
55967  *
55968  */
55969 /*
55970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0
55971  *
55972  * Byte is unmasked (i.e. is compared)
55973  */
55974 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED 0x0
55975 /*
55976  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0
55977  *
55978  * Byte is masked (i.e. not compared)
55979  */
55980 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED 0x1
55981 
55982 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
55983 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_LSB 24
55984 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
55985 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_MSB 24
55986 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
55987 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_WIDTH 1
55988 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */
55989 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET_MSK 0x01000000
55990 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */
55991 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_CLR_MSK 0xfeffffff
55992 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
55993 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_RESET 0x0
55994 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 field value from a register. */
55995 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
55996 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value suitable for setting the register. */
55997 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
55998 
55999 /*
56000  * Field : Mask Byte Control - mbc_1
56001  *
56002  * This array of bits are mask control bits for comparison of each of the MAC
56003  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56004  * received DA or SA with the contents of MAC Address55 high and low registers.
56005  * Each bit controls the masking of the bytes. You can filter a group of addresses
56006  * (known as group address filtering) by masking one or more bytes of the address.
56007  *
56008  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56009  *
56010  * Field Enumeration Values:
56011  *
56012  * Enum | Value | Description
56013  * :----------------------------------------------|:------|:------------------------------------
56014  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56015  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56016  *
56017  * Field Access Macros:
56018  *
56019  */
56020 /*
56021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1
56022  *
56023  * Byte is unmasked (i.e. is compared)
56024  */
56025 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED 0x0
56026 /*
56027  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1
56028  *
56029  * Byte is masked (i.e. not compared)
56030  */
56031 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED 0x1
56032 
56033 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
56034 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_LSB 25
56035 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
56036 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_MSB 25
56037 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
56038 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_WIDTH 1
56039 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */
56040 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET_MSK 0x02000000
56041 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */
56042 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_CLR_MSK 0xfdffffff
56043 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
56044 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_RESET 0x0
56045 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 field value from a register. */
56046 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
56047 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value suitable for setting the register. */
56048 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
56049 
56050 /*
56051  * Field : Mask Byte Control - mbc_2
56052  *
56053  * This array of bits are mask control bits for comparison of each of the MAC
56054  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56055  * received DA or SA with the contents of MAC Address55 high and low registers.
56056  * Each bit controls the masking of the bytes. You can filter a group of addresses
56057  * (known as group address filtering) by masking one or more bytes of the address.
56058  *
56059  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56060  *
56061  * Field Enumeration Values:
56062  *
56063  * Enum | Value | Description
56064  * :----------------------------------------------|:------|:------------------------------------
56065  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56066  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56067  *
56068  * Field Access Macros:
56069  *
56070  */
56071 /*
56072  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2
56073  *
56074  * Byte is unmasked (i.e. is compared)
56075  */
56076 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED 0x0
56077 /*
56078  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2
56079  *
56080  * Byte is masked (i.e. not compared)
56081  */
56082 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED 0x1
56083 
56084 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
56085 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_LSB 26
56086 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
56087 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_MSB 26
56088 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
56089 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_WIDTH 1
56090 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */
56091 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET_MSK 0x04000000
56092 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */
56093 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_CLR_MSK 0xfbffffff
56094 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
56095 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_RESET 0x0
56096 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 field value from a register. */
56097 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
56098 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value suitable for setting the register. */
56099 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
56100 
56101 /*
56102  * Field : Mask Byte Control - mbc_3
56103  *
56104  * This array of bits are mask control bits for comparison of each of the MAC
56105  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56106  * received DA or SA with the contents of MAC Address55 high and low registers.
56107  * Each bit controls the masking of the bytes. You can filter a group of addresses
56108  * (known as group address filtering) by masking one or more bytes of the address.
56109  *
56110  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56111  *
56112  * Field Enumeration Values:
56113  *
56114  * Enum | Value | Description
56115  * :----------------------------------------------|:------|:------------------------------------
56116  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56117  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56118  *
56119  * Field Access Macros:
56120  *
56121  */
56122 /*
56123  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3
56124  *
56125  * Byte is unmasked (i.e. is compared)
56126  */
56127 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED 0x0
56128 /*
56129  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3
56130  *
56131  * Byte is masked (i.e. not compared)
56132  */
56133 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED 0x1
56134 
56135 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
56136 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_LSB 27
56137 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
56138 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_MSB 27
56139 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
56140 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_WIDTH 1
56141 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */
56142 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET_MSK 0x08000000
56143 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */
56144 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_CLR_MSK 0xf7ffffff
56145 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
56146 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_RESET 0x0
56147 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 field value from a register. */
56148 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
56149 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value suitable for setting the register. */
56150 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
56151 
56152 /*
56153  * Field : Mask Byte Control - mbc_4
56154  *
56155  * This array of bits are mask control bits for comparison of each of the MAC
56156  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56157  * received DA or SA with the contents of MAC Address55 high and low registers.
56158  * Each bit controls the masking of the bytes. You can filter a group of addresses
56159  * (known as group address filtering) by masking one or more bytes of the address.
56160  *
56161  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56162  *
56163  * Field Enumeration Values:
56164  *
56165  * Enum | Value | Description
56166  * :----------------------------------------------|:------|:------------------------------------
56167  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56168  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56169  *
56170  * Field Access Macros:
56171  *
56172  */
56173 /*
56174  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4
56175  *
56176  * Byte is unmasked (i.e. is compared)
56177  */
56178 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED 0x0
56179 /*
56180  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4
56181  *
56182  * Byte is masked (i.e. not compared)
56183  */
56184 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED 0x1
56185 
56186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
56187 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_LSB 28
56188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
56189 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_MSB 28
56190 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
56191 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_WIDTH 1
56192 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */
56193 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET_MSK 0x10000000
56194 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */
56195 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_CLR_MSK 0xefffffff
56196 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
56197 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_RESET 0x0
56198 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 field value from a register. */
56199 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
56200 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value suitable for setting the register. */
56201 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
56202 
56203 /*
56204  * Field : Mask Byte Control - mbc_5
56205  *
56206  * This array of bits are mask control bits for comparison of each of the MAC
56207  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56208  * received DA or SA with the contents of MAC Address55 high and low registers.
56209  * Each bit controls the masking of the bytes. You can filter a group of addresses
56210  * (known as group address filtering) by masking one or more bytes of the address.
56211  *
56212  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56213  *
56214  * Field Enumeration Values:
56215  *
56216  * Enum | Value | Description
56217  * :----------------------------------------------|:------|:------------------------------------
56218  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56219  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56220  *
56221  * Field Access Macros:
56222  *
56223  */
56224 /*
56225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5
56226  *
56227  * Byte is unmasked (i.e. is compared)
56228  */
56229 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED 0x0
56230 /*
56231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5
56232  *
56233  * Byte is masked (i.e. not compared)
56234  */
56235 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED 0x1
56236 
56237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
56238 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_LSB 29
56239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
56240 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_MSB 29
56241 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
56242 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_WIDTH 1
56243 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */
56244 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET_MSK 0x20000000
56245 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */
56246 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_CLR_MSK 0xdfffffff
56247 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
56248 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_RESET 0x0
56249 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 field value from a register. */
56250 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
56251 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value suitable for setting the register. */
56252 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
56253 
56254 /*
56255  * Field : Source Address - sa
56256  *
56257  * When this bit is enabled, the MAC Address55[47:0] is used to compare with the SA
56258  * fields of the received frame. When this bit is disabled, the MAC Address55[47:0]
56259  * is used to compare with the DA fields of the received frame.
56260  *
56261  * Field Enumeration Values:
56262  *
56263  * Enum | Value | Description
56264  * :----------------------------------------|:------|:-----------------------------
56265  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
56266  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END | 0x1 | MAC address compare enabled
56267  *
56268  * Field Access Macros:
56269  *
56270  */
56271 /*
56272  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA
56273  *
56274  * MAC address compare disabled
56275  */
56276 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD 0x0
56277 /*
56278  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA
56279  *
56280  * MAC address compare enabled
56281  */
56282 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END 0x1
56283 
56284 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
56285 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_LSB 30
56286 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
56287 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_MSB 30
56288 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
56289 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_WIDTH 1
56290 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */
56291 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET_MSK 0x40000000
56292 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */
56293 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_CLR_MSK 0xbfffffff
56294 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
56295 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_RESET 0x0
56296 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA field value from a register. */
56297 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
56298 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value suitable for setting the register. */
56299 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
56300 
56301 /*
56302  * Field : Address Enable - ae
56303  *
56304  * When this bit is enabled, the address filter block uses the 56th MAC address for
56305  * perfect filtering. When this bit is disabled, the address filter block ignores
56306  * the address for filtering.
56307  *
56308  * Field Enumeration Values:
56309  *
56310  * Enum | Value | Description
56311  * :----------------------------------------|:------|:--------------------------------------
56312  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
56313  * ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
56314  *
56315  * Field Access Macros:
56316  *
56317  */
56318 /*
56319  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
56320  *
56321  * Second MAC address filtering disabled
56322  */
56323 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD 0x0
56324 /*
56325  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
56326  *
56327  * Second MAC address filtering enabled
56328  */
56329 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END 0x1
56330 
56331 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
56332 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_LSB 31
56333 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
56334 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_MSB 31
56335 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
56336 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_WIDTH 1
56337 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
56338 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET_MSK 0x80000000
56339 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
56340 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_CLR_MSK 0x7fffffff
56341 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
56342 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_RESET 0x0
56343 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE field value from a register. */
56344 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56345 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value suitable for setting the register. */
56346 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56347 
56348 #ifndef __ASSEMBLY__
56349 /*
56350  * WARNING: The C register and register group struct declarations are provided for
56351  * convenience and illustrative purposes. They should, however, be used with
56352  * caution as the C language standard provides no guarantees about the alignment or
56353  * atomicity of device memory accesses. The recommended practice for writing
56354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56355  * alt_write_word() functions.
56356  *
56357  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH.
56358  */
56359 struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s
56360 {
56361  uint32_t addrhi : 16; /* MAC Address55 [47:32] */
56362  uint32_t : 8; /* *UNDEFINED* */
56363  uint32_t mbc_0 : 1; /* Mask Byte Control */
56364  uint32_t mbc_1 : 1; /* Mask Byte Control */
56365  uint32_t mbc_2 : 1; /* Mask Byte Control */
56366  uint32_t mbc_3 : 1; /* Mask Byte Control */
56367  uint32_t mbc_4 : 1; /* Mask Byte Control */
56368  uint32_t mbc_5 : 1; /* Mask Byte Control */
56369  uint32_t sa : 1; /* Source Address */
56370  uint32_t ae : 1; /* Address Enable */
56371 };
56372 
56373 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH. */
56374 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t;
56375 #endif /* __ASSEMBLY__ */
56376 
56377 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register from the beginning of the component. */
56378 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST 0x938
56379 /* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register. */
56380 #define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST))
56381 
56382 /*
56383  * Register : Register 591 (MAC Address55 Low Register) - MAC_Address55_Low
56384  *
56385  * The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC
56386  * address of the station.
56387  *
56388  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
56389  * format.
56390  *
56391  * Register Layout
56392  *
56393  * Bits | Access | Reset | Description
56394  * :-------|:-------|:-----------|:---------------------
56395  * [31:0] | RW | 0xffffffff | MAC Address55 [31:0]
56396  *
56397  */
56398 /*
56399  * Field : MAC Address55 [31:0] - addrlo
56400  *
56401  * This field contains the lower 32 bits of the 56th 6-byte MAC address. The
56402  * content of this field is undefined until loaded by software after the
56403  * initialization process.
56404  *
56405  * Field Access Macros:
56406  *
56407  */
56408 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
56409 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_LSB 0
56410 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
56411 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_MSB 31
56412 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
56413 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_WIDTH 32
56414 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
56415 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET_MSK 0xffffffff
56416 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
56417 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_CLR_MSK 0x00000000
56418 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
56419 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_RESET 0xffffffff
56420 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO field value from a register. */
56421 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56422 /* Produces a ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value suitable for setting the register. */
56423 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56424 
56425 #ifndef __ASSEMBLY__
56426 /*
56427  * WARNING: The C register and register group struct declarations are provided for
56428  * convenience and illustrative purposes. They should, however, be used with
56429  * caution as the C language standard provides no guarantees about the alignment or
56430  * atomicity of device memory accesses. The recommended practice for writing
56431  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56432  * alt_write_word() functions.
56433  *
56434  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW.
56435  */
56436 struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s
56437 {
56438  uint32_t addrlo : 32; /* MAC Address55 [31:0] */
56439 };
56440 
56441 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW. */
56442 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s ALT_EMAC_GMAC_MAC_ADDR55_LOW_t;
56443 #endif /* __ASSEMBLY__ */
56444 
56445 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register from the beginning of the component. */
56446 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST 0x93c
56447 /* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register. */
56448 #define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST))
56449 
56450 /*
56451  * Register : Register 592 (MAC Address56 High Register) - MAC_Address56_High
56452  *
56453  * The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC
56454  * address of the station. Because the MAC address registers are configured to be
56455  * double-synchronized to the (G)MII clock domains, the synchronization is
56456  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
56457  * endian mode) of the MAC Address56 Low Register are written. For proper
56458  * synchronization updates, the consecutive writes to this Address Low Register
56459  * should be performed after at least four clock cycles in the destination clock
56460  * domain.
56461  *
56462  * Note that all MAC Address High registers (except MAC Address0 High) have the
56463  * same format.
56464  *
56465  * Register Layout
56466  *
56467  * Bits | Access | Reset | Description
56468  * :--------|:-------|:-------|:----------------------
56469  * [15:0] | RW | 0xffff | MAC Address56 [47:32]
56470  * [23:16] | ??? | 0x0 | *UNDEFINED*
56471  * [24] | RW | 0x0 | Mask Byte Control
56472  * [25] | RW | 0x0 | Mask Byte Control
56473  * [26] | RW | 0x0 | Mask Byte Control
56474  * [27] | RW | 0x0 | Mask Byte Control
56475  * [28] | RW | 0x0 | Mask Byte Control
56476  * [29] | RW | 0x0 | Mask Byte Control
56477  * [30] | RW | 0x0 | Source Address
56478  * [31] | RW | 0x0 | Address Enable
56479  *
56480  */
56481 /*
56482  * Field : MAC Address56 [47:32] - addrhi
56483  *
56484  * This field contains the upper 16 bits (47:32) of the 57th 6-byte MAC address.
56485  *
56486  * Field Access Macros:
56487  *
56488  */
56489 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
56490 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_LSB 0
56491 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
56492 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_MSB 15
56493 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
56494 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_WIDTH 16
56495 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
56496 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET_MSK 0x0000ffff
56497 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
56498 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_CLR_MSK 0xffff0000
56499 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
56500 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_RESET 0xffff
56501 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI field value from a register. */
56502 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
56503 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value suitable for setting the register. */
56504 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
56505 
56506 /*
56507  * Field : Mask Byte Control - mbc_0
56508  *
56509  * This array of bits are mask control bits for comparison of each of the MAC
56510  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56511  * received DA or SA with the contents of MAC Address56 high and low registers.
56512  * Each bit controls the masking of the bytes. You can filter a group of addresses
56513  * (known as group address filtering) by masking one or more bytes of the address.
56514  *
56515  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56516  *
56517  * Field Enumeration Values:
56518  *
56519  * Enum | Value | Description
56520  * :----------------------------------------------|:------|:------------------------------------
56521  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56522  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56523  *
56524  * Field Access Macros:
56525  *
56526  */
56527 /*
56528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0
56529  *
56530  * Byte is unmasked (i.e. is compared)
56531  */
56532 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED 0x0
56533 /*
56534  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0
56535  *
56536  * Byte is masked (i.e. not compared)
56537  */
56538 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED 0x1
56539 
56540 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
56541 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_LSB 24
56542 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
56543 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_MSB 24
56544 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
56545 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_WIDTH 1
56546 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */
56547 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET_MSK 0x01000000
56548 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */
56549 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_CLR_MSK 0xfeffffff
56550 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
56551 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_RESET 0x0
56552 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 field value from a register. */
56553 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
56554 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value suitable for setting the register. */
56555 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
56556 
56557 /*
56558  * Field : Mask Byte Control - mbc_1
56559  *
56560  * This array of bits are mask control bits for comparison of each of the MAC
56561  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56562  * received DA or SA with the contents of MAC Address56 high and low registers.
56563  * Each bit controls the masking of the bytes. You can filter a group of addresses
56564  * (known as group address filtering) by masking one or more bytes of the address.
56565  *
56566  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56567  *
56568  * Field Enumeration Values:
56569  *
56570  * Enum | Value | Description
56571  * :----------------------------------------------|:------|:------------------------------------
56572  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56573  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56574  *
56575  * Field Access Macros:
56576  *
56577  */
56578 /*
56579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1
56580  *
56581  * Byte is unmasked (i.e. is compared)
56582  */
56583 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED 0x0
56584 /*
56585  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1
56586  *
56587  * Byte is masked (i.e. not compared)
56588  */
56589 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED 0x1
56590 
56591 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
56592 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_LSB 25
56593 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
56594 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_MSB 25
56595 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
56596 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_WIDTH 1
56597 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */
56598 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET_MSK 0x02000000
56599 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */
56600 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_CLR_MSK 0xfdffffff
56601 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
56602 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_RESET 0x0
56603 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 field value from a register. */
56604 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
56605 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value suitable for setting the register. */
56606 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
56607 
56608 /*
56609  * Field : Mask Byte Control - mbc_2
56610  *
56611  * This array of bits are mask control bits for comparison of each of the MAC
56612  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56613  * received DA or SA with the contents of MAC Address56 high and low registers.
56614  * Each bit controls the masking of the bytes. You can filter a group of addresses
56615  * (known as group address filtering) by masking one or more bytes of the address.
56616  *
56617  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56618  *
56619  * Field Enumeration Values:
56620  *
56621  * Enum | Value | Description
56622  * :----------------------------------------------|:------|:------------------------------------
56623  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56624  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56625  *
56626  * Field Access Macros:
56627  *
56628  */
56629 /*
56630  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2
56631  *
56632  * Byte is unmasked (i.e. is compared)
56633  */
56634 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED 0x0
56635 /*
56636  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2
56637  *
56638  * Byte is masked (i.e. not compared)
56639  */
56640 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED 0x1
56641 
56642 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
56643 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_LSB 26
56644 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
56645 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_MSB 26
56646 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
56647 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_WIDTH 1
56648 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */
56649 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET_MSK 0x04000000
56650 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */
56651 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_CLR_MSK 0xfbffffff
56652 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
56653 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_RESET 0x0
56654 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 field value from a register. */
56655 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
56656 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value suitable for setting the register. */
56657 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
56658 
56659 /*
56660  * Field : Mask Byte Control - mbc_3
56661  *
56662  * This array of bits are mask control bits for comparison of each of the MAC
56663  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56664  * received DA or SA with the contents of MAC Address56 high and low registers.
56665  * Each bit controls the masking of the bytes. You can filter a group of addresses
56666  * (known as group address filtering) by masking one or more bytes of the address.
56667  *
56668  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56669  *
56670  * Field Enumeration Values:
56671  *
56672  * Enum | Value | Description
56673  * :----------------------------------------------|:------|:------------------------------------
56674  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56675  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56676  *
56677  * Field Access Macros:
56678  *
56679  */
56680 /*
56681  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3
56682  *
56683  * Byte is unmasked (i.e. is compared)
56684  */
56685 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED 0x0
56686 /*
56687  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3
56688  *
56689  * Byte is masked (i.e. not compared)
56690  */
56691 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED 0x1
56692 
56693 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
56694 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_LSB 27
56695 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
56696 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_MSB 27
56697 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
56698 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_WIDTH 1
56699 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */
56700 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET_MSK 0x08000000
56701 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */
56702 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_CLR_MSK 0xf7ffffff
56703 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
56704 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_RESET 0x0
56705 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 field value from a register. */
56706 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
56707 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value suitable for setting the register. */
56708 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
56709 
56710 /*
56711  * Field : Mask Byte Control - mbc_4
56712  *
56713  * This array of bits are mask control bits for comparison of each of the MAC
56714  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56715  * received DA or SA with the contents of MAC Address56 high and low registers.
56716  * Each bit controls the masking of the bytes. You can filter a group of addresses
56717  * (known as group address filtering) by masking one or more bytes of the address.
56718  *
56719  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56720  *
56721  * Field Enumeration Values:
56722  *
56723  * Enum | Value | Description
56724  * :----------------------------------------------|:------|:------------------------------------
56725  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56726  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56727  *
56728  * Field Access Macros:
56729  *
56730  */
56731 /*
56732  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4
56733  *
56734  * Byte is unmasked (i.e. is compared)
56735  */
56736 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED 0x0
56737 /*
56738  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4
56739  *
56740  * Byte is masked (i.e. not compared)
56741  */
56742 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED 0x1
56743 
56744 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
56745 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_LSB 28
56746 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
56747 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_MSB 28
56748 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
56749 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_WIDTH 1
56750 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */
56751 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET_MSK 0x10000000
56752 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */
56753 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_CLR_MSK 0xefffffff
56754 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
56755 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_RESET 0x0
56756 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 field value from a register. */
56757 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
56758 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value suitable for setting the register. */
56759 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
56760 
56761 /*
56762  * Field : Mask Byte Control - mbc_5
56763  *
56764  * This array of bits are mask control bits for comparison of each of the MAC
56765  * Address bytes. When masked, the MAC does not compare the corresponding byte of
56766  * received DA or SA with the contents of MAC Address56 high and low registers.
56767  * Each bit controls the masking of the bytes. You can filter a group of addresses
56768  * (known as group address filtering) by masking one or more bytes of the address.
56769  *
56770  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
56771  *
56772  * Field Enumeration Values:
56773  *
56774  * Enum | Value | Description
56775  * :----------------------------------------------|:------|:------------------------------------
56776  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
56777  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
56778  *
56779  * Field Access Macros:
56780  *
56781  */
56782 /*
56783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5
56784  *
56785  * Byte is unmasked (i.e. is compared)
56786  */
56787 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED 0x0
56788 /*
56789  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5
56790  *
56791  * Byte is masked (i.e. not compared)
56792  */
56793 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED 0x1
56794 
56795 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
56796 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_LSB 29
56797 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
56798 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_MSB 29
56799 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
56800 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_WIDTH 1
56801 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */
56802 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET_MSK 0x20000000
56803 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */
56804 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_CLR_MSK 0xdfffffff
56805 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
56806 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_RESET 0x0
56807 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 field value from a register. */
56808 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
56809 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value suitable for setting the register. */
56810 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
56811 
56812 /*
56813  * Field : Source Address - sa
56814  *
56815  * When this bit is enabled, the MAC Address56[47:0] is used to compare with the SA
56816  * fields of the received frame. When this bit is disabled, the MAC Address56[47:0]
56817  * is used to compare with the DA fields of the received frame.
56818  *
56819  * Field Enumeration Values:
56820  *
56821  * Enum | Value | Description
56822  * :----------------------------------------|:------|:-----------------------------
56823  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
56824  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END | 0x1 | MAC address compare enabled
56825  *
56826  * Field Access Macros:
56827  *
56828  */
56829 /*
56830  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA
56831  *
56832  * MAC address compare disabled
56833  */
56834 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD 0x0
56835 /*
56836  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA
56837  *
56838  * MAC address compare enabled
56839  */
56840 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END 0x1
56841 
56842 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
56843 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_LSB 30
56844 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
56845 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_MSB 30
56846 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
56847 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_WIDTH 1
56848 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */
56849 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET_MSK 0x40000000
56850 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */
56851 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_CLR_MSK 0xbfffffff
56852 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
56853 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_RESET 0x0
56854 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA field value from a register. */
56855 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
56856 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value suitable for setting the register. */
56857 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
56858 
56859 /*
56860  * Field : Address Enable - ae
56861  *
56862  * When this bit is enabled, the address filter block uses the 57th MAC address for
56863  * perfect filtering. When this bit is disabled, the address filter block ignores
56864  * the address for filtering.
56865  *
56866  * Field Enumeration Values:
56867  *
56868  * Enum | Value | Description
56869  * :----------------------------------------|:------|:--------------------------------------
56870  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
56871  * ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
56872  *
56873  * Field Access Macros:
56874  *
56875  */
56876 /*
56877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
56878  *
56879  * Second MAC address filtering disabled
56880  */
56881 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD 0x0
56882 /*
56883  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
56884  *
56885  * Second MAC address filtering enabled
56886  */
56887 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END 0x1
56888 
56889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
56890 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_LSB 31
56891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
56892 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_MSB 31
56893 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
56894 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_WIDTH 1
56895 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
56896 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET_MSK 0x80000000
56897 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
56898 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_CLR_MSK 0x7fffffff
56899 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
56900 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_RESET 0x0
56901 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE field value from a register. */
56902 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
56903 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value suitable for setting the register. */
56904 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
56905 
56906 #ifndef __ASSEMBLY__
56907 /*
56908  * WARNING: The C register and register group struct declarations are provided for
56909  * convenience and illustrative purposes. They should, however, be used with
56910  * caution as the C language standard provides no guarantees about the alignment or
56911  * atomicity of device memory accesses. The recommended practice for writing
56912  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56913  * alt_write_word() functions.
56914  *
56915  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH.
56916  */
56917 struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s
56918 {
56919  uint32_t addrhi : 16; /* MAC Address56 [47:32] */
56920  uint32_t : 8; /* *UNDEFINED* */
56921  uint32_t mbc_0 : 1; /* Mask Byte Control */
56922  uint32_t mbc_1 : 1; /* Mask Byte Control */
56923  uint32_t mbc_2 : 1; /* Mask Byte Control */
56924  uint32_t mbc_3 : 1; /* Mask Byte Control */
56925  uint32_t mbc_4 : 1; /* Mask Byte Control */
56926  uint32_t mbc_5 : 1; /* Mask Byte Control */
56927  uint32_t sa : 1; /* Source Address */
56928  uint32_t ae : 1; /* Address Enable */
56929 };
56930 
56931 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH. */
56932 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t;
56933 #endif /* __ASSEMBLY__ */
56934 
56935 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register from the beginning of the component. */
56936 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST 0x940
56937 /* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register. */
56938 #define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST))
56939 
56940 /*
56941  * Register : Register 593 (MAC Address56 Low Register) - MAC_Address56_Low
56942  *
56943  * The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC
56944  * address of the station.
56945  *
56946  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
56947  * format.
56948  *
56949  * Register Layout
56950  *
56951  * Bits | Access | Reset | Description
56952  * :-------|:-------|:-----------|:---------------------
56953  * [31:0] | RW | 0xffffffff | MAC Address56 [31:0]
56954  *
56955  */
56956 /*
56957  * Field : MAC Address56 [31:0] - addrlo
56958  *
56959  * This field contains the lower 32 bits of the 57th 6-byte MAC address. The
56960  * content of this field is undefined until loaded by software after the
56961  * initialization process.
56962  *
56963  * Field Access Macros:
56964  *
56965  */
56966 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
56967 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_LSB 0
56968 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
56969 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_MSB 31
56970 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
56971 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_WIDTH 32
56972 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
56973 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET_MSK 0xffffffff
56974 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
56975 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_CLR_MSK 0x00000000
56976 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
56977 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_RESET 0xffffffff
56978 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO field value from a register. */
56979 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
56980 /* Produces a ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value suitable for setting the register. */
56981 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
56982 
56983 #ifndef __ASSEMBLY__
56984 /*
56985  * WARNING: The C register and register group struct declarations are provided for
56986  * convenience and illustrative purposes. They should, however, be used with
56987  * caution as the C language standard provides no guarantees about the alignment or
56988  * atomicity of device memory accesses. The recommended practice for writing
56989  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
56990  * alt_write_word() functions.
56991  *
56992  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW.
56993  */
56994 struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s
56995 {
56996  uint32_t addrlo : 32; /* MAC Address56 [31:0] */
56997 };
56998 
56999 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW. */
57000 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s ALT_EMAC_GMAC_MAC_ADDR56_LOW_t;
57001 #endif /* __ASSEMBLY__ */
57002 
57003 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register from the beginning of the component. */
57004 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST 0x944
57005 /* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register. */
57006 #define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST))
57007 
57008 /*
57009  * Register : Register 594 (MAC Address57 High Register) - MAC_Address57_High
57010  *
57011  * The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC
57012  * address of the station. Because the MAC address registers are configured to be
57013  * double-synchronized to the (G)MII clock domains, the synchronization is
57014  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
57015  * endian mode) of the MAC Address57 Low Register are written. For proper
57016  * synchronization updates, the consecutive writes to this Address Low Register
57017  * should be performed after at least four clock cycles in the destination clock
57018  * domain.
57019  *
57020  * Note that all MAC Address High registers (except MAC Address0 High) have the
57021  * same format.
57022  *
57023  * Register Layout
57024  *
57025  * Bits | Access | Reset | Description
57026  * :--------|:-------|:-------|:----------------------
57027  * [15:0] | RW | 0xffff | MAC Address57 [47:32]
57028  * [23:16] | ??? | 0x0 | *UNDEFINED*
57029  * [24] | RW | 0x0 | Mask Byte Control
57030  * [25] | RW | 0x0 | Mask Byte Control
57031  * [26] | RW | 0x0 | Mask Byte Control
57032  * [27] | RW | 0x0 | Mask Byte Control
57033  * [28] | RW | 0x0 | Mask Byte Control
57034  * [29] | RW | 0x0 | Mask Byte Control
57035  * [30] | RW | 0x0 | Source Address
57036  * [31] | RW | 0x0 | Address Enable
57037  *
57038  */
57039 /*
57040  * Field : MAC Address57 [47:32] - addrhi
57041  *
57042  * This field contains the upper 16 bits (47:32) of the 58th 6-byte MAC address.
57043  *
57044  * Field Access Macros:
57045  *
57046  */
57047 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
57048 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_LSB 0
57049 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
57050 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_MSB 15
57051 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
57052 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_WIDTH 16
57053 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
57054 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET_MSK 0x0000ffff
57055 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
57056 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_CLR_MSK 0xffff0000
57057 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
57058 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_RESET 0xffff
57059 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI field value from a register. */
57060 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57061 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value suitable for setting the register. */
57062 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57063 
57064 /*
57065  * Field : Mask Byte Control - mbc_0
57066  *
57067  * This array of bits are mask control bits for comparison of each of the MAC
57068  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57069  * received DA or SA with the contents of MAC Address57 high and low registers.
57070  * Each bit controls the masking of the bytes. You can filter a group of addresses
57071  * (known as group address filtering) by masking one or more bytes of the address.
57072  *
57073  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57074  *
57075  * Field Enumeration Values:
57076  *
57077  * Enum | Value | Description
57078  * :----------------------------------------------|:------|:------------------------------------
57079  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57080  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57081  *
57082  * Field Access Macros:
57083  *
57084  */
57085 /*
57086  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0
57087  *
57088  * Byte is unmasked (i.e. is compared)
57089  */
57090 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED 0x0
57091 /*
57092  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0
57093  *
57094  * Byte is masked (i.e. not compared)
57095  */
57096 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED 0x1
57097 
57098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
57099 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_LSB 24
57100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
57101 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_MSB 24
57102 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
57103 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_WIDTH 1
57104 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */
57105 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET_MSK 0x01000000
57106 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */
57107 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_CLR_MSK 0xfeffffff
57108 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
57109 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_RESET 0x0
57110 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 field value from a register. */
57111 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
57112 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value suitable for setting the register. */
57113 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
57114 
57115 /*
57116  * Field : Mask Byte Control - mbc_1
57117  *
57118  * This array of bits are mask control bits for comparison of each of the MAC
57119  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57120  * received DA or SA with the contents of MAC Address57 high and low registers.
57121  * Each bit controls the masking of the bytes. You can filter a group of addresses
57122  * (known as group address filtering) by masking one or more bytes of the address.
57123  *
57124  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57125  *
57126  * Field Enumeration Values:
57127  *
57128  * Enum | Value | Description
57129  * :----------------------------------------------|:------|:------------------------------------
57130  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57131  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57132  *
57133  * Field Access Macros:
57134  *
57135  */
57136 /*
57137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1
57138  *
57139  * Byte is unmasked (i.e. is compared)
57140  */
57141 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED 0x0
57142 /*
57143  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1
57144  *
57145  * Byte is masked (i.e. not compared)
57146  */
57147 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED 0x1
57148 
57149 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
57150 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_LSB 25
57151 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
57152 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_MSB 25
57153 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
57154 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_WIDTH 1
57155 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */
57156 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET_MSK 0x02000000
57157 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */
57158 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_CLR_MSK 0xfdffffff
57159 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
57160 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_RESET 0x0
57161 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 field value from a register. */
57162 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
57163 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value suitable for setting the register. */
57164 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
57165 
57166 /*
57167  * Field : Mask Byte Control - mbc_2
57168  *
57169  * This array of bits are mask control bits for comparison of each of the MAC
57170  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57171  * received DA or SA with the contents of MAC Address57 high and low registers.
57172  * Each bit controls the masking of the bytes. You can filter a group of addresses
57173  * (known as group address filtering) by masking one or more bytes of the address.
57174  *
57175  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57176  *
57177  * Field Enumeration Values:
57178  *
57179  * Enum | Value | Description
57180  * :----------------------------------------------|:------|:------------------------------------
57181  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57182  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57183  *
57184  * Field Access Macros:
57185  *
57186  */
57187 /*
57188  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2
57189  *
57190  * Byte is unmasked (i.e. is compared)
57191  */
57192 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED 0x0
57193 /*
57194  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2
57195  *
57196  * Byte is masked (i.e. not compared)
57197  */
57198 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED 0x1
57199 
57200 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
57201 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_LSB 26
57202 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
57203 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_MSB 26
57204 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
57205 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_WIDTH 1
57206 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */
57207 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET_MSK 0x04000000
57208 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */
57209 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_CLR_MSK 0xfbffffff
57210 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
57211 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_RESET 0x0
57212 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 field value from a register. */
57213 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
57214 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value suitable for setting the register. */
57215 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
57216 
57217 /*
57218  * Field : Mask Byte Control - mbc_3
57219  *
57220  * This array of bits are mask control bits for comparison of each of the MAC
57221  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57222  * received DA or SA with the contents of MAC Address57 high and low registers.
57223  * Each bit controls the masking of the bytes. You can filter a group of addresses
57224  * (known as group address filtering) by masking one or more bytes of the address.
57225  *
57226  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57227  *
57228  * Field Enumeration Values:
57229  *
57230  * Enum | Value | Description
57231  * :----------------------------------------------|:------|:------------------------------------
57232  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57233  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57234  *
57235  * Field Access Macros:
57236  *
57237  */
57238 /*
57239  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3
57240  *
57241  * Byte is unmasked (i.e. is compared)
57242  */
57243 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED 0x0
57244 /*
57245  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3
57246  *
57247  * Byte is masked (i.e. not compared)
57248  */
57249 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED 0x1
57250 
57251 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
57252 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_LSB 27
57253 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
57254 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_MSB 27
57255 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
57256 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_WIDTH 1
57257 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */
57258 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET_MSK 0x08000000
57259 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */
57260 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_CLR_MSK 0xf7ffffff
57261 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
57262 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_RESET 0x0
57263 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 field value from a register. */
57264 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
57265 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value suitable for setting the register. */
57266 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
57267 
57268 /*
57269  * Field : Mask Byte Control - mbc_4
57270  *
57271  * This array of bits are mask control bits for comparison of each of the MAC
57272  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57273  * received DA or SA with the contents of MAC Address57 high and low registers.
57274  * Each bit controls the masking of the bytes. You can filter a group of addresses
57275  * (known as group address filtering) by masking one or more bytes of the address.
57276  *
57277  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57278  *
57279  * Field Enumeration Values:
57280  *
57281  * Enum | Value | Description
57282  * :----------------------------------------------|:------|:------------------------------------
57283  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57284  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57285  *
57286  * Field Access Macros:
57287  *
57288  */
57289 /*
57290  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4
57291  *
57292  * Byte is unmasked (i.e. is compared)
57293  */
57294 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED 0x0
57295 /*
57296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4
57297  *
57298  * Byte is masked (i.e. not compared)
57299  */
57300 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED 0x1
57301 
57302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
57303 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_LSB 28
57304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
57305 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_MSB 28
57306 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
57307 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_WIDTH 1
57308 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */
57309 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET_MSK 0x10000000
57310 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */
57311 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_CLR_MSK 0xefffffff
57312 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
57313 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_RESET 0x0
57314 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 field value from a register. */
57315 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
57316 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value suitable for setting the register. */
57317 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
57318 
57319 /*
57320  * Field : Mask Byte Control - mbc_5
57321  *
57322  * This array of bits are mask control bits for comparison of each of the MAC
57323  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57324  * received DA or SA with the contents of MAC Address57 high and low registers.
57325  * Each bit controls the masking of the bytes. You can filter a group of addresses
57326  * (known as group address filtering) by masking one or more bytes of the address.
57327  *
57328  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57329  *
57330  * Field Enumeration Values:
57331  *
57332  * Enum | Value | Description
57333  * :----------------------------------------------|:------|:------------------------------------
57334  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57335  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57336  *
57337  * Field Access Macros:
57338  *
57339  */
57340 /*
57341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5
57342  *
57343  * Byte is unmasked (i.e. is compared)
57344  */
57345 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED 0x0
57346 /*
57347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5
57348  *
57349  * Byte is masked (i.e. not compared)
57350  */
57351 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED 0x1
57352 
57353 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
57354 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_LSB 29
57355 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
57356 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_MSB 29
57357 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
57358 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_WIDTH 1
57359 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */
57360 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET_MSK 0x20000000
57361 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */
57362 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_CLR_MSK 0xdfffffff
57363 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
57364 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_RESET 0x0
57365 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 field value from a register. */
57366 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
57367 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value suitable for setting the register. */
57368 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
57369 
57370 /*
57371  * Field : Source Address - sa
57372  *
57373  * When this bit is enabled, the MAC Address57[47:0] is used to compare with the SA
57374  * fields of the received frame. When this bit is disabled, the MAC Address57[47:0]
57375  * is used to compare with the DA fields of the received frame.
57376  *
57377  * Field Enumeration Values:
57378  *
57379  * Enum | Value | Description
57380  * :----------------------------------------|:------|:-----------------------------
57381  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
57382  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END | 0x1 | MAC address compare enabled
57383  *
57384  * Field Access Macros:
57385  *
57386  */
57387 /*
57388  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA
57389  *
57390  * MAC address compare disabled
57391  */
57392 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD 0x0
57393 /*
57394  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA
57395  *
57396  * MAC address compare enabled
57397  */
57398 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END 0x1
57399 
57400 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
57401 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_LSB 30
57402 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
57403 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_MSB 30
57404 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
57405 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_WIDTH 1
57406 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */
57407 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET_MSK 0x40000000
57408 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */
57409 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_CLR_MSK 0xbfffffff
57410 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
57411 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_RESET 0x0
57412 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA field value from a register. */
57413 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
57414 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value suitable for setting the register. */
57415 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
57416 
57417 /*
57418  * Field : Address Enable - ae
57419  *
57420  * When this bit is enabled, the address filter block uses the 58th MAC address for
57421  * perfect filtering. When this bit is disabled, the address filter block ignores
57422  * the address for filtering.
57423  *
57424  * Field Enumeration Values:
57425  *
57426  * Enum | Value | Description
57427  * :----------------------------------------|:------|:--------------------------------------
57428  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
57429  * ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
57430  *
57431  * Field Access Macros:
57432  *
57433  */
57434 /*
57435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
57436  *
57437  * Second MAC address filtering disabled
57438  */
57439 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD 0x0
57440 /*
57441  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
57442  *
57443  * Second MAC address filtering enabled
57444  */
57445 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END 0x1
57446 
57447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
57448 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_LSB 31
57449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
57450 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_MSB 31
57451 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
57452 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_WIDTH 1
57453 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
57454 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET_MSK 0x80000000
57455 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
57456 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_CLR_MSK 0x7fffffff
57457 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
57458 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_RESET 0x0
57459 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE field value from a register. */
57460 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
57461 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value suitable for setting the register. */
57462 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
57463 
57464 #ifndef __ASSEMBLY__
57465 /*
57466  * WARNING: The C register and register group struct declarations are provided for
57467  * convenience and illustrative purposes. They should, however, be used with
57468  * caution as the C language standard provides no guarantees about the alignment or
57469  * atomicity of device memory accesses. The recommended practice for writing
57470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57471  * alt_write_word() functions.
57472  *
57473  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH.
57474  */
57475 struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s
57476 {
57477  uint32_t addrhi : 16; /* MAC Address57 [47:32] */
57478  uint32_t : 8; /* *UNDEFINED* */
57479  uint32_t mbc_0 : 1; /* Mask Byte Control */
57480  uint32_t mbc_1 : 1; /* Mask Byte Control */
57481  uint32_t mbc_2 : 1; /* Mask Byte Control */
57482  uint32_t mbc_3 : 1; /* Mask Byte Control */
57483  uint32_t mbc_4 : 1; /* Mask Byte Control */
57484  uint32_t mbc_5 : 1; /* Mask Byte Control */
57485  uint32_t sa : 1; /* Source Address */
57486  uint32_t ae : 1; /* Address Enable */
57487 };
57488 
57489 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH. */
57490 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t;
57491 #endif /* __ASSEMBLY__ */
57492 
57493 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register from the beginning of the component. */
57494 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST 0x948
57495 /* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register. */
57496 #define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST))
57497 
57498 /*
57499  * Register : Register 595 (MAC Address57 Low Register) - MAC_Address57_Low
57500  *
57501  * The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC
57502  * address of the station.
57503  *
57504  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
57505  * format.
57506  *
57507  * Register Layout
57508  *
57509  * Bits | Access | Reset | Description
57510  * :-------|:-------|:-----------|:---------------------
57511  * [31:0] | RW | 0xffffffff | MAC Address57 [31:0]
57512  *
57513  */
57514 /*
57515  * Field : MAC Address57 [31:0] - addrlo
57516  *
57517  * This field contains the lower 32 bits of the 58th 6-byte MAC address. The
57518  * content of this field is undefined until loaded by software after the
57519  * initialization process.
57520  *
57521  * Field Access Macros:
57522  *
57523  */
57524 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
57525 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_LSB 0
57526 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
57527 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_MSB 31
57528 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
57529 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_WIDTH 32
57530 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
57531 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET_MSK 0xffffffff
57532 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
57533 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_CLR_MSK 0x00000000
57534 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
57535 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_RESET 0xffffffff
57536 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO field value from a register. */
57537 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
57538 /* Produces a ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value suitable for setting the register. */
57539 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
57540 
57541 #ifndef __ASSEMBLY__
57542 /*
57543  * WARNING: The C register and register group struct declarations are provided for
57544  * convenience and illustrative purposes. They should, however, be used with
57545  * caution as the C language standard provides no guarantees about the alignment or
57546  * atomicity of device memory accesses. The recommended practice for writing
57547  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
57548  * alt_write_word() functions.
57549  *
57550  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW.
57551  */
57552 struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s
57553 {
57554  uint32_t addrlo : 32; /* MAC Address57 [31:0] */
57555 };
57556 
57557 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW. */
57558 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s ALT_EMAC_GMAC_MAC_ADDR57_LOW_t;
57559 #endif /* __ASSEMBLY__ */
57560 
57561 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register from the beginning of the component. */
57562 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST 0x94c
57563 /* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register. */
57564 #define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST))
57565 
57566 /*
57567  * Register : Register 596 (MAC Address58 High Register) - MAC_Address58_High
57568  *
57569  * The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC
57570  * address of the station. Because the MAC address registers are configured to be
57571  * double-synchronized to the (G)MII clock domains, the synchronization is
57572  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
57573  * endian mode) of the MAC Address58 Low Register are written. For proper
57574  * synchronization updates, the consecutive writes to this Address Low Register
57575  * should be performed after at least four clock cycles in the destination clock
57576  * domain.
57577  *
57578  * Note that all MAC Address High registers (except MAC Address0 High) have the
57579  * same format.
57580  *
57581  * Register Layout
57582  *
57583  * Bits | Access | Reset | Description
57584  * :--------|:-------|:-------|:----------------------
57585  * [15:0] | RW | 0xffff | MAC Address58 [47:32]
57586  * [23:16] | ??? | 0x0 | *UNDEFINED*
57587  * [24] | RW | 0x0 | Mask Byte Control
57588  * [25] | RW | 0x0 | Mask Byte Control
57589  * [26] | RW | 0x0 | Mask Byte Control
57590  * [27] | RW | 0x0 | Mask Byte Control
57591  * [28] | RW | 0x0 | Mask Byte Control
57592  * [29] | RW | 0x0 | Mask Byte Control
57593  * [30] | RW | 0x0 | Source Address
57594  * [31] | RW | 0x0 | Address Enable
57595  *
57596  */
57597 /*
57598  * Field : MAC Address58 [47:32] - addrhi
57599  *
57600  * This field contains the upper 16 bits (47:32) of the 59th 6-byte MAC address.
57601  *
57602  * Field Access Macros:
57603  *
57604  */
57605 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
57606 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_LSB 0
57607 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
57608 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_MSB 15
57609 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
57610 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_WIDTH 16
57611 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
57612 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET_MSK 0x0000ffff
57613 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
57614 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_CLR_MSK 0xffff0000
57615 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
57616 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_RESET 0xffff
57617 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI field value from a register. */
57618 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
57619 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value suitable for setting the register. */
57620 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
57621 
57622 /*
57623  * Field : Mask Byte Control - mbc_0
57624  *
57625  * This array of bits are mask control bits for comparison of each of the MAC
57626  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57627  * received DA or SA with the contents of MAC Address58 high and low registers.
57628  * Each bit controls the masking of the bytes. You can filter a group of addresses
57629  * (known as group address filtering) by masking one or more bytes of the address.
57630  *
57631  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57632  *
57633  * Field Enumeration Values:
57634  *
57635  * Enum | Value | Description
57636  * :----------------------------------------------|:------|:------------------------------------
57637  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57638  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57639  *
57640  * Field Access Macros:
57641  *
57642  */
57643 /*
57644  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0
57645  *
57646  * Byte is unmasked (i.e. is compared)
57647  */
57648 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED 0x0
57649 /*
57650  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0
57651  *
57652  * Byte is masked (i.e. not compared)
57653  */
57654 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED 0x1
57655 
57656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
57657 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_LSB 24
57658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
57659 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_MSB 24
57660 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
57661 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_WIDTH 1
57662 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */
57663 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET_MSK 0x01000000
57664 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */
57665 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_CLR_MSK 0xfeffffff
57666 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
57667 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_RESET 0x0
57668 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 field value from a register. */
57669 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
57670 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value suitable for setting the register. */
57671 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
57672 
57673 /*
57674  * Field : Mask Byte Control - mbc_1
57675  *
57676  * This array of bits are mask control bits for comparison of each of the MAC
57677  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57678  * received DA or SA with the contents of MAC Address58 high and low registers.
57679  * Each bit controls the masking of the bytes. You can filter a group of addresses
57680  * (known as group address filtering) by masking one or more bytes of the address.
57681  *
57682  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57683  *
57684  * Field Enumeration Values:
57685  *
57686  * Enum | Value | Description
57687  * :----------------------------------------------|:------|:------------------------------------
57688  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57689  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57690  *
57691  * Field Access Macros:
57692  *
57693  */
57694 /*
57695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1
57696  *
57697  * Byte is unmasked (i.e. is compared)
57698  */
57699 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED 0x0
57700 /*
57701  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1
57702  *
57703  * Byte is masked (i.e. not compared)
57704  */
57705 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED 0x1
57706 
57707 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
57708 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_LSB 25
57709 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
57710 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_MSB 25
57711 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
57712 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_WIDTH 1
57713 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */
57714 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET_MSK 0x02000000
57715 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */
57716 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_CLR_MSK 0xfdffffff
57717 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
57718 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_RESET 0x0
57719 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 field value from a register. */
57720 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
57721 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value suitable for setting the register. */
57722 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
57723 
57724 /*
57725  * Field : Mask Byte Control - mbc_2
57726  *
57727  * This array of bits are mask control bits for comparison of each of the MAC
57728  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57729  * received DA or SA with the contents of MAC Address58 high and low registers.
57730  * Each bit controls the masking of the bytes. You can filter a group of addresses
57731  * (known as group address filtering) by masking one or more bytes of the address.
57732  *
57733  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57734  *
57735  * Field Enumeration Values:
57736  *
57737  * Enum | Value | Description
57738  * :----------------------------------------------|:------|:------------------------------------
57739  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57740  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57741  *
57742  * Field Access Macros:
57743  *
57744  */
57745 /*
57746  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2
57747  *
57748  * Byte is unmasked (i.e. is compared)
57749  */
57750 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED 0x0
57751 /*
57752  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2
57753  *
57754  * Byte is masked (i.e. not compared)
57755  */
57756 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED 0x1
57757 
57758 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
57759 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_LSB 26
57760 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
57761 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_MSB 26
57762 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
57763 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_WIDTH 1
57764 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */
57765 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET_MSK 0x04000000
57766 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */
57767 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_CLR_MSK 0xfbffffff
57768 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
57769 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_RESET 0x0
57770 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 field value from a register. */
57771 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
57772 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value suitable for setting the register. */
57773 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
57774 
57775 /*
57776  * Field : Mask Byte Control - mbc_3
57777  *
57778  * This array of bits are mask control bits for comparison of each of the MAC
57779  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57780  * received DA or SA with the contents of MAC Address58 high and low registers.
57781  * Each bit controls the masking of the bytes. You can filter a group of addresses
57782  * (known as group address filtering) by masking one or more bytes of the address.
57783  *
57784  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57785  *
57786  * Field Enumeration Values:
57787  *
57788  * Enum | Value | Description
57789  * :----------------------------------------------|:------|:------------------------------------
57790  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57791  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57792  *
57793  * Field Access Macros:
57794  *
57795  */
57796 /*
57797  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3
57798  *
57799  * Byte is unmasked (i.e. is compared)
57800  */
57801 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED 0x0
57802 /*
57803  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3
57804  *
57805  * Byte is masked (i.e. not compared)
57806  */
57807 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED 0x1
57808 
57809 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
57810 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_LSB 27
57811 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
57812 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_MSB 27
57813 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
57814 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_WIDTH 1
57815 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */
57816 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET_MSK 0x08000000
57817 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */
57818 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_CLR_MSK 0xf7ffffff
57819 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
57820 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_RESET 0x0
57821 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 field value from a register. */
57822 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
57823 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value suitable for setting the register. */
57824 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
57825 
57826 /*
57827  * Field : Mask Byte Control - mbc_4
57828  *
57829  * This array of bits are mask control bits for comparison of each of the MAC
57830  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57831  * received DA or SA with the contents of MAC Address58 high and low registers.
57832  * Each bit controls the masking of the bytes. You can filter a group of addresses
57833  * (known as group address filtering) by masking one or more bytes of the address.
57834  *
57835  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57836  *
57837  * Field Enumeration Values:
57838  *
57839  * Enum | Value | Description
57840  * :----------------------------------------------|:------|:------------------------------------
57841  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57842  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57843  *
57844  * Field Access Macros:
57845  *
57846  */
57847 /*
57848  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4
57849  *
57850  * Byte is unmasked (i.e. is compared)
57851  */
57852 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED 0x0
57853 /*
57854  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4
57855  *
57856  * Byte is masked (i.e. not compared)
57857  */
57858 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED 0x1
57859 
57860 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
57861 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_LSB 28
57862 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
57863 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_MSB 28
57864 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
57865 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_WIDTH 1
57866 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */
57867 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET_MSK 0x10000000
57868 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */
57869 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_CLR_MSK 0xefffffff
57870 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
57871 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_RESET 0x0
57872 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 field value from a register. */
57873 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
57874 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value suitable for setting the register. */
57875 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
57876 
57877 /*
57878  * Field : Mask Byte Control - mbc_5
57879  *
57880  * This array of bits are mask control bits for comparison of each of the MAC
57881  * Address bytes. When masked, the MAC does not compare the corresponding byte of
57882  * received DA or SA with the contents of MAC Address58 high and low registers.
57883  * Each bit controls the masking of the bytes. You can filter a group of addresses
57884  * (known as group address filtering) by masking one or more bytes of the address.
57885  *
57886  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
57887  *
57888  * Field Enumeration Values:
57889  *
57890  * Enum | Value | Description
57891  * :----------------------------------------------|:------|:------------------------------------
57892  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
57893  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
57894  *
57895  * Field Access Macros:
57896  *
57897  */
57898 /*
57899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5
57900  *
57901  * Byte is unmasked (i.e. is compared)
57902  */
57903 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED 0x0
57904 /*
57905  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5
57906  *
57907  * Byte is masked (i.e. not compared)
57908  */
57909 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED 0x1
57910 
57911 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
57912 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_LSB 29
57913 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
57914 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_MSB 29
57915 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
57916 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_WIDTH 1
57917 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */
57918 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET_MSK 0x20000000
57919 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */
57920 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_CLR_MSK 0xdfffffff
57921 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
57922 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_RESET 0x0
57923 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 field value from a register. */
57924 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
57925 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value suitable for setting the register. */
57926 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
57927 
57928 /*
57929  * Field : Source Address - sa
57930  *
57931  * When this bit is enabled, the MAC Address58[47:0] is used to compare with the SA
57932  * fields of the received frame. When this bit is disabled, the MAC Address58[47:0]
57933  * is used to compare with the DA fields of the received frame.
57934  *
57935  * Field Enumeration Values:
57936  *
57937  * Enum | Value | Description
57938  * :----------------------------------------|:------|:-----------------------------
57939  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
57940  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END | 0x1 | MAC address compare enabled
57941  *
57942  * Field Access Macros:
57943  *
57944  */
57945 /*
57946  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA
57947  *
57948  * MAC address compare disabled
57949  */
57950 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD 0x0
57951 /*
57952  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA
57953  *
57954  * MAC address compare enabled
57955  */
57956 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END 0x1
57957 
57958 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
57959 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_LSB 30
57960 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
57961 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_MSB 30
57962 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
57963 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_WIDTH 1
57964 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */
57965 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET_MSK 0x40000000
57966 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */
57967 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_CLR_MSK 0xbfffffff
57968 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
57969 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_RESET 0x0
57970 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA field value from a register. */
57971 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
57972 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value suitable for setting the register. */
57973 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
57974 
57975 /*
57976  * Field : Address Enable - ae
57977  *
57978  * When this bit is enabled, the address filter block uses the 59th MAC address for
57979  * perfect filtering. When this bit is disabled, the address filter block ignores
57980  * the address for filtering.
57981  *
57982  * Field Enumeration Values:
57983  *
57984  * Enum | Value | Description
57985  * :----------------------------------------|:------|:--------------------------------------
57986  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
57987  * ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
57988  *
57989  * Field Access Macros:
57990  *
57991  */
57992 /*
57993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
57994  *
57995  * Second MAC address filtering disabled
57996  */
57997 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD 0x0
57998 /*
57999  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
58000  *
58001  * Second MAC address filtering enabled
58002  */
58003 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END 0x1
58004 
58005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
58006 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_LSB 31
58007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
58008 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_MSB 31
58009 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
58010 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_WIDTH 1
58011 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
58012 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET_MSK 0x80000000
58013 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
58014 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_CLR_MSK 0x7fffffff
58015 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
58016 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_RESET 0x0
58017 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE field value from a register. */
58018 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58019 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value suitable for setting the register. */
58020 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58021 
58022 #ifndef __ASSEMBLY__
58023 /*
58024  * WARNING: The C register and register group struct declarations are provided for
58025  * convenience and illustrative purposes. They should, however, be used with
58026  * caution as the C language standard provides no guarantees about the alignment or
58027  * atomicity of device memory accesses. The recommended practice for writing
58028  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58029  * alt_write_word() functions.
58030  *
58031  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH.
58032  */
58033 struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s
58034 {
58035  uint32_t addrhi : 16; /* MAC Address58 [47:32] */
58036  uint32_t : 8; /* *UNDEFINED* */
58037  uint32_t mbc_0 : 1; /* Mask Byte Control */
58038  uint32_t mbc_1 : 1; /* Mask Byte Control */
58039  uint32_t mbc_2 : 1; /* Mask Byte Control */
58040  uint32_t mbc_3 : 1; /* Mask Byte Control */
58041  uint32_t mbc_4 : 1; /* Mask Byte Control */
58042  uint32_t mbc_5 : 1; /* Mask Byte Control */
58043  uint32_t sa : 1; /* Source Address */
58044  uint32_t ae : 1; /* Address Enable */
58045 };
58046 
58047 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH. */
58048 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t;
58049 #endif /* __ASSEMBLY__ */
58050 
58051 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register from the beginning of the component. */
58052 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST 0x950
58053 /* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register. */
58054 #define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST))
58055 
58056 /*
58057  * Register : Register 597 (MAC Address58 Low Register) - MAC_Address58_Low
58058  *
58059  * The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC
58060  * address of the station.
58061  *
58062  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
58063  * format.
58064  *
58065  * Register Layout
58066  *
58067  * Bits | Access | Reset | Description
58068  * :-------|:-------|:-----------|:---------------------
58069  * [31:0] | RW | 0xffffffff | MAC Address58 [31:0]
58070  *
58071  */
58072 /*
58073  * Field : MAC Address58 [31:0] - addrlo
58074  *
58075  * This field contains the lower 32 bits of the 59th 6-byte MAC address. The
58076  * content of this field is undefined until loaded by software after the
58077  * initialization process.
58078  *
58079  * Field Access Macros:
58080  *
58081  */
58082 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
58083 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_LSB 0
58084 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
58085 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_MSB 31
58086 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
58087 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_WIDTH 32
58088 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
58089 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET_MSK 0xffffffff
58090 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
58091 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_CLR_MSK 0x00000000
58092 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
58093 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_RESET 0xffffffff
58094 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO field value from a register. */
58095 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58096 /* Produces a ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value suitable for setting the register. */
58097 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58098 
58099 #ifndef __ASSEMBLY__
58100 /*
58101  * WARNING: The C register and register group struct declarations are provided for
58102  * convenience and illustrative purposes. They should, however, be used with
58103  * caution as the C language standard provides no guarantees about the alignment or
58104  * atomicity of device memory accesses. The recommended practice for writing
58105  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58106  * alt_write_word() functions.
58107  *
58108  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW.
58109  */
58110 struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s
58111 {
58112  uint32_t addrlo : 32; /* MAC Address58 [31:0] */
58113 };
58114 
58115 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW. */
58116 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s ALT_EMAC_GMAC_MAC_ADDR58_LOW_t;
58117 #endif /* __ASSEMBLY__ */
58118 
58119 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register from the beginning of the component. */
58120 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST 0x954
58121 /* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register. */
58122 #define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST))
58123 
58124 /*
58125  * Register : Register 598 (MAC Address59 High Register) - MAC_Address59_High
58126  *
58127  * The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC
58128  * address of the station. Because the MAC address registers are configured to be
58129  * double-synchronized to the (G)MII clock domains, the synchronization is
58130  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
58131  * endian mode) of the MAC Address59 Low Register are written. For proper
58132  * synchronization updates, the consecutive writes to this Address Low Register
58133  * should be performed after at least four clock cycles in the destination clock
58134  * domain.
58135  *
58136  * Note that all MAC Address High registers (except MAC Address0 High) have the
58137  * same format.
58138  *
58139  * Register Layout
58140  *
58141  * Bits | Access | Reset | Description
58142  * :--------|:-------|:-------|:----------------------
58143  * [15:0] | RW | 0xffff | MAC Address59 [47:32]
58144  * [23:16] | ??? | 0x0 | *UNDEFINED*
58145  * [24] | RW | 0x0 | Mask Byte Control
58146  * [25] | RW | 0x0 | Mask Byte Control
58147  * [26] | RW | 0x0 | Mask Byte Control
58148  * [27] | RW | 0x0 | Mask Byte Control
58149  * [28] | RW | 0x0 | Mask Byte Control
58150  * [29] | RW | 0x0 | Mask Byte Control
58151  * [30] | RW | 0x0 | Source Address
58152  * [31] | RW | 0x0 | Address Enable
58153  *
58154  */
58155 /*
58156  * Field : MAC Address59 [47:32] - addrhi
58157  *
58158  * This field contains the upper 16 bits (47:32) of the 60th 6-byte MAC address.
58159  *
58160  * Field Access Macros:
58161  *
58162  */
58163 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
58164 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_LSB 0
58165 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
58166 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_MSB 15
58167 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
58168 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_WIDTH 16
58169 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
58170 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET_MSK 0x0000ffff
58171 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
58172 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_CLR_MSK 0xffff0000
58173 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
58174 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_RESET 0xffff
58175 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI field value from a register. */
58176 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58177 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value suitable for setting the register. */
58178 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58179 
58180 /*
58181  * Field : Mask Byte Control - mbc_0
58182  *
58183  * This array of bits are mask control bits for comparison of each of the MAC
58184  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58185  * received DA or SA with the contents of MAC Address59 high and low registers.
58186  * Each bit controls the masking of the bytes. You can filter a group of addresses
58187  * (known as group address filtering) by masking one or more bytes of the address.
58188  *
58189  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58190  *
58191  * Field Enumeration Values:
58192  *
58193  * Enum | Value | Description
58194  * :----------------------------------------------|:------|:------------------------------------
58195  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58196  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58197  *
58198  * Field Access Macros:
58199  *
58200  */
58201 /*
58202  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0
58203  *
58204  * Byte is unmasked (i.e. is compared)
58205  */
58206 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED 0x0
58207 /*
58208  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0
58209  *
58210  * Byte is masked (i.e. not compared)
58211  */
58212 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED 0x1
58213 
58214 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
58215 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_LSB 24
58216 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
58217 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_MSB 24
58218 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
58219 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_WIDTH 1
58220 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */
58221 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET_MSK 0x01000000
58222 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */
58223 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_CLR_MSK 0xfeffffff
58224 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
58225 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_RESET 0x0
58226 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 field value from a register. */
58227 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
58228 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value suitable for setting the register. */
58229 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
58230 
58231 /*
58232  * Field : Mask Byte Control - mbc_1
58233  *
58234  * This array of bits are mask control bits for comparison of each of the MAC
58235  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58236  * received DA or SA with the contents of MAC Address59 high and low registers.
58237  * Each bit controls the masking of the bytes. You can filter a group of addresses
58238  * (known as group address filtering) by masking one or more bytes of the address.
58239  *
58240  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58241  *
58242  * Field Enumeration Values:
58243  *
58244  * Enum | Value | Description
58245  * :----------------------------------------------|:------|:------------------------------------
58246  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58247  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58248  *
58249  * Field Access Macros:
58250  *
58251  */
58252 /*
58253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1
58254  *
58255  * Byte is unmasked (i.e. is compared)
58256  */
58257 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED 0x0
58258 /*
58259  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1
58260  *
58261  * Byte is masked (i.e. not compared)
58262  */
58263 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED 0x1
58264 
58265 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
58266 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_LSB 25
58267 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
58268 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_MSB 25
58269 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
58270 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_WIDTH 1
58271 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */
58272 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET_MSK 0x02000000
58273 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */
58274 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_CLR_MSK 0xfdffffff
58275 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
58276 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_RESET 0x0
58277 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 field value from a register. */
58278 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
58279 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value suitable for setting the register. */
58280 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
58281 
58282 /*
58283  * Field : Mask Byte Control - mbc_2
58284  *
58285  * This array of bits are mask control bits for comparison of each of the MAC
58286  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58287  * received DA or SA with the contents of MAC Address59 high and low registers.
58288  * Each bit controls the masking of the bytes. You can filter a group of addresses
58289  * (known as group address filtering) by masking one or more bytes of the address.
58290  *
58291  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58292  *
58293  * Field Enumeration Values:
58294  *
58295  * Enum | Value | Description
58296  * :----------------------------------------------|:------|:------------------------------------
58297  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58298  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58299  *
58300  * Field Access Macros:
58301  *
58302  */
58303 /*
58304  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2
58305  *
58306  * Byte is unmasked (i.e. is compared)
58307  */
58308 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED 0x0
58309 /*
58310  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2
58311  *
58312  * Byte is masked (i.e. not compared)
58313  */
58314 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED 0x1
58315 
58316 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
58317 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_LSB 26
58318 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
58319 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_MSB 26
58320 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
58321 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_WIDTH 1
58322 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */
58323 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET_MSK 0x04000000
58324 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */
58325 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_CLR_MSK 0xfbffffff
58326 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
58327 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_RESET 0x0
58328 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 field value from a register. */
58329 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
58330 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value suitable for setting the register. */
58331 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
58332 
58333 /*
58334  * Field : Mask Byte Control - mbc_3
58335  *
58336  * This array of bits are mask control bits for comparison of each of the MAC
58337  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58338  * received DA or SA with the contents of MAC Address59 high and low registers.
58339  * Each bit controls the masking of the bytes. You can filter a group of addresses
58340  * (known as group address filtering) by masking one or more bytes of the address.
58341  *
58342  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58343  *
58344  * Field Enumeration Values:
58345  *
58346  * Enum | Value | Description
58347  * :----------------------------------------------|:------|:------------------------------------
58348  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58349  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58350  *
58351  * Field Access Macros:
58352  *
58353  */
58354 /*
58355  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3
58356  *
58357  * Byte is unmasked (i.e. is compared)
58358  */
58359 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED 0x0
58360 /*
58361  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3
58362  *
58363  * Byte is masked (i.e. not compared)
58364  */
58365 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED 0x1
58366 
58367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
58368 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_LSB 27
58369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
58370 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_MSB 27
58371 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
58372 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_WIDTH 1
58373 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */
58374 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET_MSK 0x08000000
58375 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */
58376 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_CLR_MSK 0xf7ffffff
58377 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
58378 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_RESET 0x0
58379 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 field value from a register. */
58380 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
58381 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value suitable for setting the register. */
58382 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
58383 
58384 /*
58385  * Field : Mask Byte Control - mbc_4
58386  *
58387  * This array of bits are mask control bits for comparison of each of the MAC
58388  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58389  * received DA or SA with the contents of MAC Address59 high and low registers.
58390  * Each bit controls the masking of the bytes. You can filter a group of addresses
58391  * (known as group address filtering) by masking one or more bytes of the address.
58392  *
58393  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58394  *
58395  * Field Enumeration Values:
58396  *
58397  * Enum | Value | Description
58398  * :----------------------------------------------|:------|:------------------------------------
58399  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58400  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58401  *
58402  * Field Access Macros:
58403  *
58404  */
58405 /*
58406  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4
58407  *
58408  * Byte is unmasked (i.e. is compared)
58409  */
58410 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED 0x0
58411 /*
58412  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4
58413  *
58414  * Byte is masked (i.e. not compared)
58415  */
58416 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED 0x1
58417 
58418 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
58419 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_LSB 28
58420 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
58421 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_MSB 28
58422 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
58423 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_WIDTH 1
58424 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */
58425 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET_MSK 0x10000000
58426 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */
58427 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_CLR_MSK 0xefffffff
58428 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
58429 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_RESET 0x0
58430 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 field value from a register. */
58431 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
58432 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value suitable for setting the register. */
58433 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
58434 
58435 /*
58436  * Field : Mask Byte Control - mbc_5
58437  *
58438  * This array of bits are mask control bits for comparison of each of the MAC
58439  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58440  * received DA or SA with the contents of MAC Address59 high and low registers.
58441  * Each bit controls the masking of the bytes. You can filter a group of addresses
58442  * (known as group address filtering) by masking one or more bytes of the address.
58443  *
58444  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58445  *
58446  * Field Enumeration Values:
58447  *
58448  * Enum | Value | Description
58449  * :----------------------------------------------|:------|:------------------------------------
58450  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58451  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58452  *
58453  * Field Access Macros:
58454  *
58455  */
58456 /*
58457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5
58458  *
58459  * Byte is unmasked (i.e. is compared)
58460  */
58461 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED 0x0
58462 /*
58463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5
58464  *
58465  * Byte is masked (i.e. not compared)
58466  */
58467 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED 0x1
58468 
58469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
58470 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_LSB 29
58471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
58472 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_MSB 29
58473 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
58474 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_WIDTH 1
58475 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */
58476 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET_MSK 0x20000000
58477 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */
58478 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_CLR_MSK 0xdfffffff
58479 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
58480 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_RESET 0x0
58481 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 field value from a register. */
58482 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
58483 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value suitable for setting the register. */
58484 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
58485 
58486 /*
58487  * Field : Source Address - sa
58488  *
58489  * When this bit is enabled, the MAC Address59[47:0] is used to compare with the SA
58490  * fields of the received frame. When this bit is disabled, the MAC Address59[47:0]
58491  * is used to compare with the DA fields of the received frame.
58492  *
58493  * Field Enumeration Values:
58494  *
58495  * Enum | Value | Description
58496  * :----------------------------------------|:------|:-----------------------------
58497  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
58498  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END | 0x1 | MAC address compare enabled
58499  *
58500  * Field Access Macros:
58501  *
58502  */
58503 /*
58504  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA
58505  *
58506  * MAC address compare disabled
58507  */
58508 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD 0x0
58509 /*
58510  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA
58511  *
58512  * MAC address compare enabled
58513  */
58514 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END 0x1
58515 
58516 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
58517 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_LSB 30
58518 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
58519 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_MSB 30
58520 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
58521 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_WIDTH 1
58522 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */
58523 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET_MSK 0x40000000
58524 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */
58525 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_CLR_MSK 0xbfffffff
58526 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
58527 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_RESET 0x0
58528 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA field value from a register. */
58529 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
58530 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value suitable for setting the register. */
58531 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
58532 
58533 /*
58534  * Field : Address Enable - ae
58535  *
58536  * When this bit is enabled, the address filter block uses the 60th MAC address for
58537  * perfect filtering. When this bit is disabled, the address filter block ignores
58538  * the address for filtering.
58539  *
58540  * Field Enumeration Values:
58541  *
58542  * Enum | Value | Description
58543  * :----------------------------------------|:------|:--------------------------------------
58544  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
58545  * ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
58546  *
58547  * Field Access Macros:
58548  *
58549  */
58550 /*
58551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
58552  *
58553  * Second MAC address filtering disabled
58554  */
58555 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD 0x0
58556 /*
58557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
58558  *
58559  * Second MAC address filtering enabled
58560  */
58561 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END 0x1
58562 
58563 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
58564 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_LSB 31
58565 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
58566 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_MSB 31
58567 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
58568 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_WIDTH 1
58569 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
58570 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET_MSK 0x80000000
58571 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
58572 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_CLR_MSK 0x7fffffff
58573 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
58574 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_RESET 0x0
58575 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE field value from a register. */
58576 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
58577 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value suitable for setting the register. */
58578 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
58579 
58580 #ifndef __ASSEMBLY__
58581 /*
58582  * WARNING: The C register and register group struct declarations are provided for
58583  * convenience and illustrative purposes. They should, however, be used with
58584  * caution as the C language standard provides no guarantees about the alignment or
58585  * atomicity of device memory accesses. The recommended practice for writing
58586  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58587  * alt_write_word() functions.
58588  *
58589  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH.
58590  */
58591 struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s
58592 {
58593  uint32_t addrhi : 16; /* MAC Address59 [47:32] */
58594  uint32_t : 8; /* *UNDEFINED* */
58595  uint32_t mbc_0 : 1; /* Mask Byte Control */
58596  uint32_t mbc_1 : 1; /* Mask Byte Control */
58597  uint32_t mbc_2 : 1; /* Mask Byte Control */
58598  uint32_t mbc_3 : 1; /* Mask Byte Control */
58599  uint32_t mbc_4 : 1; /* Mask Byte Control */
58600  uint32_t mbc_5 : 1; /* Mask Byte Control */
58601  uint32_t sa : 1; /* Source Address */
58602  uint32_t ae : 1; /* Address Enable */
58603 };
58604 
58605 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH. */
58606 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t;
58607 #endif /* __ASSEMBLY__ */
58608 
58609 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register from the beginning of the component. */
58610 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST 0x958
58611 /* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register. */
58612 #define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST))
58613 
58614 /*
58615  * Register : Register 599 (MAC Address59 Low Register) - MAC_Address59_Low
58616  *
58617  * The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC
58618  * address of the station.
58619  *
58620  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
58621  * format.
58622  *
58623  * Register Layout
58624  *
58625  * Bits | Access | Reset | Description
58626  * :-------|:-------|:-----------|:---------------------
58627  * [31:0] | RW | 0xffffffff | MAC Address59 [31:0]
58628  *
58629  */
58630 /*
58631  * Field : MAC Address59 [31:0] - addrlo
58632  *
58633  * This field contains the lower 32 bits of the 60th 6-byte MAC address. The
58634  * content of this field is undefined until loaded by software after the
58635  * initialization process.
58636  *
58637  * Field Access Macros:
58638  *
58639  */
58640 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
58641 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_LSB 0
58642 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
58643 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_MSB 31
58644 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
58645 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_WIDTH 32
58646 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
58647 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET_MSK 0xffffffff
58648 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
58649 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_CLR_MSK 0x00000000
58650 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
58651 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_RESET 0xffffffff
58652 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO field value from a register. */
58653 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
58654 /* Produces a ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value suitable for setting the register. */
58655 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
58656 
58657 #ifndef __ASSEMBLY__
58658 /*
58659  * WARNING: The C register and register group struct declarations are provided for
58660  * convenience and illustrative purposes. They should, however, be used with
58661  * caution as the C language standard provides no guarantees about the alignment or
58662  * atomicity of device memory accesses. The recommended practice for writing
58663  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
58664  * alt_write_word() functions.
58665  *
58666  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW.
58667  */
58668 struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s
58669 {
58670  uint32_t addrlo : 32; /* MAC Address59 [31:0] */
58671 };
58672 
58673 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW. */
58674 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s ALT_EMAC_GMAC_MAC_ADDR59_LOW_t;
58675 #endif /* __ASSEMBLY__ */
58676 
58677 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register from the beginning of the component. */
58678 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST 0x95c
58679 /* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register. */
58680 #define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST))
58681 
58682 /*
58683  * Register : Register 600 (MAC Address60 High Register) - MAC_Address60_High
58684  *
58685  * The MAC Address60 High register holds the upper 16 bits of the 61th 6-byte MAC
58686  * address of the station. Because the MAC address registers are configured to be
58687  * double-synchronized to the (G)MII clock domains, the synchronization is
58688  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
58689  * endian mode) of the MAC Address60 Low Register are written. For proper
58690  * synchronization updates, the consecutive writes to this Address Low Register
58691  * should be performed after at least four clock cycles in the destination clock
58692  * domain.
58693  *
58694  * Note that all MAC Address High registers (except MAC Address0 High) have the
58695  * same format.
58696  *
58697  * Register Layout
58698  *
58699  * Bits | Access | Reset | Description
58700  * :--------|:-------|:-------|:----------------------
58701  * [15:0] | RW | 0xffff | MAC Address60 [47:32]
58702  * [23:16] | ??? | 0x0 | *UNDEFINED*
58703  * [24] | RW | 0x0 | Mask Byte Control
58704  * [25] | RW | 0x0 | Mask Byte Control
58705  * [26] | RW | 0x0 | Mask Byte Control
58706  * [27] | RW | 0x0 | Mask Byte Control
58707  * [28] | RW | 0x0 | Mask Byte Control
58708  * [29] | RW | 0x0 | Mask Byte Control
58709  * [30] | RW | 0x0 | Source Address
58710  * [31] | RW | 0x0 | Address Enable
58711  *
58712  */
58713 /*
58714  * Field : MAC Address60 [47:32] - addrhi
58715  *
58716  * This field contains the upper 16 bits (47:32) of the 61th 6-byte MAC address.
58717  *
58718  * Field Access Macros:
58719  *
58720  */
58721 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
58722 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_LSB 0
58723 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
58724 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_MSB 15
58725 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
58726 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_WIDTH 16
58727 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
58728 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET_MSK 0x0000ffff
58729 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
58730 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_CLR_MSK 0xffff0000
58731 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
58732 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_RESET 0xffff
58733 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI field value from a register. */
58734 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
58735 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value suitable for setting the register. */
58736 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
58737 
58738 /*
58739  * Field : Mask Byte Control - mbc_0
58740  *
58741  * This array of bits are mask control bits for comparison of each of the MAC
58742  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58743  * received DA or SA with the contents of MAC Address60 high and low registers.
58744  * Each bit controls the masking of the bytes. You can filter a group of addresses
58745  * (known as group address filtering) by masking one or more bytes of the address.
58746  *
58747  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58748  *
58749  * Field Enumeration Values:
58750  *
58751  * Enum | Value | Description
58752  * :----------------------------------------------|:------|:------------------------------------
58753  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58754  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58755  *
58756  * Field Access Macros:
58757  *
58758  */
58759 /*
58760  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0
58761  *
58762  * Byte is unmasked (i.e. is compared)
58763  */
58764 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED 0x0
58765 /*
58766  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0
58767  *
58768  * Byte is masked (i.e. not compared)
58769  */
58770 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED 0x1
58771 
58772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
58773 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_LSB 24
58774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
58775 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_MSB 24
58776 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
58777 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_WIDTH 1
58778 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */
58779 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET_MSK 0x01000000
58780 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */
58781 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_CLR_MSK 0xfeffffff
58782 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
58783 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_RESET 0x0
58784 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 field value from a register. */
58785 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
58786 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value suitable for setting the register. */
58787 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
58788 
58789 /*
58790  * Field : Mask Byte Control - mbc_1
58791  *
58792  * This array of bits are mask control bits for comparison of each of the MAC
58793  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58794  * received DA or SA with the contents of MAC Address60 high and low registers.
58795  * Each bit controls the masking of the bytes. You can filter a group of addresses
58796  * (known as group address filtering) by masking one or more bytes of the address.
58797  *
58798  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58799  *
58800  * Field Enumeration Values:
58801  *
58802  * Enum | Value | Description
58803  * :----------------------------------------------|:------|:------------------------------------
58804  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58805  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58806  *
58807  * Field Access Macros:
58808  *
58809  */
58810 /*
58811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1
58812  *
58813  * Byte is unmasked (i.e. is compared)
58814  */
58815 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED 0x0
58816 /*
58817  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1
58818  *
58819  * Byte is masked (i.e. not compared)
58820  */
58821 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED 0x1
58822 
58823 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
58824 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_LSB 25
58825 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
58826 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_MSB 25
58827 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
58828 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_WIDTH 1
58829 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */
58830 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET_MSK 0x02000000
58831 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */
58832 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_CLR_MSK 0xfdffffff
58833 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
58834 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_RESET 0x0
58835 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 field value from a register. */
58836 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
58837 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value suitable for setting the register. */
58838 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
58839 
58840 /*
58841  * Field : Mask Byte Control - mbc_2
58842  *
58843  * This array of bits are mask control bits for comparison of each of the MAC
58844  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58845  * received DA or SA with the contents of MAC Address60 high and low registers.
58846  * Each bit controls the masking of the bytes. You can filter a group of addresses
58847  * (known as group address filtering) by masking one or more bytes of the address.
58848  *
58849  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58850  *
58851  * Field Enumeration Values:
58852  *
58853  * Enum | Value | Description
58854  * :----------------------------------------------|:------|:------------------------------------
58855  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58856  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58857  *
58858  * Field Access Macros:
58859  *
58860  */
58861 /*
58862  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2
58863  *
58864  * Byte is unmasked (i.e. is compared)
58865  */
58866 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED 0x0
58867 /*
58868  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2
58869  *
58870  * Byte is masked (i.e. not compared)
58871  */
58872 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED 0x1
58873 
58874 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
58875 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_LSB 26
58876 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
58877 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_MSB 26
58878 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
58879 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_WIDTH 1
58880 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */
58881 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET_MSK 0x04000000
58882 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */
58883 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_CLR_MSK 0xfbffffff
58884 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
58885 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_RESET 0x0
58886 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 field value from a register. */
58887 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
58888 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value suitable for setting the register. */
58889 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
58890 
58891 /*
58892  * Field : Mask Byte Control - mbc_3
58893  *
58894  * This array of bits are mask control bits for comparison of each of the MAC
58895  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58896  * received DA or SA with the contents of MAC Address60 high and low registers.
58897  * Each bit controls the masking of the bytes. You can filter a group of addresses
58898  * (known as group address filtering) by masking one or more bytes of the address.
58899  *
58900  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58901  *
58902  * Field Enumeration Values:
58903  *
58904  * Enum | Value | Description
58905  * :----------------------------------------------|:------|:------------------------------------
58906  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58907  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58908  *
58909  * Field Access Macros:
58910  *
58911  */
58912 /*
58913  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3
58914  *
58915  * Byte is unmasked (i.e. is compared)
58916  */
58917 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED 0x0
58918 /*
58919  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3
58920  *
58921  * Byte is masked (i.e. not compared)
58922  */
58923 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED 0x1
58924 
58925 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
58926 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_LSB 27
58927 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
58928 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_MSB 27
58929 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
58930 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_WIDTH 1
58931 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */
58932 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET_MSK 0x08000000
58933 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */
58934 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_CLR_MSK 0xf7ffffff
58935 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
58936 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_RESET 0x0
58937 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 field value from a register. */
58938 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
58939 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value suitable for setting the register. */
58940 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
58941 
58942 /*
58943  * Field : Mask Byte Control - mbc_4
58944  *
58945  * This array of bits are mask control bits for comparison of each of the MAC
58946  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58947  * received DA or SA with the contents of MAC Address60 high and low registers.
58948  * Each bit controls the masking of the bytes. You can filter a group of addresses
58949  * (known as group address filtering) by masking one or more bytes of the address.
58950  *
58951  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
58952  *
58953  * Field Enumeration Values:
58954  *
58955  * Enum | Value | Description
58956  * :----------------------------------------------|:------|:------------------------------------
58957  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
58958  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
58959  *
58960  * Field Access Macros:
58961  *
58962  */
58963 /*
58964  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4
58965  *
58966  * Byte is unmasked (i.e. is compared)
58967  */
58968 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED 0x0
58969 /*
58970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4
58971  *
58972  * Byte is masked (i.e. not compared)
58973  */
58974 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED 0x1
58975 
58976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
58977 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_LSB 28
58978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
58979 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_MSB 28
58980 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
58981 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_WIDTH 1
58982 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */
58983 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET_MSK 0x10000000
58984 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */
58985 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_CLR_MSK 0xefffffff
58986 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
58987 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_RESET 0x0
58988 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 field value from a register. */
58989 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
58990 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value suitable for setting the register. */
58991 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
58992 
58993 /*
58994  * Field : Mask Byte Control - mbc_5
58995  *
58996  * This array of bits are mask control bits for comparison of each of the MAC
58997  * Address bytes. When masked, the MAC does not compare the corresponding byte of
58998  * received DA or SA with the contents of MAC Address60 high and low registers.
58999  * Each bit controls the masking of the bytes. You can filter a group of addresses
59000  * (known as group address filtering) by masking one or more bytes of the address.
59001  *
59002  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59003  *
59004  * Field Enumeration Values:
59005  *
59006  * Enum | Value | Description
59007  * :----------------------------------------------|:------|:------------------------------------
59008  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59009  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59010  *
59011  * Field Access Macros:
59012  *
59013  */
59014 /*
59015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5
59016  *
59017  * Byte is unmasked (i.e. is compared)
59018  */
59019 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED 0x0
59020 /*
59021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5
59022  *
59023  * Byte is masked (i.e. not compared)
59024  */
59025 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED 0x1
59026 
59027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
59028 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_LSB 29
59029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
59030 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_MSB 29
59031 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
59032 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_WIDTH 1
59033 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */
59034 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET_MSK 0x20000000
59035 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */
59036 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_CLR_MSK 0xdfffffff
59037 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
59038 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_RESET 0x0
59039 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 field value from a register. */
59040 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
59041 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value suitable for setting the register. */
59042 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
59043 
59044 /*
59045  * Field : Source Address - sa
59046  *
59047  * When this bit is enabled, the MAC Address60[47:0] is used to compare with the SA
59048  * fields of the received frame. When this bit is disabled, the MAC Address60[47:0]
59049  * is used to compare with the DA fields of the received frame.
59050  *
59051  * Field Enumeration Values:
59052  *
59053  * Enum | Value | Description
59054  * :----------------------------------------|:------|:-----------------------------
59055  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
59056  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END | 0x1 | MAC address compare enabled
59057  *
59058  * Field Access Macros:
59059  *
59060  */
59061 /*
59062  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA
59063  *
59064  * MAC address compare disabled
59065  */
59066 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD 0x0
59067 /*
59068  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA
59069  *
59070  * MAC address compare enabled
59071  */
59072 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END 0x1
59073 
59074 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
59075 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_LSB 30
59076 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
59077 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_MSB 30
59078 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
59079 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_WIDTH 1
59080 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */
59081 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET_MSK 0x40000000
59082 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */
59083 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_CLR_MSK 0xbfffffff
59084 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
59085 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_RESET 0x0
59086 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA field value from a register. */
59087 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
59088 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value suitable for setting the register. */
59089 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
59090 
59091 /*
59092  * Field : Address Enable - ae
59093  *
59094  * When this bit is enabled, the address filter block uses the 61th MAC address for
59095  * perfect filtering. When this bit is disabled, the address filter block ignores
59096  * the address for filtering.
59097  *
59098  * Field Enumeration Values:
59099  *
59100  * Enum | Value | Description
59101  * :----------------------------------------|:------|:--------------------------------------
59102  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
59103  * ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
59104  *
59105  * Field Access Macros:
59106  *
59107  */
59108 /*
59109  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
59110  *
59111  * Second MAC address filtering disabled
59112  */
59113 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD 0x0
59114 /*
59115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
59116  *
59117  * Second MAC address filtering enabled
59118  */
59119 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END 0x1
59120 
59121 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
59122 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_LSB 31
59123 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
59124 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_MSB 31
59125 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
59126 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_WIDTH 1
59127 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
59128 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET_MSK 0x80000000
59129 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
59130 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_CLR_MSK 0x7fffffff
59131 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
59132 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_RESET 0x0
59133 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE field value from a register. */
59134 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59135 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value suitable for setting the register. */
59136 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59137 
59138 #ifndef __ASSEMBLY__
59139 /*
59140  * WARNING: The C register and register group struct declarations are provided for
59141  * convenience and illustrative purposes. They should, however, be used with
59142  * caution as the C language standard provides no guarantees about the alignment or
59143  * atomicity of device memory accesses. The recommended practice for writing
59144  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59145  * alt_write_word() functions.
59146  *
59147  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH.
59148  */
59149 struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s
59150 {
59151  uint32_t addrhi : 16; /* MAC Address60 [47:32] */
59152  uint32_t : 8; /* *UNDEFINED* */
59153  uint32_t mbc_0 : 1; /* Mask Byte Control */
59154  uint32_t mbc_1 : 1; /* Mask Byte Control */
59155  uint32_t mbc_2 : 1; /* Mask Byte Control */
59156  uint32_t mbc_3 : 1; /* Mask Byte Control */
59157  uint32_t mbc_4 : 1; /* Mask Byte Control */
59158  uint32_t mbc_5 : 1; /* Mask Byte Control */
59159  uint32_t sa : 1; /* Source Address */
59160  uint32_t ae : 1; /* Address Enable */
59161 };
59162 
59163 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH. */
59164 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t;
59165 #endif /* __ASSEMBLY__ */
59166 
59167 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register from the beginning of the component. */
59168 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST 0x960
59169 /* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register. */
59170 #define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST))
59171 
59172 /*
59173  * Register : Register 601 (MAC Address60 Low Register) - MAC_Address60_Low
59174  *
59175  * The MAC Address60 Low register holds the lower 32 bits of the 61th 6-byte MAC
59176  * address of the station.
59177  *
59178  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
59179  * format.
59180  *
59181  * Register Layout
59182  *
59183  * Bits | Access | Reset | Description
59184  * :-------|:-------|:-----------|:---------------------
59185  * [31:0] | RW | 0xffffffff | MAC Address60 [31:0]
59186  *
59187  */
59188 /*
59189  * Field : MAC Address60 [31:0] - addrlo
59190  *
59191  * This field contains the lower 32 bits of the 61th 6-byte MAC address. The
59192  * content of this field is undefined until loaded by software after the
59193  * initialization process.
59194  *
59195  * Field Access Macros:
59196  *
59197  */
59198 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
59199 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_LSB 0
59200 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
59201 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_MSB 31
59202 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
59203 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_WIDTH 32
59204 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
59205 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET_MSK 0xffffffff
59206 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
59207 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_CLR_MSK 0x00000000
59208 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
59209 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_RESET 0xffffffff
59210 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO field value from a register. */
59211 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59212 /* Produces a ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value suitable for setting the register. */
59213 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59214 
59215 #ifndef __ASSEMBLY__
59216 /*
59217  * WARNING: The C register and register group struct declarations are provided for
59218  * convenience and illustrative purposes. They should, however, be used with
59219  * caution as the C language standard provides no guarantees about the alignment or
59220  * atomicity of device memory accesses. The recommended practice for writing
59221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59222  * alt_write_word() functions.
59223  *
59224  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW.
59225  */
59226 struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s
59227 {
59228  uint32_t addrlo : 32; /* MAC Address60 [31:0] */
59229 };
59230 
59231 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW. */
59232 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s ALT_EMAC_GMAC_MAC_ADDR60_LOW_t;
59233 #endif /* __ASSEMBLY__ */
59234 
59235 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register from the beginning of the component. */
59236 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST 0x964
59237 /* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register. */
59238 #define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST))
59239 
59240 /*
59241  * Register : Register 602 (MAC Address61 High Register) - MAC_Address61_High
59242  *
59243  * The MAC Address61 High register holds the upper 16 bits of the 62th 6-byte MAC
59244  * address of the station. Because the MAC address registers are configured to be
59245  * double-synchronized to the (G)MII clock domains, the synchronization is
59246  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
59247  * endian mode) of the MAC Address61 Low Register are written. For proper
59248  * synchronization updates, the consecutive writes to this Address Low Register
59249  * should be performed after at least four clock cycles in the destination clock
59250  * domain.
59251  *
59252  * Note that all MAC Address High registers (except MAC Address0 High) have the
59253  * same format.
59254  *
59255  * Register Layout
59256  *
59257  * Bits | Access | Reset | Description
59258  * :--------|:-------|:-------|:----------------------
59259  * [15:0] | RW | 0xffff | MAC Address61 [47:32]
59260  * [23:16] | ??? | 0x0 | *UNDEFINED*
59261  * [24] | RW | 0x0 | Mask Byte Control
59262  * [25] | RW | 0x0 | Mask Byte Control
59263  * [26] | RW | 0x0 | Mask Byte Control
59264  * [27] | RW | 0x0 | Mask Byte Control
59265  * [28] | RW | 0x0 | Mask Byte Control
59266  * [29] | RW | 0x0 | Mask Byte Control
59267  * [30] | RW | 0x0 | Source Address
59268  * [31] | RW | 0x0 | Address Enable
59269  *
59270  */
59271 /*
59272  * Field : MAC Address61 [47:32] - addrhi
59273  *
59274  * This field contains the upper 16 bits (47:32) of the 62th 6-byte MAC address.
59275  *
59276  * Field Access Macros:
59277  *
59278  */
59279 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
59280 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_LSB 0
59281 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
59282 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_MSB 15
59283 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
59284 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_WIDTH 16
59285 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
59286 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET_MSK 0x0000ffff
59287 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
59288 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_CLR_MSK 0xffff0000
59289 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
59290 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_RESET 0xffff
59291 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI field value from a register. */
59292 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59293 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value suitable for setting the register. */
59294 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59295 
59296 /*
59297  * Field : Mask Byte Control - mbc_0
59298  *
59299  * This array of bits are mask control bits for comparison of each of the MAC
59300  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59301  * received DA or SA with the contents of MAC Address61 high and low registers.
59302  * Each bit controls the masking of the bytes. You can filter a group of addresses
59303  * (known as group address filtering) by masking one or more bytes of the address.
59304  *
59305  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59306  *
59307  * Field Enumeration Values:
59308  *
59309  * Enum | Value | Description
59310  * :----------------------------------------------|:------|:------------------------------------
59311  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59312  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59313  *
59314  * Field Access Macros:
59315  *
59316  */
59317 /*
59318  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0
59319  *
59320  * Byte is unmasked (i.e. is compared)
59321  */
59322 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED 0x0
59323 /*
59324  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0
59325  *
59326  * Byte is masked (i.e. not compared)
59327  */
59328 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED 0x1
59329 
59330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
59331 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_LSB 24
59332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
59333 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_MSB 24
59334 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
59335 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_WIDTH 1
59336 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */
59337 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET_MSK 0x01000000
59338 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */
59339 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_CLR_MSK 0xfeffffff
59340 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
59341 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_RESET 0x0
59342 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 field value from a register. */
59343 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
59344 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value suitable for setting the register. */
59345 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
59346 
59347 /*
59348  * Field : Mask Byte Control - mbc_1
59349  *
59350  * This array of bits are mask control bits for comparison of each of the MAC
59351  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59352  * received DA or SA with the contents of MAC Address61 high and low registers.
59353  * Each bit controls the masking of the bytes. You can filter a group of addresses
59354  * (known as group address filtering) by masking one or more bytes of the address.
59355  *
59356  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59357  *
59358  * Field Enumeration Values:
59359  *
59360  * Enum | Value | Description
59361  * :----------------------------------------------|:------|:------------------------------------
59362  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59363  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59364  *
59365  * Field Access Macros:
59366  *
59367  */
59368 /*
59369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1
59370  *
59371  * Byte is unmasked (i.e. is compared)
59372  */
59373 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED 0x0
59374 /*
59375  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1
59376  *
59377  * Byte is masked (i.e. not compared)
59378  */
59379 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED 0x1
59380 
59381 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
59382 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_LSB 25
59383 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
59384 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_MSB 25
59385 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
59386 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_WIDTH 1
59387 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */
59388 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET_MSK 0x02000000
59389 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */
59390 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_CLR_MSK 0xfdffffff
59391 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
59392 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_RESET 0x0
59393 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 field value from a register. */
59394 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
59395 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value suitable for setting the register. */
59396 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
59397 
59398 /*
59399  * Field : Mask Byte Control - mbc_2
59400  *
59401  * This array of bits are mask control bits for comparison of each of the MAC
59402  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59403  * received DA or SA with the contents of MAC Address61 high and low registers.
59404  * Each bit controls the masking of the bytes. You can filter a group of addresses
59405  * (known as group address filtering) by masking one or more bytes of the address.
59406  *
59407  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59408  *
59409  * Field Enumeration Values:
59410  *
59411  * Enum | Value | Description
59412  * :----------------------------------------------|:------|:------------------------------------
59413  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59414  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59415  *
59416  * Field Access Macros:
59417  *
59418  */
59419 /*
59420  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2
59421  *
59422  * Byte is unmasked (i.e. is compared)
59423  */
59424 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED 0x0
59425 /*
59426  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2
59427  *
59428  * Byte is masked (i.e. not compared)
59429  */
59430 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED 0x1
59431 
59432 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
59433 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_LSB 26
59434 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
59435 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_MSB 26
59436 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
59437 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_WIDTH 1
59438 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */
59439 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET_MSK 0x04000000
59440 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */
59441 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_CLR_MSK 0xfbffffff
59442 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
59443 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_RESET 0x0
59444 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 field value from a register. */
59445 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
59446 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value suitable for setting the register. */
59447 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
59448 
59449 /*
59450  * Field : Mask Byte Control - mbc_3
59451  *
59452  * This array of bits are mask control bits for comparison of each of the MAC
59453  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59454  * received DA or SA with the contents of MAC Address61 high and low registers.
59455  * Each bit controls the masking of the bytes. You can filter a group of addresses
59456  * (known as group address filtering) by masking one or more bytes of the address.
59457  *
59458  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59459  *
59460  * Field Enumeration Values:
59461  *
59462  * Enum | Value | Description
59463  * :----------------------------------------------|:------|:------------------------------------
59464  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59465  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59466  *
59467  * Field Access Macros:
59468  *
59469  */
59470 /*
59471  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3
59472  *
59473  * Byte is unmasked (i.e. is compared)
59474  */
59475 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED 0x0
59476 /*
59477  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3
59478  *
59479  * Byte is masked (i.e. not compared)
59480  */
59481 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED 0x1
59482 
59483 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
59484 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_LSB 27
59485 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
59486 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_MSB 27
59487 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
59488 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_WIDTH 1
59489 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */
59490 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET_MSK 0x08000000
59491 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */
59492 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_CLR_MSK 0xf7ffffff
59493 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
59494 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_RESET 0x0
59495 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 field value from a register. */
59496 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
59497 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value suitable for setting the register. */
59498 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
59499 
59500 /*
59501  * Field : Mask Byte Control - mbc_4
59502  *
59503  * This array of bits are mask control bits for comparison of each of the MAC
59504  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59505  * received DA or SA with the contents of MAC Address61 high and low registers.
59506  * Each bit controls the masking of the bytes. You can filter a group of addresses
59507  * (known as group address filtering) by masking one or more bytes of the address.
59508  *
59509  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59510  *
59511  * Field Enumeration Values:
59512  *
59513  * Enum | Value | Description
59514  * :----------------------------------------------|:------|:------------------------------------
59515  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59516  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59517  *
59518  * Field Access Macros:
59519  *
59520  */
59521 /*
59522  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4
59523  *
59524  * Byte is unmasked (i.e. is compared)
59525  */
59526 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED 0x0
59527 /*
59528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4
59529  *
59530  * Byte is masked (i.e. not compared)
59531  */
59532 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED 0x1
59533 
59534 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
59535 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_LSB 28
59536 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
59537 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_MSB 28
59538 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
59539 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_WIDTH 1
59540 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */
59541 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET_MSK 0x10000000
59542 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */
59543 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_CLR_MSK 0xefffffff
59544 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
59545 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_RESET 0x0
59546 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 field value from a register. */
59547 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
59548 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value suitable for setting the register. */
59549 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
59550 
59551 /*
59552  * Field : Mask Byte Control - mbc_5
59553  *
59554  * This array of bits are mask control bits for comparison of each of the MAC
59555  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59556  * received DA or SA with the contents of MAC Address61 high and low registers.
59557  * Each bit controls the masking of the bytes. You can filter a group of addresses
59558  * (known as group address filtering) by masking one or more bytes of the address.
59559  *
59560  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59561  *
59562  * Field Enumeration Values:
59563  *
59564  * Enum | Value | Description
59565  * :----------------------------------------------|:------|:------------------------------------
59566  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59567  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59568  *
59569  * Field Access Macros:
59570  *
59571  */
59572 /*
59573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5
59574  *
59575  * Byte is unmasked (i.e. is compared)
59576  */
59577 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED 0x0
59578 /*
59579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5
59580  *
59581  * Byte is masked (i.e. not compared)
59582  */
59583 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED 0x1
59584 
59585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
59586 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_LSB 29
59587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
59588 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_MSB 29
59589 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
59590 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_WIDTH 1
59591 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */
59592 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET_MSK 0x20000000
59593 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */
59594 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_CLR_MSK 0xdfffffff
59595 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
59596 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_RESET 0x0
59597 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 field value from a register. */
59598 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
59599 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value suitable for setting the register. */
59600 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
59601 
59602 /*
59603  * Field : Source Address - sa
59604  *
59605  * When this bit is enabled, the MAC Address61[47:0] is used to compare with the SA
59606  * fields of the received frame. When this bit is disabled, the MAC Address61[47:0]
59607  * is used to compare with the DA fields of the received frame.
59608  *
59609  * Field Enumeration Values:
59610  *
59611  * Enum | Value | Description
59612  * :----------------------------------------|:------|:-----------------------------
59613  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
59614  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END | 0x1 | MAC address compare enabled
59615  *
59616  * Field Access Macros:
59617  *
59618  */
59619 /*
59620  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA
59621  *
59622  * MAC address compare disabled
59623  */
59624 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD 0x0
59625 /*
59626  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA
59627  *
59628  * MAC address compare enabled
59629  */
59630 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END 0x1
59631 
59632 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
59633 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_LSB 30
59634 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
59635 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_MSB 30
59636 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
59637 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_WIDTH 1
59638 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */
59639 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET_MSK 0x40000000
59640 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */
59641 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_CLR_MSK 0xbfffffff
59642 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
59643 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_RESET 0x0
59644 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA field value from a register. */
59645 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
59646 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value suitable for setting the register. */
59647 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
59648 
59649 /*
59650  * Field : Address Enable - ae
59651  *
59652  * When this bit is enabled, the address filter block uses the 62th MAC address for
59653  * perfect filtering. When this bit is disabled, the address filter block ignores
59654  * the address for filtering.
59655  *
59656  * Field Enumeration Values:
59657  *
59658  * Enum | Value | Description
59659  * :----------------------------------------|:------|:--------------------------------------
59660  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
59661  * ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
59662  *
59663  * Field Access Macros:
59664  *
59665  */
59666 /*
59667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
59668  *
59669  * Second MAC address filtering disabled
59670  */
59671 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD 0x0
59672 /*
59673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
59674  *
59675  * Second MAC address filtering enabled
59676  */
59677 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END 0x1
59678 
59679 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
59680 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_LSB 31
59681 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
59682 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_MSB 31
59683 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
59684 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_WIDTH 1
59685 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
59686 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET_MSK 0x80000000
59687 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
59688 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_CLR_MSK 0x7fffffff
59689 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
59690 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_RESET 0x0
59691 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE field value from a register. */
59692 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
59693 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value suitable for setting the register. */
59694 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
59695 
59696 #ifndef __ASSEMBLY__
59697 /*
59698  * WARNING: The C register and register group struct declarations are provided for
59699  * convenience and illustrative purposes. They should, however, be used with
59700  * caution as the C language standard provides no guarantees about the alignment or
59701  * atomicity of device memory accesses. The recommended practice for writing
59702  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59703  * alt_write_word() functions.
59704  *
59705  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH.
59706  */
59707 struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s
59708 {
59709  uint32_t addrhi : 16; /* MAC Address61 [47:32] */
59710  uint32_t : 8; /* *UNDEFINED* */
59711  uint32_t mbc_0 : 1; /* Mask Byte Control */
59712  uint32_t mbc_1 : 1; /* Mask Byte Control */
59713  uint32_t mbc_2 : 1; /* Mask Byte Control */
59714  uint32_t mbc_3 : 1; /* Mask Byte Control */
59715  uint32_t mbc_4 : 1; /* Mask Byte Control */
59716  uint32_t mbc_5 : 1; /* Mask Byte Control */
59717  uint32_t sa : 1; /* Source Address */
59718  uint32_t ae : 1; /* Address Enable */
59719 };
59720 
59721 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH. */
59722 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t;
59723 #endif /* __ASSEMBLY__ */
59724 
59725 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register from the beginning of the component. */
59726 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST 0x968
59727 /* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register. */
59728 #define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST))
59729 
59730 /*
59731  * Register : Register 603 (MAC Address61 Low Register) - MAC_Address61_Low
59732  *
59733  * The MAC Address61 Low register holds the lower 32 bits of the 62th 6-byte MAC
59734  * address of the station.
59735  *
59736  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
59737  * format.
59738  *
59739  * Register Layout
59740  *
59741  * Bits | Access | Reset | Description
59742  * :-------|:-------|:-----------|:---------------------
59743  * [31:0] | RW | 0xffffffff | MAC Address61 [31:0]
59744  *
59745  */
59746 /*
59747  * Field : MAC Address61 [31:0] - addrlo
59748  *
59749  * This field contains the lower 32 bits of the 62th 6-byte MAC address. The
59750  * content of this field is undefined until loaded by software after the
59751  * initialization process.
59752  *
59753  * Field Access Macros:
59754  *
59755  */
59756 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
59757 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_LSB 0
59758 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
59759 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_MSB 31
59760 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
59761 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_WIDTH 32
59762 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
59763 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET_MSK 0xffffffff
59764 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
59765 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_CLR_MSK 0x00000000
59766 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
59767 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_RESET 0xffffffff
59768 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO field value from a register. */
59769 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
59770 /* Produces a ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value suitable for setting the register. */
59771 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
59772 
59773 #ifndef __ASSEMBLY__
59774 /*
59775  * WARNING: The C register and register group struct declarations are provided for
59776  * convenience and illustrative purposes. They should, however, be used with
59777  * caution as the C language standard provides no guarantees about the alignment or
59778  * atomicity of device memory accesses. The recommended practice for writing
59779  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
59780  * alt_write_word() functions.
59781  *
59782  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW.
59783  */
59784 struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s
59785 {
59786  uint32_t addrlo : 32; /* MAC Address61 [31:0] */
59787 };
59788 
59789 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW. */
59790 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s ALT_EMAC_GMAC_MAC_ADDR61_LOW_t;
59791 #endif /* __ASSEMBLY__ */
59792 
59793 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register from the beginning of the component. */
59794 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST 0x96c
59795 /* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register. */
59796 #define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST))
59797 
59798 /*
59799  * Register : Register 604 (MAC Address62 High Register) - MAC_Address62_High
59800  *
59801  * The MAC Address62 High register holds the upper 16 bits of the 63th 6-byte MAC
59802  * address of the station. Because the MAC address registers are configured to be
59803  * double-synchronized to the (G)MII clock domains, the synchronization is
59804  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
59805  * endian mode) of the MAC Address62 Low Register are written. For proper
59806  * synchronization updates, the consecutive writes to this Address Low Register
59807  * should be performed after at least four clock cycles in the destination clock
59808  * domain.
59809  *
59810  * Note that all MAC Address High registers (except MAC Address0 High) have the
59811  * same format.
59812  *
59813  * Register Layout
59814  *
59815  * Bits | Access | Reset | Description
59816  * :--------|:-------|:-------|:----------------------
59817  * [15:0] | RW | 0xffff | MAC Address62 [47:32]
59818  * [23:16] | ??? | 0x0 | *UNDEFINED*
59819  * [24] | RW | 0x0 | Mask Byte Control
59820  * [25] | RW | 0x0 | Mask Byte Control
59821  * [26] | RW | 0x0 | Mask Byte Control
59822  * [27] | RW | 0x0 | Mask Byte Control
59823  * [28] | RW | 0x0 | Mask Byte Control
59824  * [29] | RW | 0x0 | Mask Byte Control
59825  * [30] | RW | 0x0 | Source Address
59826  * [31] | RW | 0x0 | Address Enable
59827  *
59828  */
59829 /*
59830  * Field : MAC Address62 [47:32] - addrhi
59831  *
59832  * This field contains the upper 16 bits (47:32) of the 63th 6-byte MAC address.
59833  *
59834  * Field Access Macros:
59835  *
59836  */
59837 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
59838 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_LSB 0
59839 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
59840 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_MSB 15
59841 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
59842 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_WIDTH 16
59843 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
59844 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET_MSK 0x0000ffff
59845 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
59846 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_CLR_MSK 0xffff0000
59847 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
59848 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_RESET 0xffff
59849 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI field value from a register. */
59850 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
59851 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value suitable for setting the register. */
59852 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
59853 
59854 /*
59855  * Field : Mask Byte Control - mbc_0
59856  *
59857  * This array of bits are mask control bits for comparison of each of the MAC
59858  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59859  * received DA or SA with the contents of MAC Address62 high and low registers.
59860  * Each bit controls the masking of the bytes. You can filter a group of addresses
59861  * (known as group address filtering) by masking one or more bytes of the address.
59862  *
59863  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59864  *
59865  * Field Enumeration Values:
59866  *
59867  * Enum | Value | Description
59868  * :----------------------------------------------|:------|:------------------------------------
59869  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59870  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59871  *
59872  * Field Access Macros:
59873  *
59874  */
59875 /*
59876  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0
59877  *
59878  * Byte is unmasked (i.e. is compared)
59879  */
59880 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED 0x0
59881 /*
59882  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0
59883  *
59884  * Byte is masked (i.e. not compared)
59885  */
59886 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED 0x1
59887 
59888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
59889 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_LSB 24
59890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
59891 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_MSB 24
59892 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
59893 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_WIDTH 1
59894 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */
59895 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET_MSK 0x01000000
59896 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */
59897 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_CLR_MSK 0xfeffffff
59898 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
59899 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_RESET 0x0
59900 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 field value from a register. */
59901 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
59902 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value suitable for setting the register. */
59903 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
59904 
59905 /*
59906  * Field : Mask Byte Control - mbc_1
59907  *
59908  * This array of bits are mask control bits for comparison of each of the MAC
59909  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59910  * received DA or SA with the contents of MAC Address62 high and low registers.
59911  * Each bit controls the masking of the bytes. You can filter a group of addresses
59912  * (known as group address filtering) by masking one or more bytes of the address.
59913  *
59914  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59915  *
59916  * Field Enumeration Values:
59917  *
59918  * Enum | Value | Description
59919  * :----------------------------------------------|:------|:------------------------------------
59920  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59921  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59922  *
59923  * Field Access Macros:
59924  *
59925  */
59926 /*
59927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1
59928  *
59929  * Byte is unmasked (i.e. is compared)
59930  */
59931 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED 0x0
59932 /*
59933  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1
59934  *
59935  * Byte is masked (i.e. not compared)
59936  */
59937 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED 0x1
59938 
59939 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
59940 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_LSB 25
59941 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
59942 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_MSB 25
59943 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
59944 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_WIDTH 1
59945 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */
59946 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET_MSK 0x02000000
59947 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */
59948 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_CLR_MSK 0xfdffffff
59949 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
59950 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_RESET 0x0
59951 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 field value from a register. */
59952 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
59953 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value suitable for setting the register. */
59954 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
59955 
59956 /*
59957  * Field : Mask Byte Control - mbc_2
59958  *
59959  * This array of bits are mask control bits for comparison of each of the MAC
59960  * Address bytes. When masked, the MAC does not compare the corresponding byte of
59961  * received DA or SA with the contents of MAC Address62 high and low registers.
59962  * Each bit controls the masking of the bytes. You can filter a group of addresses
59963  * (known as group address filtering) by masking one or more bytes of the address.
59964  *
59965  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
59966  *
59967  * Field Enumeration Values:
59968  *
59969  * Enum | Value | Description
59970  * :----------------------------------------------|:------|:------------------------------------
59971  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
59972  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
59973  *
59974  * Field Access Macros:
59975  *
59976  */
59977 /*
59978  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2
59979  *
59980  * Byte is unmasked (i.e. is compared)
59981  */
59982 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED 0x0
59983 /*
59984  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2
59985  *
59986  * Byte is masked (i.e. not compared)
59987  */
59988 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED 0x1
59989 
59990 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
59991 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_LSB 26
59992 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
59993 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_MSB 26
59994 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
59995 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_WIDTH 1
59996 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */
59997 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET_MSK 0x04000000
59998 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */
59999 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_CLR_MSK 0xfbffffff
60000 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
60001 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_RESET 0x0
60002 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 field value from a register. */
60003 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
60004 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value suitable for setting the register. */
60005 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
60006 
60007 /*
60008  * Field : Mask Byte Control - mbc_3
60009  *
60010  * This array of bits are mask control bits for comparison of each of the MAC
60011  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60012  * received DA or SA with the contents of MAC Address62 high and low registers.
60013  * Each bit controls the masking of the bytes. You can filter a group of addresses
60014  * (known as group address filtering) by masking one or more bytes of the address.
60015  *
60016  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60017  *
60018  * Field Enumeration Values:
60019  *
60020  * Enum | Value | Description
60021  * :----------------------------------------------|:------|:------------------------------------
60022  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60023  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60024  *
60025  * Field Access Macros:
60026  *
60027  */
60028 /*
60029  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3
60030  *
60031  * Byte is unmasked (i.e. is compared)
60032  */
60033 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED 0x0
60034 /*
60035  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3
60036  *
60037  * Byte is masked (i.e. not compared)
60038  */
60039 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED 0x1
60040 
60041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
60042 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_LSB 27
60043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
60044 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_MSB 27
60045 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
60046 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_WIDTH 1
60047 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */
60048 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET_MSK 0x08000000
60049 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */
60050 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_CLR_MSK 0xf7ffffff
60051 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
60052 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_RESET 0x0
60053 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 field value from a register. */
60054 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
60055 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value suitable for setting the register. */
60056 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
60057 
60058 /*
60059  * Field : Mask Byte Control - mbc_4
60060  *
60061  * This array of bits are mask control bits for comparison of each of the MAC
60062  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60063  * received DA or SA with the contents of MAC Address62 high and low registers.
60064  * Each bit controls the masking of the bytes. You can filter a group of addresses
60065  * (known as group address filtering) by masking one or more bytes of the address.
60066  *
60067  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60068  *
60069  * Field Enumeration Values:
60070  *
60071  * Enum | Value | Description
60072  * :----------------------------------------------|:------|:------------------------------------
60073  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60074  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60075  *
60076  * Field Access Macros:
60077  *
60078  */
60079 /*
60080  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4
60081  *
60082  * Byte is unmasked (i.e. is compared)
60083  */
60084 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED 0x0
60085 /*
60086  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4
60087  *
60088  * Byte is masked (i.e. not compared)
60089  */
60090 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED 0x1
60091 
60092 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
60093 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_LSB 28
60094 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
60095 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_MSB 28
60096 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
60097 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_WIDTH 1
60098 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */
60099 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET_MSK 0x10000000
60100 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */
60101 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_CLR_MSK 0xefffffff
60102 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
60103 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_RESET 0x0
60104 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 field value from a register. */
60105 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
60106 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value suitable for setting the register. */
60107 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
60108 
60109 /*
60110  * Field : Mask Byte Control - mbc_5
60111  *
60112  * This array of bits are mask control bits for comparison of each of the MAC
60113  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60114  * received DA or SA with the contents of MAC Address62 high and low registers.
60115  * Each bit controls the masking of the bytes. You can filter a group of addresses
60116  * (known as group address filtering) by masking one or more bytes of the address.
60117  *
60118  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60119  *
60120  * Field Enumeration Values:
60121  *
60122  * Enum | Value | Description
60123  * :----------------------------------------------|:------|:------------------------------------
60124  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60125  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60126  *
60127  * Field Access Macros:
60128  *
60129  */
60130 /*
60131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5
60132  *
60133  * Byte is unmasked (i.e. is compared)
60134  */
60135 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED 0x0
60136 /*
60137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5
60138  *
60139  * Byte is masked (i.e. not compared)
60140  */
60141 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED 0x1
60142 
60143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
60144 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_LSB 29
60145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
60146 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_MSB 29
60147 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
60148 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_WIDTH 1
60149 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */
60150 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET_MSK 0x20000000
60151 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */
60152 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_CLR_MSK 0xdfffffff
60153 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
60154 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_RESET 0x0
60155 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 field value from a register. */
60156 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
60157 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value suitable for setting the register. */
60158 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
60159 
60160 /*
60161  * Field : Source Address - sa
60162  *
60163  * When this bit is enabled, the MAC Address62[47:0] is used to compare with the SA
60164  * fields of the received frame. When this bit is disabled, the MAC Address62[47:0]
60165  * is used to compare with the DA fields of the received frame.
60166  *
60167  * Field Enumeration Values:
60168  *
60169  * Enum | Value | Description
60170  * :----------------------------------------|:------|:-----------------------------
60171  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
60172  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END | 0x1 | MAC address compare enabled
60173  *
60174  * Field Access Macros:
60175  *
60176  */
60177 /*
60178  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA
60179  *
60180  * MAC address compare disabled
60181  */
60182 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD 0x0
60183 /*
60184  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA
60185  *
60186  * MAC address compare enabled
60187  */
60188 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END 0x1
60189 
60190 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
60191 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_LSB 30
60192 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
60193 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_MSB 30
60194 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
60195 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_WIDTH 1
60196 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */
60197 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET_MSK 0x40000000
60198 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */
60199 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_CLR_MSK 0xbfffffff
60200 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
60201 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_RESET 0x0
60202 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA field value from a register. */
60203 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
60204 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value suitable for setting the register. */
60205 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
60206 
60207 /*
60208  * Field : Address Enable - ae
60209  *
60210  * When this bit is enabled, the address filter block uses the 63th MAC address for
60211  * perfect filtering. When this bit is disabled, the address filter block ignores
60212  * the address for filtering.
60213  *
60214  * Field Enumeration Values:
60215  *
60216  * Enum | Value | Description
60217  * :----------------------------------------|:------|:--------------------------------------
60218  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
60219  * ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
60220  *
60221  * Field Access Macros:
60222  *
60223  */
60224 /*
60225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
60226  *
60227  * Second MAC address filtering disabled
60228  */
60229 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD 0x0
60230 /*
60231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
60232  *
60233  * Second MAC address filtering enabled
60234  */
60235 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END 0x1
60236 
60237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
60238 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_LSB 31
60239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
60240 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_MSB 31
60241 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
60242 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_WIDTH 1
60243 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
60244 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET_MSK 0x80000000
60245 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
60246 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_CLR_MSK 0x7fffffff
60247 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
60248 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_RESET 0x0
60249 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE field value from a register. */
60250 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60251 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value suitable for setting the register. */
60252 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60253 
60254 #ifndef __ASSEMBLY__
60255 /*
60256  * WARNING: The C register and register group struct declarations are provided for
60257  * convenience and illustrative purposes. They should, however, be used with
60258  * caution as the C language standard provides no guarantees about the alignment or
60259  * atomicity of device memory accesses. The recommended practice for writing
60260  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60261  * alt_write_word() functions.
60262  *
60263  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH.
60264  */
60265 struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s
60266 {
60267  uint32_t addrhi : 16; /* MAC Address62 [47:32] */
60268  uint32_t : 8; /* *UNDEFINED* */
60269  uint32_t mbc_0 : 1; /* Mask Byte Control */
60270  uint32_t mbc_1 : 1; /* Mask Byte Control */
60271  uint32_t mbc_2 : 1; /* Mask Byte Control */
60272  uint32_t mbc_3 : 1; /* Mask Byte Control */
60273  uint32_t mbc_4 : 1; /* Mask Byte Control */
60274  uint32_t mbc_5 : 1; /* Mask Byte Control */
60275  uint32_t sa : 1; /* Source Address */
60276  uint32_t ae : 1; /* Address Enable */
60277 };
60278 
60279 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH. */
60280 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t;
60281 #endif /* __ASSEMBLY__ */
60282 
60283 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register from the beginning of the component. */
60284 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST 0x970
60285 /* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register. */
60286 #define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST))
60287 
60288 /*
60289  * Register : Register 605 (MAC Address62 Low Register) - MAC_Address62_Low
60290  *
60291  * The MAC Address62 Low register holds the lower 32 bits of the 63th 6-byte MAC
60292  * address of the station.
60293  *
60294  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
60295  * format.
60296  *
60297  * Register Layout
60298  *
60299  * Bits | Access | Reset | Description
60300  * :-------|:-------|:-----------|:---------------------
60301  * [31:0] | RW | 0xffffffff | MAC Address62 [31:0]
60302  *
60303  */
60304 /*
60305  * Field : MAC Address62 [31:0] - addrlo
60306  *
60307  * This field contains the lower 32 bits of the 63th 6-byte MAC address. The
60308  * content of this field is undefined until loaded by software after the
60309  * initialization process.
60310  *
60311  * Field Access Macros:
60312  *
60313  */
60314 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
60315 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_LSB 0
60316 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
60317 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_MSB 31
60318 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
60319 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_WIDTH 32
60320 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
60321 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET_MSK 0xffffffff
60322 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
60323 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_CLR_MSK 0x00000000
60324 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
60325 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_RESET 0xffffffff
60326 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO field value from a register. */
60327 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60328 /* Produces a ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value suitable for setting the register. */
60329 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60330 
60331 #ifndef __ASSEMBLY__
60332 /*
60333  * WARNING: The C register and register group struct declarations are provided for
60334  * convenience and illustrative purposes. They should, however, be used with
60335  * caution as the C language standard provides no guarantees about the alignment or
60336  * atomicity of device memory accesses. The recommended practice for writing
60337  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60338  * alt_write_word() functions.
60339  *
60340  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW.
60341  */
60342 struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s
60343 {
60344  uint32_t addrlo : 32; /* MAC Address62 [31:0] */
60345 };
60346 
60347 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW. */
60348 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s ALT_EMAC_GMAC_MAC_ADDR62_LOW_t;
60349 #endif /* __ASSEMBLY__ */
60350 
60351 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register from the beginning of the component. */
60352 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST 0x974
60353 /* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register. */
60354 #define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST))
60355 
60356 /*
60357  * Register : Register 606 (MAC Address63 High Register) - MAC_Address63_High
60358  *
60359  * The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC
60360  * address of the station. Because the MAC address registers are configured to be
60361  * double-synchronized to the (G)MII clock domains, the synchronization is
60362  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
60363  * endian mode) of the MAC Address63 Low Register are written. For proper
60364  * synchronization updates, the consecutive writes to this Address Low Register
60365  * should be performed after at least four clock cycles in the destination clock
60366  * domain.
60367  *
60368  * Note that all MAC Address High registers (except MAC Address0 High) have the
60369  * same format.
60370  *
60371  * Register Layout
60372  *
60373  * Bits | Access | Reset | Description
60374  * :--------|:-------|:-------|:----------------------
60375  * [15:0] | RW | 0xffff | MAC Address63 [47:32]
60376  * [23:16] | ??? | 0x0 | *UNDEFINED*
60377  * [24] | RW | 0x0 | Mask Byte Control
60378  * [25] | RW | 0x0 | Mask Byte Control
60379  * [26] | RW | 0x0 | Mask Byte Control
60380  * [27] | RW | 0x0 | Mask Byte Control
60381  * [28] | RW | 0x0 | Mask Byte Control
60382  * [29] | RW | 0x0 | Mask Byte Control
60383  * [30] | RW | 0x0 | Source Address
60384  * [31] | RW | 0x0 | Address Enable
60385  *
60386  */
60387 /*
60388  * Field : MAC Address63 [47:32] - addrhi
60389  *
60390  * This field contains the upper 16 bits (47:32) of the 64th 6-byte MAC address.
60391  *
60392  * Field Access Macros:
60393  *
60394  */
60395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
60396 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_LSB 0
60397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
60398 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_MSB 15
60399 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
60400 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_WIDTH 16
60401 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
60402 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET_MSK 0x0000ffff
60403 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
60404 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_CLR_MSK 0xffff0000
60405 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
60406 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_RESET 0xffff
60407 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI field value from a register. */
60408 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60409 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value suitable for setting the register. */
60410 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60411 
60412 /*
60413  * Field : Mask Byte Control - mbc_0
60414  *
60415  * This array of bits are mask control bits for comparison of each of the MAC
60416  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60417  * received DA or SA with the contents of MAC Address63 high and low registers.
60418  * Each bit controls the masking of the bytes. You can filter a group of addresses
60419  * (known as group address filtering) by masking one or more bytes of the address.
60420  *
60421  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60422  *
60423  * Field Enumeration Values:
60424  *
60425  * Enum | Value | Description
60426  * :----------------------------------------------|:------|:------------------------------------
60427  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60428  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60429  *
60430  * Field Access Macros:
60431  *
60432  */
60433 /*
60434  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0
60435  *
60436  * Byte is unmasked (i.e. is compared)
60437  */
60438 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED 0x0
60439 /*
60440  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0
60441  *
60442  * Byte is masked (i.e. not compared)
60443  */
60444 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED 0x1
60445 
60446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
60447 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_LSB 24
60448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
60449 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_MSB 24
60450 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
60451 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_WIDTH 1
60452 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */
60453 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET_MSK 0x01000000
60454 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */
60455 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_CLR_MSK 0xfeffffff
60456 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
60457 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_RESET 0x0
60458 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 field value from a register. */
60459 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
60460 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value suitable for setting the register. */
60461 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
60462 
60463 /*
60464  * Field : Mask Byte Control - mbc_1
60465  *
60466  * This array of bits are mask control bits for comparison of each of the MAC
60467  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60468  * received DA or SA with the contents of MAC Address63 high and low registers.
60469  * Each bit controls the masking of the bytes. You can filter a group of addresses
60470  * (known as group address filtering) by masking one or more bytes of the address.
60471  *
60472  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60473  *
60474  * Field Enumeration Values:
60475  *
60476  * Enum | Value | Description
60477  * :----------------------------------------------|:------|:------------------------------------
60478  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60479  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60480  *
60481  * Field Access Macros:
60482  *
60483  */
60484 /*
60485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1
60486  *
60487  * Byte is unmasked (i.e. is compared)
60488  */
60489 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED 0x0
60490 /*
60491  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1
60492  *
60493  * Byte is masked (i.e. not compared)
60494  */
60495 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED 0x1
60496 
60497 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
60498 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_LSB 25
60499 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
60500 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_MSB 25
60501 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
60502 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_WIDTH 1
60503 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */
60504 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET_MSK 0x02000000
60505 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */
60506 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_CLR_MSK 0xfdffffff
60507 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
60508 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_RESET 0x0
60509 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 field value from a register. */
60510 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
60511 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value suitable for setting the register. */
60512 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
60513 
60514 /*
60515  * Field : Mask Byte Control - mbc_2
60516  *
60517  * This array of bits are mask control bits for comparison of each of the MAC
60518  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60519  * received DA or SA with the contents of MAC Address63 high and low registers.
60520  * Each bit controls the masking of the bytes. You can filter a group of addresses
60521  * (known as group address filtering) by masking one or more bytes of the address.
60522  *
60523  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60524  *
60525  * Field Enumeration Values:
60526  *
60527  * Enum | Value | Description
60528  * :----------------------------------------------|:------|:------------------------------------
60529  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60530  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60531  *
60532  * Field Access Macros:
60533  *
60534  */
60535 /*
60536  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2
60537  *
60538  * Byte is unmasked (i.e. is compared)
60539  */
60540 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED 0x0
60541 /*
60542  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2
60543  *
60544  * Byte is masked (i.e. not compared)
60545  */
60546 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED 0x1
60547 
60548 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
60549 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_LSB 26
60550 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
60551 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_MSB 26
60552 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
60553 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_WIDTH 1
60554 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */
60555 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET_MSK 0x04000000
60556 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */
60557 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_CLR_MSK 0xfbffffff
60558 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
60559 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_RESET 0x0
60560 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 field value from a register. */
60561 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
60562 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value suitable for setting the register. */
60563 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
60564 
60565 /*
60566  * Field : Mask Byte Control - mbc_3
60567  *
60568  * This array of bits are mask control bits for comparison of each of the MAC
60569  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60570  * received DA or SA with the contents of MAC Address63 high and low registers.
60571  * Each bit controls the masking of the bytes. You can filter a group of addresses
60572  * (known as group address filtering) by masking one or more bytes of the address.
60573  *
60574  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60575  *
60576  * Field Enumeration Values:
60577  *
60578  * Enum | Value | Description
60579  * :----------------------------------------------|:------|:------------------------------------
60580  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60581  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60582  *
60583  * Field Access Macros:
60584  *
60585  */
60586 /*
60587  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3
60588  *
60589  * Byte is unmasked (i.e. is compared)
60590  */
60591 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED 0x0
60592 /*
60593  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3
60594  *
60595  * Byte is masked (i.e. not compared)
60596  */
60597 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED 0x1
60598 
60599 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
60600 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_LSB 27
60601 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
60602 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_MSB 27
60603 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
60604 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_WIDTH 1
60605 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */
60606 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET_MSK 0x08000000
60607 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */
60608 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_CLR_MSK 0xf7ffffff
60609 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
60610 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_RESET 0x0
60611 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 field value from a register. */
60612 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
60613 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value suitable for setting the register. */
60614 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
60615 
60616 /*
60617  * Field : Mask Byte Control - mbc_4
60618  *
60619  * This array of bits are mask control bits for comparison of each of the MAC
60620  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60621  * received DA or SA with the contents of MAC Address63 high and low registers.
60622  * Each bit controls the masking of the bytes. You can filter a group of addresses
60623  * (known as group address filtering) by masking one or more bytes of the address.
60624  *
60625  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60626  *
60627  * Field Enumeration Values:
60628  *
60629  * Enum | Value | Description
60630  * :----------------------------------------------|:------|:------------------------------------
60631  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60632  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60633  *
60634  * Field Access Macros:
60635  *
60636  */
60637 /*
60638  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4
60639  *
60640  * Byte is unmasked (i.e. is compared)
60641  */
60642 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED 0x0
60643 /*
60644  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4
60645  *
60646  * Byte is masked (i.e. not compared)
60647  */
60648 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED 0x1
60649 
60650 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
60651 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_LSB 28
60652 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
60653 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_MSB 28
60654 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
60655 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_WIDTH 1
60656 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */
60657 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET_MSK 0x10000000
60658 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */
60659 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_CLR_MSK 0xefffffff
60660 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
60661 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_RESET 0x0
60662 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 field value from a register. */
60663 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
60664 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value suitable for setting the register. */
60665 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
60666 
60667 /*
60668  * Field : Mask Byte Control - mbc_5
60669  *
60670  * This array of bits are mask control bits for comparison of each of the MAC
60671  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60672  * received DA or SA with the contents of MAC Address63 high and low registers.
60673  * Each bit controls the masking of the bytes. You can filter a group of addresses
60674  * (known as group address filtering) by masking one or more bytes of the address.
60675  *
60676  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60677  *
60678  * Field Enumeration Values:
60679  *
60680  * Enum | Value | Description
60681  * :----------------------------------------------|:------|:------------------------------------
60682  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60683  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60684  *
60685  * Field Access Macros:
60686  *
60687  */
60688 /*
60689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5
60690  *
60691  * Byte is unmasked (i.e. is compared)
60692  */
60693 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED 0x0
60694 /*
60695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5
60696  *
60697  * Byte is masked (i.e. not compared)
60698  */
60699 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED 0x1
60700 
60701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
60702 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_LSB 29
60703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
60704 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_MSB 29
60705 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
60706 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_WIDTH 1
60707 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */
60708 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET_MSK 0x20000000
60709 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */
60710 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_CLR_MSK 0xdfffffff
60711 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
60712 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_RESET 0x0
60713 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 field value from a register. */
60714 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
60715 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value suitable for setting the register. */
60716 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
60717 
60718 /*
60719  * Field : Source Address - sa
60720  *
60721  * When this bit is enabled, the MAC Address63[47:0] is used to compare with the SA
60722  * fields of the received frame. When this bit is disabled, the MAC Address63[47:0]
60723  * is used to compare with the DA fields of the received frame.
60724  *
60725  * Field Enumeration Values:
60726  *
60727  * Enum | Value | Description
60728  * :----------------------------------------|:------|:-----------------------------
60729  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
60730  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END | 0x1 | MAC address compare enabled
60731  *
60732  * Field Access Macros:
60733  *
60734  */
60735 /*
60736  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA
60737  *
60738  * MAC address compare disabled
60739  */
60740 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD 0x0
60741 /*
60742  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA
60743  *
60744  * MAC address compare enabled
60745  */
60746 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END 0x1
60747 
60748 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
60749 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_LSB 30
60750 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
60751 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_MSB 30
60752 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
60753 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_WIDTH 1
60754 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */
60755 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET_MSK 0x40000000
60756 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */
60757 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_CLR_MSK 0xbfffffff
60758 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
60759 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_RESET 0x0
60760 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA field value from a register. */
60761 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
60762 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value suitable for setting the register. */
60763 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
60764 
60765 /*
60766  * Field : Address Enable - ae
60767  *
60768  * When this bit is enabled, the address filter block uses the 64th MAC address for
60769  * perfect filtering. When this bit is disabled, the address filter block ignores
60770  * the address for filtering.
60771  *
60772  * Field Enumeration Values:
60773  *
60774  * Enum | Value | Description
60775  * :----------------------------------------|:------|:--------------------------------------
60776  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
60777  * ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
60778  *
60779  * Field Access Macros:
60780  *
60781  */
60782 /*
60783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
60784  *
60785  * Second MAC address filtering disabled
60786  */
60787 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD 0x0
60788 /*
60789  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
60790  *
60791  * Second MAC address filtering enabled
60792  */
60793 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END 0x1
60794 
60795 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
60796 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_LSB 31
60797 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
60798 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_MSB 31
60799 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
60800 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_WIDTH 1
60801 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
60802 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET_MSK 0x80000000
60803 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
60804 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_CLR_MSK 0x7fffffff
60805 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
60806 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_RESET 0x0
60807 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE field value from a register. */
60808 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
60809 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value suitable for setting the register. */
60810 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
60811 
60812 #ifndef __ASSEMBLY__
60813 /*
60814  * WARNING: The C register and register group struct declarations are provided for
60815  * convenience and illustrative purposes. They should, however, be used with
60816  * caution as the C language standard provides no guarantees about the alignment or
60817  * atomicity of device memory accesses. The recommended practice for writing
60818  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60819  * alt_write_word() functions.
60820  *
60821  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH.
60822  */
60823 struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s
60824 {
60825  uint32_t addrhi : 16; /* MAC Address63 [47:32] */
60826  uint32_t : 8; /* *UNDEFINED* */
60827  uint32_t mbc_0 : 1; /* Mask Byte Control */
60828  uint32_t mbc_1 : 1; /* Mask Byte Control */
60829  uint32_t mbc_2 : 1; /* Mask Byte Control */
60830  uint32_t mbc_3 : 1; /* Mask Byte Control */
60831  uint32_t mbc_4 : 1; /* Mask Byte Control */
60832  uint32_t mbc_5 : 1; /* Mask Byte Control */
60833  uint32_t sa : 1; /* Source Address */
60834  uint32_t ae : 1; /* Address Enable */
60835 };
60836 
60837 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH. */
60838 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t;
60839 #endif /* __ASSEMBLY__ */
60840 
60841 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register from the beginning of the component. */
60842 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST 0x978
60843 /* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register. */
60844 #define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST))
60845 
60846 /*
60847  * Register : Register 607 (MAC Address63 Low Register) - MAC_Address63_Low
60848  *
60849  * The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC
60850  * address of the station.
60851  *
60852  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
60853  * format.
60854  *
60855  * Register Layout
60856  *
60857  * Bits | Access | Reset | Description
60858  * :-------|:-------|:-----------|:---------------------
60859  * [31:0] | RW | 0xffffffff | MAC Address63 [31:0]
60860  *
60861  */
60862 /*
60863  * Field : MAC Address63 [31:0] - addrlo
60864  *
60865  * This field contains the lower 32 bits of the 64th 6-byte MAC address. The
60866  * content of this field is undefined until loaded by software after the
60867  * initialization process.
60868  *
60869  * Field Access Macros:
60870  *
60871  */
60872 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
60873 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_LSB 0
60874 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
60875 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_MSB 31
60876 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
60877 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_WIDTH 32
60878 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
60879 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET_MSK 0xffffffff
60880 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
60881 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_CLR_MSK 0x00000000
60882 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
60883 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_RESET 0xffffffff
60884 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO field value from a register. */
60885 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
60886 /* Produces a ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value suitable for setting the register. */
60887 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
60888 
60889 #ifndef __ASSEMBLY__
60890 /*
60891  * WARNING: The C register and register group struct declarations are provided for
60892  * convenience and illustrative purposes. They should, however, be used with
60893  * caution as the C language standard provides no guarantees about the alignment or
60894  * atomicity of device memory accesses. The recommended practice for writing
60895  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
60896  * alt_write_word() functions.
60897  *
60898  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW.
60899  */
60900 struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s
60901 {
60902  uint32_t addrlo : 32; /* MAC Address63 [31:0] */
60903 };
60904 
60905 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW. */
60906 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s ALT_EMAC_GMAC_MAC_ADDR63_LOW_t;
60907 #endif /* __ASSEMBLY__ */
60908 
60909 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register from the beginning of the component. */
60910 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST 0x97c
60911 /* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register. */
60912 #define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST))
60913 
60914 /*
60915  * Register : Register 608 (MAC Address64 High Register) - MAC_Address64_High
60916  *
60917  * The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC
60918  * address of the station. Because the MAC address registers are configured to be
60919  * double-synchronized to the (G)MII clock domains, the synchronization is
60920  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
60921  * endian mode) of the MAC Address64 Low Register are written. For proper
60922  * synchronization updates, the consecutive writes to this Address Low Register
60923  * should be performed after at least four clock cycles in the destination clock
60924  * domain.
60925  *
60926  * Note that all MAC Address High registers (except MAC Address0 High) have the
60927  * same format.
60928  *
60929  * Register Layout
60930  *
60931  * Bits | Access | Reset | Description
60932  * :--------|:-------|:-------|:----------------------
60933  * [15:0] | RW | 0xffff | MAC Address64 [47:32]
60934  * [23:16] | ??? | 0x0 | *UNDEFINED*
60935  * [24] | RW | 0x0 | Mask Byte Control
60936  * [25] | RW | 0x0 | Mask Byte Control
60937  * [26] | RW | 0x0 | Mask Byte Control
60938  * [27] | RW | 0x0 | Mask Byte Control
60939  * [28] | RW | 0x0 | Mask Byte Control
60940  * [29] | RW | 0x0 | Mask Byte Control
60941  * [30] | RW | 0x0 | Source Address
60942  * [31] | RW | 0x0 | Address Enable
60943  *
60944  */
60945 /*
60946  * Field : MAC Address64 [47:32] - addrhi
60947  *
60948  * This field contains the upper 16 bits (47:32) of the 65th 6-byte MAC address.
60949  *
60950  * Field Access Macros:
60951  *
60952  */
60953 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
60954 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_LSB 0
60955 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
60956 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_MSB 15
60957 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
60958 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_WIDTH 16
60959 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
60960 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET_MSK 0x0000ffff
60961 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
60962 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_CLR_MSK 0xffff0000
60963 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
60964 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_RESET 0xffff
60965 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI field value from a register. */
60966 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
60967 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value suitable for setting the register. */
60968 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
60969 
60970 /*
60971  * Field : Mask Byte Control - mbc_0
60972  *
60973  * This array of bits are mask control bits for comparison of each of the MAC
60974  * Address bytes. When masked, the MAC does not compare the corresponding byte of
60975  * received DA or SA with the contents of MAC Address64 high and low registers.
60976  * Each bit controls the masking of the bytes. You can filter a group of addresses
60977  * (known as group address filtering) by masking one or more bytes of the address.
60978  *
60979  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
60980  *
60981  * Field Enumeration Values:
60982  *
60983  * Enum | Value | Description
60984  * :----------------------------------------------|:------|:------------------------------------
60985  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
60986  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
60987  *
60988  * Field Access Macros:
60989  *
60990  */
60991 /*
60992  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0
60993  *
60994  * Byte is unmasked (i.e. is compared)
60995  */
60996 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED 0x0
60997 /*
60998  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0
60999  *
61000  * Byte is masked (i.e. not compared)
61001  */
61002 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED 0x1
61003 
61004 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
61005 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_LSB 24
61006 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
61007 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_MSB 24
61008 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
61009 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_WIDTH 1
61010 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */
61011 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET_MSK 0x01000000
61012 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */
61013 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_CLR_MSK 0xfeffffff
61014 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
61015 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_RESET 0x0
61016 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 field value from a register. */
61017 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
61018 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value suitable for setting the register. */
61019 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
61020 
61021 /*
61022  * Field : Mask Byte Control - mbc_1
61023  *
61024  * This array of bits are mask control bits for comparison of each of the MAC
61025  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61026  * received DA or SA with the contents of MAC Address64 high and low registers.
61027  * Each bit controls the masking of the bytes. You can filter a group of addresses
61028  * (known as group address filtering) by masking one or more bytes of the address.
61029  *
61030  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61031  *
61032  * Field Enumeration Values:
61033  *
61034  * Enum | Value | Description
61035  * :----------------------------------------------|:------|:------------------------------------
61036  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61037  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61038  *
61039  * Field Access Macros:
61040  *
61041  */
61042 /*
61043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1
61044  *
61045  * Byte is unmasked (i.e. is compared)
61046  */
61047 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED 0x0
61048 /*
61049  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1
61050  *
61051  * Byte is masked (i.e. not compared)
61052  */
61053 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED 0x1
61054 
61055 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
61056 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_LSB 25
61057 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
61058 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_MSB 25
61059 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
61060 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_WIDTH 1
61061 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */
61062 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET_MSK 0x02000000
61063 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */
61064 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_CLR_MSK 0xfdffffff
61065 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
61066 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_RESET 0x0
61067 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 field value from a register. */
61068 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
61069 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value suitable for setting the register. */
61070 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
61071 
61072 /*
61073  * Field : Mask Byte Control - mbc_2
61074  *
61075  * This array of bits are mask control bits for comparison of each of the MAC
61076  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61077  * received DA or SA with the contents of MAC Address64 high and low registers.
61078  * Each bit controls the masking of the bytes. You can filter a group of addresses
61079  * (known as group address filtering) by masking one or more bytes of the address.
61080  *
61081  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61082  *
61083  * Field Enumeration Values:
61084  *
61085  * Enum | Value | Description
61086  * :----------------------------------------------|:------|:------------------------------------
61087  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61088  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61089  *
61090  * Field Access Macros:
61091  *
61092  */
61093 /*
61094  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2
61095  *
61096  * Byte is unmasked (i.e. is compared)
61097  */
61098 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED 0x0
61099 /*
61100  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2
61101  *
61102  * Byte is masked (i.e. not compared)
61103  */
61104 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED 0x1
61105 
61106 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
61107 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_LSB 26
61108 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
61109 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_MSB 26
61110 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
61111 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_WIDTH 1
61112 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */
61113 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET_MSK 0x04000000
61114 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */
61115 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_CLR_MSK 0xfbffffff
61116 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
61117 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_RESET 0x0
61118 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 field value from a register. */
61119 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
61120 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value suitable for setting the register. */
61121 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
61122 
61123 /*
61124  * Field : Mask Byte Control - mbc_3
61125  *
61126  * This array of bits are mask control bits for comparison of each of the MAC
61127  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61128  * received DA or SA with the contents of MAC Address64 high and low registers.
61129  * Each bit controls the masking of the bytes. You can filter a group of addresses
61130  * (known as group address filtering) by masking one or more bytes of the address.
61131  *
61132  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61133  *
61134  * Field Enumeration Values:
61135  *
61136  * Enum | Value | Description
61137  * :----------------------------------------------|:------|:------------------------------------
61138  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61139  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61140  *
61141  * Field Access Macros:
61142  *
61143  */
61144 /*
61145  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3
61146  *
61147  * Byte is unmasked (i.e. is compared)
61148  */
61149 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED 0x0
61150 /*
61151  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3
61152  *
61153  * Byte is masked (i.e. not compared)
61154  */
61155 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED 0x1
61156 
61157 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
61158 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_LSB 27
61159 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
61160 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_MSB 27
61161 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
61162 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_WIDTH 1
61163 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */
61164 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET_MSK 0x08000000
61165 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */
61166 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_CLR_MSK 0xf7ffffff
61167 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
61168 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_RESET 0x0
61169 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 field value from a register. */
61170 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
61171 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value suitable for setting the register. */
61172 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
61173 
61174 /*
61175  * Field : Mask Byte Control - mbc_4
61176  *
61177  * This array of bits are mask control bits for comparison of each of the MAC
61178  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61179  * received DA or SA with the contents of MAC Address64 high and low registers.
61180  * Each bit controls the masking of the bytes. You can filter a group of addresses
61181  * (known as group address filtering) by masking one or more bytes of the address.
61182  *
61183  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61184  *
61185  * Field Enumeration Values:
61186  *
61187  * Enum | Value | Description
61188  * :----------------------------------------------|:------|:------------------------------------
61189  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61190  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61191  *
61192  * Field Access Macros:
61193  *
61194  */
61195 /*
61196  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4
61197  *
61198  * Byte is unmasked (i.e. is compared)
61199  */
61200 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED 0x0
61201 /*
61202  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4
61203  *
61204  * Byte is masked (i.e. not compared)
61205  */
61206 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED 0x1
61207 
61208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
61209 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_LSB 28
61210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
61211 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_MSB 28
61212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
61213 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_WIDTH 1
61214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */
61215 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET_MSK 0x10000000
61216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */
61217 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_CLR_MSK 0xefffffff
61218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
61219 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_RESET 0x0
61220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 field value from a register. */
61221 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
61222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value suitable for setting the register. */
61223 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
61224 
61225 /*
61226  * Field : Mask Byte Control - mbc_5
61227  *
61228  * This array of bits are mask control bits for comparison of each of the MAC
61229  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61230  * received DA or SA with the contents of MAC Address64 high and low registers.
61231  * Each bit controls the masking of the bytes. You can filter a group of addresses
61232  * (known as group address filtering) by masking one or more bytes of the address.
61233  *
61234  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61235  *
61236  * Field Enumeration Values:
61237  *
61238  * Enum | Value | Description
61239  * :----------------------------------------------|:------|:------------------------------------
61240  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61241  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61242  *
61243  * Field Access Macros:
61244  *
61245  */
61246 /*
61247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5
61248  *
61249  * Byte is unmasked (i.e. is compared)
61250  */
61251 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED 0x0
61252 /*
61253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5
61254  *
61255  * Byte is masked (i.e. not compared)
61256  */
61257 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED 0x1
61258 
61259 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
61260 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_LSB 29
61261 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
61262 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_MSB 29
61263 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
61264 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_WIDTH 1
61265 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */
61266 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET_MSK 0x20000000
61267 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */
61268 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_CLR_MSK 0xdfffffff
61269 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
61270 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_RESET 0x0
61271 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 field value from a register. */
61272 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
61273 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value suitable for setting the register. */
61274 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
61275 
61276 /*
61277  * Field : Source Address - sa
61278  *
61279  * When this bit is enabled, the MAC Address64[47:0] is used to compare with the SA
61280  * fields of the received frame. When this bit is disabled, the MAC Address64[47:0]
61281  * is used to compare with the DA fields of the received frame.
61282  *
61283  * Field Enumeration Values:
61284  *
61285  * Enum | Value | Description
61286  * :----------------------------------------|:------|:-----------------------------
61287  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
61288  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END | 0x1 | MAC address compare enabled
61289  *
61290  * Field Access Macros:
61291  *
61292  */
61293 /*
61294  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA
61295  *
61296  * MAC address compare disabled
61297  */
61298 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD 0x0
61299 /*
61300  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA
61301  *
61302  * MAC address compare enabled
61303  */
61304 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END 0x1
61305 
61306 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
61307 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_LSB 30
61308 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
61309 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_MSB 30
61310 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
61311 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_WIDTH 1
61312 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */
61313 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET_MSK 0x40000000
61314 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */
61315 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_CLR_MSK 0xbfffffff
61316 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
61317 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_RESET 0x0
61318 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA field value from a register. */
61319 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
61320 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value suitable for setting the register. */
61321 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
61322 
61323 /*
61324  * Field : Address Enable - ae
61325  *
61326  * When this bit is enabled, the address filter block uses the 65th MAC address for
61327  * perfect filtering. When this bit is disabled, the address filter block ignores
61328  * the address for filtering.
61329  *
61330  * Field Enumeration Values:
61331  *
61332  * Enum | Value | Description
61333  * :----------------------------------------|:------|:--------------------------------------
61334  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
61335  * ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
61336  *
61337  * Field Access Macros:
61338  *
61339  */
61340 /*
61341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
61342  *
61343  * Second MAC address filtering disabled
61344  */
61345 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD 0x0
61346 /*
61347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
61348  *
61349  * Second MAC address filtering enabled
61350  */
61351 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END 0x1
61352 
61353 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
61354 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_LSB 31
61355 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
61356 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_MSB 31
61357 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
61358 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_WIDTH 1
61359 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
61360 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET_MSK 0x80000000
61361 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
61362 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_CLR_MSK 0x7fffffff
61363 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
61364 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_RESET 0x0
61365 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE field value from a register. */
61366 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61367 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value suitable for setting the register. */
61368 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61369 
61370 #ifndef __ASSEMBLY__
61371 /*
61372  * WARNING: The C register and register group struct declarations are provided for
61373  * convenience and illustrative purposes. They should, however, be used with
61374  * caution as the C language standard provides no guarantees about the alignment or
61375  * atomicity of device memory accesses. The recommended practice for writing
61376  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61377  * alt_write_word() functions.
61378  *
61379  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH.
61380  */
61381 struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s
61382 {
61383  uint32_t addrhi : 16; /* MAC Address64 [47:32] */
61384  uint32_t : 8; /* *UNDEFINED* */
61385  uint32_t mbc_0 : 1; /* Mask Byte Control */
61386  uint32_t mbc_1 : 1; /* Mask Byte Control */
61387  uint32_t mbc_2 : 1; /* Mask Byte Control */
61388  uint32_t mbc_3 : 1; /* Mask Byte Control */
61389  uint32_t mbc_4 : 1; /* Mask Byte Control */
61390  uint32_t mbc_5 : 1; /* Mask Byte Control */
61391  uint32_t sa : 1; /* Source Address */
61392  uint32_t ae : 1; /* Address Enable */
61393 };
61394 
61395 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH. */
61396 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t;
61397 #endif /* __ASSEMBLY__ */
61398 
61399 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register from the beginning of the component. */
61400 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST 0x980
61401 /* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register. */
61402 #define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST))
61403 
61404 /*
61405  * Register : Register 609 (MAC Address64 Low Register) - MAC_Address64_Low
61406  *
61407  * The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC
61408  * address of the station.
61409  *
61410  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
61411  * format.
61412  *
61413  * Register Layout
61414  *
61415  * Bits | Access | Reset | Description
61416  * :-------|:-------|:-----------|:---------------------
61417  * [31:0] | RW | 0xffffffff | MAC Address64 [31:0]
61418  *
61419  */
61420 /*
61421  * Field : MAC Address64 [31:0] - addrlo
61422  *
61423  * This field contains the lower 32 bits of the 65th 6-byte MAC address. The
61424  * content of this field is undefined until loaded by software after the
61425  * initialization process.
61426  *
61427  * Field Access Macros:
61428  *
61429  */
61430 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
61431 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_LSB 0
61432 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
61433 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_MSB 31
61434 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
61435 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_WIDTH 32
61436 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
61437 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET_MSK 0xffffffff
61438 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
61439 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_CLR_MSK 0x00000000
61440 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
61441 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_RESET 0xffffffff
61442 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO field value from a register. */
61443 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
61444 /* Produces a ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value suitable for setting the register. */
61445 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
61446 
61447 #ifndef __ASSEMBLY__
61448 /*
61449  * WARNING: The C register and register group struct declarations are provided for
61450  * convenience and illustrative purposes. They should, however, be used with
61451  * caution as the C language standard provides no guarantees about the alignment or
61452  * atomicity of device memory accesses. The recommended practice for writing
61453  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61454  * alt_write_word() functions.
61455  *
61456  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW.
61457  */
61458 struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s
61459 {
61460  uint32_t addrlo : 32; /* MAC Address64 [31:0] */
61461 };
61462 
61463 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW. */
61464 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s ALT_EMAC_GMAC_MAC_ADDR64_LOW_t;
61465 #endif /* __ASSEMBLY__ */
61466 
61467 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register from the beginning of the component. */
61468 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST 0x984
61469 /* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register. */
61470 #define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST))
61471 
61472 /*
61473  * Register : Register 610 (MAC Address65 High Register) - MAC_Address65_High
61474  *
61475  * The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC
61476  * address of the station. Because the MAC address registers are configured to be
61477  * double-synchronized to the (G)MII clock domains, the synchronization is
61478  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
61479  * endian mode) of the MAC Address65 Low Register are written. For proper
61480  * synchronization updates, the consecutive writes to this Address Low Register
61481  * should be performed after at least four clock cycles in the destination clock
61482  * domain.
61483  *
61484  * Note that all MAC Address High registers (except MAC Address0 High) have the
61485  * same format.
61486  *
61487  * Register Layout
61488  *
61489  * Bits | Access | Reset | Description
61490  * :--------|:-------|:-------|:----------------------
61491  * [15:0] | RW | 0xffff | MAC Address65 [47:32]
61492  * [23:16] | ??? | 0x0 | *UNDEFINED*
61493  * [24] | RW | 0x0 | Mask Byte Control
61494  * [25] | RW | 0x0 | Mask Byte Control
61495  * [26] | RW | 0x0 | Mask Byte Control
61496  * [27] | RW | 0x0 | Mask Byte Control
61497  * [28] | RW | 0x0 | Mask Byte Control
61498  * [29] | RW | 0x0 | Mask Byte Control
61499  * [30] | RW | 0x0 | Source Address
61500  * [31] | RW | 0x0 | Address Enable
61501  *
61502  */
61503 /*
61504  * Field : MAC Address65 [47:32] - addrhi
61505  *
61506  * This field contains the upper 16 bits (47:32) of the 66th 6-byte MAC address.
61507  *
61508  * Field Access Macros:
61509  *
61510  */
61511 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
61512 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_LSB 0
61513 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
61514 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_MSB 15
61515 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
61516 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_WIDTH 16
61517 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
61518 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET_MSK 0x0000ffff
61519 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
61520 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_CLR_MSK 0xffff0000
61521 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
61522 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_RESET 0xffff
61523 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI field value from a register. */
61524 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
61525 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value suitable for setting the register. */
61526 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
61527 
61528 /*
61529  * Field : Mask Byte Control - mbc_0
61530  *
61531  * This array of bits are mask control bits for comparison of each of the MAC
61532  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61533  * received DA or SA with the contents of MAC Address65 high and low registers.
61534  * Each bit controls the masking of the bytes. You can filter a group of addresses
61535  * (known as group address filtering) by masking one or more bytes of the address.
61536  *
61537  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61538  *
61539  * Field Enumeration Values:
61540  *
61541  * Enum | Value | Description
61542  * :----------------------------------------------|:------|:------------------------------------
61543  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61544  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61545  *
61546  * Field Access Macros:
61547  *
61548  */
61549 /*
61550  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0
61551  *
61552  * Byte is unmasked (i.e. is compared)
61553  */
61554 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED 0x0
61555 /*
61556  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0
61557  *
61558  * Byte is masked (i.e. not compared)
61559  */
61560 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED 0x1
61561 
61562 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
61563 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_LSB 24
61564 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
61565 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_MSB 24
61566 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
61567 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_WIDTH 1
61568 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */
61569 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET_MSK 0x01000000
61570 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */
61571 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_CLR_MSK 0xfeffffff
61572 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
61573 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_RESET 0x0
61574 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 field value from a register. */
61575 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
61576 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value suitable for setting the register. */
61577 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
61578 
61579 /*
61580  * Field : Mask Byte Control - mbc_1
61581  *
61582  * This array of bits are mask control bits for comparison of each of the MAC
61583  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61584  * received DA or SA with the contents of MAC Address65 high and low registers.
61585  * Each bit controls the masking of the bytes. You can filter a group of addresses
61586  * (known as group address filtering) by masking one or more bytes of the address.
61587  *
61588  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61589  *
61590  * Field Enumeration Values:
61591  *
61592  * Enum | Value | Description
61593  * :----------------------------------------------|:------|:------------------------------------
61594  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61595  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61596  *
61597  * Field Access Macros:
61598  *
61599  */
61600 /*
61601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1
61602  *
61603  * Byte is unmasked (i.e. is compared)
61604  */
61605 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED 0x0
61606 /*
61607  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1
61608  *
61609  * Byte is masked (i.e. not compared)
61610  */
61611 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED 0x1
61612 
61613 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
61614 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_LSB 25
61615 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
61616 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_MSB 25
61617 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
61618 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_WIDTH 1
61619 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */
61620 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET_MSK 0x02000000
61621 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */
61622 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_CLR_MSK 0xfdffffff
61623 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
61624 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_RESET 0x0
61625 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 field value from a register. */
61626 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
61627 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value suitable for setting the register. */
61628 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
61629 
61630 /*
61631  * Field : Mask Byte Control - mbc_2
61632  *
61633  * This array of bits are mask control bits for comparison of each of the MAC
61634  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61635  * received DA or SA with the contents of MAC Address65 high and low registers.
61636  * Each bit controls the masking of the bytes. You can filter a group of addresses
61637  * (known as group address filtering) by masking one or more bytes of the address.
61638  *
61639  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61640  *
61641  * Field Enumeration Values:
61642  *
61643  * Enum | Value | Description
61644  * :----------------------------------------------|:------|:------------------------------------
61645  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61646  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61647  *
61648  * Field Access Macros:
61649  *
61650  */
61651 /*
61652  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2
61653  *
61654  * Byte is unmasked (i.e. is compared)
61655  */
61656 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED 0x0
61657 /*
61658  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2
61659  *
61660  * Byte is masked (i.e. not compared)
61661  */
61662 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED 0x1
61663 
61664 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
61665 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_LSB 26
61666 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
61667 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_MSB 26
61668 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
61669 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_WIDTH 1
61670 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */
61671 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET_MSK 0x04000000
61672 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */
61673 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_CLR_MSK 0xfbffffff
61674 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
61675 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_RESET 0x0
61676 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 field value from a register. */
61677 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
61678 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value suitable for setting the register. */
61679 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
61680 
61681 /*
61682  * Field : Mask Byte Control - mbc_3
61683  *
61684  * This array of bits are mask control bits for comparison of each of the MAC
61685  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61686  * received DA or SA with the contents of MAC Address65 high and low registers.
61687  * Each bit controls the masking of the bytes. You can filter a group of addresses
61688  * (known as group address filtering) by masking one or more bytes of the address.
61689  *
61690  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61691  *
61692  * Field Enumeration Values:
61693  *
61694  * Enum | Value | Description
61695  * :----------------------------------------------|:------|:------------------------------------
61696  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61697  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61698  *
61699  * Field Access Macros:
61700  *
61701  */
61702 /*
61703  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3
61704  *
61705  * Byte is unmasked (i.e. is compared)
61706  */
61707 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED 0x0
61708 /*
61709  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3
61710  *
61711  * Byte is masked (i.e. not compared)
61712  */
61713 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED 0x1
61714 
61715 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
61716 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_LSB 27
61717 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
61718 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_MSB 27
61719 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
61720 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_WIDTH 1
61721 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */
61722 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET_MSK 0x08000000
61723 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */
61724 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_CLR_MSK 0xf7ffffff
61725 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
61726 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_RESET 0x0
61727 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 field value from a register. */
61728 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
61729 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value suitable for setting the register. */
61730 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
61731 
61732 /*
61733  * Field : Mask Byte Control - mbc_4
61734  *
61735  * This array of bits are mask control bits for comparison of each of the MAC
61736  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61737  * received DA or SA with the contents of MAC Address65 high and low registers.
61738  * Each bit controls the masking of the bytes. You can filter a group of addresses
61739  * (known as group address filtering) by masking one or more bytes of the address.
61740  *
61741  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61742  *
61743  * Field Enumeration Values:
61744  *
61745  * Enum | Value | Description
61746  * :----------------------------------------------|:------|:------------------------------------
61747  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61748  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61749  *
61750  * Field Access Macros:
61751  *
61752  */
61753 /*
61754  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4
61755  *
61756  * Byte is unmasked (i.e. is compared)
61757  */
61758 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED 0x0
61759 /*
61760  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4
61761  *
61762  * Byte is masked (i.e. not compared)
61763  */
61764 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED 0x1
61765 
61766 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
61767 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_LSB 28
61768 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
61769 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_MSB 28
61770 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
61771 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_WIDTH 1
61772 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */
61773 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET_MSK 0x10000000
61774 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */
61775 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_CLR_MSK 0xefffffff
61776 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
61777 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_RESET 0x0
61778 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 field value from a register. */
61779 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
61780 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value suitable for setting the register. */
61781 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
61782 
61783 /*
61784  * Field : Mask Byte Control - mbc_5
61785  *
61786  * This array of bits are mask control bits for comparison of each of the MAC
61787  * Address bytes. When masked, the MAC does not compare the corresponding byte of
61788  * received DA or SA with the contents of MAC Address65 high and low registers.
61789  * Each bit controls the masking of the bytes. You can filter a group of addresses
61790  * (known as group address filtering) by masking one or more bytes of the address.
61791  *
61792  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
61793  *
61794  * Field Enumeration Values:
61795  *
61796  * Enum | Value | Description
61797  * :----------------------------------------------|:------|:------------------------------------
61798  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
61799  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
61800  *
61801  * Field Access Macros:
61802  *
61803  */
61804 /*
61805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5
61806  *
61807  * Byte is unmasked (i.e. is compared)
61808  */
61809 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED 0x0
61810 /*
61811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5
61812  *
61813  * Byte is masked (i.e. not compared)
61814  */
61815 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED 0x1
61816 
61817 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
61818 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_LSB 29
61819 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
61820 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_MSB 29
61821 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
61822 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_WIDTH 1
61823 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */
61824 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET_MSK 0x20000000
61825 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */
61826 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_CLR_MSK 0xdfffffff
61827 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
61828 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_RESET 0x0
61829 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 field value from a register. */
61830 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
61831 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value suitable for setting the register. */
61832 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
61833 
61834 /*
61835  * Field : Source Address - sa
61836  *
61837  * When this bit is enabled, the MAC Address65[47:0] is used to compare with the SA
61838  * fields of the received frame. When this bit is disabled, the MAC Address65[47:0]
61839  * is used to compare with the DA fields of the received frame.
61840  *
61841  * Field Enumeration Values:
61842  *
61843  * Enum | Value | Description
61844  * :----------------------------------------|:------|:-----------------------------
61845  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
61846  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END | 0x1 | MAC address compare enabled
61847  *
61848  * Field Access Macros:
61849  *
61850  */
61851 /*
61852  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA
61853  *
61854  * MAC address compare disabled
61855  */
61856 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD 0x0
61857 /*
61858  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA
61859  *
61860  * MAC address compare enabled
61861  */
61862 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END 0x1
61863 
61864 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
61865 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_LSB 30
61866 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
61867 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_MSB 30
61868 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
61869 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_WIDTH 1
61870 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */
61871 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET_MSK 0x40000000
61872 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */
61873 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_CLR_MSK 0xbfffffff
61874 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
61875 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_RESET 0x0
61876 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA field value from a register. */
61877 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
61878 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value suitable for setting the register. */
61879 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
61880 
61881 /*
61882  * Field : Address Enable - ae
61883  *
61884  * When this bit is enabled, the address filter block uses the 66th MAC address for
61885  * perfect filtering. When this bit is disabled, the address filter block ignores
61886  * the address for filtering.
61887  *
61888  * Field Enumeration Values:
61889  *
61890  * Enum | Value | Description
61891  * :----------------------------------------|:------|:--------------------------------------
61892  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
61893  * ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
61894  *
61895  * Field Access Macros:
61896  *
61897  */
61898 /*
61899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
61900  *
61901  * Second MAC address filtering disabled
61902  */
61903 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD 0x0
61904 /*
61905  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
61906  *
61907  * Second MAC address filtering enabled
61908  */
61909 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END 0x1
61910 
61911 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
61912 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_LSB 31
61913 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
61914 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_MSB 31
61915 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
61916 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_WIDTH 1
61917 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
61918 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET_MSK 0x80000000
61919 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
61920 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_CLR_MSK 0x7fffffff
61921 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
61922 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_RESET 0x0
61923 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE field value from a register. */
61924 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
61925 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value suitable for setting the register. */
61926 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
61927 
61928 #ifndef __ASSEMBLY__
61929 /*
61930  * WARNING: The C register and register group struct declarations are provided for
61931  * convenience and illustrative purposes. They should, however, be used with
61932  * caution as the C language standard provides no guarantees about the alignment or
61933  * atomicity of device memory accesses. The recommended practice for writing
61934  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
61935  * alt_write_word() functions.
61936  *
61937  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH.
61938  */
61939 struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s
61940 {
61941  uint32_t addrhi : 16; /* MAC Address65 [47:32] */
61942  uint32_t : 8; /* *UNDEFINED* */
61943  uint32_t mbc_0 : 1; /* Mask Byte Control */
61944  uint32_t mbc_1 : 1; /* Mask Byte Control */
61945  uint32_t mbc_2 : 1; /* Mask Byte Control */
61946  uint32_t mbc_3 : 1; /* Mask Byte Control */
61947  uint32_t mbc_4 : 1; /* Mask Byte Control */
61948  uint32_t mbc_5 : 1; /* Mask Byte Control */
61949  uint32_t sa : 1; /* Source Address */
61950  uint32_t ae : 1; /* Address Enable */
61951 };
61952 
61953 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH. */
61954 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t;
61955 #endif /* __ASSEMBLY__ */
61956 
61957 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register from the beginning of the component. */
61958 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST 0x988
61959 /* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register. */
61960 #define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST))
61961 
61962 /*
61963  * Register : Register 611 (MAC Address65 Low Register) - MAC_Address65_Low
61964  *
61965  * The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC
61966  * address of the station.
61967  *
61968  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
61969  * format.
61970  *
61971  * Register Layout
61972  *
61973  * Bits | Access | Reset | Description
61974  * :-------|:-------|:-----------|:---------------------
61975  * [31:0] | RW | 0xffffffff | MAC Address65 [31:0]
61976  *
61977  */
61978 /*
61979  * Field : MAC Address65 [31:0] - addrlo
61980  *
61981  * This field contains the lower 32 bits of the 66th 6-byte MAC address. The
61982  * content of this field is undefined until loaded by software after the
61983  * initialization process.
61984  *
61985  * Field Access Macros:
61986  *
61987  */
61988 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
61989 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_LSB 0
61990 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
61991 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_MSB 31
61992 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
61993 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_WIDTH 32
61994 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
61995 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET_MSK 0xffffffff
61996 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
61997 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_CLR_MSK 0x00000000
61998 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
61999 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_RESET 0xffffffff
62000 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO field value from a register. */
62001 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62002 /* Produces a ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value suitable for setting the register. */
62003 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62004 
62005 #ifndef __ASSEMBLY__
62006 /*
62007  * WARNING: The C register and register group struct declarations are provided for
62008  * convenience and illustrative purposes. They should, however, be used with
62009  * caution as the C language standard provides no guarantees about the alignment or
62010  * atomicity of device memory accesses. The recommended practice for writing
62011  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62012  * alt_write_word() functions.
62013  *
62014  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW.
62015  */
62016 struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s
62017 {
62018  uint32_t addrlo : 32; /* MAC Address65 [31:0] */
62019 };
62020 
62021 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW. */
62022 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s ALT_EMAC_GMAC_MAC_ADDR65_LOW_t;
62023 #endif /* __ASSEMBLY__ */
62024 
62025 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register from the beginning of the component. */
62026 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST 0x98c
62027 /* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register. */
62028 #define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST))
62029 
62030 /*
62031  * Register : Register 612 (MAC Address66 High Register) - MAC_Address66_High
62032  *
62033  * The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC
62034  * address of the station. Because the MAC address registers are configured to be
62035  * double-synchronized to the (G)MII clock domains, the synchronization is
62036  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
62037  * endian mode) of the MAC Address66 Low Register are written. For proper
62038  * synchronization updates, the consecutive writes to this Address Low Register
62039  * should be performed after at least four clock cycles in the destination clock
62040  * domain.
62041  *
62042  * Note that all MAC Address High registers (except MAC Address0 High) have the
62043  * same format.
62044  *
62045  * Register Layout
62046  *
62047  * Bits | Access | Reset | Description
62048  * :--------|:-------|:-------|:----------------------
62049  * [15:0] | RW | 0xffff | MAC Address66 [47:32]
62050  * [23:16] | ??? | 0x0 | *UNDEFINED*
62051  * [24] | RW | 0x0 | Mask Byte Control
62052  * [25] | RW | 0x0 | Mask Byte Control
62053  * [26] | RW | 0x0 | Mask Byte Control
62054  * [27] | RW | 0x0 | Mask Byte Control
62055  * [28] | RW | 0x0 | Mask Byte Control
62056  * [29] | RW | 0x0 | Mask Byte Control
62057  * [30] | RW | 0x0 | Source Address
62058  * [31] | RW | 0x0 | Address Enable
62059  *
62060  */
62061 /*
62062  * Field : MAC Address66 [47:32] - addrhi
62063  *
62064  * This field contains the upper 16 bits (47:32) of the 67th 6-byte MAC address.
62065  *
62066  * Field Access Macros:
62067  *
62068  */
62069 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
62070 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_LSB 0
62071 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
62072 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_MSB 15
62073 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
62074 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_WIDTH 16
62075 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
62076 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET_MSK 0x0000ffff
62077 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
62078 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_CLR_MSK 0xffff0000
62079 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
62080 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_RESET 0xffff
62081 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI field value from a register. */
62082 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62083 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value suitable for setting the register. */
62084 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62085 
62086 /*
62087  * Field : Mask Byte Control - mbc_0
62088  *
62089  * This array of bits are mask control bits for comparison of each of the MAC
62090  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62091  * received DA or SA with the contents of MAC Address66 high and low registers.
62092  * Each bit controls the masking of the bytes. You can filter a group of addresses
62093  * (known as group address filtering) by masking one or more bytes of the address.
62094  *
62095  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62096  *
62097  * Field Enumeration Values:
62098  *
62099  * Enum | Value | Description
62100  * :----------------------------------------------|:------|:------------------------------------
62101  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62102  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62103  *
62104  * Field Access Macros:
62105  *
62106  */
62107 /*
62108  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0
62109  *
62110  * Byte is unmasked (i.e. is compared)
62111  */
62112 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED 0x0
62113 /*
62114  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0
62115  *
62116  * Byte is masked (i.e. not compared)
62117  */
62118 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED 0x1
62119 
62120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
62121 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_LSB 24
62122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
62123 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_MSB 24
62124 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
62125 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_WIDTH 1
62126 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */
62127 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET_MSK 0x01000000
62128 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */
62129 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_CLR_MSK 0xfeffffff
62130 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
62131 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_RESET 0x0
62132 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 field value from a register. */
62133 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
62134 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value suitable for setting the register. */
62135 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
62136 
62137 /*
62138  * Field : Mask Byte Control - mbc_1
62139  *
62140  * This array of bits are mask control bits for comparison of each of the MAC
62141  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62142  * received DA or SA with the contents of MAC Address66 high and low registers.
62143  * Each bit controls the masking of the bytes. You can filter a group of addresses
62144  * (known as group address filtering) by masking one or more bytes of the address.
62145  *
62146  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62147  *
62148  * Field Enumeration Values:
62149  *
62150  * Enum | Value | Description
62151  * :----------------------------------------------|:------|:------------------------------------
62152  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62153  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62154  *
62155  * Field Access Macros:
62156  *
62157  */
62158 /*
62159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1
62160  *
62161  * Byte is unmasked (i.e. is compared)
62162  */
62163 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED 0x0
62164 /*
62165  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1
62166  *
62167  * Byte is masked (i.e. not compared)
62168  */
62169 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED 0x1
62170 
62171 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
62172 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_LSB 25
62173 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
62174 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_MSB 25
62175 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
62176 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_WIDTH 1
62177 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */
62178 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET_MSK 0x02000000
62179 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */
62180 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_CLR_MSK 0xfdffffff
62181 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
62182 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_RESET 0x0
62183 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 field value from a register. */
62184 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
62185 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value suitable for setting the register. */
62186 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
62187 
62188 /*
62189  * Field : Mask Byte Control - mbc_2
62190  *
62191  * This array of bits are mask control bits for comparison of each of the MAC
62192  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62193  * received DA or SA with the contents of MAC Address66 high and low registers.
62194  * Each bit controls the masking of the bytes. You can filter a group of addresses
62195  * (known as group address filtering) by masking one or more bytes of the address.
62196  *
62197  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62198  *
62199  * Field Enumeration Values:
62200  *
62201  * Enum | Value | Description
62202  * :----------------------------------------------|:------|:------------------------------------
62203  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62204  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62205  *
62206  * Field Access Macros:
62207  *
62208  */
62209 /*
62210  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2
62211  *
62212  * Byte is unmasked (i.e. is compared)
62213  */
62214 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED 0x0
62215 /*
62216  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2
62217  *
62218  * Byte is masked (i.e. not compared)
62219  */
62220 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED 0x1
62221 
62222 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
62223 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_LSB 26
62224 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
62225 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_MSB 26
62226 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
62227 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_WIDTH 1
62228 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */
62229 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET_MSK 0x04000000
62230 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */
62231 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_CLR_MSK 0xfbffffff
62232 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
62233 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_RESET 0x0
62234 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 field value from a register. */
62235 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
62236 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value suitable for setting the register. */
62237 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
62238 
62239 /*
62240  * Field : Mask Byte Control - mbc_3
62241  *
62242  * This array of bits are mask control bits for comparison of each of the MAC
62243  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62244  * received DA or SA with the contents of MAC Address66 high and low registers.
62245  * Each bit controls the masking of the bytes. You can filter a group of addresses
62246  * (known as group address filtering) by masking one or more bytes of the address.
62247  *
62248  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62249  *
62250  * Field Enumeration Values:
62251  *
62252  * Enum | Value | Description
62253  * :----------------------------------------------|:------|:------------------------------------
62254  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62255  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62256  *
62257  * Field Access Macros:
62258  *
62259  */
62260 /*
62261  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3
62262  *
62263  * Byte is unmasked (i.e. is compared)
62264  */
62265 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED 0x0
62266 /*
62267  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3
62268  *
62269  * Byte is masked (i.e. not compared)
62270  */
62271 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED 0x1
62272 
62273 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
62274 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_LSB 27
62275 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
62276 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_MSB 27
62277 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
62278 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_WIDTH 1
62279 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */
62280 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET_MSK 0x08000000
62281 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */
62282 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_CLR_MSK 0xf7ffffff
62283 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
62284 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_RESET 0x0
62285 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 field value from a register. */
62286 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
62287 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value suitable for setting the register. */
62288 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
62289 
62290 /*
62291  * Field : Mask Byte Control - mbc_4
62292  *
62293  * This array of bits are mask control bits for comparison of each of the MAC
62294  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62295  * received DA or SA with the contents of MAC Address66 high and low registers.
62296  * Each bit controls the masking of the bytes. You can filter a group of addresses
62297  * (known as group address filtering) by masking one or more bytes of the address.
62298  *
62299  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62300  *
62301  * Field Enumeration Values:
62302  *
62303  * Enum | Value | Description
62304  * :----------------------------------------------|:------|:------------------------------------
62305  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62306  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62307  *
62308  * Field Access Macros:
62309  *
62310  */
62311 /*
62312  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4
62313  *
62314  * Byte is unmasked (i.e. is compared)
62315  */
62316 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED 0x0
62317 /*
62318  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4
62319  *
62320  * Byte is masked (i.e. not compared)
62321  */
62322 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED 0x1
62323 
62324 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
62325 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_LSB 28
62326 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
62327 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_MSB 28
62328 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
62329 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_WIDTH 1
62330 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */
62331 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET_MSK 0x10000000
62332 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */
62333 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_CLR_MSK 0xefffffff
62334 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
62335 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_RESET 0x0
62336 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 field value from a register. */
62337 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
62338 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value suitable for setting the register. */
62339 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
62340 
62341 /*
62342  * Field : Mask Byte Control - mbc_5
62343  *
62344  * This array of bits are mask control bits for comparison of each of the MAC
62345  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62346  * received DA or SA with the contents of MAC Address66 high and low registers.
62347  * Each bit controls the masking of the bytes. You can filter a group of addresses
62348  * (known as group address filtering) by masking one or more bytes of the address.
62349  *
62350  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62351  *
62352  * Field Enumeration Values:
62353  *
62354  * Enum | Value | Description
62355  * :----------------------------------------------|:------|:------------------------------------
62356  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62357  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62358  *
62359  * Field Access Macros:
62360  *
62361  */
62362 /*
62363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5
62364  *
62365  * Byte is unmasked (i.e. is compared)
62366  */
62367 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED 0x0
62368 /*
62369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5
62370  *
62371  * Byte is masked (i.e. not compared)
62372  */
62373 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED 0x1
62374 
62375 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
62376 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_LSB 29
62377 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
62378 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_MSB 29
62379 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
62380 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_WIDTH 1
62381 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */
62382 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET_MSK 0x20000000
62383 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */
62384 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_CLR_MSK 0xdfffffff
62385 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
62386 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_RESET 0x0
62387 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 field value from a register. */
62388 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
62389 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value suitable for setting the register. */
62390 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
62391 
62392 /*
62393  * Field : Source Address - sa
62394  *
62395  * When this bit is enabled, the MAC Address66[47:0] is used to compare with the SA
62396  * fields of the received frame. When this bit is disabled, the MAC Address66[47:0]
62397  * is used to compare with the DA fields of the received frame.
62398  *
62399  * Field Enumeration Values:
62400  *
62401  * Enum | Value | Description
62402  * :----------------------------------------|:------|:-----------------------------
62403  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
62404  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END | 0x1 | MAC address compare enabled
62405  *
62406  * Field Access Macros:
62407  *
62408  */
62409 /*
62410  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA
62411  *
62412  * MAC address compare disabled
62413  */
62414 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD 0x0
62415 /*
62416  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA
62417  *
62418  * MAC address compare enabled
62419  */
62420 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END 0x1
62421 
62422 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
62423 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_LSB 30
62424 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
62425 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_MSB 30
62426 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
62427 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_WIDTH 1
62428 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */
62429 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET_MSK 0x40000000
62430 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */
62431 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_CLR_MSK 0xbfffffff
62432 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
62433 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_RESET 0x0
62434 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA field value from a register. */
62435 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
62436 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value suitable for setting the register. */
62437 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
62438 
62439 /*
62440  * Field : Address Enable - ae
62441  *
62442  * When this bit is enabled, the address filter block uses the 67th MAC address for
62443  * perfect filtering. When this bit is disabled, the address filter block ignores
62444  * the address for filtering.
62445  *
62446  * Field Enumeration Values:
62447  *
62448  * Enum | Value | Description
62449  * :----------------------------------------|:------|:--------------------------------------
62450  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
62451  * ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
62452  *
62453  * Field Access Macros:
62454  *
62455  */
62456 /*
62457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
62458  *
62459  * Second MAC address filtering disabled
62460  */
62461 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD 0x0
62462 /*
62463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
62464  *
62465  * Second MAC address filtering enabled
62466  */
62467 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END 0x1
62468 
62469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
62470 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_LSB 31
62471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
62472 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_MSB 31
62473 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
62474 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_WIDTH 1
62475 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
62476 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET_MSK 0x80000000
62477 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
62478 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_CLR_MSK 0x7fffffff
62479 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
62480 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_RESET 0x0
62481 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE field value from a register. */
62482 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
62483 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value suitable for setting the register. */
62484 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
62485 
62486 #ifndef __ASSEMBLY__
62487 /*
62488  * WARNING: The C register and register group struct declarations are provided for
62489  * convenience and illustrative purposes. They should, however, be used with
62490  * caution as the C language standard provides no guarantees about the alignment or
62491  * atomicity of device memory accesses. The recommended practice for writing
62492  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62493  * alt_write_word() functions.
62494  *
62495  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH.
62496  */
62497 struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s
62498 {
62499  uint32_t addrhi : 16; /* MAC Address66 [47:32] */
62500  uint32_t : 8; /* *UNDEFINED* */
62501  uint32_t mbc_0 : 1; /* Mask Byte Control */
62502  uint32_t mbc_1 : 1; /* Mask Byte Control */
62503  uint32_t mbc_2 : 1; /* Mask Byte Control */
62504  uint32_t mbc_3 : 1; /* Mask Byte Control */
62505  uint32_t mbc_4 : 1; /* Mask Byte Control */
62506  uint32_t mbc_5 : 1; /* Mask Byte Control */
62507  uint32_t sa : 1; /* Source Address */
62508  uint32_t ae : 1; /* Address Enable */
62509 };
62510 
62511 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH. */
62512 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t;
62513 #endif /* __ASSEMBLY__ */
62514 
62515 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register from the beginning of the component. */
62516 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST 0x990
62517 /* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register. */
62518 #define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST))
62519 
62520 /*
62521  * Register : Register 613 (MAC Address66 Low Register) - MAC_Address66_Low
62522  *
62523  * The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC
62524  * address of the station.
62525  *
62526  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
62527  * format.
62528  *
62529  * Register Layout
62530  *
62531  * Bits | Access | Reset | Description
62532  * :-------|:-------|:-----------|:---------------------
62533  * [31:0] | RW | 0xffffffff | MAC Address66 [31:0]
62534  *
62535  */
62536 /*
62537  * Field : MAC Address66 [31:0] - addrlo
62538  *
62539  * This field contains the lower 32 bits of the 67th 6-byte MAC address. The
62540  * content of this field is undefined until loaded by software after the
62541  * initialization process.
62542  *
62543  * Field Access Macros:
62544  *
62545  */
62546 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
62547 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_LSB 0
62548 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
62549 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_MSB 31
62550 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
62551 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_WIDTH 32
62552 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
62553 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET_MSK 0xffffffff
62554 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
62555 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_CLR_MSK 0x00000000
62556 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
62557 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_RESET 0xffffffff
62558 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO field value from a register. */
62559 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
62560 /* Produces a ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value suitable for setting the register. */
62561 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
62562 
62563 #ifndef __ASSEMBLY__
62564 /*
62565  * WARNING: The C register and register group struct declarations are provided for
62566  * convenience and illustrative purposes. They should, however, be used with
62567  * caution as the C language standard provides no guarantees about the alignment or
62568  * atomicity of device memory accesses. The recommended practice for writing
62569  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
62570  * alt_write_word() functions.
62571  *
62572  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW.
62573  */
62574 struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s
62575 {
62576  uint32_t addrlo : 32; /* MAC Address66 [31:0] */
62577 };
62578 
62579 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW. */
62580 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s ALT_EMAC_GMAC_MAC_ADDR66_LOW_t;
62581 #endif /* __ASSEMBLY__ */
62582 
62583 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register from the beginning of the component. */
62584 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST 0x994
62585 /* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register. */
62586 #define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST))
62587 
62588 /*
62589  * Register : Register 614 (MAC Address67 High Register) - MAC_Address67_High
62590  *
62591  * The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC
62592  * address of the station. Because the MAC address registers are configured to be
62593  * double-synchronized to the (G)MII clock domains, the synchronization is
62594  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
62595  * endian mode) of the MAC Address67 Low Register are written. For proper
62596  * synchronization updates, the consecutive writes to this Address Low Register
62597  * should be performed after at least four clock cycles in the destination clock
62598  * domain.
62599  *
62600  * Note that all MAC Address High registers (except MAC Address0 High) have the
62601  * same format.
62602  *
62603  * Register Layout
62604  *
62605  * Bits | Access | Reset | Description
62606  * :--------|:-------|:-------|:----------------------
62607  * [15:0] | RW | 0xffff | MAC Address67 [47:32]
62608  * [23:16] | ??? | 0x0 | *UNDEFINED*
62609  * [24] | RW | 0x0 | Mask Byte Control
62610  * [25] | RW | 0x0 | Mask Byte Control
62611  * [26] | RW | 0x0 | Mask Byte Control
62612  * [27] | RW | 0x0 | Mask Byte Control
62613  * [28] | RW | 0x0 | Mask Byte Control
62614  * [29] | RW | 0x0 | Mask Byte Control
62615  * [30] | RW | 0x0 | Source Address
62616  * [31] | RW | 0x0 | Address Enable
62617  *
62618  */
62619 /*
62620  * Field : MAC Address67 [47:32] - addrhi
62621  *
62622  * This field contains the upper 16 bits (47:32) of the 68th 6-byte MAC address.
62623  *
62624  * Field Access Macros:
62625  *
62626  */
62627 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
62628 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_LSB 0
62629 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
62630 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_MSB 15
62631 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
62632 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_WIDTH 16
62633 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
62634 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET_MSK 0x0000ffff
62635 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
62636 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_CLR_MSK 0xffff0000
62637 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
62638 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_RESET 0xffff
62639 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI field value from a register. */
62640 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
62641 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value suitable for setting the register. */
62642 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
62643 
62644 /*
62645  * Field : Mask Byte Control - mbc_0
62646  *
62647  * This array of bits are mask control bits for comparison of each of the MAC
62648  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62649  * received DA or SA with the contents of MAC Address67 high and low registers.
62650  * Each bit controls the masking of the bytes. You can filter a group of addresses
62651  * (known as group address filtering) by masking one or more bytes of the address.
62652  *
62653  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62654  *
62655  * Field Enumeration Values:
62656  *
62657  * Enum | Value | Description
62658  * :----------------------------------------------|:------|:------------------------------------
62659  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62660  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62661  *
62662  * Field Access Macros:
62663  *
62664  */
62665 /*
62666  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0
62667  *
62668  * Byte is unmasked (i.e. is compared)
62669  */
62670 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED 0x0
62671 /*
62672  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0
62673  *
62674  * Byte is masked (i.e. not compared)
62675  */
62676 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED 0x1
62677 
62678 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
62679 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_LSB 24
62680 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
62681 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_MSB 24
62682 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
62683 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_WIDTH 1
62684 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */
62685 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET_MSK 0x01000000
62686 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */
62687 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_CLR_MSK 0xfeffffff
62688 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
62689 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_RESET 0x0
62690 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 field value from a register. */
62691 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
62692 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value suitable for setting the register. */
62693 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
62694 
62695 /*
62696  * Field : Mask Byte Control - mbc_1
62697  *
62698  * This array of bits are mask control bits for comparison of each of the MAC
62699  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62700  * received DA or SA with the contents of MAC Address67 high and low registers.
62701  * Each bit controls the masking of the bytes. You can filter a group of addresses
62702  * (known as group address filtering) by masking one or more bytes of the address.
62703  *
62704  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62705  *
62706  * Field Enumeration Values:
62707  *
62708  * Enum | Value | Description
62709  * :----------------------------------------------|:------|:------------------------------------
62710  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62711  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62712  *
62713  * Field Access Macros:
62714  *
62715  */
62716 /*
62717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1
62718  *
62719  * Byte is unmasked (i.e. is compared)
62720  */
62721 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED 0x0
62722 /*
62723  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1
62724  *
62725  * Byte is masked (i.e. not compared)
62726  */
62727 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED 0x1
62728 
62729 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
62730 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_LSB 25
62731 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
62732 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_MSB 25
62733 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
62734 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_WIDTH 1
62735 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */
62736 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET_MSK 0x02000000
62737 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */
62738 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_CLR_MSK 0xfdffffff
62739 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
62740 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_RESET 0x0
62741 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 field value from a register. */
62742 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
62743 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value suitable for setting the register. */
62744 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
62745 
62746 /*
62747  * Field : Mask Byte Control - mbc_2
62748  *
62749  * This array of bits are mask control bits for comparison of each of the MAC
62750  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62751  * received DA or SA with the contents of MAC Address67 high and low registers.
62752  * Each bit controls the masking of the bytes. You can filter a group of addresses
62753  * (known as group address filtering) by masking one or more bytes of the address.
62754  *
62755  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62756  *
62757  * Field Enumeration Values:
62758  *
62759  * Enum | Value | Description
62760  * :----------------------------------------------|:------|:------------------------------------
62761  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62762  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62763  *
62764  * Field Access Macros:
62765  *
62766  */
62767 /*
62768  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2
62769  *
62770  * Byte is unmasked (i.e. is compared)
62771  */
62772 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED 0x0
62773 /*
62774  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2
62775  *
62776  * Byte is masked (i.e. not compared)
62777  */
62778 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED 0x1
62779 
62780 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
62781 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_LSB 26
62782 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
62783 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_MSB 26
62784 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
62785 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_WIDTH 1
62786 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */
62787 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET_MSK 0x04000000
62788 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */
62789 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_CLR_MSK 0xfbffffff
62790 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
62791 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_RESET 0x0
62792 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 field value from a register. */
62793 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
62794 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value suitable for setting the register. */
62795 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
62796 
62797 /*
62798  * Field : Mask Byte Control - mbc_3
62799  *
62800  * This array of bits are mask control bits for comparison of each of the MAC
62801  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62802  * received DA or SA with the contents of MAC Address67 high and low registers.
62803  * Each bit controls the masking of the bytes. You can filter a group of addresses
62804  * (known as group address filtering) by masking one or more bytes of the address.
62805  *
62806  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62807  *
62808  * Field Enumeration Values:
62809  *
62810  * Enum | Value | Description
62811  * :----------------------------------------------|:------|:------------------------------------
62812  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62813  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62814  *
62815  * Field Access Macros:
62816  *
62817  */
62818 /*
62819  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3
62820  *
62821  * Byte is unmasked (i.e. is compared)
62822  */
62823 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED 0x0
62824 /*
62825  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3
62826  *
62827  * Byte is masked (i.e. not compared)
62828  */
62829 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED 0x1
62830 
62831 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
62832 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_LSB 27
62833 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
62834 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_MSB 27
62835 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
62836 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_WIDTH 1
62837 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */
62838 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET_MSK 0x08000000
62839 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */
62840 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_CLR_MSK 0xf7ffffff
62841 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
62842 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_RESET 0x0
62843 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 field value from a register. */
62844 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
62845 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value suitable for setting the register. */
62846 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
62847 
62848 /*
62849  * Field : Mask Byte Control - mbc_4
62850  *
62851  * This array of bits are mask control bits for comparison of each of the MAC
62852  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62853  * received DA or SA with the contents of MAC Address67 high and low registers.
62854  * Each bit controls the masking of the bytes. You can filter a group of addresses
62855  * (known as group address filtering) by masking one or more bytes of the address.
62856  *
62857  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62858  *
62859  * Field Enumeration Values:
62860  *
62861  * Enum | Value | Description
62862  * :----------------------------------------------|:------|:------------------------------------
62863  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62864  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62865  *
62866  * Field Access Macros:
62867  *
62868  */
62869 /*
62870  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4
62871  *
62872  * Byte is unmasked (i.e. is compared)
62873  */
62874 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED 0x0
62875 /*
62876  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4
62877  *
62878  * Byte is masked (i.e. not compared)
62879  */
62880 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED 0x1
62881 
62882 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
62883 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_LSB 28
62884 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
62885 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_MSB 28
62886 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
62887 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_WIDTH 1
62888 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */
62889 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET_MSK 0x10000000
62890 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */
62891 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_CLR_MSK 0xefffffff
62892 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
62893 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_RESET 0x0
62894 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 field value from a register. */
62895 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
62896 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value suitable for setting the register. */
62897 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
62898 
62899 /*
62900  * Field : Mask Byte Control - mbc_5
62901  *
62902  * This array of bits are mask control bits for comparison of each of the MAC
62903  * Address bytes. When masked, the MAC does not compare the corresponding byte of
62904  * received DA or SA with the contents of MAC Address67 high and low registers.
62905  * Each bit controls the masking of the bytes. You can filter a group of addresses
62906  * (known as group address filtering) by masking one or more bytes of the address.
62907  *
62908  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
62909  *
62910  * Field Enumeration Values:
62911  *
62912  * Enum | Value | Description
62913  * :----------------------------------------------|:------|:------------------------------------
62914  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
62915  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
62916  *
62917  * Field Access Macros:
62918  *
62919  */
62920 /*
62921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5
62922  *
62923  * Byte is unmasked (i.e. is compared)
62924  */
62925 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED 0x0
62926 /*
62927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5
62928  *
62929  * Byte is masked (i.e. not compared)
62930  */
62931 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED 0x1
62932 
62933 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
62934 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_LSB 29
62935 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
62936 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_MSB 29
62937 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
62938 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_WIDTH 1
62939 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */
62940 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET_MSK 0x20000000
62941 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */
62942 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_CLR_MSK 0xdfffffff
62943 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
62944 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_RESET 0x0
62945 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 field value from a register. */
62946 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
62947 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value suitable for setting the register. */
62948 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
62949 
62950 /*
62951  * Field : Source Address - sa
62952  *
62953  * When this bit is enabled, the MAC Address67[47:0] is used to compare with the SA
62954  * fields of the received frame. When this bit is disabled, the MAC Address67[47:0]
62955  * is used to compare with the DA fields of the received frame.
62956  *
62957  * Field Enumeration Values:
62958  *
62959  * Enum | Value | Description
62960  * :----------------------------------------|:------|:-----------------------------
62961  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
62962  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END | 0x1 | MAC address compare enabled
62963  *
62964  * Field Access Macros:
62965  *
62966  */
62967 /*
62968  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA
62969  *
62970  * MAC address compare disabled
62971  */
62972 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD 0x0
62973 /*
62974  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA
62975  *
62976  * MAC address compare enabled
62977  */
62978 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END 0x1
62979 
62980 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
62981 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_LSB 30
62982 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
62983 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_MSB 30
62984 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
62985 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_WIDTH 1
62986 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */
62987 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET_MSK 0x40000000
62988 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */
62989 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_CLR_MSK 0xbfffffff
62990 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
62991 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_RESET 0x0
62992 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA field value from a register. */
62993 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
62994 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value suitable for setting the register. */
62995 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
62996 
62997 /*
62998  * Field : Address Enable - ae
62999  *
63000  * When this bit is enabled, the address filter block uses the 68th MAC address for
63001  * perfect filtering. When this bit is disabled, the address filter block ignores
63002  * the address for filtering.
63003  *
63004  * Field Enumeration Values:
63005  *
63006  * Enum | Value | Description
63007  * :----------------------------------------|:------|:--------------------------------------
63008  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
63009  * ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
63010  *
63011  * Field Access Macros:
63012  *
63013  */
63014 /*
63015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
63016  *
63017  * Second MAC address filtering disabled
63018  */
63019 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD 0x0
63020 /*
63021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
63022  *
63023  * Second MAC address filtering enabled
63024  */
63025 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END 0x1
63026 
63027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
63028 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_LSB 31
63029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
63030 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_MSB 31
63031 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
63032 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_WIDTH 1
63033 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
63034 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET_MSK 0x80000000
63035 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
63036 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_CLR_MSK 0x7fffffff
63037 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
63038 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_RESET 0x0
63039 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE field value from a register. */
63040 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63041 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value suitable for setting the register. */
63042 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63043 
63044 #ifndef __ASSEMBLY__
63045 /*
63046  * WARNING: The C register and register group struct declarations are provided for
63047  * convenience and illustrative purposes. They should, however, be used with
63048  * caution as the C language standard provides no guarantees about the alignment or
63049  * atomicity of device memory accesses. The recommended practice for writing
63050  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63051  * alt_write_word() functions.
63052  *
63053  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH.
63054  */
63055 struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s
63056 {
63057  uint32_t addrhi : 16; /* MAC Address67 [47:32] */
63058  uint32_t : 8; /* *UNDEFINED* */
63059  uint32_t mbc_0 : 1; /* Mask Byte Control */
63060  uint32_t mbc_1 : 1; /* Mask Byte Control */
63061  uint32_t mbc_2 : 1; /* Mask Byte Control */
63062  uint32_t mbc_3 : 1; /* Mask Byte Control */
63063  uint32_t mbc_4 : 1; /* Mask Byte Control */
63064  uint32_t mbc_5 : 1; /* Mask Byte Control */
63065  uint32_t sa : 1; /* Source Address */
63066  uint32_t ae : 1; /* Address Enable */
63067 };
63068 
63069 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH. */
63070 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t;
63071 #endif /* __ASSEMBLY__ */
63072 
63073 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register from the beginning of the component. */
63074 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST 0x998
63075 /* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register. */
63076 #define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST))
63077 
63078 /*
63079  * Register : Register 615 (MAC Address67 Low Register) - MAC_Address67_Low
63080  *
63081  * The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC
63082  * address of the station.
63083  *
63084  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
63085  * format.
63086  *
63087  * Register Layout
63088  *
63089  * Bits | Access | Reset | Description
63090  * :-------|:-------|:-----------|:---------------------
63091  * [31:0] | RW | 0xffffffff | MAC Address67 [31:0]
63092  *
63093  */
63094 /*
63095  * Field : MAC Address67 [31:0] - addrlo
63096  *
63097  * This field contains the lower 32 bits of the 68th 6-byte MAC address. The
63098  * content of this field is undefined until loaded by software after the
63099  * initialization process.
63100  *
63101  * Field Access Macros:
63102  *
63103  */
63104 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
63105 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_LSB 0
63106 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
63107 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_MSB 31
63108 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
63109 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_WIDTH 32
63110 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
63111 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET_MSK 0xffffffff
63112 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
63113 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_CLR_MSK 0x00000000
63114 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
63115 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_RESET 0xffffffff
63116 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO field value from a register. */
63117 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63118 /* Produces a ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value suitable for setting the register. */
63119 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63120 
63121 #ifndef __ASSEMBLY__
63122 /*
63123  * WARNING: The C register and register group struct declarations are provided for
63124  * convenience and illustrative purposes. They should, however, be used with
63125  * caution as the C language standard provides no guarantees about the alignment or
63126  * atomicity of device memory accesses. The recommended practice for writing
63127  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63128  * alt_write_word() functions.
63129  *
63130  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW.
63131  */
63132 struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s
63133 {
63134  uint32_t addrlo : 32; /* MAC Address67 [31:0] */
63135 };
63136 
63137 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW. */
63138 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s ALT_EMAC_GMAC_MAC_ADDR67_LOW_t;
63139 #endif /* __ASSEMBLY__ */
63140 
63141 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register from the beginning of the component. */
63142 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST 0x99c
63143 /* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register. */
63144 #define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST))
63145 
63146 /*
63147  * Register : Register 616 (MAC Address68 High Register) - MAC_Address68_High
63148  *
63149  * The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC
63150  * address of the station. Because the MAC address registers are configured to be
63151  * double-synchronized to the (G)MII clock domains, the synchronization is
63152  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
63153  * endian mode) of the MAC Address68 Low Register are written. For proper
63154  * synchronization updates, the consecutive writes to this Address Low Register
63155  * should be performed after at least four clock cycles in the destination clock
63156  * domain.
63157  *
63158  * Note that all MAC Address High registers (except MAC Address0 High) have the
63159  * same format.
63160  *
63161  * Register Layout
63162  *
63163  * Bits | Access | Reset | Description
63164  * :--------|:-------|:-------|:----------------------
63165  * [15:0] | RW | 0xffff | MAC Address68 [47:32]
63166  * [23:16] | ??? | 0x0 | *UNDEFINED*
63167  * [24] | RW | 0x0 | Mask Byte Control
63168  * [25] | RW | 0x0 | Mask Byte Control
63169  * [26] | RW | 0x0 | Mask Byte Control
63170  * [27] | RW | 0x0 | Mask Byte Control
63171  * [28] | RW | 0x0 | Mask Byte Control
63172  * [29] | RW | 0x0 | Mask Byte Control
63173  * [30] | RW | 0x0 | Source Address
63174  * [31] | RW | 0x0 | Address Enable
63175  *
63176  */
63177 /*
63178  * Field : MAC Address68 [47:32] - addrhi
63179  *
63180  * This field contains the upper 16 bits (47:32) of the 69th 6-byte MAC address.
63181  *
63182  * Field Access Macros:
63183  *
63184  */
63185 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
63186 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_LSB 0
63187 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
63188 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_MSB 15
63189 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
63190 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_WIDTH 16
63191 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
63192 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET_MSK 0x0000ffff
63193 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
63194 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_CLR_MSK 0xffff0000
63195 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
63196 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_RESET 0xffff
63197 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI field value from a register. */
63198 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63199 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value suitable for setting the register. */
63200 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63201 
63202 /*
63203  * Field : Mask Byte Control - mbc_0
63204  *
63205  * This array of bits are mask control bits for comparison of each of the MAC
63206  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63207  * received DA or SA with the contents of MAC Address68 high and low registers.
63208  * Each bit controls the masking of the bytes. You can filter a group of addresses
63209  * (known as group address filtering) by masking one or more bytes of the address.
63210  *
63211  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63212  *
63213  * Field Enumeration Values:
63214  *
63215  * Enum | Value | Description
63216  * :----------------------------------------------|:------|:------------------------------------
63217  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63218  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63219  *
63220  * Field Access Macros:
63221  *
63222  */
63223 /*
63224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0
63225  *
63226  * Byte is unmasked (i.e. is compared)
63227  */
63228 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED 0x0
63229 /*
63230  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0
63231  *
63232  * Byte is masked (i.e. not compared)
63233  */
63234 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED 0x1
63235 
63236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
63237 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_LSB 24
63238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
63239 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_MSB 24
63240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
63241 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_WIDTH 1
63242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */
63243 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET_MSK 0x01000000
63244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */
63245 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_CLR_MSK 0xfeffffff
63246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
63247 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_RESET 0x0
63248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 field value from a register. */
63249 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
63250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value suitable for setting the register. */
63251 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
63252 
63253 /*
63254  * Field : Mask Byte Control - mbc_1
63255  *
63256  * This array of bits are mask control bits for comparison of each of the MAC
63257  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63258  * received DA or SA with the contents of MAC Address68 high and low registers.
63259  * Each bit controls the masking of the bytes. You can filter a group of addresses
63260  * (known as group address filtering) by masking one or more bytes of the address.
63261  *
63262  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63263  *
63264  * Field Enumeration Values:
63265  *
63266  * Enum | Value | Description
63267  * :----------------------------------------------|:------|:------------------------------------
63268  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63269  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63270  *
63271  * Field Access Macros:
63272  *
63273  */
63274 /*
63275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1
63276  *
63277  * Byte is unmasked (i.e. is compared)
63278  */
63279 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED 0x0
63280 /*
63281  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1
63282  *
63283  * Byte is masked (i.e. not compared)
63284  */
63285 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED 0x1
63286 
63287 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
63288 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_LSB 25
63289 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
63290 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_MSB 25
63291 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
63292 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_WIDTH 1
63293 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */
63294 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET_MSK 0x02000000
63295 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */
63296 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_CLR_MSK 0xfdffffff
63297 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
63298 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_RESET 0x0
63299 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 field value from a register. */
63300 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
63301 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value suitable for setting the register. */
63302 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
63303 
63304 /*
63305  * Field : Mask Byte Control - mbc_2
63306  *
63307  * This array of bits are mask control bits for comparison of each of the MAC
63308  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63309  * received DA or SA with the contents of MAC Address68 high and low registers.
63310  * Each bit controls the masking of the bytes. You can filter a group of addresses
63311  * (known as group address filtering) by masking one or more bytes of the address.
63312  *
63313  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63314  *
63315  * Field Enumeration Values:
63316  *
63317  * Enum | Value | Description
63318  * :----------------------------------------------|:------|:------------------------------------
63319  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63320  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63321  *
63322  * Field Access Macros:
63323  *
63324  */
63325 /*
63326  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2
63327  *
63328  * Byte is unmasked (i.e. is compared)
63329  */
63330 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED 0x0
63331 /*
63332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2
63333  *
63334  * Byte is masked (i.e. not compared)
63335  */
63336 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED 0x1
63337 
63338 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
63339 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_LSB 26
63340 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
63341 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_MSB 26
63342 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
63343 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_WIDTH 1
63344 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */
63345 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET_MSK 0x04000000
63346 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */
63347 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_CLR_MSK 0xfbffffff
63348 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
63349 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_RESET 0x0
63350 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 field value from a register. */
63351 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
63352 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value suitable for setting the register. */
63353 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
63354 
63355 /*
63356  * Field : Mask Byte Control - mbc_3
63357  *
63358  * This array of bits are mask control bits for comparison of each of the MAC
63359  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63360  * received DA or SA with the contents of MAC Address68 high and low registers.
63361  * Each bit controls the masking of the bytes. You can filter a group of addresses
63362  * (known as group address filtering) by masking one or more bytes of the address.
63363  *
63364  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63365  *
63366  * Field Enumeration Values:
63367  *
63368  * Enum | Value | Description
63369  * :----------------------------------------------|:------|:------------------------------------
63370  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63371  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63372  *
63373  * Field Access Macros:
63374  *
63375  */
63376 /*
63377  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3
63378  *
63379  * Byte is unmasked (i.e. is compared)
63380  */
63381 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED 0x0
63382 /*
63383  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3
63384  *
63385  * Byte is masked (i.e. not compared)
63386  */
63387 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED 0x1
63388 
63389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
63390 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_LSB 27
63391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
63392 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_MSB 27
63393 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
63394 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_WIDTH 1
63395 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */
63396 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET_MSK 0x08000000
63397 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */
63398 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_CLR_MSK 0xf7ffffff
63399 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
63400 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_RESET 0x0
63401 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 field value from a register. */
63402 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
63403 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value suitable for setting the register. */
63404 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
63405 
63406 /*
63407  * Field : Mask Byte Control - mbc_4
63408  *
63409  * This array of bits are mask control bits for comparison of each of the MAC
63410  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63411  * received DA or SA with the contents of MAC Address68 high and low registers.
63412  * Each bit controls the masking of the bytes. You can filter a group of addresses
63413  * (known as group address filtering) by masking one or more bytes of the address.
63414  *
63415  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63416  *
63417  * Field Enumeration Values:
63418  *
63419  * Enum | Value | Description
63420  * :----------------------------------------------|:------|:------------------------------------
63421  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63422  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63423  *
63424  * Field Access Macros:
63425  *
63426  */
63427 /*
63428  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4
63429  *
63430  * Byte is unmasked (i.e. is compared)
63431  */
63432 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED 0x0
63433 /*
63434  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4
63435  *
63436  * Byte is masked (i.e. not compared)
63437  */
63438 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED 0x1
63439 
63440 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
63441 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_LSB 28
63442 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
63443 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_MSB 28
63444 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
63445 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_WIDTH 1
63446 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */
63447 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET_MSK 0x10000000
63448 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */
63449 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_CLR_MSK 0xefffffff
63450 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
63451 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_RESET 0x0
63452 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 field value from a register. */
63453 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
63454 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value suitable for setting the register. */
63455 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
63456 
63457 /*
63458  * Field : Mask Byte Control - mbc_5
63459  *
63460  * This array of bits are mask control bits for comparison of each of the MAC
63461  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63462  * received DA or SA with the contents of MAC Address68 high and low registers.
63463  * Each bit controls the masking of the bytes. You can filter a group of addresses
63464  * (known as group address filtering) by masking one or more bytes of the address.
63465  *
63466  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63467  *
63468  * Field Enumeration Values:
63469  *
63470  * Enum | Value | Description
63471  * :----------------------------------------------|:------|:------------------------------------
63472  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63473  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63474  *
63475  * Field Access Macros:
63476  *
63477  */
63478 /*
63479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5
63480  *
63481  * Byte is unmasked (i.e. is compared)
63482  */
63483 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED 0x0
63484 /*
63485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5
63486  *
63487  * Byte is masked (i.e. not compared)
63488  */
63489 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED 0x1
63490 
63491 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
63492 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_LSB 29
63493 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
63494 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_MSB 29
63495 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
63496 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_WIDTH 1
63497 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */
63498 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET_MSK 0x20000000
63499 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */
63500 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_CLR_MSK 0xdfffffff
63501 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
63502 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_RESET 0x0
63503 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 field value from a register. */
63504 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
63505 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value suitable for setting the register. */
63506 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
63507 
63508 /*
63509  * Field : Source Address - sa
63510  *
63511  * When this bit is enabled, the MAC Address68[47:0] is used to compare with the SA
63512  * fields of the received frame. When this bit is disabled, the MAC Address68[47:0]
63513  * is used to compare with the DA fields of the received frame.
63514  *
63515  * Field Enumeration Values:
63516  *
63517  * Enum | Value | Description
63518  * :----------------------------------------|:------|:-----------------------------
63519  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
63520  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END | 0x1 | MAC address compare enabled
63521  *
63522  * Field Access Macros:
63523  *
63524  */
63525 /*
63526  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA
63527  *
63528  * MAC address compare disabled
63529  */
63530 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD 0x0
63531 /*
63532  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA
63533  *
63534  * MAC address compare enabled
63535  */
63536 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END 0x1
63537 
63538 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
63539 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_LSB 30
63540 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
63541 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_MSB 30
63542 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
63543 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_WIDTH 1
63544 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */
63545 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET_MSK 0x40000000
63546 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */
63547 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_CLR_MSK 0xbfffffff
63548 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
63549 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_RESET 0x0
63550 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA field value from a register. */
63551 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
63552 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value suitable for setting the register. */
63553 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
63554 
63555 /*
63556  * Field : Address Enable - ae
63557  *
63558  * When this bit is enabled, the address filter block uses the 69th MAC address for
63559  * perfect filtering. When this bit is disabled, the address filter block ignores
63560  * the address for filtering.
63561  *
63562  * Field Enumeration Values:
63563  *
63564  * Enum | Value | Description
63565  * :----------------------------------------|:------|:--------------------------------------
63566  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
63567  * ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
63568  *
63569  * Field Access Macros:
63570  *
63571  */
63572 /*
63573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
63574  *
63575  * Second MAC address filtering disabled
63576  */
63577 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD 0x0
63578 /*
63579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
63580  *
63581  * Second MAC address filtering enabled
63582  */
63583 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END 0x1
63584 
63585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
63586 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_LSB 31
63587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
63588 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_MSB 31
63589 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
63590 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_WIDTH 1
63591 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
63592 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET_MSK 0x80000000
63593 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
63594 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_CLR_MSK 0x7fffffff
63595 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
63596 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_RESET 0x0
63597 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE field value from a register. */
63598 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
63599 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value suitable for setting the register. */
63600 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
63601 
63602 #ifndef __ASSEMBLY__
63603 /*
63604  * WARNING: The C register and register group struct declarations are provided for
63605  * convenience and illustrative purposes. They should, however, be used with
63606  * caution as the C language standard provides no guarantees about the alignment or
63607  * atomicity of device memory accesses. The recommended practice for writing
63608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63609  * alt_write_word() functions.
63610  *
63611  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH.
63612  */
63613 struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s
63614 {
63615  uint32_t addrhi : 16; /* MAC Address68 [47:32] */
63616  uint32_t : 8; /* *UNDEFINED* */
63617  uint32_t mbc_0 : 1; /* Mask Byte Control */
63618  uint32_t mbc_1 : 1; /* Mask Byte Control */
63619  uint32_t mbc_2 : 1; /* Mask Byte Control */
63620  uint32_t mbc_3 : 1; /* Mask Byte Control */
63621  uint32_t mbc_4 : 1; /* Mask Byte Control */
63622  uint32_t mbc_5 : 1; /* Mask Byte Control */
63623  uint32_t sa : 1; /* Source Address */
63624  uint32_t ae : 1; /* Address Enable */
63625 };
63626 
63627 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH. */
63628 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t;
63629 #endif /* __ASSEMBLY__ */
63630 
63631 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register from the beginning of the component. */
63632 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST 0x9a0
63633 /* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register. */
63634 #define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST))
63635 
63636 /*
63637  * Register : Register 617 (MAC Address68 Low Register) - MAC_Address68_Low
63638  *
63639  * The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC
63640  * address of the station.
63641  *
63642  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
63643  * format.
63644  *
63645  * Register Layout
63646  *
63647  * Bits | Access | Reset | Description
63648  * :-------|:-------|:-----------|:---------------------
63649  * [31:0] | RW | 0xffffffff | MAC Address68 [31:0]
63650  *
63651  */
63652 /*
63653  * Field : MAC Address68 [31:0] - addrlo
63654  *
63655  * This field contains the lower 32 bits of the 69th 6-byte MAC address. The
63656  * content of this field is undefined until loaded by software after the
63657  * initialization process.
63658  *
63659  * Field Access Macros:
63660  *
63661  */
63662 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
63663 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_LSB 0
63664 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
63665 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_MSB 31
63666 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
63667 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_WIDTH 32
63668 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
63669 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET_MSK 0xffffffff
63670 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
63671 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_CLR_MSK 0x00000000
63672 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
63673 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_RESET 0xffffffff
63674 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO field value from a register. */
63675 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
63676 /* Produces a ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value suitable for setting the register. */
63677 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
63678 
63679 #ifndef __ASSEMBLY__
63680 /*
63681  * WARNING: The C register and register group struct declarations are provided for
63682  * convenience and illustrative purposes. They should, however, be used with
63683  * caution as the C language standard provides no guarantees about the alignment or
63684  * atomicity of device memory accesses. The recommended practice for writing
63685  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
63686  * alt_write_word() functions.
63687  *
63688  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW.
63689  */
63690 struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s
63691 {
63692  uint32_t addrlo : 32; /* MAC Address68 [31:0] */
63693 };
63694 
63695 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW. */
63696 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s ALT_EMAC_GMAC_MAC_ADDR68_LOW_t;
63697 #endif /* __ASSEMBLY__ */
63698 
63699 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register from the beginning of the component. */
63700 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST 0x9a4
63701 /* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register. */
63702 #define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST))
63703 
63704 /*
63705  * Register : Register 618 (MAC Address69 High Register) - MAC_Address69_High
63706  *
63707  * The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC
63708  * address of the station. Because the MAC address registers are configured to be
63709  * double-synchronized to the (G)MII clock domains, the synchronization is
63710  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
63711  * endian mode) of the MAC Address69 Low Register are written. For proper
63712  * synchronization updates, the consecutive writes to this Address Low Register
63713  * should be performed after at least four clock cycles in the destination clock
63714  * domain.
63715  *
63716  * Note that all MAC Address High registers (except MAC Address0 High) have the
63717  * same format.
63718  *
63719  * Register Layout
63720  *
63721  * Bits | Access | Reset | Description
63722  * :--------|:-------|:-------|:----------------------
63723  * [15:0] | RW | 0xffff | MAC Address69 [47:32]
63724  * [23:16] | ??? | 0x0 | *UNDEFINED*
63725  * [24] | RW | 0x0 | Mask Byte Control
63726  * [25] | RW | 0x0 | Mask Byte Control
63727  * [26] | RW | 0x0 | Mask Byte Control
63728  * [27] | RW | 0x0 | Mask Byte Control
63729  * [28] | RW | 0x0 | Mask Byte Control
63730  * [29] | RW | 0x0 | Mask Byte Control
63731  * [30] | RW | 0x0 | Source Address
63732  * [31] | RW | 0x0 | Address Enable
63733  *
63734  */
63735 /*
63736  * Field : MAC Address69 [47:32] - addrhi
63737  *
63738  * This field contains the upper 16 bits (47:32) of the 70th 6-byte MAC address.
63739  *
63740  * Field Access Macros:
63741  *
63742  */
63743 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
63744 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_LSB 0
63745 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
63746 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_MSB 15
63747 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
63748 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_WIDTH 16
63749 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
63750 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET_MSK 0x0000ffff
63751 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
63752 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_CLR_MSK 0xffff0000
63753 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
63754 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_RESET 0xffff
63755 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI field value from a register. */
63756 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
63757 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value suitable for setting the register. */
63758 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
63759 
63760 /*
63761  * Field : Mask Byte Control - mbc_0
63762  *
63763  * This array of bits are mask control bits for comparison of each of the MAC
63764  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63765  * received DA or SA with the contents of MAC Address69 high and low registers.
63766  * Each bit controls the masking of the bytes. You can filter a group of addresses
63767  * (known as group address filtering) by masking one or more bytes of the address.
63768  *
63769  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63770  *
63771  * Field Enumeration Values:
63772  *
63773  * Enum | Value | Description
63774  * :----------------------------------------------|:------|:------------------------------------
63775  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63776  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63777  *
63778  * Field Access Macros:
63779  *
63780  */
63781 /*
63782  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0
63783  *
63784  * Byte is unmasked (i.e. is compared)
63785  */
63786 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED 0x0
63787 /*
63788  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0
63789  *
63790  * Byte is masked (i.e. not compared)
63791  */
63792 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED 0x1
63793 
63794 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
63795 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_LSB 24
63796 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
63797 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_MSB 24
63798 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
63799 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_WIDTH 1
63800 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */
63801 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET_MSK 0x01000000
63802 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */
63803 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_CLR_MSK 0xfeffffff
63804 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
63805 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_RESET 0x0
63806 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 field value from a register. */
63807 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
63808 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value suitable for setting the register. */
63809 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
63810 
63811 /*
63812  * Field : Mask Byte Control - mbc_1
63813  *
63814  * This array of bits are mask control bits for comparison of each of the MAC
63815  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63816  * received DA or SA with the contents of MAC Address69 high and low registers.
63817  * Each bit controls the masking of the bytes. You can filter a group of addresses
63818  * (known as group address filtering) by masking one or more bytes of the address.
63819  *
63820  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63821  *
63822  * Field Enumeration Values:
63823  *
63824  * Enum | Value | Description
63825  * :----------------------------------------------|:------|:------------------------------------
63826  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63827  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63828  *
63829  * Field Access Macros:
63830  *
63831  */
63832 /*
63833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1
63834  *
63835  * Byte is unmasked (i.e. is compared)
63836  */
63837 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED 0x0
63838 /*
63839  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1
63840  *
63841  * Byte is masked (i.e. not compared)
63842  */
63843 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED 0x1
63844 
63845 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
63846 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_LSB 25
63847 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
63848 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_MSB 25
63849 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
63850 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_WIDTH 1
63851 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */
63852 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET_MSK 0x02000000
63853 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */
63854 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_CLR_MSK 0xfdffffff
63855 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
63856 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_RESET 0x0
63857 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 field value from a register. */
63858 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
63859 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value suitable for setting the register. */
63860 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
63861 
63862 /*
63863  * Field : Mask Byte Control - mbc_2
63864  *
63865  * This array of bits are mask control bits for comparison of each of the MAC
63866  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63867  * received DA or SA with the contents of MAC Address69 high and low registers.
63868  * Each bit controls the masking of the bytes. You can filter a group of addresses
63869  * (known as group address filtering) by masking one or more bytes of the address.
63870  *
63871  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63872  *
63873  * Field Enumeration Values:
63874  *
63875  * Enum | Value | Description
63876  * :----------------------------------------------|:------|:------------------------------------
63877  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63878  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63879  *
63880  * Field Access Macros:
63881  *
63882  */
63883 /*
63884  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2
63885  *
63886  * Byte is unmasked (i.e. is compared)
63887  */
63888 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED 0x0
63889 /*
63890  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2
63891  *
63892  * Byte is masked (i.e. not compared)
63893  */
63894 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED 0x1
63895 
63896 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
63897 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_LSB 26
63898 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
63899 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_MSB 26
63900 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
63901 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_WIDTH 1
63902 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */
63903 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET_MSK 0x04000000
63904 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */
63905 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_CLR_MSK 0xfbffffff
63906 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
63907 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_RESET 0x0
63908 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 field value from a register. */
63909 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
63910 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value suitable for setting the register. */
63911 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
63912 
63913 /*
63914  * Field : Mask Byte Control - mbc_3
63915  *
63916  * This array of bits are mask control bits for comparison of each of the MAC
63917  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63918  * received DA or SA with the contents of MAC Address69 high and low registers.
63919  * Each bit controls the masking of the bytes. You can filter a group of addresses
63920  * (known as group address filtering) by masking one or more bytes of the address.
63921  *
63922  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63923  *
63924  * Field Enumeration Values:
63925  *
63926  * Enum | Value | Description
63927  * :----------------------------------------------|:------|:------------------------------------
63928  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63929  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63930  *
63931  * Field Access Macros:
63932  *
63933  */
63934 /*
63935  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3
63936  *
63937  * Byte is unmasked (i.e. is compared)
63938  */
63939 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED 0x0
63940 /*
63941  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3
63942  *
63943  * Byte is masked (i.e. not compared)
63944  */
63945 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED 0x1
63946 
63947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
63948 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_LSB 27
63949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
63950 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_MSB 27
63951 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
63952 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_WIDTH 1
63953 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */
63954 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET_MSK 0x08000000
63955 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */
63956 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_CLR_MSK 0xf7ffffff
63957 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
63958 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_RESET 0x0
63959 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 field value from a register. */
63960 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
63961 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value suitable for setting the register. */
63962 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
63963 
63964 /*
63965  * Field : Mask Byte Control - mbc_4
63966  *
63967  * This array of bits are mask control bits for comparison of each of the MAC
63968  * Address bytes. When masked, the MAC does not compare the corresponding byte of
63969  * received DA or SA with the contents of MAC Address69 high and low registers.
63970  * Each bit controls the masking of the bytes. You can filter a group of addresses
63971  * (known as group address filtering) by masking one or more bytes of the address.
63972  *
63973  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
63974  *
63975  * Field Enumeration Values:
63976  *
63977  * Enum | Value | Description
63978  * :----------------------------------------------|:------|:------------------------------------
63979  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
63980  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
63981  *
63982  * Field Access Macros:
63983  *
63984  */
63985 /*
63986  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4
63987  *
63988  * Byte is unmasked (i.e. is compared)
63989  */
63990 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED 0x0
63991 /*
63992  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4
63993  *
63994  * Byte is masked (i.e. not compared)
63995  */
63996 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED 0x1
63997 
63998 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
63999 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_LSB 28
64000 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
64001 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_MSB 28
64002 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
64003 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_WIDTH 1
64004 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */
64005 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET_MSK 0x10000000
64006 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */
64007 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_CLR_MSK 0xefffffff
64008 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
64009 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_RESET 0x0
64010 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 field value from a register. */
64011 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
64012 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value suitable for setting the register. */
64013 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
64014 
64015 /*
64016  * Field : Mask Byte Control - mbc_5
64017  *
64018  * This array of bits are mask control bits for comparison of each of the MAC
64019  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64020  * received DA or SA with the contents of MAC Address69 high and low registers.
64021  * Each bit controls the masking of the bytes. You can filter a group of addresses
64022  * (known as group address filtering) by masking one or more bytes of the address.
64023  *
64024  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64025  *
64026  * Field Enumeration Values:
64027  *
64028  * Enum | Value | Description
64029  * :----------------------------------------------|:------|:------------------------------------
64030  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64031  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64032  *
64033  * Field Access Macros:
64034  *
64035  */
64036 /*
64037  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5
64038  *
64039  * Byte is unmasked (i.e. is compared)
64040  */
64041 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED 0x0
64042 /*
64043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5
64044  *
64045  * Byte is masked (i.e. not compared)
64046  */
64047 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED 0x1
64048 
64049 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
64050 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_LSB 29
64051 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
64052 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_MSB 29
64053 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
64054 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_WIDTH 1
64055 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */
64056 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET_MSK 0x20000000
64057 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */
64058 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_CLR_MSK 0xdfffffff
64059 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
64060 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_RESET 0x0
64061 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 field value from a register. */
64062 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
64063 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value suitable for setting the register. */
64064 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
64065 
64066 /*
64067  * Field : Source Address - sa
64068  *
64069  * When this bit is enabled, the MAC Address69[47:0] is used to compare with the SA
64070  * fields of the received frame. When this bit is disabled, the MAC Address69[47:0]
64071  * is used to compare with the DA fields of the received frame.
64072  *
64073  * Field Enumeration Values:
64074  *
64075  * Enum | Value | Description
64076  * :----------------------------------------|:------|:-----------------------------
64077  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
64078  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END | 0x1 | MAC address compare enabled
64079  *
64080  * Field Access Macros:
64081  *
64082  */
64083 /*
64084  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA
64085  *
64086  * MAC address compare disabled
64087  */
64088 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD 0x0
64089 /*
64090  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA
64091  *
64092  * MAC address compare enabled
64093  */
64094 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END 0x1
64095 
64096 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
64097 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_LSB 30
64098 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
64099 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_MSB 30
64100 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
64101 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_WIDTH 1
64102 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */
64103 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET_MSK 0x40000000
64104 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */
64105 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_CLR_MSK 0xbfffffff
64106 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
64107 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_RESET 0x0
64108 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA field value from a register. */
64109 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
64110 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value suitable for setting the register. */
64111 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
64112 
64113 /*
64114  * Field : Address Enable - ae
64115  *
64116  * When this bit is enabled, the address filter block uses the 70th MAC address for
64117  * perfect filtering. When this bit is disabled, the address filter block ignores
64118  * the address for filtering.
64119  *
64120  * Field Enumeration Values:
64121  *
64122  * Enum | Value | Description
64123  * :----------------------------------------|:------|:--------------------------------------
64124  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
64125  * ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
64126  *
64127  * Field Access Macros:
64128  *
64129  */
64130 /*
64131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
64132  *
64133  * Second MAC address filtering disabled
64134  */
64135 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD 0x0
64136 /*
64137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
64138  *
64139  * Second MAC address filtering enabled
64140  */
64141 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END 0x1
64142 
64143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
64144 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_LSB 31
64145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
64146 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_MSB 31
64147 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
64148 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_WIDTH 1
64149 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
64150 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET_MSK 0x80000000
64151 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
64152 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_CLR_MSK 0x7fffffff
64153 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
64154 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_RESET 0x0
64155 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE field value from a register. */
64156 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64157 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value suitable for setting the register. */
64158 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64159 
64160 #ifndef __ASSEMBLY__
64161 /*
64162  * WARNING: The C register and register group struct declarations are provided for
64163  * convenience and illustrative purposes. They should, however, be used with
64164  * caution as the C language standard provides no guarantees about the alignment or
64165  * atomicity of device memory accesses. The recommended practice for writing
64166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64167  * alt_write_word() functions.
64168  *
64169  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH.
64170  */
64171 struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s
64172 {
64173  uint32_t addrhi : 16; /* MAC Address69 [47:32] */
64174  uint32_t : 8; /* *UNDEFINED* */
64175  uint32_t mbc_0 : 1; /* Mask Byte Control */
64176  uint32_t mbc_1 : 1; /* Mask Byte Control */
64177  uint32_t mbc_2 : 1; /* Mask Byte Control */
64178  uint32_t mbc_3 : 1; /* Mask Byte Control */
64179  uint32_t mbc_4 : 1; /* Mask Byte Control */
64180  uint32_t mbc_5 : 1; /* Mask Byte Control */
64181  uint32_t sa : 1; /* Source Address */
64182  uint32_t ae : 1; /* Address Enable */
64183 };
64184 
64185 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH. */
64186 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t;
64187 #endif /* __ASSEMBLY__ */
64188 
64189 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register from the beginning of the component. */
64190 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST 0x9a8
64191 /* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register. */
64192 #define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST))
64193 
64194 /*
64195  * Register : Register 619 (MAC Address69 Low Register) - MAC_Address69_Low
64196  *
64197  * The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC
64198  * address of the station.
64199  *
64200  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
64201  * format.
64202  *
64203  * Register Layout
64204  *
64205  * Bits | Access | Reset | Description
64206  * :-------|:-------|:-----------|:---------------------
64207  * [31:0] | RW | 0xffffffff | MAC Address69 [31:0]
64208  *
64209  */
64210 /*
64211  * Field : MAC Address69 [31:0] - addrlo
64212  *
64213  * This field contains the lower 32 bits of the 70th 6-byte MAC address. The
64214  * content of this field is undefined until loaded by software after the
64215  * initialization process.
64216  *
64217  * Field Access Macros:
64218  *
64219  */
64220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
64221 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_LSB 0
64222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
64223 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_MSB 31
64224 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
64225 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_WIDTH 32
64226 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
64227 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET_MSK 0xffffffff
64228 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
64229 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_CLR_MSK 0x00000000
64230 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
64231 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_RESET 0xffffffff
64232 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO field value from a register. */
64233 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64234 /* Produces a ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value suitable for setting the register. */
64235 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64236 
64237 #ifndef __ASSEMBLY__
64238 /*
64239  * WARNING: The C register and register group struct declarations are provided for
64240  * convenience and illustrative purposes. They should, however, be used with
64241  * caution as the C language standard provides no guarantees about the alignment or
64242  * atomicity of device memory accesses. The recommended practice for writing
64243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64244  * alt_write_word() functions.
64245  *
64246  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW.
64247  */
64248 struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s
64249 {
64250  uint32_t addrlo : 32; /* MAC Address69 [31:0] */
64251 };
64252 
64253 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW. */
64254 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s ALT_EMAC_GMAC_MAC_ADDR69_LOW_t;
64255 #endif /* __ASSEMBLY__ */
64256 
64257 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register from the beginning of the component. */
64258 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST 0x9ac
64259 /* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register. */
64260 #define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST))
64261 
64262 /*
64263  * Register : Register 620 (MAC Address70 High Register) - MAC_Address70_High
64264  *
64265  * The MAC Address70 High register holds the upper 16 bits of the 71th 6-byte MAC
64266  * address of the station. Because the MAC address registers are configured to be
64267  * double-synchronized to the (G)MII clock domains, the synchronization is
64268  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
64269  * endian mode) of the MAC Address70 Low Register are written. For proper
64270  * synchronization updates, the consecutive writes to this Address Low Register
64271  * should be performed after at least four clock cycles in the destination clock
64272  * domain.
64273  *
64274  * Note that all MAC Address High registers (except MAC Address0 High) have the
64275  * same format.
64276  *
64277  * Register Layout
64278  *
64279  * Bits | Access | Reset | Description
64280  * :--------|:-------|:-------|:----------------------
64281  * [15:0] | RW | 0xffff | MAC Address70 [47:32]
64282  * [23:16] | ??? | 0x0 | *UNDEFINED*
64283  * [24] | RW | 0x0 | Mask Byte Control
64284  * [25] | RW | 0x0 | Mask Byte Control
64285  * [26] | RW | 0x0 | Mask Byte Control
64286  * [27] | RW | 0x0 | Mask Byte Control
64287  * [28] | RW | 0x0 | Mask Byte Control
64288  * [29] | RW | 0x0 | Mask Byte Control
64289  * [30] | RW | 0x0 | Source Address
64290  * [31] | RW | 0x0 | Address Enable
64291  *
64292  */
64293 /*
64294  * Field : MAC Address70 [47:32] - addrhi
64295  *
64296  * This field contains the upper 16 bits (47:32) of the 71th 6-byte MAC address.
64297  *
64298  * Field Access Macros:
64299  *
64300  */
64301 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
64302 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_LSB 0
64303 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
64304 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_MSB 15
64305 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
64306 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_WIDTH 16
64307 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
64308 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET_MSK 0x0000ffff
64309 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
64310 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_CLR_MSK 0xffff0000
64311 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
64312 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_RESET 0xffff
64313 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI field value from a register. */
64314 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64315 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value suitable for setting the register. */
64316 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64317 
64318 /*
64319  * Field : Mask Byte Control - mbc_0
64320  *
64321  * This array of bits are mask control bits for comparison of each of the MAC
64322  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64323  * received DA or SA with the contents of MAC Address70 high and low registers.
64324  * Each bit controls the masking of the bytes. You can filter a group of addresses
64325  * (known as group address filtering) by masking one or more bytes of the address.
64326  *
64327  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64328  *
64329  * Field Enumeration Values:
64330  *
64331  * Enum | Value | Description
64332  * :----------------------------------------------|:------|:------------------------------------
64333  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64334  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64335  *
64336  * Field Access Macros:
64337  *
64338  */
64339 /*
64340  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0
64341  *
64342  * Byte is unmasked (i.e. is compared)
64343  */
64344 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED 0x0
64345 /*
64346  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0
64347  *
64348  * Byte is masked (i.e. not compared)
64349  */
64350 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED 0x1
64351 
64352 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
64353 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_LSB 24
64354 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
64355 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_MSB 24
64356 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
64357 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_WIDTH 1
64358 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */
64359 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET_MSK 0x01000000
64360 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */
64361 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_CLR_MSK 0xfeffffff
64362 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
64363 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_RESET 0x0
64364 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 field value from a register. */
64365 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
64366 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value suitable for setting the register. */
64367 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
64368 
64369 /*
64370  * Field : Mask Byte Control - mbc_1
64371  *
64372  * This array of bits are mask control bits for comparison of each of the MAC
64373  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64374  * received DA or SA with the contents of MAC Address70 high and low registers.
64375  * Each bit controls the masking of the bytes. You can filter a group of addresses
64376  * (known as group address filtering) by masking one or more bytes of the address.
64377  *
64378  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64379  *
64380  * Field Enumeration Values:
64381  *
64382  * Enum | Value | Description
64383  * :----------------------------------------------|:------|:------------------------------------
64384  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64385  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64386  *
64387  * Field Access Macros:
64388  *
64389  */
64390 /*
64391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1
64392  *
64393  * Byte is unmasked (i.e. is compared)
64394  */
64395 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED 0x0
64396 /*
64397  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1
64398  *
64399  * Byte is masked (i.e. not compared)
64400  */
64401 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED 0x1
64402 
64403 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
64404 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_LSB 25
64405 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
64406 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_MSB 25
64407 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
64408 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_WIDTH 1
64409 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */
64410 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET_MSK 0x02000000
64411 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */
64412 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_CLR_MSK 0xfdffffff
64413 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
64414 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_RESET 0x0
64415 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 field value from a register. */
64416 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
64417 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value suitable for setting the register. */
64418 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
64419 
64420 /*
64421  * Field : Mask Byte Control - mbc_2
64422  *
64423  * This array of bits are mask control bits for comparison of each of the MAC
64424  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64425  * received DA or SA with the contents of MAC Address70 high and low registers.
64426  * Each bit controls the masking of the bytes. You can filter a group of addresses
64427  * (known as group address filtering) by masking one or more bytes of the address.
64428  *
64429  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64430  *
64431  * Field Enumeration Values:
64432  *
64433  * Enum | Value | Description
64434  * :----------------------------------------------|:------|:------------------------------------
64435  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64436  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64437  *
64438  * Field Access Macros:
64439  *
64440  */
64441 /*
64442  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2
64443  *
64444  * Byte is unmasked (i.e. is compared)
64445  */
64446 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED 0x0
64447 /*
64448  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2
64449  *
64450  * Byte is masked (i.e. not compared)
64451  */
64452 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED 0x1
64453 
64454 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
64455 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_LSB 26
64456 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
64457 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_MSB 26
64458 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
64459 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_WIDTH 1
64460 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */
64461 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET_MSK 0x04000000
64462 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */
64463 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_CLR_MSK 0xfbffffff
64464 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
64465 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_RESET 0x0
64466 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 field value from a register. */
64467 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
64468 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value suitable for setting the register. */
64469 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
64470 
64471 /*
64472  * Field : Mask Byte Control - mbc_3
64473  *
64474  * This array of bits are mask control bits for comparison of each of the MAC
64475  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64476  * received DA or SA with the contents of MAC Address70 high and low registers.
64477  * Each bit controls the masking of the bytes. You can filter a group of addresses
64478  * (known as group address filtering) by masking one or more bytes of the address.
64479  *
64480  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64481  *
64482  * Field Enumeration Values:
64483  *
64484  * Enum | Value | Description
64485  * :----------------------------------------------|:------|:------------------------------------
64486  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64487  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64488  *
64489  * Field Access Macros:
64490  *
64491  */
64492 /*
64493  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3
64494  *
64495  * Byte is unmasked (i.e. is compared)
64496  */
64497 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED 0x0
64498 /*
64499  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3
64500  *
64501  * Byte is masked (i.e. not compared)
64502  */
64503 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED 0x1
64504 
64505 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
64506 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_LSB 27
64507 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
64508 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_MSB 27
64509 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
64510 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_WIDTH 1
64511 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */
64512 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET_MSK 0x08000000
64513 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */
64514 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_CLR_MSK 0xf7ffffff
64515 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
64516 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_RESET 0x0
64517 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 field value from a register. */
64518 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
64519 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value suitable for setting the register. */
64520 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
64521 
64522 /*
64523  * Field : Mask Byte Control - mbc_4
64524  *
64525  * This array of bits are mask control bits for comparison of each of the MAC
64526  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64527  * received DA or SA with the contents of MAC Address70 high and low registers.
64528  * Each bit controls the masking of the bytes. You can filter a group of addresses
64529  * (known as group address filtering) by masking one or more bytes of the address.
64530  *
64531  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64532  *
64533  * Field Enumeration Values:
64534  *
64535  * Enum | Value | Description
64536  * :----------------------------------------------|:------|:------------------------------------
64537  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64538  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64539  *
64540  * Field Access Macros:
64541  *
64542  */
64543 /*
64544  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4
64545  *
64546  * Byte is unmasked (i.e. is compared)
64547  */
64548 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED 0x0
64549 /*
64550  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4
64551  *
64552  * Byte is masked (i.e. not compared)
64553  */
64554 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED 0x1
64555 
64556 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
64557 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_LSB 28
64558 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
64559 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_MSB 28
64560 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
64561 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_WIDTH 1
64562 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */
64563 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET_MSK 0x10000000
64564 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */
64565 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_CLR_MSK 0xefffffff
64566 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
64567 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_RESET 0x0
64568 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 field value from a register. */
64569 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
64570 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value suitable for setting the register. */
64571 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
64572 
64573 /*
64574  * Field : Mask Byte Control - mbc_5
64575  *
64576  * This array of bits are mask control bits for comparison of each of the MAC
64577  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64578  * received DA or SA with the contents of MAC Address70 high and low registers.
64579  * Each bit controls the masking of the bytes. You can filter a group of addresses
64580  * (known as group address filtering) by masking one or more bytes of the address.
64581  *
64582  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64583  *
64584  * Field Enumeration Values:
64585  *
64586  * Enum | Value | Description
64587  * :----------------------------------------------|:------|:------------------------------------
64588  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64589  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64590  *
64591  * Field Access Macros:
64592  *
64593  */
64594 /*
64595  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5
64596  *
64597  * Byte is unmasked (i.e. is compared)
64598  */
64599 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED 0x0
64600 /*
64601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5
64602  *
64603  * Byte is masked (i.e. not compared)
64604  */
64605 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED 0x1
64606 
64607 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
64608 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_LSB 29
64609 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
64610 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_MSB 29
64611 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
64612 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_WIDTH 1
64613 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */
64614 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET_MSK 0x20000000
64615 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */
64616 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_CLR_MSK 0xdfffffff
64617 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
64618 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_RESET 0x0
64619 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 field value from a register. */
64620 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
64621 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value suitable for setting the register. */
64622 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
64623 
64624 /*
64625  * Field : Source Address - sa
64626  *
64627  * When this bit is enabled, the MAC Address70[47:0] is used to compare with the SA
64628  * fields of the received frame. When this bit is disabled, the MAC Address70[47:0]
64629  * is used to compare with the DA fields of the received frame.
64630  *
64631  * Field Enumeration Values:
64632  *
64633  * Enum | Value | Description
64634  * :----------------------------------------|:------|:-----------------------------
64635  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
64636  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END | 0x1 | MAC address compare enabled
64637  *
64638  * Field Access Macros:
64639  *
64640  */
64641 /*
64642  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA
64643  *
64644  * MAC address compare disabled
64645  */
64646 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD 0x0
64647 /*
64648  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA
64649  *
64650  * MAC address compare enabled
64651  */
64652 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END 0x1
64653 
64654 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
64655 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_LSB 30
64656 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
64657 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_MSB 30
64658 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
64659 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_WIDTH 1
64660 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */
64661 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET_MSK 0x40000000
64662 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */
64663 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_CLR_MSK 0xbfffffff
64664 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
64665 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_RESET 0x0
64666 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA field value from a register. */
64667 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
64668 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value suitable for setting the register. */
64669 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
64670 
64671 /*
64672  * Field : Address Enable - ae
64673  *
64674  * When this bit is enabled, the address filter block uses the 71th MAC address for
64675  * perfect filtering. When this bit is disabled, the address filter block ignores
64676  * the address for filtering.
64677  *
64678  * Field Enumeration Values:
64679  *
64680  * Enum | Value | Description
64681  * :----------------------------------------|:------|:--------------------------------------
64682  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
64683  * ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
64684  *
64685  * Field Access Macros:
64686  *
64687  */
64688 /*
64689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
64690  *
64691  * Second MAC address filtering disabled
64692  */
64693 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD 0x0
64694 /*
64695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
64696  *
64697  * Second MAC address filtering enabled
64698  */
64699 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END 0x1
64700 
64701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
64702 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_LSB 31
64703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
64704 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_MSB 31
64705 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
64706 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_WIDTH 1
64707 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
64708 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET_MSK 0x80000000
64709 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
64710 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_CLR_MSK 0x7fffffff
64711 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
64712 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_RESET 0x0
64713 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE field value from a register. */
64714 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
64715 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value suitable for setting the register. */
64716 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
64717 
64718 #ifndef __ASSEMBLY__
64719 /*
64720  * WARNING: The C register and register group struct declarations are provided for
64721  * convenience and illustrative purposes. They should, however, be used with
64722  * caution as the C language standard provides no guarantees about the alignment or
64723  * atomicity of device memory accesses. The recommended practice for writing
64724  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64725  * alt_write_word() functions.
64726  *
64727  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH.
64728  */
64729 struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s
64730 {
64731  uint32_t addrhi : 16; /* MAC Address70 [47:32] */
64732  uint32_t : 8; /* *UNDEFINED* */
64733  uint32_t mbc_0 : 1; /* Mask Byte Control */
64734  uint32_t mbc_1 : 1; /* Mask Byte Control */
64735  uint32_t mbc_2 : 1; /* Mask Byte Control */
64736  uint32_t mbc_3 : 1; /* Mask Byte Control */
64737  uint32_t mbc_4 : 1; /* Mask Byte Control */
64738  uint32_t mbc_5 : 1; /* Mask Byte Control */
64739  uint32_t sa : 1; /* Source Address */
64740  uint32_t ae : 1; /* Address Enable */
64741 };
64742 
64743 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH. */
64744 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t;
64745 #endif /* __ASSEMBLY__ */
64746 
64747 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register from the beginning of the component. */
64748 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST 0x9b0
64749 /* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register. */
64750 #define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST))
64751 
64752 /*
64753  * Register : Register 621 (MAC Address70 Low Register) - MAC_Address70_Low
64754  *
64755  * The MAC Address70 Low register holds the lower 32 bits of the 71th 6-byte MAC
64756  * address of the station.
64757  *
64758  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
64759  * format.
64760  *
64761  * Register Layout
64762  *
64763  * Bits | Access | Reset | Description
64764  * :-------|:-------|:-----------|:---------------------
64765  * [31:0] | RW | 0xffffffff | MAC Address70 [31:0]
64766  *
64767  */
64768 /*
64769  * Field : MAC Address70 [31:0] - addrlo
64770  *
64771  * This field contains the lower 32 bits of the 71th 6-byte MAC address. The
64772  * content of this field is undefined until loaded by software after the
64773  * initialization process.
64774  *
64775  * Field Access Macros:
64776  *
64777  */
64778 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
64779 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_LSB 0
64780 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
64781 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_MSB 31
64782 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
64783 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_WIDTH 32
64784 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
64785 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET_MSK 0xffffffff
64786 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
64787 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_CLR_MSK 0x00000000
64788 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
64789 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_RESET 0xffffffff
64790 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO field value from a register. */
64791 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
64792 /* Produces a ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value suitable for setting the register. */
64793 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
64794 
64795 #ifndef __ASSEMBLY__
64796 /*
64797  * WARNING: The C register and register group struct declarations are provided for
64798  * convenience and illustrative purposes. They should, however, be used with
64799  * caution as the C language standard provides no guarantees about the alignment or
64800  * atomicity of device memory accesses. The recommended practice for writing
64801  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
64802  * alt_write_word() functions.
64803  *
64804  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW.
64805  */
64806 struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s
64807 {
64808  uint32_t addrlo : 32; /* MAC Address70 [31:0] */
64809 };
64810 
64811 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW. */
64812 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s ALT_EMAC_GMAC_MAC_ADDR70_LOW_t;
64813 #endif /* __ASSEMBLY__ */
64814 
64815 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register from the beginning of the component. */
64816 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST 0x9b4
64817 /* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register. */
64818 #define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST))
64819 
64820 /*
64821  * Register : Register 622 (MAC Address71 High Register) - MAC_Address71_High
64822  *
64823  * The MAC Address71 High register holds the upper 16 bits of the 72th 6-byte MAC
64824  * address of the station. Because the MAC address registers are configured to be
64825  * double-synchronized to the (G)MII clock domains, the synchronization is
64826  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
64827  * endian mode) of the MAC Address71 Low Register are written. For proper
64828  * synchronization updates, the consecutive writes to this Address Low Register
64829  * should be performed after at least four clock cycles in the destination clock
64830  * domain.
64831  *
64832  * Note that all MAC Address High registers (except MAC Address0 High) have the
64833  * same format.
64834  *
64835  * Register Layout
64836  *
64837  * Bits | Access | Reset | Description
64838  * :--------|:-------|:-------|:----------------------
64839  * [15:0] | RW | 0xffff | MAC Address71 [47:32]
64840  * [23:16] | ??? | 0x0 | *UNDEFINED*
64841  * [24] | RW | 0x0 | Mask Byte Control
64842  * [25] | RW | 0x0 | Mask Byte Control
64843  * [26] | RW | 0x0 | Mask Byte Control
64844  * [27] | RW | 0x0 | Mask Byte Control
64845  * [28] | RW | 0x0 | Mask Byte Control
64846  * [29] | RW | 0x0 | Mask Byte Control
64847  * [30] | RW | 0x0 | Source Address
64848  * [31] | RW | 0x0 | Address Enable
64849  *
64850  */
64851 /*
64852  * Field : MAC Address71 [47:32] - addrhi
64853  *
64854  * This field contains the upper 16 bits (47:32) of the 72th 6-byte MAC address.
64855  *
64856  * Field Access Macros:
64857  *
64858  */
64859 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
64860 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_LSB 0
64861 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
64862 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_MSB 15
64863 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
64864 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_WIDTH 16
64865 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
64866 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET_MSK 0x0000ffff
64867 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
64868 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_CLR_MSK 0xffff0000
64869 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
64870 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_RESET 0xffff
64871 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI field value from a register. */
64872 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
64873 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value suitable for setting the register. */
64874 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
64875 
64876 /*
64877  * Field : Mask Byte Control - mbc_0
64878  *
64879  * This array of bits are mask control bits for comparison of each of the MAC
64880  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64881  * received DA or SA with the contents of MAC Address71 high and low registers.
64882  * Each bit controls the masking of the bytes. You can filter a group of addresses
64883  * (known as group address filtering) by masking one or more bytes of the address.
64884  *
64885  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64886  *
64887  * Field Enumeration Values:
64888  *
64889  * Enum | Value | Description
64890  * :----------------------------------------------|:------|:------------------------------------
64891  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64892  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64893  *
64894  * Field Access Macros:
64895  *
64896  */
64897 /*
64898  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0
64899  *
64900  * Byte is unmasked (i.e. is compared)
64901  */
64902 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED 0x0
64903 /*
64904  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0
64905  *
64906  * Byte is masked (i.e. not compared)
64907  */
64908 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED 0x1
64909 
64910 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
64911 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_LSB 24
64912 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
64913 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_MSB 24
64914 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
64915 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_WIDTH 1
64916 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */
64917 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET_MSK 0x01000000
64918 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */
64919 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_CLR_MSK 0xfeffffff
64920 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
64921 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_RESET 0x0
64922 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 field value from a register. */
64923 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
64924 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value suitable for setting the register. */
64925 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
64926 
64927 /*
64928  * Field : Mask Byte Control - mbc_1
64929  *
64930  * This array of bits are mask control bits for comparison of each of the MAC
64931  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64932  * received DA or SA with the contents of MAC Address71 high and low registers.
64933  * Each bit controls the masking of the bytes. You can filter a group of addresses
64934  * (known as group address filtering) by masking one or more bytes of the address.
64935  *
64936  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64937  *
64938  * Field Enumeration Values:
64939  *
64940  * Enum | Value | Description
64941  * :----------------------------------------------|:------|:------------------------------------
64942  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64943  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64944  *
64945  * Field Access Macros:
64946  *
64947  */
64948 /*
64949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1
64950  *
64951  * Byte is unmasked (i.e. is compared)
64952  */
64953 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED 0x0
64954 /*
64955  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1
64956  *
64957  * Byte is masked (i.e. not compared)
64958  */
64959 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED 0x1
64960 
64961 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
64962 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_LSB 25
64963 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
64964 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_MSB 25
64965 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
64966 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_WIDTH 1
64967 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */
64968 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET_MSK 0x02000000
64969 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */
64970 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_CLR_MSK 0xfdffffff
64971 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
64972 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_RESET 0x0
64973 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 field value from a register. */
64974 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
64975 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value suitable for setting the register. */
64976 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
64977 
64978 /*
64979  * Field : Mask Byte Control - mbc_2
64980  *
64981  * This array of bits are mask control bits for comparison of each of the MAC
64982  * Address bytes. When masked, the MAC does not compare the corresponding byte of
64983  * received DA or SA with the contents of MAC Address71 high and low registers.
64984  * Each bit controls the masking of the bytes. You can filter a group of addresses
64985  * (known as group address filtering) by masking one or more bytes of the address.
64986  *
64987  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
64988  *
64989  * Field Enumeration Values:
64990  *
64991  * Enum | Value | Description
64992  * :----------------------------------------------|:------|:------------------------------------
64993  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
64994  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
64995  *
64996  * Field Access Macros:
64997  *
64998  */
64999 /*
65000  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2
65001  *
65002  * Byte is unmasked (i.e. is compared)
65003  */
65004 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED 0x0
65005 /*
65006  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2
65007  *
65008  * Byte is masked (i.e. not compared)
65009  */
65010 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED 0x1
65011 
65012 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
65013 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_LSB 26
65014 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
65015 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_MSB 26
65016 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
65017 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_WIDTH 1
65018 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */
65019 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET_MSK 0x04000000
65020 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */
65021 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_CLR_MSK 0xfbffffff
65022 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
65023 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_RESET 0x0
65024 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 field value from a register. */
65025 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
65026 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value suitable for setting the register. */
65027 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
65028 
65029 /*
65030  * Field : Mask Byte Control - mbc_3
65031  *
65032  * This array of bits are mask control bits for comparison of each of the MAC
65033  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65034  * received DA or SA with the contents of MAC Address71 high and low registers.
65035  * Each bit controls the masking of the bytes. You can filter a group of addresses
65036  * (known as group address filtering) by masking one or more bytes of the address.
65037  *
65038  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65039  *
65040  * Field Enumeration Values:
65041  *
65042  * Enum | Value | Description
65043  * :----------------------------------------------|:------|:------------------------------------
65044  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65045  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65046  *
65047  * Field Access Macros:
65048  *
65049  */
65050 /*
65051  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3
65052  *
65053  * Byte is unmasked (i.e. is compared)
65054  */
65055 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED 0x0
65056 /*
65057  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3
65058  *
65059  * Byte is masked (i.e. not compared)
65060  */
65061 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED 0x1
65062 
65063 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
65064 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_LSB 27
65065 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
65066 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_MSB 27
65067 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
65068 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_WIDTH 1
65069 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */
65070 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET_MSK 0x08000000
65071 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */
65072 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_CLR_MSK 0xf7ffffff
65073 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
65074 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_RESET 0x0
65075 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 field value from a register. */
65076 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
65077 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value suitable for setting the register. */
65078 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
65079 
65080 /*
65081  * Field : Mask Byte Control - mbc_4
65082  *
65083  * This array of bits are mask control bits for comparison of each of the MAC
65084  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65085  * received DA or SA with the contents of MAC Address71 high and low registers.
65086  * Each bit controls the masking of the bytes. You can filter a group of addresses
65087  * (known as group address filtering) by masking one or more bytes of the address.
65088  *
65089  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65090  *
65091  * Field Enumeration Values:
65092  *
65093  * Enum | Value | Description
65094  * :----------------------------------------------|:------|:------------------------------------
65095  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65096  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65097  *
65098  * Field Access Macros:
65099  *
65100  */
65101 /*
65102  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4
65103  *
65104  * Byte is unmasked (i.e. is compared)
65105  */
65106 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED 0x0
65107 /*
65108  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4
65109  *
65110  * Byte is masked (i.e. not compared)
65111  */
65112 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED 0x1
65113 
65114 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
65115 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_LSB 28
65116 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
65117 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_MSB 28
65118 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
65119 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_WIDTH 1
65120 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */
65121 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET_MSK 0x10000000
65122 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */
65123 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_CLR_MSK 0xefffffff
65124 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
65125 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_RESET 0x0
65126 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 field value from a register. */
65127 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
65128 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value suitable for setting the register. */
65129 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
65130 
65131 /*
65132  * Field : Mask Byte Control - mbc_5
65133  *
65134  * This array of bits are mask control bits for comparison of each of the MAC
65135  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65136  * received DA or SA with the contents of MAC Address71 high and low registers.
65137  * Each bit controls the masking of the bytes. You can filter a group of addresses
65138  * (known as group address filtering) by masking one or more bytes of the address.
65139  *
65140  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65141  *
65142  * Field Enumeration Values:
65143  *
65144  * Enum | Value | Description
65145  * :----------------------------------------------|:------|:------------------------------------
65146  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65147  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65148  *
65149  * Field Access Macros:
65150  *
65151  */
65152 /*
65153  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5
65154  *
65155  * Byte is unmasked (i.e. is compared)
65156  */
65157 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED 0x0
65158 /*
65159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5
65160  *
65161  * Byte is masked (i.e. not compared)
65162  */
65163 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED 0x1
65164 
65165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
65166 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_LSB 29
65167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
65168 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_MSB 29
65169 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
65170 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_WIDTH 1
65171 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */
65172 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET_MSK 0x20000000
65173 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */
65174 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_CLR_MSK 0xdfffffff
65175 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
65176 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_RESET 0x0
65177 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 field value from a register. */
65178 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
65179 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value suitable for setting the register. */
65180 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
65181 
65182 /*
65183  * Field : Source Address - sa
65184  *
65185  * When this bit is enabled, the MAC Address71[47:0] is used to compare with the SA
65186  * fields of the received frame. When this bit is disabled, the MAC Address71[47:0]
65187  * is used to compare with the DA fields of the received frame.
65188  *
65189  * Field Enumeration Values:
65190  *
65191  * Enum | Value | Description
65192  * :----------------------------------------|:------|:-----------------------------
65193  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
65194  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END | 0x1 | MAC address compare enabled
65195  *
65196  * Field Access Macros:
65197  *
65198  */
65199 /*
65200  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA
65201  *
65202  * MAC address compare disabled
65203  */
65204 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD 0x0
65205 /*
65206  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA
65207  *
65208  * MAC address compare enabled
65209  */
65210 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END 0x1
65211 
65212 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
65213 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_LSB 30
65214 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
65215 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_MSB 30
65216 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
65217 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_WIDTH 1
65218 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */
65219 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET_MSK 0x40000000
65220 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */
65221 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_CLR_MSK 0xbfffffff
65222 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
65223 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_RESET 0x0
65224 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA field value from a register. */
65225 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
65226 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value suitable for setting the register. */
65227 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
65228 
65229 /*
65230  * Field : Address Enable - ae
65231  *
65232  * When this bit is enabled, the address filter block uses the 72th MAC address for
65233  * perfect filtering. When this bit is disabled, the address filter block ignores
65234  * the address for filtering.
65235  *
65236  * Field Enumeration Values:
65237  *
65238  * Enum | Value | Description
65239  * :----------------------------------------|:------|:--------------------------------------
65240  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
65241  * ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
65242  *
65243  * Field Access Macros:
65244  *
65245  */
65246 /*
65247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
65248  *
65249  * Second MAC address filtering disabled
65250  */
65251 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD 0x0
65252 /*
65253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
65254  *
65255  * Second MAC address filtering enabled
65256  */
65257 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END 0x1
65258 
65259 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
65260 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_LSB 31
65261 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
65262 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_MSB 31
65263 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
65264 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_WIDTH 1
65265 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
65266 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET_MSK 0x80000000
65267 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
65268 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_CLR_MSK 0x7fffffff
65269 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
65270 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_RESET 0x0
65271 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE field value from a register. */
65272 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65273 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value suitable for setting the register. */
65274 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65275 
65276 #ifndef __ASSEMBLY__
65277 /*
65278  * WARNING: The C register and register group struct declarations are provided for
65279  * convenience and illustrative purposes. They should, however, be used with
65280  * caution as the C language standard provides no guarantees about the alignment or
65281  * atomicity of device memory accesses. The recommended practice for writing
65282  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65283  * alt_write_word() functions.
65284  *
65285  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH.
65286  */
65287 struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s
65288 {
65289  uint32_t addrhi : 16; /* MAC Address71 [47:32] */
65290  uint32_t : 8; /* *UNDEFINED* */
65291  uint32_t mbc_0 : 1; /* Mask Byte Control */
65292  uint32_t mbc_1 : 1; /* Mask Byte Control */
65293  uint32_t mbc_2 : 1; /* Mask Byte Control */
65294  uint32_t mbc_3 : 1; /* Mask Byte Control */
65295  uint32_t mbc_4 : 1; /* Mask Byte Control */
65296  uint32_t mbc_5 : 1; /* Mask Byte Control */
65297  uint32_t sa : 1; /* Source Address */
65298  uint32_t ae : 1; /* Address Enable */
65299 };
65300 
65301 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH. */
65302 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t;
65303 #endif /* __ASSEMBLY__ */
65304 
65305 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register from the beginning of the component. */
65306 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST 0x9b8
65307 /* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register. */
65308 #define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST))
65309 
65310 /*
65311  * Register : Register 623 (MAC Address71 Low Register) - MAC_Address71_Low
65312  *
65313  * The MAC Address71 Low register holds the lower 32 bits of the 72th 6-byte MAC
65314  * address of the station.
65315  *
65316  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
65317  * format.
65318  *
65319  * Register Layout
65320  *
65321  * Bits | Access | Reset | Description
65322  * :-------|:-------|:-----------|:---------------------
65323  * [31:0] | RW | 0xffffffff | MAC Address71 [31:0]
65324  *
65325  */
65326 /*
65327  * Field : MAC Address71 [31:0] - addrlo
65328  *
65329  * This field contains the lower 32 bits of the 72th 6-byte MAC address. The
65330  * content of this field is undefined until loaded by software after the
65331  * initialization process.
65332  *
65333  * Field Access Macros:
65334  *
65335  */
65336 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
65337 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_LSB 0
65338 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
65339 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_MSB 31
65340 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
65341 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_WIDTH 32
65342 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
65343 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET_MSK 0xffffffff
65344 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
65345 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_CLR_MSK 0x00000000
65346 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
65347 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_RESET 0xffffffff
65348 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO field value from a register. */
65349 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65350 /* Produces a ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value suitable for setting the register. */
65351 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65352 
65353 #ifndef __ASSEMBLY__
65354 /*
65355  * WARNING: The C register and register group struct declarations are provided for
65356  * convenience and illustrative purposes. They should, however, be used with
65357  * caution as the C language standard provides no guarantees about the alignment or
65358  * atomicity of device memory accesses. The recommended practice for writing
65359  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65360  * alt_write_word() functions.
65361  *
65362  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW.
65363  */
65364 struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s
65365 {
65366  uint32_t addrlo : 32; /* MAC Address71 [31:0] */
65367 };
65368 
65369 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW. */
65370 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s ALT_EMAC_GMAC_MAC_ADDR71_LOW_t;
65371 #endif /* __ASSEMBLY__ */
65372 
65373 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register from the beginning of the component. */
65374 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST 0x9bc
65375 /* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register. */
65376 #define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST))
65377 
65378 /*
65379  * Register : Register 624 (MAC Address72 High Register) - MAC_Address72_High
65380  *
65381  * The MAC Address72 High register holds the upper 16 bits of the 73th 6-byte MAC
65382  * address of the station. Because the MAC address registers are configured to be
65383  * double-synchronized to the (G)MII clock domains, the synchronization is
65384  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
65385  * endian mode) of the MAC Address72 Low Register are written. For proper
65386  * synchronization updates, the consecutive writes to this Address Low Register
65387  * should be performed after at least four clock cycles in the destination clock
65388  * domain.
65389  *
65390  * Note that all MAC Address High registers (except MAC Address0 High) have the
65391  * same format.
65392  *
65393  * Register Layout
65394  *
65395  * Bits | Access | Reset | Description
65396  * :--------|:-------|:-------|:----------------------
65397  * [15:0] | RW | 0xffff | MAC Address72 [47:32]
65398  * [23:16] | ??? | 0x0 | *UNDEFINED*
65399  * [24] | RW | 0x0 | Mask Byte Control
65400  * [25] | RW | 0x0 | Mask Byte Control
65401  * [26] | RW | 0x0 | Mask Byte Control
65402  * [27] | RW | 0x0 | Mask Byte Control
65403  * [28] | RW | 0x0 | Mask Byte Control
65404  * [29] | RW | 0x0 | Mask Byte Control
65405  * [30] | RW | 0x0 | Source Address
65406  * [31] | RW | 0x0 | Address Enable
65407  *
65408  */
65409 /*
65410  * Field : MAC Address72 [47:32] - addrhi
65411  *
65412  * This field contains the upper 16 bits (47:32) of the 73th 6-byte MAC address.
65413  *
65414  * Field Access Macros:
65415  *
65416  */
65417 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
65418 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_LSB 0
65419 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
65420 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_MSB 15
65421 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
65422 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_WIDTH 16
65423 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
65424 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET_MSK 0x0000ffff
65425 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
65426 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_CLR_MSK 0xffff0000
65427 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
65428 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_RESET 0xffff
65429 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI field value from a register. */
65430 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65431 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value suitable for setting the register. */
65432 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65433 
65434 /*
65435  * Field : Mask Byte Control - mbc_0
65436  *
65437  * This array of bits are mask control bits for comparison of each of the MAC
65438  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65439  * received DA or SA with the contents of MAC Address72 high and low registers.
65440  * Each bit controls the masking of the bytes. You can filter a group of addresses
65441  * (known as group address filtering) by masking one or more bytes of the address.
65442  *
65443  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65444  *
65445  * Field Enumeration Values:
65446  *
65447  * Enum | Value | Description
65448  * :----------------------------------------------|:------|:------------------------------------
65449  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65450  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65451  *
65452  * Field Access Macros:
65453  *
65454  */
65455 /*
65456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0
65457  *
65458  * Byte is unmasked (i.e. is compared)
65459  */
65460 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED 0x0
65461 /*
65462  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0
65463  *
65464  * Byte is masked (i.e. not compared)
65465  */
65466 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED 0x1
65467 
65468 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
65469 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_LSB 24
65470 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
65471 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_MSB 24
65472 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
65473 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_WIDTH 1
65474 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */
65475 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET_MSK 0x01000000
65476 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */
65477 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_CLR_MSK 0xfeffffff
65478 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
65479 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_RESET 0x0
65480 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 field value from a register. */
65481 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
65482 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value suitable for setting the register. */
65483 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
65484 
65485 /*
65486  * Field : Mask Byte Control - mbc_1
65487  *
65488  * This array of bits are mask control bits for comparison of each of the MAC
65489  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65490  * received DA or SA with the contents of MAC Address72 high and low registers.
65491  * Each bit controls the masking of the bytes. You can filter a group of addresses
65492  * (known as group address filtering) by masking one or more bytes of the address.
65493  *
65494  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65495  *
65496  * Field Enumeration Values:
65497  *
65498  * Enum | Value | Description
65499  * :----------------------------------------------|:------|:------------------------------------
65500  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65501  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65502  *
65503  * Field Access Macros:
65504  *
65505  */
65506 /*
65507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1
65508  *
65509  * Byte is unmasked (i.e. is compared)
65510  */
65511 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED 0x0
65512 /*
65513  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1
65514  *
65515  * Byte is masked (i.e. not compared)
65516  */
65517 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED 0x1
65518 
65519 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
65520 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_LSB 25
65521 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
65522 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_MSB 25
65523 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
65524 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_WIDTH 1
65525 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */
65526 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET_MSK 0x02000000
65527 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */
65528 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_CLR_MSK 0xfdffffff
65529 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
65530 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_RESET 0x0
65531 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 field value from a register. */
65532 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
65533 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value suitable for setting the register. */
65534 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
65535 
65536 /*
65537  * Field : Mask Byte Control - mbc_2
65538  *
65539  * This array of bits are mask control bits for comparison of each of the MAC
65540  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65541  * received DA or SA with the contents of MAC Address72 high and low registers.
65542  * Each bit controls the masking of the bytes. You can filter a group of addresses
65543  * (known as group address filtering) by masking one or more bytes of the address.
65544  *
65545  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65546  *
65547  * Field Enumeration Values:
65548  *
65549  * Enum | Value | Description
65550  * :----------------------------------------------|:------|:------------------------------------
65551  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65552  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65553  *
65554  * Field Access Macros:
65555  *
65556  */
65557 /*
65558  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2
65559  *
65560  * Byte is unmasked (i.e. is compared)
65561  */
65562 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED 0x0
65563 /*
65564  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2
65565  *
65566  * Byte is masked (i.e. not compared)
65567  */
65568 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED 0x1
65569 
65570 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
65571 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_LSB 26
65572 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
65573 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_MSB 26
65574 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
65575 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_WIDTH 1
65576 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */
65577 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET_MSK 0x04000000
65578 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */
65579 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_CLR_MSK 0xfbffffff
65580 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
65581 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_RESET 0x0
65582 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 field value from a register. */
65583 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
65584 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value suitable for setting the register. */
65585 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
65586 
65587 /*
65588  * Field : Mask Byte Control - mbc_3
65589  *
65590  * This array of bits are mask control bits for comparison of each of the MAC
65591  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65592  * received DA or SA with the contents of MAC Address72 high and low registers.
65593  * Each bit controls the masking of the bytes. You can filter a group of addresses
65594  * (known as group address filtering) by masking one or more bytes of the address.
65595  *
65596  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65597  *
65598  * Field Enumeration Values:
65599  *
65600  * Enum | Value | Description
65601  * :----------------------------------------------|:------|:------------------------------------
65602  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65603  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65604  *
65605  * Field Access Macros:
65606  *
65607  */
65608 /*
65609  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3
65610  *
65611  * Byte is unmasked (i.e. is compared)
65612  */
65613 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED 0x0
65614 /*
65615  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3
65616  *
65617  * Byte is masked (i.e. not compared)
65618  */
65619 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED 0x1
65620 
65621 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
65622 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_LSB 27
65623 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
65624 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_MSB 27
65625 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
65626 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_WIDTH 1
65627 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */
65628 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET_MSK 0x08000000
65629 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */
65630 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_CLR_MSK 0xf7ffffff
65631 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
65632 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_RESET 0x0
65633 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 field value from a register. */
65634 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
65635 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value suitable for setting the register. */
65636 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
65637 
65638 /*
65639  * Field : Mask Byte Control - mbc_4
65640  *
65641  * This array of bits are mask control bits for comparison of each of the MAC
65642  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65643  * received DA or SA with the contents of MAC Address72 high and low registers.
65644  * Each bit controls the masking of the bytes. You can filter a group of addresses
65645  * (known as group address filtering) by masking one or more bytes of the address.
65646  *
65647  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65648  *
65649  * Field Enumeration Values:
65650  *
65651  * Enum | Value | Description
65652  * :----------------------------------------------|:------|:------------------------------------
65653  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65654  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65655  *
65656  * Field Access Macros:
65657  *
65658  */
65659 /*
65660  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4
65661  *
65662  * Byte is unmasked (i.e. is compared)
65663  */
65664 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED 0x0
65665 /*
65666  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4
65667  *
65668  * Byte is masked (i.e. not compared)
65669  */
65670 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED 0x1
65671 
65672 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
65673 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_LSB 28
65674 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
65675 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_MSB 28
65676 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
65677 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_WIDTH 1
65678 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */
65679 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET_MSK 0x10000000
65680 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */
65681 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_CLR_MSK 0xefffffff
65682 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
65683 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_RESET 0x0
65684 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 field value from a register. */
65685 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
65686 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value suitable for setting the register. */
65687 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
65688 
65689 /*
65690  * Field : Mask Byte Control - mbc_5
65691  *
65692  * This array of bits are mask control bits for comparison of each of the MAC
65693  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65694  * received DA or SA with the contents of MAC Address72 high and low registers.
65695  * Each bit controls the masking of the bytes. You can filter a group of addresses
65696  * (known as group address filtering) by masking one or more bytes of the address.
65697  *
65698  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
65699  *
65700  * Field Enumeration Values:
65701  *
65702  * Enum | Value | Description
65703  * :----------------------------------------------|:------|:------------------------------------
65704  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
65705  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
65706  *
65707  * Field Access Macros:
65708  *
65709  */
65710 /*
65711  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5
65712  *
65713  * Byte is unmasked (i.e. is compared)
65714  */
65715 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED 0x0
65716 /*
65717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5
65718  *
65719  * Byte is masked (i.e. not compared)
65720  */
65721 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED 0x1
65722 
65723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
65724 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_LSB 29
65725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
65726 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_MSB 29
65727 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
65728 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_WIDTH 1
65729 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */
65730 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET_MSK 0x20000000
65731 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */
65732 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_CLR_MSK 0xdfffffff
65733 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
65734 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_RESET 0x0
65735 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 field value from a register. */
65736 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
65737 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value suitable for setting the register. */
65738 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
65739 
65740 /*
65741  * Field : Source Address - sa
65742  *
65743  * When this bit is enabled, the MAC Address72[47:0] is used to compare with the SA
65744  * fields of the received frame. When this bit is disabled, the MAC Address72[47:0]
65745  * is used to compare with the DA fields of the received frame.
65746  *
65747  * Field Enumeration Values:
65748  *
65749  * Enum | Value | Description
65750  * :----------------------------------------|:------|:-----------------------------
65751  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
65752  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END | 0x1 | MAC address compare enabled
65753  *
65754  * Field Access Macros:
65755  *
65756  */
65757 /*
65758  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA
65759  *
65760  * MAC address compare disabled
65761  */
65762 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD 0x0
65763 /*
65764  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA
65765  *
65766  * MAC address compare enabled
65767  */
65768 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END 0x1
65769 
65770 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
65771 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_LSB 30
65772 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
65773 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_MSB 30
65774 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
65775 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_WIDTH 1
65776 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */
65777 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET_MSK 0x40000000
65778 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */
65779 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_CLR_MSK 0xbfffffff
65780 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
65781 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_RESET 0x0
65782 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA field value from a register. */
65783 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
65784 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value suitable for setting the register. */
65785 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
65786 
65787 /*
65788  * Field : Address Enable - ae
65789  *
65790  * When this bit is enabled, the address filter block uses the 73th MAC address for
65791  * perfect filtering. When this bit is disabled, the address filter block ignores
65792  * the address for filtering.
65793  *
65794  * Field Enumeration Values:
65795  *
65796  * Enum | Value | Description
65797  * :----------------------------------------|:------|:--------------------------------------
65798  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
65799  * ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
65800  *
65801  * Field Access Macros:
65802  *
65803  */
65804 /*
65805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
65806  *
65807  * Second MAC address filtering disabled
65808  */
65809 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD 0x0
65810 /*
65811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
65812  *
65813  * Second MAC address filtering enabled
65814  */
65815 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END 0x1
65816 
65817 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
65818 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_LSB 31
65819 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
65820 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_MSB 31
65821 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
65822 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_WIDTH 1
65823 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
65824 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET_MSK 0x80000000
65825 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
65826 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_CLR_MSK 0x7fffffff
65827 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
65828 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_RESET 0x0
65829 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE field value from a register. */
65830 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
65831 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value suitable for setting the register. */
65832 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
65833 
65834 #ifndef __ASSEMBLY__
65835 /*
65836  * WARNING: The C register and register group struct declarations are provided for
65837  * convenience and illustrative purposes. They should, however, be used with
65838  * caution as the C language standard provides no guarantees about the alignment or
65839  * atomicity of device memory accesses. The recommended practice for writing
65840  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65841  * alt_write_word() functions.
65842  *
65843  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH.
65844  */
65845 struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s
65846 {
65847  uint32_t addrhi : 16; /* MAC Address72 [47:32] */
65848  uint32_t : 8; /* *UNDEFINED* */
65849  uint32_t mbc_0 : 1; /* Mask Byte Control */
65850  uint32_t mbc_1 : 1; /* Mask Byte Control */
65851  uint32_t mbc_2 : 1; /* Mask Byte Control */
65852  uint32_t mbc_3 : 1; /* Mask Byte Control */
65853  uint32_t mbc_4 : 1; /* Mask Byte Control */
65854  uint32_t mbc_5 : 1; /* Mask Byte Control */
65855  uint32_t sa : 1; /* Source Address */
65856  uint32_t ae : 1; /* Address Enable */
65857 };
65858 
65859 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH. */
65860 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t;
65861 #endif /* __ASSEMBLY__ */
65862 
65863 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register from the beginning of the component. */
65864 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST 0x9c0
65865 /* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register. */
65866 #define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST))
65867 
65868 /*
65869  * Register : Register 625 (MAC Address72 Low Register) - MAC_Address72_Low
65870  *
65871  * The MAC Address72 Low register holds the lower 32 bits of the 73th 6-byte MAC
65872  * address of the station.
65873  *
65874  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
65875  * format.
65876  *
65877  * Register Layout
65878  *
65879  * Bits | Access | Reset | Description
65880  * :-------|:-------|:-----------|:---------------------
65881  * [31:0] | RW | 0xffffffff | MAC Address72 [31:0]
65882  *
65883  */
65884 /*
65885  * Field : MAC Address72 [31:0] - addrlo
65886  *
65887  * This field contains the lower 32 bits of the 73th 6-byte MAC address. The
65888  * content of this field is undefined until loaded by software after the
65889  * initialization process.
65890  *
65891  * Field Access Macros:
65892  *
65893  */
65894 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
65895 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_LSB 0
65896 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
65897 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_MSB 31
65898 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
65899 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_WIDTH 32
65900 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
65901 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET_MSK 0xffffffff
65902 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
65903 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_CLR_MSK 0x00000000
65904 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
65905 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_RESET 0xffffffff
65906 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO field value from a register. */
65907 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
65908 /* Produces a ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value suitable for setting the register. */
65909 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
65910 
65911 #ifndef __ASSEMBLY__
65912 /*
65913  * WARNING: The C register and register group struct declarations are provided for
65914  * convenience and illustrative purposes. They should, however, be used with
65915  * caution as the C language standard provides no guarantees about the alignment or
65916  * atomicity of device memory accesses. The recommended practice for writing
65917  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
65918  * alt_write_word() functions.
65919  *
65920  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW.
65921  */
65922 struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s
65923 {
65924  uint32_t addrlo : 32; /* MAC Address72 [31:0] */
65925 };
65926 
65927 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW. */
65928 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s ALT_EMAC_GMAC_MAC_ADDR72_LOW_t;
65929 #endif /* __ASSEMBLY__ */
65930 
65931 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register from the beginning of the component. */
65932 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST 0x9c4
65933 /* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register. */
65934 #define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST))
65935 
65936 /*
65937  * Register : Register 626 (MAC Address73 High Register) - MAC_Address73_High
65938  *
65939  * The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC
65940  * address of the station. Because the MAC address registers are configured to be
65941  * double-synchronized to the (G)MII clock domains, the synchronization is
65942  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
65943  * endian mode) of the MAC Address73 Low Register are written. For proper
65944  * synchronization updates, the consecutive writes to this Address Low Register
65945  * should be performed after at least four clock cycles in the destination clock
65946  * domain.
65947  *
65948  * Note that all MAC Address High registers (except MAC Address0 High) have the
65949  * same format.
65950  *
65951  * Register Layout
65952  *
65953  * Bits | Access | Reset | Description
65954  * :--------|:-------|:-------|:----------------------
65955  * [15:0] | RW | 0xffff | MAC Address73 [47:32]
65956  * [23:16] | ??? | 0x0 | *UNDEFINED*
65957  * [24] | RW | 0x0 | Mask Byte Control
65958  * [25] | RW | 0x0 | Mask Byte Control
65959  * [26] | RW | 0x0 | Mask Byte Control
65960  * [27] | RW | 0x0 | Mask Byte Control
65961  * [28] | RW | 0x0 | Mask Byte Control
65962  * [29] | RW | 0x0 | Mask Byte Control
65963  * [30] | RW | 0x0 | Source Address
65964  * [31] | RW | 0x0 | Address Enable
65965  *
65966  */
65967 /*
65968  * Field : MAC Address73 [47:32] - addrhi
65969  *
65970  * This field contains the upper 16 bits (47:32) of the 74th 6-byte MAC address.
65971  *
65972  * Field Access Macros:
65973  *
65974  */
65975 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
65976 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_LSB 0
65977 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
65978 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_MSB 15
65979 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
65980 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_WIDTH 16
65981 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
65982 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET_MSK 0x0000ffff
65983 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
65984 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_CLR_MSK 0xffff0000
65985 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
65986 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_RESET 0xffff
65987 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI field value from a register. */
65988 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
65989 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value suitable for setting the register. */
65990 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
65991 
65992 /*
65993  * Field : Mask Byte Control - mbc_0
65994  *
65995  * This array of bits are mask control bits for comparison of each of the MAC
65996  * Address bytes. When masked, the MAC does not compare the corresponding byte of
65997  * received DA or SA with the contents of MAC Address73 high and low registers.
65998  * Each bit controls the masking of the bytes. You can filter a group of addresses
65999  * (known as group address filtering) by masking one or more bytes of the address.
66000  *
66001  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66002  *
66003  * Field Enumeration Values:
66004  *
66005  * Enum | Value | Description
66006  * :----------------------------------------------|:------|:------------------------------------
66007  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66008  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66009  *
66010  * Field Access Macros:
66011  *
66012  */
66013 /*
66014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0
66015  *
66016  * Byte is unmasked (i.e. is compared)
66017  */
66018 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED 0x0
66019 /*
66020  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0
66021  *
66022  * Byte is masked (i.e. not compared)
66023  */
66024 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED 0x1
66025 
66026 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
66027 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_LSB 24
66028 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
66029 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_MSB 24
66030 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
66031 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_WIDTH 1
66032 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */
66033 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET_MSK 0x01000000
66034 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */
66035 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_CLR_MSK 0xfeffffff
66036 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
66037 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_RESET 0x0
66038 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 field value from a register. */
66039 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
66040 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value suitable for setting the register. */
66041 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
66042 
66043 /*
66044  * Field : Mask Byte Control - mbc_1
66045  *
66046  * This array of bits are mask control bits for comparison of each of the MAC
66047  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66048  * received DA or SA with the contents of MAC Address73 high and low registers.
66049  * Each bit controls the masking of the bytes. You can filter a group of addresses
66050  * (known as group address filtering) by masking one or more bytes of the address.
66051  *
66052  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66053  *
66054  * Field Enumeration Values:
66055  *
66056  * Enum | Value | Description
66057  * :----------------------------------------------|:------|:------------------------------------
66058  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66059  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66060  *
66061  * Field Access Macros:
66062  *
66063  */
66064 /*
66065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1
66066  *
66067  * Byte is unmasked (i.e. is compared)
66068  */
66069 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED 0x0
66070 /*
66071  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1
66072  *
66073  * Byte is masked (i.e. not compared)
66074  */
66075 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED 0x1
66076 
66077 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
66078 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_LSB 25
66079 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
66080 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_MSB 25
66081 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
66082 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_WIDTH 1
66083 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */
66084 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET_MSK 0x02000000
66085 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */
66086 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_CLR_MSK 0xfdffffff
66087 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
66088 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_RESET 0x0
66089 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 field value from a register. */
66090 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
66091 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value suitable for setting the register. */
66092 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
66093 
66094 /*
66095  * Field : Mask Byte Control - mbc_2
66096  *
66097  * This array of bits are mask control bits for comparison of each of the MAC
66098  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66099  * received DA or SA with the contents of MAC Address73 high and low registers.
66100  * Each bit controls the masking of the bytes. You can filter a group of addresses
66101  * (known as group address filtering) by masking one or more bytes of the address.
66102  *
66103  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66104  *
66105  * Field Enumeration Values:
66106  *
66107  * Enum | Value | Description
66108  * :----------------------------------------------|:------|:------------------------------------
66109  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66110  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66111  *
66112  * Field Access Macros:
66113  *
66114  */
66115 /*
66116  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2
66117  *
66118  * Byte is unmasked (i.e. is compared)
66119  */
66120 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED 0x0
66121 /*
66122  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2
66123  *
66124  * Byte is masked (i.e. not compared)
66125  */
66126 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED 0x1
66127 
66128 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
66129 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_LSB 26
66130 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
66131 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_MSB 26
66132 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
66133 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_WIDTH 1
66134 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */
66135 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET_MSK 0x04000000
66136 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */
66137 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_CLR_MSK 0xfbffffff
66138 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
66139 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_RESET 0x0
66140 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 field value from a register. */
66141 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
66142 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value suitable for setting the register. */
66143 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
66144 
66145 /*
66146  * Field : Mask Byte Control - mbc_3
66147  *
66148  * This array of bits are mask control bits for comparison of each of the MAC
66149  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66150  * received DA or SA with the contents of MAC Address73 high and low registers.
66151  * Each bit controls the masking of the bytes. You can filter a group of addresses
66152  * (known as group address filtering) by masking one or more bytes of the address.
66153  *
66154  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66155  *
66156  * Field Enumeration Values:
66157  *
66158  * Enum | Value | Description
66159  * :----------------------------------------------|:------|:------------------------------------
66160  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66161  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66162  *
66163  * Field Access Macros:
66164  *
66165  */
66166 /*
66167  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3
66168  *
66169  * Byte is unmasked (i.e. is compared)
66170  */
66171 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED 0x0
66172 /*
66173  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3
66174  *
66175  * Byte is masked (i.e. not compared)
66176  */
66177 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED 0x1
66178 
66179 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
66180 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_LSB 27
66181 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
66182 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_MSB 27
66183 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
66184 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_WIDTH 1
66185 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */
66186 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET_MSK 0x08000000
66187 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */
66188 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_CLR_MSK 0xf7ffffff
66189 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
66190 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_RESET 0x0
66191 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 field value from a register. */
66192 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
66193 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value suitable for setting the register. */
66194 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
66195 
66196 /*
66197  * Field : Mask Byte Control - mbc_4
66198  *
66199  * This array of bits are mask control bits for comparison of each of the MAC
66200  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66201  * received DA or SA with the contents of MAC Address73 high and low registers.
66202  * Each bit controls the masking of the bytes. You can filter a group of addresses
66203  * (known as group address filtering) by masking one or more bytes of the address.
66204  *
66205  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66206  *
66207  * Field Enumeration Values:
66208  *
66209  * Enum | Value | Description
66210  * :----------------------------------------------|:------|:------------------------------------
66211  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66212  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66213  *
66214  * Field Access Macros:
66215  *
66216  */
66217 /*
66218  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4
66219  *
66220  * Byte is unmasked (i.e. is compared)
66221  */
66222 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED 0x0
66223 /*
66224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4
66225  *
66226  * Byte is masked (i.e. not compared)
66227  */
66228 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED 0x1
66229 
66230 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
66231 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_LSB 28
66232 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
66233 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_MSB 28
66234 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
66235 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_WIDTH 1
66236 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */
66237 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET_MSK 0x10000000
66238 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */
66239 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_CLR_MSK 0xefffffff
66240 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
66241 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_RESET 0x0
66242 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 field value from a register. */
66243 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
66244 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value suitable for setting the register. */
66245 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
66246 
66247 /*
66248  * Field : Mask Byte Control - mbc_5
66249  *
66250  * This array of bits are mask control bits for comparison of each of the MAC
66251  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66252  * received DA or SA with the contents of MAC Address73 high and low registers.
66253  * Each bit controls the masking of the bytes. You can filter a group of addresses
66254  * (known as group address filtering) by masking one or more bytes of the address.
66255  *
66256  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66257  *
66258  * Field Enumeration Values:
66259  *
66260  * Enum | Value | Description
66261  * :----------------------------------------------|:------|:------------------------------------
66262  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66263  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66264  *
66265  * Field Access Macros:
66266  *
66267  */
66268 /*
66269  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5
66270  *
66271  * Byte is unmasked (i.e. is compared)
66272  */
66273 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED 0x0
66274 /*
66275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5
66276  *
66277  * Byte is masked (i.e. not compared)
66278  */
66279 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED 0x1
66280 
66281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
66282 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_LSB 29
66283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
66284 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_MSB 29
66285 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
66286 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_WIDTH 1
66287 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */
66288 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET_MSK 0x20000000
66289 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */
66290 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_CLR_MSK 0xdfffffff
66291 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
66292 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_RESET 0x0
66293 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 field value from a register. */
66294 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
66295 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value suitable for setting the register. */
66296 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
66297 
66298 /*
66299  * Field : Source Address - sa
66300  *
66301  * When this bit is enabled, the MAC Address73[47:0] is used to compare with the SA
66302  * fields of the received frame. When this bit is disabled, the MAC Address73[47:0]
66303  * is used to compare with the DA fields of the received frame.
66304  *
66305  * Field Enumeration Values:
66306  *
66307  * Enum | Value | Description
66308  * :----------------------------------------|:------|:-----------------------------
66309  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
66310  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END | 0x1 | MAC address compare enabled
66311  *
66312  * Field Access Macros:
66313  *
66314  */
66315 /*
66316  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA
66317  *
66318  * MAC address compare disabled
66319  */
66320 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD 0x0
66321 /*
66322  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA
66323  *
66324  * MAC address compare enabled
66325  */
66326 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END 0x1
66327 
66328 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
66329 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_LSB 30
66330 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
66331 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_MSB 30
66332 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
66333 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_WIDTH 1
66334 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */
66335 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET_MSK 0x40000000
66336 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */
66337 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_CLR_MSK 0xbfffffff
66338 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
66339 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_RESET 0x0
66340 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA field value from a register. */
66341 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
66342 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value suitable for setting the register. */
66343 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
66344 
66345 /*
66346  * Field : Address Enable - ae
66347  *
66348  * When this bit is enabled, the address filter block uses the 74th MAC address for
66349  * perfect filtering. When this bit is disabled, the address filter block ignores
66350  * the address for filtering.
66351  *
66352  * Field Enumeration Values:
66353  *
66354  * Enum | Value | Description
66355  * :----------------------------------------|:------|:--------------------------------------
66356  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
66357  * ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
66358  *
66359  * Field Access Macros:
66360  *
66361  */
66362 /*
66363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
66364  *
66365  * Second MAC address filtering disabled
66366  */
66367 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD 0x0
66368 /*
66369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
66370  *
66371  * Second MAC address filtering enabled
66372  */
66373 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END 0x1
66374 
66375 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
66376 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_LSB 31
66377 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
66378 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_MSB 31
66379 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
66380 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_WIDTH 1
66381 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
66382 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET_MSK 0x80000000
66383 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
66384 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_CLR_MSK 0x7fffffff
66385 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
66386 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_RESET 0x0
66387 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE field value from a register. */
66388 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66389 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value suitable for setting the register. */
66390 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66391 
66392 #ifndef __ASSEMBLY__
66393 /*
66394  * WARNING: The C register and register group struct declarations are provided for
66395  * convenience and illustrative purposes. They should, however, be used with
66396  * caution as the C language standard provides no guarantees about the alignment or
66397  * atomicity of device memory accesses. The recommended practice for writing
66398  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66399  * alt_write_word() functions.
66400  *
66401  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH.
66402  */
66403 struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s
66404 {
66405  uint32_t addrhi : 16; /* MAC Address73 [47:32] */
66406  uint32_t : 8; /* *UNDEFINED* */
66407  uint32_t mbc_0 : 1; /* Mask Byte Control */
66408  uint32_t mbc_1 : 1; /* Mask Byte Control */
66409  uint32_t mbc_2 : 1; /* Mask Byte Control */
66410  uint32_t mbc_3 : 1; /* Mask Byte Control */
66411  uint32_t mbc_4 : 1; /* Mask Byte Control */
66412  uint32_t mbc_5 : 1; /* Mask Byte Control */
66413  uint32_t sa : 1; /* Source Address */
66414  uint32_t ae : 1; /* Address Enable */
66415 };
66416 
66417 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH. */
66418 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t;
66419 #endif /* __ASSEMBLY__ */
66420 
66421 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register from the beginning of the component. */
66422 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST 0x9c8
66423 /* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register. */
66424 #define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST))
66425 
66426 /*
66427  * Register : Register 627 (MAC Address73 Low Register) - MAC_Address73_Low
66428  *
66429  * The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC
66430  * address of the station.
66431  *
66432  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
66433  * format.
66434  *
66435  * Register Layout
66436  *
66437  * Bits | Access | Reset | Description
66438  * :-------|:-------|:-----------|:---------------------
66439  * [31:0] | RW | 0xffffffff | MAC Address73 [31:0]
66440  *
66441  */
66442 /*
66443  * Field : MAC Address73 [31:0] - addrlo
66444  *
66445  * This field contains the lower 32 bits of the 74th 6-byte MAC address. The
66446  * content of this field is undefined until loaded by software after the
66447  * initialization process.
66448  *
66449  * Field Access Macros:
66450  *
66451  */
66452 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
66453 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_LSB 0
66454 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
66455 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_MSB 31
66456 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
66457 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_WIDTH 32
66458 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
66459 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET_MSK 0xffffffff
66460 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
66461 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_CLR_MSK 0x00000000
66462 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
66463 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_RESET 0xffffffff
66464 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO field value from a register. */
66465 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
66466 /* Produces a ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value suitable for setting the register. */
66467 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
66468 
66469 #ifndef __ASSEMBLY__
66470 /*
66471  * WARNING: The C register and register group struct declarations are provided for
66472  * convenience and illustrative purposes. They should, however, be used with
66473  * caution as the C language standard provides no guarantees about the alignment or
66474  * atomicity of device memory accesses. The recommended practice for writing
66475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66476  * alt_write_word() functions.
66477  *
66478  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW.
66479  */
66480 struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s
66481 {
66482  uint32_t addrlo : 32; /* MAC Address73 [31:0] */
66483 };
66484 
66485 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW. */
66486 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s ALT_EMAC_GMAC_MAC_ADDR73_LOW_t;
66487 #endif /* __ASSEMBLY__ */
66488 
66489 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register from the beginning of the component. */
66490 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST 0x9cc
66491 /* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register. */
66492 #define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST))
66493 
66494 /*
66495  * Register : Register 628 (MAC Address74 High Register) - MAC_Address74_High
66496  *
66497  * The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC
66498  * address of the station. Because the MAC address registers are configured to be
66499  * double-synchronized to the (G)MII clock domains, the synchronization is
66500  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
66501  * endian mode) of the MAC Address74 Low Register are written. For proper
66502  * synchronization updates, the consecutive writes to this Address Low Register
66503  * should be performed after at least four clock cycles in the destination clock
66504  * domain.
66505  *
66506  * Note that all MAC Address High registers (except MAC Address0 High) have the
66507  * same format.
66508  *
66509  * Register Layout
66510  *
66511  * Bits | Access | Reset | Description
66512  * :--------|:-------|:-------|:----------------------
66513  * [15:0] | RW | 0xffff | MAC Address74 [47:32]
66514  * [23:16] | ??? | 0x0 | *UNDEFINED*
66515  * [24] | RW | 0x0 | Mask Byte Control
66516  * [25] | RW | 0x0 | Mask Byte Control
66517  * [26] | RW | 0x0 | Mask Byte Control
66518  * [27] | RW | 0x0 | Mask Byte Control
66519  * [28] | RW | 0x0 | Mask Byte Control
66520  * [29] | RW | 0x0 | Mask Byte Control
66521  * [30] | RW | 0x0 | Source Address
66522  * [31] | RW | 0x0 | Address Enable
66523  *
66524  */
66525 /*
66526  * Field : MAC Address74 [47:32] - addrhi
66527  *
66528  * This field contains the upper 16 bits (47:32) of the 75th 6-byte MAC address.
66529  *
66530  * Field Access Macros:
66531  *
66532  */
66533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
66534 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_LSB 0
66535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
66536 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_MSB 15
66537 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
66538 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_WIDTH 16
66539 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
66540 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET_MSK 0x0000ffff
66541 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
66542 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_CLR_MSK 0xffff0000
66543 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
66544 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_RESET 0xffff
66545 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI field value from a register. */
66546 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
66547 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value suitable for setting the register. */
66548 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
66549 
66550 /*
66551  * Field : Mask Byte Control - mbc_0
66552  *
66553  * This array of bits are mask control bits for comparison of each of the MAC
66554  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66555  * received DA or SA with the contents of MAC Address74 high and low registers.
66556  * Each bit controls the masking of the bytes. You can filter a group of addresses
66557  * (known as group address filtering) by masking one or more bytes of the address.
66558  *
66559  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66560  *
66561  * Field Enumeration Values:
66562  *
66563  * Enum | Value | Description
66564  * :----------------------------------------------|:------|:------------------------------------
66565  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66566  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66567  *
66568  * Field Access Macros:
66569  *
66570  */
66571 /*
66572  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0
66573  *
66574  * Byte is unmasked (i.e. is compared)
66575  */
66576 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED 0x0
66577 /*
66578  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0
66579  *
66580  * Byte is masked (i.e. not compared)
66581  */
66582 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED 0x1
66583 
66584 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
66585 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_LSB 24
66586 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
66587 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_MSB 24
66588 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
66589 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_WIDTH 1
66590 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */
66591 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET_MSK 0x01000000
66592 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */
66593 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_CLR_MSK 0xfeffffff
66594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
66595 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_RESET 0x0
66596 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 field value from a register. */
66597 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
66598 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value suitable for setting the register. */
66599 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
66600 
66601 /*
66602  * Field : Mask Byte Control - mbc_1
66603  *
66604  * This array of bits are mask control bits for comparison of each of the MAC
66605  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66606  * received DA or SA with the contents of MAC Address74 high and low registers.
66607  * Each bit controls the masking of the bytes. You can filter a group of addresses
66608  * (known as group address filtering) by masking one or more bytes of the address.
66609  *
66610  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66611  *
66612  * Field Enumeration Values:
66613  *
66614  * Enum | Value | Description
66615  * :----------------------------------------------|:------|:------------------------------------
66616  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66617  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66618  *
66619  * Field Access Macros:
66620  *
66621  */
66622 /*
66623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1
66624  *
66625  * Byte is unmasked (i.e. is compared)
66626  */
66627 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED 0x0
66628 /*
66629  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1
66630  *
66631  * Byte is masked (i.e. not compared)
66632  */
66633 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED 0x1
66634 
66635 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
66636 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_LSB 25
66637 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
66638 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_MSB 25
66639 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
66640 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_WIDTH 1
66641 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */
66642 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET_MSK 0x02000000
66643 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */
66644 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_CLR_MSK 0xfdffffff
66645 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
66646 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_RESET 0x0
66647 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 field value from a register. */
66648 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
66649 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value suitable for setting the register. */
66650 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
66651 
66652 /*
66653  * Field : Mask Byte Control - mbc_2
66654  *
66655  * This array of bits are mask control bits for comparison of each of the MAC
66656  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66657  * received DA or SA with the contents of MAC Address74 high and low registers.
66658  * Each bit controls the masking of the bytes. You can filter a group of addresses
66659  * (known as group address filtering) by masking one or more bytes of the address.
66660  *
66661  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66662  *
66663  * Field Enumeration Values:
66664  *
66665  * Enum | Value | Description
66666  * :----------------------------------------------|:------|:------------------------------------
66667  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66668  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66669  *
66670  * Field Access Macros:
66671  *
66672  */
66673 /*
66674  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2
66675  *
66676  * Byte is unmasked (i.e. is compared)
66677  */
66678 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED 0x0
66679 /*
66680  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2
66681  *
66682  * Byte is masked (i.e. not compared)
66683  */
66684 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED 0x1
66685 
66686 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
66687 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_LSB 26
66688 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
66689 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_MSB 26
66690 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
66691 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_WIDTH 1
66692 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */
66693 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET_MSK 0x04000000
66694 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */
66695 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_CLR_MSK 0xfbffffff
66696 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
66697 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_RESET 0x0
66698 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 field value from a register. */
66699 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
66700 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value suitable for setting the register. */
66701 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
66702 
66703 /*
66704  * Field : Mask Byte Control - mbc_3
66705  *
66706  * This array of bits are mask control bits for comparison of each of the MAC
66707  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66708  * received DA or SA with the contents of MAC Address74 high and low registers.
66709  * Each bit controls the masking of the bytes. You can filter a group of addresses
66710  * (known as group address filtering) by masking one or more bytes of the address.
66711  *
66712  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66713  *
66714  * Field Enumeration Values:
66715  *
66716  * Enum | Value | Description
66717  * :----------------------------------------------|:------|:------------------------------------
66718  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66719  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66720  *
66721  * Field Access Macros:
66722  *
66723  */
66724 /*
66725  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3
66726  *
66727  * Byte is unmasked (i.e. is compared)
66728  */
66729 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED 0x0
66730 /*
66731  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3
66732  *
66733  * Byte is masked (i.e. not compared)
66734  */
66735 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED 0x1
66736 
66737 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
66738 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_LSB 27
66739 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
66740 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_MSB 27
66741 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
66742 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_WIDTH 1
66743 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */
66744 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET_MSK 0x08000000
66745 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */
66746 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_CLR_MSK 0xf7ffffff
66747 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
66748 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_RESET 0x0
66749 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 field value from a register. */
66750 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
66751 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value suitable for setting the register. */
66752 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
66753 
66754 /*
66755  * Field : Mask Byte Control - mbc_4
66756  *
66757  * This array of bits are mask control bits for comparison of each of the MAC
66758  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66759  * received DA or SA with the contents of MAC Address74 high and low registers.
66760  * Each bit controls the masking of the bytes. You can filter a group of addresses
66761  * (known as group address filtering) by masking one or more bytes of the address.
66762  *
66763  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66764  *
66765  * Field Enumeration Values:
66766  *
66767  * Enum | Value | Description
66768  * :----------------------------------------------|:------|:------------------------------------
66769  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66770  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66771  *
66772  * Field Access Macros:
66773  *
66774  */
66775 /*
66776  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4
66777  *
66778  * Byte is unmasked (i.e. is compared)
66779  */
66780 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED 0x0
66781 /*
66782  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4
66783  *
66784  * Byte is masked (i.e. not compared)
66785  */
66786 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED 0x1
66787 
66788 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
66789 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_LSB 28
66790 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
66791 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_MSB 28
66792 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
66793 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_WIDTH 1
66794 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */
66795 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET_MSK 0x10000000
66796 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */
66797 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_CLR_MSK 0xefffffff
66798 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
66799 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_RESET 0x0
66800 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 field value from a register. */
66801 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
66802 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value suitable for setting the register. */
66803 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
66804 
66805 /*
66806  * Field : Mask Byte Control - mbc_5
66807  *
66808  * This array of bits are mask control bits for comparison of each of the MAC
66809  * Address bytes. When masked, the MAC does not compare the corresponding byte of
66810  * received DA or SA with the contents of MAC Address74 high and low registers.
66811  * Each bit controls the masking of the bytes. You can filter a group of addresses
66812  * (known as group address filtering) by masking one or more bytes of the address.
66813  *
66814  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
66815  *
66816  * Field Enumeration Values:
66817  *
66818  * Enum | Value | Description
66819  * :----------------------------------------------|:------|:------------------------------------
66820  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
66821  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
66822  *
66823  * Field Access Macros:
66824  *
66825  */
66826 /*
66827  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5
66828  *
66829  * Byte is unmasked (i.e. is compared)
66830  */
66831 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED 0x0
66832 /*
66833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5
66834  *
66835  * Byte is masked (i.e. not compared)
66836  */
66837 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED 0x1
66838 
66839 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
66840 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_LSB 29
66841 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
66842 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_MSB 29
66843 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
66844 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_WIDTH 1
66845 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */
66846 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET_MSK 0x20000000
66847 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */
66848 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_CLR_MSK 0xdfffffff
66849 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
66850 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_RESET 0x0
66851 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 field value from a register. */
66852 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
66853 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value suitable for setting the register. */
66854 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
66855 
66856 /*
66857  * Field : Source Address - sa
66858  *
66859  * When this bit is enabled, the MAC Address74[47:0] is used to compare with the SA
66860  * fields of the received frame. When this bit is disabled, the MAC Address74[47:0]
66861  * is used to compare with the DA fields of the received frame.
66862  *
66863  * Field Enumeration Values:
66864  *
66865  * Enum | Value | Description
66866  * :----------------------------------------|:------|:-----------------------------
66867  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
66868  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END | 0x1 | MAC address compare enabled
66869  *
66870  * Field Access Macros:
66871  *
66872  */
66873 /*
66874  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA
66875  *
66876  * MAC address compare disabled
66877  */
66878 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD 0x0
66879 /*
66880  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA
66881  *
66882  * MAC address compare enabled
66883  */
66884 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END 0x1
66885 
66886 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
66887 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_LSB 30
66888 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
66889 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_MSB 30
66890 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
66891 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_WIDTH 1
66892 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */
66893 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET_MSK 0x40000000
66894 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */
66895 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_CLR_MSK 0xbfffffff
66896 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
66897 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_RESET 0x0
66898 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA field value from a register. */
66899 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
66900 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value suitable for setting the register. */
66901 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
66902 
66903 /*
66904  * Field : Address Enable - ae
66905  *
66906  * When this bit is enabled, the address filter block uses the 75th MAC address for
66907  * perfect filtering. When this bit is disabled, the address filter block ignores
66908  * the address for filtering.
66909  *
66910  * Field Enumeration Values:
66911  *
66912  * Enum | Value | Description
66913  * :----------------------------------------|:------|:--------------------------------------
66914  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
66915  * ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
66916  *
66917  * Field Access Macros:
66918  *
66919  */
66920 /*
66921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
66922  *
66923  * Second MAC address filtering disabled
66924  */
66925 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD 0x0
66926 /*
66927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
66928  *
66929  * Second MAC address filtering enabled
66930  */
66931 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END 0x1
66932 
66933 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
66934 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_LSB 31
66935 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
66936 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_MSB 31
66937 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
66938 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_WIDTH 1
66939 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
66940 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET_MSK 0x80000000
66941 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
66942 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_CLR_MSK 0x7fffffff
66943 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
66944 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_RESET 0x0
66945 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE field value from a register. */
66946 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
66947 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value suitable for setting the register. */
66948 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
66949 
66950 #ifndef __ASSEMBLY__
66951 /*
66952  * WARNING: The C register and register group struct declarations are provided for
66953  * convenience and illustrative purposes. They should, however, be used with
66954  * caution as the C language standard provides no guarantees about the alignment or
66955  * atomicity of device memory accesses. The recommended practice for writing
66956  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
66957  * alt_write_word() functions.
66958  *
66959  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH.
66960  */
66961 struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s
66962 {
66963  uint32_t addrhi : 16; /* MAC Address74 [47:32] */
66964  uint32_t : 8; /* *UNDEFINED* */
66965  uint32_t mbc_0 : 1; /* Mask Byte Control */
66966  uint32_t mbc_1 : 1; /* Mask Byte Control */
66967  uint32_t mbc_2 : 1; /* Mask Byte Control */
66968  uint32_t mbc_3 : 1; /* Mask Byte Control */
66969  uint32_t mbc_4 : 1; /* Mask Byte Control */
66970  uint32_t mbc_5 : 1; /* Mask Byte Control */
66971  uint32_t sa : 1; /* Source Address */
66972  uint32_t ae : 1; /* Address Enable */
66973 };
66974 
66975 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH. */
66976 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t;
66977 #endif /* __ASSEMBLY__ */
66978 
66979 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register from the beginning of the component. */
66980 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST 0x9d0
66981 /* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register. */
66982 #define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST))
66983 
66984 /*
66985  * Register : Register 629 (MAC Address74 Low Register) - MAC_Address74_Low
66986  *
66987  * The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC
66988  * address of the station.
66989  *
66990  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
66991  * format.
66992  *
66993  * Register Layout
66994  *
66995  * Bits | Access | Reset | Description
66996  * :-------|:-------|:-----------|:---------------------
66997  * [31:0] | RW | 0xffffffff | MAC Address74 [31:0]
66998  *
66999  */
67000 /*
67001  * Field : MAC Address74 [31:0] - addrlo
67002  *
67003  * This field contains the lower 32 bits of the 75th 6-byte MAC address. The
67004  * content of this field is undefined until loaded by software after the
67005  * initialization process.
67006  *
67007  * Field Access Macros:
67008  *
67009  */
67010 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
67011 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_LSB 0
67012 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
67013 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_MSB 31
67014 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
67015 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_WIDTH 32
67016 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
67017 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET_MSK 0xffffffff
67018 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
67019 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_CLR_MSK 0x00000000
67020 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
67021 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_RESET 0xffffffff
67022 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO field value from a register. */
67023 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67024 /* Produces a ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value suitable for setting the register. */
67025 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67026 
67027 #ifndef __ASSEMBLY__
67028 /*
67029  * WARNING: The C register and register group struct declarations are provided for
67030  * convenience and illustrative purposes. They should, however, be used with
67031  * caution as the C language standard provides no guarantees about the alignment or
67032  * atomicity of device memory accesses. The recommended practice for writing
67033  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67034  * alt_write_word() functions.
67035  *
67036  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW.
67037  */
67038 struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s
67039 {
67040  uint32_t addrlo : 32; /* MAC Address74 [31:0] */
67041 };
67042 
67043 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW. */
67044 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s ALT_EMAC_GMAC_MAC_ADDR74_LOW_t;
67045 #endif /* __ASSEMBLY__ */
67046 
67047 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register from the beginning of the component. */
67048 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST 0x9d4
67049 /* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register. */
67050 #define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST))
67051 
67052 /*
67053  * Register : Register 630 (MAC Address75 High Register) - MAC_Address75_High
67054  *
67055  * The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC
67056  * address of the station. Because the MAC address registers are configured to be
67057  * double-synchronized to the (G)MII clock domains, the synchronization is
67058  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
67059  * endian mode) of the MAC Address75 Low Register are written. For proper
67060  * synchronization updates, the consecutive writes to this Address Low Register
67061  * should be performed after at least four clock cycles in the destination clock
67062  * domain.
67063  *
67064  * Note that all MAC Address High registers (except MAC Address0 High) have the
67065  * same format.
67066  *
67067  * Register Layout
67068  *
67069  * Bits | Access | Reset | Description
67070  * :--------|:-------|:-------|:----------------------
67071  * [15:0] | RW | 0xffff | MAC Address75 [47:32]
67072  * [23:16] | ??? | 0x0 | *UNDEFINED*
67073  * [24] | RW | 0x0 | Mask Byte Control
67074  * [25] | RW | 0x0 | Mask Byte Control
67075  * [26] | RW | 0x0 | Mask Byte Control
67076  * [27] | RW | 0x0 | Mask Byte Control
67077  * [28] | RW | 0x0 | Mask Byte Control
67078  * [29] | RW | 0x0 | Mask Byte Control
67079  * [30] | RW | 0x0 | Source Address
67080  * [31] | RW | 0x0 | Address Enable
67081  *
67082  */
67083 /*
67084  * Field : MAC Address75 [47:32] - addrhi
67085  *
67086  * This field contains the upper 16 bits (47:32) of the 76th 6-byte MAC address.
67087  *
67088  * Field Access Macros:
67089  *
67090  */
67091 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
67092 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_LSB 0
67093 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
67094 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_MSB 15
67095 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
67096 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_WIDTH 16
67097 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
67098 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET_MSK 0x0000ffff
67099 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
67100 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_CLR_MSK 0xffff0000
67101 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
67102 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_RESET 0xffff
67103 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI field value from a register. */
67104 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67105 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value suitable for setting the register. */
67106 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67107 
67108 /*
67109  * Field : Mask Byte Control - mbc_0
67110  *
67111  * This array of bits are mask control bits for comparison of each of the MAC
67112  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67113  * received DA or SA with the contents of MAC Address75 high and low registers.
67114  * Each bit controls the masking of the bytes. You can filter a group of addresses
67115  * (known as group address filtering) by masking one or more bytes of the address.
67116  *
67117  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67118  *
67119  * Field Enumeration Values:
67120  *
67121  * Enum | Value | Description
67122  * :----------------------------------------------|:------|:------------------------------------
67123  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67124  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67125  *
67126  * Field Access Macros:
67127  *
67128  */
67129 /*
67130  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0
67131  *
67132  * Byte is unmasked (i.e. is compared)
67133  */
67134 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED 0x0
67135 /*
67136  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0
67137  *
67138  * Byte is masked (i.e. not compared)
67139  */
67140 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED 0x1
67141 
67142 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
67143 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_LSB 24
67144 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
67145 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_MSB 24
67146 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
67147 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_WIDTH 1
67148 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */
67149 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET_MSK 0x01000000
67150 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */
67151 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_CLR_MSK 0xfeffffff
67152 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
67153 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_RESET 0x0
67154 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 field value from a register. */
67155 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
67156 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value suitable for setting the register. */
67157 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
67158 
67159 /*
67160  * Field : Mask Byte Control - mbc_1
67161  *
67162  * This array of bits are mask control bits for comparison of each of the MAC
67163  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67164  * received DA or SA with the contents of MAC Address75 high and low registers.
67165  * Each bit controls the masking of the bytes. You can filter a group of addresses
67166  * (known as group address filtering) by masking one or more bytes of the address.
67167  *
67168  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67169  *
67170  * Field Enumeration Values:
67171  *
67172  * Enum | Value | Description
67173  * :----------------------------------------------|:------|:------------------------------------
67174  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67175  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67176  *
67177  * Field Access Macros:
67178  *
67179  */
67180 /*
67181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1
67182  *
67183  * Byte is unmasked (i.e. is compared)
67184  */
67185 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED 0x0
67186 /*
67187  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1
67188  *
67189  * Byte is masked (i.e. not compared)
67190  */
67191 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED 0x1
67192 
67193 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
67194 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_LSB 25
67195 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
67196 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_MSB 25
67197 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
67198 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_WIDTH 1
67199 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */
67200 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET_MSK 0x02000000
67201 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */
67202 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_CLR_MSK 0xfdffffff
67203 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
67204 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_RESET 0x0
67205 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 field value from a register. */
67206 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
67207 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value suitable for setting the register. */
67208 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
67209 
67210 /*
67211  * Field : Mask Byte Control - mbc_2
67212  *
67213  * This array of bits are mask control bits for comparison of each of the MAC
67214  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67215  * received DA or SA with the contents of MAC Address75 high and low registers.
67216  * Each bit controls the masking of the bytes. You can filter a group of addresses
67217  * (known as group address filtering) by masking one or more bytes of the address.
67218  *
67219  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67220  *
67221  * Field Enumeration Values:
67222  *
67223  * Enum | Value | Description
67224  * :----------------------------------------------|:------|:------------------------------------
67225  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67226  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67227  *
67228  * Field Access Macros:
67229  *
67230  */
67231 /*
67232  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2
67233  *
67234  * Byte is unmasked (i.e. is compared)
67235  */
67236 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED 0x0
67237 /*
67238  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2
67239  *
67240  * Byte is masked (i.e. not compared)
67241  */
67242 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED 0x1
67243 
67244 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
67245 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_LSB 26
67246 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
67247 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_MSB 26
67248 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
67249 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_WIDTH 1
67250 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */
67251 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET_MSK 0x04000000
67252 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */
67253 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_CLR_MSK 0xfbffffff
67254 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
67255 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_RESET 0x0
67256 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 field value from a register. */
67257 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
67258 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value suitable for setting the register. */
67259 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
67260 
67261 /*
67262  * Field : Mask Byte Control - mbc_3
67263  *
67264  * This array of bits are mask control bits for comparison of each of the MAC
67265  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67266  * received DA or SA with the contents of MAC Address75 high and low registers.
67267  * Each bit controls the masking of the bytes. You can filter a group of addresses
67268  * (known as group address filtering) by masking one or more bytes of the address.
67269  *
67270  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67271  *
67272  * Field Enumeration Values:
67273  *
67274  * Enum | Value | Description
67275  * :----------------------------------------------|:------|:------------------------------------
67276  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67277  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67278  *
67279  * Field Access Macros:
67280  *
67281  */
67282 /*
67283  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3
67284  *
67285  * Byte is unmasked (i.e. is compared)
67286  */
67287 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED 0x0
67288 /*
67289  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3
67290  *
67291  * Byte is masked (i.e. not compared)
67292  */
67293 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED 0x1
67294 
67295 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
67296 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_LSB 27
67297 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
67298 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_MSB 27
67299 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
67300 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_WIDTH 1
67301 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */
67302 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET_MSK 0x08000000
67303 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */
67304 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_CLR_MSK 0xf7ffffff
67305 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
67306 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_RESET 0x0
67307 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 field value from a register. */
67308 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
67309 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value suitable for setting the register. */
67310 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
67311 
67312 /*
67313  * Field : Mask Byte Control - mbc_4
67314  *
67315  * This array of bits are mask control bits for comparison of each of the MAC
67316  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67317  * received DA or SA with the contents of MAC Address75 high and low registers.
67318  * Each bit controls the masking of the bytes. You can filter a group of addresses
67319  * (known as group address filtering) by masking one or more bytes of the address.
67320  *
67321  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67322  *
67323  * Field Enumeration Values:
67324  *
67325  * Enum | Value | Description
67326  * :----------------------------------------------|:------|:------------------------------------
67327  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67328  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67329  *
67330  * Field Access Macros:
67331  *
67332  */
67333 /*
67334  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4
67335  *
67336  * Byte is unmasked (i.e. is compared)
67337  */
67338 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED 0x0
67339 /*
67340  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4
67341  *
67342  * Byte is masked (i.e. not compared)
67343  */
67344 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED 0x1
67345 
67346 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
67347 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_LSB 28
67348 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
67349 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_MSB 28
67350 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
67351 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_WIDTH 1
67352 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */
67353 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET_MSK 0x10000000
67354 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */
67355 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_CLR_MSK 0xefffffff
67356 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
67357 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_RESET 0x0
67358 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 field value from a register. */
67359 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
67360 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value suitable for setting the register. */
67361 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
67362 
67363 /*
67364  * Field : Mask Byte Control - mbc_5
67365  *
67366  * This array of bits are mask control bits for comparison of each of the MAC
67367  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67368  * received DA or SA with the contents of MAC Address75 high and low registers.
67369  * Each bit controls the masking of the bytes. You can filter a group of addresses
67370  * (known as group address filtering) by masking one or more bytes of the address.
67371  *
67372  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67373  *
67374  * Field Enumeration Values:
67375  *
67376  * Enum | Value | Description
67377  * :----------------------------------------------|:------|:------------------------------------
67378  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67379  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67380  *
67381  * Field Access Macros:
67382  *
67383  */
67384 /*
67385  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5
67386  *
67387  * Byte is unmasked (i.e. is compared)
67388  */
67389 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED 0x0
67390 /*
67391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5
67392  *
67393  * Byte is masked (i.e. not compared)
67394  */
67395 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED 0x1
67396 
67397 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
67398 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_LSB 29
67399 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
67400 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_MSB 29
67401 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
67402 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_WIDTH 1
67403 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */
67404 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET_MSK 0x20000000
67405 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */
67406 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_CLR_MSK 0xdfffffff
67407 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
67408 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_RESET 0x0
67409 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 field value from a register. */
67410 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
67411 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value suitable for setting the register. */
67412 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
67413 
67414 /*
67415  * Field : Source Address - sa
67416  *
67417  * When this bit is enabled, the MAC Address75[47:0] is used to compare with the SA
67418  * fields of the received frame. When this bit is disabled, the MAC Address75[47:0]
67419  * is used to compare with the DA fields of the received frame.
67420  *
67421  * Field Enumeration Values:
67422  *
67423  * Enum | Value | Description
67424  * :----------------------------------------|:------|:-----------------------------
67425  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
67426  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END | 0x1 | MAC address compare enabled
67427  *
67428  * Field Access Macros:
67429  *
67430  */
67431 /*
67432  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA
67433  *
67434  * MAC address compare disabled
67435  */
67436 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD 0x0
67437 /*
67438  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA
67439  *
67440  * MAC address compare enabled
67441  */
67442 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END 0x1
67443 
67444 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
67445 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_LSB 30
67446 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
67447 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_MSB 30
67448 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
67449 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_WIDTH 1
67450 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */
67451 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET_MSK 0x40000000
67452 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */
67453 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_CLR_MSK 0xbfffffff
67454 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
67455 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_RESET 0x0
67456 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA field value from a register. */
67457 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
67458 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value suitable for setting the register. */
67459 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
67460 
67461 /*
67462  * Field : Address Enable - ae
67463  *
67464  * When this bit is enabled, the address filter block uses the 76th MAC address for
67465  * perfect filtering. When this bit is disabled, the address filter block ignores
67466  * the address for filtering.
67467  *
67468  * Field Enumeration Values:
67469  *
67470  * Enum | Value | Description
67471  * :----------------------------------------|:------|:--------------------------------------
67472  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
67473  * ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
67474  *
67475  * Field Access Macros:
67476  *
67477  */
67478 /*
67479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
67480  *
67481  * Second MAC address filtering disabled
67482  */
67483 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD 0x0
67484 /*
67485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
67486  *
67487  * Second MAC address filtering enabled
67488  */
67489 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END 0x1
67490 
67491 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
67492 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_LSB 31
67493 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
67494 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_MSB 31
67495 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
67496 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_WIDTH 1
67497 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
67498 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET_MSK 0x80000000
67499 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
67500 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_CLR_MSK 0x7fffffff
67501 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
67502 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_RESET 0x0
67503 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE field value from a register. */
67504 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
67505 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value suitable for setting the register. */
67506 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
67507 
67508 #ifndef __ASSEMBLY__
67509 /*
67510  * WARNING: The C register and register group struct declarations are provided for
67511  * convenience and illustrative purposes. They should, however, be used with
67512  * caution as the C language standard provides no guarantees about the alignment or
67513  * atomicity of device memory accesses. The recommended practice for writing
67514  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67515  * alt_write_word() functions.
67516  *
67517  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH.
67518  */
67519 struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s
67520 {
67521  uint32_t addrhi : 16; /* MAC Address75 [47:32] */
67522  uint32_t : 8; /* *UNDEFINED* */
67523  uint32_t mbc_0 : 1; /* Mask Byte Control */
67524  uint32_t mbc_1 : 1; /* Mask Byte Control */
67525  uint32_t mbc_2 : 1; /* Mask Byte Control */
67526  uint32_t mbc_3 : 1; /* Mask Byte Control */
67527  uint32_t mbc_4 : 1; /* Mask Byte Control */
67528  uint32_t mbc_5 : 1; /* Mask Byte Control */
67529  uint32_t sa : 1; /* Source Address */
67530  uint32_t ae : 1; /* Address Enable */
67531 };
67532 
67533 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH. */
67534 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t;
67535 #endif /* __ASSEMBLY__ */
67536 
67537 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register from the beginning of the component. */
67538 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST 0x9d8
67539 /* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register. */
67540 #define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST))
67541 
67542 /*
67543  * Register : Register 631 (MAC Address75 Low Register) - MAC_Address75_Low
67544  *
67545  * The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC
67546  * address of the station.
67547  *
67548  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
67549  * format.
67550  *
67551  * Register Layout
67552  *
67553  * Bits | Access | Reset | Description
67554  * :-------|:-------|:-----------|:---------------------
67555  * [31:0] | RW | 0xffffffff | MAC Address75 [31:0]
67556  *
67557  */
67558 /*
67559  * Field : MAC Address75 [31:0] - addrlo
67560  *
67561  * This field contains the lower 32 bits of the 76th 6-byte MAC address. The
67562  * content of this field is undefined until loaded by software after the
67563  * initialization process.
67564  *
67565  * Field Access Macros:
67566  *
67567  */
67568 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
67569 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_LSB 0
67570 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
67571 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_MSB 31
67572 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
67573 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_WIDTH 32
67574 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
67575 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET_MSK 0xffffffff
67576 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
67577 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_CLR_MSK 0x00000000
67578 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
67579 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_RESET 0xffffffff
67580 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO field value from a register. */
67581 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
67582 /* Produces a ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value suitable for setting the register. */
67583 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
67584 
67585 #ifndef __ASSEMBLY__
67586 /*
67587  * WARNING: The C register and register group struct declarations are provided for
67588  * convenience and illustrative purposes. They should, however, be used with
67589  * caution as the C language standard provides no guarantees about the alignment or
67590  * atomicity of device memory accesses. The recommended practice for writing
67591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
67592  * alt_write_word() functions.
67593  *
67594  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW.
67595  */
67596 struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s
67597 {
67598  uint32_t addrlo : 32; /* MAC Address75 [31:0] */
67599 };
67600 
67601 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW. */
67602 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s ALT_EMAC_GMAC_MAC_ADDR75_LOW_t;
67603 #endif /* __ASSEMBLY__ */
67604 
67605 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register from the beginning of the component. */
67606 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST 0x9dc
67607 /* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register. */
67608 #define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST))
67609 
67610 /*
67611  * Register : Register 632 (MAC Address76 High Register) - MAC_Address76_High
67612  *
67613  * The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC
67614  * address of the station. Because the MAC address registers are configured to be
67615  * double-synchronized to the (G)MII clock domains, the synchronization is
67616  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
67617  * endian mode) of the MAC Address76 Low Register are written. For proper
67618  * synchronization updates, the consecutive writes to this Address Low Register
67619  * should be performed after at least four clock cycles in the destination clock
67620  * domain.
67621  *
67622  * Note that all MAC Address High registers (except MAC Address0 High) have the
67623  * same format.
67624  *
67625  * Register Layout
67626  *
67627  * Bits | Access | Reset | Description
67628  * :--------|:-------|:-------|:----------------------
67629  * [15:0] | RW | 0xffff | MAC Address76 [47:32]
67630  * [23:16] | ??? | 0x0 | *UNDEFINED*
67631  * [24] | RW | 0x0 | Mask Byte Control
67632  * [25] | RW | 0x0 | Mask Byte Control
67633  * [26] | RW | 0x0 | Mask Byte Control
67634  * [27] | RW | 0x0 | Mask Byte Control
67635  * [28] | RW | 0x0 | Mask Byte Control
67636  * [29] | RW | 0x0 | Mask Byte Control
67637  * [30] | RW | 0x0 | Source Address
67638  * [31] | RW | 0x0 | Address Enable
67639  *
67640  */
67641 /*
67642  * Field : MAC Address76 [47:32] - addrhi
67643  *
67644  * This field contains the upper 16 bits (47:32) of the 77th 6-byte MAC address.
67645  *
67646  * Field Access Macros:
67647  *
67648  */
67649 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
67650 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_LSB 0
67651 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
67652 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_MSB 15
67653 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
67654 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_WIDTH 16
67655 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
67656 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET_MSK 0x0000ffff
67657 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
67658 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_CLR_MSK 0xffff0000
67659 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
67660 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_RESET 0xffff
67661 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI field value from a register. */
67662 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
67663 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value suitable for setting the register. */
67664 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
67665 
67666 /*
67667  * Field : Mask Byte Control - mbc_0
67668  *
67669  * This array of bits are mask control bits for comparison of each of the MAC
67670  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67671  * received DA or SA with the contents of MAC Address76 high and low registers.
67672  * Each bit controls the masking of the bytes. You can filter a group of addresses
67673  * (known as group address filtering) by masking one or more bytes of the address.
67674  *
67675  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67676  *
67677  * Field Enumeration Values:
67678  *
67679  * Enum | Value | Description
67680  * :----------------------------------------------|:------|:------------------------------------
67681  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67682  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67683  *
67684  * Field Access Macros:
67685  *
67686  */
67687 /*
67688  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0
67689  *
67690  * Byte is unmasked (i.e. is compared)
67691  */
67692 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED 0x0
67693 /*
67694  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0
67695  *
67696  * Byte is masked (i.e. not compared)
67697  */
67698 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED 0x1
67699 
67700 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
67701 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_LSB 24
67702 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
67703 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_MSB 24
67704 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
67705 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_WIDTH 1
67706 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */
67707 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET_MSK 0x01000000
67708 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */
67709 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_CLR_MSK 0xfeffffff
67710 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
67711 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_RESET 0x0
67712 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 field value from a register. */
67713 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
67714 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value suitable for setting the register. */
67715 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
67716 
67717 /*
67718  * Field : Mask Byte Control - mbc_1
67719  *
67720  * This array of bits are mask control bits for comparison of each of the MAC
67721  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67722  * received DA or SA with the contents of MAC Address76 high and low registers.
67723  * Each bit controls the masking of the bytes. You can filter a group of addresses
67724  * (known as group address filtering) by masking one or more bytes of the address.
67725  *
67726  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67727  *
67728  * Field Enumeration Values:
67729  *
67730  * Enum | Value | Description
67731  * :----------------------------------------------|:------|:------------------------------------
67732  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67733  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67734  *
67735  * Field Access Macros:
67736  *
67737  */
67738 /*
67739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1
67740  *
67741  * Byte is unmasked (i.e. is compared)
67742  */
67743 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED 0x0
67744 /*
67745  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1
67746  *
67747  * Byte is masked (i.e. not compared)
67748  */
67749 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED 0x1
67750 
67751 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
67752 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_LSB 25
67753 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
67754 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_MSB 25
67755 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
67756 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_WIDTH 1
67757 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */
67758 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET_MSK 0x02000000
67759 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */
67760 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_CLR_MSK 0xfdffffff
67761 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
67762 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_RESET 0x0
67763 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 field value from a register. */
67764 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
67765 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value suitable for setting the register. */
67766 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
67767 
67768 /*
67769  * Field : Mask Byte Control - mbc_2
67770  *
67771  * This array of bits are mask control bits for comparison of each of the MAC
67772  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67773  * received DA or SA with the contents of MAC Address76 high and low registers.
67774  * Each bit controls the masking of the bytes. You can filter a group of addresses
67775  * (known as group address filtering) by masking one or more bytes of the address.
67776  *
67777  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67778  *
67779  * Field Enumeration Values:
67780  *
67781  * Enum | Value | Description
67782  * :----------------------------------------------|:------|:------------------------------------
67783  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67784  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67785  *
67786  * Field Access Macros:
67787  *
67788  */
67789 /*
67790  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2
67791  *
67792  * Byte is unmasked (i.e. is compared)
67793  */
67794 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED 0x0
67795 /*
67796  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2
67797  *
67798  * Byte is masked (i.e. not compared)
67799  */
67800 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED 0x1
67801 
67802 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
67803 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_LSB 26
67804 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
67805 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_MSB 26
67806 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
67807 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_WIDTH 1
67808 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */
67809 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET_MSK 0x04000000
67810 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */
67811 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_CLR_MSK 0xfbffffff
67812 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
67813 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_RESET 0x0
67814 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 field value from a register. */
67815 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
67816 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value suitable for setting the register. */
67817 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
67818 
67819 /*
67820  * Field : Mask Byte Control - mbc_3
67821  *
67822  * This array of bits are mask control bits for comparison of each of the MAC
67823  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67824  * received DA or SA with the contents of MAC Address76 high and low registers.
67825  * Each bit controls the masking of the bytes. You can filter a group of addresses
67826  * (known as group address filtering) by masking one or more bytes of the address.
67827  *
67828  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67829  *
67830  * Field Enumeration Values:
67831  *
67832  * Enum | Value | Description
67833  * :----------------------------------------------|:------|:------------------------------------
67834  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67835  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67836  *
67837  * Field Access Macros:
67838  *
67839  */
67840 /*
67841  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3
67842  *
67843  * Byte is unmasked (i.e. is compared)
67844  */
67845 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED 0x0
67846 /*
67847  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3
67848  *
67849  * Byte is masked (i.e. not compared)
67850  */
67851 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED 0x1
67852 
67853 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
67854 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_LSB 27
67855 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
67856 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_MSB 27
67857 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
67858 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_WIDTH 1
67859 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */
67860 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET_MSK 0x08000000
67861 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */
67862 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_CLR_MSK 0xf7ffffff
67863 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
67864 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_RESET 0x0
67865 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 field value from a register. */
67866 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
67867 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value suitable for setting the register. */
67868 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
67869 
67870 /*
67871  * Field : Mask Byte Control - mbc_4
67872  *
67873  * This array of bits are mask control bits for comparison of each of the MAC
67874  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67875  * received DA or SA with the contents of MAC Address76 high and low registers.
67876  * Each bit controls the masking of the bytes. You can filter a group of addresses
67877  * (known as group address filtering) by masking one or more bytes of the address.
67878  *
67879  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67880  *
67881  * Field Enumeration Values:
67882  *
67883  * Enum | Value | Description
67884  * :----------------------------------------------|:------|:------------------------------------
67885  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67886  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67887  *
67888  * Field Access Macros:
67889  *
67890  */
67891 /*
67892  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4
67893  *
67894  * Byte is unmasked (i.e. is compared)
67895  */
67896 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED 0x0
67897 /*
67898  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4
67899  *
67900  * Byte is masked (i.e. not compared)
67901  */
67902 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED 0x1
67903 
67904 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
67905 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_LSB 28
67906 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
67907 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_MSB 28
67908 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
67909 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_WIDTH 1
67910 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */
67911 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET_MSK 0x10000000
67912 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */
67913 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_CLR_MSK 0xefffffff
67914 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
67915 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_RESET 0x0
67916 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 field value from a register. */
67917 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
67918 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value suitable for setting the register. */
67919 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
67920 
67921 /*
67922  * Field : Mask Byte Control - mbc_5
67923  *
67924  * This array of bits are mask control bits for comparison of each of the MAC
67925  * Address bytes. When masked, the MAC does not compare the corresponding byte of
67926  * received DA or SA with the contents of MAC Address76 high and low registers.
67927  * Each bit controls the masking of the bytes. You can filter a group of addresses
67928  * (known as group address filtering) by masking one or more bytes of the address.
67929  *
67930  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
67931  *
67932  * Field Enumeration Values:
67933  *
67934  * Enum | Value | Description
67935  * :----------------------------------------------|:------|:------------------------------------
67936  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
67937  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
67938  *
67939  * Field Access Macros:
67940  *
67941  */
67942 /*
67943  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5
67944  *
67945  * Byte is unmasked (i.e. is compared)
67946  */
67947 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED 0x0
67948 /*
67949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5
67950  *
67951  * Byte is masked (i.e. not compared)
67952  */
67953 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED 0x1
67954 
67955 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
67956 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_LSB 29
67957 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
67958 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_MSB 29
67959 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
67960 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_WIDTH 1
67961 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */
67962 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET_MSK 0x20000000
67963 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */
67964 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_CLR_MSK 0xdfffffff
67965 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
67966 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_RESET 0x0
67967 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 field value from a register. */
67968 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
67969 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value suitable for setting the register. */
67970 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
67971 
67972 /*
67973  * Field : Source Address - sa
67974  *
67975  * When this bit is enabled, the MAC Address76[47:0] is used to compare with the SA
67976  * fields of the received frame. When this bit is disabled, the MAC Address76[47:0]
67977  * is used to compare with the DA fields of the received frame.
67978  *
67979  * Field Enumeration Values:
67980  *
67981  * Enum | Value | Description
67982  * :----------------------------------------|:------|:-----------------------------
67983  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
67984  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END | 0x1 | MAC address compare enabled
67985  *
67986  * Field Access Macros:
67987  *
67988  */
67989 /*
67990  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA
67991  *
67992  * MAC address compare disabled
67993  */
67994 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD 0x0
67995 /*
67996  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA
67997  *
67998  * MAC address compare enabled
67999  */
68000 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END 0x1
68001 
68002 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
68003 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_LSB 30
68004 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
68005 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_MSB 30
68006 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
68007 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_WIDTH 1
68008 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */
68009 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET_MSK 0x40000000
68010 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */
68011 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_CLR_MSK 0xbfffffff
68012 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
68013 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_RESET 0x0
68014 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA field value from a register. */
68015 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
68016 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value suitable for setting the register. */
68017 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
68018 
68019 /*
68020  * Field : Address Enable - ae
68021  *
68022  * When this bit is enabled, the address filter block uses the 77th MAC address for
68023  * perfect filtering. When this bit is disabled, the address filter block ignores
68024  * the address for filtering.
68025  *
68026  * Field Enumeration Values:
68027  *
68028  * Enum | Value | Description
68029  * :----------------------------------------|:------|:--------------------------------------
68030  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
68031  * ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
68032  *
68033  * Field Access Macros:
68034  *
68035  */
68036 /*
68037  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
68038  *
68039  * Second MAC address filtering disabled
68040  */
68041 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD 0x0
68042 /*
68043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
68044  *
68045  * Second MAC address filtering enabled
68046  */
68047 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END 0x1
68048 
68049 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
68050 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_LSB 31
68051 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
68052 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_MSB 31
68053 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
68054 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_WIDTH 1
68055 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
68056 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET_MSK 0x80000000
68057 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
68058 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_CLR_MSK 0x7fffffff
68059 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
68060 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_RESET 0x0
68061 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE field value from a register. */
68062 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
68063 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value suitable for setting the register. */
68064 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
68065 
68066 #ifndef __ASSEMBLY__
68067 /*
68068  * WARNING: The C register and register group struct declarations are provided for
68069  * convenience and illustrative purposes. They should, however, be used with
68070  * caution as the C language standard provides no guarantees about the alignment or
68071  * atomicity of device memory accesses. The recommended practice for writing
68072  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68073  * alt_write_word() functions.
68074  *
68075  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH.
68076  */
68077 struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s
68078 {
68079  uint32_t addrhi : 16; /* MAC Address76 [47:32] */
68080  uint32_t : 8; /* *UNDEFINED* */
68081  uint32_t mbc_0 : 1; /* Mask Byte Control */
68082  uint32_t mbc_1 : 1; /* Mask Byte Control */
68083  uint32_t mbc_2 : 1; /* Mask Byte Control */
68084  uint32_t mbc_3 : 1; /* Mask Byte Control */
68085  uint32_t mbc_4 : 1; /* Mask Byte Control */
68086  uint32_t mbc_5 : 1; /* Mask Byte Control */
68087  uint32_t sa : 1; /* Source Address */
68088  uint32_t ae : 1; /* Address Enable */
68089 };
68090 
68091 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH. */
68092 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t;
68093 #endif /* __ASSEMBLY__ */
68094 
68095 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register from the beginning of the component. */
68096 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST 0x9e0
68097 /* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register. */
68098 #define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST))
68099 
68100 /*
68101  * Register : Register 633 (MAC Address76 Low Register) - MAC_Address76_Low
68102  *
68103  * The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC
68104  * address of the station.
68105  *
68106  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
68107  * format.
68108  *
68109  * Register Layout
68110  *
68111  * Bits | Access | Reset | Description
68112  * :-------|:-------|:-----------|:---------------------
68113  * [31:0] | RW | 0xffffffff | MAC Address76 [31:0]
68114  *
68115  */
68116 /*
68117  * Field : MAC Address76 [31:0] - addrlo
68118  *
68119  * This field contains the lower 32 bits of the 77th 6-byte MAC address. The
68120  * content of this field is undefined until loaded by software after the
68121  * initialization process.
68122  *
68123  * Field Access Macros:
68124  *
68125  */
68126 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
68127 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_LSB 0
68128 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
68129 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_MSB 31
68130 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
68131 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_WIDTH 32
68132 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
68133 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET_MSK 0xffffffff
68134 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
68135 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_CLR_MSK 0x00000000
68136 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
68137 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_RESET 0xffffffff
68138 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO field value from a register. */
68139 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
68140 /* Produces a ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value suitable for setting the register. */
68141 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
68142 
68143 #ifndef __ASSEMBLY__
68144 /*
68145  * WARNING: The C register and register group struct declarations are provided for
68146  * convenience and illustrative purposes. They should, however, be used with
68147  * caution as the C language standard provides no guarantees about the alignment or
68148  * atomicity of device memory accesses. The recommended practice for writing
68149  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68150  * alt_write_word() functions.
68151  *
68152  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW.
68153  */
68154 struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s
68155 {
68156  uint32_t addrlo : 32; /* MAC Address76 [31:0] */
68157 };
68158 
68159 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW. */
68160 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s ALT_EMAC_GMAC_MAC_ADDR76_LOW_t;
68161 #endif /* __ASSEMBLY__ */
68162 
68163 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register from the beginning of the component. */
68164 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST 0x9e4
68165 /* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register. */
68166 #define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST))
68167 
68168 /*
68169  * Register : Register 634 (MAC Address77 High Register) - MAC_Address77_High
68170  *
68171  * The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC
68172  * address of the station. Because the MAC address registers are configured to be
68173  * double-synchronized to the (G)MII clock domains, the synchronization is
68174  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
68175  * endian mode) of the MAC Address77 Low Register are written. For proper
68176  * synchronization updates, the consecutive writes to this Address Low Register
68177  * should be performed after at least four clock cycles in the destination clock
68178  * domain.
68179  *
68180  * Note that all MAC Address High registers (except MAC Address0 High) have the
68181  * same format.
68182  *
68183  * Register Layout
68184  *
68185  * Bits | Access | Reset | Description
68186  * :--------|:-------|:-------|:----------------------
68187  * [15:0] | RW | 0xffff | MAC Address77 [47:32]
68188  * [23:16] | ??? | 0x0 | *UNDEFINED*
68189  * [24] | RW | 0x0 | Mask Byte Control
68190  * [25] | RW | 0x0 | Mask Byte Control
68191  * [26] | RW | 0x0 | Mask Byte Control
68192  * [27] | RW | 0x0 | Mask Byte Control
68193  * [28] | RW | 0x0 | Mask Byte Control
68194  * [29] | RW | 0x0 | Mask Byte Control
68195  * [30] | RW | 0x0 | Source Address
68196  * [31] | RW | 0x0 | Address Enable
68197  *
68198  */
68199 /*
68200  * Field : MAC Address77 [47:32] - addrhi
68201  *
68202  * This field contains the upper 16 bits (47:32) of the 78th 6-byte MAC address.
68203  *
68204  * Field Access Macros:
68205  *
68206  */
68207 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
68208 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_LSB 0
68209 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
68210 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_MSB 15
68211 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
68212 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_WIDTH 16
68213 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
68214 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET_MSK 0x0000ffff
68215 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
68216 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_CLR_MSK 0xffff0000
68217 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
68218 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_RESET 0xffff
68219 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI field value from a register. */
68220 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
68221 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value suitable for setting the register. */
68222 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
68223 
68224 /*
68225  * Field : Mask Byte Control - mbc_0
68226  *
68227  * This array of bits are mask control bits for comparison of each of the MAC
68228  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68229  * received DA or SA with the contents of MAC Address77 high and low registers.
68230  * Each bit controls the masking of the bytes. You can filter a group of addresses
68231  * (known as group address filtering) by masking one or more bytes of the address.
68232  *
68233  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68234  *
68235  * Field Enumeration Values:
68236  *
68237  * Enum | Value | Description
68238  * :----------------------------------------------|:------|:------------------------------------
68239  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68240  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68241  *
68242  * Field Access Macros:
68243  *
68244  */
68245 /*
68246  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0
68247  *
68248  * Byte is unmasked (i.e. is compared)
68249  */
68250 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED 0x0
68251 /*
68252  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0
68253  *
68254  * Byte is masked (i.e. not compared)
68255  */
68256 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED 0x1
68257 
68258 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
68259 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_LSB 24
68260 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
68261 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_MSB 24
68262 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
68263 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_WIDTH 1
68264 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */
68265 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET_MSK 0x01000000
68266 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */
68267 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_CLR_MSK 0xfeffffff
68268 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
68269 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_RESET 0x0
68270 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 field value from a register. */
68271 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
68272 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value suitable for setting the register. */
68273 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
68274 
68275 /*
68276  * Field : Mask Byte Control - mbc_1
68277  *
68278  * This array of bits are mask control bits for comparison of each of the MAC
68279  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68280  * received DA or SA with the contents of MAC Address77 high and low registers.
68281  * Each bit controls the masking of the bytes. You can filter a group of addresses
68282  * (known as group address filtering) by masking one or more bytes of the address.
68283  *
68284  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68285  *
68286  * Field Enumeration Values:
68287  *
68288  * Enum | Value | Description
68289  * :----------------------------------------------|:------|:------------------------------------
68290  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68291  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68292  *
68293  * Field Access Macros:
68294  *
68295  */
68296 /*
68297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1
68298  *
68299  * Byte is unmasked (i.e. is compared)
68300  */
68301 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED 0x0
68302 /*
68303  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1
68304  *
68305  * Byte is masked (i.e. not compared)
68306  */
68307 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED 0x1
68308 
68309 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
68310 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_LSB 25
68311 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
68312 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_MSB 25
68313 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
68314 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_WIDTH 1
68315 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */
68316 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET_MSK 0x02000000
68317 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */
68318 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_CLR_MSK 0xfdffffff
68319 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
68320 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_RESET 0x0
68321 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 field value from a register. */
68322 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
68323 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value suitable for setting the register. */
68324 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
68325 
68326 /*
68327  * Field : Mask Byte Control - mbc_2
68328  *
68329  * This array of bits are mask control bits for comparison of each of the MAC
68330  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68331  * received DA or SA with the contents of MAC Address77 high and low registers.
68332  * Each bit controls the masking of the bytes. You can filter a group of addresses
68333  * (known as group address filtering) by masking one or more bytes of the address.
68334  *
68335  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68336  *
68337  * Field Enumeration Values:
68338  *
68339  * Enum | Value | Description
68340  * :----------------------------------------------|:------|:------------------------------------
68341  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68342  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68343  *
68344  * Field Access Macros:
68345  *
68346  */
68347 /*
68348  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2
68349  *
68350  * Byte is unmasked (i.e. is compared)
68351  */
68352 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED 0x0
68353 /*
68354  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2
68355  *
68356  * Byte is masked (i.e. not compared)
68357  */
68358 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED 0x1
68359 
68360 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
68361 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_LSB 26
68362 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
68363 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_MSB 26
68364 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
68365 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_WIDTH 1
68366 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */
68367 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET_MSK 0x04000000
68368 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */
68369 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_CLR_MSK 0xfbffffff
68370 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
68371 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_RESET 0x0
68372 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 field value from a register. */
68373 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
68374 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value suitable for setting the register. */
68375 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
68376 
68377 /*
68378  * Field : Mask Byte Control - mbc_3
68379  *
68380  * This array of bits are mask control bits for comparison of each of the MAC
68381  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68382  * received DA or SA with the contents of MAC Address77 high and low registers.
68383  * Each bit controls the masking of the bytes. You can filter a group of addresses
68384  * (known as group address filtering) by masking one or more bytes of the address.
68385  *
68386  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68387  *
68388  * Field Enumeration Values:
68389  *
68390  * Enum | Value | Description
68391  * :----------------------------------------------|:------|:------------------------------------
68392  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68393  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68394  *
68395  * Field Access Macros:
68396  *
68397  */
68398 /*
68399  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3
68400  *
68401  * Byte is unmasked (i.e. is compared)
68402  */
68403 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED 0x0
68404 /*
68405  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3
68406  *
68407  * Byte is masked (i.e. not compared)
68408  */
68409 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED 0x1
68410 
68411 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
68412 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_LSB 27
68413 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
68414 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_MSB 27
68415 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
68416 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_WIDTH 1
68417 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */
68418 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET_MSK 0x08000000
68419 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */
68420 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_CLR_MSK 0xf7ffffff
68421 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
68422 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_RESET 0x0
68423 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 field value from a register. */
68424 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
68425 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value suitable for setting the register. */
68426 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
68427 
68428 /*
68429  * Field : Mask Byte Control - mbc_4
68430  *
68431  * This array of bits are mask control bits for comparison of each of the MAC
68432  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68433  * received DA or SA with the contents of MAC Address77 high and low registers.
68434  * Each bit controls the masking of the bytes. You can filter a group of addresses
68435  * (known as group address filtering) by masking one or more bytes of the address.
68436  *
68437  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68438  *
68439  * Field Enumeration Values:
68440  *
68441  * Enum | Value | Description
68442  * :----------------------------------------------|:------|:------------------------------------
68443  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68444  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68445  *
68446  * Field Access Macros:
68447  *
68448  */
68449 /*
68450  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4
68451  *
68452  * Byte is unmasked (i.e. is compared)
68453  */
68454 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED 0x0
68455 /*
68456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4
68457  *
68458  * Byte is masked (i.e. not compared)
68459  */
68460 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED 0x1
68461 
68462 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
68463 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_LSB 28
68464 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
68465 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_MSB 28
68466 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
68467 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_WIDTH 1
68468 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */
68469 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET_MSK 0x10000000
68470 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */
68471 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_CLR_MSK 0xefffffff
68472 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
68473 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_RESET 0x0
68474 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 field value from a register. */
68475 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
68476 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value suitable for setting the register. */
68477 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
68478 
68479 /*
68480  * Field : Mask Byte Control - mbc_5
68481  *
68482  * This array of bits are mask control bits for comparison of each of the MAC
68483  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68484  * received DA or SA with the contents of MAC Address77 high and low registers.
68485  * Each bit controls the masking of the bytes. You can filter a group of addresses
68486  * (known as group address filtering) by masking one or more bytes of the address.
68487  *
68488  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68489  *
68490  * Field Enumeration Values:
68491  *
68492  * Enum | Value | Description
68493  * :----------------------------------------------|:------|:------------------------------------
68494  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68495  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68496  *
68497  * Field Access Macros:
68498  *
68499  */
68500 /*
68501  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5
68502  *
68503  * Byte is unmasked (i.e. is compared)
68504  */
68505 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED 0x0
68506 /*
68507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5
68508  *
68509  * Byte is masked (i.e. not compared)
68510  */
68511 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED 0x1
68512 
68513 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
68514 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_LSB 29
68515 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
68516 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_MSB 29
68517 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
68518 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_WIDTH 1
68519 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */
68520 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET_MSK 0x20000000
68521 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */
68522 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_CLR_MSK 0xdfffffff
68523 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
68524 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_RESET 0x0
68525 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 field value from a register. */
68526 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
68527 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value suitable for setting the register. */
68528 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
68529 
68530 /*
68531  * Field : Source Address - sa
68532  *
68533  * When this bit is enabled, the MAC Address77[47:0] is used to compare with the SA
68534  * fields of the received frame. When this bit is disabled, the MAC Address77[47:0]
68535  * is used to compare with the DA fields of the received frame.
68536  *
68537  * Field Enumeration Values:
68538  *
68539  * Enum | Value | Description
68540  * :----------------------------------------|:------|:-----------------------------
68541  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
68542  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END | 0x1 | MAC address compare enabled
68543  *
68544  * Field Access Macros:
68545  *
68546  */
68547 /*
68548  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA
68549  *
68550  * MAC address compare disabled
68551  */
68552 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD 0x0
68553 /*
68554  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA
68555  *
68556  * MAC address compare enabled
68557  */
68558 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END 0x1
68559 
68560 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
68561 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_LSB 30
68562 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
68563 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_MSB 30
68564 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
68565 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_WIDTH 1
68566 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */
68567 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET_MSK 0x40000000
68568 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */
68569 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_CLR_MSK 0xbfffffff
68570 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
68571 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_RESET 0x0
68572 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA field value from a register. */
68573 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
68574 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value suitable for setting the register. */
68575 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
68576 
68577 /*
68578  * Field : Address Enable - ae
68579  *
68580  * When this bit is enabled, the address filter block uses the 78th MAC address for
68581  * perfect filtering. When this bit is disabled, the address filter block ignores
68582  * the address for filtering.
68583  *
68584  * Field Enumeration Values:
68585  *
68586  * Enum | Value | Description
68587  * :----------------------------------------|:------|:--------------------------------------
68588  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
68589  * ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
68590  *
68591  * Field Access Macros:
68592  *
68593  */
68594 /*
68595  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
68596  *
68597  * Second MAC address filtering disabled
68598  */
68599 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD 0x0
68600 /*
68601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
68602  *
68603  * Second MAC address filtering enabled
68604  */
68605 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END 0x1
68606 
68607 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
68608 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_LSB 31
68609 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
68610 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_MSB 31
68611 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
68612 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_WIDTH 1
68613 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
68614 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET_MSK 0x80000000
68615 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
68616 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_CLR_MSK 0x7fffffff
68617 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
68618 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_RESET 0x0
68619 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE field value from a register. */
68620 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
68621 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value suitable for setting the register. */
68622 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
68623 
68624 #ifndef __ASSEMBLY__
68625 /*
68626  * WARNING: The C register and register group struct declarations are provided for
68627  * convenience and illustrative purposes. They should, however, be used with
68628  * caution as the C language standard provides no guarantees about the alignment or
68629  * atomicity of device memory accesses. The recommended practice for writing
68630  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68631  * alt_write_word() functions.
68632  *
68633  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH.
68634  */
68635 struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s
68636 {
68637  uint32_t addrhi : 16; /* MAC Address77 [47:32] */
68638  uint32_t : 8; /* *UNDEFINED* */
68639  uint32_t mbc_0 : 1; /* Mask Byte Control */
68640  uint32_t mbc_1 : 1; /* Mask Byte Control */
68641  uint32_t mbc_2 : 1; /* Mask Byte Control */
68642  uint32_t mbc_3 : 1; /* Mask Byte Control */
68643  uint32_t mbc_4 : 1; /* Mask Byte Control */
68644  uint32_t mbc_5 : 1; /* Mask Byte Control */
68645  uint32_t sa : 1; /* Source Address */
68646  uint32_t ae : 1; /* Address Enable */
68647 };
68648 
68649 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH. */
68650 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t;
68651 #endif /* __ASSEMBLY__ */
68652 
68653 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register from the beginning of the component. */
68654 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST 0x9e8
68655 /* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register. */
68656 #define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST))
68657 
68658 /*
68659  * Register : Register 635 (MAC Address77 Low Register) - MAC_Address77_Low
68660  *
68661  * The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC
68662  * address of the station.
68663  *
68664  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
68665  * format.
68666  *
68667  * Register Layout
68668  *
68669  * Bits | Access | Reset | Description
68670  * :-------|:-------|:-----------|:---------------------
68671  * [31:0] | RW | 0xffffffff | MAC Address77 [31:0]
68672  *
68673  */
68674 /*
68675  * Field : MAC Address77 [31:0] - addrlo
68676  *
68677  * This field contains the lower 32 bits of the 78th 6-byte MAC address. The
68678  * content of this field is undefined until loaded by software after the
68679  * initialization process.
68680  *
68681  * Field Access Macros:
68682  *
68683  */
68684 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
68685 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_LSB 0
68686 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
68687 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_MSB 31
68688 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
68689 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_WIDTH 32
68690 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
68691 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET_MSK 0xffffffff
68692 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
68693 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_CLR_MSK 0x00000000
68694 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
68695 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_RESET 0xffffffff
68696 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO field value from a register. */
68697 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
68698 /* Produces a ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value suitable for setting the register. */
68699 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
68700 
68701 #ifndef __ASSEMBLY__
68702 /*
68703  * WARNING: The C register and register group struct declarations are provided for
68704  * convenience and illustrative purposes. They should, however, be used with
68705  * caution as the C language standard provides no guarantees about the alignment or
68706  * atomicity of device memory accesses. The recommended practice for writing
68707  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
68708  * alt_write_word() functions.
68709  *
68710  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW.
68711  */
68712 struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s
68713 {
68714  uint32_t addrlo : 32; /* MAC Address77 [31:0] */
68715 };
68716 
68717 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW. */
68718 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s ALT_EMAC_GMAC_MAC_ADDR77_LOW_t;
68719 #endif /* __ASSEMBLY__ */
68720 
68721 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register from the beginning of the component. */
68722 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST 0x9ec
68723 /* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register. */
68724 #define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST))
68725 
68726 /*
68727  * Register : Register 636 (MAC Address78 High Register) - MAC_Address78_High
68728  *
68729  * The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC
68730  * address of the station. Because the MAC address registers are configured to be
68731  * double-synchronized to the (G)MII clock domains, the synchronization is
68732  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
68733  * endian mode) of the MAC Address78 Low Register are written. For proper
68734  * synchronization updates, the consecutive writes to this Address Low Register
68735  * should be performed after at least four clock cycles in the destination clock
68736  * domain.
68737  *
68738  * Note that all MAC Address High registers (except MAC Address0 High) have the
68739  * same format.
68740  *
68741  * Register Layout
68742  *
68743  * Bits | Access | Reset | Description
68744  * :--------|:-------|:-------|:----------------------
68745  * [15:0] | RW | 0xffff | MAC Address78 [47:32]
68746  * [23:16] | ??? | 0x0 | *UNDEFINED*
68747  * [24] | RW | 0x0 | Mask Byte Control
68748  * [25] | RW | 0x0 | Mask Byte Control
68749  * [26] | RW | 0x0 | Mask Byte Control
68750  * [27] | RW | 0x0 | Mask Byte Control
68751  * [28] | RW | 0x0 | Mask Byte Control
68752  * [29] | RW | 0x0 | Mask Byte Control
68753  * [30] | RW | 0x0 | Source Address
68754  * [31] | RW | 0x0 | Address Enable
68755  *
68756  */
68757 /*
68758  * Field : MAC Address78 [47:32] - addrhi
68759  *
68760  * This field contains the upper 16 bits (47:32) of the 79th 6-byte MAC address.
68761  *
68762  * Field Access Macros:
68763  *
68764  */
68765 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
68766 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_LSB 0
68767 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
68768 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_MSB 15
68769 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
68770 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_WIDTH 16
68771 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
68772 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET_MSK 0x0000ffff
68773 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
68774 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_CLR_MSK 0xffff0000
68775 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
68776 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_RESET 0xffff
68777 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI field value from a register. */
68778 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
68779 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value suitable for setting the register. */
68780 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
68781 
68782 /*
68783  * Field : Mask Byte Control - mbc_0
68784  *
68785  * This array of bits are mask control bits for comparison of each of the MAC
68786  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68787  * received DA or SA with the contents of MAC Address78 high and low registers.
68788  * Each bit controls the masking of the bytes. You can filter a group of addresses
68789  * (known as group address filtering) by masking one or more bytes of the address.
68790  *
68791  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68792  *
68793  * Field Enumeration Values:
68794  *
68795  * Enum | Value | Description
68796  * :----------------------------------------------|:------|:------------------------------------
68797  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68798  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68799  *
68800  * Field Access Macros:
68801  *
68802  */
68803 /*
68804  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0
68805  *
68806  * Byte is unmasked (i.e. is compared)
68807  */
68808 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED 0x0
68809 /*
68810  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0
68811  *
68812  * Byte is masked (i.e. not compared)
68813  */
68814 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED 0x1
68815 
68816 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
68817 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_LSB 24
68818 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
68819 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_MSB 24
68820 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
68821 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_WIDTH 1
68822 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */
68823 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET_MSK 0x01000000
68824 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */
68825 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_CLR_MSK 0xfeffffff
68826 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
68827 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_RESET 0x0
68828 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 field value from a register. */
68829 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
68830 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value suitable for setting the register. */
68831 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
68832 
68833 /*
68834  * Field : Mask Byte Control - mbc_1
68835  *
68836  * This array of bits are mask control bits for comparison of each of the MAC
68837  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68838  * received DA or SA with the contents of MAC Address78 high and low registers.
68839  * Each bit controls the masking of the bytes. You can filter a group of addresses
68840  * (known as group address filtering) by masking one or more bytes of the address.
68841  *
68842  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68843  *
68844  * Field Enumeration Values:
68845  *
68846  * Enum | Value | Description
68847  * :----------------------------------------------|:------|:------------------------------------
68848  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68849  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68850  *
68851  * Field Access Macros:
68852  *
68853  */
68854 /*
68855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1
68856  *
68857  * Byte is unmasked (i.e. is compared)
68858  */
68859 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED 0x0
68860 /*
68861  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1
68862  *
68863  * Byte is masked (i.e. not compared)
68864  */
68865 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED 0x1
68866 
68867 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
68868 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_LSB 25
68869 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
68870 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_MSB 25
68871 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
68872 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_WIDTH 1
68873 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */
68874 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET_MSK 0x02000000
68875 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */
68876 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_CLR_MSK 0xfdffffff
68877 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
68878 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_RESET 0x0
68879 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 field value from a register. */
68880 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
68881 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value suitable for setting the register. */
68882 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
68883 
68884 /*
68885  * Field : Mask Byte Control - mbc_2
68886  *
68887  * This array of bits are mask control bits for comparison of each of the MAC
68888  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68889  * received DA or SA with the contents of MAC Address78 high and low registers.
68890  * Each bit controls the masking of the bytes. You can filter a group of addresses
68891  * (known as group address filtering) by masking one or more bytes of the address.
68892  *
68893  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68894  *
68895  * Field Enumeration Values:
68896  *
68897  * Enum | Value | Description
68898  * :----------------------------------------------|:------|:------------------------------------
68899  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68900  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68901  *
68902  * Field Access Macros:
68903  *
68904  */
68905 /*
68906  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2
68907  *
68908  * Byte is unmasked (i.e. is compared)
68909  */
68910 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED 0x0
68911 /*
68912  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2
68913  *
68914  * Byte is masked (i.e. not compared)
68915  */
68916 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED 0x1
68917 
68918 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
68919 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_LSB 26
68920 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
68921 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_MSB 26
68922 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
68923 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_WIDTH 1
68924 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */
68925 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET_MSK 0x04000000
68926 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */
68927 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_CLR_MSK 0xfbffffff
68928 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
68929 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_RESET 0x0
68930 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 field value from a register. */
68931 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
68932 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value suitable for setting the register. */
68933 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
68934 
68935 /*
68936  * Field : Mask Byte Control - mbc_3
68937  *
68938  * This array of bits are mask control bits for comparison of each of the MAC
68939  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68940  * received DA or SA with the contents of MAC Address78 high and low registers.
68941  * Each bit controls the masking of the bytes. You can filter a group of addresses
68942  * (known as group address filtering) by masking one or more bytes of the address.
68943  *
68944  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68945  *
68946  * Field Enumeration Values:
68947  *
68948  * Enum | Value | Description
68949  * :----------------------------------------------|:------|:------------------------------------
68950  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
68951  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
68952  *
68953  * Field Access Macros:
68954  *
68955  */
68956 /*
68957  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3
68958  *
68959  * Byte is unmasked (i.e. is compared)
68960  */
68961 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED 0x0
68962 /*
68963  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3
68964  *
68965  * Byte is masked (i.e. not compared)
68966  */
68967 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED 0x1
68968 
68969 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
68970 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_LSB 27
68971 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
68972 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_MSB 27
68973 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
68974 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_WIDTH 1
68975 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */
68976 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET_MSK 0x08000000
68977 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */
68978 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_CLR_MSK 0xf7ffffff
68979 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
68980 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_RESET 0x0
68981 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 field value from a register. */
68982 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
68983 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value suitable for setting the register. */
68984 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
68985 
68986 /*
68987  * Field : Mask Byte Control - mbc_4
68988  *
68989  * This array of bits are mask control bits for comparison of each of the MAC
68990  * Address bytes. When masked, the MAC does not compare the corresponding byte of
68991  * received DA or SA with the contents of MAC Address78 high and low registers.
68992  * Each bit controls the masking of the bytes. You can filter a group of addresses
68993  * (known as group address filtering) by masking one or more bytes of the address.
68994  *
68995  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
68996  *
68997  * Field Enumeration Values:
68998  *
68999  * Enum | Value | Description
69000  * :----------------------------------------------|:------|:------------------------------------
69001  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69002  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69003  *
69004  * Field Access Macros:
69005  *
69006  */
69007 /*
69008  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4
69009  *
69010  * Byte is unmasked (i.e. is compared)
69011  */
69012 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED 0x0
69013 /*
69014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4
69015  *
69016  * Byte is masked (i.e. not compared)
69017  */
69018 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED 0x1
69019 
69020 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
69021 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_LSB 28
69022 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
69023 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_MSB 28
69024 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
69025 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_WIDTH 1
69026 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */
69027 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET_MSK 0x10000000
69028 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */
69029 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_CLR_MSK 0xefffffff
69030 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
69031 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_RESET 0x0
69032 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 field value from a register. */
69033 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
69034 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value suitable for setting the register. */
69035 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
69036 
69037 /*
69038  * Field : Mask Byte Control - mbc_5
69039  *
69040  * This array of bits are mask control bits for comparison of each of the MAC
69041  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69042  * received DA or SA with the contents of MAC Address78 high and low registers.
69043  * Each bit controls the masking of the bytes. You can filter a group of addresses
69044  * (known as group address filtering) by masking one or more bytes of the address.
69045  *
69046  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69047  *
69048  * Field Enumeration Values:
69049  *
69050  * Enum | Value | Description
69051  * :----------------------------------------------|:------|:------------------------------------
69052  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69053  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69054  *
69055  * Field Access Macros:
69056  *
69057  */
69058 /*
69059  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5
69060  *
69061  * Byte is unmasked (i.e. is compared)
69062  */
69063 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED 0x0
69064 /*
69065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5
69066  *
69067  * Byte is masked (i.e. not compared)
69068  */
69069 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED 0x1
69070 
69071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
69072 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_LSB 29
69073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
69074 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_MSB 29
69075 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
69076 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_WIDTH 1
69077 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */
69078 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET_MSK 0x20000000
69079 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */
69080 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_CLR_MSK 0xdfffffff
69081 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
69082 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_RESET 0x0
69083 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 field value from a register. */
69084 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
69085 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value suitable for setting the register. */
69086 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
69087 
69088 /*
69089  * Field : Source Address - sa
69090  *
69091  * When this bit is enabled, the MAC Address78[47:0] is used to compare with the SA
69092  * fields of the received frame. When this bit is disabled, the MAC Address78[47:0]
69093  * is used to compare with the DA fields of the received frame.
69094  *
69095  * Field Enumeration Values:
69096  *
69097  * Enum | Value | Description
69098  * :----------------------------------------|:------|:-----------------------------
69099  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
69100  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END | 0x1 | MAC address compare enabled
69101  *
69102  * Field Access Macros:
69103  *
69104  */
69105 /*
69106  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA
69107  *
69108  * MAC address compare disabled
69109  */
69110 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD 0x0
69111 /*
69112  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA
69113  *
69114  * MAC address compare enabled
69115  */
69116 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END 0x1
69117 
69118 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
69119 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_LSB 30
69120 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
69121 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_MSB 30
69122 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
69123 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_WIDTH 1
69124 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */
69125 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET_MSK 0x40000000
69126 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */
69127 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_CLR_MSK 0xbfffffff
69128 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
69129 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_RESET 0x0
69130 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA field value from a register. */
69131 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
69132 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value suitable for setting the register. */
69133 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
69134 
69135 /*
69136  * Field : Address Enable - ae
69137  *
69138  * When this bit is enabled, the address filter block uses the 79th MAC address for
69139  * perfect filtering. When this bit is disabled, the address filter block ignores
69140  * the address for filtering.
69141  *
69142  * Field Enumeration Values:
69143  *
69144  * Enum | Value | Description
69145  * :----------------------------------------|:------|:--------------------------------------
69146  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
69147  * ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
69148  *
69149  * Field Access Macros:
69150  *
69151  */
69152 /*
69153  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
69154  *
69155  * Second MAC address filtering disabled
69156  */
69157 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD 0x0
69158 /*
69159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
69160  *
69161  * Second MAC address filtering enabled
69162  */
69163 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END 0x1
69164 
69165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
69166 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_LSB 31
69167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
69168 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_MSB 31
69169 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
69170 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_WIDTH 1
69171 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
69172 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET_MSK 0x80000000
69173 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
69174 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_CLR_MSK 0x7fffffff
69175 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
69176 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_RESET 0x0
69177 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE field value from a register. */
69178 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
69179 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value suitable for setting the register. */
69180 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
69181 
69182 #ifndef __ASSEMBLY__
69183 /*
69184  * WARNING: The C register and register group struct declarations are provided for
69185  * convenience and illustrative purposes. They should, however, be used with
69186  * caution as the C language standard provides no guarantees about the alignment or
69187  * atomicity of device memory accesses. The recommended practice for writing
69188  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69189  * alt_write_word() functions.
69190  *
69191  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH.
69192  */
69193 struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s
69194 {
69195  uint32_t addrhi : 16; /* MAC Address78 [47:32] */
69196  uint32_t : 8; /* *UNDEFINED* */
69197  uint32_t mbc_0 : 1; /* Mask Byte Control */
69198  uint32_t mbc_1 : 1; /* Mask Byte Control */
69199  uint32_t mbc_2 : 1; /* Mask Byte Control */
69200  uint32_t mbc_3 : 1; /* Mask Byte Control */
69201  uint32_t mbc_4 : 1; /* Mask Byte Control */
69202  uint32_t mbc_5 : 1; /* Mask Byte Control */
69203  uint32_t sa : 1; /* Source Address */
69204  uint32_t ae : 1; /* Address Enable */
69205 };
69206 
69207 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH. */
69208 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t;
69209 #endif /* __ASSEMBLY__ */
69210 
69211 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register from the beginning of the component. */
69212 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST 0x9f0
69213 /* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register. */
69214 #define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST))
69215 
69216 /*
69217  * Register : Register 637 (MAC Address78 Low Register) - MAC_Address78_Low
69218  *
69219  * The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC
69220  * address of the station.
69221  *
69222  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
69223  * format.
69224  *
69225  * Register Layout
69226  *
69227  * Bits | Access | Reset | Description
69228  * :-------|:-------|:-----------|:---------------------
69229  * [31:0] | RW | 0xffffffff | MAC Address78 [31:0]
69230  *
69231  */
69232 /*
69233  * Field : MAC Address78 [31:0] - addrlo
69234  *
69235  * This field contains the lower 32 bits of the 79th 6-byte MAC address. The
69236  * content of this field is undefined until loaded by software after the
69237  * initialization process.
69238  *
69239  * Field Access Macros:
69240  *
69241  */
69242 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
69243 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_LSB 0
69244 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
69245 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_MSB 31
69246 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
69247 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_WIDTH 32
69248 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
69249 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET_MSK 0xffffffff
69250 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
69251 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_CLR_MSK 0x00000000
69252 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
69253 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_RESET 0xffffffff
69254 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO field value from a register. */
69255 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
69256 /* Produces a ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value suitable for setting the register. */
69257 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
69258 
69259 #ifndef __ASSEMBLY__
69260 /*
69261  * WARNING: The C register and register group struct declarations are provided for
69262  * convenience and illustrative purposes. They should, however, be used with
69263  * caution as the C language standard provides no guarantees about the alignment or
69264  * atomicity of device memory accesses. The recommended practice for writing
69265  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69266  * alt_write_word() functions.
69267  *
69268  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW.
69269  */
69270 struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s
69271 {
69272  uint32_t addrlo : 32; /* MAC Address78 [31:0] */
69273 };
69274 
69275 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW. */
69276 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s ALT_EMAC_GMAC_MAC_ADDR78_LOW_t;
69277 #endif /* __ASSEMBLY__ */
69278 
69279 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register from the beginning of the component. */
69280 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST 0x9f4
69281 /* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register. */
69282 #define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST))
69283 
69284 /*
69285  * Register : Register 638 (MAC Address79 High Register) - MAC_Address79_High
69286  *
69287  * The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC
69288  * address of the station. Because the MAC address registers are configured to be
69289  * double-synchronized to the (G)MII clock domains, the synchronization is
69290  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
69291  * endian mode) of the MAC Address79 Low Register are written. For proper
69292  * synchronization updates, the consecutive writes to this Address Low Register
69293  * should be performed after at least four clock cycles in the destination clock
69294  * domain.
69295  *
69296  * Note that all MAC Address High registers (except MAC Address0 High) have the
69297  * same format.
69298  *
69299  * Register Layout
69300  *
69301  * Bits | Access | Reset | Description
69302  * :--------|:-------|:-------|:----------------------
69303  * [15:0] | RW | 0xffff | MAC Address79 [47:32]
69304  * [23:16] | ??? | 0x0 | *UNDEFINED*
69305  * [24] | RW | 0x0 | Mask Byte Control
69306  * [25] | RW | 0x0 | Mask Byte Control
69307  * [26] | RW | 0x0 | Mask Byte Control
69308  * [27] | RW | 0x0 | Mask Byte Control
69309  * [28] | RW | 0x0 | Mask Byte Control
69310  * [29] | RW | 0x0 | Mask Byte Control
69311  * [30] | RW | 0x0 | Source Address
69312  * [31] | RW | 0x0 | Address Enable
69313  *
69314  */
69315 /*
69316  * Field : MAC Address79 [47:32] - addrhi
69317  *
69318  * This field contains the upper 16 bits (47:32) of the 80th 6-byte MAC address.
69319  *
69320  * Field Access Macros:
69321  *
69322  */
69323 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
69324 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_LSB 0
69325 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
69326 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_MSB 15
69327 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
69328 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_WIDTH 16
69329 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
69330 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET_MSK 0x0000ffff
69331 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
69332 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_CLR_MSK 0xffff0000
69333 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
69334 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_RESET 0xffff
69335 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI field value from a register. */
69336 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
69337 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value suitable for setting the register. */
69338 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
69339 
69340 /*
69341  * Field : Mask Byte Control - mbc_0
69342  *
69343  * This array of bits are mask control bits for comparison of each of the MAC
69344  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69345  * received DA or SA with the contents of MAC Address79 high and low registers.
69346  * Each bit controls the masking of the bytes. You can filter a group of addresses
69347  * (known as group address filtering) by masking one or more bytes of the address.
69348  *
69349  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69350  *
69351  * Field Enumeration Values:
69352  *
69353  * Enum | Value | Description
69354  * :----------------------------------------------|:------|:------------------------------------
69355  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69356  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69357  *
69358  * Field Access Macros:
69359  *
69360  */
69361 /*
69362  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0
69363  *
69364  * Byte is unmasked (i.e. is compared)
69365  */
69366 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED 0x0
69367 /*
69368  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0
69369  *
69370  * Byte is masked (i.e. not compared)
69371  */
69372 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED 0x1
69373 
69374 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
69375 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_LSB 24
69376 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
69377 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_MSB 24
69378 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
69379 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_WIDTH 1
69380 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */
69381 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET_MSK 0x01000000
69382 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */
69383 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_CLR_MSK 0xfeffffff
69384 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
69385 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_RESET 0x0
69386 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 field value from a register. */
69387 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
69388 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value suitable for setting the register. */
69389 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
69390 
69391 /*
69392  * Field : Mask Byte Control - mbc_1
69393  *
69394  * This array of bits are mask control bits for comparison of each of the MAC
69395  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69396  * received DA or SA with the contents of MAC Address79 high and low registers.
69397  * Each bit controls the masking of the bytes. You can filter a group of addresses
69398  * (known as group address filtering) by masking one or more bytes of the address.
69399  *
69400  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69401  *
69402  * Field Enumeration Values:
69403  *
69404  * Enum | Value | Description
69405  * :----------------------------------------------|:------|:------------------------------------
69406  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69407  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69408  *
69409  * Field Access Macros:
69410  *
69411  */
69412 /*
69413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1
69414  *
69415  * Byte is unmasked (i.e. is compared)
69416  */
69417 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED 0x0
69418 /*
69419  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1
69420  *
69421  * Byte is masked (i.e. not compared)
69422  */
69423 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED 0x1
69424 
69425 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
69426 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_LSB 25
69427 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
69428 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_MSB 25
69429 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
69430 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_WIDTH 1
69431 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */
69432 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET_MSK 0x02000000
69433 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */
69434 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_CLR_MSK 0xfdffffff
69435 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
69436 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_RESET 0x0
69437 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 field value from a register. */
69438 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
69439 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value suitable for setting the register. */
69440 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
69441 
69442 /*
69443  * Field : Mask Byte Control - mbc_2
69444  *
69445  * This array of bits are mask control bits for comparison of each of the MAC
69446  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69447  * received DA or SA with the contents of MAC Address79 high and low registers.
69448  * Each bit controls the masking of the bytes. You can filter a group of addresses
69449  * (known as group address filtering) by masking one or more bytes of the address.
69450  *
69451  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69452  *
69453  * Field Enumeration Values:
69454  *
69455  * Enum | Value | Description
69456  * :----------------------------------------------|:------|:------------------------------------
69457  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69458  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69459  *
69460  * Field Access Macros:
69461  *
69462  */
69463 /*
69464  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2
69465  *
69466  * Byte is unmasked (i.e. is compared)
69467  */
69468 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED 0x0
69469 /*
69470  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2
69471  *
69472  * Byte is masked (i.e. not compared)
69473  */
69474 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED 0x1
69475 
69476 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
69477 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_LSB 26
69478 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
69479 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_MSB 26
69480 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
69481 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_WIDTH 1
69482 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */
69483 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET_MSK 0x04000000
69484 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */
69485 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_CLR_MSK 0xfbffffff
69486 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
69487 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_RESET 0x0
69488 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 field value from a register. */
69489 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
69490 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value suitable for setting the register. */
69491 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
69492 
69493 /*
69494  * Field : Mask Byte Control - mbc_3
69495  *
69496  * This array of bits are mask control bits for comparison of each of the MAC
69497  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69498  * received DA or SA with the contents of MAC Address79 high and low registers.
69499  * Each bit controls the masking of the bytes. You can filter a group of addresses
69500  * (known as group address filtering) by masking one or more bytes of the address.
69501  *
69502  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69503  *
69504  * Field Enumeration Values:
69505  *
69506  * Enum | Value | Description
69507  * :----------------------------------------------|:------|:------------------------------------
69508  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69509  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69510  *
69511  * Field Access Macros:
69512  *
69513  */
69514 /*
69515  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3
69516  *
69517  * Byte is unmasked (i.e. is compared)
69518  */
69519 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED 0x0
69520 /*
69521  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3
69522  *
69523  * Byte is masked (i.e. not compared)
69524  */
69525 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED 0x1
69526 
69527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
69528 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_LSB 27
69529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
69530 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_MSB 27
69531 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
69532 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_WIDTH 1
69533 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */
69534 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET_MSK 0x08000000
69535 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */
69536 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_CLR_MSK 0xf7ffffff
69537 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
69538 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_RESET 0x0
69539 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 field value from a register. */
69540 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
69541 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value suitable for setting the register. */
69542 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
69543 
69544 /*
69545  * Field : Mask Byte Control - mbc_4
69546  *
69547  * This array of bits are mask control bits for comparison of each of the MAC
69548  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69549  * received DA or SA with the contents of MAC Address79 high and low registers.
69550  * Each bit controls the masking of the bytes. You can filter a group of addresses
69551  * (known as group address filtering) by masking one or more bytes of the address.
69552  *
69553  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69554  *
69555  * Field Enumeration Values:
69556  *
69557  * Enum | Value | Description
69558  * :----------------------------------------------|:------|:------------------------------------
69559  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69560  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69561  *
69562  * Field Access Macros:
69563  *
69564  */
69565 /*
69566  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4
69567  *
69568  * Byte is unmasked (i.e. is compared)
69569  */
69570 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED 0x0
69571 /*
69572  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4
69573  *
69574  * Byte is masked (i.e. not compared)
69575  */
69576 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED 0x1
69577 
69578 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
69579 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_LSB 28
69580 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
69581 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_MSB 28
69582 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
69583 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_WIDTH 1
69584 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */
69585 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET_MSK 0x10000000
69586 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */
69587 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_CLR_MSK 0xefffffff
69588 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
69589 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_RESET 0x0
69590 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 field value from a register. */
69591 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
69592 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value suitable for setting the register. */
69593 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
69594 
69595 /*
69596  * Field : Mask Byte Control - mbc_5
69597  *
69598  * This array of bits are mask control bits for comparison of each of the MAC
69599  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69600  * received DA or SA with the contents of MAC Address79 high and low registers.
69601  * Each bit controls the masking of the bytes. You can filter a group of addresses
69602  * (known as group address filtering) by masking one or more bytes of the address.
69603  *
69604  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69605  *
69606  * Field Enumeration Values:
69607  *
69608  * Enum | Value | Description
69609  * :----------------------------------------------|:------|:------------------------------------
69610  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69611  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69612  *
69613  * Field Access Macros:
69614  *
69615  */
69616 /*
69617  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5
69618  *
69619  * Byte is unmasked (i.e. is compared)
69620  */
69621 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED 0x0
69622 /*
69623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5
69624  *
69625  * Byte is masked (i.e. not compared)
69626  */
69627 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED 0x1
69628 
69629 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
69630 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_LSB 29
69631 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
69632 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_MSB 29
69633 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
69634 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_WIDTH 1
69635 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */
69636 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET_MSK 0x20000000
69637 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */
69638 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_CLR_MSK 0xdfffffff
69639 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
69640 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_RESET 0x0
69641 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 field value from a register. */
69642 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
69643 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value suitable for setting the register. */
69644 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
69645 
69646 /*
69647  * Field : Source Address - sa
69648  *
69649  * When this bit is enabled, the MAC Address79[47:0] is used to compare with the SA
69650  * fields of the received frame. When this bit is disabled, the MAC Address79[47:0]
69651  * is used to compare with the DA fields of the received frame.
69652  *
69653  * Field Enumeration Values:
69654  *
69655  * Enum | Value | Description
69656  * :----------------------------------------|:------|:-----------------------------
69657  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
69658  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END | 0x1 | MAC address compare enabled
69659  *
69660  * Field Access Macros:
69661  *
69662  */
69663 /*
69664  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA
69665  *
69666  * MAC address compare disabled
69667  */
69668 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD 0x0
69669 /*
69670  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA
69671  *
69672  * MAC address compare enabled
69673  */
69674 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END 0x1
69675 
69676 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
69677 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_LSB 30
69678 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
69679 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_MSB 30
69680 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
69681 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_WIDTH 1
69682 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */
69683 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET_MSK 0x40000000
69684 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */
69685 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_CLR_MSK 0xbfffffff
69686 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
69687 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_RESET 0x0
69688 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA field value from a register. */
69689 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
69690 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value suitable for setting the register. */
69691 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
69692 
69693 /*
69694  * Field : Address Enable - ae
69695  *
69696  * When this bit is enabled, the address filter block uses the 80th MAC address for
69697  * perfect filtering. When this bit is disabled, the address filter block ignores
69698  * the address for filtering.
69699  *
69700  * Field Enumeration Values:
69701  *
69702  * Enum | Value | Description
69703  * :----------------------------------------|:------|:--------------------------------------
69704  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
69705  * ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
69706  *
69707  * Field Access Macros:
69708  *
69709  */
69710 /*
69711  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
69712  *
69713  * Second MAC address filtering disabled
69714  */
69715 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD 0x0
69716 /*
69717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
69718  *
69719  * Second MAC address filtering enabled
69720  */
69721 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END 0x1
69722 
69723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
69724 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_LSB 31
69725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
69726 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_MSB 31
69727 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
69728 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_WIDTH 1
69729 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
69730 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET_MSK 0x80000000
69731 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
69732 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_CLR_MSK 0x7fffffff
69733 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
69734 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_RESET 0x0
69735 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE field value from a register. */
69736 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
69737 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value suitable for setting the register. */
69738 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
69739 
69740 #ifndef __ASSEMBLY__
69741 /*
69742  * WARNING: The C register and register group struct declarations are provided for
69743  * convenience and illustrative purposes. They should, however, be used with
69744  * caution as the C language standard provides no guarantees about the alignment or
69745  * atomicity of device memory accesses. The recommended practice for writing
69746  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69747  * alt_write_word() functions.
69748  *
69749  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH.
69750  */
69751 struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s
69752 {
69753  uint32_t addrhi : 16; /* MAC Address79 [47:32] */
69754  uint32_t : 8; /* *UNDEFINED* */
69755  uint32_t mbc_0 : 1; /* Mask Byte Control */
69756  uint32_t mbc_1 : 1; /* Mask Byte Control */
69757  uint32_t mbc_2 : 1; /* Mask Byte Control */
69758  uint32_t mbc_3 : 1; /* Mask Byte Control */
69759  uint32_t mbc_4 : 1; /* Mask Byte Control */
69760  uint32_t mbc_5 : 1; /* Mask Byte Control */
69761  uint32_t sa : 1; /* Source Address */
69762  uint32_t ae : 1; /* Address Enable */
69763 };
69764 
69765 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH. */
69766 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t;
69767 #endif /* __ASSEMBLY__ */
69768 
69769 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register from the beginning of the component. */
69770 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST 0x9f8
69771 /* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register. */
69772 #define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST))
69773 
69774 /*
69775  * Register : Register 639 (MAC Address79 Low Register) - MAC_Address79_Low
69776  *
69777  * The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC
69778  * address of the station.
69779  *
69780  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
69781  * format.
69782  *
69783  * Register Layout
69784  *
69785  * Bits | Access | Reset | Description
69786  * :-------|:-------|:-----------|:---------------------
69787  * [31:0] | RW | 0xffffffff | MAC Address79 [31:0]
69788  *
69789  */
69790 /*
69791  * Field : MAC Address79 [31:0] - addrlo
69792  *
69793  * This field contains the lower 32 bits of the 80th 6-byte MAC address. The
69794  * content of this field is undefined until loaded by software after the
69795  * initialization process.
69796  *
69797  * Field Access Macros:
69798  *
69799  */
69800 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
69801 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_LSB 0
69802 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
69803 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_MSB 31
69804 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
69805 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_WIDTH 32
69806 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
69807 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET_MSK 0xffffffff
69808 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
69809 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_CLR_MSK 0x00000000
69810 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
69811 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_RESET 0xffffffff
69812 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO field value from a register. */
69813 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
69814 /* Produces a ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value suitable for setting the register. */
69815 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
69816 
69817 #ifndef __ASSEMBLY__
69818 /*
69819  * WARNING: The C register and register group struct declarations are provided for
69820  * convenience and illustrative purposes. They should, however, be used with
69821  * caution as the C language standard provides no guarantees about the alignment or
69822  * atomicity of device memory accesses. The recommended practice for writing
69823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
69824  * alt_write_word() functions.
69825  *
69826  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW.
69827  */
69828 struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s
69829 {
69830  uint32_t addrlo : 32; /* MAC Address79 [31:0] */
69831 };
69832 
69833 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW. */
69834 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s ALT_EMAC_GMAC_MAC_ADDR79_LOW_t;
69835 #endif /* __ASSEMBLY__ */
69836 
69837 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register from the beginning of the component. */
69838 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST 0x9fc
69839 /* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register. */
69840 #define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST))
69841 
69842 /*
69843  * Register : Register 640 (MAC Address80 High Register) - MAC_Address80_High
69844  *
69845  * The MAC Address80 High register holds the upper 16 bits of the 81th 6-byte MAC
69846  * address of the station. Because the MAC address registers are configured to be
69847  * double-synchronized to the (G)MII clock domains, the synchronization is
69848  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
69849  * endian mode) of the MAC Address80 Low Register are written. For proper
69850  * synchronization updates, the consecutive writes to this Address Low Register
69851  * should be performed after at least four clock cycles in the destination clock
69852  * domain.
69853  *
69854  * Note that all MAC Address High registers (except MAC Address0 High) have the
69855  * same format.
69856  *
69857  * Register Layout
69858  *
69859  * Bits | Access | Reset | Description
69860  * :--------|:-------|:-------|:----------------------
69861  * [15:0] | RW | 0xffff | MAC Address80 [47:32]
69862  * [23:16] | ??? | 0x0 | *UNDEFINED*
69863  * [24] | RW | 0x0 | Mask Byte Control
69864  * [25] | RW | 0x0 | Mask Byte Control
69865  * [26] | RW | 0x0 | Mask Byte Control
69866  * [27] | RW | 0x0 | Mask Byte Control
69867  * [28] | RW | 0x0 | Mask Byte Control
69868  * [29] | RW | 0x0 | Mask Byte Control
69869  * [30] | RW | 0x0 | Source Address
69870  * [31] | RW | 0x0 | Address Enable
69871  *
69872  */
69873 /*
69874  * Field : MAC Address80 [47:32] - addrhi
69875  *
69876  * This field contains the upper 16 bits (47:32) of the 81th 6-byte MAC address.
69877  *
69878  * Field Access Macros:
69879  *
69880  */
69881 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
69882 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_LSB 0
69883 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
69884 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_MSB 15
69885 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
69886 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_WIDTH 16
69887 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
69888 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET_MSK 0x0000ffff
69889 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
69890 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_CLR_MSK 0xffff0000
69891 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
69892 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_RESET 0xffff
69893 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI field value from a register. */
69894 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
69895 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value suitable for setting the register. */
69896 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
69897 
69898 /*
69899  * Field : Mask Byte Control - mbc_0
69900  *
69901  * This array of bits are mask control bits for comparison of each of the MAC
69902  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69903  * received DA or SA with the contents of MAC Address80 high and low registers.
69904  * Each bit controls the masking of the bytes. You can filter a group of addresses
69905  * (known as group address filtering) by masking one or more bytes of the address.
69906  *
69907  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69908  *
69909  * Field Enumeration Values:
69910  *
69911  * Enum | Value | Description
69912  * :----------------------------------------------|:------|:------------------------------------
69913  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69914  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69915  *
69916  * Field Access Macros:
69917  *
69918  */
69919 /*
69920  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0
69921  *
69922  * Byte is unmasked (i.e. is compared)
69923  */
69924 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED 0x0
69925 /*
69926  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0
69927  *
69928  * Byte is masked (i.e. not compared)
69929  */
69930 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED 0x1
69931 
69932 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
69933 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_LSB 24
69934 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
69935 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_MSB 24
69936 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
69937 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_WIDTH 1
69938 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */
69939 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET_MSK 0x01000000
69940 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */
69941 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_CLR_MSK 0xfeffffff
69942 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
69943 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_RESET 0x0
69944 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 field value from a register. */
69945 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
69946 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value suitable for setting the register. */
69947 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
69948 
69949 /*
69950  * Field : Mask Byte Control - mbc_1
69951  *
69952  * This array of bits are mask control bits for comparison of each of the MAC
69953  * Address bytes. When masked, the MAC does not compare the corresponding byte of
69954  * received DA or SA with the contents of MAC Address80 high and low registers.
69955  * Each bit controls the masking of the bytes. You can filter a group of addresses
69956  * (known as group address filtering) by masking one or more bytes of the address.
69957  *
69958  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
69959  *
69960  * Field Enumeration Values:
69961  *
69962  * Enum | Value | Description
69963  * :----------------------------------------------|:------|:------------------------------------
69964  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
69965  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
69966  *
69967  * Field Access Macros:
69968  *
69969  */
69970 /*
69971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1
69972  *
69973  * Byte is unmasked (i.e. is compared)
69974  */
69975 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED 0x0
69976 /*
69977  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1
69978  *
69979  * Byte is masked (i.e. not compared)
69980  */
69981 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED 0x1
69982 
69983 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
69984 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_LSB 25
69985 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
69986 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_MSB 25
69987 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
69988 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_WIDTH 1
69989 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */
69990 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET_MSK 0x02000000
69991 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */
69992 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_CLR_MSK 0xfdffffff
69993 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
69994 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_RESET 0x0
69995 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 field value from a register. */
69996 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
69997 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value suitable for setting the register. */
69998 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
69999 
70000 /*
70001  * Field : Mask Byte Control - mbc_2
70002  *
70003  * This array of bits are mask control bits for comparison of each of the MAC
70004  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70005  * received DA or SA with the contents of MAC Address80 high and low registers.
70006  * Each bit controls the masking of the bytes. You can filter a group of addresses
70007  * (known as group address filtering) by masking one or more bytes of the address.
70008  *
70009  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70010  *
70011  * Field Enumeration Values:
70012  *
70013  * Enum | Value | Description
70014  * :----------------------------------------------|:------|:------------------------------------
70015  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70016  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70017  *
70018  * Field Access Macros:
70019  *
70020  */
70021 /*
70022  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2
70023  *
70024  * Byte is unmasked (i.e. is compared)
70025  */
70026 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED 0x0
70027 /*
70028  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2
70029  *
70030  * Byte is masked (i.e. not compared)
70031  */
70032 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED 0x1
70033 
70034 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
70035 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_LSB 26
70036 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
70037 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_MSB 26
70038 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
70039 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_WIDTH 1
70040 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */
70041 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET_MSK 0x04000000
70042 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */
70043 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_CLR_MSK 0xfbffffff
70044 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
70045 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_RESET 0x0
70046 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 field value from a register. */
70047 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
70048 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value suitable for setting the register. */
70049 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
70050 
70051 /*
70052  * Field : Mask Byte Control - mbc_3
70053  *
70054  * This array of bits are mask control bits for comparison of each of the MAC
70055  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70056  * received DA or SA with the contents of MAC Address80 high and low registers.
70057  * Each bit controls the masking of the bytes. You can filter a group of addresses
70058  * (known as group address filtering) by masking one or more bytes of the address.
70059  *
70060  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70061  *
70062  * Field Enumeration Values:
70063  *
70064  * Enum | Value | Description
70065  * :----------------------------------------------|:------|:------------------------------------
70066  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70067  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70068  *
70069  * Field Access Macros:
70070  *
70071  */
70072 /*
70073  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3
70074  *
70075  * Byte is unmasked (i.e. is compared)
70076  */
70077 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED 0x0
70078 /*
70079  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3
70080  *
70081  * Byte is masked (i.e. not compared)
70082  */
70083 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED 0x1
70084 
70085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
70086 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_LSB 27
70087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
70088 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_MSB 27
70089 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
70090 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_WIDTH 1
70091 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */
70092 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET_MSK 0x08000000
70093 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */
70094 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_CLR_MSK 0xf7ffffff
70095 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
70096 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_RESET 0x0
70097 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 field value from a register. */
70098 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
70099 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value suitable for setting the register. */
70100 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
70101 
70102 /*
70103  * Field : Mask Byte Control - mbc_4
70104  *
70105  * This array of bits are mask control bits for comparison of each of the MAC
70106  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70107  * received DA or SA with the contents of MAC Address80 high and low registers.
70108  * Each bit controls the masking of the bytes. You can filter a group of addresses
70109  * (known as group address filtering) by masking one or more bytes of the address.
70110  *
70111  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70112  *
70113  * Field Enumeration Values:
70114  *
70115  * Enum | Value | Description
70116  * :----------------------------------------------|:------|:------------------------------------
70117  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70118  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70119  *
70120  * Field Access Macros:
70121  *
70122  */
70123 /*
70124  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4
70125  *
70126  * Byte is unmasked (i.e. is compared)
70127  */
70128 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED 0x0
70129 /*
70130  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4
70131  *
70132  * Byte is masked (i.e. not compared)
70133  */
70134 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED 0x1
70135 
70136 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
70137 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_LSB 28
70138 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
70139 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_MSB 28
70140 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
70141 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_WIDTH 1
70142 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */
70143 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET_MSK 0x10000000
70144 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */
70145 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_CLR_MSK 0xefffffff
70146 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
70147 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_RESET 0x0
70148 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 field value from a register. */
70149 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
70150 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value suitable for setting the register. */
70151 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
70152 
70153 /*
70154  * Field : Mask Byte Control - mbc_5
70155  *
70156  * This array of bits are mask control bits for comparison of each of the MAC
70157  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70158  * received DA or SA with the contents of MAC Address80 high and low registers.
70159  * Each bit controls the masking of the bytes. You can filter a group of addresses
70160  * (known as group address filtering) by masking one or more bytes of the address.
70161  *
70162  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70163  *
70164  * Field Enumeration Values:
70165  *
70166  * Enum | Value | Description
70167  * :----------------------------------------------|:------|:------------------------------------
70168  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70169  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70170  *
70171  * Field Access Macros:
70172  *
70173  */
70174 /*
70175  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5
70176  *
70177  * Byte is unmasked (i.e. is compared)
70178  */
70179 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED 0x0
70180 /*
70181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5
70182  *
70183  * Byte is masked (i.e. not compared)
70184  */
70185 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED 0x1
70186 
70187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
70188 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_LSB 29
70189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
70190 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_MSB 29
70191 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
70192 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_WIDTH 1
70193 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */
70194 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET_MSK 0x20000000
70195 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */
70196 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_CLR_MSK 0xdfffffff
70197 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
70198 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_RESET 0x0
70199 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 field value from a register. */
70200 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
70201 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value suitable for setting the register. */
70202 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
70203 
70204 /*
70205  * Field : Source Address - sa
70206  *
70207  * When this bit is enabled, the MAC Address80[47:0] is used to compare with the SA
70208  * fields of the received frame. When this bit is disabled, the MAC Address80[47:0]
70209  * is used to compare with the DA fields of the received frame.
70210  *
70211  * Field Enumeration Values:
70212  *
70213  * Enum | Value | Description
70214  * :----------------------------------------|:------|:-----------------------------
70215  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
70216  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END | 0x1 | MAC address compare enabled
70217  *
70218  * Field Access Macros:
70219  *
70220  */
70221 /*
70222  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA
70223  *
70224  * MAC address compare disabled
70225  */
70226 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD 0x0
70227 /*
70228  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA
70229  *
70230  * MAC address compare enabled
70231  */
70232 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END 0x1
70233 
70234 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
70235 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_LSB 30
70236 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
70237 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_MSB 30
70238 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
70239 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_WIDTH 1
70240 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */
70241 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET_MSK 0x40000000
70242 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */
70243 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_CLR_MSK 0xbfffffff
70244 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
70245 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_RESET 0x0
70246 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA field value from a register. */
70247 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
70248 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value suitable for setting the register. */
70249 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
70250 
70251 /*
70252  * Field : Address Enable - ae
70253  *
70254  * When this bit is enabled, the address filter block uses the 81th MAC address for
70255  * perfect filtering. When this bit is disabled, the address filter block ignores
70256  * the address for filtering.
70257  *
70258  * Field Enumeration Values:
70259  *
70260  * Enum | Value | Description
70261  * :----------------------------------------|:------|:--------------------------------------
70262  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
70263  * ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
70264  *
70265  * Field Access Macros:
70266  *
70267  */
70268 /*
70269  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
70270  *
70271  * Second MAC address filtering disabled
70272  */
70273 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD 0x0
70274 /*
70275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
70276  *
70277  * Second MAC address filtering enabled
70278  */
70279 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END 0x1
70280 
70281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
70282 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_LSB 31
70283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
70284 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_MSB 31
70285 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
70286 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_WIDTH 1
70287 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
70288 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET_MSK 0x80000000
70289 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
70290 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_CLR_MSK 0x7fffffff
70291 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
70292 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_RESET 0x0
70293 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE field value from a register. */
70294 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
70295 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value suitable for setting the register. */
70296 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
70297 
70298 #ifndef __ASSEMBLY__
70299 /*
70300  * WARNING: The C register and register group struct declarations are provided for
70301  * convenience and illustrative purposes. They should, however, be used with
70302  * caution as the C language standard provides no guarantees about the alignment or
70303  * atomicity of device memory accesses. The recommended practice for writing
70304  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70305  * alt_write_word() functions.
70306  *
70307  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH.
70308  */
70309 struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s
70310 {
70311  uint32_t addrhi : 16; /* MAC Address80 [47:32] */
70312  uint32_t : 8; /* *UNDEFINED* */
70313  uint32_t mbc_0 : 1; /* Mask Byte Control */
70314  uint32_t mbc_1 : 1; /* Mask Byte Control */
70315  uint32_t mbc_2 : 1; /* Mask Byte Control */
70316  uint32_t mbc_3 : 1; /* Mask Byte Control */
70317  uint32_t mbc_4 : 1; /* Mask Byte Control */
70318  uint32_t mbc_5 : 1; /* Mask Byte Control */
70319  uint32_t sa : 1; /* Source Address */
70320  uint32_t ae : 1; /* Address Enable */
70321 };
70322 
70323 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH. */
70324 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t;
70325 #endif /* __ASSEMBLY__ */
70326 
70327 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register from the beginning of the component. */
70328 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST 0xa00
70329 /* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register. */
70330 #define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST))
70331 
70332 /*
70333  * Register : Register 641 (MAC Address80 Low Register) - MAC_Address80_Low
70334  *
70335  * The MAC Address80 Low register holds the lower 32 bits of the 81th 6-byte MAC
70336  * address of the station.
70337  *
70338  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
70339  * format.
70340  *
70341  * Register Layout
70342  *
70343  * Bits | Access | Reset | Description
70344  * :-------|:-------|:-----------|:---------------------
70345  * [31:0] | RW | 0xffffffff | MAC Address80 [31:0]
70346  *
70347  */
70348 /*
70349  * Field : MAC Address80 [31:0] - addrlo
70350  *
70351  * This field contains the lower 32 bits of the 81th 6-byte MAC address. The
70352  * content of this field is undefined until loaded by software after the
70353  * initialization process.
70354  *
70355  * Field Access Macros:
70356  *
70357  */
70358 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
70359 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_LSB 0
70360 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
70361 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_MSB 31
70362 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
70363 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_WIDTH 32
70364 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
70365 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET_MSK 0xffffffff
70366 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
70367 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_CLR_MSK 0x00000000
70368 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
70369 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_RESET 0xffffffff
70370 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO field value from a register. */
70371 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
70372 /* Produces a ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value suitable for setting the register. */
70373 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
70374 
70375 #ifndef __ASSEMBLY__
70376 /*
70377  * WARNING: The C register and register group struct declarations are provided for
70378  * convenience and illustrative purposes. They should, however, be used with
70379  * caution as the C language standard provides no guarantees about the alignment or
70380  * atomicity of device memory accesses. The recommended practice for writing
70381  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70382  * alt_write_word() functions.
70383  *
70384  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW.
70385  */
70386 struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s
70387 {
70388  uint32_t addrlo : 32; /* MAC Address80 [31:0] */
70389 };
70390 
70391 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW. */
70392 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s ALT_EMAC_GMAC_MAC_ADDR80_LOW_t;
70393 #endif /* __ASSEMBLY__ */
70394 
70395 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register from the beginning of the component. */
70396 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST 0xa04
70397 /* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register. */
70398 #define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST))
70399 
70400 /*
70401  * Register : Register 642 (MAC Address81 High Register) - MAC_Address81_High
70402  *
70403  * The MAC Address81 High register holds the upper 16 bits of the 82th 6-byte MAC
70404  * address of the station. Because the MAC address registers are configured to be
70405  * double-synchronized to the (G)MII clock domains, the synchronization is
70406  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
70407  * endian mode) of the MAC Address81 Low Register are written. For proper
70408  * synchronization updates, the consecutive writes to this Address Low Register
70409  * should be performed after at least four clock cycles in the destination clock
70410  * domain.
70411  *
70412  * Note that all MAC Address High registers (except MAC Address0 High) have the
70413  * same format.
70414  *
70415  * Register Layout
70416  *
70417  * Bits | Access | Reset | Description
70418  * :--------|:-------|:-------|:----------------------
70419  * [15:0] | RW | 0xffff | MAC Address81 [47:32]
70420  * [23:16] | ??? | 0x0 | *UNDEFINED*
70421  * [24] | RW | 0x0 | Mask Byte Control
70422  * [25] | RW | 0x0 | Mask Byte Control
70423  * [26] | RW | 0x0 | Mask Byte Control
70424  * [27] | RW | 0x0 | Mask Byte Control
70425  * [28] | RW | 0x0 | Mask Byte Control
70426  * [29] | RW | 0x0 | Mask Byte Control
70427  * [30] | RW | 0x0 | Source Address
70428  * [31] | RW | 0x0 | Address Enable
70429  *
70430  */
70431 /*
70432  * Field : MAC Address81 [47:32] - addrhi
70433  *
70434  * This field contains the upper 16 bits (47:32) of the 82th 6-byte MAC address.
70435  *
70436  * Field Access Macros:
70437  *
70438  */
70439 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
70440 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_LSB 0
70441 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
70442 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_MSB 15
70443 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
70444 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_WIDTH 16
70445 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
70446 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET_MSK 0x0000ffff
70447 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
70448 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_CLR_MSK 0xffff0000
70449 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
70450 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_RESET 0xffff
70451 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI field value from a register. */
70452 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
70453 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value suitable for setting the register. */
70454 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
70455 
70456 /*
70457  * Field : Mask Byte Control - mbc_0
70458  *
70459  * This array of bits are mask control bits for comparison of each of the MAC
70460  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70461  * received DA or SA with the contents of MAC Address81 high and low registers.
70462  * Each bit controls the masking of the bytes. You can filter a group of addresses
70463  * (known as group address filtering) by masking one or more bytes of the address.
70464  *
70465  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70466  *
70467  * Field Enumeration Values:
70468  *
70469  * Enum | Value | Description
70470  * :----------------------------------------------|:------|:------------------------------------
70471  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70472  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70473  *
70474  * Field Access Macros:
70475  *
70476  */
70477 /*
70478  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0
70479  *
70480  * Byte is unmasked (i.e. is compared)
70481  */
70482 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED 0x0
70483 /*
70484  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0
70485  *
70486  * Byte is masked (i.e. not compared)
70487  */
70488 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED 0x1
70489 
70490 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
70491 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_LSB 24
70492 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
70493 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_MSB 24
70494 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
70495 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_WIDTH 1
70496 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */
70497 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET_MSK 0x01000000
70498 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */
70499 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_CLR_MSK 0xfeffffff
70500 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
70501 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_RESET 0x0
70502 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 field value from a register. */
70503 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
70504 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value suitable for setting the register. */
70505 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
70506 
70507 /*
70508  * Field : Mask Byte Control - mbc_1
70509  *
70510  * This array of bits are mask control bits for comparison of each of the MAC
70511  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70512  * received DA or SA with the contents of MAC Address81 high and low registers.
70513  * Each bit controls the masking of the bytes. You can filter a group of addresses
70514  * (known as group address filtering) by masking one or more bytes of the address.
70515  *
70516  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70517  *
70518  * Field Enumeration Values:
70519  *
70520  * Enum | Value | Description
70521  * :----------------------------------------------|:------|:------------------------------------
70522  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70523  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70524  *
70525  * Field Access Macros:
70526  *
70527  */
70528 /*
70529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1
70530  *
70531  * Byte is unmasked (i.e. is compared)
70532  */
70533 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED 0x0
70534 /*
70535  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1
70536  *
70537  * Byte is masked (i.e. not compared)
70538  */
70539 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED 0x1
70540 
70541 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
70542 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_LSB 25
70543 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
70544 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_MSB 25
70545 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
70546 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_WIDTH 1
70547 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */
70548 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET_MSK 0x02000000
70549 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */
70550 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_CLR_MSK 0xfdffffff
70551 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
70552 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_RESET 0x0
70553 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 field value from a register. */
70554 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
70555 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value suitable for setting the register. */
70556 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
70557 
70558 /*
70559  * Field : Mask Byte Control - mbc_2
70560  *
70561  * This array of bits are mask control bits for comparison of each of the MAC
70562  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70563  * received DA or SA with the contents of MAC Address81 high and low registers.
70564  * Each bit controls the masking of the bytes. You can filter a group of addresses
70565  * (known as group address filtering) by masking one or more bytes of the address.
70566  *
70567  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70568  *
70569  * Field Enumeration Values:
70570  *
70571  * Enum | Value | Description
70572  * :----------------------------------------------|:------|:------------------------------------
70573  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70574  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70575  *
70576  * Field Access Macros:
70577  *
70578  */
70579 /*
70580  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2
70581  *
70582  * Byte is unmasked (i.e. is compared)
70583  */
70584 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED 0x0
70585 /*
70586  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2
70587  *
70588  * Byte is masked (i.e. not compared)
70589  */
70590 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED 0x1
70591 
70592 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
70593 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_LSB 26
70594 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
70595 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_MSB 26
70596 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
70597 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_WIDTH 1
70598 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */
70599 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET_MSK 0x04000000
70600 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */
70601 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_CLR_MSK 0xfbffffff
70602 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
70603 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_RESET 0x0
70604 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 field value from a register. */
70605 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
70606 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value suitable for setting the register. */
70607 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
70608 
70609 /*
70610  * Field : Mask Byte Control - mbc_3
70611  *
70612  * This array of bits are mask control bits for comparison of each of the MAC
70613  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70614  * received DA or SA with the contents of MAC Address81 high and low registers.
70615  * Each bit controls the masking of the bytes. You can filter a group of addresses
70616  * (known as group address filtering) by masking one or more bytes of the address.
70617  *
70618  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70619  *
70620  * Field Enumeration Values:
70621  *
70622  * Enum | Value | Description
70623  * :----------------------------------------------|:------|:------------------------------------
70624  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70625  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70626  *
70627  * Field Access Macros:
70628  *
70629  */
70630 /*
70631  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3
70632  *
70633  * Byte is unmasked (i.e. is compared)
70634  */
70635 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED 0x0
70636 /*
70637  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3
70638  *
70639  * Byte is masked (i.e. not compared)
70640  */
70641 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED 0x1
70642 
70643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
70644 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_LSB 27
70645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
70646 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_MSB 27
70647 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
70648 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_WIDTH 1
70649 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */
70650 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET_MSK 0x08000000
70651 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */
70652 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_CLR_MSK 0xf7ffffff
70653 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
70654 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_RESET 0x0
70655 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 field value from a register. */
70656 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
70657 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value suitable for setting the register. */
70658 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
70659 
70660 /*
70661  * Field : Mask Byte Control - mbc_4
70662  *
70663  * This array of bits are mask control bits for comparison of each of the MAC
70664  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70665  * received DA or SA with the contents of MAC Address81 high and low registers.
70666  * Each bit controls the masking of the bytes. You can filter a group of addresses
70667  * (known as group address filtering) by masking one or more bytes of the address.
70668  *
70669  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70670  *
70671  * Field Enumeration Values:
70672  *
70673  * Enum | Value | Description
70674  * :----------------------------------------------|:------|:------------------------------------
70675  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70676  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70677  *
70678  * Field Access Macros:
70679  *
70680  */
70681 /*
70682  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4
70683  *
70684  * Byte is unmasked (i.e. is compared)
70685  */
70686 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED 0x0
70687 /*
70688  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4
70689  *
70690  * Byte is masked (i.e. not compared)
70691  */
70692 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED 0x1
70693 
70694 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
70695 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_LSB 28
70696 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
70697 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_MSB 28
70698 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
70699 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_WIDTH 1
70700 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */
70701 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET_MSK 0x10000000
70702 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */
70703 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_CLR_MSK 0xefffffff
70704 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
70705 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_RESET 0x0
70706 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 field value from a register. */
70707 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
70708 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value suitable for setting the register. */
70709 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
70710 
70711 /*
70712  * Field : Mask Byte Control - mbc_5
70713  *
70714  * This array of bits are mask control bits for comparison of each of the MAC
70715  * Address bytes. When masked, the MAC does not compare the corresponding byte of
70716  * received DA or SA with the contents of MAC Address81 high and low registers.
70717  * Each bit controls the masking of the bytes. You can filter a group of addresses
70718  * (known as group address filtering) by masking one or more bytes of the address.
70719  *
70720  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
70721  *
70722  * Field Enumeration Values:
70723  *
70724  * Enum | Value | Description
70725  * :----------------------------------------------|:------|:------------------------------------
70726  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
70727  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
70728  *
70729  * Field Access Macros:
70730  *
70731  */
70732 /*
70733  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5
70734  *
70735  * Byte is unmasked (i.e. is compared)
70736  */
70737 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED 0x0
70738 /*
70739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5
70740  *
70741  * Byte is masked (i.e. not compared)
70742  */
70743 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED 0x1
70744 
70745 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
70746 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_LSB 29
70747 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
70748 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_MSB 29
70749 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
70750 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_WIDTH 1
70751 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */
70752 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET_MSK 0x20000000
70753 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */
70754 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_CLR_MSK 0xdfffffff
70755 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
70756 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_RESET 0x0
70757 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 field value from a register. */
70758 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
70759 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value suitable for setting the register. */
70760 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
70761 
70762 /*
70763  * Field : Source Address - sa
70764  *
70765  * When this bit is enabled, the MAC Address81[47:0] is used to compare with the SA
70766  * fields of the received frame. When this bit is disabled, the MAC Address81[47:0]
70767  * is used to compare with the DA fields of the received frame.
70768  *
70769  * Field Enumeration Values:
70770  *
70771  * Enum | Value | Description
70772  * :----------------------------------------|:------|:-----------------------------
70773  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
70774  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END | 0x1 | MAC address compare enabled
70775  *
70776  * Field Access Macros:
70777  *
70778  */
70779 /*
70780  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA
70781  *
70782  * MAC address compare disabled
70783  */
70784 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD 0x0
70785 /*
70786  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA
70787  *
70788  * MAC address compare enabled
70789  */
70790 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END 0x1
70791 
70792 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
70793 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_LSB 30
70794 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
70795 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_MSB 30
70796 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
70797 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_WIDTH 1
70798 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */
70799 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET_MSK 0x40000000
70800 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */
70801 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_CLR_MSK 0xbfffffff
70802 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
70803 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_RESET 0x0
70804 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA field value from a register. */
70805 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
70806 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value suitable for setting the register. */
70807 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
70808 
70809 /*
70810  * Field : Address Enable - ae
70811  *
70812  * When this bit is enabled, the address filter block uses the 82th MAC address for
70813  * perfect filtering. When this bit is disabled, the address filter block ignores
70814  * the address for filtering.
70815  *
70816  * Field Enumeration Values:
70817  *
70818  * Enum | Value | Description
70819  * :----------------------------------------|:------|:--------------------------------------
70820  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
70821  * ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
70822  *
70823  * Field Access Macros:
70824  *
70825  */
70826 /*
70827  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
70828  *
70829  * Second MAC address filtering disabled
70830  */
70831 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD 0x0
70832 /*
70833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
70834  *
70835  * Second MAC address filtering enabled
70836  */
70837 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END 0x1
70838 
70839 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
70840 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_LSB 31
70841 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
70842 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_MSB 31
70843 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
70844 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_WIDTH 1
70845 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
70846 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET_MSK 0x80000000
70847 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
70848 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_CLR_MSK 0x7fffffff
70849 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
70850 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_RESET 0x0
70851 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE field value from a register. */
70852 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
70853 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value suitable for setting the register. */
70854 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
70855 
70856 #ifndef __ASSEMBLY__
70857 /*
70858  * WARNING: The C register and register group struct declarations are provided for
70859  * convenience and illustrative purposes. They should, however, be used with
70860  * caution as the C language standard provides no guarantees about the alignment or
70861  * atomicity of device memory accesses. The recommended practice for writing
70862  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70863  * alt_write_word() functions.
70864  *
70865  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH.
70866  */
70867 struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s
70868 {
70869  uint32_t addrhi : 16; /* MAC Address81 [47:32] */
70870  uint32_t : 8; /* *UNDEFINED* */
70871  uint32_t mbc_0 : 1; /* Mask Byte Control */
70872  uint32_t mbc_1 : 1; /* Mask Byte Control */
70873  uint32_t mbc_2 : 1; /* Mask Byte Control */
70874  uint32_t mbc_3 : 1; /* Mask Byte Control */
70875  uint32_t mbc_4 : 1; /* Mask Byte Control */
70876  uint32_t mbc_5 : 1; /* Mask Byte Control */
70877  uint32_t sa : 1; /* Source Address */
70878  uint32_t ae : 1; /* Address Enable */
70879 };
70880 
70881 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH. */
70882 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t;
70883 #endif /* __ASSEMBLY__ */
70884 
70885 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register from the beginning of the component. */
70886 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST 0xa08
70887 /* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register. */
70888 #define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST))
70889 
70890 /*
70891  * Register : Register 643 (MAC Address81 Low Register) - MAC_Address81_Low
70892  *
70893  * The MAC Address81 Low register holds the lower 32 bits of the 82th 6-byte MAC
70894  * address of the station.
70895  *
70896  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
70897  * format.
70898  *
70899  * Register Layout
70900  *
70901  * Bits | Access | Reset | Description
70902  * :-------|:-------|:-----------|:---------------------
70903  * [31:0] | RW | 0xffffffff | MAC Address81 [31:0]
70904  *
70905  */
70906 /*
70907  * Field : MAC Address81 [31:0] - addrlo
70908  *
70909  * This field contains the lower 32 bits of the 82th 6-byte MAC address. The
70910  * content of this field is undefined until loaded by software after the
70911  * initialization process.
70912  *
70913  * Field Access Macros:
70914  *
70915  */
70916 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
70917 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_LSB 0
70918 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
70919 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_MSB 31
70920 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
70921 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_WIDTH 32
70922 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
70923 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET_MSK 0xffffffff
70924 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
70925 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_CLR_MSK 0x00000000
70926 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
70927 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_RESET 0xffffffff
70928 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO field value from a register. */
70929 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
70930 /* Produces a ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value suitable for setting the register. */
70931 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
70932 
70933 #ifndef __ASSEMBLY__
70934 /*
70935  * WARNING: The C register and register group struct declarations are provided for
70936  * convenience and illustrative purposes. They should, however, be used with
70937  * caution as the C language standard provides no guarantees about the alignment or
70938  * atomicity of device memory accesses. The recommended practice for writing
70939  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
70940  * alt_write_word() functions.
70941  *
70942  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW.
70943  */
70944 struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s
70945 {
70946  uint32_t addrlo : 32; /* MAC Address81 [31:0] */
70947 };
70948 
70949 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW. */
70950 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s ALT_EMAC_GMAC_MAC_ADDR81_LOW_t;
70951 #endif /* __ASSEMBLY__ */
70952 
70953 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register from the beginning of the component. */
70954 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST 0xa0c
70955 /* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register. */
70956 #define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST))
70957 
70958 /*
70959  * Register : Register 644 (MAC Address82 High Register) - MAC_Address82_High
70960  *
70961  * The MAC Address82 High register holds the upper 16 bits of the 83th 6-byte MAC
70962  * address of the station. Because the MAC address registers are configured to be
70963  * double-synchronized to the (G)MII clock domains, the synchronization is
70964  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
70965  * endian mode) of the MAC Address82 Low Register are written. For proper
70966  * synchronization updates, the consecutive writes to this Address Low Register
70967  * should be performed after at least four clock cycles in the destination clock
70968  * domain.
70969  *
70970  * Note that all MAC Address High registers (except MAC Address0 High) have the
70971  * same format.
70972  *
70973  * Register Layout
70974  *
70975  * Bits | Access | Reset | Description
70976  * :--------|:-------|:-------|:----------------------
70977  * [15:0] | RW | 0xffff | MAC Address82 [47:32]
70978  * [23:16] | ??? | 0x0 | *UNDEFINED*
70979  * [24] | RW | 0x0 | Mask Byte Control
70980  * [25] | RW | 0x0 | Mask Byte Control
70981  * [26] | RW | 0x0 | Mask Byte Control
70982  * [27] | RW | 0x0 | Mask Byte Control
70983  * [28] | RW | 0x0 | Mask Byte Control
70984  * [29] | RW | 0x0 | Mask Byte Control
70985  * [30] | RW | 0x0 | Source Address
70986  * [31] | RW | 0x0 | Address Enable
70987  *
70988  */
70989 /*
70990  * Field : MAC Address82 [47:32] - addrhi
70991  *
70992  * This field contains the upper 16 bits (47:32) of the 83th 6-byte MAC address.
70993  *
70994  * Field Access Macros:
70995  *
70996  */
70997 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
70998 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_LSB 0
70999 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
71000 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_MSB 15
71001 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
71002 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_WIDTH 16
71003 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
71004 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET_MSK 0x0000ffff
71005 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
71006 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_CLR_MSK 0xffff0000
71007 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
71008 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_RESET 0xffff
71009 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI field value from a register. */
71010 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
71011 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value suitable for setting the register. */
71012 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
71013 
71014 /*
71015  * Field : Mask Byte Control - mbc_0
71016  *
71017  * This array of bits are mask control bits for comparison of each of the MAC
71018  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71019  * received DA or SA with the contents of MAC Address82 high and low registers.
71020  * Each bit controls the masking of the bytes. You can filter a group of addresses
71021  * (known as group address filtering) by masking one or more bytes of the address.
71022  *
71023  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71024  *
71025  * Field Enumeration Values:
71026  *
71027  * Enum | Value | Description
71028  * :----------------------------------------------|:------|:------------------------------------
71029  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71030  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71031  *
71032  * Field Access Macros:
71033  *
71034  */
71035 /*
71036  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0
71037  *
71038  * Byte is unmasked (i.e. is compared)
71039  */
71040 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED 0x0
71041 /*
71042  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0
71043  *
71044  * Byte is masked (i.e. not compared)
71045  */
71046 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED 0x1
71047 
71048 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
71049 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_LSB 24
71050 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
71051 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_MSB 24
71052 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
71053 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_WIDTH 1
71054 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */
71055 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET_MSK 0x01000000
71056 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */
71057 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_CLR_MSK 0xfeffffff
71058 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
71059 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_RESET 0x0
71060 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 field value from a register. */
71061 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
71062 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value suitable for setting the register. */
71063 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
71064 
71065 /*
71066  * Field : Mask Byte Control - mbc_1
71067  *
71068  * This array of bits are mask control bits for comparison of each of the MAC
71069  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71070  * received DA or SA with the contents of MAC Address82 high and low registers.
71071  * Each bit controls the masking of the bytes. You can filter a group of addresses
71072  * (known as group address filtering) by masking one or more bytes of the address.
71073  *
71074  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71075  *
71076  * Field Enumeration Values:
71077  *
71078  * Enum | Value | Description
71079  * :----------------------------------------------|:------|:------------------------------------
71080  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71081  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71082  *
71083  * Field Access Macros:
71084  *
71085  */
71086 /*
71087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1
71088  *
71089  * Byte is unmasked (i.e. is compared)
71090  */
71091 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED 0x0
71092 /*
71093  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1
71094  *
71095  * Byte is masked (i.e. not compared)
71096  */
71097 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED 0x1
71098 
71099 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
71100 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_LSB 25
71101 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
71102 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_MSB 25
71103 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
71104 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_WIDTH 1
71105 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */
71106 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET_MSK 0x02000000
71107 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */
71108 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_CLR_MSK 0xfdffffff
71109 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
71110 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_RESET 0x0
71111 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 field value from a register. */
71112 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
71113 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value suitable for setting the register. */
71114 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
71115 
71116 /*
71117  * Field : Mask Byte Control - mbc_2
71118  *
71119  * This array of bits are mask control bits for comparison of each of the MAC
71120  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71121  * received DA or SA with the contents of MAC Address82 high and low registers.
71122  * Each bit controls the masking of the bytes. You can filter a group of addresses
71123  * (known as group address filtering) by masking one or more bytes of the address.
71124  *
71125  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71126  *
71127  * Field Enumeration Values:
71128  *
71129  * Enum | Value | Description
71130  * :----------------------------------------------|:------|:------------------------------------
71131  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71132  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71133  *
71134  * Field Access Macros:
71135  *
71136  */
71137 /*
71138  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2
71139  *
71140  * Byte is unmasked (i.e. is compared)
71141  */
71142 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED 0x0
71143 /*
71144  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2
71145  *
71146  * Byte is masked (i.e. not compared)
71147  */
71148 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED 0x1
71149 
71150 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
71151 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_LSB 26
71152 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
71153 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_MSB 26
71154 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
71155 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_WIDTH 1
71156 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */
71157 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET_MSK 0x04000000
71158 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */
71159 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_CLR_MSK 0xfbffffff
71160 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
71161 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_RESET 0x0
71162 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 field value from a register. */
71163 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
71164 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value suitable for setting the register. */
71165 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
71166 
71167 /*
71168  * Field : Mask Byte Control - mbc_3
71169  *
71170  * This array of bits are mask control bits for comparison of each of the MAC
71171  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71172  * received DA or SA with the contents of MAC Address82 high and low registers.
71173  * Each bit controls the masking of the bytes. You can filter a group of addresses
71174  * (known as group address filtering) by masking one or more bytes of the address.
71175  *
71176  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71177  *
71178  * Field Enumeration Values:
71179  *
71180  * Enum | Value | Description
71181  * :----------------------------------------------|:------|:------------------------------------
71182  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71183  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71184  *
71185  * Field Access Macros:
71186  *
71187  */
71188 /*
71189  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3
71190  *
71191  * Byte is unmasked (i.e. is compared)
71192  */
71193 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED 0x0
71194 /*
71195  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3
71196  *
71197  * Byte is masked (i.e. not compared)
71198  */
71199 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED 0x1
71200 
71201 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
71202 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_LSB 27
71203 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
71204 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_MSB 27
71205 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
71206 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_WIDTH 1
71207 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */
71208 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET_MSK 0x08000000
71209 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */
71210 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_CLR_MSK 0xf7ffffff
71211 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
71212 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_RESET 0x0
71213 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 field value from a register. */
71214 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
71215 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value suitable for setting the register. */
71216 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
71217 
71218 /*
71219  * Field : Mask Byte Control - mbc_4
71220  *
71221  * This array of bits are mask control bits for comparison of each of the MAC
71222  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71223  * received DA or SA with the contents of MAC Address82 high and low registers.
71224  * Each bit controls the masking of the bytes. You can filter a group of addresses
71225  * (known as group address filtering) by masking one or more bytes of the address.
71226  *
71227  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71228  *
71229  * Field Enumeration Values:
71230  *
71231  * Enum | Value | Description
71232  * :----------------------------------------------|:------|:------------------------------------
71233  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71234  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71235  *
71236  * Field Access Macros:
71237  *
71238  */
71239 /*
71240  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4
71241  *
71242  * Byte is unmasked (i.e. is compared)
71243  */
71244 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED 0x0
71245 /*
71246  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4
71247  *
71248  * Byte is masked (i.e. not compared)
71249  */
71250 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED 0x1
71251 
71252 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
71253 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_LSB 28
71254 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
71255 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_MSB 28
71256 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
71257 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_WIDTH 1
71258 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */
71259 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET_MSK 0x10000000
71260 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */
71261 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_CLR_MSK 0xefffffff
71262 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
71263 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_RESET 0x0
71264 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 field value from a register. */
71265 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
71266 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value suitable for setting the register. */
71267 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
71268 
71269 /*
71270  * Field : Mask Byte Control - mbc_5
71271  *
71272  * This array of bits are mask control bits for comparison of each of the MAC
71273  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71274  * received DA or SA with the contents of MAC Address82 high and low registers.
71275  * Each bit controls the masking of the bytes. You can filter a group of addresses
71276  * (known as group address filtering) by masking one or more bytes of the address.
71277  *
71278  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71279  *
71280  * Field Enumeration Values:
71281  *
71282  * Enum | Value | Description
71283  * :----------------------------------------------|:------|:------------------------------------
71284  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71285  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71286  *
71287  * Field Access Macros:
71288  *
71289  */
71290 /*
71291  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5
71292  *
71293  * Byte is unmasked (i.e. is compared)
71294  */
71295 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED 0x0
71296 /*
71297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5
71298  *
71299  * Byte is masked (i.e. not compared)
71300  */
71301 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED 0x1
71302 
71303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
71304 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_LSB 29
71305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
71306 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_MSB 29
71307 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
71308 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_WIDTH 1
71309 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */
71310 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET_MSK 0x20000000
71311 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */
71312 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_CLR_MSK 0xdfffffff
71313 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
71314 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_RESET 0x0
71315 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 field value from a register. */
71316 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
71317 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value suitable for setting the register. */
71318 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
71319 
71320 /*
71321  * Field : Source Address - sa
71322  *
71323  * When this bit is enabled, the MAC Address82[47:0] is used to compare with the SA
71324  * fields of the received frame. When this bit is disabled, the MAC Address82[47:0]
71325  * is used to compare with the DA fields of the received frame.
71326  *
71327  * Field Enumeration Values:
71328  *
71329  * Enum | Value | Description
71330  * :----------------------------------------|:------|:-----------------------------
71331  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
71332  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END | 0x1 | MAC address compare enabled
71333  *
71334  * Field Access Macros:
71335  *
71336  */
71337 /*
71338  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA
71339  *
71340  * MAC address compare disabled
71341  */
71342 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD 0x0
71343 /*
71344  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA
71345  *
71346  * MAC address compare enabled
71347  */
71348 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END 0x1
71349 
71350 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
71351 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_LSB 30
71352 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
71353 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_MSB 30
71354 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
71355 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_WIDTH 1
71356 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */
71357 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET_MSK 0x40000000
71358 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */
71359 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_CLR_MSK 0xbfffffff
71360 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
71361 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_RESET 0x0
71362 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA field value from a register. */
71363 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
71364 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value suitable for setting the register. */
71365 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
71366 
71367 /*
71368  * Field : Address Enable - ae
71369  *
71370  * When this bit is enabled, the address filter block uses the 83th MAC address for
71371  * perfect filtering. When this bit is disabled, the address filter block ignores
71372  * the address for filtering.
71373  *
71374  * Field Enumeration Values:
71375  *
71376  * Enum | Value | Description
71377  * :----------------------------------------|:------|:--------------------------------------
71378  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
71379  * ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
71380  *
71381  * Field Access Macros:
71382  *
71383  */
71384 /*
71385  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
71386  *
71387  * Second MAC address filtering disabled
71388  */
71389 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD 0x0
71390 /*
71391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
71392  *
71393  * Second MAC address filtering enabled
71394  */
71395 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END 0x1
71396 
71397 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
71398 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_LSB 31
71399 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
71400 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_MSB 31
71401 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
71402 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_WIDTH 1
71403 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
71404 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET_MSK 0x80000000
71405 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
71406 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_CLR_MSK 0x7fffffff
71407 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
71408 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_RESET 0x0
71409 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE field value from a register. */
71410 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
71411 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value suitable for setting the register. */
71412 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
71413 
71414 #ifndef __ASSEMBLY__
71415 /*
71416  * WARNING: The C register and register group struct declarations are provided for
71417  * convenience and illustrative purposes. They should, however, be used with
71418  * caution as the C language standard provides no guarantees about the alignment or
71419  * atomicity of device memory accesses. The recommended practice for writing
71420  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71421  * alt_write_word() functions.
71422  *
71423  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH.
71424  */
71425 struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s
71426 {
71427  uint32_t addrhi : 16; /* MAC Address82 [47:32] */
71428  uint32_t : 8; /* *UNDEFINED* */
71429  uint32_t mbc_0 : 1; /* Mask Byte Control */
71430  uint32_t mbc_1 : 1; /* Mask Byte Control */
71431  uint32_t mbc_2 : 1; /* Mask Byte Control */
71432  uint32_t mbc_3 : 1; /* Mask Byte Control */
71433  uint32_t mbc_4 : 1; /* Mask Byte Control */
71434  uint32_t mbc_5 : 1; /* Mask Byte Control */
71435  uint32_t sa : 1; /* Source Address */
71436  uint32_t ae : 1; /* Address Enable */
71437 };
71438 
71439 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH. */
71440 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t;
71441 #endif /* __ASSEMBLY__ */
71442 
71443 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register from the beginning of the component. */
71444 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST 0xa10
71445 /* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register. */
71446 #define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST))
71447 
71448 /*
71449  * Register : Register 645 (MAC Address82 Low Register) - MAC_Address82_Low
71450  *
71451  * The MAC Address82 Low register holds the lower 32 bits of the 83th 6-byte MAC
71452  * address of the station.
71453  *
71454  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
71455  * format.
71456  *
71457  * Register Layout
71458  *
71459  * Bits | Access | Reset | Description
71460  * :-------|:-------|:-----------|:---------------------
71461  * [31:0] | RW | 0xffffffff | MAC Address82 [31:0]
71462  *
71463  */
71464 /*
71465  * Field : MAC Address82 [31:0] - addrlo
71466  *
71467  * This field contains the lower 32 bits of the 83th 6-byte MAC address. The
71468  * content of this field is undefined until loaded by software after the
71469  * initialization process.
71470  *
71471  * Field Access Macros:
71472  *
71473  */
71474 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
71475 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_LSB 0
71476 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
71477 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_MSB 31
71478 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
71479 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_WIDTH 32
71480 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
71481 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET_MSK 0xffffffff
71482 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
71483 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_CLR_MSK 0x00000000
71484 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
71485 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_RESET 0xffffffff
71486 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO field value from a register. */
71487 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
71488 /* Produces a ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value suitable for setting the register. */
71489 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
71490 
71491 #ifndef __ASSEMBLY__
71492 /*
71493  * WARNING: The C register and register group struct declarations are provided for
71494  * convenience and illustrative purposes. They should, however, be used with
71495  * caution as the C language standard provides no guarantees about the alignment or
71496  * atomicity of device memory accesses. The recommended practice for writing
71497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71498  * alt_write_word() functions.
71499  *
71500  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW.
71501  */
71502 struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s
71503 {
71504  uint32_t addrlo : 32; /* MAC Address82 [31:0] */
71505 };
71506 
71507 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW. */
71508 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s ALT_EMAC_GMAC_MAC_ADDR82_LOW_t;
71509 #endif /* __ASSEMBLY__ */
71510 
71511 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register from the beginning of the component. */
71512 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST 0xa14
71513 /* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register. */
71514 #define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST))
71515 
71516 /*
71517  * Register : Register 646 (MAC Address83 High Register) - MAC_Address83_High
71518  *
71519  * The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC
71520  * address of the station. Because the MAC address registers are configured to be
71521  * double-synchronized to the (G)MII clock domains, the synchronization is
71522  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
71523  * endian mode) of the MAC Address83 Low Register are written. For proper
71524  * synchronization updates, the consecutive writes to this Address Low Register
71525  * should be performed after at least four clock cycles in the destination clock
71526  * domain.
71527  *
71528  * Note that all MAC Address High registers (except MAC Address0 High) have the
71529  * same format.
71530  *
71531  * Register Layout
71532  *
71533  * Bits | Access | Reset | Description
71534  * :--------|:-------|:-------|:----------------------
71535  * [15:0] | RW | 0xffff | MAC Address83 [47:32]
71536  * [23:16] | ??? | 0x0 | *UNDEFINED*
71537  * [24] | RW | 0x0 | Mask Byte Control
71538  * [25] | RW | 0x0 | Mask Byte Control
71539  * [26] | RW | 0x0 | Mask Byte Control
71540  * [27] | RW | 0x0 | Mask Byte Control
71541  * [28] | RW | 0x0 | Mask Byte Control
71542  * [29] | RW | 0x0 | Mask Byte Control
71543  * [30] | RW | 0x0 | Source Address
71544  * [31] | RW | 0x0 | Address Enable
71545  *
71546  */
71547 /*
71548  * Field : MAC Address83 [47:32] - addrhi
71549  *
71550  * This field contains the upper 16 bits (47:32) of the 84th 6-byte MAC address.
71551  *
71552  * Field Access Macros:
71553  *
71554  */
71555 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
71556 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_LSB 0
71557 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
71558 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_MSB 15
71559 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
71560 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_WIDTH 16
71561 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
71562 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET_MSK 0x0000ffff
71563 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
71564 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_CLR_MSK 0xffff0000
71565 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
71566 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_RESET 0xffff
71567 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI field value from a register. */
71568 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
71569 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value suitable for setting the register. */
71570 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
71571 
71572 /*
71573  * Field : Mask Byte Control - mbc_0
71574  *
71575  * This array of bits are mask control bits for comparison of each of the MAC
71576  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71577  * received DA or SA with the contents of MAC Address83 high and low registers.
71578  * Each bit controls the masking of the bytes. You can filter a group of addresses
71579  * (known as group address filtering) by masking one or more bytes of the address.
71580  *
71581  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71582  *
71583  * Field Enumeration Values:
71584  *
71585  * Enum | Value | Description
71586  * :----------------------------------------------|:------|:------------------------------------
71587  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71588  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71589  *
71590  * Field Access Macros:
71591  *
71592  */
71593 /*
71594  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0
71595  *
71596  * Byte is unmasked (i.e. is compared)
71597  */
71598 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED 0x0
71599 /*
71600  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0
71601  *
71602  * Byte is masked (i.e. not compared)
71603  */
71604 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED 0x1
71605 
71606 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
71607 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_LSB 24
71608 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
71609 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_MSB 24
71610 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
71611 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_WIDTH 1
71612 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */
71613 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET_MSK 0x01000000
71614 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */
71615 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_CLR_MSK 0xfeffffff
71616 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
71617 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_RESET 0x0
71618 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 field value from a register. */
71619 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
71620 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value suitable for setting the register. */
71621 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
71622 
71623 /*
71624  * Field : Mask Byte Control - mbc_1
71625  *
71626  * This array of bits are mask control bits for comparison of each of the MAC
71627  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71628  * received DA or SA with the contents of MAC Address83 high and low registers.
71629  * Each bit controls the masking of the bytes. You can filter a group of addresses
71630  * (known as group address filtering) by masking one or more bytes of the address.
71631  *
71632  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71633  *
71634  * Field Enumeration Values:
71635  *
71636  * Enum | Value | Description
71637  * :----------------------------------------------|:------|:------------------------------------
71638  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71639  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71640  *
71641  * Field Access Macros:
71642  *
71643  */
71644 /*
71645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1
71646  *
71647  * Byte is unmasked (i.e. is compared)
71648  */
71649 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED 0x0
71650 /*
71651  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1
71652  *
71653  * Byte is masked (i.e. not compared)
71654  */
71655 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED 0x1
71656 
71657 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
71658 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_LSB 25
71659 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
71660 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_MSB 25
71661 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
71662 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_WIDTH 1
71663 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */
71664 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET_MSK 0x02000000
71665 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */
71666 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_CLR_MSK 0xfdffffff
71667 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
71668 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_RESET 0x0
71669 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 field value from a register. */
71670 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
71671 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value suitable for setting the register. */
71672 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
71673 
71674 /*
71675  * Field : Mask Byte Control - mbc_2
71676  *
71677  * This array of bits are mask control bits for comparison of each of the MAC
71678  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71679  * received DA or SA with the contents of MAC Address83 high and low registers.
71680  * Each bit controls the masking of the bytes. You can filter a group of addresses
71681  * (known as group address filtering) by masking one or more bytes of the address.
71682  *
71683  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71684  *
71685  * Field Enumeration Values:
71686  *
71687  * Enum | Value | Description
71688  * :----------------------------------------------|:------|:------------------------------------
71689  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71690  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71691  *
71692  * Field Access Macros:
71693  *
71694  */
71695 /*
71696  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2
71697  *
71698  * Byte is unmasked (i.e. is compared)
71699  */
71700 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED 0x0
71701 /*
71702  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2
71703  *
71704  * Byte is masked (i.e. not compared)
71705  */
71706 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED 0x1
71707 
71708 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
71709 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_LSB 26
71710 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
71711 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_MSB 26
71712 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
71713 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_WIDTH 1
71714 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */
71715 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET_MSK 0x04000000
71716 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */
71717 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_CLR_MSK 0xfbffffff
71718 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
71719 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_RESET 0x0
71720 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 field value from a register. */
71721 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
71722 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value suitable for setting the register. */
71723 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
71724 
71725 /*
71726  * Field : Mask Byte Control - mbc_3
71727  *
71728  * This array of bits are mask control bits for comparison of each of the MAC
71729  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71730  * received DA or SA with the contents of MAC Address83 high and low registers.
71731  * Each bit controls the masking of the bytes. You can filter a group of addresses
71732  * (known as group address filtering) by masking one or more bytes of the address.
71733  *
71734  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71735  *
71736  * Field Enumeration Values:
71737  *
71738  * Enum | Value | Description
71739  * :----------------------------------------------|:------|:------------------------------------
71740  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71741  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71742  *
71743  * Field Access Macros:
71744  *
71745  */
71746 /*
71747  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3
71748  *
71749  * Byte is unmasked (i.e. is compared)
71750  */
71751 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED 0x0
71752 /*
71753  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3
71754  *
71755  * Byte is masked (i.e. not compared)
71756  */
71757 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED 0x1
71758 
71759 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
71760 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_LSB 27
71761 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
71762 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_MSB 27
71763 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
71764 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_WIDTH 1
71765 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */
71766 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET_MSK 0x08000000
71767 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */
71768 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_CLR_MSK 0xf7ffffff
71769 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
71770 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_RESET 0x0
71771 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 field value from a register. */
71772 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
71773 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value suitable for setting the register. */
71774 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
71775 
71776 /*
71777  * Field : Mask Byte Control - mbc_4
71778  *
71779  * This array of bits are mask control bits for comparison of each of the MAC
71780  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71781  * received DA or SA with the contents of MAC Address83 high and low registers.
71782  * Each bit controls the masking of the bytes. You can filter a group of addresses
71783  * (known as group address filtering) by masking one or more bytes of the address.
71784  *
71785  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71786  *
71787  * Field Enumeration Values:
71788  *
71789  * Enum | Value | Description
71790  * :----------------------------------------------|:------|:------------------------------------
71791  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71792  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71793  *
71794  * Field Access Macros:
71795  *
71796  */
71797 /*
71798  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4
71799  *
71800  * Byte is unmasked (i.e. is compared)
71801  */
71802 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED 0x0
71803 /*
71804  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4
71805  *
71806  * Byte is masked (i.e. not compared)
71807  */
71808 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED 0x1
71809 
71810 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
71811 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_LSB 28
71812 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
71813 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_MSB 28
71814 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
71815 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_WIDTH 1
71816 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */
71817 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET_MSK 0x10000000
71818 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */
71819 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_CLR_MSK 0xefffffff
71820 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
71821 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_RESET 0x0
71822 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 field value from a register. */
71823 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
71824 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value suitable for setting the register. */
71825 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
71826 
71827 /*
71828  * Field : Mask Byte Control - mbc_5
71829  *
71830  * This array of bits are mask control bits for comparison of each of the MAC
71831  * Address bytes. When masked, the MAC does not compare the corresponding byte of
71832  * received DA or SA with the contents of MAC Address83 high and low registers.
71833  * Each bit controls the masking of the bytes. You can filter a group of addresses
71834  * (known as group address filtering) by masking one or more bytes of the address.
71835  *
71836  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
71837  *
71838  * Field Enumeration Values:
71839  *
71840  * Enum | Value | Description
71841  * :----------------------------------------------|:------|:------------------------------------
71842  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
71843  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
71844  *
71845  * Field Access Macros:
71846  *
71847  */
71848 /*
71849  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5
71850  *
71851  * Byte is unmasked (i.e. is compared)
71852  */
71853 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED 0x0
71854 /*
71855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5
71856  *
71857  * Byte is masked (i.e. not compared)
71858  */
71859 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED 0x1
71860 
71861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
71862 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_LSB 29
71863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
71864 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_MSB 29
71865 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
71866 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_WIDTH 1
71867 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */
71868 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET_MSK 0x20000000
71869 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */
71870 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_CLR_MSK 0xdfffffff
71871 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
71872 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_RESET 0x0
71873 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 field value from a register. */
71874 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
71875 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value suitable for setting the register. */
71876 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
71877 
71878 /*
71879  * Field : Source Address - sa
71880  *
71881  * When this bit is enabled, the MAC Address83[47:0] is used to compare with the SA
71882  * fields of the received frame. When this bit is disabled, the MAC Address83[47:0]
71883  * is used to compare with the DA fields of the received frame.
71884  *
71885  * Field Enumeration Values:
71886  *
71887  * Enum | Value | Description
71888  * :----------------------------------------|:------|:-----------------------------
71889  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
71890  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END | 0x1 | MAC address compare enabled
71891  *
71892  * Field Access Macros:
71893  *
71894  */
71895 /*
71896  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA
71897  *
71898  * MAC address compare disabled
71899  */
71900 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD 0x0
71901 /*
71902  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA
71903  *
71904  * MAC address compare enabled
71905  */
71906 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END 0x1
71907 
71908 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
71909 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_LSB 30
71910 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
71911 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_MSB 30
71912 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
71913 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_WIDTH 1
71914 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */
71915 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET_MSK 0x40000000
71916 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */
71917 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_CLR_MSK 0xbfffffff
71918 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
71919 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_RESET 0x0
71920 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA field value from a register. */
71921 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
71922 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value suitable for setting the register. */
71923 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
71924 
71925 /*
71926  * Field : Address Enable - ae
71927  *
71928  * When this bit is enabled, the address filter block uses the 84th MAC address for
71929  * perfect filtering. When this bit is disabled, the address filter block ignores
71930  * the address for filtering.
71931  *
71932  * Field Enumeration Values:
71933  *
71934  * Enum | Value | Description
71935  * :----------------------------------------|:------|:--------------------------------------
71936  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
71937  * ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
71938  *
71939  * Field Access Macros:
71940  *
71941  */
71942 /*
71943  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
71944  *
71945  * Second MAC address filtering disabled
71946  */
71947 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD 0x0
71948 /*
71949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
71950  *
71951  * Second MAC address filtering enabled
71952  */
71953 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END 0x1
71954 
71955 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
71956 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_LSB 31
71957 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
71958 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_MSB 31
71959 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
71960 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_WIDTH 1
71961 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
71962 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET_MSK 0x80000000
71963 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
71964 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_CLR_MSK 0x7fffffff
71965 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
71966 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_RESET 0x0
71967 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE field value from a register. */
71968 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
71969 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value suitable for setting the register. */
71970 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
71971 
71972 #ifndef __ASSEMBLY__
71973 /*
71974  * WARNING: The C register and register group struct declarations are provided for
71975  * convenience and illustrative purposes. They should, however, be used with
71976  * caution as the C language standard provides no guarantees about the alignment or
71977  * atomicity of device memory accesses. The recommended practice for writing
71978  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
71979  * alt_write_word() functions.
71980  *
71981  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH.
71982  */
71983 struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s
71984 {
71985  uint32_t addrhi : 16; /* MAC Address83 [47:32] */
71986  uint32_t : 8; /* *UNDEFINED* */
71987  uint32_t mbc_0 : 1; /* Mask Byte Control */
71988  uint32_t mbc_1 : 1; /* Mask Byte Control */
71989  uint32_t mbc_2 : 1; /* Mask Byte Control */
71990  uint32_t mbc_3 : 1; /* Mask Byte Control */
71991  uint32_t mbc_4 : 1; /* Mask Byte Control */
71992  uint32_t mbc_5 : 1; /* Mask Byte Control */
71993  uint32_t sa : 1; /* Source Address */
71994  uint32_t ae : 1; /* Address Enable */
71995 };
71996 
71997 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH. */
71998 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t;
71999 #endif /* __ASSEMBLY__ */
72000 
72001 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register from the beginning of the component. */
72002 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST 0xa18
72003 /* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register. */
72004 #define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST))
72005 
72006 /*
72007  * Register : Register 647 (MAC Address83 Low Register) - MAC_Address83_Low
72008  *
72009  * The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC
72010  * address of the station.
72011  *
72012  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
72013  * format.
72014  *
72015  * Register Layout
72016  *
72017  * Bits | Access | Reset | Description
72018  * :-------|:-------|:-----------|:---------------------
72019  * [31:0] | RW | 0xffffffff | MAC Address83 [31:0]
72020  *
72021  */
72022 /*
72023  * Field : MAC Address83 [31:0] - addrlo
72024  *
72025  * This field contains the lower 32 bits of the 84th 6-byte MAC address. The
72026  * content of this field is undefined until loaded by software after the
72027  * initialization process.
72028  *
72029  * Field Access Macros:
72030  *
72031  */
72032 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
72033 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_LSB 0
72034 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
72035 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_MSB 31
72036 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
72037 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_WIDTH 32
72038 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
72039 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET_MSK 0xffffffff
72040 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
72041 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_CLR_MSK 0x00000000
72042 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
72043 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_RESET 0xffffffff
72044 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO field value from a register. */
72045 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
72046 /* Produces a ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value suitable for setting the register. */
72047 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
72048 
72049 #ifndef __ASSEMBLY__
72050 /*
72051  * WARNING: The C register and register group struct declarations are provided for
72052  * convenience and illustrative purposes. They should, however, be used with
72053  * caution as the C language standard provides no guarantees about the alignment or
72054  * atomicity of device memory accesses. The recommended practice for writing
72055  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72056  * alt_write_word() functions.
72057  *
72058  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW.
72059  */
72060 struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s
72061 {
72062  uint32_t addrlo : 32; /* MAC Address83 [31:0] */
72063 };
72064 
72065 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW. */
72066 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s ALT_EMAC_GMAC_MAC_ADDR83_LOW_t;
72067 #endif /* __ASSEMBLY__ */
72068 
72069 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register from the beginning of the component. */
72070 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST 0xa1c
72071 /* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register. */
72072 #define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST))
72073 
72074 /*
72075  * Register : Register 648 (MAC Address84 High Register) - MAC_Address84_High
72076  *
72077  * The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC
72078  * address of the station. Because the MAC address registers are configured to be
72079  * double-synchronized to the (G)MII clock domains, the synchronization is
72080  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
72081  * endian mode) of the MAC Address84 Low Register are written. For proper
72082  * synchronization updates, the consecutive writes to this Address Low Register
72083  * should be performed after at least four clock cycles in the destination clock
72084  * domain.
72085  *
72086  * Note that all MAC Address High registers (except MAC Address0 High) have the
72087  * same format.
72088  *
72089  * Register Layout
72090  *
72091  * Bits | Access | Reset | Description
72092  * :--------|:-------|:-------|:----------------------
72093  * [15:0] | RW | 0xffff | MAC Address84 [47:32]
72094  * [23:16] | ??? | 0x0 | *UNDEFINED*
72095  * [24] | RW | 0x0 | Mask Byte Control
72096  * [25] | RW | 0x0 | Mask Byte Control
72097  * [26] | RW | 0x0 | Mask Byte Control
72098  * [27] | RW | 0x0 | Mask Byte Control
72099  * [28] | RW | 0x0 | Mask Byte Control
72100  * [29] | RW | 0x0 | Mask Byte Control
72101  * [30] | RW | 0x0 | Source Address
72102  * [31] | RW | 0x0 | Address Enable
72103  *
72104  */
72105 /*
72106  * Field : MAC Address84 [47:32] - addrhi
72107  *
72108  * This field contains the upper 16 bits (47:32) of the 85th 6-byte MAC address.
72109  *
72110  * Field Access Macros:
72111  *
72112  */
72113 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
72114 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_LSB 0
72115 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
72116 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_MSB 15
72117 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
72118 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_WIDTH 16
72119 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
72120 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET_MSK 0x0000ffff
72121 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
72122 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_CLR_MSK 0xffff0000
72123 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
72124 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_RESET 0xffff
72125 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI field value from a register. */
72126 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
72127 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value suitable for setting the register. */
72128 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
72129 
72130 /*
72131  * Field : Mask Byte Control - mbc_0
72132  *
72133  * This array of bits are mask control bits for comparison of each of the MAC
72134  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72135  * received DA or SA with the contents of MAC Address84 high and low registers.
72136  * Each bit controls the masking of the bytes. You can filter a group of addresses
72137  * (known as group address filtering) by masking one or more bytes of the address.
72138  *
72139  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72140  *
72141  * Field Enumeration Values:
72142  *
72143  * Enum | Value | Description
72144  * :----------------------------------------------|:------|:------------------------------------
72145  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72146  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72147  *
72148  * Field Access Macros:
72149  *
72150  */
72151 /*
72152  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0
72153  *
72154  * Byte is unmasked (i.e. is compared)
72155  */
72156 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED 0x0
72157 /*
72158  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0
72159  *
72160  * Byte is masked (i.e. not compared)
72161  */
72162 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED 0x1
72163 
72164 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
72165 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_LSB 24
72166 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
72167 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_MSB 24
72168 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
72169 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_WIDTH 1
72170 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */
72171 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET_MSK 0x01000000
72172 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */
72173 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_CLR_MSK 0xfeffffff
72174 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
72175 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_RESET 0x0
72176 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 field value from a register. */
72177 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
72178 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value suitable for setting the register. */
72179 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
72180 
72181 /*
72182  * Field : Mask Byte Control - mbc_1
72183  *
72184  * This array of bits are mask control bits for comparison of each of the MAC
72185  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72186  * received DA or SA with the contents of MAC Address84 high and low registers.
72187  * Each bit controls the masking of the bytes. You can filter a group of addresses
72188  * (known as group address filtering) by masking one or more bytes of the address.
72189  *
72190  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72191  *
72192  * Field Enumeration Values:
72193  *
72194  * Enum | Value | Description
72195  * :----------------------------------------------|:------|:------------------------------------
72196  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72197  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72198  *
72199  * Field Access Macros:
72200  *
72201  */
72202 /*
72203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1
72204  *
72205  * Byte is unmasked (i.e. is compared)
72206  */
72207 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED 0x0
72208 /*
72209  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1
72210  *
72211  * Byte is masked (i.e. not compared)
72212  */
72213 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED 0x1
72214 
72215 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
72216 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_LSB 25
72217 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
72218 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_MSB 25
72219 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
72220 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_WIDTH 1
72221 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */
72222 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET_MSK 0x02000000
72223 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */
72224 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_CLR_MSK 0xfdffffff
72225 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
72226 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_RESET 0x0
72227 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 field value from a register. */
72228 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
72229 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value suitable for setting the register. */
72230 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
72231 
72232 /*
72233  * Field : Mask Byte Control - mbc_2
72234  *
72235  * This array of bits are mask control bits for comparison of each of the MAC
72236  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72237  * received DA or SA with the contents of MAC Address84 high and low registers.
72238  * Each bit controls the masking of the bytes. You can filter a group of addresses
72239  * (known as group address filtering) by masking one or more bytes of the address.
72240  *
72241  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72242  *
72243  * Field Enumeration Values:
72244  *
72245  * Enum | Value | Description
72246  * :----------------------------------------------|:------|:------------------------------------
72247  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72248  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72249  *
72250  * Field Access Macros:
72251  *
72252  */
72253 /*
72254  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2
72255  *
72256  * Byte is unmasked (i.e. is compared)
72257  */
72258 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED 0x0
72259 /*
72260  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2
72261  *
72262  * Byte is masked (i.e. not compared)
72263  */
72264 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED 0x1
72265 
72266 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
72267 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_LSB 26
72268 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
72269 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_MSB 26
72270 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
72271 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_WIDTH 1
72272 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */
72273 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET_MSK 0x04000000
72274 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */
72275 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_CLR_MSK 0xfbffffff
72276 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
72277 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_RESET 0x0
72278 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 field value from a register. */
72279 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
72280 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value suitable for setting the register. */
72281 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
72282 
72283 /*
72284  * Field : Mask Byte Control - mbc_3
72285  *
72286  * This array of bits are mask control bits for comparison of each of the MAC
72287  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72288  * received DA or SA with the contents of MAC Address84 high and low registers.
72289  * Each bit controls the masking of the bytes. You can filter a group of addresses
72290  * (known as group address filtering) by masking one or more bytes of the address.
72291  *
72292  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72293  *
72294  * Field Enumeration Values:
72295  *
72296  * Enum | Value | Description
72297  * :----------------------------------------------|:------|:------------------------------------
72298  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72299  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72300  *
72301  * Field Access Macros:
72302  *
72303  */
72304 /*
72305  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3
72306  *
72307  * Byte is unmasked (i.e. is compared)
72308  */
72309 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED 0x0
72310 /*
72311  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3
72312  *
72313  * Byte is masked (i.e. not compared)
72314  */
72315 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED 0x1
72316 
72317 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
72318 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_LSB 27
72319 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
72320 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_MSB 27
72321 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
72322 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_WIDTH 1
72323 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */
72324 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET_MSK 0x08000000
72325 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */
72326 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_CLR_MSK 0xf7ffffff
72327 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
72328 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_RESET 0x0
72329 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 field value from a register. */
72330 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
72331 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value suitable for setting the register. */
72332 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
72333 
72334 /*
72335  * Field : Mask Byte Control - mbc_4
72336  *
72337  * This array of bits are mask control bits for comparison of each of the MAC
72338  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72339  * received DA or SA with the contents of MAC Address84 high and low registers.
72340  * Each bit controls the masking of the bytes. You can filter a group of addresses
72341  * (known as group address filtering) by masking one or more bytes of the address.
72342  *
72343  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72344  *
72345  * Field Enumeration Values:
72346  *
72347  * Enum | Value | Description
72348  * :----------------------------------------------|:------|:------------------------------------
72349  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72350  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72351  *
72352  * Field Access Macros:
72353  *
72354  */
72355 /*
72356  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4
72357  *
72358  * Byte is unmasked (i.e. is compared)
72359  */
72360 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED 0x0
72361 /*
72362  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4
72363  *
72364  * Byte is masked (i.e. not compared)
72365  */
72366 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED 0x1
72367 
72368 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
72369 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_LSB 28
72370 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
72371 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_MSB 28
72372 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
72373 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_WIDTH 1
72374 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */
72375 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET_MSK 0x10000000
72376 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */
72377 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_CLR_MSK 0xefffffff
72378 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
72379 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_RESET 0x0
72380 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 field value from a register. */
72381 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
72382 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value suitable for setting the register. */
72383 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
72384 
72385 /*
72386  * Field : Mask Byte Control - mbc_5
72387  *
72388  * This array of bits are mask control bits for comparison of each of the MAC
72389  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72390  * received DA or SA with the contents of MAC Address84 high and low registers.
72391  * Each bit controls the masking of the bytes. You can filter a group of addresses
72392  * (known as group address filtering) by masking one or more bytes of the address.
72393  *
72394  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72395  *
72396  * Field Enumeration Values:
72397  *
72398  * Enum | Value | Description
72399  * :----------------------------------------------|:------|:------------------------------------
72400  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72401  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72402  *
72403  * Field Access Macros:
72404  *
72405  */
72406 /*
72407  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5
72408  *
72409  * Byte is unmasked (i.e. is compared)
72410  */
72411 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED 0x0
72412 /*
72413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5
72414  *
72415  * Byte is masked (i.e. not compared)
72416  */
72417 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED 0x1
72418 
72419 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
72420 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_LSB 29
72421 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
72422 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_MSB 29
72423 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
72424 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_WIDTH 1
72425 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */
72426 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET_MSK 0x20000000
72427 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */
72428 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_CLR_MSK 0xdfffffff
72429 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
72430 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_RESET 0x0
72431 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 field value from a register. */
72432 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
72433 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value suitable for setting the register. */
72434 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
72435 
72436 /*
72437  * Field : Source Address - sa
72438  *
72439  * When this bit is enabled, the MAC Address84[47:0] is used to compare with the SA
72440  * fields of the received frame. When this bit is disabled, the MAC Address84[47:0]
72441  * is used to compare with the DA fields of the received frame.
72442  *
72443  * Field Enumeration Values:
72444  *
72445  * Enum | Value | Description
72446  * :----------------------------------------|:------|:-----------------------------
72447  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
72448  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END | 0x1 | MAC address compare enabled
72449  *
72450  * Field Access Macros:
72451  *
72452  */
72453 /*
72454  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA
72455  *
72456  * MAC address compare disabled
72457  */
72458 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD 0x0
72459 /*
72460  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA
72461  *
72462  * MAC address compare enabled
72463  */
72464 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END 0x1
72465 
72466 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
72467 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_LSB 30
72468 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
72469 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_MSB 30
72470 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
72471 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_WIDTH 1
72472 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */
72473 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET_MSK 0x40000000
72474 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */
72475 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_CLR_MSK 0xbfffffff
72476 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
72477 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_RESET 0x0
72478 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA field value from a register. */
72479 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
72480 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value suitable for setting the register. */
72481 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
72482 
72483 /*
72484  * Field : Address Enable - ae
72485  *
72486  * When this bit is enabled, the address filter block uses the 85th MAC address for
72487  * perfect filtering. When this bit is disabled, the address filter block ignores
72488  * the address for filtering.
72489  *
72490  * Field Enumeration Values:
72491  *
72492  * Enum | Value | Description
72493  * :----------------------------------------|:------|:--------------------------------------
72494  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
72495  * ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
72496  *
72497  * Field Access Macros:
72498  *
72499  */
72500 /*
72501  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
72502  *
72503  * Second MAC address filtering disabled
72504  */
72505 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD 0x0
72506 /*
72507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
72508  *
72509  * Second MAC address filtering enabled
72510  */
72511 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END 0x1
72512 
72513 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
72514 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_LSB 31
72515 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
72516 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_MSB 31
72517 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
72518 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_WIDTH 1
72519 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
72520 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET_MSK 0x80000000
72521 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
72522 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_CLR_MSK 0x7fffffff
72523 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
72524 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_RESET 0x0
72525 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE field value from a register. */
72526 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
72527 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value suitable for setting the register. */
72528 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
72529 
72530 #ifndef __ASSEMBLY__
72531 /*
72532  * WARNING: The C register and register group struct declarations are provided for
72533  * convenience and illustrative purposes. They should, however, be used with
72534  * caution as the C language standard provides no guarantees about the alignment or
72535  * atomicity of device memory accesses. The recommended practice for writing
72536  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72537  * alt_write_word() functions.
72538  *
72539  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH.
72540  */
72541 struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s
72542 {
72543  uint32_t addrhi : 16; /* MAC Address84 [47:32] */
72544  uint32_t : 8; /* *UNDEFINED* */
72545  uint32_t mbc_0 : 1; /* Mask Byte Control */
72546  uint32_t mbc_1 : 1; /* Mask Byte Control */
72547  uint32_t mbc_2 : 1; /* Mask Byte Control */
72548  uint32_t mbc_3 : 1; /* Mask Byte Control */
72549  uint32_t mbc_4 : 1; /* Mask Byte Control */
72550  uint32_t mbc_5 : 1; /* Mask Byte Control */
72551  uint32_t sa : 1; /* Source Address */
72552  uint32_t ae : 1; /* Address Enable */
72553 };
72554 
72555 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH. */
72556 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t;
72557 #endif /* __ASSEMBLY__ */
72558 
72559 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register from the beginning of the component. */
72560 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST 0xa20
72561 /* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register. */
72562 #define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST))
72563 
72564 /*
72565  * Register : Register 649 (MAC Address84 Low Register) - MAC_Address84_Low
72566  *
72567  * The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC
72568  * address of the station.
72569  *
72570  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
72571  * format.
72572  *
72573  * Register Layout
72574  *
72575  * Bits | Access | Reset | Description
72576  * :-------|:-------|:-----------|:---------------------
72577  * [31:0] | RW | 0xffffffff | MAC Address84 [31:0]
72578  *
72579  */
72580 /*
72581  * Field : MAC Address84 [31:0] - addrlo
72582  *
72583  * This field contains the lower 32 bits of the 85th 6-byte MAC address. The
72584  * content of this field is undefined until loaded by software after the
72585  * initialization process.
72586  *
72587  * Field Access Macros:
72588  *
72589  */
72590 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
72591 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_LSB 0
72592 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
72593 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_MSB 31
72594 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
72595 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_WIDTH 32
72596 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
72597 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET_MSK 0xffffffff
72598 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
72599 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_CLR_MSK 0x00000000
72600 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
72601 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_RESET 0xffffffff
72602 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO field value from a register. */
72603 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
72604 /* Produces a ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value suitable for setting the register. */
72605 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
72606 
72607 #ifndef __ASSEMBLY__
72608 /*
72609  * WARNING: The C register and register group struct declarations are provided for
72610  * convenience and illustrative purposes. They should, however, be used with
72611  * caution as the C language standard provides no guarantees about the alignment or
72612  * atomicity of device memory accesses. The recommended practice for writing
72613  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
72614  * alt_write_word() functions.
72615  *
72616  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW.
72617  */
72618 struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s
72619 {
72620  uint32_t addrlo : 32; /* MAC Address84 [31:0] */
72621 };
72622 
72623 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW. */
72624 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s ALT_EMAC_GMAC_MAC_ADDR84_LOW_t;
72625 #endif /* __ASSEMBLY__ */
72626 
72627 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register from the beginning of the component. */
72628 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST 0xa24
72629 /* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register. */
72630 #define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST))
72631 
72632 /*
72633  * Register : Register 650 (MAC Address85 High Register) - MAC_Address85_High
72634  *
72635  * The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC
72636  * address of the station. Because the MAC address registers are configured to be
72637  * double-synchronized to the (G)MII clock domains, the synchronization is
72638  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
72639  * endian mode) of the MAC Address85 Low Register are written. For proper
72640  * synchronization updates, the consecutive writes to this Address Low Register
72641  * should be performed after at least four clock cycles in the destination clock
72642  * domain.
72643  *
72644  * Note that all MAC Address High registers (except MAC Address0 High) have the
72645  * same format.
72646  *
72647  * Register Layout
72648  *
72649  * Bits | Access | Reset | Description
72650  * :--------|:-------|:-------|:----------------------
72651  * [15:0] | RW | 0xffff | MAC Address85 [47:32]
72652  * [23:16] | ??? | 0x0 | *UNDEFINED*
72653  * [24] | RW | 0x0 | Mask Byte Control
72654  * [25] | RW | 0x0 | Mask Byte Control
72655  * [26] | RW | 0x0 | Mask Byte Control
72656  * [27] | RW | 0x0 | Mask Byte Control
72657  * [28] | RW | 0x0 | Mask Byte Control
72658  * [29] | RW | 0x0 | Mask Byte Control
72659  * [30] | RW | 0x0 | Source Address
72660  * [31] | RW | 0x0 | Address Enable
72661  *
72662  */
72663 /*
72664  * Field : MAC Address85 [47:32] - addrhi
72665  *
72666  * This field contains the upper 16 bits (47:32) of the 86th 6-byte MAC address.
72667  *
72668  * Field Access Macros:
72669  *
72670  */
72671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
72672 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_LSB 0
72673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
72674 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_MSB 15
72675 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
72676 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_WIDTH 16
72677 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
72678 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET_MSK 0x0000ffff
72679 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
72680 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_CLR_MSK 0xffff0000
72681 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
72682 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_RESET 0xffff
72683 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI field value from a register. */
72684 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
72685 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value suitable for setting the register. */
72686 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
72687 
72688 /*
72689  * Field : Mask Byte Control - mbc_0
72690  *
72691  * This array of bits are mask control bits for comparison of each of the MAC
72692  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72693  * received DA or SA with the contents of MAC Address85 high and low registers.
72694  * Each bit controls the masking of the bytes. You can filter a group of addresses
72695  * (known as group address filtering) by masking one or more bytes of the address.
72696  *
72697  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72698  *
72699  * Field Enumeration Values:
72700  *
72701  * Enum | Value | Description
72702  * :----------------------------------------------|:------|:------------------------------------
72703  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72704  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72705  *
72706  * Field Access Macros:
72707  *
72708  */
72709 /*
72710  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0
72711  *
72712  * Byte is unmasked (i.e. is compared)
72713  */
72714 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED 0x0
72715 /*
72716  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0
72717  *
72718  * Byte is masked (i.e. not compared)
72719  */
72720 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED 0x1
72721 
72722 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
72723 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_LSB 24
72724 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
72725 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_MSB 24
72726 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
72727 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_WIDTH 1
72728 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */
72729 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET_MSK 0x01000000
72730 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */
72731 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_CLR_MSK 0xfeffffff
72732 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
72733 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_RESET 0x0
72734 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 field value from a register. */
72735 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
72736 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value suitable for setting the register. */
72737 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
72738 
72739 /*
72740  * Field : Mask Byte Control - mbc_1
72741  *
72742  * This array of bits are mask control bits for comparison of each of the MAC
72743  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72744  * received DA or SA with the contents of MAC Address85 high and low registers.
72745  * Each bit controls the masking of the bytes. You can filter a group of addresses
72746  * (known as group address filtering) by masking one or more bytes of the address.
72747  *
72748  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72749  *
72750  * Field Enumeration Values:
72751  *
72752  * Enum | Value | Description
72753  * :----------------------------------------------|:------|:------------------------------------
72754  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72755  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72756  *
72757  * Field Access Macros:
72758  *
72759  */
72760 /*
72761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1
72762  *
72763  * Byte is unmasked (i.e. is compared)
72764  */
72765 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED 0x0
72766 /*
72767  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1
72768  *
72769  * Byte is masked (i.e. not compared)
72770  */
72771 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED 0x1
72772 
72773 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
72774 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_LSB 25
72775 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
72776 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_MSB 25
72777 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
72778 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_WIDTH 1
72779 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */
72780 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET_MSK 0x02000000
72781 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */
72782 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_CLR_MSK 0xfdffffff
72783 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
72784 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_RESET 0x0
72785 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 field value from a register. */
72786 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
72787 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value suitable for setting the register. */
72788 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
72789 
72790 /*
72791  * Field : Mask Byte Control - mbc_2
72792  *
72793  * This array of bits are mask control bits for comparison of each of the MAC
72794  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72795  * received DA or SA with the contents of MAC Address85 high and low registers.
72796  * Each bit controls the masking of the bytes. You can filter a group of addresses
72797  * (known as group address filtering) by masking one or more bytes of the address.
72798  *
72799  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72800  *
72801  * Field Enumeration Values:
72802  *
72803  * Enum | Value | Description
72804  * :----------------------------------------------|:------|:------------------------------------
72805  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72806  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72807  *
72808  * Field Access Macros:
72809  *
72810  */
72811 /*
72812  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2
72813  *
72814  * Byte is unmasked (i.e. is compared)
72815  */
72816 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED 0x0
72817 /*
72818  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2
72819  *
72820  * Byte is masked (i.e. not compared)
72821  */
72822 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED 0x1
72823 
72824 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
72825 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_LSB 26
72826 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
72827 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_MSB 26
72828 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
72829 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_WIDTH 1
72830 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */
72831 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET_MSK 0x04000000
72832 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */
72833 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_CLR_MSK 0xfbffffff
72834 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
72835 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_RESET 0x0
72836 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 field value from a register. */
72837 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
72838 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value suitable for setting the register. */
72839 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
72840 
72841 /*
72842  * Field : Mask Byte Control - mbc_3
72843  *
72844  * This array of bits are mask control bits for comparison of each of the MAC
72845  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72846  * received DA or SA with the contents of MAC Address85 high and low registers.
72847  * Each bit controls the masking of the bytes. You can filter a group of addresses
72848  * (known as group address filtering) by masking one or more bytes of the address.
72849  *
72850  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72851  *
72852  * Field Enumeration Values:
72853  *
72854  * Enum | Value | Description
72855  * :----------------------------------------------|:------|:------------------------------------
72856  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72857  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72858  *
72859  * Field Access Macros:
72860  *
72861  */
72862 /*
72863  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3
72864  *
72865  * Byte is unmasked (i.e. is compared)
72866  */
72867 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED 0x0
72868 /*
72869  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3
72870  *
72871  * Byte is masked (i.e. not compared)
72872  */
72873 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED 0x1
72874 
72875 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
72876 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_LSB 27
72877 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
72878 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_MSB 27
72879 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
72880 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_WIDTH 1
72881 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */
72882 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET_MSK 0x08000000
72883 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */
72884 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_CLR_MSK 0xf7ffffff
72885 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
72886 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_RESET 0x0
72887 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 field value from a register. */
72888 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
72889 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value suitable for setting the register. */
72890 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
72891 
72892 /*
72893  * Field : Mask Byte Control - mbc_4
72894  *
72895  * This array of bits are mask control bits for comparison of each of the MAC
72896  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72897  * received DA or SA with the contents of MAC Address85 high and low registers.
72898  * Each bit controls the masking of the bytes. You can filter a group of addresses
72899  * (known as group address filtering) by masking one or more bytes of the address.
72900  *
72901  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72902  *
72903  * Field Enumeration Values:
72904  *
72905  * Enum | Value | Description
72906  * :----------------------------------------------|:------|:------------------------------------
72907  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72908  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72909  *
72910  * Field Access Macros:
72911  *
72912  */
72913 /*
72914  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4
72915  *
72916  * Byte is unmasked (i.e. is compared)
72917  */
72918 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED 0x0
72919 /*
72920  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4
72921  *
72922  * Byte is masked (i.e. not compared)
72923  */
72924 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED 0x1
72925 
72926 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
72927 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_LSB 28
72928 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
72929 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_MSB 28
72930 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
72931 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_WIDTH 1
72932 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */
72933 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET_MSK 0x10000000
72934 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */
72935 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_CLR_MSK 0xefffffff
72936 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
72937 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_RESET 0x0
72938 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 field value from a register. */
72939 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
72940 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value suitable for setting the register. */
72941 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
72942 
72943 /*
72944  * Field : Mask Byte Control - mbc_5
72945  *
72946  * This array of bits are mask control bits for comparison of each of the MAC
72947  * Address bytes. When masked, the MAC does not compare the corresponding byte of
72948  * received DA or SA with the contents of MAC Address85 high and low registers.
72949  * Each bit controls the masking of the bytes. You can filter a group of addresses
72950  * (known as group address filtering) by masking one or more bytes of the address.
72951  *
72952  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
72953  *
72954  * Field Enumeration Values:
72955  *
72956  * Enum | Value | Description
72957  * :----------------------------------------------|:------|:------------------------------------
72958  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
72959  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
72960  *
72961  * Field Access Macros:
72962  *
72963  */
72964 /*
72965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5
72966  *
72967  * Byte is unmasked (i.e. is compared)
72968  */
72969 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED 0x0
72970 /*
72971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5
72972  *
72973  * Byte is masked (i.e. not compared)
72974  */
72975 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED 0x1
72976 
72977 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
72978 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_LSB 29
72979 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
72980 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_MSB 29
72981 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
72982 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_WIDTH 1
72983 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */
72984 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET_MSK 0x20000000
72985 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */
72986 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_CLR_MSK 0xdfffffff
72987 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
72988 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_RESET 0x0
72989 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 field value from a register. */
72990 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
72991 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value suitable for setting the register. */
72992 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
72993 
72994 /*
72995  * Field : Source Address - sa
72996  *
72997  * When this bit is enabled, the MAC Address85[47:0] is used to compare with the SA
72998  * fields of the received frame. When this bit is disabled, the MAC Address85[47:0]
72999  * is used to compare with the DA fields of the received frame.
73000  *
73001  * Field Enumeration Values:
73002  *
73003  * Enum | Value | Description
73004  * :----------------------------------------|:------|:-----------------------------
73005  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
73006  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END | 0x1 | MAC address compare enabled
73007  *
73008  * Field Access Macros:
73009  *
73010  */
73011 /*
73012  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA
73013  *
73014  * MAC address compare disabled
73015  */
73016 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD 0x0
73017 /*
73018  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA
73019  *
73020  * MAC address compare enabled
73021  */
73022 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END 0x1
73023 
73024 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
73025 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_LSB 30
73026 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
73027 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_MSB 30
73028 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
73029 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_WIDTH 1
73030 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */
73031 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET_MSK 0x40000000
73032 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */
73033 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_CLR_MSK 0xbfffffff
73034 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
73035 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_RESET 0x0
73036 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA field value from a register. */
73037 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
73038 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value suitable for setting the register. */
73039 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
73040 
73041 /*
73042  * Field : Address Enable - ae
73043  *
73044  * When this bit is enabled, the address filter block uses the 86th MAC address for
73045  * perfect filtering. When this bit is disabled, the address filter block ignores
73046  * the address for filtering.
73047  *
73048  * Field Enumeration Values:
73049  *
73050  * Enum | Value | Description
73051  * :----------------------------------------|:------|:--------------------------------------
73052  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
73053  * ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
73054  *
73055  * Field Access Macros:
73056  *
73057  */
73058 /*
73059  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
73060  *
73061  * Second MAC address filtering disabled
73062  */
73063 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD 0x0
73064 /*
73065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
73066  *
73067  * Second MAC address filtering enabled
73068  */
73069 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END 0x1
73070 
73071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
73072 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_LSB 31
73073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
73074 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_MSB 31
73075 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
73076 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_WIDTH 1
73077 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
73078 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET_MSK 0x80000000
73079 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
73080 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_CLR_MSK 0x7fffffff
73081 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
73082 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_RESET 0x0
73083 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE field value from a register. */
73084 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
73085 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value suitable for setting the register. */
73086 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
73087 
73088 #ifndef __ASSEMBLY__
73089 /*
73090  * WARNING: The C register and register group struct declarations are provided for
73091  * convenience and illustrative purposes. They should, however, be used with
73092  * caution as the C language standard provides no guarantees about the alignment or
73093  * atomicity of device memory accesses. The recommended practice for writing
73094  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73095  * alt_write_word() functions.
73096  *
73097  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH.
73098  */
73099 struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s
73100 {
73101  uint32_t addrhi : 16; /* MAC Address85 [47:32] */
73102  uint32_t : 8; /* *UNDEFINED* */
73103  uint32_t mbc_0 : 1; /* Mask Byte Control */
73104  uint32_t mbc_1 : 1; /* Mask Byte Control */
73105  uint32_t mbc_2 : 1; /* Mask Byte Control */
73106  uint32_t mbc_3 : 1; /* Mask Byte Control */
73107  uint32_t mbc_4 : 1; /* Mask Byte Control */
73108  uint32_t mbc_5 : 1; /* Mask Byte Control */
73109  uint32_t sa : 1; /* Source Address */
73110  uint32_t ae : 1; /* Address Enable */
73111 };
73112 
73113 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH. */
73114 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t;
73115 #endif /* __ASSEMBLY__ */
73116 
73117 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register from the beginning of the component. */
73118 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST 0xa28
73119 /* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register. */
73120 #define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST))
73121 
73122 /*
73123  * Register : Register 651 (MAC Address85 Low Register) - MAC_Address85_Low
73124  *
73125  * The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC
73126  * address of the station.
73127  *
73128  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
73129  * format.
73130  *
73131  * Register Layout
73132  *
73133  * Bits | Access | Reset | Description
73134  * :-------|:-------|:-----------|:---------------------
73135  * [31:0] | RW | 0xffffffff | MAC Address85 [31:0]
73136  *
73137  */
73138 /*
73139  * Field : MAC Address85 [31:0] - addrlo
73140  *
73141  * This field contains the lower 32 bits of the 86th 6-byte MAC address. The
73142  * content of this field is undefined until loaded by software after the
73143  * initialization process.
73144  *
73145  * Field Access Macros:
73146  *
73147  */
73148 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
73149 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_LSB 0
73150 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
73151 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_MSB 31
73152 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
73153 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_WIDTH 32
73154 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
73155 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET_MSK 0xffffffff
73156 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
73157 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_CLR_MSK 0x00000000
73158 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
73159 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_RESET 0xffffffff
73160 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO field value from a register. */
73161 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
73162 /* Produces a ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value suitable for setting the register. */
73163 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
73164 
73165 #ifndef __ASSEMBLY__
73166 /*
73167  * WARNING: The C register and register group struct declarations are provided for
73168  * convenience and illustrative purposes. They should, however, be used with
73169  * caution as the C language standard provides no guarantees about the alignment or
73170  * atomicity of device memory accesses. The recommended practice for writing
73171  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73172  * alt_write_word() functions.
73173  *
73174  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW.
73175  */
73176 struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s
73177 {
73178  uint32_t addrlo : 32; /* MAC Address85 [31:0] */
73179 };
73180 
73181 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW. */
73182 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s ALT_EMAC_GMAC_MAC_ADDR85_LOW_t;
73183 #endif /* __ASSEMBLY__ */
73184 
73185 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register from the beginning of the component. */
73186 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST 0xa2c
73187 /* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register. */
73188 #define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST))
73189 
73190 /*
73191  * Register : Register 652 (MAC Address86 High Register) - MAC_Address86_High
73192  *
73193  * The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC
73194  * address of the station. Because the MAC address registers are configured to be
73195  * double-synchronized to the (G)MII clock domains, the synchronization is
73196  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
73197  * endian mode) of the MAC Address86 Low Register are written. For proper
73198  * synchronization updates, the consecutive writes to this Address Low Register
73199  * should be performed after at least four clock cycles in the destination clock
73200  * domain.
73201  *
73202  * Note that all MAC Address High registers (except MAC Address0 High) have the
73203  * same format.
73204  *
73205  * Register Layout
73206  *
73207  * Bits | Access | Reset | Description
73208  * :--------|:-------|:-------|:----------------------
73209  * [15:0] | RW | 0xffff | MAC Address86 [47:32]
73210  * [23:16] | ??? | 0x0 | *UNDEFINED*
73211  * [24] | RW | 0x0 | Mask Byte Control
73212  * [25] | RW | 0x0 | Mask Byte Control
73213  * [26] | RW | 0x0 | Mask Byte Control
73214  * [27] | RW | 0x0 | Mask Byte Control
73215  * [28] | RW | 0x0 | Mask Byte Control
73216  * [29] | RW | 0x0 | Mask Byte Control
73217  * [30] | RW | 0x0 | Source Address
73218  * [31] | RW | 0x0 | Address Enable
73219  *
73220  */
73221 /*
73222  * Field : MAC Address86 [47:32] - addrhi
73223  *
73224  * This field contains the upper 16 bits (47:32) of the 87th 6-byte MAC address.
73225  *
73226  * Field Access Macros:
73227  *
73228  */
73229 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
73230 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_LSB 0
73231 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
73232 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_MSB 15
73233 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
73234 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_WIDTH 16
73235 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
73236 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET_MSK 0x0000ffff
73237 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
73238 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_CLR_MSK 0xffff0000
73239 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
73240 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_RESET 0xffff
73241 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI field value from a register. */
73242 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
73243 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value suitable for setting the register. */
73244 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
73245 
73246 /*
73247  * Field : Mask Byte Control - mbc_0
73248  *
73249  * This array of bits are mask control bits for comparison of each of the MAC
73250  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73251  * received DA or SA with the contents of MAC Address86 high and low registers.
73252  * Each bit controls the masking of the bytes. You can filter a group of addresses
73253  * (known as group address filtering) by masking one or more bytes of the address.
73254  *
73255  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73256  *
73257  * Field Enumeration Values:
73258  *
73259  * Enum | Value | Description
73260  * :----------------------------------------------|:------|:------------------------------------
73261  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73262  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73263  *
73264  * Field Access Macros:
73265  *
73266  */
73267 /*
73268  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0
73269  *
73270  * Byte is unmasked (i.e. is compared)
73271  */
73272 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED 0x0
73273 /*
73274  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0
73275  *
73276  * Byte is masked (i.e. not compared)
73277  */
73278 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED 0x1
73279 
73280 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
73281 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_LSB 24
73282 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
73283 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_MSB 24
73284 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
73285 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_WIDTH 1
73286 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */
73287 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET_MSK 0x01000000
73288 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */
73289 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_CLR_MSK 0xfeffffff
73290 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
73291 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_RESET 0x0
73292 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 field value from a register. */
73293 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
73294 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value suitable for setting the register. */
73295 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
73296 
73297 /*
73298  * Field : Mask Byte Control - mbc_1
73299  *
73300  * This array of bits are mask control bits for comparison of each of the MAC
73301  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73302  * received DA or SA with the contents of MAC Address86 high and low registers.
73303  * Each bit controls the masking of the bytes. You can filter a group of addresses
73304  * (known as group address filtering) by masking one or more bytes of the address.
73305  *
73306  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73307  *
73308  * Field Enumeration Values:
73309  *
73310  * Enum | Value | Description
73311  * :----------------------------------------------|:------|:------------------------------------
73312  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73313  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73314  *
73315  * Field Access Macros:
73316  *
73317  */
73318 /*
73319  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1
73320  *
73321  * Byte is unmasked (i.e. is compared)
73322  */
73323 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED 0x0
73324 /*
73325  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1
73326  *
73327  * Byte is masked (i.e. not compared)
73328  */
73329 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED 0x1
73330 
73331 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
73332 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_LSB 25
73333 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
73334 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_MSB 25
73335 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
73336 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_WIDTH 1
73337 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */
73338 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET_MSK 0x02000000
73339 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */
73340 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_CLR_MSK 0xfdffffff
73341 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
73342 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_RESET 0x0
73343 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 field value from a register. */
73344 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
73345 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value suitable for setting the register. */
73346 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
73347 
73348 /*
73349  * Field : Mask Byte Control - mbc_2
73350  *
73351  * This array of bits are mask control bits for comparison of each of the MAC
73352  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73353  * received DA or SA with the contents of MAC Address86 high and low registers.
73354  * Each bit controls the masking of the bytes. You can filter a group of addresses
73355  * (known as group address filtering) by masking one or more bytes of the address.
73356  *
73357  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73358  *
73359  * Field Enumeration Values:
73360  *
73361  * Enum | Value | Description
73362  * :----------------------------------------------|:------|:------------------------------------
73363  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73364  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73365  *
73366  * Field Access Macros:
73367  *
73368  */
73369 /*
73370  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2
73371  *
73372  * Byte is unmasked (i.e. is compared)
73373  */
73374 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED 0x0
73375 /*
73376  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2
73377  *
73378  * Byte is masked (i.e. not compared)
73379  */
73380 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED 0x1
73381 
73382 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
73383 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_LSB 26
73384 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
73385 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_MSB 26
73386 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
73387 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_WIDTH 1
73388 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */
73389 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET_MSK 0x04000000
73390 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */
73391 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_CLR_MSK 0xfbffffff
73392 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
73393 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_RESET 0x0
73394 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 field value from a register. */
73395 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
73396 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value suitable for setting the register. */
73397 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
73398 
73399 /*
73400  * Field : Mask Byte Control - mbc_3
73401  *
73402  * This array of bits are mask control bits for comparison of each of the MAC
73403  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73404  * received DA or SA with the contents of MAC Address86 high and low registers.
73405  * Each bit controls the masking of the bytes. You can filter a group of addresses
73406  * (known as group address filtering) by masking one or more bytes of the address.
73407  *
73408  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73409  *
73410  * Field Enumeration Values:
73411  *
73412  * Enum | Value | Description
73413  * :----------------------------------------------|:------|:------------------------------------
73414  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73415  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73416  *
73417  * Field Access Macros:
73418  *
73419  */
73420 /*
73421  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3
73422  *
73423  * Byte is unmasked (i.e. is compared)
73424  */
73425 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED 0x0
73426 /*
73427  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3
73428  *
73429  * Byte is masked (i.e. not compared)
73430  */
73431 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED 0x1
73432 
73433 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
73434 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_LSB 27
73435 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
73436 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_MSB 27
73437 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
73438 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_WIDTH 1
73439 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */
73440 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET_MSK 0x08000000
73441 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */
73442 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_CLR_MSK 0xf7ffffff
73443 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
73444 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_RESET 0x0
73445 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 field value from a register. */
73446 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
73447 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value suitable for setting the register. */
73448 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
73449 
73450 /*
73451  * Field : Mask Byte Control - mbc_4
73452  *
73453  * This array of bits are mask control bits for comparison of each of the MAC
73454  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73455  * received DA or SA with the contents of MAC Address86 high and low registers.
73456  * Each bit controls the masking of the bytes. You can filter a group of addresses
73457  * (known as group address filtering) by masking one or more bytes of the address.
73458  *
73459  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73460  *
73461  * Field Enumeration Values:
73462  *
73463  * Enum | Value | Description
73464  * :----------------------------------------------|:------|:------------------------------------
73465  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73466  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73467  *
73468  * Field Access Macros:
73469  *
73470  */
73471 /*
73472  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4
73473  *
73474  * Byte is unmasked (i.e. is compared)
73475  */
73476 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED 0x0
73477 /*
73478  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4
73479  *
73480  * Byte is masked (i.e. not compared)
73481  */
73482 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED 0x1
73483 
73484 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
73485 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_LSB 28
73486 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
73487 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_MSB 28
73488 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
73489 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_WIDTH 1
73490 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */
73491 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET_MSK 0x10000000
73492 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */
73493 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_CLR_MSK 0xefffffff
73494 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
73495 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_RESET 0x0
73496 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 field value from a register. */
73497 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
73498 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value suitable for setting the register. */
73499 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
73500 
73501 /*
73502  * Field : Mask Byte Control - mbc_5
73503  *
73504  * This array of bits are mask control bits for comparison of each of the MAC
73505  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73506  * received DA or SA with the contents of MAC Address86 high and low registers.
73507  * Each bit controls the masking of the bytes. You can filter a group of addresses
73508  * (known as group address filtering) by masking one or more bytes of the address.
73509  *
73510  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73511  *
73512  * Field Enumeration Values:
73513  *
73514  * Enum | Value | Description
73515  * :----------------------------------------------|:------|:------------------------------------
73516  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73517  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73518  *
73519  * Field Access Macros:
73520  *
73521  */
73522 /*
73523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5
73524  *
73525  * Byte is unmasked (i.e. is compared)
73526  */
73527 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED 0x0
73528 /*
73529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5
73530  *
73531  * Byte is masked (i.e. not compared)
73532  */
73533 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED 0x1
73534 
73535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
73536 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_LSB 29
73537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
73538 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_MSB 29
73539 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
73540 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_WIDTH 1
73541 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */
73542 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET_MSK 0x20000000
73543 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */
73544 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_CLR_MSK 0xdfffffff
73545 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
73546 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_RESET 0x0
73547 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 field value from a register. */
73548 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
73549 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value suitable for setting the register. */
73550 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
73551 
73552 /*
73553  * Field : Source Address - sa
73554  *
73555  * When this bit is enabled, the MAC Address86[47:0] is used to compare with the SA
73556  * fields of the received frame. When this bit is disabled, the MAC Address86[47:0]
73557  * is used to compare with the DA fields of the received frame.
73558  *
73559  * Field Enumeration Values:
73560  *
73561  * Enum | Value | Description
73562  * :----------------------------------------|:------|:-----------------------------
73563  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
73564  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END | 0x1 | MAC address compare enabled
73565  *
73566  * Field Access Macros:
73567  *
73568  */
73569 /*
73570  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA
73571  *
73572  * MAC address compare disabled
73573  */
73574 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD 0x0
73575 /*
73576  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA
73577  *
73578  * MAC address compare enabled
73579  */
73580 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END 0x1
73581 
73582 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
73583 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_LSB 30
73584 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
73585 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_MSB 30
73586 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
73587 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_WIDTH 1
73588 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */
73589 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET_MSK 0x40000000
73590 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */
73591 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_CLR_MSK 0xbfffffff
73592 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
73593 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_RESET 0x0
73594 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA field value from a register. */
73595 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
73596 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value suitable for setting the register. */
73597 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
73598 
73599 /*
73600  * Field : Address Enable - ae
73601  *
73602  * When this bit is enabled, the address filter block uses the 87th MAC address for
73603  * perfect filtering. When this bit is disabled, the address filter block ignores
73604  * the address for filtering.
73605  *
73606  * Field Enumeration Values:
73607  *
73608  * Enum | Value | Description
73609  * :----------------------------------------|:------|:--------------------------------------
73610  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
73611  * ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
73612  *
73613  * Field Access Macros:
73614  *
73615  */
73616 /*
73617  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
73618  *
73619  * Second MAC address filtering disabled
73620  */
73621 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD 0x0
73622 /*
73623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
73624  *
73625  * Second MAC address filtering enabled
73626  */
73627 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END 0x1
73628 
73629 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
73630 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_LSB 31
73631 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
73632 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_MSB 31
73633 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
73634 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_WIDTH 1
73635 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
73636 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET_MSK 0x80000000
73637 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
73638 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_CLR_MSK 0x7fffffff
73639 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
73640 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_RESET 0x0
73641 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE field value from a register. */
73642 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
73643 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value suitable for setting the register. */
73644 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
73645 
73646 #ifndef __ASSEMBLY__
73647 /*
73648  * WARNING: The C register and register group struct declarations are provided for
73649  * convenience and illustrative purposes. They should, however, be used with
73650  * caution as the C language standard provides no guarantees about the alignment or
73651  * atomicity of device memory accesses. The recommended practice for writing
73652  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73653  * alt_write_word() functions.
73654  *
73655  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH.
73656  */
73657 struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s
73658 {
73659  uint32_t addrhi : 16; /* MAC Address86 [47:32] */
73660  uint32_t : 8; /* *UNDEFINED* */
73661  uint32_t mbc_0 : 1; /* Mask Byte Control */
73662  uint32_t mbc_1 : 1; /* Mask Byte Control */
73663  uint32_t mbc_2 : 1; /* Mask Byte Control */
73664  uint32_t mbc_3 : 1; /* Mask Byte Control */
73665  uint32_t mbc_4 : 1; /* Mask Byte Control */
73666  uint32_t mbc_5 : 1; /* Mask Byte Control */
73667  uint32_t sa : 1; /* Source Address */
73668  uint32_t ae : 1; /* Address Enable */
73669 };
73670 
73671 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH. */
73672 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t;
73673 #endif /* __ASSEMBLY__ */
73674 
73675 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register from the beginning of the component. */
73676 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST 0xa30
73677 /* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register. */
73678 #define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST))
73679 
73680 /*
73681  * Register : Register 653 (MAC Address86 Low Register) - MAC_Address86_Low
73682  *
73683  * The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC
73684  * address of the station.
73685  *
73686  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
73687  * format.
73688  *
73689  * Register Layout
73690  *
73691  * Bits | Access | Reset | Description
73692  * :-------|:-------|:-----------|:---------------------
73693  * [31:0] | RW | 0xffffffff | MAC Address86 [31:0]
73694  *
73695  */
73696 /*
73697  * Field : MAC Address86 [31:0] - addrlo
73698  *
73699  * This field contains the lower 32 bits of the 87th 6-byte MAC address. The
73700  * content of this field is undefined until loaded by software after the
73701  * initialization process.
73702  *
73703  * Field Access Macros:
73704  *
73705  */
73706 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
73707 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_LSB 0
73708 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
73709 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_MSB 31
73710 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
73711 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_WIDTH 32
73712 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
73713 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET_MSK 0xffffffff
73714 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
73715 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_CLR_MSK 0x00000000
73716 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
73717 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_RESET 0xffffffff
73718 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO field value from a register. */
73719 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
73720 /* Produces a ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value suitable for setting the register. */
73721 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
73722 
73723 #ifndef __ASSEMBLY__
73724 /*
73725  * WARNING: The C register and register group struct declarations are provided for
73726  * convenience and illustrative purposes. They should, however, be used with
73727  * caution as the C language standard provides no guarantees about the alignment or
73728  * atomicity of device memory accesses. The recommended practice for writing
73729  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
73730  * alt_write_word() functions.
73731  *
73732  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW.
73733  */
73734 struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s
73735 {
73736  uint32_t addrlo : 32; /* MAC Address86 [31:0] */
73737 };
73738 
73739 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW. */
73740 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s ALT_EMAC_GMAC_MAC_ADDR86_LOW_t;
73741 #endif /* __ASSEMBLY__ */
73742 
73743 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register from the beginning of the component. */
73744 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST 0xa34
73745 /* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register. */
73746 #define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST))
73747 
73748 /*
73749  * Register : Register 654 (MAC Address87 High Register) - MAC_Address87_High
73750  *
73751  * The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC
73752  * address of the station. Because the MAC address registers are configured to be
73753  * double-synchronized to the (G)MII clock domains, the synchronization is
73754  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
73755  * endian mode) of the MAC Address87 Low Register are written. For proper
73756  * synchronization updates, the consecutive writes to this Address Low Register
73757  * should be performed after at least four clock cycles in the destination clock
73758  * domain.
73759  *
73760  * Note that all MAC Address High registers (except MAC Address0 High) have the
73761  * same format.
73762  *
73763  * Register Layout
73764  *
73765  * Bits | Access | Reset | Description
73766  * :--------|:-------|:-------|:----------------------
73767  * [15:0] | RW | 0xffff | MAC Address87 [47:32]
73768  * [23:16] | ??? | 0x0 | *UNDEFINED*
73769  * [24] | RW | 0x0 | Mask Byte Control
73770  * [25] | RW | 0x0 | Mask Byte Control
73771  * [26] | RW | 0x0 | Mask Byte Control
73772  * [27] | RW | 0x0 | Mask Byte Control
73773  * [28] | RW | 0x0 | Mask Byte Control
73774  * [29] | RW | 0x0 | Mask Byte Control
73775  * [30] | RW | 0x0 | Source Address
73776  * [31] | RW | 0x0 | Address Enable
73777  *
73778  */
73779 /*
73780  * Field : MAC Address87 [47:32] - addrhi
73781  *
73782  * This field contains the upper 16 bits (47:32) of the 88th 6-byte MAC address.
73783  *
73784  * Field Access Macros:
73785  *
73786  */
73787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
73788 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_LSB 0
73789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
73790 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_MSB 15
73791 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
73792 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_WIDTH 16
73793 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
73794 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET_MSK 0x0000ffff
73795 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
73796 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_CLR_MSK 0xffff0000
73797 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
73798 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_RESET 0xffff
73799 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI field value from a register. */
73800 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
73801 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value suitable for setting the register. */
73802 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
73803 
73804 /*
73805  * Field : Mask Byte Control - mbc_0
73806  *
73807  * This array of bits are mask control bits for comparison of each of the MAC
73808  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73809  * received DA or SA with the contents of MAC Address87 high and low registers.
73810  * Each bit controls the masking of the bytes. You can filter a group of addresses
73811  * (known as group address filtering) by masking one or more bytes of the address.
73812  *
73813  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73814  *
73815  * Field Enumeration Values:
73816  *
73817  * Enum | Value | Description
73818  * :----------------------------------------------|:------|:------------------------------------
73819  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73820  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73821  *
73822  * Field Access Macros:
73823  *
73824  */
73825 /*
73826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0
73827  *
73828  * Byte is unmasked (i.e. is compared)
73829  */
73830 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED 0x0
73831 /*
73832  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0
73833  *
73834  * Byte is masked (i.e. not compared)
73835  */
73836 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED 0x1
73837 
73838 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
73839 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_LSB 24
73840 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
73841 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_MSB 24
73842 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
73843 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_WIDTH 1
73844 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */
73845 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET_MSK 0x01000000
73846 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */
73847 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_CLR_MSK 0xfeffffff
73848 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
73849 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_RESET 0x0
73850 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 field value from a register. */
73851 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
73852 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value suitable for setting the register. */
73853 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
73854 
73855 /*
73856  * Field : Mask Byte Control - mbc_1
73857  *
73858  * This array of bits are mask control bits for comparison of each of the MAC
73859  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73860  * received DA or SA with the contents of MAC Address87 high and low registers.
73861  * Each bit controls the masking of the bytes. You can filter a group of addresses
73862  * (known as group address filtering) by masking one or more bytes of the address.
73863  *
73864  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73865  *
73866  * Field Enumeration Values:
73867  *
73868  * Enum | Value | Description
73869  * :----------------------------------------------|:------|:------------------------------------
73870  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73871  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73872  *
73873  * Field Access Macros:
73874  *
73875  */
73876 /*
73877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1
73878  *
73879  * Byte is unmasked (i.e. is compared)
73880  */
73881 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED 0x0
73882 /*
73883  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1
73884  *
73885  * Byte is masked (i.e. not compared)
73886  */
73887 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED 0x1
73888 
73889 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
73890 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_LSB 25
73891 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
73892 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_MSB 25
73893 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
73894 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_WIDTH 1
73895 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */
73896 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET_MSK 0x02000000
73897 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */
73898 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_CLR_MSK 0xfdffffff
73899 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
73900 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_RESET 0x0
73901 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 field value from a register. */
73902 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
73903 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value suitable for setting the register. */
73904 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
73905 
73906 /*
73907  * Field : Mask Byte Control - mbc_2
73908  *
73909  * This array of bits are mask control bits for comparison of each of the MAC
73910  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73911  * received DA or SA with the contents of MAC Address87 high and low registers.
73912  * Each bit controls the masking of the bytes. You can filter a group of addresses
73913  * (known as group address filtering) by masking one or more bytes of the address.
73914  *
73915  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73916  *
73917  * Field Enumeration Values:
73918  *
73919  * Enum | Value | Description
73920  * :----------------------------------------------|:------|:------------------------------------
73921  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73922  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73923  *
73924  * Field Access Macros:
73925  *
73926  */
73927 /*
73928  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2
73929  *
73930  * Byte is unmasked (i.e. is compared)
73931  */
73932 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED 0x0
73933 /*
73934  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2
73935  *
73936  * Byte is masked (i.e. not compared)
73937  */
73938 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED 0x1
73939 
73940 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
73941 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_LSB 26
73942 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
73943 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_MSB 26
73944 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
73945 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_WIDTH 1
73946 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */
73947 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET_MSK 0x04000000
73948 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */
73949 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_CLR_MSK 0xfbffffff
73950 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
73951 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_RESET 0x0
73952 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 field value from a register. */
73953 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
73954 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value suitable for setting the register. */
73955 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
73956 
73957 /*
73958  * Field : Mask Byte Control - mbc_3
73959  *
73960  * This array of bits are mask control bits for comparison of each of the MAC
73961  * Address bytes. When masked, the MAC does not compare the corresponding byte of
73962  * received DA or SA with the contents of MAC Address87 high and low registers.
73963  * Each bit controls the masking of the bytes. You can filter a group of addresses
73964  * (known as group address filtering) by masking one or more bytes of the address.
73965  *
73966  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
73967  *
73968  * Field Enumeration Values:
73969  *
73970  * Enum | Value | Description
73971  * :----------------------------------------------|:------|:------------------------------------
73972  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
73973  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
73974  *
73975  * Field Access Macros:
73976  *
73977  */
73978 /*
73979  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3
73980  *
73981  * Byte is unmasked (i.e. is compared)
73982  */
73983 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED 0x0
73984 /*
73985  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3
73986  *
73987  * Byte is masked (i.e. not compared)
73988  */
73989 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED 0x1
73990 
73991 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
73992 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_LSB 27
73993 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
73994 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_MSB 27
73995 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
73996 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_WIDTH 1
73997 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */
73998 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET_MSK 0x08000000
73999 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */
74000 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_CLR_MSK 0xf7ffffff
74001 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
74002 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_RESET 0x0
74003 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 field value from a register. */
74004 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
74005 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value suitable for setting the register. */
74006 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
74007 
74008 /*
74009  * Field : Mask Byte Control - mbc_4
74010  *
74011  * This array of bits are mask control bits for comparison of each of the MAC
74012  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74013  * received DA or SA with the contents of MAC Address87 high and low registers.
74014  * Each bit controls the masking of the bytes. You can filter a group of addresses
74015  * (known as group address filtering) by masking one or more bytes of the address.
74016  *
74017  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74018  *
74019  * Field Enumeration Values:
74020  *
74021  * Enum | Value | Description
74022  * :----------------------------------------------|:------|:------------------------------------
74023  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74024  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74025  *
74026  * Field Access Macros:
74027  *
74028  */
74029 /*
74030  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4
74031  *
74032  * Byte is unmasked (i.e. is compared)
74033  */
74034 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED 0x0
74035 /*
74036  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4
74037  *
74038  * Byte is masked (i.e. not compared)
74039  */
74040 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED 0x1
74041 
74042 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
74043 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_LSB 28
74044 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
74045 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_MSB 28
74046 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
74047 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_WIDTH 1
74048 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */
74049 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET_MSK 0x10000000
74050 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */
74051 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_CLR_MSK 0xefffffff
74052 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
74053 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_RESET 0x0
74054 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 field value from a register. */
74055 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
74056 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value suitable for setting the register. */
74057 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
74058 
74059 /*
74060  * Field : Mask Byte Control - mbc_5
74061  *
74062  * This array of bits are mask control bits for comparison of each of the MAC
74063  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74064  * received DA or SA with the contents of MAC Address87 high and low registers.
74065  * Each bit controls the masking of the bytes. You can filter a group of addresses
74066  * (known as group address filtering) by masking one or more bytes of the address.
74067  *
74068  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74069  *
74070  * Field Enumeration Values:
74071  *
74072  * Enum | Value | Description
74073  * :----------------------------------------------|:------|:------------------------------------
74074  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74075  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74076  *
74077  * Field Access Macros:
74078  *
74079  */
74080 /*
74081  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5
74082  *
74083  * Byte is unmasked (i.e. is compared)
74084  */
74085 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED 0x0
74086 /*
74087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5
74088  *
74089  * Byte is masked (i.e. not compared)
74090  */
74091 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED 0x1
74092 
74093 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
74094 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_LSB 29
74095 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
74096 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_MSB 29
74097 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
74098 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_WIDTH 1
74099 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */
74100 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET_MSK 0x20000000
74101 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */
74102 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_CLR_MSK 0xdfffffff
74103 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
74104 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_RESET 0x0
74105 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 field value from a register. */
74106 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
74107 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value suitable for setting the register. */
74108 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
74109 
74110 /*
74111  * Field : Source Address - sa
74112  *
74113  * When this bit is enabled, the MAC Address87[47:0] is used to compare with the SA
74114  * fields of the received frame. When this bit is disabled, the MAC Address87[47:0]
74115  * is used to compare with the DA fields of the received frame.
74116  *
74117  * Field Enumeration Values:
74118  *
74119  * Enum | Value | Description
74120  * :----------------------------------------|:------|:-----------------------------
74121  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
74122  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END | 0x1 | MAC address compare enabled
74123  *
74124  * Field Access Macros:
74125  *
74126  */
74127 /*
74128  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA
74129  *
74130  * MAC address compare disabled
74131  */
74132 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD 0x0
74133 /*
74134  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA
74135  *
74136  * MAC address compare enabled
74137  */
74138 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END 0x1
74139 
74140 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
74141 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_LSB 30
74142 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
74143 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_MSB 30
74144 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
74145 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_WIDTH 1
74146 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */
74147 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET_MSK 0x40000000
74148 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */
74149 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_CLR_MSK 0xbfffffff
74150 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
74151 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_RESET 0x0
74152 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA field value from a register. */
74153 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
74154 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value suitable for setting the register. */
74155 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
74156 
74157 /*
74158  * Field : Address Enable - ae
74159  *
74160  * When this bit is enabled, the address filter block uses the 88th MAC address for
74161  * perfect filtering. When this bit is disabled, the address filter block ignores
74162  * the address for filtering.
74163  *
74164  * Field Enumeration Values:
74165  *
74166  * Enum | Value | Description
74167  * :----------------------------------------|:------|:--------------------------------------
74168  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
74169  * ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
74170  *
74171  * Field Access Macros:
74172  *
74173  */
74174 /*
74175  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
74176  *
74177  * Second MAC address filtering disabled
74178  */
74179 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD 0x0
74180 /*
74181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
74182  *
74183  * Second MAC address filtering enabled
74184  */
74185 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END 0x1
74186 
74187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
74188 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_LSB 31
74189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
74190 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_MSB 31
74191 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
74192 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_WIDTH 1
74193 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
74194 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET_MSK 0x80000000
74195 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
74196 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_CLR_MSK 0x7fffffff
74197 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
74198 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_RESET 0x0
74199 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE field value from a register. */
74200 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
74201 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value suitable for setting the register. */
74202 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
74203 
74204 #ifndef __ASSEMBLY__
74205 /*
74206  * WARNING: The C register and register group struct declarations are provided for
74207  * convenience and illustrative purposes. They should, however, be used with
74208  * caution as the C language standard provides no guarantees about the alignment or
74209  * atomicity of device memory accesses. The recommended practice for writing
74210  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74211  * alt_write_word() functions.
74212  *
74213  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH.
74214  */
74215 struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s
74216 {
74217  uint32_t addrhi : 16; /* MAC Address87 [47:32] */
74218  uint32_t : 8; /* *UNDEFINED* */
74219  uint32_t mbc_0 : 1; /* Mask Byte Control */
74220  uint32_t mbc_1 : 1; /* Mask Byte Control */
74221  uint32_t mbc_2 : 1; /* Mask Byte Control */
74222  uint32_t mbc_3 : 1; /* Mask Byte Control */
74223  uint32_t mbc_4 : 1; /* Mask Byte Control */
74224  uint32_t mbc_5 : 1; /* Mask Byte Control */
74225  uint32_t sa : 1; /* Source Address */
74226  uint32_t ae : 1; /* Address Enable */
74227 };
74228 
74229 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH. */
74230 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t;
74231 #endif /* __ASSEMBLY__ */
74232 
74233 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register from the beginning of the component. */
74234 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST 0xa38
74235 /* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register. */
74236 #define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST))
74237 
74238 /*
74239  * Register : Register 655 (MAC Address87 Low Register) - MAC_Address87_Low
74240  *
74241  * The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC
74242  * address of the station.
74243  *
74244  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
74245  * format.
74246  *
74247  * Register Layout
74248  *
74249  * Bits | Access | Reset | Description
74250  * :-------|:-------|:-----------|:---------------------
74251  * [31:0] | RW | 0xffffffff | MAC Address87 [31:0]
74252  *
74253  */
74254 /*
74255  * Field : MAC Address87 [31:0] - addrlo
74256  *
74257  * This field contains the lower 32 bits of the 88th 6-byte MAC address. The
74258  * content of this field is undefined until loaded by software after the
74259  * initialization process.
74260  *
74261  * Field Access Macros:
74262  *
74263  */
74264 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
74265 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_LSB 0
74266 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
74267 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_MSB 31
74268 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
74269 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_WIDTH 32
74270 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
74271 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET_MSK 0xffffffff
74272 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
74273 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_CLR_MSK 0x00000000
74274 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
74275 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_RESET 0xffffffff
74276 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO field value from a register. */
74277 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
74278 /* Produces a ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value suitable for setting the register. */
74279 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
74280 
74281 #ifndef __ASSEMBLY__
74282 /*
74283  * WARNING: The C register and register group struct declarations are provided for
74284  * convenience and illustrative purposes. They should, however, be used with
74285  * caution as the C language standard provides no guarantees about the alignment or
74286  * atomicity of device memory accesses. The recommended practice for writing
74287  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74288  * alt_write_word() functions.
74289  *
74290  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW.
74291  */
74292 struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s
74293 {
74294  uint32_t addrlo : 32; /* MAC Address87 [31:0] */
74295 };
74296 
74297 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW. */
74298 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s ALT_EMAC_GMAC_MAC_ADDR87_LOW_t;
74299 #endif /* __ASSEMBLY__ */
74300 
74301 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register from the beginning of the component. */
74302 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST 0xa3c
74303 /* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register. */
74304 #define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST))
74305 
74306 /*
74307  * Register : Register 656 (MAC Address88 High Register) - MAC_Address88_High
74308  *
74309  * The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC
74310  * address of the station. Because the MAC address registers are configured to be
74311  * double-synchronized to the (G)MII clock domains, the synchronization is
74312  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
74313  * endian mode) of the MAC Address88 Low Register are written. For proper
74314  * synchronization updates, the consecutive writes to this Address Low Register
74315  * should be performed after at least four clock cycles in the destination clock
74316  * domain.
74317  *
74318  * Note that all MAC Address High registers (except MAC Address0 High) have the
74319  * same format.
74320  *
74321  * Register Layout
74322  *
74323  * Bits | Access | Reset | Description
74324  * :--------|:-------|:-------|:----------------------
74325  * [15:0] | RW | 0xffff | MAC Address88 [47:32]
74326  * [23:16] | ??? | 0x0 | *UNDEFINED*
74327  * [24] | RW | 0x0 | Mask Byte Control
74328  * [25] | RW | 0x0 | Mask Byte Control
74329  * [26] | RW | 0x0 | Mask Byte Control
74330  * [27] | RW | 0x0 | Mask Byte Control
74331  * [28] | RW | 0x0 | Mask Byte Control
74332  * [29] | RW | 0x0 | Mask Byte Control
74333  * [30] | RW | 0x0 | Source Address
74334  * [31] | RW | 0x0 | Address Enable
74335  *
74336  */
74337 /*
74338  * Field : MAC Address88 [47:32] - addrhi
74339  *
74340  * This field contains the upper 16 bits (47:32) of the 89th 6-byte MAC address.
74341  *
74342  * Field Access Macros:
74343  *
74344  */
74345 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
74346 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_LSB 0
74347 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
74348 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_MSB 15
74349 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
74350 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_WIDTH 16
74351 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
74352 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET_MSK 0x0000ffff
74353 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
74354 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_CLR_MSK 0xffff0000
74355 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
74356 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_RESET 0xffff
74357 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI field value from a register. */
74358 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
74359 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value suitable for setting the register. */
74360 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
74361 
74362 /*
74363  * Field : Mask Byte Control - mbc_0
74364  *
74365  * This array of bits are mask control bits for comparison of each of the MAC
74366  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74367  * received DA or SA with the contents of MAC Address88 high and low registers.
74368  * Each bit controls the masking of the bytes. You can filter a group of addresses
74369  * (known as group address filtering) by masking one or more bytes of the address.
74370  *
74371  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74372  *
74373  * Field Enumeration Values:
74374  *
74375  * Enum | Value | Description
74376  * :----------------------------------------------|:------|:------------------------------------
74377  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74378  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74379  *
74380  * Field Access Macros:
74381  *
74382  */
74383 /*
74384  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0
74385  *
74386  * Byte is unmasked (i.e. is compared)
74387  */
74388 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED 0x0
74389 /*
74390  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0
74391  *
74392  * Byte is masked (i.e. not compared)
74393  */
74394 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED 0x1
74395 
74396 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
74397 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_LSB 24
74398 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
74399 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_MSB 24
74400 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
74401 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_WIDTH 1
74402 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */
74403 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET_MSK 0x01000000
74404 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */
74405 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_CLR_MSK 0xfeffffff
74406 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
74407 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_RESET 0x0
74408 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 field value from a register. */
74409 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
74410 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value suitable for setting the register. */
74411 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
74412 
74413 /*
74414  * Field : Mask Byte Control - mbc_1
74415  *
74416  * This array of bits are mask control bits for comparison of each of the MAC
74417  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74418  * received DA or SA with the contents of MAC Address88 high and low registers.
74419  * Each bit controls the masking of the bytes. You can filter a group of addresses
74420  * (known as group address filtering) by masking one or more bytes of the address.
74421  *
74422  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74423  *
74424  * Field Enumeration Values:
74425  *
74426  * Enum | Value | Description
74427  * :----------------------------------------------|:------|:------------------------------------
74428  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74429  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74430  *
74431  * Field Access Macros:
74432  *
74433  */
74434 /*
74435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1
74436  *
74437  * Byte is unmasked (i.e. is compared)
74438  */
74439 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED 0x0
74440 /*
74441  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1
74442  *
74443  * Byte is masked (i.e. not compared)
74444  */
74445 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED 0x1
74446 
74447 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
74448 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_LSB 25
74449 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
74450 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_MSB 25
74451 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
74452 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_WIDTH 1
74453 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */
74454 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET_MSK 0x02000000
74455 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */
74456 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_CLR_MSK 0xfdffffff
74457 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
74458 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_RESET 0x0
74459 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 field value from a register. */
74460 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
74461 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value suitable for setting the register. */
74462 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
74463 
74464 /*
74465  * Field : Mask Byte Control - mbc_2
74466  *
74467  * This array of bits are mask control bits for comparison of each of the MAC
74468  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74469  * received DA or SA with the contents of MAC Address88 high and low registers.
74470  * Each bit controls the masking of the bytes. You can filter a group of addresses
74471  * (known as group address filtering) by masking one or more bytes of the address.
74472  *
74473  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74474  *
74475  * Field Enumeration Values:
74476  *
74477  * Enum | Value | Description
74478  * :----------------------------------------------|:------|:------------------------------------
74479  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74480  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74481  *
74482  * Field Access Macros:
74483  *
74484  */
74485 /*
74486  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2
74487  *
74488  * Byte is unmasked (i.e. is compared)
74489  */
74490 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED 0x0
74491 /*
74492  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2
74493  *
74494  * Byte is masked (i.e. not compared)
74495  */
74496 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED 0x1
74497 
74498 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
74499 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_LSB 26
74500 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
74501 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_MSB 26
74502 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
74503 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_WIDTH 1
74504 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */
74505 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET_MSK 0x04000000
74506 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */
74507 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_CLR_MSK 0xfbffffff
74508 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
74509 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_RESET 0x0
74510 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 field value from a register. */
74511 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
74512 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value suitable for setting the register. */
74513 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
74514 
74515 /*
74516  * Field : Mask Byte Control - mbc_3
74517  *
74518  * This array of bits are mask control bits for comparison of each of the MAC
74519  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74520  * received DA or SA with the contents of MAC Address88 high and low registers.
74521  * Each bit controls the masking of the bytes. You can filter a group of addresses
74522  * (known as group address filtering) by masking one or more bytes of the address.
74523  *
74524  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74525  *
74526  * Field Enumeration Values:
74527  *
74528  * Enum | Value | Description
74529  * :----------------------------------------------|:------|:------------------------------------
74530  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74531  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74532  *
74533  * Field Access Macros:
74534  *
74535  */
74536 /*
74537  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3
74538  *
74539  * Byte is unmasked (i.e. is compared)
74540  */
74541 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED 0x0
74542 /*
74543  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3
74544  *
74545  * Byte is masked (i.e. not compared)
74546  */
74547 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED 0x1
74548 
74549 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
74550 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_LSB 27
74551 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
74552 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_MSB 27
74553 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
74554 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_WIDTH 1
74555 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */
74556 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET_MSK 0x08000000
74557 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */
74558 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_CLR_MSK 0xf7ffffff
74559 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
74560 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_RESET 0x0
74561 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 field value from a register. */
74562 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
74563 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value suitable for setting the register. */
74564 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
74565 
74566 /*
74567  * Field : Mask Byte Control - mbc_4
74568  *
74569  * This array of bits are mask control bits for comparison of each of the MAC
74570  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74571  * received DA or SA with the contents of MAC Address88 high and low registers.
74572  * Each bit controls the masking of the bytes. You can filter a group of addresses
74573  * (known as group address filtering) by masking one or more bytes of the address.
74574  *
74575  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74576  *
74577  * Field Enumeration Values:
74578  *
74579  * Enum | Value | Description
74580  * :----------------------------------------------|:------|:------------------------------------
74581  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74582  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74583  *
74584  * Field Access Macros:
74585  *
74586  */
74587 /*
74588  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4
74589  *
74590  * Byte is unmasked (i.e. is compared)
74591  */
74592 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED 0x0
74593 /*
74594  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4
74595  *
74596  * Byte is masked (i.e. not compared)
74597  */
74598 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED 0x1
74599 
74600 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
74601 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_LSB 28
74602 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
74603 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_MSB 28
74604 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
74605 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_WIDTH 1
74606 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */
74607 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET_MSK 0x10000000
74608 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */
74609 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_CLR_MSK 0xefffffff
74610 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
74611 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_RESET 0x0
74612 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 field value from a register. */
74613 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
74614 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value suitable for setting the register. */
74615 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
74616 
74617 /*
74618  * Field : Mask Byte Control - mbc_5
74619  *
74620  * This array of bits are mask control bits for comparison of each of the MAC
74621  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74622  * received DA or SA with the contents of MAC Address88 high and low registers.
74623  * Each bit controls the masking of the bytes. You can filter a group of addresses
74624  * (known as group address filtering) by masking one or more bytes of the address.
74625  *
74626  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74627  *
74628  * Field Enumeration Values:
74629  *
74630  * Enum | Value | Description
74631  * :----------------------------------------------|:------|:------------------------------------
74632  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74633  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74634  *
74635  * Field Access Macros:
74636  *
74637  */
74638 /*
74639  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5
74640  *
74641  * Byte is unmasked (i.e. is compared)
74642  */
74643 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED 0x0
74644 /*
74645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5
74646  *
74647  * Byte is masked (i.e. not compared)
74648  */
74649 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED 0x1
74650 
74651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
74652 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_LSB 29
74653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
74654 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_MSB 29
74655 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
74656 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_WIDTH 1
74657 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */
74658 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET_MSK 0x20000000
74659 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */
74660 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_CLR_MSK 0xdfffffff
74661 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
74662 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_RESET 0x0
74663 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 field value from a register. */
74664 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
74665 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value suitable for setting the register. */
74666 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
74667 
74668 /*
74669  * Field : Source Address - sa
74670  *
74671  * When this bit is enabled, the MAC Address88[47:0] is used to compare with the SA
74672  * fields of the received frame. When this bit is disabled, the MAC Address88[47:0]
74673  * is used to compare with the DA fields of the received frame.
74674  *
74675  * Field Enumeration Values:
74676  *
74677  * Enum | Value | Description
74678  * :----------------------------------------|:------|:-----------------------------
74679  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
74680  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END | 0x1 | MAC address compare enabled
74681  *
74682  * Field Access Macros:
74683  *
74684  */
74685 /*
74686  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA
74687  *
74688  * MAC address compare disabled
74689  */
74690 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD 0x0
74691 /*
74692  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA
74693  *
74694  * MAC address compare enabled
74695  */
74696 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END 0x1
74697 
74698 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
74699 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_LSB 30
74700 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
74701 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_MSB 30
74702 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
74703 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_WIDTH 1
74704 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */
74705 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET_MSK 0x40000000
74706 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */
74707 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_CLR_MSK 0xbfffffff
74708 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
74709 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_RESET 0x0
74710 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA field value from a register. */
74711 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
74712 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value suitable for setting the register. */
74713 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
74714 
74715 /*
74716  * Field : Address Enable - ae
74717  *
74718  * When this bit is enabled, the address filter block uses the 89th MAC address for
74719  * perfect filtering. When this bit is disabled, the address filter block ignores
74720  * the address for filtering.
74721  *
74722  * Field Enumeration Values:
74723  *
74724  * Enum | Value | Description
74725  * :----------------------------------------|:------|:--------------------------------------
74726  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
74727  * ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
74728  *
74729  * Field Access Macros:
74730  *
74731  */
74732 /*
74733  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
74734  *
74735  * Second MAC address filtering disabled
74736  */
74737 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD 0x0
74738 /*
74739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
74740  *
74741  * Second MAC address filtering enabled
74742  */
74743 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END 0x1
74744 
74745 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
74746 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_LSB 31
74747 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
74748 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_MSB 31
74749 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
74750 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_WIDTH 1
74751 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
74752 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET_MSK 0x80000000
74753 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
74754 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_CLR_MSK 0x7fffffff
74755 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
74756 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_RESET 0x0
74757 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE field value from a register. */
74758 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
74759 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value suitable for setting the register. */
74760 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
74761 
74762 #ifndef __ASSEMBLY__
74763 /*
74764  * WARNING: The C register and register group struct declarations are provided for
74765  * convenience and illustrative purposes. They should, however, be used with
74766  * caution as the C language standard provides no guarantees about the alignment or
74767  * atomicity of device memory accesses. The recommended practice for writing
74768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74769  * alt_write_word() functions.
74770  *
74771  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH.
74772  */
74773 struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s
74774 {
74775  uint32_t addrhi : 16; /* MAC Address88 [47:32] */
74776  uint32_t : 8; /* *UNDEFINED* */
74777  uint32_t mbc_0 : 1; /* Mask Byte Control */
74778  uint32_t mbc_1 : 1; /* Mask Byte Control */
74779  uint32_t mbc_2 : 1; /* Mask Byte Control */
74780  uint32_t mbc_3 : 1; /* Mask Byte Control */
74781  uint32_t mbc_4 : 1; /* Mask Byte Control */
74782  uint32_t mbc_5 : 1; /* Mask Byte Control */
74783  uint32_t sa : 1; /* Source Address */
74784  uint32_t ae : 1; /* Address Enable */
74785 };
74786 
74787 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH. */
74788 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t;
74789 #endif /* __ASSEMBLY__ */
74790 
74791 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register from the beginning of the component. */
74792 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST 0xa40
74793 /* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register. */
74794 #define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST))
74795 
74796 /*
74797  * Register : Register 657 (MAC Address88 Low Register) - MAC_Address88_Low
74798  *
74799  * The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC
74800  * address of the station.
74801  *
74802  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
74803  * format.
74804  *
74805  * Register Layout
74806  *
74807  * Bits | Access | Reset | Description
74808  * :-------|:-------|:-----------|:---------------------
74809  * [31:0] | RW | 0xffffffff | MAC Address88 [31:0]
74810  *
74811  */
74812 /*
74813  * Field : MAC Address88 [31:0] - addrlo
74814  *
74815  * This field contains the lower 32 bits of the 89th 6-byte MAC address. The
74816  * content of this field is undefined until loaded by software after the
74817  * initialization process.
74818  *
74819  * Field Access Macros:
74820  *
74821  */
74822 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
74823 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_LSB 0
74824 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
74825 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_MSB 31
74826 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
74827 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_WIDTH 32
74828 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
74829 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET_MSK 0xffffffff
74830 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
74831 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_CLR_MSK 0x00000000
74832 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
74833 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_RESET 0xffffffff
74834 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO field value from a register. */
74835 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
74836 /* Produces a ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value suitable for setting the register. */
74837 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
74838 
74839 #ifndef __ASSEMBLY__
74840 /*
74841  * WARNING: The C register and register group struct declarations are provided for
74842  * convenience and illustrative purposes. They should, however, be used with
74843  * caution as the C language standard provides no guarantees about the alignment or
74844  * atomicity of device memory accesses. The recommended practice for writing
74845  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
74846  * alt_write_word() functions.
74847  *
74848  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW.
74849  */
74850 struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s
74851 {
74852  uint32_t addrlo : 32; /* MAC Address88 [31:0] */
74853 };
74854 
74855 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW. */
74856 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s ALT_EMAC_GMAC_MAC_ADDR88_LOW_t;
74857 #endif /* __ASSEMBLY__ */
74858 
74859 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register from the beginning of the component. */
74860 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST 0xa44
74861 /* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register. */
74862 #define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST))
74863 
74864 /*
74865  * Register : Register 658 (MAC Address89 High Register) - MAC_Address89_High
74866  *
74867  * The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC
74868  * address of the station. Because the MAC address registers are configured to be
74869  * double-synchronized to the (G)MII clock domains, the synchronization is
74870  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
74871  * endian mode) of the MAC Address89 Low Register are written. For proper
74872  * synchronization updates, the consecutive writes to this Address Low Register
74873  * should be performed after at least four clock cycles in the destination clock
74874  * domain.
74875  *
74876  * Note that all MAC Address High registers (except MAC Address0 High) have the
74877  * same format.
74878  *
74879  * Register Layout
74880  *
74881  * Bits | Access | Reset | Description
74882  * :--------|:-------|:-------|:----------------------
74883  * [15:0] | RW | 0xffff | MAC Address89 [47:32]
74884  * [23:16] | ??? | 0x0 | *UNDEFINED*
74885  * [24] | RW | 0x0 | Mask Byte Control
74886  * [25] | RW | 0x0 | Mask Byte Control
74887  * [26] | RW | 0x0 | Mask Byte Control
74888  * [27] | RW | 0x0 | Mask Byte Control
74889  * [28] | RW | 0x0 | Mask Byte Control
74890  * [29] | RW | 0x0 | Mask Byte Control
74891  * [30] | RW | 0x0 | Source Address
74892  * [31] | RW | 0x0 | Address Enable
74893  *
74894  */
74895 /*
74896  * Field : MAC Address89 [47:32] - addrhi
74897  *
74898  * This field contains the upper 16 bits (47:32) of the 90th 6-byte MAC address.
74899  *
74900  * Field Access Macros:
74901  *
74902  */
74903 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
74904 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_LSB 0
74905 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
74906 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_MSB 15
74907 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
74908 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_WIDTH 16
74909 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
74910 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET_MSK 0x0000ffff
74911 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
74912 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_CLR_MSK 0xffff0000
74913 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
74914 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_RESET 0xffff
74915 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI field value from a register. */
74916 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
74917 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value suitable for setting the register. */
74918 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
74919 
74920 /*
74921  * Field : Mask Byte Control - mbc_0
74922  *
74923  * This array of bits are mask control bits for comparison of each of the MAC
74924  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74925  * received DA or SA with the contents of MAC Address89 high and low registers.
74926  * Each bit controls the masking of the bytes. You can filter a group of addresses
74927  * (known as group address filtering) by masking one or more bytes of the address.
74928  *
74929  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74930  *
74931  * Field Enumeration Values:
74932  *
74933  * Enum | Value | Description
74934  * :----------------------------------------------|:------|:------------------------------------
74935  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74936  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74937  *
74938  * Field Access Macros:
74939  *
74940  */
74941 /*
74942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0
74943  *
74944  * Byte is unmasked (i.e. is compared)
74945  */
74946 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED 0x0
74947 /*
74948  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0
74949  *
74950  * Byte is masked (i.e. not compared)
74951  */
74952 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED 0x1
74953 
74954 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
74955 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_LSB 24
74956 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
74957 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_MSB 24
74958 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
74959 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_WIDTH 1
74960 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */
74961 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET_MSK 0x01000000
74962 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */
74963 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_CLR_MSK 0xfeffffff
74964 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
74965 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_RESET 0x0
74966 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 field value from a register. */
74967 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
74968 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value suitable for setting the register. */
74969 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
74970 
74971 /*
74972  * Field : Mask Byte Control - mbc_1
74973  *
74974  * This array of bits are mask control bits for comparison of each of the MAC
74975  * Address bytes. When masked, the MAC does not compare the corresponding byte of
74976  * received DA or SA with the contents of MAC Address89 high and low registers.
74977  * Each bit controls the masking of the bytes. You can filter a group of addresses
74978  * (known as group address filtering) by masking one or more bytes of the address.
74979  *
74980  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
74981  *
74982  * Field Enumeration Values:
74983  *
74984  * Enum | Value | Description
74985  * :----------------------------------------------|:------|:------------------------------------
74986  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
74987  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
74988  *
74989  * Field Access Macros:
74990  *
74991  */
74992 /*
74993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1
74994  *
74995  * Byte is unmasked (i.e. is compared)
74996  */
74997 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED 0x0
74998 /*
74999  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1
75000  *
75001  * Byte is masked (i.e. not compared)
75002  */
75003 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED 0x1
75004 
75005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
75006 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_LSB 25
75007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
75008 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_MSB 25
75009 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
75010 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_WIDTH 1
75011 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */
75012 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET_MSK 0x02000000
75013 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */
75014 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_CLR_MSK 0xfdffffff
75015 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
75016 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_RESET 0x0
75017 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 field value from a register. */
75018 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
75019 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value suitable for setting the register. */
75020 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
75021 
75022 /*
75023  * Field : Mask Byte Control - mbc_2
75024  *
75025  * This array of bits are mask control bits for comparison of each of the MAC
75026  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75027  * received DA or SA with the contents of MAC Address89 high and low registers.
75028  * Each bit controls the masking of the bytes. You can filter a group of addresses
75029  * (known as group address filtering) by masking one or more bytes of the address.
75030  *
75031  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75032  *
75033  * Field Enumeration Values:
75034  *
75035  * Enum | Value | Description
75036  * :----------------------------------------------|:------|:------------------------------------
75037  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75038  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75039  *
75040  * Field Access Macros:
75041  *
75042  */
75043 /*
75044  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2
75045  *
75046  * Byte is unmasked (i.e. is compared)
75047  */
75048 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED 0x0
75049 /*
75050  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2
75051  *
75052  * Byte is masked (i.e. not compared)
75053  */
75054 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED 0x1
75055 
75056 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
75057 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_LSB 26
75058 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
75059 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_MSB 26
75060 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
75061 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_WIDTH 1
75062 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */
75063 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET_MSK 0x04000000
75064 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */
75065 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_CLR_MSK 0xfbffffff
75066 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
75067 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_RESET 0x0
75068 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 field value from a register. */
75069 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
75070 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value suitable for setting the register. */
75071 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
75072 
75073 /*
75074  * Field : Mask Byte Control - mbc_3
75075  *
75076  * This array of bits are mask control bits for comparison of each of the MAC
75077  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75078  * received DA or SA with the contents of MAC Address89 high and low registers.
75079  * Each bit controls the masking of the bytes. You can filter a group of addresses
75080  * (known as group address filtering) by masking one or more bytes of the address.
75081  *
75082  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75083  *
75084  * Field Enumeration Values:
75085  *
75086  * Enum | Value | Description
75087  * :----------------------------------------------|:------|:------------------------------------
75088  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75089  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75090  *
75091  * Field Access Macros:
75092  *
75093  */
75094 /*
75095  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3
75096  *
75097  * Byte is unmasked (i.e. is compared)
75098  */
75099 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED 0x0
75100 /*
75101  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3
75102  *
75103  * Byte is masked (i.e. not compared)
75104  */
75105 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED 0x1
75106 
75107 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
75108 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_LSB 27
75109 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
75110 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_MSB 27
75111 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
75112 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_WIDTH 1
75113 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */
75114 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET_MSK 0x08000000
75115 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */
75116 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_CLR_MSK 0xf7ffffff
75117 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
75118 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_RESET 0x0
75119 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 field value from a register. */
75120 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
75121 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value suitable for setting the register. */
75122 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
75123 
75124 /*
75125  * Field : Mask Byte Control - mbc_4
75126  *
75127  * This array of bits are mask control bits for comparison of each of the MAC
75128  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75129  * received DA or SA with the contents of MAC Address89 high and low registers.
75130  * Each bit controls the masking of the bytes. You can filter a group of addresses
75131  * (known as group address filtering) by masking one or more bytes of the address.
75132  *
75133  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75134  *
75135  * Field Enumeration Values:
75136  *
75137  * Enum | Value | Description
75138  * :----------------------------------------------|:------|:------------------------------------
75139  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75140  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75141  *
75142  * Field Access Macros:
75143  *
75144  */
75145 /*
75146  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4
75147  *
75148  * Byte is unmasked (i.e. is compared)
75149  */
75150 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED 0x0
75151 /*
75152  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4
75153  *
75154  * Byte is masked (i.e. not compared)
75155  */
75156 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED 0x1
75157 
75158 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
75159 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_LSB 28
75160 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
75161 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_MSB 28
75162 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
75163 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_WIDTH 1
75164 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */
75165 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET_MSK 0x10000000
75166 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */
75167 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_CLR_MSK 0xefffffff
75168 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
75169 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_RESET 0x0
75170 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 field value from a register. */
75171 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
75172 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value suitable for setting the register. */
75173 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
75174 
75175 /*
75176  * Field : Mask Byte Control - mbc_5
75177  *
75178  * This array of bits are mask control bits for comparison of each of the MAC
75179  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75180  * received DA or SA with the contents of MAC Address89 high and low registers.
75181  * Each bit controls the masking of the bytes. You can filter a group of addresses
75182  * (known as group address filtering) by masking one or more bytes of the address.
75183  *
75184  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75185  *
75186  * Field Enumeration Values:
75187  *
75188  * Enum | Value | Description
75189  * :----------------------------------------------|:------|:------------------------------------
75190  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75191  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75192  *
75193  * Field Access Macros:
75194  *
75195  */
75196 /*
75197  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5
75198  *
75199  * Byte is unmasked (i.e. is compared)
75200  */
75201 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED 0x0
75202 /*
75203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5
75204  *
75205  * Byte is masked (i.e. not compared)
75206  */
75207 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED 0x1
75208 
75209 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
75210 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_LSB 29
75211 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
75212 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_MSB 29
75213 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
75214 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_WIDTH 1
75215 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */
75216 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET_MSK 0x20000000
75217 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */
75218 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_CLR_MSK 0xdfffffff
75219 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
75220 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_RESET 0x0
75221 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 field value from a register. */
75222 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
75223 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value suitable for setting the register. */
75224 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
75225 
75226 /*
75227  * Field : Source Address - sa
75228  *
75229  * When this bit is enabled, the MAC Address89[47:0] is used to compare with the SA
75230  * fields of the received frame. When this bit is disabled, the MAC Address89[47:0]
75231  * is used to compare with the DA fields of the received frame.
75232  *
75233  * Field Enumeration Values:
75234  *
75235  * Enum | Value | Description
75236  * :----------------------------------------|:------|:-----------------------------
75237  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
75238  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END | 0x1 | MAC address compare enabled
75239  *
75240  * Field Access Macros:
75241  *
75242  */
75243 /*
75244  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA
75245  *
75246  * MAC address compare disabled
75247  */
75248 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD 0x0
75249 /*
75250  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA
75251  *
75252  * MAC address compare enabled
75253  */
75254 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END 0x1
75255 
75256 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
75257 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_LSB 30
75258 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
75259 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_MSB 30
75260 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
75261 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_WIDTH 1
75262 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */
75263 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET_MSK 0x40000000
75264 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */
75265 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_CLR_MSK 0xbfffffff
75266 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
75267 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_RESET 0x0
75268 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA field value from a register. */
75269 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
75270 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value suitable for setting the register. */
75271 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
75272 
75273 /*
75274  * Field : Address Enable - ae
75275  *
75276  * When this bit is enabled, the address filter block uses the 90th MAC address for
75277  * perfect filtering. When this bit is disabled, the address filter block ignores
75278  * the address for filtering.
75279  *
75280  * Field Enumeration Values:
75281  *
75282  * Enum | Value | Description
75283  * :----------------------------------------|:------|:--------------------------------------
75284  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
75285  * ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
75286  *
75287  * Field Access Macros:
75288  *
75289  */
75290 /*
75291  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
75292  *
75293  * Second MAC address filtering disabled
75294  */
75295 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD 0x0
75296 /*
75297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
75298  *
75299  * Second MAC address filtering enabled
75300  */
75301 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END 0x1
75302 
75303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
75304 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_LSB 31
75305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
75306 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_MSB 31
75307 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
75308 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_WIDTH 1
75309 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
75310 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET_MSK 0x80000000
75311 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
75312 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_CLR_MSK 0x7fffffff
75313 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
75314 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_RESET 0x0
75315 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE field value from a register. */
75316 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
75317 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value suitable for setting the register. */
75318 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
75319 
75320 #ifndef __ASSEMBLY__
75321 /*
75322  * WARNING: The C register and register group struct declarations are provided for
75323  * convenience and illustrative purposes. They should, however, be used with
75324  * caution as the C language standard provides no guarantees about the alignment or
75325  * atomicity of device memory accesses. The recommended practice for writing
75326  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
75327  * alt_write_word() functions.
75328  *
75329  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH.
75330  */
75331 struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s
75332 {
75333  uint32_t addrhi : 16; /* MAC Address89 [47:32] */
75334  uint32_t : 8; /* *UNDEFINED* */
75335  uint32_t mbc_0 : 1; /* Mask Byte Control */
75336  uint32_t mbc_1 : 1; /* Mask Byte Control */
75337  uint32_t mbc_2 : 1; /* Mask Byte Control */
75338  uint32_t mbc_3 : 1; /* Mask Byte Control */
75339  uint32_t mbc_4 : 1; /* Mask Byte Control */
75340  uint32_t mbc_5 : 1; /* Mask Byte Control */
75341  uint32_t sa : 1; /* Source Address */
75342  uint32_t ae : 1; /* Address Enable */
75343 };
75344 
75345 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH. */
75346 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t;
75347 #endif /* __ASSEMBLY__ */
75348 
75349 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register from the beginning of the component. */
75350 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST 0xa48
75351 /* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register. */
75352 #define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST))
75353 
75354 /*
75355  * Register : Register 659 (MAC Address89 Low Register) - MAC_Address89_Low
75356  *
75357  * The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC
75358  * address of the station.
75359  *
75360  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
75361  * format.
75362  *
75363  * Register Layout
75364  *
75365  * Bits | Access | Reset | Description
75366  * :-------|:-------|:-----------|:---------------------
75367  * [31:0] | RW | 0xffffffff | MAC Address89 [31:0]
75368  *
75369  */
75370 /*
75371  * Field : MAC Address89 [31:0] - addrlo
75372  *
75373  * This field contains the lower 32 bits of the 90th 6-byte MAC address. The
75374  * content of this field is undefined until loaded by software after the
75375  * initialization process.
75376  *
75377  * Field Access Macros:
75378  *
75379  */
75380 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
75381 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_LSB 0
75382 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
75383 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_MSB 31
75384 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
75385 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_WIDTH 32
75386 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
75387 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET_MSK 0xffffffff
75388 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
75389 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_CLR_MSK 0x00000000
75390 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
75391 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_RESET 0xffffffff
75392 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO field value from a register. */
75393 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
75394 /* Produces a ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value suitable for setting the register. */
75395 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
75396 
75397 #ifndef __ASSEMBLY__
75398 /*
75399  * WARNING: The C register and register group struct declarations are provided for
75400  * convenience and illustrative purposes. They should, however, be used with
75401  * caution as the C language standard provides no guarantees about the alignment or
75402  * atomicity of device memory accesses. The recommended practice for writing
75403  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
75404  * alt_write_word() functions.
75405  *
75406  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW.
75407  */
75408 struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s
75409 {
75410  uint32_t addrlo : 32; /* MAC Address89 [31:0] */
75411 };
75412 
75413 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW. */
75414 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s ALT_EMAC_GMAC_MAC_ADDR89_LOW_t;
75415 #endif /* __ASSEMBLY__ */
75416 
75417 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register from the beginning of the component. */
75418 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST 0xa4c
75419 /* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register. */
75420 #define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST))
75421 
75422 /*
75423  * Register : Register 660 (MAC Address90 High Register) - MAC_Address90_High
75424  *
75425  * The MAC Address90 High register holds the upper 16 bits of the 91th 6-byte MAC
75426  * address of the station. Because the MAC address registers are configured to be
75427  * double-synchronized to the (G)MII clock domains, the synchronization is
75428  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
75429  * endian mode) of the MAC Address90 Low Register are written. For proper
75430  * synchronization updates, the consecutive writes to this Address Low Register
75431  * should be performed after at least four clock cycles in the destination clock
75432  * domain.
75433  *
75434  * Note that all MAC Address High registers (except MAC Address0 High) have the
75435  * same format.
75436  *
75437  * Register Layout
75438  *
75439  * Bits | Access | Reset | Description
75440  * :--------|:-------|:-------|:----------------------
75441  * [15:0] | RW | 0xffff | MAC Address90 [47:32]
75442  * [23:16] | ??? | 0x0 | *UNDEFINED*
75443  * [24] | RW | 0x0 | Mask Byte Control
75444  * [25] | RW | 0x0 | Mask Byte Control
75445  * [26] | RW | 0x0 | Mask Byte Control
75446  * [27] | RW | 0x0 | Mask Byte Control
75447  * [28] | RW | 0x0 | Mask Byte Control
75448  * [29] | RW | 0x0 | Mask Byte Control
75449  * [30] | RW | 0x0 | Source Address
75450  * [31] | RW | 0x0 | Address Enable
75451  *
75452  */
75453 /*
75454  * Field : MAC Address90 [47:32] - addrhi
75455  *
75456  * This field contains the upper 16 bits (47:32) of the 91th 6-byte MAC address.
75457  *
75458  * Field Access Macros:
75459  *
75460  */
75461 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
75462 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_LSB 0
75463 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
75464 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_MSB 15
75465 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
75466 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_WIDTH 16
75467 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
75468 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET_MSK 0x0000ffff
75469 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
75470 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_CLR_MSK 0xffff0000
75471 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
75472 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_RESET 0xffff
75473 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI field value from a register. */
75474 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
75475 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value suitable for setting the register. */
75476 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
75477 
75478 /*
75479  * Field : Mask Byte Control - mbc_0
75480  *
75481  * This array of bits are mask control bits for comparison of each of the MAC
75482  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75483  * received DA or SA with the contents of MAC Address90 high and low registers.
75484  * Each bit controls the masking of the bytes. You can filter a group of addresses
75485  * (known as group address filtering) by masking one or more bytes of the address.
75486  *
75487  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75488  *
75489  * Field Enumeration Values:
75490  *
75491  * Enum | Value | Description
75492  * :----------------------------------------------|:------|:------------------------------------
75493  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75494  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75495  *
75496  * Field Access Macros:
75497  *
75498  */
75499 /*
75500  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0
75501  *
75502  * Byte is unmasked (i.e. is compared)
75503  */
75504 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED 0x0
75505 /*
75506  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0
75507  *
75508  * Byte is masked (i.e. not compared)
75509  */
75510 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED 0x1
75511 
75512 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
75513 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_LSB 24
75514 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
75515 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_MSB 24
75516 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
75517 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_WIDTH 1
75518 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */
75519 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET_MSK 0x01000000
75520 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */
75521 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_CLR_MSK 0xfeffffff
75522 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
75523 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_RESET 0x0
75524 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 field value from a register. */
75525 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
75526 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value suitable for setting the register. */
75527 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
75528 
75529 /*
75530  * Field : Mask Byte Control - mbc_1
75531  *
75532  * This array of bits are mask control bits for comparison of each of the MAC
75533  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75534  * received DA or SA with the contents of MAC Address90 high and low registers.
75535  * Each bit controls the masking of the bytes. You can filter a group of addresses
75536  * (known as group address filtering) by masking one or more bytes of the address.
75537  *
75538  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75539  *
75540  * Field Enumeration Values:
75541  *
75542  * Enum | Value | Description
75543  * :----------------------------------------------|:------|:------------------------------------
75544  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75545  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75546  *
75547  * Field Access Macros:
75548  *
75549  */
75550 /*
75551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1
75552  *
75553  * Byte is unmasked (i.e. is compared)
75554  */
75555 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED 0x0
75556 /*
75557  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1
75558  *
75559  * Byte is masked (i.e. not compared)
75560  */
75561 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED 0x1
75562 
75563 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
75564 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_LSB 25
75565 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
75566 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_MSB 25
75567 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
75568 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_WIDTH 1
75569 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */
75570 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET_MSK 0x02000000
75571 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */
75572 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_CLR_MSK 0xfdffffff
75573 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
75574 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_RESET 0x0
75575 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 field value from a register. */
75576 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
75577 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value suitable for setting the register. */
75578 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
75579 
75580 /*
75581  * Field : Mask Byte Control - mbc_2
75582  *
75583  * This array of bits are mask control bits for comparison of each of the MAC
75584  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75585  * received DA or SA with the contents of MAC Address90 high and low registers.
75586  * Each bit controls the masking of the bytes. You can filter a group of addresses
75587  * (known as group address filtering) by masking one or more bytes of the address.
75588  *
75589  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75590  *
75591  * Field Enumeration Values:
75592  *
75593  * Enum | Value | Description
75594  * :----------------------------------------------|:------|:------------------------------------
75595  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75596  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75597  *
75598  * Field Access Macros:
75599  *
75600  */
75601 /*
75602  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2
75603  *
75604  * Byte is unmasked (i.e. is compared)
75605  */
75606 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED 0x0
75607 /*
75608  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2
75609  *
75610  * Byte is masked (i.e. not compared)
75611  */
75612 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED 0x1
75613 
75614 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
75615 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_LSB 26
75616 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
75617 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_MSB 26
75618 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
75619 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_WIDTH 1
75620 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */
75621 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET_MSK 0x04000000
75622 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */
75623 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_CLR_MSK 0xfbffffff
75624 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
75625 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_RESET 0x0
75626 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 field value from a register. */
75627 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
75628 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value suitable for setting the register. */
75629 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
75630 
75631 /*
75632  * Field : Mask Byte Control - mbc_3
75633  *
75634  * This array of bits are mask control bits for comparison of each of the MAC
75635  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75636  * received DA or SA with the contents of MAC Address90 high and low registers.
75637  * Each bit controls the masking of the bytes. You can filter a group of addresses
75638  * (known as group address filtering) by masking one or more bytes of the address.
75639  *
75640  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75641  *
75642  * Field Enumeration Values:
75643  *
75644  * Enum | Value | Description
75645  * :----------------------------------------------|:------|:------------------------------------
75646  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75647  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75648  *
75649  * Field Access Macros:
75650  *
75651  */
75652 /*
75653  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3
75654  *
75655  * Byte is unmasked (i.e. is compared)
75656  */
75657 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED 0x0
75658 /*
75659  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3
75660  *
75661  * Byte is masked (i.e. not compared)
75662  */
75663 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED 0x1
75664 
75665 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
75666 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_LSB 27
75667 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
75668 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_MSB 27
75669 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
75670 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_WIDTH 1
75671 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */
75672 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET_MSK 0x08000000
75673 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */
75674 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_CLR_MSK 0xf7ffffff
75675 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
75676 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_RESET 0x0
75677 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 field value from a register. */
75678 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
75679 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value suitable for setting the register. */
75680 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
75681 
75682 /*
75683  * Field : Mask Byte Control - mbc_4
75684  *
75685  * This array of bits are mask control bits for comparison of each of the MAC
75686  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75687  * received DA or SA with the contents of MAC Address90 high and low registers.
75688  * Each bit controls the masking of the bytes. You can filter a group of addresses
75689  * (known as group address filtering) by masking one or more bytes of the address.
75690  *
75691  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75692  *
75693  * Field Enumeration Values:
75694  *
75695  * Enum | Value | Description
75696  * :----------------------------------------------|:------|:------------------------------------
75697  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75698  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75699  *
75700  * Field Access Macros:
75701  *
75702  */
75703 /*
75704  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4
75705  *
75706  * Byte is unmasked (i.e. is compared)
75707  */
75708 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED 0x0
75709 /*
75710  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4
75711  *
75712  * Byte is masked (i.e. not compared)
75713  */
75714 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED 0x1
75715 
75716 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
75717 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_LSB 28
75718 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
75719 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_MSB 28
75720 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
75721 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_WIDTH 1
75722 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */
75723 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET_MSK 0x10000000
75724 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */
75725 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_CLR_MSK 0xefffffff
75726 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
75727 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_RESET 0x0
75728 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 field value from a register. */
75729 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
75730 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value suitable for setting the register. */
75731 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
75732 
75733 /*
75734  * Field : Mask Byte Control - mbc_5
75735  *
75736  * This array of bits are mask control bits for comparison of each of the MAC
75737  * Address bytes. When masked, the MAC does not compare the corresponding byte of
75738  * received DA or SA with the contents of MAC Address90 high and low registers.
75739  * Each bit controls the masking of the bytes. You can filter a group of addresses
75740  * (known as group address filtering) by masking one or more bytes of the address.
75741  *
75742  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
75743  *
75744  * Field Enumeration Values:
75745  *
75746  * Enum | Value | Description
75747  * :----------------------------------------------|:------|:------------------------------------
75748  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
75749  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
75750  *
75751  * Field Access Macros:
75752  *
75753  */
75754 /*
75755  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5
75756  *
75757  * Byte is unmasked (i.e. is compared)
75758  */
75759 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED 0x0
75760 /*
75761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5
75762  *
75763  * Byte is masked (i.e. not compared)
75764  */
75765 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED 0x1
75766 
75767 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
75768 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_LSB 29
75769 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
75770 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_MSB 29
75771 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
75772 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_WIDTH 1
75773 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */
75774 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET_MSK 0x20000000
75775 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */
75776 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_CLR_MSK 0xdfffffff
75777 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
75778 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_RESET 0x0
75779 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 field value from a register. */
75780 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
75781 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value suitable for setting the register. */
75782 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
75783 
75784 /*
75785  * Field : Source Address - sa
75786  *
75787  * When this bit is enabled, the MAC Address90[47:0] is used to compare with the SA
75788  * fields of the received frame. When this bit is disabled, the MAC Address90[47:0]
75789  * is used to compare with the DA fields of the received frame.
75790  *
75791  * Field Enumeration Values:
75792  *
75793  * Enum | Value | Description
75794  * :----------------------------------------|:------|:-----------------------------
75795  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
75796  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END | 0x1 | MAC address compare enabled
75797  *
75798  * Field Access Macros:
75799  *
75800  */
75801 /*
75802  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA
75803  *
75804  * MAC address compare disabled
75805  */
75806 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD 0x0
75807 /*
75808  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA
75809  *
75810  * MAC address compare enabled
75811  */
75812 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END 0x1
75813 
75814 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
75815 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_LSB 30
75816 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
75817 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_MSB 30
75818 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
75819 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_WIDTH 1
75820 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */
75821 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET_MSK 0x40000000
75822 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */
75823 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_CLR_MSK 0xbfffffff
75824 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
75825 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_RESET 0x0
75826 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA field value from a register. */
75827 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
75828 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value suitable for setting the register. */
75829 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
75830 
75831 /*
75832  * Field : Address Enable - ae
75833  *
75834  * When this bit is enabled, the address filter block uses the 91th MAC address for
75835  * perfect filtering. When this bit is disabled, the address filter block ignores
75836  * the address for filtering.
75837  *
75838  * Field Enumeration Values:
75839  *
75840  * Enum | Value | Description
75841  * :----------------------------------------|:------|:--------------------------------------
75842  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
75843  * ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
75844  *
75845  * Field Access Macros:
75846  *
75847  */
75848 /*
75849  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
75850  *
75851  * Second MAC address filtering disabled
75852  */
75853 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD 0x0
75854 /*
75855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
75856  *
75857  * Second MAC address filtering enabled
75858  */
75859 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END 0x1
75860 
75861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
75862 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_LSB 31
75863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
75864 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_MSB 31
75865 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
75866 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_WIDTH 1
75867 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
75868 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET_MSK 0x80000000
75869 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
75870 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_CLR_MSK 0x7fffffff
75871 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
75872 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_RESET 0x0
75873 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE field value from a register. */
75874 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
75875 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value suitable for setting the register. */
75876 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
75877 
75878 #ifndef __ASSEMBLY__
75879 /*
75880  * WARNING: The C register and register group struct declarations are provided for
75881  * convenience and illustrative purposes. They should, however, be used with
75882  * caution as the C language standard provides no guarantees about the alignment or
75883  * atomicity of device memory accesses. The recommended practice for writing
75884  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
75885  * alt_write_word() functions.
75886  *
75887  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH.
75888  */
75889 struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s
75890 {
75891  uint32_t addrhi : 16; /* MAC Address90 [47:32] */
75892  uint32_t : 8; /* *UNDEFINED* */
75893  uint32_t mbc_0 : 1; /* Mask Byte Control */
75894  uint32_t mbc_1 : 1; /* Mask Byte Control */
75895  uint32_t mbc_2 : 1; /* Mask Byte Control */
75896  uint32_t mbc_3 : 1; /* Mask Byte Control */
75897  uint32_t mbc_4 : 1; /* Mask Byte Control */
75898  uint32_t mbc_5 : 1; /* Mask Byte Control */
75899  uint32_t sa : 1; /* Source Address */
75900  uint32_t ae : 1; /* Address Enable */
75901 };
75902 
75903 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH. */
75904 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t;
75905 #endif /* __ASSEMBLY__ */
75906 
75907 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register from the beginning of the component. */
75908 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST 0xa50
75909 /* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register. */
75910 #define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST))
75911 
75912 /*
75913  * Register : Register 661 (MAC Address90 Low Register) - MAC_Address90_Low
75914  *
75915  * The MAC Address90 Low register holds the lower 32 bits of the 91th 6-byte MAC
75916  * address of the station.
75917  *
75918  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
75919  * format.
75920  *
75921  * Register Layout
75922  *
75923  * Bits | Access | Reset | Description
75924  * :-------|:-------|:-----------|:---------------------
75925  * [31:0] | RW | 0xffffffff | MAC Address90 [31:0]
75926  *
75927  */
75928 /*
75929  * Field : MAC Address90 [31:0] - addrlo
75930  *
75931  * This field contains the lower 32 bits of the 91th 6-byte MAC address. The
75932  * content of this field is undefined until loaded by software after the
75933  * initialization process.
75934  *
75935  * Field Access Macros:
75936  *
75937  */
75938 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
75939 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_LSB 0
75940 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
75941 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_MSB 31
75942 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
75943 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_WIDTH 32
75944 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
75945 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET_MSK 0xffffffff
75946 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
75947 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_CLR_MSK 0x00000000
75948 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
75949 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_RESET 0xffffffff
75950 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO field value from a register. */
75951 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
75952 /* Produces a ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value suitable for setting the register. */
75953 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
75954 
75955 #ifndef __ASSEMBLY__
75956 /*
75957  * WARNING: The C register and register group struct declarations are provided for
75958  * convenience and illustrative purposes. They should, however, be used with
75959  * caution as the C language standard provides no guarantees about the alignment or
75960  * atomicity of device memory accesses. The recommended practice for writing
75961  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
75962  * alt_write_word() functions.
75963  *
75964  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW.
75965  */
75966 struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s
75967 {
75968  uint32_t addrlo : 32; /* MAC Address90 [31:0] */
75969 };
75970 
75971 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW. */
75972 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s ALT_EMAC_GMAC_MAC_ADDR90_LOW_t;
75973 #endif /* __ASSEMBLY__ */
75974 
75975 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register from the beginning of the component. */
75976 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST 0xa54
75977 /* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register. */
75978 #define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST))
75979 
75980 /*
75981  * Register : Register 662 (MAC Address91 High Register) - MAC_Address91_High
75982  *
75983  * The MAC Address91 High register holds the upper 16 bits of the 92th 6-byte MAC
75984  * address of the station. Because the MAC address registers are configured to be
75985  * double-synchronized to the (G)MII clock domains, the synchronization is
75986  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
75987  * endian mode) of the MAC Address91 Low Register are written. For proper
75988  * synchronization updates, the consecutive writes to this Address Low Register
75989  * should be performed after at least four clock cycles in the destination clock
75990  * domain.
75991  *
75992  * Note that all MAC Address High registers (except MAC Address0 High) have the
75993  * same format.
75994  *
75995  * Register Layout
75996  *
75997  * Bits | Access | Reset | Description
75998  * :--------|:-------|:-------|:----------------------
75999  * [15:0] | RW | 0xffff | MAC Address91 [47:32]
76000  * [23:16] | ??? | 0x0 | *UNDEFINED*
76001  * [24] | RW | 0x0 | Mask Byte Control
76002  * [25] | RW | 0x0 | Mask Byte Control
76003  * [26] | RW | 0x0 | Mask Byte Control
76004  * [27] | RW | 0x0 | Mask Byte Control
76005  * [28] | RW | 0x0 | Mask Byte Control
76006  * [29] | RW | 0x0 | Mask Byte Control
76007  * [30] | RW | 0x0 | Source Address
76008  * [31] | RW | 0x0 | Address Enable
76009  *
76010  */
76011 /*
76012  * Field : MAC Address91 [47:32] - addrhi
76013  *
76014  * This field contains the upper 16 bits (47:32) of the 92th 6-byte MAC address.
76015  *
76016  * Field Access Macros:
76017  *
76018  */
76019 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
76020 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_LSB 0
76021 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
76022 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_MSB 15
76023 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
76024 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_WIDTH 16
76025 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
76026 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET_MSK 0x0000ffff
76027 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
76028 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_CLR_MSK 0xffff0000
76029 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
76030 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_RESET 0xffff
76031 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI field value from a register. */
76032 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
76033 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value suitable for setting the register. */
76034 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
76035 
76036 /*
76037  * Field : Mask Byte Control - mbc_0
76038  *
76039  * This array of bits are mask control bits for comparison of each of the MAC
76040  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76041  * received DA or SA with the contents of MAC Address91 high and low registers.
76042  * Each bit controls the masking of the bytes. You can filter a group of addresses
76043  * (known as group address filtering) by masking one or more bytes of the address.
76044  *
76045  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76046  *
76047  * Field Enumeration Values:
76048  *
76049  * Enum | Value | Description
76050  * :----------------------------------------------|:------|:------------------------------------
76051  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76052  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76053  *
76054  * Field Access Macros:
76055  *
76056  */
76057 /*
76058  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0
76059  *
76060  * Byte is unmasked (i.e. is compared)
76061  */
76062 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED 0x0
76063 /*
76064  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0
76065  *
76066  * Byte is masked (i.e. not compared)
76067  */
76068 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED 0x1
76069 
76070 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
76071 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_LSB 24
76072 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
76073 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_MSB 24
76074 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
76075 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_WIDTH 1
76076 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */
76077 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET_MSK 0x01000000
76078 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */
76079 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_CLR_MSK 0xfeffffff
76080 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
76081 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_RESET 0x0
76082 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 field value from a register. */
76083 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
76084 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value suitable for setting the register. */
76085 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
76086 
76087 /*
76088  * Field : Mask Byte Control - mbc_1
76089  *
76090  * This array of bits are mask control bits for comparison of each of the MAC
76091  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76092  * received DA or SA with the contents of MAC Address91 high and low registers.
76093  * Each bit controls the masking of the bytes. You can filter a group of addresses
76094  * (known as group address filtering) by masking one or more bytes of the address.
76095  *
76096  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76097  *
76098  * Field Enumeration Values:
76099  *
76100  * Enum | Value | Description
76101  * :----------------------------------------------|:------|:------------------------------------
76102  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76103  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76104  *
76105  * Field Access Macros:
76106  *
76107  */
76108 /*
76109  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1
76110  *
76111  * Byte is unmasked (i.e. is compared)
76112  */
76113 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED 0x0
76114 /*
76115  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1
76116  *
76117  * Byte is masked (i.e. not compared)
76118  */
76119 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED 0x1
76120 
76121 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
76122 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_LSB 25
76123 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
76124 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_MSB 25
76125 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
76126 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_WIDTH 1
76127 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */
76128 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET_MSK 0x02000000
76129 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */
76130 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_CLR_MSK 0xfdffffff
76131 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
76132 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_RESET 0x0
76133 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 field value from a register. */
76134 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
76135 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value suitable for setting the register. */
76136 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
76137 
76138 /*
76139  * Field : Mask Byte Control - mbc_2
76140  *
76141  * This array of bits are mask control bits for comparison of each of the MAC
76142  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76143  * received DA or SA with the contents of MAC Address91 high and low registers.
76144  * Each bit controls the masking of the bytes. You can filter a group of addresses
76145  * (known as group address filtering) by masking one or more bytes of the address.
76146  *
76147  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76148  *
76149  * Field Enumeration Values:
76150  *
76151  * Enum | Value | Description
76152  * :----------------------------------------------|:------|:------------------------------------
76153  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76154  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76155  *
76156  * Field Access Macros:
76157  *
76158  */
76159 /*
76160  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2
76161  *
76162  * Byte is unmasked (i.e. is compared)
76163  */
76164 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED 0x0
76165 /*
76166  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2
76167  *
76168  * Byte is masked (i.e. not compared)
76169  */
76170 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED 0x1
76171 
76172 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
76173 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_LSB 26
76174 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
76175 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_MSB 26
76176 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
76177 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_WIDTH 1
76178 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */
76179 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET_MSK 0x04000000
76180 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */
76181 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_CLR_MSK 0xfbffffff
76182 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
76183 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_RESET 0x0
76184 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 field value from a register. */
76185 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
76186 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value suitable for setting the register. */
76187 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
76188 
76189 /*
76190  * Field : Mask Byte Control - mbc_3
76191  *
76192  * This array of bits are mask control bits for comparison of each of the MAC
76193  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76194  * received DA or SA with the contents of MAC Address91 high and low registers.
76195  * Each bit controls the masking of the bytes. You can filter a group of addresses
76196  * (known as group address filtering) by masking one or more bytes of the address.
76197  *
76198  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76199  *
76200  * Field Enumeration Values:
76201  *
76202  * Enum | Value | Description
76203  * :----------------------------------------------|:------|:------------------------------------
76204  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76205  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76206  *
76207  * Field Access Macros:
76208  *
76209  */
76210 /*
76211  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3
76212  *
76213  * Byte is unmasked (i.e. is compared)
76214  */
76215 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED 0x0
76216 /*
76217  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3
76218  *
76219  * Byte is masked (i.e. not compared)
76220  */
76221 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED 0x1
76222 
76223 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
76224 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_LSB 27
76225 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
76226 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_MSB 27
76227 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
76228 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_WIDTH 1
76229 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */
76230 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET_MSK 0x08000000
76231 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */
76232 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_CLR_MSK 0xf7ffffff
76233 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
76234 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_RESET 0x0
76235 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 field value from a register. */
76236 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
76237 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value suitable for setting the register. */
76238 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
76239 
76240 /*
76241  * Field : Mask Byte Control - mbc_4
76242  *
76243  * This array of bits are mask control bits for comparison of each of the MAC
76244  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76245  * received DA or SA with the contents of MAC Address91 high and low registers.
76246  * Each bit controls the masking of the bytes. You can filter a group of addresses
76247  * (known as group address filtering) by masking one or more bytes of the address.
76248  *
76249  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76250  *
76251  * Field Enumeration Values:
76252  *
76253  * Enum | Value | Description
76254  * :----------------------------------------------|:------|:------------------------------------
76255  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76256  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76257  *
76258  * Field Access Macros:
76259  *
76260  */
76261 /*
76262  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4
76263  *
76264  * Byte is unmasked (i.e. is compared)
76265  */
76266 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED 0x0
76267 /*
76268  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4
76269  *
76270  * Byte is masked (i.e. not compared)
76271  */
76272 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED 0x1
76273 
76274 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
76275 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_LSB 28
76276 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
76277 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_MSB 28
76278 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
76279 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_WIDTH 1
76280 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */
76281 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET_MSK 0x10000000
76282 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */
76283 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_CLR_MSK 0xefffffff
76284 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
76285 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_RESET 0x0
76286 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 field value from a register. */
76287 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
76288 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value suitable for setting the register. */
76289 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
76290 
76291 /*
76292  * Field : Mask Byte Control - mbc_5
76293  *
76294  * This array of bits are mask control bits for comparison of each of the MAC
76295  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76296  * received DA or SA with the contents of MAC Address91 high and low registers.
76297  * Each bit controls the masking of the bytes. You can filter a group of addresses
76298  * (known as group address filtering) by masking one or more bytes of the address.
76299  *
76300  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76301  *
76302  * Field Enumeration Values:
76303  *
76304  * Enum | Value | Description
76305  * :----------------------------------------------|:------|:------------------------------------
76306  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76307  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76308  *
76309  * Field Access Macros:
76310  *
76311  */
76312 /*
76313  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5
76314  *
76315  * Byte is unmasked (i.e. is compared)
76316  */
76317 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED 0x0
76318 /*
76319  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5
76320  *
76321  * Byte is masked (i.e. not compared)
76322  */
76323 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED 0x1
76324 
76325 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
76326 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_LSB 29
76327 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
76328 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_MSB 29
76329 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
76330 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_WIDTH 1
76331 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */
76332 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET_MSK 0x20000000
76333 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */
76334 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_CLR_MSK 0xdfffffff
76335 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
76336 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_RESET 0x0
76337 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 field value from a register. */
76338 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
76339 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value suitable for setting the register. */
76340 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
76341 
76342 /*
76343  * Field : Source Address - sa
76344  *
76345  * When this bit is enabled, the MAC Address91[47:0] is used to compare with the SA
76346  * fields of the received frame. When this bit is disabled, the MAC Address91[47:0]
76347  * is used to compare with the DA fields of the received frame.
76348  *
76349  * Field Enumeration Values:
76350  *
76351  * Enum | Value | Description
76352  * :----------------------------------------|:------|:-----------------------------
76353  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
76354  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END | 0x1 | MAC address compare enabled
76355  *
76356  * Field Access Macros:
76357  *
76358  */
76359 /*
76360  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA
76361  *
76362  * MAC address compare disabled
76363  */
76364 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD 0x0
76365 /*
76366  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA
76367  *
76368  * MAC address compare enabled
76369  */
76370 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END 0x1
76371 
76372 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
76373 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_LSB 30
76374 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
76375 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_MSB 30
76376 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
76377 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_WIDTH 1
76378 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */
76379 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET_MSK 0x40000000
76380 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */
76381 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_CLR_MSK 0xbfffffff
76382 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
76383 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_RESET 0x0
76384 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA field value from a register. */
76385 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
76386 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value suitable for setting the register. */
76387 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
76388 
76389 /*
76390  * Field : Address Enable - ae
76391  *
76392  * When this bit is enabled, the address filter block uses the 92th MAC address for
76393  * perfect filtering. When this bit is disabled, the address filter block ignores
76394  * the address for filtering.
76395  *
76396  * Field Enumeration Values:
76397  *
76398  * Enum | Value | Description
76399  * :----------------------------------------|:------|:--------------------------------------
76400  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
76401  * ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
76402  *
76403  * Field Access Macros:
76404  *
76405  */
76406 /*
76407  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
76408  *
76409  * Second MAC address filtering disabled
76410  */
76411 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD 0x0
76412 /*
76413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
76414  *
76415  * Second MAC address filtering enabled
76416  */
76417 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END 0x1
76418 
76419 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
76420 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_LSB 31
76421 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
76422 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_MSB 31
76423 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
76424 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_WIDTH 1
76425 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
76426 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET_MSK 0x80000000
76427 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
76428 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_CLR_MSK 0x7fffffff
76429 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
76430 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_RESET 0x0
76431 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE field value from a register. */
76432 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
76433 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value suitable for setting the register. */
76434 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
76435 
76436 #ifndef __ASSEMBLY__
76437 /*
76438  * WARNING: The C register and register group struct declarations are provided for
76439  * convenience and illustrative purposes. They should, however, be used with
76440  * caution as the C language standard provides no guarantees about the alignment or
76441  * atomicity of device memory accesses. The recommended practice for writing
76442  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76443  * alt_write_word() functions.
76444  *
76445  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH.
76446  */
76447 struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s
76448 {
76449  uint32_t addrhi : 16; /* MAC Address91 [47:32] */
76450  uint32_t : 8; /* *UNDEFINED* */
76451  uint32_t mbc_0 : 1; /* Mask Byte Control */
76452  uint32_t mbc_1 : 1; /* Mask Byte Control */
76453  uint32_t mbc_2 : 1; /* Mask Byte Control */
76454  uint32_t mbc_3 : 1; /* Mask Byte Control */
76455  uint32_t mbc_4 : 1; /* Mask Byte Control */
76456  uint32_t mbc_5 : 1; /* Mask Byte Control */
76457  uint32_t sa : 1; /* Source Address */
76458  uint32_t ae : 1; /* Address Enable */
76459 };
76460 
76461 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH. */
76462 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t;
76463 #endif /* __ASSEMBLY__ */
76464 
76465 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register from the beginning of the component. */
76466 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST 0xa58
76467 /* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register. */
76468 #define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST))
76469 
76470 /*
76471  * Register : Register 663 (MAC Address91 Low Register) - MAC_Address91_Low
76472  *
76473  * The MAC Address91 Low register holds the lower 32 bits of the 92th 6-byte MAC
76474  * address of the station.
76475  *
76476  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
76477  * format.
76478  *
76479  * Register Layout
76480  *
76481  * Bits | Access | Reset | Description
76482  * :-------|:-------|:-----------|:---------------------
76483  * [31:0] | RW | 0xffffffff | MAC Address91 [31:0]
76484  *
76485  */
76486 /*
76487  * Field : MAC Address91 [31:0] - addrlo
76488  *
76489  * This field contains the lower 32 bits of the 92th 6-byte MAC address. The
76490  * content of this field is undefined until loaded by software after the
76491  * initialization process.
76492  *
76493  * Field Access Macros:
76494  *
76495  */
76496 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
76497 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_LSB 0
76498 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
76499 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_MSB 31
76500 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
76501 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_WIDTH 32
76502 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
76503 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET_MSK 0xffffffff
76504 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
76505 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_CLR_MSK 0x00000000
76506 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
76507 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_RESET 0xffffffff
76508 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO field value from a register. */
76509 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
76510 /* Produces a ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value suitable for setting the register. */
76511 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
76512 
76513 #ifndef __ASSEMBLY__
76514 /*
76515  * WARNING: The C register and register group struct declarations are provided for
76516  * convenience and illustrative purposes. They should, however, be used with
76517  * caution as the C language standard provides no guarantees about the alignment or
76518  * atomicity of device memory accesses. The recommended practice for writing
76519  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
76520  * alt_write_word() functions.
76521  *
76522  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW.
76523  */
76524 struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s
76525 {
76526  uint32_t addrlo : 32; /* MAC Address91 [31:0] */
76527 };
76528 
76529 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW. */
76530 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s ALT_EMAC_GMAC_MAC_ADDR91_LOW_t;
76531 #endif /* __ASSEMBLY__ */
76532 
76533 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register from the beginning of the component. */
76534 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST 0xa5c
76535 /* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register. */
76536 #define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST))
76537 
76538 /*
76539  * Register : Register 664 (MAC Address92 High Register) - MAC_Address92_High
76540  *
76541  * The MAC Address92 High register holds the upper 16 bits of the 93th 6-byte MAC
76542  * address of the station. Because the MAC address registers are configured to be
76543  * double-synchronized to the (G)MII clock domains, the synchronization is
76544  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
76545  * endian mode) of the MAC Address92 Low Register are written. For proper
76546  * synchronization updates, the consecutive writes to this Address Low Register
76547  * should be performed after at least four clock cycles in the destination clock
76548  * domain.
76549  *
76550  * Note that all MAC Address High registers (except MAC Address0 High) have the
76551  * same format.
76552  *
76553  * Register Layout
76554  *
76555  * Bits | Access | Reset | Description
76556  * :--------|:-------|:-------|:----------------------
76557  * [15:0] | RW | 0xffff | MAC Address92 [47:32]
76558  * [23:16] | ??? | 0x0 | *UNDEFINED*
76559  * [24] | RW | 0x0 | Mask Byte Control
76560  * [25] | RW | 0x0 | Mask Byte Control
76561  * [26] | RW | 0x0 | Mask Byte Control
76562  * [27] | RW | 0x0 | Mask Byte Control
76563  * [28] | RW | 0x0 | Mask Byte Control
76564  * [29] | RW | 0x0 | Mask Byte Control
76565  * [30] | RW | 0x0 | Source Address
76566  * [31] | RW | 0x0 | Address Enable
76567  *
76568  */
76569 /*
76570  * Field : MAC Address92 [47:32] - addrhi
76571  *
76572  * This field contains the upper 16 bits (47:32) of the 93th 6-byte MAC address.
76573  *
76574  * Field Access Macros:
76575  *
76576  */
76577 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
76578 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_LSB 0
76579 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
76580 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_MSB 15
76581 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
76582 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_WIDTH 16
76583 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
76584 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET_MSK 0x0000ffff
76585 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
76586 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_CLR_MSK 0xffff0000
76587 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
76588 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_RESET 0xffff
76589 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI field value from a register. */
76590 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
76591 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value suitable for setting the register. */
76592 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
76593 
76594 /*
76595  * Field : Mask Byte Control - mbc_0
76596  *
76597  * This array of bits are mask control bits for comparison of each of the MAC
76598  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76599  * received DA or SA with the contents of MAC Address92 high and low registers.
76600  * Each bit controls the masking of the bytes. You can filter a group of addresses
76601  * (known as group address filtering) by masking one or more bytes of the address.
76602  *
76603  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76604  *
76605  * Field Enumeration Values:
76606  *
76607  * Enum | Value | Description
76608  * :----------------------------------------------|:------|:------------------------------------
76609  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76610  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76611  *
76612  * Field Access Macros:
76613  *
76614  */
76615 /*
76616  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0
76617  *
76618  * Byte is unmasked (i.e. is compared)
76619  */
76620 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED 0x0
76621 /*
76622  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0
76623  *
76624  * Byte is masked (i.e. not compared)
76625  */
76626 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED 0x1
76627 
76628 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
76629 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_LSB 24
76630 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
76631 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_MSB 24
76632 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
76633 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_WIDTH 1
76634 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */
76635 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET_MSK 0x01000000
76636 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */
76637 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_CLR_MSK 0xfeffffff
76638 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
76639 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_RESET 0x0
76640 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 field value from a register. */
76641 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
76642 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value suitable for setting the register. */
76643 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
76644 
76645 /*
76646  * Field : Mask Byte Control - mbc_1
76647  *
76648  * This array of bits are mask control bits for comparison of each of the MAC
76649  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76650  * received DA or SA with the contents of MAC Address92 high and low registers.
76651  * Each bit controls the masking of the bytes. You can filter a group of addresses
76652  * (known as group address filtering) by masking one or more bytes of the address.
76653  *
76654  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76655  *
76656  * Field Enumeration Values:
76657  *
76658  * Enum | Value | Description
76659  * :----------------------------------------------|:------|:------------------------------------
76660  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76661  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76662  *
76663  * Field Access Macros:
76664  *
76665  */
76666 /*
76667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1
76668  *
76669  * Byte is unmasked (i.e. is compared)
76670  */
76671 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED 0x0
76672 /*
76673  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1
76674  *
76675  * Byte is masked (i.e. not compared)
76676  */
76677 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED 0x1
76678 
76679 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
76680 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_LSB 25
76681 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
76682 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_MSB 25
76683 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
76684 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_WIDTH 1
76685 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */
76686 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET_MSK 0x02000000
76687 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */
76688 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_CLR_MSK 0xfdffffff
76689 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
76690 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_RESET 0x0
76691 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 field value from a register. */
76692 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
76693 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value suitable for setting the register. */
76694 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
76695 
76696 /*
76697  * Field : Mask Byte Control - mbc_2
76698  *
76699  * This array of bits are mask control bits for comparison of each of the MAC
76700  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76701  * received DA or SA with the contents of MAC Address92 high and low registers.
76702  * Each bit controls the masking of the bytes. You can filter a group of addresses
76703  * (known as group address filtering) by masking one or more bytes of the address.
76704  *
76705  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76706  *
76707  * Field Enumeration Values:
76708  *
76709  * Enum | Value | Description
76710  * :----------------------------------------------|:------|:------------------------------------
76711  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76712  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76713  *
76714  * Field Access Macros:
76715  *
76716  */
76717 /*
76718  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2
76719  *
76720  * Byte is unmasked (i.e. is compared)
76721  */
76722 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED 0x0
76723 /*
76724  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2
76725  *
76726  * Byte is masked (i.e. not compared)
76727  */
76728 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED 0x1
76729 
76730 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
76731 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_LSB 26
76732 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
76733 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_MSB 26
76734 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
76735 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_WIDTH 1
76736 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */
76737 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET_MSK 0x04000000
76738 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */
76739 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_CLR_MSK 0xfbffffff
76740 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
76741 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_RESET 0x0
76742 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 field value from a register. */
76743 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
76744 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value suitable for setting the register. */
76745 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
76746 
76747 /*
76748  * Field : Mask Byte Control - mbc_3
76749  *
76750  * This array of bits are mask control bits for comparison of each of the MAC
76751  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76752  * received DA or SA with the contents of MAC Address92 high and low registers.
76753  * Each bit controls the masking of the bytes. You can filter a group of addresses
76754  * (known as group address filtering) by masking one or more bytes of the address.
76755  *
76756  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76757  *
76758  * Field Enumeration Values:
76759  *
76760  * Enum | Value | Description
76761  * :----------------------------------------------|:------|:------------------------------------
76762  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76763  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76764  *
76765  * Field Access Macros:
76766  *
76767  */
76768 /*
76769  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3
76770  *
76771  * Byte is unmasked (i.e. is compared)
76772  */
76773 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED 0x0
76774 /*
76775  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3
76776  *
76777  * Byte is masked (i.e. not compared)
76778  */
76779 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED 0x1
76780 
76781 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
76782 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_LSB 27
76783 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
76784 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_MSB 27
76785 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
76786 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_WIDTH 1
76787 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */
76788 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET_MSK 0x08000000
76789 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */
76790 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_CLR_MSK 0xf7ffffff
76791 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
76792 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_RESET 0x0
76793 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 field value from a register. */
76794 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
76795 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value suitable for setting the register. */
76796 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
76797 
76798 /*
76799  * Field : Mask Byte Control - mbc_4
76800  *
76801  * This array of bits are mask control bits for comparison of each of the MAC
76802  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76803  * received DA or SA with the contents of MAC Address92 high and low registers.
76804  * Each bit controls the masking of the bytes. You can filter a group of addresses
76805  * (known as group address filtering) by masking one or more bytes of the address.
76806  *
76807  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76808  *
76809  * Field Enumeration Values:
76810  *
76811  * Enum | Value | Description
76812  * :----------------------------------------------|:------|:------------------------------------
76813  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76814  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76815  *
76816  * Field Access Macros:
76817  *
76818  */
76819 /*
76820  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4
76821  *
76822  * Byte is unmasked (i.e. is compared)
76823  */
76824 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED 0x0
76825 /*
76826  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4
76827  *
76828  * Byte is masked (i.e. not compared)
76829  */
76830 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED 0x1
76831 
76832 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
76833 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_LSB 28
76834 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
76835 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_MSB 28
76836 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
76837 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_WIDTH 1
76838 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */
76839 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET_MSK 0x10000000
76840 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */
76841 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_CLR_MSK 0xefffffff
76842 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
76843 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_RESET 0x0
76844 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 field value from a register. */
76845 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
76846 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value suitable for setting the register. */
76847 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
76848 
76849 /*
76850  * Field : Mask Byte Control - mbc_5
76851  *
76852  * This array of bits are mask control bits for comparison of each of the MAC
76853  * Address bytes. When masked, the MAC does not compare the corresponding byte of
76854  * received DA or SA with the contents of MAC Address92 high and low registers.
76855  * Each bit controls the masking of the bytes. You can filter a group of addresses
76856  * (known as group address filtering) by masking one or more bytes of the address.
76857  *
76858  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
76859  *
76860  * Field Enumeration Values:
76861  *
76862  * Enum | Value | Description
76863  * :----------------------------------------------|:------|:------------------------------------
76864  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
76865  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
76866  *
76867  * Field Access Macros:
76868  *
76869  */
76870 /*
76871  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5
76872  *
76873  * Byte is unmasked (i.e. is compared)
76874  */
76875 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED 0x0
76876 /*
76877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5
76878  *
76879  * Byte is masked (i.e. not compared)
76880  */
76881 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED 0x1
76882 
76883 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
76884 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_LSB 29
76885 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
76886 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_MSB 29
76887 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
76888 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_WIDTH 1
76889 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */
76890 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET_MSK 0x20000000
76891 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */
76892 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_CLR_MSK 0xdfffffff
76893 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
76894 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_RESET 0x0
76895 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 field value from a register. */
76896 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
76897 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value suitable for setting the register. */
76898 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
76899 
76900 /*
76901  * Field : Source Address - sa
76902  *
76903  * When this bit is enabled, the MAC Address92[47:0] is used to compare with the SA
76904  * fields of the received frame. When this bit is disabled, the MAC Address92[47:0]
76905  * is used to compare with the DA fields of the received frame.
76906  *
76907  * Field Enumeration Values:
76908  *
76909  * Enum | Value | Description
76910  * :----------------------------------------|:------|:-----------------------------
76911  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
76912  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END | 0x1 | MAC address compare enabled
76913  *
76914  * Field Access Macros:
76915  *
76916  */
76917 /*
76918  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA
76919  *
76920  * MAC address compare disabled
76921  */
76922 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD 0x0
76923 /*
76924  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA
76925  *
76926  * MAC address compare enabled
76927  */
76928 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END 0x1
76929 
76930 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
76931 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_LSB 30
76932 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
76933 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_MSB 30
76934 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
76935 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_WIDTH 1
76936 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */
76937 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET_MSK 0x40000000
76938 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */
76939 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_CLR_MSK 0xbfffffff
76940 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
76941 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_RESET 0x0
76942 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA field value from a register. */
76943 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
76944 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value suitable for setting the register. */
76945 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
76946 
76947 /*
76948  * Field : Address Enable - ae
76949  *
76950  * When this bit is enabled, the address filter block uses the 93th MAC address for
76951  * perfect filtering. When this bit is disabled, the address filter block ignores
76952  * the address for filtering.
76953  *
76954  * Field Enumeration Values:
76955  *
76956  * Enum | Value | Description
76957  * :----------------------------------------|:------|:--------------------------------------
76958  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
76959  * ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
76960  *
76961  * Field Access Macros:
76962  *
76963  */
76964 /*
76965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
76966  *
76967  * Second MAC address filtering disabled
76968  */
76969 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD 0x0
76970 /*
76971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
76972  *
76973  * Second MAC address filtering enabled
76974  */
76975 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END 0x1
76976 
76977 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
76978 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_LSB 31
76979 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
76980 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_MSB 31
76981 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
76982 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_WIDTH 1
76983 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
76984 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET_MSK 0x80000000
76985 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
76986 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_CLR_MSK 0x7fffffff
76987 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
76988 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_RESET 0x0
76989 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE field value from a register. */
76990 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
76991 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value suitable for setting the register. */
76992 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
76993 
76994 #ifndef __ASSEMBLY__
76995 /*
76996  * WARNING: The C register and register group struct declarations are provided for
76997  * convenience and illustrative purposes. They should, however, be used with
76998  * caution as the C language standard provides no guarantees about the alignment or
76999  * atomicity of device memory accesses. The recommended practice for writing
77000  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
77001  * alt_write_word() functions.
77002  *
77003  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH.
77004  */
77005 struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s
77006 {
77007  uint32_t addrhi : 16; /* MAC Address92 [47:32] */
77008  uint32_t : 8; /* *UNDEFINED* */
77009  uint32_t mbc_0 : 1; /* Mask Byte Control */
77010  uint32_t mbc_1 : 1; /* Mask Byte Control */
77011  uint32_t mbc_2 : 1; /* Mask Byte Control */
77012  uint32_t mbc_3 : 1; /* Mask Byte Control */
77013  uint32_t mbc_4 : 1; /* Mask Byte Control */
77014  uint32_t mbc_5 : 1; /* Mask Byte Control */
77015  uint32_t sa : 1; /* Source Address */
77016  uint32_t ae : 1; /* Address Enable */
77017 };
77018 
77019 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH. */
77020 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t;
77021 #endif /* __ASSEMBLY__ */
77022 
77023 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register from the beginning of the component. */
77024 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST 0xa60
77025 /* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register. */
77026 #define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST))
77027 
77028 /*
77029  * Register : Register 665 (MAC Address92 Low Register) - MAC_Address92_Low
77030  *
77031  * The MAC Address92 Low register holds the lower 32 bits of the 93th 6-byte MAC
77032  * address of the station.
77033  *
77034  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
77035  * format.
77036  *
77037  * Register Layout
77038  *
77039  * Bits | Access | Reset | Description
77040  * :-------|:-------|:-----------|:---------------------
77041  * [31:0] | RW | 0xffffffff | MAC Address92 [31:0]
77042  *
77043  */
77044 /*
77045  * Field : MAC Address92 [31:0] - addrlo
77046  *
77047  * This field contains the lower 32 bits of the 93th 6-byte MAC address. The
77048  * content of this field is undefined until loaded by software after the
77049  * initialization process.
77050  *
77051  * Field Access Macros:
77052  *
77053  */
77054 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
77055 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_LSB 0
77056 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
77057 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_MSB 31
77058 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
77059 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_WIDTH 32
77060 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
77061 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET_MSK 0xffffffff
77062 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
77063 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_CLR_MSK 0x00000000
77064 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
77065 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_RESET 0xffffffff
77066 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO field value from a register. */
77067 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
77068 /* Produces a ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value suitable for setting the register. */
77069 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
77070 
77071 #ifndef __ASSEMBLY__
77072 /*
77073  * WARNING: The C register and register group struct declarations are provided for
77074  * convenience and illustrative purposes. They should, however, be used with
77075  * caution as the C language standard provides no guarantees about the alignment or
77076  * atomicity of device memory accesses. The recommended practice for writing
77077  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
77078  * alt_write_word() functions.
77079  *
77080  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW.
77081  */
77082 struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s
77083 {
77084  uint32_t addrlo : 32; /* MAC Address92 [31:0] */
77085 };
77086 
77087 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW. */
77088 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s ALT_EMAC_GMAC_MAC_ADDR92_LOW_t;
77089 #endif /* __ASSEMBLY__ */
77090 
77091 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register from the beginning of the component. */
77092 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST 0xa64
77093 /* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register. */
77094 #define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST))
77095 
77096 /*
77097  * Register : Register 666 (MAC Address93 High Register) - MAC_Address93_High
77098  *
77099  * The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC
77100  * address of the station. Because the MAC address registers are configured to be
77101  * double-synchronized to the (G)MII clock domains, the synchronization is
77102  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
77103  * endian mode) of the MAC Address93 Low Register are written. For proper
77104  * synchronization updates, the consecutive writes to this Address Low Register
77105  * should be performed after at least four clock cycles in the destination clock
77106  * domain.
77107  *
77108  * Note that all MAC Address High registers (except MAC Address0 High) have the
77109  * same format.
77110  *
77111  * Register Layout
77112  *
77113  * Bits | Access | Reset | Description
77114  * :--------|:-------|:-------|:----------------------
77115  * [15:0] | RW | 0xffff | MAC Address93 [47:32]
77116  * [23:16] | ??? | 0x0 | *UNDEFINED*
77117  * [24] | RW | 0x0 | Mask Byte Control
77118  * [25] | RW | 0x0 | Mask Byte Control
77119  * [26] | RW | 0x0 | Mask Byte Control
77120  * [27] | RW | 0x0 | Mask Byte Control
77121  * [28] | RW | 0x0 | Mask Byte Control
77122  * [29] | RW | 0x0 | Mask Byte Control
77123  * [30] | RW | 0x0 | Source Address
77124  * [31] | RW | 0x0 | Address Enable
77125  *
77126  */
77127 /*
77128  * Field : MAC Address93 [47:32] - addrhi
77129  *
77130  * This field contains the upper 16 bits (47:32) of the 94th 6-byte MAC address.
77131  *
77132  * Field Access Macros:
77133  *
77134  */
77135 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
77136 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_LSB 0
77137 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
77138 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_MSB 15
77139 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
77140 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_WIDTH 16
77141 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
77142 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET_MSK 0x0000ffff
77143 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
77144 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_CLR_MSK 0xffff0000
77145 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
77146 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_RESET 0xffff
77147 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI field value from a register. */
77148 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
77149 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value suitable for setting the register. */
77150 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
77151 
77152 /*
77153  * Field : Mask Byte Control - mbc_0
77154  *
77155  * This array of bits are mask control bits for comparison of each of the MAC
77156  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77157  * received DA or SA with the contents of MAC Address93 high and low registers.
77158  * Each bit controls the masking of the bytes. You can filter a group of addresses
77159  * (known as group address filtering) by masking one or more bytes of the address.
77160  *
77161  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77162  *
77163  * Field Enumeration Values:
77164  *
77165  * Enum | Value | Description
77166  * :----------------------------------------------|:------|:------------------------------------
77167  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77168  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77169  *
77170  * Field Access Macros:
77171  *
77172  */
77173 /*
77174  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0
77175  *
77176  * Byte is unmasked (i.e. is compared)
77177  */
77178 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED 0x0
77179 /*
77180  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0
77181  *
77182  * Byte is masked (i.e. not compared)
77183  */
77184 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED 0x1
77185 
77186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
77187 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_LSB 24
77188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
77189 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_MSB 24
77190 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
77191 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_WIDTH 1
77192 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */
77193 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET_MSK 0x01000000
77194 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */
77195 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_CLR_MSK 0xfeffffff
77196 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
77197 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_RESET 0x0
77198 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 field value from a register. */
77199 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
77200 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value suitable for setting the register. */
77201 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
77202 
77203 /*
77204  * Field : Mask Byte Control - mbc_1
77205  *
77206  * This array of bits are mask control bits for comparison of each of the MAC
77207  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77208  * received DA or SA with the contents of MAC Address93 high and low registers.
77209  * Each bit controls the masking of the bytes. You can filter a group of addresses
77210  * (known as group address filtering) by masking one or more bytes of the address.
77211  *
77212  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77213  *
77214  * Field Enumeration Values:
77215  *
77216  * Enum | Value | Description
77217  * :----------------------------------------------|:------|:------------------------------------
77218  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77219  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77220  *
77221  * Field Access Macros:
77222  *
77223  */
77224 /*
77225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1
77226  *
77227  * Byte is unmasked (i.e. is compared)
77228  */
77229 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED 0x0
77230 /*
77231  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1
77232  *
77233  * Byte is masked (i.e. not compared)
77234  */
77235 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED 0x1
77236 
77237 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
77238 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_LSB 25
77239 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
77240 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_MSB 25
77241 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
77242 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_WIDTH 1
77243 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */
77244 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET_MSK 0x02000000
77245 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */
77246 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_CLR_MSK 0xfdffffff
77247 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
77248 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_RESET 0x0
77249 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 field value from a register. */
77250 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
77251 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value suitable for setting the register. */
77252 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
77253 
77254 /*
77255  * Field : Mask Byte Control - mbc_2
77256  *
77257  * This array of bits are mask control bits for comparison of each of the MAC
77258  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77259  * received DA or SA with the contents of MAC Address93 high and low registers.
77260  * Each bit controls the masking of the bytes. You can filter a group of addresses
77261  * (known as group address filtering) by masking one or more bytes of the address.
77262  *
77263  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77264  *
77265  * Field Enumeration Values:
77266  *
77267  * Enum | Value | Description
77268  * :----------------------------------------------|:------|:------------------------------------
77269  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77270  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77271  *
77272  * Field Access Macros:
77273  *
77274  */
77275 /*
77276  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2
77277  *
77278  * Byte is unmasked (i.e. is compared)
77279  */
77280 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED 0x0
77281 /*
77282  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2
77283  *
77284  * Byte is masked (i.e. not compared)
77285  */
77286 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED 0x1
77287 
77288 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
77289 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_LSB 26
77290 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
77291 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_MSB 26
77292 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
77293 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_WIDTH 1
77294 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */
77295 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET_MSK 0x04000000
77296 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */
77297 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_CLR_MSK 0xfbffffff
77298 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
77299 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_RESET 0x0
77300 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 field value from a register. */
77301 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
77302 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value suitable for setting the register. */
77303 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
77304 
77305 /*
77306  * Field : Mask Byte Control - mbc_3
77307  *
77308  * This array of bits are mask control bits for comparison of each of the MAC
77309  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77310  * received DA or SA with the contents of MAC Address93 high and low registers.
77311  * Each bit controls the masking of the bytes. You can filter a group of addresses
77312  * (known as group address filtering) by masking one or more bytes of the address.
77313  *
77314  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77315  *
77316  * Field Enumeration Values:
77317  *
77318  * Enum | Value | Description
77319  * :----------------------------------------------|:------|:------------------------------------
77320  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77321  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77322  *
77323  * Field Access Macros:
77324  *
77325  */
77326 /*
77327  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3
77328  *
77329  * Byte is unmasked (i.e. is compared)
77330  */
77331 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED 0x0
77332 /*
77333  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3
77334  *
77335  * Byte is masked (i.e. not compared)
77336  */
77337 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED 0x1
77338 
77339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
77340 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_LSB 27
77341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
77342 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_MSB 27
77343 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
77344 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_WIDTH 1
77345 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */
77346 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET_MSK 0x08000000
77347 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */
77348 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_CLR_MSK 0xf7ffffff
77349 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
77350 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_RESET 0x0
77351 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 field value from a register. */
77352 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
77353 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value suitable for setting the register. */
77354 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
77355 
77356 /*
77357  * Field : Mask Byte Control - mbc_4
77358  *
77359  * This array of bits are mask control bits for comparison of each of the MAC
77360  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77361  * received DA or SA with the contents of MAC Address93 high and low registers.
77362  * Each bit controls the masking of the bytes. You can filter a group of addresses
77363  * (known as group address filtering) by masking one or more bytes of the address.
77364  *
77365  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77366  *
77367  * Field Enumeration Values:
77368  *
77369  * Enum | Value | Description
77370  * :----------------------------------------------|:------|:------------------------------------
77371  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77372  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77373  *
77374  * Field Access Macros:
77375  *
77376  */
77377 /*
77378  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4
77379  *
77380  * Byte is unmasked (i.e. is compared)
77381  */
77382 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED 0x0
77383 /*
77384  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4
77385  *
77386  * Byte is masked (i.e. not compared)
77387  */
77388 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED 0x1
77389 
77390 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
77391 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_LSB 28
77392 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
77393 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_MSB 28
77394 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
77395 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_WIDTH 1
77396 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */
77397 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET_MSK 0x10000000
77398 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */
77399 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_CLR_MSK 0xefffffff
77400 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
77401 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_RESET 0x0
77402 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 field value from a register. */
77403 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
77404 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value suitable for setting the register. */
77405 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
77406 
77407 /*
77408  * Field : Mask Byte Control - mbc_5
77409  *
77410  * This array of bits are mask control bits for comparison of each of the MAC
77411  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77412  * received DA or SA with the contents of MAC Address93 high and low registers.
77413  * Each bit controls the masking of the bytes. You can filter a group of addresses
77414  * (known as group address filtering) by masking one or more bytes of the address.
77415  *
77416  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77417  *
77418  * Field Enumeration Values:
77419  *
77420  * Enum | Value | Description
77421  * :----------------------------------------------|:------|:------------------------------------
77422  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77423  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77424  *
77425  * Field Access Macros:
77426  *
77427  */
77428 /*
77429  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5
77430  *
77431  * Byte is unmasked (i.e. is compared)
77432  */
77433 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED 0x0
77434 /*
77435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5
77436  *
77437  * Byte is masked (i.e. not compared)
77438  */
77439 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED 0x1
77440 
77441 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
77442 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_LSB 29
77443 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
77444 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_MSB 29
77445 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
77446 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_WIDTH 1
77447 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */
77448 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET_MSK 0x20000000
77449 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */
77450 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_CLR_MSK 0xdfffffff
77451 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
77452 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_RESET 0x0
77453 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 field value from a register. */
77454 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
77455 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value suitable for setting the register. */
77456 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
77457 
77458 /*
77459  * Field : Source Address - sa
77460  *
77461  * When this bit is enabled, the MAC Address93[47:0] is used to compare with the SA
77462  * fields of the received frame. When this bit is disabled, the MAC Address93[47:0]
77463  * is used to compare with the DA fields of the received frame.
77464  *
77465  * Field Enumeration Values:
77466  *
77467  * Enum | Value | Description
77468  * :----------------------------------------|:------|:-----------------------------
77469  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
77470  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END | 0x1 | MAC address compare enabled
77471  *
77472  * Field Access Macros:
77473  *
77474  */
77475 /*
77476  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA
77477  *
77478  * MAC address compare disabled
77479  */
77480 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD 0x0
77481 /*
77482  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA
77483  *
77484  * MAC address compare enabled
77485  */
77486 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END 0x1
77487 
77488 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
77489 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_LSB 30
77490 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
77491 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_MSB 30
77492 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
77493 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_WIDTH 1
77494 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */
77495 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET_MSK 0x40000000
77496 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */
77497 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_CLR_MSK 0xbfffffff
77498 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
77499 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_RESET 0x0
77500 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA field value from a register. */
77501 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
77502 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value suitable for setting the register. */
77503 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
77504 
77505 /*
77506  * Field : Address Enable - ae
77507  *
77508  * When this bit is enabled, the address filter block uses the 94th MAC address for
77509  * perfect filtering. When this bit is disabled, the address filter block ignores
77510  * the address for filtering.
77511  *
77512  * Field Enumeration Values:
77513  *
77514  * Enum | Value | Description
77515  * :----------------------------------------|:------|:--------------------------------------
77516  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
77517  * ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
77518  *
77519  * Field Access Macros:
77520  *
77521  */
77522 /*
77523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
77524  *
77525  * Second MAC address filtering disabled
77526  */
77527 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD 0x0
77528 /*
77529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
77530  *
77531  * Second MAC address filtering enabled
77532  */
77533 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END 0x1
77534 
77535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
77536 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_LSB 31
77537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
77538 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_MSB 31
77539 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
77540 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_WIDTH 1
77541 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
77542 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET_MSK 0x80000000
77543 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
77544 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_CLR_MSK 0x7fffffff
77545 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
77546 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_RESET 0x0
77547 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE field value from a register. */
77548 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
77549 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value suitable for setting the register. */
77550 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
77551 
77552 #ifndef __ASSEMBLY__
77553 /*
77554  * WARNING: The C register and register group struct declarations are provided for
77555  * convenience and illustrative purposes. They should, however, be used with
77556  * caution as the C language standard provides no guarantees about the alignment or
77557  * atomicity of device memory accesses. The recommended practice for writing
77558  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
77559  * alt_write_word() functions.
77560  *
77561  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH.
77562  */
77563 struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s
77564 {
77565  uint32_t addrhi : 16; /* MAC Address93 [47:32] */
77566  uint32_t : 8; /* *UNDEFINED* */
77567  uint32_t mbc_0 : 1; /* Mask Byte Control */
77568  uint32_t mbc_1 : 1; /* Mask Byte Control */
77569  uint32_t mbc_2 : 1; /* Mask Byte Control */
77570  uint32_t mbc_3 : 1; /* Mask Byte Control */
77571  uint32_t mbc_4 : 1; /* Mask Byte Control */
77572  uint32_t mbc_5 : 1; /* Mask Byte Control */
77573  uint32_t sa : 1; /* Source Address */
77574  uint32_t ae : 1; /* Address Enable */
77575 };
77576 
77577 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH. */
77578 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t;
77579 #endif /* __ASSEMBLY__ */
77580 
77581 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register from the beginning of the component. */
77582 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST 0xa68
77583 /* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register. */
77584 #define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST))
77585 
77586 /*
77587  * Register : Register 667 (MAC Address93 Low Register) - MAC_Address93_Low
77588  *
77589  * The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC
77590  * address of the station.
77591  *
77592  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
77593  * format.
77594  *
77595  * Register Layout
77596  *
77597  * Bits | Access | Reset | Description
77598  * :-------|:-------|:-----------|:---------------------
77599  * [31:0] | RW | 0xffffffff | MAC Address93 [31:0]
77600  *
77601  */
77602 /*
77603  * Field : MAC Address93 [31:0] - addrlo
77604  *
77605  * This field contains the lower 32 bits of the 94th 6-byte MAC address. The
77606  * content of this field is undefined until loaded by software after the
77607  * initialization process.
77608  *
77609  * Field Access Macros:
77610  *
77611  */
77612 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
77613 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_LSB 0
77614 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
77615 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_MSB 31
77616 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
77617 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_WIDTH 32
77618 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
77619 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET_MSK 0xffffffff
77620 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
77621 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_CLR_MSK 0x00000000
77622 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
77623 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_RESET 0xffffffff
77624 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO field value from a register. */
77625 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
77626 /* Produces a ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value suitable for setting the register. */
77627 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
77628 
77629 #ifndef __ASSEMBLY__
77630 /*
77631  * WARNING: The C register and register group struct declarations are provided for
77632  * convenience and illustrative purposes. They should, however, be used with
77633  * caution as the C language standard provides no guarantees about the alignment or
77634  * atomicity of device memory accesses. The recommended practice for writing
77635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
77636  * alt_write_word() functions.
77637  *
77638  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW.
77639  */
77640 struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s
77641 {
77642  uint32_t addrlo : 32; /* MAC Address93 [31:0] */
77643 };
77644 
77645 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW. */
77646 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s ALT_EMAC_GMAC_MAC_ADDR93_LOW_t;
77647 #endif /* __ASSEMBLY__ */
77648 
77649 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register from the beginning of the component. */
77650 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST 0xa6c
77651 /* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register. */
77652 #define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST))
77653 
77654 /*
77655  * Register : Register 668 (MAC Address94 High Register) - MAC_Address94_High
77656  *
77657  * The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC
77658  * address of the station. Because the MAC address registers are configured to be
77659  * double-synchronized to the (G)MII clock domains, the synchronization is
77660  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
77661  * endian mode) of the MAC Address94 Low Register are written. For proper
77662  * synchronization updates, the consecutive writes to this Address Low Register
77663  * should be performed after at least four clock cycles in the destination clock
77664  * domain.
77665  *
77666  * Note that all MAC Address High registers (except MAC Address0 High) have the
77667  * same format.
77668  *
77669  * Register Layout
77670  *
77671  * Bits | Access | Reset | Description
77672  * :--------|:-------|:-------|:----------------------
77673  * [15:0] | RW | 0xffff | MAC Address94 [47:32]
77674  * [23:16] | ??? | 0x0 | *UNDEFINED*
77675  * [24] | RW | 0x0 | Mask Byte Control
77676  * [25] | RW | 0x0 | Mask Byte Control
77677  * [26] | RW | 0x0 | Mask Byte Control
77678  * [27] | RW | 0x0 | Mask Byte Control
77679  * [28] | RW | 0x0 | Mask Byte Control
77680  * [29] | RW | 0x0 | Mask Byte Control
77681  * [30] | RW | 0x0 | Source Address
77682  * [31] | RW | 0x0 | Address Enable
77683  *
77684  */
77685 /*
77686  * Field : MAC Address94 [47:32] - addrhi
77687  *
77688  * This field contains the upper 16 bits (47:32) of the 95th 6-byte MAC address.
77689  *
77690  * Field Access Macros:
77691  *
77692  */
77693 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
77694 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_LSB 0
77695 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
77696 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_MSB 15
77697 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
77698 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_WIDTH 16
77699 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
77700 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET_MSK 0x0000ffff
77701 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
77702 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_CLR_MSK 0xffff0000
77703 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
77704 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_RESET 0xffff
77705 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI field value from a register. */
77706 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
77707 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value suitable for setting the register. */
77708 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
77709 
77710 /*
77711  * Field : Mask Byte Control - mbc_0
77712  *
77713  * This array of bits are mask control bits for comparison of each of the MAC
77714  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77715  * received DA or SA with the contents of MAC Address94 high and low registers.
77716  * Each bit controls the masking of the bytes. You can filter a group of addresses
77717  * (known as group address filtering) by masking one or more bytes of the address.
77718  *
77719  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77720  *
77721  * Field Enumeration Values:
77722  *
77723  * Enum | Value | Description
77724  * :----------------------------------------------|:------|:------------------------------------
77725  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77726  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77727  *
77728  * Field Access Macros:
77729  *
77730  */
77731 /*
77732  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0
77733  *
77734  * Byte is unmasked (i.e. is compared)
77735  */
77736 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED 0x0
77737 /*
77738  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0
77739  *
77740  * Byte is masked (i.e. not compared)
77741  */
77742 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED 0x1
77743 
77744 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
77745 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_LSB 24
77746 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
77747 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_MSB 24
77748 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
77749 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_WIDTH 1
77750 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */
77751 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET_MSK 0x01000000
77752 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */
77753 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_CLR_MSK 0xfeffffff
77754 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
77755 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_RESET 0x0
77756 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 field value from a register. */
77757 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
77758 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value suitable for setting the register. */
77759 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
77760 
77761 /*
77762  * Field : Mask Byte Control - mbc_1
77763  *
77764  * This array of bits are mask control bits for comparison of each of the MAC
77765  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77766  * received DA or SA with the contents of MAC Address94 high and low registers.
77767  * Each bit controls the masking of the bytes. You can filter a group of addresses
77768  * (known as group address filtering) by masking one or more bytes of the address.
77769  *
77770  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77771  *
77772  * Field Enumeration Values:
77773  *
77774  * Enum | Value | Description
77775  * :----------------------------------------------|:------|:------------------------------------
77776  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77777  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77778  *
77779  * Field Access Macros:
77780  *
77781  */
77782 /*
77783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1
77784  *
77785  * Byte is unmasked (i.e. is compared)
77786  */
77787 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED 0x0
77788 /*
77789  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1
77790  *
77791  * Byte is masked (i.e. not compared)
77792  */
77793 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED 0x1
77794 
77795 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
77796 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_LSB 25
77797 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
77798 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_MSB 25
77799 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
77800 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_WIDTH 1
77801 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */
77802 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET_MSK 0x02000000
77803 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */
77804 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_CLR_MSK 0xfdffffff
77805 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
77806 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_RESET 0x0
77807 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 field value from a register. */
77808 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
77809 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value suitable for setting the register. */
77810 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
77811 
77812 /*
77813  * Field : Mask Byte Control - mbc_2
77814  *
77815  * This array of bits are mask control bits for comparison of each of the MAC
77816  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77817  * received DA or SA with the contents of MAC Address94 high and low registers.
77818  * Each bit controls the masking of the bytes. You can filter a group of addresses
77819  * (known as group address filtering) by masking one or more bytes of the address.
77820  *
77821  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77822  *
77823  * Field Enumeration Values:
77824  *
77825  * Enum | Value | Description
77826  * :----------------------------------------------|:------|:------------------------------------
77827  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77828  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77829  *
77830  * Field Access Macros:
77831  *
77832  */
77833 /*
77834  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2
77835  *
77836  * Byte is unmasked (i.e. is compared)
77837  */
77838 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED 0x0
77839 /*
77840  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2
77841  *
77842  * Byte is masked (i.e. not compared)
77843  */
77844 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED 0x1
77845 
77846 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
77847 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_LSB 26
77848 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
77849 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_MSB 26
77850 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
77851 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_WIDTH 1
77852 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */
77853 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET_MSK 0x04000000
77854 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */
77855 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_CLR_MSK 0xfbffffff
77856 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
77857 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_RESET 0x0
77858 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 field value from a register. */
77859 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
77860 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value suitable for setting the register. */
77861 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
77862 
77863 /*
77864  * Field : Mask Byte Control - mbc_3
77865  *
77866  * This array of bits are mask control bits for comparison of each of the MAC
77867  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77868  * received DA or SA with the contents of MAC Address94 high and low registers.
77869  * Each bit controls the masking of the bytes. You can filter a group of addresses
77870  * (known as group address filtering) by masking one or more bytes of the address.
77871  *
77872  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77873  *
77874  * Field Enumeration Values:
77875  *
77876  * Enum | Value | Description
77877  * :----------------------------------------------|:------|:------------------------------------
77878  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77879  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77880  *
77881  * Field Access Macros:
77882  *
77883  */
77884 /*
77885  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3
77886  *
77887  * Byte is unmasked (i.e. is compared)
77888  */
77889 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED 0x0
77890 /*
77891  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3
77892  *
77893  * Byte is masked (i.e. not compared)
77894  */
77895 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED 0x1
77896 
77897 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
77898 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_LSB 27
77899 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
77900 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_MSB 27
77901 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
77902 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_WIDTH 1
77903 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */
77904 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET_MSK 0x08000000
77905 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */
77906 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_CLR_MSK 0xf7ffffff
77907 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
77908 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_RESET 0x0
77909 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 field value from a register. */
77910 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
77911 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value suitable for setting the register. */
77912 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
77913 
77914 /*
77915  * Field : Mask Byte Control - mbc_4
77916  *
77917  * This array of bits are mask control bits for comparison of each of the MAC
77918  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77919  * received DA or SA with the contents of MAC Address94 high and low registers.
77920  * Each bit controls the masking of the bytes. You can filter a group of addresses
77921  * (known as group address filtering) by masking one or more bytes of the address.
77922  *
77923  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77924  *
77925  * Field Enumeration Values:
77926  *
77927  * Enum | Value | Description
77928  * :----------------------------------------------|:------|:------------------------------------
77929  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77930  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77931  *
77932  * Field Access Macros:
77933  *
77934  */
77935 /*
77936  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4
77937  *
77938  * Byte is unmasked (i.e. is compared)
77939  */
77940 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED 0x0
77941 /*
77942  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4
77943  *
77944  * Byte is masked (i.e. not compared)
77945  */
77946 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED 0x1
77947 
77948 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
77949 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_LSB 28
77950 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
77951 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_MSB 28
77952 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
77953 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_WIDTH 1
77954 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */
77955 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET_MSK 0x10000000
77956 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */
77957 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_CLR_MSK 0xefffffff
77958 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
77959 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_RESET 0x0
77960 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 field value from a register. */
77961 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
77962 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value suitable for setting the register. */
77963 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
77964 
77965 /*
77966  * Field : Mask Byte Control - mbc_5
77967  *
77968  * This array of bits are mask control bits for comparison of each of the MAC
77969  * Address bytes. When masked, the MAC does not compare the corresponding byte of
77970  * received DA or SA with the contents of MAC Address94 high and low registers.
77971  * Each bit controls the masking of the bytes. You can filter a group of addresses
77972  * (known as group address filtering) by masking one or more bytes of the address.
77973  *
77974  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
77975  *
77976  * Field Enumeration Values:
77977  *
77978  * Enum | Value | Description
77979  * :----------------------------------------------|:------|:------------------------------------
77980  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
77981  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
77982  *
77983  * Field Access Macros:
77984  *
77985  */
77986 /*
77987  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5
77988  *
77989  * Byte is unmasked (i.e. is compared)
77990  */
77991 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED 0x0
77992 /*
77993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5
77994  *
77995  * Byte is masked (i.e. not compared)
77996  */
77997 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED 0x1
77998 
77999 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
78000 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_LSB 29
78001 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
78002 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_MSB 29
78003 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
78004 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_WIDTH 1
78005 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */
78006 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET_MSK 0x20000000
78007 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */
78008 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_CLR_MSK 0xdfffffff
78009 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
78010 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_RESET 0x0
78011 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 field value from a register. */
78012 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
78013 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value suitable for setting the register. */
78014 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
78015 
78016 /*
78017  * Field : Source Address - sa
78018  *
78019  * When this bit is enabled, the MAC Address94[47:0] is used to compare with the SA
78020  * fields of the received frame. When this bit is disabled, the MAC Address94[47:0]
78021  * is used to compare with the DA fields of the received frame.
78022  *
78023  * Field Enumeration Values:
78024  *
78025  * Enum | Value | Description
78026  * :----------------------------------------|:------|:-----------------------------
78027  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
78028  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END | 0x1 | MAC address compare enabled
78029  *
78030  * Field Access Macros:
78031  *
78032  */
78033 /*
78034  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA
78035  *
78036  * MAC address compare disabled
78037  */
78038 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD 0x0
78039 /*
78040  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA
78041  *
78042  * MAC address compare enabled
78043  */
78044 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END 0x1
78045 
78046 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
78047 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_LSB 30
78048 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
78049 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_MSB 30
78050 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
78051 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_WIDTH 1
78052 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */
78053 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET_MSK 0x40000000
78054 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */
78055 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_CLR_MSK 0xbfffffff
78056 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
78057 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_RESET 0x0
78058 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA field value from a register. */
78059 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
78060 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value suitable for setting the register. */
78061 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
78062 
78063 /*
78064  * Field : Address Enable - ae
78065  *
78066  * When this bit is enabled, the address filter block uses the 95th MAC address for
78067  * perfect filtering. When this bit is disabled, the address filter block ignores
78068  * the address for filtering.
78069  *
78070  * Field Enumeration Values:
78071  *
78072  * Enum | Value | Description
78073  * :----------------------------------------|:------|:--------------------------------------
78074  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
78075  * ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
78076  *
78077  * Field Access Macros:
78078  *
78079  */
78080 /*
78081  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
78082  *
78083  * Second MAC address filtering disabled
78084  */
78085 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD 0x0
78086 /*
78087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
78088  *
78089  * Second MAC address filtering enabled
78090  */
78091 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END 0x1
78092 
78093 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
78094 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_LSB 31
78095 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
78096 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_MSB 31
78097 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
78098 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_WIDTH 1
78099 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
78100 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET_MSK 0x80000000
78101 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
78102 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_CLR_MSK 0x7fffffff
78103 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
78104 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_RESET 0x0
78105 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE field value from a register. */
78106 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
78107 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value suitable for setting the register. */
78108 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
78109 
78110 #ifndef __ASSEMBLY__
78111 /*
78112  * WARNING: The C register and register group struct declarations are provided for
78113  * convenience and illustrative purposes. They should, however, be used with
78114  * caution as the C language standard provides no guarantees about the alignment or
78115  * atomicity of device memory accesses. The recommended practice for writing
78116  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78117  * alt_write_word() functions.
78118  *
78119  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH.
78120  */
78121 struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s
78122 {
78123  uint32_t addrhi : 16; /* MAC Address94 [47:32] */
78124  uint32_t : 8; /* *UNDEFINED* */
78125  uint32_t mbc_0 : 1; /* Mask Byte Control */
78126  uint32_t mbc_1 : 1; /* Mask Byte Control */
78127  uint32_t mbc_2 : 1; /* Mask Byte Control */
78128  uint32_t mbc_3 : 1; /* Mask Byte Control */
78129  uint32_t mbc_4 : 1; /* Mask Byte Control */
78130  uint32_t mbc_5 : 1; /* Mask Byte Control */
78131  uint32_t sa : 1; /* Source Address */
78132  uint32_t ae : 1; /* Address Enable */
78133 };
78134 
78135 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH. */
78136 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t;
78137 #endif /* __ASSEMBLY__ */
78138 
78139 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register from the beginning of the component. */
78140 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST 0xa70
78141 /* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register. */
78142 #define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST))
78143 
78144 /*
78145  * Register : Register 669 (MAC Address94 Low Register) - MAC_Address94_Low
78146  *
78147  * The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC
78148  * address of the station.
78149  *
78150  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
78151  * format.
78152  *
78153  * Register Layout
78154  *
78155  * Bits | Access | Reset | Description
78156  * :-------|:-------|:-----------|:---------------------
78157  * [31:0] | RW | 0xffffffff | MAC Address94 [31:0]
78158  *
78159  */
78160 /*
78161  * Field : MAC Address94 [31:0] - addrlo
78162  *
78163  * This field contains the lower 32 bits of the 95th 6-byte MAC address. The
78164  * content of this field is undefined until loaded by software after the
78165  * initialization process.
78166  *
78167  * Field Access Macros:
78168  *
78169  */
78170 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
78171 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_LSB 0
78172 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
78173 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_MSB 31
78174 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
78175 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_WIDTH 32
78176 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
78177 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET_MSK 0xffffffff
78178 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
78179 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_CLR_MSK 0x00000000
78180 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
78181 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_RESET 0xffffffff
78182 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO field value from a register. */
78183 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
78184 /* Produces a ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value suitable for setting the register. */
78185 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
78186 
78187 #ifndef __ASSEMBLY__
78188 /*
78189  * WARNING: The C register and register group struct declarations are provided for
78190  * convenience and illustrative purposes. They should, however, be used with
78191  * caution as the C language standard provides no guarantees about the alignment or
78192  * atomicity of device memory accesses. The recommended practice for writing
78193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78194  * alt_write_word() functions.
78195  *
78196  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW.
78197  */
78198 struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s
78199 {
78200  uint32_t addrlo : 32; /* MAC Address94 [31:0] */
78201 };
78202 
78203 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW. */
78204 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s ALT_EMAC_GMAC_MAC_ADDR94_LOW_t;
78205 #endif /* __ASSEMBLY__ */
78206 
78207 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register from the beginning of the component. */
78208 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST 0xa74
78209 /* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register. */
78210 #define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST))
78211 
78212 /*
78213  * Register : Register 670 (MAC Address95 High Register) - MAC_Address95_High
78214  *
78215  * The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC
78216  * address of the station. Because the MAC address registers are configured to be
78217  * double-synchronized to the (G)MII clock domains, the synchronization is
78218  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
78219  * endian mode) of the MAC Address95 Low Register are written. For proper
78220  * synchronization updates, the consecutive writes to this Address Low Register
78221  * should be performed after at least four clock cycles in the destination clock
78222  * domain.
78223  *
78224  * Note that all MAC Address High registers (except MAC Address0 High) have the
78225  * same format.
78226  *
78227  * Register Layout
78228  *
78229  * Bits | Access | Reset | Description
78230  * :--------|:-------|:-------|:----------------------
78231  * [15:0] | RW | 0xffff | MAC Address95 [47:32]
78232  * [23:16] | ??? | 0x0 | *UNDEFINED*
78233  * [24] | RW | 0x0 | Mask Byte Control
78234  * [25] | RW | 0x0 | Mask Byte Control
78235  * [26] | RW | 0x0 | Mask Byte Control
78236  * [27] | RW | 0x0 | Mask Byte Control
78237  * [28] | RW | 0x0 | Mask Byte Control
78238  * [29] | RW | 0x0 | Mask Byte Control
78239  * [30] | RW | 0x0 | Source Address
78240  * [31] | RW | 0x0 | Address Enable
78241  *
78242  */
78243 /*
78244  * Field : MAC Address95 [47:32] - addrhi
78245  *
78246  * This field contains the upper 16 bits (47:32) of the 96th 6-byte MAC address.
78247  *
78248  * Field Access Macros:
78249  *
78250  */
78251 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
78252 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_LSB 0
78253 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
78254 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_MSB 15
78255 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
78256 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_WIDTH 16
78257 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
78258 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET_MSK 0x0000ffff
78259 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
78260 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_CLR_MSK 0xffff0000
78261 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
78262 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_RESET 0xffff
78263 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI field value from a register. */
78264 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
78265 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value suitable for setting the register. */
78266 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
78267 
78268 /*
78269  * Field : Mask Byte Control - mbc_0
78270  *
78271  * This array of bits are mask control bits for comparison of each of the MAC
78272  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78273  * received DA or SA with the contents of MAC Address95 high and low registers.
78274  * Each bit controls the masking of the bytes. You can filter a group of addresses
78275  * (known as group address filtering) by masking one or more bytes of the address.
78276  *
78277  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78278  *
78279  * Field Enumeration Values:
78280  *
78281  * Enum | Value | Description
78282  * :----------------------------------------------|:------|:------------------------------------
78283  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78284  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78285  *
78286  * Field Access Macros:
78287  *
78288  */
78289 /*
78290  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0
78291  *
78292  * Byte is unmasked (i.e. is compared)
78293  */
78294 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED 0x0
78295 /*
78296  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0
78297  *
78298  * Byte is masked (i.e. not compared)
78299  */
78300 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED 0x1
78301 
78302 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
78303 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_LSB 24
78304 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
78305 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_MSB 24
78306 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
78307 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_WIDTH 1
78308 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */
78309 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET_MSK 0x01000000
78310 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */
78311 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_CLR_MSK 0xfeffffff
78312 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
78313 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_RESET 0x0
78314 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 field value from a register. */
78315 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
78316 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value suitable for setting the register. */
78317 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
78318 
78319 /*
78320  * Field : Mask Byte Control - mbc_1
78321  *
78322  * This array of bits are mask control bits for comparison of each of the MAC
78323  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78324  * received DA or SA with the contents of MAC Address95 high and low registers.
78325  * Each bit controls the masking of the bytes. You can filter a group of addresses
78326  * (known as group address filtering) by masking one or more bytes of the address.
78327  *
78328  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78329  *
78330  * Field Enumeration Values:
78331  *
78332  * Enum | Value | Description
78333  * :----------------------------------------------|:------|:------------------------------------
78334  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78335  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78336  *
78337  * Field Access Macros:
78338  *
78339  */
78340 /*
78341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1
78342  *
78343  * Byte is unmasked (i.e. is compared)
78344  */
78345 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED 0x0
78346 /*
78347  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1
78348  *
78349  * Byte is masked (i.e. not compared)
78350  */
78351 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED 0x1
78352 
78353 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
78354 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_LSB 25
78355 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
78356 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_MSB 25
78357 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
78358 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_WIDTH 1
78359 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */
78360 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET_MSK 0x02000000
78361 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */
78362 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_CLR_MSK 0xfdffffff
78363 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
78364 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_RESET 0x0
78365 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 field value from a register. */
78366 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
78367 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value suitable for setting the register. */
78368 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
78369 
78370 /*
78371  * Field : Mask Byte Control - mbc_2
78372  *
78373  * This array of bits are mask control bits for comparison of each of the MAC
78374  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78375  * received DA or SA with the contents of MAC Address95 high and low registers.
78376  * Each bit controls the masking of the bytes. You can filter a group of addresses
78377  * (known as group address filtering) by masking one or more bytes of the address.
78378  *
78379  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78380  *
78381  * Field Enumeration Values:
78382  *
78383  * Enum | Value | Description
78384  * :----------------------------------------------|:------|:------------------------------------
78385  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78386  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78387  *
78388  * Field Access Macros:
78389  *
78390  */
78391 /*
78392  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2
78393  *
78394  * Byte is unmasked (i.e. is compared)
78395  */
78396 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED 0x0
78397 /*
78398  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2
78399  *
78400  * Byte is masked (i.e. not compared)
78401  */
78402 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED 0x1
78403 
78404 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
78405 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_LSB 26
78406 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
78407 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_MSB 26
78408 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
78409 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_WIDTH 1
78410 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */
78411 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET_MSK 0x04000000
78412 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */
78413 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_CLR_MSK 0xfbffffff
78414 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
78415 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_RESET 0x0
78416 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 field value from a register. */
78417 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
78418 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value suitable for setting the register. */
78419 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
78420 
78421 /*
78422  * Field : Mask Byte Control - mbc_3
78423  *
78424  * This array of bits are mask control bits for comparison of each of the MAC
78425  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78426  * received DA or SA with the contents of MAC Address95 high and low registers.
78427  * Each bit controls the masking of the bytes. You can filter a group of addresses
78428  * (known as group address filtering) by masking one or more bytes of the address.
78429  *
78430  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78431  *
78432  * Field Enumeration Values:
78433  *
78434  * Enum | Value | Description
78435  * :----------------------------------------------|:------|:------------------------------------
78436  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78437  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78438  *
78439  * Field Access Macros:
78440  *
78441  */
78442 /*
78443  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3
78444  *
78445  * Byte is unmasked (i.e. is compared)
78446  */
78447 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED 0x0
78448 /*
78449  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3
78450  *
78451  * Byte is masked (i.e. not compared)
78452  */
78453 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED 0x1
78454 
78455 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
78456 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_LSB 27
78457 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
78458 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_MSB 27
78459 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
78460 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_WIDTH 1
78461 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */
78462 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET_MSK 0x08000000
78463 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */
78464 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_CLR_MSK 0xf7ffffff
78465 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
78466 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_RESET 0x0
78467 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 field value from a register. */
78468 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
78469 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value suitable for setting the register. */
78470 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
78471 
78472 /*
78473  * Field : Mask Byte Control - mbc_4
78474  *
78475  * This array of bits are mask control bits for comparison of each of the MAC
78476  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78477  * received DA or SA with the contents of MAC Address95 high and low registers.
78478  * Each bit controls the masking of the bytes. You can filter a group of addresses
78479  * (known as group address filtering) by masking one or more bytes of the address.
78480  *
78481  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78482  *
78483  * Field Enumeration Values:
78484  *
78485  * Enum | Value | Description
78486  * :----------------------------------------------|:------|:------------------------------------
78487  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78488  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78489  *
78490  * Field Access Macros:
78491  *
78492  */
78493 /*
78494  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4
78495  *
78496  * Byte is unmasked (i.e. is compared)
78497  */
78498 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED 0x0
78499 /*
78500  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4
78501  *
78502  * Byte is masked (i.e. not compared)
78503  */
78504 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED 0x1
78505 
78506 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
78507 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_LSB 28
78508 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
78509 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_MSB 28
78510 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
78511 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_WIDTH 1
78512 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */
78513 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET_MSK 0x10000000
78514 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */
78515 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_CLR_MSK 0xefffffff
78516 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
78517 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_RESET 0x0
78518 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 field value from a register. */
78519 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
78520 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value suitable for setting the register. */
78521 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
78522 
78523 /*
78524  * Field : Mask Byte Control - mbc_5
78525  *
78526  * This array of bits are mask control bits for comparison of each of the MAC
78527  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78528  * received DA or SA with the contents of MAC Address95 high and low registers.
78529  * Each bit controls the masking of the bytes. You can filter a group of addresses
78530  * (known as group address filtering) by masking one or more bytes of the address.
78531  *
78532  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78533  *
78534  * Field Enumeration Values:
78535  *
78536  * Enum | Value | Description
78537  * :----------------------------------------------|:------|:------------------------------------
78538  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78539  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78540  *
78541  * Field Access Macros:
78542  *
78543  */
78544 /*
78545  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5
78546  *
78547  * Byte is unmasked (i.e. is compared)
78548  */
78549 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED 0x0
78550 /*
78551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5
78552  *
78553  * Byte is masked (i.e. not compared)
78554  */
78555 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED 0x1
78556 
78557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
78558 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_LSB 29
78559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
78560 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_MSB 29
78561 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
78562 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_WIDTH 1
78563 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */
78564 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET_MSK 0x20000000
78565 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */
78566 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_CLR_MSK 0xdfffffff
78567 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
78568 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_RESET 0x0
78569 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 field value from a register. */
78570 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
78571 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value suitable for setting the register. */
78572 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
78573 
78574 /*
78575  * Field : Source Address - sa
78576  *
78577  * When this bit is enabled, the MAC Address95[47:0] is used to compare with the SA
78578  * fields of the received frame. When this bit is disabled, the MAC Address95[47:0]
78579  * is used to compare with the DA fields of the received frame.
78580  *
78581  * Field Enumeration Values:
78582  *
78583  * Enum | Value | Description
78584  * :----------------------------------------|:------|:-----------------------------
78585  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
78586  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END | 0x1 | MAC address compare enabled
78587  *
78588  * Field Access Macros:
78589  *
78590  */
78591 /*
78592  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA
78593  *
78594  * MAC address compare disabled
78595  */
78596 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD 0x0
78597 /*
78598  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA
78599  *
78600  * MAC address compare enabled
78601  */
78602 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END 0x1
78603 
78604 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
78605 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_LSB 30
78606 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
78607 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_MSB 30
78608 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
78609 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_WIDTH 1
78610 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */
78611 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET_MSK 0x40000000
78612 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */
78613 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_CLR_MSK 0xbfffffff
78614 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
78615 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_RESET 0x0
78616 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA field value from a register. */
78617 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
78618 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value suitable for setting the register. */
78619 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
78620 
78621 /*
78622  * Field : Address Enable - ae
78623  *
78624  * When this bit is enabled, the address filter block uses the 96th MAC address for
78625  * perfect filtering. When this bit is disabled, the address filter block ignores
78626  * the address for filtering.
78627  *
78628  * Field Enumeration Values:
78629  *
78630  * Enum | Value | Description
78631  * :----------------------------------------|:------|:--------------------------------------
78632  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
78633  * ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
78634  *
78635  * Field Access Macros:
78636  *
78637  */
78638 /*
78639  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
78640  *
78641  * Second MAC address filtering disabled
78642  */
78643 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD 0x0
78644 /*
78645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
78646  *
78647  * Second MAC address filtering enabled
78648  */
78649 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END 0x1
78650 
78651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
78652 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_LSB 31
78653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
78654 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_MSB 31
78655 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
78656 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_WIDTH 1
78657 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
78658 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET_MSK 0x80000000
78659 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
78660 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_CLR_MSK 0x7fffffff
78661 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
78662 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_RESET 0x0
78663 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE field value from a register. */
78664 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
78665 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value suitable for setting the register. */
78666 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
78667 
78668 #ifndef __ASSEMBLY__
78669 /*
78670  * WARNING: The C register and register group struct declarations are provided for
78671  * convenience and illustrative purposes. They should, however, be used with
78672  * caution as the C language standard provides no guarantees about the alignment or
78673  * atomicity of device memory accesses. The recommended practice for writing
78674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78675  * alt_write_word() functions.
78676  *
78677  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH.
78678  */
78679 struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s
78680 {
78681  uint32_t addrhi : 16; /* MAC Address95 [47:32] */
78682  uint32_t : 8; /* *UNDEFINED* */
78683  uint32_t mbc_0 : 1; /* Mask Byte Control */
78684  uint32_t mbc_1 : 1; /* Mask Byte Control */
78685  uint32_t mbc_2 : 1; /* Mask Byte Control */
78686  uint32_t mbc_3 : 1; /* Mask Byte Control */
78687  uint32_t mbc_4 : 1; /* Mask Byte Control */
78688  uint32_t mbc_5 : 1; /* Mask Byte Control */
78689  uint32_t sa : 1; /* Source Address */
78690  uint32_t ae : 1; /* Address Enable */
78691 };
78692 
78693 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH. */
78694 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t;
78695 #endif /* __ASSEMBLY__ */
78696 
78697 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register from the beginning of the component. */
78698 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST 0xa78
78699 /* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register. */
78700 #define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST))
78701 
78702 /*
78703  * Register : Register 671 (MAC Address95 Low Register) - MAC_Address95_Low
78704  *
78705  * The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC
78706  * address of the station.
78707  *
78708  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
78709  * format.
78710  *
78711  * Register Layout
78712  *
78713  * Bits | Access | Reset | Description
78714  * :-------|:-------|:-----------|:---------------------
78715  * [31:0] | RW | 0xffffffff | MAC Address95 [31:0]
78716  *
78717  */
78718 /*
78719  * Field : MAC Address95 [31:0] - addrlo
78720  *
78721  * This field contains the lower 32 bits of the 96th 6-byte MAC address. The
78722  * content of this field is undefined until loaded by software after the
78723  * initialization process.
78724  *
78725  * Field Access Macros:
78726  *
78727  */
78728 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
78729 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_LSB 0
78730 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
78731 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_MSB 31
78732 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
78733 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_WIDTH 32
78734 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
78735 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET_MSK 0xffffffff
78736 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
78737 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_CLR_MSK 0x00000000
78738 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
78739 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_RESET 0xffffffff
78740 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO field value from a register. */
78741 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
78742 /* Produces a ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value suitable for setting the register. */
78743 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
78744 
78745 #ifndef __ASSEMBLY__
78746 /*
78747  * WARNING: The C register and register group struct declarations are provided for
78748  * convenience and illustrative purposes. They should, however, be used with
78749  * caution as the C language standard provides no guarantees about the alignment or
78750  * atomicity of device memory accesses. The recommended practice for writing
78751  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
78752  * alt_write_word() functions.
78753  *
78754  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW.
78755  */
78756 struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s
78757 {
78758  uint32_t addrlo : 32; /* MAC Address95 [31:0] */
78759 };
78760 
78761 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW. */
78762 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s ALT_EMAC_GMAC_MAC_ADDR95_LOW_t;
78763 #endif /* __ASSEMBLY__ */
78764 
78765 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register from the beginning of the component. */
78766 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST 0xa7c
78767 /* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register. */
78768 #define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST))
78769 
78770 /*
78771  * Register : Register 672 (MAC Address96 High Register) - MAC_Address96_High
78772  *
78773  * The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC
78774  * address of the station. Because the MAC address registers are configured to be
78775  * double-synchronized to the (G)MII clock domains, the synchronization is
78776  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
78777  * endian mode) of the MAC Address96 Low Register are written. For proper
78778  * synchronization updates, the consecutive writes to this Address Low Register
78779  * should be performed after at least four clock cycles in the destination clock
78780  * domain.
78781  *
78782  * Note that all MAC Address High registers (except MAC Address0 High) have the
78783  * same format.
78784  *
78785  * Register Layout
78786  *
78787  * Bits | Access | Reset | Description
78788  * :--------|:-------|:-------|:----------------------
78789  * [15:0] | RW | 0xffff | MAC Address96 [47:32]
78790  * [23:16] | ??? | 0x0 | *UNDEFINED*
78791  * [24] | RW | 0x0 | Mask Byte Control
78792  * [25] | RW | 0x0 | Mask Byte Control
78793  * [26] | RW | 0x0 | Mask Byte Control
78794  * [27] | RW | 0x0 | Mask Byte Control
78795  * [28] | RW | 0x0 | Mask Byte Control
78796  * [29] | RW | 0x0 | Mask Byte Control
78797  * [30] | RW | 0x0 | Source Address
78798  * [31] | RW | 0x0 | Address Enable
78799  *
78800  */
78801 /*
78802  * Field : MAC Address96 [47:32] - addrhi
78803  *
78804  * This field contains the upper 16 bits (47:32) of the 97th 6-byte MAC address.
78805  *
78806  * Field Access Macros:
78807  *
78808  */
78809 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
78810 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_LSB 0
78811 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
78812 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_MSB 15
78813 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
78814 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_WIDTH 16
78815 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
78816 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET_MSK 0x0000ffff
78817 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
78818 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_CLR_MSK 0xffff0000
78819 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
78820 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_RESET 0xffff
78821 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI field value from a register. */
78822 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
78823 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value suitable for setting the register. */
78824 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
78825 
78826 /*
78827  * Field : Mask Byte Control - mbc_0
78828  *
78829  * This array of bits are mask control bits for comparison of each of the MAC
78830  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78831  * received DA or SA with the contents of MAC Address96 high and low registers.
78832  * Each bit controls the masking of the bytes. You can filter a group of addresses
78833  * (known as group address filtering) by masking one or more bytes of the address.
78834  *
78835  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78836  *
78837  * Field Enumeration Values:
78838  *
78839  * Enum | Value | Description
78840  * :----------------------------------------------|:------|:------------------------------------
78841  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78842  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78843  *
78844  * Field Access Macros:
78845  *
78846  */
78847 /*
78848  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0
78849  *
78850  * Byte is unmasked (i.e. is compared)
78851  */
78852 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED 0x0
78853 /*
78854  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0
78855  *
78856  * Byte is masked (i.e. not compared)
78857  */
78858 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED 0x1
78859 
78860 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
78861 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_LSB 24
78862 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
78863 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_MSB 24
78864 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
78865 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_WIDTH 1
78866 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */
78867 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET_MSK 0x01000000
78868 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */
78869 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_CLR_MSK 0xfeffffff
78870 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
78871 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_RESET 0x0
78872 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 field value from a register. */
78873 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
78874 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value suitable for setting the register. */
78875 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
78876 
78877 /*
78878  * Field : Mask Byte Control - mbc_1
78879  *
78880  * This array of bits are mask control bits for comparison of each of the MAC
78881  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78882  * received DA or SA with the contents of MAC Address96 high and low registers.
78883  * Each bit controls the masking of the bytes. You can filter a group of addresses
78884  * (known as group address filtering) by masking one or more bytes of the address.
78885  *
78886  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78887  *
78888  * Field Enumeration Values:
78889  *
78890  * Enum | Value | Description
78891  * :----------------------------------------------|:------|:------------------------------------
78892  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78893  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78894  *
78895  * Field Access Macros:
78896  *
78897  */
78898 /*
78899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1
78900  *
78901  * Byte is unmasked (i.e. is compared)
78902  */
78903 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED 0x0
78904 /*
78905  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1
78906  *
78907  * Byte is masked (i.e. not compared)
78908  */
78909 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED 0x1
78910 
78911 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
78912 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_LSB 25
78913 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
78914 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_MSB 25
78915 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
78916 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_WIDTH 1
78917 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */
78918 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET_MSK 0x02000000
78919 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */
78920 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_CLR_MSK 0xfdffffff
78921 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
78922 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_RESET 0x0
78923 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 field value from a register. */
78924 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
78925 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value suitable for setting the register. */
78926 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
78927 
78928 /*
78929  * Field : Mask Byte Control - mbc_2
78930  *
78931  * This array of bits are mask control bits for comparison of each of the MAC
78932  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78933  * received DA or SA with the contents of MAC Address96 high and low registers.
78934  * Each bit controls the masking of the bytes. You can filter a group of addresses
78935  * (known as group address filtering) by masking one or more bytes of the address.
78936  *
78937  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78938  *
78939  * Field Enumeration Values:
78940  *
78941  * Enum | Value | Description
78942  * :----------------------------------------------|:------|:------------------------------------
78943  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78944  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78945  *
78946  * Field Access Macros:
78947  *
78948  */
78949 /*
78950  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2
78951  *
78952  * Byte is unmasked (i.e. is compared)
78953  */
78954 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED 0x0
78955 /*
78956  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2
78957  *
78958  * Byte is masked (i.e. not compared)
78959  */
78960 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED 0x1
78961 
78962 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
78963 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_LSB 26
78964 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
78965 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_MSB 26
78966 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
78967 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_WIDTH 1
78968 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */
78969 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET_MSK 0x04000000
78970 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */
78971 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_CLR_MSK 0xfbffffff
78972 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
78973 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_RESET 0x0
78974 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 field value from a register. */
78975 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
78976 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value suitable for setting the register. */
78977 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
78978 
78979 /*
78980  * Field : Mask Byte Control - mbc_3
78981  *
78982  * This array of bits are mask control bits for comparison of each of the MAC
78983  * Address bytes. When masked, the MAC does not compare the corresponding byte of
78984  * received DA or SA with the contents of MAC Address96 high and low registers.
78985  * Each bit controls the masking of the bytes. You can filter a group of addresses
78986  * (known as group address filtering) by masking one or more bytes of the address.
78987  *
78988  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
78989  *
78990  * Field Enumeration Values:
78991  *
78992  * Enum | Value | Description
78993  * :----------------------------------------------|:------|:------------------------------------
78994  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
78995  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
78996  *
78997  * Field Access Macros:
78998  *
78999  */
79000 /*
79001  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3
79002  *
79003  * Byte is unmasked (i.e. is compared)
79004  */
79005 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED 0x0
79006 /*
79007  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3
79008  *
79009  * Byte is masked (i.e. not compared)
79010  */
79011 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED 0x1
79012 
79013 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
79014 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_LSB 27
79015 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
79016 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_MSB 27
79017 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
79018 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_WIDTH 1
79019 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */
79020 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET_MSK 0x08000000
79021 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */
79022 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_CLR_MSK 0xf7ffffff
79023 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
79024 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_RESET 0x0
79025 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 field value from a register. */
79026 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
79027 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value suitable for setting the register. */
79028 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
79029 
79030 /*
79031  * Field : Mask Byte Control - mbc_4
79032  *
79033  * This array of bits are mask control bits for comparison of each of the MAC
79034  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79035  * received DA or SA with the contents of MAC Address96 high and low registers.
79036  * Each bit controls the masking of the bytes. You can filter a group of addresses
79037  * (known as group address filtering) by masking one or more bytes of the address.
79038  *
79039  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79040  *
79041  * Field Enumeration Values:
79042  *
79043  * Enum | Value | Description
79044  * :----------------------------------------------|:------|:------------------------------------
79045  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79046  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79047  *
79048  * Field Access Macros:
79049  *
79050  */
79051 /*
79052  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4
79053  *
79054  * Byte is unmasked (i.e. is compared)
79055  */
79056 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED 0x0
79057 /*
79058  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4
79059  *
79060  * Byte is masked (i.e. not compared)
79061  */
79062 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED 0x1
79063 
79064 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
79065 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_LSB 28
79066 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
79067 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_MSB 28
79068 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
79069 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_WIDTH 1
79070 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */
79071 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET_MSK 0x10000000
79072 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */
79073 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_CLR_MSK 0xefffffff
79074 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
79075 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_RESET 0x0
79076 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 field value from a register. */
79077 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
79078 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value suitable for setting the register. */
79079 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
79080 
79081 /*
79082  * Field : Mask Byte Control - mbc_5
79083  *
79084  * This array of bits are mask control bits for comparison of each of the MAC
79085  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79086  * received DA or SA with the contents of MAC Address96 high and low registers.
79087  * Each bit controls the masking of the bytes. You can filter a group of addresses
79088  * (known as group address filtering) by masking one or more bytes of the address.
79089  *
79090  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79091  *
79092  * Field Enumeration Values:
79093  *
79094  * Enum | Value | Description
79095  * :----------------------------------------------|:------|:------------------------------------
79096  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79097  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79098  *
79099  * Field Access Macros:
79100  *
79101  */
79102 /*
79103  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5
79104  *
79105  * Byte is unmasked (i.e. is compared)
79106  */
79107 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED 0x0
79108 /*
79109  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5
79110  *
79111  * Byte is masked (i.e. not compared)
79112  */
79113 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED 0x1
79114 
79115 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
79116 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_LSB 29
79117 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
79118 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_MSB 29
79119 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
79120 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_WIDTH 1
79121 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */
79122 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET_MSK 0x20000000
79123 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */
79124 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_CLR_MSK 0xdfffffff
79125 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
79126 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_RESET 0x0
79127 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 field value from a register. */
79128 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
79129 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value suitable for setting the register. */
79130 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
79131 
79132 /*
79133  * Field : Source Address - sa
79134  *
79135  * When this bit is enabled, the MAC Address96[47:0] is used to compare with the SA
79136  * fields of the received frame. When this bit is disabled, the MAC Address96[47:0]
79137  * is used to compare with the DA fields of the received frame.
79138  *
79139  * Field Enumeration Values:
79140  *
79141  * Enum | Value | Description
79142  * :----------------------------------------|:------|:-----------------------------
79143  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
79144  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END | 0x1 | MAC address compare enabled
79145  *
79146  * Field Access Macros:
79147  *
79148  */
79149 /*
79150  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA
79151  *
79152  * MAC address compare disabled
79153  */
79154 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD 0x0
79155 /*
79156  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA
79157  *
79158  * MAC address compare enabled
79159  */
79160 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END 0x1
79161 
79162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
79163 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_LSB 30
79164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
79165 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_MSB 30
79166 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
79167 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_WIDTH 1
79168 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */
79169 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET_MSK 0x40000000
79170 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */
79171 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_CLR_MSK 0xbfffffff
79172 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
79173 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_RESET 0x0
79174 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA field value from a register. */
79175 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
79176 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value suitable for setting the register. */
79177 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
79178 
79179 /*
79180  * Field : Address Enable - ae
79181  *
79182  * When this bit is enabled, the address filter block uses the 97th MAC address for
79183  * perfect filtering. When this bit is disabled, the address filter block ignores
79184  * the address for filtering.
79185  *
79186  * Field Enumeration Values:
79187  *
79188  * Enum | Value | Description
79189  * :----------------------------------------|:------|:--------------------------------------
79190  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
79191  * ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
79192  *
79193  * Field Access Macros:
79194  *
79195  */
79196 /*
79197  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
79198  *
79199  * Second MAC address filtering disabled
79200  */
79201 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD 0x0
79202 /*
79203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
79204  *
79205  * Second MAC address filtering enabled
79206  */
79207 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END 0x1
79208 
79209 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
79210 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_LSB 31
79211 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
79212 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_MSB 31
79213 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
79214 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_WIDTH 1
79215 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
79216 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET_MSK 0x80000000
79217 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
79218 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_CLR_MSK 0x7fffffff
79219 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
79220 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_RESET 0x0
79221 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE field value from a register. */
79222 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
79223 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value suitable for setting the register. */
79224 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
79225 
79226 #ifndef __ASSEMBLY__
79227 /*
79228  * WARNING: The C register and register group struct declarations are provided for
79229  * convenience and illustrative purposes. They should, however, be used with
79230  * caution as the C language standard provides no guarantees about the alignment or
79231  * atomicity of device memory accesses. The recommended practice for writing
79232  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
79233  * alt_write_word() functions.
79234  *
79235  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH.
79236  */
79237 struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s
79238 {
79239  uint32_t addrhi : 16; /* MAC Address96 [47:32] */
79240  uint32_t : 8; /* *UNDEFINED* */
79241  uint32_t mbc_0 : 1; /* Mask Byte Control */
79242  uint32_t mbc_1 : 1; /* Mask Byte Control */
79243  uint32_t mbc_2 : 1; /* Mask Byte Control */
79244  uint32_t mbc_3 : 1; /* Mask Byte Control */
79245  uint32_t mbc_4 : 1; /* Mask Byte Control */
79246  uint32_t mbc_5 : 1; /* Mask Byte Control */
79247  uint32_t sa : 1; /* Source Address */
79248  uint32_t ae : 1; /* Address Enable */
79249 };
79250 
79251 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH. */
79252 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t;
79253 #endif /* __ASSEMBLY__ */
79254 
79255 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register from the beginning of the component. */
79256 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST 0xa80
79257 /* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register. */
79258 #define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST))
79259 
79260 /*
79261  * Register : Register 673 (MAC Address96 Low Register) - MAC_Address96_Low
79262  *
79263  * The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC
79264  * address of the station.
79265  *
79266  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
79267  * format.
79268  *
79269  * Register Layout
79270  *
79271  * Bits | Access | Reset | Description
79272  * :-------|:-------|:-----------|:---------------------
79273  * [31:0] | RW | 0xffffffff | MAC Address96 [31:0]
79274  *
79275  */
79276 /*
79277  * Field : MAC Address96 [31:0] - addrlo
79278  *
79279  * This field contains the lower 32 bits of the 97th 6-byte MAC address. The
79280  * content of this field is undefined until loaded by software after the
79281  * initialization process.
79282  *
79283  * Field Access Macros:
79284  *
79285  */
79286 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
79287 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_LSB 0
79288 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
79289 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_MSB 31
79290 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
79291 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_WIDTH 32
79292 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
79293 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET_MSK 0xffffffff
79294 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
79295 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_CLR_MSK 0x00000000
79296 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
79297 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_RESET 0xffffffff
79298 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO field value from a register. */
79299 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
79300 /* Produces a ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value suitable for setting the register. */
79301 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
79302 
79303 #ifndef __ASSEMBLY__
79304 /*
79305  * WARNING: The C register and register group struct declarations are provided for
79306  * convenience and illustrative purposes. They should, however, be used with
79307  * caution as the C language standard provides no guarantees about the alignment or
79308  * atomicity of device memory accesses. The recommended practice for writing
79309  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
79310  * alt_write_word() functions.
79311  *
79312  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW.
79313  */
79314 struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s
79315 {
79316  uint32_t addrlo : 32; /* MAC Address96 [31:0] */
79317 };
79318 
79319 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW. */
79320 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s ALT_EMAC_GMAC_MAC_ADDR96_LOW_t;
79321 #endif /* __ASSEMBLY__ */
79322 
79323 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register from the beginning of the component. */
79324 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST 0xa84
79325 /* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register. */
79326 #define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST))
79327 
79328 /*
79329  * Register : Register 674 (MAC Address97 High Register) - MAC_Address97_High
79330  *
79331  * The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC
79332  * address of the station. Because the MAC address registers are configured to be
79333  * double-synchronized to the (G)MII clock domains, the synchronization is
79334  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
79335  * endian mode) of the MAC Address97 Low Register are written. For proper
79336  * synchronization updates, the consecutive writes to this Address Low Register
79337  * should be performed after at least four clock cycles in the destination clock
79338  * domain.
79339  *
79340  * Note that all MAC Address High registers (except MAC Address0 High) have the
79341  * same format.
79342  *
79343  * Register Layout
79344  *
79345  * Bits | Access | Reset | Description
79346  * :--------|:-------|:-------|:----------------------
79347  * [15:0] | RW | 0xffff | MAC Address97 [47:32]
79348  * [23:16] | ??? | 0x0 | *UNDEFINED*
79349  * [24] | RW | 0x0 | Mask Byte Control
79350  * [25] | RW | 0x0 | Mask Byte Control
79351  * [26] | RW | 0x0 | Mask Byte Control
79352  * [27] | RW | 0x0 | Mask Byte Control
79353  * [28] | RW | 0x0 | Mask Byte Control
79354  * [29] | RW | 0x0 | Mask Byte Control
79355  * [30] | RW | 0x0 | Source Address
79356  * [31] | RW | 0x0 | Address Enable
79357  *
79358  */
79359 /*
79360  * Field : MAC Address97 [47:32] - addrhi
79361  *
79362  * This field contains the upper 16 bits (47:32) of the 98th 6-byte MAC address.
79363  *
79364  * Field Access Macros:
79365  *
79366  */
79367 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
79368 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_LSB 0
79369 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
79370 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_MSB 15
79371 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
79372 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_WIDTH 16
79373 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
79374 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET_MSK 0x0000ffff
79375 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
79376 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_CLR_MSK 0xffff0000
79377 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
79378 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_RESET 0xffff
79379 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI field value from a register. */
79380 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
79381 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value suitable for setting the register. */
79382 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
79383 
79384 /*
79385  * Field : Mask Byte Control - mbc_0
79386  *
79387  * This array of bits are mask control bits for comparison of each of the MAC
79388  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79389  * received DA or SA with the contents of MAC Address97 high and low registers.
79390  * Each bit controls the masking of the bytes. You can filter a group of addresses
79391  * (known as group address filtering) by masking one or more bytes of the address.
79392  *
79393  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79394  *
79395  * Field Enumeration Values:
79396  *
79397  * Enum | Value | Description
79398  * :----------------------------------------------|:------|:------------------------------------
79399  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79400  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79401  *
79402  * Field Access Macros:
79403  *
79404  */
79405 /*
79406  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0
79407  *
79408  * Byte is unmasked (i.e. is compared)
79409  */
79410 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED 0x0
79411 /*
79412  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0
79413  *
79414  * Byte is masked (i.e. not compared)
79415  */
79416 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED 0x1
79417 
79418 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
79419 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_LSB 24
79420 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
79421 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_MSB 24
79422 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
79423 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_WIDTH 1
79424 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */
79425 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET_MSK 0x01000000
79426 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */
79427 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_CLR_MSK 0xfeffffff
79428 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
79429 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_RESET 0x0
79430 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 field value from a register. */
79431 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
79432 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value suitable for setting the register. */
79433 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
79434 
79435 /*
79436  * Field : Mask Byte Control - mbc_1
79437  *
79438  * This array of bits are mask control bits for comparison of each of the MAC
79439  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79440  * received DA or SA with the contents of MAC Address97 high and low registers.
79441  * Each bit controls the masking of the bytes. You can filter a group of addresses
79442  * (known as group address filtering) by masking one or more bytes of the address.
79443  *
79444  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79445  *
79446  * Field Enumeration Values:
79447  *
79448  * Enum | Value | Description
79449  * :----------------------------------------------|:------|:------------------------------------
79450  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79451  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79452  *
79453  * Field Access Macros:
79454  *
79455  */
79456 /*
79457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1
79458  *
79459  * Byte is unmasked (i.e. is compared)
79460  */
79461 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED 0x0
79462 /*
79463  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1
79464  *
79465  * Byte is masked (i.e. not compared)
79466  */
79467 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED 0x1
79468 
79469 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
79470 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_LSB 25
79471 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
79472 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_MSB 25
79473 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
79474 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_WIDTH 1
79475 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */
79476 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET_MSK 0x02000000
79477 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */
79478 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_CLR_MSK 0xfdffffff
79479 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
79480 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_RESET 0x0
79481 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 field value from a register. */
79482 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
79483 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value suitable for setting the register. */
79484 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
79485 
79486 /*
79487  * Field : Mask Byte Control - mbc_2
79488  *
79489  * This array of bits are mask control bits for comparison of each of the MAC
79490  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79491  * received DA or SA with the contents of MAC Address97 high and low registers.
79492  * Each bit controls the masking of the bytes. You can filter a group of addresses
79493  * (known as group address filtering) by masking one or more bytes of the address.
79494  *
79495  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79496  *
79497  * Field Enumeration Values:
79498  *
79499  * Enum | Value | Description
79500  * :----------------------------------------------|:------|:------------------------------------
79501  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79502  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79503  *
79504  * Field Access Macros:
79505  *
79506  */
79507 /*
79508  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2
79509  *
79510  * Byte is unmasked (i.e. is compared)
79511  */
79512 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED 0x0
79513 /*
79514  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2
79515  *
79516  * Byte is masked (i.e. not compared)
79517  */
79518 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED 0x1
79519 
79520 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
79521 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_LSB 26
79522 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
79523 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_MSB 26
79524 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
79525 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_WIDTH 1
79526 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */
79527 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET_MSK 0x04000000
79528 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */
79529 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_CLR_MSK 0xfbffffff
79530 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
79531 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_RESET 0x0
79532 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 field value from a register. */
79533 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
79534 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value suitable for setting the register. */
79535 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
79536 
79537 /*
79538  * Field : Mask Byte Control - mbc_3
79539  *
79540  * This array of bits are mask control bits for comparison of each of the MAC
79541  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79542  * received DA or SA with the contents of MAC Address97 high and low registers.
79543  * Each bit controls the masking of the bytes. You can filter a group of addresses
79544  * (known as group address filtering) by masking one or more bytes of the address.
79545  *
79546  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79547  *
79548  * Field Enumeration Values:
79549  *
79550  * Enum | Value | Description
79551  * :----------------------------------------------|:------|:------------------------------------
79552  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79553  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79554  *
79555  * Field Access Macros:
79556  *
79557  */
79558 /*
79559  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3
79560  *
79561  * Byte is unmasked (i.e. is compared)
79562  */
79563 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED 0x0
79564 /*
79565  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3
79566  *
79567  * Byte is masked (i.e. not compared)
79568  */
79569 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED 0x1
79570 
79571 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
79572 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_LSB 27
79573 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
79574 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_MSB 27
79575 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
79576 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_WIDTH 1
79577 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */
79578 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET_MSK 0x08000000
79579 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */
79580 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_CLR_MSK 0xf7ffffff
79581 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
79582 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_RESET 0x0
79583 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 field value from a register. */
79584 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
79585 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value suitable for setting the register. */
79586 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
79587 
79588 /*
79589  * Field : Mask Byte Control - mbc_4
79590  *
79591  * This array of bits are mask control bits for comparison of each of the MAC
79592  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79593  * received DA or SA with the contents of MAC Address97 high and low registers.
79594  * Each bit controls the masking of the bytes. You can filter a group of addresses
79595  * (known as group address filtering) by masking one or more bytes of the address.
79596  *
79597  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79598  *
79599  * Field Enumeration Values:
79600  *
79601  * Enum | Value | Description
79602  * :----------------------------------------------|:------|:------------------------------------
79603  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79604  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79605  *
79606  * Field Access Macros:
79607  *
79608  */
79609 /*
79610  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4
79611  *
79612  * Byte is unmasked (i.e. is compared)
79613  */
79614 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED 0x0
79615 /*
79616  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4
79617  *
79618  * Byte is masked (i.e. not compared)
79619  */
79620 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED 0x1
79621 
79622 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
79623 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_LSB 28
79624 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
79625 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_MSB 28
79626 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
79627 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_WIDTH 1
79628 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */
79629 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET_MSK 0x10000000
79630 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */
79631 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_CLR_MSK 0xefffffff
79632 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
79633 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_RESET 0x0
79634 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 field value from a register. */
79635 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
79636 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value suitable for setting the register. */
79637 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
79638 
79639 /*
79640  * Field : Mask Byte Control - mbc_5
79641  *
79642  * This array of bits are mask control bits for comparison of each of the MAC
79643  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79644  * received DA or SA with the contents of MAC Address97 high and low registers.
79645  * Each bit controls the masking of the bytes. You can filter a group of addresses
79646  * (known as group address filtering) by masking one or more bytes of the address.
79647  *
79648  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79649  *
79650  * Field Enumeration Values:
79651  *
79652  * Enum | Value | Description
79653  * :----------------------------------------------|:------|:------------------------------------
79654  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79655  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79656  *
79657  * Field Access Macros:
79658  *
79659  */
79660 /*
79661  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5
79662  *
79663  * Byte is unmasked (i.e. is compared)
79664  */
79665 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED 0x0
79666 /*
79667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5
79668  *
79669  * Byte is masked (i.e. not compared)
79670  */
79671 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED 0x1
79672 
79673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
79674 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_LSB 29
79675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
79676 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_MSB 29
79677 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
79678 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_WIDTH 1
79679 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */
79680 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET_MSK 0x20000000
79681 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */
79682 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_CLR_MSK 0xdfffffff
79683 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
79684 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_RESET 0x0
79685 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 field value from a register. */
79686 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
79687 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value suitable for setting the register. */
79688 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
79689 
79690 /*
79691  * Field : Source Address - sa
79692  *
79693  * When this bit is enabled, the MAC Address97[47:0] is used to compare with the SA
79694  * fields of the received frame. When this bit is disabled, the MAC Address97[47:0]
79695  * is used to compare with the DA fields of the received frame.
79696  *
79697  * Field Enumeration Values:
79698  *
79699  * Enum | Value | Description
79700  * :----------------------------------------|:------|:-----------------------------
79701  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
79702  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END | 0x1 | MAC address compare enabled
79703  *
79704  * Field Access Macros:
79705  *
79706  */
79707 /*
79708  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA
79709  *
79710  * MAC address compare disabled
79711  */
79712 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD 0x0
79713 /*
79714  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA
79715  *
79716  * MAC address compare enabled
79717  */
79718 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END 0x1
79719 
79720 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
79721 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_LSB 30
79722 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
79723 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_MSB 30
79724 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
79725 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_WIDTH 1
79726 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */
79727 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET_MSK 0x40000000
79728 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */
79729 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_CLR_MSK 0xbfffffff
79730 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
79731 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_RESET 0x0
79732 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA field value from a register. */
79733 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
79734 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value suitable for setting the register. */
79735 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
79736 
79737 /*
79738  * Field : Address Enable - ae
79739  *
79740  * When this bit is enabled, the address filter block uses the 98th MAC address for
79741  * perfect filtering. When this bit is disabled, the address filter block ignores
79742  * the address for filtering.
79743  *
79744  * Field Enumeration Values:
79745  *
79746  * Enum | Value | Description
79747  * :----------------------------------------|:------|:--------------------------------------
79748  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
79749  * ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
79750  *
79751  * Field Access Macros:
79752  *
79753  */
79754 /*
79755  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
79756  *
79757  * Second MAC address filtering disabled
79758  */
79759 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD 0x0
79760 /*
79761  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
79762  *
79763  * Second MAC address filtering enabled
79764  */
79765 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END 0x1
79766 
79767 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
79768 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_LSB 31
79769 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
79770 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_MSB 31
79771 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
79772 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_WIDTH 1
79773 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
79774 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET_MSK 0x80000000
79775 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
79776 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_CLR_MSK 0x7fffffff
79777 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
79778 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_RESET 0x0
79779 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE field value from a register. */
79780 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
79781 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value suitable for setting the register. */
79782 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
79783 
79784 #ifndef __ASSEMBLY__
79785 /*
79786  * WARNING: The C register and register group struct declarations are provided for
79787  * convenience and illustrative purposes. They should, however, be used with
79788  * caution as the C language standard provides no guarantees about the alignment or
79789  * atomicity of device memory accesses. The recommended practice for writing
79790  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
79791  * alt_write_word() functions.
79792  *
79793  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH.
79794  */
79795 struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s
79796 {
79797  uint32_t addrhi : 16; /* MAC Address97 [47:32] */
79798  uint32_t : 8; /* *UNDEFINED* */
79799  uint32_t mbc_0 : 1; /* Mask Byte Control */
79800  uint32_t mbc_1 : 1; /* Mask Byte Control */
79801  uint32_t mbc_2 : 1; /* Mask Byte Control */
79802  uint32_t mbc_3 : 1; /* Mask Byte Control */
79803  uint32_t mbc_4 : 1; /* Mask Byte Control */
79804  uint32_t mbc_5 : 1; /* Mask Byte Control */
79805  uint32_t sa : 1; /* Source Address */
79806  uint32_t ae : 1; /* Address Enable */
79807 };
79808 
79809 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH. */
79810 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t;
79811 #endif /* __ASSEMBLY__ */
79812 
79813 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register from the beginning of the component. */
79814 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST 0xa88
79815 /* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register. */
79816 #define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST))
79817 
79818 /*
79819  * Register : Register 675 (MAC Address97 Low Register) - MAC_Address97_Low
79820  *
79821  * The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC
79822  * address of the station.
79823  *
79824  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
79825  * format.
79826  *
79827  * Register Layout
79828  *
79829  * Bits | Access | Reset | Description
79830  * :-------|:-------|:-----------|:---------------------
79831  * [31:0] | RW | 0xffffffff | MAC Address97 [31:0]
79832  *
79833  */
79834 /*
79835  * Field : MAC Address97 [31:0] - addrlo
79836  *
79837  * This field contains the lower 32 bits of the 98th 6-byte MAC address. The
79838  * content of this field is undefined until loaded by software after the
79839  * initialization process.
79840  *
79841  * Field Access Macros:
79842  *
79843  */
79844 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
79845 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_LSB 0
79846 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
79847 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_MSB 31
79848 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
79849 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_WIDTH 32
79850 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
79851 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET_MSK 0xffffffff
79852 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
79853 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_CLR_MSK 0x00000000
79854 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
79855 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_RESET 0xffffffff
79856 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO field value from a register. */
79857 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
79858 /* Produces a ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value suitable for setting the register. */
79859 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
79860 
79861 #ifndef __ASSEMBLY__
79862 /*
79863  * WARNING: The C register and register group struct declarations are provided for
79864  * convenience and illustrative purposes. They should, however, be used with
79865  * caution as the C language standard provides no guarantees about the alignment or
79866  * atomicity of device memory accesses. The recommended practice for writing
79867  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
79868  * alt_write_word() functions.
79869  *
79870  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW.
79871  */
79872 struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s
79873 {
79874  uint32_t addrlo : 32; /* MAC Address97 [31:0] */
79875 };
79876 
79877 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW. */
79878 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s ALT_EMAC_GMAC_MAC_ADDR97_LOW_t;
79879 #endif /* __ASSEMBLY__ */
79880 
79881 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register from the beginning of the component. */
79882 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST 0xa8c
79883 /* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register. */
79884 #define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST))
79885 
79886 /*
79887  * Register : Register 676 (MAC Address98 High Register) - MAC_Address98_High
79888  *
79889  * The MAC Address98 High register holds the upper 16 bits of the 99th 6-byte MAC
79890  * address of the station. Because the MAC address registers are configured to be
79891  * double-synchronized to the (G)MII clock domains, the synchronization is
79892  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
79893  * endian mode) of the MAC Address98 Low Register are written. For proper
79894  * synchronization updates, the consecutive writes to this Address Low Register
79895  * should be performed after at least four clock cycles in the destination clock
79896  * domain.
79897  *
79898  * Note that all MAC Address High registers (except MAC Address0 High) have the
79899  * same format.
79900  *
79901  * Register Layout
79902  *
79903  * Bits | Access | Reset | Description
79904  * :--------|:-------|:-------|:----------------------
79905  * [15:0] | RW | 0xffff | MAC Address98 [47:32]
79906  * [23:16] | ??? | 0x0 | *UNDEFINED*
79907  * [24] | RW | 0x0 | Mask Byte Control
79908  * [25] | RW | 0x0 | Mask Byte Control
79909  * [26] | RW | 0x0 | Mask Byte Control
79910  * [27] | RW | 0x0 | Mask Byte Control
79911  * [28] | RW | 0x0 | Mask Byte Control
79912  * [29] | RW | 0x0 | Mask Byte Control
79913  * [30] | RW | 0x0 | Source Address
79914  * [31] | RW | 0x0 | Address Enable
79915  *
79916  */
79917 /*
79918  * Field : MAC Address98 [47:32] - addrhi
79919  *
79920  * This field contains the upper 16 bits (47:32) of the 99th 6-byte MAC address.
79921  *
79922  * Field Access Macros:
79923  *
79924  */
79925 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
79926 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_LSB 0
79927 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
79928 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_MSB 15
79929 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
79930 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_WIDTH 16
79931 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
79932 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET_MSK 0x0000ffff
79933 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
79934 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_CLR_MSK 0xffff0000
79935 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
79936 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_RESET 0xffff
79937 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI field value from a register. */
79938 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
79939 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value suitable for setting the register. */
79940 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
79941 
79942 /*
79943  * Field : Mask Byte Control - mbc_0
79944  *
79945  * This array of bits are mask control bits for comparison of each of the MAC
79946  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79947  * received DA or SA with the contents of MAC Address98 high and low registers.
79948  * Each bit controls the masking of the bytes. You can filter a group of addresses
79949  * (known as group address filtering) by masking one or more bytes of the address.
79950  *
79951  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
79952  *
79953  * Field Enumeration Values:
79954  *
79955  * Enum | Value | Description
79956  * :----------------------------------------------|:------|:------------------------------------
79957  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
79958  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
79959  *
79960  * Field Access Macros:
79961  *
79962  */
79963 /*
79964  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0
79965  *
79966  * Byte is unmasked (i.e. is compared)
79967  */
79968 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED 0x0
79969 /*
79970  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0
79971  *
79972  * Byte is masked (i.e. not compared)
79973  */
79974 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED 0x1
79975 
79976 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
79977 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_LSB 24
79978 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
79979 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_MSB 24
79980 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
79981 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_WIDTH 1
79982 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */
79983 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET_MSK 0x01000000
79984 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */
79985 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_CLR_MSK 0xfeffffff
79986 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
79987 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_RESET 0x0
79988 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 field value from a register. */
79989 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
79990 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value suitable for setting the register. */
79991 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
79992 
79993 /*
79994  * Field : Mask Byte Control - mbc_1
79995  *
79996  * This array of bits are mask control bits for comparison of each of the MAC
79997  * Address bytes. When masked, the MAC does not compare the corresponding byte of
79998  * received DA or SA with the contents of MAC Address98 high and low registers.
79999  * Each bit controls the masking of the bytes. You can filter a group of addresses
80000  * (known as group address filtering) by masking one or more bytes of the address.
80001  *
80002  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80003  *
80004  * Field Enumeration Values:
80005  *
80006  * Enum | Value | Description
80007  * :----------------------------------------------|:------|:------------------------------------
80008  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80009  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80010  *
80011  * Field Access Macros:
80012  *
80013  */
80014 /*
80015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1
80016  *
80017  * Byte is unmasked (i.e. is compared)
80018  */
80019 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED 0x0
80020 /*
80021  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1
80022  *
80023  * Byte is masked (i.e. not compared)
80024  */
80025 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED 0x1
80026 
80027 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
80028 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_LSB 25
80029 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
80030 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_MSB 25
80031 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
80032 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_WIDTH 1
80033 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */
80034 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET_MSK 0x02000000
80035 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */
80036 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_CLR_MSK 0xfdffffff
80037 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
80038 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_RESET 0x0
80039 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 field value from a register. */
80040 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
80041 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value suitable for setting the register. */
80042 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
80043 
80044 /*
80045  * Field : Mask Byte Control - mbc_2
80046  *
80047  * This array of bits are mask control bits for comparison of each of the MAC
80048  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80049  * received DA or SA with the contents of MAC Address98 high and low registers.
80050  * Each bit controls the masking of the bytes. You can filter a group of addresses
80051  * (known as group address filtering) by masking one or more bytes of the address.
80052  *
80053  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80054  *
80055  * Field Enumeration Values:
80056  *
80057  * Enum | Value | Description
80058  * :----------------------------------------------|:------|:------------------------------------
80059  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80060  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80061  *
80062  * Field Access Macros:
80063  *
80064  */
80065 /*
80066  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2
80067  *
80068  * Byte is unmasked (i.e. is compared)
80069  */
80070 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED 0x0
80071 /*
80072  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2
80073  *
80074  * Byte is masked (i.e. not compared)
80075  */
80076 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED 0x1
80077 
80078 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
80079 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_LSB 26
80080 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
80081 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_MSB 26
80082 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
80083 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_WIDTH 1
80084 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */
80085 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET_MSK 0x04000000
80086 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */
80087 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_CLR_MSK 0xfbffffff
80088 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
80089 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_RESET 0x0
80090 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 field value from a register. */
80091 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
80092 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value suitable for setting the register. */
80093 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
80094 
80095 /*
80096  * Field : Mask Byte Control - mbc_3
80097  *
80098  * This array of bits are mask control bits for comparison of each of the MAC
80099  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80100  * received DA or SA with the contents of MAC Address98 high and low registers.
80101  * Each bit controls the masking of the bytes. You can filter a group of addresses
80102  * (known as group address filtering) by masking one or more bytes of the address.
80103  *
80104  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80105  *
80106  * Field Enumeration Values:
80107  *
80108  * Enum | Value | Description
80109  * :----------------------------------------------|:------|:------------------------------------
80110  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80111  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80112  *
80113  * Field Access Macros:
80114  *
80115  */
80116 /*
80117  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3
80118  *
80119  * Byte is unmasked (i.e. is compared)
80120  */
80121 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED 0x0
80122 /*
80123  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3
80124  *
80125  * Byte is masked (i.e. not compared)
80126  */
80127 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED 0x1
80128 
80129 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
80130 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_LSB 27
80131 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
80132 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_MSB 27
80133 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
80134 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_WIDTH 1
80135 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */
80136 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET_MSK 0x08000000
80137 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */
80138 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_CLR_MSK 0xf7ffffff
80139 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
80140 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_RESET 0x0
80141 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 field value from a register. */
80142 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
80143 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value suitable for setting the register. */
80144 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
80145 
80146 /*
80147  * Field : Mask Byte Control - mbc_4
80148  *
80149  * This array of bits are mask control bits for comparison of each of the MAC
80150  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80151  * received DA or SA with the contents of MAC Address98 high and low registers.
80152  * Each bit controls the masking of the bytes. You can filter a group of addresses
80153  * (known as group address filtering) by masking one or more bytes of the address.
80154  *
80155  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80156  *
80157  * Field Enumeration Values:
80158  *
80159  * Enum | Value | Description
80160  * :----------------------------------------------|:------|:------------------------------------
80161  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80162  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80163  *
80164  * Field Access Macros:
80165  *
80166  */
80167 /*
80168  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4
80169  *
80170  * Byte is unmasked (i.e. is compared)
80171  */
80172 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED 0x0
80173 /*
80174  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4
80175  *
80176  * Byte is masked (i.e. not compared)
80177  */
80178 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED 0x1
80179 
80180 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
80181 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_LSB 28
80182 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
80183 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_MSB 28
80184 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
80185 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_WIDTH 1
80186 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */
80187 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET_MSK 0x10000000
80188 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */
80189 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_CLR_MSK 0xefffffff
80190 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
80191 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_RESET 0x0
80192 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 field value from a register. */
80193 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
80194 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value suitable for setting the register. */
80195 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
80196 
80197 /*
80198  * Field : Mask Byte Control - mbc_5
80199  *
80200  * This array of bits are mask control bits for comparison of each of the MAC
80201  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80202  * received DA or SA with the contents of MAC Address98 high and low registers.
80203  * Each bit controls the masking of the bytes. You can filter a group of addresses
80204  * (known as group address filtering) by masking one or more bytes of the address.
80205  *
80206  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80207  *
80208  * Field Enumeration Values:
80209  *
80210  * Enum | Value | Description
80211  * :----------------------------------------------|:------|:------------------------------------
80212  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80213  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80214  *
80215  * Field Access Macros:
80216  *
80217  */
80218 /*
80219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5
80220  *
80221  * Byte is unmasked (i.e. is compared)
80222  */
80223 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED 0x0
80224 /*
80225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5
80226  *
80227  * Byte is masked (i.e. not compared)
80228  */
80229 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED 0x1
80230 
80231 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
80232 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_LSB 29
80233 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
80234 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_MSB 29
80235 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
80236 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_WIDTH 1
80237 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */
80238 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET_MSK 0x20000000
80239 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */
80240 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_CLR_MSK 0xdfffffff
80241 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
80242 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_RESET 0x0
80243 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 field value from a register. */
80244 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
80245 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value suitable for setting the register. */
80246 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
80247 
80248 /*
80249  * Field : Source Address - sa
80250  *
80251  * When this bit is enabled, the MAC Address98[47:0] is used to compare with the SA
80252  * fields of the received frame. When this bit is disabled, the MAC Address98[47:0]
80253  * is used to compare with the DA fields of the received frame.
80254  *
80255  * Field Enumeration Values:
80256  *
80257  * Enum | Value | Description
80258  * :----------------------------------------|:------|:-----------------------------
80259  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
80260  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END | 0x1 | MAC address compare enabled
80261  *
80262  * Field Access Macros:
80263  *
80264  */
80265 /*
80266  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA
80267  *
80268  * MAC address compare disabled
80269  */
80270 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD 0x0
80271 /*
80272  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA
80273  *
80274  * MAC address compare enabled
80275  */
80276 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END 0x1
80277 
80278 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
80279 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_LSB 30
80280 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
80281 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_MSB 30
80282 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
80283 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_WIDTH 1
80284 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */
80285 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET_MSK 0x40000000
80286 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */
80287 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_CLR_MSK 0xbfffffff
80288 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
80289 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_RESET 0x0
80290 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA field value from a register. */
80291 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
80292 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value suitable for setting the register. */
80293 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
80294 
80295 /*
80296  * Field : Address Enable - ae
80297  *
80298  * When this bit is enabled, the address filter block uses the 99th MAC address for
80299  * perfect filtering. When this bit is disabled, the address filter block ignores
80300  * the address for filtering.
80301  *
80302  * Field Enumeration Values:
80303  *
80304  * Enum | Value | Description
80305  * :----------------------------------------|:------|:--------------------------------------
80306  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
80307  * ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
80308  *
80309  * Field Access Macros:
80310  *
80311  */
80312 /*
80313  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
80314  *
80315  * Second MAC address filtering disabled
80316  */
80317 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD 0x0
80318 /*
80319  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
80320  *
80321  * Second MAC address filtering enabled
80322  */
80323 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END 0x1
80324 
80325 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
80326 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_LSB 31
80327 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
80328 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_MSB 31
80329 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
80330 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_WIDTH 1
80331 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
80332 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET_MSK 0x80000000
80333 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
80334 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_CLR_MSK 0x7fffffff
80335 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
80336 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_RESET 0x0
80337 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE field value from a register. */
80338 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
80339 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value suitable for setting the register. */
80340 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
80341 
80342 #ifndef __ASSEMBLY__
80343 /*
80344  * WARNING: The C register and register group struct declarations are provided for
80345  * convenience and illustrative purposes. They should, however, be used with
80346  * caution as the C language standard provides no guarantees about the alignment or
80347  * atomicity of device memory accesses. The recommended practice for writing
80348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80349  * alt_write_word() functions.
80350  *
80351  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH.
80352  */
80353 struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s
80354 {
80355  uint32_t addrhi : 16; /* MAC Address98 [47:32] */
80356  uint32_t : 8; /* *UNDEFINED* */
80357  uint32_t mbc_0 : 1; /* Mask Byte Control */
80358  uint32_t mbc_1 : 1; /* Mask Byte Control */
80359  uint32_t mbc_2 : 1; /* Mask Byte Control */
80360  uint32_t mbc_3 : 1; /* Mask Byte Control */
80361  uint32_t mbc_4 : 1; /* Mask Byte Control */
80362  uint32_t mbc_5 : 1; /* Mask Byte Control */
80363  uint32_t sa : 1; /* Source Address */
80364  uint32_t ae : 1; /* Address Enable */
80365 };
80366 
80367 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH. */
80368 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t;
80369 #endif /* __ASSEMBLY__ */
80370 
80371 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register from the beginning of the component. */
80372 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST 0xa90
80373 /* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register. */
80374 #define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST))
80375 
80376 /*
80377  * Register : Register 677 (MAC Address98 Low Register) - MAC_Address98_Low
80378  *
80379  * The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC
80380  * address of the station.
80381  *
80382  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
80383  * format.
80384  *
80385  * Register Layout
80386  *
80387  * Bits | Access | Reset | Description
80388  * :-------|:-------|:-----------|:---------------------
80389  * [31:0] | RW | 0xffffffff | MAC Address98 [31:0]
80390  *
80391  */
80392 /*
80393  * Field : MAC Address98 [31:0] - addrlo
80394  *
80395  * This field contains the lower 32 bits of the 99th 6-byte MAC address. The
80396  * content of this field is undefined until loaded by software after the
80397  * initialization process.
80398  *
80399  * Field Access Macros:
80400  *
80401  */
80402 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
80403 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_LSB 0
80404 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
80405 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_MSB 31
80406 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
80407 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_WIDTH 32
80408 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
80409 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET_MSK 0xffffffff
80410 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
80411 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_CLR_MSK 0x00000000
80412 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
80413 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_RESET 0xffffffff
80414 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO field value from a register. */
80415 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
80416 /* Produces a ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value suitable for setting the register. */
80417 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
80418 
80419 #ifndef __ASSEMBLY__
80420 /*
80421  * WARNING: The C register and register group struct declarations are provided for
80422  * convenience and illustrative purposes. They should, however, be used with
80423  * caution as the C language standard provides no guarantees about the alignment or
80424  * atomicity of device memory accesses. The recommended practice for writing
80425  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80426  * alt_write_word() functions.
80427  *
80428  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW.
80429  */
80430 struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s
80431 {
80432  uint32_t addrlo : 32; /* MAC Address98 [31:0] */
80433 };
80434 
80435 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW. */
80436 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s ALT_EMAC_GMAC_MAC_ADDR98_LOW_t;
80437 #endif /* __ASSEMBLY__ */
80438 
80439 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register from the beginning of the component. */
80440 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST 0xa94
80441 /* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register. */
80442 #define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST))
80443 
80444 /*
80445  * Register : Register 678 (MAC Address99 High Register) - MAC_Address99_High
80446  *
80447  * The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC
80448  * address of the station. Because the MAC address registers are configured to be
80449  * double-synchronized to the (G)MII clock domains, the synchronization is
80450  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
80451  * endian mode) of the MAC Address99 Low Register are written. For proper
80452  * synchronization updates, the consecutive writes to this Address Low Register
80453  * should be performed after at least four clock cycles in the destination clock
80454  * domain.
80455  *
80456  * Note that all MAC Address High registers (except MAC Address0 High) have the
80457  * same format.
80458  *
80459  * Register Layout
80460  *
80461  * Bits | Access | Reset | Description
80462  * :--------|:-------|:-------|:----------------------
80463  * [15:0] | RW | 0xffff | MAC Address99 [47:32]
80464  * [23:16] | ??? | 0x0 | *UNDEFINED*
80465  * [24] | RW | 0x0 | Mask Byte Control
80466  * [25] | RW | 0x0 | Mask Byte Control
80467  * [26] | RW | 0x0 | Mask Byte Control
80468  * [27] | RW | 0x0 | Mask Byte Control
80469  * [28] | RW | 0x0 | Mask Byte Control
80470  * [29] | RW | 0x0 | Mask Byte Control
80471  * [30] | RW | 0x0 | Source Address
80472  * [31] | RW | 0x0 | Address Enable
80473  *
80474  */
80475 /*
80476  * Field : MAC Address99 [47:32] - addrhi
80477  *
80478  * This field contains the upper 16 bits (47:32) of the 100th 6-byte MAC address.
80479  *
80480  * Field Access Macros:
80481  *
80482  */
80483 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
80484 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_LSB 0
80485 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
80486 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_MSB 15
80487 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
80488 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_WIDTH 16
80489 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
80490 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET_MSK 0x0000ffff
80491 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
80492 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_CLR_MSK 0xffff0000
80493 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
80494 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_RESET 0xffff
80495 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI field value from a register. */
80496 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
80497 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value suitable for setting the register. */
80498 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
80499 
80500 /*
80501  * Field : Mask Byte Control - mbc_0
80502  *
80503  * This array of bits are mask control bits for comparison of each of the MAC
80504  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80505  * received DA or SA with the contents of MAC Address99 high and low registers.
80506  * Each bit controls the masking of the bytes. You can filter a group of addresses
80507  * (known as group address filtering) by masking one or more bytes of the address.
80508  *
80509  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80510  *
80511  * Field Enumeration Values:
80512  *
80513  * Enum | Value | Description
80514  * :----------------------------------------------|:------|:------------------------------------
80515  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80516  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80517  *
80518  * Field Access Macros:
80519  *
80520  */
80521 /*
80522  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0
80523  *
80524  * Byte is unmasked (i.e. is compared)
80525  */
80526 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED 0x0
80527 /*
80528  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0
80529  *
80530  * Byte is masked (i.e. not compared)
80531  */
80532 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED 0x1
80533 
80534 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
80535 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_LSB 24
80536 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
80537 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_MSB 24
80538 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
80539 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_WIDTH 1
80540 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */
80541 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET_MSK 0x01000000
80542 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */
80543 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_CLR_MSK 0xfeffffff
80544 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
80545 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_RESET 0x0
80546 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 field value from a register. */
80547 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
80548 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value suitable for setting the register. */
80549 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
80550 
80551 /*
80552  * Field : Mask Byte Control - mbc_1
80553  *
80554  * This array of bits are mask control bits for comparison of each of the MAC
80555  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80556  * received DA or SA with the contents of MAC Address99 high and low registers.
80557  * Each bit controls the masking of the bytes. You can filter a group of addresses
80558  * (known as group address filtering) by masking one or more bytes of the address.
80559  *
80560  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80561  *
80562  * Field Enumeration Values:
80563  *
80564  * Enum | Value | Description
80565  * :----------------------------------------------|:------|:------------------------------------
80566  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80567  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80568  *
80569  * Field Access Macros:
80570  *
80571  */
80572 /*
80573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1
80574  *
80575  * Byte is unmasked (i.e. is compared)
80576  */
80577 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED 0x0
80578 /*
80579  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1
80580  *
80581  * Byte is masked (i.e. not compared)
80582  */
80583 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED 0x1
80584 
80585 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
80586 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_LSB 25
80587 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
80588 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_MSB 25
80589 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
80590 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_WIDTH 1
80591 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */
80592 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET_MSK 0x02000000
80593 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */
80594 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_CLR_MSK 0xfdffffff
80595 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
80596 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_RESET 0x0
80597 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 field value from a register. */
80598 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
80599 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value suitable for setting the register. */
80600 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
80601 
80602 /*
80603  * Field : Mask Byte Control - mbc_2
80604  *
80605  * This array of bits are mask control bits for comparison of each of the MAC
80606  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80607  * received DA or SA with the contents of MAC Address99 high and low registers.
80608  * Each bit controls the masking of the bytes. You can filter a group of addresses
80609  * (known as group address filtering) by masking one or more bytes of the address.
80610  *
80611  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80612  *
80613  * Field Enumeration Values:
80614  *
80615  * Enum | Value | Description
80616  * :----------------------------------------------|:------|:------------------------------------
80617  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80618  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80619  *
80620  * Field Access Macros:
80621  *
80622  */
80623 /*
80624  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2
80625  *
80626  * Byte is unmasked (i.e. is compared)
80627  */
80628 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED 0x0
80629 /*
80630  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2
80631  *
80632  * Byte is masked (i.e. not compared)
80633  */
80634 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED 0x1
80635 
80636 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
80637 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_LSB 26
80638 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
80639 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_MSB 26
80640 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
80641 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_WIDTH 1
80642 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */
80643 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET_MSK 0x04000000
80644 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */
80645 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_CLR_MSK 0xfbffffff
80646 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
80647 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_RESET 0x0
80648 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 field value from a register. */
80649 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
80650 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value suitable for setting the register. */
80651 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
80652 
80653 /*
80654  * Field : Mask Byte Control - mbc_3
80655  *
80656  * This array of bits are mask control bits for comparison of each of the MAC
80657  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80658  * received DA or SA with the contents of MAC Address99 high and low registers.
80659  * Each bit controls the masking of the bytes. You can filter a group of addresses
80660  * (known as group address filtering) by masking one or more bytes of the address.
80661  *
80662  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80663  *
80664  * Field Enumeration Values:
80665  *
80666  * Enum | Value | Description
80667  * :----------------------------------------------|:------|:------------------------------------
80668  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80669  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80670  *
80671  * Field Access Macros:
80672  *
80673  */
80674 /*
80675  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3
80676  *
80677  * Byte is unmasked (i.e. is compared)
80678  */
80679 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED 0x0
80680 /*
80681  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3
80682  *
80683  * Byte is masked (i.e. not compared)
80684  */
80685 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED 0x1
80686 
80687 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
80688 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_LSB 27
80689 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
80690 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_MSB 27
80691 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
80692 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_WIDTH 1
80693 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */
80694 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET_MSK 0x08000000
80695 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */
80696 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_CLR_MSK 0xf7ffffff
80697 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
80698 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_RESET 0x0
80699 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 field value from a register. */
80700 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
80701 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value suitable for setting the register. */
80702 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
80703 
80704 /*
80705  * Field : Mask Byte Control - mbc_4
80706  *
80707  * This array of bits are mask control bits for comparison of each of the MAC
80708  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80709  * received DA or SA with the contents of MAC Address99 high and low registers.
80710  * Each bit controls the masking of the bytes. You can filter a group of addresses
80711  * (known as group address filtering) by masking one or more bytes of the address.
80712  *
80713  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80714  *
80715  * Field Enumeration Values:
80716  *
80717  * Enum | Value | Description
80718  * :----------------------------------------------|:------|:------------------------------------
80719  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80720  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80721  *
80722  * Field Access Macros:
80723  *
80724  */
80725 /*
80726  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4
80727  *
80728  * Byte is unmasked (i.e. is compared)
80729  */
80730 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED 0x0
80731 /*
80732  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4
80733  *
80734  * Byte is masked (i.e. not compared)
80735  */
80736 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED 0x1
80737 
80738 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
80739 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_LSB 28
80740 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
80741 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_MSB 28
80742 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
80743 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_WIDTH 1
80744 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */
80745 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET_MSK 0x10000000
80746 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */
80747 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_CLR_MSK 0xefffffff
80748 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
80749 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_RESET 0x0
80750 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 field value from a register. */
80751 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
80752 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value suitable for setting the register. */
80753 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
80754 
80755 /*
80756  * Field : Mask Byte Control - mbc_5
80757  *
80758  * This array of bits are mask control bits for comparison of each of the MAC
80759  * Address bytes. When masked, the MAC does not compare the corresponding byte of
80760  * received DA or SA with the contents of MAC Address99 high and low registers.
80761  * Each bit controls the masking of the bytes. You can filter a group of addresses
80762  * (known as group address filtering) by masking one or more bytes of the address.
80763  *
80764  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
80765  *
80766  * Field Enumeration Values:
80767  *
80768  * Enum | Value | Description
80769  * :----------------------------------------------|:------|:------------------------------------
80770  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
80771  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
80772  *
80773  * Field Access Macros:
80774  *
80775  */
80776 /*
80777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5
80778  *
80779  * Byte is unmasked (i.e. is compared)
80780  */
80781 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED 0x0
80782 /*
80783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5
80784  *
80785  * Byte is masked (i.e. not compared)
80786  */
80787 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED 0x1
80788 
80789 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
80790 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_LSB 29
80791 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
80792 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_MSB 29
80793 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
80794 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_WIDTH 1
80795 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */
80796 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET_MSK 0x20000000
80797 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */
80798 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_CLR_MSK 0xdfffffff
80799 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
80800 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_RESET 0x0
80801 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 field value from a register. */
80802 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
80803 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value suitable for setting the register. */
80804 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
80805 
80806 /*
80807  * Field : Source Address - sa
80808  *
80809  * When this bit is enabled, the MAC Address99[47:0] is used to compare with the SA
80810  * fields of the received frame. When this bit is disabled, the MAC Address99[47:0]
80811  * is used to compare with the DA fields of the received frame.
80812  *
80813  * Field Enumeration Values:
80814  *
80815  * Enum | Value | Description
80816  * :----------------------------------------|:------|:-----------------------------
80817  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
80818  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END | 0x1 | MAC address compare enabled
80819  *
80820  * Field Access Macros:
80821  *
80822  */
80823 /*
80824  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA
80825  *
80826  * MAC address compare disabled
80827  */
80828 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD 0x0
80829 /*
80830  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA
80831  *
80832  * MAC address compare enabled
80833  */
80834 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END 0x1
80835 
80836 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
80837 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_LSB 30
80838 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
80839 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_MSB 30
80840 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
80841 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_WIDTH 1
80842 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */
80843 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET_MSK 0x40000000
80844 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */
80845 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_CLR_MSK 0xbfffffff
80846 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
80847 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_RESET 0x0
80848 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA field value from a register. */
80849 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
80850 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value suitable for setting the register. */
80851 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
80852 
80853 /*
80854  * Field : Address Enable - ae
80855  *
80856  * When this bit is enabled, the address filter block uses the 100th MAC address
80857  * for perfect filtering. When this bit is disabled, the address filter block
80858  * ignores the address for filtering.
80859  *
80860  * Field Enumeration Values:
80861  *
80862  * Enum | Value | Description
80863  * :----------------------------------------|:------|:--------------------------------------
80864  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
80865  * ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
80866  *
80867  * Field Access Macros:
80868  *
80869  */
80870 /*
80871  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
80872  *
80873  * Second MAC address filtering disabled
80874  */
80875 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD 0x0
80876 /*
80877  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
80878  *
80879  * Second MAC address filtering enabled
80880  */
80881 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END 0x1
80882 
80883 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
80884 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_LSB 31
80885 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
80886 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_MSB 31
80887 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
80888 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_WIDTH 1
80889 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
80890 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET_MSK 0x80000000
80891 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
80892 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_CLR_MSK 0x7fffffff
80893 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
80894 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_RESET 0x0
80895 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE field value from a register. */
80896 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
80897 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value suitable for setting the register. */
80898 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
80899 
80900 #ifndef __ASSEMBLY__
80901 /*
80902  * WARNING: The C register and register group struct declarations are provided for
80903  * convenience and illustrative purposes. They should, however, be used with
80904  * caution as the C language standard provides no guarantees about the alignment or
80905  * atomicity of device memory accesses. The recommended practice for writing
80906  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80907  * alt_write_word() functions.
80908  *
80909  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH.
80910  */
80911 struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s
80912 {
80913  uint32_t addrhi : 16; /* MAC Address99 [47:32] */
80914  uint32_t : 8; /* *UNDEFINED* */
80915  uint32_t mbc_0 : 1; /* Mask Byte Control */
80916  uint32_t mbc_1 : 1; /* Mask Byte Control */
80917  uint32_t mbc_2 : 1; /* Mask Byte Control */
80918  uint32_t mbc_3 : 1; /* Mask Byte Control */
80919  uint32_t mbc_4 : 1; /* Mask Byte Control */
80920  uint32_t mbc_5 : 1; /* Mask Byte Control */
80921  uint32_t sa : 1; /* Source Address */
80922  uint32_t ae : 1; /* Address Enable */
80923 };
80924 
80925 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH. */
80926 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t;
80927 #endif /* __ASSEMBLY__ */
80928 
80929 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register from the beginning of the component. */
80930 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST 0xa98
80931 /* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register. */
80932 #define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST))
80933 
80934 /*
80935  * Register : Register 679 (MAC Address99 Low Register) - MAC_Address99_Low
80936  *
80937  * The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC
80938  * address of the station.
80939  *
80940  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
80941  * format.
80942  *
80943  * Register Layout
80944  *
80945  * Bits | Access | Reset | Description
80946  * :-------|:-------|:-----------|:---------------------
80947  * [31:0] | RW | 0xffffffff | MAC Address99 [31:0]
80948  *
80949  */
80950 /*
80951  * Field : MAC Address99 [31:0] - addrlo
80952  *
80953  * This field contains the lower 32 bits of the 100th 6-byte MAC address. The
80954  * content of this field is undefined until loaded by software after the
80955  * initialization process.
80956  *
80957  * Field Access Macros:
80958  *
80959  */
80960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
80961 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_LSB 0
80962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
80963 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_MSB 31
80964 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
80965 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_WIDTH 32
80966 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
80967 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET_MSK 0xffffffff
80968 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
80969 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_CLR_MSK 0x00000000
80970 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
80971 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_RESET 0xffffffff
80972 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO field value from a register. */
80973 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
80974 /* Produces a ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value suitable for setting the register. */
80975 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
80976 
80977 #ifndef __ASSEMBLY__
80978 /*
80979  * WARNING: The C register and register group struct declarations are provided for
80980  * convenience and illustrative purposes. They should, however, be used with
80981  * caution as the C language standard provides no guarantees about the alignment or
80982  * atomicity of device memory accesses. The recommended practice for writing
80983  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
80984  * alt_write_word() functions.
80985  *
80986  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW.
80987  */
80988 struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s
80989 {
80990  uint32_t addrlo : 32; /* MAC Address99 [31:0] */
80991 };
80992 
80993 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW. */
80994 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s ALT_EMAC_GMAC_MAC_ADDR99_LOW_t;
80995 #endif /* __ASSEMBLY__ */
80996 
80997 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register from the beginning of the component. */
80998 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST 0xa9c
80999 /* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register. */
81000 #define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST))
81001 
81002 /*
81003  * Register : Register 680 (MAC Address100 High Register) - MAC_Address100_High
81004  *
81005  * The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC
81006  * address of the station. Because the MAC address registers are configured to be
81007  * double-synchronized to the (G)MII clock domains, the synchronization is
81008  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
81009  * endian mode) of the MAC Address100 Low Register are written. For proper
81010  * synchronization updates, the consecutive writes to this Address Low Register
81011  * should be performed after at least four clock cycles in the destination clock
81012  * domain.
81013  *
81014  * Note that all MAC Address High registers (except MAC Address0 High) have the
81015  * same format.
81016  *
81017  * Register Layout
81018  *
81019  * Bits | Access | Reset | Description
81020  * :--------|:-------|:-------|:-----------------------
81021  * [15:0] | RW | 0xffff | MAC Address100 [47:32]
81022  * [23:16] | ??? | 0x0 | *UNDEFINED*
81023  * [24] | RW | 0x0 | Mask Byte Control
81024  * [25] | RW | 0x0 | Mask Byte Control
81025  * [26] | RW | 0x0 | Mask Byte Control
81026  * [27] | RW | 0x0 | Mask Byte Control
81027  * [28] | RW | 0x0 | Mask Byte Control
81028  * [29] | RW | 0x0 | Mask Byte Control
81029  * [30] | RW | 0x0 | Source Address
81030  * [31] | RW | 0x0 | Address Enable
81031  *
81032  */
81033 /*
81034  * Field : MAC Address100 [47:32] - addrhi
81035  *
81036  * This field contains the upper 16 bits (47:32) of the 101th 6-byte MAC address.
81037  *
81038  * Field Access Macros:
81039  *
81040  */
81041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
81042 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_LSB 0
81043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
81044 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_MSB 15
81045 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
81046 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_WIDTH 16
81047 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
81048 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET_MSK 0x0000ffff
81049 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
81050 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_CLR_MSK 0xffff0000
81051 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
81052 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_RESET 0xffff
81053 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI field value from a register. */
81054 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
81055 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value suitable for setting the register. */
81056 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
81057 
81058 /*
81059  * Field : Mask Byte Control - mbc_0
81060  *
81061  * This array of bits are mask control bits for comparison of each of the MAC
81062  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81063  * received DA or SA with the contents of MAC Address100 high and low registers.
81064  * Each bit controls the masking of the bytes. You can filter a group of addresses
81065  * (known as group address filtering) by masking one or more bytes of the address.
81066  *
81067  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81068  *
81069  * Field Enumeration Values:
81070  *
81071  * Enum | Value | Description
81072  * :-----------------------------------------------|:------|:------------------------------------
81073  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81074  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81075  *
81076  * Field Access Macros:
81077  *
81078  */
81079 /*
81080  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0
81081  *
81082  * Byte is unmasked (i.e. is compared)
81083  */
81084 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED 0x0
81085 /*
81086  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0
81087  *
81088  * Byte is masked (i.e. not compared)
81089  */
81090 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED 0x1
81091 
81092 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
81093 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_LSB 24
81094 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
81095 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_MSB 24
81096 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
81097 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_WIDTH 1
81098 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */
81099 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET_MSK 0x01000000
81100 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */
81101 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_CLR_MSK 0xfeffffff
81102 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
81103 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_RESET 0x0
81104 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 field value from a register. */
81105 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
81106 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value suitable for setting the register. */
81107 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
81108 
81109 /*
81110  * Field : Mask Byte Control - mbc_1
81111  *
81112  * This array of bits are mask control bits for comparison of each of the MAC
81113  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81114  * received DA or SA with the contents of MAC Address100 high and low registers.
81115  * Each bit controls the masking of the bytes. You can filter a group of addresses
81116  * (known as group address filtering) by masking one or more bytes of the address.
81117  *
81118  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81119  *
81120  * Field Enumeration Values:
81121  *
81122  * Enum | Value | Description
81123  * :-----------------------------------------------|:------|:------------------------------------
81124  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81125  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81126  *
81127  * Field Access Macros:
81128  *
81129  */
81130 /*
81131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1
81132  *
81133  * Byte is unmasked (i.e. is compared)
81134  */
81135 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED 0x0
81136 /*
81137  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1
81138  *
81139  * Byte is masked (i.e. not compared)
81140  */
81141 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED 0x1
81142 
81143 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
81144 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_LSB 25
81145 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
81146 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_MSB 25
81147 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
81148 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_WIDTH 1
81149 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */
81150 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET_MSK 0x02000000
81151 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */
81152 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_CLR_MSK 0xfdffffff
81153 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
81154 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_RESET 0x0
81155 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 field value from a register. */
81156 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
81157 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value suitable for setting the register. */
81158 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
81159 
81160 /*
81161  * Field : Mask Byte Control - mbc_2
81162  *
81163  * This array of bits are mask control bits for comparison of each of the MAC
81164  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81165  * received DA or SA with the contents of MAC Address100 high and low registers.
81166  * Each bit controls the masking of the bytes. You can filter a group of addresses
81167  * (known as group address filtering) by masking one or more bytes of the address.
81168  *
81169  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81170  *
81171  * Field Enumeration Values:
81172  *
81173  * Enum | Value | Description
81174  * :-----------------------------------------------|:------|:------------------------------------
81175  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81176  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81177  *
81178  * Field Access Macros:
81179  *
81180  */
81181 /*
81182  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2
81183  *
81184  * Byte is unmasked (i.e. is compared)
81185  */
81186 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED 0x0
81187 /*
81188  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2
81189  *
81190  * Byte is masked (i.e. not compared)
81191  */
81192 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED 0x1
81193 
81194 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
81195 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_LSB 26
81196 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
81197 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_MSB 26
81198 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
81199 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_WIDTH 1
81200 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */
81201 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET_MSK 0x04000000
81202 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */
81203 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_CLR_MSK 0xfbffffff
81204 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
81205 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_RESET 0x0
81206 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 field value from a register. */
81207 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
81208 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value suitable for setting the register. */
81209 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
81210 
81211 /*
81212  * Field : Mask Byte Control - mbc_3
81213  *
81214  * This array of bits are mask control bits for comparison of each of the MAC
81215  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81216  * received DA or SA with the contents of MAC Address100 high and low registers.
81217  * Each bit controls the masking of the bytes. You can filter a group of addresses
81218  * (known as group address filtering) by masking one or more bytes of the address.
81219  *
81220  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81221  *
81222  * Field Enumeration Values:
81223  *
81224  * Enum | Value | Description
81225  * :-----------------------------------------------|:------|:------------------------------------
81226  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81227  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81228  *
81229  * Field Access Macros:
81230  *
81231  */
81232 /*
81233  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3
81234  *
81235  * Byte is unmasked (i.e. is compared)
81236  */
81237 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED 0x0
81238 /*
81239  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3
81240  *
81241  * Byte is masked (i.e. not compared)
81242  */
81243 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED 0x1
81244 
81245 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
81246 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_LSB 27
81247 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
81248 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_MSB 27
81249 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
81250 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_WIDTH 1
81251 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */
81252 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET_MSK 0x08000000
81253 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */
81254 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_CLR_MSK 0xf7ffffff
81255 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
81256 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_RESET 0x0
81257 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 field value from a register. */
81258 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
81259 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value suitable for setting the register. */
81260 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
81261 
81262 /*
81263  * Field : Mask Byte Control - mbc_4
81264  *
81265  * This array of bits are mask control bits for comparison of each of the MAC
81266  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81267  * received DA or SA with the contents of MAC Address100 high and low registers.
81268  * Each bit controls the masking of the bytes. You can filter a group of addresses
81269  * (known as group address filtering) by masking one or more bytes of the address.
81270  *
81271  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81272  *
81273  * Field Enumeration Values:
81274  *
81275  * Enum | Value | Description
81276  * :-----------------------------------------------|:------|:------------------------------------
81277  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81278  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81279  *
81280  * Field Access Macros:
81281  *
81282  */
81283 /*
81284  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4
81285  *
81286  * Byte is unmasked (i.e. is compared)
81287  */
81288 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED 0x0
81289 /*
81290  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4
81291  *
81292  * Byte is masked (i.e. not compared)
81293  */
81294 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED 0x1
81295 
81296 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
81297 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_LSB 28
81298 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
81299 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_MSB 28
81300 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
81301 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_WIDTH 1
81302 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */
81303 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET_MSK 0x10000000
81304 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */
81305 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_CLR_MSK 0xefffffff
81306 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
81307 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_RESET 0x0
81308 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 field value from a register. */
81309 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
81310 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value suitable for setting the register. */
81311 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
81312 
81313 /*
81314  * Field : Mask Byte Control - mbc_5
81315  *
81316  * This array of bits are mask control bits for comparison of each of the MAC
81317  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81318  * received DA or SA with the contents of MAC Address100 high and low registers.
81319  * Each bit controls the masking of the bytes. You can filter a group of addresses
81320  * (known as group address filtering) by masking one or more bytes of the address.
81321  *
81322  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81323  *
81324  * Field Enumeration Values:
81325  *
81326  * Enum | Value | Description
81327  * :-----------------------------------------------|:------|:------------------------------------
81328  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81329  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81330  *
81331  * Field Access Macros:
81332  *
81333  */
81334 /*
81335  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5
81336  *
81337  * Byte is unmasked (i.e. is compared)
81338  */
81339 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED 0x0
81340 /*
81341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5
81342  *
81343  * Byte is masked (i.e. not compared)
81344  */
81345 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED 0x1
81346 
81347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
81348 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_LSB 29
81349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
81350 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_MSB 29
81351 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
81352 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_WIDTH 1
81353 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */
81354 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET_MSK 0x20000000
81355 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */
81356 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_CLR_MSK 0xdfffffff
81357 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
81358 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_RESET 0x0
81359 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 field value from a register. */
81360 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
81361 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value suitable for setting the register. */
81362 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
81363 
81364 /*
81365  * Field : Source Address - sa
81366  *
81367  * When this bit is enabled, the MAC Address100[47:0] is used to compare with the
81368  * SA fields of the received frame. When this bit is disabled, the MAC
81369  * Address100[47:0] is used to compare with the DA fields of the received frame.
81370  *
81371  * Field Enumeration Values:
81372  *
81373  * Enum | Value | Description
81374  * :-----------------------------------------|:------|:-----------------------------
81375  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
81376  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END | 0x1 | MAC address compare enabled
81377  *
81378  * Field Access Macros:
81379  *
81380  */
81381 /*
81382  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA
81383  *
81384  * MAC address compare disabled
81385  */
81386 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD 0x0
81387 /*
81388  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA
81389  *
81390  * MAC address compare enabled
81391  */
81392 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END 0x1
81393 
81394 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
81395 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_LSB 30
81396 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
81397 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_MSB 30
81398 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
81399 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_WIDTH 1
81400 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */
81401 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET_MSK 0x40000000
81402 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */
81403 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_CLR_MSK 0xbfffffff
81404 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
81405 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_RESET 0x0
81406 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA field value from a register. */
81407 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
81408 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value suitable for setting the register. */
81409 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
81410 
81411 /*
81412  * Field : Address Enable - ae
81413  *
81414  * When this bit is enabled, the address filter block uses the 101th MAC address
81415  * for perfect filtering. When this bit is disabled, the address filter block
81416  * ignores the address for filtering.
81417  *
81418  * Field Enumeration Values:
81419  *
81420  * Enum | Value | Description
81421  * :-----------------------------------------|:------|:--------------------------------------
81422  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
81423  * ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
81424  *
81425  * Field Access Macros:
81426  *
81427  */
81428 /*
81429  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
81430  *
81431  * Second MAC address filtering disabled
81432  */
81433 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD 0x0
81434 /*
81435  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
81436  *
81437  * Second MAC address filtering enabled
81438  */
81439 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END 0x1
81440 
81441 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
81442 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_LSB 31
81443 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
81444 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_MSB 31
81445 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
81446 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_WIDTH 1
81447 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
81448 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET_MSK 0x80000000
81449 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
81450 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_CLR_MSK 0x7fffffff
81451 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
81452 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_RESET 0x0
81453 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE field value from a register. */
81454 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
81455 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value suitable for setting the register. */
81456 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
81457 
81458 #ifndef __ASSEMBLY__
81459 /*
81460  * WARNING: The C register and register group struct declarations are provided for
81461  * convenience and illustrative purposes. They should, however, be used with
81462  * caution as the C language standard provides no guarantees about the alignment or
81463  * atomicity of device memory accesses. The recommended practice for writing
81464  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
81465  * alt_write_word() functions.
81466  *
81467  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH.
81468  */
81469 struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s
81470 {
81471  uint32_t addrhi : 16; /* MAC Address100 [47:32] */
81472  uint32_t : 8; /* *UNDEFINED* */
81473  uint32_t mbc_0 : 1; /* Mask Byte Control */
81474  uint32_t mbc_1 : 1; /* Mask Byte Control */
81475  uint32_t mbc_2 : 1; /* Mask Byte Control */
81476  uint32_t mbc_3 : 1; /* Mask Byte Control */
81477  uint32_t mbc_4 : 1; /* Mask Byte Control */
81478  uint32_t mbc_5 : 1; /* Mask Byte Control */
81479  uint32_t sa : 1; /* Source Address */
81480  uint32_t ae : 1; /* Address Enable */
81481 };
81482 
81483 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH. */
81484 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t;
81485 #endif /* __ASSEMBLY__ */
81486 
81487 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register from the beginning of the component. */
81488 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST 0xaa0
81489 /* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register. */
81490 #define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST))
81491 
81492 /*
81493  * Register : Register 681 (MAC Address100 Low Register) - MAC_Address100_Low
81494  *
81495  * The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC
81496  * address of the station.
81497  *
81498  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
81499  * format.
81500  *
81501  * Register Layout
81502  *
81503  * Bits | Access | Reset | Description
81504  * :-------|:-------|:-----------|:----------------------
81505  * [31:0] | RW | 0xffffffff | MAC Address100 [31:0]
81506  *
81507  */
81508 /*
81509  * Field : MAC Address100 [31:0] - addrlo
81510  *
81511  * This field contains the lower 32 bits of the 101th 6-byte MAC address. The
81512  * content of this field is undefined until loaded by software after the
81513  * initialization process.
81514  *
81515  * Field Access Macros:
81516  *
81517  */
81518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
81519 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_LSB 0
81520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
81521 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_MSB 31
81522 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
81523 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_WIDTH 32
81524 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
81525 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET_MSK 0xffffffff
81526 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
81527 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_CLR_MSK 0x00000000
81528 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
81529 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_RESET 0xffffffff
81530 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO field value from a register. */
81531 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
81532 /* Produces a ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value suitable for setting the register. */
81533 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
81534 
81535 #ifndef __ASSEMBLY__
81536 /*
81537  * WARNING: The C register and register group struct declarations are provided for
81538  * convenience and illustrative purposes. They should, however, be used with
81539  * caution as the C language standard provides no guarantees about the alignment or
81540  * atomicity of device memory accesses. The recommended practice for writing
81541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
81542  * alt_write_word() functions.
81543  *
81544  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW.
81545  */
81546 struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s
81547 {
81548  uint32_t addrlo : 32; /* MAC Address100 [31:0] */
81549 };
81550 
81551 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW. */
81552 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s ALT_EMAC_GMAC_MAC_ADDR100_LOW_t;
81553 #endif /* __ASSEMBLY__ */
81554 
81555 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register from the beginning of the component. */
81556 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST 0xaa4
81557 /* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register. */
81558 #define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST))
81559 
81560 /*
81561  * Register : Register 682 (MAC Address101 High Register) - MAC_Address101_High
81562  *
81563  * The MAC Address101 High register holds the upper 16 bits of the 102th 6-byte MAC
81564  * address of the station. Because the MAC address registers are configured to be
81565  * double-synchronized to the (G)MII clock domains, the synchronization is
81566  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
81567  * endian mode) of the MAC Address101 Low Register are written. For proper
81568  * synchronization updates, the consecutive writes to this Address Low Register
81569  * should be performed after at least four clock cycles in the destination clock
81570  * domain.
81571  *
81572  * Note that all MAC Address High registers (except MAC Address0 High) have the
81573  * same format.
81574  *
81575  * Register Layout
81576  *
81577  * Bits | Access | Reset | Description
81578  * :--------|:-------|:-------|:-----------------------
81579  * [15:0] | RW | 0xffff | MAC Address101 [47:32]
81580  * [23:16] | ??? | 0x0 | *UNDEFINED*
81581  * [24] | RW | 0x0 | Mask Byte Control
81582  * [25] | RW | 0x0 | Mask Byte Control
81583  * [26] | RW | 0x0 | Mask Byte Control
81584  * [27] | RW | 0x0 | Mask Byte Control
81585  * [28] | RW | 0x0 | Mask Byte Control
81586  * [29] | RW | 0x0 | Mask Byte Control
81587  * [30] | RW | 0x0 | Source Address
81588  * [31] | RW | 0x0 | Address Enable
81589  *
81590  */
81591 /*
81592  * Field : MAC Address101 [47:32] - addrhi
81593  *
81594  * This field contains the upper 16 bits (47:32) of the 102th 6-byte MAC address.
81595  *
81596  * Field Access Macros:
81597  *
81598  */
81599 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
81600 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_LSB 0
81601 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
81602 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_MSB 15
81603 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
81604 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_WIDTH 16
81605 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
81606 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET_MSK 0x0000ffff
81607 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
81608 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_CLR_MSK 0xffff0000
81609 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
81610 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_RESET 0xffff
81611 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI field value from a register. */
81612 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
81613 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value suitable for setting the register. */
81614 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
81615 
81616 /*
81617  * Field : Mask Byte Control - mbc_0
81618  *
81619  * This array of bits are mask control bits for comparison of each of the MAC
81620  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81621  * received DA or SA with the contents of MAC Address101 high and low registers.
81622  * Each bit controls the masking of the bytes. You can filter a group of addresses
81623  * (known as group address filtering) by masking one or more bytes of the address.
81624  *
81625  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81626  *
81627  * Field Enumeration Values:
81628  *
81629  * Enum | Value | Description
81630  * :-----------------------------------------------|:------|:------------------------------------
81631  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81632  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81633  *
81634  * Field Access Macros:
81635  *
81636  */
81637 /*
81638  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0
81639  *
81640  * Byte is unmasked (i.e. is compared)
81641  */
81642 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED 0x0
81643 /*
81644  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0
81645  *
81646  * Byte is masked (i.e. not compared)
81647  */
81648 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED 0x1
81649 
81650 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
81651 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_LSB 24
81652 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
81653 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_MSB 24
81654 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
81655 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_WIDTH 1
81656 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */
81657 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET_MSK 0x01000000
81658 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */
81659 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_CLR_MSK 0xfeffffff
81660 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
81661 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_RESET 0x0
81662 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 field value from a register. */
81663 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
81664 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value suitable for setting the register. */
81665 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
81666 
81667 /*
81668  * Field : Mask Byte Control - mbc_1
81669  *
81670  * This array of bits are mask control bits for comparison of each of the MAC
81671  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81672  * received DA or SA with the contents of MAC Address101 high and low registers.
81673  * Each bit controls the masking of the bytes. You can filter a group of addresses
81674  * (known as group address filtering) by masking one or more bytes of the address.
81675  *
81676  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81677  *
81678  * Field Enumeration Values:
81679  *
81680  * Enum | Value | Description
81681  * :-----------------------------------------------|:------|:------------------------------------
81682  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81683  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81684  *
81685  * Field Access Macros:
81686  *
81687  */
81688 /*
81689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1
81690  *
81691  * Byte is unmasked (i.e. is compared)
81692  */
81693 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED 0x0
81694 /*
81695  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1
81696  *
81697  * Byte is masked (i.e. not compared)
81698  */
81699 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED 0x1
81700 
81701 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
81702 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_LSB 25
81703 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
81704 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_MSB 25
81705 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
81706 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_WIDTH 1
81707 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */
81708 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET_MSK 0x02000000
81709 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */
81710 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_CLR_MSK 0xfdffffff
81711 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
81712 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_RESET 0x0
81713 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 field value from a register. */
81714 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
81715 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value suitable for setting the register. */
81716 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
81717 
81718 /*
81719  * Field : Mask Byte Control - mbc_2
81720  *
81721  * This array of bits are mask control bits for comparison of each of the MAC
81722  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81723  * received DA or SA with the contents of MAC Address101 high and low registers.
81724  * Each bit controls the masking of the bytes. You can filter a group of addresses
81725  * (known as group address filtering) by masking one or more bytes of the address.
81726  *
81727  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81728  *
81729  * Field Enumeration Values:
81730  *
81731  * Enum | Value | Description
81732  * :-----------------------------------------------|:------|:------------------------------------
81733  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81734  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81735  *
81736  * Field Access Macros:
81737  *
81738  */
81739 /*
81740  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2
81741  *
81742  * Byte is unmasked (i.e. is compared)
81743  */
81744 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED 0x0
81745 /*
81746  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2
81747  *
81748  * Byte is masked (i.e. not compared)
81749  */
81750 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED 0x1
81751 
81752 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
81753 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_LSB 26
81754 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
81755 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_MSB 26
81756 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
81757 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_WIDTH 1
81758 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */
81759 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET_MSK 0x04000000
81760 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */
81761 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_CLR_MSK 0xfbffffff
81762 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
81763 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_RESET 0x0
81764 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 field value from a register. */
81765 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
81766 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value suitable for setting the register. */
81767 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
81768 
81769 /*
81770  * Field : Mask Byte Control - mbc_3
81771  *
81772  * This array of bits are mask control bits for comparison of each of the MAC
81773  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81774  * received DA or SA with the contents of MAC Address101 high and low registers.
81775  * Each bit controls the masking of the bytes. You can filter a group of addresses
81776  * (known as group address filtering) by masking one or more bytes of the address.
81777  *
81778  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81779  *
81780  * Field Enumeration Values:
81781  *
81782  * Enum | Value | Description
81783  * :-----------------------------------------------|:------|:------------------------------------
81784  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81785  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81786  *
81787  * Field Access Macros:
81788  *
81789  */
81790 /*
81791  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3
81792  *
81793  * Byte is unmasked (i.e. is compared)
81794  */
81795 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED 0x0
81796 /*
81797  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3
81798  *
81799  * Byte is masked (i.e. not compared)
81800  */
81801 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED 0x1
81802 
81803 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
81804 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_LSB 27
81805 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
81806 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_MSB 27
81807 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
81808 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_WIDTH 1
81809 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */
81810 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET_MSK 0x08000000
81811 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */
81812 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_CLR_MSK 0xf7ffffff
81813 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
81814 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_RESET 0x0
81815 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 field value from a register. */
81816 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
81817 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value suitable for setting the register. */
81818 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
81819 
81820 /*
81821  * Field : Mask Byte Control - mbc_4
81822  *
81823  * This array of bits are mask control bits for comparison of each of the MAC
81824  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81825  * received DA or SA with the contents of MAC Address101 high and low registers.
81826  * Each bit controls the masking of the bytes. You can filter a group of addresses
81827  * (known as group address filtering) by masking one or more bytes of the address.
81828  *
81829  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81830  *
81831  * Field Enumeration Values:
81832  *
81833  * Enum | Value | Description
81834  * :-----------------------------------------------|:------|:------------------------------------
81835  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81836  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81837  *
81838  * Field Access Macros:
81839  *
81840  */
81841 /*
81842  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4
81843  *
81844  * Byte is unmasked (i.e. is compared)
81845  */
81846 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED 0x0
81847 /*
81848  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4
81849  *
81850  * Byte is masked (i.e. not compared)
81851  */
81852 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED 0x1
81853 
81854 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
81855 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_LSB 28
81856 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
81857 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_MSB 28
81858 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
81859 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_WIDTH 1
81860 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */
81861 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET_MSK 0x10000000
81862 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */
81863 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_CLR_MSK 0xefffffff
81864 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
81865 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_RESET 0x0
81866 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 field value from a register. */
81867 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
81868 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value suitable for setting the register. */
81869 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
81870 
81871 /*
81872  * Field : Mask Byte Control - mbc_5
81873  *
81874  * This array of bits are mask control bits for comparison of each of the MAC
81875  * Address bytes. When masked, the MAC does not compare the corresponding byte of
81876  * received DA or SA with the contents of MAC Address101 high and low registers.
81877  * Each bit controls the masking of the bytes. You can filter a group of addresses
81878  * (known as group address filtering) by masking one or more bytes of the address.
81879  *
81880  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
81881  *
81882  * Field Enumeration Values:
81883  *
81884  * Enum | Value | Description
81885  * :-----------------------------------------------|:------|:------------------------------------
81886  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
81887  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
81888  *
81889  * Field Access Macros:
81890  *
81891  */
81892 /*
81893  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5
81894  *
81895  * Byte is unmasked (i.e. is compared)
81896  */
81897 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED 0x0
81898 /*
81899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5
81900  *
81901  * Byte is masked (i.e. not compared)
81902  */
81903 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED 0x1
81904 
81905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
81906 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_LSB 29
81907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
81908 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_MSB 29
81909 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
81910 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_WIDTH 1
81911 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */
81912 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET_MSK 0x20000000
81913 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */
81914 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_CLR_MSK 0xdfffffff
81915 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
81916 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_RESET 0x0
81917 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 field value from a register. */
81918 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
81919 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value suitable for setting the register. */
81920 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
81921 
81922 /*
81923  * Field : Source Address - sa
81924  *
81925  * When this bit is enabled, the MAC Address101[47:0] is used to compare with the
81926  * SA fields of the received frame. When this bit is disabled, the MAC
81927  * Address101[47:0] is used to compare with the DA fields of the received frame.
81928  *
81929  * Field Enumeration Values:
81930  *
81931  * Enum | Value | Description
81932  * :-----------------------------------------|:------|:-----------------------------
81933  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
81934  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END | 0x1 | MAC address compare enabled
81935  *
81936  * Field Access Macros:
81937  *
81938  */
81939 /*
81940  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA
81941  *
81942  * MAC address compare disabled
81943  */
81944 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD 0x0
81945 /*
81946  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA
81947  *
81948  * MAC address compare enabled
81949  */
81950 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END 0x1
81951 
81952 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
81953 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_LSB 30
81954 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
81955 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_MSB 30
81956 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
81957 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_WIDTH 1
81958 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */
81959 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET_MSK 0x40000000
81960 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */
81961 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_CLR_MSK 0xbfffffff
81962 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
81963 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_RESET 0x0
81964 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA field value from a register. */
81965 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
81966 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value suitable for setting the register. */
81967 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
81968 
81969 /*
81970  * Field : Address Enable - ae
81971  *
81972  * When this bit is enabled, the address filter block uses the 102th MAC address
81973  * for perfect filtering. When this bit is disabled, the address filter block
81974  * ignores the address for filtering.
81975  *
81976  * Field Enumeration Values:
81977  *
81978  * Enum | Value | Description
81979  * :-----------------------------------------|:------|:--------------------------------------
81980  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
81981  * ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
81982  *
81983  * Field Access Macros:
81984  *
81985  */
81986 /*
81987  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
81988  *
81989  * Second MAC address filtering disabled
81990  */
81991 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD 0x0
81992 /*
81993  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
81994  *
81995  * Second MAC address filtering enabled
81996  */
81997 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END 0x1
81998 
81999 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
82000 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_LSB 31
82001 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
82002 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_MSB 31
82003 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
82004 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_WIDTH 1
82005 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
82006 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET_MSK 0x80000000
82007 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
82008 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_CLR_MSK 0x7fffffff
82009 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
82010 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_RESET 0x0
82011 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE field value from a register. */
82012 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
82013 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value suitable for setting the register. */
82014 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
82015 
82016 #ifndef __ASSEMBLY__
82017 /*
82018  * WARNING: The C register and register group struct declarations are provided for
82019  * convenience and illustrative purposes. They should, however, be used with
82020  * caution as the C language standard provides no guarantees about the alignment or
82021  * atomicity of device memory accesses. The recommended practice for writing
82022  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82023  * alt_write_word() functions.
82024  *
82025  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH.
82026  */
82027 struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s
82028 {
82029  uint32_t addrhi : 16; /* MAC Address101 [47:32] */
82030  uint32_t : 8; /* *UNDEFINED* */
82031  uint32_t mbc_0 : 1; /* Mask Byte Control */
82032  uint32_t mbc_1 : 1; /* Mask Byte Control */
82033  uint32_t mbc_2 : 1; /* Mask Byte Control */
82034  uint32_t mbc_3 : 1; /* Mask Byte Control */
82035  uint32_t mbc_4 : 1; /* Mask Byte Control */
82036  uint32_t mbc_5 : 1; /* Mask Byte Control */
82037  uint32_t sa : 1; /* Source Address */
82038  uint32_t ae : 1; /* Address Enable */
82039 };
82040 
82041 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH. */
82042 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t;
82043 #endif /* __ASSEMBLY__ */
82044 
82045 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register from the beginning of the component. */
82046 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST 0xaa8
82047 /* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register. */
82048 #define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST))
82049 
82050 /*
82051  * Register : Register 683 (MAC Address101 Low Register) - MAC_Address101_Low
82052  *
82053  * The MAC Address101 Low register holds the lower 32 bits of the 102th 6-byte MAC
82054  * address of the station.
82055  *
82056  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
82057  * format.
82058  *
82059  * Register Layout
82060  *
82061  * Bits | Access | Reset | Description
82062  * :-------|:-------|:-----------|:----------------------
82063  * [31:0] | RW | 0xffffffff | MAC Address101 [31:0]
82064  *
82065  */
82066 /*
82067  * Field : MAC Address101 [31:0] - addrlo
82068  *
82069  * This field contains the lower 32 bits of the 102th 6-byte MAC address. The
82070  * content of this field is undefined until loaded by software after the
82071  * initialization process.
82072  *
82073  * Field Access Macros:
82074  *
82075  */
82076 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
82077 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_LSB 0
82078 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
82079 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_MSB 31
82080 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
82081 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_WIDTH 32
82082 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
82083 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET_MSK 0xffffffff
82084 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
82085 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_CLR_MSK 0x00000000
82086 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
82087 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_RESET 0xffffffff
82088 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO field value from a register. */
82089 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
82090 /* Produces a ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value suitable for setting the register. */
82091 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
82092 
82093 #ifndef __ASSEMBLY__
82094 /*
82095  * WARNING: The C register and register group struct declarations are provided for
82096  * convenience and illustrative purposes. They should, however, be used with
82097  * caution as the C language standard provides no guarantees about the alignment or
82098  * atomicity of device memory accesses. The recommended practice for writing
82099  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82100  * alt_write_word() functions.
82101  *
82102  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW.
82103  */
82104 struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s
82105 {
82106  uint32_t addrlo : 32; /* MAC Address101 [31:0] */
82107 };
82108 
82109 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW. */
82110 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s ALT_EMAC_GMAC_MAC_ADDR101_LOW_t;
82111 #endif /* __ASSEMBLY__ */
82112 
82113 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register from the beginning of the component. */
82114 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST 0xaac
82115 /* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register. */
82116 #define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST))
82117 
82118 /*
82119  * Register : Register 684 (MAC Address102 High Register) - MAC_Address102_High
82120  *
82121  * The MAC Address102 High register holds the upper 16 bits of the 103th 6-byte MAC
82122  * address of the station. Because the MAC address registers are configured to be
82123  * double-synchronized to the (G)MII clock domains, the synchronization is
82124  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
82125  * endian mode) of the MAC Address102 Low Register are written. For proper
82126  * synchronization updates, the consecutive writes to this Address Low Register
82127  * should be performed after at least four clock cycles in the destination clock
82128  * domain.
82129  *
82130  * Note that all MAC Address High registers (except MAC Address0 High) have the
82131  * same format.
82132  *
82133  * Register Layout
82134  *
82135  * Bits | Access | Reset | Description
82136  * :--------|:-------|:-------|:-----------------------
82137  * [15:0] | RW | 0xffff | MAC Address102 [47:32]
82138  * [23:16] | ??? | 0x0 | *UNDEFINED*
82139  * [24] | RW | 0x0 | Mask Byte Control
82140  * [25] | RW | 0x0 | Mask Byte Control
82141  * [26] | RW | 0x0 | Mask Byte Control
82142  * [27] | RW | 0x0 | Mask Byte Control
82143  * [28] | RW | 0x0 | Mask Byte Control
82144  * [29] | RW | 0x0 | Mask Byte Control
82145  * [30] | RW | 0x0 | Source Address
82146  * [31] | RW | 0x0 | Address Enable
82147  *
82148  */
82149 /*
82150  * Field : MAC Address102 [47:32] - addrhi
82151  *
82152  * This field contains the upper 16 bits (47:32) of the 103th 6-byte MAC address.
82153  *
82154  * Field Access Macros:
82155  *
82156  */
82157 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
82158 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_LSB 0
82159 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
82160 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_MSB 15
82161 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
82162 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_WIDTH 16
82163 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
82164 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET_MSK 0x0000ffff
82165 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
82166 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_CLR_MSK 0xffff0000
82167 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
82168 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_RESET 0xffff
82169 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI field value from a register. */
82170 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
82171 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value suitable for setting the register. */
82172 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
82173 
82174 /*
82175  * Field : Mask Byte Control - mbc_0
82176  *
82177  * This array of bits are mask control bits for comparison of each of the MAC
82178  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82179  * received DA or SA with the contents of MAC Address102 high and low registers.
82180  * Each bit controls the masking of the bytes. You can filter a group of addresses
82181  * (known as group address filtering) by masking one or more bytes of the address.
82182  *
82183  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82184  *
82185  * Field Enumeration Values:
82186  *
82187  * Enum | Value | Description
82188  * :-----------------------------------------------|:------|:------------------------------------
82189  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82190  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82191  *
82192  * Field Access Macros:
82193  *
82194  */
82195 /*
82196  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0
82197  *
82198  * Byte is unmasked (i.e. is compared)
82199  */
82200 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED 0x0
82201 /*
82202  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0
82203  *
82204  * Byte is masked (i.e. not compared)
82205  */
82206 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED 0x1
82207 
82208 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
82209 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_LSB 24
82210 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
82211 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_MSB 24
82212 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
82213 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_WIDTH 1
82214 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */
82215 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET_MSK 0x01000000
82216 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */
82217 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_CLR_MSK 0xfeffffff
82218 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
82219 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_RESET 0x0
82220 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 field value from a register. */
82221 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
82222 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value suitable for setting the register. */
82223 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
82224 
82225 /*
82226  * Field : Mask Byte Control - mbc_1
82227  *
82228  * This array of bits are mask control bits for comparison of each of the MAC
82229  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82230  * received DA or SA with the contents of MAC Address102 high and low registers.
82231  * Each bit controls the masking of the bytes. You can filter a group of addresses
82232  * (known as group address filtering) by masking one or more bytes of the address.
82233  *
82234  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82235  *
82236  * Field Enumeration Values:
82237  *
82238  * Enum | Value | Description
82239  * :-----------------------------------------------|:------|:------------------------------------
82240  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82241  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82242  *
82243  * Field Access Macros:
82244  *
82245  */
82246 /*
82247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1
82248  *
82249  * Byte is unmasked (i.e. is compared)
82250  */
82251 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED 0x0
82252 /*
82253  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1
82254  *
82255  * Byte is masked (i.e. not compared)
82256  */
82257 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED 0x1
82258 
82259 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
82260 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_LSB 25
82261 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
82262 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_MSB 25
82263 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
82264 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_WIDTH 1
82265 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */
82266 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET_MSK 0x02000000
82267 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */
82268 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_CLR_MSK 0xfdffffff
82269 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
82270 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_RESET 0x0
82271 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 field value from a register. */
82272 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
82273 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value suitable for setting the register. */
82274 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
82275 
82276 /*
82277  * Field : Mask Byte Control - mbc_2
82278  *
82279  * This array of bits are mask control bits for comparison of each of the MAC
82280  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82281  * received DA or SA with the contents of MAC Address102 high and low registers.
82282  * Each bit controls the masking of the bytes. You can filter a group of addresses
82283  * (known as group address filtering) by masking one or more bytes of the address.
82284  *
82285  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82286  *
82287  * Field Enumeration Values:
82288  *
82289  * Enum | Value | Description
82290  * :-----------------------------------------------|:------|:------------------------------------
82291  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82292  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82293  *
82294  * Field Access Macros:
82295  *
82296  */
82297 /*
82298  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2
82299  *
82300  * Byte is unmasked (i.e. is compared)
82301  */
82302 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED 0x0
82303 /*
82304  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2
82305  *
82306  * Byte is masked (i.e. not compared)
82307  */
82308 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED 0x1
82309 
82310 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
82311 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_LSB 26
82312 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
82313 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_MSB 26
82314 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
82315 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_WIDTH 1
82316 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */
82317 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET_MSK 0x04000000
82318 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */
82319 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_CLR_MSK 0xfbffffff
82320 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
82321 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_RESET 0x0
82322 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 field value from a register. */
82323 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
82324 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value suitable for setting the register. */
82325 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
82326 
82327 /*
82328  * Field : Mask Byte Control - mbc_3
82329  *
82330  * This array of bits are mask control bits for comparison of each of the MAC
82331  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82332  * received DA or SA with the contents of MAC Address102 high and low registers.
82333  * Each bit controls the masking of the bytes. You can filter a group of addresses
82334  * (known as group address filtering) by masking one or more bytes of the address.
82335  *
82336  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82337  *
82338  * Field Enumeration Values:
82339  *
82340  * Enum | Value | Description
82341  * :-----------------------------------------------|:------|:------------------------------------
82342  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82343  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82344  *
82345  * Field Access Macros:
82346  *
82347  */
82348 /*
82349  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3
82350  *
82351  * Byte is unmasked (i.e. is compared)
82352  */
82353 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED 0x0
82354 /*
82355  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3
82356  *
82357  * Byte is masked (i.e. not compared)
82358  */
82359 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED 0x1
82360 
82361 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
82362 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_LSB 27
82363 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
82364 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_MSB 27
82365 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
82366 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_WIDTH 1
82367 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */
82368 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET_MSK 0x08000000
82369 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */
82370 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_CLR_MSK 0xf7ffffff
82371 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
82372 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_RESET 0x0
82373 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 field value from a register. */
82374 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
82375 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value suitable for setting the register. */
82376 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
82377 
82378 /*
82379  * Field : Mask Byte Control - mbc_4
82380  *
82381  * This array of bits are mask control bits for comparison of each of the MAC
82382  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82383  * received DA or SA with the contents of MAC Address102 high and low registers.
82384  * Each bit controls the masking of the bytes. You can filter a group of addresses
82385  * (known as group address filtering) by masking one or more bytes of the address.
82386  *
82387  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82388  *
82389  * Field Enumeration Values:
82390  *
82391  * Enum | Value | Description
82392  * :-----------------------------------------------|:------|:------------------------------------
82393  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82394  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82395  *
82396  * Field Access Macros:
82397  *
82398  */
82399 /*
82400  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4
82401  *
82402  * Byte is unmasked (i.e. is compared)
82403  */
82404 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED 0x0
82405 /*
82406  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4
82407  *
82408  * Byte is masked (i.e. not compared)
82409  */
82410 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED 0x1
82411 
82412 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
82413 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_LSB 28
82414 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
82415 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_MSB 28
82416 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
82417 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_WIDTH 1
82418 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */
82419 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET_MSK 0x10000000
82420 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */
82421 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_CLR_MSK 0xefffffff
82422 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
82423 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_RESET 0x0
82424 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 field value from a register. */
82425 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
82426 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value suitable for setting the register. */
82427 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
82428 
82429 /*
82430  * Field : Mask Byte Control - mbc_5
82431  *
82432  * This array of bits are mask control bits for comparison of each of the MAC
82433  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82434  * received DA or SA with the contents of MAC Address102 high and low registers.
82435  * Each bit controls the masking of the bytes. You can filter a group of addresses
82436  * (known as group address filtering) by masking one or more bytes of the address.
82437  *
82438  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82439  *
82440  * Field Enumeration Values:
82441  *
82442  * Enum | Value | Description
82443  * :-----------------------------------------------|:------|:------------------------------------
82444  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82445  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82446  *
82447  * Field Access Macros:
82448  *
82449  */
82450 /*
82451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5
82452  *
82453  * Byte is unmasked (i.e. is compared)
82454  */
82455 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED 0x0
82456 /*
82457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5
82458  *
82459  * Byte is masked (i.e. not compared)
82460  */
82461 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED 0x1
82462 
82463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
82464 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_LSB 29
82465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
82466 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_MSB 29
82467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
82468 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_WIDTH 1
82469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */
82470 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET_MSK 0x20000000
82471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */
82472 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_CLR_MSK 0xdfffffff
82473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
82474 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_RESET 0x0
82475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 field value from a register. */
82476 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
82477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value suitable for setting the register. */
82478 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
82479 
82480 /*
82481  * Field : Source Address - sa
82482  *
82483  * When this bit is enabled, the MAC Address102[47:0] is used to compare with the
82484  * SA fields of the received frame. When this bit is disabled, the MAC
82485  * Address102[47:0] is used to compare with the DA fields of the received frame.
82486  *
82487  * Field Enumeration Values:
82488  *
82489  * Enum | Value | Description
82490  * :-----------------------------------------|:------|:-----------------------------
82491  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
82492  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END | 0x1 | MAC address compare enabled
82493  *
82494  * Field Access Macros:
82495  *
82496  */
82497 /*
82498  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA
82499  *
82500  * MAC address compare disabled
82501  */
82502 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD 0x0
82503 /*
82504  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA
82505  *
82506  * MAC address compare enabled
82507  */
82508 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END 0x1
82509 
82510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
82511 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_LSB 30
82512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
82513 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_MSB 30
82514 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
82515 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_WIDTH 1
82516 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */
82517 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET_MSK 0x40000000
82518 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */
82519 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_CLR_MSK 0xbfffffff
82520 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
82521 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_RESET 0x0
82522 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA field value from a register. */
82523 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
82524 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value suitable for setting the register. */
82525 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
82526 
82527 /*
82528  * Field : Address Enable - ae
82529  *
82530  * When this bit is enabled, the address filter block uses the 103th MAC address
82531  * for perfect filtering. When this bit is disabled, the address filter block
82532  * ignores the address for filtering.
82533  *
82534  * Field Enumeration Values:
82535  *
82536  * Enum | Value | Description
82537  * :-----------------------------------------|:------|:--------------------------------------
82538  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
82539  * ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
82540  *
82541  * Field Access Macros:
82542  *
82543  */
82544 /*
82545  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
82546  *
82547  * Second MAC address filtering disabled
82548  */
82549 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD 0x0
82550 /*
82551  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
82552  *
82553  * Second MAC address filtering enabled
82554  */
82555 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END 0x1
82556 
82557 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
82558 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_LSB 31
82559 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
82560 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_MSB 31
82561 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
82562 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_WIDTH 1
82563 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
82564 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET_MSK 0x80000000
82565 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
82566 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_CLR_MSK 0x7fffffff
82567 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
82568 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_RESET 0x0
82569 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE field value from a register. */
82570 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
82571 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value suitable for setting the register. */
82572 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
82573 
82574 #ifndef __ASSEMBLY__
82575 /*
82576  * WARNING: The C register and register group struct declarations are provided for
82577  * convenience and illustrative purposes. They should, however, be used with
82578  * caution as the C language standard provides no guarantees about the alignment or
82579  * atomicity of device memory accesses. The recommended practice for writing
82580  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82581  * alt_write_word() functions.
82582  *
82583  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH.
82584  */
82585 struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s
82586 {
82587  uint32_t addrhi : 16; /* MAC Address102 [47:32] */
82588  uint32_t : 8; /* *UNDEFINED* */
82589  uint32_t mbc_0 : 1; /* Mask Byte Control */
82590  uint32_t mbc_1 : 1; /* Mask Byte Control */
82591  uint32_t mbc_2 : 1; /* Mask Byte Control */
82592  uint32_t mbc_3 : 1; /* Mask Byte Control */
82593  uint32_t mbc_4 : 1; /* Mask Byte Control */
82594  uint32_t mbc_5 : 1; /* Mask Byte Control */
82595  uint32_t sa : 1; /* Source Address */
82596  uint32_t ae : 1; /* Address Enable */
82597 };
82598 
82599 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH. */
82600 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t;
82601 #endif /* __ASSEMBLY__ */
82602 
82603 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register from the beginning of the component. */
82604 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST 0xab0
82605 /* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register. */
82606 #define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST))
82607 
82608 /*
82609  * Register : Register 685 (MAC Address102 Low Register) - MAC_Address102_Low
82610  *
82611  * The MAC Address102 Low register holds the lower 32 bits of the 103th 6-byte MAC
82612  * address of the station.
82613  *
82614  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
82615  * format.
82616  *
82617  * Register Layout
82618  *
82619  * Bits | Access | Reset | Description
82620  * :-------|:-------|:-----------|:----------------------
82621  * [31:0] | RW | 0xffffffff | MAC Address102 [31:0]
82622  *
82623  */
82624 /*
82625  * Field : MAC Address102 [31:0] - addrlo
82626  *
82627  * This field contains the lower 32 bits of the 103th 6-byte MAC address. The
82628  * content of this field is undefined until loaded by software after the
82629  * initialization process.
82630  *
82631  * Field Access Macros:
82632  *
82633  */
82634 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
82635 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_LSB 0
82636 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
82637 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_MSB 31
82638 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
82639 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_WIDTH 32
82640 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
82641 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET_MSK 0xffffffff
82642 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
82643 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_CLR_MSK 0x00000000
82644 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
82645 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_RESET 0xffffffff
82646 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO field value from a register. */
82647 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
82648 /* Produces a ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value suitable for setting the register. */
82649 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
82650 
82651 #ifndef __ASSEMBLY__
82652 /*
82653  * WARNING: The C register and register group struct declarations are provided for
82654  * convenience and illustrative purposes. They should, however, be used with
82655  * caution as the C language standard provides no guarantees about the alignment or
82656  * atomicity of device memory accesses. The recommended practice for writing
82657  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
82658  * alt_write_word() functions.
82659  *
82660  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW.
82661  */
82662 struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s
82663 {
82664  uint32_t addrlo : 32; /* MAC Address102 [31:0] */
82665 };
82666 
82667 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW. */
82668 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s ALT_EMAC_GMAC_MAC_ADDR102_LOW_t;
82669 #endif /* __ASSEMBLY__ */
82670 
82671 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register from the beginning of the component. */
82672 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST 0xab4
82673 /* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register. */
82674 #define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST))
82675 
82676 /*
82677  * Register : Register 686 (MAC Address103 High Register) - MAC_Address103_High
82678  *
82679  * The MAC Address103 High register holds the upper 16 bits of the 104th 6-byte MAC
82680  * address of the station. Because the MAC address registers are configured to be
82681  * double-synchronized to the (G)MII clock domains, the synchronization is
82682  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
82683  * endian mode) of the MAC Address103 Low Register are written. For proper
82684  * synchronization updates, the consecutive writes to this Address Low Register
82685  * should be performed after at least four clock cycles in the destination clock
82686  * domain.
82687  *
82688  * Note that all MAC Address High registers (except MAC Address0 High) have the
82689  * same format.
82690  *
82691  * Register Layout
82692  *
82693  * Bits | Access | Reset | Description
82694  * :--------|:-------|:-------|:-----------------------
82695  * [15:0] | RW | 0xffff | MAC Address103 [47:32]
82696  * [23:16] | ??? | 0x0 | *UNDEFINED*
82697  * [24] | RW | 0x0 | Mask Byte Control
82698  * [25] | RW | 0x0 | Mask Byte Control
82699  * [26] | RW | 0x0 | Mask Byte Control
82700  * [27] | RW | 0x0 | Mask Byte Control
82701  * [28] | RW | 0x0 | Mask Byte Control
82702  * [29] | RW | 0x0 | Mask Byte Control
82703  * [30] | RW | 0x0 | Source Address
82704  * [31] | RW | 0x0 | Address Enable
82705  *
82706  */
82707 /*
82708  * Field : MAC Address103 [47:32] - addrhi
82709  *
82710  * This field contains the upper 16 bits (47:32) of the 104th 6-byte MAC address.
82711  *
82712  * Field Access Macros:
82713  *
82714  */
82715 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
82716 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_LSB 0
82717 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
82718 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_MSB 15
82719 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
82720 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_WIDTH 16
82721 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
82722 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET_MSK 0x0000ffff
82723 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
82724 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_CLR_MSK 0xffff0000
82725 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
82726 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_RESET 0xffff
82727 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI field value from a register. */
82728 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
82729 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value suitable for setting the register. */
82730 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
82731 
82732 /*
82733  * Field : Mask Byte Control - mbc_0
82734  *
82735  * This array of bits are mask control bits for comparison of each of the MAC
82736  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82737  * received DA or SA with the contents of MAC Address103 high and low registers.
82738  * Each bit controls the masking of the bytes. You can filter a group of addresses
82739  * (known as group address filtering) by masking one or more bytes of the address.
82740  *
82741  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82742  *
82743  * Field Enumeration Values:
82744  *
82745  * Enum | Value | Description
82746  * :-----------------------------------------------|:------|:------------------------------------
82747  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82748  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82749  *
82750  * Field Access Macros:
82751  *
82752  */
82753 /*
82754  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0
82755  *
82756  * Byte is unmasked (i.e. is compared)
82757  */
82758 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED 0x0
82759 /*
82760  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0
82761  *
82762  * Byte is masked (i.e. not compared)
82763  */
82764 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED 0x1
82765 
82766 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
82767 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_LSB 24
82768 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
82769 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_MSB 24
82770 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
82771 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_WIDTH 1
82772 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */
82773 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET_MSK 0x01000000
82774 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */
82775 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_CLR_MSK 0xfeffffff
82776 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
82777 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_RESET 0x0
82778 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 field value from a register. */
82779 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
82780 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value suitable for setting the register. */
82781 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
82782 
82783 /*
82784  * Field : Mask Byte Control - mbc_1
82785  *
82786  * This array of bits are mask control bits for comparison of each of the MAC
82787  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82788  * received DA or SA with the contents of MAC Address103 high and low registers.
82789  * Each bit controls the masking of the bytes. You can filter a group of addresses
82790  * (known as group address filtering) by masking one or more bytes of the address.
82791  *
82792  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82793  *
82794  * Field Enumeration Values:
82795  *
82796  * Enum | Value | Description
82797  * :-----------------------------------------------|:------|:------------------------------------
82798  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82799  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82800  *
82801  * Field Access Macros:
82802  *
82803  */
82804 /*
82805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1
82806  *
82807  * Byte is unmasked (i.e. is compared)
82808  */
82809 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED 0x0
82810 /*
82811  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1
82812  *
82813  * Byte is masked (i.e. not compared)
82814  */
82815 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED 0x1
82816 
82817 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
82818 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_LSB 25
82819 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
82820 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_MSB 25
82821 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
82822 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_WIDTH 1
82823 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */
82824 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET_MSK 0x02000000
82825 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */
82826 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_CLR_MSK 0xfdffffff
82827 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
82828 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_RESET 0x0
82829 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 field value from a register. */
82830 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
82831 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value suitable for setting the register. */
82832 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
82833 
82834 /*
82835  * Field : Mask Byte Control - mbc_2
82836  *
82837  * This array of bits are mask control bits for comparison of each of the MAC
82838  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82839  * received DA or SA with the contents of MAC Address103 high and low registers.
82840  * Each bit controls the masking of the bytes. You can filter a group of addresses
82841  * (known as group address filtering) by masking one or more bytes of the address.
82842  *
82843  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82844  *
82845  * Field Enumeration Values:
82846  *
82847  * Enum | Value | Description
82848  * :-----------------------------------------------|:------|:------------------------------------
82849  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82850  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82851  *
82852  * Field Access Macros:
82853  *
82854  */
82855 /*
82856  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2
82857  *
82858  * Byte is unmasked (i.e. is compared)
82859  */
82860 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED 0x0
82861 /*
82862  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2
82863  *
82864  * Byte is masked (i.e. not compared)
82865  */
82866 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED 0x1
82867 
82868 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
82869 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_LSB 26
82870 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
82871 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_MSB 26
82872 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
82873 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_WIDTH 1
82874 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */
82875 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET_MSK 0x04000000
82876 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */
82877 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_CLR_MSK 0xfbffffff
82878 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
82879 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_RESET 0x0
82880 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 field value from a register. */
82881 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
82882 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value suitable for setting the register. */
82883 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
82884 
82885 /*
82886  * Field : Mask Byte Control - mbc_3
82887  *
82888  * This array of bits are mask control bits for comparison of each of the MAC
82889  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82890  * received DA or SA with the contents of MAC Address103 high and low registers.
82891  * Each bit controls the masking of the bytes. You can filter a group of addresses
82892  * (known as group address filtering) by masking one or more bytes of the address.
82893  *
82894  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82895  *
82896  * Field Enumeration Values:
82897  *
82898  * Enum | Value | Description
82899  * :-----------------------------------------------|:------|:------------------------------------
82900  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82901  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82902  *
82903  * Field Access Macros:
82904  *
82905  */
82906 /*
82907  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3
82908  *
82909  * Byte is unmasked (i.e. is compared)
82910  */
82911 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED 0x0
82912 /*
82913  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3
82914  *
82915  * Byte is masked (i.e. not compared)
82916  */
82917 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED 0x1
82918 
82919 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
82920 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_LSB 27
82921 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
82922 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_MSB 27
82923 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
82924 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_WIDTH 1
82925 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */
82926 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET_MSK 0x08000000
82927 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */
82928 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_CLR_MSK 0xf7ffffff
82929 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
82930 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_RESET 0x0
82931 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 field value from a register. */
82932 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
82933 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value suitable for setting the register. */
82934 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
82935 
82936 /*
82937  * Field : Mask Byte Control - mbc_4
82938  *
82939  * This array of bits are mask control bits for comparison of each of the MAC
82940  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82941  * received DA or SA with the contents of MAC Address103 high and low registers.
82942  * Each bit controls the masking of the bytes. You can filter a group of addresses
82943  * (known as group address filtering) by masking one or more bytes of the address.
82944  *
82945  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82946  *
82947  * Field Enumeration Values:
82948  *
82949  * Enum | Value | Description
82950  * :-----------------------------------------------|:------|:------------------------------------
82951  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
82952  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
82953  *
82954  * Field Access Macros:
82955  *
82956  */
82957 /*
82958  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4
82959  *
82960  * Byte is unmasked (i.e. is compared)
82961  */
82962 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED 0x0
82963 /*
82964  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4
82965  *
82966  * Byte is masked (i.e. not compared)
82967  */
82968 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED 0x1
82969 
82970 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
82971 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_LSB 28
82972 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
82973 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_MSB 28
82974 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
82975 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_WIDTH 1
82976 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */
82977 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET_MSK 0x10000000
82978 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */
82979 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_CLR_MSK 0xefffffff
82980 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
82981 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_RESET 0x0
82982 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 field value from a register. */
82983 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
82984 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value suitable for setting the register. */
82985 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
82986 
82987 /*
82988  * Field : Mask Byte Control - mbc_5
82989  *
82990  * This array of bits are mask control bits for comparison of each of the MAC
82991  * Address bytes. When masked, the MAC does not compare the corresponding byte of
82992  * received DA or SA with the contents of MAC Address103 high and low registers.
82993  * Each bit controls the masking of the bytes. You can filter a group of addresses
82994  * (known as group address filtering) by masking one or more bytes of the address.
82995  *
82996  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
82997  *
82998  * Field Enumeration Values:
82999  *
83000  * Enum | Value | Description
83001  * :-----------------------------------------------|:------|:------------------------------------
83002  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83003  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83004  *
83005  * Field Access Macros:
83006  *
83007  */
83008 /*
83009  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5
83010  *
83011  * Byte is unmasked (i.e. is compared)
83012  */
83013 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED 0x0
83014 /*
83015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5
83016  *
83017  * Byte is masked (i.e. not compared)
83018  */
83019 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED 0x1
83020 
83021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
83022 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_LSB 29
83023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
83024 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_MSB 29
83025 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
83026 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_WIDTH 1
83027 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */
83028 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET_MSK 0x20000000
83029 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */
83030 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_CLR_MSK 0xdfffffff
83031 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
83032 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_RESET 0x0
83033 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 field value from a register. */
83034 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
83035 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value suitable for setting the register. */
83036 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
83037 
83038 /*
83039  * Field : Source Address - sa
83040  *
83041  * When this bit is enabled, the MAC Address103[47:0] is used to compare with the
83042  * SA fields of the received frame. When this bit is disabled, the MAC
83043  * Address103[47:0] is used to compare with the DA fields of the received frame.
83044  *
83045  * Field Enumeration Values:
83046  *
83047  * Enum | Value | Description
83048  * :-----------------------------------------|:------|:-----------------------------
83049  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
83050  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END | 0x1 | MAC address compare enabled
83051  *
83052  * Field Access Macros:
83053  *
83054  */
83055 /*
83056  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA
83057  *
83058  * MAC address compare disabled
83059  */
83060 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD 0x0
83061 /*
83062  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA
83063  *
83064  * MAC address compare enabled
83065  */
83066 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END 0x1
83067 
83068 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
83069 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_LSB 30
83070 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
83071 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_MSB 30
83072 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
83073 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_WIDTH 1
83074 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */
83075 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET_MSK 0x40000000
83076 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */
83077 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_CLR_MSK 0xbfffffff
83078 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
83079 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_RESET 0x0
83080 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA field value from a register. */
83081 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
83082 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value suitable for setting the register. */
83083 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
83084 
83085 /*
83086  * Field : Address Enable - ae
83087  *
83088  * When this bit is enabled, the address filter block uses the 104th MAC address
83089  * for perfect filtering. When this bit is disabled, the address filter block
83090  * ignores the address for filtering.
83091  *
83092  * Field Enumeration Values:
83093  *
83094  * Enum | Value | Description
83095  * :-----------------------------------------|:------|:--------------------------------------
83096  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
83097  * ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
83098  *
83099  * Field Access Macros:
83100  *
83101  */
83102 /*
83103  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
83104  *
83105  * Second MAC address filtering disabled
83106  */
83107 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD 0x0
83108 /*
83109  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
83110  *
83111  * Second MAC address filtering enabled
83112  */
83113 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END 0x1
83114 
83115 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
83116 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_LSB 31
83117 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
83118 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_MSB 31
83119 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
83120 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_WIDTH 1
83121 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
83122 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET_MSK 0x80000000
83123 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
83124 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_CLR_MSK 0x7fffffff
83125 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
83126 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_RESET 0x0
83127 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE field value from a register. */
83128 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
83129 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value suitable for setting the register. */
83130 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
83131 
83132 #ifndef __ASSEMBLY__
83133 /*
83134  * WARNING: The C register and register group struct declarations are provided for
83135  * convenience and illustrative purposes. They should, however, be used with
83136  * caution as the C language standard provides no guarantees about the alignment or
83137  * atomicity of device memory accesses. The recommended practice for writing
83138  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
83139  * alt_write_word() functions.
83140  *
83141  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH.
83142  */
83143 struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s
83144 {
83145  uint32_t addrhi : 16; /* MAC Address103 [47:32] */
83146  uint32_t : 8; /* *UNDEFINED* */
83147  uint32_t mbc_0 : 1; /* Mask Byte Control */
83148  uint32_t mbc_1 : 1; /* Mask Byte Control */
83149  uint32_t mbc_2 : 1; /* Mask Byte Control */
83150  uint32_t mbc_3 : 1; /* Mask Byte Control */
83151  uint32_t mbc_4 : 1; /* Mask Byte Control */
83152  uint32_t mbc_5 : 1; /* Mask Byte Control */
83153  uint32_t sa : 1; /* Source Address */
83154  uint32_t ae : 1; /* Address Enable */
83155 };
83156 
83157 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH. */
83158 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t;
83159 #endif /* __ASSEMBLY__ */
83160 
83161 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register from the beginning of the component. */
83162 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST 0xab8
83163 /* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register. */
83164 #define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST))
83165 
83166 /*
83167  * Register : Register 687 (MAC Address103 Low Register) - MAC_Address103_Low
83168  *
83169  * The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC
83170  * address of the station.
83171  *
83172  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
83173  * format.
83174  *
83175  * Register Layout
83176  *
83177  * Bits | Access | Reset | Description
83178  * :-------|:-------|:-----------|:----------------------
83179  * [31:0] | RW | 0xffffffff | MAC Address103 [31:0]
83180  *
83181  */
83182 /*
83183  * Field : MAC Address103 [31:0] - addrlo
83184  *
83185  * This field contains the lower 32 bits of the 104th 6-byte MAC address. The
83186  * content of this field is undefined until loaded by software after the
83187  * initialization process.
83188  *
83189  * Field Access Macros:
83190  *
83191  */
83192 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
83193 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_LSB 0
83194 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
83195 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_MSB 31
83196 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
83197 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_WIDTH 32
83198 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
83199 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET_MSK 0xffffffff
83200 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
83201 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_CLR_MSK 0x00000000
83202 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
83203 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_RESET 0xffffffff
83204 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO field value from a register. */
83205 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
83206 /* Produces a ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value suitable for setting the register. */
83207 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
83208 
83209 #ifndef __ASSEMBLY__
83210 /*
83211  * WARNING: The C register and register group struct declarations are provided for
83212  * convenience and illustrative purposes. They should, however, be used with
83213  * caution as the C language standard provides no guarantees about the alignment or
83214  * atomicity of device memory accesses. The recommended practice for writing
83215  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
83216  * alt_write_word() functions.
83217  *
83218  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW.
83219  */
83220 struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s
83221 {
83222  uint32_t addrlo : 32; /* MAC Address103 [31:0] */
83223 };
83224 
83225 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW. */
83226 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s ALT_EMAC_GMAC_MAC_ADDR103_LOW_t;
83227 #endif /* __ASSEMBLY__ */
83228 
83229 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register from the beginning of the component. */
83230 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST 0xabc
83231 /* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register. */
83232 #define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST))
83233 
83234 /*
83235  * Register : Register 688 (MAC Address104 High Register) - MAC_Address104_High
83236  *
83237  * The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC
83238  * address of the station. Because the MAC address registers are configured to be
83239  * double-synchronized to the (G)MII clock domains, the synchronization is
83240  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
83241  * endian mode) of the MAC Address104 Low Register are written. For proper
83242  * synchronization updates, the consecutive writes to this Address Low Register
83243  * should be performed after at least four clock cycles in the destination clock
83244  * domain.
83245  *
83246  * Note that all MAC Address High registers (except MAC Address0 High) have the
83247  * same format.
83248  *
83249  * Register Layout
83250  *
83251  * Bits | Access | Reset | Description
83252  * :--------|:-------|:-------|:-----------------------
83253  * [15:0] | RW | 0xffff | MAC Address104 [47:32]
83254  * [23:16] | ??? | 0x0 | *UNDEFINED*
83255  * [24] | RW | 0x0 | Mask Byte Control
83256  * [25] | RW | 0x0 | Mask Byte Control
83257  * [26] | RW | 0x0 | Mask Byte Control
83258  * [27] | RW | 0x0 | Mask Byte Control
83259  * [28] | RW | 0x0 | Mask Byte Control
83260  * [29] | RW | 0x0 | Mask Byte Control
83261  * [30] | RW | 0x0 | Source Address
83262  * [31] | RW | 0x0 | Address Enable
83263  *
83264  */
83265 /*
83266  * Field : MAC Address104 [47:32] - addrhi
83267  *
83268  * This field contains the upper 16 bits (47:32) of the 105th 6-byte MAC address.
83269  *
83270  * Field Access Macros:
83271  *
83272  */
83273 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
83274 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_LSB 0
83275 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
83276 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_MSB 15
83277 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
83278 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_WIDTH 16
83279 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
83280 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET_MSK 0x0000ffff
83281 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
83282 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_CLR_MSK 0xffff0000
83283 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
83284 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_RESET 0xffff
83285 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI field value from a register. */
83286 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
83287 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value suitable for setting the register. */
83288 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
83289 
83290 /*
83291  * Field : Mask Byte Control - mbc_0
83292  *
83293  * This array of bits are mask control bits for comparison of each of the MAC
83294  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83295  * received DA or SA with the contents of MAC Address104 high and low registers.
83296  * Each bit controls the masking of the bytes. You can filter a group of addresses
83297  * (known as group address filtering) by masking one or more bytes of the address.
83298  *
83299  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83300  *
83301  * Field Enumeration Values:
83302  *
83303  * Enum | Value | Description
83304  * :-----------------------------------------------|:------|:------------------------------------
83305  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83306  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83307  *
83308  * Field Access Macros:
83309  *
83310  */
83311 /*
83312  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0
83313  *
83314  * Byte is unmasked (i.e. is compared)
83315  */
83316 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED 0x0
83317 /*
83318  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0
83319  *
83320  * Byte is masked (i.e. not compared)
83321  */
83322 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED 0x1
83323 
83324 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
83325 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_LSB 24
83326 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
83327 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_MSB 24
83328 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
83329 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_WIDTH 1
83330 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */
83331 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET_MSK 0x01000000
83332 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */
83333 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_CLR_MSK 0xfeffffff
83334 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
83335 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_RESET 0x0
83336 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 field value from a register. */
83337 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
83338 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value suitable for setting the register. */
83339 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
83340 
83341 /*
83342  * Field : Mask Byte Control - mbc_1
83343  *
83344  * This array of bits are mask control bits for comparison of each of the MAC
83345  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83346  * received DA or SA with the contents of MAC Address104 high and low registers.
83347  * Each bit controls the masking of the bytes. You can filter a group of addresses
83348  * (known as group address filtering) by masking one or more bytes of the address.
83349  *
83350  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83351  *
83352  * Field Enumeration Values:
83353  *
83354  * Enum | Value | Description
83355  * :-----------------------------------------------|:------|:------------------------------------
83356  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83357  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83358  *
83359  * Field Access Macros:
83360  *
83361  */
83362 /*
83363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1
83364  *
83365  * Byte is unmasked (i.e. is compared)
83366  */
83367 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED 0x0
83368 /*
83369  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1
83370  *
83371  * Byte is masked (i.e. not compared)
83372  */
83373 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED 0x1
83374 
83375 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
83376 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_LSB 25
83377 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
83378 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_MSB 25
83379 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
83380 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_WIDTH 1
83381 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */
83382 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET_MSK 0x02000000
83383 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */
83384 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_CLR_MSK 0xfdffffff
83385 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
83386 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_RESET 0x0
83387 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 field value from a register. */
83388 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
83389 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value suitable for setting the register. */
83390 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
83391 
83392 /*
83393  * Field : Mask Byte Control - mbc_2
83394  *
83395  * This array of bits are mask control bits for comparison of each of the MAC
83396  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83397  * received DA or SA with the contents of MAC Address104 high and low registers.
83398  * Each bit controls the masking of the bytes. You can filter a group of addresses
83399  * (known as group address filtering) by masking one or more bytes of the address.
83400  *
83401  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83402  *
83403  * Field Enumeration Values:
83404  *
83405  * Enum | Value | Description
83406  * :-----------------------------------------------|:------|:------------------------------------
83407  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83408  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83409  *
83410  * Field Access Macros:
83411  *
83412  */
83413 /*
83414  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2
83415  *
83416  * Byte is unmasked (i.e. is compared)
83417  */
83418 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED 0x0
83419 /*
83420  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2
83421  *
83422  * Byte is masked (i.e. not compared)
83423  */
83424 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED 0x1
83425 
83426 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
83427 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_LSB 26
83428 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
83429 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_MSB 26
83430 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
83431 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_WIDTH 1
83432 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */
83433 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET_MSK 0x04000000
83434 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */
83435 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_CLR_MSK 0xfbffffff
83436 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
83437 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_RESET 0x0
83438 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 field value from a register. */
83439 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
83440 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value suitable for setting the register. */
83441 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
83442 
83443 /*
83444  * Field : Mask Byte Control - mbc_3
83445  *
83446  * This array of bits are mask control bits for comparison of each of the MAC
83447  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83448  * received DA or SA with the contents of MAC Address104 high and low registers.
83449  * Each bit controls the masking of the bytes. You can filter a group of addresses
83450  * (known as group address filtering) by masking one or more bytes of the address.
83451  *
83452  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83453  *
83454  * Field Enumeration Values:
83455  *
83456  * Enum | Value | Description
83457  * :-----------------------------------------------|:------|:------------------------------------
83458  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83459  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83460  *
83461  * Field Access Macros:
83462  *
83463  */
83464 /*
83465  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3
83466  *
83467  * Byte is unmasked (i.e. is compared)
83468  */
83469 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED 0x0
83470 /*
83471  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3
83472  *
83473  * Byte is masked (i.e. not compared)
83474  */
83475 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED 0x1
83476 
83477 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
83478 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_LSB 27
83479 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
83480 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_MSB 27
83481 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
83482 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_WIDTH 1
83483 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */
83484 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET_MSK 0x08000000
83485 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */
83486 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_CLR_MSK 0xf7ffffff
83487 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
83488 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_RESET 0x0
83489 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 field value from a register. */
83490 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
83491 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value suitable for setting the register. */
83492 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
83493 
83494 /*
83495  * Field : Mask Byte Control - mbc_4
83496  *
83497  * This array of bits are mask control bits for comparison of each of the MAC
83498  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83499  * received DA or SA with the contents of MAC Address104 high and low registers.
83500  * Each bit controls the masking of the bytes. You can filter a group of addresses
83501  * (known as group address filtering) by masking one or more bytes of the address.
83502  *
83503  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83504  *
83505  * Field Enumeration Values:
83506  *
83507  * Enum | Value | Description
83508  * :-----------------------------------------------|:------|:------------------------------------
83509  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83510  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83511  *
83512  * Field Access Macros:
83513  *
83514  */
83515 /*
83516  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4
83517  *
83518  * Byte is unmasked (i.e. is compared)
83519  */
83520 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED 0x0
83521 /*
83522  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4
83523  *
83524  * Byte is masked (i.e. not compared)
83525  */
83526 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED 0x1
83527 
83528 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
83529 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_LSB 28
83530 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
83531 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_MSB 28
83532 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
83533 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_WIDTH 1
83534 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */
83535 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET_MSK 0x10000000
83536 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */
83537 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_CLR_MSK 0xefffffff
83538 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
83539 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_RESET 0x0
83540 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 field value from a register. */
83541 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
83542 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value suitable for setting the register. */
83543 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
83544 
83545 /*
83546  * Field : Mask Byte Control - mbc_5
83547  *
83548  * This array of bits are mask control bits for comparison of each of the MAC
83549  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83550  * received DA or SA with the contents of MAC Address104 high and low registers.
83551  * Each bit controls the masking of the bytes. You can filter a group of addresses
83552  * (known as group address filtering) by masking one or more bytes of the address.
83553  *
83554  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83555  *
83556  * Field Enumeration Values:
83557  *
83558  * Enum | Value | Description
83559  * :-----------------------------------------------|:------|:------------------------------------
83560  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83561  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83562  *
83563  * Field Access Macros:
83564  *
83565  */
83566 /*
83567  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5
83568  *
83569  * Byte is unmasked (i.e. is compared)
83570  */
83571 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED 0x0
83572 /*
83573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5
83574  *
83575  * Byte is masked (i.e. not compared)
83576  */
83577 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED 0x1
83578 
83579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
83580 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_LSB 29
83581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
83582 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_MSB 29
83583 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
83584 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_WIDTH 1
83585 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */
83586 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET_MSK 0x20000000
83587 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */
83588 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_CLR_MSK 0xdfffffff
83589 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
83590 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_RESET 0x0
83591 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 field value from a register. */
83592 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
83593 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value suitable for setting the register. */
83594 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
83595 
83596 /*
83597  * Field : Source Address - sa
83598  *
83599  * When this bit is enabled, the MAC Address104[47:0] is used to compare with the
83600  * SA fields of the received frame. When this bit is disabled, the MAC
83601  * Address104[47:0] is used to compare with the DA fields of the received frame.
83602  *
83603  * Field Enumeration Values:
83604  *
83605  * Enum | Value | Description
83606  * :-----------------------------------------|:------|:-----------------------------
83607  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
83608  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END | 0x1 | MAC address compare enabled
83609  *
83610  * Field Access Macros:
83611  *
83612  */
83613 /*
83614  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA
83615  *
83616  * MAC address compare disabled
83617  */
83618 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD 0x0
83619 /*
83620  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA
83621  *
83622  * MAC address compare enabled
83623  */
83624 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END 0x1
83625 
83626 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
83627 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_LSB 30
83628 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
83629 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_MSB 30
83630 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
83631 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_WIDTH 1
83632 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */
83633 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET_MSK 0x40000000
83634 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */
83635 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_CLR_MSK 0xbfffffff
83636 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
83637 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_RESET 0x0
83638 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA field value from a register. */
83639 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
83640 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value suitable for setting the register. */
83641 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
83642 
83643 /*
83644  * Field : Address Enable - ae
83645  *
83646  * When this bit is enabled, the address filter block uses the 105th MAC address
83647  * for perfect filtering. When this bit is disabled, the address filter block
83648  * ignores the address for filtering.
83649  *
83650  * Field Enumeration Values:
83651  *
83652  * Enum | Value | Description
83653  * :-----------------------------------------|:------|:--------------------------------------
83654  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
83655  * ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
83656  *
83657  * Field Access Macros:
83658  *
83659  */
83660 /*
83661  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
83662  *
83663  * Second MAC address filtering disabled
83664  */
83665 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD 0x0
83666 /*
83667  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
83668  *
83669  * Second MAC address filtering enabled
83670  */
83671 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END 0x1
83672 
83673 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
83674 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_LSB 31
83675 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
83676 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_MSB 31
83677 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
83678 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_WIDTH 1
83679 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
83680 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET_MSK 0x80000000
83681 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
83682 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_CLR_MSK 0x7fffffff
83683 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
83684 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_RESET 0x0
83685 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE field value from a register. */
83686 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
83687 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value suitable for setting the register. */
83688 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
83689 
83690 #ifndef __ASSEMBLY__
83691 /*
83692  * WARNING: The C register and register group struct declarations are provided for
83693  * convenience and illustrative purposes. They should, however, be used with
83694  * caution as the C language standard provides no guarantees about the alignment or
83695  * atomicity of device memory accesses. The recommended practice for writing
83696  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
83697  * alt_write_word() functions.
83698  *
83699  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH.
83700  */
83701 struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s
83702 {
83703  uint32_t addrhi : 16; /* MAC Address104 [47:32] */
83704  uint32_t : 8; /* *UNDEFINED* */
83705  uint32_t mbc_0 : 1; /* Mask Byte Control */
83706  uint32_t mbc_1 : 1; /* Mask Byte Control */
83707  uint32_t mbc_2 : 1; /* Mask Byte Control */
83708  uint32_t mbc_3 : 1; /* Mask Byte Control */
83709  uint32_t mbc_4 : 1; /* Mask Byte Control */
83710  uint32_t mbc_5 : 1; /* Mask Byte Control */
83711  uint32_t sa : 1; /* Source Address */
83712  uint32_t ae : 1; /* Address Enable */
83713 };
83714 
83715 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH. */
83716 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t;
83717 #endif /* __ASSEMBLY__ */
83718 
83719 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register from the beginning of the component. */
83720 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST 0xac0
83721 /* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register. */
83722 #define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST))
83723 
83724 /*
83725  * Register : Register 689 (MAC Address104 Low Register) - MAC_Address104_Low
83726  *
83727  * The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC
83728  * address of the station.
83729  *
83730  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
83731  * format.
83732  *
83733  * Register Layout
83734  *
83735  * Bits | Access | Reset | Description
83736  * :-------|:-------|:-----------|:----------------------
83737  * [31:0] | RW | 0xffffffff | MAC Address104 [31:0]
83738  *
83739  */
83740 /*
83741  * Field : MAC Address104 [31:0] - addrlo
83742  *
83743  * This field contains the lower 32 bits of the 105th 6-byte MAC address. The
83744  * content of this field is undefined until loaded by software after the
83745  * initialization process.
83746  *
83747  * Field Access Macros:
83748  *
83749  */
83750 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
83751 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_LSB 0
83752 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
83753 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_MSB 31
83754 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
83755 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_WIDTH 32
83756 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
83757 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET_MSK 0xffffffff
83758 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
83759 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_CLR_MSK 0x00000000
83760 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
83761 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_RESET 0xffffffff
83762 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO field value from a register. */
83763 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
83764 /* Produces a ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value suitable for setting the register. */
83765 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
83766 
83767 #ifndef __ASSEMBLY__
83768 /*
83769  * WARNING: The C register and register group struct declarations are provided for
83770  * convenience and illustrative purposes. They should, however, be used with
83771  * caution as the C language standard provides no guarantees about the alignment or
83772  * atomicity of device memory accesses. The recommended practice for writing
83773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
83774  * alt_write_word() functions.
83775  *
83776  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW.
83777  */
83778 struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s
83779 {
83780  uint32_t addrlo : 32; /* MAC Address104 [31:0] */
83781 };
83782 
83783 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW. */
83784 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s ALT_EMAC_GMAC_MAC_ADDR104_LOW_t;
83785 #endif /* __ASSEMBLY__ */
83786 
83787 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register from the beginning of the component. */
83788 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST 0xac4
83789 /* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register. */
83790 #define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST))
83791 
83792 /*
83793  * Register : Register 690 (MAC Address105 High Register) - MAC_Address105_High
83794  *
83795  * The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC
83796  * address of the station. Because the MAC address registers are configured to be
83797  * double-synchronized to the (G)MII clock domains, the synchronization is
83798  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
83799  * endian mode) of the MAC Address105 Low Register are written. For proper
83800  * synchronization updates, the consecutive writes to this Address Low Register
83801  * should be performed after at least four clock cycles in the destination clock
83802  * domain.
83803  *
83804  * Note that all MAC Address High registers (except MAC Address0 High) have the
83805  * same format.
83806  *
83807  * Register Layout
83808  *
83809  * Bits | Access | Reset | Description
83810  * :--------|:-------|:-------|:-----------------------
83811  * [15:0] | RW | 0xffff | MAC Address105 [47:32]
83812  * [23:16] | ??? | 0x0 | *UNDEFINED*
83813  * [24] | RW | 0x0 | Mask Byte Control
83814  * [25] | RW | 0x0 | Mask Byte Control
83815  * [26] | RW | 0x0 | Mask Byte Control
83816  * [27] | RW | 0x0 | Mask Byte Control
83817  * [28] | RW | 0x0 | Mask Byte Control
83818  * [29] | RW | 0x0 | Mask Byte Control
83819  * [30] | RW | 0x0 | Source Address
83820  * [31] | RW | 0x0 | Address Enable
83821  *
83822  */
83823 /*
83824  * Field : MAC Address105 [47:32] - addrhi
83825  *
83826  * This field contains the upper 16 bits (47:32) of the 106th 6-byte MAC address.
83827  *
83828  * Field Access Macros:
83829  *
83830  */
83831 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
83832 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_LSB 0
83833 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
83834 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_MSB 15
83835 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
83836 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_WIDTH 16
83837 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
83838 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET_MSK 0x0000ffff
83839 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
83840 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_CLR_MSK 0xffff0000
83841 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
83842 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_RESET 0xffff
83843 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI field value from a register. */
83844 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
83845 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value suitable for setting the register. */
83846 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
83847 
83848 /*
83849  * Field : Mask Byte Control - mbc_0
83850  *
83851  * This array of bits are mask control bits for comparison of each of the MAC
83852  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83853  * received DA or SA with the contents of MAC Address105 high and low registers.
83854  * Each bit controls the masking of the bytes. You can filter a group of addresses
83855  * (known as group address filtering) by masking one or more bytes of the address.
83856  *
83857  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83858  *
83859  * Field Enumeration Values:
83860  *
83861  * Enum | Value | Description
83862  * :-----------------------------------------------|:------|:------------------------------------
83863  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83864  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83865  *
83866  * Field Access Macros:
83867  *
83868  */
83869 /*
83870  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0
83871  *
83872  * Byte is unmasked (i.e. is compared)
83873  */
83874 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED 0x0
83875 /*
83876  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0
83877  *
83878  * Byte is masked (i.e. not compared)
83879  */
83880 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED 0x1
83881 
83882 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
83883 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_LSB 24
83884 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
83885 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_MSB 24
83886 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
83887 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_WIDTH 1
83888 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */
83889 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET_MSK 0x01000000
83890 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */
83891 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_CLR_MSK 0xfeffffff
83892 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
83893 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_RESET 0x0
83894 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 field value from a register. */
83895 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
83896 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value suitable for setting the register. */
83897 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
83898 
83899 /*
83900  * Field : Mask Byte Control - mbc_1
83901  *
83902  * This array of bits are mask control bits for comparison of each of the MAC
83903  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83904  * received DA or SA with the contents of MAC Address105 high and low registers.
83905  * Each bit controls the masking of the bytes. You can filter a group of addresses
83906  * (known as group address filtering) by masking one or more bytes of the address.
83907  *
83908  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83909  *
83910  * Field Enumeration Values:
83911  *
83912  * Enum | Value | Description
83913  * :-----------------------------------------------|:------|:------------------------------------
83914  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83915  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83916  *
83917  * Field Access Macros:
83918  *
83919  */
83920 /*
83921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1
83922  *
83923  * Byte is unmasked (i.e. is compared)
83924  */
83925 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED 0x0
83926 /*
83927  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1
83928  *
83929  * Byte is masked (i.e. not compared)
83930  */
83931 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED 0x1
83932 
83933 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
83934 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_LSB 25
83935 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
83936 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_MSB 25
83937 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
83938 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_WIDTH 1
83939 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */
83940 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET_MSK 0x02000000
83941 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */
83942 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_CLR_MSK 0xfdffffff
83943 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
83944 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_RESET 0x0
83945 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 field value from a register. */
83946 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
83947 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value suitable for setting the register. */
83948 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
83949 
83950 /*
83951  * Field : Mask Byte Control - mbc_2
83952  *
83953  * This array of bits are mask control bits for comparison of each of the MAC
83954  * Address bytes. When masked, the MAC does not compare the corresponding byte of
83955  * received DA or SA with the contents of MAC Address105 high and low registers.
83956  * Each bit controls the masking of the bytes. You can filter a group of addresses
83957  * (known as group address filtering) by masking one or more bytes of the address.
83958  *
83959  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
83960  *
83961  * Field Enumeration Values:
83962  *
83963  * Enum | Value | Description
83964  * :-----------------------------------------------|:------|:------------------------------------
83965  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
83966  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
83967  *
83968  * Field Access Macros:
83969  *
83970  */
83971 /*
83972  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2
83973  *
83974  * Byte is unmasked (i.e. is compared)
83975  */
83976 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED 0x0
83977 /*
83978  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2
83979  *
83980  * Byte is masked (i.e. not compared)
83981  */
83982 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED 0x1
83983 
83984 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
83985 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_LSB 26
83986 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
83987 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_MSB 26
83988 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
83989 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_WIDTH 1
83990 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */
83991 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET_MSK 0x04000000
83992 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */
83993 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_CLR_MSK 0xfbffffff
83994 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
83995 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_RESET 0x0
83996 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 field value from a register. */
83997 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
83998 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value suitable for setting the register. */
83999 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
84000 
84001 /*
84002  * Field : Mask Byte Control - mbc_3
84003  *
84004  * This array of bits are mask control bits for comparison of each of the MAC
84005  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84006  * received DA or SA with the contents of MAC Address105 high and low registers.
84007  * Each bit controls the masking of the bytes. You can filter a group of addresses
84008  * (known as group address filtering) by masking one or more bytes of the address.
84009  *
84010  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84011  *
84012  * Field Enumeration Values:
84013  *
84014  * Enum | Value | Description
84015  * :-----------------------------------------------|:------|:------------------------------------
84016  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84017  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84018  *
84019  * Field Access Macros:
84020  *
84021  */
84022 /*
84023  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3
84024  *
84025  * Byte is unmasked (i.e. is compared)
84026  */
84027 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED 0x0
84028 /*
84029  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3
84030  *
84031  * Byte is masked (i.e. not compared)
84032  */
84033 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED 0x1
84034 
84035 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
84036 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_LSB 27
84037 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
84038 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_MSB 27
84039 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
84040 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_WIDTH 1
84041 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */
84042 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET_MSK 0x08000000
84043 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */
84044 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_CLR_MSK 0xf7ffffff
84045 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
84046 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_RESET 0x0
84047 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 field value from a register. */
84048 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
84049 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value suitable for setting the register. */
84050 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
84051 
84052 /*
84053  * Field : Mask Byte Control - mbc_4
84054  *
84055  * This array of bits are mask control bits for comparison of each of the MAC
84056  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84057  * received DA or SA with the contents of MAC Address105 high and low registers.
84058  * Each bit controls the masking of the bytes. You can filter a group of addresses
84059  * (known as group address filtering) by masking one or more bytes of the address.
84060  *
84061  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84062  *
84063  * Field Enumeration Values:
84064  *
84065  * Enum | Value | Description
84066  * :-----------------------------------------------|:------|:------------------------------------
84067  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84068  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84069  *
84070  * Field Access Macros:
84071  *
84072  */
84073 /*
84074  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4
84075  *
84076  * Byte is unmasked (i.e. is compared)
84077  */
84078 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED 0x0
84079 /*
84080  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4
84081  *
84082  * Byte is masked (i.e. not compared)
84083  */
84084 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED 0x1
84085 
84086 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
84087 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_LSB 28
84088 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
84089 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_MSB 28
84090 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
84091 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_WIDTH 1
84092 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */
84093 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET_MSK 0x10000000
84094 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */
84095 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_CLR_MSK 0xefffffff
84096 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
84097 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_RESET 0x0
84098 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 field value from a register. */
84099 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
84100 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value suitable for setting the register. */
84101 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
84102 
84103 /*
84104  * Field : Mask Byte Control - mbc_5
84105  *
84106  * This array of bits are mask control bits for comparison of each of the MAC
84107  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84108  * received DA or SA with the contents of MAC Address105 high and low registers.
84109  * Each bit controls the masking of the bytes. You can filter a group of addresses
84110  * (known as group address filtering) by masking one or more bytes of the address.
84111  *
84112  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84113  *
84114  * Field Enumeration Values:
84115  *
84116  * Enum | Value | Description
84117  * :-----------------------------------------------|:------|:------------------------------------
84118  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84119  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84120  *
84121  * Field Access Macros:
84122  *
84123  */
84124 /*
84125  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5
84126  *
84127  * Byte is unmasked (i.e. is compared)
84128  */
84129 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED 0x0
84130 /*
84131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5
84132  *
84133  * Byte is masked (i.e. not compared)
84134  */
84135 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED 0x1
84136 
84137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
84138 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_LSB 29
84139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
84140 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_MSB 29
84141 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
84142 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_WIDTH 1
84143 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */
84144 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET_MSK 0x20000000
84145 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */
84146 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_CLR_MSK 0xdfffffff
84147 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
84148 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_RESET 0x0
84149 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 field value from a register. */
84150 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
84151 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value suitable for setting the register. */
84152 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
84153 
84154 /*
84155  * Field : Source Address - sa
84156  *
84157  * When this bit is enabled, the MAC Address105[47:0] is used to compare with the
84158  * SA fields of the received frame. When this bit is disabled, the MAC
84159  * Address105[47:0] is used to compare with the DA fields of the received frame.
84160  *
84161  * Field Enumeration Values:
84162  *
84163  * Enum | Value | Description
84164  * :-----------------------------------------|:------|:-----------------------------
84165  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
84166  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END | 0x1 | MAC address compare enabled
84167  *
84168  * Field Access Macros:
84169  *
84170  */
84171 /*
84172  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA
84173  *
84174  * MAC address compare disabled
84175  */
84176 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD 0x0
84177 /*
84178  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA
84179  *
84180  * MAC address compare enabled
84181  */
84182 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END 0x1
84183 
84184 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
84185 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_LSB 30
84186 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
84187 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_MSB 30
84188 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
84189 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_WIDTH 1
84190 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */
84191 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET_MSK 0x40000000
84192 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */
84193 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_CLR_MSK 0xbfffffff
84194 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
84195 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_RESET 0x0
84196 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA field value from a register. */
84197 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
84198 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value suitable for setting the register. */
84199 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
84200 
84201 /*
84202  * Field : Address Enable - ae
84203  *
84204  * When this bit is enabled, the address filter block uses the 106th MAC address
84205  * for perfect filtering. When this bit is disabled, the address filter block
84206  * ignores the address for filtering.
84207  *
84208  * Field Enumeration Values:
84209  *
84210  * Enum | Value | Description
84211  * :-----------------------------------------|:------|:--------------------------------------
84212  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
84213  * ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
84214  *
84215  * Field Access Macros:
84216  *
84217  */
84218 /*
84219  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
84220  *
84221  * Second MAC address filtering disabled
84222  */
84223 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD 0x0
84224 /*
84225  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
84226  *
84227  * Second MAC address filtering enabled
84228  */
84229 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END 0x1
84230 
84231 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
84232 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_LSB 31
84233 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
84234 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_MSB 31
84235 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
84236 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_WIDTH 1
84237 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
84238 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET_MSK 0x80000000
84239 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
84240 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_CLR_MSK 0x7fffffff
84241 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
84242 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_RESET 0x0
84243 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE field value from a register. */
84244 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
84245 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value suitable for setting the register. */
84246 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
84247 
84248 #ifndef __ASSEMBLY__
84249 /*
84250  * WARNING: The C register and register group struct declarations are provided for
84251  * convenience and illustrative purposes. They should, however, be used with
84252  * caution as the C language standard provides no guarantees about the alignment or
84253  * atomicity of device memory accesses. The recommended practice for writing
84254  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84255  * alt_write_word() functions.
84256  *
84257  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH.
84258  */
84259 struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s
84260 {
84261  uint32_t addrhi : 16; /* MAC Address105 [47:32] */
84262  uint32_t : 8; /* *UNDEFINED* */
84263  uint32_t mbc_0 : 1; /* Mask Byte Control */
84264  uint32_t mbc_1 : 1; /* Mask Byte Control */
84265  uint32_t mbc_2 : 1; /* Mask Byte Control */
84266  uint32_t mbc_3 : 1; /* Mask Byte Control */
84267  uint32_t mbc_4 : 1; /* Mask Byte Control */
84268  uint32_t mbc_5 : 1; /* Mask Byte Control */
84269  uint32_t sa : 1; /* Source Address */
84270  uint32_t ae : 1; /* Address Enable */
84271 };
84272 
84273 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH. */
84274 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t;
84275 #endif /* __ASSEMBLY__ */
84276 
84277 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register from the beginning of the component. */
84278 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST 0xac8
84279 /* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register. */
84280 #define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST))
84281 
84282 /*
84283  * Register : Register 691 (MAC Address105 Low Register) - MAC_Address105_Low
84284  *
84285  * The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC
84286  * address of the station.
84287  *
84288  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
84289  * format.
84290  *
84291  * Register Layout
84292  *
84293  * Bits | Access | Reset | Description
84294  * :-------|:-------|:-----------|:----------------------
84295  * [31:0] | RW | 0xffffffff | MAC Address105 [31:0]
84296  *
84297  */
84298 /*
84299  * Field : MAC Address105 [31:0] - addrlo
84300  *
84301  * This field contains the lower 32 bits of the 106th 6-byte MAC address. The
84302  * content of this field is undefined until loaded by software after the
84303  * initialization process.
84304  *
84305  * Field Access Macros:
84306  *
84307  */
84308 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
84309 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_LSB 0
84310 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
84311 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_MSB 31
84312 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
84313 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_WIDTH 32
84314 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
84315 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET_MSK 0xffffffff
84316 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
84317 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_CLR_MSK 0x00000000
84318 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
84319 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_RESET 0xffffffff
84320 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO field value from a register. */
84321 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
84322 /* Produces a ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value suitable for setting the register. */
84323 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
84324 
84325 #ifndef __ASSEMBLY__
84326 /*
84327  * WARNING: The C register and register group struct declarations are provided for
84328  * convenience and illustrative purposes. They should, however, be used with
84329  * caution as the C language standard provides no guarantees about the alignment or
84330  * atomicity of device memory accesses. The recommended practice for writing
84331  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84332  * alt_write_word() functions.
84333  *
84334  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW.
84335  */
84336 struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s
84337 {
84338  uint32_t addrlo : 32; /* MAC Address105 [31:0] */
84339 };
84340 
84341 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW. */
84342 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s ALT_EMAC_GMAC_MAC_ADDR105_LOW_t;
84343 #endif /* __ASSEMBLY__ */
84344 
84345 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register from the beginning of the component. */
84346 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST 0xacc
84347 /* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register. */
84348 #define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST))
84349 
84350 /*
84351  * Register : Register 692 (MAC Address106 High Register) - MAC_Address106_High
84352  *
84353  * The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC
84354  * address of the station. Because the MAC address registers are configured to be
84355  * double-synchronized to the (G)MII clock domains, the synchronization is
84356  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
84357  * endian mode) of the MAC Address106 Low Register are written. For proper
84358  * synchronization updates, the consecutive writes to this Address Low Register
84359  * should be performed after at least four clock cycles in the destination clock
84360  * domain.
84361  *
84362  * Note that all MAC Address High registers (except MAC Address0 High) have the
84363  * same format.
84364  *
84365  * Register Layout
84366  *
84367  * Bits | Access | Reset | Description
84368  * :--------|:-------|:-------|:-----------------------
84369  * [15:0] | RW | 0xffff | MAC Address106 [47:32]
84370  * [23:16] | ??? | 0x0 | *UNDEFINED*
84371  * [24] | RW | 0x0 | Mask Byte Control
84372  * [25] | RW | 0x0 | Mask Byte Control
84373  * [26] | RW | 0x0 | Mask Byte Control
84374  * [27] | RW | 0x0 | Mask Byte Control
84375  * [28] | RW | 0x0 | Mask Byte Control
84376  * [29] | RW | 0x0 | Mask Byte Control
84377  * [30] | RW | 0x0 | Source Address
84378  * [31] | RW | 0x0 | Address Enable
84379  *
84380  */
84381 /*
84382  * Field : MAC Address106 [47:32] - addrhi
84383  *
84384  * This field contains the upper 16 bits (47:32) of the 107th 6-byte MAC address.
84385  *
84386  * Field Access Macros:
84387  *
84388  */
84389 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
84390 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_LSB 0
84391 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
84392 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_MSB 15
84393 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
84394 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_WIDTH 16
84395 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
84396 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET_MSK 0x0000ffff
84397 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
84398 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_CLR_MSK 0xffff0000
84399 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
84400 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_RESET 0xffff
84401 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI field value from a register. */
84402 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
84403 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value suitable for setting the register. */
84404 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
84405 
84406 /*
84407  * Field : Mask Byte Control - mbc_0
84408  *
84409  * This array of bits are mask control bits for comparison of each of the MAC
84410  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84411  * received DA or SA with the contents of MAC Address106 high and low registers.
84412  * Each bit controls the masking of the bytes. You can filter a group of addresses
84413  * (known as group address filtering) by masking one or more bytes of the address.
84414  *
84415  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84416  *
84417  * Field Enumeration Values:
84418  *
84419  * Enum | Value | Description
84420  * :-----------------------------------------------|:------|:------------------------------------
84421  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84422  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84423  *
84424  * Field Access Macros:
84425  *
84426  */
84427 /*
84428  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0
84429  *
84430  * Byte is unmasked (i.e. is compared)
84431  */
84432 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED 0x0
84433 /*
84434  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0
84435  *
84436  * Byte is masked (i.e. not compared)
84437  */
84438 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED 0x1
84439 
84440 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
84441 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_LSB 24
84442 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
84443 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_MSB 24
84444 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
84445 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_WIDTH 1
84446 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */
84447 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET_MSK 0x01000000
84448 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */
84449 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_CLR_MSK 0xfeffffff
84450 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
84451 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_RESET 0x0
84452 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 field value from a register. */
84453 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
84454 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value suitable for setting the register. */
84455 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
84456 
84457 /*
84458  * Field : Mask Byte Control - mbc_1
84459  *
84460  * This array of bits are mask control bits for comparison of each of the MAC
84461  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84462  * received DA or SA with the contents of MAC Address106 high and low registers.
84463  * Each bit controls the masking of the bytes. You can filter a group of addresses
84464  * (known as group address filtering) by masking one or more bytes of the address.
84465  *
84466  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84467  *
84468  * Field Enumeration Values:
84469  *
84470  * Enum | Value | Description
84471  * :-----------------------------------------------|:------|:------------------------------------
84472  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84473  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84474  *
84475  * Field Access Macros:
84476  *
84477  */
84478 /*
84479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1
84480  *
84481  * Byte is unmasked (i.e. is compared)
84482  */
84483 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED 0x0
84484 /*
84485  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1
84486  *
84487  * Byte is masked (i.e. not compared)
84488  */
84489 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED 0x1
84490 
84491 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
84492 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_LSB 25
84493 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
84494 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_MSB 25
84495 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
84496 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_WIDTH 1
84497 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */
84498 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET_MSK 0x02000000
84499 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */
84500 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_CLR_MSK 0xfdffffff
84501 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
84502 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_RESET 0x0
84503 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 field value from a register. */
84504 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
84505 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value suitable for setting the register. */
84506 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
84507 
84508 /*
84509  * Field : Mask Byte Control - mbc_2
84510  *
84511  * This array of bits are mask control bits for comparison of each of the MAC
84512  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84513  * received DA or SA with the contents of MAC Address106 high and low registers.
84514  * Each bit controls the masking of the bytes. You can filter a group of addresses
84515  * (known as group address filtering) by masking one or more bytes of the address.
84516  *
84517  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84518  *
84519  * Field Enumeration Values:
84520  *
84521  * Enum | Value | Description
84522  * :-----------------------------------------------|:------|:------------------------------------
84523  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84524  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84525  *
84526  * Field Access Macros:
84527  *
84528  */
84529 /*
84530  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2
84531  *
84532  * Byte is unmasked (i.e. is compared)
84533  */
84534 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED 0x0
84535 /*
84536  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2
84537  *
84538  * Byte is masked (i.e. not compared)
84539  */
84540 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED 0x1
84541 
84542 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
84543 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_LSB 26
84544 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
84545 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_MSB 26
84546 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
84547 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_WIDTH 1
84548 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */
84549 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET_MSK 0x04000000
84550 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */
84551 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_CLR_MSK 0xfbffffff
84552 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
84553 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_RESET 0x0
84554 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 field value from a register. */
84555 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
84556 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value suitable for setting the register. */
84557 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
84558 
84559 /*
84560  * Field : Mask Byte Control - mbc_3
84561  *
84562  * This array of bits are mask control bits for comparison of each of the MAC
84563  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84564  * received DA or SA with the contents of MAC Address106 high and low registers.
84565  * Each bit controls the masking of the bytes. You can filter a group of addresses
84566  * (known as group address filtering) by masking one or more bytes of the address.
84567  *
84568  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84569  *
84570  * Field Enumeration Values:
84571  *
84572  * Enum | Value | Description
84573  * :-----------------------------------------------|:------|:------------------------------------
84574  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84575  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84576  *
84577  * Field Access Macros:
84578  *
84579  */
84580 /*
84581  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3
84582  *
84583  * Byte is unmasked (i.e. is compared)
84584  */
84585 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED 0x0
84586 /*
84587  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3
84588  *
84589  * Byte is masked (i.e. not compared)
84590  */
84591 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED 0x1
84592 
84593 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
84594 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_LSB 27
84595 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
84596 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_MSB 27
84597 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
84598 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_WIDTH 1
84599 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */
84600 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET_MSK 0x08000000
84601 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */
84602 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_CLR_MSK 0xf7ffffff
84603 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
84604 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_RESET 0x0
84605 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 field value from a register. */
84606 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
84607 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value suitable for setting the register. */
84608 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
84609 
84610 /*
84611  * Field : Mask Byte Control - mbc_4
84612  *
84613  * This array of bits are mask control bits for comparison of each of the MAC
84614  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84615  * received DA or SA with the contents of MAC Address106 high and low registers.
84616  * Each bit controls the masking of the bytes. You can filter a group of addresses
84617  * (known as group address filtering) by masking one or more bytes of the address.
84618  *
84619  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84620  *
84621  * Field Enumeration Values:
84622  *
84623  * Enum | Value | Description
84624  * :-----------------------------------------------|:------|:------------------------------------
84625  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84626  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84627  *
84628  * Field Access Macros:
84629  *
84630  */
84631 /*
84632  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4
84633  *
84634  * Byte is unmasked (i.e. is compared)
84635  */
84636 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED 0x0
84637 /*
84638  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4
84639  *
84640  * Byte is masked (i.e. not compared)
84641  */
84642 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED 0x1
84643 
84644 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
84645 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_LSB 28
84646 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
84647 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_MSB 28
84648 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
84649 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_WIDTH 1
84650 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */
84651 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET_MSK 0x10000000
84652 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */
84653 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_CLR_MSK 0xefffffff
84654 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
84655 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_RESET 0x0
84656 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 field value from a register. */
84657 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
84658 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value suitable for setting the register. */
84659 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
84660 
84661 /*
84662  * Field : Mask Byte Control - mbc_5
84663  *
84664  * This array of bits are mask control bits for comparison of each of the MAC
84665  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84666  * received DA or SA with the contents of MAC Address106 high and low registers.
84667  * Each bit controls the masking of the bytes. You can filter a group of addresses
84668  * (known as group address filtering) by masking one or more bytes of the address.
84669  *
84670  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84671  *
84672  * Field Enumeration Values:
84673  *
84674  * Enum | Value | Description
84675  * :-----------------------------------------------|:------|:------------------------------------
84676  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84677  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84678  *
84679  * Field Access Macros:
84680  *
84681  */
84682 /*
84683  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5
84684  *
84685  * Byte is unmasked (i.e. is compared)
84686  */
84687 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED 0x0
84688 /*
84689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5
84690  *
84691  * Byte is masked (i.e. not compared)
84692  */
84693 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED 0x1
84694 
84695 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
84696 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_LSB 29
84697 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
84698 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_MSB 29
84699 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
84700 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_WIDTH 1
84701 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */
84702 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET_MSK 0x20000000
84703 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */
84704 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_CLR_MSK 0xdfffffff
84705 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
84706 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_RESET 0x0
84707 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 field value from a register. */
84708 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
84709 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value suitable for setting the register. */
84710 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
84711 
84712 /*
84713  * Field : Source Address - sa
84714  *
84715  * When this bit is enabled, the MAC Address106[47:0] is used to compare with the
84716  * SA fields of the received frame. When this bit is disabled, the MAC
84717  * Address106[47:0] is used to compare with the DA fields of the received frame.
84718  *
84719  * Field Enumeration Values:
84720  *
84721  * Enum | Value | Description
84722  * :-----------------------------------------|:------|:-----------------------------
84723  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
84724  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END | 0x1 | MAC address compare enabled
84725  *
84726  * Field Access Macros:
84727  *
84728  */
84729 /*
84730  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA
84731  *
84732  * MAC address compare disabled
84733  */
84734 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD 0x0
84735 /*
84736  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA
84737  *
84738  * MAC address compare enabled
84739  */
84740 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END 0x1
84741 
84742 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
84743 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_LSB 30
84744 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
84745 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_MSB 30
84746 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
84747 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_WIDTH 1
84748 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */
84749 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET_MSK 0x40000000
84750 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */
84751 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_CLR_MSK 0xbfffffff
84752 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
84753 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_RESET 0x0
84754 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA field value from a register. */
84755 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
84756 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value suitable for setting the register. */
84757 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
84758 
84759 /*
84760  * Field : Address Enable - ae
84761  *
84762  * When this bit is enabled, the address filter block uses the 107th MAC address
84763  * for perfect filtering. When this bit is disabled, the address filter block
84764  * ignores the address for filtering.
84765  *
84766  * Field Enumeration Values:
84767  *
84768  * Enum | Value | Description
84769  * :-----------------------------------------|:------|:--------------------------------------
84770  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
84771  * ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
84772  *
84773  * Field Access Macros:
84774  *
84775  */
84776 /*
84777  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
84778  *
84779  * Second MAC address filtering disabled
84780  */
84781 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD 0x0
84782 /*
84783  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
84784  *
84785  * Second MAC address filtering enabled
84786  */
84787 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END 0x1
84788 
84789 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
84790 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_LSB 31
84791 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
84792 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_MSB 31
84793 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
84794 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_WIDTH 1
84795 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
84796 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET_MSK 0x80000000
84797 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
84798 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_CLR_MSK 0x7fffffff
84799 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
84800 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_RESET 0x0
84801 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE field value from a register. */
84802 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
84803 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value suitable for setting the register. */
84804 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
84805 
84806 #ifndef __ASSEMBLY__
84807 /*
84808  * WARNING: The C register and register group struct declarations are provided for
84809  * convenience and illustrative purposes. They should, however, be used with
84810  * caution as the C language standard provides no guarantees about the alignment or
84811  * atomicity of device memory accesses. The recommended practice for writing
84812  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84813  * alt_write_word() functions.
84814  *
84815  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH.
84816  */
84817 struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s
84818 {
84819  uint32_t addrhi : 16; /* MAC Address106 [47:32] */
84820  uint32_t : 8; /* *UNDEFINED* */
84821  uint32_t mbc_0 : 1; /* Mask Byte Control */
84822  uint32_t mbc_1 : 1; /* Mask Byte Control */
84823  uint32_t mbc_2 : 1; /* Mask Byte Control */
84824  uint32_t mbc_3 : 1; /* Mask Byte Control */
84825  uint32_t mbc_4 : 1; /* Mask Byte Control */
84826  uint32_t mbc_5 : 1; /* Mask Byte Control */
84827  uint32_t sa : 1; /* Source Address */
84828  uint32_t ae : 1; /* Address Enable */
84829 };
84830 
84831 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH. */
84832 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t;
84833 #endif /* __ASSEMBLY__ */
84834 
84835 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register from the beginning of the component. */
84836 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST 0xad0
84837 /* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register. */
84838 #define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST))
84839 
84840 /*
84841  * Register : Register 693 (MAC Address106 Low Register) - MAC_Address106_Low
84842  *
84843  * The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC
84844  * address of the station.
84845  *
84846  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
84847  * format.
84848  *
84849  * Register Layout
84850  *
84851  * Bits | Access | Reset | Description
84852  * :-------|:-------|:-----------|:----------------------
84853  * [31:0] | RW | 0xffffffff | MAC Address106 [31:0]
84854  *
84855  */
84856 /*
84857  * Field : MAC Address106 [31:0] - addrlo
84858  *
84859  * This field contains the lower 32 bits of the 107th 6-byte MAC address. The
84860  * content of this field is undefined until loaded by software after the
84861  * initialization process.
84862  *
84863  * Field Access Macros:
84864  *
84865  */
84866 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
84867 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_LSB 0
84868 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
84869 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_MSB 31
84870 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
84871 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_WIDTH 32
84872 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
84873 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET_MSK 0xffffffff
84874 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
84875 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_CLR_MSK 0x00000000
84876 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
84877 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_RESET 0xffffffff
84878 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO field value from a register. */
84879 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
84880 /* Produces a ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value suitable for setting the register. */
84881 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
84882 
84883 #ifndef __ASSEMBLY__
84884 /*
84885  * WARNING: The C register and register group struct declarations are provided for
84886  * convenience and illustrative purposes. They should, however, be used with
84887  * caution as the C language standard provides no guarantees about the alignment or
84888  * atomicity of device memory accesses. The recommended practice for writing
84889  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
84890  * alt_write_word() functions.
84891  *
84892  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW.
84893  */
84894 struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s
84895 {
84896  uint32_t addrlo : 32; /* MAC Address106 [31:0] */
84897 };
84898 
84899 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW. */
84900 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s ALT_EMAC_GMAC_MAC_ADDR106_LOW_t;
84901 #endif /* __ASSEMBLY__ */
84902 
84903 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register from the beginning of the component. */
84904 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST 0xad4
84905 /* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register. */
84906 #define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST))
84907 
84908 /*
84909  * Register : Register 694 (MAC Address107 High Register) - MAC_Address107_High
84910  *
84911  * The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC
84912  * address of the station. Because the MAC address registers are configured to be
84913  * double-synchronized to the (G)MII clock domains, the synchronization is
84914  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
84915  * endian mode) of the MAC Address107 Low Register are written. For proper
84916  * synchronization updates, the consecutive writes to this Address Low Register
84917  * should be performed after at least four clock cycles in the destination clock
84918  * domain.
84919  *
84920  * Note that all MAC Address High registers (except MAC Address0 High) have the
84921  * same format.
84922  *
84923  * Register Layout
84924  *
84925  * Bits | Access | Reset | Description
84926  * :--------|:-------|:-------|:-----------------------
84927  * [15:0] | RW | 0xffff | MAC Address107 [47:32]
84928  * [23:16] | ??? | 0x0 | *UNDEFINED*
84929  * [24] | RW | 0x0 | Mask Byte Control
84930  * [25] | RW | 0x0 | Mask Byte Control
84931  * [26] | RW | 0x0 | Mask Byte Control
84932  * [27] | RW | 0x0 | Mask Byte Control
84933  * [28] | RW | 0x0 | Mask Byte Control
84934  * [29] | RW | 0x0 | Mask Byte Control
84935  * [30] | RW | 0x0 | Source Address
84936  * [31] | RW | 0x0 | Address Enable
84937  *
84938  */
84939 /*
84940  * Field : MAC Address107 [47:32] - addrhi
84941  *
84942  * This field contains the upper 16 bits (47:32) of the 108th 6-byte MAC address.
84943  *
84944  * Field Access Macros:
84945  *
84946  */
84947 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
84948 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_LSB 0
84949 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
84950 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_MSB 15
84951 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
84952 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_WIDTH 16
84953 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
84954 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET_MSK 0x0000ffff
84955 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
84956 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_CLR_MSK 0xffff0000
84957 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
84958 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_RESET 0xffff
84959 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI field value from a register. */
84960 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
84961 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value suitable for setting the register. */
84962 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
84963 
84964 /*
84965  * Field : Mask Byte Control - mbc_0
84966  *
84967  * This array of bits are mask control bits for comparison of each of the MAC
84968  * Address bytes. When masked, the MAC does not compare the corresponding byte of
84969  * received DA or SA with the contents of MAC Address107 high and low registers.
84970  * Each bit controls the masking of the bytes. You can filter a group of addresses
84971  * (known as group address filtering) by masking one or more bytes of the address.
84972  *
84973  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
84974  *
84975  * Field Enumeration Values:
84976  *
84977  * Enum | Value | Description
84978  * :-----------------------------------------------|:------|:------------------------------------
84979  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
84980  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
84981  *
84982  * Field Access Macros:
84983  *
84984  */
84985 /*
84986  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0
84987  *
84988  * Byte is unmasked (i.e. is compared)
84989  */
84990 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED 0x0
84991 /*
84992  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0
84993  *
84994  * Byte is masked (i.e. not compared)
84995  */
84996 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED 0x1
84997 
84998 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
84999 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_LSB 24
85000 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
85001 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_MSB 24
85002 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
85003 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_WIDTH 1
85004 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */
85005 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET_MSK 0x01000000
85006 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */
85007 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_CLR_MSK 0xfeffffff
85008 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
85009 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_RESET 0x0
85010 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 field value from a register. */
85011 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
85012 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value suitable for setting the register. */
85013 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
85014 
85015 /*
85016  * Field : Mask Byte Control - mbc_1
85017  *
85018  * This array of bits are mask control bits for comparison of each of the MAC
85019  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85020  * received DA or SA with the contents of MAC Address107 high and low registers.
85021  * Each bit controls the masking of the bytes. You can filter a group of addresses
85022  * (known as group address filtering) by masking one or more bytes of the address.
85023  *
85024  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85025  *
85026  * Field Enumeration Values:
85027  *
85028  * Enum | Value | Description
85029  * :-----------------------------------------------|:------|:------------------------------------
85030  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85031  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85032  *
85033  * Field Access Macros:
85034  *
85035  */
85036 /*
85037  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1
85038  *
85039  * Byte is unmasked (i.e. is compared)
85040  */
85041 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED 0x0
85042 /*
85043  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1
85044  *
85045  * Byte is masked (i.e. not compared)
85046  */
85047 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED 0x1
85048 
85049 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
85050 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_LSB 25
85051 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
85052 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_MSB 25
85053 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
85054 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_WIDTH 1
85055 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */
85056 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET_MSK 0x02000000
85057 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */
85058 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_CLR_MSK 0xfdffffff
85059 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
85060 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_RESET 0x0
85061 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 field value from a register. */
85062 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
85063 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value suitable for setting the register. */
85064 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
85065 
85066 /*
85067  * Field : Mask Byte Control - mbc_2
85068  *
85069  * This array of bits are mask control bits for comparison of each of the MAC
85070  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85071  * received DA or SA with the contents of MAC Address107 high and low registers.
85072  * Each bit controls the masking of the bytes. You can filter a group of addresses
85073  * (known as group address filtering) by masking one or more bytes of the address.
85074  *
85075  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85076  *
85077  * Field Enumeration Values:
85078  *
85079  * Enum | Value | Description
85080  * :-----------------------------------------------|:------|:------------------------------------
85081  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85082  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85083  *
85084  * Field Access Macros:
85085  *
85086  */
85087 /*
85088  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2
85089  *
85090  * Byte is unmasked (i.e. is compared)
85091  */
85092 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED 0x0
85093 /*
85094  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2
85095  *
85096  * Byte is masked (i.e. not compared)
85097  */
85098 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED 0x1
85099 
85100 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
85101 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_LSB 26
85102 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
85103 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_MSB 26
85104 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
85105 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_WIDTH 1
85106 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */
85107 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET_MSK 0x04000000
85108 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */
85109 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_CLR_MSK 0xfbffffff
85110 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
85111 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_RESET 0x0
85112 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 field value from a register. */
85113 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
85114 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value suitable for setting the register. */
85115 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
85116 
85117 /*
85118  * Field : Mask Byte Control - mbc_3
85119  *
85120  * This array of bits are mask control bits for comparison of each of the MAC
85121  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85122  * received DA or SA with the contents of MAC Address107 high and low registers.
85123  * Each bit controls the masking of the bytes. You can filter a group of addresses
85124  * (known as group address filtering) by masking one or more bytes of the address.
85125  *
85126  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85127  *
85128  * Field Enumeration Values:
85129  *
85130  * Enum | Value | Description
85131  * :-----------------------------------------------|:------|:------------------------------------
85132  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85133  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85134  *
85135  * Field Access Macros:
85136  *
85137  */
85138 /*
85139  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3
85140  *
85141  * Byte is unmasked (i.e. is compared)
85142  */
85143 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED 0x0
85144 /*
85145  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3
85146  *
85147  * Byte is masked (i.e. not compared)
85148  */
85149 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED 0x1
85150 
85151 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
85152 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_LSB 27
85153 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
85154 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_MSB 27
85155 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
85156 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_WIDTH 1
85157 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */
85158 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET_MSK 0x08000000
85159 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */
85160 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_CLR_MSK 0xf7ffffff
85161 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
85162 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_RESET 0x0
85163 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 field value from a register. */
85164 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
85165 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value suitable for setting the register. */
85166 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
85167 
85168 /*
85169  * Field : Mask Byte Control - mbc_4
85170  *
85171  * This array of bits are mask control bits for comparison of each of the MAC
85172  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85173  * received DA or SA with the contents of MAC Address107 high and low registers.
85174  * Each bit controls the masking of the bytes. You can filter a group of addresses
85175  * (known as group address filtering) by masking one or more bytes of the address.
85176  *
85177  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85178  *
85179  * Field Enumeration Values:
85180  *
85181  * Enum | Value | Description
85182  * :-----------------------------------------------|:------|:------------------------------------
85183  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85184  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85185  *
85186  * Field Access Macros:
85187  *
85188  */
85189 /*
85190  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4
85191  *
85192  * Byte is unmasked (i.e. is compared)
85193  */
85194 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED 0x0
85195 /*
85196  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4
85197  *
85198  * Byte is masked (i.e. not compared)
85199  */
85200 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED 0x1
85201 
85202 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
85203 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_LSB 28
85204 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
85205 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_MSB 28
85206 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
85207 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_WIDTH 1
85208 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */
85209 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET_MSK 0x10000000
85210 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */
85211 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_CLR_MSK 0xefffffff
85212 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
85213 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_RESET 0x0
85214 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 field value from a register. */
85215 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
85216 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value suitable for setting the register. */
85217 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
85218 
85219 /*
85220  * Field : Mask Byte Control - mbc_5
85221  *
85222  * This array of bits are mask control bits for comparison of each of the MAC
85223  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85224  * received DA or SA with the contents of MAC Address107 high and low registers.
85225  * Each bit controls the masking of the bytes. You can filter a group of addresses
85226  * (known as group address filtering) by masking one or more bytes of the address.
85227  *
85228  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85229  *
85230  * Field Enumeration Values:
85231  *
85232  * Enum | Value | Description
85233  * :-----------------------------------------------|:------|:------------------------------------
85234  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85235  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85236  *
85237  * Field Access Macros:
85238  *
85239  */
85240 /*
85241  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5
85242  *
85243  * Byte is unmasked (i.e. is compared)
85244  */
85245 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED 0x0
85246 /*
85247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5
85248  *
85249  * Byte is masked (i.e. not compared)
85250  */
85251 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED 0x1
85252 
85253 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
85254 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_LSB 29
85255 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
85256 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_MSB 29
85257 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
85258 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_WIDTH 1
85259 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */
85260 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET_MSK 0x20000000
85261 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */
85262 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_CLR_MSK 0xdfffffff
85263 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
85264 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_RESET 0x0
85265 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 field value from a register. */
85266 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
85267 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value suitable for setting the register. */
85268 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
85269 
85270 /*
85271  * Field : Source Address - sa
85272  *
85273  * When this bit is enabled, the MAC Address107[47:0] is used to compare with the
85274  * SA fields of the received frame. When this bit is disabled, the MAC
85275  * Address107[47:0] is used to compare with the DA fields of the received frame.
85276  *
85277  * Field Enumeration Values:
85278  *
85279  * Enum | Value | Description
85280  * :-----------------------------------------|:------|:-----------------------------
85281  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
85282  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END | 0x1 | MAC address compare enabled
85283  *
85284  * Field Access Macros:
85285  *
85286  */
85287 /*
85288  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA
85289  *
85290  * MAC address compare disabled
85291  */
85292 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD 0x0
85293 /*
85294  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA
85295  *
85296  * MAC address compare enabled
85297  */
85298 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END 0x1
85299 
85300 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
85301 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_LSB 30
85302 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
85303 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_MSB 30
85304 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
85305 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_WIDTH 1
85306 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */
85307 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET_MSK 0x40000000
85308 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */
85309 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_CLR_MSK 0xbfffffff
85310 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
85311 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_RESET 0x0
85312 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA field value from a register. */
85313 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
85314 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value suitable for setting the register. */
85315 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
85316 
85317 /*
85318  * Field : Address Enable - ae
85319  *
85320  * When this bit is enabled, the address filter block uses the 108th MAC address
85321  * for perfect filtering. When this bit is disabled, the address filter block
85322  * ignores the address for filtering.
85323  *
85324  * Field Enumeration Values:
85325  *
85326  * Enum | Value | Description
85327  * :-----------------------------------------|:------|:--------------------------------------
85328  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
85329  * ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
85330  *
85331  * Field Access Macros:
85332  *
85333  */
85334 /*
85335  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
85336  *
85337  * Second MAC address filtering disabled
85338  */
85339 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD 0x0
85340 /*
85341  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
85342  *
85343  * Second MAC address filtering enabled
85344  */
85345 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END 0x1
85346 
85347 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
85348 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_LSB 31
85349 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
85350 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_MSB 31
85351 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
85352 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_WIDTH 1
85353 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
85354 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET_MSK 0x80000000
85355 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
85356 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_CLR_MSK 0x7fffffff
85357 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
85358 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_RESET 0x0
85359 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE field value from a register. */
85360 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
85361 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value suitable for setting the register. */
85362 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
85363 
85364 #ifndef __ASSEMBLY__
85365 /*
85366  * WARNING: The C register and register group struct declarations are provided for
85367  * convenience and illustrative purposes. They should, however, be used with
85368  * caution as the C language standard provides no guarantees about the alignment or
85369  * atomicity of device memory accesses. The recommended practice for writing
85370  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85371  * alt_write_word() functions.
85372  *
85373  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH.
85374  */
85375 struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s
85376 {
85377  uint32_t addrhi : 16; /* MAC Address107 [47:32] */
85378  uint32_t : 8; /* *UNDEFINED* */
85379  uint32_t mbc_0 : 1; /* Mask Byte Control */
85380  uint32_t mbc_1 : 1; /* Mask Byte Control */
85381  uint32_t mbc_2 : 1; /* Mask Byte Control */
85382  uint32_t mbc_3 : 1; /* Mask Byte Control */
85383  uint32_t mbc_4 : 1; /* Mask Byte Control */
85384  uint32_t mbc_5 : 1; /* Mask Byte Control */
85385  uint32_t sa : 1; /* Source Address */
85386  uint32_t ae : 1; /* Address Enable */
85387 };
85388 
85389 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH. */
85390 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t;
85391 #endif /* __ASSEMBLY__ */
85392 
85393 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register from the beginning of the component. */
85394 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST 0xad8
85395 /* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register. */
85396 #define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST))
85397 
85398 /*
85399  * Register : Register 695 (MAC Address107 Low Register) - MAC_Address107_Low
85400  *
85401  * The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC
85402  * address of the station.
85403  *
85404  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
85405  * format.
85406  *
85407  * Register Layout
85408  *
85409  * Bits | Access | Reset | Description
85410  * :-------|:-------|:-----------|:----------------------
85411  * [31:0] | RW | 0xffffffff | MAC Address107 [31:0]
85412  *
85413  */
85414 /*
85415  * Field : MAC Address107 [31:0] - addrlo
85416  *
85417  * This field contains the lower 32 bits of the 108th 6-byte MAC address. The
85418  * content of this field is undefined until loaded by software after the
85419  * initialization process.
85420  *
85421  * Field Access Macros:
85422  *
85423  */
85424 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
85425 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_LSB 0
85426 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
85427 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_MSB 31
85428 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
85429 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_WIDTH 32
85430 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
85431 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET_MSK 0xffffffff
85432 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
85433 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_CLR_MSK 0x00000000
85434 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
85435 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_RESET 0xffffffff
85436 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO field value from a register. */
85437 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
85438 /* Produces a ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value suitable for setting the register. */
85439 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
85440 
85441 #ifndef __ASSEMBLY__
85442 /*
85443  * WARNING: The C register and register group struct declarations are provided for
85444  * convenience and illustrative purposes. They should, however, be used with
85445  * caution as the C language standard provides no guarantees about the alignment or
85446  * atomicity of device memory accesses. The recommended practice for writing
85447  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85448  * alt_write_word() functions.
85449  *
85450  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW.
85451  */
85452 struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s
85453 {
85454  uint32_t addrlo : 32; /* MAC Address107 [31:0] */
85455 };
85456 
85457 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW. */
85458 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s ALT_EMAC_GMAC_MAC_ADDR107_LOW_t;
85459 #endif /* __ASSEMBLY__ */
85460 
85461 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register from the beginning of the component. */
85462 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST 0xadc
85463 /* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register. */
85464 #define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST))
85465 
85466 /*
85467  * Register : Register 696 (MAC Address108 High Register) - MAC_Address108_High
85468  *
85469  * The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC
85470  * address of the station. Because the MAC address registers are configured to be
85471  * double-synchronized to the (G)MII clock domains, the synchronization is
85472  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
85473  * endian mode) of the MAC Address108 Low Register are written. For proper
85474  * synchronization updates, the consecutive writes to this Address Low Register
85475  * should be performed after at least four clock cycles in the destination clock
85476  * domain.
85477  *
85478  * Note that all MAC Address High registers (except MAC Address0 High) have the
85479  * same format.
85480  *
85481  * Register Layout
85482  *
85483  * Bits | Access | Reset | Description
85484  * :--------|:-------|:-------|:-----------------------
85485  * [15:0] | RW | 0xffff | MAC Address108 [47:32]
85486  * [23:16] | ??? | 0x0 | *UNDEFINED*
85487  * [24] | RW | 0x0 | Mask Byte Control
85488  * [25] | RW | 0x0 | Mask Byte Control
85489  * [26] | RW | 0x0 | Mask Byte Control
85490  * [27] | RW | 0x0 | Mask Byte Control
85491  * [28] | RW | 0x0 | Mask Byte Control
85492  * [29] | RW | 0x0 | Mask Byte Control
85493  * [30] | RW | 0x0 | Source Address
85494  * [31] | RW | 0x0 | Address Enable
85495  *
85496  */
85497 /*
85498  * Field : MAC Address108 [47:32] - addrhi
85499  *
85500  * This field contains the upper 16 bits (47:32) of the 109th 6-byte MAC address.
85501  *
85502  * Field Access Macros:
85503  *
85504  */
85505 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
85506 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_LSB 0
85507 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
85508 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_MSB 15
85509 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
85510 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_WIDTH 16
85511 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
85512 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET_MSK 0x0000ffff
85513 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
85514 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_CLR_MSK 0xffff0000
85515 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
85516 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_RESET 0xffff
85517 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI field value from a register. */
85518 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
85519 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value suitable for setting the register. */
85520 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
85521 
85522 /*
85523  * Field : Mask Byte Control - mbc_0
85524  *
85525  * This array of bits are mask control bits for comparison of each of the MAC
85526  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85527  * received DA or SA with the contents of MAC Address108 high and low registers.
85528  * Each bit controls the masking of the bytes. You can filter a group of addresses
85529  * (known as group address filtering) by masking one or more bytes of the address.
85530  *
85531  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85532  *
85533  * Field Enumeration Values:
85534  *
85535  * Enum | Value | Description
85536  * :-----------------------------------------------|:------|:------------------------------------
85537  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85538  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85539  *
85540  * Field Access Macros:
85541  *
85542  */
85543 /*
85544  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0
85545  *
85546  * Byte is unmasked (i.e. is compared)
85547  */
85548 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED 0x0
85549 /*
85550  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0
85551  *
85552  * Byte is masked (i.e. not compared)
85553  */
85554 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED 0x1
85555 
85556 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
85557 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_LSB 24
85558 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
85559 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_MSB 24
85560 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
85561 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_WIDTH 1
85562 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */
85563 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET_MSK 0x01000000
85564 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */
85565 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_CLR_MSK 0xfeffffff
85566 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
85567 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_RESET 0x0
85568 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 field value from a register. */
85569 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
85570 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value suitable for setting the register. */
85571 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
85572 
85573 /*
85574  * Field : Mask Byte Control - mbc_1
85575  *
85576  * This array of bits are mask control bits for comparison of each of the MAC
85577  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85578  * received DA or SA with the contents of MAC Address108 high and low registers.
85579  * Each bit controls the masking of the bytes. You can filter a group of addresses
85580  * (known as group address filtering) by masking one or more bytes of the address.
85581  *
85582  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85583  *
85584  * Field Enumeration Values:
85585  *
85586  * Enum | Value | Description
85587  * :-----------------------------------------------|:------|:------------------------------------
85588  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85589  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85590  *
85591  * Field Access Macros:
85592  *
85593  */
85594 /*
85595  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1
85596  *
85597  * Byte is unmasked (i.e. is compared)
85598  */
85599 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED 0x0
85600 /*
85601  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1
85602  *
85603  * Byte is masked (i.e. not compared)
85604  */
85605 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED 0x1
85606 
85607 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
85608 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_LSB 25
85609 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
85610 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_MSB 25
85611 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
85612 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_WIDTH 1
85613 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */
85614 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET_MSK 0x02000000
85615 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */
85616 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_CLR_MSK 0xfdffffff
85617 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
85618 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_RESET 0x0
85619 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 field value from a register. */
85620 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
85621 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value suitable for setting the register. */
85622 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
85623 
85624 /*
85625  * Field : Mask Byte Control - mbc_2
85626  *
85627  * This array of bits are mask control bits for comparison of each of the MAC
85628  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85629  * received DA or SA with the contents of MAC Address108 high and low registers.
85630  * Each bit controls the masking of the bytes. You can filter a group of addresses
85631  * (known as group address filtering) by masking one or more bytes of the address.
85632  *
85633  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85634  *
85635  * Field Enumeration Values:
85636  *
85637  * Enum | Value | Description
85638  * :-----------------------------------------------|:------|:------------------------------------
85639  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85640  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85641  *
85642  * Field Access Macros:
85643  *
85644  */
85645 /*
85646  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2
85647  *
85648  * Byte is unmasked (i.e. is compared)
85649  */
85650 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED 0x0
85651 /*
85652  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2
85653  *
85654  * Byte is masked (i.e. not compared)
85655  */
85656 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED 0x1
85657 
85658 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
85659 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_LSB 26
85660 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
85661 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_MSB 26
85662 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
85663 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_WIDTH 1
85664 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */
85665 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET_MSK 0x04000000
85666 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */
85667 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_CLR_MSK 0xfbffffff
85668 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
85669 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_RESET 0x0
85670 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 field value from a register. */
85671 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
85672 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value suitable for setting the register. */
85673 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
85674 
85675 /*
85676  * Field : Mask Byte Control - mbc_3
85677  *
85678  * This array of bits are mask control bits for comparison of each of the MAC
85679  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85680  * received DA or SA with the contents of MAC Address108 high and low registers.
85681  * Each bit controls the masking of the bytes. You can filter a group of addresses
85682  * (known as group address filtering) by masking one or more bytes of the address.
85683  *
85684  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85685  *
85686  * Field Enumeration Values:
85687  *
85688  * Enum | Value | Description
85689  * :-----------------------------------------------|:------|:------------------------------------
85690  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85691  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85692  *
85693  * Field Access Macros:
85694  *
85695  */
85696 /*
85697  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3
85698  *
85699  * Byte is unmasked (i.e. is compared)
85700  */
85701 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED 0x0
85702 /*
85703  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3
85704  *
85705  * Byte is masked (i.e. not compared)
85706  */
85707 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED 0x1
85708 
85709 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
85710 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_LSB 27
85711 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
85712 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_MSB 27
85713 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
85714 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_WIDTH 1
85715 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */
85716 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET_MSK 0x08000000
85717 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */
85718 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_CLR_MSK 0xf7ffffff
85719 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
85720 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_RESET 0x0
85721 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 field value from a register. */
85722 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
85723 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value suitable for setting the register. */
85724 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
85725 
85726 /*
85727  * Field : Mask Byte Control - mbc_4
85728  *
85729  * This array of bits are mask control bits for comparison of each of the MAC
85730  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85731  * received DA or SA with the contents of MAC Address108 high and low registers.
85732  * Each bit controls the masking of the bytes. You can filter a group of addresses
85733  * (known as group address filtering) by masking one or more bytes of the address.
85734  *
85735  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85736  *
85737  * Field Enumeration Values:
85738  *
85739  * Enum | Value | Description
85740  * :-----------------------------------------------|:------|:------------------------------------
85741  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85742  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85743  *
85744  * Field Access Macros:
85745  *
85746  */
85747 /*
85748  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4
85749  *
85750  * Byte is unmasked (i.e. is compared)
85751  */
85752 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED 0x0
85753 /*
85754  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4
85755  *
85756  * Byte is masked (i.e. not compared)
85757  */
85758 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED 0x1
85759 
85760 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
85761 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_LSB 28
85762 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
85763 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_MSB 28
85764 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
85765 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_WIDTH 1
85766 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */
85767 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET_MSK 0x10000000
85768 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */
85769 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_CLR_MSK 0xefffffff
85770 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
85771 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_RESET 0x0
85772 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 field value from a register. */
85773 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
85774 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value suitable for setting the register. */
85775 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
85776 
85777 /*
85778  * Field : Mask Byte Control - mbc_5
85779  *
85780  * This array of bits are mask control bits for comparison of each of the MAC
85781  * Address bytes. When masked, the MAC does not compare the corresponding byte of
85782  * received DA or SA with the contents of MAC Address108 high and low registers.
85783  * Each bit controls the masking of the bytes. You can filter a group of addresses
85784  * (known as group address filtering) by masking one or more bytes of the address.
85785  *
85786  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
85787  *
85788  * Field Enumeration Values:
85789  *
85790  * Enum | Value | Description
85791  * :-----------------------------------------------|:------|:------------------------------------
85792  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
85793  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
85794  *
85795  * Field Access Macros:
85796  *
85797  */
85798 /*
85799  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5
85800  *
85801  * Byte is unmasked (i.e. is compared)
85802  */
85803 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED 0x0
85804 /*
85805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5
85806  *
85807  * Byte is masked (i.e. not compared)
85808  */
85809 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED 0x1
85810 
85811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
85812 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_LSB 29
85813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
85814 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_MSB 29
85815 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
85816 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_WIDTH 1
85817 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */
85818 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET_MSK 0x20000000
85819 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */
85820 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_CLR_MSK 0xdfffffff
85821 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
85822 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_RESET 0x0
85823 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 field value from a register. */
85824 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
85825 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value suitable for setting the register. */
85826 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
85827 
85828 /*
85829  * Field : Source Address - sa
85830  *
85831  * When this bit is enabled, the MAC Address108[47:0] is used to compare with the
85832  * SA fields of the received frame. When this bit is disabled, the MAC
85833  * Address108[47:0] is used to compare with the DA fields of the received frame.
85834  *
85835  * Field Enumeration Values:
85836  *
85837  * Enum | Value | Description
85838  * :-----------------------------------------|:------|:-----------------------------
85839  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
85840  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END | 0x1 | MAC address compare enabled
85841  *
85842  * Field Access Macros:
85843  *
85844  */
85845 /*
85846  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA
85847  *
85848  * MAC address compare disabled
85849  */
85850 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD 0x0
85851 /*
85852  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA
85853  *
85854  * MAC address compare enabled
85855  */
85856 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END 0x1
85857 
85858 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
85859 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_LSB 30
85860 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
85861 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_MSB 30
85862 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
85863 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_WIDTH 1
85864 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */
85865 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET_MSK 0x40000000
85866 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */
85867 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_CLR_MSK 0xbfffffff
85868 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
85869 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_RESET 0x0
85870 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA field value from a register. */
85871 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
85872 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value suitable for setting the register. */
85873 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
85874 
85875 /*
85876  * Field : Address Enable - ae
85877  *
85878  * When this bit is enabled, the address filter block uses the 109th MAC address
85879  * for perfect filtering. When this bit is disabled, the address filter block
85880  * ignores the address for filtering.
85881  *
85882  * Field Enumeration Values:
85883  *
85884  * Enum | Value | Description
85885  * :-----------------------------------------|:------|:--------------------------------------
85886  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
85887  * ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
85888  *
85889  * Field Access Macros:
85890  *
85891  */
85892 /*
85893  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
85894  *
85895  * Second MAC address filtering disabled
85896  */
85897 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD 0x0
85898 /*
85899  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
85900  *
85901  * Second MAC address filtering enabled
85902  */
85903 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END 0x1
85904 
85905 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
85906 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_LSB 31
85907 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
85908 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_MSB 31
85909 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
85910 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_WIDTH 1
85911 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
85912 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET_MSK 0x80000000
85913 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
85914 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_CLR_MSK 0x7fffffff
85915 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
85916 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_RESET 0x0
85917 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE field value from a register. */
85918 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
85919 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value suitable for setting the register. */
85920 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
85921 
85922 #ifndef __ASSEMBLY__
85923 /*
85924  * WARNING: The C register and register group struct declarations are provided for
85925  * convenience and illustrative purposes. They should, however, be used with
85926  * caution as the C language standard provides no guarantees about the alignment or
85927  * atomicity of device memory accesses. The recommended practice for writing
85928  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
85929  * alt_write_word() functions.
85930  *
85931  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH.
85932  */
85933 struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s
85934 {
85935  uint32_t addrhi : 16; /* MAC Address108 [47:32] */
85936  uint32_t : 8; /* *UNDEFINED* */
85937  uint32_t mbc_0 : 1; /* Mask Byte Control */
85938  uint32_t mbc_1 : 1; /* Mask Byte Control */
85939  uint32_t mbc_2 : 1; /* Mask Byte Control */
85940  uint32_t mbc_3 : 1; /* Mask Byte Control */
85941  uint32_t mbc_4 : 1; /* Mask Byte Control */
85942  uint32_t mbc_5 : 1; /* Mask Byte Control */
85943  uint32_t sa : 1; /* Source Address */
85944  uint32_t ae : 1; /* Address Enable */
85945 };
85946 
85947 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH. */
85948 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t;
85949 #endif /* __ASSEMBLY__ */
85950 
85951 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register from the beginning of the component. */
85952 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST 0xae0
85953 /* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register. */
85954 #define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST))
85955 
85956 /*
85957  * Register : Register 697 (MAC Address108 Low Register) - MAC_Address108_Low
85958  *
85959  * The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC
85960  * address of the station.
85961  *
85962  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
85963  * format.
85964  *
85965  * Register Layout
85966  *
85967  * Bits | Access | Reset | Description
85968  * :-------|:-------|:-----------|:----------------------
85969  * [31:0] | RW | 0xffffffff | MAC Address108 [31:0]
85970  *
85971  */
85972 /*
85973  * Field : MAC Address108 [31:0] - addrlo
85974  *
85975  * This field contains the lower 32 bits of the 109th 6-byte MAC address. The
85976  * content of this field is undefined until loaded by software after the
85977  * initialization process.
85978  *
85979  * Field Access Macros:
85980  *
85981  */
85982 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
85983 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_LSB 0
85984 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
85985 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_MSB 31
85986 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
85987 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_WIDTH 32
85988 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
85989 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET_MSK 0xffffffff
85990 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
85991 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_CLR_MSK 0x00000000
85992 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
85993 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_RESET 0xffffffff
85994 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO field value from a register. */
85995 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
85996 /* Produces a ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value suitable for setting the register. */
85997 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
85998 
85999 #ifndef __ASSEMBLY__
86000 /*
86001  * WARNING: The C register and register group struct declarations are provided for
86002  * convenience and illustrative purposes. They should, however, be used with
86003  * caution as the C language standard provides no guarantees about the alignment or
86004  * atomicity of device memory accesses. The recommended practice for writing
86005  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
86006  * alt_write_word() functions.
86007  *
86008  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW.
86009  */
86010 struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s
86011 {
86012  uint32_t addrlo : 32; /* MAC Address108 [31:0] */
86013 };
86014 
86015 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW. */
86016 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s ALT_EMAC_GMAC_MAC_ADDR108_LOW_t;
86017 #endif /* __ASSEMBLY__ */
86018 
86019 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register from the beginning of the component. */
86020 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST 0xae4
86021 /* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register. */
86022 #define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST))
86023 
86024 /*
86025  * Register : Register 698 (MAC Address109 High Register) - MAC_Address109_High
86026  *
86027  * The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC
86028  * address of the station. Because the MAC address registers are configured to be
86029  * double-synchronized to the (G)MII clock domains, the synchronization is
86030  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
86031  * endian mode) of the MAC Address109 Low Register are written. For proper
86032  * synchronization updates, the consecutive writes to this Address Low Register
86033  * should be performed after at least four clock cycles in the destination clock
86034  * domain.
86035  *
86036  * Note that all MAC Address High registers (except MAC Address0 High) have the
86037  * same format.
86038  *
86039  * Register Layout
86040  *
86041  * Bits | Access | Reset | Description
86042  * :--------|:-------|:-------|:-----------------------
86043  * [15:0] | RW | 0xffff | MAC Address109 [47:32]
86044  * [23:16] | ??? | 0x0 | *UNDEFINED*
86045  * [24] | RW | 0x0 | Mask Byte Control
86046  * [25] | RW | 0x0 | Mask Byte Control
86047  * [26] | RW | 0x0 | Mask Byte Control
86048  * [27] | RW | 0x0 | Mask Byte Control
86049  * [28] | RW | 0x0 | Mask Byte Control
86050  * [29] | RW | 0x0 | Mask Byte Control
86051  * [30] | RW | 0x0 | Source Address
86052  * [31] | RW | 0x0 | Address Enable
86053  *
86054  */
86055 /*
86056  * Field : MAC Address109 [47:32] - addrhi
86057  *
86058  * This field contains the upper 16 bits (47:32) of the 110th 6-byte MAC address.
86059  *
86060  * Field Access Macros:
86061  *
86062  */
86063 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
86064 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_LSB 0
86065 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
86066 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_MSB 15
86067 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
86068 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_WIDTH 16
86069 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
86070 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET_MSK 0x0000ffff
86071 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
86072 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_CLR_MSK 0xffff0000
86073 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
86074 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_RESET 0xffff
86075 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI field value from a register. */
86076 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
86077 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value suitable for setting the register. */
86078 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
86079 
86080 /*
86081  * Field : Mask Byte Control - mbc_0
86082  *
86083  * This array of bits are mask control bits for comparison of each of the MAC
86084  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86085  * received DA or SA with the contents of MAC Address109 high and low registers.
86086  * Each bit controls the masking of the bytes. You can filter a group of addresses
86087  * (known as group address filtering) by masking one or more bytes of the address.
86088  *
86089  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86090  *
86091  * Field Enumeration Values:
86092  *
86093  * Enum | Value | Description
86094  * :-----------------------------------------------|:------|:------------------------------------
86095  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86096  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86097  *
86098  * Field Access Macros:
86099  *
86100  */
86101 /*
86102  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0
86103  *
86104  * Byte is unmasked (i.e. is compared)
86105  */
86106 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED 0x0
86107 /*
86108  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0
86109  *
86110  * Byte is masked (i.e. not compared)
86111  */
86112 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED 0x1
86113 
86114 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
86115 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_LSB 24
86116 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
86117 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_MSB 24
86118 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
86119 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_WIDTH 1
86120 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */
86121 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET_MSK 0x01000000
86122 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */
86123 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_CLR_MSK 0xfeffffff
86124 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
86125 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_RESET 0x0
86126 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 field value from a register. */
86127 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
86128 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value suitable for setting the register. */
86129 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
86130 
86131 /*
86132  * Field : Mask Byte Control - mbc_1
86133  *
86134  * This array of bits are mask control bits for comparison of each of the MAC
86135  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86136  * received DA or SA with the contents of MAC Address109 high and low registers.
86137  * Each bit controls the masking of the bytes. You can filter a group of addresses
86138  * (known as group address filtering) by masking one or more bytes of the address.
86139  *
86140  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86141  *
86142  * Field Enumeration Values:
86143  *
86144  * Enum | Value | Description
86145  * :-----------------------------------------------|:------|:------------------------------------
86146  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86147  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86148  *
86149  * Field Access Macros:
86150  *
86151  */
86152 /*
86153  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1
86154  *
86155  * Byte is unmasked (i.e. is compared)
86156  */
86157 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED 0x0
86158 /*
86159  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1
86160  *
86161  * Byte is masked (i.e. not compared)
86162  */
86163 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED 0x1
86164 
86165 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
86166 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_LSB 25
86167 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
86168 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_MSB 25
86169 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
86170 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_WIDTH 1
86171 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */
86172 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET_MSK 0x02000000
86173 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */
86174 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_CLR_MSK 0xfdffffff
86175 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
86176 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_RESET 0x0
86177 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 field value from a register. */
86178 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
86179 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value suitable for setting the register. */
86180 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
86181 
86182 /*
86183  * Field : Mask Byte Control - mbc_2
86184  *
86185  * This array of bits are mask control bits for comparison of each of the MAC
86186  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86187  * received DA or SA with the contents of MAC Address109 high and low registers.
86188  * Each bit controls the masking of the bytes. You can filter a group of addresses
86189  * (known as group address filtering) by masking one or more bytes of the address.
86190  *
86191  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86192  *
86193  * Field Enumeration Values:
86194  *
86195  * Enum | Value | Description
86196  * :-----------------------------------------------|:------|:------------------------------------
86197  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86198  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86199  *
86200  * Field Access Macros:
86201  *
86202  */
86203 /*
86204  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2
86205  *
86206  * Byte is unmasked (i.e. is compared)
86207  */
86208 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED 0x0
86209 /*
86210  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2
86211  *
86212  * Byte is masked (i.e. not compared)
86213  */
86214 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED 0x1
86215 
86216 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
86217 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_LSB 26
86218 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
86219 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_MSB 26
86220 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
86221 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_WIDTH 1
86222 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */
86223 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET_MSK 0x04000000
86224 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */
86225 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_CLR_MSK 0xfbffffff
86226 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
86227 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_RESET 0x0
86228 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 field value from a register. */
86229 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
86230 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value suitable for setting the register. */
86231 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
86232 
86233 /*
86234  * Field : Mask Byte Control - mbc_3
86235  *
86236  * This array of bits are mask control bits for comparison of each of the MAC
86237  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86238  * received DA or SA with the contents of MAC Address109 high and low registers.
86239  * Each bit controls the masking of the bytes. You can filter a group of addresses
86240  * (known as group address filtering) by masking one or more bytes of the address.
86241  *
86242  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86243  *
86244  * Field Enumeration Values:
86245  *
86246  * Enum | Value | Description
86247  * :-----------------------------------------------|:------|:------------------------------------
86248  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86249  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86250  *
86251  * Field Access Macros:
86252  *
86253  */
86254 /*
86255  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3
86256  *
86257  * Byte is unmasked (i.e. is compared)
86258  */
86259 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED 0x0
86260 /*
86261  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3
86262  *
86263  * Byte is masked (i.e. not compared)
86264  */
86265 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED 0x1
86266 
86267 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
86268 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_LSB 27
86269 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
86270 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_MSB 27
86271 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
86272 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_WIDTH 1
86273 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */
86274 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET_MSK 0x08000000
86275 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */
86276 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_CLR_MSK 0xf7ffffff
86277 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
86278 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_RESET 0x0
86279 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 field value from a register. */
86280 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
86281 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value suitable for setting the register. */
86282 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
86283 
86284 /*
86285  * Field : Mask Byte Control - mbc_4
86286  *
86287  * This array of bits are mask control bits for comparison of each of the MAC
86288  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86289  * received DA or SA with the contents of MAC Address109 high and low registers.
86290  * Each bit controls the masking of the bytes. You can filter a group of addresses
86291  * (known as group address filtering) by masking one or more bytes of the address.
86292  *
86293  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86294  *
86295  * Field Enumeration Values:
86296  *
86297  * Enum | Value | Description
86298  * :-----------------------------------------------|:------|:------------------------------------
86299  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86300  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86301  *
86302  * Field Access Macros:
86303  *
86304  */
86305 /*
86306  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4
86307  *
86308  * Byte is unmasked (i.e. is compared)
86309  */
86310 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED 0x0
86311 /*
86312  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4
86313  *
86314  * Byte is masked (i.e. not compared)
86315  */
86316 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED 0x1
86317 
86318 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
86319 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_LSB 28
86320 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
86321 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_MSB 28
86322 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
86323 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_WIDTH 1
86324 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */
86325 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET_MSK 0x10000000
86326 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */
86327 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_CLR_MSK 0xefffffff
86328 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
86329 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_RESET 0x0
86330 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 field value from a register. */
86331 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
86332 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value suitable for setting the register. */
86333 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
86334 
86335 /*
86336  * Field : Mask Byte Control - mbc_5
86337  *
86338  * This array of bits are mask control bits for comparison of each of the MAC
86339  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86340  * received DA or SA with the contents of MAC Address109 high and low registers.
86341  * Each bit controls the masking of the bytes. You can filter a group of addresses
86342  * (known as group address filtering) by masking one or more bytes of the address.
86343  *
86344  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86345  *
86346  * Field Enumeration Values:
86347  *
86348  * Enum | Value | Description
86349  * :-----------------------------------------------|:------|:------------------------------------
86350  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86351  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86352  *
86353  * Field Access Macros:
86354  *
86355  */
86356 /*
86357  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5
86358  *
86359  * Byte is unmasked (i.e. is compared)
86360  */
86361 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED 0x0
86362 /*
86363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5
86364  *
86365  * Byte is masked (i.e. not compared)
86366  */
86367 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED 0x1
86368 
86369 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
86370 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_LSB 29
86371 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
86372 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_MSB 29
86373 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
86374 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_WIDTH 1
86375 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */
86376 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET_MSK 0x20000000
86377 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */
86378 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_CLR_MSK 0xdfffffff
86379 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
86380 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_RESET 0x0
86381 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 field value from a register. */
86382 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
86383 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value suitable for setting the register. */
86384 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
86385 
86386 /*
86387  * Field : Source Address - sa
86388  *
86389  * When this bit is enabled, the MAC Address109[47:0] is used to compare with the
86390  * SA fields of the received frame. When this bit is disabled, the MAC
86391  * Address109[47:0] is used to compare with the DA fields of the received frame.
86392  *
86393  * Field Enumeration Values:
86394  *
86395  * Enum | Value | Description
86396  * :-----------------------------------------|:------|:-----------------------------
86397  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
86398  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END | 0x1 | MAC address compare enabled
86399  *
86400  * Field Access Macros:
86401  *
86402  */
86403 /*
86404  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA
86405  *
86406  * MAC address compare disabled
86407  */
86408 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD 0x0
86409 /*
86410  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA
86411  *
86412  * MAC address compare enabled
86413  */
86414 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END 0x1
86415 
86416 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
86417 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_LSB 30
86418 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
86419 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_MSB 30
86420 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
86421 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_WIDTH 1
86422 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */
86423 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET_MSK 0x40000000
86424 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */
86425 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_CLR_MSK 0xbfffffff
86426 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
86427 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_RESET 0x0
86428 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA field value from a register. */
86429 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
86430 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value suitable for setting the register. */
86431 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
86432 
86433 /*
86434  * Field : Address Enable - ae
86435  *
86436  * When this bit is enabled, the address filter block uses the 110th MAC address
86437  * for perfect filtering. When this bit is disabled, the address filter block
86438  * ignores the address for filtering.
86439  *
86440  * Field Enumeration Values:
86441  *
86442  * Enum | Value | Description
86443  * :-----------------------------------------|:------|:--------------------------------------
86444  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
86445  * ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
86446  *
86447  * Field Access Macros:
86448  *
86449  */
86450 /*
86451  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
86452  *
86453  * Second MAC address filtering disabled
86454  */
86455 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD 0x0
86456 /*
86457  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
86458  *
86459  * Second MAC address filtering enabled
86460  */
86461 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END 0x1
86462 
86463 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
86464 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_LSB 31
86465 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
86466 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_MSB 31
86467 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
86468 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_WIDTH 1
86469 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
86470 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET_MSK 0x80000000
86471 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
86472 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_CLR_MSK 0x7fffffff
86473 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
86474 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_RESET 0x0
86475 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE field value from a register. */
86476 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
86477 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value suitable for setting the register. */
86478 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
86479 
86480 #ifndef __ASSEMBLY__
86481 /*
86482  * WARNING: The C register and register group struct declarations are provided for
86483  * convenience and illustrative purposes. They should, however, be used with
86484  * caution as the C language standard provides no guarantees about the alignment or
86485  * atomicity of device memory accesses. The recommended practice for writing
86486  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
86487  * alt_write_word() functions.
86488  *
86489  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH.
86490  */
86491 struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s
86492 {
86493  uint32_t addrhi : 16; /* MAC Address109 [47:32] */
86494  uint32_t : 8; /* *UNDEFINED* */
86495  uint32_t mbc_0 : 1; /* Mask Byte Control */
86496  uint32_t mbc_1 : 1; /* Mask Byte Control */
86497  uint32_t mbc_2 : 1; /* Mask Byte Control */
86498  uint32_t mbc_3 : 1; /* Mask Byte Control */
86499  uint32_t mbc_4 : 1; /* Mask Byte Control */
86500  uint32_t mbc_5 : 1; /* Mask Byte Control */
86501  uint32_t sa : 1; /* Source Address */
86502  uint32_t ae : 1; /* Address Enable */
86503 };
86504 
86505 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH. */
86506 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t;
86507 #endif /* __ASSEMBLY__ */
86508 
86509 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register from the beginning of the component. */
86510 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST 0xae8
86511 /* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register. */
86512 #define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST))
86513 
86514 /*
86515  * Register : Register 699 (MAC Address109 Low Register) - MAC_Address109_Low
86516  *
86517  * The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC
86518  * address of the station.
86519  *
86520  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
86521  * format.
86522  *
86523  * Register Layout
86524  *
86525  * Bits | Access | Reset | Description
86526  * :-------|:-------|:-----------|:----------------------
86527  * [31:0] | RW | 0xffffffff | MAC Address109 [31:0]
86528  *
86529  */
86530 /*
86531  * Field : MAC Address109 [31:0] - addrlo
86532  *
86533  * This field contains the lower 32 bits of the 110th 6-byte MAC address. The
86534  * content of this field is undefined until loaded by software after the
86535  * initialization process.
86536  *
86537  * Field Access Macros:
86538  *
86539  */
86540 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
86541 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_LSB 0
86542 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
86543 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_MSB 31
86544 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
86545 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_WIDTH 32
86546 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
86547 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET_MSK 0xffffffff
86548 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
86549 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_CLR_MSK 0x00000000
86550 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
86551 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_RESET 0xffffffff
86552 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO field value from a register. */
86553 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
86554 /* Produces a ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value suitable for setting the register. */
86555 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
86556 
86557 #ifndef __ASSEMBLY__
86558 /*
86559  * WARNING: The C register and register group struct declarations are provided for
86560  * convenience and illustrative purposes. They should, however, be used with
86561  * caution as the C language standard provides no guarantees about the alignment or
86562  * atomicity of device memory accesses. The recommended practice for writing
86563  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
86564  * alt_write_word() functions.
86565  *
86566  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW.
86567  */
86568 struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s
86569 {
86570  uint32_t addrlo : 32; /* MAC Address109 [31:0] */
86571 };
86572 
86573 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW. */
86574 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s ALT_EMAC_GMAC_MAC_ADDR109_LOW_t;
86575 #endif /* __ASSEMBLY__ */
86576 
86577 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register from the beginning of the component. */
86578 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST 0xaec
86579 /* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register. */
86580 #define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST))
86581 
86582 /*
86583  * Register : Register 700 (MAC Address110 High Register) - MAC_Address110_High
86584  *
86585  * The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC
86586  * address of the station. Because the MAC address registers are configured to be
86587  * double-synchronized to the (G)MII clock domains, the synchronization is
86588  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
86589  * endian mode) of the MAC Address110 Low Register are written. For proper
86590  * synchronization updates, the consecutive writes to this Address Low Register
86591  * should be performed after at least four clock cycles in the destination clock
86592  * domain.
86593  *
86594  * Note that all MAC Address High registers (except MAC Address0 High) have the
86595  * same format.
86596  *
86597  * Register Layout
86598  *
86599  * Bits | Access | Reset | Description
86600  * :--------|:-------|:-------|:-----------------------
86601  * [15:0] | RW | 0xffff | MAC Address110 [47:32]
86602  * [23:16] | ??? | 0x0 | *UNDEFINED*
86603  * [24] | RW | 0x0 | Mask Byte Control
86604  * [25] | RW | 0x0 | Mask Byte Control
86605  * [26] | RW | 0x0 | Mask Byte Control
86606  * [27] | RW | 0x0 | Mask Byte Control
86607  * [28] | RW | 0x0 | Mask Byte Control
86608  * [29] | RW | 0x0 | Mask Byte Control
86609  * [30] | RW | 0x0 | Source Address
86610  * [31] | RW | 0x0 | Address Enable
86611  *
86612  */
86613 /*
86614  * Field : MAC Address110 [47:32] - addrhi
86615  *
86616  * This field contains the upper 16 bits (47:32) of the 111th 6-byte MAC address.
86617  *
86618  * Field Access Macros:
86619  *
86620  */
86621 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
86622 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_LSB 0
86623 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
86624 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_MSB 15
86625 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
86626 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_WIDTH 16
86627 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
86628 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET_MSK 0x0000ffff
86629 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
86630 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_CLR_MSK 0xffff0000
86631 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
86632 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_RESET 0xffff
86633 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI field value from a register. */
86634 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
86635 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value suitable for setting the register. */
86636 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
86637 
86638 /*
86639  * Field : Mask Byte Control - mbc_0
86640  *
86641  * This array of bits are mask control bits for comparison of each of the MAC
86642  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86643  * received DA or SA with the contents of MAC Address110 high and low registers.
86644  * Each bit controls the masking of the bytes. You can filter a group of addresses
86645  * (known as group address filtering) by masking one or more bytes of the address.
86646  *
86647  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86648  *
86649  * Field Enumeration Values:
86650  *
86651  * Enum | Value | Description
86652  * :-----------------------------------------------|:------|:------------------------------------
86653  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86654  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86655  *
86656  * Field Access Macros:
86657  *
86658  */
86659 /*
86660  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0
86661  *
86662  * Byte is unmasked (i.e. is compared)
86663  */
86664 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED 0x0
86665 /*
86666  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0
86667  *
86668  * Byte is masked (i.e. not compared)
86669  */
86670 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED 0x1
86671 
86672 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
86673 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_LSB 24
86674 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
86675 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_MSB 24
86676 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
86677 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_WIDTH 1
86678 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */
86679 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET_MSK 0x01000000
86680 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */
86681 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_CLR_MSK 0xfeffffff
86682 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
86683 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_RESET 0x0
86684 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 field value from a register. */
86685 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
86686 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value suitable for setting the register. */
86687 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
86688 
86689 /*
86690  * Field : Mask Byte Control - mbc_1
86691  *
86692  * This array of bits are mask control bits for comparison of each of the MAC
86693  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86694  * received DA or SA with the contents of MAC Address110 high and low registers.
86695  * Each bit controls the masking of the bytes. You can filter a group of addresses
86696  * (known as group address filtering) by masking one or more bytes of the address.
86697  *
86698  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86699  *
86700  * Field Enumeration Values:
86701  *
86702  * Enum | Value | Description
86703  * :-----------------------------------------------|:------|:------------------------------------
86704  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86705  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86706  *
86707  * Field Access Macros:
86708  *
86709  */
86710 /*
86711  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1
86712  *
86713  * Byte is unmasked (i.e. is compared)
86714  */
86715 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED 0x0
86716 /*
86717  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1
86718  *
86719  * Byte is masked (i.e. not compared)
86720  */
86721 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED 0x1
86722 
86723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
86724 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_LSB 25
86725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
86726 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_MSB 25
86727 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
86728 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_WIDTH 1
86729 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */
86730 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET_MSK 0x02000000
86731 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */
86732 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_CLR_MSK 0xfdffffff
86733 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
86734 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_RESET 0x0
86735 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 field value from a register. */
86736 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
86737 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value suitable for setting the register. */
86738 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
86739 
86740 /*
86741  * Field : Mask Byte Control - mbc_2
86742  *
86743  * This array of bits are mask control bits for comparison of each of the MAC
86744  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86745  * received DA or SA with the contents of MAC Address110 high and low registers.
86746  * Each bit controls the masking of the bytes. You can filter a group of addresses
86747  * (known as group address filtering) by masking one or more bytes of the address.
86748  *
86749  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86750  *
86751  * Field Enumeration Values:
86752  *
86753  * Enum | Value | Description
86754  * :-----------------------------------------------|:------|:------------------------------------
86755  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86756  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86757  *
86758  * Field Access Macros:
86759  *
86760  */
86761 /*
86762  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2
86763  *
86764  * Byte is unmasked (i.e. is compared)
86765  */
86766 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED 0x0
86767 /*
86768  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2
86769  *
86770  * Byte is masked (i.e. not compared)
86771  */
86772 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED 0x1
86773 
86774 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
86775 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_LSB 26
86776 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
86777 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_MSB 26
86778 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
86779 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_WIDTH 1
86780 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */
86781 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET_MSK 0x04000000
86782 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */
86783 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_CLR_MSK 0xfbffffff
86784 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
86785 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_RESET 0x0
86786 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 field value from a register. */
86787 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
86788 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value suitable for setting the register. */
86789 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
86790 
86791 /*
86792  * Field : Mask Byte Control - mbc_3
86793  *
86794  * This array of bits are mask control bits for comparison of each of the MAC
86795  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86796  * received DA or SA with the contents of MAC Address110 high and low registers.
86797  * Each bit controls the masking of the bytes. You can filter a group of addresses
86798  * (known as group address filtering) by masking one or more bytes of the address.
86799  *
86800  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86801  *
86802  * Field Enumeration Values:
86803  *
86804  * Enum | Value | Description
86805  * :-----------------------------------------------|:------|:------------------------------------
86806  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86807  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86808  *
86809  * Field Access Macros:
86810  *
86811  */
86812 /*
86813  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3
86814  *
86815  * Byte is unmasked (i.e. is compared)
86816  */
86817 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED 0x0
86818 /*
86819  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3
86820  *
86821  * Byte is masked (i.e. not compared)
86822  */
86823 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED 0x1
86824 
86825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
86826 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_LSB 27
86827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
86828 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_MSB 27
86829 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
86830 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_WIDTH 1
86831 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */
86832 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET_MSK 0x08000000
86833 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */
86834 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_CLR_MSK 0xf7ffffff
86835 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
86836 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_RESET 0x0
86837 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 field value from a register. */
86838 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
86839 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value suitable for setting the register. */
86840 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
86841 
86842 /*
86843  * Field : Mask Byte Control - mbc_4
86844  *
86845  * This array of bits are mask control bits for comparison of each of the MAC
86846  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86847  * received DA or SA with the contents of MAC Address110 high and low registers.
86848  * Each bit controls the masking of the bytes. You can filter a group of addresses
86849  * (known as group address filtering) by masking one or more bytes of the address.
86850  *
86851  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86852  *
86853  * Field Enumeration Values:
86854  *
86855  * Enum | Value | Description
86856  * :-----------------------------------------------|:------|:------------------------------------
86857  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86858  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86859  *
86860  * Field Access Macros:
86861  *
86862  */
86863 /*
86864  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4
86865  *
86866  * Byte is unmasked (i.e. is compared)
86867  */
86868 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED 0x0
86869 /*
86870  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4
86871  *
86872  * Byte is masked (i.e. not compared)
86873  */
86874 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED 0x1
86875 
86876 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
86877 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_LSB 28
86878 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
86879 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_MSB 28
86880 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
86881 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_WIDTH 1
86882 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */
86883 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET_MSK 0x10000000
86884 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */
86885 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_CLR_MSK 0xefffffff
86886 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
86887 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_RESET 0x0
86888 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 field value from a register. */
86889 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
86890 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value suitable for setting the register. */
86891 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
86892 
86893 /*
86894  * Field : Mask Byte Control - mbc_5
86895  *
86896  * This array of bits are mask control bits for comparison of each of the MAC
86897  * Address bytes. When masked, the MAC does not compare the corresponding byte of
86898  * received DA or SA with the contents of MAC Address110 high and low registers.
86899  * Each bit controls the masking of the bytes. You can filter a group of addresses
86900  * (known as group address filtering) by masking one or more bytes of the address.
86901  *
86902  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
86903  *
86904  * Field Enumeration Values:
86905  *
86906  * Enum | Value | Description
86907  * :-----------------------------------------------|:------|:------------------------------------
86908  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
86909  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
86910  *
86911  * Field Access Macros:
86912  *
86913  */
86914 /*
86915  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5
86916  *
86917  * Byte is unmasked (i.e. is compared)
86918  */
86919 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED 0x0
86920 /*
86921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5
86922  *
86923  * Byte is masked (i.e. not compared)
86924  */
86925 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED 0x1
86926 
86927 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
86928 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_LSB 29
86929 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
86930 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_MSB 29
86931 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
86932 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_WIDTH 1
86933 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */
86934 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET_MSK 0x20000000
86935 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */
86936 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_CLR_MSK 0xdfffffff
86937 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
86938 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_RESET 0x0
86939 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 field value from a register. */
86940 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
86941 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value suitable for setting the register. */
86942 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
86943 
86944 /*
86945  * Field : Source Address - sa
86946  *
86947  * When this bit is enabled, the MAC Address110[47:0] is used to compare with the
86948  * SA fields of the received frame. When this bit is disabled, the MAC
86949  * Address110[47:0] is used to compare with the DA fields of the received frame.
86950  *
86951  * Field Enumeration Values:
86952  *
86953  * Enum | Value | Description
86954  * :-----------------------------------------|:------|:-----------------------------
86955  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
86956  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END | 0x1 | MAC address compare enabled
86957  *
86958  * Field Access Macros:
86959  *
86960  */
86961 /*
86962  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA
86963  *
86964  * MAC address compare disabled
86965  */
86966 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD 0x0
86967 /*
86968  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA
86969  *
86970  * MAC address compare enabled
86971  */
86972 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END 0x1
86973 
86974 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
86975 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_LSB 30
86976 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
86977 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_MSB 30
86978 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
86979 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_WIDTH 1
86980 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */
86981 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET_MSK 0x40000000
86982 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */
86983 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_CLR_MSK 0xbfffffff
86984 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
86985 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_RESET 0x0
86986 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA field value from a register. */
86987 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
86988 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value suitable for setting the register. */
86989 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
86990 
86991 /*
86992  * Field : Address Enable - ae
86993  *
86994  * When this bit is enabled, the address filter block uses the 111th MAC address
86995  * for perfect filtering. When this bit is disabled, the address filter block
86996  * ignores the address for filtering.
86997  *
86998  * Field Enumeration Values:
86999  *
87000  * Enum | Value | Description
87001  * :-----------------------------------------|:------|:--------------------------------------
87002  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
87003  * ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
87004  *
87005  * Field Access Macros:
87006  *
87007  */
87008 /*
87009  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
87010  *
87011  * Second MAC address filtering disabled
87012  */
87013 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD 0x0
87014 /*
87015  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
87016  *
87017  * Second MAC address filtering enabled
87018  */
87019 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END 0x1
87020 
87021 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
87022 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_LSB 31
87023 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
87024 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_MSB 31
87025 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
87026 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_WIDTH 1
87027 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
87028 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET_MSK 0x80000000
87029 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
87030 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_CLR_MSK 0x7fffffff
87031 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
87032 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_RESET 0x0
87033 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE field value from a register. */
87034 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
87035 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value suitable for setting the register. */
87036 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
87037 
87038 #ifndef __ASSEMBLY__
87039 /*
87040  * WARNING: The C register and register group struct declarations are provided for
87041  * convenience and illustrative purposes. They should, however, be used with
87042  * caution as the C language standard provides no guarantees about the alignment or
87043  * atomicity of device memory accesses. The recommended practice for writing
87044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87045  * alt_write_word() functions.
87046  *
87047  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH.
87048  */
87049 struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s
87050 {
87051  uint32_t addrhi : 16; /* MAC Address110 [47:32] */
87052  uint32_t : 8; /* *UNDEFINED* */
87053  uint32_t mbc_0 : 1; /* Mask Byte Control */
87054  uint32_t mbc_1 : 1; /* Mask Byte Control */
87055  uint32_t mbc_2 : 1; /* Mask Byte Control */
87056  uint32_t mbc_3 : 1; /* Mask Byte Control */
87057  uint32_t mbc_4 : 1; /* Mask Byte Control */
87058  uint32_t mbc_5 : 1; /* Mask Byte Control */
87059  uint32_t sa : 1; /* Source Address */
87060  uint32_t ae : 1; /* Address Enable */
87061 };
87062 
87063 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH. */
87064 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t;
87065 #endif /* __ASSEMBLY__ */
87066 
87067 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register from the beginning of the component. */
87068 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST 0xaf0
87069 /* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register. */
87070 #define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST))
87071 
87072 /*
87073  * Register : Register 701 (MAC Address110 Low Register) - MAC_Address110_Low
87074  *
87075  * The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC
87076  * address of the station.
87077  *
87078  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
87079  * format.
87080  *
87081  * Register Layout
87082  *
87083  * Bits | Access | Reset | Description
87084  * :-------|:-------|:-----------|:----------------------
87085  * [31:0] | RW | 0xffffffff | MAC Address110 [31:0]
87086  *
87087  */
87088 /*
87089  * Field : MAC Address110 [31:0] - addrlo
87090  *
87091  * This field contains the lower 32 bits of the 111th 6-byte MAC address. The
87092  * content of this field is undefined until loaded by software after the
87093  * initialization process.
87094  *
87095  * Field Access Macros:
87096  *
87097  */
87098 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
87099 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_LSB 0
87100 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
87101 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_MSB 31
87102 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
87103 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_WIDTH 32
87104 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
87105 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET_MSK 0xffffffff
87106 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
87107 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_CLR_MSK 0x00000000
87108 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
87109 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_RESET 0xffffffff
87110 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO field value from a register. */
87111 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
87112 /* Produces a ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value suitable for setting the register. */
87113 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
87114 
87115 #ifndef __ASSEMBLY__
87116 /*
87117  * WARNING: The C register and register group struct declarations are provided for
87118  * convenience and illustrative purposes. They should, however, be used with
87119  * caution as the C language standard provides no guarantees about the alignment or
87120  * atomicity of device memory accesses. The recommended practice for writing
87121  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87122  * alt_write_word() functions.
87123  *
87124  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW.
87125  */
87126 struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s
87127 {
87128  uint32_t addrlo : 32; /* MAC Address110 [31:0] */
87129 };
87130 
87131 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW. */
87132 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s ALT_EMAC_GMAC_MAC_ADDR110_LOW_t;
87133 #endif /* __ASSEMBLY__ */
87134 
87135 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register from the beginning of the component. */
87136 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST 0xaf4
87137 /* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register. */
87138 #define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST))
87139 
87140 /*
87141  * Register : Register 702 (MAC Address111 High Register) - MAC_Address111_High
87142  *
87143  * The MAC Address111 High register holds the upper 16 bits of the 112th 6-byte MAC
87144  * address of the station. Because the MAC address registers are configured to be
87145  * double-synchronized to the (G)MII clock domains, the synchronization is
87146  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
87147  * endian mode) of the MAC Address111 Low Register are written. For proper
87148  * synchronization updates, the consecutive writes to this Address Low Register
87149  * should be performed after at least four clock cycles in the destination clock
87150  * domain.
87151  *
87152  * Note that all MAC Address High registers (except MAC Address0 High) have the
87153  * same format.
87154  *
87155  * Register Layout
87156  *
87157  * Bits | Access | Reset | Description
87158  * :--------|:-------|:-------|:-----------------------
87159  * [15:0] | RW | 0xffff | MAC Address111 [47:32]
87160  * [23:16] | ??? | 0x0 | *UNDEFINED*
87161  * [24] | RW | 0x0 | Mask Byte Control
87162  * [25] | RW | 0x0 | Mask Byte Control
87163  * [26] | RW | 0x0 | Mask Byte Control
87164  * [27] | RW | 0x0 | Mask Byte Control
87165  * [28] | RW | 0x0 | Mask Byte Control
87166  * [29] | RW | 0x0 | Mask Byte Control
87167  * [30] | RW | 0x0 | Source Address
87168  * [31] | RW | 0x0 | Address Enable
87169  *
87170  */
87171 /*
87172  * Field : MAC Address111 [47:32] - addrhi
87173  *
87174  * This field contains the upper 16 bits (47:32) of the 112th 6-byte MAC address.
87175  *
87176  * Field Access Macros:
87177  *
87178  */
87179 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
87180 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_LSB 0
87181 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
87182 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_MSB 15
87183 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
87184 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_WIDTH 16
87185 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
87186 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET_MSK 0x0000ffff
87187 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
87188 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_CLR_MSK 0xffff0000
87189 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
87190 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_RESET 0xffff
87191 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI field value from a register. */
87192 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
87193 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value suitable for setting the register. */
87194 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
87195 
87196 /*
87197  * Field : Mask Byte Control - mbc_0
87198  *
87199  * This array of bits are mask control bits for comparison of each of the MAC
87200  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87201  * received DA or SA with the contents of MAC Address111 high and low registers.
87202  * Each bit controls the masking of the bytes. You can filter a group of addresses
87203  * (known as group address filtering) by masking one or more bytes of the address.
87204  *
87205  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87206  *
87207  * Field Enumeration Values:
87208  *
87209  * Enum | Value | Description
87210  * :-----------------------------------------------|:------|:------------------------------------
87211  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87212  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87213  *
87214  * Field Access Macros:
87215  *
87216  */
87217 /*
87218  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0
87219  *
87220  * Byte is unmasked (i.e. is compared)
87221  */
87222 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED 0x0
87223 /*
87224  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0
87225  *
87226  * Byte is masked (i.e. not compared)
87227  */
87228 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED 0x1
87229 
87230 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
87231 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_LSB 24
87232 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
87233 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_MSB 24
87234 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
87235 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_WIDTH 1
87236 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */
87237 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET_MSK 0x01000000
87238 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */
87239 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_CLR_MSK 0xfeffffff
87240 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
87241 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_RESET 0x0
87242 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 field value from a register. */
87243 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
87244 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value suitable for setting the register. */
87245 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
87246 
87247 /*
87248  * Field : Mask Byte Control - mbc_1
87249  *
87250  * This array of bits are mask control bits for comparison of each of the MAC
87251  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87252  * received DA or SA with the contents of MAC Address111 high and low registers.
87253  * Each bit controls the masking of the bytes. You can filter a group of addresses
87254  * (known as group address filtering) by masking one or more bytes of the address.
87255  *
87256  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87257  *
87258  * Field Enumeration Values:
87259  *
87260  * Enum | Value | Description
87261  * :-----------------------------------------------|:------|:------------------------------------
87262  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87263  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87264  *
87265  * Field Access Macros:
87266  *
87267  */
87268 /*
87269  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1
87270  *
87271  * Byte is unmasked (i.e. is compared)
87272  */
87273 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED 0x0
87274 /*
87275  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1
87276  *
87277  * Byte is masked (i.e. not compared)
87278  */
87279 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED 0x1
87280 
87281 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
87282 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_LSB 25
87283 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
87284 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_MSB 25
87285 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
87286 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_WIDTH 1
87287 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */
87288 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET_MSK 0x02000000
87289 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */
87290 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_CLR_MSK 0xfdffffff
87291 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
87292 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_RESET 0x0
87293 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 field value from a register. */
87294 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
87295 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value suitable for setting the register. */
87296 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
87297 
87298 /*
87299  * Field : Mask Byte Control - mbc_2
87300  *
87301  * This array of bits are mask control bits for comparison of each of the MAC
87302  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87303  * received DA or SA with the contents of MAC Address111 high and low registers.
87304  * Each bit controls the masking of the bytes. You can filter a group of addresses
87305  * (known as group address filtering) by masking one or more bytes of the address.
87306  *
87307  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87308  *
87309  * Field Enumeration Values:
87310  *
87311  * Enum | Value | Description
87312  * :-----------------------------------------------|:------|:------------------------------------
87313  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87314  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87315  *
87316  * Field Access Macros:
87317  *
87318  */
87319 /*
87320  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2
87321  *
87322  * Byte is unmasked (i.e. is compared)
87323  */
87324 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED 0x0
87325 /*
87326  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2
87327  *
87328  * Byte is masked (i.e. not compared)
87329  */
87330 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED 0x1
87331 
87332 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
87333 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_LSB 26
87334 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
87335 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_MSB 26
87336 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
87337 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_WIDTH 1
87338 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */
87339 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET_MSK 0x04000000
87340 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */
87341 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_CLR_MSK 0xfbffffff
87342 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
87343 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_RESET 0x0
87344 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 field value from a register. */
87345 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
87346 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value suitable for setting the register. */
87347 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
87348 
87349 /*
87350  * Field : Mask Byte Control - mbc_3
87351  *
87352  * This array of bits are mask control bits for comparison of each of the MAC
87353  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87354  * received DA or SA with the contents of MAC Address111 high and low registers.
87355  * Each bit controls the masking of the bytes. You can filter a group of addresses
87356  * (known as group address filtering) by masking one or more bytes of the address.
87357  *
87358  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87359  *
87360  * Field Enumeration Values:
87361  *
87362  * Enum | Value | Description
87363  * :-----------------------------------------------|:------|:------------------------------------
87364  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87365  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87366  *
87367  * Field Access Macros:
87368  *
87369  */
87370 /*
87371  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3
87372  *
87373  * Byte is unmasked (i.e. is compared)
87374  */
87375 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED 0x0
87376 /*
87377  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3
87378  *
87379  * Byte is masked (i.e. not compared)
87380  */
87381 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED 0x1
87382 
87383 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
87384 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_LSB 27
87385 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
87386 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_MSB 27
87387 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
87388 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_WIDTH 1
87389 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */
87390 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET_MSK 0x08000000
87391 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */
87392 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_CLR_MSK 0xf7ffffff
87393 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
87394 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_RESET 0x0
87395 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 field value from a register. */
87396 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
87397 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value suitable for setting the register. */
87398 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
87399 
87400 /*
87401  * Field : Mask Byte Control - mbc_4
87402  *
87403  * This array of bits are mask control bits for comparison of each of the MAC
87404  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87405  * received DA or SA with the contents of MAC Address111 high and low registers.
87406  * Each bit controls the masking of the bytes. You can filter a group of addresses
87407  * (known as group address filtering) by masking one or more bytes of the address.
87408  *
87409  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87410  *
87411  * Field Enumeration Values:
87412  *
87413  * Enum | Value | Description
87414  * :-----------------------------------------------|:------|:------------------------------------
87415  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87416  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87417  *
87418  * Field Access Macros:
87419  *
87420  */
87421 /*
87422  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4
87423  *
87424  * Byte is unmasked (i.e. is compared)
87425  */
87426 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED 0x0
87427 /*
87428  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4
87429  *
87430  * Byte is masked (i.e. not compared)
87431  */
87432 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED 0x1
87433 
87434 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
87435 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_LSB 28
87436 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
87437 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_MSB 28
87438 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
87439 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_WIDTH 1
87440 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */
87441 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET_MSK 0x10000000
87442 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */
87443 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_CLR_MSK 0xefffffff
87444 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
87445 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_RESET 0x0
87446 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 field value from a register. */
87447 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
87448 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value suitable for setting the register. */
87449 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
87450 
87451 /*
87452  * Field : Mask Byte Control - mbc_5
87453  *
87454  * This array of bits are mask control bits for comparison of each of the MAC
87455  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87456  * received DA or SA with the contents of MAC Address111 high and low registers.
87457  * Each bit controls the masking of the bytes. You can filter a group of addresses
87458  * (known as group address filtering) by masking one or more bytes of the address.
87459  *
87460  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87461  *
87462  * Field Enumeration Values:
87463  *
87464  * Enum | Value | Description
87465  * :-----------------------------------------------|:------|:------------------------------------
87466  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87467  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87468  *
87469  * Field Access Macros:
87470  *
87471  */
87472 /*
87473  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5
87474  *
87475  * Byte is unmasked (i.e. is compared)
87476  */
87477 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED 0x0
87478 /*
87479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5
87480  *
87481  * Byte is masked (i.e. not compared)
87482  */
87483 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED 0x1
87484 
87485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
87486 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_LSB 29
87487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
87488 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_MSB 29
87489 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
87490 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_WIDTH 1
87491 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */
87492 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET_MSK 0x20000000
87493 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */
87494 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_CLR_MSK 0xdfffffff
87495 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
87496 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_RESET 0x0
87497 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 field value from a register. */
87498 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
87499 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value suitable for setting the register. */
87500 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
87501 
87502 /*
87503  * Field : Source Address - sa
87504  *
87505  * When this bit is enabled, the MAC Address111[47:0] is used to compare with the
87506  * SA fields of the received frame. When this bit is disabled, the MAC
87507  * Address111[47:0] is used to compare with the DA fields of the received frame.
87508  *
87509  * Field Enumeration Values:
87510  *
87511  * Enum | Value | Description
87512  * :-----------------------------------------|:------|:-----------------------------
87513  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
87514  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END | 0x1 | MAC address compare enabled
87515  *
87516  * Field Access Macros:
87517  *
87518  */
87519 /*
87520  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA
87521  *
87522  * MAC address compare disabled
87523  */
87524 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD 0x0
87525 /*
87526  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA
87527  *
87528  * MAC address compare enabled
87529  */
87530 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END 0x1
87531 
87532 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
87533 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_LSB 30
87534 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
87535 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_MSB 30
87536 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
87537 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_WIDTH 1
87538 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */
87539 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET_MSK 0x40000000
87540 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */
87541 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_CLR_MSK 0xbfffffff
87542 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
87543 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_RESET 0x0
87544 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA field value from a register. */
87545 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
87546 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value suitable for setting the register. */
87547 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
87548 
87549 /*
87550  * Field : Address Enable - ae
87551  *
87552  * When this bit is enabled, the address filter block uses the 112th MAC address
87553  * for perfect filtering. When this bit is disabled, the address filter block
87554  * ignores the address for filtering.
87555  *
87556  * Field Enumeration Values:
87557  *
87558  * Enum | Value | Description
87559  * :-----------------------------------------|:------|:--------------------------------------
87560  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
87561  * ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
87562  *
87563  * Field Access Macros:
87564  *
87565  */
87566 /*
87567  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
87568  *
87569  * Second MAC address filtering disabled
87570  */
87571 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD 0x0
87572 /*
87573  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
87574  *
87575  * Second MAC address filtering enabled
87576  */
87577 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END 0x1
87578 
87579 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
87580 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_LSB 31
87581 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
87582 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_MSB 31
87583 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
87584 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_WIDTH 1
87585 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
87586 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET_MSK 0x80000000
87587 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
87588 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_CLR_MSK 0x7fffffff
87589 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
87590 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_RESET 0x0
87591 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE field value from a register. */
87592 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
87593 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value suitable for setting the register. */
87594 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
87595 
87596 #ifndef __ASSEMBLY__
87597 /*
87598  * WARNING: The C register and register group struct declarations are provided for
87599  * convenience and illustrative purposes. They should, however, be used with
87600  * caution as the C language standard provides no guarantees about the alignment or
87601  * atomicity of device memory accesses. The recommended practice for writing
87602  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87603  * alt_write_word() functions.
87604  *
87605  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH.
87606  */
87607 struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s
87608 {
87609  uint32_t addrhi : 16; /* MAC Address111 [47:32] */
87610  uint32_t : 8; /* *UNDEFINED* */
87611  uint32_t mbc_0 : 1; /* Mask Byte Control */
87612  uint32_t mbc_1 : 1; /* Mask Byte Control */
87613  uint32_t mbc_2 : 1; /* Mask Byte Control */
87614  uint32_t mbc_3 : 1; /* Mask Byte Control */
87615  uint32_t mbc_4 : 1; /* Mask Byte Control */
87616  uint32_t mbc_5 : 1; /* Mask Byte Control */
87617  uint32_t sa : 1; /* Source Address */
87618  uint32_t ae : 1; /* Address Enable */
87619 };
87620 
87621 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH. */
87622 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t;
87623 #endif /* __ASSEMBLY__ */
87624 
87625 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register from the beginning of the component. */
87626 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST 0xaf8
87627 /* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register. */
87628 #define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST))
87629 
87630 /*
87631  * Register : Register 703 (MAC Address111 Low Register) - MAC_Address111_Low
87632  *
87633  * The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC
87634  * address of the station.
87635  *
87636  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
87637  * format.
87638  *
87639  * Register Layout
87640  *
87641  * Bits | Access | Reset | Description
87642  * :-------|:-------|:-----------|:----------------------
87643  * [31:0] | RW | 0xffffffff | MAC Address111 [31:0]
87644  *
87645  */
87646 /*
87647  * Field : MAC Address111 [31:0] - addrlo
87648  *
87649  * This field contains the lower 32 bits of the 112th 6-byte MAC address. The
87650  * content of this field is undefined until loaded by software after the
87651  * initialization process.
87652  *
87653  * Field Access Macros:
87654  *
87655  */
87656 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
87657 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_LSB 0
87658 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
87659 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_MSB 31
87660 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
87661 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_WIDTH 32
87662 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
87663 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET_MSK 0xffffffff
87664 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
87665 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_CLR_MSK 0x00000000
87666 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
87667 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_RESET 0xffffffff
87668 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO field value from a register. */
87669 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
87670 /* Produces a ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value suitable for setting the register. */
87671 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
87672 
87673 #ifndef __ASSEMBLY__
87674 /*
87675  * WARNING: The C register and register group struct declarations are provided for
87676  * convenience and illustrative purposes. They should, however, be used with
87677  * caution as the C language standard provides no guarantees about the alignment or
87678  * atomicity of device memory accesses. The recommended practice for writing
87679  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
87680  * alt_write_word() functions.
87681  *
87682  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW.
87683  */
87684 struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s
87685 {
87686  uint32_t addrlo : 32; /* MAC Address111 [31:0] */
87687 };
87688 
87689 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW. */
87690 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s ALT_EMAC_GMAC_MAC_ADDR111_LOW_t;
87691 #endif /* __ASSEMBLY__ */
87692 
87693 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register from the beginning of the component. */
87694 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST 0xafc
87695 /* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register. */
87696 #define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST))
87697 
87698 /*
87699  * Register : Register 704 (MAC Address112 High Register) - MAC_Address112_High
87700  *
87701  * The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC
87702  * address of the station. Because the MAC address registers are configured to be
87703  * double-synchronized to the (G)MII clock domains, the synchronization is
87704  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
87705  * endian mode) of the MAC Address112 Low Register are written. For proper
87706  * synchronization updates, the consecutive writes to this Address Low Register
87707  * should be performed after at least four clock cycles in the destination clock
87708  * domain.
87709  *
87710  * Note that all MAC Address High registers (except MAC Address0 High) have the
87711  * same format.
87712  *
87713  * Register Layout
87714  *
87715  * Bits | Access | Reset | Description
87716  * :--------|:-------|:-------|:-----------------------
87717  * [15:0] | RW | 0xffff | MAC Address112 [47:32]
87718  * [23:16] | ??? | 0x0 | *UNDEFINED*
87719  * [24] | RW | 0x0 | Mask Byte Control
87720  * [25] | RW | 0x0 | Mask Byte Control
87721  * [26] | RW | 0x0 | Mask Byte Control
87722  * [27] | RW | 0x0 | Mask Byte Control
87723  * [28] | RW | 0x0 | Mask Byte Control
87724  * [29] | RW | 0x0 | Mask Byte Control
87725  * [30] | RW | 0x0 | Source Address
87726  * [31] | RW | 0x0 | Address Enable
87727  *
87728  */
87729 /*
87730  * Field : MAC Address112 [47:32] - addrhi
87731  *
87732  * This field contains the upper 16 bits (47:32) of the 113th 6-byte MAC address.
87733  *
87734  * Field Access Macros:
87735  *
87736  */
87737 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
87738 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_LSB 0
87739 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
87740 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_MSB 15
87741 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
87742 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_WIDTH 16
87743 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
87744 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET_MSK 0x0000ffff
87745 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
87746 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_CLR_MSK 0xffff0000
87747 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
87748 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_RESET 0xffff
87749 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI field value from a register. */
87750 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
87751 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value suitable for setting the register. */
87752 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
87753 
87754 /*
87755  * Field : Mask Byte Control - mbc_0
87756  *
87757  * This array of bits are mask control bits for comparison of each of the MAC
87758  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87759  * received DA or SA with the contents of MAC Address112 high and low registers.
87760  * Each bit controls the masking of the bytes. You can filter a group of addresses
87761  * (known as group address filtering) by masking one or more bytes of the address.
87762  *
87763  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87764  *
87765  * Field Enumeration Values:
87766  *
87767  * Enum | Value | Description
87768  * :-----------------------------------------------|:------|:------------------------------------
87769  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87770  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87771  *
87772  * Field Access Macros:
87773  *
87774  */
87775 /*
87776  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0
87777  *
87778  * Byte is unmasked (i.e. is compared)
87779  */
87780 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED 0x0
87781 /*
87782  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0
87783  *
87784  * Byte is masked (i.e. not compared)
87785  */
87786 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED 0x1
87787 
87788 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
87789 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_LSB 24
87790 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
87791 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_MSB 24
87792 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
87793 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_WIDTH 1
87794 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */
87795 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET_MSK 0x01000000
87796 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */
87797 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_CLR_MSK 0xfeffffff
87798 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
87799 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_RESET 0x0
87800 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 field value from a register. */
87801 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
87802 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value suitable for setting the register. */
87803 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
87804 
87805 /*
87806  * Field : Mask Byte Control - mbc_1
87807  *
87808  * This array of bits are mask control bits for comparison of each of the MAC
87809  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87810  * received DA or SA with the contents of MAC Address112 high and low registers.
87811  * Each bit controls the masking of the bytes. You can filter a group of addresses
87812  * (known as group address filtering) by masking one or more bytes of the address.
87813  *
87814  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87815  *
87816  * Field Enumeration Values:
87817  *
87818  * Enum | Value | Description
87819  * :-----------------------------------------------|:------|:------------------------------------
87820  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87821  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87822  *
87823  * Field Access Macros:
87824  *
87825  */
87826 /*
87827  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1
87828  *
87829  * Byte is unmasked (i.e. is compared)
87830  */
87831 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED 0x0
87832 /*
87833  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1
87834  *
87835  * Byte is masked (i.e. not compared)
87836  */
87837 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED 0x1
87838 
87839 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
87840 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_LSB 25
87841 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
87842 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_MSB 25
87843 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
87844 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_WIDTH 1
87845 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */
87846 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET_MSK 0x02000000
87847 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */
87848 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_CLR_MSK 0xfdffffff
87849 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
87850 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_RESET 0x0
87851 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 field value from a register. */
87852 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
87853 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value suitable for setting the register. */
87854 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
87855 
87856 /*
87857  * Field : Mask Byte Control - mbc_2
87858  *
87859  * This array of bits are mask control bits for comparison of each of the MAC
87860  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87861  * received DA or SA with the contents of MAC Address112 high and low registers.
87862  * Each bit controls the masking of the bytes. You can filter a group of addresses
87863  * (known as group address filtering) by masking one or more bytes of the address.
87864  *
87865  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87866  *
87867  * Field Enumeration Values:
87868  *
87869  * Enum | Value | Description
87870  * :-----------------------------------------------|:------|:------------------------------------
87871  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87872  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87873  *
87874  * Field Access Macros:
87875  *
87876  */
87877 /*
87878  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2
87879  *
87880  * Byte is unmasked (i.e. is compared)
87881  */
87882 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED 0x0
87883 /*
87884  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2
87885  *
87886  * Byte is masked (i.e. not compared)
87887  */
87888 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED 0x1
87889 
87890 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
87891 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_LSB 26
87892 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
87893 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_MSB 26
87894 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
87895 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_WIDTH 1
87896 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */
87897 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET_MSK 0x04000000
87898 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */
87899 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_CLR_MSK 0xfbffffff
87900 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
87901 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_RESET 0x0
87902 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 field value from a register. */
87903 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
87904 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value suitable for setting the register. */
87905 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
87906 
87907 /*
87908  * Field : Mask Byte Control - mbc_3
87909  *
87910  * This array of bits are mask control bits for comparison of each of the MAC
87911  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87912  * received DA or SA with the contents of MAC Address112 high and low registers.
87913  * Each bit controls the masking of the bytes. You can filter a group of addresses
87914  * (known as group address filtering) by masking one or more bytes of the address.
87915  *
87916  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87917  *
87918  * Field Enumeration Values:
87919  *
87920  * Enum | Value | Description
87921  * :-----------------------------------------------|:------|:------------------------------------
87922  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87923  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87924  *
87925  * Field Access Macros:
87926  *
87927  */
87928 /*
87929  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3
87930  *
87931  * Byte is unmasked (i.e. is compared)
87932  */
87933 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED 0x0
87934 /*
87935  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3
87936  *
87937  * Byte is masked (i.e. not compared)
87938  */
87939 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED 0x1
87940 
87941 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
87942 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_LSB 27
87943 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
87944 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_MSB 27
87945 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
87946 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_WIDTH 1
87947 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */
87948 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET_MSK 0x08000000
87949 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */
87950 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_CLR_MSK 0xf7ffffff
87951 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
87952 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_RESET 0x0
87953 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 field value from a register. */
87954 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
87955 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value suitable for setting the register. */
87956 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
87957 
87958 /*
87959  * Field : Mask Byte Control - mbc_4
87960  *
87961  * This array of bits are mask control bits for comparison of each of the MAC
87962  * Address bytes. When masked, the MAC does not compare the corresponding byte of
87963  * received DA or SA with the contents of MAC Address112 high and low registers.
87964  * Each bit controls the masking of the bytes. You can filter a group of addresses
87965  * (known as group address filtering) by masking one or more bytes of the address.
87966  *
87967  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
87968  *
87969  * Field Enumeration Values:
87970  *
87971  * Enum | Value | Description
87972  * :-----------------------------------------------|:------|:------------------------------------
87973  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
87974  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
87975  *
87976  * Field Access Macros:
87977  *
87978  */
87979 /*
87980  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4
87981  *
87982  * Byte is unmasked (i.e. is compared)
87983  */
87984 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED 0x0
87985 /*
87986  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4
87987  *
87988  * Byte is masked (i.e. not compared)
87989  */
87990 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED 0x1
87991 
87992 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
87993 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_LSB 28
87994 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
87995 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_MSB 28
87996 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
87997 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_WIDTH 1
87998 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */
87999 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET_MSK 0x10000000
88000 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */
88001 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_CLR_MSK 0xefffffff
88002 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
88003 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_RESET 0x0
88004 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 field value from a register. */
88005 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
88006 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value suitable for setting the register. */
88007 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
88008 
88009 /*
88010  * Field : Mask Byte Control - mbc_5
88011  *
88012  * This array of bits are mask control bits for comparison of each of the MAC
88013  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88014  * received DA or SA with the contents of MAC Address112 high and low registers.
88015  * Each bit controls the masking of the bytes. You can filter a group of addresses
88016  * (known as group address filtering) by masking one or more bytes of the address.
88017  *
88018  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88019  *
88020  * Field Enumeration Values:
88021  *
88022  * Enum | Value | Description
88023  * :-----------------------------------------------|:------|:------------------------------------
88024  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88025  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88026  *
88027  * Field Access Macros:
88028  *
88029  */
88030 /*
88031  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5
88032  *
88033  * Byte is unmasked (i.e. is compared)
88034  */
88035 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED 0x0
88036 /*
88037  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5
88038  *
88039  * Byte is masked (i.e. not compared)
88040  */
88041 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED 0x1
88042 
88043 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
88044 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_LSB 29
88045 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
88046 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_MSB 29
88047 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
88048 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_WIDTH 1
88049 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */
88050 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET_MSK 0x20000000
88051 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */
88052 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_CLR_MSK 0xdfffffff
88053 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
88054 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_RESET 0x0
88055 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 field value from a register. */
88056 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
88057 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value suitable for setting the register. */
88058 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
88059 
88060 /*
88061  * Field : Source Address - sa
88062  *
88063  * When this bit is enabled, the MAC Address112[47:0] is used to compare with the
88064  * SA fields of the received frame. When this bit is disabled, the MAC
88065  * Address112[47:0] is used to compare with the DA fields of the received frame.
88066  *
88067  * Field Enumeration Values:
88068  *
88069  * Enum | Value | Description
88070  * :-----------------------------------------|:------|:-----------------------------
88071  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
88072  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END | 0x1 | MAC address compare enabled
88073  *
88074  * Field Access Macros:
88075  *
88076  */
88077 /*
88078  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA
88079  *
88080  * MAC address compare disabled
88081  */
88082 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD 0x0
88083 /*
88084  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA
88085  *
88086  * MAC address compare enabled
88087  */
88088 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END 0x1
88089 
88090 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
88091 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_LSB 30
88092 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
88093 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_MSB 30
88094 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
88095 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_WIDTH 1
88096 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */
88097 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET_MSK 0x40000000
88098 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */
88099 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_CLR_MSK 0xbfffffff
88100 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
88101 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_RESET 0x0
88102 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA field value from a register. */
88103 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
88104 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value suitable for setting the register. */
88105 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
88106 
88107 /*
88108  * Field : Address Enable - ae
88109  *
88110  * When this bit is enabled, the address filter block uses the 113th MAC address
88111  * for perfect filtering. When this bit is disabled, the address filter block
88112  * ignores the address for filtering.
88113  *
88114  * Field Enumeration Values:
88115  *
88116  * Enum | Value | Description
88117  * :-----------------------------------------|:------|:--------------------------------------
88118  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
88119  * ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
88120  *
88121  * Field Access Macros:
88122  *
88123  */
88124 /*
88125  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
88126  *
88127  * Second MAC address filtering disabled
88128  */
88129 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD 0x0
88130 /*
88131  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
88132  *
88133  * Second MAC address filtering enabled
88134  */
88135 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END 0x1
88136 
88137 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
88138 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_LSB 31
88139 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
88140 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_MSB 31
88141 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
88142 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_WIDTH 1
88143 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
88144 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET_MSK 0x80000000
88145 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
88146 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_CLR_MSK 0x7fffffff
88147 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
88148 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_RESET 0x0
88149 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE field value from a register. */
88150 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
88151 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value suitable for setting the register. */
88152 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
88153 
88154 #ifndef __ASSEMBLY__
88155 /*
88156  * WARNING: The C register and register group struct declarations are provided for
88157  * convenience and illustrative purposes. They should, however, be used with
88158  * caution as the C language standard provides no guarantees about the alignment or
88159  * atomicity of device memory accesses. The recommended practice for writing
88160  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
88161  * alt_write_word() functions.
88162  *
88163  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH.
88164  */
88165 struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s
88166 {
88167  uint32_t addrhi : 16; /* MAC Address112 [47:32] */
88168  uint32_t : 8; /* *UNDEFINED* */
88169  uint32_t mbc_0 : 1; /* Mask Byte Control */
88170  uint32_t mbc_1 : 1; /* Mask Byte Control */
88171  uint32_t mbc_2 : 1; /* Mask Byte Control */
88172  uint32_t mbc_3 : 1; /* Mask Byte Control */
88173  uint32_t mbc_4 : 1; /* Mask Byte Control */
88174  uint32_t mbc_5 : 1; /* Mask Byte Control */
88175  uint32_t sa : 1; /* Source Address */
88176  uint32_t ae : 1; /* Address Enable */
88177 };
88178 
88179 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH. */
88180 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t;
88181 #endif /* __ASSEMBLY__ */
88182 
88183 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register from the beginning of the component. */
88184 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST 0xb00
88185 /* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register. */
88186 #define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST))
88187 
88188 /*
88189  * Register : Register 705 (MAC Address112 Low Register) - MAC_Address112_Low
88190  *
88191  * The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC
88192  * address of the station.
88193  *
88194  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
88195  * format.
88196  *
88197  * Register Layout
88198  *
88199  * Bits | Access | Reset | Description
88200  * :-------|:-------|:-----------|:----------------------
88201  * [31:0] | RW | 0xffffffff | MAC Address112 [31:0]
88202  *
88203  */
88204 /*
88205  * Field : MAC Address112 [31:0] - addrlo
88206  *
88207  * This field contains the lower 32 bits of the 113th 6-byte MAC address. The
88208  * content of this field is undefined until loaded by software after the
88209  * initialization process.
88210  *
88211  * Field Access Macros:
88212  *
88213  */
88214 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
88215 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_LSB 0
88216 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
88217 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_MSB 31
88218 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
88219 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_WIDTH 32
88220 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
88221 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET_MSK 0xffffffff
88222 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
88223 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_CLR_MSK 0x00000000
88224 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
88225 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_RESET 0xffffffff
88226 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO field value from a register. */
88227 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
88228 /* Produces a ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value suitable for setting the register. */
88229 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
88230 
88231 #ifndef __ASSEMBLY__
88232 /*
88233  * WARNING: The C register and register group struct declarations are provided for
88234  * convenience and illustrative purposes. They should, however, be used with
88235  * caution as the C language standard provides no guarantees about the alignment or
88236  * atomicity of device memory accesses. The recommended practice for writing
88237  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
88238  * alt_write_word() functions.
88239  *
88240  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW.
88241  */
88242 struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s
88243 {
88244  uint32_t addrlo : 32; /* MAC Address112 [31:0] */
88245 };
88246 
88247 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW. */
88248 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s ALT_EMAC_GMAC_MAC_ADDR112_LOW_t;
88249 #endif /* __ASSEMBLY__ */
88250 
88251 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register from the beginning of the component. */
88252 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST 0xb04
88253 /* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register. */
88254 #define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST))
88255 
88256 /*
88257  * Register : Register 706 (MAC Address113 High Register) - MAC_Address113_High
88258  *
88259  * The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC
88260  * address of the station. Because the MAC address registers are configured to be
88261  * double-synchronized to the (G)MII clock domains, the synchronization is
88262  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
88263  * endian mode) of the MAC Address113 Low Register are written. For proper
88264  * synchronization updates, the consecutive writes to this Address Low Register
88265  * should be performed after at least four clock cycles in the destination clock
88266  * domain.
88267  *
88268  * Note that all MAC Address High registers (except MAC Address0 High) have the
88269  * same format.
88270  *
88271  * Register Layout
88272  *
88273  * Bits | Access | Reset | Description
88274  * :--------|:-------|:-------|:-----------------------
88275  * [15:0] | RW | 0xffff | MAC Address113 [47:32]
88276  * [23:16] | ??? | 0x0 | *UNDEFINED*
88277  * [24] | RW | 0x0 | Mask Byte Control
88278  * [25] | RW | 0x0 | Mask Byte Control
88279  * [26] | RW | 0x0 | Mask Byte Control
88280  * [27] | RW | 0x0 | Mask Byte Control
88281  * [28] | RW | 0x0 | Mask Byte Control
88282  * [29] | RW | 0x0 | Mask Byte Control
88283  * [30] | RW | 0x0 | Source Address
88284  * [31] | RW | 0x0 | Address Enable
88285  *
88286  */
88287 /*
88288  * Field : MAC Address113 [47:32] - addrhi
88289  *
88290  * This field contains the upper 16 bits (47:32) of the 114th 6-byte MAC address.
88291  *
88292  * Field Access Macros:
88293  *
88294  */
88295 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
88296 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_LSB 0
88297 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
88298 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_MSB 15
88299 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
88300 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_WIDTH 16
88301 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
88302 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET_MSK 0x0000ffff
88303 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
88304 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_CLR_MSK 0xffff0000
88305 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
88306 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_RESET 0xffff
88307 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI field value from a register. */
88308 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
88309 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value suitable for setting the register. */
88310 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
88311 
88312 /*
88313  * Field : Mask Byte Control - mbc_0
88314  *
88315  * This array of bits are mask control bits for comparison of each of the MAC
88316  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88317  * received DA or SA with the contents of MAC Address113 high and low registers.
88318  * Each bit controls the masking of the bytes. You can filter a group of addresses
88319  * (known as group address filtering) by masking one or more bytes of the address.
88320  *
88321  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88322  *
88323  * Field Enumeration Values:
88324  *
88325  * Enum | Value | Description
88326  * :-----------------------------------------------|:------|:------------------------------------
88327  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88328  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88329  *
88330  * Field Access Macros:
88331  *
88332  */
88333 /*
88334  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0
88335  *
88336  * Byte is unmasked (i.e. is compared)
88337  */
88338 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED 0x0
88339 /*
88340  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0
88341  *
88342  * Byte is masked (i.e. not compared)
88343  */
88344 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED 0x1
88345 
88346 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
88347 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_LSB 24
88348 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
88349 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_MSB 24
88350 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
88351 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_WIDTH 1
88352 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */
88353 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET_MSK 0x01000000
88354 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */
88355 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_CLR_MSK 0xfeffffff
88356 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
88357 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_RESET 0x0
88358 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 field value from a register. */
88359 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
88360 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value suitable for setting the register. */
88361 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
88362 
88363 /*
88364  * Field : Mask Byte Control - mbc_1
88365  *
88366  * This array of bits are mask control bits for comparison of each of the MAC
88367  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88368  * received DA or SA with the contents of MAC Address113 high and low registers.
88369  * Each bit controls the masking of the bytes. You can filter a group of addresses
88370  * (known as group address filtering) by masking one or more bytes of the address.
88371  *
88372  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88373  *
88374  * Field Enumeration Values:
88375  *
88376  * Enum | Value | Description
88377  * :-----------------------------------------------|:------|:------------------------------------
88378  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88379  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88380  *
88381  * Field Access Macros:
88382  *
88383  */
88384 /*
88385  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1
88386  *
88387  * Byte is unmasked (i.e. is compared)
88388  */
88389 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED 0x0
88390 /*
88391  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1
88392  *
88393  * Byte is masked (i.e. not compared)
88394  */
88395 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED 0x1
88396 
88397 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
88398 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_LSB 25
88399 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
88400 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_MSB 25
88401 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
88402 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_WIDTH 1
88403 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */
88404 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET_MSK 0x02000000
88405 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */
88406 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_CLR_MSK 0xfdffffff
88407 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
88408 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_RESET 0x0
88409 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 field value from a register. */
88410 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
88411 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value suitable for setting the register. */
88412 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
88413 
88414 /*
88415  * Field : Mask Byte Control - mbc_2
88416  *
88417  * This array of bits are mask control bits for comparison of each of the MAC
88418  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88419  * received DA or SA with the contents of MAC Address113 high and low registers.
88420  * Each bit controls the masking of the bytes. You can filter a group of addresses
88421  * (known as group address filtering) by masking one or more bytes of the address.
88422  *
88423  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88424  *
88425  * Field Enumeration Values:
88426  *
88427  * Enum | Value | Description
88428  * :-----------------------------------------------|:------|:------------------------------------
88429  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88430  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88431  *
88432  * Field Access Macros:
88433  *
88434  */
88435 /*
88436  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2
88437  *
88438  * Byte is unmasked (i.e. is compared)
88439  */
88440 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED 0x0
88441 /*
88442  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2
88443  *
88444  * Byte is masked (i.e. not compared)
88445  */
88446 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED 0x1
88447 
88448 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
88449 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_LSB 26
88450 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
88451 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_MSB 26
88452 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
88453 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_WIDTH 1
88454 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */
88455 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET_MSK 0x04000000
88456 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */
88457 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_CLR_MSK 0xfbffffff
88458 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
88459 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_RESET 0x0
88460 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 field value from a register. */
88461 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
88462 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value suitable for setting the register. */
88463 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
88464 
88465 /*
88466  * Field : Mask Byte Control - mbc_3
88467  *
88468  * This array of bits are mask control bits for comparison of each of the MAC
88469  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88470  * received DA or SA with the contents of MAC Address113 high and low registers.
88471  * Each bit controls the masking of the bytes. You can filter a group of addresses
88472  * (known as group address filtering) by masking one or more bytes of the address.
88473  *
88474  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88475  *
88476  * Field Enumeration Values:
88477  *
88478  * Enum | Value | Description
88479  * :-----------------------------------------------|:------|:------------------------------------
88480  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88481  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88482  *
88483  * Field Access Macros:
88484  *
88485  */
88486 /*
88487  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3
88488  *
88489  * Byte is unmasked (i.e. is compared)
88490  */
88491 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED 0x0
88492 /*
88493  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3
88494  *
88495  * Byte is masked (i.e. not compared)
88496  */
88497 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED 0x1
88498 
88499 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
88500 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_LSB 27
88501 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
88502 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_MSB 27
88503 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
88504 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_WIDTH 1
88505 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */
88506 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET_MSK 0x08000000
88507 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */
88508 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_CLR_MSK 0xf7ffffff
88509 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
88510 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_RESET 0x0
88511 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 field value from a register. */
88512 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
88513 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value suitable for setting the register. */
88514 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
88515 
88516 /*
88517  * Field : Mask Byte Control - mbc_4
88518  *
88519  * This array of bits are mask control bits for comparison of each of the MAC
88520  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88521  * received DA or SA with the contents of MAC Address113 high and low registers.
88522  * Each bit controls the masking of the bytes. You can filter a group of addresses
88523  * (known as group address filtering) by masking one or more bytes of the address.
88524  *
88525  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88526  *
88527  * Field Enumeration Values:
88528  *
88529  * Enum | Value | Description
88530  * :-----------------------------------------------|:------|:------------------------------------
88531  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88532  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88533  *
88534  * Field Access Macros:
88535  *
88536  */
88537 /*
88538  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4
88539  *
88540  * Byte is unmasked (i.e. is compared)
88541  */
88542 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED 0x0
88543 /*
88544  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4
88545  *
88546  * Byte is masked (i.e. not compared)
88547  */
88548 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED 0x1
88549 
88550 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
88551 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_LSB 28
88552 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
88553 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_MSB 28
88554 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
88555 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_WIDTH 1
88556 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */
88557 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET_MSK 0x10000000
88558 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */
88559 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_CLR_MSK 0xefffffff
88560 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
88561 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_RESET 0x0
88562 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 field value from a register. */
88563 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
88564 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value suitable for setting the register. */
88565 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
88566 
88567 /*
88568  * Field : Mask Byte Control - mbc_5
88569  *
88570  * This array of bits are mask control bits for comparison of each of the MAC
88571  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88572  * received DA or SA with the contents of MAC Address113 high and low registers.
88573  * Each bit controls the masking of the bytes. You can filter a group of addresses
88574  * (known as group address filtering) by masking one or more bytes of the address.
88575  *
88576  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88577  *
88578  * Field Enumeration Values:
88579  *
88580  * Enum | Value | Description
88581  * :-----------------------------------------------|:------|:------------------------------------
88582  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88583  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88584  *
88585  * Field Access Macros:
88586  *
88587  */
88588 /*
88589  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5
88590  *
88591  * Byte is unmasked (i.e. is compared)
88592  */
88593 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED 0x0
88594 /*
88595  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5
88596  *
88597  * Byte is masked (i.e. not compared)
88598  */
88599 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED 0x1
88600 
88601 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
88602 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_LSB 29
88603 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
88604 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_MSB 29
88605 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
88606 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_WIDTH 1
88607 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */
88608 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET_MSK 0x20000000
88609 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */
88610 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_CLR_MSK 0xdfffffff
88611 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
88612 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_RESET 0x0
88613 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 field value from a register. */
88614 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
88615 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value suitable for setting the register. */
88616 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
88617 
88618 /*
88619  * Field : Source Address - sa
88620  *
88621  * When this bit is enabled, the MAC Address113[47:0] is used to compare with the
88622  * SA fields of the received frame. When this bit is disabled, the MAC
88623  * Address113[47:0] is used to compare with the DA fields of the received frame.
88624  *
88625  * Field Enumeration Values:
88626  *
88627  * Enum | Value | Description
88628  * :-----------------------------------------|:------|:-----------------------------
88629  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
88630  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END | 0x1 | MAC address compare enabled
88631  *
88632  * Field Access Macros:
88633  *
88634  */
88635 /*
88636  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA
88637  *
88638  * MAC address compare disabled
88639  */
88640 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD 0x0
88641 /*
88642  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA
88643  *
88644  * MAC address compare enabled
88645  */
88646 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END 0x1
88647 
88648 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
88649 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_LSB 30
88650 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
88651 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_MSB 30
88652 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
88653 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_WIDTH 1
88654 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */
88655 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET_MSK 0x40000000
88656 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */
88657 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_CLR_MSK 0xbfffffff
88658 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
88659 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_RESET 0x0
88660 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA field value from a register. */
88661 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
88662 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value suitable for setting the register. */
88663 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
88664 
88665 /*
88666  * Field : Address Enable - ae
88667  *
88668  * When this bit is enabled, the address filter block uses the 114th MAC address
88669  * for perfect filtering. When this bit is disabled, the address filter block
88670  * ignores the address for filtering.
88671  *
88672  * Field Enumeration Values:
88673  *
88674  * Enum | Value | Description
88675  * :-----------------------------------------|:------|:--------------------------------------
88676  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
88677  * ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
88678  *
88679  * Field Access Macros:
88680  *
88681  */
88682 /*
88683  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
88684  *
88685  * Second MAC address filtering disabled
88686  */
88687 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD 0x0
88688 /*
88689  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
88690  *
88691  * Second MAC address filtering enabled
88692  */
88693 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END 0x1
88694 
88695 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
88696 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_LSB 31
88697 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
88698 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_MSB 31
88699 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
88700 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_WIDTH 1
88701 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
88702 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET_MSK 0x80000000
88703 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
88704 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_CLR_MSK 0x7fffffff
88705 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
88706 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_RESET 0x0
88707 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE field value from a register. */
88708 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
88709 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value suitable for setting the register. */
88710 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
88711 
88712 #ifndef __ASSEMBLY__
88713 /*
88714  * WARNING: The C register and register group struct declarations are provided for
88715  * convenience and illustrative purposes. They should, however, be used with
88716  * caution as the C language standard provides no guarantees about the alignment or
88717  * atomicity of device memory accesses. The recommended practice for writing
88718  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
88719  * alt_write_word() functions.
88720  *
88721  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH.
88722  */
88723 struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s
88724 {
88725  uint32_t addrhi : 16; /* MAC Address113 [47:32] */
88726  uint32_t : 8; /* *UNDEFINED* */
88727  uint32_t mbc_0 : 1; /* Mask Byte Control */
88728  uint32_t mbc_1 : 1; /* Mask Byte Control */
88729  uint32_t mbc_2 : 1; /* Mask Byte Control */
88730  uint32_t mbc_3 : 1; /* Mask Byte Control */
88731  uint32_t mbc_4 : 1; /* Mask Byte Control */
88732  uint32_t mbc_5 : 1; /* Mask Byte Control */
88733  uint32_t sa : 1; /* Source Address */
88734  uint32_t ae : 1; /* Address Enable */
88735 };
88736 
88737 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH. */
88738 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t;
88739 #endif /* __ASSEMBLY__ */
88740 
88741 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register from the beginning of the component. */
88742 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST 0xb08
88743 /* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register. */
88744 #define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST))
88745 
88746 /*
88747  * Register : Register 707 (MAC Address113 Low Register) - MAC_Address113_Low
88748  *
88749  * The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC
88750  * address of the station.
88751  *
88752  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
88753  * format.
88754  *
88755  * Register Layout
88756  *
88757  * Bits | Access | Reset | Description
88758  * :-------|:-------|:-----------|:----------------------
88759  * [31:0] | RW | 0xffffffff | MAC Address113 [31:0]
88760  *
88761  */
88762 /*
88763  * Field : MAC Address113 [31:0] - addrlo
88764  *
88765  * This field contains the lower 32 bits of the 114th 6-byte MAC address. The
88766  * content of this field is undefined until loaded by software after the
88767  * initialization process.
88768  *
88769  * Field Access Macros:
88770  *
88771  */
88772 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
88773 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_LSB 0
88774 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
88775 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_MSB 31
88776 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
88777 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_WIDTH 32
88778 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
88779 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET_MSK 0xffffffff
88780 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
88781 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_CLR_MSK 0x00000000
88782 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
88783 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_RESET 0xffffffff
88784 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO field value from a register. */
88785 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
88786 /* Produces a ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value suitable for setting the register. */
88787 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
88788 
88789 #ifndef __ASSEMBLY__
88790 /*
88791  * WARNING: The C register and register group struct declarations are provided for
88792  * convenience and illustrative purposes. They should, however, be used with
88793  * caution as the C language standard provides no guarantees about the alignment or
88794  * atomicity of device memory accesses. The recommended practice for writing
88795  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
88796  * alt_write_word() functions.
88797  *
88798  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW.
88799  */
88800 struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s
88801 {
88802  uint32_t addrlo : 32; /* MAC Address113 [31:0] */
88803 };
88804 
88805 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW. */
88806 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s ALT_EMAC_GMAC_MAC_ADDR113_LOW_t;
88807 #endif /* __ASSEMBLY__ */
88808 
88809 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register from the beginning of the component. */
88810 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST 0xb0c
88811 /* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register. */
88812 #define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST))
88813 
88814 /*
88815  * Register : Register 708 (MAC Address114 High Register) - MAC_Address114_High
88816  *
88817  * The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC
88818  * address of the station. Because the MAC address registers are configured to be
88819  * double-synchronized to the (G)MII clock domains, the synchronization is
88820  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
88821  * endian mode) of the MAC Address114 Low Register are written. For proper
88822  * synchronization updates, the consecutive writes to this Address Low Register
88823  * should be performed after at least four clock cycles in the destination clock
88824  * domain.
88825  *
88826  * Note that all MAC Address High registers (except MAC Address0 High) have the
88827  * same format.
88828  *
88829  * Register Layout
88830  *
88831  * Bits | Access | Reset | Description
88832  * :--------|:-------|:-------|:-----------------------
88833  * [15:0] | RW | 0xffff | MAC Address114 [47:32]
88834  * [23:16] | ??? | 0x0 | *UNDEFINED*
88835  * [24] | RW | 0x0 | Mask Byte Control
88836  * [25] | RW | 0x0 | Mask Byte Control
88837  * [26] | RW | 0x0 | Mask Byte Control
88838  * [27] | RW | 0x0 | Mask Byte Control
88839  * [28] | RW | 0x0 | Mask Byte Control
88840  * [29] | RW | 0x0 | Mask Byte Control
88841  * [30] | RW | 0x0 | Source Address
88842  * [31] | RW | 0x0 | Address Enable
88843  *
88844  */
88845 /*
88846  * Field : MAC Address114 [47:32] - addrhi
88847  *
88848  * This field contains the upper 16 bits (47:32) of the 115th 6-byte MAC address.
88849  *
88850  * Field Access Macros:
88851  *
88852  */
88853 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
88854 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_LSB 0
88855 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
88856 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_MSB 15
88857 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
88858 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_WIDTH 16
88859 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
88860 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET_MSK 0x0000ffff
88861 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
88862 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_CLR_MSK 0xffff0000
88863 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
88864 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_RESET 0xffff
88865 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI field value from a register. */
88866 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
88867 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value suitable for setting the register. */
88868 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
88869 
88870 /*
88871  * Field : Mask Byte Control - mbc_0
88872  *
88873  * This array of bits are mask control bits for comparison of each of the MAC
88874  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88875  * received DA or SA with the contents of MAC Address114 high and low registers.
88876  * Each bit controls the masking of the bytes. You can filter a group of addresses
88877  * (known as group address filtering) by masking one or more bytes of the address.
88878  *
88879  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88880  *
88881  * Field Enumeration Values:
88882  *
88883  * Enum | Value | Description
88884  * :-----------------------------------------------|:------|:------------------------------------
88885  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88886  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88887  *
88888  * Field Access Macros:
88889  *
88890  */
88891 /*
88892  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0
88893  *
88894  * Byte is unmasked (i.e. is compared)
88895  */
88896 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED 0x0
88897 /*
88898  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0
88899  *
88900  * Byte is masked (i.e. not compared)
88901  */
88902 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED 0x1
88903 
88904 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
88905 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_LSB 24
88906 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
88907 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_MSB 24
88908 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
88909 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_WIDTH 1
88910 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */
88911 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET_MSK 0x01000000
88912 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */
88913 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_CLR_MSK 0xfeffffff
88914 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
88915 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_RESET 0x0
88916 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 field value from a register. */
88917 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
88918 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value suitable for setting the register. */
88919 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
88920 
88921 /*
88922  * Field : Mask Byte Control - mbc_1
88923  *
88924  * This array of bits are mask control bits for comparison of each of the MAC
88925  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88926  * received DA or SA with the contents of MAC Address114 high and low registers.
88927  * Each bit controls the masking of the bytes. You can filter a group of addresses
88928  * (known as group address filtering) by masking one or more bytes of the address.
88929  *
88930  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88931  *
88932  * Field Enumeration Values:
88933  *
88934  * Enum | Value | Description
88935  * :-----------------------------------------------|:------|:------------------------------------
88936  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88937  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88938  *
88939  * Field Access Macros:
88940  *
88941  */
88942 /*
88943  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1
88944  *
88945  * Byte is unmasked (i.e. is compared)
88946  */
88947 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED 0x0
88948 /*
88949  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1
88950  *
88951  * Byte is masked (i.e. not compared)
88952  */
88953 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED 0x1
88954 
88955 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
88956 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_LSB 25
88957 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
88958 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_MSB 25
88959 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
88960 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_WIDTH 1
88961 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */
88962 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET_MSK 0x02000000
88963 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */
88964 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_CLR_MSK 0xfdffffff
88965 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
88966 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_RESET 0x0
88967 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 field value from a register. */
88968 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
88969 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value suitable for setting the register. */
88970 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
88971 
88972 /*
88973  * Field : Mask Byte Control - mbc_2
88974  *
88975  * This array of bits are mask control bits for comparison of each of the MAC
88976  * Address bytes. When masked, the MAC does not compare the corresponding byte of
88977  * received DA or SA with the contents of MAC Address114 high and low registers.
88978  * Each bit controls the masking of the bytes. You can filter a group of addresses
88979  * (known as group address filtering) by masking one or more bytes of the address.
88980  *
88981  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
88982  *
88983  * Field Enumeration Values:
88984  *
88985  * Enum | Value | Description
88986  * :-----------------------------------------------|:------|:------------------------------------
88987  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
88988  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
88989  *
88990  * Field Access Macros:
88991  *
88992  */
88993 /*
88994  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2
88995  *
88996  * Byte is unmasked (i.e. is compared)
88997  */
88998 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED 0x0
88999 /*
89000  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2
89001  *
89002  * Byte is masked (i.e. not compared)
89003  */
89004 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED 0x1
89005 
89006 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
89007 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_LSB 26
89008 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
89009 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_MSB 26
89010 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
89011 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_WIDTH 1
89012 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */
89013 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET_MSK 0x04000000
89014 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */
89015 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_CLR_MSK 0xfbffffff
89016 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
89017 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_RESET 0x0
89018 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 field value from a register. */
89019 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
89020 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value suitable for setting the register. */
89021 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
89022 
89023 /*
89024  * Field : Mask Byte Control - mbc_3
89025  *
89026  * This array of bits are mask control bits for comparison of each of the MAC
89027  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89028  * received DA or SA with the contents of MAC Address114 high and low registers.
89029  * Each bit controls the masking of the bytes. You can filter a group of addresses
89030  * (known as group address filtering) by masking one or more bytes of the address.
89031  *
89032  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89033  *
89034  * Field Enumeration Values:
89035  *
89036  * Enum | Value | Description
89037  * :-----------------------------------------------|:------|:------------------------------------
89038  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89039  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89040  *
89041  * Field Access Macros:
89042  *
89043  */
89044 /*
89045  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3
89046  *
89047  * Byte is unmasked (i.e. is compared)
89048  */
89049 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED 0x0
89050 /*
89051  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3
89052  *
89053  * Byte is masked (i.e. not compared)
89054  */
89055 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED 0x1
89056 
89057 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
89058 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_LSB 27
89059 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
89060 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_MSB 27
89061 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
89062 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_WIDTH 1
89063 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */
89064 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET_MSK 0x08000000
89065 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */
89066 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_CLR_MSK 0xf7ffffff
89067 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
89068 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_RESET 0x0
89069 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 field value from a register. */
89070 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
89071 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value suitable for setting the register. */
89072 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
89073 
89074 /*
89075  * Field : Mask Byte Control - mbc_4
89076  *
89077  * This array of bits are mask control bits for comparison of each of the MAC
89078  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89079  * received DA or SA with the contents of MAC Address114 high and low registers.
89080  * Each bit controls the masking of the bytes. You can filter a group of addresses
89081  * (known as group address filtering) by masking one or more bytes of the address.
89082  *
89083  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89084  *
89085  * Field Enumeration Values:
89086  *
89087  * Enum | Value | Description
89088  * :-----------------------------------------------|:------|:------------------------------------
89089  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89090  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89091  *
89092  * Field Access Macros:
89093  *
89094  */
89095 /*
89096  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4
89097  *
89098  * Byte is unmasked (i.e. is compared)
89099  */
89100 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED 0x0
89101 /*
89102  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4
89103  *
89104  * Byte is masked (i.e. not compared)
89105  */
89106 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED 0x1
89107 
89108 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
89109 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_LSB 28
89110 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
89111 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_MSB 28
89112 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
89113 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_WIDTH 1
89114 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */
89115 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET_MSK 0x10000000
89116 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */
89117 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_CLR_MSK 0xefffffff
89118 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
89119 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_RESET 0x0
89120 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 field value from a register. */
89121 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
89122 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value suitable for setting the register. */
89123 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
89124 
89125 /*
89126  * Field : Mask Byte Control - mbc_5
89127  *
89128  * This array of bits are mask control bits for comparison of each of the MAC
89129  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89130  * received DA or SA with the contents of MAC Address114 high and low registers.
89131  * Each bit controls the masking of the bytes. You can filter a group of addresses
89132  * (known as group address filtering) by masking one or more bytes of the address.
89133  *
89134  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89135  *
89136  * Field Enumeration Values:
89137  *
89138  * Enum | Value | Description
89139  * :-----------------------------------------------|:------|:------------------------------------
89140  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89141  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89142  *
89143  * Field Access Macros:
89144  *
89145  */
89146 /*
89147  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5
89148  *
89149  * Byte is unmasked (i.e. is compared)
89150  */
89151 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED 0x0
89152 /*
89153  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5
89154  *
89155  * Byte is masked (i.e. not compared)
89156  */
89157 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED 0x1
89158 
89159 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
89160 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_LSB 29
89161 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
89162 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_MSB 29
89163 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
89164 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_WIDTH 1
89165 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */
89166 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET_MSK 0x20000000
89167 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */
89168 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_CLR_MSK 0xdfffffff
89169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
89170 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_RESET 0x0
89171 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 field value from a register. */
89172 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
89173 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value suitable for setting the register. */
89174 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
89175 
89176 /*
89177  * Field : Source Address - sa
89178  *
89179  * When this bit is enabled, the MAC Address114[47:0] is used to compare with the
89180  * SA fields of the received frame. When this bit is disabled, the MAC
89181  * Address114[47:0] is used to compare with the DA fields of the received frame.
89182  *
89183  * Field Enumeration Values:
89184  *
89185  * Enum | Value | Description
89186  * :-----------------------------------------|:------|:-----------------------------
89187  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
89188  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END | 0x1 | MAC address compare enabled
89189  *
89190  * Field Access Macros:
89191  *
89192  */
89193 /*
89194  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA
89195  *
89196  * MAC address compare disabled
89197  */
89198 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD 0x0
89199 /*
89200  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA
89201  *
89202  * MAC address compare enabled
89203  */
89204 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END 0x1
89205 
89206 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
89207 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_LSB 30
89208 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
89209 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_MSB 30
89210 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
89211 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_WIDTH 1
89212 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */
89213 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET_MSK 0x40000000
89214 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */
89215 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_CLR_MSK 0xbfffffff
89216 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
89217 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_RESET 0x0
89218 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA field value from a register. */
89219 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
89220 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value suitable for setting the register. */
89221 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
89222 
89223 /*
89224  * Field : Address Enable - ae
89225  *
89226  * When this bit is enabled, the address filter block uses the 115th MAC address
89227  * for perfect filtering. When this bit is disabled, the address filter block
89228  * ignores the address for filtering.
89229  *
89230  * Field Enumeration Values:
89231  *
89232  * Enum | Value | Description
89233  * :-----------------------------------------|:------|:--------------------------------------
89234  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
89235  * ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
89236  *
89237  * Field Access Macros:
89238  *
89239  */
89240 /*
89241  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
89242  *
89243  * Second MAC address filtering disabled
89244  */
89245 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD 0x0
89246 /*
89247  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
89248  *
89249  * Second MAC address filtering enabled
89250  */
89251 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END 0x1
89252 
89253 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
89254 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_LSB 31
89255 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
89256 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_MSB 31
89257 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
89258 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_WIDTH 1
89259 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
89260 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET_MSK 0x80000000
89261 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
89262 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_CLR_MSK 0x7fffffff
89263 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
89264 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_RESET 0x0
89265 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE field value from a register. */
89266 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
89267 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value suitable for setting the register. */
89268 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
89269 
89270 #ifndef __ASSEMBLY__
89271 /*
89272  * WARNING: The C register and register group struct declarations are provided for
89273  * convenience and illustrative purposes. They should, however, be used with
89274  * caution as the C language standard provides no guarantees about the alignment or
89275  * atomicity of device memory accesses. The recommended practice for writing
89276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89277  * alt_write_word() functions.
89278  *
89279  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH.
89280  */
89281 struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s
89282 {
89283  uint32_t addrhi : 16; /* MAC Address114 [47:32] */
89284  uint32_t : 8; /* *UNDEFINED* */
89285  uint32_t mbc_0 : 1; /* Mask Byte Control */
89286  uint32_t mbc_1 : 1; /* Mask Byte Control */
89287  uint32_t mbc_2 : 1; /* Mask Byte Control */
89288  uint32_t mbc_3 : 1; /* Mask Byte Control */
89289  uint32_t mbc_4 : 1; /* Mask Byte Control */
89290  uint32_t mbc_5 : 1; /* Mask Byte Control */
89291  uint32_t sa : 1; /* Source Address */
89292  uint32_t ae : 1; /* Address Enable */
89293 };
89294 
89295 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH. */
89296 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t;
89297 #endif /* __ASSEMBLY__ */
89298 
89299 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register from the beginning of the component. */
89300 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST 0xb10
89301 /* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register. */
89302 #define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST))
89303 
89304 /*
89305  * Register : Register 709 (MAC Address114 Low Register) - MAC_Address114_Low
89306  *
89307  * The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC
89308  * address of the station.
89309  *
89310  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
89311  * format.
89312  *
89313  * Register Layout
89314  *
89315  * Bits | Access | Reset | Description
89316  * :-------|:-------|:-----------|:----------------------
89317  * [31:0] | RW | 0xffffffff | MAC Address114 [31:0]
89318  *
89319  */
89320 /*
89321  * Field : MAC Address114 [31:0] - addrlo
89322  *
89323  * This field contains the lower 32 bits of the 115th 6-byte MAC address. The
89324  * content of this field is undefined until loaded by software after the
89325  * initialization process.
89326  *
89327  * Field Access Macros:
89328  *
89329  */
89330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
89331 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_LSB 0
89332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
89333 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_MSB 31
89334 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
89335 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_WIDTH 32
89336 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
89337 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET_MSK 0xffffffff
89338 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
89339 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_CLR_MSK 0x00000000
89340 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
89341 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_RESET 0xffffffff
89342 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO field value from a register. */
89343 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
89344 /* Produces a ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value suitable for setting the register. */
89345 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
89346 
89347 #ifndef __ASSEMBLY__
89348 /*
89349  * WARNING: The C register and register group struct declarations are provided for
89350  * convenience and illustrative purposes. They should, however, be used with
89351  * caution as the C language standard provides no guarantees about the alignment or
89352  * atomicity of device memory accesses. The recommended practice for writing
89353  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89354  * alt_write_word() functions.
89355  *
89356  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW.
89357  */
89358 struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s
89359 {
89360  uint32_t addrlo : 32; /* MAC Address114 [31:0] */
89361 };
89362 
89363 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW. */
89364 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s ALT_EMAC_GMAC_MAC_ADDR114_LOW_t;
89365 #endif /* __ASSEMBLY__ */
89366 
89367 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register from the beginning of the component. */
89368 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST 0xb14
89369 /* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register. */
89370 #define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST))
89371 
89372 /*
89373  * Register : Register 710 (MAC Address115 High Register) - MAC_Address115_High
89374  *
89375  * The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC
89376  * address of the station. Because the MAC address registers are configured to be
89377  * double-synchronized to the (G)MII clock domains, the synchronization is
89378  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
89379  * endian mode) of the MAC Address115 Low Register are written. For proper
89380  * synchronization updates, the consecutive writes to this Address Low Register
89381  * should be performed after at least four clock cycles in the destination clock
89382  * domain.
89383  *
89384  * Note that all MAC Address High registers (except MAC Address0 High) have the
89385  * same format.
89386  *
89387  * Register Layout
89388  *
89389  * Bits | Access | Reset | Description
89390  * :--------|:-------|:-------|:-----------------------
89391  * [15:0] | RW | 0xffff | MAC Address115 [47:32]
89392  * [23:16] | ??? | 0x0 | *UNDEFINED*
89393  * [24] | RW | 0x0 | Mask Byte Control
89394  * [25] | RW | 0x0 | Mask Byte Control
89395  * [26] | RW | 0x0 | Mask Byte Control
89396  * [27] | RW | 0x0 | Mask Byte Control
89397  * [28] | RW | 0x0 | Mask Byte Control
89398  * [29] | RW | 0x0 | Mask Byte Control
89399  * [30] | RW | 0x0 | Source Address
89400  * [31] | RW | 0x0 | Address Enable
89401  *
89402  */
89403 /*
89404  * Field : MAC Address115 [47:32] - addrhi
89405  *
89406  * This field contains the upper 16 bits (47:32) of the 116th 6-byte MAC address.
89407  *
89408  * Field Access Macros:
89409  *
89410  */
89411 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
89412 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_LSB 0
89413 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
89414 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_MSB 15
89415 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
89416 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_WIDTH 16
89417 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
89418 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET_MSK 0x0000ffff
89419 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
89420 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_CLR_MSK 0xffff0000
89421 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
89422 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_RESET 0xffff
89423 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI field value from a register. */
89424 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
89425 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value suitable for setting the register. */
89426 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
89427 
89428 /*
89429  * Field : Mask Byte Control - mbc_0
89430  *
89431  * This array of bits are mask control bits for comparison of each of the MAC
89432  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89433  * received DA or SA with the contents of MAC Address115 high and low registers.
89434  * Each bit controls the masking of the bytes. You can filter a group of addresses
89435  * (known as group address filtering) by masking one or more bytes of the address.
89436  *
89437  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89438  *
89439  * Field Enumeration Values:
89440  *
89441  * Enum | Value | Description
89442  * :-----------------------------------------------|:------|:------------------------------------
89443  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89444  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89445  *
89446  * Field Access Macros:
89447  *
89448  */
89449 /*
89450  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0
89451  *
89452  * Byte is unmasked (i.e. is compared)
89453  */
89454 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED 0x0
89455 /*
89456  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0
89457  *
89458  * Byte is masked (i.e. not compared)
89459  */
89460 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED 0x1
89461 
89462 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
89463 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_LSB 24
89464 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
89465 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_MSB 24
89466 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
89467 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_WIDTH 1
89468 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */
89469 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET_MSK 0x01000000
89470 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */
89471 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_CLR_MSK 0xfeffffff
89472 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
89473 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_RESET 0x0
89474 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 field value from a register. */
89475 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
89476 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value suitable for setting the register. */
89477 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
89478 
89479 /*
89480  * Field : Mask Byte Control - mbc_1
89481  *
89482  * This array of bits are mask control bits for comparison of each of the MAC
89483  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89484  * received DA or SA with the contents of MAC Address115 high and low registers.
89485  * Each bit controls the masking of the bytes. You can filter a group of addresses
89486  * (known as group address filtering) by masking one or more bytes of the address.
89487  *
89488  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89489  *
89490  * Field Enumeration Values:
89491  *
89492  * Enum | Value | Description
89493  * :-----------------------------------------------|:------|:------------------------------------
89494  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89495  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89496  *
89497  * Field Access Macros:
89498  *
89499  */
89500 /*
89501  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1
89502  *
89503  * Byte is unmasked (i.e. is compared)
89504  */
89505 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED 0x0
89506 /*
89507  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1
89508  *
89509  * Byte is masked (i.e. not compared)
89510  */
89511 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED 0x1
89512 
89513 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
89514 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_LSB 25
89515 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
89516 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_MSB 25
89517 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
89518 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_WIDTH 1
89519 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */
89520 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET_MSK 0x02000000
89521 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */
89522 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_CLR_MSK 0xfdffffff
89523 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
89524 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_RESET 0x0
89525 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 field value from a register. */
89526 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
89527 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value suitable for setting the register. */
89528 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
89529 
89530 /*
89531  * Field : Mask Byte Control - mbc_2
89532  *
89533  * This array of bits are mask control bits for comparison of each of the MAC
89534  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89535  * received DA or SA with the contents of MAC Address115 high and low registers.
89536  * Each bit controls the masking of the bytes. You can filter a group of addresses
89537  * (known as group address filtering) by masking one or more bytes of the address.
89538  *
89539  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89540  *
89541  * Field Enumeration Values:
89542  *
89543  * Enum | Value | Description
89544  * :-----------------------------------------------|:------|:------------------------------------
89545  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89546  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89547  *
89548  * Field Access Macros:
89549  *
89550  */
89551 /*
89552  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2
89553  *
89554  * Byte is unmasked (i.e. is compared)
89555  */
89556 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED 0x0
89557 /*
89558  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2
89559  *
89560  * Byte is masked (i.e. not compared)
89561  */
89562 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED 0x1
89563 
89564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
89565 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_LSB 26
89566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
89567 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_MSB 26
89568 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
89569 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_WIDTH 1
89570 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */
89571 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET_MSK 0x04000000
89572 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */
89573 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_CLR_MSK 0xfbffffff
89574 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
89575 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_RESET 0x0
89576 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 field value from a register. */
89577 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
89578 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value suitable for setting the register. */
89579 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
89580 
89581 /*
89582  * Field : Mask Byte Control - mbc_3
89583  *
89584  * This array of bits are mask control bits for comparison of each of the MAC
89585  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89586  * received DA or SA with the contents of MAC Address115 high and low registers.
89587  * Each bit controls the masking of the bytes. You can filter a group of addresses
89588  * (known as group address filtering) by masking one or more bytes of the address.
89589  *
89590  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89591  *
89592  * Field Enumeration Values:
89593  *
89594  * Enum | Value | Description
89595  * :-----------------------------------------------|:------|:------------------------------------
89596  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89597  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89598  *
89599  * Field Access Macros:
89600  *
89601  */
89602 /*
89603  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3
89604  *
89605  * Byte is unmasked (i.e. is compared)
89606  */
89607 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED 0x0
89608 /*
89609  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3
89610  *
89611  * Byte is masked (i.e. not compared)
89612  */
89613 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED 0x1
89614 
89615 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
89616 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_LSB 27
89617 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
89618 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_MSB 27
89619 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
89620 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_WIDTH 1
89621 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */
89622 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET_MSK 0x08000000
89623 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */
89624 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_CLR_MSK 0xf7ffffff
89625 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
89626 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_RESET 0x0
89627 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 field value from a register. */
89628 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
89629 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value suitable for setting the register. */
89630 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
89631 
89632 /*
89633  * Field : Mask Byte Control - mbc_4
89634  *
89635  * This array of bits are mask control bits for comparison of each of the MAC
89636  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89637  * received DA or SA with the contents of MAC Address115 high and low registers.
89638  * Each bit controls the masking of the bytes. You can filter a group of addresses
89639  * (known as group address filtering) by masking one or more bytes of the address.
89640  *
89641  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89642  *
89643  * Field Enumeration Values:
89644  *
89645  * Enum | Value | Description
89646  * :-----------------------------------------------|:------|:------------------------------------
89647  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89648  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89649  *
89650  * Field Access Macros:
89651  *
89652  */
89653 /*
89654  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4
89655  *
89656  * Byte is unmasked (i.e. is compared)
89657  */
89658 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED 0x0
89659 /*
89660  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4
89661  *
89662  * Byte is masked (i.e. not compared)
89663  */
89664 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED 0x1
89665 
89666 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
89667 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_LSB 28
89668 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
89669 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_MSB 28
89670 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
89671 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_WIDTH 1
89672 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */
89673 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET_MSK 0x10000000
89674 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */
89675 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_CLR_MSK 0xefffffff
89676 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
89677 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_RESET 0x0
89678 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 field value from a register. */
89679 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
89680 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value suitable for setting the register. */
89681 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
89682 
89683 /*
89684  * Field : Mask Byte Control - mbc_5
89685  *
89686  * This array of bits are mask control bits for comparison of each of the MAC
89687  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89688  * received DA or SA with the contents of MAC Address115 high and low registers.
89689  * Each bit controls the masking of the bytes. You can filter a group of addresses
89690  * (known as group address filtering) by masking one or more bytes of the address.
89691  *
89692  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89693  *
89694  * Field Enumeration Values:
89695  *
89696  * Enum | Value | Description
89697  * :-----------------------------------------------|:------|:------------------------------------
89698  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
89699  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
89700  *
89701  * Field Access Macros:
89702  *
89703  */
89704 /*
89705  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5
89706  *
89707  * Byte is unmasked (i.e. is compared)
89708  */
89709 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED 0x0
89710 /*
89711  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5
89712  *
89713  * Byte is masked (i.e. not compared)
89714  */
89715 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED 0x1
89716 
89717 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
89718 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_LSB 29
89719 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
89720 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_MSB 29
89721 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
89722 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_WIDTH 1
89723 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */
89724 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET_MSK 0x20000000
89725 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */
89726 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_CLR_MSK 0xdfffffff
89727 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
89728 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_RESET 0x0
89729 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 field value from a register. */
89730 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
89731 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value suitable for setting the register. */
89732 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
89733 
89734 /*
89735  * Field : Source Address - sa
89736  *
89737  * When this bit is enabled, the MAC Address115[47:0] is used to compare with the
89738  * SA fields of the received frame. When this bit is disabled, the MAC
89739  * Address115[47:0] is used to compare with the DA fields of the received frame.
89740  *
89741  * Field Enumeration Values:
89742  *
89743  * Enum | Value | Description
89744  * :-----------------------------------------|:------|:-----------------------------
89745  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
89746  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END | 0x1 | MAC address compare enabled
89747  *
89748  * Field Access Macros:
89749  *
89750  */
89751 /*
89752  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA
89753  *
89754  * MAC address compare disabled
89755  */
89756 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD 0x0
89757 /*
89758  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA
89759  *
89760  * MAC address compare enabled
89761  */
89762 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END 0x1
89763 
89764 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
89765 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_LSB 30
89766 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
89767 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_MSB 30
89768 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
89769 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_WIDTH 1
89770 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */
89771 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET_MSK 0x40000000
89772 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */
89773 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_CLR_MSK 0xbfffffff
89774 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
89775 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_RESET 0x0
89776 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA field value from a register. */
89777 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
89778 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value suitable for setting the register. */
89779 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
89780 
89781 /*
89782  * Field : Address Enable - ae
89783  *
89784  * When this bit is enabled, the address filter block uses the 116th MAC address
89785  * for perfect filtering. When this bit is disabled, the address filter block
89786  * ignores the address for filtering.
89787  *
89788  * Field Enumeration Values:
89789  *
89790  * Enum | Value | Description
89791  * :-----------------------------------------|:------|:--------------------------------------
89792  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
89793  * ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
89794  *
89795  * Field Access Macros:
89796  *
89797  */
89798 /*
89799  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
89800  *
89801  * Second MAC address filtering disabled
89802  */
89803 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD 0x0
89804 /*
89805  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
89806  *
89807  * Second MAC address filtering enabled
89808  */
89809 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END 0x1
89810 
89811 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
89812 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_LSB 31
89813 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
89814 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_MSB 31
89815 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
89816 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_WIDTH 1
89817 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
89818 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET_MSK 0x80000000
89819 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
89820 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_CLR_MSK 0x7fffffff
89821 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
89822 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_RESET 0x0
89823 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE field value from a register. */
89824 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
89825 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value suitable for setting the register. */
89826 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
89827 
89828 #ifndef __ASSEMBLY__
89829 /*
89830  * WARNING: The C register and register group struct declarations are provided for
89831  * convenience and illustrative purposes. They should, however, be used with
89832  * caution as the C language standard provides no guarantees about the alignment or
89833  * atomicity of device memory accesses. The recommended practice for writing
89834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89835  * alt_write_word() functions.
89836  *
89837  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH.
89838  */
89839 struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s
89840 {
89841  uint32_t addrhi : 16; /* MAC Address115 [47:32] */
89842  uint32_t : 8; /* *UNDEFINED* */
89843  uint32_t mbc_0 : 1; /* Mask Byte Control */
89844  uint32_t mbc_1 : 1; /* Mask Byte Control */
89845  uint32_t mbc_2 : 1; /* Mask Byte Control */
89846  uint32_t mbc_3 : 1; /* Mask Byte Control */
89847  uint32_t mbc_4 : 1; /* Mask Byte Control */
89848  uint32_t mbc_5 : 1; /* Mask Byte Control */
89849  uint32_t sa : 1; /* Source Address */
89850  uint32_t ae : 1; /* Address Enable */
89851 };
89852 
89853 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH. */
89854 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t;
89855 #endif /* __ASSEMBLY__ */
89856 
89857 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register from the beginning of the component. */
89858 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST 0xb18
89859 /* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register. */
89860 #define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST))
89861 
89862 /*
89863  * Register : Register 711 (MAC Address115 Low Register) - MAC_Address115_Low
89864  *
89865  * The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC
89866  * address of the station.
89867  *
89868  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
89869  * format.
89870  *
89871  * Register Layout
89872  *
89873  * Bits | Access | Reset | Description
89874  * :-------|:-------|:-----------|:----------------------
89875  * [31:0] | RW | 0xffffffff | MAC Address115 [31:0]
89876  *
89877  */
89878 /*
89879  * Field : MAC Address115 [31:0] - addrlo
89880  *
89881  * This field contains the lower 32 bits of the 116th 6-byte MAC address. The
89882  * content of this field is undefined until loaded by software after the
89883  * initialization process.
89884  *
89885  * Field Access Macros:
89886  *
89887  */
89888 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
89889 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_LSB 0
89890 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
89891 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_MSB 31
89892 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
89893 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_WIDTH 32
89894 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
89895 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET_MSK 0xffffffff
89896 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
89897 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_CLR_MSK 0x00000000
89898 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
89899 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_RESET 0xffffffff
89900 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO field value from a register. */
89901 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
89902 /* Produces a ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value suitable for setting the register. */
89903 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
89904 
89905 #ifndef __ASSEMBLY__
89906 /*
89907  * WARNING: The C register and register group struct declarations are provided for
89908  * convenience and illustrative purposes. They should, however, be used with
89909  * caution as the C language standard provides no guarantees about the alignment or
89910  * atomicity of device memory accesses. The recommended practice for writing
89911  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
89912  * alt_write_word() functions.
89913  *
89914  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW.
89915  */
89916 struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s
89917 {
89918  uint32_t addrlo : 32; /* MAC Address115 [31:0] */
89919 };
89920 
89921 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW. */
89922 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s ALT_EMAC_GMAC_MAC_ADDR115_LOW_t;
89923 #endif /* __ASSEMBLY__ */
89924 
89925 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register from the beginning of the component. */
89926 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST 0xb1c
89927 /* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register. */
89928 #define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST))
89929 
89930 /*
89931  * Register : Register 712 (MAC Address116 High Register) - MAC_Address116_High
89932  *
89933  * The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC
89934  * address of the station. Because the MAC address registers are configured to be
89935  * double-synchronized to the (G)MII clock domains, the synchronization is
89936  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
89937  * endian mode) of the MAC Address116 Low Register are written. For proper
89938  * synchronization updates, the consecutive writes to this Address Low Register
89939  * should be performed after at least four clock cycles in the destination clock
89940  * domain.
89941  *
89942  * Note that all MAC Address High registers (except MAC Address0 High) have the
89943  * same format.
89944  *
89945  * Register Layout
89946  *
89947  * Bits | Access | Reset | Description
89948  * :--------|:-------|:-------|:-----------------------
89949  * [15:0] | RW | 0xffff | MAC Address116 [47:32]
89950  * [23:16] | ??? | 0x0 | *UNDEFINED*
89951  * [24] | RW | 0x0 | Mask Byte Control
89952  * [25] | RW | 0x0 | Mask Byte Control
89953  * [26] | RW | 0x0 | Mask Byte Control
89954  * [27] | RW | 0x0 | Mask Byte Control
89955  * [28] | RW | 0x0 | Mask Byte Control
89956  * [29] | RW | 0x0 | Mask Byte Control
89957  * [30] | RW | 0x0 | Source Address
89958  * [31] | RW | 0x0 | Address Enable
89959  *
89960  */
89961 /*
89962  * Field : MAC Address116 [47:32] - addrhi
89963  *
89964  * This field contains the upper 16 bits (47:32) of the 117th 6-byte MAC address.
89965  *
89966  * Field Access Macros:
89967  *
89968  */
89969 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
89970 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_LSB 0
89971 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
89972 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_MSB 15
89973 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
89974 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_WIDTH 16
89975 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
89976 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET_MSK 0x0000ffff
89977 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
89978 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_CLR_MSK 0xffff0000
89979 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
89980 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_RESET 0xffff
89981 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI field value from a register. */
89982 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
89983 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value suitable for setting the register. */
89984 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
89985 
89986 /*
89987  * Field : Mask Byte Control - mbc_0
89988  *
89989  * This array of bits are mask control bits for comparison of each of the MAC
89990  * Address bytes. When masked, the MAC does not compare the corresponding byte of
89991  * received DA or SA with the contents of MAC Address116 high and low registers.
89992  * Each bit controls the masking of the bytes. You can filter a group of addresses
89993  * (known as group address filtering) by masking one or more bytes of the address.
89994  *
89995  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
89996  *
89997  * Field Enumeration Values:
89998  *
89999  * Enum | Value | Description
90000  * :-----------------------------------------------|:------|:------------------------------------
90001  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90002  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90003  *
90004  * Field Access Macros:
90005  *
90006  */
90007 /*
90008  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0
90009  *
90010  * Byte is unmasked (i.e. is compared)
90011  */
90012 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED 0x0
90013 /*
90014  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0
90015  *
90016  * Byte is masked (i.e. not compared)
90017  */
90018 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED 0x1
90019 
90020 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
90021 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_LSB 24
90022 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
90023 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_MSB 24
90024 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
90025 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_WIDTH 1
90026 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */
90027 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET_MSK 0x01000000
90028 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */
90029 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_CLR_MSK 0xfeffffff
90030 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
90031 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_RESET 0x0
90032 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 field value from a register. */
90033 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
90034 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value suitable for setting the register. */
90035 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
90036 
90037 /*
90038  * Field : Mask Byte Control - mbc_1
90039  *
90040  * This array of bits are mask control bits for comparison of each of the MAC
90041  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90042  * received DA or SA with the contents of MAC Address116 high and low registers.
90043  * Each bit controls the masking of the bytes. You can filter a group of addresses
90044  * (known as group address filtering) by masking one or more bytes of the address.
90045  *
90046  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90047  *
90048  * Field Enumeration Values:
90049  *
90050  * Enum | Value | Description
90051  * :-----------------------------------------------|:------|:------------------------------------
90052  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90053  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90054  *
90055  * Field Access Macros:
90056  *
90057  */
90058 /*
90059  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1
90060  *
90061  * Byte is unmasked (i.e. is compared)
90062  */
90063 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED 0x0
90064 /*
90065  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1
90066  *
90067  * Byte is masked (i.e. not compared)
90068  */
90069 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED 0x1
90070 
90071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
90072 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_LSB 25
90073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
90074 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_MSB 25
90075 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
90076 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_WIDTH 1
90077 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */
90078 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET_MSK 0x02000000
90079 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */
90080 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_CLR_MSK 0xfdffffff
90081 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
90082 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_RESET 0x0
90083 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 field value from a register. */
90084 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
90085 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value suitable for setting the register. */
90086 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
90087 
90088 /*
90089  * Field : Mask Byte Control - mbc_2
90090  *
90091  * This array of bits are mask control bits for comparison of each of the MAC
90092  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90093  * received DA or SA with the contents of MAC Address116 high and low registers.
90094  * Each bit controls the masking of the bytes. You can filter a group of addresses
90095  * (known as group address filtering) by masking one or more bytes of the address.
90096  *
90097  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90098  *
90099  * Field Enumeration Values:
90100  *
90101  * Enum | Value | Description
90102  * :-----------------------------------------------|:------|:------------------------------------
90103  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90104  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90105  *
90106  * Field Access Macros:
90107  *
90108  */
90109 /*
90110  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2
90111  *
90112  * Byte is unmasked (i.e. is compared)
90113  */
90114 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED 0x0
90115 /*
90116  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2
90117  *
90118  * Byte is masked (i.e. not compared)
90119  */
90120 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED 0x1
90121 
90122 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
90123 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_LSB 26
90124 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
90125 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_MSB 26
90126 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
90127 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_WIDTH 1
90128 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */
90129 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET_MSK 0x04000000
90130 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */
90131 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_CLR_MSK 0xfbffffff
90132 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
90133 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_RESET 0x0
90134 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 field value from a register. */
90135 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
90136 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value suitable for setting the register. */
90137 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
90138 
90139 /*
90140  * Field : Mask Byte Control - mbc_3
90141  *
90142  * This array of bits are mask control bits for comparison of each of the MAC
90143  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90144  * received DA or SA with the contents of MAC Address116 high and low registers.
90145  * Each bit controls the masking of the bytes. You can filter a group of addresses
90146  * (known as group address filtering) by masking one or more bytes of the address.
90147  *
90148  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90149  *
90150  * Field Enumeration Values:
90151  *
90152  * Enum | Value | Description
90153  * :-----------------------------------------------|:------|:------------------------------------
90154  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90155  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90156  *
90157  * Field Access Macros:
90158  *
90159  */
90160 /*
90161  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3
90162  *
90163  * Byte is unmasked (i.e. is compared)
90164  */
90165 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED 0x0
90166 /*
90167  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3
90168  *
90169  * Byte is masked (i.e. not compared)
90170  */
90171 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED 0x1
90172 
90173 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
90174 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_LSB 27
90175 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
90176 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_MSB 27
90177 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
90178 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_WIDTH 1
90179 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */
90180 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET_MSK 0x08000000
90181 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */
90182 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_CLR_MSK 0xf7ffffff
90183 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
90184 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_RESET 0x0
90185 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 field value from a register. */
90186 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
90187 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value suitable for setting the register. */
90188 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
90189 
90190 /*
90191  * Field : Mask Byte Control - mbc_4
90192  *
90193  * This array of bits are mask control bits for comparison of each of the MAC
90194  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90195  * received DA or SA with the contents of MAC Address116 high and low registers.
90196  * Each bit controls the masking of the bytes. You can filter a group of addresses
90197  * (known as group address filtering) by masking one or more bytes of the address.
90198  *
90199  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90200  *
90201  * Field Enumeration Values:
90202  *
90203  * Enum | Value | Description
90204  * :-----------------------------------------------|:------|:------------------------------------
90205  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90206  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90207  *
90208  * Field Access Macros:
90209  *
90210  */
90211 /*
90212  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4
90213  *
90214  * Byte is unmasked (i.e. is compared)
90215  */
90216 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED 0x0
90217 /*
90218  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4
90219  *
90220  * Byte is masked (i.e. not compared)
90221  */
90222 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED 0x1
90223 
90224 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
90225 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_LSB 28
90226 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
90227 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_MSB 28
90228 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
90229 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_WIDTH 1
90230 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */
90231 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET_MSK 0x10000000
90232 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */
90233 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_CLR_MSK 0xefffffff
90234 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
90235 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_RESET 0x0
90236 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 field value from a register. */
90237 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
90238 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value suitable for setting the register. */
90239 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
90240 
90241 /*
90242  * Field : Mask Byte Control - mbc_5
90243  *
90244  * This array of bits are mask control bits for comparison of each of the MAC
90245  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90246  * received DA or SA with the contents of MAC Address116 high and low registers.
90247  * Each bit controls the masking of the bytes. You can filter a group of addresses
90248  * (known as group address filtering) by masking one or more bytes of the address.
90249  *
90250  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90251  *
90252  * Field Enumeration Values:
90253  *
90254  * Enum | Value | Description
90255  * :-----------------------------------------------|:------|:------------------------------------
90256  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90257  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90258  *
90259  * Field Access Macros:
90260  *
90261  */
90262 /*
90263  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5
90264  *
90265  * Byte is unmasked (i.e. is compared)
90266  */
90267 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED 0x0
90268 /*
90269  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5
90270  *
90271  * Byte is masked (i.e. not compared)
90272  */
90273 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED 0x1
90274 
90275 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
90276 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_LSB 29
90277 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
90278 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_MSB 29
90279 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
90280 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_WIDTH 1
90281 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */
90282 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET_MSK 0x20000000
90283 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */
90284 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_CLR_MSK 0xdfffffff
90285 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
90286 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_RESET 0x0
90287 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 field value from a register. */
90288 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
90289 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value suitable for setting the register. */
90290 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
90291 
90292 /*
90293  * Field : Source Address - sa
90294  *
90295  * When this bit is enabled, the MAC Address116[47:0] is used to compare with the
90296  * SA fields of the received frame. When this bit is disabled, the MAC
90297  * Address116[47:0] is used to compare with the DA fields of the received frame.
90298  *
90299  * Field Enumeration Values:
90300  *
90301  * Enum | Value | Description
90302  * :-----------------------------------------|:------|:-----------------------------
90303  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
90304  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END | 0x1 | MAC address compare enabled
90305  *
90306  * Field Access Macros:
90307  *
90308  */
90309 /*
90310  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA
90311  *
90312  * MAC address compare disabled
90313  */
90314 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD 0x0
90315 /*
90316  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA
90317  *
90318  * MAC address compare enabled
90319  */
90320 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END 0x1
90321 
90322 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
90323 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_LSB 30
90324 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
90325 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_MSB 30
90326 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
90327 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_WIDTH 1
90328 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */
90329 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET_MSK 0x40000000
90330 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */
90331 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_CLR_MSK 0xbfffffff
90332 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
90333 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_RESET 0x0
90334 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA field value from a register. */
90335 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
90336 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value suitable for setting the register. */
90337 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
90338 
90339 /*
90340  * Field : Address Enable - ae
90341  *
90342  * When this bit is enabled, the address filter block uses the 117th MAC address
90343  * for perfect filtering. When this bit is disabled, the address filter block
90344  * ignores the address for filtering.
90345  *
90346  * Field Enumeration Values:
90347  *
90348  * Enum | Value | Description
90349  * :-----------------------------------------|:------|:--------------------------------------
90350  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
90351  * ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
90352  *
90353  * Field Access Macros:
90354  *
90355  */
90356 /*
90357  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
90358  *
90359  * Second MAC address filtering disabled
90360  */
90361 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD 0x0
90362 /*
90363  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
90364  *
90365  * Second MAC address filtering enabled
90366  */
90367 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END 0x1
90368 
90369 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
90370 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_LSB 31
90371 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
90372 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_MSB 31
90373 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
90374 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_WIDTH 1
90375 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
90376 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET_MSK 0x80000000
90377 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
90378 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_CLR_MSK 0x7fffffff
90379 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
90380 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_RESET 0x0
90381 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE field value from a register. */
90382 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
90383 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value suitable for setting the register. */
90384 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
90385 
90386 #ifndef __ASSEMBLY__
90387 /*
90388  * WARNING: The C register and register group struct declarations are provided for
90389  * convenience and illustrative purposes. They should, however, be used with
90390  * caution as the C language standard provides no guarantees about the alignment or
90391  * atomicity of device memory accesses. The recommended practice for writing
90392  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
90393  * alt_write_word() functions.
90394  *
90395  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH.
90396  */
90397 struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s
90398 {
90399  uint32_t addrhi : 16; /* MAC Address116 [47:32] */
90400  uint32_t : 8; /* *UNDEFINED* */
90401  uint32_t mbc_0 : 1; /* Mask Byte Control */
90402  uint32_t mbc_1 : 1; /* Mask Byte Control */
90403  uint32_t mbc_2 : 1; /* Mask Byte Control */
90404  uint32_t mbc_3 : 1; /* Mask Byte Control */
90405  uint32_t mbc_4 : 1; /* Mask Byte Control */
90406  uint32_t mbc_5 : 1; /* Mask Byte Control */
90407  uint32_t sa : 1; /* Source Address */
90408  uint32_t ae : 1; /* Address Enable */
90409 };
90410 
90411 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH. */
90412 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t;
90413 #endif /* __ASSEMBLY__ */
90414 
90415 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register from the beginning of the component. */
90416 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST 0xb20
90417 /* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register. */
90418 #define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST))
90419 
90420 /*
90421  * Register : Register 713 (MAC Address116 Low Register) - MAC_Address116_Low
90422  *
90423  * The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC
90424  * address of the station.
90425  *
90426  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
90427  * format.
90428  *
90429  * Register Layout
90430  *
90431  * Bits | Access | Reset | Description
90432  * :-------|:-------|:-----------|:----------------------
90433  * [31:0] | RW | 0xffffffff | MAC Address116 [31:0]
90434  *
90435  */
90436 /*
90437  * Field : MAC Address116 [31:0] - addrlo
90438  *
90439  * This field contains the lower 32 bits of the 117th 6-byte MAC address. The
90440  * content of this field is undefined until loaded by software after the
90441  * initialization process.
90442  *
90443  * Field Access Macros:
90444  *
90445  */
90446 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
90447 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_LSB 0
90448 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
90449 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_MSB 31
90450 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
90451 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_WIDTH 32
90452 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
90453 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET_MSK 0xffffffff
90454 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
90455 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_CLR_MSK 0x00000000
90456 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
90457 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_RESET 0xffffffff
90458 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO field value from a register. */
90459 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
90460 /* Produces a ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value suitable for setting the register. */
90461 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
90462 
90463 #ifndef __ASSEMBLY__
90464 /*
90465  * WARNING: The C register and register group struct declarations are provided for
90466  * convenience and illustrative purposes. They should, however, be used with
90467  * caution as the C language standard provides no guarantees about the alignment or
90468  * atomicity of device memory accesses. The recommended practice for writing
90469  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
90470  * alt_write_word() functions.
90471  *
90472  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW.
90473  */
90474 struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s
90475 {
90476  uint32_t addrlo : 32; /* MAC Address116 [31:0] */
90477 };
90478 
90479 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW. */
90480 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s ALT_EMAC_GMAC_MAC_ADDR116_LOW_t;
90481 #endif /* __ASSEMBLY__ */
90482 
90483 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register from the beginning of the component. */
90484 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST 0xb24
90485 /* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register. */
90486 #define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST))
90487 
90488 /*
90489  * Register : Register 714 (MAC Address117 High Register) - MAC_Address117_High
90490  *
90491  * The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC
90492  * address of the station. Because the MAC address registers are configured to be
90493  * double-synchronized to the (G)MII clock domains, the synchronization is
90494  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
90495  * endian mode) of the MAC Address117 Low Register are written. For proper
90496  * synchronization updates, the consecutive writes to this Address Low Register
90497  * should be performed after at least four clock cycles in the destination clock
90498  * domain.
90499  *
90500  * Note that all MAC Address High registers (except MAC Address0 High) have the
90501  * same format.
90502  *
90503  * Register Layout
90504  *
90505  * Bits | Access | Reset | Description
90506  * :--------|:-------|:-------|:-----------------------
90507  * [15:0] | RW | 0xffff | MAC Address117 [47:32]
90508  * [23:16] | ??? | 0x0 | *UNDEFINED*
90509  * [24] | RW | 0x0 | Mask Byte Control
90510  * [25] | RW | 0x0 | Mask Byte Control
90511  * [26] | RW | 0x0 | Mask Byte Control
90512  * [27] | RW | 0x0 | Mask Byte Control
90513  * [28] | RW | 0x0 | Mask Byte Control
90514  * [29] | RW | 0x0 | Mask Byte Control
90515  * [30] | RW | 0x0 | Source Address
90516  * [31] | RW | 0x0 | Address Enable
90517  *
90518  */
90519 /*
90520  * Field : MAC Address117 [47:32] - addrhi
90521  *
90522  * This field contains the upper 16 bits (47:32) of the 118th 6-byte MAC address.
90523  *
90524  * Field Access Macros:
90525  *
90526  */
90527 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
90528 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_LSB 0
90529 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
90530 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_MSB 15
90531 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
90532 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_WIDTH 16
90533 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
90534 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET_MSK 0x0000ffff
90535 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
90536 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_CLR_MSK 0xffff0000
90537 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
90538 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_RESET 0xffff
90539 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI field value from a register. */
90540 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
90541 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value suitable for setting the register. */
90542 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
90543 
90544 /*
90545  * Field : Mask Byte Control - mbc_0
90546  *
90547  * This array of bits are mask control bits for comparison of each of the MAC
90548  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90549  * received DA or SA with the contents of MAC Address117 high and low registers.
90550  * Each bit controls the masking of the bytes. You can filter a group of addresses
90551  * (known as group address filtering) by masking one or more bytes of the address.
90552  *
90553  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90554  *
90555  * Field Enumeration Values:
90556  *
90557  * Enum | Value | Description
90558  * :-----------------------------------------------|:------|:------------------------------------
90559  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90560  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90561  *
90562  * Field Access Macros:
90563  *
90564  */
90565 /*
90566  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0
90567  *
90568  * Byte is unmasked (i.e. is compared)
90569  */
90570 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED 0x0
90571 /*
90572  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0
90573  *
90574  * Byte is masked (i.e. not compared)
90575  */
90576 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED 0x1
90577 
90578 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
90579 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_LSB 24
90580 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
90581 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_MSB 24
90582 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
90583 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_WIDTH 1
90584 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */
90585 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET_MSK 0x01000000
90586 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */
90587 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_CLR_MSK 0xfeffffff
90588 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
90589 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_RESET 0x0
90590 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 field value from a register. */
90591 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
90592 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value suitable for setting the register. */
90593 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
90594 
90595 /*
90596  * Field : Mask Byte Control - mbc_1
90597  *
90598  * This array of bits are mask control bits for comparison of each of the MAC
90599  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90600  * received DA or SA with the contents of MAC Address117 high and low registers.
90601  * Each bit controls the masking of the bytes. You can filter a group of addresses
90602  * (known as group address filtering) by masking one or more bytes of the address.
90603  *
90604  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90605  *
90606  * Field Enumeration Values:
90607  *
90608  * Enum | Value | Description
90609  * :-----------------------------------------------|:------|:------------------------------------
90610  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90611  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90612  *
90613  * Field Access Macros:
90614  *
90615  */
90616 /*
90617  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1
90618  *
90619  * Byte is unmasked (i.e. is compared)
90620  */
90621 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED 0x0
90622 /*
90623  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1
90624  *
90625  * Byte is masked (i.e. not compared)
90626  */
90627 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED 0x1
90628 
90629 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
90630 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_LSB 25
90631 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
90632 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_MSB 25
90633 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
90634 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_WIDTH 1
90635 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */
90636 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET_MSK 0x02000000
90637 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */
90638 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_CLR_MSK 0xfdffffff
90639 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
90640 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_RESET 0x0
90641 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 field value from a register. */
90642 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
90643 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value suitable for setting the register. */
90644 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
90645 
90646 /*
90647  * Field : Mask Byte Control - mbc_2
90648  *
90649  * This array of bits are mask control bits for comparison of each of the MAC
90650  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90651  * received DA or SA with the contents of MAC Address117 high and low registers.
90652  * Each bit controls the masking of the bytes. You can filter a group of addresses
90653  * (known as group address filtering) by masking one or more bytes of the address.
90654  *
90655  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90656  *
90657  * Field Enumeration Values:
90658  *
90659  * Enum | Value | Description
90660  * :-----------------------------------------------|:------|:------------------------------------
90661  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90662  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90663  *
90664  * Field Access Macros:
90665  *
90666  */
90667 /*
90668  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2
90669  *
90670  * Byte is unmasked (i.e. is compared)
90671  */
90672 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED 0x0
90673 /*
90674  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2
90675  *
90676  * Byte is masked (i.e. not compared)
90677  */
90678 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED 0x1
90679 
90680 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
90681 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_LSB 26
90682 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
90683 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_MSB 26
90684 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
90685 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_WIDTH 1
90686 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */
90687 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET_MSK 0x04000000
90688 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */
90689 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_CLR_MSK 0xfbffffff
90690 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
90691 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_RESET 0x0
90692 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 field value from a register. */
90693 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
90694 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value suitable for setting the register. */
90695 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
90696 
90697 /*
90698  * Field : Mask Byte Control - mbc_3
90699  *
90700  * This array of bits are mask control bits for comparison of each of the MAC
90701  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90702  * received DA or SA with the contents of MAC Address117 high and low registers.
90703  * Each bit controls the masking of the bytes. You can filter a group of addresses
90704  * (known as group address filtering) by masking one or more bytes of the address.
90705  *
90706  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90707  *
90708  * Field Enumeration Values:
90709  *
90710  * Enum | Value | Description
90711  * :-----------------------------------------------|:------|:------------------------------------
90712  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90713  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90714  *
90715  * Field Access Macros:
90716  *
90717  */
90718 /*
90719  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3
90720  *
90721  * Byte is unmasked (i.e. is compared)
90722  */
90723 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED 0x0
90724 /*
90725  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3
90726  *
90727  * Byte is masked (i.e. not compared)
90728  */
90729 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED 0x1
90730 
90731 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
90732 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_LSB 27
90733 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
90734 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_MSB 27
90735 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
90736 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_WIDTH 1
90737 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */
90738 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET_MSK 0x08000000
90739 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */
90740 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_CLR_MSK 0xf7ffffff
90741 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
90742 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_RESET 0x0
90743 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 field value from a register. */
90744 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
90745 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value suitable for setting the register. */
90746 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
90747 
90748 /*
90749  * Field : Mask Byte Control - mbc_4
90750  *
90751  * This array of bits are mask control bits for comparison of each of the MAC
90752  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90753  * received DA or SA with the contents of MAC Address117 high and low registers.
90754  * Each bit controls the masking of the bytes. You can filter a group of addresses
90755  * (known as group address filtering) by masking one or more bytes of the address.
90756  *
90757  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90758  *
90759  * Field Enumeration Values:
90760  *
90761  * Enum | Value | Description
90762  * :-----------------------------------------------|:------|:------------------------------------
90763  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90764  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90765  *
90766  * Field Access Macros:
90767  *
90768  */
90769 /*
90770  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4
90771  *
90772  * Byte is unmasked (i.e. is compared)
90773  */
90774 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED 0x0
90775 /*
90776  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4
90777  *
90778  * Byte is masked (i.e. not compared)
90779  */
90780 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED 0x1
90781 
90782 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
90783 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_LSB 28
90784 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
90785 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_MSB 28
90786 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
90787 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_WIDTH 1
90788 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */
90789 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET_MSK 0x10000000
90790 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */
90791 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_CLR_MSK 0xefffffff
90792 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
90793 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_RESET 0x0
90794 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 field value from a register. */
90795 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
90796 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value suitable for setting the register. */
90797 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
90798 
90799 /*
90800  * Field : Mask Byte Control - mbc_5
90801  *
90802  * This array of bits are mask control bits for comparison of each of the MAC
90803  * Address bytes. When masked, the MAC does not compare the corresponding byte of
90804  * received DA or SA with the contents of MAC Address117 high and low registers.
90805  * Each bit controls the masking of the bytes. You can filter a group of addresses
90806  * (known as group address filtering) by masking one or more bytes of the address.
90807  *
90808  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
90809  *
90810  * Field Enumeration Values:
90811  *
90812  * Enum | Value | Description
90813  * :-----------------------------------------------|:------|:------------------------------------
90814  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
90815  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
90816  *
90817  * Field Access Macros:
90818  *
90819  */
90820 /*
90821  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5
90822  *
90823  * Byte is unmasked (i.e. is compared)
90824  */
90825 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED 0x0
90826 /*
90827  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5
90828  *
90829  * Byte is masked (i.e. not compared)
90830  */
90831 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED 0x1
90832 
90833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
90834 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_LSB 29
90835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
90836 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_MSB 29
90837 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
90838 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_WIDTH 1
90839 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */
90840 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET_MSK 0x20000000
90841 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */
90842 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_CLR_MSK 0xdfffffff
90843 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
90844 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_RESET 0x0
90845 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 field value from a register. */
90846 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
90847 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value suitable for setting the register. */
90848 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
90849 
90850 /*
90851  * Field : Source Address - sa
90852  *
90853  * When this bit is enabled, the MAC Address117[47:0] is used to compare with the
90854  * SA fields of the received frame. When this bit is disabled, the MAC
90855  * Address117[47:0] is used to compare with the DA fields of the received frame.
90856  *
90857  * Field Enumeration Values:
90858  *
90859  * Enum | Value | Description
90860  * :-----------------------------------------|:------|:-----------------------------
90861  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
90862  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END | 0x1 | MAC address compare enabled
90863  *
90864  * Field Access Macros:
90865  *
90866  */
90867 /*
90868  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA
90869  *
90870  * MAC address compare disabled
90871  */
90872 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD 0x0
90873 /*
90874  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA
90875  *
90876  * MAC address compare enabled
90877  */
90878 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END 0x1
90879 
90880 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
90881 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_LSB 30
90882 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
90883 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_MSB 30
90884 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
90885 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_WIDTH 1
90886 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */
90887 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET_MSK 0x40000000
90888 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */
90889 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_CLR_MSK 0xbfffffff
90890 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
90891 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_RESET 0x0
90892 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA field value from a register. */
90893 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
90894 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value suitable for setting the register. */
90895 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
90896 
90897 /*
90898  * Field : Address Enable - ae
90899  *
90900  * When this bit is enabled, the address filter block uses the 118th MAC address
90901  * for perfect filtering. When this bit is disabled, the address filter block
90902  * ignores the address for filtering.
90903  *
90904  * Field Enumeration Values:
90905  *
90906  * Enum | Value | Description
90907  * :-----------------------------------------|:------|:--------------------------------------
90908  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
90909  * ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
90910  *
90911  * Field Access Macros:
90912  *
90913  */
90914 /*
90915  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
90916  *
90917  * Second MAC address filtering disabled
90918  */
90919 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD 0x0
90920 /*
90921  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
90922  *
90923  * Second MAC address filtering enabled
90924  */
90925 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END 0x1
90926 
90927 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
90928 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_LSB 31
90929 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
90930 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_MSB 31
90931 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
90932 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_WIDTH 1
90933 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
90934 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET_MSK 0x80000000
90935 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
90936 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_CLR_MSK 0x7fffffff
90937 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
90938 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_RESET 0x0
90939 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE field value from a register. */
90940 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
90941 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value suitable for setting the register. */
90942 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
90943 
90944 #ifndef __ASSEMBLY__
90945 /*
90946  * WARNING: The C register and register group struct declarations are provided for
90947  * convenience and illustrative purposes. They should, however, be used with
90948  * caution as the C language standard provides no guarantees about the alignment or
90949  * atomicity of device memory accesses. The recommended practice for writing
90950  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
90951  * alt_write_word() functions.
90952  *
90953  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH.
90954  */
90955 struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s
90956 {
90957  uint32_t addrhi : 16; /* MAC Address117 [47:32] */
90958  uint32_t : 8; /* *UNDEFINED* */
90959  uint32_t mbc_0 : 1; /* Mask Byte Control */
90960  uint32_t mbc_1 : 1; /* Mask Byte Control */
90961  uint32_t mbc_2 : 1; /* Mask Byte Control */
90962  uint32_t mbc_3 : 1; /* Mask Byte Control */
90963  uint32_t mbc_4 : 1; /* Mask Byte Control */
90964  uint32_t mbc_5 : 1; /* Mask Byte Control */
90965  uint32_t sa : 1; /* Source Address */
90966  uint32_t ae : 1; /* Address Enable */
90967 };
90968 
90969 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH. */
90970 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t;
90971 #endif /* __ASSEMBLY__ */
90972 
90973 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register from the beginning of the component. */
90974 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST 0xb28
90975 /* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register. */
90976 #define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST))
90977 
90978 /*
90979  * Register : Register 715 (MAC Address117 Low Register) - MAC_Address117_Low
90980  *
90981  * The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC
90982  * address of the station.
90983  *
90984  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
90985  * format.
90986  *
90987  * Register Layout
90988  *
90989  * Bits | Access | Reset | Description
90990  * :-------|:-------|:-----------|:----------------------
90991  * [31:0] | RW | 0xffffffff | MAC Address117 [31:0]
90992  *
90993  */
90994 /*
90995  * Field : MAC Address117 [31:0] - addrlo
90996  *
90997  * This field contains the lower 32 bits of the 118th 6-byte MAC address. The
90998  * content of this field is undefined until loaded by software after the
90999  * initialization process.
91000  *
91001  * Field Access Macros:
91002  *
91003  */
91004 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
91005 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_LSB 0
91006 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
91007 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_MSB 31
91008 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
91009 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_WIDTH 32
91010 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
91011 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET_MSK 0xffffffff
91012 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
91013 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_CLR_MSK 0x00000000
91014 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
91015 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_RESET 0xffffffff
91016 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO field value from a register. */
91017 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
91018 /* Produces a ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value suitable for setting the register. */
91019 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
91020 
91021 #ifndef __ASSEMBLY__
91022 /*
91023  * WARNING: The C register and register group struct declarations are provided for
91024  * convenience and illustrative purposes. They should, however, be used with
91025  * caution as the C language standard provides no guarantees about the alignment or
91026  * atomicity of device memory accesses. The recommended practice for writing
91027  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91028  * alt_write_word() functions.
91029  *
91030  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW.
91031  */
91032 struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s
91033 {
91034  uint32_t addrlo : 32; /* MAC Address117 [31:0] */
91035 };
91036 
91037 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW. */
91038 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s ALT_EMAC_GMAC_MAC_ADDR117_LOW_t;
91039 #endif /* __ASSEMBLY__ */
91040 
91041 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register from the beginning of the component. */
91042 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST 0xb2c
91043 /* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register. */
91044 #define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST))
91045 
91046 /*
91047  * Register : Register 716 (MAC Address118 High Register) - MAC_Address118_High
91048  *
91049  * The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC
91050  * address of the station. Because the MAC address registers are configured to be
91051  * double-synchronized to the (G)MII clock domains, the synchronization is
91052  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
91053  * endian mode) of the MAC Address118 Low Register are written. For proper
91054  * synchronization updates, the consecutive writes to this Address Low Register
91055  * should be performed after at least four clock cycles in the destination clock
91056  * domain.
91057  *
91058  * Note that all MAC Address High registers (except MAC Address0 High) have the
91059  * same format.
91060  *
91061  * Register Layout
91062  *
91063  * Bits | Access | Reset | Description
91064  * :--------|:-------|:-------|:-----------------------
91065  * [15:0] | RW | 0xffff | MAC Address118 [47:32]
91066  * [23:16] | ??? | 0x0 | *UNDEFINED*
91067  * [24] | RW | 0x0 | Mask Byte Control
91068  * [25] | RW | 0x0 | Mask Byte Control
91069  * [26] | RW | 0x0 | Mask Byte Control
91070  * [27] | RW | 0x0 | Mask Byte Control
91071  * [28] | RW | 0x0 | Mask Byte Control
91072  * [29] | RW | 0x0 | Mask Byte Control
91073  * [30] | RW | 0x0 | Source Address
91074  * [31] | RW | 0x0 | Address Enable
91075  *
91076  */
91077 /*
91078  * Field : MAC Address118 [47:32] - addrhi
91079  *
91080  * This field contains the upper 16 bits (47:32) of the 119th 6-byte MAC address.
91081  *
91082  * Field Access Macros:
91083  *
91084  */
91085 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
91086 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_LSB 0
91087 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
91088 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_MSB 15
91089 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
91090 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_WIDTH 16
91091 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
91092 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET_MSK 0x0000ffff
91093 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
91094 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_CLR_MSK 0xffff0000
91095 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
91096 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_RESET 0xffff
91097 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI field value from a register. */
91098 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
91099 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value suitable for setting the register. */
91100 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
91101 
91102 /*
91103  * Field : Mask Byte Control - mbc_0
91104  *
91105  * This array of bits are mask control bits for comparison of each of the MAC
91106  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91107  * received DA or SA with the contents of MAC Address118 high and low registers.
91108  * Each bit controls the masking of the bytes. You can filter a group of addresses
91109  * (known as group address filtering) by masking one or more bytes of the address.
91110  *
91111  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91112  *
91113  * Field Enumeration Values:
91114  *
91115  * Enum | Value | Description
91116  * :-----------------------------------------------|:------|:------------------------------------
91117  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91118  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91119  *
91120  * Field Access Macros:
91121  *
91122  */
91123 /*
91124  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0
91125  *
91126  * Byte is unmasked (i.e. is compared)
91127  */
91128 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED 0x0
91129 /*
91130  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0
91131  *
91132  * Byte is masked (i.e. not compared)
91133  */
91134 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED 0x1
91135 
91136 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
91137 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_LSB 24
91138 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
91139 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_MSB 24
91140 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
91141 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_WIDTH 1
91142 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */
91143 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET_MSK 0x01000000
91144 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */
91145 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_CLR_MSK 0xfeffffff
91146 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
91147 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_RESET 0x0
91148 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 field value from a register. */
91149 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
91150 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value suitable for setting the register. */
91151 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
91152 
91153 /*
91154  * Field : Mask Byte Control - mbc_1
91155  *
91156  * This array of bits are mask control bits for comparison of each of the MAC
91157  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91158  * received DA or SA with the contents of MAC Address118 high and low registers.
91159  * Each bit controls the masking of the bytes. You can filter a group of addresses
91160  * (known as group address filtering) by masking one or more bytes of the address.
91161  *
91162  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91163  *
91164  * Field Enumeration Values:
91165  *
91166  * Enum | Value | Description
91167  * :-----------------------------------------------|:------|:------------------------------------
91168  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91169  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91170  *
91171  * Field Access Macros:
91172  *
91173  */
91174 /*
91175  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1
91176  *
91177  * Byte is unmasked (i.e. is compared)
91178  */
91179 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED 0x0
91180 /*
91181  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1
91182  *
91183  * Byte is masked (i.e. not compared)
91184  */
91185 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED 0x1
91186 
91187 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
91188 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_LSB 25
91189 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
91190 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_MSB 25
91191 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
91192 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_WIDTH 1
91193 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */
91194 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET_MSK 0x02000000
91195 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */
91196 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_CLR_MSK 0xfdffffff
91197 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
91198 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_RESET 0x0
91199 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 field value from a register. */
91200 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
91201 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value suitable for setting the register. */
91202 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
91203 
91204 /*
91205  * Field : Mask Byte Control - mbc_2
91206  *
91207  * This array of bits are mask control bits for comparison of each of the MAC
91208  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91209  * received DA or SA with the contents of MAC Address118 high and low registers.
91210  * Each bit controls the masking of the bytes. You can filter a group of addresses
91211  * (known as group address filtering) by masking one or more bytes of the address.
91212  *
91213  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91214  *
91215  * Field Enumeration Values:
91216  *
91217  * Enum | Value | Description
91218  * :-----------------------------------------------|:------|:------------------------------------
91219  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91220  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91221  *
91222  * Field Access Macros:
91223  *
91224  */
91225 /*
91226  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2
91227  *
91228  * Byte is unmasked (i.e. is compared)
91229  */
91230 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED 0x0
91231 /*
91232  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2
91233  *
91234  * Byte is masked (i.e. not compared)
91235  */
91236 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED 0x1
91237 
91238 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
91239 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_LSB 26
91240 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
91241 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_MSB 26
91242 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
91243 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_WIDTH 1
91244 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */
91245 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET_MSK 0x04000000
91246 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */
91247 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_CLR_MSK 0xfbffffff
91248 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
91249 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_RESET 0x0
91250 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 field value from a register. */
91251 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
91252 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value suitable for setting the register. */
91253 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
91254 
91255 /*
91256  * Field : Mask Byte Control - mbc_3
91257  *
91258  * This array of bits are mask control bits for comparison of each of the MAC
91259  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91260  * received DA or SA with the contents of MAC Address118 high and low registers.
91261  * Each bit controls the masking of the bytes. You can filter a group of addresses
91262  * (known as group address filtering) by masking one or more bytes of the address.
91263  *
91264  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91265  *
91266  * Field Enumeration Values:
91267  *
91268  * Enum | Value | Description
91269  * :-----------------------------------------------|:------|:------------------------------------
91270  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91271  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91272  *
91273  * Field Access Macros:
91274  *
91275  */
91276 /*
91277  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3
91278  *
91279  * Byte is unmasked (i.e. is compared)
91280  */
91281 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED 0x0
91282 /*
91283  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3
91284  *
91285  * Byte is masked (i.e. not compared)
91286  */
91287 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED 0x1
91288 
91289 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
91290 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_LSB 27
91291 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
91292 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_MSB 27
91293 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
91294 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_WIDTH 1
91295 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */
91296 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET_MSK 0x08000000
91297 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */
91298 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_CLR_MSK 0xf7ffffff
91299 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
91300 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_RESET 0x0
91301 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 field value from a register. */
91302 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
91303 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value suitable for setting the register. */
91304 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
91305 
91306 /*
91307  * Field : Mask Byte Control - mbc_4
91308  *
91309  * This array of bits are mask control bits for comparison of each of the MAC
91310  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91311  * received DA or SA with the contents of MAC Address118 high and low registers.
91312  * Each bit controls the masking of the bytes. You can filter a group of addresses
91313  * (known as group address filtering) by masking one or more bytes of the address.
91314  *
91315  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91316  *
91317  * Field Enumeration Values:
91318  *
91319  * Enum | Value | Description
91320  * :-----------------------------------------------|:------|:------------------------------------
91321  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91322  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91323  *
91324  * Field Access Macros:
91325  *
91326  */
91327 /*
91328  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4
91329  *
91330  * Byte is unmasked (i.e. is compared)
91331  */
91332 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED 0x0
91333 /*
91334  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4
91335  *
91336  * Byte is masked (i.e. not compared)
91337  */
91338 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED 0x1
91339 
91340 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
91341 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_LSB 28
91342 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
91343 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_MSB 28
91344 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
91345 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_WIDTH 1
91346 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */
91347 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET_MSK 0x10000000
91348 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */
91349 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_CLR_MSK 0xefffffff
91350 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
91351 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_RESET 0x0
91352 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 field value from a register. */
91353 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
91354 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value suitable for setting the register. */
91355 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
91356 
91357 /*
91358  * Field : Mask Byte Control - mbc_5
91359  *
91360  * This array of bits are mask control bits for comparison of each of the MAC
91361  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91362  * received DA or SA with the contents of MAC Address118 high and low registers.
91363  * Each bit controls the masking of the bytes. You can filter a group of addresses
91364  * (known as group address filtering) by masking one or more bytes of the address.
91365  *
91366  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91367  *
91368  * Field Enumeration Values:
91369  *
91370  * Enum | Value | Description
91371  * :-----------------------------------------------|:------|:------------------------------------
91372  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91373  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91374  *
91375  * Field Access Macros:
91376  *
91377  */
91378 /*
91379  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5
91380  *
91381  * Byte is unmasked (i.e. is compared)
91382  */
91383 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED 0x0
91384 /*
91385  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5
91386  *
91387  * Byte is masked (i.e. not compared)
91388  */
91389 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED 0x1
91390 
91391 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
91392 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_LSB 29
91393 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
91394 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_MSB 29
91395 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
91396 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_WIDTH 1
91397 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */
91398 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET_MSK 0x20000000
91399 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */
91400 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_CLR_MSK 0xdfffffff
91401 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
91402 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_RESET 0x0
91403 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 field value from a register. */
91404 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
91405 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value suitable for setting the register. */
91406 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
91407 
91408 /*
91409  * Field : Source Address - sa
91410  *
91411  * When this bit is enabled, the MAC Address118[47:0] is used to compare with the
91412  * SA fields of the received frame. When this bit is disabled, the MAC
91413  * Address118[47:0] is used to compare with the DA fields of the received frame.
91414  *
91415  * Field Enumeration Values:
91416  *
91417  * Enum | Value | Description
91418  * :-----------------------------------------|:------|:-----------------------------
91419  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
91420  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END | 0x1 | MAC address compare enabled
91421  *
91422  * Field Access Macros:
91423  *
91424  */
91425 /*
91426  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA
91427  *
91428  * MAC address compare disabled
91429  */
91430 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD 0x0
91431 /*
91432  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA
91433  *
91434  * MAC address compare enabled
91435  */
91436 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END 0x1
91437 
91438 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
91439 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_LSB 30
91440 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
91441 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_MSB 30
91442 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
91443 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_WIDTH 1
91444 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */
91445 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET_MSK 0x40000000
91446 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */
91447 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_CLR_MSK 0xbfffffff
91448 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
91449 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_RESET 0x0
91450 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA field value from a register. */
91451 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
91452 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value suitable for setting the register. */
91453 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
91454 
91455 /*
91456  * Field : Address Enable - ae
91457  *
91458  * When this bit is enabled, the address filter block uses the 119th MAC address
91459  * for perfect filtering. When this bit is disabled, the address filter block
91460  * ignores the address for filtering.
91461  *
91462  * Field Enumeration Values:
91463  *
91464  * Enum | Value | Description
91465  * :-----------------------------------------|:------|:--------------------------------------
91466  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
91467  * ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
91468  *
91469  * Field Access Macros:
91470  *
91471  */
91472 /*
91473  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
91474  *
91475  * Second MAC address filtering disabled
91476  */
91477 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD 0x0
91478 /*
91479  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
91480  *
91481  * Second MAC address filtering enabled
91482  */
91483 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END 0x1
91484 
91485 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
91486 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_LSB 31
91487 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
91488 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_MSB 31
91489 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
91490 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_WIDTH 1
91491 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
91492 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET_MSK 0x80000000
91493 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
91494 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_CLR_MSK 0x7fffffff
91495 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
91496 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_RESET 0x0
91497 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE field value from a register. */
91498 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
91499 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value suitable for setting the register. */
91500 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
91501 
91502 #ifndef __ASSEMBLY__
91503 /*
91504  * WARNING: The C register and register group struct declarations are provided for
91505  * convenience and illustrative purposes. They should, however, be used with
91506  * caution as the C language standard provides no guarantees about the alignment or
91507  * atomicity of device memory accesses. The recommended practice for writing
91508  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91509  * alt_write_word() functions.
91510  *
91511  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH.
91512  */
91513 struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s
91514 {
91515  uint32_t addrhi : 16; /* MAC Address118 [47:32] */
91516  uint32_t : 8; /* *UNDEFINED* */
91517  uint32_t mbc_0 : 1; /* Mask Byte Control */
91518  uint32_t mbc_1 : 1; /* Mask Byte Control */
91519  uint32_t mbc_2 : 1; /* Mask Byte Control */
91520  uint32_t mbc_3 : 1; /* Mask Byte Control */
91521  uint32_t mbc_4 : 1; /* Mask Byte Control */
91522  uint32_t mbc_5 : 1; /* Mask Byte Control */
91523  uint32_t sa : 1; /* Source Address */
91524  uint32_t ae : 1; /* Address Enable */
91525 };
91526 
91527 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH. */
91528 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t;
91529 #endif /* __ASSEMBLY__ */
91530 
91531 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register from the beginning of the component. */
91532 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST 0xb30
91533 /* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register. */
91534 #define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST))
91535 
91536 /*
91537  * Register : Register 717 (MAC Address118 Low Register) - MAC_Address118_Low
91538  *
91539  * The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC
91540  * address of the station.
91541  *
91542  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
91543  * format.
91544  *
91545  * Register Layout
91546  *
91547  * Bits | Access | Reset | Description
91548  * :-------|:-------|:-----------|:----------------------
91549  * [31:0] | RW | 0xffffffff | MAC Address118 [31:0]
91550  *
91551  */
91552 /*
91553  * Field : MAC Address118 [31:0] - addrlo
91554  *
91555  * This field contains the lower 32 bits of the 119th 6-byte MAC address. The
91556  * content of this field is undefined until loaded by software after the
91557  * initialization process.
91558  *
91559  * Field Access Macros:
91560  *
91561  */
91562 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
91563 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_LSB 0
91564 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
91565 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_MSB 31
91566 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
91567 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_WIDTH 32
91568 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
91569 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET_MSK 0xffffffff
91570 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
91571 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_CLR_MSK 0x00000000
91572 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
91573 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_RESET 0xffffffff
91574 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO field value from a register. */
91575 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
91576 /* Produces a ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value suitable for setting the register. */
91577 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
91578 
91579 #ifndef __ASSEMBLY__
91580 /*
91581  * WARNING: The C register and register group struct declarations are provided for
91582  * convenience and illustrative purposes. They should, however, be used with
91583  * caution as the C language standard provides no guarantees about the alignment or
91584  * atomicity of device memory accesses. The recommended practice for writing
91585  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
91586  * alt_write_word() functions.
91587  *
91588  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW.
91589  */
91590 struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s
91591 {
91592  uint32_t addrlo : 32; /* MAC Address118 [31:0] */
91593 };
91594 
91595 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW. */
91596 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s ALT_EMAC_GMAC_MAC_ADDR118_LOW_t;
91597 #endif /* __ASSEMBLY__ */
91598 
91599 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register from the beginning of the component. */
91600 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST 0xb34
91601 /* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register. */
91602 #define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST))
91603 
91604 /*
91605  * Register : Register 718 (MAC Address119 High Register) - MAC_Address119_High
91606  *
91607  * The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC
91608  * address of the station. Because the MAC address registers are configured to be
91609  * double-synchronized to the (G)MII clock domains, the synchronization is
91610  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
91611  * endian mode) of the MAC Address119 Low Register are written. For proper
91612  * synchronization updates, the consecutive writes to this Address Low Register
91613  * should be performed after at least four clock cycles in the destination clock
91614  * domain.
91615  *
91616  * Note that all MAC Address High registers (except MAC Address0 High) have the
91617  * same format.
91618  *
91619  * Register Layout
91620  *
91621  * Bits | Access | Reset | Description
91622  * :--------|:-------|:-------|:-----------------------
91623  * [15:0] | RW | 0xffff | MAC Address119 [47:32]
91624  * [23:16] | ??? | 0x0 | *UNDEFINED*
91625  * [24] | RW | 0x0 | Mask Byte Control
91626  * [25] | RW | 0x0 | Mask Byte Control
91627  * [26] | RW | 0x0 | Mask Byte Control
91628  * [27] | RW | 0x0 | Mask Byte Control
91629  * [28] | RW | 0x0 | Mask Byte Control
91630  * [29] | RW | 0x0 | Mask Byte Control
91631  * [30] | RW | 0x0 | Source Address
91632  * [31] | RW | 0x0 | Address Enable
91633  *
91634  */
91635 /*
91636  * Field : MAC Address119 [47:32] - addrhi
91637  *
91638  * This field contains the upper 16 bits (47:32) of the 120th 6-byte MAC address.
91639  *
91640  * Field Access Macros:
91641  *
91642  */
91643 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
91644 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_LSB 0
91645 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
91646 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_MSB 15
91647 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
91648 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_WIDTH 16
91649 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
91650 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET_MSK 0x0000ffff
91651 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
91652 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_CLR_MSK 0xffff0000
91653 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
91654 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_RESET 0xffff
91655 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI field value from a register. */
91656 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
91657 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value suitable for setting the register. */
91658 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
91659 
91660 /*
91661  * Field : Mask Byte Control - mbc_0
91662  *
91663  * This array of bits are mask control bits for comparison of each of the MAC
91664  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91665  * received DA or SA with the contents of MAC Address119 high and low registers.
91666  * Each bit controls the masking of the bytes. You can filter a group of addresses
91667  * (known as group address filtering) by masking one or more bytes of the address.
91668  *
91669  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91670  *
91671  * Field Enumeration Values:
91672  *
91673  * Enum | Value | Description
91674  * :-----------------------------------------------|:------|:------------------------------------
91675  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91676  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91677  *
91678  * Field Access Macros:
91679  *
91680  */
91681 /*
91682  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0
91683  *
91684  * Byte is unmasked (i.e. is compared)
91685  */
91686 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED 0x0
91687 /*
91688  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0
91689  *
91690  * Byte is masked (i.e. not compared)
91691  */
91692 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED 0x1
91693 
91694 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
91695 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_LSB 24
91696 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
91697 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_MSB 24
91698 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
91699 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_WIDTH 1
91700 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */
91701 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET_MSK 0x01000000
91702 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */
91703 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_CLR_MSK 0xfeffffff
91704 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
91705 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_RESET 0x0
91706 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 field value from a register. */
91707 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
91708 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value suitable for setting the register. */
91709 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
91710 
91711 /*
91712  * Field : Mask Byte Control - mbc_1
91713  *
91714  * This array of bits are mask control bits for comparison of each of the MAC
91715  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91716  * received DA or SA with the contents of MAC Address119 high and low registers.
91717  * Each bit controls the masking of the bytes. You can filter a group of addresses
91718  * (known as group address filtering) by masking one or more bytes of the address.
91719  *
91720  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91721  *
91722  * Field Enumeration Values:
91723  *
91724  * Enum | Value | Description
91725  * :-----------------------------------------------|:------|:------------------------------------
91726  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91727  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91728  *
91729  * Field Access Macros:
91730  *
91731  */
91732 /*
91733  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1
91734  *
91735  * Byte is unmasked (i.e. is compared)
91736  */
91737 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED 0x0
91738 /*
91739  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1
91740  *
91741  * Byte is masked (i.e. not compared)
91742  */
91743 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED 0x1
91744 
91745 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
91746 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_LSB 25
91747 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
91748 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_MSB 25
91749 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
91750 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_WIDTH 1
91751 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */
91752 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET_MSK 0x02000000
91753 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */
91754 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_CLR_MSK 0xfdffffff
91755 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
91756 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_RESET 0x0
91757 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 field value from a register. */
91758 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
91759 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value suitable for setting the register. */
91760 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
91761 
91762 /*
91763  * Field : Mask Byte Control - mbc_2
91764  *
91765  * This array of bits are mask control bits for comparison of each of the MAC
91766  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91767  * received DA or SA with the contents of MAC Address119 high and low registers.
91768  * Each bit controls the masking of the bytes. You can filter a group of addresses
91769  * (known as group address filtering) by masking one or more bytes of the address.
91770  *
91771  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91772  *
91773  * Field Enumeration Values:
91774  *
91775  * Enum | Value | Description
91776  * :-----------------------------------------------|:------|:------------------------------------
91777  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91778  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91779  *
91780  * Field Access Macros:
91781  *
91782  */
91783 /*
91784  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2
91785  *
91786  * Byte is unmasked (i.e. is compared)
91787  */
91788 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED 0x0
91789 /*
91790  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2
91791  *
91792  * Byte is masked (i.e. not compared)
91793  */
91794 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED 0x1
91795 
91796 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
91797 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_LSB 26
91798 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
91799 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_MSB 26
91800 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
91801 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_WIDTH 1
91802 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */
91803 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET_MSK 0x04000000
91804 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */
91805 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_CLR_MSK 0xfbffffff
91806 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
91807 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_RESET 0x0
91808 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 field value from a register. */
91809 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
91810 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value suitable for setting the register. */
91811 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
91812 
91813 /*
91814  * Field : Mask Byte Control - mbc_3
91815  *
91816  * This array of bits are mask control bits for comparison of each of the MAC
91817  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91818  * received DA or SA with the contents of MAC Address119 high and low registers.
91819  * Each bit controls the masking of the bytes. You can filter a group of addresses
91820  * (known as group address filtering) by masking one or more bytes of the address.
91821  *
91822  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91823  *
91824  * Field Enumeration Values:
91825  *
91826  * Enum | Value | Description
91827  * :-----------------------------------------------|:------|:------------------------------------
91828  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91829  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91830  *
91831  * Field Access Macros:
91832  *
91833  */
91834 /*
91835  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3
91836  *
91837  * Byte is unmasked (i.e. is compared)
91838  */
91839 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED 0x0
91840 /*
91841  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3
91842  *
91843  * Byte is masked (i.e. not compared)
91844  */
91845 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED 0x1
91846 
91847 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
91848 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_LSB 27
91849 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
91850 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_MSB 27
91851 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
91852 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_WIDTH 1
91853 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */
91854 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET_MSK 0x08000000
91855 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */
91856 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_CLR_MSK 0xf7ffffff
91857 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
91858 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_RESET 0x0
91859 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 field value from a register. */
91860 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
91861 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value suitable for setting the register. */
91862 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
91863 
91864 /*
91865  * Field : Mask Byte Control - mbc_4
91866  *
91867  * This array of bits are mask control bits for comparison of each of the MAC
91868  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91869  * received DA or SA with the contents of MAC Address119 high and low registers.
91870  * Each bit controls the masking of the bytes. You can filter a group of addresses
91871  * (known as group address filtering) by masking one or more bytes of the address.
91872  *
91873  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91874  *
91875  * Field Enumeration Values:
91876  *
91877  * Enum | Value | Description
91878  * :-----------------------------------------------|:------|:------------------------------------
91879  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91880  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91881  *
91882  * Field Access Macros:
91883  *
91884  */
91885 /*
91886  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4
91887  *
91888  * Byte is unmasked (i.e. is compared)
91889  */
91890 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED 0x0
91891 /*
91892  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4
91893  *
91894  * Byte is masked (i.e. not compared)
91895  */
91896 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED 0x1
91897 
91898 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
91899 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_LSB 28
91900 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
91901 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_MSB 28
91902 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
91903 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_WIDTH 1
91904 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */
91905 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET_MSK 0x10000000
91906 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */
91907 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_CLR_MSK 0xefffffff
91908 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
91909 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_RESET 0x0
91910 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 field value from a register. */
91911 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
91912 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value suitable for setting the register. */
91913 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
91914 
91915 /*
91916  * Field : Mask Byte Control - mbc_5
91917  *
91918  * This array of bits are mask control bits for comparison of each of the MAC
91919  * Address bytes. When masked, the MAC does not compare the corresponding byte of
91920  * received DA or SA with the contents of MAC Address119 high and low registers.
91921  * Each bit controls the masking of the bytes. You can filter a group of addresses
91922  * (known as group address filtering) by masking one or more bytes of the address.
91923  *
91924  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
91925  *
91926  * Field Enumeration Values:
91927  *
91928  * Enum | Value | Description
91929  * :-----------------------------------------------|:------|:------------------------------------
91930  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
91931  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
91932  *
91933  * Field Access Macros:
91934  *
91935  */
91936 /*
91937  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5
91938  *
91939  * Byte is unmasked (i.e. is compared)
91940  */
91941 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED 0x0
91942 /*
91943  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5
91944  *
91945  * Byte is masked (i.e. not compared)
91946  */
91947 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED 0x1
91948 
91949 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
91950 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_LSB 29
91951 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
91952 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_MSB 29
91953 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
91954 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_WIDTH 1
91955 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */
91956 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET_MSK 0x20000000
91957 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */
91958 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_CLR_MSK 0xdfffffff
91959 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
91960 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_RESET 0x0
91961 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 field value from a register. */
91962 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
91963 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value suitable for setting the register. */
91964 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
91965 
91966 /*
91967  * Field : Source Address - sa
91968  *
91969  * When this bit is enabled, the MAC Address119[47:0] is used to compare with the
91970  * SA fields of the received frame. When this bit is disabled, the MAC
91971  * Address119[47:0] is used to compare with the DA fields of the received frame.
91972  *
91973  * Field Enumeration Values:
91974  *
91975  * Enum | Value | Description
91976  * :-----------------------------------------|:------|:-----------------------------
91977  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
91978  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END | 0x1 | MAC address compare enabled
91979  *
91980  * Field Access Macros:
91981  *
91982  */
91983 /*
91984  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA
91985  *
91986  * MAC address compare disabled
91987  */
91988 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD 0x0
91989 /*
91990  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA
91991  *
91992  * MAC address compare enabled
91993  */
91994 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END 0x1
91995 
91996 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
91997 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_LSB 30
91998 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
91999 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_MSB 30
92000 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
92001 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_WIDTH 1
92002 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */
92003 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET_MSK 0x40000000
92004 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */
92005 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_CLR_MSK 0xbfffffff
92006 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
92007 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_RESET 0x0
92008 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA field value from a register. */
92009 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
92010 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value suitable for setting the register. */
92011 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
92012 
92013 /*
92014  * Field : Address Enable - ae
92015  *
92016  * When this bit is enabled, the address filter block uses the 120th MAC address
92017  * for perfect filtering. When this bit is disabled, the address filter block
92018  * ignores the address for filtering.
92019  *
92020  * Field Enumeration Values:
92021  *
92022  * Enum | Value | Description
92023  * :-----------------------------------------|:------|:--------------------------------------
92024  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
92025  * ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
92026  *
92027  * Field Access Macros:
92028  *
92029  */
92030 /*
92031  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
92032  *
92033  * Second MAC address filtering disabled
92034  */
92035 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD 0x0
92036 /*
92037  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
92038  *
92039  * Second MAC address filtering enabled
92040  */
92041 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END 0x1
92042 
92043 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
92044 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_LSB 31
92045 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
92046 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_MSB 31
92047 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
92048 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_WIDTH 1
92049 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
92050 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET_MSK 0x80000000
92051 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
92052 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_CLR_MSK 0x7fffffff
92053 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
92054 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_RESET 0x0
92055 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE field value from a register. */
92056 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
92057 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value suitable for setting the register. */
92058 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
92059 
92060 #ifndef __ASSEMBLY__
92061 /*
92062  * WARNING: The C register and register group struct declarations are provided for
92063  * convenience and illustrative purposes. They should, however, be used with
92064  * caution as the C language standard provides no guarantees about the alignment or
92065  * atomicity of device memory accesses. The recommended practice for writing
92066  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
92067  * alt_write_word() functions.
92068  *
92069  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH.
92070  */
92071 struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s
92072 {
92073  uint32_t addrhi : 16; /* MAC Address119 [47:32] */
92074  uint32_t : 8; /* *UNDEFINED* */
92075  uint32_t mbc_0 : 1; /* Mask Byte Control */
92076  uint32_t mbc_1 : 1; /* Mask Byte Control */
92077  uint32_t mbc_2 : 1; /* Mask Byte Control */
92078  uint32_t mbc_3 : 1; /* Mask Byte Control */
92079  uint32_t mbc_4 : 1; /* Mask Byte Control */
92080  uint32_t mbc_5 : 1; /* Mask Byte Control */
92081  uint32_t sa : 1; /* Source Address */
92082  uint32_t ae : 1; /* Address Enable */
92083 };
92084 
92085 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH. */
92086 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t;
92087 #endif /* __ASSEMBLY__ */
92088 
92089 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register from the beginning of the component. */
92090 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST 0xb38
92091 /* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register. */
92092 #define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST))
92093 
92094 /*
92095  * Register : Register 719 (MAC Address119 Low Register) - MAC_Address119_Low
92096  *
92097  * The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC
92098  * address of the station.
92099  *
92100  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
92101  * format.
92102  *
92103  * Register Layout
92104  *
92105  * Bits | Access | Reset | Description
92106  * :-------|:-------|:-----------|:----------------------
92107  * [31:0] | RW | 0xffffffff | MAC Address119 [31:0]
92108  *
92109  */
92110 /*
92111  * Field : MAC Address119 [31:0] - addrlo
92112  *
92113  * This field contains the lower 32 bits of the 120th 6-byte MAC address. The
92114  * content of this field is undefined until loaded by software after the
92115  * initialization process.
92116  *
92117  * Field Access Macros:
92118  *
92119  */
92120 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
92121 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_LSB 0
92122 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
92123 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_MSB 31
92124 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
92125 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_WIDTH 32
92126 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
92127 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET_MSK 0xffffffff
92128 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
92129 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_CLR_MSK 0x00000000
92130 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
92131 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_RESET 0xffffffff
92132 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO field value from a register. */
92133 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
92134 /* Produces a ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value suitable for setting the register. */
92135 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
92136 
92137 #ifndef __ASSEMBLY__
92138 /*
92139  * WARNING: The C register and register group struct declarations are provided for
92140  * convenience and illustrative purposes. They should, however, be used with
92141  * caution as the C language standard provides no guarantees about the alignment or
92142  * atomicity of device memory accesses. The recommended practice for writing
92143  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
92144  * alt_write_word() functions.
92145  *
92146  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW.
92147  */
92148 struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s
92149 {
92150  uint32_t addrlo : 32; /* MAC Address119 [31:0] */
92151 };
92152 
92153 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW. */
92154 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s ALT_EMAC_GMAC_MAC_ADDR119_LOW_t;
92155 #endif /* __ASSEMBLY__ */
92156 
92157 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register from the beginning of the component. */
92158 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST 0xb3c
92159 /* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register. */
92160 #define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST))
92161 
92162 /*
92163  * Register : Register 720 (MAC Address120 High Register) - MAC_Address120_High
92164  *
92165  * The MAC Address120 High register holds the upper 16 bits of the 121th 6-byte MAC
92166  * address of the station. Because the MAC address registers are configured to be
92167  * double-synchronized to the (G)MII clock domains, the synchronization is
92168  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
92169  * endian mode) of the MAC Address120 Low Register are written. For proper
92170  * synchronization updates, the consecutive writes to this Address Low Register
92171  * should be performed after at least four clock cycles in the destination clock
92172  * domain.
92173  *
92174  * Note that all MAC Address High registers (except MAC Address0 High) have the
92175  * same format.
92176  *
92177  * Register Layout
92178  *
92179  * Bits | Access | Reset | Description
92180  * :--------|:-------|:-------|:-----------------------
92181  * [15:0] | RW | 0xffff | MAC Address120 [47:32]
92182  * [23:16] | ??? | 0x0 | *UNDEFINED*
92183  * [24] | RW | 0x0 | Mask Byte Control
92184  * [25] | RW | 0x0 | Mask Byte Control
92185  * [26] | RW | 0x0 | Mask Byte Control
92186  * [27] | RW | 0x0 | Mask Byte Control
92187  * [28] | RW | 0x0 | Mask Byte Control
92188  * [29] | RW | 0x0 | Mask Byte Control
92189  * [30] | RW | 0x0 | Source Address
92190  * [31] | RW | 0x0 | Address Enable
92191  *
92192  */
92193 /*
92194  * Field : MAC Address120 [47:32] - addrhi
92195  *
92196  * This field contains the upper 16 bits (47:32) of the 121th 6-byte MAC address.
92197  *
92198  * Field Access Macros:
92199  *
92200  */
92201 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
92202 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_LSB 0
92203 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
92204 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_MSB 15
92205 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
92206 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_WIDTH 16
92207 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
92208 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET_MSK 0x0000ffff
92209 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
92210 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_CLR_MSK 0xffff0000
92211 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
92212 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_RESET 0xffff
92213 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI field value from a register. */
92214 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
92215 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value suitable for setting the register. */
92216 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
92217 
92218 /*
92219  * Field : Mask Byte Control - mbc_0
92220  *
92221  * This array of bits are mask control bits for comparison of each of the MAC
92222  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92223  * received DA or SA with the contents of MAC Address120 high and low registers.
92224  * Each bit controls the masking of the bytes. You can filter a group of addresses
92225  * (known as group address filtering) by masking one or more bytes of the address.
92226  *
92227  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92228  *
92229  * Field Enumeration Values:
92230  *
92231  * Enum | Value | Description
92232  * :-----------------------------------------------|:------|:------------------------------------
92233  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92234  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92235  *
92236  * Field Access Macros:
92237  *
92238  */
92239 /*
92240  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0
92241  *
92242  * Byte is unmasked (i.e. is compared)
92243  */
92244 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED 0x0
92245 /*
92246  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0
92247  *
92248  * Byte is masked (i.e. not compared)
92249  */
92250 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED 0x1
92251 
92252 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
92253 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_LSB 24
92254 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
92255 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_MSB 24
92256 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
92257 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_WIDTH 1
92258 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */
92259 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET_MSK 0x01000000
92260 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */
92261 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_CLR_MSK 0xfeffffff
92262 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
92263 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_RESET 0x0
92264 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 field value from a register. */
92265 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
92266 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value suitable for setting the register. */
92267 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
92268 
92269 /*
92270  * Field : Mask Byte Control - mbc_1
92271  *
92272  * This array of bits are mask control bits for comparison of each of the MAC
92273  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92274  * received DA or SA with the contents of MAC Address120 high and low registers.
92275  * Each bit controls the masking of the bytes. You can filter a group of addresses
92276  * (known as group address filtering) by masking one or more bytes of the address.
92277  *
92278  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92279  *
92280  * Field Enumeration Values:
92281  *
92282  * Enum | Value | Description
92283  * :-----------------------------------------------|:------|:------------------------------------
92284  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92285  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92286  *
92287  * Field Access Macros:
92288  *
92289  */
92290 /*
92291  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1
92292  *
92293  * Byte is unmasked (i.e. is compared)
92294  */
92295 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED 0x0
92296 /*
92297  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1
92298  *
92299  * Byte is masked (i.e. not compared)
92300  */
92301 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED 0x1
92302 
92303 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
92304 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_LSB 25
92305 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
92306 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_MSB 25
92307 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
92308 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_WIDTH 1
92309 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */
92310 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET_MSK 0x02000000
92311 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */
92312 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_CLR_MSK 0xfdffffff
92313 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
92314 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_RESET 0x0
92315 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 field value from a register. */
92316 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
92317 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value suitable for setting the register. */
92318 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
92319 
92320 /*
92321  * Field : Mask Byte Control - mbc_2
92322  *
92323  * This array of bits are mask control bits for comparison of each of the MAC
92324  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92325  * received DA or SA with the contents of MAC Address120 high and low registers.
92326  * Each bit controls the masking of the bytes. You can filter a group of addresses
92327  * (known as group address filtering) by masking one or more bytes of the address.
92328  *
92329  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92330  *
92331  * Field Enumeration Values:
92332  *
92333  * Enum | Value | Description
92334  * :-----------------------------------------------|:------|:------------------------------------
92335  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92336  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92337  *
92338  * Field Access Macros:
92339  *
92340  */
92341 /*
92342  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2
92343  *
92344  * Byte is unmasked (i.e. is compared)
92345  */
92346 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED 0x0
92347 /*
92348  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2
92349  *
92350  * Byte is masked (i.e. not compared)
92351  */
92352 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED 0x1
92353 
92354 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
92355 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_LSB 26
92356 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
92357 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_MSB 26
92358 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
92359 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_WIDTH 1
92360 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */
92361 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET_MSK 0x04000000
92362 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */
92363 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_CLR_MSK 0xfbffffff
92364 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
92365 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_RESET 0x0
92366 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 field value from a register. */
92367 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
92368 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value suitable for setting the register. */
92369 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
92370 
92371 /*
92372  * Field : Mask Byte Control - mbc_3
92373  *
92374  * This array of bits are mask control bits for comparison of each of the MAC
92375  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92376  * received DA or SA with the contents of MAC Address120 high and low registers.
92377  * Each bit controls the masking of the bytes. You can filter a group of addresses
92378  * (known as group address filtering) by masking one or more bytes of the address.
92379  *
92380  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92381  *
92382  * Field Enumeration Values:
92383  *
92384  * Enum | Value | Description
92385  * :-----------------------------------------------|:------|:------------------------------------
92386  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92387  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92388  *
92389  * Field Access Macros:
92390  *
92391  */
92392 /*
92393  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3
92394  *
92395  * Byte is unmasked (i.e. is compared)
92396  */
92397 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED 0x0
92398 /*
92399  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3
92400  *
92401  * Byte is masked (i.e. not compared)
92402  */
92403 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED 0x1
92404 
92405 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
92406 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_LSB 27
92407 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
92408 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_MSB 27
92409 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
92410 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_WIDTH 1
92411 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */
92412 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET_MSK 0x08000000
92413 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */
92414 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_CLR_MSK 0xf7ffffff
92415 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
92416 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_RESET 0x0
92417 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 field value from a register. */
92418 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
92419 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value suitable for setting the register. */
92420 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
92421 
92422 /*
92423  * Field : Mask Byte Control - mbc_4
92424  *
92425  * This array of bits are mask control bits for comparison of each of the MAC
92426  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92427  * received DA or SA with the contents of MAC Address120 high and low registers.
92428  * Each bit controls the masking of the bytes. You can filter a group of addresses
92429  * (known as group address filtering) by masking one or more bytes of the address.
92430  *
92431  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92432  *
92433  * Field Enumeration Values:
92434  *
92435  * Enum | Value | Description
92436  * :-----------------------------------------------|:------|:------------------------------------
92437  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92438  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92439  *
92440  * Field Access Macros:
92441  *
92442  */
92443 /*
92444  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4
92445  *
92446  * Byte is unmasked (i.e. is compared)
92447  */
92448 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED 0x0
92449 /*
92450  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4
92451  *
92452  * Byte is masked (i.e. not compared)
92453  */
92454 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED 0x1
92455 
92456 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
92457 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_LSB 28
92458 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
92459 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_MSB 28
92460 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
92461 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_WIDTH 1
92462 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */
92463 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET_MSK 0x10000000
92464 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */
92465 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_CLR_MSK 0xefffffff
92466 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
92467 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_RESET 0x0
92468 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 field value from a register. */
92469 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
92470 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value suitable for setting the register. */
92471 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
92472 
92473 /*
92474  * Field : Mask Byte Control - mbc_5
92475  *
92476  * This array of bits are mask control bits for comparison of each of the MAC
92477  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92478  * received DA or SA with the contents of MAC Address120 high and low registers.
92479  * Each bit controls the masking of the bytes. You can filter a group of addresses
92480  * (known as group address filtering) by masking one or more bytes of the address.
92481  *
92482  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92483  *
92484  * Field Enumeration Values:
92485  *
92486  * Enum | Value | Description
92487  * :-----------------------------------------------|:------|:------------------------------------
92488  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92489  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92490  *
92491  * Field Access Macros:
92492  *
92493  */
92494 /*
92495  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5
92496  *
92497  * Byte is unmasked (i.e. is compared)
92498  */
92499 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED 0x0
92500 /*
92501  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5
92502  *
92503  * Byte is masked (i.e. not compared)
92504  */
92505 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED 0x1
92506 
92507 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
92508 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_LSB 29
92509 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
92510 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_MSB 29
92511 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
92512 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_WIDTH 1
92513 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */
92514 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET_MSK 0x20000000
92515 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */
92516 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_CLR_MSK 0xdfffffff
92517 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
92518 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_RESET 0x0
92519 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 field value from a register. */
92520 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
92521 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value suitable for setting the register. */
92522 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
92523 
92524 /*
92525  * Field : Source Address - sa
92526  *
92527  * When this bit is enabled, the MAC Address120[47:0] is used to compare with the
92528  * SA fields of the received frame. When this bit is disabled, the MAC
92529  * Address120[47:0] is used to compare with the DA fields of the received frame.
92530  *
92531  * Field Enumeration Values:
92532  *
92533  * Enum | Value | Description
92534  * :-----------------------------------------|:------|:-----------------------------
92535  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
92536  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END | 0x1 | MAC address compare enabled
92537  *
92538  * Field Access Macros:
92539  *
92540  */
92541 /*
92542  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA
92543  *
92544  * MAC address compare disabled
92545  */
92546 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD 0x0
92547 /*
92548  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA
92549  *
92550  * MAC address compare enabled
92551  */
92552 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END 0x1
92553 
92554 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
92555 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_LSB 30
92556 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
92557 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_MSB 30
92558 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
92559 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_WIDTH 1
92560 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */
92561 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET_MSK 0x40000000
92562 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */
92563 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_CLR_MSK 0xbfffffff
92564 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
92565 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_RESET 0x0
92566 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA field value from a register. */
92567 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
92568 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value suitable for setting the register. */
92569 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
92570 
92571 /*
92572  * Field : Address Enable - ae
92573  *
92574  * When this bit is enabled, the address filter block uses the 121th MAC address
92575  * for perfect filtering. When this bit is disabled, the address filter block
92576  * ignores the address for filtering.
92577  *
92578  * Field Enumeration Values:
92579  *
92580  * Enum | Value | Description
92581  * :-----------------------------------------|:------|:--------------------------------------
92582  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
92583  * ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
92584  *
92585  * Field Access Macros:
92586  *
92587  */
92588 /*
92589  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
92590  *
92591  * Second MAC address filtering disabled
92592  */
92593 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD 0x0
92594 /*
92595  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
92596  *
92597  * Second MAC address filtering enabled
92598  */
92599 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END 0x1
92600 
92601 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
92602 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_LSB 31
92603 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
92604 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_MSB 31
92605 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
92606 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_WIDTH 1
92607 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
92608 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET_MSK 0x80000000
92609 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
92610 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_CLR_MSK 0x7fffffff
92611 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
92612 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_RESET 0x0
92613 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE field value from a register. */
92614 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
92615 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value suitable for setting the register. */
92616 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
92617 
92618 #ifndef __ASSEMBLY__
92619 /*
92620  * WARNING: The C register and register group struct declarations are provided for
92621  * convenience and illustrative purposes. They should, however, be used with
92622  * caution as the C language standard provides no guarantees about the alignment or
92623  * atomicity of device memory accesses. The recommended practice for writing
92624  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
92625  * alt_write_word() functions.
92626  *
92627  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH.
92628  */
92629 struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s
92630 {
92631  uint32_t addrhi : 16; /* MAC Address120 [47:32] */
92632  uint32_t : 8; /* *UNDEFINED* */
92633  uint32_t mbc_0 : 1; /* Mask Byte Control */
92634  uint32_t mbc_1 : 1; /* Mask Byte Control */
92635  uint32_t mbc_2 : 1; /* Mask Byte Control */
92636  uint32_t mbc_3 : 1; /* Mask Byte Control */
92637  uint32_t mbc_4 : 1; /* Mask Byte Control */
92638  uint32_t mbc_5 : 1; /* Mask Byte Control */
92639  uint32_t sa : 1; /* Source Address */
92640  uint32_t ae : 1; /* Address Enable */
92641 };
92642 
92643 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH. */
92644 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t;
92645 #endif /* __ASSEMBLY__ */
92646 
92647 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register from the beginning of the component. */
92648 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST 0xb40
92649 /* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register. */
92650 #define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST))
92651 
92652 /*
92653  * Register : Register 721 (MAC Address120 Low Register) - MAC_Address120_Low
92654  *
92655  * The MAC Address120 Low register holds the lower 32 bits of the 121th 6-byte MAC
92656  * address of the station.
92657  *
92658  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
92659  * format.
92660  *
92661  * Register Layout
92662  *
92663  * Bits | Access | Reset | Description
92664  * :-------|:-------|:-----------|:----------------------
92665  * [31:0] | RW | 0xffffffff | MAC Address120 [31:0]
92666  *
92667  */
92668 /*
92669  * Field : MAC Address120 [31:0] - addrlo
92670  *
92671  * This field contains the lower 32 bits of the 121th 6-byte MAC address. The
92672  * content of this field is undefined until loaded by software after the
92673  * initialization process.
92674  *
92675  * Field Access Macros:
92676  *
92677  */
92678 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
92679 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_LSB 0
92680 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
92681 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_MSB 31
92682 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
92683 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_WIDTH 32
92684 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
92685 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET_MSK 0xffffffff
92686 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
92687 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_CLR_MSK 0x00000000
92688 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
92689 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_RESET 0xffffffff
92690 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO field value from a register. */
92691 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
92692 /* Produces a ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value suitable for setting the register. */
92693 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
92694 
92695 #ifndef __ASSEMBLY__
92696 /*
92697  * WARNING: The C register and register group struct declarations are provided for
92698  * convenience and illustrative purposes. They should, however, be used with
92699  * caution as the C language standard provides no guarantees about the alignment or
92700  * atomicity of device memory accesses. The recommended practice for writing
92701  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
92702  * alt_write_word() functions.
92703  *
92704  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW.
92705  */
92706 struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s
92707 {
92708  uint32_t addrlo : 32; /* MAC Address120 [31:0] */
92709 };
92710 
92711 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW. */
92712 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s ALT_EMAC_GMAC_MAC_ADDR120_LOW_t;
92713 #endif /* __ASSEMBLY__ */
92714 
92715 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register from the beginning of the component. */
92716 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST 0xb44
92717 /* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register. */
92718 #define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST))
92719 
92720 /*
92721  * Register : Register 722 (MAC Address121 High Register) - MAC_Address121_High
92722  *
92723  * The MAC Address121 High register holds the upper 16 bits of the 122th 6-byte MAC
92724  * address of the station. Because the MAC address registers are configured to be
92725  * double-synchronized to the (G)MII clock domains, the synchronization is
92726  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
92727  * endian mode) of the MAC Address121 Low Register are written. For proper
92728  * synchronization updates, the consecutive writes to this Address Low Register
92729  * should be performed after at least four clock cycles in the destination clock
92730  * domain.
92731  *
92732  * Note that all MAC Address High registers (except MAC Address0 High) have the
92733  * same format.
92734  *
92735  * Register Layout
92736  *
92737  * Bits | Access | Reset | Description
92738  * :--------|:-------|:-------|:-----------------------
92739  * [15:0] | RW | 0xffff | MAC Address121 [47:32]
92740  * [23:16] | ??? | 0x0 | *UNDEFINED*
92741  * [24] | RW | 0x0 | Mask Byte Control
92742  * [25] | RW | 0x0 | Mask Byte Control
92743  * [26] | RW | 0x0 | Mask Byte Control
92744  * [27] | RW | 0x0 | Mask Byte Control
92745  * [28] | RW | 0x0 | Mask Byte Control
92746  * [29] | RW | 0x0 | Mask Byte Control
92747  * [30] | RW | 0x0 | Source Address
92748  * [31] | RW | 0x0 | Address Enable
92749  *
92750  */
92751 /*
92752  * Field : MAC Address121 [47:32] - addrhi
92753  *
92754  * This field contains the upper 16 bits (47:32) of the 122th 6-byte MAC address.
92755  *
92756  * Field Access Macros:
92757  *
92758  */
92759 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
92760 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_LSB 0
92761 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
92762 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_MSB 15
92763 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
92764 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_WIDTH 16
92765 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
92766 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET_MSK 0x0000ffff
92767 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
92768 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_CLR_MSK 0xffff0000
92769 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
92770 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_RESET 0xffff
92771 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI field value from a register. */
92772 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
92773 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value suitable for setting the register. */
92774 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
92775 
92776 /*
92777  * Field : Mask Byte Control - mbc_0
92778  *
92779  * This array of bits are mask control bits for comparison of each of the MAC
92780  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92781  * received DA or SA with the contents of MAC Address121 high and low registers.
92782  * Each bit controls the masking of the bytes. You can filter a group of addresses
92783  * (known as group address filtering) by masking one or more bytes of the address.
92784  *
92785  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92786  *
92787  * Field Enumeration Values:
92788  *
92789  * Enum | Value | Description
92790  * :-----------------------------------------------|:------|:------------------------------------
92791  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92792  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92793  *
92794  * Field Access Macros:
92795  *
92796  */
92797 /*
92798  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0
92799  *
92800  * Byte is unmasked (i.e. is compared)
92801  */
92802 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED 0x0
92803 /*
92804  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0
92805  *
92806  * Byte is masked (i.e. not compared)
92807  */
92808 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED 0x1
92809 
92810 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
92811 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_LSB 24
92812 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
92813 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_MSB 24
92814 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
92815 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_WIDTH 1
92816 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */
92817 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET_MSK 0x01000000
92818 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */
92819 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_CLR_MSK 0xfeffffff
92820 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
92821 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_RESET 0x0
92822 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 field value from a register. */
92823 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
92824 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value suitable for setting the register. */
92825 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
92826 
92827 /*
92828  * Field : Mask Byte Control - mbc_1
92829  *
92830  * This array of bits are mask control bits for comparison of each of the MAC
92831  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92832  * received DA or SA with the contents of MAC Address121 high and low registers.
92833  * Each bit controls the masking of the bytes. You can filter a group of addresses
92834  * (known as group address filtering) by masking one or more bytes of the address.
92835  *
92836  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92837  *
92838  * Field Enumeration Values:
92839  *
92840  * Enum | Value | Description
92841  * :-----------------------------------------------|:------|:------------------------------------
92842  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92843  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92844  *
92845  * Field Access Macros:
92846  *
92847  */
92848 /*
92849  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1
92850  *
92851  * Byte is unmasked (i.e. is compared)
92852  */
92853 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED 0x0
92854 /*
92855  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1
92856  *
92857  * Byte is masked (i.e. not compared)
92858  */
92859 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED 0x1
92860 
92861 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
92862 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_LSB 25
92863 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
92864 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_MSB 25
92865 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
92866 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_WIDTH 1
92867 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */
92868 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET_MSK 0x02000000
92869 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */
92870 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_CLR_MSK 0xfdffffff
92871 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
92872 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_RESET 0x0
92873 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 field value from a register. */
92874 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
92875 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value suitable for setting the register. */
92876 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
92877 
92878 /*
92879  * Field : Mask Byte Control - mbc_2
92880  *
92881  * This array of bits are mask control bits for comparison of each of the MAC
92882  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92883  * received DA or SA with the contents of MAC Address121 high and low registers.
92884  * Each bit controls the masking of the bytes. You can filter a group of addresses
92885  * (known as group address filtering) by masking one or more bytes of the address.
92886  *
92887  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92888  *
92889  * Field Enumeration Values:
92890  *
92891  * Enum | Value | Description
92892  * :-----------------------------------------------|:------|:------------------------------------
92893  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92894  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92895  *
92896  * Field Access Macros:
92897  *
92898  */
92899 /*
92900  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2
92901  *
92902  * Byte is unmasked (i.e. is compared)
92903  */
92904 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED 0x0
92905 /*
92906  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2
92907  *
92908  * Byte is masked (i.e. not compared)
92909  */
92910 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED 0x1
92911 
92912 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
92913 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_LSB 26
92914 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
92915 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_MSB 26
92916 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
92917 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_WIDTH 1
92918 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */
92919 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET_MSK 0x04000000
92920 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */
92921 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_CLR_MSK 0xfbffffff
92922 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
92923 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_RESET 0x0
92924 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 field value from a register. */
92925 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
92926 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value suitable for setting the register. */
92927 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
92928 
92929 /*
92930  * Field : Mask Byte Control - mbc_3
92931  *
92932  * This array of bits are mask control bits for comparison of each of the MAC
92933  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92934  * received DA or SA with the contents of MAC Address121 high and low registers.
92935  * Each bit controls the masking of the bytes. You can filter a group of addresses
92936  * (known as group address filtering) by masking one or more bytes of the address.
92937  *
92938  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92939  *
92940  * Field Enumeration Values:
92941  *
92942  * Enum | Value | Description
92943  * :-----------------------------------------------|:------|:------------------------------------
92944  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92945  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92946  *
92947  * Field Access Macros:
92948  *
92949  */
92950 /*
92951  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3
92952  *
92953  * Byte is unmasked (i.e. is compared)
92954  */
92955 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED 0x0
92956 /*
92957  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3
92958  *
92959  * Byte is masked (i.e. not compared)
92960  */
92961 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED 0x1
92962 
92963 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
92964 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_LSB 27
92965 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
92966 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_MSB 27
92967 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
92968 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_WIDTH 1
92969 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */
92970 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET_MSK 0x08000000
92971 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */
92972 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_CLR_MSK 0xf7ffffff
92973 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
92974 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_RESET 0x0
92975 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 field value from a register. */
92976 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
92977 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value suitable for setting the register. */
92978 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
92979 
92980 /*
92981  * Field : Mask Byte Control - mbc_4
92982  *
92983  * This array of bits are mask control bits for comparison of each of the MAC
92984  * Address bytes. When masked, the MAC does not compare the corresponding byte of
92985  * received DA or SA with the contents of MAC Address121 high and low registers.
92986  * Each bit controls the masking of the bytes. You can filter a group of addresses
92987  * (known as group address filtering) by masking one or more bytes of the address.
92988  *
92989  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
92990  *
92991  * Field Enumeration Values:
92992  *
92993  * Enum | Value | Description
92994  * :-----------------------------------------------|:------|:------------------------------------
92995  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
92996  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
92997  *
92998  * Field Access Macros:
92999  *
93000  */
93001 /*
93002  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4
93003  *
93004  * Byte is unmasked (i.e. is compared)
93005  */
93006 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED 0x0
93007 /*
93008  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4
93009  *
93010  * Byte is masked (i.e. not compared)
93011  */
93012 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED 0x1
93013 
93014 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
93015 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_LSB 28
93016 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
93017 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_MSB 28
93018 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
93019 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_WIDTH 1
93020 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */
93021 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET_MSK 0x10000000
93022 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */
93023 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_CLR_MSK 0xefffffff
93024 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
93025 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_RESET 0x0
93026 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 field value from a register. */
93027 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
93028 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value suitable for setting the register. */
93029 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
93030 
93031 /*
93032  * Field : Mask Byte Control - mbc_5
93033  *
93034  * This array of bits are mask control bits for comparison of each of the MAC
93035  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93036  * received DA or SA with the contents of MAC Address121 high and low registers.
93037  * Each bit controls the masking of the bytes. You can filter a group of addresses
93038  * (known as group address filtering) by masking one or more bytes of the address.
93039  *
93040  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93041  *
93042  * Field Enumeration Values:
93043  *
93044  * Enum | Value | Description
93045  * :-----------------------------------------------|:------|:------------------------------------
93046  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93047  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93048  *
93049  * Field Access Macros:
93050  *
93051  */
93052 /*
93053  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5
93054  *
93055  * Byte is unmasked (i.e. is compared)
93056  */
93057 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED 0x0
93058 /*
93059  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5
93060  *
93061  * Byte is masked (i.e. not compared)
93062  */
93063 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED 0x1
93064 
93065 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
93066 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_LSB 29
93067 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
93068 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_MSB 29
93069 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
93070 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_WIDTH 1
93071 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */
93072 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET_MSK 0x20000000
93073 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */
93074 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_CLR_MSK 0xdfffffff
93075 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
93076 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_RESET 0x0
93077 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 field value from a register. */
93078 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
93079 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value suitable for setting the register. */
93080 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
93081 
93082 /*
93083  * Field : Source Address - sa
93084  *
93085  * When this bit is enabled, the MAC Address121[47:0] is used to compare with the
93086  * SA fields of the received frame. When this bit is disabled, the MAC
93087  * Address121[47:0] is used to compare with the DA fields of the received frame.
93088  *
93089  * Field Enumeration Values:
93090  *
93091  * Enum | Value | Description
93092  * :-----------------------------------------|:------|:-----------------------------
93093  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
93094  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END | 0x1 | MAC address compare enabled
93095  *
93096  * Field Access Macros:
93097  *
93098  */
93099 /*
93100  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA
93101  *
93102  * MAC address compare disabled
93103  */
93104 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD 0x0
93105 /*
93106  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA
93107  *
93108  * MAC address compare enabled
93109  */
93110 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END 0x1
93111 
93112 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
93113 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_LSB 30
93114 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
93115 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_MSB 30
93116 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
93117 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_WIDTH 1
93118 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */
93119 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET_MSK 0x40000000
93120 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */
93121 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_CLR_MSK 0xbfffffff
93122 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
93123 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_RESET 0x0
93124 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA field value from a register. */
93125 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
93126 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value suitable for setting the register. */
93127 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
93128 
93129 /*
93130  * Field : Address Enable - ae
93131  *
93132  * When this bit is enabled, the address filter block uses the 122th MAC address
93133  * for perfect filtering. When this bit is disabled, the address filter block
93134  * ignores the address for filtering.
93135  *
93136  * Field Enumeration Values:
93137  *
93138  * Enum | Value | Description
93139  * :-----------------------------------------|:------|:--------------------------------------
93140  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
93141  * ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
93142  *
93143  * Field Access Macros:
93144  *
93145  */
93146 /*
93147  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
93148  *
93149  * Second MAC address filtering disabled
93150  */
93151 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD 0x0
93152 /*
93153  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
93154  *
93155  * Second MAC address filtering enabled
93156  */
93157 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END 0x1
93158 
93159 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
93160 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_LSB 31
93161 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
93162 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_MSB 31
93163 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
93164 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_WIDTH 1
93165 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
93166 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET_MSK 0x80000000
93167 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
93168 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_CLR_MSK 0x7fffffff
93169 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
93170 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_RESET 0x0
93171 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE field value from a register. */
93172 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
93173 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value suitable for setting the register. */
93174 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
93175 
93176 #ifndef __ASSEMBLY__
93177 /*
93178  * WARNING: The C register and register group struct declarations are provided for
93179  * convenience and illustrative purposes. They should, however, be used with
93180  * caution as the C language standard provides no guarantees about the alignment or
93181  * atomicity of device memory accesses. The recommended practice for writing
93182  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93183  * alt_write_word() functions.
93184  *
93185  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH.
93186  */
93187 struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s
93188 {
93189  uint32_t addrhi : 16; /* MAC Address121 [47:32] */
93190  uint32_t : 8; /* *UNDEFINED* */
93191  uint32_t mbc_0 : 1; /* Mask Byte Control */
93192  uint32_t mbc_1 : 1; /* Mask Byte Control */
93193  uint32_t mbc_2 : 1; /* Mask Byte Control */
93194  uint32_t mbc_3 : 1; /* Mask Byte Control */
93195  uint32_t mbc_4 : 1; /* Mask Byte Control */
93196  uint32_t mbc_5 : 1; /* Mask Byte Control */
93197  uint32_t sa : 1; /* Source Address */
93198  uint32_t ae : 1; /* Address Enable */
93199 };
93200 
93201 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH. */
93202 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t;
93203 #endif /* __ASSEMBLY__ */
93204 
93205 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register from the beginning of the component. */
93206 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST 0xb48
93207 /* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register. */
93208 #define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST))
93209 
93210 /*
93211  * Register : Register 723 (MAC Address121 Low Register) - MAC_Address121_Low
93212  *
93213  * The MAC Address121 Low register holds the lower 32 bits of the 122th 6-byte MAC
93214  * address of the station.
93215  *
93216  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
93217  * format.
93218  *
93219  * Register Layout
93220  *
93221  * Bits | Access | Reset | Description
93222  * :-------|:-------|:-----------|:----------------------
93223  * [31:0] | RW | 0xffffffff | MAC Address121 [31:0]
93224  *
93225  */
93226 /*
93227  * Field : MAC Address121 [31:0] - addrlo
93228  *
93229  * This field contains the lower 32 bits of the 122th 6-byte MAC address. The
93230  * content of this field is undefined until loaded by software after the
93231  * initialization process.
93232  *
93233  * Field Access Macros:
93234  *
93235  */
93236 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
93237 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_LSB 0
93238 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
93239 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_MSB 31
93240 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
93241 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_WIDTH 32
93242 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
93243 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET_MSK 0xffffffff
93244 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
93245 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_CLR_MSK 0x00000000
93246 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
93247 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_RESET 0xffffffff
93248 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO field value from a register. */
93249 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
93250 /* Produces a ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value suitable for setting the register. */
93251 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
93252 
93253 #ifndef __ASSEMBLY__
93254 /*
93255  * WARNING: The C register and register group struct declarations are provided for
93256  * convenience and illustrative purposes. They should, however, be used with
93257  * caution as the C language standard provides no guarantees about the alignment or
93258  * atomicity of device memory accesses. The recommended practice for writing
93259  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93260  * alt_write_word() functions.
93261  *
93262  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW.
93263  */
93264 struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s
93265 {
93266  uint32_t addrlo : 32; /* MAC Address121 [31:0] */
93267 };
93268 
93269 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW. */
93270 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s ALT_EMAC_GMAC_MAC_ADDR121_LOW_t;
93271 #endif /* __ASSEMBLY__ */
93272 
93273 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register from the beginning of the component. */
93274 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST 0xb4c
93275 /* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register. */
93276 #define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST))
93277 
93278 /*
93279  * Register : Register 724 (MAC Address122 High Register) - MAC_Address122_High
93280  *
93281  * The MAC Address122 High register holds the upper 16 bits of the 123th 6-byte MAC
93282  * address of the station. Because the MAC address registers are configured to be
93283  * double-synchronized to the (G)MII clock domains, the synchronization is
93284  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
93285  * endian mode) of the MAC Address122 Low Register are written. For proper
93286  * synchronization updates, the consecutive writes to this Address Low Register
93287  * should be performed after at least four clock cycles in the destination clock
93288  * domain.
93289  *
93290  * Note that all MAC Address High registers (except MAC Address0 High) have the
93291  * same format.
93292  *
93293  * Register Layout
93294  *
93295  * Bits | Access | Reset | Description
93296  * :--------|:-------|:-------|:-----------------------
93297  * [15:0] | RW | 0xffff | MAC Address122 [47:32]
93298  * [23:16] | ??? | 0x0 | *UNDEFINED*
93299  * [24] | RW | 0x0 | Mask Byte Control
93300  * [25] | RW | 0x0 | Mask Byte Control
93301  * [26] | RW | 0x0 | Mask Byte Control
93302  * [27] | RW | 0x0 | Mask Byte Control
93303  * [28] | RW | 0x0 | Mask Byte Control
93304  * [29] | RW | 0x0 | Mask Byte Control
93305  * [30] | RW | 0x0 | Source Address
93306  * [31] | RW | 0x0 | Address Enable
93307  *
93308  */
93309 /*
93310  * Field : MAC Address122 [47:32] - addrhi
93311  *
93312  * This field contains the upper 16 bits (47:32) of the 123th 6-byte MAC address.
93313  *
93314  * Field Access Macros:
93315  *
93316  */
93317 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
93318 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_LSB 0
93319 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
93320 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_MSB 15
93321 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
93322 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_WIDTH 16
93323 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
93324 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET_MSK 0x0000ffff
93325 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
93326 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_CLR_MSK 0xffff0000
93327 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
93328 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_RESET 0xffff
93329 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI field value from a register. */
93330 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
93331 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value suitable for setting the register. */
93332 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
93333 
93334 /*
93335  * Field : Mask Byte Control - mbc_0
93336  *
93337  * This array of bits are mask control bits for comparison of each of the MAC
93338  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93339  * received DA or SA with the contents of MAC Address122 high and low registers.
93340  * Each bit controls the masking of the bytes. You can filter a group of addresses
93341  * (known as group address filtering) by masking one or more bytes of the address.
93342  *
93343  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93344  *
93345  * Field Enumeration Values:
93346  *
93347  * Enum | Value | Description
93348  * :-----------------------------------------------|:------|:------------------------------------
93349  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93350  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93351  *
93352  * Field Access Macros:
93353  *
93354  */
93355 /*
93356  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0
93357  *
93358  * Byte is unmasked (i.e. is compared)
93359  */
93360 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED 0x0
93361 /*
93362  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0
93363  *
93364  * Byte is masked (i.e. not compared)
93365  */
93366 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED 0x1
93367 
93368 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
93369 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_LSB 24
93370 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
93371 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_MSB 24
93372 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
93373 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_WIDTH 1
93374 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */
93375 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET_MSK 0x01000000
93376 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */
93377 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_CLR_MSK 0xfeffffff
93378 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
93379 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_RESET 0x0
93380 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 field value from a register. */
93381 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
93382 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value suitable for setting the register. */
93383 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
93384 
93385 /*
93386  * Field : Mask Byte Control - mbc_1
93387  *
93388  * This array of bits are mask control bits for comparison of each of the MAC
93389  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93390  * received DA or SA with the contents of MAC Address122 high and low registers.
93391  * Each bit controls the masking of the bytes. You can filter a group of addresses
93392  * (known as group address filtering) by masking one or more bytes of the address.
93393  *
93394  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93395  *
93396  * Field Enumeration Values:
93397  *
93398  * Enum | Value | Description
93399  * :-----------------------------------------------|:------|:------------------------------------
93400  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93401  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93402  *
93403  * Field Access Macros:
93404  *
93405  */
93406 /*
93407  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1
93408  *
93409  * Byte is unmasked (i.e. is compared)
93410  */
93411 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED 0x0
93412 /*
93413  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1
93414  *
93415  * Byte is masked (i.e. not compared)
93416  */
93417 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED 0x1
93418 
93419 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
93420 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_LSB 25
93421 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
93422 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_MSB 25
93423 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
93424 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_WIDTH 1
93425 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */
93426 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET_MSK 0x02000000
93427 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */
93428 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_CLR_MSK 0xfdffffff
93429 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
93430 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_RESET 0x0
93431 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 field value from a register. */
93432 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
93433 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value suitable for setting the register. */
93434 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
93435 
93436 /*
93437  * Field : Mask Byte Control - mbc_2
93438  *
93439  * This array of bits are mask control bits for comparison of each of the MAC
93440  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93441  * received DA or SA with the contents of MAC Address122 high and low registers.
93442  * Each bit controls the masking of the bytes. You can filter a group of addresses
93443  * (known as group address filtering) by masking one or more bytes of the address.
93444  *
93445  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93446  *
93447  * Field Enumeration Values:
93448  *
93449  * Enum | Value | Description
93450  * :-----------------------------------------------|:------|:------------------------------------
93451  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93452  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93453  *
93454  * Field Access Macros:
93455  *
93456  */
93457 /*
93458  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2
93459  *
93460  * Byte is unmasked (i.e. is compared)
93461  */
93462 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED 0x0
93463 /*
93464  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2
93465  *
93466  * Byte is masked (i.e. not compared)
93467  */
93468 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED 0x1
93469 
93470 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
93471 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_LSB 26
93472 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
93473 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_MSB 26
93474 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
93475 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_WIDTH 1
93476 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */
93477 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET_MSK 0x04000000
93478 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */
93479 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_CLR_MSK 0xfbffffff
93480 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
93481 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_RESET 0x0
93482 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 field value from a register. */
93483 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
93484 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value suitable for setting the register. */
93485 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
93486 
93487 /*
93488  * Field : Mask Byte Control - mbc_3
93489  *
93490  * This array of bits are mask control bits for comparison of each of the MAC
93491  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93492  * received DA or SA with the contents of MAC Address122 high and low registers.
93493  * Each bit controls the masking of the bytes. You can filter a group of addresses
93494  * (known as group address filtering) by masking one or more bytes of the address.
93495  *
93496  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93497  *
93498  * Field Enumeration Values:
93499  *
93500  * Enum | Value | Description
93501  * :-----------------------------------------------|:------|:------------------------------------
93502  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93503  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93504  *
93505  * Field Access Macros:
93506  *
93507  */
93508 /*
93509  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3
93510  *
93511  * Byte is unmasked (i.e. is compared)
93512  */
93513 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED 0x0
93514 /*
93515  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3
93516  *
93517  * Byte is masked (i.e. not compared)
93518  */
93519 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED 0x1
93520 
93521 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
93522 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_LSB 27
93523 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
93524 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_MSB 27
93525 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
93526 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_WIDTH 1
93527 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */
93528 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET_MSK 0x08000000
93529 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */
93530 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_CLR_MSK 0xf7ffffff
93531 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
93532 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_RESET 0x0
93533 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 field value from a register. */
93534 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
93535 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value suitable for setting the register. */
93536 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
93537 
93538 /*
93539  * Field : Mask Byte Control - mbc_4
93540  *
93541  * This array of bits are mask control bits for comparison of each of the MAC
93542  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93543  * received DA or SA with the contents of MAC Address122 high and low registers.
93544  * Each bit controls the masking of the bytes. You can filter a group of addresses
93545  * (known as group address filtering) by masking one or more bytes of the address.
93546  *
93547  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93548  *
93549  * Field Enumeration Values:
93550  *
93551  * Enum | Value | Description
93552  * :-----------------------------------------------|:------|:------------------------------------
93553  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93554  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93555  *
93556  * Field Access Macros:
93557  *
93558  */
93559 /*
93560  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4
93561  *
93562  * Byte is unmasked (i.e. is compared)
93563  */
93564 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED 0x0
93565 /*
93566  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4
93567  *
93568  * Byte is masked (i.e. not compared)
93569  */
93570 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED 0x1
93571 
93572 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
93573 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_LSB 28
93574 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
93575 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_MSB 28
93576 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
93577 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_WIDTH 1
93578 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */
93579 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET_MSK 0x10000000
93580 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */
93581 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_CLR_MSK 0xefffffff
93582 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
93583 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_RESET 0x0
93584 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 field value from a register. */
93585 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
93586 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value suitable for setting the register. */
93587 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
93588 
93589 /*
93590  * Field : Mask Byte Control - mbc_5
93591  *
93592  * This array of bits are mask control bits for comparison of each of the MAC
93593  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93594  * received DA or SA with the contents of MAC Address122 high and low registers.
93595  * Each bit controls the masking of the bytes. You can filter a group of addresses
93596  * (known as group address filtering) by masking one or more bytes of the address.
93597  *
93598  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93599  *
93600  * Field Enumeration Values:
93601  *
93602  * Enum | Value | Description
93603  * :-----------------------------------------------|:------|:------------------------------------
93604  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93605  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93606  *
93607  * Field Access Macros:
93608  *
93609  */
93610 /*
93611  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5
93612  *
93613  * Byte is unmasked (i.e. is compared)
93614  */
93615 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED 0x0
93616 /*
93617  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5
93618  *
93619  * Byte is masked (i.e. not compared)
93620  */
93621 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED 0x1
93622 
93623 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
93624 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_LSB 29
93625 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
93626 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_MSB 29
93627 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
93628 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_WIDTH 1
93629 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */
93630 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET_MSK 0x20000000
93631 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */
93632 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_CLR_MSK 0xdfffffff
93633 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
93634 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_RESET 0x0
93635 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 field value from a register. */
93636 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
93637 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value suitable for setting the register. */
93638 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
93639 
93640 /*
93641  * Field : Source Address - sa
93642  *
93643  * When this bit is enabled, the MAC Address122[47:0] is used to compare with the
93644  * SA fields of the received frame. When this bit is disabled, the MAC
93645  * Address122[47:0] is used to compare with the DA fields of the received frame.
93646  *
93647  * Field Enumeration Values:
93648  *
93649  * Enum | Value | Description
93650  * :-----------------------------------------|:------|:-----------------------------
93651  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
93652  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END | 0x1 | MAC address compare enabled
93653  *
93654  * Field Access Macros:
93655  *
93656  */
93657 /*
93658  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA
93659  *
93660  * MAC address compare disabled
93661  */
93662 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD 0x0
93663 /*
93664  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA
93665  *
93666  * MAC address compare enabled
93667  */
93668 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END 0x1
93669 
93670 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
93671 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_LSB 30
93672 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
93673 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_MSB 30
93674 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
93675 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_WIDTH 1
93676 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */
93677 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET_MSK 0x40000000
93678 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */
93679 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_CLR_MSK 0xbfffffff
93680 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
93681 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_RESET 0x0
93682 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA field value from a register. */
93683 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
93684 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value suitable for setting the register. */
93685 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
93686 
93687 /*
93688  * Field : Address Enable - ae
93689  *
93690  * When this bit is enabled, the address filter block uses the 123th MAC address
93691  * for perfect filtering. When this bit is disabled, the address filter block
93692  * ignores the address for filtering.
93693  *
93694  * Field Enumeration Values:
93695  *
93696  * Enum | Value | Description
93697  * :-----------------------------------------|:------|:--------------------------------------
93698  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
93699  * ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
93700  *
93701  * Field Access Macros:
93702  *
93703  */
93704 /*
93705  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
93706  *
93707  * Second MAC address filtering disabled
93708  */
93709 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD 0x0
93710 /*
93711  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
93712  *
93713  * Second MAC address filtering enabled
93714  */
93715 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END 0x1
93716 
93717 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
93718 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_LSB 31
93719 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
93720 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_MSB 31
93721 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
93722 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_WIDTH 1
93723 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
93724 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET_MSK 0x80000000
93725 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
93726 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_CLR_MSK 0x7fffffff
93727 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
93728 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_RESET 0x0
93729 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE field value from a register. */
93730 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
93731 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value suitable for setting the register. */
93732 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
93733 
93734 #ifndef __ASSEMBLY__
93735 /*
93736  * WARNING: The C register and register group struct declarations are provided for
93737  * convenience and illustrative purposes. They should, however, be used with
93738  * caution as the C language standard provides no guarantees about the alignment or
93739  * atomicity of device memory accesses. The recommended practice for writing
93740  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93741  * alt_write_word() functions.
93742  *
93743  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH.
93744  */
93745 struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s
93746 {
93747  uint32_t addrhi : 16; /* MAC Address122 [47:32] */
93748  uint32_t : 8; /* *UNDEFINED* */
93749  uint32_t mbc_0 : 1; /* Mask Byte Control */
93750  uint32_t mbc_1 : 1; /* Mask Byte Control */
93751  uint32_t mbc_2 : 1; /* Mask Byte Control */
93752  uint32_t mbc_3 : 1; /* Mask Byte Control */
93753  uint32_t mbc_4 : 1; /* Mask Byte Control */
93754  uint32_t mbc_5 : 1; /* Mask Byte Control */
93755  uint32_t sa : 1; /* Source Address */
93756  uint32_t ae : 1; /* Address Enable */
93757 };
93758 
93759 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH. */
93760 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t;
93761 #endif /* __ASSEMBLY__ */
93762 
93763 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register from the beginning of the component. */
93764 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST 0xb50
93765 /* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register. */
93766 #define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST))
93767 
93768 /*
93769  * Register : Register 725 (MAC Address122 Low Register) - MAC_Address122_Low
93770  *
93771  * The MAC Address122 Low register holds the lower 32 bits of the 123th 6-byte MAC
93772  * address of the station.
93773  *
93774  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
93775  * format.
93776  *
93777  * Register Layout
93778  *
93779  * Bits | Access | Reset | Description
93780  * :-------|:-------|:-----------|:----------------------
93781  * [31:0] | RW | 0xffffffff | MAC Address122 [31:0]
93782  *
93783  */
93784 /*
93785  * Field : MAC Address122 [31:0] - addrlo
93786  *
93787  * This field contains the lower 32 bits of the 123th 6-byte MAC address. The
93788  * content of this field is undefined until loaded by software after the
93789  * initialization process.
93790  *
93791  * Field Access Macros:
93792  *
93793  */
93794 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
93795 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_LSB 0
93796 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
93797 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_MSB 31
93798 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
93799 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_WIDTH 32
93800 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
93801 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET_MSK 0xffffffff
93802 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
93803 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_CLR_MSK 0x00000000
93804 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
93805 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_RESET 0xffffffff
93806 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO field value from a register. */
93807 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
93808 /* Produces a ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value suitable for setting the register. */
93809 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
93810 
93811 #ifndef __ASSEMBLY__
93812 /*
93813  * WARNING: The C register and register group struct declarations are provided for
93814  * convenience and illustrative purposes. They should, however, be used with
93815  * caution as the C language standard provides no guarantees about the alignment or
93816  * atomicity of device memory accesses. The recommended practice for writing
93817  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
93818  * alt_write_word() functions.
93819  *
93820  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW.
93821  */
93822 struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s
93823 {
93824  uint32_t addrlo : 32; /* MAC Address122 [31:0] */
93825 };
93826 
93827 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW. */
93828 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s ALT_EMAC_GMAC_MAC_ADDR122_LOW_t;
93829 #endif /* __ASSEMBLY__ */
93830 
93831 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register from the beginning of the component. */
93832 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST 0xb54
93833 /* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register. */
93834 #define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST))
93835 
93836 /*
93837  * Register : Register 726 (MAC Address123 High Register) - MAC_Address123_High
93838  *
93839  * The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC
93840  * address of the station. Because the MAC address registers are configured to be
93841  * double-synchronized to the (G)MII clock domains, the synchronization is
93842  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
93843  * endian mode) of the MAC Address123 Low Register are written. For proper
93844  * synchronization updates, the consecutive writes to this Address Low Register
93845  * should be performed after at least four clock cycles in the destination clock
93846  * domain.
93847  *
93848  * Note that all MAC Address High registers (except MAC Address0 High) have the
93849  * same format.
93850  *
93851  * Register Layout
93852  *
93853  * Bits | Access | Reset | Description
93854  * :--------|:-------|:-------|:-----------------------
93855  * [15:0] | RW | 0xffff | MAC Address123 [47:32]
93856  * [23:16] | ??? | 0x0 | *UNDEFINED*
93857  * [24] | RW | 0x0 | Mask Byte Control
93858  * [25] | RW | 0x0 | Mask Byte Control
93859  * [26] | RW | 0x0 | Mask Byte Control
93860  * [27] | RW | 0x0 | Mask Byte Control
93861  * [28] | RW | 0x0 | Mask Byte Control
93862  * [29] | RW | 0x0 | Mask Byte Control
93863  * [30] | RW | 0x0 | Source Address
93864  * [31] | RW | 0x0 | Address Enable
93865  *
93866  */
93867 /*
93868  * Field : MAC Address123 [47:32] - addrhi
93869  *
93870  * This field contains the upper 16 bits (47:32) of the 124th 6-byte MAC address.
93871  *
93872  * Field Access Macros:
93873  *
93874  */
93875 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
93876 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_LSB 0
93877 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
93878 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_MSB 15
93879 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
93880 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_WIDTH 16
93881 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
93882 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET_MSK 0x0000ffff
93883 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
93884 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_CLR_MSK 0xffff0000
93885 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
93886 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_RESET 0xffff
93887 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI field value from a register. */
93888 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
93889 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value suitable for setting the register. */
93890 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
93891 
93892 /*
93893  * Field : Mask Byte Control - mbc_0
93894  *
93895  * This array of bits are mask control bits for comparison of each of the MAC
93896  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93897  * received DA or SA with the contents of MAC Address123 high and low registers.
93898  * Each bit controls the masking of the bytes. You can filter a group of addresses
93899  * (known as group address filtering) by masking one or more bytes of the address.
93900  *
93901  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93902  *
93903  * Field Enumeration Values:
93904  *
93905  * Enum | Value | Description
93906  * :-----------------------------------------------|:------|:------------------------------------
93907  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93908  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93909  *
93910  * Field Access Macros:
93911  *
93912  */
93913 /*
93914  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0
93915  *
93916  * Byte is unmasked (i.e. is compared)
93917  */
93918 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED 0x0
93919 /*
93920  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0
93921  *
93922  * Byte is masked (i.e. not compared)
93923  */
93924 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED 0x1
93925 
93926 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
93927 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_LSB 24
93928 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
93929 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_MSB 24
93930 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
93931 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_WIDTH 1
93932 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */
93933 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET_MSK 0x01000000
93934 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */
93935 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_CLR_MSK 0xfeffffff
93936 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
93937 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_RESET 0x0
93938 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 field value from a register. */
93939 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
93940 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value suitable for setting the register. */
93941 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
93942 
93943 /*
93944  * Field : Mask Byte Control - mbc_1
93945  *
93946  * This array of bits are mask control bits for comparison of each of the MAC
93947  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93948  * received DA or SA with the contents of MAC Address123 high and low registers.
93949  * Each bit controls the masking of the bytes. You can filter a group of addresses
93950  * (known as group address filtering) by masking one or more bytes of the address.
93951  *
93952  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
93953  *
93954  * Field Enumeration Values:
93955  *
93956  * Enum | Value | Description
93957  * :-----------------------------------------------|:------|:------------------------------------
93958  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
93959  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
93960  *
93961  * Field Access Macros:
93962  *
93963  */
93964 /*
93965  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1
93966  *
93967  * Byte is unmasked (i.e. is compared)
93968  */
93969 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED 0x0
93970 /*
93971  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1
93972  *
93973  * Byte is masked (i.e. not compared)
93974  */
93975 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED 0x1
93976 
93977 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
93978 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_LSB 25
93979 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
93980 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_MSB 25
93981 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
93982 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_WIDTH 1
93983 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */
93984 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET_MSK 0x02000000
93985 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */
93986 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_CLR_MSK 0xfdffffff
93987 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
93988 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_RESET 0x0
93989 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 field value from a register. */
93990 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
93991 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value suitable for setting the register. */
93992 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
93993 
93994 /*
93995  * Field : Mask Byte Control - mbc_2
93996  *
93997  * This array of bits are mask control bits for comparison of each of the MAC
93998  * Address bytes. When masked, the MAC does not compare the corresponding byte of
93999  * received DA or SA with the contents of MAC Address123 high and low registers.
94000  * Each bit controls the masking of the bytes. You can filter a group of addresses
94001  * (known as group address filtering) by masking one or more bytes of the address.
94002  *
94003  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94004  *
94005  * Field Enumeration Values:
94006  *
94007  * Enum | Value | Description
94008  * :-----------------------------------------------|:------|:------------------------------------
94009  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94010  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94011  *
94012  * Field Access Macros:
94013  *
94014  */
94015 /*
94016  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2
94017  *
94018  * Byte is unmasked (i.e. is compared)
94019  */
94020 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED 0x0
94021 /*
94022  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2
94023  *
94024  * Byte is masked (i.e. not compared)
94025  */
94026 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED 0x1
94027 
94028 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
94029 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_LSB 26
94030 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
94031 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_MSB 26
94032 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
94033 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_WIDTH 1
94034 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */
94035 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET_MSK 0x04000000
94036 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */
94037 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_CLR_MSK 0xfbffffff
94038 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
94039 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_RESET 0x0
94040 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 field value from a register. */
94041 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
94042 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value suitable for setting the register. */
94043 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
94044 
94045 /*
94046  * Field : Mask Byte Control - mbc_3
94047  *
94048  * This array of bits are mask control bits for comparison of each of the MAC
94049  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94050  * received DA or SA with the contents of MAC Address123 high and low registers.
94051  * Each bit controls the masking of the bytes. You can filter a group of addresses
94052  * (known as group address filtering) by masking one or more bytes of the address.
94053  *
94054  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94055  *
94056  * Field Enumeration Values:
94057  *
94058  * Enum | Value | Description
94059  * :-----------------------------------------------|:------|:------------------------------------
94060  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94061  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94062  *
94063  * Field Access Macros:
94064  *
94065  */
94066 /*
94067  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3
94068  *
94069  * Byte is unmasked (i.e. is compared)
94070  */
94071 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED 0x0
94072 /*
94073  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3
94074  *
94075  * Byte is masked (i.e. not compared)
94076  */
94077 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED 0x1
94078 
94079 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
94080 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_LSB 27
94081 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
94082 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_MSB 27
94083 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
94084 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_WIDTH 1
94085 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */
94086 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET_MSK 0x08000000
94087 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */
94088 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_CLR_MSK 0xf7ffffff
94089 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
94090 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_RESET 0x0
94091 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 field value from a register. */
94092 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
94093 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value suitable for setting the register. */
94094 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
94095 
94096 /*
94097  * Field : Mask Byte Control - mbc_4
94098  *
94099  * This array of bits are mask control bits for comparison of each of the MAC
94100  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94101  * received DA or SA with the contents of MAC Address123 high and low registers.
94102  * Each bit controls the masking of the bytes. You can filter a group of addresses
94103  * (known as group address filtering) by masking one or more bytes of the address.
94104  *
94105  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94106  *
94107  * Field Enumeration Values:
94108  *
94109  * Enum | Value | Description
94110  * :-----------------------------------------------|:------|:------------------------------------
94111  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94112  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94113  *
94114  * Field Access Macros:
94115  *
94116  */
94117 /*
94118  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4
94119  *
94120  * Byte is unmasked (i.e. is compared)
94121  */
94122 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED 0x0
94123 /*
94124  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4
94125  *
94126  * Byte is masked (i.e. not compared)
94127  */
94128 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED 0x1
94129 
94130 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
94131 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_LSB 28
94132 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
94133 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_MSB 28
94134 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
94135 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_WIDTH 1
94136 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */
94137 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET_MSK 0x10000000
94138 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */
94139 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_CLR_MSK 0xefffffff
94140 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
94141 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_RESET 0x0
94142 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 field value from a register. */
94143 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
94144 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value suitable for setting the register. */
94145 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
94146 
94147 /*
94148  * Field : Mask Byte Control - mbc_5
94149  *
94150  * This array of bits are mask control bits for comparison of each of the MAC
94151  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94152  * received DA or SA with the contents of MAC Address123 high and low registers.
94153  * Each bit controls the masking of the bytes. You can filter a group of addresses
94154  * (known as group address filtering) by masking one or more bytes of the address.
94155  *
94156  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94157  *
94158  * Field Enumeration Values:
94159  *
94160  * Enum | Value | Description
94161  * :-----------------------------------------------|:------|:------------------------------------
94162  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94163  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94164  *
94165  * Field Access Macros:
94166  *
94167  */
94168 /*
94169  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5
94170  *
94171  * Byte is unmasked (i.e. is compared)
94172  */
94173 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED 0x0
94174 /*
94175  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5
94176  *
94177  * Byte is masked (i.e. not compared)
94178  */
94179 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED 0x1
94180 
94181 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
94182 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_LSB 29
94183 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
94184 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_MSB 29
94185 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
94186 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_WIDTH 1
94187 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */
94188 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET_MSK 0x20000000
94189 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */
94190 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_CLR_MSK 0xdfffffff
94191 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
94192 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_RESET 0x0
94193 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 field value from a register. */
94194 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
94195 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value suitable for setting the register. */
94196 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
94197 
94198 /*
94199  * Field : Source Address - sa
94200  *
94201  * When this bit is enabled, the MAC Address123[47:0] is used to compare with the
94202  * SA fields of the received frame. When this bit is disabled, the MAC
94203  * Address123[47:0] is used to compare with the DA fields of the received frame.
94204  *
94205  * Field Enumeration Values:
94206  *
94207  * Enum | Value | Description
94208  * :-----------------------------------------|:------|:-----------------------------
94209  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
94210  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END | 0x1 | MAC address compare enabled
94211  *
94212  * Field Access Macros:
94213  *
94214  */
94215 /*
94216  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA
94217  *
94218  * MAC address compare disabled
94219  */
94220 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD 0x0
94221 /*
94222  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA
94223  *
94224  * MAC address compare enabled
94225  */
94226 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END 0x1
94227 
94228 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
94229 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_LSB 30
94230 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
94231 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_MSB 30
94232 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
94233 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_WIDTH 1
94234 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */
94235 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET_MSK 0x40000000
94236 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */
94237 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_CLR_MSK 0xbfffffff
94238 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
94239 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_RESET 0x0
94240 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA field value from a register. */
94241 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
94242 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value suitable for setting the register. */
94243 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
94244 
94245 /*
94246  * Field : Address Enable - ae
94247  *
94248  * When this bit is enabled, the address filter block uses the 124th MAC address
94249  * for perfect filtering. When this bit is disabled, the address filter block
94250  * ignores the address for filtering.
94251  *
94252  * Field Enumeration Values:
94253  *
94254  * Enum | Value | Description
94255  * :-----------------------------------------|:------|:--------------------------------------
94256  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
94257  * ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
94258  *
94259  * Field Access Macros:
94260  *
94261  */
94262 /*
94263  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
94264  *
94265  * Second MAC address filtering disabled
94266  */
94267 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD 0x0
94268 /*
94269  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
94270  *
94271  * Second MAC address filtering enabled
94272  */
94273 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END 0x1
94274 
94275 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
94276 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_LSB 31
94277 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
94278 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_MSB 31
94279 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
94280 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_WIDTH 1
94281 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
94282 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET_MSK 0x80000000
94283 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
94284 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_CLR_MSK 0x7fffffff
94285 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
94286 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_RESET 0x0
94287 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE field value from a register. */
94288 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
94289 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value suitable for setting the register. */
94290 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
94291 
94292 #ifndef __ASSEMBLY__
94293 /*
94294  * WARNING: The C register and register group struct declarations are provided for
94295  * convenience and illustrative purposes. They should, however, be used with
94296  * caution as the C language standard provides no guarantees about the alignment or
94297  * atomicity of device memory accesses. The recommended practice for writing
94298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94299  * alt_write_word() functions.
94300  *
94301  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH.
94302  */
94303 struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s
94304 {
94305  uint32_t addrhi : 16; /* MAC Address123 [47:32] */
94306  uint32_t : 8; /* *UNDEFINED* */
94307  uint32_t mbc_0 : 1; /* Mask Byte Control */
94308  uint32_t mbc_1 : 1; /* Mask Byte Control */
94309  uint32_t mbc_2 : 1; /* Mask Byte Control */
94310  uint32_t mbc_3 : 1; /* Mask Byte Control */
94311  uint32_t mbc_4 : 1; /* Mask Byte Control */
94312  uint32_t mbc_5 : 1; /* Mask Byte Control */
94313  uint32_t sa : 1; /* Source Address */
94314  uint32_t ae : 1; /* Address Enable */
94315 };
94316 
94317 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH. */
94318 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t;
94319 #endif /* __ASSEMBLY__ */
94320 
94321 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register from the beginning of the component. */
94322 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST 0xb58
94323 /* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register. */
94324 #define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST))
94325 
94326 /*
94327  * Register : Register 727 (MAC Address123 Low Register) - MAC_Address123_Low
94328  *
94329  * The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC
94330  * address of the station.
94331  *
94332  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
94333  * format.
94334  *
94335  * Register Layout
94336  *
94337  * Bits | Access | Reset | Description
94338  * :-------|:-------|:-----------|:----------------------
94339  * [31:0] | RW | 0xffffffff | MAC Address123 [31:0]
94340  *
94341  */
94342 /*
94343  * Field : MAC Address123 [31:0] - addrlo
94344  *
94345  * This field contains the lower 32 bits of the 124th 6-byte MAC address. The
94346  * content of this field is undefined until loaded by software after the
94347  * initialization process.
94348  *
94349  * Field Access Macros:
94350  *
94351  */
94352 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
94353 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_LSB 0
94354 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
94355 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_MSB 31
94356 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
94357 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_WIDTH 32
94358 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
94359 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET_MSK 0xffffffff
94360 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
94361 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_CLR_MSK 0x00000000
94362 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
94363 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_RESET 0xffffffff
94364 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO field value from a register. */
94365 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
94366 /* Produces a ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value suitable for setting the register. */
94367 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
94368 
94369 #ifndef __ASSEMBLY__
94370 /*
94371  * WARNING: The C register and register group struct declarations are provided for
94372  * convenience and illustrative purposes. They should, however, be used with
94373  * caution as the C language standard provides no guarantees about the alignment or
94374  * atomicity of device memory accesses. The recommended practice for writing
94375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94376  * alt_write_word() functions.
94377  *
94378  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW.
94379  */
94380 struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s
94381 {
94382  uint32_t addrlo : 32; /* MAC Address123 [31:0] */
94383 };
94384 
94385 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW. */
94386 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s ALT_EMAC_GMAC_MAC_ADDR123_LOW_t;
94387 #endif /* __ASSEMBLY__ */
94388 
94389 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register from the beginning of the component. */
94390 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST 0xb5c
94391 /* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register. */
94392 #define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST))
94393 
94394 /*
94395  * Register : Register 728 (MAC Address124 High Register) - MAC_Address124_High
94396  *
94397  * The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC
94398  * address of the station. Because the MAC address registers are configured to be
94399  * double-synchronized to the (G)MII clock domains, the synchronization is
94400  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
94401  * endian mode) of the MAC Address124 Low Register are written. For proper
94402  * synchronization updates, the consecutive writes to this Address Low Register
94403  * should be performed after at least four clock cycles in the destination clock
94404  * domain.
94405  *
94406  * Note that all MAC Address High registers (except MAC Address0 High) have the
94407  * same format.
94408  *
94409  * Register Layout
94410  *
94411  * Bits | Access | Reset | Description
94412  * :--------|:-------|:-------|:-----------------------
94413  * [15:0] | RW | 0xffff | MAC Address124 [47:32]
94414  * [23:16] | ??? | 0x0 | *UNDEFINED*
94415  * [24] | RW | 0x0 | Mask Byte Control
94416  * [25] | RW | 0x0 | Mask Byte Control
94417  * [26] | RW | 0x0 | Mask Byte Control
94418  * [27] | RW | 0x0 | Mask Byte Control
94419  * [28] | RW | 0x0 | Mask Byte Control
94420  * [29] | RW | 0x0 | Mask Byte Control
94421  * [30] | RW | 0x0 | Source Address
94422  * [31] | RW | 0x0 | Address Enable
94423  *
94424  */
94425 /*
94426  * Field : MAC Address124 [47:32] - addrhi
94427  *
94428  * This field contains the upper 16 bits (47:32) of the 125th 6-byte MAC address.
94429  *
94430  * Field Access Macros:
94431  *
94432  */
94433 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
94434 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_LSB 0
94435 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
94436 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_MSB 15
94437 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
94438 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_WIDTH 16
94439 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
94440 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET_MSK 0x0000ffff
94441 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
94442 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_CLR_MSK 0xffff0000
94443 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
94444 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_RESET 0xffff
94445 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI field value from a register. */
94446 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
94447 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value suitable for setting the register. */
94448 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
94449 
94450 /*
94451  * Field : Mask Byte Control - mbc_0
94452  *
94453  * This array of bits are mask control bits for comparison of each of the MAC
94454  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94455  * received DA or SA with the contents of MAC Address124 high and low registers.
94456  * Each bit controls the masking of the bytes. You can filter a group of addresses
94457  * (known as group address filtering) by masking one or more bytes of the address.
94458  *
94459  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94460  *
94461  * Field Enumeration Values:
94462  *
94463  * Enum | Value | Description
94464  * :-----------------------------------------------|:------|:------------------------------------
94465  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94466  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94467  *
94468  * Field Access Macros:
94469  *
94470  */
94471 /*
94472  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0
94473  *
94474  * Byte is unmasked (i.e. is compared)
94475  */
94476 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED 0x0
94477 /*
94478  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0
94479  *
94480  * Byte is masked (i.e. not compared)
94481  */
94482 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED 0x1
94483 
94484 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
94485 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_LSB 24
94486 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
94487 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_MSB 24
94488 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
94489 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_WIDTH 1
94490 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */
94491 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET_MSK 0x01000000
94492 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */
94493 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_CLR_MSK 0xfeffffff
94494 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
94495 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_RESET 0x0
94496 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 field value from a register. */
94497 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
94498 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value suitable for setting the register. */
94499 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
94500 
94501 /*
94502  * Field : Mask Byte Control - mbc_1
94503  *
94504  * This array of bits are mask control bits for comparison of each of the MAC
94505  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94506  * received DA or SA with the contents of MAC Address124 high and low registers.
94507  * Each bit controls the masking of the bytes. You can filter a group of addresses
94508  * (known as group address filtering) by masking one or more bytes of the address.
94509  *
94510  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94511  *
94512  * Field Enumeration Values:
94513  *
94514  * Enum | Value | Description
94515  * :-----------------------------------------------|:------|:------------------------------------
94516  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94517  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94518  *
94519  * Field Access Macros:
94520  *
94521  */
94522 /*
94523  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1
94524  *
94525  * Byte is unmasked (i.e. is compared)
94526  */
94527 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED 0x0
94528 /*
94529  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1
94530  *
94531  * Byte is masked (i.e. not compared)
94532  */
94533 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED 0x1
94534 
94535 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
94536 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_LSB 25
94537 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
94538 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_MSB 25
94539 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
94540 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_WIDTH 1
94541 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */
94542 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET_MSK 0x02000000
94543 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */
94544 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_CLR_MSK 0xfdffffff
94545 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
94546 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_RESET 0x0
94547 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 field value from a register. */
94548 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
94549 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value suitable for setting the register. */
94550 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
94551 
94552 /*
94553  * Field : Mask Byte Control - mbc_2
94554  *
94555  * This array of bits are mask control bits for comparison of each of the MAC
94556  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94557  * received DA or SA with the contents of MAC Address124 high and low registers.
94558  * Each bit controls the masking of the bytes. You can filter a group of addresses
94559  * (known as group address filtering) by masking one or more bytes of the address.
94560  *
94561  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94562  *
94563  * Field Enumeration Values:
94564  *
94565  * Enum | Value | Description
94566  * :-----------------------------------------------|:------|:------------------------------------
94567  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94568  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94569  *
94570  * Field Access Macros:
94571  *
94572  */
94573 /*
94574  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2
94575  *
94576  * Byte is unmasked (i.e. is compared)
94577  */
94578 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED 0x0
94579 /*
94580  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2
94581  *
94582  * Byte is masked (i.e. not compared)
94583  */
94584 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED 0x1
94585 
94586 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
94587 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_LSB 26
94588 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
94589 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_MSB 26
94590 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
94591 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_WIDTH 1
94592 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */
94593 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET_MSK 0x04000000
94594 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */
94595 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_CLR_MSK 0xfbffffff
94596 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
94597 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_RESET 0x0
94598 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 field value from a register. */
94599 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
94600 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value suitable for setting the register. */
94601 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
94602 
94603 /*
94604  * Field : Mask Byte Control - mbc_3
94605  *
94606  * This array of bits are mask control bits for comparison of each of the MAC
94607  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94608  * received DA or SA with the contents of MAC Address124 high and low registers.
94609  * Each bit controls the masking of the bytes. You can filter a group of addresses
94610  * (known as group address filtering) by masking one or more bytes of the address.
94611  *
94612  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94613  *
94614  * Field Enumeration Values:
94615  *
94616  * Enum | Value | Description
94617  * :-----------------------------------------------|:------|:------------------------------------
94618  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94619  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94620  *
94621  * Field Access Macros:
94622  *
94623  */
94624 /*
94625  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3
94626  *
94627  * Byte is unmasked (i.e. is compared)
94628  */
94629 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED 0x0
94630 /*
94631  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3
94632  *
94633  * Byte is masked (i.e. not compared)
94634  */
94635 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED 0x1
94636 
94637 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
94638 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_LSB 27
94639 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
94640 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_MSB 27
94641 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
94642 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_WIDTH 1
94643 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */
94644 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET_MSK 0x08000000
94645 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */
94646 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_CLR_MSK 0xf7ffffff
94647 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
94648 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_RESET 0x0
94649 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 field value from a register. */
94650 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
94651 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value suitable for setting the register. */
94652 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
94653 
94654 /*
94655  * Field : Mask Byte Control - mbc_4
94656  *
94657  * This array of bits are mask control bits for comparison of each of the MAC
94658  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94659  * received DA or SA with the contents of MAC Address124 high and low registers.
94660  * Each bit controls the masking of the bytes. You can filter a group of addresses
94661  * (known as group address filtering) by masking one or more bytes of the address.
94662  *
94663  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94664  *
94665  * Field Enumeration Values:
94666  *
94667  * Enum | Value | Description
94668  * :-----------------------------------------------|:------|:------------------------------------
94669  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94670  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94671  *
94672  * Field Access Macros:
94673  *
94674  */
94675 /*
94676  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4
94677  *
94678  * Byte is unmasked (i.e. is compared)
94679  */
94680 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED 0x0
94681 /*
94682  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4
94683  *
94684  * Byte is masked (i.e. not compared)
94685  */
94686 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED 0x1
94687 
94688 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
94689 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_LSB 28
94690 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
94691 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_MSB 28
94692 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
94693 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_WIDTH 1
94694 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */
94695 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET_MSK 0x10000000
94696 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */
94697 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_CLR_MSK 0xefffffff
94698 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
94699 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_RESET 0x0
94700 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 field value from a register. */
94701 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
94702 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value suitable for setting the register. */
94703 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
94704 
94705 /*
94706  * Field : Mask Byte Control - mbc_5
94707  *
94708  * This array of bits are mask control bits for comparison of each of the MAC
94709  * Address bytes. When masked, the MAC does not compare the corresponding byte of
94710  * received DA or SA with the contents of MAC Address124 high and low registers.
94711  * Each bit controls the masking of the bytes. You can filter a group of addresses
94712  * (known as group address filtering) by masking one or more bytes of the address.
94713  *
94714  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
94715  *
94716  * Field Enumeration Values:
94717  *
94718  * Enum | Value | Description
94719  * :-----------------------------------------------|:------|:------------------------------------
94720  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
94721  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
94722  *
94723  * Field Access Macros:
94724  *
94725  */
94726 /*
94727  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5
94728  *
94729  * Byte is unmasked (i.e. is compared)
94730  */
94731 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED 0x0
94732 /*
94733  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5
94734  *
94735  * Byte is masked (i.e. not compared)
94736  */
94737 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED 0x1
94738 
94739 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
94740 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_LSB 29
94741 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
94742 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_MSB 29
94743 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
94744 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_WIDTH 1
94745 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */
94746 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET_MSK 0x20000000
94747 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */
94748 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_CLR_MSK 0xdfffffff
94749 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
94750 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_RESET 0x0
94751 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 field value from a register. */
94752 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
94753 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value suitable for setting the register. */
94754 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
94755 
94756 /*
94757  * Field : Source Address - sa
94758  *
94759  * When this bit is enabled, the MAC Address124[47:0] is used to compare with the
94760  * SA fields of the received frame. When this bit is disabled, the MAC
94761  * Address124[47:0] is used to compare with the DA fields of the received frame.
94762  *
94763  * Field Enumeration Values:
94764  *
94765  * Enum | Value | Description
94766  * :-----------------------------------------|:------|:-----------------------------
94767  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
94768  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END | 0x1 | MAC address compare enabled
94769  *
94770  * Field Access Macros:
94771  *
94772  */
94773 /*
94774  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA
94775  *
94776  * MAC address compare disabled
94777  */
94778 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD 0x0
94779 /*
94780  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA
94781  *
94782  * MAC address compare enabled
94783  */
94784 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END 0x1
94785 
94786 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
94787 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_LSB 30
94788 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
94789 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_MSB 30
94790 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
94791 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_WIDTH 1
94792 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */
94793 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET_MSK 0x40000000
94794 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */
94795 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_CLR_MSK 0xbfffffff
94796 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
94797 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_RESET 0x0
94798 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA field value from a register. */
94799 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
94800 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value suitable for setting the register. */
94801 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
94802 
94803 /*
94804  * Field : Address Enable - ae
94805  *
94806  * When this bit is enabled, the address filter block uses the 125th MAC address
94807  * for perfect filtering. When this bit is disabled, the address filter block
94808  * ignores the address for filtering.
94809  *
94810  * Field Enumeration Values:
94811  *
94812  * Enum | Value | Description
94813  * :-----------------------------------------|:------|:--------------------------------------
94814  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
94815  * ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
94816  *
94817  * Field Access Macros:
94818  *
94819  */
94820 /*
94821  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
94822  *
94823  * Second MAC address filtering disabled
94824  */
94825 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD 0x0
94826 /*
94827  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
94828  *
94829  * Second MAC address filtering enabled
94830  */
94831 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END 0x1
94832 
94833 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
94834 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_LSB 31
94835 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
94836 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_MSB 31
94837 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
94838 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_WIDTH 1
94839 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
94840 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET_MSK 0x80000000
94841 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
94842 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_CLR_MSK 0x7fffffff
94843 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
94844 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_RESET 0x0
94845 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE field value from a register. */
94846 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
94847 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value suitable for setting the register. */
94848 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
94849 
94850 #ifndef __ASSEMBLY__
94851 /*
94852  * WARNING: The C register and register group struct declarations are provided for
94853  * convenience and illustrative purposes. They should, however, be used with
94854  * caution as the C language standard provides no guarantees about the alignment or
94855  * atomicity of device memory accesses. The recommended practice for writing
94856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94857  * alt_write_word() functions.
94858  *
94859  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH.
94860  */
94861 struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s
94862 {
94863  uint32_t addrhi : 16; /* MAC Address124 [47:32] */
94864  uint32_t : 8; /* *UNDEFINED* */
94865  uint32_t mbc_0 : 1; /* Mask Byte Control */
94866  uint32_t mbc_1 : 1; /* Mask Byte Control */
94867  uint32_t mbc_2 : 1; /* Mask Byte Control */
94868  uint32_t mbc_3 : 1; /* Mask Byte Control */
94869  uint32_t mbc_4 : 1; /* Mask Byte Control */
94870  uint32_t mbc_5 : 1; /* Mask Byte Control */
94871  uint32_t sa : 1; /* Source Address */
94872  uint32_t ae : 1; /* Address Enable */
94873 };
94874 
94875 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH. */
94876 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t;
94877 #endif /* __ASSEMBLY__ */
94878 
94879 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register from the beginning of the component. */
94880 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST 0xb60
94881 /* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register. */
94882 #define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST))
94883 
94884 /*
94885  * Register : Register 729 (MAC Address124 Low Register) - MAC_Address124_Low
94886  *
94887  * The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC
94888  * address of the station.
94889  *
94890  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
94891  * format.
94892  *
94893  * Register Layout
94894  *
94895  * Bits | Access | Reset | Description
94896  * :-------|:-------|:-----------|:----------------------
94897  * [31:0] | RW | 0xffffffff | MAC Address124 [31:0]
94898  *
94899  */
94900 /*
94901  * Field : MAC Address124 [31:0] - addrlo
94902  *
94903  * This field contains the lower 32 bits of the 125th 6-byte MAC address. The
94904  * content of this field is undefined until loaded by software after the
94905  * initialization process.
94906  *
94907  * Field Access Macros:
94908  *
94909  */
94910 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
94911 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_LSB 0
94912 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
94913 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_MSB 31
94914 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
94915 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_WIDTH 32
94916 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
94917 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET_MSK 0xffffffff
94918 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
94919 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_CLR_MSK 0x00000000
94920 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
94921 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_RESET 0xffffffff
94922 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO field value from a register. */
94923 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
94924 /* Produces a ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value suitable for setting the register. */
94925 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
94926 
94927 #ifndef __ASSEMBLY__
94928 /*
94929  * WARNING: The C register and register group struct declarations are provided for
94930  * convenience and illustrative purposes. They should, however, be used with
94931  * caution as the C language standard provides no guarantees about the alignment or
94932  * atomicity of device memory accesses. The recommended practice for writing
94933  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
94934  * alt_write_word() functions.
94935  *
94936  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW.
94937  */
94938 struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s
94939 {
94940  uint32_t addrlo : 32; /* MAC Address124 [31:0] */
94941 };
94942 
94943 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW. */
94944 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s ALT_EMAC_GMAC_MAC_ADDR124_LOW_t;
94945 #endif /* __ASSEMBLY__ */
94946 
94947 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register from the beginning of the component. */
94948 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST 0xb64
94949 /* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register. */
94950 #define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST))
94951 
94952 /*
94953  * Register : Register 730 (MAC Address125 High Register) - MAC_Address125_High
94954  *
94955  * The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC
94956  * address of the station. Because the MAC address registers are configured to be
94957  * double-synchronized to the (G)MII clock domains, the synchronization is
94958  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
94959  * endian mode) of the MAC Address125 Low Register are written. For proper
94960  * synchronization updates, the consecutive writes to this Address Low Register
94961  * should be performed after at least four clock cycles in the destination clock
94962  * domain.
94963  *
94964  * Note that all MAC Address High registers (except MAC Address0 High) have the
94965  * same format.
94966  *
94967  * Register Layout
94968  *
94969  * Bits | Access | Reset | Description
94970  * :--------|:-------|:-------|:-----------------------
94971  * [15:0] | RW | 0xffff | MAC Address125 [47:32]
94972  * [23:16] | ??? | 0x0 | *UNDEFINED*
94973  * [24] | RW | 0x0 | Mask Byte Control
94974  * [25] | RW | 0x0 | Mask Byte Control
94975  * [26] | RW | 0x0 | Mask Byte Control
94976  * [27] | RW | 0x0 | Mask Byte Control
94977  * [28] | RW | 0x0 | Mask Byte Control
94978  * [29] | RW | 0x0 | Mask Byte Control
94979  * [30] | RW | 0x0 | Source Address
94980  * [31] | RW | 0x0 | Address Enable
94981  *
94982  */
94983 /*
94984  * Field : MAC Address125 [47:32] - addrhi
94985  *
94986  * This field contains the upper 16 bits (47:32) of the 126th 6-byte MAC address.
94987  *
94988  * Field Access Macros:
94989  *
94990  */
94991 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
94992 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_LSB 0
94993 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
94994 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_MSB 15
94995 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
94996 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_WIDTH 16
94997 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
94998 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET_MSK 0x0000ffff
94999 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
95000 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_CLR_MSK 0xffff0000
95001 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
95002 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_RESET 0xffff
95003 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI field value from a register. */
95004 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
95005 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value suitable for setting the register. */
95006 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
95007 
95008 /*
95009  * Field : Mask Byte Control - mbc_0
95010  *
95011  * This array of bits are mask control bits for comparison of each of the MAC
95012  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95013  * received DA or SA with the contents of MAC Address125 high and low registers.
95014  * Each bit controls the masking of the bytes. You can filter a group of addresses
95015  * (known as group address filtering) by masking one or more bytes of the address.
95016  *
95017  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95018  *
95019  * Field Enumeration Values:
95020  *
95021  * Enum | Value | Description
95022  * :-----------------------------------------------|:------|:------------------------------------
95023  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95024  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95025  *
95026  * Field Access Macros:
95027  *
95028  */
95029 /*
95030  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0
95031  *
95032  * Byte is unmasked (i.e. is compared)
95033  */
95034 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED 0x0
95035 /*
95036  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0
95037  *
95038  * Byte is masked (i.e. not compared)
95039  */
95040 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED 0x1
95041 
95042 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
95043 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_LSB 24
95044 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
95045 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_MSB 24
95046 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
95047 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_WIDTH 1
95048 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */
95049 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET_MSK 0x01000000
95050 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */
95051 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_CLR_MSK 0xfeffffff
95052 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
95053 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_RESET 0x0
95054 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 field value from a register. */
95055 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
95056 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value suitable for setting the register. */
95057 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
95058 
95059 /*
95060  * Field : Mask Byte Control - mbc_1
95061  *
95062  * This array of bits are mask control bits for comparison of each of the MAC
95063  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95064  * received DA or SA with the contents of MAC Address125 high and low registers.
95065  * Each bit controls the masking of the bytes. You can filter a group of addresses
95066  * (known as group address filtering) by masking one or more bytes of the address.
95067  *
95068  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95069  *
95070  * Field Enumeration Values:
95071  *
95072  * Enum | Value | Description
95073  * :-----------------------------------------------|:------|:------------------------------------
95074  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95075  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95076  *
95077  * Field Access Macros:
95078  *
95079  */
95080 /*
95081  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1
95082  *
95083  * Byte is unmasked (i.e. is compared)
95084  */
95085 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED 0x0
95086 /*
95087  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1
95088  *
95089  * Byte is masked (i.e. not compared)
95090  */
95091 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED 0x1
95092 
95093 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
95094 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_LSB 25
95095 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
95096 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_MSB 25
95097 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
95098 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_WIDTH 1
95099 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */
95100 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET_MSK 0x02000000
95101 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */
95102 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_CLR_MSK 0xfdffffff
95103 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
95104 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_RESET 0x0
95105 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 field value from a register. */
95106 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
95107 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value suitable for setting the register. */
95108 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
95109 
95110 /*
95111  * Field : Mask Byte Control - mbc_2
95112  *
95113  * This array of bits are mask control bits for comparison of each of the MAC
95114  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95115  * received DA or SA with the contents of MAC Address125 high and low registers.
95116  * Each bit controls the masking of the bytes. You can filter a group of addresses
95117  * (known as group address filtering) by masking one or more bytes of the address.
95118  *
95119  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95120  *
95121  * Field Enumeration Values:
95122  *
95123  * Enum | Value | Description
95124  * :-----------------------------------------------|:------|:------------------------------------
95125  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95126  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95127  *
95128  * Field Access Macros:
95129  *
95130  */
95131 /*
95132  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2
95133  *
95134  * Byte is unmasked (i.e. is compared)
95135  */
95136 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED 0x0
95137 /*
95138  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2
95139  *
95140  * Byte is masked (i.e. not compared)
95141  */
95142 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED 0x1
95143 
95144 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
95145 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_LSB 26
95146 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
95147 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_MSB 26
95148 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
95149 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_WIDTH 1
95150 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */
95151 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET_MSK 0x04000000
95152 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */
95153 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_CLR_MSK 0xfbffffff
95154 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
95155 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_RESET 0x0
95156 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 field value from a register. */
95157 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
95158 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value suitable for setting the register. */
95159 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
95160 
95161 /*
95162  * Field : Mask Byte Control - mbc_3
95163  *
95164  * This array of bits are mask control bits for comparison of each of the MAC
95165  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95166  * received DA or SA with the contents of MAC Address125 high and low registers.
95167  * Each bit controls the masking of the bytes. You can filter a group of addresses
95168  * (known as group address filtering) by masking one or more bytes of the address.
95169  *
95170  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95171  *
95172  * Field Enumeration Values:
95173  *
95174  * Enum | Value | Description
95175  * :-----------------------------------------------|:------|:------------------------------------
95176  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95177  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95178  *
95179  * Field Access Macros:
95180  *
95181  */
95182 /*
95183  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3
95184  *
95185  * Byte is unmasked (i.e. is compared)
95186  */
95187 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED 0x0
95188 /*
95189  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3
95190  *
95191  * Byte is masked (i.e. not compared)
95192  */
95193 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED 0x1
95194 
95195 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
95196 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_LSB 27
95197 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
95198 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_MSB 27
95199 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
95200 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_WIDTH 1
95201 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */
95202 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET_MSK 0x08000000
95203 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */
95204 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_CLR_MSK 0xf7ffffff
95205 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
95206 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_RESET 0x0
95207 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 field value from a register. */
95208 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
95209 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value suitable for setting the register. */
95210 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
95211 
95212 /*
95213  * Field : Mask Byte Control - mbc_4
95214  *
95215  * This array of bits are mask control bits for comparison of each of the MAC
95216  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95217  * received DA or SA with the contents of MAC Address125 high and low registers.
95218  * Each bit controls the masking of the bytes. You can filter a group of addresses
95219  * (known as group address filtering) by masking one or more bytes of the address.
95220  *
95221  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95222  *
95223  * Field Enumeration Values:
95224  *
95225  * Enum | Value | Description
95226  * :-----------------------------------------------|:------|:------------------------------------
95227  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95228  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95229  *
95230  * Field Access Macros:
95231  *
95232  */
95233 /*
95234  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4
95235  *
95236  * Byte is unmasked (i.e. is compared)
95237  */
95238 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED 0x0
95239 /*
95240  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4
95241  *
95242  * Byte is masked (i.e. not compared)
95243  */
95244 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED 0x1
95245 
95246 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
95247 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_LSB 28
95248 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
95249 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_MSB 28
95250 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
95251 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_WIDTH 1
95252 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */
95253 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET_MSK 0x10000000
95254 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */
95255 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_CLR_MSK 0xefffffff
95256 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
95257 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_RESET 0x0
95258 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 field value from a register. */
95259 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
95260 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value suitable for setting the register. */
95261 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
95262 
95263 /*
95264  * Field : Mask Byte Control - mbc_5
95265  *
95266  * This array of bits are mask control bits for comparison of each of the MAC
95267  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95268  * received DA or SA with the contents of MAC Address125 high and low registers.
95269  * Each bit controls the masking of the bytes. You can filter a group of addresses
95270  * (known as group address filtering) by masking one or more bytes of the address.
95271  *
95272  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95273  *
95274  * Field Enumeration Values:
95275  *
95276  * Enum | Value | Description
95277  * :-----------------------------------------------|:------|:------------------------------------
95278  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95279  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95280  *
95281  * Field Access Macros:
95282  *
95283  */
95284 /*
95285  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5
95286  *
95287  * Byte is unmasked (i.e. is compared)
95288  */
95289 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED 0x0
95290 /*
95291  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5
95292  *
95293  * Byte is masked (i.e. not compared)
95294  */
95295 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED 0x1
95296 
95297 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
95298 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_LSB 29
95299 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
95300 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_MSB 29
95301 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
95302 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_WIDTH 1
95303 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */
95304 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET_MSK 0x20000000
95305 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */
95306 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_CLR_MSK 0xdfffffff
95307 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
95308 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_RESET 0x0
95309 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 field value from a register. */
95310 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
95311 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value suitable for setting the register. */
95312 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
95313 
95314 /*
95315  * Field : Source Address - sa
95316  *
95317  * When this bit is enabled, the MAC Address125[47:0] is used to compare with the
95318  * SA fields of the received frame. When this bit is disabled, the MAC
95319  * Address125[47:0] is used to compare with the DA fields of the received frame.
95320  *
95321  * Field Enumeration Values:
95322  *
95323  * Enum | Value | Description
95324  * :-----------------------------------------|:------|:-----------------------------
95325  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
95326  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END | 0x1 | MAC address compare enabled
95327  *
95328  * Field Access Macros:
95329  *
95330  */
95331 /*
95332  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA
95333  *
95334  * MAC address compare disabled
95335  */
95336 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD 0x0
95337 /*
95338  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA
95339  *
95340  * MAC address compare enabled
95341  */
95342 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END 0x1
95343 
95344 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
95345 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_LSB 30
95346 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
95347 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_MSB 30
95348 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
95349 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_WIDTH 1
95350 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */
95351 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET_MSK 0x40000000
95352 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */
95353 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_CLR_MSK 0xbfffffff
95354 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
95355 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_RESET 0x0
95356 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA field value from a register. */
95357 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
95358 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value suitable for setting the register. */
95359 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
95360 
95361 /*
95362  * Field : Address Enable - ae
95363  *
95364  * When this bit is enabled, the address filter block uses the 126th MAC address
95365  * for perfect filtering. When this bit is disabled, the address filter block
95366  * ignores the address for filtering.
95367  *
95368  * Field Enumeration Values:
95369  *
95370  * Enum | Value | Description
95371  * :-----------------------------------------|:------|:--------------------------------------
95372  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
95373  * ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
95374  *
95375  * Field Access Macros:
95376  *
95377  */
95378 /*
95379  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
95380  *
95381  * Second MAC address filtering disabled
95382  */
95383 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD 0x0
95384 /*
95385  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
95386  *
95387  * Second MAC address filtering enabled
95388  */
95389 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END 0x1
95390 
95391 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
95392 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_LSB 31
95393 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
95394 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_MSB 31
95395 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
95396 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_WIDTH 1
95397 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
95398 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET_MSK 0x80000000
95399 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
95400 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_CLR_MSK 0x7fffffff
95401 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
95402 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_RESET 0x0
95403 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE field value from a register. */
95404 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
95405 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value suitable for setting the register. */
95406 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
95407 
95408 #ifndef __ASSEMBLY__
95409 /*
95410  * WARNING: The C register and register group struct declarations are provided for
95411  * convenience and illustrative purposes. They should, however, be used with
95412  * caution as the C language standard provides no guarantees about the alignment or
95413  * atomicity of device memory accesses. The recommended practice for writing
95414  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95415  * alt_write_word() functions.
95416  *
95417  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH.
95418  */
95419 struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s
95420 {
95421  uint32_t addrhi : 16; /* MAC Address125 [47:32] */
95422  uint32_t : 8; /* *UNDEFINED* */
95423  uint32_t mbc_0 : 1; /* Mask Byte Control */
95424  uint32_t mbc_1 : 1; /* Mask Byte Control */
95425  uint32_t mbc_2 : 1; /* Mask Byte Control */
95426  uint32_t mbc_3 : 1; /* Mask Byte Control */
95427  uint32_t mbc_4 : 1; /* Mask Byte Control */
95428  uint32_t mbc_5 : 1; /* Mask Byte Control */
95429  uint32_t sa : 1; /* Source Address */
95430  uint32_t ae : 1; /* Address Enable */
95431 };
95432 
95433 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH. */
95434 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t;
95435 #endif /* __ASSEMBLY__ */
95436 
95437 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register from the beginning of the component. */
95438 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST 0xb68
95439 /* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register. */
95440 #define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST))
95441 
95442 /*
95443  * Register : Register 731 (MAC Address125 Low Register) - MAC_Address125_Low
95444  *
95445  * The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC
95446  * address of the station.
95447  *
95448  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
95449  * format.
95450  *
95451  * Register Layout
95452  *
95453  * Bits | Access | Reset | Description
95454  * :-------|:-------|:-----------|:----------------------
95455  * [31:0] | RW | 0xffffffff | MAC Address125 [31:0]
95456  *
95457  */
95458 /*
95459  * Field : MAC Address125 [31:0] - addrlo
95460  *
95461  * This field contains the lower 32 bits of the 126th 6-byte MAC address. The
95462  * content of this field is undefined until loaded by software after the
95463  * initialization process.
95464  *
95465  * Field Access Macros:
95466  *
95467  */
95468 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
95469 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_LSB 0
95470 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
95471 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_MSB 31
95472 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
95473 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_WIDTH 32
95474 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
95475 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET_MSK 0xffffffff
95476 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
95477 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_CLR_MSK 0x00000000
95478 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
95479 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_RESET 0xffffffff
95480 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO field value from a register. */
95481 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
95482 /* Produces a ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value suitable for setting the register. */
95483 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
95484 
95485 #ifndef __ASSEMBLY__
95486 /*
95487  * WARNING: The C register and register group struct declarations are provided for
95488  * convenience and illustrative purposes. They should, however, be used with
95489  * caution as the C language standard provides no guarantees about the alignment or
95490  * atomicity of device memory accesses. The recommended practice for writing
95491  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95492  * alt_write_word() functions.
95493  *
95494  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW.
95495  */
95496 struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s
95497 {
95498  uint32_t addrlo : 32; /* MAC Address125 [31:0] */
95499 };
95500 
95501 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW. */
95502 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s ALT_EMAC_GMAC_MAC_ADDR125_LOW_t;
95503 #endif /* __ASSEMBLY__ */
95504 
95505 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register from the beginning of the component. */
95506 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST 0xb6c
95507 /* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register. */
95508 #define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST))
95509 
95510 /*
95511  * Register : Register 732 (MAC Address126 High Register) - MAC_Address126_High
95512  *
95513  * The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC
95514  * address of the station. Because the MAC address registers are configured to be
95515  * double-synchronized to the (G)MII clock domains, the synchronization is
95516  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
95517  * endian mode) of the MAC Address126 Low Register are written. For proper
95518  * synchronization updates, the consecutive writes to this Address Low Register
95519  * should be performed after at least four clock cycles in the destination clock
95520  * domain.
95521  *
95522  * Note that all MAC Address High registers (except MAC Address0 High) have the
95523  * same format.
95524  *
95525  * Register Layout
95526  *
95527  * Bits | Access | Reset | Description
95528  * :--------|:-------|:-------|:-----------------------
95529  * [15:0] | RW | 0xffff | MAC Address126 [47:32]
95530  * [23:16] | ??? | 0x0 | *UNDEFINED*
95531  * [24] | RW | 0x0 | Mask Byte Control
95532  * [25] | RW | 0x0 | Mask Byte Control
95533  * [26] | RW | 0x0 | Mask Byte Control
95534  * [27] | RW | 0x0 | Mask Byte Control
95535  * [28] | RW | 0x0 | Mask Byte Control
95536  * [29] | RW | 0x0 | Mask Byte Control
95537  * [30] | RW | 0x0 | Source Address
95538  * [31] | RW | 0x0 | Address Enable
95539  *
95540  */
95541 /*
95542  * Field : MAC Address126 [47:32] - addrhi
95543  *
95544  * This field contains the upper 16 bits (47:32) of the 127th 6-byte MAC address.
95545  *
95546  * Field Access Macros:
95547  *
95548  */
95549 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
95550 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_LSB 0
95551 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
95552 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_MSB 15
95553 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
95554 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_WIDTH 16
95555 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
95556 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET_MSK 0x0000ffff
95557 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
95558 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_CLR_MSK 0xffff0000
95559 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
95560 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_RESET 0xffff
95561 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI field value from a register. */
95562 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
95563 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value suitable for setting the register. */
95564 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
95565 
95566 /*
95567  * Field : Mask Byte Control - mbc_0
95568  *
95569  * This array of bits are mask control bits for comparison of each of the MAC
95570  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95571  * received DA or SA with the contents of MAC Address126 high and low registers.
95572  * Each bit controls the masking of the bytes. You can filter a group of addresses
95573  * (known as group address filtering) by masking one or more bytes of the address.
95574  *
95575  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95576  *
95577  * Field Enumeration Values:
95578  *
95579  * Enum | Value | Description
95580  * :-----------------------------------------------|:------|:------------------------------------
95581  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95582  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95583  *
95584  * Field Access Macros:
95585  *
95586  */
95587 /*
95588  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0
95589  *
95590  * Byte is unmasked (i.e. is compared)
95591  */
95592 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED 0x0
95593 /*
95594  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0
95595  *
95596  * Byte is masked (i.e. not compared)
95597  */
95598 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED 0x1
95599 
95600 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
95601 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_LSB 24
95602 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
95603 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_MSB 24
95604 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
95605 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_WIDTH 1
95606 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */
95607 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET_MSK 0x01000000
95608 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */
95609 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_CLR_MSK 0xfeffffff
95610 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
95611 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_RESET 0x0
95612 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 field value from a register. */
95613 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
95614 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value suitable for setting the register. */
95615 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
95616 
95617 /*
95618  * Field : Mask Byte Control - mbc_1
95619  *
95620  * This array of bits are mask control bits for comparison of each of the MAC
95621  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95622  * received DA or SA with the contents of MAC Address126 high and low registers.
95623  * Each bit controls the masking of the bytes. You can filter a group of addresses
95624  * (known as group address filtering) by masking one or more bytes of the address.
95625  *
95626  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95627  *
95628  * Field Enumeration Values:
95629  *
95630  * Enum | Value | Description
95631  * :-----------------------------------------------|:------|:------------------------------------
95632  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95633  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95634  *
95635  * Field Access Macros:
95636  *
95637  */
95638 /*
95639  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1
95640  *
95641  * Byte is unmasked (i.e. is compared)
95642  */
95643 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED 0x0
95644 /*
95645  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1
95646  *
95647  * Byte is masked (i.e. not compared)
95648  */
95649 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED 0x1
95650 
95651 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
95652 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_LSB 25
95653 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
95654 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_MSB 25
95655 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
95656 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_WIDTH 1
95657 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */
95658 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET_MSK 0x02000000
95659 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */
95660 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_CLR_MSK 0xfdffffff
95661 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
95662 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_RESET 0x0
95663 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 field value from a register. */
95664 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
95665 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value suitable for setting the register. */
95666 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
95667 
95668 /*
95669  * Field : Mask Byte Control - mbc_2
95670  *
95671  * This array of bits are mask control bits for comparison of each of the MAC
95672  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95673  * received DA or SA with the contents of MAC Address126 high and low registers.
95674  * Each bit controls the masking of the bytes. You can filter a group of addresses
95675  * (known as group address filtering) by masking one or more bytes of the address.
95676  *
95677  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95678  *
95679  * Field Enumeration Values:
95680  *
95681  * Enum | Value | Description
95682  * :-----------------------------------------------|:------|:------------------------------------
95683  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95684  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95685  *
95686  * Field Access Macros:
95687  *
95688  */
95689 /*
95690  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2
95691  *
95692  * Byte is unmasked (i.e. is compared)
95693  */
95694 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED 0x0
95695 /*
95696  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2
95697  *
95698  * Byte is masked (i.e. not compared)
95699  */
95700 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED 0x1
95701 
95702 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
95703 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_LSB 26
95704 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
95705 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_MSB 26
95706 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
95707 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_WIDTH 1
95708 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */
95709 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET_MSK 0x04000000
95710 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */
95711 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_CLR_MSK 0xfbffffff
95712 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
95713 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_RESET 0x0
95714 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 field value from a register. */
95715 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
95716 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value suitable for setting the register. */
95717 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
95718 
95719 /*
95720  * Field : Mask Byte Control - mbc_3
95721  *
95722  * This array of bits are mask control bits for comparison of each of the MAC
95723  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95724  * received DA or SA with the contents of MAC Address126 high and low registers.
95725  * Each bit controls the masking of the bytes. You can filter a group of addresses
95726  * (known as group address filtering) by masking one or more bytes of the address.
95727  *
95728  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95729  *
95730  * Field Enumeration Values:
95731  *
95732  * Enum | Value | Description
95733  * :-----------------------------------------------|:------|:------------------------------------
95734  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95735  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95736  *
95737  * Field Access Macros:
95738  *
95739  */
95740 /*
95741  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3
95742  *
95743  * Byte is unmasked (i.e. is compared)
95744  */
95745 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED 0x0
95746 /*
95747  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3
95748  *
95749  * Byte is masked (i.e. not compared)
95750  */
95751 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED 0x1
95752 
95753 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
95754 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_LSB 27
95755 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
95756 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_MSB 27
95757 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
95758 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_WIDTH 1
95759 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */
95760 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET_MSK 0x08000000
95761 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */
95762 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_CLR_MSK 0xf7ffffff
95763 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
95764 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_RESET 0x0
95765 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 field value from a register. */
95766 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
95767 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value suitable for setting the register. */
95768 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
95769 
95770 /*
95771  * Field : Mask Byte Control - mbc_4
95772  *
95773  * This array of bits are mask control bits for comparison of each of the MAC
95774  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95775  * received DA or SA with the contents of MAC Address126 high and low registers.
95776  * Each bit controls the masking of the bytes. You can filter a group of addresses
95777  * (known as group address filtering) by masking one or more bytes of the address.
95778  *
95779  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95780  *
95781  * Field Enumeration Values:
95782  *
95783  * Enum | Value | Description
95784  * :-----------------------------------------------|:------|:------------------------------------
95785  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95786  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95787  *
95788  * Field Access Macros:
95789  *
95790  */
95791 /*
95792  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4
95793  *
95794  * Byte is unmasked (i.e. is compared)
95795  */
95796 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED 0x0
95797 /*
95798  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4
95799  *
95800  * Byte is masked (i.e. not compared)
95801  */
95802 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED 0x1
95803 
95804 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
95805 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_LSB 28
95806 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
95807 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_MSB 28
95808 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
95809 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_WIDTH 1
95810 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */
95811 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET_MSK 0x10000000
95812 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */
95813 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_CLR_MSK 0xefffffff
95814 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
95815 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_RESET 0x0
95816 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 field value from a register. */
95817 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
95818 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value suitable for setting the register. */
95819 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
95820 
95821 /*
95822  * Field : Mask Byte Control - mbc_5
95823  *
95824  * This array of bits are mask control bits for comparison of each of the MAC
95825  * Address bytes. When masked, the MAC does not compare the corresponding byte of
95826  * received DA or SA with the contents of MAC Address126 high and low registers.
95827  * Each bit controls the masking of the bytes. You can filter a group of addresses
95828  * (known as group address filtering) by masking one or more bytes of the address.
95829  *
95830  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
95831  *
95832  * Field Enumeration Values:
95833  *
95834  * Enum | Value | Description
95835  * :-----------------------------------------------|:------|:------------------------------------
95836  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
95837  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
95838  *
95839  * Field Access Macros:
95840  *
95841  */
95842 /*
95843  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5
95844  *
95845  * Byte is unmasked (i.e. is compared)
95846  */
95847 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED 0x0
95848 /*
95849  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5
95850  *
95851  * Byte is masked (i.e. not compared)
95852  */
95853 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED 0x1
95854 
95855 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
95856 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_LSB 29
95857 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
95858 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_MSB 29
95859 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
95860 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_WIDTH 1
95861 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */
95862 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET_MSK 0x20000000
95863 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */
95864 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_CLR_MSK 0xdfffffff
95865 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
95866 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_RESET 0x0
95867 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 field value from a register. */
95868 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
95869 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value suitable for setting the register. */
95870 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
95871 
95872 /*
95873  * Field : Source Address - sa
95874  *
95875  * When this bit is enabled, the MAC Address126[47:0] is used to compare with the
95876  * SA fields of the received frame. When this bit is disabled, the MAC
95877  * Address126[47:0] is used to compare with the DA fields of the received frame.
95878  *
95879  * Field Enumeration Values:
95880  *
95881  * Enum | Value | Description
95882  * :-----------------------------------------|:------|:-----------------------------
95883  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
95884  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END | 0x1 | MAC address compare enabled
95885  *
95886  * Field Access Macros:
95887  *
95888  */
95889 /*
95890  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA
95891  *
95892  * MAC address compare disabled
95893  */
95894 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD 0x0
95895 /*
95896  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA
95897  *
95898  * MAC address compare enabled
95899  */
95900 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END 0x1
95901 
95902 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
95903 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_LSB 30
95904 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
95905 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_MSB 30
95906 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
95907 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_WIDTH 1
95908 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */
95909 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET_MSK 0x40000000
95910 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */
95911 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_CLR_MSK 0xbfffffff
95912 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
95913 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_RESET 0x0
95914 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA field value from a register. */
95915 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
95916 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value suitable for setting the register. */
95917 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
95918 
95919 /*
95920  * Field : Address Enable - ae
95921  *
95922  * When this bit is enabled, the address filter block uses the 127th MAC address
95923  * for perfect filtering. When this bit is disabled, the address filter block
95924  * ignores the address for filtering.
95925  *
95926  * Field Enumeration Values:
95927  *
95928  * Enum | Value | Description
95929  * :-----------------------------------------|:------|:--------------------------------------
95930  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
95931  * ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
95932  *
95933  * Field Access Macros:
95934  *
95935  */
95936 /*
95937  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
95938  *
95939  * Second MAC address filtering disabled
95940  */
95941 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD 0x0
95942 /*
95943  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
95944  *
95945  * Second MAC address filtering enabled
95946  */
95947 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END 0x1
95948 
95949 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
95950 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_LSB 31
95951 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
95952 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_MSB 31
95953 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
95954 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_WIDTH 1
95955 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
95956 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET_MSK 0x80000000
95957 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
95958 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_CLR_MSK 0x7fffffff
95959 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
95960 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_RESET 0x0
95961 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE field value from a register. */
95962 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
95963 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value suitable for setting the register. */
95964 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
95965 
95966 #ifndef __ASSEMBLY__
95967 /*
95968  * WARNING: The C register and register group struct declarations are provided for
95969  * convenience and illustrative purposes. They should, however, be used with
95970  * caution as the C language standard provides no guarantees about the alignment or
95971  * atomicity of device memory accesses. The recommended practice for writing
95972  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
95973  * alt_write_word() functions.
95974  *
95975  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH.
95976  */
95977 struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s
95978 {
95979  uint32_t addrhi : 16; /* MAC Address126 [47:32] */
95980  uint32_t : 8; /* *UNDEFINED* */
95981  uint32_t mbc_0 : 1; /* Mask Byte Control */
95982  uint32_t mbc_1 : 1; /* Mask Byte Control */
95983  uint32_t mbc_2 : 1; /* Mask Byte Control */
95984  uint32_t mbc_3 : 1; /* Mask Byte Control */
95985  uint32_t mbc_4 : 1; /* Mask Byte Control */
95986  uint32_t mbc_5 : 1; /* Mask Byte Control */
95987  uint32_t sa : 1; /* Source Address */
95988  uint32_t ae : 1; /* Address Enable */
95989 };
95990 
95991 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH. */
95992 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t;
95993 #endif /* __ASSEMBLY__ */
95994 
95995 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register from the beginning of the component. */
95996 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST 0xb70
95997 /* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register. */
95998 #define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST))
95999 
96000 /*
96001  * Register : Register 733 (MAC Address126 Low Register) - MAC_Address126_Low
96002  *
96003  * The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC
96004  * address of the station.
96005  *
96006  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
96007  * format.
96008  *
96009  * Register Layout
96010  *
96011  * Bits | Access | Reset | Description
96012  * :-------|:-------|:-----------|:----------------------
96013  * [31:0] | RW | 0xffffffff | MAC Address126 [31:0]
96014  *
96015  */
96016 /*
96017  * Field : MAC Address126 [31:0] - addrlo
96018  *
96019  * This field contains the lower 32 bits of the 127th 6-byte MAC address. The
96020  * content of this field is undefined until loaded by software after the
96021  * initialization process.
96022  *
96023  * Field Access Macros:
96024  *
96025  */
96026 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
96027 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_LSB 0
96028 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
96029 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_MSB 31
96030 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
96031 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_WIDTH 32
96032 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
96033 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET_MSK 0xffffffff
96034 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
96035 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_CLR_MSK 0x00000000
96036 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
96037 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_RESET 0xffffffff
96038 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO field value from a register. */
96039 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
96040 /* Produces a ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value suitable for setting the register. */
96041 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
96042 
96043 #ifndef __ASSEMBLY__
96044 /*
96045  * WARNING: The C register and register group struct declarations are provided for
96046  * convenience and illustrative purposes. They should, however, be used with
96047  * caution as the C language standard provides no guarantees about the alignment or
96048  * atomicity of device memory accesses. The recommended practice for writing
96049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
96050  * alt_write_word() functions.
96051  *
96052  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW.
96053  */
96054 struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s
96055 {
96056  uint32_t addrlo : 32; /* MAC Address126 [31:0] */
96057 };
96058 
96059 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW. */
96060 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s ALT_EMAC_GMAC_MAC_ADDR126_LOW_t;
96061 #endif /* __ASSEMBLY__ */
96062 
96063 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register from the beginning of the component. */
96064 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST 0xb74
96065 /* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register. */
96066 #define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST))
96067 
96068 /*
96069  * Register : Register 734 (MAC Address127 High Register) - MAC_Address127_High
96070  *
96071  * The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC
96072  * address of the station. Because the MAC address registers are configured to be
96073  * double-synchronized to the (G)MII clock domains, the synchronization is
96074  * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
96075  * endian mode) of the MAC Address127 Low Register are written. For proper
96076  * synchronization updates, the consecutive writes to this Address Low Register
96077  * should be performed after at least four clock cycles in the destination clock
96078  * domain.
96079  *
96080  * Note that all MAC Address High registers (except MAC Address0 High) have the
96081  * same format.
96082  *
96083  * Register Layout
96084  *
96085  * Bits | Access | Reset | Description
96086  * :--------|:-------|:-------|:-----------------------
96087  * [15:0] | RW | 0xffff | MAC Address127 [47:32]
96088  * [23:16] | ??? | 0x0 | *UNDEFINED*
96089  * [24] | RW | 0x0 | Mask Byte Control
96090  * [25] | RW | 0x0 | Mask Byte Control
96091  * [26] | RW | 0x0 | Mask Byte Control
96092  * [27] | RW | 0x0 | Mask Byte Control
96093  * [28] | RW | 0x0 | Mask Byte Control
96094  * [29] | RW | 0x0 | Mask Byte Control
96095  * [30] | RW | 0x0 | Source Address
96096  * [31] | RW | 0x0 | Address Enable
96097  *
96098  */
96099 /*
96100  * Field : MAC Address127 [47:32] - addrhi
96101  *
96102  * This field contains the upper 16 bits (47:32) of the 128th 6-byte MAC address.
96103  *
96104  * Field Access Macros:
96105  *
96106  */
96107 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
96108 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_LSB 0
96109 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
96110 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_MSB 15
96111 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
96112 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_WIDTH 16
96113 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
96114 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET_MSK 0x0000ffff
96115 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
96116 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_CLR_MSK 0xffff0000
96117 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
96118 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_RESET 0xffff
96119 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI field value from a register. */
96120 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
96121 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value suitable for setting the register. */
96122 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)
96123 
96124 /*
96125  * Field : Mask Byte Control - mbc_0
96126  *
96127  * This array of bits are mask control bits for comparison of each of the MAC
96128  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96129  * received DA or SA with the contents of MAC Address127 high and low registers.
96130  * Each bit controls the masking of the bytes. You can filter a group of addresses
96131  * (known as group address filtering) by masking one or more bytes of the address.
96132  *
96133  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96134  *
96135  * Field Enumeration Values:
96136  *
96137  * Enum | Value | Description
96138  * :-----------------------------------------------|:------|:------------------------------------
96139  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96140  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96141  *
96142  * Field Access Macros:
96143  *
96144  */
96145 /*
96146  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0
96147  *
96148  * Byte is unmasked (i.e. is compared)
96149  */
96150 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED 0x0
96151 /*
96152  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0
96153  *
96154  * Byte is masked (i.e. not compared)
96155  */
96156 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED 0x1
96157 
96158 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
96159 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_LSB 24
96160 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
96161 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_MSB 24
96162 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
96163 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_WIDTH 1
96164 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */
96165 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET_MSK 0x01000000
96166 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */
96167 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_CLR_MSK 0xfeffffff
96168 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
96169 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_RESET 0x0
96170 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 field value from a register. */
96171 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
96172 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value suitable for setting the register. */
96173 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)
96174 
96175 /*
96176  * Field : Mask Byte Control - mbc_1
96177  *
96178  * This array of bits are mask control bits for comparison of each of the MAC
96179  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96180  * received DA or SA with the contents of MAC Address127 high and low registers.
96181  * Each bit controls the masking of the bytes. You can filter a group of addresses
96182  * (known as group address filtering) by masking one or more bytes of the address.
96183  *
96184  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96185  *
96186  * Field Enumeration Values:
96187  *
96188  * Enum | Value | Description
96189  * :-----------------------------------------------|:------|:------------------------------------
96190  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96191  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96192  *
96193  * Field Access Macros:
96194  *
96195  */
96196 /*
96197  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1
96198  *
96199  * Byte is unmasked (i.e. is compared)
96200  */
96201 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED 0x0
96202 /*
96203  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1
96204  *
96205  * Byte is masked (i.e. not compared)
96206  */
96207 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED 0x1
96208 
96209 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
96210 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_LSB 25
96211 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
96212 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_MSB 25
96213 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
96214 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_WIDTH 1
96215 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */
96216 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET_MSK 0x02000000
96217 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */
96218 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_CLR_MSK 0xfdffffff
96219 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
96220 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_RESET 0x0
96221 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 field value from a register. */
96222 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
96223 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value suitable for setting the register. */
96224 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)
96225 
96226 /*
96227  * Field : Mask Byte Control - mbc_2
96228  *
96229  * This array of bits are mask control bits for comparison of each of the MAC
96230  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96231  * received DA or SA with the contents of MAC Address127 high and low registers.
96232  * Each bit controls the masking of the bytes. You can filter a group of addresses
96233  * (known as group address filtering) by masking one or more bytes of the address.
96234  *
96235  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96236  *
96237  * Field Enumeration Values:
96238  *
96239  * Enum | Value | Description
96240  * :-----------------------------------------------|:------|:------------------------------------
96241  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96242  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96243  *
96244  * Field Access Macros:
96245  *
96246  */
96247 /*
96248  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2
96249  *
96250  * Byte is unmasked (i.e. is compared)
96251  */
96252 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED 0x0
96253 /*
96254  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2
96255  *
96256  * Byte is masked (i.e. not compared)
96257  */
96258 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED 0x1
96259 
96260 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
96261 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_LSB 26
96262 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
96263 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_MSB 26
96264 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
96265 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_WIDTH 1
96266 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */
96267 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET_MSK 0x04000000
96268 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */
96269 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_CLR_MSK 0xfbffffff
96270 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
96271 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_RESET 0x0
96272 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 field value from a register. */
96273 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
96274 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value suitable for setting the register. */
96275 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)
96276 
96277 /*
96278  * Field : Mask Byte Control - mbc_3
96279  *
96280  * This array of bits are mask control bits for comparison of each of the MAC
96281  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96282  * received DA or SA with the contents of MAC Address127 high and low registers.
96283  * Each bit controls the masking of the bytes. You can filter a group of addresses
96284  * (known as group address filtering) by masking one or more bytes of the address.
96285  *
96286  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96287  *
96288  * Field Enumeration Values:
96289  *
96290  * Enum | Value | Description
96291  * :-----------------------------------------------|:------|:------------------------------------
96292  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96293  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96294  *
96295  * Field Access Macros:
96296  *
96297  */
96298 /*
96299  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3
96300  *
96301  * Byte is unmasked (i.e. is compared)
96302  */
96303 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED 0x0
96304 /*
96305  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3
96306  *
96307  * Byte is masked (i.e. not compared)
96308  */
96309 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED 0x1
96310 
96311 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
96312 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_LSB 27
96313 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
96314 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_MSB 27
96315 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
96316 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_WIDTH 1
96317 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */
96318 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET_MSK 0x08000000
96319 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */
96320 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_CLR_MSK 0xf7ffffff
96321 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
96322 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_RESET 0x0
96323 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 field value from a register. */
96324 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
96325 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value suitable for setting the register. */
96326 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)
96327 
96328 /*
96329  * Field : Mask Byte Control - mbc_4
96330  *
96331  * This array of bits are mask control bits for comparison of each of the MAC
96332  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96333  * received DA or SA with the contents of MAC Address127 high and low registers.
96334  * Each bit controls the masking of the bytes. You can filter a group of addresses
96335  * (known as group address filtering) by masking one or more bytes of the address.
96336  *
96337  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96338  *
96339  * Field Enumeration Values:
96340  *
96341  * Enum | Value | Description
96342  * :-----------------------------------------------|:------|:------------------------------------
96343  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96344  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96345  *
96346  * Field Access Macros:
96347  *
96348  */
96349 /*
96350  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4
96351  *
96352  * Byte is unmasked (i.e. is compared)
96353  */
96354 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED 0x0
96355 /*
96356  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4
96357  *
96358  * Byte is masked (i.e. not compared)
96359  */
96360 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED 0x1
96361 
96362 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
96363 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_LSB 28
96364 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
96365 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_MSB 28
96366 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
96367 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_WIDTH 1
96368 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */
96369 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET_MSK 0x10000000
96370 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */
96371 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_CLR_MSK 0xefffffff
96372 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
96373 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_RESET 0x0
96374 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 field value from a register. */
96375 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
96376 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value suitable for setting the register. */
96377 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)
96378 
96379 /*
96380  * Field : Mask Byte Control - mbc_5
96381  *
96382  * This array of bits are mask control bits for comparison of each of the MAC
96383  * Address bytes. When masked, the MAC does not compare the corresponding byte of
96384  * received DA or SA with the contents of MAC Address127 high and low registers.
96385  * Each bit controls the masking of the bytes. You can filter a group of addresses
96386  * (known as group address filtering) by masking one or more bytes of the address.
96387  *
96388  * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
96389  *
96390  * Field Enumeration Values:
96391  *
96392  * Enum | Value | Description
96393  * :-----------------------------------------------|:------|:------------------------------------
96394  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED | 0x0 | Byte is unmasked (i.e. is compared)
96395  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED | 0x1 | Byte is masked (i.e. not compared)
96396  *
96397  * Field Access Macros:
96398  *
96399  */
96400 /*
96401  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5
96402  *
96403  * Byte is unmasked (i.e. is compared)
96404  */
96405 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED 0x0
96406 /*
96407  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5
96408  *
96409  * Byte is masked (i.e. not compared)
96410  */
96411 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED 0x1
96412 
96413 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
96414 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_LSB 29
96415 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
96416 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_MSB 29
96417 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
96418 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_WIDTH 1
96419 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */
96420 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET_MSK 0x20000000
96421 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */
96422 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_CLR_MSK 0xdfffffff
96423 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
96424 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_RESET 0x0
96425 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 field value from a register. */
96426 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
96427 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value suitable for setting the register. */
96428 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)
96429 
96430 /*
96431  * Field : Source Address - sa
96432  *
96433  * When this bit is enabled, the MAC Address127[47:0] is used to compare with the
96434  * SA fields of the received frame. When this bit is disabled, the MAC
96435  * Address127[47:0] is used to compare with the DA fields of the received frame.
96436  *
96437  * Field Enumeration Values:
96438  *
96439  * Enum | Value | Description
96440  * :-----------------------------------------|:------|:-----------------------------
96441  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD | 0x0 | MAC address compare disabled
96442  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END | 0x1 | MAC address compare enabled
96443  *
96444  * Field Access Macros:
96445  *
96446  */
96447 /*
96448  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA
96449  *
96450  * MAC address compare disabled
96451  */
96452 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD 0x0
96453 /*
96454  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA
96455  *
96456  * MAC address compare enabled
96457  */
96458 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END 0x1
96459 
96460 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
96461 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_LSB 30
96462 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
96463 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_MSB 30
96464 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
96465 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_WIDTH 1
96466 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */
96467 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET_MSK 0x40000000
96468 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */
96469 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_CLR_MSK 0xbfffffff
96470 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
96471 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_RESET 0x0
96472 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA field value from a register. */
96473 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
96474 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value suitable for setting the register. */
96475 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)
96476 
96477 /*
96478  * Field : Address Enable - ae
96479  *
96480  * When this bit is enabled, the address filter block uses the 128th MAC address
96481  * for perfect filtering. When this bit is disabled, the address filter block
96482  * ignores the address for filtering.
96483  *
96484  * Field Enumeration Values:
96485  *
96486  * Enum | Value | Description
96487  * :-----------------------------------------|:------|:--------------------------------------
96488  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD | 0x0 | Second MAC address filtering disabled
96489  * ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END | 0x1 | Second MAC address filtering enabled
96490  *
96491  * Field Access Macros:
96492  *
96493  */
96494 /*
96495  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
96496  *
96497  * Second MAC address filtering disabled
96498  */
96499 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD 0x0
96500 /*
96501  * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
96502  *
96503  * Second MAC address filtering enabled
96504  */
96505 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END 0x1
96506 
96507 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
96508 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_LSB 31
96509 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
96510 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_MSB 31
96511 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
96512 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_WIDTH 1
96513 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
96514 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET_MSK 0x80000000
96515 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
96516 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_CLR_MSK 0x7fffffff
96517 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
96518 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_RESET 0x0
96519 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE field value from a register. */
96520 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
96521 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value suitable for setting the register. */
96522 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)
96523 
96524 #ifndef __ASSEMBLY__
96525 /*
96526  * WARNING: The C register and register group struct declarations are provided for
96527  * convenience and illustrative purposes. They should, however, be used with
96528  * caution as the C language standard provides no guarantees about the alignment or
96529  * atomicity of device memory accesses. The recommended practice for writing
96530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
96531  * alt_write_word() functions.
96532  *
96533  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH.
96534  */
96535 struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s
96536 {
96537  uint32_t addrhi : 16; /* MAC Address127 [47:32] */
96538  uint32_t : 8; /* *UNDEFINED* */
96539  uint32_t mbc_0 : 1; /* Mask Byte Control */
96540  uint32_t mbc_1 : 1; /* Mask Byte Control */
96541  uint32_t mbc_2 : 1; /* Mask Byte Control */
96542  uint32_t mbc_3 : 1; /* Mask Byte Control */
96543  uint32_t mbc_4 : 1; /* Mask Byte Control */
96544  uint32_t mbc_5 : 1; /* Mask Byte Control */
96545  uint32_t sa : 1; /* Source Address */
96546  uint32_t ae : 1; /* Address Enable */
96547 };
96548 
96549 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH. */
96550 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t;
96551 #endif /* __ASSEMBLY__ */
96552 
96553 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register from the beginning of the component. */
96554 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST 0xb78
96555 /* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register. */
96556 #define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST))
96557 
96558 /*
96559  * Register : Register 735 (MAC Address127 Low Register) - MAC_Address127_Low
96560  *
96561  * The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC
96562  * address of the station.
96563  *
96564  * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
96565  * format.
96566  *
96567  * Register Layout
96568  *
96569  * Bits | Access | Reset | Description
96570  * :-------|:-------|:-----------|:----------------------
96571  * [31:0] | RW | 0xffffffff | MAC Address127 [31:0]
96572  *
96573  */
96574 /*
96575  * Field : MAC Address127 [31:0] - addrlo
96576  *
96577  * This field contains the lower 32 bits of the 128th 6-byte MAC address. The
96578  * content of this field is undefined until loaded by software after the
96579  * initialization process.
96580  *
96581  * Field Access Macros:
96582  *
96583  */
96584 /* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
96585 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_LSB 0
96586 /* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
96587 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_MSB 31
96588 /* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
96589 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_WIDTH 32
96590 /* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
96591 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET_MSK 0xffffffff
96592 /* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
96593 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_CLR_MSK 0x00000000
96594 /* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
96595 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_RESET 0xffffffff
96596 /* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO field value from a register. */
96597 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
96598 /* Produces a ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value suitable for setting the register. */
96599 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)
96600 
96601 #ifndef __ASSEMBLY__
96602 /*
96603  * WARNING: The C register and register group struct declarations are provided for
96604  * convenience and illustrative purposes. They should, however, be used with
96605  * caution as the C language standard provides no guarantees about the alignment or
96606  * atomicity of device memory accesses. The recommended practice for writing
96607  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
96608  * alt_write_word() functions.
96609  *
96610  * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW.
96611  */
96612 struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s
96613 {
96614  uint32_t addrlo : 32; /* MAC Address127 [31:0] */
96615 };
96616 
96617 /* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW. */
96618 typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s ALT_EMAC_GMAC_MAC_ADDR127_LOW_t;
96619 #endif /* __ASSEMBLY__ */
96620 
96621 /* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register from the beginning of the component. */
96622 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST 0xb7c
96623 /* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register. */
96624 #define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST))
96625 
96626 #ifndef __ASSEMBLY__
96627 /*
96628  * WARNING: The C register and register group struct declarations are provided for
96629  * convenience and illustrative purposes. They should, however, be used with
96630  * caution as the C language standard provides no guarantees about the alignment or
96631  * atomicity of device memory accesses. The recommended practice for writing
96632  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
96633  * alt_write_word() functions.
96634  *
96635  * The struct declaration for register group ALT_EMAC_GMAC.
96636  */
96637 struct ALT_EMAC_GMAC_s
96638 {
96639  ALT_EMAC_GMAC_MAC_CFG_t MAC_Configuration; /* ALT_EMAC_GMAC_MAC_CFG */
96640  ALT_EMAC_GMAC_MAC_FRM_FLT_t MAC_Frame_Filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */
96641  volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
96642  ALT_EMAC_GMAC_GMII_ADDR_t GMII_Address; /* ALT_EMAC_GMAC_GMII_ADDR */
96643  ALT_EMAC_GMAC_GMII_DATA_t GMII_Data; /* ALT_EMAC_GMAC_GMII_DATA */
96644  ALT_EMAC_GMAC_FLOW_CTL_t Flow_Control; /* ALT_EMAC_GMAC_FLOW_CTL */
96645  ALT_EMAC_GMAC_VLAN_TAG_t VLAN_Tag; /* ALT_EMAC_GMAC_VLAN_TAG */
96646  ALT_EMAC_GMAC_VER_t Version; /* ALT_EMAC_GMAC_VER */
96647  ALT_EMAC_GMAC_DBG_t Debug; /* ALT_EMAC_GMAC_DBG */
96648  volatile uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */
96649  ALT_EMAC_GMAC_LPI_CTL_STAT_t LPI_Control_Status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */
96650  ALT_EMAC_GMAC_LPI_TMRS_CTL_t LPI_Timers_Control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
96651  ALT_EMAC_GMAC_INT_STAT_t Interrupt_Status; /* ALT_EMAC_GMAC_INT_STAT */
96652  ALT_EMAC_GMAC_INT_MSK_t Interrupt_Mask; /* ALT_EMAC_GMAC_INT_MSK */
96653  ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t MAC_Address0_High; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
96654  ALT_EMAC_GMAC_MAC_ADDR0_LOW_t MAC_Address0_Low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
96655  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t MAC_Address1_High; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
96656  ALT_EMAC_GMAC_MAC_ADDR1_LOW_t MAC_Address1_Low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
96657  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t MAC_Address2_High; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
96658  ALT_EMAC_GMAC_MAC_ADDR2_LOW_t MAC_Address2_Low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
96659  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t MAC_Address3_High; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
96660  ALT_EMAC_GMAC_MAC_ADDR3_LOW_t MAC_Address3_Low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
96661  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t MAC_Address4_High; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
96662  ALT_EMAC_GMAC_MAC_ADDR4_LOW_t MAC_Address4_Low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
96663  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t MAC_Address5_High; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
96664  ALT_EMAC_GMAC_MAC_ADDR5_LOW_t MAC_Address5_Low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
96665  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t MAC_Address6_High; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
96666  ALT_EMAC_GMAC_MAC_ADDR6_LOW_t MAC_Address6_Low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
96667  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t MAC_Address7_High; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
96668  ALT_EMAC_GMAC_MAC_ADDR7_LOW_t MAC_Address7_Low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
96669  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t MAC_Address8_High; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
96670  ALT_EMAC_GMAC_MAC_ADDR8_LOW_t MAC_Address8_Low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
96671  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t MAC_Address9_High; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
96672  ALT_EMAC_GMAC_MAC_ADDR9_LOW_t MAC_Address9_Low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
96673  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t MAC_Address10_High; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
96674  ALT_EMAC_GMAC_MAC_ADDR10_LOW_t MAC_Address10_Low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
96675  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t MAC_Address11_High; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
96676  ALT_EMAC_GMAC_MAC_ADDR11_LOW_t MAC_Address11_Low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
96677  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t MAC_Address12_High; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
96678  ALT_EMAC_GMAC_MAC_ADDR12_LOW_t MAC_Address12_Low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
96679  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t MAC_Address13_High; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
96680  ALT_EMAC_GMAC_MAC_ADDR13_LOW_t MAC_Address13_Low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
96681  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t MAC_Address14_High; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
96682  ALT_EMAC_GMAC_MAC_ADDR14_LOW_t MAC_Address14_Low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
96683  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t MAC_Address15_High; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
96684  ALT_EMAC_GMAC_MAC_ADDR15_LOW_t MAC_Address15_Low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
96685  volatile uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */
96686  ALT_EMAC_GMAC_MII_CTL_STAT_t SGMII_RGMII_SMII_Control_Status; /* ALT_EMAC_GMAC_MII_CTL_STAT */
96687  volatile uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */
96688  ALT_EMAC_GMAC_MMC_CTL_t MMC_Control; /* ALT_EMAC_GMAC_MMC_CTL */
96689  ALT_EMAC_GMAC_MMC_RX_INT_t MMC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */
96690  ALT_EMAC_GMAC_MMC_TX_INT_t MMC_Transmit_Interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */
96691  ALT_EMAC_GMAC_MMC_RX_INT_MSK_t MMC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
96692  ALT_EMAC_GMAC_MMC_TX_INT_MSK_t MMC_Transmit_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
96693  ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
96694  ALT_EMAC_GMAC_TXFRMCOUNT_GB_t txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
96695  ALT_EMAC_GMAC_TXBCASTFRMS_G_t txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
96696  ALT_EMAC_GMAC_TXMCASTFRMS_G_t txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
96697  ALT_EMAC_GMAC_TX64OCTETS_GB_t tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */
96698  ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
96699  ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
96700  ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
96701  ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
96702  ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
96703  ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
96704  ALT_EMAC_GMAC_TXMCASTFRMS_GB_t txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
96705  ALT_EMAC_GMAC_TXBCASTFRMS_GB_t txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
96706  ALT_EMAC_GMAC_TXUNDERFLOWERROR_t txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
96707  ALT_EMAC_GMAC_TXSINGLECOL_G_t txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */
96708  ALT_EMAC_GMAC_TXMULTICOL_G_t txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */
96709  ALT_EMAC_GMAC_TXDEFERRED_t txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */
96710  ALT_EMAC_GMAC_TXLATECOL_t txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */
96711  ALT_EMAC_GMAC_TXEXESSCOL_t txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */
96712  ALT_EMAC_GMAC_TXCARRIERERR_t txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */
96713  ALT_EMAC_GMAC_TXOCTETCNT_t txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */
96714  ALT_EMAC_GMAC_TXFRMCOUNT_G_t txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
96715  ALT_EMAC_GMAC_TXEXCESSDEF_t txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */
96716  ALT_EMAC_GMAC_TXPAUSEFRMS_t txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */
96717  ALT_EMAC_GMAC_TXVLANFRMS_G_t txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */
96718  ALT_EMAC_GMAC_TXOVERSIZE_G_t txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */
96719  volatile uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */
96720  ALT_EMAC_GMAC_RXFRMCOUNT_GB_t rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
96721  ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
96722  ALT_EMAC_GMAC_RXOCTETCOUNT_G_t rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
96723  ALT_EMAC_GMAC_RXBCASTFRMS_G_t rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
96724  ALT_EMAC_GMAC_RXMCASTFRMS_G_t rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
96725  ALT_EMAC_GMAC_RXCRCERROR_t rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */
96726  ALT_EMAC_GMAC_RXALIGNMENTERROR_t rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
96727  ALT_EMAC_GMAC_RXRUNTERROR_t rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */
96728  ALT_EMAC_GMAC_RXJABBERERROR_t rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */
96729  ALT_EMAC_GMAC_RXUNDERSIZE_G_t rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
96730  ALT_EMAC_GMAC_RXOVERSIZE_G_t rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */
96731  ALT_EMAC_GMAC_RX64OCTETS_GB_t rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */
96732  ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
96733  ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
96734  ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
96735  ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
96736  ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
96737  ALT_EMAC_GMAC_RXUNICASTFRMS_G_t rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
96738  ALT_EMAC_GMAC_RXLENERROR_t rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */
96739  ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
96740  ALT_EMAC_GMAC_RXPAUSEFRMS_t rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */
96741  ALT_EMAC_GMAC_RXFIFOOVF_t rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */
96742  ALT_EMAC_GMAC_RXVLANFRMS_GB_t rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
96743  ALT_EMAC_GMAC_RXWDERROR_t rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */
96744  ALT_EMAC_GMAC_RXRCVERROR_t rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */
96745  ALT_EMAC_GMAC_RXCTLFRMS_G_t rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */
96746  volatile uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */
96747  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t MMC_IPC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
96748  volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
96749  ALT_EMAC_GMAC_MMC_IPC_RX_INT_t MMC_IPC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
96750  volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
96751  ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
96752  ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
96753  ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
96754  ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
96755  ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
96756  ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
96757  ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
96758  ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
96759  ALT_EMAC_GMAC_RXUDP_GD_FRMS_t rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
96760  ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
96761  ALT_EMAC_GMAC_RXTCP_GD_FRMS_t rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
96762  ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
96763  ALT_EMAC_GMAC_RXICMP_GD_FRMS_t rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
96764  ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
96765  volatile uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */
96766  ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
96767  ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
96768  ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
96769  ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
96770  ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
96771  ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
96772  ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
96773  ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
96774  ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
96775  ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
96776  ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
96777  ALT_EMAC_GMAC_RXTCPERROCTETS_t rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */
96778  ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
96779  ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
96780  volatile uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */
96781  ALT_EMAC_GMAC_L3_L4_CTL0_t L3_L4_Control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */
96782  ALT_EMAC_GMAC_LYR4_ADDR0_t Layer4_Address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */
96783  volatile uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */
96784  ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t Layer3_Addr0_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
96785  ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t Layer3_Addr1_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
96786  ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t Layer3_Addr2_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
96787  ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t Layer3_Addr3_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
96788  volatile uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */
96789  ALT_EMAC_GMAC_L3_L4_CTL1_t L3_L4_Control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */
96790  ALT_EMAC_GMAC_LYR4_ADDR1_t Layer4_Address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */
96791  volatile uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */
96792  ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t Layer3_Addr0_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
96793  ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t Layer3_Addr1_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
96794  ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t Layer3_Addr2_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
96795  ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t Layer3_Addr3_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
96796  volatile uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */
96797  ALT_EMAC_GMAC_L3_L4_CTL2_t L3_L4_Control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */
96798  ALT_EMAC_GMAC_LYR4_ADDR2_t Layer4_Address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */
96799  volatile uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */
96800  ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t Layer3_Addr0_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
96801  ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t Layer3_Addr1_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
96802  ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t Layer3_Addr2_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
96803  ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t Layer3_Addr3_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
96804  volatile uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */
96805  ALT_EMAC_GMAC_L3_L4_CTL3_t L3_L4_Control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */
96806  ALT_EMAC_GMAC_LYR4_ADDR3_t Layer4_Address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */
96807  volatile uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */
96808  ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t Layer3_Addr0_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
96809  ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t Layer3_Addr1_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
96810  ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t Layer3_Addr2_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
96811  ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t Layer3_Addr3_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
96812  volatile uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */
96813  ALT_EMAC_GMAC_HASH_TABLE_REG0_t Hash_Table_Reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
96814  ALT_EMAC_GMAC_HASH_TABLE_REG1_t Hash_Table_Reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
96815  ALT_EMAC_GMAC_HASH_TABLE_REG2_t Hash_Table_Reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
96816  ALT_EMAC_GMAC_HASH_TABLE_REG3_t Hash_Table_Reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
96817  ALT_EMAC_GMAC_HASH_TABLE_REG4_t Hash_Table_Reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
96818  ALT_EMAC_GMAC_HASH_TABLE_REG5_t Hash_Table_Reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
96819  ALT_EMAC_GMAC_HASH_TABLE_REG6_t Hash_Table_Reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
96820  ALT_EMAC_GMAC_HASH_TABLE_REG7_t Hash_Table_Reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
96821  volatile uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */
96822  ALT_EMAC_GMAC_VLAN_INCL_REG_t VLAN_Incl_Reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */
96823  ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t VLAN_Hash_Table_Reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
96824  volatile uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */
96825  ALT_EMAC_GMAC_TS_CTL_t Timestamp_Control; /* ALT_EMAC_GMAC_TS_CTL */
96826  ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t Sub_Second_Increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
96827  ALT_EMAC_GMAC_SYS_TIME_SECS_t System_Time_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */
96828  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t System_Time_Nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
96829  ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t System_Time_Seconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
96830  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t System_Time_Nanoseconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
96831  ALT_EMAC_GMAC_TS_ADDEND_t Timestamp_Addend; /* ALT_EMAC_GMAC_TS_ADDEND */
96832  ALT_EMAC_GMAC_TGT_TIME_SECS_t Target_Time_Seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */
96833  ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t Target_Time_Nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
96834  ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t System_Time_Higher_Word_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
96835  ALT_EMAC_GMAC_TS_STAT_t Timestamp_Status; /* ALT_EMAC_GMAC_TS_STAT */
96836  ALT_EMAC_GMAC_PPS_CTL_t PPS_Control; /* ALT_EMAC_GMAC_PPS_CTL */
96837  ALT_EMAC_GMAC_AUX_TS_NANOSECS_t Auxiliary_Timestamp_Nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
96838  ALT_EMAC_GMAC_AUX_TS_SECS_t Auxiliary_Timestamp_Seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */
96839  volatile uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */
96840  ALT_EMAC_GMAC_PPS0_INTERVAL_t PPS0_Interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */
96841  ALT_EMAC_GMAC_PPS0_WIDTH_t PPS0_Width; /* ALT_EMAC_GMAC_PPS0_WIDTH */
96842  volatile uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */
96843  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t MAC_Address16_High; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
96844  ALT_EMAC_GMAC_MAC_ADDR16_LOW_t MAC_Address16_Low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
96845  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t MAC_Address17_High; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
96846  ALT_EMAC_GMAC_MAC_ADDR17_LOW_t MAC_Address17_Low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
96847  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t MAC_Address18_High; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
96848  ALT_EMAC_GMAC_MAC_ADDR18_LOW_t MAC_Address18_Low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
96849  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t MAC_Address19_High; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
96850  ALT_EMAC_GMAC_MAC_ADDR19_LOW_t MAC_Address19_Low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
96851  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t MAC_Address20_High; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
96852  ALT_EMAC_GMAC_MAC_ADDR20_LOW_t MAC_Address20_Low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
96853  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t MAC_Address21_High; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
96854  ALT_EMAC_GMAC_MAC_ADDR21_LOW_t MAC_Address21_Low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
96855  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t MAC_Address22_High; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
96856  ALT_EMAC_GMAC_MAC_ADDR22_LOW_t MAC_Address22_Low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
96857  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t MAC_Address23_High; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
96858  ALT_EMAC_GMAC_MAC_ADDR23_LOW_t MAC_Address23_Low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
96859  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t MAC_Address24_High; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
96860  ALT_EMAC_GMAC_MAC_ADDR24_LOW_t MAC_Address24_Low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
96861  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t MAC_Address25_High; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
96862  ALT_EMAC_GMAC_MAC_ADDR25_LOW_t MAC_Address25_Low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
96863  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t MAC_Address26_High; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
96864  ALT_EMAC_GMAC_MAC_ADDR26_LOW_t MAC_Address26_Low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
96865  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t MAC_Address27_High; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
96866  ALT_EMAC_GMAC_MAC_ADDR27_LOW_t MAC_Address27_Low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
96867  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t MAC_Address28_High; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
96868  ALT_EMAC_GMAC_MAC_ADDR28_LOW_t MAC_Address28_Low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
96869  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t MAC_Address29_High; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
96870  ALT_EMAC_GMAC_MAC_ADDR29_LOW_t MAC_Address29_Low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
96871  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t MAC_Address30_High; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
96872  ALT_EMAC_GMAC_MAC_ADDR30_LOW_t MAC_Address30_Low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
96873  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t MAC_Address31_High; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
96874  ALT_EMAC_GMAC_MAC_ADDR31_LOW_t MAC_Address31_Low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
96875  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t MAC_Address32_High; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
96876  ALT_EMAC_GMAC_MAC_ADDR32_LOW_t MAC_Address32_Low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
96877  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t MAC_Address33_High; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
96878  ALT_EMAC_GMAC_MAC_ADDR33_LOW_t MAC_Address33_Low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
96879  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t MAC_Address34_High; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
96880  ALT_EMAC_GMAC_MAC_ADDR34_LOW_t MAC_Address34_Low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
96881  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t MAC_Address35_High; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
96882  ALT_EMAC_GMAC_MAC_ADDR35_LOW_t MAC_Address35_Low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
96883  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t MAC_Address36_High; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
96884  ALT_EMAC_GMAC_MAC_ADDR36_LOW_t MAC_Address36_Low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
96885  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t MAC_Address37_High; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
96886  ALT_EMAC_GMAC_MAC_ADDR37_LOW_t MAC_Address37_Low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
96887  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t MAC_Address38_High; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
96888  ALT_EMAC_GMAC_MAC_ADDR38_LOW_t MAC_Address38_Low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
96889  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t MAC_Address39_High; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
96890  ALT_EMAC_GMAC_MAC_ADDR39_LOW_t MAC_Address39_Low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
96891  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t MAC_Address40_High; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
96892  ALT_EMAC_GMAC_MAC_ADDR40_LOW_t MAC_Address40_Low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
96893  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t MAC_Address41_High; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
96894  ALT_EMAC_GMAC_MAC_ADDR41_LOW_t MAC_Address41_Low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
96895  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t MAC_Address42_High; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
96896  ALT_EMAC_GMAC_MAC_ADDR42_LOW_t MAC_Address42_Low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
96897  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t MAC_Address43_High; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
96898  ALT_EMAC_GMAC_MAC_ADDR43_LOW_t MAC_Address43_Low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
96899  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t MAC_Address44_High; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
96900  ALT_EMAC_GMAC_MAC_ADDR44_LOW_t MAC_Address44_Low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
96901  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t MAC_Address45_High; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
96902  ALT_EMAC_GMAC_MAC_ADDR45_LOW_t MAC_Address45_Low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
96903  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t MAC_Address46_High; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
96904  ALT_EMAC_GMAC_MAC_ADDR46_LOW_t MAC_Address46_Low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
96905  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t MAC_Address47_High; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
96906  ALT_EMAC_GMAC_MAC_ADDR47_LOW_t MAC_Address47_Low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
96907  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t MAC_Address48_High; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
96908  ALT_EMAC_GMAC_MAC_ADDR48_LOW_t MAC_Address48_Low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
96909  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t MAC_Address49_High; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
96910  ALT_EMAC_GMAC_MAC_ADDR49_LOW_t MAC_Address49_Low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
96911  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t MAC_Address50_High; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
96912  ALT_EMAC_GMAC_MAC_ADDR50_LOW_t MAC_Address50_Low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
96913  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t MAC_Address51_High; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
96914  ALT_EMAC_GMAC_MAC_ADDR51_LOW_t MAC_Address51_Low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
96915  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t MAC_Address52_High; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
96916  ALT_EMAC_GMAC_MAC_ADDR52_LOW_t MAC_Address52_Low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
96917  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t MAC_Address53_High; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
96918  ALT_EMAC_GMAC_MAC_ADDR53_LOW_t MAC_Address53_Low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
96919  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t MAC_Address54_High; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
96920  ALT_EMAC_GMAC_MAC_ADDR54_LOW_t MAC_Address54_Low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
96921  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t MAC_Address55_High; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
96922  ALT_EMAC_GMAC_MAC_ADDR55_LOW_t MAC_Address55_Low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
96923  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t MAC_Address56_High; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
96924  ALT_EMAC_GMAC_MAC_ADDR56_LOW_t MAC_Address56_Low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
96925  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t MAC_Address57_High; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
96926  ALT_EMAC_GMAC_MAC_ADDR57_LOW_t MAC_Address57_Low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
96927  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t MAC_Address58_High; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
96928  ALT_EMAC_GMAC_MAC_ADDR58_LOW_t MAC_Address58_Low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
96929  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t MAC_Address59_High; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
96930  ALT_EMAC_GMAC_MAC_ADDR59_LOW_t MAC_Address59_Low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
96931  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t MAC_Address60_High; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
96932  ALT_EMAC_GMAC_MAC_ADDR60_LOW_t MAC_Address60_Low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
96933  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t MAC_Address61_High; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
96934  ALT_EMAC_GMAC_MAC_ADDR61_LOW_t MAC_Address61_Low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
96935  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t MAC_Address62_High; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
96936  ALT_EMAC_GMAC_MAC_ADDR62_LOW_t MAC_Address62_Low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
96937  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t MAC_Address63_High; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
96938  ALT_EMAC_GMAC_MAC_ADDR63_LOW_t MAC_Address63_Low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
96939  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t MAC_Address64_High; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
96940  ALT_EMAC_GMAC_MAC_ADDR64_LOW_t MAC_Address64_Low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
96941  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t MAC_Address65_High; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
96942  ALT_EMAC_GMAC_MAC_ADDR65_LOW_t MAC_Address65_Low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
96943  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t MAC_Address66_High; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
96944  ALT_EMAC_GMAC_MAC_ADDR66_LOW_t MAC_Address66_Low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
96945  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t MAC_Address67_High; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
96946  ALT_EMAC_GMAC_MAC_ADDR67_LOW_t MAC_Address67_Low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
96947  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t MAC_Address68_High; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
96948  ALT_EMAC_GMAC_MAC_ADDR68_LOW_t MAC_Address68_Low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
96949  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t MAC_Address69_High; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
96950  ALT_EMAC_GMAC_MAC_ADDR69_LOW_t MAC_Address69_Low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
96951  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t MAC_Address70_High; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
96952  ALT_EMAC_GMAC_MAC_ADDR70_LOW_t MAC_Address70_Low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
96953  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t MAC_Address71_High; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
96954  ALT_EMAC_GMAC_MAC_ADDR71_LOW_t MAC_Address71_Low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
96955  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t MAC_Address72_High; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
96956  ALT_EMAC_GMAC_MAC_ADDR72_LOW_t MAC_Address72_Low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
96957  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t MAC_Address73_High; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
96958  ALT_EMAC_GMAC_MAC_ADDR73_LOW_t MAC_Address73_Low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
96959  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t MAC_Address74_High; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
96960  ALT_EMAC_GMAC_MAC_ADDR74_LOW_t MAC_Address74_Low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
96961  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t MAC_Address75_High; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
96962  ALT_EMAC_GMAC_MAC_ADDR75_LOW_t MAC_Address75_Low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
96963  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t MAC_Address76_High; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
96964  ALT_EMAC_GMAC_MAC_ADDR76_LOW_t MAC_Address76_Low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
96965  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t MAC_Address77_High; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
96966  ALT_EMAC_GMAC_MAC_ADDR77_LOW_t MAC_Address77_Low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
96967  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t MAC_Address78_High; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
96968  ALT_EMAC_GMAC_MAC_ADDR78_LOW_t MAC_Address78_Low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
96969  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t MAC_Address79_High; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
96970  ALT_EMAC_GMAC_MAC_ADDR79_LOW_t MAC_Address79_Low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
96971  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t MAC_Address80_High; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
96972  ALT_EMAC_GMAC_MAC_ADDR80_LOW_t MAC_Address80_Low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
96973  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t MAC_Address81_High; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
96974  ALT_EMAC_GMAC_MAC_ADDR81_LOW_t MAC_Address81_Low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
96975  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t MAC_Address82_High; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
96976  ALT_EMAC_GMAC_MAC_ADDR82_LOW_t MAC_Address82_Low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
96977  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t MAC_Address83_High; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
96978  ALT_EMAC_GMAC_MAC_ADDR83_LOW_t MAC_Address83_Low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
96979  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t MAC_Address84_High; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
96980  ALT_EMAC_GMAC_MAC_ADDR84_LOW_t MAC_Address84_Low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
96981  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t MAC_Address85_High; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
96982  ALT_EMAC_GMAC_MAC_ADDR85_LOW_t MAC_Address85_Low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
96983  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t MAC_Address86_High; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
96984  ALT_EMAC_GMAC_MAC_ADDR86_LOW_t MAC_Address86_Low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
96985  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t MAC_Address87_High; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
96986  ALT_EMAC_GMAC_MAC_ADDR87_LOW_t MAC_Address87_Low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
96987  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t MAC_Address88_High; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
96988  ALT_EMAC_GMAC_MAC_ADDR88_LOW_t MAC_Address88_Low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
96989  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t MAC_Address89_High; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
96990  ALT_EMAC_GMAC_MAC_ADDR89_LOW_t MAC_Address89_Low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
96991  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t MAC_Address90_High; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
96992  ALT_EMAC_GMAC_MAC_ADDR90_LOW_t MAC_Address90_Low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
96993  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t MAC_Address91_High; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
96994  ALT_EMAC_GMAC_MAC_ADDR91_LOW_t MAC_Address91_Low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
96995  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t MAC_Address92_High; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
96996  ALT_EMAC_GMAC_MAC_ADDR92_LOW_t MAC_Address92_Low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
96997  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t MAC_Address93_High; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
96998  ALT_EMAC_GMAC_MAC_ADDR93_LOW_t MAC_Address93_Low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
96999  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t MAC_Address94_High; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
97000  ALT_EMAC_GMAC_MAC_ADDR94_LOW_t MAC_Address94_Low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
97001  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t MAC_Address95_High; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
97002  ALT_EMAC_GMAC_MAC_ADDR95_LOW_t MAC_Address95_Low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
97003  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t MAC_Address96_High; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
97004  ALT_EMAC_GMAC_MAC_ADDR96_LOW_t MAC_Address96_Low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
97005  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t MAC_Address97_High; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
97006  ALT_EMAC_GMAC_MAC_ADDR97_LOW_t MAC_Address97_Low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
97007  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t MAC_Address98_High; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
97008  ALT_EMAC_GMAC_MAC_ADDR98_LOW_t MAC_Address98_Low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
97009  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t MAC_Address99_High; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
97010  ALT_EMAC_GMAC_MAC_ADDR99_LOW_t MAC_Address99_Low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
97011  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t MAC_Address100_High; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
97012  ALT_EMAC_GMAC_MAC_ADDR100_LOW_t MAC_Address100_Low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
97013  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t MAC_Address101_High; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
97014  ALT_EMAC_GMAC_MAC_ADDR101_LOW_t MAC_Address101_Low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
97015  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t MAC_Address102_High; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
97016  ALT_EMAC_GMAC_MAC_ADDR102_LOW_t MAC_Address102_Low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
97017  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t MAC_Address103_High; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
97018  ALT_EMAC_GMAC_MAC_ADDR103_LOW_t MAC_Address103_Low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
97019  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t MAC_Address104_High; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
97020  ALT_EMAC_GMAC_MAC_ADDR104_LOW_t MAC_Address104_Low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
97021  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t MAC_Address105_High; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
97022  ALT_EMAC_GMAC_MAC_ADDR105_LOW_t MAC_Address105_Low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
97023  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t MAC_Address106_High; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
97024  ALT_EMAC_GMAC_MAC_ADDR106_LOW_t MAC_Address106_Low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
97025  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t MAC_Address107_High; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
97026  ALT_EMAC_GMAC_MAC_ADDR107_LOW_t MAC_Address107_Low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
97027  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t MAC_Address108_High; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
97028  ALT_EMAC_GMAC_MAC_ADDR108_LOW_t MAC_Address108_Low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
97029  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t MAC_Address109_High; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
97030  ALT_EMAC_GMAC_MAC_ADDR109_LOW_t MAC_Address109_Low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
97031  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t MAC_Address110_High; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
97032  ALT_EMAC_GMAC_MAC_ADDR110_LOW_t MAC_Address110_Low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
97033  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t MAC_Address111_High; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
97034  ALT_EMAC_GMAC_MAC_ADDR111_LOW_t MAC_Address111_Low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
97035  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t MAC_Address112_High; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
97036  ALT_EMAC_GMAC_MAC_ADDR112_LOW_t MAC_Address112_Low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
97037  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t MAC_Address113_High; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
97038  ALT_EMAC_GMAC_MAC_ADDR113_LOW_t MAC_Address113_Low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
97039  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t MAC_Address114_High; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
97040  ALT_EMAC_GMAC_MAC_ADDR114_LOW_t MAC_Address114_Low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
97041  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t MAC_Address115_High; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
97042  ALT_EMAC_GMAC_MAC_ADDR115_LOW_t MAC_Address115_Low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
97043  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t MAC_Address116_High; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
97044  ALT_EMAC_GMAC_MAC_ADDR116_LOW_t MAC_Address116_Low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
97045  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t MAC_Address117_High; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
97046  ALT_EMAC_GMAC_MAC_ADDR117_LOW_t MAC_Address117_Low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
97047  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t MAC_Address118_High; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
97048  ALT_EMAC_GMAC_MAC_ADDR118_LOW_t MAC_Address118_Low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
97049  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t MAC_Address119_High; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
97050  ALT_EMAC_GMAC_MAC_ADDR119_LOW_t MAC_Address119_Low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
97051  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t MAC_Address120_High; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
97052  ALT_EMAC_GMAC_MAC_ADDR120_LOW_t MAC_Address120_Low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
97053  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t MAC_Address121_High; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
97054  ALT_EMAC_GMAC_MAC_ADDR121_LOW_t MAC_Address121_Low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
97055  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t MAC_Address122_High; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
97056  ALT_EMAC_GMAC_MAC_ADDR122_LOW_t MAC_Address122_Low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
97057  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t MAC_Address123_High; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
97058  ALT_EMAC_GMAC_MAC_ADDR123_LOW_t MAC_Address123_Low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
97059  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t MAC_Address124_High; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
97060  ALT_EMAC_GMAC_MAC_ADDR124_LOW_t MAC_Address124_Low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
97061  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t MAC_Address125_High; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
97062  ALT_EMAC_GMAC_MAC_ADDR125_LOW_t MAC_Address125_Low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
97063  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t MAC_Address126_High; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
97064  ALT_EMAC_GMAC_MAC_ADDR126_LOW_t MAC_Address126_Low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
97065  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t MAC_Address127_High; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
97066  ALT_EMAC_GMAC_MAC_ADDR127_LOW_t MAC_Address127_Low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
97067 };
97068 
97069 /* The typedef declaration for register group ALT_EMAC_GMAC. */
97070 typedef volatile struct ALT_EMAC_GMAC_s ALT_EMAC_GMAC_t;
97071 /* The struct declaration for the raw register contents of register group ALT_EMAC_GMAC. */
97072 struct ALT_EMAC_GMAC_raw_s
97073 {
97074  volatile uint32_t MAC_Configuration; /* ALT_EMAC_GMAC_MAC_CFG */
97075  volatile uint32_t MAC_Frame_Filter; /* ALT_EMAC_GMAC_MAC_FRM_FLT */
97076  uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
97077  volatile uint32_t GMII_Address; /* ALT_EMAC_GMAC_GMII_ADDR */
97078  volatile uint32_t GMII_Data; /* ALT_EMAC_GMAC_GMII_DATA */
97079  volatile uint32_t Flow_Control; /* ALT_EMAC_GMAC_FLOW_CTL */
97080  volatile uint32_t VLAN_Tag; /* ALT_EMAC_GMAC_VLAN_TAG */
97081  volatile uint32_t Version; /* ALT_EMAC_GMAC_VER */
97082  volatile uint32_t Debug; /* ALT_EMAC_GMAC_DBG */
97083  uint32_t _pad_0x28_0x2f[2]; /* *UNDEFINED* */
97084  volatile uint32_t LPI_Control_Status; /* ALT_EMAC_GMAC_LPI_CTL_STAT */
97085  volatile uint32_t LPI_Timers_Control; /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
97086  volatile uint32_t Interrupt_Status; /* ALT_EMAC_GMAC_INT_STAT */
97087  volatile uint32_t Interrupt_Mask; /* ALT_EMAC_GMAC_INT_MSK */
97088  volatile uint32_t MAC_Address0_High; /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
97089  volatile uint32_t MAC_Address0_Low; /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
97090  volatile uint32_t MAC_Address1_High; /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
97091  volatile uint32_t MAC_Address1_Low; /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
97092  volatile uint32_t MAC_Address2_High; /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
97093  volatile uint32_t MAC_Address2_Low; /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
97094  volatile uint32_t MAC_Address3_High; /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
97095  volatile uint32_t MAC_Address3_Low; /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
97096  volatile uint32_t MAC_Address4_High; /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
97097  volatile uint32_t MAC_Address4_Low; /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
97098  volatile uint32_t MAC_Address5_High; /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
97099  volatile uint32_t MAC_Address5_Low; /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
97100  volatile uint32_t MAC_Address6_High; /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
97101  volatile uint32_t MAC_Address6_Low; /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
97102  volatile uint32_t MAC_Address7_High; /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
97103  volatile uint32_t MAC_Address7_Low; /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
97104  volatile uint32_t MAC_Address8_High; /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
97105  volatile uint32_t MAC_Address8_Low; /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
97106  volatile uint32_t MAC_Address9_High; /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
97107  volatile uint32_t MAC_Address9_Low; /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
97108  volatile uint32_t MAC_Address10_High; /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
97109  volatile uint32_t MAC_Address10_Low; /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
97110  volatile uint32_t MAC_Address11_High; /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
97111  volatile uint32_t MAC_Address11_Low; /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
97112  volatile uint32_t MAC_Address12_High; /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
97113  volatile uint32_t MAC_Address12_Low; /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
97114  volatile uint32_t MAC_Address13_High; /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
97115  volatile uint32_t MAC_Address13_Low; /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
97116  volatile uint32_t MAC_Address14_High; /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
97117  volatile uint32_t MAC_Address14_Low; /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
97118  volatile uint32_t MAC_Address15_High; /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
97119  volatile uint32_t MAC_Address15_Low; /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
97120  uint32_t _pad_0xc0_0xd7[6]; /* *UNDEFINED* */
97121  volatile uint32_t SGMII_RGMII_SMII_Control_Status; /* ALT_EMAC_GMAC_MII_CTL_STAT */
97122  uint32_t _pad_0xdc_0xff[9]; /* *UNDEFINED* */
97123  volatile uint32_t MMC_Control; /* ALT_EMAC_GMAC_MMC_CTL */
97124  volatile uint32_t MMC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_RX_INT */
97125  volatile uint32_t MMC_Transmit_Interrupt; /* ALT_EMAC_GMAC_MMC_TX_INT */
97126  volatile uint32_t MMC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
97127  volatile uint32_t MMC_Transmit_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
97128  volatile uint32_t txoctetcount_gb; /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
97129  volatile uint32_t txframecount_gb; /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
97130  volatile uint32_t txbroadcastframes_g; /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
97131  volatile uint32_t txmulticastframes_g; /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
97132  volatile uint32_t tx64octets_gb; /* ALT_EMAC_GMAC_TX64OCTETS_GB */
97133  volatile uint32_t tx65to127octets_gb; /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
97134  volatile uint32_t tx128to255octets_gb; /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
97135  volatile uint32_t tx256to511octets_gb; /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
97136  volatile uint32_t tx512to1023octets_gb; /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
97137  volatile uint32_t tx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
97138  volatile uint32_t txunicastframes_gb; /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
97139  volatile uint32_t txmulticastframes_gb; /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
97140  volatile uint32_t txbroadcastframes_gb; /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
97141  volatile uint32_t txunderflowerror; /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
97142  volatile uint32_t txsinglecol_g; /* ALT_EMAC_GMAC_TXSINGLECOL_G */
97143  volatile uint32_t txmulticol_g; /* ALT_EMAC_GMAC_TXMULTICOL_G */
97144  volatile uint32_t txdeferred; /* ALT_EMAC_GMAC_TXDEFERRED */
97145  volatile uint32_t txlatecol; /* ALT_EMAC_GMAC_TXLATECOL */
97146  volatile uint32_t txexesscol; /* ALT_EMAC_GMAC_TXEXESSCOL */
97147  volatile uint32_t txcarriererr; /* ALT_EMAC_GMAC_TXCARRIERERR */
97148  volatile uint32_t txoctetcnt; /* ALT_EMAC_GMAC_TXOCTETCNT */
97149  volatile uint32_t txframecount_g; /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
97150  volatile uint32_t txexcessdef; /* ALT_EMAC_GMAC_TXEXCESSDEF */
97151  volatile uint32_t txpauseframes; /* ALT_EMAC_GMAC_TXPAUSEFRMS */
97152  volatile uint32_t txvlanframes_g; /* ALT_EMAC_GMAC_TXVLANFRMS_G */
97153  volatile uint32_t txoversize_g; /* ALT_EMAC_GMAC_TXOVERSIZE_G */
97154  uint32_t _pad_0x17c_0x17f; /* *UNDEFINED* */
97155  volatile uint32_t rxframecount_gb; /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
97156  volatile uint32_t rxoctetcount_gb; /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
97157  volatile uint32_t rxoctetcount_g; /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
97158  volatile uint32_t rxbroadcastframes_g; /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
97159  volatile uint32_t rxmulticastframes_g; /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
97160  volatile uint32_t rxcrcerror; /* ALT_EMAC_GMAC_RXCRCERROR */
97161  volatile uint32_t rxalignmenterror; /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
97162  volatile uint32_t rxrunterror; /* ALT_EMAC_GMAC_RXRUNTERROR */
97163  volatile uint32_t rxjabbererror; /* ALT_EMAC_GMAC_RXJABBERERROR */
97164  volatile uint32_t rxundersize_g; /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
97165  volatile uint32_t rxoversize_g; /* ALT_EMAC_GMAC_RXOVERSIZE_G */
97166  volatile uint32_t rx64octets_gb; /* ALT_EMAC_GMAC_RX64OCTETS_GB */
97167  volatile uint32_t rx65to127octets_gb; /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
97168  volatile uint32_t rx128to255octets_gb; /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
97169  volatile uint32_t rx256to511octets_gb; /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
97170  volatile uint32_t rx512to1023octets_gb; /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
97171  volatile uint32_t rx1024tomaxoctets_gb; /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
97172  volatile uint32_t rxunicastframes_g; /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
97173  volatile uint32_t rxlengtherror; /* ALT_EMAC_GMAC_RXLENERROR */
97174  volatile uint32_t rxoutofrangetype; /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
97175  volatile uint32_t rxpauseframes; /* ALT_EMAC_GMAC_RXPAUSEFRMS */
97176  volatile uint32_t rxfifooverflow; /* ALT_EMAC_GMAC_RXFIFOOVF */
97177  volatile uint32_t rxvlanframes_gb; /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
97178  volatile uint32_t rxwatchdogerror; /* ALT_EMAC_GMAC_RXWDERROR */
97179  volatile uint32_t rxrcverror; /* ALT_EMAC_GMAC_RXRCVERROR */
97180  volatile uint32_t rxctrlframes_g; /* ALT_EMAC_GMAC_RXCTLFRMS_G */
97181  uint32_t _pad_0x1e8_0x1ff[6]; /* *UNDEFINED* */
97182  volatile uint32_t MMC_IPC_Receive_Interrupt_Mask; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
97183  uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
97184  volatile uint32_t MMC_IPC_Receive_Interrupt; /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
97185  uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
97186  volatile uint32_t rxipv4_gd_frms; /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
97187  volatile uint32_t rxipv4_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
97188  volatile uint32_t rxipv4_nopay_frms; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
97189  volatile uint32_t rxipv4_frag_frms; /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
97190  volatile uint32_t rxipv4_udsbl_frms; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
97191  volatile uint32_t rxipv6_gd_frms; /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
97192  volatile uint32_t rxipv6_hdrerr_frms; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
97193  volatile uint32_t rxipv6_nopay_frms; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
97194  volatile uint32_t rxudp_gd_frms; /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
97195  volatile uint32_t rxudp_err_frms; /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
97196  volatile uint32_t rxtcp_gd_frms; /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
97197  volatile uint32_t rxtcp_err_frms; /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
97198  volatile uint32_t rxicmp_gd_frms; /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
97199  volatile uint32_t rxicmp_err_frms; /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
97200  uint32_t _pad_0x248_0x24f[2]; /* *UNDEFINED* */
97201  volatile uint32_t rxipv4_gd_octets; /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
97202  volatile uint32_t rxipv4_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
97203  volatile uint32_t rxipv4_nopay_octets; /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
97204  volatile uint32_t rxipv4_frag_octets; /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
97205  volatile uint32_t rxipv4_udsbl_octets; /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
97206  volatile uint32_t rxipv6_gd_octets; /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
97207  volatile uint32_t rxipv6_hdrerr_octets; /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
97208  volatile uint32_t rxipv6_nopay_octets; /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
97209  volatile uint32_t rxudp_gd_octets; /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
97210  volatile uint32_t rxudp_err_octets; /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
97211  volatile uint32_t rxtcp_gd_octets; /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
97212  volatile uint32_t rxtcperroctets; /* ALT_EMAC_GMAC_RXTCPERROCTETS */
97213  volatile uint32_t rxicmp_gd_octets; /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
97214  volatile uint32_t rxicmp_err_octets; /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
97215  uint32_t _pad_0x288_0x3ff[94]; /* *UNDEFINED* */
97216  volatile uint32_t L3_L4_Control0; /* ALT_EMAC_GMAC_L3_L4_CTL0 */
97217  volatile uint32_t Layer4_Address0; /* ALT_EMAC_GMAC_LYR4_ADDR0 */
97218  uint32_t _pad_0x408_0x40f[2]; /* *UNDEFINED* */
97219  volatile uint32_t Layer3_Addr0_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
97220  volatile uint32_t Layer3_Addr1_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
97221  volatile uint32_t Layer3_Addr2_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
97222  volatile uint32_t Layer3_Addr3_Reg0; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
97223  uint32_t _pad_0x420_0x42f[4]; /* *UNDEFINED* */
97224  volatile uint32_t L3_L4_Control1; /* ALT_EMAC_GMAC_L3_L4_CTL1 */
97225  volatile uint32_t Layer4_Address1; /* ALT_EMAC_GMAC_LYR4_ADDR1 */
97226  uint32_t _pad_0x438_0x43f[2]; /* *UNDEFINED* */
97227  volatile uint32_t Layer3_Addr0_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
97228  volatile uint32_t Layer3_Addr1_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
97229  volatile uint32_t Layer3_Addr2_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
97230  volatile uint32_t Layer3_Addr3_Reg1; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
97231  uint32_t _pad_0x450_0x45f[4]; /* *UNDEFINED* */
97232  volatile uint32_t L3_L4_Control2; /* ALT_EMAC_GMAC_L3_L4_CTL2 */
97233  volatile uint32_t Layer4_Address2; /* ALT_EMAC_GMAC_LYR4_ADDR2 */
97234  uint32_t _pad_0x468_0x46f[2]; /* *UNDEFINED* */
97235  volatile uint32_t Layer3_Addr0_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
97236  volatile uint32_t Layer3_Addr1_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
97237  volatile uint32_t Layer3_Addr2_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
97238  volatile uint32_t Layer3_Addr3_Reg2; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
97239  uint32_t _pad_0x480_0x48f[4]; /* *UNDEFINED* */
97240  volatile uint32_t L3_L4_Control3; /* ALT_EMAC_GMAC_L3_L4_CTL3 */
97241  volatile uint32_t Layer4_Address3; /* ALT_EMAC_GMAC_LYR4_ADDR3 */
97242  uint32_t _pad_0x498_0x49f[2]; /* *UNDEFINED* */
97243  volatile uint32_t Layer3_Addr0_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
97244  volatile uint32_t Layer3_Addr1_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
97245  volatile uint32_t Layer3_Addr2_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
97246  volatile uint32_t Layer3_Addr3_Reg3; /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
97247  uint32_t _pad_0x4b0_0x4ff[20]; /* *UNDEFINED* */
97248  volatile uint32_t Hash_Table_Reg0; /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
97249  volatile uint32_t Hash_Table_Reg1; /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
97250  volatile uint32_t Hash_Table_Reg2; /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
97251  volatile uint32_t Hash_Table_Reg3; /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
97252  volatile uint32_t Hash_Table_Reg4; /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
97253  volatile uint32_t Hash_Table_Reg5; /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
97254  volatile uint32_t Hash_Table_Reg6; /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
97255  volatile uint32_t Hash_Table_Reg7; /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
97256  uint32_t _pad_0x520_0x583[25]; /* *UNDEFINED* */
97257  volatile uint32_t VLAN_Incl_Reg; /* ALT_EMAC_GMAC_VLAN_INCL_REG */
97258  volatile uint32_t VLAN_Hash_Table_Reg; /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
97259  uint32_t _pad_0x58c_0x6ff[93]; /* *UNDEFINED* */
97260  volatile uint32_t Timestamp_Control; /* ALT_EMAC_GMAC_TS_CTL */
97261  volatile uint32_t Sub_Second_Increment; /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
97262  volatile uint32_t System_Time_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_SECS */
97263  volatile uint32_t System_Time_Nanoseconds; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
97264  volatile uint32_t System_Time_Seconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
97265  volatile uint32_t System_Time_Nanoseconds_Update; /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
97266  volatile uint32_t Timestamp_Addend; /* ALT_EMAC_GMAC_TS_ADDEND */
97267  volatile uint32_t Target_Time_Seconds; /* ALT_EMAC_GMAC_TGT_TIME_SECS */
97268  volatile uint32_t Target_Time_Nanoseconds; /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
97269  volatile uint32_t System_Time_Higher_Word_Seconds; /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
97270  volatile uint32_t Timestamp_Status; /* ALT_EMAC_GMAC_TS_STAT */
97271  volatile uint32_t PPS_Control; /* ALT_EMAC_GMAC_PPS_CTL */
97272  volatile uint32_t Auxiliary_Timestamp_Nanoseconds; /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
97273  volatile uint32_t Auxiliary_Timestamp_Seconds; /* ALT_EMAC_GMAC_AUX_TS_SECS */
97274  uint32_t _pad_0x738_0x75f[10]; /* *UNDEFINED* */
97275  volatile uint32_t PPS0_Interval; /* ALT_EMAC_GMAC_PPS0_INTERVAL */
97276  volatile uint32_t PPS0_Width; /* ALT_EMAC_GMAC_PPS0_WIDTH */
97277  uint32_t _pad_0x768_0x7ff[38]; /* *UNDEFINED* */
97278  volatile uint32_t MAC_Address16_High; /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
97279  volatile uint32_t MAC_Address16_Low; /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
97280  volatile uint32_t MAC_Address17_High; /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
97281  volatile uint32_t MAC_Address17_Low; /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
97282  volatile uint32_t MAC_Address18_High; /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
97283  volatile uint32_t MAC_Address18_Low; /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
97284  volatile uint32_t MAC_Address19_High; /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
97285  volatile uint32_t MAC_Address19_Low; /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
97286  volatile uint32_t MAC_Address20_High; /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
97287  volatile uint32_t MAC_Address20_Low; /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
97288  volatile uint32_t MAC_Address21_High; /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
97289  volatile uint32_t MAC_Address21_Low; /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
97290  volatile uint32_t MAC_Address22_High; /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
97291  volatile uint32_t MAC_Address22_Low; /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
97292  volatile uint32_t MAC_Address23_High; /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
97293  volatile uint32_t MAC_Address23_Low; /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
97294  volatile uint32_t MAC_Address24_High; /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
97295  volatile uint32_t MAC_Address24_Low; /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
97296  volatile uint32_t MAC_Address25_High; /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
97297  volatile uint32_t MAC_Address25_Low; /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
97298  volatile uint32_t MAC_Address26_High; /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
97299  volatile uint32_t MAC_Address26_Low; /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
97300  volatile uint32_t MAC_Address27_High; /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
97301  volatile uint32_t MAC_Address27_Low; /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
97302  volatile uint32_t MAC_Address28_High; /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
97303  volatile uint32_t MAC_Address28_Low; /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
97304  volatile uint32_t MAC_Address29_High; /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
97305  volatile uint32_t MAC_Address29_Low; /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
97306  volatile uint32_t MAC_Address30_High; /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
97307  volatile uint32_t MAC_Address30_Low; /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
97308  volatile uint32_t MAC_Address31_High; /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
97309  volatile uint32_t MAC_Address31_Low; /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
97310  volatile uint32_t MAC_Address32_High; /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
97311  volatile uint32_t MAC_Address32_Low; /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
97312  volatile uint32_t MAC_Address33_High; /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
97313  volatile uint32_t MAC_Address33_Low; /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
97314  volatile uint32_t MAC_Address34_High; /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
97315  volatile uint32_t MAC_Address34_Low; /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
97316  volatile uint32_t MAC_Address35_High; /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
97317  volatile uint32_t MAC_Address35_Low; /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
97318  volatile uint32_t MAC_Address36_High; /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
97319  volatile uint32_t MAC_Address36_Low; /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
97320  volatile uint32_t MAC_Address37_High; /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
97321  volatile uint32_t MAC_Address37_Low; /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
97322  volatile uint32_t MAC_Address38_High; /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
97323  volatile uint32_t MAC_Address38_Low; /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
97324  volatile uint32_t MAC_Address39_High; /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
97325  volatile uint32_t MAC_Address39_Low; /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
97326  volatile uint32_t MAC_Address40_High; /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
97327  volatile uint32_t MAC_Address40_Low; /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
97328  volatile uint32_t MAC_Address41_High; /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
97329  volatile uint32_t MAC_Address41_Low; /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
97330  volatile uint32_t MAC_Address42_High; /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
97331  volatile uint32_t MAC_Address42_Low; /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
97332  volatile uint32_t MAC_Address43_High; /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
97333  volatile uint32_t MAC_Address43_Low; /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
97334  volatile uint32_t MAC_Address44_High; /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
97335  volatile uint32_t MAC_Address44_Low; /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
97336  volatile uint32_t MAC_Address45_High; /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
97337  volatile uint32_t MAC_Address45_Low; /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
97338  volatile uint32_t MAC_Address46_High; /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
97339  volatile uint32_t MAC_Address46_Low; /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
97340  volatile uint32_t MAC_Address47_High; /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
97341  volatile uint32_t MAC_Address47_Low; /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
97342  volatile uint32_t MAC_Address48_High; /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
97343  volatile uint32_t MAC_Address48_Low; /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
97344  volatile uint32_t MAC_Address49_High; /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
97345  volatile uint32_t MAC_Address49_Low; /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
97346  volatile uint32_t MAC_Address50_High; /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
97347  volatile uint32_t MAC_Address50_Low; /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
97348  volatile uint32_t MAC_Address51_High; /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
97349  volatile uint32_t MAC_Address51_Low; /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
97350  volatile uint32_t MAC_Address52_High; /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
97351  volatile uint32_t MAC_Address52_Low; /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
97352  volatile uint32_t MAC_Address53_High; /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
97353  volatile uint32_t MAC_Address53_Low; /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
97354  volatile uint32_t MAC_Address54_High; /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
97355  volatile uint32_t MAC_Address54_Low; /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
97356  volatile uint32_t MAC_Address55_High; /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
97357  volatile uint32_t MAC_Address55_Low; /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
97358  volatile uint32_t MAC_Address56_High; /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
97359  volatile uint32_t MAC_Address56_Low; /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
97360  volatile uint32_t MAC_Address57_High; /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
97361  volatile uint32_t MAC_Address57_Low; /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
97362  volatile uint32_t MAC_Address58_High; /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
97363  volatile uint32_t MAC_Address58_Low; /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
97364  volatile uint32_t MAC_Address59_High; /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
97365  volatile uint32_t MAC_Address59_Low; /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
97366  volatile uint32_t MAC_Address60_High; /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
97367  volatile uint32_t MAC_Address60_Low; /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
97368  volatile uint32_t MAC_Address61_High; /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
97369  volatile uint32_t MAC_Address61_Low; /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
97370  volatile uint32_t MAC_Address62_High; /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
97371  volatile uint32_t MAC_Address62_Low; /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
97372  volatile uint32_t MAC_Address63_High; /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
97373  volatile uint32_t MAC_Address63_Low; /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
97374  volatile uint32_t MAC_Address64_High; /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
97375  volatile uint32_t MAC_Address64_Low; /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
97376  volatile uint32_t MAC_Address65_High; /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
97377  volatile uint32_t MAC_Address65_Low; /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
97378  volatile uint32_t MAC_Address66_High; /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
97379  volatile uint32_t MAC_Address66_Low; /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
97380  volatile uint32_t MAC_Address67_High; /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
97381  volatile uint32_t MAC_Address67_Low; /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
97382  volatile uint32_t MAC_Address68_High; /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
97383  volatile uint32_t MAC_Address68_Low; /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
97384  volatile uint32_t MAC_Address69_High; /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
97385  volatile uint32_t MAC_Address69_Low; /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
97386  volatile uint32_t MAC_Address70_High; /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
97387  volatile uint32_t MAC_Address70_Low; /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
97388  volatile uint32_t MAC_Address71_High; /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
97389  volatile uint32_t MAC_Address71_Low; /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
97390  volatile uint32_t MAC_Address72_High; /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
97391  volatile uint32_t MAC_Address72_Low; /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
97392  volatile uint32_t MAC_Address73_High; /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
97393  volatile uint32_t MAC_Address73_Low; /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
97394  volatile uint32_t MAC_Address74_High; /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
97395  volatile uint32_t MAC_Address74_Low; /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
97396  volatile uint32_t MAC_Address75_High; /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
97397  volatile uint32_t MAC_Address75_Low; /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
97398  volatile uint32_t MAC_Address76_High; /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
97399  volatile uint32_t MAC_Address76_Low; /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
97400  volatile uint32_t MAC_Address77_High; /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
97401  volatile uint32_t MAC_Address77_Low; /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
97402  volatile uint32_t MAC_Address78_High; /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
97403  volatile uint32_t MAC_Address78_Low; /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
97404  volatile uint32_t MAC_Address79_High; /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
97405  volatile uint32_t MAC_Address79_Low; /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
97406  volatile uint32_t MAC_Address80_High; /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
97407  volatile uint32_t MAC_Address80_Low; /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
97408  volatile uint32_t MAC_Address81_High; /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
97409  volatile uint32_t MAC_Address81_Low; /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
97410  volatile uint32_t MAC_Address82_High; /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
97411  volatile uint32_t MAC_Address82_Low; /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
97412  volatile uint32_t MAC_Address83_High; /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
97413  volatile uint32_t MAC_Address83_Low; /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
97414  volatile uint32_t MAC_Address84_High; /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
97415  volatile uint32_t MAC_Address84_Low; /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
97416  volatile uint32_t MAC_Address85_High; /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
97417  volatile uint32_t MAC_Address85_Low; /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
97418  volatile uint32_t MAC_Address86_High; /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
97419  volatile uint32_t MAC_Address86_Low; /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
97420  volatile uint32_t MAC_Address87_High; /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
97421  volatile uint32_t MAC_Address87_Low; /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
97422  volatile uint32_t MAC_Address88_High; /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
97423  volatile uint32_t MAC_Address88_Low; /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
97424  volatile uint32_t MAC_Address89_High; /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
97425  volatile uint32_t MAC_Address89_Low; /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
97426  volatile uint32_t MAC_Address90_High; /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
97427  volatile uint32_t MAC_Address90_Low; /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
97428  volatile uint32_t MAC_Address91_High; /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
97429  volatile uint32_t MAC_Address91_Low; /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
97430  volatile uint32_t MAC_Address92_High; /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
97431  volatile uint32_t MAC_Address92_Low; /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
97432  volatile uint32_t MAC_Address93_High; /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
97433  volatile uint32_t MAC_Address93_Low; /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
97434  volatile uint32_t MAC_Address94_High; /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
97435  volatile uint32_t MAC_Address94_Low; /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
97436  volatile uint32_t MAC_Address95_High; /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
97437  volatile uint32_t MAC_Address95_Low; /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
97438  volatile uint32_t MAC_Address96_High; /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
97439  volatile uint32_t MAC_Address96_Low; /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
97440  volatile uint32_t MAC_Address97_High; /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
97441  volatile uint32_t MAC_Address97_Low; /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
97442  volatile uint32_t MAC_Address98_High; /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
97443  volatile uint32_t MAC_Address98_Low; /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
97444  volatile uint32_t MAC_Address99_High; /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
97445  volatile uint32_t MAC_Address99_Low; /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
97446  volatile uint32_t MAC_Address100_High; /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
97447  volatile uint32_t MAC_Address100_Low; /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
97448  volatile uint32_t MAC_Address101_High; /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
97449  volatile uint32_t MAC_Address101_Low; /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
97450  volatile uint32_t MAC_Address102_High; /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
97451  volatile uint32_t MAC_Address102_Low; /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
97452  volatile uint32_t MAC_Address103_High; /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
97453  volatile uint32_t MAC_Address103_Low; /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
97454  volatile uint32_t MAC_Address104_High; /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
97455  volatile uint32_t MAC_Address104_Low; /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
97456  volatile uint32_t MAC_Address105_High; /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
97457  volatile uint32_t MAC_Address105_Low; /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
97458  volatile uint32_t MAC_Address106_High; /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
97459  volatile uint32_t MAC_Address106_Low; /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
97460  volatile uint32_t MAC_Address107_High; /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
97461  volatile uint32_t MAC_Address107_Low; /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
97462  volatile uint32_t MAC_Address108_High; /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
97463  volatile uint32_t MAC_Address108_Low; /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
97464  volatile uint32_t MAC_Address109_High; /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
97465  volatile uint32_t MAC_Address109_Low; /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
97466  volatile uint32_t MAC_Address110_High; /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
97467  volatile uint32_t MAC_Address110_Low; /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
97468  volatile uint32_t MAC_Address111_High; /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
97469  volatile uint32_t MAC_Address111_Low; /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
97470  volatile uint32_t MAC_Address112_High; /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
97471  volatile uint32_t MAC_Address112_Low; /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
97472  volatile uint32_t MAC_Address113_High; /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
97473  volatile uint32_t MAC_Address113_Low; /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
97474  volatile uint32_t MAC_Address114_High; /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
97475  volatile uint32_t MAC_Address114_Low; /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
97476  volatile uint32_t MAC_Address115_High; /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
97477  volatile uint32_t MAC_Address115_Low; /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
97478  volatile uint32_t MAC_Address116_High; /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
97479  volatile uint32_t MAC_Address116_Low; /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
97480  volatile uint32_t MAC_Address117_High; /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
97481  volatile uint32_t MAC_Address117_Low; /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
97482  volatile uint32_t MAC_Address118_High; /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
97483  volatile uint32_t MAC_Address118_Low; /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
97484  volatile uint32_t MAC_Address119_High; /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
97485  volatile uint32_t MAC_Address119_Low; /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
97486  volatile uint32_t MAC_Address120_High; /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
97487  volatile uint32_t MAC_Address120_Low; /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
97488  volatile uint32_t MAC_Address121_High; /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
97489  volatile uint32_t MAC_Address121_Low; /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
97490  volatile uint32_t MAC_Address122_High; /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
97491  volatile uint32_t MAC_Address122_Low; /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
97492  volatile uint32_t MAC_Address123_High; /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
97493  volatile uint32_t MAC_Address123_Low; /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
97494  volatile uint32_t MAC_Address124_High; /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
97495  volatile uint32_t MAC_Address124_Low; /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
97496  volatile uint32_t MAC_Address125_High; /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
97497  volatile uint32_t MAC_Address125_Low; /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
97498  volatile uint32_t MAC_Address126_High; /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
97499  volatile uint32_t MAC_Address126_Low; /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
97500  volatile uint32_t MAC_Address127_High; /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
97501  volatile uint32_t MAC_Address127_Low; /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
97502 };
97503 
97504 /* The typedef declaration for the raw register contents of register group ALT_EMAC_GMAC. */
97505 typedef volatile struct ALT_EMAC_GMAC_raw_s ALT_EMAC_GMAC_raw_t;
97506 #endif /* __ASSEMBLY__ */
97507 
97508 
97509 /*
97510  * Register Group : DMA Register Group - ALT_EMAC_DMA
97511  * DMA Register Group
97512  *
97513  * DMA Register Group
97514  *
97515  */
97516 /*
97517  * Register : Register 0 (Bus Mode Register) - Bus_Mode
97518  *
97519  * The Bus Mode register establishes the bus operating modes for the DMA.
97520  *
97521  * Register Layout
97522  *
97523  * Bits | Access | Reset | Description
97524  * :--------|:-------|:------|:--------------------------
97525  * [0] | RW | 0x1 | Software Reset
97526  * [1] | ??? | 0x0 | *UNDEFINED*
97527  * [6:2] | RW | 0x0 | Descriptor Skip Length
97528  * [7] | RW | 0x0 | Alternate Descriptor Size
97529  * [13:8] | RW | 0x1 | Programmable Burst Length
97530  * [15:14] | ??? | 0x0 | *UNDEFINED*
97531  * [16] | RW | 0x0 | Fixed Burst
97532  * [22:17] | RW | 0x1 | Rx DMA PBL
97533  * [23] | RW | 0x0 | Use Separate PBL
97534  * [24] | RW | 0x0 | 8xPBL Mode
97535  * [25] | RW | 0x0 | Address Aligned Beats
97536  * [31:26] | ??? | 0x0 | *UNDEFINED*
97537  *
97538  */
97539 /*
97540  * Field : Software Reset - swr
97541  *
97542  * When this bit is set, the MAC DMA Controller resets the logic and all internal
97543  * registers of the MAC. It is cleared automatically after the reset operation has
97544  * completed in all of the EMAC clock domains. Before reprogramming any register of
97545  * the EMAC, you should read a zero (0) value in this bit .
97546  *
97547  * Note:
97548  *
97549  * * The Software reset function is driven only by this bit. Bit 0 of Register 64
97550  * (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register)
97551  * has no impact on the Software reset function.
97552  *
97553  * * The reset operation is completed only when all resets in all active clock
97554  * domains are de-asserted. Therefore, it is essential that all the PHY inputs
97555  * clocks (applicable for the selected PHY interface) are present for the
97556  * software reset completion.
97557  *
97558  * Field Enumeration Values:
97559  *
97560  * Enum | Value | Description
97561  * :----------------------------------|:------|:--------------------------------
97562  * ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST | 0x0 | MAC DMA Controller Clears Logic
97563  * ALT_EMAC_DMA_BUS_MOD_SWR_E_RST | 0x1 | MAC DMA Controller Resets Logic
97564  *
97565  * Field Access Macros:
97566  *
97567  */
97568 /*
97569  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
97570  *
97571  * MAC DMA Controller Clears Logic
97572  */
97573 #define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0
97574 /*
97575  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
97576  *
97577  * MAC DMA Controller Resets Logic
97578  */
97579 #define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1
97580 
97581 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
97582 #define ALT_EMAC_DMA_BUS_MOD_SWR_LSB 0
97583 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
97584 #define ALT_EMAC_DMA_BUS_MOD_SWR_MSB 0
97585 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
97586 #define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH 1
97587 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
97588 #define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK 0x00000001
97589 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
97590 #define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK 0xfffffffe
97591 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
97592 #define ALT_EMAC_DMA_BUS_MOD_SWR_RESET 0x1
97593 /* Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register. */
97594 #define ALT_EMAC_DMA_BUS_MOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
97595 /* Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register. */
97596 #define ALT_EMAC_DMA_BUS_MOD_SWR_SET(value) (((value) << 0) & 0x00000001)
97597 
97598 /*
97599  * Field : Descriptor Skip Length - dsl
97600  *
97601  * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit,
97602  * 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address
97603  * skipping starts from the end of current descriptor to the start of next
97604  * descriptor. When the DSL value is equal to zero, then the descriptor table is
97605  * taken as contiguous by the DMA in Ring mode.
97606  *
97607  * Field Access Macros:
97608  *
97609  */
97610 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
97611 #define ALT_EMAC_DMA_BUS_MOD_DSL_LSB 2
97612 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
97613 #define ALT_EMAC_DMA_BUS_MOD_DSL_MSB 6
97614 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
97615 #define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH 5
97616 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
97617 #define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK 0x0000007c
97618 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
97619 #define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK 0xffffff83
97620 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
97621 #define ALT_EMAC_DMA_BUS_MOD_DSL_RESET 0x0
97622 /* Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register. */
97623 #define ALT_EMAC_DMA_BUS_MOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
97624 /* Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register. */
97625 #define ALT_EMAC_DMA_BUS_MOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
97626 
97627 /*
97628  * Field : Alternate Descriptor Size - atds
97629  *
97630  * When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS).
97631  * This is required when the Advanced Timestamp feature or the IPC Full Offload
97632  * Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not
97633  * required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2)
97634  * features are not enabled. In such cases, you can use the 16 bytes descriptor to
97635  * save 4 bytes of memory.
97636  *
97637  * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).
97638  *
97639  * This bit preserves the backward compatibility for the descriptor size. In
97640  * versions prior to 3.50a, the descriptor size is 16 bytes for both normal and
97641  * enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes
97642  * because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2)
97643  * features.
97644  *
97645  * Field Enumeration Values:
97646  *
97647  * Enum | Value | Description
97648  * :-----------------------------------|:------|:--------------------------------
97649  * ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST | 0x0 | MAC DMA Controller Clears Logic
97650  * ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST | 0x1 | MAC DMA Controller Resets Logic
97651  *
97652  * Field Access Macros:
97653  *
97654  */
97655 /*
97656  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
97657  *
97658  * MAC DMA Controller Clears Logic
97659  */
97660 #define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0
97661 /*
97662  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
97663  *
97664  * MAC DMA Controller Resets Logic
97665  */
97666 #define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1
97667 
97668 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
97669 #define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB 7
97670 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
97671 #define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB 7
97672 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
97673 #define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH 1
97674 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
97675 #define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK 0x00000080
97676 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
97677 #define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK 0xffffff7f
97678 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
97679 #define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET 0x0
97680 /* Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register. */
97681 #define ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value) (((value) & 0x00000080) >> 7)
97682 /* Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register. */
97683 #define ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value) (((value) << 7) & 0x00000080)
97684 
97685 /*
97686  * Field : Programmable Burst Length - pbl
97687  *
97688  * These bits indicate the maximum number of beats to be transferred in one DMA
97689  * transaction. This is the maximum value that is used in a single block Read or
97690  * Write. The DMA always attempts to burst as specified in PBL each time it starts
97691  * a Burst transfer on the host bus. PBL can be programmed with permissible values
97692  * of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When
97693  * USP is set high, this PBL value is applicable only for Tx DMA transactions.
97694  *
97695  * If the number of beats to be transferred is more than 32, then perform the
97696  * following steps:
97697  *
97698  * 1. Set the 8xPBL mode.
97699  *
97700  * 2. Set the PBL.
97701  *
97702  * For example, if the maximum number of beats to be transferred is 64, then first
97703  * set 8xPBL to 1 and then set PBL to 8. The PBL values have the following
97704  * limitation: The maximum number of possible beats (PBL) is limited by the size of
97705  * the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The
97706  * FIFO has a constraint that the maximum beat supported is half the depth of the
97707  * FIFO, except when specified.
97708  *
97709  * Field Access Macros:
97710  *
97711  */
97712 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
97713 #define ALT_EMAC_DMA_BUS_MOD_PBL_LSB 8
97714 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
97715 #define ALT_EMAC_DMA_BUS_MOD_PBL_MSB 13
97716 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
97717 #define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH 6
97718 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
97719 #define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK 0x00003f00
97720 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
97721 #define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK 0xffffc0ff
97722 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
97723 #define ALT_EMAC_DMA_BUS_MOD_PBL_RESET 0x1
97724 /* Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register. */
97725 #define ALT_EMAC_DMA_BUS_MOD_PBL_GET(value) (((value) & 0x00003f00) >> 8)
97726 /* Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register. */
97727 #define ALT_EMAC_DMA_BUS_MOD_PBL_SET(value) (((value) << 8) & 0x00003f00)
97728 
97729 /*
97730  * Field : Fixed Burst - fb
97731  *
97732  * This bit controls whether the AXI Master interface performs fixed burst
97733  * transfers or not. When set, the AXI interface uses FIXED bursts during the start
97734  * of the normal burst transfers. When reset, the AXI interface uses SINGLE and
97735  * INCR burst transfer operations.
97736  *
97737  * For more information, see Bit 0 (UNDEFINED) of the AXI Bus Mode register.
97738  *
97739  * Field Enumeration Values:
97740  *
97741  * Enum | Value | Description
97742  * :-------------------------------------|:------|:-----------------------------
97743  * ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB | 0x0 | SINGLE or INCR Burst
97744  * ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 | 0x1 | FIXED Burst (1, 4, 8, or 16)
97745  *
97746  * Field Access Macros:
97747  *
97748  */
97749 /*
97750  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
97751  *
97752  * SINGLE or INCR Burst
97753  */
97754 #define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0
97755 /*
97756  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
97757  *
97758  * FIXED Burst (1, 4, 8, or 16)
97759  */
97760 #define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1
97761 
97762 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
97763 #define ALT_EMAC_DMA_BUS_MOD_FB_LSB 16
97764 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
97765 #define ALT_EMAC_DMA_BUS_MOD_FB_MSB 16
97766 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
97767 #define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH 1
97768 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
97769 #define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK 0x00010000
97770 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
97771 #define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK 0xfffeffff
97772 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
97773 #define ALT_EMAC_DMA_BUS_MOD_FB_RESET 0x0
97774 /* Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register. */
97775 #define ALT_EMAC_DMA_BUS_MOD_FB_GET(value) (((value) & 0x00010000) >> 16)
97776 /* Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register. */
97777 #define ALT_EMAC_DMA_BUS_MOD_FB_SET(value) (((value) << 16) & 0x00010000)
97778 
97779 /*
97780  * Field : Rx DMA PBL - rpbl
97781  *
97782  * This field indicates the maximum number of beats to be transferred in one Rx DMA
97783  * transaction. This is the maximum value that is used in a single block Read or
97784  * Write.
97785  *
97786  * The Rx DMA always attempts to burst as specified in the RPBL bit each time it
97787  * starts a Burst transfer on the host bus. You can program RPBL with values of 1,
97788  * 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
97789  *
97790  * This field is valid and applicable only when USP is set high.
97791  *
97792  * Field Enumeration Values:
97793  *
97794  * Enum | Value | Description
97795  * :---------------------------------------|:------|:---------------------------------------
97796  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 | 0x1 | Beats Trans. in one Rx DMA Transaction
97797  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 | 0x2 | Beats Trans. in one Rx DMA Transaction
97798  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 | 0x4 | Beats Trans. in one Rx DMA Transaction
97799  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 | 0x8 | Beats Trans. in one Rx DMA Transaction
97800  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 | 0x10 | Beats Trans. in one Rx DMA Transaction
97801  * ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 | 0x20 | Beats Trans. in one Rx DMA Transaction
97802  *
97803  * Field Access Macros:
97804  *
97805  */
97806 /*
97807  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97808  *
97809  * Beats Trans. in one Rx DMA Transaction
97810  */
97811 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1
97812 /*
97813  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97814  *
97815  * Beats Trans. in one Rx DMA Transaction
97816  */
97817 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2
97818 /*
97819  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97820  *
97821  * Beats Trans. in one Rx DMA Transaction
97822  */
97823 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4
97824 /*
97825  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97826  *
97827  * Beats Trans. in one Rx DMA Transaction
97828  */
97829 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8
97830 /*
97831  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97832  *
97833  * Beats Trans. in one Rx DMA Transaction
97834  */
97835 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10
97836 /*
97837  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
97838  *
97839  * Beats Trans. in one Rx DMA Transaction
97840  */
97841 #define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20
97842 
97843 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
97844 #define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB 17
97845 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
97846 #define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB 22
97847 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
97848 #define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH 6
97849 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
97850 #define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK 0x007e0000
97851 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
97852 #define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK 0xff81ffff
97853 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
97854 #define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET 0x1
97855 /* Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register. */
97856 #define ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value) (((value) & 0x007e0000) >> 17)
97857 /* Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register. */
97858 #define ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value) (((value) << 17) & 0x007e0000)
97859 
97860 /*
97861  * Field : Use Separate PBL - usp
97862  *
97863  * When set high, this bit configures the Rx DMA to use the value configured in
97864  * Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA
97865  * operations.
97866  *
97867  * When reset to low, the PBL value in Bits[13:8] is applicable for both DMA
97868  * engines.
97869  *
97870  * Field Enumeration Values:
97871  *
97872  * Enum | Value | Description
97873  * :--------------------------------|:------|:----------------------------
97874  * ALT_EMAC_DMA_BUS_MOD_USP_E_DISD | 0x0 | Configures TX RX DMA to PBL
97875  * ALT_EMAC_DMA_BUS_MOD_USP_E_END | 0x1 | Configures TX DMA to PBL
97876  *
97877  * Field Access Macros:
97878  *
97879  */
97880 /*
97881  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
97882  *
97883  * Configures TX RX DMA to PBL
97884  */
97885 #define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0
97886 /*
97887  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
97888  *
97889  * Configures TX DMA to PBL
97890  */
97891 #define ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1
97892 
97893 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
97894 #define ALT_EMAC_DMA_BUS_MOD_USP_LSB 23
97895 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
97896 #define ALT_EMAC_DMA_BUS_MOD_USP_MSB 23
97897 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
97898 #define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH 1
97899 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
97900 #define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK 0x00800000
97901 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
97902 #define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK 0xff7fffff
97903 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
97904 #define ALT_EMAC_DMA_BUS_MOD_USP_RESET 0x0
97905 /* Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register. */
97906 #define ALT_EMAC_DMA_BUS_MOD_USP_GET(value) (((value) & 0x00800000) >> 23)
97907 /* Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register. */
97908 #define ALT_EMAC_DMA_BUS_MOD_USP_SET(value) (((value) << 23) & 0x00800000)
97909 
97910 /*
97911  * Field : 8xPBL Mode - eightxpbl
97912  *
97913  * When set high, this bit multiplies the programmed PBL value (Bits[22:17] and
97914  * Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
97915  * 128, and 256 beats depending on the PBL value.
97916  *
97917  * Field Enumeration Values:
97918  *
97919  * Enum | Value | Description
97920  * :--------------------------------------|:------|:--------------------------
97921  * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD | 0x0 | Non Multiply Mode
97922  * ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END | 0x1 | Multiplies PBL value by 8
97923  *
97924  * Field Access Macros:
97925  *
97926  */
97927 /*
97928  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
97929  *
97930  * Non Multiply Mode
97931  */
97932 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0
97933 /*
97934  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
97935  *
97936  * Multiplies PBL value by 8
97937  */
97938 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1
97939 
97940 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
97941 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB 24
97942 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
97943 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB 24
97944 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
97945 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH 1
97946 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
97947 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK 0x01000000
97948 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
97949 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK 0xfeffffff
97950 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
97951 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET 0x0
97952 /* Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register. */
97953 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value) (((value) & 0x01000000) >> 24)
97954 /* Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register. */
97955 #define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000)
97956 
97957 /*
97958  * Field : Address Aligned Beats - aal
97959  *
97960  * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface
97961  * generates all bursts aligned to the start address LS bits. If the FB bit is
97962  * equal to 0, the first burst (accessing the data buffer's start address) is not
97963  * aligned, but subsequent bursts are aligned to the address.
97964  *
97965  * Field Enumeration Values:
97966  *
97967  * Enum | Value | Description
97968  * :--------------------------------|:------|:----------------------------------------
97969  * ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD | 0x0 | No Address-Aligned Beats
97970  * ALT_EMAC_DMA_BUS_MOD_AAL_E_END | 0x1 | Address-Aligned Beats (dependent on FB)
97971  *
97972  * Field Access Macros:
97973  *
97974  */
97975 /*
97976  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
97977  *
97978  * No Address-Aligned Beats
97979  */
97980 #define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0
97981 /*
97982  * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
97983  *
97984  * Address-Aligned Beats (dependent on FB)
97985  */
97986 #define ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1
97987 
97988 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
97989 #define ALT_EMAC_DMA_BUS_MOD_AAL_LSB 25
97990 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
97991 #define ALT_EMAC_DMA_BUS_MOD_AAL_MSB 25
97992 /* The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
97993 #define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH 1
97994 /* The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
97995 #define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK 0x02000000
97996 /* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
97997 #define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK 0xfdffffff
97998 /* The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
97999 #define ALT_EMAC_DMA_BUS_MOD_AAL_RESET 0x0
98000 /* Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register. */
98001 #define ALT_EMAC_DMA_BUS_MOD_AAL_GET(value) (((value) & 0x02000000) >> 25)
98002 /* Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register. */
98003 #define ALT_EMAC_DMA_BUS_MOD_AAL_SET(value) (((value) << 25) & 0x02000000)
98004 
98005 #ifndef __ASSEMBLY__
98006 /*
98007  * WARNING: The C register and register group struct declarations are provided for
98008  * convenience and illustrative purposes. They should, however, be used with
98009  * caution as the C language standard provides no guarantees about the alignment or
98010  * atomicity of device memory accesses. The recommended practice for writing
98011  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98012  * alt_write_word() functions.
98013  *
98014  * The struct declaration for register ALT_EMAC_DMA_BUS_MOD.
98015  */
98016 struct ALT_EMAC_DMA_BUS_MOD_s
98017 {
98018  uint32_t swr : 1; /* Software Reset */
98019  uint32_t : 1; /* *UNDEFINED* */
98020  uint32_t dsl : 5; /* Descriptor Skip Length */
98021  uint32_t atds : 1; /* Alternate Descriptor Size */
98022  uint32_t pbl : 6; /* Programmable Burst Length */
98023  uint32_t : 2; /* *UNDEFINED* */
98024  uint32_t fb : 1; /* Fixed Burst */
98025  uint32_t rpbl : 6; /* Rx DMA PBL */
98026  uint32_t usp : 1; /* Use Separate PBL */
98027  uint32_t eightxpbl : 1; /* 8xPBL Mode */
98028  uint32_t aal : 1; /* Address Aligned Beats */
98029  uint32_t : 6; /* *UNDEFINED* */
98030 };
98031 
98032 /* The typedef declaration for register ALT_EMAC_DMA_BUS_MOD. */
98033 typedef volatile struct ALT_EMAC_DMA_BUS_MOD_s ALT_EMAC_DMA_BUS_MOD_t;
98034 #endif /* __ASSEMBLY__ */
98035 
98036 /* The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component. */
98037 #define ALT_EMAC_DMA_BUS_MOD_OFST 0x0
98038 /* The address of the ALT_EMAC_DMA_BUS_MOD register. */
98039 #define ALT_EMAC_DMA_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST))
98040 
98041 /*
98042  * Register : Register 1 (Transmit Poll Demand Register) - Transmit_Poll_Demand
98043  *
98044  * The Transmit Poll Demand register enables the Tx DMA to check whether or not the
98045  * DMA owns the current descriptor. The Transmit Poll Demand command is given to
98046  * wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the
98047  * Suspend mode because of an Underflow error in a transmitted frame or the
98048  * unavailability of descriptors owned by it. You can give this command anytime and
98049  * the Tx DMA resets this command when it again starts fetching the current
98050  * descriptor from host memory.
98051  *
98052  * Register Layout
98053  *
98054  * Bits | Access | Reset | Description
98055  * :-------|:-------|:------|:---------------------
98056  * [31:0] | RW | 0x0 | Transmit Poll Demand
98057  *
98058  */
98059 /*
98060  * Field : Transmit Poll Demand - tpd
98061  *
98062  * When these bits are written with any value, the DMA reads the current descriptor
98063  * pointed to by Register 18 (Current Host Transmit Descriptor Register). If that
98064  * descriptor is not available (owned by the Host), the transmission returns to the
98065  * Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If
98066  * the descriptor is available, the transmission resumes.
98067  *
98068  * Field Access Macros:
98069  *
98070  */
98071 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
98072 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_LSB 0
98073 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
98074 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_MSB 31
98075 /* The width in bits of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
98076 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_WIDTH 32
98077 /* The mask used to set the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
98078 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET_MSK 0xffffffff
98079 /* The mask used to clear the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
98080 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_CLR_MSK 0x00000000
98081 /* The reset value of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
98082 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_RESET 0x0
98083 /* Extracts the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD field value from a register. */
98084 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0)
98085 /* Produces a ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value suitable for setting the register. */
98086 #define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff)
98087 
98088 #ifndef __ASSEMBLY__
98089 /*
98090  * WARNING: The C register and register group struct declarations are provided for
98091  * convenience and illustrative purposes. They should, however, be used with
98092  * caution as the C language standard provides no guarantees about the alignment or
98093  * atomicity of device memory accesses. The recommended practice for writing
98094  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98095  * alt_write_word() functions.
98096  *
98097  * The struct declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND.
98098  */
98099 struct ALT_EMAC_DMA_TX_POLL_DEMAND_s
98100 {
98101  uint32_t tpd : 32; /* Transmit Poll Demand */
98102 };
98103 
98104 /* The typedef declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND. */
98105 typedef volatile struct ALT_EMAC_DMA_TX_POLL_DEMAND_s ALT_EMAC_DMA_TX_POLL_DEMAND_t;
98106 #endif /* __ASSEMBLY__ */
98107 
98108 /* The byte offset of the ALT_EMAC_DMA_TX_POLL_DEMAND register from the beginning of the component. */
98109 #define ALT_EMAC_DMA_TX_POLL_DEMAND_OFST 0x4
98110 /* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register. */
98111 #define ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_POLL_DEMAND_OFST))
98112 
98113 /*
98114  * Register : Register 2 (Receive Poll Demand Register) - Receive_Poll_Demand
98115  *
98116  * The Receive Poll Demand register enables the receive DMA to check for new
98117  * descriptors. This command is used to wake up the Rx DMA from the SUSPEND state.
98118  * The RxDMA can go into the SUSPEND state only because of the unavailability of
98119  * descriptors it owns.
98120  *
98121  * Register Layout
98122  *
98123  * Bits | Access | Reset | Description
98124  * :-------|:-------|:------|:--------------------
98125  * [31:0] | RW | 0x0 | Receive Poll Demand
98126  *
98127  */
98128 /*
98129  * Field : Receive Poll Demand - rpd
98130  *
98131  * When these bits are written with any value, the DMA reads the current descriptor
98132  * pointed to by Register 19 (Current Host Receive Descriptor Register). If that
98133  * descriptor is not available (owned by the Host), the reception returns to the
98134  * Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not
98135  * asserted. If the descriptor is available, the Rx DMA returns to the active
98136  * state.
98137  *
98138  * Field Access Macros:
98139  *
98140  */
98141 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
98142 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_LSB 0
98143 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
98144 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_MSB 31
98145 /* The width in bits of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
98146 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_WIDTH 32
98147 /* The mask used to set the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
98148 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET_MSK 0xffffffff
98149 /* The mask used to clear the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
98150 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_CLR_MSK 0x00000000
98151 /* The reset value of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
98152 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_RESET 0x0
98153 /* Extracts the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD field value from a register. */
98154 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0)
98155 /* Produces a ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value suitable for setting the register. */
98156 #define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff)
98157 
98158 #ifndef __ASSEMBLY__
98159 /*
98160  * WARNING: The C register and register group struct declarations are provided for
98161  * convenience and illustrative purposes. They should, however, be used with
98162  * caution as the C language standard provides no guarantees about the alignment or
98163  * atomicity of device memory accesses. The recommended practice for writing
98164  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98165  * alt_write_word() functions.
98166  *
98167  * The struct declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND.
98168  */
98169 struct ALT_EMAC_DMA_RX_POLL_DEMAND_s
98170 {
98171  uint32_t rpd : 32; /* Receive Poll Demand */
98172 };
98173 
98174 /* The typedef declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND. */
98175 typedef volatile struct ALT_EMAC_DMA_RX_POLL_DEMAND_s ALT_EMAC_DMA_RX_POLL_DEMAND_t;
98176 #endif /* __ASSEMBLY__ */
98177 
98178 /* The byte offset of the ALT_EMAC_DMA_RX_POLL_DEMAND register from the beginning of the component. */
98179 #define ALT_EMAC_DMA_RX_POLL_DEMAND_OFST 0x8
98180 /* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register. */
98181 #define ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_POLL_DEMAND_OFST))
98182 
98183 /*
98184  * Register : Register 3 (Receive Descriptor List Address Register) - Receive_Descriptor_List_Address
98185  *
98186  * The Receive Descriptor List Address register points to the start of the Receive
98187  * Descriptor List. The descriptor lists reside in the host's physical memory space
98188  * and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data
98189  * bus). The DMA internally converts it to bus width aligned address by making the
98190  * corresponding LS bits low. Writing to this register is permitted only when
98191  * reception is stopped. When stopped, this register must be written to before the
98192  * receive Start command is given.
98193  *
98194  * You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR)
98195  * is set to zero in Register 6 (Operation Mode Register). When stopped, this
98196  * register can be written with a new descriptor list address. When you set the SR
98197  * bit to 1, the DMA takes the newly programmed descriptor base address.
98198  *
98199  * If this register is not changed when the SR bit is set to 0, then the DMA takes
98200  * the descriptor address where it was stopped earlier.
98201  *
98202  * Register Layout
98203  *
98204  * Bits | Access | Reset | Description
98205  * :-------|:-------|:------|:----------------------
98206  * [1:0] | ??? | 0x0 | *UNDEFINED*
98207  * [31:2] | RW | 0x0 | Start of Receive List
98208  *
98209  */
98210 /*
98211  * Field : Start of Receive List - rdesla_32bit
98212  *
98213  * This field contains the base address of the first descriptor in the Receive
98214  * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally
98215  * taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO).
98216  *
98217  * Field Access Macros:
98218  *
98219  */
98220 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
98221 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_LSB 2
98222 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
98223 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_MSB 31
98224 /* The width in bits of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
98225 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_WIDTH 30
98226 /* The mask used to set the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
98227 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET_MSK 0xfffffffc
98228 /* The mask used to clear the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
98229 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_CLR_MSK 0x00000003
98230 /* The reset value of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
98231 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_RESET 0x0
98232 /* Extracts the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT field value from a register. */
98233 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
98234 /* Produces a ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value suitable for setting the register. */
98235 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
98236 
98237 #ifndef __ASSEMBLY__
98238 /*
98239  * WARNING: The C register and register group struct declarations are provided for
98240  * convenience and illustrative purposes. They should, however, be used with
98241  * caution as the C language standard provides no guarantees about the alignment or
98242  * atomicity of device memory accesses. The recommended practice for writing
98243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98244  * alt_write_word() functions.
98245  *
98246  * The struct declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR.
98247  */
98248 struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s
98249 {
98250  uint32_t : 2; /* *UNDEFINED* */
98251  uint32_t rdesla_32bit : 30; /* Start of Receive List */
98252 };
98253 
98254 /* The typedef declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR. */
98255 typedef volatile struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t;
98256 #endif /* __ASSEMBLY__ */
98257 
98258 /* The byte offset of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register from the beginning of the component. */
98259 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST 0xc
98260 /* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register. */
98261 #define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST))
98262 
98263 /*
98264  * Register : Register 4 (Transmit Descriptor List Address Register) - Transmit_Descriptor_List_Address
98265  *
98266  * The Transmit Descriptor List Address register points to the start of the
98267  * Transmit Descriptor List. The descriptor lists reside in the host's physical
98268  * memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or
98269  * 128-bit data bus). The DMA internally converts it to bus width aligned address
98270  * by making the corresponding LSB to low.
98271  *
98272  * You can write to this register only when the Tx DMA has stopped, that is, Bit 13
98273  * (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this
98274  * register can be written with a new descriptor list address. When you set the ST
98275  * bit to 1, the DMA takes the newly programmed descriptor base address.
98276  *
98277  * If this register is not changed when the ST bit is set to 0, then the DMA takes
98278  * the descriptor address where it was stopped earlier.
98279  *
98280  * Register Layout
98281  *
98282  * Bits | Access | Reset | Description
98283  * :-------|:-------|:------|:-----------------------
98284  * [1:0] | ??? | 0x0 | *UNDEFINED*
98285  * [31:2] | RW | 0x0 | Start of Transmit List
98286  *
98287  */
98288 /*
98289  * Field : Start of Transmit List - tdesla_32bit
98290  *
98291  * This field contains the base address of the first descriptor in the Transmit
98292  * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are
98293  * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only
98294  * (RO).
98295  *
98296  * Field Access Macros:
98297  *
98298  */
98299 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
98300 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_LSB 2
98301 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
98302 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_MSB 31
98303 /* The width in bits of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
98304 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_WIDTH 30
98305 /* The mask used to set the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
98306 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET_MSK 0xfffffffc
98307 /* The mask used to clear the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
98308 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_CLR_MSK 0x00000003
98309 /* The reset value of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
98310 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_RESET 0x0
98311 /* Extracts the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT field value from a register. */
98312 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
98313 /* Produces a ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value suitable for setting the register. */
98314 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)
98315 
98316 #ifndef __ASSEMBLY__
98317 /*
98318  * WARNING: The C register and register group struct declarations are provided for
98319  * convenience and illustrative purposes. They should, however, be used with
98320  * caution as the C language standard provides no guarantees about the alignment or
98321  * atomicity of device memory accesses. The recommended practice for writing
98322  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
98323  * alt_write_word() functions.
98324  *
98325  * The struct declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR.
98326  */
98327 struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s
98328 {
98329  uint32_t : 2; /* *UNDEFINED* */
98330  uint32_t tdesla_32bit : 30; /* Start of Transmit List */
98331 };
98332 
98333 /* The typedef declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR. */
98334 typedef volatile struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t;
98335 #endif /* __ASSEMBLY__ */
98336 
98337 /* The byte offset of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register from the beginning of the component. */
98338 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST 0x10
98339 /* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register. */
98340 #define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST))
98341 
98342 /*
98343  * Register : Register 5 (Status Register) - Status
98344  *
98345  * The Status register contains all status bits that the DMA reports to the host.
98346  * The software driver reads this register during an interrupt service routine or
98347  * polling. Most of the fields in this register cause the host to be interrupted.
98348  * The bits of this register are not cleared when read. Writing 1'b1 to
98349  * (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has
98350  * no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit
98351  * in Register 7 (Interrupt Enable Register).
98352  *
98353  * Register Layout
98354  *
98355  * Bits | Access | Reset | Description
98356  * :--------|:-------|:------|:-----------------------------------
98357  * [0] | RW | 0x0 | Transmit Interrupt
98358  * [1] | RW | 0x0 | Transmit Process Stopped
98359  * [2] | RW | 0x0 | Transmit Buffer Unavailable
98360  * [3] | RW | 0x0 | Transmit Jabber Timeout
98361  * [4] | RW | 0x0 | Receive Overflow
98362  * [5] | RW | 0x0 | Transmit Underflow
98363  * [6] | RW | 0x0 | Receive Interrupt
98364  * [7] | RW | 0x0 | Receive Buffer Unavailable
98365  * [8] | RW | 0x0 | Receive Process Stopped
98366  * [9] | RW | 0x0 | Receive Watchdog Timeout
98367  * [10] | RW | 0x0 | Early Transmit Interrupt
98368  * [12:11] | ??? | 0x0 | *UNDEFINED*
98369  * [13] | RW | 0x0 | Fatal Bus Error Interrupt
98370  * [14] | RW | 0x0 | Early Receive Interrupt
98371  * [15] | RW | 0x0 | Abnormal Interrupt Summary
98372  * [16] | RW | 0x0 | Normal Interrupt Summary
98373  * [19:17] | R | 0x0 | Received Process State
98374  * [22:20] | R | 0x0 | Transmit Process State
98375  * [25:23] | R | 0x0 | Error Bits
98376  * [26] | R | 0x0 | GMAC Line Interface Interrupt
98377  * [27] | R | 0x0 | GMAC MMC Interrupt
98378  * [28] | ??? | 0x0 | *UNDEFINED*
98379  * [29] | R | 0x0 | Timestamp Trigger Interrupt
98380  * [30] | R | 0x0 | GMAC LPI Interrupt (for Channel 0)
98381  * [31] | ??? | 0x0 | *UNDEFINED*
98382  *
98383  */
98384 /*
98385  * Field : Transmit Interrupt - ti
98386  *
98387  * This bit indicates that the frame transmission is complete. When transmission is
98388  * complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in the first
98389  * descriptor, and the specific frame status information is updated in the
98390  * descriptor.
98391  *
98392  * Field Access Macros:
98393  *
98394  */
98395 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
98396 #define ALT_EMAC_DMA_STAT_TI_LSB 0
98397 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
98398 #define ALT_EMAC_DMA_STAT_TI_MSB 0
98399 /* The width in bits of the ALT_EMAC_DMA_STAT_TI register field. */
98400 #define ALT_EMAC_DMA_STAT_TI_WIDTH 1
98401 /* The mask used to set the ALT_EMAC_DMA_STAT_TI register field value. */
98402 #define ALT_EMAC_DMA_STAT_TI_SET_MSK 0x00000001
98403 /* The mask used to clear the ALT_EMAC_DMA_STAT_TI register field value. */
98404 #define ALT_EMAC_DMA_STAT_TI_CLR_MSK 0xfffffffe
98405 /* The reset value of the ALT_EMAC_DMA_STAT_TI register field. */
98406 #define ALT_EMAC_DMA_STAT_TI_RESET 0x0
98407 /* Extracts the ALT_EMAC_DMA_STAT_TI field value from a register. */
98408 #define ALT_EMAC_DMA_STAT_TI_GET(value) (((value) & 0x00000001) >> 0)
98409 /* Produces a ALT_EMAC_DMA_STAT_TI register field value suitable for setting the register. */
98410 #define ALT_EMAC_DMA_STAT_TI_SET(value) (((value) << 0) & 0x00000001)
98411 
98412 /*
98413  * Field : Transmit Process Stopped - tps
98414  *
98415  * This bit is set when the transmission is stopped.
98416  *
98417  * Field Access Macros:
98418  *
98419  */
98420 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
98421 #define ALT_EMAC_DMA_STAT_TPS_LSB 1
98422 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
98423 #define ALT_EMAC_DMA_STAT_TPS_MSB 1
98424 /* The width in bits of the ALT_EMAC_DMA_STAT_TPS register field. */
98425 #define ALT_EMAC_DMA_STAT_TPS_WIDTH 1
98426 /* The mask used to set the ALT_EMAC_DMA_STAT_TPS register field value. */
98427 #define ALT_EMAC_DMA_STAT_TPS_SET_MSK 0x00000002
98428 /* The mask used to clear the ALT_EMAC_DMA_STAT_TPS register field value. */
98429 #define ALT_EMAC_DMA_STAT_TPS_CLR_MSK 0xfffffffd
98430 /* The reset value of the ALT_EMAC_DMA_STAT_TPS register field. */
98431 #define ALT_EMAC_DMA_STAT_TPS_RESET 0x0
98432 /* Extracts the ALT_EMAC_DMA_STAT_TPS field value from a register. */
98433 #define ALT_EMAC_DMA_STAT_TPS_GET(value) (((value) & 0x00000002) >> 1)
98434 /* Produces a ALT_EMAC_DMA_STAT_TPS register field value suitable for setting the register. */
98435 #define ALT_EMAC_DMA_STAT_TPS_SET(value) (((value) << 1) & 0x00000002)
98436 
98437 /*
98438  * Field : Transmit Buffer Unavailable - tu
98439  *
98440  * This bit indicates that the host owns the Next Descriptor in the Transmit List
98441  * and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain
98442  * the Transmit Process state transitions.
98443  *
98444  * To resume processing Transmit descriptors, the host should change the ownership
98445  * of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
98446  * command.
98447  *
98448  * Field Access Macros:
98449  *
98450  */
98451 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
98452 #define ALT_EMAC_DMA_STAT_TU_LSB 2
98453 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
98454 #define ALT_EMAC_DMA_STAT_TU_MSB 2
98455 /* The width in bits of the ALT_EMAC_DMA_STAT_TU register field. */
98456 #define ALT_EMAC_DMA_STAT_TU_WIDTH 1
98457 /* The mask used to set the ALT_EMAC_DMA_STAT_TU register field value. */
98458 #define ALT_EMAC_DMA_STAT_TU_SET_MSK 0x00000004
98459 /* The mask used to clear the ALT_EMAC_DMA_STAT_TU register field value. */
98460 #define ALT_EMAC_DMA_STAT_TU_CLR_MSK 0xfffffffb
98461 /* The reset value of the ALT_EMAC_DMA_STAT_TU register field. */
98462 #define ALT_EMAC_DMA_STAT_TU_RESET 0x0
98463 /* Extracts the ALT_EMAC_DMA_STAT_TU field value from a register. */
98464 #define ALT_EMAC_DMA_STAT_TU_GET(value) (((value) & 0x00000004) >> 2)
98465 /* Produces a ALT_EMAC_DMA_STAT_TU register field value suitable for setting the register. */
98466 #define ALT_EMAC_DMA_STAT_TU_SET(value) (((value) << 2) & 0x00000004)
98467 
98468 /*
98469  * Field : Transmit Jabber Timeout - tjt
98470  *
98471  * This bit indicates that the Transmit Jabber Timer expired, which happens when
98472  * the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled).
98473  * When the Jabber Timeout occurs, the transmission process is aborted and placed
98474  * in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to
98475  * assert.
98476  *
98477  * Field Access Macros:
98478  *
98479  */
98480 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
98481 #define ALT_EMAC_DMA_STAT_TJT_LSB 3
98482 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
98483 #define ALT_EMAC_DMA_STAT_TJT_MSB 3
98484 /* The width in bits of the ALT_EMAC_DMA_STAT_TJT register field. */
98485 #define ALT_EMAC_DMA_STAT_TJT_WIDTH 1
98486 /* The mask used to set the ALT_EMAC_DMA_STAT_TJT register field value. */
98487 #define ALT_EMAC_DMA_STAT_TJT_SET_MSK 0x00000008
98488 /* The mask used to clear the ALT_EMAC_DMA_STAT_TJT register field value. */
98489 #define ALT_EMAC_DMA_STAT_TJT_CLR_MSK 0xfffffff7
98490 /* The reset value of the ALT_EMAC_DMA_STAT_TJT register field. */
98491 #define ALT_EMAC_DMA_STAT_TJT_RESET 0x0
98492 /* Extracts the ALT_EMAC_DMA_STAT_TJT field value from a register. */
98493 #define ALT_EMAC_DMA_STAT_TJT_GET(value) (((value) & 0x00000008) >> 3)
98494 /* Produces a ALT_EMAC_DMA_STAT_TJT register field value suitable for setting the register. */
98495 #define ALT_EMAC_DMA_STAT_TJT_SET(value) (((value) << 3) & 0x00000008)
98496 
98497 /*
98498  * Field : Receive Overflow - ovf
98499  *
98500  * This bit indicates that the Receive Buffer had an Overflow during frame
98501  * reception. If the partial frame is transferred to the application, the overflow
98502  * status is set in RDES0[11].
98503  *
98504  * Field Access Macros:
98505  *
98506  */
98507 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
98508 #define ALT_EMAC_DMA_STAT_OVF_LSB 4
98509 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
98510 #define ALT_EMAC_DMA_STAT_OVF_MSB 4
98511 /* The width in bits of the ALT_EMAC_DMA_STAT_OVF register field. */
98512 #define ALT_EMAC_DMA_STAT_OVF_WIDTH 1
98513 /* The mask used to set the ALT_EMAC_DMA_STAT_OVF register field value. */
98514 #define ALT_EMAC_DMA_STAT_OVF_SET_MSK 0x00000010
98515 /* The mask used to clear the ALT_EMAC_DMA_STAT_OVF register field value. */
98516 #define ALT_EMAC_DMA_STAT_OVF_CLR_MSK 0xffffffef
98517 /* The reset value of the ALT_EMAC_DMA_STAT_OVF register field. */
98518 #define ALT_EMAC_DMA_STAT_OVF_RESET 0x0
98519 /* Extracts the ALT_EMAC_DMA_STAT_OVF field value from a register. */
98520 #define ALT_EMAC_DMA_STAT_OVF_GET(value) (((value) & 0x00000010) >> 4)
98521 /* Produces a ALT_EMAC_DMA_STAT_OVF register field value suitable for setting the register. */
98522 #define ALT_EMAC_DMA_STAT_OVF_SET(value) (((value) << 4) & 0x00000010)
98523 
98524 /*
98525  * Field : Transmit Underflow - unf
98526  *
98527  * This bit indicates that the Transmit Buffer had an Underflow during frame
98528  * transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.
98529  *
98530  * Field Access Macros:
98531  *
98532  */
98533 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
98534 #define ALT_EMAC_DMA_STAT_UNF_LSB 5
98535 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
98536 #define ALT_EMAC_DMA_STAT_UNF_MSB 5
98537 /* The width in bits of the ALT_EMAC_DMA_STAT_UNF register field. */
98538 #define ALT_EMAC_DMA_STAT_UNF_WIDTH 1
98539 /* The mask used to set the ALT_EMAC_DMA_STAT_UNF register field value. */
98540 #define ALT_EMAC_DMA_STAT_UNF_SET_MSK 0x00000020
98541 /* The mask used to clear the ALT_EMAC_DMA_STAT_UNF register field value. */
98542 #define ALT_EMAC_DMA_STAT_UNF_CLR_MSK 0xffffffdf
98543 /* The reset value of the ALT_EMAC_DMA_STAT_UNF register field. */
98544 #define ALT_EMAC_DMA_STAT_UNF_RESET 0x0
98545 /* Extracts the ALT_EMAC_DMA_STAT_UNF field value from a register. */
98546 #define ALT_EMAC_DMA_STAT_UNF_GET(value) (((value) & 0x00000020) >> 5)
98547 /* Produces a ALT_EMAC_DMA_STAT_UNF register field value suitable for setting the register. */
98548 #define ALT_EMAC_DMA_STAT_UNF_SET(value) (((value) << 5) & 0x00000020)
98549 
98550 /*
98551  * Field : Receive Interrupt - ri
98552  *
98553  * This bit indicates that the frame reception is complete. When reception is
98554  * complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the
98555  * last Descriptor, and the specific frame status information is updated in the
98556  * descriptor.
98557  *
98558  * The reception remains in the Running state.
98559  *
98560  * Field Access Macros:
98561  *
98562  */
98563 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
98564 #define ALT_EMAC_DMA_STAT_RI_LSB 6
98565 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
98566 #define ALT_EMAC_DMA_STAT_RI_MSB 6
98567 /* The width in bits of the ALT_EMAC_DMA_STAT_RI register field. */
98568 #define ALT_EMAC_DMA_STAT_RI_WIDTH 1
98569 /* The mask used to set the ALT_EMAC_DMA_STAT_RI register field value. */
98570 #define ALT_EMAC_DMA_STAT_RI_SET_MSK 0x00000040
98571 /* The mask used to clear the ALT_EMAC_DMA_STAT_RI register field value. */
98572 #define ALT_EMAC_DMA_STAT_RI_CLR_MSK 0xffffffbf
98573 /* The reset value of the ALT_EMAC_DMA_STAT_RI register field. */
98574 #define ALT_EMAC_DMA_STAT_RI_RESET 0x0
98575 /* Extracts the ALT_EMAC_DMA_STAT_RI field value from a register. */
98576 #define ALT_EMAC_DMA_STAT_RI_GET(value) (((value) & 0x00000040) >> 6)
98577 /* Produces a ALT_EMAC_DMA_STAT_RI register field value suitable for setting the register. */
98578 #define ALT_EMAC_DMA_STAT_RI_SET(value) (((value) << 6) & 0x00000040)
98579 
98580 /*
98581  * Field : Receive Buffer Unavailable - ru
98582  *
98583  * This bit indicates that the host owns the Next Descriptor in the Receive List
98584  * and the DMA cannot acquire it. The Receive Process is suspended. To resume
98585  * processing Receive descriptors, the host should change the ownership of the
98586  * descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
98587  * issued, the Receive Process resumes when the next recognized incoming frame is
98588  * received. This bit is set only when the previous Receive Descriptor is owned by
98589  * the DMA.
98590  *
98591  * Field Access Macros:
98592  *
98593  */
98594 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
98595 #define ALT_EMAC_DMA_STAT_RU_LSB 7
98596 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
98597 #define ALT_EMAC_DMA_STAT_RU_MSB 7
98598 /* The width in bits of the ALT_EMAC_DMA_STAT_RU register field. */
98599 #define ALT_EMAC_DMA_STAT_RU_WIDTH 1
98600 /* The mask used to set the ALT_EMAC_DMA_STAT_RU register field value. */
98601 #define ALT_EMAC_DMA_STAT_RU_SET_MSK 0x00000080
98602 /* The mask used to clear the ALT_EMAC_DMA_STAT_RU register field value. */
98603 #define ALT_EMAC_DMA_STAT_RU_CLR_MSK 0xffffff7f
98604 /* The reset value of the ALT_EMAC_DMA_STAT_RU register field. */
98605 #define ALT_EMAC_DMA_STAT_RU_RESET 0x0
98606 /* Extracts the ALT_EMAC_DMA_STAT_RU field value from a register. */
98607 #define ALT_EMAC_DMA_STAT_RU_GET(value) (((value) & 0x00000080) >> 7)
98608 /* Produces a ALT_EMAC_DMA_STAT_RU register field value suitable for setting the register. */
98609 #define ALT_EMAC_DMA_STAT_RU_SET(value) (((value) << 7) & 0x00000080)
98610 
98611 /*
98612  * Field : Receive Process Stopped - rps
98613  *
98614  * This bit is asserted when the Receive Process enters the Stopped state.
98615  *
98616  * Field Access Macros:
98617  *
98618  */
98619 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
98620 #define ALT_EMAC_DMA_STAT_RPS_LSB 8
98621 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
98622 #define ALT_EMAC_DMA_STAT_RPS_MSB 8
98623 /* The width in bits of the ALT_EMAC_DMA_STAT_RPS register field. */
98624 #define ALT_EMAC_DMA_STAT_RPS_WIDTH 1
98625 /* The mask used to set the ALT_EMAC_DMA_STAT_RPS register field value. */
98626 #define ALT_EMAC_DMA_STAT_RPS_SET_MSK 0x00000100
98627 /* The mask used to clear the ALT_EMAC_DMA_STAT_RPS register field value. */
98628 #define ALT_EMAC_DMA_STAT_RPS_CLR_MSK 0xfffffeff
98629 /* The reset value of the ALT_EMAC_DMA_STAT_RPS register field. */
98630 #define ALT_EMAC_DMA_STAT_RPS_RESET 0x0
98631 /* Extracts the ALT_EMAC_DMA_STAT_RPS field value from a register. */
98632 #define ALT_EMAC_DMA_STAT_RPS_GET(value) (((value) & 0x00000100) >> 8)
98633 /* Produces a ALT_EMAC_DMA_STAT_RPS register field value suitable for setting the register. */
98634 #define ALT_EMAC_DMA_STAT_RPS_SET(value) (((value) << 8) & 0x00000100)
98635 
98636 /*
98637  * Field : Receive Watchdog Timeout - rwt
98638  *
98639  * This bit is asserted when a frame with length greater than 2,048 bytes is
98640  * received (10, 240 when Jumbo Frame mode is enabled).
98641  *
98642  * Field Access Macros:
98643  *
98644  */
98645 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
98646 #define ALT_EMAC_DMA_STAT_RWT_LSB 9
98647 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
98648 #define ALT_EMAC_DMA_STAT_RWT_MSB 9
98649 /* The width in bits of the ALT_EMAC_DMA_STAT_RWT register field. */
98650 #define ALT_EMAC_DMA_STAT_RWT_WIDTH 1
98651 /* The mask used to set the ALT_EMAC_DMA_STAT_RWT register field value. */
98652 #define ALT_EMAC_DMA_STAT_RWT_SET_MSK 0x00000200
98653 /* The mask used to clear the ALT_EMAC_DMA_STAT_RWT register field value. */
98654 #define ALT_EMAC_DMA_STAT_RWT_CLR_MSK 0xfffffdff
98655 /* The reset value of the ALT_EMAC_DMA_STAT_RWT register field. */
98656 #define ALT_EMAC_DMA_STAT_RWT_RESET 0x0
98657 /* Extracts the ALT_EMAC_DMA_STAT_RWT field value from a register. */
98658 #define ALT_EMAC_DMA_STAT_RWT_GET(value) (((value) & 0x00000200) >> 9)
98659 /* Produces a ALT_EMAC_DMA_STAT_RWT register field value suitable for setting the register. */
98660 #define ALT_EMAC_DMA_STAT_RWT_SET(value) (((value) << 9) & 0x00000200)
98661 
98662 /*
98663  * Field : Early Transmit Interrupt - eti
98664  *
98665  * This bit indicates that the frame to be transmitted is fully transferred to the
98666  * MTL Transmit FIFO.
98667  *
98668  * Field Access Macros:
98669  *
98670  */
98671 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
98672 #define ALT_EMAC_DMA_STAT_ETI_LSB 10
98673 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
98674 #define ALT_EMAC_DMA_STAT_ETI_MSB 10
98675 /* The width in bits of the ALT_EMAC_DMA_STAT_ETI register field. */
98676 #define ALT_EMAC_DMA_STAT_ETI_WIDTH 1
98677 /* The mask used to set the ALT_EMAC_DMA_STAT_ETI register field value. */
98678 #define ALT_EMAC_DMA_STAT_ETI_SET_MSK 0x00000400
98679 /* The mask used to clear the ALT_EMAC_DMA_STAT_ETI register field value. */
98680 #define ALT_EMAC_DMA_STAT_ETI_CLR_MSK 0xfffffbff
98681 /* The reset value of the ALT_EMAC_DMA_STAT_ETI register field. */
98682 #define ALT_EMAC_DMA_STAT_ETI_RESET 0x0
98683 /* Extracts the ALT_EMAC_DMA_STAT_ETI field value from a register. */
98684 #define ALT_EMAC_DMA_STAT_ETI_GET(value) (((value) & 0x00000400) >> 10)
98685 /* Produces a ALT_EMAC_DMA_STAT_ETI register field value suitable for setting the register. */
98686 #define ALT_EMAC_DMA_STAT_ETI_SET(value) (((value) << 10) & 0x00000400)
98687 
98688 /*
98689  * Field : Fatal Bus Error Interrupt - fbi
98690  *
98691  * This bit indicates that a bus error occurred, as described in Bits[25:23]. When
98692  * this bit is set, the corresponding DMA engine disables all of its bus accesses.
98693  *
98694  * Field Access Macros:
98695  *
98696  */
98697 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
98698 #define ALT_EMAC_DMA_STAT_FBI_LSB 13
98699 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
98700 #define ALT_EMAC_DMA_STAT_FBI_MSB 13
98701 /* The width in bits of the ALT_EMAC_DMA_STAT_FBI register field. */
98702 #define ALT_EMAC_DMA_STAT_FBI_WIDTH 1
98703 /* The mask used to set the ALT_EMAC_DMA_STAT_FBI register field value. */
98704 #define ALT_EMAC_DMA_STAT_FBI_SET_MSK 0x00002000
98705 /* The mask used to clear the ALT_EMAC_DMA_STAT_FBI register field value. */
98706 #define ALT_EMAC_DMA_STAT_FBI_CLR_MSK 0xffffdfff
98707 /* The reset value of the ALT_EMAC_DMA_STAT_FBI register field. */
98708 #define ALT_EMAC_DMA_STAT_FBI_RESET 0x0
98709 /* Extracts the ALT_EMAC_DMA_STAT_FBI field value from a register. */
98710 #define ALT_EMAC_DMA_STAT_FBI_GET(value) (((value) & 0x00002000) >> 13)
98711 /* Produces a ALT_EMAC_DMA_STAT_FBI register field value suitable for setting the register. */
98712 #define ALT_EMAC_DMA_STAT_FBI_SET(value) (((value) << 13) & 0x00002000)
98713 
98714 /*
98715  * Field : Early Receive Interrupt - eri
98716  *
98717  * This bit indicates that the DMA had filled the first data buffer of the packet.
98718  * Bit 6 (RI) of this register automatically clears this bit.
98719  *
98720  * Field Access Macros:
98721  *
98722  */
98723 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
98724 #define ALT_EMAC_DMA_STAT_ERI_LSB 14
98725 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
98726 #define ALT_EMAC_DMA_STAT_ERI_MSB 14
98727 /* The width in bits of the ALT_EMAC_DMA_STAT_ERI register field. */
98728 #define ALT_EMAC_DMA_STAT_ERI_WIDTH 1
98729 /* The mask used to set the ALT_EMAC_DMA_STAT_ERI register field value. */
98730 #define ALT_EMAC_DMA_STAT_ERI_SET_MSK 0x00004000
98731 /* The mask used to clear the ALT_EMAC_DMA_STAT_ERI register field value. */
98732 #define ALT_EMAC_DMA_STAT_ERI_CLR_MSK 0xffffbfff
98733 /* The reset value of the ALT_EMAC_DMA_STAT_ERI register field. */
98734 #define ALT_EMAC_DMA_STAT_ERI_RESET 0x0
98735 /* Extracts the ALT_EMAC_DMA_STAT_ERI field value from a register. */
98736 #define ALT_EMAC_DMA_STAT_ERI_GET(value) (((value) & 0x00004000) >> 14)
98737 /* Produces a ALT_EMAC_DMA_STAT_ERI register field value suitable for setting the register. */
98738 #define ALT_EMAC_DMA_STAT_ERI_SET(value) (((value) << 14) & 0x00004000)
98739 
98740 /*
98741  * Field : Abnormal Interrupt Summary - ais
98742  *
98743  * Abnormal Interrupt Summary bit value is the logical OR of the following when the
98744  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
98745  * Register):
98746  *
98747  * * Register 5[1]: Transmit Process Stopped
98748  *
98749  * * Register 5[3]: Transmit Jabber Timeout
98750  *
98751  * * Register 5[4]: Receive FIFO Overflow
98752  *
98753  * * Register 5[5]: Transmit Underflow
98754  *
98755  * * Register 5[7]: Receive Buffer Unavailable
98756  *
98757  * * Register 5[8]: Receive Process Stopped
98758  *
98759  * * Register 5[9]: Receive Watchdog Timeout
98760  *
98761  * * Register 5[10]: Early Transmit Interrupt
98762  *
98763  * * Register 5[13]: Fatal Bus Error
98764  *
98765  * Only unmasked bits affect the Abnormal Interrupt Summary bit.
98766  *
98767  * This is a sticky bit and must be cleared each time a corresponding bit, which
98768  * causes AIS to be set, is cleared.
98769  *
98770  * Field Access Macros:
98771  *
98772  */
98773 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
98774 #define ALT_EMAC_DMA_STAT_AIS_LSB 15
98775 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
98776 #define ALT_EMAC_DMA_STAT_AIS_MSB 15
98777 /* The width in bits of the ALT_EMAC_DMA_STAT_AIS register field. */
98778 #define ALT_EMAC_DMA_STAT_AIS_WIDTH 1
98779 /* The mask used to set the ALT_EMAC_DMA_STAT_AIS register field value. */
98780 #define ALT_EMAC_DMA_STAT_AIS_SET_MSK 0x00008000
98781 /* The mask used to clear the ALT_EMAC_DMA_STAT_AIS register field value. */
98782 #define ALT_EMAC_DMA_STAT_AIS_CLR_MSK 0xffff7fff
98783 /* The reset value of the ALT_EMAC_DMA_STAT_AIS register field. */
98784 #define ALT_EMAC_DMA_STAT_AIS_RESET 0x0
98785 /* Extracts the ALT_EMAC_DMA_STAT_AIS field value from a register. */
98786 #define ALT_EMAC_DMA_STAT_AIS_GET(value) (((value) & 0x00008000) >> 15)
98787 /* Produces a ALT_EMAC_DMA_STAT_AIS register field value suitable for setting the register. */
98788 #define ALT_EMAC_DMA_STAT_AIS_SET(value) (((value) << 15) & 0x00008000)
98789 
98790 /*
98791  * Field : Normal Interrupt Summary - nis
98792  *
98793  * Normal Interrupt Summary bit value is the logical OR of the following when the
98794  * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
98795  * Register):
98796  *
98797  * * Register 5[0]: Transmit Interrupt
98798  *
98799  * * Register 5[2]: Transmit Buffer Unavailable
98800  *
98801  * * Register 5[6]: Receive Interrupt
98802  *
98803  * * Register 5[14]: Early Receive Interrupt
98804  *
98805  * Only unmasked bits (interrupts for which interrupt enable is set in Register 7)
98806  * affect the Normal Interrupt Summary bit.
98807  *
98808  * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a
98809  * corresponding bit, which causes NIS to be set, is cleared.
98810  *
98811  * Field Access Macros:
98812  *
98813  */
98814 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
98815 #define ALT_EMAC_DMA_STAT_NIS_LSB 16
98816 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
98817 #define ALT_EMAC_DMA_STAT_NIS_MSB 16
98818 /* The width in bits of the ALT_EMAC_DMA_STAT_NIS register field. */
98819 #define ALT_EMAC_DMA_STAT_NIS_WIDTH 1
98820 /* The mask used to set the ALT_EMAC_DMA_STAT_NIS register field value. */
98821 #define ALT_EMAC_DMA_STAT_NIS_SET_MSK 0x00010000
98822 /* The mask used to clear the ALT_EMAC_DMA_STAT_NIS register field value. */
98823 #define ALT_EMAC_DMA_STAT_NIS_CLR_MSK 0xfffeffff
98824 /* The reset value of the ALT_EMAC_DMA_STAT_NIS register field. */
98825 #define ALT_EMAC_DMA_STAT_NIS_RESET 0x0
98826 /* Extracts the ALT_EMAC_DMA_STAT_NIS field value from a register. */
98827 #define ALT_EMAC_DMA_STAT_NIS_GET(value) (((value) & 0x00010000) >> 16)
98828 /* Produces a ALT_EMAC_DMA_STAT_NIS register field value suitable for setting the register. */
98829 #define ALT_EMAC_DMA_STAT_NIS_SET(value) (((value) << 16) & 0x00010000)
98830 
98831 /*
98832  * Field : Received Process State - rs
98833  *
98834  * This field indicates the Receive DMA FSM state. This field does not generate an
98835  * interrupt.
98836  *
98837  * Field Enumeration Values:
98838  *
98839  * Enum | Value | Description
98840  * :--------------------------------|:------|:-------------------------------------------------
98841  * ALT_EMAC_DMA_STAT_RS_E_STOPPED | 0x0 | Stopped Reset or Stop Receive Command issued
98842  * ALT_EMAC_DMA_STAT_RS_E_RUNFETCH | 0x1 | Running: Fetching Receive Transfer Descriptor
98843  * ALT_EMAC_DMA_STAT_RS_E_RESERVE | 0x2 | Reserved for future use
98844  * ALT_EMAC_DMA_STAT_RS_E_RUNWAIT | 0x3 | Running: Waiting for receive packet
98845  * ALT_EMAC_DMA_STAT_RS_E_SUSPEND | 0x4 | Suspended: Receive Descriptor Unavailable
98846  * ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE | 0x5 | Running: Closing Receive Descriptor
98847  * ALT_EMAC_DMA_STAT_RS_E_TIMESTMP | 0x6 | TIME_STAMP write state
98848  * ALT_EMAC_DMA_STAT_RS_E_RUNTRANS | 0x7 | Transferring rcv packet data from receive buffer
98849  * : | | to host memory
98850  *
98851  * Field Access Macros:
98852  *
98853  */
98854 /*
98855  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98856  *
98857  * Stopped Reset or Stop Receive Command issued
98858  */
98859 #define ALT_EMAC_DMA_STAT_RS_E_STOPPED 0x0
98860 /*
98861  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98862  *
98863  * Running: Fetching Receive Transfer Descriptor
98864  */
98865 #define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH 0x1
98866 /*
98867  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98868  *
98869  * Reserved for future use
98870  */
98871 #define ALT_EMAC_DMA_STAT_RS_E_RESERVE 0x2
98872 /*
98873  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98874  *
98875  * Running: Waiting for receive packet
98876  */
98877 #define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT 0x3
98878 /*
98879  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98880  *
98881  * Suspended: Receive Descriptor Unavailable
98882  */
98883 #define ALT_EMAC_DMA_STAT_RS_E_SUSPEND 0x4
98884 /*
98885  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98886  *
98887  * Running: Closing Receive Descriptor
98888  */
98889 #define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE 0x5
98890 /*
98891  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98892  *
98893  * TIME_STAMP write state
98894  */
98895 #define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP 0x6
98896 /*
98897  * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
98898  *
98899  * Transferring rcv packet data from receive buffer to host memory
98900  */
98901 #define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS 0x7
98902 
98903 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
98904 #define ALT_EMAC_DMA_STAT_RS_LSB 17
98905 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
98906 #define ALT_EMAC_DMA_STAT_RS_MSB 19
98907 /* The width in bits of the ALT_EMAC_DMA_STAT_RS register field. */
98908 #define ALT_EMAC_DMA_STAT_RS_WIDTH 3
98909 /* The mask used to set the ALT_EMAC_DMA_STAT_RS register field value. */
98910 #define ALT_EMAC_DMA_STAT_RS_SET_MSK 0x000e0000
98911 /* The mask used to clear the ALT_EMAC_DMA_STAT_RS register field value. */
98912 #define ALT_EMAC_DMA_STAT_RS_CLR_MSK 0xfff1ffff
98913 /* The reset value of the ALT_EMAC_DMA_STAT_RS register field. */
98914 #define ALT_EMAC_DMA_STAT_RS_RESET 0x0
98915 /* Extracts the ALT_EMAC_DMA_STAT_RS field value from a register. */
98916 #define ALT_EMAC_DMA_STAT_RS_GET(value) (((value) & 0x000e0000) >> 17)
98917 /* Produces a ALT_EMAC_DMA_STAT_RS register field value suitable for setting the register. */
98918 #define ALT_EMAC_DMA_STAT_RS_SET(value) (((value) << 17) & 0x000e0000)
98919 
98920 /*
98921  * Field : Transmit Process State - ts
98922  *
98923  * This field indicates the Transmit DMA FSM state. This field does not generate an
98924  * interrupt.
98925  *
98926  * Field Enumeration Values:
98927  *
98928  * Enum | Value | Description
98929  * :--------------------------------|:------|:----------------------------------------------
98930  * ALT_EMAC_DMA_STAT_TS_E_STOPPED | 0x0 | Stopped Reset or Stop Transmit Command
98931  * ALT_EMAC_DMA_STAT_TS_E_RUNFETCH | 0x1 | Running: Fetching Tranmit Transfer Descriptor
98932  * ALT_EMAC_DMA_STAT_TS_E_RUNWAIT | 0x2 | Running; Waiting for status
98933  * ALT_EMAC_DMA_STAT_TS_E_RUNRD | 0x3 | Running; Reading Data host memory buffer and
98934  * : | | queuing it to transmit buffer (Tx FIFO)
98935  * ALT_EMAC_DMA_STAT_TS_E_TIMESTMP | 0x4 | TIME_STAMP write state
98936  * ALT_EMAC_DMA_STAT_TS_E_RESERVE | 0x5 | Reserved for future use
98937  * ALT_EMAC_DMA_STAT_TS_E_SUSPTX | 0x6 | Suspended; Transmit Descriptor Unavailable or
98938  * : | | Transmit Buffer Underflow
98939  * ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE | 0x7 | Running; Closing Transmit Descriptor
98940  *
98941  * Field Access Macros:
98942  *
98943  */
98944 /*
98945  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98946  *
98947  * Stopped Reset or Stop Transmit Command
98948  */
98949 #define ALT_EMAC_DMA_STAT_TS_E_STOPPED 0x0
98950 /*
98951  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98952  *
98953  * Running: Fetching Tranmit Transfer Descriptor
98954  */
98955 #define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH 0x1
98956 /*
98957  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98958  *
98959  * Running; Waiting for status
98960  */
98961 #define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT 0x2
98962 /*
98963  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98964  *
98965  * Running; Reading Data host memory buffer and queuing it to transmit buffer (Tx
98966  * FIFO)
98967  */
98968 #define ALT_EMAC_DMA_STAT_TS_E_RUNRD 0x3
98969 /*
98970  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98971  *
98972  * TIME_STAMP write state
98973  */
98974 #define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP 0x4
98975 /*
98976  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98977  *
98978  * Reserved for future use
98979  */
98980 #define ALT_EMAC_DMA_STAT_TS_E_RESERVE 0x5
98981 /*
98982  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98983  *
98984  * Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow
98985  */
98986 #define ALT_EMAC_DMA_STAT_TS_E_SUSPTX 0x6
98987 /*
98988  * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
98989  *
98990  * Running; Closing Transmit Descriptor
98991  */
98992 #define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE 0x7
98993 
98994 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
98995 #define ALT_EMAC_DMA_STAT_TS_LSB 20
98996 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
98997 #define ALT_EMAC_DMA_STAT_TS_MSB 22
98998 /* The width in bits of the ALT_EMAC_DMA_STAT_TS register field. */
98999 #define ALT_EMAC_DMA_STAT_TS_WIDTH 3
99000 /* The mask used to set the ALT_EMAC_DMA_STAT_TS register field value. */
99001 #define ALT_EMAC_DMA_STAT_TS_SET_MSK 0x00700000
99002 /* The mask used to clear the ALT_EMAC_DMA_STAT_TS register field value. */
99003 #define ALT_EMAC_DMA_STAT_TS_CLR_MSK 0xff8fffff
99004 /* The reset value of the ALT_EMAC_DMA_STAT_TS register field. */
99005 #define ALT_EMAC_DMA_STAT_TS_RESET 0x0
99006 /* Extracts the ALT_EMAC_DMA_STAT_TS field value from a register. */
99007 #define ALT_EMAC_DMA_STAT_TS_GET(value) (((value) & 0x00700000) >> 20)
99008 /* Produces a ALT_EMAC_DMA_STAT_TS register field value suitable for setting the register. */
99009 #define ALT_EMAC_DMA_STAT_TS_SET(value) (((value) << 20) & 0x00700000)
99010 
99011 /*
99012  * Field : Error Bits - eb
99013  *
99014  * This field indicates the type of error that caused a Bus Error, for example,
99015  * error response on the AHB or AXI interface. This field is valid only when Bit 13
99016  * (FBI) is set. This field does not generate an interrupt.
99017  *
99018  * * Bit 23
99019  *
99020  * - 1'b1: Error during data transfer by the Tx DMA
99021  *
99022  * - 1'b0: Error during data transfer by the Rx DMA
99023  *
99024  * * Bit 24
99025  *
99026  * - 1'b1: Error during read transfer
99027  *
99028  * - 1'b0: Error during write transfer
99029  *
99030  * * Bit 25
99031  *
99032  * - 1'b1: Error during descriptor access
99033  *
99034  * - 1'b0: Error during data buffer access
99035  *
99036  * Field Access Macros:
99037  *
99038  */
99039 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
99040 #define ALT_EMAC_DMA_STAT_EB_LSB 23
99041 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
99042 #define ALT_EMAC_DMA_STAT_EB_MSB 25
99043 /* The width in bits of the ALT_EMAC_DMA_STAT_EB register field. */
99044 #define ALT_EMAC_DMA_STAT_EB_WIDTH 3
99045 /* The mask used to set the ALT_EMAC_DMA_STAT_EB register field value. */
99046 #define ALT_EMAC_DMA_STAT_EB_SET_MSK 0x03800000
99047 /* The mask used to clear the ALT_EMAC_DMA_STAT_EB register field value. */
99048 #define ALT_EMAC_DMA_STAT_EB_CLR_MSK 0xfc7fffff
99049 /* The reset value of the ALT_EMAC_DMA_STAT_EB register field. */
99050 #define ALT_EMAC_DMA_STAT_EB_RESET 0x0
99051 /* Extracts the ALT_EMAC_DMA_STAT_EB field value from a register. */
99052 #define ALT_EMAC_DMA_STAT_EB_GET(value) (((value) & 0x03800000) >> 23)
99053 /* Produces a ALT_EMAC_DMA_STAT_EB register field value suitable for setting the register. */
99054 #define ALT_EMAC_DMA_STAT_EB_SET(value) (((value) << 23) & 0x03800000)
99055 
99056 /*
99057  * Field : GMAC Line Interface Interrupt - gli
99058  *
99059  * This bit reflects an interrupt event in the PCS (link change and AN complete),
99060  * SMII (link change), or RGMII (link change) interface block of the EMAC. The
99061  * software must read the corresponding registers (Register 49 for PCS or Register
99062  * 54 for SMII or RGMII) in the EMAC to get the exact cause of the interrupt and
99063  * clear the source of interrupt to make this bit as 1'b0. The interrupt signal
99064  * from the EMAC subsystem (sbd_intr_o) is high when this bit is high.
99065  *
99066  * Field Enumeration Values:
99067  *
99068  * Enum | Value | Description
99069  * :-----------------------------------|:------|:--------------------
99070  * ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP | 0x0 | No Interrupt
99071  * ALT_EMAC_DMA_STAT_GLI_E_INTERRUP | 0x1 | GMAC Line Interrupt
99072  *
99073  * Field Access Macros:
99074  *
99075  */
99076 /*
99077  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
99078  *
99079  * No Interrupt
99080  */
99081 #define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP 0x0
99082 /*
99083  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
99084  *
99085  * GMAC Line Interrupt
99086  */
99087 #define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP 0x1
99088 
99089 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
99090 #define ALT_EMAC_DMA_STAT_GLI_LSB 26
99091 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
99092 #define ALT_EMAC_DMA_STAT_GLI_MSB 26
99093 /* The width in bits of the ALT_EMAC_DMA_STAT_GLI register field. */
99094 #define ALT_EMAC_DMA_STAT_GLI_WIDTH 1
99095 /* The mask used to set the ALT_EMAC_DMA_STAT_GLI register field value. */
99096 #define ALT_EMAC_DMA_STAT_GLI_SET_MSK 0x04000000
99097 /* The mask used to clear the ALT_EMAC_DMA_STAT_GLI register field value. */
99098 #define ALT_EMAC_DMA_STAT_GLI_CLR_MSK 0xfbffffff
99099 /* The reset value of the ALT_EMAC_DMA_STAT_GLI register field. */
99100 #define ALT_EMAC_DMA_STAT_GLI_RESET 0x0
99101 /* Extracts the ALT_EMAC_DMA_STAT_GLI field value from a register. */
99102 #define ALT_EMAC_DMA_STAT_GLI_GET(value) (((value) & 0x04000000) >> 26)
99103 /* Produces a ALT_EMAC_DMA_STAT_GLI register field value suitable for setting the register. */
99104 #define ALT_EMAC_DMA_STAT_GLI_SET(value) (((value) << 26) & 0x04000000)
99105 
99106 /*
99107  * Field : GMAC MMC Interrupt - gmi
99108  *
99109  * This bit reflects an interrupt event in the MMC block of the EMAC. The software
99110  * must read the corresponding registers in the EMAC to get the exact cause of
99111  * interrupt and clear the source of interrupt to make this bit as 1'b0. The
99112  * interrupt signal from the EMAC subsystem (sbd_intr_o) is high when this bit is
99113  * high.
99114  *
99115  * Field Enumeration Values:
99116  *
99117  * Enum | Value | Description
99118  * :-----------------------------------|:------|:-------------------
99119  * ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP | 0x0 | No Interrupt
99120  * ALT_EMAC_DMA_STAT_GMI_E_INTERRUP | 0x1 | GMAC MMC Interrupt
99121  *
99122  * Field Access Macros:
99123  *
99124  */
99125 /*
99126  * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
99127  *
99128  * No Interrupt
99129  */
99130 #define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP 0x0
99131 /*
99132  * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
99133  *
99134  * GMAC MMC Interrupt
99135  */
99136 #define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP 0x1
99137 
99138 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
99139 #define ALT_EMAC_DMA_STAT_GMI_LSB 27
99140 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
99141 #define ALT_EMAC_DMA_STAT_GMI_MSB 27
99142 /* The width in bits of the ALT_EMAC_DMA_STAT_GMI register field. */
99143 #define ALT_EMAC_DMA_STAT_GMI_WIDTH 1
99144 /* The mask used to set the ALT_EMAC_DMA_STAT_GMI register field value. */
99145 #define ALT_EMAC_DMA_STAT_GMI_SET_MSK 0x08000000
99146 /* The mask used to clear the ALT_EMAC_DMA_STAT_GMI register field value. */
99147 #define ALT_EMAC_DMA_STAT_GMI_CLR_MSK 0xf7ffffff
99148 /* The reset value of the ALT_EMAC_DMA_STAT_GMI register field. */
99149 #define ALT_EMAC_DMA_STAT_GMI_RESET 0x0
99150 /* Extracts the ALT_EMAC_DMA_STAT_GMI field value from a register. */
99151 #define ALT_EMAC_DMA_STAT_GMI_GET(value) (((value) & 0x08000000) >> 27)
99152 /* Produces a ALT_EMAC_DMA_STAT_GMI register field value suitable for setting the register. */
99153 #define ALT_EMAC_DMA_STAT_GMI_SET(value) (((value) << 27) & 0x08000000)
99154 
99155 /*
99156  * Field : Timestamp Trigger Interrupt - tti
99157  *
99158  * This bit indicates an interrupt event in the Timestamp Generator block of EMAC.
99159  * The software must read the corresponding registers in the EMAC to get the exact
99160  * cause of interrupt and clear its source to reset this bit to 1'b0. When this bit
99161  * is high, the interrupt signal from the EMAC subsystem (sbd_intr_o) is high.
99162  *
99163  * Field Enumeration Values:
99164  *
99165  * Enum | Value | Description
99166  * :-----------------------------------|:------|:----------------------------
99167  * ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP | 0x0 | No Interrupt
99168  * ALT_EMAC_DMA_STAT_TTI_E_INTERRUP | 0x1 | Timestamp Trigger Interrupt
99169  *
99170  * Field Access Macros:
99171  *
99172  */
99173 /*
99174  * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
99175  *
99176  * No Interrupt
99177  */
99178 #define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP 0x0
99179 /*
99180  * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
99181  *
99182  * Timestamp Trigger Interrupt
99183  */
99184 #define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP 0x1
99185 
99186 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
99187 #define ALT_EMAC_DMA_STAT_TTI_LSB 29
99188 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
99189 #define ALT_EMAC_DMA_STAT_TTI_MSB 29
99190 /* The width in bits of the ALT_EMAC_DMA_STAT_TTI register field. */
99191 #define ALT_EMAC_DMA_STAT_TTI_WIDTH 1
99192 /* The mask used to set the ALT_EMAC_DMA_STAT_TTI register field value. */
99193 #define ALT_EMAC_DMA_STAT_TTI_SET_MSK 0x20000000
99194 /* The mask used to clear the ALT_EMAC_DMA_STAT_TTI register field value. */
99195 #define ALT_EMAC_DMA_STAT_TTI_CLR_MSK 0xdfffffff
99196 /* The reset value of the ALT_EMAC_DMA_STAT_TTI register field. */
99197 #define ALT_EMAC_DMA_STAT_TTI_RESET 0x0
99198 /* Extracts the ALT_EMAC_DMA_STAT_TTI field value from a register. */
99199 #define ALT_EMAC_DMA_STAT_TTI_GET(value) (((value) & 0x20000000) >> 29)
99200 /* Produces a ALT_EMAC_DMA_STAT_TTI register field value suitable for setting the register. */
99201 #define ALT_EMAC_DMA_STAT_TTI_SET(value) (((value) << 29) & 0x20000000)
99202 
99203 /*
99204  * Field : GMAC LPI Interrupt (for Channel 0) - glpii
99205  *
99206  * This bit indicates an interrupt event in the LPI logic of the EMAC. To reset
99207  * this bit to 1'b0, the software must read the corresponding registers in the EMAC
99208  * to get the exact cause of the interrupt and clear its source.
99209  *
99210  * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high.
99211  *
99212  * Field Enumeration Values:
99213  *
99214  * Enum | Value | Description
99215  * :-------------------------------------|:------|:-------------------
99216  * ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP | 0x0 | No Interrupt
99217  * ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP | 0x1 | GMAC LPI Interrupt
99218  *
99219  * Field Access Macros:
99220  *
99221  */
99222 /*
99223  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
99224  *
99225  * No Interrupt
99226  */
99227 #define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP 0x0
99228 /*
99229  * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
99230  *
99231  * GMAC LPI Interrupt
99232  */
99233 #define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP 0x1
99234 
99235 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
99236 #define ALT_EMAC_DMA_STAT_GLPII_LSB 30
99237 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
99238 #define ALT_EMAC_DMA_STAT_GLPII_MSB 30
99239 /* The width in bits of the ALT_EMAC_DMA_STAT_GLPII register field. */
99240 #define ALT_EMAC_DMA_STAT_GLPII_WIDTH 1
99241 /* The mask used to set the ALT_EMAC_DMA_STAT_GLPII register field value. */
99242 #define ALT_EMAC_DMA_STAT_GLPII_SET_MSK 0x40000000
99243 /* The mask used to clear the ALT_EMAC_DMA_STAT_GLPII register field value. */
99244 #define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK 0xbfffffff
99245 /* The reset value of the ALT_EMAC_DMA_STAT_GLPII register field. */
99246 #define ALT_EMAC_DMA_STAT_GLPII_RESET 0x0
99247 /* Extracts the ALT_EMAC_DMA_STAT_GLPII field value from a register. */
99248 #define ALT_EMAC_DMA_STAT_GLPII_GET(value) (((value) & 0x40000000) >> 30)
99249 /* Produces a ALT_EMAC_DMA_STAT_GLPII register field value suitable for setting the register. */
99250 #define ALT_EMAC_DMA_STAT_GLPII_SET(value) (((value) << 30) & 0x40000000)
99251 
99252 #ifndef __ASSEMBLY__
99253 /*
99254  * WARNING: The C register and register group struct declarations are provided for
99255  * convenience and illustrative purposes. They should, however, be used with
99256  * caution as the C language standard provides no guarantees about the alignment or
99257  * atomicity of device memory accesses. The recommended practice for writing
99258  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
99259  * alt_write_word() functions.
99260  *
99261  * The struct declaration for register ALT_EMAC_DMA_STAT.
99262  */
99263 struct ALT_EMAC_DMA_STAT_s
99264 {
99265  uint32_t ti : 1; /* Transmit Interrupt */
99266  uint32_t tps : 1; /* Transmit Process Stopped */
99267  uint32_t tu : 1; /* Transmit Buffer Unavailable */
99268  uint32_t tjt : 1; /* Transmit Jabber Timeout */
99269  uint32_t ovf : 1; /* Receive Overflow */
99270  uint32_t unf : 1; /* Transmit Underflow */
99271  uint32_t ri : 1; /* Receive Interrupt */
99272  uint32_t ru : 1; /* Receive Buffer Unavailable */
99273  uint32_t rps : 1; /* Receive Process Stopped */
99274  uint32_t rwt : 1; /* Receive Watchdog Timeout */
99275  uint32_t eti : 1; /* Early Transmit Interrupt */
99276  uint32_t : 2; /* *UNDEFINED* */
99277  uint32_t fbi : 1; /* Fatal Bus Error Interrupt */
99278  uint32_t eri : 1; /* Early Receive Interrupt */
99279  uint32_t ais : 1; /* Abnormal Interrupt Summary */
99280  uint32_t nis : 1; /* Normal Interrupt Summary */
99281  const uint32_t rs : 3; /* Received Process State */
99282  const uint32_t ts : 3; /* Transmit Process State */
99283  const uint32_t eb : 3; /* Error Bits */
99284  const uint32_t gli : 1; /* GMAC Line Interface Interrupt */
99285  const uint32_t gmi : 1; /* GMAC MMC Interrupt */
99286  uint32_t : 1; /* *UNDEFINED* */
99287  const uint32_t tti : 1; /* Timestamp Trigger Interrupt */
99288  const uint32_t glpii : 1; /* GMAC LPI Interrupt (for Channel 0) */
99289  uint32_t : 1; /* *UNDEFINED* */
99290 };
99291 
99292 /* The typedef declaration for register ALT_EMAC_DMA_STAT. */
99293 typedef volatile struct ALT_EMAC_DMA_STAT_s ALT_EMAC_DMA_STAT_t;
99294 #endif /* __ASSEMBLY__ */
99295 
99296 /* The byte offset of the ALT_EMAC_DMA_STAT register from the beginning of the component. */
99297 #define ALT_EMAC_DMA_STAT_OFST 0x14
99298 /* The address of the ALT_EMAC_DMA_STAT register. */
99299 #define ALT_EMAC_DMA_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST))
99300 
99301 /*
99302  * Register : Register 6 (Operation Mode Register) - Operation_Mode
99303  *
99304  * The Operation Mode register establishes the Transmit and Receive operating modes
99305  * and commands. This register should be the last CSR to be written as part of the
99306  * DMA initialization.
99307  *
99308  * Register Layout
99309  *
99310  * Bits | Access | Reset | Description
99311  * :--------|:-------|:------|:-------------------------------------------------------------------------
99312  * [0] | ??? | 0x0 | *UNDEFINED*
99313  * [1] | RW | 0x0 | Start or Stop Receive
99314  * [2] | RW | 0x0 | Operate on Second Frame
99315  * [4:3] | RW | 0x0 | Receive Threshold Control
99316  * [5] | ??? | 0x0 | *UNDEFINED*
99317  * [6] | RW | 0x0 | Forward Undersized Good Frames
99318  * [7] | RW | 0x0 | Forward Error Frames
99319  * [8] | RW | 0x0 | Enable HW Flow Control
99320  * [10:9] | RW | 0x0 | Threshold for Activating Flow Control (in half-duplex and full-duplex)
99321  * [12:11] | RW | 0x0 | Threshold for Deactivating Flow Control (in half-duplex and full-duplex)
99322  * [13] | RW | 0x0 | Start or Stop Transmission Command
99323  * [16:14] | RW | 0x0 | Transmit Threshold Control
99324  * [19:17] | ??? | 0x0 | *UNDEFINED*
99325  * [20] | RW | 0x0 | Flush Transmit FIFO
99326  * [21] | RW | 0x0 | Transmit Store and Forward
99327  * [23:22] | ??? | 0x0 | *UNDEFINED*
99328  * [24] | RW | 0x0 | Disable Flushing of Received Frames
99329  * [25] | RW | 0x0 | Receive Store and Forward
99330  * [26] | RW | 0x0 | Disable Dropping of TCP/IP Checksum Error Frames
99331  * [31:27] | ??? | 0x0 | *UNDEFINED*
99332  *
99333  */
99334 /*
99335  * Field : Start or Stop Receive - sr
99336  *
99337  * When this bit is set, the Receive process is placed in the Running state. The
99338  * DMA attempts to acquire the descriptor from the Receive list and processes the
99339  * incoming frames. The descriptor acquisition is attempted from the current
99340  * position in the list, which is the address set by Register 3 (Receive Descriptor
99341  * List Address Register) or the position retained when the Receive process was
99342  * previously stopped. If the DMA does not own the descriptor, reception is
99343  * suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register)
99344  * is set. The Start Receive command is effective only when the reception has
99345  * stopped. If the command is issued before setting Register 3 (Receive Descriptor
99346  * List Address Register), the DMA behavior is unpredictable.
99347  *
99348  * When this bit is cleared, the Rx DMA operation is stopped after the transfer of
99349  * the current frame. The next descriptor position in the Receive list is saved and
99350  * becomes the current position after the Receive process is restarted. The Stop
99351  * Receive command is effective only when the Receive process is in either the
99352  * Running (waiting for receive packet) or in the Suspended state.
99353  *
99354  * Field Enumeration Values:
99355  *
99356  * Enum | Value | Description
99357  * :------------------------------|:------|:----------------------------
99358  * ALT_EMAC_DMA_OP_MOD_SR_E_DISD | 0x0 | Rx DMA operation is stopped
99359  * ALT_EMAC_DMA_OP_MOD_SR_E_END | 0x1 | Rx DMA operation is started
99360  *
99361  * Field Access Macros:
99362  *
99363  */
99364 /*
99365  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
99366  *
99367  * Rx DMA operation is stopped
99368  */
99369 #define ALT_EMAC_DMA_OP_MOD_SR_E_DISD 0x0
99370 /*
99371  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
99372  *
99373  * Rx DMA operation is started
99374  */
99375 #define ALT_EMAC_DMA_OP_MOD_SR_E_END 0x1
99376 
99377 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
99378 #define ALT_EMAC_DMA_OP_MOD_SR_LSB 1
99379 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
99380 #define ALT_EMAC_DMA_OP_MOD_SR_MSB 1
99381 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field. */
99382 #define ALT_EMAC_DMA_OP_MOD_SR_WIDTH 1
99383 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value. */
99384 #define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK 0x00000002
99385 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value. */
99386 #define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK 0xfffffffd
99387 /* The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field. */
99388 #define ALT_EMAC_DMA_OP_MOD_SR_RESET 0x0
99389 /* Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register. */
99390 #define ALT_EMAC_DMA_OP_MOD_SR_GET(value) (((value) & 0x00000002) >> 1)
99391 /* Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register. */
99392 #define ALT_EMAC_DMA_OP_MOD_SR_SET(value) (((value) << 1) & 0x00000002)
99393 
99394 /*
99395  * Field : Operate on Second Frame - osf
99396  *
99397  * When this bit is set, it instructs the DMA to process the second frame of the
99398  * Transmit data even before the status for the first frame is obtained.
99399  *
99400  * Field Enumeration Values:
99401  *
99402  * Enum | Value | Description
99403  * :-------------------------------|:------|:----------------------------------
99404  * ALT_EMAC_DMA_OP_MOD_OSF_E_DISD | 0x0 | DMA Does Not Process second frame
99405  * ALT_EMAC_DMA_OP_MOD_OSF_E_END | 0x1 | DMA Processes second frame
99406  *
99407  * Field Access Macros:
99408  *
99409  */
99410 /*
99411  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
99412  *
99413  * DMA Does Not Process second frame
99414  */
99415 #define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD 0x0
99416 /*
99417  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
99418  *
99419  * DMA Processes second frame
99420  */
99421 #define ALT_EMAC_DMA_OP_MOD_OSF_E_END 0x1
99422 
99423 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
99424 #define ALT_EMAC_DMA_OP_MOD_OSF_LSB 2
99425 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
99426 #define ALT_EMAC_DMA_OP_MOD_OSF_MSB 2
99427 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
99428 #define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH 1
99429 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
99430 #define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK 0x00000004
99431 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
99432 #define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK 0xfffffffb
99433 /* The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
99434 #define ALT_EMAC_DMA_OP_MOD_OSF_RESET 0x0
99435 /* Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register. */
99436 #define ALT_EMAC_DMA_OP_MOD_OSF_GET(value) (((value) & 0x00000004) >> 2)
99437 /* Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register. */
99438 #define ALT_EMAC_DMA_OP_MOD_OSF_SET(value) (((value) << 2) & 0x00000004)
99439 
99440 /*
99441  * Field : Receive Threshold Control - rtc
99442  *
99443  * These two bits control the threshold level of the MTL Receive FIFO. Transfer
99444  * (request) to DMA starts when the frame size within the MTL Receive FIFO is
99445  * larger than the threshold. In addition, full frames with length less than the
99446  * threshold are transferred automatically.
99447  *
99448  * These bits are valid only when the RSF bit is zero, and are ignored when the RSF
99449  * bit is set to 1.
99450  *
99451  * Field Enumeration Values:
99452  *
99453  * Enum | Value | Description
99454  * :-------------------------------------|:------|:---------------------------------
99455  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 | 0x0 | MTL Rcv Fifo threshold level 64
99456  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 | 0x1 | MTL Rcv Fifo threshold level 32
99457  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 | 0x2 | MTL Rcv Fifo threshold level 96
99458  * ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 | 0x3 | MTL Rcv Fifo threshold level 128
99459  *
99460  * Field Access Macros:
99461  *
99462  */
99463 /*
99464  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
99465  *
99466  * MTL Rcv Fifo threshold level 64
99467  */
99468 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 0x0
99469 /*
99470  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
99471  *
99472  * MTL Rcv Fifo threshold level 32
99473  */
99474 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 0x1
99475 /*
99476  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
99477  *
99478  * MTL Rcv Fifo threshold level 96
99479  */
99480 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 0x2
99481 /*
99482  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
99483  *
99484  * MTL Rcv Fifo threshold level 128
99485  */
99486 #define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 0x3
99487 
99488 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
99489 #define ALT_EMAC_DMA_OP_MOD_RTC_LSB 3
99490 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
99491 #define ALT_EMAC_DMA_OP_MOD_RTC_MSB 4
99492 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
99493 #define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH 2
99494 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
99495 #define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK 0x00000018
99496 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
99497 #define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK 0xffffffe7
99498 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
99499 #define ALT_EMAC_DMA_OP_MOD_RTC_RESET 0x0
99500 /* Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register. */
99501 #define ALT_EMAC_DMA_OP_MOD_RTC_GET(value) (((value) & 0x00000018) >> 3)
99502 /* Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register. */
99503 #define ALT_EMAC_DMA_OP_MOD_RTC_SET(value) (((value) << 3) & 0x00000018)
99504 
99505 /*
99506  * Field : Forward Undersized Good Frames - fuf
99507  *
99508  * When set, the Rx FIFO forwards Undersized frames (frames with no Error and
99509  * length less than 64 bytes) including pad-bytes and CRC.
99510  *
99511  * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame
99512  * is already transferred because of the lower value of Receive Threshold, for
99513  * example, RTC = 01.
99514  *
99515  * Field Enumeration Values:
99516  *
99517  * Enum | Value | Description
99518  * :-------------------------------|:------|:-------------------------------
99519  * ALT_EMAC_DMA_OP_MOD_FUF_E_DISD | 0x0 | Drops Frames less than 64Bytes
99520  * ALT_EMAC_DMA_OP_MOD_FUF_E_END | 0x1 | Forward Frames with no errors
99521  *
99522  * Field Access Macros:
99523  *
99524  */
99525 /*
99526  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
99527  *
99528  * Drops Frames less than 64Bytes
99529  */
99530 #define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD 0x0
99531 /*
99532  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
99533  *
99534  * Forward Frames with no errors
99535  */
99536 #define ALT_EMAC_DMA_OP_MOD_FUF_E_END 0x1
99537 
99538 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
99539 #define ALT_EMAC_DMA_OP_MOD_FUF_LSB 6
99540 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
99541 #define ALT_EMAC_DMA_OP_MOD_FUF_MSB 6
99542 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
99543 #define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH 1
99544 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
99545 #define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK 0x00000040
99546 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
99547 #define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK 0xffffffbf
99548 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
99549 #define ALT_EMAC_DMA_OP_MOD_FUF_RESET 0x0
99550 /* Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register. */
99551 #define ALT_EMAC_DMA_OP_MOD_FUF_GET(value) (((value) & 0x00000040) >> 6)
99552 /* Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register. */
99553 #define ALT_EMAC_DMA_OP_MOD_FUF_SET(value) (((value) << 6) & 0x00000040)
99554 
99555 /*
99556  * Field : Forward Error Frames - fef
99557  *
99558  * When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
99559  * collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However,
99560  * if the start byte (write) pointer of a frame is already transferred to the read
99561  * controller side (in Threshold mode), then the frame is not dropped.
99562  *
99563  * When the FEF bit is set, all frames except runt error frames are forwarded to
99564  * the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial
99565  * frame is written, then the frame is dropped irrespective of the FEF bit setting.
99566  * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial
99567  * frame is written, then a partial frame may be forwarded to the DMA.
99568  *
99569  * Field Enumeration Values:
99570  *
99571  * Enum | Value | Description
99572  * :-------------------------------|:------|:--------------------------------
99573  * ALT_EMAC_DMA_OP_MOD_FEF_E_DISD | 0x0 | Drops Frames with error status
99574  * ALT_EMAC_DMA_OP_MOD_FEF_E_END | 0x1 | Forward all Frames(except runt)
99575  *
99576  * Field Access Macros:
99577  *
99578  */
99579 /*
99580  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
99581  *
99582  * Drops Frames with error status
99583  */
99584 #define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD 0x0
99585 /*
99586  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
99587  *
99588  * Forward all Frames(except runt)
99589  */
99590 #define ALT_EMAC_DMA_OP_MOD_FEF_E_END 0x1
99591 
99592 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
99593 #define ALT_EMAC_DMA_OP_MOD_FEF_LSB 7
99594 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
99595 #define ALT_EMAC_DMA_OP_MOD_FEF_MSB 7
99596 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
99597 #define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH 1
99598 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
99599 #define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK 0x00000080
99600 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
99601 #define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK 0xffffff7f
99602 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
99603 #define ALT_EMAC_DMA_OP_MOD_FEF_RESET 0x0
99604 /* Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register. */
99605 #define ALT_EMAC_DMA_OP_MOD_FEF_GET(value) (((value) & 0x00000080) >> 7)
99606 /* Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register. */
99607 #define ALT_EMAC_DMA_OP_MOD_FEF_SET(value) (((value) << 7) & 0x00000080)
99608 
99609 /*
99610  * Field : Enable HW Flow Control - efc
99611  *
99612  * When this bit is set, the flow control signal operation based on the fill-level
99613  * of Rx FIFO is enabled. When reset, the flow control operation is disabled.
99614  *
99615  * Field Enumeration Values:
99616  *
99617  * Enum | Value | Description
99618  * :-------------------------------|:------|:--------------------------------
99619  * ALT_EMAC_DMA_OP_MOD_EFC_E_DISD | 0x0 | Rx FIFO Fill Level Disabled
99620  * ALT_EMAC_DMA_OP_MOD_EFC_E_END | 0x1 | Rx FIFO Fill Level Enabled Ctrl
99621  *
99622  * Field Access Macros:
99623  *
99624  */
99625 /*
99626  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
99627  *
99628  * Rx FIFO Fill Level Disabled
99629  */
99630 #define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD 0x0
99631 /*
99632  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
99633  *
99634  * Rx FIFO Fill Level Enabled Ctrl
99635  */
99636 #define ALT_EMAC_DMA_OP_MOD_EFC_E_END 0x1
99637 
99638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
99639 #define ALT_EMAC_DMA_OP_MOD_EFC_LSB 8
99640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
99641 #define ALT_EMAC_DMA_OP_MOD_EFC_MSB 8
99642 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
99643 #define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH 1
99644 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
99645 #define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK 0x00000100
99646 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
99647 #define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK 0xfffffeff
99648 /* The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
99649 #define ALT_EMAC_DMA_OP_MOD_EFC_RESET 0x0
99650 /* Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register. */
99651 #define ALT_EMAC_DMA_OP_MOD_EFC_GET(value) (((value) & 0x00000100) >> 8)
99652 /* Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register. */
99653 #define ALT_EMAC_DMA_OP_MOD_EFC_SET(value) (((value) << 8) & 0x00000100)
99654 
99655 /*
99656  * Field : Threshold for Activating Flow Control (in half-duplex and full-duplex) - rfa
99657  *
99658  * These bits control the threshold (Fill level of Rx FIFO) at which the flow
99659  * control is activated.
99660  *
99661  * These values only apply to the Rx FIFO when the EFC bit is set high.
99662  *
99663  * Field Enumeration Values:
99664  *
99665  * Enum | Value | Description
99666  * :--------------------------------------|:------|:----------------
99667  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K | 0x0 | Full minus 1 KB
99668  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K | 0x1 | Full minus 2 KB
99669  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K | 0x2 | Full minus 3 KB
99670  * ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K | 0x3 | Full minus 4 KB
99671  *
99672  * Field Access Macros:
99673  *
99674  */
99675 /*
99676  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
99677  *
99678  * Full minus 1 KB
99679  */
99680 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K 0x0
99681 /*
99682  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
99683  *
99684  * Full minus 2 KB
99685  */
99686 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K 0x1
99687 /*
99688  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
99689  *
99690  * Full minus 3 KB
99691  */
99692 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K 0x2
99693 /*
99694  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
99695  *
99696  * Full minus 4 KB
99697  */
99698 #define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K 0x3
99699 
99700 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
99701 #define ALT_EMAC_DMA_OP_MOD_RFA_LSB 9
99702 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
99703 #define ALT_EMAC_DMA_OP_MOD_RFA_MSB 10
99704 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
99705 #define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH 2
99706 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
99707 #define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK 0x00000600
99708 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
99709 #define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK 0xfffff9ff
99710 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
99711 #define ALT_EMAC_DMA_OP_MOD_RFA_RESET 0x0
99712 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register. */
99713 #define ALT_EMAC_DMA_OP_MOD_RFA_GET(value) (((value) & 0x00000600) >> 9)
99714 /* Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register. */
99715 #define ALT_EMAC_DMA_OP_MOD_RFA_SET(value) (((value) << 9) & 0x00000600)
99716 
99717 /*
99718  * Field : Threshold for Deactivating Flow Control (in half-duplex and full-duplex) - rfd
99719  *
99720  * These bits control the threshold (Fill-level of Rx FIFO) at which the flow
99721  * control is de-asserted after activation.
99722  *
99723  * The de-assertion is effective only after flow control is asserted.
99724  *
99725  * Field Enumeration Values:
99726  *
99727  * Enum | Value | Description
99728  * :--------------------------------------|:------|:----------------
99729  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K | 0x0 | Full minus 1 KB
99730  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K | 0x1 | Full minus 2 KB
99731  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K | 0x2 | Full minus 3 KB
99732  * ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K | 0x3 | Full minus 4 KB
99733  *
99734  * Field Access Macros:
99735  *
99736  */
99737 /*
99738  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
99739  *
99740  * Full minus 1 KB
99741  */
99742 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K 0x0
99743 /*
99744  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
99745  *
99746  * Full minus 2 KB
99747  */
99748 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K 0x1
99749 /*
99750  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
99751  *
99752  * Full minus 3 KB
99753  */
99754 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K 0x2
99755 /*
99756  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
99757  *
99758  * Full minus 4 KB
99759  */
99760 #define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K 0x3
99761 
99762 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
99763 #define ALT_EMAC_DMA_OP_MOD_RFD_LSB 11
99764 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
99765 #define ALT_EMAC_DMA_OP_MOD_RFD_MSB 12
99766 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
99767 #define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH 2
99768 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
99769 #define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK 0x00001800
99770 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
99771 #define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK 0xffffe7ff
99772 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
99773 #define ALT_EMAC_DMA_OP_MOD_RFD_RESET 0x0
99774 /* Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register. */
99775 #define ALT_EMAC_DMA_OP_MOD_RFD_GET(value) (((value) & 0x00001800) >> 11)
99776 /* Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register. */
99777 #define ALT_EMAC_DMA_OP_MOD_RFD_SET(value) (((value) << 11) & 0x00001800)
99778 
99779 /*
99780  * Field : Start or Stop Transmission Command - st
99781  *
99782  * When this bit is set, transmission is placed in the Running state, and the DMA
99783  * checks the Transmit List at the current position for a frame to be transmitted.
99784  * Descriptor acquisition is attempted either from the current position in the
99785  * list, which is the Transmit List Base Address set by Register 4 (Transmit
99786  * Descriptor List Address Register), or from the position retained when
99787  * transmission was stopped previously. If the DMA does not own the current
99788  * descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer
99789  * Unavailable) of Register 5 (Status Register) is set. The Start Transmission
99790  * command is effective only when transmission is stopped. If the command is issued
99791  * before setting Register 4 (Transmit Descriptor List Address Register), then the
99792  * DMA behavior is unpredictable.
99793  *
99794  * When this bit is reset, the transmission process is placed in the Stopped state
99795  * after completing the transmission of the current frame. The Next Descriptor
99796  * position in the Transmit List is saved, and it becomes the current position when
99797  * transmission is restarted. To change the list address, you need to program
99798  * Register 4 (Transmit Descriptor List Address Register) with a new value when
99799  * this bit is reset. The new value is considered when this bit is set again. The
99800  * stop transmission command is effective only when the transmission of the current
99801  * frame is complete or the transmission is in the Suspended state.
99802  *
99803  * Field Enumeration Values:
99804  *
99805  * Enum | Value | Description
99806  * :------------------------------|:------|:---------------------------
99807  * ALT_EMAC_DMA_OP_MOD_ST_E_DISD | 0x0 | Transmission Stopped State
99808  * ALT_EMAC_DMA_OP_MOD_ST_E_END | 0x1 | Transmission in Run State
99809  *
99810  * Field Access Macros:
99811  *
99812  */
99813 /*
99814  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
99815  *
99816  * Transmission Stopped State
99817  */
99818 #define ALT_EMAC_DMA_OP_MOD_ST_E_DISD 0x0
99819 /*
99820  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
99821  *
99822  * Transmission in Run State
99823  */
99824 #define ALT_EMAC_DMA_OP_MOD_ST_E_END 0x1
99825 
99826 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
99827 #define ALT_EMAC_DMA_OP_MOD_ST_LSB 13
99828 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
99829 #define ALT_EMAC_DMA_OP_MOD_ST_MSB 13
99830 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field. */
99831 #define ALT_EMAC_DMA_OP_MOD_ST_WIDTH 1
99832 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value. */
99833 #define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK 0x00002000
99834 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value. */
99835 #define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK 0xffffdfff
99836 /* The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field. */
99837 #define ALT_EMAC_DMA_OP_MOD_ST_RESET 0x0
99838 /* Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register. */
99839 #define ALT_EMAC_DMA_OP_MOD_ST_GET(value) (((value) & 0x00002000) >> 13)
99840 /* Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register. */
99841 #define ALT_EMAC_DMA_OP_MOD_ST_SET(value) (((value) << 13) & 0x00002000)
99842 
99843 /*
99844  * Field : Transmit Threshold Control - ttc
99845  *
99846  * These bits control the threshold level of the MTL Transmit FIFO. Transmission
99847  * starts when the frame size within the MTL Transmit FIFO is larger than the
99848  * threshold. In addition, full frames with a length less than the threshold are
99849  * also transmitted. These bits are used only when Bit 21 (TSF) is reset.
99850  *
99851  * Field Enumeration Values:
99852  *
99853  * Enum | Value | Description
99854  * :--------------------------------------|:------|:--------------------------------
99855  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 | 0x0 | MTL Transmit FIFO Threshold 64
99856  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 | 0x1 | MTL Transmit FIFO Threshold 128
99857  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 | 0x2 | MTL Transmit FIFO Threshold 192
99858  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 | 0x3 | MTL Transmit FIFO Threshold 256
99859  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 | 0x4 | MTL Transmit FIFO Threshold 40
99860  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 | 0x5 | MTL Transmit FIFO Threshold 32
99861  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 | 0x6 | MTL Transmit FIFO Threshold 24
99862  * ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 | 0x7 | MTL Transmit FIFO Threshold 16
99863  *
99864  * Field Access Macros:
99865  *
99866  */
99867 /*
99868  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99869  *
99870  * MTL Transmit FIFO Threshold 64
99871  */
99872 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 0x0
99873 /*
99874  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99875  *
99876  * MTL Transmit FIFO Threshold 128
99877  */
99878 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 0x1
99879 /*
99880  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99881  *
99882  * MTL Transmit FIFO Threshold 192
99883  */
99884 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 0x2
99885 /*
99886  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99887  *
99888  * MTL Transmit FIFO Threshold 256
99889  */
99890 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 0x3
99891 /*
99892  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99893  *
99894  * MTL Transmit FIFO Threshold 40
99895  */
99896 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 0x4
99897 /*
99898  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99899  *
99900  * MTL Transmit FIFO Threshold 32
99901  */
99902 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 0x5
99903 /*
99904  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99905  *
99906  * MTL Transmit FIFO Threshold 24
99907  */
99908 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 0x6
99909 /*
99910  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
99911  *
99912  * MTL Transmit FIFO Threshold 16
99913  */
99914 #define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 0x7
99915 
99916 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
99917 #define ALT_EMAC_DMA_OP_MOD_TTC_LSB 14
99918 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
99919 #define ALT_EMAC_DMA_OP_MOD_TTC_MSB 16
99920 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
99921 #define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH 3
99922 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
99923 #define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK 0x0001c000
99924 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
99925 #define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK 0xfffe3fff
99926 /* The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
99927 #define ALT_EMAC_DMA_OP_MOD_TTC_RESET 0x0
99928 /* Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register. */
99929 #define ALT_EMAC_DMA_OP_MOD_TTC_GET(value) (((value) & 0x0001c000) >> 14)
99930 /* Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register. */
99931 #define ALT_EMAC_DMA_OP_MOD_TTC_SET(value) (((value) << 14) & 0x0001c000)
99932 
99933 /*
99934  * Field : Flush Transmit FIFO - ftf
99935  *
99936  * When this bit is set, the transmit FIFO controller logic is reset to its default
99937  * values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared
99938  * internally when the flushing operation is completed. The Operation Mode register
99939  * should not be written to until this bit is cleared. The data which is already
99940  * accepted by the MAC transmitter is not flushed. It is scheduled for transmission
99941  * and results in underflow and runt frame transmission.
99942  *
99943  * Note: The flush operation is complete only when the Tx FIFO is emptied of its
99944  * contents and all the pending Transmit Status of the transmitted frames are
99945  * accepted by the host. To complete this flush operation, the PHY transmit clock
99946  * is required to be active.
99947  *
99948  * Field Enumeration Values:
99949  *
99950  * Enum | Value | Description
99951  * :-------------------------------|:------|:-------------------------
99952  * ALT_EMAC_DMA_OP_MOD_FTF_E_DISD | 0x0 | Tx FIFO Data not Flushed
99953  * ALT_EMAC_DMA_OP_MOD_FTF_E_END | 0x1 | TX FIFO Data Flushed
99954  *
99955  * Field Access Macros:
99956  *
99957  */
99958 /*
99959  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
99960  *
99961  * Tx FIFO Data not Flushed
99962  */
99963 #define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD 0x0
99964 /*
99965  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
99966  *
99967  * TX FIFO Data Flushed
99968  */
99969 #define ALT_EMAC_DMA_OP_MOD_FTF_E_END 0x1
99970 
99971 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
99972 #define ALT_EMAC_DMA_OP_MOD_FTF_LSB 20
99973 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
99974 #define ALT_EMAC_DMA_OP_MOD_FTF_MSB 20
99975 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
99976 #define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH 1
99977 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
99978 #define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK 0x00100000
99979 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
99980 #define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK 0xffefffff
99981 /* The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
99982 #define ALT_EMAC_DMA_OP_MOD_FTF_RESET 0x0
99983 /* Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register. */
99984 #define ALT_EMAC_DMA_OP_MOD_FTF_GET(value) (((value) & 0x00100000) >> 20)
99985 /* Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register. */
99986 #define ALT_EMAC_DMA_OP_MOD_FTF_SET(value) (((value) << 20) & 0x00100000)
99987 
99988 /*
99989  * Field : Transmit Store and Forward - tsf
99990  *
99991  * When this bit is set, transmission starts when a full frame resides in the MTL
99992  * Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are
99993  * ignored. This bit should be changed only when the transmission is stopped.
99994  *
99995  * Field Enumeration Values:
99996  *
99997  * Enum | Value | Description
99998  * :-------------------------------|:------|:----------------------------------
99999  * ALT_EMAC_DMA_OP_MOD_TSF_E_DISD | 0x0 | Tx Does not Start with Full Frame
100000  * ALT_EMAC_DMA_OP_MOD_TSF_E_END | 0x1 | Tx Start with Full Frame
100001  *
100002  * Field Access Macros:
100003  *
100004  */
100005 /*
100006  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
100007  *
100008  * Tx Does not Start with Full Frame
100009  */
100010 #define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD 0x0
100011 /*
100012  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
100013  *
100014  * Tx Start with Full Frame
100015  */
100016 #define ALT_EMAC_DMA_OP_MOD_TSF_E_END 0x1
100017 
100018 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
100019 #define ALT_EMAC_DMA_OP_MOD_TSF_LSB 21
100020 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
100021 #define ALT_EMAC_DMA_OP_MOD_TSF_MSB 21
100022 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
100023 #define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH 1
100024 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
100025 #define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK 0x00200000
100026 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
100027 #define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK 0xffdfffff
100028 /* The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
100029 #define ALT_EMAC_DMA_OP_MOD_TSF_RESET 0x0
100030 /* Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register. */
100031 #define ALT_EMAC_DMA_OP_MOD_TSF_GET(value) (((value) & 0x00200000) >> 21)
100032 /* Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register. */
100033 #define ALT_EMAC_DMA_OP_MOD_TSF_SET(value) (((value) << 21) & 0x00200000)
100034 
100035 /*
100036  * Field : Disable Flushing of Received Frames - dff
100037  *
100038  * When this bit is set, the Rx DMA does not flush any frames because of the
100039  * unavailability of receive descriptors or buffers as it does normally when this
100040  * bit is reset.
100041  *
100042  * Field Enumeration Values:
100043  *
100044  * Enum | Value | Description
100045  * :-------------------------------|:------|:-------------------
100046  * ALT_EMAC_DMA_OP_MOD_DFF_E_DISD | 0x0 | Rx DMA Flushed
100047  * ALT_EMAC_DMA_OP_MOD_DFF_E_END | 0x1 | Rx DMA not Flushed
100048  *
100049  * Field Access Macros:
100050  *
100051  */
100052 /*
100053  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
100054  *
100055  * Rx DMA Flushed
100056  */
100057 #define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD 0x0
100058 /*
100059  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
100060  *
100061  * Rx DMA not Flushed
100062  */
100063 #define ALT_EMAC_DMA_OP_MOD_DFF_E_END 0x1
100064 
100065 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
100066 #define ALT_EMAC_DMA_OP_MOD_DFF_LSB 24
100067 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
100068 #define ALT_EMAC_DMA_OP_MOD_DFF_MSB 24
100069 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
100070 #define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH 1
100071 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
100072 #define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK 0x01000000
100073 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
100074 #define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK 0xfeffffff
100075 /* The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
100076 #define ALT_EMAC_DMA_OP_MOD_DFF_RESET 0x0
100077 /* Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register. */
100078 #define ALT_EMAC_DMA_OP_MOD_DFF_GET(value) (((value) & 0x01000000) >> 24)
100079 /* Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register. */
100080 #define ALT_EMAC_DMA_OP_MOD_DFF_SET(value) (((value) << 24) & 0x01000000)
100081 
100082 /*
100083  * Field : Receive Store and Forward - rsf
100084  *
100085  * When this bit is set, the MTL reads a frame from the Rx FIFO only after the
100086  * complete frame has been written to it, ignoring the RTC bits. When this bit is
100087  * reset, the Rx FIFO operates in the cut-through mode, subject to the threshold
100088  * specified by the RTC bits.
100089  *
100090  * Field Enumeration Values:
100091  *
100092  * Enum | Value | Description
100093  * :-------------------------------|:------|:---------------------------------------
100094  * ALT_EMAC_DMA_OP_MOD_RSF_E_DISD | 0x0 | Rx Fifo cut-through mode
100095  * ALT_EMAC_DMA_OP_MOD_RSF_E_END | 0x1 | Read Rx FIFO only after complete frame
100096  *
100097  * Field Access Macros:
100098  *
100099  */
100100 /*
100101  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
100102  *
100103  * Rx Fifo cut-through mode
100104  */
100105 #define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD 0x0
100106 /*
100107  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
100108  *
100109  * Read Rx FIFO only after complete frame
100110  */
100111 #define ALT_EMAC_DMA_OP_MOD_RSF_E_END 0x1
100112 
100113 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
100114 #define ALT_EMAC_DMA_OP_MOD_RSF_LSB 25
100115 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
100116 #define ALT_EMAC_DMA_OP_MOD_RSF_MSB 25
100117 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
100118 #define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH 1
100119 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
100120 #define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK 0x02000000
100121 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
100122 #define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK 0xfdffffff
100123 /* The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
100124 #define ALT_EMAC_DMA_OP_MOD_RSF_RESET 0x0
100125 /* Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register. */
100126 #define ALT_EMAC_DMA_OP_MOD_RSF_GET(value) (((value) & 0x02000000) >> 25)
100127 /* Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register. */
100128 #define ALT_EMAC_DMA_OP_MOD_RSF_SET(value) (((value) << 25) & 0x02000000)
100129 
100130 /*
100131  * Field : Disable Dropping of TCP/IP Checksum Error Frames - dt
100132  *
100133  * When this bit is set, the MAC does not drop the frames which only have errors
100134  * detected by the Receive Checksum Offload engine. Such frames do not have any
100135  * errors (including FCS error) in the Ethernet frame received by the MAC but have
100136  * errors only in the encapsulated payload. When this bit is reset, all error
100137  * frames are dropped if the FEF bit is reset.
100138  *
100139  * Field Enumeration Values:
100140  *
100141  * Enum | Value | Description
100142  * :------------------------------|:------|:------------------------------------
100143  * ALT_EMAC_DMA_OP_MOD_DT_E_DISD | 0x0 | All Error Frames Dropped
100144  * ALT_EMAC_DMA_OP_MOD_DT_E_END | 0x1 | MAC does not drop frame with errors
100145  *
100146  * Field Access Macros:
100147  *
100148  */
100149 /*
100150  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
100151  *
100152  * All Error Frames Dropped
100153  */
100154 #define ALT_EMAC_DMA_OP_MOD_DT_E_DISD 0x0
100155 /*
100156  * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
100157  *
100158  * MAC does not drop frame with errors
100159  */
100160 #define ALT_EMAC_DMA_OP_MOD_DT_E_END 0x1
100161 
100162 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
100163 #define ALT_EMAC_DMA_OP_MOD_DT_LSB 26
100164 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
100165 #define ALT_EMAC_DMA_OP_MOD_DT_MSB 26
100166 /* The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field. */
100167 #define ALT_EMAC_DMA_OP_MOD_DT_WIDTH 1
100168 /* The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value. */
100169 #define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK 0x04000000
100170 /* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value. */
100171 #define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK 0xfbffffff
100172 /* The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field. */
100173 #define ALT_EMAC_DMA_OP_MOD_DT_RESET 0x0
100174 /* Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register. */
100175 #define ALT_EMAC_DMA_OP_MOD_DT_GET(value) (((value) & 0x04000000) >> 26)
100176 /* Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register. */
100177 #define ALT_EMAC_DMA_OP_MOD_DT_SET(value) (((value) << 26) & 0x04000000)
100178 
100179 #ifndef __ASSEMBLY__
100180 /*
100181  * WARNING: The C register and register group struct declarations are provided for
100182  * convenience and illustrative purposes. They should, however, be used with
100183  * caution as the C language standard provides no guarantees about the alignment or
100184  * atomicity of device memory accesses. The recommended practice for writing
100185  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100186  * alt_write_word() functions.
100187  *
100188  * The struct declaration for register ALT_EMAC_DMA_OP_MOD.
100189  */
100190 struct ALT_EMAC_DMA_OP_MOD_s
100191 {
100192  uint32_t : 1; /* *UNDEFINED* */
100193  uint32_t sr : 1; /* Start or Stop Receive */
100194  uint32_t osf : 1; /* Operate on Second Frame */
100195  uint32_t rtc : 2; /* Receive Threshold Control */
100196  uint32_t : 1; /* *UNDEFINED* */
100197  uint32_t fuf : 1; /* Forward Undersized Good Frames */
100198  uint32_t fef : 1; /* Forward Error Frames */
100199  uint32_t efc : 1; /* Enable HW Flow Control */
100200  uint32_t rfa : 2; /* Threshold for Activating Flow Control (in half-duplex and full-duplex) */
100201  uint32_t rfd : 2; /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex) */
100202  uint32_t st : 1; /* Start or Stop Transmission Command */
100203  uint32_t ttc : 3; /* Transmit Threshold Control */
100204  uint32_t : 3; /* *UNDEFINED* */
100205  uint32_t ftf : 1; /* Flush Transmit FIFO */
100206  uint32_t tsf : 1; /* Transmit Store and Forward */
100207  uint32_t : 2; /* *UNDEFINED* */
100208  uint32_t dff : 1; /* Disable Flushing of Received Frames */
100209  uint32_t rsf : 1; /* Receive Store and Forward */
100210  uint32_t dt : 1; /* Disable Dropping of TCP/IP Checksum Error Frames */
100211  uint32_t : 5; /* *UNDEFINED* */
100212 };
100213 
100214 /* The typedef declaration for register ALT_EMAC_DMA_OP_MOD. */
100215 typedef volatile struct ALT_EMAC_DMA_OP_MOD_s ALT_EMAC_DMA_OP_MOD_t;
100216 #endif /* __ASSEMBLY__ */
100217 
100218 /* The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component. */
100219 #define ALT_EMAC_DMA_OP_MOD_OFST 0x18
100220 /* The address of the ALT_EMAC_DMA_OP_MOD register. */
100221 #define ALT_EMAC_DMA_OP_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST))
100222 
100223 /*
100224  * Register : Register 7 (Interrupt Enable Register) - Interrupt_Enable
100225  *
100226  * The Interrupt Enable register enables the interrupts reported by Register 5
100227  * (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt.
100228  * After a hardware or software reset, all interrupts are disabled.
100229  *
100230  * Register Layout
100231  *
100232  * Bits | Access | Reset | Description
100233  * :--------|:-------|:------|:----------------------------------
100234  * [0] | RW | 0x0 | Transmit Interrupt Enable
100235  * [1] | RW | 0x0 | Transmit Stopped Enable
100236  * [2] | RW | 0x0 | Transmit Buffer Unvailable Enable
100237  * [3] | RW | 0x0 | Transmit Jabber Timeout Enable
100238  * [4] | RW | 0x0 | Overflow Interrupt Enable
100239  * [5] | RW | 0x0 | Underflow Interrupt Enable
100240  * [6] | RW | 0x0 | Receive Interrupt Enable
100241  * [7] | RW | 0x0 | Receive Buffer Unavailable Enable
100242  * [8] | RW | 0x0 | Receive Stopped Enable
100243  * [9] | RW | 0x0 | Receive Watchdog Timeout Enable
100244  * [10] | RW | 0x0 | Early Transmit Interrupt Enable
100245  * [12:11] | ??? | 0x0 | *UNDEFINED*
100246  * [13] | RW | 0x0 | Fatal Bus Error Enable
100247  * [14] | RW | 0x0 | Early Receive Interrupt Enable
100248  * [15] | RW | 0x0 | Abnormal Interrupt Summary Enable
100249  * [16] | RW | 0x0 | Normal Interrupt Summary Enable
100250  * [31:17] | ??? | 0x0 | *UNDEFINED*
100251  *
100252  */
100253 /*
100254  * Field : Transmit Interrupt Enable - tie
100255  *
100256  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
100257  * Interrupt is enabled. When this bit is reset, the Transmit Interrupt is
100258  * disabled.
100259  *
100260  * Field Enumeration Values:
100261  *
100262  * Enum | Value | Description
100263  * :-------------------------------|:------|:----------------------------
100264  * ALT_EMAC_DMA_INT_EN_TIE_E_DISD | 0x0 | Transmit Interrupt Disabled
100265  * ALT_EMAC_DMA_INT_EN_TIE_E_END | 0x1 | Transmit Interrupt Enabled
100266  *
100267  * Field Access Macros:
100268  *
100269  */
100270 /*
100271  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
100272  *
100273  * Transmit Interrupt Disabled
100274  */
100275 #define ALT_EMAC_DMA_INT_EN_TIE_E_DISD 0x0
100276 /*
100277  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
100278  *
100279  * Transmit Interrupt Enabled
100280  */
100281 #define ALT_EMAC_DMA_INT_EN_TIE_E_END 0x1
100282 
100283 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
100284 #define ALT_EMAC_DMA_INT_EN_TIE_LSB 0
100285 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
100286 #define ALT_EMAC_DMA_INT_EN_TIE_MSB 0
100287 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TIE register field. */
100288 #define ALT_EMAC_DMA_INT_EN_TIE_WIDTH 1
100289 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TIE register field value. */
100290 #define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK 0x00000001
100291 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TIE register field value. */
100292 #define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK 0xfffffffe
100293 /* The reset value of the ALT_EMAC_DMA_INT_EN_TIE register field. */
100294 #define ALT_EMAC_DMA_INT_EN_TIE_RESET 0x0
100295 /* Extracts the ALT_EMAC_DMA_INT_EN_TIE field value from a register. */
100296 #define ALT_EMAC_DMA_INT_EN_TIE_GET(value) (((value) & 0x00000001) >> 0)
100297 /* Produces a ALT_EMAC_DMA_INT_EN_TIE register field value suitable for setting the register. */
100298 #define ALT_EMAC_DMA_INT_EN_TIE_SET(value) (((value) << 0) & 0x00000001)
100299 
100300 /*
100301  * Field : Transmit Stopped Enable - tse
100302  *
100303  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100304  * Transmission Stopped Interrupt is enabled. When this bit is reset, the
100305  * Transmission Stopped Interrupt is disabled.
100306  *
100307  * Field Enumeration Values:
100308  *
100309  * Enum | Value | Description
100310  * :-------------------------------|:------|:------------------------------------
100311  * ALT_EMAC_DMA_INT_EN_TSE_E_DISD | 0x0 | Transmit Stopped Interrupt Disabled
100312  * ALT_EMAC_DMA_INT_EN_TSE_E_END | 0x1 | Transmit Stopped Interrupt Enabled
100313  *
100314  * Field Access Macros:
100315  *
100316  */
100317 /*
100318  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
100319  *
100320  * Transmit Stopped Interrupt Disabled
100321  */
100322 #define ALT_EMAC_DMA_INT_EN_TSE_E_DISD 0x0
100323 /*
100324  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
100325  *
100326  * Transmit Stopped Interrupt Enabled
100327  */
100328 #define ALT_EMAC_DMA_INT_EN_TSE_E_END 0x1
100329 
100330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
100331 #define ALT_EMAC_DMA_INT_EN_TSE_LSB 1
100332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
100333 #define ALT_EMAC_DMA_INT_EN_TSE_MSB 1
100334 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TSE register field. */
100335 #define ALT_EMAC_DMA_INT_EN_TSE_WIDTH 1
100336 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TSE register field value. */
100337 #define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK 0x00000002
100338 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TSE register field value. */
100339 #define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK 0xfffffffd
100340 /* The reset value of the ALT_EMAC_DMA_INT_EN_TSE register field. */
100341 #define ALT_EMAC_DMA_INT_EN_TSE_RESET 0x0
100342 /* Extracts the ALT_EMAC_DMA_INT_EN_TSE field value from a register. */
100343 #define ALT_EMAC_DMA_INT_EN_TSE_GET(value) (((value) & 0x00000002) >> 1)
100344 /* Produces a ALT_EMAC_DMA_INT_EN_TSE register field value suitable for setting the register. */
100345 #define ALT_EMAC_DMA_INT_EN_TSE_SET(value) (((value) << 1) & 0x00000002)
100346 
100347 /*
100348  * Field : Transmit Buffer Unvailable Enable - tue
100349  *
100350  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
100351  * Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit
100352  * Buffer Unavailable Interrupt is disabled.
100353  *
100354  * Field Enumeration Values:
100355  *
100356  * Enum | Value | Description
100357  * :-------------------------------|:------|:-----------------------------------------------
100358  * ALT_EMAC_DMA_INT_EN_TUE_E_DISD | 0x0 | Transmit Buffer Unavailable Interrupt Disabled
100359  * ALT_EMAC_DMA_INT_EN_TUE_E_END | 0x1 | Transmit Buffer Unavailable Interrupt Enabled
100360  *
100361  * Field Access Macros:
100362  *
100363  */
100364 /*
100365  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
100366  *
100367  * Transmit Buffer Unavailable Interrupt Disabled
100368  */
100369 #define ALT_EMAC_DMA_INT_EN_TUE_E_DISD 0x0
100370 /*
100371  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
100372  *
100373  * Transmit Buffer Unavailable Interrupt Enabled
100374  */
100375 #define ALT_EMAC_DMA_INT_EN_TUE_E_END 0x1
100376 
100377 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
100378 #define ALT_EMAC_DMA_INT_EN_TUE_LSB 2
100379 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
100380 #define ALT_EMAC_DMA_INT_EN_TUE_MSB 2
100381 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TUE register field. */
100382 #define ALT_EMAC_DMA_INT_EN_TUE_WIDTH 1
100383 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TUE register field value. */
100384 #define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK 0x00000004
100385 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TUE register field value. */
100386 #define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK 0xfffffffb
100387 /* The reset value of the ALT_EMAC_DMA_INT_EN_TUE register field. */
100388 #define ALT_EMAC_DMA_INT_EN_TUE_RESET 0x0
100389 /* Extracts the ALT_EMAC_DMA_INT_EN_TUE field value from a register. */
100390 #define ALT_EMAC_DMA_INT_EN_TUE_GET(value) (((value) & 0x00000004) >> 2)
100391 /* Produces a ALT_EMAC_DMA_INT_EN_TUE register field value suitable for setting the register. */
100392 #define ALT_EMAC_DMA_INT_EN_TUE_SET(value) (((value) << 2) & 0x00000004)
100393 
100394 /*
100395  * Field : Transmit Jabber Timeout Enable - tje
100396  *
100397  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100398  * Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the
100399  * Transmit Jabber Timeout Interrupt is disabled.
100400  *
100401  * Field Enumeration Values:
100402  *
100403  * Enum | Value | Description
100404  * :-------------------------------|:------|:-------------------------------------------
100405  * ALT_EMAC_DMA_INT_EN_TJE_E_DISD | 0x0 | Transmit Jabber Timeout Interrupt Disabled
100406  * ALT_EMAC_DMA_INT_EN_TJE_E_END | 0x1 | Transmit Jabber Timeout Interrupt Enabled
100407  *
100408  * Field Access Macros:
100409  *
100410  */
100411 /*
100412  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
100413  *
100414  * Transmit Jabber Timeout Interrupt Disabled
100415  */
100416 #define ALT_EMAC_DMA_INT_EN_TJE_E_DISD 0x0
100417 /*
100418  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
100419  *
100420  * Transmit Jabber Timeout Interrupt Enabled
100421  */
100422 #define ALT_EMAC_DMA_INT_EN_TJE_E_END 0x1
100423 
100424 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
100425 #define ALT_EMAC_DMA_INT_EN_TJE_LSB 3
100426 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
100427 #define ALT_EMAC_DMA_INT_EN_TJE_MSB 3
100428 /* The width in bits of the ALT_EMAC_DMA_INT_EN_TJE register field. */
100429 #define ALT_EMAC_DMA_INT_EN_TJE_WIDTH 1
100430 /* The mask used to set the ALT_EMAC_DMA_INT_EN_TJE register field value. */
100431 #define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK 0x00000008
100432 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_TJE register field value. */
100433 #define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK 0xfffffff7
100434 /* The reset value of the ALT_EMAC_DMA_INT_EN_TJE register field. */
100435 #define ALT_EMAC_DMA_INT_EN_TJE_RESET 0x0
100436 /* Extracts the ALT_EMAC_DMA_INT_EN_TJE field value from a register. */
100437 #define ALT_EMAC_DMA_INT_EN_TJE_GET(value) (((value) & 0x00000008) >> 3)
100438 /* Produces a ALT_EMAC_DMA_INT_EN_TJE register field value suitable for setting the register. */
100439 #define ALT_EMAC_DMA_INT_EN_TJE_SET(value) (((value) << 3) & 0x00000008)
100440 
100441 /*
100442  * Field : Overflow Interrupt Enable - ove
100443  *
100444  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100445  * Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow
100446  * Interrupt is disabled.
100447  *
100448  * Field Enumeration Values:
100449  *
100450  * Enum | Value | Description
100451  * :-------------------------------|:------|:-------------------------------------
100452  * ALT_EMAC_DMA_INT_EN_OVE_E_DISD | 0x0 | Transmit Overflow Interrupt Disabled
100453  * ALT_EMAC_DMA_INT_EN_OVE_E_END | 0x1 | Transmit Overflow Interrupt Enabled
100454  *
100455  * Field Access Macros:
100456  *
100457  */
100458 /*
100459  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
100460  *
100461  * Transmit Overflow Interrupt Disabled
100462  */
100463 #define ALT_EMAC_DMA_INT_EN_OVE_E_DISD 0x0
100464 /*
100465  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
100466  *
100467  * Transmit Overflow Interrupt Enabled
100468  */
100469 #define ALT_EMAC_DMA_INT_EN_OVE_E_END 0x1
100470 
100471 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
100472 #define ALT_EMAC_DMA_INT_EN_OVE_LSB 4
100473 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
100474 #define ALT_EMAC_DMA_INT_EN_OVE_MSB 4
100475 /* The width in bits of the ALT_EMAC_DMA_INT_EN_OVE register field. */
100476 #define ALT_EMAC_DMA_INT_EN_OVE_WIDTH 1
100477 /* The mask used to set the ALT_EMAC_DMA_INT_EN_OVE register field value. */
100478 #define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK 0x00000010
100479 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_OVE register field value. */
100480 #define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK 0xffffffef
100481 /* The reset value of the ALT_EMAC_DMA_INT_EN_OVE register field. */
100482 #define ALT_EMAC_DMA_INT_EN_OVE_RESET 0x0
100483 /* Extracts the ALT_EMAC_DMA_INT_EN_OVE field value from a register. */
100484 #define ALT_EMAC_DMA_INT_EN_OVE_GET(value) (((value) & 0x00000010) >> 4)
100485 /* Produces a ALT_EMAC_DMA_INT_EN_OVE register field value suitable for setting the register. */
100486 #define ALT_EMAC_DMA_INT_EN_OVE_SET(value) (((value) << 4) & 0x00000010)
100487 
100488 /*
100489  * Field : Underflow Interrupt Enable - une
100490  *
100491  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100492  * Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow
100493  * Interrupt is disabled.
100494  *
100495  * Field Enumeration Values:
100496  *
100497  * Enum | Value | Description
100498  * :-------------------------------|:------|:-----------------------------
100499  * ALT_EMAC_DMA_INT_EN_UNE_E_DISD | 0x0 | Underflow Interrupt Disabled
100500  * ALT_EMAC_DMA_INT_EN_UNE_E_END | 0x1 | Underflow Interrupt Enabled
100501  *
100502  * Field Access Macros:
100503  *
100504  */
100505 /*
100506  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
100507  *
100508  * Underflow Interrupt Disabled
100509  */
100510 #define ALT_EMAC_DMA_INT_EN_UNE_E_DISD 0x0
100511 /*
100512  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
100513  *
100514  * Underflow Interrupt Enabled
100515  */
100516 #define ALT_EMAC_DMA_INT_EN_UNE_E_END 0x1
100517 
100518 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
100519 #define ALT_EMAC_DMA_INT_EN_UNE_LSB 5
100520 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
100521 #define ALT_EMAC_DMA_INT_EN_UNE_MSB 5
100522 /* The width in bits of the ALT_EMAC_DMA_INT_EN_UNE register field. */
100523 #define ALT_EMAC_DMA_INT_EN_UNE_WIDTH 1
100524 /* The mask used to set the ALT_EMAC_DMA_INT_EN_UNE register field value. */
100525 #define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK 0x00000020
100526 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_UNE register field value. */
100527 #define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK 0xffffffdf
100528 /* The reset value of the ALT_EMAC_DMA_INT_EN_UNE register field. */
100529 #define ALT_EMAC_DMA_INT_EN_UNE_RESET 0x0
100530 /* Extracts the ALT_EMAC_DMA_INT_EN_UNE field value from a register. */
100531 #define ALT_EMAC_DMA_INT_EN_UNE_GET(value) (((value) & 0x00000020) >> 5)
100532 /* Produces a ALT_EMAC_DMA_INT_EN_UNE register field value suitable for setting the register. */
100533 #define ALT_EMAC_DMA_INT_EN_UNE_SET(value) (((value) << 5) & 0x00000020)
100534 
100535 /*
100536  * Field : Receive Interrupt Enable - rie
100537  *
100538  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive
100539  * Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
100540  *
100541  * Field Enumeration Values:
100542  *
100543  * Enum | Value | Description
100544  * :-------------------------------|:------|:---------------------------
100545  * ALT_EMAC_DMA_INT_EN_RIE_E_DISD | 0x0 | Receive Interrupt Disabled
100546  * ALT_EMAC_DMA_INT_EN_RIE_E_END | 0x1 | Receive Interrupt Enabled
100547  *
100548  * Field Access Macros:
100549  *
100550  */
100551 /*
100552  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
100553  *
100554  * Receive Interrupt Disabled
100555  */
100556 #define ALT_EMAC_DMA_INT_EN_RIE_E_DISD 0x0
100557 /*
100558  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
100559  *
100560  * Receive Interrupt Enabled
100561  */
100562 #define ALT_EMAC_DMA_INT_EN_RIE_E_END 0x1
100563 
100564 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
100565 #define ALT_EMAC_DMA_INT_EN_RIE_LSB 6
100566 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
100567 #define ALT_EMAC_DMA_INT_EN_RIE_MSB 6
100568 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RIE register field. */
100569 #define ALT_EMAC_DMA_INT_EN_RIE_WIDTH 1
100570 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RIE register field value. */
100571 #define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK 0x00000040
100572 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RIE register field value. */
100573 #define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK 0xffffffbf
100574 /* The reset value of the ALT_EMAC_DMA_INT_EN_RIE register field. */
100575 #define ALT_EMAC_DMA_INT_EN_RIE_RESET 0x0
100576 /* Extracts the ALT_EMAC_DMA_INT_EN_RIE field value from a register. */
100577 #define ALT_EMAC_DMA_INT_EN_RIE_GET(value) (((value) & 0x00000040) >> 6)
100578 /* Produces a ALT_EMAC_DMA_INT_EN_RIE register field value suitable for setting the register. */
100579 #define ALT_EMAC_DMA_INT_EN_RIE_SET(value) (((value) << 6) & 0x00000040)
100580 
100581 /*
100582  * Field : Receive Buffer Unavailable Enable - rue
100583  *
100584  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100585  * Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the
100586  * Receive Buffer Unavailable Interrupt is disabled.
100587  *
100588  * Field Access Macros:
100589  *
100590  */
100591 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
100592 #define ALT_EMAC_DMA_INT_EN_RUE_LSB 7
100593 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
100594 #define ALT_EMAC_DMA_INT_EN_RUE_MSB 7
100595 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RUE register field. */
100596 #define ALT_EMAC_DMA_INT_EN_RUE_WIDTH 1
100597 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RUE register field value. */
100598 #define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK 0x00000080
100599 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RUE register field value. */
100600 #define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK 0xffffff7f
100601 /* The reset value of the ALT_EMAC_DMA_INT_EN_RUE register field. */
100602 #define ALT_EMAC_DMA_INT_EN_RUE_RESET 0x0
100603 /* Extracts the ALT_EMAC_DMA_INT_EN_RUE field value from a register. */
100604 #define ALT_EMAC_DMA_INT_EN_RUE_GET(value) (((value) & 0x00000080) >> 7)
100605 /* Produces a ALT_EMAC_DMA_INT_EN_RUE register field value suitable for setting the register. */
100606 #define ALT_EMAC_DMA_INT_EN_RUE_SET(value) (((value) << 7) & 0x00000080)
100607 
100608 /*
100609  * Field : Receive Stopped Enable - rse
100610  *
100611  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100612  * Receive Stopped Interrupt is enabled. When this bit is reset, the Receive
100613  * Stopped Interrupt is disabled.
100614  *
100615  * Field Enumeration Values:
100616  *
100617  * Enum | Value | Description
100618  * :-------------------------------|:------|:-----------------------------------
100619  * ALT_EMAC_DMA_INT_EN_RSE_E_DISD | 0x0 | Receive Stopped Interrupt Disabled
100620  * ALT_EMAC_DMA_INT_EN_RSE_E_END | 0x1 | Receive Stopped Interrupt Enabled
100621  *
100622  * Field Access Macros:
100623  *
100624  */
100625 /*
100626  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
100627  *
100628  * Receive Stopped Interrupt Disabled
100629  */
100630 #define ALT_EMAC_DMA_INT_EN_RSE_E_DISD 0x0
100631 /*
100632  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
100633  *
100634  * Receive Stopped Interrupt Enabled
100635  */
100636 #define ALT_EMAC_DMA_INT_EN_RSE_E_END 0x1
100637 
100638 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
100639 #define ALT_EMAC_DMA_INT_EN_RSE_LSB 8
100640 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
100641 #define ALT_EMAC_DMA_INT_EN_RSE_MSB 8
100642 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RSE register field. */
100643 #define ALT_EMAC_DMA_INT_EN_RSE_WIDTH 1
100644 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RSE register field value. */
100645 #define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK 0x00000100
100646 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSE register field value. */
100647 #define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK 0xfffffeff
100648 /* The reset value of the ALT_EMAC_DMA_INT_EN_RSE register field. */
100649 #define ALT_EMAC_DMA_INT_EN_RSE_RESET 0x0
100650 /* Extracts the ALT_EMAC_DMA_INT_EN_RSE field value from a register. */
100651 #define ALT_EMAC_DMA_INT_EN_RSE_GET(value) (((value) & 0x00000100) >> 8)
100652 /* Produces a ALT_EMAC_DMA_INT_EN_RSE register field value suitable for setting the register. */
100653 #define ALT_EMAC_DMA_INT_EN_RSE_SET(value) (((value) << 8) & 0x00000100)
100654 
100655 /*
100656  * Field : Receive Watchdog Timeout Enable - rwe
100657  *
100658  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
100659  * Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the
100660  * Receive Watchdog Timeout Interrupt is disabled.
100661  *
100662  * Field Enumeration Values:
100663  *
100664  * Enum | Value | Description
100665  * :-------------------------------|:------|:--------------------------------------------
100666  * ALT_EMAC_DMA_INT_EN_RWE_E_DISD | 0x0 | Receive Watchdog Timeout Interrupt Disabled
100667  * ALT_EMAC_DMA_INT_EN_RWE_E_END | 0x1 | Receive Watchdog Timeout Interrupt Enabled
100668  *
100669  * Field Access Macros:
100670  *
100671  */
100672 /*
100673  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
100674  *
100675  * Receive Watchdog Timeout Interrupt Disabled
100676  */
100677 #define ALT_EMAC_DMA_INT_EN_RWE_E_DISD 0x0
100678 /*
100679  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
100680  *
100681  * Receive Watchdog Timeout Interrupt Enabled
100682  */
100683 #define ALT_EMAC_DMA_INT_EN_RWE_E_END 0x1
100684 
100685 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
100686 #define ALT_EMAC_DMA_INT_EN_RWE_LSB 9
100687 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
100688 #define ALT_EMAC_DMA_INT_EN_RWE_MSB 9
100689 /* The width in bits of the ALT_EMAC_DMA_INT_EN_RWE register field. */
100690 #define ALT_EMAC_DMA_INT_EN_RWE_WIDTH 1
100691 /* The mask used to set the ALT_EMAC_DMA_INT_EN_RWE register field value. */
100692 #define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK 0x00000200
100693 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_RWE register field value. */
100694 #define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK 0xfffffdff
100695 /* The reset value of the ALT_EMAC_DMA_INT_EN_RWE register field. */
100696 #define ALT_EMAC_DMA_INT_EN_RWE_RESET 0x0
100697 /* Extracts the ALT_EMAC_DMA_INT_EN_RWE field value from a register. */
100698 #define ALT_EMAC_DMA_INT_EN_RWE_GET(value) (((value) & 0x00000200) >> 9)
100699 /* Produces a ALT_EMAC_DMA_INT_EN_RWE register field value suitable for setting the register. */
100700 #define ALT_EMAC_DMA_INT_EN_RWE_SET(value) (((value) << 9) & 0x00000200)
100701 
100702 /*
100703  * Field : Early Transmit Interrupt Enable - ete
100704  *
100705  * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the
100706  * Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit
100707  * Interrupt is disabled.
100708  *
100709  * Field Enumeration Values:
100710  *
100711  * Enum | Value | Description
100712  * :-------------------------------|:------|:----------------------------------
100713  * ALT_EMAC_DMA_INT_EN_ETE_E_DISD | 0x0 | Early Transmit Interrupt Disabled
100714  * ALT_EMAC_DMA_INT_EN_ETE_E_END | 0x1 | Early Transmit Interrupt Enabled
100715  *
100716  * Field Access Macros:
100717  *
100718  */
100719 /*
100720  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
100721  *
100722  * Early Transmit Interrupt Disabled
100723  */
100724 #define ALT_EMAC_DMA_INT_EN_ETE_E_DISD 0x0
100725 /*
100726  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
100727  *
100728  * Early Transmit Interrupt Enabled
100729  */
100730 #define ALT_EMAC_DMA_INT_EN_ETE_E_END 0x1
100731 
100732 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
100733 #define ALT_EMAC_DMA_INT_EN_ETE_LSB 10
100734 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
100735 #define ALT_EMAC_DMA_INT_EN_ETE_MSB 10
100736 /* The width in bits of the ALT_EMAC_DMA_INT_EN_ETE register field. */
100737 #define ALT_EMAC_DMA_INT_EN_ETE_WIDTH 1
100738 /* The mask used to set the ALT_EMAC_DMA_INT_EN_ETE register field value. */
100739 #define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK 0x00000400
100740 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_ETE register field value. */
100741 #define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK 0xfffffbff
100742 /* The reset value of the ALT_EMAC_DMA_INT_EN_ETE register field. */
100743 #define ALT_EMAC_DMA_INT_EN_ETE_RESET 0x0
100744 /* Extracts the ALT_EMAC_DMA_INT_EN_ETE field value from a register. */
100745 #define ALT_EMAC_DMA_INT_EN_ETE_GET(value) (((value) & 0x00000400) >> 10)
100746 /* Produces a ALT_EMAC_DMA_INT_EN_ETE register field value suitable for setting the register. */
100747 #define ALT_EMAC_DMA_INT_EN_ETE_SET(value) (((value) << 10) & 0x00000400)
100748 
100749 /*
100750  * Field : Fatal Bus Error Enable - fbe
100751  *
100752  * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal
100753  * Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error
100754  * Enable Interrupt is disabled.
100755  *
100756  * Field Enumeration Values:
100757  *
100758  * Enum | Value | Description
100759  * :-------------------------------|:------|:-----------------------------------
100760  * ALT_EMAC_DMA_INT_EN_FBE_E_DISD | 0x0 | Fatal Bus Error Interrupt Disabled
100761  * ALT_EMAC_DMA_INT_EN_FBE_E_END | 0x1 | Fatal Bus Error Interrupt Enabled
100762  *
100763  * Field Access Macros:
100764  *
100765  */
100766 /*
100767  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
100768  *
100769  * Fatal Bus Error Interrupt Disabled
100770  */
100771 #define ALT_EMAC_DMA_INT_EN_FBE_E_DISD 0x0
100772 /*
100773  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
100774  *
100775  * Fatal Bus Error Interrupt Enabled
100776  */
100777 #define ALT_EMAC_DMA_INT_EN_FBE_E_END 0x1
100778 
100779 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
100780 #define ALT_EMAC_DMA_INT_EN_FBE_LSB 13
100781 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
100782 #define ALT_EMAC_DMA_INT_EN_FBE_MSB 13
100783 /* The width in bits of the ALT_EMAC_DMA_INT_EN_FBE register field. */
100784 #define ALT_EMAC_DMA_INT_EN_FBE_WIDTH 1
100785 /* The mask used to set the ALT_EMAC_DMA_INT_EN_FBE register field value. */
100786 #define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK 0x00002000
100787 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_FBE register field value. */
100788 #define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK 0xffffdfff
100789 /* The reset value of the ALT_EMAC_DMA_INT_EN_FBE register field. */
100790 #define ALT_EMAC_DMA_INT_EN_FBE_RESET 0x0
100791 /* Extracts the ALT_EMAC_DMA_INT_EN_FBE field value from a register. */
100792 #define ALT_EMAC_DMA_INT_EN_FBE_GET(value) (((value) & 0x00002000) >> 13)
100793 /* Produces a ALT_EMAC_DMA_INT_EN_FBE register field value suitable for setting the register. */
100794 #define ALT_EMAC_DMA_INT_EN_FBE_SET(value) (((value) << 13) & 0x00002000)
100795 
100796 /*
100797  * Field : Early Receive Interrupt Enable - ere
100798  *
100799  * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early
100800  * Receive Interrupt is enabled. When this bit is reset, the Early Receive
100801  * Interrupt is disabled.
100802  *
100803  * Field Enumeration Values:
100804  *
100805  * Enum | Value | Description
100806  * :-------------------------------|:------|:---------------------------------
100807  * ALT_EMAC_DMA_INT_EN_ERE_E_DISD | 0x0 | Early Receive Interrupt Disabled
100808  * ALT_EMAC_DMA_INT_EN_ERE_E_END | 0x1 | Early Receive Interrupt Enabled
100809  *
100810  * Field Access Macros:
100811  *
100812  */
100813 /*
100814  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
100815  *
100816  * Early Receive Interrupt Disabled
100817  */
100818 #define ALT_EMAC_DMA_INT_EN_ERE_E_DISD 0x0
100819 /*
100820  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
100821  *
100822  * Early Receive Interrupt Enabled
100823  */
100824 #define ALT_EMAC_DMA_INT_EN_ERE_E_END 0x1
100825 
100826 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
100827 #define ALT_EMAC_DMA_INT_EN_ERE_LSB 14
100828 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
100829 #define ALT_EMAC_DMA_INT_EN_ERE_MSB 14
100830 /* The width in bits of the ALT_EMAC_DMA_INT_EN_ERE register field. */
100831 #define ALT_EMAC_DMA_INT_EN_ERE_WIDTH 1
100832 /* The mask used to set the ALT_EMAC_DMA_INT_EN_ERE register field value. */
100833 #define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK 0x00004000
100834 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_ERE register field value. */
100835 #define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK 0xffffbfff
100836 /* The reset value of the ALT_EMAC_DMA_INT_EN_ERE register field. */
100837 #define ALT_EMAC_DMA_INT_EN_ERE_RESET 0x0
100838 /* Extracts the ALT_EMAC_DMA_INT_EN_ERE field value from a register. */
100839 #define ALT_EMAC_DMA_INT_EN_ERE_GET(value) (((value) & 0x00004000) >> 14)
100840 /* Produces a ALT_EMAC_DMA_INT_EN_ERE register field value suitable for setting the register. */
100841 #define ALT_EMAC_DMA_INT_EN_ERE_SET(value) (((value) << 14) & 0x00004000)
100842 
100843 /*
100844  * Field : Abnormal Interrupt Summary Enable - aie
100845  *
100846  * When this bit is set, abnormal interrupt summary is enabled. When this bit is
100847  * reset, the abnormal interrupt summary is disabled. This bit enables the
100848  * following interrupts in Register 5 (Status Register):
100849  *
100850  * * Register 5[1]: Transmit Process Stopped
100851  *
100852  * * Register 5[3]: Transmit Jabber Timeout
100853  *
100854  * * Register 5[4]: Receive Overflow
100855  *
100856  * * Register 5[5]: Transmit Underflow
100857  *
100858  * * Register 5[7]: Receive Buffer Unavailable
100859  *
100860  * * Register 5[8]: Receive Process Stopped
100861  *
100862  * * Register 5[9]: Receive Watchdog Timeout
100863  *
100864  * * Register 5[10]: Early Transmit Interrupt
100865  *
100866  * * Register 5[13]: Fatal Bus Error
100867  *
100868  * Field Enumeration Values:
100869  *
100870  * Enum | Value | Description
100871  * :-------------------------------|:------|:----------------------------------------------
100872  * ALT_EMAC_DMA_INT_EN_AIE_E_DISD | 0x0 | Abnormal Interrupt Summary Interrupt Disabled
100873  * ALT_EMAC_DMA_INT_EN_AIE_E_END | 0x1 | Abnormal Interrupt Summary Interrupt Enabled
100874  *
100875  * Field Access Macros:
100876  *
100877  */
100878 /*
100879  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
100880  *
100881  * Abnormal Interrupt Summary Interrupt Disabled
100882  */
100883 #define ALT_EMAC_DMA_INT_EN_AIE_E_DISD 0x0
100884 /*
100885  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
100886  *
100887  * Abnormal Interrupt Summary Interrupt Enabled
100888  */
100889 #define ALT_EMAC_DMA_INT_EN_AIE_E_END 0x1
100890 
100891 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
100892 #define ALT_EMAC_DMA_INT_EN_AIE_LSB 15
100893 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
100894 #define ALT_EMAC_DMA_INT_EN_AIE_MSB 15
100895 /* The width in bits of the ALT_EMAC_DMA_INT_EN_AIE register field. */
100896 #define ALT_EMAC_DMA_INT_EN_AIE_WIDTH 1
100897 /* The mask used to set the ALT_EMAC_DMA_INT_EN_AIE register field value. */
100898 #define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK 0x00008000
100899 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_AIE register field value. */
100900 #define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK 0xffff7fff
100901 /* The reset value of the ALT_EMAC_DMA_INT_EN_AIE register field. */
100902 #define ALT_EMAC_DMA_INT_EN_AIE_RESET 0x0
100903 /* Extracts the ALT_EMAC_DMA_INT_EN_AIE field value from a register. */
100904 #define ALT_EMAC_DMA_INT_EN_AIE_GET(value) (((value) & 0x00008000) >> 15)
100905 /* Produces a ALT_EMAC_DMA_INT_EN_AIE register field value suitable for setting the register. */
100906 #define ALT_EMAC_DMA_INT_EN_AIE_SET(value) (((value) << 15) & 0x00008000)
100907 
100908 /*
100909  * Field : Normal Interrupt Summary Enable - nie
100910  *
100911  * When this bit is set, normal interrupt summary is enabled. When this bit is
100912  * reset, normal interrupt summary is disabled. This bit enables the following
100913  * interrupts in Register 5 (Status Register):
100914  *
100915  * * Register 5[0]: Transmit Interrupt
100916  *
100917  * * Register 5[2]: Transmit Buffer Unavailable
100918  *
100919  * * Register 5[6]: Receive Interrupt
100920  *
100921  * * Register 5[14]: Early Receive Interrupt
100922  *
100923  * Field Enumeration Values:
100924  *
100925  * Enum | Value | Description
100926  * :-------------------------------|:------|:----------------------------------
100927  * ALT_EMAC_DMA_INT_EN_NIE_E_DISD | 0x0 | Normal Interrupt Summary Disabled
100928  * ALT_EMAC_DMA_INT_EN_NIE_E_END | 0x1 | Normal Interrupt Summary Enabled
100929  *
100930  * Field Access Macros:
100931  *
100932  */
100933 /*
100934  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
100935  *
100936  * Normal Interrupt Summary Disabled
100937  */
100938 #define ALT_EMAC_DMA_INT_EN_NIE_E_DISD 0x0
100939 /*
100940  * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
100941  *
100942  * Normal Interrupt Summary Enabled
100943  */
100944 #define ALT_EMAC_DMA_INT_EN_NIE_E_END 0x1
100945 
100946 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
100947 #define ALT_EMAC_DMA_INT_EN_NIE_LSB 16
100948 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
100949 #define ALT_EMAC_DMA_INT_EN_NIE_MSB 16
100950 /* The width in bits of the ALT_EMAC_DMA_INT_EN_NIE register field. */
100951 #define ALT_EMAC_DMA_INT_EN_NIE_WIDTH 1
100952 /* The mask used to set the ALT_EMAC_DMA_INT_EN_NIE register field value. */
100953 #define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK 0x00010000
100954 /* The mask used to clear the ALT_EMAC_DMA_INT_EN_NIE register field value. */
100955 #define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK 0xfffeffff
100956 /* The reset value of the ALT_EMAC_DMA_INT_EN_NIE register field. */
100957 #define ALT_EMAC_DMA_INT_EN_NIE_RESET 0x0
100958 /* Extracts the ALT_EMAC_DMA_INT_EN_NIE field value from a register. */
100959 #define ALT_EMAC_DMA_INT_EN_NIE_GET(value) (((value) & 0x00010000) >> 16)
100960 /* Produces a ALT_EMAC_DMA_INT_EN_NIE register field value suitable for setting the register. */
100961 #define ALT_EMAC_DMA_INT_EN_NIE_SET(value) (((value) << 16) & 0x00010000)
100962 
100963 #ifndef __ASSEMBLY__
100964 /*
100965  * WARNING: The C register and register group struct declarations are provided for
100966  * convenience and illustrative purposes. They should, however, be used with
100967  * caution as the C language standard provides no guarantees about the alignment or
100968  * atomicity of device memory accesses. The recommended practice for writing
100969  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
100970  * alt_write_word() functions.
100971  *
100972  * The struct declaration for register ALT_EMAC_DMA_INT_EN.
100973  */
100974 struct ALT_EMAC_DMA_INT_EN_s
100975 {
100976  uint32_t tie : 1; /* Transmit Interrupt Enable */
100977  uint32_t tse : 1; /* Transmit Stopped Enable */
100978  uint32_t tue : 1; /* Transmit Buffer Unvailable Enable */
100979  uint32_t tje : 1; /* Transmit Jabber Timeout Enable */
100980  uint32_t ove : 1; /* Overflow Interrupt Enable */
100981  uint32_t une : 1; /* Underflow Interrupt Enable */
100982  uint32_t rie : 1; /* Receive Interrupt Enable */
100983  uint32_t rue : 1; /* Receive Buffer Unavailable Enable */
100984  uint32_t rse : 1; /* Receive Stopped Enable */
100985  uint32_t rwe : 1; /* Receive Watchdog Timeout Enable */
100986  uint32_t ete : 1; /* Early Transmit Interrupt Enable */
100987  uint32_t : 2; /* *UNDEFINED* */
100988  uint32_t fbe : 1; /* Fatal Bus Error Enable */
100989  uint32_t ere : 1; /* Early Receive Interrupt Enable */
100990  uint32_t aie : 1; /* Abnormal Interrupt Summary Enable */
100991  uint32_t nie : 1; /* Normal Interrupt Summary Enable */
100992  uint32_t : 15; /* *UNDEFINED* */
100993 };
100994 
100995 /* The typedef declaration for register ALT_EMAC_DMA_INT_EN. */
100996 typedef volatile struct ALT_EMAC_DMA_INT_EN_s ALT_EMAC_DMA_INT_EN_t;
100997 #endif /* __ASSEMBLY__ */
100998 
100999 /* The byte offset of the ALT_EMAC_DMA_INT_EN register from the beginning of the component. */
101000 #define ALT_EMAC_DMA_INT_EN_OFST 0x1c
101001 /* The address of the ALT_EMAC_DMA_INT_EN register. */
101002 #define ALT_EMAC_DMA_INT_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST))
101003 
101004 /*
101005  * Register : Register 8 (Missed Frame and Buffer Overflow Counter Register) - Missed_Frame_And_Buffer_Overflow_Counter
101006  *
101007  * The DMA maintains two counters to track the number of frames missed during
101008  * reception. This register reports the current value of the counter. The counter
101009  * is used for diagnostic purposes. Bits[15:0] indicate missed frames because of
101010  * the host buffer being unavailable. Bits[27:17] indicate missed frames because of
101011  * buffer overflow conditions (MTL and MAC) and runt frames (good frames of less
101012  * than 64 bytes) dropped by the MTL.
101013  *
101014  * Register Layout
101015  *
101016  * Bits | Access | Reset | Description
101017  * :--------|:-------|:------|:-----------------------------------------
101018  * [15:0] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT
101019  * [16] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF
101020  * [27:17] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT
101021  * [28] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF
101022  * [31:29] | ??? | 0x0 | *UNDEFINED*
101023  *
101024  */
101025 /*
101026  * Field : misfrmcnt
101027  *
101028  * This field indicates the number of frames missed by the controller because of
101029  * the Host Receive Buffer being unavailable. This counter is incremented each time
101030  * the DMA discards an incoming frame. The counter is cleared when this register is
101031  * read with mci_be_i[0] at 1'b1.
101032  *
101033  * Field Access Macros:
101034  *
101035  */
101036 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
101037 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB 0
101038 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
101039 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB 15
101040 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
101041 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH 16
101042 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
101043 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK 0x0000ffff
101044 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
101045 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK 0xffff0000
101046 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
101047 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET 0x0
101048 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT field value from a register. */
101049 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0)
101050 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value suitable for setting the register. */
101051 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff)
101052 
101053 /*
101054  * Field : miscntovf
101055  *
101056  * Overflow bit for Missed Frame Counter
101057  *
101058  * Field Access Macros:
101059  *
101060  */
101061 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
101062 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB 16
101063 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
101064 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB 16
101065 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
101066 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH 1
101067 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
101068 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK 0x00010000
101069 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
101070 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK 0xfffeffff
101071 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
101072 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET 0x0
101073 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF field value from a register. */
101074 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16)
101075 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value suitable for setting the register. */
101076 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000)
101077 
101078 /*
101079  * Field : ovffrmcnt
101080  *
101081  * This field indicates the number of frames missed by the application. This
101082  * counter is incremented each time the MTL asserts the sideband signal
101083  * mtl_rxoverflow_o. The counter is cleared when this register is read with
101084  * mci_be_i[2] at 1'b1.
101085  *
101086  * Field Access Macros:
101087  *
101088  */
101089 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
101090 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB 17
101091 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
101092 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB 27
101093 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
101094 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH 11
101095 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
101096 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK 0x0ffe0000
101097 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
101098 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK 0xf001ffff
101099 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
101100 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET 0x0
101101 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT field value from a register. */
101102 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17)
101103 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value suitable for setting the register. */
101104 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000)
101105 
101106 /*
101107  * Field : ovfcntovf
101108  *
101109  * Overflow bit for FIFO Overflow Counter
101110  *
101111  * Field Access Macros:
101112  *
101113  */
101114 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
101115 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB 28
101116 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
101117 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB 28
101118 /* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
101119 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH 1
101120 /* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
101121 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK 0x10000000
101122 /* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
101123 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK 0xefffffff
101124 /* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
101125 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET 0x0
101126 /* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF field value from a register. */
101127 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28)
101128 /* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value suitable for setting the register. */
101129 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000)
101130 
101131 #ifndef __ASSEMBLY__
101132 /*
101133  * WARNING: The C register and register group struct declarations are provided for
101134  * convenience and illustrative purposes. They should, however, be used with
101135  * caution as the C language standard provides no guarantees about the alignment or
101136  * atomicity of device memory accesses. The recommended practice for writing
101137  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101138  * alt_write_word() functions.
101139  *
101140  * The struct declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR.
101141  */
101142 struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s
101143 {
101144  const uint32_t misfrmcnt : 16; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT */
101145  const uint32_t miscntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF */
101146  const uint32_t ovffrmcnt : 11; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT */
101147  const uint32_t ovfcntovf : 1; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF */
101148  uint32_t : 3; /* *UNDEFINED* */
101149 };
101150 
101151 /* The typedef declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR. */
101152 typedef volatile struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t;
101153 #endif /* __ASSEMBLY__ */
101154 
101155 /* The byte offset of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register from the beginning of the component. */
101156 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST 0x20
101157 /* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register. */
101158 #define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST))
101159 
101160 /*
101161  * Register : Register 9 (Receive Interrupt Watchdog Timer Register) - Receive_Interrupt_Watchdog_Timer
101162  *
101163  * This register, when written with non-zero value, enables the watchdog timer for
101164  * the Receive Interrupt (Bit 6) of Register 5 (Status Register)
101165  *
101166  * Register Layout
101167  *
101168  * Bits | Access | Reset | Description
101169  * :-------|:-------|:------|:------------------------
101170  * [7:0] | RW | 0x0 | RI Watchdog Timer Count
101171  * [31:8] | ??? | 0x0 | *UNDEFINED*
101172  *
101173  */
101174 /*
101175  * Field : RI Watchdog Timer Count - riwt
101176  *
101177  * This bit indicates the number of system clock cycles multiplied by 256 for which
101178  * the watchdog timer is set. The watchdog timer gets triggered with the programmed
101179  * value after the Rx DMA completes the transfer of a frame for which the RI status
101180  * bit is not set because of the setting in the corresponding descriptor RDES1[31].
101181  * When the watchdog timer runs out, the RI bit is set and the timer is stopped.
101182  * The watchdog timer is reset when the RI bit is set high because of automatic
101183  * setting of RI as per RDES1[31] of any received frame.
101184  *
101185  * Field Access Macros:
101186  *
101187  */
101188 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
101189 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB 0
101190 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
101191 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB 7
101192 /* The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
101193 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH 8
101194 /* The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
101195 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK 0x000000ff
101196 /* The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
101197 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK 0xffffff00
101198 /* The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
101199 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET 0x0
101200 /* Extracts the ALT_EMAC_DMA_RX_INT_WDT_RIWT field value from a register. */
101201 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET(value) (((value) & 0x000000ff) >> 0)
101202 /* Produces a ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value suitable for setting the register. */
101203 #define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET(value) (((value) << 0) & 0x000000ff)
101204 
101205 #ifndef __ASSEMBLY__
101206 /*
101207  * WARNING: The C register and register group struct declarations are provided for
101208  * convenience and illustrative purposes. They should, however, be used with
101209  * caution as the C language standard provides no guarantees about the alignment or
101210  * atomicity of device memory accesses. The recommended practice for writing
101211  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101212  * alt_write_word() functions.
101213  *
101214  * The struct declaration for register ALT_EMAC_DMA_RX_INT_WDT.
101215  */
101216 struct ALT_EMAC_DMA_RX_INT_WDT_s
101217 {
101218  uint32_t riwt : 8; /* RI Watchdog Timer Count */
101219  uint32_t : 24; /* *UNDEFINED* */
101220 };
101221 
101222 /* The typedef declaration for register ALT_EMAC_DMA_RX_INT_WDT. */
101223 typedef volatile struct ALT_EMAC_DMA_RX_INT_WDT_s ALT_EMAC_DMA_RX_INT_WDT_t;
101224 #endif /* __ASSEMBLY__ */
101225 
101226 /* The byte offset of the ALT_EMAC_DMA_RX_INT_WDT register from the beginning of the component. */
101227 #define ALT_EMAC_DMA_RX_INT_WDT_OFST 0x24
101228 /* The address of the ALT_EMAC_DMA_RX_INT_WDT register. */
101229 #define ALT_EMAC_DMA_RX_INT_WDT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST))
101230 
101231 /*
101232  * Register : Register 10 (AXI Bus Mode Register) - AXI_Bus_Mode
101233  *
101234  * The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly
101235  * used to control the burst splitting and the number of outstanding requests.
101236  *
101237  * Register Layout
101238  *
101239  * Bits | Access | Reset | Description
101240  * :--------|:-------|:------|:-------------------------------------------
101241  * [0] | R | 0x1 | AXI Undefined Burst Length
101242  * [1] | RW | 0x0 | AXI Burst Length 4
101243  * [2] | RW | 0x0 | AXI Burst Length 8
101244  * [3] | RW | 0x0 | AXI Burst Length 16
101245  * [11:4] | ??? | 0x0 | *UNDEFINED*
101246  * [12] | R | 0x0 | Address-Aligned Beats
101247  * [13] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
101248  * [15:14] | ??? | 0x0 | *UNDEFINED*
101249  * [19:16] | RW | 0x1 | AXI Maximum Read OutStanding Request Limit
101250  * [23:20] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT
101251  * [29:24] | ??? | 0x0 | *UNDEFINED*
101252  * [30] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
101253  * [31] | RW | 0x0 | Enable Low Power Interface (LPI)
101254  *
101255  */
101256 /*
101257  * Field : AXI Undefined Burst Length - undefined
101258  *
101259  * This bit is read-only bit and indicates the complement (invert) value of Bit 16
101260  * (FB) in Register 0 (Bus Mode Register[16]).
101261  *
101262  * * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length
101263  * equal to or below the maximum allowed burst length programmed in Bits[7:1].
101264  *
101265  * * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst
101266  * lengths as indicated by BLEN16, BLEN8, or BLEN4, or a burst length of 1.
101267  *
101268  * Field Enumeration Values:
101269  *
101270  * Enum | Value | Description
101271  * :------------------------------------------|:------|:----------------------------
101272  * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD | 0x0 | Fixed Burst Lengths 4 to 32
101273  * ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END | 0x1 | Any Burst Length up to max
101274  *
101275  * Field Access Macros:
101276  *
101277  */
101278 /*
101279  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
101280  *
101281  * Fixed Burst Lengths 4 to 32
101282  */
101283 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD 0x0
101284 /*
101285  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
101286  *
101287  * Any Burst Length up to max
101288  */
101289 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END 0x1
101290 
101291 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
101292 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB 0
101293 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
101294 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB 0
101295 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
101296 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH 1
101297 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
101298 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK 0x00000001
101299 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
101300 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK 0xfffffffe
101301 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
101302 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET 0x1
101303 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED field value from a register. */
101304 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET(value) (((value) & 0x00000001) >> 0)
101305 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value suitable for setting the register. */
101306 #define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET(value) (((value) << 0) & 0x00000001)
101307 
101308 /*
101309  * Field : AXI Burst Length 4 - blen4
101310  *
101311  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4
101312  * on the AXI Master interface.
101313  *
101314  * Setting this bit has no effect when UNDEFINED is set to 1.
101315  *
101316  * Field Enumeration Values:
101317  *
101318  * Enum | Value | Description
101319  * :--------------------------------------|:------|:-------------------------
101320  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD | 0x0 | AXI No Fixed Busrts
101321  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END | 0x1 | AXI Fixed Burst BLEN = 4
101322  *
101323  * Field Access Macros:
101324  *
101325  */
101326 /*
101327  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
101328  *
101329  * AXI No Fixed Busrts
101330  */
101331 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD 0x0
101332 /*
101333  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
101334  *
101335  * AXI Fixed Burst BLEN = 4
101336  */
101337 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END 0x1
101338 
101339 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
101340 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB 1
101341 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
101342 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB 1
101343 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
101344 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH 1
101345 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
101346 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK 0x00000002
101347 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
101348 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK 0xfffffffd
101349 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
101350 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET 0x0
101351 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 field value from a register. */
101352 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET(value) (((value) & 0x00000002) >> 1)
101353 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value suitable for setting the register. */
101354 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET(value) (((value) << 1) & 0x00000002)
101355 
101356 /*
101357  * Field : AXI Burst Length 8 - blen8
101358  *
101359  * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8
101360  * on the AXI Master interface.
101361  *
101362  * Setting this bit has no effect when UNDEFINED is set to 1.
101363  *
101364  * Field Enumeration Values:
101365  *
101366  * Enum | Value | Description
101367  * :--------------------------------------|:------|:-------------------------
101368  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD | 0x0 | AXI No Fixed Busrts
101369  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END | 0x1 | AXI Fixed Burst BLEN = 8
101370  *
101371  * Field Access Macros:
101372  *
101373  */
101374 /*
101375  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
101376  *
101377  * AXI No Fixed Busrts
101378  */
101379 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD 0x0
101380 /*
101381  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
101382  *
101383  * AXI Fixed Burst BLEN = 8
101384  */
101385 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END 0x1
101386 
101387 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
101388 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB 2
101389 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
101390 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB 2
101391 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
101392 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH 1
101393 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
101394 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK 0x00000004
101395 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
101396 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK 0xfffffffb
101397 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
101398 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET 0x0
101399 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 field value from a register. */
101400 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET(value) (((value) & 0x00000004) >> 2)
101401 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value suitable for setting the register. */
101402 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET(value) (((value) << 2) & 0x00000004)
101403 
101404 /*
101405  * Field : AXI Burst Length 16 - blen16
101406  *
101407  * When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to
101408  * select a burst length of 16 on the AXI Master interface.
101409  *
101410  * Field Enumeration Values:
101411  *
101412  * Enum | Value | Description
101413  * :---------------------------------------|:------|:--------------------------
101414  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD | 0x0 | AXI No Fixed Busrts
101415  * ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END | 0x1 | AXI Fixed Burst BLEN = 16
101416  *
101417  * Field Access Macros:
101418  *
101419  */
101420 /*
101421  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
101422  *
101423  * AXI No Fixed Busrts
101424  */
101425 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD 0x0
101426 /*
101427  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
101428  *
101429  * AXI Fixed Burst BLEN = 16
101430  */
101431 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END 0x1
101432 
101433 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
101434 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB 3
101435 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
101436 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB 3
101437 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
101438 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH 1
101439 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
101440 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK 0x00000008
101441 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
101442 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK 0xfffffff7
101443 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
101444 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET 0x0
101445 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 field value from a register. */
101446 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET(value) (((value) & 0x00000008) >> 3)
101447 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value suitable for setting the register. */
101448 #define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET(value) (((value) << 3) & 0x00000008)
101449 
101450 /*
101451  * Field : Address-Aligned Beats - axi_aal
101452  *
101453  * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode
101454  * Register).
101455  *
101456  * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers
101457  * on both read and write channels.
101458  *
101459  * Field Enumeration Values:
101460  *
101461  * Enum | Value | Description
101462  * :----------------------------------------|:------|:----------------------------
101463  * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD | 0x0 | No Address-Alignment Bursts
101464  * ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END | 0x1 | Address-Alignmnet Bursts
101465  *
101466  * Field Access Macros:
101467  *
101468  */
101469 /*
101470  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
101471  *
101472  * No Address-Alignment Bursts
101473  */
101474 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0
101475 /*
101476  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
101477  *
101478  * Address-Alignmnet Bursts
101479  */
101480 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END 0x1
101481 
101482 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
101483 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB 12
101484 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
101485 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB 12
101486 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
101487 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH 1
101488 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
101489 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK 0x00001000
101490 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
101491 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK 0xffffefff
101492 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
101493 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET 0x0
101494 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL field value from a register. */
101495 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12)
101496 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value suitable for setting the register. */
101497 #define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET(value) (((value) << 12) & 0x00001000)
101498 
101499 /*
101500  * Field : onekbbe
101501  *
101502  * 1 KB Boundary Crossing Enable for the GMAC-AXI Master
101503  *
101504  * When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB
101505  * boundary. When reset, the GMAC-AXI Master performs burst transfers that do not
101506  * cross 4 KB boundary.
101507  *
101508  * Field Enumeration Values:
101509  *
101510  * Enum | Value | Description
101511  * :---------------------------------------------------|:------|:------------
101512  * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY | 0x0 | 4K boundary
101513  * ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY | 0x1 | 1K boundary
101514  *
101515  * Field Access Macros:
101516  *
101517  */
101518 /*
101519  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
101520  *
101521  * 4K boundary
101522  */
101523 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY 0x0
101524 /*
101525  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
101526  *
101527  * 1K boundary
101528  */
101529 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY 0x1
101530 
101531 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
101532 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB 13
101533 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
101534 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB 13
101535 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
101536 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH 1
101537 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
101538 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK 0x00002000
101539 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
101540 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK 0xffffdfff
101541 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
101542 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET 0x0
101543 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE field value from a register. */
101544 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13)
101545 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value suitable for setting the register. */
101546 #define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET(value) (((value) << 13) & 0x00002000)
101547 
101548 /*
101549  * Field : AXI Maximum Read OutStanding Request Limit - rd_osr_lmt
101550  *
101551  * This value limits the maximum outstanding request on the AXI read interface.
101552  *
101553  * Maximum outstanding requests = RD_OSR_LMT+1
101554  *
101555  * Field Access Macros:
101556  *
101557  */
101558 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
101559 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB 16
101560 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
101561 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB 19
101562 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
101563 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH 4
101564 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
101565 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK 0x000f0000
101566 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
101567 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK 0xfff0ffff
101568 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
101569 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET 0x1
101570 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT field value from a register. */
101571 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET(value) (((value) & 0x000f0000) >> 16)
101572 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value suitable for setting the register. */
101573 #define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET(value) (((value) << 16) & 0x000f0000)
101574 
101575 /*
101576  * Field : wr_osr_lmt
101577  *
101578  * AXI Maximum Write OutStanding Request Limit
101579  *
101580  * Field Access Macros:
101581  *
101582  */
101583 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
101584 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB 20
101585 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
101586 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB 23
101587 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
101588 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH 4
101589 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
101590 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK 0x00f00000
101591 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
101592 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK 0xff0fffff
101593 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
101594 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET 0x1
101595 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT field value from a register. */
101596 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET(value) (((value) & 0x00f00000) >> 20)
101597 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value suitable for setting the register. */
101598 #define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00f00000)
101599 
101600 /*
101601  * Field : lpi_xit_frm
101602  *
101603  * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only
101604  * when the Magic Packet or Remote Wake Up Packet is received.
101605  *
101606  * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any
101607  * frame is received.
101608  *
101609  * Field Enumeration Values:
101610  *
101611  * Enum | Value | Description
101612  * :--------------------------------------------|:------|:---------------------------------------
101613  * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD | 0x0 | Do Not exit LPI Mode with Magic Packet
101614  * ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END | 0x1 | Exit LPI Mode with Magic Packet
101615  *
101616  * Field Access Macros:
101617  *
101618  */
101619 /*
101620  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
101621  *
101622  * Do Not exit LPI Mode with Magic Packet
101623  */
101624 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0
101625 /*
101626  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
101627  *
101628  * Exit LPI Mode with Magic Packet
101629  */
101630 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END 0x1
101631 
101632 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
101633 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB 30
101634 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
101635 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB 30
101636 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
101637 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH 1
101638 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
101639 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK 0x40000000
101640 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
101641 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK 0xbfffffff
101642 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
101643 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET 0x0
101644 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM field value from a register. */
101645 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30)
101646 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value suitable for setting the register. */
101647 #define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000)
101648 
101649 /*
101650  * Field : Enable Low Power Interface (LPI) - en_lpi
101651  *
101652  * When set to 1, this bit enables the LPI mode supported by the AXI master and
101653  * accepts the LPI request from the AXI System Clock controller.
101654  *
101655  * When set to 0, this bit disables the LPI mode and always denies the LPI request
101656  * from the AXI System Clock controller.
101657  *
101658  * Field Enumeration Values:
101659  *
101660  * Enum | Value | Description
101661  * :---------------------------------------|:------|:-----------------
101662  * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD | 0x0 | Disable LPI Mode
101663  * ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END | 0x1 | Enable LPI Mode
101664  *
101665  * Field Access Macros:
101666  *
101667  */
101668 /*
101669  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
101670  *
101671  * Disable LPI Mode
101672  */
101673 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD 0x0
101674 /*
101675  * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
101676  *
101677  * Enable LPI Mode
101678  */
101679 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END 0x1
101680 
101681 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
101682 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB 31
101683 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
101684 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB 31
101685 /* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
101686 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH 1
101687 /* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
101688 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK 0x80000000
101689 /* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
101690 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK 0x7fffffff
101691 /* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
101692 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET 0x0
101693 /* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI field value from a register. */
101694 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET(value) (((value) & 0x80000000) >> 31)
101695 /* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value suitable for setting the register. */
101696 #define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET(value) (((value) << 31) & 0x80000000)
101697 
101698 #ifndef __ASSEMBLY__
101699 /*
101700  * WARNING: The C register and register group struct declarations are provided for
101701  * convenience and illustrative purposes. They should, however, be used with
101702  * caution as the C language standard provides no guarantees about the alignment or
101703  * atomicity of device memory accesses. The recommended practice for writing
101704  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101705  * alt_write_word() functions.
101706  *
101707  * The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MOD.
101708  */
101709 struct ALT_EMAC_DMA_AXI_BUS_MOD_s
101710 {
101711  const uint32_t undefined : 1; /* AXI Undefined Burst Length */
101712  uint32_t blen4 : 1; /* AXI Burst Length 4 */
101713  uint32_t blen8 : 1; /* AXI Burst Length 8 */
101714  uint32_t blen16 : 1; /* AXI Burst Length 16 */
101715  uint32_t : 8; /* *UNDEFINED* */
101716  const uint32_t axi_aal : 1; /* Address-Aligned Beats */
101717  uint32_t onekbbe : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE */
101718  uint32_t : 2; /* *UNDEFINED* */
101719  uint32_t rd_osr_lmt : 4; /* AXI Maximum Read OutStanding Request Limit */
101720  uint32_t wr_osr_lmt : 4; /* ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT */
101721  uint32_t : 6; /* *UNDEFINED* */
101722  uint32_t lpi_xit_frm : 1; /* ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM */
101723  uint32_t en_lpi : 1; /* Enable Low Power Interface (LPI) */
101724 };
101725 
101726 /* The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MOD. */
101727 typedef volatile struct ALT_EMAC_DMA_AXI_BUS_MOD_s ALT_EMAC_DMA_AXI_BUS_MOD_t;
101728 #endif /* __ASSEMBLY__ */
101729 
101730 /* The byte offset of the ALT_EMAC_DMA_AXI_BUS_MOD register from the beginning of the component. */
101731 #define ALT_EMAC_DMA_AXI_BUS_MOD_OFST 0x28
101732 /* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register. */
101733 #define ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST))
101734 
101735 /*
101736  * Register : Register 11 (AHB or AXI Status Register) - AHB_or_AXI_Status
101737  *
101738  * This register provides the active status of the AXI interface's read and write
101739  * channels. This register is useful for debugging purposes. In addition, this
101740  * register is valid only in the Channel 0 DMA when multiple channels are present
101741  * in the AV mode.
101742  *
101743  * Register Layout
101744  *
101745  * Bits | Access | Reset | Description
101746  * :-------|:-------|:------|:--------------------------------
101747  * [0] | R | 0x0 | AXI Master Write Channel Status
101748  * [1] | R | 0x0 | AXI Master Read Channel Status
101749  * [31:2] | ??? | 0x0 | *UNDEFINED*
101750  *
101751  */
101752 /*
101753  * Field : AXI Master Write Channel Status - axwhsts
101754  *
101755  * When high, it indicates that AXI Master's write channel is active and
101756  * transferring data
101757  *
101758  * Field Access Macros:
101759  *
101760  */
101761 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
101762 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB 0
101763 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
101764 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB 0
101765 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
101766 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH 1
101767 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
101768 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK 0x00000001
101769 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
101770 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK 0xfffffffe
101771 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
101772 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET 0x0
101773 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS field value from a register. */
101774 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0)
101775 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value suitable for setting the register. */
101776 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET(value) (((value) << 0) & 0x00000001)
101777 
101778 /*
101779  * Field : AXI Master Read Channel Status - axirdsts
101780  *
101781  * When high, it indicates that AXI Master's read channel is active and
101782  * transferring data.
101783  *
101784  * Field Access Macros:
101785  *
101786  */
101787 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
101788 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB 1
101789 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
101790 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB 1
101791 /* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
101792 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH 1
101793 /* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
101794 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK 0x00000002
101795 /* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
101796 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK 0xfffffffd
101797 /* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
101798 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET 0x0
101799 /* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS field value from a register. */
101800 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1)
101801 /* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value suitable for setting the register. */
101802 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002)
101803 
101804 #ifndef __ASSEMBLY__
101805 /*
101806  * WARNING: The C register and register group struct declarations are provided for
101807  * convenience and illustrative purposes. They should, however, be used with
101808  * caution as the C language standard provides no guarantees about the alignment or
101809  * atomicity of device memory accesses. The recommended practice for writing
101810  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101811  * alt_write_word() functions.
101812  *
101813  * The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT.
101814  */
101815 struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s
101816 {
101817  const uint32_t axwhsts : 1; /* AXI Master Write Channel Status */
101818  const uint32_t axirdsts : 1; /* AXI Master Read Channel Status */
101819  uint32_t : 30; /* *UNDEFINED* */
101820 };
101821 
101822 /* The typedef declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT. */
101823 typedef volatile struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s ALT_EMAC_DMA_AHB_OR_AXI_STAT_t;
101824 #endif /* __ASSEMBLY__ */
101825 
101826 /* The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register from the beginning of the component. */
101827 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST 0x2c
101828 /* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register. */
101829 #define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST))
101830 
101831 /*
101832  * Register : Register 18 (Current Host Transmit Descriptor Register) - Current_Host_Transmit_Descriptor
101833  *
101834  * The Current Host Transmit Descriptor register points to the start address of the
101835  * current Transmit Descriptor read by the DMA.
101836  *
101837  * Register Layout
101838  *
101839  * Bits | Access | Reset | Description
101840  * :-------|:-------|:------|:-----------------------------------------
101841  * [31:0] | R | 0x0 | Host Transmit Descriptor Address Pointer
101842  *
101843  */
101844 /*
101845  * Field : Host Transmit Descriptor Address Pointer - curtdesaptr
101846  *
101847  * Cleared on Reset. Pointer updated by the DMA during operation.
101848  *
101849  * Field Access Macros:
101850  *
101851  */
101852 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
101853 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_LSB 0
101854 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
101855 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_MSB 31
101856 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
101857 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_WIDTH 32
101858 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
101859 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET_MSK 0xffffffff
101860 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
101861 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_CLR_MSK 0x00000000
101862 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
101863 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_RESET 0x0
101864 /* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR field value from a register. */
101865 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
101866 /* Produces a ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value suitable for setting the register. */
101867 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
101868 
101869 #ifndef __ASSEMBLY__
101870 /*
101871  * WARNING: The C register and register group struct declarations are provided for
101872  * convenience and illustrative purposes. They should, however, be used with
101873  * caution as the C language standard provides no guarantees about the alignment or
101874  * atomicity of device memory accesses. The recommended practice for writing
101875  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101876  * alt_write_word() functions.
101877  *
101878  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC.
101879  */
101880 struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s
101881 {
101882  const uint32_t curtdesaptr : 32; /* Host Transmit Descriptor Address Pointer */
101883 };
101884 
101885 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC. */
101886 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s ALT_EMAC_DMA_CUR_HOST_TX_DESC_t;
101887 #endif /* __ASSEMBLY__ */
101888 
101889 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register from the beginning of the component. */
101890 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST 0x48
101891 /* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register. */
101892 #define ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST))
101893 
101894 /*
101895  * Register : Register 19 (Current Host Receive Descriptor Register) - Current_Host_Receive_Descriptor
101896  *
101897  * The Current Host Receive Descriptor register points to the start address of the
101898  * current Receive Descriptor read by the DMA.
101899  *
101900  * Register Layout
101901  *
101902  * Bits | Access | Reset | Description
101903  * :-------|:-------|:------|:----------------------------------------
101904  * [31:0] | R | 0x0 | Host Receive Descriptor Address Pointer
101905  *
101906  */
101907 /*
101908  * Field : Host Receive Descriptor Address Pointer - currdesaptr
101909  *
101910  * Cleared on Reset. Pointer updated by the DMA during operation.
101911  *
101912  * Field Access Macros:
101913  *
101914  */
101915 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
101916 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_LSB 0
101917 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
101918 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_MSB 31
101919 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
101920 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_WIDTH 32
101921 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
101922 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET_MSK 0xffffffff
101923 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
101924 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_CLR_MSK 0x00000000
101925 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
101926 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_RESET 0x0
101927 /* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR field value from a register. */
101928 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
101929 /* Produces a ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value suitable for setting the register. */
101930 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff)
101931 
101932 #ifndef __ASSEMBLY__
101933 /*
101934  * WARNING: The C register and register group struct declarations are provided for
101935  * convenience and illustrative purposes. They should, however, be used with
101936  * caution as the C language standard provides no guarantees about the alignment or
101937  * atomicity of device memory accesses. The recommended practice for writing
101938  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
101939  * alt_write_word() functions.
101940  *
101941  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC.
101942  */
101943 struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s
101944 {
101945  const uint32_t currdesaptr : 32; /* Host Receive Descriptor Address Pointer */
101946 };
101947 
101948 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC. */
101949 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s ALT_EMAC_DMA_CUR_HOST_RX_DESC_t;
101950 #endif /* __ASSEMBLY__ */
101951 
101952 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register from the beginning of the component. */
101953 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST 0x4c
101954 /* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register. */
101955 #define ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST))
101956 
101957 /*
101958  * Register : Register 20 (Current Host Transmit Buffer Address Register) - Current_Host_Transmit_Buffer_Address
101959  *
101960  * The Current Host Transmit Buffer Address register points to the current Transmit
101961  * Buffer Address being read by the DMA.
101962  *
101963  * Register Layout
101964  *
101965  * Bits | Access | Reset | Description
101966  * :-------|:-------|:------|:-------------------------------------
101967  * [31:0] | R | 0x0 | Host Transmit Buffer Address Pointer
101968  *
101969  */
101970 /*
101971  * Field : Host Transmit Buffer Address Pointer - curtbufaptr
101972  *
101973  * Cleared on Reset. Pointer updated by the DMA during operation.
101974  *
101975  * Field Access Macros:
101976  *
101977  */
101978 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
101979 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_LSB 0
101980 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
101981 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_MSB 31
101982 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
101983 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_WIDTH 32
101984 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
101985 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET_MSK 0xffffffff
101986 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
101987 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_CLR_MSK 0x00000000
101988 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
101989 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_RESET 0x0
101990 /* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR field value from a register. */
101991 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
101992 /* Produces a ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value suitable for setting the register. */
101993 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
101994 
101995 #ifndef __ASSEMBLY__
101996 /*
101997  * WARNING: The C register and register group struct declarations are provided for
101998  * convenience and illustrative purposes. They should, however, be used with
101999  * caution as the C language standard provides no guarantees about the alignment or
102000  * atomicity of device memory accesses. The recommended practice for writing
102001  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102002  * alt_write_word() functions.
102003  *
102004  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR.
102005  */
102006 struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s
102007 {
102008  const uint32_t curtbufaptr : 32; /* Host Transmit Buffer Address Pointer */
102009 };
102010 
102011 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR. */
102012 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t;
102013 #endif /* __ASSEMBLY__ */
102014 
102015 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register from the beginning of the component. */
102016 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST 0x50
102017 /* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register. */
102018 #define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST))
102019 
102020 /*
102021  * Register : Register 21 (Current Host Receive Buffer Address Register) - Current_Host_Receive_Buffer_Address
102022  *
102023  * The Current Host Receive Buffer Address register points to the current Receive
102024  * Buffer address being read by the DMA.
102025  *
102026  * Register Layout
102027  *
102028  * Bits | Access | Reset | Description
102029  * :-------|:-------|:------|:------------------------------------
102030  * [31:0] | R | 0x0 | Host Receive Buffer Address Pointer
102031  *
102032  */
102033 /*
102034  * Field : Host Receive Buffer Address Pointer - currbufaptr
102035  *
102036  * Cleared on Reset. Pointer updated by the DMA during operation.
102037  *
102038  * Field Access Macros:
102039  *
102040  */
102041 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
102042 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_LSB 0
102043 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
102044 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_MSB 31
102045 /* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
102046 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_WIDTH 32
102047 /* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
102048 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET_MSK 0xffffffff
102049 /* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
102050 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_CLR_MSK 0x00000000
102051 /* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
102052 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_RESET 0x0
102053 /* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR field value from a register. */
102054 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
102055 /* Produces a ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value suitable for setting the register. */
102056 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)
102057 
102058 #ifndef __ASSEMBLY__
102059 /*
102060  * WARNING: The C register and register group struct declarations are provided for
102061  * convenience and illustrative purposes. They should, however, be used with
102062  * caution as the C language standard provides no guarantees about the alignment or
102063  * atomicity of device memory accesses. The recommended practice for writing
102064  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
102065  * alt_write_word() functions.
102066  *
102067  * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR.
102068  */
102069 struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s
102070 {
102071  const uint32_t currbufaptr : 32; /* Host Receive Buffer Address Pointer */
102072 };
102073 
102074 /* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR. */
102075 typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t;
102076 #endif /* __ASSEMBLY__ */
102077 
102078 /* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register from the beginning of the component. */
102079 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST 0x54
102080 /* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register. */
102081 #define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST))
102082 
102083 /*
102084  * Register : Register 22 (HW Feature Register) - HW_Feature
102085  *
102086  * This register indicates the presence of the optional features or functions of
102087  * the gmac. The software driver can use this register to dynamically enable or
102088  * disable the programs related to the optional blocks.
102089  *
102090  * Register Layout
102091  *
102092  * Bits | Access | Reset | Description
102093  * :--------|:-------|:------|:------------------------------
102094  * [0] | R | 0x1 | MII Selection
102095  * [1] | R | 0x1 | GMII Selection
102096  * [2] | R | 0x1 | Half Duplex Selection
102097  * [3] | ??? | 0x0 | *UNDEFINED*
102098  * [4] | R | 0x1 | Hash Filter
102099  * [5] | R | 0x1 | Multiple MAC Address Register
102100  * [6] | R | 0x0 | PCS Select
102101  * [7] | ??? | 0x0 | *UNDEFINED*
102102  * [8] | R | 0x1 | SMA Select
102103  * [9] | R | 0x1 | RWK Select
102104  * [10] | R | 0x1 | MGK Select
102105  * [11] | R | 0x1 | MMC Select
102106  * [12] | R | 0x1 | TS Version1 Select
102107  * [13] | R | 0x1 | TS Version2 Select
102108  * [14] | R | 0x1 | Energy Efficient Ethernet
102109  * [15] | R | 0x0 | AV Select
102110  * [16] | R | 0x1 | Tx Offload Checksum
102111  * [17] | R | 0x0 | Rx Type 1 Checksum Offload
102112  * [18] | R | 0x1 | Rx Type 2 Checksum Offload
102113  * [19] | R | 0x1 | Rx FIFO Size
102114  * [21:20] | R | 0x0 | Rx Channel Count
102115  * [23:22] | R | 0x0 | Tx Channel Count
102116  * [24] | R | 0x1 | Enhanced Descriptor Select
102117  * [27:25] | ??? | 0x0 | *UNDEFINED*
102118  * [30:28] | R | 0x0 | Selected PHY Interface
102119  * [31] | ??? | 0x0 | *UNDEFINED*
102120  *
102121  */
102122 /*
102123  * Field : MII Selection - miisel
102124  *
102125  * 10/100 Mbps support
102126  *
102127  * Field Enumeration Values:
102128  *
102129  * Enum | Value | Description
102130  * :--------------------------------------|:------|:-----------------------------
102131  * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD | 0x0 | 10 Mbps or 100 Mbps disabled
102132  * ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END | 0x1 | 10 Mbps or 100 Mbps enabled
102133  *
102134  * Field Access Macros:
102135  *
102136  */
102137 /*
102138  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
102139  *
102140  * 10 Mbps or 100 Mbps disabled
102141  */
102142 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD 0x0
102143 /*
102144  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
102145  *
102146  * 10 Mbps or 100 Mbps enabled
102147  */
102148 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END 0x1
102149 
102150 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
102151 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB 0
102152 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
102153 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB 0
102154 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
102155 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH 1
102156 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
102157 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK 0x00000001
102158 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
102159 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK 0xfffffffe
102160 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
102161 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET 0x1
102162 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register. */
102163 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0)
102164 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register. */
102165 #define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001)
102166 
102167 /*
102168  * Field : GMII Selection - gmiisel
102169  *
102170  * 1000 Mbps support
102171  *
102172  * Field Enumeration Values:
102173  *
102174  * Enum | Value | Description
102175  * :---------------------------------------|:------|:-------------------
102176  * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD | 0x0 | 1000 Mbps disabled
102177  * ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END | 0x1 | 1000 Mbps enabled
102178  *
102179  * Field Access Macros:
102180  *
102181  */
102182 /*
102183  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
102184  *
102185  * 1000 Mbps disabled
102186  */
102187 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD 0x0
102188 /*
102189  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
102190  *
102191  * 1000 Mbps enabled
102192  */
102193 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END 0x1
102194 
102195 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
102196 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB 1
102197 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
102198 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB 1
102199 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
102200 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH 1
102201 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
102202 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK 0x00000002
102203 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
102204 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK 0xfffffffd
102205 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
102206 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET 0x1
102207 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register. */
102208 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1)
102209 /* Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register. */
102210 #define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002)
102211 
102212 /*
102213  * Field : Half Duplex Selection - hdsel
102214  *
102215  * Half-Duplex support
102216  *
102217  * Field Enumeration Values:
102218  *
102219  * Enum | Value | Description
102220  * :-------------------------------------|:------|:---------------------
102221  * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD | 0x0 | Half Duplex disabled
102222  * ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END | 0x1 | Half Duplex enabled
102223  *
102224  * Field Access Macros:
102225  *
102226  */
102227 /*
102228  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
102229  *
102230  * Half Duplex disabled
102231  */
102232 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD 0x0
102233 /*
102234  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
102235  *
102236  * Half Duplex enabled
102237  */
102238 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END 0x1
102239 
102240 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
102241 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB 2
102242 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
102243 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB 2
102244 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
102245 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH 1
102246 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
102247 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK 0x00000004
102248 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
102249 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK 0xfffffffb
102250 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
102251 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET 0x1
102252 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register. */
102253 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2)
102254 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register. */
102255 #define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004)
102256 
102257 /*
102258  * Field : Hash Filter - hashsel
102259  *
102260  * HASH Filter support
102261  *
102262  * Field Enumeration Values:
102263  *
102264  * Enum | Value | Description
102265  * :---------------------------------------|:------|:---------------------
102266  * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD | 0x0 | Hash Filter disabled
102267  * ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END | 0x1 | Hash Filter enabled
102268  *
102269  * Field Access Macros:
102270  *
102271  */
102272 /*
102273  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
102274  *
102275  * Hash Filter disabled
102276  */
102277 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD 0x0
102278 /*
102279  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
102280  *
102281  * Hash Filter enabled
102282  */
102283 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END 0x1
102284 
102285 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
102286 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB 4
102287 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
102288 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB 4
102289 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
102290 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH 1
102291 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
102292 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK 0x00000010
102293 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
102294 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK 0xffffffef
102295 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
102296 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET 0x1
102297 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register. */
102298 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4)
102299 /* Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register. */
102300 #define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010)
102301 
102302 /*
102303  * Field : Multiple MAC Address Register - addmacadrsel
102304  *
102305  * Multiple MAC Address Registers support
102306  *
102307  * Field Enumeration Values:
102308  *
102309  * Enum | Value | Description
102310  * :--------------------------------------------|:------|:----------------------------------------
102311  * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD | 0x0 | Multiple MAC Address registers disabled
102312  * ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END | 0x1 | Multiple MAC Address registers enabled
102313  *
102314  * Field Access Macros:
102315  *
102316  */
102317 /*
102318  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
102319  *
102320  * Multiple MAC Address registers disabled
102321  */
102322 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD 0x0
102323 /*
102324  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
102325  *
102326  * Multiple MAC Address registers enabled
102327  */
102328 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END 0x1
102329 
102330 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
102331 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB 5
102332 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
102333 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB 5
102334 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
102335 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH 1
102336 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
102337 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK 0x00000020
102338 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
102339 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK 0xffffffdf
102340 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
102341 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET 0x1
102342 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register. */
102343 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5)
102344 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register. */
102345 #define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020)
102346 
102347 /*
102348  * Field : PCS Select - pcssel
102349  *
102350  * TBI/SGMII/RTBI PHY interface support
102351  *
102352  * Field Enumeration Values:
102353  *
102354  * Enum | Value | Description
102355  * :--------------------------------------|:------|:---------------------
102356  * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD | 0x0 | PCS Support disabled
102357  * ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END | 0x1 | PCS Support enabled
102358  *
102359  * Field Access Macros:
102360  *
102361  */
102362 /*
102363  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
102364  *
102365  * PCS Support disabled
102366  */
102367 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD 0x0
102368 /*
102369  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
102370  *
102371  * PCS Support enabled
102372  */
102373 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END 0x1
102374 
102375 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
102376 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB 6
102377 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
102378 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB 6
102379 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
102380 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH 1
102381 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
102382 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK 0x00000040
102383 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
102384 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK 0xffffffbf
102385 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
102386 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET 0x0
102387 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register. */
102388 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6)
102389 /* Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register. */
102390 #define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040)
102391 
102392 /*
102393  * Field : SMA Select - smasel
102394  *
102395  * SMA (MDIO) Interface support
102396  *
102397  * Field Enumeration Values:
102398  *
102399  * Enum | Value | Description
102400  * :--------------------------------------|:------|:-------------------------------
102401  * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD | 0x0 | SMA Interface Support disabled
102402  * ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END | 0x1 | SMA Interface Support enabled
102403  *
102404  * Field Access Macros:
102405  *
102406  */
102407 /*
102408  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
102409  *
102410  * SMA Interface Support disabled
102411  */
102412 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD 0x0
102413 /*
102414  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
102415  *
102416  * SMA Interface Support enabled
102417  */
102418 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END 0x1
102419 
102420 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
102421 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB 8
102422 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
102423 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB 8
102424 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
102425 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH 1
102426 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
102427 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK 0x00000100
102428 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
102429 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK 0xfffffeff
102430 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
102431 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET 0x1
102432 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register. */
102433 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8)
102434 /* Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register. */
102435 #define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100)
102436 
102437 /*
102438  * Field : RWK Select - rwksel
102439  *
102440  * PMT Remote Wakeup support
102441  *
102442  * Field Enumeration Values:
102443  *
102444  * Enum | Value | Description
102445  * :--------------------------------------|:------|:----------------------------
102446  * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD | 0x0 | PMT Remote Wake Up disabled
102447  * ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END | 0x1 | PMT Remote Wake Up enabled
102448  *
102449  * Field Access Macros:
102450  *
102451  */
102452 /*
102453  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
102454  *
102455  * PMT Remote Wake Up disabled
102456  */
102457 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD 0x0
102458 /*
102459  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
102460  *
102461  * PMT Remote Wake Up enabled
102462  */
102463 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END 0x1
102464 
102465 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
102466 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB 9
102467 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
102468 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB 9
102469 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
102470 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH 1
102471 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
102472 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK 0x00000200
102473 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
102474 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK 0xfffffdff
102475 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
102476 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET 0x1
102477 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register. */
102478 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9)
102479 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register. */
102480 #define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200)
102481 
102482 /*
102483  * Field : MGK Select - mgksel
102484  *
102485  * PMT Magic Packet
102486  *
102487  * Field Enumeration Values:
102488  *
102489  * Enum | Value | Description
102490  * :--------------------------------------|:------|:--------------------------
102491  * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD | 0x0 | PMT Magic Packet disabled
102492  * ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END | 0x1 | PMT Magic Packet enabled
102493  *
102494  * Field Access Macros:
102495  *
102496  */
102497 /*
102498  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
102499  *
102500  * PMT Magic Packet disabled
102501  */
102502 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD 0x0
102503 /*
102504  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
102505  *
102506  * PMT Magic Packet enabled
102507  */
102508 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END 0x1
102509 
102510 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
102511 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB 10
102512 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
102513 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB 10
102514 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
102515 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH 1
102516 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
102517 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK 0x00000400
102518 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
102519 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK 0xfffffbff
102520 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
102521 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET 0x1
102522 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register. */
102523 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10)
102524 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register. */
102525 #define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400)
102526 
102527 /*
102528  * Field : MMC Select - mmcsel
102529  *
102530  * RMON block
102531  *
102532  * Field Enumeration Values:
102533  *
102534  * Enum | Value | Description
102535  * :--------------------------------------|:------|:--------------------
102536  * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD | 0x0 | Rmon block disabled
102537  * ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END | 0x1 | Rmon block enabled
102538  *
102539  * Field Access Macros:
102540  *
102541  */
102542 /*
102543  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
102544  *
102545  * Rmon block disabled
102546  */
102547 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD 0x0
102548 /*
102549  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
102550  *
102551  * Rmon block enabled
102552  */
102553 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END 0x1
102554 
102555 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
102556 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB 11
102557 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
102558 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB 11
102559 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
102560 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH 1
102561 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
102562 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK 0x00000800
102563 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
102564 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK 0xfffff7ff
102565 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
102566 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET 0x1
102567 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register. */
102568 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11)
102569 /* Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register. */
102570 #define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800)
102571 
102572 /*
102573  * Field : TS Version1 Select - tsver1sel
102574  *
102575  * Only IEEE 1588-2002 Timestamp
102576  *
102577  * Field Enumeration Values:
102578  *
102579  * Enum | Value | Description
102580  * :-----------------------------------------|:------|:----------------------------
102581  * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD | 0x0 | TS Version1 Select disabled
102582  * ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END | 0x1 | TS Version1 Select enabled
102583  *
102584  * Field Access Macros:
102585  *
102586  */
102587 /*
102588  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
102589  *
102590  * TS Version1 Select disabled
102591  */
102592 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD 0x0
102593 /*
102594  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
102595  *
102596  * TS Version1 Select enabled
102597  */
102598 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END 0x1
102599 
102600 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
102601 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB 12
102602 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
102603 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB 12
102604 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
102605 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH 1
102606 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
102607 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK 0x00001000
102608 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
102609 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK 0xffffefff
102610 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
102611 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET 0x1
102612 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register. */
102613 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12)
102614 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register. */
102615 #define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000)
102616 
102617 /*
102618  * Field : TS Version2 Select - tsver2sel
102619  *
102620  * IEEE 1588-2008 Advanced Timestamp
102621  *
102622  * Field Enumeration Values:
102623  *
102624  * Enum | Value | Description
102625  * :-----------------------------------------|:------|:----------------------------
102626  * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD | 0x0 | TS Version2 Select disabled
102627  * ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END | 0x1 | TS Version2 Select enabled
102628  *
102629  * Field Access Macros:
102630  *
102631  */
102632 /*
102633  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
102634  *
102635  * TS Version2 Select disabled
102636  */
102637 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD 0x0
102638 /*
102639  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
102640  *
102641  * TS Version2 Select enabled
102642  */
102643 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END 0x1
102644 
102645 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
102646 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB 13
102647 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
102648 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB 13
102649 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
102650 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH 1
102651 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
102652 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK 0x00002000
102653 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
102654 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK 0xffffdfff
102655 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
102656 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET 0x1
102657 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register. */
102658 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13)
102659 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register. */
102660 #define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000)
102661 
102662 /*
102663  * Field : Energy Efficient Ethernet - eeesel
102664  *
102665  * Energy Efficient Ethernet Feature
102666  *
102667  * Field Enumeration Values:
102668  *
102669  * Enum | Value | Description
102670  * :--------------------------------------|:------|:-----------------------------------
102671  * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD | 0x0 | Energy Efficient Ethernet disabled
102672  * ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END | 0x1 | Energy Efficient Ethernet enabled
102673  *
102674  * Field Access Macros:
102675  *
102676  */
102677 /*
102678  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
102679  *
102680  * Energy Efficient Ethernet disabled
102681  */
102682 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD 0x0
102683 /*
102684  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
102685  *
102686  * Energy Efficient Ethernet enabled
102687  */
102688 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END 0x1
102689 
102690 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
102691 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB 14
102692 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
102693 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB 14
102694 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
102695 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH 1
102696 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
102697 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK 0x00004000
102698 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
102699 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK 0xffffbfff
102700 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
102701 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET 0x1
102702 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register. */
102703 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14)
102704 /* Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register. */
102705 #define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000)
102706 
102707 /*
102708  * Field : AV Select - avsel
102709  *
102710  * AV Feature
102711  *
102712  * Field Enumeration Values:
102713  *
102714  * Enum | Value | Description
102715  * :-------------------------------------|:------|:-------------------
102716  * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD | 0x0 | AV Select disabled
102717  * ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END | 0x1 | AV Select enabled
102718  *
102719  * Field Access Macros:
102720  *
102721  */
102722 /*
102723  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
102724  *
102725  * AV Select disabled
102726  */
102727 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD 0x0
102728 /*
102729  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
102730  *
102731  * AV Select enabled
102732  */
102733 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END 0x1
102734 
102735 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
102736 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB 15
102737 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
102738 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB 15
102739 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
102740 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH 1
102741 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
102742 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK 0x00008000
102743 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
102744 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK 0xffff7fff
102745 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
102746 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET 0x0
102747 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register. */
102748 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15)
102749 /* Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register. */
102750 #define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000)
102751 
102752 /*
102753  * Field : Tx Offload Checksum - txoesel
102754  *
102755  * Checksum Offload in Tx
102756  *
102757  * Field Enumeration Values:
102758  *
102759  * Enum | Value | Description
102760  * :---------------------------------------|:------|:-----------------------------
102761  * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD | 0x0 | Tx Offload Checksum disabled
102762  * ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END | 0x1 | Tx Offload Checksum enabled
102763  *
102764  * Field Access Macros:
102765  *
102766  */
102767 /*
102768  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
102769  *
102770  * Tx Offload Checksum disabled
102771  */
102772 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD 0x0
102773 /*
102774  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
102775  *
102776  * Tx Offload Checksum enabled
102777  */
102778 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END 0x1
102779 
102780 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
102781 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB 16
102782 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
102783 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB 16
102784 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
102785 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH 1
102786 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
102787 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK 0x00010000
102788 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
102789 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK 0xfffeffff
102790 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
102791 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET 0x1
102792 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXOESEL field value from a register. */
102793 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET(value) (((value) & 0x00010000) >> 16)
102794 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value suitable for setting the register. */
102795 #define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET(value) (((value) << 16) & 0x00010000)
102796 
102797 /*
102798  * Field : Rx Type 1 Checksum Offload - rxtyp1coe
102799  *
102800  * IP Checksum Offload (Type 1) in Rx
102801  *
102802  * Field Enumeration Values:
102803  *
102804  * Enum | Value | Description
102805  * :-----------------------------------------|:------|:------------------------------------
102806  * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD | 0x0 | Rx Type 1 Checksum Offload disabled
102807  * ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END | 0x1 | Rx Type 1 Checksum Offload enabled
102808  *
102809  * Field Access Macros:
102810  *
102811  */
102812 /*
102813  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
102814  *
102815  * Rx Type 1 Checksum Offload disabled
102816  */
102817 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD 0x0
102818 /*
102819  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
102820  *
102821  * Rx Type 1 Checksum Offload enabled
102822  */
102823 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END 0x1
102824 
102825 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
102826 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB 17
102827 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
102828 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB 17
102829 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
102830 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH 1
102831 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
102832 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK 0x00020000
102833 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
102834 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK 0xfffdffff
102835 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
102836 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET 0x0
102837 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register. */
102838 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17)
102839 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register. */
102840 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000)
102841 
102842 /*
102843  * Field : Rx Type 2 Checksum Offload - rxtyp2coe
102844  *
102845  * IP Checksum Offload (Type 2) in Rx
102846  *
102847  * Field Enumeration Values:
102848  *
102849  * Enum | Value | Description
102850  * :-----------------------------------------|:------|:------------------------------------
102851  * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD | 0x0 | Rx Type 2 Checksum Offload disabled
102852  * ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END | 0x1 | Rx Type 2 Checksum Offload enabled
102853  *
102854  * Field Access Macros:
102855  *
102856  */
102857 /*
102858  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
102859  *
102860  * Rx Type 2 Checksum Offload disabled
102861  */
102862 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD 0x0
102863 /*
102864  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
102865  *
102866  * Rx Type 2 Checksum Offload enabled
102867  */
102868 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END 0x1
102869 
102870 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
102871 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB 18
102872 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
102873 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB 18
102874 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
102875 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH 1
102876 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
102877 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK 0x00040000
102878 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
102879 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK 0xfffbffff
102880 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
102881 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET 0x1
102882 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register. */
102883 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18)
102884 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register. */
102885 #define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000)
102886 
102887 /*
102888  * Field : Rx FIFO Size - rxfifosize
102889  *
102890  * RxFIFO > 2048 Bytes
102891  *
102892  * Field Enumeration Values:
102893  *
102894  * Enum | Value | Description
102895  * :------------------------------------------|:------|:-----------------------------
102896  * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD | 0x0 | RxFIFO > 2048 bytes disabled
102897  * ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END | 0x1 | RxFIFO > 2048 bytes enabled
102898  *
102899  * Field Access Macros:
102900  *
102901  */
102902 /*
102903  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
102904  *
102905  * RxFIFO > 2048 bytes disabled
102906  */
102907 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD 0x0
102908 /*
102909  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
102910  *
102911  * RxFIFO > 2048 bytes enabled
102912  */
102913 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END 0x1
102914 
102915 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
102916 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB 19
102917 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
102918 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB 19
102919 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
102920 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH 1
102921 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
102922 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK 0x00080000
102923 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
102924 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK 0xfff7ffff
102925 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
102926 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET 0x1
102927 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register. */
102928 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19)
102929 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register. */
102930 #define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000)
102931 
102932 /*
102933  * Field : Rx Channel Count - rxchcnt
102934  *
102935  * Number of additional Rx channels
102936  *
102937  * Field Enumeration Values:
102938  *
102939  * Enum | Value | Description
102940  * :---------------------------------------|:------|:--------------------------
102941  * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD | 0x0 | Rx Channel Count disabled
102942  * ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END | 0x1 | Rx Channel Count enabled
102943  *
102944  * Field Access Macros:
102945  *
102946  */
102947 /*
102948  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
102949  *
102950  * Rx Channel Count disabled
102951  */
102952 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD 0x0
102953 /*
102954  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
102955  *
102956  * Rx Channel Count enabled
102957  */
102958 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END 0x1
102959 
102960 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
102961 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB 20
102962 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
102963 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB 21
102964 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
102965 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH 2
102966 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
102967 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK 0x00300000
102968 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
102969 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK 0xffcfffff
102970 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
102971 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET 0x0
102972 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register. */
102973 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20)
102974 /* Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register. */
102975 #define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000)
102976 
102977 /*
102978  * Field : Tx Channel Count - txchcnt
102979  *
102980  * Number of additional Tx channels
102981  *
102982  * Field Enumeration Values:
102983  *
102984  * Enum | Value | Description
102985  * :---------------------------------------|:------|:--------------------------
102986  * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD | 0x0 | Tx Channel Count disabled
102987  * ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END | 0x1 | Tx Channel Count enabled
102988  *
102989  * Field Access Macros:
102990  *
102991  */
102992 /*
102993  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
102994  *
102995  * Tx Channel Count disabled
102996  */
102997 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD 0x0
102998 /*
102999  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
103000  *
103001  * Tx Channel Count enabled
103002  */
103003 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END 0x1
103004 
103005 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
103006 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB 22
103007 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
103008 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB 23
103009 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
103010 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH 2
103011 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
103012 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK 0x00c00000
103013 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
103014 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK 0xff3fffff
103015 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
103016 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET 0x0
103017 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register. */
103018 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22)
103019 /* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register. */
103020 #define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000)
103021 
103022 /*
103023  * Field : Enhanced Descriptor Select - enhdessel
103024  *
103025  * Alternate (Enhanced Descriptor)
103026  *
103027  * Field Enumeration Values:
103028  *
103029  * Enum | Value | Description
103030  * :-----------------------------------------|:------|:------------------------------------
103031  * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD | 0x0 | Enhanced Descriptor Select disabled
103032  * ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END | 0x1 | Enhanced Descriptor Select enabled
103033  *
103034  * Field Access Macros:
103035  *
103036  */
103037 /*
103038  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
103039  *
103040  * Enhanced Descriptor Select disabled
103041  */
103042 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD 0x0
103043 /*
103044  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
103045  *
103046  * Enhanced Descriptor Select enabled
103047  */
103048 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END 0x1
103049 
103050 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
103051 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB 24
103052 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
103053 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB 24
103054 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
103055 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH 1
103056 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
103057 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK 0x01000000
103058 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
103059 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK 0xfeffffff
103060 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
103061 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET 0x1
103062 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register. */
103063 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24)
103064 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register. */
103065 #define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000)
103066 
103067 /*
103068  * Field : Selected PHY Interface - actphyif
103069  *
103070  * When you have multiple PHY interfaces in your configuration, this field
103071  * indicates the sampled value of emacx_phy_if_selduring reset de-assertion.
103072  *
103073  * Field Enumeration Values:
103074  *
103075  * Enum | Value | Description
103076  * :--------------------------------------------|:------|:--------------------------
103077  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 | 0x0 | Sampled Value GMII or MII
103078  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 | 0x1 | Sampled Value RGMII
103079  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 | 0x2 | Sampled Value SGMII
103080  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 | 0x3 | Sampled Value TBI
103081  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 | 0x4 | Sampled Value RMII
103082  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 | 0x5 | Sampled Value RTBI
103083  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 | 0x6 | Sampled Value SMII
103084  * ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 | 0x7 | Sampled Value RevMII
103085  *
103086  * Field Access Macros:
103087  *
103088  */
103089 /*
103090  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103091  *
103092  * Sampled Value GMII or MII
103093  */
103094 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 0x0
103095 /*
103096  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103097  *
103098  * Sampled Value RGMII
103099  */
103100 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 0x1
103101 /*
103102  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103103  *
103104  * Sampled Value SGMII
103105  */
103106 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 0x2
103107 /*
103108  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103109  *
103110  * Sampled Value TBI
103111  */
103112 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 0x3
103113 /*
103114  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103115  *
103116  * Sampled Value RMII
103117  */
103118 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 0x4
103119 /*
103120  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103121  *
103122  * Sampled Value RTBI
103123  */
103124 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 0x5
103125 /*
103126  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103127  *
103128  * Sampled Value SMII
103129  */
103130 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 0x6
103131 /*
103132  * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
103133  *
103134  * Sampled Value RevMII
103135  */
103136 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 0x7
103137 
103138 /* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
103139 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB 28
103140 /* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
103141 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB 30
103142 /* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
103143 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH 3
103144 /* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
103145 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK 0x70000000
103146 /* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
103147 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK 0x8fffffff
103148 /* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
103149 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET 0x0
103150 /* Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register. */
103151 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28)
103152 /* Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register. */
103153 #define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000)
103154 
103155 #ifndef __ASSEMBLY__
103156 /*
103157  * WARNING: The C register and register group struct declarations are provided for
103158  * convenience and illustrative purposes. They should, however, be used with
103159  * caution as the C language standard provides no guarantees about the alignment or
103160  * atomicity of device memory accesses. The recommended practice for writing
103161  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
103162  * alt_write_word() functions.
103163  *
103164  * The struct declaration for register ALT_EMAC_DMA_HW_FEATURE.
103165  */
103166 struct ALT_EMAC_DMA_HW_FEATURE_s
103167 {
103168  const uint32_t miisel : 1; /* MII Selection */
103169  const uint32_t gmiisel : 1; /* GMII Selection */
103170  const uint32_t hdsel : 1; /* Half Duplex Selection */
103171  uint32_t : 1; /* *UNDEFINED* */
103172  const uint32_t hashsel : 1; /* Hash Filter */
103173  const uint32_t addmacadrsel : 1; /* Multiple MAC Address Register */
103174  const uint32_t pcssel : 1; /* PCS Select */
103175  uint32_t : 1; /* *UNDEFINED* */
103176  const uint32_t smasel : 1; /* SMA Select */
103177  const uint32_t rwksel : 1; /* RWK Select */
103178  const uint32_t mgksel : 1; /* MGK Select */
103179  const uint32_t mmcsel : 1; /* MMC Select */
103180  const uint32_t tsver1sel : 1; /* TS Version1 Select */
103181  const uint32_t tsver2sel : 1; /* TS Version2 Select */
103182  const uint32_t eeesel : 1; /* Energy Efficient Ethernet */
103183  const uint32_t avsel : 1; /* AV Select */
103184  const uint32_t txoesel : 1; /* Tx Offload Checksum */
103185  const uint32_t rxtyp1coe : 1; /* Rx Type 1 Checksum Offload */
103186  const uint32_t rxtyp2coe : 1; /* Rx Type 2 Checksum Offload */
103187  const uint32_t rxfifosize : 1; /* Rx FIFO Size */
103188  const uint32_t rxchcnt : 2; /* Rx Channel Count */
103189  const uint32_t txchcnt : 2; /* Tx Channel Count */
103190  const uint32_t enhdessel : 1; /* Enhanced Descriptor Select */
103191  uint32_t : 3; /* *UNDEFINED* */
103192  const uint32_t actphyif : 3; /* Selected PHY Interface */
103193  uint32_t : 1; /* *UNDEFINED* */
103194 };
103195 
103196 /* The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE. */
103197 typedef volatile struct ALT_EMAC_DMA_HW_FEATURE_s ALT_EMAC_DMA_HW_FEATURE_t;
103198 #endif /* __ASSEMBLY__ */
103199 
103200 /* The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component. */
103201 #define ALT_EMAC_DMA_HW_FEATURE_OFST 0x58
103202 /* The address of the ALT_EMAC_DMA_HW_FEATURE register. */
103203 #define ALT_EMAC_DMA_HW_FEATURE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))
103204 
103205 #ifndef __ASSEMBLY__
103206 /*
103207  * WARNING: The C register and register group struct declarations are provided for
103208  * convenience and illustrative purposes. They should, however, be used with
103209  * caution as the C language standard provides no guarantees about the alignment or
103210  * atomicity of device memory accesses. The recommended practice for writing
103211  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
103212  * alt_write_word() functions.
103213  *
103214  * The struct declaration for register group ALT_EMAC_DMA.
103215  */
103216 struct ALT_EMAC_DMA_s
103217 {
103218  ALT_EMAC_DMA_BUS_MOD_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MOD */
103219  ALT_EMAC_DMA_TX_POLL_DEMAND_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */
103220  ALT_EMAC_DMA_RX_POLL_DEMAND_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */
103221  ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
103222  ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
103223  ALT_EMAC_DMA_STAT_t Status; /* ALT_EMAC_DMA_STAT */
103224  ALT_EMAC_DMA_OP_MOD_t Operation_Mode; /* ALT_EMAC_DMA_OP_MOD */
103225  ALT_EMAC_DMA_INT_EN_t Interrupt_Enable; /* ALT_EMAC_DMA_INT_EN */
103226  ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
103227  ALT_EMAC_DMA_RX_INT_WDT_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RX_INT_WDT */
103228  ALT_EMAC_DMA_AXI_BUS_MOD_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */
103229  ALT_EMAC_DMA_AHB_OR_AXI_STAT_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
103230  volatile uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */
103231  ALT_EMAC_DMA_CUR_HOST_TX_DESC_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
103232  ALT_EMAC_DMA_CUR_HOST_RX_DESC_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
103233  ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
103234  ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
103235  ALT_EMAC_DMA_HW_FEATURE_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */
103236 };
103237 
103238 /* The typedef declaration for register group ALT_EMAC_DMA. */
103239 typedef volatile struct ALT_EMAC_DMA_s ALT_EMAC_DMA_t;
103240 /* The struct declaration for the raw register contents of register group ALT_EMAC_DMA. */
103241 struct ALT_EMAC_DMA_raw_s
103242 {
103243  volatile uint32_t Bus_Mode; /* ALT_EMAC_DMA_BUS_MOD */
103244  volatile uint32_t Transmit_Poll_Demand; /* ALT_EMAC_DMA_TX_POLL_DEMAND */
103245  volatile uint32_t Receive_Poll_Demand; /* ALT_EMAC_DMA_RX_POLL_DEMAND */
103246  volatile uint32_t Receive_Descriptor_List_Address; /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
103247  volatile uint32_t Transmit_Descriptor_List_Address; /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
103248  volatile uint32_t Status; /* ALT_EMAC_DMA_STAT */
103249  volatile uint32_t Operation_Mode; /* ALT_EMAC_DMA_OP_MOD */
103250  volatile uint32_t Interrupt_Enable; /* ALT_EMAC_DMA_INT_EN */
103251  volatile uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
103252  volatile uint32_t Receive_Interrupt_Watchdog_Timer; /* ALT_EMAC_DMA_RX_INT_WDT */
103253  volatile uint32_t AXI_Bus_Mode; /* ALT_EMAC_DMA_AXI_BUS_MOD */
103254  volatile uint32_t AHB_or_AXI_Status; /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
103255  uint32_t _pad_0x30_0x47[6]; /* *UNDEFINED* */
103256  volatile uint32_t Current_Host_Transmit_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
103257  volatile uint32_t Current_Host_Receive_Descriptor; /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
103258  volatile uint32_t Current_Host_Transmit_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
103259  volatile uint32_t Current_Host_Receive_Buffer_Address; /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
103260  volatile uint32_t HW_Feature; /* ALT_EMAC_DMA_HW_FEATURE */
103261 };
103262 
103263 /* The typedef declaration for the raw register contents of register group ALT_EMAC_DMA. */
103264 typedef volatile struct ALT_EMAC_DMA_raw_s ALT_EMAC_DMA_raw_t;
103265 #endif /* __ASSEMBLY__ */
103266 
103267 
103268 #ifndef __ASSEMBLY__
103269 /*
103270  * WARNING: The C register and register group struct declarations are provided for
103271  * convenience and illustrative purposes. They should, however, be used with
103272  * caution as the C language standard provides no guarantees about the alignment or
103273  * atomicity of device memory accesses. The recommended practice for writing
103274  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
103275  * alt_write_word() functions.
103276  *
103277  * The struct declaration for register group ALT_EMAC.
103278  */
103279 struct ALT_EMAC_s
103280 {
103281  ALT_EMAC_GMAC_t gmacgrp; /* ALT_EMAC_GMAC */
103282  volatile uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */
103283  ALT_EMAC_DMA_t dmagrp; /* ALT_EMAC_DMA */
103284  volatile uint32_t _pad_0x105c_0x2000[1001]; /* *UNDEFINED* */
103285 };
103286 
103287 /* The typedef declaration for register group ALT_EMAC. */
103288 typedef volatile struct ALT_EMAC_s ALT_EMAC_t;
103289 /* The struct declaration for the raw register contents of register group ALT_EMAC. */
103290 struct ALT_EMAC_raw_s
103291 {
103292  ALT_EMAC_GMAC_raw_t gmacgrp; /* ALT_EMAC_GMAC */
103293  uint32_t _pad_0xb80_0xfff[288]; /* *UNDEFINED* */
103294  ALT_EMAC_DMA_raw_t dmagrp; /* ALT_EMAC_DMA */
103295  uint32_t _pad_0x105c_0x2000[1001]; /* *UNDEFINED* */
103296 };
103297 
103298 /* The typedef declaration for the raw register contents of register group ALT_EMAC. */
103299 typedef volatile struct ALT_EMAC_raw_s ALT_EMAC_raw_t;
103300 #endif /* __ASSEMBLY__ */
103301 
103302 
103303 #ifdef __cplusplus
103304 }
103305 #endif /* __cplusplus */
103306 #endif /* __ALTERA_ALT_EMAC_H__ */
103307