Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_noc_fw_ocram_scr.h
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32 
33 /* Altera - ALT_NOC_FW_OCRAM_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_OCRAM_SCR
50  *
51  */
52 /*
53  * Register : enable
54  *
55  * Enable
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :-------|:-------|:--------|:-------------------------------
61  * [0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG0EN
62  * [1] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG1EN
63  * [2] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG2EN
64  * [3] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG3EN
65  * [4] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG4EN
66  * [5] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_REG5EN
67  * [31:6] | ??? | Unknown | *UNDEFINED*
68  *
69  */
70 /*
71  * Field : region0enable
72  *
73  * Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is
74  * disabled
75  *
76  * Field Access Macros:
77  *
78  */
79 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field. */
80 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_LSB 0
81 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field. */
82 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_MSB 0
83 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field. */
84 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_WIDTH 1
85 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field value. */
86 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_SET_MSK 0x00000001
87 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field value. */
88 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_CLR_MSK 0xfffffffe
89 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field. */
90 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_RESET 0x0
91 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG0EN field value from a register. */
92 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
93 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG0EN register field value suitable for setting the register. */
94 #define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_SET(value) (((value) << 0) & 0x00000001)
95 
96 /*
97  * Field : region1enable
98  *
99  * Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is
100  * disabled
101  *
102  * Field Access Macros:
103  *
104  */
105 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field. */
106 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_LSB 1
107 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field. */
108 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_MSB 1
109 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field. */
110 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_WIDTH 1
111 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field value. */
112 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_SET_MSK 0x00000002
113 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field value. */
114 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_CLR_MSK 0xfffffffd
115 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field. */
116 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_RESET 0x0
117 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG1EN field value from a register. */
118 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
119 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG1EN register field value suitable for setting the register. */
120 #define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_SET(value) (((value) << 1) & 0x00000002)
121 
122 /*
123  * Field : region2enable
124  *
125  * Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is
126  * disabled
127  *
128  * Field Access Macros:
129  *
130  */
131 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field. */
132 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_LSB 2
133 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field. */
134 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_MSB 2
135 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field. */
136 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_WIDTH 1
137 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field value. */
138 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_SET_MSK 0x00000004
139 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field value. */
140 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_CLR_MSK 0xfffffffb
141 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field. */
142 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_RESET 0x0
143 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG2EN field value from a register. */
144 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
145 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG2EN register field value suitable for setting the register. */
146 #define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_SET(value) (((value) << 2) & 0x00000004)
147 
148 /*
149  * Field : region3enable
150  *
151  * Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is
152  * disabled
153  *
154  * Field Access Macros:
155  *
156  */
157 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field. */
158 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_LSB 3
159 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field. */
160 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_MSB 3
161 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field. */
162 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_WIDTH 1
163 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field value. */
164 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_SET_MSK 0x00000008
165 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field value. */
166 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_CLR_MSK 0xfffffff7
167 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field. */
168 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_RESET 0x0
169 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG3EN field value from a register. */
170 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
171 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG3EN register field value suitable for setting the register. */
172 #define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_SET(value) (((value) << 3) & 0x00000008)
173 
174 /*
175  * Field : region4enable
176  *
177  * Region 4 Enable. Value of 1 means region is enabled, Value of 0 means region is
178  * disabled
179  *
180  * Field Access Macros:
181  *
182  */
183 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field. */
184 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_LSB 4
185 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field. */
186 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_MSB 4
187 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field. */
188 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_WIDTH 1
189 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field value. */
190 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_SET_MSK 0x00000010
191 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field value. */
192 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_CLR_MSK 0xffffffef
193 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field. */
194 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_RESET 0x0
195 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG4EN field value from a register. */
196 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
197 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG4EN register field value suitable for setting the register. */
198 #define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_SET(value) (((value) << 4) & 0x00000010)
199 
200 /*
201  * Field : region5enable
202  *
203  * Region 5 Enable. Value of 1 means region is enabled, Value of 0 means region is
204  * disabled
205  *
206  * Field Access Macros:
207  *
208  */
209 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field. */
210 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_LSB 5
211 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field. */
212 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_MSB 5
213 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field. */
214 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_WIDTH 1
215 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field value. */
216 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_SET_MSK 0x00000020
217 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field value. */
218 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_CLR_MSK 0xffffffdf
219 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field. */
220 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_RESET 0x0
221 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_REG5EN field value from a register. */
222 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
223 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_REG5EN register field value suitable for setting the register. */
224 #define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_SET(value) (((value) << 5) & 0x00000020)
225 
226 #ifndef __ASSEMBLY__
227 /*
228  * WARNING: The C register and register group struct declarations are provided for
229  * convenience and illustrative purposes. They should, however, be used with
230  * caution as the C language standard provides no guarantees about the alignment or
231  * atomicity of device memory accesses. The recommended practice for writing
232  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
233  * alt_write_word() functions.
234  *
235  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_EN.
236  */
237 struct ALT_NOC_FW_OCRAM_SCR_EN_s
238 {
239  uint32_t region0enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG0EN */
240  uint32_t region1enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG1EN */
241  uint32_t region2enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG2EN */
242  uint32_t region3enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG3EN */
243  uint32_t region4enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG4EN */
244  uint32_t region5enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_REG5EN */
245  uint32_t : 26; /* *UNDEFINED* */
246 };
247 
248 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_EN. */
249 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_EN_s ALT_NOC_FW_OCRAM_SCR_EN_t;
250 #endif /* __ASSEMBLY__ */
251 
252 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN register. */
253 #define ALT_NOC_FW_OCRAM_SCR_EN_RESET 0x00000000
254 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_EN register from the beginning of the component. */
255 #define ALT_NOC_FW_OCRAM_SCR_EN_OFST 0x0
256 
257 /*
258  * Register : enable_set
259  *
260  * Sets Region Enable field when written with 1
261  *
262  * Register Layout
263  *
264  * Bits | Access | Reset | Description
265  * :-------|:-------|:--------|:-----------------------------------
266  * [0] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN
267  * [1] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN
268  * [2] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN
269  * [3] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN
270  * [4] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN
271  * [5] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN
272  * [31:6] | ??? | Unknown | *UNDEFINED*
273  *
274  */
275 /*
276  * Field : region0enable
277  *
278  * Region 0 Enable Set
279  *
280  * Writing zero has no effect
281  *
282  * Writing one will set the region0enable bit to one
283  *
284  * Field Access Macros:
285  *
286  */
287 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field. */
288 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_LSB 0
289 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field. */
290 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_MSB 0
291 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field. */
292 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_WIDTH 1
293 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field value. */
294 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_SET_MSK 0x00000001
295 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field value. */
296 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_CLR_MSK 0xfffffffe
297 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field. */
298 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_RESET 0x0
299 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN field value from a register. */
300 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
301 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN register field value suitable for setting the register. */
302 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_SET(value) (((value) << 0) & 0x00000001)
303 
304 /*
305  * Field : region1enable
306  *
307  * Region 1 Enable Set
308  *
309  * Writing zero has no effect
310  *
311  * Writing one will set the region1enable bit to one
312  *
313  * Field Access Macros:
314  *
315  */
316 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field. */
317 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_LSB 1
318 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field. */
319 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_MSB 1
320 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field. */
321 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_WIDTH 1
322 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field value. */
323 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_SET_MSK 0x00000002
324 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field value. */
325 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_CLR_MSK 0xfffffffd
326 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field. */
327 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_RESET 0x0
328 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN field value from a register. */
329 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
330 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN register field value suitable for setting the register. */
331 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_SET(value) (((value) << 1) & 0x00000002)
332 
333 /*
334  * Field : region2enable
335  *
336  * Region 2 Enable Set
337  *
338  * Writing zero has no effect
339  *
340  * Writing one will set the region2enable bit to one
341  *
342  * Field Access Macros:
343  *
344  */
345 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field. */
346 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_LSB 2
347 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field. */
348 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_MSB 2
349 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field. */
350 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_WIDTH 1
351 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field value. */
352 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_SET_MSK 0x00000004
353 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field value. */
354 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_CLR_MSK 0xfffffffb
355 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field. */
356 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_RESET 0x0
357 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN field value from a register. */
358 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
359 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN register field value suitable for setting the register. */
360 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_SET(value) (((value) << 2) & 0x00000004)
361 
362 /*
363  * Field : region3enable
364  *
365  * Region 3 Enable Set
366  *
367  * Writing zero has no effect
368  *
369  * Writing one will set the region3enable bit to one
370  *
371  * Field Access Macros:
372  *
373  */
374 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field. */
375 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_LSB 3
376 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field. */
377 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_MSB 3
378 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field. */
379 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_WIDTH 1
380 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field value. */
381 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_SET_MSK 0x00000008
382 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field value. */
383 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_CLR_MSK 0xfffffff7
384 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field. */
385 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_RESET 0x0
386 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN field value from a register. */
387 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
388 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN register field value suitable for setting the register. */
389 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_SET(value) (((value) << 3) & 0x00000008)
390 
391 /*
392  * Field : region4enable
393  *
394  * Region 4 Enable Set
395  *
396  * Writing zero has no effect
397  *
398  * Writing one will set the region4enable bit to one
399  *
400  * Field Access Macros:
401  *
402  */
403 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field. */
404 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_LSB 4
405 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field. */
406 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_MSB 4
407 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field. */
408 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_WIDTH 1
409 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field value. */
410 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_SET_MSK 0x00000010
411 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field value. */
412 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_CLR_MSK 0xffffffef
413 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field. */
414 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_RESET 0x0
415 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN field value from a register. */
416 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
417 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN register field value suitable for setting the register. */
418 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_SET(value) (((value) << 4) & 0x00000010)
419 
420 /*
421  * Field : region5enable
422  *
423  * Region 5 Enable Set
424  *
425  * Writing zero has no effect
426  *
427  * Writing one will set the region5enable bit to one
428  *
429  * Field Access Macros:
430  *
431  */
432 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field. */
433 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_LSB 5
434 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field. */
435 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_MSB 5
436 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field. */
437 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_WIDTH 1
438 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field value. */
439 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_SET_MSK 0x00000020
440 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field value. */
441 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_CLR_MSK 0xffffffdf
442 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field. */
443 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_RESET 0x0
444 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN field value from a register. */
445 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
446 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN register field value suitable for setting the register. */
447 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_SET(value) (((value) << 5) & 0x00000020)
448 
449 #ifndef __ASSEMBLY__
450 /*
451  * WARNING: The C register and register group struct declarations are provided for
452  * convenience and illustrative purposes. They should, however, be used with
453  * caution as the C language standard provides no guarantees about the alignment or
454  * atomicity of device memory accesses. The recommended practice for writing
455  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
456  * alt_write_word() functions.
457  *
458  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_EN_SET.
459  */
460 struct ALT_NOC_FW_OCRAM_SCR_EN_SET_s
461 {
462  uint32_t region0enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN */
463  uint32_t region1enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN */
464  uint32_t region2enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN */
465  uint32_t region3enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN */
466  uint32_t region4enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN */
467  uint32_t region5enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN */
468  uint32_t : 26; /* *UNDEFINED* */
469 };
470 
471 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_EN_SET. */
472 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_EN_SET_s ALT_NOC_FW_OCRAM_SCR_EN_SET_t;
473 #endif /* __ASSEMBLY__ */
474 
475 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_SET register. */
476 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_RESET 0x00000000
477 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_EN_SET register from the beginning of the component. */
478 #define ALT_NOC_FW_OCRAM_SCR_EN_SET_OFST 0x4
479 
480 /*
481  * Register : enable_clear
482  *
483  * Clears Region Enable field when written with 1
484  *
485  * Register Layout
486  *
487  * Bits | Access | Reset | Description
488  * :-------|:-------|:--------|:-----------------------------------
489  * [0] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN
490  * [1] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN
491  * [2] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN
492  * [3] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN
493  * [4] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN
494  * [5] | W | 0x0 | ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN
495  * [31:6] | ??? | Unknown | *UNDEFINED*
496  *
497  */
498 /*
499  * Field : region0enable
500  *
501  * Region 0 Enable Clear
502  *
503  * Writing zero has no effect
504  *
505  * Writing one will clear the region0enable bit to zero
506  *
507  * Field Access Macros:
508  *
509  */
510 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field. */
511 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_LSB 0
512 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field. */
513 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_MSB 0
514 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field. */
515 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_WIDTH 1
516 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field value. */
517 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_SET_MSK 0x00000001
518 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field value. */
519 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_CLR_MSK 0xfffffffe
520 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field. */
521 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_RESET 0x0
522 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN field value from a register. */
523 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
524 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN register field value suitable for setting the register. */
525 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_SET(value) (((value) << 0) & 0x00000001)
526 
527 /*
528  * Field : region1enable
529  *
530  * Region 1 Enable Clear
531  *
532  * Writing zero has no effect
533  *
534  * Writing one will clear the region1enable bit to zero
535  *
536  * Field Access Macros:
537  *
538  */
539 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field. */
540 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_LSB 1
541 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field. */
542 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_MSB 1
543 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field. */
544 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_WIDTH 1
545 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field value. */
546 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_SET_MSK 0x00000002
547 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field value. */
548 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_CLR_MSK 0xfffffffd
549 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field. */
550 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_RESET 0x0
551 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN field value from a register. */
552 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
553 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN register field value suitable for setting the register. */
554 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_SET(value) (((value) << 1) & 0x00000002)
555 
556 /*
557  * Field : region2enable
558  *
559  * Region 2 Enable Clear
560  *
561  * Writing zero has no effect
562  *
563  * Writing one will clear the region2enable bit to zero
564  *
565  * Field Access Macros:
566  *
567  */
568 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field. */
569 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_LSB 2
570 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field. */
571 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_MSB 2
572 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field. */
573 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_WIDTH 1
574 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field value. */
575 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_SET_MSK 0x00000004
576 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field value. */
577 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_CLR_MSK 0xfffffffb
578 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field. */
579 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_RESET 0x0
580 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN field value from a register. */
581 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
582 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN register field value suitable for setting the register. */
583 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_SET(value) (((value) << 2) & 0x00000004)
584 
585 /*
586  * Field : region3enable
587  *
588  * Region 3 Enable Clear
589  *
590  * Writing zero has no effect
591  *
592  * Writing one will clear the region3enable bit to zero
593  *
594  * Field Access Macros:
595  *
596  */
597 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field. */
598 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_LSB 3
599 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field. */
600 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_MSB 3
601 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field. */
602 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_WIDTH 1
603 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field value. */
604 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_SET_MSK 0x00000008
605 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field value. */
606 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_CLR_MSK 0xfffffff7
607 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field. */
608 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_RESET 0x0
609 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN field value from a register. */
610 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
611 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN register field value suitable for setting the register. */
612 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_SET(value) (((value) << 3) & 0x00000008)
613 
614 /*
615  * Field : region4enable
616  *
617  * Region 4 Enable Clear
618  *
619  * Writing zero has no effect
620  *
621  * Writing one will clear the region4enable bit to zero
622  *
623  * Field Access Macros:
624  *
625  */
626 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field. */
627 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_LSB 4
628 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field. */
629 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_MSB 4
630 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field. */
631 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_WIDTH 1
632 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field value. */
633 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_SET_MSK 0x00000010
634 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field value. */
635 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_CLR_MSK 0xffffffef
636 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field. */
637 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_RESET 0x0
638 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN field value from a register. */
639 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
640 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN register field value suitable for setting the register. */
641 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_SET(value) (((value) << 4) & 0x00000010)
642 
643 /*
644  * Field : region5enable
645  *
646  * Region 5 Enable Clear
647  *
648  * Writing zero has no effect
649  *
650  * Writing one will clear the region5enable bit to zero
651  *
652  * Field Access Macros:
653  *
654  */
655 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field. */
656 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_LSB 5
657 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field. */
658 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_MSB 5
659 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field. */
660 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_WIDTH 1
661 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field value. */
662 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_SET_MSK 0x00000020
663 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field value. */
664 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_CLR_MSK 0xffffffdf
665 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field. */
666 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_RESET 0x0
667 /* Extracts the ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN field value from a register. */
668 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
669 /* Produces a ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN register field value suitable for setting the register. */
670 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_SET(value) (((value) << 5) & 0x00000020)
671 
672 #ifndef __ASSEMBLY__
673 /*
674  * WARNING: The C register and register group struct declarations are provided for
675  * convenience and illustrative purposes. They should, however, be used with
676  * caution as the C language standard provides no guarantees about the alignment or
677  * atomicity of device memory accesses. The recommended practice for writing
678  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
679  * alt_write_word() functions.
680  *
681  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_EN_CLR.
682  */
683 struct ALT_NOC_FW_OCRAM_SCR_EN_CLR_s
684 {
685  uint32_t region0enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN */
686  uint32_t region1enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN */
687  uint32_t region2enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN */
688  uint32_t region3enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN */
689  uint32_t region4enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN */
690  uint32_t region5enable : 1; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN */
691  uint32_t : 26; /* *UNDEFINED* */
692 };
693 
694 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_EN_CLR. */
695 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_EN_CLR_s ALT_NOC_FW_OCRAM_SCR_EN_CLR_t;
696 #endif /* __ASSEMBLY__ */
697 
698 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_EN_CLR register. */
699 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_RESET 0x00000000
700 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_EN_CLR register from the beginning of the component. */
701 #define ALT_NOC_FW_OCRAM_SCR_EN_CLR_OFST 0x8
702 
703 /*
704  * Register : region0addr
705  *
706  * Base and Limit definition for Region 0
707  *
708  * Register Layout
709  *
710  * Bits | Access | Reset | Description
711  * :--------|:-------|:--------|:------------------------------------
712  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE
713  * [15:6] | ??? | Unknown | *UNDEFINED*
714  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT
715  * [31:22] | ??? | Unknown | *UNDEFINED*
716  *
717  */
718 /*
719  * Field : base
720  *
721  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
722  * zeros. Region start address is {base, 12'h000}
723  *
724  * Field Access Macros:
725  *
726  */
727 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field. */
728 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_LSB 0
729 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field. */
730 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_MSB 5
731 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field. */
732 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_WIDTH 6
733 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field value. */
734 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_SET_MSK 0x0000003f
735 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field value. */
736 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_CLR_MSK 0xffffffc0
737 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field. */
738 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_RESET 0x0
739 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE field value from a register. */
740 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
741 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE register field value suitable for setting the register. */
742 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
743 
744 /*
745  * Field : limit
746  *
747  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
748  * ones. Region end address is {limit, 12'hFFF}
749  *
750  * Field Access Macros:
751  *
752  */
753 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field. */
754 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_LSB 16
755 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field. */
756 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_MSB 21
757 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field. */
758 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_WIDTH 6
759 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field value. */
760 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_SET_MSK 0x003f0000
761 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field value. */
762 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_CLR_MSK 0xffc0ffff
763 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field. */
764 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_RESET 0x0
765 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT field value from a register. */
766 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
767 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT register field value suitable for setting the register. */
768 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
769 
770 #ifndef __ASSEMBLY__
771 /*
772  * WARNING: The C register and register group struct declarations are provided for
773  * convenience and illustrative purposes. They should, however, be used with
774  * caution as the C language standard provides no guarantees about the alignment or
775  * atomicity of device memory accesses. The recommended practice for writing
776  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
777  * alt_write_word() functions.
778  *
779  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG0ADDR.
780  */
781 struct ALT_NOC_FW_OCRAM_SCR_REG0ADDR_s
782 {
783  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE */
784  uint32_t : 10; /* *UNDEFINED* */
785  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT */
786  uint32_t : 10; /* *UNDEFINED* */
787 };
788 
789 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG0ADDR. */
790 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG0ADDR_s ALT_NOC_FW_OCRAM_SCR_REG0ADDR_t;
791 #endif /* __ASSEMBLY__ */
792 
793 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR register. */
794 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_RESET 0x00000000
795 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG0ADDR register from the beginning of the component. */
796 #define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_OFST 0xc
797 
798 /*
799  * Register : region1addr
800  *
801  * Base and Limit definition for Region 1
802  *
803  * Register Layout
804  *
805  * Bits | Access | Reset | Description
806  * :--------|:-------|:--------|:------------------------------------
807  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE
808  * [15:6] | ??? | Unknown | *UNDEFINED*
809  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT
810  * [31:22] | ??? | Unknown | *UNDEFINED*
811  *
812  */
813 /*
814  * Field : base
815  *
816  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
817  * zeros. Region start address is {base, 12'h000}
818  *
819  * Field Access Macros:
820  *
821  */
822 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field. */
823 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_LSB 0
824 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field. */
825 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_MSB 5
826 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field. */
827 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_WIDTH 6
828 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field value. */
829 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_SET_MSK 0x0000003f
830 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field value. */
831 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_CLR_MSK 0xffffffc0
832 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field. */
833 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_RESET 0x0
834 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE field value from a register. */
835 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
836 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE register field value suitable for setting the register. */
837 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
838 
839 /*
840  * Field : limit
841  *
842  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
843  * ones. Region end address is {limit, 12'hFFF}
844  *
845  * Field Access Macros:
846  *
847  */
848 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field. */
849 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_LSB 16
850 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field. */
851 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_MSB 21
852 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field. */
853 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_WIDTH 6
854 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field value. */
855 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_SET_MSK 0x003f0000
856 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field value. */
857 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_CLR_MSK 0xffc0ffff
858 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field. */
859 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_RESET 0x0
860 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT field value from a register. */
861 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
862 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT register field value suitable for setting the register. */
863 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
864 
865 #ifndef __ASSEMBLY__
866 /*
867  * WARNING: The C register and register group struct declarations are provided for
868  * convenience and illustrative purposes. They should, however, be used with
869  * caution as the C language standard provides no guarantees about the alignment or
870  * atomicity of device memory accesses. The recommended practice for writing
871  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
872  * alt_write_word() functions.
873  *
874  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG1ADDR.
875  */
876 struct ALT_NOC_FW_OCRAM_SCR_REG1ADDR_s
877 {
878  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE */
879  uint32_t : 10; /* *UNDEFINED* */
880  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT */
881  uint32_t : 10; /* *UNDEFINED* */
882 };
883 
884 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG1ADDR. */
885 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG1ADDR_s ALT_NOC_FW_OCRAM_SCR_REG1ADDR_t;
886 #endif /* __ASSEMBLY__ */
887 
888 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR register. */
889 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_RESET 0x00000000
890 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG1ADDR register from the beginning of the component. */
891 #define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_OFST 0x10
892 
893 /*
894  * Register : region2addr
895  *
896  * Base and Limit definition for Region 2
897  *
898  * Register Layout
899  *
900  * Bits | Access | Reset | Description
901  * :--------|:-------|:--------|:------------------------------------
902  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE
903  * [15:6] | ??? | Unknown | *UNDEFINED*
904  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT
905  * [31:22] | ??? | Unknown | *UNDEFINED*
906  *
907  */
908 /*
909  * Field : base
910  *
911  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
912  * zeros. Region start address is {base, 12'h000}
913  *
914  * Field Access Macros:
915  *
916  */
917 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field. */
918 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_LSB 0
919 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field. */
920 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_MSB 5
921 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field. */
922 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_WIDTH 6
923 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field value. */
924 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_SET_MSK 0x0000003f
925 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field value. */
926 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_CLR_MSK 0xffffffc0
927 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field. */
928 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_RESET 0x0
929 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE field value from a register. */
930 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
931 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE register field value suitable for setting the register. */
932 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
933 
934 /*
935  * Field : limit
936  *
937  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
938  * ones. Region end address is {limit, 12'hFFF}
939  *
940  * Field Access Macros:
941  *
942  */
943 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field. */
944 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_LSB 16
945 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field. */
946 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_MSB 21
947 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field. */
948 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_WIDTH 6
949 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field value. */
950 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_SET_MSK 0x003f0000
951 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field value. */
952 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_CLR_MSK 0xffc0ffff
953 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field. */
954 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_RESET 0x0
955 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT field value from a register. */
956 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
957 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT register field value suitable for setting the register. */
958 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
959 
960 #ifndef __ASSEMBLY__
961 /*
962  * WARNING: The C register and register group struct declarations are provided for
963  * convenience and illustrative purposes. They should, however, be used with
964  * caution as the C language standard provides no guarantees about the alignment or
965  * atomicity of device memory accesses. The recommended practice for writing
966  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
967  * alt_write_word() functions.
968  *
969  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG2ADDR.
970  */
971 struct ALT_NOC_FW_OCRAM_SCR_REG2ADDR_s
972 {
973  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE */
974  uint32_t : 10; /* *UNDEFINED* */
975  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT */
976  uint32_t : 10; /* *UNDEFINED* */
977 };
978 
979 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG2ADDR. */
980 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG2ADDR_s ALT_NOC_FW_OCRAM_SCR_REG2ADDR_t;
981 #endif /* __ASSEMBLY__ */
982 
983 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR register. */
984 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_RESET 0x00000000
985 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG2ADDR register from the beginning of the component. */
986 #define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_OFST 0x14
987 
988 /*
989  * Register : region3addr
990  *
991  * Base and Limit definition for Region 3
992  *
993  * Register Layout
994  *
995  * Bits | Access | Reset | Description
996  * :--------|:-------|:--------|:------------------------------------
997  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE
998  * [15:6] | ??? | Unknown | *UNDEFINED*
999  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT
1000  * [31:22] | ??? | Unknown | *UNDEFINED*
1001  *
1002  */
1003 /*
1004  * Field : base
1005  *
1006  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
1007  * zeros. Region start address is {base, 12'h000}
1008  *
1009  * Field Access Macros:
1010  *
1011  */
1012 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field. */
1013 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_LSB 0
1014 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field. */
1015 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_MSB 5
1016 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field. */
1017 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_WIDTH 6
1018 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field value. */
1019 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_SET_MSK 0x0000003f
1020 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field value. */
1021 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_CLR_MSK 0xffffffc0
1022 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field. */
1023 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_RESET 0x0
1024 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE field value from a register. */
1025 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1026 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE register field value suitable for setting the register. */
1027 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1028 
1029 /*
1030  * Field : limit
1031  *
1032  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
1033  * ones. Region end address is {limit, 12'hFFF}
1034  *
1035  * Field Access Macros:
1036  *
1037  */
1038 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field. */
1039 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_LSB 16
1040 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field. */
1041 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_MSB 21
1042 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field. */
1043 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_WIDTH 6
1044 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field value. */
1045 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_SET_MSK 0x003f0000
1046 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field value. */
1047 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_CLR_MSK 0xffc0ffff
1048 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field. */
1049 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_RESET 0x0
1050 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT field value from a register. */
1051 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1052 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT register field value suitable for setting the register. */
1053 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1054 
1055 #ifndef __ASSEMBLY__
1056 /*
1057  * WARNING: The C register and register group struct declarations are provided for
1058  * convenience and illustrative purposes. They should, however, be used with
1059  * caution as the C language standard provides no guarantees about the alignment or
1060  * atomicity of device memory accesses. The recommended practice for writing
1061  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1062  * alt_write_word() functions.
1063  *
1064  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG3ADDR.
1065  */
1066 struct ALT_NOC_FW_OCRAM_SCR_REG3ADDR_s
1067 {
1068  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE */
1069  uint32_t : 10; /* *UNDEFINED* */
1070  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT */
1071  uint32_t : 10; /* *UNDEFINED* */
1072 };
1073 
1074 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG3ADDR. */
1075 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG3ADDR_s ALT_NOC_FW_OCRAM_SCR_REG3ADDR_t;
1076 #endif /* __ASSEMBLY__ */
1077 
1078 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR register. */
1079 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_RESET 0x00000000
1080 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG3ADDR register from the beginning of the component. */
1081 #define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_OFST 0x18
1082 
1083 /*
1084  * Register : region4addr
1085  *
1086  * Base and Limit definition for Region 4
1087  *
1088  * Register Layout
1089  *
1090  * Bits | Access | Reset | Description
1091  * :--------|:-------|:--------|:------------------------------------
1092  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE
1093  * [15:6] | ??? | Unknown | *UNDEFINED*
1094  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT
1095  * [31:22] | ??? | Unknown | *UNDEFINED*
1096  *
1097  */
1098 /*
1099  * Field : base
1100  *
1101  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
1102  * zeros. Region start address is {base, 12'h000}
1103  *
1104  * Field Access Macros:
1105  *
1106  */
1107 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field. */
1108 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_LSB 0
1109 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field. */
1110 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_MSB 5
1111 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field. */
1112 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_WIDTH 6
1113 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field value. */
1114 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_SET_MSK 0x0000003f
1115 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field value. */
1116 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_CLR_MSK 0xffffffc0
1117 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field. */
1118 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_RESET 0x0
1119 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE field value from a register. */
1120 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1121 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE register field value suitable for setting the register. */
1122 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1123 
1124 /*
1125  * Field : limit
1126  *
1127  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
1128  * ones. Region end address is {limit, 12'hFFF}
1129  *
1130  * Field Access Macros:
1131  *
1132  */
1133 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field. */
1134 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_LSB 16
1135 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field. */
1136 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_MSB 21
1137 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field. */
1138 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_WIDTH 6
1139 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field value. */
1140 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_SET_MSK 0x003f0000
1141 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field value. */
1142 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_CLR_MSK 0xffc0ffff
1143 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field. */
1144 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_RESET 0x0
1145 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT field value from a register. */
1146 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1147 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT register field value suitable for setting the register. */
1148 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1149 
1150 #ifndef __ASSEMBLY__
1151 /*
1152  * WARNING: The C register and register group struct declarations are provided for
1153  * convenience and illustrative purposes. They should, however, be used with
1154  * caution as the C language standard provides no guarantees about the alignment or
1155  * atomicity of device memory accesses. The recommended practice for writing
1156  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1157  * alt_write_word() functions.
1158  *
1159  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG4ADDR.
1160  */
1161 struct ALT_NOC_FW_OCRAM_SCR_REG4ADDR_s
1162 {
1163  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE */
1164  uint32_t : 10; /* *UNDEFINED* */
1165  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT */
1166  uint32_t : 10; /* *UNDEFINED* */
1167 };
1168 
1169 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG4ADDR. */
1170 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG4ADDR_s ALT_NOC_FW_OCRAM_SCR_REG4ADDR_t;
1171 #endif /* __ASSEMBLY__ */
1172 
1173 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR register. */
1174 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_RESET 0x00000000
1175 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG4ADDR register from the beginning of the component. */
1176 #define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_OFST 0x1c
1177 
1178 /*
1179  * Register : region5addr
1180  *
1181  * Base and Limit definition for Region 5
1182  *
1183  * Register Layout
1184  *
1185  * Bits | Access | Reset | Description
1186  * :--------|:-------|:--------|:------------------------------------
1187  * [5:0] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE
1188  * [15:6] | ??? | Unknown | *UNDEFINED*
1189  * [21:16] | RW | 0x0 | ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT
1190  * [31:22] | ??? | Unknown | *UNDEFINED*
1191  *
1192  */
1193 /*
1194  * Field : base
1195  *
1196  * Base defines the 6 bit MSB of the address field. Remaining LSB field is all
1197  * zeros. Region start address is {base, 12'h000}
1198  *
1199  * Field Access Macros:
1200  *
1201  */
1202 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field. */
1203 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_LSB 0
1204 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field. */
1205 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_MSB 5
1206 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field. */
1207 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_WIDTH 6
1208 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field value. */
1209 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_SET_MSK 0x0000003f
1210 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field value. */
1211 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_CLR_MSK 0xffffffc0
1212 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field. */
1213 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_RESET 0x0
1214 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE field value from a register. */
1215 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1216 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE register field value suitable for setting the register. */
1217 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1218 
1219 /*
1220  * Field : limit
1221  *
1222  * Limit defines the 6 bit MSB of the address field. Remaining LSB field is all
1223  * ones. Region end address is {limit, 12'hFFF}
1224  *
1225  * Field Access Macros:
1226  *
1227  */
1228 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field. */
1229 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_LSB 16
1230 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field. */
1231 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_MSB 21
1232 /* The width in bits of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field. */
1233 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_WIDTH 6
1234 /* The mask used to set the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field value. */
1235 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_SET_MSK 0x003f0000
1236 /* The mask used to clear the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field value. */
1237 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_CLR_MSK 0xffc0ffff
1238 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field. */
1239 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_RESET 0x0
1240 /* Extracts the ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT field value from a register. */
1241 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1242 /* Produces a ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT register field value suitable for setting the register. */
1243 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1244 
1245 #ifndef __ASSEMBLY__
1246 /*
1247  * WARNING: The C register and register group struct declarations are provided for
1248  * convenience and illustrative purposes. They should, however, be used with
1249  * caution as the C language standard provides no guarantees about the alignment or
1250  * atomicity of device memory accesses. The recommended practice for writing
1251  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1252  * alt_write_word() functions.
1253  *
1254  * The struct declaration for register ALT_NOC_FW_OCRAM_SCR_REG5ADDR.
1255  */
1256 struct ALT_NOC_FW_OCRAM_SCR_REG5ADDR_s
1257 {
1258  uint32_t base : 6; /* ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE */
1259  uint32_t : 10; /* *UNDEFINED* */
1260  uint32_t limit : 6; /* ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT */
1261  uint32_t : 10; /* *UNDEFINED* */
1262 };
1263 
1264 /* The typedef declaration for register ALT_NOC_FW_OCRAM_SCR_REG5ADDR. */
1265 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_REG5ADDR_s ALT_NOC_FW_OCRAM_SCR_REG5ADDR_t;
1266 #endif /* __ASSEMBLY__ */
1267 
1268 /* The reset value of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR register. */
1269 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_RESET 0x00000000
1270 /* The byte offset of the ALT_NOC_FW_OCRAM_SCR_REG5ADDR register from the beginning of the component. */
1271 #define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_OFST 0x20
1272 
1273 #ifndef __ASSEMBLY__
1274 /*
1275  * WARNING: The C register and register group struct declarations are provided for
1276  * convenience and illustrative purposes. They should, however, be used with
1277  * caution as the C language standard provides no guarantees about the alignment or
1278  * atomicity of device memory accesses. The recommended practice for writing
1279  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1280  * alt_write_word() functions.
1281  *
1282  * The struct declaration for register group ALT_NOC_FW_OCRAM_SCR.
1283  */
1284 struct ALT_NOC_FW_OCRAM_SCR_s
1285 {
1286  ALT_NOC_FW_OCRAM_SCR_EN_t enable; /* ALT_NOC_FW_OCRAM_SCR_EN */
1287  ALT_NOC_FW_OCRAM_SCR_EN_SET_t enable_set; /* ALT_NOC_FW_OCRAM_SCR_EN_SET */
1288  ALT_NOC_FW_OCRAM_SCR_EN_CLR_t enable_clear; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR */
1289  ALT_NOC_FW_OCRAM_SCR_REG0ADDR_t region0addr; /* ALT_NOC_FW_OCRAM_SCR_REG0ADDR */
1290  ALT_NOC_FW_OCRAM_SCR_REG1ADDR_t region1addr; /* ALT_NOC_FW_OCRAM_SCR_REG1ADDR */
1291  ALT_NOC_FW_OCRAM_SCR_REG2ADDR_t region2addr; /* ALT_NOC_FW_OCRAM_SCR_REG2ADDR */
1292  ALT_NOC_FW_OCRAM_SCR_REG3ADDR_t region3addr; /* ALT_NOC_FW_OCRAM_SCR_REG3ADDR */
1293  ALT_NOC_FW_OCRAM_SCR_REG4ADDR_t region4addr; /* ALT_NOC_FW_OCRAM_SCR_REG4ADDR */
1294  ALT_NOC_FW_OCRAM_SCR_REG5ADDR_t region5addr; /* ALT_NOC_FW_OCRAM_SCR_REG5ADDR */
1295  volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */
1296 };
1297 
1298 /* The typedef declaration for register group ALT_NOC_FW_OCRAM_SCR. */
1299 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_s ALT_NOC_FW_OCRAM_SCR_t;
1300 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_OCRAM_SCR. */
1301 struct ALT_NOC_FW_OCRAM_SCR_raw_s
1302 {
1303  volatile uint32_t enable; /* ALT_NOC_FW_OCRAM_SCR_EN */
1304  volatile uint32_t enable_set; /* ALT_NOC_FW_OCRAM_SCR_EN_SET */
1305  volatile uint32_t enable_clear; /* ALT_NOC_FW_OCRAM_SCR_EN_CLR */
1306  volatile uint32_t region0addr; /* ALT_NOC_FW_OCRAM_SCR_REG0ADDR */
1307  volatile uint32_t region1addr; /* ALT_NOC_FW_OCRAM_SCR_REG1ADDR */
1308  volatile uint32_t region2addr; /* ALT_NOC_FW_OCRAM_SCR_REG2ADDR */
1309  volatile uint32_t region3addr; /* ALT_NOC_FW_OCRAM_SCR_REG3ADDR */
1310  volatile uint32_t region4addr; /* ALT_NOC_FW_OCRAM_SCR_REG4ADDR */
1311  volatile uint32_t region5addr; /* ALT_NOC_FW_OCRAM_SCR_REG5ADDR */
1312  uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */
1313 };
1314 
1315 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_OCRAM_SCR. */
1316 typedef volatile struct ALT_NOC_FW_OCRAM_SCR_raw_s ALT_NOC_FW_OCRAM_SCR_raw_t;
1317 #endif /* __ASSEMBLY__ */
1318 
1319 
1320 #ifdef __cplusplus
1321 }
1322 #endif /* __cplusplus */
1323 #endif /* __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__ */
1324