Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_io48_hmc_mmr.h
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32 
33 /* Altera - ALT_IO48_HMC_MMR */
34 
35 #ifndef __ALT_SOCAL_IO48_HMC_MMR_H__
36 #define __ALT_SOCAL_IO48_HMC_MMR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_IO48_HMC_MMR
50  *
51  */
52 /*
53  * Register : dbgcfg0
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:------|:----------------------------------------------
59  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL
60  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL
61  * [2] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL
62  * [3] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN
63  * [4] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL
64  * [8:5] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD
65  * [31:9] | ??? | 0x0 | *UNDEFINED*
66  *
67  */
68 /*
69  * Field : cfg_wdata_driver_sel
70  *
71  * TBD
72  *
73  * Field Access Macros:
74  *
75  */
76 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
77 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB 0
78 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
79 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB 0
80 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
81 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH 1
82 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value. */
83 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK 0x00000001
84 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value. */
85 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK 0xfffffffe
86 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field. */
87 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET 0x0
88 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL field value from a register. */
89 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value) (((value) & 0x00000001) >> 0)
90 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value suitable for setting the register. */
91 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value) (((value) << 0) & 0x00000001)
92 
93 /*
94  * Field : cfg_prbs_ctrl_sel
95  *
96  * TBD
97  *
98  * Field Access Macros:
99  *
100  */
101 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field. */
102 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_LSB 1
103 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field. */
104 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_MSB 1
105 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field. */
106 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_WIDTH 1
107 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value. */
108 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET_MSK 0x00000002
109 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value. */
110 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_CLR_MSK 0xfffffffd
111 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field. */
112 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_RESET 0x0
113 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL field value from a register. */
114 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_GET(value) (((value) & 0x00000002) >> 1)
115 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value suitable for setting the register. */
116 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET(value) (((value) << 1) & 0x00000002)
117 
118 /*
119  * Field : cfg_mmr_driver_sel
120  *
121  * TBD
122  *
123  * Field Access Macros:
124  *
125  */
126 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field. */
127 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_LSB 2
128 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field. */
129 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_MSB 2
130 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field. */
131 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_WIDTH 1
132 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value. */
133 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET_MSK 0x00000004
134 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value. */
135 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_CLR_MSK 0xfffffffb
136 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field. */
137 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_RESET 0x0
138 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL field value from a register. */
139 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_GET(value) (((value) & 0x00000004) >> 2)
140 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value suitable for setting the register. */
141 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET(value) (((value) << 2) & 0x00000004)
142 
143 /*
144  * Field : cfg_loopback_en
145  *
146  * TBD
147  *
148  * Field Access Macros:
149  *
150  */
151 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field. */
152 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_LSB 3
153 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field. */
154 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_MSB 3
155 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field. */
156 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_WIDTH 1
157 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value. */
158 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK 0x00000008
159 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value. */
160 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK 0xfffffff7
161 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field. */
162 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_RESET 0x0
163 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN field value from a register. */
164 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_GET(value) (((value) & 0x00000008) >> 3)
165 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value suitable for setting the register. */
166 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET(value) (((value) << 3) & 0x00000008)
167 
168 /*
169  * Field : cfg_cmd_driver_sel
170  *
171  * TBD
172  *
173  * Field Access Macros:
174  *
175  */
176 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
177 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB 4
178 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
179 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB 4
180 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
181 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH 1
182 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value. */
183 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK 0x00000010
184 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value. */
185 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK 0xffffffef
186 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field. */
187 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET 0x0
188 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL field value from a register. */
189 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value) (((value) & 0x00000010) >> 4)
190 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value suitable for setting the register. */
191 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value) (((value) << 4) & 0x00000010)
192 
193 /*
194  * Field : cfg_dbg_mode
195  *
196  * TBD
197  *
198  * Field Access Macros:
199  *
200  */
201 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field. */
202 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_LSB 5
203 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field. */
204 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_MSB 8
205 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field. */
206 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_WIDTH 4
207 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value. */
208 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET_MSK 0x000001e0
209 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value. */
210 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_CLR_MSK 0xfffffe1f
211 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field. */
212 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_RESET 0x0
213 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD field value from a register. */
214 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_GET(value) (((value) & 0x000001e0) >> 5)
215 /* Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value suitable for setting the register. */
216 #define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET(value) (((value) << 5) & 0x000001e0)
217 
218 #ifndef __ASSEMBLY__
219 /*
220  * WARNING: The C register and register group struct declarations are provided for
221  * convenience and illustrative purposes. They should, however, be used with
222  * caution as the C language standard provides no guarantees about the alignment or
223  * atomicity of device memory accesses. The recommended practice for writing
224  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
225  * alt_write_word() functions.
226  *
227  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG0.
228  */
229 struct ALT_IO48_HMC_MMR_DBGCFG0_s
230 {
231  uint32_t cfg_wdata_driver_sel : 1; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL */
232  uint32_t cfg_prbs_ctrl_sel : 1; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL */
233  uint32_t cfg_mmr_driver_sel : 1; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL */
234  uint32_t cfg_loopback_en : 1; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN */
235  uint32_t cfg_cmd_driver_sel : 1; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL */
236  uint32_t cfg_dbg_mode : 4; /* ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD */
237  uint32_t : 23; /* *UNDEFINED* */
238 };
239 
240 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG0. */
241 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG0_s ALT_IO48_HMC_MMR_DBGCFG0_t;
242 #endif /* __ASSEMBLY__ */
243 
244 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG0 register. */
245 #define ALT_IO48_HMC_MMR_DBGCFG0_RESET 0x00000000
246 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG0 register from the beginning of the component. */
247 #define ALT_IO48_HMC_MMR_DBGCFG0_OFST 0x0
248 
249 /*
250  * Register : dbgcfg1
251  *
252  * Register Layout
253  *
254  * Bits | Access | Reset | Description
255  * :-------|:-------|:------|:-------------------------------------
256  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL
257  *
258  */
259 /*
260  * Field : cfg_dbg_ctrl
261  *
262  * TBD
263  *
264  * Field Access Macros:
265  *
266  */
267 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field. */
268 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_LSB 0
269 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field. */
270 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_MSB 31
271 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field. */
272 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_WIDTH 32
273 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field value. */
274 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET_MSK 0xffffffff
275 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field value. */
276 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_CLR_MSK 0x00000000
277 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field. */
278 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_RESET 0x0
279 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL field value from a register. */
280 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_GET(value) (((value) & 0xffffffff) >> 0)
281 /* Produces a ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL register field value suitable for setting the register. */
282 #define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET(value) (((value) << 0) & 0xffffffff)
283 
284 #ifndef __ASSEMBLY__
285 /*
286  * WARNING: The C register and register group struct declarations are provided for
287  * convenience and illustrative purposes. They should, however, be used with
288  * caution as the C language standard provides no guarantees about the alignment or
289  * atomicity of device memory accesses. The recommended practice for writing
290  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
291  * alt_write_word() functions.
292  *
293  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG1.
294  */
295 struct ALT_IO48_HMC_MMR_DBGCFG1_s
296 {
297  uint32_t cfg_dbg_ctrl : 32; /* ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL */
298 };
299 
300 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG1. */
301 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG1_s ALT_IO48_HMC_MMR_DBGCFG1_t;
302 #endif /* __ASSEMBLY__ */
303 
304 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG1 register. */
305 #define ALT_IO48_HMC_MMR_DBGCFG1_RESET 0x00000000
306 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG1 register from the beginning of the component. */
307 #define ALT_IO48_HMC_MMR_DBGCFG1_OFST 0x4
308 
309 /*
310  * Register : dbgcfg2
311  *
312  * Register Layout
313  *
314  * Bits | Access | Reset | Description
315  * :-------|:-------|:------|:-----------------------------------------
316  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U
317  *
318  */
319 /*
320  * Field : cfg_bist_cmd0_u
321  *
322  * TBD
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field. */
328 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_LSB 0
329 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field. */
330 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_MSB 31
331 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field. */
332 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_WIDTH 32
333 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field value. */
334 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET_MSK 0xffffffff
335 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field value. */
336 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_CLR_MSK 0x00000000
337 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field. */
338 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_RESET 0x0
339 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U field value from a register. */
340 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_GET(value) (((value) & 0xffffffff) >> 0)
341 /* Produces a ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U register field value suitable for setting the register. */
342 #define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET(value) (((value) << 0) & 0xffffffff)
343 
344 #ifndef __ASSEMBLY__
345 /*
346  * WARNING: The C register and register group struct declarations are provided for
347  * convenience and illustrative purposes. They should, however, be used with
348  * caution as the C language standard provides no guarantees about the alignment or
349  * atomicity of device memory accesses. The recommended practice for writing
350  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
351  * alt_write_word() functions.
352  *
353  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG2.
354  */
355 struct ALT_IO48_HMC_MMR_DBGCFG2_s
356 {
357  uint32_t cfg_bist_cmd0_u : 32; /* ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U */
358 };
359 
360 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG2. */
361 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG2_s ALT_IO48_HMC_MMR_DBGCFG2_t;
362 #endif /* __ASSEMBLY__ */
363 
364 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG2 register. */
365 #define ALT_IO48_HMC_MMR_DBGCFG2_RESET 0x00000000
366 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG2 register from the beginning of the component. */
367 #define ALT_IO48_HMC_MMR_DBGCFG2_OFST 0x8
368 
369 /*
370  * Register : dbgcfg3
371  *
372  * Register Layout
373  *
374  * Bits | Access | Reset | Description
375  * :-------|:-------|:------|:-----------------------------------------
376  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L
377  *
378  */
379 /*
380  * Field : cfg_bist_cmd0_l
381  *
382  * TBD
383  *
384  * Field Access Macros:
385  *
386  */
387 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field. */
388 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_LSB 0
389 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field. */
390 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_MSB 31
391 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field. */
392 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_WIDTH 32
393 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field value. */
394 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET_MSK 0xffffffff
395 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field value. */
396 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_CLR_MSK 0x00000000
397 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field. */
398 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_RESET 0x0
399 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L field value from a register. */
400 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_GET(value) (((value) & 0xffffffff) >> 0)
401 /* Produces a ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L register field value suitable for setting the register. */
402 #define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET(value) (((value) << 0) & 0xffffffff)
403 
404 #ifndef __ASSEMBLY__
405 /*
406  * WARNING: The C register and register group struct declarations are provided for
407  * convenience and illustrative purposes. They should, however, be used with
408  * caution as the C language standard provides no guarantees about the alignment or
409  * atomicity of device memory accesses. The recommended practice for writing
410  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
411  * alt_write_word() functions.
412  *
413  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG3.
414  */
415 struct ALT_IO48_HMC_MMR_DBGCFG3_s
416 {
417  uint32_t cfg_bist_cmd0_l : 32; /* ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L */
418 };
419 
420 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG3. */
421 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG3_s ALT_IO48_HMC_MMR_DBGCFG3_t;
422 #endif /* __ASSEMBLY__ */
423 
424 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG3 register. */
425 #define ALT_IO48_HMC_MMR_DBGCFG3_RESET 0x00000000
426 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG3 register from the beginning of the component. */
427 #define ALT_IO48_HMC_MMR_DBGCFG3_OFST 0xc
428 
429 /*
430  * Register : dbgcfg4
431  *
432  * Register Layout
433  *
434  * Bits | Access | Reset | Description
435  * :-------|:-------|:------|:-----------------------------------------
436  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U
437  *
438  */
439 /*
440  * Field : cfg_bist_cmd1_u
441  *
442  * TBD
443  *
444  * Field Access Macros:
445  *
446  */
447 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field. */
448 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_LSB 0
449 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field. */
450 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_MSB 31
451 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field. */
452 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32
453 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value. */
454 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff
455 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value. */
456 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000
457 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field. */
458 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0
459 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U field value from a register. */
460 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0)
461 /* Produces a ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value suitable for setting the register. */
462 #define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff)
463 
464 #ifndef __ASSEMBLY__
465 /*
466  * WARNING: The C register and register group struct declarations are provided for
467  * convenience and illustrative purposes. They should, however, be used with
468  * caution as the C language standard provides no guarantees about the alignment or
469  * atomicity of device memory accesses. The recommended practice for writing
470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
471  * alt_write_word() functions.
472  *
473  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG4.
474  */
475 struct ALT_IO48_HMC_MMR_DBGCFG4_s
476 {
477  uint32_t cfg_bist_cmd1_u : 32; /* ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U */
478 };
479 
480 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG4. */
481 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG4_s ALT_IO48_HMC_MMR_DBGCFG4_t;
482 #endif /* __ASSEMBLY__ */
483 
484 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG4 register. */
485 #define ALT_IO48_HMC_MMR_DBGCFG4_RESET 0x00000000
486 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG4 register from the beginning of the component. */
487 #define ALT_IO48_HMC_MMR_DBGCFG4_OFST 0x10
488 
489 /*
490  * Register : dbgcfg5
491  *
492  * Register Layout
493  *
494  * Bits | Access | Reset | Description
495  * :-------|:-------|:------|:-----------------------------------------
496  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L
497  *
498  */
499 /*
500  * Field : cfg_bist_cmd1_l
501  *
502  * TBD
503  *
504  * Field Access Macros:
505  *
506  */
507 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field. */
508 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_LSB 0
509 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field. */
510 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_MSB 31
511 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field. */
512 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_WIDTH 32
513 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field value. */
514 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET_MSK 0xffffffff
515 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field value. */
516 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_CLR_MSK 0x00000000
517 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field. */
518 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_RESET 0x0
519 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L field value from a register. */
520 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_GET(value) (((value) & 0xffffffff) >> 0)
521 /* Produces a ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L register field value suitable for setting the register. */
522 #define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET(value) (((value) << 0) & 0xffffffff)
523 
524 #ifndef __ASSEMBLY__
525 /*
526  * WARNING: The C register and register group struct declarations are provided for
527  * convenience and illustrative purposes. They should, however, be used with
528  * caution as the C language standard provides no guarantees about the alignment or
529  * atomicity of device memory accesses. The recommended practice for writing
530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
531  * alt_write_word() functions.
532  *
533  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG5.
534  */
535 struct ALT_IO48_HMC_MMR_DBGCFG5_s
536 {
537  uint32_t cfg_bist_cmd1_l : 32; /* ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L */
538 };
539 
540 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG5. */
541 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG5_s ALT_IO48_HMC_MMR_DBGCFG5_t;
542 #endif /* __ASSEMBLY__ */
543 
544 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG5 register. */
545 #define ALT_IO48_HMC_MMR_DBGCFG5_RESET 0x00000000
546 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG5 register from the beginning of the component. */
547 #define ALT_IO48_HMC_MMR_DBGCFG5_OFST 0x14
548 
549 /*
550  * Register : dbgcfg6
551  *
552  * Register Layout
553  *
554  * Bits | Access | Reset | Description
555  * :--------|:-------|:------|:-----------------------------------------
556  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL
557  * [31:16] | ??? | 0x0 | *UNDEFINED*
558  *
559  */
560 /*
561  * Field : cfg_dbg_out_sel
562  *
563  * Select which debug signals sent out for observation
564  *
565  * Field Access Macros:
566  *
567  */
568 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field. */
569 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_LSB 0
570 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field. */
571 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_MSB 15
572 /* The width in bits of the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field. */
573 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_WIDTH 16
574 /* The mask used to set the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field value. */
575 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET_MSK 0x0000ffff
576 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field value. */
577 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_CLR_MSK 0xffff0000
578 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field. */
579 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_RESET 0x0
580 /* Extracts the ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL field value from a register. */
581 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_GET(value) (((value) & 0x0000ffff) >> 0)
582 /* Produces a ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL register field value suitable for setting the register. */
583 #define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET(value) (((value) << 0) & 0x0000ffff)
584 
585 #ifndef __ASSEMBLY__
586 /*
587  * WARNING: The C register and register group struct declarations are provided for
588  * convenience and illustrative purposes. They should, however, be used with
589  * caution as the C language standard provides no guarantees about the alignment or
590  * atomicity of device memory accesses. The recommended practice for writing
591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
592  * alt_write_word() functions.
593  *
594  * The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG6.
595  */
596 struct ALT_IO48_HMC_MMR_DBGCFG6_s
597 {
598  uint32_t cfg_dbg_out_sel : 16; /* ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL */
599  uint32_t : 16; /* *UNDEFINED* */
600 };
601 
602 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG6. */
603 typedef volatile struct ALT_IO48_HMC_MMR_DBGCFG6_s ALT_IO48_HMC_MMR_DBGCFG6_t;
604 #endif /* __ASSEMBLY__ */
605 
606 /* The reset value of the ALT_IO48_HMC_MMR_DBGCFG6 register. */
607 #define ALT_IO48_HMC_MMR_DBGCFG6_RESET 0x00000000
608 /* The byte offset of the ALT_IO48_HMC_MMR_DBGCFG6 register from the beginning of the component. */
609 #define ALT_IO48_HMC_MMR_DBGCFG6_OFST 0x18
610 
611 /*
612  * Register : reserve0
613  *
614  * Register Layout
615  *
616  * Bits | Access | Reset | Description
617  * :--------|:-------|:------|:---------------------------------------
618  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0
619  * [31:16] | ??? | 0x0 | *UNDEFINED*
620  *
621  */
622 /*
623  * Field : cfg_reserve0
624  *
625  * General purpose reserve register
626  *
627  * Field Access Macros:
628  *
629  */
630 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field. */
631 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_LSB 0
632 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field. */
633 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_MSB 15
634 /* The width in bits of the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field. */
635 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_WIDTH 16
636 /* The mask used to set the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field value. */
637 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET_MSK 0x0000ffff
638 /* The mask used to clear the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field value. */
639 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_CLR_MSK 0xffff0000
640 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field. */
641 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_RESET 0x0
642 /* Extracts the ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 field value from a register. */
643 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
644 /* Produces a ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 register field value suitable for setting the register. */
645 #define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
646 
647 #ifndef __ASSEMBLY__
648 /*
649  * WARNING: The C register and register group struct declarations are provided for
650  * convenience and illustrative purposes. They should, however, be used with
651  * caution as the C language standard provides no guarantees about the alignment or
652  * atomicity of device memory accesses. The recommended practice for writing
653  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
654  * alt_write_word() functions.
655  *
656  * The struct declaration for register ALT_IO48_HMC_MMR_RESERVE0.
657  */
658 struct ALT_IO48_HMC_MMR_RESERVE0_s
659 {
660  uint32_t cfg_reserve0 : 16; /* ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0 */
661  uint32_t : 16; /* *UNDEFINED* */
662 };
663 
664 /* The typedef declaration for register ALT_IO48_HMC_MMR_RESERVE0. */
665 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE0_s ALT_IO48_HMC_MMR_RESERVE0_t;
666 #endif /* __ASSEMBLY__ */
667 
668 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE0 register. */
669 #define ALT_IO48_HMC_MMR_RESERVE0_RESET 0x00000000
670 /* The byte offset of the ALT_IO48_HMC_MMR_RESERVE0 register from the beginning of the component. */
671 #define ALT_IO48_HMC_MMR_RESERVE0_OFST 0x1c
672 
673 /*
674  * Register : reserve1
675  *
676  * Register Layout
677  *
678  * Bits | Access | Reset | Description
679  * :--------|:-------|:------|:---------------------------------------
680  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1
681  * [31:16] | ??? | 0x0 | *UNDEFINED*
682  *
683  */
684 /*
685  * Field : cfg_reserve1
686  *
687  * General purpose reserve register
688  *
689  * Field Access Macros:
690  *
691  */
692 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field. */
693 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_LSB 0
694 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field. */
695 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_MSB 15
696 /* The width in bits of the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field. */
697 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_WIDTH 16
698 /* The mask used to set the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field value. */
699 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET_MSK 0x0000ffff
700 /* The mask used to clear the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field value. */
701 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_CLR_MSK 0xffff0000
702 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field. */
703 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_RESET 0x0
704 /* Extracts the ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 field value from a register. */
705 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
706 /* Produces a ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 register field value suitable for setting the register. */
707 #define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
708 
709 #ifndef __ASSEMBLY__
710 /*
711  * WARNING: The C register and register group struct declarations are provided for
712  * convenience and illustrative purposes. They should, however, be used with
713  * caution as the C language standard provides no guarantees about the alignment or
714  * atomicity of device memory accesses. The recommended practice for writing
715  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
716  * alt_write_word() functions.
717  *
718  * The struct declaration for register ALT_IO48_HMC_MMR_RESERVE1.
719  */
720 struct ALT_IO48_HMC_MMR_RESERVE1_s
721 {
722  uint32_t cfg_reserve1 : 16; /* ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1 */
723  uint32_t : 16; /* *UNDEFINED* */
724 };
725 
726 /* The typedef declaration for register ALT_IO48_HMC_MMR_RESERVE1. */
727 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE1_s ALT_IO48_HMC_MMR_RESERVE1_t;
728 #endif /* __ASSEMBLY__ */
729 
730 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE1 register. */
731 #define ALT_IO48_HMC_MMR_RESERVE1_RESET 0x00000000
732 /* The byte offset of the ALT_IO48_HMC_MMR_RESERVE1 register from the beginning of the component. */
733 #define ALT_IO48_HMC_MMR_RESERVE1_OFST 0x20
734 
735 /*
736  * Register : reserve2
737  *
738  * Register Layout
739  *
740  * Bits | Access | Reset | Description
741  * :--------|:-------|:------|:---------------------------------------
742  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2
743  * [31:16] | ??? | 0x0 | *UNDEFINED*
744  *
745  */
746 /*
747  * Field : cfg_reserve2
748  *
749  * General purpose reserve register
750  *
751  * Field Access Macros:
752  *
753  */
754 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field. */
755 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_LSB 0
756 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field. */
757 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_MSB 15
758 /* The width in bits of the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field. */
759 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_WIDTH 16
760 /* The mask used to set the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field value. */
761 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET_MSK 0x0000ffff
762 /* The mask used to clear the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field value. */
763 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_CLR_MSK 0xffff0000
764 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field. */
765 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_RESET 0x0
766 /* Extracts the ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 field value from a register. */
767 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
768 /* Produces a ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 register field value suitable for setting the register. */
769 #define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
770 
771 #ifndef __ASSEMBLY__
772 /*
773  * WARNING: The C register and register group struct declarations are provided for
774  * convenience and illustrative purposes. They should, however, be used with
775  * caution as the C language standard provides no guarantees about the alignment or
776  * atomicity of device memory accesses. The recommended practice for writing
777  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
778  * alt_write_word() functions.
779  *
780  * The struct declaration for register ALT_IO48_HMC_MMR_RESERVE2.
781  */
782 struct ALT_IO48_HMC_MMR_RESERVE2_s
783 {
784  uint32_t cfg_reserve2 : 16; /* ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2 */
785  uint32_t : 16; /* *UNDEFINED* */
786 };
787 
788 /* The typedef declaration for register ALT_IO48_HMC_MMR_RESERVE2. */
789 typedef volatile struct ALT_IO48_HMC_MMR_RESERVE2_s ALT_IO48_HMC_MMR_RESERVE2_t;
790 #endif /* __ASSEMBLY__ */
791 
792 /* The reset value of the ALT_IO48_HMC_MMR_RESERVE2 register. */
793 #define ALT_IO48_HMC_MMR_RESERVE2_RESET 0x00000000
794 /* The byte offset of the ALT_IO48_HMC_MMR_RESERVE2 register from the beginning of the component. */
795 #define ALT_IO48_HMC_MMR_RESERVE2_OFST 0x24
796 
797 /*
798  * Register : ctrlcfg0
799  *
800  * Register Layout
801  *
802  * Bits | Access | Reset | Description
803  * :--------|:-------|:------|:--------------------------------------------
804  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE
805  * [6:4] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE
806  * [8:7] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS
807  * [13:9] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN
808  * [18:14] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN
809  * [23:19] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN
810  * [28:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN
811  * [31:29] | ??? | 0x0 | *UNDEFINED*
812  *
813  */
814 /*
815  * Field : cfg_mem_type
816  *
817  * Selects memory type. Program this field with one of the following binary values,
818  * "0000" for DDR3 SDRAM, "0001" for DDR4 SDRAM, "0010" for LPDDR3 SDRAM and "0011"
819  * for RLDRAM3.
820  *
821  * Field Access Macros:
822  *
823  */
824 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field. */
825 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_LSB 0
826 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field. */
827 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_MSB 3
828 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field. */
829 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_WIDTH 4
830 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value. */
831 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET_MSK 0x0000000f
832 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value. */
833 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_CLR_MSK 0xfffffff0
834 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field. */
835 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_RESET 0x0
836 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE field value from a register. */
837 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_GET(value) (((value) & 0x0000000f) >> 0)
838 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value suitable for setting the register. */
839 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET(value) (((value) << 0) & 0x0000000f)
840 
841 /*
842  * Field : cfg_dimm_type
843  *
844  * Selects dimm type. Program this field with one of the following binary values,
845  * "3
846  *
847  * Field Access Macros:
848  *
849  */
850 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field. */
851 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_LSB 4
852 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field. */
853 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_MSB 6
854 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field. */
855 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_WIDTH 3
856 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value. */
857 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET_MSK 0x00000070
858 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value. */
859 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_CLR_MSK 0xffffff8f
860 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field. */
861 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_RESET 0x0
862 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE field value from a register. */
863 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_GET(value) (((value) & 0x00000070) >> 4)
864 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value suitable for setting the register. */
865 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET(value) (((value) << 4) & 0x00000070)
866 
867 /*
868  * Field : cfg_ac_pos
869  *
870  * Specify C/A (command/address) pin position. 2
871  *
872  * Field Access Macros:
873  *
874  */
875 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field. */
876 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_LSB 7
877 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field. */
878 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_MSB 8
879 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field. */
880 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_WIDTH 2
881 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value. */
882 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET_MSK 0x00000180
883 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value. */
884 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_CLR_MSK 0xfffffe7f
885 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field. */
886 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_RESET 0x0
887 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS field value from a register. */
888 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_GET(value) (((value) & 0x00000180) >> 7)
889 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value suitable for setting the register. */
890 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET(value) (((value) << 7) & 0x00000180)
891 
892 /*
893  * Field : cfg_ctrl_burst_length
894  *
895  * Configures burst length for control path. Legal values are valid for JEDEC
896  * allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and
897  * LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can
898  * be programmed with 2 or 4 or 8
899  *
900  * Field Access Macros:
901  *
902  */
903 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field. */
904 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_LSB 9
905 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field. */
906 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_MSB 13
907 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field. */
908 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_WIDTH 5
909 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value. */
910 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET_MSK 0x00003e00
911 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value. */
912 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_CLR_MSK 0xffffc1ff
913 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field. */
914 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_RESET 0x0
915 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN field value from a register. */
916 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_GET(value) (((value) & 0x00003e00) >> 9)
917 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value suitable for setting the register. */
918 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET(value) (((value) << 9) & 0x00003e00)
919 
920 /*
921  * Field : cfg_dbc0_burst_length
922  *
923  * Configures burst length for DBC0. Legal values are valid for JEDEC allowed DRAM
924  * values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should
925  * be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with
926  * 2 or 4 or 8
927  *
928  * Field Access Macros:
929  *
930  */
931 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field. */
932 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_LSB 14
933 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field. */
934 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_MSB 18
935 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field. */
936 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_WIDTH 5
937 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value. */
938 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET_MSK 0x0007c000
939 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value. */
940 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_CLR_MSK 0xfff83fff
941 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field. */
942 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_RESET 0x0
943 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN field value from a register. */
944 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_GET(value) (((value) & 0x0007c000) >> 14)
945 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value suitable for setting the register. */
946 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET(value) (((value) << 14) & 0x0007c000)
947 
948 /*
949  * Field : cfg_dbc1_burst_length
950  *
951  * Configures burst length for DBC1. Legal values are valid for JEDEC allowed DRAM
952  * values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should
953  * be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with
954  * 2 or 4 or 8
955  *
956  * Field Access Macros:
957  *
958  */
959 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field. */
960 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_LSB 19
961 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field. */
962 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_MSB 23
963 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field. */
964 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_WIDTH 5
965 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value. */
966 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET_MSK 0x00f80000
967 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value. */
968 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_CLR_MSK 0xff07ffff
969 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field. */
970 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_RESET 0x0
971 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN field value from a register. */
972 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_GET(value) (((value) & 0x00f80000) >> 19)
973 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value suitable for setting the register. */
974 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET(value) (((value) << 19) & 0x00f80000)
975 
976 /*
977  * Field : cfg_dbc2_burst_length
978  *
979  * Configures burst length for DBC2. Legal values are valid for JEDEC allowed DRAM
980  * values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should
981  * be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with
982  * 2 or 4 or 8
983  *
984  * Field Access Macros:
985  *
986  */
987 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field. */
988 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_LSB 24
989 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field. */
990 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_MSB 28
991 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field. */
992 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_WIDTH 5
993 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value. */
994 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET_MSK 0x1f000000
995 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value. */
996 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_CLR_MSK 0xe0ffffff
997 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field. */
998 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_RESET 0x0
999 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN field value from a register. */
1000 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_GET(value) (((value) & 0x1f000000) >> 24)
1001 /* Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value suitable for setting the register. */
1002 #define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET(value) (((value) << 24) & 0x1f000000)
1003 
1004 #ifndef __ASSEMBLY__
1005 /*
1006  * WARNING: The C register and register group struct declarations are provided for
1007  * convenience and illustrative purposes. They should, however, be used with
1008  * caution as the C language standard provides no guarantees about the alignment or
1009  * atomicity of device memory accesses. The recommended practice for writing
1010  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1011  * alt_write_word() functions.
1012  *
1013  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG0.
1014  */
1015 struct ALT_IO48_HMC_MMR_CTLCFG0_s
1016 {
1017  uint32_t cfg_mem_type : 4; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE */
1018  uint32_t cfg_dimm_type : 3; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE */
1019  uint32_t cfg_ac_pos : 2; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS */
1020  uint32_t cfg_ctrl_burst_length : 5; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN */
1021  uint32_t cfg_dbc0_burst_length : 5; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN */
1022  uint32_t cfg_dbc1_burst_length : 5; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN */
1023  uint32_t cfg_dbc2_burst_length : 5; /* ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN */
1024  uint32_t : 3; /* *UNDEFINED* */
1025 };
1026 
1027 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG0. */
1028 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG0_s ALT_IO48_HMC_MMR_CTLCFG0_t;
1029 #endif /* __ASSEMBLY__ */
1030 
1031 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG0 register. */
1032 #define ALT_IO48_HMC_MMR_CTLCFG0_RESET 0x00000000
1033 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG0 register from the beginning of the component. */
1034 #define ALT_IO48_HMC_MMR_CTLCFG0_OFST 0x28
1035 
1036 /*
1037  * Register : ctrlcfg1
1038  *
1039  * Register Layout
1040  *
1041  * Bits | Access | Reset | Description
1042  * :--------|:-------|:------|:------------------------------------------------
1043  * [4:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN
1044  * [6:5] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER
1045  * [7] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC
1046  * [8] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC
1047  * [9] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC
1048  * [10] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC
1049  * [11] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC
1050  * [12] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA
1051  * [13] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA
1052  * [14] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA
1053  * [15] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA
1054  * [16] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA
1055  * [17] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA
1056  * [18] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD
1057  * [24:19] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT
1058  * [25] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN
1059  * [26] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM
1060  * [27] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM
1061  * [28] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM
1062  * [29] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM
1063  * [30] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM
1064  * [31] | ??? | 0x0 | *UNDEFINED*
1065  *
1066  */
1067 /*
1068  * Field : cfg_dbc3_burst_length
1069  *
1070  * Configures burst length for DBC3. Legal values are valid for JEDEC allowed DRAM
1071  * values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should
1072  * be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with
1073  * 2 or 4 or 8
1074  *
1075  * Field Access Macros:
1076  *
1077  */
1078 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field. */
1079 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_LSB 0
1080 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field. */
1081 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_MSB 4
1082 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field. */
1083 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_WIDTH 5
1084 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value. */
1085 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET_MSK 0x0000001f
1086 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value. */
1087 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_CLR_MSK 0xffffffe0
1088 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field. */
1089 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_RESET 0x0
1090 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN field value from a register. */
1091 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_GET(value) (((value) & 0x0000001f) >> 0)
1092 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value suitable for setting the register. */
1093 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET(value) (((value) << 0) & 0x0000001f)
1094 
1095 /*
1096  * Field : cfg_addr_order
1097  *
1098  * Selects the order for address interleaving. Programming this field with
1099  * different values gives different mappings between the AXI or Avalon-MM address
1100  * and the SDRAM address. Program this field with the following binary values to
1101  * select the ordering. "00" - chip, row, bank(BG, BA), column; "01" - chip,
1102  * bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column;
1103  *
1104  * Field Access Macros:
1105  *
1106  */
1107 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field. */
1108 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_LSB 5
1109 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field. */
1110 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_MSB 6
1111 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field. */
1112 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_WIDTH 2
1113 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value. */
1114 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET_MSK 0x00000060
1115 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value. */
1116 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_CLR_MSK 0xffffff9f
1117 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field. */
1118 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_RESET 0x0
1119 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER field value from a register. */
1120 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_GET(value) (((value) & 0x00000060) >> 5)
1121 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value suitable for setting the register. */
1122 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET(value) (((value) << 5) & 0x00000060)
1123 
1124 /*
1125  * Field : cfg_ctrl_enable_ecc
1126  *
1127  * Enable the generation and checking of ECC.
1128  *
1129  * Field Access Macros:
1130  *
1131  */
1132 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field. */
1133 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_LSB 7
1134 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field. */
1135 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_MSB 7
1136 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field. */
1137 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_WIDTH 1
1138 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value. */
1139 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET_MSK 0x00000080
1140 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value. */
1141 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_CLR_MSK 0xffffff7f
1142 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field. */
1143 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_RESET 0x0
1144 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC field value from a register. */
1145 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_GET(value) (((value) & 0x00000080) >> 7)
1146 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value suitable for setting the register. */
1147 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET(value) (((value) << 7) & 0x00000080)
1148 
1149 /*
1150  * Field : cfg_dbc0_enable_ecc
1151  *
1152  * Enable the generation and checking of ECC.
1153  *
1154  * Field Access Macros:
1155  *
1156  */
1157 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field. */
1158 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_LSB 8
1159 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field. */
1160 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_MSB 8
1161 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field. */
1162 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_WIDTH 1
1163 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value. */
1164 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET_MSK 0x00000100
1165 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value. */
1166 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_CLR_MSK 0xfffffeff
1167 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field. */
1168 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_RESET 0x0
1169 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC field value from a register. */
1170 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_GET(value) (((value) & 0x00000100) >> 8)
1171 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value suitable for setting the register. */
1172 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET(value) (((value) << 8) & 0x00000100)
1173 
1174 /*
1175  * Field : cfg_dbc1_enable_ecc
1176  *
1177  * Enable the generation and checking of ECC.
1178  *
1179  * Field Access Macros:
1180  *
1181  */
1182 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field. */
1183 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_LSB 9
1184 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field. */
1185 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_MSB 9
1186 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field. */
1187 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_WIDTH 1
1188 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value. */
1189 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET_MSK 0x00000200
1190 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value. */
1191 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_CLR_MSK 0xfffffdff
1192 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field. */
1193 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_RESET 0x0
1194 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC field value from a register. */
1195 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_GET(value) (((value) & 0x00000200) >> 9)
1196 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value suitable for setting the register. */
1197 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET(value) (((value) << 9) & 0x00000200)
1198 
1199 /*
1200  * Field : cfg_dbc2_enable_ecc
1201  *
1202  * Enable the generation and checking of ECC.
1203  *
1204  * Field Access Macros:
1205  *
1206  */
1207 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field. */
1208 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_LSB 10
1209 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field. */
1210 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_MSB 10
1211 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field. */
1212 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_WIDTH 1
1213 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value. */
1214 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET_MSK 0x00000400
1215 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value. */
1216 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_CLR_MSK 0xfffffbff
1217 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field. */
1218 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_RESET 0x0
1219 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC field value from a register. */
1220 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_GET(value) (((value) & 0x00000400) >> 10)
1221 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value suitable for setting the register. */
1222 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET(value) (((value) << 10) & 0x00000400)
1223 
1224 /*
1225  * Field : cfg_dbc3_enable_ecc
1226  *
1227  * Enable the generation and checking of ECC.
1228  *
1229  * Field Access Macros:
1230  *
1231  */
1232 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field. */
1233 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_LSB 11
1234 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field. */
1235 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_MSB 11
1236 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field. */
1237 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_WIDTH 1
1238 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value. */
1239 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET_MSK 0x00000800
1240 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value. */
1241 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_CLR_MSK 0xfffff7ff
1242 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field. */
1243 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_RESET 0x0
1244 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC field value from a register. */
1245 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_GET(value) (((value) & 0x00000800) >> 11)
1246 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value suitable for setting the register. */
1247 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET(value) (((value) << 11) & 0x00000800)
1248 
1249 /*
1250  * Field : cfg_reorder_data
1251  *
1252  * This bit controls whether the controller can re-order operations to optimize
1253  * SDRAM bandwidth. It should generally be set to a one.
1254  *
1255  * Field Access Macros:
1256  *
1257  */
1258 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field. */
1259 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_LSB 12
1260 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field. */
1261 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_MSB 12
1262 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field. */
1263 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_WIDTH 1
1264 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value. */
1265 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET_MSK 0x00001000
1266 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value. */
1267 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_CLR_MSK 0xffffefff
1268 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field. */
1269 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_RESET 0x0
1270 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA field value from a register. */
1271 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_GET(value) (((value) & 0x00001000) >> 12)
1272 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value suitable for setting the register. */
1273 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET(value) (((value) << 12) & 0x00001000)
1274 
1275 /*
1276  * Field : cfg_ctrl_reorder_rdata
1277  *
1278  * This bit controls whether the controller need to re-order the read return data.
1279  *
1280  * Field Access Macros:
1281  *
1282  */
1283 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field. */
1284 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_LSB 13
1285 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field. */
1286 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_MSB 13
1287 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field. */
1288 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_WIDTH 1
1289 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value. */
1290 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET_MSK 0x00002000
1291 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value. */
1292 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_CLR_MSK 0xffffdfff
1293 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field. */
1294 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_RESET 0x0
1295 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA field value from a register. */
1296 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_GET(value) (((value) & 0x00002000) >> 13)
1297 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value suitable for setting the register. */
1298 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET(value) (((value) << 13) & 0x00002000)
1299 
1300 /*
1301  * Field : cfg_dbc0_reorder_rdata
1302  *
1303  * This bit controls whether the controller need to re-order the read return data.
1304  *
1305  * Field Access Macros:
1306  *
1307  */
1308 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field. */
1309 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_LSB 14
1310 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field. */
1311 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_MSB 14
1312 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field. */
1313 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH 1
1314 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value. */
1315 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK 0x00004000
1316 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value. */
1317 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK 0xffffbfff
1318 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field. */
1319 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_RESET 0x0
1320 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA field value from a register. */
1321 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_GET(value) (((value) & 0x00004000) >> 14)
1322 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value suitable for setting the register. */
1323 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET(value) (((value) << 14) & 0x00004000)
1324 
1325 /*
1326  * Field : cfg_dbc1_reorder_rdata
1327  *
1328  * This bit controls whether the controller need to re-order the read return data.
1329  *
1330  * Field Access Macros:
1331  *
1332  */
1333 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field. */
1334 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_LSB 15
1335 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field. */
1336 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_MSB 15
1337 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field. */
1338 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH 1
1339 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value. */
1340 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK 0x00008000
1341 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value. */
1342 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK 0xffff7fff
1343 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field. */
1344 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_RESET 0x0
1345 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA field value from a register. */
1346 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_GET(value) (((value) & 0x00008000) >> 15)
1347 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value suitable for setting the register. */
1348 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET(value) (((value) << 15) & 0x00008000)
1349 
1350 /*
1351  * Field : cfg_dbc2_reorder_rdata
1352  *
1353  * This bit controls whether the controller need to re-order the read return data.
1354  *
1355  * Field Access Macros:
1356  *
1357  */
1358 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field. */
1359 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_LSB 16
1360 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field. */
1361 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_MSB 16
1362 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field. */
1363 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH 1
1364 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value. */
1365 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK 0x00010000
1366 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value. */
1367 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK 0xfffeffff
1368 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field. */
1369 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_RESET 0x0
1370 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA field value from a register. */
1371 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_GET(value) (((value) & 0x00010000) >> 16)
1372 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value suitable for setting the register. */
1373 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET(value) (((value) << 16) & 0x00010000)
1374 
1375 /*
1376  * Field : cfg_dbc3_reorder_rdata
1377  *
1378  * This bit controls whether the controller need to re-order the read return data.
1379  *
1380  * Field Access Macros:
1381  *
1382  */
1383 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field. */
1384 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_LSB 17
1385 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field. */
1386 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_MSB 17
1387 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field. */
1388 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH 1
1389 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value. */
1390 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK 0x00020000
1391 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value. */
1392 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK 0xfffdffff
1393 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field. */
1394 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_RESET 0x0
1395 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA field value from a register. */
1396 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_GET(value) (((value) & 0x00020000) >> 17)
1397 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value suitable for setting the register. */
1398 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET(value) (((value) << 17) & 0x00020000)
1399 
1400 /*
1401  * Field : cfg_reorder_read
1402  *
1403  * This bit controls whether the controller can re-order read command to. 1
1404  *
1405  * Field Access Macros:
1406  *
1407  */
1408 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field. */
1409 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_LSB 18
1410 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field. */
1411 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_MSB 18
1412 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field. */
1413 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_WIDTH 1
1414 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value. */
1415 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET_MSK 0x00040000
1416 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value. */
1417 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_CLR_MSK 0xfffbffff
1418 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field. */
1419 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_RESET 0x0
1420 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD field value from a register. */
1421 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_GET(value) (((value) & 0x00040000) >> 18)
1422 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value suitable for setting the register. */
1423 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET(value) (((value) << 18) & 0x00040000)
1424 
1425 /*
1426  * Field : cfg_starve_limit
1427  *
1428  * Specifies the number of DRAM burst transactions an individual transaction will
1429  * allow to reorder ahead of it before its priority is raised in the memory
1430  * controller.
1431  *
1432  * Field Access Macros:
1433  *
1434  */
1435 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field. */
1436 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_LSB 19
1437 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field. */
1438 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_MSB 24
1439 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field. */
1440 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_WIDTH 6
1441 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value. */
1442 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET_MSK 0x01f80000
1443 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value. */
1444 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_CLR_MSK 0xfe07ffff
1445 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field. */
1446 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_RESET 0x0
1447 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT field value from a register. */
1448 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_GET(value) (((value) & 0x01f80000) >> 19)
1449 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value suitable for setting the register. */
1450 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET(value) (((value) << 19) & 0x01f80000)
1451 
1452 /*
1453  * Field : cfg_dqstrk_en
1454  *
1455  * Enables DQS tracking in the PHY.
1456  *
1457  * Field Access Macros:
1458  *
1459  */
1460 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field. */
1461 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_LSB 25
1462 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field. */
1463 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_MSB 25
1464 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field. */
1465 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_WIDTH 1
1466 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value. */
1467 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET_MSK 0x02000000
1468 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value. */
1469 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_CLR_MSK 0xfdffffff
1470 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field. */
1471 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_RESET 0x0
1472 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN field value from a register. */
1473 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_GET(value) (((value) & 0x02000000) >> 25)
1474 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value suitable for setting the register. */
1475 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET(value) (((value) << 25) & 0x02000000)
1476 
1477 /*
1478  * Field : cfg_ctrl_enable_dm
1479  *
1480  * Set to a one to enable DRAM operation if DM pins are connected.
1481  *
1482  * Field Access Macros:
1483  *
1484  */
1485 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field. */
1486 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_LSB 26
1487 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field. */
1488 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_MSB 26
1489 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field. */
1490 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_WIDTH 1
1491 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value. */
1492 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET_MSK 0x04000000
1493 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value. */
1494 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_CLR_MSK 0xfbffffff
1495 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field. */
1496 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_RESET 0x0
1497 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM field value from a register. */
1498 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_GET(value) (((value) & 0x04000000) >> 26)
1499 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value suitable for setting the register. */
1500 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET(value) (((value) << 26) & 0x04000000)
1501 
1502 /*
1503  * Field : cfg_dbc0_enable_dm
1504  *
1505  * Set to a one to enable DRAM operation if DM pins are connected.
1506  *
1507  * Field Access Macros:
1508  *
1509  */
1510 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field. */
1511 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_LSB 27
1512 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field. */
1513 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_MSB 27
1514 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field. */
1515 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_WIDTH 1
1516 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value. */
1517 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET_MSK 0x08000000
1518 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value. */
1519 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_CLR_MSK 0xf7ffffff
1520 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field. */
1521 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_RESET 0x0
1522 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM field value from a register. */
1523 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_GET(value) (((value) & 0x08000000) >> 27)
1524 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value suitable for setting the register. */
1525 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET(value) (((value) << 27) & 0x08000000)
1526 
1527 /*
1528  * Field : cfg_dbc1_enable_dm
1529  *
1530  * Set to a one to enable DRAM operation if DM pins are connected.
1531  *
1532  * Field Access Macros:
1533  *
1534  */
1535 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field. */
1536 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_LSB 28
1537 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field. */
1538 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_MSB 28
1539 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field. */
1540 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_WIDTH 1
1541 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value. */
1542 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET_MSK 0x10000000
1543 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value. */
1544 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_CLR_MSK 0xefffffff
1545 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field. */
1546 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_RESET 0x0
1547 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM field value from a register. */
1548 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_GET(value) (((value) & 0x10000000) >> 28)
1549 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value suitable for setting the register. */
1550 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET(value) (((value) << 28) & 0x10000000)
1551 
1552 /*
1553  * Field : cfg_dbc2_enable_dm
1554  *
1555  * Set to a one to enable DRAM operation if DM pins are connected.
1556  *
1557  * Field Access Macros:
1558  *
1559  */
1560 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field. */
1561 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_LSB 29
1562 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field. */
1563 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_MSB 29
1564 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field. */
1565 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_WIDTH 1
1566 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value. */
1567 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET_MSK 0x20000000
1568 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value. */
1569 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_CLR_MSK 0xdfffffff
1570 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field. */
1571 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_RESET 0x0
1572 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM field value from a register. */
1573 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_GET(value) (((value) & 0x20000000) >> 29)
1574 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value suitable for setting the register. */
1575 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET(value) (((value) << 29) & 0x20000000)
1576 
1577 /*
1578  * Field : cfg_dbc3_enable_dm
1579  *
1580  * Set to a one to enable DRAM operation if DM pins are connected.
1581  *
1582  * Field Access Macros:
1583  *
1584  */
1585 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field. */
1586 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_LSB 30
1587 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field. */
1588 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_MSB 30
1589 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field. */
1590 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_WIDTH 1
1591 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value. */
1592 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET_MSK 0x40000000
1593 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value. */
1594 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_CLR_MSK 0xbfffffff
1595 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field. */
1596 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_RESET 0x0
1597 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM field value from a register. */
1598 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_GET(value) (((value) & 0x40000000) >> 30)
1599 /* Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value suitable for setting the register. */
1600 #define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET(value) (((value) << 30) & 0x40000000)
1601 
1602 #ifndef __ASSEMBLY__
1603 /*
1604  * WARNING: The C register and register group struct declarations are provided for
1605  * convenience and illustrative purposes. They should, however, be used with
1606  * caution as the C language standard provides no guarantees about the alignment or
1607  * atomicity of device memory accesses. The recommended practice for writing
1608  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1609  * alt_write_word() functions.
1610  *
1611  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG1.
1612  */
1613 struct ALT_IO48_HMC_MMR_CTLCFG1_s
1614 {
1615  uint32_t cfg_dbc3_burst_length : 5; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN */
1616  uint32_t cfg_addr_order : 2; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER */
1617  uint32_t cfg_ctrl_enable_ecc : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC */
1618  uint32_t cfg_dbc0_enable_ecc : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC */
1619  uint32_t cfg_dbc1_enable_ecc : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC */
1620  uint32_t cfg_dbc2_enable_ecc : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC */
1621  uint32_t cfg_dbc3_enable_ecc : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC */
1622  uint32_t cfg_reorder_data : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA */
1623  uint32_t cfg_ctrl_reorder_rdata : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA */
1624  uint32_t cfg_dbc0_reorder_rdata : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA */
1625  uint32_t cfg_dbc1_reorder_rdata : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA */
1626  uint32_t cfg_dbc2_reorder_rdata : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA */
1627  uint32_t cfg_dbc3_reorder_rdata : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA */
1628  uint32_t cfg_reorder_read : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD */
1629  uint32_t cfg_starve_limit : 6; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT */
1630  uint32_t cfg_dqstrk_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN */
1631  uint32_t cfg_ctrl_enable_dm : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM */
1632  uint32_t cfg_dbc0_enable_dm : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM */
1633  uint32_t cfg_dbc1_enable_dm : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM */
1634  uint32_t cfg_dbc2_enable_dm : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM */
1635  uint32_t cfg_dbc3_enable_dm : 1; /* ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM */
1636  uint32_t : 1; /* *UNDEFINED* */
1637 };
1638 
1639 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG1. */
1640 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG1_s ALT_IO48_HMC_MMR_CTLCFG1_t;
1641 #endif /* __ASSEMBLY__ */
1642 
1643 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG1 register. */
1644 #define ALT_IO48_HMC_MMR_CTLCFG1_RESET 0x00000000
1645 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG1 register from the beginning of the component. */
1646 #define ALT_IO48_HMC_MMR_CTLCFG1_OFST 0x2c
1647 
1648 /*
1649  * Register : ctrlcfg2
1650  *
1651  * Register Layout
1652  *
1653  * Bits | Access | Reset | Description
1654  * :--------|:-------|:------|:----------------------------------------------
1655  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD
1656  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD
1657  * [2] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD
1658  * [3] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD
1659  * [4] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD
1660  * [6:5] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0
1661  * [8:7] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1
1662  * [9] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL
1663  * [10] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL
1664  * [11] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL
1665  * [12] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL
1666  * [14:13] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL
1667  * [17:15] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT
1668  * [20:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT
1669  * [23:21] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT
1670  * [26:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT
1671  * [31:27] | ??? | 0x0 | *UNDEFINED*
1672  *
1673  */
1674 /*
1675  * Field : cfg_ctrl_output_regd
1676  *
1677  * Set to one to register the HMC command output. Set to 0 to disable it.
1678  *
1679  * Field Access Macros:
1680  *
1681  */
1682 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field. */
1683 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_LSB 0
1684 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field. */
1685 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_MSB 0
1686 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field. */
1687 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_WIDTH 1
1688 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value. */
1689 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET_MSK 0x00000001
1690 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value. */
1691 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_CLR_MSK 0xfffffffe
1692 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field. */
1693 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_RESET 0x0
1694 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD field value from a register. */
1695 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_GET(value) (((value) & 0x00000001) >> 0)
1696 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value suitable for setting the register. */
1697 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET(value) (((value) << 0) & 0x00000001)
1698 
1699 /*
1700  * Field : cfg_dbc0_output_regd
1701  *
1702  * Set to one to register the HMC command output. Set to 0 to disable it.
1703  *
1704  * Field Access Macros:
1705  *
1706  */
1707 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
1708 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_LSB 1
1709 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
1710 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_MSB 1
1711 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
1712 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH 1
1713 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value. */
1714 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK 0x00000002
1715 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value. */
1716 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK 0xfffffffd
1717 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field. */
1718 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_RESET 0x0
1719 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD field value from a register. */
1720 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value) (((value) & 0x00000002) >> 1)
1721 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value suitable for setting the register. */
1722 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value) (((value) << 1) & 0x00000002)
1723 
1724 /*
1725  * Field : cfg_dbc1_output_regd
1726  *
1727  * Set to one to register the HMC command output. Set to 0 to disable it.
1728  *
1729  * Field Access Macros:
1730  *
1731  */
1732 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
1733 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_LSB 2
1734 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
1735 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_MSB 2
1736 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
1737 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH 1
1738 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value. */
1739 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK 0x00000004
1740 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value. */
1741 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK 0xfffffffb
1742 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field. */
1743 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_RESET 0x0
1744 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD field value from a register. */
1745 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value) (((value) & 0x00000004) >> 2)
1746 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value suitable for setting the register. */
1747 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value) (((value) << 2) & 0x00000004)
1748 
1749 /*
1750  * Field : cfg_dbc2_output_regd
1751  *
1752  * Set to one to register the HMC command output. Set to 0 to disable it.
1753  *
1754  * Field Access Macros:
1755  *
1756  */
1757 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
1758 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_LSB 3
1759 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
1760 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_MSB 3
1761 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
1762 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH 1
1763 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value. */
1764 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK 0x00000008
1765 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value. */
1766 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK 0xfffffff7
1767 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field. */
1768 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_RESET 0x0
1769 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD field value from a register. */
1770 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value) (((value) & 0x00000008) >> 3)
1771 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value suitable for setting the register. */
1772 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value) (((value) << 3) & 0x00000008)
1773 
1774 /*
1775  * Field : cfg_dbc3_output_regd
1776  *
1777  * Set to one to register the HMC command output. Set to 0 to disable it.
1778  *
1779  * Field Access Macros:
1780  *
1781  */
1782 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
1783 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_LSB 4
1784 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
1785 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_MSB 4
1786 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
1787 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH 1
1788 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value. */
1789 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK 0x00000010
1790 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value. */
1791 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK 0xffffffef
1792 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field. */
1793 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_RESET 0x0
1794 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD field value from a register. */
1795 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value) (((value) & 0x00000010) >> 4)
1796 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value suitable for setting the register. */
1797 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value) (((value) << 4) & 0x00000010)
1798 
1799 /*
1800  * Field : cfg_ctrl2dbc_switch0
1801  *
1802  * Select of the MUX ctrl2dbc_switch0. 2
1803  *
1804  * Field Access Macros:
1805  *
1806  */
1807 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field. */
1808 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_LSB 5
1809 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field. */
1810 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_MSB 6
1811 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field. */
1812 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_WIDTH 2
1813 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value. */
1814 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET_MSK 0x00000060
1815 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value. */
1816 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_CLR_MSK 0xffffff9f
1817 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field. */
1818 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_RESET 0x0
1819 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 field value from a register. */
1820 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_GET(value) (((value) & 0x00000060) >> 5)
1821 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value suitable for setting the register. */
1822 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET(value) (((value) << 5) & 0x00000060)
1823 
1824 /*
1825  * Field : cfg_ctrl2dbc_switch1
1826  *
1827  * Select of the MUX ctrl2dbc_switch1. 2
1828  *
1829  * Field Access Macros:
1830  *
1831  */
1832 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field. */
1833 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_LSB 7
1834 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field. */
1835 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_MSB 8
1836 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field. */
1837 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_WIDTH 2
1838 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value. */
1839 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET_MSK 0x00000180
1840 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value. */
1841 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_CLR_MSK 0xfffffe7f
1842 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field. */
1843 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_RESET 0x0
1844 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 field value from a register. */
1845 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_GET(value) (((value) & 0x00000180) >> 7)
1846 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value suitable for setting the register. */
1847 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET(value) (((value) << 7) & 0x00000180)
1848 
1849 /*
1850  * Field : cfg_dbc0_ctrl_sel
1851  *
1852  * DBC0 - control path select. 1
1853  *
1854  * Field Access Macros:
1855  *
1856  */
1857 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field. */
1858 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_LSB 9
1859 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field. */
1860 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_MSB 9
1861 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field. */
1862 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_WIDTH 1
1863 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value. */
1864 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET_MSK 0x00000200
1865 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value. */
1866 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_CLR_MSK 0xfffffdff
1867 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field. */
1868 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_RESET 0x0
1869 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL field value from a register. */
1870 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_GET(value) (((value) & 0x00000200) >> 9)
1871 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value suitable for setting the register. */
1872 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET(value) (((value) << 9) & 0x00000200)
1873 
1874 /*
1875  * Field : cfg_dbc1_ctrl_sel
1876  *
1877  * DBC1 - control path select. 1
1878  *
1879  * Field Access Macros:
1880  *
1881  */
1882 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field. */
1883 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_LSB 10
1884 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field. */
1885 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_MSB 10
1886 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field. */
1887 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_WIDTH 1
1888 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value. */
1889 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET_MSK 0x00000400
1890 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value. */
1891 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_CLR_MSK 0xfffffbff
1892 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field. */
1893 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_RESET 0x0
1894 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL field value from a register. */
1895 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_GET(value) (((value) & 0x00000400) >> 10)
1896 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value suitable for setting the register. */
1897 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET(value) (((value) << 10) & 0x00000400)
1898 
1899 /*
1900  * Field : cfg_dbc2_ctrl_sel
1901  *
1902  * DBC2 - control path select. 1
1903  *
1904  * Field Access Macros:
1905  *
1906  */
1907 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field. */
1908 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_LSB 11
1909 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field. */
1910 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_MSB 11
1911 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field. */
1912 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_WIDTH 1
1913 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value. */
1914 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET_MSK 0x00000800
1915 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value. */
1916 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_CLR_MSK 0xfffff7ff
1917 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field. */
1918 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_RESET 0x0
1919 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL field value from a register. */
1920 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_GET(value) (((value) & 0x00000800) >> 11)
1921 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value suitable for setting the register. */
1922 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET(value) (((value) << 11) & 0x00000800)
1923 
1924 /*
1925  * Field : cfg_dbc3_ctrl_sel
1926  *
1927  * DBC3 - control path select. 1
1928  *
1929  * Field Access Macros:
1930  *
1931  */
1932 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field. */
1933 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_LSB 12
1934 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field. */
1935 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_MSB 12
1936 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field. */
1937 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_WIDTH 1
1938 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value. */
1939 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET_MSK 0x00001000
1940 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value. */
1941 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_CLR_MSK 0xffffefff
1942 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field. */
1943 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_RESET 0x0
1944 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL field value from a register. */
1945 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_GET(value) (((value) & 0x00001000) >> 12)
1946 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value suitable for setting the register. */
1947 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET(value) (((value) << 12) & 0x00001000)
1948 
1949 /*
1950  * Field : cfg_dbc2ctrl_sel
1951  *
1952  * Specifies which DBC is driven by the local control path. 2
1953  *
1954  * Field Access Macros:
1955  *
1956  */
1957 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field. */
1958 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_LSB 13
1959 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field. */
1960 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_MSB 14
1961 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field. */
1962 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_WIDTH 2
1963 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value. */
1964 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET_MSK 0x00006000
1965 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value. */
1966 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_CLR_MSK 0xffff9fff
1967 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field. */
1968 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_RESET 0x0
1969 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL field value from a register. */
1970 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_GET(value) (((value) & 0x00006000) >> 13)
1971 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value suitable for setting the register. */
1972 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET(value) (((value) << 13) & 0x00006000)
1973 
1974 /*
1975  * Field : cfg_dbc0_pipe_lat
1976  *
1977  * Specifies in number of controller clock cycles the latency of pipelining the
1978  * signals from control path to DBC0
1979  *
1980  * Field Access Macros:
1981  *
1982  */
1983 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field. */
1984 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_LSB 15
1985 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field. */
1986 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_MSB 17
1987 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field. */
1988 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_WIDTH 3
1989 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value. */
1990 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK 0x00038000
1991 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value. */
1992 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK 0xfffc7fff
1993 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field. */
1994 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_RESET 0x0
1995 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT field value from a register. */
1996 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_GET(value) (((value) & 0x00038000) >> 15)
1997 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value suitable for setting the register. */
1998 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET(value) (((value) << 15) & 0x00038000)
1999 
2000 /*
2001  * Field : cfg_dbc1_pipe_lat
2002  *
2003  * Specifies in number of controller clock cycles the latency of pipelining the
2004  * signals from control path to DBC1
2005  *
2006  * Field Access Macros:
2007  *
2008  */
2009 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field. */
2010 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_LSB 18
2011 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field. */
2012 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_MSB 20
2013 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field. */
2014 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_WIDTH 3
2015 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value. */
2016 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK 0x001c0000
2017 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value. */
2018 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK 0xffe3ffff
2019 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field. */
2020 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_RESET 0x0
2021 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT field value from a register. */
2022 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_GET(value) (((value) & 0x001c0000) >> 18)
2023 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value suitable for setting the register. */
2024 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET(value) (((value) << 18) & 0x001c0000)
2025 
2026 /*
2027  * Field : cfg_dbc2_pipe_lat
2028  *
2029  * Specifies in number of controller clock cycles the latency of pipelining the
2030  * signals from control path to DBC2
2031  *
2032  * Field Access Macros:
2033  *
2034  */
2035 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field. */
2036 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_LSB 21
2037 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field. */
2038 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_MSB 23
2039 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field. */
2040 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_WIDTH 3
2041 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value. */
2042 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK 0x00e00000
2043 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value. */
2044 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK 0xff1fffff
2045 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field. */
2046 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_RESET 0x0
2047 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT field value from a register. */
2048 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_GET(value) (((value) & 0x00e00000) >> 21)
2049 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value suitable for setting the register. */
2050 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET(value) (((value) << 21) & 0x00e00000)
2051 
2052 /*
2053  * Field : cfg_dbc3_pipe_lat
2054  *
2055  * Specifies in number of controller clock cycles the latency of pipelining the
2056  * signals from control path to DBC3
2057  *
2058  * Field Access Macros:
2059  *
2060  */
2061 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field. */
2062 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_LSB 24
2063 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field. */
2064 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_MSB 26
2065 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field. */
2066 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_WIDTH 3
2067 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value. */
2068 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK 0x07000000
2069 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value. */
2070 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK 0xf8ffffff
2071 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field. */
2072 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_RESET 0x0
2073 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT field value from a register. */
2074 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_GET(value) (((value) & 0x07000000) >> 24)
2075 /* Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value suitable for setting the register. */
2076 #define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET(value) (((value) << 24) & 0x07000000)
2077 
2078 #ifndef __ASSEMBLY__
2079 /*
2080  * WARNING: The C register and register group struct declarations are provided for
2081  * convenience and illustrative purposes. They should, however, be used with
2082  * caution as the C language standard provides no guarantees about the alignment or
2083  * atomicity of device memory accesses. The recommended practice for writing
2084  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2085  * alt_write_word() functions.
2086  *
2087  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG2.
2088  */
2089 struct ALT_IO48_HMC_MMR_CTLCFG2_s
2090 {
2091  uint32_t cfg_ctrl_output_regd : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD */
2092  uint32_t cfg_dbc0_output_regd : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD */
2093  uint32_t cfg_dbc1_output_regd : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD */
2094  uint32_t cfg_dbc2_output_regd : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD */
2095  uint32_t cfg_dbc3_output_regd : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD */
2096  uint32_t cfg_ctrl2dbc_switch0 : 2; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 */
2097  uint32_t cfg_ctrl2dbc_switch1 : 2; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 */
2098  uint32_t cfg_dbc0_ctrl_sel : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL */
2099  uint32_t cfg_dbc1_ctrl_sel : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL */
2100  uint32_t cfg_dbc2_ctrl_sel : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL */
2101  uint32_t cfg_dbc3_ctrl_sel : 1; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL */
2102  uint32_t cfg_dbc2ctrl_sel : 2; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL */
2103  uint32_t cfg_dbc0_pipe_lat : 3; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT */
2104  uint32_t cfg_dbc1_pipe_lat : 3; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT */
2105  uint32_t cfg_dbc2_pipe_lat : 3; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT */
2106  uint32_t cfg_dbc3_pipe_lat : 3; /* ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT */
2107  uint32_t : 5; /* *UNDEFINED* */
2108 };
2109 
2110 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG2. */
2111 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG2_s ALT_IO48_HMC_MMR_CTLCFG2_t;
2112 #endif /* __ASSEMBLY__ */
2113 
2114 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG2 register. */
2115 #define ALT_IO48_HMC_MMR_CTLCFG2_RESET 0x00000000
2116 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG2 register from the beginning of the component. */
2117 #define ALT_IO48_HMC_MMR_CTLCFG2_OFST 0x30
2118 
2119 /*
2120  * Register : ctrlcfg3
2121  *
2122  * Register Layout
2123  *
2124  * Bits | Access | Reset | Description
2125  * :--------|:-------|:------|:------------------------------------------------
2126  * [2:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE
2127  * [5:3] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE
2128  * [8:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE
2129  * [11:9] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE
2130  * [14:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE
2131  * [15] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL
2132  * [16] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL
2133  * [17] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL
2134  * [18] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL
2135  * [19] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL
2136  * [20] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN
2137  * [21] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN
2138  * [22] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN
2139  * [23] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN
2140  * [24] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN
2141  * [25] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE
2142  * [26] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN
2143  * [27] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN
2144  * [30:28] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD
2145  * [31] | ??? | 0x0 | *UNDEFINED*
2146  *
2147  */
2148 /*
2149  * Field : cfg_ctrl_cmd_rate
2150  *
2151  * 3
2152  *
2153  * Field Access Macros:
2154  *
2155  */
2156 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field. */
2157 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_LSB 0
2158 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field. */
2159 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_MSB 2
2160 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field. */
2161 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_WIDTH 3
2162 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value. */
2163 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET_MSK 0x00000007
2164 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value. */
2165 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_CLR_MSK 0xfffffff8
2166 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field. */
2167 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_RESET 0x0
2168 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE field value from a register. */
2169 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0)
2170 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value suitable for setting the register. */
2171 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007)
2172 
2173 /*
2174  * Field : cfg_dbc0_cmd_rate
2175  *
2176  * 3
2177  *
2178  * Field Access Macros:
2179  *
2180  */
2181 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field. */
2182 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_LSB 3
2183 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field. */
2184 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_MSB 5
2185 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field. */
2186 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3
2187 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value. */
2188 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038
2189 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value. */
2190 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7
2191 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field. */
2192 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0
2193 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE field value from a register. */
2194 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3)
2195 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value suitable for setting the register. */
2196 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038)
2197 
2198 /*
2199  * Field : cfg_dbc1_cmd_rate
2200  *
2201  * 3
2202  *
2203  * Field Access Macros:
2204  *
2205  */
2206 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field. */
2207 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_LSB 6
2208 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field. */
2209 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_MSB 8
2210 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field. */
2211 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3
2212 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value. */
2213 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0
2214 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value. */
2215 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f
2216 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field. */
2217 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0
2218 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE field value from a register. */
2219 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6)
2220 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value suitable for setting the register. */
2221 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0)
2222 
2223 /*
2224  * Field : cfg_dbc2_cmd_rate
2225  *
2226  * 3
2227  *
2228  * Field Access Macros:
2229  *
2230  */
2231 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field. */
2232 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_LSB 9
2233 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field. */
2234 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_MSB 11
2235 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field. */
2236 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3
2237 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value. */
2238 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00
2239 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value. */
2240 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff
2241 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field. */
2242 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0
2243 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE field value from a register. */
2244 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9)
2245 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value suitable for setting the register. */
2246 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00)
2247 
2248 /*
2249  * Field : cfg_dbc3_cmd_rate
2250  *
2251  * 3
2252  *
2253  * Field Access Macros:
2254  *
2255  */
2256 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field. */
2257 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_LSB 12
2258 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field. */
2259 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_MSB 14
2260 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field. */
2261 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3
2262 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value. */
2263 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000
2264 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value. */
2265 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff
2266 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field. */
2267 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0
2268 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE field value from a register. */
2269 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12)
2270 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value suitable for setting the register. */
2271 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000)
2272 
2273 /*
2274  * Field : cfg_ctrl_in_protocol
2275  *
2276  * 1
2277  *
2278  * Field Access Macros:
2279  *
2280  */
2281 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field. */
2282 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_LSB 15
2283 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field. */
2284 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_MSB 15
2285 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field. */
2286 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_WIDTH 1
2287 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value. */
2288 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET_MSK 0x00008000
2289 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value. */
2290 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_CLR_MSK 0xffff7fff
2291 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field. */
2292 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_RESET 0x0
2293 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL field value from a register. */
2294 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15)
2295 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value suitable for setting the register. */
2296 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000)
2297 
2298 /*
2299  * Field : cfg_dbc0_in_protocol
2300  *
2301  * 1
2302  *
2303  * Field Access Macros:
2304  *
2305  */
2306 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
2307 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16
2308 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
2309 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16
2310 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
2311 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1
2312 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value. */
2313 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000
2314 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value. */
2315 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff
2316 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field. */
2317 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0
2318 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL field value from a register. */
2319 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16)
2320 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value suitable for setting the register. */
2321 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000)
2322 
2323 /*
2324  * Field : cfg_dbc1_in_protocol
2325  *
2326  * 1
2327  *
2328  * Field Access Macros:
2329  *
2330  */
2331 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
2332 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17
2333 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
2334 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17
2335 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
2336 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1
2337 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value. */
2338 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000
2339 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value. */
2340 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff
2341 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field. */
2342 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0
2343 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL field value from a register. */
2344 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17)
2345 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value suitable for setting the register. */
2346 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000)
2347 
2348 /*
2349  * Field : cfg_dbc2_in_protocol
2350  *
2351  * 1
2352  *
2353  * Field Access Macros:
2354  *
2355  */
2356 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
2357 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18
2358 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
2359 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18
2360 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
2361 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1
2362 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value. */
2363 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000
2364 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value. */
2365 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff
2366 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field. */
2367 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0
2368 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL field value from a register. */
2369 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18)
2370 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value suitable for setting the register. */
2371 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000)
2372 
2373 /*
2374  * Field : cfg_dbc3_in_protocol
2375  *
2376  * 1
2377  *
2378  * Field Access Macros:
2379  *
2380  */
2381 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
2382 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19
2383 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
2384 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19
2385 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
2386 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1
2387 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value. */
2388 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000
2389 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value. */
2390 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff
2391 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field. */
2392 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0
2393 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL field value from a register. */
2394 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19)
2395 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value suitable for setting the register. */
2396 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000)
2397 
2398 /*
2399  * Field : cfg_ctrl_dualport_en
2400  *
2401  * Enable the second command port for RLDRAM3 only (BL=2 or 4)
2402  *
2403  * Field Access Macros:
2404  *
2405  */
2406 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field. */
2407 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_LSB 20
2408 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field. */
2409 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_MSB 20
2410 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field. */
2411 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_WIDTH 1
2412 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value. */
2413 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET_MSK 0x00100000
2414 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value. */
2415 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_CLR_MSK 0xffefffff
2416 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field. */
2417 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_RESET 0x0
2418 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN field value from a register. */
2419 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20)
2420 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value suitable for setting the register. */
2421 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000)
2422 
2423 /*
2424  * Field : cfg_dbc0_dualport_en
2425  *
2426  * Enable the second data port for RLDRAM3 only (BL=2 or 4)
2427  *
2428  * Field Access Macros:
2429  *
2430  */
2431 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field. */
2432 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21
2433 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field. */
2434 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21
2435 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field. */
2436 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1
2437 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value. */
2438 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000
2439 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value. */
2440 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff
2441 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field. */
2442 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0
2443 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN field value from a register. */
2444 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21)
2445 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value suitable for setting the register. */
2446 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000)
2447 
2448 /*
2449  * Field : cfg_dbc1_dualport_en
2450  *
2451  * Enable the second data port for RLDRAM3 only (BL=2 or 4)
2452  *
2453  * Field Access Macros:
2454  *
2455  */
2456 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field. */
2457 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22
2458 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field. */
2459 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22
2460 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field. */
2461 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1
2462 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value. */
2463 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000
2464 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value. */
2465 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff
2466 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field. */
2467 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0
2468 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN field value from a register. */
2469 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22)
2470 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value suitable for setting the register. */
2471 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000)
2472 
2473 /*
2474  * Field : cfg_dbc2_dualport_en
2475  *
2476  * Enable the second data port for RLDRAM3 only (BL=2 or 4)
2477  *
2478  * Field Access Macros:
2479  *
2480  */
2481 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field. */
2482 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23
2483 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field. */
2484 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23
2485 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field. */
2486 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1
2487 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value. */
2488 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000
2489 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value. */
2490 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff
2491 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field. */
2492 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0
2493 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN field value from a register. */
2494 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23)
2495 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value suitable for setting the register. */
2496 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000)
2497 
2498 /*
2499  * Field : cfg_dbc3_dualport_en
2500  *
2501  * Enable the second data port for RLDRAM3 only (BL=2 or 4)
2502  *
2503  * Field Access Macros:
2504  *
2505  */
2506 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field. */
2507 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24
2508 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field. */
2509 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24
2510 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field. */
2511 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1
2512 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value. */
2513 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000
2514 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value. */
2515 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff
2516 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field. */
2517 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0
2518 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN field value from a register. */
2519 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24)
2520 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value suitable for setting the register. */
2521 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000)
2522 
2523 /*
2524  * Field : cfg_arbiter_type
2525  *
2526  * Indicates controller arbiter operating mode. Set this to: - 1
2527  *
2528  * Field Access Macros:
2529  *
2530  */
2531 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field. */
2532 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_LSB 25
2533 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field. */
2534 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_MSB 25
2535 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field. */
2536 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_WIDTH 1
2537 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value. */
2538 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000
2539 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value. */
2540 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff
2541 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field. */
2542 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_RESET 0x0
2543 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE field value from a register. */
2544 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25)
2545 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value suitable for setting the register. */
2546 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000)
2547 
2548 /*
2549  * Field : cfg_open_page_en
2550  *
2551  * Set to 1 to enable the open page policy when command reordering is disabled
2552  * (cfg_cmd_reorder = 0). This bit does not matter when cfg_cmd_reorder is 1.
2553  *
2554  * Field Access Macros:
2555  *
2556  */
2557 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field. */
2558 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_LSB 26
2559 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field. */
2560 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_MSB 26
2561 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field. */
2562 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1
2563 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value. */
2564 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000
2565 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value. */
2566 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff
2567 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field. */
2568 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0
2569 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN field value from a register. */
2570 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26)
2571 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value suitable for setting the register. */
2572 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000)
2573 
2574 /*
2575  * Field : cfg_geardn_en
2576  *
2577  * Set to 1 to enable the gear down mode for DDR4
2578  *
2579  * Field Access Macros:
2580  *
2581  */
2582 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field. */
2583 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_LSB 27
2584 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field. */
2585 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_MSB 27
2586 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field. */
2587 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_WIDTH 1
2588 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value. */
2589 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000
2590 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value. */
2591 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff
2592 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field. */
2593 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_RESET 0x0
2594 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN field value from a register. */
2595 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27)
2596 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value suitable for setting the register. */
2597 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000)
2598 
2599 /*
2600  * Field : cfg_rld3_multibank_mode
2601  *
2602  * Multibank setting, specific for RLDRAM3. Set this to: - 3
2603  *
2604  * Field Access Macros:
2605  *
2606  */
2607 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field. */
2608 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_LSB 28
2609 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field. */
2610 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_MSB 30
2611 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field. */
2612 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_WIDTH 3
2613 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value. */
2614 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET_MSK 0x70000000
2615 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value. */
2616 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_CLR_MSK 0x8fffffff
2617 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field. */
2618 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_RESET 0x0
2619 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD field value from a register. */
2620 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_GET(value) (((value) & 0x70000000) >> 28)
2621 /* Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value suitable for setting the register. */
2622 #define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET(value) (((value) << 28) & 0x70000000)
2623 
2624 #ifndef __ASSEMBLY__
2625 /*
2626  * WARNING: The C register and register group struct declarations are provided for
2627  * convenience and illustrative purposes. They should, however, be used with
2628  * caution as the C language standard provides no guarantees about the alignment or
2629  * atomicity of device memory accesses. The recommended practice for writing
2630  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2631  * alt_write_word() functions.
2632  *
2633  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG3.
2634  */
2635 struct ALT_IO48_HMC_MMR_CTLCFG3_s
2636 {
2637  uint32_t cfg_ctrl_cmd_rate : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE */
2638  uint32_t cfg_dbc0_cmd_rate : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE */
2639  uint32_t cfg_dbc1_cmd_rate : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE */
2640  uint32_t cfg_dbc2_cmd_rate : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE */
2641  uint32_t cfg_dbc3_cmd_rate : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE */
2642  uint32_t cfg_ctrl_in_protocol : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL */
2643  uint32_t cfg_dbc0_in_protocol : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL */
2644  uint32_t cfg_dbc1_in_protocol : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL */
2645  uint32_t cfg_dbc2_in_protocol : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL */
2646  uint32_t cfg_dbc3_in_protocol : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL */
2647  uint32_t cfg_ctrl_dualport_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN */
2648  uint32_t cfg_dbc0_dualport_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN */
2649  uint32_t cfg_dbc1_dualport_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN */
2650  uint32_t cfg_dbc2_dualport_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN */
2651  uint32_t cfg_dbc3_dualport_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN */
2652  uint32_t cfg_arbiter_type : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE */
2653  uint32_t cfg_open_page_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN */
2654  uint32_t cfg_geardn_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN */
2655  uint32_t cfg_rld3_multibank_mode : 3; /* ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD */
2656  uint32_t : 1; /* *UNDEFINED* */
2657 };
2658 
2659 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG3. */
2660 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG3_s ALT_IO48_HMC_MMR_CTLCFG3_t;
2661 #endif /* __ASSEMBLY__ */
2662 
2663 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG3 register. */
2664 #define ALT_IO48_HMC_MMR_CTLCFG3_RESET 0x00000000
2665 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG3 register from the beginning of the component. */
2666 #define ALT_IO48_HMC_MMR_CTLCFG3_OFST 0x34
2667 
2668 /*
2669  * Register : ctrlcfg4
2670  *
2671  * Register Layout
2672  *
2673  * Bits | Access | Reset | Description
2674  * :--------|:-------|:------|:-------------------------------------------------
2675  * [4:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID
2676  * [6:5] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD
2677  * [9:7] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN
2678  * [12:10] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN
2679  * [15:13] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN
2680  * [18:16] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN
2681  * [21:19] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN
2682  * [23:22] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET
2683  * [25:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET
2684  * [27:26] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET
2685  * [29:28] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET
2686  * [31:30] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET
2687  *
2688  */
2689 /*
2690  * Field : cfg_tile_id
2691  *
2692  * Tile ID
2693  *
2694  * Field Access Macros:
2695  *
2696  */
2697 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field. */
2698 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_LSB 0
2699 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field. */
2700 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_MSB 4
2701 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field. */
2702 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_WIDTH 5
2703 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value. */
2704 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f
2705 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value. */
2706 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0
2707 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field. */
2708 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_RESET 0x0
2709 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID field value from a register. */
2710 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0)
2711 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value suitable for setting the register. */
2712 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f)
2713 
2714 /*
2715  * Field : cfg_pingpong_mode
2716  *
2717  * Ping Pong mode: 2
2718  *
2719  * Field Access Macros:
2720  *
2721  */
2722 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field. */
2723 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_LSB 5
2724 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field. */
2725 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_MSB 6
2726 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field. */
2727 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_WIDTH 2
2728 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value. */
2729 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET_MSK 0x00000060
2730 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value. */
2731 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_CLR_MSK 0xffffff9f
2732 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field. */
2733 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_RESET 0x0
2734 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD field value from a register. */
2735 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_GET(value) (((value) & 0x00000060) >> 5)
2736 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value suitable for setting the register. */
2737 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET(value) (((value) << 5) & 0x00000060)
2738 
2739 /*
2740  * Field : cfg_ctrl_slot_rotate_en
2741  *
2742  * Cmd slot rotate enable: bit[0] controls write, 1
2743  *
2744  * Field Access Macros:
2745  *
2746  */
2747 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field. */
2748 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_LSB 7
2749 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field. */
2750 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_MSB 9
2751 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field. */
2752 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_WIDTH 3
2753 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value. */
2754 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET_MSK 0x00000380
2755 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value. */
2756 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f
2757 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field. */
2758 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_RESET 0x0
2759 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN field value from a register. */
2760 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7)
2761 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value suitable for setting the register. */
2762 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380)
2763 
2764 /*
2765  * Field : cfg_dbc0_slot_rotate_en
2766  *
2767  * DBC0 slot rotate enable: bit[0] controls write, 1
2768  *
2769  * Field Access Macros:
2770  *
2771  */
2772 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
2773 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10
2774 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
2775 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12
2776 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
2777 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3
2778 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value. */
2779 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00
2780 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value. */
2781 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff
2782 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field. */
2783 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0
2784 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN field value from a register. */
2785 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10)
2786 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value suitable for setting the register. */
2787 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00)
2788 
2789 /*
2790  * Field : cfg_dbc1_slot_rotate_en
2791  *
2792  * DBC1 slot rotate enable: bit[0] controls write, 1
2793  *
2794  * Field Access Macros:
2795  *
2796  */
2797 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
2798 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13
2799 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
2800 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15
2801 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
2802 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3
2803 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value. */
2804 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000
2805 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value. */
2806 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff
2807 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field. */
2808 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0
2809 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN field value from a register. */
2810 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13)
2811 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value suitable for setting the register. */
2812 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000)
2813 
2814 /*
2815  * Field : cfg_dbc2_slot_rotate_en
2816  *
2817  * DBC2 slot rotate enable: bit[0] controls write, 1
2818  *
2819  * Field Access Macros:
2820  *
2821  */
2822 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
2823 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16
2824 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
2825 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18
2826 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
2827 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3
2828 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value. */
2829 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000
2830 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value. */
2831 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff
2832 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field. */
2833 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0
2834 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN field value from a register. */
2835 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16)
2836 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value suitable for setting the register. */
2837 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000)
2838 
2839 /*
2840  * Field : cfg_dbc3_slot_rotate_en
2841  *
2842  * DBC3 slot rotate enable: bit[0] controls write, 1
2843  *
2844  * Field Access Macros:
2845  *
2846  */
2847 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
2848 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19
2849 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
2850 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21
2851 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
2852 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3
2853 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value. */
2854 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000
2855 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value. */
2856 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff
2857 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field. */
2858 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0
2859 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN field value from a register. */
2860 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19)
2861 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value suitable for setting the register. */
2862 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000)
2863 
2864 /*
2865  * Field : cfg_ctrl_slot_offset
2866  *
2867  * Enables afi information to be offset by numbers of FR cycles. Affected afi
2868  * signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst,
2869  * afi_mrnk_write and afi_mrnk_read. Set this to: - 2
2870  *
2871  * Field Access Macros:
2872  *
2873  */
2874 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field. */
2875 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_LSB 22
2876 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field. */
2877 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_MSB 23
2878 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field. */
2879 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_WIDTH 2
2880 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value. */
2881 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET_MSK 0x00c00000
2882 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value. */
2883 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_CLR_MSK 0xff3fffff
2884 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field. */
2885 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_RESET 0x0
2886 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET field value from a register. */
2887 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22)
2888 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value suitable for setting the register. */
2889 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000)
2890 
2891 /*
2892  * Field : cfg_dbc0_slot_offset
2893  *
2894  * Enables afi information to be offset by numbers of FR cycles. Affected afi
2895  * signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst,
2896  * afi_mrnk_write and afi_mrnk_read. Set this to: - 2
2897  *
2898  * Field Access Macros:
2899  *
2900  */
2901 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
2902 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24
2903 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
2904 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25
2905 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
2906 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2
2907 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value. */
2908 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000
2909 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value. */
2910 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff
2911 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field. */
2912 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0
2913 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET field value from a register. */
2914 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24)
2915 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value suitable for setting the register. */
2916 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000)
2917 
2918 /*
2919  * Field : cfg_dbc1_slot_offset
2920  *
2921  * Enables afi information to be offset by numbers of FR cycles. Affected afi
2922  * signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst,
2923  * afi_mrnk_write and afi_mrnk_read. Set this to: - 2
2924  *
2925  * Field Access Macros:
2926  *
2927  */
2928 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
2929 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26
2930 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
2931 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27
2932 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
2933 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2
2934 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value. */
2935 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000
2936 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value. */
2937 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff
2938 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field. */
2939 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0
2940 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET field value from a register. */
2941 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26)
2942 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value suitable for setting the register. */
2943 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000)
2944 
2945 /*
2946  * Field : cfg_dbc2_slot_offset
2947  *
2948  * Enables afi information to be offset by numbers of FR cycles. Affected afi
2949  * signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst,
2950  * afi_mrnk_write and afi_mrnk_read. Set this to: - 2
2951  *
2952  * Field Access Macros:
2953  *
2954  */
2955 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
2956 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28
2957 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
2958 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29
2959 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
2960 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2
2961 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value. */
2962 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000
2963 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value. */
2964 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff
2965 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field. */
2966 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0
2967 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET field value from a register. */
2968 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28)
2969 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value suitable for setting the register. */
2970 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000)
2971 
2972 /*
2973  * Field : cfg_dbc3_slot_offset
2974  *
2975  * Enables afi information to be offset by numbers of FR cycles. Affected afi
2976  * signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst,
2977  * afi_mrnk_write and afi_mrnk_read. Set this to: - 2
2978  *
2979  * Field Access Macros:
2980  *
2981  */
2982 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
2983 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30
2984 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
2985 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31
2986 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
2987 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2
2988 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value. */
2989 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000
2990 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value. */
2991 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff
2992 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field. */
2993 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0
2994 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET field value from a register. */
2995 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30)
2996 /* Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value suitable for setting the register. */
2997 #define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000)
2998 
2999 #ifndef __ASSEMBLY__
3000 /*
3001  * WARNING: The C register and register group struct declarations are provided for
3002  * convenience and illustrative purposes. They should, however, be used with
3003  * caution as the C language standard provides no guarantees about the alignment or
3004  * atomicity of device memory accesses. The recommended practice for writing
3005  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3006  * alt_write_word() functions.
3007  *
3008  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG4.
3009  */
3010 struct ALT_IO48_HMC_MMR_CTLCFG4_s
3011 {
3012  uint32_t cfg_tile_id : 5; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID */
3013  uint32_t cfg_pingpong_mode : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD */
3014  uint32_t cfg_ctrl_slot_rotate_en : 3; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN */
3015  uint32_t cfg_dbc0_slot_rotate_en : 3; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN */
3016  uint32_t cfg_dbc1_slot_rotate_en : 3; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN */
3017  uint32_t cfg_dbc2_slot_rotate_en : 3; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN */
3018  uint32_t cfg_dbc3_slot_rotate_en : 3; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN */
3019  uint32_t cfg_ctrl_slot_offset : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET */
3020  uint32_t cfg_dbc0_slot_offset : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET */
3021  uint32_t cfg_dbc1_slot_offset : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET */
3022  uint32_t cfg_dbc2_slot_offset : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET */
3023  uint32_t cfg_dbc3_slot_offset : 2; /* ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET */
3024 };
3025 
3026 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG4. */
3027 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG4_s ALT_IO48_HMC_MMR_CTLCFG4_t;
3028 #endif /* __ASSEMBLY__ */
3029 
3030 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG4 register. */
3031 #define ALT_IO48_HMC_MMR_CTLCFG4_RESET 0x00000000
3032 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG4 register from the beginning of the component. */
3033 #define ALT_IO48_HMC_MMR_CTLCFG4_OFST 0x38
3034 
3035 /*
3036  * Register : ctrlcfg5
3037  *
3038  * Register Layout
3039  *
3040  * Bits | Access | Reset | Description
3041  * :--------|:-------|:------|:------------------------------------------
3042  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT
3043  * [7:4] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT
3044  * [8] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN
3045  * [9] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN
3046  * [10] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN
3047  * [11] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN
3048  * [12] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN
3049  * [31:13] | ??? | 0x0 | *UNDEFINED*
3050  *
3051  */
3052 /*
3053  * Field : cfg_col_cmd_slot
3054  *
3055  * Specify the col cmd slot. One hot encoding.
3056  *
3057  * Field Access Macros:
3058  *
3059  */
3060 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field. */
3061 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_LSB 0
3062 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field. */
3063 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_MSB 3
3064 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field. */
3065 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_WIDTH 4
3066 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value. */
3067 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET_MSK 0x0000000f
3068 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value. */
3069 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_CLR_MSK 0xfffffff0
3070 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field. */
3071 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_RESET 0x0
3072 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT field value from a register. */
3073 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_GET(value) (((value) & 0x0000000f) >> 0)
3074 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value suitable for setting the register. */
3075 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET(value) (((value) << 0) & 0x0000000f)
3076 
3077 /*
3078  * Field : cfg_row_cmd_slot
3079  *
3080  * Specify the row cmd slot. One hot encoding.
3081  *
3082  * Field Access Macros:
3083  *
3084  */
3085 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field. */
3086 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_LSB 4
3087 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field. */
3088 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_MSB 7
3089 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field. */
3090 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_WIDTH 4
3091 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value. */
3092 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET_MSK 0x000000f0
3093 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value. */
3094 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK 0xffffff0f
3095 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field. */
3096 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_RESET 0x0
3097 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT field value from a register. */
3098 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_GET(value) (((value) & 0x000000f0) >> 4)
3099 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value suitable for setting the register. */
3100 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET(value) (((value) << 4) & 0x000000f0)
3101 
3102 /*
3103  * Field : cfg_ctrl_rc_en
3104  *
3105  * Set to 1 to enable the rate conversion. It converts QR input from core to HR
3106  * inside HMC
3107  *
3108  * Field Access Macros:
3109  *
3110  */
3111 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field. */
3112 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_LSB 8
3113 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field. */
3114 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_MSB 8
3115 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field. */
3116 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_WIDTH 1
3117 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value. */
3118 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET_MSK 0x00000100
3119 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value. */
3120 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_CLR_MSK 0xfffffeff
3121 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field. */
3122 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_RESET 0x0
3123 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN field value from a register. */
3124 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_GET(value) (((value) & 0x00000100) >> 8)
3125 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value suitable for setting the register. */
3126 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET(value) (((value) << 8) & 0x00000100)
3127 
3128 /*
3129  * Field : cfg_dbc0_rc_en
3130  *
3131  * Set to 1 to enable the rate conversion. It converts QR input from core to HR
3132  * inside HMC
3133  *
3134  * Field Access Macros:
3135  *
3136  */
3137 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field. */
3138 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_LSB 9
3139 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field. */
3140 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_MSB 9
3141 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field. */
3142 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_WIDTH 1
3143 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value. */
3144 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET_MSK 0x00000200
3145 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value. */
3146 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_CLR_MSK 0xfffffdff
3147 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field. */
3148 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_RESET 0x0
3149 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN field value from a register. */
3150 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_GET(value) (((value) & 0x00000200) >> 9)
3151 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value suitable for setting the register. */
3152 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET(value) (((value) << 9) & 0x00000200)
3153 
3154 /*
3155  * Field : cfg_dbc1_rc_en
3156  *
3157  * Set to 1 to enable the rate conversion. It converts QR input from core to HR
3158  * inside HMC
3159  *
3160  * Field Access Macros:
3161  *
3162  */
3163 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field. */
3164 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_LSB 10
3165 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field. */
3166 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_MSB 10
3167 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field. */
3168 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_WIDTH 1
3169 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value. */
3170 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET_MSK 0x00000400
3171 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value. */
3172 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_CLR_MSK 0xfffffbff
3173 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field. */
3174 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_RESET 0x0
3175 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN field value from a register. */
3176 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_GET(value) (((value) & 0x00000400) >> 10)
3177 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value suitable for setting the register. */
3178 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET(value) (((value) << 10) & 0x00000400)
3179 
3180 /*
3181  * Field : cfg_dbc2_rc_en
3182  *
3183  * Set to 1 to enable the rate conversion. It converts QR input from core to HR
3184  * inside HMC
3185  *
3186  * Field Access Macros:
3187  *
3188  */
3189 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field. */
3190 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_LSB 11
3191 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field. */
3192 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_MSB 11
3193 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field. */
3194 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_WIDTH 1
3195 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value. */
3196 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET_MSK 0x00000800
3197 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value. */
3198 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_CLR_MSK 0xfffff7ff
3199 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field. */
3200 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_RESET 0x0
3201 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN field value from a register. */
3202 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_GET(value) (((value) & 0x00000800) >> 11)
3203 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value suitable for setting the register. */
3204 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET(value) (((value) << 11) & 0x00000800)
3205 
3206 /*
3207  * Field : cfg_dbc3_rc_en
3208  *
3209  * Set to 1 to enable the rate conversion. It converts QR input from core to HR
3210  * inside HMC
3211  *
3212  * Field Access Macros:
3213  *
3214  */
3215 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field. */
3216 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_LSB 12
3217 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field. */
3218 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_MSB 12
3219 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field. */
3220 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_WIDTH 1
3221 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value. */
3222 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET_MSK 0x00001000
3223 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value. */
3224 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_CLR_MSK 0xffffefff
3225 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field. */
3226 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_RESET 0x0
3227 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN field value from a register. */
3228 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_GET(value) (((value) & 0x00001000) >> 12)
3229 /* Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value suitable for setting the register. */
3230 #define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET(value) (((value) << 12) & 0x00001000)
3231 
3232 #ifndef __ASSEMBLY__
3233 /*
3234  * WARNING: The C register and register group struct declarations are provided for
3235  * convenience and illustrative purposes. They should, however, be used with
3236  * caution as the C language standard provides no guarantees about the alignment or
3237  * atomicity of device memory accesses. The recommended practice for writing
3238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3239  * alt_write_word() functions.
3240  *
3241  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG5.
3242  */
3243 struct ALT_IO48_HMC_MMR_CTLCFG5_s
3244 {
3245  uint32_t cfg_col_cmd_slot : 4; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT */
3246  uint32_t cfg_row_cmd_slot : 4; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT */
3247  uint32_t cfg_ctrl_rc_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN */
3248  uint32_t cfg_dbc0_rc_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN */
3249  uint32_t cfg_dbc1_rc_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN */
3250  uint32_t cfg_dbc2_rc_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN */
3251  uint32_t cfg_dbc3_rc_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN */
3252  uint32_t : 19; /* *UNDEFINED* */
3253 };
3254 
3255 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG5. */
3256 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG5_s ALT_IO48_HMC_MMR_CTLCFG5_t;
3257 #endif /* __ASSEMBLY__ */
3258 
3259 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG5 register. */
3260 #define ALT_IO48_HMC_MMR_CTLCFG5_RESET 0x00000000
3261 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG5 register from the beginning of the component. */
3262 #define ALT_IO48_HMC_MMR_CTLCFG5_OFST 0x3c
3263 
3264 /*
3265  * Register : ctrlcfg6
3266  *
3267  * Register Layout
3268  *
3269  * Bits | Access | Reset | Description
3270  * :--------|:-------|:------|:-------------------------------------
3271  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP
3272  * [31:16] | ??? | 0x0 | *UNDEFINED*
3273  *
3274  */
3275 /*
3276  * Field : cfg_cs_chip
3277  *
3278  * Chip select mapping scheme. Mapping seperated into 4 sections:
3279  * [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which CS_n
3280  * signal should be active when command goes to current CS. Eg: if we set to 16
3281  *
3282  * Field Access Macros:
3283  *
3284  */
3285 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field. */
3286 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_LSB 0
3287 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field. */
3288 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_MSB 15
3289 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field. */
3290 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_WIDTH 16
3291 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field value. */
3292 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET_MSK 0x0000ffff
3293 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field value. */
3294 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_CLR_MSK 0xffff0000
3295 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field. */
3296 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_RESET 0x0
3297 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP field value from a register. */
3298 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3299 /* Produces a ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP register field value suitable for setting the register. */
3300 #define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3301 
3302 #ifndef __ASSEMBLY__
3303 /*
3304  * WARNING: The C register and register group struct declarations are provided for
3305  * convenience and illustrative purposes. They should, however, be used with
3306  * caution as the C language standard provides no guarantees about the alignment or
3307  * atomicity of device memory accesses. The recommended practice for writing
3308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3309  * alt_write_word() functions.
3310  *
3311  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG6.
3312  */
3313 struct ALT_IO48_HMC_MMR_CTLCFG6_s
3314 {
3315  uint32_t cfg_cs_chip : 16; /* ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP */
3316  uint32_t : 16; /* *UNDEFINED* */
3317 };
3318 
3319 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG6. */
3320 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG6_s ALT_IO48_HMC_MMR_CTLCFG6_t;
3321 #endif /* __ASSEMBLY__ */
3322 
3323 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG6 register. */
3324 #define ALT_IO48_HMC_MMR_CTLCFG6_RESET 0x00000000
3325 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG6 register from the beginning of the component. */
3326 #define ALT_IO48_HMC_MMR_CTLCFG6_OFST 0x40
3327 
3328 /*
3329  * Register : ctrlcfg7
3330  *
3331  * Register Layout
3332  *
3333  * Bits | Access | Reset | Description
3334  * :--------|:-------|:------|:-------------------------------------------
3335  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN
3336  * [7:1] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY
3337  * [14:8] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY
3338  * [31:15] | ??? | 0x0 | *UNDEFINED*
3339  *
3340  */
3341 /*
3342  * Field : cfg_clkgating_en
3343  *
3344  * Set to 1 to enable the clock gating. The clock is shut off for the whole HMC
3345  *
3346  * Field Access Macros:
3347  *
3348  */
3349 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field. */
3350 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_LSB 0
3351 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field. */
3352 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_MSB 0
3353 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field. */
3354 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_WIDTH 1
3355 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value. */
3356 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET_MSK 0x00000001
3357 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value. */
3358 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_CLR_MSK 0xfffffffe
3359 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field. */
3360 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_RESET 0x0
3361 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN field value from a register. */
3362 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_GET(value) (((value) & 0x00000001) >> 0)
3363 /* Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value suitable for setting the register. */
3364 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET(value) (((value) << 0) & 0x00000001)
3365 
3366 /*
3367  * Field : cfg_rb_reserved_entry
3368  *
3369  * Specify how many enties are reserved in read buffer before almost full is
3370  * asserted
3371  *
3372  * Field Access Macros:
3373  *
3374  */
3375 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field. */
3376 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_LSB 1
3377 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field. */
3378 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_MSB 7
3379 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field. */
3380 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_WIDTH 7
3381 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value. */
3382 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET_MSK 0x000000fe
3383 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value. */
3384 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_CLR_MSK 0xffffff01
3385 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field. */
3386 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_RESET 0x0
3387 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY field value from a register. */
3388 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_GET(value) (((value) & 0x000000fe) >> 1)
3389 /* Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value suitable for setting the register. */
3390 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET(value) (((value) << 1) & 0x000000fe)
3391 
3392 /*
3393  * Field : cfg_wb_reserved_entry
3394  *
3395  * Specify how many enties are reserved in write buffer before almost full is
3396  * asserted
3397  *
3398  * Field Access Macros:
3399  *
3400  */
3401 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field. */
3402 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_LSB 8
3403 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field. */
3404 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_MSB 14
3405 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field. */
3406 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_WIDTH 7
3407 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value. */
3408 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET_MSK 0x00007f00
3409 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value. */
3410 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_CLR_MSK 0xffff80ff
3411 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field. */
3412 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_RESET 0x0
3413 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY field value from a register. */
3414 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_GET(value) (((value) & 0x00007f00) >> 8)
3415 /* Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value suitable for setting the register. */
3416 #define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET(value) (((value) << 8) & 0x00007f00)
3417 
3418 #ifndef __ASSEMBLY__
3419 /*
3420  * WARNING: The C register and register group struct declarations are provided for
3421  * convenience and illustrative purposes. They should, however, be used with
3422  * caution as the C language standard provides no guarantees about the alignment or
3423  * atomicity of device memory accesses. The recommended practice for writing
3424  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3425  * alt_write_word() functions.
3426  *
3427  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG7.
3428  */
3429 struct ALT_IO48_HMC_MMR_CTLCFG7_s
3430 {
3431  uint32_t cfg_clkgating_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN */
3432  uint32_t cfg_rb_reserved_entry : 7; /* ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY */
3433  uint32_t cfg_wb_reserved_entry : 7; /* ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY */
3434  uint32_t : 17; /* *UNDEFINED* */
3435 };
3436 
3437 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG7. */
3438 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG7_s ALT_IO48_HMC_MMR_CTLCFG7_t;
3439 #endif /* __ASSEMBLY__ */
3440 
3441 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG7 register. */
3442 #define ALT_IO48_HMC_MMR_CTLCFG7_RESET 0x00000000
3443 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG7 register from the beginning of the component. */
3444 #define ALT_IO48_HMC_MMR_CTLCFG7_OFST 0x44
3445 
3446 /*
3447  * Register : ctrlcfg8
3448  *
3449  * Register Layout
3450  *
3451  * Bits | Access | Reset | Description
3452  * :-------|:-------|:------|:------------------------------------------
3453  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN
3454  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV
3455  * [2] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN
3456  * [31:3] | ??? | 0x0 | *UNDEFINED*
3457  *
3458  */
3459 /*
3460  * Field : cfg_3ds_en
3461  *
3462  * Setting to 1 to enable #DS support for DDR4
3463  *
3464  * Field Access Macros:
3465  *
3466  */
3467 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field. */
3468 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_LSB 0
3469 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field. */
3470 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_MSB 0
3471 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field. */
3472 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_WIDTH 1
3473 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value. */
3474 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET_MSK 0x00000001
3475 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value. */
3476 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe
3477 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field. */
3478 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_RESET 0x0
3479 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN field value from a register. */
3480 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0)
3481 /* Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value suitable for setting the register. */
3482 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001)
3483 
3484 /*
3485  * Field : cfg_ck_inv
3486  *
3487  * Use to program CK polarity. 1
3488  *
3489  * Field Access Macros:
3490  *
3491  */
3492 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field. */
3493 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_LSB 1
3494 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field. */
3495 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_MSB 1
3496 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field. */
3497 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_WIDTH 1
3498 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value. */
3499 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET_MSK 0x00000002
3500 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value. */
3501 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd
3502 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field. */
3503 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_RESET 0x0
3504 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV field value from a register. */
3505 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1)
3506 /* Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value suitable for setting the register. */
3507 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002)
3508 
3509 /*
3510  * Field : cfg_addr_mplx_en
3511  *
3512  * Setting to 1 enables RLD3 address mulplex mode
3513  *
3514  * Field Access Macros:
3515  *
3516  */
3517 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field. */
3518 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_LSB 2
3519 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field. */
3520 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_MSB 2
3521 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field. */
3522 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_WIDTH 1
3523 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value. */
3524 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET_MSK 0x00000004
3525 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value. */
3526 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_CLR_MSK 0xfffffffb
3527 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field. */
3528 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_RESET 0x0
3529 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN field value from a register. */
3530 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_GET(value) (((value) & 0x00000004) >> 2)
3531 /* Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value suitable for setting the register. */
3532 #define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET(value) (((value) << 2) & 0x00000004)
3533 
3534 #ifndef __ASSEMBLY__
3535 /*
3536  * WARNING: The C register and register group struct declarations are provided for
3537  * convenience and illustrative purposes. They should, however, be used with
3538  * caution as the C language standard provides no guarantees about the alignment or
3539  * atomicity of device memory accesses. The recommended practice for writing
3540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3541  * alt_write_word() functions.
3542  *
3543  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG8.
3544  */
3545 struct ALT_IO48_HMC_MMR_CTLCFG8_s
3546 {
3547  uint32_t cfg_3ds_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN */
3548  uint32_t cfg_ck_inv : 1; /* ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV */
3549  uint32_t cfg_addr_mplx_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN */
3550  uint32_t : 29; /* *UNDEFINED* */
3551 };
3552 
3553 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG8. */
3554 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG8_s ALT_IO48_HMC_MMR_CTLCFG8_t;
3555 #endif /* __ASSEMBLY__ */
3556 
3557 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG8 register. */
3558 #define ALT_IO48_HMC_MMR_CTLCFG8_RESET 0x00000000
3559 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG8 register from the beginning of the component. */
3560 #define ALT_IO48_HMC_MMR_CTLCFG8_OFST 0x48
3561 
3562 /*
3563  * Register : ctrlcfg9
3564  *
3565  * Register Layout
3566  *
3567  * Bits | Access | Reset | Description
3568  * :-------|:-------|:------|:-------------------------------------------
3569  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN
3570  * [31:1] | ??? | 0x0 | *UNDEFINED*
3571  *
3572  */
3573 /*
3574  * Field : cfg_dfx_bypass_en
3575  *
3576  * Used for dft and timing characterization only. 1
3577  *
3578  * Field Access Macros:
3579  *
3580  */
3581 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field. */
3582 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_LSB 0
3583 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field. */
3584 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_MSB 0
3585 /* The width in bits of the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field. */
3586 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_WIDTH 1
3587 /* The mask used to set the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field value. */
3588 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET_MSK 0x00000001
3589 /* The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field value. */
3590 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_CLR_MSK 0xfffffffe
3591 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field. */
3592 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_RESET 0x0
3593 /* Extracts the ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN field value from a register. */
3594 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_GET(value) (((value) & 0x00000001) >> 0)
3595 /* Produces a ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN register field value suitable for setting the register. */
3596 #define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET(value) (((value) << 0) & 0x00000001)
3597 
3598 #ifndef __ASSEMBLY__
3599 /*
3600  * WARNING: The C register and register group struct declarations are provided for
3601  * convenience and illustrative purposes. They should, however, be used with
3602  * caution as the C language standard provides no guarantees about the alignment or
3603  * atomicity of device memory accesses. The recommended practice for writing
3604  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3605  * alt_write_word() functions.
3606  *
3607  * The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG9.
3608  */
3609 struct ALT_IO48_HMC_MMR_CTLCFG9_s
3610 {
3611  uint32_t cfg_dfx_bypass_en : 1; /* ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN */
3612  uint32_t : 31; /* *UNDEFINED* */
3613 };
3614 
3615 /* The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG9. */
3616 typedef volatile struct ALT_IO48_HMC_MMR_CTLCFG9_s ALT_IO48_HMC_MMR_CTLCFG9_t;
3617 #endif /* __ASSEMBLY__ */
3618 
3619 /* The reset value of the ALT_IO48_HMC_MMR_CTLCFG9 register. */
3620 #define ALT_IO48_HMC_MMR_CTLCFG9_RESET 0x00000000
3621 /* The byte offset of the ALT_IO48_HMC_MMR_CTLCFG9 register from the beginning of the component. */
3622 #define ALT_IO48_HMC_MMR_CTLCFG9_OFST 0x4c
3623 
3624 /*
3625  * Register : dramtiming0
3626  *
3627  * Register Layout
3628  *
3629  * Bits | Access | Reset | Description
3630  * :--------|:-------|:------|:----------------------------------------------------------
3631  * [6:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL
3632  * [12:7] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES
3633  * [18:13] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES
3634  * [31:19] | ??? | 0x0 | *UNDEFINED*
3635  *
3636  */
3637 /*
3638  * Field : cfg_tcl
3639  *
3640  * Memory read latency.
3641  *
3642  * Field Access Macros:
3643  *
3644  */
3645 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field. */
3646 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_LSB 0
3647 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field. */
3648 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_MSB 6
3649 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field. */
3650 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_WIDTH 7
3651 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value. */
3652 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET_MSK 0x0000007f
3653 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value. */
3654 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_CLR_MSK 0xffffff80
3655 /* The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field. */
3656 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_RESET 0x0
3657 /* Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL field value from a register. */
3658 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_GET(value) (((value) & 0x0000007f) >> 0)
3659 /* Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value suitable for setting the register. */
3660 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET(value) (((value) << 0) & 0x0000007f)
3661 
3662 /*
3663  * Field : cfg_power_saving_exit_cycles
3664  *
3665  * The minimum number of cycles to stay in a low power state. This applies to both
3666  * power down and self-refresh and should be set to the greater of tPD and tCKESR.
3667  *
3668  * Field Access Macros:
3669  *
3670  */
3671 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
3672 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB 7
3673 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
3674 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB 12
3675 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
3676 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH 6
3677 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value. */
3678 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK 0x00001f80
3679 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value. */
3680 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK 0xffffe07f
3681 /* The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field. */
3682 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET 0x0
3683 /* Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES field value from a register. */
3684 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value) (((value) & 0x00001f80) >> 7)
3685 /* Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value suitable for setting the register. */
3686 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value) (((value) << 7) & 0x00001f80)
3687 
3688 /*
3689  * Field : cfg_mem_clk_disable_entry_cycles
3690  *
3691  * Set to a the number of clocks after the execution of an self-refresh to stop the
3692  * clock. This register is generally set based on PHY design latency and should
3693  * generally not be changed.
3694  *
3695  * Field Access Macros:
3696  *
3697  */
3698 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field. */
3699 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_LSB 13
3700 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field. */
3701 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_MSB 18
3702 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field. */
3703 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_WIDTH 6
3704 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value. */
3705 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET_MSK 0x0007e000
3706 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value. */
3707 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_CLR_MSK 0xfff81fff
3708 /* The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field. */
3709 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_RESET 0x0
3710 /* Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES field value from a register. */
3711 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_GET(value) (((value) & 0x0007e000) >> 13)
3712 /* Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value suitable for setting the register. */
3713 #define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET(value) (((value) << 13) & 0x0007e000)
3714 
3715 #ifndef __ASSEMBLY__
3716 /*
3717  * WARNING: The C register and register group struct declarations are provided for
3718  * convenience and illustrative purposes. They should, however, be used with
3719  * caution as the C language standard provides no guarantees about the alignment or
3720  * atomicity of device memory accesses. The recommended practice for writing
3721  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3722  * alt_write_word() functions.
3723  *
3724  * The struct declaration for register ALT_IO48_HMC_MMR_DRAMTIMING0.
3725  */
3726 struct ALT_IO48_HMC_MMR_DRAMTIMING0_s
3727 {
3728  uint32_t cfg_tcl : 7; /* ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL */
3729  uint32_t cfg_power_saving_exit_cycles : 6; /* ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES */
3730  uint32_t cfg_mem_clk_disable_entry_cycles : 6; /* ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES */
3731  uint32_t : 13; /* *UNDEFINED* */
3732 };
3733 
3734 /* The typedef declaration for register ALT_IO48_HMC_MMR_DRAMTIMING0. */
3735 typedef volatile struct ALT_IO48_HMC_MMR_DRAMTIMING0_s ALT_IO48_HMC_MMR_DRAMTIMING0_t;
3736 #endif /* __ASSEMBLY__ */
3737 
3738 /* The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0 register. */
3739 #define ALT_IO48_HMC_MMR_DRAMTIMING0_RESET 0x00000000
3740 /* The byte offset of the ALT_IO48_HMC_MMR_DRAMTIMING0 register from the beginning of the component. */
3741 #define ALT_IO48_HMC_MMR_DRAMTIMING0_OFST 0x50
3742 
3743 /*
3744  * Register : dramodt0
3745  *
3746  * Register Layout
3747  *
3748  * Bits | Access | Reset | Description
3749  * :--------|:-------|:------|:------------------------------------------
3750  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP
3751  * [31:16] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP
3752  *
3753  */
3754 /*
3755  * Field : cfg_write_odt_chip
3756  *
3757  * ODT scheme setting for write command. Setting seperated into 4 sections:
3758  * [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip
3759  * should ODT be asserted when write occurs on current CS. Eg: if we set to 16
3760  *
3761  * Field Access Macros:
3762  *
3763  */
3764 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field. */
3765 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_LSB 0
3766 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field. */
3767 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_MSB 15
3768 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field. */
3769 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_WIDTH 16
3770 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value. */
3771 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET_MSK 0x0000ffff
3772 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value. */
3773 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_CLR_MSK 0xffff0000
3774 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field. */
3775 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_RESET 0x0
3776 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP field value from a register. */
3777 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3778 /* Produces a ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value suitable for setting the register. */
3779 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3780 
3781 /*
3782  * Field : cfg_read_odt_chip
3783  *
3784  * ODT scheme setting for read command. Setting seperated into 4 sections:
3785  * [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip
3786  * should ODT be asserted when write occurs on current CS. Eg: if we set to 16
3787  *
3788  * Field Access Macros:
3789  *
3790  */
3791 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field. */
3792 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_LSB 16
3793 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field. */
3794 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_MSB 31
3795 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field. */
3796 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_WIDTH 16
3797 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value. */
3798 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET_MSK 0xffff0000
3799 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value. */
3800 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_CLR_MSK 0x0000ffff
3801 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field. */
3802 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_RESET 0x0
3803 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP field value from a register. */
3804 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_GET(value) (((value) & 0xffff0000) >> 16)
3805 /* Produces a ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value suitable for setting the register. */
3806 #define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET(value) (((value) << 16) & 0xffff0000)
3807 
3808 #ifndef __ASSEMBLY__
3809 /*
3810  * WARNING: The C register and register group struct declarations are provided for
3811  * convenience and illustrative purposes. They should, however, be used with
3812  * caution as the C language standard provides no guarantees about the alignment or
3813  * atomicity of device memory accesses. The recommended practice for writing
3814  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3815  * alt_write_word() functions.
3816  *
3817  * The struct declaration for register ALT_IO48_HMC_MMR_DRAMODT0.
3818  */
3819 struct ALT_IO48_HMC_MMR_DRAMODT0_s
3820 {
3821  uint32_t cfg_write_odt_chip : 16; /* ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP */
3822  uint32_t cfg_read_odt_chip : 16; /* ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP */
3823 };
3824 
3825 /* The typedef declaration for register ALT_IO48_HMC_MMR_DRAMODT0. */
3826 typedef volatile struct ALT_IO48_HMC_MMR_DRAMODT0_s ALT_IO48_HMC_MMR_DRAMODT0_t;
3827 #endif /* __ASSEMBLY__ */
3828 
3829 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT0 register. */
3830 #define ALT_IO48_HMC_MMR_DRAMODT0_RESET 0x00000000
3831 /* The byte offset of the ALT_IO48_HMC_MMR_DRAMODT0 register from the beginning of the component. */
3832 #define ALT_IO48_HMC_MMR_DRAMODT0_OFST 0x54
3833 
3834 /*
3835  * Register : dramodt1
3836  *
3837  * Register Layout
3838  *
3839  * Bits | Access | Reset | Description
3840  * :--------|:-------|:------|:--------------------------------------------
3841  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON
3842  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON
3843  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD
3844  * [23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD
3845  * [31:24] | ??? | 0x0 | *UNDEFINED*
3846  *
3847  */
3848 /*
3849  * Field : cfg_wr_odt_on
3850  *
3851  * Indicates number of memory clock cycle gap between write command and ODT signal
3852  * rising edge
3853  *
3854  * Field Access Macros:
3855  *
3856  */
3857 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field. */
3858 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_LSB 0
3859 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field. */
3860 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_MSB 5
3861 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field. */
3862 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_WIDTH 6
3863 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value. */
3864 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET_MSK 0x0000003f
3865 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value. */
3866 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK 0xffffffc0
3867 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field. */
3868 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_RESET 0x0
3869 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON field value from a register. */
3870 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_GET(value) (((value) & 0x0000003f) >> 0)
3871 /* Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value suitable for setting the register. */
3872 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET(value) (((value) << 0) & 0x0000003f)
3873 
3874 /*
3875  * Field : cfg_rd_odt_on
3876  *
3877  * Indicates number of memory clock cycle gap between read command and ODT signal
3878  * rising edge
3879  *
3880  * Field Access Macros:
3881  *
3882  */
3883 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field. */
3884 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_LSB 6
3885 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field. */
3886 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_MSB 11
3887 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field. */
3888 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_WIDTH 6
3889 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value. */
3890 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET_MSK 0x00000fc0
3891 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value. */
3892 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK 0xfffff03f
3893 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field. */
3894 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_RESET 0x0
3895 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON field value from a register. */
3896 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_GET(value) (((value) & 0x00000fc0) >> 6)
3897 /* Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value suitable for setting the register. */
3898 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET(value) (((value) << 6) & 0x00000fc0)
3899 
3900 /*
3901  * Field : cfg_wr_odt_period
3902  *
3903  * Indicates number of memory clock cycle write ODT signal should stay asserted
3904  * after rising edge
3905  *
3906  * Field Access Macros:
3907  *
3908  */
3909 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
3910 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_LSB 12
3911 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
3912 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_MSB 17
3913 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
3914 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH 6
3915 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value. */
3916 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK 0x0003f000
3917 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value. */
3918 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK 0xfffc0fff
3919 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field. */
3920 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_RESET 0x0
3921 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD field value from a register. */
3922 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value) (((value) & 0x0003f000) >> 12)
3923 /* Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value suitable for setting the register. */
3924 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value) (((value) << 12) & 0x0003f000)
3925 
3926 /*
3927  * Field : cfg_rd_odt_period
3928  *
3929  * Indicates number of memory clock cycle read ODT signal should stay asserted
3930  * after rising edge
3931  *
3932  * Field Access Macros:
3933  *
3934  */
3935 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
3936 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_LSB 18
3937 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
3938 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_MSB 23
3939 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
3940 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH 6
3941 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value. */
3942 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK 0x00fc0000
3943 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value. */
3944 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK 0xff03ffff
3945 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field. */
3946 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_RESET 0x0
3947 /* Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD field value from a register. */
3948 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value) (((value) & 0x00fc0000) >> 18)
3949 /* Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value suitable for setting the register. */
3950 #define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value) (((value) << 18) & 0x00fc0000)
3951 
3952 #ifndef __ASSEMBLY__
3953 /*
3954  * WARNING: The C register and register group struct declarations are provided for
3955  * convenience and illustrative purposes. They should, however, be used with
3956  * caution as the C language standard provides no guarantees about the alignment or
3957  * atomicity of device memory accesses. The recommended practice for writing
3958  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3959  * alt_write_word() functions.
3960  *
3961  * The struct declaration for register ALT_IO48_HMC_MMR_DRAMODT1.
3962  */
3963 struct ALT_IO48_HMC_MMR_DRAMODT1_s
3964 {
3965  uint32_t cfg_wr_odt_on : 6; /* ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON */
3966  uint32_t cfg_rd_odt_on : 6; /* ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON */
3967  uint32_t cfg_wr_odt_period : 6; /* ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD */
3968  uint32_t cfg_rd_odt_period : 6; /* ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD */
3969  uint32_t : 8; /* *UNDEFINED* */
3970 };
3971 
3972 /* The typedef declaration for register ALT_IO48_HMC_MMR_DRAMODT1. */
3973 typedef volatile struct ALT_IO48_HMC_MMR_DRAMODT1_s ALT_IO48_HMC_MMR_DRAMODT1_t;
3974 #endif /* __ASSEMBLY__ */
3975 
3976 /* The reset value of the ALT_IO48_HMC_MMR_DRAMODT1 register. */
3977 #define ALT_IO48_HMC_MMR_DRAMODT1_RESET 0x00000000
3978 /* The byte offset of the ALT_IO48_HMC_MMR_DRAMODT1 register from the beginning of the component. */
3979 #define ALT_IO48_HMC_MMR_DRAMODT1_OFST 0x58
3980 
3981 /*
3982  * Register : sbcfg0
3983  *
3984  * Register Layout
3985  *
3986  * Bits | Access | Reset | Description
3987  * :--------|:-------|:------|:----------------------------------------------
3988  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0
3989  * [31:16] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1
3990  *
3991  */
3992 /*
3993  * Field : cfg_rld3_refresh_seq0
3994  *
3995  * Banks to Refresh for RLD3 in sequence 0. Must not be more than 4 banks
3996  *
3997  * Field Access Macros:
3998  *
3999  */
4000 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
4001 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB 0
4002 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
4003 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB 15
4004 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
4005 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH 16
4006 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value. */
4007 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK 0x0000ffff
4008 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value. */
4009 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK 0xffff0000
4010 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field. */
4011 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET 0x0
4012 /* Extracts the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 field value from a register. */
4013 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value) (((value) & 0x0000ffff) >> 0)
4014 /* Produces a ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value suitable for setting the register. */
4015 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value) (((value) << 0) & 0x0000ffff)
4016 
4017 /*
4018  * Field : cfg_rld3_refresh_seq1
4019  *
4020  * Banks to Refresh for RLD3 in sequence 1. Must not be more than 4 banks
4021  *
4022  * Field Access Macros:
4023  *
4024  */
4025 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
4026 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB 16
4027 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
4028 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB 31
4029 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
4030 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH 16
4031 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value. */
4032 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK 0xffff0000
4033 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value. */
4034 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK 0x0000ffff
4035 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field. */
4036 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET 0x0
4037 /* Extracts the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 field value from a register. */
4038 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value) (((value) & 0xffff0000) >> 16)
4039 /* Produces a ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value suitable for setting the register. */
4040 #define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value) (((value) << 16) & 0xffff0000)
4041 
4042 #ifndef __ASSEMBLY__
4043 /*
4044  * WARNING: The C register and register group struct declarations are provided for
4045  * convenience and illustrative purposes. They should, however, be used with
4046  * caution as the C language standard provides no guarantees about the alignment or
4047  * atomicity of device memory accesses. The recommended practice for writing
4048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4049  * alt_write_word() functions.
4050  *
4051  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG0.
4052  */
4053 struct ALT_IO48_HMC_MMR_SBCFG0_s
4054 {
4055  uint32_t cfg_rld3_refresh_seq0 : 16; /* ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 */
4056  uint32_t cfg_rld3_refresh_seq1 : 16; /* ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 */
4057 };
4058 
4059 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG0. */
4060 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG0_s ALT_IO48_HMC_MMR_SBCFG0_t;
4061 #endif /* __ASSEMBLY__ */
4062 
4063 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG0 register. */
4064 #define ALT_IO48_HMC_MMR_SBCFG0_RESET 0x00000000
4065 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG0 register from the beginning of the component. */
4066 #define ALT_IO48_HMC_MMR_SBCFG0_OFST 0x5c
4067 
4068 /*
4069  * Register : sbcfg1
4070  *
4071  * Register Layout
4072  *
4073  * Bits | Access | Reset | Description
4074  * :--------|:-------|:------|:----------------------------------------------
4075  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2
4076  * [31:16] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3
4077  *
4078  */
4079 /*
4080  * Field : cfg_rld3_refresh_seq2
4081  *
4082  * Banks to Refresh for RLD3 in sequence 2. Must not be more than 4 banks
4083  *
4084  * Field Access Macros:
4085  *
4086  */
4087 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
4088 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_LSB 0
4089 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
4090 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_MSB 15
4091 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
4092 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_WIDTH 16
4093 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value. */
4094 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET_MSK 0x0000ffff
4095 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value. */
4096 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_CLR_MSK 0xffff0000
4097 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field. */
4098 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_RESET 0x0
4099 /* Extracts the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 field value from a register. */
4100 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_GET(value) (((value) & 0x0000ffff) >> 0)
4101 /* Produces a ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 register field value suitable for setting the register. */
4102 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET(value) (((value) << 0) & 0x0000ffff)
4103 
4104 /*
4105  * Field : cfg_rld3_refresh_seq3
4106  *
4107  * Banks to Refresh for RLD3 in sequence 3. Must not be more than 4 banks
4108  *
4109  * Field Access Macros:
4110  *
4111  */
4112 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
4113 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_LSB 16
4114 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
4115 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_MSB 31
4116 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
4117 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_WIDTH 16
4118 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value. */
4119 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET_MSK 0xffff0000
4120 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value. */
4121 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_CLR_MSK 0x0000ffff
4122 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field. */
4123 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_RESET 0x0
4124 /* Extracts the ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 field value from a register. */
4125 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_GET(value) (((value) & 0xffff0000) >> 16)
4126 /* Produces a ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 register field value suitable for setting the register. */
4127 #define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET(value) (((value) << 16) & 0xffff0000)
4128 
4129 #ifndef __ASSEMBLY__
4130 /*
4131  * WARNING: The C register and register group struct declarations are provided for
4132  * convenience and illustrative purposes. They should, however, be used with
4133  * caution as the C language standard provides no guarantees about the alignment or
4134  * atomicity of device memory accesses. The recommended practice for writing
4135  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4136  * alt_write_word() functions.
4137  *
4138  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG1.
4139  */
4140 struct ALT_IO48_HMC_MMR_SBCFG1_s
4141 {
4142  uint32_t cfg_rld3_refresh_seq2 : 16; /* ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2 */
4143  uint32_t cfg_rld3_refresh_seq3 : 16; /* ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3 */
4144 };
4145 
4146 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG1. */
4147 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG1_s ALT_IO48_HMC_MMR_SBCFG1_t;
4148 #endif /* __ASSEMBLY__ */
4149 
4150 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG1 register. */
4151 #define ALT_IO48_HMC_MMR_SBCFG1_RESET 0x00000000
4152 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG1 register from the beginning of the component. */
4153 #define ALT_IO48_HMC_MMR_SBCFG1_OFST 0x60
4154 
4155 /*
4156  * Register : sbcfg2
4157  *
4158  * Register Layout
4159  *
4160  * Bits | Access | Reset | Description
4161  * :-------|:-------|:------|:-------------------------------------------------
4162  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS
4163  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS
4164  * [2] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS
4165  * [3] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS
4166  * [4] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN
4167  * [5] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN
4168  * [7:6] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK
4169  * [31:8] | ??? | 0x0 | *UNDEFINED*
4170  *
4171  */
4172 /*
4173  * Field : cfg_srf_zqcal_disable
4174  *
4175  * Set to 1 to disable ZQ Calibration after self refresh
4176  *
4177  * Field Access Macros:
4178  *
4179  */
4180 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field. */
4181 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_LSB 0
4182 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field. */
4183 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_MSB 0
4184 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field. */
4185 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_WIDTH 1
4186 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value. */
4187 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET_MSK 0x00000001
4188 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value. */
4189 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_CLR_MSK 0xfffffffe
4190 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field. */
4191 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_RESET 0x0
4192 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS field value from a register. */
4193 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_GET(value) (((value) & 0x00000001) >> 0)
4194 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value suitable for setting the register. */
4195 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET(value) (((value) << 0) & 0x00000001)
4196 
4197 /*
4198  * Field : cfg_mps_zqcal_disable
4199  *
4200  * Set to 1 to disable ZQ Calibration after Maximum Power Saving exit
4201  *
4202  * Field Access Macros:
4203  *
4204  */
4205 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field. */
4206 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_LSB 1
4207 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field. */
4208 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_MSB 1
4209 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field. */
4210 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_WIDTH 1
4211 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value. */
4212 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET_MSK 0x00000002
4213 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value. */
4214 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_CLR_MSK 0xfffffffd
4215 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field. */
4216 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_RESET 0x0
4217 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS field value from a register. */
4218 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_GET(value) (((value) & 0x00000002) >> 1)
4219 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value suitable for setting the register. */
4220 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET(value) (((value) << 1) & 0x00000002)
4221 
4222 /*
4223  * Field : cfg_mps_dqstrk_disable
4224  *
4225  * Set to 1 to disable DQS Tracking after Maximum Power Saving exit
4226  *
4227  * Field Access Macros:
4228  *
4229  */
4230 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field. */
4231 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_LSB 2
4232 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field. */
4233 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_MSB 2
4234 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field. */
4235 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_WIDTH 1
4236 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value. */
4237 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET_MSK 0x00000004
4238 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value. */
4239 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_CLR_MSK 0xfffffffb
4240 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field. */
4241 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_RESET 0x0
4242 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS field value from a register. */
4243 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_GET(value) (((value) & 0x00000004) >> 2)
4244 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value suitable for setting the register. */
4245 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET(value) (((value) << 2) & 0x00000004)
4246 
4247 /*
4248  * Field : cfg_sb_cg_disable
4249  *
4250  * Set to 1 to disable mem_ck gating during self refresh and deep power down
4251  *
4252  * Field Access Macros:
4253  *
4254  */
4255 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field. */
4256 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_LSB 3
4257 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field. */
4258 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_MSB 3
4259 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field. */
4260 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_WIDTH 1
4261 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value. */
4262 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET_MSK 0x00000008
4263 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value. */
4264 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_CLR_MSK 0xfffffff7
4265 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field. */
4266 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_RESET 0x0
4267 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS field value from a register. */
4268 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_GET(value) (((value) & 0x00000008) >> 3)
4269 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value suitable for setting the register. */
4270 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET(value) (((value) << 3) & 0x00000008)
4271 
4272 /*
4273  * Field : cfg_user_rfsh_en
4274  *
4275  * Setting to 1 to enable user refresh
4276  *
4277  * Field Access Macros:
4278  *
4279  */
4280 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field. */
4281 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_LSB 4
4282 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field. */
4283 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_MSB 4
4284 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field. */
4285 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1
4286 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value. */
4287 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010
4288 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value. */
4289 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef
4290 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field. */
4291 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0
4292 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN field value from a register. */
4293 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4)
4294 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value suitable for setting the register. */
4295 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010)
4296 
4297 /*
4298  * Field : cfg_srf_autoexit_en
4299  *
4300  * Setting to 1 to enable controller to exit Self Refresh when new command is
4301  * detected
4302  *
4303  * Field Access Macros:
4304  *
4305  */
4306 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
4307 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5
4308 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
4309 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5
4310 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
4311 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1
4312 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value. */
4313 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020
4314 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value. */
4315 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf
4316 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field. */
4317 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0
4318 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN field value from a register. */
4319 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5)
4320 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value suitable for setting the register. */
4321 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020)
4322 
4323 /*
4324  * Field : cfg_srf_entry_exit_block
4325  *
4326  * Blocking arbiter from issuing cmds for the 4 cases, 2
4327  *
4328  * Field Access Macros:
4329  *
4330  */
4331 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
4332 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6
4333 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
4334 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7
4335 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
4336 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2
4337 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value. */
4338 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0
4339 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value. */
4340 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f
4341 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field. */
4342 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0
4343 /* Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK field value from a register. */
4344 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6)
4345 /* Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value suitable for setting the register. */
4346 #define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0)
4347 
4348 #ifndef __ASSEMBLY__
4349 /*
4350  * WARNING: The C register and register group struct declarations are provided for
4351  * convenience and illustrative purposes. They should, however, be used with
4352  * caution as the C language standard provides no guarantees about the alignment or
4353  * atomicity of device memory accesses. The recommended practice for writing
4354  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4355  * alt_write_word() functions.
4356  *
4357  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG2.
4358  */
4359 struct ALT_IO48_HMC_MMR_SBCFG2_s
4360 {
4361  uint32_t cfg_srf_zqcal_disable : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS */
4362  uint32_t cfg_mps_zqcal_disable : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS */
4363  uint32_t cfg_mps_dqstrk_disable : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS */
4364  uint32_t cfg_sb_cg_disable : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS */
4365  uint32_t cfg_user_rfsh_en : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN */
4366  uint32_t cfg_srf_autoexit_en : 1; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN */
4367  uint32_t cfg_srf_entry_exit_block : 2; /* ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK */
4368  uint32_t : 24; /* *UNDEFINED* */
4369 };
4370 
4371 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG2. */
4372 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG2_s ALT_IO48_HMC_MMR_SBCFG2_t;
4373 #endif /* __ASSEMBLY__ */
4374 
4375 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG2 register. */
4376 #define ALT_IO48_HMC_MMR_SBCFG2_RESET 0x00000000
4377 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG2 register from the beginning of the component. */
4378 #define ALT_IO48_HMC_MMR_SBCFG2_OFST 0x64
4379 
4380 /*
4381  * Register : sbcfg3
4382  *
4383  * Register Layout
4384  *
4385  * Bits | Access | Reset | Description
4386  * :--------|:-------|:------|:----------------------------------------
4387  * [19:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3
4388  * [31:20] | ??? | 0x0 | *UNDEFINED*
4389  *
4390  */
4391 /*
4392  * Field : cfg_sb_ddr4_mr3
4393  *
4394  * This register stores the DDR4 MR3 Content
4395  *
4396  * Field Access Macros:
4397  *
4398  */
4399 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field. */
4400 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_LSB 0
4401 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field. */
4402 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_MSB 19
4403 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field. */
4404 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_WIDTH 20
4405 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field value. */
4406 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET_MSK 0x000fffff
4407 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field value. */
4408 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_CLR_MSK 0xfff00000
4409 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field. */
4410 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_RESET 0x0
4411 /* Extracts the ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 field value from a register. */
4412 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_GET(value) (((value) & 0x000fffff) >> 0)
4413 /* Produces a ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 register field value suitable for setting the register. */
4414 #define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET(value) (((value) << 0) & 0x000fffff)
4415 
4416 #ifndef __ASSEMBLY__
4417 /*
4418  * WARNING: The C register and register group struct declarations are provided for
4419  * convenience and illustrative purposes. They should, however, be used with
4420  * caution as the C language standard provides no guarantees about the alignment or
4421  * atomicity of device memory accesses. The recommended practice for writing
4422  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4423  * alt_write_word() functions.
4424  *
4425  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG3.
4426  */
4427 struct ALT_IO48_HMC_MMR_SBCFG3_s
4428 {
4429  uint32_t cfg_sb_ddr4_mr3 : 20; /* ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3 */
4430  uint32_t : 12; /* *UNDEFINED* */
4431 };
4432 
4433 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG3. */
4434 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG3_s ALT_IO48_HMC_MMR_SBCFG3_t;
4435 #endif /* __ASSEMBLY__ */
4436 
4437 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG3 register. */
4438 #define ALT_IO48_HMC_MMR_SBCFG3_RESET 0x00000000
4439 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG3 register from the beginning of the component. */
4440 #define ALT_IO48_HMC_MMR_SBCFG3_OFST 0x68
4441 
4442 /*
4443  * Register : sbcfg4
4444  *
4445  * Register Layout
4446  *
4447  * Bits | Access | Reset | Description
4448  * :--------|:-------|:------|:----------------------------------------
4449  * [19:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4
4450  * [31:20] | ??? | 0x0 | *UNDEFINED*
4451  *
4452  */
4453 /*
4454  * Field : cfg_sb_ddr4_mr4
4455  *
4456  * This register stores the DDR4 MR4 Content
4457  *
4458  * Field Access Macros:
4459  *
4460  */
4461 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field. */
4462 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_LSB 0
4463 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field. */
4464 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_MSB 19
4465 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field. */
4466 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_WIDTH 20
4467 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value. */
4468 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK 0x000fffff
4469 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value. */
4470 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK 0xfff00000
4471 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field. */
4472 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_RESET 0x0
4473 /* Extracts the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 field value from a register. */
4474 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_GET(value) (((value) & 0x000fffff) >> 0)
4475 /* Produces a ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value suitable for setting the register. */
4476 #define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET(value) (((value) << 0) & 0x000fffff)
4477 
4478 #ifndef __ASSEMBLY__
4479 /*
4480  * WARNING: The C register and register group struct declarations are provided for
4481  * convenience and illustrative purposes. They should, however, be used with
4482  * caution as the C language standard provides no guarantees about the alignment or
4483  * atomicity of device memory accesses. The recommended practice for writing
4484  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4485  * alt_write_word() functions.
4486  *
4487  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG4.
4488  */
4489 struct ALT_IO48_HMC_MMR_SBCFG4_s
4490 {
4491  uint32_t cfg_sb_ddr4_mr4 : 20; /* ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 */
4492  uint32_t : 12; /* *UNDEFINED* */
4493 };
4494 
4495 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG4. */
4496 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG4_s ALT_IO48_HMC_MMR_SBCFG4_t;
4497 #endif /* __ASSEMBLY__ */
4498 
4499 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG4 register. */
4500 #define ALT_IO48_HMC_MMR_SBCFG4_RESET 0x00000000
4501 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG4 register from the beginning of the component. */
4502 #define ALT_IO48_HMC_MMR_SBCFG4_OFST 0x6c
4503 
4504 /*
4505  * Register : sbcfg5
4506  *
4507  * Register Layout
4508  *
4509  * Bits | Access | Reset | Description
4510  * :-------|:-------|:------|:-------------------------------------------------
4511  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN
4512  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN
4513  * [31:2] | ??? | 0x0 | *UNDEFINED*
4514  *
4515  */
4516 /*
4517  * Field : cfg_short_dqstrk_ctrl_en
4518  *
4519  * Set to 1 to enable controller controlled DQS short tracking, Set to 0 to enable
4520  * sequencer controlled DQS short tracking
4521  *
4522  * Field Access Macros:
4523  *
4524  */
4525 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field. */
4526 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_LSB 0
4527 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field. */
4528 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_MSB 0
4529 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field. */
4530 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_WIDTH 1
4531 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value. */
4532 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET_MSK 0x00000001
4533 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value. */
4534 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_CLR_MSK 0xfffffffe
4535 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field. */
4536 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_RESET 0x0
4537 /* Extracts the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN field value from a register. */
4538 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000001) >> 0)
4539 /* Produces a ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value suitable for setting the register. */
4540 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET(value) (((value) << 0) & 0x00000001)
4541 
4542 /*
4543  * Field : cfg_period_dqstrk_ctrl_en
4544  *
4545  * Set to 1 to enable controller to issue periodic DQS tracking
4546  *
4547  * Field Access Macros:
4548  *
4549  */
4550 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field. */
4551 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_LSB 1
4552 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field. */
4553 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_MSB 1
4554 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field. */
4555 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_WIDTH 1
4556 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value. */
4557 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET_MSK 0x00000002
4558 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value. */
4559 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_CLR_MSK 0xfffffffd
4560 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field. */
4561 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_RESET 0x0
4562 /* Extracts the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN field value from a register. */
4563 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000002) >> 1)
4564 /* Produces a ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value suitable for setting the register. */
4565 #define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET(value) (((value) << 1) & 0x00000002)
4566 
4567 #ifndef __ASSEMBLY__
4568 /*
4569  * WARNING: The C register and register group struct declarations are provided for
4570  * convenience and illustrative purposes. They should, however, be used with
4571  * caution as the C language standard provides no guarantees about the alignment or
4572  * atomicity of device memory accesses. The recommended practice for writing
4573  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4574  * alt_write_word() functions.
4575  *
4576  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG5.
4577  */
4578 struct ALT_IO48_HMC_MMR_SBCFG5_s
4579 {
4580  uint32_t cfg_short_dqstrk_ctrl_en : 1; /* ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN */
4581  uint32_t cfg_period_dqstrk_ctrl_en : 1; /* ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN */
4582  uint32_t : 30; /* *UNDEFINED* */
4583 };
4584 
4585 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG5. */
4586 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG5_s ALT_IO48_HMC_MMR_SBCFG5_t;
4587 #endif /* __ASSEMBLY__ */
4588 
4589 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG5 register. */
4590 #define ALT_IO48_HMC_MMR_SBCFG5_RESET 0x00000000
4591 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG5 register from the beginning of the component. */
4592 #define ALT_IO48_HMC_MMR_SBCFG5_OFST 0x70
4593 
4594 /*
4595  * Register : sbcfg6
4596  *
4597  * Register Layout
4598  *
4599  * Bits | Access | Reset | Description
4600  * :--------|:-------|:------|:---------------------------------------------------------
4601  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL
4602  * [23:16] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST
4603  * [31:24] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID
4604  *
4605  */
4606 /*
4607  * Field : cfg_period_dqstrk_interval
4608  *
4609  * Inverval between two controller controlled periodic DQS tracking
4610  *
4611  * Field Access Macros:
4612  *
4613  */
4614 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
4615 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB 0
4616 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
4617 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB 15
4618 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
4619 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH 16
4620 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value. */
4621 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK 0x0000ffff
4622 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value. */
4623 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK 0xffff0000
4624 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field. */
4625 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET 0x0
4626 /* Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL field value from a register. */
4627 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value) (((value) & 0x0000ffff) >> 0)
4628 /* Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value suitable for setting the register. */
4629 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value) (((value) << 0) & 0x0000ffff)
4630 
4631 /*
4632  * Field : cfg_t_param_dqstrk_to_valid_last
4633  *
4634  * DQS Tracking Rd to Valid timing for the last Rank
4635  *
4636  * Field Access Macros:
4637  *
4638  */
4639 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
4640 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB 16
4641 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
4642 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB 23
4643 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
4644 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH 8
4645 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value. */
4646 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK 0x00ff0000
4647 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value. */
4648 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK 0xff00ffff
4649 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field. */
4650 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET 0x0
4651 /* Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST field value from a register. */
4652 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value) (((value) & 0x00ff0000) >> 16)
4653 /* Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value suitable for setting the register. */
4654 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value) (((value) << 16) & 0x00ff0000)
4655 
4656 /*
4657  * Field : cfg_t_param_dqstrk_to_valid
4658  *
4659  * DQS Tracking Rd to Valid timing for Ranks other than the Last
4660  *
4661  * Field Access Macros:
4662  *
4663  */
4664 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
4665 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB 24
4666 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
4667 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB 31
4668 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
4669 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH 8
4670 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value. */
4671 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK 0xff000000
4672 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value. */
4673 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK 0x00ffffff
4674 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field. */
4675 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET 0x0
4676 /* Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID field value from a register. */
4677 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value) (((value) & 0xff000000) >> 24)
4678 /* Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value suitable for setting the register. */
4679 #define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value) (((value) << 24) & 0xff000000)
4680 
4681 #ifndef __ASSEMBLY__
4682 /*
4683  * WARNING: The C register and register group struct declarations are provided for
4684  * convenience and illustrative purposes. They should, however, be used with
4685  * caution as the C language standard provides no guarantees about the alignment or
4686  * atomicity of device memory accesses. The recommended practice for writing
4687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4688  * alt_write_word() functions.
4689  *
4690  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG6.
4691  */
4692 struct ALT_IO48_HMC_MMR_SBCFG6_s
4693 {
4694  uint32_t cfg_period_dqstrk_interval : 16; /* ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL */
4695  uint32_t cfg_t_param_dqstrk_to_valid_last : 8; /* ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST */
4696  uint32_t cfg_t_param_dqstrk_to_valid : 8; /* ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID */
4697 };
4698 
4699 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG6. */
4700 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG6_s ALT_IO48_HMC_MMR_SBCFG6_t;
4701 #endif /* __ASSEMBLY__ */
4702 
4703 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG6 register. */
4704 #define ALT_IO48_HMC_MMR_SBCFG6_RESET 0x00000000
4705 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG6 register from the beginning of the component. */
4706 #define ALT_IO48_HMC_MMR_SBCFG6_OFST 0x74
4707 
4708 /*
4709  * Register : sbcfg7
4710  *
4711  * Register Layout
4712  *
4713  * Bits | Access | Reset | Description
4714  * :-------|:-------|:------|:------------------------------------------------
4715  * [6:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD
4716  * [31:7] | ??? | 0x0 | *UNDEFINED*
4717  *
4718  */
4719 /*
4720  * Field : cfg_rfsh_warn_threshold
4721  *
4722  * Threshold to warn a refresh is needed within the number of controller clock
4723  * cycles specified by the threshold
4724  *
4725  * Field Access Macros:
4726  *
4727  */
4728 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
4729 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB 0
4730 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
4731 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB 6
4732 /* The width in bits of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
4733 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH 7
4734 /* The mask used to set the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value. */
4735 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK 0x0000007f
4736 /* The mask used to clear the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value. */
4737 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK 0xffffff80
4738 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field. */
4739 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET 0x0
4740 /* Extracts the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD field value from a register. */
4741 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value) (((value) & 0x0000007f) >> 0)
4742 /* Produces a ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value suitable for setting the register. */
4743 #define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value) (((value) << 0) & 0x0000007f)
4744 
4745 #ifndef __ASSEMBLY__
4746 /*
4747  * WARNING: The C register and register group struct declarations are provided for
4748  * convenience and illustrative purposes. They should, however, be used with
4749  * caution as the C language standard provides no guarantees about the alignment or
4750  * atomicity of device memory accesses. The recommended practice for writing
4751  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4752  * alt_write_word() functions.
4753  *
4754  * The struct declaration for register ALT_IO48_HMC_MMR_SBCFG7.
4755  */
4756 struct ALT_IO48_HMC_MMR_SBCFG7_s
4757 {
4758  uint32_t cfg_rfsh_warn_threshold : 7; /* ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD */
4759  uint32_t : 25; /* *UNDEFINED* */
4760 };
4761 
4762 /* The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG7. */
4763 typedef volatile struct ALT_IO48_HMC_MMR_SBCFG7_s ALT_IO48_HMC_MMR_SBCFG7_t;
4764 #endif /* __ASSEMBLY__ */
4765 
4766 /* The reset value of the ALT_IO48_HMC_MMR_SBCFG7 register. */
4767 #define ALT_IO48_HMC_MMR_SBCFG7_RESET 0x00000000
4768 /* The byte offset of the ALT_IO48_HMC_MMR_SBCFG7 register from the beginning of the component. */
4769 #define ALT_IO48_HMC_MMR_SBCFG7_OFST 0x78
4770 
4771 /*
4772  * Register : caltiming0
4773  *
4774  * Register Layout
4775  *
4776  * Bits | Access | Reset | Description
4777  * :--------|:-------|:------|:-------------------------------------------------------------
4778  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR
4779  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH
4780  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT
4781  * [23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK
4782  * [29:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG
4783  * [31:30] | ??? | 0x0 | *UNDEFINED*
4784  *
4785  */
4786 /*
4787  * Field : cfg_t_param_act_to_rdwr
4788  *
4789  * Activate to Read/write command timing
4790  *
4791  * Field Access Macros:
4792  *
4793  */
4794 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
4795 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_LSB 0
4796 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
4797 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_MSB 5
4798 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
4799 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_WIDTH 6
4800 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value. */
4801 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET_MSK 0x0000003f
4802 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value. */
4803 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_CLR_MSK 0xffffffc0
4804 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field. */
4805 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_RESET 0x0
4806 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR field value from a register. */
4807 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_GET(value) (((value) & 0x0000003f) >> 0)
4808 /* Produces a ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR register field value suitable for setting the register. */
4809 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET(value) (((value) << 0) & 0x0000003f)
4810 
4811 /*
4812  * Field : cfg_t_param_act_to_pch
4813  *
4814  * Active to precharge
4815  *
4816  * Field Access Macros:
4817  *
4818  */
4819 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
4820 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_LSB 6
4821 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
4822 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_MSB 11
4823 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
4824 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_WIDTH 6
4825 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value. */
4826 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET_MSK 0x00000fc0
4827 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value. */
4828 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_CLR_MSK 0xfffff03f
4829 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field. */
4830 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_RESET 0x0
4831 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH field value from a register. */
4832 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
4833 /* Produces a ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH register field value suitable for setting the register. */
4834 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
4835 
4836 /*
4837  * Field : cfg_t_param_act_to_act
4838  *
4839  * Active to activate timing on same bank
4840  *
4841  * Field Access Macros:
4842  *
4843  */
4844 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
4845 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_LSB 12
4846 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
4847 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_MSB 17
4848 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
4849 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_WIDTH 6
4850 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value. */
4851 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET_MSK 0x0003f000
4852 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value. */
4853 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_CLR_MSK 0xfffc0fff
4854 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field. */
4855 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_RESET 0x0
4856 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT field value from a register. */
4857 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_GET(value) (((value) & 0x0003f000) >> 12)
4858 /* Produces a ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT register field value suitable for setting the register. */
4859 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET(value) (((value) << 12) & 0x0003f000)
4860 
4861 /*
4862  * Field : cfg_t_param_act_to_act_diff_bank
4863  *
4864  * Active to activate timing on different banks, for DDR4 same bank group
4865  *
4866  * Field Access Macros:
4867  *
4868  */
4869 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
4870 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_LSB 18
4871 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
4872 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_MSB 23
4873 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
4874 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH 6
4875 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value. */
4876 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET_MSK 0x00fc0000
4877 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value. */
4878 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_CLR_MSK 0xff03ffff
4879 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field. */
4880 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_RESET 0x0
4881 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK field value from a register. */
4882 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_GET(value) (((value) & 0x00fc0000) >> 18)
4883 /* Produces a ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK register field value suitable for setting the register. */
4884 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET(value) (((value) << 18) & 0x00fc0000)
4885 
4886 /*
4887  * Field : cfg_t_param_act_to_act_diff_bg
4888  *
4889  * Active to activate timing on different bank groups, DDR4 only
4890  *
4891  * Field Access Macros:
4892  *
4893  */
4894 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
4895 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_LSB 24
4896 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
4897 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_MSB 29
4898 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
4899 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_WIDTH 6
4900 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value. */
4901 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET_MSK 0x3f000000
4902 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value. */
4903 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_CLR_MSK 0xc0ffffff
4904 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field. */
4905 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_RESET 0x0
4906 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG field value from a register. */
4907 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_GET(value) (((value) & 0x3f000000) >> 24)
4908 /* Produces a ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG register field value suitable for setting the register. */
4909 #define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET(value) (((value) << 24) & 0x3f000000)
4910 
4911 #ifndef __ASSEMBLY__
4912 /*
4913  * WARNING: The C register and register group struct declarations are provided for
4914  * convenience and illustrative purposes. They should, however, be used with
4915  * caution as the C language standard provides no guarantees about the alignment or
4916  * atomicity of device memory accesses. The recommended practice for writing
4917  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4918  * alt_write_word() functions.
4919  *
4920  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING0.
4921  */
4922 struct ALT_IO48_HMC_MMR_CALTIMING0_s
4923 {
4924  uint32_t cfg_t_param_act_to_rdwr : 6; /* ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR */
4925  uint32_t cfg_t_param_act_to_pch : 6; /* ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH */
4926  uint32_t cfg_t_param_act_to_act : 6; /* ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT */
4927  uint32_t cfg_t_param_act_to_act_diff_bank : 6; /* ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK */
4928  uint32_t cfg_t_param_act_to_act_diff_bg : 6; /* ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG */
4929  uint32_t : 2; /* *UNDEFINED* */
4930 };
4931 
4932 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING0. */
4933 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING0_s ALT_IO48_HMC_MMR_CALTIMING0_t;
4934 #endif /* __ASSEMBLY__ */
4935 
4936 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING0 register. */
4937 #define ALT_IO48_HMC_MMR_CALTIMING0_RESET 0x00000000
4938 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING0 register from the beginning of the component. */
4939 #define ALT_IO48_HMC_MMR_CALTIMING0_OFST 0x7c
4940 
4941 /*
4942  * Register : caltiming1
4943  *
4944  * Register Layout
4945  *
4946  * Bits | Access | Reset | Description
4947  * :--------|:-------|:------|:-----------------------------------------------------------
4948  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD
4949  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP
4950  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG
4951  * [23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR
4952  * [29:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP
4953  * [31:30] | ??? | 0x0 | *UNDEFINED*
4954  *
4955  */
4956 /*
4957  * Field : cfg_t_param_rd_to_rd
4958  *
4959  * Read to read command timing on same bank
4960  *
4961  * Field Access Macros:
4962  *
4963  */
4964 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
4965 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0
4966 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
4967 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5
4968 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
4969 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6
4970 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value. */
4971 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f
4972 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value. */
4973 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0
4974 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field. */
4975 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0
4976 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD field value from a register. */
4977 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0)
4978 /* Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value suitable for setting the register. */
4979 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f)
4980 
4981 /*
4982  * Field : cfg_t_param_rd_to_rd_diff_chip
4983  *
4984  * Read to read command timing on different chips
4985  *
4986  * Field Access Macros:
4987  *
4988  */
4989 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
4990 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6
4991 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
4992 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11
4993 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
4994 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6
4995 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value. */
4996 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0
4997 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value. */
4998 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f
4999 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field. */
5000 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0
5001 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP field value from a register. */
5002 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6)
5003 /* Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value suitable for setting the register. */
5004 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0)
5005 
5006 /*
5007  * Field : cfg_t_param_rd_to_rd_diff_bg
5008  *
5009  * Read to read command timing on different chips
5010  *
5011  * Field Access Macros:
5012  *
5013  */
5014 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
5015 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12
5016 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
5017 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17
5018 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
5019 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6
5020 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value. */
5021 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000
5022 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value. */
5023 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff
5024 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field. */
5025 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0
5026 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG field value from a register. */
5027 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12)
5028 /* Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value suitable for setting the register. */
5029 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000)
5030 
5031 /*
5032  * Field : cfg_t_param_rd_to_wr
5033  *
5034  * Write to read command timing on same bank
5035  *
5036  * Field Access Macros:
5037  *
5038  */
5039 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
5040 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18
5041 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
5042 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23
5043 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
5044 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6
5045 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value. */
5046 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000
5047 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value. */
5048 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff
5049 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field. */
5050 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0
5051 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR field value from a register. */
5052 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5053 /* Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value suitable for setting the register. */
5054 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5055 
5056 /*
5057  * Field : cfg_t_param_rd_to_wr_diff_chip
5058  *
5059  * Read to write command timing on different chips
5060  *
5061  * Field Access Macros:
5062  *
5063  */
5064 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
5065 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24
5066 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
5067 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29
5068 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
5069 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6
5070 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value. */
5071 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5072 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value. */
5073 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5074 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field. */
5075 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0
5076 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP field value from a register. */
5077 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5078 /* Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value suitable for setting the register. */
5079 #define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5080 
5081 #ifndef __ASSEMBLY__
5082 /*
5083  * WARNING: The C register and register group struct declarations are provided for
5084  * convenience and illustrative purposes. They should, however, be used with
5085  * caution as the C language standard provides no guarantees about the alignment or
5086  * atomicity of device memory accesses. The recommended practice for writing
5087  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5088  * alt_write_word() functions.
5089  *
5090  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING1.
5091  */
5092 struct ALT_IO48_HMC_MMR_CALTIMING1_s
5093 {
5094  uint32_t cfg_t_param_rd_to_rd : 6; /* ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD */
5095  uint32_t cfg_t_param_rd_to_rd_diff_chip : 6; /* ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP */
5096  uint32_t cfg_t_param_rd_to_rd_diff_bg : 6; /* ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG */
5097  uint32_t cfg_t_param_rd_to_wr : 6; /* ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR */
5098  uint32_t cfg_t_param_rd_to_wr_diff_chip : 6; /* ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP */
5099  uint32_t : 2; /* *UNDEFINED* */
5100 };
5101 
5102 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING1. */
5103 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING1_s ALT_IO48_HMC_MMR_CALTIMING1_t;
5104 #endif /* __ASSEMBLY__ */
5105 
5106 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING1 register. */
5107 #define ALT_IO48_HMC_MMR_CALTIMING1_RESET 0x00000000
5108 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING1 register from the beginning of the component. */
5109 #define ALT_IO48_HMC_MMR_CALTIMING1_OFST 0x80
5110 
5111 /*
5112  * Register : caltiming2
5113  *
5114  * Register Layout
5115  *
5116  * Bits | Access | Reset | Description
5117  * :--------|:-------|:------|:-----------------------------------------------------------
5118  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG
5119  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH
5120  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID
5121  * [23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR
5122  * [29:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP
5123  * [31:30] | ??? | 0x0 | *UNDEFINED*
5124  *
5125  */
5126 /*
5127  * Field : cfg_t_param_rd_to_wr_diff_bg
5128  *
5129  * Read to write command timing on different bank groups
5130  *
5131  * Field Access Macros:
5132  *
5133  */
5134 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
5135 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_LSB 0
5136 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
5137 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_MSB 5
5138 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
5139 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_WIDTH 6
5140 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value. */
5141 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5142 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value. */
5143 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5144 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field. */
5145 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_RESET 0x0
5146 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG field value from a register. */
5147 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5148 /* Produces a ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG register field value suitable for setting the register. */
5149 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5150 
5151 /*
5152  * Field : cfg_t_param_rd_to_pch
5153  *
5154  * Read to precharge command timing
5155  *
5156  * Field Access Macros:
5157  *
5158  */
5159 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
5160 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_LSB 6
5161 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
5162 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_MSB 11
5163 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
5164 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_WIDTH 6
5165 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value. */
5166 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET_MSK 0x00000fc0
5167 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value. */
5168 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_CLR_MSK 0xfffff03f
5169 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field. */
5170 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_RESET 0x0
5171 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH field value from a register. */
5172 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
5173 /* Produces a ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH register field value suitable for setting the register. */
5174 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
5175 
5176 /*
5177  * Field : cfg_t_param_rd_ap_to_valid
5178  *
5179  * Read command with autoprecharge to data valid timing
5180  *
5181  * Field Access Macros:
5182  *
5183  */
5184 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
5185 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_LSB 12
5186 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
5187 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_MSB 17
5188 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
5189 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_WIDTH 6
5190 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value. */
5191 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET_MSK 0x0003f000
5192 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value. */
5193 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_CLR_MSK 0xfffc0fff
5194 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field. */
5195 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_RESET 0x0
5196 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID field value from a register. */
5197 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5198 /* Produces a ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID register field value suitable for setting the register. */
5199 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5200 
5201 /*
5202  * Field : cfg_t_param_wr_to_wr
5203  *
5204  * Write to write command timing on same bank.
5205  *
5206  * Field Access Macros:
5207  *
5208  */
5209 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
5210 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_LSB 18
5211 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
5212 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_MSB 23
5213 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
5214 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_WIDTH 6
5215 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value. */
5216 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET_MSK 0x00fc0000
5217 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value. */
5218 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_CLR_MSK 0xff03ffff
5219 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field. */
5220 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_RESET 0x0
5221 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR field value from a register. */
5222 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5223 /* Produces a ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR register field value suitable for setting the register. */
5224 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5225 
5226 /*
5227  * Field : cfg_t_param_wr_to_wr_diff_chip
5228  *
5229  * Write to write command timing on different chips.
5230  *
5231  * Field Access Macros:
5232  *
5233  */
5234 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
5235 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_LSB 24
5236 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
5237 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_MSB 29
5238 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
5239 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH 6
5240 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value. */
5241 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5242 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value. */
5243 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5244 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field. */
5245 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_RESET 0x0
5246 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP field value from a register. */
5247 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5248 /* Produces a ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP register field value suitable for setting the register. */
5249 #define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5250 
5251 #ifndef __ASSEMBLY__
5252 /*
5253  * WARNING: The C register and register group struct declarations are provided for
5254  * convenience and illustrative purposes. They should, however, be used with
5255  * caution as the C language standard provides no guarantees about the alignment or
5256  * atomicity of device memory accesses. The recommended practice for writing
5257  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5258  * alt_write_word() functions.
5259  *
5260  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING2.
5261  */
5262 struct ALT_IO48_HMC_MMR_CALTIMING2_s
5263 {
5264  uint32_t cfg_t_param_rd_to_wr_diff_bg : 6; /* ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG */
5265  uint32_t cfg_t_param_rd_to_pch : 6; /* ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH */
5266  uint32_t cfg_t_param_rd_ap_to_valid : 6; /* ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID */
5267  uint32_t cfg_t_param_wr_to_wr : 6; /* ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR */
5268  uint32_t cfg_t_param_wr_to_wr_diff_chip : 6; /* ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP */
5269  uint32_t : 2; /* *UNDEFINED* */
5270 };
5271 
5272 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING2. */
5273 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING2_s ALT_IO48_HMC_MMR_CALTIMING2_t;
5274 #endif /* __ASSEMBLY__ */
5275 
5276 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING2 register. */
5277 #define ALT_IO48_HMC_MMR_CALTIMING2_RESET 0x00000000
5278 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING2 register from the beginning of the component. */
5279 #define ALT_IO48_HMC_MMR_CALTIMING2_OFST 0x84
5280 
5281 /*
5282  * Register : caltiming3
5283  *
5284  * Register Layout
5285  *
5286  * Bits | Access | Reset | Description
5287  * :--------|:-------|:------|:-----------------------------------------------------------
5288  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG
5289  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD
5290  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP
5291  * [23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG
5292  * [29:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH
5293  * [31:30] | ??? | 0x0 | *UNDEFINED*
5294  *
5295  */
5296 /*
5297  * Field : cfg_t_param_wr_to_wr_diff_bg
5298  *
5299  * Write to write command timing on different bank groups.
5300  *
5301  * Field Access Macros:
5302  *
5303  */
5304 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
5305 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_LSB 0
5306 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
5307 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_MSB 5
5308 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
5309 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_WIDTH 6
5310 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value. */
5311 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5312 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value. */
5313 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5314 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field. */
5315 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_RESET 0x0
5316 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG field value from a register. */
5317 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5318 /* Produces a ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG register field value suitable for setting the register. */
5319 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5320 
5321 /*
5322  * Field : cfg_t_param_wr_to_rd
5323  *
5324  * Write to read command timing.
5325  *
5326  * Field Access Macros:
5327  *
5328  */
5329 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
5330 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_LSB 6
5331 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
5332 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_MSB 11
5333 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
5334 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_WIDTH 6
5335 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value. */
5336 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET_MSK 0x00000fc0
5337 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value. */
5338 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_CLR_MSK 0xfffff03f
5339 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field. */
5340 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_RESET 0x0
5341 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD field value from a register. */
5342 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_GET(value) (((value) & 0x00000fc0) >> 6)
5343 /* Produces a ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD register field value suitable for setting the register. */
5344 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET(value) (((value) << 6) & 0x00000fc0)
5345 
5346 /*
5347  * Field : cfg_t_param_wr_to_rd_diff_chip
5348  *
5349  * Write to read command timing on different chips.
5350  *
5351  * Field Access Macros:
5352  *
5353  */
5354 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
5355 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_LSB 12
5356 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
5357 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_MSB 17
5358 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
5359 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH 6
5360 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value. */
5361 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET_MSK 0x0003f000
5362 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value. */
5363 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_CLR_MSK 0xfffc0fff
5364 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field. */
5365 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_RESET 0x0
5366 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP field value from a register. */
5367 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x0003f000) >> 12)
5368 /* Produces a ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP register field value suitable for setting the register. */
5369 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET(value) (((value) << 12) & 0x0003f000)
5370 
5371 /*
5372  * Field : cfg_t_param_wr_to_rd_diff_bg
5373  *
5374  * Write to read command timing on different bank groups
5375  *
5376  * Field Access Macros:
5377  *
5378  */
5379 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
5380 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_LSB 18
5381 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
5382 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_MSB 23
5383 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
5384 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_WIDTH 6
5385 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value. */
5386 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET_MSK 0x00fc0000
5387 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value. */
5388 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_CLR_MSK 0xff03ffff
5389 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field. */
5390 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_RESET 0x0
5391 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG field value from a register. */
5392 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_GET(value) (((value) & 0x00fc0000) >> 18)
5393 /* Produces a ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG register field value suitable for setting the register. */
5394 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET(value) (((value) << 18) & 0x00fc0000)
5395 
5396 /*
5397  * Field : cfg_t_param_wr_to_pch
5398  *
5399  * Write to precharge command timing.
5400  *
5401  * Field Access Macros:
5402  *
5403  */
5404 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
5405 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_LSB 24
5406 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
5407 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_MSB 29
5408 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
5409 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_WIDTH 6
5410 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value. */
5411 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET_MSK 0x3f000000
5412 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value. */
5413 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_CLR_MSK 0xc0ffffff
5414 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field. */
5415 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_RESET 0x0
5416 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH field value from a register. */
5417 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_GET(value) (((value) & 0x3f000000) >> 24)
5418 /* Produces a ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH register field value suitable for setting the register. */
5419 #define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET(value) (((value) << 24) & 0x3f000000)
5420 
5421 #ifndef __ASSEMBLY__
5422 /*
5423  * WARNING: The C register and register group struct declarations are provided for
5424  * convenience and illustrative purposes. They should, however, be used with
5425  * caution as the C language standard provides no guarantees about the alignment or
5426  * atomicity of device memory accesses. The recommended practice for writing
5427  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5428  * alt_write_word() functions.
5429  *
5430  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING3.
5431  */
5432 struct ALT_IO48_HMC_MMR_CALTIMING3_s
5433 {
5434  uint32_t cfg_t_param_wr_to_wr_diff_bg : 6; /* ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG */
5435  uint32_t cfg_t_param_wr_to_rd : 6; /* ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD */
5436  uint32_t cfg_t_param_wr_to_rd_diff_chip : 6; /* ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP */
5437  uint32_t cfg_t_param_wr_to_rd_diff_bg : 6; /* ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG */
5438  uint32_t cfg_t_param_wr_to_pch : 6; /* ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH */
5439  uint32_t : 2; /* *UNDEFINED* */
5440 };
5441 
5442 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING3. */
5443 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING3_s ALT_IO48_HMC_MMR_CALTIMING3_t;
5444 #endif /* __ASSEMBLY__ */
5445 
5446 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING3 register. */
5447 #define ALT_IO48_HMC_MMR_CALTIMING3_RESET 0x00000000
5448 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING3 register from the beginning of the component. */
5449 #define ALT_IO48_HMC_MMR_CALTIMING3_OFST 0x88
5450 
5451 /*
5452  * Register : caltiming4
5453  *
5454  * Register Layout
5455  *
5456  * Bits | Access | Reset | Description
5457  * :--------|:-------|:------|:---------------------------------------------------------
5458  * [5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID
5459  * [11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID
5460  * [17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID
5461  * [25:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID
5462  * [31:26] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID
5463  *
5464  */
5465 /*
5466  * Field : cfg_t_param_wr_ap_to_valid
5467  *
5468  * Write with autoprecharge to valid command timing.
5469  *
5470  * Field Access Macros:
5471  *
5472  */
5473 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
5474 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB 0
5475 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
5476 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB 5
5477 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
5478 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH 6
5479 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value. */
5480 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK 0x0000003f
5481 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value. */
5482 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK 0xffffffc0
5483 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field. */
5484 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET 0x0
5485 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID field value from a register. */
5486 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value) (((value) & 0x0000003f) >> 0)
5487 /* Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value suitable for setting the register. */
5488 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value) (((value) << 0) & 0x0000003f)
5489 
5490 /*
5491  * Field : cfg_t_param_pch_to_valid
5492  *
5493  * Precharge to valid command timing.
5494  *
5495  * Field Access Macros:
5496  *
5497  */
5498 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
5499 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB 6
5500 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
5501 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB 11
5502 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
5503 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH 6
5504 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value. */
5505 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK 0x00000fc0
5506 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value. */
5507 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK 0xfffff03f
5508 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field. */
5509 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET 0x0
5510 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID field value from a register. */
5511 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value) (((value) & 0x00000fc0) >> 6)
5512 /* Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value suitable for setting the register. */
5513 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value) (((value) << 6) & 0x00000fc0)
5514 
5515 /*
5516  * Field : cfg_t_param_pch_all_to_valid
5517  *
5518  * Precharge all to banks being ready for bank activation command.
5519  *
5520  * Field Access Macros:
5521  *
5522  */
5523 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
5524 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB 12
5525 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
5526 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB 17
5527 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
5528 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH 6
5529 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value. */
5530 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK 0x0003f000
5531 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value. */
5532 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK 0xfffc0fff
5533 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field. */
5534 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET 0x0
5535 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID field value from a register. */
5536 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5537 /* Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value suitable for setting the register. */
5538 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5539 
5540 /*
5541  * Field : cfg_t_param_arf_to_valid
5542  *
5543  * Auto Refresh to valid DRAM command window.
5544  *
5545  * Field Access Macros:
5546  *
5547  */
5548 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
5549 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB 18
5550 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
5551 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB 25
5552 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
5553 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH 8
5554 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value. */
5555 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK 0x03fc0000
5556 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value. */
5557 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK 0xfc03ffff
5558 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field. */
5559 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET 0x0
5560 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID field value from a register. */
5561 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value) (((value) & 0x03fc0000) >> 18)
5562 /* Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value suitable for setting the register. */
5563 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value) (((value) << 18) & 0x03fc0000)
5564 
5565 /*
5566  * Field : cfg_t_param_pdn_to_valid
5567  *
5568  * Power down to valid bank command window.
5569  *
5570  * Field Access Macros:
5571  *
5572  */
5573 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
5574 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB 26
5575 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
5576 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB 31
5577 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
5578 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH 6
5579 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value. */
5580 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK 0xfc000000
5581 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value. */
5582 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK 0x03ffffff
5583 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field. */
5584 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET 0x0
5585 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID field value from a register. */
5586 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value) (((value) & 0xfc000000) >> 26)
5587 /* Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value suitable for setting the register. */
5588 #define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value) (((value) << 26) & 0xfc000000)
5589 
5590 #ifndef __ASSEMBLY__
5591 /*
5592  * WARNING: The C register and register group struct declarations are provided for
5593  * convenience and illustrative purposes. They should, however, be used with
5594  * caution as the C language standard provides no guarantees about the alignment or
5595  * atomicity of device memory accesses. The recommended practice for writing
5596  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5597  * alt_write_word() functions.
5598  *
5599  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING4.
5600  */
5601 struct ALT_IO48_HMC_MMR_CALTIMING4_s
5602 {
5603  uint32_t cfg_t_param_wr_ap_to_valid : 6; /* ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID */
5604  uint32_t cfg_t_param_pch_to_valid : 6; /* ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID */
5605  uint32_t cfg_t_param_pch_all_to_valid : 6; /* ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID */
5606  uint32_t cfg_t_param_arf_to_valid : 8; /* ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID */
5607  uint32_t cfg_t_param_pdn_to_valid : 6; /* ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID */
5608 };
5609 
5610 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING4. */
5611 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING4_s ALT_IO48_HMC_MMR_CALTIMING4_t;
5612 #endif /* __ASSEMBLY__ */
5613 
5614 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING4 register. */
5615 #define ALT_IO48_HMC_MMR_CALTIMING4_RESET 0x00000000
5616 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING4 register from the beginning of the component. */
5617 #define ALT_IO48_HMC_MMR_CALTIMING4_OFST 0x8c
5618 
5619 /*
5620  * Register : caltiming5
5621  *
5622  * Register Layout
5623  *
5624  * Bits | Access | Reset | Description
5625  * :--------|:-------|:------|:------------------------------------------------------
5626  * [9:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID
5627  * [19:10] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL
5628  * [31:20] | ??? | 0x0 | *UNDEFINED*
5629  *
5630  */
5631 /*
5632  * Field : cfg_t_param_srf_to_valid
5633  *
5634  * Self-refresh to valid bank command window.
5635  *
5636  * Field Access Macros:
5637  *
5638  */
5639 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
5640 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB 0
5641 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
5642 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB 9
5643 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
5644 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH 10
5645 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value. */
5646 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK 0x000003ff
5647 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value. */
5648 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK 0xfffffc00
5649 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field. */
5650 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET 0x0
5651 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID field value from a register. */
5652 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value) (((value) & 0x000003ff) >> 0)
5653 /* Produces a ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value suitable for setting the register. */
5654 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value) (((value) << 0) & 0x000003ff)
5655 
5656 /*
5657  * Field : cfg_t_param_srf_to_zq_cal
5658  *
5659  * Self refresh to ZQ calibration window
5660  *
5661  * Field Access Macros:
5662  *
5663  */
5664 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
5665 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB 10
5666 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
5667 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB 19
5668 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
5669 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH 10
5670 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value. */
5671 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK 0x000ffc00
5672 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value. */
5673 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK 0xfff003ff
5674 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field. */
5675 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET 0x0
5676 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL field value from a register. */
5677 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value) (((value) & 0x000ffc00) >> 10)
5678 /* Produces a ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value suitable for setting the register. */
5679 #define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value) (((value) << 10) & 0x000ffc00)
5680 
5681 #ifndef __ASSEMBLY__
5682 /*
5683  * WARNING: The C register and register group struct declarations are provided for
5684  * convenience and illustrative purposes. They should, however, be used with
5685  * caution as the C language standard provides no guarantees about the alignment or
5686  * atomicity of device memory accesses. The recommended practice for writing
5687  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5688  * alt_write_word() functions.
5689  *
5690  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING5.
5691  */
5692 struct ALT_IO48_HMC_MMR_CALTIMING5_s
5693 {
5694  uint32_t cfg_t_param_srf_to_valid : 10; /* ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID */
5695  uint32_t cfg_t_param_srf_to_zq_cal : 10; /* ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL */
5696  uint32_t : 12; /* *UNDEFINED* */
5697 };
5698 
5699 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING5. */
5700 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING5_s ALT_IO48_HMC_MMR_CALTIMING5_t;
5701 #endif /* __ASSEMBLY__ */
5702 
5703 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING5 register. */
5704 #define ALT_IO48_HMC_MMR_CALTIMING5_RESET 0x00000000
5705 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING5 register from the beginning of the component. */
5706 #define ALT_IO48_HMC_MMR_CALTIMING5_OFST 0x90
5707 
5708 /*
5709  * Register : caltiming6
5710  *
5711  * Register Layout
5712  *
5713  * Bits | Access | Reset | Description
5714  * :--------|:-------|:------|:---------------------------------------------------
5715  * [12:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD
5716  * [28:13] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD
5717  * [31:29] | ??? | 0x0 | *UNDEFINED*
5718  *
5719  */
5720 /*
5721  * Field : cfg_t_param_arf_period
5722  *
5723  * Auto-refresh period
5724  *
5725  * Field Access Macros:
5726  *
5727  */
5728 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
5729 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_LSB 0
5730 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
5731 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_MSB 12
5732 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
5733 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_WIDTH 13
5734 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value. */
5735 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET_MSK 0x00001fff
5736 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value. */
5737 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_CLR_MSK 0xffffe000
5738 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field. */
5739 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_RESET 0x0
5740 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD field value from a register. */
5741 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_GET(value) (((value) & 0x00001fff) >> 0)
5742 /* Produces a ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD register field value suitable for setting the register. */
5743 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET(value) (((value) << 0) & 0x00001fff)
5744 
5745 /*
5746  * Field : cfg_t_param_pdn_period
5747  *
5748  * Clock power down recovery period.
5749  *
5750  * Field Access Macros:
5751  *
5752  */
5753 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
5754 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_LSB 13
5755 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
5756 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_MSB 28
5757 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
5758 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_WIDTH 16
5759 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value. */
5760 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET_MSK 0x1fffe000
5761 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value. */
5762 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_CLR_MSK 0xe0001fff
5763 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field. */
5764 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_RESET 0x0
5765 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD field value from a register. */
5766 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_GET(value) (((value) & 0x1fffe000) >> 13)
5767 /* Produces a ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD register field value suitable for setting the register. */
5768 #define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET(value) (((value) << 13) & 0x1fffe000)
5769 
5770 #ifndef __ASSEMBLY__
5771 /*
5772  * WARNING: The C register and register group struct declarations are provided for
5773  * convenience and illustrative purposes. They should, however, be used with
5774  * caution as the C language standard provides no guarantees about the alignment or
5775  * atomicity of device memory accesses. The recommended practice for writing
5776  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5777  * alt_write_word() functions.
5778  *
5779  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING6.
5780  */
5781 struct ALT_IO48_HMC_MMR_CALTIMING6_s
5782 {
5783  uint32_t cfg_t_param_arf_period : 13; /* ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD */
5784  uint32_t cfg_t_param_pdn_period : 16; /* ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD */
5785  uint32_t : 3; /* *UNDEFINED* */
5786 };
5787 
5788 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING6. */
5789 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING6_s ALT_IO48_HMC_MMR_CALTIMING6_t;
5790 #endif /* __ASSEMBLY__ */
5791 
5792 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING6 register. */
5793 #define ALT_IO48_HMC_MMR_CALTIMING6_RESET 0x00000000
5794 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING6 register from the beginning of the component. */
5795 #define ALT_IO48_HMC_MMR_CALTIMING6_OFST 0x94
5796 
5797 /*
5798  * Register : caltiming7
5799  *
5800  * Register Layout
5801  *
5802  * Bits | Access | Reset | Description
5803  * :--------|:-------|:------|:------------------------------------------------------
5804  * [8:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID
5805  * [15:9] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID
5806  * [19:16] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID
5807  * [29:20] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID
5808  * [31:30] | ??? | 0x0 | *UNDEFINED*
5809  *
5810  */
5811 /*
5812  * Field : cfg_t_param_zqcl_to_valid
5813  *
5814  * Long ZQ calibration to valid
5815  *
5816  * Field Access Macros:
5817  *
5818  */
5819 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
5820 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB 0
5821 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
5822 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB 8
5823 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
5824 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH 9
5825 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value. */
5826 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK 0x000001ff
5827 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value. */
5828 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK 0xfffffe00
5829 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field. */
5830 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET 0x0
5831 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID field value from a register. */
5832 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value) (((value) & 0x000001ff) >> 0)
5833 /* Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value suitable for setting the register. */
5834 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value) (((value) << 0) & 0x000001ff)
5835 
5836 /*
5837  * Field : cfg_t_param_zqcs_to_valid
5838  *
5839  * Short ZQ calibration to valid
5840  *
5841  * Field Access Macros:
5842  *
5843  */
5844 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
5845 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB 9
5846 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
5847 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB 15
5848 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
5849 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH 7
5850 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value. */
5851 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK 0x0000fe00
5852 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value. */
5853 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK 0xffff01ff
5854 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field. */
5855 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET 0x0
5856 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID field value from a register. */
5857 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value) (((value) & 0x0000fe00) >> 9)
5858 /* Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value suitable for setting the register. */
5859 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value) (((value) << 9) & 0x0000fe00)
5860 
5861 /*
5862  * Field : cfg_t_param_mrs_to_valid
5863  *
5864  * Mode Register Setting to valid
5865  *
5866  * Field Access Macros:
5867  *
5868  */
5869 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
5870 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB 16
5871 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
5872 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB 19
5873 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
5874 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH 4
5875 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value. */
5876 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK 0x000f0000
5877 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value. */
5878 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK 0xfff0ffff
5879 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field. */
5880 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET 0x0
5881 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID field value from a register. */
5882 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value) (((value) & 0x000f0000) >> 16)
5883 /* Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value suitable for setting the register. */
5884 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value) (((value) << 16) & 0x000f0000)
5885 
5886 /*
5887  * Field : cfg_t_param_mps_to_valid
5888  *
5889  * Timing parameter for Maximum Power Saving to any valid command. tXMP
5890  *
5891  * Field Access Macros:
5892  *
5893  */
5894 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
5895 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB 20
5896 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
5897 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB 29
5898 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
5899 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH 10
5900 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value. */
5901 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK 0x3ff00000
5902 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value. */
5903 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK 0xc00fffff
5904 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field. */
5905 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET 0x0
5906 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID field value from a register. */
5907 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value) (((value) & 0x3ff00000) >> 20)
5908 /* Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value suitable for setting the register. */
5909 #define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value) (((value) << 20) & 0x3ff00000)
5910 
5911 #ifndef __ASSEMBLY__
5912 /*
5913  * WARNING: The C register and register group struct declarations are provided for
5914  * convenience and illustrative purposes. They should, however, be used with
5915  * caution as the C language standard provides no guarantees about the alignment or
5916  * atomicity of device memory accesses. The recommended practice for writing
5917  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5918  * alt_write_word() functions.
5919  *
5920  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING7.
5921  */
5922 struct ALT_IO48_HMC_MMR_CALTIMING7_s
5923 {
5924  uint32_t cfg_t_param_zqcl_to_valid : 9; /* ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID */
5925  uint32_t cfg_t_param_zqcs_to_valid : 7; /* ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID */
5926  uint32_t cfg_t_param_mrs_to_valid : 4; /* ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID */
5927  uint32_t cfg_t_param_mps_to_valid : 10; /* ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID */
5928  uint32_t : 2; /* *UNDEFINED* */
5929 };
5930 
5931 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING7. */
5932 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING7_s ALT_IO48_HMC_MMR_CALTIMING7_t;
5933 #endif /* __ASSEMBLY__ */
5934 
5935 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING7 register. */
5936 #define ALT_IO48_HMC_MMR_CALTIMING7_RESET 0x00000000
5937 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING7 register from the beginning of the component. */
5938 #define ALT_IO48_HMC_MMR_CALTIMING7_OFST 0x98
5939 
5940 /*
5941  * Register : caltiming8
5942  *
5943  * Register Layout
5944  *
5945  * Bits | Access | Reset | Description
5946  * :--------|:-------|:------|:-----------------------------------------------------------------
5947  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID
5948  * [8:4] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID
5949  * [12:9] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE
5950  * [16:13] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS
5951  * [19:17] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY
5952  * [27:20] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID
5953  * [31:28] | ??? | 0x0 | *UNDEFINED*
5954  *
5955  */
5956 /*
5957  * Field : cfg_t_param_mrr_to_valid
5958  *
5959  * Timing parameter for Mode Register Read to any valid command
5960  *
5961  * Field Access Macros:
5962  *
5963  */
5964 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
5965 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB 0
5966 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
5967 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB 3
5968 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
5969 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH 4
5970 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value. */
5971 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK 0x0000000f
5972 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value. */
5973 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK 0xfffffff0
5974 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field. */
5975 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET 0x0
5976 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID field value from a register. */
5977 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value) (((value) & 0x0000000f) >> 0)
5978 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value suitable for setting the register. */
5979 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value) (((value) << 0) & 0x0000000f)
5980 
5981 /*
5982  * Field : cfg_t_param_mpr_to_valid
5983  *
5984  * Timing parameter for Multi Purpose Register Read to any valid command
5985  *
5986  * Field Access Macros:
5987  *
5988  */
5989 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
5990 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB 4
5991 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
5992 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB 8
5993 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
5994 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH 5
5995 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value. */
5996 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK 0x000001f0
5997 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value. */
5998 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK 0xfffffe0f
5999 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field. */
6000 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET 0x0
6001 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID field value from a register. */
6002 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value) (((value) & 0x000001f0) >> 4)
6003 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value suitable for setting the register. */
6004 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value) (((value) << 4) & 0x000001f0)
6005 
6006 /*
6007  * Field : cfg_t_param_mps_exit_cs_to_cke
6008  *
6009  * Timing parameter for exit Maximum Power Saving. Timing requirement for CS
6010  * assertion vs CKE de-assertion. tMPX_S
6011  *
6012  * Field Access Macros:
6013  *
6014  */
6015 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
6016 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB 9
6017 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
6018 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB 12
6019 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
6020 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH 4
6021 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value. */
6022 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK 0x00001e00
6023 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value. */
6024 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK 0xffffe1ff
6025 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field. */
6026 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET 0x0
6027 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE field value from a register. */
6028 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value) (((value) & 0x00001e00) >> 9)
6029 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value suitable for setting the register. */
6030 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value) (((value) << 9) & 0x00001e00)
6031 
6032 /*
6033  * Field : cfg_t_param_mps_exit_cke_to_cs
6034  *
6035  * Timing parameter for exit Maximum Power Saving. Timing requirement for CKE de-
6036  * assertion vs CS de-assertion. tMPX_LH
6037  *
6038  * Field Access Macros:
6039  *
6040  */
6041 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
6042 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB 13
6043 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
6044 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB 16
6045 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
6046 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH 4
6047 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value. */
6048 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK 0x0001e000
6049 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value. */
6050 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK 0xfffe1fff
6051 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field. */
6052 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET 0x0
6053 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS field value from a register. */
6054 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value) (((value) & 0x0001e000) >> 13)
6055 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value suitable for setting the register. */
6056 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value) (((value) << 13) & 0x0001e000)
6057 
6058 /*
6059  * Field : cfg_t_param_rld3_multibank_ref_delay
6060  *
6061  * RLD3 Refresh to Refresh Delay for all sequences
6062  *
6063  * Field Access Macros:
6064  *
6065  */
6066 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
6067 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB 17
6068 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
6069 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB 19
6070 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
6071 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH 3
6072 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value. */
6073 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK 0x000e0000
6074 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value. */
6075 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK 0xfff1ffff
6076 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field. */
6077 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET 0x0
6078 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY field value from a register. */
6079 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value) (((value) & 0x000e0000) >> 17)
6080 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value suitable for setting the register. */
6081 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value) (((value) << 17) & 0x000e0000)
6082 
6083 /*
6084  * Field : cfg_t_param_mmr_cmd_to_valid
6085  *
6086  * MMR cmd to valid delay
6087  *
6088  * Field Access Macros:
6089  *
6090  */
6091 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
6092 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB 20
6093 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
6094 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB 27
6095 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
6096 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH 8
6097 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value. */
6098 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK 0x0ff00000
6099 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value. */
6100 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK 0xf00fffff
6101 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field. */
6102 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET 0x0
6103 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID field value from a register. */
6104 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value) (((value) & 0x0ff00000) >> 20)
6105 /* Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value suitable for setting the register. */
6106 #define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value) (((value) << 20) & 0x0ff00000)
6107 
6108 #ifndef __ASSEMBLY__
6109 /*
6110  * WARNING: The C register and register group struct declarations are provided for
6111  * convenience and illustrative purposes. They should, however, be used with
6112  * caution as the C language standard provides no guarantees about the alignment or
6113  * atomicity of device memory accesses. The recommended practice for writing
6114  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6115  * alt_write_word() functions.
6116  *
6117  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING8.
6118  */
6119 struct ALT_IO48_HMC_MMR_CALTIMING8_s
6120 {
6121  uint32_t cfg_t_param_mrr_to_valid : 4; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID */
6122  uint32_t cfg_t_param_mpr_to_valid : 5; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID */
6123  uint32_t cfg_t_param_mps_exit_cs_to_cke : 4; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE */
6124  uint32_t cfg_t_param_mps_exit_cke_to_cs : 4; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS */
6125  uint32_t cfg_t_param_rld3_multibank_ref_delay : 3; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY */
6126  uint32_t cfg_t_param_mmr_cmd_to_valid : 8; /* ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID */
6127  uint32_t : 4; /* *UNDEFINED* */
6128 };
6129 
6130 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING8. */
6131 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING8_s ALT_IO48_HMC_MMR_CALTIMING8_t;
6132 #endif /* __ASSEMBLY__ */
6133 
6134 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING8 register. */
6135 #define ALT_IO48_HMC_MMR_CALTIMING8_RESET 0x00000000
6136 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING8 register from the beginning of the component. */
6137 #define ALT_IO48_HMC_MMR_CALTIMING8_OFST 0x9c
6138 
6139 /*
6140  * Register : caltiming9
6141  *
6142  * Register Layout
6143  *
6144  * Bits | Access | Reset | Description
6145  * :-------|:-------|:------|:-----------------------------------------------------
6146  * [7:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT
6147  * [31:8] | ??? | 0x0 | *UNDEFINED*
6148  *
6149  */
6150 /*
6151  * Field : cfg_t_param_4_act_to_act
6152  *
6153  * The four-activate window timing parameter.
6154  *
6155  * Field Access Macros:
6156  *
6157  */
6158 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
6159 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_LSB 0
6160 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
6161 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_MSB 7
6162 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
6163 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_WIDTH 8
6164 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value. */
6165 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET_MSK 0x000000ff
6166 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value. */
6167 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_CLR_MSK 0xffffff00
6168 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field. */
6169 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_RESET 0x0
6170 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT field value from a register. */
6171 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6172 /* Produces a ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT register field value suitable for setting the register. */
6173 #define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6174 
6175 #ifndef __ASSEMBLY__
6176 /*
6177  * WARNING: The C register and register group struct declarations are provided for
6178  * convenience and illustrative purposes. They should, however, be used with
6179  * caution as the C language standard provides no guarantees about the alignment or
6180  * atomicity of device memory accesses. The recommended practice for writing
6181  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6182  * alt_write_word() functions.
6183  *
6184  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING9.
6185  */
6186 struct ALT_IO48_HMC_MMR_CALTIMING9_s
6187 {
6188  uint32_t cfg_t_param_4_act_to_act : 8; /* ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT */
6189  uint32_t : 24; /* *UNDEFINED* */
6190 };
6191 
6192 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING9. */
6193 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING9_s ALT_IO48_HMC_MMR_CALTIMING9_t;
6194 #endif /* __ASSEMBLY__ */
6195 
6196 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING9 register. */
6197 #define ALT_IO48_HMC_MMR_CALTIMING9_RESET 0x00000000
6198 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING9 register from the beginning of the component. */
6199 #define ALT_IO48_HMC_MMR_CALTIMING9_OFST 0xa0
6200 
6201 /*
6202  * Register : caltiming10
6203  *
6204  * Register Layout
6205  *
6206  * Bits | Access | Reset | Description
6207  * :-------|:-------|:------|:-------------------------------------------------------
6208  * [7:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT
6209  * [31:8] | ??? | 0x0 | *UNDEFINED*
6210  *
6211  */
6212 /*
6213  * Field : cfg_t_param_16_act_to_act
6214  *
6215  * The 16-activate window timing parameter (RLD3).
6216  *
6217  * Field Access Macros:
6218  *
6219  */
6220 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
6221 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_LSB 0
6222 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
6223 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_MSB 7
6224 /* The width in bits of the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
6225 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_WIDTH 8
6226 /* The mask used to set the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value. */
6227 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET_MSK 0x000000ff
6228 /* The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value. */
6229 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_CLR_MSK 0xffffff00
6230 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field. */
6231 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_RESET 0x0
6232 /* Extracts the ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT field value from a register. */
6233 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6234 /* Produces a ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT register field value suitable for setting the register. */
6235 #define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6236 
6237 #ifndef __ASSEMBLY__
6238 /*
6239  * WARNING: The C register and register group struct declarations are provided for
6240  * convenience and illustrative purposes. They should, however, be used with
6241  * caution as the C language standard provides no guarantees about the alignment or
6242  * atomicity of device memory accesses. The recommended practice for writing
6243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6244  * alt_write_word() functions.
6245  *
6246  * The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING10.
6247  */
6248 struct ALT_IO48_HMC_MMR_CALTIMING10_s
6249 {
6250  uint32_t cfg_t_param_16_act_to_act : 8; /* ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT */
6251  uint32_t : 24; /* *UNDEFINED* */
6252 };
6253 
6254 /* The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING10. */
6255 typedef volatile struct ALT_IO48_HMC_MMR_CALTIMING10_s ALT_IO48_HMC_MMR_CALTIMING10_t;
6256 #endif /* __ASSEMBLY__ */
6257 
6258 /* The reset value of the ALT_IO48_HMC_MMR_CALTIMING10 register. */
6259 #define ALT_IO48_HMC_MMR_CALTIMING10_RESET 0x00000000
6260 /* The byte offset of the ALT_IO48_HMC_MMR_CALTIMING10 register from the beginning of the component. */
6261 #define ALT_IO48_HMC_MMR_CALTIMING10_OFST 0xa4
6262 
6263 /*
6264  * Register : dramaddrw
6265  *
6266  * Register Layout
6267  *
6268  * Bits | Access | Reset | Description
6269  * :--------|:-------|:------|:-----------------------------------------------------
6270  * [4:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH
6271  * [9:5] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH
6272  * [13:10] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH
6273  * [15:14] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH
6274  * [18:16] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH
6275  * [31:19] | ??? | 0x0 | *UNDEFINED*
6276  *
6277  */
6278 /*
6279  * Field : cfg_col_addr_width
6280  *
6281  * The number of column address bits for the memory devices in your memory
6282  * interface.
6283  *
6284  * Field Access Macros:
6285  *
6286  */
6287 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
6288 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB 0
6289 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
6290 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB 4
6291 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
6292 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH 5
6293 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value. */
6294 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
6295 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value. */
6296 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
6297 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field. */
6298 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET 0x0
6299 /* Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH field value from a register. */
6300 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
6301 /* Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value suitable for setting the register. */
6302 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
6303 
6304 /*
6305  * Field : cfg_row_addr_width
6306  *
6307  * The number of row address bits for the memory devices in your memory interface.
6308  *
6309  * Field Access Macros:
6310  *
6311  */
6312 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
6313 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB 5
6314 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
6315 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB 9
6316 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
6317 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH 5
6318 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value. */
6319 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
6320 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value. */
6321 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
6322 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field. */
6323 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET 0x0
6324 /* Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH field value from a register. */
6325 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
6326 /* Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value suitable for setting the register. */
6327 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
6328 
6329 /*
6330  * Field : cfg_bank_addr_width
6331  *
6332  * The number of bank address bits for the memory devices in your memory interface.
6333  *
6334  * Field Access Macros:
6335  *
6336  */
6337 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
6338 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB 10
6339 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
6340 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB 13
6341 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
6342 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH 4
6343 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value. */
6344 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
6345 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value. */
6346 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
6347 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field. */
6348 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET 0x0
6349 /* Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH field value from a register. */
6350 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
6351 /* Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value suitable for setting the register. */
6352 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
6353 
6354 /*
6355  * Field : cfg_bank_group_addr_width
6356  *
6357  * The number of bank group address bits for the memory devices in your memory
6358  * interface.
6359  *
6360  * Field Access Macros:
6361  *
6362  */
6363 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
6364 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
6365 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
6366 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
6367 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
6368 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
6369 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
6370 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
6371 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value. */
6372 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
6373 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field. */
6374 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
6375 /* Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH field value from a register. */
6376 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
6377 /* Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value suitable for setting the register. */
6378 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
6379 
6380 /*
6381  * Field : cfg_cs_addr_width
6382  *
6383  * The number of chip select address bits for the memory devices in your memory
6384  * interface.
6385  *
6386  * Field Access Macros:
6387  *
6388  */
6389 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
6390 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB 16
6391 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
6392 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB 18
6393 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
6394 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH 3
6395 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value. */
6396 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
6397 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value. */
6398 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
6399 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field. */
6400 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET 0x0
6401 /* Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH field value from a register. */
6402 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
6403 /* Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value suitable for setting the register. */
6404 #define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
6405 
6406 #ifndef __ASSEMBLY__
6407 /*
6408  * WARNING: The C register and register group struct declarations are provided for
6409  * convenience and illustrative purposes. They should, however, be used with
6410  * caution as the C language standard provides no guarantees about the alignment or
6411  * atomicity of device memory accesses. The recommended practice for writing
6412  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6413  * alt_write_word() functions.
6414  *
6415  * The struct declaration for register ALT_IO48_HMC_MMR_DRAMADDRW.
6416  */
6417 struct ALT_IO48_HMC_MMR_DRAMADDRW_s
6418 {
6419  uint32_t cfg_col_addr_width : 5; /* ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH */
6420  uint32_t cfg_row_addr_width : 5; /* ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH */
6421  uint32_t cfg_bank_addr_width : 4; /* ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH */
6422  uint32_t cfg_bank_group_addr_width : 2; /* ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH */
6423  uint32_t cfg_cs_addr_width : 3; /* ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH */
6424  uint32_t : 13; /* *UNDEFINED* */
6425 };
6426 
6427 /* The typedef declaration for register ALT_IO48_HMC_MMR_DRAMADDRW. */
6428 typedef volatile struct ALT_IO48_HMC_MMR_DRAMADDRW_s ALT_IO48_HMC_MMR_DRAMADDRW_t;
6429 #endif /* __ASSEMBLY__ */
6430 
6431 /* The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW register. */
6432 #define ALT_IO48_HMC_MMR_DRAMADDRW_RESET 0x00000000
6433 /* The byte offset of the ALT_IO48_HMC_MMR_DRAMADDRW register from the beginning of the component. */
6434 #define ALT_IO48_HMC_MMR_DRAMADDRW_OFST 0xa8
6435 
6436 /*
6437  * Register : sideband0
6438  *
6439  * Register Layout
6440  *
6441  * Bits | Access | Reset | Description
6442  * :-------|:-------|:------|:------------------------------------------
6443  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER
6444  * [31:1] | ??? | 0x0 | *UNDEFINED*
6445  *
6446  */
6447 /*
6448  * Field : mr_cmd_trigger
6449  *
6450  * Write to 1 to trigger the execution of the mode register command. It
6451  *
6452  * Field Access Macros:
6453  *
6454  */
6455 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field. */
6456 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_LSB 0
6457 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field. */
6458 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_MSB 0
6459 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field. */
6460 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_WIDTH 1
6461 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field value. */
6462 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET_MSK 0x00000001
6463 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field value. */
6464 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_CLR_MSK 0xfffffffe
6465 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field. */
6466 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_RESET 0x0
6467 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER field value from a register. */
6468 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_GET(value) (((value) & 0x00000001) >> 0)
6469 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER register field value suitable for setting the register. */
6470 #define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET(value) (((value) << 0) & 0x00000001)
6471 
6472 #ifndef __ASSEMBLY__
6473 /*
6474  * WARNING: The C register and register group struct declarations are provided for
6475  * convenience and illustrative purposes. They should, however, be used with
6476  * caution as the C language standard provides no guarantees about the alignment or
6477  * atomicity of device memory accesses. The recommended practice for writing
6478  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6479  * alt_write_word() functions.
6480  *
6481  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND0.
6482  */
6483 struct ALT_IO48_HMC_MMR_SIDEBAND0_s
6484 {
6485  uint32_t mr_cmd_trigger : 1; /* ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER */
6486  uint32_t : 31; /* *UNDEFINED* */
6487 };
6488 
6489 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND0. */
6490 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND0_s ALT_IO48_HMC_MMR_SIDEBAND0_t;
6491 #endif /* __ASSEMBLY__ */
6492 
6493 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND0 register. */
6494 #define ALT_IO48_HMC_MMR_SIDEBAND0_RESET 0x00000000
6495 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND0 register from the beginning of the component. */
6496 #define ALT_IO48_HMC_MMR_SIDEBAND0_OFST 0xac
6497 
6498 /*
6499  * Register : sideband1
6500  *
6501  * Register Layout
6502  *
6503  * Bits | Access | Reset | Description
6504  * :-------|:-------|:------|:-------------------------------------------
6505  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ
6506  * [31:4] | ??? | 0x0 | *UNDEFINED*
6507  *
6508  */
6509 /*
6510  * Field : mmr_refresh_req
6511  *
6512  * When asserted, indicates Refresh request to the specific rank. Each bit
6513  * corresponds to each rank. Controller clear this bit to
6514  *
6515  * Field Access Macros:
6516  *
6517  */
6518 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field. */
6519 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_LSB 0
6520 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field. */
6521 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_MSB 3
6522 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field. */
6523 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_WIDTH 4
6524 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field value. */
6525 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET_MSK 0x0000000f
6526 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field value. */
6527 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_CLR_MSK 0xfffffff0
6528 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field. */
6529 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_RESET 0x0
6530 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ field value from a register. */
6531 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6532 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ register field value suitable for setting the register. */
6533 #define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6534 
6535 #ifndef __ASSEMBLY__
6536 /*
6537  * WARNING: The C register and register group struct declarations are provided for
6538  * convenience and illustrative purposes. They should, however, be used with
6539  * caution as the C language standard provides no guarantees about the alignment or
6540  * atomicity of device memory accesses. The recommended practice for writing
6541  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6542  * alt_write_word() functions.
6543  *
6544  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND1.
6545  */
6546 struct ALT_IO48_HMC_MMR_SIDEBAND1_s
6547 {
6548  uint32_t mmr_refresh_req : 4; /* ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ */
6549  uint32_t : 28; /* *UNDEFINED* */
6550 };
6551 
6552 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND1. */
6553 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND1_s ALT_IO48_HMC_MMR_SIDEBAND1_t;
6554 #endif /* __ASSEMBLY__ */
6555 
6556 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND1 register. */
6557 #define ALT_IO48_HMC_MMR_SIDEBAND1_RESET 0x00000000
6558 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND1 register from the beginning of the component. */
6559 #define ALT_IO48_HMC_MMR_SIDEBAND1_OFST 0xb0
6560 
6561 /*
6562  * Register : sideband2
6563  *
6564  * Register Layout
6565  *
6566  * Bits | Access | Reset | Description
6567  * :-------|:-------|:------|:----------------------------------------------
6568  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ
6569  * [31:1] | ??? | 0x0 | *UNDEFINED*
6570  *
6571  */
6572 /*
6573  * Field : mmr_zqcal_long_req
6574  *
6575  * When asserted, indicates long ZQ cal request. This bit is write clear
6576  *
6577  * Field Access Macros:
6578  *
6579  */
6580 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
6581 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_LSB 0
6582 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
6583 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_MSB 0
6584 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
6585 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_WIDTH 1
6586 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value. */
6587 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET_MSK 0x00000001
6588 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value. */
6589 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_CLR_MSK 0xfffffffe
6590 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field. */
6591 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_RESET 0x0
6592 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ field value from a register. */
6593 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_GET(value) (((value) & 0x00000001) >> 0)
6594 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ register field value suitable for setting the register. */
6595 #define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET(value) (((value) << 0) & 0x00000001)
6596 
6597 #ifndef __ASSEMBLY__
6598 /*
6599  * WARNING: The C register and register group struct declarations are provided for
6600  * convenience and illustrative purposes. They should, however, be used with
6601  * caution as the C language standard provides no guarantees about the alignment or
6602  * atomicity of device memory accesses. The recommended practice for writing
6603  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6604  * alt_write_word() functions.
6605  *
6606  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND2.
6607  */
6608 struct ALT_IO48_HMC_MMR_SIDEBAND2_s
6609 {
6610  uint32_t mmr_zqcal_long_req : 1; /* ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ */
6611  uint32_t : 31; /* *UNDEFINED* */
6612 };
6613 
6614 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND2. */
6615 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND2_s ALT_IO48_HMC_MMR_SIDEBAND2_t;
6616 #endif /* __ASSEMBLY__ */
6617 
6618 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND2 register. */
6619 #define ALT_IO48_HMC_MMR_SIDEBAND2_RESET 0x00000000
6620 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND2 register from the beginning of the component. */
6621 #define ALT_IO48_HMC_MMR_SIDEBAND2_OFST 0xb4
6622 
6623 /*
6624  * Register : sideband3
6625  *
6626  * Register Layout
6627  *
6628  * Bits | Access | Reset | Description
6629  * :-------|:-------|:------|:-----------------------------------------------
6630  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ
6631  * [31:1] | ??? | 0x0 | *UNDEFINED*
6632  *
6633  */
6634 /*
6635  * Field : mmr_zqcal_short_req
6636  *
6637  * When asserted, indicates short ZQ cal request. This bit is write clear
6638  *
6639  * Field Access Macros:
6640  *
6641  */
6642 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
6643 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_LSB 0
6644 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
6645 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_MSB 0
6646 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
6647 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_WIDTH 1
6648 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value. */
6649 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET_MSK 0x00000001
6650 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value. */
6651 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_CLR_MSK 0xfffffffe
6652 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field. */
6653 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_RESET 0x0
6654 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ field value from a register. */
6655 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_GET(value) (((value) & 0x00000001) >> 0)
6656 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ register field value suitable for setting the register. */
6657 #define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET(value) (((value) << 0) & 0x00000001)
6658 
6659 #ifndef __ASSEMBLY__
6660 /*
6661  * WARNING: The C register and register group struct declarations are provided for
6662  * convenience and illustrative purposes. They should, however, be used with
6663  * caution as the C language standard provides no guarantees about the alignment or
6664  * atomicity of device memory accesses. The recommended practice for writing
6665  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6666  * alt_write_word() functions.
6667  *
6668  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND3.
6669  */
6670 struct ALT_IO48_HMC_MMR_SIDEBAND3_s
6671 {
6672  uint32_t mmr_zqcal_short_req : 1; /* ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ */
6673  uint32_t : 31; /* *UNDEFINED* */
6674 };
6675 
6676 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND3. */
6677 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND3_s ALT_IO48_HMC_MMR_SIDEBAND3_t;
6678 #endif /* __ASSEMBLY__ */
6679 
6680 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND3 register. */
6681 #define ALT_IO48_HMC_MMR_SIDEBAND3_RESET 0x00000000
6682 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND3 register from the beginning of the component. */
6683 #define ALT_IO48_HMC_MMR_SIDEBAND3_OFST 0xb8
6684 
6685 /*
6686  * Register : sideband4
6687  *
6688  * Register Layout
6689  *
6690  * Bits | Access | Reset | Description
6691  * :-------|:-------|:------|:---------------------------------------------
6692  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ
6693  * [31:4] | ??? | 0x0 | *UNDEFINED*
6694  *
6695  */
6696 /*
6697  * Field : mmr_self_rfsh_req
6698  *
6699  * When asserted, indicates self refresh request to the specific rank. Each bit
6700  * corresponds to each rank. These bits are write clear
6701  *
6702  * Field Access Macros:
6703  *
6704  */
6705 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
6706 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_LSB 0
6707 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
6708 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_MSB 3
6709 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
6710 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_WIDTH 4
6711 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field value. */
6712 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET_MSK 0x0000000f
6713 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field value. */
6714 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_CLR_MSK 0xfffffff0
6715 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field. */
6716 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_RESET 0x0
6717 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ field value from a register. */
6718 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6719 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ register field value suitable for setting the register. */
6720 #define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6721 
6722 #ifndef __ASSEMBLY__
6723 /*
6724  * WARNING: The C register and register group struct declarations are provided for
6725  * convenience and illustrative purposes. They should, however, be used with
6726  * caution as the C language standard provides no guarantees about the alignment or
6727  * atomicity of device memory accesses. The recommended practice for writing
6728  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6729  * alt_write_word() functions.
6730  *
6731  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND4.
6732  */
6733 struct ALT_IO48_HMC_MMR_SIDEBAND4_s
6734 {
6735  uint32_t mmr_self_rfsh_req : 4; /* ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ */
6736  uint32_t : 28; /* *UNDEFINED* */
6737 };
6738 
6739 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND4. */
6740 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND4_s ALT_IO48_HMC_MMR_SIDEBAND4_t;
6741 #endif /* __ASSEMBLY__ */
6742 
6743 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND4 register. */
6744 #define ALT_IO48_HMC_MMR_SIDEBAND4_RESET 0x00000000
6745 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND4 register from the beginning of the component. */
6746 #define ALT_IO48_HMC_MMR_SIDEBAND4_OFST 0xbc
6747 
6748 /*
6749  * Register : sideband5
6750  *
6751  * Register Layout
6752  *
6753  * Bits | Access | Reset | Description
6754  * :-------|:-------|:------|:-------------------------------------------
6755  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ
6756  * [31:1] | ??? | 0x0 | *UNDEFINED*
6757  *
6758  */
6759 /*
6760  * Field : mmr_dpd_mps_req
6761  *
6762  * When asserted, indicates deep power down or max power saving request. This bit
6763  * is write clear
6764  *
6765  * Field Access Macros:
6766  *
6767  */
6768 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
6769 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_LSB 0
6770 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
6771 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_MSB 0
6772 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
6773 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_WIDTH 1
6774 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field value. */
6775 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET_MSK 0x00000001
6776 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field value. */
6777 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_CLR_MSK 0xfffffffe
6778 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field. */
6779 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_RESET 0x0
6780 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ field value from a register. */
6781 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_GET(value) (((value) & 0x00000001) >> 0)
6782 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ register field value suitable for setting the register. */
6783 #define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET(value) (((value) << 0) & 0x00000001)
6784 
6785 #ifndef __ASSEMBLY__
6786 /*
6787  * WARNING: The C register and register group struct declarations are provided for
6788  * convenience and illustrative purposes. They should, however, be used with
6789  * caution as the C language standard provides no guarantees about the alignment or
6790  * atomicity of device memory accesses. The recommended practice for writing
6791  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6792  * alt_write_word() functions.
6793  *
6794  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND5.
6795  */
6796 struct ALT_IO48_HMC_MMR_SIDEBAND5_s
6797 {
6798  uint32_t mmr_dpd_mps_req : 1; /* ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ */
6799  uint32_t : 31; /* *UNDEFINED* */
6800 };
6801 
6802 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND5. */
6803 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND5_s ALT_IO48_HMC_MMR_SIDEBAND5_t;
6804 #endif /* __ASSEMBLY__ */
6805 
6806 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND5 register. */
6807 #define ALT_IO48_HMC_MMR_SIDEBAND5_RESET 0x00000000
6808 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND5 register from the beginning of the component. */
6809 #define ALT_IO48_HMC_MMR_SIDEBAND5_OFST 0xc0
6810 
6811 /*
6812  * Register : sideband6
6813  *
6814  * Register Layout
6815  *
6816  * Bits | Access | Reset | Description
6817  * :-------|:-------|:------|:--------------------------------------
6818  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK
6819  * [31:1] | ??? | 0x0 | *UNDEFINED*
6820  *
6821  */
6822 /*
6823  * Field : mr_cmd_ack
6824  *
6825  * Acknowledge to mode register command
6826  *
6827  * Field Access Macros:
6828  *
6829  */
6830 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field. */
6831 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_LSB 0
6832 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field. */
6833 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_MSB 0
6834 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field. */
6835 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_WIDTH 1
6836 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field value. */
6837 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET_MSK 0x00000001
6838 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field value. */
6839 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_CLR_MSK 0xfffffffe
6840 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field. */
6841 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_RESET 0x0
6842 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK field value from a register. */
6843 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_GET(value) (((value) & 0x00000001) >> 0)
6844 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK register field value suitable for setting the register. */
6845 #define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET(value) (((value) << 0) & 0x00000001)
6846 
6847 #ifndef __ASSEMBLY__
6848 /*
6849  * WARNING: The C register and register group struct declarations are provided for
6850  * convenience and illustrative purposes. They should, however, be used with
6851  * caution as the C language standard provides no guarantees about the alignment or
6852  * atomicity of device memory accesses. The recommended practice for writing
6853  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6854  * alt_write_word() functions.
6855  *
6856  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND6.
6857  */
6858 struct ALT_IO48_HMC_MMR_SIDEBAND6_s
6859 {
6860  uint32_t mr_cmd_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK */
6861  uint32_t : 31; /* *UNDEFINED* */
6862 };
6863 
6864 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND6. */
6865 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND6_s ALT_IO48_HMC_MMR_SIDEBAND6_t;
6866 #endif /* __ASSEMBLY__ */
6867 
6868 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND6 register. */
6869 #define ALT_IO48_HMC_MMR_SIDEBAND6_RESET 0x00000000
6870 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND6 register from the beginning of the component. */
6871 #define ALT_IO48_HMC_MMR_SIDEBAND6_OFST 0xc4
6872 
6873 /*
6874  * Register : sideband7
6875  *
6876  * Register Layout
6877  *
6878  * Bits | Access | Reset | Description
6879  * :-------|:-------|:------|:-------------------------------------------
6880  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK
6881  * [31:1] | ??? | 0x0 | *UNDEFINED*
6882  *
6883  */
6884 /*
6885  * Field : mmr_refresh_ack
6886  *
6887  * Acknowledge to indicate refresh is in progress
6888  *
6889  * Field Access Macros:
6890  *
6891  */
6892 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field. */
6893 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_LSB 0
6894 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field. */
6895 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_MSB 0
6896 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field. */
6897 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_WIDTH 1
6898 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field value. */
6899 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET_MSK 0x00000001
6900 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field value. */
6901 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_CLR_MSK 0xfffffffe
6902 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field. */
6903 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_RESET 0x0
6904 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK field value from a register. */
6905 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_GET(value) (((value) & 0x00000001) >> 0)
6906 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK register field value suitable for setting the register. */
6907 #define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET(value) (((value) << 0) & 0x00000001)
6908 
6909 #ifndef __ASSEMBLY__
6910 /*
6911  * WARNING: The C register and register group struct declarations are provided for
6912  * convenience and illustrative purposes. They should, however, be used with
6913  * caution as the C language standard provides no guarantees about the alignment or
6914  * atomicity of device memory accesses. The recommended practice for writing
6915  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6916  * alt_write_word() functions.
6917  *
6918  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND7.
6919  */
6920 struct ALT_IO48_HMC_MMR_SIDEBAND7_s
6921 {
6922  uint32_t mmr_refresh_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK */
6923  uint32_t : 31; /* *UNDEFINED* */
6924 };
6925 
6926 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND7. */
6927 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND7_s ALT_IO48_HMC_MMR_SIDEBAND7_t;
6928 #endif /* __ASSEMBLY__ */
6929 
6930 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND7 register. */
6931 #define ALT_IO48_HMC_MMR_SIDEBAND7_RESET 0x00000000
6932 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND7 register from the beginning of the component. */
6933 #define ALT_IO48_HMC_MMR_SIDEBAND7_OFST 0xc8
6934 
6935 /*
6936  * Register : sideband8
6937  *
6938  * Register Layout
6939  *
6940  * Bits | Access | Reset | Description
6941  * :-------|:-------|:------|:-----------------------------------------
6942  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK
6943  * [31:1] | ??? | 0x0 | *UNDEFINED*
6944  *
6945  */
6946 /*
6947  * Field : mmr_zqcal_ack
6948  *
6949  * Acknowledge to indicate ZQCAL is progress
6950  *
6951  * Field Access Macros:
6952  *
6953  */
6954 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field. */
6955 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_LSB 0
6956 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field. */
6957 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_MSB 0
6958 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field. */
6959 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_WIDTH 1
6960 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field value. */
6961 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET_MSK 0x00000001
6962 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field value. */
6963 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_CLR_MSK 0xfffffffe
6964 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field. */
6965 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_RESET 0x0
6966 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK field value from a register. */
6967 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_GET(value) (((value) & 0x00000001) >> 0)
6968 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK register field value suitable for setting the register. */
6969 #define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET(value) (((value) << 0) & 0x00000001)
6970 
6971 #ifndef __ASSEMBLY__
6972 /*
6973  * WARNING: The C register and register group struct declarations are provided for
6974  * convenience and illustrative purposes. They should, however, be used with
6975  * caution as the C language standard provides no guarantees about the alignment or
6976  * atomicity of device memory accesses. The recommended practice for writing
6977  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6978  * alt_write_word() functions.
6979  *
6980  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND8.
6981  */
6982 struct ALT_IO48_HMC_MMR_SIDEBAND8_s
6983 {
6984  uint32_t mmr_zqcal_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK */
6985  uint32_t : 31; /* *UNDEFINED* */
6986 };
6987 
6988 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND8. */
6989 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND8_s ALT_IO48_HMC_MMR_SIDEBAND8_t;
6990 #endif /* __ASSEMBLY__ */
6991 
6992 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND8 register. */
6993 #define ALT_IO48_HMC_MMR_SIDEBAND8_RESET 0x00000000
6994 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND8 register from the beginning of the component. */
6995 #define ALT_IO48_HMC_MMR_SIDEBAND8_OFST 0xcc
6996 
6997 /*
6998  * Register : sideband9
6999  *
7000  * Register Layout
7001  *
7002  * Bits | Access | Reset | Description
7003  * :-------|:-------|:------|:---------------------------------------------
7004  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK
7005  * [31:1] | ??? | 0x0 | *UNDEFINED*
7006  *
7007  */
7008 /*
7009  * Field : mmr_self_rfsh_ack
7010  *
7011  * Acknowledge to indicate self refresh is progress
7012  *
7013  * Field Access Macros:
7014  *
7015  */
7016 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
7017 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_LSB 0
7018 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
7019 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_MSB 0
7020 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
7021 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_WIDTH 1
7022 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field value. */
7023 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET_MSK 0x00000001
7024 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field value. */
7025 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_CLR_MSK 0xfffffffe
7026 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field. */
7027 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_RESET 0x0
7028 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK field value from a register. */
7029 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_GET(value) (((value) & 0x00000001) >> 0)
7030 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK register field value suitable for setting the register. */
7031 #define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET(value) (((value) << 0) & 0x00000001)
7032 
7033 #ifndef __ASSEMBLY__
7034 /*
7035  * WARNING: The C register and register group struct declarations are provided for
7036  * convenience and illustrative purposes. They should, however, be used with
7037  * caution as the C language standard provides no guarantees about the alignment or
7038  * atomicity of device memory accesses. The recommended practice for writing
7039  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7040  * alt_write_word() functions.
7041  *
7042  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND9.
7043  */
7044 struct ALT_IO48_HMC_MMR_SIDEBAND9_s
7045 {
7046  uint32_t mmr_self_rfsh_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK */
7047  uint32_t : 31; /* *UNDEFINED* */
7048 };
7049 
7050 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND9. */
7051 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND9_s ALT_IO48_HMC_MMR_SIDEBAND9_t;
7052 #endif /* __ASSEMBLY__ */
7053 
7054 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND9 register. */
7055 #define ALT_IO48_HMC_MMR_SIDEBAND9_RESET 0x00000000
7056 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND9 register from the beginning of the component. */
7057 #define ALT_IO48_HMC_MMR_SIDEBAND9_OFST 0xd0
7058 
7059 /*
7060  * Register : sideband10
7061  *
7062  * Register Layout
7063  *
7064  * Bits | Access | Reset | Description
7065  * :-------|:-------|:------|:--------------------------------------------
7066  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK
7067  * [31:1] | ??? | 0x0 | *UNDEFINED*
7068  *
7069  */
7070 /*
7071  * Field : mmr_dpd_mps_ack
7072  *
7073  * Acknowledge to indicate deep power down/max power saving is in progress
7074  *
7075  * Field Access Macros:
7076  *
7077  */
7078 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
7079 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_LSB 0
7080 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
7081 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_MSB 0
7082 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
7083 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_WIDTH 1
7084 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field value. */
7085 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET_MSK 0x00000001
7086 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field value. */
7087 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_CLR_MSK 0xfffffffe
7088 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field. */
7089 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_RESET 0x0
7090 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK field value from a register. */
7091 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_GET(value) (((value) & 0x00000001) >> 0)
7092 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK register field value suitable for setting the register. */
7093 #define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET(value) (((value) << 0) & 0x00000001)
7094 
7095 #ifndef __ASSEMBLY__
7096 /*
7097  * WARNING: The C register and register group struct declarations are provided for
7098  * convenience and illustrative purposes. They should, however, be used with
7099  * caution as the C language standard provides no guarantees about the alignment or
7100  * atomicity of device memory accesses. The recommended practice for writing
7101  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7102  * alt_write_word() functions.
7103  *
7104  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND10.
7105  */
7106 struct ALT_IO48_HMC_MMR_SIDEBAND10_s
7107 {
7108  uint32_t mmr_dpd_mps_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK */
7109  uint32_t : 31; /* *UNDEFINED* */
7110 };
7111 
7112 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND10. */
7113 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND10_s ALT_IO48_HMC_MMR_SIDEBAND10_t;
7114 #endif /* __ASSEMBLY__ */
7115 
7116 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND10 register. */
7117 #define ALT_IO48_HMC_MMR_SIDEBAND10_RESET 0x00000000
7118 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND10 register from the beginning of the component. */
7119 #define ALT_IO48_HMC_MMR_SIDEBAND10_OFST 0xd4
7120 
7121 /*
7122  * Register : sideband11
7123  *
7124  * Register Layout
7125  *
7126  * Bits | Access | Reset | Description
7127  * :-------|:-------|:------|:--------------------------------------------
7128  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK
7129  * [31:1] | ??? | 0x0 | *UNDEFINED*
7130  *
7131  */
7132 /*
7133  * Field : mmr_auto_pd_ack
7134  *
7135  * Acknowledge to indicate auto power down is in progress
7136  *
7137  * Field Access Macros:
7138  *
7139  */
7140 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
7141 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_LSB 0
7142 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
7143 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_MSB 0
7144 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
7145 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_WIDTH 1
7146 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field value. */
7147 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET_MSK 0x00000001
7148 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field value. */
7149 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_CLR_MSK 0xfffffffe
7150 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field. */
7151 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_RESET 0x0
7152 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK field value from a register. */
7153 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_GET(value) (((value) & 0x00000001) >> 0)
7154 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK register field value suitable for setting the register. */
7155 #define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET(value) (((value) << 0) & 0x00000001)
7156 
7157 #ifndef __ASSEMBLY__
7158 /*
7159  * WARNING: The C register and register group struct declarations are provided for
7160  * convenience and illustrative purposes. They should, however, be used with
7161  * caution as the C language standard provides no guarantees about the alignment or
7162  * atomicity of device memory accesses. The recommended practice for writing
7163  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7164  * alt_write_word() functions.
7165  *
7166  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND11.
7167  */
7168 struct ALT_IO48_HMC_MMR_SIDEBAND11_s
7169 {
7170  uint32_t mmr_auto_pd_ack : 1; /* ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK */
7171  uint32_t : 31; /* *UNDEFINED* */
7172 };
7173 
7174 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND11. */
7175 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND11_s ALT_IO48_HMC_MMR_SIDEBAND11_t;
7176 #endif /* __ASSEMBLY__ */
7177 
7178 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND11 register. */
7179 #define ALT_IO48_HMC_MMR_SIDEBAND11_RESET 0x00000000
7180 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND11 register from the beginning of the component. */
7181 #define ALT_IO48_HMC_MMR_SIDEBAND11_OFST 0xd8
7182 
7183 /*
7184  * Register : sideband12
7185  *
7186  * Register Layout
7187  *
7188  * Bits | Access | Reset | Description
7189  * :-------|:-------|:------|:----------------------------------------
7190  * [2:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE
7191  * [6:3] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK
7192  * [31:7] | ??? | 0x0 | *UNDEFINED*
7193  *
7194  */
7195 /*
7196  * Field : mr_cmd_type
7197  *
7198  * Indicates the type of Mode Register Command
7199  *
7200  * Field Access Macros:
7201  *
7202  */
7203 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field. */
7204 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_LSB 0
7205 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field. */
7206 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_MSB 2
7207 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field. */
7208 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_WIDTH 3
7209 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field value. */
7210 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET_MSK 0x00000007
7211 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field value. */
7212 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_CLR_MSK 0xfffffff8
7213 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field. */
7214 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_RESET 0x0
7215 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE field value from a register. */
7216 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_GET(value) (((value) & 0x00000007) >> 0)
7217 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE register field value suitable for setting the register. */
7218 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET(value) (((value) << 0) & 0x00000007)
7219 
7220 /*
7221  * Field : mr_cmd_rank
7222  *
7223  * Indicates which rank the mode register command is intended to.
7224  *
7225  * Field Access Macros:
7226  *
7227  */
7228 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field. */
7229 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_LSB 3
7230 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field. */
7231 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_MSB 6
7232 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field. */
7233 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_WIDTH 4
7234 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field value. */
7235 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET_MSK 0x00000078
7236 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field value. */
7237 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_CLR_MSK 0xffffff87
7238 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field. */
7239 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_RESET 0x0
7240 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK field value from a register. */
7241 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_GET(value) (((value) & 0x00000078) >> 3)
7242 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK register field value suitable for setting the register. */
7243 #define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET(value) (((value) << 3) & 0x00000078)
7244 
7245 #ifndef __ASSEMBLY__
7246 /*
7247  * WARNING: The C register and register group struct declarations are provided for
7248  * convenience and illustrative purposes. They should, however, be used with
7249  * caution as the C language standard provides no guarantees about the alignment or
7250  * atomicity of device memory accesses. The recommended practice for writing
7251  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7252  * alt_write_word() functions.
7253  *
7254  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND12.
7255  */
7256 struct ALT_IO48_HMC_MMR_SIDEBAND12_s
7257 {
7258  uint32_t mr_cmd_type : 3; /* ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE */
7259  uint32_t mr_cmd_rank : 4; /* ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK */
7260  uint32_t : 25; /* *UNDEFINED* */
7261 };
7262 
7263 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND12. */
7264 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND12_s ALT_IO48_HMC_MMR_SIDEBAND12_t;
7265 #endif /* __ASSEMBLY__ */
7266 
7267 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND12 register. */
7268 #define ALT_IO48_HMC_MMR_SIDEBAND12_RESET 0x00000000
7269 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND12 register from the beginning of the component. */
7270 #define ALT_IO48_HMC_MMR_SIDEBAND12_OFST 0xdc
7271 
7272 /*
7273  * Register : sideband13
7274  *
7275  * Register Layout
7276  *
7277  * Bits | Access | Reset | Description
7278  * :-------|:-------|:------|:------------------------------------------
7279  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE
7280  *
7281  */
7282 /*
7283  * Field : mr_cmd_opcode
7284  *
7285  * [31:27] reserved. Register Command Opcode Information to be used for Register
7286  * Command LPDDR3 [26:20] Reserved [19:10] falling edge CA. [9:0] rising edge CA
7287  * DDR4 [26:24] C2:C0 [23] ACT [22:21] BG1:BG0 [20] Reserved [19:18] BA1:BA0 [17]
7288  * A17 [16] RAS [15] CAS [14] WE [13:0] A13:A0 DDR3 [26:21] Reserved [20:18]
7289  * BA2:BA0 [17] A17 [16] RAS [15] CAS [14] WE [13] Reserved [12:0] A12:A0 RLDRAM3
7290  * [26] Reserved [25:22] BA3:BA0 [21] REF [20] WE [19:0] A19:A0
7291  *
7292  * Field Access Macros:
7293  *
7294  */
7295 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field. */
7296 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_LSB 0
7297 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field. */
7298 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_MSB 31
7299 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field. */
7300 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_WIDTH 32
7301 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value. */
7302 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET_MSK 0xffffffff
7303 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value. */
7304 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK 0x00000000
7305 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field. */
7306 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_RESET 0x0
7307 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE field value from a register. */
7308 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_GET(value) (((value) & 0xffffffff) >> 0)
7309 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value suitable for setting the register. */
7310 #define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET(value) (((value) << 0) & 0xffffffff)
7311 
7312 #ifndef __ASSEMBLY__
7313 /*
7314  * WARNING: The C register and register group struct declarations are provided for
7315  * convenience and illustrative purposes. They should, however, be used with
7316  * caution as the C language standard provides no guarantees about the alignment or
7317  * atomicity of device memory accesses. The recommended practice for writing
7318  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7319  * alt_write_word() functions.
7320  *
7321  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND13.
7322  */
7323 struct ALT_IO48_HMC_MMR_SIDEBAND13_s
7324 {
7325  uint32_t mr_cmd_opcode : 32; /* ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE */
7326 };
7327 
7328 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND13. */
7329 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND13_s ALT_IO48_HMC_MMR_SIDEBAND13_t;
7330 #endif /* __ASSEMBLY__ */
7331 
7332 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND13 register. */
7333 #define ALT_IO48_HMC_MMR_SIDEBAND13_RESET 0x00000000
7334 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND13 register from the beginning of the component. */
7335 #define ALT_IO48_HMC_MMR_SIDEBAND13_OFST 0xe0
7336 
7337 /*
7338  * Register : sideband14
7339  *
7340  * Register Layout
7341  *
7342  * Bits | Access | Reset | Description
7343  * :--------|:-------|:------|:---------------------------------------------
7344  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK
7345  * [31:16] | ??? | 0x0 | *UNDEFINED*
7346  *
7347  */
7348 /*
7349  * Field : mmr_refresh_bank
7350  *
7351  * user refresh bank information, binary representation of bank address. Enables
7352  * refresh to that bank address when requested
7353  *
7354  * Field Access Macros:
7355  *
7356  */
7357 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field. */
7358 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_LSB 0
7359 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field. */
7360 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_MSB 15
7361 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field. */
7362 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_WIDTH 16
7363 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field value. */
7364 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET_MSK 0x0000ffff
7365 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field value. */
7366 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_CLR_MSK 0xffff0000
7367 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field. */
7368 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_RESET 0x0
7369 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK field value from a register. */
7370 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_GET(value) (((value) & 0x0000ffff) >> 0)
7371 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK register field value suitable for setting the register. */
7372 #define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET(value) (((value) << 0) & 0x0000ffff)
7373 
7374 #ifndef __ASSEMBLY__
7375 /*
7376  * WARNING: The C register and register group struct declarations are provided for
7377  * convenience and illustrative purposes. They should, however, be used with
7378  * caution as the C language standard provides no guarantees about the alignment or
7379  * atomicity of device memory accesses. The recommended practice for writing
7380  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7381  * alt_write_word() functions.
7382  *
7383  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND14.
7384  */
7385 struct ALT_IO48_HMC_MMR_SIDEBAND14_s
7386 {
7387  uint32_t mmr_refresh_bank : 16; /* ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK */
7388  uint32_t : 16; /* *UNDEFINED* */
7389 };
7390 
7391 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND14. */
7392 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND14_s ALT_IO48_HMC_MMR_SIDEBAND14_t;
7393 #endif /* __ASSEMBLY__ */
7394 
7395 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND14 register. */
7396 #define ALT_IO48_HMC_MMR_SIDEBAND14_RESET 0x00000000
7397 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND14 register from the beginning of the component. */
7398 #define ALT_IO48_HMC_MMR_SIDEBAND14_OFST 0xe4
7399 
7400 /*
7401  * Register : sideband15
7402  *
7403  * Register Layout
7404  *
7405  * Bits | Access | Reset | Description
7406  * :-------|:-------|:------|:-------------------------------------------
7407  * [3:0] | RW | 0x0 | ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK
7408  * [31:4] | ??? | 0x0 | *UNDEFINED*
7409  *
7410  */
7411 /*
7412  * Field : mmr_stall_rank
7413  *
7414  * Setting to 1 to stall the corresponding rank
7415  *
7416  * Field Access Macros:
7417  *
7418  */
7419 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field. */
7420 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_LSB 0
7421 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field. */
7422 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_MSB 3
7423 /* The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field. */
7424 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_WIDTH 4
7425 /* The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field value. */
7426 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET_MSK 0x0000000f
7427 /* The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field value. */
7428 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_CLR_MSK 0xfffffff0
7429 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field. */
7430 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_RESET 0x0
7431 /* Extracts the ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK field value from a register. */
7432 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_GET(value) (((value) & 0x0000000f) >> 0)
7433 /* Produces a ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK register field value suitable for setting the register. */
7434 #define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET(value) (((value) << 0) & 0x0000000f)
7435 
7436 #ifndef __ASSEMBLY__
7437 /*
7438  * WARNING: The C register and register group struct declarations are provided for
7439  * convenience and illustrative purposes. They should, however, be used with
7440  * caution as the C language standard provides no guarantees about the alignment or
7441  * atomicity of device memory accesses. The recommended practice for writing
7442  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7443  * alt_write_word() functions.
7444  *
7445  * The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND15.
7446  */
7447 struct ALT_IO48_HMC_MMR_SIDEBAND15_s
7448 {
7449  uint32_t mmr_stall_rank : 4; /* ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK */
7450  uint32_t : 28; /* *UNDEFINED* */
7451 };
7452 
7453 /* The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND15. */
7454 typedef volatile struct ALT_IO48_HMC_MMR_SIDEBAND15_s ALT_IO48_HMC_MMR_SIDEBAND15_t;
7455 #endif /* __ASSEMBLY__ */
7456 
7457 /* The reset value of the ALT_IO48_HMC_MMR_SIDEBAND15 register. */
7458 #define ALT_IO48_HMC_MMR_SIDEBAND15_RESET 0x00000000
7459 /* The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND15 register from the beginning of the component. */
7460 #define ALT_IO48_HMC_MMR_SIDEBAND15_OFST 0xe8
7461 
7462 /*
7463  * Register : dramsts
7464  *
7465  * Register Layout
7466  *
7467  * Bits | Access | Reset | Description
7468  * :-------|:-------|:------|:-----------------------------------------
7469  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS
7470  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL
7471  * [31:2] | ??? | 0x0 | *UNDEFINED*
7472  *
7473  */
7474 /*
7475  * Field : phy_cal_success
7476  *
7477  * This bit will be set to 1 if the PHY was able to successfully calibrate.
7478  *
7479  * Field Access Macros:
7480  *
7481  */
7482 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field. */
7483 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_LSB 0
7484 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field. */
7485 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_MSB 0
7486 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field. */
7487 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_WIDTH 1
7488 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field value. */
7489 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET_MSK 0x00000001
7490 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field value. */
7491 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_CLR_MSK 0xfffffffe
7492 /* The reset value of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field. */
7493 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_RESET 0x0
7494 /* Extracts the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS field value from a register. */
7495 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_GET(value) (((value) & 0x00000001) >> 0)
7496 /* Produces a ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS register field value suitable for setting the register. */
7497 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET(value) (((value) << 0) & 0x00000001)
7498 
7499 /*
7500  * Field : phy_cal_fail
7501  *
7502  * This bit will be set to 1 if the PHY was unable to calibrate.
7503  *
7504  * Field Access Macros:
7505  *
7506  */
7507 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field. */
7508 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_LSB 1
7509 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field. */
7510 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_MSB 1
7511 /* The width in bits of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field. */
7512 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_WIDTH 1
7513 /* The mask used to set the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field value. */
7514 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET_MSK 0x00000002
7515 /* The mask used to clear the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field value. */
7516 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_CLR_MSK 0xfffffffd
7517 /* The reset value of the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field. */
7518 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_RESET 0x0
7519 /* Extracts the ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL field value from a register. */
7520 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_GET(value) (((value) & 0x00000002) >> 1)
7521 /* Produces a ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL register field value suitable for setting the register. */
7522 #define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET(value) (((value) << 1) & 0x00000002)
7523 
7524 #ifndef __ASSEMBLY__
7525 /*
7526  * WARNING: The C register and register group struct declarations are provided for
7527  * convenience and illustrative purposes. They should, however, be used with
7528  * caution as the C language standard provides no guarantees about the alignment or
7529  * atomicity of device memory accesses. The recommended practice for writing
7530  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7531  * alt_write_word() functions.
7532  *
7533  * The struct declaration for register ALT_IO48_HMC_MMR_DRAMSTS.
7534  */
7535 struct ALT_IO48_HMC_MMR_DRAMSTS_s
7536 {
7537  uint32_t phy_cal_success : 1; /* ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS */
7538  uint32_t phy_cal_fail : 1; /* ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL */
7539  uint32_t : 30; /* *UNDEFINED* */
7540 };
7541 
7542 /* The typedef declaration for register ALT_IO48_HMC_MMR_DRAMSTS. */
7543 typedef volatile struct ALT_IO48_HMC_MMR_DRAMSTS_s ALT_IO48_HMC_MMR_DRAMSTS_t;
7544 #endif /* __ASSEMBLY__ */
7545 
7546 /* The reset value of the ALT_IO48_HMC_MMR_DRAMSTS register. */
7547 #define ALT_IO48_HMC_MMR_DRAMSTS_RESET 0x00000000
7548 /* The byte offset of the ALT_IO48_HMC_MMR_DRAMSTS register from the beginning of the component. */
7549 #define ALT_IO48_HMC_MMR_DRAMSTS_OFST 0xec
7550 
7551 /*
7552  * Register : dbgdone
7553  *
7554  * Register Layout
7555  *
7556  * Bits | Access | Reset | Description
7557  * :-------|:-------|:------|:----------------------------------
7558  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE
7559  * [31:1] | ??? | 0x0 | *UNDEFINED*
7560  *
7561  */
7562 /*
7563  * Field : dbg_done
7564  *
7565  * Indicates the debug test is completed
7566  *
7567  * Field Access Macros:
7568  *
7569  */
7570 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field. */
7571 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_LSB 0
7572 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field. */
7573 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_MSB 0
7574 /* The width in bits of the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field. */
7575 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_WIDTH 1
7576 /* The mask used to set the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field value. */
7577 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET_MSK 0x00000001
7578 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field value. */
7579 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_CLR_MSK 0xfffffffe
7580 /* The reset value of the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field. */
7581 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_RESET 0x0
7582 /* Extracts the ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE field value from a register. */
7583 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_GET(value) (((value) & 0x00000001) >> 0)
7584 /* Produces a ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE register field value suitable for setting the register. */
7585 #define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET(value) (((value) << 0) & 0x00000001)
7586 
7587 #ifndef __ASSEMBLY__
7588 /*
7589  * WARNING: The C register and register group struct declarations are provided for
7590  * convenience and illustrative purposes. They should, however, be used with
7591  * caution as the C language standard provides no guarantees about the alignment or
7592  * atomicity of device memory accesses. The recommended practice for writing
7593  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7594  * alt_write_word() functions.
7595  *
7596  * The struct declaration for register ALT_IO48_HMC_MMR_DBGDONE.
7597  */
7598 struct ALT_IO48_HMC_MMR_DBGDONE_s
7599 {
7600  uint32_t dbg_done : 1; /* ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE */
7601  uint32_t : 31; /* *UNDEFINED* */
7602 };
7603 
7604 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGDONE. */
7605 typedef volatile struct ALT_IO48_HMC_MMR_DBGDONE_s ALT_IO48_HMC_MMR_DBGDONE_t;
7606 #endif /* __ASSEMBLY__ */
7607 
7608 /* The reset value of the ALT_IO48_HMC_MMR_DBGDONE register. */
7609 #define ALT_IO48_HMC_MMR_DBGDONE_RESET 0x00000000
7610 /* The byte offset of the ALT_IO48_HMC_MMR_DBGDONE register from the beginning of the component. */
7611 #define ALT_IO48_HMC_MMR_DBGDONE_OFST 0xf0
7612 
7613 /*
7614  * Register : dbgsignals
7615  *
7616  * Register Layout
7617  *
7618  * Bits | Access | Reset | Description
7619  * :-------|:-------|:------|:--------------------------------------------
7620  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT
7621  *
7622  */
7623 /*
7624  * Field : dbg_signals_out
7625  *
7626  * Debug signals output
7627  *
7628  * Field Access Macros:
7629  *
7630  */
7631 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
7632 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_LSB 0
7633 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
7634 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_MSB 31
7635 /* The width in bits of the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
7636 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_WIDTH 32
7637 /* The mask used to set the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field value. */
7638 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET_MSK 0xffffffff
7639 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field value. */
7640 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_CLR_MSK 0x00000000
7641 /* The reset value of the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field. */
7642 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_RESET 0x0
7643 /* Extracts the ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT field value from a register. */
7644 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_GET(value) (((value) & 0xffffffff) >> 0)
7645 /* Produces a ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT register field value suitable for setting the register. */
7646 #define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET(value) (((value) << 0) & 0xffffffff)
7647 
7648 #ifndef __ASSEMBLY__
7649 /*
7650  * WARNING: The C register and register group struct declarations are provided for
7651  * convenience and illustrative purposes. They should, however, be used with
7652  * caution as the C language standard provides no guarantees about the alignment or
7653  * atomicity of device memory accesses. The recommended practice for writing
7654  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7655  * alt_write_word() functions.
7656  *
7657  * The struct declaration for register ALT_IO48_HMC_MMR_DBGSIGNALS.
7658  */
7659 struct ALT_IO48_HMC_MMR_DBGSIGNALS_s
7660 {
7661  uint32_t dbg_signals_out : 32; /* ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT */
7662 };
7663 
7664 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGSIGNALS. */
7665 typedef volatile struct ALT_IO48_HMC_MMR_DBGSIGNALS_s ALT_IO48_HMC_MMR_DBGSIGNALS_t;
7666 #endif /* __ASSEMBLY__ */
7667 
7668 /* The reset value of the ALT_IO48_HMC_MMR_DBGSIGNALS register. */
7669 #define ALT_IO48_HMC_MMR_DBGSIGNALS_RESET 0x00000000
7670 /* The byte offset of the ALT_IO48_HMC_MMR_DBGSIGNALS register from the beginning of the component. */
7671 #define ALT_IO48_HMC_MMR_DBGSIGNALS_OFST 0xf4
7672 
7673 /*
7674  * Register : dbgreset
7675  *
7676  * Register Layout
7677  *
7678  * Bits | Access | Reset | Description
7679  * :-------|:-------|:------|:--------------------------------------
7680  * [0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST
7681  * [1] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST
7682  * [31:2] | ??? | 0x0 | *UNDEFINED*
7683  *
7684  */
7685 /*
7686  * Field : counter_zero_reset
7687  *
7688  * Used for performance monitoring. Writing to this register resets the first
7689  * counter. Note that this bit auto-clears after one clock cycle.
7690  *
7691  * Field Access Macros:
7692  *
7693  */
7694 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field. */
7695 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_LSB 0
7696 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field. */
7697 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_MSB 0
7698 /* The width in bits of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field. */
7699 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_WIDTH 1
7700 /* The mask used to set the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value. */
7701 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET_MSK 0x00000001
7702 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value. */
7703 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_CLR_MSK 0xfffffffe
7704 /* The reset value of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field. */
7705 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_RESET 0x0
7706 /* Extracts the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST field value from a register. */
7707 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_GET(value) (((value) & 0x00000001) >> 0)
7708 /* Produces a ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value suitable for setting the register. */
7709 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET(value) (((value) << 0) & 0x00000001)
7710 
7711 /*
7712  * Field : counter_one_reset
7713  *
7714  * Used for performance monitoring. Writing to this register resets the second
7715  * counter. Note that this bit auto-clears after one clock cycle.
7716  *
7717  * Field Access Macros:
7718  *
7719  */
7720 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field. */
7721 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_LSB 1
7722 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field. */
7723 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_MSB 1
7724 /* The width in bits of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field. */
7725 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_WIDTH 1
7726 /* The mask used to set the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value. */
7727 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET_MSK 0x00000002
7728 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value. */
7729 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_CLR_MSK 0xfffffffd
7730 /* The reset value of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field. */
7731 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_RESET 0x0
7732 /* Extracts the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST field value from a register. */
7733 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_GET(value) (((value) & 0x00000002) >> 1)
7734 /* Produces a ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value suitable for setting the register. */
7735 #define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET(value) (((value) << 1) & 0x00000002)
7736 
7737 #ifndef __ASSEMBLY__
7738 /*
7739  * WARNING: The C register and register group struct declarations are provided for
7740  * convenience and illustrative purposes. They should, however, be used with
7741  * caution as the C language standard provides no guarantees about the alignment or
7742  * atomicity of device memory accesses. The recommended practice for writing
7743  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7744  * alt_write_word() functions.
7745  *
7746  * The struct declaration for register ALT_IO48_HMC_MMR_DBGRST.
7747  */
7748 struct ALT_IO48_HMC_MMR_DBGRST_s
7749 {
7750  uint32_t counter_zero_reset : 1; /* ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST */
7751  uint32_t counter_one_reset : 1; /* ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST */
7752  uint32_t : 30; /* *UNDEFINED* */
7753 };
7754 
7755 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGRST. */
7756 typedef volatile struct ALT_IO48_HMC_MMR_DBGRST_s ALT_IO48_HMC_MMR_DBGRST_t;
7757 #endif /* __ASSEMBLY__ */
7758 
7759 /* The reset value of the ALT_IO48_HMC_MMR_DBGRST register. */
7760 #define ALT_IO48_HMC_MMR_DBGRST_RESET 0x00000000
7761 /* The byte offset of the ALT_IO48_HMC_MMR_DBGRST register from the beginning of the component. */
7762 #define ALT_IO48_HMC_MMR_DBGRST_OFST 0xf8
7763 
7764 /*
7765  * Register : dbgmatch
7766  *
7767  * Register Layout
7768  *
7769  * Bits | Access | Reset | Description
7770  * :--------|:-------|:------|:------------------------------------
7771  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO
7772  * [31:16] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE
7773  *
7774  */
7775 /*
7776  * Field : counter_zero
7777  *
7778  * counter value
7779  *
7780  * Field Access Macros:
7781  *
7782  */
7783 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field. */
7784 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_LSB 0
7785 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field. */
7786 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_MSB 15
7787 /* The width in bits of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field. */
7788 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_WIDTH 16
7789 /* The mask used to set the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value. */
7790 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET_MSK 0x0000ffff
7791 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value. */
7792 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_CLR_MSK 0xffff0000
7793 /* The reset value of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field. */
7794 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_RESET 0x0
7795 /* Extracts the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO field value from a register. */
7796 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_GET(value) (((value) & 0x0000ffff) >> 0)
7797 /* Produces a ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value suitable for setting the register. */
7798 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET(value) (((value) << 0) & 0x0000ffff)
7799 
7800 /*
7801  * Field : counter_one
7802  *
7803  * counter value
7804  *
7805  * Field Access Macros:
7806  *
7807  */
7808 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field. */
7809 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_LSB 16
7810 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field. */
7811 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_MSB 31
7812 /* The width in bits of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field. */
7813 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_WIDTH 16
7814 /* The mask used to set the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value. */
7815 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET_MSK 0xffff0000
7816 /* The mask used to clear the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value. */
7817 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_CLR_MSK 0x0000ffff
7818 /* The reset value of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field. */
7819 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_RESET 0x0
7820 /* Extracts the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE field value from a register. */
7821 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_GET(value) (((value) & 0xffff0000) >> 16)
7822 /* Produces a ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value suitable for setting the register. */
7823 #define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET(value) (((value) << 16) & 0xffff0000)
7824 
7825 #ifndef __ASSEMBLY__
7826 /*
7827  * WARNING: The C register and register group struct declarations are provided for
7828  * convenience and illustrative purposes. They should, however, be used with
7829  * caution as the C language standard provides no guarantees about the alignment or
7830  * atomicity of device memory accesses. The recommended practice for writing
7831  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7832  * alt_write_word() functions.
7833  *
7834  * The struct declaration for register ALT_IO48_HMC_MMR_DBGMATCH.
7835  */
7836 struct ALT_IO48_HMC_MMR_DBGMATCH_s
7837 {
7838  uint32_t counter_zero : 16; /* ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO */
7839  uint32_t counter_one : 16; /* ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE */
7840 };
7841 
7842 /* The typedef declaration for register ALT_IO48_HMC_MMR_DBGMATCH. */
7843 typedef volatile struct ALT_IO48_HMC_MMR_DBGMATCH_s ALT_IO48_HMC_MMR_DBGMATCH_t;
7844 #endif /* __ASSEMBLY__ */
7845 
7846 /* The reset value of the ALT_IO48_HMC_MMR_DBGMATCH register. */
7847 #define ALT_IO48_HMC_MMR_DBGMATCH_RESET 0x00000000
7848 /* The byte offset of the ALT_IO48_HMC_MMR_DBGMATCH register from the beginning of the component. */
7849 #define ALT_IO48_HMC_MMR_DBGMATCH_OFST 0xfc
7850 
7851 /*
7852  * Register : counter0mask
7853  *
7854  * Register Layout
7855  *
7856  * Bits | Access | Reset | Description
7857  * :-------|:-------|:------|:----------------------------------------
7858  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK
7859  *
7860  */
7861 /*
7862  * Field : counter_zero_mask
7863  *
7864  * Performance monitoring register. This register is used to mask off the internal
7865  * signals selected by the debug select byte to either examine a bit (and expect it
7866  * to be a one or a zero) or to ignore the bit.
7867  *
7868  * Field Access Macros:
7869  *
7870  */
7871 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field. */
7872 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_LSB 0
7873 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field. */
7874 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_MSB 31
7875 /* The width in bits of the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field. */
7876 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_WIDTH 32
7877 /* The mask used to set the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field value. */
7878 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET_MSK 0xffffffff
7879 /* The mask used to clear the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field value. */
7880 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_CLR_MSK 0x00000000
7881 /* The reset value of the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field. */
7882 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_RESET 0x0
7883 /* Extracts the ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK field value from a register. */
7884 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7885 /* Produces a ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK register field value suitable for setting the register. */
7886 #define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET(value) (((value) << 0) & 0xffffffff)
7887 
7888 #ifndef __ASSEMBLY__
7889 /*
7890  * WARNING: The C register and register group struct declarations are provided for
7891  * convenience and illustrative purposes. They should, however, be used with
7892  * caution as the C language standard provides no guarantees about the alignment or
7893  * atomicity of device memory accesses. The recommended practice for writing
7894  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7895  * alt_write_word() functions.
7896  *
7897  * The struct declaration for register ALT_IO48_HMC_MMR_CNTR0MSK.
7898  */
7899 struct ALT_IO48_HMC_MMR_CNTR0MSK_s
7900 {
7901  uint32_t counter_zero_mask : 32; /* ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK */
7902 };
7903 
7904 /* The typedef declaration for register ALT_IO48_HMC_MMR_CNTR0MSK. */
7905 typedef volatile struct ALT_IO48_HMC_MMR_CNTR0MSK_s ALT_IO48_HMC_MMR_CNTR0MSK_t;
7906 #endif /* __ASSEMBLY__ */
7907 
7908 /* The reset value of the ALT_IO48_HMC_MMR_CNTR0MSK register. */
7909 #define ALT_IO48_HMC_MMR_CNTR0MSK_RESET 0x00000000
7910 /* The byte offset of the ALT_IO48_HMC_MMR_CNTR0MSK register from the beginning of the component. */
7911 #define ALT_IO48_HMC_MMR_CNTR0MSK_OFST 0x100
7912 
7913 /*
7914  * Register : counter1mask
7915  *
7916  * Register Layout
7917  *
7918  * Bits | Access | Reset | Description
7919  * :-------|:-------|:------|:---------------------------------------
7920  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK
7921  *
7922  */
7923 /*
7924  * Field : counter_one_mask
7925  *
7926  * Performance monitoring register. This register is used to mask off the internal
7927  * signals selected by the debug select byte to either examine a bit (and expect it
7928  * to be a one or a zero) or to ignore the bit.
7929  *
7930  * Field Access Macros:
7931  *
7932  */
7933 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field. */
7934 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_LSB 0
7935 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field. */
7936 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_MSB 31
7937 /* The width in bits of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field. */
7938 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_WIDTH 32
7939 /* The mask used to set the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value. */
7940 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET_MSK 0xffffffff
7941 /* The mask used to clear the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value. */
7942 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_CLR_MSK 0x00000000
7943 /* The reset value of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field. */
7944 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_RESET 0x0
7945 /* Extracts the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK field value from a register. */
7946 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7947 /* Produces a ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value suitable for setting the register. */
7948 #define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET(value) (((value) << 0) & 0xffffffff)
7949 
7950 #ifndef __ASSEMBLY__
7951 /*
7952  * WARNING: The C register and register group struct declarations are provided for
7953  * convenience and illustrative purposes. They should, however, be used with
7954  * caution as the C language standard provides no guarantees about the alignment or
7955  * atomicity of device memory accesses. The recommended practice for writing
7956  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7957  * alt_write_word() functions.
7958  *
7959  * The struct declaration for register ALT_IO48_HMC_MMR_CNTR1MSK.
7960  */
7961 struct ALT_IO48_HMC_MMR_CNTR1MSK_s
7962 {
7963  uint32_t counter_one_mask : 32; /* ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK */
7964 };
7965 
7966 /* The typedef declaration for register ALT_IO48_HMC_MMR_CNTR1MSK. */
7967 typedef volatile struct ALT_IO48_HMC_MMR_CNTR1MSK_s ALT_IO48_HMC_MMR_CNTR1MSK_t;
7968 #endif /* __ASSEMBLY__ */
7969 
7970 /* The reset value of the ALT_IO48_HMC_MMR_CNTR1MSK register. */
7971 #define ALT_IO48_HMC_MMR_CNTR1MSK_RESET 0x00000000
7972 /* The byte offset of the ALT_IO48_HMC_MMR_CNTR1MSK register from the beginning of the component. */
7973 #define ALT_IO48_HMC_MMR_CNTR1MSK_OFST 0x104
7974 
7975 /*
7976  * Register : counter0match
7977  *
7978  * Register Layout
7979  *
7980  * Bits | Access | Reset | Description
7981  * :-------|:-------|:------|:--------------------------------------------
7982  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH
7983  *
7984  */
7985 /*
7986  * Field : counter_zero_match
7987  *
7988  * Counts events which happens during the sample window which counter_zero_mask was
7989  * satisfied.
7990  *
7991  * Field Access Macros:
7992  *
7993  */
7994 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field. */
7995 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_LSB 0
7996 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field. */
7997 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_MSB 31
7998 /* The width in bits of the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field. */
7999 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_WIDTH 32
8000 /* The mask used to set the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field value. */
8001 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET_MSK 0xffffffff
8002 /* The mask used to clear the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field value. */
8003 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_CLR_MSK 0x00000000
8004 /* The reset value of the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field. */
8005 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_RESET 0x0
8006 /* Extracts the ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH field value from a register. */
8007 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8008 /* Produces a ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH register field value suitable for setting the register. */
8009 #define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8010 
8011 #ifndef __ASSEMBLY__
8012 /*
8013  * WARNING: The C register and register group struct declarations are provided for
8014  * convenience and illustrative purposes. They should, however, be used with
8015  * caution as the C language standard provides no guarantees about the alignment or
8016  * atomicity of device memory accesses. The recommended practice for writing
8017  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8018  * alt_write_word() functions.
8019  *
8020  * The struct declaration for register ALT_IO48_HMC_MMR_CNTR0MATCH.
8021  */
8022 struct ALT_IO48_HMC_MMR_CNTR0MATCH_s
8023 {
8024  uint32_t counter_zero_match : 32; /* ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH */
8025 };
8026 
8027 /* The typedef declaration for register ALT_IO48_HMC_MMR_CNTR0MATCH. */
8028 typedef volatile struct ALT_IO48_HMC_MMR_CNTR0MATCH_s ALT_IO48_HMC_MMR_CNTR0MATCH_t;
8029 #endif /* __ASSEMBLY__ */
8030 
8031 /* The reset value of the ALT_IO48_HMC_MMR_CNTR0MATCH register. */
8032 #define ALT_IO48_HMC_MMR_CNTR0MATCH_RESET 0x00000000
8033 /* The byte offset of the ALT_IO48_HMC_MMR_CNTR0MATCH register from the beginning of the component. */
8034 #define ALT_IO48_HMC_MMR_CNTR0MATCH_OFST 0x108
8035 
8036 /*
8037  * Register : counter1match
8038  *
8039  * Register Layout
8040  *
8041  * Bits | Access | Reset | Description
8042  * :-------|:-------|:------|:-------------------------------------------
8043  * [31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH
8044  *
8045  */
8046 /*
8047  * Field : counter_one_match
8048  *
8049  * Counts events which happens during the sample window which counter_one_mask was
8050  * satisfied.
8051  *
8052  * Field Access Macros:
8053  *
8054  */
8055 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field. */
8056 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_LSB 0
8057 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field. */
8058 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_MSB 31
8059 /* The width in bits of the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field. */
8060 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_WIDTH 32
8061 /* The mask used to set the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field value. */
8062 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET_MSK 0xffffffff
8063 /* The mask used to clear the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field value. */
8064 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_CLR_MSK 0x00000000
8065 /* The reset value of the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field. */
8066 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_RESET 0x0
8067 /* Extracts the ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH field value from a register. */
8068 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8069 /* Produces a ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH register field value suitable for setting the register. */
8070 #define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8071 
8072 #ifndef __ASSEMBLY__
8073 /*
8074  * WARNING: The C register and register group struct declarations are provided for
8075  * convenience and illustrative purposes. They should, however, be used with
8076  * caution as the C language standard provides no guarantees about the alignment or
8077  * atomicity of device memory accesses. The recommended practice for writing
8078  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8079  * alt_write_word() functions.
8080  *
8081  * The struct declaration for register ALT_IO48_HMC_MMR_CNTR1MATCH.
8082  */
8083 struct ALT_IO48_HMC_MMR_CNTR1MATCH_s
8084 {
8085  uint32_t counter_one_match : 32; /* ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH */
8086 };
8087 
8088 /* The typedef declaration for register ALT_IO48_HMC_MMR_CNTR1MATCH. */
8089 typedef volatile struct ALT_IO48_HMC_MMR_CNTR1MATCH_s ALT_IO48_HMC_MMR_CNTR1MATCH_t;
8090 #endif /* __ASSEMBLY__ */
8091 
8092 /* The reset value of the ALT_IO48_HMC_MMR_CNTR1MATCH register. */
8093 #define ALT_IO48_HMC_MMR_CNTR1MATCH_RESET 0x00000000
8094 /* The byte offset of the ALT_IO48_HMC_MMR_CNTR1MATCH register from the beginning of the component. */
8095 #define ALT_IO48_HMC_MMR_CNTR1MATCH_OFST 0x10c
8096 
8097 /*
8098  * Register : niosreserve0
8099  *
8100  * Register Layout
8101  *
8102  * Bits | Access | Reset | Description
8103  * :--------|:-------|:------|:--------------------------------------------
8104  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0
8105  * [31:16] | ??? | 0x0 | *UNDEFINED*
8106  *
8107  */
8108 /*
8109  * Field : nios_reserve0
8110  *
8111  * Reserved register0 for Nios
8112  *
8113  * Field Access Macros:
8114  *
8115  */
8116 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field. */
8117 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_LSB 0
8118 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field. */
8119 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_MSB 15
8120 /* The width in bits of the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field. */
8121 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_WIDTH 16
8122 /* The mask used to set the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field value. */
8123 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET_MSK 0x0000ffff
8124 /* The mask used to clear the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field value. */
8125 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_CLR_MSK 0xffff0000
8126 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field. */
8127 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_RESET 0x0
8128 /* Extracts the ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 field value from a register. */
8129 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
8130 /* Produces a ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 register field value suitable for setting the register. */
8131 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
8132 
8133 #ifndef __ASSEMBLY__
8134 /*
8135  * WARNING: The C register and register group struct declarations are provided for
8136  * convenience and illustrative purposes. They should, however, be used with
8137  * caution as the C language standard provides no guarantees about the alignment or
8138  * atomicity of device memory accesses. The recommended practice for writing
8139  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8140  * alt_write_word() functions.
8141  *
8142  * The struct declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE0.
8143  */
8144 struct ALT_IO48_HMC_MMR_NIOSRESERVE0_s
8145 {
8146  uint32_t nios_reserve0 : 16; /* ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0 */
8147  uint32_t : 16; /* *UNDEFINED* */
8148 };
8149 
8150 /* The typedef declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE0. */
8151 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE0_s ALT_IO48_HMC_MMR_NIOSRESERVE0_t;
8152 #endif /* __ASSEMBLY__ */
8153 
8154 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE0 register. */
8155 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_RESET 0x00000000
8156 /* The byte offset of the ALT_IO48_HMC_MMR_NIOSRESERVE0 register from the beginning of the component. */
8157 #define ALT_IO48_HMC_MMR_NIOSRESERVE0_OFST 0x110
8158 
8159 /*
8160  * Register : niosreserve1
8161  *
8162  * Register Layout
8163  *
8164  * Bits | Access | Reset | Description
8165  * :--------|:-------|:------|:--------------------------------------------
8166  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1
8167  * [31:16] | ??? | 0x0 | *UNDEFINED*
8168  *
8169  */
8170 /*
8171  * Field : nios_reserve1
8172  *
8173  * Reserved register1 for Nios
8174  *
8175  * Field Access Macros:
8176  *
8177  */
8178 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field. */
8179 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_LSB 0
8180 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field. */
8181 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_MSB 15
8182 /* The width in bits of the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field. */
8183 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_WIDTH 16
8184 /* The mask used to set the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field value. */
8185 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET_MSK 0x0000ffff
8186 /* The mask used to clear the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field value. */
8187 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_CLR_MSK 0xffff0000
8188 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field. */
8189 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_RESET 0x0
8190 /* Extracts the ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 field value from a register. */
8191 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
8192 /* Produces a ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 register field value suitable for setting the register. */
8193 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
8194 
8195 #ifndef __ASSEMBLY__
8196 /*
8197  * WARNING: The C register and register group struct declarations are provided for
8198  * convenience and illustrative purposes. They should, however, be used with
8199  * caution as the C language standard provides no guarantees about the alignment or
8200  * atomicity of device memory accesses. The recommended practice for writing
8201  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8202  * alt_write_word() functions.
8203  *
8204  * The struct declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE1.
8205  */
8206 struct ALT_IO48_HMC_MMR_NIOSRESERVE1_s
8207 {
8208  uint32_t nios_reserve1 : 16; /* ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1 */
8209  uint32_t : 16; /* *UNDEFINED* */
8210 };
8211 
8212 /* The typedef declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE1. */
8213 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE1_s ALT_IO48_HMC_MMR_NIOSRESERVE1_t;
8214 #endif /* __ASSEMBLY__ */
8215 
8216 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE1 register. */
8217 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_RESET 0x00000000
8218 /* The byte offset of the ALT_IO48_HMC_MMR_NIOSRESERVE1 register from the beginning of the component. */
8219 #define ALT_IO48_HMC_MMR_NIOSRESERVE1_OFST 0x114
8220 
8221 /*
8222  * Register : niosreserve2
8223  *
8224  * Register Layout
8225  *
8226  * Bits | Access | Reset | Description
8227  * :--------|:-------|:------|:--------------------------------------------
8228  * [15:0] | RW | 0x0 | ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2
8229  * [31:16] | ??? | 0x0 | *UNDEFINED*
8230  *
8231  */
8232 /*
8233  * Field : nios_reserve2
8234  *
8235  * Reserved register2 for Nios
8236  *
8237  * Field Access Macros:
8238  *
8239  */
8240 /* The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field. */
8241 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_LSB 0
8242 /* The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field. */
8243 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_MSB 15
8244 /* The width in bits of the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field. */
8245 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_WIDTH 16
8246 /* The mask used to set the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field value. */
8247 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET_MSK 0x0000ffff
8248 /* The mask used to clear the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field value. */
8249 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_CLR_MSK 0xffff0000
8250 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field. */
8251 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_RESET 0x0
8252 /* Extracts the ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 field value from a register. */
8253 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
8254 /* Produces a ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 register field value suitable for setting the register. */
8255 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
8256 
8257 #ifndef __ASSEMBLY__
8258 /*
8259  * WARNING: The C register and register group struct declarations are provided for
8260  * convenience and illustrative purposes. They should, however, be used with
8261  * caution as the C language standard provides no guarantees about the alignment or
8262  * atomicity of device memory accesses. The recommended practice for writing
8263  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8264  * alt_write_word() functions.
8265  *
8266  * The struct declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE2.
8267  */
8268 struct ALT_IO48_HMC_MMR_NIOSRESERVE2_s
8269 {
8270  uint32_t nios_reserve2 : 16; /* ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2 */
8271  uint32_t : 16; /* *UNDEFINED* */
8272 };
8273 
8274 /* The typedef declaration for register ALT_IO48_HMC_MMR_NIOSRESERVE2. */
8275 typedef volatile struct ALT_IO48_HMC_MMR_NIOSRESERVE2_s ALT_IO48_HMC_MMR_NIOSRESERVE2_t;
8276 #endif /* __ASSEMBLY__ */
8277 
8278 /* The reset value of the ALT_IO48_HMC_MMR_NIOSRESERVE2 register. */
8279 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_RESET 0x00000000
8280 /* The byte offset of the ALT_IO48_HMC_MMR_NIOSRESERVE2 register from the beginning of the component. */
8281 #define ALT_IO48_HMC_MMR_NIOSRESERVE2_OFST 0x118
8282 
8283 #ifndef __ASSEMBLY__
8284 /*
8285  * WARNING: The C register and register group struct declarations are provided for
8286  * convenience and illustrative purposes. They should, however, be used with
8287  * caution as the C language standard provides no guarantees about the alignment or
8288  * atomicity of device memory accesses. The recommended practice for writing
8289  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8290  * alt_write_word() functions.
8291  *
8292  * The struct declaration for register group ALT_IO48_HMC_MMR.
8293  */
8294 struct ALT_IO48_HMC_MMR_s
8295 {
8296  ALT_IO48_HMC_MMR_DBGCFG0_t dbgcfg0; /* ALT_IO48_HMC_MMR_DBGCFG0 */
8297  ALT_IO48_HMC_MMR_DBGCFG1_t dbgcfg1; /* ALT_IO48_HMC_MMR_DBGCFG1 */
8298  ALT_IO48_HMC_MMR_DBGCFG2_t dbgcfg2; /* ALT_IO48_HMC_MMR_DBGCFG2 */
8299  ALT_IO48_HMC_MMR_DBGCFG3_t dbgcfg3; /* ALT_IO48_HMC_MMR_DBGCFG3 */
8300  ALT_IO48_HMC_MMR_DBGCFG4_t dbgcfg4; /* ALT_IO48_HMC_MMR_DBGCFG4 */
8301  ALT_IO48_HMC_MMR_DBGCFG5_t dbgcfg5; /* ALT_IO48_HMC_MMR_DBGCFG5 */
8302  ALT_IO48_HMC_MMR_DBGCFG6_t dbgcfg6; /* ALT_IO48_HMC_MMR_DBGCFG6 */
8303  ALT_IO48_HMC_MMR_RESERVE0_t reserve0; /* ALT_IO48_HMC_MMR_RESERVE0 */
8304  ALT_IO48_HMC_MMR_RESERVE1_t reserve1; /* ALT_IO48_HMC_MMR_RESERVE1 */
8305  ALT_IO48_HMC_MMR_RESERVE2_t reserve2; /* ALT_IO48_HMC_MMR_RESERVE2 */
8306  ALT_IO48_HMC_MMR_CTLCFG0_t ctrlcfg0; /* ALT_IO48_HMC_MMR_CTLCFG0 */
8307  ALT_IO48_HMC_MMR_CTLCFG1_t ctrlcfg1; /* ALT_IO48_HMC_MMR_CTLCFG1 */
8308  ALT_IO48_HMC_MMR_CTLCFG2_t ctrlcfg2; /* ALT_IO48_HMC_MMR_CTLCFG2 */
8309  ALT_IO48_HMC_MMR_CTLCFG3_t ctrlcfg3; /* ALT_IO48_HMC_MMR_CTLCFG3 */
8310  ALT_IO48_HMC_MMR_CTLCFG4_t ctrlcfg4; /* ALT_IO48_HMC_MMR_CTLCFG4 */
8311  ALT_IO48_HMC_MMR_CTLCFG5_t ctrlcfg5; /* ALT_IO48_HMC_MMR_CTLCFG5 */
8312  ALT_IO48_HMC_MMR_CTLCFG6_t ctrlcfg6; /* ALT_IO48_HMC_MMR_CTLCFG6 */
8313  ALT_IO48_HMC_MMR_CTLCFG7_t ctrlcfg7; /* ALT_IO48_HMC_MMR_CTLCFG7 */
8314  ALT_IO48_HMC_MMR_CTLCFG8_t ctrlcfg8; /* ALT_IO48_HMC_MMR_CTLCFG8 */
8315  ALT_IO48_HMC_MMR_CTLCFG9_t ctrlcfg9; /* ALT_IO48_HMC_MMR_CTLCFG9 */
8316  ALT_IO48_HMC_MMR_DRAMTIMING0_t dramtiming0; /* ALT_IO48_HMC_MMR_DRAMTIMING0 */
8317  ALT_IO48_HMC_MMR_DRAMODT0_t dramodt0; /* ALT_IO48_HMC_MMR_DRAMODT0 */
8318  ALT_IO48_HMC_MMR_DRAMODT1_t dramodt1; /* ALT_IO48_HMC_MMR_DRAMODT1 */
8319  ALT_IO48_HMC_MMR_SBCFG0_t sbcfg0; /* ALT_IO48_HMC_MMR_SBCFG0 */
8320  ALT_IO48_HMC_MMR_SBCFG1_t sbcfg1; /* ALT_IO48_HMC_MMR_SBCFG1 */
8321  ALT_IO48_HMC_MMR_SBCFG2_t sbcfg2; /* ALT_IO48_HMC_MMR_SBCFG2 */
8322  ALT_IO48_HMC_MMR_SBCFG3_t sbcfg3; /* ALT_IO48_HMC_MMR_SBCFG3 */
8323  ALT_IO48_HMC_MMR_SBCFG4_t sbcfg4; /* ALT_IO48_HMC_MMR_SBCFG4 */
8324  ALT_IO48_HMC_MMR_SBCFG5_t sbcfg5; /* ALT_IO48_HMC_MMR_SBCFG5 */
8325  ALT_IO48_HMC_MMR_SBCFG6_t sbcfg6; /* ALT_IO48_HMC_MMR_SBCFG6 */
8326  ALT_IO48_HMC_MMR_SBCFG7_t sbcfg7; /* ALT_IO48_HMC_MMR_SBCFG7 */
8327  ALT_IO48_HMC_MMR_CALTIMING0_t caltiming0; /* ALT_IO48_HMC_MMR_CALTIMING0 */
8328  ALT_IO48_HMC_MMR_CALTIMING1_t caltiming1; /* ALT_IO48_HMC_MMR_CALTIMING1 */
8329  ALT_IO48_HMC_MMR_CALTIMING2_t caltiming2; /* ALT_IO48_HMC_MMR_CALTIMING2 */
8330  ALT_IO48_HMC_MMR_CALTIMING3_t caltiming3; /* ALT_IO48_HMC_MMR_CALTIMING3 */
8331  ALT_IO48_HMC_MMR_CALTIMING4_t caltiming4; /* ALT_IO48_HMC_MMR_CALTIMING4 */
8332  ALT_IO48_HMC_MMR_CALTIMING5_t caltiming5; /* ALT_IO48_HMC_MMR_CALTIMING5 */
8333  ALT_IO48_HMC_MMR_CALTIMING6_t caltiming6; /* ALT_IO48_HMC_MMR_CALTIMING6 */
8334  ALT_IO48_HMC_MMR_CALTIMING7_t caltiming7; /* ALT_IO48_HMC_MMR_CALTIMING7 */
8335  ALT_IO48_HMC_MMR_CALTIMING8_t caltiming8; /* ALT_IO48_HMC_MMR_CALTIMING8 */
8336  ALT_IO48_HMC_MMR_CALTIMING9_t caltiming9; /* ALT_IO48_HMC_MMR_CALTIMING9 */
8337  ALT_IO48_HMC_MMR_CALTIMING10_t caltiming10; /* ALT_IO48_HMC_MMR_CALTIMING10 */
8338  ALT_IO48_HMC_MMR_DRAMADDRW_t dramaddrw; /* ALT_IO48_HMC_MMR_DRAMADDRW */
8339  ALT_IO48_HMC_MMR_SIDEBAND0_t sideband0; /* ALT_IO48_HMC_MMR_SIDEBAND0 */
8340  ALT_IO48_HMC_MMR_SIDEBAND1_t sideband1; /* ALT_IO48_HMC_MMR_SIDEBAND1 */
8341  ALT_IO48_HMC_MMR_SIDEBAND2_t sideband2; /* ALT_IO48_HMC_MMR_SIDEBAND2 */
8342  ALT_IO48_HMC_MMR_SIDEBAND3_t sideband3; /* ALT_IO48_HMC_MMR_SIDEBAND3 */
8343  ALT_IO48_HMC_MMR_SIDEBAND4_t sideband4; /* ALT_IO48_HMC_MMR_SIDEBAND4 */
8344  ALT_IO48_HMC_MMR_SIDEBAND5_t sideband5; /* ALT_IO48_HMC_MMR_SIDEBAND5 */
8345  ALT_IO48_HMC_MMR_SIDEBAND6_t sideband6; /* ALT_IO48_HMC_MMR_SIDEBAND6 */
8346  ALT_IO48_HMC_MMR_SIDEBAND7_t sideband7; /* ALT_IO48_HMC_MMR_SIDEBAND7 */
8347  ALT_IO48_HMC_MMR_SIDEBAND8_t sideband8; /* ALT_IO48_HMC_MMR_SIDEBAND8 */
8348  ALT_IO48_HMC_MMR_SIDEBAND9_t sideband9; /* ALT_IO48_HMC_MMR_SIDEBAND9 */
8349  ALT_IO48_HMC_MMR_SIDEBAND10_t sideband10; /* ALT_IO48_HMC_MMR_SIDEBAND10 */
8350  ALT_IO48_HMC_MMR_SIDEBAND11_t sideband11; /* ALT_IO48_HMC_MMR_SIDEBAND11 */
8351  ALT_IO48_HMC_MMR_SIDEBAND12_t sideband12; /* ALT_IO48_HMC_MMR_SIDEBAND12 */
8352  ALT_IO48_HMC_MMR_SIDEBAND13_t sideband13; /* ALT_IO48_HMC_MMR_SIDEBAND13 */
8353  ALT_IO48_HMC_MMR_SIDEBAND14_t sideband14; /* ALT_IO48_HMC_MMR_SIDEBAND14 */
8354  ALT_IO48_HMC_MMR_SIDEBAND15_t sideband15; /* ALT_IO48_HMC_MMR_SIDEBAND15 */
8355  ALT_IO48_HMC_MMR_DRAMSTS_t dramsts; /* ALT_IO48_HMC_MMR_DRAMSTS */
8356  ALT_IO48_HMC_MMR_DBGDONE_t dbgdone; /* ALT_IO48_HMC_MMR_DBGDONE */
8357  ALT_IO48_HMC_MMR_DBGSIGNALS_t dbgsignals; /* ALT_IO48_HMC_MMR_DBGSIGNALS */
8358  ALT_IO48_HMC_MMR_DBGRST_t dbgreset; /* ALT_IO48_HMC_MMR_DBGRST */
8359  ALT_IO48_HMC_MMR_DBGMATCH_t dbgmatch; /* ALT_IO48_HMC_MMR_DBGMATCH */
8360  ALT_IO48_HMC_MMR_CNTR0MSK_t counter0mask; /* ALT_IO48_HMC_MMR_CNTR0MSK */
8361  ALT_IO48_HMC_MMR_CNTR1MSK_t counter1mask; /* ALT_IO48_HMC_MMR_CNTR1MSK */
8362  ALT_IO48_HMC_MMR_CNTR0MATCH_t counter0match; /* ALT_IO48_HMC_MMR_CNTR0MATCH */
8363  ALT_IO48_HMC_MMR_CNTR1MATCH_t counter1match; /* ALT_IO48_HMC_MMR_CNTR1MATCH */
8364  ALT_IO48_HMC_MMR_NIOSRESERVE0_t niosreserve0; /* ALT_IO48_HMC_MMR_NIOSRESERVE0 */
8365  ALT_IO48_HMC_MMR_NIOSRESERVE1_t niosreserve1; /* ALT_IO48_HMC_MMR_NIOSRESERVE1 */
8366  ALT_IO48_HMC_MMR_NIOSRESERVE2_t niosreserve2; /* ALT_IO48_HMC_MMR_NIOSRESERVE2 */
8367  volatile uint32_t _pad_0x11c_0x1000[953]; /* *UNDEFINED* */
8368 };
8369 
8370 /* The typedef declaration for register group ALT_IO48_HMC_MMR. */
8371 typedef volatile struct ALT_IO48_HMC_MMR_s ALT_IO48_HMC_MMR_t;
8372 /* The struct declaration for the raw register contents of register group ALT_IO48_HMC_MMR. */
8373 struct ALT_IO48_HMC_MMR_raw_s
8374 {
8375  volatile uint32_t dbgcfg0; /* ALT_IO48_HMC_MMR_DBGCFG0 */
8376  volatile uint32_t dbgcfg1; /* ALT_IO48_HMC_MMR_DBGCFG1 */
8377  volatile uint32_t dbgcfg2; /* ALT_IO48_HMC_MMR_DBGCFG2 */
8378  volatile uint32_t dbgcfg3; /* ALT_IO48_HMC_MMR_DBGCFG3 */
8379  volatile uint32_t dbgcfg4; /* ALT_IO48_HMC_MMR_DBGCFG4 */
8380  volatile uint32_t dbgcfg5; /* ALT_IO48_HMC_MMR_DBGCFG5 */
8381  volatile uint32_t dbgcfg6; /* ALT_IO48_HMC_MMR_DBGCFG6 */
8382  volatile uint32_t reserve0; /* ALT_IO48_HMC_MMR_RESERVE0 */
8383  volatile uint32_t reserve1; /* ALT_IO48_HMC_MMR_RESERVE1 */
8384  volatile uint32_t reserve2; /* ALT_IO48_HMC_MMR_RESERVE2 */
8385  volatile uint32_t ctrlcfg0; /* ALT_IO48_HMC_MMR_CTLCFG0 */
8386  volatile uint32_t ctrlcfg1; /* ALT_IO48_HMC_MMR_CTLCFG1 */
8387  volatile uint32_t ctrlcfg2; /* ALT_IO48_HMC_MMR_CTLCFG2 */
8388  volatile uint32_t ctrlcfg3; /* ALT_IO48_HMC_MMR_CTLCFG3 */
8389  volatile uint32_t ctrlcfg4; /* ALT_IO48_HMC_MMR_CTLCFG4 */
8390  volatile uint32_t ctrlcfg5; /* ALT_IO48_HMC_MMR_CTLCFG5 */
8391  volatile uint32_t ctrlcfg6; /* ALT_IO48_HMC_MMR_CTLCFG6 */
8392  volatile uint32_t ctrlcfg7; /* ALT_IO48_HMC_MMR_CTLCFG7 */
8393  volatile uint32_t ctrlcfg8; /* ALT_IO48_HMC_MMR_CTLCFG8 */
8394  volatile uint32_t ctrlcfg9; /* ALT_IO48_HMC_MMR_CTLCFG9 */
8395  volatile uint32_t dramtiming0; /* ALT_IO48_HMC_MMR_DRAMTIMING0 */
8396  volatile uint32_t dramodt0; /* ALT_IO48_HMC_MMR_DRAMODT0 */
8397  volatile uint32_t dramodt1; /* ALT_IO48_HMC_MMR_DRAMODT1 */
8398  volatile uint32_t sbcfg0; /* ALT_IO48_HMC_MMR_SBCFG0 */
8399  volatile uint32_t sbcfg1; /* ALT_IO48_HMC_MMR_SBCFG1 */
8400  volatile uint32_t sbcfg2; /* ALT_IO48_HMC_MMR_SBCFG2 */
8401  volatile uint32_t sbcfg3; /* ALT_IO48_HMC_MMR_SBCFG3 */
8402  volatile uint32_t sbcfg4; /* ALT_IO48_HMC_MMR_SBCFG4 */
8403  volatile uint32_t sbcfg5; /* ALT_IO48_HMC_MMR_SBCFG5 */
8404  volatile uint32_t sbcfg6; /* ALT_IO48_HMC_MMR_SBCFG6 */
8405  volatile uint32_t sbcfg7; /* ALT_IO48_HMC_MMR_SBCFG7 */
8406  volatile uint32_t caltiming0; /* ALT_IO48_HMC_MMR_CALTIMING0 */
8407  volatile uint32_t caltiming1; /* ALT_IO48_HMC_MMR_CALTIMING1 */
8408  volatile uint32_t caltiming2; /* ALT_IO48_HMC_MMR_CALTIMING2 */
8409  volatile uint32_t caltiming3; /* ALT_IO48_HMC_MMR_CALTIMING3 */
8410  volatile uint32_t caltiming4; /* ALT_IO48_HMC_MMR_CALTIMING4 */
8411  volatile uint32_t caltiming5; /* ALT_IO48_HMC_MMR_CALTIMING5 */
8412  volatile uint32_t caltiming6; /* ALT_IO48_HMC_MMR_CALTIMING6 */
8413  volatile uint32_t caltiming7; /* ALT_IO48_HMC_MMR_CALTIMING7 */
8414  volatile uint32_t caltiming8; /* ALT_IO48_HMC_MMR_CALTIMING8 */
8415  volatile uint32_t caltiming9; /* ALT_IO48_HMC_MMR_CALTIMING9 */
8416  volatile uint32_t caltiming10; /* ALT_IO48_HMC_MMR_CALTIMING10 */
8417  volatile uint32_t dramaddrw; /* ALT_IO48_HMC_MMR_DRAMADDRW */
8418  volatile uint32_t sideband0; /* ALT_IO48_HMC_MMR_SIDEBAND0 */
8419  volatile uint32_t sideband1; /* ALT_IO48_HMC_MMR_SIDEBAND1 */
8420  volatile uint32_t sideband2; /* ALT_IO48_HMC_MMR_SIDEBAND2 */
8421  volatile uint32_t sideband3; /* ALT_IO48_HMC_MMR_SIDEBAND3 */
8422  volatile uint32_t sideband4; /* ALT_IO48_HMC_MMR_SIDEBAND4 */
8423  volatile uint32_t sideband5; /* ALT_IO48_HMC_MMR_SIDEBAND5 */
8424  volatile uint32_t sideband6; /* ALT_IO48_HMC_MMR_SIDEBAND6 */
8425  volatile uint32_t sideband7; /* ALT_IO48_HMC_MMR_SIDEBAND7 */
8426  volatile uint32_t sideband8; /* ALT_IO48_HMC_MMR_SIDEBAND8 */
8427  volatile uint32_t sideband9; /* ALT_IO48_HMC_MMR_SIDEBAND9 */
8428  volatile uint32_t sideband10; /* ALT_IO48_HMC_MMR_SIDEBAND10 */
8429  volatile uint32_t sideband11; /* ALT_IO48_HMC_MMR_SIDEBAND11 */
8430  volatile uint32_t sideband12; /* ALT_IO48_HMC_MMR_SIDEBAND12 */
8431  volatile uint32_t sideband13; /* ALT_IO48_HMC_MMR_SIDEBAND13 */
8432  volatile uint32_t sideband14; /* ALT_IO48_HMC_MMR_SIDEBAND14 */
8433  volatile uint32_t sideband15; /* ALT_IO48_HMC_MMR_SIDEBAND15 */
8434  volatile uint32_t dramsts; /* ALT_IO48_HMC_MMR_DRAMSTS */
8435  volatile uint32_t dbgdone; /* ALT_IO48_HMC_MMR_DBGDONE */
8436  volatile uint32_t dbgsignals; /* ALT_IO48_HMC_MMR_DBGSIGNALS */
8437  volatile uint32_t dbgreset; /* ALT_IO48_HMC_MMR_DBGRST */
8438  volatile uint32_t dbgmatch; /* ALT_IO48_HMC_MMR_DBGMATCH */
8439  volatile uint32_t counter0mask; /* ALT_IO48_HMC_MMR_CNTR0MSK */
8440  volatile uint32_t counter1mask; /* ALT_IO48_HMC_MMR_CNTR1MSK */
8441  volatile uint32_t counter0match; /* ALT_IO48_HMC_MMR_CNTR0MATCH */
8442  volatile uint32_t counter1match; /* ALT_IO48_HMC_MMR_CNTR1MATCH */
8443  volatile uint32_t niosreserve0; /* ALT_IO48_HMC_MMR_NIOSRESERVE0 */
8444  volatile uint32_t niosreserve1; /* ALT_IO48_HMC_MMR_NIOSRESERVE1 */
8445  volatile uint32_t niosreserve2; /* ALT_IO48_HMC_MMR_NIOSRESERVE2 */
8446  uint32_t _pad_0x11c_0x1000[953]; /* *UNDEFINED* */
8447 };
8448 
8449 /* The typedef declaration for the raw register contents of register group ALT_IO48_HMC_MMR. */
8450 typedef volatile struct ALT_IO48_HMC_MMR_raw_s ALT_IO48_HMC_MMR_raw_t;
8451 #endif /* __ASSEMBLY__ */
8452 
8453 
8454 #ifdef __cplusplus
8455 }
8456 #endif /* __cplusplus */
8457 #endif /* __ALT_SOCAL_IO48_HMC_MMR_H__ */
8458