35 #ifndef __ALT_SOCAL_SPIS_H__
36 #define __ALT_SOCAL_SPIS_H__
136 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_04BITS 0x3
142 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_05BITS 0x4
148 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_06BITS 0x5
154 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_07BITS 0x6
160 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_08BITS 0x7
166 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_09BITS 0x8
172 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_10BITS 0x9
178 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_11BITS 0xa
184 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_12BITS 0xb
190 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_13BITS 0xc
196 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_14BITS 0xd
202 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_15BITS 0xe
208 #define ALT_SPIS_CTRLR0_DFS_E_FRAME_16BITS 0xf
211 #define ALT_SPIS_CTRLR0_DFS_LSB 0
213 #define ALT_SPIS_CTRLR0_DFS_MSB 3
215 #define ALT_SPIS_CTRLR0_DFS_WIDTH 4
217 #define ALT_SPIS_CTRLR0_DFS_SET_MSK 0x0000000f
219 #define ALT_SPIS_CTRLR0_DFS_CLR_MSK 0xfffffff0
221 #define ALT_SPIS_CTRLR0_DFS_RESET 0x0
223 #define ALT_SPIS_CTRLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
225 #define ALT_SPIS_CTRLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
258 #define ALT_SPIS_CTRLR0_FRF_E_MOTOROLLA_SPI 0x0
264 #define ALT_SPIS_CTRLR0_FRF_E_TEXAS_SSP 0x1
270 #define ALT_SPIS_CTRLR0_FRF_E_NS_MICROWIRE 0x2
273 #define ALT_SPIS_CTRLR0_FRF_LSB 4
275 #define ALT_SPIS_CTRLR0_FRF_MSB 5
277 #define ALT_SPIS_CTRLR0_FRF_WIDTH 2
279 #define ALT_SPIS_CTRLR0_FRF_SET_MSK 0x00000030
281 #define ALT_SPIS_CTRLR0_FRF_CLR_MSK 0xffffffcf
283 #define ALT_SPIS_CTRLR0_FRF_RESET 0x0
285 #define ALT_SPIS_CTRLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
287 #define ALT_SPIS_CTRLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
325 #define ALT_SPIS_CTRLR0_SCPH_E_MIDDLE_BIT 0x0
331 #define ALT_SPIS_CTRLR0_SCPH_E_START_BIT 0x1
334 #define ALT_SPIS_CTRLR0_SCPH_LSB 6
336 #define ALT_SPIS_CTRLR0_SCPH_MSB 6
338 #define ALT_SPIS_CTRLR0_SCPH_WIDTH 1
340 #define ALT_SPIS_CTRLR0_SCPH_SET_MSK 0x00000040
342 #define ALT_SPIS_CTRLR0_SCPH_CLR_MSK 0xffffffbf
344 #define ALT_SPIS_CTRLR0_SCPH_RESET 0x0
346 #define ALT_SPIS_CTRLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
348 #define ALT_SPIS_CTRLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
380 #define ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_HIGH 0x0
386 #define ALT_SPIS_CTRLR0_SCPOL_E_INACTIVE_LOW 0x1
389 #define ALT_SPIS_CTRLR0_SCPOL_LSB 7
391 #define ALT_SPIS_CTRLR0_SCPOL_MSB 7
393 #define ALT_SPIS_CTRLR0_SCPOL_WIDTH 1
395 #define ALT_SPIS_CTRLR0_SCPOL_SET_MSK 0x00000080
397 #define ALT_SPIS_CTRLR0_SCPOL_CLR_MSK 0xffffff7f
399 #define ALT_SPIS_CTRLR0_SCPOL_RESET 0x0
401 #define ALT_SPIS_CTRLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
403 #define ALT_SPIS_CTRLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
466 #define ALT_SPIS_CTRLR0_TMOD_E_TX_AND_RX 0x0
472 #define ALT_SPIS_CTRLR0_TMOD_E_TX_ONLY 0x1
478 #define ALT_SPIS_CTRLR0_TMOD_E_RX_ONLY 0x2
484 #define ALT_SPIS_CTRLR0_TMOD_E_EEPROM_READ 0x3
487 #define ALT_SPIS_CTRLR0_TMOD_LSB 8
489 #define ALT_SPIS_CTRLR0_TMOD_MSB 9
491 #define ALT_SPIS_CTRLR0_TMOD_WIDTH 2
493 #define ALT_SPIS_CTRLR0_TMOD_SET_MSK 0x00000300
495 #define ALT_SPIS_CTRLR0_TMOD_CLR_MSK 0xfffffcff
497 #define ALT_SPIS_CTRLR0_TMOD_RESET 0x0
499 #define ALT_SPIS_CTRLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
501 #define ALT_SPIS_CTRLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
551 #define ALT_SPIS_CTRLR0_SLV_OE_E_ENABLED 0x0
557 #define ALT_SPIS_CTRLR0_SLV_OE_E_DISABLED 0x1
560 #define ALT_SPIS_CTRLR0_SLV_OE_LSB 10
562 #define ALT_SPIS_CTRLR0_SLV_OE_MSB 10
564 #define ALT_SPIS_CTRLR0_SLV_OE_WIDTH 1
566 #define ALT_SPIS_CTRLR0_SLV_OE_SET_MSK 0x00000400
568 #define ALT_SPIS_CTRLR0_SLV_OE_CLR_MSK 0xfffffbff
570 #define ALT_SPIS_CTRLR0_SLV_OE_RESET 0x0
572 #define ALT_SPIS_CTRLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
574 #define ALT_SPIS_CTRLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
604 #define ALT_SPIS_CTRLR0_SRL_E_NORMAL_MODE 0x0
610 #define ALT_SPIS_CTRLR0_SRL_E_TESTING_MODE 0x1
613 #define ALT_SPIS_CTRLR0_SRL_LSB 11
615 #define ALT_SPIS_CTRLR0_SRL_MSB 11
617 #define ALT_SPIS_CTRLR0_SRL_WIDTH 1
619 #define ALT_SPIS_CTRLR0_SRL_SET_MSK 0x00000800
621 #define ALT_SPIS_CTRLR0_SRL_CLR_MSK 0xfffff7ff
623 #define ALT_SPIS_CTRLR0_SRL_RESET 0x0
625 #define ALT_SPIS_CTRLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
627 #define ALT_SPIS_CTRLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
673 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_01_BIT 0x0
679 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_02_BIT 0x1
685 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_03_BIT 0x2
691 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_04_BIT 0x3
697 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_05_BIT 0x4
703 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_06_BIT 0x5
709 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_07_BIT 0x6
715 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_08_BIT 0x7
721 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_09_BIT 0x8
727 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_10_BIT 0x9
733 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_11_BIT 0xa
739 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_12_BIT 0xb
745 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_13_BIT 0xc
751 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_14_BIT 0xd
757 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_15_BIT 0xe
763 #define ALT_SPIS_CTRLR0_CFS_E_SIZE_16_BIT 0xf
766 #define ALT_SPIS_CTRLR0_CFS_LSB 12
768 #define ALT_SPIS_CTRLR0_CFS_MSB 15
770 #define ALT_SPIS_CTRLR0_CFS_WIDTH 4
772 #define ALT_SPIS_CTRLR0_CFS_SET_MSK 0x0000f000
774 #define ALT_SPIS_CTRLR0_CFS_CLR_MSK 0xffff0fff
776 #define ALT_SPIS_CTRLR0_CFS_RESET 0x0
778 #define ALT_SPIS_CTRLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
780 #define ALT_SPIS_CTRLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
848 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_04BITS 0x3
854 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_05BITS 0x4
860 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_06BITS 0x5
866 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_07BITS 0x6
872 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_08BITS 0x7
878 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_09BITS 0x8
884 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_10BITS 0x9
890 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_11BITS 0xa
896 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_12BITS 0xb
902 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_13BITS 0xc
908 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_14BITS 0xd
914 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_15BITS 0xe
920 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_16BITS 0xf
926 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_17BITS 0x10
932 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_18BITS 0x11
938 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_19BITS 0x12
944 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_20BITS 0x13
950 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_21BITS 0x14
956 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_22BITS 0x15
962 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_23BITS 0x16
968 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_24BITS 0x17
974 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_25BITS 0x18
980 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_26BITS 0x19
986 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_27BITS 0x1a
992 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_28BITS 0x1b
998 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_29BITS 0x1c
1004 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_30BITS 0x1d
1010 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_31BITS 0x1e
1016 #define ALT_SPIS_CTRLR0_DFS_32_E_FRAME_32BITS 0x1f
1019 #define ALT_SPIS_CTRLR0_DFS_32_LSB 16
1021 #define ALT_SPIS_CTRLR0_DFS_32_MSB 20
1023 #define ALT_SPIS_CTRLR0_DFS_32_WIDTH 5
1025 #define ALT_SPIS_CTRLR0_DFS_32_SET_MSK 0x001f0000
1027 #define ALT_SPIS_CTRLR0_DFS_32_CLR_MSK 0xffe0ffff
1029 #define ALT_SPIS_CTRLR0_DFS_32_RESET 0x7
1031 #define ALT_SPIS_CTRLR0_DFS_32_GET(value) (((value) & 0x001f0000) >> 16)
1033 #define ALT_SPIS_CTRLR0_DFS_32_SET(value) (((value) << 16) & 0x001f0000)
1055 #define ALT_SPIS_CTRLR0_SPI_FRF_LSB 21
1057 #define ALT_SPIS_CTRLR0_SPI_FRF_MSB 22
1059 #define ALT_SPIS_CTRLR0_SPI_FRF_WIDTH 2
1061 #define ALT_SPIS_CTRLR0_SPI_FRF_SET_MSK 0x00600000
1063 #define ALT_SPIS_CTRLR0_SPI_FRF_CLR_MSK 0xff9fffff
1065 #define ALT_SPIS_CTRLR0_SPI_FRF_RESET 0x0
1067 #define ALT_SPIS_CTRLR0_SPI_FRF_GET(value) (((value) & 0x00600000) >> 21)
1069 #define ALT_SPIS_CTRLR0_SPI_FRF_SET(value) (((value) << 21) & 0x00600000)
1080 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_LSB 23
1082 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_MSB 31
1084 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_WIDTH 9
1086 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_SET_MSK 0xff800000
1088 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_CLR_MSK 0x007fffff
1090 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_RESET 0x0
1092 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_GET(value) (((value) & 0xff800000) >> 23)
1094 #define ALT_SPIS_CTRLR0_RSVD_CTRLR0_SET(value) (((value) << 23) & 0xff800000)
1096 #ifndef __ASSEMBLY__
1108 struct ALT_SPIS_CTRLR0_s
1110 const volatile uint32_t DFS : 4;
1111 volatile uint32_t FRF : 2;
1112 volatile uint32_t SCPH : 1;
1113 volatile uint32_t SCPOL : 1;
1114 volatile uint32_t TMOD : 2;
1115 volatile uint32_t SLV_OE : 1;
1116 volatile uint32_t SRL : 1;
1117 volatile uint32_t CFS : 4;
1118 volatile uint32_t DFS_32 : 5;
1119 const volatile uint32_t SPI_FRF : 2;
1120 const volatile uint32_t RSVD_CTRLR0 : 9;
1124 typedef struct ALT_SPIS_CTRLR0_s ALT_SPIS_CTRLR0_t;
1128 #define ALT_SPIS_CTRLR0_RESET 0x00070000
1130 #define ALT_SPIS_CTRLR0_OFST 0x0
1132 #define ALT_SPIS_CTRLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTRLR0_OFST))
1179 #define ALT_SPIS_SSIENR_SSI_EN_E_DISABLE 0x0
1185 #define ALT_SPIS_SSIENR_SSI_EN_E_ENABLED 0x1
1188 #define ALT_SPIS_SSIENR_SSI_EN_LSB 0
1190 #define ALT_SPIS_SSIENR_SSI_EN_MSB 0
1192 #define ALT_SPIS_SSIENR_SSI_EN_WIDTH 1
1194 #define ALT_SPIS_SSIENR_SSI_EN_SET_MSK 0x00000001
1196 #define ALT_SPIS_SSIENR_SSI_EN_CLR_MSK 0xfffffffe
1198 #define ALT_SPIS_SSIENR_SSI_EN_RESET 0x0
1200 #define ALT_SPIS_SSIENR_SSI_EN_GET(value) (((value) & 0x00000001) >> 0)
1202 #define ALT_SPIS_SSIENR_SSI_EN_SET(value) (((value) << 0) & 0x00000001)
1213 #define ALT_SPIS_SSIENR_RSVD_SSIENR_LSB 1
1215 #define ALT_SPIS_SSIENR_RSVD_SSIENR_MSB 31
1217 #define ALT_SPIS_SSIENR_RSVD_SSIENR_WIDTH 31
1219 #define ALT_SPIS_SSIENR_RSVD_SSIENR_SET_MSK 0xfffffffe
1221 #define ALT_SPIS_SSIENR_RSVD_SSIENR_CLR_MSK 0x00000001
1223 #define ALT_SPIS_SSIENR_RSVD_SSIENR_RESET 0x0
1225 #define ALT_SPIS_SSIENR_RSVD_SSIENR_GET(value) (((value) & 0xfffffffe) >> 1)
1227 #define ALT_SPIS_SSIENR_RSVD_SSIENR_SET(value) (((value) << 1) & 0xfffffffe)
1229 #ifndef __ASSEMBLY__
1241 struct ALT_SPIS_SSIENR_s
1243 volatile uint32_t SSI_EN : 1;
1244 const volatile uint32_t RSVD_SSIENR : 31;
1248 typedef struct ALT_SPIS_SSIENR_s ALT_SPIS_SSIENR_t;
1252 #define ALT_SPIS_SSIENR_RESET 0x00000000
1254 #define ALT_SPIS_SSIENR_OFST 0x8
1256 #define ALT_SPIS_SSIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SSIENR_OFST))
1315 #define ALT_SPIS_MWCR_MWMOD_E_NON_SEQUENTIAL 0x0
1321 #define ALT_SPIS_MWCR_MWMOD_E_SEQUENTIAL 0x1
1324 #define ALT_SPIS_MWCR_MWMOD_LSB 0
1326 #define ALT_SPIS_MWCR_MWMOD_MSB 0
1328 #define ALT_SPIS_MWCR_MWMOD_WIDTH 1
1330 #define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
1332 #define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
1334 #define ALT_SPIS_MWCR_MWMOD_RESET 0x0
1336 #define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
1338 #define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
1370 #define ALT_SPIS_MWCR_MDD_E_RECEIVE 0x0
1376 #define ALT_SPIS_MWCR_MDD_E_TRANSMIT 0x1
1379 #define ALT_SPIS_MWCR_MDD_LSB 1
1381 #define ALT_SPIS_MWCR_MDD_MSB 1
1383 #define ALT_SPIS_MWCR_MDD_WIDTH 1
1385 #define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
1387 #define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
1389 #define ALT_SPIS_MWCR_MDD_RESET 0x0
1391 #define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1393 #define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1404 #define ALT_SPIS_MWCR_RSVD_MHS_LSB 2
1406 #define ALT_SPIS_MWCR_RSVD_MHS_MSB 2
1408 #define ALT_SPIS_MWCR_RSVD_MHS_WIDTH 1
1410 #define ALT_SPIS_MWCR_RSVD_MHS_SET_MSK 0x00000004
1412 #define ALT_SPIS_MWCR_RSVD_MHS_CLR_MSK 0xfffffffb
1414 #define ALT_SPIS_MWCR_RSVD_MHS_RESET 0x0
1416 #define ALT_SPIS_MWCR_RSVD_MHS_GET(value) (((value) & 0x00000004) >> 2)
1418 #define ALT_SPIS_MWCR_RSVD_MHS_SET(value) (((value) << 2) & 0x00000004)
1429 #define ALT_SPIS_MWCR_RSVD_MWCR_LSB 3
1431 #define ALT_SPIS_MWCR_RSVD_MWCR_MSB 31
1433 #define ALT_SPIS_MWCR_RSVD_MWCR_WIDTH 29
1435 #define ALT_SPIS_MWCR_RSVD_MWCR_SET_MSK 0xfffffff8
1437 #define ALT_SPIS_MWCR_RSVD_MWCR_CLR_MSK 0x00000007
1439 #define ALT_SPIS_MWCR_RSVD_MWCR_RESET 0x0
1441 #define ALT_SPIS_MWCR_RSVD_MWCR_GET(value) (((value) & 0xfffffff8) >> 3)
1443 #define ALT_SPIS_MWCR_RSVD_MWCR_SET(value) (((value) << 3) & 0xfffffff8)
1445 #ifndef __ASSEMBLY__
1457 struct ALT_SPIS_MWCR_s
1459 volatile uint32_t MWMOD : 1;
1460 volatile uint32_t MDD : 1;
1461 const volatile uint32_t RSVD_MHS : 1;
1462 const volatile uint32_t RSVD_MWCR : 29;
1466 typedef struct ALT_SPIS_MWCR_s ALT_SPIS_MWCR_t;
1470 #define ALT_SPIS_MWCR_RESET 0x00000000
1472 #define ALT_SPIS_MWCR_OFST 0xc
1474 #define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
1516 #define ALT_SPIS_TXFTLR_TFT_LSB 0
1518 #define ALT_SPIS_TXFTLR_TFT_MSB 7
1520 #define ALT_SPIS_TXFTLR_TFT_WIDTH 8
1522 #define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
1524 #define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
1526 #define ALT_SPIS_TXFTLR_TFT_RESET 0x0
1528 #define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1530 #define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1541 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_LSB 8
1543 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_MSB 31
1545 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_WIDTH 24
1547 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_SET_MSK 0xffffff00
1549 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_CLR_MSK 0x000000ff
1551 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_RESET 0x0
1553 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1555 #define ALT_SPIS_TXFTLR_RSVD_TXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1557 #ifndef __ASSEMBLY__
1569 struct ALT_SPIS_TXFTLR_s
1571 volatile uint32_t TFT : 8;
1572 const volatile uint32_t RSVD_TXFTLR : 24;
1576 typedef struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t;
1580 #define ALT_SPIS_TXFTLR_RESET 0x00000000
1582 #define ALT_SPIS_TXFTLR_OFST 0x18
1584 #define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
1626 #define ALT_SPIS_RXFTLR_RFT_LSB 0
1628 #define ALT_SPIS_RXFTLR_RFT_MSB 7
1630 #define ALT_SPIS_RXFTLR_RFT_WIDTH 8
1632 #define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
1634 #define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
1636 #define ALT_SPIS_RXFTLR_RFT_RESET 0x0
1638 #define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1640 #define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1651 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_LSB 8
1653 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_MSB 31
1655 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_WIDTH 24
1657 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_SET_MSK 0xffffff00
1659 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_CLR_MSK 0x000000ff
1661 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_RESET 0x0
1663 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_GET(value) (((value) & 0xffffff00) >> 8)
1665 #define ALT_SPIS_RXFTLR_RSVD_RXFTLR_SET(value) (((value) << 8) & 0xffffff00)
1667 #ifndef __ASSEMBLY__
1679 struct ALT_SPIS_RXFTLR_s
1681 volatile uint32_t RFT : 8;
1682 const volatile uint32_t RSVD_RXFTLR : 24;
1686 typedef struct ALT_SPIS_RXFTLR_s ALT_SPIS_RXFTLR_t;
1690 #define ALT_SPIS_RXFTLR_RESET 0x00000000
1692 #define ALT_SPIS_RXFTLR_OFST 0x1c
1694 #define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
1720 #define ALT_SPIS_TXFLR_TXTFL_LSB 0
1722 #define ALT_SPIS_TXFLR_TXTFL_MSB 8
1724 #define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
1726 #define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
1728 #define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1730 #define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
1732 #define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1734 #define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1745 #define ALT_SPIS_TXFLR_RSVD_TXFLR_LSB 9
1747 #define ALT_SPIS_TXFLR_RSVD_TXFLR_MSB 31
1749 #define ALT_SPIS_TXFLR_RSVD_TXFLR_WIDTH 23
1751 #define ALT_SPIS_TXFLR_RSVD_TXFLR_SET_MSK 0xfffffe00
1753 #define ALT_SPIS_TXFLR_RSVD_TXFLR_CLR_MSK 0x000001ff
1755 #define ALT_SPIS_TXFLR_RSVD_TXFLR_RESET 0x0
1757 #define ALT_SPIS_TXFLR_RSVD_TXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
1759 #define ALT_SPIS_TXFLR_RSVD_TXFLR_SET(value) (((value) << 9) & 0xfffffe00)
1761 #ifndef __ASSEMBLY__
1773 struct ALT_SPIS_TXFLR_s
1775 const volatile uint32_t TXTFL : 9;
1776 const volatile uint32_t RSVD_TXFLR : 23;
1780 typedef struct ALT_SPIS_TXFLR_s ALT_SPIS_TXFLR_t;
1784 #define ALT_SPIS_TXFLR_RESET 0x00000000
1786 #define ALT_SPIS_TXFLR_OFST 0x20
1788 #define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
1814 #define ALT_SPIS_RXFLR_RXTFL_LSB 0
1816 #define ALT_SPIS_RXFLR_RXTFL_MSB 8
1818 #define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
1820 #define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
1822 #define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1824 #define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
1826 #define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1828 #define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1839 #define ALT_SPIS_RXFLR_RSVD_RXFLR_LSB 9
1841 #define ALT_SPIS_RXFLR_RSVD_RXFLR_MSB 31
1843 #define ALT_SPIS_RXFLR_RSVD_RXFLR_WIDTH 23
1845 #define ALT_SPIS_RXFLR_RSVD_RXFLR_SET_MSK 0xfffffe00
1847 #define ALT_SPIS_RXFLR_RSVD_RXFLR_CLR_MSK 0x000001ff
1849 #define ALT_SPIS_RXFLR_RSVD_RXFLR_RESET 0x0
1851 #define ALT_SPIS_RXFLR_RSVD_RXFLR_GET(value) (((value) & 0xfffffe00) >> 9)
1853 #define ALT_SPIS_RXFLR_RSVD_RXFLR_SET(value) (((value) << 9) & 0xfffffe00)
1855 #ifndef __ASSEMBLY__
1867 struct ALT_SPIS_RXFLR_s
1869 const volatile uint32_t RXTFL : 9;
1870 const volatile uint32_t RSVD_RXFLR : 23;
1874 typedef struct ALT_SPIS_RXFLR_s ALT_SPIS_RXFLR_t;
1878 #define ALT_SPIS_RXFLR_RESET 0x00000000
1880 #define ALT_SPIS_RXFLR_OFST 0x24
1882 #define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1939 #define ALT_SPIS_SR_BUSY_E_INACTIVE 0x0
1945 #define ALT_SPIS_SR_BUSY_E_ACTIVE 0x1
1948 #define ALT_SPIS_SR_BUSY_LSB 0
1950 #define ALT_SPIS_SR_BUSY_MSB 0
1952 #define ALT_SPIS_SR_BUSY_WIDTH 1
1954 #define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1956 #define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1958 #define ALT_SPIS_SR_BUSY_RESET 0x0
1960 #define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1962 #define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1990 #define ALT_SPIS_SR_TFNF_E_FULL 0x0
1996 #define ALT_SPIS_SR_TFNF_E_NOT_FULL 0x1
1999 #define ALT_SPIS_SR_TFNF_LSB 1
2001 #define ALT_SPIS_SR_TFNF_MSB 1
2003 #define ALT_SPIS_SR_TFNF_WIDTH 1
2005 #define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
2007 #define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
2009 #define ALT_SPIS_SR_TFNF_RESET 0x1
2011 #define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
2013 #define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
2045 #define ALT_SPIS_SR_TFE_E_NOT_EMPTY 0x0
2051 #define ALT_SPIS_SR_TFE_E_EMPTY 0x1
2054 #define ALT_SPIS_SR_TFE_LSB 2
2056 #define ALT_SPIS_SR_TFE_MSB 2
2058 #define ALT_SPIS_SR_TFE_WIDTH 1
2060 #define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
2062 #define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
2064 #define ALT_SPIS_SR_TFE_RESET 0x1
2066 #define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
2068 #define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
2100 #define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
2106 #define ALT_SPIS_SR_RFNE_E_NOT_EMPTY 0x1
2109 #define ALT_SPIS_SR_RFNE_LSB 3
2111 #define ALT_SPIS_SR_RFNE_MSB 3
2113 #define ALT_SPIS_SR_RFNE_WIDTH 1
2115 #define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
2117 #define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
2119 #define ALT_SPIS_SR_RFNE_RESET 0x0
2121 #define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
2123 #define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
2153 #define ALT_SPIS_SR_RFF_E_NOT_FULL 0x0
2159 #define ALT_SPIS_SR_RFF_E_FULL 0x1
2162 #define ALT_SPIS_SR_RFF_LSB 4
2164 #define ALT_SPIS_SR_RFF_MSB 4
2166 #define ALT_SPIS_SR_RFF_WIDTH 1
2168 #define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
2170 #define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
2172 #define ALT_SPIS_SR_RFF_RESET 0x0
2174 #define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
2176 #define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
2210 #define ALT_SPIS_SR_TXE_E_NO_ERROR 0x0
2216 #define ALT_SPIS_SR_TXE_E_TX_ERROR 0x1
2219 #define ALT_SPIS_SR_TXE_LSB 5
2221 #define ALT_SPIS_SR_TXE_MSB 5
2223 #define ALT_SPIS_SR_TXE_WIDTH 1
2225 #define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
2227 #define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
2229 #define ALT_SPIS_SR_TXE_RESET 0x0
2231 #define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
2233 #define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
2244 #define ALT_SPIS_SR_RSVD_DCOL_LSB 6
2246 #define ALT_SPIS_SR_RSVD_DCOL_MSB 6
2248 #define ALT_SPIS_SR_RSVD_DCOL_WIDTH 1
2250 #define ALT_SPIS_SR_RSVD_DCOL_SET_MSK 0x00000040
2252 #define ALT_SPIS_SR_RSVD_DCOL_CLR_MSK 0xffffffbf
2254 #define ALT_SPIS_SR_RSVD_DCOL_RESET 0x0
2256 #define ALT_SPIS_SR_RSVD_DCOL_GET(value) (((value) & 0x00000040) >> 6)
2258 #define ALT_SPIS_SR_RSVD_DCOL_SET(value) (((value) << 6) & 0x00000040)
2269 #define ALT_SPIS_SR_RSVD_SR_LSB 7
2271 #define ALT_SPIS_SR_RSVD_SR_MSB 31
2273 #define ALT_SPIS_SR_RSVD_SR_WIDTH 25
2275 #define ALT_SPIS_SR_RSVD_SR_SET_MSK 0xffffff80
2277 #define ALT_SPIS_SR_RSVD_SR_CLR_MSK 0x0000007f
2279 #define ALT_SPIS_SR_RSVD_SR_RESET 0x0
2281 #define ALT_SPIS_SR_RSVD_SR_GET(value) (((value) & 0xffffff80) >> 7)
2283 #define ALT_SPIS_SR_RSVD_SR_SET(value) (((value) << 7) & 0xffffff80)
2285 #ifndef __ASSEMBLY__
2297 struct ALT_SPIS_SR_s
2299 const volatile uint32_t BUSY : 1;
2300 const volatile uint32_t TFNF : 1;
2301 const volatile uint32_t TFE : 1;
2302 const volatile uint32_t RFNE : 1;
2303 const volatile uint32_t RFF : 1;
2304 const volatile uint32_t TXE : 1;
2305 const volatile uint32_t RSVD_DCOL : 1;
2306 const volatile uint32_t RSVD_SR : 25;
2310 typedef struct ALT_SPIS_SR_s ALT_SPIS_SR_t;
2314 #define ALT_SPIS_SR_RESET 0x00000006
2316 #define ALT_SPIS_SR_OFST 0x28
2318 #define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
2362 #define ALT_SPIS_IMR_TXEIM_E_MASKED 0x0
2368 #define ALT_SPIS_IMR_TXEIM_E_UNMASKED 0x1
2371 #define ALT_SPIS_IMR_TXEIM_LSB 0
2373 #define ALT_SPIS_IMR_TXEIM_MSB 0
2375 #define ALT_SPIS_IMR_TXEIM_WIDTH 1
2377 #define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
2379 #define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
2381 #define ALT_SPIS_IMR_TXEIM_RESET 0x1
2383 #define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2385 #define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2411 #define ALT_SPIS_IMR_TXOIM_E_MASKED 0x0
2417 #define ALT_SPIS_IMR_TXOIM_E_UNMASKED 0x1
2420 #define ALT_SPIS_IMR_TXOIM_LSB 1
2422 #define ALT_SPIS_IMR_TXOIM_MSB 1
2424 #define ALT_SPIS_IMR_TXOIM_WIDTH 1
2426 #define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
2428 #define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
2430 #define ALT_SPIS_IMR_TXOIM_RESET 0x1
2432 #define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2434 #define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2460 #define ALT_SPIS_IMR_RXUIM_E_MASKED 0x0
2466 #define ALT_SPIS_IMR_RXUIM_E_UNMASKED 0x1
2469 #define ALT_SPIS_IMR_RXUIM_LSB 2
2471 #define ALT_SPIS_IMR_RXUIM_MSB 2
2473 #define ALT_SPIS_IMR_RXUIM_WIDTH 1
2475 #define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
2477 #define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
2479 #define ALT_SPIS_IMR_RXUIM_RESET 0x1
2481 #define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2483 #define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2509 #define ALT_SPIS_IMR_RXOIM_E_MASKED 0x0
2515 #define ALT_SPIS_IMR_RXOIM_E_UNMASKED 0x1
2518 #define ALT_SPIS_IMR_RXOIM_LSB 3
2520 #define ALT_SPIS_IMR_RXOIM_MSB 3
2522 #define ALT_SPIS_IMR_RXOIM_WIDTH 1
2524 #define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
2526 #define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
2528 #define ALT_SPIS_IMR_RXOIM_RESET 0x1
2530 #define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2532 #define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2558 #define ALT_SPIS_IMR_RXFIM_E_MASKED 0x0
2564 #define ALT_SPIS_IMR_RXFIM_E_UNMASKED 0x1
2567 #define ALT_SPIS_IMR_RXFIM_LSB 4
2569 #define ALT_SPIS_IMR_RXFIM_MSB 4
2571 #define ALT_SPIS_IMR_RXFIM_WIDTH 1
2573 #define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
2575 #define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
2577 #define ALT_SPIS_IMR_RXFIM_RESET 0x1
2579 #define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2581 #define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2592 #define ALT_SPIS_IMR_RSVD_MSTIM_LSB 5
2594 #define ALT_SPIS_IMR_RSVD_MSTIM_MSB 5
2596 #define ALT_SPIS_IMR_RSVD_MSTIM_WIDTH 1
2598 #define ALT_SPIS_IMR_RSVD_MSTIM_SET_MSK 0x00000020
2600 #define ALT_SPIS_IMR_RSVD_MSTIM_CLR_MSK 0xffffffdf
2602 #define ALT_SPIS_IMR_RSVD_MSTIM_RESET 0x0
2604 #define ALT_SPIS_IMR_RSVD_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
2606 #define ALT_SPIS_IMR_RSVD_MSTIM_SET(value) (((value) << 5) & 0x00000020)
2617 #define ALT_SPIS_IMR_RSVD_IMR_LSB 6
2619 #define ALT_SPIS_IMR_RSVD_IMR_MSB 31
2621 #define ALT_SPIS_IMR_RSVD_IMR_WIDTH 26
2623 #define ALT_SPIS_IMR_RSVD_IMR_SET_MSK 0xffffffc0
2625 #define ALT_SPIS_IMR_RSVD_IMR_CLR_MSK 0x0000003f
2627 #define ALT_SPIS_IMR_RSVD_IMR_RESET 0x0
2629 #define ALT_SPIS_IMR_RSVD_IMR_GET(value) (((value) & 0xffffffc0) >> 6)
2631 #define ALT_SPIS_IMR_RSVD_IMR_SET(value) (((value) << 6) & 0xffffffc0)
2633 #ifndef __ASSEMBLY__
2645 struct ALT_SPIS_IMR_s
2647 volatile uint32_t TXEIM : 1;
2648 volatile uint32_t TXOIM : 1;
2649 volatile uint32_t RXUIM : 1;
2650 volatile uint32_t RXOIM : 1;
2651 volatile uint32_t RXFIM : 1;
2652 const volatile uint32_t RSVD_MSTIM : 1;
2653 const volatile uint32_t RSVD_IMR : 26;
2657 typedef struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t;
2661 #define ALT_SPIS_IMR_RESET 0x0000001f
2663 #define ALT_SPIS_IMR_OFST 0x2c
2665 #define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
2709 #define ALT_SPIS_ISR_TXEIS_E_INACTIVE 0x0
2715 #define ALT_SPIS_ISR_TXEIS_E_ACTIVE 0x1
2718 #define ALT_SPIS_ISR_TXEIS_LSB 0
2720 #define ALT_SPIS_ISR_TXEIS_MSB 0
2722 #define ALT_SPIS_ISR_TXEIS_WIDTH 1
2724 #define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
2726 #define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
2728 #define ALT_SPIS_ISR_TXEIS_RESET 0x0
2730 #define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2732 #define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2758 #define ALT_SPIS_ISR_TXOIS_E_INACTIVE 0x0
2764 #define ALT_SPIS_ISR_TXOIS_E_ACTIVE 0x1
2767 #define ALT_SPIS_ISR_TXOIS_LSB 1
2769 #define ALT_SPIS_ISR_TXOIS_MSB 1
2771 #define ALT_SPIS_ISR_TXOIS_WIDTH 1
2773 #define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
2775 #define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
2777 #define ALT_SPIS_ISR_TXOIS_RESET 0x0
2779 #define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2781 #define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2807 #define ALT_SPIS_ISR_RXUIS_E_INACTIVE 0x0
2813 #define ALT_SPIS_ISR_RXUIS_E_ACTIVE 0x1
2816 #define ALT_SPIS_ISR_RXUIS_LSB 2
2818 #define ALT_SPIS_ISR_RXUIS_MSB 2
2820 #define ALT_SPIS_ISR_RXUIS_WIDTH 1
2822 #define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
2824 #define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
2826 #define ALT_SPIS_ISR_RXUIS_RESET 0x0
2828 #define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2830 #define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2856 #define ALT_SPIS_ISR_RXOIS_E_INACTIVE 0x0
2862 #define ALT_SPIS_ISR_RXOIS_E_ACTIVE 0x1
2865 #define ALT_SPIS_ISR_RXOIS_LSB 3
2867 #define ALT_SPIS_ISR_RXOIS_MSB 3
2869 #define ALT_SPIS_ISR_RXOIS_WIDTH 1
2871 #define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
2873 #define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
2875 #define ALT_SPIS_ISR_RXOIS_RESET 0x0
2877 #define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2879 #define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2905 #define ALT_SPIS_ISR_RXFIS_E_INACTIVE 0x0
2911 #define ALT_SPIS_ISR_RXFIS_E_ACTIVE 0x1
2914 #define ALT_SPIS_ISR_RXFIS_LSB 4
2916 #define ALT_SPIS_ISR_RXFIS_MSB 4
2918 #define ALT_SPIS_ISR_RXFIS_WIDTH 1
2920 #define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
2922 #define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
2924 #define ALT_SPIS_ISR_RXFIS_RESET 0x0
2926 #define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2928 #define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2939 #define ALT_SPIS_ISR_RSVD_MSTIS_LSB 5
2941 #define ALT_SPIS_ISR_RSVD_MSTIS_MSB 5
2943 #define ALT_SPIS_ISR_RSVD_MSTIS_WIDTH 1
2945 #define ALT_SPIS_ISR_RSVD_MSTIS_SET_MSK 0x00000020
2947 #define ALT_SPIS_ISR_RSVD_MSTIS_CLR_MSK 0xffffffdf
2949 #define ALT_SPIS_ISR_RSVD_MSTIS_RESET 0x0
2951 #define ALT_SPIS_ISR_RSVD_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2953 #define ALT_SPIS_ISR_RSVD_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2964 #define ALT_SPIS_ISR_RSVD_ISR_LSB 6
2966 #define ALT_SPIS_ISR_RSVD_ISR_MSB 31
2968 #define ALT_SPIS_ISR_RSVD_ISR_WIDTH 26
2970 #define ALT_SPIS_ISR_RSVD_ISR_SET_MSK 0xffffffc0
2972 #define ALT_SPIS_ISR_RSVD_ISR_CLR_MSK 0x0000003f
2974 #define ALT_SPIS_ISR_RSVD_ISR_RESET 0x0
2976 #define ALT_SPIS_ISR_RSVD_ISR_GET(value) (((value) & 0xffffffc0) >> 6)
2978 #define ALT_SPIS_ISR_RSVD_ISR_SET(value) (((value) << 6) & 0xffffffc0)
2980 #ifndef __ASSEMBLY__
2992 struct ALT_SPIS_ISR_s
2994 const volatile uint32_t TXEIS : 1;
2995 const volatile uint32_t TXOIS : 1;
2996 const volatile uint32_t RXUIS : 1;
2997 const volatile uint32_t RXOIS : 1;
2998 const volatile uint32_t RXFIS : 1;
2999 const volatile uint32_t RSVD_MSTIS : 1;
3000 const volatile uint32_t RSVD_ISR : 26;
3004 typedef struct ALT_SPIS_ISR_s ALT_SPIS_ISR_t;
3008 #define ALT_SPIS_ISR_RESET 0x00000000
3010 #define ALT_SPIS_ISR_OFST 0x30
3012 #define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
3056 #define ALT_SPIS_RISR_TXEIR_E_INACTIVE 0x0
3062 #define ALT_SPIS_RISR_TXEIR_E_ACTIVE 0x1
3065 #define ALT_SPIS_RISR_TXEIR_LSB 0
3067 #define ALT_SPIS_RISR_TXEIR_MSB 0
3069 #define ALT_SPIS_RISR_TXEIR_WIDTH 1
3071 #define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
3073 #define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
3075 #define ALT_SPIS_RISR_TXEIR_RESET 0x0
3077 #define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
3079 #define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
3105 #define ALT_SPIS_RISR_TXOIR_E_INACTIVE 0x0
3111 #define ALT_SPIS_RISR_TXOIR_E_ACTIVE 0x1
3114 #define ALT_SPIS_RISR_TXOIR_LSB 1
3116 #define ALT_SPIS_RISR_TXOIR_MSB 1
3118 #define ALT_SPIS_RISR_TXOIR_WIDTH 1
3120 #define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
3122 #define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
3124 #define ALT_SPIS_RISR_TXOIR_RESET 0x0
3126 #define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
3128 #define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
3154 #define ALT_SPIS_RISR_RXUIR_E_INACTIVE 0x0
3160 #define ALT_SPIS_RISR_RXUIR_E_ACTIVE 0x1
3163 #define ALT_SPIS_RISR_RXUIR_LSB 2
3165 #define ALT_SPIS_RISR_RXUIR_MSB 2
3167 #define ALT_SPIS_RISR_RXUIR_WIDTH 1
3169 #define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
3171 #define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
3173 #define ALT_SPIS_RISR_RXUIR_RESET 0x0
3175 #define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
3177 #define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
3203 #define ALT_SPIS_RISR_RXOIR_E_INACTIVE 0x0
3209 #define ALT_SPIS_RISR_RXOIR_E_ACTIVE 0x1
3212 #define ALT_SPIS_RISR_RXOIR_LSB 3
3214 #define ALT_SPIS_RISR_RXOIR_MSB 3
3216 #define ALT_SPIS_RISR_RXOIR_WIDTH 1
3218 #define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
3220 #define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
3222 #define ALT_SPIS_RISR_RXOIR_RESET 0x0
3224 #define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
3226 #define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
3252 #define ALT_SPIS_RISR_RXFIR_E_INACTIVE 0x0
3258 #define ALT_SPIS_RISR_RXFIR_E_ACTIVE 0x1
3261 #define ALT_SPIS_RISR_RXFIR_LSB 4
3263 #define ALT_SPIS_RISR_RXFIR_MSB 4
3265 #define ALT_SPIS_RISR_RXFIR_WIDTH 1
3267 #define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
3269 #define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
3271 #define ALT_SPIS_RISR_RXFIR_RESET 0x0
3273 #define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
3275 #define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
3286 #define ALT_SPIS_RISR_RSVD_MSTIR_LSB 5
3288 #define ALT_SPIS_RISR_RSVD_MSTIR_MSB 5
3290 #define ALT_SPIS_RISR_RSVD_MSTIR_WIDTH 1
3292 #define ALT_SPIS_RISR_RSVD_MSTIR_SET_MSK 0x00000020
3294 #define ALT_SPIS_RISR_RSVD_MSTIR_CLR_MSK 0xffffffdf
3296 #define ALT_SPIS_RISR_RSVD_MSTIR_RESET 0x0
3298 #define ALT_SPIS_RISR_RSVD_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
3300 #define ALT_SPIS_RISR_RSVD_MSTIR_SET(value) (((value) << 5) & 0x00000020)
3311 #define ALT_SPIS_RISR_RSVD_RISR_LSB 6
3313 #define ALT_SPIS_RISR_RSVD_RISR_MSB 31
3315 #define ALT_SPIS_RISR_RSVD_RISR_WIDTH 26
3317 #define ALT_SPIS_RISR_RSVD_RISR_SET_MSK 0xffffffc0
3319 #define ALT_SPIS_RISR_RSVD_RISR_CLR_MSK 0x0000003f
3321 #define ALT_SPIS_RISR_RSVD_RISR_RESET 0x0
3323 #define ALT_SPIS_RISR_RSVD_RISR_GET(value) (((value) & 0xffffffc0) >> 6)
3325 #define ALT_SPIS_RISR_RSVD_RISR_SET(value) (((value) << 6) & 0xffffffc0)
3327 #ifndef __ASSEMBLY__
3339 struct ALT_SPIS_RISR_s
3341 const volatile uint32_t TXEIR : 1;
3342 const volatile uint32_t TXOIR : 1;
3343 const volatile uint32_t RXUIR : 1;
3344 const volatile uint32_t RXOIR : 1;
3345 const volatile uint32_t RXFIR : 1;
3346 const volatile uint32_t RSVD_MSTIR : 1;
3347 const volatile uint32_t RSVD_RISR : 26;
3351 typedef struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t;
3355 #define ALT_SPIS_RISR_RESET 0x00000000
3357 #define ALT_SPIS_RISR_OFST 0x34
3359 #define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
3387 #define ALT_SPIS_TXOICR_TXOICR_LSB 0
3389 #define ALT_SPIS_TXOICR_TXOICR_MSB 0
3391 #define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
3393 #define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
3395 #define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3397 #define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
3399 #define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3401 #define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3412 #define ALT_SPIS_TXOICR_RSVD_TXOICR_LSB 1
3414 #define ALT_SPIS_TXOICR_RSVD_TXOICR_MSB 31
3416 #define ALT_SPIS_TXOICR_RSVD_TXOICR_WIDTH 31
3418 #define ALT_SPIS_TXOICR_RSVD_TXOICR_SET_MSK 0xfffffffe
3420 #define ALT_SPIS_TXOICR_RSVD_TXOICR_CLR_MSK 0x00000001
3422 #define ALT_SPIS_TXOICR_RSVD_TXOICR_RESET 0x0
3424 #define ALT_SPIS_TXOICR_RSVD_TXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3426 #define ALT_SPIS_TXOICR_RSVD_TXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3428 #ifndef __ASSEMBLY__
3440 struct ALT_SPIS_TXOICR_s
3442 const volatile uint32_t TXOICR : 1;
3443 const volatile uint32_t RSVD_TXOICR : 31;
3447 typedef struct ALT_SPIS_TXOICR_s ALT_SPIS_TXOICR_t;
3451 #define ALT_SPIS_TXOICR_RESET 0x00000000
3453 #define ALT_SPIS_TXOICR_OFST 0x38
3455 #define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
3483 #define ALT_SPIS_RXOICR_RXOICR_LSB 0
3485 #define ALT_SPIS_RXOICR_RXOICR_MSB 0
3487 #define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
3489 #define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
3491 #define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3493 #define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
3495 #define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3497 #define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3508 #define ALT_SPIS_RXOICR_RSVD_RXOICR_LSB 1
3510 #define ALT_SPIS_RXOICR_RSVD_RXOICR_MSB 31
3512 #define ALT_SPIS_RXOICR_RSVD_RXOICR_WIDTH 31
3514 #define ALT_SPIS_RXOICR_RSVD_RXOICR_SET_MSK 0xfffffffe
3516 #define ALT_SPIS_RXOICR_RSVD_RXOICR_CLR_MSK 0x00000001
3518 #define ALT_SPIS_RXOICR_RSVD_RXOICR_RESET 0x0
3520 #define ALT_SPIS_RXOICR_RSVD_RXOICR_GET(value) (((value) & 0xfffffffe) >> 1)
3522 #define ALT_SPIS_RXOICR_RSVD_RXOICR_SET(value) (((value) << 1) & 0xfffffffe)
3524 #ifndef __ASSEMBLY__
3536 struct ALT_SPIS_RXOICR_s
3538 const volatile uint32_t RXOICR : 1;
3539 const volatile uint32_t RSVD_RXOICR : 31;
3543 typedef struct ALT_SPIS_RXOICR_s ALT_SPIS_RXOICR_t;
3547 #define ALT_SPIS_RXOICR_RESET 0x00000000
3549 #define ALT_SPIS_RXOICR_OFST 0x3c
3551 #define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
3579 #define ALT_SPIS_RXUICR_RXUICR_LSB 0
3581 #define ALT_SPIS_RXUICR_RXUICR_MSB 0
3583 #define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
3585 #define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
3587 #define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
3589 #define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
3591 #define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
3593 #define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
3604 #define ALT_SPIS_RXUICR_RSVD_RXUICR_LSB 1
3606 #define ALT_SPIS_RXUICR_RSVD_RXUICR_MSB 31
3608 #define ALT_SPIS_RXUICR_RSVD_RXUICR_WIDTH 31
3610 #define ALT_SPIS_RXUICR_RSVD_RXUICR_SET_MSK 0xfffffffe
3612 #define ALT_SPIS_RXUICR_RSVD_RXUICR_CLR_MSK 0x00000001
3614 #define ALT_SPIS_RXUICR_RSVD_RXUICR_RESET 0x0
3616 #define ALT_SPIS_RXUICR_RSVD_RXUICR_GET(value) (((value) & 0xfffffffe) >> 1)
3618 #define ALT_SPIS_RXUICR_RSVD_RXUICR_SET(value) (((value) << 1) & 0xfffffffe)
3620 #ifndef __ASSEMBLY__
3632 struct ALT_SPIS_RXUICR_s
3634 const volatile uint32_t RXUICR : 1;
3635 const volatile uint32_t RSVD_RXUICR : 31;
3639 typedef struct ALT_SPIS_RXUICR_s ALT_SPIS_RXUICR_t;
3643 #define ALT_SPIS_RXUICR_RESET 0x00000000
3645 #define ALT_SPIS_RXUICR_OFST 0x40
3647 #define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
3675 #define ALT_SPIS_MSTICR_MSTICR_LSB 0
3677 #define ALT_SPIS_MSTICR_MSTICR_MSB 0
3679 #define ALT_SPIS_MSTICR_MSTICR_WIDTH 1
3681 #define ALT_SPIS_MSTICR_MSTICR_SET_MSK 0x00000001
3683 #define ALT_SPIS_MSTICR_MSTICR_CLR_MSK 0xfffffffe
3685 #define ALT_SPIS_MSTICR_MSTICR_RESET 0x0
3687 #define ALT_SPIS_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
3689 #define ALT_SPIS_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
3700 #define ALT_SPIS_MSTICR_RSVD_MSTICR_LSB 1
3702 #define ALT_SPIS_MSTICR_RSVD_MSTICR_MSB 31
3704 #define ALT_SPIS_MSTICR_RSVD_MSTICR_WIDTH 31
3706 #define ALT_SPIS_MSTICR_RSVD_MSTICR_SET_MSK 0xfffffffe
3708 #define ALT_SPIS_MSTICR_RSVD_MSTICR_CLR_MSK 0x00000001
3710 #define ALT_SPIS_MSTICR_RSVD_MSTICR_RESET 0x0
3712 #define ALT_SPIS_MSTICR_RSVD_MSTICR_GET(value) (((value) & 0xfffffffe) >> 1)
3714 #define ALT_SPIS_MSTICR_RSVD_MSTICR_SET(value) (((value) << 1) & 0xfffffffe)
3716 #ifndef __ASSEMBLY__
3728 struct ALT_SPIS_MSTICR_s
3730 const volatile uint32_t MSTICR : 1;
3731 const volatile uint32_t RSVD_MSTICR : 31;
3735 typedef struct ALT_SPIS_MSTICR_s ALT_SPIS_MSTICR_t;
3739 #define ALT_SPIS_MSTICR_RESET 0x00000000
3741 #define ALT_SPIS_MSTICR_OFST 0x44
3743 #define ALT_SPIS_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MSTICR_OFST))
3773 #define ALT_SPIS_ICR_ICR_LSB 0
3775 #define ALT_SPIS_ICR_ICR_MSB 0
3777 #define ALT_SPIS_ICR_ICR_WIDTH 1
3779 #define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
3781 #define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
3783 #define ALT_SPIS_ICR_ICR_RESET 0x0
3785 #define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
3787 #define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
3798 #define ALT_SPIS_ICR_RSVD_ICR_LSB 1
3800 #define ALT_SPIS_ICR_RSVD_ICR_MSB 31
3802 #define ALT_SPIS_ICR_RSVD_ICR_WIDTH 31
3804 #define ALT_SPIS_ICR_RSVD_ICR_SET_MSK 0xfffffffe
3806 #define ALT_SPIS_ICR_RSVD_ICR_CLR_MSK 0x00000001
3808 #define ALT_SPIS_ICR_RSVD_ICR_RESET 0x0
3810 #define ALT_SPIS_ICR_RSVD_ICR_GET(value) (((value) & 0xfffffffe) >> 1)
3812 #define ALT_SPIS_ICR_RSVD_ICR_SET(value) (((value) << 1) & 0xfffffffe)
3814 #ifndef __ASSEMBLY__
3826 struct ALT_SPIS_ICR_s
3828 const volatile uint32_t ICR : 1;
3829 const volatile uint32_t RSVD_ICR : 31;
3833 typedef struct ALT_SPIS_ICR_s ALT_SPIS_ICR_t;
3837 #define ALT_SPIS_ICR_RESET 0x00000000
3839 #define ALT_SPIS_ICR_OFST 0x48
3841 #define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
3895 #define ALT_SPIS_DMACR_RDMAE_E_DISABLE 0x0
3901 #define ALT_SPIS_DMACR_RDMAE_E_ENABLED 0x1
3904 #define ALT_SPIS_DMACR_RDMAE_LSB 0
3906 #define ALT_SPIS_DMACR_RDMAE_MSB 0
3908 #define ALT_SPIS_DMACR_RDMAE_WIDTH 1
3910 #define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
3912 #define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
3914 #define ALT_SPIS_DMACR_RDMAE_RESET 0x0
3916 #define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3918 #define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3946 #define ALT_SPIS_DMACR_TDMAE_E_DISABLE 0x0
3952 #define ALT_SPIS_DMACR_TDMAE_E_ENABLED 0x1
3955 #define ALT_SPIS_DMACR_TDMAE_LSB 1
3957 #define ALT_SPIS_DMACR_TDMAE_MSB 1
3959 #define ALT_SPIS_DMACR_TDMAE_WIDTH 1
3961 #define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
3963 #define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
3965 #define ALT_SPIS_DMACR_TDMAE_RESET 0x0
3967 #define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3969 #define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3980 #define ALT_SPIS_DMACR_RSVD_DMACR_LSB 2
3982 #define ALT_SPIS_DMACR_RSVD_DMACR_MSB 31
3984 #define ALT_SPIS_DMACR_RSVD_DMACR_WIDTH 30
3986 #define ALT_SPIS_DMACR_RSVD_DMACR_SET_MSK 0xfffffffc
3988 #define ALT_SPIS_DMACR_RSVD_DMACR_CLR_MSK 0x00000003
3990 #define ALT_SPIS_DMACR_RSVD_DMACR_RESET 0x0
3992 #define ALT_SPIS_DMACR_RSVD_DMACR_GET(value) (((value) & 0xfffffffc) >> 2)
3994 #define ALT_SPIS_DMACR_RSVD_DMACR_SET(value) (((value) << 2) & 0xfffffffc)
3996 #ifndef __ASSEMBLY__
4008 struct ALT_SPIS_DMACR_s
4010 volatile uint32_t RDMAE : 1;
4011 volatile uint32_t TDMAE : 1;
4012 const volatile uint32_t RSVD_DMACR : 30;
4016 typedef struct ALT_SPIS_DMACR_s ALT_SPIS_DMACR_t;
4020 #define ALT_SPIS_DMACR_RESET 0x00000000
4022 #define ALT_SPIS_DMACR_OFST 0x4c
4024 #define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
4066 #define ALT_SPIS_DMATDLR_DMATDL_LSB 0
4068 #define ALT_SPIS_DMATDLR_DMATDL_MSB 7
4070 #define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
4072 #define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
4074 #define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
4076 #define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
4078 #define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
4080 #define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
4091 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_LSB 8
4093 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_MSB 31
4095 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_WIDTH 24
4097 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_SET_MSK 0xffffff00
4099 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_CLR_MSK 0x000000ff
4101 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_RESET 0x0
4103 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_GET(value) (((value) & 0xffffff00) >> 8)
4105 #define ALT_SPIS_DMATDLR_RSVD_DMATDLR_SET(value) (((value) << 8) & 0xffffff00)
4107 #ifndef __ASSEMBLY__
4119 struct ALT_SPIS_DMATDLR_s
4121 volatile uint32_t DMATDL : 8;
4122 const volatile uint32_t RSVD_DMATDLR : 24;
4126 typedef struct ALT_SPIS_DMATDLR_s ALT_SPIS_DMATDLR_t;
4130 #define ALT_SPIS_DMATDLR_RESET 0x00000000
4132 #define ALT_SPIS_DMATDLR_OFST 0x50
4134 #define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
4174 #define ALT_SPIS_DMARDLR_DMARDL_LSB 0
4176 #define ALT_SPIS_DMARDLR_DMARDL_MSB 7
4178 #define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
4180 #define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
4182 #define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
4184 #define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
4186 #define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
4188 #define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
4199 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_LSB 8
4201 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_MSB 31
4203 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_WIDTH 24
4205 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_SET_MSK 0xffffff00
4207 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_CLR_MSK 0x000000ff
4209 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_RESET 0x0
4211 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_GET(value) (((value) & 0xffffff00) >> 8)
4213 #define ALT_SPIS_DMARDLR_RSVD_DMARDLR_SET(value) (((value) << 8) & 0xffffff00)
4215 #ifndef __ASSEMBLY__
4227 struct ALT_SPIS_DMARDLR_s
4229 volatile uint32_t DMARDL : 8;
4230 const volatile uint32_t RSVD_DMARDLR : 24;
4234 typedef struct ALT_SPIS_DMARDLR_s ALT_SPIS_DMARDLR_t;
4238 #define ALT_SPIS_DMARDLR_RESET 0x00000000
4240 #define ALT_SPIS_DMARDLR_OFST 0x54
4242 #define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
4270 #define ALT_SPIS_IDR_IDCODE_LSB 0
4272 #define ALT_SPIS_IDR_IDCODE_MSB 31
4274 #define ALT_SPIS_IDR_IDCODE_WIDTH 32
4276 #define ALT_SPIS_IDR_IDCODE_SET_MSK 0xffffffff
4278 #define ALT_SPIS_IDR_IDCODE_CLR_MSK 0x00000000
4280 #define ALT_SPIS_IDR_IDCODE_RESET 0x5510005
4282 #define ALT_SPIS_IDR_IDCODE_GET(value) (((value) & 0xffffffff) >> 0)
4284 #define ALT_SPIS_IDR_IDCODE_SET(value) (((value) << 0) & 0xffffffff)
4286 #ifndef __ASSEMBLY__
4298 struct ALT_SPIS_IDR_s
4300 const volatile uint32_t IDCODE : 32;
4304 typedef struct ALT_SPIS_IDR_s ALT_SPIS_IDR_t;
4308 #define ALT_SPIS_IDR_RESET 0x05510005
4310 #define ALT_SPIS_IDR_OFST 0x58
4312 #define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
4337 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0
4339 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31
4341 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_WIDTH 32
4343 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_SET_MSK 0xffffffff
4345 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_CLR_MSK 0x00000000
4347 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430302a
4349 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_GET(value) (((value) & 0xffffffff) >> 0)
4351 #define ALT_SPIS_SSI_VERSION_ID_SSI_COMP_VERSION_SET(value) (((value) << 0) & 0xffffffff)
4353 #ifndef __ASSEMBLY__
4365 struct ALT_SPIS_SSI_VERSION_ID_s
4367 const volatile uint32_t SSI_COMP_VERSION : 32;
4371 typedef struct ALT_SPIS_SSI_VERSION_ID_s ALT_SPIS_SSI_VERSION_ID_t;
4375 #define ALT_SPIS_SSI_VERSION_ID_RESET 0x3430302a
4377 #define ALT_SPIS_SSI_VERSION_ID_OFST 0x5c
4379 #define ALT_SPIS_SSI_VERSION_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SSI_VERSION_ID_OFST))
4426 #define ALT_SPIS_DR0_DR0_LSB 0
4428 #define ALT_SPIS_DR0_DR0_MSB 31
4430 #define ALT_SPIS_DR0_DR0_WIDTH 32
4432 #define ALT_SPIS_DR0_DR0_SET_MSK 0xffffffff
4434 #define ALT_SPIS_DR0_DR0_CLR_MSK 0x00000000
4436 #define ALT_SPIS_DR0_DR0_RESET 0x0
4438 #define ALT_SPIS_DR0_DR0_GET(value) (((value) & 0xffffffff) >> 0)
4440 #define ALT_SPIS_DR0_DR0_SET(value) (((value) << 0) & 0xffffffff)
4442 #ifndef __ASSEMBLY__
4454 struct ALT_SPIS_DR0_s
4456 volatile uint32_t dr0 : 32;
4460 typedef struct ALT_SPIS_DR0_s ALT_SPIS_DR0_t;
4464 #define ALT_SPIS_DR0_RESET 0x00000000
4466 #define ALT_SPIS_DR0_OFST 0x60
4468 #define ALT_SPIS_DR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR0_OFST))
4515 #define ALT_SPIS_DR1_DR1_LSB 0
4517 #define ALT_SPIS_DR1_DR1_MSB 31
4519 #define ALT_SPIS_DR1_DR1_WIDTH 32
4521 #define ALT_SPIS_DR1_DR1_SET_MSK 0xffffffff
4523 #define ALT_SPIS_DR1_DR1_CLR_MSK 0x00000000
4525 #define ALT_SPIS_DR1_DR1_RESET 0x0
4527 #define ALT_SPIS_DR1_DR1_GET(value) (((value) & 0xffffffff) >> 0)
4529 #define ALT_SPIS_DR1_DR1_SET(value) (((value) << 0) & 0xffffffff)
4531 #ifndef __ASSEMBLY__
4543 struct ALT_SPIS_DR1_s
4545 volatile uint32_t dr1 : 32;
4549 typedef struct ALT_SPIS_DR1_s ALT_SPIS_DR1_t;
4553 #define ALT_SPIS_DR1_RESET 0x00000000
4555 #define ALT_SPIS_DR1_OFST 0x64
4557 #define ALT_SPIS_DR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR1_OFST))
4604 #define ALT_SPIS_DR2_DR2_LSB 0
4606 #define ALT_SPIS_DR2_DR2_MSB 31
4608 #define ALT_SPIS_DR2_DR2_WIDTH 32
4610 #define ALT_SPIS_DR2_DR2_SET_MSK 0xffffffff
4612 #define ALT_SPIS_DR2_DR2_CLR_MSK 0x00000000
4614 #define ALT_SPIS_DR2_DR2_RESET 0x0
4616 #define ALT_SPIS_DR2_DR2_GET(value) (((value) & 0xffffffff) >> 0)
4618 #define ALT_SPIS_DR2_DR2_SET(value) (((value) << 0) & 0xffffffff)
4620 #ifndef __ASSEMBLY__
4632 struct ALT_SPIS_DR2_s
4634 volatile uint32_t dr2 : 32;
4638 typedef struct ALT_SPIS_DR2_s ALT_SPIS_DR2_t;
4642 #define ALT_SPIS_DR2_RESET 0x00000000
4644 #define ALT_SPIS_DR2_OFST 0x68
4646 #define ALT_SPIS_DR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR2_OFST))
4693 #define ALT_SPIS_DR3_DR3_LSB 0
4695 #define ALT_SPIS_DR3_DR3_MSB 31
4697 #define ALT_SPIS_DR3_DR3_WIDTH 32
4699 #define ALT_SPIS_DR3_DR3_SET_MSK 0xffffffff
4701 #define ALT_SPIS_DR3_DR3_CLR_MSK 0x00000000
4703 #define ALT_SPIS_DR3_DR3_RESET 0x0
4705 #define ALT_SPIS_DR3_DR3_GET(value) (((value) & 0xffffffff) >> 0)
4707 #define ALT_SPIS_DR3_DR3_SET(value) (((value) << 0) & 0xffffffff)
4709 #ifndef __ASSEMBLY__
4721 struct ALT_SPIS_DR3_s
4723 volatile uint32_t dr3 : 32;
4727 typedef struct ALT_SPIS_DR3_s ALT_SPIS_DR3_t;
4731 #define ALT_SPIS_DR3_RESET 0x00000000
4733 #define ALT_SPIS_DR3_OFST 0x6c
4735 #define ALT_SPIS_DR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR3_OFST))
4782 #define ALT_SPIS_DR4_DR4_LSB 0
4784 #define ALT_SPIS_DR4_DR4_MSB 31
4786 #define ALT_SPIS_DR4_DR4_WIDTH 32
4788 #define ALT_SPIS_DR4_DR4_SET_MSK 0xffffffff
4790 #define ALT_SPIS_DR4_DR4_CLR_MSK 0x00000000
4792 #define ALT_SPIS_DR4_DR4_RESET 0x0
4794 #define ALT_SPIS_DR4_DR4_GET(value) (((value) & 0xffffffff) >> 0)
4796 #define ALT_SPIS_DR4_DR4_SET(value) (((value) << 0) & 0xffffffff)
4798 #ifndef __ASSEMBLY__
4810 struct ALT_SPIS_DR4_s
4812 volatile uint32_t dr4 : 32;
4816 typedef struct ALT_SPIS_DR4_s ALT_SPIS_DR4_t;
4820 #define ALT_SPIS_DR4_RESET 0x00000000
4822 #define ALT_SPIS_DR4_OFST 0x70
4824 #define ALT_SPIS_DR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR4_OFST))
4871 #define ALT_SPIS_DR5_DR5_LSB 0
4873 #define ALT_SPIS_DR5_DR5_MSB 31
4875 #define ALT_SPIS_DR5_DR5_WIDTH 32
4877 #define ALT_SPIS_DR5_DR5_SET_MSK 0xffffffff
4879 #define ALT_SPIS_DR5_DR5_CLR_MSK 0x00000000
4881 #define ALT_SPIS_DR5_DR5_RESET 0x0
4883 #define ALT_SPIS_DR5_DR5_GET(value) (((value) & 0xffffffff) >> 0)
4885 #define ALT_SPIS_DR5_DR5_SET(value) (((value) << 0) & 0xffffffff)
4887 #ifndef __ASSEMBLY__
4899 struct ALT_SPIS_DR5_s
4901 volatile uint32_t dr5 : 32;
4905 typedef struct ALT_SPIS_DR5_s ALT_SPIS_DR5_t;
4909 #define ALT_SPIS_DR5_RESET 0x00000000
4911 #define ALT_SPIS_DR5_OFST 0x74
4913 #define ALT_SPIS_DR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR5_OFST))
4960 #define ALT_SPIS_DR6_DR6_LSB 0
4962 #define ALT_SPIS_DR6_DR6_MSB 31
4964 #define ALT_SPIS_DR6_DR6_WIDTH 32
4966 #define ALT_SPIS_DR6_DR6_SET_MSK 0xffffffff
4968 #define ALT_SPIS_DR6_DR6_CLR_MSK 0x00000000
4970 #define ALT_SPIS_DR6_DR6_RESET 0x0
4972 #define ALT_SPIS_DR6_DR6_GET(value) (((value) & 0xffffffff) >> 0)
4974 #define ALT_SPIS_DR6_DR6_SET(value) (((value) << 0) & 0xffffffff)
4976 #ifndef __ASSEMBLY__
4988 struct ALT_SPIS_DR6_s
4990 volatile uint32_t dr6 : 32;
4994 typedef struct ALT_SPIS_DR6_s ALT_SPIS_DR6_t;
4998 #define ALT_SPIS_DR6_RESET 0x00000000
5000 #define ALT_SPIS_DR6_OFST 0x78
5002 #define ALT_SPIS_DR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR6_OFST))
5049 #define ALT_SPIS_DR7_DR7_LSB 0
5051 #define ALT_SPIS_DR7_DR7_MSB 31
5053 #define ALT_SPIS_DR7_DR7_WIDTH 32
5055 #define ALT_SPIS_DR7_DR7_SET_MSK 0xffffffff
5057 #define ALT_SPIS_DR7_DR7_CLR_MSK 0x00000000
5059 #define ALT_SPIS_DR7_DR7_RESET 0x0
5061 #define ALT_SPIS_DR7_DR7_GET(value) (((value) & 0xffffffff) >> 0)
5063 #define ALT_SPIS_DR7_DR7_SET(value) (((value) << 0) & 0xffffffff)
5065 #ifndef __ASSEMBLY__
5077 struct ALT_SPIS_DR7_s
5079 volatile uint32_t dr7 : 32;
5083 typedef struct ALT_SPIS_DR7_s ALT_SPIS_DR7_t;
5087 #define ALT_SPIS_DR7_RESET 0x00000000
5089 #define ALT_SPIS_DR7_OFST 0x7c
5091 #define ALT_SPIS_DR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR7_OFST))
5138 #define ALT_SPIS_DR8_DR8_LSB 0
5140 #define ALT_SPIS_DR8_DR8_MSB 31
5142 #define ALT_SPIS_DR8_DR8_WIDTH 32
5144 #define ALT_SPIS_DR8_DR8_SET_MSK 0xffffffff
5146 #define ALT_SPIS_DR8_DR8_CLR_MSK 0x00000000
5148 #define ALT_SPIS_DR8_DR8_RESET 0x0
5150 #define ALT_SPIS_DR8_DR8_GET(value) (((value) & 0xffffffff) >> 0)
5152 #define ALT_SPIS_DR8_DR8_SET(value) (((value) << 0) & 0xffffffff)
5154 #ifndef __ASSEMBLY__
5166 struct ALT_SPIS_DR8_s
5168 volatile uint32_t dr8 : 32;
5172 typedef struct ALT_SPIS_DR8_s ALT_SPIS_DR8_t;
5176 #define ALT_SPIS_DR8_RESET 0x00000000
5178 #define ALT_SPIS_DR8_OFST 0x80
5180 #define ALT_SPIS_DR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR8_OFST))
5227 #define ALT_SPIS_DR9_DR9_LSB 0
5229 #define ALT_SPIS_DR9_DR9_MSB 31
5231 #define ALT_SPIS_DR9_DR9_WIDTH 32
5233 #define ALT_SPIS_DR9_DR9_SET_MSK 0xffffffff
5235 #define ALT_SPIS_DR9_DR9_CLR_MSK 0x00000000
5237 #define ALT_SPIS_DR9_DR9_RESET 0x0
5239 #define ALT_SPIS_DR9_DR9_GET(value) (((value) & 0xffffffff) >> 0)
5241 #define ALT_SPIS_DR9_DR9_SET(value) (((value) << 0) & 0xffffffff)
5243 #ifndef __ASSEMBLY__
5255 struct ALT_SPIS_DR9_s
5257 volatile uint32_t dr9 : 32;
5261 typedef struct ALT_SPIS_DR9_s ALT_SPIS_DR9_t;
5265 #define ALT_SPIS_DR9_RESET 0x00000000
5267 #define ALT_SPIS_DR9_OFST 0x84
5269 #define ALT_SPIS_DR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR9_OFST))
5316 #define ALT_SPIS_DR10_DR10_LSB 0
5318 #define ALT_SPIS_DR10_DR10_MSB 31
5320 #define ALT_SPIS_DR10_DR10_WIDTH 32
5322 #define ALT_SPIS_DR10_DR10_SET_MSK 0xffffffff
5324 #define ALT_SPIS_DR10_DR10_CLR_MSK 0x00000000
5326 #define ALT_SPIS_DR10_DR10_RESET 0x0
5328 #define ALT_SPIS_DR10_DR10_GET(value) (((value) & 0xffffffff) >> 0)
5330 #define ALT_SPIS_DR10_DR10_SET(value) (((value) << 0) & 0xffffffff)
5332 #ifndef __ASSEMBLY__
5344 struct ALT_SPIS_DR10_s
5346 volatile uint32_t dr10 : 32;
5350 typedef struct ALT_SPIS_DR10_s ALT_SPIS_DR10_t;
5354 #define ALT_SPIS_DR10_RESET 0x00000000
5356 #define ALT_SPIS_DR10_OFST 0x88
5358 #define ALT_SPIS_DR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR10_OFST))
5405 #define ALT_SPIS_DR11_DR11_LSB 0
5407 #define ALT_SPIS_DR11_DR11_MSB 31
5409 #define ALT_SPIS_DR11_DR11_WIDTH 32
5411 #define ALT_SPIS_DR11_DR11_SET_MSK 0xffffffff
5413 #define ALT_SPIS_DR11_DR11_CLR_MSK 0x00000000
5415 #define ALT_SPIS_DR11_DR11_RESET 0x0
5417 #define ALT_SPIS_DR11_DR11_GET(value) (((value) & 0xffffffff) >> 0)
5419 #define ALT_SPIS_DR11_DR11_SET(value) (((value) << 0) & 0xffffffff)
5421 #ifndef __ASSEMBLY__
5433 struct ALT_SPIS_DR11_s
5435 volatile uint32_t dr11 : 32;
5439 typedef struct ALT_SPIS_DR11_s ALT_SPIS_DR11_t;
5443 #define ALT_SPIS_DR11_RESET 0x00000000
5445 #define ALT_SPIS_DR11_OFST 0x8c
5447 #define ALT_SPIS_DR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR11_OFST))
5494 #define ALT_SPIS_DR12_DR12_LSB 0
5496 #define ALT_SPIS_DR12_DR12_MSB 31
5498 #define ALT_SPIS_DR12_DR12_WIDTH 32
5500 #define ALT_SPIS_DR12_DR12_SET_MSK 0xffffffff
5502 #define ALT_SPIS_DR12_DR12_CLR_MSK 0x00000000
5504 #define ALT_SPIS_DR12_DR12_RESET 0x0
5506 #define ALT_SPIS_DR12_DR12_GET(value) (((value) & 0xffffffff) >> 0)
5508 #define ALT_SPIS_DR12_DR12_SET(value) (((value) << 0) & 0xffffffff)
5510 #ifndef __ASSEMBLY__
5522 struct ALT_SPIS_DR12_s
5524 volatile uint32_t dr12 : 32;
5528 typedef struct ALT_SPIS_DR12_s ALT_SPIS_DR12_t;
5532 #define ALT_SPIS_DR12_RESET 0x00000000
5534 #define ALT_SPIS_DR12_OFST 0x90
5536 #define ALT_SPIS_DR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR12_OFST))
5583 #define ALT_SPIS_DR13_DR13_LSB 0
5585 #define ALT_SPIS_DR13_DR13_MSB 31
5587 #define ALT_SPIS_DR13_DR13_WIDTH 32
5589 #define ALT_SPIS_DR13_DR13_SET_MSK 0xffffffff
5591 #define ALT_SPIS_DR13_DR13_CLR_MSK 0x00000000
5593 #define ALT_SPIS_DR13_DR13_RESET 0x0
5595 #define ALT_SPIS_DR13_DR13_GET(value) (((value) & 0xffffffff) >> 0)
5597 #define ALT_SPIS_DR13_DR13_SET(value) (((value) << 0) & 0xffffffff)
5599 #ifndef __ASSEMBLY__
5611 struct ALT_SPIS_DR13_s
5613 volatile uint32_t dr13 : 32;
5617 typedef struct ALT_SPIS_DR13_s ALT_SPIS_DR13_t;
5621 #define ALT_SPIS_DR13_RESET 0x00000000
5623 #define ALT_SPIS_DR13_OFST 0x94
5625 #define ALT_SPIS_DR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR13_OFST))
5672 #define ALT_SPIS_DR14_DR14_LSB 0
5674 #define ALT_SPIS_DR14_DR14_MSB 31
5676 #define ALT_SPIS_DR14_DR14_WIDTH 32
5678 #define ALT_SPIS_DR14_DR14_SET_MSK 0xffffffff
5680 #define ALT_SPIS_DR14_DR14_CLR_MSK 0x00000000
5682 #define ALT_SPIS_DR14_DR14_RESET 0x0
5684 #define ALT_SPIS_DR14_DR14_GET(value) (((value) & 0xffffffff) >> 0)
5686 #define ALT_SPIS_DR14_DR14_SET(value) (((value) << 0) & 0xffffffff)
5688 #ifndef __ASSEMBLY__
5700 struct ALT_SPIS_DR14_s
5702 volatile uint32_t dr14 : 32;
5706 typedef struct ALT_SPIS_DR14_s ALT_SPIS_DR14_t;
5710 #define ALT_SPIS_DR14_RESET 0x00000000
5712 #define ALT_SPIS_DR14_OFST 0x98
5714 #define ALT_SPIS_DR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR14_OFST))
5761 #define ALT_SPIS_DR15_DR15_LSB 0
5763 #define ALT_SPIS_DR15_DR15_MSB 31
5765 #define ALT_SPIS_DR15_DR15_WIDTH 32
5767 #define ALT_SPIS_DR15_DR15_SET_MSK 0xffffffff
5769 #define ALT_SPIS_DR15_DR15_CLR_MSK 0x00000000
5771 #define ALT_SPIS_DR15_DR15_RESET 0x0
5773 #define ALT_SPIS_DR15_DR15_GET(value) (((value) & 0xffffffff) >> 0)
5775 #define ALT_SPIS_DR15_DR15_SET(value) (((value) << 0) & 0xffffffff)
5777 #ifndef __ASSEMBLY__
5789 struct ALT_SPIS_DR15_s
5791 volatile uint32_t dr15 : 32;
5795 typedef struct ALT_SPIS_DR15_s ALT_SPIS_DR15_t;
5799 #define ALT_SPIS_DR15_RESET 0x00000000
5801 #define ALT_SPIS_DR15_OFST 0x9c
5803 #define ALT_SPIS_DR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR15_OFST))
5850 #define ALT_SPIS_DR16_DR16_LSB 0
5852 #define ALT_SPIS_DR16_DR16_MSB 31
5854 #define ALT_SPIS_DR16_DR16_WIDTH 32
5856 #define ALT_SPIS_DR16_DR16_SET_MSK 0xffffffff
5858 #define ALT_SPIS_DR16_DR16_CLR_MSK 0x00000000
5860 #define ALT_SPIS_DR16_DR16_RESET 0x0
5862 #define ALT_SPIS_DR16_DR16_GET(value) (((value) & 0xffffffff) >> 0)
5864 #define ALT_SPIS_DR16_DR16_SET(value) (((value) << 0) & 0xffffffff)
5866 #ifndef __ASSEMBLY__
5878 struct ALT_SPIS_DR16_s
5880 volatile uint32_t dr16 : 32;
5884 typedef struct ALT_SPIS_DR16_s ALT_SPIS_DR16_t;
5888 #define ALT_SPIS_DR16_RESET 0x00000000
5890 #define ALT_SPIS_DR16_OFST 0xa0
5892 #define ALT_SPIS_DR16_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR16_OFST))
5939 #define ALT_SPIS_DR17_DR17_LSB 0
5941 #define ALT_SPIS_DR17_DR17_MSB 31
5943 #define ALT_SPIS_DR17_DR17_WIDTH 32
5945 #define ALT_SPIS_DR17_DR17_SET_MSK 0xffffffff
5947 #define ALT_SPIS_DR17_DR17_CLR_MSK 0x00000000
5949 #define ALT_SPIS_DR17_DR17_RESET 0x0
5951 #define ALT_SPIS_DR17_DR17_GET(value) (((value) & 0xffffffff) >> 0)
5953 #define ALT_SPIS_DR17_DR17_SET(value) (((value) << 0) & 0xffffffff)
5955 #ifndef __ASSEMBLY__
5967 struct ALT_SPIS_DR17_s
5969 volatile uint32_t dr17 : 32;
5973 typedef struct ALT_SPIS_DR17_s ALT_SPIS_DR17_t;
5977 #define ALT_SPIS_DR17_RESET 0x00000000
5979 #define ALT_SPIS_DR17_OFST 0xa4
5981 #define ALT_SPIS_DR17_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR17_OFST))
6028 #define ALT_SPIS_DR18_DR18_LSB 0
6030 #define ALT_SPIS_DR18_DR18_MSB 31
6032 #define ALT_SPIS_DR18_DR18_WIDTH 32
6034 #define ALT_SPIS_DR18_DR18_SET_MSK 0xffffffff
6036 #define ALT_SPIS_DR18_DR18_CLR_MSK 0x00000000
6038 #define ALT_SPIS_DR18_DR18_RESET 0x0
6040 #define ALT_SPIS_DR18_DR18_GET(value) (((value) & 0xffffffff) >> 0)
6042 #define ALT_SPIS_DR18_DR18_SET(value) (((value) << 0) & 0xffffffff)
6044 #ifndef __ASSEMBLY__
6056 struct ALT_SPIS_DR18_s
6058 volatile uint32_t dr18 : 32;
6062 typedef struct ALT_SPIS_DR18_s ALT_SPIS_DR18_t;
6066 #define ALT_SPIS_DR18_RESET 0x00000000
6068 #define ALT_SPIS_DR18_OFST 0xa8
6070 #define ALT_SPIS_DR18_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR18_OFST))
6117 #define ALT_SPIS_DR19_DR19_LSB 0
6119 #define ALT_SPIS_DR19_DR19_MSB 31
6121 #define ALT_SPIS_DR19_DR19_WIDTH 32
6123 #define ALT_SPIS_DR19_DR19_SET_MSK 0xffffffff
6125 #define ALT_SPIS_DR19_DR19_CLR_MSK 0x00000000
6127 #define ALT_SPIS_DR19_DR19_RESET 0x0
6129 #define ALT_SPIS_DR19_DR19_GET(value) (((value) & 0xffffffff) >> 0)
6131 #define ALT_SPIS_DR19_DR19_SET(value) (((value) << 0) & 0xffffffff)
6133 #ifndef __ASSEMBLY__
6145 struct ALT_SPIS_DR19_s
6147 volatile uint32_t dr19 : 32;
6151 typedef struct ALT_SPIS_DR19_s ALT_SPIS_DR19_t;
6155 #define ALT_SPIS_DR19_RESET 0x00000000
6157 #define ALT_SPIS_DR19_OFST 0xac
6159 #define ALT_SPIS_DR19_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR19_OFST))
6206 #define ALT_SPIS_DR20_DR20_LSB 0
6208 #define ALT_SPIS_DR20_DR20_MSB 31
6210 #define ALT_SPIS_DR20_DR20_WIDTH 32
6212 #define ALT_SPIS_DR20_DR20_SET_MSK 0xffffffff
6214 #define ALT_SPIS_DR20_DR20_CLR_MSK 0x00000000
6216 #define ALT_SPIS_DR20_DR20_RESET 0x0
6218 #define ALT_SPIS_DR20_DR20_GET(value) (((value) & 0xffffffff) >> 0)
6220 #define ALT_SPIS_DR20_DR20_SET(value) (((value) << 0) & 0xffffffff)
6222 #ifndef __ASSEMBLY__
6234 struct ALT_SPIS_DR20_s
6236 volatile uint32_t dr20 : 32;
6240 typedef struct ALT_SPIS_DR20_s ALT_SPIS_DR20_t;
6244 #define ALT_SPIS_DR20_RESET 0x00000000
6246 #define ALT_SPIS_DR20_OFST 0xb0
6248 #define ALT_SPIS_DR20_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR20_OFST))
6295 #define ALT_SPIS_DR21_DR21_LSB 0
6297 #define ALT_SPIS_DR21_DR21_MSB 31
6299 #define ALT_SPIS_DR21_DR21_WIDTH 32
6301 #define ALT_SPIS_DR21_DR21_SET_MSK 0xffffffff
6303 #define ALT_SPIS_DR21_DR21_CLR_MSK 0x00000000
6305 #define ALT_SPIS_DR21_DR21_RESET 0x0
6307 #define ALT_SPIS_DR21_DR21_GET(value) (((value) & 0xffffffff) >> 0)
6309 #define ALT_SPIS_DR21_DR21_SET(value) (((value) << 0) & 0xffffffff)
6311 #ifndef __ASSEMBLY__
6323 struct ALT_SPIS_DR21_s
6325 volatile uint32_t dr21 : 32;
6329 typedef struct ALT_SPIS_DR21_s ALT_SPIS_DR21_t;
6333 #define ALT_SPIS_DR21_RESET 0x00000000
6335 #define ALT_SPIS_DR21_OFST 0xb4
6337 #define ALT_SPIS_DR21_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR21_OFST))
6384 #define ALT_SPIS_DR22_DR22_LSB 0
6386 #define ALT_SPIS_DR22_DR22_MSB 31
6388 #define ALT_SPIS_DR22_DR22_WIDTH 32
6390 #define ALT_SPIS_DR22_DR22_SET_MSK 0xffffffff
6392 #define ALT_SPIS_DR22_DR22_CLR_MSK 0x00000000
6394 #define ALT_SPIS_DR22_DR22_RESET 0x0
6396 #define ALT_SPIS_DR22_DR22_GET(value) (((value) & 0xffffffff) >> 0)
6398 #define ALT_SPIS_DR22_DR22_SET(value) (((value) << 0) & 0xffffffff)
6400 #ifndef __ASSEMBLY__
6412 struct ALT_SPIS_DR22_s
6414 volatile uint32_t dr22 : 32;
6418 typedef struct ALT_SPIS_DR22_s ALT_SPIS_DR22_t;
6422 #define ALT_SPIS_DR22_RESET 0x00000000
6424 #define ALT_SPIS_DR22_OFST 0xb8
6426 #define ALT_SPIS_DR22_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR22_OFST))
6473 #define ALT_SPIS_DR23_DR23_LSB 0
6475 #define ALT_SPIS_DR23_DR23_MSB 31
6477 #define ALT_SPIS_DR23_DR23_WIDTH 32
6479 #define ALT_SPIS_DR23_DR23_SET_MSK 0xffffffff
6481 #define ALT_SPIS_DR23_DR23_CLR_MSK 0x00000000
6483 #define ALT_SPIS_DR23_DR23_RESET 0x0
6485 #define ALT_SPIS_DR23_DR23_GET(value) (((value) & 0xffffffff) >> 0)
6487 #define ALT_SPIS_DR23_DR23_SET(value) (((value) << 0) & 0xffffffff)
6489 #ifndef __ASSEMBLY__
6501 struct ALT_SPIS_DR23_s
6503 volatile uint32_t dr23 : 32;
6507 typedef struct ALT_SPIS_DR23_s ALT_SPIS_DR23_t;
6511 #define ALT_SPIS_DR23_RESET 0x00000000
6513 #define ALT_SPIS_DR23_OFST 0xbc
6515 #define ALT_SPIS_DR23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR23_OFST))
6562 #define ALT_SPIS_DR24_DR24_LSB 0
6564 #define ALT_SPIS_DR24_DR24_MSB 31
6566 #define ALT_SPIS_DR24_DR24_WIDTH 32
6568 #define ALT_SPIS_DR24_DR24_SET_MSK 0xffffffff
6570 #define ALT_SPIS_DR24_DR24_CLR_MSK 0x00000000
6572 #define ALT_SPIS_DR24_DR24_RESET 0x0
6574 #define ALT_SPIS_DR24_DR24_GET(value) (((value) & 0xffffffff) >> 0)
6576 #define ALT_SPIS_DR24_DR24_SET(value) (((value) << 0) & 0xffffffff)
6578 #ifndef __ASSEMBLY__
6590 struct ALT_SPIS_DR24_s
6592 volatile uint32_t dr24 : 32;
6596 typedef struct ALT_SPIS_DR24_s ALT_SPIS_DR24_t;
6600 #define ALT_SPIS_DR24_RESET 0x00000000
6602 #define ALT_SPIS_DR24_OFST 0xc0
6604 #define ALT_SPIS_DR24_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR24_OFST))
6651 #define ALT_SPIS_DR25_DR25_LSB 0
6653 #define ALT_SPIS_DR25_DR25_MSB 31
6655 #define ALT_SPIS_DR25_DR25_WIDTH 32
6657 #define ALT_SPIS_DR25_DR25_SET_MSK 0xffffffff
6659 #define ALT_SPIS_DR25_DR25_CLR_MSK 0x00000000
6661 #define ALT_SPIS_DR25_DR25_RESET 0x0
6663 #define ALT_SPIS_DR25_DR25_GET(value) (((value) & 0xffffffff) >> 0)
6665 #define ALT_SPIS_DR25_DR25_SET(value) (((value) << 0) & 0xffffffff)
6667 #ifndef __ASSEMBLY__
6679 struct ALT_SPIS_DR25_s
6681 volatile uint32_t dr25 : 32;
6685 typedef struct ALT_SPIS_DR25_s ALT_SPIS_DR25_t;
6689 #define ALT_SPIS_DR25_RESET 0x00000000
6691 #define ALT_SPIS_DR25_OFST 0xc4
6693 #define ALT_SPIS_DR25_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR25_OFST))
6740 #define ALT_SPIS_DR26_DR26_LSB 0
6742 #define ALT_SPIS_DR26_DR26_MSB 31
6744 #define ALT_SPIS_DR26_DR26_WIDTH 32
6746 #define ALT_SPIS_DR26_DR26_SET_MSK 0xffffffff
6748 #define ALT_SPIS_DR26_DR26_CLR_MSK 0x00000000
6750 #define ALT_SPIS_DR26_DR26_RESET 0x0
6752 #define ALT_SPIS_DR26_DR26_GET(value) (((value) & 0xffffffff) >> 0)
6754 #define ALT_SPIS_DR26_DR26_SET(value) (((value) << 0) & 0xffffffff)
6756 #ifndef __ASSEMBLY__
6768 struct ALT_SPIS_DR26_s
6770 volatile uint32_t dr26 : 32;
6774 typedef struct ALT_SPIS_DR26_s ALT_SPIS_DR26_t;
6778 #define ALT_SPIS_DR26_RESET 0x00000000
6780 #define ALT_SPIS_DR26_OFST 0xc8
6782 #define ALT_SPIS_DR26_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR26_OFST))
6829 #define ALT_SPIS_DR27_DR27_LSB 0
6831 #define ALT_SPIS_DR27_DR27_MSB 31
6833 #define ALT_SPIS_DR27_DR27_WIDTH 32
6835 #define ALT_SPIS_DR27_DR27_SET_MSK 0xffffffff
6837 #define ALT_SPIS_DR27_DR27_CLR_MSK 0x00000000
6839 #define ALT_SPIS_DR27_DR27_RESET 0x0
6841 #define ALT_SPIS_DR27_DR27_GET(value) (((value) & 0xffffffff) >> 0)
6843 #define ALT_SPIS_DR27_DR27_SET(value) (((value) << 0) & 0xffffffff)
6845 #ifndef __ASSEMBLY__
6857 struct ALT_SPIS_DR27_s
6859 volatile uint32_t dr27 : 32;
6863 typedef struct ALT_SPIS_DR27_s ALT_SPIS_DR27_t;
6867 #define ALT_SPIS_DR27_RESET 0x00000000
6869 #define ALT_SPIS_DR27_OFST 0xcc
6871 #define ALT_SPIS_DR27_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR27_OFST))
6918 #define ALT_SPIS_DR28_DR28_LSB 0
6920 #define ALT_SPIS_DR28_DR28_MSB 31
6922 #define ALT_SPIS_DR28_DR28_WIDTH 32
6924 #define ALT_SPIS_DR28_DR28_SET_MSK 0xffffffff
6926 #define ALT_SPIS_DR28_DR28_CLR_MSK 0x00000000
6928 #define ALT_SPIS_DR28_DR28_RESET 0x0
6930 #define ALT_SPIS_DR28_DR28_GET(value) (((value) & 0xffffffff) >> 0)
6932 #define ALT_SPIS_DR28_DR28_SET(value) (((value) << 0) & 0xffffffff)
6934 #ifndef __ASSEMBLY__
6946 struct ALT_SPIS_DR28_s
6948 volatile uint32_t dr28 : 32;
6952 typedef struct ALT_SPIS_DR28_s ALT_SPIS_DR28_t;
6956 #define ALT_SPIS_DR28_RESET 0x00000000
6958 #define ALT_SPIS_DR28_OFST 0xd0
6960 #define ALT_SPIS_DR28_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR28_OFST))
7007 #define ALT_SPIS_DR29_DR29_LSB 0
7009 #define ALT_SPIS_DR29_DR29_MSB 31
7011 #define ALT_SPIS_DR29_DR29_WIDTH 32
7013 #define ALT_SPIS_DR29_DR29_SET_MSK 0xffffffff
7015 #define ALT_SPIS_DR29_DR29_CLR_MSK 0x00000000
7017 #define ALT_SPIS_DR29_DR29_RESET 0x0
7019 #define ALT_SPIS_DR29_DR29_GET(value) (((value) & 0xffffffff) >> 0)
7021 #define ALT_SPIS_DR29_DR29_SET(value) (((value) << 0) & 0xffffffff)
7023 #ifndef __ASSEMBLY__
7035 struct ALT_SPIS_DR29_s
7037 volatile uint32_t dr29 : 32;
7041 typedef struct ALT_SPIS_DR29_s ALT_SPIS_DR29_t;
7045 #define ALT_SPIS_DR29_RESET 0x00000000
7047 #define ALT_SPIS_DR29_OFST 0xd4
7049 #define ALT_SPIS_DR29_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR29_OFST))
7096 #define ALT_SPIS_DR30_DR30_LSB 0
7098 #define ALT_SPIS_DR30_DR30_MSB 31
7100 #define ALT_SPIS_DR30_DR30_WIDTH 32
7102 #define ALT_SPIS_DR30_DR30_SET_MSK 0xffffffff
7104 #define ALT_SPIS_DR30_DR30_CLR_MSK 0x00000000
7106 #define ALT_SPIS_DR30_DR30_RESET 0x0
7108 #define ALT_SPIS_DR30_DR30_GET(value) (((value) & 0xffffffff) >> 0)
7110 #define ALT_SPIS_DR30_DR30_SET(value) (((value) << 0) & 0xffffffff)
7112 #ifndef __ASSEMBLY__
7124 struct ALT_SPIS_DR30_s
7126 volatile uint32_t dr30 : 32;
7130 typedef struct ALT_SPIS_DR30_s ALT_SPIS_DR30_t;
7134 #define ALT_SPIS_DR30_RESET 0x00000000
7136 #define ALT_SPIS_DR30_OFST 0xd8
7138 #define ALT_SPIS_DR30_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR30_OFST))
7185 #define ALT_SPIS_DR31_DR31_LSB 0
7187 #define ALT_SPIS_DR31_DR31_MSB 31
7189 #define ALT_SPIS_DR31_DR31_WIDTH 32
7191 #define ALT_SPIS_DR31_DR31_SET_MSK 0xffffffff
7193 #define ALT_SPIS_DR31_DR31_CLR_MSK 0x00000000
7195 #define ALT_SPIS_DR31_DR31_RESET 0x0
7197 #define ALT_SPIS_DR31_DR31_GET(value) (((value) & 0xffffffff) >> 0)
7199 #define ALT_SPIS_DR31_DR31_SET(value) (((value) << 0) & 0xffffffff)
7201 #ifndef __ASSEMBLY__
7213 struct ALT_SPIS_DR31_s
7215 volatile uint32_t dr31 : 32;
7219 typedef struct ALT_SPIS_DR31_s ALT_SPIS_DR31_t;
7223 #define ALT_SPIS_DR31_RESET 0x00000000
7225 #define ALT_SPIS_DR31_OFST 0xdc
7227 #define ALT_SPIS_DR31_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR31_OFST))
7274 #define ALT_SPIS_DR32_DR32_LSB 0
7276 #define ALT_SPIS_DR32_DR32_MSB 31
7278 #define ALT_SPIS_DR32_DR32_WIDTH 32
7280 #define ALT_SPIS_DR32_DR32_SET_MSK 0xffffffff
7282 #define ALT_SPIS_DR32_DR32_CLR_MSK 0x00000000
7284 #define ALT_SPIS_DR32_DR32_RESET 0x0
7286 #define ALT_SPIS_DR32_DR32_GET(value) (((value) & 0xffffffff) >> 0)
7288 #define ALT_SPIS_DR32_DR32_SET(value) (((value) << 0) & 0xffffffff)
7290 #ifndef __ASSEMBLY__
7302 struct ALT_SPIS_DR32_s
7304 volatile uint32_t dr32 : 32;
7308 typedef struct ALT_SPIS_DR32_s ALT_SPIS_DR32_t;
7312 #define ALT_SPIS_DR32_RESET 0x00000000
7314 #define ALT_SPIS_DR32_OFST 0xe0
7316 #define ALT_SPIS_DR32_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR32_OFST))
7363 #define ALT_SPIS_DR33_DR33_LSB 0
7365 #define ALT_SPIS_DR33_DR33_MSB 31
7367 #define ALT_SPIS_DR33_DR33_WIDTH 32
7369 #define ALT_SPIS_DR33_DR33_SET_MSK 0xffffffff
7371 #define ALT_SPIS_DR33_DR33_CLR_MSK 0x00000000
7373 #define ALT_SPIS_DR33_DR33_RESET 0x0
7375 #define ALT_SPIS_DR33_DR33_GET(value) (((value) & 0xffffffff) >> 0)
7377 #define ALT_SPIS_DR33_DR33_SET(value) (((value) << 0) & 0xffffffff)
7379 #ifndef __ASSEMBLY__
7391 struct ALT_SPIS_DR33_s
7393 volatile uint32_t dr33 : 32;
7397 typedef struct ALT_SPIS_DR33_s ALT_SPIS_DR33_t;
7401 #define ALT_SPIS_DR33_RESET 0x00000000
7403 #define ALT_SPIS_DR33_OFST 0xe4
7405 #define ALT_SPIS_DR33_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR33_OFST))
7452 #define ALT_SPIS_DR34_DR34_LSB 0
7454 #define ALT_SPIS_DR34_DR34_MSB 31
7456 #define ALT_SPIS_DR34_DR34_WIDTH 32
7458 #define ALT_SPIS_DR34_DR34_SET_MSK 0xffffffff
7460 #define ALT_SPIS_DR34_DR34_CLR_MSK 0x00000000
7462 #define ALT_SPIS_DR34_DR34_RESET 0x0
7464 #define ALT_SPIS_DR34_DR34_GET(value) (((value) & 0xffffffff) >> 0)
7466 #define ALT_SPIS_DR34_DR34_SET(value) (((value) << 0) & 0xffffffff)
7468 #ifndef __ASSEMBLY__
7480 struct ALT_SPIS_DR34_s
7482 volatile uint32_t dr34 : 32;
7486 typedef struct ALT_SPIS_DR34_s ALT_SPIS_DR34_t;
7490 #define ALT_SPIS_DR34_RESET 0x00000000
7492 #define ALT_SPIS_DR34_OFST 0xe8
7494 #define ALT_SPIS_DR34_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR34_OFST))
7541 #define ALT_SPIS_DR35_DR35_LSB 0
7543 #define ALT_SPIS_DR35_DR35_MSB 31
7545 #define ALT_SPIS_DR35_DR35_WIDTH 32
7547 #define ALT_SPIS_DR35_DR35_SET_MSK 0xffffffff
7549 #define ALT_SPIS_DR35_DR35_CLR_MSK 0x00000000
7551 #define ALT_SPIS_DR35_DR35_RESET 0x0
7553 #define ALT_SPIS_DR35_DR35_GET(value) (((value) & 0xffffffff) >> 0)
7555 #define ALT_SPIS_DR35_DR35_SET(value) (((value) << 0) & 0xffffffff)
7557 #ifndef __ASSEMBLY__
7569 struct ALT_SPIS_DR35_s
7571 volatile uint32_t dr35 : 32;
7575 typedef struct ALT_SPIS_DR35_s ALT_SPIS_DR35_t;
7579 #define ALT_SPIS_DR35_RESET 0x00000000
7581 #define ALT_SPIS_DR35_OFST 0xec
7583 #define ALT_SPIS_DR35_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR35_OFST))
7606 #define ALT_SPIS_RSVD_1_RSVD1_LSB 0
7608 #define ALT_SPIS_RSVD_1_RSVD1_MSB 31
7610 #define ALT_SPIS_RSVD_1_RSVD1_WIDTH 32
7612 #define ALT_SPIS_RSVD_1_RSVD1_SET_MSK 0xffffffff
7614 #define ALT_SPIS_RSVD_1_RSVD1_CLR_MSK 0x00000000
7616 #define ALT_SPIS_RSVD_1_RSVD1_RESET 0x0
7618 #define ALT_SPIS_RSVD_1_RSVD1_GET(value) (((value) & 0xffffffff) >> 0)
7620 #define ALT_SPIS_RSVD_1_RSVD1_SET(value) (((value) << 0) & 0xffffffff)
7622 #ifndef __ASSEMBLY__
7634 struct ALT_SPIS_RSVD_1_s
7636 const volatile uint32_t RSVD1 : 32;
7640 typedef struct ALT_SPIS_RSVD_1_s ALT_SPIS_RSVD_1_t;
7644 #define ALT_SPIS_RSVD_1_RESET 0x00000000
7646 #define ALT_SPIS_RSVD_1_OFST 0xf8
7648 #define ALT_SPIS_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RSVD_1_OFST))
7671 #define ALT_SPIS_RSVD_2_RSVD2_LSB 0
7673 #define ALT_SPIS_RSVD_2_RSVD2_MSB 31
7675 #define ALT_SPIS_RSVD_2_RSVD2_WIDTH 32
7677 #define ALT_SPIS_RSVD_2_RSVD2_SET_MSK 0xffffffff
7679 #define ALT_SPIS_RSVD_2_RSVD2_CLR_MSK 0x00000000
7681 #define ALT_SPIS_RSVD_2_RSVD2_RESET 0x0
7683 #define ALT_SPIS_RSVD_2_RSVD2_GET(value) (((value) & 0xffffffff) >> 0)
7685 #define ALT_SPIS_RSVD_2_RSVD2_SET(value) (((value) << 0) & 0xffffffff)
7687 #ifndef __ASSEMBLY__
7699 struct ALT_SPIS_RSVD_2_s
7701 const volatile uint32_t RSVD2 : 32;
7705 typedef struct ALT_SPIS_RSVD_2_s ALT_SPIS_RSVD_2_t;
7709 #define ALT_SPIS_RSVD_2_RESET 0x00000000
7711 #define ALT_SPIS_RSVD_2_OFST 0xfc
7713 #define ALT_SPIS_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RSVD_2_OFST))
7715 #ifndef __ASSEMBLY__
7729 volatile ALT_SPIS_CTRLR0_t CTRLR0;
7730 volatile uint32_t _pad_0x4_0x7;
7731 volatile ALT_SPIS_SSIENR_t SSIENR;
7732 volatile ALT_SPIS_MWCR_t MWCR;
7733 volatile uint32_t _pad_0x10_0x17[2];
7734 volatile ALT_SPIS_TXFTLR_t TXFTLR;
7735 volatile ALT_SPIS_RXFTLR_t RXFTLR;
7736 volatile ALT_SPIS_TXFLR_t TXFLR;
7737 volatile ALT_SPIS_RXFLR_t RXFLR;
7738 volatile ALT_SPIS_SR_t SR;
7739 volatile ALT_SPIS_IMR_t IMR;
7740 volatile ALT_SPIS_ISR_t ISR;
7741 volatile ALT_SPIS_RISR_t RISR;
7742 volatile ALT_SPIS_TXOICR_t TXOICR;
7743 volatile ALT_SPIS_RXOICR_t RXOICR;
7744 volatile ALT_SPIS_RXUICR_t RXUICR;
7745 volatile ALT_SPIS_MSTICR_t MSTICR;
7746 volatile ALT_SPIS_ICR_t ICR;
7747 volatile ALT_SPIS_DMACR_t DMACR;
7748 volatile ALT_SPIS_DMATDLR_t DMATDLR;
7749 volatile ALT_SPIS_DMARDLR_t DMARDLR;
7750 volatile ALT_SPIS_IDR_t IDR;
7751 volatile ALT_SPIS_SSI_VERSION_ID_t SSI_VERSION_ID;
7752 volatile ALT_SPIS_DR0_t DR0;
7753 volatile ALT_SPIS_DR1_t DR1;
7754 volatile ALT_SPIS_DR2_t DR2;
7755 volatile ALT_SPIS_DR3_t DR3;
7756 volatile ALT_SPIS_DR4_t DR4;
7757 volatile ALT_SPIS_DR5_t DR5;
7758 volatile ALT_SPIS_DR6_t DR6;
7759 volatile ALT_SPIS_DR7_t DR7;
7760 volatile ALT_SPIS_DR8_t DR8;
7761 volatile ALT_SPIS_DR9_t DR9;
7762 volatile ALT_SPIS_DR10_t DR10;
7763 volatile ALT_SPIS_DR11_t DR11;
7764 volatile ALT_SPIS_DR12_t DR12;
7765 volatile ALT_SPIS_DR13_t DR13;
7766 volatile ALT_SPIS_DR14_t DR14;
7767 volatile ALT_SPIS_DR15_t DR15;
7768 volatile ALT_SPIS_DR16_t DR16;
7769 volatile ALT_SPIS_DR17_t DR17;
7770 volatile ALT_SPIS_DR18_t DR18;
7771 volatile ALT_SPIS_DR19_t DR19;
7772 volatile ALT_SPIS_DR20_t DR20;
7773 volatile ALT_SPIS_DR21_t DR21;
7774 volatile ALT_SPIS_DR22_t DR22;
7775 volatile ALT_SPIS_DR23_t DR23;
7776 volatile ALT_SPIS_DR24_t DR24;
7777 volatile ALT_SPIS_DR25_t DR25;
7778 volatile ALT_SPIS_DR26_t DR26;
7779 volatile ALT_SPIS_DR27_t DR27;
7780 volatile ALT_SPIS_DR28_t DR28;
7781 volatile ALT_SPIS_DR29_t DR29;
7782 volatile ALT_SPIS_DR30_t DR30;
7783 volatile ALT_SPIS_DR31_t DR31;
7784 volatile ALT_SPIS_DR32_t DR32;
7785 volatile ALT_SPIS_DR33_t DR33;
7786 volatile ALT_SPIS_DR34_t DR34;
7787 volatile ALT_SPIS_DR35_t DR35;
7788 volatile uint32_t _pad_0xf0_0xf7[2];
7789 volatile ALT_SPIS_RSVD_1_t RSVD_1;
7790 volatile ALT_SPIS_RSVD_2_t RSVD_2;
7794 typedef struct ALT_SPIS_s ALT_SPIS_t;
7796 struct ALT_SPIS_raw_s
7798 volatile uint32_t CTRLR0;
7799 volatile uint32_t _pad_0x4_0x7;
7800 volatile uint32_t SSIENR;
7801 volatile uint32_t MWCR;
7802 volatile uint32_t _pad_0x10_0x17[2];
7803 volatile uint32_t TXFTLR;
7804 volatile uint32_t RXFTLR;
7805 volatile uint32_t TXFLR;
7806 volatile uint32_t RXFLR;
7807 volatile uint32_t SR;
7808 volatile uint32_t IMR;
7809 volatile uint32_t ISR;
7810 volatile uint32_t RISR;
7811 volatile uint32_t TXOICR;
7812 volatile uint32_t RXOICR;
7813 volatile uint32_t RXUICR;
7814 volatile uint32_t MSTICR;
7815 volatile uint32_t ICR;
7816 volatile uint32_t DMACR;
7817 volatile uint32_t DMATDLR;
7818 volatile uint32_t DMARDLR;
7819 volatile uint32_t IDR;
7820 volatile uint32_t SSI_VERSION_ID;
7821 volatile uint32_t DR0;
7822 volatile uint32_t DR1;
7823 volatile uint32_t DR2;
7824 volatile uint32_t DR3;
7825 volatile uint32_t DR4;
7826 volatile uint32_t DR5;
7827 volatile uint32_t DR6;
7828 volatile uint32_t DR7;
7829 volatile uint32_t DR8;
7830 volatile uint32_t DR9;
7831 volatile uint32_t DR10;
7832 volatile uint32_t DR11;
7833 volatile uint32_t DR12;
7834 volatile uint32_t DR13;
7835 volatile uint32_t DR14;
7836 volatile uint32_t DR15;
7837 volatile uint32_t DR16;
7838 volatile uint32_t DR17;
7839 volatile uint32_t DR18;
7840 volatile uint32_t DR19;
7841 volatile uint32_t DR20;
7842 volatile uint32_t DR21;
7843 volatile uint32_t DR22;
7844 volatile uint32_t DR23;
7845 volatile uint32_t DR24;
7846 volatile uint32_t DR25;
7847 volatile uint32_t DR26;
7848 volatile uint32_t DR27;
7849 volatile uint32_t DR28;
7850 volatile uint32_t DR29;
7851 volatile uint32_t DR30;
7852 volatile uint32_t DR31;
7853 volatile uint32_t DR32;
7854 volatile uint32_t DR33;
7855 volatile uint32_t DR34;
7856 volatile uint32_t DR35;
7857 volatile uint32_t _pad_0xf0_0xf7[2];
7858 volatile uint32_t RSVD_1;
7859 volatile uint32_t RSVD_2;
7863 typedef struct ALT_SPIS_raw_s ALT_SPIS_raw_t;