35 #ifndef __ALTERA_ALT_SDMMC_H__
36 #define __ALTERA_ALT_SDMMC_H__
107 #define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
113 #define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
116 #define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
118 #define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
120 #define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
122 #define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
124 #define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
126 #define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
128 #define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
130 #define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
153 #define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
159 #define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
162 #define ALT_SDMMC_CTL_FIFO_RST_LSB 1
164 #define ALT_SDMMC_CTL_FIFO_RST_MSB 1
166 #define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
168 #define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
170 #define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
172 #define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
174 #define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
176 #define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
198 #define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
204 #define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
207 #define ALT_SDMMC_CTL_DMA_RST_LSB 2
209 #define ALT_SDMMC_CTL_DMA_RST_MSB 2
211 #define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
213 #define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
215 #define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
217 #define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
219 #define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
221 #define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
244 #define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
250 #define ALT_SDMMC_CTL_INT_EN_E_END 0x1
253 #define ALT_SDMMC_CTL_INT_EN_LSB 4
255 #define ALT_SDMMC_CTL_INT_EN_MSB 4
257 #define ALT_SDMMC_CTL_INT_EN_WIDTH 1
259 #define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
261 #define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
263 #define ALT_SDMMC_CTL_INT_EN_RESET 0x0
265 #define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
267 #define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
289 #define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
295 #define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
298 #define ALT_SDMMC_CTL_RD_WAIT_LSB 6
300 #define ALT_SDMMC_CTL_RD_WAIT_MSB 6
302 #define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
304 #define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
306 #define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
308 #define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
310 #define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
312 #define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
338 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
344 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
347 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
349 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
351 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
353 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
355 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
357 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
359 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
361 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
386 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
392 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
395 #define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
397 #define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
399 #define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
401 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
403 #define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
405 #define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
407 #define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
409 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
440 #define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
446 #define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
449 #define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
451 #define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
453 #define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
455 #define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
457 #define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
459 #define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
461 #define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
463 #define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
490 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
496 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
499 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
501 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
503 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
505 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
507 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
509 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
511 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
513 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
538 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
544 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
547 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
549 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
551 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
553 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
555 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
557 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
559 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
561 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
584 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
590 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
593 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
595 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
597 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
599 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
601 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
603 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
605 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
607 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
620 struct ALT_SDMMC_CTL_s
622 uint32_t controller_reset : 1;
623 uint32_t fifo_reset : 1;
624 uint32_t dma_reset : 1;
626 uint32_t int_enable : 1;
628 uint32_t read_wait : 1;
629 uint32_t send_irq_response : 1;
630 uint32_t abort_read_data : 1;
631 uint32_t send_ccsd : 1;
632 uint32_t send_auto_stop_ccsd : 1;
633 uint32_t ceata_device_interrupt_status : 1;
635 uint32_t use_internal_dmac : 1;
640 typedef volatile struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t;
644 #define ALT_SDMMC_CTL_OFST 0x0
682 #define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
688 #define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
691 #define ALT_SDMMC_PWREN_POWER_EN_LSB 0
693 #define ALT_SDMMC_PWREN_POWER_EN_MSB 0
695 #define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
697 #define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
699 #define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
701 #define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
703 #define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
705 #define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
718 struct ALT_SDMMC_PWREN_s
720 uint32_t power_enable : 1;
725 typedef volatile struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
729 #define ALT_SDMMC_PWREN_OFST 0x4
755 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
757 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
759 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
761 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
763 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
765 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
767 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
769 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
782 struct ALT_SDMMC_CLKDIV_s
784 uint32_t clk_divider0 : 8;
789 typedef volatile struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
793 #define ALT_SDMMC_CLKDIV_OFST 0x8
829 #define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
832 #define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
834 #define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 1
836 #define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 2
838 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0x00000003
840 #define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0xfffffffc
842 #define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
844 #define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0x00000003) >> 0)
846 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0x00000003)
859 struct ALT_SDMMC_CLKSRC_s
861 uint32_t clk_source : 2;
866 typedef volatile struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
870 #define ALT_SDMMC_CLKSRC_OFST 0xc
907 #define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
913 #define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
916 #define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
918 #define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
920 #define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
922 #define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
924 #define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
926 #define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
928 #define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
930 #define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
954 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
960 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
963 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
965 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
967 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
969 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
971 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
973 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
975 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
977 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
990 struct ALT_SDMMC_CLKENA_s
992 uint32_t cclk_enable : 1;
994 uint32_t cclk_low_power : 1;
999 typedef volatile struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
1003 #define ALT_SDMMC_CLKENA_OFST 0x10
1027 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1029 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1031 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1033 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1035 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1037 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1039 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1041 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1054 #define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1056 #define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1058 #define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1060 #define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1062 #define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1064 #define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1066 #define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1068 #define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1070 #ifndef __ASSEMBLY__
1081 struct ALT_SDMMC_TMOUT_s
1083 uint32_t response_timeout : 8;
1084 uint32_t data_timeout : 24;
1088 typedef volatile struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
1092 #define ALT_SDMMC_TMOUT_OFST 0x14
1129 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1135 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1138 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1140 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1142 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1144 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1146 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1148 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1150 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1152 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1175 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1181 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1184 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1186 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1188 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1190 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1192 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1194 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1196 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1198 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1200 #ifndef __ASSEMBLY__
1211 struct ALT_SDMMC_CTYPE_s
1213 uint32_t card_width2 : 1;
1215 uint32_t card_width1 : 1;
1220 typedef volatile struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
1224 #define ALT_SDMMC_CTYPE_OFST 0x18
1248 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1250 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1252 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1254 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1256 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1258 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1260 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1262 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1264 #ifndef __ASSEMBLY__
1275 struct ALT_SDMMC_BLKSIZ_s
1277 uint32_t block_size : 16;
1282 typedef volatile struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
1286 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
1318 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1320 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1322 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1324 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1326 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1328 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1330 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1332 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1334 #ifndef __ASSEMBLY__
1345 struct ALT_SDMMC_BYTCNT_s
1347 uint32_t byte_count : 32;
1351 typedef volatile struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
1355 #define ALT_SDMMC_BYTCNT_OFST 0x20
1407 #define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1413 #define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1416 #define ALT_SDMMC_INTMSK_CD_LSB 0
1418 #define ALT_SDMMC_INTMSK_CD_MSB 0
1420 #define ALT_SDMMC_INTMSK_CD_WIDTH 1
1422 #define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1424 #define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1426 #define ALT_SDMMC_INTMSK_CD_RESET 0x0
1428 #define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1430 #define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1453 #define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1459 #define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1462 #define ALT_SDMMC_INTMSK_RE_LSB 1
1464 #define ALT_SDMMC_INTMSK_RE_MSB 1
1466 #define ALT_SDMMC_INTMSK_RE_WIDTH 1
1468 #define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1470 #define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1472 #define ALT_SDMMC_INTMSK_RE_RESET 0x0
1474 #define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1476 #define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1499 #define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1505 #define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1508 #define ALT_SDMMC_INTMSK_CMD_LSB 2
1510 #define ALT_SDMMC_INTMSK_CMD_MSB 2
1512 #define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1514 #define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1516 #define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1518 #define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1520 #define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1522 #define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1545 #define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1551 #define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1554 #define ALT_SDMMC_INTMSK_DTO_LSB 3
1556 #define ALT_SDMMC_INTMSK_DTO_MSB 3
1558 #define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1560 #define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1562 #define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1564 #define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1566 #define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1568 #define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1591 #define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1597 #define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1600 #define ALT_SDMMC_INTMSK_TXDR_LSB 4
1602 #define ALT_SDMMC_INTMSK_TXDR_MSB 4
1604 #define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1606 #define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1608 #define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1610 #define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1612 #define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1614 #define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1637 #define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1643 #define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1646 #define ALT_SDMMC_INTMSK_RXDR_LSB 5
1648 #define ALT_SDMMC_INTMSK_RXDR_MSB 5
1650 #define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1652 #define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1654 #define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1656 #define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1658 #define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1660 #define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1683 #define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
1689 #define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
1692 #define ALT_SDMMC_INTMSK_RCRC_LSB 6
1694 #define ALT_SDMMC_INTMSK_RCRC_MSB 6
1696 #define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
1698 #define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
1700 #define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
1702 #define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
1704 #define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
1706 #define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
1729 #define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
1735 #define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
1738 #define ALT_SDMMC_INTMSK_DCRC_LSB 7
1740 #define ALT_SDMMC_INTMSK_DCRC_MSB 7
1742 #define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
1744 #define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
1746 #define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
1748 #define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
1750 #define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
1752 #define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
1775 #define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
1781 #define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
1784 #define ALT_SDMMC_INTMSK_RTO_LSB 8
1786 #define ALT_SDMMC_INTMSK_RTO_MSB 8
1788 #define ALT_SDMMC_INTMSK_RTO_WIDTH 1
1790 #define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
1792 #define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
1794 #define ALT_SDMMC_INTMSK_RTO_RESET 0x0
1796 #define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
1798 #define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
1821 #define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
1827 #define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
1830 #define ALT_SDMMC_INTMSK_DRT_LSB 9
1832 #define ALT_SDMMC_INTMSK_DRT_MSB 9
1834 #define ALT_SDMMC_INTMSK_DRT_WIDTH 1
1836 #define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
1838 #define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
1840 #define ALT_SDMMC_INTMSK_DRT_RESET 0x0
1842 #define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
1844 #define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
1867 #define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
1873 #define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
1876 #define ALT_SDMMC_INTMSK_HTO_LSB 10
1878 #define ALT_SDMMC_INTMSK_HTO_MSB 10
1880 #define ALT_SDMMC_INTMSK_HTO_WIDTH 1
1882 #define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
1884 #define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
1886 #define ALT_SDMMC_INTMSK_HTO_RESET 0x0
1888 #define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
1890 #define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
1913 #define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
1919 #define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
1922 #define ALT_SDMMC_INTMSK_FRUN_LSB 11
1924 #define ALT_SDMMC_INTMSK_FRUN_MSB 11
1926 #define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
1928 #define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
1930 #define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
1932 #define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
1934 #define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
1936 #define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
1959 #define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
1965 #define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
1968 #define ALT_SDMMC_INTMSK_HLE_LSB 12
1970 #define ALT_SDMMC_INTMSK_HLE_MSB 12
1972 #define ALT_SDMMC_INTMSK_HLE_WIDTH 1
1974 #define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
1976 #define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
1978 #define ALT_SDMMC_INTMSK_HLE_RESET 0x0
1980 #define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
1982 #define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
2005 #define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2011 #define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2014 #define ALT_SDMMC_INTMSK_SBE_LSB 13
2016 #define ALT_SDMMC_INTMSK_SBE_MSB 13
2018 #define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2020 #define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2022 #define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2024 #define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2026 #define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2028 #define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2051 #define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2057 #define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2060 #define ALT_SDMMC_INTMSK_ACD_LSB 14
2062 #define ALT_SDMMC_INTMSK_ACD_MSB 14
2064 #define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2066 #define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2068 #define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2070 #define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2072 #define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2074 #define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2097 #define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2103 #define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2106 #define ALT_SDMMC_INTMSK_EBE_LSB 15
2108 #define ALT_SDMMC_INTMSK_EBE_MSB 15
2110 #define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2112 #define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2114 #define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2116 #define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2118 #define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2120 #define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2143 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2149 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2152 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2154 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 16
2156 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 1
2158 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0x00010000
2160 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0xfffeffff
2162 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2164 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0x00010000) >> 16)
2166 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0x00010000)
2168 #ifndef __ASSEMBLY__
2179 struct ALT_SDMMC_INTMSK_s
2197 uint32_t sdio_int_mask : 1;
2202 typedef volatile struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t;
2206 #define ALT_SDMMC_INTMSK_OFST 0x24
2229 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2231 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2233 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2235 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2237 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2239 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2241 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2243 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2245 #ifndef __ASSEMBLY__
2256 struct ALT_SDMMC_CMDARG_s
2258 uint32_t cmd_arg : 32;
2262 typedef volatile struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
2266 #define ALT_SDMMC_CMDARG_OFST 0x28
2311 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2313 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2315 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2317 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2319 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2321 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2323 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2325 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2347 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x0
2353 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x1
2356 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2358 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2360 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2362 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2364 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2366 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2368 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2370 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2392 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2398 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2401 #define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2403 #define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2405 #define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2407 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2409 #define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2411 #define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2413 #define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2415 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2438 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2444 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2447 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2449 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2451 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2453 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2455 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2457 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2459 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2461 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2483 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2489 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2492 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2494 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2496 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2498 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2500 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2502 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2504 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2506 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2528 #define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2534 #define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2537 #define ALT_SDMMC_CMD_RD_WR_LSB 10
2539 #define ALT_SDMMC_CMD_RD_WR_MSB 10
2541 #define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2543 #define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2545 #define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2547 #define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2549 #define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2551 #define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2573 #define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2579 #define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2582 #define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2584 #define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2586 #define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2588 #define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2590 #define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2592 #define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2594 #define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2596 #define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2627 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2633 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2636 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2638 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2640 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2642 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2644 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2646 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2648 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2650 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
2674 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
2680 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
2683 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
2685 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
2687 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
2689 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
2691 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
2693 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
2695 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
2697 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
2728 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
2734 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
2737 #define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
2739 #define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
2741 #define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
2743 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
2745 #define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
2747 #define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
2749 #define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
2751 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
2779 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
2785 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
2788 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
2790 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
2792 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
2794 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
2796 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
2798 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
2800 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
2802 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
2813 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
2815 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
2817 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
2819 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
2821 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
2823 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
2825 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
2827 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
2859 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
2865 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
2868 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
2870 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
2872 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
2874 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
2876 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
2878 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
2880 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
2882 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
2910 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
2916 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
2919 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
2921 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
2923 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
2925 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
2927 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
2929 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
2931 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
2933 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
2963 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
2970 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
2973 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
2975 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
2977 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
2979 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
2981 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
2983 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
2985 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
2987 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
3011 #define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3017 #define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3020 #define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3022 #define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3024 #define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3026 #define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3028 #define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3030 #define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3032 #define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3034 #define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3057 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3063 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3066 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3068 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3070 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3072 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3074 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3076 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3078 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3080 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3103 #define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3109 #define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3112 #define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3114 #define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3116 #define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3118 #define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3120 #define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3122 #define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3124 #define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3126 #define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3148 #define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3154 #define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3157 #define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3159 #define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3161 #define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3163 #define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3165 #define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3167 #define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3169 #define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3171 #define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3193 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3199 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3202 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3204 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3206 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3208 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3210 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3212 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3214 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3216 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3247 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3253 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3256 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3258 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3260 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3262 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3264 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3266 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3268 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3270 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3296 #define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3302 #define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3305 #define ALT_SDMMC_CMD_START_CMD_LSB 31
3307 #define ALT_SDMMC_CMD_START_CMD_MSB 31
3309 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3311 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3313 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3315 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3317 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3319 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3321 #ifndef __ASSEMBLY__
3332 struct ALT_SDMMC_CMD_s
3334 uint32_t cmd_index : 6;
3335 uint32_t response_expect : 1;
3336 uint32_t response_length : 1;
3337 uint32_t check_response_crc : 1;
3338 uint32_t data_expected : 1;
3339 uint32_t read_write : 1;
3341 uint32_t send_auto_stop : 1;
3342 uint32_t wait_prvdata_complete : 1;
3343 uint32_t stop_abort_cmd : 1;
3344 uint32_t send_initialization : 1;
3345 uint32_t card_number : 5;
3346 uint32_t update_clock_registers_only : 1;
3347 uint32_t read_ceata_device : 1;
3348 uint32_t ccs_expected : 1;
3349 uint32_t enable_boot : 1;
3350 uint32_t expect_boot_ack : 1;
3351 uint32_t disable_boot : 1;
3352 uint32_t boot_mode : 1;
3353 uint32_t volt_switch : 1;
3354 uint32_t use_hold_reg : 1;
3356 uint32_t start_cmd : 1;
3360 typedef volatile struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
3364 #define ALT_SDMMC_CMD_OFST 0x2c
3387 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3389 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3391 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3393 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3395 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3397 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3399 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3401 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3403 #ifndef __ASSEMBLY__
3414 struct ALT_SDMMC_RESP0_s
3416 const uint32_t response0 : 32;
3420 typedef volatile struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
3424 #define ALT_SDMMC_RESP0_OFST 0x30
3448 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3450 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3452 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3454 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3456 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3458 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3460 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3462 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3464 #ifndef __ASSEMBLY__
3475 struct ALT_SDMMC_RESP1_s
3477 const uint32_t response1 : 32;
3481 typedef volatile struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
3485 #define ALT_SDMMC_RESP1_OFST 0x34
3506 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3508 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3510 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3512 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3514 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3516 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3518 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3520 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3522 #ifndef __ASSEMBLY__
3533 struct ALT_SDMMC_RESP2_s
3535 const uint32_t response2 : 32;
3539 typedef volatile struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
3543 #define ALT_SDMMC_RESP2_OFST 0x38
3564 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
3566 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
3568 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
3570 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
3572 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
3574 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
3576 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
3578 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
3580 #ifndef __ASSEMBLY__
3591 struct ALT_SDMMC_RESP3_s
3593 const uint32_t response3 : 32;
3597 typedef volatile struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
3601 #define ALT_SDMMC_RESP3_OFST 0x3c
3652 #define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
3658 #define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
3661 #define ALT_SDMMC_MINTSTS_CD_LSB 0
3663 #define ALT_SDMMC_MINTSTS_CD_MSB 0
3665 #define ALT_SDMMC_MINTSTS_CD_WIDTH 1
3667 #define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
3669 #define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
3671 #define ALT_SDMMC_MINTSTS_CD_RESET 0x0
3673 #define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
3675 #define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
3697 #define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
3703 #define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
3706 #define ALT_SDMMC_MINTSTS_RESP_LSB 1
3708 #define ALT_SDMMC_MINTSTS_RESP_MSB 1
3710 #define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
3712 #define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
3714 #define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
3716 #define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
3718 #define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
3720 #define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
3742 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
3748 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
3751 #define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
3753 #define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
3755 #define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
3757 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
3759 #define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
3761 #define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
3763 #define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
3765 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
3787 #define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
3793 #define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
3796 #define ALT_SDMMC_MINTSTS_DT_LSB 3
3798 #define ALT_SDMMC_MINTSTS_DT_MSB 3
3800 #define ALT_SDMMC_MINTSTS_DT_WIDTH 1
3802 #define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
3804 #define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
3806 #define ALT_SDMMC_MINTSTS_DT_RESET 0x0
3808 #define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
3810 #define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
3832 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
3838 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
3841 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
3843 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
3845 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
3847 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
3849 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
3851 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
3853 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
3855 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
3877 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
3883 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
3886 #define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
3888 #define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
3890 #define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
3892 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
3894 #define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
3896 #define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
3898 #define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
3900 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
3922 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
3928 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
3931 #define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
3933 #define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
3935 #define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
3937 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
3939 #define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
3941 #define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
3943 #define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
3945 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
3967 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
3973 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
3976 #define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
3978 #define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
3980 #define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
3982 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
3984 #define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
3986 #define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
3988 #define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
3990 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
4012 #define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4018 #define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4021 #define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4023 #define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4025 #define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4027 #define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4029 #define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4031 #define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4033 #define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4035 #define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4057 #define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4063 #define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4066 #define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4068 #define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4070 #define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4072 #define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4074 #define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4076 #define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4078 #define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4080 #define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4102 #define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4108 #define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4111 #define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4113 #define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4115 #define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4117 #define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4119 #define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4121 #define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4123 #define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4125 #define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4147 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4153 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4156 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4158 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4160 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4162 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4164 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4166 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4168 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4170 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4192 #define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4198 #define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4201 #define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4203 #define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4205 #define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4207 #define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4209 #define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4211 #define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4213 #define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4215 #define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4237 #define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4243 #define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4246 #define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4248 #define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4250 #define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4252 #define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4254 #define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4256 #define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4258 #define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4260 #define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4282 #define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4288 #define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4291 #define ALT_SDMMC_MINTSTS_ACD_LSB 14
4293 #define ALT_SDMMC_MINTSTS_ACD_MSB 14
4295 #define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4297 #define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4299 #define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4301 #define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4303 #define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4305 #define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4327 #define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4333 #define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4336 #define ALT_SDMMC_MINTSTS_EBE_LSB 15
4338 #define ALT_SDMMC_MINTSTS_EBE_MSB 15
4340 #define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4342 #define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4344 #define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4346 #define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4348 #define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4350 #define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4375 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4381 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4384 #define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4386 #define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 16
4388 #define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 1
4390 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0x00010000
4392 #define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
4394 #define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4396 #define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
4398 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
4400 #ifndef __ASSEMBLY__
4411 struct ALT_SDMMC_MINTSTS_s
4413 const uint32_t cd : 1;
4414 const uint32_t resp : 1;
4415 const uint32_t cmd_done : 1;
4416 const uint32_t dt : 1;
4417 const uint32_t dttxfifodr : 1;
4418 const uint32_t rxfifodr : 1;
4419 const uint32_t respcrcerr : 1;
4420 const uint32_t datacrcerr : 1;
4421 const uint32_t respto : 1;
4422 const uint32_t datardto : 1;
4423 const uint32_t dshto : 1;
4424 const uint32_t fifoovunerr : 1;
4425 const uint32_t hlwerr : 1;
4426 const uint32_t strerr : 1;
4427 const uint32_t acd : 1;
4428 const uint32_t ebe : 1;
4429 const uint32_t sdio_interrupt : 1;
4434 typedef volatile struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
4438 #define ALT_SDMMC_MINTSTS_OFST 0x40
4490 #define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4496 #define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4499 #define ALT_SDMMC_RINTSTS_CD_LSB 0
4501 #define ALT_SDMMC_RINTSTS_CD_MSB 0
4503 #define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4505 #define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4507 #define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4509 #define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4511 #define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4513 #define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4536 #define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4542 #define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4545 #define ALT_SDMMC_RINTSTS_RE_LSB 1
4547 #define ALT_SDMMC_RINTSTS_RE_MSB 1
4549 #define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4551 #define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4553 #define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4555 #define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4557 #define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
4559 #define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
4582 #define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
4588 #define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
4591 #define ALT_SDMMC_RINTSTS_CMD_LSB 2
4593 #define ALT_SDMMC_RINTSTS_CMD_MSB 2
4595 #define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
4597 #define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
4599 #define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
4601 #define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
4603 #define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
4605 #define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
4628 #define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
4634 #define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
4637 #define ALT_SDMMC_RINTSTS_DTO_LSB 3
4639 #define ALT_SDMMC_RINTSTS_DTO_MSB 3
4641 #define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
4643 #define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
4645 #define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
4647 #define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
4649 #define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
4651 #define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
4674 #define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
4680 #define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
4683 #define ALT_SDMMC_RINTSTS_TXDR_LSB 4
4685 #define ALT_SDMMC_RINTSTS_TXDR_MSB 4
4687 #define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
4689 #define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
4691 #define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
4693 #define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
4695 #define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
4697 #define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
4720 #define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
4726 #define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
4729 #define ALT_SDMMC_RINTSTS_RXDR_LSB 5
4731 #define ALT_SDMMC_RINTSTS_RXDR_MSB 5
4733 #define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
4735 #define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
4737 #define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
4739 #define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
4741 #define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
4743 #define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
4766 #define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
4772 #define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
4775 #define ALT_SDMMC_RINTSTS_RCRC_LSB 6
4777 #define ALT_SDMMC_RINTSTS_RCRC_MSB 6
4779 #define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
4781 #define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
4783 #define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
4785 #define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
4787 #define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
4789 #define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
4812 #define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
4818 #define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
4821 #define ALT_SDMMC_RINTSTS_DCRC_LSB 7
4823 #define ALT_SDMMC_RINTSTS_DCRC_MSB 7
4825 #define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
4827 #define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
4829 #define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
4831 #define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
4833 #define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
4835 #define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
4859 #define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
4865 #define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
4868 #define ALT_SDMMC_RINTSTS_BAR_LSB 8
4870 #define ALT_SDMMC_RINTSTS_BAR_MSB 8
4872 #define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
4874 #define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
4876 #define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
4878 #define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
4880 #define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
4882 #define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
4906 #define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
4912 #define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
4915 #define ALT_SDMMC_RINTSTS_BDS_LSB 9
4917 #define ALT_SDMMC_RINTSTS_BDS_MSB 9
4919 #define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
4921 #define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
4923 #define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
4925 #define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
4927 #define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
4929 #define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
4954 #define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
4960 #define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
4963 #define ALT_SDMMC_RINTSTS_HTO_LSB 10
4965 #define ALT_SDMMC_RINTSTS_HTO_MSB 10
4967 #define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
4969 #define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
4971 #define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
4973 #define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
4975 #define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
4977 #define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
5000 #define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5006 #define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5009 #define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5011 #define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5013 #define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5015 #define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5017 #define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5019 #define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5021 #define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5023 #define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5046 #define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5052 #define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5055 #define ALT_SDMMC_RINTSTS_HLE_LSB 12
5057 #define ALT_SDMMC_RINTSTS_HLE_MSB 12
5059 #define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5061 #define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5063 #define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5065 #define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5067 #define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5069 #define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5092 #define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5098 #define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5101 #define ALT_SDMMC_RINTSTS_SBE_LSB 13
5103 #define ALT_SDMMC_RINTSTS_SBE_MSB 13
5105 #define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5107 #define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5109 #define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5111 #define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5113 #define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5115 #define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5138 #define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5144 #define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5147 #define ALT_SDMMC_RINTSTS_ACD_LSB 14
5149 #define ALT_SDMMC_RINTSTS_ACD_MSB 14
5151 #define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5153 #define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5155 #define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5157 #define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5159 #define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5161 #define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5184 #define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5190 #define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5193 #define ALT_SDMMC_RINTSTS_EBE_LSB 15
5195 #define ALT_SDMMC_RINTSTS_EBE_MSB 15
5197 #define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5199 #define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5201 #define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5203 #define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5205 #define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5207 #define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5229 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5235 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5238 #define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5240 #define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 16
5242 #define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 1
5244 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0x00010000
5246 #define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
5248 #define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5250 #define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
5252 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
5254 #ifndef __ASSEMBLY__
5265 struct ALT_SDMMC_RINTSTS_s
5283 uint32_t sdio_interrupt : 1;
5288 typedef volatile struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
5292 #define ALT_SDMMC_RINTSTS_OFST 0x44
5337 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5343 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5346 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5348 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5350 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5352 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5354 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5356 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5358 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5360 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5383 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5389 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5392 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5394 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5396 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5398 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5400 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5402 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5404 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5406 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5428 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5434 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5437 #define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5439 #define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5441 #define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5443 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5445 #define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5447 #define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5449 #define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5451 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5473 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x0
5479 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x1
5482 #define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5484 #define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5486 #define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5488 #define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5490 #define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5492 #define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5494 #define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5496 #define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
5532 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
5538 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
5544 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
5550 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
5556 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
5562 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
5568 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
5574 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
5580 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
5586 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
5592 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
5598 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
5604 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
5610 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
5616 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
5622 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
5625 #define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
5627 #define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
5629 #define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
5631 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
5633 #define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
5635 #define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
5637 #define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
5639 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
5662 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
5668 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
5671 #define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
5673 #define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
5675 #define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
5677 #define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
5679 #define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
5681 #define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
5683 #define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
5685 #define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
5708 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
5714 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
5717 #define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
5719 #define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
5721 #define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
5723 #define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
5725 #define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
5727 #define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
5729 #define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
5731 #define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
5753 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
5759 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
5762 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
5764 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
5766 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
5768 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
5770 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
5772 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
5774 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
5776 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
5787 #define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
5789 #define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
5791 #define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
5793 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
5795 #define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
5797 #define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
5799 #define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
5801 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
5812 #define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
5814 #define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
5816 #define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
5818 #define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
5820 #define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
5822 #define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
5824 #define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
5826 #define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
5828 #ifndef __ASSEMBLY__
5839 struct ALT_SDMMC_STAT_s
5841 const uint32_t fifo_rx_watermark : 1;
5842 const uint32_t fifo_tx_watermark : 1;
5843 const uint32_t fifo_empty : 1;
5844 const uint32_t fifo_full : 1;
5845 const uint32_t command_fsm_states : 4;
5846 const uint32_t data_3_status : 1;
5847 const uint32_t data_busy : 1;
5848 const uint32_t data_state_mc_busy : 1;
5849 const uint32_t response_index : 6;
5850 const uint32_t fifo_count : 13;
5855 typedef volatile struct ALT_SDMMC_STAT_s ALT_SDMMC_STAT_t;
5859 #define ALT_SDMMC_STAT_OFST 0x48
5900 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
5902 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
5904 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
5906 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
5908 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
5910 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
5912 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
5914 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
5945 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
5947 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
5949 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
5951 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
5953 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
5955 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
5957 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
5959 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
5991 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
5997 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
6003 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6009 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6015 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6021 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6027 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6030 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6032 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6034 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6036 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6038 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6040 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6042 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6044 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6046 #ifndef __ASSEMBLY__
6057 struct ALT_SDMMC_FIFOTH_s
6059 uint32_t tx_wmark : 12;
6061 uint32_t rx_wmark : 12;
6062 uint32_t dw_dma_multiple_transaction_size : 3;
6067 typedef volatile struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
6071 #define ALT_SDMMC_FIFOTH_OFST 0x4c
6106 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6112 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6115 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6117 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6119 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6121 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6123 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6125 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6127 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6129 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6131 #ifndef __ASSEMBLY__
6142 struct ALT_SDMMC_CDETECT_s
6144 const uint32_t card_detect_n : 1;
6149 typedef volatile struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
6153 #define ALT_SDMMC_CDETECT_OFST 0x50
6188 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6194 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6197 #define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6199 #define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6201 #define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6203 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6205 #define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6207 #define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6209 #define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6211 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6213 #ifndef __ASSEMBLY__
6224 struct ALT_SDMMC_WRTPRT_s
6226 const uint32_t write_protect : 1;
6231 typedef volatile struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
6235 #define ALT_SDMMC_WRTPRT_OFST 0x54
6256 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
6258 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
6260 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
6262 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
6264 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
6266 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
6268 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6270 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6272 #ifndef __ASSEMBLY__
6283 struct ALT_SDMMC_TCBCNT_s
6285 const uint32_t trans_card_byte_count : 32;
6289 typedef volatile struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
6293 #define ALT_SDMMC_TCBCNT_OFST 0x5c
6318 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
6320 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
6322 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
6324 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
6326 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
6328 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
6330 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6332 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6334 #ifndef __ASSEMBLY__
6345 struct ALT_SDMMC_TBBCNT_s
6347 const uint32_t trans_fifo_byte_count : 32;
6351 typedef volatile struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
6355 #define ALT_SDMMC_TBBCNT_OFST 0x60
6378 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
6380 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
6382 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
6384 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
6386 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
6388 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
6390 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
6392 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
6394 #ifndef __ASSEMBLY__
6405 struct ALT_SDMMC_DEBNCE_s
6407 uint32_t debounce_count : 24;
6412 typedef volatile struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
6416 #define ALT_SDMMC_DEBNCE_OFST 0x64
6437 #define ALT_SDMMC_USRID_USR_ID_LSB 0
6439 #define ALT_SDMMC_USRID_USR_ID_MSB 31
6441 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
6443 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
6445 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
6447 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
6449 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
6451 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
6453 #ifndef __ASSEMBLY__
6464 struct ALT_SDMMC_USRID_s
6466 uint32_t usr_id : 32;
6470 typedef volatile struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
6474 #define ALT_SDMMC_USRID_OFST 0x68
6495 #define ALT_SDMMC_VERID_VER_ID_LSB 0
6497 #define ALT_SDMMC_VERID_VER_ID_MSB 31
6499 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
6501 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
6503 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
6505 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342240a
6507 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
6509 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
6511 #ifndef __ASSEMBLY__
6522 struct ALT_SDMMC_VERID_s
6524 const uint32_t ver_id : 32;
6528 typedef volatile struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
6532 #define ALT_SDMMC_VERID_OFST 0x6c
6578 #define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
6581 #define ALT_SDMMC_HCON_CT_LSB 0
6583 #define ALT_SDMMC_HCON_CT_MSB 0
6585 #define ALT_SDMMC_HCON_CT_WIDTH 1
6587 #define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
6589 #define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
6591 #define ALT_SDMMC_HCON_CT_RESET 0x1
6593 #define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
6595 #define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
6616 #define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
6619 #define ALT_SDMMC_HCON_NC_LSB 1
6621 #define ALT_SDMMC_HCON_NC_MSB 5
6623 #define ALT_SDMMC_HCON_NC_WIDTH 5
6625 #define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
6627 #define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
6629 #define ALT_SDMMC_HCON_NC_RESET 0x0
6631 #define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
6633 #define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
6654 #define ALT_SDMMC_HCON_HBUS_E_APB 0x0
6657 #define ALT_SDMMC_HCON_HBUS_LSB 6
6659 #define ALT_SDMMC_HCON_HBUS_MSB 6
6661 #define ALT_SDMMC_HCON_HBUS_WIDTH 1
6663 #define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
6665 #define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
6667 #define ALT_SDMMC_HCON_HBUS_RESET 0x0
6669 #define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
6671 #define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
6692 #define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
6695 #define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
6697 #define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
6699 #define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
6701 #define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
6703 #define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
6705 #define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
6707 #define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
6709 #define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
6730 #define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
6733 #define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
6735 #define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
6737 #define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
6739 #define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
6741 #define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
6743 #define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
6745 #define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
6747 #define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
6769 #define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
6772 #define ALT_SDMMC_HCON_DMAINTF_LSB 16
6774 #define ALT_SDMMC_HCON_DMAINTF_MSB 17
6776 #define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
6778 #define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
6780 #define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
6782 #define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
6784 #define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
6786 #define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
6808 #define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
6811 #define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
6813 #define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
6815 #define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
6817 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
6819 #define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
6821 #define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
6823 #define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
6825 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
6846 #define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
6849 #define ALT_SDMMC_HCON_RIOS_LSB 21
6851 #define ALT_SDMMC_HCON_RIOS_MSB 21
6853 #define ALT_SDMMC_HCON_RIOS_WIDTH 1
6855 #define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
6857 #define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
6859 #define ALT_SDMMC_HCON_RIOS_RESET 0x0
6861 #define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
6863 #define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
6884 #define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
6887 #define ALT_SDMMC_HCON_IHR_LSB 22
6889 #define ALT_SDMMC_HCON_IHR_MSB 22
6891 #define ALT_SDMMC_HCON_IHR_WIDTH 1
6893 #define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
6895 #define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
6897 #define ALT_SDMMC_HCON_IHR_RESET 0x1
6899 #define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
6901 #define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
6922 #define ALT_SDMMC_HCON_SCFP_E_SET 0x1
6925 #define ALT_SDMMC_HCON_SCFP_LSB 23
6927 #define ALT_SDMMC_HCON_SCFP_MSB 23
6929 #define ALT_SDMMC_HCON_SCFP_WIDTH 1
6931 #define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
6933 #define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
6935 #define ALT_SDMMC_HCON_SCFP_RESET 0x1
6937 #define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
6939 #define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
6960 #define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
6963 #define ALT_SDMMC_HCON_NCD_LSB 24
6965 #define ALT_SDMMC_HCON_NCD_MSB 25
6967 #define ALT_SDMMC_HCON_NCD_WIDTH 2
6969 #define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
6971 #define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
6973 #define ALT_SDMMC_HCON_NCD_RESET 0x0
6975 #define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
6977 #define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
6998 #define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
7001 #define ALT_SDMMC_HCON_ARO_LSB 26
7003 #define ALT_SDMMC_HCON_ARO_MSB 26
7005 #define ALT_SDMMC_HCON_ARO_WIDTH 1
7007 #define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7009 #define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7011 #define ALT_SDMMC_HCON_ARO_RESET 0x0
7013 #define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7015 #define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7017 #ifndef __ASSEMBLY__
7028 struct ALT_SDMMC_HCON_s
7030 const uint32_t ct : 1;
7031 const uint32_t nc : 5;
7032 const uint32_t hbus : 1;
7033 const uint32_t hdatawidth : 3;
7034 const uint32_t haddrwidth : 6;
7035 const uint32_t dmaintf : 2;
7036 const uint32_t dmadatawidth : 3;
7037 const uint32_t rios : 1;
7038 const uint32_t ihr : 1;
7039 const uint32_t scfp : 1;
7040 const uint32_t ncd : 2;
7041 const uint32_t aro : 1;
7046 typedef volatile struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
7050 #define ALT_SDMMC_HCON_OFST 0x70
7091 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7097 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7100 #define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7102 #define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 0
7104 #define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 1
7106 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x00000001
7108 #define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xfffffffe
7110 #define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7112 #define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x00000001) >> 0)
7114 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x00000001)
7136 #define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7142 #define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7145 #define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7147 #define ALT_SDMMC_UHS_REG_DDR_REG_MSB 16
7149 #define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 1
7151 #define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0x00010000
7153 #define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0xfffeffff
7155 #define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7157 #define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0x00010000) >> 16)
7159 #define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0x00010000)
7161 #ifndef __ASSEMBLY__
7172 struct ALT_SDMMC_UHS_REG_s
7174 uint32_t volt_reg : 1;
7176 uint32_t ddr_reg : 1;
7181 typedef volatile struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
7185 #define ALT_SDMMC_UHS_REG_OFST 0x74
7219 #define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
7225 #define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
7228 #define ALT_SDMMC_RST_N_CARD_RST_LSB 0
7230 #define ALT_SDMMC_RST_N_CARD_RST_MSB 0
7232 #define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
7234 #define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
7236 #define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
7238 #define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
7240 #define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
7242 #define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
7244 #ifndef __ASSEMBLY__
7255 struct ALT_SDMMC_RST_N_s
7257 uint32_t card_reset : 1;
7262 typedef volatile struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
7266 #define ALT_SDMMC_RST_N_OFST 0x78
7306 #define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
7312 #define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
7315 #define ALT_SDMMC_BMOD_SWR_LSB 0
7317 #define ALT_SDMMC_BMOD_SWR_MSB 0
7319 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
7321 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
7323 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
7325 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
7327 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
7329 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
7353 #define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
7359 #define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
7362 #define ALT_SDMMC_BMOD_FB_LSB 1
7364 #define ALT_SDMMC_BMOD_FB_MSB 1
7366 #define ALT_SDMMC_BMOD_FB_WIDTH 1
7368 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
7370 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
7372 #define ALT_SDMMC_BMOD_FB_RESET 0x0
7374 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
7376 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
7388 #define ALT_SDMMC_BMOD_DSL_LSB 2
7390 #define ALT_SDMMC_BMOD_DSL_MSB 6
7392 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
7394 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
7396 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
7398 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
7400 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
7402 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
7424 #define ALT_SDMMC_BMOD_DE_E_END 0x1
7430 #define ALT_SDMMC_BMOD_DE_E_DISD 0x0
7433 #define ALT_SDMMC_BMOD_DE_LSB 7
7435 #define ALT_SDMMC_BMOD_DE_MSB 7
7437 #define ALT_SDMMC_BMOD_DE_WIDTH 1
7439 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
7441 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
7443 #define ALT_SDMMC_BMOD_DE_RESET 0x0
7445 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
7447 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
7479 #define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
7485 #define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
7491 #define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
7497 #define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
7503 #define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
7509 #define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
7515 #define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
7521 #define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
7524 #define ALT_SDMMC_BMOD_PBL_LSB 8
7526 #define ALT_SDMMC_BMOD_PBL_MSB 10
7528 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
7530 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
7532 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
7534 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
7536 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
7538 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
7540 #ifndef __ASSEMBLY__
7551 struct ALT_SDMMC_BMOD_s
7557 const uint32_t pbl : 3;
7562 typedef volatile struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
7566 #define ALT_SDMMC_BMOD_OFST 0x80
7591 #define ALT_SDMMC_PLDMND_PD_LSB 0
7593 #define ALT_SDMMC_PLDMND_PD_MSB 31
7595 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
7597 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
7599 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
7601 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
7603 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
7605 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
7607 #ifndef __ASSEMBLY__
7618 struct ALT_SDMMC_PLDMND_s
7624 typedef volatile struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
7628 #define ALT_SDMMC_PLDMND_OFST 0x84
7653 #define ALT_SDMMC_DBADDR_SDL_LSB 2
7655 #define ALT_SDMMC_DBADDR_SDL_MSB 31
7657 #define ALT_SDMMC_DBADDR_SDL_WIDTH 30
7659 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xfffffffc
7661 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000003
7663 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
7665 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xfffffffc) >> 2)
7667 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 2) & 0xfffffffc)
7669 #ifndef __ASSEMBLY__
7680 struct ALT_SDMMC_DBADDR_s
7687 typedef volatile struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
7691 #define ALT_SDMMC_DBADDR_OFST 0x88
7736 #define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
7742 #define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
7745 #define ALT_SDMMC_IDSTS_TI_LSB 0
7747 #define ALT_SDMMC_IDSTS_TI_MSB 0
7749 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
7751 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
7753 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
7755 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
7757 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
7759 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
7781 #define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
7787 #define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
7790 #define ALT_SDMMC_IDSTS_RI_LSB 1
7792 #define ALT_SDMMC_IDSTS_RI_MSB 1
7794 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
7796 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
7798 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
7800 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
7802 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
7804 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
7827 #define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
7833 #define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
7836 #define ALT_SDMMC_IDSTS_FBE_LSB 2
7838 #define ALT_SDMMC_IDSTS_FBE_MSB 2
7840 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
7842 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
7844 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
7846 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
7848 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
7850 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
7875 #define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
7881 #define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
7884 #define ALT_SDMMC_IDSTS_DU_LSB 4
7886 #define ALT_SDMMC_IDSTS_DU_MSB 4
7888 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
7890 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
7892 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
7894 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
7896 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
7898 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
7935 #define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
7941 #define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
7944 #define ALT_SDMMC_IDSTS_CES_LSB 5
7946 #define ALT_SDMMC_IDSTS_CES_MSB 5
7948 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
7950 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
7952 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
7954 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
7956 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
7958 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
7987 #define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
7993 #define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
7996 #define ALT_SDMMC_IDSTS_NIS_LSB 8
7998 #define ALT_SDMMC_IDSTS_NIS_MSB 8
8000 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8002 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8004 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8006 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8008 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8010 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8041 #define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8047 #define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8050 #define ALT_SDMMC_IDSTS_AIS_LSB 9
8052 #define ALT_SDMMC_IDSTS_AIS_MSB 9
8054 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8056 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8058 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8060 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8062 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8064 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
8087 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
8093 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
8096 #define ALT_SDMMC_IDSTS_EB_LSB 10
8098 #define ALT_SDMMC_IDSTS_EB_MSB 12
8100 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
8102 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
8104 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
8106 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
8108 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
8110 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
8139 #define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
8145 #define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
8151 #define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
8157 #define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
8163 #define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
8169 #define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
8175 #define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
8181 #define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
8187 #define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
8190 #define ALT_SDMMC_IDSTS_FSM_LSB 13
8192 #define ALT_SDMMC_IDSTS_FSM_MSB 16
8194 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
8196 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
8198 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
8200 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
8202 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
8204 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
8206 #ifndef __ASSEMBLY__
8217 struct ALT_SDMMC_IDSTS_s
8228 const uint32_t eb : 3;
8229 const uint32_t fsm : 4;
8234 typedef volatile struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
8238 #define ALT_SDMMC_IDSTS_OFST 0x8c
8282 #define ALT_SDMMC_IDINTEN_TI_E_END 0x1
8288 #define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
8291 #define ALT_SDMMC_IDINTEN_TI_LSB 0
8293 #define ALT_SDMMC_IDINTEN_TI_MSB 0
8295 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
8297 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
8299 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
8301 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
8303 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
8305 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
8328 #define ALT_SDMMC_IDINTEN_RI_E_END 0x1
8334 #define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
8337 #define ALT_SDMMC_IDINTEN_RI_LSB 1
8339 #define ALT_SDMMC_IDINTEN_RI_MSB 1
8341 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
8343 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
8345 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
8347 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
8349 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
8351 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
8374 #define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
8380 #define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
8383 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
8385 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
8387 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
8389 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
8391 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
8393 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
8395 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
8397 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
8420 #define ALT_SDMMC_IDINTEN_DU_E_END 0x1
8426 #define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
8429 #define ALT_SDMMC_IDINTEN_DU_LSB 4
8431 #define ALT_SDMMC_IDINTEN_DU_MSB 4
8433 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
8435 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
8437 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
8439 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
8441 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
8443 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
8465 #define ALT_SDMMC_IDINTEN_CES_E_END 0x1
8471 #define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
8474 #define ALT_SDMMC_IDINTEN_CES_LSB 5
8476 #define ALT_SDMMC_IDINTEN_CES_MSB 5
8478 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
8480 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
8482 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
8484 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
8486 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
8488 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
8510 #define ALT_SDMMC_IDINTEN_NI_E_END 0x1
8516 #define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
8519 #define ALT_SDMMC_IDINTEN_NI_LSB 8
8521 #define ALT_SDMMC_IDINTEN_NI_MSB 8
8523 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
8525 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
8527 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
8529 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
8531 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
8533 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
8561 #define ALT_SDMMC_IDINTEN_AI_E_END 0x1
8567 #define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
8570 #define ALT_SDMMC_IDINTEN_AI_LSB 9
8572 #define ALT_SDMMC_IDINTEN_AI_MSB 9
8574 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
8576 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
8578 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
8580 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
8582 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
8584 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
8586 #ifndef __ASSEMBLY__
8597 struct ALT_SDMMC_IDINTEN_s
8612 typedef volatile struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
8616 #define ALT_SDMMC_IDINTEN_OFST 0x90
8640 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
8642 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
8644 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
8646 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
8648 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
8650 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
8652 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
8654 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
8656 #ifndef __ASSEMBLY__
8667 struct ALT_SDMMC_DSCADDR_s
8669 const uint32_t hda : 32;
8673 typedef volatile struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
8677 #define ALT_SDMMC_DSCADDR_OFST 0x94
8701 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
8703 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
8705 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
8707 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
8709 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
8711 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
8713 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
8715 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
8717 #ifndef __ASSEMBLY__
8728 struct ALT_SDMMC_BUFADDR_s
8730 const uint32_t hba : 32;
8734 typedef volatile struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
8738 #define ALT_SDMMC_BUFADDR_OFST 0x98
8776 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
8782 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
8785 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
8787 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
8789 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
8791 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
8793 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
8795 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
8797 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
8799 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
8810 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
8812 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 27
8814 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 12
8816 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x0fff0000
8818 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xf000ffff
8820 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
8822 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x0fff0000) >> 16)
8824 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x0fff0000)
8826 #ifndef __ASSEMBLY__
8837 struct ALT_SDMMC_CARDTHRCTL_s
8839 uint32_t cardrdthren : 1;
8841 uint32_t cardrdthreshold : 12;
8846 typedef volatile struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
8850 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
8885 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
8891 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
8894 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
8896 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
8898 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
8900 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
8902 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
8904 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
8906 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
8908 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
8910 #ifndef __ASSEMBLY__
8921 struct ALT_SDMMC_BACK_END_POWER_R_s
8923 uint32_t back_end_power : 16;
8928 typedef volatile struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
8932 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
8957 #define ALT_SDMMC_DATA_VALUE_LSB 0
8959 #define ALT_SDMMC_DATA_VALUE_MSB 31
8961 #define ALT_SDMMC_DATA_VALUE_WIDTH 32
8963 #define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
8965 #define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
8967 #define ALT_SDMMC_DATA_VALUE_RESET 0x0
8969 #define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
8971 #define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
8973 #ifndef __ASSEMBLY__
8984 struct ALT_SDMMC_DATA_s
8986 uint32_t value : 32;
8990 typedef volatile struct ALT_SDMMC_DATA_s ALT_SDMMC_DATA_t;
8994 #define ALT_SDMMC_DATA_OFST 0x200
8996 #ifndef __ASSEMBLY__
9009 ALT_SDMMC_CTL_t ctrl;
9010 ALT_SDMMC_PWREN_t pwren;
9011 ALT_SDMMC_CLKDIV_t clkdiv;
9012 ALT_SDMMC_CLKSRC_t clksrc;
9013 ALT_SDMMC_CLKENA_t clkena;
9014 ALT_SDMMC_TMOUT_t tmout;
9015 ALT_SDMMC_CTYPE_t ctype;
9016 ALT_SDMMC_BLKSIZ_t blksiz;
9017 ALT_SDMMC_BYTCNT_t bytcnt;
9018 ALT_SDMMC_INTMSK_t intmask;
9019 ALT_SDMMC_CMDARG_t cmdarg;
9020 ALT_SDMMC_CMD_t cmd;
9021 ALT_SDMMC_RESP0_t resp0;
9022 ALT_SDMMC_RESP1_t resp1;
9023 ALT_SDMMC_RESP2_t resp2;
9024 ALT_SDMMC_RESP3_t resp3;
9025 ALT_SDMMC_MINTSTS_t mintsts;
9026 ALT_SDMMC_RINTSTS_t rintsts;
9027 ALT_SDMMC_STAT_t status;
9028 ALT_SDMMC_FIFOTH_t fifoth;
9029 ALT_SDMMC_CDETECT_t cdetect;
9030 ALT_SDMMC_WRTPRT_t wrtprt;
9031 volatile uint32_t _pad_0x58_0x5b;
9032 ALT_SDMMC_TCBCNT_t tcbcnt;
9033 ALT_SDMMC_TBBCNT_t tbbcnt;
9034 ALT_SDMMC_DEBNCE_t debnce;
9035 ALT_SDMMC_USRID_t usrid;
9036 ALT_SDMMC_VERID_t verid;
9037 ALT_SDMMC_HCON_t hcon;
9038 ALT_SDMMC_UHS_REG_t uhs_reg;
9039 ALT_SDMMC_RST_N_t rst_n;
9040 volatile uint32_t _pad_0x7c_0x7f;
9041 ALT_SDMMC_BMOD_t bmod;
9042 ALT_SDMMC_PLDMND_t pldmnd;
9043 ALT_SDMMC_DBADDR_t dbaddr;
9044 ALT_SDMMC_IDSTS_t idsts;
9045 ALT_SDMMC_IDINTEN_t idinten;
9046 ALT_SDMMC_DSCADDR_t dscaddr;
9047 ALT_SDMMC_BUFADDR_t bufaddr;
9048 volatile uint32_t _pad_0x9c_0xff[25];
9049 ALT_SDMMC_CARDTHRCTL_t cardthrctl;
9050 ALT_SDMMC_BACK_END_POWER_R_t back_end_power_r;
9051 volatile uint32_t _pad_0x108_0x1ff[62];
9052 ALT_SDMMC_DATA_t data;
9053 volatile uint32_t _pad_0x204_0x400[127];
9057 typedef volatile struct ALT_SDMMC_s ALT_SDMMC_t;
9059 struct ALT_SDMMC_raw_s
9061 volatile uint32_t ctrl;
9062 volatile uint32_t pwren;
9063 volatile uint32_t clkdiv;
9064 volatile uint32_t clksrc;
9065 volatile uint32_t clkena;
9066 volatile uint32_t tmout;
9067 volatile uint32_t ctype;
9068 volatile uint32_t blksiz;
9069 volatile uint32_t bytcnt;
9070 volatile uint32_t intmask;
9071 volatile uint32_t cmdarg;
9072 volatile uint32_t cmd;
9073 volatile uint32_t resp0;
9074 volatile uint32_t resp1;
9075 volatile uint32_t resp2;
9076 volatile uint32_t resp3;
9077 volatile uint32_t mintsts;
9078 volatile uint32_t rintsts;
9079 volatile uint32_t status;
9080 volatile uint32_t fifoth;
9081 volatile uint32_t cdetect;
9082 volatile uint32_t wrtprt;
9083 uint32_t _pad_0x58_0x5b;
9084 volatile uint32_t tcbcnt;
9085 volatile uint32_t tbbcnt;
9086 volatile uint32_t debnce;
9087 volatile uint32_t usrid;
9088 volatile uint32_t verid;
9089 volatile uint32_t hcon;
9090 volatile uint32_t uhs_reg;
9091 volatile uint32_t rst_n;
9092 uint32_t _pad_0x7c_0x7f;
9093 volatile uint32_t bmod;
9094 volatile uint32_t pldmnd;
9095 volatile uint32_t dbaddr;
9096 volatile uint32_t idsts;
9097 volatile uint32_t idinten;
9098 volatile uint32_t dscaddr;
9099 volatile uint32_t bufaddr;
9100 uint32_t _pad_0x9c_0xff[25];
9101 volatile uint32_t cardthrctl;
9102 volatile uint32_t back_end_power_r;
9103 uint32_t _pad_0x108_0x1ff[62];
9104 volatile uint32_t data;
9105 uint32_t _pad_0x204_0x400[127];
9109 typedef volatile struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;