Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_noc_mpu_m0_rate_adresp_main_rate.h
1 /***********************************************************************************
2 * *
3 * Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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32 
33 /* Altera - ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE */
34 
35 #ifndef __ALT_SOCAL_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_H__
36 #define __ALT_SOCAL_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE
50  *
51  */
52 /*
53  * Register : MPU_M0_rate_adResp_main_RateAdapter_Id_CoreId
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :-------|:-------|:---------|:-------------------------------------------------------------------------------
59  * [7:0] | R | 0x1 | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID
60  * [31:8] | R | 0x7af9a6 | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM
61  *
62  */
63 /*
64  * Field : CORETYPEID
65  *
66  * Field identifying the type of IP.
67  *
68  * Field Access Macros:
69  *
70  */
71 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field. */
72 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_LSB 0
73 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field. */
74 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_MSB 7
75 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field. */
76 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_WIDTH 8
77 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field value. */
78 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_SET_MSK 0x000000ff
79 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field value. */
80 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_CLR_MSK 0xffffff00
81 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field. */
82 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_RESET 0x1
83 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID field value from a register. */
84 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID register field value suitable for setting the register. */
86 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
88 /*
89  * Field : CORECHECKSUM
90  *
91  * Field containing a checksum of the parameters of the IP.
92  *
93  * Field Access Macros:
94  *
95  */
96 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field. */
97 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_LSB 8
98 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field. */
99 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_MSB 31
100 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field. */
101 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_WIDTH 24
102 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field value. */
103 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_SET_MSK 0xffffff00
104 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field value. */
105 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field. */
107 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_RESET 0x7af9a6
108 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM field value from a register. */
109 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM register field value suitable for setting the register. */
111 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 /*
115  * WARNING: The C register and register group struct declarations are provided for
116  * convenience and illustrative purposes. They should, however, be used with
117  * caution as the C language standard provides no guarantees about the alignment or
118  * atomicity of device memory accesses. The recommended practice for writing
119  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
120  * alt_write_word() functions.
121  *
122  * The struct declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID.
123  */
124 struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_s
125 {
126  const uint32_t CORETYPEID : 8; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_TYPEID */
127  const uint32_t CORECHECKSUM : 24; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_CHECKSUM */
128 };
129 
130 /* The typedef declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID. */
131 typedef volatile struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_s ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_t;
132 #endif /* __ASSEMBLY__ */
133 
134 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID register. */
135 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_RESET 0x7af9a601
136 /* The byte offset of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID register from the beginning of the component. */
137 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_OFST 0x0
138 /* The address of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID register. */
139 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_OFST))
140 
141 /*
142  * Register : MPU_M0_rate_adResp_main_RateAdapter_Id_RevisionId
143  *
144  * Register Layout
145  *
146  * Bits | Access | Reset | Description
147  * :-------|:-------|:--------|:-------------------------------------------------------------------------------
148  * [7:0] | R | 0x0 | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID
149  * [31:8] | R | 0x129ff | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID
150  *
151  */
152 /*
153  * Field : USERID
154  *
155  * Field containing a user defined value, not used anywhere inside the IP itself.
156  *
157  * Field Access Macros:
158  *
159  */
160 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field. */
161 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_LSB 0
162 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field. */
163 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_MSB 7
164 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field. */
165 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_WIDTH 8
166 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field value. */
167 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_SET_MSK 0x000000ff
168 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field value. */
169 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_CLR_MSK 0xffffff00
170 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field. */
171 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_RESET 0x0
172 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID field value from a register. */
173 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
174 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID register field value suitable for setting the register. */
175 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
176 
177 /*
178  * Field : FLEXNOCID
179  *
180  * Field containing the build revision of the software used to generate the IP HDL
181  * code.
182  *
183  * Field Access Macros:
184  *
185  */
186 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
187 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_LSB 8
188 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
189 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_MSB 31
190 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
191 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_WIDTH 24
192 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field value. */
193 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_SET_MSK 0xffffff00
194 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field value. */
195 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_CLR_MSK 0x000000ff
196 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field. */
197 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_RESET 0x129ff
198 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID field value from a register. */
199 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
200 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID register field value suitable for setting the register. */
201 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
202 
203 #ifndef __ASSEMBLY__
204 /*
205  * WARNING: The C register and register group struct declarations are provided for
206  * convenience and illustrative purposes. They should, however, be used with
207  * caution as the C language standard provides no guarantees about the alignment or
208  * atomicity of device memory accesses. The recommended practice for writing
209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
210  * alt_write_word() functions.
211  *
212  * The struct declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID.
213  */
214 struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_s
215 {
216  const uint32_t USERID : 8; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_UID */
217  const uint32_t FLEXNOCID : 24; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_FLEXNOCID */
218 };
219 
220 /* The typedef declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID. */
221 typedef volatile struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_s ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_t;
222 #endif /* __ASSEMBLY__ */
223 
224 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID register. */
225 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_RESET 0x0129ff00
226 /* The byte offset of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID register from the beginning of the component. */
227 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_OFST 0x4
228 /* The address of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID register. */
229 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_OFST))
230 
231 /*
232  * Register : MPU_M0_rate_adResp_main_RateAdapter_Rate
233  *
234  *
235  * Register Layout
236  *
237  * Bits | Access | Reset | Description
238  * :--------|:-------|:--------|:-------------------------------------------------------------------------
239  * [9:0] | RW | 0x0 | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE
240  * [31:10] | ??? | Unknown | *UNDEFINED*
241  *
242  */
243 /*
244  * Field : RATE
245  *
246  * The ratio of outgoing to incoming throughput. This value determines what portion
247  * of a received packet will be stored before its head is transmitted. An optimal
248  * setting avoids transmitting bubbles, while adding no delay to packets. The ratio
249  * is expressed as 256 / (ratio - 1). For example, a 3:1 ratio of outgoing to
250  * incoming throughput would be indicated by value 0x06E. Note that throughput is
251  * the product of clock frequency x data bus width. A value of 0x000 causes the
252  * rate adapter to store a packet until either the entire packet is received or the
253  * buffer becomes full.
254  *
255  * Field Access Macros:
256  *
257  */
258 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field. */
259 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_LSB 0
260 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field. */
261 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_MSB 9
262 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field. */
263 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_WIDTH 10
264 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field value. */
265 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_SET_MSK 0x000003ff
266 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field value. */
267 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_CLR_MSK 0xfffffc00
268 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field. */
269 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_RESET 0x0
270 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE field value from a register. */
271 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_GET(value) (((value) & 0x000003ff) >> 0)
272 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE register field value suitable for setting the register. */
273 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE_SET(value) (((value) << 0) & 0x000003ff)
274 
275 #ifndef __ASSEMBLY__
276 /*
277  * WARNING: The C register and register group struct declarations are provided for
278  * convenience and illustrative purposes. They should, however, be used with
279  * caution as the C language standard provides no guarantees about the alignment or
280  * atomicity of device memory accesses. The recommended practice for writing
281  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
282  * alt_write_word() functions.
283  *
284  * The struct declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE.
285  */
286 struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_s
287 {
288  uint32_t RATE : 10; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RATE */
289  uint32_t : 22; /* *UNDEFINED* */
290 };
291 
292 /* The typedef declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE. */
293 typedef volatile struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_s ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_t;
294 #endif /* __ASSEMBLY__ */
295 
296 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE register. */
297 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_RESET 0x00000000
298 /* The byte offset of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE register from the beginning of the component. */
299 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_OFST 0x8
300 /* The address of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE register. */
301 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_OFST))
302 
303 /*
304  * Register : MPU_M0_rate_adResp_main_RateAdapter_Bypass
305  *
306  *
307  * Register Layout
308  *
309  * Bits | Access | Reset | Description
310  * :-------|:-------|:--------|:-----------------------------------------------------------------------------
311  * [0] | RW | 0x0 | ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS
312  * [31:1] | ??? | Unknown | *UNDEFINED*
313  *
314  */
315 /*
316  * Field : BYPASS
317  *
318  * Disable the rate adaptation capability. This causes the rate adapter to act as a
319  * FIFO by transmitting received words, without delay, as soon as they can be
320  * transmitted. This setting is useful when the incoming throughput is equal to or
321  * greater than the downstream throughput.
322  *
323  * Field Access Macros:
324  *
325  */
326 /* The Least Significant Bit (LSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field. */
327 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_LSB 0
328 /* The Most Significant Bit (MSB) position of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field. */
329 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_MSB 0
330 /* The width in bits of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field. */
331 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_WIDTH 1
332 /* The mask used to set the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field value. */
333 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_SET_MSK 0x00000001
334 /* The mask used to clear the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field value. */
335 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_CLR_MSK 0xfffffffe
336 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field. */
337 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_RESET 0x0
338 /* Extracts the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS field value from a register. */
339 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_GET(value) (((value) & 0x00000001) >> 0)
340 /* Produces a ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS register field value suitable for setting the register. */
341 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS_SET(value) (((value) << 0) & 0x00000001)
342 
343 #ifndef __ASSEMBLY__
344 /*
345  * WARNING: The C register and register group struct declarations are provided for
346  * convenience and illustrative purposes. They should, however, be used with
347  * caution as the C language standard provides no guarantees about the alignment or
348  * atomicity of device memory accesses. The recommended practice for writing
349  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
350  * alt_write_word() functions.
351  *
352  * The struct declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS.
353  */
354 struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_s
355 {
356  uint32_t BYPASS : 1; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_BYPASS */
357  uint32_t : 31; /* *UNDEFINED* */
358 };
359 
360 /* The typedef declaration for register ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS. */
361 typedef volatile struct ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_s ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_t;
362 #endif /* __ASSEMBLY__ */
363 
364 /* The reset value of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS register. */
365 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_RESET 0x00000000
366 /* The byte offset of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS register from the beginning of the component. */
367 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_OFST 0xc
368 /* The address of the ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS register. */
369 #define ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_OFST))
370 
371 #ifndef __ASSEMBLY__
372 /*
373  * WARNING: The C register and register group struct declarations are provided for
374  * convenience and illustrative purposes. They should, however, be used with
375  * caution as the C language standard provides no guarantees about the alignment or
376  * atomicity of device memory accesses. The recommended practice for writing
377  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
378  * alt_write_word() functions.
379  *
380  * The struct declaration for register group ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE.
381  */
382 struct ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_s
383 {
384  ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID_t MPU_M0_rate_adResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID */
385  ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID_t MPU_M0_rate_adResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID */
386  ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE_t MPU_M0_rate_adResp_main_RateAdapter_Rate; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE */
387  ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS_t MPU_M0_rate_adResp_main_RateAdapter_Bypass; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS */
388  volatile uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
389 };
390 
391 /* The typedef declaration for register group ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE. */
392 typedef volatile struct ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_s ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_t;
393 /* The struct declaration for the raw register contents of register group ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE. */
394 struct ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_raw_s
395 {
396  volatile uint32_t MPU_M0_rate_adResp_main_RateAdapter_Id_CoreId; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_COREID */
397  volatile uint32_t MPU_M0_rate_adResp_main_RateAdapter_Id_RevisionId; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_REVID */
398  volatile uint32_t MPU_M0_rate_adResp_main_RateAdapter_Rate; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_RATE */
399  volatile uint32_t MPU_M0_rate_adResp_main_RateAdapter_Bypass; /* ALT_NOC_MPU_RATE_ADRESP_MAIN_RATE_MPU_M0_RATE_ADRESP_MAIN_RATE_BYPASS */
400  uint32_t _pad_0x10_0x80[28]; /* *UNDEFINED* */
401 };
402 
403 /* The typedef declaration for the raw register contents of register group ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE. */
404 typedef volatile struct ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_raw_s ALT_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_raw_t;
405 #endif /* __ASSEMBLY__ */
406 
407 
408 #ifdef __cplusplus
409 }
410 #endif /* __cplusplus */
411 #endif /* __ALT_SOCAL_NOC_MPU_M0_RATE_ADRESP_MAIN_RATE_H__ */
412