35 #ifndef __ALT_SOCAL_NOC_FW_LWH2F_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_LWH2F_SCR_H__
91 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_LSB 0
93 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_MSB 0
95 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_WIDTH 1
97 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_SET_MSK 0x00000001
99 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_CLR_MSK 0xfffffffe
101 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_RESET 0x0
103 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_GET(value) (((value) & 0x00000001) >> 0)
105 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_MPU_SET(value) (((value) << 0) & 0x00000001)
118 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_LSB 8
120 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_MSB 8
122 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_WIDTH 1
124 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_SET_MSK 0x00000100
126 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_CLR_MSK 0xfffffeff
128 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_RESET 0x0
130 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_GET(value) (((value) & 0x00000100) >> 8)
132 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_DMA_SET(value) (((value) << 8) & 0x00000100)
145 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_LSB 17
147 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_MSB 17
149 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_WIDTH 1
151 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_SET_MSK 0x00020000
153 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_CLR_MSK 0xfffdffff
155 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_RESET 0x0
157 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_GET(value) (((value) & 0x00020000) >> 17)
159 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC0_SET(value) (((value) << 17) & 0x00020000)
172 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_LSB 18
174 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_MSB 18
176 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_WIDTH 1
178 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_SET_MSK 0x00040000
180 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_CLR_MSK 0xfffbffff
182 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_RESET 0x0
184 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_GET(value) (((value) & 0x00040000) >> 18)
186 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC1_SET(value) (((value) << 18) & 0x00040000)
199 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_LSB 19
201 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_MSB 19
203 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_WIDTH 1
205 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_SET_MSK 0x00080000
207 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_CLR_MSK 0xfff7ffff
209 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_RESET 0x0
211 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_GET(value) (((value) & 0x00080000) >> 19)
213 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_EMAC2_SET(value) (((value) << 19) & 0x00080000)
226 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_LSB 20
228 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_MSB 20
230 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_WIDTH 1
232 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_SET_MSK 0x00100000
234 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_CLR_MSK 0xffefffff
236 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_RESET 0x0
238 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_GET(value) (((value) & 0x00100000) >> 20)
240 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB0_SET(value) (((value) << 20) & 0x00100000)
253 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_LSB 21
255 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_MSB 21
257 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_WIDTH 1
259 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_SET_MSK 0x00200000
261 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_CLR_MSK 0xffdfffff
263 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_RESET 0x0
265 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_GET(value) (((value) & 0x00200000) >> 21)
267 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_USB1_SET(value) (((value) << 21) & 0x00200000)
280 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_LSB 22
282 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_MSB 22
284 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_WIDTH 1
286 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_SET_MSK 0x00400000
288 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_CLR_MSK 0xffbfffff
290 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_RESET 0x0
292 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
294 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDMMC_SET(value) (((value) << 22) & 0x00400000)
307 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_LSB 23
309 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_MSB 23
311 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_WIDTH 1
313 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_SET_MSK 0x00800000
315 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_CLR_MSK 0xff7fffff
317 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_RESET 0x0
319 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_GET(value) (((value) & 0x00800000) >> 23)
321 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_NAND_SET(value) (((value) << 23) & 0x00800000)
334 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_LSB 24
336 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_MSB 24
338 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_WIDTH 1
340 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_SET_MSK 0x01000000
342 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_CLR_MSK 0xfeffffff
344 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_RESET 0x0
346 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_GET(value) (((value) & 0x01000000) >> 24)
348 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_AXI_AP_SET(value) (((value) << 24) & 0x01000000)
361 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_LSB 25
363 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_MSB 25
365 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_WIDTH 1
367 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_SET_MSK 0x02000000
369 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_CLR_MSK 0xfdffffff
371 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_RESET 0x0
373 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_GET(value) (((value) & 0x02000000) >> 25)
375 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_ETR_SET(value) (((value) << 25) & 0x02000000)
388 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_LSB 26
390 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_MSB 26
392 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_WIDTH 1
394 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_SET_MSK 0x04000000
396 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_CLR_MSK 0xfbffffff
398 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_RESET 0x0
400 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_GET(value) (((value) & 0x04000000) >> 26)
402 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_SDMMC_SET(value) (((value) << 26) & 0x04000000)
415 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_LSB 27
417 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_MSB 27
419 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_WIDTH 1
421 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_SET_MSK 0x08000000
423 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_CLR_MSK 0xf7ffffff
425 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_RESET 0x0
427 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_GET(value) (((value) & 0x08000000) >> 27)
429 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_SDM_NAND_SET(value) (((value) << 27) & 0x08000000)
443 struct ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_s
445 volatile uint32_t mpu : 1;
447 volatile uint32_t dma : 1;
449 volatile uint32_t emac0 : 1;
450 volatile uint32_t emac1 : 1;
451 volatile uint32_t emac2 : 1;
452 volatile uint32_t usb0 : 1;
453 volatile uint32_t usb1 : 1;
454 volatile uint32_t sdmmc : 1;
455 volatile uint32_t nand : 1;
456 volatile uint32_t axi_ap : 1;
457 volatile uint32_t etr : 1;
458 volatile uint32_t sdm_sdmmc : 1;
459 volatile uint32_t sdm_nand : 1;
464 typedef struct ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_s ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_t;
468 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_RESET 0x00000000
470 #define ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_OFST 0x0
484 struct ALT_NOC_FW_LWH2F_SCR_s
486 volatile ALT_NOC_FW_LWH2F_SCR_LWSOC2FPGA_t lwsoc2fpga;
487 volatile uint32_t _pad_0x4_0x100[63];
491 typedef struct ALT_NOC_FW_LWH2F_SCR_s ALT_NOC_FW_LWH2F_SCR_t;
493 struct ALT_NOC_FW_LWH2F_SCR_raw_s
495 volatile uint32_t lwsoc2fpga;
496 volatile uint32_t _pad_0x4_0x100[63];
500 typedef struct ALT_NOC_FW_LWH2F_SCR_raw_s ALT_NOC_FW_LWH2F_SCR_raw_t;