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alt_soc_noc_fw_ddr_f2sdr_scr.h
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32 
33 /* Altera - ALT_SOC_NOC_FW_DDR_F2SDR_SCR */
34 
35 #ifndef __ALT_SOCAL_SOC_NOC_FW_DDR_F2SDR_SCR_H__
36 #define __ALT_SOCAL_SOC_NOC_FW_DDR_F2SDR_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : SOC_NOC_FW_DDR_F2SDR_SCR
50  * DDR Security Control Registers (SCR)
51  *
52  */
53 /*
54  * Register : enable
55  *
56  * Enable
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :-------|:-------|:------|:--------------------------------------------------
62  * [0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE
63  * [1] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE
64  * [2] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE
65  * [3] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE
66  * [31:4] | ??? | 0x0 | *UNDEFINED*
67  *
68  */
69 /*
70  * Field : region0enable
71  *
72  * Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is
73  * disabled
74  *
75  * Field Access Macros:
76  *
77  */
78 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field. */
79 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_LSB 0
80 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field. */
81 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_MSB 0
82 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field. */
83 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_WIDTH 1
84 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field value. */
85 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_SET_MSK 0x00000001
86 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field value. */
87 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_CLR_MSK 0xfffffffe
88 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field. */
89 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_RESET 0x0
90 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE field value from a register. */
91 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
92 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE register field value suitable for setting the register. */
93 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
94 
95 /*
96  * Field : region1enable
97  *
98  * Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is
99  * disabled
100  *
101  * Field Access Macros:
102  *
103  */
104 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field. */
105 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_LSB 1
106 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field. */
107 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_MSB 1
108 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field. */
109 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_WIDTH 1
110 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field value. */
111 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_SET_MSK 0x00000002
112 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field value. */
113 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_CLR_MSK 0xfffffffd
114 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field. */
115 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_RESET 0x0
116 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE field value from a register. */
117 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
118 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE register field value suitable for setting the register. */
119 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
120 
121 /*
122  * Field : region2enable
123  *
124  * Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is
125  * disabled
126  *
127  * Field Access Macros:
128  *
129  */
130 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field. */
131 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_LSB 2
132 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field. */
133 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_MSB 2
134 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field. */
135 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_WIDTH 1
136 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field value. */
137 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_SET_MSK 0x00000004
138 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field value. */
139 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_CLR_MSK 0xfffffffb
140 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field. */
141 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_RESET 0x0
142 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE field value from a register. */
143 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
144 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE register field value suitable for setting the register. */
145 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
146 
147 /*
148  * Field : region3enable
149  *
150  * Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is
151  * disabled
152  *
153  * Field Access Macros:
154  *
155  */
156 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field. */
157 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_LSB 3
158 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field. */
159 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_MSB 3
160 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field. */
161 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_WIDTH 1
162 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field value. */
163 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_SET_MSK 0x00000008
164 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field value. */
165 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_CLR_MSK 0xfffffff7
166 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field. */
167 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_RESET 0x0
168 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE field value from a register. */
169 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
170 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE register field value suitable for setting the register. */
171 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
172 
173 #ifndef __ASSEMBLY__
174 /*
175  * WARNING: The C register and register group struct declarations are provided for
176  * convenience and illustrative purposes. They should, however, be used with
177  * caution as the C language standard provides no guarantees about the alignment or
178  * atomicity of device memory accesses. The recommended practice for coding device
179  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
180  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
181  * alt_write_dword() functions for 64 bit registers.
182  *
183  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE.
184  */
185 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_s
186 {
187  volatile uint32_t region0enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION0ENABLE */
188  volatile uint32_t region1enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION1ENABLE */
189  volatile uint32_t region2enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION2ENABLE */
190  volatile uint32_t region3enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_REGION3ENABLE */
191  uint32_t : 28; /* *UNDEFINED* */
192 };
193 
194 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE. */
195 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_t;
196 #endif /* __ASSEMBLY__ */
197 
198 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE register. */
199 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_RESET 0x00000000
200 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE register from the beginning of the component. */
201 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_OFST 0x0
202 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE register. */
203 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_OFST))
204 
205 /*
206  * Register : enable_set
207  *
208  * Sets Master Region Enable field when written with 1
209  *
210  * Register Layout
211  *
212  * Bits | Access | Reset | Description
213  * :-------|:-------|:------|:------------------------------------------------------
214  * [0] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE
215  * [1] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE
216  * [2] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE
217  * [3] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE
218  * [31:4] | ??? | 0x0 | *UNDEFINED*
219  *
220  */
221 /*
222  * Field : region0enable
223  *
224  * Region 0 Enable Set.
225  *
226  * Writing zero has no effect
227  *
228  * Writing one will set the region0enable bit to one
229  *
230  * Field Access Macros:
231  *
232  */
233 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field. */
234 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_LSB 0
235 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field. */
236 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_MSB 0
237 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field. */
238 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_WIDTH 1
239 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field value. */
240 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_SET_MSK 0x00000001
241 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field value. */
242 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_CLR_MSK 0xfffffffe
243 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field. */
244 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_RESET 0x0
245 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE field value from a register. */
246 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
247 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE register field value suitable for setting the register. */
248 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
249 
250 /*
251  * Field : region1enable
252  *
253  * Region 1 Enable Set.
254  *
255  * Writing zero has no effect
256  *
257  * Writing one will set the region1enable bit to one
258  *
259  * Field Access Macros:
260  *
261  */
262 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field. */
263 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_LSB 1
264 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field. */
265 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_MSB 1
266 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field. */
267 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_WIDTH 1
268 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field value. */
269 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_SET_MSK 0x00000002
270 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field value. */
271 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_CLR_MSK 0xfffffffd
272 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field. */
273 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_RESET 0x0
274 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE field value from a register. */
275 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
276 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE register field value suitable for setting the register. */
277 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
278 
279 /*
280  * Field : region2enable
281  *
282  * Region 2 Enable Set.
283  *
284  * Writing zero has no effect
285  *
286  * Writing one will set the region2enable bit to one
287  *
288  * Field Access Macros:
289  *
290  */
291 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field. */
292 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_LSB 2
293 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field. */
294 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_MSB 2
295 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field. */
296 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_WIDTH 1
297 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field value. */
298 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_SET_MSK 0x00000004
299 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field value. */
300 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_CLR_MSK 0xfffffffb
301 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field. */
302 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_RESET 0x0
303 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE field value from a register. */
304 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
305 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE register field value suitable for setting the register. */
306 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
307 
308 /*
309  * Field : region3enable
310  *
311  * Region 3 Enable Set.
312  *
313  * Writing zero has no effect
314  *
315  * Writing one will set the region3enable bit to one
316  *
317  * Field Access Macros:
318  *
319  */
320 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field. */
321 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_LSB 3
322 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field. */
323 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_MSB 3
324 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field. */
325 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_WIDTH 1
326 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field value. */
327 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_SET_MSK 0x00000008
328 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field value. */
329 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_CLR_MSK 0xfffffff7
330 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field. */
331 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_RESET 0x0
332 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE field value from a register. */
333 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
334 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE register field value suitable for setting the register. */
335 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
336 
337 #ifndef __ASSEMBLY__
338 /*
339  * WARNING: The C register and register group struct declarations are provided for
340  * convenience and illustrative purposes. They should, however, be used with
341  * caution as the C language standard provides no guarantees about the alignment or
342  * atomicity of device memory accesses. The recommended practice for coding device
343  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
344  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
345  * alt_write_dword() functions for 64 bit registers.
346  *
347  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET.
348  */
349 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_s
350 {
351  volatile uint32_t region0enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION0ENABLE */
352  volatile uint32_t region1enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION1ENABLE */
353  volatile uint32_t region2enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION2ENABLE */
354  volatile uint32_t region3enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_REGION3ENABLE */
355  uint32_t : 28; /* *UNDEFINED* */
356 };
357 
358 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET. */
359 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_t;
360 #endif /* __ASSEMBLY__ */
361 
362 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET register. */
363 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_RESET 0x00000000
364 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET register from the beginning of the component. */
365 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_OFST 0x4
366 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET register. */
367 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_OFST))
368 
369 /*
370  * Register : enable_clear
371  *
372  * Clears Master Region Enable field when written with 1
373  *
374  * Register Layout
375  *
376  * Bits | Access | Reset | Description
377  * :-------|:-------|:------|:--------------------------------------------------------
378  * [0] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE
379  * [1] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE
380  * [2] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE
381  * [3] | W | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE
382  * [31:4] | ??? | 0x0 | *UNDEFINED*
383  *
384  */
385 /*
386  * Field : region0enable
387  *
388  * Region 0 Enable Clear.
389  *
390  * Writing zero has no effect
391  *
392  * Writing one will clear the region0enable bit to zero
393  *
394  * Field Access Macros:
395  *
396  */
397 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field. */
398 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_LSB 0
399 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field. */
400 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_MSB 0
401 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field. */
402 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_WIDTH 1
403 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field value. */
404 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_SET_MSK 0x00000001
405 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field value. */
406 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_CLR_MSK 0xfffffffe
407 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field. */
408 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_RESET 0x0
409 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE field value from a register. */
410 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
411 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE register field value suitable for setting the register. */
412 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
413 
414 /*
415  * Field : region1enable
416  *
417  * Region 1 Enable Clear.
418  *
419  * Writing zero has no effect
420  *
421  * Writing one will clear the region1enable bit to zero
422  *
423  * Field Access Macros:
424  *
425  */
426 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field. */
427 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_LSB 1
428 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field. */
429 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_MSB 1
430 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field. */
431 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_WIDTH 1
432 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field value. */
433 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_SET_MSK 0x00000002
434 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field value. */
435 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_CLR_MSK 0xfffffffd
436 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field. */
437 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_RESET 0x0
438 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE field value from a register. */
439 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
440 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE register field value suitable for setting the register. */
441 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
442 
443 /*
444  * Field : region2enable
445  *
446  * Region 2 Enable Clear.
447  *
448  * Writing zero has no effect
449  *
450  * Writing one will clear the region2enable bit to zero
451  *
452  * Field Access Macros:
453  *
454  */
455 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field. */
456 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_LSB 2
457 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field. */
458 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_MSB 2
459 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field. */
460 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_WIDTH 1
461 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field value. */
462 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_SET_MSK 0x00000004
463 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field value. */
464 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_CLR_MSK 0xfffffffb
465 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field. */
466 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_RESET 0x0
467 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE field value from a register. */
468 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
469 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE register field value suitable for setting the register. */
470 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
471 
472 /*
473  * Field : region3enable
474  *
475  * Region 3 Enable Clear.
476  *
477  * Writing zero has no effect
478  *
479  * Writing one will clear the region3enable bit to zero
480  *
481  * Field Access Macros:
482  *
483  */
484 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field. */
485 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_LSB 3
486 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field. */
487 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_MSB 3
488 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field. */
489 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_WIDTH 1
490 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field value. */
491 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_SET_MSK 0x00000008
492 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field value. */
493 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_CLR_MSK 0xfffffff7
494 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field. */
495 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_RESET 0x0
496 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE field value from a register. */
497 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
498 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE register field value suitable for setting the register. */
499 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
500 
501 #ifndef __ASSEMBLY__
502 /*
503  * WARNING: The C register and register group struct declarations are provided for
504  * convenience and illustrative purposes. They should, however, be used with
505  * caution as the C language standard provides no guarantees about the alignment or
506  * atomicity of device memory accesses. The recommended practice for coding device
507  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
508  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
509  * alt_write_dword() functions for 64 bit registers.
510  *
511  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR.
512  */
513 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_s
514 {
515  volatile uint32_t region0enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION0ENABLE */
516  volatile uint32_t region1enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION1ENABLE */
517  volatile uint32_t region2enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION2ENABLE */
518  volatile uint32_t region3enable : 1; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_REGION3ENABLE */
519  uint32_t : 28; /* *UNDEFINED* */
520 };
521 
522 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR. */
523 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_t;
524 #endif /* __ASSEMBLY__ */
525 
526 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR register. */
527 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_RESET 0x00000000
528 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR register from the beginning of the component. */
529 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_OFST 0x8
530 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR register. */
531 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_OFST))
532 
533 /*
534  * Register : region0addr_base
535  *
536  * Base definition for Region 0
537  *
538  * Register Layout
539  *
540  * Bits | Access | Reset | Description
541  * :--------|:-------|:------|:---------------------------------------------------
542  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW
543  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH
544  *
545  */
546 /*
547  * Field : low
548  *
549  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
550  *
551  * Field Access Macros:
552  *
553  */
554 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field. */
555 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_LSB 0
556 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field. */
557 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_MSB 15
558 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field. */
559 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_WIDTH 16
560 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field value. */
561 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_SET_MSK 0x0000ffff
562 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field value. */
563 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_CLR_MSK 0xffff0000
564 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field. */
565 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_RESET 0x0
566 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW field value from a register. */
567 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
568 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW register field value suitable for setting the register. */
569 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
570 
571 /*
572  * Field : high
573  *
574  * defines the 16 bit MSB of the base address field.
575  *
576  * Field Access Macros:
577  *
578  */
579 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field. */
580 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_LSB 16
581 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field. */
582 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_MSB 31
583 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field. */
584 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_WIDTH 16
585 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field value. */
586 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_SET_MSK 0xffff0000
587 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field value. */
588 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
589 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field. */
590 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_RESET 0x0
591 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH field value from a register. */
592 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
593 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH register field value suitable for setting the register. */
594 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
595 
596 #ifndef __ASSEMBLY__
597 /*
598  * WARNING: The C register and register group struct declarations are provided for
599  * convenience and illustrative purposes. They should, however, be used with
600  * caution as the C language standard provides no guarantees about the alignment or
601  * atomicity of device memory accesses. The recommended practice for coding device
602  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
603  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
604  * alt_write_dword() functions for 64 bit registers.
605  *
606  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE.
607  */
608 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_s
609 {
610  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_LOW */
611  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_HIGH */
612 };
613 
614 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE. */
615 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_t;
616 #endif /* __ASSEMBLY__ */
617 
618 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE register. */
619 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_RESET 0x00000000
620 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE register from the beginning of the component. */
621 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_OFST 0x10
622 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE register. */
623 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_OFST))
624 
625 /*
626  * Register : region0addr_baseext
627  *
628  * base extended definition for Region 0
629  *
630  * Register Layout
631  *
632  * Bits | Access | Reset | Description
633  * :-------|:-------|:------|:-----------------------------------------------------
634  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW
635  * [31:5] | ??? | 0x0 | *UNDEFINED*
636  *
637  */
638 /*
639  * Field : low
640  *
641  * defines the 5 bit LSB of the base extended address field.
642  *
643  * Field Access Macros:
644  *
645  */
646 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field. */
647 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_LSB 0
648 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field. */
649 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_MSB 4
650 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field. */
651 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_WIDTH 5
652 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field value. */
653 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
654 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field value. */
655 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
656 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field. */
657 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_RESET 0x0
658 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW field value from a register. */
659 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
660 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW register field value suitable for setting the register. */
661 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
662 
663 #ifndef __ASSEMBLY__
664 /*
665  * WARNING: The C register and register group struct declarations are provided for
666  * convenience and illustrative purposes. They should, however, be used with
667  * caution as the C language standard provides no guarantees about the alignment or
668  * atomicity of device memory accesses. The recommended practice for coding device
669  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
670  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
671  * alt_write_dword() functions for 64 bit registers.
672  *
673  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT.
674  */
675 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_s
676 {
677  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_LOW */
678  uint32_t : 27; /* *UNDEFINED* */
679 };
680 
681 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT. */
682 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_t;
683 #endif /* __ASSEMBLY__ */
684 
685 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT register. */
686 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_RESET 0x00000000
687 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT register from the beginning of the component. */
688 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_OFST 0x14
689 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT register. */
690 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_OFST))
691 
692 /*
693  * Register : region0addr_limit
694  *
695  * Limit definition for Region 0
696  *
697  * Register Layout
698  *
699  * Bits | Access | Reset | Description
700  * :--------|:-------|:-------|:----------------------------------------------------
701  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW
702  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH
703  *
704  */
705 /*
706  * Field : low
707  *
708  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
709  *
710  * Field Access Macros:
711  *
712  */
713 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field. */
714 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_LSB 0
715 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field. */
716 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_MSB 15
717 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field. */
718 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_WIDTH 16
719 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field value. */
720 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
721 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field value. */
722 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
723 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field. */
724 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_RESET 0xffff
725 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW field value from a register. */
726 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
727 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW register field value suitable for setting the register. */
728 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
729 
730 /*
731  * Field : high
732  *
733  * defines the 16 bit MSB of the limit address field.
734  *
735  * Field Access Macros:
736  *
737  */
738 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field. */
739 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_LSB 16
740 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field. */
741 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_MSB 31
742 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field. */
743 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_WIDTH 16
744 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field value. */
745 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
746 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field value. */
747 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
748 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field. */
749 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_RESET 0x0
750 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH field value from a register. */
751 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
752 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH register field value suitable for setting the register. */
753 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
754 
755 #ifndef __ASSEMBLY__
756 /*
757  * WARNING: The C register and register group struct declarations are provided for
758  * convenience and illustrative purposes. They should, however, be used with
759  * caution as the C language standard provides no guarantees about the alignment or
760  * atomicity of device memory accesses. The recommended practice for coding device
761  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
762  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
763  * alt_write_dword() functions for 64 bit registers.
764  *
765  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT.
766  */
767 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_s
768 {
769  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_LOW */
770  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_HIGH */
771 };
772 
773 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT. */
774 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_t;
775 #endif /* __ASSEMBLY__ */
776 
777 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT register. */
778 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_RESET 0x0000ffff
779 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT register from the beginning of the component. */
780 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_OFST 0x18
781 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT register. */
782 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_OFST))
783 
784 /*
785  * Register : region0addr_limitext
786  *
787  * limit extended definition for Region 0
788  *
789  * Register Layout
790  *
791  * Bits | Access | Reset | Description
792  * :-------|:-------|:------|:------------------------------------------------------
793  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW
794  * [31:5] | ??? | 0x0 | *UNDEFINED*
795  *
796  */
797 /*
798  * Field : low
799  *
800  * defines the 5 bit LSB of the limit extended address field.
801  *
802  * Field Access Macros:
803  *
804  */
805 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field. */
806 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_LSB 0
807 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field. */
808 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_MSB 4
809 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field. */
810 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_WIDTH 5
811 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field value. */
812 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
813 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field value. */
814 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
815 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field. */
816 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_RESET 0x0
817 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW field value from a register. */
818 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
819 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
820 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
821 
822 #ifndef __ASSEMBLY__
823 /*
824  * WARNING: The C register and register group struct declarations are provided for
825  * convenience and illustrative purposes. They should, however, be used with
826  * caution as the C language standard provides no guarantees about the alignment or
827  * atomicity of device memory accesses. The recommended practice for coding device
828  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
829  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
830  * alt_write_dword() functions for 64 bit registers.
831  *
832  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT.
833  */
834 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_s
835 {
836  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_LOW */
837  uint32_t : 27; /* *UNDEFINED* */
838 };
839 
840 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT. */
841 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_t;
842 #endif /* __ASSEMBLY__ */
843 
844 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT register. */
845 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_RESET 0x00000000
846 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT register from the beginning of the component. */
847 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_OFST 0x1c
848 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT register. */
849 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_OFST))
850 
851 /*
852  * Register : region1addr_base
853  *
854  * Base definition for Region 1
855  *
856  * Register Layout
857  *
858  * Bits | Access | Reset | Description
859  * :--------|:-------|:------|:---------------------------------------------------
860  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW
861  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH
862  *
863  */
864 /*
865  * Field : low
866  *
867  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
868  *
869  * Field Access Macros:
870  *
871  */
872 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field. */
873 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_LSB 0
874 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field. */
875 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_MSB 15
876 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field. */
877 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_WIDTH 16
878 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field value. */
879 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_SET_MSK 0x0000ffff
880 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field value. */
881 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_CLR_MSK 0xffff0000
882 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field. */
883 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_RESET 0x0
884 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW field value from a register. */
885 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
886 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW register field value suitable for setting the register. */
887 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
888 
889 /*
890  * Field : high
891  *
892  * defines the 16 bit MSB of the base address field.
893  *
894  * Field Access Macros:
895  *
896  */
897 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field. */
898 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_LSB 16
899 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field. */
900 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_MSB 31
901 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field. */
902 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_WIDTH 16
903 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field value. */
904 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_SET_MSK 0xffff0000
905 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field value. */
906 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
907 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field. */
908 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_RESET 0x0
909 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH field value from a register. */
910 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
911 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH register field value suitable for setting the register. */
912 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
913 
914 #ifndef __ASSEMBLY__
915 /*
916  * WARNING: The C register and register group struct declarations are provided for
917  * convenience and illustrative purposes. They should, however, be used with
918  * caution as the C language standard provides no guarantees about the alignment or
919  * atomicity of device memory accesses. The recommended practice for coding device
920  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
921  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
922  * alt_write_dword() functions for 64 bit registers.
923  *
924  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE.
925  */
926 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_s
927 {
928  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_LOW */
929  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_HIGH */
930 };
931 
932 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE. */
933 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_t;
934 #endif /* __ASSEMBLY__ */
935 
936 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE register. */
937 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_RESET 0x00000000
938 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE register from the beginning of the component. */
939 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_OFST 0x20
940 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE register. */
941 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_OFST))
942 
943 /*
944  * Register : region1addr_baseext
945  *
946  * base extended definition for Region 1
947  *
948  * Register Layout
949  *
950  * Bits | Access | Reset | Description
951  * :-------|:-------|:------|:-----------------------------------------------------
952  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW
953  * [31:5] | ??? | 0x0 | *UNDEFINED*
954  *
955  */
956 /*
957  * Field : low
958  *
959  * defines the 5 bit LSB of the base extended address field.
960  *
961  * Field Access Macros:
962  *
963  */
964 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field. */
965 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_LSB 0
966 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field. */
967 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_MSB 4
968 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field. */
969 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_WIDTH 5
970 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field value. */
971 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
972 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field value. */
973 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
974 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field. */
975 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_RESET 0x0
976 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW field value from a register. */
977 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
978 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW register field value suitable for setting the register. */
979 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
980 
981 #ifndef __ASSEMBLY__
982 /*
983  * WARNING: The C register and register group struct declarations are provided for
984  * convenience and illustrative purposes. They should, however, be used with
985  * caution as the C language standard provides no guarantees about the alignment or
986  * atomicity of device memory accesses. The recommended practice for coding device
987  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
988  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
989  * alt_write_dword() functions for 64 bit registers.
990  *
991  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT.
992  */
993 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_s
994 {
995  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_LOW */
996  uint32_t : 27; /* *UNDEFINED* */
997 };
998 
999 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT. */
1000 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_t;
1001 #endif /* __ASSEMBLY__ */
1002 
1003 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT register. */
1004 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_RESET 0x00000000
1005 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT register from the beginning of the component. */
1006 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_OFST 0x24
1007 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT register. */
1008 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_OFST))
1009 
1010 /*
1011  * Register : region1addr_limit
1012  *
1013  * Limit definition for Region 1
1014  *
1015  * Register Layout
1016  *
1017  * Bits | Access | Reset | Description
1018  * :--------|:-------|:-------|:----------------------------------------------------
1019  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW
1020  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH
1021  *
1022  */
1023 /*
1024  * Field : low
1025  *
1026  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
1027  *
1028  * Field Access Macros:
1029  *
1030  */
1031 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field. */
1032 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_LSB 0
1033 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field. */
1034 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_MSB 15
1035 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field. */
1036 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_WIDTH 16
1037 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field value. */
1038 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
1039 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field value. */
1040 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
1041 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field. */
1042 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_RESET 0xffff
1043 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW field value from a register. */
1044 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1045 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW register field value suitable for setting the register. */
1046 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1047 
1048 /*
1049  * Field : high
1050  *
1051  * defines the 16 bit MSB of the limit address field.
1052  *
1053  * Field Access Macros:
1054  *
1055  */
1056 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field. */
1057 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_LSB 16
1058 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field. */
1059 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_MSB 31
1060 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field. */
1061 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_WIDTH 16
1062 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field value. */
1063 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
1064 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field value. */
1065 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
1066 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field. */
1067 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_RESET 0x0
1068 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH field value from a register. */
1069 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1070 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH register field value suitable for setting the register. */
1071 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1072 
1073 #ifndef __ASSEMBLY__
1074 /*
1075  * WARNING: The C register and register group struct declarations are provided for
1076  * convenience and illustrative purposes. They should, however, be used with
1077  * caution as the C language standard provides no guarantees about the alignment or
1078  * atomicity of device memory accesses. The recommended practice for coding device
1079  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1080  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1081  * alt_write_dword() functions for 64 bit registers.
1082  *
1083  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT.
1084  */
1085 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_s
1086 {
1087  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_LOW */
1088  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_HIGH */
1089 };
1090 
1091 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT. */
1092 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_t;
1093 #endif /* __ASSEMBLY__ */
1094 
1095 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT register. */
1096 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_RESET 0x0000ffff
1097 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT register from the beginning of the component. */
1098 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_OFST 0x28
1099 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT register. */
1100 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_OFST))
1101 
1102 /*
1103  * Register : region1addr_limitext
1104  *
1105  * limit extended definition for Region 1
1106  *
1107  * Register Layout
1108  *
1109  * Bits | Access | Reset | Description
1110  * :-------|:-------|:------|:------------------------------------------------------
1111  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW
1112  * [31:5] | ??? | 0x0 | *UNDEFINED*
1113  *
1114  */
1115 /*
1116  * Field : low
1117  *
1118  * defines the 5 bit LSB of the limit extended address field.
1119  *
1120  * Field Access Macros:
1121  *
1122  */
1123 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field. */
1124 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_LSB 0
1125 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field. */
1126 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_MSB 4
1127 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field. */
1128 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_WIDTH 5
1129 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field value. */
1130 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
1131 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field value. */
1132 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
1133 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field. */
1134 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_RESET 0x0
1135 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW field value from a register. */
1136 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1137 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
1138 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1139 
1140 #ifndef __ASSEMBLY__
1141 /*
1142  * WARNING: The C register and register group struct declarations are provided for
1143  * convenience and illustrative purposes. They should, however, be used with
1144  * caution as the C language standard provides no guarantees about the alignment or
1145  * atomicity of device memory accesses. The recommended practice for coding device
1146  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1147  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1148  * alt_write_dword() functions for 64 bit registers.
1149  *
1150  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT.
1151  */
1152 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_s
1153 {
1154  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_LOW */
1155  uint32_t : 27; /* *UNDEFINED* */
1156 };
1157 
1158 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT. */
1159 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_t;
1160 #endif /* __ASSEMBLY__ */
1161 
1162 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT register. */
1163 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_RESET 0x00000000
1164 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT register from the beginning of the component. */
1165 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_OFST 0x2c
1166 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT register. */
1167 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_OFST))
1168 
1169 /*
1170  * Register : region2addr_base
1171  *
1172  * Base definition for Region 2
1173  *
1174  * Register Layout
1175  *
1176  * Bits | Access | Reset | Description
1177  * :--------|:-------|:------|:---------------------------------------------------
1178  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW
1179  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH
1180  *
1181  */
1182 /*
1183  * Field : low
1184  *
1185  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
1186  *
1187  * Field Access Macros:
1188  *
1189  */
1190 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field. */
1191 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_LSB 0
1192 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field. */
1193 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_MSB 15
1194 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field. */
1195 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_WIDTH 16
1196 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field value. */
1197 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_SET_MSK 0x0000ffff
1198 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field value. */
1199 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_CLR_MSK 0xffff0000
1200 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field. */
1201 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_RESET 0x0
1202 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW field value from a register. */
1203 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1204 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW register field value suitable for setting the register. */
1205 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1206 
1207 /*
1208  * Field : high
1209  *
1210  * defines the 16 bit MSB of the base address field.
1211  *
1212  * Field Access Macros:
1213  *
1214  */
1215 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field. */
1216 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_LSB 16
1217 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field. */
1218 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_MSB 31
1219 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field. */
1220 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_WIDTH 16
1221 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field value. */
1222 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_SET_MSK 0xffff0000
1223 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field value. */
1224 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1225 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field. */
1226 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_RESET 0x0
1227 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH field value from a register. */
1228 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1229 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH register field value suitable for setting the register. */
1230 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1231 
1232 #ifndef __ASSEMBLY__
1233 /*
1234  * WARNING: The C register and register group struct declarations are provided for
1235  * convenience and illustrative purposes. They should, however, be used with
1236  * caution as the C language standard provides no guarantees about the alignment or
1237  * atomicity of device memory accesses. The recommended practice for coding device
1238  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1239  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1240  * alt_write_dword() functions for 64 bit registers.
1241  *
1242  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE.
1243  */
1244 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_s
1245 {
1246  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_LOW */
1247  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_HIGH */
1248 };
1249 
1250 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE. */
1251 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_t;
1252 #endif /* __ASSEMBLY__ */
1253 
1254 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE register. */
1255 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_RESET 0x00000000
1256 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE register from the beginning of the component. */
1257 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_OFST 0x30
1258 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE register. */
1259 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_OFST))
1260 
1261 /*
1262  * Register : region2addr_baseext
1263  *
1264  * base extended definition for Region 2
1265  *
1266  * Register Layout
1267  *
1268  * Bits | Access | Reset | Description
1269  * :-------|:-------|:------|:-----------------------------------------------------
1270  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW
1271  * [31:5] | ??? | 0x0 | *UNDEFINED*
1272  *
1273  */
1274 /*
1275  * Field : low
1276  *
1277  * defines the 5 bit LSB of the base extended address field.
1278  *
1279  * Field Access Macros:
1280  *
1281  */
1282 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field. */
1283 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_LSB 0
1284 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field. */
1285 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_MSB 4
1286 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field. */
1287 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_WIDTH 5
1288 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field value. */
1289 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
1290 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field value. */
1291 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
1292 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field. */
1293 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_RESET 0x0
1294 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW field value from a register. */
1295 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1296 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW register field value suitable for setting the register. */
1297 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1298 
1299 #ifndef __ASSEMBLY__
1300 /*
1301  * WARNING: The C register and register group struct declarations are provided for
1302  * convenience and illustrative purposes. They should, however, be used with
1303  * caution as the C language standard provides no guarantees about the alignment or
1304  * atomicity of device memory accesses. The recommended practice for coding device
1305  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1306  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1307  * alt_write_dword() functions for 64 bit registers.
1308  *
1309  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT.
1310  */
1311 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_s
1312 {
1313  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_LOW */
1314  uint32_t : 27; /* *UNDEFINED* */
1315 };
1316 
1317 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT. */
1318 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_t;
1319 #endif /* __ASSEMBLY__ */
1320 
1321 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT register. */
1322 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_RESET 0x00000000
1323 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT register from the beginning of the component. */
1324 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_OFST 0x34
1325 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT register. */
1326 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_OFST))
1327 
1328 /*
1329  * Register : region2addr_limit
1330  *
1331  * Limit definition for Region 2
1332  *
1333  * Register Layout
1334  *
1335  * Bits | Access | Reset | Description
1336  * :--------|:-------|:-------|:----------------------------------------------------
1337  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW
1338  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH
1339  *
1340  */
1341 /*
1342  * Field : low
1343  *
1344  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
1345  *
1346  * Field Access Macros:
1347  *
1348  */
1349 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field. */
1350 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_LSB 0
1351 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field. */
1352 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_MSB 15
1353 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field. */
1354 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_WIDTH 16
1355 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field value. */
1356 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
1357 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field value. */
1358 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
1359 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field. */
1360 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_RESET 0xffff
1361 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW field value from a register. */
1362 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1363 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW register field value suitable for setting the register. */
1364 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1365 
1366 /*
1367  * Field : high
1368  *
1369  * defines the 16 bit MSB of the limit address field.
1370  *
1371  * Field Access Macros:
1372  *
1373  */
1374 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field. */
1375 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_LSB 16
1376 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field. */
1377 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_MSB 31
1378 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field. */
1379 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_WIDTH 16
1380 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field value. */
1381 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
1382 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field value. */
1383 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
1384 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field. */
1385 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_RESET 0x0
1386 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH field value from a register. */
1387 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1388 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH register field value suitable for setting the register. */
1389 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1390 
1391 #ifndef __ASSEMBLY__
1392 /*
1393  * WARNING: The C register and register group struct declarations are provided for
1394  * convenience and illustrative purposes. They should, however, be used with
1395  * caution as the C language standard provides no guarantees about the alignment or
1396  * atomicity of device memory accesses. The recommended practice for coding device
1397  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1398  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1399  * alt_write_dword() functions for 64 bit registers.
1400  *
1401  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT.
1402  */
1403 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_s
1404 {
1405  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_LOW */
1406  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_HIGH */
1407 };
1408 
1409 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT. */
1410 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_t;
1411 #endif /* __ASSEMBLY__ */
1412 
1413 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT register. */
1414 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_RESET 0x0000ffff
1415 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT register from the beginning of the component. */
1416 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_OFST 0x38
1417 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT register. */
1418 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_OFST))
1419 
1420 /*
1421  * Register : region2addr_limitext
1422  *
1423  * limit extended definition for Region 2
1424  *
1425  * Register Layout
1426  *
1427  * Bits | Access | Reset | Description
1428  * :-------|:-------|:------|:------------------------------------------------------
1429  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW
1430  * [31:5] | ??? | 0x0 | *UNDEFINED*
1431  *
1432  */
1433 /*
1434  * Field : low
1435  *
1436  * defines the 5 bit LSB of the limit extended address field.
1437  *
1438  * Field Access Macros:
1439  *
1440  */
1441 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field. */
1442 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_LSB 0
1443 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field. */
1444 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_MSB 4
1445 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field. */
1446 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_WIDTH 5
1447 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field value. */
1448 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
1449 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field value. */
1450 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
1451 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field. */
1452 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_RESET 0x0
1453 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW field value from a register. */
1454 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1455 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
1456 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1457 
1458 #ifndef __ASSEMBLY__
1459 /*
1460  * WARNING: The C register and register group struct declarations are provided for
1461  * convenience and illustrative purposes. They should, however, be used with
1462  * caution as the C language standard provides no guarantees about the alignment or
1463  * atomicity of device memory accesses. The recommended practice for coding device
1464  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1465  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1466  * alt_write_dword() functions for 64 bit registers.
1467  *
1468  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT.
1469  */
1470 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_s
1471 {
1472  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_LOW */
1473  uint32_t : 27; /* *UNDEFINED* */
1474 };
1475 
1476 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT. */
1477 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_t;
1478 #endif /* __ASSEMBLY__ */
1479 
1480 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT register. */
1481 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_RESET 0x00000000
1482 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT register from the beginning of the component. */
1483 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_OFST 0x3c
1484 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT register. */
1485 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_OFST))
1486 
1487 /*
1488  * Register : region3addr_base
1489  *
1490  * Base definition for Region 3
1491  *
1492  * Register Layout
1493  *
1494  * Bits | Access | Reset | Description
1495  * :--------|:-------|:------|:---------------------------------------------------
1496  * [15:0] | R | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW
1497  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH
1498  *
1499  */
1500 /*
1501  * Field : low
1502  *
1503  * LSB field is all zeros. Region start address is {baseext,base, 16'h000}
1504  *
1505  * Field Access Macros:
1506  *
1507  */
1508 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field. */
1509 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_LSB 0
1510 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field. */
1511 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_MSB 15
1512 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field. */
1513 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_WIDTH 16
1514 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field value. */
1515 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_SET_MSK 0x0000ffff
1516 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field value. */
1517 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_CLR_MSK 0xffff0000
1518 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field. */
1519 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_RESET 0x0
1520 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW field value from a register. */
1521 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1522 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW register field value suitable for setting the register. */
1523 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1524 
1525 /*
1526  * Field : high
1527  *
1528  * defines the 16 bit MSB of the base address field.
1529  *
1530  * Field Access Macros:
1531  *
1532  */
1533 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field. */
1534 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_LSB 16
1535 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field. */
1536 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_MSB 31
1537 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field. */
1538 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_WIDTH 16
1539 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field value. */
1540 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_SET_MSK 0xffff0000
1541 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field value. */
1542 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1543 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field. */
1544 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_RESET 0x0
1545 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH field value from a register. */
1546 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1547 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH register field value suitable for setting the register. */
1548 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1549 
1550 #ifndef __ASSEMBLY__
1551 /*
1552  * WARNING: The C register and register group struct declarations are provided for
1553  * convenience and illustrative purposes. They should, however, be used with
1554  * caution as the C language standard provides no guarantees about the alignment or
1555  * atomicity of device memory accesses. The recommended practice for coding device
1556  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1557  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1558  * alt_write_dword() functions for 64 bit registers.
1559  *
1560  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE.
1561  */
1562 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_s
1563 {
1564  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_LOW */
1565  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_HIGH */
1566 };
1567 
1568 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE. */
1569 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_t;
1570 #endif /* __ASSEMBLY__ */
1571 
1572 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE register. */
1573 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_RESET 0x00000000
1574 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE register from the beginning of the component. */
1575 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_OFST 0x40
1576 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE register. */
1577 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_OFST))
1578 
1579 /*
1580  * Register : region3addr_baseext
1581  *
1582  * base extended definition for Region 3
1583  *
1584  * Register Layout
1585  *
1586  * Bits | Access | Reset | Description
1587  * :-------|:-------|:------|:-----------------------------------------------------
1588  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW
1589  * [31:5] | ??? | 0x0 | *UNDEFINED*
1590  *
1591  */
1592 /*
1593  * Field : low
1594  *
1595  * defines the 5 bit LSB of the base extended address field.
1596  *
1597  * Field Access Macros:
1598  *
1599  */
1600 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field. */
1601 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_LSB 0
1602 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field. */
1603 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_MSB 4
1604 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field. */
1605 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_WIDTH 5
1606 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field value. */
1607 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
1608 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field value. */
1609 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
1610 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field. */
1611 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_RESET 0x0
1612 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW field value from a register. */
1613 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1614 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW register field value suitable for setting the register. */
1615 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1616 
1617 #ifndef __ASSEMBLY__
1618 /*
1619  * WARNING: The C register and register group struct declarations are provided for
1620  * convenience and illustrative purposes. They should, however, be used with
1621  * caution as the C language standard provides no guarantees about the alignment or
1622  * atomicity of device memory accesses. The recommended practice for coding device
1623  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1624  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1625  * alt_write_dword() functions for 64 bit registers.
1626  *
1627  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT.
1628  */
1629 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_s
1630 {
1631  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_LOW */
1632  uint32_t : 27; /* *UNDEFINED* */
1633 };
1634 
1635 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT. */
1636 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_t;
1637 #endif /* __ASSEMBLY__ */
1638 
1639 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT register. */
1640 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_RESET 0x00000000
1641 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT register from the beginning of the component. */
1642 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_OFST 0x44
1643 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT register. */
1644 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_OFST))
1645 
1646 /*
1647  * Register : region3addr_limit
1648  *
1649  * Limit definition for Region 3
1650  *
1651  * Register Layout
1652  *
1653  * Bits | Access | Reset | Description
1654  * :--------|:-------|:-------|:----------------------------------------------------
1655  * [15:0] | R | 0xffff | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW
1656  * [31:16] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH
1657  *
1658  */
1659 /*
1660  * Field : low
1661  *
1662  * LSB field is all one. Region end address is {limitext,limit, 16'hFFFF}
1663  *
1664  * Field Access Macros:
1665  *
1666  */
1667 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field. */
1668 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_LSB 0
1669 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field. */
1670 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_MSB 15
1671 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field. */
1672 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_WIDTH 16
1673 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field value. */
1674 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
1675 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field value. */
1676 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
1677 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field. */
1678 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_RESET 0xffff
1679 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW field value from a register. */
1680 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1681 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW register field value suitable for setting the register. */
1682 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1683 
1684 /*
1685  * Field : high
1686  *
1687  * defines the 16 bit MSB of the limit address field.
1688  *
1689  * Field Access Macros:
1690  *
1691  */
1692 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field. */
1693 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_LSB 16
1694 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field. */
1695 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_MSB 31
1696 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field. */
1697 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_WIDTH 16
1698 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field value. */
1699 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
1700 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field value. */
1701 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
1702 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field. */
1703 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_RESET 0x0
1704 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH field value from a register. */
1705 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1706 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH register field value suitable for setting the register. */
1707 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1708 
1709 #ifndef __ASSEMBLY__
1710 /*
1711  * WARNING: The C register and register group struct declarations are provided for
1712  * convenience and illustrative purposes. They should, however, be used with
1713  * caution as the C language standard provides no guarantees about the alignment or
1714  * atomicity of device memory accesses. The recommended practice for coding device
1715  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1716  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1717  * alt_write_dword() functions for 64 bit registers.
1718  *
1719  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT.
1720  */
1721 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_s
1722 {
1723  const volatile uint32_t low : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_LOW */
1724  volatile uint32_t high : 16; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_HIGH */
1725 };
1726 
1727 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT. */
1728 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_t;
1729 #endif /* __ASSEMBLY__ */
1730 
1731 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT register. */
1732 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_RESET 0x0000ffff
1733 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT register from the beginning of the component. */
1734 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_OFST 0x48
1735 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT register. */
1736 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_OFST))
1737 
1738 /*
1739  * Register : region3addr_limitext
1740  *
1741  * limit extended definition for Region 3
1742  *
1743  * Register Layout
1744  *
1745  * Bits | Access | Reset | Description
1746  * :-------|:-------|:------|:------------------------------------------------------
1747  * [4:0] | RW | 0x0 | ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW
1748  * [31:5] | ??? | 0x0 | *UNDEFINED*
1749  *
1750  */
1751 /*
1752  * Field : low
1753  *
1754  * defines the 5 bit LSB of the limit extended address field.
1755  *
1756  * Field Access Macros:
1757  *
1758  */
1759 /* The Least Significant Bit (LSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field. */
1760 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_LSB 0
1761 /* The Most Significant Bit (MSB) position of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field. */
1762 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_MSB 4
1763 /* The width in bits of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field. */
1764 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_WIDTH 5
1765 /* The mask used to set the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field value. */
1766 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
1767 /* The mask used to clear the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field value. */
1768 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
1769 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field. */
1770 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_RESET 0x0
1771 /* Extracts the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW field value from a register. */
1772 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1773 /* Produces a ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW register field value suitable for setting the register. */
1774 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1775 
1776 #ifndef __ASSEMBLY__
1777 /*
1778  * WARNING: The C register and register group struct declarations are provided for
1779  * convenience and illustrative purposes. They should, however, be used with
1780  * caution as the C language standard provides no guarantees about the alignment or
1781  * atomicity of device memory accesses. The recommended practice for coding device
1782  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1783  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1784  * alt_write_dword() functions for 64 bit registers.
1785  *
1786  * The struct declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT.
1787  */
1788 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_s
1789 {
1790  volatile uint32_t low : 5; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_LOW */
1791  uint32_t : 27; /* *UNDEFINED* */
1792 };
1793 
1794 /* The typedef declaration for register ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT. */
1795 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_t;
1796 #endif /* __ASSEMBLY__ */
1797 
1798 /* The reset value of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT register. */
1799 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_RESET 0x00000000
1800 /* The byte offset of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT register from the beginning of the component. */
1801 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_OFST 0x4c
1802 /* The address of the ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT register. */
1803 #define ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_OFST))
1804 
1805 #ifndef __ASSEMBLY__
1806 /*
1807  * WARNING: The C register and register group struct declarations are provided for
1808  * convenience and illustrative purposes. They should, however, be used with
1809  * caution as the C language standard provides no guarantees about the alignment or
1810  * atomicity of device memory accesses. The recommended practice for coding device
1811  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1812  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1813  * alt_write_dword() functions for 64 bit registers.
1814  *
1815  * The struct declaration for register group ALT_SOC_NOC_FW_DDR_F2SDR_SCR.
1816  */
1817 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_s
1818 {
1819  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_t enable; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE */
1820  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET_t enable_set; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET */
1821  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR_t enable_clear; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR */
1822  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
1823  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE_t region0addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE */
1824  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT_t region0addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT */
1825  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT_t region0addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT */
1826  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT_t region0addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT */
1827  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE_t region1addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE */
1828  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT_t region1addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT */
1829  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT_t region1addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT */
1830  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT_t region1addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT */
1831  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE_t region2addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE */
1832  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT_t region2addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT */
1833  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT_t region2addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT */
1834  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT_t region2addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT */
1835  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE_t region3addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE */
1836  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT_t region3addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT */
1837  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT_t region3addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT */
1838  volatile ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT_t region3addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT */
1839  volatile uint32_t _pad_0x50_0x100[44]; /* *UNDEFINED* */
1840 };
1841 
1842 /* The typedef declaration for register group ALT_SOC_NOC_FW_DDR_F2SDR_SCR. */
1843 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_t;
1844 /* The struct declaration for the raw register contents of register group ALT_SOC_NOC_FW_DDR_F2SDR_SCR. */
1845 struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_raw_s
1846 {
1847  volatile uint32_t enable; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE */
1848  volatile uint32_t enable_set; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_SET */
1849  volatile uint32_t enable_clear; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_ENABLE_CLEAR */
1850  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
1851  volatile uint32_t region0addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASE */
1852  volatile uint32_t region0addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_BASEEXT */
1853  volatile uint32_t region0addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMIT */
1854  volatile uint32_t region0addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION0ADDR_LIMITEXT */
1855  volatile uint32_t region1addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASE */
1856  volatile uint32_t region1addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_BASEEXT */
1857  volatile uint32_t region1addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMIT */
1858  volatile uint32_t region1addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION1ADDR_LIMITEXT */
1859  volatile uint32_t region2addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASE */
1860  volatile uint32_t region2addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_BASEEXT */
1861  volatile uint32_t region2addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMIT */
1862  volatile uint32_t region2addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION2ADDR_LIMITEXT */
1863  volatile uint32_t region3addr_base; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASE */
1864  volatile uint32_t region3addr_baseext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_BASEEXT */
1865  volatile uint32_t region3addr_limit; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMIT */
1866  volatile uint32_t region3addr_limitext; /* ALT_SOC_NOC_FW_DDR_F2SDR_SCR_REGION3ADDR_LIMITEXT */
1867  volatile uint32_t _pad_0x50_0x100[44]; /* *UNDEFINED* */
1868 };
1869 
1870 /* The typedef declaration for the raw register contents of register group ALT_SOC_NOC_FW_DDR_F2SDR_SCR. */
1871 typedef struct ALT_SOC_NOC_FW_DDR_F2SDR_SCR_raw_s ALT_SOC_NOC_FW_DDR_F2SDR_SCR_raw_t;
1872 #endif /* __ASSEMBLY__ */
1873 
1874 
1875 #ifdef __cplusplus
1876 }
1877 #endif /* __cplusplus */
1878 #endif /* __ALT_SOCAL_SOC_NOC_FW_DDR_F2SDR_SCR_H__ */
1879