35 #ifndef __ALT_SOCAL_ECC_H__
36 #define __ALT_SOCAL_ECC_H__
76 #define ALT_ECC_IP_REV_ID_SIREV_LSB 0
78 #define ALT_ECC_IP_REV_ID_SIREV_MSB 15
80 #define ALT_ECC_IP_REV_ID_SIREV_WIDTH 16
82 #define ALT_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
84 #define ALT_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
86 #define ALT_ECC_IP_REV_ID_SIREV_RESET 0x0
88 #define ALT_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
90 #define ALT_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
104 struct ALT_ECC_IP_REV_ID_s
106 const volatile uint32_t SIREV : 16;
111 typedef struct ALT_ECC_IP_REV_ID_s ALT_ECC_IP_REV_ID_t;
115 #define ALT_ECC_IP_REV_ID_RESET 0x00000000
117 #define ALT_ECC_IP_REV_ID_OFST 0x0
119 #define ALT_ECC_IP_REV_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_IP_REV_ID_OFST))
154 #define ALT_ECC_IP_REV_ID2_ADDR_LSB 0
156 #define ALT_ECC_IP_REV_ID2_ADDR_MSB 4
158 #define ALT_ECC_IP_REV_ID2_ADDR_WIDTH 5
160 #define ALT_ECC_IP_REV_ID2_ADDR_SET_MSK 0x0000001f
162 #define ALT_ECC_IP_REV_ID2_ADDR_CLR_MSK 0xffffffe0
164 #define ALT_ECC_IP_REV_ID2_ADDR_RESET 0x0
166 #define ALT_ECC_IP_REV_ID2_ADDR_GET(value) (((value) & 0x0000001f) >> 0)
168 #define ALT_ECC_IP_REV_ID2_ADDR_SET(value) (((value) << 0) & 0x0000001f)
198 #define ALT_ECC_IP_REV_ID2_DAT_LSB 5
200 #define ALT_ECC_IP_REV_ID2_DAT_MSB 9
202 #define ALT_ECC_IP_REV_ID2_DAT_WIDTH 5
204 #define ALT_ECC_IP_REV_ID2_DAT_SET_MSK 0x000003e0
206 #define ALT_ECC_IP_REV_ID2_DAT_CLR_MSK 0xfffffc1f
208 #define ALT_ECC_IP_REV_ID2_DAT_RESET 0x0
210 #define ALT_ECC_IP_REV_ID2_DAT_GET(value) (((value) & 0x000003e0) >> 5)
212 #define ALT_ECC_IP_REV_ID2_DAT_SET(value) (((value) << 5) & 0x000003e0)
236 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_LSB 10
238 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_MSB 12
240 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_WIDTH 3
242 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_SET_MSK 0x00001c00
244 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_CLR_MSK 0xffffe3ff
246 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_RESET 0x0
248 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_GET(value) (((value) & 0x00001c00) >> 10)
250 #define ALT_ECC_IP_REV_ID2_ECC_SIZE_SET(value) (((value) << 10) & 0x00001c00)
269 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_LSB 13
271 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_MSB 15
273 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_WIDTH 3
275 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_SET_MSK 0x0000e000
277 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_CLR_MSK 0xffff1fff
279 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_RESET 0x0
281 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_GET(value) (((value) & 0x0000e000) >> 13)
283 #define ALT_ECC_IP_REV_ID2_RAM_TYPE_SET(value) (((value) << 13) & 0x0000e000)
304 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_LSB 16
306 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_MSB 19
308 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_WIDTH 4
310 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_SET_MSK 0x000f0000
312 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_CLR_MSK 0xfff0ffff
314 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_RESET 0x0
316 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_GET(value) (((value) & 0x000f0000) >> 16)
318 #define ALT_ECC_IP_REV_ID2_LUT_TBL_DEP_SET(value) (((value) << 16) & 0x000f0000)
332 struct ALT_ECC_IP_REV_ID2_s
334 const volatile uint32_t ADDR : 5;
335 const volatile uint32_t DAT : 5;
336 const volatile uint32_t ECC_SIZE : 3;
337 const volatile uint32_t RAM_TYPE : 3;
338 const volatile uint32_t LUT_TBL_DEP : 4;
343 typedef struct ALT_ECC_IP_REV_ID2_s ALT_ECC_IP_REV_ID2_t;
347 #define ALT_ECC_IP_REV_ID2_RESET 0x00000000
349 #define ALT_ECC_IP_REV_ID2_OFST 0x4
351 #define ALT_ECC_IP_REV_ID2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_IP_REV_ID2_OFST))
393 #define ALT_ECC_CTRL_ECC_EN_E_DISABLE 0x0
398 #define ALT_ECC_CTRL_ECC_EN_E_ENABLE 0x1
401 #define ALT_ECC_CTRL_ECC_EN_LSB 0
403 #define ALT_ECC_CTRL_ECC_EN_MSB 0
405 #define ALT_ECC_CTRL_ECC_EN_WIDTH 1
407 #define ALT_ECC_CTRL_ECC_EN_SET_MSK 0x00000001
409 #define ALT_ECC_CTRL_ECC_EN_CLR_MSK 0xfffffffe
411 #define ALT_ECC_CTRL_ECC_EN_RESET 0x0
413 #define ALT_ECC_CTRL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
415 #define ALT_ECC_CTRL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
437 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_E_DISABLE 0x0
442 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_E_ENABLE 0x1
445 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_LSB 1
447 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_MSB 1
449 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_WIDTH 1
451 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_SET_MSK 0x00000002
453 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_CLR_MSK 0xfffffffd
455 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_RESET 0x1
457 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_GET(value) (((value) & 0x00000002) >> 1)
459 #define ALT_ECC_CTRL_ECC_SLVERR_DIS_SET(value) (((value) << 1) & 0x00000002)
470 #define ALT_ECC_CTRL_CNT_RSTA_LSB 8
472 #define ALT_ECC_CTRL_CNT_RSTA_MSB 8
474 #define ALT_ECC_CTRL_CNT_RSTA_WIDTH 1
476 #define ALT_ECC_CTRL_CNT_RSTA_SET_MSK 0x00000100
478 #define ALT_ECC_CTRL_CNT_RSTA_CLR_MSK 0xfffffeff
480 #define ALT_ECC_CTRL_CNT_RSTA_RESET 0x0
482 #define ALT_ECC_CTRL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
484 #define ALT_ECC_CTRL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
495 #define ALT_ECC_CTRL_CNT_RSTB_LSB 9
497 #define ALT_ECC_CTRL_CNT_RSTB_MSB 9
499 #define ALT_ECC_CTRL_CNT_RSTB_WIDTH 1
501 #define ALT_ECC_CTRL_CNT_RSTB_SET_MSK 0x00000200
503 #define ALT_ECC_CTRL_CNT_RSTB_CLR_MSK 0xfffffdff
505 #define ALT_ECC_CTRL_CNT_RSTB_RESET 0x0
507 #define ALT_ECC_CTRL_CNT_RSTB_GET(value) (((value) & 0x00000200) >> 9)
509 #define ALT_ECC_CTRL_CNT_RSTB_SET(value) (((value) << 9) & 0x00000200)
520 #define ALT_ECC_CTRL_INITA_LSB 16
522 #define ALT_ECC_CTRL_INITA_MSB 16
524 #define ALT_ECC_CTRL_INITA_WIDTH 1
526 #define ALT_ECC_CTRL_INITA_SET_MSK 0x00010000
528 #define ALT_ECC_CTRL_INITA_CLR_MSK 0xfffeffff
530 #define ALT_ECC_CTRL_INITA_RESET 0x0
532 #define ALT_ECC_CTRL_INITA_GET(value) (((value) & 0x00010000) >> 16)
534 #define ALT_ECC_CTRL_INITA_SET(value) (((value) << 16) & 0x00010000)
545 #define ALT_ECC_CTRL_INITB_LSB 24
547 #define ALT_ECC_CTRL_INITB_MSB 24
549 #define ALT_ECC_CTRL_INITB_WIDTH 1
551 #define ALT_ECC_CTRL_INITB_SET_MSK 0x01000000
553 #define ALT_ECC_CTRL_INITB_CLR_MSK 0xfeffffff
555 #define ALT_ECC_CTRL_INITB_RESET 0x0
557 #define ALT_ECC_CTRL_INITB_GET(value) (((value) & 0x01000000) >> 24)
559 #define ALT_ECC_CTRL_INITB_SET(value) (((value) << 24) & 0x01000000)
573 struct ALT_ECC_CTRL_s
575 volatile uint32_t ECC_EN : 1;
576 volatile uint32_t ECC_SLVERR_DIS : 1;
578 volatile uint32_t CNT_RSTA : 1;
579 volatile uint32_t CNT_RSTB : 1;
581 volatile uint32_t INITA : 1;
583 volatile uint32_t INITB : 1;
588 typedef struct ALT_ECC_CTRL_s ALT_ECC_CTRL_t;
592 #define ALT_ECC_CTRL_RESET 0x00000002
594 #define ALT_ECC_CTRL_OFST 0x8
596 #define ALT_ECC_CTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_CTRL_OFST))
623 #define ALT_ECC_INITSTAT_INITCOMPLETEA_LSB 0
625 #define ALT_ECC_INITSTAT_INITCOMPLETEA_MSB 0
627 #define ALT_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
629 #define ALT_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
631 #define ALT_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
633 #define ALT_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
635 #define ALT_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
637 #define ALT_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
648 #define ALT_ECC_INITSTAT_INITCOMPLETEB_LSB 8
650 #define ALT_ECC_INITSTAT_INITCOMPLETEB_MSB 8
652 #define ALT_ECC_INITSTAT_INITCOMPLETEB_WIDTH 1
654 #define ALT_ECC_INITSTAT_INITCOMPLETEB_SET_MSK 0x00000100
656 #define ALT_ECC_INITSTAT_INITCOMPLETEB_CLR_MSK 0xfffffeff
658 #define ALT_ECC_INITSTAT_INITCOMPLETEB_RESET 0x0
660 #define ALT_ECC_INITSTAT_INITCOMPLETEB_GET(value) (((value) & 0x00000100) >> 8)
662 #define ALT_ECC_INITSTAT_INITCOMPLETEB_SET(value) (((value) << 8) & 0x00000100)
676 struct ALT_ECC_INITSTAT_s
678 volatile uint32_t INITCOMPLETEA : 1;
680 volatile uint32_t INITCOMPLETEB : 1;
685 typedef struct ALT_ECC_INITSTAT_s ALT_ECC_INITSTAT_t;
689 #define ALT_ECC_INITSTAT_RESET 0x00000000
691 #define ALT_ECC_INITSTAT_OFST 0xc
693 #define ALT_ECC_INITSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INITSTAT_OFST))
727 #define ALT_ECC_ERRINTEN_SERRINTEN_E_DISABLE 0x0
732 #define ALT_ECC_ERRINTEN_SERRINTEN_E_ENABLE 0x1
735 #define ALT_ECC_ERRINTEN_SERRINTEN_LSB 0
737 #define ALT_ECC_ERRINTEN_SERRINTEN_MSB 0
739 #define ALT_ECC_ERRINTEN_SERRINTEN_WIDTH 1
741 #define ALT_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
743 #define ALT_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
745 #define ALT_ECC_ERRINTEN_SERRINTEN_RESET 0x0
747 #define ALT_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
749 #define ALT_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
763 struct ALT_ECC_ERRINTEN_s
765 volatile uint32_t SERRINTEN : 1;
770 typedef struct ALT_ECC_ERRINTEN_s ALT_ECC_ERRINTEN_t;
774 #define ALT_ECC_ERRINTEN_RESET 0x00000000
776 #define ALT_ECC_ERRINTEN_OFST 0x10
778 #define ALT_ECC_ERRINTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTEN_OFST))
802 #define ALT_ECC_ERRINTENS_SERRINTS_LSB 0
804 #define ALT_ECC_ERRINTENS_SERRINTS_MSB 0
806 #define ALT_ECC_ERRINTENS_SERRINTS_WIDTH 1
808 #define ALT_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
810 #define ALT_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
812 #define ALT_ECC_ERRINTENS_SERRINTS_RESET 0x0
814 #define ALT_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
816 #define ALT_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
830 struct ALT_ECC_ERRINTENS_s
832 volatile uint32_t SERRINTS : 1;
837 typedef struct ALT_ECC_ERRINTENS_s ALT_ECC_ERRINTENS_t;
841 #define ALT_ECC_ERRINTENS_RESET 0x00000000
843 #define ALT_ECC_ERRINTENS_OFST 0x14
845 #define ALT_ECC_ERRINTENS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTENS_OFST))
869 #define ALT_ECC_ERRINTENR_SERRINTR_LSB 0
871 #define ALT_ECC_ERRINTENR_SERRINTR_MSB 0
873 #define ALT_ECC_ERRINTENR_SERRINTR_WIDTH 1
875 #define ALT_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
877 #define ALT_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
879 #define ALT_ECC_ERRINTENR_SERRINTR_RESET 0x0
881 #define ALT_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
883 #define ALT_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
897 struct ALT_ECC_ERRINTENR_s
899 volatile uint32_t SERRINTR : 1;
904 typedef struct ALT_ECC_ERRINTENR_s ALT_ECC_ERRINTENR_t;
908 #define ALT_ECC_ERRINTENR_RESET 0x00000000
910 #define ALT_ECC_ERRINTENR_OFST 0x18
912 #define ALT_ECC_ERRINTENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ERRINTENR_OFST))
953 #define ALT_ECC_INTMODE_INTMODE_E_INTR_ALL_ERR 0x0
961 #define ALT_ECC_INTMODE_INTMODE_E_INTR_DIST_ERR 0x1
964 #define ALT_ECC_INTMODE_INTMODE_LSB 0
966 #define ALT_ECC_INTMODE_INTMODE_MSB 0
968 #define ALT_ECC_INTMODE_INTMODE_WIDTH 1
970 #define ALT_ECC_INTMODE_INTMODE_SET_MSK 0x00000001
972 #define ALT_ECC_INTMODE_INTMODE_CLR_MSK 0xfffffffe
974 #define ALT_ECC_INTMODE_INTMODE_RESET 0x0
976 #define ALT_ECC_INTMODE_INTMODE_GET(value) (((value) & 0x00000001) >> 0)
978 #define ALT_ECC_INTMODE_INTMODE_SET(value) (((value) << 0) & 0x00000001)
1000 #define ALT_ECC_INTMODE_INTONOVF_E_DISABLE 0x0
1006 #define ALT_ECC_INTMODE_INTONOVF_E_ENABLE 0x1
1009 #define ALT_ECC_INTMODE_INTONOVF_LSB 8
1011 #define ALT_ECC_INTMODE_INTONOVF_MSB 8
1013 #define ALT_ECC_INTMODE_INTONOVF_WIDTH 1
1015 #define ALT_ECC_INTMODE_INTONOVF_SET_MSK 0x00000100
1017 #define ALT_ECC_INTMODE_INTONOVF_CLR_MSK 0xfffffeff
1019 #define ALT_ECC_INTMODE_INTONOVF_RESET 0x0
1021 #define ALT_ECC_INTMODE_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
1023 #define ALT_ECC_INTMODE_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
1045 #define ALT_ECC_INTMODE_INTONCMP_E_DISABLE 0x0
1051 #define ALT_ECC_INTMODE_INTONCMP_E_ENABLE 0x1
1054 #define ALT_ECC_INTMODE_INTONCMP_LSB 16
1056 #define ALT_ECC_INTMODE_INTONCMP_MSB 16
1058 #define ALT_ECC_INTMODE_INTONCMP_WIDTH 1
1060 #define ALT_ECC_INTMODE_INTONCMP_SET_MSK 0x00010000
1062 #define ALT_ECC_INTMODE_INTONCMP_CLR_MSK 0xfffeffff
1064 #define ALT_ECC_INTMODE_INTONCMP_RESET 0x0
1066 #define ALT_ECC_INTMODE_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
1068 #define ALT_ECC_INTMODE_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
1070 #ifndef __ASSEMBLY__
1082 struct ALT_ECC_INTMODE_s
1084 volatile uint32_t INTMODE : 1;
1086 volatile uint32_t INTONOVF : 1;
1088 volatile uint32_t INTONCMP : 1;
1093 typedef struct ALT_ECC_INTMODE_s ALT_ECC_INTMODE_t;
1097 #define ALT_ECC_INTMODE_RESET 0x00000000
1099 #define ALT_ECC_INTMODE_OFST 0x1c
1101 #define ALT_ECC_INTMODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTMODE_OFST))
1133 #define ALT_ECC_INTSTAT_SERRPENA_LSB 0
1135 #define ALT_ECC_INTSTAT_SERRPENA_MSB 0
1137 #define ALT_ECC_INTSTAT_SERRPENA_WIDTH 1
1139 #define ALT_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
1141 #define ALT_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
1143 #define ALT_ECC_INTSTAT_SERRPENA_RESET 0x0
1145 #define ALT_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
1147 #define ALT_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
1158 #define ALT_ECC_INTSTAT_DERRPENA_LSB 8
1160 #define ALT_ECC_INTSTAT_DERRPENA_MSB 8
1162 #define ALT_ECC_INTSTAT_DERRPENA_WIDTH 1
1164 #define ALT_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
1166 #define ALT_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
1168 #define ALT_ECC_INTSTAT_DERRPENA_RESET 0x0
1170 #define ALT_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
1172 #define ALT_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
1183 #define ALT_ECC_INTSTAT_SERRPENB_LSB 16
1185 #define ALT_ECC_INTSTAT_SERRPENB_MSB 16
1187 #define ALT_ECC_INTSTAT_SERRPENB_WIDTH 1
1189 #define ALT_ECC_INTSTAT_SERRPENB_SET_MSK 0x00010000
1191 #define ALT_ECC_INTSTAT_SERRPENB_CLR_MSK 0xfffeffff
1193 #define ALT_ECC_INTSTAT_SERRPENB_RESET 0x0
1195 #define ALT_ECC_INTSTAT_SERRPENB_GET(value) (((value) & 0x00010000) >> 16)
1197 #define ALT_ECC_INTSTAT_SERRPENB_SET(value) (((value) << 16) & 0x00010000)
1208 #define ALT_ECC_INTSTAT_DERRPENB_LSB 24
1210 #define ALT_ECC_INTSTAT_DERRPENB_MSB 24
1212 #define ALT_ECC_INTSTAT_DERRPENB_WIDTH 1
1214 #define ALT_ECC_INTSTAT_DERRPENB_SET_MSK 0x01000000
1216 #define ALT_ECC_INTSTAT_DERRPENB_CLR_MSK 0xfeffffff
1218 #define ALT_ECC_INTSTAT_DERRPENB_RESET 0x0
1220 #define ALT_ECC_INTSTAT_DERRPENB_GET(value) (((value) & 0x01000000) >> 24)
1222 #define ALT_ECC_INTSTAT_DERRPENB_SET(value) (((value) << 24) & 0x01000000)
1224 #ifndef __ASSEMBLY__
1236 struct ALT_ECC_INTSTAT_s
1238 volatile uint32_t SERRPENA : 1;
1240 volatile uint32_t DERRPENA : 1;
1242 volatile uint32_t SERRPENB : 1;
1244 volatile uint32_t DERRPENB : 1;
1249 typedef struct ALT_ECC_INTSTAT_s ALT_ECC_INTSTAT_t;
1253 #define ALT_ECC_INTSTAT_RESET 0x00000000
1255 #define ALT_ECC_INTSTAT_OFST 0x20
1257 #define ALT_ECC_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTSTAT_OFST))
1287 #define ALT_ECC_INTTEST_TSERRA_LSB 0
1289 #define ALT_ECC_INTTEST_TSERRA_MSB 0
1291 #define ALT_ECC_INTTEST_TSERRA_WIDTH 1
1293 #define ALT_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
1295 #define ALT_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
1297 #define ALT_ECC_INTTEST_TSERRA_RESET 0x0
1299 #define ALT_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
1301 #define ALT_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
1312 #define ALT_ECC_INTTEST_TDERRA_LSB 8
1314 #define ALT_ECC_INTTEST_TDERRA_MSB 8
1316 #define ALT_ECC_INTTEST_TDERRA_WIDTH 1
1318 #define ALT_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
1320 #define ALT_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
1322 #define ALT_ECC_INTTEST_TDERRA_RESET 0x0
1324 #define ALT_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
1326 #define ALT_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
1337 #define ALT_ECC_INTTEST_TSERRB_LSB 16
1339 #define ALT_ECC_INTTEST_TSERRB_MSB 16
1341 #define ALT_ECC_INTTEST_TSERRB_WIDTH 1
1343 #define ALT_ECC_INTTEST_TSERRB_SET_MSK 0x00010000
1345 #define ALT_ECC_INTTEST_TSERRB_CLR_MSK 0xfffeffff
1347 #define ALT_ECC_INTTEST_TSERRB_RESET 0x0
1349 #define ALT_ECC_INTTEST_TSERRB_GET(value) (((value) & 0x00010000) >> 16)
1351 #define ALT_ECC_INTTEST_TSERRB_SET(value) (((value) << 16) & 0x00010000)
1362 #define ALT_ECC_INTTEST_TDERRB_LSB 24
1364 #define ALT_ECC_INTTEST_TDERRB_MSB 24
1366 #define ALT_ECC_INTTEST_TDERRB_WIDTH 1
1368 #define ALT_ECC_INTTEST_TDERRB_SET_MSK 0x01000000
1370 #define ALT_ECC_INTTEST_TDERRB_CLR_MSK 0xfeffffff
1372 #define ALT_ECC_INTTEST_TDERRB_RESET 0x0
1374 #define ALT_ECC_INTTEST_TDERRB_GET(value) (((value) & 0x01000000) >> 24)
1376 #define ALT_ECC_INTTEST_TDERRB_SET(value) (((value) << 24) & 0x01000000)
1378 #ifndef __ASSEMBLY__
1390 struct ALT_ECC_INTTEST_s
1392 volatile uint32_t TSERRA : 1;
1394 volatile uint32_t TDERRA : 1;
1396 volatile uint32_t TSERRB : 1;
1398 volatile uint32_t TDERRB : 1;
1403 typedef struct ALT_ECC_INTTEST_s ALT_ECC_INTTEST_t;
1407 #define ALT_ECC_INTTEST_RESET 0x00000000
1409 #define ALT_ECC_INTTEST_OFST 0x24
1411 #define ALT_ECC_INTTEST_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_INTTEST_OFST))
1440 #define ALT_ECC_MODSTAT_CMPFLGA_LSB 0
1442 #define ALT_ECC_MODSTAT_CMPFLGA_MSB 0
1444 #define ALT_ECC_MODSTAT_CMPFLGA_WIDTH 1
1446 #define ALT_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
1448 #define ALT_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
1450 #define ALT_ECC_MODSTAT_CMPFLGA_RESET 0x0
1452 #define ALT_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
1454 #define ALT_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
1465 #define ALT_ECC_MODSTAT_CMPFLGB_LSB 1
1467 #define ALT_ECC_MODSTAT_CMPFLGB_MSB 1
1469 #define ALT_ECC_MODSTAT_CMPFLGB_WIDTH 1
1471 #define ALT_ECC_MODSTAT_CMPFLGB_SET_MSK 0x00000002
1473 #define ALT_ECC_MODSTAT_CMPFLGB_CLR_MSK 0xfffffffd
1475 #define ALT_ECC_MODSTAT_CMPFLGB_RESET 0x0
1477 #define ALT_ECC_MODSTAT_CMPFLGB_GET(value) (((value) & 0x00000002) >> 1)
1479 #define ALT_ECC_MODSTAT_CMPFLGB_SET(value) (((value) << 1) & 0x00000002)
1490 #define ALT_ECC_MODSTAT_RMW_SERRA_LSB 2
1492 #define ALT_ECC_MODSTAT_RMW_SERRA_MSB 2
1494 #define ALT_ECC_MODSTAT_RMW_SERRA_WIDTH 1
1496 #define ALT_ECC_MODSTAT_RMW_SERRA_SET_MSK 0x00000004
1498 #define ALT_ECC_MODSTAT_RMW_SERRA_CLR_MSK 0xfffffffb
1500 #define ALT_ECC_MODSTAT_RMW_SERRA_RESET 0x0
1502 #define ALT_ECC_MODSTAT_RMW_SERRA_GET(value) (((value) & 0x00000004) >> 2)
1504 #define ALT_ECC_MODSTAT_RMW_SERRA_SET(value) (((value) << 2) & 0x00000004)
1515 #define ALT_ECC_MODSTAT_RMW_SERRB_LSB 3
1517 #define ALT_ECC_MODSTAT_RMW_SERRB_MSB 3
1519 #define ALT_ECC_MODSTAT_RMW_SERRB_WIDTH 1
1521 #define ALT_ECC_MODSTAT_RMW_SERRB_SET_MSK 0x00000008
1523 #define ALT_ECC_MODSTAT_RMW_SERRB_CLR_MSK 0xfffffff7
1525 #define ALT_ECC_MODSTAT_RMW_SERRB_RESET 0x0
1527 #define ALT_ECC_MODSTAT_RMW_SERRB_GET(value) (((value) & 0x00000008) >> 3)
1529 #define ALT_ECC_MODSTAT_RMW_SERRB_SET(value) (((value) << 3) & 0x00000008)
1540 #define ALT_ECC_MODSTAT_RMW_DERRA_LSB 4
1542 #define ALT_ECC_MODSTAT_RMW_DERRA_MSB 4
1544 #define ALT_ECC_MODSTAT_RMW_DERRA_WIDTH 1
1546 #define ALT_ECC_MODSTAT_RMW_DERRA_SET_MSK 0x00000010
1548 #define ALT_ECC_MODSTAT_RMW_DERRA_CLR_MSK 0xffffffef
1550 #define ALT_ECC_MODSTAT_RMW_DERRA_RESET 0x0
1552 #define ALT_ECC_MODSTAT_RMW_DERRA_GET(value) (((value) & 0x00000010) >> 4)
1554 #define ALT_ECC_MODSTAT_RMW_DERRA_SET(value) (((value) << 4) & 0x00000010)
1565 #define ALT_ECC_MODSTAT_RMW_DERRB_LSB 5
1567 #define ALT_ECC_MODSTAT_RMW_DERRB_MSB 5
1569 #define ALT_ECC_MODSTAT_RMW_DERRB_WIDTH 1
1571 #define ALT_ECC_MODSTAT_RMW_DERRB_SET_MSK 0x00000020
1573 #define ALT_ECC_MODSTAT_RMW_DERRB_CLR_MSK 0xffffffdf
1575 #define ALT_ECC_MODSTAT_RMW_DERRB_RESET 0x0
1577 #define ALT_ECC_MODSTAT_RMW_DERRB_GET(value) (((value) & 0x00000020) >> 5)
1579 #define ALT_ECC_MODSTAT_RMW_DERRB_SET(value) (((value) << 5) & 0x00000020)
1581 #ifndef __ASSEMBLY__
1593 struct ALT_ECC_MODSTAT_s
1595 volatile uint32_t CMPFLGA : 1;
1596 volatile uint32_t CMPFLGB : 1;
1597 volatile uint32_t RMW_SERRA : 1;
1598 volatile uint32_t RMW_SERRB : 1;
1599 volatile uint32_t RMW_DERRA : 1;
1600 volatile uint32_t RMW_DERRB : 1;
1605 typedef struct ALT_ECC_MODSTAT_s ALT_ECC_MODSTAT_t;
1609 #define ALT_ECC_MODSTAT_RESET 0x00000000
1611 #define ALT_ECC_MODSTAT_OFST 0x28
1613 #define ALT_ECC_MODSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_MODSTAT_OFST))
1638 #define ALT_ECC_DERRADDRA_ADDRESS_LSB 0
1640 #define ALT_ECC_DERRADDRA_ADDRESS_MSB 30
1642 #define ALT_ECC_DERRADDRA_ADDRESS_WIDTH 31
1644 #define ALT_ECC_DERRADDRA_ADDRESS_SET_MSK 0x7fffffff
1646 #define ALT_ECC_DERRADDRA_ADDRESS_CLR_MSK 0x80000000
1648 #define ALT_ECC_DERRADDRA_ADDRESS_RESET 0x0
1650 #define ALT_ECC_DERRADDRA_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1652 #define ALT_ECC_DERRADDRA_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1654 #ifndef __ASSEMBLY__
1666 struct ALT_ECC_DERRADDRA_s
1668 volatile uint32_t Address : 31;
1673 typedef struct ALT_ECC_DERRADDRA_s ALT_ECC_DERRADDRA_t;
1677 #define ALT_ECC_DERRADDRA_RESET 0x00000000
1679 #define ALT_ECC_DERRADDRA_OFST 0x2c
1681 #define ALT_ECC_DERRADDRA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_DERRADDRA_OFST))
1706 #define ALT_ECC_SERRADDRA_ADDRESS_LSB 0
1708 #define ALT_ECC_SERRADDRA_ADDRESS_MSB 30
1710 #define ALT_ECC_SERRADDRA_ADDRESS_WIDTH 31
1712 #define ALT_ECC_SERRADDRA_ADDRESS_SET_MSK 0x7fffffff
1714 #define ALT_ECC_SERRADDRA_ADDRESS_CLR_MSK 0x80000000
1716 #define ALT_ECC_SERRADDRA_ADDRESS_RESET 0x0
1718 #define ALT_ECC_SERRADDRA_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1720 #define ALT_ECC_SERRADDRA_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1722 #ifndef __ASSEMBLY__
1734 struct ALT_ECC_SERRADDRA_s
1736 volatile uint32_t Address : 31;
1741 typedef struct ALT_ECC_SERRADDRA_s ALT_ECC_SERRADDRA_t;
1745 #define ALT_ECC_SERRADDRA_RESET 0x00000000
1747 #define ALT_ECC_SERRADDRA_OFST 0x30
1749 #define ALT_ECC_SERRADDRA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRADDRA_OFST))
1774 #define ALT_ECC_DERRADDRB_ADDRESS_LSB 0
1776 #define ALT_ECC_DERRADDRB_ADDRESS_MSB 30
1778 #define ALT_ECC_DERRADDRB_ADDRESS_WIDTH 31
1780 #define ALT_ECC_DERRADDRB_ADDRESS_SET_MSK 0x7fffffff
1782 #define ALT_ECC_DERRADDRB_ADDRESS_CLR_MSK 0x80000000
1784 #define ALT_ECC_DERRADDRB_ADDRESS_RESET 0x0
1786 #define ALT_ECC_DERRADDRB_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1788 #define ALT_ECC_DERRADDRB_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1790 #ifndef __ASSEMBLY__
1802 struct ALT_ECC_DERRADDRB_s
1804 volatile uint32_t Address : 31;
1809 typedef struct ALT_ECC_DERRADDRB_s ALT_ECC_DERRADDRB_t;
1813 #define ALT_ECC_DERRADDRB_RESET 0x00000000
1815 #define ALT_ECC_DERRADDRB_OFST 0x34
1817 #define ALT_ECC_DERRADDRB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_DERRADDRB_OFST))
1842 #define ALT_ECC_SERRADDRB_ADDRESS_LSB 0
1844 #define ALT_ECC_SERRADDRB_ADDRESS_MSB 30
1846 #define ALT_ECC_SERRADDRB_ADDRESS_WIDTH 31
1848 #define ALT_ECC_SERRADDRB_ADDRESS_SET_MSK 0x7fffffff
1850 #define ALT_ECC_SERRADDRB_ADDRESS_CLR_MSK 0x80000000
1852 #define ALT_ECC_SERRADDRB_ADDRESS_RESET 0x0
1854 #define ALT_ECC_SERRADDRB_ADDRESS_GET(value) (((value) & 0x7fffffff) >> 0)
1856 #define ALT_ECC_SERRADDRB_ADDRESS_SET(value) (((value) << 0) & 0x7fffffff)
1858 #ifndef __ASSEMBLY__
1870 struct ALT_ECC_SERRADDRB_s
1872 volatile uint32_t Address : 31;
1877 typedef struct ALT_ECC_SERRADDRB_s ALT_ECC_SERRADDRB_t;
1881 #define ALT_ECC_SERRADDRB_RESET 0x00000000
1883 #define ALT_ECC_SERRADDRB_OFST 0x38
1885 #define ALT_ECC_SERRADDRB_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRADDRB_OFST))
1908 #define ALT_ECC_SERRCNTREG_SERRCNT_LSB 0
1910 #define ALT_ECC_SERRCNTREG_SERRCNT_MSB 31
1912 #define ALT_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1914 #define ALT_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1916 #define ALT_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1918 #define ALT_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1920 #define ALT_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1922 #define ALT_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1924 #ifndef __ASSEMBLY__
1936 struct ALT_ECC_SERRCNTREG_s
1938 volatile uint32_t SERRCNT : 32;
1942 typedef struct ALT_ECC_SERRCNTREG_s ALT_ECC_SERRCNTREG_t;
1946 #define ALT_ECC_SERRCNTREG_RESET 0x00000000
1948 #define ALT_ECC_SERRCNTREG_OFST 0x3c
1950 #define ALT_ECC_SERRCNTREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRCNTREG_OFST))
1975 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1977 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 30
1979 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 31
1981 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x7fffffff
1983 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0x80000000
1985 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1987 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x7fffffff) >> 0)
1989 #define ALT_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x7fffffff)
1991 #ifndef __ASSEMBLY__
2003 struct ALT_ECC_ECC_ADDRBUS_s
2005 volatile uint32_t ECC_AddrBUS : 31;
2010 typedef struct ALT_ECC_ECC_ADDRBUS_s ALT_ECC_ECC_ADDRBUS_t;
2014 #define ALT_ECC_ECC_ADDRBUS_RESET 0x00000000
2016 #define ALT_ECC_ECC_ADDRBUS_OFST 0x40
2018 #define ALT_ECC_ECC_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_ADDRBUS_OFST))
2041 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
2043 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
2045 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
2047 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2049 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2051 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
2053 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2055 #define ALT_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2057 #ifndef __ASSEMBLY__
2069 struct ALT_ECC_ECC_RDATA0BUS_s
2071 volatile uint32_t ECC_RDataBUS : 32;
2075 typedef struct ALT_ECC_ECC_RDATA0BUS_s ALT_ECC_ECC_RDATA0BUS_t;
2079 #define ALT_ECC_ECC_RDATA0BUS_RESET 0x00000000
2081 #define ALT_ECC_ECC_RDATA0BUS_OFST 0x44
2083 #define ALT_ECC_ECC_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA0BUS_OFST))
2106 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
2108 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 31
2110 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
2112 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2114 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2116 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
2118 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2120 #define ALT_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2122 #ifndef __ASSEMBLY__
2134 struct ALT_ECC_ECC_RDATA1BUS_s
2136 volatile uint32_t ECC_RDataBUS : 32;
2140 typedef struct ALT_ECC_ECC_RDATA1BUS_s ALT_ECC_ECC_RDATA1BUS_t;
2144 #define ALT_ECC_ECC_RDATA1BUS_RESET 0x00000000
2146 #define ALT_ECC_ECC_RDATA1BUS_OFST 0x48
2148 #define ALT_ECC_ECC_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA1BUS_OFST))
2171 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
2173 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
2175 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
2177 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2179 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2181 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
2183 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2185 #define ALT_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2187 #ifndef __ASSEMBLY__
2199 struct ALT_ECC_ECC_RDATA2BUS_s
2201 volatile uint32_t ECC_RDataBUS : 32;
2205 typedef struct ALT_ECC_ECC_RDATA2BUS_s ALT_ECC_ECC_RDATA2BUS_t;
2209 #define ALT_ECC_ECC_RDATA2BUS_RESET 0x00000000
2211 #define ALT_ECC_ECC_RDATA2BUS_OFST 0x4c
2213 #define ALT_ECC_ECC_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA2BUS_OFST))
2236 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
2238 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
2240 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
2242 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
2244 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
2246 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
2248 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2250 #define ALT_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2252 #ifndef __ASSEMBLY__
2264 struct ALT_ECC_ECC_RDATA3BUS_s
2266 volatile uint32_t ECC_RDataBUS : 32;
2270 typedef struct ALT_ECC_ECC_RDATA3BUS_s ALT_ECC_ECC_RDATA3BUS_t;
2274 #define ALT_ECC_ECC_RDATA3BUS_RESET 0x00000000
2276 #define ALT_ECC_ECC_RDATA3BUS_OFST 0x50
2278 #define ALT_ECC_ECC_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATA3BUS_OFST))
2301 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
2303 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
2305 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
2307 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2309 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2311 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
2313 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2315 #define ALT_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2317 #ifndef __ASSEMBLY__
2329 struct ALT_ECC_ECC_WDATA0BUS_s
2331 volatile uint32_t ECC_WDataBUS : 32;
2335 typedef struct ALT_ECC_ECC_WDATA0BUS_s ALT_ECC_ECC_WDATA0BUS_t;
2339 #define ALT_ECC_ECC_WDATA0BUS_RESET 0x00000000
2341 #define ALT_ECC_ECC_WDATA0BUS_OFST 0x54
2343 #define ALT_ECC_ECC_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA0BUS_OFST))
2366 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
2368 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 31
2370 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
2372 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2374 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2376 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
2378 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2380 #define ALT_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2382 #ifndef __ASSEMBLY__
2394 struct ALT_ECC_ECC_WDATA1BUS_s
2396 volatile uint32_t ECC_WDataBUS : 32;
2400 typedef struct ALT_ECC_ECC_WDATA1BUS_s ALT_ECC_ECC_WDATA1BUS_t;
2404 #define ALT_ECC_ECC_WDATA1BUS_RESET 0x00000000
2406 #define ALT_ECC_ECC_WDATA1BUS_OFST 0x58
2408 #define ALT_ECC_ECC_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA1BUS_OFST))
2431 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
2433 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
2435 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
2437 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2439 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2441 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
2443 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2445 #define ALT_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2447 #ifndef __ASSEMBLY__
2459 struct ALT_ECC_ECC_WDATA2BUS_s
2461 volatile uint32_t ECC_WDataBUS : 32;
2465 typedef struct ALT_ECC_ECC_WDATA2BUS_s ALT_ECC_ECC_WDATA2BUS_t;
2469 #define ALT_ECC_ECC_WDATA2BUS_RESET 0x00000000
2471 #define ALT_ECC_ECC_WDATA2BUS_OFST 0x5c
2473 #define ALT_ECC_ECC_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA2BUS_OFST))
2496 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
2498 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
2500 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
2502 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
2504 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
2506 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
2508 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
2510 #define ALT_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
2512 #ifndef __ASSEMBLY__
2524 struct ALT_ECC_ECC_WDATA3BUS_s
2526 volatile uint32_t ECC_WDataBUS : 32;
2530 typedef struct ALT_ECC_ECC_WDATA3BUS_s ALT_ECC_ECC_WDATA3BUS_t;
2534 #define ALT_ECC_ECC_WDATA3BUS_RESET 0x00000000
2536 #define ALT_ECC_ECC_WDATA3BUS_OFST 0x60
2538 #define ALT_ECC_ECC_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATA3BUS_OFST))
2565 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
2567 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 7
2569 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 8
2571 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x000000ff
2573 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff00
2575 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
2577 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
2579 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
2590 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
2592 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 15
2594 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 8
2596 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x0000ff00
2598 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff00ff
2600 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
2602 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2604 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
2615 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
2617 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 23
2619 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 8
2621 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x00ff0000
2623 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff00ffff
2625 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
2627 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2629 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
2640 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
2642 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 31
2644 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 8
2646 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0xff000000
2648 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x00ffffff
2650 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
2652 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
2654 #define ALT_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0xff000000)
2656 #ifndef __ASSEMBLY__
2668 struct ALT_ECC_ECC_RDATAECC0BUS_s
2670 volatile uint32_t ECC_RDataecc0BUS : 8;
2671 volatile uint32_t ECC_RDataecc1BUS : 8;
2672 volatile uint32_t ECC_RDataecc2BUS : 8;
2673 volatile uint32_t ECC_RDataecc3BUS : 8;
2677 typedef struct ALT_ECC_ECC_RDATAECC0BUS_s ALT_ECC_ECC_RDATAECC0BUS_t;
2681 #define ALT_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
2683 #define ALT_ECC_ECC_RDATAECC0BUS_OFST 0x64
2685 #define ALT_ECC_ECC_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATAECC0BUS_OFST))
2712 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
2714 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 7
2716 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 8
2718 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x000000ff
2720 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff00
2722 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
2724 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x000000ff) >> 0)
2726 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x000000ff)
2737 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
2739 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 15
2741 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 8
2743 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x0000ff00
2745 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff00ff
2747 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
2749 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2751 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x0000ff00)
2762 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
2764 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 23
2766 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 8
2768 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x00ff0000
2770 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff00ffff
2772 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
2774 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2776 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x00ff0000)
2787 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
2789 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 31
2791 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 8
2793 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0xff000000
2795 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x00ffffff
2797 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
2799 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0xff000000) >> 24)
2801 #define ALT_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0xff000000)
2803 #ifndef __ASSEMBLY__
2815 struct ALT_ECC_ECC_RDATAECC1BUS_s
2817 volatile uint32_t ECC_RDataecc4BUS : 8;
2818 volatile uint32_t ECC_RDataecc5BUS : 8;
2819 volatile uint32_t ECC_RDataecc6BUS : 8;
2820 volatile uint32_t ECC_RDataecc7BUS : 8;
2824 typedef struct ALT_ECC_ECC_RDATAECC1BUS_s ALT_ECC_ECC_RDATAECC1BUS_t;
2828 #define ALT_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
2830 #define ALT_ECC_ECC_RDATAECC1BUS_OFST 0x68
2832 #define ALT_ECC_ECC_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_RDATAECC1BUS_OFST))
2859 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
2861 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 7
2863 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 8
2865 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x000000ff
2867 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff00
2869 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2871 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
2873 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
2884 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2886 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 15
2888 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 8
2890 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x0000ff00
2892 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff00ff
2894 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2896 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
2898 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
2909 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2911 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 23
2913 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 8
2915 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x00ff0000
2917 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff00ffff
2919 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2921 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
2923 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
2934 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2936 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 31
2938 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 8
2940 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0xff000000
2942 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x00ffffff
2944 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2946 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
2948 #define ALT_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0xff000000)
2950 #ifndef __ASSEMBLY__
2962 struct ALT_ECC_ECC_WDATAECC0BUS_s
2964 volatile uint32_t ECC_WDataecc0BUS : 8;
2965 volatile uint32_t ECC_WDataecc1BUS : 8;
2966 volatile uint32_t ECC_WDataecc2BUS : 8;
2967 volatile uint32_t ECC_WDataecc3BUS : 8;
2971 typedef struct ALT_ECC_ECC_WDATAECC0BUS_s ALT_ECC_ECC_WDATAECC0BUS_t;
2975 #define ALT_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2977 #define ALT_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2979 #define ALT_ECC_ECC_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATAECC0BUS_OFST))
3006 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
3008 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 7
3010 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 8
3012 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x000000ff
3014 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff00
3016 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
3018 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x000000ff) >> 0)
3020 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x000000ff)
3031 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
3033 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 15
3035 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 8
3037 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x0000ff00
3039 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff00ff
3041 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
3043 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3045 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x0000ff00)
3056 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
3058 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 23
3060 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 8
3062 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x00ff0000
3064 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff00ffff
3066 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
3068 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3070 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x00ff0000)
3081 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
3083 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 31
3085 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 8
3087 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0xff000000
3089 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x00ffffff
3091 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
3093 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0xff000000) >> 24)
3095 #define ALT_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0xff000000)
3097 #ifndef __ASSEMBLY__
3109 struct ALT_ECC_ECC_WDATAECC1BUS_s
3111 volatile uint32_t ECC_WDataecc4BUS : 8;
3112 volatile uint32_t ECC_WDataecc5BUS : 8;
3113 volatile uint32_t ECC_WDataecc6BUS : 8;
3114 volatile uint32_t ECC_WDataecc7BUS : 8;
3118 typedef struct ALT_ECC_ECC_WDATAECC1BUS_s ALT_ECC_ECC_WDATAECC1BUS_t;
3122 #define ALT_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
3124 #define ALT_ECC_ECC_WDATAECC1BUS_OFST 0x70
3126 #define ALT_ECC_ECC_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDATAECC1BUS_OFST))
3150 #define ALT_ECC_ECC_DBYTECTRL_DBEN_LSB 0
3152 #define ALT_ECC_ECC_DBYTECTRL_DBEN_MSB 7
3154 #define ALT_ECC_ECC_DBYTECTRL_DBEN_WIDTH 8
3156 #define ALT_ECC_ECC_DBYTECTRL_DBEN_SET_MSK 0x000000ff
3158 #define ALT_ECC_ECC_DBYTECTRL_DBEN_CLR_MSK 0xffffff00
3160 #define ALT_ECC_ECC_DBYTECTRL_DBEN_RESET 0x0
3162 #define ALT_ECC_ECC_DBYTECTRL_DBEN_GET(value) (((value) & 0x000000ff) >> 0)
3164 #define ALT_ECC_ECC_DBYTECTRL_DBEN_SET(value) (((value) << 0) & 0x000000ff)
3166 #ifndef __ASSEMBLY__
3178 struct ALT_ECC_ECC_DBYTECTRL_s
3180 volatile uint32_t DBEN : 8;
3185 typedef struct ALT_ECC_ECC_DBYTECTRL_s ALT_ECC_ECC_DBYTECTRL_t;
3189 #define ALT_ECC_ECC_DBYTECTRL_RESET 0x00000000
3191 #define ALT_ECC_ECC_DBYTECTRL_OFST 0x74
3193 #define ALT_ECC_ECC_DBYTECTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_DBYTECTRL_OFST))
3225 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_LSB 0
3227 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_MSB 0
3229 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_WIDTH 1
3231 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_SET_MSK 0x00000001
3233 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_CLR_MSK 0xfffffffe
3235 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_RESET 0x0
3237 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
3239 #define ALT_ECC_ECC_ACCCTRL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
3250 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_LSB 1
3252 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_MSB 1
3254 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_WIDTH 1
3256 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_SET_MSK 0x00000002
3258 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_CLR_MSK 0xfffffffd
3260 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_RESET 0x0
3262 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
3264 #define ALT_ECC_ECC_ACCCTRL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
3275 #define ALT_ECC_ECC_ACCCTRL_RDWR_LSB 8
3277 #define ALT_ECC_ECC_ACCCTRL_RDWR_MSB 8
3279 #define ALT_ECC_ECC_ACCCTRL_RDWR_WIDTH 1
3281 #define ALT_ECC_ECC_ACCCTRL_RDWR_SET_MSK 0x00000100
3283 #define ALT_ECC_ECC_ACCCTRL_RDWR_CLR_MSK 0xfffffeff
3285 #define ALT_ECC_ECC_ACCCTRL_RDWR_RESET 0x0
3287 #define ALT_ECC_ECC_ACCCTRL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
3289 #define ALT_ECC_ECC_ACCCTRL_RDWR_SET(value) (((value) << 8) & 0x00000100)
3291 #ifndef __ASSEMBLY__
3303 struct ALT_ECC_ECC_ACCCTRL_s
3305 volatile uint32_t DATAOVR : 1;
3306 volatile uint32_t ECCOVR : 1;
3308 volatile uint32_t RDWR : 1;
3313 typedef struct ALT_ECC_ECC_ACCCTRL_s ALT_ECC_ECC_ACCCTRL_t;
3317 #define ALT_ECC_ECC_ACCCTRL_RESET 0x00000000
3319 #define ALT_ECC_ECC_ACCCTRL_OFST 0x78
3321 #define ALT_ECC_ECC_ACCCTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_ACCCTRL_OFST))
3347 #define ALT_ECC_ECC_STARTACC_ENBUSB_LSB 0
3349 #define ALT_ECC_ECC_STARTACC_ENBUSB_MSB 0
3351 #define ALT_ECC_ECC_STARTACC_ENBUSB_WIDTH 1
3353 #define ALT_ECC_ECC_STARTACC_ENBUSB_SET_MSK 0x00000001
3355 #define ALT_ECC_ECC_STARTACC_ENBUSB_CLR_MSK 0xfffffffe
3357 #define ALT_ECC_ECC_STARTACC_ENBUSB_RESET 0x0
3359 #define ALT_ECC_ECC_STARTACC_ENBUSB_GET(value) (((value) & 0x00000001) >> 0)
3361 #define ALT_ECC_ECC_STARTACC_ENBUSB_SET(value) (((value) << 0) & 0x00000001)
3372 #define ALT_ECC_ECC_STARTACC_ENBUSA_LSB 16
3374 #define ALT_ECC_ECC_STARTACC_ENBUSA_MSB 16
3376 #define ALT_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
3378 #define ALT_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
3380 #define ALT_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
3382 #define ALT_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
3384 #define ALT_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
3386 #define ALT_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
3388 #ifndef __ASSEMBLY__
3400 struct ALT_ECC_ECC_STARTACC_s
3402 volatile uint32_t ENBUSB : 1;
3404 volatile uint32_t ENBUSA : 1;
3409 typedef struct ALT_ECC_ECC_STARTACC_s ALT_ECC_ECC_STARTACC_t;
3413 #define ALT_ECC_ECC_STARTACC_RESET 0x00000000
3415 #define ALT_ECC_ECC_STARTACC_OFST 0x7c
3417 #define ALT_ECC_ECC_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_STARTACC_OFST))
3441 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_LSB 0
3443 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_MSB 0
3445 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_WIDTH 1
3447 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_SET_MSK 0x00000001
3449 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_CLR_MSK 0xfffffffe
3451 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_RESET 0x0
3453 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
3455 #define ALT_ECC_ECC_WDCTRL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
3457 #ifndef __ASSEMBLY__
3469 struct ALT_ECC_ECC_WDCTRL_s
3471 volatile uint32_t WDEN_RAM : 1;
3476 typedef struct ALT_ECC_ECC_WDCTRL_s ALT_ECC_ECC_WDCTRL_t;
3480 #define ALT_ECC_ECC_WDCTRL_RESET 0x00000000
3482 #define ALT_ECC_ECC_WDCTRL_OFST 0x80
3484 #define ALT_ECC_ECC_WDCTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_WDCTRL_OFST))
3535 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_LSB 0
3537 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_MSB 0
3539 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_WIDTH 1
3541 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_SET_MSK 0x00000001
3543 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
3545 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_RESET 0x0
3547 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
3549 #define ALT_ECC_ECC_DECODERSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
3570 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_LSB 1
3572 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_MSB 1
3574 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_WIDTH 1
3576 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_SET_MSK 0x00000002
3578 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
3580 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_RESET 0x0
3582 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
3584 #define ALT_ECC_ECC_DECODERSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
3605 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_LSB 2
3607 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_MSB 2
3609 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_WIDTH 1
3611 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_SET_MSK 0x00000004
3613 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
3615 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_RESET 0x0
3617 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
3619 #define ALT_ECC_ECC_DECODERSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
3640 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_LSB 3
3642 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_MSB 3
3644 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_WIDTH 1
3646 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_SET_MSK 0x00000008
3648 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
3650 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_RESET 0x0
3652 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
3654 #define ALT_ECC_ECC_DECODERSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
3675 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_LSB 4
3677 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_MSB 4
3679 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_WIDTH 1
3681 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_SET_MSK 0x00000010
3683 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_CLR_MSK 0xffffffef
3685 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_RESET 0x0
3687 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_GET(value) (((value) & 0x00000010) >> 4)
3689 #define ALT_ECC_ECC_DECODERSTAT_DEC4SERRFLG_SET(value) (((value) << 4) & 0x00000010)
3710 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_LSB 5
3712 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_MSB 5
3714 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_WIDTH 1
3716 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_SET_MSK 0x00000020
3718 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_CLR_MSK 0xffffffdf
3720 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_RESET 0x0
3722 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_GET(value) (((value) & 0x00000020) >> 5)
3724 #define ALT_ECC_ECC_DECODERSTAT_DEC5SERRFLG_SET(value) (((value) << 5) & 0x00000020)
3745 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_LSB 6
3747 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_MSB 6
3749 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_WIDTH 1
3751 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_SET_MSK 0x00000040
3753 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_CLR_MSK 0xffffffbf
3755 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_RESET 0x0
3757 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_GET(value) (((value) & 0x00000040) >> 6)
3759 #define ALT_ECC_ECC_DECODERSTAT_DEC6SERRFLG_SET(value) (((value) << 6) & 0x00000040)
3780 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_LSB 7
3782 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_MSB 7
3784 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_WIDTH 1
3786 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_SET_MSK 0x00000080
3788 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_CLR_MSK 0xffffff7f
3790 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_RESET 0x0
3792 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_GET(value) (((value) & 0x00000080) >> 7)
3794 #define ALT_ECC_ECC_DECODERSTAT_DEC7SERRFLG_SET(value) (((value) << 7) & 0x00000080)
3815 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_LSB 8
3817 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_MSB 8
3819 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_WIDTH 1
3821 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_SET_MSK 0x00000100
3823 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
3825 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_RESET 0x0
3827 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
3829 #define ALT_ECC_ECC_DECODERSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
3850 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_LSB 9
3852 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_MSB 9
3854 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_WIDTH 1
3856 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_SET_MSK 0x00000200
3858 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
3860 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_RESET 0x0
3862 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
3864 #define ALT_ECC_ECC_DECODERSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
3885 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_LSB 10
3887 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_MSB 10
3889 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_WIDTH 1
3891 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_SET_MSK 0x00000400
3893 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
3895 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_RESET 0x0
3897 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
3899 #define ALT_ECC_ECC_DECODERSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
3920 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_LSB 11
3922 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_MSB 11
3924 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_WIDTH 1
3926 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_SET_MSK 0x00000800
3928 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
3930 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_RESET 0x0
3932 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
3934 #define ALT_ECC_ECC_DECODERSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
3955 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_LSB 12
3957 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_MSB 12
3959 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_WIDTH 1
3961 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_SET_MSK 0x00001000
3963 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_CLR_MSK 0xffffefff
3965 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_RESET 0x0
3967 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_GET(value) (((value) & 0x00001000) >> 12)
3969 #define ALT_ECC_ECC_DECODERSTAT_DEC4DERRFLG_SET(value) (((value) << 12) & 0x00001000)
3990 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_LSB 13
3992 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_MSB 13
3994 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_WIDTH 1
3996 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_SET_MSK 0x00002000
3998 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_CLR_MSK 0xffffdfff
4000 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_RESET 0x0
4002 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_GET(value) (((value) & 0x00002000) >> 13)
4004 #define ALT_ECC_ECC_DECODERSTAT_DEC5DERRFLG_SET(value) (((value) << 13) & 0x00002000)
4025 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_LSB 14
4027 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_MSB 14
4029 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_WIDTH 1
4031 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_SET_MSK 0x00004000
4033 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_CLR_MSK 0xffffbfff
4035 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_RESET 0x0
4037 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_GET(value) (((value) & 0x00004000) >> 14)
4039 #define ALT_ECC_ECC_DECODERSTAT_DEC6DERRFLG_SET(value) (((value) << 14) & 0x00004000)
4060 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_LSB 15
4062 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_MSB 15
4064 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_WIDTH 1
4066 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_SET_MSK 0x00008000
4068 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_CLR_MSK 0xffff7fff
4070 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_RESET 0x0
4072 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_GET(value) (((value) & 0x00008000) >> 15)
4074 #define ALT_ECC_ECC_DECODERSTAT_DEC7DERRFLG_SET(value) (((value) << 15) & 0x00008000)
4076 #ifndef __ASSEMBLY__
4088 struct ALT_ECC_ECC_DECODERSTAT_s
4090 volatile uint32_t DEC0SERRFLG : 1;
4091 volatile uint32_t DEC1SERRFLG : 1;
4092 volatile uint32_t DEC2SERRFLG : 1;
4093 volatile uint32_t DEC3SERRFLG : 1;
4094 volatile uint32_t DEC4SERRFLG : 1;
4095 volatile uint32_t DEC5SERRFLG : 1;
4096 volatile uint32_t DEC6SERRFLG : 1;
4097 volatile uint32_t DEC7SERRFLG : 1;
4098 volatile uint32_t DEC0DERRFLG : 1;
4099 volatile uint32_t DEC1DERRFLG : 1;
4100 volatile uint32_t DEC2DERRFLG : 1;
4101 volatile uint32_t DEC3DERRFLG : 1;
4102 volatile uint32_t DEC4DERRFLG : 1;
4103 volatile uint32_t DEC5DERRFLG : 1;
4104 volatile uint32_t DEC6DERRFLG : 1;
4105 volatile uint32_t DEC7DERRFLG : 1;
4110 typedef struct ALT_ECC_ECC_DECODERSTAT_s ALT_ECC_ECC_DECODERSTAT_t;
4114 #define ALT_ECC_ECC_DECODERSTAT_RESET 0x00000000
4116 #define ALT_ECC_ECC_DECODERSTAT_OFST 0x84
4118 #define ALT_ECC_ECC_DECODERSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_ECC_DECODERSTAT_OFST))
4163 #define ALT_ECC_SERRLKUPA0_ADDRESS_LSB 0
4165 #define ALT_ECC_SERRLKUPA0_ADDRESS_MSB 23
4167 #define ALT_ECC_SERRLKUPA0_ADDRESS_WIDTH 24
4169 #define ALT_ECC_SERRLKUPA0_ADDRESS_SET_MSK 0x00ffffff
4171 #define ALT_ECC_SERRLKUPA0_ADDRESS_CLR_MSK 0xff000000
4173 #define ALT_ECC_SERRLKUPA0_ADDRESS_RESET 0x0
4175 #define ALT_ECC_SERRLKUPA0_ADDRESS_GET(value) (((value) & 0x00ffffff) >> 0)
4177 #define ALT_ECC_SERRLKUPA0_ADDRESS_SET(value) (((value) << 0) & 0x00ffffff)
4187 #define ALT_ECC_SERRLKUPA0_VALID1_LSB 24
4189 #define ALT_ECC_SERRLKUPA0_VALID1_MSB 24
4191 #define ALT_ECC_SERRLKUPA0_VALID1_WIDTH 1
4193 #define ALT_ECC_SERRLKUPA0_VALID1_SET_MSK 0x01000000
4195 #define ALT_ECC_SERRLKUPA0_VALID1_CLR_MSK 0xfeffffff
4197 #define ALT_ECC_SERRLKUPA0_VALID1_RESET 0x0
4199 #define ALT_ECC_SERRLKUPA0_VALID1_GET(value) (((value) & 0x01000000) >> 24)
4201 #define ALT_ECC_SERRLKUPA0_VALID1_SET(value) (((value) << 24) & 0x01000000)
4211 #define ALT_ECC_SERRLKUPA0_VALID2_LSB 25
4213 #define ALT_ECC_SERRLKUPA0_VALID2_MSB 25
4215 #define ALT_ECC_SERRLKUPA0_VALID2_WIDTH 1
4217 #define ALT_ECC_SERRLKUPA0_VALID2_SET_MSK 0x02000000
4219 #define ALT_ECC_SERRLKUPA0_VALID2_CLR_MSK 0xfdffffff
4221 #define ALT_ECC_SERRLKUPA0_VALID2_RESET 0x0
4223 #define ALT_ECC_SERRLKUPA0_VALID2_GET(value) (((value) & 0x02000000) >> 25)
4225 #define ALT_ECC_SERRLKUPA0_VALID2_SET(value) (((value) << 25) & 0x02000000)
4235 #define ALT_ECC_SERRLKUPA0_VALID3_LSB 26
4237 #define ALT_ECC_SERRLKUPA0_VALID3_MSB 26
4239 #define ALT_ECC_SERRLKUPA0_VALID3_WIDTH 1
4241 #define ALT_ECC_SERRLKUPA0_VALID3_SET_MSK 0x04000000
4243 #define ALT_ECC_SERRLKUPA0_VALID3_CLR_MSK 0xfbffffff
4245 #define ALT_ECC_SERRLKUPA0_VALID3_RESET 0x0
4247 #define ALT_ECC_SERRLKUPA0_VALID3_GET(value) (((value) & 0x04000000) >> 26)
4249 #define ALT_ECC_SERRLKUPA0_VALID3_SET(value) (((value) << 26) & 0x04000000)
4259 #define ALT_ECC_SERRLKUPA0_VALID4_LSB 27
4261 #define ALT_ECC_SERRLKUPA0_VALID4_MSB 27
4263 #define ALT_ECC_SERRLKUPA0_VALID4_WIDTH 1
4265 #define ALT_ECC_SERRLKUPA0_VALID4_SET_MSK 0x08000000
4267 #define ALT_ECC_SERRLKUPA0_VALID4_CLR_MSK 0xf7ffffff
4269 #define ALT_ECC_SERRLKUPA0_VALID4_RESET 0x0
4271 #define ALT_ECC_SERRLKUPA0_VALID4_GET(value) (((value) & 0x08000000) >> 27)
4273 #define ALT_ECC_SERRLKUPA0_VALID4_SET(value) (((value) << 27) & 0x08000000)
4283 #define ALT_ECC_SERRLKUPA0_VALID5_LSB 28
4285 #define ALT_ECC_SERRLKUPA0_VALID5_MSB 28
4287 #define ALT_ECC_SERRLKUPA0_VALID5_WIDTH 1
4289 #define ALT_ECC_SERRLKUPA0_VALID5_SET_MSK 0x10000000
4291 #define ALT_ECC_SERRLKUPA0_VALID5_CLR_MSK 0xefffffff
4293 #define ALT_ECC_SERRLKUPA0_VALID5_RESET 0x0
4295 #define ALT_ECC_SERRLKUPA0_VALID5_GET(value) (((value) & 0x10000000) >> 28)
4297 #define ALT_ECC_SERRLKUPA0_VALID5_SET(value) (((value) << 28) & 0x10000000)
4307 #define ALT_ECC_SERRLKUPA0_VALID6_LSB 29
4309 #define ALT_ECC_SERRLKUPA0_VALID6_MSB 29
4311 #define ALT_ECC_SERRLKUPA0_VALID6_WIDTH 1
4313 #define ALT_ECC_SERRLKUPA0_VALID6_SET_MSK 0x20000000
4315 #define ALT_ECC_SERRLKUPA0_VALID6_CLR_MSK 0xdfffffff
4317 #define ALT_ECC_SERRLKUPA0_VALID6_RESET 0x0
4319 #define ALT_ECC_SERRLKUPA0_VALID6_GET(value) (((value) & 0x20000000) >> 29)
4321 #define ALT_ECC_SERRLKUPA0_VALID6_SET(value) (((value) << 29) & 0x20000000)
4331 #define ALT_ECC_SERRLKUPA0_VALID7_LSB 30
4333 #define ALT_ECC_SERRLKUPA0_VALID7_MSB 30
4335 #define ALT_ECC_SERRLKUPA0_VALID7_WIDTH 1
4337 #define ALT_ECC_SERRLKUPA0_VALID7_SET_MSK 0x40000000
4339 #define ALT_ECC_SERRLKUPA0_VALID7_CLR_MSK 0xbfffffff
4341 #define ALT_ECC_SERRLKUPA0_VALID7_RESET 0x0
4343 #define ALT_ECC_SERRLKUPA0_VALID7_GET(value) (((value) & 0x40000000) >> 30)
4345 #define ALT_ECC_SERRLKUPA0_VALID7_SET(value) (((value) << 30) & 0x40000000)
4355 #define ALT_ECC_SERRLKUPA0_VALID8_LSB 31
4357 #define ALT_ECC_SERRLKUPA0_VALID8_MSB 31
4359 #define ALT_ECC_SERRLKUPA0_VALID8_WIDTH 1
4361 #define ALT_ECC_SERRLKUPA0_VALID8_SET_MSK 0x80000000
4363 #define ALT_ECC_SERRLKUPA0_VALID8_CLR_MSK 0x7fffffff
4365 #define ALT_ECC_SERRLKUPA0_VALID8_RESET 0x0
4367 #define ALT_ECC_SERRLKUPA0_VALID8_GET(value) (((value) & 0x80000000) >> 31)
4369 #define ALT_ECC_SERRLKUPA0_VALID8_SET(value) (((value) << 31) & 0x80000000)
4371 #ifndef __ASSEMBLY__
4383 struct ALT_ECC_SERRLKUPA0_s
4385 const volatile uint32_t Address : 24;
4386 volatile uint32_t VALID1 : 1;
4387 volatile uint32_t VALID2 : 1;
4388 volatile uint32_t VALID3 : 1;
4389 volatile uint32_t VALID4 : 1;
4390 volatile uint32_t VALID5 : 1;
4391 volatile uint32_t VALID6 : 1;
4392 volatile uint32_t VALID7 : 1;
4393 volatile uint32_t VALID8 : 1;
4397 typedef struct ALT_ECC_SERRLKUPA0_s ALT_ECC_SERRLKUPA0_t;
4401 #define ALT_ECC_SERRLKUPA0_RESET 0x00000000
4403 #define ALT_ECC_SERRLKUPA0_OFST 0x90
4405 #define ALT_ECC_SERRLKUPA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRLKUPA0_OFST))
4450 #define ALT_ECC_SERRLKUPB0_ADDRESS_LSB 0
4452 #define ALT_ECC_SERRLKUPB0_ADDRESS_MSB 23
4454 #define ALT_ECC_SERRLKUPB0_ADDRESS_WIDTH 24
4456 #define ALT_ECC_SERRLKUPB0_ADDRESS_SET_MSK 0x00ffffff
4458 #define ALT_ECC_SERRLKUPB0_ADDRESS_CLR_MSK 0xff000000
4460 #define ALT_ECC_SERRLKUPB0_ADDRESS_RESET 0x0
4462 #define ALT_ECC_SERRLKUPB0_ADDRESS_GET(value) (((value) & 0x00ffffff) >> 0)
4464 #define ALT_ECC_SERRLKUPB0_ADDRESS_SET(value) (((value) << 0) & 0x00ffffff)
4474 #define ALT_ECC_SERRLKUPB0_VALID1_LSB 24
4476 #define ALT_ECC_SERRLKUPB0_VALID1_MSB 24
4478 #define ALT_ECC_SERRLKUPB0_VALID1_WIDTH 1
4480 #define ALT_ECC_SERRLKUPB0_VALID1_SET_MSK 0x01000000
4482 #define ALT_ECC_SERRLKUPB0_VALID1_CLR_MSK 0xfeffffff
4484 #define ALT_ECC_SERRLKUPB0_VALID1_RESET 0x0
4486 #define ALT_ECC_SERRLKUPB0_VALID1_GET(value) (((value) & 0x01000000) >> 24)
4488 #define ALT_ECC_SERRLKUPB0_VALID1_SET(value) (((value) << 24) & 0x01000000)
4498 #define ALT_ECC_SERRLKUPB0_VALID2_LSB 25
4500 #define ALT_ECC_SERRLKUPB0_VALID2_MSB 25
4502 #define ALT_ECC_SERRLKUPB0_VALID2_WIDTH 1
4504 #define ALT_ECC_SERRLKUPB0_VALID2_SET_MSK 0x02000000
4506 #define ALT_ECC_SERRLKUPB0_VALID2_CLR_MSK 0xfdffffff
4508 #define ALT_ECC_SERRLKUPB0_VALID2_RESET 0x0
4510 #define ALT_ECC_SERRLKUPB0_VALID2_GET(value) (((value) & 0x02000000) >> 25)
4512 #define ALT_ECC_SERRLKUPB0_VALID2_SET(value) (((value) << 25) & 0x02000000)
4522 #define ALT_ECC_SERRLKUPB0_VALID3_LSB 26
4524 #define ALT_ECC_SERRLKUPB0_VALID3_MSB 26
4526 #define ALT_ECC_SERRLKUPB0_VALID3_WIDTH 1
4528 #define ALT_ECC_SERRLKUPB0_VALID3_SET_MSK 0x04000000
4530 #define ALT_ECC_SERRLKUPB0_VALID3_CLR_MSK 0xfbffffff
4532 #define ALT_ECC_SERRLKUPB0_VALID3_RESET 0x0
4534 #define ALT_ECC_SERRLKUPB0_VALID3_GET(value) (((value) & 0x04000000) >> 26)
4536 #define ALT_ECC_SERRLKUPB0_VALID3_SET(value) (((value) << 26) & 0x04000000)
4546 #define ALT_ECC_SERRLKUPB0_VALID4_LSB 27
4548 #define ALT_ECC_SERRLKUPB0_VALID4_MSB 27
4550 #define ALT_ECC_SERRLKUPB0_VALID4_WIDTH 1
4552 #define ALT_ECC_SERRLKUPB0_VALID4_SET_MSK 0x08000000
4554 #define ALT_ECC_SERRLKUPB0_VALID4_CLR_MSK 0xf7ffffff
4556 #define ALT_ECC_SERRLKUPB0_VALID4_RESET 0x0
4558 #define ALT_ECC_SERRLKUPB0_VALID4_GET(value) (((value) & 0x08000000) >> 27)
4560 #define ALT_ECC_SERRLKUPB0_VALID4_SET(value) (((value) << 27) & 0x08000000)
4570 #define ALT_ECC_SERRLKUPB0_VALID5_LSB 28
4572 #define ALT_ECC_SERRLKUPB0_VALID5_MSB 28
4574 #define ALT_ECC_SERRLKUPB0_VALID5_WIDTH 1
4576 #define ALT_ECC_SERRLKUPB0_VALID5_SET_MSK 0x10000000
4578 #define ALT_ECC_SERRLKUPB0_VALID5_CLR_MSK 0xefffffff
4580 #define ALT_ECC_SERRLKUPB0_VALID5_RESET 0x0
4582 #define ALT_ECC_SERRLKUPB0_VALID5_GET(value) (((value) & 0x10000000) >> 28)
4584 #define ALT_ECC_SERRLKUPB0_VALID5_SET(value) (((value) << 28) & 0x10000000)
4594 #define ALT_ECC_SERRLKUPB0_VALID6_LSB 29
4596 #define ALT_ECC_SERRLKUPB0_VALID6_MSB 29
4598 #define ALT_ECC_SERRLKUPB0_VALID6_WIDTH 1
4600 #define ALT_ECC_SERRLKUPB0_VALID6_SET_MSK 0x20000000
4602 #define ALT_ECC_SERRLKUPB0_VALID6_CLR_MSK 0xdfffffff
4604 #define ALT_ECC_SERRLKUPB0_VALID6_RESET 0x0
4606 #define ALT_ECC_SERRLKUPB0_VALID6_GET(value) (((value) & 0x20000000) >> 29)
4608 #define ALT_ECC_SERRLKUPB0_VALID6_SET(value) (((value) << 29) & 0x20000000)
4618 #define ALT_ECC_SERRLKUPB0_VALID7_LSB 30
4620 #define ALT_ECC_SERRLKUPB0_VALID7_MSB 30
4622 #define ALT_ECC_SERRLKUPB0_VALID7_WIDTH 1
4624 #define ALT_ECC_SERRLKUPB0_VALID7_SET_MSK 0x40000000
4626 #define ALT_ECC_SERRLKUPB0_VALID7_CLR_MSK 0xbfffffff
4628 #define ALT_ECC_SERRLKUPB0_VALID7_RESET 0x0
4630 #define ALT_ECC_SERRLKUPB0_VALID7_GET(value) (((value) & 0x40000000) >> 30)
4632 #define ALT_ECC_SERRLKUPB0_VALID7_SET(value) (((value) << 30) & 0x40000000)
4642 #define ALT_ECC_SERRLKUPB0_VALID8_LSB 31
4644 #define ALT_ECC_SERRLKUPB0_VALID8_MSB 31
4646 #define ALT_ECC_SERRLKUPB0_VALID8_WIDTH 1
4648 #define ALT_ECC_SERRLKUPB0_VALID8_SET_MSK 0x80000000
4650 #define ALT_ECC_SERRLKUPB0_VALID8_CLR_MSK 0x7fffffff
4652 #define ALT_ECC_SERRLKUPB0_VALID8_RESET 0x0
4654 #define ALT_ECC_SERRLKUPB0_VALID8_GET(value) (((value) & 0x80000000) >> 31)
4656 #define ALT_ECC_SERRLKUPB0_VALID8_SET(value) (((value) << 31) & 0x80000000)
4658 #ifndef __ASSEMBLY__
4670 struct ALT_ECC_SERRLKUPB0_s
4672 const volatile uint32_t Address : 24;
4673 volatile uint32_t VALID1 : 1;
4674 volatile uint32_t VALID2 : 1;
4675 volatile uint32_t VALID3 : 1;
4676 volatile uint32_t VALID4 : 1;
4677 volatile uint32_t VALID5 : 1;
4678 volatile uint32_t VALID6 : 1;
4679 volatile uint32_t VALID7 : 1;
4680 volatile uint32_t VALID8 : 1;
4684 typedef struct ALT_ECC_SERRLKUPB0_s ALT_ECC_SERRLKUPB0_t;
4688 #define ALT_ECC_SERRLKUPB0_RESET 0x00000000
4690 #define ALT_ECC_SERRLKUPB0_OFST 0xd0
4692 #define ALT_ECC_SERRLKUPB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SERRLKUPB0_OFST))
4694 #ifndef __ASSEMBLY__
4708 volatile ALT_ECC_IP_REV_ID_t IP_REV_ID;
4709 volatile ALT_ECC_IP_REV_ID2_t IP_REV_ID2;
4710 volatile ALT_ECC_CTRL_t CTRL;
4711 volatile ALT_ECC_INITSTAT_t INITSTAT;
4712 volatile ALT_ECC_ERRINTEN_t ERRINTEN;
4713 volatile ALT_ECC_ERRINTENS_t ERRINTENS;
4714 volatile ALT_ECC_ERRINTENR_t ERRINTENR;
4715 volatile ALT_ECC_INTMODE_t INTMODE;
4716 volatile ALT_ECC_INTSTAT_t INTSTAT;
4717 volatile ALT_ECC_INTTEST_t INTTEST;
4718 volatile ALT_ECC_MODSTAT_t MODSTAT;
4719 volatile ALT_ECC_DERRADDRA_t DERRADDRA;
4720 volatile ALT_ECC_SERRADDRA_t SERRADDRA;
4721 volatile ALT_ECC_DERRADDRB_t DERRADDRB;
4722 volatile ALT_ECC_SERRADDRB_t SERRADDRB;
4723 volatile ALT_ECC_SERRCNTREG_t SERRCNTREG;
4724 volatile ALT_ECC_ECC_ADDRBUS_t ECC_Addrbus;
4725 volatile ALT_ECC_ECC_RDATA0BUS_t ECC_RData0bus;
4726 volatile ALT_ECC_ECC_RDATA1BUS_t ECC_RData1bus;
4727 volatile ALT_ECC_ECC_RDATA2BUS_t ECC_RData2bus;
4728 volatile ALT_ECC_ECC_RDATA3BUS_t ECC_RData3bus;
4729 volatile ALT_ECC_ECC_WDATA0BUS_t ECC_WData0bus;
4730 volatile ALT_ECC_ECC_WDATA1BUS_t ECC_WData1bus;
4731 volatile ALT_ECC_ECC_WDATA2BUS_t ECC_WData2bus;
4732 volatile ALT_ECC_ECC_WDATA3BUS_t ECC_WData3bus;
4733 volatile ALT_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus;
4734 volatile ALT_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus;
4735 volatile ALT_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus;
4736 volatile ALT_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus;
4737 volatile ALT_ECC_ECC_DBYTECTRL_t ECC_dbytectrl;
4738 volatile ALT_ECC_ECC_ACCCTRL_t ECC_accctrl;
4739 volatile ALT_ECC_ECC_STARTACC_t ECC_startacc;
4740 volatile ALT_ECC_ECC_WDCTRL_t ECC_wdctrl;
4741 volatile ALT_ECC_ECC_DECODERSTAT_t ECC_DECODERSTAT;
4742 volatile uint32_t _pad_0x88_0x8f[2];
4743 volatile ALT_ECC_SERRLKUPA0_t SERRLKUPA0;
4744 volatile uint32_t _pad_0x94_0xcf[15];
4745 volatile ALT_ECC_SERRLKUPB0_t SERRLKUPB0;
4746 volatile uint32_t _pad_0xd4_0x400[203];
4750 typedef struct ALT_ECC_s ALT_ECC_t;
4752 struct ALT_ECC_raw_s
4754 volatile uint32_t IP_REV_ID;
4755 volatile uint32_t IP_REV_ID2;
4756 volatile uint32_t CTRL;
4757 volatile uint32_t INITSTAT;
4758 volatile uint32_t ERRINTEN;
4759 volatile uint32_t ERRINTENS;
4760 volatile uint32_t ERRINTENR;
4761 volatile uint32_t INTMODE;
4762 volatile uint32_t INTSTAT;
4763 volatile uint32_t INTTEST;
4764 volatile uint32_t MODSTAT;
4765 volatile uint32_t DERRADDRA;
4766 volatile uint32_t SERRADDRA;
4767 volatile uint32_t DERRADDRB;
4768 volatile uint32_t SERRADDRB;
4769 volatile uint32_t SERRCNTREG;
4770 volatile uint32_t ECC_Addrbus;
4771 volatile uint32_t ECC_RData0bus;
4772 volatile uint32_t ECC_RData1bus;
4773 volatile uint32_t ECC_RData2bus;
4774 volatile uint32_t ECC_RData3bus;
4775 volatile uint32_t ECC_WData0bus;
4776 volatile uint32_t ECC_WData1bus;
4777 volatile uint32_t ECC_WData2bus;
4778 volatile uint32_t ECC_WData3bus;
4779 volatile uint32_t ECC_RDataecc0bus;
4780 volatile uint32_t ECC_RDataecc1bus;
4781 volatile uint32_t ECC_WDataecc0bus;
4782 volatile uint32_t ECC_WDataecc1bus;
4783 volatile uint32_t ECC_dbytectrl;
4784 volatile uint32_t ECC_accctrl;
4785 volatile uint32_t ECC_startacc;
4786 volatile uint32_t ECC_wdctrl;
4787 volatile uint32_t ECC_DECODERSTAT;
4788 volatile uint32_t _pad_0x88_0x8f[2];
4789 volatile uint32_t SERRLKUPA0;
4790 volatile uint32_t _pad_0x94_0xcf[15];
4791 volatile uint32_t SERRLKUPB0;
4792 volatile uint32_t _pad_0xd4_0x400[203];
4796 typedef struct ALT_ECC_raw_s ALT_ECC_raw_t;