35 #ifndef __ALT_SOCAL_SDMMC_H__
36 #define __ALT_SOCAL_SDMMC_H__
121 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_E_NO_CHANGE 0x0
127 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_E_ASSERT_RESET 0x1
130 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_LSB 0
132 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_MSB 0
134 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_WIDTH 1
136 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_SET_MSK 0x00000001
138 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_CLR_MSK 0xfffffffe
140 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_RESET 0x0
142 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_GET(value) (((value) & 0x00000001) >> 0)
144 #define ALT_SDMMC_CTRL_CONTROLLER_RESET_SET(value) (((value) << 0) & 0x00000001)
171 #define ALT_SDMMC_CTRL_FIFO_RESET_E_NO_CHANGE 0x0
177 #define ALT_SDMMC_CTRL_FIFO_RESET_E_ASSERT_RESET 0x1
180 #define ALT_SDMMC_CTRL_FIFO_RESET_LSB 1
182 #define ALT_SDMMC_CTRL_FIFO_RESET_MSB 1
184 #define ALT_SDMMC_CTRL_FIFO_RESET_WIDTH 1
186 #define ALT_SDMMC_CTRL_FIFO_RESET_SET_MSK 0x00000002
188 #define ALT_SDMMC_CTRL_FIFO_RESET_CLR_MSK 0xfffffffd
190 #define ALT_SDMMC_CTRL_FIFO_RESET_RESET 0x0
192 #define ALT_SDMMC_CTRL_FIFO_RESET_GET(value) (((value) & 0x00000002) >> 1)
194 #define ALT_SDMMC_CTRL_FIFO_RESET_SET(value) (((value) << 1) & 0x00000002)
222 #define ALT_SDMMC_CTRL_DMA_RESET_E_NO_CHANGE 0x0
228 #define ALT_SDMMC_CTRL_DMA_RESET_E_ASSERT_RESET 0x1
231 #define ALT_SDMMC_CTRL_DMA_RESET_LSB 2
233 #define ALT_SDMMC_CTRL_DMA_RESET_MSB 2
235 #define ALT_SDMMC_CTRL_DMA_RESET_WIDTH 1
237 #define ALT_SDMMC_CTRL_DMA_RESET_SET_MSK 0x00000004
239 #define ALT_SDMMC_CTRL_DMA_RESET_CLR_MSK 0xfffffffb
241 #define ALT_SDMMC_CTRL_DMA_RESET_RESET 0x0
243 #define ALT_SDMMC_CTRL_DMA_RESET_GET(value) (((value) & 0x00000004) >> 2)
245 #define ALT_SDMMC_CTRL_DMA_RESET_SET(value) (((value) << 2) & 0x00000004)
275 #define ALT_SDMMC_CTRL_INT_ENABLE_E_DISABLED 0x0
281 #define ALT_SDMMC_CTRL_INT_ENABLE_E_ENABLED 0x1
284 #define ALT_SDMMC_CTRL_INT_ENABLE_LSB 4
286 #define ALT_SDMMC_CTRL_INT_ENABLE_MSB 4
288 #define ALT_SDMMC_CTRL_INT_ENABLE_WIDTH 1
290 #define ALT_SDMMC_CTRL_INT_ENABLE_SET_MSK 0x00000010
292 #define ALT_SDMMC_CTRL_INT_ENABLE_CLR_MSK 0xffffffef
294 #define ALT_SDMMC_CTRL_INT_ENABLE_RESET 0x0
296 #define ALT_SDMMC_CTRL_INT_ENABLE_GET(value) (((value) & 0x00000010) >> 4)
298 #define ALT_SDMMC_CTRL_INT_ENABLE_SET(value) (((value) << 4) & 0x00000010)
324 #define ALT_SDMMC_CTRL_DMA_ENABLE_E_DISABLED 0x0
330 #define ALT_SDMMC_CTRL_DMA_ENABLE_E_ENABLED 0x1
333 #define ALT_SDMMC_CTRL_DMA_ENABLE_LSB 5
335 #define ALT_SDMMC_CTRL_DMA_ENABLE_MSB 5
337 #define ALT_SDMMC_CTRL_DMA_ENABLE_WIDTH 1
339 #define ALT_SDMMC_CTRL_DMA_ENABLE_SET_MSK 0x00000020
341 #define ALT_SDMMC_CTRL_DMA_ENABLE_CLR_MSK 0xffffffdf
343 #define ALT_SDMMC_CTRL_DMA_ENABLE_RESET 0x0
345 #define ALT_SDMMC_CTRL_DMA_ENABLE_GET(value) (((value) & 0x00000020) >> 5)
347 #define ALT_SDMMC_CTRL_DMA_ENABLE_SET(value) (((value) << 5) & 0x00000020)
373 #define ALT_SDMMC_CTRL_READ_WAIT_E_CLEAR 0x0
379 #define ALT_SDMMC_CTRL_READ_WAIT_E_ASSERT 0x1
382 #define ALT_SDMMC_CTRL_READ_WAIT_LSB 6
384 #define ALT_SDMMC_CTRL_READ_WAIT_MSB 6
386 #define ALT_SDMMC_CTRL_READ_WAIT_WIDTH 1
388 #define ALT_SDMMC_CTRL_READ_WAIT_SET_MSK 0x00000040
390 #define ALT_SDMMC_CTRL_READ_WAIT_CLR_MSK 0xffffffbf
392 #define ALT_SDMMC_CTRL_READ_WAIT_RESET 0x0
394 #define ALT_SDMMC_CTRL_READ_WAIT_GET(value) (((value) & 0x00000040) >> 6)
396 #define ALT_SDMMC_CTRL_READ_WAIT_SET(value) (((value) << 6) & 0x00000040)
428 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_FALSE 0x0
434 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_E_TRUE 0x1
437 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_LSB 7
439 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_MSB 7
441 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_WIDTH 1
443 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
445 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
447 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_RESET 0x0
449 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
451 #define ALT_SDMMC_CTRL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
481 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_E_FALSE 0x0
487 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_E_TRUE 0x1
490 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_LSB 8
492 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_MSB 8
494 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_WIDTH 1
496 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_SET_MSK 0x00000100
498 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_CLR_MSK 0xfffffeff
500 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_RESET 0x0
502 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_GET(value) (((value) & 0x00000100) >> 8)
504 #define ALT_SDMMC_CTRL_ABORT_READ_DATA_SET(value) (((value) << 8) & 0x00000100)
532 #define ALT_SDMMC_CTRL_SEND_CCSD_E_CLEAR 0x0
540 #define ALT_SDMMC_CTRL_SEND_CCSD_E_ENABLED 0x1
543 #define ALT_SDMMC_CTRL_SEND_CCSD_LSB 9
545 #define ALT_SDMMC_CTRL_SEND_CCSD_MSB 9
547 #define ALT_SDMMC_CTRL_SEND_CCSD_WIDTH 1
549 #define ALT_SDMMC_CTRL_SEND_CCSD_SET_MSK 0x00000200
551 #define ALT_SDMMC_CTRL_SEND_CCSD_CLR_MSK 0xfffffdff
553 #define ALT_SDMMC_CTRL_SEND_CCSD_RESET 0x0
555 #define ALT_SDMMC_CTRL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
557 #define ALT_SDMMC_CTRL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
585 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_CLEAR 0x0
593 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_E_ENABLED 0x1
596 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_LSB 10
598 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_MSB 10
600 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_WIDTH 1
602 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
604 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
606 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_RESET 0x0
608 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
610 #define ALT_SDMMC_CTRL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
634 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_DISABLED 0x0
640 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_E_ENABLED 0x1
643 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_LSB 11
645 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MSB 11
647 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_WIDTH 1
649 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SET_MSK 0x00000800
651 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_CLR_MSK 0xfffff7ff
653 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_RESET 0x0
655 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_GET(value) (((value) & 0x00000800) >> 11)
657 #define ALT_SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SET(value) (((value) << 11) & 0x00000800)
670 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_LSB 16
672 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_MSB 19
674 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_WIDTH 4
676 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_SET_MSK 0x000f0000
678 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff
680 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_RESET 0x0
682 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16)
684 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000)
697 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_LSB 20
699 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_MSB 23
701 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_WIDTH 4
703 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_SET_MSK 0x00f00000
705 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff
707 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_RESET 0x0
709 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20)
711 #define ALT_SDMMC_CTRL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000)
742 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_DISABLED 0x0
748 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_E_ENABLED 0x1
751 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_LSB 24
753 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_MSB 24
755 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_WIDTH 1
757 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_SET_MSK 0x01000000
759 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_CLR_MSK 0xfeffffff
761 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_RESET 0x0
763 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24)
765 #define ALT_SDMMC_CTRL_ENABLE_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000)
792 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_DISABLED 0x0
798 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_E_ENABLED 0x1
801 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_LSB 25
803 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_MSB 25
805 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_WIDTH 1
807 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
809 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
811 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_RESET 0x0
813 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
815 #define ALT_SDMMC_CTRL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
829 struct ALT_SDMMC_CTRL_s
831 volatile uint32_t CONTROLLER_RESET : 1;
832 volatile uint32_t FIFO_RESET : 1;
833 volatile uint32_t DMA_RESET : 1;
835 volatile uint32_t INT_ENABLE : 1;
836 volatile uint32_t DMA_ENABLE : 1;
837 volatile uint32_t READ_WAIT : 1;
838 volatile uint32_t SEND_IRQ_RESPONSE : 1;
839 volatile uint32_t ABORT_READ_DATA : 1;
840 volatile uint32_t SEND_CCSD : 1;
841 volatile uint32_t SEND_AUTO_STOP_CCSD : 1;
842 volatile uint32_t CEATA_DEVICE_INTERRUPT_STATUS : 1;
844 volatile uint32_t CARD_VOLTAGE_A : 4;
845 volatile uint32_t CARD_VOLTAGE_B : 4;
846 volatile uint32_t ENABLE_OD_PULLUP : 1;
847 volatile uint32_t USE_INTERNAL_DMAC : 1;
852 typedef struct ALT_SDMMC_CTRL_s ALT_SDMMC_CTRL_t;
856 #define ALT_SDMMC_CTRL_RESET 0x00000000
858 #define ALT_SDMMC_CTRL_OFST 0x0
860 #define ALT_SDMMC_CTRL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CTRL_OFST))
904 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_OFF 0x0
910 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_E_POWER_ON 0x1
913 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_LSB 0
915 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_MSB 0
917 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_WIDTH 1
919 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_SET_MSK 0x00000001
921 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_CLR_MSK 0xfffffffe
923 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_RESET 0x0
925 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_GET(value) (((value) & 0x00000001) >> 0)
927 #define ALT_SDMMC_PWREN_POWER_ENABLE_0_SET(value) (((value) << 0) & 0x00000001)
941 struct ALT_SDMMC_PWREN_s
943 volatile uint32_t POWER_ENABLE_0 : 1;
948 typedef struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
952 #define ALT_SDMMC_PWREN_RESET 0x00000000
954 #define ALT_SDMMC_PWREN_OFST 0x4
956 #define ALT_SDMMC_PWREN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_PWREN_OFST))
984 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_LSB 0
986 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_MSB 7
988 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_WIDTH 8
990 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_SET_MSK 0x000000ff
992 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_CLR_MSK 0xffffff00
994 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_RESET 0x0
996 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_GET(value) (((value) & 0x000000ff) >> 0)
998 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER0_SET(value) (((value) << 0) & 0x000000ff)
1012 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_LSB 8
1014 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_MSB 15
1016 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_WIDTH 8
1018 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_SET_MSK 0x0000ff00
1020 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_CLR_MSK 0xffff00ff
1022 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_RESET 0x0
1024 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_GET(value) (((value) & 0x0000ff00) >> 8)
1026 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER1_SET(value) (((value) << 8) & 0x0000ff00)
1040 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_LSB 16
1042 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_MSB 23
1044 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_WIDTH 8
1046 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_SET_MSK 0x00ff0000
1048 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_CLR_MSK 0xff00ffff
1050 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_RESET 0x0
1052 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_GET(value) (((value) & 0x00ff0000) >> 16)
1054 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER2_SET(value) (((value) << 16) & 0x00ff0000)
1068 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_LSB 24
1070 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_MSB 31
1072 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_WIDTH 8
1074 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_SET_MSK 0xff000000
1076 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_CLR_MSK 0x00ffffff
1078 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_RESET 0x0
1080 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_GET(value) (((value) & 0xff000000) >> 24)
1082 #define ALT_SDMMC_CLKDIV_CLK_DIVIDER3_SET(value) (((value) << 24) & 0xff000000)
1084 #ifndef __ASSEMBLY__
1096 struct ALT_SDMMC_CLKDIV_s
1098 volatile uint32_t CLK_DIVIDER0 : 8;
1099 const volatile uint32_t CLK_DIVIDER1 : 8;
1100 const volatile uint32_t CLK_DIVIDER2 : 8;
1101 const volatile uint32_t CLK_DIVIDER3 : 8;
1105 typedef struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
1109 #define ALT_SDMMC_CLKDIV_RESET 0x00000000
1111 #define ALT_SDMMC_CLKDIV_OFST 0x8
1113 #define ALT_SDMMC_CLKDIV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKDIV_OFST))
1178 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV0 0x0
1184 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV1 0x1
1190 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV2 0x2
1196 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_E_DIV3 0x3
1199 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_LSB 0
1201 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_MSB 1
1203 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_WIDTH 2
1205 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_SET_MSK 0x00000003
1207 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_CLR_MSK 0xfffffffc
1209 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_RESET 0x0
1211 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_GET(value) (((value) & 0x00000003) >> 0)
1213 #define ALT_SDMMC_CLKSRC_CARD0_CLK_SOURCE_SET(value) (((value) << 0) & 0x00000003)
1251 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV0 0x0
1257 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV1 0x1
1263 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV2 0x2
1269 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_E_DIV3 0x3
1272 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_LSB 2
1274 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_MSB 3
1276 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_WIDTH 2
1278 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_SET_MSK 0x0000000c
1280 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_CLR_MSK 0xfffffff3
1282 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_RESET 0x0
1284 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_GET(value) (((value) & 0x0000000c) >> 2)
1286 #define ALT_SDMMC_CLKSRC_CARD1_CLK_SOURCE_SET(value) (((value) << 2) & 0x0000000c)
1324 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV0 0x0
1330 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV1 0x1
1336 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV2 0x2
1342 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_E_DIV3 0x3
1345 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_LSB 4
1347 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_MSB 5
1349 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_WIDTH 2
1351 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_SET_MSK 0x00000030
1353 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_CLR_MSK 0xffffffcf
1355 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_RESET 0x0
1357 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_GET(value) (((value) & 0x00000030) >> 4)
1359 #define ALT_SDMMC_CLKSRC_CARD2_CLK_SOURCE_SET(value) (((value) << 4) & 0x00000030)
1397 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV0 0x0
1403 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV1 0x1
1409 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV2 0x2
1415 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_E_DIV3 0x3
1418 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_LSB 6
1420 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_MSB 7
1422 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_WIDTH 2
1424 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_SET_MSK 0x000000c0
1426 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_CLR_MSK 0xffffff3f
1428 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_RESET 0x0
1430 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_GET(value) (((value) & 0x000000c0) >> 6)
1432 #define ALT_SDMMC_CLKSRC_CARD3_CLK_SOURCE_SET(value) (((value) << 6) & 0x000000c0)
1470 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV0 0x0
1476 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV1 0x1
1482 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV2 0x2
1488 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_E_DIV3 0x3
1491 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_LSB 8
1493 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_MSB 9
1495 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_WIDTH 2
1497 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_SET_MSK 0x00000300
1499 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_CLR_MSK 0xfffffcff
1501 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_RESET 0x0
1503 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_GET(value) (((value) & 0x00000300) >> 8)
1505 #define ALT_SDMMC_CLKSRC_CARD4_CLK_SOURCE_SET(value) (((value) << 8) & 0x00000300)
1543 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV0 0x0
1549 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV1 0x1
1555 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV2 0x2
1561 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_E_DIV3 0x3
1564 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_LSB 10
1566 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_MSB 11
1568 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_WIDTH 2
1570 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_SET_MSK 0x00000c00
1572 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_CLR_MSK 0xfffff3ff
1574 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_RESET 0x0
1576 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_GET(value) (((value) & 0x00000c00) >> 10)
1578 #define ALT_SDMMC_CLKSRC_CARD5_CLK_SOURCE_SET(value) (((value) << 10) & 0x00000c00)
1616 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV0 0x0
1622 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV1 0x1
1628 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV2 0x2
1634 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_E_DIV3 0x3
1637 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_LSB 12
1639 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_MSB 13
1641 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_WIDTH 2
1643 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_SET_MSK 0x00003000
1645 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_CLR_MSK 0xffffcfff
1647 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_RESET 0x0
1649 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_GET(value) (((value) & 0x00003000) >> 12)
1651 #define ALT_SDMMC_CLKSRC_CARD6_CLK_SOURCE_SET(value) (((value) << 12) & 0x00003000)
1689 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV0 0x0
1695 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV1 0x1
1701 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV2 0x2
1707 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_E_DIV3 0x3
1710 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_LSB 14
1712 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_MSB 15
1714 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_WIDTH 2
1716 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_SET_MSK 0x0000c000
1718 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_CLR_MSK 0xffff3fff
1720 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_RESET 0x0
1722 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_GET(value) (((value) & 0x0000c000) >> 14)
1724 #define ALT_SDMMC_CLKSRC_CARD7_CLK_SOURCE_SET(value) (((value) << 14) & 0x0000c000)
1762 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV0 0x0
1768 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV1 0x1
1774 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV2 0x2
1780 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_E_DIV3 0x3
1783 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_LSB 16
1785 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_MSB 17
1787 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_WIDTH 2
1789 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_SET_MSK 0x00030000
1791 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_CLR_MSK 0xfffcffff
1793 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_RESET 0x0
1795 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_GET(value) (((value) & 0x00030000) >> 16)
1797 #define ALT_SDMMC_CLKSRC_CARD8_CLK_SOURCE_SET(value) (((value) << 16) & 0x00030000)
1835 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV0 0x0
1841 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV1 0x1
1847 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV2 0x2
1853 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_E_DIV3 0x3
1856 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_LSB 18
1858 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_MSB 19
1860 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_WIDTH 2
1862 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_SET_MSK 0x000c0000
1864 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_CLR_MSK 0xfff3ffff
1866 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_RESET 0x0
1868 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_GET(value) (((value) & 0x000c0000) >> 18)
1870 #define ALT_SDMMC_CLKSRC_CARD9_CLK_SOURCE_SET(value) (((value) << 18) & 0x000c0000)
1908 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV0 0x0
1914 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV1 0x1
1920 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV2 0x2
1926 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_E_DIV3 0x3
1929 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_LSB 20
1931 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_MSB 21
1933 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_WIDTH 2
1935 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_SET_MSK 0x00300000
1937 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_CLR_MSK 0xffcfffff
1939 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_RESET 0x0
1941 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_GET(value) (((value) & 0x00300000) >> 20)
1943 #define ALT_SDMMC_CLKSRC_CARD10_CLK_SOURCE_SET(value) (((value) << 20) & 0x00300000)
1981 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV0 0x0
1987 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV1 0x1
1993 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV2 0x2
1999 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_E_DIV3 0x3
2002 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_LSB 22
2004 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_MSB 23
2006 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_WIDTH 2
2008 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_SET_MSK 0x00c00000
2010 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_CLR_MSK 0xff3fffff
2012 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_RESET 0x0
2014 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_GET(value) (((value) & 0x00c00000) >> 22)
2016 #define ALT_SDMMC_CLKSRC_CARD11_CLK_SOURCE_SET(value) (((value) << 22) & 0x00c00000)
2054 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV0 0x0
2060 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV1 0x1
2066 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV2 0x2
2072 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_E_DIV3 0x3
2075 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_LSB 24
2077 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_MSB 25
2079 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_WIDTH 2
2081 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_SET_MSK 0x03000000
2083 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_CLR_MSK 0xfcffffff
2085 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_RESET 0x0
2087 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_GET(value) (((value) & 0x03000000) >> 24)
2089 #define ALT_SDMMC_CLKSRC_CARD12_CLK_SOURCE_SET(value) (((value) << 24) & 0x03000000)
2127 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV0 0x0
2133 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV1 0x1
2139 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV2 0x2
2145 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_E_DIV3 0x3
2148 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_LSB 26
2150 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_MSB 27
2152 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_WIDTH 2
2154 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_SET_MSK 0x0c000000
2156 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_CLR_MSK 0xf3ffffff
2158 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_RESET 0x0
2160 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_GET(value) (((value) & 0x0c000000) >> 26)
2162 #define ALT_SDMMC_CLKSRC_CARD13_CLK_SOURCE_SET(value) (((value) << 26) & 0x0c000000)
2200 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV0 0x0
2206 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV1 0x1
2212 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV2 0x2
2218 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_E_DIV3 0x3
2221 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_LSB 28
2223 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_MSB 29
2225 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_WIDTH 2
2227 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_SET_MSK 0x30000000
2229 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_CLR_MSK 0xcfffffff
2231 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_RESET 0x0
2233 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_GET(value) (((value) & 0x30000000) >> 28)
2235 #define ALT_SDMMC_CLKSRC_CARD14_CLK_SOURCE_SET(value) (((value) << 28) & 0x30000000)
2273 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV0 0x0
2279 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV1 0x1
2285 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV2 0x2
2291 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_E_DIV3 0x3
2294 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_LSB 30
2296 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_MSB 31
2298 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_WIDTH 2
2300 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_SET_MSK 0xc0000000
2302 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_CLR_MSK 0x3fffffff
2304 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_RESET 0x0
2306 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_GET(value) (((value) & 0xc0000000) >> 30)
2308 #define ALT_SDMMC_CLKSRC_CARD15_CLK_SOURCE_SET(value) (((value) << 30) & 0xc0000000)
2310 #ifndef __ASSEMBLY__
2322 struct ALT_SDMMC_CLKSRC_s
2324 const volatile uint32_t CARD0_CLK_SOURCE : 2;
2325 const volatile uint32_t CARD1_CLK_SOURCE : 2;
2326 const volatile uint32_t CARD2_CLK_SOURCE : 2;
2327 const volatile uint32_t CARD3_CLK_SOURCE : 2;
2328 const volatile uint32_t CARD4_CLK_SOURCE : 2;
2329 const volatile uint32_t CARD5_CLK_SOURCE : 2;
2330 const volatile uint32_t CARD6_CLK_SOURCE : 2;
2331 const volatile uint32_t CARD7_CLK_SOURCE : 2;
2332 const volatile uint32_t CARD8_CLK_SOURCE : 2;
2333 const volatile uint32_t CARD9_CLK_SOURCE : 2;
2334 const volatile uint32_t CARD10_CLK_SOURCE : 2;
2335 const volatile uint32_t CARD11_CLK_SOURCE : 2;
2336 const volatile uint32_t CARD12_CLK_SOURCE : 2;
2337 const volatile uint32_t CARD13_CLK_SOURCE : 2;
2338 const volatile uint32_t CARD14_CLK_SOURCE : 2;
2339 const volatile uint32_t CARD15_CLK_SOURCE : 2;
2343 typedef struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
2347 #define ALT_SDMMC_CLKSRC_RESET 0x00000000
2349 #define ALT_SDMMC_CLKSRC_OFST 0xc
2351 #define ALT_SDMMC_CLKSRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKSRC_OFST))
2396 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_DISABLED 0x0
2402 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_E_ENABLED 0x1
2405 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_LSB 0
2407 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_MSB 0
2409 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_WIDTH 1
2411 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_SET_MSK 0x00000001
2413 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_CLR_MSK 0xfffffffe
2415 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_RESET 0x0
2417 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_GET(value) (((value) & 0x00000001) >> 0)
2419 #define ALT_SDMMC_CLKENA_CCLK_ENABLE_0_SET(value) (((value) << 0) & 0x00000001)
2450 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_NON_LOW_POWER 0x0
2456 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_E_LOW_POWER 0x1
2459 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_LSB 16
2461 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_MSB 16
2463 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_WIDTH 1
2465 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_SET_MSK 0x00010000
2467 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_CLR_MSK 0xfffeffff
2469 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_RESET 0x0
2471 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_GET(value) (((value) & 0x00010000) >> 16)
2473 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_0_SET(value) (((value) << 16) & 0x00010000)
2475 #ifndef __ASSEMBLY__
2487 struct ALT_SDMMC_CLKENA_s
2489 volatile uint32_t CCLK_ENABLE_0 : 1;
2491 volatile uint32_t CCLK_LOW_POWER_0 : 1;
2496 typedef struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
2500 #define ALT_SDMMC_CLKENA_RESET 0x00000000
2502 #define ALT_SDMMC_CLKENA_OFST 0x10
2504 #define ALT_SDMMC_CLKENA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CLKENA_OFST))
2530 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_LSB 0
2532 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_MSB 7
2534 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_WIDTH 8
2536 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_SET_MSK 0x000000ff
2538 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_CLR_MSK 0xffffff00
2540 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_RESET 0x40
2542 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_GET(value) (((value) & 0x000000ff) >> 0)
2544 #define ALT_SDMMC_TMOUT_RESPONSE_TIMEOUT_SET(value) (((value) << 0) & 0x000000ff)
2563 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_LSB 8
2565 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_MSB 31
2567 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_WIDTH 24
2569 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_SET_MSK 0xffffff00
2571 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_CLR_MSK 0x000000ff
2573 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_RESET 0xffffff
2575 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_GET(value) (((value) & 0xffffff00) >> 8)
2577 #define ALT_SDMMC_TMOUT_DATA_TIMEOUT_SET(value) (((value) << 8) & 0xffffff00)
2579 #ifndef __ASSEMBLY__
2591 struct ALT_SDMMC_TMOUT_s
2593 volatile uint32_t RESPONSE_TIMEOUT : 8;
2594 volatile uint32_t DATA_TIMEOUT : 24;
2598 typedef struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
2602 #define ALT_SDMMC_TMOUT_RESET 0xffffff40
2604 #define ALT_SDMMC_TMOUT_OFST 0x14
2606 #define ALT_SDMMC_TMOUT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TMOUT_OFST))
2651 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_ONE_BIT 0x0
2657 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_E_FOUR_BIT 0x1
2660 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_LSB 0
2662 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_MSB 0
2664 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_WIDTH 1
2666 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_SET_MSK 0x00000001
2668 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_CLR_MSK 0xfffffffe
2670 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_RESET 0x0
2672 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
2674 #define ALT_SDMMC_CTYPE_CARD0_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
2702 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_NON_8BIT 0x0
2708 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_E_YES_8BIT 0x1
2711 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_LSB 16
2713 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_MSB 16
2715 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_WIDTH 1
2717 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_SET_MSK 0x00010000
2719 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_CLR_MSK 0xfffeffff
2721 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_RESET 0x0
2723 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
2725 #define ALT_SDMMC_CTYPE_CARD0_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
2727 #ifndef __ASSEMBLY__
2739 struct ALT_SDMMC_CTYPE_s
2741 volatile uint32_t CARD0_WIDTH2 : 1;
2743 volatile uint32_t CARD0_WIDTH1 : 1;
2748 typedef struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
2752 #define ALT_SDMMC_CTYPE_RESET 0x00000000
2754 #define ALT_SDMMC_CTYPE_OFST 0x18
2756 #define ALT_SDMMC_CTYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CTYPE_OFST))
2780 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
2782 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
2784 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
2786 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
2788 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
2790 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
2792 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
2794 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
2796 #ifndef __ASSEMBLY__
2808 struct ALT_SDMMC_BLKSIZ_s
2810 volatile uint32_t BLOCK_SIZE : 16;
2815 typedef struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
2819 #define ALT_SDMMC_BLKSIZ_RESET 0x00000200
2821 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
2823 #define ALT_SDMMC_BLKSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BLKSIZ_OFST))
2851 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
2853 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
2855 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
2857 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
2859 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
2861 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
2863 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
2865 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
2867 #ifndef __ASSEMBLY__
2879 struct ALT_SDMMC_BYTCNT_s
2881 volatile uint32_t BYTE_COUNT : 32;
2885 typedef struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
2889 #define ALT_SDMMC_BYTCNT_RESET 0x00000200
2891 #define ALT_SDMMC_BYTCNT_OFST 0x20
2893 #define ALT_SDMMC_BYTCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BYTCNT_OFST))
2960 #define ALT_SDMMC_INTMASK_CD_INT_MASK_E_MASKED 0x0
2966 #define ALT_SDMMC_INTMASK_CD_INT_MASK_E_ENABLED 0x1
2969 #define ALT_SDMMC_INTMASK_CD_INT_MASK_LSB 0
2971 #define ALT_SDMMC_INTMASK_CD_INT_MASK_MSB 0
2973 #define ALT_SDMMC_INTMASK_CD_INT_MASK_WIDTH 1
2975 #define ALT_SDMMC_INTMASK_CD_INT_MASK_SET_MSK 0x00000001
2977 #define ALT_SDMMC_INTMASK_CD_INT_MASK_CLR_MSK 0xfffffffe
2979 #define ALT_SDMMC_INTMASK_CD_INT_MASK_RESET 0x0
2981 #define ALT_SDMMC_INTMASK_CD_INT_MASK_GET(value) (((value) & 0x00000001) >> 0)
2983 #define ALT_SDMMC_INTMASK_CD_INT_MASK_SET(value) (((value) << 0) & 0x00000001)
3007 #define ALT_SDMMC_INTMASK_RE_INT_MASK_E_MASKED 0x0
3013 #define ALT_SDMMC_INTMASK_RE_INT_MASK_E_ENABLED 0x1
3016 #define ALT_SDMMC_INTMASK_RE_INT_MASK_LSB 1
3018 #define ALT_SDMMC_INTMASK_RE_INT_MASK_MSB 1
3020 #define ALT_SDMMC_INTMASK_RE_INT_MASK_WIDTH 1
3022 #define ALT_SDMMC_INTMASK_RE_INT_MASK_SET_MSK 0x00000002
3024 #define ALT_SDMMC_INTMASK_RE_INT_MASK_CLR_MSK 0xfffffffd
3026 #define ALT_SDMMC_INTMASK_RE_INT_MASK_RESET 0x0
3028 #define ALT_SDMMC_INTMASK_RE_INT_MASK_GET(value) (((value) & 0x00000002) >> 1)
3030 #define ALT_SDMMC_INTMASK_RE_INT_MASK_SET(value) (((value) << 1) & 0x00000002)
3054 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_E_MASKED 0x0
3060 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_E_ENABLED 0x1
3063 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_LSB 2
3065 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_MSB 2
3067 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_WIDTH 1
3069 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_SET_MSK 0x00000004
3071 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_CLR_MSK 0xfffffffb
3073 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_RESET 0x0
3075 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_GET(value) (((value) & 0x00000004) >> 2)
3077 #define ALT_SDMMC_INTMASK_CMD_INT_MASK_SET(value) (((value) << 2) & 0x00000004)
3101 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_E_MASKED 0x0
3107 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_E_ENABLED 0x1
3110 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_LSB 3
3112 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_MSB 3
3114 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_WIDTH 1
3116 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_SET_MSK 0x00000008
3118 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_CLR_MSK 0xfffffff7
3120 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_RESET 0x0
3122 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_GET(value) (((value) & 0x00000008) >> 3)
3124 #define ALT_SDMMC_INTMASK_DTO_INT_MASK_SET(value) (((value) << 3) & 0x00000008)
3148 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_MASKED 0x0
3154 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_E_ENABLED 0x1
3157 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_LSB 4
3159 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_MSB 4
3161 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_WIDTH 1
3163 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_SET_MSK 0x00000010
3165 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_CLR_MSK 0xffffffef
3167 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_RESET 0x0
3169 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_GET(value) (((value) & 0x00000010) >> 4)
3171 #define ALT_SDMMC_INTMASK_TXDR_INT_MASK_SET(value) (((value) << 4) & 0x00000010)
3195 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_MASKED 0x0
3201 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_E_ENABLED 0x1
3204 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_LSB 5
3206 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_MSB 5
3208 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_WIDTH 1
3210 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_SET_MSK 0x00000020
3212 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_CLR_MSK 0xffffffdf
3214 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_RESET 0x0
3216 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_GET(value) (((value) & 0x00000020) >> 5)
3218 #define ALT_SDMMC_INTMASK_RXDR_INT_MASK_SET(value) (((value) << 5) & 0x00000020)
3242 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_MASKED 0x0
3248 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_E_ENABLED 0x1
3251 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_LSB 6
3253 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_MSB 6
3255 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_WIDTH 1
3257 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_SET_MSK 0x00000040
3259 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_CLR_MSK 0xffffffbf
3261 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_RESET 0x0
3263 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_GET(value) (((value) & 0x00000040) >> 6)
3265 #define ALT_SDMMC_INTMASK_RCRC_INT_MASK_SET(value) (((value) << 6) & 0x00000040)
3289 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_MASKED 0x0
3295 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_E_ENABLED 0x1
3298 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_LSB 7
3300 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_MSB 7
3302 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_WIDTH 1
3304 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_SET_MSK 0x00000080
3306 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_CLR_MSK 0xffffff7f
3308 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_RESET 0x0
3310 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_GET(value) (((value) & 0x00000080) >> 7)
3312 #define ALT_SDMMC_INTMASK_DCRC_INT_MASK_SET(value) (((value) << 7) & 0x00000080)
3336 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_E_MASKED 0x0
3342 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_E_ENABLED 0x1
3345 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_LSB 8
3347 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_MSB 8
3349 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_WIDTH 1
3351 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_SET_MSK 0x00000100
3353 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_CLR_MSK 0xfffffeff
3355 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_RESET 0x0
3357 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_GET(value) (((value) & 0x00000100) >> 8)
3359 #define ALT_SDMMC_INTMASK_RTO_INT_MASK_SET(value) (((value) << 8) & 0x00000100)
3383 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_MASKED 0x0
3389 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_E_ENABLED 0x1
3392 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_LSB 9
3394 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_MSB 9
3396 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_WIDTH 1
3398 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_SET_MSK 0x00000200
3400 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_CLR_MSK 0xfffffdff
3402 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_RESET 0x0
3404 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_GET(value) (((value) & 0x00000200) >> 9)
3406 #define ALT_SDMMC_INTMASK_DRTO_INT_MASK_SET(value) (((value) << 9) & 0x00000200)
3430 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_E_MASKED 0x0
3436 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_E_ENABLED 0x1
3439 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_LSB 10
3441 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_MSB 10
3443 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_WIDTH 1
3445 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_SET_MSK 0x00000400
3447 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_CLR_MSK 0xfffffbff
3449 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_RESET 0x0
3451 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_GET(value) (((value) & 0x00000400) >> 10)
3453 #define ALT_SDMMC_INTMASK_HTO_INT_MASK_SET(value) (((value) << 10) & 0x00000400)
3477 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_MASKED 0x0
3483 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_E_ENABLED 0x1
3486 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_LSB 11
3488 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_MSB 11
3490 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_WIDTH 1
3492 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_SET_MSK 0x00000800
3494 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_CLR_MSK 0xfffff7ff
3496 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_RESET 0x0
3498 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_GET(value) (((value) & 0x00000800) >> 11)
3500 #define ALT_SDMMC_INTMASK_FRUN_INT_MASK_SET(value) (((value) << 11) & 0x00000800)
3524 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_E_MASKED 0x0
3530 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_E_ENABLED 0x1
3533 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_LSB 12
3535 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_MSB 12
3537 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_WIDTH 1
3539 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_SET_MSK 0x00001000
3541 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_CLR_MSK 0xffffefff
3543 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_RESET 0x0
3545 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_GET(value) (((value) & 0x00001000) >> 12)
3547 #define ALT_SDMMC_INTMASK_HLE_INT_MASK_SET(value) (((value) << 12) & 0x00001000)
3571 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_MASKED 0x0
3577 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_E_ENABLED 0x1
3580 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_LSB 13
3582 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_MSB 13
3584 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_WIDTH 1
3586 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_SET_MSK 0x00002000
3588 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_CLR_MSK 0xffffdfff
3590 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_RESET 0x0
3592 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_GET(value) (((value) & 0x00002000) >> 13)
3594 #define ALT_SDMMC_INTMASK_SBE_BCI_INT_MASK_SET(value) (((value) << 13) & 0x00002000)
3618 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_E_MASKED 0x0
3624 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_E_ENABLED 0x1
3627 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_LSB 14
3629 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_MSB 14
3631 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_WIDTH 1
3633 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_SET_MSK 0x00004000
3635 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_CLR_MSK 0xffffbfff
3637 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_RESET 0x0
3639 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_GET(value) (((value) & 0x00004000) >> 14)
3641 #define ALT_SDMMC_INTMASK_ACD_INT_MASK_SET(value) (((value) << 14) & 0x00004000)
3665 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_E_MASKED 0x0
3671 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_E_ENABLED 0x1
3674 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_LSB 15
3676 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_MSB 15
3678 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_WIDTH 1
3680 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_SET_MSK 0x00008000
3682 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_CLR_MSK 0xffff7fff
3684 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_RESET 0x0
3686 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_GET(value) (((value) & 0x00008000) >> 15)
3688 #define ALT_SDMMC_INTMASK_EBE_INT_MASK_SET(value) (((value) << 15) & 0x00008000)
3716 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_MASKED 0x0
3722 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_E_ENABLED 0x1
3725 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_LSB 16
3727 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_MSB 16
3729 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_WIDTH 1
3731 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_SET_MSK 0x00010000
3733 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_CLR_MSK 0xfffeffff
3735 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_RESET 0x0
3737 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_GET(value) (((value) & 0x00010000) >> 16)
3739 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD0_SET(value) (((value) << 16) & 0x00010000)
3767 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_MASKED 0x0
3773 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_E_ENABLED 0x1
3776 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_LSB 17
3778 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_MSB 17
3780 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_WIDTH 1
3782 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_SET_MSK 0x00020000
3784 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_CLR_MSK 0xfffdffff
3786 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_RESET 0x0
3788 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_GET(value) (((value) & 0x00020000) >> 17)
3790 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD1_SET(value) (((value) << 17) & 0x00020000)
3818 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_MASKED 0x0
3824 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_E_ENABLED 0x1
3827 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_LSB 18
3829 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_MSB 18
3831 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_WIDTH 1
3833 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_SET_MSK 0x00040000
3835 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_CLR_MSK 0xfffbffff
3837 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_RESET 0x0
3839 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_GET(value) (((value) & 0x00040000) >> 18)
3841 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD2_SET(value) (((value) << 18) & 0x00040000)
3869 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_MASKED 0x0
3875 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_E_ENABLED 0x1
3878 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_LSB 19
3880 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_MSB 19
3882 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_WIDTH 1
3884 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_SET_MSK 0x00080000
3886 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_CLR_MSK 0xfff7ffff
3888 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_RESET 0x0
3890 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_GET(value) (((value) & 0x00080000) >> 19)
3892 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD3_SET(value) (((value) << 19) & 0x00080000)
3920 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_MASKED 0x0
3926 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_E_ENABLED 0x1
3929 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_LSB 20
3931 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_MSB 20
3933 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_WIDTH 1
3935 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_SET_MSK 0x00100000
3937 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_CLR_MSK 0xffefffff
3939 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_RESET 0x0
3941 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_GET(value) (((value) & 0x00100000) >> 20)
3943 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD4_SET(value) (((value) << 20) & 0x00100000)
3971 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_MASKED 0x0
3977 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_E_ENABLED 0x1
3980 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_LSB 21
3982 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_MSB 21
3984 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_WIDTH 1
3986 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_SET_MSK 0x00200000
3988 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_CLR_MSK 0xffdfffff
3990 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_RESET 0x0
3992 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_GET(value) (((value) & 0x00200000) >> 21)
3994 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD5_SET(value) (((value) << 21) & 0x00200000)
4022 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_MASKED 0x0
4028 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_E_ENABLED 0x1
4031 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_LSB 22
4033 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_MSB 22
4035 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_WIDTH 1
4037 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_SET_MSK 0x00400000
4039 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_CLR_MSK 0xffbfffff
4041 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_RESET 0x0
4043 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_GET(value) (((value) & 0x00400000) >> 22)
4045 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD6_SET(value) (((value) << 22) & 0x00400000)
4073 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_MASKED 0x0
4079 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_E_ENABLED 0x1
4082 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_LSB 23
4084 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_MSB 23
4086 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_WIDTH 1
4088 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_SET_MSK 0x00800000
4090 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_CLR_MSK 0xff7fffff
4092 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_RESET 0x0
4094 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_GET(value) (((value) & 0x00800000) >> 23)
4096 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD7_SET(value) (((value) << 23) & 0x00800000)
4124 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_MASKED 0x0
4130 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_E_ENABLED 0x1
4133 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_LSB 24
4135 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_MSB 24
4137 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_WIDTH 1
4139 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_SET_MSK 0x01000000
4141 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_CLR_MSK 0xfeffffff
4143 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_RESET 0x0
4145 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_GET(value) (((value) & 0x01000000) >> 24)
4147 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD8_SET(value) (((value) << 24) & 0x01000000)
4175 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_MASKED 0x0
4181 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_E_ENABLED 0x1
4184 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_LSB 25
4186 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_MSB 25
4188 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_WIDTH 1
4190 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_SET_MSK 0x02000000
4192 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_CLR_MSK 0xfdffffff
4194 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_RESET 0x0
4196 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_GET(value) (((value) & 0x02000000) >> 25)
4198 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD9_SET(value) (((value) << 25) & 0x02000000)
4226 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_MASKED 0x0
4232 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_E_ENABLED 0x1
4235 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_LSB 26
4237 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_MSB 26
4239 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_WIDTH 1
4241 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_SET_MSK 0x04000000
4243 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_CLR_MSK 0xfbffffff
4245 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_RESET 0x0
4247 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_GET(value) (((value) & 0x04000000) >> 26)
4249 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD10_SET(value) (((value) << 26) & 0x04000000)
4277 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_MASKED 0x0
4283 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_E_ENABLED 0x1
4286 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_LSB 27
4288 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_MSB 27
4290 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_WIDTH 1
4292 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_SET_MSK 0x08000000
4294 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_CLR_MSK 0xf7ffffff
4296 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_RESET 0x0
4298 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_GET(value) (((value) & 0x08000000) >> 27)
4300 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD11_SET(value) (((value) << 27) & 0x08000000)
4328 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_MASKED 0x0
4334 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_E_ENABLED 0x1
4337 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_LSB 28
4339 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_MSB 28
4341 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_WIDTH 1
4343 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_SET_MSK 0x10000000
4345 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_CLR_MSK 0xefffffff
4347 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_RESET 0x0
4349 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_GET(value) (((value) & 0x10000000) >> 28)
4351 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD12_SET(value) (((value) << 28) & 0x10000000)
4379 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_MASKED 0x0
4385 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_E_ENABLED 0x1
4388 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_LSB 29
4390 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_MSB 29
4392 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_WIDTH 1
4394 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_SET_MSK 0x20000000
4396 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_CLR_MSK 0xdfffffff
4398 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_RESET 0x0
4400 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_GET(value) (((value) & 0x20000000) >> 29)
4402 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD13_SET(value) (((value) << 29) & 0x20000000)
4430 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_MASKED 0x0
4436 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_E_ENABLED 0x1
4439 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_LSB 30
4441 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_MSB 30
4443 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_WIDTH 1
4445 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_SET_MSK 0x40000000
4447 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_CLR_MSK 0xbfffffff
4449 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_RESET 0x0
4451 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_GET(value) (((value) & 0x40000000) >> 30)
4453 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD14_SET(value) (((value) << 30) & 0x40000000)
4481 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_MASKED 0x0
4487 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_E_ENABLED 0x1
4490 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_LSB 31
4492 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_MSB 31
4494 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_WIDTH 1
4496 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_SET_MSK 0x80000000
4498 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_CLR_MSK 0x7fffffff
4500 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_RESET 0x0
4502 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_GET(value) (((value) & 0x80000000) >> 31)
4504 #define ALT_SDMMC_INTMASK_SDIO_INT_MASK_CARD15_SET(value) (((value) << 31) & 0x80000000)
4506 #ifndef __ASSEMBLY__
4518 struct ALT_SDMMC_INTMASK_s
4520 volatile uint32_t CD_INT_MASK : 1;
4521 volatile uint32_t RE_INT_MASK : 1;
4522 volatile uint32_t CMD_INT_MASK : 1;
4523 volatile uint32_t DTO_INT_MASK : 1;
4524 volatile uint32_t TXDR_INT_MASK : 1;
4525 volatile uint32_t RXDR_INT_MASK : 1;
4526 volatile uint32_t RCRC_INT_MASK : 1;
4527 volatile uint32_t DCRC_INT_MASK : 1;
4528 volatile uint32_t RTO_INT_MASK : 1;
4529 volatile uint32_t DRTO_INT_MASK : 1;
4530 volatile uint32_t HTO_INT_MASK : 1;
4531 volatile uint32_t FRUN_INT_MASK : 1;
4532 volatile uint32_t HLE_INT_MASK : 1;
4533 volatile uint32_t SBE_BCI_INT_MASK : 1;
4534 volatile uint32_t ACD_INT_MASK : 1;
4535 volatile uint32_t EBE_INT_MASK : 1;
4536 volatile uint32_t SDIO_INT_MASK_CARD0 : 1;
4537 volatile uint32_t SDIO_INT_MASK_CARD1 : 1;
4538 volatile uint32_t SDIO_INT_MASK_CARD2 : 1;
4539 volatile uint32_t SDIO_INT_MASK_CARD3 : 1;
4540 volatile uint32_t SDIO_INT_MASK_CARD4 : 1;
4541 volatile uint32_t SDIO_INT_MASK_CARD5 : 1;
4542 volatile uint32_t SDIO_INT_MASK_CARD6 : 1;
4543 volatile uint32_t SDIO_INT_MASK_CARD7 : 1;
4544 volatile uint32_t SDIO_INT_MASK_CARD8 : 1;
4545 volatile uint32_t SDIO_INT_MASK_CARD9 : 1;
4546 volatile uint32_t SDIO_INT_MASK_CARD10 : 1;
4547 volatile uint32_t SDIO_INT_MASK_CARD11 : 1;
4548 volatile uint32_t SDIO_INT_MASK_CARD12 : 1;
4549 volatile uint32_t SDIO_INT_MASK_CARD13 : 1;
4550 volatile uint32_t SDIO_INT_MASK_CARD14 : 1;
4551 volatile uint32_t SDIO_INT_MASK_CARD15 : 1;
4555 typedef struct ALT_SDMMC_INTMASK_s ALT_SDMMC_INTMASK_t;
4559 #define ALT_SDMMC_INTMASK_RESET 0x00000000
4561 #define ALT_SDMMC_INTMASK_OFST 0x24
4563 #define ALT_SDMMC_INTMASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_INTMASK_OFST))
4586 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
4588 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
4590 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
4592 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
4594 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
4596 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
4598 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
4600 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
4602 #ifndef __ASSEMBLY__
4614 struct ALT_SDMMC_CMDARG_s
4616 volatile uint32_t CMD_ARG : 32;
4620 typedef struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
4624 #define ALT_SDMMC_CMDARG_RESET 0x00000000
4626 #define ALT_SDMMC_CMDARG_OFST 0x28
4628 #define ALT_SDMMC_CMDARG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CMDARG_OFST))
4673 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
4675 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
4677 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
4679 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
4681 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
4683 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
4685 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
4687 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
4711 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NO_RESP 0x0
4717 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP_EXP 0x1
4720 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
4722 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
4724 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
4726 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
4728 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
4730 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
4732 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
4734 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
4758 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_E_SHORT_RESP 0x0
4764 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_E_LONG_RESP 0x1
4767 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_LSB 7
4769 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_MSB 7
4771 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_WIDTH 1
4773 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_SET_MSK 0x00000080
4775 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_CLR_MSK 0xffffff7f
4777 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_RESET 0x0
4779 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_GET(value) (((value) & 0x00000080) >> 7)
4781 #define ALT_SDMMC_CMD_RESPONSE_LENGTH_SET(value) (((value) << 7) & 0x00000080)
4808 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_FALSE 0x0
4814 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_TRUE 0x1
4817 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
4819 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
4821 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
4823 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
4825 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
4827 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
4829 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
4831 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
4855 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_FALSE 0x0
4861 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_TRUE 0x1
4864 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
4866 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
4868 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
4870 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
4872 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
4874 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
4876 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
4878 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
4904 #define ALT_SDMMC_CMD_READ_WRITE_E_READ 0x0
4910 #define ALT_SDMMC_CMD_READ_WRITE_E_WRITE 0x1
4913 #define ALT_SDMMC_CMD_READ_WRITE_LSB 10
4915 #define ALT_SDMMC_CMD_READ_WRITE_MSB 10
4917 #define ALT_SDMMC_CMD_READ_WRITE_WIDTH 1
4919 #define ALT_SDMMC_CMD_READ_WRITE_SET_MSK 0x00000400
4921 #define ALT_SDMMC_CMD_READ_WRITE_CLR_MSK 0xfffffbff
4923 #define ALT_SDMMC_CMD_READ_WRITE_RESET 0x0
4925 #define ALT_SDMMC_CMD_READ_WRITE_GET(value) (((value) & 0x00000400) >> 10)
4927 #define ALT_SDMMC_CMD_READ_WRITE_SET(value) (((value) << 10) & 0x00000400)
4953 #define ALT_SDMMC_CMD_TRANSFER_MODE_E_BLOCK 0x0
4959 #define ALT_SDMMC_CMD_TRANSFER_MODE_E_STREAM 0x1
4962 #define ALT_SDMMC_CMD_TRANSFER_MODE_LSB 11
4964 #define ALT_SDMMC_CMD_TRANSFER_MODE_MSB 11
4966 #define ALT_SDMMC_CMD_TRANSFER_MODE_WIDTH 1
4968 #define ALT_SDMMC_CMD_TRANSFER_MODE_SET_MSK 0x00000800
4970 #define ALT_SDMMC_CMD_TRANSFER_MODE_CLR_MSK 0xfffff7ff
4972 #define ALT_SDMMC_CMD_TRANSFER_MODE_RESET 0x0
4974 #define ALT_SDMMC_CMD_TRANSFER_MODE_GET(value) (((value) & 0x00000800) >> 11)
4976 #define ALT_SDMMC_CMD_TRANSFER_MODE_SET(value) (((value) << 11) & 0x00000800)
5015 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_FALSE 0x0
5021 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_TRUE 0x1
5024 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
5026 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
5028 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
5030 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
5032 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
5034 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
5036 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
5038 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
5071 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NO_WAIT 0x0
5077 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
5080 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
5082 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
5084 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
5086 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
5088 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
5090 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
5092 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
5094 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
5132 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_E_FALSE 0x0
5138 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_E_TRUE 0x1
5141 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_LSB 14
5143 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_MSB 14
5145 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_WIDTH 1
5147 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_SET_MSK 0x00004000
5149 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_CLR_MSK 0xffffbfff
5151 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_RESET 0x0
5153 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_GET(value) (((value) & 0x00004000) >> 14)
5155 #define ALT_SDMMC_CMD_STOP_ABORT_CMD_SET(value) (((value) << 14) & 0x00004000)
5186 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_FALSE 0x0
5192 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_TRUE 0x1
5195 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
5197 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
5199 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
5201 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
5203 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
5205 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
5207 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
5209 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
5230 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
5232 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
5234 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
5236 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
5238 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
5240 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
5242 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
5244 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
5281 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_FALSE 0x0
5287 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_E_TRUE 0x1
5290 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_LSB 21
5292 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MSB 21
5294 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_WIDTH 1
5296 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SET_MSK 0x00200000
5298 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_CLR_MSK 0xffdfffff
5300 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_RESET 0x0
5302 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
5304 #define ALT_SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SET(value) (((value) << 21) & 0x00200000)
5338 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_NO_READ 0x0
5344 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_E_READ 0x1
5347 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_LSB 22
5349 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_MSB 22
5351 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_WIDTH 1
5353 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_SET_MSK 0x00400000
5355 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_CLR_MSK 0xffbfffff
5357 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_RESET 0x0
5359 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
5361 #define ALT_SDMMC_CMD_READ_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
5396 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_FALSE 0x0
5402 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_TRUE 0x1
5405 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
5407 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
5409 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
5411 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
5413 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
5415 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
5417 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
5419 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
5445 #define ALT_SDMMC_CMD_ENABLE_BOOT_E_FALSE 0x0
5451 #define ALT_SDMMC_CMD_ENABLE_BOOT_E_TRUE 0x1
5454 #define ALT_SDMMC_CMD_ENABLE_BOOT_LSB 24
5456 #define ALT_SDMMC_CMD_ENABLE_BOOT_MSB 24
5458 #define ALT_SDMMC_CMD_ENABLE_BOOT_WIDTH 1
5460 #define ALT_SDMMC_CMD_ENABLE_BOOT_SET_MSK 0x01000000
5462 #define ALT_SDMMC_CMD_ENABLE_BOOT_CLR_MSK 0xfeffffff
5464 #define ALT_SDMMC_CMD_ENABLE_BOOT_RESET 0x0
5466 #define ALT_SDMMC_CMD_ENABLE_BOOT_GET(value) (((value) & 0x01000000) >> 24)
5468 #define ALT_SDMMC_CMD_ENABLE_BOOT_SET(value) (((value) << 24) & 0x01000000)
5493 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_FALSE 0x0
5499 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_TRUE 0x1
5502 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
5504 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
5506 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
5508 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
5510 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
5512 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
5514 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
5516 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
5539 #define ALT_SDMMC_CMD_DISABLE_BOOT_E_FALSE 0x0
5545 #define ALT_SDMMC_CMD_DISABLE_BOOT_E_TRUE 0x1
5548 #define ALT_SDMMC_CMD_DISABLE_BOOT_LSB 26
5550 #define ALT_SDMMC_CMD_DISABLE_BOOT_MSB 26
5552 #define ALT_SDMMC_CMD_DISABLE_BOOT_WIDTH 1
5554 #define ALT_SDMMC_CMD_DISABLE_BOOT_SET_MSK 0x04000000
5556 #define ALT_SDMMC_CMD_DISABLE_BOOT_CLR_MSK 0xfbffffff
5558 #define ALT_SDMMC_CMD_DISABLE_BOOT_RESET 0x0
5560 #define ALT_SDMMC_CMD_DISABLE_BOOT_GET(value) (((value) & 0x04000000) >> 26)
5562 #define ALT_SDMMC_CMD_DISABLE_BOOT_SET(value) (((value) << 26) & 0x04000000)
5588 #define ALT_SDMMC_CMD_BOOT_MODE_E_MANDATORY 0x0
5594 #define ALT_SDMMC_CMD_BOOT_MODE_E_ALTERNATE 0x1
5597 #define ALT_SDMMC_CMD_BOOT_MODE_LSB 27
5599 #define ALT_SDMMC_CMD_BOOT_MODE_MSB 27
5601 #define ALT_SDMMC_CMD_BOOT_MODE_WIDTH 1
5603 #define ALT_SDMMC_CMD_BOOT_MODE_SET_MSK 0x08000000
5605 #define ALT_SDMMC_CMD_BOOT_MODE_CLR_MSK 0xf7ffffff
5607 #define ALT_SDMMC_CMD_BOOT_MODE_RESET 0x0
5609 #define ALT_SDMMC_CMD_BOOT_MODE_GET(value) (((value) & 0x08000000) >> 27)
5611 #define ALT_SDMMC_CMD_BOOT_MODE_SET(value) (((value) << 27) & 0x08000000)
5637 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_FALSE 0x0
5643 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_TRUE 0x1
5646 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
5648 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
5650 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
5652 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
5654 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
5656 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
5658 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
5660 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
5688 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_FALSE 0x0
5694 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_TRUE 0x1
5697 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
5699 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
5701 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
5703 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
5705 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
5707 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
5709 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
5711 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
5741 #define ALT_SDMMC_CMD_START_CMD_E_FALSE 0x0
5747 #define ALT_SDMMC_CMD_START_CMD_E_TRUE 0x1
5750 #define ALT_SDMMC_CMD_START_CMD_LSB 31
5752 #define ALT_SDMMC_CMD_START_CMD_MSB 31
5754 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
5756 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
5758 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
5760 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
5762 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
5764 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
5766 #ifndef __ASSEMBLY__
5778 struct ALT_SDMMC_CMD_s
5780 volatile uint32_t CMD_INDEX : 6;
5781 volatile uint32_t RESPONSE_EXPECT : 1;
5782 volatile uint32_t RESPONSE_LENGTH : 1;
5783 volatile uint32_t CHECK_RESPONSE_CRC : 1;
5784 volatile uint32_t DATA_EXPECTED : 1;
5785 volatile uint32_t READ_WRITE : 1;
5786 volatile uint32_t TRANSFER_MODE : 1;
5787 volatile uint32_t SEND_AUTO_STOP : 1;
5788 volatile uint32_t WAIT_PRVDATA_COMPLETE : 1;
5789 volatile uint32_t STOP_ABORT_CMD : 1;
5790 volatile uint32_t SEND_INITIALIZATION : 1;
5791 volatile uint32_t CARD_NUMBER : 5;
5792 volatile uint32_t UPDATE_CLOCK_REGISTERS_ONLY : 1;
5793 volatile uint32_t READ_CEATA_DEVICE : 1;
5794 volatile uint32_t CCS_EXPECTED : 1;
5795 volatile uint32_t ENABLE_BOOT : 1;
5796 volatile uint32_t EXPECT_BOOT_ACK : 1;
5797 volatile uint32_t DISABLE_BOOT : 1;
5798 volatile uint32_t BOOT_MODE : 1;
5799 volatile uint32_t VOLT_SWITCH : 1;
5800 volatile uint32_t USE_HOLD_REG : 1;
5802 volatile uint32_t START_CMD : 1;
5806 typedef struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
5810 #define ALT_SDMMC_CMD_RESET 0x20000000
5812 #define ALT_SDMMC_CMD_OFST 0x2c
5814 #define ALT_SDMMC_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CMD_OFST))
5837 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
5839 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
5841 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
5843 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
5845 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
5847 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
5849 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
5851 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
5853 #ifndef __ASSEMBLY__
5865 struct ALT_SDMMC_RESP0_s
5867 const volatile uint32_t RESPONSE0 : 32;
5871 typedef struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
5875 #define ALT_SDMMC_RESP0_RESET 0x00000000
5877 #define ALT_SDMMC_RESP0_OFST 0x30
5879 #define ALT_SDMMC_RESP0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP0_OFST))
5907 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
5909 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
5911 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
5913 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
5915 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
5917 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
5919 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
5921 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
5923 #ifndef __ASSEMBLY__
5935 struct ALT_SDMMC_RESP1_s
5937 const volatile uint32_t RESPONSE1 : 32;
5941 typedef struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
5945 #define ALT_SDMMC_RESP1_RESET 0x00000000
5947 #define ALT_SDMMC_RESP1_OFST 0x34
5949 #define ALT_SDMMC_RESP1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP1_OFST))
5972 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
5974 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
5976 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
5978 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
5980 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
5982 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
5984 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
5986 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
5988 #ifndef __ASSEMBLY__
6000 struct ALT_SDMMC_RESP2_s
6002 const volatile uint32_t RESPONSE2 : 32;
6006 typedef struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
6010 #define ALT_SDMMC_RESP2_RESET 0x00000000
6012 #define ALT_SDMMC_RESP2_OFST 0x38
6014 #define ALT_SDMMC_RESP2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP2_OFST))
6037 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
6039 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
6041 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
6043 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
6045 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
6047 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
6049 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
6051 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
6053 #ifndef __ASSEMBLY__
6065 struct ALT_SDMMC_RESP3_s
6067 const volatile uint32_t RESPONSE3 : 32;
6071 typedef struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
6075 #define ALT_SDMMC_RESP3_RESET 0x00000000
6077 #define ALT_SDMMC_RESP3_OFST 0x3c
6079 #define ALT_SDMMC_RESP3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RESP3_OFST))
6154 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_DISABLED 0x0
6161 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_E_ENABLED 0x1
6164 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_LSB 0
6166 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_MSB 0
6168 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_WIDTH 1
6170 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_SET_MSK 0x00000001
6172 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_CLR_MSK 0xfffffffe
6174 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_RESET 0x0
6176 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_GET(value) (((value) & 0x00000001) >> 0)
6178 #define ALT_SDMMC_MINTSTS_CARD_DETECT_INTERRUPT_SET(value) (((value) << 0) & 0x00000001)
6202 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_DISABLED 0x0
6209 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_E_ENABLED 0x1
6212 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_LSB 1
6214 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_MSB 1
6216 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_WIDTH 1
6218 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_SET_MSK 0x00000002
6220 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_CLR_MSK 0xfffffffd
6222 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_RESET 0x0
6224 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_GET(value) (((value) & 0x00000002) >> 1)
6226 #define ALT_SDMMC_MINTSTS_RESPONSE_ERROR_INTERRUPT_SET(value) (((value) << 1) & 0x00000002)
6250 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_DISABLED 0x0
6257 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_E_ENABLED 0x1
6260 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_LSB 2
6262 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_MSB 2
6264 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_WIDTH 1
6266 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_SET_MSK 0x00000004
6268 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_CLR_MSK 0xfffffffb
6270 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_RESET 0x0
6272 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_GET(value) (((value) & 0x00000004) >> 2)
6274 #define ALT_SDMMC_MINTSTS_COMMAND_DONE_INTERRUPT_SET(value) (((value) << 2) & 0x00000004)
6298 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_DISABLED 0x0
6305 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_E_ENABLED 0x1
6308 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_LSB 3
6310 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_MSB 3
6312 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_WIDTH 1
6314 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_SET_MSK 0x00000008
6316 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_CLR_MSK 0xfffffff7
6318 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_RESET 0x0
6320 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_GET(value) (((value) & 0x00000008) >> 3)
6322 #define ALT_SDMMC_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT_SET(value) (((value) << 3) & 0x00000008)
6346 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_DISABLED 0x0
6353 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_E_ENABLED 0x1
6356 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_LSB 4
6358 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_MSB 4
6360 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_WIDTH 1
6362 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_SET_MSK 0x00000010
6364 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_CLR_MSK 0xffffffef
6366 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_RESET 0x0
6368 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_GET(value) (((value) & 0x00000010) >> 4)
6370 #define ALT_SDMMC_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT_SET(value) (((value) << 4) & 0x00000010)
6394 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_DISABLED 0x0
6401 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_E_ENABLED 0x1
6404 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_LSB 5
6406 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_MSB 5
6408 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_WIDTH 1
6410 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_SET_MSK 0x00000020
6412 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_CLR_MSK 0xffffffdf
6414 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_RESET 0x0
6416 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_GET(value) (((value) & 0x00000020) >> 5)
6418 #define ALT_SDMMC_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT_SET(value) (((value) << 5) & 0x00000020)
6442 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_DISABLED 0x0
6449 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_E_ENABLED 0x1
6452 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_LSB 6
6454 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_MSB 6
6456 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_WIDTH 1
6458 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_SET_MSK 0x00000040
6460 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_CLR_MSK 0xffffffbf
6462 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_RESET 0x0
6464 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_GET(value) (((value) & 0x00000040) >> 6)
6466 #define ALT_SDMMC_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT_SET(value) (((value) << 6) & 0x00000040)
6490 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_DISABLED 0x0
6497 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_E_ENABLED 0x1
6500 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_LSB 7
6502 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_MSB 7
6504 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_WIDTH 1
6506 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_SET_MSK 0x00000080
6508 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_CLR_MSK 0xffffff7f
6510 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_RESET 0x0
6512 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_GET(value) (((value) & 0x00000080) >> 7)
6514 #define ALT_SDMMC_MINTSTS_DATA_CRC_ERROR_INTERRUPT_SET(value) (((value) << 7) & 0x00000080)
6538 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6545 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6548 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_LSB 8
6550 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_MSB 8
6552 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_WIDTH 1
6554 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_SET_MSK 0x00000100
6556 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffeff
6558 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_RESET 0x0
6560 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000100) >> 8)
6562 #define ALT_SDMMC_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT_SET(value) (((value) << 8) & 0x00000100)
6586 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6593 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6596 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_LSB 9
6598 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_MSB 9
6600 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_WIDTH 1
6602 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_SET_MSK 0x00000200
6604 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffdff
6606 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_RESET 0x0
6608 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000200) >> 9)
6610 #define ALT_SDMMC_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT_SET(value) (((value) << 9) & 0x00000200)
6634 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_DISABLED 0x0
6641 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_E_ENABLED 0x1
6644 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_LSB 10
6646 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_MSB 10
6648 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_WIDTH 1
6650 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_SET_MSK 0x00000400
6652 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_CLR_MSK 0xfffffbff
6654 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_RESET 0x0
6656 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_GET(value) (((value) & 0x00000400) >> 10)
6658 #define ALT_SDMMC_MINTSTS_HOST_TIMEOUT_INTERRUPT_SET(value) (((value) << 10) & 0x00000400)
6682 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_DISABLED 0x0
6689 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_E_ENABLED 0x1
6692 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_LSB 11
6694 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_MSB 11
6696 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_WIDTH 1
6698 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_SET_MSK 0x00000800
6700 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_CLR_MSK 0xfffff7ff
6702 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_RESET 0x0
6704 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_GET(value) (((value) & 0x00000800) >> 11)
6706 #define ALT_SDMMC_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT_SET(value) (((value) << 11) & 0x00000800)
6730 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_DISABLED 0x0
6737 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_E_ENABLED 0x1
6740 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_LSB 12
6742 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_MSB 12
6744 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_WIDTH 1
6746 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_SET_MSK 0x00001000
6748 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_CLR_MSK 0xffffefff
6750 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_RESET 0x0
6752 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_GET(value) (((value) & 0x00001000) >> 12)
6754 #define ALT_SDMMC_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT_SET(value) (((value) << 12) & 0x00001000)
6778 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_DISABLED 0x0
6785 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_E_ENABLED 0x1
6788 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_LSB 13
6790 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_MSB 13
6792 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_WIDTH 1
6794 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_SET_MSK 0x00002000
6796 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_CLR_MSK 0xffffdfff
6798 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_RESET 0x0
6800 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_GET(value) (((value) & 0x00002000) >> 13)
6802 #define ALT_SDMMC_MINTSTS_BUSY_COMPLETE_INTERRUPT_INTERRUPT_SET(value) (((value) << 13) & 0x00002000)
6825 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_DISABLED 0x0
6832 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_E_ENABLED 0x1
6835 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_LSB 14
6837 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_MSB 14
6839 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_WIDTH 1
6841 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_SET_MSK 0x00004000
6843 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_CLR_MSK 0xffffbfff
6845 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_RESET 0x0
6847 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_GET(value) (((value) & 0x00004000) >> 14)
6849 #define ALT_SDMMC_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT_SET(value) (((value) << 14) & 0x00004000)
6875 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_DISABLED 0x0
6882 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_E_ENABLED 0x1
6885 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_LSB 15
6887 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_MSB 15
6889 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_WIDTH 1
6891 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_SET_MSK 0x00008000
6893 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_CLR_MSK 0xffff7fff
6895 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_RESET 0x0
6897 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_GET(value) (((value) & 0x00008000) >> 15)
6899 #define ALT_SDMMC_MINTSTS_END_BIT_ERROR_INTERRUPT_SET(value) (((value) << 15) & 0x00008000)
6930 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED 0x0
6936 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED 0x1
6939 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_LSB 16
6941 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_MSB 16
6943 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_WIDTH 1
6945 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_SET_MSK 0x00010000
6947 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_CLR_MSK 0xfffeffff
6949 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_RESET 0x0
6951 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_GET(value) (((value) & 0x00010000) >> 16)
6953 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD0_SET(value) (((value) << 16) & 0x00010000)
6984 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED 0x0
6990 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED 0x1
6993 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_LSB 17
6995 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_MSB 17
6997 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_WIDTH 1
6999 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_SET_MSK 0x00020000
7001 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_CLR_MSK 0xfffdffff
7003 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_RESET 0x0
7005 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_GET(value) (((value) & 0x00020000) >> 17)
7007 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD1_SET(value) (((value) << 17) & 0x00020000)
7038 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED 0x0
7044 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED 0x1
7047 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_LSB 18
7049 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_MSB 18
7051 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_WIDTH 1
7053 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_SET_MSK 0x00040000
7055 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_CLR_MSK 0xfffbffff
7057 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_RESET 0x0
7059 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_GET(value) (((value) & 0x00040000) >> 18)
7061 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD2_SET(value) (((value) << 18) & 0x00040000)
7092 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED 0x0
7098 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED 0x1
7101 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_LSB 19
7103 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_MSB 19
7105 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_WIDTH 1
7107 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_SET_MSK 0x00080000
7109 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_CLR_MSK 0xfff7ffff
7111 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_RESET 0x0
7113 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_GET(value) (((value) & 0x00080000) >> 19)
7115 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD3_SET(value) (((value) << 19) & 0x00080000)
7146 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED 0x0
7152 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED 0x1
7155 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_LSB 20
7157 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_MSB 20
7159 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_WIDTH 1
7161 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_SET_MSK 0x00100000
7163 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_CLR_MSK 0xffefffff
7165 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_RESET 0x0
7167 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_GET(value) (((value) & 0x00100000) >> 20)
7169 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD4_SET(value) (((value) << 20) & 0x00100000)
7200 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED 0x0
7206 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED 0x1
7209 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_LSB 21
7211 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_MSB 21
7213 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_WIDTH 1
7215 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_SET_MSK 0x00200000
7217 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_CLR_MSK 0xffdfffff
7219 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_RESET 0x0
7221 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_GET(value) (((value) & 0x00200000) >> 21)
7223 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD5_SET(value) (((value) << 21) & 0x00200000)
7254 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED 0x0
7260 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED 0x1
7263 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_LSB 22
7265 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_MSB 22
7267 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_WIDTH 1
7269 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_SET_MSK 0x00400000
7271 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_CLR_MSK 0xffbfffff
7273 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_RESET 0x0
7275 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_GET(value) (((value) & 0x00400000) >> 22)
7277 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD6_SET(value) (((value) << 22) & 0x00400000)
7308 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED 0x0
7314 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED 0x1
7317 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_LSB 23
7319 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_MSB 23
7321 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_WIDTH 1
7323 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_SET_MSK 0x00800000
7325 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_CLR_MSK 0xff7fffff
7327 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_RESET 0x0
7329 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_GET(value) (((value) & 0x00800000) >> 23)
7331 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD7_SET(value) (((value) << 23) & 0x00800000)
7362 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED 0x0
7368 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED 0x1
7371 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_LSB 24
7373 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_MSB 24
7375 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_WIDTH 1
7377 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_SET_MSK 0x01000000
7379 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_CLR_MSK 0xfeffffff
7381 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_RESET 0x0
7383 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_GET(value) (((value) & 0x01000000) >> 24)
7385 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD8_SET(value) (((value) << 24) & 0x01000000)
7416 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED 0x0
7422 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED 0x1
7425 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_LSB 25
7427 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_MSB 25
7429 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_WIDTH 1
7431 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_SET_MSK 0x02000000
7433 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_CLR_MSK 0xfdffffff
7435 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_RESET 0x0
7437 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_GET(value) (((value) & 0x02000000) >> 25)
7439 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD9_SET(value) (((value) << 25) & 0x02000000)
7470 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED 0x0
7476 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED 0x1
7479 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_LSB 26
7481 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_MSB 26
7483 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_WIDTH 1
7485 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_SET_MSK 0x04000000
7487 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_CLR_MSK 0xfbffffff
7489 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_RESET 0x0
7491 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_GET(value) (((value) & 0x04000000) >> 26)
7493 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD10_SET(value) (((value) << 26) & 0x04000000)
7524 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED 0x0
7530 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED 0x1
7533 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_LSB 27
7535 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_MSB 27
7537 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_WIDTH 1
7539 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_SET_MSK 0x08000000
7541 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_CLR_MSK 0xf7ffffff
7543 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_RESET 0x0
7545 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_GET(value) (((value) & 0x08000000) >> 27)
7547 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD11_SET(value) (((value) << 27) & 0x08000000)
7578 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED 0x0
7584 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED 0x1
7587 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_LSB 28
7589 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_MSB 28
7591 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_WIDTH 1
7593 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_SET_MSK 0x10000000
7595 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_CLR_MSK 0xefffffff
7597 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_RESET 0x0
7599 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_GET(value) (((value) & 0x10000000) >> 28)
7601 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD12_SET(value) (((value) << 28) & 0x10000000)
7632 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED 0x0
7638 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED 0x1
7641 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_LSB 29
7643 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_MSB 29
7645 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_WIDTH 1
7647 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_SET_MSK 0x20000000
7649 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_CLR_MSK 0xdfffffff
7651 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_RESET 0x0
7653 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_GET(value) (((value) & 0x20000000) >> 29)
7655 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD13_SET(value) (((value) << 29) & 0x20000000)
7686 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED 0x0
7692 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED 0x1
7695 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_LSB 30
7697 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_MSB 30
7699 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_WIDTH 1
7701 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_SET_MSK 0x40000000
7703 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_CLR_MSK 0xbfffffff
7705 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_RESET 0x0
7707 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_GET(value) (((value) & 0x40000000) >> 30)
7709 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD14_SET(value) (((value) << 30) & 0x40000000)
7740 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED 0x0
7746 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED 0x1
7749 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_LSB 31
7751 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_MSB 31
7753 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_WIDTH 1
7755 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_SET_MSK 0x80000000
7757 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_CLR_MSK 0x7fffffff
7759 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_RESET 0x0
7761 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_GET(value) (((value) & 0x80000000) >> 31)
7763 #define ALT_SDMMC_MINTSTS_SDIO_INTERRUPT_CARD15_SET(value) (((value) << 31) & 0x80000000)
7765 #ifndef __ASSEMBLY__
7777 struct ALT_SDMMC_MINTSTS_s
7779 const volatile uint32_t CARD_DETECT_INTERRUPT : 1;
7780 const volatile uint32_t RESPONSE_ERROR_INTERRUPT : 1;
7781 const volatile uint32_t COMMAND_DONE_INTERRUPT : 1;
7782 const volatile uint32_t DATA_TRANSFER_OVER_INTERRUPT : 1;
7783 const volatile uint32_t TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT : 1;
7784 const volatile uint32_t RECEIVE_FIFO_DATA_REQUEST_INTERRUPT : 1;
7785 const volatile uint32_t RESPONSE_CRC_ERROR_INTERRUPT : 1;
7786 const volatile uint32_t DATA_CRC_ERROR_INTERRUPT : 1;
7787 const volatile uint32_t RESPONSE_TIMEOUT_INTERRUPT : 1;
7788 const volatile uint32_t DATA_READ_TIMEOUT_INTERRUPT : 1;
7789 const volatile uint32_t HOST_TIMEOUT_INTERRUPT : 1;
7790 const volatile uint32_t FIFO_UNDER_OVER_RUN_INTERRUPT : 1;
7791 const volatile uint32_t HARDWARE_LOCKED_WRITE_INTERRUPT : 1;
7792 const volatile uint32_t BUSY_COMPLETE_INTERRUPT_INTERRUPT : 1;
7793 const volatile uint32_t AUTO_COMMAND_DONE_INTERRUPT : 1;
7794 const volatile uint32_t END_BIT_ERROR_INTERRUPT : 1;
7795 const volatile uint32_t SDIO_INTERRUPT_CARD0 : 1;
7796 const volatile uint32_t SDIO_INTERRUPT_CARD1 : 1;
7797 const volatile uint32_t SDIO_INTERRUPT_CARD2 : 1;
7798 const volatile uint32_t SDIO_INTERRUPT_CARD3 : 1;
7799 const volatile uint32_t SDIO_INTERRUPT_CARD4 : 1;
7800 const volatile uint32_t SDIO_INTERRUPT_CARD5 : 1;
7801 const volatile uint32_t SDIO_INTERRUPT_CARD6 : 1;
7802 const volatile uint32_t SDIO_INTERRUPT_CARD7 : 1;
7803 const volatile uint32_t SDIO_INTERRUPT_CARD8 : 1;
7804 const volatile uint32_t SDIO_INTERRUPT_CARD9 : 1;
7805 const volatile uint32_t SDIO_INTERRUPT_CARD10 : 1;
7806 const volatile uint32_t SDIO_INTERRUPT_CARD11 : 1;
7807 const volatile uint32_t SDIO_INTERRUPT_CARD12 : 1;
7808 const volatile uint32_t SDIO_INTERRUPT_CARD13 : 1;
7809 const volatile uint32_t SDIO_INTERRUPT_CARD14 : 1;
7810 const volatile uint32_t SDIO_INTERRUPT_CARD15 : 1;
7814 typedef struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
7818 #define ALT_SDMMC_MINTSTS_RESET 0x00000000
7820 #define ALT_SDMMC_MINTSTS_OFST 0x40
7822 #define ALT_SDMMC_MINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_MINTSTS_OFST))
7898 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_DISABLED 0x0
7905 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_E_ENABLED 0x1
7908 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_LSB 0
7910 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_MSB 0
7912 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_WIDTH 1
7914 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_SET_MSK 0x00000001
7916 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_CLR_MSK 0xfffffffe
7918 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_RESET 0x0
7920 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_GET(value) (((value) & 0x00000001) >> 0)
7922 #define ALT_SDMMC_RINTSTS_CARD_DETECT_STATUS_SET(value) (((value) << 0) & 0x00000001)
7949 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_DISABLED 0x0
7956 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_E_ENABLED 0x1
7959 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_LSB 1
7961 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_MSB 1
7963 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_WIDTH 1
7965 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_SET_MSK 0x00000002
7967 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_CLR_MSK 0xfffffffd
7969 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_RESET 0x0
7971 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_GET(value) (((value) & 0x00000002) >> 1)
7973 #define ALT_SDMMC_RINTSTS_RESPONSE_ERROR_STATUS_SET(value) (((value) << 1) & 0x00000002)
8000 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_DISABLED 0x0
8007 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_E_ENABLED 0x1
8010 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_LSB 2
8012 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_MSB 2
8014 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_WIDTH 1
8016 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_SET_MSK 0x00000004
8018 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_CLR_MSK 0xfffffffb
8020 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_RESET 0x0
8022 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_GET(value) (((value) & 0x00000004) >> 2)
8024 #define ALT_SDMMC_RINTSTS_COMMAND_DONE_STATUS_SET(value) (((value) << 2) & 0x00000004)
8051 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_DISABLED 0x0
8058 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_E_ENABLED 0x1
8061 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_LSB 3
8063 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_MSB 3
8065 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_WIDTH 1
8067 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_SET_MSK 0x00000008
8069 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_CLR_MSK 0xfffffff7
8071 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_RESET 0x0
8073 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_GET(value) (((value) & 0x00000008) >> 3)
8075 #define ALT_SDMMC_RINTSTS_DATA_TRANSFER_OVER_STATUS_SET(value) (((value) << 3) & 0x00000008)
8102 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_DISABLED 0x0
8109 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_E_ENABLED 0x1
8112 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_LSB 4
8114 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_MSB 4
8116 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_WIDTH 1
8118 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_SET_MSK 0x00000010
8120 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_CLR_MSK 0xffffffef
8122 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_RESET 0x0
8124 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_GET(value) (((value) & 0x00000010) >> 4)
8126 #define ALT_SDMMC_RINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_STATUS_SET(value) (((value) << 4) & 0x00000010)
8153 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_DISABLED 0x0
8160 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_E_ENABLED 0x1
8163 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_LSB 5
8165 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_MSB 5
8167 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_WIDTH 1
8169 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_SET_MSK 0x00000020
8171 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_CLR_MSK 0xffffffdf
8173 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_RESET 0x0
8175 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_GET(value) (((value) & 0x00000020) >> 5)
8177 #define ALT_SDMMC_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS_SET(value) (((value) << 5) & 0x00000020)
8204 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_DISABLED 0x0
8211 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_E_ENABLED 0x1
8214 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_LSB 6
8216 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_MSB 6
8218 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_WIDTH 1
8220 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_SET_MSK 0x00000040
8222 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_CLR_MSK 0xffffffbf
8224 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_RESET 0x0
8226 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_GET(value) (((value) & 0x00000040) >> 6)
8228 #define ALT_SDMMC_RINTSTS_RESPONSE_CRC_ERROR_STATUS_SET(value) (((value) << 6) & 0x00000040)
8255 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_DISABLED 0x0
8262 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_E_ENABLED 0x1
8265 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_LSB 7
8267 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_MSB 7
8269 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_WIDTH 1
8271 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_SET_MSK 0x00000080
8273 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_CLR_MSK 0xffffff7f
8275 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_RESET 0x0
8277 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_GET(value) (((value) & 0x00000080) >> 7)
8279 #define ALT_SDMMC_RINTSTS_DATA_CRC_ERROR_STATUS_SET(value) (((value) << 7) & 0x00000080)
8306 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_DISABLED 0x0
8313 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_E_ENABLED 0x1
8316 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_LSB 8
8318 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_MSB 8
8320 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_WIDTH 1
8322 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_SET_MSK 0x00000100
8324 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_CLR_MSK 0xfffffeff
8326 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_RESET 0x0
8328 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_GET(value) (((value) & 0x00000100) >> 8)
8330 #define ALT_SDMMC_RINTSTS_RESPONSE_TIMEOUT_STATUS_SET(value) (((value) << 8) & 0x00000100)
8357 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_DISABLED 0x0
8364 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_E_ENABLED 0x1
8367 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_LSB 9
8369 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_MSB 9
8371 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_WIDTH 1
8373 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_SET_MSK 0x00000200
8375 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_CLR_MSK 0xfffffdff
8377 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_RESET 0x0
8379 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_GET(value) (((value) & 0x00000200) >> 9)
8381 #define ALT_SDMMC_RINTSTS_DATA_READ_TIMEOUT_STATUS_SET(value) (((value) << 9) & 0x00000200)
8408 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_DISABLED 0x0
8415 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_E_ENABLED 0x1
8418 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_LSB 10
8420 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_MSB 10
8422 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_WIDTH 1
8424 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_SET_MSK 0x00000400
8426 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_CLR_MSK 0xfffffbff
8428 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_RESET 0x0
8430 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_GET(value) (((value) & 0x00000400) >> 10)
8432 #define ALT_SDMMC_RINTSTS_HOST_TIMEOUT_STATUS_SET(value) (((value) << 10) & 0x00000400)
8459 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_DISABLED 0x0
8466 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_E_ENABLED 0x1
8469 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_LSB 11
8471 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_MSB 11
8473 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_WIDTH 1
8475 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_SET_MSK 0x00000800
8477 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_CLR_MSK 0xfffff7ff
8479 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_RESET 0x0
8481 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_GET(value) (((value) & 0x00000800) >> 11)
8483 #define ALT_SDMMC_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS_SET(value) (((value) << 11) & 0x00000800)
8510 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_DISABLED 0x0
8517 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_E_ENABLED 0x1
8520 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_LSB 12
8522 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_MSB 12
8524 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_WIDTH 1
8526 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_SET_MSK 0x00001000
8528 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_CLR_MSK 0xffffefff
8530 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_RESET 0x0
8532 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_GET(value) (((value) & 0x00001000) >> 12)
8534 #define ALT_SDMMC_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS_SET(value) (((value) << 12) & 0x00001000)
8561 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_DISABLED 0x0
8568 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_E_ENABLED 0x1
8571 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_LSB 13
8573 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_MSB 13
8575 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_WIDTH 1
8577 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_SET_MSK 0x00002000
8579 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_CLR_MSK 0xffffdfff
8581 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_RESET 0x0
8583 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_GET(value) (((value) & 0x00002000) >> 13)
8585 #define ALT_SDMMC_RINTSTS_BUSY_COMPLETE_STATUS_SET(value) (((value) << 13) & 0x00002000)
8612 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_DISABLED 0x0
8619 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_E_ENABLED 0x1
8622 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_LSB 14
8624 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_MSB 14
8626 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_WIDTH 1
8628 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_SET_MSK 0x00004000
8630 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_CLR_MSK 0xffffbfff
8632 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_RESET 0x0
8634 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_GET(value) (((value) & 0x00004000) >> 14)
8636 #define ALT_SDMMC_RINTSTS_AUTO_COMMAND_DONE_STATUS_SET(value) (((value) << 14) & 0x00004000)
8665 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_DISABLED 0x0
8672 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_E_ENABLED 0x1
8675 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_LSB 15
8677 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_MSB 15
8679 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_WIDTH 1
8681 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_SET_MSK 0x00008000
8683 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_CLR_MSK 0xffff7fff
8685 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_RESET 0x0
8687 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_GET(value) (((value) & 0x00008000) >> 15)
8689 #define ALT_SDMMC_RINTSTS_END_BIT_ERROR_STATUS_SET(value) (((value) << 15) & 0x00008000)
8721 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_DISABLED 0x0
8727 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_E_ENABLED 0x1
8730 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_LSB 16
8732 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_MSB 16
8734 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_WIDTH 1
8736 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_SET_MSK 0x00010000
8738 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_CLR_MSK 0xfffeffff
8740 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_RESET 0x0
8742 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_GET(value) (((value) & 0x00010000) >> 16)
8744 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD0_SET(value) (((value) << 16) & 0x00010000)
8776 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_DISABLED 0x0
8782 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_E_ENABLED 0x1
8785 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_LSB 17
8787 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_MSB 17
8789 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_WIDTH 1
8791 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_SET_MSK 0x00020000
8793 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_CLR_MSK 0xfffdffff
8795 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_RESET 0x0
8797 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_GET(value) (((value) & 0x00020000) >> 17)
8799 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD1_SET(value) (((value) << 17) & 0x00020000)
8831 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_DISABLED 0x0
8837 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_E_ENABLED 0x1
8840 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_LSB 18
8842 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_MSB 18
8844 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_WIDTH 1
8846 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_SET_MSK 0x00040000
8848 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_CLR_MSK 0xfffbffff
8850 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_RESET 0x0
8852 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_GET(value) (((value) & 0x00040000) >> 18)
8854 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD2_SET(value) (((value) << 18) & 0x00040000)
8886 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_DISABLED 0x0
8892 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_E_ENABLED 0x1
8895 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_LSB 19
8897 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_MSB 19
8899 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_WIDTH 1
8901 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_SET_MSK 0x00080000
8903 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_CLR_MSK 0xfff7ffff
8905 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_RESET 0x0
8907 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_GET(value) (((value) & 0x00080000) >> 19)
8909 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD3_SET(value) (((value) << 19) & 0x00080000)
8941 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_DISABLED 0x0
8947 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_E_ENABLED 0x1
8950 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_LSB 20
8952 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_MSB 20
8954 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_WIDTH 1
8956 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_SET_MSK 0x00100000
8958 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_CLR_MSK 0xffefffff
8960 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_RESET 0x0
8962 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_GET(value) (((value) & 0x00100000) >> 20)
8964 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD4_SET(value) (((value) << 20) & 0x00100000)
8996 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_DISABLED 0x0
9002 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_E_ENABLED 0x1
9005 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_LSB 21
9007 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_MSB 21
9009 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_WIDTH 1
9011 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_SET_MSK 0x00200000
9013 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_CLR_MSK 0xffdfffff
9015 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_RESET 0x0
9017 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_GET(value) (((value) & 0x00200000) >> 21)
9019 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD5_SET(value) (((value) << 21) & 0x00200000)
9051 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_DISABLED 0x0
9057 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_E_ENABLED 0x1
9060 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_LSB 22
9062 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_MSB 22
9064 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_WIDTH 1
9066 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_SET_MSK 0x00400000
9068 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_CLR_MSK 0xffbfffff
9070 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_RESET 0x0
9072 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_GET(value) (((value) & 0x00400000) >> 22)
9074 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD6_SET(value) (((value) << 22) & 0x00400000)
9106 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_DISABLED 0x0
9112 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_E_ENABLED 0x1
9115 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_LSB 23
9117 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_MSB 23
9119 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_WIDTH 1
9121 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_SET_MSK 0x00800000
9123 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_CLR_MSK 0xff7fffff
9125 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_RESET 0x0
9127 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_GET(value) (((value) & 0x00800000) >> 23)
9129 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD7_SET(value) (((value) << 23) & 0x00800000)
9161 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_DISABLED 0x0
9167 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_E_ENABLED 0x1
9170 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_LSB 24
9172 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_MSB 24
9174 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_WIDTH 1
9176 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_SET_MSK 0x01000000
9178 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_CLR_MSK 0xfeffffff
9180 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_RESET 0x0
9182 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_GET(value) (((value) & 0x01000000) >> 24)
9184 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD8_SET(value) (((value) << 24) & 0x01000000)
9216 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_DISABLED 0x0
9222 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_E_ENABLED 0x1
9225 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_LSB 25
9227 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_MSB 25
9229 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_WIDTH 1
9231 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_SET_MSK 0x02000000
9233 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_CLR_MSK 0xfdffffff
9235 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_RESET 0x0
9237 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_GET(value) (((value) & 0x02000000) >> 25)
9239 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD9_SET(value) (((value) << 25) & 0x02000000)
9271 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_DISABLED 0x0
9277 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_E_ENABLED 0x1
9280 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_LSB 26
9282 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_MSB 26
9284 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_WIDTH 1
9286 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_SET_MSK 0x04000000
9288 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_CLR_MSK 0xfbffffff
9290 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_RESET 0x0
9292 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_GET(value) (((value) & 0x04000000) >> 26)
9294 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD10_SET(value) (((value) << 26) & 0x04000000)
9326 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_DISABLED 0x0
9332 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_E_ENABLED 0x1
9335 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_LSB 27
9337 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_MSB 27
9339 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_WIDTH 1
9341 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_SET_MSK 0x08000000
9343 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_CLR_MSK 0xf7ffffff
9345 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_RESET 0x0
9347 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_GET(value) (((value) & 0x08000000) >> 27)
9349 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD11_SET(value) (((value) << 27) & 0x08000000)
9381 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_DISABLED 0x0
9387 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_E_ENABLED 0x1
9390 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_LSB 28
9392 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_MSB 28
9394 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_WIDTH 1
9396 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_SET_MSK 0x10000000
9398 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_CLR_MSK 0xefffffff
9400 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_RESET 0x0
9402 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_GET(value) (((value) & 0x10000000) >> 28)
9404 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD12_SET(value) (((value) << 28) & 0x10000000)
9436 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_DISABLED 0x0
9442 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_E_ENABLED 0x1
9445 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_LSB 29
9447 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_MSB 29
9449 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_WIDTH 1
9451 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_SET_MSK 0x20000000
9453 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_CLR_MSK 0xdfffffff
9455 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_RESET 0x0
9457 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_GET(value) (((value) & 0x20000000) >> 29)
9459 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD13_SET(value) (((value) << 29) & 0x20000000)
9491 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_DISABLED 0x0
9497 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_E_ENABLED 0x1
9500 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_LSB 30
9502 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_MSB 30
9504 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_WIDTH 1
9506 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_SET_MSK 0x40000000
9508 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_CLR_MSK 0xbfffffff
9510 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_RESET 0x0
9512 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_GET(value) (((value) & 0x40000000) >> 30)
9514 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD14_SET(value) (((value) << 30) & 0x40000000)
9546 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_DISABLED 0x0
9552 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_E_ENABLED 0x1
9555 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_LSB 31
9557 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_MSB 31
9559 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_WIDTH 1
9561 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_SET_MSK 0x80000000
9563 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_CLR_MSK 0x7fffffff
9565 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_RESET 0x0
9567 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_GET(value) (((value) & 0x80000000) >> 31)
9569 #define ALT_SDMMC_RINTSTS_SDIO_INTERRUPT_CARD15_SET(value) (((value) << 31) & 0x80000000)
9571 #ifndef __ASSEMBLY__
9583 struct ALT_SDMMC_RINTSTS_s
9585 volatile uint32_t CARD_DETECT_STATUS : 1;
9586 volatile uint32_t RESPONSE_ERROR_STATUS : 1;
9587 volatile uint32_t COMMAND_DONE_STATUS : 1;
9588 volatile uint32_t DATA_TRANSFER_OVER_STATUS : 1;
9589 volatile uint32_t TRANSMIT_RECEIVE_FIFO_DATA_STATUS : 1;
9590 volatile uint32_t RECEIVE_FIFO_DATA_REQUEST_STATUS : 1;
9591 volatile uint32_t RESPONSE_CRC_ERROR_STATUS : 1;
9592 volatile uint32_t DATA_CRC_ERROR_STATUS : 1;
9593 volatile uint32_t RESPONSE_TIMEOUT_STATUS : 1;
9594 volatile uint32_t DATA_READ_TIMEOUT_STATUS : 1;
9595 volatile uint32_t HOST_TIMEOUT_STATUS : 1;
9596 volatile uint32_t FIFO_UNDER_OVER_RUN_STATUS : 1;
9597 volatile uint32_t HARDWARE_LOCKED_WRITE_STATUS : 1;
9598 volatile uint32_t BUSY_COMPLETE_STATUS : 1;
9599 volatile uint32_t AUTO_COMMAND_DONE_STATUS : 1;
9600 volatile uint32_t END_BIT_ERROR_STATUS : 1;
9601 volatile uint32_t SDIO_INTERRUPT_CARD0 : 1;
9602 volatile uint32_t SDIO_INTERRUPT_CARD1 : 1;
9603 volatile uint32_t SDIO_INTERRUPT_CARD2 : 1;
9604 volatile uint32_t SDIO_INTERRUPT_CARD3 : 1;
9605 volatile uint32_t SDIO_INTERRUPT_CARD4 : 1;
9606 volatile uint32_t SDIO_INTERRUPT_CARD5 : 1;
9607 volatile uint32_t SDIO_INTERRUPT_CARD6 : 1;
9608 volatile uint32_t SDIO_INTERRUPT_CARD7 : 1;
9609 volatile uint32_t SDIO_INTERRUPT_CARD8 : 1;
9610 volatile uint32_t SDIO_INTERRUPT_CARD9 : 1;
9611 volatile uint32_t SDIO_INTERRUPT_CARD10 : 1;
9612 volatile uint32_t SDIO_INTERRUPT_CARD11 : 1;
9613 volatile uint32_t SDIO_INTERRUPT_CARD12 : 1;
9614 volatile uint32_t SDIO_INTERRUPT_CARD13 : 1;
9615 volatile uint32_t SDIO_INTERRUPT_CARD14 : 1;
9616 volatile uint32_t SDIO_INTERRUPT_CARD15 : 1;
9620 typedef struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
9624 #define ALT_SDMMC_RINTSTS_RESET 0x00000000
9626 #define ALT_SDMMC_RINTSTS_OFST 0x44
9628 #define ALT_SDMMC_RINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RINTSTS_OFST))
9681 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_CLEAR 0x0
9687 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_E_SET 0x1
9690 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_LSB 0
9692 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_MSB 0
9694 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_WIDTH 1
9696 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_SET_MSK 0x00000001
9698 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
9700 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_RESET 0x0
9702 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
9704 #define ALT_SDMMC_STATUS_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
9728 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_CLEAR 0x0
9734 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_E_SET 0x1
9737 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_LSB 1
9739 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_MSB 1
9741 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_WIDTH 1
9743 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_SET_MSK 0x00000002
9745 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
9747 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_RESET 0x1
9749 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
9751 #define ALT_SDMMC_STATUS_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
9773 #define ALT_SDMMC_STATUS_FIFO_EMPTY_E_CLEAR 0x0
9779 #define ALT_SDMMC_STATUS_FIFO_EMPTY_E_SET 0x1
9782 #define ALT_SDMMC_STATUS_FIFO_EMPTY_LSB 2
9784 #define ALT_SDMMC_STATUS_FIFO_EMPTY_MSB 2
9786 #define ALT_SDMMC_STATUS_FIFO_EMPTY_WIDTH 1
9788 #define ALT_SDMMC_STATUS_FIFO_EMPTY_SET_MSK 0x00000004
9790 #define ALT_SDMMC_STATUS_FIFO_EMPTY_CLR_MSK 0xfffffffb
9792 #define ALT_SDMMC_STATUS_FIFO_EMPTY_RESET 0x1
9794 #define ALT_SDMMC_STATUS_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
9796 #define ALT_SDMMC_STATUS_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
9818 #define ALT_SDMMC_STATUS_FIFO_FULL_E_CLEAR 0x0
9824 #define ALT_SDMMC_STATUS_FIFO_FULL_E_SET 0x1
9827 #define ALT_SDMMC_STATUS_FIFO_FULL_LSB 3
9829 #define ALT_SDMMC_STATUS_FIFO_FULL_MSB 3
9831 #define ALT_SDMMC_STATUS_FIFO_FULL_WIDTH 1
9833 #define ALT_SDMMC_STATUS_FIFO_FULL_SET_MSK 0x00000008
9835 #define ALT_SDMMC_STATUS_FIFO_FULL_CLR_MSK 0xfffffff7
9837 #define ALT_SDMMC_STATUS_FIFO_FULL_RESET 0x0
9839 #define ALT_SDMMC_STATUS_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
9841 #define ALT_SDMMC_STATUS_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
9900 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_LSB 4
9902 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_MSB 7
9904 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_WIDTH 4
9906 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_SET_MSK 0x000000f0
9908 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_CLR_MSK 0xffffff0f
9910 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_RESET 0x0
9912 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
9914 #define ALT_SDMMC_STATUS_COMMAND_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
9940 #define ALT_SDMMC_STATUS_DATA_3_STATUS_E_LOW 0x0
9946 #define ALT_SDMMC_STATUS_DATA_3_STATUS_E_HIGH 0x1
9949 #define ALT_SDMMC_STATUS_DATA_3_STATUS_LSB 8
9951 #define ALT_SDMMC_STATUS_DATA_3_STATUS_MSB 8
9953 #define ALT_SDMMC_STATUS_DATA_3_STATUS_WIDTH 1
9955 #define ALT_SDMMC_STATUS_DATA_3_STATUS_SET_MSK 0x00000100
9957 #define ALT_SDMMC_STATUS_DATA_3_STATUS_CLR_MSK 0xfffffeff
9959 #define ALT_SDMMC_STATUS_DATA_3_STATUS_RESET 0x1
9961 #define ALT_SDMMC_STATUS_DATA_3_STATUS_GET(value) (((value) & 0x00000100) >> 8)
9963 #define ALT_SDMMC_STATUS_DATA_3_STATUS_SET(value) (((value) << 8) & 0x00000100)
9989 #define ALT_SDMMC_STATUS_DATA_BUSY_E_LOW 0x0
9995 #define ALT_SDMMC_STATUS_DATA_BUSY_E_HIGH 0x1
9998 #define ALT_SDMMC_STATUS_DATA_BUSY_LSB 9
10000 #define ALT_SDMMC_STATUS_DATA_BUSY_MSB 9
10002 #define ALT_SDMMC_STATUS_DATA_BUSY_WIDTH 1
10004 #define ALT_SDMMC_STATUS_DATA_BUSY_SET_MSK 0x00000200
10006 #define ALT_SDMMC_STATUS_DATA_BUSY_CLR_MSK 0xfffffdff
10008 #define ALT_SDMMC_STATUS_DATA_BUSY_RESET 0x0
10010 #define ALT_SDMMC_STATUS_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
10012 #define ALT_SDMMC_STATUS_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
10034 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_LOW 0x0
10040 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_E_HIGH 0x1
10043 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_LSB 10
10045 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_MSB 10
10047 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_WIDTH 1
10049 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
10051 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
10053 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_RESET 0x0
10055 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
10057 #define ALT_SDMMC_STATUS_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
10068 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_LSB 11
10070 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_MSB 16
10072 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_WIDTH 6
10074 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_SET_MSK 0x0001f800
10076 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
10078 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_RESET 0x0
10080 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
10082 #define ALT_SDMMC_STATUS_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
10093 #define ALT_SDMMC_STATUS_FIFO_COUNT_LSB 17
10095 #define ALT_SDMMC_STATUS_FIFO_COUNT_MSB 29
10097 #define ALT_SDMMC_STATUS_FIFO_COUNT_WIDTH 13
10099 #define ALT_SDMMC_STATUS_FIFO_COUNT_SET_MSK 0x3ffe0000
10101 #define ALT_SDMMC_STATUS_FIFO_COUNT_CLR_MSK 0xc001ffff
10103 #define ALT_SDMMC_STATUS_FIFO_COUNT_RESET 0x0
10105 #define ALT_SDMMC_STATUS_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
10107 #define ALT_SDMMC_STATUS_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
10131 #define ALT_SDMMC_STATUS_DMA_ACK_E_LOW 0x0
10137 #define ALT_SDMMC_STATUS_DMA_ACK_E_HIGH 0x1
10140 #define ALT_SDMMC_STATUS_DMA_ACK_LSB 30
10142 #define ALT_SDMMC_STATUS_DMA_ACK_MSB 30
10144 #define ALT_SDMMC_STATUS_DMA_ACK_WIDTH 1
10146 #define ALT_SDMMC_STATUS_DMA_ACK_SET_MSK 0x40000000
10148 #define ALT_SDMMC_STATUS_DMA_ACK_CLR_MSK 0xbfffffff
10150 #define ALT_SDMMC_STATUS_DMA_ACK_RESET 0x0
10152 #define ALT_SDMMC_STATUS_DMA_ACK_GET(value) (((value) & 0x40000000) >> 30)
10154 #define ALT_SDMMC_STATUS_DMA_ACK_SET(value) (((value) << 30) & 0x40000000)
10178 #define ALT_SDMMC_STATUS_DMA_REQ_E_LOW 0x0
10184 #define ALT_SDMMC_STATUS_DMA_REQ_E_HIGH 0x1
10187 #define ALT_SDMMC_STATUS_DMA_REQ_LSB 31
10189 #define ALT_SDMMC_STATUS_DMA_REQ_MSB 31
10191 #define ALT_SDMMC_STATUS_DMA_REQ_WIDTH 1
10193 #define ALT_SDMMC_STATUS_DMA_REQ_SET_MSK 0x80000000
10195 #define ALT_SDMMC_STATUS_DMA_REQ_CLR_MSK 0x7fffffff
10197 #define ALT_SDMMC_STATUS_DMA_REQ_RESET 0x0
10199 #define ALT_SDMMC_STATUS_DMA_REQ_GET(value) (((value) & 0x80000000) >> 31)
10201 #define ALT_SDMMC_STATUS_DMA_REQ_SET(value) (((value) << 31) & 0x80000000)
10203 #ifndef __ASSEMBLY__
10215 struct ALT_SDMMC_STATUS_s
10217 const volatile uint32_t FIFO_RX_WATERMARK : 1;
10218 const volatile uint32_t FIFO_TX_WATERMARK : 1;
10219 const volatile uint32_t FIFO_EMPTY : 1;
10220 const volatile uint32_t FIFO_FULL : 1;
10221 const volatile uint32_t COMMAND_FSM_STATES : 4;
10222 const volatile uint32_t DATA_3_STATUS : 1;
10223 const volatile uint32_t DATA_BUSY : 1;
10224 const volatile uint32_t DATA_STATE_MC_BUSY : 1;
10225 const volatile uint32_t RESPONSE_INDEX : 6;
10226 const volatile uint32_t FIFO_COUNT : 13;
10227 const volatile uint32_t DMA_ACK : 1;
10228 const volatile uint32_t DMA_REQ : 1;
10232 typedef struct ALT_SDMMC_STATUS_s ALT_SDMMC_STATUS_t;
10236 #define ALT_SDMMC_STATUS_RESET 0x00000106
10238 #define ALT_SDMMC_STATUS_OFST 0x48
10240 #define ALT_SDMMC_STATUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_STATUS_OFST))
10292 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
10294 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
10296 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
10298 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
10300 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
10302 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
10304 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
10306 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
10345 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
10347 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
10349 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
10351 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
10353 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
10355 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
10357 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
10359 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
10447 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_1 0x0
10453 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_4 0x1
10459 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_8 0x2
10465 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_16 0x3
10471 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_32 0x4
10477 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_64 0x5
10483 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_128 0x6
10489 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_E_BURST_256 0x7
10492 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_LSB 28
10494 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_MSB 30
10496 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_WIDTH 3
10498 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_SET_MSK 0x70000000
10500 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
10502 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_RESET 0x0
10504 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
10506 #define ALT_SDMMC_FIFOTH_DW_DMA_MULTIPLE_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
10508 #ifndef __ASSEMBLY__
10520 struct ALT_SDMMC_FIFOTH_s
10522 volatile uint32_t TX_WMark : 12;
10524 volatile uint32_t RX_WMark : 12;
10525 volatile uint32_t DW_DMA_Multiple_Transaction_Size : 3;
10530 typedef struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
10534 #define ALT_SDMMC_FIFOTH_RESET 0x03ff0000
10536 #define ALT_SDMMC_FIFOTH_OFST 0x4c
10538 #define ALT_SDMMC_FIFOTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_FIFOTH_OFST))
10581 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_LOW 0x0
10587 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_E_HIGH 0x1
10590 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_LSB 0
10592 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_MSB 0
10594 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_WIDTH 1
10596 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_SET_MSK 0x00000001
10598 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_CLR_MSK 0xfffffffe
10600 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_RESET 0x1
10602 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
10604 #define ALT_SDMMC_CDETECT_CARD0_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
10606 #ifndef __ASSEMBLY__
10618 struct ALT_SDMMC_CDETECT_s
10620 const volatile uint32_t CARD0_DETECT_N : 1;
10625 typedef struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
10629 #define ALT_SDMMC_CDETECT_RESET 0x00000001
10631 #define ALT_SDMMC_CDETECT_OFST 0x50
10633 #define ALT_SDMMC_CDETECT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CDETECT_OFST))
10677 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_LOW 0x0
10683 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_E_HIGH 0x1
10686 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_LSB 0
10688 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_MSB 0
10690 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_WIDTH 1
10692 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_SET_MSK 0x00000001
10694 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_CLR_MSK 0xfffffffe
10696 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_RESET 0x1
10698 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_GET(value) (((value) & 0x00000001) >> 0)
10700 #define ALT_SDMMC_WRTPRT_WRITE_PROTECT_0_SET(value) (((value) << 0) & 0x00000001)
10702 #ifndef __ASSEMBLY__
10714 struct ALT_SDMMC_WRTPRT_s
10716 const volatile uint32_t WRITE_PROTECT_0 : 1;
10721 typedef struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
10725 #define ALT_SDMMC_WRTPRT_RESET 0x00000001
10727 #define ALT_SDMMC_WRTPRT_OFST 0x54
10729 #define ALT_SDMMC_WRTPRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_WRTPRT_OFST))
10761 #define ALT_SDMMC_GPIO_GPI_LSB 0
10763 #define ALT_SDMMC_GPIO_GPI_MSB 7
10765 #define ALT_SDMMC_GPIO_GPI_WIDTH 8
10767 #define ALT_SDMMC_GPIO_GPI_SET_MSK 0x000000ff
10769 #define ALT_SDMMC_GPIO_GPI_CLR_MSK 0xffffff00
10771 #define ALT_SDMMC_GPIO_GPI_RESET 0x0
10773 #define ALT_SDMMC_GPIO_GPI_GET(value) (((value) & 0x000000ff) >> 0)
10775 #define ALT_SDMMC_GPIO_GPI_SET(value) (((value) << 0) & 0x000000ff)
10787 #define ALT_SDMMC_GPIO_GPO_LSB 8
10789 #define ALT_SDMMC_GPIO_GPO_MSB 23
10791 #define ALT_SDMMC_GPIO_GPO_WIDTH 16
10793 #define ALT_SDMMC_GPIO_GPO_SET_MSK 0x00ffff00
10795 #define ALT_SDMMC_GPIO_GPO_CLR_MSK 0xff0000ff
10797 #define ALT_SDMMC_GPIO_GPO_RESET 0x0
10799 #define ALT_SDMMC_GPIO_GPO_GET(value) (((value) & 0x00ffff00) >> 8)
10801 #define ALT_SDMMC_GPIO_GPO_SET(value) (((value) << 8) & 0x00ffff00)
10803 #ifndef __ASSEMBLY__
10815 struct ALT_SDMMC_GPIO_s
10817 const volatile uint32_t GPI : 8;
10818 volatile uint32_t GPO : 16;
10823 typedef struct ALT_SDMMC_GPIO_s ALT_SDMMC_GPIO_t;
10827 #define ALT_SDMMC_GPIO_RESET 0x00000000
10829 #define ALT_SDMMC_GPIO_OFST 0x58
10831 #define ALT_SDMMC_GPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_GPIO_OFST))
10869 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
10871 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
10873 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
10875 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
10877 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
10879 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
10881 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
10883 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
10885 #ifndef __ASSEMBLY__
10897 struct ALT_SDMMC_TCBCNT_s
10899 const volatile uint32_t TRANS_CARD_BYTE_COUNT : 32;
10903 typedef struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
10907 #define ALT_SDMMC_TCBCNT_RESET 0x00000000
10909 #define ALT_SDMMC_TCBCNT_OFST 0x5c
10911 #define ALT_SDMMC_TCBCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TCBCNT_OFST))
10949 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
10951 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
10953 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
10955 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
10957 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
10959 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
10961 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
10963 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
10965 #ifndef __ASSEMBLY__
10977 struct ALT_SDMMC_TBBCNT_s
10979 const volatile uint32_t TRANS_FIFO_BYTE_COUNT : 32;
10983 typedef struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
10987 #define ALT_SDMMC_TBBCNT_RESET 0x00000000
10989 #define ALT_SDMMC_TBBCNT_OFST 0x60
10991 #define ALT_SDMMC_TBBCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_TBBCNT_OFST))
11023 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
11025 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
11027 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
11029 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
11031 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
11033 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
11035 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
11037 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
11039 #ifndef __ASSEMBLY__
11051 struct ALT_SDMMC_DEBNCE_s
11053 volatile uint32_t DEBOUNCE_COUNT : 24;
11058 typedef struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
11062 #define ALT_SDMMC_DEBNCE_RESET 0x00ffffff
11064 #define ALT_SDMMC_DEBNCE_OFST 0x64
11066 #define ALT_SDMMC_DEBNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DEBNCE_OFST))
11098 #define ALT_SDMMC_USRID_USR_ID_LSB 0
11100 #define ALT_SDMMC_USRID_USR_ID_MSB 31
11102 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
11104 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
11106 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
11108 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
11110 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
11112 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
11114 #ifndef __ASSEMBLY__
11126 struct ALT_SDMMC_USRID_s
11128 volatile uint32_t USR_ID : 32;
11132 typedef struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
11136 #define ALT_SDMMC_USRID_RESET 0x07967797
11138 #define ALT_SDMMC_USRID_OFST 0x68
11140 #define ALT_SDMMC_USRID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_USRID_OFST))
11170 #define ALT_SDMMC_VERID_VER_ID_LSB 0
11172 #define ALT_SDMMC_VERID_VER_ID_MSB 31
11174 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
11176 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
11178 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
11180 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342280a
11182 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
11184 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
11186 #ifndef __ASSEMBLY__
11198 struct ALT_SDMMC_VERID_s
11200 const volatile uint32_t VER_ID : 32;
11204 typedef struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
11208 #define ALT_SDMMC_VERID_RESET 0x5342280a
11210 #define ALT_SDMMC_VERID_OFST 0x6c
11212 #define ALT_SDMMC_VERID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_VERID_OFST))
11265 #define ALT_SDMMC_HCON_CARD_TYPE_E_MMC_ONLY 0x0
11271 #define ALT_SDMMC_HCON_CARD_TYPE_E_SDMMC 0x1
11274 #define ALT_SDMMC_HCON_CARD_TYPE_LSB 0
11276 #define ALT_SDMMC_HCON_CARD_TYPE_MSB 0
11278 #define ALT_SDMMC_HCON_CARD_TYPE_WIDTH 1
11280 #define ALT_SDMMC_HCON_CARD_TYPE_SET_MSK 0x00000001
11282 #define ALT_SDMMC_HCON_CARD_TYPE_CLR_MSK 0xfffffffe
11284 #define ALT_SDMMC_HCON_CARD_TYPE_RESET 0x1
11286 #define ALT_SDMMC_HCON_CARD_TYPE_GET(value) (((value) & 0x00000001) >> 0)
11288 #define ALT_SDMMC_HCON_CARD_TYPE_SET(value) (((value) << 0) & 0x00000001)
11299 #define ALT_SDMMC_HCON_NUM_CARD_LSB 1
11301 #define ALT_SDMMC_HCON_NUM_CARD_MSB 5
11303 #define ALT_SDMMC_HCON_NUM_CARD_WIDTH 5
11305 #define ALT_SDMMC_HCON_NUM_CARD_SET_MSK 0x0000003e
11307 #define ALT_SDMMC_HCON_NUM_CARD_CLR_MSK 0xffffffc1
11309 #define ALT_SDMMC_HCON_NUM_CARD_RESET 0x0
11311 #define ALT_SDMMC_HCON_NUM_CARD_GET(value) (((value) & 0x0000003e) >> 1)
11313 #define ALT_SDMMC_HCON_NUM_CARD_SET(value) (((value) << 1) & 0x0000003e)
11335 #define ALT_SDMMC_HCON_BUS_TYPE_E_APB 0x0
11341 #define ALT_SDMMC_HCON_BUS_TYPE_E_AHB 0x1
11344 #define ALT_SDMMC_HCON_BUS_TYPE_LSB 6
11346 #define ALT_SDMMC_HCON_BUS_TYPE_MSB 6
11348 #define ALT_SDMMC_HCON_BUS_TYPE_WIDTH 1
11350 #define ALT_SDMMC_HCON_BUS_TYPE_SET_MSK 0x00000040
11352 #define ALT_SDMMC_HCON_BUS_TYPE_CLR_MSK 0xffffffbf
11354 #define ALT_SDMMC_HCON_BUS_TYPE_RESET 0x0
11356 #define ALT_SDMMC_HCON_BUS_TYPE_GET(value) (((value) & 0x00000040) >> 6)
11358 #define ALT_SDMMC_HCON_BUS_TYPE_SET(value) (((value) << 6) & 0x00000040)
11377 #define ALT_SDMMC_HCON_H_DATA_WIDTH_LSB 7
11379 #define ALT_SDMMC_HCON_H_DATA_WIDTH_MSB 9
11381 #define ALT_SDMMC_HCON_H_DATA_WIDTH_WIDTH 3
11383 #define ALT_SDMMC_HCON_H_DATA_WIDTH_SET_MSK 0x00000380
11385 #define ALT_SDMMC_HCON_H_DATA_WIDTH_CLR_MSK 0xfffffc7f
11387 #define ALT_SDMMC_HCON_H_DATA_WIDTH_RESET 0x1
11389 #define ALT_SDMMC_HCON_H_DATA_WIDTH_GET(value) (((value) & 0x00000380) >> 7)
11391 #define ALT_SDMMC_HCON_H_DATA_WIDTH_SET(value) (((value) << 7) & 0x00000380)
11414 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_LSB 10
11416 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_MSB 15
11418 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_WIDTH 6
11420 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_SET_MSK 0x0000fc00
11422 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_CLR_MSK 0xffff03ff
11424 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_RESET 0xc
11426 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
11428 #define ALT_SDMMC_HCON_H_ADDR_WIDTH_SET(value) (((value) << 10) & 0x0000fc00)
11452 #define ALT_SDMMC_HCON_DMA_IF_E_NONE 0x0
11458 #define ALT_SDMMC_HCON_DMA_IF_E_DW_DMA 0x1
11464 #define ALT_SDMMC_HCON_DMA_IF_E_GEN_DMA 0x2
11470 #define ALT_SDMMC_HCON_DMA_IF_E_NDW_DMA 0x3
11473 #define ALT_SDMMC_HCON_DMA_IF_LSB 16
11475 #define ALT_SDMMC_HCON_DMA_IF_MSB 17
11477 #define ALT_SDMMC_HCON_DMA_IF_WIDTH 2
11479 #define ALT_SDMMC_HCON_DMA_IF_SET_MSK 0x00030000
11481 #define ALT_SDMMC_HCON_DMA_IF_CLR_MSK 0xfffcffff
11483 #define ALT_SDMMC_HCON_DMA_IF_RESET 0x0
11485 #define ALT_SDMMC_HCON_DMA_IF_GET(value) (((value) & 0x00030000) >> 16)
11487 #define ALT_SDMMC_HCON_DMA_IF_SET(value) (((value) << 16) & 0x00030000)
11506 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_LSB 18
11508 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_MSB 20
11510 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_WIDTH 3
11512 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_SET_MSK 0x001c0000
11514 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_CLR_MSK 0xffe3ffff
11516 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_RESET 0x1
11518 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_GET(value) (((value) & 0x001c0000) >> 18)
11520 #define ALT_SDMMC_HCON_GE_DMA_DATA_WIDTH_SET(value) (((value) << 18) & 0x001c0000)
11542 #define ALT_SDMMC_HCON_FIFO_RAM_IN_E_NO 0x0
11548 #define ALT_SDMMC_HCON_FIFO_RAM_IN_E_YES 0x1
11551 #define ALT_SDMMC_HCON_FIFO_RAM_IN_LSB 21
11553 #define ALT_SDMMC_HCON_FIFO_RAM_IN_MSB 21
11555 #define ALT_SDMMC_HCON_FIFO_RAM_IN_WIDTH 1
11557 #define ALT_SDMMC_HCON_FIFO_RAM_IN_SET_MSK 0x00200000
11559 #define ALT_SDMMC_HCON_FIFO_RAM_IN_CLR_MSK 0xffdfffff
11561 #define ALT_SDMMC_HCON_FIFO_RAM_IN_RESET 0x0
11563 #define ALT_SDMMC_HCON_FIFO_RAM_IN_GET(value) (((value) & 0x00200000) >> 21)
11565 #define ALT_SDMMC_HCON_FIFO_RAM_IN_SET(value) (((value) << 21) & 0x00200000)
11587 #define ALT_SDMMC_HCON_HOLD_REG_E_NO 0x0
11593 #define ALT_SDMMC_HCON_HOLD_REG_E_YES 0x1
11596 #define ALT_SDMMC_HCON_HOLD_REG_LSB 22
11598 #define ALT_SDMMC_HCON_HOLD_REG_MSB 22
11600 #define ALT_SDMMC_HCON_HOLD_REG_WIDTH 1
11602 #define ALT_SDMMC_HCON_HOLD_REG_SET_MSK 0x00400000
11604 #define ALT_SDMMC_HCON_HOLD_REG_CLR_MSK 0xffbfffff
11606 #define ALT_SDMMC_HCON_HOLD_REG_RESET 0x1
11608 #define ALT_SDMMC_HCON_HOLD_REG_GET(value) (((value) & 0x00400000) >> 22)
11610 #define ALT_SDMMC_HCON_HOLD_REG_SET(value) (((value) << 22) & 0x00400000)
11632 #define ALT_SDMMC_HCON_FALSE_PATH_E_NO 0x0
11638 #define ALT_SDMMC_HCON_FALSE_PATH_E_YES 0x1
11641 #define ALT_SDMMC_HCON_FALSE_PATH_LSB 23
11643 #define ALT_SDMMC_HCON_FALSE_PATH_MSB 23
11645 #define ALT_SDMMC_HCON_FALSE_PATH_WIDTH 1
11647 #define ALT_SDMMC_HCON_FALSE_PATH_SET_MSK 0x00800000
11649 #define ALT_SDMMC_HCON_FALSE_PATH_CLR_MSK 0xff7fffff
11651 #define ALT_SDMMC_HCON_FALSE_PATH_RESET 0x1
11653 #define ALT_SDMMC_HCON_FALSE_PATH_GET(value) (((value) & 0x00800000) >> 23)
11655 #define ALT_SDMMC_HCON_FALSE_PATH_SET(value) (((value) << 23) & 0x00800000)
11666 #define ALT_SDMMC_HCON_NUM_CLK_DIC_LSB 24
11668 #define ALT_SDMMC_HCON_NUM_CLK_DIC_MSB 25
11670 #define ALT_SDMMC_HCON_NUM_CLK_DIC_WIDTH 2
11672 #define ALT_SDMMC_HCON_NUM_CLK_DIC_SET_MSK 0x03000000
11674 #define ALT_SDMMC_HCON_NUM_CLK_DIC_CLR_MSK 0xfcffffff
11676 #define ALT_SDMMC_HCON_NUM_CLK_DIC_RESET 0x0
11678 #define ALT_SDMMC_HCON_NUM_CLK_DIC_GET(value) (((value) & 0x03000000) >> 24)
11680 #define ALT_SDMMC_HCON_NUM_CLK_DIC_SET(value) (((value) << 24) & 0x03000000)
11702 #define ALT_SDMMC_HCON_AREA_OPT_E_NO 0x0
11708 #define ALT_SDMMC_HCON_AREA_OPT_E_YES 0x1
11711 #define ALT_SDMMC_HCON_AREA_OPT_LSB 26
11713 #define ALT_SDMMC_HCON_AREA_OPT_MSB 26
11715 #define ALT_SDMMC_HCON_AREA_OPT_WIDTH 1
11717 #define ALT_SDMMC_HCON_AREA_OPT_SET_MSK 0x04000000
11719 #define ALT_SDMMC_HCON_AREA_OPT_CLR_MSK 0xfbffffff
11721 #define ALT_SDMMC_HCON_AREA_OPT_RESET 0x0
11723 #define ALT_SDMMC_HCON_AREA_OPT_GET(value) (((value) & 0x04000000) >> 26)
11725 #define ALT_SDMMC_HCON_AREA_OPT_SET(value) (((value) << 26) & 0x04000000)
11747 #define ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR32 0x0
11753 #define ALT_SDMMC_HCON_ADDR_CONFIG_E_ADDR64 0x1
11756 #define ALT_SDMMC_HCON_ADDR_CONFIG_LSB 27
11758 #define ALT_SDMMC_HCON_ADDR_CONFIG_MSB 27
11760 #define ALT_SDMMC_HCON_ADDR_CONFIG_WIDTH 1
11762 #define ALT_SDMMC_HCON_ADDR_CONFIG_SET_MSK 0x08000000
11764 #define ALT_SDMMC_HCON_ADDR_CONFIG_CLR_MSK 0xf7ffffff
11766 #define ALT_SDMMC_HCON_ADDR_CONFIG_RESET 0x0
11768 #define ALT_SDMMC_HCON_ADDR_CONFIG_GET(value) (((value) & 0x08000000) >> 27)
11770 #define ALT_SDMMC_HCON_ADDR_CONFIG_SET(value) (((value) << 27) & 0x08000000)
11772 #ifndef __ASSEMBLY__
11784 struct ALT_SDMMC_HCON_s
11786 const volatile uint32_t CARD_TYPE : 1;
11787 const volatile uint32_t NUM_CARD : 5;
11788 const volatile uint32_t BUS_TYPE : 1;
11789 const volatile uint32_t H_DATA_WIDTH : 3;
11790 const volatile uint32_t H_ADDR_WIDTH : 6;
11791 const volatile uint32_t DMA_IF : 2;
11792 const volatile uint32_t GE_DMA_DATA_WIDTH : 3;
11793 const volatile uint32_t FIFO_RAM_IN : 1;
11794 const volatile uint32_t HOLD_REG : 1;
11795 const volatile uint32_t FALSE_PATH : 1;
11796 const volatile uint32_t NUM_CLK_DIC : 2;
11797 const volatile uint32_t AREA_OPT : 1;
11798 const volatile uint32_t ADDR_CONFIG : 1;
11803 typedef struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
11807 #define ALT_SDMMC_HCON_RESET 0x00c43081
11809 #define ALT_SDMMC_HCON_OFST 0x70
11811 #define ALT_SDMMC_HCON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_HCON_OFST))
11898 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL33 0x0
11904 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_E_VOL18 0x1
11907 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_LSB 0
11909 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_MSB 0
11911 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_WIDTH 1
11913 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_SET_MSK 0x00000001
11915 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_CLR_MSK 0xfffffffe
11917 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_RESET 0x0
11919 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_GET(value) (((value) & 0x00000001) >> 0)
11921 #define ALT_SDMMC_UHS_REG_VOLT_REG_0_SET(value) (((value) << 0) & 0x00000001)
11959 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL33 0x0
11965 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_E_VOL18 0x1
11968 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_LSB 1
11970 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_MSB 1
11972 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_WIDTH 1
11974 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_SET_MSK 0x00000002
11976 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_CLR_MSK 0xfffffffd
11978 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_RESET 0x0
11980 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_GET(value) (((value) & 0x00000002) >> 1)
11982 #define ALT_SDMMC_UHS_REG_VOLT_REG_1_SET(value) (((value) << 1) & 0x00000002)
12020 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL33 0x0
12026 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_E_VOL18 0x1
12029 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_LSB 2
12031 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_MSB 2
12033 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_WIDTH 1
12035 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_SET_MSK 0x00000004
12037 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_CLR_MSK 0xfffffffb
12039 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_RESET 0x0
12041 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_GET(value) (((value) & 0x00000004) >> 2)
12043 #define ALT_SDMMC_UHS_REG_VOLT_REG_2_SET(value) (((value) << 2) & 0x00000004)
12081 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL33 0x0
12087 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_E_VOL18 0x1
12090 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_LSB 3
12092 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_MSB 3
12094 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_WIDTH 1
12096 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_SET_MSK 0x00000008
12098 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_CLR_MSK 0xfffffff7
12100 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_RESET 0x0
12102 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_GET(value) (((value) & 0x00000008) >> 3)
12104 #define ALT_SDMMC_UHS_REG_VOLT_REG_3_SET(value) (((value) << 3) & 0x00000008)
12142 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL33 0x0
12148 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_E_VOL18 0x1
12151 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_LSB 4
12153 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_MSB 4
12155 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_WIDTH 1
12157 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_SET_MSK 0x00000010
12159 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_CLR_MSK 0xffffffef
12161 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_RESET 0x0
12163 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_GET(value) (((value) & 0x00000010) >> 4)
12165 #define ALT_SDMMC_UHS_REG_VOLT_REG_4_SET(value) (((value) << 4) & 0x00000010)
12203 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL33 0x0
12209 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_E_VOL18 0x1
12212 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_LSB 5
12214 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_MSB 5
12216 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_WIDTH 1
12218 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_SET_MSK 0x00000020
12220 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_CLR_MSK 0xffffffdf
12222 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_RESET 0x0
12224 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_GET(value) (((value) & 0x00000020) >> 5)
12226 #define ALT_SDMMC_UHS_REG_VOLT_REG_5_SET(value) (((value) << 5) & 0x00000020)
12264 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL33 0x0
12270 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_E_VOL18 0x1
12273 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_LSB 6
12275 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_MSB 6
12277 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_WIDTH 1
12279 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_SET_MSK 0x00000040
12281 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_CLR_MSK 0xffffffbf
12283 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_RESET 0x0
12285 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_GET(value) (((value) & 0x00000040) >> 6)
12287 #define ALT_SDMMC_UHS_REG_VOLT_REG_6_SET(value) (((value) << 6) & 0x00000040)
12325 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL33 0x0
12331 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_E_VOL18 0x1
12334 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_LSB 7
12336 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_MSB 7
12338 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_WIDTH 1
12340 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_SET_MSK 0x00000080
12342 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_CLR_MSK 0xffffff7f
12344 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_RESET 0x0
12346 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_GET(value) (((value) & 0x00000080) >> 7)
12348 #define ALT_SDMMC_UHS_REG_VOLT_REG_7_SET(value) (((value) << 7) & 0x00000080)
12386 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL33 0x0
12392 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_E_VOL18 0x1
12395 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_LSB 8
12397 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_MSB 8
12399 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_WIDTH 1
12401 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_SET_MSK 0x00000100
12403 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_CLR_MSK 0xfffffeff
12405 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_RESET 0x0
12407 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_GET(value) (((value) & 0x00000100) >> 8)
12409 #define ALT_SDMMC_UHS_REG_VOLT_REG_8_SET(value) (((value) << 8) & 0x00000100)
12447 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL33 0x0
12453 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_E_VOL18 0x1
12456 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_LSB 9
12458 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_MSB 9
12460 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_WIDTH 1
12462 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_SET_MSK 0x00000200
12464 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_CLR_MSK 0xfffffdff
12466 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_RESET 0x0
12468 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_GET(value) (((value) & 0x00000200) >> 9)
12470 #define ALT_SDMMC_UHS_REG_VOLT_REG_9_SET(value) (((value) << 9) & 0x00000200)
12508 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL33 0x0
12514 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_E_VOL18 0x1
12517 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_LSB 10
12519 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_MSB 10
12521 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_WIDTH 1
12523 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_SET_MSK 0x00000400
12525 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_CLR_MSK 0xfffffbff
12527 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_RESET 0x0
12529 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_GET(value) (((value) & 0x00000400) >> 10)
12531 #define ALT_SDMMC_UHS_REG_VOLT_REG_10_SET(value) (((value) << 10) & 0x00000400)
12569 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL33 0x0
12575 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_E_VOL18 0x1
12578 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_LSB 11
12580 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_MSB 11
12582 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_WIDTH 1
12584 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_SET_MSK 0x00000800
12586 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_CLR_MSK 0xfffff7ff
12588 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_RESET 0x0
12590 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_GET(value) (((value) & 0x00000800) >> 11)
12592 #define ALT_SDMMC_UHS_REG_VOLT_REG_11_SET(value) (((value) << 11) & 0x00000800)
12630 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL33 0x0
12636 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_E_VOL18 0x1
12639 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_LSB 12
12641 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_MSB 12
12643 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_WIDTH 1
12645 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_SET_MSK 0x00001000
12647 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_CLR_MSK 0xffffefff
12649 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_RESET 0x0
12651 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_GET(value) (((value) & 0x00001000) >> 12)
12653 #define ALT_SDMMC_UHS_REG_VOLT_REG_12_SET(value) (((value) << 12) & 0x00001000)
12691 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL33 0x0
12697 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_E_VOL18 0x1
12700 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_LSB 13
12702 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_MSB 13
12704 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_WIDTH 1
12706 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_SET_MSK 0x00002000
12708 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_CLR_MSK 0xffffdfff
12710 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_RESET 0x0
12712 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_GET(value) (((value) & 0x00002000) >> 13)
12714 #define ALT_SDMMC_UHS_REG_VOLT_REG_13_SET(value) (((value) << 13) & 0x00002000)
12752 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL33 0x0
12758 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_E_VOL18 0x1
12761 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_LSB 14
12763 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_MSB 14
12765 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_WIDTH 1
12767 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_SET_MSK 0x00004000
12769 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_CLR_MSK 0xffffbfff
12771 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_RESET 0x0
12773 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_GET(value) (((value) & 0x00004000) >> 14)
12775 #define ALT_SDMMC_UHS_REG_VOLT_REG_14_SET(value) (((value) << 14) & 0x00004000)
12813 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL33 0x0
12819 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_E_VOL18 0x1
12822 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_LSB 15
12824 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_MSB 15
12826 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_WIDTH 1
12828 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_SET_MSK 0x00008000
12830 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_CLR_MSK 0xffff7fff
12832 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_RESET 0x0
12834 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_GET(value) (((value) & 0x00008000) >> 15)
12836 #define ALT_SDMMC_UHS_REG_VOLT_REG_15_SET(value) (((value) << 15) & 0x00008000)
12866 #define ALT_SDMMC_UHS_REG_DDR_REG_0_E_DISABLED 0x0
12872 #define ALT_SDMMC_UHS_REG_DDR_REG_0_E_ENABLED 0x1
12875 #define ALT_SDMMC_UHS_REG_DDR_REG_0_LSB 16
12877 #define ALT_SDMMC_UHS_REG_DDR_REG_0_MSB 16
12879 #define ALT_SDMMC_UHS_REG_DDR_REG_0_WIDTH 1
12881 #define ALT_SDMMC_UHS_REG_DDR_REG_0_SET_MSK 0x00010000
12883 #define ALT_SDMMC_UHS_REG_DDR_REG_0_CLR_MSK 0xfffeffff
12885 #define ALT_SDMMC_UHS_REG_DDR_REG_0_RESET 0x0
12887 #define ALT_SDMMC_UHS_REG_DDR_REG_0_GET(value) (((value) & 0x00010000) >> 16)
12889 #define ALT_SDMMC_UHS_REG_DDR_REG_0_SET(value) (((value) << 16) & 0x00010000)
12919 #define ALT_SDMMC_UHS_REG_DDR_REG_1_E_DISABLED 0x0
12925 #define ALT_SDMMC_UHS_REG_DDR_REG_1_E_ENABLED 0x1
12928 #define ALT_SDMMC_UHS_REG_DDR_REG_1_LSB 17
12930 #define ALT_SDMMC_UHS_REG_DDR_REG_1_MSB 17
12932 #define ALT_SDMMC_UHS_REG_DDR_REG_1_WIDTH 1
12934 #define ALT_SDMMC_UHS_REG_DDR_REG_1_SET_MSK 0x00020000
12936 #define ALT_SDMMC_UHS_REG_DDR_REG_1_CLR_MSK 0xfffdffff
12938 #define ALT_SDMMC_UHS_REG_DDR_REG_1_RESET 0x0
12940 #define ALT_SDMMC_UHS_REG_DDR_REG_1_GET(value) (((value) & 0x00020000) >> 17)
12942 #define ALT_SDMMC_UHS_REG_DDR_REG_1_SET(value) (((value) << 17) & 0x00020000)
12972 #define ALT_SDMMC_UHS_REG_DDR_REG_2_E_DISABLED 0x0
12978 #define ALT_SDMMC_UHS_REG_DDR_REG_2_E_ENABLED 0x1
12981 #define ALT_SDMMC_UHS_REG_DDR_REG_2_LSB 18
12983 #define ALT_SDMMC_UHS_REG_DDR_REG_2_MSB 18
12985 #define ALT_SDMMC_UHS_REG_DDR_REG_2_WIDTH 1
12987 #define ALT_SDMMC_UHS_REG_DDR_REG_2_SET_MSK 0x00040000
12989 #define ALT_SDMMC_UHS_REG_DDR_REG_2_CLR_MSK 0xfffbffff
12991 #define ALT_SDMMC_UHS_REG_DDR_REG_2_RESET 0x0
12993 #define ALT_SDMMC_UHS_REG_DDR_REG_2_GET(value) (((value) & 0x00040000) >> 18)
12995 #define ALT_SDMMC_UHS_REG_DDR_REG_2_SET(value) (((value) << 18) & 0x00040000)
13025 #define ALT_SDMMC_UHS_REG_DDR_REG_3_E_DISABLED 0x0
13031 #define ALT_SDMMC_UHS_REG_DDR_REG_3_E_ENABLED 0x1
13034 #define ALT_SDMMC_UHS_REG_DDR_REG_3_LSB 19
13036 #define ALT_SDMMC_UHS_REG_DDR_REG_3_MSB 19
13038 #define ALT_SDMMC_UHS_REG_DDR_REG_3_WIDTH 1
13040 #define ALT_SDMMC_UHS_REG_DDR_REG_3_SET_MSK 0x00080000
13042 #define ALT_SDMMC_UHS_REG_DDR_REG_3_CLR_MSK 0xfff7ffff
13044 #define ALT_SDMMC_UHS_REG_DDR_REG_3_RESET 0x0
13046 #define ALT_SDMMC_UHS_REG_DDR_REG_3_GET(value) (((value) & 0x00080000) >> 19)
13048 #define ALT_SDMMC_UHS_REG_DDR_REG_3_SET(value) (((value) << 19) & 0x00080000)
13078 #define ALT_SDMMC_UHS_REG_DDR_REG_4_E_DISABLED 0x0
13084 #define ALT_SDMMC_UHS_REG_DDR_REG_4_E_ENABLED 0x1
13087 #define ALT_SDMMC_UHS_REG_DDR_REG_4_LSB 20
13089 #define ALT_SDMMC_UHS_REG_DDR_REG_4_MSB 20
13091 #define ALT_SDMMC_UHS_REG_DDR_REG_4_WIDTH 1
13093 #define ALT_SDMMC_UHS_REG_DDR_REG_4_SET_MSK 0x00100000
13095 #define ALT_SDMMC_UHS_REG_DDR_REG_4_CLR_MSK 0xffefffff
13097 #define ALT_SDMMC_UHS_REG_DDR_REG_4_RESET 0x0
13099 #define ALT_SDMMC_UHS_REG_DDR_REG_4_GET(value) (((value) & 0x00100000) >> 20)
13101 #define ALT_SDMMC_UHS_REG_DDR_REG_4_SET(value) (((value) << 20) & 0x00100000)
13131 #define ALT_SDMMC_UHS_REG_DDR_REG_5_E_DISABLED 0x0
13137 #define ALT_SDMMC_UHS_REG_DDR_REG_5_E_ENABLED 0x1
13140 #define ALT_SDMMC_UHS_REG_DDR_REG_5_LSB 21
13142 #define ALT_SDMMC_UHS_REG_DDR_REG_5_MSB 21
13144 #define ALT_SDMMC_UHS_REG_DDR_REG_5_WIDTH 1
13146 #define ALT_SDMMC_UHS_REG_DDR_REG_5_SET_MSK 0x00200000
13148 #define ALT_SDMMC_UHS_REG_DDR_REG_5_CLR_MSK 0xffdfffff
13150 #define ALT_SDMMC_UHS_REG_DDR_REG_5_RESET 0x0
13152 #define ALT_SDMMC_UHS_REG_DDR_REG_5_GET(value) (((value) & 0x00200000) >> 21)
13154 #define ALT_SDMMC_UHS_REG_DDR_REG_5_SET(value) (((value) << 21) & 0x00200000)
13184 #define ALT_SDMMC_UHS_REG_DDR_REG_6_E_DISABLED 0x0
13190 #define ALT_SDMMC_UHS_REG_DDR_REG_6_E_ENABLED 0x1
13193 #define ALT_SDMMC_UHS_REG_DDR_REG_6_LSB 22
13195 #define ALT_SDMMC_UHS_REG_DDR_REG_6_MSB 22
13197 #define ALT_SDMMC_UHS_REG_DDR_REG_6_WIDTH 1
13199 #define ALT_SDMMC_UHS_REG_DDR_REG_6_SET_MSK 0x00400000
13201 #define ALT_SDMMC_UHS_REG_DDR_REG_6_CLR_MSK 0xffbfffff
13203 #define ALT_SDMMC_UHS_REG_DDR_REG_6_RESET 0x0
13205 #define ALT_SDMMC_UHS_REG_DDR_REG_6_GET(value) (((value) & 0x00400000) >> 22)
13207 #define ALT_SDMMC_UHS_REG_DDR_REG_6_SET(value) (((value) << 22) & 0x00400000)
13237 #define ALT_SDMMC_UHS_REG_DDR_REG_7_E_DISABLED 0x0
13243 #define ALT_SDMMC_UHS_REG_DDR_REG_7_E_ENABLED 0x1
13246 #define ALT_SDMMC_UHS_REG_DDR_REG_7_LSB 23
13248 #define ALT_SDMMC_UHS_REG_DDR_REG_7_MSB 23
13250 #define ALT_SDMMC_UHS_REG_DDR_REG_7_WIDTH 1
13252 #define ALT_SDMMC_UHS_REG_DDR_REG_7_SET_MSK 0x00800000
13254 #define ALT_SDMMC_UHS_REG_DDR_REG_7_CLR_MSK 0xff7fffff
13256 #define ALT_SDMMC_UHS_REG_DDR_REG_7_RESET 0x0
13258 #define ALT_SDMMC_UHS_REG_DDR_REG_7_GET(value) (((value) & 0x00800000) >> 23)
13260 #define ALT_SDMMC_UHS_REG_DDR_REG_7_SET(value) (((value) << 23) & 0x00800000)
13290 #define ALT_SDMMC_UHS_REG_DDR_REG_8_E_DISABLED 0x0
13296 #define ALT_SDMMC_UHS_REG_DDR_REG_8_E_ENABLED 0x1
13299 #define ALT_SDMMC_UHS_REG_DDR_REG_8_LSB 24
13301 #define ALT_SDMMC_UHS_REG_DDR_REG_8_MSB 24
13303 #define ALT_SDMMC_UHS_REG_DDR_REG_8_WIDTH 1
13305 #define ALT_SDMMC_UHS_REG_DDR_REG_8_SET_MSK 0x01000000
13307 #define ALT_SDMMC_UHS_REG_DDR_REG_8_CLR_MSK 0xfeffffff
13309 #define ALT_SDMMC_UHS_REG_DDR_REG_8_RESET 0x0
13311 #define ALT_SDMMC_UHS_REG_DDR_REG_8_GET(value) (((value) & 0x01000000) >> 24)
13313 #define ALT_SDMMC_UHS_REG_DDR_REG_8_SET(value) (((value) << 24) & 0x01000000)
13343 #define ALT_SDMMC_UHS_REG_DDR_REG_9_E_DISABLED 0x0
13349 #define ALT_SDMMC_UHS_REG_DDR_REG_9_E_ENABLED 0x1
13352 #define ALT_SDMMC_UHS_REG_DDR_REG_9_LSB 25
13354 #define ALT_SDMMC_UHS_REG_DDR_REG_9_MSB 25
13356 #define ALT_SDMMC_UHS_REG_DDR_REG_9_WIDTH 1
13358 #define ALT_SDMMC_UHS_REG_DDR_REG_9_SET_MSK 0x02000000
13360 #define ALT_SDMMC_UHS_REG_DDR_REG_9_CLR_MSK 0xfdffffff
13362 #define ALT_SDMMC_UHS_REG_DDR_REG_9_RESET 0x0
13364 #define ALT_SDMMC_UHS_REG_DDR_REG_9_GET(value) (((value) & 0x02000000) >> 25)
13366 #define ALT_SDMMC_UHS_REG_DDR_REG_9_SET(value) (((value) << 25) & 0x02000000)
13396 #define ALT_SDMMC_UHS_REG_DDR_REG_10_E_DISABLED 0x0
13402 #define ALT_SDMMC_UHS_REG_DDR_REG_10_E_ENABLED 0x1
13405 #define ALT_SDMMC_UHS_REG_DDR_REG_10_LSB 26
13407 #define ALT_SDMMC_UHS_REG_DDR_REG_10_MSB 26
13409 #define ALT_SDMMC_UHS_REG_DDR_REG_10_WIDTH 1
13411 #define ALT_SDMMC_UHS_REG_DDR_REG_10_SET_MSK 0x04000000
13413 #define ALT_SDMMC_UHS_REG_DDR_REG_10_CLR_MSK 0xfbffffff
13415 #define ALT_SDMMC_UHS_REG_DDR_REG_10_RESET 0x0
13417 #define ALT_SDMMC_UHS_REG_DDR_REG_10_GET(value) (((value) & 0x04000000) >> 26)
13419 #define ALT_SDMMC_UHS_REG_DDR_REG_10_SET(value) (((value) << 26) & 0x04000000)
13449 #define ALT_SDMMC_UHS_REG_DDR_REG_11_E_DISABLED 0x0
13455 #define ALT_SDMMC_UHS_REG_DDR_REG_11_E_ENABLED 0x1
13458 #define ALT_SDMMC_UHS_REG_DDR_REG_11_LSB 27
13460 #define ALT_SDMMC_UHS_REG_DDR_REG_11_MSB 27
13462 #define ALT_SDMMC_UHS_REG_DDR_REG_11_WIDTH 1
13464 #define ALT_SDMMC_UHS_REG_DDR_REG_11_SET_MSK 0x08000000
13466 #define ALT_SDMMC_UHS_REG_DDR_REG_11_CLR_MSK 0xf7ffffff
13468 #define ALT_SDMMC_UHS_REG_DDR_REG_11_RESET 0x0
13470 #define ALT_SDMMC_UHS_REG_DDR_REG_11_GET(value) (((value) & 0x08000000) >> 27)
13472 #define ALT_SDMMC_UHS_REG_DDR_REG_11_SET(value) (((value) << 27) & 0x08000000)
13502 #define ALT_SDMMC_UHS_REG_DDR_REG_12_E_DISABLED 0x0
13508 #define ALT_SDMMC_UHS_REG_DDR_REG_12_E_ENABLED 0x1
13511 #define ALT_SDMMC_UHS_REG_DDR_REG_12_LSB 28
13513 #define ALT_SDMMC_UHS_REG_DDR_REG_12_MSB 28
13515 #define ALT_SDMMC_UHS_REG_DDR_REG_12_WIDTH 1
13517 #define ALT_SDMMC_UHS_REG_DDR_REG_12_SET_MSK 0x10000000
13519 #define ALT_SDMMC_UHS_REG_DDR_REG_12_CLR_MSK 0xefffffff
13521 #define ALT_SDMMC_UHS_REG_DDR_REG_12_RESET 0x0
13523 #define ALT_SDMMC_UHS_REG_DDR_REG_12_GET(value) (((value) & 0x10000000) >> 28)
13525 #define ALT_SDMMC_UHS_REG_DDR_REG_12_SET(value) (((value) << 28) & 0x10000000)
13555 #define ALT_SDMMC_UHS_REG_DDR_REG_13_E_DISABLED 0x0
13561 #define ALT_SDMMC_UHS_REG_DDR_REG_13_E_ENABLED 0x1
13564 #define ALT_SDMMC_UHS_REG_DDR_REG_13_LSB 29
13566 #define ALT_SDMMC_UHS_REG_DDR_REG_13_MSB 29
13568 #define ALT_SDMMC_UHS_REG_DDR_REG_13_WIDTH 1
13570 #define ALT_SDMMC_UHS_REG_DDR_REG_13_SET_MSK 0x20000000
13572 #define ALT_SDMMC_UHS_REG_DDR_REG_13_CLR_MSK 0xdfffffff
13574 #define ALT_SDMMC_UHS_REG_DDR_REG_13_RESET 0x0
13576 #define ALT_SDMMC_UHS_REG_DDR_REG_13_GET(value) (((value) & 0x20000000) >> 29)
13578 #define ALT_SDMMC_UHS_REG_DDR_REG_13_SET(value) (((value) << 29) & 0x20000000)
13608 #define ALT_SDMMC_UHS_REG_DDR_REG_14_E_DISABLED 0x0
13614 #define ALT_SDMMC_UHS_REG_DDR_REG_14_E_ENABLED 0x1
13617 #define ALT_SDMMC_UHS_REG_DDR_REG_14_LSB 30
13619 #define ALT_SDMMC_UHS_REG_DDR_REG_14_MSB 30
13621 #define ALT_SDMMC_UHS_REG_DDR_REG_14_WIDTH 1
13623 #define ALT_SDMMC_UHS_REG_DDR_REG_14_SET_MSK 0x40000000
13625 #define ALT_SDMMC_UHS_REG_DDR_REG_14_CLR_MSK 0xbfffffff
13627 #define ALT_SDMMC_UHS_REG_DDR_REG_14_RESET 0x0
13629 #define ALT_SDMMC_UHS_REG_DDR_REG_14_GET(value) (((value) & 0x40000000) >> 30)
13631 #define ALT_SDMMC_UHS_REG_DDR_REG_14_SET(value) (((value) << 30) & 0x40000000)
13661 #define ALT_SDMMC_UHS_REG_DDR_REG_15_E_DISABLED 0x0
13667 #define ALT_SDMMC_UHS_REG_DDR_REG_15_E_ENABLED 0x1
13670 #define ALT_SDMMC_UHS_REG_DDR_REG_15_LSB 31
13672 #define ALT_SDMMC_UHS_REG_DDR_REG_15_MSB 31
13674 #define ALT_SDMMC_UHS_REG_DDR_REG_15_WIDTH 1
13676 #define ALT_SDMMC_UHS_REG_DDR_REG_15_SET_MSK 0x80000000
13678 #define ALT_SDMMC_UHS_REG_DDR_REG_15_CLR_MSK 0x7fffffff
13680 #define ALT_SDMMC_UHS_REG_DDR_REG_15_RESET 0x0
13682 #define ALT_SDMMC_UHS_REG_DDR_REG_15_GET(value) (((value) & 0x80000000) >> 31)
13684 #define ALT_SDMMC_UHS_REG_DDR_REG_15_SET(value) (((value) << 31) & 0x80000000)
13686 #ifndef __ASSEMBLY__
13698 struct ALT_SDMMC_UHS_REG_s
13700 volatile uint32_t VOLT_REG_0 : 1;
13701 volatile uint32_t VOLT_REG_1 : 1;
13702 volatile uint32_t VOLT_REG_2 : 1;
13703 volatile uint32_t VOLT_REG_3 : 1;
13704 volatile uint32_t VOLT_REG_4 : 1;
13705 volatile uint32_t VOLT_REG_5 : 1;
13706 volatile uint32_t VOLT_REG_6 : 1;
13707 volatile uint32_t VOLT_REG_7 : 1;
13708 volatile uint32_t VOLT_REG_8 : 1;
13709 volatile uint32_t VOLT_REG_9 : 1;
13710 volatile uint32_t VOLT_REG_10 : 1;
13711 volatile uint32_t VOLT_REG_11 : 1;
13712 volatile uint32_t VOLT_REG_12 : 1;
13713 volatile uint32_t VOLT_REG_13 : 1;
13714 volatile uint32_t VOLT_REG_14 : 1;
13715 volatile uint32_t VOLT_REG_15 : 1;
13716 volatile uint32_t DDR_REG_0 : 1;
13717 volatile uint32_t DDR_REG_1 : 1;
13718 volatile uint32_t DDR_REG_2 : 1;
13719 volatile uint32_t DDR_REG_3 : 1;
13720 volatile uint32_t DDR_REG_4 : 1;
13721 volatile uint32_t DDR_REG_5 : 1;
13722 volatile uint32_t DDR_REG_6 : 1;
13723 volatile uint32_t DDR_REG_7 : 1;
13724 volatile uint32_t DDR_REG_8 : 1;
13725 volatile uint32_t DDR_REG_9 : 1;
13726 volatile uint32_t DDR_REG_10 : 1;
13727 volatile uint32_t DDR_REG_11 : 1;
13728 volatile uint32_t DDR_REG_12 : 1;
13729 volatile uint32_t DDR_REG_13 : 1;
13730 volatile uint32_t DDR_REG_14 : 1;
13731 volatile uint32_t DDR_REG_15 : 1;
13735 typedef struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
13739 #define ALT_SDMMC_UHS_REG_RESET 0x00000000
13741 #define ALT_SDMMC_UHS_REG_OFST 0x74
13743 #define ALT_SDMMC_UHS_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_UHS_REG_OFST))
13797 #define ALT_SDMMC_RST_N_CARD0_RESET_E_ASSERT 0x0
13803 #define ALT_SDMMC_RST_N_CARD0_RESET_E_DEASSERT 0x1
13806 #define ALT_SDMMC_RST_N_CARD0_RESET_LSB 0
13808 #define ALT_SDMMC_RST_N_CARD0_RESET_MSB 0
13810 #define ALT_SDMMC_RST_N_CARD0_RESET_WIDTH 1
13812 #define ALT_SDMMC_RST_N_CARD0_RESET_SET_MSK 0x00000001
13814 #define ALT_SDMMC_RST_N_CARD0_RESET_CLR_MSK 0xfffffffe
13816 #define ALT_SDMMC_RST_N_CARD0_RESET_RESET 0x1
13818 #define ALT_SDMMC_RST_N_CARD0_RESET_GET(value) (((value) & 0x00000001) >> 0)
13820 #define ALT_SDMMC_RST_N_CARD0_RESET_SET(value) (((value) << 0) & 0x00000001)
13822 #ifndef __ASSEMBLY__
13834 struct ALT_SDMMC_RST_N_s
13836 volatile uint32_t CARD0_RESET : 1;
13841 typedef struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
13845 #define ALT_SDMMC_RST_N_RESET 0x00000001
13847 #define ALT_SDMMC_RST_N_OFST 0x78
13849 #define ALT_SDMMC_RST_N_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_RST_N_OFST))
13896 #define ALT_SDMMC_BMOD_SWR_E_FALSE 0x0
13902 #define ALT_SDMMC_BMOD_SWR_E_TRUE 0x1
13905 #define ALT_SDMMC_BMOD_SWR_LSB 0
13907 #define ALT_SDMMC_BMOD_SWR_MSB 0
13909 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
13911 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
13913 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
13915 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
13917 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
13919 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
13947 #define ALT_SDMMC_BMOD_FB_E_FALSE 0x0
13953 #define ALT_SDMMC_BMOD_FB_E_TRUE 0x1
13956 #define ALT_SDMMC_BMOD_FB_LSB 1
13958 #define ALT_SDMMC_BMOD_FB_MSB 1
13960 #define ALT_SDMMC_BMOD_FB_WIDTH 1
13962 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
13964 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
13966 #define ALT_SDMMC_BMOD_FB_RESET 0x0
13968 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
13970 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
13985 #define ALT_SDMMC_BMOD_DSL_LSB 2
13987 #define ALT_SDMMC_BMOD_DSL_MSB 6
13989 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
13991 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
13993 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
13995 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
13997 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
13999 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
14023 #define ALT_SDMMC_BMOD_DE_E_DISABLED 0x0
14029 #define ALT_SDMMC_BMOD_DE_E_ENABLED 0x1
14032 #define ALT_SDMMC_BMOD_DE_LSB 7
14034 #define ALT_SDMMC_BMOD_DE_MSB 7
14036 #define ALT_SDMMC_BMOD_DE_WIDTH 1
14038 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
14040 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
14042 #define ALT_SDMMC_BMOD_DE_RESET 0x0
14044 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
14046 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
14102 #define ALT_SDMMC_BMOD_PBL_E_BURST_1 0x0
14108 #define ALT_SDMMC_BMOD_PBL_E_BURST_4 0x1
14114 #define ALT_SDMMC_BMOD_PBL_E_BURST_8 0x2
14120 #define ALT_SDMMC_BMOD_PBL_E_BURST_16 0x3
14126 #define ALT_SDMMC_BMOD_PBL_E_BURST_32 0x4
14132 #define ALT_SDMMC_BMOD_PBL_E_BURST_64 0x5
14138 #define ALT_SDMMC_BMOD_PBL_E_BURST_128 0x6
14144 #define ALT_SDMMC_BMOD_PBL_E_BURST_256 0x7
14147 #define ALT_SDMMC_BMOD_PBL_LSB 8
14149 #define ALT_SDMMC_BMOD_PBL_MSB 10
14151 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
14153 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
14155 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
14157 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
14159 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
14161 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
14163 #ifndef __ASSEMBLY__
14175 struct ALT_SDMMC_BMOD_s
14177 volatile uint32_t SWR : 1;
14178 volatile uint32_t FB : 1;
14179 volatile uint32_t DSL : 5;
14180 volatile uint32_t DE : 1;
14181 const volatile uint32_t PBL : 3;
14186 typedef struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
14190 #define ALT_SDMMC_BMOD_RESET 0x00000000
14192 #define ALT_SDMMC_BMOD_OFST 0x80
14194 #define ALT_SDMMC_BMOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BMOD_OFST))
14229 #define ALT_SDMMC_PLDMND_PD_LSB 0
14231 #define ALT_SDMMC_PLDMND_PD_MSB 31
14233 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
14235 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
14237 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
14239 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
14241 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
14243 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
14245 #ifndef __ASSEMBLY__
14257 struct ALT_SDMMC_PLDMND_s
14259 volatile uint32_t PD : 32;
14263 typedef struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
14267 #define ALT_SDMMC_PLDMND_RESET 0x00000000
14269 #define ALT_SDMMC_PLDMND_OFST 0x84
14271 #define ALT_SDMMC_PLDMND_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_PLDMND_OFST))
14303 #define ALT_SDMMC_DBADDR_SDL_LSB 0
14305 #define ALT_SDMMC_DBADDR_SDL_MSB 31
14307 #define ALT_SDMMC_DBADDR_SDL_WIDTH 32
14309 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xffffffff
14311 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000000
14313 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
14315 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xffffffff) >> 0)
14317 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 0) & 0xffffffff)
14319 #ifndef __ASSEMBLY__
14331 struct ALT_SDMMC_DBADDR_s
14333 volatile uint32_t SDL : 32;
14337 typedef struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
14341 #define ALT_SDMMC_DBADDR_RESET 0x00000000
14343 #define ALT_SDMMC_DBADDR_OFST 0x88
14345 #define ALT_SDMMC_DBADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DBADDR_OFST))
14397 #define ALT_SDMMC_IDSTS_TI_E_SET 0x0
14403 #define ALT_SDMMC_IDSTS_TI_E_CLEAR 0x1
14406 #define ALT_SDMMC_IDSTS_TI_LSB 0
14408 #define ALT_SDMMC_IDSTS_TI_MSB 0
14410 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
14412 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
14414 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
14416 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
14418 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
14420 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
14443 #define ALT_SDMMC_IDSTS_RI_E_SET 0x0
14449 #define ALT_SDMMC_IDSTS_RI_E_CLEAR 0x1
14452 #define ALT_SDMMC_IDSTS_RI_LSB 1
14454 #define ALT_SDMMC_IDSTS_RI_MSB 1
14456 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
14458 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
14460 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
14462 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
14464 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
14466 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
14490 #define ALT_SDMMC_IDSTS_FBE_E_SET 0x0
14496 #define ALT_SDMMC_IDSTS_FBE_E_CLEAR 0x1
14499 #define ALT_SDMMC_IDSTS_FBE_LSB 2
14501 #define ALT_SDMMC_IDSTS_FBE_MSB 2
14503 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
14505 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
14507 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
14509 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
14511 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
14513 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
14536 #define ALT_SDMMC_IDSTS_DU_E_SET 0x0
14542 #define ALT_SDMMC_IDSTS_DU_E_CLEAR 0x1
14545 #define ALT_SDMMC_IDSTS_DU_LSB 4
14547 #define ALT_SDMMC_IDSTS_DU_MSB 4
14549 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
14551 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
14553 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
14555 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
14557 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
14559 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
14606 #define ALT_SDMMC_IDSTS_CES_E_SET 0x0
14612 #define ALT_SDMMC_IDSTS_CES_E_CLEAR 0x1
14615 #define ALT_SDMMC_IDSTS_CES_LSB 5
14617 #define ALT_SDMMC_IDSTS_CES_MSB 5
14619 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
14621 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
14623 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
14625 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
14627 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
14629 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
14662 #define ALT_SDMMC_IDSTS_NIS_E_SET 0x0
14668 #define ALT_SDMMC_IDSTS_NIS_E_CLEAR 0x1
14671 #define ALT_SDMMC_IDSTS_NIS_LSB 8
14673 #define ALT_SDMMC_IDSTS_NIS_MSB 8
14675 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
14677 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
14679 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
14681 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
14683 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
14685 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
14718 #define ALT_SDMMC_IDSTS_AIS_E_SET 0x0
14724 #define ALT_SDMMC_IDSTS_AIS_E_CLEAR 0x1
14727 #define ALT_SDMMC_IDSTS_AIS_LSB 9
14729 #define ALT_SDMMC_IDSTS_AIS_MSB 9
14731 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
14733 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
14735 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
14737 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
14739 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
14741 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
14764 #define ALT_SDMMC_IDSTS_EB_LSB 10
14766 #define ALT_SDMMC_IDSTS_EB_MSB 12
14768 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
14770 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
14772 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
14774 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
14776 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
14778 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
14809 #define ALT_SDMMC_IDSTS_FSM_LSB 13
14811 #define ALT_SDMMC_IDSTS_FSM_MSB 16
14813 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
14815 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
14817 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
14819 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
14821 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
14823 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
14825 #ifndef __ASSEMBLY__
14837 struct ALT_SDMMC_IDSTS_s
14839 volatile uint32_t TI : 1;
14840 volatile uint32_t RI : 1;
14841 volatile uint32_t FBE : 1;
14843 volatile uint32_t DU : 1;
14844 volatile uint32_t CES : 1;
14846 volatile uint32_t NIS : 1;
14847 volatile uint32_t AIS : 1;
14848 const volatile uint32_t EB : 3;
14849 const volatile uint32_t FSM : 4;
14854 typedef struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
14858 #define ALT_SDMMC_IDSTS_RESET 0x00000000
14860 #define ALT_SDMMC_IDSTS_OFST 0x8c
14862 #define ALT_SDMMC_IDSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_IDSTS_OFST))
14913 #define ALT_SDMMC_IDINTEN_TI_E_DISABLED 0x0
14919 #define ALT_SDMMC_IDINTEN_TI_E_ENABLED 0x1
14922 #define ALT_SDMMC_IDINTEN_TI_LSB 0
14924 #define ALT_SDMMC_IDINTEN_TI_MSB 0
14926 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
14928 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
14930 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
14932 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
14934 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
14936 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
14960 #define ALT_SDMMC_IDINTEN_RI_E_DISABLED 0x0
14966 #define ALT_SDMMC_IDINTEN_RI_E_ENABLED 0x1
14969 #define ALT_SDMMC_IDINTEN_RI_LSB 1
14971 #define ALT_SDMMC_IDINTEN_RI_MSB 1
14973 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
14975 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
14977 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
14979 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
14981 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
14983 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
15008 #define ALT_SDMMC_IDINTEN_FBE_E_DISABLED 0x0
15015 #define ALT_SDMMC_IDINTEN_FBE_E_ENABLED 0x1
15018 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
15020 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
15022 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
15024 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
15026 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
15028 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
15030 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
15032 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
15057 #define ALT_SDMMC_IDINTEN_DU_E_DISABLED 0x0
15064 #define ALT_SDMMC_IDINTEN_DU_E_ENABLED 0x1
15067 #define ALT_SDMMC_IDINTEN_DU_LSB 4
15069 #define ALT_SDMMC_IDINTEN_DU_MSB 4
15071 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
15073 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
15075 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
15077 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
15079 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
15081 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
15104 #define ALT_SDMMC_IDINTEN_CES_E_DISABLED 0x0
15110 #define ALT_SDMMC_IDINTEN_CES_E_ENABLED 0x1
15113 #define ALT_SDMMC_IDINTEN_CES_LSB 5
15115 #define ALT_SDMMC_IDINTEN_CES_MSB 5
15117 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
15119 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
15121 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
15123 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
15125 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
15127 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
15154 #define ALT_SDMMC_IDINTEN_NI_E_DISABLED 0x0
15160 #define ALT_SDMMC_IDINTEN_NI_E_ENABLED 0x1
15163 #define ALT_SDMMC_IDINTEN_NI_LSB 8
15165 #define ALT_SDMMC_IDINTEN_NI_MSB 8
15167 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
15169 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
15171 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
15173 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
15175 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
15177 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
15204 #define ALT_SDMMC_IDINTEN_AI_E_DISABLED 0x0
15210 #define ALT_SDMMC_IDINTEN_AI_E_ENABLED 0x1
15213 #define ALT_SDMMC_IDINTEN_AI_LSB 9
15215 #define ALT_SDMMC_IDINTEN_AI_MSB 9
15217 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
15219 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
15221 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
15223 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
15225 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
15227 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
15229 #ifndef __ASSEMBLY__
15241 struct ALT_SDMMC_IDINTEN_s
15243 volatile uint32_t TI : 1;
15244 volatile uint32_t RI : 1;
15245 volatile uint32_t FBE : 1;
15247 volatile uint32_t DU : 1;
15248 volatile uint32_t CES : 1;
15250 volatile uint32_t NI : 1;
15251 volatile uint32_t AI : 1;
15256 typedef struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
15260 #define ALT_SDMMC_IDINTEN_RESET 0x00000000
15262 #define ALT_SDMMC_IDINTEN_OFST 0x90
15264 #define ALT_SDMMC_IDINTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_IDINTEN_OFST))
15295 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
15297 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
15299 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
15301 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
15303 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
15305 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
15307 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
15309 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
15311 #ifndef __ASSEMBLY__
15323 struct ALT_SDMMC_DSCADDR_s
15325 const volatile uint32_t HDA : 32;
15329 typedef struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
15333 #define ALT_SDMMC_DSCADDR_RESET 0x00000000
15335 #define ALT_SDMMC_DSCADDR_OFST 0x94
15337 #define ALT_SDMMC_DSCADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_DSCADDR_OFST))
15368 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
15370 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
15372 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
15374 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
15376 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
15378 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
15380 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
15382 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
15384 #ifndef __ASSEMBLY__
15396 struct ALT_SDMMC_BUFADDR_s
15398 const volatile uint32_t HBA : 32;
15402 typedef struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
15406 #define ALT_SDMMC_BUFADDR_RESET 0x00000000
15408 #define ALT_SDMMC_BUFADDR_OFST 0x98
15410 #define ALT_SDMMC_BUFADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BUFADDR_OFST))
15463 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISABLED 0x0
15469 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_ENABLED 0x1
15472 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
15474 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
15476 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
15478 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
15480 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
15482 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
15484 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
15486 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
15519 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_DISABLED 0x0
15525 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_E_ENABLED 0x1
15528 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_LSB 1
15530 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_MSB 1
15532 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_WIDTH 1
15534 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET_MSK 0x00000002
15536 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_CLR_MSK 0xfffffffd
15538 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_RESET 0x0
15540 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_GET(value) (((value) & 0x00000002) >> 1)
15542 #define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET(value) (((value) << 1) & 0x00000002)
15572 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_DISABLED 0x0
15578 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_E_ENABLED 0x1
15581 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_LSB 2
15583 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_MSB 2
15585 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_WIDTH 1
15587 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_SET_MSK 0x00000004
15589 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_CLR_MSK 0xfffffffb
15591 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_RESET 0x0
15593 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_GET(value) (((value) & 0x00000004) >> 2)
15595 #define ALT_SDMMC_CARDTHRCTL_CARDWRTHREN_SET(value) (((value) << 2) & 0x00000004)
15618 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
15620 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 28
15622 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 13
15624 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x1fff0000
15626 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xe000ffff
15628 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
15630 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x1fff0000) >> 16)
15632 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x1fff0000)
15634 #ifndef __ASSEMBLY__
15646 struct ALT_SDMMC_CARDTHRCTL_s
15648 volatile uint32_t CARDRDTHREN : 1;
15649 volatile uint32_t BUSY_CLR_INT_EN : 1;
15650 const volatile uint32_t CARDWRTHREN : 1;
15652 volatile uint32_t CARDRDTHRESHOLD : 13;
15657 typedef struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
15661 #define ALT_SDMMC_CARDTHRCTL_RESET 0x00000000
15663 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
15665 #define ALT_SDMMC_CARDTHRCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_CARDTHRCTL_OFST))
15727 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_DISABLED 0x0
15733 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_E_ENABLED 0x1
15736 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_LSB 0
15738 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_MSB 0
15740 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_WIDTH 1
15742 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_SET_MSK 0x00000001
15744 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_CLR_MSK 0xfffffffe
15746 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_RESET 0x0
15748 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_GET(value) (((value) & 0x00000001) >> 0)
15750 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_0_SET(value) (((value) << 0) & 0x00000001)
15778 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_DISABLED 0x0
15784 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_E_ENABLED 0x1
15787 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_LSB 1
15789 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_MSB 1
15791 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_WIDTH 1
15793 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_SET_MSK 0x00000002
15795 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_CLR_MSK 0xfffffffd
15797 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_RESET 0x0
15799 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_GET(value) (((value) & 0x00000002) >> 1)
15801 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_1_SET(value) (((value) << 1) & 0x00000002)
15829 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_DISABLED 0x0
15835 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_E_ENABLED 0x1
15838 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_LSB 2
15840 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_MSB 2
15842 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_WIDTH 1
15844 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_SET_MSK 0x00000004
15846 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_CLR_MSK 0xfffffffb
15848 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_RESET 0x0
15850 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_GET(value) (((value) & 0x00000004) >> 2)
15852 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_2_SET(value) (((value) << 2) & 0x00000004)
15880 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_DISABLED 0x0
15886 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_E_ENABLED 0x1
15889 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_LSB 3
15891 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_MSB 3
15893 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_WIDTH 1
15895 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_SET_MSK 0x00000008
15897 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_CLR_MSK 0xfffffff7
15899 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_RESET 0x0
15901 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_GET(value) (((value) & 0x00000008) >> 3)
15903 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_3_SET(value) (((value) << 3) & 0x00000008)
15931 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_DISABLED 0x0
15937 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_E_ENABLED 0x1
15940 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_LSB 4
15942 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_MSB 4
15944 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_WIDTH 1
15946 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_SET_MSK 0x00000010
15948 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_CLR_MSK 0xffffffef
15950 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_RESET 0x0
15952 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_GET(value) (((value) & 0x00000010) >> 4)
15954 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_4_SET(value) (((value) << 4) & 0x00000010)
15982 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_DISABLED 0x0
15988 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_E_ENABLED 0x1
15991 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_LSB 5
15993 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_MSB 5
15995 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_WIDTH 1
15997 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_SET_MSK 0x00000020
15999 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_CLR_MSK 0xffffffdf
16001 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_RESET 0x0
16003 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_GET(value) (((value) & 0x00000020) >> 5)
16005 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_5_SET(value) (((value) << 5) & 0x00000020)
16033 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_DISABLED 0x0
16039 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_E_ENABLED 0x1
16042 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_LSB 6
16044 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_MSB 6
16046 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_WIDTH 1
16048 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_SET_MSK 0x00000040
16050 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_CLR_MSK 0xffffffbf
16052 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_RESET 0x0
16054 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_GET(value) (((value) & 0x00000040) >> 6)
16056 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_6_SET(value) (((value) << 6) & 0x00000040)
16084 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_DISABLED 0x0
16090 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_E_ENABLED 0x1
16093 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_LSB 7
16095 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_MSB 7
16097 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_WIDTH 1
16099 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_SET_MSK 0x00000080
16101 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_CLR_MSK 0xffffff7f
16103 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_RESET 0x0
16105 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_GET(value) (((value) & 0x00000080) >> 7)
16107 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_7_SET(value) (((value) << 7) & 0x00000080)
16135 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_DISABLED 0x0
16141 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_E_ENABLED 0x1
16144 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_LSB 8
16146 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_MSB 8
16148 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_WIDTH 1
16150 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_SET_MSK 0x00000100
16152 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_CLR_MSK 0xfffffeff
16154 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_RESET 0x0
16156 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_GET(value) (((value) & 0x00000100) >> 8)
16158 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_8_SET(value) (((value) << 8) & 0x00000100)
16186 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_DISABLED 0x0
16192 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_E_ENABLED 0x1
16195 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_LSB 9
16197 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_MSB 9
16199 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_WIDTH 1
16201 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_SET_MSK 0x00000200
16203 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_CLR_MSK 0xfffffdff
16205 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_RESET 0x0
16207 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_GET(value) (((value) & 0x00000200) >> 9)
16209 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_9_SET(value) (((value) << 9) & 0x00000200)
16237 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_DISABLED 0x0
16243 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_E_ENABLED 0x1
16246 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_LSB 10
16248 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_MSB 10
16250 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_WIDTH 1
16252 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_SET_MSK 0x00000400
16254 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_CLR_MSK 0xfffffbff
16256 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_RESET 0x0
16258 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_GET(value) (((value) & 0x00000400) >> 10)
16260 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_10_SET(value) (((value) << 10) & 0x00000400)
16288 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_DISABLED 0x0
16294 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_E_ENABLED 0x1
16297 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_LSB 11
16299 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_MSB 11
16301 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_WIDTH 1
16303 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_SET_MSK 0x00000800
16305 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_CLR_MSK 0xfffff7ff
16307 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_RESET 0x0
16309 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_GET(value) (((value) & 0x00000800) >> 11)
16311 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_11_SET(value) (((value) << 11) & 0x00000800)
16339 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_DISABLED 0x0
16345 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_E_ENABLED 0x1
16348 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_LSB 12
16350 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_MSB 12
16352 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_WIDTH 1
16354 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_SET_MSK 0x00001000
16356 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_CLR_MSK 0xffffefff
16358 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_RESET 0x0
16360 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_GET(value) (((value) & 0x00001000) >> 12)
16362 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_12_SET(value) (((value) << 12) & 0x00001000)
16390 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_DISABLED 0x0
16396 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_E_ENABLED 0x1
16399 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_LSB 13
16401 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_MSB 13
16403 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_WIDTH 1
16405 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_SET_MSK 0x00002000
16407 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_CLR_MSK 0xffffdfff
16409 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_RESET 0x0
16411 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_GET(value) (((value) & 0x00002000) >> 13)
16413 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_13_SET(value) (((value) << 13) & 0x00002000)
16441 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_DISABLED 0x0
16447 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_E_ENABLED 0x1
16450 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_LSB 14
16452 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_MSB 14
16454 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_WIDTH 1
16456 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_SET_MSK 0x00004000
16458 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_CLR_MSK 0xffffbfff
16460 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_RESET 0x0
16462 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_GET(value) (((value) & 0x00004000) >> 14)
16464 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_14_SET(value) (((value) << 14) & 0x00004000)
16492 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_DISABLED 0x0
16498 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_E_ENABLED 0x1
16501 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_LSB 15
16503 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_MSB 15
16505 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_WIDTH 1
16507 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_SET_MSK 0x00008000
16509 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_CLR_MSK 0xffff7fff
16511 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_RESET 0x0
16513 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_GET(value) (((value) & 0x00008000) >> 15)
16515 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_15_SET(value) (((value) << 15) & 0x00008000)
16517 #ifndef __ASSEMBLY__
16529 struct ALT_SDMMC_BACK_END_POWER_R_s
16531 volatile uint32_t BACK_END_POWER_0 : 1;
16532 volatile uint32_t BACK_END_POWER_1 : 1;
16533 volatile uint32_t BACK_END_POWER_2 : 1;
16534 volatile uint32_t BACK_END_POWER_3 : 1;
16535 volatile uint32_t BACK_END_POWER_4 : 1;
16536 volatile uint32_t BACK_END_POWER_5 : 1;
16537 volatile uint32_t BACK_END_POWER_6 : 1;
16538 volatile uint32_t BACK_END_POWER_7 : 1;
16539 volatile uint32_t BACK_END_POWER_8 : 1;
16540 volatile uint32_t BACK_END_POWER_9 : 1;
16541 volatile uint32_t BACK_END_POWER_10 : 1;
16542 volatile uint32_t BACK_END_POWER_11 : 1;
16543 volatile uint32_t BACK_END_POWER_12 : 1;
16544 volatile uint32_t BACK_END_POWER_13 : 1;
16545 volatile uint32_t BACK_END_POWER_14 : 1;
16546 volatile uint32_t BACK_END_POWER_15 : 1;
16551 typedef struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
16555 #define ALT_SDMMC_BACK_END_POWER_R_RESET 0x00000000
16557 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
16559 #define ALT_SDMMC_BACK_END_POWER_R_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_BACK_END_POWER_R_OFST))
16628 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_DISABLED 0x0
16634 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_E_ENABLED 0x1
16637 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_LSB 0
16639 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_MSB 0
16641 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_WIDTH 1
16643 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_SET_MSK 0x00000001
16645 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_CLR_MSK 0xfffffffe
16647 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_RESET 0x0
16649 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_GET(value) (((value) & 0x00000001) >> 0)
16651 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_0_SET(value) (((value) << 0) & 0x00000001)
16684 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_DISABLED 0x0
16690 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_E_ENABLED 0x1
16693 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_LSB 1
16695 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_MSB 1
16697 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_WIDTH 1
16699 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_SET_MSK 0x00000002
16701 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_CLR_MSK 0xfffffffd
16703 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_RESET 0x0
16705 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_GET(value) (((value) & 0x00000002) >> 1)
16707 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_1_SET(value) (((value) << 1) & 0x00000002)
16740 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_DISABLED 0x0
16746 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_E_ENABLED 0x1
16749 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_LSB 2
16751 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_MSB 2
16753 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_WIDTH 1
16755 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_SET_MSK 0x00000004
16757 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_CLR_MSK 0xfffffffb
16759 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_RESET 0x0
16761 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_GET(value) (((value) & 0x00000004) >> 2)
16763 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_2_SET(value) (((value) << 2) & 0x00000004)
16796 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_DISABLED 0x0
16802 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_E_ENABLED 0x1
16805 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_LSB 3
16807 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_MSB 3
16809 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_WIDTH 1
16811 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_SET_MSK 0x00000008
16813 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_CLR_MSK 0xfffffff7
16815 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_RESET 0x0
16817 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_GET(value) (((value) & 0x00000008) >> 3)
16819 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_3_SET(value) (((value) << 3) & 0x00000008)
16852 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_DISABLED 0x0
16858 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_E_ENABLED 0x1
16861 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_LSB 4
16863 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_MSB 4
16865 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_WIDTH 1
16867 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_SET_MSK 0x00000010
16869 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_CLR_MSK 0xffffffef
16871 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_RESET 0x0
16873 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_GET(value) (((value) & 0x00000010) >> 4)
16875 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_4_SET(value) (((value) << 4) & 0x00000010)
16908 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_DISABLED 0x0
16914 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_E_ENABLED 0x1
16917 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_LSB 5
16919 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_MSB 5
16921 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_WIDTH 1
16923 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_SET_MSK 0x00000020
16925 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_CLR_MSK 0xffffffdf
16927 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_RESET 0x0
16929 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_GET(value) (((value) & 0x00000020) >> 5)
16931 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_5_SET(value) (((value) << 5) & 0x00000020)
16964 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_DISABLED 0x0
16970 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_E_ENABLED 0x1
16973 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_LSB 6
16975 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_MSB 6
16977 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_WIDTH 1
16979 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_SET_MSK 0x00000040
16981 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_CLR_MSK 0xffffffbf
16983 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_RESET 0x0
16985 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_GET(value) (((value) & 0x00000040) >> 6)
16987 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_6_SET(value) (((value) << 6) & 0x00000040)
17020 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_DISABLED 0x0
17026 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_E_ENABLED 0x1
17029 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_LSB 7
17031 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_MSB 7
17033 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_WIDTH 1
17035 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_SET_MSK 0x00000080
17037 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_CLR_MSK 0xffffff7f
17039 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_RESET 0x0
17041 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_GET(value) (((value) & 0x00000080) >> 7)
17043 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_7_SET(value) (((value) << 7) & 0x00000080)
17076 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_DISABLED 0x0
17082 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_E_ENABLED 0x1
17085 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_LSB 8
17087 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_MSB 8
17089 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_WIDTH 1
17091 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_SET_MSK 0x00000100
17093 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_CLR_MSK 0xfffffeff
17095 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_RESET 0x0
17097 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_GET(value) (((value) & 0x00000100) >> 8)
17099 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_8_SET(value) (((value) << 8) & 0x00000100)
17132 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_DISABLED 0x0
17138 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_E_ENABLED 0x1
17141 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_LSB 9
17143 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_MSB 9
17145 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_WIDTH 1
17147 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_SET_MSK 0x00000200
17149 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_CLR_MSK 0xfffffdff
17151 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_RESET 0x0
17153 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_GET(value) (((value) & 0x00000200) >> 9)
17155 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_9_SET(value) (((value) << 9) & 0x00000200)
17188 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_DISABLED 0x0
17194 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_E_ENABLED 0x1
17197 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_LSB 10
17199 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_MSB 10
17201 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_WIDTH 1
17203 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_SET_MSK 0x00000400
17205 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_CLR_MSK 0xfffffbff
17207 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_RESET 0x0
17209 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_GET(value) (((value) & 0x00000400) >> 10)
17211 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_10_SET(value) (((value) << 10) & 0x00000400)
17244 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_DISABLED 0x0
17250 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_E_ENABLED 0x1
17253 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_LSB 11
17255 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_MSB 11
17257 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_WIDTH 1
17259 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_SET_MSK 0x00000800
17261 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_CLR_MSK 0xfffff7ff
17263 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_RESET 0x0
17265 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_GET(value) (((value) & 0x00000800) >> 11)
17267 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_11_SET(value) (((value) << 11) & 0x00000800)
17300 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_DISABLED 0x0
17306 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_E_ENABLED 0x1
17309 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_LSB 12
17311 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_MSB 12
17313 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_WIDTH 1
17315 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_SET_MSK 0x00001000
17317 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_CLR_MSK 0xffffefff
17319 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_RESET 0x0
17321 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_GET(value) (((value) & 0x00001000) >> 12)
17323 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_12_SET(value) (((value) << 12) & 0x00001000)
17356 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_DISABLED 0x0
17362 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_E_ENABLED 0x1
17365 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_LSB 13
17367 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_MSB 13
17369 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_WIDTH 1
17371 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_SET_MSK 0x00002000
17373 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_CLR_MSK 0xffffdfff
17375 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_RESET 0x0
17377 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_GET(value) (((value) & 0x00002000) >> 13)
17379 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_13_SET(value) (((value) << 13) & 0x00002000)
17412 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_DISABLED 0x0
17418 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_E_ENABLED 0x1
17421 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_LSB 14
17423 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_MSB 14
17425 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_WIDTH 1
17427 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_SET_MSK 0x00004000
17429 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_CLR_MSK 0xffffbfff
17431 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_RESET 0x0
17433 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_GET(value) (((value) & 0x00004000) >> 14)
17435 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_14_SET(value) (((value) << 14) & 0x00004000)
17468 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_DISABLED 0x0
17474 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_E_ENABLED 0x1
17477 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_LSB 15
17479 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_MSB 15
17481 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_WIDTH 1
17483 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_SET_MSK 0x00008000
17485 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_CLR_MSK 0xffff7fff
17487 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_RESET 0x0
17489 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_GET(value) (((value) & 0x00008000) >> 15)
17491 #define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_15_SET(value) (((value) << 15) & 0x00008000)
17504 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_LSB 16
17506 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_MSB 22
17508 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_WIDTH 7
17510 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_SET_MSK 0x007f0000
17512 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_CLR_MSK 0xff80ffff
17514 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_RESET 0x0
17516 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_GET(value) (((value) & 0x007f0000) >> 16)
17518 #define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTRL_SET(value) (((value) << 16) & 0x007f0000)
17531 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_LSB 23
17533 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_MSB 29
17535 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_WIDTH 7
17537 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_SET_MSK 0x3f800000
17539 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_CLR_MSK 0xc07fffff
17541 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_RESET 0x0
17543 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_GET(value) (((value) & 0x3f800000) >> 23)
17545 #define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTRL_SET(value) (((value) << 23) & 0x3f800000)
17557 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_LSB 30
17559 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_MSB 31
17561 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_WIDTH 2
17563 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_SET_MSK 0xc0000000
17565 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_CLR_MSK 0x3fffffff
17567 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_RESET 0x0
17569 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_GET(value) (((value) & 0xc0000000) >> 30)
17571 #define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTRL_SET(value) (((value) << 30) & 0xc0000000)
17573 #ifndef __ASSEMBLY__
17585 struct ALT_SDMMC_UHS_REG_EXT_s
17587 volatile uint32_t MMC_VOLT_REG_0 : 1;
17588 volatile uint32_t MMC_VOLT_REG_1 : 1;
17589 volatile uint32_t MMC_VOLT_REG_2 : 1;
17590 volatile uint32_t MMC_VOLT_REG_3 : 1;
17591 volatile uint32_t MMC_VOLT_REG_4 : 1;
17592 volatile uint32_t MMC_VOLT_REG_5 : 1;
17593 volatile uint32_t MMC_VOLT_REG_6 : 1;
17594 volatile uint32_t MMC_VOLT_REG_7 : 1;
17595 volatile uint32_t MMC_VOLT_REG_8 : 1;
17596 volatile uint32_t MMC_VOLT_REG_9 : 1;
17597 volatile uint32_t MMC_VOLT_REG_10 : 1;
17598 volatile uint32_t MMC_VOLT_REG_11 : 1;
17599 volatile uint32_t MMC_VOLT_REG_12 : 1;
17600 volatile uint32_t MMC_VOLT_REG_13 : 1;
17601 volatile uint32_t MMC_VOLT_REG_14 : 1;
17602 volatile uint32_t MMC_VOLT_REG_15 : 1;
17603 volatile uint32_t CLK_SMPL_PHASE_CTRL : 7;
17604 volatile uint32_t CLK_DRV_PHASE_CTRL : 7;
17605 volatile uint32_t EXT_CLK_MUX_CTRL : 2;
17609 typedef struct ALT_SDMMC_UHS_REG_EXT_s ALT_SDMMC_UHS_REG_EXT_t;
17613 #define ALT_SDMMC_UHS_REG_EXT_RESET 0x00000000
17615 #define ALT_SDMMC_UHS_REG_EXT_OFST 0x108
17617 #define ALT_SDMMC_UHS_REG_EXT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_UHS_REG_EXT_OFST))
17672 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_DISABLED 0x0
17678 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_E_ENABLED 0x1
17681 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_LSB 0
17683 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_MSB 0
17685 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_WIDTH 1
17687 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_SET_MSK 0x00000001
17689 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_CLR_MSK 0xfffffffe
17691 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_RESET 0x0
17693 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_GET(value) (((value) & 0x00000001) >> 0)
17695 #define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_0_SET(value) (((value) << 0) & 0x00000001)
17729 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_DISABLED 0x0
17735 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_E_ENABLED 0x1
17738 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_LSB 31
17740 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_MSB 31
17742 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_WIDTH 1
17744 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_SET_MSK 0x80000000
17746 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_CLR_MSK 0x7fffffff
17748 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_RESET 0x0
17750 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_GET(value) (((value) & 0x80000000) >> 31)
17752 #define ALT_SDMMC_EMMC_DDR_REG_HS400_MODE_SET(value) (((value) << 31) & 0x80000000)
17754 #ifndef __ASSEMBLY__
17766 struct ALT_SDMMC_EMMC_DDR_REG_s
17768 volatile uint32_t HALF_START_BIT_0 : 1;
17770 const volatile uint32_t HS400_MODE : 1;
17774 typedef struct ALT_SDMMC_EMMC_DDR_REG_s ALT_SDMMC_EMMC_DDR_REG_t;
17778 #define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000
17780 #define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c
17782 #define ALT_SDMMC_EMMC_DDR_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_EMMC_DDR_REG_OFST))
17834 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_DEFAULT 0x0
17840 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_POSEDGE 0x1
17846 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_NEGEDGE 0x2
17852 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_E_RSVD 0x3
17855 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_LSB 0
17857 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_MSB 1
17859 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_WIDTH 2
17861 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_SET_MSK 0x00000003
17863 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_CLR_MSK 0xfffffffc
17865 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_RESET 0x0
17867 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_GET(value) (((value) & 0x00000003) >> 0)
17869 #define ALT_SDMMC_ENABLE_SHIFT_ENABLE_SHIFT_CARD0_SET(value) (((value) << 0) & 0x00000003)
17871 #ifndef __ASSEMBLY__
17883 struct ALT_SDMMC_ENABLE_SHIFT_s
17885 volatile uint32_t ENABLE_SHIFT_CARD0 : 2;
17890 typedef struct ALT_SDMMC_ENABLE_SHIFT_s ALT_SDMMC_ENABLE_SHIFT_t;
17894 #define ALT_SDMMC_ENABLE_SHIFT_RESET 0x00000000
17896 #define ALT_SDMMC_ENABLE_SHIFT_OFST 0x110
17898 #define ALT_SDMMC_ENABLE_SHIFT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDMMC_ENABLE_SHIFT_OFST))
17923 #define SDMMC_DATA_VALUE_LSB 0
17925 #define SDMMC_DATA_VALUE_MSB 31
17927 #define SDMMC_DATA_VALUE_WIDTH 32
17929 #define SDMMC_DATA_VALUE_SET_MSK 0xffffffff
17931 #define SDMMC_DATA_VALUE_CLR_MSK 0x00000000
17933 #define SDMMC_DATA_VALUE_RESET 0x0
17935 #define SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
17937 #define SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
17939 #ifndef __ASSEMBLY__
17951 struct SDMMC_DATA_s
17953 volatile uint32_t value : 32;
17957 typedef struct SDMMC_DATA_s SDMMC_DATA_t;
17961 #define SDMMC_DATA_RESET 0x00000000
17963 #define SDMMC_DATA_OFST 0x200
17965 #define SDMMC_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + SDMMC_DATA_OFST))
17967 #ifndef __ASSEMBLY__
17981 volatile ALT_SDMMC_CTRL_t CTRL;
17982 volatile ALT_SDMMC_PWREN_t PWREN;
17983 volatile ALT_SDMMC_CLKDIV_t CLKDIV;
17984 volatile ALT_SDMMC_CLKSRC_t CLKSRC;
17985 volatile ALT_SDMMC_CLKENA_t CLKENA;
17986 volatile ALT_SDMMC_TMOUT_t TMOUT;
17987 volatile ALT_SDMMC_CTYPE_t CTYPE;
17988 volatile ALT_SDMMC_BLKSIZ_t BLKSIZ;
17989 volatile ALT_SDMMC_BYTCNT_t BYTCNT;
17990 volatile ALT_SDMMC_INTMASK_t INTMASK;
17991 volatile ALT_SDMMC_CMDARG_t CMDARG;
17992 volatile ALT_SDMMC_CMD_t CMD;
17993 volatile ALT_SDMMC_RESP0_t RESP0;
17994 volatile ALT_SDMMC_RESP1_t RESP1;
17995 volatile ALT_SDMMC_RESP2_t RESP2;
17996 volatile ALT_SDMMC_RESP3_t RESP3;
17997 volatile ALT_SDMMC_MINTSTS_t MINTSTS;
17998 volatile ALT_SDMMC_RINTSTS_t RINTSTS;
17999 volatile ALT_SDMMC_STATUS_t STATUS;
18000 volatile ALT_SDMMC_FIFOTH_t FIFOTH;
18001 volatile ALT_SDMMC_CDETECT_t CDETECT;
18002 volatile ALT_SDMMC_WRTPRT_t WRTPRT;
18003 volatile ALT_SDMMC_GPIO_t GPIO;
18004 volatile ALT_SDMMC_TCBCNT_t TCBCNT;
18005 volatile ALT_SDMMC_TBBCNT_t TBBCNT;
18006 volatile ALT_SDMMC_DEBNCE_t DEBNCE;
18007 volatile ALT_SDMMC_USRID_t USRID;
18008 volatile ALT_SDMMC_VERID_t VERID;
18009 volatile ALT_SDMMC_HCON_t HCON;
18010 volatile ALT_SDMMC_UHS_REG_t UHS_REG;
18011 volatile ALT_SDMMC_RST_N_t RST_n;
18012 volatile uint32_t _pad_0x7c_0x7f;
18013 volatile ALT_SDMMC_BMOD_t BMOD;
18014 volatile ALT_SDMMC_PLDMND_t PLDMND;
18015 volatile ALT_SDMMC_DBADDR_t DBADDR;
18016 volatile ALT_SDMMC_IDSTS_t IDSTS;
18017 volatile ALT_SDMMC_IDINTEN_t IDINTEN;
18018 volatile ALT_SDMMC_DSCADDR_t DSCADDR;
18019 volatile ALT_SDMMC_BUFADDR_t BUFADDR;
18020 volatile uint32_t _pad_0x9c_0xff[25];
18021 volatile ALT_SDMMC_CARDTHRCTL_t CARDTHRCTL;
18022 volatile ALT_SDMMC_BACK_END_POWER_R_t BACK_END_POWER_R;
18023 volatile ALT_SDMMC_UHS_REG_EXT_t UHS_REG_EXT;
18024 volatile ALT_SDMMC_EMMC_DDR_REG_t EMMC_DDR_REG;
18025 volatile ALT_SDMMC_ENABLE_SHIFT_t ENABLE_SHIFT;
18026 volatile uint32_t _pad_0x114_0x1ff[59];
18027 volatile SDMMC_DATA_t DATA;
18028 volatile uint32_t _pad_0x204_0x400[127];
18032 typedef struct ALT_SDMMC_s ALT_SDMMC_t;
18034 struct ALT_SDMMC_raw_s
18036 volatile uint32_t CTRL;
18037 volatile uint32_t PWREN;
18038 volatile uint32_t CLKDIV;
18039 volatile uint32_t CLKSRC;
18040 volatile uint32_t CLKENA;
18041 volatile uint32_t TMOUT;
18042 volatile uint32_t CTYPE;
18043 volatile uint32_t BLKSIZ;
18044 volatile uint32_t BYTCNT;
18045 volatile uint32_t INTMASK;
18046 volatile uint32_t CMDARG;
18047 volatile uint32_t CMD;
18048 volatile uint32_t RESP0;
18049 volatile uint32_t RESP1;
18050 volatile uint32_t RESP2;
18051 volatile uint32_t RESP3;
18052 volatile uint32_t MINTSTS;
18053 volatile uint32_t RINTSTS;
18054 volatile uint32_t STATUS;
18055 volatile uint32_t FIFOTH;
18056 volatile uint32_t CDETECT;
18057 volatile uint32_t WRTPRT;
18058 volatile uint32_t GPIO;
18059 volatile uint32_t TCBCNT;
18060 volatile uint32_t TBBCNT;
18061 volatile uint32_t DEBNCE;
18062 volatile uint32_t USRID;
18063 volatile uint32_t VERID;
18064 volatile uint32_t HCON;
18065 volatile uint32_t UHS_REG;
18066 volatile uint32_t RST_n;
18067 volatile uint32_t _pad_0x7c_0x7f;
18068 volatile uint32_t BMOD;
18069 volatile uint32_t PLDMND;
18070 volatile uint32_t DBADDR;
18071 volatile uint32_t IDSTS;
18072 volatile uint32_t IDINTEN;
18073 volatile uint32_t DSCADDR;
18074 volatile uint32_t BUFADDR;
18075 volatile uint32_t _pad_0x9c_0xff[25];
18076 volatile uint32_t CARDTHRCTL;
18077 volatile uint32_t BACK_END_POWER_R;
18078 volatile uint32_t UHS_REG_EXT;
18079 volatile uint32_t EMMC_DDR_REG;
18080 volatile uint32_t ENABLE_SHIFT;
18081 volatile uint32_t _pad_0x114_0x1ff[59];
18082 volatile uint32_t DATA;
18083 volatile uint32_t _pad_0x204_0x400[127];
18087 typedef struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;