Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_ecc_emac2_tx_ecc.h
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32 
33 /* Altera - ALT_ECC_EMAC2_TX_ECC */
34 
35 #ifndef __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__
36 #define __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_ECC_EMAC2_TX_ECC
50  *
51  */
52 /*
53  * Register : IP_REV_ID
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:-------------------------------------
59  * [15:0] | R | 0x0 | ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV
60  * [31:16] | ??? | 0x0 | *UNDEFINED*
61  *
62  */
63 /*
64  * Field : SIREV
65  *
66  * IP Rev #
67  *
68  * These bits indicate the silicon revision number.
69  *
70  * Field Access Macros:
71  *
72  */
73 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field. */
74 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_LSB 0
75 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field. */
76 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_MSB 15
77 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field. */
78 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_WIDTH 16
79 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field value. */
80 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field value. */
82 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field. */
84 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_RESET 0x0
85 /* Extracts the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV field value from a register. */
86 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 /* Produces a ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV register field value suitable for setting the register. */
88 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 /*
92  * WARNING: The C register and register group struct declarations are provided for
93  * convenience and illustrative purposes. They should, however, be used with
94  * caution as the C language standard provides no guarantees about the alignment or
95  * atomicity of device memory accesses. The recommended practice for writing
96  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
97  * alt_write_word() functions.
98  *
99  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_IP_REV_ID.
100  */
101 struct ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_s
102 {
103  const uint32_t SIREV : 16; /* ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV */
104  uint32_t : 16; /* *UNDEFINED* */
105 };
106 
107 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_IP_REV_ID. */
108 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_s ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_t;
109 #endif /* __ASSEMBLY__ */
110 
111 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID register. */
112 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_RESET 0x00000000
113 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_IP_REV_ID register from the beginning of the component. */
114 #define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_OFST 0x0
115 
116 /*
117  * Register : CTRL
118  *
119  * ECC Control Register
120  *
121  * Register Layout
122  *
123  * Bits | Access | Reset | Description
124  * :--------|:-------|:------|:----------------------------------
125  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN
126  * [7:1] | ??? | 0x0 | *UNDEFINED*
127  * [8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA
128  * [15:9] | ??? | 0x0 | *UNDEFINED*
129  * [16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_CTL_INITA
130  * [31:17] | ??? | 0x0 | *UNDEFINED*
131  *
132  */
133 /*
134  * Field : ECC_EN
135  *
136  * Enable for the ECC detection and correction logic.
137  *
138  * Field Access Macros:
139  *
140  */
141 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field. */
142 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_LSB 0
143 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field. */
144 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_MSB 0
145 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field. */
146 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_WIDTH 1
147 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field value. */
148 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_SET_MSK 0x00000001
149 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field value. */
150 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
151 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field. */
152 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_RESET 0x0
153 /* Extracts the ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN field value from a register. */
154 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
155 /* Produces a ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN register field value suitable for setting the register. */
156 #define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
157 
158 /*
159  * Field : CNT_RSTA
160  *
161  * Enable to reset internal single-bit error counter A value to zero
162  *
163  * Field Access Macros:
164  *
165  */
166 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field. */
167 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_LSB 8
168 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field. */
169 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_MSB 8
170 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field. */
171 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_WIDTH 1
172 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field value. */
173 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
174 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field value. */
175 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
176 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field. */
177 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_RESET 0x0
178 /* Extracts the ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA field value from a register. */
179 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
180 /* Produces a ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA register field value suitable for setting the register. */
181 #define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
182 
183 /*
184  * Field : INITA
185  *
186  * Enable for the hardware memory initialization PORTA.
187  *
188  * Field Access Macros:
189  *
190  */
191 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field. */
192 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_LSB 16
193 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field. */
194 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_MSB 16
195 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field. */
196 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_WIDTH 1
197 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field value. */
198 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_SET_MSK 0x00010000
199 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field value. */
200 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_CLR_MSK 0xfffeffff
201 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field. */
202 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_RESET 0x0
203 /* Extracts the ALT_ECC_EMAC2_TX_ECC_CTL_INITA field value from a register. */
204 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
205 /* Produces a ALT_ECC_EMAC2_TX_ECC_CTL_INITA register field value suitable for setting the register. */
206 #define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
207 
208 #ifndef __ASSEMBLY__
209 /*
210  * WARNING: The C register and register group struct declarations are provided for
211  * convenience and illustrative purposes. They should, however, be used with
212  * caution as the C language standard provides no guarantees about the alignment or
213  * atomicity of device memory accesses. The recommended practice for writing
214  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
215  * alt_write_word() functions.
216  *
217  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_CTL.
218  */
219 struct ALT_ECC_EMAC2_TX_ECC_CTL_s
220 {
221  uint32_t ECC_EN : 1; /* ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN */
222  uint32_t : 7; /* *UNDEFINED* */
223  uint32_t CNT_RSTA : 1; /* ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA */
224  uint32_t : 7; /* *UNDEFINED* */
225  uint32_t INITA : 1; /* ALT_ECC_EMAC2_TX_ECC_CTL_INITA */
226  uint32_t : 15; /* *UNDEFINED* */
227 };
228 
229 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_CTL. */
230 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_CTL_s ALT_ECC_EMAC2_TX_ECC_CTL_t;
231 #endif /* __ASSEMBLY__ */
232 
233 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_CTL register. */
234 #define ALT_ECC_EMAC2_TX_ECC_CTL_RESET 0x00000000
235 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_CTL register from the beginning of the component. */
236 #define ALT_ECC_EMAC2_TX_ECC_CTL_OFST 0x8
237 
238 /*
239  * Register : INITSTAT
240  *
241  * This bit is used to set the initialize the memory and ecc to a known value
242  *
243  * Register Layout
244  *
245  * Bits | Access | Reset | Description
246  * :-------|:-------|:------|:--------------------------------------------
247  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA
248  * [31:1] | ??? | 0x0 | *UNDEFINED*
249  *
250  */
251 /*
252  * Field : INITCOMPLETEA
253  *
254  * This bit is used to verify if the hardware memory initialization has completed
255  * PORTB.
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field. */
261 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_LSB 0
262 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field. */
263 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_MSB 0
264 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field. */
265 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
266 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field value. */
267 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
268 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field value. */
269 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
270 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field. */
271 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
272 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA field value from a register. */
273 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
274 /* Produces a ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA register field value suitable for setting the register. */
275 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
276 
277 #ifndef __ASSEMBLY__
278 /*
279  * WARNING: The C register and register group struct declarations are provided for
280  * convenience and illustrative purposes. They should, however, be used with
281  * caution as the C language standard provides no guarantees about the alignment or
282  * atomicity of device memory accesses. The recommended practice for writing
283  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
284  * alt_write_word() functions.
285  *
286  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_INITSTAT.
287  */
288 struct ALT_ECC_EMAC2_TX_ECC_INITSTAT_s
289 {
290  uint32_t INITCOMPLETEA : 1; /* ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA */
291  uint32_t : 31; /* *UNDEFINED* */
292 };
293 
294 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_INITSTAT. */
295 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_INITSTAT_s ALT_ECC_EMAC2_TX_ECC_INITSTAT_t;
296 #endif /* __ASSEMBLY__ */
297 
298 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INITSTAT register. */
299 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_RESET 0x00000000
300 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_INITSTAT register from the beginning of the component. */
301 #define ALT_ECC_EMAC2_TX_ECC_INITSTAT_OFST 0xc
302 
303 /*
304  * Register : ERRINTEN
305  *
306  * Error Interrupt enable
307  *
308  * Register Layout
309  *
310  * Bits | Access | Reset | Description
311  * :-------|:-------|:------|:----------------------------------------
312  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN
313  * [31:1] | ??? | 0x0 | *UNDEFINED*
314  *
315  */
316 /*
317  * Field : SERRINTEN
318  *
319  * This bit is used to enable the single bit error interrupt of ECC RAM system
320  *
321  * Field Access Macros:
322  *
323  */
324 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field. */
325 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_LSB 0
326 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field. */
327 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_MSB 0
328 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field. */
329 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_WIDTH 1
330 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field value. */
331 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
332 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field value. */
333 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
334 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field. */
335 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_RESET 0x0
336 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN field value from a register. */
337 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
338 /* Produces a ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN register field value suitable for setting the register. */
339 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
340 
341 #ifndef __ASSEMBLY__
342 /*
343  * WARNING: The C register and register group struct declarations are provided for
344  * convenience and illustrative purposes. They should, however, be used with
345  * caution as the C language standard provides no guarantees about the alignment or
346  * atomicity of device memory accesses. The recommended practice for writing
347  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
348  * alt_write_word() functions.
349  *
350  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTEN.
351  */
352 struct ALT_ECC_EMAC2_TX_ECC_ERRINTEN_s
353 {
354  uint32_t SERRINTEN : 1; /* ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN */
355  uint32_t : 31; /* *UNDEFINED* */
356 };
357 
358 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTEN. */
359 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ERRINTEN_s ALT_ECC_EMAC2_TX_ECC_ERRINTEN_t;
360 #endif /* __ASSEMBLY__ */
361 
362 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN register. */
363 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_RESET 0x00000000
364 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ERRINTEN register from the beginning of the component. */
365 #define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_OFST 0x10
366 
367 /*
368  * Register : ERRINTENS
369  *
370  * Error Interrupt set
371  *
372  * Register Layout
373  *
374  * Bits | Access | Reset | Description
375  * :-------|:-------|:------|:----------------------------------------
376  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS
377  * [31:1] | ??? | 0x0 | *UNDEFINED*
378  *
379  */
380 /*
381  * Field : SERRINTS
382  *
383  * This bit is used to set the single-bit error interrupt bit.
384  *
385  * Field Access Macros:
386  *
387  */
388 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field. */
389 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_LSB 0
390 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field. */
391 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_MSB 0
392 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field. */
393 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_WIDTH 1
394 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field value. */
395 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
396 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field value. */
397 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
398 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field. */
399 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_RESET 0x0
400 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS field value from a register. */
401 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
402 /* Produces a ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS register field value suitable for setting the register. */
403 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
404 
405 #ifndef __ASSEMBLY__
406 /*
407  * WARNING: The C register and register group struct declarations are provided for
408  * convenience and illustrative purposes. They should, however, be used with
409  * caution as the C language standard provides no guarantees about the alignment or
410  * atomicity of device memory accesses. The recommended practice for writing
411  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
412  * alt_write_word() functions.
413  *
414  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTENS.
415  */
416 struct ALT_ECC_EMAC2_TX_ECC_ERRINTENS_s
417 {
418  uint32_t SERRINTS : 1; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS */
419  uint32_t : 31; /* *UNDEFINED* */
420 };
421 
422 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTENS. */
423 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ERRINTENS_s ALT_ECC_EMAC2_TX_ECC_ERRINTENS_t;
424 #endif /* __ASSEMBLY__ */
425 
426 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS register. */
427 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_RESET 0x00000000
428 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ERRINTENS register from the beginning of the component. */
429 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_OFST 0x14
430 
431 /*
432  * Register : ERRINTENR
433  *
434  * Error Interrupt reset.
435  *
436  * Register Layout
437  *
438  * Bits | Access | Reset | Description
439  * :-------|:-------|:------|:----------------------------------------
440  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR
441  * [31:1] | ??? | 0x0 | *UNDEFINED*
442  *
443  */
444 /*
445  * Field : SERRINTR
446  *
447  * This bit is used to reset the single-bit error interrupt bit. o
448  *
449  * Reads reflect SERRINTEN.
450  *
451  * 1'b0: Writing of zero has no effect.
452  *
453  * 1'b1: By writing one, this bit will reset SERRINTEN bit to 0. This is performing
454  * a bitwise writing of this feature.
455  *
456  * Field Access Macros:
457  *
458  */
459 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field. */
460 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_LSB 0
461 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field. */
462 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_MSB 0
463 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field. */
464 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_WIDTH 1
465 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field value. */
466 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
467 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field value. */
468 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
469 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field. */
470 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_RESET 0x0
471 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR field value from a register. */
472 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
473 /* Produces a ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR register field value suitable for setting the register. */
474 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
475 
476 #ifndef __ASSEMBLY__
477 /*
478  * WARNING: The C register and register group struct declarations are provided for
479  * convenience and illustrative purposes. They should, however, be used with
480  * caution as the C language standard provides no guarantees about the alignment or
481  * atomicity of device memory accesses. The recommended practice for writing
482  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
483  * alt_write_word() functions.
484  *
485  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTENR.
486  */
487 struct ALT_ECC_EMAC2_TX_ECC_ERRINTENR_s
488 {
489  uint32_t SERRINTR : 1; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR */
490  uint32_t : 31; /* *UNDEFINED* */
491 };
492 
493 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ERRINTENR. */
494 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ERRINTENR_s ALT_ECC_EMAC2_TX_ECC_ERRINTENR_t;
495 #endif /* __ASSEMBLY__ */
496 
497 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR register. */
498 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_RESET 0x00000000
499 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ERRINTENR register from the beginning of the component. */
500 #define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_OFST 0x18
501 
502 /*
503  * Register : INTMODE
504  *
505  * Reads reflect SERRINTEN.
506  *
507  * Register Layout
508  *
509  * Bits | Access | Reset | Description
510  * :--------|:-------|:------|:-------------------------------------
511  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD
512  * [7:1] | ??? | 0x0 | *UNDEFINED*
513  * [8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF
514  * [15:9] | ??? | 0x0 | *UNDEFINED*
515  * [16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP
516  * [31:17] | ??? | 0x0 | *UNDEFINED*
517  *
518  */
519 /*
520  * Field : INTMODE
521  *
522  * Interrupt mode for single-bit errors.
523  *
524  * Field Access Macros:
525  *
526  */
527 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field. */
528 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_LSB 0
529 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field. */
530 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_MSB 0
531 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field. */
532 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_WIDTH 1
533 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field value. */
534 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
535 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field value. */
536 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
537 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field. */
538 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_RESET 0x0
539 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD field value from a register. */
540 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
541 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD register field value suitable for setting the register. */
542 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
543 
544 /*
545  * Field : INTONOVF
546  *
547  * Enable interrupt on overflow.
548  *
549  * Field Access Macros:
550  *
551  */
552 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field. */
553 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_LSB 8
554 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field. */
555 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_MSB 8
556 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field. */
557 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_WIDTH 1
558 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field value. */
559 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
560 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field value. */
561 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
562 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field. */
563 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_RESET 0x0
564 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF field value from a register. */
565 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
566 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF register field value suitable for setting the register. */
567 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
568 
569 /*
570  * Field : INTONCMP
571  *
572  * Enable interrupt on compare.
573  *
574  * Field Access Macros:
575  *
576  */
577 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field. */
578 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_LSB 16
579 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field. */
580 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_MSB 16
581 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field. */
582 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_WIDTH 1
583 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field value. */
584 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
585 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field value. */
586 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
587 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field. */
588 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_RESET 0x0
589 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP field value from a register. */
590 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
591 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP register field value suitable for setting the register. */
592 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
593 
594 #ifndef __ASSEMBLY__
595 /*
596  * WARNING: The C register and register group struct declarations are provided for
597  * convenience and illustrative purposes. They should, however, be used with
598  * caution as the C language standard provides no guarantees about the alignment or
599  * atomicity of device memory accesses. The recommended practice for writing
600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
601  * alt_write_word() functions.
602  *
603  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_INTMOD.
604  */
605 struct ALT_ECC_EMAC2_TX_ECC_INTMOD_s
606 {
607  uint32_t INTMODE : 1; /* ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD */
608  uint32_t : 7; /* *UNDEFINED* */
609  uint32_t INTONOVF : 1; /* ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF */
610  uint32_t : 7; /* *UNDEFINED* */
611  uint32_t INTONCMP : 1; /* ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP */
612  uint32_t : 15; /* *UNDEFINED* */
613 };
614 
615 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_INTMOD. */
616 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_INTMOD_s ALT_ECC_EMAC2_TX_ECC_INTMOD_t;
617 #endif /* __ASSEMBLY__ */
618 
619 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTMOD register. */
620 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_RESET 0x00000000
621 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_INTMOD register from the beginning of the component. */
622 #define ALT_ECC_EMAC2_TX_ECC_INTMOD_OFST 0x1c
623 
624 /*
625  * Register : INTTEST
626  *
627  * This bits is used to test interrupt from ECC RAM to GIC
628  *
629  * Register Layout
630  *
631  * Bits | Access | Reset | Description
632  * :-------|:-------|:------|:------------------------------------
633  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA
634  * [7:1] | ??? | 0x0 | *UNDEFINED*
635  * [8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA
636  * [31:9] | ??? | 0x0 | *UNDEFINED*
637  *
638  */
639 /*
640  * Field : TSERRA
641  *
642  * Test PORTA Single-bit error.
643  *
644  * Field Access Macros:
645  *
646  */
647 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field. */
648 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_LSB 0
649 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field. */
650 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_MSB 0
651 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field. */
652 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_WIDTH 1
653 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field value. */
654 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
655 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field value. */
656 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
657 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field. */
658 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_RESET 0x0
659 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA field value from a register. */
660 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
661 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA register field value suitable for setting the register. */
662 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
663 
664 /*
665  * Field : TDERRA
666  *
667  * Test PORTA Double-bit error.
668  *
669  * Field Access Macros:
670  *
671  */
672 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field. */
673 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_LSB 8
674 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field. */
675 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_MSB 8
676 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field. */
677 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_WIDTH 1
678 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field value. */
679 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
680 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field value. */
681 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
682 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field. */
683 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_RESET 0x0
684 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA field value from a register. */
685 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
686 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA register field value suitable for setting the register. */
687 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
688 
689 #ifndef __ASSEMBLY__
690 /*
691  * WARNING: The C register and register group struct declarations are provided for
692  * convenience and illustrative purposes. They should, however, be used with
693  * caution as the C language standard provides no guarantees about the alignment or
694  * atomicity of device memory accesses. The recommended practice for writing
695  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
696  * alt_write_word() functions.
697  *
698  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_INTTEST.
699  */
700 struct ALT_ECC_EMAC2_TX_ECC_INTTEST_s
701 {
702  uint32_t TSERRA : 1; /* ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA */
703  uint32_t : 7; /* *UNDEFINED* */
704  uint32_t TDERRA : 1; /* ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA */
705  uint32_t : 23; /* *UNDEFINED* */
706 };
707 
708 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_INTTEST. */
709 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_INTTEST_s ALT_ECC_EMAC2_TX_ECC_INTTEST_t;
710 #endif /* __ASSEMBLY__ */
711 
712 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTTEST register. */
713 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_RESET 0x00000000
714 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_INTTEST register from the beginning of the component. */
715 #define ALT_ECC_EMAC2_TX_ECC_INTTEST_OFST 0x24
716 
717 /*
718  * Register : MODSTAT
719  *
720  * Counter feature status flag
721  *
722  * Register Layout
723  *
724  * Bits | Access | Reset | Description
725  * :-------|:-------|:------|:-------------------------------------
726  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA
727  * [31:1] | ??? | 0x0 | *UNDEFINED*
728  *
729  */
730 /*
731  * Field : CMPFLGA
732  *
733  * Port A compare status flag
734  *
735  * Field Access Macros:
736  *
737  */
738 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field. */
739 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_LSB 0
740 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field. */
741 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_MSB 0
742 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field. */
743 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_WIDTH 1
744 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field value. */
745 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
746 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field value. */
747 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
748 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field. */
749 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_RESET 0x0
750 /* Extracts the ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA field value from a register. */
751 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
752 /* Produces a ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA register field value suitable for setting the register. */
753 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
754 
755 #ifndef __ASSEMBLY__
756 /*
757  * WARNING: The C register and register group struct declarations are provided for
758  * convenience and illustrative purposes. They should, however, be used with
759  * caution as the C language standard provides no guarantees about the alignment or
760  * atomicity of device memory accesses. The recommended practice for writing
761  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
762  * alt_write_word() functions.
763  *
764  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_MODSTAT.
765  */
766 struct ALT_ECC_EMAC2_TX_ECC_MODSTAT_s
767 {
768  uint32_t CMPFLGA : 1; /* ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA */
769  uint32_t : 31; /* *UNDEFINED* */
770 };
771 
772 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_MODSTAT. */
773 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_MODSTAT_s ALT_ECC_EMAC2_TX_ECC_MODSTAT_t;
774 #endif /* __ASSEMBLY__ */
775 
776 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_MODSTAT register. */
777 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_RESET 0x00000000
778 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_MODSTAT register from the beginning of the component. */
779 #define ALT_ECC_EMAC2_TX_ECC_MODSTAT_OFST 0x28
780 
781 /*
782  * Register : DERRADDRA
783  *
784  * This register shows the address of PORTA current double-bit error. RAM size will
785  * determine the maximum number of address bits.
786  *
787  * Register Layout
788  *
789  * Bits | Access | Reset | Description
790  * :--------|:-------|:------|:------------------------------------
791  * [9:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR
792  * [31:10] | ??? | 0x0 | *UNDEFINED*
793  *
794  */
795 /*
796  * Field : Address
797  *
798  * Recent double-bit error address.
799  *
800  * Field Access Macros:
801  *
802  */
803 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field. */
804 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_LSB 0
805 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field. */
806 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_MSB 9
807 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field. */
808 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_WIDTH 10
809 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field value. */
810 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_SET_MSK 0x000003ff
811 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field value. */
812 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
813 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field. */
814 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_RESET 0x0
815 /* Extracts the ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR field value from a register. */
816 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
817 /* Produces a ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR register field value suitable for setting the register. */
818 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
819 
820 #ifndef __ASSEMBLY__
821 /*
822  * WARNING: The C register and register group struct declarations are provided for
823  * convenience and illustrative purposes. They should, however, be used with
824  * caution as the C language standard provides no guarantees about the alignment or
825  * atomicity of device memory accesses. The recommended practice for writing
826  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
827  * alt_write_word() functions.
828  *
829  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_DERRADDRA.
830  */
831 struct ALT_ECC_EMAC2_TX_ECC_DERRADDRA_s
832 {
833  uint32_t Address : 10; /* ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR */
834  uint32_t : 22; /* *UNDEFINED* */
835 };
836 
837 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_DERRADDRA. */
838 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_DERRADDRA_s ALT_ECC_EMAC2_TX_ECC_DERRADDRA_t;
839 #endif /* __ASSEMBLY__ */
840 
841 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA register. */
842 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_RESET 0x00000000
843 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_DERRADDRA register from the beginning of the component. */
844 #define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_OFST 0x2c
845 
846 /*
847  * Register : SERRADDRA
848  *
849  * This register shows the address of PORTA current single-bit error. RAM size will
850  * determine the maximum number of address bits.
851  *
852  * Register Layout
853  *
854  * Bits | Access | Reset | Description
855  * :--------|:-------|:------|:------------------------------------
856  * [9:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR
857  * [31:10] | ??? | 0x0 | *UNDEFINED*
858  *
859  */
860 /*
861  * Field : Address
862  *
863  * Recent single-bit error address.
864  *
865  * Field Access Macros:
866  *
867  */
868 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field. */
869 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_LSB 0
870 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field. */
871 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_MSB 9
872 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field. */
873 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_WIDTH 10
874 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field value. */
875 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_SET_MSK 0x000003ff
876 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field value. */
877 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
878 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field. */
879 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_RESET 0x0
880 /* Extracts the ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR field value from a register. */
881 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
882 /* Produces a ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR register field value suitable for setting the register. */
883 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
884 
885 #ifndef __ASSEMBLY__
886 /*
887  * WARNING: The C register and register group struct declarations are provided for
888  * convenience and illustrative purposes. They should, however, be used with
889  * caution as the C language standard provides no guarantees about the alignment or
890  * atomicity of device memory accesses. The recommended practice for writing
891  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
892  * alt_write_word() functions.
893  *
894  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_SERRADDRA.
895  */
896 struct ALT_ECC_EMAC2_TX_ECC_SERRADDRA_s
897 {
898  uint32_t Address : 10; /* ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR */
899  uint32_t : 22; /* *UNDEFINED* */
900 };
901 
902 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_SERRADDRA. */
903 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_SERRADDRA_s ALT_ECC_EMAC2_TX_ECC_SERRADDRA_t;
904 #endif /* __ASSEMBLY__ */
905 
906 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA register. */
907 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_RESET 0x00000000
908 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_SERRADDRA register from the beginning of the component. */
909 #define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_OFST 0x30
910 
911 /*
912  * Register : INTSTAT
913  *
914  * This bit is used to enable interrupt generation on SERR lookup table overflow.
915  * When all the entries in the table are valid=1 and this is bit is enabled,
916  * serr_req signal will be asserted.
917  *
918  * Register Layout
919  *
920  * Bits | Access | Reset | Description
921  * :-------|:-------|:------|:--------------------------------------
922  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA
923  * [7:1] | ??? | 0x0 | *UNDEFINED*
924  * [8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA
925  * [31:9] | ??? | 0x0 | *UNDEFINED*
926  *
927  */
928 /*
929  * Field : SERRPENA
930  *
931  * Single-bit error pending for PORTA.
932  *
933  * Field Access Macros:
934  *
935  */
936 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field. */
937 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_LSB 0
938 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field. */
939 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_MSB 0
940 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field. */
941 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_WIDTH 1
942 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field value. */
943 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
944 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field value. */
945 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
946 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field. */
947 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_RESET 0x0
948 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA field value from a register. */
949 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
950 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA register field value suitable for setting the register. */
951 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
952 
953 /*
954  * Field : DERRPENA
955  *
956  * Double-bit error pending for PORTA.
957  *
958  * Field Access Macros:
959  *
960  */
961 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field. */
962 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_LSB 8
963 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field. */
964 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_MSB 8
965 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field. */
966 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_WIDTH 1
967 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field value. */
968 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
969 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field value. */
970 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
971 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field. */
972 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_RESET 0x0
973 /* Extracts the ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA field value from a register. */
974 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
975 /* Produces a ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA register field value suitable for setting the register. */
976 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
977 
978 #ifndef __ASSEMBLY__
979 /*
980  * WARNING: The C register and register group struct declarations are provided for
981  * convenience and illustrative purposes. They should, however, be used with
982  * caution as the C language standard provides no guarantees about the alignment or
983  * atomicity of device memory accesses. The recommended practice for writing
984  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
985  * alt_write_word() functions.
986  *
987  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_INTSTAT.
988  */
989 struct ALT_ECC_EMAC2_TX_ECC_INTSTAT_s
990 {
991  uint32_t SERRPENA : 1; /* ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA */
992  uint32_t : 7; /* *UNDEFINED* */
993  uint32_t DERRPENA : 1; /* ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA */
994  uint32_t : 23; /* *UNDEFINED* */
995 };
996 
997 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_INTSTAT. */
998 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_INTSTAT_s ALT_ECC_EMAC2_TX_ECC_INTSTAT_t;
999 #endif /* __ASSEMBLY__ */
1000 
1001 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_INTSTAT register. */
1002 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_RESET 0x00000000
1003 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_INTSTAT register from the beginning of the component. */
1004 #define ALT_ECC_EMAC2_TX_ECC_INTSTAT_OFST 0x20
1005 
1006 /*
1007  * Register : SERRCNTREG
1008  *
1009  * Maximum counter value for single-bit error interrupt
1010  *
1011  * Register Layout
1012  *
1013  * Bits | Access | Reset | Description
1014  * :-------|:-------|:------|:----------------------------------------
1015  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT
1016  *
1017  */
1018 /*
1019  * Field : SERRCNT
1020  *
1021  * Counter value
1022  *
1023  * Field Access Macros:
1024  *
1025  */
1026 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field. */
1027 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_LSB 0
1028 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field. */
1029 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_MSB 31
1030 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field. */
1031 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1032 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field value. */
1033 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1034 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field value. */
1035 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1036 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field. */
1037 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1038 /* Extracts the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT field value from a register. */
1039 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1040 /* Produces a ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT register field value suitable for setting the register. */
1041 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1042 
1043 #ifndef __ASSEMBLY__
1044 /*
1045  * WARNING: The C register and register group struct declarations are provided for
1046  * convenience and illustrative purposes. They should, however, be used with
1047  * caution as the C language standard provides no guarantees about the alignment or
1048  * atomicity of device memory accesses. The recommended practice for writing
1049  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1050  * alt_write_word() functions.
1051  *
1052  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_SERRCNTREG.
1053  */
1054 struct ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_s
1055 {
1056  uint32_t SERRCNT : 32; /* ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT */
1057 };
1058 
1059 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_SERRCNTREG. */
1060 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_s ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_t;
1061 #endif /* __ASSEMBLY__ */
1062 
1063 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG register. */
1064 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_RESET 0x00000000
1065 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_SERRCNTREG register from the beginning of the component. */
1066 #define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_OFST 0x3c
1067 
1068 /*
1069  * Register : ECC_Addrbus
1070  *
1071  * MSB bit of address is determined by ADR.
1072  *
1073  * Register Layout
1074  *
1075  * Bits | Access | Reset | Description
1076  * :--------|:-------|:------|:---------------------------------------------
1077  * [9:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS
1078  * [31:10] | ??? | 0x0 | *UNDEFINED*
1079  *
1080  */
1081 /*
1082  * Field : ECC_AddrBUS
1083  *
1084  * Address will be driven to RAM to either read or write the data. Address will be
1085  * latched by the RAM when the Enbus is asserted.
1086  *
1087  * Field Access Macros:
1088  *
1089  */
1090 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1091 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1092 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1093 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 9
1094 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1095 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1096 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1097 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1098 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value. */
1099 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1100 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field. */
1101 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1102 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS field value from a register. */
1103 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1104 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS register field value suitable for setting the register. */
1105 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1106 
1107 #ifndef __ASSEMBLY__
1108 /*
1109  * WARNING: The C register and register group struct declarations are provided for
1110  * convenience and illustrative purposes. They should, however, be used with
1111  * caution as the C language standard provides no guarantees about the alignment or
1112  * atomicity of device memory accesses. The recommended practice for writing
1113  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1114  * alt_write_word() functions.
1115  *
1116  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS.
1117  */
1118 struct ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_s
1119 {
1120  uint32_t ECC_AddrBUS : 10; /* ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS */
1121  uint32_t : 22; /* *UNDEFINED* */
1122 };
1123 
1124 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS. */
1125 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_s ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_t;
1126 #endif /* __ASSEMBLY__ */
1127 
1128 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS register. */
1129 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_RESET 0x00000000
1130 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS register from the beginning of the component. */
1131 #define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_OFST 0x40
1132 
1133 /*
1134  * Register : ECC_RData0bus
1135  *
1136  * Data will be read to this register field.
1137  *
1138  * Register Layout
1139  *
1140  * Bits | Access | Reset | Description
1141  * :-------|:-------|:------|:------------------------------------------------
1142  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS
1143  *
1144  */
1145 /*
1146  * Field : ECC_RDataBUS
1147  *
1148  * ECC_RDataBUS[31:0].
1149  *
1150  * Field Access Macros:
1151  *
1152  */
1153 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1154 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1155 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1156 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1157 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1158 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1159 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
1160 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1161 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value. */
1162 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1163 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field. */
1164 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1165 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS field value from a register. */
1166 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1167 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS register field value suitable for setting the register. */
1168 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1169 
1170 #ifndef __ASSEMBLY__
1171 /*
1172  * WARNING: The C register and register group struct declarations are provided for
1173  * convenience and illustrative purposes. They should, however, be used with
1174  * caution as the C language standard provides no guarantees about the alignment or
1175  * atomicity of device memory accesses. The recommended practice for writing
1176  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1177  * alt_write_word() functions.
1178  *
1179  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS.
1180  */
1181 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_s
1182 {
1183  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS */
1184 };
1185 
1186 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS. */
1187 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_t;
1188 #endif /* __ASSEMBLY__ */
1189 
1190 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS register. */
1191 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_RESET 0x00000000
1192 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS register from the beginning of the component. */
1193 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_OFST 0x44
1194 
1195 /*
1196  * Register : ECC_RData1bus
1197  *
1198  * Data will be read to this register field.
1199  *
1200  * Register Layout
1201  *
1202  * Bits | Access | Reset | Description
1203  * :-------|:-------|:------|:------------------------------------------------
1204  * [2:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS
1205  * [31:3] | ??? | 0x0 | *UNDEFINED*
1206  *
1207  */
1208 /*
1209  * Field : ECC_RDataBUS
1210  *
1211  * ECC_RDataBUS[63:32].
1212  *
1213  * Field Access Macros:
1214  *
1215  */
1216 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1217 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1218 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1219 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 2
1220 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1221 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 3
1222 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
1223 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0x00000007
1224 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value. */
1225 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0xfffffff8
1226 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field. */
1227 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1228 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS field value from a register. */
1229 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1230 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS register field value suitable for setting the register. */
1231 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0x00000007)
1232 
1233 #ifndef __ASSEMBLY__
1234 /*
1235  * WARNING: The C register and register group struct declarations are provided for
1236  * convenience and illustrative purposes. They should, however, be used with
1237  * caution as the C language standard provides no guarantees about the alignment or
1238  * atomicity of device memory accesses. The recommended practice for writing
1239  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1240  * alt_write_word() functions.
1241  *
1242  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS.
1243  */
1244 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_s
1245 {
1246  uint32_t ECC_RDataBUS : 3; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS */
1247  uint32_t : 29; /* *UNDEFINED* */
1248 };
1249 
1250 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS. */
1251 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_t;
1252 #endif /* __ASSEMBLY__ */
1253 
1254 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS register. */
1255 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_RESET 0x00000000
1256 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS register from the beginning of the component. */
1257 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_OFST 0x48
1258 
1259 /*
1260  * Register : ECC_RData2bus
1261  *
1262  * Data will be read to this register field.
1263  *
1264  * Register Layout
1265  *
1266  * Bits | Access | Reset | Description
1267  * :-------|:-------|:------|:------------------------------------------------
1268  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS
1269  *
1270  */
1271 /*
1272  * Field : ECC_RDataBUS
1273  *
1274  * ECC_RDataBUS[95:64].
1275  *
1276  * Field Access Macros:
1277  *
1278  */
1279 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1280 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1281 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1282 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1283 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1284 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1285 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
1286 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1287 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value. */
1288 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1289 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field. */
1290 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1291 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS field value from a register. */
1292 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1293 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS register field value suitable for setting the register. */
1294 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1295 
1296 #ifndef __ASSEMBLY__
1297 /*
1298  * WARNING: The C register and register group struct declarations are provided for
1299  * convenience and illustrative purposes. They should, however, be used with
1300  * caution as the C language standard provides no guarantees about the alignment or
1301  * atomicity of device memory accesses. The recommended practice for writing
1302  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1303  * alt_write_word() functions.
1304  *
1305  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS.
1306  */
1307 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_s
1308 {
1309  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS */
1310 };
1311 
1312 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS. */
1313 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_t;
1314 #endif /* __ASSEMBLY__ */
1315 
1316 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS register. */
1317 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_RESET 0x00000000
1318 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS register from the beginning of the component. */
1319 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_OFST 0x4c
1320 
1321 /*
1322  * Register : ECC_RData3bus
1323  *
1324  * Data will be read to this register field.
1325  *
1326  * Register Layout
1327  *
1328  * Bits | Access | Reset | Description
1329  * :-------|:-------|:------|:------------------------------------------------
1330  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS
1331  *
1332  */
1333 /*
1334  * Field : ECC_RDataBUS
1335  *
1336  * ECC_RDataBUS[127-96].
1337  *
1338  * Field Access Macros:
1339  *
1340  */
1341 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1342 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1343 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1344 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1345 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1346 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1347 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
1348 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1349 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value. */
1350 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1351 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field. */
1352 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1353 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS field value from a register. */
1354 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1355 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS register field value suitable for setting the register. */
1356 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1357 
1358 #ifndef __ASSEMBLY__
1359 /*
1360  * WARNING: The C register and register group struct declarations are provided for
1361  * convenience and illustrative purposes. They should, however, be used with
1362  * caution as the C language standard provides no guarantees about the alignment or
1363  * atomicity of device memory accesses. The recommended practice for writing
1364  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1365  * alt_write_word() functions.
1366  *
1367  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS.
1368  */
1369 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_s
1370 {
1371  uint32_t ECC_RDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS */
1372 };
1373 
1374 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS. */
1375 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_t;
1376 #endif /* __ASSEMBLY__ */
1377 
1378 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS register. */
1379 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_RESET 0x00000000
1380 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS register from the beginning of the component. */
1381 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_OFST 0x50
1382 
1383 /*
1384  * Register : ECC_WData0bus
1385  *
1386  * Data from the register will be written to the RAM.
1387  *
1388  * Register Layout
1389  *
1390  * Bits | Access | Reset | Description
1391  * :-------|:-------|:------|:------------------------------------------------
1392  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS
1393  *
1394  */
1395 /*
1396  * Field : ECC_WDataBUS
1397  *
1398  * ECC_WDataBUS[31:0].
1399  *
1400  * Field Access Macros:
1401  *
1402  */
1403 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1404 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1405 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1406 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1407 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1408 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1409 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
1410 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1411 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value. */
1412 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1413 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field. */
1414 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1415 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS field value from a register. */
1416 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1417 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS register field value suitable for setting the register. */
1418 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1419 
1420 #ifndef __ASSEMBLY__
1421 /*
1422  * WARNING: The C register and register group struct declarations are provided for
1423  * convenience and illustrative purposes. They should, however, be used with
1424  * caution as the C language standard provides no guarantees about the alignment or
1425  * atomicity of device memory accesses. The recommended practice for writing
1426  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1427  * alt_write_word() functions.
1428  *
1429  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS.
1430  */
1431 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_s
1432 {
1433  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS */
1434 };
1435 
1436 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS. */
1437 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_t;
1438 #endif /* __ASSEMBLY__ */
1439 
1440 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS register. */
1441 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_RESET 0x00000000
1442 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS register from the beginning of the component. */
1443 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_OFST 0x54
1444 
1445 /*
1446  * Register : ECC_WData1bus
1447  *
1448  * Data from the register will be written to the RAM.
1449  *
1450  * Register Layout
1451  *
1452  * Bits | Access | Reset | Description
1453  * :-------|:-------|:------|:------------------------------------------------
1454  * [2:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS
1455  * [31:3] | ??? | 0x0 | *UNDEFINED*
1456  *
1457  */
1458 /*
1459  * Field : ECC_WDataBUS
1460  *
1461  * ECC_WDataBUS[63:32].
1462  *
1463  * Field Access Macros:
1464  *
1465  */
1466 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1467 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1468 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1469 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 2
1470 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1471 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 3
1472 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
1473 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0x00000007
1474 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value. */
1475 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0xfffffff8
1476 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field. */
1477 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1478 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS field value from a register. */
1479 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1480 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS register field value suitable for setting the register. */
1481 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0x00000007)
1482 
1483 #ifndef __ASSEMBLY__
1484 /*
1485  * WARNING: The C register and register group struct declarations are provided for
1486  * convenience and illustrative purposes. They should, however, be used with
1487  * caution as the C language standard provides no guarantees about the alignment or
1488  * atomicity of device memory accesses. The recommended practice for writing
1489  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1490  * alt_write_word() functions.
1491  *
1492  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS.
1493  */
1494 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_s
1495 {
1496  uint32_t ECC_WDataBUS : 3; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS */
1497  uint32_t : 29; /* *UNDEFINED* */
1498 };
1499 
1500 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS. */
1501 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_t;
1502 #endif /* __ASSEMBLY__ */
1503 
1504 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS register. */
1505 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_RESET 0x00000000
1506 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS register from the beginning of the component. */
1507 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_OFST 0x58
1508 
1509 /*
1510  * Register : ECC_WData2bus
1511  *
1512  * Data from the register will be written to the RAM.
1513  *
1514  * Register Layout
1515  *
1516  * Bits | Access | Reset | Description
1517  * :-------|:-------|:------|:------------------------------------------------
1518  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS
1519  *
1520  */
1521 /*
1522  * Field : ECC_WDataBUS
1523  *
1524  * ECC_WDataBUS[95-64].
1525  *
1526  * Field Access Macros:
1527  *
1528  */
1529 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1530 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1531 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1532 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1533 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1534 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1535 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
1536 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1537 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value. */
1538 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1539 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field. */
1540 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1541 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS field value from a register. */
1542 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1543 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS register field value suitable for setting the register. */
1544 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1545 
1546 #ifndef __ASSEMBLY__
1547 /*
1548  * WARNING: The C register and register group struct declarations are provided for
1549  * convenience and illustrative purposes. They should, however, be used with
1550  * caution as the C language standard provides no guarantees about the alignment or
1551  * atomicity of device memory accesses. The recommended practice for writing
1552  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1553  * alt_write_word() functions.
1554  *
1555  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS.
1556  */
1557 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_s
1558 {
1559  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS */
1560 };
1561 
1562 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS. */
1563 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_t;
1564 #endif /* __ASSEMBLY__ */
1565 
1566 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS register. */
1567 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_RESET 0x00000000
1568 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS register from the beginning of the component. */
1569 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_OFST 0x5c
1570 
1571 /*
1572  * Register : ECC_WData3bus
1573  *
1574  * Data from the register will be written to the RAM.
1575  *
1576  * Register Layout
1577  *
1578  * Bits | Access | Reset | Description
1579  * :-------|:-------|:------|:------------------------------------------------
1580  * [31:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS
1581  *
1582  */
1583 /*
1584  * Field : ECC_WDataBUS
1585  *
1586  * ECC_WDataBUS[127-96].
1587  *
1588  * Field Access Macros:
1589  *
1590  */
1591 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1592 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1593 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1594 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1595 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1596 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1597 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
1598 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1599 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value. */
1600 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1601 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field. */
1602 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1603 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS field value from a register. */
1604 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1605 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS register field value suitable for setting the register. */
1606 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1607 
1608 #ifndef __ASSEMBLY__
1609 /*
1610  * WARNING: The C register and register group struct declarations are provided for
1611  * convenience and illustrative purposes. They should, however, be used with
1612  * caution as the C language standard provides no guarantees about the alignment or
1613  * atomicity of device memory accesses. The recommended practice for writing
1614  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1615  * alt_write_word() functions.
1616  *
1617  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS.
1618  */
1619 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_s
1620 {
1621  uint32_t ECC_WDataBUS : 32; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS */
1622 };
1623 
1624 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS. */
1625 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_t;
1626 #endif /* __ASSEMBLY__ */
1627 
1628 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS register. */
1629 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_RESET 0x00000000
1630 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS register from the beginning of the component. */
1631 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_OFST 0x60
1632 
1633 /*
1634  * Register : ECC_RDataecc0bus
1635  *
1636  * The msb bit for the register is configured based on DAT parameter (RAM word
1637  * size). Unimplemented bytes of this register will be reserved.
1638  *
1639  * Register Layout
1640  *
1641  * Bits | Access | Reset | Description
1642  * :--------|:-------|:------|:-------------------------------------------------------
1643  * [6:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS
1644  * [7] | ??? | 0x0 | *UNDEFINED*
1645  * [14:8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS
1646  * [15] | ??? | 0x0 | *UNDEFINED*
1647  * [22:16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS
1648  * [23] | ??? | 0x0 | *UNDEFINED*
1649  * [30:24] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS
1650  * [31] | ??? | 0x0 | *UNDEFINED*
1651  *
1652  */
1653 /*
1654  * Field : ECC_RDataecc0BUS
1655  *
1656  * Eccdata will be read to this register field.
1657  *
1658  * Field Access Macros:
1659  *
1660  */
1661 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1662 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1663 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1664 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1665 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1666 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1667 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1668 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1669 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value. */
1670 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1671 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field. */
1672 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1673 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register. */
1674 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1675 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register. */
1676 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1677 
1678 /*
1679  * Field : ECC_RDataecc1BUS
1680  *
1681  * Eccdata will be read to this register field.
1682  *
1683  * Field Access Macros:
1684  *
1685  */
1686 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1687 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1688 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1689 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1690 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1691 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1692 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1693 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1694 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value. */
1695 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1696 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field. */
1697 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1698 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register. */
1699 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1700 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register. */
1701 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1702 
1703 /*
1704  * Field : ECC_RDataecc2BUS
1705  *
1706  * Eccdata will be read to this register field.
1707  *
1708  * Field Access Macros:
1709  *
1710  */
1711 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1712 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1713 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1714 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1715 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1716 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1717 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1718 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1719 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value. */
1720 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1721 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field. */
1722 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1723 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register. */
1724 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1725 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register. */
1726 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1727 
1728 /*
1729  * Field : ECC_RDataecc3BUS
1730  *
1731  * Eccdata will be read to this register field.
1732  *
1733  * Field Access Macros:
1734  *
1735  */
1736 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1737 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1738 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1739 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1740 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1741 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1742 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1743 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1744 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value. */
1745 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1746 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field. */
1747 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1748 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register. */
1749 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1750 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register. */
1751 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1752 
1753 #ifndef __ASSEMBLY__
1754 /*
1755  * WARNING: The C register and register group struct declarations are provided for
1756  * convenience and illustrative purposes. They should, however, be used with
1757  * caution as the C language standard provides no guarantees about the alignment or
1758  * atomicity of device memory accesses. The recommended practice for writing
1759  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1760  * alt_write_word() functions.
1761  *
1762  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS.
1763  */
1764 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_s
1765 {
1766  uint32_t ECC_RDataecc0BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS */
1767  uint32_t : 1; /* *UNDEFINED* */
1768  uint32_t ECC_RDataecc1BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS */
1769  uint32_t : 1; /* *UNDEFINED* */
1770  uint32_t ECC_RDataecc2BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS */
1771  uint32_t : 1; /* *UNDEFINED* */
1772  uint32_t ECC_RDataecc3BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS */
1773  uint32_t : 1; /* *UNDEFINED* */
1774 };
1775 
1776 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS. */
1777 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_t;
1778 #endif /* __ASSEMBLY__ */
1779 
1780 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS register. */
1781 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1782 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS register from the beginning of the component. */
1783 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_OFST 0x64
1784 
1785 /*
1786  * Register : ECC_RDataecc1bus
1787  *
1788  * The msb bit for the register is configured based on DAT parameter (RAM word
1789  * size). Unimplemented bytes of this register will be reserved.
1790  *
1791  * Register Layout
1792  *
1793  * Bits | Access | Reset | Description
1794  * :--------|:-------|:------|:-------------------------------------------------------
1795  * [6:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS
1796  * [7] | ??? | 0x0 | *UNDEFINED*
1797  * [14:8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS
1798  * [15] | ??? | 0x0 | *UNDEFINED*
1799  * [22:16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS
1800  * [23] | ??? | 0x0 | *UNDEFINED*
1801  * [30:24] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS
1802  * [31] | ??? | 0x0 | *UNDEFINED*
1803  *
1804  */
1805 /*
1806  * Field : ECC_RDataecc4BUS
1807  *
1808  * Eccdata will be read to this register field.
1809  *
1810  * Field Access Macros:
1811  *
1812  */
1813 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1814 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1815 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1816 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1817 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1818 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1819 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1820 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1821 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value. */
1822 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1823 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field. */
1824 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1825 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS field value from a register. */
1826 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1827 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS register field value suitable for setting the register. */
1828 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1829 
1830 /*
1831  * Field : ECC_RDataecc5BUS
1832  *
1833  * Eccdata will be read to this register field.
1834  *
1835  * Field Access Macros:
1836  *
1837  */
1838 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1839 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1840 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1841 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1842 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1843 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1844 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1845 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1846 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value. */
1847 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1848 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field. */
1849 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1850 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS field value from a register. */
1851 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1852 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS register field value suitable for setting the register. */
1853 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1854 
1855 /*
1856  * Field : ECC_RDataecc6BUS
1857  *
1858  * Eccdata will be read to this register field.
1859  *
1860  * Field Access Macros:
1861  *
1862  */
1863 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1864 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1865 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1866 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1867 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1868 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1869 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1870 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1871 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value. */
1872 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1873 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field. */
1874 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1875 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS field value from a register. */
1876 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1877 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS register field value suitable for setting the register. */
1878 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1879 
1880 /*
1881  * Field : ECC_RDataecc7BUS
1882  *
1883  * Eccdata will be read to this register field.
1884  *
1885  * Field Access Macros:
1886  *
1887  */
1888 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1889 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1890 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1891 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1892 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1893 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1894 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1895 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1896 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value. */
1897 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1898 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field. */
1899 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1900 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS field value from a register. */
1901 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1902 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS register field value suitable for setting the register. */
1903 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1904 
1905 #ifndef __ASSEMBLY__
1906 /*
1907  * WARNING: The C register and register group struct declarations are provided for
1908  * convenience and illustrative purposes. They should, however, be used with
1909  * caution as the C language standard provides no guarantees about the alignment or
1910  * atomicity of device memory accesses. The recommended practice for writing
1911  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1912  * alt_write_word() functions.
1913  *
1914  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS.
1915  */
1916 struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_s
1917 {
1918  uint32_t ECC_RDataecc4BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS */
1919  uint32_t : 1; /* *UNDEFINED* */
1920  uint32_t ECC_RDataecc5BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS */
1921  uint32_t : 1; /* *UNDEFINED* */
1922  uint32_t ECC_RDataecc6BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS */
1923  uint32_t : 1; /* *UNDEFINED* */
1924  uint32_t ECC_RDataecc7BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS */
1925  uint32_t : 1; /* *UNDEFINED* */
1926 };
1927 
1928 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS. */
1929 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_t;
1930 #endif /* __ASSEMBLY__ */
1931 
1932 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS register. */
1933 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1934 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS register from the beginning of the component. */
1935 #define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_OFST 0x68
1936 
1937 /*
1938  * Register : ECC_WDataecc0bus
1939  *
1940  * The msb bit for the register is configured based on DAT parameter (RAM word
1941  * size). Unimplemented bytes of this register will be reserved.
1942  *
1943  * Register Layout
1944  *
1945  * Bits | Access | Reset | Description
1946  * :--------|:-------|:------|:-------------------------------------------------------
1947  * [6:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS
1948  * [7] | ??? | 0x0 | *UNDEFINED*
1949  * [14:8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS
1950  * [15] | ??? | 0x0 | *UNDEFINED*
1951  * [22:16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS
1952  * [23] | ??? | 0x0 | *UNDEFINED*
1953  * [30:24] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS
1954  * [31] | ??? | 0x0 | *UNDEFINED*
1955  *
1956  */
1957 /*
1958  * Field : ECC_WDataecc0BUS
1959  *
1960  * Eccdata from the register will be written to the RAM.
1961  *
1962  * Field Access Macros:
1963  *
1964  */
1965 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1966 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1967 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1968 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1969 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1970 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1971 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
1972 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1973 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value. */
1974 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1975 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field. */
1976 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1977 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register. */
1978 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1979 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register. */
1980 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1981 
1982 /*
1983  * Field : ECC_WDataecc1BUS
1984  *
1985  * Eccdata from the register will be written to the RAM.
1986  *
1987  * Field Access Macros:
1988  *
1989  */
1990 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
1991 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
1992 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
1993 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
1994 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
1995 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
1996 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
1997 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
1998 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value. */
1999 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2000 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field. */
2001 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2002 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register. */
2003 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2004 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register. */
2005 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2006 
2007 /*
2008  * Field : ECC_WDataecc2BUS
2009  *
2010  * Eccdata from the register will be written to the RAM.
2011  *
2012  * Field Access Macros:
2013  *
2014  */
2015 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2016 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2017 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2018 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2019 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2020 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2021 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2022 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2023 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value. */
2024 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2025 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field. */
2026 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2027 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register. */
2028 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2029 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register. */
2030 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2031 
2032 /*
2033  * Field : ECC_WDataecc3BUS
2034  *
2035  * Eccdata from the register will be written to the RAM.
2036  *
2037  * Field Access Macros:
2038  *
2039  */
2040 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2041 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2042 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2043 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2044 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2045 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2046 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2047 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2048 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value. */
2049 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2050 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field. */
2051 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2052 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register. */
2053 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2054 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register. */
2055 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2056 
2057 #ifndef __ASSEMBLY__
2058 /*
2059  * WARNING: The C register and register group struct declarations are provided for
2060  * convenience and illustrative purposes. They should, however, be used with
2061  * caution as the C language standard provides no guarantees about the alignment or
2062  * atomicity of device memory accesses. The recommended practice for writing
2063  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2064  * alt_write_word() functions.
2065  *
2066  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS.
2067  */
2068 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_s
2069 {
2070  uint32_t ECC_WDataecc0BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS */
2071  uint32_t : 1; /* *UNDEFINED* */
2072  uint32_t ECC_WDataecc1BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS */
2073  uint32_t : 1; /* *UNDEFINED* */
2074  uint32_t ECC_WDataecc2BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS */
2075  uint32_t : 1; /* *UNDEFINED* */
2076  uint32_t ECC_WDataecc3BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS */
2077  uint32_t : 1; /* *UNDEFINED* */
2078 };
2079 
2080 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS. */
2081 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_t;
2082 #endif /* __ASSEMBLY__ */
2083 
2084 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS register. */
2085 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2086 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS register from the beginning of the component. */
2087 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2088 
2089 /*
2090  * Register : ECC_WDataecc1bus
2091  *
2092  * The msb bit for the register is configured based on DAT parameter (RAM word
2093  * size). Unimplemented bytes of this register will be reserved.
2094  *
2095  * Register Layout
2096  *
2097  * Bits | Access | Reset | Description
2098  * :--------|:-------|:------|:-------------------------------------------------------
2099  * [6:0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS
2100  * [7] | ??? | 0x0 | *UNDEFINED*
2101  * [14:8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS
2102  * [15] | ??? | 0x0 | *UNDEFINED*
2103  * [22:16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS
2104  * [23] | ??? | 0x0 | *UNDEFINED*
2105  * [30:24] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS
2106  * [31] | ??? | 0x0 | *UNDEFINED*
2107  *
2108  */
2109 /*
2110  * Field : ECC_WDataecc4BUS
2111  *
2112  * Eccdata from the register will be written to the RAM.
2113  *
2114  * Field Access Macros:
2115  *
2116  */
2117 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2118 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2119 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2120 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2121 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2122 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2123 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2124 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2125 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value. */
2126 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2127 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field. */
2128 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2129 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register. */
2130 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2131 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register. */
2132 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2133 
2134 /*
2135  * Field : ECC_WDataecc5BUS
2136  *
2137  * Eccdata from the register will be written to the RAM.
2138  *
2139  * Field Access Macros:
2140  *
2141  */
2142 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2143 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2144 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2145 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2146 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2147 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2148 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2149 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2150 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value. */
2151 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2152 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field. */
2153 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2154 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register. */
2155 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2156 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register. */
2157 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2158 
2159 /*
2160  * Field : ECC_WDataecc6BUS
2161  *
2162  * Eccdata from the register will be written to the RAM.
2163  *
2164  * Field Access Macros:
2165  *
2166  */
2167 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2168 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2169 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2170 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2171 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2172 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2173 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2174 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2175 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value. */
2176 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2177 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field. */
2178 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2179 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register. */
2180 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2181 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register. */
2182 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2183 
2184 /*
2185  * Field : ECC_WDataecc7BUS
2186  *
2187  * Eccdata from the register will be written to the RAM.
2188  *
2189  * Field Access Macros:
2190  *
2191  */
2192 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2193 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2194 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2195 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2196 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2197 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2198 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2199 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2200 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value. */
2201 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2202 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field. */
2203 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2204 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register. */
2205 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2206 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register. */
2207 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2208 
2209 #ifndef __ASSEMBLY__
2210 /*
2211  * WARNING: The C register and register group struct declarations are provided for
2212  * convenience and illustrative purposes. They should, however, be used with
2213  * caution as the C language standard provides no guarantees about the alignment or
2214  * atomicity of device memory accesses. The recommended practice for writing
2215  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2216  * alt_write_word() functions.
2217  *
2218  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS.
2219  */
2220 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_s
2221 {
2222  uint32_t ECC_WDataecc4BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS */
2223  uint32_t : 1; /* *UNDEFINED* */
2224  uint32_t ECC_WDataecc5BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS */
2225  uint32_t : 1; /* *UNDEFINED* */
2226  uint32_t ECC_WDataecc6BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS */
2227  uint32_t : 1; /* *UNDEFINED* */
2228  uint32_t ECC_WDataecc7BUS : 7; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS */
2229  uint32_t : 1; /* *UNDEFINED* */
2230 };
2231 
2232 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS. */
2233 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_s ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_t;
2234 #endif /* __ASSEMBLY__ */
2235 
2236 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS register. */
2237 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2238 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS register from the beginning of the component. */
2239 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_OFST 0x70
2240 
2241 /*
2242  * Register : ECC_dbytectrl
2243  *
2244  * Max number of implemented byte enabled is DAT/8
2245  *
2246  * Register Layout
2247  *
2248  * Bits | Access | Reset | Description
2249  * :-------|:-------|:------|:---------------------------------------
2250  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN
2251  * [31:1] | ??? | 0x0 | *UNDEFINED*
2252  *
2253  */
2254 /*
2255  * Field : DBEN
2256  *
2257  * Byte or word enable for access.
2258  *
2259  * Field Access Macros:
2260  *
2261  */
2262 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field. */
2263 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_LSB 0
2264 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field. */
2265 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_MSB 0
2266 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field. */
2267 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_WIDTH 1
2268 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field value. */
2269 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x00000001
2270 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field value. */
2271 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2272 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field. */
2273 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2274 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN field value from a register. */
2275 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2276 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN register field value suitable for setting the register. */
2277 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2278 
2279 #ifndef __ASSEMBLY__
2280 /*
2281  * WARNING: The C register and register group struct declarations are provided for
2282  * convenience and illustrative purposes. They should, however, be used with
2283  * caution as the C language standard provides no guarantees about the alignment or
2284  * atomicity of device memory accesses. The recommended practice for writing
2285  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2286  * alt_write_word() functions.
2287  *
2288  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL.
2289  */
2290 struct ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_s
2291 {
2292  uint32_t DBEN : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN */
2293  uint32_t : 31; /* *UNDEFINED* */
2294 };
2295 
2296 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL. */
2297 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_s ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_t;
2298 #endif /* __ASSEMBLY__ */
2299 
2300 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL register. */
2301 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_RESET 0x00000000
2302 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL register from the beginning of the component. */
2303 #define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_OFST 0x74
2304 
2305 /*
2306  * Register : ECC_accctrl
2307  *
2308  * These bits determine which byte of data/ecc to write to RAM.
2309  *
2310  * Register Layout
2311  *
2312  * Bits | Access | Reset | Description
2313  * :-------|:-------|:------|:----------------------------------------
2314  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR
2315  * [1] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR
2316  * [7:2] | ??? | 0x0 | *UNDEFINED*
2317  * [8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR
2318  * [31:9] | ??? | 0x0 | *UNDEFINED*
2319  *
2320  */
2321 /*
2322  * Field : DATAOVR
2323  *
2324  * RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode
2325  * set by ECC_RW.
2326  *
2327  * 1'b0: Data override disabled.
2328  *
2329  * 1'b1: Data override enabled.
2330  *
2331  * Field Access Macros:
2332  *
2333  */
2334 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field. */
2335 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2336 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field. */
2337 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2338 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field. */
2339 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2340 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value. */
2341 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2342 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value. */
2343 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2344 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field. */
2345 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2346 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR field value from a register. */
2347 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2348 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value suitable for setting the register. */
2349 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2350 
2351 /*
2352  * Field : ECCOVR
2353  *
2354  * ECC Data Override.
2355  *
2356  * Field Access Macros:
2357  *
2358  */
2359 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field. */
2360 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2361 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field. */
2362 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2363 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field. */
2364 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2365 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value. */
2366 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2367 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value. */
2368 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2369 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field. */
2370 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2371 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR field value from a register. */
2372 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2373 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value suitable for setting the register. */
2374 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2375 
2376 /*
2377  * Field : RDWR
2378  *
2379  * Control for read/write.
2380  *
2381  * Field Access Macros:
2382  *
2383  */
2384 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field. */
2385 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_LSB 8
2386 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field. */
2387 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_MSB 8
2388 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field. */
2389 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2390 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value. */
2391 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2392 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value. */
2393 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2394 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field. */
2395 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2396 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR field value from a register. */
2397 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2398 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value suitable for setting the register. */
2399 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2400 
2401 #ifndef __ASSEMBLY__
2402 /*
2403  * WARNING: The C register and register group struct declarations are provided for
2404  * convenience and illustrative purposes. They should, however, be used with
2405  * caution as the C language standard provides no guarantees about the alignment or
2406  * atomicity of device memory accesses. The recommended practice for writing
2407  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2408  * alt_write_word() functions.
2409  *
2410  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL.
2411  */
2412 struct ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s
2413 {
2414  uint32_t DATAOVR : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR */
2415  uint32_t ECCOVR : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR */
2416  uint32_t : 6; /* *UNDEFINED* */
2417  uint32_t RDWR : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR */
2418  uint32_t : 23; /* *UNDEFINED* */
2419 };
2420 
2421 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL. */
2422 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_t;
2423 #endif /* __ASSEMBLY__ */
2424 
2425 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL register. */
2426 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RESET 0x00000000
2427 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL register from the beginning of the component. */
2428 #define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_OFST 0x78
2429 
2430 /*
2431  * Register : ECC_startacc
2432  *
2433  * These bits determine which byte of data/ecc to write to RAM.
2434  *
2435  * Register Layout
2436  *
2437  * Bits | Access | Reset | Description
2438  * :--------|:-------|:------|:-----------------------------------------
2439  * [15:0] | ??? | 0x0 | *UNDEFINED*
2440  * [16] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA
2441  * [31:17] | ??? | 0x0 | *UNDEFINED*
2442  *
2443  */
2444 /*
2445  * Field : ENBUSA
2446  *
2447  * Start RAM access for PORTA.
2448  *
2449  * Field Access Macros:
2450  *
2451  */
2452 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field. */
2453 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_LSB 16
2454 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field. */
2455 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_MSB 16
2456 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field. */
2457 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2458 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field value. */
2459 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2460 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field value. */
2461 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2462 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field. */
2463 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2464 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA field value from a register. */
2465 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2466 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA register field value suitable for setting the register. */
2467 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2468 
2469 #ifndef __ASSEMBLY__
2470 /*
2471  * WARNING: The C register and register group struct declarations are provided for
2472  * convenience and illustrative purposes. They should, however, be used with
2473  * caution as the C language standard provides no guarantees about the alignment or
2474  * atomicity of device memory accesses. The recommended practice for writing
2475  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2476  * alt_write_word() functions.
2477  *
2478  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC.
2479  */
2480 struct ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_s
2481 {
2482  uint32_t : 16; /* *UNDEFINED* */
2483  uint32_t ENBUSA : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA */
2484  uint32_t : 15; /* *UNDEFINED* */
2485 };
2486 
2487 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC. */
2488 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_s ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_t;
2489 #endif /* __ASSEMBLY__ */
2490 
2491 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC register. */
2492 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_RESET 0x00000000
2493 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC register from the beginning of the component. */
2494 #define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_OFST 0x7c
2495 
2496 /*
2497  * Register : ECC_wdctrl
2498  *
2499  * Bits to Enable/Disable Watch Dog Timer
2500  *
2501  * Register Layout
2502  *
2503  * Bits | Access | Reset | Description
2504  * :-------|:-------|:------|:----------------------------------------
2505  * [0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM
2506  * [31:1] | ??? | 0x0 | *UNDEFINED*
2507  *
2508  */
2509 /*
2510  * Field : WDEN_RAM
2511  *
2512  * Enable watchdog timeout for OCP register access to IP RAM.
2513  *
2514  * Field Access Macros:
2515  *
2516  */
2517 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field. */
2518 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2519 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field. */
2520 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2521 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field. */
2522 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2523 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field value. */
2524 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2525 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field value. */
2526 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2527 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field. */
2528 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2529 /* Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM field value from a register. */
2530 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2531 /* Produces a ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM register field value suitable for setting the register. */
2532 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2533 
2534 #ifndef __ASSEMBLY__
2535 /*
2536  * WARNING: The C register and register group struct declarations are provided for
2537  * convenience and illustrative purposes. They should, however, be used with
2538  * caution as the C language standard provides no guarantees about the alignment or
2539  * atomicity of device memory accesses. The recommended practice for writing
2540  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2541  * alt_write_word() functions.
2542  *
2543  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL.
2544  */
2545 struct ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_s
2546 {
2547  uint32_t WDEN_RAM : 1; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM */
2548  uint32_t : 31; /* *UNDEFINED* */
2549 };
2550 
2551 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL. */
2552 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_s ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_t;
2553 #endif /* __ASSEMBLY__ */
2554 
2555 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL register. */
2556 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_RESET 0x00000000
2557 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL register from the beginning of the component. */
2558 #define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_OFST 0x80
2559 
2560 /*
2561  * Register : SERRLKUPA0
2562  *
2563  * Single-bit error address in LOOKUP TABLE for PORTA.
2564  *
2565  * Register Layout
2566  *
2567  * Bits | Access | Reset | Description
2568  * :--------|:-------|:------|:--------------------------------------
2569  * [9:0] | R | 0x0 | ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR
2570  * [30:10] | ??? | 0x0 | *UNDEFINED*
2571  * [31] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID
2572  *
2573  */
2574 /*
2575  * Field : Address
2576  *
2577  * Recent Single-bit error address.
2578  *
2579  * This register shows the address of the each single-bit error. RAM size will
2580  * determine the maximum number of address bits. If ram size is 32 Kbytes, bit
2581  * 30-16 will be reserved and read as zero.
2582  *
2583  * Field Access Macros:
2584  *
2585  */
2586 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field. */
2587 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_LSB 0
2588 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field. */
2589 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_MSB 9
2590 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field. */
2591 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_WIDTH 10
2592 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value. */
2593 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
2594 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value. */
2595 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
2596 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field. */
2597 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_RESET 0x0
2598 /* Extracts the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR field value from a register. */
2599 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2600 /* Produces a ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value suitable for setting the register. */
2601 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2602 
2603 /*
2604  * Field : VALID
2605  *
2606  * Valid flag bit. Valid bit indicates if the address in this register is current
2607  * or stale.
2608  *
2609  * Field Access Macros:
2610  *
2611  */
2612 /* The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field. */
2613 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_LSB 31
2614 /* The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field. */
2615 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_MSB 31
2616 /* The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field. */
2617 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_WIDTH 1
2618 /* The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value. */
2619 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2620 /* The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value. */
2621 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2622 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field. */
2623 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_RESET 0x0
2624 /* Extracts the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID field value from a register. */
2625 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2626 /* Produces a ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value suitable for setting the register. */
2627 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2628 
2629 #ifndef __ASSEMBLY__
2630 /*
2631  * WARNING: The C register and register group struct declarations are provided for
2632  * convenience and illustrative purposes. They should, however, be used with
2633  * caution as the C language standard provides no guarantees about the alignment or
2634  * atomicity of device memory accesses. The recommended practice for writing
2635  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2636  * alt_write_word() functions.
2637  *
2638  * The struct declaration for register ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0.
2639  */
2640 struct ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s
2641 {
2642  const uint32_t Address : 10; /* ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR */
2643  uint32_t : 21; /* *UNDEFINED* */
2644  uint32_t VALID : 1; /* ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID */
2645 };
2646 
2647 /* The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0. */
2648 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_t;
2649 #endif /* __ASSEMBLY__ */
2650 
2651 /* The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 register. */
2652 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_RESET 0x00000000
2653 /* The byte offset of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 register from the beginning of the component. */
2654 #define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_OFST 0x90
2655 
2656 #ifndef __ASSEMBLY__
2657 /*
2658  * WARNING: The C register and register group struct declarations are provided for
2659  * convenience and illustrative purposes. They should, however, be used with
2660  * caution as the C language standard provides no guarantees about the alignment or
2661  * atomicity of device memory accesses. The recommended practice for writing
2662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2663  * alt_write_word() functions.
2664  *
2665  * The struct declaration for register group ALT_ECC_EMAC2_TX_ECC.
2666  */
2667 struct ALT_ECC_EMAC2_TX_ECC_s
2668 {
2669  ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_t IP_REV_ID; /* ALT_ECC_EMAC2_TX_ECC_IP_REV_ID */
2670  volatile uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2671  ALT_ECC_EMAC2_TX_ECC_CTL_t CTRL; /* ALT_ECC_EMAC2_TX_ECC_CTL */
2672  ALT_ECC_EMAC2_TX_ECC_INITSTAT_t INITSTAT; /* ALT_ECC_EMAC2_TX_ECC_INITSTAT */
2673  ALT_ECC_EMAC2_TX_ECC_ERRINTEN_t ERRINTEN; /* ALT_ECC_EMAC2_TX_ECC_ERRINTEN */
2674  ALT_ECC_EMAC2_TX_ECC_ERRINTENS_t ERRINTENS; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENS */
2675  ALT_ECC_EMAC2_TX_ECC_ERRINTENR_t ERRINTENR; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENR */
2676  ALT_ECC_EMAC2_TX_ECC_INTMOD_t INTMODE; /* ALT_ECC_EMAC2_TX_ECC_INTMOD */
2677  ALT_ECC_EMAC2_TX_ECC_INTSTAT_t INTSTAT; /* ALT_ECC_EMAC2_TX_ECC_INTSTAT */
2678  ALT_ECC_EMAC2_TX_ECC_INTTEST_t INTTEST; /* ALT_ECC_EMAC2_TX_ECC_INTTEST */
2679  ALT_ECC_EMAC2_TX_ECC_MODSTAT_t MODSTAT; /* ALT_ECC_EMAC2_TX_ECC_MODSTAT */
2680  ALT_ECC_EMAC2_TX_ECC_DERRADDRA_t DERRADDRA; /* ALT_ECC_EMAC2_TX_ECC_DERRADDRA */
2681  ALT_ECC_EMAC2_TX_ECC_SERRADDRA_t SERRADDRA; /* ALT_ECC_EMAC2_TX_ECC_SERRADDRA */
2682  volatile uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2683  ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_t SERRCNTREG; /* ALT_ECC_EMAC2_TX_ECC_SERRCNTREG */
2684  ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_t ECC_Addrbus; /* ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS */
2685  ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_t ECC_RData0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS */
2686  ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_t ECC_RData1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS */
2687  ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_t ECC_RData2bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS */
2688  ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_t ECC_RData3bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS */
2689  ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_t ECC_WData0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS */
2690  ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_t ECC_WData1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS */
2691  ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_t ECC_WData2bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS */
2692  ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_t ECC_WData3bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS */
2693  ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_t ECC_RDataecc0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS */
2694  ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_t ECC_RDataecc1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS */
2695  ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_t ECC_WDataecc0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS */
2696  ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_t ECC_WDataecc1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS */
2697  ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_t ECC_dbytectrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL */
2698  ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_t ECC_accctrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL */
2699  ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_t ECC_startacc; /* ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC */
2700  ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_t ECC_wdctrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL */
2701  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2702  ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_t SERRLKUPA0; /* ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 */
2703  volatile uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2704 };
2705 
2706 /* The typedef declaration for register group ALT_ECC_EMAC2_TX_ECC. */
2707 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_s ALT_ECC_EMAC2_TX_ECC_t;
2708 /* The struct declaration for the raw register contents of register group ALT_ECC_EMAC2_TX_ECC. */
2709 struct ALT_ECC_EMAC2_TX_ECC_raw_s
2710 {
2711  volatile uint32_t IP_REV_ID; /* ALT_ECC_EMAC2_TX_ECC_IP_REV_ID */
2712  uint32_t _pad_0x4_0x7; /* *UNDEFINED* */
2713  volatile uint32_t CTRL; /* ALT_ECC_EMAC2_TX_ECC_CTL */
2714  volatile uint32_t INITSTAT; /* ALT_ECC_EMAC2_TX_ECC_INITSTAT */
2715  volatile uint32_t ERRINTEN; /* ALT_ECC_EMAC2_TX_ECC_ERRINTEN */
2716  volatile uint32_t ERRINTENS; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENS */
2717  volatile uint32_t ERRINTENR; /* ALT_ECC_EMAC2_TX_ECC_ERRINTENR */
2718  volatile uint32_t INTMODE; /* ALT_ECC_EMAC2_TX_ECC_INTMOD */
2719  volatile uint32_t INTSTAT; /* ALT_ECC_EMAC2_TX_ECC_INTSTAT */
2720  volatile uint32_t INTTEST; /* ALT_ECC_EMAC2_TX_ECC_INTTEST */
2721  volatile uint32_t MODSTAT; /* ALT_ECC_EMAC2_TX_ECC_MODSTAT */
2722  volatile uint32_t DERRADDRA; /* ALT_ECC_EMAC2_TX_ECC_DERRADDRA */
2723  volatile uint32_t SERRADDRA; /* ALT_ECC_EMAC2_TX_ECC_SERRADDRA */
2724  uint32_t _pad_0x34_0x3b[2]; /* *UNDEFINED* */
2725  volatile uint32_t SERRCNTREG; /* ALT_ECC_EMAC2_TX_ECC_SERRCNTREG */
2726  volatile uint32_t ECC_Addrbus; /* ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS */
2727  volatile uint32_t ECC_RData0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS */
2728  volatile uint32_t ECC_RData1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS */
2729  volatile uint32_t ECC_RData2bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS */
2730  volatile uint32_t ECC_RData3bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS */
2731  volatile uint32_t ECC_WData0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS */
2732  volatile uint32_t ECC_WData1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS */
2733  volatile uint32_t ECC_WData2bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS */
2734  volatile uint32_t ECC_WData3bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS */
2735  volatile uint32_t ECC_RDataecc0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS */
2736  volatile uint32_t ECC_RDataecc1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS */
2737  volatile uint32_t ECC_WDataecc0bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS */
2738  volatile uint32_t ECC_WDataecc1bus; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS */
2739  volatile uint32_t ECC_dbytectrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL */
2740  volatile uint32_t ECC_accctrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL */
2741  volatile uint32_t ECC_startacc; /* ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC */
2742  volatile uint32_t ECC_wdctrl; /* ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL */
2743  uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
2744  volatile uint32_t SERRLKUPA0; /* ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 */
2745  uint32_t _pad_0x94_0x400[219]; /* *UNDEFINED* */
2746 };
2747 
2748 /* The typedef declaration for the raw register contents of register group ALT_ECC_EMAC2_TX_ECC. */
2749 typedef volatile struct ALT_ECC_EMAC2_TX_ECC_raw_s ALT_ECC_EMAC2_TX_ECC_raw_t;
2750 #endif /* __ASSEMBLY__ */
2751 
2752 
2753 #ifdef __cplusplus
2754 }
2755 #endif /* __cplusplus */
2756 #endif /* __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__ */
2757