Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
 All Groups
alt_uart.h
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32 
33 /* Altera - ALT_UART */
34 
35 #ifndef __ALT_SOCAL_UART_H__
36 #define __ALT_SOCAL_UART_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_UART
50  *
51  */
52 /*
53  * Register : Rx Buffer, Tx Holding, and Divisor Latch Low - rbr_thr_dll
54  *
55  * This is a multi-function register. This register holds receives and transmit
56  * data and controls the least-signficant 8 bits of the baud rate divisor.
57  *
58  * Register Layout
59  *
60  * Bits | Access | Reset | Description
61  * :-------|:-------|:------|:--------------------------------------------
62  * [7:0] | RW | 0x0 | Value
63  * [31:8] | R | 0x0 | ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8
64  *
65  */
66 /*
67  * Field : Value - value
68  *
69  * Receive Buffer Register:
70  *
71  * This register contains the data byte received on the serial input port
72  * (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0]
73  * in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of
74  * Register FCR is set to 0) the data in the RBR must be read before the next data
75  * arrives, otherwise it will be overwritten, resulting in an overrun error. If
76  * FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses
77  * the head of the receive FIFO. If the receive FIFO is full, and this register is
78  * not read before the next data character arrives, then the data already in the
79  * FIFO will be preserved but any incoming data will be lost. An overrun error will
80  * also occur.
81  *
82  * Transmit Holding Register:
83  *
84  * This register contains data to be transmitted on the serial output port. Data
85  * should only be written to the THR when the THR Empty bit [5] of the LSR Register
86  * is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and
87  * THRE is set to 1, writing a single character to the THR clears the THRE. Any
88  * additional writes to the THR before the THRE is set again causes the THR data to
89  * be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and
90  * THRE is set up to 128 characters of data may be written to the THR before the
91  * FIFO is full. Any attempt to write data when the FIFO is full results in the
92  * write data being lost.
93  *
94  * Divisor Latch Low:
95  *
96  * This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch
97  * register that contains the baud rate divisor for the UART. This register may
98  * only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The
99  * output baud rate is equal to the serial clock l4_sp_clk frequency divided by
100  * sixteen times the value of the baud rate divisor, as follows:
101  *
102  * baud rate = (serial clock freq) / (16 * divisor)
103  *
104  * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud
105  * clock is disabled and no serial communications will occur. Also, once the DLL is
106  * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
107  * transmitting or receiving data.
108  *
109  * Field Access Macros:
110  *
111  */
112 /* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
113 #define ALT_UART_RBR_THR_DLL_VALUE_LSB 0
114 /* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field. */
115 #define ALT_UART_RBR_THR_DLL_VALUE_MSB 7
116 /* The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field. */
117 #define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8
118 /* The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value. */
119 #define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff
120 /* The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value. */
121 #define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00
122 /* The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field. */
123 #define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0
124 /* Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register. */
125 #define ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
126 /* Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register. */
127 #define ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff)
128 
129 /*
130  * Field : rsvd_rbr_thr_dll_31to8
131  *
132  * Reserved bits [31:8] - Read Only
133  *
134  * Field Access Macros:
135  *
136  */
137 /* The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field. */
138 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_LSB 8
139 /* The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field. */
140 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_MSB 31
141 /* The width in bits of the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field. */
142 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_WIDTH 24
143 /* The mask used to set the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field value. */
144 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_SET_MSK 0xffffff00
145 /* The mask used to clear the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field value. */
146 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_CLR_MSK 0x000000ff
147 /* The reset value of the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field. */
148 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_RESET 0x0
149 /* Extracts the ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 field value from a register. */
150 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
151 /* Produces a ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 register field value suitable for setting the register. */
152 #define ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8_SET(value) (((value) << 8) & 0xffffff00)
153 
154 #ifndef __ASSEMBLY__
155 /*
156  * WARNING: The C register and register group struct declarations are provided for
157  * convenience and illustrative purposes. They should, however, be used with
158  * caution as the C language standard provides no guarantees about the alignment or
159  * atomicity of device memory accesses. The recommended practice for writing
160  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
161  * alt_write_word() functions.
162  *
163  * The struct declaration for register ALT_UART_RBR_THR_DLL.
164  */
165 struct ALT_UART_RBR_THR_DLL_s
166 {
167  uint32_t value : 8; /* Value */
168  const uint32_t rsvd_rbr_thr_dll_31to8 : 24; /* ALT_UART_RBR_THR_DLL_RSVD_RBR_THR_DLL_31TO8 */
169 };
170 
171 /* The typedef declaration for register ALT_UART_RBR_THR_DLL. */
172 typedef volatile struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t;
173 #endif /* __ASSEMBLY__ */
174 
175 /* The reset value of the ALT_UART_RBR_THR_DLL register. */
176 #define ALT_UART_RBR_THR_DLL_RESET 0x00000000
177 /* The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component. */
178 #define ALT_UART_RBR_THR_DLL_OFST 0x0
179 /* The address of the ALT_UART_RBR_THR_DLL register. */
180 #define ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST))
181 
182 /*
183  * Register : Interrupt Enable and Divisor Latch High - ier_dlh
184  *
185  * This is a multi-function register. This register enables/disables receive and
186  * transmit interrupts and also controls the most-significant 8-bits of the baud
187  * rate divisor.
188  *
189  * Divisor Latch High Register:
190  *
191  * This register is accessed when the DLAB bit [7] of the LCR Register is set to
192  * 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output
193  * baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen
194  * times the value of the baud rate divisor, as follows:
195  *
196  * baud rate = (serial clock freq) / (16 * divisor):
197  *
198  * Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud
199  * clock is disabled and no serial communications will occur. Also, once the DLL is
200  * set, at least 8 l4_sp_clk clock cycles should be allowed to pass before
201  * transmitting or receiving data.
202  *
203  * Interrupt Enable Register:
204  *
205  * This register may only be accessed when the DLAB bit [7] of the LCR Register is
206  * set to 0.Allows control of the Interrupt Enables for transmit and receive
207  * functions.
208  *
209  * Register Layout
210  *
211  * Bits | Access | Reset | Description
212  * :-------|:-------|:------|:--------------------------------------------
213  * [0] | RW | 0x0 | DLH[0] and Receive Data Interrupt Enable
214  * [1] | RW | 0x0 | DLH[1] and Transmit Data Interrupt Control
215  * [2] | RW | 0x0 | DLH[2] and Enable Receiver Line Status
216  * [3] | RW | 0x0 | DLH[3] and Enable Modem Status Interrupt
217  * [4] | RW | 0x0 | DLH[4]
218  * [5] | RW | 0x0 | DLH[5]
219  * [6] | RW | 0x0 | DLH[6]
220  * [7] | RW | 0x0 | DLH[7] and PTIME THRE Interrupt Mode Enable
221  * [31:8] | R | 0x0 | ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8
222  *
223  */
224 /*
225  * Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0
226  *
227  * Divisor Latch High Register:
228  *
229  * Bit 0 of DLH value.
230  *
231  * Interrupt Enable Register:
232  *
233  * Used to enable/disable the generation of the Receive Data Available Interrupt
234  * and the Character Timeout Interrupt(if FIFO's enabled). These are the second
235  * highest priority interrupts.
236  *
237  * Field Enumeration Values:
238  *
239  * Enum | Value | Description
240  * :-----------------------------------|:------|:------------------
241  * ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD | 0x0 | Interrupt Disable
242  * ALT_UART_IER_DLH_ERBFI_DLH0_E_END | 0x1 | Interrupt Enable
243  *
244  * Field Access Macros:
245  *
246  */
247 /*
248  * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
249  *
250  * Interrupt Disable
251  */
252 #define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0
253 /*
254  * Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0
255  *
256  * Interrupt Enable
257  */
258 #define ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1
259 
260 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
261 #define ALT_UART_IER_DLH_ERBFI_DLH0_LSB 0
262 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
263 #define ALT_UART_IER_DLH_ERBFI_DLH0_MSB 0
264 /* The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
265 #define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH 1
266 /* The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
267 #define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK 0x00000001
268 /* The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value. */
269 #define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK 0xfffffffe
270 /* The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field. */
271 #define ALT_UART_IER_DLH_ERBFI_DLH0_RESET 0x0
272 /* Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register. */
273 #define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value) (((value) & 0x00000001) >> 0)
274 /* Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register. */
275 #define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value) (((value) << 0) & 0x00000001)
276 
277 /*
278  * Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl
279  *
280  * Divisor Latch High Register:
281  *
282  * Bit 1 of DLH value.
283  *
284  * Interrupt Enable Register:
285  *
286  * Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable
287  * the generation of Transmitter Holding Register Empty Interrupt. This is the
288  * third highest priority interrupt.
289  *
290  * Field Enumeration Values:
291  *
292  * Enum | Value | Description
293  * :-----------------------------------|:------|:------------
294  * ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD | 0x0 | Tx disable
295  * ALT_UART_IER_DLH_ETBEI_DLHL_E_END | 0x1 | Tx enable
296  *
297  * Field Access Macros:
298  *
299  */
300 /*
301  * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
302  *
303  * Tx disable
304  */
305 #define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0
306 /*
307  * Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL
308  *
309  * Tx enable
310  */
311 #define ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1
312 
313 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
314 #define ALT_UART_IER_DLH_ETBEI_DLHL_LSB 1
315 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
316 #define ALT_UART_IER_DLH_ETBEI_DLHL_MSB 1
317 /* The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
318 #define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH 1
319 /* The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
320 #define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK 0x00000002
321 /* The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value. */
322 #define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK 0xfffffffd
323 /* The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field. */
324 #define ALT_UART_IER_DLH_ETBEI_DLHL_RESET 0x0
325 /* Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register. */
326 #define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value) (((value) & 0x00000002) >> 1)
327 /* Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register. */
328 #define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value) (((value) << 1) & 0x00000002)
329 
330 /*
331  * Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2
332  *
333  * Divisor Latch High Register:
334  *
335  * Bit 2 of DLH value.
336  *
337  * Interrupt Enable Register:
338  *
339  * This is used to enable/disable the generation of Receiver Line Status Interrupt.
340  * This is the highest priority interrupt.
341  *
342  * Field Enumeration Values:
343  *
344  * Enum | Value | Description
345  * :----------------------------------|:------|:----------------------------
346  * ALT_UART_IER_DLH_ELSI_DHL2_E_DISD | 0x0 | Disable interrupt line stat
347  * ALT_UART_IER_DLH_ELSI_DHL2_E_END | 0x1 | Enable interrupt line stat
348  *
349  * Field Access Macros:
350  *
351  */
352 /*
353  * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
354  *
355  * Disable interrupt line stat
356  */
357 #define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0
358 /*
359  * Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2
360  *
361  * Enable interrupt line stat
362  */
363 #define ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1
364 
365 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
366 #define ALT_UART_IER_DLH_ELSI_DHL2_LSB 2
367 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
368 #define ALT_UART_IER_DLH_ELSI_DHL2_MSB 2
369 /* The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
370 #define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH 1
371 /* The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
372 #define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK 0x00000004
373 /* The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value. */
374 #define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK 0xfffffffb
375 /* The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field. */
376 #define ALT_UART_IER_DLH_ELSI_DHL2_RESET 0x0
377 /* Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register. */
378 #define ALT_UART_IER_DLH_ELSI_DHL2_GET(value) (((value) & 0x00000004) >> 2)
379 /* Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register. */
380 #define ALT_UART_IER_DLH_ELSI_DHL2_SET(value) (((value) << 2) & 0x00000004)
381 
382 /*
383  * Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3
384  *
385  * Divisor Latch High Register:
386  *
387  * Bit 3 of DLH value.
388  *
389  * Interrupt Enable Register:
390  *
391  * This is used to enable/disable the generation of Modem Status Interrupts. This
392  * is the fourth highest priority interrupt.
393  *
394  * Field Enumeration Values:
395  *
396  * Enum | Value | Description
397  * :-----------------------------------|:------|:-------------------------------
398  * ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD | 0x0 | disable modem status interrupt
399  * ALT_UART_IER_DLH_EDSSI_DHL3_E_END | 0x1 | enable modem status interrupt
400  *
401  * Field Access Macros:
402  *
403  */
404 /*
405  * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
406  *
407  * disable modem status interrupt
408  */
409 #define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0
410 /*
411  * Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3
412  *
413  * enable modem status interrupt
414  */
415 #define ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1
416 
417 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
418 #define ALT_UART_IER_DLH_EDSSI_DHL3_LSB 3
419 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
420 #define ALT_UART_IER_DLH_EDSSI_DHL3_MSB 3
421 /* The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
422 #define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH 1
423 /* The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
424 #define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK 0x00000008
425 /* The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value. */
426 #define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK 0xfffffff7
427 /* The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field. */
428 #define ALT_UART_IER_DLH_EDSSI_DHL3_RESET 0x0
429 /* Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register. */
430 #define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value) (((value) & 0x00000008) >> 3)
431 /* Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register. */
432 #define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value) (((value) << 3) & 0x00000008)
433 
434 /*
435  * Field : DLH[4] - dlh4
436  *
437  * Bit 4 of DLH value.
438  *
439  * Field Access Macros:
440  *
441  */
442 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
443 #define ALT_UART_IER_DLH_DLH4_LSB 4
444 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field. */
445 #define ALT_UART_IER_DLH_DLH4_MSB 4
446 /* The width in bits of the ALT_UART_IER_DLH_DLH4 register field. */
447 #define ALT_UART_IER_DLH_DLH4_WIDTH 1
448 /* The mask used to set the ALT_UART_IER_DLH_DLH4 register field value. */
449 #define ALT_UART_IER_DLH_DLH4_SET_MSK 0x00000010
450 /* The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value. */
451 #define ALT_UART_IER_DLH_DLH4_CLR_MSK 0xffffffef
452 /* The reset value of the ALT_UART_IER_DLH_DLH4 register field. */
453 #define ALT_UART_IER_DLH_DLH4_RESET 0x0
454 /* Extracts the ALT_UART_IER_DLH_DLH4 field value from a register. */
455 #define ALT_UART_IER_DLH_DLH4_GET(value) (((value) & 0x00000010) >> 4)
456 /* Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register. */
457 #define ALT_UART_IER_DLH_DLH4_SET(value) (((value) << 4) & 0x00000010)
458 
459 /*
460  * Field : DLH[5] - dlh5
461  *
462  * Bit 5 of DLH value.
463  *
464  * Field Access Macros:
465  *
466  */
467 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
468 #define ALT_UART_IER_DLH_DLH5_LSB 5
469 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field. */
470 #define ALT_UART_IER_DLH_DLH5_MSB 5
471 /* The width in bits of the ALT_UART_IER_DLH_DLH5 register field. */
472 #define ALT_UART_IER_DLH_DLH5_WIDTH 1
473 /* The mask used to set the ALT_UART_IER_DLH_DLH5 register field value. */
474 #define ALT_UART_IER_DLH_DLH5_SET_MSK 0x00000020
475 /* The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value. */
476 #define ALT_UART_IER_DLH_DLH5_CLR_MSK 0xffffffdf
477 /* The reset value of the ALT_UART_IER_DLH_DLH5 register field. */
478 #define ALT_UART_IER_DLH_DLH5_RESET 0x0
479 /* Extracts the ALT_UART_IER_DLH_DLH5 field value from a register. */
480 #define ALT_UART_IER_DLH_DLH5_GET(value) (((value) & 0x00000020) >> 5)
481 /* Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register. */
482 #define ALT_UART_IER_DLH_DLH5_SET(value) (((value) << 5) & 0x00000020)
483 
484 /*
485  * Field : DLH[6] - dlh6
486  *
487  * Bit 6 of DLH value.
488  *
489  * Field Access Macros:
490  *
491  */
492 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
493 #define ALT_UART_IER_DLH_DLH6_LSB 6
494 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field. */
495 #define ALT_UART_IER_DLH_DLH6_MSB 6
496 /* The width in bits of the ALT_UART_IER_DLH_DLH6 register field. */
497 #define ALT_UART_IER_DLH_DLH6_WIDTH 1
498 /* The mask used to set the ALT_UART_IER_DLH_DLH6 register field value. */
499 #define ALT_UART_IER_DLH_DLH6_SET_MSK 0x00000040
500 /* The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value. */
501 #define ALT_UART_IER_DLH_DLH6_CLR_MSK 0xffffffbf
502 /* The reset value of the ALT_UART_IER_DLH_DLH6 register field. */
503 #define ALT_UART_IER_DLH_DLH6_RESET 0x0
504 /* Extracts the ALT_UART_IER_DLH_DLH6 field value from a register. */
505 #define ALT_UART_IER_DLH_DLH6_GET(value) (((value) & 0x00000040) >> 6)
506 /* Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register. */
507 #define ALT_UART_IER_DLH_DLH6_SET(value) (((value) << 6) & 0x00000040)
508 
509 /*
510  * Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7
511  *
512  * Divisor Latch High Register:
513  *
514  * Bit 7 of DLH value.
515  *
516  * Interrupt Enable Register:
517  *
518  * This is used to enable/disable the generation of THRE Interrupt.
519  *
520  * Field Enumeration Values:
521  *
522  * Enum | Value | Description
523  * :-----------------------------------|:------|:------------------------------------
524  * ALT_UART_IER_DLH_PTIME_DLH7_E_DISD | 0x0 | disable tx-hold-reg-empty interrupt
525  * ALT_UART_IER_DLH_PTIME_DLH7_E_END | 0x1 | enable tx-hold-reg-empty interrupt
526  *
527  * Field Access Macros:
528  *
529  */
530 /*
531  * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
532  *
533  * disable tx-hold-reg-empty interrupt
534  */
535 #define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0
536 /*
537  * Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7
538  *
539  * enable tx-hold-reg-empty interrupt
540  */
541 #define ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1
542 
543 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
544 #define ALT_UART_IER_DLH_PTIME_DLH7_LSB 7
545 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
546 #define ALT_UART_IER_DLH_PTIME_DLH7_MSB 7
547 /* The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
548 #define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH 1
549 /* The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
550 #define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK 0x00000080
551 /* The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value. */
552 #define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK 0xffffff7f
553 /* The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field. */
554 #define ALT_UART_IER_DLH_PTIME_DLH7_RESET 0x0
555 /* Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register. */
556 #define ALT_UART_IER_DLH_PTIME_DLH7_GET(value) (((value) & 0x00000080) >> 7)
557 /* Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register. */
558 #define ALT_UART_IER_DLH_PTIME_DLH7_SET(value) (((value) << 7) & 0x00000080)
559 
560 /*
561  * Field : rsvd_ier_dlh_31to8
562  *
563  * Reserved bits [31:8] - Read Only
564  *
565  * Field Access Macros:
566  *
567  */
568 /* The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field. */
569 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_LSB 8
570 /* The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field. */
571 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_MSB 31
572 /* The width in bits of the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field. */
573 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_WIDTH 24
574 /* The mask used to set the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field value. */
575 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_SET_MSK 0xffffff00
576 /* The mask used to clear the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field value. */
577 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_CLR_MSK 0x000000ff
578 /* The reset value of the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field. */
579 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_RESET 0x0
580 /* Extracts the ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 field value from a register. */
581 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
582 /* Produces a ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 register field value suitable for setting the register. */
583 #define ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8_SET(value) (((value) << 8) & 0xffffff00)
584 
585 #ifndef __ASSEMBLY__
586 /*
587  * WARNING: The C register and register group struct declarations are provided for
588  * convenience and illustrative purposes. They should, however, be used with
589  * caution as the C language standard provides no guarantees about the alignment or
590  * atomicity of device memory accesses. The recommended practice for writing
591  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
592  * alt_write_word() functions.
593  *
594  * The struct declaration for register ALT_UART_IER_DLH.
595  */
596 struct ALT_UART_IER_DLH_s
597 {
598  uint32_t erbfi_dlh0 : 1; /* DLH[0] and Receive Data Interrupt Enable */
599  uint32_t etbei_dlhl : 1; /* DLH[1] and Transmit Data Interrupt Control */
600  uint32_t elsi_dhl2 : 1; /* DLH[2] and Enable Receiver Line Status */
601  uint32_t edssi_dhl3 : 1; /* DLH[3] and Enable Modem Status Interrupt */
602  uint32_t dlh4 : 1; /* DLH[4] */
603  uint32_t dlh5 : 1; /* DLH[5] */
604  uint32_t dlh6 : 1; /* DLH[6] */
605  uint32_t ptime_dlh7 : 1; /* DLH[7] and PTIME THRE Interrupt Mode Enable */
606  const uint32_t rsvd_ier_dlh_31to8 : 24; /* ALT_UART_IER_DLH_RSVD_IER_DLH_31TO8 */
607 };
608 
609 /* The typedef declaration for register ALT_UART_IER_DLH. */
610 typedef volatile struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t;
611 #endif /* __ASSEMBLY__ */
612 
613 /* The reset value of the ALT_UART_IER_DLH register. */
614 #define ALT_UART_IER_DLH_RESET 0x00000000
615 /* The byte offset of the ALT_UART_IER_DLH register from the beginning of the component. */
616 #define ALT_UART_IER_DLH_OFST 0x4
617 /* The address of the ALT_UART_IER_DLH register. */
618 #define ALT_UART_IER_DLH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))
619 
620 /*
621  * Register : iir
622  *
623  * Interrupt Identification Register
624  *
625  * Register Layout
626  *
627  * Bits | Access | Reset | Description
628  * :-------|:-------|:------|:----------------------------
629  * [3:0] | R | 0x1 | ALT_UART_IIR_ID
630  * [5:4] | R | 0x0 | ALT_UART_IIR_RSVD_IIR_5TO4
631  * [7:6] | R | 0x0 | ALT_UART_IIR_FIFOEN
632  * [31:8] | R | 0x0 | ALT_UART_IIR_RSVD_IIR_31TO8
633  *
634  */
635 /*
636  * Field : id
637  *
638  * Bits[3:0], Interrupt ID (or IID):
639  *
640  * This indicates the highest priority pending interrupt which can be one of the
641  *
642  * following types:
643  *
644  * 0000 = modem status.
645  *
646  * 0001 = no interrupt pending.
647  *
648  * 0010 = THR empty.
649  *
650  * 0100 = received data available.
651  *
652  * 0110 = receiver line status.
653  *
654  * 0111 = busy detect.
655  *
656  * 1100 = character timeout.
657  *
658  * Note, an interrupt of type 0111 (busy detect) will never get indicated if
659  *
660  * UART_16550_COMPATIBLE == YES in coreConsultant.
661  *
662  * Field Enumeration Values:
663  *
664  * Enum | Value | Description
665  * :---------------------------------|:------|:-----------------------
666  * ALT_UART_IIR_ID_E_MODMSTAT | 0x0 | Modem status
667  * ALT_UART_IIR_ID_E_NOINTRPENDING | 0x1 | No Interrupt pending
668  * ALT_UART_IIR_ID_E_THREMPTY | 0x2 | THR empty
669  * ALT_UART_IIR_ID_E_RXDATAVAILABLE | 0x4 | Receive data available
670  * ALT_UART_IIR_ID_E_RXLINESTAT | 0x6 | Receive line status
671  * ALT_UART_IIR_ID_E_BUSYDETECT | 0x7 | Busy detect
672  * ALT_UART_IIR_ID_E_CHARTMO | 0xc | Character timeout
673  *
674  * Field Access Macros:
675  *
676  */
677 /*
678  * Enumerated value for register field ALT_UART_IIR_ID
679  *
680  * Modem status
681  */
682 #define ALT_UART_IIR_ID_E_MODMSTAT 0x0
683 /*
684  * Enumerated value for register field ALT_UART_IIR_ID
685  *
686  * No Interrupt pending
687  */
688 #define ALT_UART_IIR_ID_E_NOINTRPENDING 0x1
689 /*
690  * Enumerated value for register field ALT_UART_IIR_ID
691  *
692  * THR empty
693  */
694 #define ALT_UART_IIR_ID_E_THREMPTY 0x2
695 /*
696  * Enumerated value for register field ALT_UART_IIR_ID
697  *
698  * Receive data available
699  */
700 #define ALT_UART_IIR_ID_E_RXDATAVAILABLE 0x4
701 /*
702  * Enumerated value for register field ALT_UART_IIR_ID
703  *
704  * Receive line status
705  */
706 #define ALT_UART_IIR_ID_E_RXLINESTAT 0x6
707 /*
708  * Enumerated value for register field ALT_UART_IIR_ID
709  *
710  * Busy detect
711  */
712 #define ALT_UART_IIR_ID_E_BUSYDETECT 0x7
713 /*
714  * Enumerated value for register field ALT_UART_IIR_ID
715  *
716  * Character timeout
717  */
718 #define ALT_UART_IIR_ID_E_CHARTMO 0xc
719 
720 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_ID register field. */
721 #define ALT_UART_IIR_ID_LSB 0
722 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_ID register field. */
723 #define ALT_UART_IIR_ID_MSB 3
724 /* The width in bits of the ALT_UART_IIR_ID register field. */
725 #define ALT_UART_IIR_ID_WIDTH 4
726 /* The mask used to set the ALT_UART_IIR_ID register field value. */
727 #define ALT_UART_IIR_ID_SET_MSK 0x0000000f
728 /* The mask used to clear the ALT_UART_IIR_ID register field value. */
729 #define ALT_UART_IIR_ID_CLR_MSK 0xfffffff0
730 /* The reset value of the ALT_UART_IIR_ID register field. */
731 #define ALT_UART_IIR_ID_RESET 0x1
732 /* Extracts the ALT_UART_IIR_ID field value from a register. */
733 #define ALT_UART_IIR_ID_GET(value) (((value) & 0x0000000f) >> 0)
734 /* Produces a ALT_UART_IIR_ID register field value suitable for setting the register. */
735 #define ALT_UART_IIR_ID_SET(value) (((value) << 0) & 0x0000000f)
736 
737 /*
738  * Field : rsvd_iir_5to4
739  *
740  * Reserved bits [5:4] - Read Only
741  *
742  * Field Access Macros:
743  *
744  */
745 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
746 #define ALT_UART_IIR_RSVD_IIR_5TO4_LSB 4
747 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
748 #define ALT_UART_IIR_RSVD_IIR_5TO4_MSB 5
749 /* The width in bits of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
750 #define ALT_UART_IIR_RSVD_IIR_5TO4_WIDTH 2
751 /* The mask used to set the ALT_UART_IIR_RSVD_IIR_5TO4 register field value. */
752 #define ALT_UART_IIR_RSVD_IIR_5TO4_SET_MSK 0x00000030
753 /* The mask used to clear the ALT_UART_IIR_RSVD_IIR_5TO4 register field value. */
754 #define ALT_UART_IIR_RSVD_IIR_5TO4_CLR_MSK 0xffffffcf
755 /* The reset value of the ALT_UART_IIR_RSVD_IIR_5TO4 register field. */
756 #define ALT_UART_IIR_RSVD_IIR_5TO4_RESET 0x0
757 /* Extracts the ALT_UART_IIR_RSVD_IIR_5TO4 field value from a register. */
758 #define ALT_UART_IIR_RSVD_IIR_5TO4_GET(value) (((value) & 0x00000030) >> 4)
759 /* Produces a ALT_UART_IIR_RSVD_IIR_5TO4 register field value suitable for setting the register. */
760 #define ALT_UART_IIR_RSVD_IIR_5TO4_SET(value) (((value) << 4) & 0x00000030)
761 
762 /*
763  * Field : fifoen
764  *
765  * Bits[7:6], FIFO's Enabled (or FIFOSE):
766  *
767  * This is used to indicate whether the FIFO's are enabled or disabled.
768  *
769  * 00 = disabled.
770  *
771  * 11 = enabled
772  *
773  * Field Enumeration Values:
774  *
775  * Enum | Value | Description
776  * :---------------------------|:------|:--------------
777  * ALT_UART_IIR_FIFOEN_E_DISD | 0x0 | FIFO disabled
778  * ALT_UART_IIR_FIFOEN_E_END | 0x3 | FIFO enabled
779  *
780  * Field Access Macros:
781  *
782  */
783 /*
784  * Enumerated value for register field ALT_UART_IIR_FIFOEN
785  *
786  * FIFO disabled
787  */
788 #define ALT_UART_IIR_FIFOEN_E_DISD 0x0
789 /*
790  * Enumerated value for register field ALT_UART_IIR_FIFOEN
791  *
792  * FIFO enabled
793  */
794 #define ALT_UART_IIR_FIFOEN_E_END 0x3
795 
796 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_FIFOEN register field. */
797 #define ALT_UART_IIR_FIFOEN_LSB 6
798 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_FIFOEN register field. */
799 #define ALT_UART_IIR_FIFOEN_MSB 7
800 /* The width in bits of the ALT_UART_IIR_FIFOEN register field. */
801 #define ALT_UART_IIR_FIFOEN_WIDTH 2
802 /* The mask used to set the ALT_UART_IIR_FIFOEN register field value. */
803 #define ALT_UART_IIR_FIFOEN_SET_MSK 0x000000c0
804 /* The mask used to clear the ALT_UART_IIR_FIFOEN register field value. */
805 #define ALT_UART_IIR_FIFOEN_CLR_MSK 0xffffff3f
806 /* The reset value of the ALT_UART_IIR_FIFOEN register field. */
807 #define ALT_UART_IIR_FIFOEN_RESET 0x0
808 /* Extracts the ALT_UART_IIR_FIFOEN field value from a register. */
809 #define ALT_UART_IIR_FIFOEN_GET(value) (((value) & 0x000000c0) >> 6)
810 /* Produces a ALT_UART_IIR_FIFOEN register field value suitable for setting the register. */
811 #define ALT_UART_IIR_FIFOEN_SET(value) (((value) << 6) & 0x000000c0)
812 
813 /*
814  * Field : rsvd_iir_31to8
815  *
816  * Reserved bits [31:8] - Read Only
817  *
818  * Field Access Macros:
819  *
820  */
821 /* The Least Significant Bit (LSB) position of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
822 #define ALT_UART_IIR_RSVD_IIR_31TO8_LSB 8
823 /* The Most Significant Bit (MSB) position of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
824 #define ALT_UART_IIR_RSVD_IIR_31TO8_MSB 31
825 /* The width in bits of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
826 #define ALT_UART_IIR_RSVD_IIR_31TO8_WIDTH 24
827 /* The mask used to set the ALT_UART_IIR_RSVD_IIR_31TO8 register field value. */
828 #define ALT_UART_IIR_RSVD_IIR_31TO8_SET_MSK 0xffffff00
829 /* The mask used to clear the ALT_UART_IIR_RSVD_IIR_31TO8 register field value. */
830 #define ALT_UART_IIR_RSVD_IIR_31TO8_CLR_MSK 0x000000ff
831 /* The reset value of the ALT_UART_IIR_RSVD_IIR_31TO8 register field. */
832 #define ALT_UART_IIR_RSVD_IIR_31TO8_RESET 0x0
833 /* Extracts the ALT_UART_IIR_RSVD_IIR_31TO8 field value from a register. */
834 #define ALT_UART_IIR_RSVD_IIR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
835 /* Produces a ALT_UART_IIR_RSVD_IIR_31TO8 register field value suitable for setting the register. */
836 #define ALT_UART_IIR_RSVD_IIR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
837 
838 #ifndef __ASSEMBLY__
839 /*
840  * WARNING: The C register and register group struct declarations are provided for
841  * convenience and illustrative purposes. They should, however, be used with
842  * caution as the C language standard provides no guarantees about the alignment or
843  * atomicity of device memory accesses. The recommended practice for writing
844  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
845  * alt_write_word() functions.
846  *
847  * The struct declaration for register ALT_UART_IIR.
848  */
849 struct ALT_UART_IIR_s
850 {
851  const uint32_t id : 4; /* ALT_UART_IIR_ID */
852  const uint32_t rsvd_iir_5to4 : 2; /* ALT_UART_IIR_RSVD_IIR_5TO4 */
853  const uint32_t fifoen : 2; /* ALT_UART_IIR_FIFOEN */
854  const uint32_t rsvd_iir_31to8 : 24; /* ALT_UART_IIR_RSVD_IIR_31TO8 */
855 };
856 
857 /* The typedef declaration for register ALT_UART_IIR. */
858 typedef volatile struct ALT_UART_IIR_s ALT_UART_IIR_t;
859 #endif /* __ASSEMBLY__ */
860 
861 /* The reset value of the ALT_UART_IIR register. */
862 #define ALT_UART_IIR_RESET 0x00000001
863 /* The byte offset of the ALT_UART_IIR register from the beginning of the component. */
864 #define ALT_UART_IIR_OFST 0x8
865 /* The address of the ALT_UART_IIR register. */
866 #define ALT_UART_IIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IIR_OFST))
867 
868 /*
869  * Register : fcr
870  *
871  * FIFO Control Register
872  *
873  * Register Layout
874  *
875  * Bits | Access | Reset | Description
876  * :-------|:-------|:------|:--------------------
877  * [0] | W | 0x0 | ALT_UART_FCR_FIFOE
878  * [1] | W | 0x0 | ALT_UART_FCR_RFIFOR
879  * [2] | W | 0x0 | ALT_UART_FCR_XFIFOR
880  * [3] | W | 0x0 | ALT_UART_FCR_DMAM
881  * [5:4] | W | 0x0 | ALT_UART_FCR_TET
882  * [7:6] | W | 0x0 | ALT_UART_FCR_RT
883  * [31:8] | ??? | 0x0 | *UNDEFINED*
884  *
885  */
886 /*
887  * Field : fifoe
888  *
889  * Bit[0], FIFO Enable (or FIFOE):
890  *
891  * This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever
892  * the
893  *
894  * value of this bit is changed both the XMIT and RCVR controller portion of FIFO's
895  *
896  * will be reset.
897  *
898  * Field Enumeration Values:
899  *
900  * Enum | Value | Description
901  * :--------------------------|:------|:--------------
902  * ALT_UART_FCR_FIFOE_E_DISD | 0x0 | FIFO disabled
903  * ALT_UART_FCR_FIFOE_E_END | 0x1 | FIFO enabled
904  *
905  * Field Access Macros:
906  *
907  */
908 /*
909  * Enumerated value for register field ALT_UART_FCR_FIFOE
910  *
911  * FIFO disabled
912  */
913 #define ALT_UART_FCR_FIFOE_E_DISD 0x0
914 /*
915  * Enumerated value for register field ALT_UART_FCR_FIFOE
916  *
917  * FIFO enabled
918  */
919 #define ALT_UART_FCR_FIFOE_E_END 0x1
920 
921 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field. */
922 #define ALT_UART_FCR_FIFOE_LSB 0
923 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field. */
924 #define ALT_UART_FCR_FIFOE_MSB 0
925 /* The width in bits of the ALT_UART_FCR_FIFOE register field. */
926 #define ALT_UART_FCR_FIFOE_WIDTH 1
927 /* The mask used to set the ALT_UART_FCR_FIFOE register field value. */
928 #define ALT_UART_FCR_FIFOE_SET_MSK 0x00000001
929 /* The mask used to clear the ALT_UART_FCR_FIFOE register field value. */
930 #define ALT_UART_FCR_FIFOE_CLR_MSK 0xfffffffe
931 /* The reset value of the ALT_UART_FCR_FIFOE register field. */
932 #define ALT_UART_FCR_FIFOE_RESET 0x0
933 /* Extracts the ALT_UART_FCR_FIFOE field value from a register. */
934 #define ALT_UART_FCR_FIFOE_GET(value) (((value) & 0x00000001) >> 0)
935 /* Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register. */
936 #define ALT_UART_FCR_FIFOE_SET(value) (((value) << 0) & 0x00000001)
937 
938 /*
939  * Field : rfifor
940  *
941  * Bit[1], RCVR FIFO Reset (or RFIFOR):
942  *
943  * This resets the control portion of the receive FIFO and treats the FIFO as
944  * empty.
945  *
946  * This will also de-assert the DMA RX request and single signals when additional
947  *
948  * DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
949  *
950  * 'self-clearing' and it is not necessary to clear this bit.
951  *
952  * Field Enumeration Values:
953  *
954  * Enum | Value | Description
955  * :--------------------------|:------|:-------------------
956  * ALT_UART_FCR_RFIFOR_E_RST | 0x1 | Receive FIFO reset
957  *
958  * Field Access Macros:
959  *
960  */
961 /*
962  * Enumerated value for register field ALT_UART_FCR_RFIFOR
963  *
964  * Receive FIFO reset
965  */
966 #define ALT_UART_FCR_RFIFOR_E_RST 0x1
967 
968 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field. */
969 #define ALT_UART_FCR_RFIFOR_LSB 1
970 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field. */
971 #define ALT_UART_FCR_RFIFOR_MSB 1
972 /* The width in bits of the ALT_UART_FCR_RFIFOR register field. */
973 #define ALT_UART_FCR_RFIFOR_WIDTH 1
974 /* The mask used to set the ALT_UART_FCR_RFIFOR register field value. */
975 #define ALT_UART_FCR_RFIFOR_SET_MSK 0x00000002
976 /* The mask used to clear the ALT_UART_FCR_RFIFOR register field value. */
977 #define ALT_UART_FCR_RFIFOR_CLR_MSK 0xfffffffd
978 /* The reset value of the ALT_UART_FCR_RFIFOR register field. */
979 #define ALT_UART_FCR_RFIFOR_RESET 0x0
980 /* Extracts the ALT_UART_FCR_RFIFOR field value from a register. */
981 #define ALT_UART_FCR_RFIFOR_GET(value) (((value) & 0x00000002) >> 1)
982 /* Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register. */
983 #define ALT_UART_FCR_RFIFOR_SET(value) (((value) << 1) & 0x00000002)
984 
985 /*
986  * Field : xfifor
987  *
988  * Bit[2], XMIT FIFO Reset (or XFIFOR):
989  *
990  * This resets the control portion of the transmit FIFO and treats the FIFO as
991  * empty.
992  *
993  * This will also de-assert the DMA TX request and single signals when additional
994  *
995  * DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
996  *
997  * 'self-clearing' and it is not necessary to clear this bit.
998  *
999  * Field Enumeration Values:
1000  *
1001  * Enum | Value | Description
1002  * :--------------------------|:------|:--------------------
1003  * ALT_UART_FCR_XFIFOR_E_RST | 0x1 | Transmit FIFO reset
1004  *
1005  * Field Access Macros:
1006  *
1007  */
1008 /*
1009  * Enumerated value for register field ALT_UART_FCR_XFIFOR
1010  *
1011  * Transmit FIFO reset
1012  */
1013 #define ALT_UART_FCR_XFIFOR_E_RST 0x1
1014 
1015 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field. */
1016 #define ALT_UART_FCR_XFIFOR_LSB 2
1017 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field. */
1018 #define ALT_UART_FCR_XFIFOR_MSB 2
1019 /* The width in bits of the ALT_UART_FCR_XFIFOR register field. */
1020 #define ALT_UART_FCR_XFIFOR_WIDTH 1
1021 /* The mask used to set the ALT_UART_FCR_XFIFOR register field value. */
1022 #define ALT_UART_FCR_XFIFOR_SET_MSK 0x00000004
1023 /* The mask used to clear the ALT_UART_FCR_XFIFOR register field value. */
1024 #define ALT_UART_FCR_XFIFOR_CLR_MSK 0xfffffffb
1025 /* The reset value of the ALT_UART_FCR_XFIFOR register field. */
1026 #define ALT_UART_FCR_XFIFOR_RESET 0x0
1027 /* Extracts the ALT_UART_FCR_XFIFOR field value from a register. */
1028 #define ALT_UART_FCR_XFIFOR_GET(value) (((value) & 0x00000004) >> 2)
1029 /* Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register. */
1030 #define ALT_UART_FCR_XFIFOR_SET(value) (((value) << 2) & 0x00000004)
1031 
1032 /*
1033  * Field : dmam
1034  *
1035  * Bit[3], DMA Mode (or DMAM):
1036  *
1037  * This determines the DMA signalling mode used for the dma_tx_req_n and
1038  * dma_rx_req_n
1039  *
1040  * output signals when additional DMA handshaking signals are not selected
1041  *
1042  * (DMA_EXTRA == NO). See section 5.9 on page 56 for details on DMA support.
1043  *
1044  * 0 = mode 0
1045  *
1046  * 1 = mode 1
1047  *
1048  * Field Enumeration Values:
1049  *
1050  * Enum | Value | Description
1051  * :-------------------------|:------|:------------
1052  * ALT_UART_FCR_DMAM_E_MOD0 | 0x0 | Mode 0
1053  * ALT_UART_FCR_DMAM_E_MOD1 | 0x1 | Mode 1
1054  *
1055  * Field Access Macros:
1056  *
1057  */
1058 /*
1059  * Enumerated value for register field ALT_UART_FCR_DMAM
1060  *
1061  * Mode 0
1062  */
1063 #define ALT_UART_FCR_DMAM_E_MOD0 0x0
1064 /*
1065  * Enumerated value for register field ALT_UART_FCR_DMAM
1066  *
1067  * Mode 1
1068  */
1069 #define ALT_UART_FCR_DMAM_E_MOD1 0x1
1070 
1071 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field. */
1072 #define ALT_UART_FCR_DMAM_LSB 3
1073 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field. */
1074 #define ALT_UART_FCR_DMAM_MSB 3
1075 /* The width in bits of the ALT_UART_FCR_DMAM register field. */
1076 #define ALT_UART_FCR_DMAM_WIDTH 1
1077 /* The mask used to set the ALT_UART_FCR_DMAM register field value. */
1078 #define ALT_UART_FCR_DMAM_SET_MSK 0x00000008
1079 /* The mask used to clear the ALT_UART_FCR_DMAM register field value. */
1080 #define ALT_UART_FCR_DMAM_CLR_MSK 0xfffffff7
1081 /* The reset value of the ALT_UART_FCR_DMAM register field. */
1082 #define ALT_UART_FCR_DMAM_RESET 0x0
1083 /* Extracts the ALT_UART_FCR_DMAM field value from a register. */
1084 #define ALT_UART_FCR_DMAM_GET(value) (((value) & 0x00000008) >> 3)
1085 /* Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register. */
1086 #define ALT_UART_FCR_DMAM_SET(value) (((value) << 3) & 0x00000008)
1087 
1088 /*
1089  * Field : tet
1090  *
1091  * Bits[5:4], TX Empty Trigger (or TET):
1092  *
1093  * Writes will have no effect when THRE_MODE_USER == Disabled. This is used to
1094  * select
1095  *
1096  * the empty threshold level at which the THRE Interrupts will be generated when
1097  * the
1098  *
1099  * mode is active. It also determines when the dma_tx_req_n signal will be asserted
1100  * when
1101  *
1102  * in certain modes of operation. See section 5.9 on page 56 for details on DMA
1103  * support.
1104  *
1105  * The following trigger levels are supported:
1106  *
1107  * 00 = FIFO empty
1108  *
1109  * 01 = 2 characters in the FIFO
1110  *
1111  * 10 = FIFO 1/4 full
1112  *
1113  * 11 = FIFO full
1114  *
1115  * Field Enumeration Values:
1116  *
1117  * Enum | Value | Description
1118  * :-------------------------------------|:------|:---------------------
1119  * ALT_UART_FCR_TET_E_FIFO_EMPTY | 0x0 | FIFO empty
1120  * ALT_UART_FCR_TET_E_FIFO_CHAR_2 | 0x1 | 2 characters in FIFO
1121  * ALT_UART_FCR_TET_E_FIFO_QUARTER_FULL | 0x2 | FIFO 1/4 full
1122  * ALT_UART_FCR_TET_E_FIFO_HALF_FULL | 0x3 | FIFO 1/2 full
1123  *
1124  * Field Access Macros:
1125  *
1126  */
1127 /*
1128  * Enumerated value for register field ALT_UART_FCR_TET
1129  *
1130  * FIFO empty
1131  */
1132 #define ALT_UART_FCR_TET_E_FIFO_EMPTY 0x0
1133 /*
1134  * Enumerated value for register field ALT_UART_FCR_TET
1135  *
1136  * 2 characters in FIFO
1137  */
1138 #define ALT_UART_FCR_TET_E_FIFO_CHAR_2 0x1
1139 /*
1140  * Enumerated value for register field ALT_UART_FCR_TET
1141  *
1142  * FIFO 1/4 full
1143  */
1144 #define ALT_UART_FCR_TET_E_FIFO_QUARTER_FULL 0x2
1145 /*
1146  * Enumerated value for register field ALT_UART_FCR_TET
1147  *
1148  * FIFO 1/2 full
1149  */
1150 #define ALT_UART_FCR_TET_E_FIFO_HALF_FULL 0x3
1151 
1152 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field. */
1153 #define ALT_UART_FCR_TET_LSB 4
1154 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field. */
1155 #define ALT_UART_FCR_TET_MSB 5
1156 /* The width in bits of the ALT_UART_FCR_TET register field. */
1157 #define ALT_UART_FCR_TET_WIDTH 2
1158 /* The mask used to set the ALT_UART_FCR_TET register field value. */
1159 #define ALT_UART_FCR_TET_SET_MSK 0x00000030
1160 /* The mask used to clear the ALT_UART_FCR_TET register field value. */
1161 #define ALT_UART_FCR_TET_CLR_MSK 0xffffffcf
1162 /* The reset value of the ALT_UART_FCR_TET register field. */
1163 #define ALT_UART_FCR_TET_RESET 0x0
1164 /* Extracts the ALT_UART_FCR_TET field value from a register. */
1165 #define ALT_UART_FCR_TET_GET(value) (((value) & 0x00000030) >> 4)
1166 /* Produces a ALT_UART_FCR_TET register field value suitable for setting the register. */
1167 #define ALT_UART_FCR_TET_SET(value) (((value) << 4) & 0x00000030)
1168 
1169 /*
1170  * Field : rt
1171  *
1172  * Bits[7:6], RCVR Trigger (or RT):.
1173  *
1174  * This is used to select the trigger level in the receiver FIFO at which the
1175  *
1176  * Received Data Available Interrupt will be generated. In auto flow control mode
1177  *
1178  * it is used to determine when the rts_n signal will be de-asserted. It also
1179  *
1180  * determines when the dma_rx_req_n signal will be asserted when in certain modes
1181  *
1182  * of operation. See section 5.9 on page 56 for details on DMA support. The
1183  *
1184  * following trigger levels are supported:
1185  *
1186  * 00 = 1 character in the FIFO
1187  *
1188  * 01 = FIFO 1/4 full
1189  *
1190  * 10 = FIFO 1/2 full
1191  *
1192  * 11 = FIFO 2 less than full
1193  *
1194  * Field Enumeration Values:
1195  *
1196  * Enum | Value | Description
1197  * :------------------------------------|:------|:----------------------
1198  * ALT_UART_FCR_RT_E_FIFO_CHAR_1 | 0x0 | 1 character in FIFO
1199  * ALT_UART_FCR_RT_E_FIFO_QUARTER_FULL | 0x1 | FIFO 1/4 full
1200  * ALT_UART_FCR_RT_E_FIFO_HALF_FULL | 0x2 | FIFO 1/2 full
1201  * ALT_UART_FCR_RT_E_FIFO_FULL_2 | 0x3 | FIFO 2 less than full
1202  *
1203  * Field Access Macros:
1204  *
1205  */
1206 /*
1207  * Enumerated value for register field ALT_UART_FCR_RT
1208  *
1209  * 1 character in FIFO
1210  */
1211 #define ALT_UART_FCR_RT_E_FIFO_CHAR_1 0x0
1212 /*
1213  * Enumerated value for register field ALT_UART_FCR_RT
1214  *
1215  * FIFO 1/4 full
1216  */
1217 #define ALT_UART_FCR_RT_E_FIFO_QUARTER_FULL 0x1
1218 /*
1219  * Enumerated value for register field ALT_UART_FCR_RT
1220  *
1221  * FIFO 1/2 full
1222  */
1223 #define ALT_UART_FCR_RT_E_FIFO_HALF_FULL 0x2
1224 /*
1225  * Enumerated value for register field ALT_UART_FCR_RT
1226  *
1227  * FIFO 2 less than full
1228  */
1229 #define ALT_UART_FCR_RT_E_FIFO_FULL_2 0x3
1230 
1231 /* The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field. */
1232 #define ALT_UART_FCR_RT_LSB 6
1233 /* The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field. */
1234 #define ALT_UART_FCR_RT_MSB 7
1235 /* The width in bits of the ALT_UART_FCR_RT register field. */
1236 #define ALT_UART_FCR_RT_WIDTH 2
1237 /* The mask used to set the ALT_UART_FCR_RT register field value. */
1238 #define ALT_UART_FCR_RT_SET_MSK 0x000000c0
1239 /* The mask used to clear the ALT_UART_FCR_RT register field value. */
1240 #define ALT_UART_FCR_RT_CLR_MSK 0xffffff3f
1241 /* The reset value of the ALT_UART_FCR_RT register field. */
1242 #define ALT_UART_FCR_RT_RESET 0x0
1243 /* Extracts the ALT_UART_FCR_RT field value from a register. */
1244 #define ALT_UART_FCR_RT_GET(value) (((value) & 0x000000c0) >> 6)
1245 /* Produces a ALT_UART_FCR_RT register field value suitable for setting the register. */
1246 #define ALT_UART_FCR_RT_SET(value) (((value) << 6) & 0x000000c0)
1247 
1248 #ifndef __ASSEMBLY__
1249 /*
1250  * WARNING: The C register and register group struct declarations are provided for
1251  * convenience and illustrative purposes. They should, however, be used with
1252  * caution as the C language standard provides no guarantees about the alignment or
1253  * atomicity of device memory accesses. The recommended practice for writing
1254  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1255  * alt_write_word() functions.
1256  *
1257  * The struct declaration for register ALT_UART_FCR.
1258  */
1259 struct ALT_UART_FCR_s
1260 {
1261  uint32_t fifoe : 1; /* ALT_UART_FCR_FIFOE */
1262  uint32_t rfifor : 1; /* ALT_UART_FCR_RFIFOR */
1263  uint32_t xfifor : 1; /* ALT_UART_FCR_XFIFOR */
1264  uint32_t dmam : 1; /* ALT_UART_FCR_DMAM */
1265  uint32_t tet : 2; /* ALT_UART_FCR_TET */
1266  uint32_t rt : 2; /* ALT_UART_FCR_RT */
1267  uint32_t : 24; /* *UNDEFINED* */
1268 };
1269 
1270 /* The typedef declaration for register ALT_UART_FCR. */
1271 typedef volatile struct ALT_UART_FCR_s ALT_UART_FCR_t;
1272 #endif /* __ASSEMBLY__ */
1273 
1274 /* The reset value of the ALT_UART_FCR register. */
1275 #define ALT_UART_FCR_RESET 0x00000000
1276 /* The byte offset of the ALT_UART_FCR register from the beginning of the component. */
1277 #define ALT_UART_FCR_OFST 0x8
1278 /* The address of the ALT_UART_FCR register. */
1279 #define ALT_UART_FCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))
1280 
1281 /*
1282  * Register : lcr
1283  *
1284  * Line Control Register
1285  *
1286  * Register Layout
1287  *
1288  * Bits | Access | Reset | Description
1289  * :-------|:-------|:------|:----------------------------
1290  * [1:0] | RW | 0x0 | ALT_UART_LCR_DLS
1291  * [2] | RW | 0x0 | ALT_UART_LCR_STOP
1292  * [3] | RW | 0x0 | ALT_UART_LCR_PEN
1293  * [4] | RW | 0x0 | ALT_UART_LCR_EPS
1294  * [5] | RW | 0x0 | ALT_UART_LCR_SP
1295  * [6] | RW | 0x0 | ALT_UART_LCR_BREAK
1296  * [7] | RW | 0x0 | ALT_UART_LCR_DLAB
1297  * [31:8] | R | 0x0 | ALT_UART_LCR_RSVD_LCR_31TO8
1298  *
1299  */
1300 /*
1301  * Field : dls
1302  *
1303  * Data Length Select.
1304  *
1305  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1306  * (USR[0]
1307  *
1308  * is zero), otherwise always writable, always readable. This is used to select the
1309  *
1310  * number of data bits per character that the peripheral will transmit and receive.
1311  *
1312  * The number of bit that may be selected areas follows:
1313  *
1314  * 00 = 5 bits
1315  *
1316  * 01 = 6 bits
1317  *
1318  * 10 = 7 bits
1319  *
1320  * 11 = 8 bits
1321  *
1322  * Field Enumeration Values:
1323  *
1324  * Enum | Value | Description
1325  * :------------------------|:------|:------------
1326  * ALT_UART_LCR_DLS_E_LEN5 | 0x0 | 5 bits
1327  * ALT_UART_LCR_DLS_E_LEN6 | 0x1 | 6 bits
1328  * ALT_UART_LCR_DLS_E_LEN7 | 0x2 | 7 bits
1329  * ALT_UART_LCR_DLS_E_LEN8 | 0x3 | 8 bits
1330  *
1331  * Field Access Macros:
1332  *
1333  */
1334 /*
1335  * Enumerated value for register field ALT_UART_LCR_DLS
1336  *
1337  * 5 bits
1338  */
1339 #define ALT_UART_LCR_DLS_E_LEN5 0x0
1340 /*
1341  * Enumerated value for register field ALT_UART_LCR_DLS
1342  *
1343  * 6 bits
1344  */
1345 #define ALT_UART_LCR_DLS_E_LEN6 0x1
1346 /*
1347  * Enumerated value for register field ALT_UART_LCR_DLS
1348  *
1349  * 7 bits
1350  */
1351 #define ALT_UART_LCR_DLS_E_LEN7 0x2
1352 /*
1353  * Enumerated value for register field ALT_UART_LCR_DLS
1354  *
1355  * 8 bits
1356  */
1357 #define ALT_UART_LCR_DLS_E_LEN8 0x3
1358 
1359 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLS register field. */
1360 #define ALT_UART_LCR_DLS_LSB 0
1361 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLS register field. */
1362 #define ALT_UART_LCR_DLS_MSB 1
1363 /* The width in bits of the ALT_UART_LCR_DLS register field. */
1364 #define ALT_UART_LCR_DLS_WIDTH 2
1365 /* The mask used to set the ALT_UART_LCR_DLS register field value. */
1366 #define ALT_UART_LCR_DLS_SET_MSK 0x00000003
1367 /* The mask used to clear the ALT_UART_LCR_DLS register field value. */
1368 #define ALT_UART_LCR_DLS_CLR_MSK 0xfffffffc
1369 /* The reset value of the ALT_UART_LCR_DLS register field. */
1370 #define ALT_UART_LCR_DLS_RESET 0x0
1371 /* Extracts the ALT_UART_LCR_DLS field value from a register. */
1372 #define ALT_UART_LCR_DLS_GET(value) (((value) & 0x00000003) >> 0)
1373 /* Produces a ALT_UART_LCR_DLS register field value suitable for setting the register. */
1374 #define ALT_UART_LCR_DLS_SET(value) (((value) << 0) & 0x00000003)
1375 
1376 /*
1377  * Field : stop
1378  *
1379  * Number of stop bits.
1380  *
1381  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1382  * (USR[0]
1383  *
1384  * is zero), otherwise always writable, always readable. This is used to select the
1385  * number
1386  *
1387  * of stop bits per character that the peripheral will transmit and receive. If set
1388  * to
1389  *
1390  * zero, one stop bit is transmitted in the serial data. If set to one and the data
1391  *
1392  * bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is
1393  * transmitted.
1394  *
1395  * Otherwise, two stop bits are transmitted.
1396  *
1397  * Note that regardless of the number of stop bits selected the receiver will only
1398  *
1399  * check the first stop bit.
1400  *
1401  * 0 = 1 stop bit
1402  *
1403  * 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero,
1404  *
1405  * else 2 stop bit
1406  *
1407  * Field Enumeration Values:
1408  *
1409  * Enum | Value | Description
1410  * :----------------------------------|:------|:------------------------------------------
1411  * ALT_UART_LCR_STOP_E_ONESTOP | 0x0 | one stop bit
1412  * ALT_UART_LCR_STOP_E_ONEPOINT5STOP | 0x1 | 1.5 stop bits when DLS (LCR[1:0]) is zero
1413  *
1414  * Field Access Macros:
1415  *
1416  */
1417 /*
1418  * Enumerated value for register field ALT_UART_LCR_STOP
1419  *
1420  * one stop bit
1421  */
1422 #define ALT_UART_LCR_STOP_E_ONESTOP 0x0
1423 /*
1424  * Enumerated value for register field ALT_UART_LCR_STOP
1425  *
1426  * 1.5 stop bits when DLS (LCR[1:0]) is zero
1427  */
1428 #define ALT_UART_LCR_STOP_E_ONEPOINT5STOP 0x1
1429 
1430 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_STOP register field. */
1431 #define ALT_UART_LCR_STOP_LSB 2
1432 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_STOP register field. */
1433 #define ALT_UART_LCR_STOP_MSB 2
1434 /* The width in bits of the ALT_UART_LCR_STOP register field. */
1435 #define ALT_UART_LCR_STOP_WIDTH 1
1436 /* The mask used to set the ALT_UART_LCR_STOP register field value. */
1437 #define ALT_UART_LCR_STOP_SET_MSK 0x00000004
1438 /* The mask used to clear the ALT_UART_LCR_STOP register field value. */
1439 #define ALT_UART_LCR_STOP_CLR_MSK 0xfffffffb
1440 /* The reset value of the ALT_UART_LCR_STOP register field. */
1441 #define ALT_UART_LCR_STOP_RESET 0x0
1442 /* Extracts the ALT_UART_LCR_STOP field value from a register. */
1443 #define ALT_UART_LCR_STOP_GET(value) (((value) & 0x00000004) >> 2)
1444 /* Produces a ALT_UART_LCR_STOP register field value suitable for setting the register. */
1445 #define ALT_UART_LCR_STOP_SET(value) (((value) << 2) & 0x00000004)
1446 
1447 /*
1448  * Field : pen
1449  *
1450  * Parity Enable.
1451  *
1452  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1453  * (USR[0]
1454  *
1455  * is zero), otherwise always writable, always readable. This bit is used to enable
1456  *
1457  * and disable parity generation and detection in transmitted and received serial
1458  *
1459  * character respectively.
1460  *
1461  * 0 = parity disabled
1462  *
1463  * 1 = parity enabled
1464  *
1465  * Field Enumeration Values:
1466  *
1467  * Enum | Value | Description
1468  * :------------------------|:------|:----------------
1469  * ALT_UART_LCR_PEN_E_DISD | 0x0 | parity disabled
1470  * ALT_UART_LCR_PEN_E_END | 0x1 | parity enabled
1471  *
1472  * Field Access Macros:
1473  *
1474  */
1475 /*
1476  * Enumerated value for register field ALT_UART_LCR_PEN
1477  *
1478  * parity disabled
1479  */
1480 #define ALT_UART_LCR_PEN_E_DISD 0x0
1481 /*
1482  * Enumerated value for register field ALT_UART_LCR_PEN
1483  *
1484  * parity enabled
1485  */
1486 #define ALT_UART_LCR_PEN_E_END 0x1
1487 
1488 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_PEN register field. */
1489 #define ALT_UART_LCR_PEN_LSB 3
1490 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_PEN register field. */
1491 #define ALT_UART_LCR_PEN_MSB 3
1492 /* The width in bits of the ALT_UART_LCR_PEN register field. */
1493 #define ALT_UART_LCR_PEN_WIDTH 1
1494 /* The mask used to set the ALT_UART_LCR_PEN register field value. */
1495 #define ALT_UART_LCR_PEN_SET_MSK 0x00000008
1496 /* The mask used to clear the ALT_UART_LCR_PEN register field value. */
1497 #define ALT_UART_LCR_PEN_CLR_MSK 0xfffffff7
1498 /* The reset value of the ALT_UART_LCR_PEN register field. */
1499 #define ALT_UART_LCR_PEN_RESET 0x0
1500 /* Extracts the ALT_UART_LCR_PEN field value from a register. */
1501 #define ALT_UART_LCR_PEN_GET(value) (((value) & 0x00000008) >> 3)
1502 /* Produces a ALT_UART_LCR_PEN register field value suitable for setting the register. */
1503 #define ALT_UART_LCR_PEN_SET(value) (((value) << 3) & 0x00000008)
1504 
1505 /*
1506  * Field : eps
1507  *
1508  * Even Parity Select.
1509  *
1510  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1511  * (USR[0]
1512  *
1513  * is zero), otherwise always writable, always readable. This is used to select
1514  *
1515  * between even and odd parity, when parity is enabled (PEN set to one). If set to
1516  *
1517  * one, an even number of logic '1's is transmitted or checked. If set to zero, an
1518  *
1519  * odd number of logic '1's is transmitted or checked.
1520  *
1521  * Field Enumeration Values:
1522  *
1523  * Enum | Value | Description
1524  * :---------------------------|:------|:------------
1525  * ALT_UART_LCR_EPS_E_ODDPAR | 0x0 | odd parity
1526  * ALT_UART_LCR_EPS_E_EVENPAR | 0x1 | even parity
1527  *
1528  * Field Access Macros:
1529  *
1530  */
1531 /*
1532  * Enumerated value for register field ALT_UART_LCR_EPS
1533  *
1534  * odd parity
1535  */
1536 #define ALT_UART_LCR_EPS_E_ODDPAR 0x0
1537 /*
1538  * Enumerated value for register field ALT_UART_LCR_EPS
1539  *
1540  * even parity
1541  */
1542 #define ALT_UART_LCR_EPS_E_EVENPAR 0x1
1543 
1544 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_EPS register field. */
1545 #define ALT_UART_LCR_EPS_LSB 4
1546 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_EPS register field. */
1547 #define ALT_UART_LCR_EPS_MSB 4
1548 /* The width in bits of the ALT_UART_LCR_EPS register field. */
1549 #define ALT_UART_LCR_EPS_WIDTH 1
1550 /* The mask used to set the ALT_UART_LCR_EPS register field value. */
1551 #define ALT_UART_LCR_EPS_SET_MSK 0x00000010
1552 /* The mask used to clear the ALT_UART_LCR_EPS register field value. */
1553 #define ALT_UART_LCR_EPS_CLR_MSK 0xffffffef
1554 /* The reset value of the ALT_UART_LCR_EPS register field. */
1555 #define ALT_UART_LCR_EPS_RESET 0x0
1556 /* Extracts the ALT_UART_LCR_EPS field value from a register. */
1557 #define ALT_UART_LCR_EPS_GET(value) (((value) & 0x00000010) >> 4)
1558 /* Produces a ALT_UART_LCR_EPS register field value suitable for setting the register. */
1559 #define ALT_UART_LCR_EPS_SET(value) (((value) << 4) & 0x00000010)
1560 
1561 /*
1562  * Field : sp
1563  *
1564  * From DW_apb_uart_regfile.sv:
1565  *
1566  * // aaraujo @ 17/05/2011 : CRM_9000431453
1567  *
1568  * // Stick parity lcr_ir[5] is now programmable
1569  *
1570  * lcr_ir[5:0] <= ipwdata[5:0];
1571  *
1572  * Field Enumeration Values:
1573  *
1574  * Enum | Value | Description
1575  * :-----------------------|:------|:----------------------
1576  * ALT_UART_LCR_SP_E_DISD | 0x0 | Stick Parity Disabled
1577  * ALT_UART_LCR_SP_E_END | 0x1 | Stick Parity Enabled
1578  *
1579  * Field Access Macros:
1580  *
1581  */
1582 /*
1583  * Enumerated value for register field ALT_UART_LCR_SP
1584  *
1585  * Stick Parity Disabled
1586  */
1587 #define ALT_UART_LCR_SP_E_DISD 0x0
1588 /*
1589  * Enumerated value for register field ALT_UART_LCR_SP
1590  *
1591  * Stick Parity Enabled
1592  */
1593 #define ALT_UART_LCR_SP_E_END 0x1
1594 
1595 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_SP register field. */
1596 #define ALT_UART_LCR_SP_LSB 5
1597 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_SP register field. */
1598 #define ALT_UART_LCR_SP_MSB 5
1599 /* The width in bits of the ALT_UART_LCR_SP register field. */
1600 #define ALT_UART_LCR_SP_WIDTH 1
1601 /* The mask used to set the ALT_UART_LCR_SP register field value. */
1602 #define ALT_UART_LCR_SP_SET_MSK 0x00000020
1603 /* The mask used to clear the ALT_UART_LCR_SP register field value. */
1604 #define ALT_UART_LCR_SP_CLR_MSK 0xffffffdf
1605 /* The reset value of the ALT_UART_LCR_SP register field. */
1606 #define ALT_UART_LCR_SP_RESET 0x0
1607 /* Extracts the ALT_UART_LCR_SP field value from a register. */
1608 #define ALT_UART_LCR_SP_GET(value) (((value) & 0x00000020) >> 5)
1609 /* Produces a ALT_UART_LCR_SP register field value suitable for setting the register. */
1610 #define ALT_UART_LCR_SP_SET(value) (((value) << 5) & 0x00000020)
1611 
1612 /*
1613  * Field : break
1614  *
1615  * Break Control Bit.
1616  *
1617  * This is used to cause a break condition to be transmitted to the receiving
1618  * device.
1619  *
1620  * If set to one the serial output is forced to the spacing (logic 0) state. When
1621  *
1622  * not in Loopback Mode, as determined by MCR[4], the sout line is forced low until
1623  *
1624  * the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one)
1625  *
1626  * the sir_out_n line is continuously pulsed. When in Loopback Mode, the break
1627  *
1628  * condition is internally looped back to the receiver and the sir_out_n line is
1629  *
1630  * forced low.
1631  *
1632  * Field Access Macros:
1633  *
1634  */
1635 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_BREAK register field. */
1636 #define ALT_UART_LCR_BREAK_LSB 6
1637 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_BREAK register field. */
1638 #define ALT_UART_LCR_BREAK_MSB 6
1639 /* The width in bits of the ALT_UART_LCR_BREAK register field. */
1640 #define ALT_UART_LCR_BREAK_WIDTH 1
1641 /* The mask used to set the ALT_UART_LCR_BREAK register field value. */
1642 #define ALT_UART_LCR_BREAK_SET_MSK 0x00000040
1643 /* The mask used to clear the ALT_UART_LCR_BREAK register field value. */
1644 #define ALT_UART_LCR_BREAK_CLR_MSK 0xffffffbf
1645 /* The reset value of the ALT_UART_LCR_BREAK register field. */
1646 #define ALT_UART_LCR_BREAK_RESET 0x0
1647 /* Extracts the ALT_UART_LCR_BREAK field value from a register. */
1648 #define ALT_UART_LCR_BREAK_GET(value) (((value) & 0x00000040) >> 6)
1649 /* Produces a ALT_UART_LCR_BREAK register field value suitable for setting the register. */
1650 #define ALT_UART_LCR_BREAK_SET(value) (((value) << 6) & 0x00000040)
1651 
1652 /*
1653  * Field : dlab
1654  *
1655  * Divisor Latch Access Bit.
1656  *
1657  * If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy
1658  * (USR[0]
1659  *
1660  * is zero), otherwise always writable, always readable. This bit is used to enable
1661  *
1662  * reading and writing of the Divisor Latch register (DLL and DLH) to set the baud
1663  *
1664  * rate of the UART. This bit must be cleared after initial baud rate setup in
1665  * order
1666  *
1667  * to access other registers.
1668  *
1669  * Field Access Macros:
1670  *
1671  */
1672 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_DLAB register field. */
1673 #define ALT_UART_LCR_DLAB_LSB 7
1674 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_DLAB register field. */
1675 #define ALT_UART_LCR_DLAB_MSB 7
1676 /* The width in bits of the ALT_UART_LCR_DLAB register field. */
1677 #define ALT_UART_LCR_DLAB_WIDTH 1
1678 /* The mask used to set the ALT_UART_LCR_DLAB register field value. */
1679 #define ALT_UART_LCR_DLAB_SET_MSK 0x00000080
1680 /* The mask used to clear the ALT_UART_LCR_DLAB register field value. */
1681 #define ALT_UART_LCR_DLAB_CLR_MSK 0xffffff7f
1682 /* The reset value of the ALT_UART_LCR_DLAB register field. */
1683 #define ALT_UART_LCR_DLAB_RESET 0x0
1684 /* Extracts the ALT_UART_LCR_DLAB field value from a register. */
1685 #define ALT_UART_LCR_DLAB_GET(value) (((value) & 0x00000080) >> 7)
1686 /* Produces a ALT_UART_LCR_DLAB register field value suitable for setting the register. */
1687 #define ALT_UART_LCR_DLAB_SET(value) (((value) << 7) & 0x00000080)
1688 
1689 /*
1690  * Field : rsvd_lcr_31to8
1691  *
1692  * Reserved bits [31:8] - Read Only
1693  *
1694  * Field Access Macros:
1695  *
1696  */
1697 /* The Least Significant Bit (LSB) position of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1698 #define ALT_UART_LCR_RSVD_LCR_31TO8_LSB 8
1699 /* The Most Significant Bit (MSB) position of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1700 #define ALT_UART_LCR_RSVD_LCR_31TO8_MSB 31
1701 /* The width in bits of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1702 #define ALT_UART_LCR_RSVD_LCR_31TO8_WIDTH 24
1703 /* The mask used to set the ALT_UART_LCR_RSVD_LCR_31TO8 register field value. */
1704 #define ALT_UART_LCR_RSVD_LCR_31TO8_SET_MSK 0xffffff00
1705 /* The mask used to clear the ALT_UART_LCR_RSVD_LCR_31TO8 register field value. */
1706 #define ALT_UART_LCR_RSVD_LCR_31TO8_CLR_MSK 0x000000ff
1707 /* The reset value of the ALT_UART_LCR_RSVD_LCR_31TO8 register field. */
1708 #define ALT_UART_LCR_RSVD_LCR_31TO8_RESET 0x0
1709 /* Extracts the ALT_UART_LCR_RSVD_LCR_31TO8 field value from a register. */
1710 #define ALT_UART_LCR_RSVD_LCR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
1711 /* Produces a ALT_UART_LCR_RSVD_LCR_31TO8 register field value suitable for setting the register. */
1712 #define ALT_UART_LCR_RSVD_LCR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
1713 
1714 #ifndef __ASSEMBLY__
1715 /*
1716  * WARNING: The C register and register group struct declarations are provided for
1717  * convenience and illustrative purposes. They should, however, be used with
1718  * caution as the C language standard provides no guarantees about the alignment or
1719  * atomicity of device memory accesses. The recommended practice for writing
1720  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1721  * alt_write_word() functions.
1722  *
1723  * The struct declaration for register ALT_UART_LCR.
1724  */
1725 struct ALT_UART_LCR_s
1726 {
1727  uint32_t dls : 2; /* ALT_UART_LCR_DLS */
1728  uint32_t stop : 1; /* ALT_UART_LCR_STOP */
1729  uint32_t pen : 1; /* ALT_UART_LCR_PEN */
1730  uint32_t eps : 1; /* ALT_UART_LCR_EPS */
1731  uint32_t sp : 1; /* ALT_UART_LCR_SP */
1732  uint32_t break_ : 1; /* ALT_UART_LCR_BREAK */
1733  uint32_t dlab : 1; /* ALT_UART_LCR_DLAB */
1734  const uint32_t rsvd_lcr_31to8 : 24; /* ALT_UART_LCR_RSVD_LCR_31TO8 */
1735 };
1736 
1737 /* The typedef declaration for register ALT_UART_LCR. */
1738 typedef volatile struct ALT_UART_LCR_s ALT_UART_LCR_t;
1739 #endif /* __ASSEMBLY__ */
1740 
1741 /* The reset value of the ALT_UART_LCR register. */
1742 #define ALT_UART_LCR_RESET 0x00000000
1743 /* The byte offset of the ALT_UART_LCR register from the beginning of the component. */
1744 #define ALT_UART_LCR_OFST 0xc
1745 /* The address of the ALT_UART_LCR register. */
1746 #define ALT_UART_LCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LCR_OFST))
1747 
1748 /*
1749  * Register : mcr
1750  *
1751  * Modem Control Register
1752  *
1753  * Register Layout
1754  *
1755  * Bits | Access | Reset | Description
1756  * :-------|:-------|:------|:----------------------------
1757  * [0] | RW | 0x0 | ALT_UART_MCR_DTR
1758  * [1] | RW | 0x0 | ALT_UART_MCR_RTS
1759  * [2] | RW | 0x0 | ALT_UART_MCR_OUT1
1760  * [3] | RW | 0x0 | ALT_UART_MCR_OUT2
1761  * [4] | RW | 0x0 | ALT_UART_MCR_LOOPBACK
1762  * [5] | RW | 0x0 | ALT_UART_MCR_AFCE
1763  * [6] | R | 0x0 | ALT_UART_MCR_SIRE
1764  * [31:7] | R | 0x0 | ALT_UART_MCR_RSVD_MCR_31TO7
1765  *
1766  */
1767 /*
1768  * Field : dtr
1769  *
1770  * Data Terminal Ready.
1771  *
1772  * This is used to directly control the Data Terminal Ready (dtr_n) output. The
1773  * value
1774  *
1775  * written to this location is inverted and driven out on dtr_n, that is:
1776  *
1777  * 0 = dtr_n de-asserted (logic 1)
1778  *
1779  * 1 = dtr_n asserted (logic 0)
1780  *
1781  * The Data Terminal Ready output is used to inform the modem or data set that the
1782  *
1783  * UART is ready to establish communications. Note that in Loopback mode (MCR[4]
1784  *
1785  * set to one), the dtr_n output is held inactive high while the value of this
1786  *
1787  * location is internally looped back to an input.
1788  *
1789  * Field Enumeration Values:
1790  *
1791  * Enum | Value | Description
1792  * :--------------------------|:------|:---------------------------------
1793  * ALT_UART_MCR_DTR_E_LOGIC1 | 0x0 | uart_dtr_n de-asserted (logic 1)
1794  * ALT_UART_MCR_DTR_E_LOGIC0 | 0x1 | uart_dtr_n asserted (logic 0)
1795  *
1796  * Field Access Macros:
1797  *
1798  */
1799 /*
1800  * Enumerated value for register field ALT_UART_MCR_DTR
1801  *
1802  * uart_dtr_n de-asserted (logic 1)
1803  */
1804 #define ALT_UART_MCR_DTR_E_LOGIC1 0x0
1805 /*
1806  * Enumerated value for register field ALT_UART_MCR_DTR
1807  *
1808  * uart_dtr_n asserted (logic 0)
1809  */
1810 #define ALT_UART_MCR_DTR_E_LOGIC0 0x1
1811 
1812 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field. */
1813 #define ALT_UART_MCR_DTR_LSB 0
1814 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field. */
1815 #define ALT_UART_MCR_DTR_MSB 0
1816 /* The width in bits of the ALT_UART_MCR_DTR register field. */
1817 #define ALT_UART_MCR_DTR_WIDTH 1
1818 /* The mask used to set the ALT_UART_MCR_DTR register field value. */
1819 #define ALT_UART_MCR_DTR_SET_MSK 0x00000001
1820 /* The mask used to clear the ALT_UART_MCR_DTR register field value. */
1821 #define ALT_UART_MCR_DTR_CLR_MSK 0xfffffffe
1822 /* The reset value of the ALT_UART_MCR_DTR register field. */
1823 #define ALT_UART_MCR_DTR_RESET 0x0
1824 /* Extracts the ALT_UART_MCR_DTR field value from a register. */
1825 #define ALT_UART_MCR_DTR_GET(value) (((value) & 0x00000001) >> 0)
1826 /* Produces a ALT_UART_MCR_DTR register field value suitable for setting the register. */
1827 #define ALT_UART_MCR_DTR_SET(value) (((value) << 0) & 0x00000001)
1828 
1829 /*
1830  * Field : rts
1831  *
1832  * Request to Send.
1833  *
1834  * This is used to directly control the Request to Send (rts_n) output. The Request
1835  *
1836  * To Send (rts_n) output is used to inform the modem or data set that the UART is
1837  *
1838  * ready to exchange data.
1839  *
1840  * When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal
1841  *
1842  * is set low by programming MCR[1] (RTS) to a high.
1843  *
1844  * In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and
1845  *
1846  * FIFO's enable (FCR[0] set to one), the rts_n output is controlled in the same
1847  * way,
1848  *
1849  * but is also gated with the receiver FIFO threshold trigger (rts_n is inactive
1850  * high
1851  *
1852  * when above the threshold).
1853  *
1854  * The rts_n signal will be de-asserted when MCR[1] is set low.
1855  *
1856  * Note that in Loopback mode (MCR[4] set to one), the rts_n output is held
1857  * inactive
1858  *
1859  * high while the value of this location is internally looped back to an input.
1860  *
1861  * Field Enumeration Values:
1862  *
1863  * Enum | Value | Description
1864  * :--------------------------|:------|:---------------------------------
1865  * ALT_UART_MCR_RTS_E_LOGIC1 | 0x0 | uart_rts_n de-asserted (logic 1)
1866  * ALT_UART_MCR_RTS_E_LOGIC0 | 0x1 | uart_rts_n asserted (logic 0)
1867  *
1868  * Field Access Macros:
1869  *
1870  */
1871 /*
1872  * Enumerated value for register field ALT_UART_MCR_RTS
1873  *
1874  * uart_rts_n de-asserted (logic 1)
1875  */
1876 #define ALT_UART_MCR_RTS_E_LOGIC1 0x0
1877 /*
1878  * Enumerated value for register field ALT_UART_MCR_RTS
1879  *
1880  * uart_rts_n asserted (logic 0)
1881  */
1882 #define ALT_UART_MCR_RTS_E_LOGIC0 0x1
1883 
1884 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field. */
1885 #define ALT_UART_MCR_RTS_LSB 1
1886 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field. */
1887 #define ALT_UART_MCR_RTS_MSB 1
1888 /* The width in bits of the ALT_UART_MCR_RTS register field. */
1889 #define ALT_UART_MCR_RTS_WIDTH 1
1890 /* The mask used to set the ALT_UART_MCR_RTS register field value. */
1891 #define ALT_UART_MCR_RTS_SET_MSK 0x00000002
1892 /* The mask used to clear the ALT_UART_MCR_RTS register field value. */
1893 #define ALT_UART_MCR_RTS_CLR_MSK 0xfffffffd
1894 /* The reset value of the ALT_UART_MCR_RTS register field. */
1895 #define ALT_UART_MCR_RTS_RESET 0x0
1896 /* Extracts the ALT_UART_MCR_RTS field value from a register. */
1897 #define ALT_UART_MCR_RTS_GET(value) (((value) & 0x00000002) >> 1)
1898 /* Produces a ALT_UART_MCR_RTS register field value suitable for setting the register. */
1899 #define ALT_UART_MCR_RTS_SET(value) (((value) << 1) & 0x00000002)
1900 
1901 /*
1902  * Field : out1
1903  *
1904  * OUT1.
1905  *
1906  * This is used to directly control the user-designated Output1 (out1_n) output.
1907  * The
1908  *
1909  * value written to this location is inverted and driven out on out1_n, that is:
1910  *
1911  * 0 = out1_n de-asserted (logic 1)
1912  *
1913  * 1 = out1_n asserted (logic 0)
1914  *
1915  * Note that in Loopback mode (MCR[4] set to one), the out1_n output is held
1916  * inactive high
1917  *
1918  * while the value of this location is internally looped back to an input.
1919  *
1920  * Field Enumeration Values:
1921  *
1922  * Enum | Value | Description
1923  * :---------------------------|:------|:----------------------------------
1924  * ALT_UART_MCR_OUT1_E_LOGIC1 | 0x0 | uart_out1_n de-asserted (logic 1)
1925  * ALT_UART_MCR_OUT1_E_LOGIC0 | 0x1 | uart_out1_n asserted (logic 0)
1926  *
1927  * Field Access Macros:
1928  *
1929  */
1930 /*
1931  * Enumerated value for register field ALT_UART_MCR_OUT1
1932  *
1933  * uart_out1_n de-asserted (logic 1)
1934  */
1935 #define ALT_UART_MCR_OUT1_E_LOGIC1 0x0
1936 /*
1937  * Enumerated value for register field ALT_UART_MCR_OUT1
1938  *
1939  * uart_out1_n asserted (logic 0)
1940  */
1941 #define ALT_UART_MCR_OUT1_E_LOGIC0 0x1
1942 
1943 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field. */
1944 #define ALT_UART_MCR_OUT1_LSB 2
1945 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field. */
1946 #define ALT_UART_MCR_OUT1_MSB 2
1947 /* The width in bits of the ALT_UART_MCR_OUT1 register field. */
1948 #define ALT_UART_MCR_OUT1_WIDTH 1
1949 /* The mask used to set the ALT_UART_MCR_OUT1 register field value. */
1950 #define ALT_UART_MCR_OUT1_SET_MSK 0x00000004
1951 /* The mask used to clear the ALT_UART_MCR_OUT1 register field value. */
1952 #define ALT_UART_MCR_OUT1_CLR_MSK 0xfffffffb
1953 /* The reset value of the ALT_UART_MCR_OUT1 register field. */
1954 #define ALT_UART_MCR_OUT1_RESET 0x0
1955 /* Extracts the ALT_UART_MCR_OUT1 field value from a register. */
1956 #define ALT_UART_MCR_OUT1_GET(value) (((value) & 0x00000004) >> 2)
1957 /* Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register. */
1958 #define ALT_UART_MCR_OUT1_SET(value) (((value) << 2) & 0x00000004)
1959 
1960 /*
1961  * Field : out2
1962  *
1963  * OUT2.
1964  *
1965  * This is used to directly control the user-designated Output2 (out2_n) output.
1966  * The
1967  *
1968  * value written to this location is inverted and driven out on out2_n, that is:
1969  *
1970  * 0 = out2_n de-asserted (logic 1)
1971  *
1972  * 1 = out2_n asserted (logic 0)
1973  *
1974  * Note that in Loopback mode (MCR[4] set to one), the out2_n output is held
1975  * inactive
1976  *
1977  * high while the value of this location is internally looped back to an input.
1978  *
1979  * Field Enumeration Values:
1980  *
1981  * Enum | Value | Description
1982  * :---------------------------|:------|:----------------------------------
1983  * ALT_UART_MCR_OUT2_E_LOGIC1 | 0x0 | uart_out2_n de-asserted (logic 1)
1984  * ALT_UART_MCR_OUT2_E_LOGIC0 | 0x1 | uart_out2_n asserted (logic 0)
1985  *
1986  * Field Access Macros:
1987  *
1988  */
1989 /*
1990  * Enumerated value for register field ALT_UART_MCR_OUT2
1991  *
1992  * uart_out2_n de-asserted (logic 1)
1993  */
1994 #define ALT_UART_MCR_OUT2_E_LOGIC1 0x0
1995 /*
1996  * Enumerated value for register field ALT_UART_MCR_OUT2
1997  *
1998  * uart_out2_n asserted (logic 0)
1999  */
2000 #define ALT_UART_MCR_OUT2_E_LOGIC0 0x1
2001 
2002 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field. */
2003 #define ALT_UART_MCR_OUT2_LSB 3
2004 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field. */
2005 #define ALT_UART_MCR_OUT2_MSB 3
2006 /* The width in bits of the ALT_UART_MCR_OUT2 register field. */
2007 #define ALT_UART_MCR_OUT2_WIDTH 1
2008 /* The mask used to set the ALT_UART_MCR_OUT2 register field value. */
2009 #define ALT_UART_MCR_OUT2_SET_MSK 0x00000008
2010 /* The mask used to clear the ALT_UART_MCR_OUT2 register field value. */
2011 #define ALT_UART_MCR_OUT2_CLR_MSK 0xfffffff7
2012 /* The reset value of the ALT_UART_MCR_OUT2 register field. */
2013 #define ALT_UART_MCR_OUT2_RESET 0x0
2014 /* Extracts the ALT_UART_MCR_OUT2 field value from a register. */
2015 #define ALT_UART_MCR_OUT2_GET(value) (((value) & 0x00000008) >> 3)
2016 /* Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register. */
2017 #define ALT_UART_MCR_OUT2_SET(value) (((value) << 3) & 0x00000008)
2018 
2019 /*
2020  * Field : loopback
2021  *
2022  * LoopBack Bit.
2023  *
2024  * This is used to put the UART into a dDW_iagnostic mode for test purposes.
2025  *
2026  * If operating in UART mode (SIR_MODE != Enabled OR NOT active, MCR[6] set to
2027  * zero),
2028  *
2029  * data on the sout line is held high, while serial data output is looped back to
2030  * the
2031  *
2032  * sin line, internally. In this mode all the interrupts are fully functional.
2033  * Also,
2034  *
2035  * in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are
2036  *
2037  * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are
2038  * looped
2039  *
2040  * back to the inputs, internally.
2041  *
2042  * If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to
2043  * one),
2044  *
2045  * data on the sir_out_n line is held low, while serial data output is inverted and
2046  *
2047  * looped back to the sir_in line.
2048  *
2049  * Field Access Macros:
2050  *
2051  */
2052 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field. */
2053 #define ALT_UART_MCR_LOOPBACK_LSB 4
2054 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field. */
2055 #define ALT_UART_MCR_LOOPBACK_MSB 4
2056 /* The width in bits of the ALT_UART_MCR_LOOPBACK register field. */
2057 #define ALT_UART_MCR_LOOPBACK_WIDTH 1
2058 /* The mask used to set the ALT_UART_MCR_LOOPBACK register field value. */
2059 #define ALT_UART_MCR_LOOPBACK_SET_MSK 0x00000010
2060 /* The mask used to clear the ALT_UART_MCR_LOOPBACK register field value. */
2061 #define ALT_UART_MCR_LOOPBACK_CLR_MSK 0xffffffef
2062 /* The reset value of the ALT_UART_MCR_LOOPBACK register field. */
2063 #define ALT_UART_MCR_LOOPBACK_RESET 0x0
2064 /* Extracts the ALT_UART_MCR_LOOPBACK field value from a register. */
2065 #define ALT_UART_MCR_LOOPBACK_GET(value) (((value) & 0x00000010) >> 4)
2066 /* Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register. */
2067 #define ALT_UART_MCR_LOOPBACK_SET(value) (((value) << 4) & 0x00000010)
2068 
2069 /*
2070  * Field : afce
2071  *
2072  * Auto Flow Control Enable.
2073  *
2074  * Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are
2075  * enabled
2076  *
2077  * and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features
2078  * are
2079  *
2080  * enabled as described in section 5.6 on page 51.
2081  *
2082  * 0 = Auto Flow Control Mode disabled
2083  *
2084  * 1 = Auto Flow Control Mode enabled
2085  *
2086  * Field Enumeration Values:
2087  *
2088  * Enum | Value | Description
2089  * :-------------------------|:------|:--------------------------------
2090  * ALT_UART_MCR_AFCE_E_DISD | 0x0 | Auto Flow Control Mode disabled
2091  * ALT_UART_MCR_AFCE_E_END | 0x1 | Auto Flow Control Mode enabled
2092  *
2093  * Field Access Macros:
2094  *
2095  */
2096 /*
2097  * Enumerated value for register field ALT_UART_MCR_AFCE
2098  *
2099  * Auto Flow Control Mode disabled
2100  */
2101 #define ALT_UART_MCR_AFCE_E_DISD 0x0
2102 /*
2103  * Enumerated value for register field ALT_UART_MCR_AFCE
2104  *
2105  * Auto Flow Control Mode enabled
2106  */
2107 #define ALT_UART_MCR_AFCE_E_END 0x1
2108 
2109 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field. */
2110 #define ALT_UART_MCR_AFCE_LSB 5
2111 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field. */
2112 #define ALT_UART_MCR_AFCE_MSB 5
2113 /* The width in bits of the ALT_UART_MCR_AFCE register field. */
2114 #define ALT_UART_MCR_AFCE_WIDTH 1
2115 /* The mask used to set the ALT_UART_MCR_AFCE register field value. */
2116 #define ALT_UART_MCR_AFCE_SET_MSK 0x00000020
2117 /* The mask used to clear the ALT_UART_MCR_AFCE register field value. */
2118 #define ALT_UART_MCR_AFCE_CLR_MSK 0xffffffdf
2119 /* The reset value of the ALT_UART_MCR_AFCE register field. */
2120 #define ALT_UART_MCR_AFCE_RESET 0x0
2121 /* Extracts the ALT_UART_MCR_AFCE field value from a register. */
2122 #define ALT_UART_MCR_AFCE_GET(value) (((value) & 0x00000020) >> 5)
2123 /* Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register. */
2124 #define ALT_UART_MCR_AFCE_SET(value) (((value) << 5) & 0x00000020)
2125 
2126 /*
2127  * Field : sire
2128  *
2129  * SIR Mode Enable.
2130  *
2131  * Writeable only when SIR_MODE == Enabled, always readable. This is used to
2132  * enable/
2133  *
2134  * disable the IrDA SIR Mode features as described in section 5.2 on page 47.
2135  *
2136  * 0 = IrDA SIR Mode disabled
2137  *
2138  * 1 = IrDA SIR Mode enabled
2139  *
2140  * Field Access Macros:
2141  *
2142  */
2143 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_SIRE register field. */
2144 #define ALT_UART_MCR_SIRE_LSB 6
2145 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_SIRE register field. */
2146 #define ALT_UART_MCR_SIRE_MSB 6
2147 /* The width in bits of the ALT_UART_MCR_SIRE register field. */
2148 #define ALT_UART_MCR_SIRE_WIDTH 1
2149 /* The mask used to set the ALT_UART_MCR_SIRE register field value. */
2150 #define ALT_UART_MCR_SIRE_SET_MSK 0x00000040
2151 /* The mask used to clear the ALT_UART_MCR_SIRE register field value. */
2152 #define ALT_UART_MCR_SIRE_CLR_MSK 0xffffffbf
2153 /* The reset value of the ALT_UART_MCR_SIRE register field. */
2154 #define ALT_UART_MCR_SIRE_RESET 0x0
2155 /* Extracts the ALT_UART_MCR_SIRE field value from a register. */
2156 #define ALT_UART_MCR_SIRE_GET(value) (((value) & 0x00000040) >> 6)
2157 /* Produces a ALT_UART_MCR_SIRE register field value suitable for setting the register. */
2158 #define ALT_UART_MCR_SIRE_SET(value) (((value) << 6) & 0x00000040)
2159 
2160 /*
2161  * Field : rsvd_mcr_31to7
2162  *
2163  * Reserved bits [31:7] - Read Only
2164  *
2165  * Field Access Macros:
2166  *
2167  */
2168 /* The Least Significant Bit (LSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
2169 #define ALT_UART_MCR_RSVD_MCR_31TO7_LSB 7
2170 /* The Most Significant Bit (MSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
2171 #define ALT_UART_MCR_RSVD_MCR_31TO7_MSB 31
2172 /* The width in bits of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
2173 #define ALT_UART_MCR_RSVD_MCR_31TO7_WIDTH 25
2174 /* The mask used to set the ALT_UART_MCR_RSVD_MCR_31TO7 register field value. */
2175 #define ALT_UART_MCR_RSVD_MCR_31TO7_SET_MSK 0xffffff80
2176 /* The mask used to clear the ALT_UART_MCR_RSVD_MCR_31TO7 register field value. */
2177 #define ALT_UART_MCR_RSVD_MCR_31TO7_CLR_MSK 0x0000007f
2178 /* The reset value of the ALT_UART_MCR_RSVD_MCR_31TO7 register field. */
2179 #define ALT_UART_MCR_RSVD_MCR_31TO7_RESET 0x0
2180 /* Extracts the ALT_UART_MCR_RSVD_MCR_31TO7 field value from a register. */
2181 #define ALT_UART_MCR_RSVD_MCR_31TO7_GET(value) (((value) & 0xffffff80) >> 7)
2182 /* Produces a ALT_UART_MCR_RSVD_MCR_31TO7 register field value suitable for setting the register. */
2183 #define ALT_UART_MCR_RSVD_MCR_31TO7_SET(value) (((value) << 7) & 0xffffff80)
2184 
2185 #ifndef __ASSEMBLY__
2186 /*
2187  * WARNING: The C register and register group struct declarations are provided for
2188  * convenience and illustrative purposes. They should, however, be used with
2189  * caution as the C language standard provides no guarantees about the alignment or
2190  * atomicity of device memory accesses. The recommended practice for writing
2191  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2192  * alt_write_word() functions.
2193  *
2194  * The struct declaration for register ALT_UART_MCR.
2195  */
2196 struct ALT_UART_MCR_s
2197 {
2198  uint32_t dtr : 1; /* ALT_UART_MCR_DTR */
2199  uint32_t rts : 1; /* ALT_UART_MCR_RTS */
2200  uint32_t out1 : 1; /* ALT_UART_MCR_OUT1 */
2201  uint32_t out2 : 1; /* ALT_UART_MCR_OUT2 */
2202  uint32_t loopback : 1; /* ALT_UART_MCR_LOOPBACK */
2203  uint32_t afce : 1; /* ALT_UART_MCR_AFCE */
2204  const uint32_t sire : 1; /* ALT_UART_MCR_SIRE */
2205  const uint32_t rsvd_mcr_31to7 : 25; /* ALT_UART_MCR_RSVD_MCR_31TO7 */
2206 };
2207 
2208 /* The typedef declaration for register ALT_UART_MCR. */
2209 typedef volatile struct ALT_UART_MCR_s ALT_UART_MCR_t;
2210 #endif /* __ASSEMBLY__ */
2211 
2212 /* The reset value of the ALT_UART_MCR register. */
2213 #define ALT_UART_MCR_RESET 0x00000000
2214 /* The byte offset of the ALT_UART_MCR register from the beginning of the component. */
2215 #define ALT_UART_MCR_OFST 0x10
2216 /* The address of the ALT_UART_MCR register. */
2217 #define ALT_UART_MCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))
2218 
2219 /*
2220  * Register : lsr
2221  *
2222  * Line Status Register
2223  *
2224  * Register Layout
2225  *
2226  * Bits | Access | Reset | Description
2227  * :-------|:-------|:------|:----------------------------
2228  * [0] | R | 0x0 | ALT_UART_LSR_DR
2229  * [1] | R | 0x0 | ALT_UART_LSR_OE
2230  * [2] | R | 0x0 | ALT_UART_LSR_PE
2231  * [3] | R | 0x0 | ALT_UART_LSR_FE
2232  * [4] | R | 0x0 | ALT_UART_LSR_BI
2233  * [5] | R | 0x1 | ALT_UART_LSR_THRE
2234  * [6] | R | 0x1 | ALT_UART_LSR_TEMT
2235  * [7] | R | 0x0 | ALT_UART_LSR_RFE
2236  * [31:8] | R | 0x0 | ALT_UART_LSR_RSVD_LSR_31TO8
2237  *
2238  */
2239 /*
2240  * Field : dr
2241  *
2242  * Data Ready bit.
2243  *
2244  * This is used to indicate that the receiver contains at least one character in
2245  * the
2246  *
2247  * RBR or the receiver FIFO.
2248  *
2249  * 0 = no data ready
2250  *
2251  * 1 = data ready
2252  *
2253  * This bit is cleared when the RBR is read in the non-FIFO mode, or when the
2254  * receiver
2255  *
2256  * FIFO is empty, in the FIFO mode.
2257  *
2258  * Field Enumeration Values:
2259  *
2260  * Enum | Value | Description
2261  * :----------------------------|:------|:--------------
2262  * ALT_UART_LSR_DR_E_NODATARDY | 0x0 | no data ready
2263  * ALT_UART_LSR_DR_E_DATARDY | 0x1 | data ready
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /*
2269  * Enumerated value for register field ALT_UART_LSR_DR
2270  *
2271  * no data ready
2272  */
2273 #define ALT_UART_LSR_DR_E_NODATARDY 0x0
2274 /*
2275  * Enumerated value for register field ALT_UART_LSR_DR
2276  *
2277  * data ready
2278  */
2279 #define ALT_UART_LSR_DR_E_DATARDY 0x1
2280 
2281 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_DR register field. */
2282 #define ALT_UART_LSR_DR_LSB 0
2283 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_DR register field. */
2284 #define ALT_UART_LSR_DR_MSB 0
2285 /* The width in bits of the ALT_UART_LSR_DR register field. */
2286 #define ALT_UART_LSR_DR_WIDTH 1
2287 /* The mask used to set the ALT_UART_LSR_DR register field value. */
2288 #define ALT_UART_LSR_DR_SET_MSK 0x00000001
2289 /* The mask used to clear the ALT_UART_LSR_DR register field value. */
2290 #define ALT_UART_LSR_DR_CLR_MSK 0xfffffffe
2291 /* The reset value of the ALT_UART_LSR_DR register field. */
2292 #define ALT_UART_LSR_DR_RESET 0x0
2293 /* Extracts the ALT_UART_LSR_DR field value from a register. */
2294 #define ALT_UART_LSR_DR_GET(value) (((value) & 0x00000001) >> 0)
2295 /* Produces a ALT_UART_LSR_DR register field value suitable for setting the register. */
2296 #define ALT_UART_LSR_DR_SET(value) (((value) << 0) & 0x00000001)
2297 
2298 /*
2299  * Field : oe
2300  *
2301  * Overrun error bit.
2302  *
2303  * This is used to indicate the occurrence of an overrun error. This occurs if a
2304  * new data
2305  *
2306  * character was received before the previous data was read. In the non-FIFO mode,
2307  * the OE
2308  *
2309  * bit is set when a new character arrives in the receiver before the previous
2310  * character
2311  *
2312  * was read from the RBR. When this happens, the data in the RBR is overwritten. In
2313  * the
2314  *
2315  * FIFO mode, an overrun error occurs when the FIFO is full and a new character
2316  * arrives at
2317  *
2318  * the receiver. The data in the FIFO is retained and the data in the receive shift
2319  * register
2320  *
2321  * is lost.
2322  *
2323  * 0 = no overrun error
2324  *
2325  * 1 = overrun error
2326  *
2327  * Reading the LSR clears the OE bit.
2328  *
2329  * Field Enumeration Values:
2330  *
2331  * Enum | Value | Description
2332  * :----------------------------|:------|:-----------------
2333  * ALT_UART_LSR_OE_E_NOOVERRUN | 0x0 | no overrun error
2334  * ALT_UART_LSR_OE_E_OVERRUN | 0x1 | overrun error
2335  *
2336  * Field Access Macros:
2337  *
2338  */
2339 /*
2340  * Enumerated value for register field ALT_UART_LSR_OE
2341  *
2342  * no overrun error
2343  */
2344 #define ALT_UART_LSR_OE_E_NOOVERRUN 0x0
2345 /*
2346  * Enumerated value for register field ALT_UART_LSR_OE
2347  *
2348  * overrun error
2349  */
2350 #define ALT_UART_LSR_OE_E_OVERRUN 0x1
2351 
2352 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_OE register field. */
2353 #define ALT_UART_LSR_OE_LSB 1
2354 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_OE register field. */
2355 #define ALT_UART_LSR_OE_MSB 1
2356 /* The width in bits of the ALT_UART_LSR_OE register field. */
2357 #define ALT_UART_LSR_OE_WIDTH 1
2358 /* The mask used to set the ALT_UART_LSR_OE register field value. */
2359 #define ALT_UART_LSR_OE_SET_MSK 0x00000002
2360 /* The mask used to clear the ALT_UART_LSR_OE register field value. */
2361 #define ALT_UART_LSR_OE_CLR_MSK 0xfffffffd
2362 /* The reset value of the ALT_UART_LSR_OE register field. */
2363 #define ALT_UART_LSR_OE_RESET 0x0
2364 /* Extracts the ALT_UART_LSR_OE field value from a register. */
2365 #define ALT_UART_LSR_OE_GET(value) (((value) & 0x00000002) >> 1)
2366 /* Produces a ALT_UART_LSR_OE register field value suitable for setting the register. */
2367 #define ALT_UART_LSR_OE_SET(value) (((value) << 1) & 0x00000002)
2368 
2369 /*
2370  * Field : pe
2371  *
2372  * Parity Error bit.
2373  *
2374  * This is used to indicate the occurrence of a parity error in the receiver if the
2375  *
2376  * Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity
2377  * error is
2378  *
2379  * associated with a character received, it is revealed when the character with the
2380  * parity
2381  *
2382  * error arrives at the top of the FIFO.
2383  *
2384  * It should be noted that the Parity Error (PE) bit (LSR[2]) will be set if a
2385  * break
2386  *
2387  * interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
2388  *
2389  * 0 = no parity error
2390  *
2391  * 1 = parity error
2392  *
2393  * Reading the LSR clears the PE bit.
2394  *
2395  * Field Enumeration Values:
2396  *
2397  * Enum | Value | Description
2398  * :------------------------------|:------|:----------------
2399  * ALT_UART_LSR_PE_E_NOPARITYERR | 0x0 | no parity error
2400  * ALT_UART_LSR_PE_E_PARITYERR | 0x1 | no parity error
2401  *
2402  * Field Access Macros:
2403  *
2404  */
2405 /*
2406  * Enumerated value for register field ALT_UART_LSR_PE
2407  *
2408  * no parity error
2409  */
2410 #define ALT_UART_LSR_PE_E_NOPARITYERR 0x0
2411 /*
2412  * Enumerated value for register field ALT_UART_LSR_PE
2413  *
2414  * no parity error
2415  */
2416 #define ALT_UART_LSR_PE_E_PARITYERR 0x1
2417 
2418 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_PE register field. */
2419 #define ALT_UART_LSR_PE_LSB 2
2420 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_PE register field. */
2421 #define ALT_UART_LSR_PE_MSB 2
2422 /* The width in bits of the ALT_UART_LSR_PE register field. */
2423 #define ALT_UART_LSR_PE_WIDTH 1
2424 /* The mask used to set the ALT_UART_LSR_PE register field value. */
2425 #define ALT_UART_LSR_PE_SET_MSK 0x00000004
2426 /* The mask used to clear the ALT_UART_LSR_PE register field value. */
2427 #define ALT_UART_LSR_PE_CLR_MSK 0xfffffffb
2428 /* The reset value of the ALT_UART_LSR_PE register field. */
2429 #define ALT_UART_LSR_PE_RESET 0x0
2430 /* Extracts the ALT_UART_LSR_PE field value from a register. */
2431 #define ALT_UART_LSR_PE_GET(value) (((value) & 0x00000004) >> 2)
2432 /* Produces a ALT_UART_LSR_PE register field value suitable for setting the register. */
2433 #define ALT_UART_LSR_PE_SET(value) (((value) << 2) & 0x00000004)
2434 
2435 /*
2436  * Field : fe
2437  *
2438  * Framing Error bit.
2439  *
2440  * This is used to indicate the occurrence of a framing error in the receiver. A
2441  * framing
2442  *
2443  * error occurs when the receiver does not detect a valid STOP bit in the received
2444  * data.
2445  *
2446  * In the FIFO mode, since the framing error is associated with a character
2447  * received, it
2448  *
2449  * is revealed when the character with the framing error is at the top of the FIFO.
2450  * When
2451  *
2452  * a framing error occurs the UART will try resynchronize. It does this by assuming
2453  * that
2454  *
2455  * the error was due to the start bit of the next character and then continues
2456  * receiving
2457  *
2458  * the other bit i.e. data, and/or parity and stop.
2459  *
2460  * It should be noted that the Framing Error (FE) bit (LSR[3]) will be set if a
2461  * break
2462  *
2463  * interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
2464  *
2465  * 0 = no framing error
2466  *
2467  * 1 = framing error
2468  *
2469  * Reading the LSR clears the FE bit.
2470  *
2471  * Field Enumeration Values:
2472  *
2473  * Enum | Value | Description
2474  * :---------------------------|:------|:-----------------
2475  * ALT_UART_LSR_FE_E_NOFRMERR | 0x0 | no framing error
2476  * ALT_UART_LSR_FE_E_FRMERR | 0x1 | framing error
2477  *
2478  * Field Access Macros:
2479  *
2480  */
2481 /*
2482  * Enumerated value for register field ALT_UART_LSR_FE
2483  *
2484  * no framing error
2485  */
2486 #define ALT_UART_LSR_FE_E_NOFRMERR 0x0
2487 /*
2488  * Enumerated value for register field ALT_UART_LSR_FE
2489  *
2490  * framing error
2491  */
2492 #define ALT_UART_LSR_FE_E_FRMERR 0x1
2493 
2494 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_FE register field. */
2495 #define ALT_UART_LSR_FE_LSB 3
2496 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_FE register field. */
2497 #define ALT_UART_LSR_FE_MSB 3
2498 /* The width in bits of the ALT_UART_LSR_FE register field. */
2499 #define ALT_UART_LSR_FE_WIDTH 1
2500 /* The mask used to set the ALT_UART_LSR_FE register field value. */
2501 #define ALT_UART_LSR_FE_SET_MSK 0x00000008
2502 /* The mask used to clear the ALT_UART_LSR_FE register field value. */
2503 #define ALT_UART_LSR_FE_CLR_MSK 0xfffffff7
2504 /* The reset value of the ALT_UART_LSR_FE register field. */
2505 #define ALT_UART_LSR_FE_RESET 0x0
2506 /* Extracts the ALT_UART_LSR_FE field value from a register. */
2507 #define ALT_UART_LSR_FE_GET(value) (((value) & 0x00000008) >> 3)
2508 /* Produces a ALT_UART_LSR_FE register field value suitable for setting the register. */
2509 #define ALT_UART_LSR_FE_SET(value) (((value) << 3) & 0x00000008)
2510 
2511 /*
2512  * Field : bi
2513  *
2514  * Break Interrupt bit.
2515  *
2516  * This is used to indicate the detection of a break sequence on the serial input
2517  * data.
2518  *
2519  * If in UART mode it is set whenever the serial input, sin, is held in a logic
2520  * '0'
2521  *
2522  * state for longer than the sum of start time + data bits + parity + stop bits.
2523  *
2524  * If in infrared mode it is set whenever the serial input, sir_in, is
2525  * continuously
2526  *
2527  * pulsed to logic '0' for longer than the sum of start time + data bits + parity +
2528  * stop
2529  *
2530  * bits.
2531  *
2532  * A break condition on serial input causes one and only one character, consisting
2533  * of
2534  *
2535  * all zeros, to be received by the UART. In the FIFO mode, the character
2536  * associated
2537  *
2538  * with the break condition is carried through the FIFO and is revealed when the
2539  *
2540  * character is at the top of the FIFO. Reading the LSR clears the BI bit. In the
2541  *
2542  * non-FIFO mode, the BI indication occurs immediately and persists until the LSR
2543  * is
2544  *
2545  * read.
2546  *
2547  * Field Access Macros:
2548  *
2549  */
2550 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_BI register field. */
2551 #define ALT_UART_LSR_BI_LSB 4
2552 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_BI register field. */
2553 #define ALT_UART_LSR_BI_MSB 4
2554 /* The width in bits of the ALT_UART_LSR_BI register field. */
2555 #define ALT_UART_LSR_BI_WIDTH 1
2556 /* The mask used to set the ALT_UART_LSR_BI register field value. */
2557 #define ALT_UART_LSR_BI_SET_MSK 0x00000010
2558 /* The mask used to clear the ALT_UART_LSR_BI register field value. */
2559 #define ALT_UART_LSR_BI_CLR_MSK 0xffffffef
2560 /* The reset value of the ALT_UART_LSR_BI register field. */
2561 #define ALT_UART_LSR_BI_RESET 0x0
2562 /* Extracts the ALT_UART_LSR_BI field value from a register. */
2563 #define ALT_UART_LSR_BI_GET(value) (((value) & 0x00000010) >> 4)
2564 /* Produces a ALT_UART_LSR_BI register field value suitable for setting the register. */
2565 #define ALT_UART_LSR_BI_SET(value) (((value) << 4) & 0x00000010)
2566 
2567 /*
2568  * Field : thre
2569  *
2570  * Transmit Holding Register Empty bit.
2571  *
2572  * If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and
2573  *
2574  * regardless of FIFO's being implemented/enabled or not, this bit indicates that
2575  *
2576  * the THR or TX FIFO is empty. This bit is set whenever data is transferred from
2577  *
2578  * the THR or TX FIFO to the transmitter shift register and no new data has been
2579  *
2580  * written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if
2581  * the
2582  *
2583  * THRE Interrupt is enabled.
2584  *
2585  * If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active
2586  *
2587  * (IER[7] set to one and FCR[0] set to one respectively), the functionality is
2588  * switched
2589  *
2590  * to indicate the transmitter FIFO is full, and no longer controls THRE
2591  * interrupts,
2592  *
2593  * which are then controlled by the FCR[5:4] threshold setting. Programmable THRE
2594  *
2595  * interrupt mode operation is described in detail in section 5.7 on page 52.
2596  *
2597  * Field Access Macros:
2598  *
2599  */
2600 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_THRE register field. */
2601 #define ALT_UART_LSR_THRE_LSB 5
2602 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_THRE register field. */
2603 #define ALT_UART_LSR_THRE_MSB 5
2604 /* The width in bits of the ALT_UART_LSR_THRE register field. */
2605 #define ALT_UART_LSR_THRE_WIDTH 1
2606 /* The mask used to set the ALT_UART_LSR_THRE register field value. */
2607 #define ALT_UART_LSR_THRE_SET_MSK 0x00000020
2608 /* The mask used to clear the ALT_UART_LSR_THRE register field value. */
2609 #define ALT_UART_LSR_THRE_CLR_MSK 0xffffffdf
2610 /* The reset value of the ALT_UART_LSR_THRE register field. */
2611 #define ALT_UART_LSR_THRE_RESET 0x1
2612 /* Extracts the ALT_UART_LSR_THRE field value from a register. */
2613 #define ALT_UART_LSR_THRE_GET(value) (((value) & 0x00000020) >> 5)
2614 /* Produces a ALT_UART_LSR_THRE register field value suitable for setting the register. */
2615 #define ALT_UART_LSR_THRE_SET(value) (((value) << 5) & 0x00000020)
2616 
2617 /*
2618  * Field : temt
2619  *
2620  * Transmitter Empty bit.
2621  *
2622  * If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one), this
2623  *
2624  * bit is set whenever the Transmitter Shift Register and the FIFO are both empty.
2625  *
2626  * If in the non-FIFO mode or FIFO's are disabled, this bit is set whenever the
2627  *
2628  * Transmitter Holding Register and the Transmitter Shift Register are both empty.
2629  *
2630  * Field Enumeration Values:
2631  *
2632  * Enum | Value | Description
2633  * :-----------------------------|:------|:-----------------------
2634  * ALT_UART_LSR_TEMT_E_NOTEMPTY | 0x0 | Transmit Empty not set
2635  * ALT_UART_LSR_TEMT_E_EMPTY | 0x1 | Transmit Empty set
2636  *
2637  * Field Access Macros:
2638  *
2639  */
2640 /*
2641  * Enumerated value for register field ALT_UART_LSR_TEMT
2642  *
2643  * Transmit Empty not set
2644  */
2645 #define ALT_UART_LSR_TEMT_E_NOTEMPTY 0x0
2646 /*
2647  * Enumerated value for register field ALT_UART_LSR_TEMT
2648  *
2649  * Transmit Empty set
2650  */
2651 #define ALT_UART_LSR_TEMT_E_EMPTY 0x1
2652 
2653 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_TEMT register field. */
2654 #define ALT_UART_LSR_TEMT_LSB 6
2655 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_TEMT register field. */
2656 #define ALT_UART_LSR_TEMT_MSB 6
2657 /* The width in bits of the ALT_UART_LSR_TEMT register field. */
2658 #define ALT_UART_LSR_TEMT_WIDTH 1
2659 /* The mask used to set the ALT_UART_LSR_TEMT register field value. */
2660 #define ALT_UART_LSR_TEMT_SET_MSK 0x00000040
2661 /* The mask used to clear the ALT_UART_LSR_TEMT register field value. */
2662 #define ALT_UART_LSR_TEMT_CLR_MSK 0xffffffbf
2663 /* The reset value of the ALT_UART_LSR_TEMT register field. */
2664 #define ALT_UART_LSR_TEMT_RESET 0x1
2665 /* Extracts the ALT_UART_LSR_TEMT field value from a register. */
2666 #define ALT_UART_LSR_TEMT_GET(value) (((value) & 0x00000040) >> 6)
2667 /* Produces a ALT_UART_LSR_TEMT register field value suitable for setting the register. */
2668 #define ALT_UART_LSR_TEMT_SET(value) (((value) << 6) & 0x00000040)
2669 
2670 /*
2671  * Field : rfe
2672  *
2673  * Receiver FIFO Error bit.
2674  *
2675  * This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0]
2676  *
2677  * set to one). This is used to indicate if there is at least one parity error,
2678  * framing
2679  *
2680  * error, or break indication in the FIFO. That is:
2681  *
2682  * 0 = no error in RX FIFO
2683  *
2684  * 1 = error in RX FIFO
2685  *
2686  * This bit is cleared when the LSR is read and the character with the error is at
2687  * the
2688  *
2689  * top of the receiver FIFO and there are no subsequent errors in the FIFO.
2690  *
2691  * Field Enumeration Values:
2692  *
2693  * Enum | Value | Description
2694  * :-------------------------|:------|:--------------------
2695  * ALT_UART_LSR_RFE_E_NOERR | 0x0 | no error in Rx FIFO
2696  * ALT_UART_LSR_RFE_E_ERR | 0x1 | error in Rx FIFO
2697  *
2698  * Field Access Macros:
2699  *
2700  */
2701 /*
2702  * Enumerated value for register field ALT_UART_LSR_RFE
2703  *
2704  * no error in Rx FIFO
2705  */
2706 #define ALT_UART_LSR_RFE_E_NOERR 0x0
2707 /*
2708  * Enumerated value for register field ALT_UART_LSR_RFE
2709  *
2710  * error in Rx FIFO
2711  */
2712 #define ALT_UART_LSR_RFE_E_ERR 0x1
2713 
2714 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RFE register field. */
2715 #define ALT_UART_LSR_RFE_LSB 7
2716 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RFE register field. */
2717 #define ALT_UART_LSR_RFE_MSB 7
2718 /* The width in bits of the ALT_UART_LSR_RFE register field. */
2719 #define ALT_UART_LSR_RFE_WIDTH 1
2720 /* The mask used to set the ALT_UART_LSR_RFE register field value. */
2721 #define ALT_UART_LSR_RFE_SET_MSK 0x00000080
2722 /* The mask used to clear the ALT_UART_LSR_RFE register field value. */
2723 #define ALT_UART_LSR_RFE_CLR_MSK 0xffffff7f
2724 /* The reset value of the ALT_UART_LSR_RFE register field. */
2725 #define ALT_UART_LSR_RFE_RESET 0x0
2726 /* Extracts the ALT_UART_LSR_RFE field value from a register. */
2727 #define ALT_UART_LSR_RFE_GET(value) (((value) & 0x00000080) >> 7)
2728 /* Produces a ALT_UART_LSR_RFE register field value suitable for setting the register. */
2729 #define ALT_UART_LSR_RFE_SET(value) (((value) << 7) & 0x00000080)
2730 
2731 /*
2732  * Field : rsvd_lsr_31to8
2733  *
2734  * Reserved bits [31:8] - Read Only
2735  *
2736  * Field Access Macros:
2737  *
2738  */
2739 /* The Least Significant Bit (LSB) position of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2740 #define ALT_UART_LSR_RSVD_LSR_31TO8_LSB 8
2741 /* The Most Significant Bit (MSB) position of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2742 #define ALT_UART_LSR_RSVD_LSR_31TO8_MSB 31
2743 /* The width in bits of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2744 #define ALT_UART_LSR_RSVD_LSR_31TO8_WIDTH 24
2745 /* The mask used to set the ALT_UART_LSR_RSVD_LSR_31TO8 register field value. */
2746 #define ALT_UART_LSR_RSVD_LSR_31TO8_SET_MSK 0xffffff00
2747 /* The mask used to clear the ALT_UART_LSR_RSVD_LSR_31TO8 register field value. */
2748 #define ALT_UART_LSR_RSVD_LSR_31TO8_CLR_MSK 0x000000ff
2749 /* The reset value of the ALT_UART_LSR_RSVD_LSR_31TO8 register field. */
2750 #define ALT_UART_LSR_RSVD_LSR_31TO8_RESET 0x0
2751 /* Extracts the ALT_UART_LSR_RSVD_LSR_31TO8 field value from a register. */
2752 #define ALT_UART_LSR_RSVD_LSR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
2753 /* Produces a ALT_UART_LSR_RSVD_LSR_31TO8 register field value suitable for setting the register. */
2754 #define ALT_UART_LSR_RSVD_LSR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
2755 
2756 #ifndef __ASSEMBLY__
2757 /*
2758  * WARNING: The C register and register group struct declarations are provided for
2759  * convenience and illustrative purposes. They should, however, be used with
2760  * caution as the C language standard provides no guarantees about the alignment or
2761  * atomicity of device memory accesses. The recommended practice for writing
2762  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2763  * alt_write_word() functions.
2764  *
2765  * The struct declaration for register ALT_UART_LSR.
2766  */
2767 struct ALT_UART_LSR_s
2768 {
2769  const uint32_t dr : 1; /* ALT_UART_LSR_DR */
2770  const uint32_t oe : 1; /* ALT_UART_LSR_OE */
2771  const uint32_t pe : 1; /* ALT_UART_LSR_PE */
2772  const uint32_t fe : 1; /* ALT_UART_LSR_FE */
2773  const uint32_t bi : 1; /* ALT_UART_LSR_BI */
2774  const uint32_t thre : 1; /* ALT_UART_LSR_THRE */
2775  const uint32_t temt : 1; /* ALT_UART_LSR_TEMT */
2776  const uint32_t rfe : 1; /* ALT_UART_LSR_RFE */
2777  const uint32_t rsvd_lsr_31to8 : 24; /* ALT_UART_LSR_RSVD_LSR_31TO8 */
2778 };
2779 
2780 /* The typedef declaration for register ALT_UART_LSR. */
2781 typedef volatile struct ALT_UART_LSR_s ALT_UART_LSR_t;
2782 #endif /* __ASSEMBLY__ */
2783 
2784 /* The reset value of the ALT_UART_LSR register. */
2785 #define ALT_UART_LSR_RESET 0x00000060
2786 /* The byte offset of the ALT_UART_LSR register from the beginning of the component. */
2787 #define ALT_UART_LSR_OFST 0x14
2788 /* The address of the ALT_UART_LSR register. */
2789 #define ALT_UART_LSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_LSR_OFST))
2790 
2791 /*
2792  * Register : msr
2793  *
2794  * Modem Status Register
2795  *
2796  * It should be noted that whenever bits 0, 1, 2 or 3 is set to logic one, to
2797  * indicate
2798  *
2799  * a change on the modem control inputs, a modem status interrupt will be generated
2800  *
2801  * if enabled via the IER regardless of when the change occurred. Since the delta
2802  * bits
2803  *
2804  * (bits 0, 1, 3) can get set after a reset if their respective modem signals are
2805  *
2806  * active (see individual bits for details), a read of the MSR after reset can be
2807  *
2808  * performed to prevent unwanted interrupts.
2809  *
2810  * Register Layout
2811  *
2812  * Bits | Access | Reset | Description
2813  * :-------|:-------|:------|:----------------------------
2814  * [0] | R | 0x0 | ALT_UART_MSR_DCTS
2815  * [1] | R | 0x0 | ALT_UART_MSR_DDSR
2816  * [2] | R | 0x0 | ALT_UART_MSR_TERI
2817  * [3] | R | 0x0 | ALT_UART_MSR_DDCD
2818  * [4] | R | 0x0 | ALT_UART_MSR_CTS
2819  * [5] | R | 0x0 | ALT_UART_MSR_DSR
2820  * [6] | R | 0x0 | ALT_UART_MSR_RI
2821  * [7] | R | 0x0 | ALT_UART_MSR_DCD
2822  * [31:8] | R | 0x0 | ALT_UART_MSR_RSVD_MSC_31TO8
2823  *
2824  */
2825 /*
2826  * Field : dcts
2827  *
2828  * Delta Clear to Send.
2829  *
2830  * This is used to indicate that the modem control line cts_n has changed since the
2831  *
2832  * last time the MSR was read. That is:
2833  *
2834  * 0 = no change on cts_n since last read of MSR
2835  *
2836  * 1 = change on cts_n since last read of MSR
2837  *
2838  * Reading the MSR clears the DCTS bit.
2839  *
2840  * In Loopback Mode (MCR[4] set to one), DCTS reflects changes on MCR[1] (RTS).
2841  *
2842  * Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a
2843  * reset
2844  *
2845  * occurs (software or otherwise), then the DCTS bit will get set when the reset is
2846  *
2847  * removed if the cts_n signal remains asserted.
2848  *
2849  * Field Enumeration Values:
2850  *
2851  * Enum | Value | Description
2852  * :--------------------------|:------|:-----------------------------------------------
2853  * ALT_UART_MSR_DCTS_E_NOCHG | 0x0 | no change on uart_cts_n since last read of MSR
2854  * ALT_UART_MSR_DCTS_E_CHG | 0x1 | change on uart_cts_n since last read of MSR
2855  *
2856  * Field Access Macros:
2857  *
2858  */
2859 /*
2860  * Enumerated value for register field ALT_UART_MSR_DCTS
2861  *
2862  * no change on uart_cts_n since last read of MSR
2863  */
2864 #define ALT_UART_MSR_DCTS_E_NOCHG 0x0
2865 /*
2866  * Enumerated value for register field ALT_UART_MSR_DCTS
2867  *
2868  * change on uart_cts_n since last read of MSR
2869  */
2870 #define ALT_UART_MSR_DCTS_E_CHG 0x1
2871 
2872 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field. */
2873 #define ALT_UART_MSR_DCTS_LSB 0
2874 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field. */
2875 #define ALT_UART_MSR_DCTS_MSB 0
2876 /* The width in bits of the ALT_UART_MSR_DCTS register field. */
2877 #define ALT_UART_MSR_DCTS_WIDTH 1
2878 /* The mask used to set the ALT_UART_MSR_DCTS register field value. */
2879 #define ALT_UART_MSR_DCTS_SET_MSK 0x00000001
2880 /* The mask used to clear the ALT_UART_MSR_DCTS register field value. */
2881 #define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe
2882 /* The reset value of the ALT_UART_MSR_DCTS register field. */
2883 #define ALT_UART_MSR_DCTS_RESET 0x0
2884 /* Extracts the ALT_UART_MSR_DCTS field value from a register. */
2885 #define ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0)
2886 /* Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register. */
2887 #define ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001)
2888 
2889 /*
2890  * Field : ddsr
2891  *
2892  * Delta Data Set Ready.
2893  *
2894  * This is used to indicate that the modem control line dsr_n has changed since
2895  *
2896  * the last time the MSR was read. That is:
2897  *
2898  * 0 = no change on dsr_n since last read of MSR
2899  *
2900  * 1 = change on dsr_n since last read of MSR
2901  *
2902  * Reading the MSR clears the DDSR bit.
2903  *
2904  * In Loopback Mode (MCR[4] set to one), DDSR reflects changes on MCR[0] (DTR).
2905  *
2906  * Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a
2907  * reset
2908  *
2909  * occurs (software or otherwise), then the DDSR bit will get set when the reset is
2910  *
2911  * removed if the dsr_n signal remains asserted.
2912  *
2913  * Field Enumeration Values:
2914  *
2915  * Enum | Value | Description
2916  * :--------------------------|:------|:-----------------------------------------------
2917  * ALT_UART_MSR_DDSR_E_NOCHG | 0x0 | no change on uart_dsr_n since last read of MSR
2918  * ALT_UART_MSR_DDSR_E_CHG | 0x1 | change on uart_dsr_n since last read of MSR
2919  *
2920  * Field Access Macros:
2921  *
2922  */
2923 /*
2924  * Enumerated value for register field ALT_UART_MSR_DDSR
2925  *
2926  * no change on uart_dsr_n since last read of MSR
2927  */
2928 #define ALT_UART_MSR_DDSR_E_NOCHG 0x0
2929 /*
2930  * Enumerated value for register field ALT_UART_MSR_DDSR
2931  *
2932  * change on uart_dsr_n since last read of MSR
2933  */
2934 #define ALT_UART_MSR_DDSR_E_CHG 0x1
2935 
2936 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field. */
2937 #define ALT_UART_MSR_DDSR_LSB 1
2938 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field. */
2939 #define ALT_UART_MSR_DDSR_MSB 1
2940 /* The width in bits of the ALT_UART_MSR_DDSR register field. */
2941 #define ALT_UART_MSR_DDSR_WIDTH 1
2942 /* The mask used to set the ALT_UART_MSR_DDSR register field value. */
2943 #define ALT_UART_MSR_DDSR_SET_MSK 0x00000002
2944 /* The mask used to clear the ALT_UART_MSR_DDSR register field value. */
2945 #define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd
2946 /* The reset value of the ALT_UART_MSR_DDSR register field. */
2947 #define ALT_UART_MSR_DDSR_RESET 0x0
2948 /* Extracts the ALT_UART_MSR_DDSR field value from a register. */
2949 #define ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1)
2950 /* Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register. */
2951 #define ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002)
2952 
2953 /*
2954  * Field : teri
2955  *
2956  * Trailing Edge of Ring Indicator.
2957  *
2958  * This is used to indicate that a change on the input ri_n (from an active low, to
2959  *
2960  * an inactive high state) has occurred since the last time the MSR was read. That
2961  * is:
2962  *
2963  * 0 = no change on ri_n since last read of MSR
2964  *
2965  * 1 = change on ri_n since last read of MSR
2966  *
2967  * Reading the MSR clears the TERI bit.
2968  *
2969  * In Loopback Mode (MCR[4] set to one), TERI reflects when MCR[2] (Out1) has
2970  * changed
2971  *
2972  * state from a high to a low.
2973  *
2974  * Field Enumeration Values:
2975  *
2976  * Enum | Value | Description
2977  * :--------------------------|:------|:----------------------------------------------
2978  * ALT_UART_MSR_TERI_E_NOCHG | 0x0 | no change on uart_ri_n since last read of MSR
2979  * ALT_UART_MSR_TERI_E_CHG | 0x1 | change on uart_ri_n since last read of MSR
2980  *
2981  * Field Access Macros:
2982  *
2983  */
2984 /*
2985  * Enumerated value for register field ALT_UART_MSR_TERI
2986  *
2987  * no change on uart_ri_n since last read of MSR
2988  */
2989 #define ALT_UART_MSR_TERI_E_NOCHG 0x0
2990 /*
2991  * Enumerated value for register field ALT_UART_MSR_TERI
2992  *
2993  * change on uart_ri_n since last read of MSR
2994  */
2995 #define ALT_UART_MSR_TERI_E_CHG 0x1
2996 
2997 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field. */
2998 #define ALT_UART_MSR_TERI_LSB 2
2999 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field. */
3000 #define ALT_UART_MSR_TERI_MSB 2
3001 /* The width in bits of the ALT_UART_MSR_TERI register field. */
3002 #define ALT_UART_MSR_TERI_WIDTH 1
3003 /* The mask used to set the ALT_UART_MSR_TERI register field value. */
3004 #define ALT_UART_MSR_TERI_SET_MSK 0x00000004
3005 /* The mask used to clear the ALT_UART_MSR_TERI register field value. */
3006 #define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb
3007 /* The reset value of the ALT_UART_MSR_TERI register field. */
3008 #define ALT_UART_MSR_TERI_RESET 0x0
3009 /* Extracts the ALT_UART_MSR_TERI field value from a register. */
3010 #define ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2)
3011 /* Produces a ALT_UART_MSR_TERI register field value suitable for setting the register. */
3012 #define ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004)
3013 
3014 /*
3015  * Field : ddcd
3016  *
3017  * Delta Data Carrier Detect.
3018  *
3019  * This is used to indicate that the modem control line dcd_n has changed since the
3020  * last
3021  *
3022  * time the MSR was read. That is:
3023  *
3024  * 0 = no change on dcd_n since last read of MSR
3025  *
3026  * 1 = change on dcd_n since last read of MSR
3027  *
3028  * Reading the MSR clears the DDCD bit.
3029  *
3030  * In Loopback Mode (MCR[4] set to one), DDCD reflects changes on MCR[3] (Out2).
3031  *
3032  * Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a
3033  * reset
3034  *
3035  * occurs (software or otherwise), then the DDCD bit will get set when the reset is
3036  *
3037  * removed if the dcd_n signal remains asserted.
3038  *
3039  * Field Enumeration Values:
3040  *
3041  * Enum | Value | Description
3042  * :--------------------------|:------|:-----------------------------------------------
3043  * ALT_UART_MSR_DDCD_E_NOCHG | 0x0 | no change on uart_dcd_n since last read of MSR
3044  * ALT_UART_MSR_DDCD_E_CHG | 0x1 | change on uart_dcd_n since last read of MSR
3045  *
3046  * Field Access Macros:
3047  *
3048  */
3049 /*
3050  * Enumerated value for register field ALT_UART_MSR_DDCD
3051  *
3052  * no change on uart_dcd_n since last read of MSR
3053  */
3054 #define ALT_UART_MSR_DDCD_E_NOCHG 0x0
3055 /*
3056  * Enumerated value for register field ALT_UART_MSR_DDCD
3057  *
3058  * change on uart_dcd_n since last read of MSR
3059  */
3060 #define ALT_UART_MSR_DDCD_E_CHG 0x1
3061 
3062 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field. */
3063 #define ALT_UART_MSR_DDCD_LSB 3
3064 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field. */
3065 #define ALT_UART_MSR_DDCD_MSB 3
3066 /* The width in bits of the ALT_UART_MSR_DDCD register field. */
3067 #define ALT_UART_MSR_DDCD_WIDTH 1
3068 /* The mask used to set the ALT_UART_MSR_DDCD register field value. */
3069 #define ALT_UART_MSR_DDCD_SET_MSK 0x00000008
3070 /* The mask used to clear the ALT_UART_MSR_DDCD register field value. */
3071 #define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7
3072 /* The reset value of the ALT_UART_MSR_DDCD register field. */
3073 #define ALT_UART_MSR_DDCD_RESET 0x0
3074 /* Extracts the ALT_UART_MSR_DDCD field value from a register. */
3075 #define ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3)
3076 /* Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register. */
3077 #define ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008)
3078 
3079 /*
3080  * Field : cts
3081  *
3082  * Clear to Send.
3083  *
3084  * This is used to indicate the current state of the modem control line cts_n. That
3085  * is,
3086  *
3087  * this bit is the complement cts_n. When the Clear to Send input (cts_n) is
3088  * asserted
3089  *
3090  * it is an indication that the modem or data set is ready to exchange data with
3091  * the
3092  *
3093  * DW_apb_uart.
3094  *
3095  * 0 = cts_n input is de-asserted (logic 1)
3096  *
3097  * 1 = cts_n input is asserted (logic 0)
3098  *
3099  * In Loopback Mode (MCR[4] set to one), CTS is the same as MCR[1] (RTS).
3100  *
3101  * Field Enumeration Values:
3102  *
3103  * Enum | Value | Description
3104  * :--------------------------|:------|:------------------------------------------
3105  * ALT_UART_MSR_CTS_E_LOGIC1 | 0x0 | uart_cts_n input is de-asserted (logic 1)
3106  * ALT_UART_MSR_CTS_E_LOGIC0 | 0x1 | uart_cts_n input is asserted (logic 0)
3107  *
3108  * Field Access Macros:
3109  *
3110  */
3111 /*
3112  * Enumerated value for register field ALT_UART_MSR_CTS
3113  *
3114  * uart_cts_n input is de-asserted (logic 1)
3115  */
3116 #define ALT_UART_MSR_CTS_E_LOGIC1 0x0
3117 /*
3118  * Enumerated value for register field ALT_UART_MSR_CTS
3119  *
3120  * uart_cts_n input is asserted (logic 0)
3121  */
3122 #define ALT_UART_MSR_CTS_E_LOGIC0 0x1
3123 
3124 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field. */
3125 #define ALT_UART_MSR_CTS_LSB 4
3126 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field. */
3127 #define ALT_UART_MSR_CTS_MSB 4
3128 /* The width in bits of the ALT_UART_MSR_CTS register field. */
3129 #define ALT_UART_MSR_CTS_WIDTH 1
3130 /* The mask used to set the ALT_UART_MSR_CTS register field value. */
3131 #define ALT_UART_MSR_CTS_SET_MSK 0x00000010
3132 /* The mask used to clear the ALT_UART_MSR_CTS register field value. */
3133 #define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef
3134 /* The reset value of the ALT_UART_MSR_CTS register field. */
3135 #define ALT_UART_MSR_CTS_RESET 0x0
3136 /* Extracts the ALT_UART_MSR_CTS field value from a register. */
3137 #define ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4)
3138 /* Produces a ALT_UART_MSR_CTS register field value suitable for setting the register. */
3139 #define ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010)
3140 
3141 /*
3142  * Field : dsr
3143  *
3144  * Data Set Ready.
3145  *
3146  * This is used to indicate the current state of the modem control line dsr_n. That
3147  * is
3148  *
3149  * this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is
3150  * asserted
3151  *
3152  * it is an indication that the modem or data set is ready to establish
3153  * communications
3154  *
3155  * with the DW_apb_uart.
3156  *
3157  * 0 = dsr_n input is de-asserted (logic 1)
3158  *
3159  * 1 = dsr_n input is asserted (logic 0)
3160  *
3161  * In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR).
3162  *
3163  * Field Enumeration Values:
3164  *
3165  * Enum | Value | Description
3166  * :--------------------------|:------|:------------------------------------------
3167  * ALT_UART_MSR_DSR_E_LOGIC1 | 0x0 | uart_dsr_n input is de-asserted (logic 1)
3168  * ALT_UART_MSR_DSR_E_LOGIC0 | 0x1 | uart_dsr_n input is asserted (logic 0)
3169  *
3170  * Field Access Macros:
3171  *
3172  */
3173 /*
3174  * Enumerated value for register field ALT_UART_MSR_DSR
3175  *
3176  * uart_dsr_n input is de-asserted (logic 1)
3177  */
3178 #define ALT_UART_MSR_DSR_E_LOGIC1 0x0
3179 /*
3180  * Enumerated value for register field ALT_UART_MSR_DSR
3181  *
3182  * uart_dsr_n input is asserted (logic 0)
3183  */
3184 #define ALT_UART_MSR_DSR_E_LOGIC0 0x1
3185 
3186 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field. */
3187 #define ALT_UART_MSR_DSR_LSB 5
3188 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field. */
3189 #define ALT_UART_MSR_DSR_MSB 5
3190 /* The width in bits of the ALT_UART_MSR_DSR register field. */
3191 #define ALT_UART_MSR_DSR_WIDTH 1
3192 /* The mask used to set the ALT_UART_MSR_DSR register field value. */
3193 #define ALT_UART_MSR_DSR_SET_MSK 0x00000020
3194 /* The mask used to clear the ALT_UART_MSR_DSR register field value. */
3195 #define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf
3196 /* The reset value of the ALT_UART_MSR_DSR register field. */
3197 #define ALT_UART_MSR_DSR_RESET 0x0
3198 /* Extracts the ALT_UART_MSR_DSR field value from a register. */
3199 #define ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5)
3200 /* Produces a ALT_UART_MSR_DSR register field value suitable for setting the register. */
3201 #define ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020)
3202 
3203 /*
3204  * Field : ri
3205  *
3206  * Ring Indicator.
3207  *
3208  * This is used to indicate the current state of the modem control line ri_n. That
3209  * is
3210  *
3211  * this bit is the complement ri_n. When the Ring Indicator input (ri_n) is
3212  * asserted
3213  *
3214  * it is an indication that a telephone ringing signal has been received by the
3215  * modem
3216  *
3217  * or data set.
3218  *
3219  * 0 = ri_n input is de-asserted (logic 1)
3220  *
3221  * 1 = ri_n input is asserted (logic 0)
3222  *
3223  * In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1).
3224  *
3225  * Field Enumeration Values:
3226  *
3227  * Enum | Value | Description
3228  * :-------------------------|:------|:-----------------------------------------
3229  * ALT_UART_MSR_RI_E_LOGIC1 | 0x0 | uart_ri_n input is de-asserted (logic 1)
3230  * ALT_UART_MSR_RI_E_LOGIC0 | 0x1 | uart_ri_n input is asserted (logic 0)
3231  *
3232  * Field Access Macros:
3233  *
3234  */
3235 /*
3236  * Enumerated value for register field ALT_UART_MSR_RI
3237  *
3238  * uart_ri_n input is de-asserted (logic 1)
3239  */
3240 #define ALT_UART_MSR_RI_E_LOGIC1 0x0
3241 /*
3242  * Enumerated value for register field ALT_UART_MSR_RI
3243  *
3244  * uart_ri_n input is asserted (logic 0)
3245  */
3246 #define ALT_UART_MSR_RI_E_LOGIC0 0x1
3247 
3248 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field. */
3249 #define ALT_UART_MSR_RI_LSB 6
3250 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field. */
3251 #define ALT_UART_MSR_RI_MSB 6
3252 /* The width in bits of the ALT_UART_MSR_RI register field. */
3253 #define ALT_UART_MSR_RI_WIDTH 1
3254 /* The mask used to set the ALT_UART_MSR_RI register field value. */
3255 #define ALT_UART_MSR_RI_SET_MSK 0x00000040
3256 /* The mask used to clear the ALT_UART_MSR_RI register field value. */
3257 #define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf
3258 /* The reset value of the ALT_UART_MSR_RI register field. */
3259 #define ALT_UART_MSR_RI_RESET 0x0
3260 /* Extracts the ALT_UART_MSR_RI field value from a register. */
3261 #define ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6)
3262 /* Produces a ALT_UART_MSR_RI register field value suitable for setting the register. */
3263 #define ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040)
3264 
3265 /*
3266  * Field : dcd
3267  *
3268  * Data Carrier Detect.
3269  *
3270  * This is used to indicate the current state of the modem control line dcd_n. That
3271  * is
3272  *
3273  * this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is
3274  *
3275  * asserted it is an indication that the carrier has been detected by the modem or
3276  *
3277  * data set.
3278  *
3279  * 0 = dcd_n input is de-asserted (logic 1)
3280  *
3281  * 1 = dcd_n input is asserted (logic 0)
3282  *
3283  * In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2).
3284  *
3285  * Field Enumeration Values:
3286  *
3287  * Enum | Value | Description
3288  * :--------------------------|:------|:------------------------------------------
3289  * ALT_UART_MSR_DCD_E_LOGIC1 | 0x0 | uart_dcd_n input is de-asserted (logic 1)
3290  * ALT_UART_MSR_DCD_E_LOGIC0 | 0x1 | uart_dcd_n input is asserted (logic 0)
3291  *
3292  * Field Access Macros:
3293  *
3294  */
3295 /*
3296  * Enumerated value for register field ALT_UART_MSR_DCD
3297  *
3298  * uart_dcd_n input is de-asserted (logic 1)
3299  */
3300 #define ALT_UART_MSR_DCD_E_LOGIC1 0x0
3301 /*
3302  * Enumerated value for register field ALT_UART_MSR_DCD
3303  *
3304  * uart_dcd_n input is asserted (logic 0)
3305  */
3306 #define ALT_UART_MSR_DCD_E_LOGIC0 0x1
3307 
3308 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field. */
3309 #define ALT_UART_MSR_DCD_LSB 7
3310 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field. */
3311 #define ALT_UART_MSR_DCD_MSB 7
3312 /* The width in bits of the ALT_UART_MSR_DCD register field. */
3313 #define ALT_UART_MSR_DCD_WIDTH 1
3314 /* The mask used to set the ALT_UART_MSR_DCD register field value. */
3315 #define ALT_UART_MSR_DCD_SET_MSK 0x00000080
3316 /* The mask used to clear the ALT_UART_MSR_DCD register field value. */
3317 #define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f
3318 /* The reset value of the ALT_UART_MSR_DCD register field. */
3319 #define ALT_UART_MSR_DCD_RESET 0x0
3320 /* Extracts the ALT_UART_MSR_DCD field value from a register. */
3321 #define ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7)
3322 /* Produces a ALT_UART_MSR_DCD register field value suitable for setting the register. */
3323 #define ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080)
3324 
3325 /*
3326  * Field : rsvd_msc_31to8
3327  *
3328  * Reserved bits [31:8] - Read Only
3329  *
3330  * Field Access Macros:
3331  *
3332  */
3333 /* The Least Significant Bit (LSB) position of the ALT_UART_MSR_RSVD_MSC_31TO8 register field. */
3334 #define ALT_UART_MSR_RSVD_MSC_31TO8_LSB 8
3335 /* The Most Significant Bit (MSB) position of the ALT_UART_MSR_RSVD_MSC_31TO8 register field. */
3336 #define ALT_UART_MSR_RSVD_MSC_31TO8_MSB 31
3337 /* The width in bits of the ALT_UART_MSR_RSVD_MSC_31TO8 register field. */
3338 #define ALT_UART_MSR_RSVD_MSC_31TO8_WIDTH 24
3339 /* The mask used to set the ALT_UART_MSR_RSVD_MSC_31TO8 register field value. */
3340 #define ALT_UART_MSR_RSVD_MSC_31TO8_SET_MSK 0xffffff00
3341 /* The mask used to clear the ALT_UART_MSR_RSVD_MSC_31TO8 register field value. */
3342 #define ALT_UART_MSR_RSVD_MSC_31TO8_CLR_MSK 0x000000ff
3343 /* The reset value of the ALT_UART_MSR_RSVD_MSC_31TO8 register field. */
3344 #define ALT_UART_MSR_RSVD_MSC_31TO8_RESET 0x0
3345 /* Extracts the ALT_UART_MSR_RSVD_MSC_31TO8 field value from a register. */
3346 #define ALT_UART_MSR_RSVD_MSC_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3347 /* Produces a ALT_UART_MSR_RSVD_MSC_31TO8 register field value suitable for setting the register. */
3348 #define ALT_UART_MSR_RSVD_MSC_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3349 
3350 #ifndef __ASSEMBLY__
3351 /*
3352  * WARNING: The C register and register group struct declarations are provided for
3353  * convenience and illustrative purposes. They should, however, be used with
3354  * caution as the C language standard provides no guarantees about the alignment or
3355  * atomicity of device memory accesses. The recommended practice for writing
3356  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3357  * alt_write_word() functions.
3358  *
3359  * The struct declaration for register ALT_UART_MSR.
3360  */
3361 struct ALT_UART_MSR_s
3362 {
3363  const uint32_t dcts : 1; /* ALT_UART_MSR_DCTS */
3364  const uint32_t ddsr : 1; /* ALT_UART_MSR_DDSR */
3365  const uint32_t teri : 1; /* ALT_UART_MSR_TERI */
3366  const uint32_t ddcd : 1; /* ALT_UART_MSR_DDCD */
3367  const uint32_t cts : 1; /* ALT_UART_MSR_CTS */
3368  const uint32_t dsr : 1; /* ALT_UART_MSR_DSR */
3369  const uint32_t ri : 1; /* ALT_UART_MSR_RI */
3370  const uint32_t dcd : 1; /* ALT_UART_MSR_DCD */
3371  const uint32_t rsvd_msc_31to8 : 24; /* ALT_UART_MSR_RSVD_MSC_31TO8 */
3372 };
3373 
3374 /* The typedef declaration for register ALT_UART_MSR. */
3375 typedef volatile struct ALT_UART_MSR_s ALT_UART_MSR_t;
3376 #endif /* __ASSEMBLY__ */
3377 
3378 /* The reset value of the ALT_UART_MSR register. */
3379 #define ALT_UART_MSR_RESET 0x00000000
3380 /* The byte offset of the ALT_UART_MSR register from the beginning of the component. */
3381 #define ALT_UART_MSR_OFST 0x18
3382 /* The address of the ALT_UART_MSR register. */
3383 #define ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST))
3384 
3385 /*
3386  * Register : scr
3387  *
3388  * Scratchpad Register
3389  *
3390  * Register Layout
3391  *
3392  * Bits | Access | Reset | Description
3393  * :-------|:-------|:------|:----------------------------
3394  * [7:0] | RW | 0x0 | ALT_UART_SCR_SCR
3395  * [31:8] | R | 0x0 | ALT_UART_SCR_RSVD_SCR_31TO8
3396  *
3397  */
3398 /*
3399  * Field : scr
3400  *
3401  * This register is for programmers to use as a temporary storage space. It has no
3402  *
3403  * defined purpose in the DW_apb_uart.
3404  *
3405  * Field Access Macros:
3406  *
3407  */
3408 /* The Least Significant Bit (LSB) position of the ALT_UART_SCR_SCR register field. */
3409 #define ALT_UART_SCR_SCR_LSB 0
3410 /* The Most Significant Bit (MSB) position of the ALT_UART_SCR_SCR register field. */
3411 #define ALT_UART_SCR_SCR_MSB 7
3412 /* The width in bits of the ALT_UART_SCR_SCR register field. */
3413 #define ALT_UART_SCR_SCR_WIDTH 8
3414 /* The mask used to set the ALT_UART_SCR_SCR register field value. */
3415 #define ALT_UART_SCR_SCR_SET_MSK 0x000000ff
3416 /* The mask used to clear the ALT_UART_SCR_SCR register field value. */
3417 #define ALT_UART_SCR_SCR_CLR_MSK 0xffffff00
3418 /* The reset value of the ALT_UART_SCR_SCR register field. */
3419 #define ALT_UART_SCR_SCR_RESET 0x0
3420 /* Extracts the ALT_UART_SCR_SCR field value from a register. */
3421 #define ALT_UART_SCR_SCR_GET(value) (((value) & 0x000000ff) >> 0)
3422 /* Produces a ALT_UART_SCR_SCR register field value suitable for setting the register. */
3423 #define ALT_UART_SCR_SCR_SET(value) (((value) << 0) & 0x000000ff)
3424 
3425 /*
3426  * Field : rsvd_scr_31to8
3427  *
3428  * Reserved bits [31:8] - Read Only
3429  *
3430  * Field Access Macros:
3431  *
3432  */
3433 /* The Least Significant Bit (LSB) position of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3434 #define ALT_UART_SCR_RSVD_SCR_31TO8_LSB 8
3435 /* The Most Significant Bit (MSB) position of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3436 #define ALT_UART_SCR_RSVD_SCR_31TO8_MSB 31
3437 /* The width in bits of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3438 #define ALT_UART_SCR_RSVD_SCR_31TO8_WIDTH 24
3439 /* The mask used to set the ALT_UART_SCR_RSVD_SCR_31TO8 register field value. */
3440 #define ALT_UART_SCR_RSVD_SCR_31TO8_SET_MSK 0xffffff00
3441 /* The mask used to clear the ALT_UART_SCR_RSVD_SCR_31TO8 register field value. */
3442 #define ALT_UART_SCR_RSVD_SCR_31TO8_CLR_MSK 0x000000ff
3443 /* The reset value of the ALT_UART_SCR_RSVD_SCR_31TO8 register field. */
3444 #define ALT_UART_SCR_RSVD_SCR_31TO8_RESET 0x0
3445 /* Extracts the ALT_UART_SCR_RSVD_SCR_31TO8 field value from a register. */
3446 #define ALT_UART_SCR_RSVD_SCR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3447 /* Produces a ALT_UART_SCR_RSVD_SCR_31TO8 register field value suitable for setting the register. */
3448 #define ALT_UART_SCR_RSVD_SCR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3449 
3450 #ifndef __ASSEMBLY__
3451 /*
3452  * WARNING: The C register and register group struct declarations are provided for
3453  * convenience and illustrative purposes. They should, however, be used with
3454  * caution as the C language standard provides no guarantees about the alignment or
3455  * atomicity of device memory accesses. The recommended practice for writing
3456  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3457  * alt_write_word() functions.
3458  *
3459  * The struct declaration for register ALT_UART_SCR.
3460  */
3461 struct ALT_UART_SCR_s
3462 {
3463  uint32_t scr : 8; /* ALT_UART_SCR_SCR */
3464  const uint32_t rsvd_scr_31to8 : 24; /* ALT_UART_SCR_RSVD_SCR_31TO8 */
3465 };
3466 
3467 /* The typedef declaration for register ALT_UART_SCR. */
3468 typedef volatile struct ALT_UART_SCR_s ALT_UART_SCR_t;
3469 #endif /* __ASSEMBLY__ */
3470 
3471 /* The reset value of the ALT_UART_SCR register. */
3472 #define ALT_UART_SCR_RESET 0x00000000
3473 /* The byte offset of the ALT_UART_SCR register from the beginning of the component. */
3474 #define ALT_UART_SCR_OFST 0x1c
3475 /* The address of the ALT_UART_SCR register. */
3476 #define ALT_UART_SCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SCR_OFST))
3477 
3478 /*
3479  * Register : Shadow RBR and THR - srbr_sthr_0
3480  *
3481  * This is multi-function register. It is shadow register for Receive Buffer
3482  * Register and Transmit Holding Register.
3483  *
3484  * Register Layout
3485  *
3486  * Bits | Access | Reset | Description
3487  * :-------|:-------|:------|:-------------------------------------
3488  * [7:0] | R | 0x0 | ALT_UART_SRBR_SRBR_STHR_0
3489  * [31:8] | R | 0x0 | ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8
3490  *
3491  */
3492 /*
3493  * Field : srbr_sthr_0
3494  *
3495  * This is shadow register for RBR and THR and has been allocated sixteen 32-bit
3496  * locations so as to accomodate burst accesses from the master.
3497  *
3498  * srbr :
3499  *
3500  * This register contains the data byte received on the serial input port (sin) in
3501  * UART mode or the serial infrared input (sir_in) in infrared mode. The data in
3502  * this register is valid only if the Data Ready (DR) bit in the Line status
3503  * Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are
3504  * disabled (FCR[0] set to zero), the data in the RBR must be read before the next
3505  * data arrives, otherwise it is overwritten, resulting in an overrun error. If in
3506  * FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this
3507  * register accesses the head of the receive FIFO. If the receive FIFO is full and
3508  * this register is not read before the next data character arrives, then the data
3509  * already in the FIFO are preserved, but any incoming data is lost. An overrun
3510  * error also occurs.
3511  *
3512  * sthr:
3513  *
3514  * This register contains data to be transmitted on the serial output port (sout)
3515  * in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data
3516  * should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set.
3517  * If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set,
3518  * writing a single character to the THR clears the THRE. Any additional writes to
3519  * the THR before the THRE is set again causes the THR data to be overwritten. If
3520  * in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number
3521  * of characters of data may be written to the THR before the FIFO is full. The
3522  * number x (default=16) is determined by the value of FIFO Depth that you set
3523  * during configuration. Any attempt to write data when the FIFO is full results in
3524  * the write data being lost.
3525  *
3526  * Field Access Macros:
3527  *
3528  */
3529 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR_STHR_0 register field. */
3530 #define ALT_UART_SRBR_SRBR_STHR_0_LSB 0
3531 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR_STHR_0 register field. */
3532 #define ALT_UART_SRBR_SRBR_STHR_0_MSB 7
3533 /* The width in bits of the ALT_UART_SRBR_SRBR_STHR_0 register field. */
3534 #define ALT_UART_SRBR_SRBR_STHR_0_WIDTH 8
3535 /* The mask used to set the ALT_UART_SRBR_SRBR_STHR_0 register field value. */
3536 #define ALT_UART_SRBR_SRBR_STHR_0_SET_MSK 0x000000ff
3537 /* The mask used to clear the ALT_UART_SRBR_SRBR_STHR_0 register field value. */
3538 #define ALT_UART_SRBR_SRBR_STHR_0_CLR_MSK 0xffffff00
3539 /* The reset value of the ALT_UART_SRBR_SRBR_STHR_0 register field. */
3540 #define ALT_UART_SRBR_SRBR_STHR_0_RESET 0x0
3541 /* Extracts the ALT_UART_SRBR_SRBR_STHR_0 field value from a register. */
3542 #define ALT_UART_SRBR_SRBR_STHR_0_GET(value) (((value) & 0x000000ff) >> 0)
3543 /* Produces a ALT_UART_SRBR_SRBR_STHR_0 register field value suitable for setting the register. */
3544 #define ALT_UART_SRBR_SRBR_STHR_0_SET(value) (((value) << 0) & 0x000000ff)
3545 
3546 /*
3547  * Field : rsvd_srbr_sthr_0_31to8
3548  *
3549  * Reserved bits [31:8] - Read Only
3550  *
3551  * Field Access Macros:
3552  *
3553  */
3554 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field. */
3555 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_LSB 8
3556 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field. */
3557 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_MSB 31
3558 /* The width in bits of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field. */
3559 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_WIDTH 24
3560 /* The mask used to set the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value. */
3561 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET_MSK 0xffffff00
3562 /* The mask used to clear the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value. */
3563 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_CLR_MSK 0x000000ff
3564 /* The reset value of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field. */
3565 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_RESET 0x0
3566 /* Extracts the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 field value from a register. */
3567 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3568 /* Produces a ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value suitable for setting the register. */
3569 #define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3570 
3571 #ifndef __ASSEMBLY__
3572 /*
3573  * WARNING: The C register and register group struct declarations are provided for
3574  * convenience and illustrative purposes. They should, however, be used with
3575  * caution as the C language standard provides no guarantees about the alignment or
3576  * atomicity of device memory accesses. The recommended practice for writing
3577  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3578  * alt_write_word() functions.
3579  *
3580  * The struct declaration for register ALT_UART_SRBR.
3581  */
3582 struct ALT_UART_SRBR_s
3583 {
3584  const uint32_t srbr_sthr_0 : 8; /* ALT_UART_SRBR_SRBR_STHR_0 */
3585  const uint32_t rsvd_srbr_sthr_0_31to8 : 24; /* ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 */
3586 };
3587 
3588 /* The typedef declaration for register ALT_UART_SRBR. */
3589 typedef volatile struct ALT_UART_SRBR_s ALT_UART_SRBR_t;
3590 #endif /* __ASSEMBLY__ */
3591 
3592 /* The reset value of the ALT_UART_SRBR register. */
3593 #define ALT_UART_SRBR_RESET 0x00000000
3594 /* The byte offset of the ALT_UART_SRBR register from the beginning of the component. */
3595 #define ALT_UART_SRBR_OFST 0x30
3596 /* The address of the ALT_UART_SRBR register. */
3597 #define ALT_UART_SRBR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))
3598 
3599 /*
3600  * Register : Shadow RBR and THR - srbr_sthr_1
3601  *
3602  * This is multi-function register. It is shadow register for Receive Buffer
3603  * Register and Transmit Holding Register.
3604  *
3605  * Register Layout
3606  *
3607  * Bits | Access | Reset | Description
3608  * :-------|:-------|:------|:--------------------------------------------
3609  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_1_SRBR_STHR_1
3610  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8
3611  *
3612  */
3613 /*
3614  * Field : srbr_sthr_1
3615  *
3616  * See srbr_sthr_0 description
3617  *
3618  * Field Access Macros:
3619  *
3620  */
3621 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field. */
3622 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_LSB 0
3623 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field. */
3624 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_MSB 7
3625 /* The width in bits of the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field. */
3626 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_WIDTH 8
3627 /* The mask used to set the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field value. */
3628 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_SET_MSK 0x000000ff
3629 /* The mask used to clear the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field value. */
3630 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_CLR_MSK 0xffffff00
3631 /* The reset value of the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field. */
3632 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_RESET 0x0
3633 /* Extracts the ALT_UART_SRBR_STHR_1_SRBR_STHR_1 field value from a register. */
3634 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_GET(value) (((value) & 0x000000ff) >> 0)
3635 /* Produces a ALT_UART_SRBR_STHR_1_SRBR_STHR_1 register field value suitable for setting the register. */
3636 #define ALT_UART_SRBR_STHR_1_SRBR_STHR_1_SET(value) (((value) << 0) & 0x000000ff)
3637 
3638 /*
3639  * Field : rsvd_srbr_sthr_1_31to8
3640  *
3641  * Reserved bits [31:8] - Read Only
3642  *
3643  * Field Access Macros:
3644  *
3645  */
3646 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field. */
3647 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_LSB 8
3648 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field. */
3649 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_MSB 31
3650 /* The width in bits of the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field. */
3651 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_WIDTH 24
3652 /* The mask used to set the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field value. */
3653 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_SET_MSK 0xffffff00
3654 /* The mask used to clear the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field value. */
3655 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_CLR_MSK 0x000000ff
3656 /* The reset value of the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field. */
3657 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_RESET 0x0
3658 /* Extracts the ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 field value from a register. */
3659 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3660 /* Produces a ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 register field value suitable for setting the register. */
3661 #define ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3662 
3663 #ifndef __ASSEMBLY__
3664 /*
3665  * WARNING: The C register and register group struct declarations are provided for
3666  * convenience and illustrative purposes. They should, however, be used with
3667  * caution as the C language standard provides no guarantees about the alignment or
3668  * atomicity of device memory accesses. The recommended practice for writing
3669  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3670  * alt_write_word() functions.
3671  *
3672  * The struct declaration for register ALT_UART_SRBR_STHR_1.
3673  */
3674 struct ALT_UART_SRBR_STHR_1_s
3675 {
3676  const uint32_t srbr_sthr_1 : 8; /* ALT_UART_SRBR_STHR_1_SRBR_STHR_1 */
3677  const uint32_t rsvd_srbr_sthr_1_31to8 : 24; /* ALT_UART_SRBR_STHR_1_RSVD_SRBR_STHR_1_31TO8 */
3678 };
3679 
3680 /* The typedef declaration for register ALT_UART_SRBR_STHR_1. */
3681 typedef volatile struct ALT_UART_SRBR_STHR_1_s ALT_UART_SRBR_STHR_1_t;
3682 #endif /* __ASSEMBLY__ */
3683 
3684 /* The reset value of the ALT_UART_SRBR_STHR_1 register. */
3685 #define ALT_UART_SRBR_STHR_1_RESET 0x00000000
3686 /* The byte offset of the ALT_UART_SRBR_STHR_1 register from the beginning of the component. */
3687 #define ALT_UART_SRBR_STHR_1_OFST 0x34
3688 /* The address of the ALT_UART_SRBR_STHR_1 register. */
3689 #define ALT_UART_SRBR_STHR_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_1_OFST))
3690 
3691 /*
3692  * Register : Shadow RBR and THR - srbr_sthr_2
3693  *
3694  * This is multi-function register. It is shadow register for Receive Buffer
3695  * Register and Transmit Holding Register.
3696  *
3697  * Register Layout
3698  *
3699  * Bits | Access | Reset | Description
3700  * :-------|:-------|:------|:--------------------------------------------
3701  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_2_SRBR_STHR_2
3702  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8
3703  *
3704  */
3705 /*
3706  * Field : srbr_sthr_2
3707  *
3708  * See srbr_sthr_0 description
3709  *
3710  * Field Access Macros:
3711  *
3712  */
3713 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field. */
3714 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_LSB 0
3715 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field. */
3716 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_MSB 7
3717 /* The width in bits of the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field. */
3718 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_WIDTH 8
3719 /* The mask used to set the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field value. */
3720 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_SET_MSK 0x000000ff
3721 /* The mask used to clear the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field value. */
3722 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_CLR_MSK 0xffffff00
3723 /* The reset value of the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field. */
3724 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_RESET 0x0
3725 /* Extracts the ALT_UART_SRBR_STHR_2_SRBR_STHR_2 field value from a register. */
3726 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_GET(value) (((value) & 0x000000ff) >> 0)
3727 /* Produces a ALT_UART_SRBR_STHR_2_SRBR_STHR_2 register field value suitable for setting the register. */
3728 #define ALT_UART_SRBR_STHR_2_SRBR_STHR_2_SET(value) (((value) << 0) & 0x000000ff)
3729 
3730 /*
3731  * Field : rsvd_srbr_sthr_2_31to8
3732  *
3733  * Reserved bits [31:8] - Read Only
3734  *
3735  * Field Access Macros:
3736  *
3737  */
3738 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field. */
3739 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_LSB 8
3740 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field. */
3741 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_MSB 31
3742 /* The width in bits of the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field. */
3743 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_WIDTH 24
3744 /* The mask used to set the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field value. */
3745 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_SET_MSK 0xffffff00
3746 /* The mask used to clear the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field value. */
3747 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_CLR_MSK 0x000000ff
3748 /* The reset value of the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field. */
3749 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_RESET 0x0
3750 /* Extracts the ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 field value from a register. */
3751 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3752 /* Produces a ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 register field value suitable for setting the register. */
3753 #define ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3754 
3755 #ifndef __ASSEMBLY__
3756 /*
3757  * WARNING: The C register and register group struct declarations are provided for
3758  * convenience and illustrative purposes. They should, however, be used with
3759  * caution as the C language standard provides no guarantees about the alignment or
3760  * atomicity of device memory accesses. The recommended practice for writing
3761  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3762  * alt_write_word() functions.
3763  *
3764  * The struct declaration for register ALT_UART_SRBR_STHR_2.
3765  */
3766 struct ALT_UART_SRBR_STHR_2_s
3767 {
3768  const uint32_t srbr_sthr_2 : 8; /* ALT_UART_SRBR_STHR_2_SRBR_STHR_2 */
3769  const uint32_t rsvd_srbr_sthr_2_31to8 : 24; /* ALT_UART_SRBR_STHR_2_RSVD_SRBR_STHR_2_31TO8 */
3770 };
3771 
3772 /* The typedef declaration for register ALT_UART_SRBR_STHR_2. */
3773 typedef volatile struct ALT_UART_SRBR_STHR_2_s ALT_UART_SRBR_STHR_2_t;
3774 #endif /* __ASSEMBLY__ */
3775 
3776 /* The reset value of the ALT_UART_SRBR_STHR_2 register. */
3777 #define ALT_UART_SRBR_STHR_2_RESET 0x00000000
3778 /* The byte offset of the ALT_UART_SRBR_STHR_2 register from the beginning of the component. */
3779 #define ALT_UART_SRBR_STHR_2_OFST 0x38
3780 /* The address of the ALT_UART_SRBR_STHR_2 register. */
3781 #define ALT_UART_SRBR_STHR_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_2_OFST))
3782 
3783 /*
3784  * Register : Shadow RBR and THR - srbr_sthr_3
3785  *
3786  * This is multi-function register. It is shadow register for Receive Buffer
3787  * Register and Transmit Holding Register.
3788  *
3789  * Register Layout
3790  *
3791  * Bits | Access | Reset | Description
3792  * :-------|:-------|:------|:--------------------------------------------
3793  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_3_SRBR_STHR_3
3794  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8
3795  *
3796  */
3797 /*
3798  * Field : srbr_sthr_3
3799  *
3800  * See srbr_sthr_0 description
3801  *
3802  * Field Access Macros:
3803  *
3804  */
3805 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field. */
3806 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_LSB 0
3807 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field. */
3808 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_MSB 7
3809 /* The width in bits of the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field. */
3810 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_WIDTH 8
3811 /* The mask used to set the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field value. */
3812 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_SET_MSK 0x000000ff
3813 /* The mask used to clear the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field value. */
3814 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_CLR_MSK 0xffffff00
3815 /* The reset value of the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field. */
3816 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_RESET 0x0
3817 /* Extracts the ALT_UART_SRBR_STHR_3_SRBR_STHR_3 field value from a register. */
3818 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_GET(value) (((value) & 0x000000ff) >> 0)
3819 /* Produces a ALT_UART_SRBR_STHR_3_SRBR_STHR_3 register field value suitable for setting the register. */
3820 #define ALT_UART_SRBR_STHR_3_SRBR_STHR_3_SET(value) (((value) << 0) & 0x000000ff)
3821 
3822 /*
3823  * Field : rsvd_srbr_sthr_3_31to8
3824  *
3825  * Reserved bits [31:8] - Read Only
3826  *
3827  * Field Access Macros:
3828  *
3829  */
3830 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field. */
3831 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_LSB 8
3832 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field. */
3833 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_MSB 31
3834 /* The width in bits of the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field. */
3835 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_WIDTH 24
3836 /* The mask used to set the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field value. */
3837 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_SET_MSK 0xffffff00
3838 /* The mask used to clear the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field value. */
3839 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_CLR_MSK 0x000000ff
3840 /* The reset value of the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field. */
3841 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_RESET 0x0
3842 /* Extracts the ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 field value from a register. */
3843 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3844 /* Produces a ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 register field value suitable for setting the register. */
3845 #define ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3846 
3847 #ifndef __ASSEMBLY__
3848 /*
3849  * WARNING: The C register and register group struct declarations are provided for
3850  * convenience and illustrative purposes. They should, however, be used with
3851  * caution as the C language standard provides no guarantees about the alignment or
3852  * atomicity of device memory accesses. The recommended practice for writing
3853  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3854  * alt_write_word() functions.
3855  *
3856  * The struct declaration for register ALT_UART_SRBR_STHR_3.
3857  */
3858 struct ALT_UART_SRBR_STHR_3_s
3859 {
3860  const uint32_t srbr_sthr_3 : 8; /* ALT_UART_SRBR_STHR_3_SRBR_STHR_3 */
3861  const uint32_t rsvd_srbr_sthr_3_31to8 : 24; /* ALT_UART_SRBR_STHR_3_RSVD_SRBR_STHR_3_31TO8 */
3862 };
3863 
3864 /* The typedef declaration for register ALT_UART_SRBR_STHR_3. */
3865 typedef volatile struct ALT_UART_SRBR_STHR_3_s ALT_UART_SRBR_STHR_3_t;
3866 #endif /* __ASSEMBLY__ */
3867 
3868 /* The reset value of the ALT_UART_SRBR_STHR_3 register. */
3869 #define ALT_UART_SRBR_STHR_3_RESET 0x00000000
3870 /* The byte offset of the ALT_UART_SRBR_STHR_3 register from the beginning of the component. */
3871 #define ALT_UART_SRBR_STHR_3_OFST 0x3c
3872 /* The address of the ALT_UART_SRBR_STHR_3 register. */
3873 #define ALT_UART_SRBR_STHR_3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_3_OFST))
3874 
3875 /*
3876  * Register : Shadow RBR and THR - srbr_sthr_4
3877  *
3878  * This is multi-function register. It is shadow register for Receive Buffer
3879  * Register and Transmit Holding Register.
3880  *
3881  * Register Layout
3882  *
3883  * Bits | Access | Reset | Description
3884  * :-------|:-------|:------|:--------------------------------------------
3885  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_4_SRBR_STHR_4
3886  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8
3887  *
3888  */
3889 /*
3890  * Field : srbr_sthr_4
3891  *
3892  * See srbr_sthr_0 description
3893  *
3894  * Field Access Macros:
3895  *
3896  */
3897 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field. */
3898 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_LSB 0
3899 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field. */
3900 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_MSB 7
3901 /* The width in bits of the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field. */
3902 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_WIDTH 8
3903 /* The mask used to set the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field value. */
3904 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_SET_MSK 0x000000ff
3905 /* The mask used to clear the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field value. */
3906 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_CLR_MSK 0xffffff00
3907 /* The reset value of the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field. */
3908 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_RESET 0x0
3909 /* Extracts the ALT_UART_SRBR_STHR_4_SRBR_STHR_4 field value from a register. */
3910 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_GET(value) (((value) & 0x000000ff) >> 0)
3911 /* Produces a ALT_UART_SRBR_STHR_4_SRBR_STHR_4 register field value suitable for setting the register. */
3912 #define ALT_UART_SRBR_STHR_4_SRBR_STHR_4_SET(value) (((value) << 0) & 0x000000ff)
3913 
3914 /*
3915  * Field : rsvd_srbr_sthr_4_31to8
3916  *
3917  * Reserved bits [31:8] - Read Only
3918  *
3919  * Field Access Macros:
3920  *
3921  */
3922 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field. */
3923 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_LSB 8
3924 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field. */
3925 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_MSB 31
3926 /* The width in bits of the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field. */
3927 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_WIDTH 24
3928 /* The mask used to set the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field value. */
3929 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_SET_MSK 0xffffff00
3930 /* The mask used to clear the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field value. */
3931 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_CLR_MSK 0x000000ff
3932 /* The reset value of the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field. */
3933 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_RESET 0x0
3934 /* Extracts the ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 field value from a register. */
3935 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
3936 /* Produces a ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 register field value suitable for setting the register. */
3937 #define ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8_SET(value) (((value) << 8) & 0xffffff00)
3938 
3939 #ifndef __ASSEMBLY__
3940 /*
3941  * WARNING: The C register and register group struct declarations are provided for
3942  * convenience and illustrative purposes. They should, however, be used with
3943  * caution as the C language standard provides no guarantees about the alignment or
3944  * atomicity of device memory accesses. The recommended practice for writing
3945  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3946  * alt_write_word() functions.
3947  *
3948  * The struct declaration for register ALT_UART_SRBR_STHR_4.
3949  */
3950 struct ALT_UART_SRBR_STHR_4_s
3951 {
3952  const uint32_t srbr_sthr_4 : 8; /* ALT_UART_SRBR_STHR_4_SRBR_STHR_4 */
3953  const uint32_t rsvd_srbr_sthr_4_31to8 : 24; /* ALT_UART_SRBR_STHR_4_RSVD_SRBR_STHR_4_31TO8 */
3954 };
3955 
3956 /* The typedef declaration for register ALT_UART_SRBR_STHR_4. */
3957 typedef volatile struct ALT_UART_SRBR_STHR_4_s ALT_UART_SRBR_STHR_4_t;
3958 #endif /* __ASSEMBLY__ */
3959 
3960 /* The reset value of the ALT_UART_SRBR_STHR_4 register. */
3961 #define ALT_UART_SRBR_STHR_4_RESET 0x00000000
3962 /* The byte offset of the ALT_UART_SRBR_STHR_4 register from the beginning of the component. */
3963 #define ALT_UART_SRBR_STHR_4_OFST 0x40
3964 /* The address of the ALT_UART_SRBR_STHR_4 register. */
3965 #define ALT_UART_SRBR_STHR_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_4_OFST))
3966 
3967 /*
3968  * Register : Shadow RBR and THR - srbr_sthr_5
3969  *
3970  * This is multi-function register. It is shadow register for Receive Buffer
3971  * Register and Transmit Holding Register.
3972  *
3973  * Register Layout
3974  *
3975  * Bits | Access | Reset | Description
3976  * :-------|:-------|:------|:--------------------------------------------
3977  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_5_SRBR_STHR_5
3978  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8
3979  *
3980  */
3981 /*
3982  * Field : srbr_sthr_5
3983  *
3984  * See srbr_sthr_0 description
3985  *
3986  * Field Access Macros:
3987  *
3988  */
3989 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field. */
3990 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_LSB 0
3991 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field. */
3992 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_MSB 7
3993 /* The width in bits of the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field. */
3994 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_WIDTH 8
3995 /* The mask used to set the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field value. */
3996 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_SET_MSK 0x000000ff
3997 /* The mask used to clear the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field value. */
3998 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_CLR_MSK 0xffffff00
3999 /* The reset value of the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field. */
4000 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_RESET 0x0
4001 /* Extracts the ALT_UART_SRBR_STHR_5_SRBR_STHR_5 field value from a register. */
4002 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_GET(value) (((value) & 0x000000ff) >> 0)
4003 /* Produces a ALT_UART_SRBR_STHR_5_SRBR_STHR_5 register field value suitable for setting the register. */
4004 #define ALT_UART_SRBR_STHR_5_SRBR_STHR_5_SET(value) (((value) << 0) & 0x000000ff)
4005 
4006 /*
4007  * Field : rsvd_srbr_sthr_5_31to8
4008  *
4009  * Reserved bits [31:8] - Read Only
4010  *
4011  * Field Access Macros:
4012  *
4013  */
4014 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field. */
4015 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_LSB 8
4016 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field. */
4017 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_MSB 31
4018 /* The width in bits of the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field. */
4019 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_WIDTH 24
4020 /* The mask used to set the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field value. */
4021 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_SET_MSK 0xffffff00
4022 /* The mask used to clear the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field value. */
4023 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_CLR_MSK 0x000000ff
4024 /* The reset value of the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field. */
4025 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_RESET 0x0
4026 /* Extracts the ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 field value from a register. */
4027 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4028 /* Produces a ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 register field value suitable for setting the register. */
4029 #define ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4030 
4031 #ifndef __ASSEMBLY__
4032 /*
4033  * WARNING: The C register and register group struct declarations are provided for
4034  * convenience and illustrative purposes. They should, however, be used with
4035  * caution as the C language standard provides no guarantees about the alignment or
4036  * atomicity of device memory accesses. The recommended practice for writing
4037  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4038  * alt_write_word() functions.
4039  *
4040  * The struct declaration for register ALT_UART_SRBR_STHR_5.
4041  */
4042 struct ALT_UART_SRBR_STHR_5_s
4043 {
4044  const uint32_t srbr_sthr_5 : 8; /* ALT_UART_SRBR_STHR_5_SRBR_STHR_5 */
4045  const uint32_t rsvd_srbr_sthr_5_31to8 : 24; /* ALT_UART_SRBR_STHR_5_RSVD_SRBR_STHR_5_31TO8 */
4046 };
4047 
4048 /* The typedef declaration for register ALT_UART_SRBR_STHR_5. */
4049 typedef volatile struct ALT_UART_SRBR_STHR_5_s ALT_UART_SRBR_STHR_5_t;
4050 #endif /* __ASSEMBLY__ */
4051 
4052 /* The reset value of the ALT_UART_SRBR_STHR_5 register. */
4053 #define ALT_UART_SRBR_STHR_5_RESET 0x00000000
4054 /* The byte offset of the ALT_UART_SRBR_STHR_5 register from the beginning of the component. */
4055 #define ALT_UART_SRBR_STHR_5_OFST 0x44
4056 /* The address of the ALT_UART_SRBR_STHR_5 register. */
4057 #define ALT_UART_SRBR_STHR_5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_5_OFST))
4058 
4059 /*
4060  * Register : Shadow RBR and THR - srbr_sthr_6
4061  *
4062  * This is multi-function register. It is shadow register for Receive Buffer
4063  * Register and Transmit Holding Register.
4064  *
4065  * Register Layout
4066  *
4067  * Bits | Access | Reset | Description
4068  * :-------|:-------|:------|:--------------------------------------------
4069  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_6_SRBR_STHR_6
4070  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8
4071  *
4072  */
4073 /*
4074  * Field : srbr_sthr_6
4075  *
4076  * See srbr_sthr_0 description
4077  *
4078  * Field Access Macros:
4079  *
4080  */
4081 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field. */
4082 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_LSB 0
4083 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field. */
4084 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_MSB 7
4085 /* The width in bits of the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field. */
4086 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_WIDTH 8
4087 /* The mask used to set the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field value. */
4088 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_SET_MSK 0x000000ff
4089 /* The mask used to clear the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field value. */
4090 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_CLR_MSK 0xffffff00
4091 /* The reset value of the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field. */
4092 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_RESET 0x0
4093 /* Extracts the ALT_UART_SRBR_STHR_6_SRBR_STHR_6 field value from a register. */
4094 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_GET(value) (((value) & 0x000000ff) >> 0)
4095 /* Produces a ALT_UART_SRBR_STHR_6_SRBR_STHR_6 register field value suitable for setting the register. */
4096 #define ALT_UART_SRBR_STHR_6_SRBR_STHR_6_SET(value) (((value) << 0) & 0x000000ff)
4097 
4098 /*
4099  * Field : rsvd_srbr_sthr_6_31to8
4100  *
4101  * Reserved bits [31:8] - Read Only
4102  *
4103  * Field Access Macros:
4104  *
4105  */
4106 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field. */
4107 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_LSB 8
4108 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field. */
4109 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_MSB 31
4110 /* The width in bits of the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field. */
4111 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_WIDTH 24
4112 /* The mask used to set the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field value. */
4113 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_SET_MSK 0xffffff00
4114 /* The mask used to clear the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field value. */
4115 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_CLR_MSK 0x000000ff
4116 /* The reset value of the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field. */
4117 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_RESET 0x0
4118 /* Extracts the ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 field value from a register. */
4119 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4120 /* Produces a ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 register field value suitable for setting the register. */
4121 #define ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4122 
4123 #ifndef __ASSEMBLY__
4124 /*
4125  * WARNING: The C register and register group struct declarations are provided for
4126  * convenience and illustrative purposes. They should, however, be used with
4127  * caution as the C language standard provides no guarantees about the alignment or
4128  * atomicity of device memory accesses. The recommended practice for writing
4129  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4130  * alt_write_word() functions.
4131  *
4132  * The struct declaration for register ALT_UART_SRBR_STHR_6.
4133  */
4134 struct ALT_UART_SRBR_STHR_6_s
4135 {
4136  const uint32_t srbr_sthr_6 : 8; /* ALT_UART_SRBR_STHR_6_SRBR_STHR_6 */
4137  const uint32_t rsvd_srbr_sthr_6_31to8 : 24; /* ALT_UART_SRBR_STHR_6_RSVD_SRBR_STHR_6_31TO8 */
4138 };
4139 
4140 /* The typedef declaration for register ALT_UART_SRBR_STHR_6. */
4141 typedef volatile struct ALT_UART_SRBR_STHR_6_s ALT_UART_SRBR_STHR_6_t;
4142 #endif /* __ASSEMBLY__ */
4143 
4144 /* The reset value of the ALT_UART_SRBR_STHR_6 register. */
4145 #define ALT_UART_SRBR_STHR_6_RESET 0x00000000
4146 /* The byte offset of the ALT_UART_SRBR_STHR_6 register from the beginning of the component. */
4147 #define ALT_UART_SRBR_STHR_6_OFST 0x48
4148 /* The address of the ALT_UART_SRBR_STHR_6 register. */
4149 #define ALT_UART_SRBR_STHR_6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_6_OFST))
4150 
4151 /*
4152  * Register : Shadow RBR and THR - srbr_sthr_7
4153  *
4154  * This is multi-function register. It is shadow register for Receive Buffer
4155  * Register and Transmit Holding Register.
4156  *
4157  * Register Layout
4158  *
4159  * Bits | Access | Reset | Description
4160  * :-------|:-------|:------|:--------------------------------------------
4161  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_7_SRBR_STHR_7
4162  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8
4163  *
4164  */
4165 /*
4166  * Field : srbr_sthr_7
4167  *
4168  * See srbr_sthr_0 description
4169  *
4170  * Field Access Macros:
4171  *
4172  */
4173 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field. */
4174 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_LSB 0
4175 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field. */
4176 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_MSB 7
4177 /* The width in bits of the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field. */
4178 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_WIDTH 8
4179 /* The mask used to set the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field value. */
4180 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_SET_MSK 0x000000ff
4181 /* The mask used to clear the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field value. */
4182 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_CLR_MSK 0xffffff00
4183 /* The reset value of the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field. */
4184 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_RESET 0x0
4185 /* Extracts the ALT_UART_SRBR_STHR_7_SRBR_STHR_7 field value from a register. */
4186 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_GET(value) (((value) & 0x000000ff) >> 0)
4187 /* Produces a ALT_UART_SRBR_STHR_7_SRBR_STHR_7 register field value suitable for setting the register. */
4188 #define ALT_UART_SRBR_STHR_7_SRBR_STHR_7_SET(value) (((value) << 0) & 0x000000ff)
4189 
4190 /*
4191  * Field : rsvd_srbr_sthr_7_31to8
4192  *
4193  * Reserved bits [31:8] - Read Only
4194  *
4195  * Field Access Macros:
4196  *
4197  */
4198 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field. */
4199 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_LSB 8
4200 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field. */
4201 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_MSB 31
4202 /* The width in bits of the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field. */
4203 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_WIDTH 24
4204 /* The mask used to set the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field value. */
4205 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_SET_MSK 0xffffff00
4206 /* The mask used to clear the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field value. */
4207 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_CLR_MSK 0x000000ff
4208 /* The reset value of the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field. */
4209 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_RESET 0x0
4210 /* Extracts the ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 field value from a register. */
4211 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4212 /* Produces a ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 register field value suitable for setting the register. */
4213 #define ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4214 
4215 #ifndef __ASSEMBLY__
4216 /*
4217  * WARNING: The C register and register group struct declarations are provided for
4218  * convenience and illustrative purposes. They should, however, be used with
4219  * caution as the C language standard provides no guarantees about the alignment or
4220  * atomicity of device memory accesses. The recommended practice for writing
4221  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4222  * alt_write_word() functions.
4223  *
4224  * The struct declaration for register ALT_UART_SRBR_STHR_7.
4225  */
4226 struct ALT_UART_SRBR_STHR_7_s
4227 {
4228  const uint32_t srbr_sthr_7 : 8; /* ALT_UART_SRBR_STHR_7_SRBR_STHR_7 */
4229  const uint32_t rsvd_srbr_sthr_7_31to8 : 24; /* ALT_UART_SRBR_STHR_7_RSVD_SRBR_STHR_7_31TO8 */
4230 };
4231 
4232 /* The typedef declaration for register ALT_UART_SRBR_STHR_7. */
4233 typedef volatile struct ALT_UART_SRBR_STHR_7_s ALT_UART_SRBR_STHR_7_t;
4234 #endif /* __ASSEMBLY__ */
4235 
4236 /* The reset value of the ALT_UART_SRBR_STHR_7 register. */
4237 #define ALT_UART_SRBR_STHR_7_RESET 0x00000000
4238 /* The byte offset of the ALT_UART_SRBR_STHR_7 register from the beginning of the component. */
4239 #define ALT_UART_SRBR_STHR_7_OFST 0x4c
4240 /* The address of the ALT_UART_SRBR_STHR_7 register. */
4241 #define ALT_UART_SRBR_STHR_7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_7_OFST))
4242 
4243 /*
4244  * Register : Shadow RBR and THR - srbr_sthr_8
4245  *
4246  * This is multi-function register. It is shadow register for Receive Buffer
4247  * Register and Transmit Holding Register.
4248  *
4249  * Register Layout
4250  *
4251  * Bits | Access | Reset | Description
4252  * :-------|:-------|:------|:--------------------------------------------
4253  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_8_SRBR_STHR_8
4254  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8
4255  *
4256  */
4257 /*
4258  * Field : srbr_sthr_8
4259  *
4260  * See srbr_sthr_0 description
4261  *
4262  * Field Access Macros:
4263  *
4264  */
4265 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field. */
4266 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_LSB 0
4267 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field. */
4268 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_MSB 7
4269 /* The width in bits of the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field. */
4270 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_WIDTH 8
4271 /* The mask used to set the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field value. */
4272 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_SET_MSK 0x000000ff
4273 /* The mask used to clear the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field value. */
4274 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_CLR_MSK 0xffffff00
4275 /* The reset value of the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field. */
4276 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_RESET 0x0
4277 /* Extracts the ALT_UART_SRBR_STHR_8_SRBR_STHR_8 field value from a register. */
4278 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_GET(value) (((value) & 0x000000ff) >> 0)
4279 /* Produces a ALT_UART_SRBR_STHR_8_SRBR_STHR_8 register field value suitable for setting the register. */
4280 #define ALT_UART_SRBR_STHR_8_SRBR_STHR_8_SET(value) (((value) << 0) & 0x000000ff)
4281 
4282 /*
4283  * Field : rsvd_srbr_sthr_8_31to8
4284  *
4285  * Reserved bits [31:8] - Read Only
4286  *
4287  * Field Access Macros:
4288  *
4289  */
4290 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field. */
4291 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_LSB 8
4292 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field. */
4293 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_MSB 31
4294 /* The width in bits of the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field. */
4295 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_WIDTH 24
4296 /* The mask used to set the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field value. */
4297 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_SET_MSK 0xffffff00
4298 /* The mask used to clear the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field value. */
4299 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_CLR_MSK 0x000000ff
4300 /* The reset value of the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field. */
4301 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_RESET 0x0
4302 /* Extracts the ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 field value from a register. */
4303 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4304 /* Produces a ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 register field value suitable for setting the register. */
4305 #define ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4306 
4307 #ifndef __ASSEMBLY__
4308 /*
4309  * WARNING: The C register and register group struct declarations are provided for
4310  * convenience and illustrative purposes. They should, however, be used with
4311  * caution as the C language standard provides no guarantees about the alignment or
4312  * atomicity of device memory accesses. The recommended practice for writing
4313  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4314  * alt_write_word() functions.
4315  *
4316  * The struct declaration for register ALT_UART_SRBR_STHR_8.
4317  */
4318 struct ALT_UART_SRBR_STHR_8_s
4319 {
4320  const uint32_t srbr_sthr_8 : 8; /* ALT_UART_SRBR_STHR_8_SRBR_STHR_8 */
4321  const uint32_t rsvd_srbr_sthr_8_31to8 : 24; /* ALT_UART_SRBR_STHR_8_RSVD_SRBR_STHR_8_31TO8 */
4322 };
4323 
4324 /* The typedef declaration for register ALT_UART_SRBR_STHR_8. */
4325 typedef volatile struct ALT_UART_SRBR_STHR_8_s ALT_UART_SRBR_STHR_8_t;
4326 #endif /* __ASSEMBLY__ */
4327 
4328 /* The reset value of the ALT_UART_SRBR_STHR_8 register. */
4329 #define ALT_UART_SRBR_STHR_8_RESET 0x00000000
4330 /* The byte offset of the ALT_UART_SRBR_STHR_8 register from the beginning of the component. */
4331 #define ALT_UART_SRBR_STHR_8_OFST 0x50
4332 /* The address of the ALT_UART_SRBR_STHR_8 register. */
4333 #define ALT_UART_SRBR_STHR_8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_8_OFST))
4334 
4335 /*
4336  * Register : Shadow RBR and THR - srbr_sthr_9
4337  *
4338  * This is multi-function register. It is shadow register for Receive Buffer
4339  * Register and Transmit Holding Register.
4340  *
4341  * Register Layout
4342  *
4343  * Bits | Access | Reset | Description
4344  * :-------|:-------|:------|:--------------------------------------------
4345  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_9_SRBR_STHR_9
4346  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8
4347  *
4348  */
4349 /*
4350  * Field : srbr_sthr_9
4351  *
4352  * See srbr_sthr_0 description
4353  *
4354  * Field Access Macros:
4355  *
4356  */
4357 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field. */
4358 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_LSB 0
4359 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field. */
4360 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_MSB 7
4361 /* The width in bits of the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field. */
4362 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_WIDTH 8
4363 /* The mask used to set the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field value. */
4364 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_SET_MSK 0x000000ff
4365 /* The mask used to clear the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field value. */
4366 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_CLR_MSK 0xffffff00
4367 /* The reset value of the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field. */
4368 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_RESET 0x0
4369 /* Extracts the ALT_UART_SRBR_STHR_9_SRBR_STHR_9 field value from a register. */
4370 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_GET(value) (((value) & 0x000000ff) >> 0)
4371 /* Produces a ALT_UART_SRBR_STHR_9_SRBR_STHR_9 register field value suitable for setting the register. */
4372 #define ALT_UART_SRBR_STHR_9_SRBR_STHR_9_SET(value) (((value) << 0) & 0x000000ff)
4373 
4374 /*
4375  * Field : rsvd_srbr_sthr_9_31to8
4376  *
4377  * Reserved bits [31:8] - Read Only
4378  *
4379  * Field Access Macros:
4380  *
4381  */
4382 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field. */
4383 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_LSB 8
4384 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field. */
4385 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_MSB 31
4386 /* The width in bits of the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field. */
4387 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_WIDTH 24
4388 /* The mask used to set the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field value. */
4389 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_SET_MSK 0xffffff00
4390 /* The mask used to clear the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field value. */
4391 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_CLR_MSK 0x000000ff
4392 /* The reset value of the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field. */
4393 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_RESET 0x0
4394 /* Extracts the ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 field value from a register. */
4395 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4396 /* Produces a ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 register field value suitable for setting the register. */
4397 #define ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4398 
4399 #ifndef __ASSEMBLY__
4400 /*
4401  * WARNING: The C register and register group struct declarations are provided for
4402  * convenience and illustrative purposes. They should, however, be used with
4403  * caution as the C language standard provides no guarantees about the alignment or
4404  * atomicity of device memory accesses. The recommended practice for writing
4405  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4406  * alt_write_word() functions.
4407  *
4408  * The struct declaration for register ALT_UART_SRBR_STHR_9.
4409  */
4410 struct ALT_UART_SRBR_STHR_9_s
4411 {
4412  const uint32_t srbr_sthr_9 : 8; /* ALT_UART_SRBR_STHR_9_SRBR_STHR_9 */
4413  const uint32_t rsvd_srbr_sthr_9_31to8 : 24; /* ALT_UART_SRBR_STHR_9_RSVD_SRBR_STHR_9_31TO8 */
4414 };
4415 
4416 /* The typedef declaration for register ALT_UART_SRBR_STHR_9. */
4417 typedef volatile struct ALT_UART_SRBR_STHR_9_s ALT_UART_SRBR_STHR_9_t;
4418 #endif /* __ASSEMBLY__ */
4419 
4420 /* The reset value of the ALT_UART_SRBR_STHR_9 register. */
4421 #define ALT_UART_SRBR_STHR_9_RESET 0x00000000
4422 /* The byte offset of the ALT_UART_SRBR_STHR_9 register from the beginning of the component. */
4423 #define ALT_UART_SRBR_STHR_9_OFST 0x54
4424 /* The address of the ALT_UART_SRBR_STHR_9 register. */
4425 #define ALT_UART_SRBR_STHR_9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_9_OFST))
4426 
4427 /*
4428  * Register : Shadow RBR and THR - srbr_sthr_10
4429  *
4430  * This is multi-function register. It is shadow register for Receive Buffer
4431  * Register and Transmit Holding Register.
4432  *
4433  * Register Layout
4434  *
4435  * Bits | Access | Reset | Description
4436  * :-------|:-------|:------|:----------------------------------------------
4437  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_10_SRBR_STHR_10
4438  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8
4439  *
4440  */
4441 /*
4442  * Field : srbr_sthr_10
4443  *
4444  * See srbr_sthr_0 description
4445  *
4446  * Field Access Macros:
4447  *
4448  */
4449 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field. */
4450 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_LSB 0
4451 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field. */
4452 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_MSB 7
4453 /* The width in bits of the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field. */
4454 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_WIDTH 8
4455 /* The mask used to set the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field value. */
4456 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_SET_MSK 0x000000ff
4457 /* The mask used to clear the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field value. */
4458 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_CLR_MSK 0xffffff00
4459 /* The reset value of the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field. */
4460 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_RESET 0x0
4461 /* Extracts the ALT_UART_SRBR_STHR_10_SRBR_STHR_10 field value from a register. */
4462 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_GET(value) (((value) & 0x000000ff) >> 0)
4463 /* Produces a ALT_UART_SRBR_STHR_10_SRBR_STHR_10 register field value suitable for setting the register. */
4464 #define ALT_UART_SRBR_STHR_10_SRBR_STHR_10_SET(value) (((value) << 0) & 0x000000ff)
4465 
4466 /*
4467  * Field : rsvd_srbr_sthr_10_31to8
4468  *
4469  * Reserved bits [31:8] - Read Only
4470  *
4471  * Field Access Macros:
4472  *
4473  */
4474 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field. */
4475 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_LSB 8
4476 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field. */
4477 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_MSB 31
4478 /* The width in bits of the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field. */
4479 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_WIDTH 24
4480 /* The mask used to set the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field value. */
4481 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_SET_MSK 0xffffff00
4482 /* The mask used to clear the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field value. */
4483 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_CLR_MSK 0x000000ff
4484 /* The reset value of the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field. */
4485 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_RESET 0x0
4486 /* Extracts the ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 field value from a register. */
4487 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4488 /* Produces a ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 register field value suitable for setting the register. */
4489 #define ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4490 
4491 #ifndef __ASSEMBLY__
4492 /*
4493  * WARNING: The C register and register group struct declarations are provided for
4494  * convenience and illustrative purposes. They should, however, be used with
4495  * caution as the C language standard provides no guarantees about the alignment or
4496  * atomicity of device memory accesses. The recommended practice for writing
4497  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4498  * alt_write_word() functions.
4499  *
4500  * The struct declaration for register ALT_UART_SRBR_STHR_10.
4501  */
4502 struct ALT_UART_SRBR_STHR_10_s
4503 {
4504  const uint32_t srbr_sthr_10 : 8; /* ALT_UART_SRBR_STHR_10_SRBR_STHR_10 */
4505  const uint32_t rsvd_srbr_sthr_10_31to8 : 24; /* ALT_UART_SRBR_STHR_10_RSVD_SRBR_STHR_10_31TO8 */
4506 };
4507 
4508 /* The typedef declaration for register ALT_UART_SRBR_STHR_10. */
4509 typedef volatile struct ALT_UART_SRBR_STHR_10_s ALT_UART_SRBR_STHR_10_t;
4510 #endif /* __ASSEMBLY__ */
4511 
4512 /* The reset value of the ALT_UART_SRBR_STHR_10 register. */
4513 #define ALT_UART_SRBR_STHR_10_RESET 0x00000000
4514 /* The byte offset of the ALT_UART_SRBR_STHR_10 register from the beginning of the component. */
4515 #define ALT_UART_SRBR_STHR_10_OFST 0x58
4516 /* The address of the ALT_UART_SRBR_STHR_10 register. */
4517 #define ALT_UART_SRBR_STHR_10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_10_OFST))
4518 
4519 /*
4520  * Register : Shadow RBR and THR - srbr_sthr_11
4521  *
4522  * This is multi-function register. It is shadow register for Receive Buffer
4523  * Register and Transmit Holding Register.
4524  *
4525  * Register Layout
4526  *
4527  * Bits | Access | Reset | Description
4528  * :-------|:-------|:------|:----------------------------------------------
4529  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_11_SRBR_STHR_11
4530  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8
4531  *
4532  */
4533 /*
4534  * Field : srbr_sthr_11
4535  *
4536  * See srbr_sthr_0 description
4537  *
4538  * Field Access Macros:
4539  *
4540  */
4541 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field. */
4542 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_LSB 0
4543 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field. */
4544 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_MSB 7
4545 /* The width in bits of the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field. */
4546 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_WIDTH 8
4547 /* The mask used to set the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field value. */
4548 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_SET_MSK 0x000000ff
4549 /* The mask used to clear the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field value. */
4550 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_CLR_MSK 0xffffff00
4551 /* The reset value of the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field. */
4552 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_RESET 0x0
4553 /* Extracts the ALT_UART_SRBR_STHR_11_SRBR_STHR_11 field value from a register. */
4554 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_GET(value) (((value) & 0x000000ff) >> 0)
4555 /* Produces a ALT_UART_SRBR_STHR_11_SRBR_STHR_11 register field value suitable for setting the register. */
4556 #define ALT_UART_SRBR_STHR_11_SRBR_STHR_11_SET(value) (((value) << 0) & 0x000000ff)
4557 
4558 /*
4559  * Field : rsvd_srbr_sthr_11_31to8
4560  *
4561  * Reserved bits [31:8] - Read Only
4562  *
4563  * Field Access Macros:
4564  *
4565  */
4566 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field. */
4567 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_LSB 8
4568 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field. */
4569 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_MSB 31
4570 /* The width in bits of the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field. */
4571 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_WIDTH 24
4572 /* The mask used to set the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field value. */
4573 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_SET_MSK 0xffffff00
4574 /* The mask used to clear the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field value. */
4575 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_CLR_MSK 0x000000ff
4576 /* The reset value of the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field. */
4577 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_RESET 0x0
4578 /* Extracts the ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 field value from a register. */
4579 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4580 /* Produces a ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 register field value suitable for setting the register. */
4581 #define ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4582 
4583 #ifndef __ASSEMBLY__
4584 /*
4585  * WARNING: The C register and register group struct declarations are provided for
4586  * convenience and illustrative purposes. They should, however, be used with
4587  * caution as the C language standard provides no guarantees about the alignment or
4588  * atomicity of device memory accesses. The recommended practice for writing
4589  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4590  * alt_write_word() functions.
4591  *
4592  * The struct declaration for register ALT_UART_SRBR_STHR_11.
4593  */
4594 struct ALT_UART_SRBR_STHR_11_s
4595 {
4596  const uint32_t srbr_sthr_11 : 8; /* ALT_UART_SRBR_STHR_11_SRBR_STHR_11 */
4597  const uint32_t rsvd_srbr_sthr_11_31to8 : 24; /* ALT_UART_SRBR_STHR_11_RSVD_SRBR_STHR_11_31TO8 */
4598 };
4599 
4600 /* The typedef declaration for register ALT_UART_SRBR_STHR_11. */
4601 typedef volatile struct ALT_UART_SRBR_STHR_11_s ALT_UART_SRBR_STHR_11_t;
4602 #endif /* __ASSEMBLY__ */
4603 
4604 /* The reset value of the ALT_UART_SRBR_STHR_11 register. */
4605 #define ALT_UART_SRBR_STHR_11_RESET 0x00000000
4606 /* The byte offset of the ALT_UART_SRBR_STHR_11 register from the beginning of the component. */
4607 #define ALT_UART_SRBR_STHR_11_OFST 0x5c
4608 /* The address of the ALT_UART_SRBR_STHR_11 register. */
4609 #define ALT_UART_SRBR_STHR_11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_11_OFST))
4610 
4611 /*
4612  * Register : Shadow RBR and THR - srbr_sthr_12
4613  *
4614  * This is multi-function register. It is shadow register for Receive Buffer
4615  * Register and Transmit Holding Register.
4616  *
4617  * Register Layout
4618  *
4619  * Bits | Access | Reset | Description
4620  * :-------|:-------|:------|:----------------------------------------------
4621  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_12_SRBR_STHR_12
4622  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8
4623  *
4624  */
4625 /*
4626  * Field : srbr_sthr_12
4627  *
4628  * See srbr_sthr_0 description
4629  *
4630  * Field Access Macros:
4631  *
4632  */
4633 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field. */
4634 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_LSB 0
4635 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field. */
4636 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_MSB 7
4637 /* The width in bits of the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field. */
4638 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_WIDTH 8
4639 /* The mask used to set the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field value. */
4640 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_SET_MSK 0x000000ff
4641 /* The mask used to clear the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field value. */
4642 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_CLR_MSK 0xffffff00
4643 /* The reset value of the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field. */
4644 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_RESET 0x0
4645 /* Extracts the ALT_UART_SRBR_STHR_12_SRBR_STHR_12 field value from a register. */
4646 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_GET(value) (((value) & 0x000000ff) >> 0)
4647 /* Produces a ALT_UART_SRBR_STHR_12_SRBR_STHR_12 register field value suitable for setting the register. */
4648 #define ALT_UART_SRBR_STHR_12_SRBR_STHR_12_SET(value) (((value) << 0) & 0x000000ff)
4649 
4650 /*
4651  * Field : rsvd_srbr_sthr_12_31to8
4652  *
4653  * Reserved bits [31:8] - Read Only
4654  *
4655  * Field Access Macros:
4656  *
4657  */
4658 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field. */
4659 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_LSB 8
4660 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field. */
4661 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_MSB 31
4662 /* The width in bits of the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field. */
4663 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_WIDTH 24
4664 /* The mask used to set the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field value. */
4665 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_SET_MSK 0xffffff00
4666 /* The mask used to clear the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field value. */
4667 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_CLR_MSK 0x000000ff
4668 /* The reset value of the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field. */
4669 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_RESET 0x0
4670 /* Extracts the ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 field value from a register. */
4671 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4672 /* Produces a ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 register field value suitable for setting the register. */
4673 #define ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4674 
4675 #ifndef __ASSEMBLY__
4676 /*
4677  * WARNING: The C register and register group struct declarations are provided for
4678  * convenience and illustrative purposes. They should, however, be used with
4679  * caution as the C language standard provides no guarantees about the alignment or
4680  * atomicity of device memory accesses. The recommended practice for writing
4681  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4682  * alt_write_word() functions.
4683  *
4684  * The struct declaration for register ALT_UART_SRBR_STHR_12.
4685  */
4686 struct ALT_UART_SRBR_STHR_12_s
4687 {
4688  const uint32_t srbr_sthr_12 : 8; /* ALT_UART_SRBR_STHR_12_SRBR_STHR_12 */
4689  const uint32_t rsvd_srbr_sthr_12_31to8 : 24; /* ALT_UART_SRBR_STHR_12_RSVD_SRBR_STHR_12_31TO8 */
4690 };
4691 
4692 /* The typedef declaration for register ALT_UART_SRBR_STHR_12. */
4693 typedef volatile struct ALT_UART_SRBR_STHR_12_s ALT_UART_SRBR_STHR_12_t;
4694 #endif /* __ASSEMBLY__ */
4695 
4696 /* The reset value of the ALT_UART_SRBR_STHR_12 register. */
4697 #define ALT_UART_SRBR_STHR_12_RESET 0x00000000
4698 /* The byte offset of the ALT_UART_SRBR_STHR_12 register from the beginning of the component. */
4699 #define ALT_UART_SRBR_STHR_12_OFST 0x60
4700 /* The address of the ALT_UART_SRBR_STHR_12 register. */
4701 #define ALT_UART_SRBR_STHR_12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_12_OFST))
4702 
4703 /*
4704  * Register : Shadow RBR and THR - srbr_sthr_13
4705  *
4706  * This is multi-function register. It is shadow register for Receive Buffer
4707  * Register and Transmit Holding Register.
4708  *
4709  * Register Layout
4710  *
4711  * Bits | Access | Reset | Description
4712  * :-------|:-------|:------|:----------------------------------------------
4713  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_13_SRBR_STHR_13
4714  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8
4715  *
4716  */
4717 /*
4718  * Field : srbr_sthr_13
4719  *
4720  * See srbr_sthr_0 description
4721  *
4722  * Field Access Macros:
4723  *
4724  */
4725 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field. */
4726 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_LSB 0
4727 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field. */
4728 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_MSB 7
4729 /* The width in bits of the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field. */
4730 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_WIDTH 8
4731 /* The mask used to set the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field value. */
4732 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_SET_MSK 0x000000ff
4733 /* The mask used to clear the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field value. */
4734 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_CLR_MSK 0xffffff00
4735 /* The reset value of the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field. */
4736 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_RESET 0x0
4737 /* Extracts the ALT_UART_SRBR_STHR_13_SRBR_STHR_13 field value from a register. */
4738 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_GET(value) (((value) & 0x000000ff) >> 0)
4739 /* Produces a ALT_UART_SRBR_STHR_13_SRBR_STHR_13 register field value suitable for setting the register. */
4740 #define ALT_UART_SRBR_STHR_13_SRBR_STHR_13_SET(value) (((value) << 0) & 0x000000ff)
4741 
4742 /*
4743  * Field : rsvd_srbr_sthr_13_31to8
4744  *
4745  * Reserved bits [31:8] - Read Only
4746  *
4747  * Field Access Macros:
4748  *
4749  */
4750 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field. */
4751 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_LSB 8
4752 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field. */
4753 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_MSB 31
4754 /* The width in bits of the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field. */
4755 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_WIDTH 24
4756 /* The mask used to set the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field value. */
4757 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_SET_MSK 0xffffff00
4758 /* The mask used to clear the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field value. */
4759 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_CLR_MSK 0x000000ff
4760 /* The reset value of the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field. */
4761 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_RESET 0x0
4762 /* Extracts the ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 field value from a register. */
4763 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4764 /* Produces a ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 register field value suitable for setting the register. */
4765 #define ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4766 
4767 #ifndef __ASSEMBLY__
4768 /*
4769  * WARNING: The C register and register group struct declarations are provided for
4770  * convenience and illustrative purposes. They should, however, be used with
4771  * caution as the C language standard provides no guarantees about the alignment or
4772  * atomicity of device memory accesses. The recommended practice for writing
4773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4774  * alt_write_word() functions.
4775  *
4776  * The struct declaration for register ALT_UART_SRBR_STHR_13.
4777  */
4778 struct ALT_UART_SRBR_STHR_13_s
4779 {
4780  const uint32_t srbr_sthr_13 : 8; /* ALT_UART_SRBR_STHR_13_SRBR_STHR_13 */
4781  const uint32_t rsvd_srbr_sthr_13_31to8 : 24; /* ALT_UART_SRBR_STHR_13_RSVD_SRBR_STHR_13_31TO8 */
4782 };
4783 
4784 /* The typedef declaration for register ALT_UART_SRBR_STHR_13. */
4785 typedef volatile struct ALT_UART_SRBR_STHR_13_s ALT_UART_SRBR_STHR_13_t;
4786 #endif /* __ASSEMBLY__ */
4787 
4788 /* The reset value of the ALT_UART_SRBR_STHR_13 register. */
4789 #define ALT_UART_SRBR_STHR_13_RESET 0x00000000
4790 /* The byte offset of the ALT_UART_SRBR_STHR_13 register from the beginning of the component. */
4791 #define ALT_UART_SRBR_STHR_13_OFST 0x64
4792 /* The address of the ALT_UART_SRBR_STHR_13 register. */
4793 #define ALT_UART_SRBR_STHR_13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_13_OFST))
4794 
4795 /*
4796  * Register : Shadow RBR and THR - srbr_sthr_14
4797  *
4798  * This is multi-function register. It is shadow register for Receive Buffer
4799  * Register and Transmit Holding Register.
4800  *
4801  * Register Layout
4802  *
4803  * Bits | Access | Reset | Description
4804  * :-------|:-------|:------|:----------------------------------------------
4805  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_14_SRBR_STHR_14
4806  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8
4807  *
4808  */
4809 /*
4810  * Field : srbr_sthr_14
4811  *
4812  * See srbr_sthr_0 description
4813  *
4814  * Field Access Macros:
4815  *
4816  */
4817 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field. */
4818 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_LSB 0
4819 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field. */
4820 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_MSB 7
4821 /* The width in bits of the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field. */
4822 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_WIDTH 8
4823 /* The mask used to set the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field value. */
4824 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_SET_MSK 0x000000ff
4825 /* The mask used to clear the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field value. */
4826 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_CLR_MSK 0xffffff00
4827 /* The reset value of the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field. */
4828 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_RESET 0x0
4829 /* Extracts the ALT_UART_SRBR_STHR_14_SRBR_STHR_14 field value from a register. */
4830 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_GET(value) (((value) & 0x000000ff) >> 0)
4831 /* Produces a ALT_UART_SRBR_STHR_14_SRBR_STHR_14 register field value suitable for setting the register. */
4832 #define ALT_UART_SRBR_STHR_14_SRBR_STHR_14_SET(value) (((value) << 0) & 0x000000ff)
4833 
4834 /*
4835  * Field : rsvd_srbr_sthr_14_31to8
4836  *
4837  * Reserved bits [31:8] - Read Only
4838  *
4839  * Field Access Macros:
4840  *
4841  */
4842 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field. */
4843 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_LSB 8
4844 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field. */
4845 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_MSB 31
4846 /* The width in bits of the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field. */
4847 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_WIDTH 24
4848 /* The mask used to set the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field value. */
4849 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_SET_MSK 0xffffff00
4850 /* The mask used to clear the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field value. */
4851 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_CLR_MSK 0x000000ff
4852 /* The reset value of the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field. */
4853 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_RESET 0x0
4854 /* Extracts the ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 field value from a register. */
4855 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4856 /* Produces a ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 register field value suitable for setting the register. */
4857 #define ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4858 
4859 #ifndef __ASSEMBLY__
4860 /*
4861  * WARNING: The C register and register group struct declarations are provided for
4862  * convenience and illustrative purposes. They should, however, be used with
4863  * caution as the C language standard provides no guarantees about the alignment or
4864  * atomicity of device memory accesses. The recommended practice for writing
4865  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4866  * alt_write_word() functions.
4867  *
4868  * The struct declaration for register ALT_UART_SRBR_STHR_14.
4869  */
4870 struct ALT_UART_SRBR_STHR_14_s
4871 {
4872  const uint32_t srbr_sthr_14 : 8; /* ALT_UART_SRBR_STHR_14_SRBR_STHR_14 */
4873  const uint32_t rsvd_srbr_sthr_14_31to8 : 24; /* ALT_UART_SRBR_STHR_14_RSVD_SRBR_STHR_14_31TO8 */
4874 };
4875 
4876 /* The typedef declaration for register ALT_UART_SRBR_STHR_14. */
4877 typedef volatile struct ALT_UART_SRBR_STHR_14_s ALT_UART_SRBR_STHR_14_t;
4878 #endif /* __ASSEMBLY__ */
4879 
4880 /* The reset value of the ALT_UART_SRBR_STHR_14 register. */
4881 #define ALT_UART_SRBR_STHR_14_RESET 0x00000000
4882 /* The byte offset of the ALT_UART_SRBR_STHR_14 register from the beginning of the component. */
4883 #define ALT_UART_SRBR_STHR_14_OFST 0x68
4884 /* The address of the ALT_UART_SRBR_STHR_14 register. */
4885 #define ALT_UART_SRBR_STHR_14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_14_OFST))
4886 
4887 /*
4888  * Register : Shadow RBR and THR - srbr_sthr_15
4889  *
4890  * This is multi-function register. It is shadow register for Receive Buffer
4891  * Register and Transmit Holding Register.
4892  *
4893  * Register Layout
4894  *
4895  * Bits | Access | Reset | Description
4896  * :-------|:-------|:------|:----------------------------------------------
4897  * [7:0] | R | 0x0 | ALT_UART_SRBR_STHR_15_SRBR_STHR_15
4898  * [31:8] | R | 0x0 | ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8
4899  *
4900  */
4901 /*
4902  * Field : srbr_sthr_15
4903  *
4904  * See srbr_sthr_0 description
4905  *
4906  * Field Access Macros:
4907  *
4908  */
4909 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field. */
4910 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_LSB 0
4911 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field. */
4912 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_MSB 7
4913 /* The width in bits of the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field. */
4914 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_WIDTH 8
4915 /* The mask used to set the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field value. */
4916 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_SET_MSK 0x000000ff
4917 /* The mask used to clear the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field value. */
4918 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_CLR_MSK 0xffffff00
4919 /* The reset value of the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field. */
4920 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_RESET 0x0
4921 /* Extracts the ALT_UART_SRBR_STHR_15_SRBR_STHR_15 field value from a register. */
4922 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_GET(value) (((value) & 0x000000ff) >> 0)
4923 /* Produces a ALT_UART_SRBR_STHR_15_SRBR_STHR_15 register field value suitable for setting the register. */
4924 #define ALT_UART_SRBR_STHR_15_SRBR_STHR_15_SET(value) (((value) << 0) & 0x000000ff)
4925 
4926 /*
4927  * Field : rsvd_srbr_sthr_15_31to8
4928  *
4929  * Reserved bits [31:8] - Read Only
4930  *
4931  * Field Access Macros:
4932  *
4933  */
4934 /* The Least Significant Bit (LSB) position of the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field. */
4935 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_LSB 8
4936 /* The Most Significant Bit (MSB) position of the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field. */
4937 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_MSB 31
4938 /* The width in bits of the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field. */
4939 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_WIDTH 24
4940 /* The mask used to set the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field value. */
4941 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_SET_MSK 0xffffff00
4942 /* The mask used to clear the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field value. */
4943 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_CLR_MSK 0x000000ff
4944 /* The reset value of the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field. */
4945 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_RESET 0x0
4946 /* Extracts the ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 field value from a register. */
4947 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
4948 /* Produces a ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 register field value suitable for setting the register. */
4949 #define ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8_SET(value) (((value) << 8) & 0xffffff00)
4950 
4951 #ifndef __ASSEMBLY__
4952 /*
4953  * WARNING: The C register and register group struct declarations are provided for
4954  * convenience and illustrative purposes. They should, however, be used with
4955  * caution as the C language standard provides no guarantees about the alignment or
4956  * atomicity of device memory accesses. The recommended practice for writing
4957  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4958  * alt_write_word() functions.
4959  *
4960  * The struct declaration for register ALT_UART_SRBR_STHR_15.
4961  */
4962 struct ALT_UART_SRBR_STHR_15_s
4963 {
4964  const uint32_t srbr_sthr_15 : 8; /* ALT_UART_SRBR_STHR_15_SRBR_STHR_15 */
4965  const uint32_t rsvd_srbr_sthr_15_31to8 : 24; /* ALT_UART_SRBR_STHR_15_RSVD_SRBR_STHR_15_31TO8 */
4966 };
4967 
4968 /* The typedef declaration for register ALT_UART_SRBR_STHR_15. */
4969 typedef volatile struct ALT_UART_SRBR_STHR_15_s ALT_UART_SRBR_STHR_15_t;
4970 #endif /* __ASSEMBLY__ */
4971 
4972 /* The reset value of the ALT_UART_SRBR_STHR_15 register. */
4973 #define ALT_UART_SRBR_STHR_15_RESET 0x00000000
4974 /* The byte offset of the ALT_UART_SRBR_STHR_15 register from the beginning of the component. */
4975 #define ALT_UART_SRBR_STHR_15_OFST 0x6c
4976 /* The address of the ALT_UART_SRBR_STHR_15 register. */
4977 #define ALT_UART_SRBR_STHR_15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_STHR_15_OFST))
4978 
4979 /*
4980  * Register : far
4981  *
4982  * FIFO Access Register
4983  *
4984  * Register Layout
4985  *
4986  * Bits | Access | Reset | Description
4987  * :-------|:-------|:------|:----------------------------
4988  * [0] | RW | 0x0 | ALT_UART_FAR_SRBR_STHR
4989  * [31:1] | R | 0x0 | ALT_UART_FAR_RSVD_FAR_31TO1
4990  *
4991  */
4992 /*
4993  * Field : srbr_sthr
4994  *
4995  * Writes will have no effect when FIFO_ACCESS == No, always readable. This
4996  * register
4997  *
4998  * is use to enable a FIFO access mode for testing, so that the receive FIFO can be
4999  *
5000  * written by the master and the transmit FIFO can be read by the master when
5001  * FIFO's
5002  *
5003  * are implemented and enabled. When FIFO's are not implemented or not enabled it
5004  *
5005  * allows the RBR to be written by the master and the THR to be read by the master.
5006  *
5007  * 0 = FIFO access mode disabled
5008  *
5009  * 1 = FIFO access mode enabled
5010  *
5011  * Note, that when the FIFO access mode is enabled/disabled, the control portion of
5012  *
5013  * the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
5014  *
5015  * Field Enumeration Values:
5016  *
5017  * Enum | Value | Description
5018  * :------------------------------|:------|:--------------------------
5019  * ALT_UART_FAR_SRBR_STHR_E_DISD | 0x0 | FIFO access mode disabled
5020  * ALT_UART_FAR_SRBR_STHR_E_END | 0x1 | FIFO access mode enabled
5021  *
5022  * Field Access Macros:
5023  *
5024  */
5025 /*
5026  * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
5027  *
5028  * FIFO access mode disabled
5029  */
5030 #define ALT_UART_FAR_SRBR_STHR_E_DISD 0x0
5031 /*
5032  * Enumerated value for register field ALT_UART_FAR_SRBR_STHR
5033  *
5034  * FIFO access mode enabled
5035  */
5036 #define ALT_UART_FAR_SRBR_STHR_E_END 0x1
5037 
5038 /* The Least Significant Bit (LSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
5039 #define ALT_UART_FAR_SRBR_STHR_LSB 0
5040 /* The Most Significant Bit (MSB) position of the ALT_UART_FAR_SRBR_STHR register field. */
5041 #define ALT_UART_FAR_SRBR_STHR_MSB 0
5042 /* The width in bits of the ALT_UART_FAR_SRBR_STHR register field. */
5043 #define ALT_UART_FAR_SRBR_STHR_WIDTH 1
5044 /* The mask used to set the ALT_UART_FAR_SRBR_STHR register field value. */
5045 #define ALT_UART_FAR_SRBR_STHR_SET_MSK 0x00000001
5046 /* The mask used to clear the ALT_UART_FAR_SRBR_STHR register field value. */
5047 #define ALT_UART_FAR_SRBR_STHR_CLR_MSK 0xfffffffe
5048 /* The reset value of the ALT_UART_FAR_SRBR_STHR register field. */
5049 #define ALT_UART_FAR_SRBR_STHR_RESET 0x0
5050 /* Extracts the ALT_UART_FAR_SRBR_STHR field value from a register. */
5051 #define ALT_UART_FAR_SRBR_STHR_GET(value) (((value) & 0x00000001) >> 0)
5052 /* Produces a ALT_UART_FAR_SRBR_STHR register field value suitable for setting the register. */
5053 #define ALT_UART_FAR_SRBR_STHR_SET(value) (((value) << 0) & 0x00000001)
5054 
5055 /*
5056  * Field : rsvd_far_31to1
5057  *
5058  * Reserved bits [31:1] - Read Only
5059  *
5060  * Field Access Macros:
5061  *
5062  */
5063 /* The Least Significant Bit (LSB) position of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
5064 #define ALT_UART_FAR_RSVD_FAR_31TO1_LSB 1
5065 /* The Most Significant Bit (MSB) position of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
5066 #define ALT_UART_FAR_RSVD_FAR_31TO1_MSB 31
5067 /* The width in bits of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
5068 #define ALT_UART_FAR_RSVD_FAR_31TO1_WIDTH 31
5069 /* The mask used to set the ALT_UART_FAR_RSVD_FAR_31TO1 register field value. */
5070 #define ALT_UART_FAR_RSVD_FAR_31TO1_SET_MSK 0xfffffffe
5071 /* The mask used to clear the ALT_UART_FAR_RSVD_FAR_31TO1 register field value. */
5072 #define ALT_UART_FAR_RSVD_FAR_31TO1_CLR_MSK 0x00000001
5073 /* The reset value of the ALT_UART_FAR_RSVD_FAR_31TO1 register field. */
5074 #define ALT_UART_FAR_RSVD_FAR_31TO1_RESET 0x0
5075 /* Extracts the ALT_UART_FAR_RSVD_FAR_31TO1 field value from a register. */
5076 #define ALT_UART_FAR_RSVD_FAR_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
5077 /* Produces a ALT_UART_FAR_RSVD_FAR_31TO1 register field value suitable for setting the register. */
5078 #define ALT_UART_FAR_RSVD_FAR_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
5079 
5080 #ifndef __ASSEMBLY__
5081 /*
5082  * WARNING: The C register and register group struct declarations are provided for
5083  * convenience and illustrative purposes. They should, however, be used with
5084  * caution as the C language standard provides no guarantees about the alignment or
5085  * atomicity of device memory accesses. The recommended practice for writing
5086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5087  * alt_write_word() functions.
5088  *
5089  * The struct declaration for register ALT_UART_FAR.
5090  */
5091 struct ALT_UART_FAR_s
5092 {
5093  uint32_t srbr_sthr : 1; /* ALT_UART_FAR_SRBR_STHR */
5094  const uint32_t rsvd_far_31to1 : 31; /* ALT_UART_FAR_RSVD_FAR_31TO1 */
5095 };
5096 
5097 /* The typedef declaration for register ALT_UART_FAR. */
5098 typedef volatile struct ALT_UART_FAR_s ALT_UART_FAR_t;
5099 #endif /* __ASSEMBLY__ */
5100 
5101 /* The reset value of the ALT_UART_FAR register. */
5102 #define ALT_UART_FAR_RESET 0x00000000
5103 /* The byte offset of the ALT_UART_FAR register from the beginning of the component. */
5104 #define ALT_UART_FAR_OFST 0x70
5105 /* The address of the ALT_UART_FAR register. */
5106 #define ALT_UART_FAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FAR_OFST))
5107 
5108 /*
5109  * Register : tfr
5110  *
5111  * Transmit FIFO Read
5112  *
5113  * Register Layout
5114  *
5115  * Bits | Access | Reset | Description
5116  * :-------|:-------|:------|:----------------------------
5117  * [7:0] | R | 0x0 | ALT_UART_TFR_TFR
5118  * [31:8] | R | 0x0 | ALT_UART_TFR_RSVD_TFR_31TO8
5119  *
5120  */
5121 /*
5122  * Field : tfr
5123  *
5124  * Transmit FIFO Read.
5125  *
5126  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
5127  * one).
5128  *
5129  * When FIFO's are implemented and enabled, reading this register gives the data at
5130  * the
5131  *
5132  * top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives
5133  * the
5134  *
5135  * next data value that is currently at the top of the FIFO.
5136  *
5137  * When FIFO's are not implemented or not enabled, reading this register gives the
5138  * data
5139  *
5140  * in the THR.
5141  *
5142  * Field Access Macros:
5143  *
5144  */
5145 /* The Least Significant Bit (LSB) position of the ALT_UART_TFR_TFR register field. */
5146 #define ALT_UART_TFR_TFR_LSB 0
5147 /* The Most Significant Bit (MSB) position of the ALT_UART_TFR_TFR register field. */
5148 #define ALT_UART_TFR_TFR_MSB 7
5149 /* The width in bits of the ALT_UART_TFR_TFR register field. */
5150 #define ALT_UART_TFR_TFR_WIDTH 8
5151 /* The mask used to set the ALT_UART_TFR_TFR register field value. */
5152 #define ALT_UART_TFR_TFR_SET_MSK 0x000000ff
5153 /* The mask used to clear the ALT_UART_TFR_TFR register field value. */
5154 #define ALT_UART_TFR_TFR_CLR_MSK 0xffffff00
5155 /* The reset value of the ALT_UART_TFR_TFR register field. */
5156 #define ALT_UART_TFR_TFR_RESET 0x0
5157 /* Extracts the ALT_UART_TFR_TFR field value from a register. */
5158 #define ALT_UART_TFR_TFR_GET(value) (((value) & 0x000000ff) >> 0)
5159 /* Produces a ALT_UART_TFR_TFR register field value suitable for setting the register. */
5160 #define ALT_UART_TFR_TFR_SET(value) (((value) << 0) & 0x000000ff)
5161 
5162 /*
5163  * Field : rsvd_tfr_31to8
5164  *
5165  * Reserved bits [31:8] - Read Only
5166  *
5167  * Field Access Macros:
5168  *
5169  */
5170 /* The Least Significant Bit (LSB) position of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
5171 #define ALT_UART_TFR_RSVD_TFR_31TO8_LSB 8
5172 /* The Most Significant Bit (MSB) position of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
5173 #define ALT_UART_TFR_RSVD_TFR_31TO8_MSB 31
5174 /* The width in bits of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
5175 #define ALT_UART_TFR_RSVD_TFR_31TO8_WIDTH 24
5176 /* The mask used to set the ALT_UART_TFR_RSVD_TFR_31TO8 register field value. */
5177 #define ALT_UART_TFR_RSVD_TFR_31TO8_SET_MSK 0xffffff00
5178 /* The mask used to clear the ALT_UART_TFR_RSVD_TFR_31TO8 register field value. */
5179 #define ALT_UART_TFR_RSVD_TFR_31TO8_CLR_MSK 0x000000ff
5180 /* The reset value of the ALT_UART_TFR_RSVD_TFR_31TO8 register field. */
5181 #define ALT_UART_TFR_RSVD_TFR_31TO8_RESET 0x0
5182 /* Extracts the ALT_UART_TFR_RSVD_TFR_31TO8 field value from a register. */
5183 #define ALT_UART_TFR_RSVD_TFR_31TO8_GET(value) (((value) & 0xffffff00) >> 8)
5184 /* Produces a ALT_UART_TFR_RSVD_TFR_31TO8 register field value suitable for setting the register. */
5185 #define ALT_UART_TFR_RSVD_TFR_31TO8_SET(value) (((value) << 8) & 0xffffff00)
5186 
5187 #ifndef __ASSEMBLY__
5188 /*
5189  * WARNING: The C register and register group struct declarations are provided for
5190  * convenience and illustrative purposes. They should, however, be used with
5191  * caution as the C language standard provides no guarantees about the alignment or
5192  * atomicity of device memory accesses. The recommended practice for writing
5193  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5194  * alt_write_word() functions.
5195  *
5196  * The struct declaration for register ALT_UART_TFR.
5197  */
5198 struct ALT_UART_TFR_s
5199 {
5200  const uint32_t tfr : 8; /* ALT_UART_TFR_TFR */
5201  const uint32_t rsvd_tfr_31to8 : 24; /* ALT_UART_TFR_RSVD_TFR_31TO8 */
5202 };
5203 
5204 /* The typedef declaration for register ALT_UART_TFR. */
5205 typedef volatile struct ALT_UART_TFR_s ALT_UART_TFR_t;
5206 #endif /* __ASSEMBLY__ */
5207 
5208 /* The reset value of the ALT_UART_TFR register. */
5209 #define ALT_UART_TFR_RESET 0x00000000
5210 /* The byte offset of the ALT_UART_TFR register from the beginning of the component. */
5211 #define ALT_UART_TFR_OFST 0x74
5212 /* The address of the ALT_UART_TFR register. */
5213 #define ALT_UART_TFR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFR_OFST))
5214 
5215 /*
5216  * Register : rfw
5217  *
5218  * Receive FIFO Write
5219  *
5220  * Register Layout
5221  *
5222  * Bits | Access | Reset | Description
5223  * :--------|:-------|:------|:-----------------------------
5224  * [7:0] | W | 0x0 | ALT_UART_RFW_RFWD
5225  * [8] | W | 0x0 | ALT_UART_RFW_RFPE
5226  * [9] | W | 0x0 | ALT_UART_RFW_RFFE
5227  * [31:10] | R | 0x0 | ALT_UART_RFW_RSVD_RFW_31TO10
5228  *
5229  */
5230 /*
5231  * Field : rfwd
5232  *
5233  * Receive FIFO Write Data.
5234  *
5235  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
5236  * one).
5237  *
5238  * When FIFO's are implemented and enabled, the data that is written to the RFWD is
5239  * pushed
5240  *
5241  * into the receive FIFO. Each consecutive write pushes the new data to the next
5242  * write
5243  *
5244  * location in the receive FIFO.
5245  *
5246  * When FIFO's are not implemented or not enabled, the data that is written to the
5247  * RFWD
5248  *
5249  * is pushed into the RBR.
5250  *
5251  * Field Access Macros:
5252  *
5253  */
5254 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFWD register field. */
5255 #define ALT_UART_RFW_RFWD_LSB 0
5256 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFWD register field. */
5257 #define ALT_UART_RFW_RFWD_MSB 7
5258 /* The width in bits of the ALT_UART_RFW_RFWD register field. */
5259 #define ALT_UART_RFW_RFWD_WIDTH 8
5260 /* The mask used to set the ALT_UART_RFW_RFWD register field value. */
5261 #define ALT_UART_RFW_RFWD_SET_MSK 0x000000ff
5262 /* The mask used to clear the ALT_UART_RFW_RFWD register field value. */
5263 #define ALT_UART_RFW_RFWD_CLR_MSK 0xffffff00
5264 /* The reset value of the ALT_UART_RFW_RFWD register field. */
5265 #define ALT_UART_RFW_RFWD_RESET 0x0
5266 /* Extracts the ALT_UART_RFW_RFWD field value from a register. */
5267 #define ALT_UART_RFW_RFWD_GET(value) (((value) & 0x000000ff) >> 0)
5268 /* Produces a ALT_UART_RFW_RFWD register field value suitable for setting the register. */
5269 #define ALT_UART_RFW_RFWD_SET(value) (((value) << 0) & 0x000000ff)
5270 
5271 /*
5272  * Field : rfpe
5273  *
5274  * Receive FIFO Parity Error.
5275  *
5276  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
5277  * one).
5278  *
5279  * When FIFO's are implemented and enabled, this bit is used to write parity error
5280  *
5281  * detection information to the receive FIFO.
5282  *
5283  * When FIFO's are not implemented or not enabled, this bit is used to write parity
5284  *
5285  * error detection information to the RBR.
5286  *
5287  * Field Access Macros:
5288  *
5289  */
5290 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFPE register field. */
5291 #define ALT_UART_RFW_RFPE_LSB 8
5292 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFPE register field. */
5293 #define ALT_UART_RFW_RFPE_MSB 8
5294 /* The width in bits of the ALT_UART_RFW_RFPE register field. */
5295 #define ALT_UART_RFW_RFPE_WIDTH 1
5296 /* The mask used to set the ALT_UART_RFW_RFPE register field value. */
5297 #define ALT_UART_RFW_RFPE_SET_MSK 0x00000100
5298 /* The mask used to clear the ALT_UART_RFW_RFPE register field value. */
5299 #define ALT_UART_RFW_RFPE_CLR_MSK 0xfffffeff
5300 /* The reset value of the ALT_UART_RFW_RFPE register field. */
5301 #define ALT_UART_RFW_RFPE_RESET 0x0
5302 /* Extracts the ALT_UART_RFW_RFPE field value from a register. */
5303 #define ALT_UART_RFW_RFPE_GET(value) (((value) & 0x00000100) >> 8)
5304 /* Produces a ALT_UART_RFW_RFPE register field value suitable for setting the register. */
5305 #define ALT_UART_RFW_RFPE_SET(value) (((value) << 8) & 0x00000100)
5306 
5307 /*
5308  * Field : rffe
5309  *
5310  * Receive FIFO Framing Error.
5311  *
5312  * These bits are only valid when FIFO access mode is enabled (FAR[0] is set to
5313  * one).
5314  *
5315  * When FIFO's are implemented and enabled, this bit is used to write framing error
5316  *
5317  * detection information to the receive FIFO.
5318  *
5319  * When FIFO's are not implemented or not enabled, this bit is used to write
5320  * framing
5321  *
5322  * error detection information to the RBR.
5323  *
5324  * Field Access Macros:
5325  *
5326  */
5327 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RFFE register field. */
5328 #define ALT_UART_RFW_RFFE_LSB 9
5329 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RFFE register field. */
5330 #define ALT_UART_RFW_RFFE_MSB 9
5331 /* The width in bits of the ALT_UART_RFW_RFFE register field. */
5332 #define ALT_UART_RFW_RFFE_WIDTH 1
5333 /* The mask used to set the ALT_UART_RFW_RFFE register field value. */
5334 #define ALT_UART_RFW_RFFE_SET_MSK 0x00000200
5335 /* The mask used to clear the ALT_UART_RFW_RFFE register field value. */
5336 #define ALT_UART_RFW_RFFE_CLR_MSK 0xfffffdff
5337 /* The reset value of the ALT_UART_RFW_RFFE register field. */
5338 #define ALT_UART_RFW_RFFE_RESET 0x0
5339 /* Extracts the ALT_UART_RFW_RFFE field value from a register. */
5340 #define ALT_UART_RFW_RFFE_GET(value) (((value) & 0x00000200) >> 9)
5341 /* Produces a ALT_UART_RFW_RFFE register field value suitable for setting the register. */
5342 #define ALT_UART_RFW_RFFE_SET(value) (((value) << 9) & 0x00000200)
5343 
5344 /*
5345  * Field : rsvd_rfw_31to10
5346  *
5347  * Reserved bits [31:10] - Read Only
5348  *
5349  * Field Access Macros:
5350  *
5351  */
5352 /* The Least Significant Bit (LSB) position of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5353 #define ALT_UART_RFW_RSVD_RFW_31TO10_LSB 10
5354 /* The Most Significant Bit (MSB) position of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5355 #define ALT_UART_RFW_RSVD_RFW_31TO10_MSB 31
5356 /* The width in bits of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5357 #define ALT_UART_RFW_RSVD_RFW_31TO10_WIDTH 22
5358 /* The mask used to set the ALT_UART_RFW_RSVD_RFW_31TO10 register field value. */
5359 #define ALT_UART_RFW_RSVD_RFW_31TO10_SET_MSK 0xfffffc00
5360 /* The mask used to clear the ALT_UART_RFW_RSVD_RFW_31TO10 register field value. */
5361 #define ALT_UART_RFW_RSVD_RFW_31TO10_CLR_MSK 0x000003ff
5362 /* The reset value of the ALT_UART_RFW_RSVD_RFW_31TO10 register field. */
5363 #define ALT_UART_RFW_RSVD_RFW_31TO10_RESET 0x0
5364 /* Extracts the ALT_UART_RFW_RSVD_RFW_31TO10 field value from a register. */
5365 #define ALT_UART_RFW_RSVD_RFW_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
5366 /* Produces a ALT_UART_RFW_RSVD_RFW_31TO10 register field value suitable for setting the register. */
5367 #define ALT_UART_RFW_RSVD_RFW_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
5368 
5369 #ifndef __ASSEMBLY__
5370 /*
5371  * WARNING: The C register and register group struct declarations are provided for
5372  * convenience and illustrative purposes. They should, however, be used with
5373  * caution as the C language standard provides no guarantees about the alignment or
5374  * atomicity of device memory accesses. The recommended practice for writing
5375  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5376  * alt_write_word() functions.
5377  *
5378  * The struct declaration for register ALT_UART_RFW.
5379  */
5380 struct ALT_UART_RFW_s
5381 {
5382  uint32_t rfwd : 8; /* ALT_UART_RFW_RFWD */
5383  uint32_t rfpe : 1; /* ALT_UART_RFW_RFPE */
5384  uint32_t rffe : 1; /* ALT_UART_RFW_RFFE */
5385  const uint32_t rsvd_rfw_31to10 : 22; /* ALT_UART_RFW_RSVD_RFW_31TO10 */
5386 };
5387 
5388 /* The typedef declaration for register ALT_UART_RFW. */
5389 typedef volatile struct ALT_UART_RFW_s ALT_UART_RFW_t;
5390 #endif /* __ASSEMBLY__ */
5391 
5392 /* The reset value of the ALT_UART_RFW register. */
5393 #define ALT_UART_RFW_RESET 0x00000000
5394 /* The byte offset of the ALT_UART_RFW register from the beginning of the component. */
5395 #define ALT_UART_RFW_OFST 0x78
5396 /* The address of the ALT_UART_RFW register. */
5397 #define ALT_UART_RFW_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFW_OFST))
5398 
5399 /*
5400  * Register : usr
5401  *
5402  * UART Status register.
5403  *
5404  * Register Layout
5405  *
5406  * Bits | Access | Reset | Description
5407  * :-------|:-------|:------|:----------------------------
5408  * [0] | R | 0x0 | ALT_UART_USR_RSVD_BUSY
5409  * [1] | R | 0x1 | ALT_UART_USR_TFNF
5410  * [2] | R | 0x1 | ALT_UART_USR_TFE
5411  * [3] | R | 0x0 | ALT_UART_USR_RFNE
5412  * [4] | R | 0x0 | ALT_UART_USR_RFF
5413  * [31:5] | R | 0x0 | ALT_UART_USR_RSVD_USR_31TO5
5414  *
5415  */
5416 /*
5417  * Field : rsvd_busy
5418  *
5419  * UART Busy.
5420  *
5421  * This bit is only valid when UART_16550_COMPATIBLE == NO. This indicates that a
5422  * serial
5423  *
5424  * transfer is in progress, when cleared indicates that the DW_apb_uart is idle or
5425  * inactive.
5426  *
5427  * 0 = DW_apb_uart is idle or inactive
5428  *
5429  * 1 - DW_apb_uart is busy (actively transferring data)
5430  *
5431  * Note that it is possible for the UART Busy bit to be cleared even though a new
5432  *
5433  * character may have been sent from another device. That is, if the DW_apb_uart
5434  *
5435  * has no data in the THR and RBR and there is no transmission in progress and a
5436  * start
5437  *
5438  * bit of a new character has just reached the DW_apb_uart. This is due to the fact
5439  *
5440  * that a valid start is not seen until the middle of the bit period and this
5441  * duration
5442  *
5443  * is dependent on the baud divisor that has been programmed. If a second system
5444  * clock
5445  *
5446  * has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also
5447  * be
5448  *
5449  * delayed by several cycles of the slower clock.
5450  *
5451  * Field Access Macros:
5452  *
5453  */
5454 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RSVD_BUSY register field. */
5455 #define ALT_UART_USR_RSVD_BUSY_LSB 0
5456 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RSVD_BUSY register field. */
5457 #define ALT_UART_USR_RSVD_BUSY_MSB 0
5458 /* The width in bits of the ALT_UART_USR_RSVD_BUSY register field. */
5459 #define ALT_UART_USR_RSVD_BUSY_WIDTH 1
5460 /* The mask used to set the ALT_UART_USR_RSVD_BUSY register field value. */
5461 #define ALT_UART_USR_RSVD_BUSY_SET_MSK 0x00000001
5462 /* The mask used to clear the ALT_UART_USR_RSVD_BUSY register field value. */
5463 #define ALT_UART_USR_RSVD_BUSY_CLR_MSK 0xfffffffe
5464 /* The reset value of the ALT_UART_USR_RSVD_BUSY register field. */
5465 #define ALT_UART_USR_RSVD_BUSY_RESET 0x0
5466 /* Extracts the ALT_UART_USR_RSVD_BUSY field value from a register. */
5467 #define ALT_UART_USR_RSVD_BUSY_GET(value) (((value) & 0x00000001) >> 0)
5468 /* Produces a ALT_UART_USR_RSVD_BUSY register field value suitable for setting the register. */
5469 #define ALT_UART_USR_RSVD_BUSY_SET(value) (((value) << 0) & 0x00000001)
5470 
5471 /*
5472  * Field : tfnf
5473  *
5474  * Transmit FIFO Not Full.
5475  *
5476  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5477  *
5478  * transmit FIFO in not full.
5479  *
5480  * 0 = Transmit FIFO is full
5481  *
5482  * 1 = Transmit FIFO is not full
5483  *
5484  * This bit is cleared when the TX FIFO is full.
5485  *
5486  * Field Enumeration Values:
5487  *
5488  * Enum | Value | Description
5489  * :----------------------------|:------|:--------------------------
5490  * ALT_UART_USR_TFNF_E_FULL | 0x0 | Transmit FIFO is full
5491  * ALT_UART_USR_TFNF_E_NOTFULL | 0x1 | Transmit FIFO is not full
5492  *
5493  * Field Access Macros:
5494  *
5495  */
5496 /*
5497  * Enumerated value for register field ALT_UART_USR_TFNF
5498  *
5499  * Transmit FIFO is full
5500  */
5501 #define ALT_UART_USR_TFNF_E_FULL 0x0
5502 /*
5503  * Enumerated value for register field ALT_UART_USR_TFNF
5504  *
5505  * Transmit FIFO is not full
5506  */
5507 #define ALT_UART_USR_TFNF_E_NOTFULL 0x1
5508 
5509 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFNF register field. */
5510 #define ALT_UART_USR_TFNF_LSB 1
5511 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFNF register field. */
5512 #define ALT_UART_USR_TFNF_MSB 1
5513 /* The width in bits of the ALT_UART_USR_TFNF register field. */
5514 #define ALT_UART_USR_TFNF_WIDTH 1
5515 /* The mask used to set the ALT_UART_USR_TFNF register field value. */
5516 #define ALT_UART_USR_TFNF_SET_MSK 0x00000002
5517 /* The mask used to clear the ALT_UART_USR_TFNF register field value. */
5518 #define ALT_UART_USR_TFNF_CLR_MSK 0xfffffffd
5519 /* The reset value of the ALT_UART_USR_TFNF register field. */
5520 #define ALT_UART_USR_TFNF_RESET 0x1
5521 /* Extracts the ALT_UART_USR_TFNF field value from a register. */
5522 #define ALT_UART_USR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
5523 /* Produces a ALT_UART_USR_TFNF register field value suitable for setting the register. */
5524 #define ALT_UART_USR_TFNF_SET(value) (((value) << 1) & 0x00000002)
5525 
5526 /*
5527  * Field : tfe
5528  *
5529  * Transmit FIFO Empty.
5530  *
5531  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5532  *
5533  * transmit FIFO is completely empty.
5534  *
5535  * 0 = Transmit FIFO is not empty
5536  *
5537  * 1 = Transmit FIFO is empty
5538  *
5539  * This bit is cleared when the TX FIFO is no longer empty.
5540  *
5541  * Field Enumeration Values:
5542  *
5543  * Enum | Value | Description
5544  * :----------------------------|:------|:---------------------------
5545  * ALT_UART_USR_TFE_E_NOTEMPTY | 0x0 | Transmit FIFO is not empty
5546  * ALT_UART_USR_TFE_E_EMPTY | 0x1 | Transmit FIFO is empty
5547  *
5548  * Field Access Macros:
5549  *
5550  */
5551 /*
5552  * Enumerated value for register field ALT_UART_USR_TFE
5553  *
5554  * Transmit FIFO is not empty
5555  */
5556 #define ALT_UART_USR_TFE_E_NOTEMPTY 0x0
5557 /*
5558  * Enumerated value for register field ALT_UART_USR_TFE
5559  *
5560  * Transmit FIFO is empty
5561  */
5562 #define ALT_UART_USR_TFE_E_EMPTY 0x1
5563 
5564 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_TFE register field. */
5565 #define ALT_UART_USR_TFE_LSB 2
5566 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_TFE register field. */
5567 #define ALT_UART_USR_TFE_MSB 2
5568 /* The width in bits of the ALT_UART_USR_TFE register field. */
5569 #define ALT_UART_USR_TFE_WIDTH 1
5570 /* The mask used to set the ALT_UART_USR_TFE register field value. */
5571 #define ALT_UART_USR_TFE_SET_MSK 0x00000004
5572 /* The mask used to clear the ALT_UART_USR_TFE register field value. */
5573 #define ALT_UART_USR_TFE_CLR_MSK 0xfffffffb
5574 /* The reset value of the ALT_UART_USR_TFE register field. */
5575 #define ALT_UART_USR_TFE_RESET 0x1
5576 /* Extracts the ALT_UART_USR_TFE field value from a register. */
5577 #define ALT_UART_USR_TFE_GET(value) (((value) & 0x00000004) >> 2)
5578 /* Produces a ALT_UART_USR_TFE register field value suitable for setting the register. */
5579 #define ALT_UART_USR_TFE_SET(value) (((value) << 2) & 0x00000004)
5580 
5581 /*
5582  * Field : rfne
5583  *
5584  * Receive FIFO Not Empty.
5585  *
5586  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5587  *
5588  * receive FIFO contains one or more entries.
5589  *
5590  * 0 = Receive FIFO is empty
5591  *
5592  * 1 = Receive FIFO is not empty
5593  *
5594  * This bit is cleared when the RX FIFO is empty.
5595  *
5596  * Field Enumeration Values:
5597  *
5598  * Enum | Value | Description
5599  * :-----------------------------|:------|:--------------------------
5600  * ALT_UART_USR_RFNE_E_EMPTY | 0x0 | Receiive FIFO is empty
5601  * ALT_UART_USR_RFNE_E_NOTEMPTY | 0x1 | Receive FIFO is not empty
5602  *
5603  * Field Access Macros:
5604  *
5605  */
5606 /*
5607  * Enumerated value for register field ALT_UART_USR_RFNE
5608  *
5609  * Receiive FIFO is empty
5610  */
5611 #define ALT_UART_USR_RFNE_E_EMPTY 0x0
5612 /*
5613  * Enumerated value for register field ALT_UART_USR_RFNE
5614  *
5615  * Receive FIFO is not empty
5616  */
5617 #define ALT_UART_USR_RFNE_E_NOTEMPTY 0x1
5618 
5619 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFNE register field. */
5620 #define ALT_UART_USR_RFNE_LSB 3
5621 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFNE register field. */
5622 #define ALT_UART_USR_RFNE_MSB 3
5623 /* The width in bits of the ALT_UART_USR_RFNE register field. */
5624 #define ALT_UART_USR_RFNE_WIDTH 1
5625 /* The mask used to set the ALT_UART_USR_RFNE register field value. */
5626 #define ALT_UART_USR_RFNE_SET_MSK 0x00000008
5627 /* The mask used to clear the ALT_UART_USR_RFNE register field value. */
5628 #define ALT_UART_USR_RFNE_CLR_MSK 0xfffffff7
5629 /* The reset value of the ALT_UART_USR_RFNE register field. */
5630 #define ALT_UART_USR_RFNE_RESET 0x0
5631 /* Extracts the ALT_UART_USR_RFNE field value from a register. */
5632 #define ALT_UART_USR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
5633 /* Produces a ALT_UART_USR_RFNE register field value suitable for setting the register. */
5634 #define ALT_UART_USR_RFNE_SET(value) (((value) << 3) & 0x00000008)
5635 
5636 /*
5637  * Field : rff
5638  *
5639  * Receive FIFO Full.
5640  *
5641  * This bit is only valid when FIFO_STAT == YES. This is used to indicate that the
5642  *
5643  * receive FIFO is completely full. That is:
5644  *
5645  * 0 = Receive FIFO not full
5646  *
5647  * 1 = Receive FIFO Full
5648  *
5649  * This bit is cleared when the RX FIFO is no longer full.
5650  *
5651  * Field Enumeration Values:
5652  *
5653  * Enum | Value | Description
5654  * :---------------------------|:------|:-----------------------
5655  * ALT_UART_USR_RFF_E_NOTFULL | 0x0 | Receiive FIFO not full
5656  * ALT_UART_USR_RFF_E_FULL | 0x1 | Transmit FIFO is full
5657  *
5658  * Field Access Macros:
5659  *
5660  */
5661 /*
5662  * Enumerated value for register field ALT_UART_USR_RFF
5663  *
5664  * Receiive FIFO not full
5665  */
5666 #define ALT_UART_USR_RFF_E_NOTFULL 0x0
5667 /*
5668  * Enumerated value for register field ALT_UART_USR_RFF
5669  *
5670  * Transmit FIFO is full
5671  */
5672 #define ALT_UART_USR_RFF_E_FULL 0x1
5673 
5674 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RFF register field. */
5675 #define ALT_UART_USR_RFF_LSB 4
5676 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RFF register field. */
5677 #define ALT_UART_USR_RFF_MSB 4
5678 /* The width in bits of the ALT_UART_USR_RFF register field. */
5679 #define ALT_UART_USR_RFF_WIDTH 1
5680 /* The mask used to set the ALT_UART_USR_RFF register field value. */
5681 #define ALT_UART_USR_RFF_SET_MSK 0x00000010
5682 /* The mask used to clear the ALT_UART_USR_RFF register field value. */
5683 #define ALT_UART_USR_RFF_CLR_MSK 0xffffffef
5684 /* The reset value of the ALT_UART_USR_RFF register field. */
5685 #define ALT_UART_USR_RFF_RESET 0x0
5686 /* Extracts the ALT_UART_USR_RFF field value from a register. */
5687 #define ALT_UART_USR_RFF_GET(value) (((value) & 0x00000010) >> 4)
5688 /* Produces a ALT_UART_USR_RFF register field value suitable for setting the register. */
5689 #define ALT_UART_USR_RFF_SET(value) (((value) << 4) & 0x00000010)
5690 
5691 /*
5692  * Field : rsvd_usr_31to5
5693  *
5694  * Reserved bits [31:5] - Read Only
5695  *
5696  * Field Access Macros:
5697  *
5698  */
5699 /* The Least Significant Bit (LSB) position of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5700 #define ALT_UART_USR_RSVD_USR_31TO5_LSB 5
5701 /* The Most Significant Bit (MSB) position of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5702 #define ALT_UART_USR_RSVD_USR_31TO5_MSB 31
5703 /* The width in bits of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5704 #define ALT_UART_USR_RSVD_USR_31TO5_WIDTH 27
5705 /* The mask used to set the ALT_UART_USR_RSVD_USR_31TO5 register field value. */
5706 #define ALT_UART_USR_RSVD_USR_31TO5_SET_MSK 0xffffffe0
5707 /* The mask used to clear the ALT_UART_USR_RSVD_USR_31TO5 register field value. */
5708 #define ALT_UART_USR_RSVD_USR_31TO5_CLR_MSK 0x0000001f
5709 /* The reset value of the ALT_UART_USR_RSVD_USR_31TO5 register field. */
5710 #define ALT_UART_USR_RSVD_USR_31TO5_RESET 0x0
5711 /* Extracts the ALT_UART_USR_RSVD_USR_31TO5 field value from a register. */
5712 #define ALT_UART_USR_RSVD_USR_31TO5_GET(value) (((value) & 0xffffffe0) >> 5)
5713 /* Produces a ALT_UART_USR_RSVD_USR_31TO5 register field value suitable for setting the register. */
5714 #define ALT_UART_USR_RSVD_USR_31TO5_SET(value) (((value) << 5) & 0xffffffe0)
5715 
5716 #ifndef __ASSEMBLY__
5717 /*
5718  * WARNING: The C register and register group struct declarations are provided for
5719  * convenience and illustrative purposes. They should, however, be used with
5720  * caution as the C language standard provides no guarantees about the alignment or
5721  * atomicity of device memory accesses. The recommended practice for writing
5722  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5723  * alt_write_word() functions.
5724  *
5725  * The struct declaration for register ALT_UART_USR.
5726  */
5727 struct ALT_UART_USR_s
5728 {
5729  const uint32_t rsvd_busy : 1; /* ALT_UART_USR_RSVD_BUSY */
5730  const uint32_t tfnf : 1; /* ALT_UART_USR_TFNF */
5731  const uint32_t tfe : 1; /* ALT_UART_USR_TFE */
5732  const uint32_t rfne : 1; /* ALT_UART_USR_RFNE */
5733  const uint32_t rff : 1; /* ALT_UART_USR_RFF */
5734  const uint32_t rsvd_usr_31to5 : 27; /* ALT_UART_USR_RSVD_USR_31TO5 */
5735 };
5736 
5737 /* The typedef declaration for register ALT_UART_USR. */
5738 typedef volatile struct ALT_UART_USR_s ALT_UART_USR_t;
5739 #endif /* __ASSEMBLY__ */
5740 
5741 /* The reset value of the ALT_UART_USR register. */
5742 #define ALT_UART_USR_RESET 0x00000006
5743 /* The byte offset of the ALT_UART_USR register from the beginning of the component. */
5744 #define ALT_UART_USR_OFST 0x7c
5745 /* The address of the ALT_UART_USR register. */
5746 #define ALT_UART_USR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_USR_OFST))
5747 
5748 /*
5749  * Register : tfl
5750  *
5751  * Register Layout
5752  *
5753  * Bits | Access | Reset | Description
5754  * :-------|:-------|:------|:-------------------------------------
5755  * [7:0] | R | 0x0 | ALT_UART_TFL_TFL
5756  * [31:8] | R | 0x0 | ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH
5757  *
5758  */
5759 /*
5760  * Field : tfl
5761  *
5762  * Transmit FIFO Level.
5763  *
5764  * This is indicates the number of data entries in the transmit FIFO.
5765  *
5766  * Field Access Macros:
5767  *
5768  */
5769 /* The Least Significant Bit (LSB) position of the ALT_UART_TFL_TFL register field. */
5770 #define ALT_UART_TFL_TFL_LSB 0
5771 /* The Most Significant Bit (MSB) position of the ALT_UART_TFL_TFL register field. */
5772 #define ALT_UART_TFL_TFL_MSB 7
5773 /* The width in bits of the ALT_UART_TFL_TFL register field. */
5774 #define ALT_UART_TFL_TFL_WIDTH 8
5775 /* The mask used to set the ALT_UART_TFL_TFL register field value. */
5776 #define ALT_UART_TFL_TFL_SET_MSK 0x000000ff
5777 /* The mask used to clear the ALT_UART_TFL_TFL register field value. */
5778 #define ALT_UART_TFL_TFL_CLR_MSK 0xffffff00
5779 /* The reset value of the ALT_UART_TFL_TFL register field. */
5780 #define ALT_UART_TFL_TFL_RESET 0x0
5781 /* Extracts the ALT_UART_TFL_TFL field value from a register. */
5782 #define ALT_UART_TFL_TFL_GET(value) (((value) & 0x000000ff) >> 0)
5783 /* Produces a ALT_UART_TFL_TFL register field value suitable for setting the register. */
5784 #define ALT_UART_TFL_TFL_SET(value) (((value) << 0) & 0x000000ff)
5785 
5786 /*
5787  * Field : rsvd_tfl_31toaddr_width
5788  *
5789  * Reserved bits: 31 downto addr bus width + 1 - Read Only
5790  *
5791  * Field Access Macros:
5792  *
5793  */
5794 /* The Least Significant Bit (LSB) position of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5795 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_LSB 8
5796 /* The Most Significant Bit (MSB) position of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5797 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_MSB 31
5798 /* The width in bits of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5799 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_WIDTH 24
5800 /* The mask used to set the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value. */
5801 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_SET_MSK 0xffffff00
5802 /* The mask used to clear the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value. */
5803 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_CLR_MSK 0x000000ff
5804 /* The reset value of the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field. */
5805 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_RESET 0x0
5806 /* Extracts the ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH field value from a register. */
5807 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_GET(value) (((value) & 0xffffff00) >> 8)
5808 /* Produces a ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH register field value suitable for setting the register. */
5809 #define ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH_SET(value) (((value) << 8) & 0xffffff00)
5810 
5811 #ifndef __ASSEMBLY__
5812 /*
5813  * WARNING: The C register and register group struct declarations are provided for
5814  * convenience and illustrative purposes. They should, however, be used with
5815  * caution as the C language standard provides no guarantees about the alignment or
5816  * atomicity of device memory accesses. The recommended practice for writing
5817  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5818  * alt_write_word() functions.
5819  *
5820  * The struct declaration for register ALT_UART_TFL.
5821  */
5822 struct ALT_UART_TFL_s
5823 {
5824  const uint32_t tfl : 8; /* ALT_UART_TFL_TFL */
5825  const uint32_t rsvd_tfl_31toaddr_width : 24; /* ALT_UART_TFL_RSVD_TFL_31TOADDR_WIDTH */
5826 };
5827 
5828 /* The typedef declaration for register ALT_UART_TFL. */
5829 typedef volatile struct ALT_UART_TFL_s ALT_UART_TFL_t;
5830 #endif /* __ASSEMBLY__ */
5831 
5832 /* The reset value of the ALT_UART_TFL register. */
5833 #define ALT_UART_TFL_RESET 0x00000000
5834 /* The byte offset of the ALT_UART_TFL register from the beginning of the component. */
5835 #define ALT_UART_TFL_OFST 0x80
5836 /* The address of the ALT_UART_TFL register. */
5837 #define ALT_UART_TFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_TFL_OFST))
5838 
5839 /*
5840  * Register : rfl
5841  *
5842  * Receive FIFO Level.
5843  *
5844  * Register Layout
5845  *
5846  * Bits | Access | Reset | Description
5847  * :-------|:-------|:------|:-------------------------------------
5848  * [7:0] | R | 0x0 | ALT_UART_RFL_RFL
5849  * [31:8] | R | 0x0 | ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH
5850  *
5851  */
5852 /*
5853  * Field : rfl
5854  *
5855  * Receive FIFO Level.
5856  *
5857  * This is indicates the number of data entries in the receive FIFO.
5858  *
5859  * Field Access Macros:
5860  *
5861  */
5862 /* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RFL register field. */
5863 #define ALT_UART_RFL_RFL_LSB 0
5864 /* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RFL register field. */
5865 #define ALT_UART_RFL_RFL_MSB 7
5866 /* The width in bits of the ALT_UART_RFL_RFL register field. */
5867 #define ALT_UART_RFL_RFL_WIDTH 8
5868 /* The mask used to set the ALT_UART_RFL_RFL register field value. */
5869 #define ALT_UART_RFL_RFL_SET_MSK 0x000000ff
5870 /* The mask used to clear the ALT_UART_RFL_RFL register field value. */
5871 #define ALT_UART_RFL_RFL_CLR_MSK 0xffffff00
5872 /* The reset value of the ALT_UART_RFL_RFL register field. */
5873 #define ALT_UART_RFL_RFL_RESET 0x0
5874 /* Extracts the ALT_UART_RFL_RFL field value from a register. */
5875 #define ALT_UART_RFL_RFL_GET(value) (((value) & 0x000000ff) >> 0)
5876 /* Produces a ALT_UART_RFL_RFL register field value suitable for setting the register. */
5877 #define ALT_UART_RFL_RFL_SET(value) (((value) << 0) & 0x000000ff)
5878 
5879 /*
5880  * Field : rsvd_rfl_31toaddr_width
5881  *
5882  * Reserved bits: 31 downnto addr bus width + 1 - Read Only
5883  *
5884  * Field Access Macros:
5885  *
5886  */
5887 /* The Least Significant Bit (LSB) position of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5888 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_LSB 8
5889 /* The Most Significant Bit (MSB) position of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5890 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_MSB 31
5891 /* The width in bits of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5892 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_WIDTH 24
5893 /* The mask used to set the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value. */
5894 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_SET_MSK 0xffffff00
5895 /* The mask used to clear the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value. */
5896 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_CLR_MSK 0x000000ff
5897 /* The reset value of the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field. */
5898 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_RESET 0x0
5899 /* Extracts the ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH field value from a register. */
5900 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_GET(value) (((value) & 0xffffff00) >> 8)
5901 /* Produces a ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH register field value suitable for setting the register. */
5902 #define ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH_SET(value) (((value) << 8) & 0xffffff00)
5903 
5904 #ifndef __ASSEMBLY__
5905 /*
5906  * WARNING: The C register and register group struct declarations are provided for
5907  * convenience and illustrative purposes. They should, however, be used with
5908  * caution as the C language standard provides no guarantees about the alignment or
5909  * atomicity of device memory accesses. The recommended practice for writing
5910  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5911  * alt_write_word() functions.
5912  *
5913  * The struct declaration for register ALT_UART_RFL.
5914  */
5915 struct ALT_UART_RFL_s
5916 {
5917  const uint32_t rfl : 8; /* ALT_UART_RFL_RFL */
5918  const uint32_t rsvd_rfl_31toaddr_width : 24; /* ALT_UART_RFL_RSVD_RFL_31TOADDR_WIDTH */
5919 };
5920 
5921 /* The typedef declaration for register ALT_UART_RFL. */
5922 typedef volatile struct ALT_UART_RFL_s ALT_UART_RFL_t;
5923 #endif /* __ASSEMBLY__ */
5924 
5925 /* The reset value of the ALT_UART_RFL register. */
5926 #define ALT_UART_RFL_RESET 0x00000000
5927 /* The byte offset of the ALT_UART_RFL register from the beginning of the component. */
5928 #define ALT_UART_RFL_OFST 0x84
5929 /* The address of the ALT_UART_RFL register. */
5930 #define ALT_UART_RFL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RFL_OFST))
5931 
5932 /*
5933  * Register : srr
5934  *
5935  * Software Reset Register.
5936  *
5937  * Register Layout
5938  *
5939  * Bits | Access | Reset | Description
5940  * :-------|:-------|:------|:----------------------------
5941  * [0] | W | 0x0 | ALT_UART_SRR_UR
5942  * [1] | W | 0x0 | ALT_UART_SRR_RFR
5943  * [2] | W | 0x0 | ALT_UART_SRR_XFR
5944  * [31:3] | R | 0x0 | ALT_UART_SRR_RSVD_SRR_31TO3
5945  *
5946  */
5947 /*
5948  * Field : ur
5949  *
5950  * UART Reset.
5951  *
5952  * This asynchronously resets the DW_apb_uart and synchronously removes the reset
5953  *
5954  * assertion. For a two clock implementation both pclk and sclk domains will be
5955  * reset.
5956  *
5957  * Field Enumeration Values:
5958  *
5959  * Enum | Value | Description
5960  * :------------------------|:------|:--------------
5961  * ALT_UART_SRR_UR_E_NORST | 0x0 | No reset Uart
5962  * ALT_UART_SRR_UR_E_RST | 0x1 | Reset Uart
5963  *
5964  * Field Access Macros:
5965  *
5966  */
5967 /*
5968  * Enumerated value for register field ALT_UART_SRR_UR
5969  *
5970  * No reset Uart
5971  */
5972 #define ALT_UART_SRR_UR_E_NORST 0x0
5973 /*
5974  * Enumerated value for register field ALT_UART_SRR_UR
5975  *
5976  * Reset Uart
5977  */
5978 #define ALT_UART_SRR_UR_E_RST 0x1
5979 
5980 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field. */
5981 #define ALT_UART_SRR_UR_LSB 0
5982 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field. */
5983 #define ALT_UART_SRR_UR_MSB 0
5984 /* The width in bits of the ALT_UART_SRR_UR register field. */
5985 #define ALT_UART_SRR_UR_WIDTH 1
5986 /* The mask used to set the ALT_UART_SRR_UR register field value. */
5987 #define ALT_UART_SRR_UR_SET_MSK 0x00000001
5988 /* The mask used to clear the ALT_UART_SRR_UR register field value. */
5989 #define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe
5990 /* The reset value of the ALT_UART_SRR_UR register field. */
5991 #define ALT_UART_SRR_UR_RESET 0x0
5992 /* Extracts the ALT_UART_SRR_UR field value from a register. */
5993 #define ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0)
5994 /* Produces a ALT_UART_SRR_UR register field value suitable for setting the register. */
5995 #define ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001)
5996 
5997 /*
5998  * Field : rfr
5999  *
6000  * RCVR FIFO Reset.
6001  *
6002  * Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for
6003  *
6004  * the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on
6005  * software
6006  *
6007  * having to store previously written FCR values (which are pretty static) just to
6008  *
6009  * reset the reeive FIFO.
6010  *
6011  * This resets the control portion of the receive FIFO and treats the FIFO as
6012  * empty.
6013  *
6014  * This will also de-assert the DMA RX request and single signals when additional
6015  * DMA
6016  *
6017  * handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
6018  *
6019  * 'self-clearing' and it is not necessary to clear this bit.
6020  *
6021  * Field Enumeration Values:
6022  *
6023  * Enum | Value | Description
6024  * :-------------------------|:------|:-----------------
6025  * ALT_UART_SRR_RFR_E_NORST | 0x0 | No reset Rx FIFO
6026  * ALT_UART_SRR_RFR_E_RST | 0x1 | Reset Rx FIFO
6027  *
6028  * Field Access Macros:
6029  *
6030  */
6031 /*
6032  * Enumerated value for register field ALT_UART_SRR_RFR
6033  *
6034  * No reset Rx FIFO
6035  */
6036 #define ALT_UART_SRR_RFR_E_NORST 0x0
6037 /*
6038  * Enumerated value for register field ALT_UART_SRR_RFR
6039  *
6040  * Reset Rx FIFO
6041  */
6042 #define ALT_UART_SRR_RFR_E_RST 0x1
6043 
6044 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field. */
6045 #define ALT_UART_SRR_RFR_LSB 1
6046 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field. */
6047 #define ALT_UART_SRR_RFR_MSB 1
6048 /* The width in bits of the ALT_UART_SRR_RFR register field. */
6049 #define ALT_UART_SRR_RFR_WIDTH 1
6050 /* The mask used to set the ALT_UART_SRR_RFR register field value. */
6051 #define ALT_UART_SRR_RFR_SET_MSK 0x00000002
6052 /* The mask used to clear the ALT_UART_SRR_RFR register field value. */
6053 #define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd
6054 /* The reset value of the ALT_UART_SRR_RFR register field. */
6055 #define ALT_UART_SRR_RFR_RESET 0x0
6056 /* Extracts the ALT_UART_SRR_RFR field value from a register. */
6057 #define ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1)
6058 /* Produces a ALT_UART_SRR_RFR register field value suitable for setting the register. */
6059 #define ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002)
6060 
6061 /*
6062  * Field : xfr
6063  *
6064  * XMIT FIFO Reset.
6065  *
6066  * Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for
6067  *
6068  * the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on
6069  * software
6070  *
6071  * having to store previously written FCR values (which are pretty static) just to
6072  *
6073  * reset the transmit FIFO.
6074  *
6075  * This resets the control portion of the transmit FIFO and treats the FIFO as
6076  * empty.
6077  *
6078  * This will also de-assert the DMA TX request and single signals when additional
6079  * DMA
6080  *
6081  * handshaking signals are selected
6082  *
6083  * Field Enumeration Values:
6084  *
6085  * Enum | Value | Description
6086  * :-------------------------|:------|:-----------------
6087  * ALT_UART_SRR_XFR_E_NORST | 0x0 | No reset Tx FIFO
6088  * ALT_UART_SRR_XFR_E_RST | 0x1 | Reset Tx FIFO
6089  *
6090  * Field Access Macros:
6091  *
6092  */
6093 /*
6094  * Enumerated value for register field ALT_UART_SRR_XFR
6095  *
6096  * No reset Tx FIFO
6097  */
6098 #define ALT_UART_SRR_XFR_E_NORST 0x0
6099 /*
6100  * Enumerated value for register field ALT_UART_SRR_XFR
6101  *
6102  * Reset Tx FIFO
6103  */
6104 #define ALT_UART_SRR_XFR_E_RST 0x1
6105 
6106 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field. */
6107 #define ALT_UART_SRR_XFR_LSB 2
6108 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field. */
6109 #define ALT_UART_SRR_XFR_MSB 2
6110 /* The width in bits of the ALT_UART_SRR_XFR register field. */
6111 #define ALT_UART_SRR_XFR_WIDTH 1
6112 /* The mask used to set the ALT_UART_SRR_XFR register field value. */
6113 #define ALT_UART_SRR_XFR_SET_MSK 0x00000004
6114 /* The mask used to clear the ALT_UART_SRR_XFR register field value. */
6115 #define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb
6116 /* The reset value of the ALT_UART_SRR_XFR register field. */
6117 #define ALT_UART_SRR_XFR_RESET 0x0
6118 /* Extracts the ALT_UART_SRR_XFR field value from a register. */
6119 #define ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2)
6120 /* Produces a ALT_UART_SRR_XFR register field value suitable for setting the register. */
6121 #define ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004)
6122 
6123 /*
6124  * Field : rsvd_srr_31to3
6125  *
6126  * Reserved bits [31:3] - Read Only
6127  *
6128  * Field Access Macros:
6129  *
6130  */
6131 /* The Least Significant Bit (LSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
6132 #define ALT_UART_SRR_RSVD_SRR_31TO3_LSB 3
6133 /* The Most Significant Bit (MSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
6134 #define ALT_UART_SRR_RSVD_SRR_31TO3_MSB 31
6135 /* The width in bits of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
6136 #define ALT_UART_SRR_RSVD_SRR_31TO3_WIDTH 29
6137 /* The mask used to set the ALT_UART_SRR_RSVD_SRR_31TO3 register field value. */
6138 #define ALT_UART_SRR_RSVD_SRR_31TO3_SET_MSK 0xfffffff8
6139 /* The mask used to clear the ALT_UART_SRR_RSVD_SRR_31TO3 register field value. */
6140 #define ALT_UART_SRR_RSVD_SRR_31TO3_CLR_MSK 0x00000007
6141 /* The reset value of the ALT_UART_SRR_RSVD_SRR_31TO3 register field. */
6142 #define ALT_UART_SRR_RSVD_SRR_31TO3_RESET 0x0
6143 /* Extracts the ALT_UART_SRR_RSVD_SRR_31TO3 field value from a register. */
6144 #define ALT_UART_SRR_RSVD_SRR_31TO3_GET(value) (((value) & 0xfffffff8) >> 3)
6145 /* Produces a ALT_UART_SRR_RSVD_SRR_31TO3 register field value suitable for setting the register. */
6146 #define ALT_UART_SRR_RSVD_SRR_31TO3_SET(value) (((value) << 3) & 0xfffffff8)
6147 
6148 #ifndef __ASSEMBLY__
6149 /*
6150  * WARNING: The C register and register group struct declarations are provided for
6151  * convenience and illustrative purposes. They should, however, be used with
6152  * caution as the C language standard provides no guarantees about the alignment or
6153  * atomicity of device memory accesses. The recommended practice for writing
6154  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6155  * alt_write_word() functions.
6156  *
6157  * The struct declaration for register ALT_UART_SRR.
6158  */
6159 struct ALT_UART_SRR_s
6160 {
6161  uint32_t ur : 1; /* ALT_UART_SRR_UR */
6162  uint32_t rfr : 1; /* ALT_UART_SRR_RFR */
6163  uint32_t xfr : 1; /* ALT_UART_SRR_XFR */
6164  const uint32_t rsvd_srr_31to3 : 29; /* ALT_UART_SRR_RSVD_SRR_31TO3 */
6165 };
6166 
6167 /* The typedef declaration for register ALT_UART_SRR. */
6168 typedef volatile struct ALT_UART_SRR_s ALT_UART_SRR_t;
6169 #endif /* __ASSEMBLY__ */
6170 
6171 /* The reset value of the ALT_UART_SRR register. */
6172 #define ALT_UART_SRR_RESET 0x00000000
6173 /* The byte offset of the ALT_UART_SRR register from the beginning of the component. */
6174 #define ALT_UART_SRR_OFST 0x88
6175 /* The address of the ALT_UART_SRR register. */
6176 #define ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST))
6177 
6178 /*
6179  * Register : srts
6180  *
6181  * Shadow Request to Send.
6182  *
6183  * Register Layout
6184  *
6185  * Bits | Access | Reset | Description
6186  * :-------|:-------|:------|:------------------------------
6187  * [0] | RW | 0x0 | ALT_UART_SRTS_SRTS
6188  * [31:1] | R | 0x0 | ALT_UART_SRTS_RSVD_SRTS_31TO1
6189  *
6190  */
6191 /*
6192  * Field : srts
6193  *
6194  * Shadow Request to Send.
6195  *
6196  * This is a shadow register for the RTS bit (MCR[1]), this can be used to remove
6197  * the
6198  *
6199  * burden of having to performing a read modify write on the MCR.
6200  *
6201  * This is used to directly control the Request to Send (rts_n) output. The Request
6202  *
6203  * To Send (rts_n) output is used to inform the modem or data set that the UART is
6204  * ready
6205  *
6206  * to exchange data.
6207  *
6208  * When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal
6209  * is
6210  *
6211  * set low by programming MCR[1] (RTS) to a high.
6212  *
6213  * In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and
6214  * FIFO's
6215  *
6216  * enable (FCR[0] set to one), the rts_n output is controlled in the same way, but
6217  * is
6218  *
6219  * also gated with the receiver FIFO threshold trigger (rts_n is inactive high when
6220  *
6221  * above the threshold) only when RTC Flow Trigger is disabled; otherwise it is
6222  * gated by the
6223  *
6224  * receiver FIFO almost-full trigger, where almost full refers to two available
6225  * slots in
6226  *
6227  * the FIFO (rts_n is inactive high when above the threshold).
6228  *
6229  * Note that in Loopback mode (MCR[4] set to one), the rts_n output is held
6230  * inactive
6231  *
6232  * high while the value of this location is internally looped back to an input.
6233  *
6234  * Field Enumeration Values:
6235  *
6236  * Enum | Value | Description
6237  * :----------------------------|:------|:------------------
6238  * ALT_UART_SRTS_SRTS_E_LOGIC1 | 0x0 | uart_rts_n logic1
6239  * ALT_UART_SRTS_SRTS_E_LOGIC0 | 0x1 | uart_rts_n logic0
6240  *
6241  * Field Access Macros:
6242  *
6243  */
6244 /*
6245  * Enumerated value for register field ALT_UART_SRTS_SRTS
6246  *
6247  * uart_rts_n logic1
6248  */
6249 #define ALT_UART_SRTS_SRTS_E_LOGIC1 0x0
6250 /*
6251  * Enumerated value for register field ALT_UART_SRTS_SRTS
6252  *
6253  * uart_rts_n logic0
6254  */
6255 #define ALT_UART_SRTS_SRTS_E_LOGIC0 0x1
6256 
6257 /* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_SRTS register field. */
6258 #define ALT_UART_SRTS_SRTS_LSB 0
6259 /* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_SRTS register field. */
6260 #define ALT_UART_SRTS_SRTS_MSB 0
6261 /* The width in bits of the ALT_UART_SRTS_SRTS register field. */
6262 #define ALT_UART_SRTS_SRTS_WIDTH 1
6263 /* The mask used to set the ALT_UART_SRTS_SRTS register field value. */
6264 #define ALT_UART_SRTS_SRTS_SET_MSK 0x00000001
6265 /* The mask used to clear the ALT_UART_SRTS_SRTS register field value. */
6266 #define ALT_UART_SRTS_SRTS_CLR_MSK 0xfffffffe
6267 /* The reset value of the ALT_UART_SRTS_SRTS register field. */
6268 #define ALT_UART_SRTS_SRTS_RESET 0x0
6269 /* Extracts the ALT_UART_SRTS_SRTS field value from a register. */
6270 #define ALT_UART_SRTS_SRTS_GET(value) (((value) & 0x00000001) >> 0)
6271 /* Produces a ALT_UART_SRTS_SRTS register field value suitable for setting the register. */
6272 #define ALT_UART_SRTS_SRTS_SET(value) (((value) << 0) & 0x00000001)
6273 
6274 /*
6275  * Field : rsvd_srts_31to1
6276  *
6277  * Reserved bits [31:1] - Read Only
6278  *
6279  * Field Access Macros:
6280  *
6281  */
6282 /* The Least Significant Bit (LSB) position of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
6283 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_LSB 1
6284 /* The Most Significant Bit (MSB) position of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
6285 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_MSB 31
6286 /* The width in bits of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
6287 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_WIDTH 31
6288 /* The mask used to set the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value. */
6289 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_SET_MSK 0xfffffffe
6290 /* The mask used to clear the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value. */
6291 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_CLR_MSK 0x00000001
6292 /* The reset value of the ALT_UART_SRTS_RSVD_SRTS_31TO1 register field. */
6293 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_RESET 0x0
6294 /* Extracts the ALT_UART_SRTS_RSVD_SRTS_31TO1 field value from a register. */
6295 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6296 /* Produces a ALT_UART_SRTS_RSVD_SRTS_31TO1 register field value suitable for setting the register. */
6297 #define ALT_UART_SRTS_RSVD_SRTS_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6298 
6299 #ifndef __ASSEMBLY__
6300 /*
6301  * WARNING: The C register and register group struct declarations are provided for
6302  * convenience and illustrative purposes. They should, however, be used with
6303  * caution as the C language standard provides no guarantees about the alignment or
6304  * atomicity of device memory accesses. The recommended practice for writing
6305  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6306  * alt_write_word() functions.
6307  *
6308  * The struct declaration for register ALT_UART_SRTS.
6309  */
6310 struct ALT_UART_SRTS_s
6311 {
6312  uint32_t srts : 1; /* ALT_UART_SRTS_SRTS */
6313  const uint32_t rsvd_srts_31to1 : 31; /* ALT_UART_SRTS_RSVD_SRTS_31TO1 */
6314 };
6315 
6316 /* The typedef declaration for register ALT_UART_SRTS. */
6317 typedef volatile struct ALT_UART_SRTS_s ALT_UART_SRTS_t;
6318 #endif /* __ASSEMBLY__ */
6319 
6320 /* The reset value of the ALT_UART_SRTS register. */
6321 #define ALT_UART_SRTS_RESET 0x00000000
6322 /* The byte offset of the ALT_UART_SRTS register from the beginning of the component. */
6323 #define ALT_UART_SRTS_OFST 0x8c
6324 /* The address of the ALT_UART_SRTS register. */
6325 #define ALT_UART_SRTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRTS_OFST))
6326 
6327 /*
6328  * Register : sbcr
6329  *
6330  * Shadow Break Control Register.
6331  *
6332  * Register Layout
6333  *
6334  * Bits | Access | Reset | Description
6335  * :-------|:-------|:------|:------------------------------
6336  * [0] | RW | 0x0 | ALT_UART_SBCR_SBCR
6337  * [31:1] | R | 0x0 | ALT_UART_SBCR_RSVD_SBCR_31TO1
6338  *
6339  */
6340 /*
6341  * Field : sbcr
6342  *
6343  * Shadow Break Control Bit.
6344  *
6345  * This is a shadow register for the Break bit (LCR[6]), this can be used to remove
6346  *
6347  * the burden of having to performing a read modify write on the LCR.
6348  *
6349  * This is used to cause a break condition to be transmitted to the receiving
6350  * device.
6351  *
6352  * If set to one the serial output is forced to the spacing (logic 0) state. When
6353  * not
6354  *
6355  * in Loopback Mode, as determined by MCR[4], the sout line is forced low until the
6356  *
6357  * Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the
6358  *
6359  * sir_out_n line is continuously pulsed. When in Loopback Mode, the break
6360  * condition
6361  *
6362  * is internally looped back to the receiver.
6363  *
6364  * Field Enumeration Values:
6365  *
6366  * Enum | Value | Description
6367  * :--------------------------|:------|:----------------------------
6368  * ALT_UART_SBCR_SBCR_E_DISD | 0x0 | no break
6369  * ALT_UART_SBCR_SBCR_E_END | 0x1 | break serial output spacing
6370  *
6371  * Field Access Macros:
6372  *
6373  */
6374 /*
6375  * Enumerated value for register field ALT_UART_SBCR_SBCR
6376  *
6377  * no break
6378  */
6379 #define ALT_UART_SBCR_SBCR_E_DISD 0x0
6380 /*
6381  * Enumerated value for register field ALT_UART_SBCR_SBCR
6382  *
6383  * break serial output spacing
6384  */
6385 #define ALT_UART_SBCR_SBCR_E_END 0x1
6386 
6387 /* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_SBCR register field. */
6388 #define ALT_UART_SBCR_SBCR_LSB 0
6389 /* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_SBCR register field. */
6390 #define ALT_UART_SBCR_SBCR_MSB 0
6391 /* The width in bits of the ALT_UART_SBCR_SBCR register field. */
6392 #define ALT_UART_SBCR_SBCR_WIDTH 1
6393 /* The mask used to set the ALT_UART_SBCR_SBCR register field value. */
6394 #define ALT_UART_SBCR_SBCR_SET_MSK 0x00000001
6395 /* The mask used to clear the ALT_UART_SBCR_SBCR register field value. */
6396 #define ALT_UART_SBCR_SBCR_CLR_MSK 0xfffffffe
6397 /* The reset value of the ALT_UART_SBCR_SBCR register field. */
6398 #define ALT_UART_SBCR_SBCR_RESET 0x0
6399 /* Extracts the ALT_UART_SBCR_SBCR field value from a register. */
6400 #define ALT_UART_SBCR_SBCR_GET(value) (((value) & 0x00000001) >> 0)
6401 /* Produces a ALT_UART_SBCR_SBCR register field value suitable for setting the register. */
6402 #define ALT_UART_SBCR_SBCR_SET(value) (((value) << 0) & 0x00000001)
6403 
6404 /*
6405  * Field : rsvd_sbcr_31to1
6406  *
6407  * Reserved bits [31:1] - Read Only
6408  *
6409  * Field Access Macros:
6410  *
6411  */
6412 /* The Least Significant Bit (LSB) position of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6413 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_LSB 1
6414 /* The Most Significant Bit (MSB) position of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6415 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_MSB 31
6416 /* The width in bits of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6417 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_WIDTH 31
6418 /* The mask used to set the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value. */
6419 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_SET_MSK 0xfffffffe
6420 /* The mask used to clear the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value. */
6421 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_CLR_MSK 0x00000001
6422 /* The reset value of the ALT_UART_SBCR_RSVD_SBCR_31TO1 register field. */
6423 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_RESET 0x0
6424 /* Extracts the ALT_UART_SBCR_RSVD_SBCR_31TO1 field value from a register. */
6425 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6426 /* Produces a ALT_UART_SBCR_RSVD_SBCR_31TO1 register field value suitable for setting the register. */
6427 #define ALT_UART_SBCR_RSVD_SBCR_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6428 
6429 #ifndef __ASSEMBLY__
6430 /*
6431  * WARNING: The C register and register group struct declarations are provided for
6432  * convenience and illustrative purposes. They should, however, be used with
6433  * caution as the C language standard provides no guarantees about the alignment or
6434  * atomicity of device memory accesses. The recommended practice for writing
6435  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6436  * alt_write_word() functions.
6437  *
6438  * The struct declaration for register ALT_UART_SBCR.
6439  */
6440 struct ALT_UART_SBCR_s
6441 {
6442  uint32_t sbcr : 1; /* ALT_UART_SBCR_SBCR */
6443  const uint32_t rsvd_sbcr_31to1 : 31; /* ALT_UART_SBCR_RSVD_SBCR_31TO1 */
6444 };
6445 
6446 /* The typedef declaration for register ALT_UART_SBCR. */
6447 typedef volatile struct ALT_UART_SBCR_s ALT_UART_SBCR_t;
6448 #endif /* __ASSEMBLY__ */
6449 
6450 /* The reset value of the ALT_UART_SBCR register. */
6451 #define ALT_UART_SBCR_RESET 0x00000000
6452 /* The byte offset of the ALT_UART_SBCR register from the beginning of the component. */
6453 #define ALT_UART_SBCR_OFST 0x90
6454 /* The address of the ALT_UART_SBCR register. */
6455 #define ALT_UART_SBCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SBCR_OFST))
6456 
6457 /*
6458  * Register : sdmam
6459  *
6460  * Shadow DMA Mode.
6461  *
6462  * Register Layout
6463  *
6464  * Bits | Access | Reset | Description
6465  * :-------|:-------|:------|:--------------------------------
6466  * [0] | RW | 0x0 | ALT_UART_SDMAM_SDMAM
6467  * [31:1] | R | 0x0 | ALT_UART_SDMAM_RSVD_SDMAM_31TO1
6468  *
6469  */
6470 /*
6471  * Field : sdmam
6472  *
6473  * Shadow DMA Mode.
6474  *
6475  * This is a shadow register for the DMA mode bit (FCR[3]). This can be used to
6476  * remove
6477  *
6478  * the burden of having to store the previously written value to the FCR in memory
6479  * and
6480  *
6481  * having to mask this value so that only the DMA Mode bit gets updated.
6482  *
6483  * This determines the DMA signalling mode used for the dma_tx_req_n and
6484  * dma_rx_req_n
6485  *
6486  * output signals when additional DMA handshaking signals are not selected
6487  *
6488  * (DMA_EXTRA == NO). See section 5.9 on page 54 for details on DMA support.
6489  *
6490  * 0 = mode 0
6491  *
6492  * 1 = mode 1
6493  *
6494  * Field Enumeration Values:
6495  *
6496  * Enum | Value | Description
6497  * :------------------------------|:------|:---------------------------
6498  * ALT_UART_SDMAM_SDMAM_E_SINGLE | 0x0 | Single DMA Transfer Mode
6499  * ALT_UART_SDMAM_SDMAM_E_MULT | 0x1 | Multiple DMA Transfer Mode
6500  *
6501  * Field Access Macros:
6502  *
6503  */
6504 /*
6505  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
6506  *
6507  * Single DMA Transfer Mode
6508  */
6509 #define ALT_UART_SDMAM_SDMAM_E_SINGLE 0x0
6510 /*
6511  * Enumerated value for register field ALT_UART_SDMAM_SDMAM
6512  *
6513  * Multiple DMA Transfer Mode
6514  */
6515 #define ALT_UART_SDMAM_SDMAM_E_MULT 0x1
6516 
6517 /* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_SDMAM register field. */
6518 #define ALT_UART_SDMAM_SDMAM_LSB 0
6519 /* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_SDMAM register field. */
6520 #define ALT_UART_SDMAM_SDMAM_MSB 0
6521 /* The width in bits of the ALT_UART_SDMAM_SDMAM register field. */
6522 #define ALT_UART_SDMAM_SDMAM_WIDTH 1
6523 /* The mask used to set the ALT_UART_SDMAM_SDMAM register field value. */
6524 #define ALT_UART_SDMAM_SDMAM_SET_MSK 0x00000001
6525 /* The mask used to clear the ALT_UART_SDMAM_SDMAM register field value. */
6526 #define ALT_UART_SDMAM_SDMAM_CLR_MSK 0xfffffffe
6527 /* The reset value of the ALT_UART_SDMAM_SDMAM register field. */
6528 #define ALT_UART_SDMAM_SDMAM_RESET 0x0
6529 /* Extracts the ALT_UART_SDMAM_SDMAM field value from a register. */
6530 #define ALT_UART_SDMAM_SDMAM_GET(value) (((value) & 0x00000001) >> 0)
6531 /* Produces a ALT_UART_SDMAM_SDMAM register field value suitable for setting the register. */
6532 #define ALT_UART_SDMAM_SDMAM_SET(value) (((value) << 0) & 0x00000001)
6533 
6534 /*
6535  * Field : rsvd_sdmam_31to1
6536  *
6537  * Reserved bits [31:1] - Read Only
6538  *
6539  * Field Access Macros:
6540  *
6541  */
6542 /* The Least Significant Bit (LSB) position of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6543 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_LSB 1
6544 /* The Most Significant Bit (MSB) position of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6545 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_MSB 31
6546 /* The width in bits of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6547 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_WIDTH 31
6548 /* The mask used to set the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value. */
6549 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_SET_MSK 0xfffffffe
6550 /* The mask used to clear the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value. */
6551 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_CLR_MSK 0x00000001
6552 /* The reset value of the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field. */
6553 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_RESET 0x0
6554 /* Extracts the ALT_UART_SDMAM_RSVD_SDMAM_31TO1 field value from a register. */
6555 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6556 /* Produces a ALT_UART_SDMAM_RSVD_SDMAM_31TO1 register field value suitable for setting the register. */
6557 #define ALT_UART_SDMAM_RSVD_SDMAM_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6558 
6559 #ifndef __ASSEMBLY__
6560 /*
6561  * WARNING: The C register and register group struct declarations are provided for
6562  * convenience and illustrative purposes. They should, however, be used with
6563  * caution as the C language standard provides no guarantees about the alignment or
6564  * atomicity of device memory accesses. The recommended practice for writing
6565  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6566  * alt_write_word() functions.
6567  *
6568  * The struct declaration for register ALT_UART_SDMAM.
6569  */
6570 struct ALT_UART_SDMAM_s
6571 {
6572  uint32_t sdmam : 1; /* ALT_UART_SDMAM_SDMAM */
6573  const uint32_t rsvd_sdmam_31to1 : 31; /* ALT_UART_SDMAM_RSVD_SDMAM_31TO1 */
6574 };
6575 
6576 /* The typedef declaration for register ALT_UART_SDMAM. */
6577 typedef volatile struct ALT_UART_SDMAM_s ALT_UART_SDMAM_t;
6578 #endif /* __ASSEMBLY__ */
6579 
6580 /* The reset value of the ALT_UART_SDMAM register. */
6581 #define ALT_UART_SDMAM_RESET 0x00000000
6582 /* The byte offset of the ALT_UART_SDMAM register from the beginning of the component. */
6583 #define ALT_UART_SDMAM_OFST 0x94
6584 /* The address of the ALT_UART_SDMAM register. */
6585 #define ALT_UART_SDMAM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SDMAM_OFST))
6586 
6587 /*
6588  * Register : sfe
6589  *
6590  * Shadow FIFO Enable
6591  *
6592  * Register Layout
6593  *
6594  * Bits | Access | Reset | Description
6595  * :-------|:-------|:------|:----------------------------
6596  * [0] | RW | 0x0 | ALT_UART_SFE_SFE
6597  * [31:1] | R | 0x0 | ALT_UART_SFE_RSVD_SFE_31TO1
6598  *
6599  */
6600 /*
6601  * Field : sfe
6602  *
6603  * Shadow FIFO Enable.
6604  *
6605  * This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to
6606  *
6607  * remove the burden of having to store the previously written value to the FCR in
6608  *
6609  * memory and having to mask this value so that only the FIFO enable bit gets
6610  * updated.
6611  *
6612  * This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. If this
6613  *
6614  * bit is set to zero (disabled) after being enabled then both the XMIT and RCVR
6615  *
6616  * controller portion of FIFO's will be reset.
6617  *
6618  * Field Enumeration Values:
6619  *
6620  * Enum | Value | Description
6621  * :------------------------|:------|:--------------
6622  * ALT_UART_SFE_SFE_E_DISD | 0x0 | Disable Rx/Tx
6623  * ALT_UART_SFE_SFE_E_END | 0x1 | Enable Rx/Tx
6624  *
6625  * Field Access Macros:
6626  *
6627  */
6628 /*
6629  * Enumerated value for register field ALT_UART_SFE_SFE
6630  *
6631  * Disable Rx/Tx
6632  */
6633 #define ALT_UART_SFE_SFE_E_DISD 0x0
6634 /*
6635  * Enumerated value for register field ALT_UART_SFE_SFE
6636  *
6637  * Enable Rx/Tx
6638  */
6639 #define ALT_UART_SFE_SFE_E_END 0x1
6640 
6641 /* The Least Significant Bit (LSB) position of the ALT_UART_SFE_SFE register field. */
6642 #define ALT_UART_SFE_SFE_LSB 0
6643 /* The Most Significant Bit (MSB) position of the ALT_UART_SFE_SFE register field. */
6644 #define ALT_UART_SFE_SFE_MSB 0
6645 /* The width in bits of the ALT_UART_SFE_SFE register field. */
6646 #define ALT_UART_SFE_SFE_WIDTH 1
6647 /* The mask used to set the ALT_UART_SFE_SFE register field value. */
6648 #define ALT_UART_SFE_SFE_SET_MSK 0x00000001
6649 /* The mask used to clear the ALT_UART_SFE_SFE register field value. */
6650 #define ALT_UART_SFE_SFE_CLR_MSK 0xfffffffe
6651 /* The reset value of the ALT_UART_SFE_SFE register field. */
6652 #define ALT_UART_SFE_SFE_RESET 0x0
6653 /* Extracts the ALT_UART_SFE_SFE field value from a register. */
6654 #define ALT_UART_SFE_SFE_GET(value) (((value) & 0x00000001) >> 0)
6655 /* Produces a ALT_UART_SFE_SFE register field value suitable for setting the register. */
6656 #define ALT_UART_SFE_SFE_SET(value) (((value) << 0) & 0x00000001)
6657 
6658 /*
6659  * Field : rsvd_sfe_31to1
6660  *
6661  * Reserved bits [31:1] - Read Only
6662  *
6663  * Field Access Macros:
6664  *
6665  */
6666 /* The Least Significant Bit (LSB) position of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6667 #define ALT_UART_SFE_RSVD_SFE_31TO1_LSB 1
6668 /* The Most Significant Bit (MSB) position of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6669 #define ALT_UART_SFE_RSVD_SFE_31TO1_MSB 31
6670 /* The width in bits of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6671 #define ALT_UART_SFE_RSVD_SFE_31TO1_WIDTH 31
6672 /* The mask used to set the ALT_UART_SFE_RSVD_SFE_31TO1 register field value. */
6673 #define ALT_UART_SFE_RSVD_SFE_31TO1_SET_MSK 0xfffffffe
6674 /* The mask used to clear the ALT_UART_SFE_RSVD_SFE_31TO1 register field value. */
6675 #define ALT_UART_SFE_RSVD_SFE_31TO1_CLR_MSK 0x00000001
6676 /* The reset value of the ALT_UART_SFE_RSVD_SFE_31TO1 register field. */
6677 #define ALT_UART_SFE_RSVD_SFE_31TO1_RESET 0x0
6678 /* Extracts the ALT_UART_SFE_RSVD_SFE_31TO1 field value from a register. */
6679 #define ALT_UART_SFE_RSVD_SFE_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
6680 /* Produces a ALT_UART_SFE_RSVD_SFE_31TO1 register field value suitable for setting the register. */
6681 #define ALT_UART_SFE_RSVD_SFE_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
6682 
6683 #ifndef __ASSEMBLY__
6684 /*
6685  * WARNING: The C register and register group struct declarations are provided for
6686  * convenience and illustrative purposes. They should, however, be used with
6687  * caution as the C language standard provides no guarantees about the alignment or
6688  * atomicity of device memory accesses. The recommended practice for writing
6689  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6690  * alt_write_word() functions.
6691  *
6692  * The struct declaration for register ALT_UART_SFE.
6693  */
6694 struct ALT_UART_SFE_s
6695 {
6696  uint32_t sfe : 1; /* ALT_UART_SFE_SFE */
6697  const uint32_t rsvd_sfe_31to1 : 31; /* ALT_UART_SFE_RSVD_SFE_31TO1 */
6698 };
6699 
6700 /* The typedef declaration for register ALT_UART_SFE. */
6701 typedef volatile struct ALT_UART_SFE_s ALT_UART_SFE_t;
6702 #endif /* __ASSEMBLY__ */
6703 
6704 /* The reset value of the ALT_UART_SFE register. */
6705 #define ALT_UART_SFE_RESET 0x00000000
6706 /* The byte offset of the ALT_UART_SFE register from the beginning of the component. */
6707 #define ALT_UART_SFE_OFST 0x98
6708 /* The address of the ALT_UART_SFE register. */
6709 #define ALT_UART_SFE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SFE_OFST))
6710 
6711 /*
6712  * Register : srt
6713  *
6714  * Shadow RCVR Trigger
6715  *
6716  * Register Layout
6717  *
6718  * Bits | Access | Reset | Description
6719  * :-------|:-------|:------|:----------------------------
6720  * [1:0] | RW | 0x0 | ALT_UART_SRT_SRT
6721  * [31:2] | R | 0x0 | ALT_UART_SRT_RSVD_SRT_31TO2
6722  *
6723  */
6724 /*
6725  * Field : srt
6726  *
6727  * Shadow RCVR Trigger.
6728  *
6729  * This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used
6730  * to
6731  *
6732  * remove the burden of having to store the previously written value to the FCR in
6733  *
6734  * memory and having to mask this value so that only the RCVR trigger bit gets
6735  * updated.
6736  *
6737  * This is used to select the trigger level in the receiver FIFO at which the
6738  * Received
6739  *
6740  * Data Available Interrupt will be generated. It also determines when the
6741  * dma_rx_req_n
6742  *
6743  * signal will be asserted when DMA Mode (FCR[3]) is set to one. The following
6744  * trigger
6745  *
6746  * levels are supported:
6747  *
6748  * 00 = 1 character in the FIFO
6749  *
6750  * 01 = FIFO ? full
6751  *
6752  * 10 = FIFO ? full
6753  *
6754  * 11 = FIFO 2 less than full
6755  *
6756  * Field Enumeration Values:
6757  *
6758  * Enum | Value | Description
6759  * :-------------------------------|:------|:----------------------
6760  * ALT_UART_SRT_SRT_E_ONECHAR | 0x0 | one character in fifo
6761  * ALT_UART_SRT_SRT_E_QUARTERFULL | 0x1 | FIFO 1/4 full
6762  * ALT_UART_SRT_SRT_E_HALFFULL | 0x2 | FIFO 1/2 full
6763  * ALT_UART_SRT_SRT_E_FULLLESS2 | 0x3 | FIFO 2 less than full
6764  *
6765  * Field Access Macros:
6766  *
6767  */
6768 /*
6769  * Enumerated value for register field ALT_UART_SRT_SRT
6770  *
6771  * one character in fifo
6772  */
6773 #define ALT_UART_SRT_SRT_E_ONECHAR 0x0
6774 /*
6775  * Enumerated value for register field ALT_UART_SRT_SRT
6776  *
6777  * FIFO 1/4 full
6778  */
6779 #define ALT_UART_SRT_SRT_E_QUARTERFULL 0x1
6780 /*
6781  * Enumerated value for register field ALT_UART_SRT_SRT
6782  *
6783  * FIFO 1/2 full
6784  */
6785 #define ALT_UART_SRT_SRT_E_HALFFULL 0x2
6786 /*
6787  * Enumerated value for register field ALT_UART_SRT_SRT
6788  *
6789  * FIFO 2 less than full
6790  */
6791 #define ALT_UART_SRT_SRT_E_FULLLESS2 0x3
6792 
6793 /* The Least Significant Bit (LSB) position of the ALT_UART_SRT_SRT register field. */
6794 #define ALT_UART_SRT_SRT_LSB 0
6795 /* The Most Significant Bit (MSB) position of the ALT_UART_SRT_SRT register field. */
6796 #define ALT_UART_SRT_SRT_MSB 1
6797 /* The width in bits of the ALT_UART_SRT_SRT register field. */
6798 #define ALT_UART_SRT_SRT_WIDTH 2
6799 /* The mask used to set the ALT_UART_SRT_SRT register field value. */
6800 #define ALT_UART_SRT_SRT_SET_MSK 0x00000003
6801 /* The mask used to clear the ALT_UART_SRT_SRT register field value. */
6802 #define ALT_UART_SRT_SRT_CLR_MSK 0xfffffffc
6803 /* The reset value of the ALT_UART_SRT_SRT register field. */
6804 #define ALT_UART_SRT_SRT_RESET 0x0
6805 /* Extracts the ALT_UART_SRT_SRT field value from a register. */
6806 #define ALT_UART_SRT_SRT_GET(value) (((value) & 0x00000003) >> 0)
6807 /* Produces a ALT_UART_SRT_SRT register field value suitable for setting the register. */
6808 #define ALT_UART_SRT_SRT_SET(value) (((value) << 0) & 0x00000003)
6809 
6810 /*
6811  * Field : rsvd_srt_31to2
6812  *
6813  * Reserved bits [31:2] - Read Only
6814  *
6815  * Field Access Macros:
6816  *
6817  */
6818 /* The Least Significant Bit (LSB) position of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6819 #define ALT_UART_SRT_RSVD_SRT_31TO2_LSB 2
6820 /* The Most Significant Bit (MSB) position of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6821 #define ALT_UART_SRT_RSVD_SRT_31TO2_MSB 31
6822 /* The width in bits of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6823 #define ALT_UART_SRT_RSVD_SRT_31TO2_WIDTH 30
6824 /* The mask used to set the ALT_UART_SRT_RSVD_SRT_31TO2 register field value. */
6825 #define ALT_UART_SRT_RSVD_SRT_31TO2_SET_MSK 0xfffffffc
6826 /* The mask used to clear the ALT_UART_SRT_RSVD_SRT_31TO2 register field value. */
6827 #define ALT_UART_SRT_RSVD_SRT_31TO2_CLR_MSK 0x00000003
6828 /* The reset value of the ALT_UART_SRT_RSVD_SRT_31TO2 register field. */
6829 #define ALT_UART_SRT_RSVD_SRT_31TO2_RESET 0x0
6830 /* Extracts the ALT_UART_SRT_RSVD_SRT_31TO2 field value from a register. */
6831 #define ALT_UART_SRT_RSVD_SRT_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6832 /* Produces a ALT_UART_SRT_RSVD_SRT_31TO2 register field value suitable for setting the register. */
6833 #define ALT_UART_SRT_RSVD_SRT_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6834 
6835 #ifndef __ASSEMBLY__
6836 /*
6837  * WARNING: The C register and register group struct declarations are provided for
6838  * convenience and illustrative purposes. They should, however, be used with
6839  * caution as the C language standard provides no guarantees about the alignment or
6840  * atomicity of device memory accesses. The recommended practice for writing
6841  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6842  * alt_write_word() functions.
6843  *
6844  * The struct declaration for register ALT_UART_SRT.
6845  */
6846 struct ALT_UART_SRT_s
6847 {
6848  uint32_t srt : 2; /* ALT_UART_SRT_SRT */
6849  const uint32_t rsvd_srt_31to2 : 30; /* ALT_UART_SRT_RSVD_SRT_31TO2 */
6850 };
6851 
6852 /* The typedef declaration for register ALT_UART_SRT. */
6853 typedef volatile struct ALT_UART_SRT_s ALT_UART_SRT_t;
6854 #endif /* __ASSEMBLY__ */
6855 
6856 /* The reset value of the ALT_UART_SRT register. */
6857 #define ALT_UART_SRT_RESET 0x00000000
6858 /* The byte offset of the ALT_UART_SRT register from the beginning of the component. */
6859 #define ALT_UART_SRT_OFST 0x9c
6860 /* The address of the ALT_UART_SRT register. */
6861 #define ALT_UART_SRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRT_OFST))
6862 
6863 /*
6864  * Register : stet
6865  *
6866  * Shadow TX Empty Trigger
6867  *
6868  * Register Layout
6869  *
6870  * Bits | Access | Reset | Description
6871  * :-------|:-------|:------|:------------------------------
6872  * [1:0] | RW | 0x0 | ALT_UART_STET_STET
6873  * [31:2] | R | 0x0 | ALT_UART_STET_RSVD_STET_31TO2
6874  *
6875  */
6876 /*
6877  * Field : stet
6878  *
6879  * Shadow TX Empty Trigger.
6880  *
6881  * This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be
6882  * used
6883  *
6884  * to remove the burden of having to store the previously written value to the FCR
6885  * in
6886  *
6887  * memory and having to mask this value so that only the TX empty trigger bit gets
6888  * updated.
6889  *
6890  * Writes will have no effect when THRE_MODE_USER == Disabled. This is used to
6891  * select the
6892  *
6893  * empty threshold level at which the THRE Interrupts will be generated when the
6894  * mode is
6895  *
6896  * active. These threshold levels are also described in. The following trigger
6897  * levels are
6898  *
6899  * supported:
6900  *
6901  * 00 = FIFO empty
6902  *
6903  * 01 = 2 characters in the FIFO
6904  *
6905  * 10 = FIFO ? full
6906  *
6907  * 11 = FIFO ? full
6908  *
6909  * Field Enumeration Values:
6910  *
6911  * Enum | Value | Description
6912  * :---------------------------------|:------|:-----------------------
6913  * ALT_UART_STET_STET_E_FIFOEMPTY | 0x0 | FIFO empty
6914  * ALT_UART_STET_STET_E_TWOCHARS | 0x1 | Two characters in FIFO
6915  * ALT_UART_STET_STET_E_QUARTERFULL | 0x2 | FIFO quarter full
6916  * ALT_UART_STET_STET_E_HALFFULL | 0x3 | FIFO half full
6917  *
6918  * Field Access Macros:
6919  *
6920  */
6921 /*
6922  * Enumerated value for register field ALT_UART_STET_STET
6923  *
6924  * FIFO empty
6925  */
6926 #define ALT_UART_STET_STET_E_FIFOEMPTY 0x0
6927 /*
6928  * Enumerated value for register field ALT_UART_STET_STET
6929  *
6930  * Two characters in FIFO
6931  */
6932 #define ALT_UART_STET_STET_E_TWOCHARS 0x1
6933 /*
6934  * Enumerated value for register field ALT_UART_STET_STET
6935  *
6936  * FIFO quarter full
6937  */
6938 #define ALT_UART_STET_STET_E_QUARTERFULL 0x2
6939 /*
6940  * Enumerated value for register field ALT_UART_STET_STET
6941  *
6942  * FIFO half full
6943  */
6944 #define ALT_UART_STET_STET_E_HALFFULL 0x3
6945 
6946 /* The Least Significant Bit (LSB) position of the ALT_UART_STET_STET register field. */
6947 #define ALT_UART_STET_STET_LSB 0
6948 /* The Most Significant Bit (MSB) position of the ALT_UART_STET_STET register field. */
6949 #define ALT_UART_STET_STET_MSB 1
6950 /* The width in bits of the ALT_UART_STET_STET register field. */
6951 #define ALT_UART_STET_STET_WIDTH 2
6952 /* The mask used to set the ALT_UART_STET_STET register field value. */
6953 #define ALT_UART_STET_STET_SET_MSK 0x00000003
6954 /* The mask used to clear the ALT_UART_STET_STET register field value. */
6955 #define ALT_UART_STET_STET_CLR_MSK 0xfffffffc
6956 /* The reset value of the ALT_UART_STET_STET register field. */
6957 #define ALT_UART_STET_STET_RESET 0x0
6958 /* Extracts the ALT_UART_STET_STET field value from a register. */
6959 #define ALT_UART_STET_STET_GET(value) (((value) & 0x00000003) >> 0)
6960 /* Produces a ALT_UART_STET_STET register field value suitable for setting the register. */
6961 #define ALT_UART_STET_STET_SET(value) (((value) << 0) & 0x00000003)
6962 
6963 /*
6964  * Field : rsvd_stet_31to2
6965  *
6966  * Reserved bits [31:2] - Read Only
6967  *
6968  * Field Access Macros:
6969  *
6970  */
6971 /* The Least Significant Bit (LSB) position of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6972 #define ALT_UART_STET_RSVD_STET_31TO2_LSB 2
6973 /* The Most Significant Bit (MSB) position of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6974 #define ALT_UART_STET_RSVD_STET_31TO2_MSB 31
6975 /* The width in bits of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6976 #define ALT_UART_STET_RSVD_STET_31TO2_WIDTH 30
6977 /* The mask used to set the ALT_UART_STET_RSVD_STET_31TO2 register field value. */
6978 #define ALT_UART_STET_RSVD_STET_31TO2_SET_MSK 0xfffffffc
6979 /* The mask used to clear the ALT_UART_STET_RSVD_STET_31TO2 register field value. */
6980 #define ALT_UART_STET_RSVD_STET_31TO2_CLR_MSK 0x00000003
6981 /* The reset value of the ALT_UART_STET_RSVD_STET_31TO2 register field. */
6982 #define ALT_UART_STET_RSVD_STET_31TO2_RESET 0x0
6983 /* Extracts the ALT_UART_STET_RSVD_STET_31TO2 field value from a register. */
6984 #define ALT_UART_STET_RSVD_STET_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6985 /* Produces a ALT_UART_STET_RSVD_STET_31TO2 register field value suitable for setting the register. */
6986 #define ALT_UART_STET_RSVD_STET_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6987 
6988 #ifndef __ASSEMBLY__
6989 /*
6990  * WARNING: The C register and register group struct declarations are provided for
6991  * convenience and illustrative purposes. They should, however, be used with
6992  * caution as the C language standard provides no guarantees about the alignment or
6993  * atomicity of device memory accesses. The recommended practice for writing
6994  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6995  * alt_write_word() functions.
6996  *
6997  * The struct declaration for register ALT_UART_STET.
6998  */
6999 struct ALT_UART_STET_s
7000 {
7001  uint32_t stet : 2; /* ALT_UART_STET_STET */
7002  const uint32_t rsvd_stet_31to2 : 30; /* ALT_UART_STET_RSVD_STET_31TO2 */
7003 };
7004 
7005 /* The typedef declaration for register ALT_UART_STET. */
7006 typedef volatile struct ALT_UART_STET_s ALT_UART_STET_t;
7007 #endif /* __ASSEMBLY__ */
7008 
7009 /* The reset value of the ALT_UART_STET register. */
7010 #define ALT_UART_STET_RESET 0x00000000
7011 /* The byte offset of the ALT_UART_STET register from the beginning of the component. */
7012 #define ALT_UART_STET_OFST 0xa0
7013 /* The address of the ALT_UART_STET register. */
7014 #define ALT_UART_STET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_STET_OFST))
7015 
7016 /*
7017  * Register : htx
7018  *
7019  * Halt TX
7020  *
7021  * Register Layout
7022  *
7023  * Bits | Access | Reset | Description
7024  * :-------|:-------|:------|:----------------------------
7025  * [0] | RW | 0x0 | ALT_UART_HTX_HTX
7026  * [31:1] | R | 0x0 | ALT_UART_HTX_RSVD_HTX_31TO1
7027  *
7028  */
7029 /*
7030  * Field : htx
7031  *
7032  * Halt TX.
7033  *
7034  * Writes will have no effect when FIFO_MODE == NONE, always readable. This
7035  * register
7036  *
7037  * is use to halt transmissions for testing, so that the transmit FIFO can be
7038  * filled
7039  *
7040  * by the master when FIFO's are implemented and enabled.
7041  *
7042  * Note, if FIFO's are implemented and not enabled the setting of the halt TX
7043  * register
7044  *
7045  * will have no effect on operation.
7046  *
7047  * 0 = Halt TX disabled
7048  *
7049  * 1 = Halt TX enabled
7050  *
7051  * Field Enumeration Values:
7052  *
7053  * Enum | Value | Description
7054  * :------------------------|:------|:-----------------
7055  * ALT_UART_HTX_HTX_E_DISD | 0x0 | Halt Tx disabled
7056  * ALT_UART_HTX_HTX_E_END | 0x1 | Halt Tx enabled
7057  *
7058  * Field Access Macros:
7059  *
7060  */
7061 /*
7062  * Enumerated value for register field ALT_UART_HTX_HTX
7063  *
7064  * Halt Tx disabled
7065  */
7066 #define ALT_UART_HTX_HTX_E_DISD 0x0
7067 /*
7068  * Enumerated value for register field ALT_UART_HTX_HTX
7069  *
7070  * Halt Tx enabled
7071  */
7072 #define ALT_UART_HTX_HTX_E_END 0x1
7073 
7074 /* The Least Significant Bit (LSB) position of the ALT_UART_HTX_HTX register field. */
7075 #define ALT_UART_HTX_HTX_LSB 0
7076 /* The Most Significant Bit (MSB) position of the ALT_UART_HTX_HTX register field. */
7077 #define ALT_UART_HTX_HTX_MSB 0
7078 /* The width in bits of the ALT_UART_HTX_HTX register field. */
7079 #define ALT_UART_HTX_HTX_WIDTH 1
7080 /* The mask used to set the ALT_UART_HTX_HTX register field value. */
7081 #define ALT_UART_HTX_HTX_SET_MSK 0x00000001
7082 /* The mask used to clear the ALT_UART_HTX_HTX register field value. */
7083 #define ALT_UART_HTX_HTX_CLR_MSK 0xfffffffe
7084 /* The reset value of the ALT_UART_HTX_HTX register field. */
7085 #define ALT_UART_HTX_HTX_RESET 0x0
7086 /* Extracts the ALT_UART_HTX_HTX field value from a register. */
7087 #define ALT_UART_HTX_HTX_GET(value) (((value) & 0x00000001) >> 0)
7088 /* Produces a ALT_UART_HTX_HTX register field value suitable for setting the register. */
7089 #define ALT_UART_HTX_HTX_SET(value) (((value) << 0) & 0x00000001)
7090 
7091 /*
7092  * Field : rsvd_htx_31to1
7093  *
7094  * Reserved bits [31:1] - Read Only
7095  *
7096  * Field Access Macros:
7097  *
7098  */
7099 /* The Least Significant Bit (LSB) position of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
7100 #define ALT_UART_HTX_RSVD_HTX_31TO1_LSB 1
7101 /* The Most Significant Bit (MSB) position of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
7102 #define ALT_UART_HTX_RSVD_HTX_31TO1_MSB 31
7103 /* The width in bits of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
7104 #define ALT_UART_HTX_RSVD_HTX_31TO1_WIDTH 31
7105 /* The mask used to set the ALT_UART_HTX_RSVD_HTX_31TO1 register field value. */
7106 #define ALT_UART_HTX_RSVD_HTX_31TO1_SET_MSK 0xfffffffe
7107 /* The mask used to clear the ALT_UART_HTX_RSVD_HTX_31TO1 register field value. */
7108 #define ALT_UART_HTX_RSVD_HTX_31TO1_CLR_MSK 0x00000001
7109 /* The reset value of the ALT_UART_HTX_RSVD_HTX_31TO1 register field. */
7110 #define ALT_UART_HTX_RSVD_HTX_31TO1_RESET 0x0
7111 /* Extracts the ALT_UART_HTX_RSVD_HTX_31TO1 field value from a register. */
7112 #define ALT_UART_HTX_RSVD_HTX_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
7113 /* Produces a ALT_UART_HTX_RSVD_HTX_31TO1 register field value suitable for setting the register. */
7114 #define ALT_UART_HTX_RSVD_HTX_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
7115 
7116 #ifndef __ASSEMBLY__
7117 /*
7118  * WARNING: The C register and register group struct declarations are provided for
7119  * convenience and illustrative purposes. They should, however, be used with
7120  * caution as the C language standard provides no guarantees about the alignment or
7121  * atomicity of device memory accesses. The recommended practice for writing
7122  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7123  * alt_write_word() functions.
7124  *
7125  * The struct declaration for register ALT_UART_HTX.
7126  */
7127 struct ALT_UART_HTX_s
7128 {
7129  uint32_t htx : 1; /* ALT_UART_HTX_HTX */
7130  const uint32_t rsvd_htx_31to1 : 31; /* ALT_UART_HTX_RSVD_HTX_31TO1 */
7131 };
7132 
7133 /* The typedef declaration for register ALT_UART_HTX. */
7134 typedef volatile struct ALT_UART_HTX_s ALT_UART_HTX_t;
7135 #endif /* __ASSEMBLY__ */
7136 
7137 /* The reset value of the ALT_UART_HTX register. */
7138 #define ALT_UART_HTX_RESET 0x00000000
7139 /* The byte offset of the ALT_UART_HTX register from the beginning of the component. */
7140 #define ALT_UART_HTX_OFST 0xa4
7141 /* The address of the ALT_UART_HTX register. */
7142 #define ALT_UART_HTX_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_HTX_OFST))
7143 
7144 /*
7145  * Register : dmasa
7146  *
7147  * DMA Software Acknowledge
7148  *
7149  * Register Layout
7150  *
7151  * Bits | Access | Reset | Description
7152  * :-------|:-------|:------|:--------------------------------
7153  * [0] | W | 0x0 | ALT_UART_DMASA_DMASA
7154  * [31:1] | R | 0x0 | ALT_UART_DMASA_RSVD_DMASA_31TO1
7155  *
7156  */
7157 /*
7158  * Field : dmasa
7159  *
7160  * DMA Software Acknowledge.
7161  *
7162  * Writes will have no effect when DMA_EXTRA == No. This register is use to
7163  * perform
7164  *
7165  * DMA software acknowledge if a transfer needs to be terminated due to an error
7166  *
7167  * condition. For example, if the DMA disables the channel, then the DW_apb_uart
7168  * should
7169  *
7170  * clear its request. This will cause the TX request, TX single, RX request and RX
7171  *
7172  * single signals to de-assert.
7173  *
7174  * Note that this bit is 'self-clearing' and it is not necessary to clear this bit.
7175  *
7176  * Field Access Macros:
7177  *
7178  */
7179 /* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_DMASA register field. */
7180 #define ALT_UART_DMASA_DMASA_LSB 0
7181 /* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_DMASA register field. */
7182 #define ALT_UART_DMASA_DMASA_MSB 0
7183 /* The width in bits of the ALT_UART_DMASA_DMASA register field. */
7184 #define ALT_UART_DMASA_DMASA_WIDTH 1
7185 /* The mask used to set the ALT_UART_DMASA_DMASA register field value. */
7186 #define ALT_UART_DMASA_DMASA_SET_MSK 0x00000001
7187 /* The mask used to clear the ALT_UART_DMASA_DMASA register field value. */
7188 #define ALT_UART_DMASA_DMASA_CLR_MSK 0xfffffffe
7189 /* The reset value of the ALT_UART_DMASA_DMASA register field. */
7190 #define ALT_UART_DMASA_DMASA_RESET 0x0
7191 /* Extracts the ALT_UART_DMASA_DMASA field value from a register. */
7192 #define ALT_UART_DMASA_DMASA_GET(value) (((value) & 0x00000001) >> 0)
7193 /* Produces a ALT_UART_DMASA_DMASA register field value suitable for setting the register. */
7194 #define ALT_UART_DMASA_DMASA_SET(value) (((value) << 0) & 0x00000001)
7195 
7196 /*
7197  * Field : rsvd_dmasa_31to1
7198  *
7199  * Reserved bits [31:1] - Read Only
7200  *
7201  * Field Access Macros:
7202  *
7203  */
7204 /* The Least Significant Bit (LSB) position of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
7205 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_LSB 1
7206 /* The Most Significant Bit (MSB) position of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
7207 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_MSB 31
7208 /* The width in bits of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
7209 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_WIDTH 31
7210 /* The mask used to set the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value. */
7211 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_SET_MSK 0xfffffffe
7212 /* The mask used to clear the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value. */
7213 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_CLR_MSK 0x00000001
7214 /* The reset value of the ALT_UART_DMASA_RSVD_DMASA_31TO1 register field. */
7215 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_RESET 0x0
7216 /* Extracts the ALT_UART_DMASA_RSVD_DMASA_31TO1 field value from a register. */
7217 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
7218 /* Produces a ALT_UART_DMASA_RSVD_DMASA_31TO1 register field value suitable for setting the register. */
7219 #define ALT_UART_DMASA_RSVD_DMASA_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
7220 
7221 #ifndef __ASSEMBLY__
7222 /*
7223  * WARNING: The C register and register group struct declarations are provided for
7224  * convenience and illustrative purposes. They should, however, be used with
7225  * caution as the C language standard provides no guarantees about the alignment or
7226  * atomicity of device memory accesses. The recommended practice for writing
7227  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7228  * alt_write_word() functions.
7229  *
7230  * The struct declaration for register ALT_UART_DMASA.
7231  */
7232 struct ALT_UART_DMASA_s
7233 {
7234  uint32_t dmasa : 1; /* ALT_UART_DMASA_DMASA */
7235  const uint32_t rsvd_dmasa_31to1 : 31; /* ALT_UART_DMASA_RSVD_DMASA_31TO1 */
7236 };
7237 
7238 /* The typedef declaration for register ALT_UART_DMASA. */
7239 typedef volatile struct ALT_UART_DMASA_s ALT_UART_DMASA_t;
7240 #endif /* __ASSEMBLY__ */
7241 
7242 /* The reset value of the ALT_UART_DMASA register. */
7243 #define ALT_UART_DMASA_RESET 0x00000000
7244 /* The byte offset of the ALT_UART_DMASA register from the beginning of the component. */
7245 #define ALT_UART_DMASA_OFST 0xa8
7246 /* The address of the ALT_UART_DMASA register. */
7247 #define ALT_UART_DMASA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_DMASA_OFST))
7248 
7249 /*
7250  * Register : cpr
7251  *
7252  * Component Parameter Register
7253  *
7254  * Register Layout
7255  *
7256  * Bits | Access | Reset | Description
7257  * :--------|:-------|:------|:--------------------------------
7258  * [1:0] | R | 0x2 | ALT_UART_CPR_APBDATAWIDTH
7259  * [3:2] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_3TO2
7260  * [4] | R | 0x1 | ALT_UART_CPR_AFCE_MOD
7261  * [5] | R | 0x1 | ALT_UART_CPR_THRE_MOD
7262  * [6] | R | 0x0 | ALT_UART_CPR_SIR_MOD
7263  * [7] | R | 0x0 | ALT_UART_CPR_SIR_LP_MOD
7264  * [8] | R | 0x1 | ALT_UART_CPR_ADDITIONAL_FEAT
7265  * [9] | R | 0x1 | ALT_UART_CPR_FIFO_ACCESS
7266  * [10] | R | 0x1 | ALT_UART_CPR_FIFO_STAT
7267  * [11] | R | 0x1 | ALT_UART_CPR_SHADOW
7268  * [12] | R | 0x1 | ALT_UART_CPR_UART_ADD_ENC_PARAM
7269  * [13] | R | 0x1 | ALT_UART_CPR_DMA_EXTRA
7270  * [15:14] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_15TO14
7271  * [23:16] | R | 0x8 | ALT_UART_CPR_FIFO_MOD
7272  * [31:24] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_31TO24
7273  *
7274  */
7275 /*
7276  * Field : apbdatawidth
7277  *
7278  * Encoding of APB_DATA_WIDTH configuration parameter value.
7279  *
7280  * 00 = 8 bits,
7281  *
7282  * 01 = 16 bits,
7283  *
7284  * 10 = 32 bits,
7285  *
7286  * 11 = reserved
7287  *
7288  * Field Enumeration Values:
7289  *
7290  * Enum | Value | Description
7291  * :----------------------------------------|:------|:-------------------------
7292  * ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
7293  *
7294  * Field Access Macros:
7295  *
7296  */
7297 /*
7298  * Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH
7299  *
7300  * APB Data Width = 32-bits
7301  */
7302 #define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2
7303 
7304 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
7305 #define ALT_UART_CPR_APBDATAWIDTH_LSB 0
7306 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field. */
7307 #define ALT_UART_CPR_APBDATAWIDTH_MSB 1
7308 /* The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field. */
7309 #define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2
7310 /* The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value. */
7311 #define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003
7312 /* The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value. */
7313 #define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc
7314 /* The reset value of the ALT_UART_CPR_APBDATAWIDTH register field. */
7315 #define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2
7316 /* Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register. */
7317 #define ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0)
7318 /* Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register. */
7319 #define ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003)
7320 
7321 /*
7322  * Field : rsvd_cpr_3to2
7323  *
7324  * Reserved bits [3:2] - Read Only
7325  *
7326  * Field Access Macros:
7327  *
7328  */
7329 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7330 #define ALT_UART_CPR_RSVD_CPR_3TO2_LSB 2
7331 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7332 #define ALT_UART_CPR_RSVD_CPR_3TO2_MSB 3
7333 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7334 #define ALT_UART_CPR_RSVD_CPR_3TO2_WIDTH 2
7335 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_3TO2 register field value. */
7336 #define ALT_UART_CPR_RSVD_CPR_3TO2_SET_MSK 0x0000000c
7337 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_3TO2 register field value. */
7338 #define ALT_UART_CPR_RSVD_CPR_3TO2_CLR_MSK 0xfffffff3
7339 /* The reset value of the ALT_UART_CPR_RSVD_CPR_3TO2 register field. */
7340 #define ALT_UART_CPR_RSVD_CPR_3TO2_RESET 0x0
7341 /* Extracts the ALT_UART_CPR_RSVD_CPR_3TO2 field value from a register. */
7342 #define ALT_UART_CPR_RSVD_CPR_3TO2_GET(value) (((value) & 0x0000000c) >> 2)
7343 /* Produces a ALT_UART_CPR_RSVD_CPR_3TO2 register field value suitable for setting the register. */
7344 #define ALT_UART_CPR_RSVD_CPR_3TO2_SET(value) (((value) << 2) & 0x0000000c)
7345 
7346 /*
7347  * Field : afce_mode
7348  *
7349  * Encoding of AFCE_MODE configuration parameter value.
7350  *
7351  * 0 = FALSE,
7352  *
7353  * 1 = TRUE
7354  *
7355  * Field Enumeration Values:
7356  *
7357  * Enum | Value | Description
7358  * :----------------------------|:------|:------------
7359  * ALT_UART_CPR_AFCE_MOD_E_END | 0x1 | Auto Flow
7360  *
7361  * Field Access Macros:
7362  *
7363  */
7364 /*
7365  * Enumerated value for register field ALT_UART_CPR_AFCE_MOD
7366  *
7367  * Auto Flow
7368  */
7369 #define ALT_UART_CPR_AFCE_MOD_E_END 0x1
7370 
7371 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
7372 #define ALT_UART_CPR_AFCE_MOD_LSB 4
7373 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field. */
7374 #define ALT_UART_CPR_AFCE_MOD_MSB 4
7375 /* The width in bits of the ALT_UART_CPR_AFCE_MOD register field. */
7376 #define ALT_UART_CPR_AFCE_MOD_WIDTH 1
7377 /* The mask used to set the ALT_UART_CPR_AFCE_MOD register field value. */
7378 #define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010
7379 /* The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value. */
7380 #define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef
7381 /* The reset value of the ALT_UART_CPR_AFCE_MOD register field. */
7382 #define ALT_UART_CPR_AFCE_MOD_RESET 0x1
7383 /* Extracts the ALT_UART_CPR_AFCE_MOD field value from a register. */
7384 #define ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4)
7385 /* Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register. */
7386 #define ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010)
7387 
7388 /*
7389  * Field : thre_mode
7390  *
7391  * Encoding of THRE_MODE configuration parameter value.
7392  *
7393  * 0 = FALSE,
7394  *
7395  * 1 = TRUE
7396  *
7397  * Field Enumeration Values:
7398  *
7399  * Enum | Value | Description
7400  * :----------------------------|:------|:------------------------------------------
7401  * ALT_UART_CPR_THRE_MOD_E_END | 0x1 | Programmable Tx Hold Reg. Empty interrupt
7402  * : | | present
7403  *
7404  * Field Access Macros:
7405  *
7406  */
7407 /*
7408  * Enumerated value for register field ALT_UART_CPR_THRE_MOD
7409  *
7410  * Programmable Tx Hold Reg. Empty interrupt present
7411  */
7412 #define ALT_UART_CPR_THRE_MOD_E_END 0x1
7413 
7414 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field. */
7415 #define ALT_UART_CPR_THRE_MOD_LSB 5
7416 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field. */
7417 #define ALT_UART_CPR_THRE_MOD_MSB 5
7418 /* The width in bits of the ALT_UART_CPR_THRE_MOD register field. */
7419 #define ALT_UART_CPR_THRE_MOD_WIDTH 1
7420 /* The mask used to set the ALT_UART_CPR_THRE_MOD register field value. */
7421 #define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020
7422 /* The mask used to clear the ALT_UART_CPR_THRE_MOD register field value. */
7423 #define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf
7424 /* The reset value of the ALT_UART_CPR_THRE_MOD register field. */
7425 #define ALT_UART_CPR_THRE_MOD_RESET 0x1
7426 /* Extracts the ALT_UART_CPR_THRE_MOD field value from a register. */
7427 #define ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5)
7428 /* Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register. */
7429 #define ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020)
7430 
7431 /*
7432  * Field : sir_mode
7433  *
7434  * Encoding of SIR_MODE configuration parameter value.
7435  *
7436  * 0 = FALSE,
7437  *
7438  * 1 = TRUE
7439  *
7440  * Field Enumeration Values:
7441  *
7442  * Enum | Value | Description
7443  * :----------------------------|:------|:-----------------------
7444  * ALT_UART_CPR_SIR_MOD_E_DISD | 0x0 | Sir Mode Not Supported
7445  *
7446  * Field Access Macros:
7447  *
7448  */
7449 /*
7450  * Enumerated value for register field ALT_UART_CPR_SIR_MOD
7451  *
7452  * Sir Mode Not Supported
7453  */
7454 #define ALT_UART_CPR_SIR_MOD_E_DISD 0x0
7455 
7456 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field. */
7457 #define ALT_UART_CPR_SIR_MOD_LSB 6
7458 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field. */
7459 #define ALT_UART_CPR_SIR_MOD_MSB 6
7460 /* The width in bits of the ALT_UART_CPR_SIR_MOD register field. */
7461 #define ALT_UART_CPR_SIR_MOD_WIDTH 1
7462 /* The mask used to set the ALT_UART_CPR_SIR_MOD register field value. */
7463 #define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040
7464 /* The mask used to clear the ALT_UART_CPR_SIR_MOD register field value. */
7465 #define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf
7466 /* The reset value of the ALT_UART_CPR_SIR_MOD register field. */
7467 #define ALT_UART_CPR_SIR_MOD_RESET 0x0
7468 /* Extracts the ALT_UART_CPR_SIR_MOD field value from a register. */
7469 #define ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6)
7470 /* Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register. */
7471 #define ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040)
7472 
7473 /*
7474  * Field : sir_lp_mode
7475  *
7476  * Encoding of SIR_LP_MODE configuration parameter value.
7477  *
7478  * 0 = FALSE,
7479  *
7480  * 1 = TRUE
7481  *
7482  * Field Enumeration Values:
7483  *
7484  * Enum | Value | Description
7485  * :-------------------------------|:------|:--------------------------
7486  * ALT_UART_CPR_SIR_LP_MOD_E_DISD | 0x0 | LP Sir Mode Not Supported
7487  *
7488  * Field Access Macros:
7489  *
7490  */
7491 /*
7492  * Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD
7493  *
7494  * LP Sir Mode Not Supported
7495  */
7496 #define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0
7497 
7498 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
7499 #define ALT_UART_CPR_SIR_LP_MOD_LSB 7
7500 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field. */
7501 #define ALT_UART_CPR_SIR_LP_MOD_MSB 7
7502 /* The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field. */
7503 #define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1
7504 /* The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value. */
7505 #define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080
7506 /* The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value. */
7507 #define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f
7508 /* The reset value of the ALT_UART_CPR_SIR_LP_MOD register field. */
7509 #define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0
7510 /* Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register. */
7511 #define ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7)
7512 /* Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register. */
7513 #define ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080)
7514 
7515 /*
7516  * Field : additional_feat
7517  *
7518  * Encoding of ADDITIONAL_FEATURES configuration parameter value.
7519  *
7520  * 0 = FALSE,
7521  *
7522  * 1 = TRUE
7523  *
7524  * Field Enumeration Values:
7525  *
7526  * Enum | Value | Description
7527  * :-----------------------------------|:------|:------------------------------
7528  * ALT_UART_CPR_ADDITIONAL_FEAT_E_END | 0x1 | Additional Features Supported
7529  *
7530  * Field Access Macros:
7531  *
7532  */
7533 /*
7534  * Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
7535  *
7536  * Additional Features Supported
7537  */
7538 #define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1
7539 
7540 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7541 #define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8
7542 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7543 #define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8
7544 /* The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7545 #define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1
7546 /* The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
7547 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100
7548 /* The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value. */
7549 #define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff
7550 /* The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field. */
7551 #define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1
7552 /* Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register. */
7553 #define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8)
7554 /* Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register. */
7555 #define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100)
7556 
7557 /*
7558  * Field : fifo_access
7559  *
7560  * Encoding of FIFO_ACCESS configuration parameter value.
7561  *
7562  * 0 = FALSE,
7563  *
7564  * 1 = TRUE
7565  *
7566  * Field Enumeration Values:
7567  *
7568  * Enum | Value | Description
7569  * :-------------------------------|:------|:----------------------
7570  * ALT_UART_CPR_FIFO_ACCESS_E_END | 0x1 | FIFO Access Supported
7571  *
7572  * Field Access Macros:
7573  *
7574  */
7575 /*
7576  * Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
7577  *
7578  * FIFO Access Supported
7579  */
7580 #define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1
7581 
7582 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
7583 #define ALT_UART_CPR_FIFO_ACCESS_LSB 9
7584 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field. */
7585 #define ALT_UART_CPR_FIFO_ACCESS_MSB 9
7586 /* The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field. */
7587 #define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1
7588 /* The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value. */
7589 #define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200
7590 /* The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value. */
7591 #define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff
7592 /* The reset value of the ALT_UART_CPR_FIFO_ACCESS register field. */
7593 #define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1
7594 /* Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register. */
7595 #define ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9)
7596 /* Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register. */
7597 #define ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200)
7598 
7599 /*
7600  * Field : fifo_stat
7601  *
7602  * Encoding of FIFO_STAT configuration parameter value.
7603  *
7604  * 0 = FALSE,
7605  *
7606  * 1 = TRUE
7607  *
7608  * Field Enumeration Values:
7609  *
7610  * Enum | Value | Description
7611  * :-----------------------------|:------|:--------------------
7612  * ALT_UART_CPR_FIFO_STAT_E_END | 0x1 | FIFO Stat Supported
7613  *
7614  * Field Access Macros:
7615  *
7616  */
7617 /*
7618  * Enumerated value for register field ALT_UART_CPR_FIFO_STAT
7619  *
7620  * FIFO Stat Supported
7621  */
7622 #define ALT_UART_CPR_FIFO_STAT_E_END 0x1
7623 
7624 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
7625 #define ALT_UART_CPR_FIFO_STAT_LSB 10
7626 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field. */
7627 #define ALT_UART_CPR_FIFO_STAT_MSB 10
7628 /* The width in bits of the ALT_UART_CPR_FIFO_STAT register field. */
7629 #define ALT_UART_CPR_FIFO_STAT_WIDTH 1
7630 /* The mask used to set the ALT_UART_CPR_FIFO_STAT register field value. */
7631 #define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400
7632 /* The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value. */
7633 #define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff
7634 /* The reset value of the ALT_UART_CPR_FIFO_STAT register field. */
7635 #define ALT_UART_CPR_FIFO_STAT_RESET 0x1
7636 /* Extracts the ALT_UART_CPR_FIFO_STAT field value from a register. */
7637 #define ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10)
7638 /* Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register. */
7639 #define ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400)
7640 
7641 /*
7642  * Field : shadow
7643  *
7644  * Encoding of SHADOW configuration parameter value.
7645  *
7646  * 0 = FALSE,
7647  *
7648  * 1 = TRUE
7649  *
7650  * Field Enumeration Values:
7651  *
7652  * Enum | Value | Description
7653  * :--------------------------|:------|:-----------------
7654  * ALT_UART_CPR_SHADOW_E_END | 0x1 | Shadow Supported
7655  *
7656  * Field Access Macros:
7657  *
7658  */
7659 /*
7660  * Enumerated value for register field ALT_UART_CPR_SHADOW
7661  *
7662  * Shadow Supported
7663  */
7664 #define ALT_UART_CPR_SHADOW_E_END 0x1
7665 
7666 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field. */
7667 #define ALT_UART_CPR_SHADOW_LSB 11
7668 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field. */
7669 #define ALT_UART_CPR_SHADOW_MSB 11
7670 /* The width in bits of the ALT_UART_CPR_SHADOW register field. */
7671 #define ALT_UART_CPR_SHADOW_WIDTH 1
7672 /* The mask used to set the ALT_UART_CPR_SHADOW register field value. */
7673 #define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800
7674 /* The mask used to clear the ALT_UART_CPR_SHADOW register field value. */
7675 #define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff
7676 /* The reset value of the ALT_UART_CPR_SHADOW register field. */
7677 #define ALT_UART_CPR_SHADOW_RESET 0x1
7678 /* Extracts the ALT_UART_CPR_SHADOW field value from a register. */
7679 #define ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11)
7680 /* Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register. */
7681 #define ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800)
7682 
7683 /*
7684  * Field : uart_add_encoded_param
7685  *
7686  * Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value.
7687  *
7688  * 0 = FALSE,
7689  *
7690  * 1 = TRUE
7691  *
7692  * Field Enumeration Values:
7693  *
7694  * Enum | Value | Description
7695  * :--------------------------------------|:------|:--------------------
7696  * ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END | 0x1 | ID register present
7697  *
7698  * Field Access Macros:
7699  *
7700  */
7701 /*
7702  * Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM
7703  *
7704  * ID register present
7705  */
7706 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1
7707 
7708 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
7709 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12
7710 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
7711 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12
7712 /* The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
7713 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1
7714 /* The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
7715 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000
7716 /* The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value. */
7717 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff
7718 /* The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field. */
7719 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1
7720 /* Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register. */
7721 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12)
7722 /* Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register. */
7723 #define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000)
7724 
7725 /*
7726  * Field : dma_extra
7727  *
7728  * Encoding of DMA_EXTRA configuration parameter value.
7729  *
7730  * 0 = FALSE,DW_apb_uart.ralf
7731  *
7732  * 1 = TRUE
7733  *
7734  * Field Enumeration Values:
7735  *
7736  * Enum | Value | Description
7737  * :-----------------------------|:------|:--------------------
7738  * ALT_UART_CPR_DMA_EXTRA_E_END | 0x1 | DMA Extra Supported
7739  *
7740  * Field Access Macros:
7741  *
7742  */
7743 /*
7744  * Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
7745  *
7746  * DMA Extra Supported
7747  */
7748 #define ALT_UART_CPR_DMA_EXTRA_E_END 0x1
7749 
7750 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
7751 #define ALT_UART_CPR_DMA_EXTRA_LSB 13
7752 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field. */
7753 #define ALT_UART_CPR_DMA_EXTRA_MSB 13
7754 /* The width in bits of the ALT_UART_CPR_DMA_EXTRA register field. */
7755 #define ALT_UART_CPR_DMA_EXTRA_WIDTH 1
7756 /* The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value. */
7757 #define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000
7758 /* The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value. */
7759 #define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff
7760 /* The reset value of the ALT_UART_CPR_DMA_EXTRA register field. */
7761 #define ALT_UART_CPR_DMA_EXTRA_RESET 0x1
7762 /* Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register. */
7763 #define ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13)
7764 /* Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register. */
7765 #define ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000)
7766 
7767 /*
7768  * Field : rsvd_cpr_15to14
7769  *
7770  * Reserved bits [15:14] - Read Only
7771  *
7772  * Field Access Macros:
7773  *
7774  */
7775 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7776 #define ALT_UART_CPR_RSVD_CPR_15TO14_LSB 14
7777 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7778 #define ALT_UART_CPR_RSVD_CPR_15TO14_MSB 15
7779 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7780 #define ALT_UART_CPR_RSVD_CPR_15TO14_WIDTH 2
7781 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_15TO14 register field value. */
7782 #define ALT_UART_CPR_RSVD_CPR_15TO14_SET_MSK 0x0000c000
7783 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_15TO14 register field value. */
7784 #define ALT_UART_CPR_RSVD_CPR_15TO14_CLR_MSK 0xffff3fff
7785 /* The reset value of the ALT_UART_CPR_RSVD_CPR_15TO14 register field. */
7786 #define ALT_UART_CPR_RSVD_CPR_15TO14_RESET 0x0
7787 /* Extracts the ALT_UART_CPR_RSVD_CPR_15TO14 field value from a register. */
7788 #define ALT_UART_CPR_RSVD_CPR_15TO14_GET(value) (((value) & 0x0000c000) >> 14)
7789 /* Produces a ALT_UART_CPR_RSVD_CPR_15TO14 register field value suitable for setting the register. */
7790 #define ALT_UART_CPR_RSVD_CPR_15TO14_SET(value) (((value) << 14) & 0x0000c000)
7791 
7792 /*
7793  * Field : fifo_mode
7794  *
7795  * Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf
7796  *
7797  * 0x00 = 0,
7798  *
7799  * 0x01 = 16,
7800  *
7801  * 0x02 = 32,
7802  *
7803  * toset
7804  *
7805  * 0x80 = 2048,
7806  *
7807  * 0x81- 0xff = reserved
7808  *
7809  * Field Enumeration Values:
7810  *
7811  * Enum | Value | Description
7812  * :-------------------------------------|:------|:---------------------
7813  * ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES | 0x80 | FIFO Depth 128 bytes
7814  *
7815  * Field Access Macros:
7816  *
7817  */
7818 /*
7819  * Enumerated value for register field ALT_UART_CPR_FIFO_MOD
7820  *
7821  * FIFO Depth 128 bytes
7822  */
7823 #define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80
7824 
7825 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
7826 #define ALT_UART_CPR_FIFO_MOD_LSB 16
7827 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field. */
7828 #define ALT_UART_CPR_FIFO_MOD_MSB 23
7829 /* The width in bits of the ALT_UART_CPR_FIFO_MOD register field. */
7830 #define ALT_UART_CPR_FIFO_MOD_WIDTH 8
7831 /* The mask used to set the ALT_UART_CPR_FIFO_MOD register field value. */
7832 #define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000
7833 /* The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value. */
7834 #define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff
7835 /* The reset value of the ALT_UART_CPR_FIFO_MOD register field. */
7836 #define ALT_UART_CPR_FIFO_MOD_RESET 0x8
7837 /* Extracts the ALT_UART_CPR_FIFO_MOD field value from a register. */
7838 #define ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16)
7839 /* Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register. */
7840 #define ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000)
7841 
7842 /*
7843  * Field : rsvd_cpr_31to24
7844  *
7845  * Reserved bits [31:24] - Read Only
7846  *
7847  * Field Access Macros:
7848  *
7849  */
7850 /* The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7851 #define ALT_UART_CPR_RSVD_CPR_31TO24_LSB 24
7852 /* The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7853 #define ALT_UART_CPR_RSVD_CPR_31TO24_MSB 31
7854 /* The width in bits of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7855 #define ALT_UART_CPR_RSVD_CPR_31TO24_WIDTH 8
7856 /* The mask used to set the ALT_UART_CPR_RSVD_CPR_31TO24 register field value. */
7857 #define ALT_UART_CPR_RSVD_CPR_31TO24_SET_MSK 0xff000000
7858 /* The mask used to clear the ALT_UART_CPR_RSVD_CPR_31TO24 register field value. */
7859 #define ALT_UART_CPR_RSVD_CPR_31TO24_CLR_MSK 0x00ffffff
7860 /* The reset value of the ALT_UART_CPR_RSVD_CPR_31TO24 register field. */
7861 #define ALT_UART_CPR_RSVD_CPR_31TO24_RESET 0x0
7862 /* Extracts the ALT_UART_CPR_RSVD_CPR_31TO24 field value from a register. */
7863 #define ALT_UART_CPR_RSVD_CPR_31TO24_GET(value) (((value) & 0xff000000) >> 24)
7864 /* Produces a ALT_UART_CPR_RSVD_CPR_31TO24 register field value suitable for setting the register. */
7865 #define ALT_UART_CPR_RSVD_CPR_31TO24_SET(value) (((value) << 24) & 0xff000000)
7866 
7867 #ifndef __ASSEMBLY__
7868 /*
7869  * WARNING: The C register and register group struct declarations are provided for
7870  * convenience and illustrative purposes. They should, however, be used with
7871  * caution as the C language standard provides no guarantees about the alignment or
7872  * atomicity of device memory accesses. The recommended practice for writing
7873  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7874  * alt_write_word() functions.
7875  *
7876  * The struct declaration for register ALT_UART_CPR.
7877  */
7878 struct ALT_UART_CPR_s
7879 {
7880  const uint32_t apbdatawidth : 2; /* ALT_UART_CPR_APBDATAWIDTH */
7881  const uint32_t rsvd_cpr_3to2 : 2; /* ALT_UART_CPR_RSVD_CPR_3TO2 */
7882  const uint32_t afce_mode : 1; /* ALT_UART_CPR_AFCE_MOD */
7883  const uint32_t thre_mode : 1; /* ALT_UART_CPR_THRE_MOD */
7884  const uint32_t sir_mode : 1; /* ALT_UART_CPR_SIR_MOD */
7885  const uint32_t sir_lp_mode : 1; /* ALT_UART_CPR_SIR_LP_MOD */
7886  const uint32_t additional_feat : 1; /* ALT_UART_CPR_ADDITIONAL_FEAT */
7887  const uint32_t fifo_access : 1; /* ALT_UART_CPR_FIFO_ACCESS */
7888  const uint32_t fifo_stat : 1; /* ALT_UART_CPR_FIFO_STAT */
7889  const uint32_t shadow : 1; /* ALT_UART_CPR_SHADOW */
7890  const uint32_t uart_add_encoded_param : 1; /* ALT_UART_CPR_UART_ADD_ENC_PARAM */
7891  const uint32_t dma_extra : 1; /* ALT_UART_CPR_DMA_EXTRA */
7892  const uint32_t rsvd_cpr_15to14 : 2; /* ALT_UART_CPR_RSVD_CPR_15TO14 */
7893  const uint32_t fifo_mode : 8; /* ALT_UART_CPR_FIFO_MOD */
7894  const uint32_t rsvd_cpr_31to24 : 8; /* ALT_UART_CPR_RSVD_CPR_31TO24 */
7895 };
7896 
7897 /* The typedef declaration for register ALT_UART_CPR. */
7898 typedef volatile struct ALT_UART_CPR_s ALT_UART_CPR_t;
7899 #endif /* __ASSEMBLY__ */
7900 
7901 /* The reset value of the ALT_UART_CPR register. */
7902 #define ALT_UART_CPR_RESET 0x00083f32
7903 /* The byte offset of the ALT_UART_CPR register from the beginning of the component. */
7904 #define ALT_UART_CPR_OFST 0xf4
7905 /* The address of the ALT_UART_CPR register. */
7906 #define ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))
7907 
7908 /*
7909  * Register : ucv
7910  *
7911  * Component Version
7912  *
7913  * Register Layout
7914  *
7915  * Bits | Access | Reset | Description
7916  * :-------|:-------|:-----------|:--------------------------------
7917  * [31:0] | R | 0x3331342a | ALT_UART_UCV_UART_COMPONENT_VER
7918  *
7919  */
7920 /*
7921  * Field : uart_component_version
7922  *
7923  * ASCII value for each number in the version, followed by *.
7924  *
7925  * For example 32_30_31_2A represents the version 2.01*
7926  *
7927  * Field Access Macros:
7928  *
7929  */
7930 /* The Least Significant Bit (LSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
7931 #define ALT_UART_UCV_UART_COMPONENT_VER_LSB 0
7932 /* The Most Significant Bit (MSB) position of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
7933 #define ALT_UART_UCV_UART_COMPONENT_VER_MSB 31
7934 /* The width in bits of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
7935 #define ALT_UART_UCV_UART_COMPONENT_VER_WIDTH 32
7936 /* The mask used to set the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
7937 #define ALT_UART_UCV_UART_COMPONENT_VER_SET_MSK 0xffffffff
7938 /* The mask used to clear the ALT_UART_UCV_UART_COMPONENT_VER register field value. */
7939 #define ALT_UART_UCV_UART_COMPONENT_VER_CLR_MSK 0x00000000
7940 /* The reset value of the ALT_UART_UCV_UART_COMPONENT_VER register field. */
7941 #define ALT_UART_UCV_UART_COMPONENT_VER_RESET 0x3331342a
7942 /* Extracts the ALT_UART_UCV_UART_COMPONENT_VER field value from a register. */
7943 #define ALT_UART_UCV_UART_COMPONENT_VER_GET(value) (((value) & 0xffffffff) >> 0)
7944 /* Produces a ALT_UART_UCV_UART_COMPONENT_VER register field value suitable for setting the register. */
7945 #define ALT_UART_UCV_UART_COMPONENT_VER_SET(value) (((value) << 0) & 0xffffffff)
7946 
7947 #ifndef __ASSEMBLY__
7948 /*
7949  * WARNING: The C register and register group struct declarations are provided for
7950  * convenience and illustrative purposes. They should, however, be used with
7951  * caution as the C language standard provides no guarantees about the alignment or
7952  * atomicity of device memory accesses. The recommended practice for writing
7953  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7954  * alt_write_word() functions.
7955  *
7956  * The struct declaration for register ALT_UART_UCV.
7957  */
7958 struct ALT_UART_UCV_s
7959 {
7960  const uint32_t uart_component_version : 32; /* ALT_UART_UCV_UART_COMPONENT_VER */
7961 };
7962 
7963 /* The typedef declaration for register ALT_UART_UCV. */
7964 typedef volatile struct ALT_UART_UCV_s ALT_UART_UCV_t;
7965 #endif /* __ASSEMBLY__ */
7966 
7967 /* The reset value of the ALT_UART_UCV register. */
7968 #define ALT_UART_UCV_RESET 0x3331342a
7969 /* The byte offset of the ALT_UART_UCV register from the beginning of the component. */
7970 #define ALT_UART_UCV_OFST 0xf8
7971 /* The address of the ALT_UART_UCV register. */
7972 #define ALT_UART_UCV_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_UCV_OFST))
7973 
7974 /*
7975  * Register : ctr
7976  *
7977  * Component Type Register
7978  *
7979  * Register Layout
7980  *
7981  * Bits | Access | Reset | Description
7982  * :-------|:-------|:-----------|:---------------------------
7983  * [31:0] | R | 0x44570110 | ALT_UART_CTR_PERIPHERAL_ID
7984  *
7985  */
7986 /*
7987  * Field : peripheral_id
7988  *
7989  * This register contains the peripherals identification code.
7990  *
7991  * Field Access Macros:
7992  *
7993  */
7994 /* The Least Significant Bit (LSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7995 #define ALT_UART_CTR_PERIPHERAL_ID_LSB 0
7996 /* The Most Significant Bit (MSB) position of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7997 #define ALT_UART_CTR_PERIPHERAL_ID_MSB 31
7998 /* The width in bits of the ALT_UART_CTR_PERIPHERAL_ID register field. */
7999 #define ALT_UART_CTR_PERIPHERAL_ID_WIDTH 32
8000 /* The mask used to set the ALT_UART_CTR_PERIPHERAL_ID register field value. */
8001 #define ALT_UART_CTR_PERIPHERAL_ID_SET_MSK 0xffffffff
8002 /* The mask used to clear the ALT_UART_CTR_PERIPHERAL_ID register field value. */
8003 #define ALT_UART_CTR_PERIPHERAL_ID_CLR_MSK 0x00000000
8004 /* The reset value of the ALT_UART_CTR_PERIPHERAL_ID register field. */
8005 #define ALT_UART_CTR_PERIPHERAL_ID_RESET 0x44570110
8006 /* Extracts the ALT_UART_CTR_PERIPHERAL_ID field value from a register. */
8007 #define ALT_UART_CTR_PERIPHERAL_ID_GET(value) (((value) & 0xffffffff) >> 0)
8008 /* Produces a ALT_UART_CTR_PERIPHERAL_ID register field value suitable for setting the register. */
8009 #define ALT_UART_CTR_PERIPHERAL_ID_SET(value) (((value) << 0) & 0xffffffff)
8010 
8011 #ifndef __ASSEMBLY__
8012 /*
8013  * WARNING: The C register and register group struct declarations are provided for
8014  * convenience and illustrative purposes. They should, however, be used with
8015  * caution as the C language standard provides no guarantees about the alignment or
8016  * atomicity of device memory accesses. The recommended practice for writing
8017  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8018  * alt_write_word() functions.
8019  *
8020  * The struct declaration for register ALT_UART_CTR.
8021  */
8022 struct ALT_UART_CTR_s
8023 {
8024  const uint32_t peripheral_id : 32; /* ALT_UART_CTR_PERIPHERAL_ID */
8025 };
8026 
8027 /* The typedef declaration for register ALT_UART_CTR. */
8028 typedef volatile struct ALT_UART_CTR_s ALT_UART_CTR_t;
8029 #endif /* __ASSEMBLY__ */
8030 
8031 /* The reset value of the ALT_UART_CTR register. */
8032 #define ALT_UART_CTR_RESET 0x44570110
8033 /* The byte offset of the ALT_UART_CTR register from the beginning of the component. */
8034 #define ALT_UART_CTR_OFST 0xfc
8035 /* The address of the ALT_UART_CTR register. */
8036 #define ALT_UART_CTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CTR_OFST))
8037 
8038 #ifndef __ASSEMBLY__
8039 /*
8040  * WARNING: The C register and register group struct declarations are provided for
8041  * convenience and illustrative purposes. They should, however, be used with
8042  * caution as the C language standard provides no guarantees about the alignment or
8043  * atomicity of device memory accesses. The recommended practice for writing
8044  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8045  * alt_write_word() functions.
8046  *
8047  * The struct declaration for register group ALT_UART.
8048  */
8049 struct ALT_UART_s
8050 {
8051  ALT_UART_RBR_THR_DLL_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
8052  ALT_UART_IER_DLH_t ier_dlh; /* ALT_UART_IER_DLH */
8053  /* Union for registers colocated at base address offset #0x. */
8054  union
8055  {
8056  ALT_UART_IIR_t iir; /* ALT_UART_IIR */
8057  ALT_UART_FCR_t fcr; /* ALT_UART_FCR */
8058  } _u_0x8;
8059  ALT_UART_LCR_t lcr; /* ALT_UART_LCR */
8060  ALT_UART_MCR_t mcr; /* ALT_UART_MCR */
8061  ALT_UART_LSR_t lsr; /* ALT_UART_LSR */
8062  ALT_UART_MSR_t msr; /* ALT_UART_MSR */
8063  ALT_UART_SCR_t scr; /* ALT_UART_SCR */
8064  volatile uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
8065  ALT_UART_SRBR_t srbr_sthr_0; /* ALT_UART_SRBR */
8066  ALT_UART_SRBR_STHR_1_t srbr_sthr_1; /* ALT_UART_SRBR_STHR_1 */
8067  ALT_UART_SRBR_STHR_2_t srbr_sthr_2; /* ALT_UART_SRBR_STHR_2 */
8068  ALT_UART_SRBR_STHR_3_t srbr_sthr_3; /* ALT_UART_SRBR_STHR_3 */
8069  ALT_UART_SRBR_STHR_4_t srbr_sthr_4; /* ALT_UART_SRBR_STHR_4 */
8070  ALT_UART_SRBR_STHR_5_t srbr_sthr_5; /* ALT_UART_SRBR_STHR_5 */
8071  ALT_UART_SRBR_STHR_6_t srbr_sthr_6; /* ALT_UART_SRBR_STHR_6 */
8072  ALT_UART_SRBR_STHR_7_t srbr_sthr_7; /* ALT_UART_SRBR_STHR_7 */
8073  ALT_UART_SRBR_STHR_8_t srbr_sthr_8; /* ALT_UART_SRBR_STHR_8 */
8074  ALT_UART_SRBR_STHR_9_t srbr_sthr_9; /* ALT_UART_SRBR_STHR_9 */
8075  ALT_UART_SRBR_STHR_10_t srbr_sthr_10; /* ALT_UART_SRBR_STHR_10 */
8076  ALT_UART_SRBR_STHR_11_t srbr_sthr_11; /* ALT_UART_SRBR_STHR_11 */
8077  ALT_UART_SRBR_STHR_12_t srbr_sthr_12; /* ALT_UART_SRBR_STHR_12 */
8078  ALT_UART_SRBR_STHR_13_t srbr_sthr_13; /* ALT_UART_SRBR_STHR_13 */
8079  ALT_UART_SRBR_STHR_14_t srbr_sthr_14; /* ALT_UART_SRBR_STHR_14 */
8080  ALT_UART_SRBR_STHR_15_t srbr_sthr_15; /* ALT_UART_SRBR_STHR_15 */
8081  ALT_UART_FAR_t far; /* ALT_UART_FAR */
8082  ALT_UART_TFR_t tfr; /* ALT_UART_TFR */
8083  ALT_UART_RFW_t rfw; /* ALT_UART_RFW */
8084  ALT_UART_USR_t usr; /* ALT_UART_USR */
8085  ALT_UART_TFL_t tfl; /* ALT_UART_TFL */
8086  ALT_UART_RFL_t rfl; /* ALT_UART_RFL */
8087  ALT_UART_SRR_t srr; /* ALT_UART_SRR */
8088  ALT_UART_SRTS_t srts; /* ALT_UART_SRTS */
8089  ALT_UART_SBCR_t sbcr; /* ALT_UART_SBCR */
8090  ALT_UART_SDMAM_t sdmam; /* ALT_UART_SDMAM */
8091  ALT_UART_SFE_t sfe; /* ALT_UART_SFE */
8092  ALT_UART_SRT_t srt; /* ALT_UART_SRT */
8093  ALT_UART_STET_t stet; /* ALT_UART_STET */
8094  ALT_UART_HTX_t htx; /* ALT_UART_HTX */
8095  ALT_UART_DMASA_t dmasa; /* ALT_UART_DMASA */
8096  volatile uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
8097  ALT_UART_CPR_t cpr; /* ALT_UART_CPR */
8098  ALT_UART_UCV_t ucv; /* ALT_UART_UCV */
8099  ALT_UART_CTR_t ctr; /* ALT_UART_CTR */
8100 };
8101 
8102 /* The typedef declaration for register group ALT_UART. */
8103 typedef volatile struct ALT_UART_s ALT_UART_t;
8104 /* The struct declaration for the raw register contents of register group ALT_UART. */
8105 struct ALT_UART_raw_s
8106 {
8107  volatile uint32_t rbr_thr_dll; /* ALT_UART_RBR_THR_DLL */
8108  volatile uint32_t ier_dlh; /* ALT_UART_IER_DLH */
8109  /* Union for registers colocated at base address offset #0x. */
8110  union
8111  {
8112  volatile uint32_t iir; /* ALT_UART_IIR */
8113  volatile uint32_t fcr; /* ALT_UART_FCR */
8114  } _u_0x8;
8115  volatile uint32_t lcr; /* ALT_UART_LCR */
8116  volatile uint32_t mcr; /* ALT_UART_MCR */
8117  volatile uint32_t lsr; /* ALT_UART_LSR */
8118  volatile uint32_t msr; /* ALT_UART_MSR */
8119  volatile uint32_t scr; /* ALT_UART_SCR */
8120  uint32_t _pad_0x20_0x2f[4]; /* *UNDEFINED* */
8121  volatile uint32_t srbr_sthr_0; /* ALT_UART_SRBR */
8122  volatile uint32_t srbr_sthr_1; /* ALT_UART_SRBR_STHR_1 */
8123  volatile uint32_t srbr_sthr_2; /* ALT_UART_SRBR_STHR_2 */
8124  volatile uint32_t srbr_sthr_3; /* ALT_UART_SRBR_STHR_3 */
8125  volatile uint32_t srbr_sthr_4; /* ALT_UART_SRBR_STHR_4 */
8126  volatile uint32_t srbr_sthr_5; /* ALT_UART_SRBR_STHR_5 */
8127  volatile uint32_t srbr_sthr_6; /* ALT_UART_SRBR_STHR_6 */
8128  volatile uint32_t srbr_sthr_7; /* ALT_UART_SRBR_STHR_7 */
8129  volatile uint32_t srbr_sthr_8; /* ALT_UART_SRBR_STHR_8 */
8130  volatile uint32_t srbr_sthr_9; /* ALT_UART_SRBR_STHR_9 */
8131  volatile uint32_t srbr_sthr_10; /* ALT_UART_SRBR_STHR_10 */
8132  volatile uint32_t srbr_sthr_11; /* ALT_UART_SRBR_STHR_11 */
8133  volatile uint32_t srbr_sthr_12; /* ALT_UART_SRBR_STHR_12 */
8134  volatile uint32_t srbr_sthr_13; /* ALT_UART_SRBR_STHR_13 */
8135  volatile uint32_t srbr_sthr_14; /* ALT_UART_SRBR_STHR_14 */
8136  volatile uint32_t srbr_sthr_15; /* ALT_UART_SRBR_STHR_15 */
8137  volatile uint32_t far; /* ALT_UART_FAR */
8138  volatile uint32_t tfr; /* ALT_UART_TFR */
8139  volatile uint32_t rfw; /* ALT_UART_RFW */
8140  volatile uint32_t usr; /* ALT_UART_USR */
8141  volatile uint32_t tfl; /* ALT_UART_TFL */
8142  volatile uint32_t rfl; /* ALT_UART_RFL */
8143  volatile uint32_t srr; /* ALT_UART_SRR */
8144  volatile uint32_t srts; /* ALT_UART_SRTS */
8145  volatile uint32_t sbcr; /* ALT_UART_SBCR */
8146  volatile uint32_t sdmam; /* ALT_UART_SDMAM */
8147  volatile uint32_t sfe; /* ALT_UART_SFE */
8148  volatile uint32_t srt; /* ALT_UART_SRT */
8149  volatile uint32_t stet; /* ALT_UART_STET */
8150  volatile uint32_t htx; /* ALT_UART_HTX */
8151  volatile uint32_t dmasa; /* ALT_UART_DMASA */
8152  uint32_t _pad_0xac_0xf3[18]; /* *UNDEFINED* */
8153  volatile uint32_t cpr; /* ALT_UART_CPR */
8154  volatile uint32_t ucv; /* ALT_UART_UCV */
8155  volatile uint32_t ctr; /* ALT_UART_CTR */
8156 };
8157 
8158 /* The typedef declaration for the raw register contents of register group ALT_UART. */
8159 typedef volatile struct ALT_UART_raw_s ALT_UART_raw_t;
8160 #endif /* __ASSEMBLY__ */
8161 
8162 
8163 #ifdef __cplusplus
8164 }
8165 #endif /* __cplusplus */
8166 #endif /* __ALT_SOCAL_UART_H__ */
8167