Hardware Libraries  20.1
Arria 10 SoC Abstration Layer
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alt_noc_fw_ddr_mpu_f2sdr_ddr_scr.h
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32 
33 /* Altera - ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR
50  *
51  */
52 /*
53  * Register : enable
54  *
55  * Enable
56  *
57  * Register Layout
58  *
59  * Bits | Access | Reset | Description
60  * :--------|:-------|:------|:-------------------------------------------------
61  * [0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN
62  * [1] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN
63  * [2] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN
64  * [3] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN
65  * [4] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN
66  * [5] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN
67  * [6] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN
68  * [7] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN
69  * [8] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN
70  * [9] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN
71  * [10] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN
72  * [11] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN
73  * [12] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN
74  * [13] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN
75  * [14] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN
76  * [15] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN
77  * [31:16] | ??? | 0x0 | *UNDEFINED*
78  *
79  */
80 /*
81  * Field : mpuregion0enable
82  *
83  * MPU Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region
84  * is disabled
85  *
86  * Field Access Macros:
87  *
88  */
89 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field. */
90 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_LSB 0
91 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field. */
92 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_MSB 0
93 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field. */
94 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_WIDTH 1
95 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field value. */
96 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_SET_MSK 0x00000001
97 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field value. */
98 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_CLR_MSK 0xfffffffe
99 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field. */
100 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_RESET 0x0
101 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN field value from a register. */
102 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
103 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN register field value suitable for setting the register. */
104 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
105 
106 /*
107  * Field : mpuregion1enable
108  *
109  * MPU Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region
110  * is disabled
111  *
112  * Field Access Macros:
113  *
114  */
115 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field. */
116 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_LSB 1
117 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field. */
118 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_MSB 1
119 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field. */
120 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_WIDTH 1
121 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field value. */
122 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_SET_MSK 0x00000002
123 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field value. */
124 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_CLR_MSK 0xfffffffd
125 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field. */
126 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_RESET 0x0
127 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN field value from a register. */
128 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
129 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN register field value suitable for setting the register. */
130 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
131 
132 /*
133  * Field : mpuregion2enable
134  *
135  * MPU Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region
136  * is disabled
137  *
138  * Field Access Macros:
139  *
140  */
141 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field. */
142 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_LSB 2
143 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field. */
144 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_MSB 2
145 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field. */
146 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_WIDTH 1
147 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field value. */
148 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_SET_MSK 0x00000004
149 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field value. */
150 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_CLR_MSK 0xfffffffb
151 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field. */
152 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_RESET 0x0
153 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN field value from a register. */
154 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
155 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN register field value suitable for setting the register. */
156 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
157 
158 /*
159  * Field : mpuregion3enable
160  *
161  * MPU Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region
162  * is disabled
163  *
164  * Field Access Macros:
165  *
166  */
167 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field. */
168 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_LSB 3
169 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field. */
170 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_MSB 3
171 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field. */
172 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_WIDTH 1
173 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field value. */
174 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_SET_MSK 0x00000008
175 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field value. */
176 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_CLR_MSK 0xfffffff7
177 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field. */
178 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_RESET 0x0
179 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN field value from a register. */
180 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
181 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN register field value suitable for setting the register. */
182 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
183 
184 /*
185  * Field : fpga2sdram0region0enable
186  *
187  * FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means
188  * region is disabled
189  *
190  * Field Access Macros:
191  *
192  */
193 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field. */
194 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_LSB 4
195 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field. */
196 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_MSB 4
197 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field. */
198 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_WIDTH 1
199 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field value. */
200 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK 0x00000010
201 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field value. */
202 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_CLR_MSK 0xffffffef
203 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field. */
204 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_RESET 0x0
205 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN field value from a register. */
206 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
207 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN register field value suitable for setting the register. */
208 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
209 
210 /*
211  * Field : fpga2sdram0region1enable
212  *
213  * FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means
214  * region is disabled
215  *
216  * Field Access Macros:
217  *
218  */
219 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field. */
220 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_LSB 5
221 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field. */
222 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_MSB 5
223 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field. */
224 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_WIDTH 1
225 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field value. */
226 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK 0x00000020
227 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field value. */
228 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_CLR_MSK 0xffffffdf
229 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field. */
230 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_RESET 0x0
231 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN field value from a register. */
232 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
233 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN register field value suitable for setting the register. */
234 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
235 
236 /*
237  * Field : fpga2sdram0region2enable
238  *
239  * FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means
240  * region is disabled
241  *
242  * Field Access Macros:
243  *
244  */
245 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field. */
246 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_LSB 6
247 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field. */
248 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_MSB 6
249 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field. */
250 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_WIDTH 1
251 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field value. */
252 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK 0x00000040
253 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field value. */
254 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_CLR_MSK 0xffffffbf
255 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field. */
256 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_RESET 0x0
257 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN field value from a register. */
258 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
259 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN register field value suitable for setting the register. */
260 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
261 
262 /*
263  * Field : fpga2sdram0region3enable
264  *
265  * FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means
266  * region is disabled
267  *
268  * Field Access Macros:
269  *
270  */
271 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field. */
272 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_LSB 7
273 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field. */
274 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_MSB 7
275 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field. */
276 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_WIDTH 1
277 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field value. */
278 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK 0x00000080
279 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field value. */
280 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_CLR_MSK 0xffffff7f
281 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field. */
282 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_RESET 0x0
283 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN field value from a register. */
284 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
285 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN register field value suitable for setting the register. */
286 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
287 
288 /*
289  * Field : fpga2sdram1region0enable
290  *
291  * FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means
292  * region is disabled
293  *
294  * Field Access Macros:
295  *
296  */
297 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field. */
298 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_LSB 8
299 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field. */
300 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_MSB 8
301 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field. */
302 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_WIDTH 1
303 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field value. */
304 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK 0x00000100
305 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field value. */
306 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_CLR_MSK 0xfffffeff
307 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field. */
308 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_RESET 0x0
309 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN field value from a register. */
310 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
311 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN register field value suitable for setting the register. */
312 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
313 
314 /*
315  * Field : fpga2sdram1region1enable
316  *
317  * FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means
318  * region is disabled
319  *
320  * Field Access Macros:
321  *
322  */
323 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field. */
324 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_LSB 9
325 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field. */
326 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_MSB 9
327 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field. */
328 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_WIDTH 1
329 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field value. */
330 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK 0x00000200
331 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field value. */
332 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_CLR_MSK 0xfffffdff
333 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field. */
334 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_RESET 0x0
335 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN field value from a register. */
336 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
337 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN register field value suitable for setting the register. */
338 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
339 
340 /*
341  * Field : fpga2sdram1region2enable
342  *
343  * FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means
344  * region is disabled
345  *
346  * Field Access Macros:
347  *
348  */
349 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field. */
350 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_LSB 10
351 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field. */
352 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_MSB 10
353 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field. */
354 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_WIDTH 1
355 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field value. */
356 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK 0x00000400
357 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field value. */
358 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_CLR_MSK 0xfffffbff
359 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field. */
360 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_RESET 0x0
361 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN field value from a register. */
362 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
363 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN register field value suitable for setting the register. */
364 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
365 
366 /*
367  * Field : fpga2sdram1region3enable
368  *
369  * FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means
370  * region is disabled
371  *
372  * Field Access Macros:
373  *
374  */
375 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field. */
376 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_LSB 11
377 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field. */
378 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_MSB 11
379 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field. */
380 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_WIDTH 1
381 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field value. */
382 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK 0x00000800
383 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field value. */
384 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
385 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field. */
386 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_RESET 0x0
387 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN field value from a register. */
388 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
389 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN register field value suitable for setting the register. */
390 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
391 
392 /*
393  * Field : fpga2sdram2region0enable
394  *
395  * FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means
396  * region is disabled
397  *
398  * Field Access Macros:
399  *
400  */
401 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field. */
402 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_LSB 12
403 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field. */
404 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_MSB 12
405 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field. */
406 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_WIDTH 1
407 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field value. */
408 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK 0x00001000
409 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field value. */
410 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_CLR_MSK 0xffffefff
411 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field. */
412 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_RESET 0x0
413 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN field value from a register. */
414 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
415 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN register field value suitable for setting the register. */
416 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
417 
418 /*
419  * Field : fpga2sdram2region1enable
420  *
421  * FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means
422  * region is disabled
423  *
424  * Field Access Macros:
425  *
426  */
427 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field. */
428 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_LSB 13
429 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field. */
430 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_MSB 13
431 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field. */
432 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_WIDTH 1
433 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field value. */
434 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK 0x00002000
435 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field value. */
436 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_CLR_MSK 0xffffdfff
437 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field. */
438 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_RESET 0x0
439 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN field value from a register. */
440 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
441 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN register field value suitable for setting the register. */
442 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
443 
444 /*
445  * Field : fpga2sdram2region2enable
446  *
447  * FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means
448  * region is disabled
449  *
450  * Field Access Macros:
451  *
452  */
453 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field. */
454 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_LSB 14
455 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field. */
456 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_MSB 14
457 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field. */
458 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_WIDTH 1
459 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field value. */
460 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK 0x00004000
461 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field value. */
462 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_CLR_MSK 0xffffbfff
463 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field. */
464 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_RESET 0x0
465 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN field value from a register. */
466 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
467 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN register field value suitable for setting the register. */
468 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
469 
470 /*
471  * Field : fpga2sdram2region3enable
472  *
473  * FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means
474  * region is disabled
475  *
476  * Field Access Macros:
477  *
478  */
479 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field. */
480 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_LSB 15
481 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field. */
482 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_MSB 15
483 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field. */
484 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_WIDTH 1
485 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field value. */
486 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK 0x00008000
487 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field value. */
488 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_CLR_MSK 0xffff7fff
489 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field. */
490 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_RESET 0x0
491 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN field value from a register. */
492 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
493 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN register field value suitable for setting the register. */
494 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
495 
496 #ifndef __ASSEMBLY__
497 /*
498  * WARNING: The C register and register group struct declarations are provided for
499  * convenience and illustrative purposes. They should, however, be used with
500  * caution as the C language standard provides no guarantees about the alignment or
501  * atomicity of device memory accesses. The recommended practice for writing
502  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
503  * alt_write_word() functions.
504  *
505  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN.
506  */
507 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_s
508 {
509  uint32_t mpuregion0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN */
510  uint32_t mpuregion1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN */
511  uint32_t mpuregion2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN */
512  uint32_t mpuregion3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN */
513  uint32_t fpga2sdram0region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN */
514  uint32_t fpga2sdram0region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN */
515  uint32_t fpga2sdram0region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN */
516  uint32_t fpga2sdram0region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN */
517  uint32_t fpga2sdram1region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN */
518  uint32_t fpga2sdram1region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN */
519  uint32_t fpga2sdram1region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN */
520  uint32_t fpga2sdram1region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN */
521  uint32_t fpga2sdram2region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN */
522  uint32_t fpga2sdram2region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN */
523  uint32_t fpga2sdram2region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN */
524  uint32_t fpga2sdram2region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN */
525  uint32_t : 16; /* *UNDEFINED* */
526 };
527 
528 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN. */
529 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_t;
530 #endif /* __ASSEMBLY__ */
531 
532 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN register. */
533 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_RESET 0x00000000
534 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN register from the beginning of the component. */
535 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_OFST 0x0
536 
537 /*
538  * Register : enable_set
539  *
540  * Sets Master Region Enable field when written with 1
541  *
542  * Register Layout
543  *
544  * Bits | Access | Reset | Description
545  * :--------|:-------|:------|:-----------------------------------------------------
546  * [0] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN
547  * [1] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN
548  * [2] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN
549  * [3] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN
550  * [4] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN
551  * [5] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN
552  * [6] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN
553  * [7] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN
554  * [8] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN
555  * [9] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN
556  * [10] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN
557  * [11] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN
558  * [12] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN
559  * [13] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN
560  * [14] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN
561  * [15] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN
562  * [31:16] | ??? | 0x0 | *UNDEFINED*
563  *
564  */
565 /*
566  * Field : mpuregion0enable
567  *
568  * MPU Region 0 Enable Set.
569  *
570  * Writing zero has no effect
571  *
572  * Writing one will set the mpuregion0enable bit to one
573  *
574  * Field Access Macros:
575  *
576  */
577 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field. */
578 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_LSB 0
579 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field. */
580 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_MSB 0
581 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field. */
582 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_WIDTH 1
583 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value. */
584 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET_MSK 0x00000001
585 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value. */
586 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_CLR_MSK 0xfffffffe
587 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field. */
588 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_RESET 0x0
589 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN field value from a register. */
590 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
591 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value suitable for setting the register. */
592 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
593 
594 /*
595  * Field : mpuregion1enable
596  *
597  * MPU Region 1 Enable Set.
598  *
599  * Writing zero has no effect
600  *
601  * Writing one will set the mpuregion1enable bit to one
602  *
603  * Field Access Macros:
604  *
605  */
606 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field. */
607 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_LSB 1
608 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field. */
609 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_MSB 1
610 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field. */
611 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_WIDTH 1
612 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value. */
613 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET_MSK 0x00000002
614 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value. */
615 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_CLR_MSK 0xfffffffd
616 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field. */
617 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_RESET 0x0
618 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN field value from a register. */
619 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
620 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value suitable for setting the register. */
621 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
622 
623 /*
624  * Field : mpuregion2enable
625  *
626  * MPU Region 2 Enable Set.
627  *
628  * Writing zero has no effect
629  *
630  * Writing one will set the mpuregion2enable bit to one
631  *
632  * Field Access Macros:
633  *
634  */
635 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field. */
636 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_LSB 2
637 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field. */
638 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_MSB 2
639 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field. */
640 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_WIDTH 1
641 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value. */
642 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET_MSK 0x00000004
643 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value. */
644 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_CLR_MSK 0xfffffffb
645 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field. */
646 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_RESET 0x0
647 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN field value from a register. */
648 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
649 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value suitable for setting the register. */
650 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
651 
652 /*
653  * Field : mpuregion3enable
654  *
655  * MPU Region 3 Enable Set.
656  *
657  * Writing zero has no effect
658  *
659  * Writing one will set the mpuregion3enable bit to one
660  *
661  * Field Access Macros:
662  *
663  */
664 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field. */
665 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_LSB 3
666 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field. */
667 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_MSB 3
668 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field. */
669 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_WIDTH 1
670 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value. */
671 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET_MSK 0x00000008
672 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value. */
673 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_CLR_MSK 0xfffffff7
674 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field. */
675 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_RESET 0x0
676 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN field value from a register. */
677 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
678 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value suitable for setting the register. */
679 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
680 
681 /*
682  * Field : fpga2sdram0region0enable
683  *
684  * FPGA2SDRAM0 Region 0 Enable Set.
685  *
686  * Writing zero has no effect
687  *
688  * Writing one will set the fpga2sdram0region0enable bit to one
689  *
690  * Field Access Macros:
691  *
692  */
693 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field. */
694 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_LSB 4
695 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field. */
696 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_MSB 4
697 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field. */
698 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_WIDTH 1
699 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value. */
700 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET_MSK 0x00000010
701 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value. */
702 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_CLR_MSK 0xffffffef
703 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field. */
704 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_RESET 0x0
705 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN field value from a register. */
706 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
707 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value suitable for setting the register. */
708 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
709 
710 /*
711  * Field : fpga2sdram0region1enable
712  *
713  * FPGA2SDRAM0 Region 1 Enable Set.
714  *
715  * Writing zero has no effect
716  *
717  * Writing one will set the fpga2sdram0region1enable bit to one
718  *
719  * Field Access Macros:
720  *
721  */
722 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field. */
723 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_LSB 5
724 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field. */
725 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_MSB 5
726 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field. */
727 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_WIDTH 1
728 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value. */
729 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET_MSK 0x00000020
730 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value. */
731 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_CLR_MSK 0xffffffdf
732 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field. */
733 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_RESET 0x0
734 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN field value from a register. */
735 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
736 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value suitable for setting the register. */
737 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
738 
739 /*
740  * Field : fpga2sdram0region2enable
741  *
742  * FPGA2SDRAM0 Region 2 Enable Set.
743  *
744  * Writing zero has no effect
745  *
746  * Writing one will set the fpga2sdram0region2enable bit to one
747  *
748  * Field Access Macros:
749  *
750  */
751 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field. */
752 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_LSB 6
753 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field. */
754 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_MSB 6
755 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field. */
756 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_WIDTH 1
757 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value. */
758 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET_MSK 0x00000040
759 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value. */
760 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_CLR_MSK 0xffffffbf
761 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field. */
762 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_RESET 0x0
763 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN field value from a register. */
764 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
765 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value suitable for setting the register. */
766 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
767 
768 /*
769  * Field : fpga2sdram0region3enable
770  *
771  * FPGA2SDRAM0 Region 3 Enable Set.
772  *
773  * Writing zero has no effect
774  *
775  * Writing one will set the fpga2sdram0region3enable bit to one
776  *
777  * Field Access Macros:
778  *
779  */
780 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field. */
781 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_LSB 7
782 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field. */
783 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_MSB 7
784 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field. */
785 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_WIDTH 1
786 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value. */
787 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET_MSK 0x00000080
788 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value. */
789 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_CLR_MSK 0xffffff7f
790 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field. */
791 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_RESET 0x0
792 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN field value from a register. */
793 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
794 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value suitable for setting the register. */
795 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
796 
797 /*
798  * Field : fpga2sdram1region0enable
799  *
800  * FPGA2SDRAM1 Region 0 Enable Set.
801  *
802  * Writing zero has no effect
803  *
804  * Writing one will set the fpga2sdram1region0enable bit to one
805  *
806  * Field Access Macros:
807  *
808  */
809 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field. */
810 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_LSB 8
811 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field. */
812 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_MSB 8
813 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field. */
814 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_WIDTH 1
815 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value. */
816 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET_MSK 0x00000100
817 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value. */
818 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_CLR_MSK 0xfffffeff
819 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field. */
820 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_RESET 0x0
821 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN field value from a register. */
822 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
823 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value suitable for setting the register. */
824 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
825 
826 /*
827  * Field : fpga2sdram1region1enable
828  *
829  * FPGA2SDRAM1 Region 1 Enable Set.
830  *
831  * Writing zero has no effect
832  *
833  * Writing one will set the fpga2sdram1region1enable bit to one
834  *
835  * Field Access Macros:
836  *
837  */
838 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field. */
839 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_LSB 9
840 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field. */
841 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_MSB 9
842 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field. */
843 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_WIDTH 1
844 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value. */
845 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET_MSK 0x00000200
846 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value. */
847 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_CLR_MSK 0xfffffdff
848 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field. */
849 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_RESET 0x0
850 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN field value from a register. */
851 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
852 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value suitable for setting the register. */
853 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
854 
855 /*
856  * Field : fpga2sdram1region2enable
857  *
858  * FPGA2SDRAM1 Region 2 Enable Set.
859  *
860  * Writing zero has no effect
861  *
862  * Writing one will set the fpga2sdram1region2enable bit to one
863  *
864  * Field Access Macros:
865  *
866  */
867 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field. */
868 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_LSB 10
869 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field. */
870 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_MSB 10
871 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field. */
872 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_WIDTH 1
873 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value. */
874 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET_MSK 0x00000400
875 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value. */
876 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_CLR_MSK 0xfffffbff
877 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field. */
878 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_RESET 0x0
879 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN field value from a register. */
880 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
881 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value suitable for setting the register. */
882 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
883 
884 /*
885  * Field : fpga2sdram1region3enable
886  *
887  * FPGA2SDRAM1 Region 3 Enable Set.
888  *
889  * Writing zero has no effect
890  *
891  * Writing one will set the fpga2sdram1region3enable bit to one
892  *
893  * Field Access Macros:
894  *
895  */
896 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field. */
897 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_LSB 11
898 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field. */
899 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_MSB 11
900 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field. */
901 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_WIDTH 1
902 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value. */
903 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET_MSK 0x00000800
904 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value. */
905 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
906 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field. */
907 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_RESET 0x0
908 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN field value from a register. */
909 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
910 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value suitable for setting the register. */
911 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
912 
913 /*
914  * Field : fpga2sdram2region0enable
915  *
916  * FPGA2SDRAM2 Region 0 Enable Set.
917  *
918  * Writing zero has no effect
919  *
920  * Writing one will set the fpga2sdram2region0enable bit to one
921  *
922  * Field Access Macros:
923  *
924  */
925 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field. */
926 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_LSB 12
927 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field. */
928 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_MSB 12
929 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field. */
930 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_WIDTH 1
931 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value. */
932 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET_MSK 0x00001000
933 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value. */
934 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_CLR_MSK 0xffffefff
935 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field. */
936 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_RESET 0x0
937 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN field value from a register. */
938 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
939 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value suitable for setting the register. */
940 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
941 
942 /*
943  * Field : fpga2sdram2region1enable
944  *
945  * FPGA2SDRAM2 Region 1 Enable Set.
946  *
947  * Writing zero has no effect
948  *
949  * Writing one will set the fpga2sdram2region1enable bit to one
950  *
951  * Field Access Macros:
952  *
953  */
954 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field. */
955 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_LSB 13
956 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field. */
957 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_MSB 13
958 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field. */
959 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_WIDTH 1
960 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value. */
961 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET_MSK 0x00002000
962 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value. */
963 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_CLR_MSK 0xffffdfff
964 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field. */
965 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_RESET 0x0
966 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN field value from a register. */
967 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
968 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value suitable for setting the register. */
969 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
970 
971 /*
972  * Field : fpga2sdram2region2enable
973  *
974  * FPGA2SDRAM2 Region 2 Enable Set.
975  *
976  * Writing zero has no effect
977  *
978  * Writing one will set the fpga2sdram2region2enable bit to one
979  *
980  * Field Access Macros:
981  *
982  */
983 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field. */
984 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_LSB 14
985 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field. */
986 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_MSB 14
987 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field. */
988 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_WIDTH 1
989 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value. */
990 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET_MSK 0x00004000
991 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value. */
992 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_CLR_MSK 0xffffbfff
993 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field. */
994 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_RESET 0x0
995 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN field value from a register. */
996 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
997 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value suitable for setting the register. */
998 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
999 
1000 /*
1001  * Field : fpga2sdram2region3enable
1002  *
1003  * FPGA2SDRAM2 Region 3 Enable Set.
1004  *
1005  * Writing zero has no effect
1006  *
1007  * Writing one will set the fpga2sdram2region3enable bit to one
1008  *
1009  * Field Access Macros:
1010  *
1011  */
1012 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field. */
1013 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_LSB 15
1014 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field. */
1015 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_MSB 15
1016 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field. */
1017 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_WIDTH 1
1018 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value. */
1019 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET_MSK 0x00008000
1020 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value. */
1021 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_CLR_MSK 0xffff7fff
1022 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field. */
1023 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_RESET 0x0
1024 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN field value from a register. */
1025 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
1026 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value suitable for setting the register. */
1027 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
1028 
1029 #ifndef __ASSEMBLY__
1030 /*
1031  * WARNING: The C register and register group struct declarations are provided for
1032  * convenience and illustrative purposes. They should, however, be used with
1033  * caution as the C language standard provides no guarantees about the alignment or
1034  * atomicity of device memory accesses. The recommended practice for writing
1035  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1036  * alt_write_word() functions.
1037  *
1038  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET.
1039  */
1040 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s
1041 {
1042  uint32_t mpuregion0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN */
1043  uint32_t mpuregion1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN */
1044  uint32_t mpuregion2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN */
1045  uint32_t mpuregion3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN */
1046  uint32_t fpga2sdram0region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN */
1047  uint32_t fpga2sdram0region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN */
1048  uint32_t fpga2sdram0region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN */
1049  uint32_t fpga2sdram0region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN */
1050  uint32_t fpga2sdram1region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN */
1051  uint32_t fpga2sdram1region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN */
1052  uint32_t fpga2sdram1region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN */
1053  uint32_t fpga2sdram1region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN */
1054  uint32_t fpga2sdram2region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN */
1055  uint32_t fpga2sdram2region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN */
1056  uint32_t fpga2sdram2region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN */
1057  uint32_t fpga2sdram2region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN */
1058  uint32_t : 16; /* *UNDEFINED* */
1059 };
1060 
1061 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET. */
1062 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_t;
1063 #endif /* __ASSEMBLY__ */
1064 
1065 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET register. */
1066 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_RESET 0x00000000
1067 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET register from the beginning of the component. */
1068 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_OFST 0x4
1069 
1070 /*
1071  * Register : enable_clear
1072  *
1073  * Clears Master Region Enable field when written with 1
1074  *
1075  * Register Layout
1076  *
1077  * Bits | Access | Reset | Description
1078  * :--------|:-------|:------|:-----------------------------------------------------
1079  * [0] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN
1080  * [1] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN
1081  * [2] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN
1082  * [3] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN
1083  * [4] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN
1084  * [5] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN
1085  * [6] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN
1086  * [7] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN
1087  * [8] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN
1088  * [9] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN
1089  * [10] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN
1090  * [11] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN
1091  * [12] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN
1092  * [13] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN
1093  * [14] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN
1094  * [15] | W | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN
1095  * [31:16] | ??? | 0x0 | *UNDEFINED*
1096  *
1097  */
1098 /*
1099  * Field : mpuregion0enable
1100  *
1101  * MPU Region 0 Enable Clear.
1102  *
1103  * Writing zero has no effect
1104  *
1105  * Writing one will clear the mpuregion0enable bit to zero
1106  *
1107  * Field Access Macros:
1108  *
1109  */
1110 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field. */
1111 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_LSB 0
1112 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field. */
1113 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_MSB 0
1114 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field. */
1115 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_WIDTH 1
1116 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field value. */
1117 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_SET_MSK 0x00000001
1118 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field value. */
1119 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_CLR_MSK 0xfffffffe
1120 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field. */
1121 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_RESET 0x0
1122 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN field value from a register. */
1123 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
1124 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN register field value suitable for setting the register. */
1125 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
1126 
1127 /*
1128  * Field : mpuregion1enable
1129  *
1130  * MPU Region 1 Enable Clear.
1131  *
1132  * Writing zero has no effect
1133  *
1134  * Writing one will clear the mpuregion1enable bit to zero
1135  *
1136  * Field Access Macros:
1137  *
1138  */
1139 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field. */
1140 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_LSB 1
1141 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field. */
1142 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_MSB 1
1143 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field. */
1144 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_WIDTH 1
1145 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field value. */
1146 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_SET_MSK 0x00000002
1147 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field value. */
1148 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_CLR_MSK 0xfffffffd
1149 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field. */
1150 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_RESET 0x0
1151 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN field value from a register. */
1152 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
1153 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN register field value suitable for setting the register. */
1154 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
1155 
1156 /*
1157  * Field : mpuregion2enable
1158  *
1159  * MPU Region 2 Enable Clear.
1160  *
1161  * Writing zero has no effect
1162  *
1163  * Writing one will clear the mpuregion2enable bit to zero
1164  *
1165  * Field Access Macros:
1166  *
1167  */
1168 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field. */
1169 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_LSB 2
1170 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field. */
1171 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_MSB 2
1172 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field. */
1173 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_WIDTH 1
1174 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field value. */
1175 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_SET_MSK 0x00000004
1176 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field value. */
1177 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_CLR_MSK 0xfffffffb
1178 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field. */
1179 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_RESET 0x0
1180 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN field value from a register. */
1181 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
1182 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN register field value suitable for setting the register. */
1183 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
1184 
1185 /*
1186  * Field : mpuregion3enable
1187  *
1188  * MPU Region 3 Enable Clear.
1189  *
1190  * Writing zero has no effect
1191  *
1192  * Writing one will clear the mpuregion3enable bit to zero
1193  *
1194  * Field Access Macros:
1195  *
1196  */
1197 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field. */
1198 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_LSB 3
1199 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field. */
1200 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_MSB 3
1201 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field. */
1202 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_WIDTH 1
1203 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field value. */
1204 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_SET_MSK 0x00000008
1205 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field value. */
1206 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_CLR_MSK 0xfffffff7
1207 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field. */
1208 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_RESET 0x0
1209 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN field value from a register. */
1210 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
1211 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN register field value suitable for setting the register. */
1212 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
1213 
1214 /*
1215  * Field : fpga2sdram0region0enable
1216  *
1217  * FPGA2SDRAM0 Region 0 Enable Clear.
1218  *
1219  * Writing zero has no effect
1220  *
1221  * Writing one will clear the fpga2sdram0region0enable bit to zero
1222  *
1223  * Field Access Macros:
1224  *
1225  */
1226 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field. */
1227 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_LSB 4
1228 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field. */
1229 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_MSB 4
1230 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field. */
1231 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_WIDTH 1
1232 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field value. */
1233 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_SET_MSK 0x00000010
1234 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field value. */
1235 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_CLR_MSK 0xffffffef
1236 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field. */
1237 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_RESET 0x0
1238 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN field value from a register. */
1239 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
1240 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN register field value suitable for setting the register. */
1241 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
1242 
1243 /*
1244  * Field : fpga2sdram0region1enable
1245  *
1246  * FPGA2SDRAM0 Region 1 Enable Clear.
1247  *
1248  * Writing zero has no effect
1249  *
1250  * Writing one will clear the fpga2sdram0region1enable bit to zero
1251  *
1252  * Field Access Macros:
1253  *
1254  */
1255 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field. */
1256 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_LSB 5
1257 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field. */
1258 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_MSB 5
1259 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field. */
1260 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_WIDTH 1
1261 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field value. */
1262 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_SET_MSK 0x00000020
1263 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field value. */
1264 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_CLR_MSK 0xffffffdf
1265 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field. */
1266 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_RESET 0x0
1267 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN field value from a register. */
1268 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
1269 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN register field value suitable for setting the register. */
1270 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
1271 
1272 /*
1273  * Field : fpga2sdram0region2enable
1274  *
1275  * FPGA2SDRAM0 Region 2 Enable Clear.
1276  *
1277  * Writing zero has no effect
1278  *
1279  * Writing one will clear the fpga2sdram0region2enable bit to zero
1280  *
1281  * Field Access Macros:
1282  *
1283  */
1284 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field. */
1285 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_LSB 6
1286 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field. */
1287 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_MSB 6
1288 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field. */
1289 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_WIDTH 1
1290 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field value. */
1291 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_SET_MSK 0x00000040
1292 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field value. */
1293 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_CLR_MSK 0xffffffbf
1294 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field. */
1295 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_RESET 0x0
1296 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN field value from a register. */
1297 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
1298 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN register field value suitable for setting the register. */
1299 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
1300 
1301 /*
1302  * Field : fpga2sdram0region3enable
1303  *
1304  * FPGA2SDRAM0 Region 3 Enable Clear.
1305  *
1306  * Writing zero has no effect
1307  *
1308  * Writing one will clear the fpga2sdram0region3enable bit to zero
1309  *
1310  * Field Access Macros:
1311  *
1312  */
1313 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field. */
1314 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_LSB 7
1315 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field. */
1316 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_MSB 7
1317 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field. */
1318 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_WIDTH 1
1319 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field value. */
1320 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_SET_MSK 0x00000080
1321 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field value. */
1322 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_CLR_MSK 0xffffff7f
1323 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field. */
1324 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_RESET 0x0
1325 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN field value from a register. */
1326 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
1327 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN register field value suitable for setting the register. */
1328 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
1329 
1330 /*
1331  * Field : fpga2sdram1region0enable
1332  *
1333  * FPGA2SDRAM1 Region 0 Enable Clear.
1334  *
1335  * Writing zero has no effect
1336  *
1337  * Writing one will clear the fpga2sdram1region0enable bit to zero
1338  *
1339  * Field Access Macros:
1340  *
1341  */
1342 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field. */
1343 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_LSB 8
1344 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field. */
1345 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_MSB 8
1346 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field. */
1347 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_WIDTH 1
1348 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field value. */
1349 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_SET_MSK 0x00000100
1350 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field value. */
1351 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_CLR_MSK 0xfffffeff
1352 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field. */
1353 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_RESET 0x0
1354 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN field value from a register. */
1355 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
1356 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN register field value suitable for setting the register. */
1357 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
1358 
1359 /*
1360  * Field : fpga2sdram1region1enable
1361  *
1362  * FPGA2SDRAM1 Region 1 Enable Clear.
1363  *
1364  * Writing zero has no effect
1365  *
1366  * Writing one will clear the fpga2sdram1region1enable bit to zero
1367  *
1368  * Field Access Macros:
1369  *
1370  */
1371 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field. */
1372 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_LSB 9
1373 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field. */
1374 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_MSB 9
1375 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field. */
1376 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_WIDTH 1
1377 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field value. */
1378 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_SET_MSK 0x00000200
1379 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field value. */
1380 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_CLR_MSK 0xfffffdff
1381 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field. */
1382 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_RESET 0x0
1383 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN field value from a register. */
1384 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
1385 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN register field value suitable for setting the register. */
1386 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
1387 
1388 /*
1389  * Field : fpga2sdram1region2enable
1390  *
1391  * FPGA2SDRAM1 Region 2 Enable Clear.
1392  *
1393  * Writing zero has no effect
1394  *
1395  * Writing one will clear the fpga2sdram1region2enable bit to zero
1396  *
1397  * Field Access Macros:
1398  *
1399  */
1400 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field. */
1401 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_LSB 10
1402 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field. */
1403 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_MSB 10
1404 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field. */
1405 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_WIDTH 1
1406 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field value. */
1407 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_SET_MSK 0x00000400
1408 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field value. */
1409 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_CLR_MSK 0xfffffbff
1410 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field. */
1411 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_RESET 0x0
1412 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN field value from a register. */
1413 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
1414 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN register field value suitable for setting the register. */
1415 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
1416 
1417 /*
1418  * Field : fpga2sdram1region3enable
1419  *
1420  * FPGA2SDRAM1 Region 3 Enable Clear.
1421  *
1422  * Writing zero has no effect
1423  *
1424  * Writing one will clear the fpga2sdram1region3enable bit to zero
1425  *
1426  * Field Access Macros:
1427  *
1428  */
1429 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field. */
1430 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_LSB 11
1431 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field. */
1432 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_MSB 11
1433 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field. */
1434 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_WIDTH 1
1435 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field value. */
1436 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_SET_MSK 0x00000800
1437 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field value. */
1438 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
1439 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field. */
1440 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_RESET 0x0
1441 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN field value from a register. */
1442 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
1443 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN register field value suitable for setting the register. */
1444 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
1445 
1446 /*
1447  * Field : fpga2sdram2region0enable
1448  *
1449  * FPGA2SDRAM2 Region 0 Enable Clear.
1450  *
1451  * Writing zero has no effect
1452  *
1453  * Writing one will clear the fpga2sdram2region0enable bit to zero
1454  *
1455  * Field Access Macros:
1456  *
1457  */
1458 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field. */
1459 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_LSB 12
1460 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field. */
1461 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_MSB 12
1462 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field. */
1463 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_WIDTH 1
1464 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field value. */
1465 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_SET_MSK 0x00001000
1466 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field value. */
1467 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_CLR_MSK 0xffffefff
1468 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field. */
1469 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_RESET 0x0
1470 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN field value from a register. */
1471 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
1472 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN register field value suitable for setting the register. */
1473 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
1474 
1475 /*
1476  * Field : fpga2sdram2region1enable
1477  *
1478  * FPGA2SDRAM2 Region 1 Enable Clear.
1479  *
1480  * Writing zero has no effect
1481  *
1482  * Writing one will clear the fpga2sdram2region1enable bit to zero
1483  *
1484  * Field Access Macros:
1485  *
1486  */
1487 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field. */
1488 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_LSB 13
1489 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field. */
1490 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_MSB 13
1491 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field. */
1492 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_WIDTH 1
1493 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field value. */
1494 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_SET_MSK 0x00002000
1495 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field value. */
1496 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_CLR_MSK 0xffffdfff
1497 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field. */
1498 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_RESET 0x0
1499 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN field value from a register. */
1500 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
1501 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN register field value suitable for setting the register. */
1502 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
1503 
1504 /*
1505  * Field : fpga2sdram2region2enable
1506  *
1507  * FPGA2SDRAM2 Region 2 Enable Clear.
1508  *
1509  * Writing zero has no effect
1510  *
1511  * Writing one will clear the fpga2sdram2region2enable bit to zero
1512  *
1513  * Field Access Macros:
1514  *
1515  */
1516 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field. */
1517 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_LSB 14
1518 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field. */
1519 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_MSB 14
1520 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field. */
1521 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_WIDTH 1
1522 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field value. */
1523 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_SET_MSK 0x00004000
1524 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field value. */
1525 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_CLR_MSK 0xffffbfff
1526 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field. */
1527 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_RESET 0x0
1528 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN field value from a register. */
1529 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
1530 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN register field value suitable for setting the register. */
1531 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
1532 
1533 /*
1534  * Field : fpga2sdram2region3enable
1535  *
1536  * FPGA2SDRAM2 Region 3 Enable Clear.
1537  *
1538  * Writing zero has no effect
1539  *
1540  * Writing one will clear the fpga2sdram2region3enable bit to zero
1541  *
1542  * Field Access Macros:
1543  *
1544  */
1545 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field. */
1546 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_LSB 15
1547 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field. */
1548 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_MSB 15
1549 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field. */
1550 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_WIDTH 1
1551 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field value. */
1552 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_SET_MSK 0x00008000
1553 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field value. */
1554 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_CLR_MSK 0xffff7fff
1555 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field. */
1556 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_RESET 0x0
1557 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN field value from a register. */
1558 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
1559 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN register field value suitable for setting the register. */
1560 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
1561 
1562 #ifndef __ASSEMBLY__
1563 /*
1564  * WARNING: The C register and register group struct declarations are provided for
1565  * convenience and illustrative purposes. They should, however, be used with
1566  * caution as the C language standard provides no guarantees about the alignment or
1567  * atomicity of device memory accesses. The recommended practice for writing
1568  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1569  * alt_write_word() functions.
1570  *
1571  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR.
1572  */
1573 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_s
1574 {
1575  uint32_t mpuregion0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN */
1576  uint32_t mpuregion1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN */
1577  uint32_t mpuregion2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN */
1578  uint32_t mpuregion3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN */
1579  uint32_t fpga2sdram0region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN */
1580  uint32_t fpga2sdram0region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN */
1581  uint32_t fpga2sdram0region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN */
1582  uint32_t fpga2sdram0region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN */
1583  uint32_t fpga2sdram1region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN */
1584  uint32_t fpga2sdram1region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN */
1585  uint32_t fpga2sdram1region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN */
1586  uint32_t fpga2sdram1region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN */
1587  uint32_t fpga2sdram2region0enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN */
1588  uint32_t fpga2sdram2region1enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN */
1589  uint32_t fpga2sdram2region2enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN */
1590  uint32_t fpga2sdram2region3enable : 1; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN */
1591  uint32_t : 16; /* *UNDEFINED* */
1592 };
1593 
1594 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR. */
1595 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_t;
1596 #endif /* __ASSEMBLY__ */
1597 
1598 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR register. */
1599 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_RESET 0x00000000
1600 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR register from the beginning of the component. */
1601 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_OFST 0x8
1602 
1603 /*
1604  * Register : mpuregion0addr
1605  *
1606  * Base and Limit definition for MPU Region 0
1607  *
1608  * Register Layout
1609  *
1610  * Bits | Access | Reset | Description
1611  * :--------|:-------|:------|:---------------------------------------------------
1612  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE
1613  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT
1614  *
1615  */
1616 /*
1617  * Field : base
1618  *
1619  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1620  * zeros. Region start address is {base, 16'h000}
1621  *
1622  * Field Access Macros:
1623  *
1624  */
1625 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field. */
1626 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_LSB 0
1627 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field. */
1628 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_MSB 15
1629 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field. */
1630 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_WIDTH 16
1631 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field value. */
1632 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_SET_MSK 0x0000ffff
1633 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field value. */
1634 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_CLR_MSK 0xffff0000
1635 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field. */
1636 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_RESET 0x0
1637 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE field value from a register. */
1638 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1639 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE register field value suitable for setting the register. */
1640 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1641 
1642 /*
1643  * Field : limit
1644  *
1645  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1646  * ones. Region end address is {limit, 16'hFFF}
1647  *
1648  * Field Access Macros:
1649  *
1650  */
1651 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field. */
1652 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_LSB 16
1653 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field. */
1654 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_MSB 31
1655 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field. */
1656 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_WIDTH 16
1657 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field value. */
1658 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_SET_MSK 0xffff0000
1659 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field value. */
1660 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
1661 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field. */
1662 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_RESET 0x0
1663 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT field value from a register. */
1664 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1665 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT register field value suitable for setting the register. */
1666 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1667 
1668 #ifndef __ASSEMBLY__
1669 /*
1670  * WARNING: The C register and register group struct declarations are provided for
1671  * convenience and illustrative purposes. They should, however, be used with
1672  * caution as the C language standard provides no guarantees about the alignment or
1673  * atomicity of device memory accesses. The recommended practice for writing
1674  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1675  * alt_write_word() functions.
1676  *
1677  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR.
1678  */
1679 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_s
1680 {
1681  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE */
1682  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT */
1683 };
1684 
1685 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR. */
1686 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_t;
1687 #endif /* __ASSEMBLY__ */
1688 
1689 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR register. */
1690 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_RESET 0x00000000
1691 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR register from the beginning of the component. */
1692 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_OFST 0x10
1693 
1694 /*
1695  * Register : mpuregion1addr
1696  *
1697  * Base and Limit definition for MPU Region 1
1698  *
1699  * Register Layout
1700  *
1701  * Bits | Access | Reset | Description
1702  * :--------|:-------|:------|:---------------------------------------------------
1703  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE
1704  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT
1705  *
1706  */
1707 /*
1708  * Field : base
1709  *
1710  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1711  * zeros. Region start address is {base, 16'h000}
1712  *
1713  * Field Access Macros:
1714  *
1715  */
1716 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field. */
1717 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_LSB 0
1718 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field. */
1719 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_MSB 15
1720 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field. */
1721 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_WIDTH 16
1722 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field value. */
1723 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_SET_MSK 0x0000ffff
1724 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field value. */
1725 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_CLR_MSK 0xffff0000
1726 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field. */
1727 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_RESET 0x0
1728 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE field value from a register. */
1729 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1730 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE register field value suitable for setting the register. */
1731 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1732 
1733 /*
1734  * Field : limit
1735  *
1736  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1737  * ones. Region end address is {limit, 16'hFFF}
1738  *
1739  * Field Access Macros:
1740  *
1741  */
1742 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field. */
1743 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_LSB 16
1744 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field. */
1745 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_MSB 31
1746 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field. */
1747 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_WIDTH 16
1748 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field value. */
1749 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_SET_MSK 0xffff0000
1750 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field value. */
1751 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1752 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field. */
1753 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_RESET 0x0
1754 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT field value from a register. */
1755 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1756 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT register field value suitable for setting the register. */
1757 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1758 
1759 #ifndef __ASSEMBLY__
1760 /*
1761  * WARNING: The C register and register group struct declarations are provided for
1762  * convenience and illustrative purposes. They should, however, be used with
1763  * caution as the C language standard provides no guarantees about the alignment or
1764  * atomicity of device memory accesses. The recommended practice for writing
1765  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1766  * alt_write_word() functions.
1767  *
1768  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR.
1769  */
1770 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_s
1771 {
1772  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE */
1773  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT */
1774 };
1775 
1776 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR. */
1777 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_t;
1778 #endif /* __ASSEMBLY__ */
1779 
1780 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR register. */
1781 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_RESET 0x00000000
1782 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR register from the beginning of the component. */
1783 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_OFST 0x14
1784 
1785 /*
1786  * Register : mpuregion2addr
1787  *
1788  * Base and Limit definition for MPU Region 2
1789  *
1790  * Register Layout
1791  *
1792  * Bits | Access | Reset | Description
1793  * :--------|:-------|:------|:---------------------------------------------------
1794  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE
1795  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT
1796  *
1797  */
1798 /*
1799  * Field : base
1800  *
1801  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1802  * zeros. Region start address is {base, 16'h000}
1803  *
1804  * Field Access Macros:
1805  *
1806  */
1807 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field. */
1808 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_LSB 0
1809 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field. */
1810 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_MSB 15
1811 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field. */
1812 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_WIDTH 16
1813 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field value. */
1814 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_SET_MSK 0x0000ffff
1815 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field value. */
1816 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_CLR_MSK 0xffff0000
1817 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field. */
1818 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_RESET 0x0
1819 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE field value from a register. */
1820 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1821 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE register field value suitable for setting the register. */
1822 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1823 
1824 /*
1825  * Field : limit
1826  *
1827  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1828  * ones. Region end address is {limit, 16'hFFF}
1829  *
1830  * Field Access Macros:
1831  *
1832  */
1833 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field. */
1834 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_LSB 16
1835 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field. */
1836 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_MSB 31
1837 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field. */
1838 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_WIDTH 16
1839 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field value. */
1840 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_SET_MSK 0xffff0000
1841 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field value. */
1842 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1843 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field. */
1844 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_RESET 0x0
1845 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT field value from a register. */
1846 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1847 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT register field value suitable for setting the register. */
1848 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1849 
1850 #ifndef __ASSEMBLY__
1851 /*
1852  * WARNING: The C register and register group struct declarations are provided for
1853  * convenience and illustrative purposes. They should, however, be used with
1854  * caution as the C language standard provides no guarantees about the alignment or
1855  * atomicity of device memory accesses. The recommended practice for writing
1856  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1857  * alt_write_word() functions.
1858  *
1859  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR.
1860  */
1861 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_s
1862 {
1863  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE */
1864  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT */
1865 };
1866 
1867 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR. */
1868 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_t;
1869 #endif /* __ASSEMBLY__ */
1870 
1871 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR register. */
1872 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_RESET 0x00000000
1873 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR register from the beginning of the component. */
1874 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_OFST 0x18
1875 
1876 /*
1877  * Register : mpuregion3addr
1878  *
1879  * Base and Limit definition for MPU Region 3
1880  *
1881  * Register Layout
1882  *
1883  * Bits | Access | Reset | Description
1884  * :--------|:-------|:------|:---------------------------------------------------
1885  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE
1886  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT
1887  *
1888  */
1889 /*
1890  * Field : base
1891  *
1892  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1893  * zeros. Region start address is {base, 16'h000}
1894  *
1895  * Field Access Macros:
1896  *
1897  */
1898 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field. */
1899 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_LSB 0
1900 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field. */
1901 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_MSB 15
1902 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field. */
1903 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_WIDTH 16
1904 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field value. */
1905 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_SET_MSK 0x0000ffff
1906 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field value. */
1907 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_CLR_MSK 0xffff0000
1908 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field. */
1909 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_RESET 0x0
1910 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE field value from a register. */
1911 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1912 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE register field value suitable for setting the register. */
1913 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1914 
1915 /*
1916  * Field : limit
1917  *
1918  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
1919  * ones. Region end address is {limit, 16'hFFF}
1920  *
1921  * Field Access Macros:
1922  *
1923  */
1924 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field. */
1925 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_LSB 16
1926 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field. */
1927 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_MSB 31
1928 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field. */
1929 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_WIDTH 16
1930 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field value. */
1931 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_SET_MSK 0xffff0000
1932 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field value. */
1933 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1934 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field. */
1935 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_RESET 0x0
1936 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT field value from a register. */
1937 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1938 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT register field value suitable for setting the register. */
1939 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1940 
1941 #ifndef __ASSEMBLY__
1942 /*
1943  * WARNING: The C register and register group struct declarations are provided for
1944  * convenience and illustrative purposes. They should, however, be used with
1945  * caution as the C language standard provides no guarantees about the alignment or
1946  * atomicity of device memory accesses. The recommended practice for writing
1947  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1948  * alt_write_word() functions.
1949  *
1950  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR.
1951  */
1952 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_s
1953 {
1954  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE */
1955  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT */
1956 };
1957 
1958 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR. */
1959 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_t;
1960 #endif /* __ASSEMBLY__ */
1961 
1962 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR register. */
1963 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_RESET 0x00000000
1964 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR register from the beginning of the component. */
1965 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_OFST 0x1c
1966 
1967 /*
1968  * Register : fpga2sdram0region0addr
1969  *
1970  * Base and Limit definition for FPGA2SDRAM0 Region 0
1971  *
1972  * Register Layout
1973  *
1974  * Bits | Access | Reset | Description
1975  * :--------|:-------|:------|:------------------------------------------------------
1976  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE
1977  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT
1978  *
1979  */
1980 /*
1981  * Field : base
1982  *
1983  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
1984  * zeros. Region start address is {base, 16'h000}
1985  *
1986  * Field Access Macros:
1987  *
1988  */
1989 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field. */
1990 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_LSB 0
1991 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field. */
1992 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_MSB 15
1993 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field. */
1994 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_WIDTH 16
1995 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field value. */
1996 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_SET_MSK 0x0000ffff
1997 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field value. */
1998 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_CLR_MSK 0xffff0000
1999 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field. */
2000 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_RESET 0x0
2001 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE field value from a register. */
2002 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2003 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE register field value suitable for setting the register. */
2004 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2005 
2006 /*
2007  * Field : limit
2008  *
2009  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2010  * ones. Region end address is {limit, 16'hFFF}
2011  *
2012  * Field Access Macros:
2013  *
2014  */
2015 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field. */
2016 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_LSB 16
2017 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field. */
2018 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_MSB 31
2019 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field. */
2020 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_WIDTH 16
2021 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field value. */
2022 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_SET_MSK 0xffff0000
2023 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field value. */
2024 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2025 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field. */
2026 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_RESET 0x0
2027 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT field value from a register. */
2028 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2029 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT register field value suitable for setting the register. */
2030 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2031 
2032 #ifndef __ASSEMBLY__
2033 /*
2034  * WARNING: The C register and register group struct declarations are provided for
2035  * convenience and illustrative purposes. They should, however, be used with
2036  * caution as the C language standard provides no guarantees about the alignment or
2037  * atomicity of device memory accesses. The recommended practice for writing
2038  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2039  * alt_write_word() functions.
2040  *
2041  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR.
2042  */
2043 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_s
2044 {
2045  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE */
2046  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT */
2047 };
2048 
2049 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR. */
2050 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_t;
2051 #endif /* __ASSEMBLY__ */
2052 
2053 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR register. */
2054 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_RESET 0x00000000
2055 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR register from the beginning of the component. */
2056 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_OFST 0x20
2057 
2058 /*
2059  * Register : fpga2sdram0region1addr
2060  *
2061  * Base and Limit definition for FPGA2SDRAM0 Region 1
2062  *
2063  * Register Layout
2064  *
2065  * Bits | Access | Reset | Description
2066  * :--------|:-------|:------|:------------------------------------------------------
2067  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE
2068  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT
2069  *
2070  */
2071 /*
2072  * Field : base
2073  *
2074  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2075  * zeros. Region start address is {base, 16'h000}
2076  *
2077  * Field Access Macros:
2078  *
2079  */
2080 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field. */
2081 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_LSB 0
2082 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field. */
2083 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_MSB 15
2084 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field. */
2085 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_WIDTH 16
2086 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field value. */
2087 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_SET_MSK 0x0000ffff
2088 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field value. */
2089 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_CLR_MSK 0xffff0000
2090 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field. */
2091 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_RESET 0x0
2092 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE field value from a register. */
2093 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2094 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE register field value suitable for setting the register. */
2095 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2096 
2097 /*
2098  * Field : limit
2099  *
2100  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2101  * ones. Region end address is {limit, 16'hFFF}
2102  *
2103  * Field Access Macros:
2104  *
2105  */
2106 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field. */
2107 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_LSB 16
2108 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field. */
2109 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_MSB 31
2110 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field. */
2111 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_WIDTH 16
2112 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field value. */
2113 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_SET_MSK 0xffff0000
2114 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field value. */
2115 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2116 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field. */
2117 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_RESET 0x0
2118 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT field value from a register. */
2119 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2120 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT register field value suitable for setting the register. */
2121 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2122 
2123 #ifndef __ASSEMBLY__
2124 /*
2125  * WARNING: The C register and register group struct declarations are provided for
2126  * convenience and illustrative purposes. They should, however, be used with
2127  * caution as the C language standard provides no guarantees about the alignment or
2128  * atomicity of device memory accesses. The recommended practice for writing
2129  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2130  * alt_write_word() functions.
2131  *
2132  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR.
2133  */
2134 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_s
2135 {
2136  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE */
2137  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT */
2138 };
2139 
2140 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR. */
2141 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_t;
2142 #endif /* __ASSEMBLY__ */
2143 
2144 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR register. */
2145 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_RESET 0x00000000
2146 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR register from the beginning of the component. */
2147 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_OFST 0x24
2148 
2149 /*
2150  * Register : fpga2sdram0region2addr
2151  *
2152  * Base and Limit definition for FPGA2SDRAM0 Region 2
2153  *
2154  * Register Layout
2155  *
2156  * Bits | Access | Reset | Description
2157  * :--------|:-------|:------|:------------------------------------------------------
2158  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE
2159  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT
2160  *
2161  */
2162 /*
2163  * Field : base
2164  *
2165  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2166  * zeros. Region start address is {base, 16'h000}
2167  *
2168  * Field Access Macros:
2169  *
2170  */
2171 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field. */
2172 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_LSB 0
2173 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field. */
2174 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_MSB 15
2175 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field. */
2176 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_WIDTH 16
2177 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field value. */
2178 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_SET_MSK 0x0000ffff
2179 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field value. */
2180 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_CLR_MSK 0xffff0000
2181 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field. */
2182 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_RESET 0x0
2183 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE field value from a register. */
2184 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2185 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE register field value suitable for setting the register. */
2186 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2187 
2188 /*
2189  * Field : limit
2190  *
2191  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2192  * ones. Region end address is {limit, 16'hFFF}
2193  *
2194  * Field Access Macros:
2195  *
2196  */
2197 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field. */
2198 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_LSB 16
2199 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field. */
2200 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_MSB 31
2201 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field. */
2202 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_WIDTH 16
2203 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field value. */
2204 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_SET_MSK 0xffff0000
2205 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field value. */
2206 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2207 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field. */
2208 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_RESET 0x0
2209 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT field value from a register. */
2210 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2211 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT register field value suitable for setting the register. */
2212 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2213 
2214 #ifndef __ASSEMBLY__
2215 /*
2216  * WARNING: The C register and register group struct declarations are provided for
2217  * convenience and illustrative purposes. They should, however, be used with
2218  * caution as the C language standard provides no guarantees about the alignment or
2219  * atomicity of device memory accesses. The recommended practice for writing
2220  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2221  * alt_write_word() functions.
2222  *
2223  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR.
2224  */
2225 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_s
2226 {
2227  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE */
2228  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT */
2229 };
2230 
2231 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR. */
2232 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_t;
2233 #endif /* __ASSEMBLY__ */
2234 
2235 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR register. */
2236 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_RESET 0x00000000
2237 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR register from the beginning of the component. */
2238 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_OFST 0x28
2239 
2240 /*
2241  * Register : fpga2sdram0region3addr
2242  *
2243  * Base and Limit definition for FPGA2SDRAM0 Region 3
2244  *
2245  * Register Layout
2246  *
2247  * Bits | Access | Reset | Description
2248  * :--------|:-------|:------|:------------------------------------------------------
2249  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE
2250  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT
2251  *
2252  */
2253 /*
2254  * Field : base
2255  *
2256  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2257  * zeros. Region start address is {base, 16'h000}
2258  *
2259  * Field Access Macros:
2260  *
2261  */
2262 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field. */
2263 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_LSB 0
2264 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field. */
2265 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_MSB 15
2266 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field. */
2267 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_WIDTH 16
2268 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field value. */
2269 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_SET_MSK 0x0000ffff
2270 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field value. */
2271 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_CLR_MSK 0xffff0000
2272 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field. */
2273 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_RESET 0x0
2274 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE field value from a register. */
2275 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2276 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE register field value suitable for setting the register. */
2277 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2278 
2279 /*
2280  * Field : limit
2281  *
2282  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2283  * ones. Region end address is {limit, 16'hFFF}
2284  *
2285  * Field Access Macros:
2286  *
2287  */
2288 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field. */
2289 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_LSB 16
2290 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field. */
2291 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_MSB 31
2292 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field. */
2293 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_WIDTH 16
2294 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field value. */
2295 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_SET_MSK 0xffff0000
2296 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field value. */
2297 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
2298 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field. */
2299 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_RESET 0x0
2300 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT field value from a register. */
2301 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2302 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT register field value suitable for setting the register. */
2303 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2304 
2305 #ifndef __ASSEMBLY__
2306 /*
2307  * WARNING: The C register and register group struct declarations are provided for
2308  * convenience and illustrative purposes. They should, however, be used with
2309  * caution as the C language standard provides no guarantees about the alignment or
2310  * atomicity of device memory accesses. The recommended practice for writing
2311  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2312  * alt_write_word() functions.
2313  *
2314  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR.
2315  */
2316 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_s
2317 {
2318  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE */
2319  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT */
2320 };
2321 
2322 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR. */
2323 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_t;
2324 #endif /* __ASSEMBLY__ */
2325 
2326 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR register. */
2327 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_RESET 0x00000000
2328 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR register from the beginning of the component. */
2329 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_OFST 0x2c
2330 
2331 /*
2332  * Register : fpga2sdram1region0addr
2333  *
2334  * Base and Limit definition for FPGA2SDRAM1 Region 0
2335  *
2336  * Register Layout
2337  *
2338  * Bits | Access | Reset | Description
2339  * :--------|:-------|:------|:------------------------------------------------------
2340  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE
2341  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT
2342  *
2343  */
2344 /*
2345  * Field : base
2346  *
2347  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2348  * zeros. Region start address is {base, 16'h000}
2349  *
2350  * Field Access Macros:
2351  *
2352  */
2353 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field. */
2354 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_LSB 0
2355 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field. */
2356 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_MSB 15
2357 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field. */
2358 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_WIDTH 16
2359 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field value. */
2360 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_SET_MSK 0x0000ffff
2361 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field value. */
2362 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_CLR_MSK 0xffff0000
2363 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field. */
2364 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_RESET 0x0
2365 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE field value from a register. */
2366 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2367 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE register field value suitable for setting the register. */
2368 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2369 
2370 /*
2371  * Field : limit
2372  *
2373  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2374  * ones. Region end address is {limit, 16'hFFF}
2375  *
2376  * Field Access Macros:
2377  *
2378  */
2379 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field. */
2380 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_LSB 16
2381 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field. */
2382 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_MSB 31
2383 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field. */
2384 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_WIDTH 16
2385 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field value. */
2386 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_SET_MSK 0xffff0000
2387 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field value. */
2388 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2389 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field. */
2390 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_RESET 0x0
2391 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT field value from a register. */
2392 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2393 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT register field value suitable for setting the register. */
2394 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2395 
2396 #ifndef __ASSEMBLY__
2397 /*
2398  * WARNING: The C register and register group struct declarations are provided for
2399  * convenience and illustrative purposes. They should, however, be used with
2400  * caution as the C language standard provides no guarantees about the alignment or
2401  * atomicity of device memory accesses. The recommended practice for writing
2402  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2403  * alt_write_word() functions.
2404  *
2405  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR.
2406  */
2407 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_s
2408 {
2409  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE */
2410  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT */
2411 };
2412 
2413 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR. */
2414 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_t;
2415 #endif /* __ASSEMBLY__ */
2416 
2417 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR register. */
2418 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_RESET 0x00000000
2419 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR register from the beginning of the component. */
2420 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_OFST 0x30
2421 
2422 /*
2423  * Register : fpga2sdram1region1addr
2424  *
2425  * Base and Limit definition for FPGA2SDRAM1 Region 1
2426  *
2427  * Register Layout
2428  *
2429  * Bits | Access | Reset | Description
2430  * :--------|:-------|:------|:------------------------------------------------------
2431  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE
2432  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT
2433  *
2434  */
2435 /*
2436  * Field : base
2437  *
2438  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2439  * zeros. Region start address is {base, 16'h000}
2440  *
2441  * Field Access Macros:
2442  *
2443  */
2444 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field. */
2445 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_LSB 0
2446 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field. */
2447 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_MSB 15
2448 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field. */
2449 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_WIDTH 16
2450 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field value. */
2451 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_SET_MSK 0x0000ffff
2452 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field value. */
2453 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_CLR_MSK 0xffff0000
2454 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field. */
2455 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_RESET 0x0
2456 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE field value from a register. */
2457 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2458 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE register field value suitable for setting the register. */
2459 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2460 
2461 /*
2462  * Field : limit
2463  *
2464  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2465  * ones. Region end address is {limit, 16'hFFF}
2466  *
2467  * Field Access Macros:
2468  *
2469  */
2470 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field. */
2471 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_LSB 16
2472 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field. */
2473 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_MSB 31
2474 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field. */
2475 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_WIDTH 16
2476 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field value. */
2477 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_SET_MSK 0xffff0000
2478 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field value. */
2479 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2480 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field. */
2481 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_RESET 0x0
2482 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT field value from a register. */
2483 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2484 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT register field value suitable for setting the register. */
2485 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2486 
2487 #ifndef __ASSEMBLY__
2488 /*
2489  * WARNING: The C register and register group struct declarations are provided for
2490  * convenience and illustrative purposes. They should, however, be used with
2491  * caution as the C language standard provides no guarantees about the alignment or
2492  * atomicity of device memory accesses. The recommended practice for writing
2493  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2494  * alt_write_word() functions.
2495  *
2496  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR.
2497  */
2498 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_s
2499 {
2500  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE */
2501  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT */
2502 };
2503 
2504 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR. */
2505 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_t;
2506 #endif /* __ASSEMBLY__ */
2507 
2508 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR register. */
2509 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_RESET 0x00000000
2510 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR register from the beginning of the component. */
2511 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_OFST 0x34
2512 
2513 /*
2514  * Register : fpga2sdram1region2addr
2515  *
2516  * Base and Limit definition for FPGA2SDRAM1 Region 2
2517  *
2518  * Register Layout
2519  *
2520  * Bits | Access | Reset | Description
2521  * :--------|:-------|:------|:------------------------------------------------------
2522  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE
2523  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT
2524  *
2525  */
2526 /*
2527  * Field : base
2528  *
2529  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2530  * zeros. Region start address is {base, 16'h000}
2531  *
2532  * Field Access Macros:
2533  *
2534  */
2535 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field. */
2536 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_LSB 0
2537 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field. */
2538 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_MSB 15
2539 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field. */
2540 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_WIDTH 16
2541 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field value. */
2542 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_SET_MSK 0x0000ffff
2543 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field value. */
2544 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_CLR_MSK 0xffff0000
2545 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field. */
2546 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_RESET 0x0
2547 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE field value from a register. */
2548 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2549 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE register field value suitable for setting the register. */
2550 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2551 
2552 /*
2553  * Field : limit
2554  *
2555  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2556  * ones. Region end address is {limit, 16'hFFF}
2557  *
2558  * Field Access Macros:
2559  *
2560  */
2561 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field. */
2562 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_LSB 16
2563 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field. */
2564 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_MSB 31
2565 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field. */
2566 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_WIDTH 16
2567 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field value. */
2568 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_SET_MSK 0xffff0000
2569 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field value. */
2570 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2571 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field. */
2572 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_RESET 0x0
2573 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT field value from a register. */
2574 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2575 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT register field value suitable for setting the register. */
2576 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2577 
2578 #ifndef __ASSEMBLY__
2579 /*
2580  * WARNING: The C register and register group struct declarations are provided for
2581  * convenience and illustrative purposes. They should, however, be used with
2582  * caution as the C language standard provides no guarantees about the alignment or
2583  * atomicity of device memory accesses. The recommended practice for writing
2584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2585  * alt_write_word() functions.
2586  *
2587  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR.
2588  */
2589 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_s
2590 {
2591  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE */
2592  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT */
2593 };
2594 
2595 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR. */
2596 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_t;
2597 #endif /* __ASSEMBLY__ */
2598 
2599 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR register. */
2600 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_RESET 0x00000000
2601 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR register from the beginning of the component. */
2602 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_OFST 0x38
2603 
2604 /*
2605  * Register : fpga2sdram1region3addr
2606  *
2607  * Base and Limit definition for FPGA2SDRAM1 Region 3
2608  *
2609  * Register Layout
2610  *
2611  * Bits | Access | Reset | Description
2612  * :--------|:-------|:------|:------------------------------------------------------
2613  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE
2614  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT
2615  *
2616  */
2617 /*
2618  * Field : base
2619  *
2620  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2621  * zeros. Region start address is {base, 16'h000}
2622  *
2623  * Field Access Macros:
2624  *
2625  */
2626 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field. */
2627 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_LSB 0
2628 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field. */
2629 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_MSB 15
2630 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field. */
2631 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_WIDTH 16
2632 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field value. */
2633 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_SET_MSK 0x0000ffff
2634 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field value. */
2635 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_CLR_MSK 0xffff0000
2636 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field. */
2637 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_RESET 0x0
2638 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE field value from a register. */
2639 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2640 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE register field value suitable for setting the register. */
2641 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2642 
2643 /*
2644  * Field : limit
2645  *
2646  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2647  * ones. Region end address is {limit, 16'hFFF}
2648  *
2649  * Field Access Macros:
2650  *
2651  */
2652 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field. */
2653 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_LSB 16
2654 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field. */
2655 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_MSB 31
2656 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field. */
2657 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_WIDTH 16
2658 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field value. */
2659 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_SET_MSK 0xffff0000
2660 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field value. */
2661 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
2662 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field. */
2663 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_RESET 0x0
2664 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT field value from a register. */
2665 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2666 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT register field value suitable for setting the register. */
2667 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2668 
2669 #ifndef __ASSEMBLY__
2670 /*
2671  * WARNING: The C register and register group struct declarations are provided for
2672  * convenience and illustrative purposes. They should, however, be used with
2673  * caution as the C language standard provides no guarantees about the alignment or
2674  * atomicity of device memory accesses. The recommended practice for writing
2675  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2676  * alt_write_word() functions.
2677  *
2678  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR.
2679  */
2680 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_s
2681 {
2682  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE */
2683  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT */
2684 };
2685 
2686 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR. */
2687 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_t;
2688 #endif /* __ASSEMBLY__ */
2689 
2690 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR register. */
2691 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_RESET 0x00000000
2692 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR register from the beginning of the component. */
2693 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_OFST 0x3c
2694 
2695 /*
2696  * Register : fpga2sdram2region0addr
2697  *
2698  * Base and Limit definition for FPGA2SDRAM2 Region 0
2699  *
2700  * Register Layout
2701  *
2702  * Bits | Access | Reset | Description
2703  * :--------|:-------|:------|:------------------------------------------------------
2704  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE
2705  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT
2706  *
2707  */
2708 /*
2709  * Field : base
2710  *
2711  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2712  * zeros. Region start address is {base, 16'h000}
2713  *
2714  * Field Access Macros:
2715  *
2716  */
2717 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field. */
2718 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_LSB 0
2719 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field. */
2720 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_MSB 15
2721 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field. */
2722 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_WIDTH 16
2723 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field value. */
2724 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_SET_MSK 0x0000ffff
2725 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field value. */
2726 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_CLR_MSK 0xffff0000
2727 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field. */
2728 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_RESET 0x0
2729 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE field value from a register. */
2730 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2731 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE register field value suitable for setting the register. */
2732 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2733 
2734 /*
2735  * Field : limit
2736  *
2737  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2738  * ones. Region end address is {limit, 16'hFFF}
2739  *
2740  * Field Access Macros:
2741  *
2742  */
2743 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field. */
2744 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_LSB 16
2745 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field. */
2746 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_MSB 31
2747 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field. */
2748 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_WIDTH 16
2749 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field value. */
2750 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_SET_MSK 0xffff0000
2751 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field value. */
2752 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2753 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field. */
2754 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_RESET 0x0
2755 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT field value from a register. */
2756 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2757 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT register field value suitable for setting the register. */
2758 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2759 
2760 #ifndef __ASSEMBLY__
2761 /*
2762  * WARNING: The C register and register group struct declarations are provided for
2763  * convenience and illustrative purposes. They should, however, be used with
2764  * caution as the C language standard provides no guarantees about the alignment or
2765  * atomicity of device memory accesses. The recommended practice for writing
2766  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2767  * alt_write_word() functions.
2768  *
2769  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR.
2770  */
2771 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_s
2772 {
2773  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE */
2774  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT */
2775 };
2776 
2777 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR. */
2778 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_t;
2779 #endif /* __ASSEMBLY__ */
2780 
2781 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR register. */
2782 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_RESET 0x00000000
2783 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR register from the beginning of the component. */
2784 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_OFST 0x40
2785 
2786 /*
2787  * Register : fpga2sdram2region1addr
2788  *
2789  * Base and Limit definition for FPGA2SDRAM2 Region 1
2790  *
2791  * Register Layout
2792  *
2793  * Bits | Access | Reset | Description
2794  * :--------|:-------|:------|:------------------------------------------------------
2795  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE
2796  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT
2797  *
2798  */
2799 /*
2800  * Field : base
2801  *
2802  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2803  * zeros. Region start address is {base, 16'h000}
2804  *
2805  * Field Access Macros:
2806  *
2807  */
2808 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field. */
2809 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_LSB 0
2810 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field. */
2811 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_MSB 15
2812 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field. */
2813 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_WIDTH 16
2814 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field value. */
2815 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_SET_MSK 0x0000ffff
2816 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field value. */
2817 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_CLR_MSK 0xffff0000
2818 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field. */
2819 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_RESET 0x0
2820 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE field value from a register. */
2821 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2822 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE register field value suitable for setting the register. */
2823 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2824 
2825 /*
2826  * Field : limit
2827  *
2828  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2829  * ones. Region end address is {limit, 16'hFFF}
2830  *
2831  * Field Access Macros:
2832  *
2833  */
2834 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field. */
2835 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_LSB 16
2836 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field. */
2837 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_MSB 31
2838 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field. */
2839 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_WIDTH 16
2840 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field value. */
2841 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_SET_MSK 0xffff0000
2842 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field value. */
2843 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2844 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field. */
2845 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_RESET 0x0
2846 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT field value from a register. */
2847 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2848 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT register field value suitable for setting the register. */
2849 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2850 
2851 #ifndef __ASSEMBLY__
2852 /*
2853  * WARNING: The C register and register group struct declarations are provided for
2854  * convenience and illustrative purposes. They should, however, be used with
2855  * caution as the C language standard provides no guarantees about the alignment or
2856  * atomicity of device memory accesses. The recommended practice for writing
2857  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2858  * alt_write_word() functions.
2859  *
2860  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR.
2861  */
2862 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_s
2863 {
2864  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE */
2865  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT */
2866 };
2867 
2868 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR. */
2869 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_t;
2870 #endif /* __ASSEMBLY__ */
2871 
2872 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR register. */
2873 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_RESET 0x00000000
2874 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR register from the beginning of the component. */
2875 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_OFST 0x44
2876 
2877 /*
2878  * Register : fpga2sdram2region2addr
2879  *
2880  * Base and Limit definition for FPGA2SDRAM2 Region 2
2881  *
2882  * Register Layout
2883  *
2884  * Bits | Access | Reset | Description
2885  * :--------|:-------|:------|:------------------------------------------------------
2886  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE
2887  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT
2888  *
2889  */
2890 /*
2891  * Field : base
2892  *
2893  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2894  * zeros. Region start address is {base, 16'h000}
2895  *
2896  * Field Access Macros:
2897  *
2898  */
2899 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field. */
2900 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_LSB 0
2901 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field. */
2902 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_MSB 15
2903 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field. */
2904 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_WIDTH 16
2905 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field value. */
2906 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_SET_MSK 0x0000ffff
2907 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field value. */
2908 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_CLR_MSK 0xffff0000
2909 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field. */
2910 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_RESET 0x0
2911 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE field value from a register. */
2912 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2913 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE register field value suitable for setting the register. */
2914 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2915 
2916 /*
2917  * Field : limit
2918  *
2919  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
2920  * ones. Region end address is {limit, 16'hFFF}
2921  *
2922  * Field Access Macros:
2923  *
2924  */
2925 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field. */
2926 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_LSB 16
2927 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field. */
2928 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_MSB 31
2929 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field. */
2930 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_WIDTH 16
2931 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field value. */
2932 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_SET_MSK 0xffff0000
2933 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field value. */
2934 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2935 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field. */
2936 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_RESET 0x0
2937 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT field value from a register. */
2938 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2939 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT register field value suitable for setting the register. */
2940 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2941 
2942 #ifndef __ASSEMBLY__
2943 /*
2944  * WARNING: The C register and register group struct declarations are provided for
2945  * convenience and illustrative purposes. They should, however, be used with
2946  * caution as the C language standard provides no guarantees about the alignment or
2947  * atomicity of device memory accesses. The recommended practice for writing
2948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2949  * alt_write_word() functions.
2950  *
2951  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR.
2952  */
2953 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_s
2954 {
2955  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE */
2956  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT */
2957 };
2958 
2959 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR. */
2960 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_t;
2961 #endif /* __ASSEMBLY__ */
2962 
2963 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR register. */
2964 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_RESET 0x00000000
2965 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR register from the beginning of the component. */
2966 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_OFST 0x48
2967 
2968 /*
2969  * Register : fpga2sdram2region3addr
2970  *
2971  * Base and Limit definition for FPGA2SDRAM2 Region 3
2972  *
2973  * Register Layout
2974  *
2975  * Bits | Access | Reset | Description
2976  * :--------|:-------|:------|:------------------------------------------------------
2977  * [15:0] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE
2978  * [31:16] | RW | 0x0 | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT
2979  *
2980  */
2981 /*
2982  * Field : base
2983  *
2984  * Base defines the 16 bit MSB of the address field. Remaining LSB field is all
2985  * zeros. Region start address is {base, 16'h000}
2986  *
2987  * Field Access Macros:
2988  *
2989  */
2990 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field. */
2991 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_LSB 0
2992 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field. */
2993 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_MSB 15
2994 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field. */
2995 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_WIDTH 16
2996 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field value. */
2997 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_SET_MSK 0x0000ffff
2998 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field value. */
2999 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_CLR_MSK 0xffff0000
3000 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field. */
3001 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_RESET 0x0
3002 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE field value from a register. */
3003 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
3004 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE register field value suitable for setting the register. */
3005 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
3006 
3007 /*
3008  * Field : limit
3009  *
3010  * Limit defines the 16 bit MSB of the address field. Remaining LSB field is all
3011  * ones. Region end address is {limit, 16'hFFF}
3012  *
3013  * Field Access Macros:
3014  *
3015  */
3016 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field. */
3017 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_LSB 16
3018 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field. */
3019 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_MSB 31
3020 /* The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field. */
3021 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_WIDTH 16
3022 /* The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field value. */
3023 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_SET_MSK 0xffff0000
3024 /* The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field value. */
3025 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
3026 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field. */
3027 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_RESET 0x0
3028 /* Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT field value from a register. */
3029 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
3030 /* Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT register field value suitable for setting the register. */
3031 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
3032 
3033 #ifndef __ASSEMBLY__
3034 /*
3035  * WARNING: The C register and register group struct declarations are provided for
3036  * convenience and illustrative purposes. They should, however, be used with
3037  * caution as the C language standard provides no guarantees about the alignment or
3038  * atomicity of device memory accesses. The recommended practice for writing
3039  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3040  * alt_write_word() functions.
3041  *
3042  * The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR.
3043  */
3044 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_s
3045 {
3046  uint32_t base : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE */
3047  uint32_t limit : 16; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT */
3048 };
3049 
3050 /* The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR. */
3051 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_t;
3052 #endif /* __ASSEMBLY__ */
3053 
3054 /* The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR register. */
3055 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_RESET 0x00000000
3056 /* The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR register from the beginning of the component. */
3057 #define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_OFST 0x4c
3058 
3059 #ifndef __ASSEMBLY__
3060 /*
3061  * WARNING: The C register and register group struct declarations are provided for
3062  * convenience and illustrative purposes. They should, however, be used with
3063  * caution as the C language standard provides no guarantees about the alignment or
3064  * atomicity of device memory accesses. The recommended practice for writing
3065  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3066  * alt_write_word() functions.
3067  *
3068  * The struct declaration for register group ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR.
3069  */
3070 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_s
3071 {
3072  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_t enable; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN */
3073  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_t enable_set; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET */
3074  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_t enable_clear; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR */
3075  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3076  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_t mpuregion0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR */
3077  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_t mpuregion1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR */
3078  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_t mpuregion2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR */
3079  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_t mpuregion3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR */
3080  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_t fpga2sdram0region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR */
3081  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_t fpga2sdram0region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR */
3082  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_t fpga2sdram0region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR */
3083  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_t fpga2sdram0region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR */
3084  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_t fpga2sdram1region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR */
3085  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_t fpga2sdram1region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR */
3086  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_t fpga2sdram1region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR */
3087  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_t fpga2sdram1region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR */
3088  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_t fpga2sdram2region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR */
3089  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_t fpga2sdram2region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR */
3090  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_t fpga2sdram2region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR */
3091  ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_t fpga2sdram2region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR */
3092  volatile uint32_t _pad_0x50_0x100[44]; /* *UNDEFINED* */
3093 };
3094 
3095 /* The typedef declaration for register group ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR. */
3096 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_t;
3097 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR. */
3098 struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_s
3099 {
3100  volatile uint32_t enable; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN */
3101  volatile uint32_t enable_set; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET */
3102  volatile uint32_t enable_clear; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR */
3103  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3104  volatile uint32_t mpuregion0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR */
3105  volatile uint32_t mpuregion1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR */
3106  volatile uint32_t mpuregion2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR */
3107  volatile uint32_t mpuregion3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR */
3108  volatile uint32_t fpga2sdram0region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR */
3109  volatile uint32_t fpga2sdram0region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR */
3110  volatile uint32_t fpga2sdram0region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR */
3111  volatile uint32_t fpga2sdram0region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR */
3112  volatile uint32_t fpga2sdram1region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR */
3113  volatile uint32_t fpga2sdram1region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR */
3114  volatile uint32_t fpga2sdram1region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR */
3115  volatile uint32_t fpga2sdram1region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR */
3116  volatile uint32_t fpga2sdram2region0addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR */
3117  volatile uint32_t fpga2sdram2region1addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR */
3118  volatile uint32_t fpga2sdram2region2addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR */
3119  volatile uint32_t fpga2sdram2region3addr; /* ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR */
3120  uint32_t _pad_0x50_0x100[44]; /* *UNDEFINED* */
3121 };
3122 
3123 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR. */
3124 typedef volatile struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_s ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_t;
3125 #endif /* __ASSEMBLY__ */
3126 
3127 
3128 #ifdef __cplusplus
3129 }
3130 #endif /* __cplusplus */
3131 #endif /* __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__ */
3132