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alt_tmr.h
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32 
33 /* Altera - ALT_TMR */
34 
35 #ifndef __ALT_SOCAL_TMR_H__
36 #define __ALT_SOCAL_TMR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : TMR
50  * DW_apb_timers address block
51  *
52  */
53 /*
54  * Register : Timer1 Load Count Register - TIMER1LOADCOUNT
55  *
56  * Name: Timer1 Load Count Register
57  *
58  * Size: 8-32 bits
59  *
60  * Address Offset: 0x00
61  *
62  * Read/Write Access: Read/Write
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :-------|:-------|:------|:----------------------------------------
68  * [31:0] | RW | 0x0 | ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT
69  *
70  */
71 /*
72  * Field : TIMER1LOADCOUNT
73  *
74  * Value to be loaded into Timer1. This is the value from which counting
75  *
76  * commences. Any value written to this register is loaded into the associated
77  * timer.
78  *
79  * Field Access Macros:
80  *
81  */
82 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field. */
83 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_LSB 0
84 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field. */
85 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_MSB 31
86 /* The width in bits of the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field. */
87 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_WIDTH 32
88 /* The mask used to set the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field value. */
89 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_SET_MSK 0xffffffff
90 /* The mask used to clear the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field value. */
91 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_CLR_MSK 0x00000000
92 /* The reset value of the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field. */
93 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_RESET 0x0
94 /* Extracts the ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT field value from a register. */
95 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_GET(value) (((value) & 0xffffffff) >> 0)
96 /* Produces a ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT register field value suitable for setting the register. */
97 #define ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT_SET(value) (((value) << 0) & 0xffffffff)
98 
99 #ifndef __ASSEMBLY__
100 /*
101  * WARNING: The C register and register group struct declarations are provided for
102  * convenience and illustrative purposes. They should, however, be used with
103  * caution as the C language standard provides no guarantees about the alignment or
104  * atomicity of device memory accesses. The recommended practice for coding device
105  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
106  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
107  * alt_write_dword() functions for 64 bit registers.
108  *
109  * The struct declaration for register ALT_TMR_TIMER1LOADCOUNT.
110  */
111 struct ALT_TMR_TIMER1LOADCOUNT_s
112 {
113  volatile uint32_t TIMER1LOADCOUNT : 32; /* ALT_TMR_TIMER1LOADCOUNT_TIMER1LOADCOUNT */
114 };
115 
116 /* The typedef declaration for register ALT_TMR_TIMER1LOADCOUNT. */
117 typedef struct ALT_TMR_TIMER1LOADCOUNT_s ALT_TMR_TIMER1LOADCOUNT_t;
118 #endif /* __ASSEMBLY__ */
119 
120 /* The reset value of the ALT_TMR_TIMER1LOADCOUNT register. */
121 #define ALT_TMR_TIMER1LOADCOUNT_RESET 0x00000000
122 /* The byte offset of the ALT_TMR_TIMER1LOADCOUNT register from the beginning of the component. */
123 #define ALT_TMR_TIMER1LOADCOUNT_OFST 0x0
124 /* The address of the ALT_TMR_TIMER1LOADCOUNT register. */
125 #define ALT_TMR_TIMER1LOADCOUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMER1LOADCOUNT_OFST))
126 
127 /*
128  * Register : TIMER1CURRENTVAL
129  *
130  * Name: Timer1 Current Value
131  *
132  * Size: 8-32 bits
133  *
134  * Address Offset: 4
135  *
136  * Read/Write Access: Read
137  *
138  * Register Layout
139  *
140  * Bits | Access | Reset | Description
141  * :-------|:-------|:------|:------------------------------------------
142  * [31:0] | R | 0x0 | ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL
143  *
144  */
145 /*
146  * Field : TIMER1CURRENTVAL
147  *
148  * Current Value of Timer1. This register is supported only
149  *
150  * when timer_1_clk is synchronous to pclk. Reading this
151  *
152  * register when using independent clocks results in an
153  *
154  * undefined value.
155  *
156  * Field Access Macros:
157  *
158  */
159 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field. */
160 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_LSB 0
161 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field. */
162 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_MSB 31
163 /* The width in bits of the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field. */
164 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_WIDTH 32
165 /* The mask used to set the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field value. */
166 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_SET_MSK 0xffffffff
167 /* The mask used to clear the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field value. */
168 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_CLR_MSK 0x00000000
169 /* The reset value of the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field. */
170 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_RESET 0x0
171 /* Extracts the ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL field value from a register. */
172 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_GET(value) (((value) & 0xffffffff) >> 0)
173 /* Produces a ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL register field value suitable for setting the register. */
174 #define ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL_SET(value) (((value) << 0) & 0xffffffff)
175 
176 #ifndef __ASSEMBLY__
177 /*
178  * WARNING: The C register and register group struct declarations are provided for
179  * convenience and illustrative purposes. They should, however, be used with
180  * caution as the C language standard provides no guarantees about the alignment or
181  * atomicity of device memory accesses. The recommended practice for coding device
182  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
183  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
184  * alt_write_dword() functions for 64 bit registers.
185  *
186  * The struct declaration for register ALT_TMR_TIMER1CURRENTVAL.
187  */
188 struct ALT_TMR_TIMER1CURRENTVAL_s
189 {
190  const volatile uint32_t TIMER1CURRENTVAL : 32; /* ALT_TMR_TIMER1CURRENTVAL_TIMER1CURRENTVAL */
191 };
192 
193 /* The typedef declaration for register ALT_TMR_TIMER1CURRENTVAL. */
194 typedef struct ALT_TMR_TIMER1CURRENTVAL_s ALT_TMR_TIMER1CURRENTVAL_t;
195 #endif /* __ASSEMBLY__ */
196 
197 /* The reset value of the ALT_TMR_TIMER1CURRENTVAL register. */
198 #define ALT_TMR_TIMER1CURRENTVAL_RESET 0x00000000
199 /* The byte offset of the ALT_TMR_TIMER1CURRENTVAL register from the beginning of the component. */
200 #define ALT_TMR_TIMER1CURRENTVAL_OFST 0x4
201 /* The address of the ALT_TMR_TIMER1CURRENTVAL register. */
202 #define ALT_TMR_TIMER1CURRENTVAL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMER1CURRENTVAL_OFST))
203 
204 /*
205  * Register : Timer1 Control Register - TIMER1CONTROLREG
206  *
207  * Name: Timer1 Control Register
208  *
209  * Size: 4 bits
210  *
211  * Address Offset: 8
212  *
213  * Read/Write Access: Read/Write
214  *
215  * This register controls enabling, operating mode (free-running or defined-count),
216  * and interrupt mask of
217  *
218  * Timer1. You can program each Timer1ControlReg to enable or disable a specific
219  * timer and to control
220  *
221  * its mode of operation.
222  *
223  * Register Layout
224  *
225  * Bits | Access | Reset | Description
226  * :-------|:-------|:------|:----------------------------------------------
227  * [0] | RW | 0x0 | ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE
228  * [1] | RW | 0x0 | ALT_TMR_TIMER1CONTROLREG_TIMER_MODE
229  * [2] | RW | 0x0 | ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK
230  * [31:3] | ??? | 0x0 | *UNDEFINED*
231  *
232  */
233 /*
234  * Field : TIMER_ENABLE
235  *
236  * Timer enable bit for Timer1.
237  *
238  * 0: disable
239  *
240  * 1: enable
241  *
242  * Field Enumeration Values:
243  *
244  * Enum | Value | Description
245  * :------------------------------------------------|:------|:-------------------
246  * ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_E_DISABLE | 0x0 | Timer1 is disabled
247  * ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_E_ENABLED | 0x1 | Timer1 is enabled
248  *
249  * Field Access Macros:
250  *
251  */
252 /*
253  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE
254  *
255  * Timer1 is disabled
256  */
257 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_E_DISABLE 0x0
258 /*
259  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE
260  *
261  * Timer1 is enabled
262  */
263 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_E_ENABLED 0x1
264 
265 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field. */
266 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_LSB 0
267 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field. */
268 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_MSB 0
269 /* The width in bits of the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field. */
270 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_WIDTH 1
271 /* The mask used to set the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field value. */
272 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_SET_MSK 0x00000001
273 /* The mask used to clear the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field value. */
274 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_CLR_MSK 0xfffffffe
275 /* The reset value of the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field. */
276 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_RESET 0x0
277 /* Extracts the ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE field value from a register. */
278 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
279 /* Produces a ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE register field value suitable for setting the register. */
280 #define ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE_SET(value) (((value) << 0) & 0x00000001)
281 
282 /*
283  * Field : TIMER_MODE
284  *
285  * Timer mode for Timer1.
286  *
287  * 0: free_running mode
288  *
289  * 1: user_defined count mode
290  *
291  * NOTE: You must set the Timer1LoadCount register to all 1s before
292  *
293  * enabling the timer in free-running mode.
294  *
295  * Field Enumeration Values:
296  *
297  * Enum | Value | Description
298  * :---------------------------------------------------|:------|:-------------------------------
299  * ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_E_FREE_RUNNING | 0x0 | Free Running mode of operation
300  * ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_E_USER_DEFINED | 0x1 | User-Defined mode of operation
301  *
302  * Field Access Macros:
303  *
304  */
305 /*
306  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_MODE
307  *
308  * Free Running mode of operation
309  */
310 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_E_FREE_RUNNING 0x0
311 /*
312  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_MODE
313  *
314  * User-Defined mode of operation
315  */
316 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_E_USER_DEFINED 0x1
317 
318 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field. */
319 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_LSB 1
320 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field. */
321 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_MSB 1
322 /* The width in bits of the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field. */
323 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_WIDTH 1
324 /* The mask used to set the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field value. */
325 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_SET_MSK 0x00000002
326 /* The mask used to clear the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field value. */
327 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_CLR_MSK 0xfffffffd
328 /* The reset value of the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field. */
329 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_RESET 0x0
330 /* Extracts the ALT_TMR_TIMER1CONTROLREG_TIMER_MODE field value from a register. */
331 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_GET(value) (((value) & 0x00000002) >> 1)
332 /* Produces a ALT_TMR_TIMER1CONTROLREG_TIMER_MODE register field value suitable for setting the register. */
333 #define ALT_TMR_TIMER1CONTROLREG_TIMER_MODE_SET(value) (((value) << 1) & 0x00000002)
334 
335 /*
336  * Field : TIMER_INTERRUPT_MASK
337  *
338  * Timer interrupt mask for Timer1.
339  *
340  * 0: not masked
341  *
342  * 1: masked
343  *
344  * Field Enumeration Values:
345  *
346  * Enum | Value | Description
347  * :---------------------------------------------------------|:------|:-----------------------------
348  * ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_E_UNMASKED | 0x0 | Timer1 interrupt is unmasked
349  * ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_E_MASKED | 0x1 | Timer1 interrupt is masked
350  *
351  * Field Access Macros:
352  *
353  */
354 /*
355  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK
356  *
357  * Timer1 interrupt is unmasked
358  */
359 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_E_UNMASKED 0x0
360 /*
361  * Enumerated value for register field ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK
362  *
363  * Timer1 interrupt is masked
364  */
365 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_E_MASKED 0x1
366 
367 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field. */
368 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_LSB 2
369 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field. */
370 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_MSB 2
371 /* The width in bits of the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field. */
372 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_WIDTH 1
373 /* The mask used to set the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field value. */
374 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_SET_MSK 0x00000004
375 /* The mask used to clear the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field value. */
376 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_CLR_MSK 0xfffffffb
377 /* The reset value of the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field. */
378 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_RESET 0x0
379 /* Extracts the ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK field value from a register. */
380 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_GET(value) (((value) & 0x00000004) >> 2)
381 /* Produces a ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK register field value suitable for setting the register. */
382 #define ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK_SET(value) (((value) << 2) & 0x00000004)
383 
384 #ifndef __ASSEMBLY__
385 /*
386  * WARNING: The C register and register group struct declarations are provided for
387  * convenience and illustrative purposes. They should, however, be used with
388  * caution as the C language standard provides no guarantees about the alignment or
389  * atomicity of device memory accesses. The recommended practice for coding device
390  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
391  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
392  * alt_write_dword() functions for 64 bit registers.
393  *
394  * The struct declaration for register ALT_TMR_TIMER1CONTROLREG.
395  */
396 struct ALT_TMR_TIMER1CONTROLREG_s
397 {
398  volatile uint32_t TIMER_ENABLE : 1; /* ALT_TMR_TIMER1CONTROLREG_TIMER_ENABLE */
399  volatile uint32_t TIMER_MODE : 1; /* ALT_TMR_TIMER1CONTROLREG_TIMER_MODE */
400  volatile uint32_t TIMER_INTERRUPT_MASK : 1; /* ALT_TMR_TIMER1CONTROLREG_TIMER_INTERRUPT_MASK */
401  uint32_t : 29; /* *UNDEFINED* */
402 };
403 
404 /* The typedef declaration for register ALT_TMR_TIMER1CONTROLREG. */
405 typedef struct ALT_TMR_TIMER1CONTROLREG_s ALT_TMR_TIMER1CONTROLREG_t;
406 #endif /* __ASSEMBLY__ */
407 
408 /* The reset value of the ALT_TMR_TIMER1CONTROLREG register. */
409 #define ALT_TMR_TIMER1CONTROLREG_RESET 0x00000000
410 /* The byte offset of the ALT_TMR_TIMER1CONTROLREG register from the beginning of the component. */
411 #define ALT_TMR_TIMER1CONTROLREG_OFST 0x8
412 /* The address of the ALT_TMR_TIMER1CONTROLREG register. */
413 #define ALT_TMR_TIMER1CONTROLREG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMER1CONTROLREG_OFST))
414 
415 /*
416  * Register : Timer1 End-of-Interrupt Register - TIMER1EOI
417  *
418  * Name: Timer1 End-of-Interrupt Register
419  *
420  * Size: 1 bit
421  *
422  * Address Offset: 12
423  *
424  * Read/Write Access: Read
425  *
426  * Register Layout
427  *
428  * Bits | Access | Reset | Description
429  * :-------|:-------|:------|:----------------------------
430  * [0] | R | 0x0 | ALT_TMR_TIMER1EOI_TIMER1EOI
431  * [31:1] | ??? | 0x0 | *UNDEFINED*
432  *
433  */
434 /*
435  * Field : TIMER1EOI
436  *
437  * Reading from this register
438  *
439  * returns all zeroes (0) and clears the interrupt from Timer1.
440  *
441  * Field Access Macros:
442  *
443  */
444 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1EOI_TIMER1EOI register field. */
445 #define ALT_TMR_TIMER1EOI_TIMER1EOI_LSB 0
446 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1EOI_TIMER1EOI register field. */
447 #define ALT_TMR_TIMER1EOI_TIMER1EOI_MSB 0
448 /* The width in bits of the ALT_TMR_TIMER1EOI_TIMER1EOI register field. */
449 #define ALT_TMR_TIMER1EOI_TIMER1EOI_WIDTH 1
450 /* The mask used to set the ALT_TMR_TIMER1EOI_TIMER1EOI register field value. */
451 #define ALT_TMR_TIMER1EOI_TIMER1EOI_SET_MSK 0x00000001
452 /* The mask used to clear the ALT_TMR_TIMER1EOI_TIMER1EOI register field value. */
453 #define ALT_TMR_TIMER1EOI_TIMER1EOI_CLR_MSK 0xfffffffe
454 /* The reset value of the ALT_TMR_TIMER1EOI_TIMER1EOI register field. */
455 #define ALT_TMR_TIMER1EOI_TIMER1EOI_RESET 0x0
456 /* Extracts the ALT_TMR_TIMER1EOI_TIMER1EOI field value from a register. */
457 #define ALT_TMR_TIMER1EOI_TIMER1EOI_GET(value) (((value) & 0x00000001) >> 0)
458 /* Produces a ALT_TMR_TIMER1EOI_TIMER1EOI register field value suitable for setting the register. */
459 #define ALT_TMR_TIMER1EOI_TIMER1EOI_SET(value) (((value) << 0) & 0x00000001)
460 
461 #ifndef __ASSEMBLY__
462 /*
463  * WARNING: The C register and register group struct declarations are provided for
464  * convenience and illustrative purposes. They should, however, be used with
465  * caution as the C language standard provides no guarantees about the alignment or
466  * atomicity of device memory accesses. The recommended practice for coding device
467  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
468  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
469  * alt_write_dword() functions for 64 bit registers.
470  *
471  * The struct declaration for register ALT_TMR_TIMER1EOI.
472  */
473 struct ALT_TMR_TIMER1EOI_s
474 {
475  const volatile uint32_t TIMER1EOI : 1; /* ALT_TMR_TIMER1EOI_TIMER1EOI */
476  uint32_t : 31; /* *UNDEFINED* */
477 };
478 
479 /* The typedef declaration for register ALT_TMR_TIMER1EOI. */
480 typedef struct ALT_TMR_TIMER1EOI_s ALT_TMR_TIMER1EOI_t;
481 #endif /* __ASSEMBLY__ */
482 
483 /* The reset value of the ALT_TMR_TIMER1EOI register. */
484 #define ALT_TMR_TIMER1EOI_RESET 0x00000000
485 /* The byte offset of the ALT_TMR_TIMER1EOI register from the beginning of the component. */
486 #define ALT_TMR_TIMER1EOI_OFST 0xc
487 /* The address of the ALT_TMR_TIMER1EOI register. */
488 #define ALT_TMR_TIMER1EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMER1EOI_OFST))
489 
490 /*
491  * Register : Timer1 Interrupt Status Register - TIMER1INTSTAT
492  *
493  * Name: Timer1 Interrupt Status Register
494  *
495  * Size: 1 bit
496  *
497  * Address Offset: 16
498  *
499  * Read/Write Access: Read
500  *
501  * Register Layout
502  *
503  * Bits | Access | Reset | Description
504  * :-------|:-------|:------|:------------------------------------
505  * [0] | R | 0x0 | ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT
506  * [31:1] | ??? | 0x0 | *UNDEFINED*
507  *
508  */
509 /*
510  * Field : TIMER1INTSTAT
511  *
512  * Contains the interrupt status for Timer1.
513  *
514  * Field Enumeration Values:
515  *
516  * Enum | Value | Description
517  * :-----------------------------------------------|:------|:-----------------------------
518  * ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_E_INACTIVE | 0x0 | Timer2 Interrupt is inactive
519  * ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_E_ACTIVE | 0x1 | Timer1 Interrupt is active
520  *
521  * Field Access Macros:
522  *
523  */
524 /*
525  * Enumerated value for register field ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT
526  *
527  * Timer2 Interrupt is inactive
528  */
529 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_E_INACTIVE 0x0
530 /*
531  * Enumerated value for register field ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT
532  *
533  * Timer1 Interrupt is active
534  */
535 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_E_ACTIVE 0x1
536 
537 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field. */
538 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_LSB 0
539 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field. */
540 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_MSB 0
541 /* The width in bits of the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field. */
542 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_WIDTH 1
543 /* The mask used to set the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field value. */
544 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_SET_MSK 0x00000001
545 /* The mask used to clear the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field value. */
546 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_CLR_MSK 0xfffffffe
547 /* The reset value of the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field. */
548 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_RESET 0x0
549 /* Extracts the ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT field value from a register. */
550 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_GET(value) (((value) & 0x00000001) >> 0)
551 /* Produces a ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT register field value suitable for setting the register. */
552 #define ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT_SET(value) (((value) << 0) & 0x00000001)
553 
554 #ifndef __ASSEMBLY__
555 /*
556  * WARNING: The C register and register group struct declarations are provided for
557  * convenience and illustrative purposes. They should, however, be used with
558  * caution as the C language standard provides no guarantees about the alignment or
559  * atomicity of device memory accesses. The recommended practice for coding device
560  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
561  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
562  * alt_write_dword() functions for 64 bit registers.
563  *
564  * The struct declaration for register ALT_TMR_TIMER1INTSTAT.
565  */
566 struct ALT_TMR_TIMER1INTSTAT_s
567 {
568  const volatile uint32_t TIMER1INTSTAT : 1; /* ALT_TMR_TIMER1INTSTAT_TIMER1INTSTAT */
569  uint32_t : 31; /* *UNDEFINED* */
570 };
571 
572 /* The typedef declaration for register ALT_TMR_TIMER1INTSTAT. */
573 typedef struct ALT_TMR_TIMER1INTSTAT_s ALT_TMR_TIMER1INTSTAT_t;
574 #endif /* __ASSEMBLY__ */
575 
576 /* The reset value of the ALT_TMR_TIMER1INTSTAT register. */
577 #define ALT_TMR_TIMER1INTSTAT_RESET 0x00000000
578 /* The byte offset of the ALT_TMR_TIMER1INTSTAT register from the beginning of the component. */
579 #define ALT_TMR_TIMER1INTSTAT_OFST 0x10
580 /* The address of the ALT_TMR_TIMER1INTSTAT register. */
581 #define ALT_TMR_TIMER1INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMER1INTSTAT_OFST))
582 
583 /*
584  * Register : Timers Interrupt Status Register - TIMERSINTSTAT
585  *
586  * Name: Timers Interrupt Status Register
587  *
588  * Size: 1-8 bits
589  *
590  * Address Offset: 0xa0
591  *
592  * Read/Write Access: Read
593  *
594  * Register Layout
595  *
596  * Bits | Access | Reset | Description
597  * :-------|:-------|:------|:------------------------------------
598  * [0] | R | 0x0 | ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT
599  * [31:1] | ??? | 0x0 | *UNDEFINED*
600  *
601  */
602 /*
603  * Field : TIMERSINTSTAT
604  *
605  * Contains the interrupt status of all timers in the component. If a bit of
606  *
607  * this register is 0, then the corresponding timer interrupt is not active
608  *
609  * and the corresponding interrupt could be on either the timer_intr bus
610  *
611  * or the timer_intr_n bus, depending on the interrupt polarity you have
612  *
613  * chosen. Similarly, if a bit of this register is 1, then the corresponding
614  *
615  * interrupt bit has been set in the relevant interrupt bus. In both cases,
616  *
617  * the status reported is the status after the interrupt mask has been
618  *
619  * applied. Reading from this register does not clear any active
620  *
621  * interrupts:
622  *
623  * 0 = either timer_intr or timer_intr_n is not active after masking
624  *
625  * 1 = either timer_intr or timer_intr_n is active after masking.
626  *
627  * Field Enumeration Values:
628  *
629  * Enum | Value | Description
630  * :-----------------------------------------------|:------|:---------------------------
631  * ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_E_INACTIVE | 0x0 | Timer_intr(_n) is inactive
632  * ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_E_ACTIVE | 0x1 | Timer_intr(_n) is active
633  *
634  * Field Access Macros:
635  *
636  */
637 /*
638  * Enumerated value for register field ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT
639  *
640  * Timer_intr(_n) is inactive
641  */
642 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_E_INACTIVE 0x0
643 /*
644  * Enumerated value for register field ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT
645  *
646  * Timer_intr(_n) is active
647  */
648 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_E_ACTIVE 0x1
649 
650 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field. */
651 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_LSB 0
652 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field. */
653 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_MSB 0
654 /* The width in bits of the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field. */
655 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_WIDTH 1
656 /* The mask used to set the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field value. */
657 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_SET_MSK 0x00000001
658 /* The mask used to clear the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field value. */
659 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_CLR_MSK 0xfffffffe
660 /* The reset value of the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field. */
661 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_RESET 0x0
662 /* Extracts the ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT field value from a register. */
663 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
664 /* Produces a ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT register field value suitable for setting the register. */
665 #define ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT_SET(value) (((value) << 0) & 0x00000001)
666 
667 #ifndef __ASSEMBLY__
668 /*
669  * WARNING: The C register and register group struct declarations are provided for
670  * convenience and illustrative purposes. They should, however, be used with
671  * caution as the C language standard provides no guarantees about the alignment or
672  * atomicity of device memory accesses. The recommended practice for coding device
673  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
674  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
675  * alt_write_dword() functions for 64 bit registers.
676  *
677  * The struct declaration for register ALT_TMR_TIMERSINTSTAT.
678  */
679 struct ALT_TMR_TIMERSINTSTAT_s
680 {
681  const volatile uint32_t TIMERSINTSTAT : 1; /* ALT_TMR_TIMERSINTSTAT_TIMERSINTSTAT */
682  uint32_t : 31; /* *UNDEFINED* */
683 };
684 
685 /* The typedef declaration for register ALT_TMR_TIMERSINTSTAT. */
686 typedef struct ALT_TMR_TIMERSINTSTAT_s ALT_TMR_TIMERSINTSTAT_t;
687 #endif /* __ASSEMBLY__ */
688 
689 /* The reset value of the ALT_TMR_TIMERSINTSTAT register. */
690 #define ALT_TMR_TIMERSINTSTAT_RESET 0x00000000
691 /* The byte offset of the ALT_TMR_TIMERSINTSTAT register from the beginning of the component. */
692 #define ALT_TMR_TIMERSINTSTAT_OFST 0xa0
693 /* The address of the ALT_TMR_TIMERSINTSTAT register. */
694 #define ALT_TMR_TIMERSINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMERSINTSTAT_OFST))
695 
696 /*
697  * Register : Timers End-of-Interrupt Register - TIMERSEOI
698  *
699  * Name: Timers End-of-Interrupt Register
700  *
701  * Size: 1-8 bits
702  *
703  * Address Offset: 0xa4
704  *
705  * Read/Write Access: Read
706  *
707  * Register Layout
708  *
709  * Bits | Access | Reset | Description
710  * :-------|:-------|:------|:----------------------------
711  * [0] | R | 0x0 | ALT_TMR_TIMERSEOI_TIMERSEOI
712  * [31:1] | ??? | 0x0 | *UNDEFINED*
713  *
714  */
715 /*
716  * Field : TIMERSEOI
717  *
718  * Reading this register returns all zeroes (0) and clears all active
719  *
720  * interrupts.
721  *
722  * Field Access Macros:
723  *
724  */
725 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMERSEOI_TIMERSEOI register field. */
726 #define ALT_TMR_TIMERSEOI_TIMERSEOI_LSB 0
727 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMERSEOI_TIMERSEOI register field. */
728 #define ALT_TMR_TIMERSEOI_TIMERSEOI_MSB 0
729 /* The width in bits of the ALT_TMR_TIMERSEOI_TIMERSEOI register field. */
730 #define ALT_TMR_TIMERSEOI_TIMERSEOI_WIDTH 1
731 /* The mask used to set the ALT_TMR_TIMERSEOI_TIMERSEOI register field value. */
732 #define ALT_TMR_TIMERSEOI_TIMERSEOI_SET_MSK 0x00000001
733 /* The mask used to clear the ALT_TMR_TIMERSEOI_TIMERSEOI register field value. */
734 #define ALT_TMR_TIMERSEOI_TIMERSEOI_CLR_MSK 0xfffffffe
735 /* The reset value of the ALT_TMR_TIMERSEOI_TIMERSEOI register field. */
736 #define ALT_TMR_TIMERSEOI_TIMERSEOI_RESET 0x0
737 /* Extracts the ALT_TMR_TIMERSEOI_TIMERSEOI field value from a register. */
738 #define ALT_TMR_TIMERSEOI_TIMERSEOI_GET(value) (((value) & 0x00000001) >> 0)
739 /* Produces a ALT_TMR_TIMERSEOI_TIMERSEOI register field value suitable for setting the register. */
740 #define ALT_TMR_TIMERSEOI_TIMERSEOI_SET(value) (((value) << 0) & 0x00000001)
741 
742 #ifndef __ASSEMBLY__
743 /*
744  * WARNING: The C register and register group struct declarations are provided for
745  * convenience and illustrative purposes. They should, however, be used with
746  * caution as the C language standard provides no guarantees about the alignment or
747  * atomicity of device memory accesses. The recommended practice for coding device
748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
750  * alt_write_dword() functions for 64 bit registers.
751  *
752  * The struct declaration for register ALT_TMR_TIMERSEOI.
753  */
754 struct ALT_TMR_TIMERSEOI_s
755 {
756  const volatile uint32_t TIMERSEOI : 1; /* ALT_TMR_TIMERSEOI_TIMERSEOI */
757  uint32_t : 31; /* *UNDEFINED* */
758 };
759 
760 /* The typedef declaration for register ALT_TMR_TIMERSEOI. */
761 typedef struct ALT_TMR_TIMERSEOI_s ALT_TMR_TIMERSEOI_t;
762 #endif /* __ASSEMBLY__ */
763 
764 /* The reset value of the ALT_TMR_TIMERSEOI register. */
765 #define ALT_TMR_TIMERSEOI_RESET 0x00000000
766 /* The byte offset of the ALT_TMR_TIMERSEOI register from the beginning of the component. */
767 #define ALT_TMR_TIMERSEOI_OFST 0xa4
768 /* The address of the ALT_TMR_TIMERSEOI register. */
769 #define ALT_TMR_TIMERSEOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMERSEOI_OFST))
770 
771 /*
772  * Register : Timers Raw Interrupt Status Register - TIMERSRAWINTSTAT
773  *
774  * Name: Timers Raw Interrupt Status Register
775  *
776  * Size: 1-8 bits
777  *
778  * Address Offset: 0xa8
779  *
780  * Read/Write Access: Read
781  *
782  * Register Layout
783  *
784  * Bits | Access | Reset | Description
785  * :-------|:-------|:------|:------------------------------------------
786  * [0] | R | 0x0 | ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT
787  * [31:1] | ??? | 0x0 | *UNDEFINED*
788  *
789  */
790 /*
791  * Field : TIMERSRAWINTSTAT
792  *
793  * The register contains the unmasked interrupt status of all timers in
794  *
795  * the component.
796  *
797  * 0 = either timer_intr or timer_intr_n is not active prior to masking
798  *
799  * 1 = either timer_intr or timer_intr_n is active prior to masking.
800  *
801  * Field Enumeration Values:
802  *
803  * Enum | Value | Description
804  * :-----------------------------------------------------|:------|:-------------------------------
805  * ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_E_INACTIVE | 0x0 | Raw Timer_intr(_n) is inactive
806  * ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_E_ACTIVE | 0x1 | Raw Timer_intr(_n) is active
807  *
808  * Field Access Macros:
809  *
810  */
811 /*
812  * Enumerated value for register field ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT
813  *
814  * Raw Timer_intr(_n) is inactive
815  */
816 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_E_INACTIVE 0x0
817 /*
818  * Enumerated value for register field ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT
819  *
820  * Raw Timer_intr(_n) is active
821  */
822 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_E_ACTIVE 0x1
823 
824 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field. */
825 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_LSB 0
826 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field. */
827 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_MSB 0
828 /* The width in bits of the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field. */
829 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_WIDTH 1
830 /* The mask used to set the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field value. */
831 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_SET_MSK 0x00000001
832 /* The mask used to clear the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field value. */
833 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_CLR_MSK 0xfffffffe
834 /* The reset value of the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field. */
835 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_RESET 0x0
836 /* Extracts the ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT field value from a register. */
837 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_GET(value) (((value) & 0x00000001) >> 0)
838 /* Produces a ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT register field value suitable for setting the register. */
839 #define ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT_SET(value) (((value) << 0) & 0x00000001)
840 
841 #ifndef __ASSEMBLY__
842 /*
843  * WARNING: The C register and register group struct declarations are provided for
844  * convenience and illustrative purposes. They should, however, be used with
845  * caution as the C language standard provides no guarantees about the alignment or
846  * atomicity of device memory accesses. The recommended practice for coding device
847  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
848  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
849  * alt_write_dword() functions for 64 bit registers.
850  *
851  * The struct declaration for register ALT_TMR_TIMERSRAWINTSTAT.
852  */
853 struct ALT_TMR_TIMERSRAWINTSTAT_s
854 {
855  const volatile uint32_t TIMERSRAWINTSTAT : 1; /* ALT_TMR_TIMERSRAWINTSTAT_TIMERSRAWINTSTAT */
856  uint32_t : 31; /* *UNDEFINED* */
857 };
858 
859 /* The typedef declaration for register ALT_TMR_TIMERSRAWINTSTAT. */
860 typedef struct ALT_TMR_TIMERSRAWINTSTAT_s ALT_TMR_TIMERSRAWINTSTAT_t;
861 #endif /* __ASSEMBLY__ */
862 
863 /* The reset value of the ALT_TMR_TIMERSRAWINTSTAT register. */
864 #define ALT_TMR_TIMERSRAWINTSTAT_RESET 0x00000000
865 /* The byte offset of the ALT_TMR_TIMERSRAWINTSTAT register from the beginning of the component. */
866 #define ALT_TMR_TIMERSRAWINTSTAT_OFST 0xa8
867 /* The address of the ALT_TMR_TIMERSRAWINTSTAT register. */
868 #define ALT_TMR_TIMERSRAWINTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMERSRAWINTSTAT_OFST))
869 
870 /*
871  * Register : Timers Component Version - TIMERSCOMPVERSION
872  *
873  * Name: Timers Component Version
874  *
875  * Size: 32 bits
876  *
877  * Address Offset: 0xac
878  *
879  * Read/Write Access: Read
880  *
881  * Register Layout
882  *
883  * Bits | Access | Reset | Description
884  * :-------|:-------|:-----------|:--------------------------------------------
885  * [31:0] | R | 0x3230392a | ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION
886  *
887  */
888 /*
889  * Field : TIMERSCOMPVERSION
890  *
891  * Current revision number of the DW_apb_timers component.
892  *
893  * Field Access Macros:
894  *
895  */
896 /* The Least Significant Bit (LSB) position of the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field. */
897 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_LSB 0
898 /* The Most Significant Bit (MSB) position of the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field. */
899 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_MSB 31
900 /* The width in bits of the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field. */
901 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_WIDTH 32
902 /* The mask used to set the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field value. */
903 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_SET_MSK 0xffffffff
904 /* The mask used to clear the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field value. */
905 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_CLR_MSK 0x00000000
906 /* The reset value of the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field. */
907 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_RESET 0x3230392a
908 /* Extracts the ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION field value from a register. */
909 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_GET(value) (((value) & 0xffffffff) >> 0)
910 /* Produces a ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION register field value suitable for setting the register. */
911 #define ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION_SET(value) (((value) << 0) & 0xffffffff)
912 
913 #ifndef __ASSEMBLY__
914 /*
915  * WARNING: The C register and register group struct declarations are provided for
916  * convenience and illustrative purposes. They should, however, be used with
917  * caution as the C language standard provides no guarantees about the alignment or
918  * atomicity of device memory accesses. The recommended practice for coding device
919  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
920  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
921  * alt_write_dword() functions for 64 bit registers.
922  *
923  * The struct declaration for register ALT_TMR_TIMERSCOMPVERSION.
924  */
925 struct ALT_TMR_TIMERSCOMPVERSION_s
926 {
927  const volatile uint32_t TIMERSCOMPVERSION : 32; /* ALT_TMR_TIMERSCOMPVERSION_TIMERSCOMPVERSION */
928 };
929 
930 /* The typedef declaration for register ALT_TMR_TIMERSCOMPVERSION. */
931 typedef struct ALT_TMR_TIMERSCOMPVERSION_s ALT_TMR_TIMERSCOMPVERSION_t;
932 #endif /* __ASSEMBLY__ */
933 
934 /* The reset value of the ALT_TMR_TIMERSCOMPVERSION register. */
935 #define ALT_TMR_TIMERSCOMPVERSION_RESET 0x3230392a
936 /* The byte offset of the ALT_TMR_TIMERSCOMPVERSION register from the beginning of the component. */
937 #define ALT_TMR_TIMERSCOMPVERSION_OFST 0xac
938 /* The address of the ALT_TMR_TIMERSCOMPVERSION register. */
939 #define ALT_TMR_TIMERSCOMPVERSION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TIMERSCOMPVERSION_OFST))
940 
941 #ifndef __ASSEMBLY__
942 /*
943  * WARNING: The C register and register group struct declarations are provided for
944  * convenience and illustrative purposes. They should, however, be used with
945  * caution as the C language standard provides no guarantees about the alignment or
946  * atomicity of device memory accesses. The recommended practice for coding device
947  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
948  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
949  * alt_write_dword() functions for 64 bit registers.
950  *
951  * The struct declaration for register group ALT_TMR.
952  */
953 struct ALT_TMR_s
954 {
955  volatile ALT_TMR_TIMER1LOADCOUNT_t TIMER1LOADCOUNT; /* ALT_TMR_TIMER1LOADCOUNT */
956  volatile ALT_TMR_TIMER1CURRENTVAL_t TIMER1CURRENTVAL; /* ALT_TMR_TIMER1CURRENTVAL */
957  volatile ALT_TMR_TIMER1CONTROLREG_t TIMER1CONTROLREG; /* ALT_TMR_TIMER1CONTROLREG */
958  volatile ALT_TMR_TIMER1EOI_t TIMER1EOI; /* ALT_TMR_TIMER1EOI */
959  volatile ALT_TMR_TIMER1INTSTAT_t TIMER1INTSTAT; /* ALT_TMR_TIMER1INTSTAT */
960  volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
961  volatile ALT_TMR_TIMERSINTSTAT_t TIMERSINTSTAT; /* ALT_TMR_TIMERSINTSTAT */
962  volatile ALT_TMR_TIMERSEOI_t TIMERSEOI; /* ALT_TMR_TIMERSEOI */
963  volatile ALT_TMR_TIMERSRAWINTSTAT_t TIMERSRAWINTSTAT; /* ALT_TMR_TIMERSRAWINTSTAT */
964  volatile ALT_TMR_TIMERSCOMPVERSION_t TIMERSCOMPVERSION; /* ALT_TMR_TIMERSCOMPVERSION */
965  volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
966 };
967 
968 /* The typedef declaration for register group ALT_TMR. */
969 typedef struct ALT_TMR_s ALT_TMR_t;
970 /* The struct declaration for the raw register contents of register group ALT_TMR. */
971 struct ALT_TMR_raw_s
972 {
973  volatile uint32_t TIMER1LOADCOUNT; /* ALT_TMR_TIMER1LOADCOUNT */
974  volatile uint32_t TIMER1CURRENTVAL; /* ALT_TMR_TIMER1CURRENTVAL */
975  volatile uint32_t TIMER1CONTROLREG; /* ALT_TMR_TIMER1CONTROLREG */
976  volatile uint32_t TIMER1EOI; /* ALT_TMR_TIMER1EOI */
977  volatile uint32_t TIMER1INTSTAT; /* ALT_TMR_TIMER1INTSTAT */
978  volatile uint32_t _pad_0x14_0x9f[35]; /* *UNDEFINED* */
979  volatile uint32_t TIMERSINTSTAT; /* ALT_TMR_TIMERSINTSTAT */
980  volatile uint32_t TIMERSEOI; /* ALT_TMR_TIMERSEOI */
981  volatile uint32_t TIMERSRAWINTSTAT; /* ALT_TMR_TIMERSRAWINTSTAT */
982  volatile uint32_t TIMERSCOMPVERSION; /* ALT_TMR_TIMERSCOMPVERSION */
983  volatile uint32_t _pad_0xb0_0x100[20]; /* *UNDEFINED* */
984 };
985 
986 /* The typedef declaration for the raw register contents of register group ALT_TMR. */
987 typedef struct ALT_TMR_raw_s ALT_TMR_raw_t;
988 #endif /* __ASSEMBLY__ */
989 
990 
991 #ifdef __cplusplus
992 }
993 #endif /* __cplusplus */
994 #endif /* __ALT_SOCAL_TMR_H__ */
995