35 #ifndef __ALTERA_ALT_RSTMGR_H__
36 #define __ALTERA_ALT_RSTMGR_H__
111 #define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
113 #define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
115 #define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
117 #define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
119 #define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
121 #define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
123 #define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
125 #define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
136 #define ALT_RSTMGR_STAT_NPORPINRST_LSB 1
138 #define ALT_RSTMGR_STAT_NPORPINRST_MSB 1
140 #define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
142 #define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
144 #define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
146 #define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
148 #define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
150 #define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
161 #define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
163 #define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
165 #define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
167 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
169 #define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
171 #define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
173 #define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
175 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
186 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
188 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
190 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
192 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
194 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
196 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
198 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
200 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
211 #define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
213 #define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
215 #define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
217 #define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
219 #define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
221 #define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
223 #define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
225 #define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
236 #define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
238 #define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
240 #define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
242 #define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
244 #define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
246 #define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
248 #define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
250 #define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
261 #define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
263 #define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
265 #define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
267 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
269 #define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
271 #define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
273 #define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
275 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
287 #define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
289 #define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
291 #define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
293 #define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
295 #define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
297 #define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
299 #define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
301 #define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
312 #define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
314 #define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
316 #define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
318 #define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
320 #define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
322 #define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
324 #define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
326 #define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
337 #define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
339 #define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
341 #define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
343 #define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
345 #define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
347 #define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
349 #define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
351 #define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
362 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 14
364 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 14
366 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
368 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
370 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
372 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
374 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
376 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
387 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 15
389 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 15
391 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
393 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
395 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
397 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
399 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
401 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
412 #define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
414 #define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
416 #define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
418 #define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
420 #define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
422 #define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
424 #define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
426 #define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
437 #define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
439 #define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
441 #define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
443 #define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
445 #define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
447 #define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
449 #define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
451 #define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
465 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
467 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
469 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
471 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
473 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
475 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
477 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
479 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
492 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
494 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
496 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
498 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
500 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
502 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
504 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
506 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
519 #define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
521 #define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
523 #define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
525 #define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
527 #define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
529 #define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
531 #define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
533 #define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
546 #define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
548 #define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
550 #define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
552 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
554 #define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
556 #define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
558 #define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
560 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
573 #define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
575 #define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
577 #define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
579 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
581 #define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
583 #define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
585 #define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
587 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
600 struct ALT_RSTMGR_STAT_s
602 uint32_t porvoltrst : 1;
603 uint32_t nporpinrst : 1;
604 uint32_t fpgacoldrst : 1;
605 uint32_t configiocoldrst : 1;
606 uint32_t swcoldrst : 1;
608 uint32_t nrstpinrst : 1;
609 uint32_t fpgawarmrst : 1;
610 uint32_t swwarmrst : 1;
612 uint32_t mpuwd0rst : 1;
613 uint32_t mpuwd1rst : 1;
614 uint32_t l4wd0rst : 1;
615 uint32_t l4wd1rst : 1;
617 uint32_t fpgadbgrst : 1;
618 uint32_t cdbgreqrst : 1;
620 uint32_t sdrselfreftimeout : 1;
621 uint32_t fpgamgrhstimeout : 1;
622 uint32_t scanhstimeout : 1;
623 uint32_t fpgahstimeout : 1;
624 uint32_t etrstalltimeout : 1;
629 typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
633 #define ALT_RSTMGR_STAT_OFST 0x0
687 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
689 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
691 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
693 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
695 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
697 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
699 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
701 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
713 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
715 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
717 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
719 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
721 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
723 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
725 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
727 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
742 #define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
744 #define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
746 #define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
748 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
750 #define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
752 #define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
754 #define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
756 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
773 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
775 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
777 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
779 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
781 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
783 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
785 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
787 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
800 #define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
802 #define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
804 #define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
806 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
808 #define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
810 #define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
812 #define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
814 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
835 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
837 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
839 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
841 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
843 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
845 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
847 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
849 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
865 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
867 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
869 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
871 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
873 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
875 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
877 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
879 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
891 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
893 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
895 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
897 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
899 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
901 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
903 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
905 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
926 #define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
928 #define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
930 #define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
932 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
934 #define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
936 #define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
938 #define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
940 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
956 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
958 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
960 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
962 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
964 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
966 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
968 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
970 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
982 #define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
984 #define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
986 #define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
988 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
990 #define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
992 #define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
994 #define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
996 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
1014 #define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
1016 #define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
1018 #define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
1020 #define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
1022 #define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
1024 #define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
1026 #define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
1028 #define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
1043 #define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
1045 #define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
1047 #define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
1049 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
1051 #define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
1053 #define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
1055 #define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
1057 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
1069 #define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
1071 #define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
1073 #define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
1075 #define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
1077 #define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
1079 #define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
1081 #define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
1083 #define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
1102 #define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
1104 #define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
1106 #define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
1108 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
1110 #define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
1112 #define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
1114 #define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
1116 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
1132 #define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
1134 #define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
1136 #define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
1138 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
1140 #define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
1142 #define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
1144 #define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
1146 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
1158 #define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
1160 #define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
1162 #define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
1164 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
1166 #define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
1168 #define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
1170 #define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
1172 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
1187 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
1189 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
1191 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
1193 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
1195 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
1197 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
1199 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
1201 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
1203 #ifndef __ASSEMBLY__
1214 struct ALT_RSTMGR_CTL_s
1216 uint32_t swcoldrstreq : 1;
1217 uint32_t swwarmrstreq : 1;
1219 uint32_t sdrselfrefen : 1;
1220 uint32_t sdrselfrefreq : 1;
1221 const uint32_t sdrselfreqack : 1;
1223 uint32_t fpgamgrhsen : 1;
1224 uint32_t fpgamgrhsreq : 1;
1225 const uint32_t fpgamgrhsack : 1;
1227 uint32_t scanmgrhsen : 1;
1228 uint32_t scanmgrhsreq : 1;
1229 const uint32_t scanmgrhsack : 1;
1231 uint32_t fpgahsen : 1;
1232 uint32_t fpgahsreq : 1;
1233 const uint32_t fpgahsack : 1;
1235 uint32_t etrstallen : 1;
1236 uint32_t etrstallreq : 1;
1237 const uint32_t etrstallack : 1;
1238 uint32_t etrstallwarmrst : 1;
1243 typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1247 #define ALT_RSTMGR_CTL_OFST 0x4
1277 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
1279 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
1281 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1283 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
1285 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
1287 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1289 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
1291 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
1304 #define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
1306 #define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
1308 #define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1310 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
1312 #define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
1314 #define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1316 #define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
1318 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
1320 #ifndef __ASSEMBLY__
1331 struct ALT_RSTMGR_COUNTS_s
1333 uint32_t warmrstcycles : 8;
1334 uint32_t nrstcnt : 20;
1339 typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t;
1343 #define ALT_RSTMGR_COUNTS_OFST 0x8
1394 #define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1396 #define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1398 #define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1400 #define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
1402 #define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
1404 #define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
1406 #define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
1408 #define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
1426 #define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
1428 #define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
1430 #define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
1432 #define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
1434 #define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
1436 #define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
1438 #define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
1440 #define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
1451 #define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
1453 #define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
1455 #define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
1457 #define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
1459 #define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
1461 #define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
1463 #define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
1465 #define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
1478 #define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
1480 #define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
1482 #define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
1484 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
1486 #define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
1488 #define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
1490 #define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
1492 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
1503 #define ALT_RSTMGR_MPUMODRST_L2_LSB 4
1505 #define ALT_RSTMGR_MPUMODRST_L2_MSB 4
1507 #define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
1509 #define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
1511 #define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
1513 #define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
1515 #define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
1517 #define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
1519 #ifndef __ASSEMBLY__
1530 struct ALT_RSTMGR_MPUMODRST_s
1535 uint32_t scuper : 1;
1541 typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
1545 #define ALT_RSTMGR_MPUMODRST_OFST 0x10
1615 #define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
1617 #define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
1619 #define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
1621 #define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
1623 #define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
1625 #define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
1627 #define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1629 #define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1640 #define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
1642 #define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
1644 #define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
1646 #define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
1648 #define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
1650 #define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
1652 #define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1654 #define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1665 #define ALT_RSTMGR_PERMODRST_USB0_LSB 2
1667 #define ALT_RSTMGR_PERMODRST_USB0_MSB 2
1669 #define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
1671 #define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
1673 #define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
1675 #define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
1677 #define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
1679 #define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
1690 #define ALT_RSTMGR_PERMODRST_USB1_LSB 3
1692 #define ALT_RSTMGR_PERMODRST_USB1_MSB 3
1694 #define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
1696 #define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
1698 #define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
1700 #define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
1702 #define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
1704 #define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
1715 #define ALT_RSTMGR_PERMODRST_NAND_LSB 4
1717 #define ALT_RSTMGR_PERMODRST_NAND_MSB 4
1719 #define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
1721 #define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
1723 #define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
1725 #define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
1727 #define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
1729 #define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
1740 #define ALT_RSTMGR_PERMODRST_QSPI_LSB 5
1742 #define ALT_RSTMGR_PERMODRST_QSPI_MSB 5
1744 #define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
1746 #define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
1748 #define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
1750 #define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
1752 #define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
1754 #define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
1765 #define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
1767 #define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
1769 #define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
1771 #define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
1773 #define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
1775 #define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
1777 #define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
1779 #define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
1790 #define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
1792 #define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
1794 #define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
1796 #define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
1798 #define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
1800 #define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
1802 #define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
1804 #define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
1815 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
1817 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
1819 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
1821 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
1823 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
1825 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
1827 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
1829 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
1840 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
1842 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
1844 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
1846 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
1848 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
1850 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
1852 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
1854 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
1865 #define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
1867 #define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
1869 #define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
1871 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
1873 #define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
1875 #define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
1877 #define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
1879 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
1890 #define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
1892 #define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
1894 #define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
1896 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
1898 #define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
1900 #define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
1902 #define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
1904 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
1915 #define ALT_RSTMGR_PERMODRST_I2C0_LSB 12
1917 #define ALT_RSTMGR_PERMODRST_I2C0_MSB 12
1919 #define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
1921 #define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
1923 #define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
1925 #define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
1927 #define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
1929 #define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
1940 #define ALT_RSTMGR_PERMODRST_I2C1_LSB 13
1942 #define ALT_RSTMGR_PERMODRST_I2C1_MSB 13
1944 #define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
1946 #define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
1948 #define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
1950 #define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
1952 #define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
1954 #define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
1965 #define ALT_RSTMGR_PERMODRST_I2C2_LSB 14
1967 #define ALT_RSTMGR_PERMODRST_I2C2_MSB 14
1969 #define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
1971 #define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
1973 #define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
1975 #define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
1977 #define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
1979 #define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
1990 #define ALT_RSTMGR_PERMODRST_I2C3_LSB 15
1992 #define ALT_RSTMGR_PERMODRST_I2C3_MSB 15
1994 #define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
1996 #define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
1998 #define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
2000 #define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
2002 #define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
2004 #define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
2015 #define ALT_RSTMGR_PERMODRST_UART0_LSB 16
2017 #define ALT_RSTMGR_PERMODRST_UART0_MSB 16
2019 #define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
2021 #define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
2023 #define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
2025 #define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
2027 #define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
2029 #define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
2040 #define ALT_RSTMGR_PERMODRST_UART1_LSB 17
2042 #define ALT_RSTMGR_PERMODRST_UART1_MSB 17
2044 #define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
2046 #define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
2048 #define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
2050 #define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
2052 #define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
2054 #define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
2065 #define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
2067 #define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
2069 #define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
2071 #define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
2073 #define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
2075 #define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
2077 #define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
2079 #define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
2090 #define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
2092 #define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
2094 #define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
2096 #define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
2098 #define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
2100 #define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
2102 #define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
2104 #define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
2115 #define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
2117 #define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
2119 #define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
2121 #define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
2123 #define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
2125 #define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
2127 #define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
2129 #define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
2140 #define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
2142 #define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
2144 #define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
2146 #define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
2148 #define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
2150 #define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
2152 #define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
2154 #define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
2165 #define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
2167 #define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
2169 #define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
2171 #define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
2173 #define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
2175 #define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
2177 #define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
2179 #define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
2192 #define ALT_RSTMGR_PERMODRST_CAN0_LSB 23
2194 #define ALT_RSTMGR_PERMODRST_CAN0_MSB 23
2196 #define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
2198 #define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
2200 #define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
2202 #define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
2204 #define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
2206 #define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
2219 #define ALT_RSTMGR_PERMODRST_CAN1_LSB 24
2221 #define ALT_RSTMGR_PERMODRST_CAN1_MSB 24
2223 #define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
2225 #define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
2227 #define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
2229 #define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
2231 #define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
2233 #define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
2244 #define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
2246 #define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
2248 #define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
2250 #define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
2252 #define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
2254 #define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
2256 #define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
2258 #define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
2269 #define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
2271 #define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
2273 #define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
2275 #define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
2277 #define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
2279 #define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
2281 #define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
2283 #define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
2294 #define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
2296 #define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
2298 #define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
2300 #define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
2302 #define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
2304 #define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
2306 #define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
2308 #define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
2319 #define ALT_RSTMGR_PERMODRST_DMA_LSB 28
2321 #define ALT_RSTMGR_PERMODRST_DMA_MSB 28
2323 #define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
2325 #define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
2327 #define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
2329 #define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
2331 #define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
2333 #define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
2344 #define ALT_RSTMGR_PERMODRST_SDR_LSB 29
2346 #define ALT_RSTMGR_PERMODRST_SDR_MSB 29
2348 #define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
2350 #define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
2352 #define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
2354 #define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
2356 #define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
2358 #define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
2360 #ifndef __ASSEMBLY__
2371 struct ALT_RSTMGR_PERMODRST_s
2381 uint32_t osc1timer0 : 1;
2382 uint32_t osc1timer1 : 1;
2383 uint32_t sptimer0 : 1;
2384 uint32_t sptimer1 : 1;
2407 typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t;
2411 #define ALT_RSTMGR_PERMODRST_OFST 0x14
2460 #define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
2462 #define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
2464 #define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
2466 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
2468 #define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
2470 #define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
2472 #define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
2474 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
2486 #define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
2488 #define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
2490 #define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
2492 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
2494 #define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
2496 #define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
2498 #define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
2500 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
2512 #define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
2514 #define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
2516 #define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
2518 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
2520 #define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
2522 #define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
2524 #define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
2526 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
2538 #define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
2540 #define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
2542 #define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
2544 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
2546 #define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
2548 #define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
2550 #define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
2552 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
2564 #define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
2566 #define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
2568 #define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
2570 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
2572 #define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
2574 #define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
2576 #define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
2578 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
2590 #define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
2592 #define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
2594 #define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
2596 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
2598 #define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
2600 #define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
2602 #define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
2604 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
2616 #define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
2618 #define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
2620 #define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
2622 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
2624 #define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
2626 #define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
2628 #define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
2630 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
2642 #define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
2644 #define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
2646 #define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
2648 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
2650 #define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
2652 #define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
2654 #define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
2656 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
2658 #ifndef __ASSEMBLY__
2669 struct ALT_RSTMGR_PER2MODRST_s
2671 uint32_t dmaif0 : 1;
2672 uint32_t dmaif1 : 1;
2673 uint32_t dmaif2 : 1;
2674 uint32_t dmaif3 : 1;
2675 uint32_t dmaif4 : 1;
2676 uint32_t dmaif5 : 1;
2677 uint32_t dmaif6 : 1;
2678 uint32_t dmaif7 : 1;
2683 typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t;
2687 #define ALT_RSTMGR_PER2MODRST_OFST 0x18
2730 #define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
2732 #define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
2734 #define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
2736 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
2738 #define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
2740 #define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
2742 #define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
2744 #define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
2755 #define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
2757 #define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
2759 #define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
2761 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
2763 #define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
2765 #define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
2767 #define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
2769 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
2780 #define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
2782 #define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
2784 #define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
2786 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
2788 #define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
2790 #define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
2792 #define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
2794 #define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
2796 #ifndef __ASSEMBLY__
2807 struct ALT_RSTMGR_BRGMODRST_s
2809 uint32_t hps2fpga : 1;
2810 uint32_t lwhps2fpga : 1;
2811 uint32_t fpga2hps : 1;
2816 typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
2820 #define ALT_RSTMGR_BRGMODRST_OFST 0x1c
2872 #define ALT_RSTMGR_MISCMODRST_ROM_LSB 0
2874 #define ALT_RSTMGR_MISCMODRST_ROM_MSB 0
2876 #define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
2878 #define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
2880 #define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
2882 #define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
2884 #define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
2886 #define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
2897 #define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
2899 #define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
2901 #define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
2903 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
2905 #define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
2907 #define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
2909 #define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
2911 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
2923 #define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
2925 #define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
2927 #define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
2929 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
2931 #define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
2933 #define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
2935 #define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
2937 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
2949 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
2951 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
2953 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
2955 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
2957 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
2959 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
2961 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
2963 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
2974 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
2976 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
2978 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
2980 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
2982 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
2984 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
2986 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
2988 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
2999 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
3001 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
3003 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
3005 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
3007 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
3009 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
3011 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
3013 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
3025 #define ALT_RSTMGR_MISCMODRST_S2F_LSB 6
3027 #define ALT_RSTMGR_MISCMODRST_S2F_MSB 6
3029 #define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
3031 #define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
3033 #define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
3035 #define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
3037 #define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
3039 #define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
3051 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
3053 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
3055 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
3057 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
3059 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
3061 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
3063 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
3065 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
3076 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
3078 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
3080 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
3082 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
3084 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
3086 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
3088 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
3090 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
3101 #define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
3103 #define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
3105 #define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
3107 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
3109 #define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
3111 #define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
3113 #define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
3115 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
3126 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
3128 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
3130 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
3132 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
3134 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
3136 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
3138 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
3140 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
3151 #define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
3153 #define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
3155 #define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
3157 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
3159 #define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
3161 #define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
3163 #define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
3165 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
3176 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
3178 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
3180 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
3182 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
3184 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
3186 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
3188 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
3190 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
3201 #define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
3203 #define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
3205 #define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
3207 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
3209 #define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
3211 #define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
3213 #define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
3215 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
3226 #define ALT_RSTMGR_MISCMODRST_DBG_LSB 14
3228 #define ALT_RSTMGR_MISCMODRST_DBG_MSB 14
3230 #define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
3232 #define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
3234 #define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
3236 #define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
3238 #define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
3240 #define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
3252 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
3254 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
3256 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
3258 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
3260 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
3262 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
3264 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
3266 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
3277 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
3279 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
3281 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
3283 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
3285 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
3287 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
3289 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
3291 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
3293 #ifndef __ASSEMBLY__
3304 struct ALT_RSTMGR_MISCMODRST_s
3308 uint32_t sysmgr : 1;
3309 uint32_t sysmgrcold : 1;
3310 uint32_t fpgamgr : 1;
3311 uint32_t acpidmap : 1;
3313 uint32_t s2fcold : 1;
3314 uint32_t nrstpin : 1;
3315 uint32_t timestampcold : 1;
3316 uint32_t clkmgrcold : 1;
3317 uint32_t scanmgr : 1;
3318 uint32_t frzctrlcold : 1;
3319 uint32_t sysdbg : 1;
3321 uint32_t tapcold : 1;
3322 uint32_t sdrcold : 1;
3327 typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t;
3331 #define ALT_RSTMGR_MISCMODRST_OFST 0x20
3333 #ifndef __ASSEMBLY__
3346 ALT_RSTMGR_STAT_t stat;
3347 ALT_RSTMGR_CTL_t ctrl;
3348 ALT_RSTMGR_COUNTS_t counts;
3349 volatile uint32_t _pad_0xc_0xf;
3350 ALT_RSTMGR_MPUMODRST_t mpumodrst;
3351 ALT_RSTMGR_PERMODRST_t permodrst;
3352 ALT_RSTMGR_PER2MODRST_t per2modrst;
3353 ALT_RSTMGR_BRGMODRST_t brgmodrst;
3354 ALT_RSTMGR_MISCMODRST_t miscmodrst;
3355 volatile uint32_t _pad_0x24_0x100[55];
3359 typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
3361 struct ALT_RSTMGR_raw_s
3363 volatile uint32_t stat;
3364 volatile uint32_t ctrl;
3365 volatile uint32_t counts;
3366 uint32_t _pad_0xc_0xf;
3367 volatile uint32_t mpumodrst;
3368 volatile uint32_t permodrst;
3369 volatile uint32_t per2modrst;
3370 volatile uint32_t brgmodrst;
3371 volatile uint32_t miscmodrst;
3372 uint32_t _pad_0x24_0x100[55];
3376 typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;