Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_rstmgr.h
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32 
33 /* Altera - ALT_RSTMGR */
34 
35 #ifndef __ALTERA_ALT_RSTMGR_H__
36 #define __ALTERA_ALT_RSTMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : Reset Manager Module - ALT_RSTMGR
45  * Reset Manager Module
46  *
47  * Registers in the Reset Manager module
48  *
49  */
50 /*
51  * Register : Status Register - stat
52  *
53  * The STAT register contains bits that indicate the reset source or a timeout
54  * event. For reset sources, a field is 1 if its associated reset requester caused
55  * the reset. For timeout events, a field is 1 if its associated timeout occured as
56  * part of a hardware sequenced warm/debug reset.
57  *
58  * Software clears bits by writing them with a value of 1. Writes to bits with a
59  * value of 0 are ignored.
60  *
61  * After a cold reset is complete, all bits are reset to their reset value except
62  * for the bit(s) that indicate the source of the cold reset. If multiple cold
63  * reset requests overlap with each other, the source de-asserts the request last
64  * will be logged. The other reset request source(s) de-assert the request in the
65  * same cycle will also be logged, the rest of the fields are reset to default
66  * value of 0.
67  *
68  * After a warm reset is complete, the bit(s) that indicate the source of the warm
69  * reset are set to 1. A warm reset doesn't clear any of the bits in the STAT
70  * register; these bits must be cleared by software writing the STAT register.
71  *
72  * Register Layout
73  *
74  * Bits | Access | Reset | Description
75  * :--------|:-------|:------|:-------------------------------------
76  * [0] | RW | 0x0 | Power-On Voltage Detector Cold Reset
77  * [1] | RW | 0x0 | nPOR Pin Cold Reset
78  * [2] | RW | 0x0 | FPGA Core Cold Reset
79  * [3] | RW | 0x0 | CONFIG_IO Cold Reset
80  * [4] | RW | 0x0 | Software Cold Reset
81  * [7:5] | ??? | 0x0 | *UNDEFINED*
82  * [8] | RW | 0x0 | nRST Pin Warm Reset
83  * [9] | RW | 0x0 | FPGA Core Warm Reset
84  * [10] | RW | 0x0 | Software Warm Reset
85  * [11] | ??? | 0x0 | *UNDEFINED*
86  * [12] | RW | 0x0 | MPU Watchdog 0 Warm Reset
87  * [13] | RW | 0x0 | MPU Watchdog 1 Warm Reset
88  * [14] | RW | 0x0 | L4 Watchdog 0 Warm Reset
89  * [15] | RW | 0x0 | L4 Watchdog 1 Warm Reset
90  * [17:16] | ??? | 0x0 | *UNDEFINED*
91  * [18] | RW | 0x0 | FPGA Core Debug Reset
92  * [19] | RW | 0x0 | DAP Debug Reset
93  * [23:20] | ??? | 0x0 | *UNDEFINED*
94  * [24] | RW | 0x0 | SDRAM Self-Refresh Timeout
95  * [25] | RW | 0x0 | FPGA manager handshake Timeout
96  * [26] | RW | 0x0 | SCAN manager handshake Timeout
97  * [27] | RW | 0x0 | FPGA handshake Timeout
98  * [28] | RW | 0x0 | ETR Stall Timeout
99  * [31:29] | ??? | 0x0 | *UNDEFINED*
100  *
101  */
102 /*
103  * Field : Power-On Voltage Detector Cold Reset - porvoltrst
104  *
105  * Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)
106  *
107  * Field Access Macros:
108  *
109  */
110 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
111 #define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
112 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
113 #define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
114 /* The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
115 #define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
116 /* The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
117 #define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
118 /* The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value. */
119 #define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
120 /* The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field. */
121 #define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
122 /* Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register. */
123 #define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
124 /* Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register. */
125 #define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
126 
127 /*
128  * Field : nPOR Pin Cold Reset - nporpinrst
129  *
130  * nPOR pin triggered a cold reset (por_pin_req = 1)
131  *
132  * Field Access Macros:
133  *
134  */
135 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
136 #define ALT_RSTMGR_STAT_NPORPINRST_LSB 1
137 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field. */
138 #define ALT_RSTMGR_STAT_NPORPINRST_MSB 1
139 /* The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field. */
140 #define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
141 /* The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value. */
142 #define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
143 /* The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value. */
144 #define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
145 /* The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field. */
146 #define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
147 /* Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register. */
148 #define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
149 /* Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register. */
150 #define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
151 
152 /*
153  * Field : FPGA Core Cold Reset - fpgacoldrst
154  *
155  * FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)
156  *
157  * Field Access Macros:
158  *
159  */
160 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
161 #define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
162 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
163 #define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
164 /* The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
165 #define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
166 /* The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
167 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
168 /* The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value. */
169 #define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
170 /* The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field. */
171 #define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
172 /* Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register. */
173 #define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
174 /* Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register. */
175 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
176 
177 /*
178  * Field : CONFIG_IO Cold Reset - configiocoldrst
179  *
180  * FPGA entered CONFIG_IO mode and a triggered a cold reset
181  *
182  * Field Access Macros:
183  *
184  */
185 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
186 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
187 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
188 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
189 /* The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
190 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
191 /* The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
192 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
193 /* The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value. */
194 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
195 /* The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field. */
196 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
197 /* Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register. */
198 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
199 /* Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register. */
200 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
201 
202 /*
203  * Field : Software Cold Reset - swcoldrst
204  *
205  * Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset
206  *
207  * Field Access Macros:
208  *
209  */
210 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
211 #define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
212 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
213 #define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
214 /* The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
215 #define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
216 /* The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
217 #define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
218 /* The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value. */
219 #define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
220 /* The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field. */
221 #define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
222 /* Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register. */
223 #define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
224 /* Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register. */
225 #define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
226 
227 /*
228  * Field : nRST Pin Warm Reset - nrstpinrst
229  *
230  * nRST pin triggered a hardware sequenced warm reset
231  *
232  * Field Access Macros:
233  *
234  */
235 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
236 #define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
237 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
238 #define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
239 /* The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
240 #define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
241 /* The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
242 #define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
243 /* The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value. */
244 #define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
245 /* The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field. */
246 #define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
247 /* Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register. */
248 #define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
249 /* Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register. */
250 #define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
251 
252 /*
253  * Field : FPGA Core Warm Reset - fpgawarmrst
254  *
255  * FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)
256  *
257  * Field Access Macros:
258  *
259  */
260 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
261 #define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
262 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
263 #define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
264 /* The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
265 #define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
266 /* The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
267 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
268 /* The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value. */
269 #define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
270 /* The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field. */
271 #define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
272 /* Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register. */
273 #define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
274 /* Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register. */
275 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
276 
277 /*
278  * Field : Software Warm Reset - swwarmrst
279  *
280  * Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm
281  * reset
282  *
283  * Field Access Macros:
284  *
285  */
286 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
287 #define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
288 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field. */
289 #define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
290 /* The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field. */
291 #define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
292 /* The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value. */
293 #define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
294 /* The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value. */
295 #define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
296 /* The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field. */
297 #define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
298 /* Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register. */
299 #define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
300 /* Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register. */
301 #define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
302 
303 /*
304  * Field : MPU Watchdog 0 Warm Reset - mpuwd0rst
305  *
306  * MPU Watchdog 0 triggered a hardware sequenced warm reset
307  *
308  * Field Access Macros:
309  *
310  */
311 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
312 #define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
313 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
314 #define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
315 /* The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
316 #define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
317 /* The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
318 #define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
319 /* The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value. */
320 #define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
321 /* The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field. */
322 #define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
323 /* Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register. */
324 #define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
325 /* Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register. */
326 #define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
327 
328 /*
329  * Field : MPU Watchdog 1 Warm Reset - mpuwd1rst
330  *
331  * MPU Watchdog 1 triggered a hardware sequenced warm reset
332  *
333  * Field Access Macros:
334  *
335  */
336 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
337 #define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
338 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
339 #define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
340 /* The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
341 #define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
342 /* The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
343 #define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
344 /* The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value. */
345 #define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
346 /* The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field. */
347 #define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
348 /* Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register. */
349 #define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
350 /* Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register. */
351 #define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
352 
353 /*
354  * Field : L4 Watchdog 0 Warm Reset - l4wd0rst
355  *
356  * L4 Watchdog 0 triggered a hardware sequenced warm reset
357  *
358  * Field Access Macros:
359  *
360  */
361 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
362 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 14
363 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field. */
364 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 14
365 /* The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field. */
366 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
367 /* The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value. */
368 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
369 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value. */
370 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
371 /* The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field. */
372 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
373 /* Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register. */
374 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
375 /* Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register. */
376 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
377 
378 /*
379  * Field : L4 Watchdog 1 Warm Reset - l4wd1rst
380  *
381  * L4 Watchdog 1 triggered a hardware sequenced warm reset
382  *
383  * Field Access Macros:
384  *
385  */
386 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
387 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 15
388 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field. */
389 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 15
390 /* The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field. */
391 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
392 /* The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value. */
393 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
394 /* The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value. */
395 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
396 /* The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field. */
397 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
398 /* Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register. */
399 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
400 /* Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register. */
401 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
402 
403 /*
404  * Field : FPGA Core Debug Reset - fpgadbgrst
405  *
406  * FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)
407  *
408  * Field Access Macros:
409  *
410  */
411 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
412 #define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
413 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
414 #define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
415 /* The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
416 #define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
417 /* The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
418 #define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
419 /* The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value. */
420 #define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
421 /* The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field. */
422 #define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
423 /* Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register. */
424 #define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
425 /* Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register. */
426 #define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
427 
428 /*
429  * Field : DAP Debug Reset - cdbgreqrst
430  *
431  * DAP triggered debug reset
432  *
433  * Field Access Macros:
434  *
435  */
436 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
437 #define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
438 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
439 #define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
440 /* The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
441 #define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
442 /* The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
443 #define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
444 /* The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value. */
445 #define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
446 /* The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field. */
447 #define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
448 /* Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register. */
449 #define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
450 /* Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register. */
451 #define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
452 
453 /*
454  * Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout
455  *
456  * A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to
457  * put the SDRAM devices into self-refresh mode before starting a hardware
458  * sequenced warm reset timed-out and the Reset Manager had to proceed with the
459  * warm reset anyway.
460  *
461  * Field Access Macros:
462  *
463  */
464 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
465 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
466 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
467 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
468 /* The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
469 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
470 /* The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
471 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
472 /* The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value. */
473 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
474 /* The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field. */
475 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
476 /* Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register. */
477 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
478 /* Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register. */
479 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
480 
481 /*
482  * Field : FPGA manager handshake Timeout - fpgamgrhstimeout
483  *
484  * A 1 indicates that Reset Manager's request to the FPGA manager to stop driving
485  * configuration clock to FPGA CB before starting a hardware sequenced warm reset
486  * timed-out and the Reset Manager had to proceed with the warm reset anyway.
487  *
488  * Field Access Macros:
489  *
490  */
491 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
492 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
493 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
494 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
495 /* The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
496 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
497 /* The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
498 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
499 /* The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value. */
500 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
501 /* The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field. */
502 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
503 /* Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register. */
504 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
505 /* Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register. */
506 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
507 
508 /*
509  * Field : SCAN manager handshake Timeout - scanhstimeout
510  *
511  * A 1 indicates that Reset Manager's request to the SCAN manager to stop driving
512  * JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out
513  * and the Reset Manager had to proceed with the warm reset anyway.
514  *
515  * Field Access Macros:
516  *
517  */
518 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
519 #define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
520 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
521 #define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
522 /* The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
523 #define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
524 /* The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
525 #define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
526 /* The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value. */
527 #define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
528 /* The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field. */
529 #define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
530 /* Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register. */
531 #define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
532 /* Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register. */
533 #define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
534 
535 /*
536  * Field : FPGA handshake Timeout - fpgahstimeout
537  *
538  * A 1 indicates that Reset Manager's handshake request to FPGA before starting a
539  * hardware sequenced warm reset timed-out and the Reset Manager had to proceed
540  * with the warm reset anyway.
541  *
542  * Field Access Macros:
543  *
544  */
545 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
546 #define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
547 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
548 #define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
549 /* The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
550 #define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
551 /* The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
552 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
553 /* The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value. */
554 #define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
555 /* The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field. */
556 #define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
557 /* Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register. */
558 #define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
559 /* Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register. */
560 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
561 
562 /*
563  * Field : ETR Stall Timeout - etrstalltimeout
564  *
565  * A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to
566  * stall its AXI master port before starting a hardware sequenced warm reset timed-
567  * out and the Reset Manager had to proceed with the warm reset anyway.
568  *
569  * Field Access Macros:
570  *
571  */
572 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
573 #define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
574 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
575 #define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
576 /* The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
577 #define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
578 /* The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
579 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
580 /* The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value. */
581 #define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
582 /* The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field. */
583 #define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
584 /* Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register. */
585 #define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
586 /* Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register. */
587 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
588 
589 #ifndef __ASSEMBLY__
590 /*
591  * WARNING: The C register and register group struct declarations are provided for
592  * convenience and illustrative purposes. They should, however, be used with
593  * caution as the C language standard provides no guarantees about the alignment or
594  * atomicity of device memory accesses. The recommended practice for writing
595  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
596  * alt_write_word() functions.
597  *
598  * The struct declaration for register ALT_RSTMGR_STAT.
599  */
600 struct ALT_RSTMGR_STAT_s
601 {
602  uint32_t porvoltrst : 1; /* Power-On Voltage Detector Cold Reset */
603  uint32_t nporpinrst : 1; /* nPOR Pin Cold Reset */
604  uint32_t fpgacoldrst : 1; /* FPGA Core Cold Reset */
605  uint32_t configiocoldrst : 1; /* CONFIG_IO Cold Reset */
606  uint32_t swcoldrst : 1; /* Software Cold Reset */
607  uint32_t : 3; /* *UNDEFINED* */
608  uint32_t nrstpinrst : 1; /* nRST Pin Warm Reset */
609  uint32_t fpgawarmrst : 1; /* FPGA Core Warm Reset */
610  uint32_t swwarmrst : 1; /* Software Warm Reset */
611  uint32_t : 1; /* *UNDEFINED* */
612  uint32_t mpuwd0rst : 1; /* MPU Watchdog 0 Warm Reset */
613  uint32_t mpuwd1rst : 1; /* MPU Watchdog 1 Warm Reset */
614  uint32_t l4wd0rst : 1; /* L4 Watchdog 0 Warm Reset */
615  uint32_t l4wd1rst : 1; /* L4 Watchdog 1 Warm Reset */
616  uint32_t : 2; /* *UNDEFINED* */
617  uint32_t fpgadbgrst : 1; /* FPGA Core Debug Reset */
618  uint32_t cdbgreqrst : 1; /* DAP Debug Reset */
619  uint32_t : 4; /* *UNDEFINED* */
620  uint32_t sdrselfreftimeout : 1; /* SDRAM Self-Refresh Timeout */
621  uint32_t fpgamgrhstimeout : 1; /* FPGA manager handshake Timeout */
622  uint32_t scanhstimeout : 1; /* SCAN manager handshake Timeout */
623  uint32_t fpgahstimeout : 1; /* FPGA handshake Timeout */
624  uint32_t etrstalltimeout : 1; /* ETR Stall Timeout */
625  uint32_t : 3; /* *UNDEFINED* */
626 };
627 
628 /* The typedef declaration for register ALT_RSTMGR_STAT. */
629 typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
630 #endif /* __ASSEMBLY__ */
631 
632 /* The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component. */
633 #define ALT_RSTMGR_STAT_OFST 0x0
634 
635 /*
636  * Register : Control Register - ctrl
637  *
638  * The CTRL register is used by software to control reset behavior.It includes
639  * fields for software to initiate the cold and warm reset, enable hardware
640  * handshake with other modules before warm reset, and perform software handshake.
641  * The software handshake sequence must match the hardware sequence. Software
642  * mustde-assert the handshake request after asserting warm reset and before de-
643  * assert the warm reset.
644  *
645  * Fields are only reset by a cold reset.
646  *
647  * Register Layout
648  *
649  * Bits | Access | Reset | Description
650  * :--------|:-------|:--------|:---------------------------------------------------
651  * [0] | RW | 0x0 | Software Cold Reset Request
652  * [1] | RW | 0x0 | Software Warm Reset Request
653  * [3:2] | ??? | 0x0 | *UNDEFINED*
654  * [4] | RW | 0x0 | SDRAM Self-Refresh Enable
655  * [5] | RW | 0x0 | SDRAM Self-Refresh Request
656  * [6] | R | 0x0 | SDRAM Self-Refresh Acknowledge
657  * [7] | ??? | 0x0 | *UNDEFINED*
658  * [8] | RW | 0x0 | FPGA Manager Handshake Enable
659  * [9] | RW | 0x0 | FPGA Manager Handshake Request
660  * [10] | R | Unknown | FPGA Manager Handshake Acknowledge
661  * [11] | ??? | 0x0 | *UNDEFINED*
662  * [12] | RW | 0x0 | SCAN Manager Handshake Enable
663  * [13] | RW | 0x0 | SCAN Manager Handshake Request
664  * [14] | R | Unknown | SCAN Manager Handshake Acknowledge
665  * [15] | ??? | 0x0 | *UNDEFINED*
666  * [16] | RW | 0x0 | FPGA Handshake Enable
667  * [17] | RW | 0x0 | FPGA Handshake Request
668  * [18] | R | Unknown | FPGA Handshake Acknowledge
669  * [19] | ??? | 0x0 | *UNDEFINED*
670  * [20] | RW | 0x1 | ETR (Embedded Trace Router) Stall Enable
671  * [21] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request
672  * [22] | R | 0x0 | ETR (Embedded Trace Router) Stall Acknowledge
673  * [23] | RW | 0x0 | ETR (Embedded Trace Router) Stall After Warm Reset
674  * [31:24] | ??? | 0x0 | *UNDEFINED*
675  *
676  */
677 /*
678  * Field : Software Cold Reset Request - swcoldrstreq
679  *
680  * This is a one-shot bit written by software to 1 to trigger a cold reset. It
681  * always reads the value 0.
682  *
683  * Field Access Macros:
684  *
685  */
686 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
687 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
688 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
689 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
690 /* The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
691 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
692 /* The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
693 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
694 /* The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value. */
695 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
696 /* The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field. */
697 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
698 /* Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register. */
699 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
700 /* Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register. */
701 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
702 
703 /*
704  * Field : Software Warm Reset Request - swwarmrstreq
705  *
706  * This is a one-shot bit written by software to 1 to trigger a hardware sequenced
707  * warm reset. It always reads the value 0.
708  *
709  * Field Access Macros:
710  *
711  */
712 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
713 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
714 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
715 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
716 /* The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
717 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
718 /* The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
719 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
720 /* The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value. */
721 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
722 /* The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field. */
723 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
724 /* Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register. */
725 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
726 /* Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register. */
727 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
728 
729 /*
730  * Field : SDRAM Self-Refresh Enable - sdrselfrefen
731  *
732  * This field controls whether the contents of SDRAM devices survive a hardware
733  * sequenced warm reset. If set to 1, the Reset Manager makes a request to the
734  * SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode
735  * before asserting warm reset signals. However, if SDRAM is already in warm reset,
736  * Handshake with SDRAM is not performed.
737  *
738  * Field Access Macros:
739  *
740  */
741 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
742 #define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
743 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
744 #define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
745 /* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
746 #define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
747 /* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
748 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
749 /* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value. */
750 #define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
751 /* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field. */
752 #define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
753 /* Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register. */
754 #define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
755 /* Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register. */
756 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
757 
758 /*
759  * Field : SDRAM Self-Refresh Request - sdrselfrefreq
760  *
761  * Software writes this field 1 to request to the SDRAM Controller Subsystem that
762  * it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM
763  * contents across a software warm reset.
764  *
765  * Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.
766  * Note that it is possible for the SDRAM Controller Subsystem to never assert
767  * SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
768  *
769  * Field Access Macros:
770  *
771  */
772 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
773 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
774 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
775 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
776 /* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
777 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
778 /* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
779 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
780 /* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value. */
781 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
782 /* The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field. */
783 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
784 /* Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register. */
785 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
786 /* Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register. */
787 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
788 
789 /*
790  * Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack
791  *
792  * This is the acknowlege for a SDRAM self-refresh mode request initiated by the
793  * SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put
794  * the SDRAM devices into self-refresh mode.
795  *
796  * Field Access Macros:
797  *
798  */
799 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
800 #define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
801 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
802 #define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
803 /* The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
804 #define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
805 /* The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
806 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
807 /* The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value. */
808 #define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
809 /* The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field. */
810 #define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
811 /* Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register. */
812 #define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
813 /* Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register. */
814 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
815 
816 /*
817  * Field : FPGA Manager Handshake Enable - fpgamgrhsen
818  *
819  * Enables a handshake between the Reset Manager and FPGA Manager before a warm
820  * reset. The handshake is used to warn the FPGA Manager that a warm reset it
821  * coming so it can prepare for it. When the FPGA Manager receives a warm reset
822  * handshake, the FPGA Manager drives its output clock to a quiescent state to
823  * avoid glitches.
824  *
825  * If set to 1, the Manager makes a request to the FPGA Managerbefore asserting
826  * warm reset signals. However if the FPGA Manager is already in warm reset, the
827  * handshake is skipped.
828  *
829  * If set to 0, the handshake is skipped.
830  *
831  * Field Access Macros:
832  *
833  */
834 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
835 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
836 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
837 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
838 /* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
839 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
840 /* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
841 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
842 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value. */
843 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
844 /* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field. */
845 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
846 /* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register. */
847 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
848 /* Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register. */
849 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
850 
851 /*
852  * Field : FPGA Manager Handshake Request - fpgamgrhsreq
853  *
854  * Software writes this field 1 to request to the FPGA Manager to idle its output
855  * clock.
856  *
857  * Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.
858  * Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so
859  * software should timeout in this case.
860  *
861  * Field Access Macros:
862  *
863  */
864 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
865 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
866 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
867 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
868 /* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
869 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
870 /* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
871 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
872 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value. */
873 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
874 /* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field. */
875 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
876 /* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register. */
877 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
878 /* Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register. */
879 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
880 
881 /*
882  * Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack
883  *
884  * This is the acknowlege (high active) that the FPGA manager has successfully
885  * idled its output clock.
886  *
887  * Field Access Macros:
888  *
889  */
890 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
891 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
892 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
893 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
894 /* The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field. */
895 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
896 /* The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
897 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
898 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value. */
899 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
900 /* The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN. */
901 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
902 /* Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register. */
903 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
904 /* Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register. */
905 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
906 
907 /*
908  * Field : SCAN Manager Handshake Enable - scanmgrhsen
909  *
910  * Enables a handshake between the Reset Manager and Scan Manager before a warm
911  * reset. The handshake is used to warn the Scan Manager that a warm reset it
912  * coming so it can prepare for it. When the Scan Manager receives a warm reset
913  * handshake, the Scan Manager drives its output clocks to a quiescent state to
914  * avoid glitches.
915  *
916  * If set to 1, the Reset Manager makes a request to the Scan Managerbefore
917  * asserting warm reset signals. However if the Scan Manager is already in warm
918  * reset, the handshake is skipped.
919  *
920  * If set to 0, the handshake is skipped.
921  *
922  * Field Access Macros:
923  *
924  */
925 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
926 #define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
927 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
928 #define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
929 /* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
930 #define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
931 /* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
932 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
933 /* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value. */
934 #define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
935 /* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field. */
936 #define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
937 /* Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register. */
938 #define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
939 /* Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register. */
940 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
941 
942 /*
943  * Field : SCAN Manager Handshake Request - scanmgrhsreq
944  *
945  * Software writes this field 1 to request to the SCAN manager to idle its output
946  * clocks.
947  *
948  * Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0.
949  * Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g.
950  * its input clock is disabled) so software should timeout in this case.
951  *
952  * Field Access Macros:
953  *
954  */
955 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
956 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
957 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
958 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
959 /* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
960 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
961 /* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
962 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
963 /* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value. */
964 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
965 /* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field. */
966 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
967 /* Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register. */
968 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
969 /* Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register. */
970 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
971 
972 /*
973  * Field : SCAN Manager Handshake Acknowledge - scanmgrhsack
974  *
975  * This is the acknowlege (high active) that the SCAN manager has successfully
976  * idled its output clocks.
977  *
978  * Field Access Macros:
979  *
980  */
981 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
982 #define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
983 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
984 #define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
985 /* The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field. */
986 #define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
987 /* The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
988 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
989 /* The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value. */
990 #define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
991 /* The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN. */
992 #define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
993 /* Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register. */
994 #define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
995 /* Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register. */
996 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
997 
998 /*
999  * Field : FPGA Handshake Enable - fpgahsen
1000  *
1001  * This field controls whether to perform handshake with FPGA before asserting warm
1002  * reset.
1003  *
1004  * If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm
1005  * reset signals. However if FPGA is already in warm reset state, the handshake is
1006  * not performed.
1007  *
1008  * If set to 0, the handshake is not performed
1009  *
1010  * Field Access Macros:
1011  *
1012  */
1013 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1014 #define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
1015 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1016 #define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
1017 /* The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1018 #define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
1019 /* The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1020 #define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
1021 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value. */
1022 #define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
1023 /* The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field. */
1024 #define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
1025 /* Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register. */
1026 #define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
1027 /* Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register. */
1028 #define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
1029 
1030 /*
1031  * Field : FPGA Handshake Request - fpgahsreq
1032  *
1033  * Software writes this field 1 to initiate handshake request to FPGA .
1034  *
1035  * Software waits for the FPGAHSACK to be active and then writes this field to 0.
1036  * Note that it is possible for the FPGA to never assert FPGAHSACK so software
1037  * should timeout in this case.
1038  *
1039  * Field Access Macros:
1040  *
1041  */
1042 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1043 #define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
1044 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1045 #define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
1046 /* The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1047 #define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
1048 /* The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1049 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
1050 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value. */
1051 #define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
1052 /* The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field. */
1053 #define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
1054 /* Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register. */
1055 #define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
1056 /* Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register. */
1057 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
1058 
1059 /*
1060  * Field : FPGA Handshake Acknowledge - fpgahsack
1061  *
1062  * This is the acknowlege (high active) that the FPGA handshake acknowledge has
1063  * been received by Reset Manager.
1064  *
1065  * Field Access Macros:
1066  *
1067  */
1068 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1069 #define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
1070 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1071 #define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
1072 /* The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field. */
1073 #define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
1074 /* The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1075 #define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
1076 /* The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value. */
1077 #define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
1078 /* The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN. */
1079 #define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
1080 /* Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register. */
1081 #define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
1082 /* Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register. */
1083 #define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
1084 
1085 /*
1086  * Field : ETR (Embedded Trace Router) Stall Enable - etrstallen
1087  *
1088  * This field controls whether the ETR is requested to idle its AXI master
1089  * interface (i.e. finish outstanding transactions and not initiate any more) to
1090  * the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager
1091  * makes a request to the ETR to stall its AXI master and waits for it to finish
1092  * any outstanding AXI transactions before a warm reset of the L3 Interconnect or a
1093  * debug reset of the ETR. This stalling is required because the debug logic
1094  * (including the ETR) is reset on a debug reset and the ETR AXI master is
1095  * connected to the L3 Interconnect which is reset on a warm reset and these resets
1096  * can happen independently.
1097  *
1098  * Field Access Macros:
1099  *
1100  */
1101 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1102 #define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
1103 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1104 #define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
1105 /* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1106 #define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
1107 /* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1108 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
1109 /* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value. */
1110 #define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
1111 /* The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field. */
1112 #define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
1113 /* Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register. */
1114 #define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
1115 /* Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register. */
1116 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
1117 
1118 /*
1119  * Field : ETR (Embedded Trace Router) Stall Request - etrstallreq
1120  *
1121  * Software writes this field 1 to request to the ETR that it stalls its AXI master
1122  * to the L3 Interconnect.
1123  *
1124  * Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.
1125  * Note that it is possible for the ETR to never assert ETRSTALLACK so software
1126  * should timeout if ETRSTALLACK is never asserted.
1127  *
1128  * Field Access Macros:
1129  *
1130  */
1131 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1132 #define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
1133 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1134 #define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
1135 /* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1136 #define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
1137 /* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1138 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
1139 /* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value. */
1140 #define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
1141 /* The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field. */
1142 #define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
1143 /* Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register. */
1144 #define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
1145 /* Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register. */
1146 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
1147 
1148 /*
1149  * Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack
1150  *
1151  * This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ
1152  * field. A 1 indicates that the ETR has stalled its AXI master
1153  *
1154  * Field Access Macros:
1155  *
1156  */
1157 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1158 #define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
1159 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1160 #define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
1161 /* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1162 #define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
1163 /* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1164 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
1165 /* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value. */
1166 #define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
1167 /* The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field. */
1168 #define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
1169 /* Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register. */
1170 #define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
1171 /* Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register. */
1172 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
1173 
1174 /*
1175  * Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst
1176  *
1177  * If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to
1178  * indicate that the stall of the ETR AXI master is pending. Hardware leaves the
1179  * ETR stalled until software clears this field by writing it with 1. Software must
1180  * only clear this field when it is ready to have the ETR AXI master start making
1181  * AXI requests to write trace data.
1182  *
1183  * Field Access Macros:
1184  *
1185  */
1186 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1187 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
1188 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1189 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
1190 /* The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1191 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
1192 /* The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1193 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
1194 /* The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value. */
1195 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
1196 /* The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field. */
1197 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
1198 /* Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register. */
1199 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
1200 /* Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register. */
1201 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
1202 
1203 #ifndef __ASSEMBLY__
1204 /*
1205  * WARNING: The C register and register group struct declarations are provided for
1206  * convenience and illustrative purposes. They should, however, be used with
1207  * caution as the C language standard provides no guarantees about the alignment or
1208  * atomicity of device memory accesses. The recommended practice for writing
1209  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1210  * alt_write_word() functions.
1211  *
1212  * The struct declaration for register ALT_RSTMGR_CTL.
1213  */
1214 struct ALT_RSTMGR_CTL_s
1215 {
1216  uint32_t swcoldrstreq : 1; /* Software Cold Reset Request */
1217  uint32_t swwarmrstreq : 1; /* Software Warm Reset Request */
1218  uint32_t : 2; /* *UNDEFINED* */
1219  uint32_t sdrselfrefen : 1; /* SDRAM Self-Refresh Enable */
1220  uint32_t sdrselfrefreq : 1; /* SDRAM Self-Refresh Request */
1221  const uint32_t sdrselfreqack : 1; /* SDRAM Self-Refresh Acknowledge */
1222  uint32_t : 1; /* *UNDEFINED* */
1223  uint32_t fpgamgrhsen : 1; /* FPGA Manager Handshake Enable */
1224  uint32_t fpgamgrhsreq : 1; /* FPGA Manager Handshake Request */
1225  const uint32_t fpgamgrhsack : 1; /* FPGA Manager Handshake Acknowledge */
1226  uint32_t : 1; /* *UNDEFINED* */
1227  uint32_t scanmgrhsen : 1; /* SCAN Manager Handshake Enable */
1228  uint32_t scanmgrhsreq : 1; /* SCAN Manager Handshake Request */
1229  const uint32_t scanmgrhsack : 1; /* SCAN Manager Handshake Acknowledge */
1230  uint32_t : 1; /* *UNDEFINED* */
1231  uint32_t fpgahsen : 1; /* FPGA Handshake Enable */
1232  uint32_t fpgahsreq : 1; /* FPGA Handshake Request */
1233  const uint32_t fpgahsack : 1; /* FPGA Handshake Acknowledge */
1234  uint32_t : 1; /* *UNDEFINED* */
1235  uint32_t etrstallen : 1; /* ETR (Embedded Trace Router) Stall Enable */
1236  uint32_t etrstallreq : 1; /* ETR (Embedded Trace Router) Stall Request */
1237  const uint32_t etrstallack : 1; /* ETR (Embedded Trace Router) Stall Acknowledge */
1238  uint32_t etrstallwarmrst : 1; /* ETR (Embedded Trace Router) Stall After Warm Reset */
1239  uint32_t : 8; /* *UNDEFINED* */
1240 };
1241 
1242 /* The typedef declaration for register ALT_RSTMGR_CTL. */
1243 typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1244 #endif /* __ASSEMBLY__ */
1245 
1246 /* The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component. */
1247 #define ALT_RSTMGR_CTL_OFST 0x4
1248 
1249 /*
1250  * Register : Reset Cycles Count Register - counts
1251  *
1252  * The COUNTS register is used by software to control reset behavior.It includes
1253  * fields for software to control the behavior of the warm reset and nRST pin.
1254  *
1255  * Fields are only reset by a cold reset.
1256  *
1257  * Register Layout
1258  *
1259  * Bits | Access | Reset | Description
1260  * :--------|:-------|:------|:-------------------------------
1261  * [7:0] | RW | 0x80 | Warm reset release delay count
1262  * [27:8] | RW | 0x800 | nRST Pin Count
1263  * [31:28] | ??? | 0x0 | *UNDEFINED*
1264  *
1265  */
1266 /*
1267  * Field : Warm reset release delay count - warmrstcycles
1268  *
1269  * On a warm reset, the Reset Manager releases the reset to the Clock Manager, and
1270  * then waits for the number of cycles specified in this register before releasing
1271  * the rest of the hardware controlled resets. Value must be greater than 16.
1272  *
1273  * Field Access Macros:
1274  *
1275  */
1276 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1277 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
1278 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1279 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
1280 /* The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1281 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1282 /* The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1283 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
1284 /* The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value. */
1285 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
1286 /* The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field. */
1287 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1288 /* Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register. */
1289 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
1290 /* Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register. */
1291 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
1292 
1293 /*
1294  * Field : nRST Pin Count - nrstcnt
1295  *
1296  * The Reset Manager pulls down the nRST pin on a warm reset for the number of
1297  * cycles specified in this register. A value of 0x0 prevents the Reset Manager
1298  * from pulling down the nRST pin.
1299  *
1300  * Field Access Macros:
1301  *
1302  */
1303 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1304 #define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
1305 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1306 #define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
1307 /* The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1308 #define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1309 /* The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1310 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
1311 /* The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value. */
1312 #define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
1313 /* The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field. */
1314 #define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1315 /* Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register. */
1316 #define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
1317 /* Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register. */
1318 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
1319 
1320 #ifndef __ASSEMBLY__
1321 /*
1322  * WARNING: The C register and register group struct declarations are provided for
1323  * convenience and illustrative purposes. They should, however, be used with
1324  * caution as the C language standard provides no guarantees about the alignment or
1325  * atomicity of device memory accesses. The recommended practice for writing
1326  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1327  * alt_write_word() functions.
1328  *
1329  * The struct declaration for register ALT_RSTMGR_COUNTS.
1330  */
1331 struct ALT_RSTMGR_COUNTS_s
1332 {
1333  uint32_t warmrstcycles : 8; /* Warm reset release delay count */
1334  uint32_t nrstcnt : 20; /* nRST Pin Count */
1335  uint32_t : 4; /* *UNDEFINED* */
1336 };
1337 
1338 /* The typedef declaration for register ALT_RSTMGR_COUNTS. */
1339 typedef volatile struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t;
1340 #endif /* __ASSEMBLY__ */
1341 
1342 /* The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component. */
1343 #define ALT_RSTMGR_COUNTS_OFST 0x8
1344 
1345 /*
1346  * Register : MPU Module Reset Register - mpumodrst
1347  *
1348  * The MPUMODRST register is used by software to trigger module resets (individual
1349  * module reset signals). Software explicitly asserts and de-asserts module reset
1350  * signals by writing bits in the appropriate *MODRST register. It is up to
1351  * software to ensure module reset signals are asserted for the appropriate length
1352  * of time and are de-asserted in the correct order. It is also up to software to
1353  * not assert a module reset signal that would prevent software from de-asserting
1354  * the module reset signal. For example, software should not assert the module
1355  * reset to the CPU executing the software.
1356  *
1357  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1358  * assert the module reset signal.
1359  *
1360  * All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset
1361  * by a cold reset. The CPU1 field is also reset by a warm reset if not masked by
1362  * the corresponding MPUWARMMASK field.
1363  *
1364  * Register Layout
1365  *
1366  * Bits | Access | Reset | Description
1367  * :-------|:-------|:------|:----------------
1368  * [0] | RW | 0x0 | CPU0
1369  * [1] | RW | 0x1 | CPU1
1370  * [2] | RW | 0x0 | Watchdogs
1371  * [3] | RW | 0x0 | SCU/Peripherals
1372  * [4] | RW | 0x0 | L2
1373  * [31:5] | ??? | 0x0 | *UNDEFINED*
1374  *
1375  */
1376 /*
1377  * Field : CPU0 - cpu0
1378  *
1379  * Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1,
1380  * ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is
1381  * de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.
1382  *
1383  * When software changes this field from 1 to 0, it triggers the following
1384  * sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-
1385  * asserted.
1386  *
1387  * Software needs to wait for at least 64 osc1_clk cycles between each change of
1388  * this field to keep the proper reset/clkoff sequence.
1389  *
1390  * Field Access Macros:
1391  *
1392  */
1393 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1394 #define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1395 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1396 #define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1397 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1398 #define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1399 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1400 #define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
1401 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value. */
1402 #define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
1403 /* The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field. */
1404 #define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
1405 /* Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register. */
1406 #define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
1407 /* Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register. */
1408 #define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
1409 
1410 /*
1411  * Field : CPU1 - cpu1
1412  *
1413  * Resets Cortex-A9 CPU1 in MPU.
1414  *
1415  * It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until
1416  * software is ready to release CPU1 from reset by writing 0 to this field.
1417  *
1418  * On single-core devices, writes to this field are ignored.On dual-core devices,
1419  * writes to this field trigger the same sequence as writes to the CPU0 field
1420  * (except the sequence is performed on CPU1).
1421  *
1422  * Field Access Macros:
1423  *
1424  */
1425 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1426 #define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
1427 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1428 #define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
1429 /* The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1430 #define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
1431 /* The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1432 #define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
1433 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value. */
1434 #define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
1435 /* The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field. */
1436 #define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
1437 /* Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register. */
1438 #define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
1439 /* Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register. */
1440 #define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
1441 
1442 /*
1443  * Field : Watchdogs - wds
1444  *
1445  * Resets both per-CPU Watchdog Reset Status registers in MPU.
1446  *
1447  * Field Access Macros:
1448  *
1449  */
1450 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1451 #define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
1452 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1453 #define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
1454 /* The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1455 #define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
1456 /* The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1457 #define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
1458 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value. */
1459 #define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
1460 /* The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field. */
1461 #define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
1462 /* Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register. */
1463 #define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
1464 /* Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register. */
1465 #define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
1466 
1467 /*
1468  * Field : SCU/Peripherals - scuper
1469  *
1470  * Resets SCU and peripherals. Peripherals consist of the interrupt controller,
1471  * global timer, both per-CPU private timers, and both per-CPU watchdogs (except
1472  * for the Watchdog Reset Status registers).
1473  *
1474  * Field Access Macros:
1475  *
1476  */
1477 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1478 #define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
1479 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1480 #define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
1481 /* The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1482 #define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
1483 /* The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1484 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
1485 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value. */
1486 #define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
1487 /* The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field. */
1488 #define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
1489 /* Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register. */
1490 #define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
1491 /* Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register. */
1492 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
1493 
1494 /*
1495  * Field : L2 - l2
1496  *
1497  * Resets L2 cache controller
1498  *
1499  * Field Access Macros:
1500  *
1501  */
1502 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1503 #define ALT_RSTMGR_MPUMODRST_L2_LSB 4
1504 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1505 #define ALT_RSTMGR_MPUMODRST_L2_MSB 4
1506 /* The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1507 #define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
1508 /* The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1509 #define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
1510 /* The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value. */
1511 #define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
1512 /* The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field. */
1513 #define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
1514 /* Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register. */
1515 #define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
1516 /* Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register. */
1517 #define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
1518 
1519 #ifndef __ASSEMBLY__
1520 /*
1521  * WARNING: The C register and register group struct declarations are provided for
1522  * convenience and illustrative purposes. They should, however, be used with
1523  * caution as the C language standard provides no guarantees about the alignment or
1524  * atomicity of device memory accesses. The recommended practice for writing
1525  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1526  * alt_write_word() functions.
1527  *
1528  * The struct declaration for register ALT_RSTMGR_MPUMODRST.
1529  */
1530 struct ALT_RSTMGR_MPUMODRST_s
1531 {
1532  uint32_t cpu0 : 1; /* CPU0 */
1533  uint32_t cpu1 : 1; /* CPU1 */
1534  uint32_t wds : 1; /* Watchdogs */
1535  uint32_t scuper : 1; /* SCU/Peripherals */
1536  uint32_t l2 : 1; /* L2 */
1537  uint32_t : 27; /* *UNDEFINED* */
1538 };
1539 
1540 /* The typedef declaration for register ALT_RSTMGR_MPUMODRST. */
1541 typedef volatile struct ALT_RSTMGR_MPUMODRST_s ALT_RSTMGR_MPUMODRST_t;
1542 #endif /* __ASSEMBLY__ */
1543 
1544 /* The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component. */
1545 #define ALT_RSTMGR_MPUMODRST_OFST 0x10
1546 
1547 /*
1548  * Register : Peripheral Module Reset Register - permodrst
1549  *
1550  * The PERMODRST register is used by software to trigger module resets (individual
1551  * module reset signals). Software explicitly asserts and de-asserts module reset
1552  * signals by writing bits in the appropriate *MODRST register. It is up to
1553  * software to ensure module reset signals are asserted for the appropriate length
1554  * of time and are de-asserted in the correct order. It is also up to software to
1555  * not assert a module reset signal that would prevent software from de-asserting
1556  * the module reset signal. For example, software should not assert the module
1557  * reset to the CPU executing the software.
1558  *
1559  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
1560  * assert the module reset signal.
1561  *
1562  * All fields are reset by a cold reset.All fields are also reset by a warm reset
1563  * if not masked by the corresponding PERWARMMASK field.
1564  *
1565  * The reset value of all fields is 1. This holds the corresponding module in reset
1566  * until software is ready to release the module from reset by writing 0 to its
1567  * field.
1568  *
1569  * Register Layout
1570  *
1571  * Bits | Access | Reset | Description
1572  * :--------|:-------|:------|:---------------------------
1573  * [0] | RW | 0x1 | EMAC0
1574  * [1] | RW | 0x1 | EMAC1
1575  * [2] | RW | 0x1 | USB0
1576  * [3] | RW | 0x1 | USB1
1577  * [4] | RW | 0x1 | NAND Flash
1578  * [5] | RW | 0x1 | QSPI Flash
1579  * [6] | RW | 0x1 | L4 Watchdog 0
1580  * [7] | RW | 0x1 | L4 Watchdog 1
1581  * [8] | RW | 0x1 | OSC1 Timer 0
1582  * [9] | RW | 0x1 | OSC1 Timer 1
1583  * [10] | RW | 0x1 | SP Timer 0
1584  * [11] | RW | 0x1 | SP Timer 1
1585  * [12] | RW | 0x1 | I2C0
1586  * [13] | RW | 0x1 | I2C1
1587  * [14] | RW | 0x1 | I2C2
1588  * [15] | RW | 0x1 | I2C3
1589  * [16] | RW | 0x1 | UART0
1590  * [17] | RW | 0x1 | UART1
1591  * [18] | RW | 0x1 | SPIM0
1592  * [19] | RW | 0x1 | SPIM1
1593  * [20] | RW | 0x1 | SPIS0
1594  * [21] | RW | 0x1 | SPIS1
1595  * [22] | RW | 0x1 | SD/MMC
1596  * [23] | RW | 0x1 | CAN0
1597  * [24] | RW | 0x1 | CAN1
1598  * [25] | RW | 0x1 | GPIO0
1599  * [26] | RW | 0x1 | GPIO1
1600  * [27] | RW | 0x1 | GPIO2
1601  * [28] | RW | 0x1 | DMA Controller
1602  * [29] | RW | 0x1 | SDRAM Controller Subsystem
1603  * [31:30] | ??? | 0x0 | *UNDEFINED*
1604  *
1605  */
1606 /*
1607  * Field : EMAC0 - emac0
1608  *
1609  * Resets EMAC0
1610  *
1611  * Field Access Macros:
1612  *
1613  */
1614 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1615 #define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
1616 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1617 #define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
1618 /* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1619 #define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
1620 /* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1621 #define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
1622 /* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
1623 #define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
1624 /* The reset value of the ALT_RSTMGR_PERMODRST_EMAC0 register field. */
1625 #define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
1626 /* Extracts the ALT_RSTMGR_PERMODRST_EMAC0 field value from a register. */
1627 #define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1628 /* Produces a ALT_RSTMGR_PERMODRST_EMAC0 register field value suitable for setting the register. */
1629 #define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1630 
1631 /*
1632  * Field : EMAC1 - emac1
1633  *
1634  * Resets EMAC1
1635  *
1636  * Field Access Macros:
1637  *
1638  */
1639 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1640 #define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
1641 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1642 #define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
1643 /* The width in bits of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1644 #define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
1645 /* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1646 #define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
1647 /* The mask used to clear the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
1648 #define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
1649 /* The reset value of the ALT_RSTMGR_PERMODRST_EMAC1 register field. */
1650 #define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
1651 /* Extracts the ALT_RSTMGR_PERMODRST_EMAC1 field value from a register. */
1652 #define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1653 /* Produces a ALT_RSTMGR_PERMODRST_EMAC1 register field value suitable for setting the register. */
1654 #define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1655 
1656 /*
1657  * Field : USB0 - usb0
1658  *
1659  * Resets USB0
1660  *
1661  * Field Access Macros:
1662  *
1663  */
1664 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1665 #define ALT_RSTMGR_PERMODRST_USB0_LSB 2
1666 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1667 #define ALT_RSTMGR_PERMODRST_USB0_MSB 2
1668 /* The width in bits of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1669 #define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
1670 /* The mask used to set the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1671 #define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
1672 /* The mask used to clear the ALT_RSTMGR_PERMODRST_USB0 register field value. */
1673 #define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
1674 /* The reset value of the ALT_RSTMGR_PERMODRST_USB0 register field. */
1675 #define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
1676 /* Extracts the ALT_RSTMGR_PERMODRST_USB0 field value from a register. */
1677 #define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
1678 /* Produces a ALT_RSTMGR_PERMODRST_USB0 register field value suitable for setting the register. */
1679 #define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
1680 
1681 /*
1682  * Field : USB1 - usb1
1683  *
1684  * Resets USB1
1685  *
1686  * Field Access Macros:
1687  *
1688  */
1689 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1690 #define ALT_RSTMGR_PERMODRST_USB1_LSB 3
1691 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1692 #define ALT_RSTMGR_PERMODRST_USB1_MSB 3
1693 /* The width in bits of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1694 #define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
1695 /* The mask used to set the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1696 #define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
1697 /* The mask used to clear the ALT_RSTMGR_PERMODRST_USB1 register field value. */
1698 #define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
1699 /* The reset value of the ALT_RSTMGR_PERMODRST_USB1 register field. */
1700 #define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
1701 /* Extracts the ALT_RSTMGR_PERMODRST_USB1 field value from a register. */
1702 #define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
1703 /* Produces a ALT_RSTMGR_PERMODRST_USB1 register field value suitable for setting the register. */
1704 #define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
1705 
1706 /*
1707  * Field : NAND Flash - nand
1708  *
1709  * Resets NAND flash controller
1710  *
1711  * Field Access Macros:
1712  *
1713  */
1714 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1715 #define ALT_RSTMGR_PERMODRST_NAND_LSB 4
1716 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_NAND register field. */
1717 #define ALT_RSTMGR_PERMODRST_NAND_MSB 4
1718 /* The width in bits of the ALT_RSTMGR_PERMODRST_NAND register field. */
1719 #define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
1720 /* The mask used to set the ALT_RSTMGR_PERMODRST_NAND register field value. */
1721 #define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
1722 /* The mask used to clear the ALT_RSTMGR_PERMODRST_NAND register field value. */
1723 #define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
1724 /* The reset value of the ALT_RSTMGR_PERMODRST_NAND register field. */
1725 #define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
1726 /* Extracts the ALT_RSTMGR_PERMODRST_NAND field value from a register. */
1727 #define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
1728 /* Produces a ALT_RSTMGR_PERMODRST_NAND register field value suitable for setting the register. */
1729 #define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
1730 
1731 /*
1732  * Field : QSPI Flash - qspi
1733  *
1734  * Resets QSPI flash controller
1735  *
1736  * Field Access Macros:
1737  *
1738  */
1739 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1740 #define ALT_RSTMGR_PERMODRST_QSPI_LSB 5
1741 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1742 #define ALT_RSTMGR_PERMODRST_QSPI_MSB 5
1743 /* The width in bits of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1744 #define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
1745 /* The mask used to set the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1746 #define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
1747 /* The mask used to clear the ALT_RSTMGR_PERMODRST_QSPI register field value. */
1748 #define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
1749 /* The reset value of the ALT_RSTMGR_PERMODRST_QSPI register field. */
1750 #define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
1751 /* Extracts the ALT_RSTMGR_PERMODRST_QSPI field value from a register. */
1752 #define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
1753 /* Produces a ALT_RSTMGR_PERMODRST_QSPI register field value suitable for setting the register. */
1754 #define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
1755 
1756 /*
1757  * Field : L4 Watchdog 0 - l4wd0
1758  *
1759  * Resets watchdog 0 connected to L4
1760  *
1761  * Field Access Macros:
1762  *
1763  */
1764 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1765 #define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
1766 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1767 #define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
1768 /* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1769 #define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
1770 /* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1771 #define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
1772 /* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD0 register field value. */
1773 #define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
1774 /* The reset value of the ALT_RSTMGR_PERMODRST_L4WD0 register field. */
1775 #define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
1776 /* Extracts the ALT_RSTMGR_PERMODRST_L4WD0 field value from a register. */
1777 #define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
1778 /* Produces a ALT_RSTMGR_PERMODRST_L4WD0 register field value suitable for setting the register. */
1779 #define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
1780 
1781 /*
1782  * Field : L4 Watchdog 1 - l4wd1
1783  *
1784  * Resets watchdog 1 connected to L4
1785  *
1786  * Field Access Macros:
1787  *
1788  */
1789 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1790 #define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
1791 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1792 #define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
1793 /* The width in bits of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1794 #define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
1795 /* The mask used to set the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1796 #define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
1797 /* The mask used to clear the ALT_RSTMGR_PERMODRST_L4WD1 register field value. */
1798 #define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
1799 /* The reset value of the ALT_RSTMGR_PERMODRST_L4WD1 register field. */
1800 #define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
1801 /* Extracts the ALT_RSTMGR_PERMODRST_L4WD1 field value from a register. */
1802 #define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
1803 /* Produces a ALT_RSTMGR_PERMODRST_L4WD1 register field value suitable for setting the register. */
1804 #define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
1805 
1806 /*
1807  * Field : OSC1 Timer 0 - osc1timer0
1808  *
1809  * Resets OSC1 timer 0 connected to L4
1810  *
1811  * Field Access Macros:
1812  *
1813  */
1814 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1815 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
1816 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1817 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
1818 /* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1819 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
1820 /* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1821 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
1822 /* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value. */
1823 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
1824 /* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR0 register field. */
1825 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
1826 /* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR0 field value from a register. */
1827 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
1828 /* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR0 register field value suitable for setting the register. */
1829 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
1830 
1831 /*
1832  * Field : OSC1 Timer 1 - osc1timer1
1833  *
1834  * Resets OSC1 timer 1 connected to L4
1835  *
1836  * Field Access Macros:
1837  *
1838  */
1839 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1840 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
1841 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1842 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
1843 /* The width in bits of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1844 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
1845 /* The mask used to set the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1846 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
1847 /* The mask used to clear the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value. */
1848 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
1849 /* The reset value of the ALT_RSTMGR_PERMODRST_OSC1TMR1 register field. */
1850 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
1851 /* Extracts the ALT_RSTMGR_PERMODRST_OSC1TMR1 field value from a register. */
1852 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
1853 /* Produces a ALT_RSTMGR_PERMODRST_OSC1TMR1 register field value suitable for setting the register. */
1854 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
1855 
1856 /*
1857  * Field : SP Timer 0 - sptimer0
1858  *
1859  * Resets SP timer 0 connected to L4
1860  *
1861  * Field Access Macros:
1862  *
1863  */
1864 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1865 #define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
1866 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1867 #define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
1868 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1869 #define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
1870 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1871 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
1872 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR0 register field value. */
1873 #define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
1874 /* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR0 register field. */
1875 #define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
1876 /* Extracts the ALT_RSTMGR_PERMODRST_SPTMR0 field value from a register. */
1877 #define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
1878 /* Produces a ALT_RSTMGR_PERMODRST_SPTMR0 register field value suitable for setting the register. */
1879 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
1880 
1881 /*
1882  * Field : SP Timer 1 - sptimer1
1883  *
1884  * Resets SP timer 1 connected to L4
1885  *
1886  * Field Access Macros:
1887  *
1888  */
1889 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1890 #define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
1891 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1892 #define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
1893 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1894 #define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
1895 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1896 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
1897 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPTMR1 register field value. */
1898 #define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
1899 /* The reset value of the ALT_RSTMGR_PERMODRST_SPTMR1 register field. */
1900 #define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
1901 /* Extracts the ALT_RSTMGR_PERMODRST_SPTMR1 field value from a register. */
1902 #define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
1903 /* Produces a ALT_RSTMGR_PERMODRST_SPTMR1 register field value suitable for setting the register. */
1904 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
1905 
1906 /*
1907  * Field : I2C0 - i2c0
1908  *
1909  * Resets I2C0 controller
1910  *
1911  * Field Access Macros:
1912  *
1913  */
1914 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1915 #define ALT_RSTMGR_PERMODRST_I2C0_LSB 12
1916 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1917 #define ALT_RSTMGR_PERMODRST_I2C0_MSB 12
1918 /* The width in bits of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1919 #define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
1920 /* The mask used to set the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1921 #define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
1922 /* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C0 register field value. */
1923 #define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
1924 /* The reset value of the ALT_RSTMGR_PERMODRST_I2C0 register field. */
1925 #define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
1926 /* Extracts the ALT_RSTMGR_PERMODRST_I2C0 field value from a register. */
1927 #define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
1928 /* Produces a ALT_RSTMGR_PERMODRST_I2C0 register field value suitable for setting the register. */
1929 #define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
1930 
1931 /*
1932  * Field : I2C1 - i2c1
1933  *
1934  * Resets I2C1 controller
1935  *
1936  * Field Access Macros:
1937  *
1938  */
1939 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1940 #define ALT_RSTMGR_PERMODRST_I2C1_LSB 13
1941 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1942 #define ALT_RSTMGR_PERMODRST_I2C1_MSB 13
1943 /* The width in bits of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1944 #define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
1945 /* The mask used to set the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1946 #define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
1947 /* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C1 register field value. */
1948 #define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
1949 /* The reset value of the ALT_RSTMGR_PERMODRST_I2C1 register field. */
1950 #define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
1951 /* Extracts the ALT_RSTMGR_PERMODRST_I2C1 field value from a register. */
1952 #define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
1953 /* Produces a ALT_RSTMGR_PERMODRST_I2C1 register field value suitable for setting the register. */
1954 #define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
1955 
1956 /*
1957  * Field : I2C2 - i2c2
1958  *
1959  * Resets I2C2 controller
1960  *
1961  * Field Access Macros:
1962  *
1963  */
1964 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1965 #define ALT_RSTMGR_PERMODRST_I2C2_LSB 14
1966 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1967 #define ALT_RSTMGR_PERMODRST_I2C2_MSB 14
1968 /* The width in bits of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1969 #define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
1970 /* The mask used to set the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1971 #define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
1972 /* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C2 register field value. */
1973 #define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
1974 /* The reset value of the ALT_RSTMGR_PERMODRST_I2C2 register field. */
1975 #define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
1976 /* Extracts the ALT_RSTMGR_PERMODRST_I2C2 field value from a register. */
1977 #define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
1978 /* Produces a ALT_RSTMGR_PERMODRST_I2C2 register field value suitable for setting the register. */
1979 #define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
1980 
1981 /*
1982  * Field : I2C3 - i2c3
1983  *
1984  * Resets I2C3 controller
1985  *
1986  * Field Access Macros:
1987  *
1988  */
1989 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1990 #define ALT_RSTMGR_PERMODRST_I2C3_LSB 15
1991 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1992 #define ALT_RSTMGR_PERMODRST_I2C3_MSB 15
1993 /* The width in bits of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
1994 #define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
1995 /* The mask used to set the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
1996 #define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
1997 /* The mask used to clear the ALT_RSTMGR_PERMODRST_I2C3 register field value. */
1998 #define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
1999 /* The reset value of the ALT_RSTMGR_PERMODRST_I2C3 register field. */
2000 #define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
2001 /* Extracts the ALT_RSTMGR_PERMODRST_I2C3 field value from a register. */
2002 #define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
2003 /* Produces a ALT_RSTMGR_PERMODRST_I2C3 register field value suitable for setting the register. */
2004 #define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
2005 
2006 /*
2007  * Field : UART0 - uart0
2008  *
2009  * Resets UART0
2010  *
2011  * Field Access Macros:
2012  *
2013  */
2014 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2015 #define ALT_RSTMGR_PERMODRST_UART0_LSB 16
2016 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2017 #define ALT_RSTMGR_PERMODRST_UART0_MSB 16
2018 /* The width in bits of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2019 #define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
2020 /* The mask used to set the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2021 #define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
2022 /* The mask used to clear the ALT_RSTMGR_PERMODRST_UART0 register field value. */
2023 #define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
2024 /* The reset value of the ALT_RSTMGR_PERMODRST_UART0 register field. */
2025 #define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
2026 /* Extracts the ALT_RSTMGR_PERMODRST_UART0 field value from a register. */
2027 #define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
2028 /* Produces a ALT_RSTMGR_PERMODRST_UART0 register field value suitable for setting the register. */
2029 #define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
2030 
2031 /*
2032  * Field : UART1 - uart1
2033  *
2034  * Resets UART1
2035  *
2036  * Field Access Macros:
2037  *
2038  */
2039 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2040 #define ALT_RSTMGR_PERMODRST_UART1_LSB 17
2041 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2042 #define ALT_RSTMGR_PERMODRST_UART1_MSB 17
2043 /* The width in bits of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2044 #define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
2045 /* The mask used to set the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2046 #define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
2047 /* The mask used to clear the ALT_RSTMGR_PERMODRST_UART1 register field value. */
2048 #define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
2049 /* The reset value of the ALT_RSTMGR_PERMODRST_UART1 register field. */
2050 #define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
2051 /* Extracts the ALT_RSTMGR_PERMODRST_UART1 field value from a register. */
2052 #define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
2053 /* Produces a ALT_RSTMGR_PERMODRST_UART1 register field value suitable for setting the register. */
2054 #define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
2055 
2056 /*
2057  * Field : SPIM0 - spim0
2058  *
2059  * Resets SPIM0 controller
2060  *
2061  * Field Access Macros:
2062  *
2063  */
2064 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2065 #define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
2066 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2067 #define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
2068 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2069 #define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
2070 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2071 #define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
2072 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM0 register field value. */
2073 #define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
2074 /* The reset value of the ALT_RSTMGR_PERMODRST_SPIM0 register field. */
2075 #define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
2076 /* Extracts the ALT_RSTMGR_PERMODRST_SPIM0 field value from a register. */
2077 #define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
2078 /* Produces a ALT_RSTMGR_PERMODRST_SPIM0 register field value suitable for setting the register. */
2079 #define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
2080 
2081 /*
2082  * Field : SPIM1 - spim1
2083  *
2084  * Resets SPIM1 controller
2085  *
2086  * Field Access Macros:
2087  *
2088  */
2089 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2090 #define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
2091 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2092 #define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
2093 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2094 #define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
2095 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2096 #define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
2097 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIM1 register field value. */
2098 #define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
2099 /* The reset value of the ALT_RSTMGR_PERMODRST_SPIM1 register field. */
2100 #define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
2101 /* Extracts the ALT_RSTMGR_PERMODRST_SPIM1 field value from a register. */
2102 #define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
2103 /* Produces a ALT_RSTMGR_PERMODRST_SPIM1 register field value suitable for setting the register. */
2104 #define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
2105 
2106 /*
2107  * Field : SPIS0 - spis0
2108  *
2109  * Resets SPIS0 controller
2110  *
2111  * Field Access Macros:
2112  *
2113  */
2114 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2115 #define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
2116 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2117 #define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
2118 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2119 #define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
2120 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2121 #define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
2122 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS0 register field value. */
2123 #define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
2124 /* The reset value of the ALT_RSTMGR_PERMODRST_SPIS0 register field. */
2125 #define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
2126 /* Extracts the ALT_RSTMGR_PERMODRST_SPIS0 field value from a register. */
2127 #define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
2128 /* Produces a ALT_RSTMGR_PERMODRST_SPIS0 register field value suitable for setting the register. */
2129 #define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
2130 
2131 /*
2132  * Field : SPIS1 - spis1
2133  *
2134  * Resets SPIS1 controller
2135  *
2136  * Field Access Macros:
2137  *
2138  */
2139 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2140 #define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
2141 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2142 #define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
2143 /* The width in bits of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2144 #define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
2145 /* The mask used to set the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2146 #define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
2147 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SPIS1 register field value. */
2148 #define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
2149 /* The reset value of the ALT_RSTMGR_PERMODRST_SPIS1 register field. */
2150 #define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
2151 /* Extracts the ALT_RSTMGR_PERMODRST_SPIS1 field value from a register. */
2152 #define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
2153 /* Produces a ALT_RSTMGR_PERMODRST_SPIS1 register field value suitable for setting the register. */
2154 #define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
2155 
2156 /*
2157  * Field : SD/MMC - sdmmc
2158  *
2159  * Resets SD/MMC controller
2160  *
2161  * Field Access Macros:
2162  *
2163  */
2164 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2165 #define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
2166 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2167 #define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
2168 /* The width in bits of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2169 #define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
2170 /* The mask used to set the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2171 #define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
2172 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SDMMC register field value. */
2173 #define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
2174 /* The reset value of the ALT_RSTMGR_PERMODRST_SDMMC register field. */
2175 #define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
2176 /* Extracts the ALT_RSTMGR_PERMODRST_SDMMC field value from a register. */
2177 #define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
2178 /* Produces a ALT_RSTMGR_PERMODRST_SDMMC register field value suitable for setting the register. */
2179 #define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
2180 
2181 /*
2182  * Field : CAN0 - can0
2183  *
2184  * Resets CAN0 controller.
2185  *
2186  * Writes to this field on devices not containing CAN controllers will be ignored.
2187  *
2188  * Field Access Macros:
2189  *
2190  */
2191 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2192 #define ALT_RSTMGR_PERMODRST_CAN0_LSB 23
2193 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2194 #define ALT_RSTMGR_PERMODRST_CAN0_MSB 23
2195 /* The width in bits of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2196 #define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
2197 /* The mask used to set the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2198 #define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
2199 /* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN0 register field value. */
2200 #define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
2201 /* The reset value of the ALT_RSTMGR_PERMODRST_CAN0 register field. */
2202 #define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
2203 /* Extracts the ALT_RSTMGR_PERMODRST_CAN0 field value from a register. */
2204 #define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
2205 /* Produces a ALT_RSTMGR_PERMODRST_CAN0 register field value suitable for setting the register. */
2206 #define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
2207 
2208 /*
2209  * Field : CAN1 - can1
2210  *
2211  * Resets CAN1 controller.
2212  *
2213  * Writes to this field on devices not containing CAN controllers will be ignored.
2214  *
2215  * Field Access Macros:
2216  *
2217  */
2218 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2219 #define ALT_RSTMGR_PERMODRST_CAN1_LSB 24
2220 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2221 #define ALT_RSTMGR_PERMODRST_CAN1_MSB 24
2222 /* The width in bits of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2223 #define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
2224 /* The mask used to set the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2225 #define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
2226 /* The mask used to clear the ALT_RSTMGR_PERMODRST_CAN1 register field value. */
2227 #define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
2228 /* The reset value of the ALT_RSTMGR_PERMODRST_CAN1 register field. */
2229 #define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
2230 /* Extracts the ALT_RSTMGR_PERMODRST_CAN1 field value from a register. */
2231 #define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
2232 /* Produces a ALT_RSTMGR_PERMODRST_CAN1 register field value suitable for setting the register. */
2233 #define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
2234 
2235 /*
2236  * Field : GPIO0 - gpio0
2237  *
2238  * Resets GPIO0
2239  *
2240  * Field Access Macros:
2241  *
2242  */
2243 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2244 #define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
2245 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2246 #define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
2247 /* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2248 #define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
2249 /* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2250 #define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
2251 /* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO0 register field value. */
2252 #define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
2253 /* The reset value of the ALT_RSTMGR_PERMODRST_GPIO0 register field. */
2254 #define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
2255 /* Extracts the ALT_RSTMGR_PERMODRST_GPIO0 field value from a register. */
2256 #define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
2257 /* Produces a ALT_RSTMGR_PERMODRST_GPIO0 register field value suitable for setting the register. */
2258 #define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
2259 
2260 /*
2261  * Field : GPIO1 - gpio1
2262  *
2263  * Resets GPIO1
2264  *
2265  * Field Access Macros:
2266  *
2267  */
2268 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2269 #define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
2270 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2271 #define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
2272 /* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2273 #define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
2274 /* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2275 #define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
2276 /* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO1 register field value. */
2277 #define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
2278 /* The reset value of the ALT_RSTMGR_PERMODRST_GPIO1 register field. */
2279 #define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
2280 /* Extracts the ALT_RSTMGR_PERMODRST_GPIO1 field value from a register. */
2281 #define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
2282 /* Produces a ALT_RSTMGR_PERMODRST_GPIO1 register field value suitable for setting the register. */
2283 #define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
2284 
2285 /*
2286  * Field : GPIO2 - gpio2
2287  *
2288  * Resets GPIO2
2289  *
2290  * Field Access Macros:
2291  *
2292  */
2293 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2294 #define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
2295 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2296 #define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
2297 /* The width in bits of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2298 #define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
2299 /* The mask used to set the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2300 #define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
2301 /* The mask used to clear the ALT_RSTMGR_PERMODRST_GPIO2 register field value. */
2302 #define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
2303 /* The reset value of the ALT_RSTMGR_PERMODRST_GPIO2 register field. */
2304 #define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
2305 /* Extracts the ALT_RSTMGR_PERMODRST_GPIO2 field value from a register. */
2306 #define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
2307 /* Produces a ALT_RSTMGR_PERMODRST_GPIO2 register field value suitable for setting the register. */
2308 #define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
2309 
2310 /*
2311  * Field : DMA Controller - dma
2312  *
2313  * Resets DMA controller
2314  *
2315  * Field Access Macros:
2316  *
2317  */
2318 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2319 #define ALT_RSTMGR_PERMODRST_DMA_LSB 28
2320 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_DMA register field. */
2321 #define ALT_RSTMGR_PERMODRST_DMA_MSB 28
2322 /* The width in bits of the ALT_RSTMGR_PERMODRST_DMA register field. */
2323 #define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
2324 /* The mask used to set the ALT_RSTMGR_PERMODRST_DMA register field value. */
2325 #define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
2326 /* The mask used to clear the ALT_RSTMGR_PERMODRST_DMA register field value. */
2327 #define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
2328 /* The reset value of the ALT_RSTMGR_PERMODRST_DMA register field. */
2329 #define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
2330 /* Extracts the ALT_RSTMGR_PERMODRST_DMA field value from a register. */
2331 #define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
2332 /* Produces a ALT_RSTMGR_PERMODRST_DMA register field value suitable for setting the register. */
2333 #define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
2334 
2335 /*
2336  * Field : SDRAM Controller Subsystem - sdr
2337  *
2338  * Resets SDRAM Controller Subsystem affected by a warm or cold reset.
2339  *
2340  * Field Access Macros:
2341  *
2342  */
2343 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2344 #define ALT_RSTMGR_PERMODRST_SDR_LSB 29
2345 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PERMODRST_SDR register field. */
2346 #define ALT_RSTMGR_PERMODRST_SDR_MSB 29
2347 /* The width in bits of the ALT_RSTMGR_PERMODRST_SDR register field. */
2348 #define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
2349 /* The mask used to set the ALT_RSTMGR_PERMODRST_SDR register field value. */
2350 #define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
2351 /* The mask used to clear the ALT_RSTMGR_PERMODRST_SDR register field value. */
2352 #define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
2353 /* The reset value of the ALT_RSTMGR_PERMODRST_SDR register field. */
2354 #define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
2355 /* Extracts the ALT_RSTMGR_PERMODRST_SDR field value from a register. */
2356 #define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
2357 /* Produces a ALT_RSTMGR_PERMODRST_SDR register field value suitable for setting the register. */
2358 #define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
2359 
2360 #ifndef __ASSEMBLY__
2361 /*
2362  * WARNING: The C register and register group struct declarations are provided for
2363  * convenience and illustrative purposes. They should, however, be used with
2364  * caution as the C language standard provides no guarantees about the alignment or
2365  * atomicity of device memory accesses. The recommended practice for writing
2366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2367  * alt_write_word() functions.
2368  *
2369  * The struct declaration for register ALT_RSTMGR_PERMODRST.
2370  */
2371 struct ALT_RSTMGR_PERMODRST_s
2372 {
2373  uint32_t emac0 : 1; /* EMAC0 */
2374  uint32_t emac1 : 1; /* EMAC1 */
2375  uint32_t usb0 : 1; /* USB0 */
2376  uint32_t usb1 : 1; /* USB1 */
2377  uint32_t nand : 1; /* NAND Flash */
2378  uint32_t qspi : 1; /* QSPI Flash */
2379  uint32_t l4wd0 : 1; /* L4 Watchdog 0 */
2380  uint32_t l4wd1 : 1; /* L4 Watchdog 1 */
2381  uint32_t osc1timer0 : 1; /* OSC1 Timer 0 */
2382  uint32_t osc1timer1 : 1; /* OSC1 Timer 1 */
2383  uint32_t sptimer0 : 1; /* SP Timer 0 */
2384  uint32_t sptimer1 : 1; /* SP Timer 1 */
2385  uint32_t i2c0 : 1; /* I2C0 */
2386  uint32_t i2c1 : 1; /* I2C1 */
2387  uint32_t i2c2 : 1; /* I2C2 */
2388  uint32_t i2c3 : 1; /* I2C3 */
2389  uint32_t uart0 : 1; /* UART0 */
2390  uint32_t uart1 : 1; /* UART1 */
2391  uint32_t spim0 : 1; /* SPIM0 */
2392  uint32_t spim1 : 1; /* SPIM1 */
2393  uint32_t spis0 : 1; /* SPIS0 */
2394  uint32_t spis1 : 1; /* SPIS1 */
2395  uint32_t sdmmc : 1; /* SD/MMC */
2396  uint32_t can0 : 1; /* CAN0 */
2397  uint32_t can1 : 1; /* CAN1 */
2398  uint32_t gpio0 : 1; /* GPIO0 */
2399  uint32_t gpio1 : 1; /* GPIO1 */
2400  uint32_t gpio2 : 1; /* GPIO2 */
2401  uint32_t dma : 1; /* DMA Controller */
2402  uint32_t sdr : 1; /* SDRAM Controller Subsystem */
2403  uint32_t : 2; /* *UNDEFINED* */
2404 };
2405 
2406 /* The typedef declaration for register ALT_RSTMGR_PERMODRST. */
2407 typedef volatile struct ALT_RSTMGR_PERMODRST_s ALT_RSTMGR_PERMODRST_t;
2408 #endif /* __ASSEMBLY__ */
2409 
2410 /* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of the component. */
2411 #define ALT_RSTMGR_PERMODRST_OFST 0x14
2412 
2413 /*
2414  * Register : Peripheral 2 Module Reset Register - per2modrst
2415  *
2416  * The PER2MODRST register is used by software to trigger module resets (individual
2417  * module reset signals). Software explicitly asserts and de-asserts module reset
2418  * signals by writing bits in the appropriate *MODRST register. It is up to
2419  * software to ensure module reset signals are asserted for the appropriate length
2420  * of time and are de-asserted in the correct order. It is also up to software to
2421  * not assert a module reset signal that would prevent software from de-asserting
2422  * the module reset signal. For example, software should not assert the module
2423  * reset to the CPU executing the software.
2424  *
2425  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2426  * assert the module reset signal.
2427  *
2428  * All fields are reset by a cold reset.All fields are also reset by a warm reset
2429  * if not masked by the corresponding PERWARMMASK field.
2430  *
2431  * The reset value of all fields is 1. This holds the corresponding module in reset
2432  * until software is ready to release the module from reset by writing 0 to its
2433  * field.
2434  *
2435  * Register Layout
2436  *
2437  * Bits | Access | Reset | Description
2438  * :-------|:-------|:------|:------------
2439  * [0] | RW | 0x1 | FPGA DMA0
2440  * [1] | RW | 0x1 | FPGA DMA1
2441  * [2] | RW | 0x1 | FPGA DMA2
2442  * [3] | RW | 0x1 | FPGA DMA3
2443  * [4] | RW | 0x1 | FPGA DMA4
2444  * [5] | RW | 0x1 | FPGA DMA5
2445  * [6] | RW | 0x1 | FPGA DMA6
2446  * [7] | RW | 0x1 | FPGA DMA7
2447  * [31:8] | ??? | 0x0 | *UNDEFINED*
2448  *
2449  */
2450 /*
2451  * Field : FPGA DMA0 - dmaif0
2452  *
2453  * Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA
2454  * Controller
2455  *
2456  * Field Access Macros:
2457  *
2458  */
2459 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2460 #define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
2461 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2462 #define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
2463 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2464 #define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
2465 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2466 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
2467 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF0 register field value. */
2468 #define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
2469 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF0 register field. */
2470 #define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
2471 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF0 field value from a register. */
2472 #define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
2473 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF0 register field value suitable for setting the register. */
2474 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
2475 
2476 /*
2477  * Field : FPGA DMA1 - dmaif1
2478  *
2479  * Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA
2480  * Controller
2481  *
2482  * Field Access Macros:
2483  *
2484  */
2485 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2486 #define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
2487 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2488 #define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
2489 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2490 #define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
2491 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2492 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
2493 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF1 register field value. */
2494 #define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
2495 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF1 register field. */
2496 #define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
2497 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF1 field value from a register. */
2498 #define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
2499 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF1 register field value suitable for setting the register. */
2500 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
2501 
2502 /*
2503  * Field : FPGA DMA2 - dmaif2
2504  *
2505  * Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA
2506  * Controller
2507  *
2508  * Field Access Macros:
2509  *
2510  */
2511 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2512 #define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
2513 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2514 #define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
2515 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2516 #define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
2517 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2518 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
2519 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF2 register field value. */
2520 #define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
2521 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF2 register field. */
2522 #define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
2523 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF2 field value from a register. */
2524 #define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
2525 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF2 register field value suitable for setting the register. */
2526 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
2527 
2528 /*
2529  * Field : FPGA DMA3 - dmaif3
2530  *
2531  * Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA
2532  * Controller
2533  *
2534  * Field Access Macros:
2535  *
2536  */
2537 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2538 #define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
2539 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2540 #define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
2541 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2542 #define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
2543 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2544 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
2545 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF3 register field value. */
2546 #define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
2547 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF3 register field. */
2548 #define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
2549 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF3 field value from a register. */
2550 #define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
2551 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF3 register field value suitable for setting the register. */
2552 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
2553 
2554 /*
2555  * Field : FPGA DMA4 - dmaif4
2556  *
2557  * Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA
2558  * Controller
2559  *
2560  * Field Access Macros:
2561  *
2562  */
2563 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2564 #define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
2565 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2566 #define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
2567 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2568 #define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
2569 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2570 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
2571 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF4 register field value. */
2572 #define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
2573 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF4 register field. */
2574 #define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
2575 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF4 field value from a register. */
2576 #define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
2577 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF4 register field value suitable for setting the register. */
2578 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
2579 
2580 /*
2581  * Field : FPGA DMA5 - dmaif5
2582  *
2583  * Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA
2584  * Controller
2585  *
2586  * Field Access Macros:
2587  *
2588  */
2589 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2590 #define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
2591 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2592 #define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
2593 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2594 #define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
2595 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2596 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
2597 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF5 register field value. */
2598 #define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
2599 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF5 register field. */
2600 #define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
2601 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF5 field value from a register. */
2602 #define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
2603 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF5 register field value suitable for setting the register. */
2604 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
2605 
2606 /*
2607  * Field : FPGA DMA6 - dmaif6
2608  *
2609  * Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA
2610  * Controller
2611  *
2612  * Field Access Macros:
2613  *
2614  */
2615 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2616 #define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
2617 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2618 #define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
2619 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2620 #define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
2621 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2622 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
2623 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF6 register field value. */
2624 #define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
2625 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF6 register field. */
2626 #define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
2627 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF6 field value from a register. */
2628 #define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
2629 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF6 register field value suitable for setting the register. */
2630 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
2631 
2632 /*
2633  * Field : FPGA DMA7 - dmaif7
2634  *
2635  * Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA
2636  * Controller
2637  *
2638  * Field Access Macros:
2639  *
2640  */
2641 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2642 #define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
2643 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2644 #define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
2645 /* The width in bits of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2646 #define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
2647 /* The mask used to set the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2648 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
2649 /* The mask used to clear the ALT_RSTMGR_PER2MODRST_DMAIF7 register field value. */
2650 #define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
2651 /* The reset value of the ALT_RSTMGR_PER2MODRST_DMAIF7 register field. */
2652 #define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
2653 /* Extracts the ALT_RSTMGR_PER2MODRST_DMAIF7 field value from a register. */
2654 #define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
2655 /* Produces a ALT_RSTMGR_PER2MODRST_DMAIF7 register field value suitable for setting the register. */
2656 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
2657 
2658 #ifndef __ASSEMBLY__
2659 /*
2660  * WARNING: The C register and register group struct declarations are provided for
2661  * convenience and illustrative purposes. They should, however, be used with
2662  * caution as the C language standard provides no guarantees about the alignment or
2663  * atomicity of device memory accesses. The recommended practice for writing
2664  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2665  * alt_write_word() functions.
2666  *
2667  * The struct declaration for register ALT_RSTMGR_PER2MODRST.
2668  */
2669 struct ALT_RSTMGR_PER2MODRST_s
2670 {
2671  uint32_t dmaif0 : 1; /* FPGA DMA0 */
2672  uint32_t dmaif1 : 1; /* FPGA DMA1 */
2673  uint32_t dmaif2 : 1; /* FPGA DMA2 */
2674  uint32_t dmaif3 : 1; /* FPGA DMA3 */
2675  uint32_t dmaif4 : 1; /* FPGA DMA4 */
2676  uint32_t dmaif5 : 1; /* FPGA DMA5 */
2677  uint32_t dmaif6 : 1; /* FPGA DMA6 */
2678  uint32_t dmaif7 : 1; /* FPGA DMA7 */
2679  uint32_t : 24; /* *UNDEFINED* */
2680 };
2681 
2682 /* The typedef declaration for register ALT_RSTMGR_PER2MODRST. */
2683 typedef volatile struct ALT_RSTMGR_PER2MODRST_s ALT_RSTMGR_PER2MODRST_t;
2684 #endif /* __ASSEMBLY__ */
2685 
2686 /* The byte offset of the ALT_RSTMGR_PER2MODRST register from the beginning of the component. */
2687 #define ALT_RSTMGR_PER2MODRST_OFST 0x18
2688 
2689 /*
2690  * Register : Bridge Module Reset Register - brgmodrst
2691  *
2692  * The BRGMODRST register is used by software to trigger module resets (individual
2693  * module reset signals). Software explicitly asserts and de-asserts module reset
2694  * signals by writing bits in the appropriate *MODRST register. It is up to
2695  * software to ensure module reset signals are asserted for the appropriate length
2696  * of time and are de-asserted in the correct order. It is also up to software to
2697  * not assert a module reset signal that would prevent software from de-asserting
2698  * the module reset signal. For example, software should not assert the module
2699  * reset to the CPU executing the software.
2700  *
2701  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2702  * assert the module reset signal.
2703  *
2704  * All fields are reset by a cold reset.All fields are also reset by a warm reset
2705  * if not masked by the corresponding BRGWARMMASK field.
2706  *
2707  * The reset value of all fields is 1. This holds the corresponding module in reset
2708  * until software is ready to release the module from reset by writing 0 to its
2709  * field.
2710  *
2711  * Register Layout
2712  *
2713  * Bits | Access | Reset | Description
2714  * :-------|:-------|:------|:------------------
2715  * [0] | RW | 0x1 | HPS2FPGA Bridge
2716  * [1] | RW | 0x1 | LWHPS2FPGA Bridge
2717  * [2] | RW | 0x1 | FPGA2HPS Bridge
2718  * [31:3] | ??? | 0x0 | *UNDEFINED*
2719  *
2720  */
2721 /*
2722  * Field : HPS2FPGA Bridge - hps2fpga
2723  *
2724  * Resets HPS2FPGA Bridge
2725  *
2726  * Field Access Macros:
2727  *
2728  */
2729 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2730 #define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
2731 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2732 #define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
2733 /* The width in bits of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2734 #define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
2735 /* The mask used to set the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2736 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
2737 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_H2F register field value. */
2738 #define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
2739 /* The reset value of the ALT_RSTMGR_BRGMODRST_H2F register field. */
2740 #define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
2741 /* Extracts the ALT_RSTMGR_BRGMODRST_H2F field value from a register. */
2742 #define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
2743 /* Produces a ALT_RSTMGR_BRGMODRST_H2F register field value suitable for setting the register. */
2744 #define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
2745 
2746 /*
2747  * Field : LWHPS2FPGA Bridge - lwhps2fpga
2748  *
2749  * Resets LWHPS2FPGA Bridge
2750  *
2751  * Field Access Macros:
2752  *
2753  */
2754 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2755 #define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
2756 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2757 #define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
2758 /* The width in bits of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2759 #define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
2760 /* The mask used to set the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2761 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
2762 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_LWH2F register field value. */
2763 #define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
2764 /* The reset value of the ALT_RSTMGR_BRGMODRST_LWH2F register field. */
2765 #define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
2766 /* Extracts the ALT_RSTMGR_BRGMODRST_LWH2F field value from a register. */
2767 #define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
2768 /* Produces a ALT_RSTMGR_BRGMODRST_LWH2F register field value suitable for setting the register. */
2769 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
2770 
2771 /*
2772  * Field : FPGA2HPS Bridge - fpga2hps
2773  *
2774  * Resets FPGA2HPS Bridge
2775  *
2776  * Field Access Macros:
2777  *
2778  */
2779 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2780 #define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
2781 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2782 #define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
2783 /* The width in bits of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2784 #define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
2785 /* The mask used to set the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2786 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
2787 /* The mask used to clear the ALT_RSTMGR_BRGMODRST_F2H register field value. */
2788 #define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
2789 /* The reset value of the ALT_RSTMGR_BRGMODRST_F2H register field. */
2790 #define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
2791 /* Extracts the ALT_RSTMGR_BRGMODRST_F2H field value from a register. */
2792 #define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
2793 /* Produces a ALT_RSTMGR_BRGMODRST_F2H register field value suitable for setting the register. */
2794 #define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
2795 
2796 #ifndef __ASSEMBLY__
2797 /*
2798  * WARNING: The C register and register group struct declarations are provided for
2799  * convenience and illustrative purposes. They should, however, be used with
2800  * caution as the C language standard provides no guarantees about the alignment or
2801  * atomicity of device memory accesses. The recommended practice for writing
2802  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2803  * alt_write_word() functions.
2804  *
2805  * The struct declaration for register ALT_RSTMGR_BRGMODRST.
2806  */
2807 struct ALT_RSTMGR_BRGMODRST_s
2808 {
2809  uint32_t hps2fpga : 1; /* HPS2FPGA Bridge */
2810  uint32_t lwhps2fpga : 1; /* LWHPS2FPGA Bridge */
2811  uint32_t fpga2hps : 1; /* FPGA2HPS Bridge */
2812  uint32_t : 29; /* *UNDEFINED* */
2813 };
2814 
2815 /* The typedef declaration for register ALT_RSTMGR_BRGMODRST. */
2816 typedef volatile struct ALT_RSTMGR_BRGMODRST_s ALT_RSTMGR_BRGMODRST_t;
2817 #endif /* __ASSEMBLY__ */
2818 
2819 /* The byte offset of the ALT_RSTMGR_BRGMODRST register from the beginning of the component. */
2820 #define ALT_RSTMGR_BRGMODRST_OFST 0x1c
2821 
2822 /*
2823  * Register : Miscellaneous Module Reset Register - miscmodrst
2824  *
2825  * The MISCMODRST register is used by software to trigger module resets (individual
2826  * module reset signals). Software explicitly asserts and de-asserts module reset
2827  * signals by writing bits in the appropriate *MODRST register. It is up to
2828  * software to ensure module reset signals are asserted for the appropriate length
2829  * of time and are de-asserted in the correct order. It is also up to software to
2830  * not assert a module reset signal that would prevent software from de-asserting
2831  * the module reset signal. For example, software should not assert the module
2832  * reset to the CPU executing the software.
2833  *
2834  * Software writes a bit to 1 to assert the module reset signal and to 0 to de-
2835  * assert the module reset signal.
2836  *
2837  * All fields are only reset by a cold reset
2838  *
2839  * Register Layout
2840  *
2841  * Bits | Access | Reset | Description
2842  * :--------|:-------|:------|:--------------------------------------
2843  * [0] | RW | 0x0 | Boot ROM
2844  * [1] | RW | 0x0 | On-chip RAM
2845  * [2] | RW | 0x0 | System Manager (Cold or Warm)
2846  * [3] | RW | 0x0 | System Manager (Cold-only)
2847  * [4] | RW | 0x0 | FPGA Manager
2848  * [5] | RW | 0x0 | ACP ID Mapper
2849  * [6] | RW | 0x0 | HPS to FPGA Core (Cold or Warm)
2850  * [7] | RW | 0x0 | HPS to FPGA Core (Cold-only)
2851  * [8] | RW | 0x0 | nRST Pin
2852  * [9] | RW | 0x0 | Timestamp
2853  * [10] | RW | 0x0 | Clock Manager
2854  * [11] | RW | 0x0 | Scan Manager
2855  * [12] | RW | 0x0 | Freeze Controller
2856  * [13] | RW | 0x0 | System/Debug
2857  * [14] | RW | 0x0 | Debug
2858  * [15] | RW | 0x0 | TAP Controller
2859  * [16] | RW | 0x0 | SDRAM Controller Subsystem Cold Reset
2860  * [31:17] | ??? | 0x0 | *UNDEFINED*
2861  *
2862  */
2863 /*
2864  * Field : Boot ROM - rom
2865  *
2866  * Resets Boot ROM
2867  *
2868  * Field Access Macros:
2869  *
2870  */
2871 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2872 #define ALT_RSTMGR_MISCMODRST_ROM_LSB 0
2873 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2874 #define ALT_RSTMGR_MISCMODRST_ROM_MSB 0
2875 /* The width in bits of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2876 #define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
2877 /* The mask used to set the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2878 #define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
2879 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_ROM register field value. */
2880 #define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
2881 /* The reset value of the ALT_RSTMGR_MISCMODRST_ROM register field. */
2882 #define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
2883 /* Extracts the ALT_RSTMGR_MISCMODRST_ROM field value from a register. */
2884 #define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
2885 /* Produces a ALT_RSTMGR_MISCMODRST_ROM register field value suitable for setting the register. */
2886 #define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
2887 
2888 /*
2889  * Field : On-chip RAM - ocram
2890  *
2891  * Resets On-chip RAM
2892  *
2893  * Field Access Macros:
2894  *
2895  */
2896 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2897 #define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
2898 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2899 #define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
2900 /* The width in bits of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2901 #define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
2902 /* The mask used to set the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2903 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
2904 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_OCRAM register field value. */
2905 #define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
2906 /* The reset value of the ALT_RSTMGR_MISCMODRST_OCRAM register field. */
2907 #define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
2908 /* Extracts the ALT_RSTMGR_MISCMODRST_OCRAM field value from a register. */
2909 #define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
2910 /* Produces a ALT_RSTMGR_MISCMODRST_OCRAM register field value suitable for setting the register. */
2911 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
2912 
2913 /*
2914  * Field : System Manager (Cold or Warm) - sysmgr
2915  *
2916  * Resets logic in System Manager that doesn't differentiate between cold and warm
2917  * resets
2918  *
2919  * Field Access Macros:
2920  *
2921  */
2922 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2923 #define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
2924 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2925 #define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
2926 /* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2927 #define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
2928 /* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2929 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
2930 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGR register field value. */
2931 #define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
2932 /* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGR register field. */
2933 #define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
2934 /* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGR field value from a register. */
2935 #define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
2936 /* Produces a ALT_RSTMGR_MISCMODRST_SYSMGR register field value suitable for setting the register. */
2937 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
2938 
2939 /*
2940  * Field : System Manager (Cold-only) - sysmgrcold
2941  *
2942  * Resets logic in System Manager that is only reset by a cold reset (ignores warm
2943  * reset)
2944  *
2945  * Field Access Macros:
2946  *
2947  */
2948 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2949 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
2950 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2951 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
2952 /* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2953 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
2954 /* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2955 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
2956 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value. */
2957 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
2958 /* The reset value of the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field. */
2959 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
2960 /* Extracts the ALT_RSTMGR_MISCMODRST_SYSMGRCOLD field value from a register. */
2961 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
2962 /* Produces a ALT_RSTMGR_MISCMODRST_SYSMGRCOLD register field value suitable for setting the register. */
2963 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
2964 
2965 /*
2966  * Field : FPGA Manager - fpgamgr
2967  *
2968  * Resets FPGA Manager
2969  *
2970  * Field Access Macros:
2971  *
2972  */
2973 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2974 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
2975 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2976 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
2977 /* The width in bits of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2978 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
2979 /* The mask used to set the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2980 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
2981 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_FPGAMGR register field value. */
2982 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
2983 /* The reset value of the ALT_RSTMGR_MISCMODRST_FPGAMGR register field. */
2984 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
2985 /* Extracts the ALT_RSTMGR_MISCMODRST_FPGAMGR field value from a register. */
2986 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
2987 /* Produces a ALT_RSTMGR_MISCMODRST_FPGAMGR register field value suitable for setting the register. */
2988 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
2989 
2990 /*
2991  * Field : ACP ID Mapper - acpidmap
2992  *
2993  * Resets ACP ID Mapper
2994  *
2995  * Field Access Macros:
2996  *
2997  */
2998 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
2999 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
3000 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3001 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
3002 /* The width in bits of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3003 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
3004 /* The mask used to set the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3005 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
3006 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value. */
3007 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
3008 /* The reset value of the ALT_RSTMGR_MISCMODRST_ACPIDMAP register field. */
3009 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
3010 /* Extracts the ALT_RSTMGR_MISCMODRST_ACPIDMAP field value from a register. */
3011 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
3012 /* Produces a ALT_RSTMGR_MISCMODRST_ACPIDMAP register field value suitable for setting the register. */
3013 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
3014 
3015 /*
3016  * Field : HPS to FPGA Core (Cold or Warm) - s2f
3017  *
3018  * Resets logic in FPGA core that doesn't differentiate between HPS cold and warm
3019  * resets (h2f_rst_n = 1)
3020  *
3021  * Field Access Macros:
3022  *
3023  */
3024 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3025 #define ALT_RSTMGR_MISCMODRST_S2F_LSB 6
3026 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3027 #define ALT_RSTMGR_MISCMODRST_S2F_MSB 6
3028 /* The width in bits of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3029 #define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
3030 /* The mask used to set the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3031 #define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
3032 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2F register field value. */
3033 #define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
3034 /* The reset value of the ALT_RSTMGR_MISCMODRST_S2F register field. */
3035 #define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
3036 /* Extracts the ALT_RSTMGR_MISCMODRST_S2F field value from a register. */
3037 #define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
3038 /* Produces a ALT_RSTMGR_MISCMODRST_S2F register field value suitable for setting the register. */
3039 #define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
3040 
3041 /*
3042  * Field : HPS to FPGA Core (Cold-only) - s2fcold
3043  *
3044  * Resets logic in FPGA core that is only reset by a cold reset (ignores warm
3045  * reset) (h2f_cold_rst_n = 1)
3046  *
3047  * Field Access Macros:
3048  *
3049  */
3050 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3051 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
3052 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3053 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
3054 /* The width in bits of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3055 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
3056 /* The mask used to set the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3057 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
3058 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_S2FCOLD register field value. */
3059 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
3060 /* The reset value of the ALT_RSTMGR_MISCMODRST_S2FCOLD register field. */
3061 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
3062 /* Extracts the ALT_RSTMGR_MISCMODRST_S2FCOLD field value from a register. */
3063 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
3064 /* Produces a ALT_RSTMGR_MISCMODRST_S2FCOLD register field value suitable for setting the register. */
3065 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
3066 
3067 /*
3068  * Field : nRST Pin - nrstpin
3069  *
3070  * Pulls nRST pin low
3071  *
3072  * Field Access Macros:
3073  *
3074  */
3075 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3076 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
3077 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3078 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
3079 /* The width in bits of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3080 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
3081 /* The mask used to set the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3082 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
3083 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_NRSTPIN register field value. */
3084 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
3085 /* The reset value of the ALT_RSTMGR_MISCMODRST_NRSTPIN register field. */
3086 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
3087 /* Extracts the ALT_RSTMGR_MISCMODRST_NRSTPIN field value from a register. */
3088 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
3089 /* Produces a ALT_RSTMGR_MISCMODRST_NRSTPIN register field value suitable for setting the register. */
3090 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
3091 
3092 /*
3093  * Field : Timestamp - timestampcold
3094  *
3095  * Resets debug timestamp to 0 (cold reset only)
3096  *
3097  * Field Access Macros:
3098  *
3099  */
3100 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3101 #define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
3102 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3103 #define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
3104 /* The width in bits of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3105 #define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
3106 /* The mask used to set the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3107 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
3108 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_TSCOLD register field value. */
3109 #define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
3110 /* The reset value of the ALT_RSTMGR_MISCMODRST_TSCOLD register field. */
3111 #define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
3112 /* Extracts the ALT_RSTMGR_MISCMODRST_TSCOLD field value from a register. */
3113 #define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
3114 /* Produces a ALT_RSTMGR_MISCMODRST_TSCOLD register field value suitable for setting the register. */
3115 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
3116 
3117 /*
3118  * Field : Clock Manager - clkmgrcold
3119  *
3120  * Resets Clock Manager (cold reset only)
3121  *
3122  * Field Access Macros:
3123  *
3124  */
3125 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3126 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
3127 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3128 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
3129 /* The width in bits of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3130 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
3131 /* The mask used to set the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3132 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
3133 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value. */
3134 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
3135 /* The reset value of the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field. */
3136 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
3137 /* Extracts the ALT_RSTMGR_MISCMODRST_CLKMGRCOLD field value from a register. */
3138 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
3139 /* Produces a ALT_RSTMGR_MISCMODRST_CLKMGRCOLD register field value suitable for setting the register. */
3140 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
3141 
3142 /*
3143  * Field : Scan Manager - scanmgr
3144  *
3145  * Resets Scan Manager
3146  *
3147  * Field Access Macros:
3148  *
3149  */
3150 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3151 #define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
3152 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3153 #define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
3154 /* The width in bits of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3155 #define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
3156 /* The mask used to set the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3157 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
3158 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_SCANMGR register field value. */
3159 #define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
3160 /* The reset value of the ALT_RSTMGR_MISCMODRST_SCANMGR register field. */
3161 #define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
3162 /* Extracts the ALT_RSTMGR_MISCMODRST_SCANMGR field value from a register. */
3163 #define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
3164 /* Produces a ALT_RSTMGR_MISCMODRST_SCANMGR register field value suitable for setting the register. */
3165 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
3166 
3167 /*
3168  * Field : Freeze Controller - frzctrlcold
3169  *
3170  * Resets Freeze Controller in System Manager (cold reset only)
3171  *
3172  * Field Access Macros:
3173  *
3174  */
3175 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3176 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
3177 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3178 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
3179 /* The width in bits of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3180 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
3181 /* The mask used to set the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3182 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
3183 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value. */
3184 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
3185 /* The reset value of the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field. */
3186 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
3187 /* Extracts the ALT_RSTMGR_MISCMODRST_FRZCTLCOLD field value from a register. */
3188 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
3189 /* Produces a ALT_RSTMGR_MISCMODRST_FRZCTLCOLD register field value suitable for setting the register. */
3190 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
3191 
3192 /*
3193  * Field : System/Debug - sysdbg
3194  *
3195  * Resets logic that spans the system and debug domains.
3196  *
3197  * Field Access Macros:
3198  *
3199  */
3200 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3201 #define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
3202 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3203 #define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
3204 /* The width in bits of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3205 #define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
3206 /* The mask used to set the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3207 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
3208 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_SYSDBG register field value. */
3209 #define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
3210 /* The reset value of the ALT_RSTMGR_MISCMODRST_SYSDBG register field. */
3211 #define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
3212 /* Extracts the ALT_RSTMGR_MISCMODRST_SYSDBG field value from a register. */
3213 #define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
3214 /* Produces a ALT_RSTMGR_MISCMODRST_SYSDBG register field value suitable for setting the register. */
3215 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
3216 
3217 /*
3218  * Field : Debug - dbg
3219  *
3220  * Resets logic located only in the debug domain.
3221  *
3222  * Field Access Macros:
3223  *
3224  */
3225 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3226 #define ALT_RSTMGR_MISCMODRST_DBG_LSB 14
3227 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3228 #define ALT_RSTMGR_MISCMODRST_DBG_MSB 14
3229 /* The width in bits of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3230 #define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
3231 /* The mask used to set the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3232 #define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
3233 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_DBG register field value. */
3234 #define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
3235 /* The reset value of the ALT_RSTMGR_MISCMODRST_DBG register field. */
3236 #define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
3237 /* Extracts the ALT_RSTMGR_MISCMODRST_DBG field value from a register. */
3238 #define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
3239 /* Produces a ALT_RSTMGR_MISCMODRST_DBG register field value suitable for setting the register. */
3240 #define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
3241 
3242 /*
3243  * Field : TAP Controller - tapcold
3244  *
3245  * Resets portion of DAP JTAG TAP controller no reset by a debug probe reset (i.e.
3246  * nTRST pin). Cold reset only.
3247  *
3248  * Field Access Macros:
3249  *
3250  */
3251 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3252 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
3253 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3254 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
3255 /* The width in bits of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3256 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
3257 /* The mask used to set the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3258 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
3259 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_TAPCOLD register field value. */
3260 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
3261 /* The reset value of the ALT_RSTMGR_MISCMODRST_TAPCOLD register field. */
3262 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
3263 /* Extracts the ALT_RSTMGR_MISCMODRST_TAPCOLD field value from a register. */
3264 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
3265 /* Produces a ALT_RSTMGR_MISCMODRST_TAPCOLD register field value suitable for setting the register. */
3266 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
3267 
3268 /*
3269  * Field : SDRAM Controller Subsystem Cold Reset - sdrcold
3270  *
3271  * Resets logic in SDRAM Controller Subsystem affected only by a cold reset.
3272  *
3273  * Field Access Macros:
3274  *
3275  */
3276 /* The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3277 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
3278 /* The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3279 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
3280 /* The width in bits of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3281 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
3282 /* The mask used to set the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3283 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
3284 /* The mask used to clear the ALT_RSTMGR_MISCMODRST_SDRCOLD register field value. */
3285 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
3286 /* The reset value of the ALT_RSTMGR_MISCMODRST_SDRCOLD register field. */
3287 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
3288 /* Extracts the ALT_RSTMGR_MISCMODRST_SDRCOLD field value from a register. */
3289 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
3290 /* Produces a ALT_RSTMGR_MISCMODRST_SDRCOLD register field value suitable for setting the register. */
3291 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
3292 
3293 #ifndef __ASSEMBLY__
3294 /*
3295  * WARNING: The C register and register group struct declarations are provided for
3296  * convenience and illustrative purposes. They should, however, be used with
3297  * caution as the C language standard provides no guarantees about the alignment or
3298  * atomicity of device memory accesses. The recommended practice for writing
3299  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3300  * alt_write_word() functions.
3301  *
3302  * The struct declaration for register ALT_RSTMGR_MISCMODRST.
3303  */
3304 struct ALT_RSTMGR_MISCMODRST_s
3305 {
3306  uint32_t rom : 1; /* Boot ROM */
3307  uint32_t ocram : 1; /* On-chip RAM */
3308  uint32_t sysmgr : 1; /* System Manager (Cold or Warm) */
3309  uint32_t sysmgrcold : 1; /* System Manager (Cold-only) */
3310  uint32_t fpgamgr : 1; /* FPGA Manager */
3311  uint32_t acpidmap : 1; /* ACP ID Mapper */
3312  uint32_t s2f : 1; /* HPS to FPGA Core (Cold or Warm) */
3313  uint32_t s2fcold : 1; /* HPS to FPGA Core (Cold-only) */
3314  uint32_t nrstpin : 1; /* nRST Pin */
3315  uint32_t timestampcold : 1; /* Timestamp */
3316  uint32_t clkmgrcold : 1; /* Clock Manager */
3317  uint32_t scanmgr : 1; /* Scan Manager */
3318  uint32_t frzctrlcold : 1; /* Freeze Controller */
3319  uint32_t sysdbg : 1; /* System/Debug */
3320  uint32_t dbg : 1; /* Debug */
3321  uint32_t tapcold : 1; /* TAP Controller */
3322  uint32_t sdrcold : 1; /* SDRAM Controller Subsystem Cold Reset */
3323  uint32_t : 15; /* *UNDEFINED* */
3324 };
3325 
3326 /* The typedef declaration for register ALT_RSTMGR_MISCMODRST. */
3327 typedef volatile struct ALT_RSTMGR_MISCMODRST_s ALT_RSTMGR_MISCMODRST_t;
3328 #endif /* __ASSEMBLY__ */
3329 
3330 /* The byte offset of the ALT_RSTMGR_MISCMODRST register from the beginning of the component. */
3331 #define ALT_RSTMGR_MISCMODRST_OFST 0x20
3332 
3333 #ifndef __ASSEMBLY__
3334 /*
3335  * WARNING: The C register and register group struct declarations are provided for
3336  * convenience and illustrative purposes. They should, however, be used with
3337  * caution as the C language standard provides no guarantees about the alignment or
3338  * atomicity of device memory accesses. The recommended practice for writing
3339  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3340  * alt_write_word() functions.
3341  *
3342  * The struct declaration for register group ALT_RSTMGR.
3343  */
3344 struct ALT_RSTMGR_s
3345 {
3346  ALT_RSTMGR_STAT_t stat; /* ALT_RSTMGR_STAT */
3347  ALT_RSTMGR_CTL_t ctrl; /* ALT_RSTMGR_CTL */
3348  ALT_RSTMGR_COUNTS_t counts; /* ALT_RSTMGR_COUNTS */
3349  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3350  ALT_RSTMGR_MPUMODRST_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
3351  ALT_RSTMGR_PERMODRST_t permodrst; /* ALT_RSTMGR_PERMODRST */
3352  ALT_RSTMGR_PER2MODRST_t per2modrst; /* ALT_RSTMGR_PER2MODRST */
3353  ALT_RSTMGR_BRGMODRST_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
3354  ALT_RSTMGR_MISCMODRST_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */
3355  volatile uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */
3356 };
3357 
3358 /* The typedef declaration for register group ALT_RSTMGR. */
3359 typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
3360 /* The struct declaration for the raw register contents of register group ALT_RSTMGR. */
3361 struct ALT_RSTMGR_raw_s
3362 {
3363  volatile uint32_t stat; /* ALT_RSTMGR_STAT */
3364  volatile uint32_t ctrl; /* ALT_RSTMGR_CTL */
3365  volatile uint32_t counts; /* ALT_RSTMGR_COUNTS */
3366  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3367  volatile uint32_t mpumodrst; /* ALT_RSTMGR_MPUMODRST */
3368  volatile uint32_t permodrst; /* ALT_RSTMGR_PERMODRST */
3369  volatile uint32_t per2modrst; /* ALT_RSTMGR_PER2MODRST */
3370  volatile uint32_t brgmodrst; /* ALT_RSTMGR_BRGMODRST */
3371  volatile uint32_t miscmodrst; /* ALT_RSTMGR_MISCMODRST */
3372  uint32_t _pad_0x24_0x100[55]; /* *UNDEFINED* */
3373 };
3374 
3375 /* The typedef declaration for the raw register contents of register group ALT_RSTMGR. */
3376 typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;
3377 #endif /* __ASSEMBLY__ */
3378 
3379 
3380 #ifdef __cplusplus
3381 }
3382 #endif /* __cplusplus */
3383 #endif /* __ALTERA_ALT_RSTMGR_H__ */
3384