Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups
alt_fpga_manager.h
1 /******************************************************************************
2  *
3  * Copyright 2015 Altera Corporation. All Rights Reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its contributors
16  * may be used to endorse or promote products derived from this software without
17  * specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  ******************************************************************************/
32 
33 /*
34  * $Id: //acds/rel/20.1/embedded/ip/hps/altera_hps/hwlib/include/soc_a10/alt_fpga_manager.h#1 $
35  */
36 
37 #ifndef __ALT_FPGA_MANAGER_H__
38 #define __ALT_FPGA_MANAGER_H__
39 
40 #include "hwlib.h"
41 #include "alt_dma.h"
42 
43 #ifdef __cplusplus
44 extern "C"
45 {
46 #endif /* __cplusplus */
47 
70 #ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
71 #define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
72 #endif
73 
78 typedef enum ALT_FPGA_CFG_MODE_e
79 {
85 
91 
97 
103 
109 
115 
121 
127 
129 
137 ALT_STATUS_CODE alt_fpga_init(void);
138 
145 ALT_STATUS_CODE alt_fpga_uninit(void);
146 
162 
171 ALT_STATUS_CODE alt_fpga_control_disable(void);
172 
181 bool alt_fpga_control_is_enabled(void);
182 
198 ALT_STATUS_CODE alt_fpga_reset_assert(void);
199 
214 ALT_STATUS_CODE alt_fpga_reset_deassert(void);
215 
220 typedef enum ALT_FPGA_STATUS_e
221 {
226 
233 
239 
244 
250 
255 
261 
266 
271 
276 
281 
286 
291 
296 
301 
306 
311 
316 
321 
326 
331 
333 
340 uint32_t alt_fpga_status_get(void);
341 
385 typedef int32_t (*alt_fpga_istream_t)(void * buf, size_t len, void * user_data);
386 
415 ALT_STATUS_CODE alt_fpga_configure(const void * buf,
416  size_t len);
417 
441 ALT_STATUS_CODE alt_fpga_configure_list(const void ** buf_list,
442  const size_t * len_list,
443  size_t list_count);
444 
445 
446 #if ALT_FPGA_ENABLE_DMA_SUPPORT
447 
476 ALT_STATUS_CODE alt_fpga_configure_dma(const void * buf,
477  size_t len,
478  ALT_DMA_CHANNEL_t dma_channel);
479 
513 ALT_STATUS_CODE alt_fpga_configure_list_dma(const void ** buf_list,
514  const size_t * len_list,
515  size_t list_count,
516  ALT_DMA_CHANNEL_t dma_channel);
517 
518 #endif
519 
543 ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream,
544  void * user_data);
545 
546 #if ALT_FPGA_ENABLE_DMA_SUPPORT
547 
580 ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream,
581  void * user_data,
582  ALT_DMA_CHANNEL_t dma_channel);
583 
584 #endif
585 
624 ALT_STATUS_CODE alt_fpga_int_enable(uint32_t mask);
625 
641 ALT_STATUS_CODE alt_fpga_int_disable(uint32_t mask);
642 
652 uint32_t alt_fpga_int_get(void);
653 
669 ALT_STATUS_CODE alt_fpga_int_clear(uint32_t mask);
670 
691 typedef enum ALT_FPGA_GPI_e
692 {
694  ALT_FPGA_GPI_0 = (int32_t)(1UL << 0),
695 
697  ALT_FPGA_GPI_1 = (int32_t)(1UL << 1),
698 
700  ALT_FPGA_GPI_2 = (int32_t)(1UL << 2),
701 
703  ALT_FPGA_GPI_3 = (int32_t)(1UL << 3),
704 
706  ALT_FPGA_GPI_4 = (int32_t)(1UL << 4),
707 
709  ALT_FPGA_GPI_5 = (int32_t)(1UL << 5),
710 
712  ALT_FPGA_GPI_6 = (int32_t)(1UL << 6),
713 
715  ALT_FPGA_GPI_7 = (int32_t)(1UL << 7),
716 
718  ALT_FPGA_GPI_8 = (int32_t)(1UL << 8),
719 
721  ALT_FPGA_GPI_9 = (int32_t)(1UL << 9),
722 
724  ALT_FPGA_GPI_10 = (int32_t)(1UL << 10),
725 
727  ALT_FPGA_GPI_11 = (int32_t)(1UL << 11),
728 
730  ALT_FPGA_GPI_12 = (int32_t)(1UL << 12),
731 
733  ALT_FPGA_GPI_13 = (int32_t)(1UL << 13),
734 
736  ALT_FPGA_GPI_14 = (int32_t)(1UL << 14),
737 
739  ALT_FPGA_GPI_15 = (int32_t)(1UL << 15),
740 
742  ALT_FPGA_GPI_16 = (int32_t)(1UL << 16),
743 
745  ALT_FPGA_GPI_17 = (int32_t)(1UL << 17),
746 
748  ALT_FPGA_GPI_18 = (int32_t)(1UL << 18),
749 
751  ALT_FPGA_GPI_19 = (int32_t)(1UL << 19),
752 
754  ALT_FPGA_GPI_20 = (int32_t)(1UL << 20),
755 
757  ALT_FPGA_GPI_21 = (int32_t)(1UL << 21),
758 
760  ALT_FPGA_GPI_22 = (int32_t)(1UL << 22),
761 
763  ALT_FPGA_GPI_23 = (int32_t)(1UL << 23),
764 
766  ALT_FPGA_GPI_24 = (int32_t)(1UL << 24),
767 
769  ALT_FPGA_GPI_25 = (int32_t)(1UL << 25),
770 
772  ALT_FPGA_GPI_26 = (int32_t)(1UL << 26),
773 
775  ALT_FPGA_GPI_27 = (int32_t)(1UL << 27),
776 
778  ALT_FPGA_GPI_28 = (int32_t)(1UL << 28),
779 
781  ALT_FPGA_GPI_29 = (int32_t)(1UL << 29),
782 
784  ALT_FPGA_GPI_30 = (int32_t)(1UL << 30),
785 
787  ALT_FPGA_GPI_31 = (int32_t)(1UL << 31)
788 
790 
808 uint32_t alt_fpga_gpi_read(uint32_t mask);
809 
814 typedef enum ALT_FPGA_GPO_e
815 {
817  ALT_FPGA_GPO_0 = (int32_t)(1UL << 0),
818 
820  ALT_FPGA_GPO_1 = (int32_t)(1UL << 1),
821 
823  ALT_FPGA_GPO_2 = (int32_t)(1UL << 2),
824 
826  ALT_FPGA_GPO_3 = (int32_t)(1UL << 3),
827 
829  ALT_FPGA_GPO_4 = (int32_t)(1UL << 4),
830 
832  ALT_FPGA_GPO_5 = (int32_t)(1UL << 5),
833 
835  ALT_FPGA_GPO_6 = (int32_t)(1UL << 6),
836 
838  ALT_FPGA_GPO_7 = (int32_t)(1UL << 7),
839 
841  ALT_FPGA_GPO_8 = (int32_t)(1UL << 8),
842 
844  ALT_FPGA_GPO_9 = (int32_t)(1UL << 9),
845 
847  ALT_FPGA_GPO_10 = (int32_t)(1UL << 10),
848 
850  ALT_FPGA_GPO_11 = (int32_t)(1UL << 11),
851 
853  ALT_FPGA_GPO_12 = (int32_t)(1UL << 12),
854 
856  ALT_FPGA_GPO_13 = (int32_t)(1UL << 13),
857 
859  ALT_FPGA_GPO_14 = (int32_t)(1UL << 14),
860 
862  ALT_FPGA_GPO_15 = (int32_t)(1UL << 15),
863 
865  ALT_FPGA_GPO_16 = (int32_t)(1UL << 16),
866 
868  ALT_FPGA_GPO_17 = (int32_t)(1UL << 17),
869 
871  ALT_FPGA_GPO_18 = (int32_t)(1UL << 18),
872 
874  ALT_FPGA_GPO_19 = (int32_t)(1UL << 19),
875 
877  ALT_FPGA_GPO_20 = (int32_t)(1UL << 20),
878 
880  ALT_FPGA_GPO_21 = (int32_t)(1UL << 21),
881 
883  ALT_FPGA_GPO_22 = (int32_t)(1UL << 22),
884 
886  ALT_FPGA_GPO_23 = (int32_t)(1UL << 23),
887 
889  ALT_FPGA_GPO_24 = (int32_t)(1UL << 24),
890 
892  ALT_FPGA_GPO_25 = (int32_t)(1UL << 25),
893 
895  ALT_FPGA_GPO_26 = (int32_t)(1UL << 26),
896 
898  ALT_FPGA_GPO_27 = (int32_t)(1UL << 27),
899 
901  ALT_FPGA_GPO_28 = (int32_t)(1UL << 28),
902 
904  ALT_FPGA_GPO_29 = (int32_t)(1UL << 29),
905 
907  ALT_FPGA_GPO_30 = (int32_t)(1UL << 30),
908 
910  ALT_FPGA_GPO_31 = (int32_t)(1UL << 31)
911 
913 
938 ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value);
939 
948 #ifdef __cplusplus
949 }
950 #endif /* __cplusplus */
951 
952 #endif /* __ALT_FPGA_MANAGER_H__ */