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20.1
Arria 10 SoC Hardware Manager
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alt_fpga_manager.h
1
/******************************************************************************
2
*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
32
33
/*
34
* $Id: //acds/rel/20.1std/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_fpga_manager.h#1 $
35
*/
36
37
#ifndef __ALT_FPGA_MGR_H__
38
#define __ALT_FPGA_MGR_H__
39
40
#include "hwlib.h"
41
#include "alt_dma.h"
42
#include <stdio.h>
43
44
#ifdef __cplusplus
45
extern
"C"
46
{
47
#endif
/* __cplusplus */
48
67
#ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
68
#define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
69
#endif
70
78
ALT_STATUS_CODE
alt_fpga_init
(
void
);
79
86
ALT_STATUS_CODE
alt_fpga_uninit
(
void
);
87
108
ALT_STATUS_CODE
alt_fpga_control_enable
(
void
);
109
118
ALT_STATUS_CODE
alt_fpga_control_disable
(
void
);
119
128
bool
alt_fpga_control_is_enabled
(
void
);
129
134
typedef
enum
ALT_FPGA_STATE_e
135
{
146
ALT_FPGA_STATE_POWER_UP
= 0x0,
147
154
ALT_FPGA_STATE_RESET
= 0x1,
155
162
ALT_FPGA_STATE_CFG
= 0x2,
163
169
ALT_FPGA_STATE_INIT
= 0x3,
170
176
ALT_FPGA_STATE_USER_MODE
= 0x4,
177
182
ALT_FPGA_STATE_UNKNOWN
= 0x5,
183
194
ALT_FPGA_STATE_POWER_OFF
= 0xF
195
196
}
ALT_FPGA_STATE_t
;
197
203
ALT_FPGA_STATE_t
alt_fpga_state_get
(
void
);
204
209
typedef
enum
ALT_FPGA_MON_STATUS_e
210
{
215
ALT_FPGA_MON_nSTATUS
= 0x0001,
216
221
ALT_FPGA_MON_CONF_DONE
= 0x0002,
222
227
ALT_FPGA_MON_INIT_DONE
= 0x0004,
228
233
ALT_FPGA_MON_CRC_ERROR
= 0x0008,
234
239
ALT_FPGA_MON_CVP_CONF_DONE
= 0x0010,
240
245
ALT_FPGA_MON_PR_READY
= 0x0020,
246
251
ALT_FPGA_MON_PR_ERROR
= 0x0040,
252
257
ALT_FPGA_MON_PR_DONE
= 0x0080,
258
267
ALT_FPGA_MON_nCONFIG_PIN
= 0x0100,
268
277
ALT_FPGA_MON_nSTATUS_PIN
= 0x0200,
278
287
ALT_FPGA_MON_CONF_DONE_PIN
= 0x0400,
288
292
ALT_FPGA_MON_FPGA_POWER_ON
= 0x0800
293
294
}
ALT_FPGA_MON_STATUS_t
;
295
312
uint32_t
alt_fpga_mon_status_get
(
void
);
313
329
ALT_STATUS_CODE
alt_fpga_reset_assert
(
void
);
330
345
ALT_STATUS_CODE
alt_fpga_reset_deassert
(
void
);
346
366
typedef
enum
ALT_FPGA_CFG_MODE_e
367
{
372
ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC
= 0x0,
373
378
ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC
= 0x1,
379
384
ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC
= 0x2,
385
390
ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC
= 0x4,
391
396
ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC
= 0x5,
397
402
ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC
= 0x6,
403
408
ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC
= 0x8,
409
414
ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC
= 0x9,
415
420
ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC
= 0xa,
421
426
ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC
= 0xc,
427
432
ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC
= 0xd,
433
438
ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC
= 0xe,
439
443
ALT_FPGA_CFG_MODE_UNKNOWN
= 0x20
444
445
}
ALT_FPGA_CFG_MODE_t
;
446
456
ALT_FPGA_CFG_MODE_t
alt_fpga_cfg_mode_get
(
void
);
457
478
ALT_STATUS_CODE
alt_fpga_cfg_mode_set
(
ALT_FPGA_CFG_MODE_t
cfg_mode);
479
523
typedef
int32_t (*
alt_fpga_istream_t
)(
void
* buf,
size_t
buf_len,
void
* user_data);
524
564
ALT_STATUS_CODE
alt_fpga_configure
(
const
void
* cfg_buf,
565
size_t
cfg_buf_len);
566
567
#if ALT_FPGA_ENABLE_DMA_SUPPORT
568
603
ALT_STATUS_CODE alt_fpga_configure_dma(
const
void
* cfg_buf,
604
size_t
cfg_buf_len,
605
ALT_DMA_CHANNEL_t
dma_channel);
606
607
#endif
608
643
ALT_STATUS_CODE
alt_fpga_istream_configure
(
alt_fpga_istream_t
cfg_stream,
644
void
* user_data);
645
646
#if ALT_FPGA_ENABLE_DMA_SUPPORT
647
685
ALT_STATUS_CODE alt_fpga_istream_configure_dma(
alt_fpga_istream_t
cfg_stream,
686
void
* user_data,
687
ALT_DMA_CHANNEL_t
dma_channel);
688
689
#endif
690
751
ALT_STATUS_CODE
alt_fpga_man_irq_disable
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
752
775
ALT_STATUS_CODE
alt_fpga_man_irq_enable
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
776
788
uint32_t
alt_fpga_man_irq_type_get
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
789
804
ALT_STATUS_CODE
alt_fpga_man_irq_type_set
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask,
805
ALT_FPGA_MON_STATUS_t
mon_stat_config);
806
817
uint32_t
alt_fpga_man_irq_pol_get
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
818
833
ALT_STATUS_CODE
alt_fpga_man_irq_pol_set
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask,
834
ALT_FPGA_MON_STATUS_t
mon_stat_config);
835
856
typedef
enum
ALT_FPGA_GPI_e
857
{
859
ALT_FPGA_GPI_0
= (int32_t)(1UL << 0),
860
862
ALT_FPGA_GPI_1
= (int32_t)(1UL << 1),
863
865
ALT_FPGA_GPI_2
= (int32_t)(1UL << 2),
866
868
ALT_FPGA_GPI_3
= (int32_t)(1UL << 3),
869
871
ALT_FPGA_GPI_4
= (int32_t)(1UL << 4),
872
874
ALT_FPGA_GPI_5
= (int32_t)(1UL << 5),
875
877
ALT_FPGA_GPI_6
= (int32_t)(1UL << 6),
878
880
ALT_FPGA_GPI_7
= (int32_t)(1UL << 7),
881
883
ALT_FPGA_GPI_8
= (int32_t)(1UL << 8),
884
886
ALT_FPGA_GPI_9
= (int32_t)(1UL << 9),
887
889
ALT_FPGA_GPI_10
= (int32_t)(1UL << 10),
890
892
ALT_FPGA_GPI_11
= (int32_t)(1UL << 11),
893
895
ALT_FPGA_GPI_12
= (int32_t)(1UL << 12),
896
898
ALT_FPGA_GPI_13
= (int32_t)(1UL << 13),
899
901
ALT_FPGA_GPI_14
= (int32_t)(1UL << 14),
902
904
ALT_FPGA_GPI_15
= (int32_t)(1UL << 15),
905
907
ALT_FPGA_GPI_16
= (int32_t)(1UL << 16),
908
910
ALT_FPGA_GPI_17
= (int32_t)(1UL << 17),
911
913
ALT_FPGA_GPI_18
= (int32_t)(1UL << 18),
914
916
ALT_FPGA_GPI_19
= (int32_t)(1UL << 19),
917
919
ALT_FPGA_GPI_20
= (int32_t)(1UL << 20),
920
922
ALT_FPGA_GPI_21
= (int32_t)(1UL << 21),
923
925
ALT_FPGA_GPI_22
= (int32_t)(1UL << 22),
926
928
ALT_FPGA_GPI_23
= (int32_t)(1UL << 23),
929
931
ALT_FPGA_GPI_24
= (int32_t)(1UL << 24),
932
934
ALT_FPGA_GPI_25
= (int32_t)(1UL << 25),
935
937
ALT_FPGA_GPI_26
= (int32_t)(1UL << 26),
938
940
ALT_FPGA_GPI_27
= (int32_t)(1UL << 27),
941
943
ALT_FPGA_GPI_28
= (int32_t)(1UL << 28),
944
946
ALT_FPGA_GPI_29
= (int32_t)(1UL << 29),
947
949
ALT_FPGA_GPI_30
= (int32_t)(1UL << 30),
950
952
ALT_FPGA_GPI_31
= (int32_t)(1UL << 31)
953
954
}
ALT_FPGA_GPI_t
;
955
973
uint32_t
alt_fpga_gpi_read
(uint32_t mask);
974
979
typedef
enum
ALT_FPGA_GPO_e
980
{
982
ALT_FPGA_GPO_0
= (int32_t)(1UL << 0),
983
985
ALT_FPGA_GPO_1
= (int32_t)(1UL << 1),
986
988
ALT_FPGA_GPO_2
= (int32_t)(1UL << 2),
989
991
ALT_FPGA_GPO_3
= (int32_t)(1UL << 3),
992
994
ALT_FPGA_GPO_4
= (int32_t)(1UL << 4),
995
997
ALT_FPGA_GPO_5
= (int32_t)(1UL << 5),
998
1000
ALT_FPGA_GPO_6
= (int32_t)(1UL << 6),
1001
1003
ALT_FPGA_GPO_7
= (int32_t)(1UL << 7),
1004
1006
ALT_FPGA_GPO_8
= (int32_t)(1UL << 8),
1007
1009
ALT_FPGA_GPO_9
= (int32_t)(1UL << 9),
1010
1012
ALT_FPGA_GPO_10
= (int32_t)(1UL << 10),
1013
1015
ALT_FPGA_GPO_11
= (int32_t)(1UL << 11),
1016
1018
ALT_FPGA_GPO_12
= (int32_t)(1UL << 12),
1019
1021
ALT_FPGA_GPO_13
= (int32_t)(1UL << 13),
1022
1024
ALT_FPGA_GPO_14
= (int32_t)(1UL << 14),
1025
1027
ALT_FPGA_GPO_15
= (int32_t)(1UL << 15),
1028
1030
ALT_FPGA_GPO_16
= (int32_t)(1UL << 16),
1031
1033
ALT_FPGA_GPO_17
= (int32_t)(1UL << 17),
1034
1036
ALT_FPGA_GPO_18
= (int32_t)(1UL << 18),
1037
1039
ALT_FPGA_GPO_19
= (int32_t)(1UL << 19),
1040
1042
ALT_FPGA_GPO_20
= (int32_t)(1UL << 20),
1043
1045
ALT_FPGA_GPO_21
= (int32_t)(1UL << 21),
1046
1048
ALT_FPGA_GPO_22
= (int32_t)(1UL << 22),
1049
1051
ALT_FPGA_GPO_23
= (int32_t)(1UL << 23),
1052
1054
ALT_FPGA_GPO_24
= (int32_t)(1UL << 24),
1055
1057
ALT_FPGA_GPO_25
= (int32_t)(1UL << 25),
1058
1060
ALT_FPGA_GPO_26
= (int32_t)(1UL << 26),
1061
1063
ALT_FPGA_GPO_27
= (int32_t)(1UL << 27),
1064
1066
ALT_FPGA_GPO_28
= (int32_t)(1UL << 28),
1067
1069
ALT_FPGA_GPO_29
= (int32_t)(1UL << 29),
1070
1072
ALT_FPGA_GPO_30
= (int32_t)(1UL << 30),
1073
1075
ALT_FPGA_GPO_31
= (int32_t)(1UL << 31)
1076
1077
}
ALT_FPGA_GPO_t
;
1078
1103
ALT_STATUS_CODE
alt_fpga_gpo_write
(uint32_t mask, uint32_t value);
1104
1113
#ifdef __cplusplus
1114
}
1115
#endif
/* __cplusplus */
1116
1117
#endif
/* __ALT_FPGA_MGR_H__ */
include
soc_cv_av
alt_fpga_manager.h
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