35 #ifndef __ALT_SOCAL_SOC_NOC_FW_DDR_SCR_H__
36 #define __ALT_SOCAL_SOC_NOC_FW_DDR_SCR_H__
91 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_LSB 0
93 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_MSB 0
95 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_WIDTH 1
97 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_SET_MSK 0x00000001
99 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
101 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_RESET 0x0
103 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
105 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
117 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_LSB 1
119 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_MSB 1
121 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_WIDTH 1
123 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_SET_MSK 0x00000002
125 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
127 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_RESET 0x0
129 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
131 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
143 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_LSB 2
145 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_MSB 2
147 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_WIDTH 1
149 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_SET_MSK 0x00000004
151 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
153 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_RESET 0x0
155 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
157 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
169 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_LSB 3
171 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_MSB 3
173 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_WIDTH 1
175 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_SET_MSK 0x00000008
177 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
179 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_RESET 0x0
181 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
183 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
195 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_LSB 4
197 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_MSB 4
199 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_WIDTH 1
201 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_SET_MSK 0x00000010
203 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_CLR_MSK 0xffffffef
205 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_RESET 0x0
207 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
209 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
221 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_LSB 5
223 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_MSB 5
225 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_WIDTH 1
227 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_SET_MSK 0x00000020
229 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
231 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_RESET 0x0
233 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
235 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
247 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_LSB 6
249 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_MSB 6
251 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_WIDTH 1
253 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_SET_MSK 0x00000040
255 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
257 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_RESET 0x0
259 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
261 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
273 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_LSB 7
275 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_MSB 7
277 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_WIDTH 1
279 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_SET_MSK 0x00000080
281 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
283 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_RESET 0x0
285 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
287 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
299 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_LSB 8
301 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_MSB 8
303 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_WIDTH 1
305 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_SET_MSK 0x00000100
307 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
309 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_RESET 0x0
311 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
313 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
325 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_LSB 9
327 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_MSB 9
329 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_WIDTH 1
331 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_SET_MSK 0x00000200
333 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
335 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_RESET 0x0
337 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
339 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
351 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_LSB 10
353 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_MSB 10
355 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_WIDTH 1
357 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_SET_MSK 0x00000400
359 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
361 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_RESET 0x0
363 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
365 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
377 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_LSB 11
379 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_MSB 11
381 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_WIDTH 1
383 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_SET_MSK 0x00000800
385 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
387 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_RESET 0x0
389 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
391 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
403 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_LSB 12
405 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_MSB 12
407 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_WIDTH 1
409 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_SET_MSK 0x00001000
411 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
413 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_RESET 0x0
415 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
417 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
429 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_LSB 13
431 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_MSB 13
433 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_WIDTH 1
435 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_SET_MSK 0x00002000
437 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
439 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_RESET 0x0
441 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
443 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
455 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_LSB 14
457 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_MSB 14
459 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_WIDTH 1
461 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_SET_MSK 0x00004000
463 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
465 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_RESET 0x0
467 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
469 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
481 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_LSB 15
483 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_MSB 15
485 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_WIDTH 1
487 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_SET_MSK 0x00008000
489 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
491 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_RESET 0x0
493 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
495 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
509 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_s
511 volatile uint32_t mpuregion0enable : 1;
512 volatile uint32_t mpuregion1enable : 1;
513 volatile uint32_t mpuregion2enable : 1;
514 volatile uint32_t mpuregion3enable : 1;
515 volatile uint32_t mpuregion4enable : 1;
516 volatile uint32_t mpuregion5enable : 1;
517 volatile uint32_t mpuregion6enable : 1;
518 volatile uint32_t mpuregion7enable : 1;
519 volatile uint32_t nonmpuregion0enable : 1;
520 volatile uint32_t nonmpuregion1enable : 1;
521 volatile uint32_t nonmpuregion2enable : 1;
522 volatile uint32_t nonmpuregion3enable : 1;
523 volatile uint32_t nonmpuregion4enable : 1;
524 volatile uint32_t nonmpuregion5enable : 1;
525 volatile uint32_t nonmpuregion6enable : 1;
526 volatile uint32_t nonmpuregion7enable : 1;
531 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_t;
535 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_RESET 0x00000000
537 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_OFST 0x0
580 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_LSB 0
582 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_MSB 0
584 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_WIDTH 1
586 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_SET_MSK 0x00000001
588 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
590 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_RESET 0x0
592 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
594 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
609 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_LSB 1
611 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_MSB 1
613 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_WIDTH 1
615 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_SET_MSK 0x00000002
617 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
619 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_RESET 0x0
621 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
623 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
638 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_LSB 2
640 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_MSB 2
642 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_WIDTH 1
644 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_SET_MSK 0x00000004
646 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
648 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_RESET 0x0
650 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
652 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
667 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_LSB 3
669 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_MSB 3
671 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_WIDTH 1
673 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_SET_MSK 0x00000008
675 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
677 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_RESET 0x0
679 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
681 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
696 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_LSB 4
698 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_MSB 4
700 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_WIDTH 1
702 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_SET_MSK 0x00000010
704 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_CLR_MSK 0xffffffef
706 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_RESET 0x0
708 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
710 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
725 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_LSB 5
727 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_MSB 5
729 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_WIDTH 1
731 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_SET_MSK 0x00000020
733 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
735 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_RESET 0x0
737 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
739 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
754 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_LSB 6
756 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_MSB 6
758 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_WIDTH 1
760 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_SET_MSK 0x00000040
762 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
764 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_RESET 0x0
766 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
768 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
783 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_LSB 7
785 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_MSB 7
787 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_WIDTH 1
789 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_SET_MSK 0x00000080
791 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
793 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_RESET 0x0
795 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
797 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
812 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_LSB 8
814 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_MSB 8
816 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_WIDTH 1
818 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_SET_MSK 0x00000100
820 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
822 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_RESET 0x0
824 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
826 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
841 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_LSB 9
843 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_MSB 9
845 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_WIDTH 1
847 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_SET_MSK 0x00000200
849 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
851 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_RESET 0x0
853 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
855 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
870 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_LSB 10
872 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_MSB 10
874 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_WIDTH 1
876 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_SET_MSK 0x00000400
878 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
880 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_RESET 0x0
882 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
884 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
899 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_LSB 11
901 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_MSB 11
903 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_WIDTH 1
905 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_SET_MSK 0x00000800
907 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
909 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_RESET 0x0
911 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
913 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
928 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_LSB 12
930 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_MSB 12
932 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_WIDTH 1
934 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_SET_MSK 0x00001000
936 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
938 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_RESET 0x0
940 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
942 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
957 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_LSB 13
959 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_MSB 13
961 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_WIDTH 1
963 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_SET_MSK 0x00002000
965 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
967 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_RESET 0x0
969 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
971 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
986 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_LSB 14
988 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_MSB 14
990 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_WIDTH 1
992 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_SET_MSK 0x00004000
994 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
996 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_RESET 0x0
998 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
1000 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
1015 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_LSB 15
1017 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_MSB 15
1019 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_WIDTH 1
1021 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_SET_MSK 0x00008000
1023 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
1025 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_RESET 0x0
1027 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
1029 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
1031 #ifndef __ASSEMBLY__
1043 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_s
1045 volatile uint32_t mpuregion0enable : 1;
1046 volatile uint32_t mpuregion1enable : 1;
1047 volatile uint32_t mpuregion2enable : 1;
1048 volatile uint32_t mpuregion3enable : 1;
1049 volatile uint32_t mpuregion4enable : 1;
1050 volatile uint32_t mpuregion5enable : 1;
1051 volatile uint32_t mpuregion6enable : 1;
1052 volatile uint32_t mpuregion7enable : 1;
1053 volatile uint32_t nonmpuregion0enable : 1;
1054 volatile uint32_t nonmpuregion1enable : 1;
1055 volatile uint32_t nonmpuregion2enable : 1;
1056 volatile uint32_t nonmpuregion3enable : 1;
1057 volatile uint32_t nonmpuregion4enable : 1;
1058 volatile uint32_t nonmpuregion5enable : 1;
1059 volatile uint32_t nonmpuregion6enable : 1;
1060 volatile uint32_t nonmpuregion7enable : 1;
1065 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_t;
1069 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_RESET 0x00000000
1071 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_OFST 0x4
1114 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_LSB 0
1116 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_MSB 0
1118 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_WIDTH 1
1120 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_SET_MSK 0x00000001
1122 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_CLR_MSK 0xfffffffe
1124 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_RESET 0x0
1126 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_GET(value) (((value) & 0x00000001) >> 0)
1128 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION0ENABLE_SET(value) (((value) << 0) & 0x00000001)
1143 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_LSB 1
1145 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_MSB 1
1147 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_WIDTH 1
1149 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_SET_MSK 0x00000002
1151 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_CLR_MSK 0xfffffffd
1153 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_RESET 0x0
1155 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_GET(value) (((value) & 0x00000002) >> 1)
1157 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION1ENABLE_SET(value) (((value) << 1) & 0x00000002)
1172 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_LSB 2
1174 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_MSB 2
1176 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_WIDTH 1
1178 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_SET_MSK 0x00000004
1180 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_CLR_MSK 0xfffffffb
1182 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_RESET 0x0
1184 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_GET(value) (((value) & 0x00000004) >> 2)
1186 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION2ENABLE_SET(value) (((value) << 2) & 0x00000004)
1201 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_LSB 3
1203 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_MSB 3
1205 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_WIDTH 1
1207 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_SET_MSK 0x00000008
1209 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_CLR_MSK 0xfffffff7
1211 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_RESET 0x0
1213 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_GET(value) (((value) & 0x00000008) >> 3)
1215 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION3ENABLE_SET(value) (((value) << 3) & 0x00000008)
1230 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_LSB 4
1232 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_MSB 4
1234 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_WIDTH 1
1236 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_SET_MSK 0x00000010
1238 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_CLR_MSK 0xffffffef
1240 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_RESET 0x0
1242 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_GET(value) (((value) & 0x00000010) >> 4)
1244 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION4ENABLE_SET(value) (((value) << 4) & 0x00000010)
1259 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_LSB 5
1261 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_MSB 5
1263 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_WIDTH 1
1265 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_SET_MSK 0x00000020
1267 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_CLR_MSK 0xffffffdf
1269 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_RESET 0x0
1271 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_GET(value) (((value) & 0x00000020) >> 5)
1273 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION5ENABLE_SET(value) (((value) << 5) & 0x00000020)
1288 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_LSB 6
1290 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_MSB 6
1292 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_WIDTH 1
1294 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_SET_MSK 0x00000040
1296 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_CLR_MSK 0xffffffbf
1298 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_RESET 0x0
1300 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_GET(value) (((value) & 0x00000040) >> 6)
1302 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION6ENABLE_SET(value) (((value) << 6) & 0x00000040)
1317 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_LSB 7
1319 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_MSB 7
1321 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_WIDTH 1
1323 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_SET_MSK 0x00000080
1325 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_CLR_MSK 0xffffff7f
1327 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_RESET 0x0
1329 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_GET(value) (((value) & 0x00000080) >> 7)
1331 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_MPUREGION7ENABLE_SET(value) (((value) << 7) & 0x00000080)
1346 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_LSB 8
1348 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_MSB 8
1350 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_WIDTH 1
1352 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_SET_MSK 0x00000100
1354 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_CLR_MSK 0xfffffeff
1356 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_RESET 0x0
1358 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_GET(value) (((value) & 0x00000100) >> 8)
1360 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION0ENABLE_SET(value) (((value) << 8) & 0x00000100)
1375 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_LSB 9
1377 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_MSB 9
1379 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_WIDTH 1
1381 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_SET_MSK 0x00000200
1383 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_CLR_MSK 0xfffffdff
1385 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_RESET 0x0
1387 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_GET(value) (((value) & 0x00000200) >> 9)
1389 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION1ENABLE_SET(value) (((value) << 9) & 0x00000200)
1404 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_LSB 10
1406 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_MSB 10
1408 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_WIDTH 1
1410 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_SET_MSK 0x00000400
1412 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_CLR_MSK 0xfffffbff
1414 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_RESET 0x0
1416 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_GET(value) (((value) & 0x00000400) >> 10)
1418 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION2ENABLE_SET(value) (((value) << 10) & 0x00000400)
1433 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_LSB 11
1435 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_MSB 11
1437 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_WIDTH 1
1439 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_SET_MSK 0x00000800
1441 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_CLR_MSK 0xfffff7ff
1443 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_RESET 0x0
1445 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_GET(value) (((value) & 0x00000800) >> 11)
1447 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION3ENABLE_SET(value) (((value) << 11) & 0x00000800)
1462 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_LSB 12
1464 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_MSB 12
1466 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_WIDTH 1
1468 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_SET_MSK 0x00001000
1470 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_CLR_MSK 0xffffefff
1472 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_RESET 0x0
1474 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_GET(value) (((value) & 0x00001000) >> 12)
1476 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION4ENABLE_SET(value) (((value) << 12) & 0x00001000)
1491 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_LSB 13
1493 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_MSB 13
1495 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_WIDTH 1
1497 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_SET_MSK 0x00002000
1499 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_CLR_MSK 0xffffdfff
1501 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_RESET 0x0
1503 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_GET(value) (((value) & 0x00002000) >> 13)
1505 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION5ENABLE_SET(value) (((value) << 13) & 0x00002000)
1520 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_LSB 14
1522 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_MSB 14
1524 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_WIDTH 1
1526 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_SET_MSK 0x00004000
1528 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_CLR_MSK 0xffffbfff
1530 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_RESET 0x0
1532 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_GET(value) (((value) & 0x00004000) >> 14)
1534 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION6ENABLE_SET(value) (((value) << 14) & 0x00004000)
1549 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_LSB 15
1551 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_MSB 15
1553 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_WIDTH 1
1555 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_SET_MSK 0x00008000
1557 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_CLR_MSK 0xffff7fff
1559 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_RESET 0x0
1561 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_GET(value) (((value) & 0x00008000) >> 15)
1563 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_NONMPUREGION7ENABLE_SET(value) (((value) << 15) & 0x00008000)
1565 #ifndef __ASSEMBLY__
1577 struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_s
1579 volatile uint32_t mpuregion0enable : 1;
1580 volatile uint32_t mpuregion1enable : 1;
1581 volatile uint32_t mpuregion2enable : 1;
1582 volatile uint32_t mpuregion3enable : 1;
1583 volatile uint32_t mpuregion4enable : 1;
1584 volatile uint32_t mpuregion5enable : 1;
1585 volatile uint32_t mpuregion6enable : 1;
1586 volatile uint32_t mpuregion7enable : 1;
1587 volatile uint32_t nonmpuregion0enable : 1;
1588 volatile uint32_t nonmpuregion1enable : 1;
1589 volatile uint32_t nonmpuregion2enable : 1;
1590 volatile uint32_t nonmpuregion3enable : 1;
1591 volatile uint32_t nonmpuregion4enable : 1;
1592 volatile uint32_t nonmpuregion5enable : 1;
1593 volatile uint32_t nonmpuregion6enable : 1;
1594 volatile uint32_t nonmpuregion7enable : 1;
1599 typedef struct ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_s ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_t;
1603 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_RESET 0x00000000
1605 #define ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_OFST 0x8
1629 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_LSB 0
1631 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_MSB 15
1633 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_WIDTH 16
1635 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_SET_MSK 0x0000ffff
1637 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_CLR_MSK 0xffff0000
1639 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_RESET 0x0
1641 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1643 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1654 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_LSB 16
1656 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_MSB 31
1658 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_WIDTH 16
1660 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_SET_MSK 0xffff0000
1662 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1664 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_RESET 0x0
1666 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1668 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1670 #ifndef __ASSEMBLY__
1682 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_s
1684 const volatile uint32_t low : 16;
1685 volatile uint32_t high : 16;
1689 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_t;
1693 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_RESET 0x00000000
1695 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_OFST 0x10
1719 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_LSB 0
1721 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_MSB 4
1723 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_WIDTH 5
1725 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
1727 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
1729 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_RESET 0x0
1731 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1733 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1735 #ifndef __ASSEMBLY__
1747 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_s
1749 volatile uint32_t low : 5;
1754 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_t;
1758 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_RESET 0x00000000
1760 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_OFST 0x14
1784 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_LSB 0
1786 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_MSB 15
1788 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_WIDTH 16
1790 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
1792 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
1794 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_RESET 0xffff
1796 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1798 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1809 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_LSB 16
1811 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_MSB 31
1813 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_WIDTH 16
1815 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
1817 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
1819 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_RESET 0x0
1821 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1823 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1825 #ifndef __ASSEMBLY__
1837 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_s
1839 const volatile uint32_t low : 16;
1840 volatile uint32_t high : 16;
1844 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_t;
1848 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_RESET 0x0000ffff
1850 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_OFST 0x18
1874 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_LSB 0
1876 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_MSB 4
1878 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_WIDTH 5
1880 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
1882 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
1884 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_RESET 0x0
1886 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
1888 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
1890 #ifndef __ASSEMBLY__
1902 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_s
1904 volatile uint32_t low : 5;
1909 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_t;
1913 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_RESET 0x00000000
1915 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_OFST 0x1c
1939 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_LSB 0
1941 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_MSB 15
1943 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_WIDTH 16
1945 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_SET_MSK 0x0000ffff
1947 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_CLR_MSK 0xffff0000
1949 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_RESET 0x0
1951 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
1953 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
1964 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_LSB 16
1966 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_MSB 31
1968 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_WIDTH 16
1970 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_SET_MSK 0xffff0000
1972 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
1974 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_RESET 0x0
1976 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
1978 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
1980 #ifndef __ASSEMBLY__
1992 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_s
1994 const volatile uint32_t low : 16;
1995 volatile uint32_t high : 16;
1999 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_t;
2003 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_RESET 0x00000000
2005 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_OFST 0x20
2029 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_LSB 0
2031 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_MSB 4
2033 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_WIDTH 5
2035 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2037 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2039 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_RESET 0x0
2041 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2043 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2045 #ifndef __ASSEMBLY__
2057 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_s
2059 volatile uint32_t low : 5;
2064 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_t;
2068 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_RESET 0x00000000
2070 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_OFST 0x24
2094 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_LSB 0
2096 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_MSB 15
2098 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_WIDTH 16
2100 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2102 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2104 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_RESET 0xffff
2106 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2108 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2119 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_LSB 16
2121 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_MSB 31
2123 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_WIDTH 16
2125 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2127 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2129 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_RESET 0x0
2131 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2133 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2135 #ifndef __ASSEMBLY__
2147 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_s
2149 const volatile uint32_t low : 16;
2150 volatile uint32_t high : 16;
2154 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_t;
2158 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_RESET 0x0000ffff
2160 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_OFST 0x28
2184 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_LSB 0
2186 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_MSB 4
2188 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_WIDTH 5
2190 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2192 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2194 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_RESET 0x0
2196 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2198 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2200 #ifndef __ASSEMBLY__
2212 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_s
2214 volatile uint32_t low : 5;
2219 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_t;
2223 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_RESET 0x00000000
2225 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_OFST 0x2c
2249 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_LSB 0
2251 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_MSB 15
2253 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_WIDTH 16
2255 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_SET_MSK 0x0000ffff
2257 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_CLR_MSK 0xffff0000
2259 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_RESET 0x0
2261 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2263 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2274 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_LSB 16
2276 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_MSB 31
2278 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_WIDTH 16
2280 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_SET_MSK 0xffff0000
2282 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2284 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_RESET 0x0
2286 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2288 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2290 #ifndef __ASSEMBLY__
2302 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_s
2304 const volatile uint32_t low : 16;
2305 volatile uint32_t high : 16;
2309 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_t;
2313 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_RESET 0x00000000
2315 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_OFST 0x30
2339 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_LSB 0
2341 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_MSB 4
2343 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_WIDTH 5
2345 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2347 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2349 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_RESET 0x0
2351 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2353 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2355 #ifndef __ASSEMBLY__
2367 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_s
2369 volatile uint32_t low : 5;
2374 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_t;
2378 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_RESET 0x00000000
2380 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_OFST 0x34
2404 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_LSB 0
2406 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_MSB 15
2408 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_WIDTH 16
2410 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2412 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2414 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_RESET 0xffff
2416 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2418 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2429 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_LSB 16
2431 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_MSB 31
2433 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_WIDTH 16
2435 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2437 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2439 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_RESET 0x0
2441 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2443 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2445 #ifndef __ASSEMBLY__
2457 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_s
2459 const volatile uint32_t low : 16;
2460 volatile uint32_t high : 16;
2464 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_t;
2468 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_RESET 0x0000ffff
2470 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_OFST 0x38
2494 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_LSB 0
2496 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_MSB 4
2498 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_WIDTH 5
2500 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2502 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2504 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_RESET 0x0
2506 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2508 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2510 #ifndef __ASSEMBLY__
2522 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_s
2524 volatile uint32_t low : 5;
2529 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_t;
2533 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_RESET 0x00000000
2535 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_OFST 0x3c
2559 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_LSB 0
2561 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_MSB 15
2563 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_WIDTH 16
2565 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_SET_MSK 0x0000ffff
2567 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_CLR_MSK 0xffff0000
2569 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_RESET 0x0
2571 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2573 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2584 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_LSB 16
2586 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_MSB 31
2588 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_WIDTH 16
2590 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_SET_MSK 0xffff0000
2592 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2594 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_RESET 0x0
2596 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2598 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2600 #ifndef __ASSEMBLY__
2612 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_s
2614 const volatile uint32_t low : 16;
2615 volatile uint32_t high : 16;
2619 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_t;
2623 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_RESET 0x00000000
2625 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_OFST 0x40
2649 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_LSB 0
2651 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_MSB 4
2653 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_WIDTH 5
2655 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2657 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2659 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_RESET 0x0
2661 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2663 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2665 #ifndef __ASSEMBLY__
2677 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_s
2679 volatile uint32_t low : 5;
2684 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_t;
2688 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_RESET 0x00000000
2690 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_OFST 0x44
2714 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_LSB 0
2716 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_MSB 15
2718 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_WIDTH 16
2720 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
2722 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
2724 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_RESET 0xffff
2726 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2728 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2739 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_LSB 16
2741 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_MSB 31
2743 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_WIDTH 16
2745 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
2747 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
2749 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_RESET 0x0
2751 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2753 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2755 #ifndef __ASSEMBLY__
2767 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_s
2769 const volatile uint32_t low : 16;
2770 volatile uint32_t high : 16;
2774 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_t;
2778 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_RESET 0x0000ffff
2780 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_OFST 0x48
2804 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_LSB 0
2806 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_MSB 4
2808 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_WIDTH 5
2810 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
2812 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
2814 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_RESET 0x0
2816 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2818 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2820 #ifndef __ASSEMBLY__
2832 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_s
2834 volatile uint32_t low : 5;
2839 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_t;
2843 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_RESET 0x00000000
2845 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_OFST 0x4c
2869 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_LSB 0
2871 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_MSB 15
2873 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_WIDTH 16
2875 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_SET_MSK 0x0000ffff
2877 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_CLR_MSK 0xffff0000
2879 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_RESET 0x0
2881 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
2883 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
2894 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_LSB 16
2896 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_MSB 31
2898 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_WIDTH 16
2900 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_SET_MSK 0xffff0000
2902 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
2904 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_RESET 0x0
2906 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
2908 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
2910 #ifndef __ASSEMBLY__
2922 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_s
2924 const volatile uint32_t low : 16;
2925 volatile uint32_t high : 16;
2929 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_t;
2933 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_RESET 0x00000000
2935 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_OFST 0x50
2959 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_LSB 0
2961 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_MSB 4
2963 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_WIDTH 5
2965 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
2967 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
2969 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_RESET 0x0
2971 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
2973 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
2975 #ifndef __ASSEMBLY__
2987 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_s
2989 volatile uint32_t low : 5;
2994 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_t;
2998 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_RESET 0x00000000
3000 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_OFST 0x54
3024 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_LSB 0
3026 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_MSB 15
3028 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_WIDTH 16
3030 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3032 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3034 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_RESET 0xffff
3036 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3038 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3049 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_LSB 16
3051 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_MSB 31
3053 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_WIDTH 16
3055 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3057 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3059 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_RESET 0x0
3061 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3063 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3065 #ifndef __ASSEMBLY__
3077 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_s
3079 const volatile uint32_t low : 16;
3080 volatile uint32_t high : 16;
3084 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_t;
3088 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_RESET 0x0000ffff
3090 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_OFST 0x58
3114 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_LSB 0
3116 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_MSB 4
3118 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_WIDTH 5
3120 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3122 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3124 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_RESET 0x0
3126 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3128 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3130 #ifndef __ASSEMBLY__
3142 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_s
3144 volatile uint32_t low : 5;
3149 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_t;
3153 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_RESET 0x00000000
3155 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_OFST 0x5c
3179 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_LSB 0
3181 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_MSB 15
3183 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_WIDTH 16
3185 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_SET_MSK 0x0000ffff
3187 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_CLR_MSK 0xffff0000
3189 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_RESET 0x0
3191 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3193 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3204 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_LSB 16
3206 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_MSB 31
3208 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_WIDTH 16
3210 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_SET_MSK 0xffff0000
3212 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3214 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_RESET 0x0
3216 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3218 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3220 #ifndef __ASSEMBLY__
3232 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_s
3234 const volatile uint32_t low : 16;
3235 volatile uint32_t high : 16;
3239 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_t;
3243 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_RESET 0x00000000
3245 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_OFST 0x60
3269 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_LSB 0
3271 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_MSB 4
3273 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_WIDTH 5
3275 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3277 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3279 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_RESET 0x0
3281 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3283 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3285 #ifndef __ASSEMBLY__
3297 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_s
3299 volatile uint32_t low : 5;
3304 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_t;
3308 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_RESET 0x00000000
3310 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_OFST 0x64
3334 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_LSB 0
3336 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_MSB 15
3338 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_WIDTH 16
3340 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3342 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3344 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_RESET 0xffff
3346 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3348 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3359 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_LSB 16
3361 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_MSB 31
3363 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_WIDTH 16
3365 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3367 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3369 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_RESET 0x0
3371 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3373 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3375 #ifndef __ASSEMBLY__
3387 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_s
3389 const volatile uint32_t low : 16;
3390 volatile uint32_t high : 16;
3394 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_t;
3398 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_RESET 0x0000ffff
3400 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_OFST 0x68
3424 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_LSB 0
3426 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_MSB 4
3428 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_WIDTH 5
3430 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3432 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3434 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_RESET 0x0
3436 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3438 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3440 #ifndef __ASSEMBLY__
3452 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_s
3454 volatile uint32_t low : 5;
3459 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_t;
3463 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_RESET 0x00000000
3465 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_OFST 0x6c
3489 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_LSB 0
3491 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_MSB 15
3493 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_WIDTH 16
3495 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_SET_MSK 0x0000ffff
3497 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_CLR_MSK 0xffff0000
3499 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_RESET 0x0
3501 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3503 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3514 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_LSB 16
3516 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_MSB 31
3518 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_WIDTH 16
3520 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_SET_MSK 0xffff0000
3522 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3524 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_RESET 0x0
3526 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3528 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3530 #ifndef __ASSEMBLY__
3542 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_s
3544 const volatile uint32_t low : 16;
3545 volatile uint32_t high : 16;
3549 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_t;
3553 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_RESET 0x00000000
3555 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_OFST 0x70
3579 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_LSB 0
3581 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_MSB 4
3583 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_WIDTH 5
3585 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3587 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3589 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_RESET 0x0
3591 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3593 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3595 #ifndef __ASSEMBLY__
3607 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_s
3609 volatile uint32_t low : 5;
3614 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_t;
3618 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_RESET 0x00000000
3620 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_OFST 0x74
3644 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_LSB 0
3646 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_MSB 15
3648 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_WIDTH 16
3650 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3652 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3654 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_RESET 0xffff
3656 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3658 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3669 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_LSB 16
3671 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_MSB 31
3673 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_WIDTH 16
3675 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3677 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3679 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_RESET 0x0
3681 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3683 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3685 #ifndef __ASSEMBLY__
3697 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_s
3699 const volatile uint32_t low : 16;
3700 volatile uint32_t high : 16;
3704 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_t;
3708 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_RESET 0x0000ffff
3710 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_OFST 0x78
3734 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_LSB 0
3736 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_MSB 4
3738 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_WIDTH 5
3740 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
3742 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
3744 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_RESET 0x0
3746 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3748 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3750 #ifndef __ASSEMBLY__
3762 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_s
3764 volatile uint32_t low : 5;
3769 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_t;
3773 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_RESET 0x00000000
3775 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_OFST 0x7c
3799 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_LSB 0
3801 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_MSB 15
3803 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_WIDTH 16
3805 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_SET_MSK 0x0000ffff
3807 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_CLR_MSK 0xffff0000
3809 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_RESET 0x0
3811 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3813 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3824 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_LSB 16
3826 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_MSB 31
3828 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_WIDTH 16
3830 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_SET_MSK 0xffff0000
3832 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
3834 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_RESET 0x0
3836 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3838 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3840 #ifndef __ASSEMBLY__
3852 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_s
3854 const volatile uint32_t low : 16;
3855 volatile uint32_t high : 16;
3859 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_t;
3863 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_RESET 0x00000000
3865 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_OFST 0x80
3889 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_LSB 0
3891 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_MSB 4
3893 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_WIDTH 5
3895 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
3897 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
3899 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_RESET 0x0
3901 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
3903 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
3905 #ifndef __ASSEMBLY__
3917 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_s
3919 volatile uint32_t low : 5;
3924 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_t;
3928 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_RESET 0x00000000
3930 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_OFST 0x84
3954 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_LSB 0
3956 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_MSB 15
3958 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_WIDTH 16
3960 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
3962 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
3964 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_RESET 0xffff
3966 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
3968 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
3979 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_LSB 16
3981 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_MSB 31
3983 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_WIDTH 16
3985 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
3987 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
3989 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_RESET 0x0
3991 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
3993 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
3995 #ifndef __ASSEMBLY__
4007 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_s
4009 const volatile uint32_t low : 16;
4010 volatile uint32_t high : 16;
4014 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_t;
4018 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_RESET 0x0000ffff
4020 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_OFST 0x88
4044 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_LSB 0
4046 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_MSB 4
4048 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_WIDTH 5
4050 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4052 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4054 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_RESET 0x0
4056 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4058 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4060 #ifndef __ASSEMBLY__
4072 struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_s
4074 volatile uint32_t low : 5;
4079 typedef struct ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_t;
4083 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_RESET 0x00000000
4085 #define ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_OFST 0x8c
4109 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_LSB 0
4111 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_MSB 15
4113 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_WIDTH 16
4115 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_SET_MSK 0x0000ffff
4117 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_CLR_MSK 0xffff0000
4119 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_RESET 0x0
4121 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4123 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4134 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_LSB 16
4136 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_MSB 31
4138 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_WIDTH 16
4140 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_SET_MSK 0xffff0000
4142 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4144 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_RESET 0x0
4146 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4148 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4150 #ifndef __ASSEMBLY__
4162 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_s
4164 const volatile uint32_t low : 16;
4165 volatile uint32_t high : 16;
4169 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_t;
4173 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_RESET 0x00000000
4175 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_OFST 0x90
4199 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_LSB 0
4201 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_MSB 4
4203 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_WIDTH 5
4205 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4207 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4209 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_RESET 0x0
4211 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4213 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4215 #ifndef __ASSEMBLY__
4227 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_s
4229 volatile uint32_t low : 5;
4234 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_t;
4238 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_RESET 0x00000000
4240 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_OFST 0x94
4264 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_LSB 0
4266 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_MSB 15
4268 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_WIDTH 16
4270 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4272 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4274 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_RESET 0xffff
4276 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4278 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4289 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_LSB 16
4291 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_MSB 31
4293 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_WIDTH 16
4295 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4297 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4299 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_RESET 0x0
4301 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4303 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4305 #ifndef __ASSEMBLY__
4317 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_s
4319 const volatile uint32_t low : 16;
4320 volatile uint32_t high : 16;
4324 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_t;
4328 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_RESET 0x0000ffff
4330 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_OFST 0x98
4354 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_LSB 0
4356 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_MSB 4
4358 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_WIDTH 5
4360 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4362 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4364 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_RESET 0x0
4366 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4368 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4370 #ifndef __ASSEMBLY__
4382 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_s
4384 volatile uint32_t low : 5;
4389 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_t;
4393 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_RESET 0x00000000
4395 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_OFST 0x9c
4419 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_LSB 0
4421 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_MSB 15
4423 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_WIDTH 16
4425 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_SET_MSK 0x0000ffff
4427 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_CLR_MSK 0xffff0000
4429 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_RESET 0x0
4431 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4433 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4444 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_LSB 16
4446 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_MSB 31
4448 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_WIDTH 16
4450 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_SET_MSK 0xffff0000
4452 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4454 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_RESET 0x0
4456 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4458 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4460 #ifndef __ASSEMBLY__
4472 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_s
4474 const volatile uint32_t low : 16;
4475 volatile uint32_t high : 16;
4479 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_t;
4483 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_RESET 0x00000000
4485 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_OFST 0xa0
4509 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_LSB 0
4511 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_MSB 4
4513 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_WIDTH 5
4515 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4517 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4519 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_RESET 0x0
4521 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4523 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4525 #ifndef __ASSEMBLY__
4537 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_s
4539 volatile uint32_t low : 5;
4544 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_t;
4548 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_RESET 0x00000000
4550 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_OFST 0xa4
4574 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_LSB 0
4576 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_MSB 15
4578 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_WIDTH 16
4580 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4582 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4584 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_RESET 0xffff
4586 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4588 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4599 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_LSB 16
4601 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_MSB 31
4603 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_WIDTH 16
4605 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4607 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4609 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_RESET 0x0
4611 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4613 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4615 #ifndef __ASSEMBLY__
4627 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_s
4629 const volatile uint32_t low : 16;
4630 volatile uint32_t high : 16;
4634 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_t;
4638 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_RESET 0x0000ffff
4640 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_OFST 0xa8
4664 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_LSB 0
4666 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_MSB 4
4668 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_WIDTH 5
4670 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4672 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4674 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_RESET 0x0
4676 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4678 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4680 #ifndef __ASSEMBLY__
4692 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_s
4694 volatile uint32_t low : 5;
4699 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_t;
4703 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_RESET 0x00000000
4705 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_OFST 0xac
4729 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_LSB 0
4731 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_MSB 15
4733 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_WIDTH 16
4735 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_SET_MSK 0x0000ffff
4737 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_CLR_MSK 0xffff0000
4739 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_RESET 0x0
4741 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4743 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4754 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_LSB 16
4756 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_MSB 31
4758 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_WIDTH 16
4760 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_SET_MSK 0xffff0000
4762 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
4764 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_RESET 0x0
4766 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4768 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4770 #ifndef __ASSEMBLY__
4782 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_s
4784 const volatile uint32_t low : 16;
4785 volatile uint32_t high : 16;
4789 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_t;
4793 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_RESET 0x00000000
4795 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_OFST 0xb0
4819 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_LSB 0
4821 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_MSB 4
4823 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_WIDTH 5
4825 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
4827 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
4829 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_RESET 0x0
4831 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4833 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4835 #ifndef __ASSEMBLY__
4847 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_s
4849 volatile uint32_t low : 5;
4854 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_t;
4858 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_RESET 0x00000000
4860 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_OFST 0xb4
4884 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_LSB 0
4886 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_MSB 15
4888 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_WIDTH 16
4890 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
4892 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
4894 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_RESET 0xffff
4896 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
4898 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
4909 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_LSB 16
4911 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_MSB 31
4913 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_WIDTH 16
4915 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
4917 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
4919 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_RESET 0x0
4921 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
4923 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
4925 #ifndef __ASSEMBLY__
4937 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_s
4939 const volatile uint32_t low : 16;
4940 volatile uint32_t high : 16;
4944 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_t;
4948 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_RESET 0x0000ffff
4950 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_OFST 0xb8
4974 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_LSB 0
4976 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_MSB 4
4978 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_WIDTH 5
4980 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
4982 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
4984 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_RESET 0x0
4986 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
4988 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
4990 #ifndef __ASSEMBLY__
5002 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_s
5004 volatile uint32_t low : 5;
5009 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_t;
5013 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_RESET 0x00000000
5015 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_OFST 0xbc
5039 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_LSB 0
5041 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_MSB 15
5043 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_WIDTH 16
5045 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_SET_MSK 0x0000ffff
5047 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_CLR_MSK 0xffff0000
5049 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_RESET 0x0
5051 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5053 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5064 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_LSB 16
5066 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_MSB 31
5068 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_WIDTH 16
5070 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_SET_MSK 0xffff0000
5072 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5074 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_RESET 0x0
5076 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5078 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5080 #ifndef __ASSEMBLY__
5092 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_s
5094 const volatile uint32_t low : 16;
5095 volatile uint32_t high : 16;
5099 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_t;
5103 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_RESET 0x00000000
5105 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_OFST 0xc0
5129 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_LSB 0
5131 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_MSB 4
5133 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_WIDTH 5
5135 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5137 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5139 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_RESET 0x0
5141 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5143 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5145 #ifndef __ASSEMBLY__
5157 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_s
5159 volatile uint32_t low : 5;
5164 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_t;
5168 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_RESET 0x00000000
5170 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_OFST 0xc4
5194 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_LSB 0
5196 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_MSB 15
5198 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_WIDTH 16
5200 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5202 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5204 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_RESET 0xffff
5206 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5208 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5219 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_LSB 16
5221 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_MSB 31
5223 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_WIDTH 16
5225 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5227 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5229 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_RESET 0x0
5231 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5233 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5235 #ifndef __ASSEMBLY__
5247 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_s
5249 const volatile uint32_t low : 16;
5250 volatile uint32_t high : 16;
5254 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_t;
5258 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_RESET 0x0000ffff
5260 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_OFST 0xc8
5284 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_LSB 0
5286 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_MSB 4
5288 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_WIDTH 5
5290 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5292 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5294 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_RESET 0x0
5296 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5298 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5300 #ifndef __ASSEMBLY__
5312 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_s
5314 volatile uint32_t low : 5;
5319 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_t;
5323 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_RESET 0x00000000
5325 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_OFST 0xcc
5349 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_LSB 0
5351 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_MSB 15
5353 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_WIDTH 16
5355 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_SET_MSK 0x0000ffff
5357 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_CLR_MSK 0xffff0000
5359 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_RESET 0x0
5361 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5363 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5374 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_LSB 16
5376 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_MSB 31
5378 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_WIDTH 16
5380 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_SET_MSK 0xffff0000
5382 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5384 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_RESET 0x0
5386 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5388 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5390 #ifndef __ASSEMBLY__
5402 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_s
5404 const volatile uint32_t low : 16;
5405 volatile uint32_t high : 16;
5409 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_t;
5413 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_RESET 0x00000000
5415 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_OFST 0xd0
5439 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_LSB 0
5441 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_MSB 4
5443 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_WIDTH 5
5445 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5447 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5449 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_RESET 0x0
5451 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5453 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5455 #ifndef __ASSEMBLY__
5467 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_s
5469 volatile uint32_t low : 5;
5474 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_t;
5478 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_RESET 0x00000000
5480 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_OFST 0xd4
5504 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_LSB 0
5506 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_MSB 15
5508 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_WIDTH 16
5510 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5512 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5514 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_RESET 0xffff
5516 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5518 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5529 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_LSB 16
5531 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_MSB 31
5533 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_WIDTH 16
5535 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5537 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5539 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_RESET 0x0
5541 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5543 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5545 #ifndef __ASSEMBLY__
5557 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_s
5559 const volatile uint32_t low : 16;
5560 volatile uint32_t high : 16;
5564 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_t;
5568 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_RESET 0x0000ffff
5570 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_OFST 0xd8
5594 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_LSB 0
5596 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_MSB 4
5598 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_WIDTH 5
5600 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5602 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5604 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_RESET 0x0
5606 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5608 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5610 #ifndef __ASSEMBLY__
5622 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_s
5624 volatile uint32_t low : 5;
5629 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_t;
5633 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_RESET 0x00000000
5635 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_OFST 0xdc
5659 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_LSB 0
5661 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_MSB 15
5663 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_WIDTH 16
5665 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_SET_MSK 0x0000ffff
5667 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_CLR_MSK 0xffff0000
5669 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_RESET 0x0
5671 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5673 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5684 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_LSB 16
5686 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_MSB 31
5688 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_WIDTH 16
5690 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_SET_MSK 0xffff0000
5692 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
5694 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_RESET 0x0
5696 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5698 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5700 #ifndef __ASSEMBLY__
5712 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_s
5714 const volatile uint32_t low : 16;
5715 volatile uint32_t high : 16;
5719 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_t;
5723 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_RESET 0x00000000
5725 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_OFST 0xe0
5749 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_LSB 0
5751 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_MSB 4
5753 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_WIDTH 5
5755 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
5757 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
5759 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_RESET 0x0
5761 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5763 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5765 #ifndef __ASSEMBLY__
5777 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_s
5779 volatile uint32_t low : 5;
5784 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_t;
5788 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_RESET 0x00000000
5790 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_OFST 0xe4
5814 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_LSB 0
5816 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_MSB 15
5818 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_WIDTH 16
5820 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
5822 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
5824 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_RESET 0xffff
5826 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5828 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5839 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_LSB 16
5841 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_MSB 31
5843 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_WIDTH 16
5845 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
5847 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
5849 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_RESET 0x0
5851 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
5853 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
5855 #ifndef __ASSEMBLY__
5867 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_s
5869 const volatile uint32_t low : 16;
5870 volatile uint32_t high : 16;
5874 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_t;
5878 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_RESET 0x0000ffff
5880 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_OFST 0xe8
5904 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_LSB 0
5906 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_MSB 4
5908 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_WIDTH 5
5910 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
5912 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
5914 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_RESET 0x0
5916 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
5918 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
5920 #ifndef __ASSEMBLY__
5932 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_s
5934 volatile uint32_t low : 5;
5939 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_t;
5943 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_RESET 0x00000000
5945 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_OFST 0xec
5969 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_LSB 0
5971 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_MSB 15
5973 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_WIDTH 16
5975 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_SET_MSK 0x0000ffff
5977 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_CLR_MSK 0xffff0000
5979 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_RESET 0x0
5981 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
5983 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
5994 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_LSB 16
5996 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_MSB 31
5998 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_WIDTH 16
6000 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_SET_MSK 0xffff0000
6002 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
6004 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_RESET 0x0
6006 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6008 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6010 #ifndef __ASSEMBLY__
6022 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_s
6024 const volatile uint32_t low : 16;
6025 volatile uint32_t high : 16;
6029 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_t;
6033 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_RESET 0x00000000
6035 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_OFST 0xf0
6059 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_LSB 0
6061 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_MSB 4
6063 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_WIDTH 5
6065 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
6067 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
6069 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_RESET 0x0
6071 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6073 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6075 #ifndef __ASSEMBLY__
6087 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_s
6089 volatile uint32_t low : 5;
6094 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_t;
6098 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_RESET 0x00000000
6100 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_OFST 0xf4
6124 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_LSB 0
6126 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_MSB 15
6128 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_WIDTH 16
6130 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
6132 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
6134 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_RESET 0xffff
6136 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6138 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6149 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_LSB 16
6151 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_MSB 31
6153 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_WIDTH 16
6155 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
6157 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
6159 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_RESET 0x0
6161 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6163 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6165 #ifndef __ASSEMBLY__
6177 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_s
6179 const volatile uint32_t low : 16;
6180 volatile uint32_t high : 16;
6184 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_t;
6188 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_RESET 0x0000ffff
6190 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_OFST 0xf8
6214 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_LSB 0
6216 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_MSB 4
6218 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_WIDTH 5
6220 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
6222 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
6224 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_RESET 0x0
6226 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6228 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6230 #ifndef __ASSEMBLY__
6242 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_s
6244 volatile uint32_t low : 5;
6249 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_t;
6253 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_RESET 0x00000000
6255 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_OFST 0xfc
6279 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_LSB 0
6281 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_MSB 15
6283 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_WIDTH 16
6285 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_SET_MSK 0x0000ffff
6287 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_CLR_MSK 0xffff0000
6289 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_RESET 0x0
6291 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6293 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6304 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_LSB 16
6306 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_MSB 31
6308 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_WIDTH 16
6310 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_SET_MSK 0xffff0000
6312 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_CLR_MSK 0x0000ffff
6314 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_RESET 0x0
6316 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6318 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6320 #ifndef __ASSEMBLY__
6332 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_s
6334 const volatile uint32_t low : 16;
6335 volatile uint32_t high : 16;
6339 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_t;
6343 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_RESET 0x00000000
6345 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_OFST 0x100
6369 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_LSB 0
6371 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_MSB 4
6373 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_WIDTH 5
6375 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_SET_MSK 0x0000001f
6377 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_CLR_MSK 0xffffffe0
6379 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_RESET 0x0
6381 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6383 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6385 #ifndef __ASSEMBLY__
6397 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_s
6399 volatile uint32_t low : 5;
6404 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_t;
6408 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_RESET 0x00000000
6410 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_OFST 0x104
6434 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_LSB 0
6436 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_MSB 15
6438 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_WIDTH 16
6440 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_SET_MSK 0x0000ffff
6442 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_CLR_MSK 0xffff0000
6444 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_RESET 0xffff
6446 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_GET(value) (((value) & 0x0000ffff) >> 0)
6448 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_LOW_SET(value) (((value) << 0) & 0x0000ffff)
6459 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_LSB 16
6461 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_MSB 31
6463 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_WIDTH 16
6465 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_SET_MSK 0xffff0000
6467 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_CLR_MSK 0x0000ffff
6469 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_RESET 0x0
6471 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_GET(value) (((value) & 0xffff0000) >> 16)
6473 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_HIGH_SET(value) (((value) << 16) & 0xffff0000)
6475 #ifndef __ASSEMBLY__
6487 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_s
6489 const volatile uint32_t low : 16;
6490 volatile uint32_t high : 16;
6494 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_t;
6498 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_RESET 0x0000ffff
6500 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_OFST 0x108
6524 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_LSB 0
6526 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_MSB 4
6528 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_WIDTH 5
6530 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_SET_MSK 0x0000001f
6532 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_CLR_MSK 0xffffffe0
6534 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_RESET 0x0
6536 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_GET(value) (((value) & 0x0000001f) >> 0)
6538 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_LOW_SET(value) (((value) << 0) & 0x0000001f)
6540 #ifndef __ASSEMBLY__
6552 struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_s
6554 volatile uint32_t low : 5;
6559 typedef struct ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_s ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_t;
6563 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_RESET 0x00000000
6565 #define ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_OFST 0x10c
6567 #ifndef __ASSEMBLY__
6579 struct ALT_SOC_NOC_FW_DDR_SCR_s
6581 volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_t enable;
6582 volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_SET_t enable_set;
6583 volatile ALT_SOC_NOC_FW_DDR_SCR_ENABLE_CLEAR_t enable_clear;
6584 volatile uint32_t _pad_0xc_0xf;
6585 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASE_t mpuregion0addr_base;
6586 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_BASEEXT_t mpuregion0addr_baseext;
6587 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT_t mpuregion0addr_limit;
6588 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT_t mpuregion0addr_limitext;
6589 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASE_t mpuregion1addr_base;
6590 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_BASEEXT_t mpuregion1addr_baseext;
6591 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMIT_t mpuregion1addr_limit;
6592 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION1ADDR_LIMITEXT_t mpuregion1addr_limitext;
6593 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASE_t mpuregion2addr_base;
6594 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_BASEEXT_t mpuregion2addr_baseext;
6595 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMIT_t mpuregion2addr_limit;
6596 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION2ADDR_LIMITEXT_t mpuregion2addr_limitext;
6597 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASE_t mpuregion3addr_base;
6598 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_BASEEXT_t mpuregion3addr_baseext;
6599 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMIT_t mpuregion3addr_limit;
6600 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION3ADDR_LIMITEXT_t mpuregion3addr_limitext;
6601 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASE_t mpuregion4addr_base;
6602 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_BASEEXT_t mpuregion4addr_baseext;
6603 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMIT_t mpuregion4addr_limit;
6604 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION4ADDR_LIMITEXT_t mpuregion4addr_limitext;
6605 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASE_t mpuregion5addr_base;
6606 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_BASEEXT_t mpuregion5addr_baseext;
6607 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMIT_t mpuregion5addr_limit;
6608 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION5ADDR_LIMITEXT_t mpuregion5addr_limitext;
6609 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASE_t mpuregion6addr_base;
6610 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_BASEEXT_t mpuregion6addr_baseext;
6611 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMIT_t mpuregion6addr_limit;
6612 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION6ADDR_LIMITEXT_t mpuregion6addr_limitext;
6613 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASE_t mpuregion7addr_base;
6614 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_BASEEXT_t mpuregion7addr_baseext;
6615 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMIT_t mpuregion7addr_limit;
6616 volatile ALT_SOC_NOC_FW_DDR_SCR_MPUREGION7ADDR_LIMITEXT_t mpuregion7addr_limitext;
6617 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASE_t nonmpuregion0addr_base;
6618 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_BASEEXT_t nonmpuregion0addr_baseext;
6619 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT_t nonmpuregion0addr_limit;
6620 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_t nonmpuregion0addr_limitext;
6621 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASE_t nonmpuregion1addr_base;
6622 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_BASEEXT_t nonmpuregion1addr_baseext;
6623 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMIT_t nonmpuregion1addr_limit;
6624 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION1ADDR_LIMITEXT_t nonmpuregion1addr_limitext;
6625 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASE_t nonmpuregion2addr_base;
6626 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_BASEEXT_t nonmpuregion2addr_baseext;
6627 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMIT_t nonmpuregion2addr_limit;
6628 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION2ADDR_LIMITEXT_t nonmpuregion2addr_limitext;
6629 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASE_t nonmpuregion3addr_base;
6630 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_BASEEXT_t nonmpuregion3addr_baseext;
6631 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMIT_t nonmpuregion3addr_limit;
6632 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION3ADDR_LIMITEXT_t nonmpuregion3addr_limitext;
6633 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASE_t nonmpuregion4addr_base;
6634 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_BASEEXT_t nonmpuregion4addr_baseext;
6635 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMIT_t nonmpuregion4addr_limit;
6636 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION4ADDR_LIMITEXT_t nonmpuregion4addr_limitext;
6637 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASE_t nonmpuregion5addr_base;
6638 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_BASEEXT_t nonmpuregion5addr_baseext;
6639 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMIT_t nonmpuregion5addr_limit;
6640 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION5ADDR_LIMITEXT_t nonmpuregion5addr_limitext;
6641 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASE_t nonmpuregion6addr_base;
6642 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_BASEEXT_t nonmpuregion6addr_baseext;
6643 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMIT_t nonmpuregion6addr_limit;
6644 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION6ADDR_LIMITEXT_t nonmpuregion6addr_limitext;
6645 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASE_t nonmpuregion7addr_base;
6646 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_BASEEXT_t nonmpuregion7addr_baseext;
6647 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMIT_t nonmpuregion7addr_limit;
6648 volatile ALT_SOC_NOC_FW_DDR_SCR_NONMPUREGION7ADDR_LIMITEXT_t nonmpuregion7addr_limitext;
6649 volatile uint32_t _pad_0x110_0x100;
6653 typedef struct ALT_SOC_NOC_FW_DDR_SCR_s ALT_SOC_NOC_FW_DDR_SCR_t;
6655 struct ALT_SOC_NOC_FW_DDR_SCR_raw_s
6657 volatile uint32_t enable;
6658 volatile uint32_t enable_set;
6659 volatile uint32_t enable_clear;
6660 volatile uint32_t _pad_0xc_0xf;
6661 volatile uint32_t mpuregion0addr_base;
6662 volatile uint32_t mpuregion0addr_baseext;
6663 volatile uint32_t mpuregion0addr_limit;
6664 volatile uint32_t mpuregion0addr_limitext;
6665 volatile uint32_t mpuregion1addr_base;
6666 volatile uint32_t mpuregion1addr_baseext;
6667 volatile uint32_t mpuregion1addr_limit;
6668 volatile uint32_t mpuregion1addr_limitext;
6669 volatile uint32_t mpuregion2addr_base;
6670 volatile uint32_t mpuregion2addr_baseext;
6671 volatile uint32_t mpuregion2addr_limit;
6672 volatile uint32_t mpuregion2addr_limitext;
6673 volatile uint32_t mpuregion3addr_base;
6674 volatile uint32_t mpuregion3addr_baseext;
6675 volatile uint32_t mpuregion3addr_limit;
6676 volatile uint32_t mpuregion3addr_limitext;
6677 volatile uint32_t mpuregion4addr_base;
6678 volatile uint32_t mpuregion4addr_baseext;
6679 volatile uint32_t mpuregion4addr_limit;
6680 volatile uint32_t mpuregion4addr_limitext;
6681 volatile uint32_t mpuregion5addr_base;
6682 volatile uint32_t mpuregion5addr_baseext;
6683 volatile uint32_t mpuregion5addr_limit;
6684 volatile uint32_t mpuregion5addr_limitext;
6685 volatile uint32_t mpuregion6addr_base;
6686 volatile uint32_t mpuregion6addr_baseext;
6687 volatile uint32_t mpuregion6addr_limit;
6688 volatile uint32_t mpuregion6addr_limitext;
6689 volatile uint32_t mpuregion7addr_base;
6690 volatile uint32_t mpuregion7addr_baseext;
6691 volatile uint32_t mpuregion7addr_limit;
6692 volatile uint32_t mpuregion7addr_limitext;
6693 volatile uint32_t nonmpuregion0addr_base;
6694 volatile uint32_t nonmpuregion0addr_baseext;
6695 volatile uint32_t nonmpuregion0addr_limit;
6696 volatile uint32_t nonmpuregion0addr_limitext;
6697 volatile uint32_t nonmpuregion1addr_base;
6698 volatile uint32_t nonmpuregion1addr_baseext;
6699 volatile uint32_t nonmpuregion1addr_limit;
6700 volatile uint32_t nonmpuregion1addr_limitext;
6701 volatile uint32_t nonmpuregion2addr_base;
6702 volatile uint32_t nonmpuregion2addr_baseext;
6703 volatile uint32_t nonmpuregion2addr_limit;
6704 volatile uint32_t nonmpuregion2addr_limitext;
6705 volatile uint32_t nonmpuregion3addr_base;
6706 volatile uint32_t nonmpuregion3addr_baseext;
6707 volatile uint32_t nonmpuregion3addr_limit;
6708 volatile uint32_t nonmpuregion3addr_limitext;
6709 volatile uint32_t nonmpuregion4addr_base;
6710 volatile uint32_t nonmpuregion4addr_baseext;
6711 volatile uint32_t nonmpuregion4addr_limit;
6712 volatile uint32_t nonmpuregion4addr_limitext;
6713 volatile uint32_t nonmpuregion5addr_base;
6714 volatile uint32_t nonmpuregion5addr_baseext;
6715 volatile uint32_t nonmpuregion5addr_limit;
6716 volatile uint32_t nonmpuregion5addr_limitext;
6717 volatile uint32_t nonmpuregion6addr_base;
6718 volatile uint32_t nonmpuregion6addr_baseext;
6719 volatile uint32_t nonmpuregion6addr_limit;
6720 volatile uint32_t nonmpuregion6addr_limitext;
6721 volatile uint32_t nonmpuregion7addr_base;
6722 volatile uint32_t nonmpuregion7addr_baseext;
6723 volatile uint32_t nonmpuregion7addr_limit;
6724 volatile uint32_t nonmpuregion7addr_limitext;
6725 volatile uint32_t _pad_0x110_0x100;
6729 typedef struct ALT_SOC_NOC_FW_DDR_SCR_raw_s ALT_SOC_NOC_FW_DDR_SCR_raw_t;