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alt_noc_fw_mmap_priv.h
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32 
33 /* Altera - ALT_NOC_FW_MMAP_PRIV */
34 
35 #ifndef __ALT_SOCAL_NOC_FW_MMAP_PRIV_H__
36 #define __ALT_SOCAL_NOC_FW_MMAP_PRIV_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : NOC_FW_MMAP_PRIV
50  * L4_Privilege Filter
51  *
52  */
53 /*
54  * Register : priv
55  *
56  * This register controls access to various Peripherals depending on the privilege
57  * setting. By default, all slaves will be assumed as Privileged. To allow non-
58  * Privileged access to a slave, the corresponding bit for the slave must be set.
59  * Once set, both Privilege and non-Privileged transactions are allowed to the
60  * Slave. Note that the privilege filter only checks for transaction Privilege
61  * level, transaction Security is left to Firewalls. Firewalls therefore may still
62  * block transaction to Peripherals depending on Security configurations.
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :--------|:-------|:------|:----------------------------------------
68  * [0] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER
69  * [1] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA
70  * [2] | ??? | 0x0 | *UNDEFINED*
71  * [3] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER
72  * [4] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER
73  * [5] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE
74  * [6] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE
75  * [7] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0
76  * [8] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1
77  * [9] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0
78  * [10] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1
79  * [11] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0
80  * [12] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1
81  * [13] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2
82  * [15:14] | ??? | 0x0 | *UNDEFINED*
83  * [16] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC
84  * [17] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0
85  * [18] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1
86  * [19] | ??? | 0x0 | *UNDEFINED*
87  * [20] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0
88  * [21] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1
89  * [22] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2
90  * [23] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3
91  * [24] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4
92  * [25] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0
93  * [26] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1
94  * [27] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_UART0
95  * [28] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_UART1
96  * [29] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA
97  * [30] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA
98  * [31] | RW | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_TCU
99  *
100  */
101 /*
102  * Field : nand_register
103  *
104  * Privilege bit for nand register. When 0, only privileged transactions are
105  * allowed to slave. When 1, both privileged and non-privileged transactions are
106  * allowed to slave
107  *
108  * Field Access Macros:
109  *
110  */
111 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field. */
112 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_LSB 0
113 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field. */
114 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_MSB 0
115 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field. */
116 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_WIDTH 1
117 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field value. */
118 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_SET_MSK 0x00000001
119 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field value. */
120 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_CLR_MSK 0xfffffffe
121 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field. */
122 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_RESET 0x0
123 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER field value from a register. */
124 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
125 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER register field value suitable for setting the register. */
126 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
127 
128 /*
129  * Field : nand_data
130  *
131  * Privilege bit for nand_data. When 0, only privileged transactions are allowed to
132  * slave. When 1, both privileged and non-privileged transactions are allowed to
133  * slave
134  *
135  * Field Access Macros:
136  *
137  */
138 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field. */
139 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_LSB 1
140 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field. */
141 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_MSB 1
142 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field. */
143 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_WIDTH 1
144 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field value. */
145 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_SET_MSK 0x00000002
146 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field value. */
147 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_CLR_MSK 0xfffffffd
148 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field. */
149 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_RESET 0x0
150 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA field value from a register. */
151 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
152 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA register field value suitable for setting the register. */
153 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
154 
155 /*
156  * Field : usb0_register
157  *
158  * Privilege bit for usb0_register. When 0, only privileged transactions are
159  * allowed to slave. When 1, both privileged and non-privileged transactions are
160  * allowed to slave
161  *
162  * Field Access Macros:
163  *
164  */
165 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field. */
166 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_LSB 3
167 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field. */
168 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_MSB 3
169 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field. */
170 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_WIDTH 1
171 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field value. */
172 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_SET_MSK 0x00000008
173 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field value. */
174 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_CLR_MSK 0xfffffff7
175 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field. */
176 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_RESET 0x0
177 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER field value from a register. */
178 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
179 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER register field value suitable for setting the register. */
180 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
181 
182 /*
183  * Field : usb1_register
184  *
185  * Privilege bit for usb1_register. When 0, only privileged transactions are
186  * allowed to slave. When 1, both privileged and non-privileged transactions are
187  * allowed to slave
188  *
189  * Field Access Macros:
190  *
191  */
192 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field. */
193 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_LSB 4
194 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field. */
195 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_MSB 4
196 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field. */
197 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_WIDTH 1
198 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field value. */
199 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_SET_MSK 0x00000010
200 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field value. */
201 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_CLR_MSK 0xffffffef
202 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field. */
203 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_RESET 0x0
204 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER field value from a register. */
205 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
206 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER register field value suitable for setting the register. */
207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
208 
209 /*
210  * Field : dma_nonsecure
211  *
212  * Privilege bit for dma_nonsecure. When 0, only privileged transactions are
213  * allowed to slave. When 1, both privileged and non-privileged transactions are
214  * allowed to slave
215  *
216  * Field Access Macros:
217  *
218  */
219 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field. */
220 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_LSB 5
221 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field. */
222 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_MSB 5
223 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field. */
224 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_WIDTH 1
225 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field value. */
226 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_SET_MSK 0x00000020
227 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field value. */
228 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_CLR_MSK 0xffffffdf
229 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field. */
230 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_RESET 0x0
231 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE field value from a register. */
232 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
233 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE register field value suitable for setting the register. */
234 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
235 
236 /*
237  * Field : dma_secure
238  *
239  * Privilege bit for dma_secure. When 0, only privileged transactions are allowed
240  * to slave. When 1, both privileged and non-privileged transactions are allowed to
241  * slave
242  *
243  * Field Access Macros:
244  *
245  */
246 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field. */
247 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_LSB 6
248 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field. */
249 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_MSB 6
250 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field. */
251 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_WIDTH 1
252 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field value. */
253 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_SET_MSK 0x00000040
254 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field value. */
255 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_CLR_MSK 0xffffffbf
256 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field. */
257 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_RESET 0x0
258 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE field value from a register. */
259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
260 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE register field value suitable for setting the register. */
261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
262 
263 /*
264  * Field : spi_master0
265  *
266  * Privilege bit for spi_master0. When 0, only privileged transactions are allowed
267  * to slave. When 1, both privileged and non-privileged transactions are allowed to
268  * slave
269  *
270  * Field Access Macros:
271  *
272  */
273 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field. */
274 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_LSB 7
275 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field. */
276 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_MSB 7
277 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field. */
278 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_WIDTH 1
279 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field value. */
280 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_SET_MSK 0x00000080
281 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field value. */
282 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_CLR_MSK 0xffffff7f
283 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field. */
284 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_RESET 0x0
285 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 field value from a register. */
286 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
287 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 register field value suitable for setting the register. */
288 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
289 
290 /*
291  * Field : spi_master1
292  *
293  * Privilege bit for spi_master1. When 0, only privileged transactions are allowed
294  * to slave. When 1, both privileged and non-privileged transactions are allowed to
295  * slave
296  *
297  * Field Access Macros:
298  *
299  */
300 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field. */
301 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_LSB 8
302 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field. */
303 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_MSB 8
304 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field. */
305 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_WIDTH 1
306 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field value. */
307 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_SET_MSK 0x00000100
308 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field value. */
309 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_CLR_MSK 0xfffffeff
310 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field. */
311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_RESET 0x0
312 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 field value from a register. */
313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
314 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 register field value suitable for setting the register. */
315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
316 
317 /*
318  * Field : spi_slave0
319  *
320  * Privilege bit for spi_slave0. When 0, only privileged transactions are allowed
321  * to slave. When 1, both privileged and non-privileged transactions are allowed to
322  * slave
323  *
324  * Field Access Macros:
325  *
326  */
327 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field. */
328 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_LSB 9
329 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field. */
330 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_MSB 9
331 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field. */
332 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_WIDTH 1
333 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field value. */
334 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_SET_MSK 0x00000200
335 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field value. */
336 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_CLR_MSK 0xfffffdff
337 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field. */
338 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_RESET 0x0
339 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 field value from a register. */
340 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
341 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 register field value suitable for setting the register. */
342 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
343 
344 /*
345  * Field : spi_slave1
346  *
347  * Privilege bit for spi_slave1. When 0, only privileged transactions are allowed
348  * to slave. When 1, both privileged and non-privileged transactions are allowed to
349  * slave
350  *
351  * Field Access Macros:
352  *
353  */
354 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field. */
355 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_LSB 10
356 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field. */
357 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_MSB 10
358 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field. */
359 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_WIDTH 1
360 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field value. */
361 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_SET_MSK 0x00000400
362 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field value. */
363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_CLR_MSK 0xfffffbff
364 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field. */
365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_RESET 0x0
366 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 field value from a register. */
367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
368 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 register field value suitable for setting the register. */
369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
370 
371 /*
372  * Field : emac0
373  *
374  * Privilege bit for emac0. When 0, only privileged transactions are allowed to
375  * slave. When 1, both privileged and non-privileged transactions are allowed to
376  * slave
377  *
378  * Field Access Macros:
379  *
380  */
381 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field. */
382 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_LSB 11
383 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field. */
384 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_MSB 11
385 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field. */
386 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_WIDTH 1
387 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field value. */
388 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_SET_MSK 0x00000800
389 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field value. */
390 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_CLR_MSK 0xfffff7ff
391 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field. */
392 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_RESET 0x0
393 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 field value from a register. */
394 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
395 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 register field value suitable for setting the register. */
396 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_SET(value) (((value) << 11) & 0x00000800)
397 
398 /*
399  * Field : emac1
400  *
401  * Privilege bit for emac1. When 0, only privileged transactions are allowed to
402  * slave. When 1, both privileged and non-privileged transactions are allowed to
403  * slave
404  *
405  * Field Access Macros:
406  *
407  */
408 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field. */
409 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_LSB 12
410 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field. */
411 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_MSB 12
412 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field. */
413 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_WIDTH 1
414 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field value. */
415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_SET_MSK 0x00001000
416 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field value. */
417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_CLR_MSK 0xffffefff
418 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field. */
419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_RESET 0x0
420 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 field value from a register. */
421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
422 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 register field value suitable for setting the register. */
423 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_SET(value) (((value) << 12) & 0x00001000)
424 
425 /*
426  * Field : emac2
427  *
428  * Privilege bit for emac2. When 0, only privileged transactions are allowed to
429  * slave. When 1, both privileged and non-privileged transactions are allowed to
430  * slave
431  *
432  * Field Access Macros:
433  *
434  */
435 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field. */
436 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_LSB 13
437 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field. */
438 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_MSB 13
439 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field. */
440 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_WIDTH 1
441 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field value. */
442 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_SET_MSK 0x00002000
443 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field value. */
444 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_CLR_MSK 0xffffdfff
445 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field. */
446 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_RESET 0x0
447 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 field value from a register. */
448 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
449 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 register field value suitable for setting the register. */
450 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_SET(value) (((value) << 13) & 0x00002000)
451 
452 /*
453  * Field : sdmmc
454  *
455  * Privilege bit for sdmmc. When 0, only privileged transactions are allowed to
456  * slave. When 1, both privileged and non-privileged transactions are allowed to
457  * slave
458  *
459  * Field Access Macros:
460  *
461  */
462 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field. */
463 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_LSB 16
464 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field. */
465 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_MSB 16
466 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field. */
467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_WIDTH 1
468 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field value. */
469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_SET_MSK 0x00010000
470 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field value. */
471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_CLR_MSK 0xfffeffff
472 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field. */
473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_RESET 0x0
474 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC field value from a register. */
475 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
476 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC register field value suitable for setting the register. */
477 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_SET(value) (((value) << 16) & 0x00010000)
478 
479 /*
480  * Field : gpio0
481  *
482  * Privilege bit for gpio0. When 0, only privileged transactions are allowed to
483  * slave. When 1, both privileged and non-privileged transactions are allowed to
484  * slave
485  *
486  * Field Access Macros:
487  *
488  */
489 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field. */
490 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_LSB 17
491 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field. */
492 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_MSB 17
493 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field. */
494 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_WIDTH 1
495 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field value. */
496 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_SET_MSK 0x00020000
497 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field value. */
498 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_CLR_MSK 0xfffdffff
499 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field. */
500 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_RESET 0x0
501 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 field value from a register. */
502 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
503 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 register field value suitable for setting the register. */
504 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_SET(value) (((value) << 17) & 0x00020000)
505 
506 /*
507  * Field : gpio1
508  *
509  * Privilege bit for gpio1. When 0, only privileged transactions are allowed to
510  * slave. When 1, both privileged and non-privileged transactions are allowed to
511  * slave
512  *
513  * Field Access Macros:
514  *
515  */
516 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field. */
517 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_LSB 18
518 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field. */
519 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_MSB 18
520 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field. */
521 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_WIDTH 1
522 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field value. */
523 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_SET_MSK 0x00040000
524 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field value. */
525 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_CLR_MSK 0xfffbffff
526 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field. */
527 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_RESET 0x0
528 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 field value from a register. */
529 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
530 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 register field value suitable for setting the register. */
531 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_SET(value) (((value) << 18) & 0x00040000)
532 
533 /*
534  * Field : i2c0
535  *
536  * Privilege bit for i2c0. When 0, only privileged transactions are allowed to
537  * slave. When 1, both privileged and non-privileged transactions are allowed to
538  * slave
539  *
540  * Field Access Macros:
541  *
542  */
543 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field. */
544 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_LSB 20
545 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field. */
546 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_MSB 20
547 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field. */
548 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_WIDTH 1
549 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field value. */
550 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_SET_MSK 0x00100000
551 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field value. */
552 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_CLR_MSK 0xffefffff
553 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field. */
554 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_RESET 0x0
555 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 field value from a register. */
556 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_GET(value) (((value) & 0x00100000) >> 20)
557 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 register field value suitable for setting the register. */
558 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_SET(value) (((value) << 20) & 0x00100000)
559 
560 /*
561  * Field : i2c1
562  *
563  * Privilege bit for i2c1. When 0, only privileged transactions are allowed to
564  * slave. When 1, both privileged and non-privileged transactions are allowed to
565  * slave
566  *
567  * Field Access Macros:
568  *
569  */
570 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field. */
571 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_LSB 21
572 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field. */
573 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_MSB 21
574 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field. */
575 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_WIDTH 1
576 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field value. */
577 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_SET_MSK 0x00200000
578 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field value. */
579 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_CLR_MSK 0xffdfffff
580 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field. */
581 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_RESET 0x0
582 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 field value from a register. */
583 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_GET(value) (((value) & 0x00200000) >> 21)
584 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 register field value suitable for setting the register. */
585 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_SET(value) (((value) << 21) & 0x00200000)
586 
587 /*
588  * Field : i2c2
589  *
590  * Privilege bit for i2c2. When 0, only privileged transactions are allowed to
591  * slave. When 1, both privileged and non-privileged transactions are allowed to
592  * slave
593  *
594  * Field Access Macros:
595  *
596  */
597 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field. */
598 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_LSB 22
599 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field. */
600 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_MSB 22
601 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field. */
602 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_WIDTH 1
603 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field value. */
604 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_SET_MSK 0x00400000
605 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field value. */
606 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_CLR_MSK 0xffbfffff
607 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field. */
608 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_RESET 0x0
609 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 field value from a register. */
610 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_GET(value) (((value) & 0x00400000) >> 22)
611 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 register field value suitable for setting the register. */
612 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_SET(value) (((value) << 22) & 0x00400000)
613 
614 /*
615  * Field : i2c3
616  *
617  * Privilege bit for i2c3. When 0, only privileged transactions are allowed to
618  * slave. When 1, both privileged and non-privileged transactions are allowed to
619  * slave
620  *
621  * Field Access Macros:
622  *
623  */
624 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field. */
625 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_LSB 23
626 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field. */
627 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_MSB 23
628 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field. */
629 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_WIDTH 1
630 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field value. */
631 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_SET_MSK 0x00800000
632 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field value. */
633 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_CLR_MSK 0xff7fffff
634 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field. */
635 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_RESET 0x0
636 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 field value from a register. */
637 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_GET(value) (((value) & 0x00800000) >> 23)
638 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 register field value suitable for setting the register. */
639 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_SET(value) (((value) << 23) & 0x00800000)
640 
641 /*
642  * Field : i2c4
643  *
644  * Privilege bit for i2c4. When 0, only privileged transactions are allowed to
645  * slave. When 1, both privileged and non-privileged transactions are allowed to
646  * slave
647  *
648  * Field Access Macros:
649  *
650  */
651 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field. */
652 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_LSB 24
653 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field. */
654 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_MSB 24
655 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field. */
656 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_WIDTH 1
657 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field value. */
658 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_SET_MSK 0x01000000
659 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field value. */
660 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_CLR_MSK 0xfeffffff
661 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field. */
662 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_RESET 0x0
663 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 field value from a register. */
664 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_GET(value) (((value) & 0x01000000) >> 24)
665 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 register field value suitable for setting the register. */
666 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_SET(value) (((value) << 24) & 0x01000000)
667 
668 /*
669  * Field : sp_timer0
670  *
671  * Privilege bit for sp_timer0. When 0, only privileged transactions are allowed to
672  * slave. When 1, both privileged and non-privileged transactions are allowed to
673  * slave
674  *
675  * Field Access Macros:
676  *
677  */
678 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field. */
679 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_LSB 25
680 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field. */
681 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_MSB 25
682 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field. */
683 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_WIDTH 1
684 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field value. */
685 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_SET_MSK 0x02000000
686 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field value. */
687 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_CLR_MSK 0xfdffffff
688 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field. */
689 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_RESET 0x0
690 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 field value from a register. */
691 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
692 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 register field value suitable for setting the register. */
693 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
694 
695 /*
696  * Field : sp_timer1
697  *
698  * Privilege bit for sp_timer1. When 0, only privileged transactions are allowed to
699  * slave. When 1, both privileged and non-privileged transactions are allowed to
700  * slave
701  *
702  * Field Access Macros:
703  *
704  */
705 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field. */
706 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_LSB 26
707 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field. */
708 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_MSB 26
709 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field. */
710 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_WIDTH 1
711 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field value. */
712 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_SET_MSK 0x04000000
713 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field value. */
714 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_CLR_MSK 0xfbffffff
715 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field. */
716 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_RESET 0x0
717 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 field value from a register. */
718 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
719 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 register field value suitable for setting the register. */
720 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
721 
722 /*
723  * Field : uart0
724  *
725  * Privilege bit for uart0. When 0, only privileged transactions are allowed to
726  * slave. When 1, both privileged and non-privileged transactions are allowed to
727  * slave
728  *
729  * Field Access Macros:
730  *
731  */
732 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field. */
733 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_LSB 27
734 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field. */
735 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_MSB 27
736 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field. */
737 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_WIDTH 1
738 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field value. */
739 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_SET_MSK 0x08000000
740 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field value. */
741 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_CLR_MSK 0xf7ffffff
742 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field. */
743 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_RESET 0x0
744 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 field value from a register. */
745 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_GET(value) (((value) & 0x08000000) >> 27)
746 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 register field value suitable for setting the register. */
747 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_SET(value) (((value) << 27) & 0x08000000)
748 
749 /*
750  * Field : uart1
751  *
752  * Privilege bit for uart1. When 0, only privileged transactions are allowed to
753  * slave. When 1, both privileged and non-privileged transactions are allowed to
754  * slave
755  *
756  * Field Access Macros:
757  *
758  */
759 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field. */
760 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_LSB 28
761 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field. */
762 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_MSB 28
763 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field. */
764 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_WIDTH 1
765 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field value. */
766 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_SET_MSK 0x10000000
767 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field value. */
768 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_CLR_MSK 0xefffffff
769 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field. */
770 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_RESET 0x0
771 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 field value from a register. */
772 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_GET(value) (((value) & 0x10000000) >> 28)
773 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 register field value suitable for setting the register. */
774 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_SET(value) (((value) << 28) & 0x10000000)
775 
776 /*
777  * Field : lwsoc2fpga
778  *
779  * Privilege bit for Lightweight SOC2FPGA. When 0, only privileged transactions are
780  * allowed to slave. When 1, both privileged and non-privileged transactions are
781  * allowed to slave
782  *
783  * Field Access Macros:
784  *
785  */
786 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field. */
787 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_LSB 29
788 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field. */
789 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_MSB 29
790 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field. */
791 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_WIDTH 1
792 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field value. */
793 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_SET_MSK 0x20000000
794 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field value. */
795 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_CLR_MSK 0xdfffffff
796 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field. */
797 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_RESET 0x0
798 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA field value from a register. */
799 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
800 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA register field value suitable for setting the register. */
801 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
802 
803 /*
804  * Field : soc2fpga
805  *
806  * Privilege bit for SOC2FPGA. When 0, only privileged transactions are allowed to
807  * slave. When 1, both privileged and non-privileged transactions are allowed to
808  * slave
809  *
810  * Field Access Macros:
811  *
812  */
813 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field. */
814 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_LSB 30
815 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field. */
816 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_MSB 30
817 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field. */
818 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_WIDTH 1
819 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field value. */
820 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_SET_MSK 0x40000000
821 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field value. */
822 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_CLR_MSK 0xbfffffff
823 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field. */
824 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_RESET 0x0
825 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA field value from a register. */
826 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
827 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA register field value suitable for setting the register. */
828 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
829 
830 /*
831  * Field : tcu
832  *
833  * Privilege bit for TCU slave. When 0, only privileged transactions are allowed to
834  * slave. When 1, both privileged and non-privileged transactions are allowed to
835  * slave
836  *
837  * Field Access Macros:
838  *
839  */
840 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field. */
841 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_LSB 31
842 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field. */
843 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_MSB 31
844 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field. */
845 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_WIDTH 1
846 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field value. */
847 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_SET_MSK 0x80000000
848 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field value. */
849 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_CLR_MSK 0x7fffffff
850 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field. */
851 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_RESET 0x0
852 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_TCU field value from a register. */
853 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_GET(value) (((value) & 0x80000000) >> 31)
854 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_TCU register field value suitable for setting the register. */
855 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_SET(value) (((value) << 31) & 0x80000000)
856 
857 #ifndef __ASSEMBLY__
858 /*
859  * WARNING: The C register and register group struct declarations are provided for
860  * convenience and illustrative purposes. They should, however, be used with
861  * caution as the C language standard provides no guarantees about the alignment or
862  * atomicity of device memory accesses. The recommended practice for coding device
863  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
864  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
865  * alt_write_dword() functions for 64 bit registers.
866  *
867  * The struct declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV.
868  */
869 struct ALT_NOC_FW_MMAP_PRIV_PRIV_s
870 {
871  volatile uint32_t nand_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER */
872  volatile uint32_t nand_data : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA */
873  uint32_t : 1; /* *UNDEFINED* */
874  volatile uint32_t usb0_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER */
875  volatile uint32_t usb1_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER */
876  volatile uint32_t dma_nonsecure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE */
877  volatile uint32_t dma_secure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE */
878  volatile uint32_t spi_master0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0 */
879  volatile uint32_t spi_master1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1 */
880  volatile uint32_t spi_slave0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0 */
881  volatile uint32_t spi_slave1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1 */
882  volatile uint32_t emac0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0 */
883  volatile uint32_t emac1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1 */
884  volatile uint32_t emac2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2 */
885  uint32_t : 2; /* *UNDEFINED* */
886  volatile uint32_t sdmmc : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC */
887  volatile uint32_t gpio0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0 */
888  volatile uint32_t gpio1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1 */
889  uint32_t : 1; /* *UNDEFINED* */
890  volatile uint32_t i2c0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0 */
891  volatile uint32_t i2c1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1 */
892  volatile uint32_t i2c2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2 */
893  volatile uint32_t i2c3 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3 */
894  volatile uint32_t i2c4 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4 */
895  volatile uint32_t sp_timer0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0 */
896  volatile uint32_t sp_timer1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1 */
897  volatile uint32_t uart0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_UART0 */
898  volatile uint32_t uart1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_UART1 */
899  volatile uint32_t lwsoc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA */
900  volatile uint32_t soc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA */
901  volatile uint32_t tcu : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_TCU */
902 };
903 
904 /* The typedef declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV. */
905 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_s ALT_NOC_FW_MMAP_PRIV_PRIV_t;
906 #endif /* __ASSEMBLY__ */
907 
908 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV register. */
909 #define ALT_NOC_FW_MMAP_PRIV_PRIV_RESET 0x00000000
910 /* The byte offset of the ALT_NOC_FW_MMAP_PRIV_PRIV register from the beginning of the component. */
911 #define ALT_NOC_FW_MMAP_PRIV_PRIV_OFST 0x0
912 
913 /*
914  * Register : priv_set
915  *
916  * Sets Region Enable field when written with 1
917  *
918  * Register Layout
919  *
920  * Bits | Access | Reset | Description
921  * :--------|:-------|:------|:--------------------------------------------
922  * [0] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER
923  * [1] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA
924  * [2] | ??? | 0x0 | *UNDEFINED*
925  * [3] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER
926  * [4] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER
927  * [5] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE
928  * [6] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE
929  * [7] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0
930  * [8] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1
931  * [9] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0
932  * [10] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1
933  * [11] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0
934  * [12] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1
935  * [13] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2
936  * [15:14] | ??? | 0x0 | *UNDEFINED*
937  * [16] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC
938  * [17] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0
939  * [18] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1
940  * [19] | ??? | 0x0 | *UNDEFINED*
941  * [20] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0
942  * [21] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1
943  * [22] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2
944  * [23] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3
945  * [24] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4
946  * [25] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0
947  * [26] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1
948  * [27] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0
949  * [28] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1
950  * [29] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA
951  * [30] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA
952  * [31] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU
953  *
954  */
955 /*
956  * Field : nand_register
957  *
958  * Privilege bit for nand register. Writing zero has no effect. Writing one will
959  * set the privilege bit
960  *
961  * Field Access Macros:
962  *
963  */
964 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field. */
965 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_LSB 0
966 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field. */
967 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_MSB 0
968 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field. */
969 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_WIDTH 1
970 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field value. */
971 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_SET_MSK 0x00000001
972 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field value. */
973 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_CLR_MSK 0xfffffffe
974 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field. */
975 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_RESET 0x0
976 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER field value from a register. */
977 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
978 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER register field value suitable for setting the register. */
979 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
980 
981 /*
982  * Field : nand_data
983  *
984  * Privilege bit for nand_data. Writing zero has no effect. Writing one will set
985  * the privilege bit
986  *
987  * Field Access Macros:
988  *
989  */
990 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field. */
991 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_LSB 1
992 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field. */
993 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_MSB 1
994 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field. */
995 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_WIDTH 1
996 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field value. */
997 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_SET_MSK 0x00000002
998 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field value. */
999 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_CLR_MSK 0xfffffffd
1000 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field. */
1001 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_RESET 0x0
1002 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA field value from a register. */
1003 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1004 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA register field value suitable for setting the register. */
1005 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1006 
1007 /*
1008  * Field : usb0_register
1009  *
1010  * Privilege bit for usb0_register. Writing zero has no effect. Writing one will
1011  * set the privilege bit
1012  *
1013  * Field Access Macros:
1014  *
1015  */
1016 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field. */
1017 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_LSB 3
1018 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field. */
1019 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_MSB 3
1020 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field. */
1021 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_WIDTH 1
1022 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field value. */
1023 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_SET_MSK 0x00000008
1024 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field value. */
1025 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_CLR_MSK 0xfffffff7
1026 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field. */
1027 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_RESET 0x0
1028 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER field value from a register. */
1029 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
1030 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER register field value suitable for setting the register. */
1031 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
1032 
1033 /*
1034  * Field : usb1_register
1035  *
1036  * Privilege bit for usb1_register. Writing zero has no effect. Writing one will
1037  * set the privilege bit
1038  *
1039  * Field Access Macros:
1040  *
1041  */
1042 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field. */
1043 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_LSB 4
1044 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field. */
1045 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_MSB 4
1046 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field. */
1047 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_WIDTH 1
1048 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field value. */
1049 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_SET_MSK 0x00000010
1050 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field value. */
1051 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_CLR_MSK 0xffffffef
1052 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field. */
1053 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_RESET 0x0
1054 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER field value from a register. */
1055 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
1056 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER register field value suitable for setting the register. */
1057 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
1058 
1059 /*
1060  * Field : dma_nonsecure
1061  *
1062  * Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will
1063  * set the privilege bit
1064  *
1065  * Field Access Macros:
1066  *
1067  */
1068 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field. */
1069 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_LSB 5
1070 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field. */
1071 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_MSB 5
1072 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field. */
1073 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_WIDTH 1
1074 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field value. */
1075 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_SET_MSK 0x00000020
1076 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field value. */
1077 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_CLR_MSK 0xffffffdf
1078 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field. */
1079 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_RESET 0x0
1080 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE field value from a register. */
1081 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1082 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE register field value suitable for setting the register. */
1083 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1084 
1085 /*
1086  * Field : dma_secure
1087  *
1088  * Privilege bit for dma_secure. Writing zero has no effect. Writing one will set
1089  * the privilege bit
1090  *
1091  * Field Access Macros:
1092  *
1093  */
1094 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field. */
1095 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_LSB 6
1096 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field. */
1097 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_MSB 6
1098 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field. */
1099 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_WIDTH 1
1100 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field value. */
1101 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_SET_MSK 0x00000040
1102 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field value. */
1103 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_CLR_MSK 0xffffffbf
1104 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field. */
1105 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_RESET 0x0
1106 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE field value from a register. */
1107 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1108 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE register field value suitable for setting the register. */
1109 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1110 
1111 /*
1112  * Field : spi_master0
1113  *
1114  * Privilege bit for spi_master0. Writing zero has no effect. Writing one will set
1115  * the privilege bit
1116  *
1117  * Field Access Macros:
1118  *
1119  */
1120 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field. */
1121 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_LSB 7
1122 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field. */
1123 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_MSB 7
1124 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field. */
1125 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_WIDTH 1
1126 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field value. */
1127 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_SET_MSK 0x00000080
1128 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field value. */
1129 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_CLR_MSK 0xffffff7f
1130 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field. */
1131 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_RESET 0x0
1132 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 field value from a register. */
1133 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
1134 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 register field value suitable for setting the register. */
1135 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
1136 
1137 /*
1138  * Field : spi_master1
1139  *
1140  * Privilege bit for spi_master1. Writing zero has no effect. Writing one will set
1141  * the privilege bit
1142  *
1143  * Field Access Macros:
1144  *
1145  */
1146 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field. */
1147 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_LSB 8
1148 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field. */
1149 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_MSB 8
1150 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field. */
1151 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_WIDTH 1
1152 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field value. */
1153 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_SET_MSK 0x00000100
1154 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field value. */
1155 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_CLR_MSK 0xfffffeff
1156 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field. */
1157 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_RESET 0x0
1158 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 field value from a register. */
1159 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
1160 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 register field value suitable for setting the register. */
1161 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
1162 
1163 /*
1164  * Field : spi_slave0
1165  *
1166  * Privilege bit for spi_slave0. Writing zero has no effect. Writing one will set
1167  * the privilege bit
1168  *
1169  * Field Access Macros:
1170  *
1171  */
1172 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field. */
1173 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_LSB 9
1174 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field. */
1175 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_MSB 9
1176 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field. */
1177 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_WIDTH 1
1178 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field value. */
1179 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_SET_MSK 0x00000200
1180 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field value. */
1181 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_CLR_MSK 0xfffffdff
1182 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field. */
1183 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_RESET 0x0
1184 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 field value from a register. */
1185 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
1186 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 register field value suitable for setting the register. */
1187 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
1188 
1189 /*
1190  * Field : spi_slave1
1191  *
1192  * Privilege bit for spi_slave1. Writing zero has no effect. Writing one will set
1193  * the privilege bit
1194  *
1195  * Field Access Macros:
1196  *
1197  */
1198 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field. */
1199 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_LSB 10
1200 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field. */
1201 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_MSB 10
1202 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field. */
1203 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_WIDTH 1
1204 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field value. */
1205 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_SET_MSK 0x00000400
1206 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field value. */
1207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_CLR_MSK 0xfffffbff
1208 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field. */
1209 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_RESET 0x0
1210 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 field value from a register. */
1211 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
1212 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 register field value suitable for setting the register. */
1213 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
1214 
1215 /*
1216  * Field : emac0
1217  *
1218  * Privilege bit for emac0. Writing zero has no effect. Writing one will set the
1219  * privilege bit
1220  *
1221  * Field Access Macros:
1222  *
1223  */
1224 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field. */
1225 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_LSB 11
1226 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field. */
1227 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_MSB 11
1228 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field. */
1229 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_WIDTH 1
1230 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field value. */
1231 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_SET_MSK 0x00000800
1232 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field value. */
1233 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_CLR_MSK 0xfffff7ff
1234 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field. */
1235 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_RESET 0x0
1236 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 field value from a register. */
1237 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
1238 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 register field value suitable for setting the register. */
1239 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_SET(value) (((value) << 11) & 0x00000800)
1240 
1241 /*
1242  * Field : emac1
1243  *
1244  * Privilege bit for emac1. Writing zero has no effect. Writing one will set the
1245  * privilege bit
1246  *
1247  * Field Access Macros:
1248  *
1249  */
1250 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field. */
1251 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_LSB 12
1252 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field. */
1253 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_MSB 12
1254 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field. */
1255 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_WIDTH 1
1256 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field value. */
1257 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_SET_MSK 0x00001000
1258 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field value. */
1259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_CLR_MSK 0xffffefff
1260 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field. */
1261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_RESET 0x0
1262 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 field value from a register. */
1263 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
1264 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 register field value suitable for setting the register. */
1265 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_SET(value) (((value) << 12) & 0x00001000)
1266 
1267 /*
1268  * Field : emac2
1269  *
1270  * Privilege bit for emac2. Writing zero has no effect. Writing one will set the
1271  * privilege bit
1272  *
1273  * Field Access Macros:
1274  *
1275  */
1276 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field. */
1277 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_LSB 13
1278 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field. */
1279 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_MSB 13
1280 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field. */
1281 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_WIDTH 1
1282 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field value. */
1283 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_SET_MSK 0x00002000
1284 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field value. */
1285 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_CLR_MSK 0xffffdfff
1286 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field. */
1287 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_RESET 0x0
1288 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 field value from a register. */
1289 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
1290 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 register field value suitable for setting the register. */
1291 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_SET(value) (((value) << 13) & 0x00002000)
1292 
1293 /*
1294  * Field : sdmmc
1295  *
1296  * Privilege bit for sdmmc. Writing zero has no effect. Writing one will set the
1297  * privilege bit
1298  *
1299  * Field Access Macros:
1300  *
1301  */
1302 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field. */
1303 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_LSB 16
1304 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field. */
1305 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_MSB 16
1306 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field. */
1307 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_WIDTH 1
1308 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field value. */
1309 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_SET_MSK 0x00010000
1310 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field value. */
1311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_CLR_MSK 0xfffeffff
1312 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field. */
1313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_RESET 0x0
1314 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC field value from a register. */
1315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
1316 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC register field value suitable for setting the register. */
1317 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_SET(value) (((value) << 16) & 0x00010000)
1318 
1319 /*
1320  * Field : gpio0
1321  *
1322  * Privilege bit for gpio0. Writing zero has no effect. Writing one will set the
1323  * privilege bit
1324  *
1325  * Field Access Macros:
1326  *
1327  */
1328 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field. */
1329 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_LSB 17
1330 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field. */
1331 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_MSB 17
1332 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field. */
1333 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_WIDTH 1
1334 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field value. */
1335 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_SET_MSK 0x00020000
1336 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field value. */
1337 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_CLR_MSK 0xfffdffff
1338 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field. */
1339 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_RESET 0x0
1340 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 field value from a register. */
1341 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
1342 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 register field value suitable for setting the register. */
1343 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_SET(value) (((value) << 17) & 0x00020000)
1344 
1345 /*
1346  * Field : gpio1
1347  *
1348  * Privilege bit for gpio1. Writing zero has no effect. Writing one will set the
1349  * privilege bit
1350  *
1351  * Field Access Macros:
1352  *
1353  */
1354 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field. */
1355 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_LSB 18
1356 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field. */
1357 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_MSB 18
1358 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field. */
1359 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_WIDTH 1
1360 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field value. */
1361 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_SET_MSK 0x00040000
1362 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field value. */
1363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_CLR_MSK 0xfffbffff
1364 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field. */
1365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_RESET 0x0
1366 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 field value from a register. */
1367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
1368 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 register field value suitable for setting the register. */
1369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_SET(value) (((value) << 18) & 0x00040000)
1370 
1371 /*
1372  * Field : i2c0
1373  *
1374  * Privilege bit for i2c0. Writing zero has no effect. Writing one will set the
1375  * privilege bit
1376  *
1377  * Field Access Macros:
1378  *
1379  */
1380 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field. */
1381 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_LSB 20
1382 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field. */
1383 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_MSB 20
1384 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field. */
1385 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_WIDTH 1
1386 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field value. */
1387 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_SET_MSK 0x00100000
1388 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field value. */
1389 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_CLR_MSK 0xffefffff
1390 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field. */
1391 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_RESET 0x0
1392 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 field value from a register. */
1393 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_GET(value) (((value) & 0x00100000) >> 20)
1394 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 register field value suitable for setting the register. */
1395 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_SET(value) (((value) << 20) & 0x00100000)
1396 
1397 /*
1398  * Field : i2c1
1399  *
1400  * Privilege bit for i2c1. Writing zero has no effect. Writing one will set the
1401  * privilege bit
1402  *
1403  * Field Access Macros:
1404  *
1405  */
1406 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field. */
1407 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_LSB 21
1408 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field. */
1409 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_MSB 21
1410 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field. */
1411 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_WIDTH 1
1412 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field value. */
1413 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_SET_MSK 0x00200000
1414 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field value. */
1415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_CLR_MSK 0xffdfffff
1416 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field. */
1417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_RESET 0x0
1418 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 field value from a register. */
1419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_GET(value) (((value) & 0x00200000) >> 21)
1420 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 register field value suitable for setting the register. */
1421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_SET(value) (((value) << 21) & 0x00200000)
1422 
1423 /*
1424  * Field : i2c2
1425  *
1426  * Privilege bit for i2c2. Writing zero has no effect. Writing one will set the
1427  * privilege bit
1428  *
1429  * Field Access Macros:
1430  *
1431  */
1432 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field. */
1433 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_LSB 22
1434 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field. */
1435 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_MSB 22
1436 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field. */
1437 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_WIDTH 1
1438 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field value. */
1439 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_SET_MSK 0x00400000
1440 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field value. */
1441 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_CLR_MSK 0xffbfffff
1442 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field. */
1443 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_RESET 0x0
1444 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 field value from a register. */
1445 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_GET(value) (((value) & 0x00400000) >> 22)
1446 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 register field value suitable for setting the register. */
1447 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_SET(value) (((value) << 22) & 0x00400000)
1448 
1449 /*
1450  * Field : i2c3
1451  *
1452  * Privilege bit for i2c3. Writing zero has no effect. Writing one will set the
1453  * privilege bit
1454  *
1455  * Field Access Macros:
1456  *
1457  */
1458 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field. */
1459 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_LSB 23
1460 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field. */
1461 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_MSB 23
1462 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field. */
1463 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_WIDTH 1
1464 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field value. */
1465 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_SET_MSK 0x00800000
1466 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field value. */
1467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_CLR_MSK 0xff7fffff
1468 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field. */
1469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_RESET 0x0
1470 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 field value from a register. */
1471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_GET(value) (((value) & 0x00800000) >> 23)
1472 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 register field value suitable for setting the register. */
1473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_SET(value) (((value) << 23) & 0x00800000)
1474 
1475 /*
1476  * Field : i2c4
1477  *
1478  * Privilege bit for i2c4. Writing zero has no effect. Writing one will set the
1479  * privilege bit
1480  *
1481  * Field Access Macros:
1482  *
1483  */
1484 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field. */
1485 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_LSB 24
1486 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field. */
1487 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_MSB 24
1488 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field. */
1489 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_WIDTH 1
1490 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field value. */
1491 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_SET_MSK 0x01000000
1492 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field value. */
1493 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_CLR_MSK 0xfeffffff
1494 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field. */
1495 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_RESET 0x0
1496 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 field value from a register. */
1497 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_GET(value) (((value) & 0x01000000) >> 24)
1498 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 register field value suitable for setting the register. */
1499 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_SET(value) (((value) << 24) & 0x01000000)
1500 
1501 /*
1502  * Field : sp_timer0
1503  *
1504  * Privilege bit for sp_timer0. Writing zero has no effect. Writing one will set
1505  * the privilege bit
1506  *
1507  * Field Access Macros:
1508  *
1509  */
1510 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field. */
1511 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_LSB 25
1512 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field. */
1513 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_MSB 25
1514 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field. */
1515 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_WIDTH 1
1516 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field value. */
1517 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_SET_MSK 0x02000000
1518 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field value. */
1519 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_CLR_MSK 0xfdffffff
1520 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field. */
1521 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_RESET 0x0
1522 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 field value from a register. */
1523 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
1524 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 register field value suitable for setting the register. */
1525 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
1526 
1527 /*
1528  * Field : sp_timer1
1529  *
1530  * Privilege bit for sp_timer1. Writing zero has no effect. Writing one will set
1531  * the privilege bit
1532  *
1533  * Field Access Macros:
1534  *
1535  */
1536 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field. */
1537 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_LSB 26
1538 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field. */
1539 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_MSB 26
1540 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field. */
1541 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_WIDTH 1
1542 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field value. */
1543 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_SET_MSK 0x04000000
1544 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field value. */
1545 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_CLR_MSK 0xfbffffff
1546 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field. */
1547 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_RESET 0x0
1548 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 field value from a register. */
1549 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
1550 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 register field value suitable for setting the register. */
1551 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
1552 
1553 /*
1554  * Field : uart0
1555  *
1556  * Privilege bit for uart0. Writing zero has no effect. Writing one will set the
1557  * privilege bit
1558  *
1559  * Field Access Macros:
1560  *
1561  */
1562 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field. */
1563 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_LSB 27
1564 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field. */
1565 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_MSB 27
1566 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field. */
1567 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_WIDTH 1
1568 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field value. */
1569 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_SET_MSK 0x08000000
1570 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field value. */
1571 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_CLR_MSK 0xf7ffffff
1572 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field. */
1573 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_RESET 0x0
1574 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 field value from a register. */
1575 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_GET(value) (((value) & 0x08000000) >> 27)
1576 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 register field value suitable for setting the register. */
1577 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_SET(value) (((value) << 27) & 0x08000000)
1578 
1579 /*
1580  * Field : uart1
1581  *
1582  * Privilege bit for uart1. Writing zero has no effect. Writing one will set the
1583  * privilege bit
1584  *
1585  * Field Access Macros:
1586  *
1587  */
1588 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field. */
1589 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_LSB 28
1590 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field. */
1591 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_MSB 28
1592 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field. */
1593 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_WIDTH 1
1594 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field value. */
1595 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_SET_MSK 0x10000000
1596 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field value. */
1597 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_CLR_MSK 0xefffffff
1598 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field. */
1599 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_RESET 0x0
1600 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 field value from a register. */
1601 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_GET(value) (((value) & 0x10000000) >> 28)
1602 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 register field value suitable for setting the register. */
1603 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_SET(value) (((value) << 28) & 0x10000000)
1604 
1605 /*
1606  * Field : lwsoc2fpga
1607  *
1608  * Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one
1609  * will set the privilege bit
1610  *
1611  * Field Access Macros:
1612  *
1613  */
1614 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field. */
1615 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_LSB 29
1616 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field. */
1617 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_MSB 29
1618 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field. */
1619 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_WIDTH 1
1620 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field value. */
1621 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_SET_MSK 0x20000000
1622 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field value. */
1623 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_CLR_MSK 0xdfffffff
1624 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field. */
1625 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_RESET 0x0
1626 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA field value from a register. */
1627 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
1628 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA register field value suitable for setting the register. */
1629 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
1630 
1631 /*
1632  * Field : soc2fpga
1633  *
1634  * Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will set the
1635  * privilege bit
1636  *
1637  * Field Access Macros:
1638  *
1639  */
1640 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field. */
1641 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_LSB 30
1642 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field. */
1643 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_MSB 30
1644 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field. */
1645 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_WIDTH 1
1646 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field value. */
1647 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_SET_MSK 0x40000000
1648 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field value. */
1649 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_CLR_MSK 0xbfffffff
1650 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field. */
1651 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_RESET 0x0
1652 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA field value from a register. */
1653 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
1654 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA register field value suitable for setting the register. */
1655 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
1656 
1657 /*
1658  * Field : tcu
1659  *
1660  * Privilege bit for TCU slave. Writing zero has no effect. Writing one will set
1661  * the privilege bit
1662  *
1663  * Field Access Macros:
1664  *
1665  */
1666 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field. */
1667 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_LSB 31
1668 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field. */
1669 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_MSB 31
1670 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field. */
1671 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_WIDTH 1
1672 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field value. */
1673 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_SET_MSK 0x80000000
1674 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field value. */
1675 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_CLR_MSK 0x7fffffff
1676 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field. */
1677 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_RESET 0x0
1678 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU field value from a register. */
1679 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_GET(value) (((value) & 0x80000000) >> 31)
1680 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU register field value suitable for setting the register. */
1681 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_SET(value) (((value) << 31) & 0x80000000)
1682 
1683 #ifndef __ASSEMBLY__
1684 /*
1685  * WARNING: The C register and register group struct declarations are provided for
1686  * convenience and illustrative purposes. They should, however, be used with
1687  * caution as the C language standard provides no guarantees about the alignment or
1688  * atomicity of device memory accesses. The recommended practice for coding device
1689  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1690  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1691  * alt_write_dword() functions for 64 bit registers.
1692  *
1693  * The struct declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV_SET.
1694  */
1695 struct ALT_NOC_FW_MMAP_PRIV_PRIV_SET_s
1696 {
1697  volatile uint32_t nand_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER */
1698  volatile uint32_t nand_data : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA */
1699  uint32_t : 1; /* *UNDEFINED* */
1700  volatile uint32_t usb0_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER */
1701  volatile uint32_t usb1_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER */
1702  volatile uint32_t dma_nonsecure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE */
1703  volatile uint32_t dma_secure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE */
1704  volatile uint32_t spi_master0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0 */
1705  volatile uint32_t spi_master1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1 */
1706  volatile uint32_t spi_slave0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0 */
1707  volatile uint32_t spi_slave1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1 */
1708  volatile uint32_t emac0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0 */
1709  volatile uint32_t emac1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1 */
1710  volatile uint32_t emac2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2 */
1711  uint32_t : 2; /* *UNDEFINED* */
1712  volatile uint32_t sdmmc : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC */
1713  volatile uint32_t gpio0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0 */
1714  volatile uint32_t gpio1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1 */
1715  uint32_t : 1; /* *UNDEFINED* */
1716  volatile uint32_t i2c0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0 */
1717  volatile uint32_t i2c1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1 */
1718  volatile uint32_t i2c2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2 */
1719  volatile uint32_t i2c3 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3 */
1720  volatile uint32_t i2c4 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4 */
1721  volatile uint32_t sp_timer0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0 */
1722  volatile uint32_t sp_timer1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1 */
1723  volatile uint32_t uart0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0 */
1724  volatile uint32_t uart1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1 */
1725  volatile uint32_t lwsoc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA */
1726  volatile uint32_t soc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA */
1727  volatile uint32_t tcu : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU */
1728 };
1729 
1730 /* The typedef declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV_SET. */
1731 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_SET_s ALT_NOC_FW_MMAP_PRIV_PRIV_SET_t;
1732 #endif /* __ASSEMBLY__ */
1733 
1734 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET register. */
1735 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_RESET 0x00000000
1736 /* The byte offset of the ALT_NOC_FW_MMAP_PRIV_PRIV_SET register from the beginning of the component. */
1737 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_OFST 0x4
1738 
1739 /*
1740  * Register : priv_clear
1741  *
1742  * Clears Region Enable field when written with 1
1743  *
1744  * Register Layout
1745  *
1746  * Bits | Access | Reset | Description
1747  * :--------|:-------|:------|:----------------------------------------------
1748  * [0] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER
1749  * [1] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA
1750  * [2] | ??? | 0x0 | *UNDEFINED*
1751  * [3] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER
1752  * [4] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER
1753  * [5] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE
1754  * [6] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE
1755  * [7] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0
1756  * [8] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1
1757  * [9] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0
1758  * [10] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1
1759  * [11] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0
1760  * [12] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1
1761  * [13] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2
1762  * [15:14] | ??? | 0x0 | *UNDEFINED*
1763  * [16] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC
1764  * [17] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0
1765  * [18] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1
1766  * [19] | ??? | 0x0 | *UNDEFINED*
1767  * [20] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0
1768  * [21] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1
1769  * [22] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2
1770  * [23] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3
1771  * [24] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4
1772  * [25] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0
1773  * [26] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1
1774  * [27] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0
1775  * [28] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1
1776  * [29] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA
1777  * [30] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA
1778  * [31] | W | 0x0 | ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU
1779  *
1780  */
1781 /*
1782  * Field : nand_register
1783  *
1784  * Privilege bit for nand register. Writing zero has no effect. Writing one will
1785  * clear the privilege bit
1786  *
1787  * Field Access Macros:
1788  *
1789  */
1790 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field. */
1791 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_LSB 0
1792 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field. */
1793 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_MSB 0
1794 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field. */
1795 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_WIDTH 1
1796 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field value. */
1797 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_SET_MSK 0x00000001
1798 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field value. */
1799 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_CLR_MSK 0xfffffffe
1800 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field. */
1801 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_RESET 0x0
1802 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER field value from a register. */
1803 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
1804 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER register field value suitable for setting the register. */
1805 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
1806 
1807 /*
1808  * Field : nand_data
1809  *
1810  * Privilege bit for nand_data. Writing zero has no effect. Writing one will clear
1811  * the privilege bit
1812  *
1813  * Field Access Macros:
1814  *
1815  */
1816 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field. */
1817 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_LSB 1
1818 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field. */
1819 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_MSB 1
1820 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field. */
1821 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_WIDTH 1
1822 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field value. */
1823 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_SET_MSK 0x00000002
1824 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field value. */
1825 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_CLR_MSK 0xfffffffd
1826 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field. */
1827 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_RESET 0x0
1828 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA field value from a register. */
1829 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1830 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA register field value suitable for setting the register. */
1831 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1832 
1833 /*
1834  * Field : usb0_register
1835  *
1836  * Privilege bit for usb0_register. Writing zero has no effect. Writing one will
1837  * clear the privilege bit
1838  *
1839  * Field Access Macros:
1840  *
1841  */
1842 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field. */
1843 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_LSB 3
1844 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field. */
1845 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_MSB 3
1846 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field. */
1847 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_WIDTH 1
1848 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field value. */
1849 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_SET_MSK 0x00000008
1850 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field value. */
1851 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_CLR_MSK 0xfffffff7
1852 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field. */
1853 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_RESET 0x0
1854 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER field value from a register. */
1855 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
1856 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER register field value suitable for setting the register. */
1857 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
1858 
1859 /*
1860  * Field : usb1_register
1861  *
1862  * Privilege bit for usb1_register. Writing zero has no effect. Writing one will
1863  * clear the privilege bit
1864  *
1865  * Field Access Macros:
1866  *
1867  */
1868 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field. */
1869 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_LSB 4
1870 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field. */
1871 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_MSB 4
1872 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field. */
1873 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_WIDTH 1
1874 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field value. */
1875 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_SET_MSK 0x00000010
1876 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field value. */
1877 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_CLR_MSK 0xffffffef
1878 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field. */
1879 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_RESET 0x0
1880 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER field value from a register. */
1881 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
1882 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER register field value suitable for setting the register. */
1883 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
1884 
1885 /*
1886  * Field : dma_nonsecure
1887  *
1888  * Privilege bit for dma_nonsecure. Writing zero has no effect. Writing one will
1889  * clear the privilege bit
1890  *
1891  * Field Access Macros:
1892  *
1893  */
1894 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field. */
1895 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_LSB 5
1896 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field. */
1897 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_MSB 5
1898 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field. */
1899 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_WIDTH 1
1900 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field value. */
1901 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_SET_MSK 0x00000020
1902 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field value. */
1903 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_CLR_MSK 0xffffffdf
1904 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field. */
1905 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_RESET 0x0
1906 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE field value from a register. */
1907 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1908 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE register field value suitable for setting the register. */
1909 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1910 
1911 /*
1912  * Field : dma_secure
1913  *
1914  * Privilege bit for dma_secure. Writing zero has no effect. Writing one will clear
1915  * the privilege bit
1916  *
1917  * Field Access Macros:
1918  *
1919  */
1920 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field. */
1921 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_LSB 6
1922 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field. */
1923 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_MSB 6
1924 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field. */
1925 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_WIDTH 1
1926 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field value. */
1927 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_SET_MSK 0x00000040
1928 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field value. */
1929 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_CLR_MSK 0xffffffbf
1930 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field. */
1931 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_RESET 0x0
1932 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE field value from a register. */
1933 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1934 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE register field value suitable for setting the register. */
1935 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1936 
1937 /*
1938  * Field : spi_master0
1939  *
1940  * Privilege bit for spi_master0. Writing zero has no effect. Writing one will
1941  * clear the privilege bit
1942  *
1943  * Field Access Macros:
1944  *
1945  */
1946 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field. */
1947 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_LSB 7
1948 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field. */
1949 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_MSB 7
1950 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field. */
1951 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_WIDTH 1
1952 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field value. */
1953 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_SET_MSK 0x00000080
1954 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field value. */
1955 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_CLR_MSK 0xffffff7f
1956 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field. */
1957 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_RESET 0x0
1958 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 field value from a register. */
1959 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
1960 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 register field value suitable for setting the register. */
1961 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
1962 
1963 /*
1964  * Field : spi_master1
1965  *
1966  * Privilege bit for spi_master1. Writing zero has no effect. Writing one will
1967  * clear the privilege bit
1968  *
1969  * Field Access Macros:
1970  *
1971  */
1972 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field. */
1973 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_LSB 8
1974 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field. */
1975 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_MSB 8
1976 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field. */
1977 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_WIDTH 1
1978 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field value. */
1979 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_SET_MSK 0x00000100
1980 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field value. */
1981 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_CLR_MSK 0xfffffeff
1982 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field. */
1983 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_RESET 0x0
1984 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 field value from a register. */
1985 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
1986 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 register field value suitable for setting the register. */
1987 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
1988 
1989 /*
1990  * Field : spi_slave0
1991  *
1992  * Privilege bit for spi_slave0. Writing zero has no effect. Writing one will clear
1993  * the privilege bit
1994  *
1995  * Field Access Macros:
1996  *
1997  */
1998 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field. */
1999 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_LSB 9
2000 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field. */
2001 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_MSB 9
2002 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field. */
2003 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_WIDTH 1
2004 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field value. */
2005 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_SET_MSK 0x00000200
2006 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field value. */
2007 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_CLR_MSK 0xfffffdff
2008 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field. */
2009 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_RESET 0x0
2010 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 field value from a register. */
2011 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
2012 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 register field value suitable for setting the register. */
2013 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
2014 
2015 /*
2016  * Field : spi_slave1
2017  *
2018  * Privilege bit for spi_slave1. Writing zero has no effect. Writing one will clear
2019  * the privilege bit
2020  *
2021  * Field Access Macros:
2022  *
2023  */
2024 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field. */
2025 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_LSB 10
2026 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field. */
2027 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_MSB 10
2028 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field. */
2029 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_WIDTH 1
2030 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field value. */
2031 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_SET_MSK 0x00000400
2032 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field value. */
2033 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_CLR_MSK 0xfffffbff
2034 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field. */
2035 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_RESET 0x0
2036 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 field value from a register. */
2037 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
2038 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 register field value suitable for setting the register. */
2039 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
2040 
2041 /*
2042  * Field : emac0
2043  *
2044  * Privilege bit for emac0. Writing zero has no effect. Writing one will clear the
2045  * privilege bit
2046  *
2047  * Field Access Macros:
2048  *
2049  */
2050 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field. */
2051 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_LSB 11
2052 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field. */
2053 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_MSB 11
2054 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field. */
2055 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_WIDTH 1
2056 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field value. */
2057 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_SET_MSK 0x00000800
2058 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field value. */
2059 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_CLR_MSK 0xfffff7ff
2060 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field. */
2061 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_RESET 0x0
2062 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 field value from a register. */
2063 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
2064 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 register field value suitable for setting the register. */
2065 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_SET(value) (((value) << 11) & 0x00000800)
2066 
2067 /*
2068  * Field : emac1
2069  *
2070  * Privilege bit for emac1. Writing zero has no effect. Writing one will clear the
2071  * privilege bit
2072  *
2073  * Field Access Macros:
2074  *
2075  */
2076 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field. */
2077 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_LSB 12
2078 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field. */
2079 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_MSB 12
2080 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field. */
2081 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_WIDTH 1
2082 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field value. */
2083 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_SET_MSK 0x00001000
2084 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field value. */
2085 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_CLR_MSK 0xffffefff
2086 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field. */
2087 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_RESET 0x0
2088 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 field value from a register. */
2089 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
2090 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 register field value suitable for setting the register. */
2091 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_SET(value) (((value) << 12) & 0x00001000)
2092 
2093 /*
2094  * Field : emac2
2095  *
2096  * Privilege bit for emac2. Writing zero has no effect. Writing one will clear the
2097  * privilege bit
2098  *
2099  * Field Access Macros:
2100  *
2101  */
2102 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field. */
2103 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_LSB 13
2104 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field. */
2105 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_MSB 13
2106 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field. */
2107 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_WIDTH 1
2108 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field value. */
2109 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_SET_MSK 0x00002000
2110 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field value. */
2111 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_CLR_MSK 0xffffdfff
2112 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field. */
2113 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_RESET 0x0
2114 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 field value from a register. */
2115 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
2116 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 register field value suitable for setting the register. */
2117 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_SET(value) (((value) << 13) & 0x00002000)
2118 
2119 /*
2120  * Field : sdmmc
2121  *
2122  * Privilege bit for sdmmc. Writing zero has no effect. Writing one will clear the
2123  * privilege bit
2124  *
2125  * Field Access Macros:
2126  *
2127  */
2128 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field. */
2129 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_LSB 16
2130 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field. */
2131 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_MSB 16
2132 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field. */
2133 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_WIDTH 1
2134 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field value. */
2135 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_SET_MSK 0x00010000
2136 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field value. */
2137 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_CLR_MSK 0xfffeffff
2138 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field. */
2139 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_RESET 0x0
2140 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC field value from a register. */
2141 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
2142 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC register field value suitable for setting the register. */
2143 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_SET(value) (((value) << 16) & 0x00010000)
2144 
2145 /*
2146  * Field : gpio0
2147  *
2148  * Privilege bit for gpio0. Writing zero has no effect. Writing one will clear the
2149  * privilege bit
2150  *
2151  * Field Access Macros:
2152  *
2153  */
2154 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field. */
2155 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_LSB 17
2156 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field. */
2157 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_MSB 17
2158 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field. */
2159 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_WIDTH 1
2160 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field value. */
2161 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_SET_MSK 0x00020000
2162 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field value. */
2163 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_CLR_MSK 0xfffdffff
2164 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field. */
2165 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_RESET 0x0
2166 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 field value from a register. */
2167 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
2168 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 register field value suitable for setting the register. */
2169 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_SET(value) (((value) << 17) & 0x00020000)
2170 
2171 /*
2172  * Field : gpio1
2173  *
2174  * Privilege bit for gpio1. Writing zero has no effect. Writing one will clear the
2175  * privilege bit
2176  *
2177  * Field Access Macros:
2178  *
2179  */
2180 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field. */
2181 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_LSB 18
2182 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field. */
2183 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_MSB 18
2184 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field. */
2185 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_WIDTH 1
2186 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field value. */
2187 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_SET_MSK 0x00040000
2188 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field value. */
2189 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_CLR_MSK 0xfffbffff
2190 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field. */
2191 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_RESET 0x0
2192 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 field value from a register. */
2193 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
2194 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 register field value suitable for setting the register. */
2195 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_SET(value) (((value) << 18) & 0x00040000)
2196 
2197 /*
2198  * Field : i2c0
2199  *
2200  * Privilege bit for i2c0. Writing zero has no effect. Writing one will clear the
2201  * privilege bit
2202  *
2203  * Field Access Macros:
2204  *
2205  */
2206 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field. */
2207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_LSB 20
2208 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field. */
2209 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_MSB 20
2210 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field. */
2211 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_WIDTH 1
2212 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field value. */
2213 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_SET_MSK 0x00100000
2214 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field value. */
2215 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_CLR_MSK 0xffefffff
2216 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field. */
2217 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_RESET 0x0
2218 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 field value from a register. */
2219 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_GET(value) (((value) & 0x00100000) >> 20)
2220 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 register field value suitable for setting the register. */
2221 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_SET(value) (((value) << 20) & 0x00100000)
2222 
2223 /*
2224  * Field : i2c1
2225  *
2226  * Privilege bit for i2c1. Writing zero has no effect. Writing one will clear the
2227  * privilege bit
2228  *
2229  * Field Access Macros:
2230  *
2231  */
2232 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field. */
2233 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_LSB 21
2234 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field. */
2235 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_MSB 21
2236 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field. */
2237 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_WIDTH 1
2238 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field value. */
2239 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_SET_MSK 0x00200000
2240 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field value. */
2241 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_CLR_MSK 0xffdfffff
2242 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field. */
2243 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_RESET 0x0
2244 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 field value from a register. */
2245 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_GET(value) (((value) & 0x00200000) >> 21)
2246 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 register field value suitable for setting the register. */
2247 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_SET(value) (((value) << 21) & 0x00200000)
2248 
2249 /*
2250  * Field : i2c2
2251  *
2252  * Privilege bit for i2c2. Writing zero has no effect. Writing one will clear the
2253  * privilege bit
2254  *
2255  * Field Access Macros:
2256  *
2257  */
2258 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field. */
2259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_LSB 22
2260 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field. */
2261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_MSB 22
2262 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field. */
2263 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_WIDTH 1
2264 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field value. */
2265 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_SET_MSK 0x00400000
2266 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field value. */
2267 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_CLR_MSK 0xffbfffff
2268 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field. */
2269 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_RESET 0x0
2270 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 field value from a register. */
2271 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_GET(value) (((value) & 0x00400000) >> 22)
2272 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 register field value suitable for setting the register. */
2273 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_SET(value) (((value) << 22) & 0x00400000)
2274 
2275 /*
2276  * Field : i2c3
2277  *
2278  * Privilege bit for i2c3. Writing zero has no effect. Writing one will clear the
2279  * privilege bit
2280  *
2281  * Field Access Macros:
2282  *
2283  */
2284 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field. */
2285 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_LSB 23
2286 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field. */
2287 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_MSB 23
2288 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field. */
2289 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_WIDTH 1
2290 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field value. */
2291 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_SET_MSK 0x00800000
2292 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field value. */
2293 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_CLR_MSK 0xff7fffff
2294 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field. */
2295 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_RESET 0x0
2296 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 field value from a register. */
2297 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_GET(value) (((value) & 0x00800000) >> 23)
2298 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 register field value suitable for setting the register. */
2299 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_SET(value) (((value) << 23) & 0x00800000)
2300 
2301 /*
2302  * Field : i2c4
2303  *
2304  * Privilege bit for i2c4. Writing zero has no effect. Writing one will clear the
2305  * privilege bit
2306  *
2307  * Field Access Macros:
2308  *
2309  */
2310 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field. */
2311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_LSB 24
2312 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field. */
2313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_MSB 24
2314 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field. */
2315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_WIDTH 1
2316 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field value. */
2317 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_SET_MSK 0x01000000
2318 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field value. */
2319 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_CLR_MSK 0xfeffffff
2320 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field. */
2321 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_RESET 0x0
2322 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 field value from a register. */
2323 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_GET(value) (((value) & 0x01000000) >> 24)
2324 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 register field value suitable for setting the register. */
2325 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_SET(value) (((value) << 24) & 0x01000000)
2326 
2327 /*
2328  * Field : sp_timer0
2329  *
2330  * Privilege bit for sp_timer0. Writing zero has no effect. Writing one will clear
2331  * the privilege bit
2332  *
2333  * Field Access Macros:
2334  *
2335  */
2336 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field. */
2337 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_LSB 25
2338 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field. */
2339 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_MSB 25
2340 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field. */
2341 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_WIDTH 1
2342 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field value. */
2343 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_SET_MSK 0x02000000
2344 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field value. */
2345 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_CLR_MSK 0xfdffffff
2346 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field. */
2347 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_RESET 0x0
2348 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 field value from a register. */
2349 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
2350 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 register field value suitable for setting the register. */
2351 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
2352 
2353 /*
2354  * Field : sp_timer1
2355  *
2356  * Privilege bit for sp_timer1. Writing zero has no effect. Writing one will clear
2357  * the privilege bit
2358  *
2359  * Field Access Macros:
2360  *
2361  */
2362 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field. */
2363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_LSB 26
2364 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field. */
2365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_MSB 26
2366 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field. */
2367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_WIDTH 1
2368 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field value. */
2369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_SET_MSK 0x04000000
2370 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field value. */
2371 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_CLR_MSK 0xfbffffff
2372 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field. */
2373 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_RESET 0x0
2374 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 field value from a register. */
2375 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
2376 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 register field value suitable for setting the register. */
2377 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
2378 
2379 /*
2380  * Field : uart0
2381  *
2382  * Privilege bit for uart0. Writing zero has no effect. Writing one will clear the
2383  * privilege bit
2384  *
2385  * Field Access Macros:
2386  *
2387  */
2388 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field. */
2389 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_LSB 27
2390 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field. */
2391 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_MSB 27
2392 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field. */
2393 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_WIDTH 1
2394 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field value. */
2395 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_SET_MSK 0x08000000
2396 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field value. */
2397 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_CLR_MSK 0xf7ffffff
2398 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field. */
2399 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_RESET 0x0
2400 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 field value from a register. */
2401 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_GET(value) (((value) & 0x08000000) >> 27)
2402 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 register field value suitable for setting the register. */
2403 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_SET(value) (((value) << 27) & 0x08000000)
2404 
2405 /*
2406  * Field : uart1
2407  *
2408  * Privilege bit for uart1. Writing zero has no effect. Writing one will clear the
2409  * privilege bit
2410  *
2411  * Field Access Macros:
2412  *
2413  */
2414 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field. */
2415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_LSB 28
2416 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field. */
2417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_MSB 28
2418 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field. */
2419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_WIDTH 1
2420 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field value. */
2421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_SET_MSK 0x10000000
2422 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field value. */
2423 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_CLR_MSK 0xefffffff
2424 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field. */
2425 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_RESET 0x0
2426 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 field value from a register. */
2427 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_GET(value) (((value) & 0x10000000) >> 28)
2428 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 register field value suitable for setting the register. */
2429 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_SET(value) (((value) << 28) & 0x10000000)
2430 
2431 /*
2432  * Field : lwsoc2fpga
2433  *
2434  * Privilege bit for Lightweight SOC2FPGA. Writing zero has no effect. Writing one
2435  * will clear the privilege bit
2436  *
2437  * Field Access Macros:
2438  *
2439  */
2440 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field. */
2441 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_LSB 29
2442 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field. */
2443 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_MSB 29
2444 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field. */
2445 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_WIDTH 1
2446 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field value. */
2447 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_SET_MSK 0x20000000
2448 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field value. */
2449 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_CLR_MSK 0xdfffffff
2450 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field. */
2451 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_RESET 0x0
2452 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA field value from a register. */
2453 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
2454 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA register field value suitable for setting the register. */
2455 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
2456 
2457 /*
2458  * Field : soc2fpga
2459  *
2460  * Privilege bit for SOC2FPGA. Writing zero has no effect. Writing one will clear
2461  * the privilege bit
2462  *
2463  * Field Access Macros:
2464  *
2465  */
2466 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field. */
2467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_LSB 30
2468 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field. */
2469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_MSB 30
2470 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field. */
2471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_WIDTH 1
2472 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field value. */
2473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_SET_MSK 0x40000000
2474 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field value. */
2475 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_CLR_MSK 0xbfffffff
2476 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field. */
2477 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_RESET 0x0
2478 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA field value from a register. */
2479 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
2480 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA register field value suitable for setting the register. */
2481 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
2482 
2483 /*
2484  * Field : tcu
2485  *
2486  * Privilege bit for TCU slave. Writing zero has no effect. Writing one will clear
2487  * the privilege bit
2488  *
2489  * Field Access Macros:
2490  *
2491  */
2492 /* The Least Significant Bit (LSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field. */
2493 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_LSB 31
2494 /* The Most Significant Bit (MSB) position of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field. */
2495 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_MSB 31
2496 /* The width in bits of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field. */
2497 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_WIDTH 1
2498 /* The mask used to set the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field value. */
2499 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_SET_MSK 0x80000000
2500 /* The mask used to clear the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field value. */
2501 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_CLR_MSK 0x7fffffff
2502 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field. */
2503 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_RESET 0x0
2504 /* Extracts the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU field value from a register. */
2505 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_GET(value) (((value) & 0x80000000) >> 31)
2506 /* Produces a ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU register field value suitable for setting the register. */
2507 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_SET(value) (((value) << 31) & 0x80000000)
2508 
2509 #ifndef __ASSEMBLY__
2510 /*
2511  * WARNING: The C register and register group struct declarations are provided for
2512  * convenience and illustrative purposes. They should, however, be used with
2513  * caution as the C language standard provides no guarantees about the alignment or
2514  * atomicity of device memory accesses. The recommended practice for coding device
2515  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2516  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2517  * alt_write_dword() functions for 64 bit registers.
2518  *
2519  * The struct declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR.
2520  */
2521 struct ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_s
2522 {
2523  volatile uint32_t nand_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER */
2524  volatile uint32_t nand_data : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA */
2525  uint32_t : 1; /* *UNDEFINED* */
2526  volatile uint32_t usb0_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER */
2527  volatile uint32_t usb1_register : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER */
2528  volatile uint32_t dma_nonsecure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE */
2529  volatile uint32_t dma_secure : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE */
2530  volatile uint32_t spi_master0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0 */
2531  volatile uint32_t spi_master1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1 */
2532  volatile uint32_t spi_slave0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0 */
2533  volatile uint32_t spi_slave1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1 */
2534  volatile uint32_t emac0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0 */
2535  volatile uint32_t emac1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1 */
2536  volatile uint32_t emac2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2 */
2537  uint32_t : 2; /* *UNDEFINED* */
2538  volatile uint32_t sdmmc : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC */
2539  volatile uint32_t gpio0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0 */
2540  volatile uint32_t gpio1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1 */
2541  uint32_t : 1; /* *UNDEFINED* */
2542  volatile uint32_t i2c0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0 */
2543  volatile uint32_t i2c1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1 */
2544  volatile uint32_t i2c2 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2 */
2545  volatile uint32_t i2c3 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3 */
2546  volatile uint32_t i2c4 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4 */
2547  volatile uint32_t sp_timer0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0 */
2548  volatile uint32_t sp_timer1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1 */
2549  volatile uint32_t uart0 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0 */
2550  volatile uint32_t uart1 : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1 */
2551  volatile uint32_t lwsoc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA */
2552  volatile uint32_t soc2fpga : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA */
2553  volatile uint32_t tcu : 1; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU */
2554 };
2555 
2556 /* The typedef declaration for register ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR. */
2557 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_s ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_t;
2558 #endif /* __ASSEMBLY__ */
2559 
2560 /* The reset value of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR register. */
2561 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_RESET 0x00000000
2562 /* The byte offset of the ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR register from the beginning of the component. */
2563 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_OFST 0x8
2564 
2565 #ifndef __ASSEMBLY__
2566 /*
2567  * WARNING: The C register and register group struct declarations are provided for
2568  * convenience and illustrative purposes. They should, however, be used with
2569  * caution as the C language standard provides no guarantees about the alignment or
2570  * atomicity of device memory accesses. The recommended practice for coding device
2571  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2572  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2573  * alt_write_dword() functions for 64 bit registers.
2574  *
2575  * The struct declaration for register group ALT_NOC_FW_MMAP_PRIV.
2576  */
2577 struct ALT_NOC_FW_MMAP_PRIV_s
2578 {
2579  volatile ALT_NOC_FW_MMAP_PRIV_PRIV_t priv; /* ALT_NOC_FW_MMAP_PRIV_PRIV */
2580  volatile ALT_NOC_FW_MMAP_PRIV_PRIV_SET_t priv_set; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET */
2581  volatile ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_t priv_clear; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR */
2582  volatile uint32_t _pad_0xc_0x100[61]; /* *UNDEFINED* */
2583 };
2584 
2585 /* The typedef declaration for register group ALT_NOC_FW_MMAP_PRIV. */
2586 typedef struct ALT_NOC_FW_MMAP_PRIV_s ALT_NOC_FW_MMAP_PRIV_t;
2587 /* The struct declaration for the raw register contents of register group ALT_NOC_FW_MMAP_PRIV. */
2588 struct ALT_NOC_FW_MMAP_PRIV_raw_s
2589 {
2590  volatile uint32_t priv; /* ALT_NOC_FW_MMAP_PRIV_PRIV */
2591  volatile uint32_t priv_set; /* ALT_NOC_FW_MMAP_PRIV_PRIV_SET */
2592  volatile uint32_t priv_clear; /* ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR */
2593  volatile uint32_t _pad_0xc_0x100[61]; /* *UNDEFINED* */
2594 };
2595 
2596 /* The typedef declaration for the raw register contents of register group ALT_NOC_FW_MMAP_PRIV. */
2597 typedef struct ALT_NOC_FW_MMAP_PRIV_raw_s ALT_NOC_FW_MMAP_PRIV_raw_t;
2598 #endif /* __ASSEMBLY__ */
2599 
2600 
2601 #ifdef __cplusplus
2602 }
2603 #endif /* __cplusplus */
2604 #endif /* __ALT_SOCAL_NOC_FW_MMAP_PRIV_H__ */
2605