35 #ifndef __ALT_SOCAL_NOC_FW_MMAP_PRIV_H__
36 #define __ALT_SOCAL_NOC_FW_MMAP_PRIV_H__
112 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_LSB 0
114 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_MSB 0
116 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_WIDTH 1
118 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_SET_MSK 0x00000001
120 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_CLR_MSK 0xfffffffe
122 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_RESET 0x0
124 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
126 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
139 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_LSB 1
141 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_MSB 1
143 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_WIDTH 1
145 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_SET_MSK 0x00000002
147 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_CLR_MSK 0xfffffffd
149 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_RESET 0x0
151 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
153 #define ALT_NOC_FW_MMAP_PRIV_PRIV_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
166 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_LSB 3
168 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_MSB 3
170 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_WIDTH 1
172 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_SET_MSK 0x00000008
174 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_CLR_MSK 0xfffffff7
176 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_RESET 0x0
178 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
180 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
193 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_LSB 4
195 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_MSB 4
197 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_WIDTH 1
199 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_SET_MSK 0x00000010
201 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_CLR_MSK 0xffffffef
203 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_RESET 0x0
205 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
220 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_LSB 5
222 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_MSB 5
224 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_WIDTH 1
226 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_SET_MSK 0x00000020
228 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_CLR_MSK 0xffffffdf
230 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_RESET 0x0
232 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
234 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
247 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_LSB 6
249 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_MSB 6
251 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_WIDTH 1
253 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_SET_MSK 0x00000040
255 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_CLR_MSK 0xffffffbf
257 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_RESET 0x0
259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
274 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_LSB 7
276 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_MSB 7
278 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_WIDTH 1
280 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_SET_MSK 0x00000080
282 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_CLR_MSK 0xffffff7f
284 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_RESET 0x0
286 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
288 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
301 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_LSB 8
303 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_MSB 8
305 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_WIDTH 1
307 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_SET_MSK 0x00000100
309 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_CLR_MSK 0xfffffeff
311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_RESET 0x0
313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
328 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_LSB 9
330 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_MSB 9
332 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_WIDTH 1
334 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_SET_MSK 0x00000200
336 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_CLR_MSK 0xfffffdff
338 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_RESET 0x0
340 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
342 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
355 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_LSB 10
357 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_MSB 10
359 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_WIDTH 1
361 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_SET_MSK 0x00000400
363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_CLR_MSK 0xfffffbff
365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_RESET 0x0
367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
382 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_LSB 11
384 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_MSB 11
386 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_WIDTH 1
388 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_SET_MSK 0x00000800
390 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_CLR_MSK 0xfffff7ff
392 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_RESET 0x0
394 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
396 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC0_SET(value) (((value) << 11) & 0x00000800)
409 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_LSB 12
411 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_MSB 12
413 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_WIDTH 1
415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_SET_MSK 0x00001000
417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_CLR_MSK 0xffffefff
419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_RESET 0x0
421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
423 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC1_SET(value) (((value) << 12) & 0x00001000)
436 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_LSB 13
438 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_MSB 13
440 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_WIDTH 1
442 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_SET_MSK 0x00002000
444 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_CLR_MSK 0xffffdfff
446 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_RESET 0x0
448 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
450 #define ALT_NOC_FW_MMAP_PRIV_PRIV_EMAC2_SET(value) (((value) << 13) & 0x00002000)
463 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_LSB 16
465 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_MSB 16
467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_WIDTH 1
469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_SET_MSK 0x00010000
471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_CLR_MSK 0xfffeffff
473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_RESET 0x0
475 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
477 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SDMMC_SET(value) (((value) << 16) & 0x00010000)
490 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_LSB 17
492 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_MSB 17
494 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_WIDTH 1
496 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_SET_MSK 0x00020000
498 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_CLR_MSK 0xfffdffff
500 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_RESET 0x0
502 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
504 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO0_SET(value) (((value) << 17) & 0x00020000)
517 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_LSB 18
519 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_MSB 18
521 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_WIDTH 1
523 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_SET_MSK 0x00040000
525 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_CLR_MSK 0xfffbffff
527 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_RESET 0x0
529 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
531 #define ALT_NOC_FW_MMAP_PRIV_PRIV_GPIO1_SET(value) (((value) << 18) & 0x00040000)
544 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_LSB 20
546 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_MSB 20
548 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_WIDTH 1
550 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_SET_MSK 0x00100000
552 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_CLR_MSK 0xffefffff
554 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_RESET 0x0
556 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_GET(value) (((value) & 0x00100000) >> 20)
558 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C0_SET(value) (((value) << 20) & 0x00100000)
571 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_LSB 21
573 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_MSB 21
575 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_WIDTH 1
577 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_SET_MSK 0x00200000
579 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_CLR_MSK 0xffdfffff
581 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_RESET 0x0
583 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_GET(value) (((value) & 0x00200000) >> 21)
585 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C1_SET(value) (((value) << 21) & 0x00200000)
598 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_LSB 22
600 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_MSB 22
602 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_WIDTH 1
604 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_SET_MSK 0x00400000
606 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_CLR_MSK 0xffbfffff
608 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_RESET 0x0
610 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_GET(value) (((value) & 0x00400000) >> 22)
612 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C2_SET(value) (((value) << 22) & 0x00400000)
625 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_LSB 23
627 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_MSB 23
629 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_WIDTH 1
631 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_SET_MSK 0x00800000
633 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_CLR_MSK 0xff7fffff
635 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_RESET 0x0
637 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_GET(value) (((value) & 0x00800000) >> 23)
639 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C3_SET(value) (((value) << 23) & 0x00800000)
652 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_LSB 24
654 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_MSB 24
656 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_WIDTH 1
658 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_SET_MSK 0x01000000
660 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_CLR_MSK 0xfeffffff
662 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_RESET 0x0
664 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_GET(value) (((value) & 0x01000000) >> 24)
666 #define ALT_NOC_FW_MMAP_PRIV_PRIV_I2C4_SET(value) (((value) << 24) & 0x01000000)
679 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_LSB 25
681 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_MSB 25
683 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_WIDTH 1
685 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_SET_MSK 0x02000000
687 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_CLR_MSK 0xfdffffff
689 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_RESET 0x0
691 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
693 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
706 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_LSB 26
708 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_MSB 26
710 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_WIDTH 1
712 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_SET_MSK 0x04000000
714 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_CLR_MSK 0xfbffffff
716 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_RESET 0x0
718 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
720 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
733 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_LSB 27
735 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_MSB 27
737 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_WIDTH 1
739 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_SET_MSK 0x08000000
741 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_CLR_MSK 0xf7ffffff
743 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_RESET 0x0
745 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_GET(value) (((value) & 0x08000000) >> 27)
747 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART0_SET(value) (((value) << 27) & 0x08000000)
760 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_LSB 28
762 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_MSB 28
764 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_WIDTH 1
766 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_SET_MSK 0x10000000
768 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_CLR_MSK 0xefffffff
770 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_RESET 0x0
772 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_GET(value) (((value) & 0x10000000) >> 28)
774 #define ALT_NOC_FW_MMAP_PRIV_PRIV_UART1_SET(value) (((value) << 28) & 0x10000000)
787 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_LSB 29
789 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_MSB 29
791 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_WIDTH 1
793 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_SET_MSK 0x20000000
795 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_CLR_MSK 0xdfffffff
797 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_RESET 0x0
799 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
801 #define ALT_NOC_FW_MMAP_PRIV_PRIV_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
814 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_LSB 30
816 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_MSB 30
818 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_WIDTH 1
820 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_SET_MSK 0x40000000
822 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_CLR_MSK 0xbfffffff
824 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_RESET 0x0
826 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
828 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
841 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_LSB 31
843 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_MSB 31
845 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_WIDTH 1
847 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_SET_MSK 0x80000000
849 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_CLR_MSK 0x7fffffff
851 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_RESET 0x0
853 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_GET(value) (((value) & 0x80000000) >> 31)
855 #define ALT_NOC_FW_MMAP_PRIV_PRIV_TCU_SET(value) (((value) << 31) & 0x80000000)
869 struct ALT_NOC_FW_MMAP_PRIV_PRIV_s
871 volatile uint32_t nand_register : 1;
872 volatile uint32_t nand_data : 1;
874 volatile uint32_t usb0_register : 1;
875 volatile uint32_t usb1_register : 1;
876 volatile uint32_t dma_nonsecure : 1;
877 volatile uint32_t dma_secure : 1;
878 volatile uint32_t spi_master0 : 1;
879 volatile uint32_t spi_master1 : 1;
880 volatile uint32_t spi_slave0 : 1;
881 volatile uint32_t spi_slave1 : 1;
882 volatile uint32_t emac0 : 1;
883 volatile uint32_t emac1 : 1;
884 volatile uint32_t emac2 : 1;
886 volatile uint32_t sdmmc : 1;
887 volatile uint32_t gpio0 : 1;
888 volatile uint32_t gpio1 : 1;
890 volatile uint32_t i2c0 : 1;
891 volatile uint32_t i2c1 : 1;
892 volatile uint32_t i2c2 : 1;
893 volatile uint32_t i2c3 : 1;
894 volatile uint32_t i2c4 : 1;
895 volatile uint32_t sp_timer0 : 1;
896 volatile uint32_t sp_timer1 : 1;
897 volatile uint32_t uart0 : 1;
898 volatile uint32_t uart1 : 1;
899 volatile uint32_t lwsoc2fpga : 1;
900 volatile uint32_t soc2fpga : 1;
901 volatile uint32_t tcu : 1;
905 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_s ALT_NOC_FW_MMAP_PRIV_PRIV_t;
909 #define ALT_NOC_FW_MMAP_PRIV_PRIV_RESET 0x00000000
911 #define ALT_NOC_FW_MMAP_PRIV_PRIV_OFST 0x0
965 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_LSB 0
967 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_MSB 0
969 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_WIDTH 1
971 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_SET_MSK 0x00000001
973 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_CLR_MSK 0xfffffffe
975 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_RESET 0x0
977 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
979 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
991 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_LSB 1
993 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_MSB 1
995 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_WIDTH 1
997 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_SET_MSK 0x00000002
999 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_CLR_MSK 0xfffffffd
1001 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_RESET 0x0
1003 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1005 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1017 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_LSB 3
1019 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_MSB 3
1021 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_WIDTH 1
1023 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_SET_MSK 0x00000008
1025 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_CLR_MSK 0xfffffff7
1027 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_RESET 0x0
1029 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
1031 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
1043 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_LSB 4
1045 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_MSB 4
1047 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_WIDTH 1
1049 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_SET_MSK 0x00000010
1051 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_CLR_MSK 0xffffffef
1053 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_RESET 0x0
1055 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
1057 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
1069 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_LSB 5
1071 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_MSB 5
1073 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_WIDTH 1
1075 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_SET_MSK 0x00000020
1077 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_CLR_MSK 0xffffffdf
1079 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_RESET 0x0
1081 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1083 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1095 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_LSB 6
1097 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_MSB 6
1099 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_WIDTH 1
1101 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_SET_MSK 0x00000040
1103 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_CLR_MSK 0xffffffbf
1105 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_RESET 0x0
1107 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1109 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1121 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_LSB 7
1123 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_MSB 7
1125 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_WIDTH 1
1127 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_SET_MSK 0x00000080
1129 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_CLR_MSK 0xffffff7f
1131 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_RESET 0x0
1133 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
1135 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
1147 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_LSB 8
1149 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_MSB 8
1151 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_WIDTH 1
1153 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_SET_MSK 0x00000100
1155 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_CLR_MSK 0xfffffeff
1157 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_RESET 0x0
1159 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
1161 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
1173 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_LSB 9
1175 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_MSB 9
1177 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_WIDTH 1
1179 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_SET_MSK 0x00000200
1181 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_CLR_MSK 0xfffffdff
1183 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_RESET 0x0
1185 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
1187 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
1199 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_LSB 10
1201 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_MSB 10
1203 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_WIDTH 1
1205 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_SET_MSK 0x00000400
1207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_CLR_MSK 0xfffffbff
1209 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_RESET 0x0
1211 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
1213 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
1225 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_LSB 11
1227 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_MSB 11
1229 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_WIDTH 1
1231 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_SET_MSK 0x00000800
1233 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_CLR_MSK 0xfffff7ff
1235 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_RESET 0x0
1237 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
1239 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC0_SET(value) (((value) << 11) & 0x00000800)
1251 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_LSB 12
1253 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_MSB 12
1255 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_WIDTH 1
1257 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_SET_MSK 0x00001000
1259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_CLR_MSK 0xffffefff
1261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_RESET 0x0
1263 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
1265 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC1_SET(value) (((value) << 12) & 0x00001000)
1277 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_LSB 13
1279 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_MSB 13
1281 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_WIDTH 1
1283 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_SET_MSK 0x00002000
1285 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_CLR_MSK 0xffffdfff
1287 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_RESET 0x0
1289 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
1291 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_EMAC2_SET(value) (((value) << 13) & 0x00002000)
1303 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_LSB 16
1305 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_MSB 16
1307 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_WIDTH 1
1309 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_SET_MSK 0x00010000
1311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_CLR_MSK 0xfffeffff
1313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_RESET 0x0
1315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
1317 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SDMMC_SET(value) (((value) << 16) & 0x00010000)
1329 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_LSB 17
1331 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_MSB 17
1333 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_WIDTH 1
1335 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_SET_MSK 0x00020000
1337 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_CLR_MSK 0xfffdffff
1339 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_RESET 0x0
1341 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
1343 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO0_SET(value) (((value) << 17) & 0x00020000)
1355 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_LSB 18
1357 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_MSB 18
1359 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_WIDTH 1
1361 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_SET_MSK 0x00040000
1363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_CLR_MSK 0xfffbffff
1365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_RESET 0x0
1367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
1369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_GPIO1_SET(value) (((value) << 18) & 0x00040000)
1381 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_LSB 20
1383 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_MSB 20
1385 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_WIDTH 1
1387 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_SET_MSK 0x00100000
1389 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_CLR_MSK 0xffefffff
1391 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_RESET 0x0
1393 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_GET(value) (((value) & 0x00100000) >> 20)
1395 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C0_SET(value) (((value) << 20) & 0x00100000)
1407 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_LSB 21
1409 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_MSB 21
1411 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_WIDTH 1
1413 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_SET_MSK 0x00200000
1415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_CLR_MSK 0xffdfffff
1417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_RESET 0x0
1419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_GET(value) (((value) & 0x00200000) >> 21)
1421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C1_SET(value) (((value) << 21) & 0x00200000)
1433 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_LSB 22
1435 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_MSB 22
1437 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_WIDTH 1
1439 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_SET_MSK 0x00400000
1441 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_CLR_MSK 0xffbfffff
1443 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_RESET 0x0
1445 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_GET(value) (((value) & 0x00400000) >> 22)
1447 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C2_SET(value) (((value) << 22) & 0x00400000)
1459 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_LSB 23
1461 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_MSB 23
1463 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_WIDTH 1
1465 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_SET_MSK 0x00800000
1467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_CLR_MSK 0xff7fffff
1469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_RESET 0x0
1471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_GET(value) (((value) & 0x00800000) >> 23)
1473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C3_SET(value) (((value) << 23) & 0x00800000)
1485 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_LSB 24
1487 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_MSB 24
1489 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_WIDTH 1
1491 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_SET_MSK 0x01000000
1493 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_CLR_MSK 0xfeffffff
1495 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_RESET 0x0
1497 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_GET(value) (((value) & 0x01000000) >> 24)
1499 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_I2C4_SET(value) (((value) << 24) & 0x01000000)
1511 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_LSB 25
1513 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_MSB 25
1515 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_WIDTH 1
1517 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_SET_MSK 0x02000000
1519 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_CLR_MSK 0xfdffffff
1521 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_RESET 0x0
1523 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
1525 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
1537 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_LSB 26
1539 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_MSB 26
1541 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_WIDTH 1
1543 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_SET_MSK 0x04000000
1545 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_CLR_MSK 0xfbffffff
1547 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_RESET 0x0
1549 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
1551 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
1563 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_LSB 27
1565 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_MSB 27
1567 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_WIDTH 1
1569 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_SET_MSK 0x08000000
1571 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_CLR_MSK 0xf7ffffff
1573 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_RESET 0x0
1575 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_GET(value) (((value) & 0x08000000) >> 27)
1577 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART0_SET(value) (((value) << 27) & 0x08000000)
1589 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_LSB 28
1591 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_MSB 28
1593 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_WIDTH 1
1595 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_SET_MSK 0x10000000
1597 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_CLR_MSK 0xefffffff
1599 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_RESET 0x0
1601 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_GET(value) (((value) & 0x10000000) >> 28)
1603 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_UART1_SET(value) (((value) << 28) & 0x10000000)
1615 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_LSB 29
1617 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_MSB 29
1619 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_WIDTH 1
1621 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_SET_MSK 0x20000000
1623 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_CLR_MSK 0xdfffffff
1625 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_RESET 0x0
1627 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
1629 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
1641 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_LSB 30
1643 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_MSB 30
1645 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_WIDTH 1
1647 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_SET_MSK 0x40000000
1649 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_CLR_MSK 0xbfffffff
1651 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_RESET 0x0
1653 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
1655 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
1667 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_LSB 31
1669 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_MSB 31
1671 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_WIDTH 1
1673 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_SET_MSK 0x80000000
1675 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_CLR_MSK 0x7fffffff
1677 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_RESET 0x0
1679 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_GET(value) (((value) & 0x80000000) >> 31)
1681 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_TCU_SET(value) (((value) << 31) & 0x80000000)
1683 #ifndef __ASSEMBLY__
1695 struct ALT_NOC_FW_MMAP_PRIV_PRIV_SET_s
1697 volatile uint32_t nand_register : 1;
1698 volatile uint32_t nand_data : 1;
1700 volatile uint32_t usb0_register : 1;
1701 volatile uint32_t usb1_register : 1;
1702 volatile uint32_t dma_nonsecure : 1;
1703 volatile uint32_t dma_secure : 1;
1704 volatile uint32_t spi_master0 : 1;
1705 volatile uint32_t spi_master1 : 1;
1706 volatile uint32_t spi_slave0 : 1;
1707 volatile uint32_t spi_slave1 : 1;
1708 volatile uint32_t emac0 : 1;
1709 volatile uint32_t emac1 : 1;
1710 volatile uint32_t emac2 : 1;
1712 volatile uint32_t sdmmc : 1;
1713 volatile uint32_t gpio0 : 1;
1714 volatile uint32_t gpio1 : 1;
1716 volatile uint32_t i2c0 : 1;
1717 volatile uint32_t i2c1 : 1;
1718 volatile uint32_t i2c2 : 1;
1719 volatile uint32_t i2c3 : 1;
1720 volatile uint32_t i2c4 : 1;
1721 volatile uint32_t sp_timer0 : 1;
1722 volatile uint32_t sp_timer1 : 1;
1723 volatile uint32_t uart0 : 1;
1724 volatile uint32_t uart1 : 1;
1725 volatile uint32_t lwsoc2fpga : 1;
1726 volatile uint32_t soc2fpga : 1;
1727 volatile uint32_t tcu : 1;
1731 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_SET_s ALT_NOC_FW_MMAP_PRIV_PRIV_SET_t;
1735 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_RESET 0x00000000
1737 #define ALT_NOC_FW_MMAP_PRIV_PRIV_SET_OFST 0x4
1791 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_LSB 0
1793 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_MSB 0
1795 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_WIDTH 1
1797 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_SET_MSK 0x00000001
1799 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_CLR_MSK 0xfffffffe
1801 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_RESET 0x0
1803 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_GET(value) (((value) & 0x00000001) >> 0)
1805 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_REGISTER_SET(value) (((value) << 0) & 0x00000001)
1817 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_LSB 1
1819 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_MSB 1
1821 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_WIDTH 1
1823 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_SET_MSK 0x00000002
1825 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_CLR_MSK 0xfffffffd
1827 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_RESET 0x0
1829 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1831 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1843 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_LSB 3
1845 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_MSB 3
1847 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_WIDTH 1
1849 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_SET_MSK 0x00000008
1851 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_CLR_MSK 0xfffffff7
1853 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_RESET 0x0
1855 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_GET(value) (((value) & 0x00000008) >> 3)
1857 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB0_REGISTER_SET(value) (((value) << 3) & 0x00000008)
1869 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_LSB 4
1871 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_MSB 4
1873 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_WIDTH 1
1875 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_SET_MSK 0x00000010
1877 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_CLR_MSK 0xffffffef
1879 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_RESET 0x0
1881 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_GET(value) (((value) & 0x00000010) >> 4)
1883 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_USB1_REGISTER_SET(value) (((value) << 4) & 0x00000010)
1895 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_LSB 5
1897 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_MSB 5
1899 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_WIDTH 1
1901 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_SET_MSK 0x00000020
1903 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_CLR_MSK 0xffffffdf
1905 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_RESET 0x0
1907 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1909 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1921 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_LSB 6
1923 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_MSB 6
1925 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_WIDTH 1
1927 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_SET_MSK 0x00000040
1929 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_CLR_MSK 0xffffffbf
1931 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_RESET 0x0
1933 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1935 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1947 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_LSB 7
1949 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_MSB 7
1951 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_WIDTH 1
1953 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_SET_MSK 0x00000080
1955 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_CLR_MSK 0xffffff7f
1957 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_RESET 0x0
1959 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_GET(value) (((value) & 0x00000080) >> 7)
1961 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER0_SET(value) (((value) << 7) & 0x00000080)
1973 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_LSB 8
1975 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_MSB 8
1977 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_WIDTH 1
1979 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_SET_MSK 0x00000100
1981 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_CLR_MSK 0xfffffeff
1983 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_RESET 0x0
1985 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_GET(value) (((value) & 0x00000100) >> 8)
1987 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_MASTER1_SET(value) (((value) << 8) & 0x00000100)
1999 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_LSB 9
2001 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_MSB 9
2003 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_WIDTH 1
2005 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_SET_MSK 0x00000200
2007 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_CLR_MSK 0xfffffdff
2009 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_RESET 0x0
2011 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_GET(value) (((value) & 0x00000200) >> 9)
2013 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE0_SET(value) (((value) << 9) & 0x00000200)
2025 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_LSB 10
2027 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_MSB 10
2029 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_WIDTH 1
2031 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_SET_MSK 0x00000400
2033 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_CLR_MSK 0xfffffbff
2035 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_RESET 0x0
2037 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_GET(value) (((value) & 0x00000400) >> 10)
2039 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SPI_SLAVE1_SET(value) (((value) << 10) & 0x00000400)
2051 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_LSB 11
2053 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_MSB 11
2055 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_WIDTH 1
2057 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_SET_MSK 0x00000800
2059 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_CLR_MSK 0xfffff7ff
2061 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_RESET 0x0
2063 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
2065 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC0_SET(value) (((value) << 11) & 0x00000800)
2077 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_LSB 12
2079 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_MSB 12
2081 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_WIDTH 1
2083 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_SET_MSK 0x00001000
2085 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_CLR_MSK 0xffffefff
2087 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_RESET 0x0
2089 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
2091 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC1_SET(value) (((value) << 12) & 0x00001000)
2103 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_LSB 13
2105 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_MSB 13
2107 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_WIDTH 1
2109 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_SET_MSK 0x00002000
2111 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_CLR_MSK 0xffffdfff
2113 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_RESET 0x0
2115 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
2117 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_EMAC2_SET(value) (((value) << 13) & 0x00002000)
2129 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_LSB 16
2131 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_MSB 16
2133 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_WIDTH 1
2135 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_SET_MSK 0x00010000
2137 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_CLR_MSK 0xfffeffff
2139 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_RESET 0x0
2141 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
2143 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SDMMC_SET(value) (((value) << 16) & 0x00010000)
2155 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_LSB 17
2157 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_MSB 17
2159 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_WIDTH 1
2161 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_SET_MSK 0x00020000
2163 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_CLR_MSK 0xfffdffff
2165 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_RESET 0x0
2167 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
2169 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO0_SET(value) (((value) << 17) & 0x00020000)
2181 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_LSB 18
2183 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_MSB 18
2185 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_WIDTH 1
2187 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_SET_MSK 0x00040000
2189 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_CLR_MSK 0xfffbffff
2191 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_RESET 0x0
2193 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
2195 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_GPIO1_SET(value) (((value) << 18) & 0x00040000)
2207 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_LSB 20
2209 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_MSB 20
2211 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_WIDTH 1
2213 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_SET_MSK 0x00100000
2215 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_CLR_MSK 0xffefffff
2217 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_RESET 0x0
2219 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_GET(value) (((value) & 0x00100000) >> 20)
2221 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C0_SET(value) (((value) << 20) & 0x00100000)
2233 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_LSB 21
2235 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_MSB 21
2237 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_WIDTH 1
2239 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_SET_MSK 0x00200000
2241 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_CLR_MSK 0xffdfffff
2243 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_RESET 0x0
2245 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_GET(value) (((value) & 0x00200000) >> 21)
2247 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C1_SET(value) (((value) << 21) & 0x00200000)
2259 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_LSB 22
2261 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_MSB 22
2263 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_WIDTH 1
2265 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_SET_MSK 0x00400000
2267 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_CLR_MSK 0xffbfffff
2269 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_RESET 0x0
2271 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_GET(value) (((value) & 0x00400000) >> 22)
2273 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C2_SET(value) (((value) << 22) & 0x00400000)
2285 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_LSB 23
2287 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_MSB 23
2289 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_WIDTH 1
2291 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_SET_MSK 0x00800000
2293 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_CLR_MSK 0xff7fffff
2295 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_RESET 0x0
2297 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_GET(value) (((value) & 0x00800000) >> 23)
2299 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C3_SET(value) (((value) << 23) & 0x00800000)
2311 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_LSB 24
2313 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_MSB 24
2315 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_WIDTH 1
2317 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_SET_MSK 0x01000000
2319 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_CLR_MSK 0xfeffffff
2321 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_RESET 0x0
2323 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_GET(value) (((value) & 0x01000000) >> 24)
2325 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_I2C4_SET(value) (((value) << 24) & 0x01000000)
2337 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_LSB 25
2339 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_MSB 25
2341 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_WIDTH 1
2343 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_SET_MSK 0x02000000
2345 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_CLR_MSK 0xfdffffff
2347 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_RESET 0x0
2349 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_GET(value) (((value) & 0x02000000) >> 25)
2351 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER0_SET(value) (((value) << 25) & 0x02000000)
2363 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_LSB 26
2365 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_MSB 26
2367 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_WIDTH 1
2369 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_SET_MSK 0x04000000
2371 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_CLR_MSK 0xfbffffff
2373 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_RESET 0x0
2375 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_GET(value) (((value) & 0x04000000) >> 26)
2377 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SP_TIMER1_SET(value) (((value) << 26) & 0x04000000)
2389 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_LSB 27
2391 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_MSB 27
2393 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_WIDTH 1
2395 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_SET_MSK 0x08000000
2397 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_CLR_MSK 0xf7ffffff
2399 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_RESET 0x0
2401 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_GET(value) (((value) & 0x08000000) >> 27)
2403 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART0_SET(value) (((value) << 27) & 0x08000000)
2415 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_LSB 28
2417 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_MSB 28
2419 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_WIDTH 1
2421 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_SET_MSK 0x10000000
2423 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_CLR_MSK 0xefffffff
2425 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_RESET 0x0
2427 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_GET(value) (((value) & 0x10000000) >> 28)
2429 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_UART1_SET(value) (((value) << 28) & 0x10000000)
2441 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_LSB 29
2443 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_MSB 29
2445 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_WIDTH 1
2447 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_SET_MSK 0x20000000
2449 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_CLR_MSK 0xdfffffff
2451 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_RESET 0x0
2453 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_GET(value) (((value) & 0x20000000) >> 29)
2455 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_LWSOC2FPGA_SET(value) (((value) << 29) & 0x20000000)
2467 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_LSB 30
2469 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_MSB 30
2471 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_WIDTH 1
2473 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_SET_MSK 0x40000000
2475 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_CLR_MSK 0xbfffffff
2477 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_RESET 0x0
2479 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_GET(value) (((value) & 0x40000000) >> 30)
2481 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_SOC2FPGA_SET(value) (((value) << 30) & 0x40000000)
2493 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_LSB 31
2495 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_MSB 31
2497 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_WIDTH 1
2499 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_SET_MSK 0x80000000
2501 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_CLR_MSK 0x7fffffff
2503 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_RESET 0x0
2505 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_GET(value) (((value) & 0x80000000) >> 31)
2507 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_TCU_SET(value) (((value) << 31) & 0x80000000)
2509 #ifndef __ASSEMBLY__
2521 struct ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_s
2523 volatile uint32_t nand_register : 1;
2524 volatile uint32_t nand_data : 1;
2526 volatile uint32_t usb0_register : 1;
2527 volatile uint32_t usb1_register : 1;
2528 volatile uint32_t dma_nonsecure : 1;
2529 volatile uint32_t dma_secure : 1;
2530 volatile uint32_t spi_master0 : 1;
2531 volatile uint32_t spi_master1 : 1;
2532 volatile uint32_t spi_slave0 : 1;
2533 volatile uint32_t spi_slave1 : 1;
2534 volatile uint32_t emac0 : 1;
2535 volatile uint32_t emac1 : 1;
2536 volatile uint32_t emac2 : 1;
2538 volatile uint32_t sdmmc : 1;
2539 volatile uint32_t gpio0 : 1;
2540 volatile uint32_t gpio1 : 1;
2542 volatile uint32_t i2c0 : 1;
2543 volatile uint32_t i2c1 : 1;
2544 volatile uint32_t i2c2 : 1;
2545 volatile uint32_t i2c3 : 1;
2546 volatile uint32_t i2c4 : 1;
2547 volatile uint32_t sp_timer0 : 1;
2548 volatile uint32_t sp_timer1 : 1;
2549 volatile uint32_t uart0 : 1;
2550 volatile uint32_t uart1 : 1;
2551 volatile uint32_t lwsoc2fpga : 1;
2552 volatile uint32_t soc2fpga : 1;
2553 volatile uint32_t tcu : 1;
2557 typedef struct ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_s ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_t;
2561 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_RESET 0x00000000
2563 #define ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_OFST 0x8
2565 #ifndef __ASSEMBLY__
2577 struct ALT_NOC_FW_MMAP_PRIV_s
2579 volatile ALT_NOC_FW_MMAP_PRIV_PRIV_t priv;
2580 volatile ALT_NOC_FW_MMAP_PRIV_PRIV_SET_t priv_set;
2581 volatile ALT_NOC_FW_MMAP_PRIV_PRIV_CLEAR_t priv_clear;
2582 volatile uint32_t _pad_0xc_0x100[61];
2586 typedef struct ALT_NOC_FW_MMAP_PRIV_s ALT_NOC_FW_MMAP_PRIV_t;
2588 struct ALT_NOC_FW_MMAP_PRIV_raw_s
2590 volatile uint32_t priv;
2591 volatile uint32_t priv_set;
2592 volatile uint32_t priv_clear;
2593 volatile uint32_t _pad_0xc_0x100[61];
2597 typedef struct ALT_NOC_FW_MMAP_PRIV_raw_s ALT_NOC_FW_MMAP_PRIV_raw_t;