35 #ifndef __ALT_SOCAL_NAND_H__
36 #define __ALT_SOCAL_NAND_H__
81 #define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
83 #define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
85 #define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
87 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
89 #define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
91 #define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
93 #define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
95 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
108 #define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
110 #define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
112 #define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
114 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
116 #define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
118 #define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
120 #define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
122 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
135 #define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
137 #define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
139 #define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
141 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
143 #define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
145 #define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
147 #define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
149 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
162 #define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
164 #define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
166 #define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
168 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
170 #define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
172 #define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
174 #define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
176 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
189 struct ALT_NAND_CFG_DEVICE_RST_s
199 typedef volatile struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t;
203 #define ALT_NAND_CFG_DEVICE_RST_RESET 0x00000000
205 #define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
235 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
237 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
239 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
241 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
243 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
245 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
247 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
249 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
262 struct ALT_NAND_CFG_TFR_SPARE_REG_s
269 typedef volatile struct ALT_NAND_CFG_TFR_SPARE_REG_s ALT_NAND_CFG_TFR_SPARE_REG_t;
273 #define ALT_NAND_CFG_TFR_SPARE_REG_RESET 0x00000000
275 #define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
315 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
317 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
319 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
321 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
323 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
325 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
327 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
329 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
342 struct ALT_NAND_CFG_LD_WAIT_CNT_s
349 typedef volatile struct ALT_NAND_CFG_LD_WAIT_CNT_s ALT_NAND_CFG_LD_WAIT_CNT_t;
353 #define ALT_NAND_CFG_LD_WAIT_CNT_RESET 0x000001f4
355 #define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
399 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
401 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
403 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
405 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
407 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
409 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f40
411 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
413 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
426 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
433 typedef volatile struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
437 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_RESET 0x00001f40
439 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
483 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
485 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
487 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
489 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
491 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
493 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f40
495 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
497 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
510 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
517 typedef volatile struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
521 #define ALT_NAND_CFG_ERASE_WAIT_CNT_RESET 0x00001f40
523 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
553 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
555 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
557 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
559 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
561 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
563 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
565 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
567 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
580 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
587 typedef volatile struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
591 #define ALT_NAND_CFG_INT_MON_CYCCNT_RESET 0x000001f4
593 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
624 #define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
626 #define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
628 #define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
630 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
632 #define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
634 #define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
636 #define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
638 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
653 #define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
655 #define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
657 #define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
659 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
661 #define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
663 #define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
665 #define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
667 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
682 #define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
684 #define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
686 #define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
688 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
690 #define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
692 #define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
694 #define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
696 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
711 #define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
713 #define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
715 #define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
717 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
719 #define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
721 #define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
723 #define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
725 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
738 struct ALT_NAND_CFG_RB_PIN_END_s
748 typedef volatile struct ALT_NAND_CFG_RB_PIN_END_s ALT_NAND_CFG_RB_PIN_END_t;
752 #define ALT_NAND_CFG_RB_PIN_END_RESET 0x00000001
754 #define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
782 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
784 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
786 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
788 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
790 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
792 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
794 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
796 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
809 struct ALT_NAND_CFG_MULTIPLANE_OP_s
816 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_OP_s ALT_NAND_CFG_MULTIPLANE_OP_t;
820 #define ALT_NAND_CFG_MULTIPLANE_OP_RESET 0x00000000
822 #define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
858 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
860 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
862 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
864 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
866 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
868 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
870 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
872 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
885 struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s
892 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_RD_EN_s ALT_NAND_CFG_MULTIPLANE_RD_EN_t;
896 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_RESET 0x00000000
898 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
922 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
924 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
926 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
928 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
930 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
932 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
934 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
936 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
949 struct ALT_NAND_CFG_COPYBACK_DIS_s
956 typedef volatile struct ALT_NAND_CFG_COPYBACK_DIS_s ALT_NAND_CFG_COPYBACK_DIS_t;
960 #define ALT_NAND_CFG_COPYBACK_DIS_RESET 0x00000000
962 #define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
986 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
988 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
990 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
992 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
994 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
996 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
998 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1000 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1002 #ifndef __ASSEMBLY__
1013 struct ALT_NAND_CFG_CACHE_WR_EN_s
1020 typedef volatile struct ALT_NAND_CFG_CACHE_WR_EN_s ALT_NAND_CFG_CACHE_WR_EN_t;
1024 #define ALT_NAND_CFG_CACHE_WR_EN_RESET 0x00000000
1026 #define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
1050 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
1052 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
1054 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
1056 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
1058 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
1060 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
1062 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1064 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1066 #ifndef __ASSEMBLY__
1077 struct ALT_NAND_CFG_CACHE_RD_EN_s
1084 typedef volatile struct ALT_NAND_CFG_CACHE_RD_EN_s ALT_NAND_CFG_CACHE_RD_EN_t;
1088 #define ALT_NAND_CFG_CACHE_RD_EN_RESET 0x00000000
1090 #define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1116 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1118 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1120 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1122 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1124 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1126 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1128 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1130 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1155 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1157 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1159 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1161 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1163 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1165 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1167 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1169 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1171 #ifndef __ASSEMBLY__
1182 struct ALT_NAND_CFG_PREFETCH_MOD_s
1184 uint32_t prefetch_en : 1;
1186 uint32_t prefetch_burst_length : 12;
1191 typedef volatile struct ALT_NAND_CFG_PREFETCH_MOD_s ALT_NAND_CFG_PREFETCH_MOD_t;
1195 #define ALT_NAND_CFG_PREFETCH_MOD_RESET 0x00000001
1197 #define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1225 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1227 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1229 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1231 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1233 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1235 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1237 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1239 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1241 #ifndef __ASSEMBLY__
1252 struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
1259 typedef volatile struct ALT_NAND_CFG_CHIP_EN_DONT_CARE_s ALT_NAND_CFG_CHIP_EN_DONT_CARE_t;
1263 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_RESET 0x00000000
1265 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1299 #define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1301 #define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1303 #define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1305 #define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1307 #define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1309 #define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1311 #define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1313 #define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1315 #ifndef __ASSEMBLY__
1326 struct ALT_NAND_CFG_ECC_EN_s
1333 typedef volatile struct ALT_NAND_CFG_ECC_EN_s ALT_NAND_CFG_ECC_EN_t;
1337 #define ALT_NAND_CFG_ECC_EN_RESET 0x00000001
1339 #define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1367 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1369 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1371 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1373 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1375 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1377 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1379 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1381 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1394 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1396 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1398 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1400 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1402 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1404 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1406 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1408 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1421 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1423 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1425 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1427 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1429 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1431 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1433 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1435 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1437 #ifndef __ASSEMBLY__
1448 struct ALT_NAND_CFG_GLOB_INT_EN_s
1452 uint32_t timeout_disable : 1;
1454 uint32_t error_rpt_disable : 1;
1459 typedef volatile struct ALT_NAND_CFG_GLOB_INT_EN_s ALT_NAND_CFG_GLOB_INT_EN_t;
1463 #define ALT_NAND_CFG_GLOB_INT_EN_RESET 0x00000000
1465 #define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1494 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1496 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1498 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1500 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1502 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1504 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1506 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1508 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1522 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1524 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1526 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1528 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1530 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1532 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1534 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1536 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1538 #ifndef __ASSEMBLY__
1549 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1551 uint32_t we_2_re : 6;
1558 typedef volatile struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1562 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_RESET 0x00001432
1564 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1593 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1595 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 6
1597 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 7
1599 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000007f
1601 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffff80
1603 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1605 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000007f) >> 0)
1607 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000007f)
1623 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1625 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1627 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1629 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1631 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1633 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1635 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1637 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1639 #ifndef __ASSEMBLY__
1650 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1652 uint32_t addr_2_data : 7;
1659 typedef volatile struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1663 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_RESET 0x00001432
1665 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1694 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1696 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1698 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1700 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1702 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1704 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1706 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1708 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1710 #ifndef __ASSEMBLY__
1721 struct ALT_NAND_CFG_RE_2_WE_s
1728 typedef volatile struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1732 #define ALT_NAND_CFG_RE_2_WE_RESET 0x00000032
1734 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1762 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1764 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1766 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1768 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1770 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1772 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1774 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1776 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1778 #ifndef __ASSEMBLY__
1789 struct ALT_NAND_CFG_ACC_CLKS_s
1796 typedef volatile struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1800 #define ALT_NAND_CFG_ACC_CLKS_RESET 0x00000000
1802 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1844 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1846 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1848 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1850 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1852 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1854 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1856 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1858 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1860 #ifndef __ASSEMBLY__
1871 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1878 typedef volatile struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1882 #define ALT_NAND_CFG_NUMBER_OF_PLANES_RESET 0x00000000
1884 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1914 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1916 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1918 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1920 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1922 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1924 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1926 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1928 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1930 #ifndef __ASSEMBLY__
1941 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
1943 uint32_t value : 16;
1948 typedef volatile struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
1952 #define ALT_NAND_CFG_PAGES_PER_BLOCK_RESET 0x00000000
1954 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1986 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1988 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1990 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1992 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1994 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1996 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1998 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
2000 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
2002 #ifndef __ASSEMBLY__
2013 struct ALT_NAND_CFG_DEVICE_WIDTH_s
2020 typedef volatile struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
2024 #define ALT_NAND_CFG_DEVICE_WIDTH_RESET 0x00000003
2026 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
2056 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
2058 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
2060 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
2062 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2064 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2066 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
2068 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2070 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2072 #ifndef __ASSEMBLY__
2083 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
2085 uint32_t value : 16;
2090 typedef volatile struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
2094 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_RESET 0x00000000
2096 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
2126 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
2128 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
2130 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
2132 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2134 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2136 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
2138 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2140 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2142 #ifndef __ASSEMBLY__
2153 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
2155 uint32_t value : 16;
2160 typedef volatile struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
2164 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_RESET 0x00000000
2166 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2196 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2198 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2200 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2202 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2204 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2206 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2208 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2210 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2223 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4
2225 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4
2227 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1
2229 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010
2231 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef
2233 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0
2235 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4)
2237 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010)
2239 #ifndef __ASSEMBLY__
2250 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2259 typedef volatile struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2263 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000
2265 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2295 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2297 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2299 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2301 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2303 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2305 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2307 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2309 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2311 #ifndef __ASSEMBLY__
2322 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2329 typedef volatile struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2333 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_RESET 0x00000000
2335 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2376 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2378 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2380 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2382 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2384 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2386 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2388 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2390 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2423 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB 16
2425 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB 31
2427 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH 16
2429 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK 0xffff0000
2431 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK 0x0000ffff
2433 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET 0x0
2435 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value) (((value) & 0xffff0000) >> 16)
2437 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value) (((value) << 16) & 0xffff0000)
2439 #ifndef __ASSEMBLY__
2450 struct ALT_NAND_CFG_ECC_CORRECTION_s
2454 uint32_t erase_threshold : 16;
2458 typedef volatile struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2462 #define ALT_NAND_CFG_ECC_CORRECTION_RESET 0x00000008
2464 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2578 #define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2580 #define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2582 #define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2584 #define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2586 #define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2588 #define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2590 #define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2592 #define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2594 #ifndef __ASSEMBLY__
2605 struct ALT_NAND_CFG_RD_MOD_s
2612 typedef volatile struct ALT_NAND_CFG_RD_MOD_s ALT_NAND_CFG_RD_MOD_t;
2616 #define ALT_NAND_CFG_RD_MOD_RESET 0x00000000
2618 #define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2695 #define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2697 #define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2699 #define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2701 #define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2703 #define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2705 #define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2707 #define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2709 #define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2711 #ifndef __ASSEMBLY__
2722 struct ALT_NAND_CFG_WR_MOD_s
2729 typedef volatile struct ALT_NAND_CFG_WR_MOD_s ALT_NAND_CFG_WR_MOD_t;
2733 #define ALT_NAND_CFG_WR_MOD_RESET 0x00000000
2735 #define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2813 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2815 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2817 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2819 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2821 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2823 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2825 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2827 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2829 #ifndef __ASSEMBLY__
2840 struct ALT_NAND_CFG_COPYBACK_MOD_s
2847 typedef volatile struct ALT_NAND_CFG_COPYBACK_MOD_s ALT_NAND_CFG_COPYBACK_MOD_t;
2851 #define ALT_NAND_CFG_COPYBACK_MOD_RESET 0x00000000
2853 #define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2886 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2888 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2890 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2892 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2894 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2896 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2898 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2900 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2902 #ifndef __ASSEMBLY__
2913 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
2920 typedef volatile struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
2924 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_RESET 0x00000012
2926 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2960 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2962 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2964 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2966 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2968 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2970 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2972 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2974 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2976 #ifndef __ASSEMBLY__
2987 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
2994 typedef volatile struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
2998 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_RESET 0x0000000c
3000 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
3035 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
3037 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
3039 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
3041 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
3043 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
3045 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
3047 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
3049 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
3051 #ifndef __ASSEMBLY__
3062 struct ALT_NAND_CFG_MAX_RD_DELAY_s
3069 typedef volatile struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
3073 #define ALT_NAND_CFG_MAX_RD_DELAY_RESET 0x00000000
3075 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
3116 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
3118 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
3120 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
3122 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
3124 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
3126 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
3128 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3130 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3143 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12
3145 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17
3147 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6
3149 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000
3151 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff
3153 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa
3155 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12)
3157 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000)
3159 #ifndef __ASSEMBLY__
3170 struct ALT_NAND_CFG_CS_SETUP_CNT_s
3179 typedef volatile struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
3183 #define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003
3185 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
3221 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
3223 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
3225 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
3227 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
3229 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
3231 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
3233 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3235 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3237 #ifndef __ASSEMBLY__
3248 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
3255 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
3259 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_RESET 0x00000000
3261 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
3287 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
3289 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
3291 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
3293 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
3295 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
3297 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
3299 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3301 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3303 #ifndef __ASSEMBLY__
3314 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
3316 uint32_t value : 16;
3321 typedef volatile struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
3325 #define ALT_NAND_CFG_SPARE_AREA_MARKER_RESET 0x0000ffff
3327 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
3353 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
3355 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
3357 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
3359 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
3361 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
3363 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
3365 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
3367 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
3369 #ifndef __ASSEMBLY__
3380 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
3387 typedef volatile struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
3391 #define ALT_NAND_CFG_DEVICES_CONNECTED_RESET 0x00000000
3393 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
3434 #define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
3436 #define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 15
3438 #define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 16
3440 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x0000ffff
3442 #define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffff0000
3444 #define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
3446 #define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3448 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3450 #ifndef __ASSEMBLY__
3461 struct ALT_NAND_CFG_DIE_MSK_s
3463 uint32_t value : 16;
3468 typedef volatile struct ALT_NAND_CFG_DIE_MSK_s ALT_NAND_CFG_DIE_MSK_t;
3472 #define ALT_NAND_CFG_DIE_MSK_RESET 0x00000000
3474 #define ALT_NAND_CFG_DIE_MSK_OFST 0x260
3506 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3508 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3510 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3512 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3514 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3516 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3518 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3520 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3522 #ifndef __ASSEMBLY__
3533 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3535 uint32_t value : 16;
3540 typedef volatile struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3544 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_RESET 0x00000001
3546 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3579 #define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3581 #define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3583 #define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3585 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3587 #define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3589 #define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3591 #define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3593 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3595 #ifndef __ASSEMBLY__
3606 struct ALT_NAND_CFG_WR_PROTECT_s
3613 typedef volatile struct ALT_NAND_CFG_WR_PROTECT_s ALT_NAND_CFG_WR_PROTECT_t;
3617 #define ALT_NAND_CFG_WR_PROTECT_RESET 0x00000001
3619 #define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3650 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3652 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3654 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3656 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3658 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3660 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3662 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3664 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3666 #ifndef __ASSEMBLY__
3677 struct ALT_NAND_CFG_RE_2_RE_s
3684 typedef volatile struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3688 #define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032
3690 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3721 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3723 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3725 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3727 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3729 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3731 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3733 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3735 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3737 #ifndef __ASSEMBLY__
3748 struct ALT_NAND_CFG_POR_RST_COUNT_s
3750 uint32_t value : 16;
3755 typedef volatile struct ALT_NAND_CFG_POR_RST_COUNT_s ALT_NAND_CFG_POR_RST_COUNT_t;
3759 #define ALT_NAND_CFG_POR_RST_COUNT_RESET 0x0000013b
3761 #define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3793 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3795 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3797 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3799 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3801 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3803 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3805 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3807 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3809 #ifndef __ASSEMBLY__
3820 struct ALT_NAND_CFG_WD_RST_COUNT_s
3822 uint32_t value : 16;
3827 typedef volatile struct ALT_NAND_CFG_WD_RST_COUNT_s ALT_NAND_CFG_WD_RST_COUNT_t;
3831 #define ALT_NAND_CFG_WD_RST_COUNT_RESET 0x00005b9a
3833 #define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3835 #ifndef __ASSEMBLY__
3846 struct ALT_NAND_CFG_s
3848 ALT_NAND_CFG_DEVICE_RST_t device_reset;
3849 volatile uint32_t _pad_0x4_0xf[3];
3850 ALT_NAND_CFG_TFR_SPARE_REG_t transfer_spare_reg;
3851 volatile uint32_t _pad_0x14_0x1f[3];
3852 ALT_NAND_CFG_LD_WAIT_CNT_t load_wait_cnt;
3853 volatile uint32_t _pad_0x24_0x2f[3];
3854 ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt;
3855 volatile uint32_t _pad_0x34_0x3f[3];
3856 ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt;
3857 volatile uint32_t _pad_0x44_0x4f[3];
3858 ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt;
3859 volatile uint32_t _pad_0x54_0x5f[3];
3860 ALT_NAND_CFG_RB_PIN_END_t rb_pin_enabled;
3861 volatile uint32_t _pad_0x64_0x6f[3];
3862 ALT_NAND_CFG_MULTIPLANE_OP_t multiplane_operation;
3863 volatile uint32_t _pad_0x74_0x7f[3];
3864 ALT_NAND_CFG_MULTIPLANE_RD_EN_t multiplane_read_enable;
3865 volatile uint32_t _pad_0x84_0x8f[3];
3866 ALT_NAND_CFG_COPYBACK_DIS_t copyback_disable;
3867 volatile uint32_t _pad_0x94_0x9f[3];
3868 ALT_NAND_CFG_CACHE_WR_EN_t cache_write_enable;
3869 volatile uint32_t _pad_0xa4_0xaf[3];
3870 ALT_NAND_CFG_CACHE_RD_EN_t cache_read_enable;
3871 volatile uint32_t _pad_0xb4_0xbf[3];
3872 ALT_NAND_CFG_PREFETCH_MOD_t prefetch_mode;
3873 volatile uint32_t _pad_0xc4_0xcf[3];
3874 ALT_NAND_CFG_CHIP_EN_DONT_CARE_t chip_enable_dont_care;
3875 volatile uint32_t _pad_0xd4_0xdf[3];
3876 ALT_NAND_CFG_ECC_EN_t ecc_enable;
3877 volatile uint32_t _pad_0xe4_0xef[3];
3878 ALT_NAND_CFG_GLOB_INT_EN_t global_int_enable;
3879 volatile uint32_t _pad_0xf4_0xff[3];
3880 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re;
3881 volatile uint32_t _pad_0x104_0x10f[3];
3882 ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data;
3883 volatile uint32_t _pad_0x114_0x11f[3];
3884 ALT_NAND_CFG_RE_2_WE_t re_2_we;
3885 volatile uint32_t _pad_0x124_0x12f[3];
3886 ALT_NAND_CFG_ACC_CLKS_t acc_clks;
3887 volatile uint32_t _pad_0x134_0x13f[3];
3888 ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes;
3889 volatile uint32_t _pad_0x144_0x14f[3];
3890 ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block;
3891 volatile uint32_t _pad_0x154_0x15f[3];
3892 ALT_NAND_CFG_DEVICE_WIDTH_t device_width;
3893 volatile uint32_t _pad_0x164_0x16f[3];
3894 ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size;
3895 volatile uint32_t _pad_0x174_0x17f[3];
3896 ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size;
3897 volatile uint32_t _pad_0x184_0x18f[3];
3898 ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles;
3899 volatile uint32_t _pad_0x194_0x19f[3];
3900 ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict;
3901 volatile uint32_t _pad_0x1a4_0x1af[3];
3902 ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction;
3903 volatile uint32_t _pad_0x1b4_0x1bf[3];
3904 ALT_NAND_CFG_RD_MOD_t read_mode;
3905 volatile uint32_t _pad_0x1c4_0x1cf[3];
3906 ALT_NAND_CFG_WR_MOD_t write_mode;
3907 volatile uint32_t _pad_0x1d4_0x1df[3];
3908 ALT_NAND_CFG_COPYBACK_MOD_t copyback_mode;
3909 volatile uint32_t _pad_0x1e4_0x1ef[3];
3910 ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt;
3911 volatile uint32_t _pad_0x1f4_0x1ff[3];
3912 ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt;
3913 volatile uint32_t _pad_0x204_0x20f[3];
3914 ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay;
3915 volatile uint32_t _pad_0x214_0x21f[3];
3916 ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt;
3917 volatile uint32_t _pad_0x224_0x22f[3];
3918 ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes;
3919 volatile uint32_t _pad_0x234_0x23f[3];
3920 ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker;
3921 volatile uint32_t _pad_0x244_0x24f[3];
3922 ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected;
3923 volatile uint32_t _pad_0x254_0x25f[3];
3924 ALT_NAND_CFG_DIE_MSK_t die_mask;
3925 volatile uint32_t _pad_0x264_0x26f[3];
3926 ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane;
3927 volatile uint32_t _pad_0x274_0x27f[3];
3928 ALT_NAND_CFG_WR_PROTECT_t write_protect;
3929 volatile uint32_t _pad_0x284_0x28f[3];
3930 ALT_NAND_CFG_RE_2_RE_t re_2_re;
3931 volatile uint32_t _pad_0x294_0x29f[3];
3932 ALT_NAND_CFG_POR_RST_COUNT_t por_reset_count;
3933 volatile uint32_t _pad_0x2a4_0x2af[3];
3934 ALT_NAND_CFG_WD_RST_COUNT_t watchdog_reset_count;
3938 typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
3940 struct ALT_NAND_CFG_raw_s
3942 volatile uint32_t device_reset;
3943 uint32_t _pad_0x4_0xf[3];
3944 volatile uint32_t transfer_spare_reg;
3945 uint32_t _pad_0x14_0x1f[3];
3946 volatile uint32_t load_wait_cnt;
3947 uint32_t _pad_0x24_0x2f[3];
3948 volatile uint32_t program_wait_cnt;
3949 uint32_t _pad_0x34_0x3f[3];
3950 volatile uint32_t erase_wait_cnt;
3951 uint32_t _pad_0x44_0x4f[3];
3952 volatile uint32_t int_mon_cyccnt;
3953 uint32_t _pad_0x54_0x5f[3];
3954 volatile uint32_t rb_pin_enabled;
3955 uint32_t _pad_0x64_0x6f[3];
3956 volatile uint32_t multiplane_operation;
3957 uint32_t _pad_0x74_0x7f[3];
3958 volatile uint32_t multiplane_read_enable;
3959 uint32_t _pad_0x84_0x8f[3];
3960 volatile uint32_t copyback_disable;
3961 uint32_t _pad_0x94_0x9f[3];
3962 volatile uint32_t cache_write_enable;
3963 uint32_t _pad_0xa4_0xaf[3];
3964 volatile uint32_t cache_read_enable;
3965 uint32_t _pad_0xb4_0xbf[3];
3966 volatile uint32_t prefetch_mode;
3967 uint32_t _pad_0xc4_0xcf[3];
3968 volatile uint32_t chip_enable_dont_care;
3969 uint32_t _pad_0xd4_0xdf[3];
3970 volatile uint32_t ecc_enable;
3971 uint32_t _pad_0xe4_0xef[3];
3972 volatile uint32_t global_int_enable;
3973 uint32_t _pad_0xf4_0xff[3];
3974 volatile uint32_t twhr2_and_we_2_re;
3975 uint32_t _pad_0x104_0x10f[3];
3976 volatile uint32_t tcwaw_and_addr_2_data;
3977 uint32_t _pad_0x114_0x11f[3];
3978 volatile uint32_t re_2_we;
3979 uint32_t _pad_0x124_0x12f[3];
3980 volatile uint32_t acc_clks;
3981 uint32_t _pad_0x134_0x13f[3];
3982 volatile uint32_t number_of_planes;
3983 uint32_t _pad_0x144_0x14f[3];
3984 volatile uint32_t pages_per_block;
3985 uint32_t _pad_0x154_0x15f[3];
3986 volatile uint32_t device_width;
3987 uint32_t _pad_0x164_0x16f[3];
3988 volatile uint32_t device_main_area_size;
3989 uint32_t _pad_0x174_0x17f[3];
3990 volatile uint32_t device_spare_area_size;
3991 uint32_t _pad_0x184_0x18f[3];
3992 volatile uint32_t two_row_addr_cycles;
3993 uint32_t _pad_0x194_0x19f[3];
3994 volatile uint32_t multiplane_addr_restrict;
3995 uint32_t _pad_0x1a4_0x1af[3];
3996 volatile uint32_t ecc_correction;
3997 uint32_t _pad_0x1b4_0x1bf[3];
3998 volatile uint32_t read_mode;
3999 uint32_t _pad_0x1c4_0x1cf[3];
4000 volatile uint32_t write_mode;
4001 uint32_t _pad_0x1d4_0x1df[3];
4002 volatile uint32_t copyback_mode;
4003 uint32_t _pad_0x1e4_0x1ef[3];
4004 volatile uint32_t rdwr_en_lo_cnt;
4005 uint32_t _pad_0x1f4_0x1ff[3];
4006 volatile uint32_t rdwr_en_hi_cnt;
4007 uint32_t _pad_0x204_0x20f[3];
4008 volatile uint32_t max_rd_delay;
4009 uint32_t _pad_0x214_0x21f[3];
4010 volatile uint32_t cs_setup_cnt;
4011 uint32_t _pad_0x224_0x22f[3];
4012 volatile uint32_t spare_area_skip_bytes;
4013 uint32_t _pad_0x234_0x23f[3];
4014 volatile uint32_t spare_area_marker;
4015 uint32_t _pad_0x244_0x24f[3];
4016 volatile uint32_t devices_connected;
4017 uint32_t _pad_0x254_0x25f[3];
4018 volatile uint32_t die_mask;
4019 uint32_t _pad_0x264_0x26f[3];
4020 volatile uint32_t first_block_of_next_plane;
4021 uint32_t _pad_0x274_0x27f[3];
4022 volatile uint32_t write_protect;
4023 uint32_t _pad_0x284_0x28f[3];
4024 volatile uint32_t re_2_re;
4025 uint32_t _pad_0x294_0x29f[3];
4026 volatile uint32_t por_reset_count;
4027 uint32_t _pad_0x2a4_0x2af[3];
4028 volatile uint32_t watchdog_reset_count;
4032 typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
4060 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
4062 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
4064 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
4066 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
4068 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
4070 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
4072 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4074 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4076 #ifndef __ASSEMBLY__
4087 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
4094 typedef volatile struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
4098 #define ALT_NAND_PARAM_MANUFACTURER_ID_RESET 0x00000000
4100 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
4122 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
4124 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
4126 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
4128 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
4130 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
4132 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
4134 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4136 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4138 #ifndef __ASSEMBLY__
4149 struct ALT_NAND_PARAM_DEVICE_ID_s
4151 const uint32_t value : 8;
4156 typedef volatile struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
4160 #define ALT_NAND_PARAM_DEVICE_ID_RESET 0x00000000
4162 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
4186 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
4188 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
4190 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
4192 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
4194 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
4196 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
4198 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4200 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4202 #ifndef __ASSEMBLY__
4213 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
4215 const uint32_t value : 8;
4220 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
4224 #define ALT_NAND_PARAM_DEVICE_PARAM_0_RESET 0x00000000
4226 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
4250 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
4252 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
4254 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
4256 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
4258 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
4260 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
4262 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4264 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4266 #ifndef __ASSEMBLY__
4277 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
4279 const uint32_t value : 8;
4284 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
4288 #define ALT_NAND_PARAM_DEVICE_PARAM_1_RESET 0x00000000
4290 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
4312 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
4314 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
4316 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
4318 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
4320 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
4322 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
4324 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4326 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4328 #ifndef __ASSEMBLY__
4339 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
4341 const uint32_t value : 8;
4346 typedef volatile struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
4350 #define ALT_NAND_PARAM_DEVICE_PARAM_2_RESET 0x00000000
4352 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
4380 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
4382 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
4384 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
4386 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
4388 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
4390 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
4392 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4394 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4396 #ifndef __ASSEMBLY__
4407 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
4409 const uint32_t value : 16;
4414 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
4418 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_RESET 0x00000000
4420 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
4448 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
4450 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
4452 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
4454 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
4456 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
4458 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
4460 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4462 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4464 #ifndef __ASSEMBLY__
4475 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
4477 const uint32_t value : 16;
4482 typedef volatile struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
4486 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_RESET 0x00000000
4488 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
4513 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
4515 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 7
4517 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 8
4519 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x000000ff
4521 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffffff00
4523 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
4525 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4527 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4538 #define ALT_NAND_PARAM_REVISION_MINOR_LSB 8
4540 #define ALT_NAND_PARAM_REVISION_MINOR_MSB 15
4542 #define ALT_NAND_PARAM_REVISION_MINOR_WIDTH 8
4544 #define ALT_NAND_PARAM_REVISION_MINOR_SET_MSK 0x0000ff00
4546 #define ALT_NAND_PARAM_REVISION_MINOR_CLR_MSK 0xffff00ff
4548 #define ALT_NAND_PARAM_REVISION_MINOR_RESET 0x1
4550 #define ALT_NAND_PARAM_REVISION_MINOR_GET(value) (((value) & 0x0000ff00) >> 8)
4552 #define ALT_NAND_PARAM_REVISION_MINOR_SET(value) (((value) << 8) & 0x0000ff00)
4554 #ifndef __ASSEMBLY__
4565 struct ALT_NAND_PARAM_REVISION_s
4567 const uint32_t value : 8;
4568 const uint32_t minor : 8;
4573 typedef volatile struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
4577 #define ALT_NAND_PARAM_REVISION_RESET 0x00000105
4579 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4631 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4633 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4635 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4637 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4639 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4641 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4643 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4645 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4647 #ifndef __ASSEMBLY__
4658 struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
4660 const uint32_t value : 16;
4665 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_FEATURES_s ALT_NAND_PARAM_ONFI_DEV_FEATURES_t;
4669 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_RESET 0x00000000
4671 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4721 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4723 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4725 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4727 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4729 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4731 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4733 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4735 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4737 #ifndef __ASSEMBLY__
4748 struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
4750 const uint32_t value : 16;
4755 typedef volatile struct ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t;
4759 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_RESET 0x00000000
4761 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4797 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4799 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4801 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4803 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4805 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4807 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4809 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4811 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4813 #ifndef __ASSEMBLY__
4824 struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s
4826 const uint32_t value : 6;
4831 typedef volatile struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s ALT_NAND_PARAM_ONFI_TIMING_MOD_t;
4835 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_RESET 0x00000000
4837 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4873 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4875 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4877 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4879 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4881 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4883 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4885 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4887 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4889 #ifndef __ASSEMBLY__
4900 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
4902 const uint32_t value : 6;
4907 typedef volatile struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t;
4911 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_RESET 0x00000000
4913 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4946 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4948 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4950 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4952 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4954 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4956 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4958 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4960 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4975 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4977 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4979 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4981 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4983 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4985 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4987 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4989 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
5008 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_LSB 12
5010 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_MSB 12
5012 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_WIDTH 1
5014 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET_MSK 0x00001000
5016 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_CLR_MSK 0xffffefff
5018 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_RESET 0x0
5020 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_GET(value) (((value) & 0x00001000) >> 12)
5022 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET(value) (((value) << 12) & 0x00001000)
5038 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_LSB 16
5040 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_MSB 16
5042 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_WIDTH 1
5044 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET_MSK 0x00010000
5046 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_CLR_MSK 0xfffeffff
5048 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_RESET 0x0
5050 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_GET(value) (((value) & 0x00010000) >> 16)
5052 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET(value) (((value) << 16) & 0x00010000)
5070 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_LSB 20
5072 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_MSB 20
5074 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_WIDTH 1
5076 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET_MSK 0x00100000
5078 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_CLR_MSK 0xffefffff
5080 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_RESET 0x0
5082 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_GET(value) (((value) & 0x00100000) >> 20)
5084 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET(value) (((value) << 20) & 0x00100000)
5086 #ifndef __ASSEMBLY__
5097 struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
5099 const uint32_t no_of_luns : 8;
5100 uint32_t onfi_device : 1;
5102 uint32_t prog_page_reg_clear_enhancement : 1;
5104 uint32_t onfi_jedec_multiplane_erase_seq : 1;
5106 uint32_t ce_reduction_volume_addr_and_change : 1;
5111 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t;
5115 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_RESET 0x00000000
5117 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
5145 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
5147 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
5149 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
5151 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
5153 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
5155 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
5157 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5159 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5161 #ifndef __ASSEMBLY__
5172 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
5174 const uint32_t value : 16;
5179 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t;
5183 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_RESET 0x00000000
5185 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
5213 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
5215 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
5217 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
5219 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
5221 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
5223 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
5225 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5227 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5229 #ifndef __ASSEMBLY__
5240 struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
5242 const uint32_t value : 16;
5247 typedef volatile struct ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t;
5251 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_RESET 0x00000000
5253 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
5296 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
5298 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
5300 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
5302 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
5304 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
5306 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x2
5308 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
5310 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
5321 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
5323 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
5325 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
5327 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
5329 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
5331 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
5333 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
5335 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
5346 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
5348 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
5350 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
5352 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
5354 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
5356 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x1
5358 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
5360 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
5371 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
5373 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
5375 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
5377 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
5379 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
5381 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
5383 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
5385 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
5396 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
5398 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
5400 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
5402 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
5404 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
5406 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
5408 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
5410 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
5421 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
5423 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
5425 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
5427 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
5429 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
5431 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
5433 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
5435 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
5446 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
5448 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
5450 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
5452 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
5454 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
5456 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
5458 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
5460 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
5471 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
5473 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
5475 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
5477 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
5479 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
5481 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
5483 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
5485 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
5496 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
5498 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
5500 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
5502 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
5504 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
5506 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
5508 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
5510 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
5512 #ifndef __ASSEMBLY__
5523 struct ALT_NAND_PARAM_FEATURES_s
5525 const uint32_t n_banks : 2;
5527 const uint32_t dma : 1;
5528 const uint32_t cmd_dma : 1;
5529 const uint32_t partition : 1;
5530 const uint32_t xdma_sideband : 1;
5531 const uint32_t gpreg : 1;
5532 const uint32_t index_addr : 1;
5533 const uint32_t dfi_intf : 1;
5534 const uint32_t lba : 1;
5539 typedef volatile struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
5543 #define ALT_NAND_PARAM_FEATURES_RESET 0x000008c2
5545 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
5547 #ifndef __ASSEMBLY__
5558 struct ALT_NAND_PARAM_s
5560 ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id;
5561 volatile uint32_t _pad_0x4_0xf[3];
5562 ALT_NAND_PARAM_DEVICE_ID_t device_id;
5563 volatile uint32_t _pad_0x14_0x1f[3];
5564 ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0;
5565 volatile uint32_t _pad_0x24_0x2f[3];
5566 ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1;
5567 volatile uint32_t _pad_0x34_0x3f[3];
5568 ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2;
5569 volatile uint32_t _pad_0x44_0x4f[3];
5570 ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size;
5571 volatile uint32_t _pad_0x54_0x5f[3];
5572 ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size;
5573 volatile uint32_t _pad_0x64_0x6f[3];
5574 ALT_NAND_PARAM_REVISION_t revision;
5575 volatile uint32_t _pad_0x74_0x7f[3];
5576 ALT_NAND_PARAM_ONFI_DEV_FEATURES_t onfi_device_features;
5577 volatile uint32_t _pad_0x84_0x8f[3];
5578 ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t onfi_optional_commands;
5579 volatile uint32_t _pad_0x94_0x9f[3];
5580 ALT_NAND_PARAM_ONFI_TIMING_MOD_t onfi_timing_mode;
5581 volatile uint32_t _pad_0xa4_0xaf[3];
5582 ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t onfi_pgm_cache_timing_mode;
5583 volatile uint32_t _pad_0xb4_0xbf[3];
5584 ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t onfi_device_no_of_luns;
5585 volatile uint32_t _pad_0xc4_0xcf[3];
5586 ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l;
5587 volatile uint32_t _pad_0xd4_0xdf[3];
5588 ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u;
5589 volatile uint32_t _pad_0xe4_0xef[3];
5590 ALT_NAND_PARAM_FEATURES_t features;
5594 typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
5596 struct ALT_NAND_PARAM_raw_s
5598 volatile uint32_t manufacturer_id;
5599 uint32_t _pad_0x4_0xf[3];
5600 volatile uint32_t device_id;
5601 uint32_t _pad_0x14_0x1f[3];
5602 volatile uint32_t device_param_0;
5603 uint32_t _pad_0x24_0x2f[3];
5604 volatile uint32_t device_param_1;
5605 uint32_t _pad_0x34_0x3f[3];
5606 volatile uint32_t device_param_2;
5607 uint32_t _pad_0x44_0x4f[3];
5608 volatile uint32_t logical_page_data_size;
5609 uint32_t _pad_0x54_0x5f[3];
5610 volatile uint32_t logical_page_spare_size;
5611 uint32_t _pad_0x64_0x6f[3];
5612 volatile uint32_t revision;
5613 uint32_t _pad_0x74_0x7f[3];
5614 volatile uint32_t onfi_device_features;
5615 uint32_t _pad_0x84_0x8f[3];
5616 volatile uint32_t onfi_optional_commands;
5617 uint32_t _pad_0x94_0x9f[3];
5618 volatile uint32_t onfi_timing_mode;
5619 uint32_t _pad_0xa4_0xaf[3];
5620 volatile uint32_t onfi_pgm_cache_timing_mode;
5621 uint32_t _pad_0xb4_0xbf[3];
5622 volatile uint32_t onfi_device_no_of_luns;
5623 uint32_t _pad_0xc4_0xcf[3];
5624 volatile uint32_t onfi_device_no_of_blocks_per_lun_l;
5625 uint32_t _pad_0xd4_0xdf[3];
5626 volatile uint32_t onfi_device_no_of_blocks_per_lun_u;
5627 uint32_t _pad_0xe4_0xef[3];
5628 volatile uint32_t features;
5632 typedef volatile struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
5668 #define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
5670 #define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
5672 #define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
5674 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
5676 #define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
5678 #define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
5680 #define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
5682 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
5694 #define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
5696 #define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
5698 #define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
5700 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
5702 #define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
5704 #define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
5706 #define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
5708 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
5720 #define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
5722 #define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
5724 #define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
5726 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
5728 #define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
5730 #define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
5732 #define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
5734 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
5746 #define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
5748 #define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
5750 #define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
5752 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
5754 #define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
5756 #define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
5758 #define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
5760 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
5762 #ifndef __ASSEMBLY__
5773 struct ALT_NAND_STAT_TFR_MOD_s
5775 const uint32_t value0 : 2;
5776 const uint32_t value1 : 2;
5777 const uint32_t value2 : 2;
5778 const uint32_t value3 : 2;
5783 typedef volatile struct ALT_NAND_STAT_TFR_MOD_s ALT_NAND_STAT_TFR_MOD_t;
5787 #define ALT_NAND_STAT_TFR_MOD_RESET 0x00000000
5789 #define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5829 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5831 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5833 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5835 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5837 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5839 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5841 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5843 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5854 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5856 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5858 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5860 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5862 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5864 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5866 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5868 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5882 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5884 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5886 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5888 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5890 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5892 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5894 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5896 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5911 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5913 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5915 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5917 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5919 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5921 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5923 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5925 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5940 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5942 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5944 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5946 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5948 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5950 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5952 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5954 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5965 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5967 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5969 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5971 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5973 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5975 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5977 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5979 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5990 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5992 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5994 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5996 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5998 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6000 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
6002 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6004 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6015 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
6017 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
6019 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
6021 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
6023 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
6025 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
6027 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6029 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6041 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
6043 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
6045 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6047 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6049 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6051 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6053 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6055 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6069 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
6071 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
6073 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
6075 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
6077 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
6079 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
6081 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6083 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6097 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
6099 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
6101 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
6103 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
6105 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6107 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
6109 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6111 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6122 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
6124 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
6126 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
6128 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
6130 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
6132 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
6134 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6136 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6147 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
6149 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
6151 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
6153 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
6155 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
6157 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
6159 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6161 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6178 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
6180 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
6182 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
6184 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
6186 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6188 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
6190 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6192 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6203 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
6205 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
6207 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
6209 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
6211 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6213 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
6215 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6217 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6250 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_LSB 16
6252 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_MSB 16
6254 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_WIDTH 1
6256 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET_MSK 0x00010000
6258 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_CLR_MSK 0xfffeffff
6260 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_RESET 0x0
6262 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6264 #define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6266 #ifndef __ASSEMBLY__
6277 struct ALT_NAND_STAT_INTR_STAT0_s
6279 uint32_t ecc_uncor_err : 1;
6281 uint32_t dma_cmd_comp : 1;
6282 uint32_t time_out : 1;
6283 uint32_t program_fail : 1;
6284 uint32_t erase_fail : 1;
6285 uint32_t load_comp : 1;
6286 uint32_t program_comp : 1;
6287 uint32_t erase_comp : 1;
6288 uint32_t pipe_cpybck_cmd_comp : 1;
6289 uint32_t locked_blk : 1;
6290 uint32_t unsup_cmd : 1;
6291 uint32_t int_act : 1;
6292 uint32_t rst_comp : 1;
6293 uint32_t pipe_cmd_err : 1;
6294 uint32_t page_xfer_inc : 1;
6295 uint32_t erased_page : 1;
6300 typedef volatile struct ALT_NAND_STAT_INTR_STAT0_s ALT_NAND_STAT_INTR_STAT0_t;
6304 #define ALT_NAND_STAT_INTR_STAT0_RESET 0x00000000
6306 #define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
6349 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
6351 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
6353 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
6355 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6357 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6359 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
6361 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6363 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6374 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
6376 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
6378 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
6380 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
6382 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6384 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
6386 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6388 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6402 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
6404 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
6406 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
6408 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
6410 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
6412 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
6414 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6416 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6431 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
6433 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
6435 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
6437 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
6439 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6441 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
6443 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6445 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6460 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
6462 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
6464 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
6466 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
6468 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
6470 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
6472 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6474 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6485 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
6487 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
6489 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
6491 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
6493 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
6495 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
6497 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6499 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6510 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
6512 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
6514 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
6516 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
6518 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6520 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
6522 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6524 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6535 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
6537 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
6539 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
6541 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
6543 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
6545 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
6547 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6549 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6561 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
6563 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
6565 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6567 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6569 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6571 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6573 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6575 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6589 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
6591 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
6593 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
6595 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
6597 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
6599 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
6601 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6603 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6617 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
6619 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
6621 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
6623 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
6625 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6627 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
6629 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6631 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6642 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
6644 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
6646 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
6648 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
6650 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
6652 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
6654 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6656 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6667 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
6669 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
6671 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
6673 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
6675 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
6677 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
6679 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6681 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6698 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
6700 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
6702 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
6704 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
6706 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6708 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
6710 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6712 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6723 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
6725 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
6727 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
6729 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
6731 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6733 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
6735 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6737 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6770 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_LSB 16
6772 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_MSB 16
6774 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_WIDTH 1
6776 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET_MSK 0x00010000
6778 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_CLR_MSK 0xfffeffff
6780 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_RESET 0x0
6782 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6784 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6786 #ifndef __ASSEMBLY__
6797 struct ALT_NAND_STAT_INTR_EN0_s
6799 uint32_t ecc_uncor_err : 1;
6801 uint32_t dma_cmd_comp : 1;
6802 uint32_t time_out : 1;
6803 uint32_t program_fail : 1;
6804 uint32_t erase_fail : 1;
6805 uint32_t load_comp : 1;
6806 uint32_t program_comp : 1;
6807 uint32_t erase_comp : 1;
6808 uint32_t pipe_cpybck_cmd_comp : 1;
6809 uint32_t locked_blk : 1;
6810 uint32_t unsup_cmd : 1;
6811 uint32_t int_act : 1;
6812 uint32_t rst_comp : 1;
6813 uint32_t pipe_cmd_err : 1;
6814 uint32_t page_xfer_inc : 1;
6815 uint32_t erased_page : 1;
6820 typedef volatile struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
6824 #define ALT_NAND_STAT_INTR_EN0_RESET 0x00002000
6826 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
6852 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
6854 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
6856 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
6858 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
6860 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
6862 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
6864 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
6866 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
6868 #ifndef __ASSEMBLY__
6879 struct ALT_NAND_STAT_PAGE_CNT0_s
6881 const uint32_t value : 8;
6886 typedef volatile struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
6890 #define ALT_NAND_STAT_PAGE_CNT0_RESET 0x00000000
6892 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
6918 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6920 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6922 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6924 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6926 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6928 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6930 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6932 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6934 #ifndef __ASSEMBLY__
6945 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
6947 const uint32_t value : 16;
6952 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
6956 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_RESET 0x00000000
6958 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6984 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6986 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6988 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6990 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6992 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6994 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6996 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6998 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7000 #ifndef __ASSEMBLY__
7011 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
7013 const uint32_t value : 16;
7018 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
7022 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_RESET 0x00000000
7024 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
7064 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
7066 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
7068 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
7070 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7072 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7074 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
7076 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7078 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7089 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
7091 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
7093 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
7095 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
7097 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7099 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
7101 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7103 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7117 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
7119 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
7121 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
7123 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
7125 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
7127 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
7129 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7131 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7146 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
7148 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
7150 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
7152 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
7154 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7156 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
7158 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7160 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7175 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
7177 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
7179 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
7181 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
7183 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
7185 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
7187 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7189 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7200 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
7202 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
7204 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
7206 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
7208 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
7210 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
7212 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7214 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7225 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
7227 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
7229 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
7231 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
7233 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7235 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
7237 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7239 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7250 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
7252 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
7254 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
7256 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
7258 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
7260 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
7262 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7264 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7276 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
7278 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
7280 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7282 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7284 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7286 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7288 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7290 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7304 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
7306 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
7308 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
7310 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
7312 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
7314 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
7316 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7318 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7332 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
7334 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
7336 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
7338 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
7340 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7342 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
7344 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7346 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7357 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
7359 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
7361 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
7363 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
7365 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
7367 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
7369 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7371 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7383 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
7385 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
7387 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
7389 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
7391 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
7393 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
7395 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7397 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7414 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
7416 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
7418 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
7420 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
7422 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7424 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
7426 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7428 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7439 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
7441 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
7443 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
7445 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
7447 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7449 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
7451 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7453 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7486 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_LSB 16
7488 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_MSB 16
7490 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_WIDTH 1
7492 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET_MSK 0x00010000
7494 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_CLR_MSK 0xfffeffff
7496 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_RESET 0x0
7498 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
7500 #define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
7502 #ifndef __ASSEMBLY__
7513 struct ALT_NAND_STAT_INTR_STAT1_s
7515 uint32_t ecc_uncor_err : 1;
7517 uint32_t dma_cmd_comp : 1;
7518 uint32_t time_out : 1;
7519 uint32_t program_fail : 1;
7520 uint32_t erase_fail : 1;
7521 uint32_t load_comp : 1;
7522 uint32_t program_comp : 1;
7523 uint32_t erase_comp : 1;
7524 uint32_t pipe_cpybck_cmd_comp : 1;
7525 uint32_t locked_blk : 1;
7526 uint32_t unsup_cmd : 1;
7527 uint32_t int_act : 1;
7528 uint32_t rst_comp : 1;
7529 uint32_t pipe_cmd_err : 1;
7530 uint32_t page_xfer_inc : 1;
7531 uint32_t erased_page : 1;
7536 typedef volatile struct ALT_NAND_STAT_INTR_STAT1_s ALT_NAND_STAT_INTR_STAT1_t;
7540 #define ALT_NAND_STAT_INTR_STAT1_RESET 0x00000000
7542 #define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
7585 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
7587 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
7589 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
7591 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7593 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7595 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
7597 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7599 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7610 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
7612 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
7614 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
7616 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
7618 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7620 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
7622 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7624 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7638 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
7640 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
7642 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
7644 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
7646 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
7648 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
7650 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7652 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7667 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
7669 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
7671 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
7673 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
7675 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7677 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
7679 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7681 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7696 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
7698 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
7700 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
7702 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
7704 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
7706 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
7708 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7710 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7721 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
7723 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
7725 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
7727 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
7729 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
7731 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
7733 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7735 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7746 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
7748 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
7750 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
7752 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
7754 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7756 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
7758 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7760 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7771 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
7773 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
7775 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
7777 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
7779 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
7781 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
7783 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7785 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7797 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
7799 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
7801 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7803 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7805 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7807 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7809 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7811 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7825 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
7827 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
7829 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
7831 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
7833 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
7835 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
7837 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7839 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7853 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
7855 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
7857 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
7859 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
7861 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7863 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
7865 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7867 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7878 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
7880 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
7882 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
7884 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
7886 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
7888 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
7890 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7892 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7903 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
7905 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
7907 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
7909 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
7911 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
7913 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
7915 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7917 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7934 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
7936 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
7938 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
7940 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
7942 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7944 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
7946 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7948 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7959 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
7961 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
7963 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
7965 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
7967 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7969 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
7971 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7973 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8006 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_LSB 16
8008 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_MSB 16
8010 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_WIDTH 1
8012 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET_MSK 0x00010000
8014 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_CLR_MSK 0xfffeffff
8016 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_RESET 0x0
8018 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8020 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8022 #ifndef __ASSEMBLY__
8033 struct ALT_NAND_STAT_INTR_EN1_s
8035 uint32_t ecc_uncor_err : 1;
8037 uint32_t dma_cmd_comp : 1;
8038 uint32_t time_out : 1;
8039 uint32_t program_fail : 1;
8040 uint32_t erase_fail : 1;
8041 uint32_t load_comp : 1;
8042 uint32_t program_comp : 1;
8043 uint32_t erase_comp : 1;
8044 uint32_t pipe_cpybck_cmd_comp : 1;
8045 uint32_t locked_blk : 1;
8046 uint32_t unsup_cmd : 1;
8047 uint32_t int_act : 1;
8048 uint32_t rst_comp : 1;
8049 uint32_t pipe_cmd_err : 1;
8050 uint32_t page_xfer_inc : 1;
8051 uint32_t erased_page : 1;
8056 typedef volatile struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
8060 #define ALT_NAND_STAT_INTR_EN1_RESET 0x00002000
8062 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
8088 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
8090 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
8092 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
8094 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
8096 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
8098 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
8100 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8102 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8104 #ifndef __ASSEMBLY__
8115 struct ALT_NAND_STAT_PAGE_CNT1_s
8117 const uint32_t value : 8;
8122 typedef volatile struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
8126 #define ALT_NAND_STAT_PAGE_CNT1_RESET 0x00000000
8128 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
8154 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
8156 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
8158 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
8160 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
8162 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
8164 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
8166 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8168 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8170 #ifndef __ASSEMBLY__
8181 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
8183 const uint32_t value : 16;
8188 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
8192 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_RESET 0x00000000
8194 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
8220 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
8222 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
8224 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
8226 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
8228 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
8230 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
8232 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8234 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8236 #ifndef __ASSEMBLY__
8247 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
8249 const uint32_t value : 16;
8254 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
8258 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_RESET 0x00000000
8260 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
8300 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
8302 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
8304 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
8306 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8308 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8310 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
8312 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8314 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8325 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
8327 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
8329 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
8331 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
8333 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8335 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
8337 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8339 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8353 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
8355 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
8357 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
8359 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
8361 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
8363 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
8365 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8367 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8382 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
8384 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
8386 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
8388 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
8390 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8392 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
8394 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8396 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8411 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
8413 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
8415 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
8417 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
8419 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
8421 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
8423 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8425 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8436 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
8438 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
8440 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
8442 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
8444 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
8446 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
8448 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8450 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8461 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
8463 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
8465 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
8467 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
8469 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8471 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
8473 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8475 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8486 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
8488 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
8490 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
8492 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
8494 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
8496 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
8498 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8500 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8512 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
8514 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
8516 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8518 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8520 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8522 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8524 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8526 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8540 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
8542 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
8544 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
8546 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
8548 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
8550 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
8552 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8554 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8568 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
8570 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
8572 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
8574 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
8576 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
8578 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
8580 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8582 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8593 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
8595 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
8597 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
8599 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
8601 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
8603 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
8605 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8607 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8619 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
8621 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
8623 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
8625 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
8627 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
8629 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
8631 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8633 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8650 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
8652 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
8654 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
8656 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
8658 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8660 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
8662 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8664 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8675 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
8677 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
8679 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
8681 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
8683 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8685 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
8687 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8689 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8722 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_LSB 16
8724 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_MSB 16
8726 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_WIDTH 1
8728 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET_MSK 0x00010000
8730 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_CLR_MSK 0xfffeffff
8732 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_RESET 0x0
8734 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8736 #define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8738 #ifndef __ASSEMBLY__
8749 struct ALT_NAND_STAT_INTR_STAT2_s
8751 uint32_t ecc_uncor_err : 1;
8753 uint32_t dma_cmd_comp : 1;
8754 uint32_t time_out : 1;
8755 uint32_t program_fail : 1;
8756 uint32_t erase_fail : 1;
8757 uint32_t load_comp : 1;
8758 uint32_t program_comp : 1;
8759 uint32_t erase_comp : 1;
8760 uint32_t pipe_cpybck_cmd_comp : 1;
8761 uint32_t locked_blk : 1;
8762 uint32_t unsup_cmd : 1;
8763 uint32_t int_act : 1;
8764 uint32_t rst_comp : 1;
8765 uint32_t pipe_cmd_err : 1;
8766 uint32_t page_xfer_inc : 1;
8767 uint32_t erased_page : 1;
8772 typedef volatile struct ALT_NAND_STAT_INTR_STAT2_s ALT_NAND_STAT_INTR_STAT2_t;
8776 #define ALT_NAND_STAT_INTR_STAT2_RESET 0x00000000
8778 #define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
8821 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
8823 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
8825 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
8827 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8829 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8831 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
8833 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8835 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8846 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
8848 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
8850 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
8852 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
8854 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8856 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
8858 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8860 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8874 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
8876 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
8878 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
8880 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
8882 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
8884 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
8886 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8888 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8903 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
8905 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
8907 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
8909 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
8911 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8913 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
8915 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8917 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8932 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
8934 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
8936 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
8938 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
8940 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
8942 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
8944 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8946 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8957 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
8959 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
8961 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
8963 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
8965 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
8967 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
8969 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8971 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8982 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
8984 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
8986 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
8988 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
8990 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8992 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
8994 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8996 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9007 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
9009 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
9011 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
9013 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
9015 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
9017 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
9019 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9021 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9033 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
9035 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
9037 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9039 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9041 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9043 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9045 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9047 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9061 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
9063 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
9065 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
9067 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
9069 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
9071 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
9073 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9075 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9089 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
9091 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
9093 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
9095 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
9097 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
9099 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
9101 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9103 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9114 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
9116 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
9118 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
9120 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
9122 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
9124 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
9126 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9128 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9139 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
9141 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
9143 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
9145 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
9147 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
9149 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
9151 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9153 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9170 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
9172 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
9174 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
9176 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
9178 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9180 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
9182 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9184 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9195 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
9197 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
9199 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
9201 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
9203 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9205 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
9207 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9209 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9242 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_LSB 16
9244 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_MSB 16
9246 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_WIDTH 1
9248 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET_MSK 0x00010000
9250 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_CLR_MSK 0xfffeffff
9252 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_RESET 0x0
9254 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9256 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9258 #ifndef __ASSEMBLY__
9269 struct ALT_NAND_STAT_INTR_EN2_s
9271 uint32_t ecc_uncor_err : 1;
9273 uint32_t dma_cmd_comp : 1;
9274 uint32_t time_out : 1;
9275 uint32_t program_fail : 1;
9276 uint32_t erase_fail : 1;
9277 uint32_t load_comp : 1;
9278 uint32_t program_comp : 1;
9279 uint32_t erase_comp : 1;
9280 uint32_t pipe_cpybck_cmd_comp : 1;
9281 uint32_t locked_blk : 1;
9282 uint32_t unsup_cmd : 1;
9283 uint32_t int_act : 1;
9284 uint32_t rst_comp : 1;
9285 uint32_t pipe_cmd_err : 1;
9286 uint32_t page_xfer_inc : 1;
9287 uint32_t erased_page : 1;
9292 typedef volatile struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
9296 #define ALT_NAND_STAT_INTR_EN2_RESET 0x00002000
9298 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
9324 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
9326 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
9328 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
9330 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
9332 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
9334 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
9336 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9338 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9340 #ifndef __ASSEMBLY__
9351 struct ALT_NAND_STAT_PAGE_CNT2_s
9353 const uint32_t value : 8;
9358 typedef volatile struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
9362 #define ALT_NAND_STAT_PAGE_CNT2_RESET 0x00000000
9364 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
9390 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
9392 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
9394 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
9396 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
9398 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
9400 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
9402 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9404 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9406 #ifndef __ASSEMBLY__
9417 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
9419 const uint32_t value : 16;
9424 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
9428 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_RESET 0x00000000
9430 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
9456 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
9458 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
9460 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
9462 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
9464 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
9466 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
9468 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9470 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9472 #ifndef __ASSEMBLY__
9483 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
9485 const uint32_t value : 16;
9490 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
9494 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_RESET 0x00000000
9496 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
9536 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
9538 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
9540 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
9542 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
9544 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9546 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
9548 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9550 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9561 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
9563 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
9565 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
9567 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
9569 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9571 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
9573 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9575 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9589 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
9591 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
9593 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
9595 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
9597 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
9599 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
9601 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9603 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9618 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
9620 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
9622 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
9624 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
9626 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
9628 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
9630 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9632 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9647 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
9649 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
9651 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
9653 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
9655 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
9657 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
9659 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9661 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9672 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
9674 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
9676 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
9678 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
9680 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
9682 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
9684 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9686 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
9697 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
9699 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
9701 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
9703 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
9705 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
9707 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
9709 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9711 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9722 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
9724 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
9726 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
9728 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
9730 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
9732 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
9734 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9736 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9748 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
9750 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
9752 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9754 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9756 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9758 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9760 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9762 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9776 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
9778 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
9780 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
9782 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
9784 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
9786 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
9788 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9790 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9804 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
9806 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
9808 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
9810 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
9812 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9814 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
9816 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9818 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9829 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
9831 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
9833 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
9835 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
9837 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
9839 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
9841 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9843 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9855 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
9857 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
9859 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
9861 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
9863 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
9865 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
9867 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9869 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9886 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
9888 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
9890 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
9892 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
9894 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9896 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
9898 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9900 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9911 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
9913 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
9915 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
9917 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
9919 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9921 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
9923 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9925 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9958 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_LSB 16
9960 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_MSB 16
9962 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_WIDTH 1
9964 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET_MSK 0x00010000
9966 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_CLR_MSK 0xfffeffff
9968 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_RESET 0x0
9970 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9972 #define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9974 #ifndef __ASSEMBLY__
9985 struct ALT_NAND_STAT_INTR_STAT3_s
9987 uint32_t ecc_uncor_err : 1;
9989 uint32_t dma_cmd_comp : 1;
9990 uint32_t time_out : 1;
9991 uint32_t program_fail : 1;
9992 uint32_t erase_fail : 1;
9993 uint32_t load_comp : 1;
9994 uint32_t program_comp : 1;
9995 uint32_t erase_comp : 1;
9996 uint32_t pipe_cpybck_cmd_comp : 1;
9997 uint32_t locked_blk : 1;
9998 uint32_t unsup_cmd : 1;
9999 uint32_t int_act : 1;
10000 uint32_t rst_comp : 1;
10001 uint32_t pipe_cmd_err : 1;
10002 uint32_t page_xfer_inc : 1;
10003 uint32_t erased_page : 1;
10008 typedef volatile struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t;
10012 #define ALT_NAND_STAT_INTR_STAT3_RESET 0x00000000
10014 #define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
10057 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
10059 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
10061 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
10063 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
10065 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
10067 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
10069 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
10071 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
10082 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
10084 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
10086 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
10088 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
10090 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
10092 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
10094 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
10096 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
10110 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
10112 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
10114 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
10116 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
10118 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
10120 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
10122 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
10124 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
10139 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
10141 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
10143 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
10145 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
10147 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
10149 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
10151 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
10153 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
10168 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
10170 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
10172 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
10174 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
10176 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
10178 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
10180 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
10182 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
10193 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
10195 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
10197 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
10199 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
10201 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
10203 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
10205 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
10207 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
10218 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
10220 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
10222 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
10224 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
10226 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
10228 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
10230 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
10232 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
10243 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
10245 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
10247 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
10249 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
10251 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
10253 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
10255 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
10257 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
10269 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
10271 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
10273 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
10275 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10277 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10279 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10281 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10283 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10297 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
10299 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
10301 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
10303 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
10305 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
10307 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
10309 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10311 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10325 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
10327 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
10329 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
10331 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
10333 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10335 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
10337 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10339 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10350 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
10352 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
10354 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
10356 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
10358 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
10360 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
10362 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10364 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10375 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
10377 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
10379 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
10381 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
10383 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
10385 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
10387 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10389 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10406 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
10408 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
10410 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
10412 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
10414 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10416 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
10418 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10420 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10431 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
10433 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
10435 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
10437 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
10439 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10441 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
10443 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10445 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10478 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_LSB 16
10480 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_MSB 16
10482 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_WIDTH 1
10484 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET_MSK 0x00010000
10486 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_CLR_MSK 0xfffeffff
10488 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_RESET 0x0
10490 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10492 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10494 #ifndef __ASSEMBLY__
10505 struct ALT_NAND_STAT_INTR_EN3_s
10507 uint32_t ecc_uncor_err : 1;
10509 uint32_t dma_cmd_comp : 1;
10510 uint32_t time_out : 1;
10511 uint32_t program_fail : 1;
10512 uint32_t erase_fail : 1;
10513 uint32_t load_comp : 1;
10514 uint32_t program_comp : 1;
10515 uint32_t erase_comp : 1;
10516 uint32_t pipe_cpybck_cmd_comp : 1;
10517 uint32_t locked_blk : 1;
10518 uint32_t unsup_cmd : 1;
10519 uint32_t int_act : 1;
10520 uint32_t rst_comp : 1;
10521 uint32_t pipe_cmd_err : 1;
10522 uint32_t page_xfer_inc : 1;
10523 uint32_t erased_page : 1;
10528 typedef volatile struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
10532 #define ALT_NAND_STAT_INTR_EN3_RESET 0x00002000
10534 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
10560 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
10562 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
10564 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
10566 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
10568 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
10570 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
10572 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
10574 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
10576 #ifndef __ASSEMBLY__
10587 struct ALT_NAND_STAT_PAGE_CNT3_s
10589 const uint32_t value : 8;
10594 typedef volatile struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
10598 #define ALT_NAND_STAT_PAGE_CNT3_RESET 0x00000000
10600 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
10626 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
10628 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
10630 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
10632 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
10634 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
10636 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
10638 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10640 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10642 #ifndef __ASSEMBLY__
10653 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
10655 const uint32_t value : 16;
10660 typedef volatile struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
10664 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_RESET 0x00000000
10666 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
10692 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
10694 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
10696 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
10698 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
10700 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
10702 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
10704 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10706 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10708 #ifndef __ASSEMBLY__
10719 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
10721 const uint32_t value : 16;
10726 typedef volatile struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
10730 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_RESET 0x00000000
10732 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
10734 #ifndef __ASSEMBLY__
10745 struct ALT_NAND_STAT_s
10748 volatile uint32_t _pad_0x4_0xf[3];
10749 ALT_NAND_STAT_INTR_STAT0_t intr_status0;
10750 volatile uint32_t _pad_0x14_0x1f[3];
10751 ALT_NAND_STAT_INTR_EN0_t intr_en0;
10752 volatile uint32_t _pad_0x24_0x2f[3];
10753 ALT_NAND_STAT_PAGE_CNT0_t page_cnt0;
10754 volatile uint32_t _pad_0x34_0x3f[3];
10755 ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0;
10756 volatile uint32_t _pad_0x44_0x4f[3];
10757 ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0;
10758 volatile uint32_t _pad_0x54_0x5f[3];
10759 ALT_NAND_STAT_INTR_STAT1_t intr_status1;
10760 volatile uint32_t _pad_0x64_0x6f[3];
10761 ALT_NAND_STAT_INTR_EN1_t intr_en1;
10762 volatile uint32_t _pad_0x74_0x7f[3];
10763 ALT_NAND_STAT_PAGE_CNT1_t page_cnt1;
10764 volatile uint32_t _pad_0x84_0x8f[3];
10765 ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1;
10766 volatile uint32_t _pad_0x94_0x9f[3];
10767 ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1;
10768 volatile uint32_t _pad_0xa4_0xaf[3];
10769 ALT_NAND_STAT_INTR_STAT2_t intr_status2;
10770 volatile uint32_t _pad_0xb4_0xbf[3];
10771 ALT_NAND_STAT_INTR_EN2_t intr_en2;
10772 volatile uint32_t _pad_0xc4_0xcf[3];
10773 ALT_NAND_STAT_PAGE_CNT2_t page_cnt2;
10774 volatile uint32_t _pad_0xd4_0xdf[3];
10775 ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2;
10776 volatile uint32_t _pad_0xe4_0xef[3];
10777 ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2;
10778 volatile uint32_t _pad_0xf4_0xff[3];
10779 ALT_NAND_STAT_INTR_STAT3_t intr_status3;
10780 volatile uint32_t _pad_0x104_0x10f[3];
10781 ALT_NAND_STAT_INTR_EN3_t intr_en3;
10782 volatile uint32_t _pad_0x114_0x11f[3];
10783 ALT_NAND_STAT_PAGE_CNT3_t page_cnt3;
10784 volatile uint32_t _pad_0x124_0x12f[3];
10785 ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3;
10786 volatile uint32_t _pad_0x134_0x13f[3];
10787 ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3;
10791 typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
10793 struct ALT_NAND_STAT_raw_s
10796 uint32_t _pad_0x4_0xf[3];
10797 volatile uint32_t intr_status0;
10798 uint32_t _pad_0x14_0x1f[3];
10799 volatile uint32_t intr_en0;
10800 uint32_t _pad_0x24_0x2f[3];
10801 volatile uint32_t page_cnt0;
10802 uint32_t _pad_0x34_0x3f[3];
10803 volatile uint32_t err_page_addr0;
10804 uint32_t _pad_0x44_0x4f[3];
10805 volatile uint32_t err_block_addr0;
10806 uint32_t _pad_0x54_0x5f[3];
10807 volatile uint32_t intr_status1;
10808 uint32_t _pad_0x64_0x6f[3];
10809 volatile uint32_t intr_en1;
10810 uint32_t _pad_0x74_0x7f[3];
10811 volatile uint32_t page_cnt1;
10812 uint32_t _pad_0x84_0x8f[3];
10813 volatile uint32_t err_page_addr1;
10814 uint32_t _pad_0x94_0x9f[3];
10815 volatile uint32_t err_block_addr1;
10816 uint32_t _pad_0xa4_0xaf[3];
10817 volatile uint32_t intr_status2;
10818 uint32_t _pad_0xb4_0xbf[3];
10819 volatile uint32_t intr_en2;
10820 uint32_t _pad_0xc4_0xcf[3];
10821 volatile uint32_t page_cnt2;
10822 uint32_t _pad_0xd4_0xdf[3];
10823 volatile uint32_t err_page_addr2;
10824 uint32_t _pad_0xe4_0xef[3];
10825 volatile uint32_t err_block_addr2;
10826 uint32_t _pad_0xf4_0xff[3];
10827 volatile uint32_t intr_status3;
10828 uint32_t _pad_0x104_0x10f[3];
10829 volatile uint32_t intr_en3;
10830 uint32_t _pad_0x114_0x11f[3];
10831 volatile uint32_t page_cnt3;
10832 uint32_t _pad_0x124_0x12f[3];
10833 volatile uint32_t err_page_addr3;
10834 uint32_t _pad_0x134_0x13f[3];
10835 volatile uint32_t err_block_addr3;
10839 typedef volatile struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
10882 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
10884 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
10886 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
10888 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
10890 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
10892 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
10894 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
10896 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
10910 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
10912 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
10914 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
10916 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
10918 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
10920 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
10922 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
10924 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
10941 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
10943 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
10945 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
10947 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
10949 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
10951 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
10953 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
10955 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
10969 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
10971 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
10973 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
10975 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
10977 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
10979 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
10981 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
10983 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
10985 #ifndef __ASSEMBLY__
10996 struct ALT_NAND_ECC_ECCCORINFO_B01_s
10998 const uint32_t max_errors_b0 : 7;
10999 const uint32_t uncor_err_b0 : 1;
11000 const uint32_t max_errors_b1 : 7;
11001 const uint32_t uncor_err_b1 : 1;
11006 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
11010 #define ALT_NAND_ECC_ECCCORINFO_B01_RESET 0x00000000
11012 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
11049 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
11051 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
11053 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
11055 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
11057 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
11059 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
11061 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
11063 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
11077 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
11079 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
11081 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
11083 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
11085 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
11087 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
11089 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
11091 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
11108 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
11110 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
11112 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
11114 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
11116 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
11118 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
11120 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
11122 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
11136 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
11138 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
11140 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
11142 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
11144 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
11146 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
11148 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
11150 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
11152 #ifndef __ASSEMBLY__
11163 struct ALT_NAND_ECC_ECCCORINFO_B23_s
11165 const uint32_t max_errors_b2 : 7;
11166 const uint32_t uncor_err_b2 : 1;
11167 const uint32_t max_errors_b3 : 7;
11168 const uint32_t uncor_err_b3 : 1;
11173 typedef volatile struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
11177 #define ALT_NAND_ECC_ECCCORINFO_B23_RESET 0x00000000
11179 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
11181 #ifndef __ASSEMBLY__
11192 struct ALT_NAND_ECC_s
11194 ALT_NAND_ECC_ECCCORINFO_B01_t ecccorinfo_b01;
11195 volatile uint32_t _pad_0x4_0xf[3];
11196 ALT_NAND_ECC_ECCCORINFO_B23_t ecccorinfo_b23;
11200 typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
11202 struct ALT_NAND_ECC_raw_s
11204 volatile uint32_t ecccorinfo_b01;
11205 uint32_t _pad_0x4_0xf[3];
11206 volatile uint32_t ecccorinfo_b23;
11210 typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
11240 #define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
11242 #define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
11244 #define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
11246 #define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
11248 #define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
11250 #define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
11252 #define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
11254 #define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
11256 #ifndef __ASSEMBLY__
11267 struct ALT_NAND_DMA_DMA_EN_s
11274 typedef volatile struct ALT_NAND_DMA_DMA_EN_s ALT_NAND_DMA_DMA_EN_t;
11278 #define ALT_NAND_DMA_DMA_EN_RESET 0x00000000
11280 #define ALT_NAND_DMA_DMA_EN_OFST 0x0
11311 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
11313 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
11315 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
11317 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
11319 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
11321 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
11323 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11325 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11337 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_LSB 1
11339 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_MSB 1
11341 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_WIDTH 1
11343 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11345 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11347 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_RESET 0x0
11349 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11351 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11363 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_LSB 2
11365 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_MSB 2
11367 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_WIDTH 1
11369 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11371 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11373 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_RESET 0x0
11375 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11377 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11389 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_LSB 3
11391 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_MSB 3
11393 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_WIDTH 1
11395 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11397 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11399 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_RESET 0x0
11401 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11403 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11415 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_LSB 4
11417 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_MSB 4
11419 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_WIDTH 1
11421 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11423 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11425 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_RESET 0x0
11427 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11429 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11440 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_LSB 6
11442 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_MSB 6
11444 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_WIDTH 1
11446 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET_MSK 0x00000040
11448 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11450 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_RESET 0x0
11452 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11454 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11456 #ifndef __ASSEMBLY__
11467 struct ALT_NAND_DMA_DMA_INTR_s
11469 uint32_t target_error : 1;
11470 uint32_t desc_comp_channel0 : 1;
11471 uint32_t desc_comp_channel1 : 1;
11472 uint32_t desc_comp_channel2 : 1;
11473 uint32_t desc_comp_channel3 : 1;
11475 uint32_t cmddma_idle : 1;
11480 typedef volatile struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
11484 #define ALT_NAND_DMA_DMA_INTR_RESET 0x00000000
11486 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
11517 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
11519 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
11521 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
11523 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
11525 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
11527 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
11529 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11531 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11543 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB 1
11545 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB 1
11547 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH 1
11549 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11551 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11553 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET 0x0
11555 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11557 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11569 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB 2
11571 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB 2
11573 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH 1
11575 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11577 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11579 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET 0x0
11581 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11583 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11595 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB 3
11597 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB 3
11599 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH 1
11601 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11603 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11605 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET 0x0
11607 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11609 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11621 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB 4
11623 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB 4
11625 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH 1
11627 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11629 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11631 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET 0x0
11633 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11635 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11648 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB 6
11650 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB 6
11652 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH 1
11654 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK 0x00000040
11656 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11658 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET 0x0
11660 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11662 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11664 #ifndef __ASSEMBLY__
11675 struct ALT_NAND_DMA_DMA_INTR_EN_s
11677 uint32_t target_error : 1;
11678 uint32_t desc_comp_channel0 : 1;
11679 uint32_t desc_comp_channel1 : 1;
11680 uint32_t desc_comp_channel2 : 1;
11681 uint32_t desc_comp_channel3 : 1;
11683 uint32_t cmddma_idle : 1;
11688 typedef volatile struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
11692 #define ALT_NAND_DMA_DMA_INTR_EN_RESET 0x00000000
11694 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
11719 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
11721 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
11723 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
11725 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
11727 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
11729 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
11731 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11733 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11735 #ifndef __ASSEMBLY__
11746 struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
11748 const uint32_t value : 16;
11753 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_LO_s ALT_NAND_DMA_TGT_ERR_ADDR_LO_t;
11757 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_RESET 0x00000000
11759 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
11784 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
11786 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
11788 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
11790 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
11792 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
11794 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
11796 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11798 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11800 #ifndef __ASSEMBLY__
11811 struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
11813 const uint32_t value : 16;
11818 typedef volatile struct ALT_NAND_DMA_TGT_ERR_ADDR_HI_s ALT_NAND_DMA_TGT_ERR_ADDR_HI_t;
11822 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_RESET 0x00000000
11824 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
11851 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_LSB 0
11853 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_MSB 0
11855 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_WIDTH 1
11857 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET_MSK 0x00000001
11859 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_CLR_MSK 0xfffffffe
11861 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_RESET 0x0
11863 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
11865 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
11876 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_LSB 1
11878 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_MSB 1
11880 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_WIDTH 1
11882 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET_MSK 0x00000002
11884 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_CLR_MSK 0xfffffffd
11886 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_RESET 0x0
11888 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
11890 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
11901 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_LSB 2
11903 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_MSB 2
11905 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_WIDTH 1
11907 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET_MSK 0x00000004
11909 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_CLR_MSK 0xfffffffb
11911 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_RESET 0x0
11913 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
11915 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
11926 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_LSB 3
11928 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_MSB 3
11930 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_WIDTH 1
11932 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET_MSK 0x00000008
11934 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_CLR_MSK 0xfffffff7
11936 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_RESET 0x0
11938 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
11940 #define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
11942 #ifndef __ASSEMBLY__
11953 struct ALT_NAND_DMA_CHNL_ACT_s
11955 const uint32_t channel0 : 1;
11956 const uint32_t channel1 : 1;
11957 const uint32_t channel2 : 1;
11958 const uint32_t channel3 : 1;
11963 typedef volatile struct ALT_NAND_DMA_CHNL_ACT_s ALT_NAND_DMA_CHNL_ACT_t;
11967 #define ALT_NAND_DMA_CHNL_ACT_RESET 0x00000000
11969 #define ALT_NAND_DMA_CHNL_ACT_OFST 0x60
12008 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
12010 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
12012 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
12014 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
12016 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
12018 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
12020 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
12022 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
12037 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
12039 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
12041 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
12043 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
12045 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
12047 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
12049 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
12051 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
12065 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_LSB 8
12067 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_MSB 31
12069 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_WIDTH 24
12071 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET_MSK 0xffffff00
12073 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_CLR_MSK 0x000000ff
12075 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_RESET 0x0
12077 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_GET(value) (((value) & 0xffffff00) >> 8)
12079 #define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET(value) (((value) << 8) & 0xffffff00)
12081 #ifndef __ASSEMBLY__
12092 struct ALT_NAND_DMA_FLSH_BURST_LEN_s
12094 uint32_t value : 2;
12096 uint32_t continous_burst : 1;
12098 uint32_t polling_sync_counter_value : 24;
12102 typedef volatile struct ALT_NAND_DMA_FLSH_BURST_LEN_s ALT_NAND_DMA_FLSH_BURST_LEN_t;
12106 #define ALT_NAND_DMA_FLSH_BURST_LEN_RESET 0x00000001
12108 #define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
12138 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
12140 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
12142 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
12144 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
12146 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
12148 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
12150 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
12152 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
12178 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
12180 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
12182 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
12184 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
12186 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
12188 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
12190 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
12192 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
12217 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_LSB 8
12219 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_MSB 8
12221 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_WIDTH 1
12223 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET_MSK 0x00000100
12225 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_CLR_MSK 0xfffffeff
12227 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_RESET 0x1
12229 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_GET(value) (((value) & 0x00000100) >> 8)
12231 #define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET(value) (((value) << 8) & 0x00000100)
12233 #ifndef __ASSEMBLY__
12244 struct ALT_NAND_DMA_INTRLV_s
12246 uint32_t chip_interleave_enable : 1;
12248 uint32_t allow_int_reads_within_luns : 1;
12250 uint32_t cmd_dma_error_enable : 1;
12255 typedef volatile struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t;
12259 #define ALT_NAND_DMA_INTRLV_RESET 0x00000110
12261 #define ALT_NAND_DMA_INTRLV_OFST 0x80
12294 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_LSB 0
12296 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_MSB 3
12298 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_WIDTH 4
12300 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET_MSK 0x0000000f
12302 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_CLR_MSK 0xfffffff0
12304 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_RESET 0x0
12306 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_GET(value) (((value) & 0x0000000f) >> 0)
12308 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET(value) (((value) << 0) & 0x0000000f)
12310 #ifndef __ASSEMBLY__
12321 struct ALT_NAND_DMA_RESCAN_BUF_FLAG_s
12328 typedef volatile struct ALT_NAND_DMA_RESCAN_BUF_FLAG_s ALT_NAND_DMA_RESCAN_BUF_FLAG_t;
12332 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_RESET 0x00000000
12334 #define ALT_NAND_DMA_RESCAN_BUF_FLAG_OFST 0x90
12379 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
12381 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
12383 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
12385 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
12387 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
12389 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
12391 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
12393 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
12410 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24
12412 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24
12414 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1
12416 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000
12418 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff
12420 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0
12422 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET(value) (((value) & 0x01000000) >> 24)
12424 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET(value) (((value) << 24) & 0x01000000)
12444 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_LSB 28
12446 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_MSB 28
12448 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_WIDTH 1
12450 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET_MSK 0x10000000
12452 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_CLR_MSK 0xefffffff
12454 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_RESET 0x0
12456 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28)
12458 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000)
12460 #ifndef __ASSEMBLY__
12471 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
12473 uint32_t value : 4;
12475 uint32_t update_sync_before_prog_comp : 1;
12477 uint32_t issue_read_before_sync : 1;
12482 typedef volatile struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
12486 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f
12488 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0
12518 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
12520 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
12522 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
12524 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
12526 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
12528 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
12530 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12532 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12534 #ifndef __ASSEMBLY__
12545 struct ALT_NAND_DMA_LUN_STAT_CMD_s
12547 uint32_t value : 16;
12552 typedef volatile struct ALT_NAND_DMA_LUN_STAT_CMD_s ALT_NAND_DMA_LUN_STAT_CMD_t;
12556 #define ALT_NAND_DMA_LUN_STAT_CMD_RESET 0x00007878
12558 #define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xb0
12586 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0
12588 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0
12590 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1
12592 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001
12594 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe
12596 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0
12598 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12600 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12611 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1
12613 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1
12615 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1
12617 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002
12619 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd
12621 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0
12623 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12625 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12636 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2
12638 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2
12640 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1
12642 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004
12644 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb
12646 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0
12648 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12650 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12661 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3
12663 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3
12665 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1
12667 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008
12669 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7
12671 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0
12673 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12675 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12677 #ifndef __ASSEMBLY__
12688 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
12690 uint32_t channel0 : 1;
12691 uint32_t channel1 : 1;
12692 uint32_t channel2 : 1;
12693 uint32_t channel3 : 1;
12698 typedef volatile struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t;
12702 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000
12704 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0
12732 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_LSB 0
12734 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_MSB 0
12736 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_WIDTH 1
12738 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET_MSK 0x00000001
12740 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_CLR_MSK 0xfffffffe
12742 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_RESET 0x0
12744 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12746 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12757 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_LSB 1
12759 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_MSB 1
12761 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_WIDTH 1
12763 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET_MSK 0x00000002
12765 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_CLR_MSK 0xfffffffd
12767 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_RESET 0x0
12769 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12771 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12782 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_LSB 2
12784 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_MSB 2
12786 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_WIDTH 1
12788 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET_MSK 0x00000004
12790 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_CLR_MSK 0xfffffffb
12792 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_RESET 0x0
12794 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12796 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12807 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_LSB 3
12809 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_MSB 3
12811 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_WIDTH 1
12813 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET_MSK 0x00000008
12815 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_CLR_MSK 0xfffffff7
12817 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_RESET 0x0
12819 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12821 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12823 #ifndef __ASSEMBLY__
12834 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
12836 uint32_t channel0 : 1;
12837 uint32_t channel1 : 1;
12838 uint32_t channel2 : 1;
12839 uint32_t channel3 : 1;
12844 typedef volatile struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t;
12848 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_RESET 0x00000000
12850 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST 0xd0
12852 #ifndef __ASSEMBLY__
12863 struct ALT_NAND_DMA_s
12865 ALT_NAND_DMA_DMA_EN_t dma_enable;
12866 volatile uint32_t _pad_0x4_0x1f[7];
12867 ALT_NAND_DMA_DMA_INTR_t dma_intr;
12868 volatile uint32_t _pad_0x24_0x2f[3];
12869 ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en;
12870 volatile uint32_t _pad_0x34_0x3f[3];
12871 ALT_NAND_DMA_TGT_ERR_ADDR_LO_t target_err_addr_lo;
12872 volatile uint32_t _pad_0x44_0x4f[3];
12873 ALT_NAND_DMA_TGT_ERR_ADDR_HI_t target_err_addr_hi;
12874 volatile uint32_t _pad_0x54_0x5f[3];
12875 ALT_NAND_DMA_CHNL_ACT_t chnl_active;
12876 volatile uint32_t _pad_0x64_0x6f[3];
12877 ALT_NAND_DMA_FLSH_BURST_LEN_t flash_burst_length;
12878 volatile uint32_t _pad_0x74_0x7f[3];
12879 ALT_NAND_DMA_INTRLV_t chip_interleave_enable_and_allow_int_reads;
12880 volatile uint32_t _pad_0x84_0x8f[3];
12881 ALT_NAND_DMA_RESCAN_BUF_FLAG_t rescan_buffer_flag;
12882 volatile uint32_t _pad_0x94_0x9f[3];
12883 ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun;
12884 volatile uint32_t _pad_0xa4_0xaf[3];
12885 ALT_NAND_DMA_LUN_STAT_CMD_t lun_status_cmd;
12886 volatile uint32_t _pad_0xb4_0xbf[3];
12887 ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t cmd_dma_channel_error;
12888 volatile uint32_t _pad_0xc4_0xcf[3];
12889 ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t cmd_dma_channel_error_en;
12893 typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
12895 struct ALT_NAND_DMA_raw_s
12897 volatile uint32_t dma_enable;
12898 uint32_t _pad_0x4_0x1f[7];
12899 volatile uint32_t dma_intr;
12900 uint32_t _pad_0x24_0x2f[3];
12901 volatile uint32_t dma_intr_en;
12902 uint32_t _pad_0x34_0x3f[3];
12903 volatile uint32_t target_err_addr_lo;
12904 uint32_t _pad_0x44_0x4f[3];
12905 volatile uint32_t target_err_addr_hi;
12906 uint32_t _pad_0x54_0x5f[3];
12907 volatile uint32_t chnl_active;
12908 uint32_t _pad_0x64_0x6f[3];
12909 volatile uint32_t flash_burst_length;
12910 uint32_t _pad_0x74_0x7f[3];
12911 volatile uint32_t chip_interleave_enable_and_allow_int_reads;
12912 uint32_t _pad_0x84_0x8f[3];
12913 volatile uint32_t rescan_buffer_flag;
12914 uint32_t _pad_0x94_0x9f[3];
12915 volatile uint32_t no_of_blocks_per_lun;
12916 uint32_t _pad_0xa4_0xaf[3];
12917 volatile uint32_t lun_status_cmd;
12918 uint32_t _pad_0xb4_0xbf[3];
12919 volatile uint32_t cmd_dma_channel_error;
12920 uint32_t _pad_0xc4_0xcf[3];
12921 volatile uint32_t cmd_dma_channel_error_en;
12925 typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;