Altera SoCAL  20.1
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_sdmmc.h
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32 
33 /* Altera - ALT_SDMMC */
34 
35 #ifndef __ALTERA_ALT_SDMMC_H__
36 #define __ALTERA_ALT_SDMMC_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : SDMMC Module - ALT_SDMMC
45  * SDMMC Module
46  *
47  * Registers in the SD/MMC module
48  *
49  */
50 /*
51  * Register : Control Register - ctrl
52  *
53  * Sets various operating condiitions.
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:------------------------------
59  * [0] | RW | 0x0 | Controller Reset
60  * [1] | RW | 0x0 | FIFO Reset
61  * [2] | RW | 0x0 | Dma Reset
62  * [3] | ??? | 0x0 | *UNDEFINED*
63  * [4] | RW | 0x0 | Int Enable
64  * [5] | ??? | 0x0 | *UNDEFINED*
65  * [6] | RW | 0x0 | Read Wait
66  * [7] | RW | 0x0 | Send Irq Response
67  * [8] | RW | 0x0 | Abort Read Data
68  * [9] | RW | 0x0 | Send CCSD
69  * [10] | RW | 0x0 | Send Auto Stop CCSD
70  * [11] | RW | 0x0 | Ceata Device Interrupt Status
71  * [24:12] | ??? | 0x0 | *UNDEFINED*
72  * [25] | RW | 0x0 | Use Internal DMAC
73  * [31:26] | ??? | 0x0 | *UNDEFINED*
74  *
75  */
76 /*
77  * Field : Controller Reset - controller_reset
78  *
79  * This bit resets the controller. This bit is auto-cleared after two l4_mp_clk and
80  * two sdmmc_clk clock cycles. This resets:
81  *
82  * * BIU/CIU interface
83  *
84  * * CIU and state machines
85  *
86  * * abort_read_data, send_irq_response, and read_wait bits of control register
87  *
88  * * start_cmd bit of command register
89  *
90  * Does not affect any registers, DMA interface, FIFO or host interrupts.
91  *
92  * Field Enumeration Values:
93  *
94  * Enum | Value | Description
95  * :------------------------------------|:------|:------------------------
96  * ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE | 0x0 | No change -default
97  * ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE | 0x1 | Reset SD/MMC controller
98  *
99  * Field Access Macros:
100  *
101  */
102 /*
103  * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
104  *
105  * No change -default
106  */
107 #define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
108 /*
109  * Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
110  *
111  * Reset SD/MMC controller
112  */
113 #define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
114 
115 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */
116 #define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
117 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field. */
118 #define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
119 /* The width in bits of the ALT_SDMMC_CTL_CTLLER_RST register field. */
120 #define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
121 /* The mask used to set the ALT_SDMMC_CTL_CTLLER_RST register field value. */
122 #define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
123 /* The mask used to clear the ALT_SDMMC_CTL_CTLLER_RST register field value. */
124 #define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
125 /* The reset value of the ALT_SDMMC_CTL_CTLLER_RST register field. */
126 #define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
127 /* Extracts the ALT_SDMMC_CTL_CTLLER_RST field value from a register. */
128 #define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
129 /* Produces a ALT_SDMMC_CTL_CTLLER_RST register field value suitable for setting the register. */
130 #define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
131 
132 /*
133  * Field : FIFO Reset - fifo_reset
134  *
135  * This bit resets the FIFO. This bit is auto-cleared after completion of reset
136  * operation.
137  *
138  * Field Enumeration Values:
139  *
140  * Enum | Value | Description
141  * :----------------------------------|:------|:------------------------------------------
142  * ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE | 0x0 | No change
143  * ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE | 0x1 | Reset to data FIFO To reset FIFO pointers
144  *
145  * Field Access Macros:
146  *
147  */
148 /*
149  * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
150  *
151  * No change
152  */
153 #define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
154 /*
155  * Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
156  *
157  * Reset to data FIFO To reset FIFO pointers
158  */
159 #define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
160 
161 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */
162 #define ALT_SDMMC_CTL_FIFO_RST_LSB 1
163 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_FIFO_RST register field. */
164 #define ALT_SDMMC_CTL_FIFO_RST_MSB 1
165 /* The width in bits of the ALT_SDMMC_CTL_FIFO_RST register field. */
166 #define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
167 /* The mask used to set the ALT_SDMMC_CTL_FIFO_RST register field value. */
168 #define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
169 /* The mask used to clear the ALT_SDMMC_CTL_FIFO_RST register field value. */
170 #define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
171 /* The reset value of the ALT_SDMMC_CTL_FIFO_RST register field. */
172 #define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
173 /* Extracts the ALT_SDMMC_CTL_FIFO_RST field value from a register. */
174 #define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
175 /* Produces a ALT_SDMMC_CTL_FIFO_RST register field value suitable for setting the register. */
176 #define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
177 
178 /*
179  * Field : Dma Reset - dma_reset
180  *
181  * This bit resets the DMA interface control logic
182  *
183  * Field Enumeration Values:
184  *
185  * Enum | Value | Description
186  * :---------------------------------|:------|:-------------------------------------------
187  * ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE | 0x0 | No change
188  * ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE | 0x1 | Reset internal DMA interface control logic
189  *
190  * Field Access Macros:
191  *
192  */
193 /*
194  * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
195  *
196  * No change
197  */
198 #define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
199 /*
200  * Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
201  *
202  * Reset internal DMA interface control logic
203  */
204 #define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
205 
206 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */
207 #define ALT_SDMMC_CTL_DMA_RST_LSB 2
208 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_RST register field. */
209 #define ALT_SDMMC_CTL_DMA_RST_MSB 2
210 /* The width in bits of the ALT_SDMMC_CTL_DMA_RST register field. */
211 #define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
212 /* The mask used to set the ALT_SDMMC_CTL_DMA_RST register field value. */
213 #define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
214 /* The mask used to clear the ALT_SDMMC_CTL_DMA_RST register field value. */
215 #define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
216 /* The reset value of the ALT_SDMMC_CTL_DMA_RST register field. */
217 #define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
218 /* Extracts the ALT_SDMMC_CTL_DMA_RST field value from a register. */
219 #define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
220 /* Produces a ALT_SDMMC_CTL_DMA_RST register field value suitable for setting the register. */
221 #define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
222 
223 /*
224  * Field : Int Enable - int_enable
225  *
226  * This bit enables and disable interrupts if one or more unmasked interrupts are
227  * set.
228  *
229  * Field Enumeration Values:
230  *
231  * Enum | Value | Description
232  * :----------------------------|:------|:-------------------
233  * ALT_SDMMC_CTL_INT_EN_E_DISD | 0x0 | Disable Interrupts
234  * ALT_SDMMC_CTL_INT_EN_E_END | 0x1 | Enable interrupts
235  *
236  * Field Access Macros:
237  *
238  */
239 /*
240  * Enumerated value for register field ALT_SDMMC_CTL_INT_EN
241  *
242  * Disable Interrupts
243  */
244 #define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
245 /*
246  * Enumerated value for register field ALT_SDMMC_CTL_INT_EN
247  *
248  * Enable interrupts
249  */
250 #define ALT_SDMMC_CTL_INT_EN_E_END 0x1
251 
252 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_INT_EN register field. */
253 #define ALT_SDMMC_CTL_INT_EN_LSB 4
254 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_INT_EN register field. */
255 #define ALT_SDMMC_CTL_INT_EN_MSB 4
256 /* The width in bits of the ALT_SDMMC_CTL_INT_EN register field. */
257 #define ALT_SDMMC_CTL_INT_EN_WIDTH 1
258 /* The mask used to set the ALT_SDMMC_CTL_INT_EN register field value. */
259 #define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
260 /* The mask used to clear the ALT_SDMMC_CTL_INT_EN register field value. */
261 #define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
262 /* The reset value of the ALT_SDMMC_CTL_INT_EN register field. */
263 #define ALT_SDMMC_CTL_INT_EN_RESET 0x0
264 /* Extracts the ALT_SDMMC_CTL_INT_EN field value from a register. */
265 #define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
266 /* Produces a ALT_SDMMC_CTL_INT_EN register field value suitable for setting the register. */
267 #define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
268 
269 /*
270  * Field : Read Wait - read_wait
271  *
272  * For sending read-wait to SDIO cards.
273  *
274  * Field Enumeration Values:
275  *
276  * Enum | Value | Description
277  * :---------------------------------|:------|:-----------------
278  * ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT | 0x0 | Read Wait
279  * ALT_SDMMC_CTL_RD_WAIT_E_ASSERT | 0x1 | Assert Read Wait
280  *
281  * Field Access Macros:
282  *
283  */
284 /*
285  * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
286  *
287  * Read Wait
288  */
289 #define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
290 /*
291  * Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
292  *
293  * Assert Read Wait
294  */
295 #define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
296 
297 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */
298 #define ALT_SDMMC_CTL_RD_WAIT_LSB 6
299 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_RD_WAIT register field. */
300 #define ALT_SDMMC_CTL_RD_WAIT_MSB 6
301 /* The width in bits of the ALT_SDMMC_CTL_RD_WAIT register field. */
302 #define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
303 /* The mask used to set the ALT_SDMMC_CTL_RD_WAIT register field value. */
304 #define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
305 /* The mask used to clear the ALT_SDMMC_CTL_RD_WAIT register field value. */
306 #define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
307 /* The reset value of the ALT_SDMMC_CTL_RD_WAIT register field. */
308 #define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
309 /* Extracts the ALT_SDMMC_CTL_RD_WAIT field value from a register. */
310 #define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
311 /* Produces a ALT_SDMMC_CTL_RD_WAIT register field value suitable for setting the register. */
312 #define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
313 
314 /*
315  * Field : Send Irq Response - send_irq_response
316  *
317  * Bit automatically clears once response is sent. To wait for MMC card interrupts,
318  * host issues CMD40, and SD/MMC waits for interrupt response from MMC card(s). In
319  * meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set
320  * this bit, at which time SD/MMC command state-machine sends CMD40 response on bus
321  * and returns to idle state.
322  *
323  * Field Enumeration Values:
324  *
325  * Enum | Value | Description
326  * :-------------------------------------------|:------|:-----------------------
327  * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE | 0x0 | No change
328  * ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE | 0x1 | Send auto IRQ response
329  *
330  * Field Access Macros:
331  *
332  */
333 /*
334  * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
335  *
336  * No change
337  */
338 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
339 /*
340  * Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
341  *
342  * Send auto IRQ response
343  */
344 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
345 
346 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
347 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
348 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
349 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
350 /* The width in bits of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
351 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
352 /* The mask used to set the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */
353 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
354 /* The mask used to clear the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value. */
355 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
356 /* The reset value of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field. */
357 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
358 /* Extracts the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE field value from a register. */
359 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
360 /* Produces a ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value suitable for setting the register. */
361 #define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
362 
363 /*
364  * Field : Abort Read Data - abort_read_data
365  *
366  * After suspend command is issued during read-transfer, software polls card to
367  * find when suspend happened. Once suspend occurs software sets bit to reset data
368  * state-machine, which is waiting for next block of data. Bit automatically clears
369  * once data statemachine resets to idle. Used in SDIO card suspend sequence.
370  *
371  * Field Enumeration Values:
372  *
373  * Enum | Value | Description
374  * :-------------------------------------|:------|:------------
375  * ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE | 0x0 | No change
376  * ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE | 0x1 | Abort Read
377  *
378  * Field Access Macros:
379  *
380  */
381 /*
382  * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
383  *
384  * No change
385  */
386 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
387 /*
388  * Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
389  *
390  * Abort Read
391  */
392 #define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
393 
394 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
395 #define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
396 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
397 #define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
398 /* The width in bits of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
399 #define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
400 /* The mask used to set the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */
401 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
402 /* The mask used to clear the ALT_SDMMC_CTL_ABT_RD_DATA register field value. */
403 #define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
404 /* The reset value of the ALT_SDMMC_CTL_ABT_RD_DATA register field. */
405 #define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
406 /* Extracts the ALT_SDMMC_CTL_ABT_RD_DATA field value from a register. */
407 #define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
408 /* Produces a ALT_SDMMC_CTL_ABT_RD_DATA register field value suitable for setting the register. */
409 #define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
410 
411 /*
412  * Field : Send CCSD - send_ccsd
413  *
414  * When set, SD/MMC sends CCSD to CE-ATA device. Software sets this bit only if
415  * current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in
416  * CE-ATA device. Once the CCSD pattern is sent to device, SD/MMC automatically
417  * clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and
418  * generates interrupt to host if Command Done interrupt is not masked.
419  *
420  * NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the
421  * CCSD on the CMD line. Due to this, during the boundary conditions it may happen
422  * that CCSD is sent to the CE-ATA device, even if the device signalled CCS.
423  *
424  * Field Enumeration Values:
425  *
426  * Enum | Value | Description
427  * :-----------------------------------|:------|:-------------------------------------------------
428  * ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit
429  * ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT | 0x1 | Send Command Completion Signal Disable (CCSD) to
430  * : | | CE-ATA device
431  *
432  * Field Access Macros:
433  *
434  */
435 /*
436  * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
437  *
438  * Clear bit if SD/MMC does not reset the bit
439  */
440 #define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
441 /*
442  * Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
443  *
444  * Send Command Completion Signal Disable (CCSD) to CE-ATA device
445  */
446 #define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
447 
448 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */
449 #define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
450 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field. */
451 #define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
452 /* The width in bits of the ALT_SDMMC_CTL_SEND_CCSD register field. */
453 #define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
454 /* The mask used to set the ALT_SDMMC_CTL_SEND_CCSD register field value. */
455 #define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
456 /* The mask used to clear the ALT_SDMMC_CTL_SEND_CCSD register field value. */
457 #define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
458 /* The reset value of the ALT_SDMMC_CTL_SEND_CCSD register field. */
459 #define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
460 /* Extracts the ALT_SDMMC_CTL_SEND_CCSD field value from a register. */
461 #define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
462 /* Produces a ALT_SDMMC_CTL_SEND_CCSD register field value suitable for setting the register. */
463 #define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
464 
465 /*
466  * Field : Send Auto Stop CCSD - send_auto_stop_ccsd
467  *
468  * Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd
469  * should not be set independent of send_ccsd. When set, SD/MMC automatically sends
470  * internally generated STOP command (CMD12) to CE-ATA device. After sending
471  * internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set
472  * and generates interrupt to host if Auto CommandDone interrupt is not masked.
473  * After sending the CCSD, SD/MMC automatically clears send_auto_stop_ccsd bit.
474  *
475  * Field Enumeration Values:
476  *
477  * Enum | Value | Description
478  * :---------------------------------------------|:------|:-------------------------------------------
479  * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT | 0x0 | Clear bit if SD/MMC does not reset the bit
480  * ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT | 0x1 | Send internally generated STOP.
481  *
482  * Field Access Macros:
483  *
484  */
485 /*
486  * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
487  *
488  * Clear bit if SD/MMC does not reset the bit
489  */
490 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
491 /*
492  * Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
493  *
494  * Send internally generated STOP.
495  */
496 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
497 
498 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
499 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
500 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
501 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
502 /* The width in bits of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
503 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
504 /* The mask used to set the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */
505 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
506 /* The mask used to clear the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value. */
507 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
508 /* The reset value of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field. */
509 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
510 /* Extracts the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD field value from a register. */
511 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
512 /* Produces a ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register. */
513 #define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
514 
515 /*
516  * Field : Ceata Device Interrupt Status - ceata_device_interrupt_status
517  *
518  * Software should appropriately write to this bit after power-on reset or any
519  * other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is
520  * disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software
521  * should set this bit.
522  *
523  * Field Enumeration Values:
524  *
525  * Enum | Value | Description
526  * :-------------------------------------------|:------|:----------------------------------------
527  * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD | 0x0 | Interrupts not enabled in CE-ATA device
528  * ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END | 0x1 | Interrupts are enabled in CE-ATA device
529  *
530  * Field Access Macros:
531  *
532  */
533 /*
534  * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
535  *
536  * Interrupts not enabled in CE-ATA device
537  */
538 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
539 /*
540  * Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
541  *
542  * Interrupts are enabled in CE-ATA device
543  */
544 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
545 
546 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
547 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
548 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
549 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
550 /* The width in bits of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
551 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
552 /* The mask used to set the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */
553 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
554 /* The mask used to clear the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value. */
555 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
556 /* The reset value of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field. */
557 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
558 /* Extracts the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT field value from a register. */
559 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
560 /* Produces a ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value suitable for setting the register. */
561 #define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
562 
563 /*
564  * Field : Use Internal DMAC - use_internal_dmac
565  *
566  * Enable and Disable Internal DMA transfers.
567  *
568  * Field Enumeration Values:
569  *
570  * Enum | Value | Description
571  * :---------------------------------------|:------|:--------------------------------------------
572  * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD | 0x0 | The host performs data transfers thru slave
573  * : | | interface
574  * ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END | 0x1 | Internal DMAC used for data transfer
575  *
576  * Field Access Macros:
577  *
578  */
579 /*
580  * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
581  *
582  * The host performs data transfers thru slave interface
583  */
584 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
585 /*
586  * Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
587  *
588  * Internal DMAC used for data transfer
589  */
590 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
591 
592 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
593 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
594 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
595 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
596 /* The width in bits of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
597 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
598 /* The mask used to set the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */
599 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
600 /* The mask used to clear the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value. */
601 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
602 /* The reset value of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field. */
603 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
604 /* Extracts the ALT_SDMMC_CTL_USE_INTERNAL_DMAC field value from a register. */
605 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
606 /* Produces a ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value suitable for setting the register. */
607 #define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
608 
609 #ifndef __ASSEMBLY__
610 /*
611  * WARNING: The C register and register group struct declarations are provided for
612  * convenience and illustrative purposes. They should, however, be used with
613  * caution as the C language standard provides no guarantees about the alignment or
614  * atomicity of device memory accesses. The recommended practice for writing
615  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
616  * alt_write_word() functions.
617  *
618  * The struct declaration for register ALT_SDMMC_CTL.
619  */
620 struct ALT_SDMMC_CTL_s
621 {
622  uint32_t controller_reset : 1; /* Controller Reset */
623  uint32_t fifo_reset : 1; /* FIFO Reset */
624  uint32_t dma_reset : 1; /* Dma Reset */
625  uint32_t : 1; /* *UNDEFINED* */
626  uint32_t int_enable : 1; /* Int Enable */
627  uint32_t : 1; /* *UNDEFINED* */
628  uint32_t read_wait : 1; /* Read Wait */
629  uint32_t send_irq_response : 1; /* Send Irq Response */
630  uint32_t abort_read_data : 1; /* Abort Read Data */
631  uint32_t send_ccsd : 1; /* Send CCSD */
632  uint32_t send_auto_stop_ccsd : 1; /* Send Auto Stop CCSD */
633  uint32_t ceata_device_interrupt_status : 1; /* Ceata Device Interrupt Status */
634  uint32_t : 13; /* *UNDEFINED* */
635  uint32_t use_internal_dmac : 1; /* Use Internal DMAC */
636  uint32_t : 6; /* *UNDEFINED* */
637 };
638 
639 /* The typedef declaration for register ALT_SDMMC_CTL. */
640 typedef volatile struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t;
641 #endif /* __ASSEMBLY__ */
642 
643 /* The byte offset of the ALT_SDMMC_CTL register from the beginning of the component. */
644 #define ALT_SDMMC_CTL_OFST 0x0
645 
646 /*
647  * Register : Power Enable Register - pwren
648  *
649  * Power on/off switch for card; once power is turned on, firmware should wait for
650  * regulator/switch ramp-up time before trying to initialize card.
651  *
652  * Register Layout
653  *
654  * Bits | Access | Reset | Description
655  * :-------|:-------|:------|:-------------
656  * [0] | RW | 0x0 | Power Enable
657  * [31:1] | ??? | 0x0 | *UNDEFINED*
658  *
659  */
660 /*
661  * Field : Power Enable - power_enable
662  *
663  * Power on/off switch for one card; for example, bit[0] controls the card. Once
664  * power is turned on, firmware should wait for regulator/switch ramp-up time
665  * before trying to initialize card.
666  *
667  * Field Enumeration Values:
668  *
669  * Enum | Value | Description
670  * :-------------------------------|:------|:------------
671  * ALT_SDMMC_PWREN_POWER_EN_E_OFF | 0x0 | Power Off
672  * ALT_SDMMC_PWREN_POWER_EN_E_ON | 0x1 | Power On
673  *
674  * Field Access Macros:
675  *
676  */
677 /*
678  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN
679  *
680  * Power Off
681  */
682 #define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
683 /*
684  * Enumerated value for register field ALT_SDMMC_PWREN_POWER_EN
685  *
686  * Power On
687  */
688 #define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
689 
690 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */
691 #define ALT_SDMMC_PWREN_POWER_EN_LSB 0
692 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PWREN_POWER_EN register field. */
693 #define ALT_SDMMC_PWREN_POWER_EN_MSB 0
694 /* The width in bits of the ALT_SDMMC_PWREN_POWER_EN register field. */
695 #define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
696 /* The mask used to set the ALT_SDMMC_PWREN_POWER_EN register field value. */
697 #define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
698 /* The mask used to clear the ALT_SDMMC_PWREN_POWER_EN register field value. */
699 #define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
700 /* The reset value of the ALT_SDMMC_PWREN_POWER_EN register field. */
701 #define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
702 /* Extracts the ALT_SDMMC_PWREN_POWER_EN field value from a register. */
703 #define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
704 /* Produces a ALT_SDMMC_PWREN_POWER_EN register field value suitable for setting the register. */
705 #define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
706 
707 #ifndef __ASSEMBLY__
708 /*
709  * WARNING: The C register and register group struct declarations are provided for
710  * convenience and illustrative purposes. They should, however, be used with
711  * caution as the C language standard provides no guarantees about the alignment or
712  * atomicity of device memory accesses. The recommended practice for writing
713  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
714  * alt_write_word() functions.
715  *
716  * The struct declaration for register ALT_SDMMC_PWREN.
717  */
718 struct ALT_SDMMC_PWREN_s
719 {
720  uint32_t power_enable : 1; /* Power Enable */
721  uint32_t : 31; /* *UNDEFINED* */
722 };
723 
724 /* The typedef declaration for register ALT_SDMMC_PWREN. */
725 typedef volatile struct ALT_SDMMC_PWREN_s ALT_SDMMC_PWREN_t;
726 #endif /* __ASSEMBLY__ */
727 
728 /* The byte offset of the ALT_SDMMC_PWREN register from the beginning of the component. */
729 #define ALT_SDMMC_PWREN_OFST 0x4
730 
731 /*
732  * Register : Clock Divider Register - clkdiv
733  *
734  * Divides Clock sdmmc_clk.
735  *
736  * Register Layout
737  *
738  * Bits | Access | Reset | Description
739  * :-------|:-------|:------|:--------------
740  * [7:0] | RW | 0x0 | Clk Divider 0
741  * [31:8] | ??? | 0x0 | *UNDEFINED*
742  *
743  */
744 /*
745  * Field : Clk Divider 0 - clk_divider0
746  *
747  * Clock divider-0 value. Clock division is 2*n. For example, value of 0 means
748  * divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2,
749  * value of ff means divide by 2*255 = 510, and so on.
750  *
751  * Field Access Macros:
752  *
753  */
754 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
755 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
756 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
757 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
758 /* The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
759 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
760 /* The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */
761 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
762 /* The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value. */
763 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
764 /* The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field. */
765 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
766 /* Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR0 field value from a register. */
767 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
768 /* Produces a ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value suitable for setting the register. */
769 #define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
770 
771 #ifndef __ASSEMBLY__
772 /*
773  * WARNING: The C register and register group struct declarations are provided for
774  * convenience and illustrative purposes. They should, however, be used with
775  * caution as the C language standard provides no guarantees about the alignment or
776  * atomicity of device memory accesses. The recommended practice for writing
777  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
778  * alt_write_word() functions.
779  *
780  * The struct declaration for register ALT_SDMMC_CLKDIV.
781  */
782 struct ALT_SDMMC_CLKDIV_s
783 {
784  uint32_t clk_divider0 : 8; /* Clk Divider 0 */
785  uint32_t : 24; /* *UNDEFINED* */
786 };
787 
788 /* The typedef declaration for register ALT_SDMMC_CLKDIV. */
789 typedef volatile struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t;
790 #endif /* __ASSEMBLY__ */
791 
792 /* The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component. */
793 #define ALT_SDMMC_CLKDIV_OFST 0x8
794 
795 /*
796  * Register : SD Clock Source Register - clksrc
797  *
798  * Selects among available clock dividers. The sdmmc_cclk_out is always from clock
799  * divider 0.
800  *
801  * Register Layout
802  *
803  * Bits | Access | Reset | Description
804  * :-------|:-------|:------|:-------------
805  * [1:0] | RW | 0x0 | Clock Source
806  * [31:2] | ??? | 0x0 | *UNDEFINED*
807  *
808  */
809 /*
810  * Field : Clock Source - clk_source
811  *
812  * Selects among available clock dividers. The SD/MMC module is configured with
813  * just one clock divider so this register should always be set to choose clkdiv0.
814  *
815  * Field Enumeration Values:
816  *
817  * Enum | Value | Description
818  * :-----------------------------------|:------|:----------------
819  * ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 | 0x0 | Clock divider 0
820  *
821  * Field Access Macros:
822  *
823  */
824 /*
825  * Enumerated value for register field ALT_SDMMC_CLKSRC_CLK_SRC
826  *
827  * Clock divider 0
828  */
829 #define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
830 
831 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
832 #define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
833 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
834 #define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 1
835 /* The width in bits of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
836 #define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 2
837 /* The mask used to set the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */
838 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0x00000003
839 /* The mask used to clear the ALT_SDMMC_CLKSRC_CLK_SRC register field value. */
840 #define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0xfffffffc
841 /* The reset value of the ALT_SDMMC_CLKSRC_CLK_SRC register field. */
842 #define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
843 /* Extracts the ALT_SDMMC_CLKSRC_CLK_SRC field value from a register. */
844 #define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0x00000003) >> 0)
845 /* Produces a ALT_SDMMC_CLKSRC_CLK_SRC register field value suitable for setting the register. */
846 #define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0x00000003)
847 
848 #ifndef __ASSEMBLY__
849 /*
850  * WARNING: The C register and register group struct declarations are provided for
851  * convenience and illustrative purposes. They should, however, be used with
852  * caution as the C language standard provides no guarantees about the alignment or
853  * atomicity of device memory accesses. The recommended practice for writing
854  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
855  * alt_write_word() functions.
856  *
857  * The struct declaration for register ALT_SDMMC_CLKSRC.
858  */
859 struct ALT_SDMMC_CLKSRC_s
860 {
861  uint32_t clk_source : 2; /* Clock Source */
862  uint32_t : 30; /* *UNDEFINED* */
863 };
864 
865 /* The typedef declaration for register ALT_SDMMC_CLKSRC. */
866 typedef volatile struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t;
867 #endif /* __ASSEMBLY__ */
868 
869 /* The byte offset of the ALT_SDMMC_CLKSRC register from the beginning of the component. */
870 #define ALT_SDMMC_CLKSRC_OFST 0xc
871 
872 /*
873  * Register : Clock Enable Register - clkena
874  *
875  * Controls external SD/MMC Clock Enable.
876  *
877  * Register Layout
878  *
879  * Bits | Access | Reset | Description
880  * :--------|:-------|:------|:---------------
881  * [0] | RW | 0x0 | Cclk Enable
882  * [15:1] | ??? | 0x0 | *UNDEFINED*
883  * [16] | RW | 0x0 | Cclk Low Power
884  * [31:17] | ??? | 0x0 | *UNDEFINED*
885  *
886  */
887 /*
888  * Field : Cclk Enable - cclk_enable
889  *
890  * Enables sdmmc_cclk_out.
891  *
892  * Field Enumeration Values:
893  *
894  * Enum | Value | Description
895  * :--------------------------------|:------|:---------------
896  * ALT_SDMMC_CLKENA_CCLK_EN_E_DISD | 0x0 | SD/MMC Disable
897  * ALT_SDMMC_CLKENA_CCLK_EN_E_END | 0x1 | SD/MMC Enable
898  *
899  * Field Access Macros:
900  *
901  */
902 /*
903  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
904  *
905  * SD/MMC Disable
906  */
907 #define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
908 /*
909  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
910  *
911  * SD/MMC Enable
912  */
913 #define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
914 
915 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
916 #define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
917 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
918 #define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
919 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
920 #define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
921 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_EN register field value. */
922 #define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
923 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_EN register field value. */
924 #define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
925 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_EN register field. */
926 #define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
927 /* Extracts the ALT_SDMMC_CLKENA_CCLK_EN field value from a register. */
928 #define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
929 /* Produces a ALT_SDMMC_CLKENA_CCLK_EN register field value suitable for setting the register. */
930 #define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
931 
932 /*
933  * Field : Cclk Low Power - cclk_low_power
934  *
935  * In low-power mode, stop sdmmc_cclk_out when card in IDLE (should be normally set
936  * to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected,
937  * clock should not be stopped).
938  *
939  * Field Enumeration Values:
940  *
941  * Enum | Value | Description
942  * :---------------------------------------|:------|:-------------------
943  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD | 0x0 | Non-low-power mode
944  * ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END | 0x1 | Low-power mode
945  *
946  * Field Access Macros:
947  *
948  */
949 /*
950  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
951  *
952  * Non-low-power mode
953  */
954 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
955 /*
956  * Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
957  *
958  * Low-power mode
959  */
960 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
961 
962 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
963 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
964 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
965 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
966 /* The width in bits of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
967 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
968 /* The mask used to set the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */
969 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
970 /* The mask used to clear the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value. */
971 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
972 /* The reset value of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field. */
973 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
974 /* Extracts the ALT_SDMMC_CLKENA_CCLK_LOW_POWER field value from a register. */
975 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
976 /* Produces a ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value suitable for setting the register. */
977 #define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
978 
979 #ifndef __ASSEMBLY__
980 /*
981  * WARNING: The C register and register group struct declarations are provided for
982  * convenience and illustrative purposes. They should, however, be used with
983  * caution as the C language standard provides no guarantees about the alignment or
984  * atomicity of device memory accesses. The recommended practice for writing
985  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
986  * alt_write_word() functions.
987  *
988  * The struct declaration for register ALT_SDMMC_CLKENA.
989  */
990 struct ALT_SDMMC_CLKENA_s
991 {
992  uint32_t cclk_enable : 1; /* Cclk Enable */
993  uint32_t : 15; /* *UNDEFINED* */
994  uint32_t cclk_low_power : 1; /* Cclk Low Power */
995  uint32_t : 15; /* *UNDEFINED* */
996 };
997 
998 /* The typedef declaration for register ALT_SDMMC_CLKENA. */
999 typedef volatile struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t;
1000 #endif /* __ASSEMBLY__ */
1001 
1002 /* The byte offset of the ALT_SDMMC_CLKENA register from the beginning of the component. */
1003 #define ALT_SDMMC_CLKENA_OFST 0x10
1004 
1005 /*
1006  * Register : Timeout Register - tmout
1007  *
1008  * Sets timeout values
1009  *
1010  * Register Layout
1011  *
1012  * Bits | Access | Reset | Description
1013  * :-------|:-------|:---------|:-----------------
1014  * [7:0] | RW | 0x40 | Response Timeout
1015  * [31:8] | RW | 0xffffff | Data Timeout
1016  *
1017  */
1018 /*
1019  * Field : Response Timeout - response_timeout
1020  *
1021  * Response timeout value. Value is in number of card output clocks sdmmc_cclk_out.
1022  *
1023  * Field Access Macros:
1024  *
1025  */
1026 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1027 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1028 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1029 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1030 /* The width in bits of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1031 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1032 /* The mask used to set the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */
1033 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1034 /* The mask used to clear the ALT_SDMMC_TMOUT_RESPONSE_TMO register field value. */
1035 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1036 /* The reset value of the ALT_SDMMC_TMOUT_RESPONSE_TMO register field. */
1037 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1038 /* Extracts the ALT_SDMMC_TMOUT_RESPONSE_TMO field value from a register. */
1039 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1040 /* Produces a ALT_SDMMC_TMOUT_RESPONSE_TMO register field value suitable for setting the register. */
1041 #define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1042 
1043 /*
1044  * Field : Data Timeout - data_timeout
1045  *
1046  * Value for card Data Read Timeout; same value also used for Data Starvation by
1047  * Host timeout. Value is in number of card output clocks sdmmc_cclk_out of
1048  * selected card.
1049  *
1050  * Field Access Macros:
1051  *
1052  */
1053 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1054 #define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1055 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1056 #define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1057 /* The width in bits of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1058 #define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1059 /* The mask used to set the ALT_SDMMC_TMOUT_DATA_TMO register field value. */
1060 #define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1061 /* The mask used to clear the ALT_SDMMC_TMOUT_DATA_TMO register field value. */
1062 #define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1063 /* The reset value of the ALT_SDMMC_TMOUT_DATA_TMO register field. */
1064 #define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1065 /* Extracts the ALT_SDMMC_TMOUT_DATA_TMO field value from a register. */
1066 #define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1067 /* Produces a ALT_SDMMC_TMOUT_DATA_TMO register field value suitable for setting the register. */
1068 #define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1069 
1070 #ifndef __ASSEMBLY__
1071 /*
1072  * WARNING: The C register and register group struct declarations are provided for
1073  * convenience and illustrative purposes. They should, however, be used with
1074  * caution as the C language standard provides no guarantees about the alignment or
1075  * atomicity of device memory accesses. The recommended practice for writing
1076  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1077  * alt_write_word() functions.
1078  *
1079  * The struct declaration for register ALT_SDMMC_TMOUT.
1080  */
1081 struct ALT_SDMMC_TMOUT_s
1082 {
1083  uint32_t response_timeout : 8; /* Response Timeout */
1084  uint32_t data_timeout : 24; /* Data Timeout */
1085 };
1086 
1087 /* The typedef declaration for register ALT_SDMMC_TMOUT. */
1088 typedef volatile struct ALT_SDMMC_TMOUT_s ALT_SDMMC_TMOUT_t;
1089 #endif /* __ASSEMBLY__ */
1090 
1091 /* The byte offset of the ALT_SDMMC_TMOUT register from the beginning of the component. */
1092 #define ALT_SDMMC_TMOUT_OFST 0x14
1093 
1094 /*
1095  * Register : Card Type Register - ctype
1096  *
1097  * Describes card formats.
1098  *
1099  * Register Layout
1100  *
1101  * Bits | Access | Reset | Description
1102  * :--------|:-------|:------|:-----------------------
1103  * [0] | RW | 0x0 | Card Width 1 or 4 Bits
1104  * [15:1] | ??? | 0x0 | *UNDEFINED*
1105  * [16] | RW | 0x0 | Card Width 8 Bit
1106  * [31:17] | ??? | 0x0 | *UNDEFINED*
1107  *
1108  */
1109 /*
1110  * Field : Card Width 1 or 4 Bits - card_width2
1111  *
1112  * Ignored if card_width1 is MODE8BIT.
1113  *
1114  * Field Enumeration Values:
1115  *
1116  * Enum | Value | Description
1117  * :--------------------------------------|:------|:------------
1118  * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT | 0x0 | 1-bit mode
1119  * ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT | 0x1 | 4-bit mode
1120  *
1121  * Field Access Macros:
1122  *
1123  */
1124 /*
1125  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2
1126  *
1127  * 1-bit mode
1128  */
1129 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1130 /*
1131  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH2
1132  *
1133  * 4-bit mode
1134  */
1135 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1136 
1137 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1138 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1139 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1140 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1141 /* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1142 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1143 /* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */
1144 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1145 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value. */
1146 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1147 /* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH2 register field. */
1148 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1149 /* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH2 field value from a register. */
1150 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1151 /* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH2 register field value suitable for setting the register. */
1152 #define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1153 
1154 /*
1155  * Field : Card Width 8 Bit - card_width1
1156  *
1157  * Indicates if card is 8 bit or othersize. If not 8-bit, card_width2 specifies the
1158  * width.
1159  *
1160  * Field Enumeration Values:
1161  *
1162  * Enum | Value | Description
1163  * :--------------------------------------|:------|:---------------
1164  * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT | 0x0 | Non 8-bit mode
1165  * ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT | 0x1 | 8-bit mode
1166  *
1167  * Field Access Macros:
1168  *
1169  */
1170 /*
1171  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1
1172  *
1173  * Non 8-bit mode
1174  */
1175 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1176 /*
1177  * Enumerated value for register field ALT_SDMMC_CTYPE_CARD_WIDTH1
1178  *
1179  * 8-bit mode
1180  */
1181 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1182 
1183 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1184 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1185 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1186 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1187 /* The width in bits of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1188 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1189 /* The mask used to set the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */
1190 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1191 /* The mask used to clear the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value. */
1192 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1193 /* The reset value of the ALT_SDMMC_CTYPE_CARD_WIDTH1 register field. */
1194 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1195 /* Extracts the ALT_SDMMC_CTYPE_CARD_WIDTH1 field value from a register. */
1196 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1197 /* Produces a ALT_SDMMC_CTYPE_CARD_WIDTH1 register field value suitable for setting the register. */
1198 #define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1199 
1200 #ifndef __ASSEMBLY__
1201 /*
1202  * WARNING: The C register and register group struct declarations are provided for
1203  * convenience and illustrative purposes. They should, however, be used with
1204  * caution as the C language standard provides no guarantees about the alignment or
1205  * atomicity of device memory accesses. The recommended practice for writing
1206  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1207  * alt_write_word() functions.
1208  *
1209  * The struct declaration for register ALT_SDMMC_CTYPE.
1210  */
1211 struct ALT_SDMMC_CTYPE_s
1212 {
1213  uint32_t card_width2 : 1; /* Card Width 1 or 4 Bits */
1214  uint32_t : 15; /* *UNDEFINED* */
1215  uint32_t card_width1 : 1; /* Card Width 8 Bit */
1216  uint32_t : 15; /* *UNDEFINED* */
1217 };
1218 
1219 /* The typedef declaration for register ALT_SDMMC_CTYPE. */
1220 typedef volatile struct ALT_SDMMC_CTYPE_s ALT_SDMMC_CTYPE_t;
1221 #endif /* __ASSEMBLY__ */
1222 
1223 /* The byte offset of the ALT_SDMMC_CTYPE register from the beginning of the component. */
1224 #define ALT_SDMMC_CTYPE_OFST 0x18
1225 
1226 /*
1227  * Register : Block Size Register - blksiz
1228  *
1229  * The Block Size.
1230  *
1231  * Register Layout
1232  *
1233  * Bits | Access | Reset | Description
1234  * :--------|:-------|:------|:------------
1235  * [15:0] | RW | 0x200 | Block Size
1236  * [31:16] | ??? | 0x0 | *UNDEFINED*
1237  *
1238  */
1239 /*
1240  * Field : Block Size - block_size
1241  *
1242  * The size of a block in bytes.
1243  *
1244  * Field Access Macros:
1245  *
1246  */
1247 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1248 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1249 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1250 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1251 /* The width in bits of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1252 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1253 /* The mask used to set the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
1254 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1255 /* The mask used to clear the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value. */
1256 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1257 /* The reset value of the ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field. */
1258 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1259 /* Extracts the ALT_SDMMC_BLKSIZ_BLOCK_SIZE field value from a register. */
1260 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1261 /* Produces a ALT_SDMMC_BLKSIZ_BLOCK_SIZE register field value suitable for setting the register. */
1262 #define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1263 
1264 #ifndef __ASSEMBLY__
1265 /*
1266  * WARNING: The C register and register group struct declarations are provided for
1267  * convenience and illustrative purposes. They should, however, be used with
1268  * caution as the C language standard provides no guarantees about the alignment or
1269  * atomicity of device memory accesses. The recommended practice for writing
1270  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1271  * alt_write_word() functions.
1272  *
1273  * The struct declaration for register ALT_SDMMC_BLKSIZ.
1274  */
1275 struct ALT_SDMMC_BLKSIZ_s
1276 {
1277  uint32_t block_size : 16; /* Block Size */
1278  uint32_t : 16; /* *UNDEFINED* */
1279 };
1280 
1281 /* The typedef declaration for register ALT_SDMMC_BLKSIZ. */
1282 typedef volatile struct ALT_SDMMC_BLKSIZ_s ALT_SDMMC_BLKSIZ_t;
1283 #endif /* __ASSEMBLY__ */
1284 
1285 /* The byte offset of the ALT_SDMMC_BLKSIZ register from the beginning of the component. */
1286 #define ALT_SDMMC_BLKSIZ_OFST 0x1c
1287 
1288 /*
1289  * Register : Byte Count Register - bytcnt
1290  *
1291  * The number of bytes to be transferred.
1292  *
1293  * Register Layout
1294  *
1295  * Bits | Access | Reset | Description
1296  * :-------|:-------|:------|:------------
1297  * [31:0] | RW | 0x200 | Byte Count
1298  *
1299  */
1300 /*
1301  * Field : Byte Count - byte_count
1302  *
1303  * This value should be an integer multiple of the Block Size for block transfers.
1304  * For undefined number of byte transfers, byte count should be set to 0. When byte
1305  * count is set to 0, it is responsibility of host to explicitly send stop/abort
1306  * command to terminate data transfer.
1307  *
1308  * Note: In SDIO mode, if a single transfer is greater than 4 bytes and non-DWORD-
1309  * aligned, the transfer should be broken where only the last transfer is non-
1310  * DWORD-aligned and less than 4 bytes. For example, if a transfer of 129 bytes
1311  * must occur, then the driver should start at least two transfers; one with 128
1312  * bytes and the other with 1 byte.
1313  *
1314  * Field Access Macros:
1315  *
1316  */
1317 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1318 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1319 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1320 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1321 /* The width in bits of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1322 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1323 /* The mask used to set the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
1324 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1325 /* The mask used to clear the ALT_SDMMC_BYTCNT_BYTE_COUNT register field value. */
1326 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1327 /* The reset value of the ALT_SDMMC_BYTCNT_BYTE_COUNT register field. */
1328 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1329 /* Extracts the ALT_SDMMC_BYTCNT_BYTE_COUNT field value from a register. */
1330 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1331 /* Produces a ALT_SDMMC_BYTCNT_BYTE_COUNT register field value suitable for setting the register. */
1332 #define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1333 
1334 #ifndef __ASSEMBLY__
1335 /*
1336  * WARNING: The C register and register group struct declarations are provided for
1337  * convenience and illustrative purposes. They should, however, be used with
1338  * caution as the C language standard provides no guarantees about the alignment or
1339  * atomicity of device memory accesses. The recommended practice for writing
1340  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1341  * alt_write_word() functions.
1342  *
1343  * The struct declaration for register ALT_SDMMC_BYTCNT.
1344  */
1345 struct ALT_SDMMC_BYTCNT_s
1346 {
1347  uint32_t byte_count : 32; /* Byte Count */
1348 };
1349 
1350 /* The typedef declaration for register ALT_SDMMC_BYTCNT. */
1351 typedef volatile struct ALT_SDMMC_BYTCNT_s ALT_SDMMC_BYTCNT_t;
1352 #endif /* __ASSEMBLY__ */
1353 
1354 /* The byte offset of the ALT_SDMMC_BYTCNT register from the beginning of the component. */
1355 #define ALT_SDMMC_BYTCNT_OFST 0x20
1356 
1357 /*
1358  * Register : Interrupt Mask Register - intmask
1359  *
1360  * Allows Masking of Various Interrupts
1361  *
1362  * Register Layout
1363  *
1364  * Bits | Access | Reset | Description
1365  * :--------|:-------|:------|:--------------------------------
1366  * [0] | RW | 0x0 | Card Detected
1367  * [1] | RW | 0x0 | Response Error
1368  * [2] | RW | 0x0 | Command Done
1369  * [3] | RW | 0x0 | Data Transfer Over
1370  * [4] | RW | 0x0 | Transmit FIFO Data Request
1371  * [5] | RW | 0x0 | Receive FIFO Data Request (
1372  * [6] | RW | 0x0 | Response CRC Error
1373  * [7] | RW | 0x0 | Data CRC Error
1374  * [8] | RW | 0x0 | Response Timeout
1375  * [9] | RW | 0x0 | Data Read Timeout
1376  * [10] | RW | 0x0 | Data Starvation Host Timeout
1377  * [11] | RW | 0x0 | FIFO Underrun Overrun Error
1378  * [12] | RW | 0x0 | Hardware Locked Write Error
1379  * [13] | RW | 0x0 | Start-bit Error
1380  * [14] | RW | 0x0 | Auto Command Done
1381  * [15] | RW | 0x0 | End-bit Error Read Write no CRC
1382  * [16] | RW | 0x0 | SDIO Interrupt Mask
1383  * [31:17] | ??? | 0x0 | *UNDEFINED*
1384  *
1385  */
1386 /*
1387  * Field : Card Detected - cd
1388  *
1389  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1390  * enables interrupt.
1391  *
1392  * Field Enumeration Values:
1393  *
1394  * Enum | Value | Description
1395  * :----------------------------|:------|:--------------------
1396  * ALT_SDMMC_INTMSK_CD_E_MSK | 0x0 | Card Detected Mask
1397  * ALT_SDMMC_INTMSK_CD_E_NOMSK | 0x1 | Card Detect No Mask
1398  *
1399  * Field Access Macros:
1400  *
1401  */
1402 /*
1403  * Enumerated value for register field ALT_SDMMC_INTMSK_CD
1404  *
1405  * Card Detected Mask
1406  */
1407 #define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1408 /*
1409  * Enumerated value for register field ALT_SDMMC_INTMSK_CD
1410  *
1411  * Card Detect No Mask
1412  */
1413 #define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1414 
1415 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CD register field. */
1416 #define ALT_SDMMC_INTMSK_CD_LSB 0
1417 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CD register field. */
1418 #define ALT_SDMMC_INTMSK_CD_MSB 0
1419 /* The width in bits of the ALT_SDMMC_INTMSK_CD register field. */
1420 #define ALT_SDMMC_INTMSK_CD_WIDTH 1
1421 /* The mask used to set the ALT_SDMMC_INTMSK_CD register field value. */
1422 #define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1423 /* The mask used to clear the ALT_SDMMC_INTMSK_CD register field value. */
1424 #define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1425 /* The reset value of the ALT_SDMMC_INTMSK_CD register field. */
1426 #define ALT_SDMMC_INTMSK_CD_RESET 0x0
1427 /* Extracts the ALT_SDMMC_INTMSK_CD field value from a register. */
1428 #define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1429 /* Produces a ALT_SDMMC_INTMSK_CD register field value suitable for setting the register. */
1430 #define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1431 
1432 /*
1433  * Field : Response Error - re
1434  *
1435  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1436  * enables interrupt.
1437  *
1438  * Field Enumeration Values:
1439  *
1440  * Enum | Value | Description
1441  * :----------------------------|:------|:-----------------------
1442  * ALT_SDMMC_INTMSK_RE_E_MSK | 0x0 | Response error Mask
1443  * ALT_SDMMC_INTMSK_RE_E_NOMSK | 0x1 | Response error No Mask
1444  *
1445  * Field Access Macros:
1446  *
1447  */
1448 /*
1449  * Enumerated value for register field ALT_SDMMC_INTMSK_RE
1450  *
1451  * Response error Mask
1452  */
1453 #define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1454 /*
1455  * Enumerated value for register field ALT_SDMMC_INTMSK_RE
1456  *
1457  * Response error No Mask
1458  */
1459 #define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1460 
1461 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RE register field. */
1462 #define ALT_SDMMC_INTMSK_RE_LSB 1
1463 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RE register field. */
1464 #define ALT_SDMMC_INTMSK_RE_MSB 1
1465 /* The width in bits of the ALT_SDMMC_INTMSK_RE register field. */
1466 #define ALT_SDMMC_INTMSK_RE_WIDTH 1
1467 /* The mask used to set the ALT_SDMMC_INTMSK_RE register field value. */
1468 #define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1469 /* The mask used to clear the ALT_SDMMC_INTMSK_RE register field value. */
1470 #define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1471 /* The reset value of the ALT_SDMMC_INTMSK_RE register field. */
1472 #define ALT_SDMMC_INTMSK_RE_RESET 0x0
1473 /* Extracts the ALT_SDMMC_INTMSK_RE field value from a register. */
1474 #define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1475 /* Produces a ALT_SDMMC_INTMSK_RE register field value suitable for setting the register. */
1476 #define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1477 
1478 /*
1479  * Field : Command Done - cmd
1480  *
1481  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1482  * enables interrupt.
1483  *
1484  * Field Enumeration Values:
1485  *
1486  * Enum | Value | Description
1487  * :-----------------------------|:------|:---------------------
1488  * ALT_SDMMC_INTMSK_CMD_E_MSK | 0x0 | Command Done Mask
1489  * ALT_SDMMC_INTMSK_CMD_E_NOMSK | 0x1 | Command Done No Mask
1490  *
1491  * Field Access Macros:
1492  *
1493  */
1494 /*
1495  * Enumerated value for register field ALT_SDMMC_INTMSK_CMD
1496  *
1497  * Command Done Mask
1498  */
1499 #define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1500 /*
1501  * Enumerated value for register field ALT_SDMMC_INTMSK_CMD
1502  *
1503  * Command Done No Mask
1504  */
1505 #define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1506 
1507 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CMD register field. */
1508 #define ALT_SDMMC_INTMSK_CMD_LSB 2
1509 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CMD register field. */
1510 #define ALT_SDMMC_INTMSK_CMD_MSB 2
1511 /* The width in bits of the ALT_SDMMC_INTMSK_CMD register field. */
1512 #define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1513 /* The mask used to set the ALT_SDMMC_INTMSK_CMD register field value. */
1514 #define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1515 /* The mask used to clear the ALT_SDMMC_INTMSK_CMD register field value. */
1516 #define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1517 /* The reset value of the ALT_SDMMC_INTMSK_CMD register field. */
1518 #define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1519 /* Extracts the ALT_SDMMC_INTMSK_CMD field value from a register. */
1520 #define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1521 /* Produces a ALT_SDMMC_INTMSK_CMD register field value suitable for setting the register. */
1522 #define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1523 
1524 /*
1525  * Field : Data Transfer Over - dto
1526  *
1527  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1528  * enables interrupt.
1529  *
1530  * Field Enumeration Values:
1531  *
1532  * Enum | Value | Description
1533  * :-----------------------------|:------|:---------------------------
1534  * ALT_SDMMC_INTMSK_DTO_E_MSK | 0x0 | Data transfer over Mask
1535  * ALT_SDMMC_INTMSK_DTO_E_NOMSK | 0x1 | Data transfer over No Mask
1536  *
1537  * Field Access Macros:
1538  *
1539  */
1540 /*
1541  * Enumerated value for register field ALT_SDMMC_INTMSK_DTO
1542  *
1543  * Data transfer over Mask
1544  */
1545 #define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1546 /*
1547  * Enumerated value for register field ALT_SDMMC_INTMSK_DTO
1548  *
1549  * Data transfer over No Mask
1550  */
1551 #define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1552 
1553 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DTO register field. */
1554 #define ALT_SDMMC_INTMSK_DTO_LSB 3
1555 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DTO register field. */
1556 #define ALT_SDMMC_INTMSK_DTO_MSB 3
1557 /* The width in bits of the ALT_SDMMC_INTMSK_DTO register field. */
1558 #define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1559 /* The mask used to set the ALT_SDMMC_INTMSK_DTO register field value. */
1560 #define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1561 /* The mask used to clear the ALT_SDMMC_INTMSK_DTO register field value. */
1562 #define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1563 /* The reset value of the ALT_SDMMC_INTMSK_DTO register field. */
1564 #define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1565 /* Extracts the ALT_SDMMC_INTMSK_DTO field value from a register. */
1566 #define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1567 /* Produces a ALT_SDMMC_INTMSK_DTO register field value suitable for setting the register. */
1568 #define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1569 
1570 /*
1571  * Field : Transmit FIFO Data Request - txdr
1572  *
1573  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1574  * enables interrupt.
1575  *
1576  * Field Enumeration Values:
1577  *
1578  * Enum | Value | Description
1579  * :------------------------------|:------|:-----------------------------------
1580  * ALT_SDMMC_INTMSK_TXDR_E_MSK | 0x0 | Transmit FIFO data request Mask
1581  * ALT_SDMMC_INTMSK_TXDR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask
1582  *
1583  * Field Access Macros:
1584  *
1585  */
1586 /*
1587  * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR
1588  *
1589  * Transmit FIFO data request Mask
1590  */
1591 #define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1592 /*
1593  * Enumerated value for register field ALT_SDMMC_INTMSK_TXDR
1594  *
1595  * Transmit FIFO data request No Mask
1596  */
1597 #define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1598 
1599 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */
1600 #define ALT_SDMMC_INTMSK_TXDR_LSB 4
1601 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_TXDR register field. */
1602 #define ALT_SDMMC_INTMSK_TXDR_MSB 4
1603 /* The width in bits of the ALT_SDMMC_INTMSK_TXDR register field. */
1604 #define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1605 /* The mask used to set the ALT_SDMMC_INTMSK_TXDR register field value. */
1606 #define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1607 /* The mask used to clear the ALT_SDMMC_INTMSK_TXDR register field value. */
1608 #define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1609 /* The reset value of the ALT_SDMMC_INTMSK_TXDR register field. */
1610 #define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1611 /* Extracts the ALT_SDMMC_INTMSK_TXDR field value from a register. */
1612 #define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1613 /* Produces a ALT_SDMMC_INTMSK_TXDR register field value suitable for setting the register. */
1614 #define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1615 
1616 /*
1617  * Field : Receive FIFO Data Request ( - rxdr
1618  *
1619  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1620  * enables interrupt.
1621  *
1622  * Field Enumeration Values:
1623  *
1624  * Enum | Value | Description
1625  * :------------------------------|:------|:----------------------------------
1626  * ALT_SDMMC_INTMSK_RXDR_E_MSK | 0x0 | Receive FIFO data request Mask
1627  * ALT_SDMMC_INTMSK_RXDR_E_NOMSK | 0x1 | Receive FIFO data request No Mask
1628  *
1629  * Field Access Macros:
1630  *
1631  */
1632 /*
1633  * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR
1634  *
1635  * Receive FIFO data request Mask
1636  */
1637 #define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1638 /*
1639  * Enumerated value for register field ALT_SDMMC_INTMSK_RXDR
1640  *
1641  * Receive FIFO data request No Mask
1642  */
1643 #define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1644 
1645 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */
1646 #define ALT_SDMMC_INTMSK_RXDR_LSB 5
1647 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RXDR register field. */
1648 #define ALT_SDMMC_INTMSK_RXDR_MSB 5
1649 /* The width in bits of the ALT_SDMMC_INTMSK_RXDR register field. */
1650 #define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1651 /* The mask used to set the ALT_SDMMC_INTMSK_RXDR register field value. */
1652 #define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1653 /* The mask used to clear the ALT_SDMMC_INTMSK_RXDR register field value. */
1654 #define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1655 /* The reset value of the ALT_SDMMC_INTMSK_RXDR register field. */
1656 #define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1657 /* Extracts the ALT_SDMMC_INTMSK_RXDR field value from a register. */
1658 #define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1659 /* Produces a ALT_SDMMC_INTMSK_RXDR register field value suitable for setting the register. */
1660 #define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1661 
1662 /*
1663  * Field : Response CRC Error - rcrc
1664  *
1665  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1666  * enables interrupt.
1667  *
1668  * Field Enumeration Values:
1669  *
1670  * Enum | Value | Description
1671  * :------------------------------|:------|:---------------------------
1672  * ALT_SDMMC_INTMSK_RCRC_E_MSK | 0x0 | Response CRC error Mask
1673  * ALT_SDMMC_INTMSK_RCRC_E_NOMSK | 0x1 | Response CRC error No Mask
1674  *
1675  * Field Access Macros:
1676  *
1677  */
1678 /*
1679  * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC
1680  *
1681  * Response CRC error Mask
1682  */
1683 #define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
1684 /*
1685  * Enumerated value for register field ALT_SDMMC_INTMSK_RCRC
1686  *
1687  * Response CRC error No Mask
1688  */
1689 #define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
1690 
1691 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */
1692 #define ALT_SDMMC_INTMSK_RCRC_LSB 6
1693 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RCRC register field. */
1694 #define ALT_SDMMC_INTMSK_RCRC_MSB 6
1695 /* The width in bits of the ALT_SDMMC_INTMSK_RCRC register field. */
1696 #define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
1697 /* The mask used to set the ALT_SDMMC_INTMSK_RCRC register field value. */
1698 #define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
1699 /* The mask used to clear the ALT_SDMMC_INTMSK_RCRC register field value. */
1700 #define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
1701 /* The reset value of the ALT_SDMMC_INTMSK_RCRC register field. */
1702 #define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
1703 /* Extracts the ALT_SDMMC_INTMSK_RCRC field value from a register. */
1704 #define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
1705 /* Produces a ALT_SDMMC_INTMSK_RCRC register field value suitable for setting the register. */
1706 #define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
1707 
1708 /*
1709  * Field : Data CRC Error - dcrc
1710  *
1711  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1712  * enables interrupt.
1713  *
1714  * Field Enumeration Values:
1715  *
1716  * Enum | Value | Description
1717  * :------------------------------|:------|:-----------------------
1718  * ALT_SDMMC_INTMSK_DCRC_E_MSK | 0x0 | Data CRC error Mask
1719  * ALT_SDMMC_INTMSK_DCRC_E_NOMSK | 0x1 | Data CRC error No Mask
1720  *
1721  * Field Access Macros:
1722  *
1723  */
1724 /*
1725  * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC
1726  *
1727  * Data CRC error Mask
1728  */
1729 #define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
1730 /*
1731  * Enumerated value for register field ALT_SDMMC_INTMSK_DCRC
1732  *
1733  * Data CRC error No Mask
1734  */
1735 #define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
1736 
1737 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */
1738 #define ALT_SDMMC_INTMSK_DCRC_LSB 7
1739 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DCRC register field. */
1740 #define ALT_SDMMC_INTMSK_DCRC_MSB 7
1741 /* The width in bits of the ALT_SDMMC_INTMSK_DCRC register field. */
1742 #define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
1743 /* The mask used to set the ALT_SDMMC_INTMSK_DCRC register field value. */
1744 #define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
1745 /* The mask used to clear the ALT_SDMMC_INTMSK_DCRC register field value. */
1746 #define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
1747 /* The reset value of the ALT_SDMMC_INTMSK_DCRC register field. */
1748 #define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
1749 /* Extracts the ALT_SDMMC_INTMSK_DCRC field value from a register. */
1750 #define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
1751 /* Produces a ALT_SDMMC_INTMSK_DCRC register field value suitable for setting the register. */
1752 #define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
1753 
1754 /*
1755  * Field : Response Timeout - rto
1756  *
1757  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1758  * enables interrupt.
1759  *
1760  * Field Enumeration Values:
1761  *
1762  * Enum | Value | Description
1763  * :-----------------------------|:------|:-------------------------
1764  * ALT_SDMMC_INTMSK_RTO_E_MSK | 0x0 | Response timeout Mask
1765  * ALT_SDMMC_INTMSK_RTO_E_NOMSK | 0x1 | Response timeout No Mask
1766  *
1767  * Field Access Macros:
1768  *
1769  */
1770 /*
1771  * Enumerated value for register field ALT_SDMMC_INTMSK_RTO
1772  *
1773  * Response timeout Mask
1774  */
1775 #define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
1776 /*
1777  * Enumerated value for register field ALT_SDMMC_INTMSK_RTO
1778  *
1779  * Response timeout No Mask
1780  */
1781 #define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
1782 
1783 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RTO register field. */
1784 #define ALT_SDMMC_INTMSK_RTO_LSB 8
1785 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RTO register field. */
1786 #define ALT_SDMMC_INTMSK_RTO_MSB 8
1787 /* The width in bits of the ALT_SDMMC_INTMSK_RTO register field. */
1788 #define ALT_SDMMC_INTMSK_RTO_WIDTH 1
1789 /* The mask used to set the ALT_SDMMC_INTMSK_RTO register field value. */
1790 #define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
1791 /* The mask used to clear the ALT_SDMMC_INTMSK_RTO register field value. */
1792 #define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
1793 /* The reset value of the ALT_SDMMC_INTMSK_RTO register field. */
1794 #define ALT_SDMMC_INTMSK_RTO_RESET 0x0
1795 /* Extracts the ALT_SDMMC_INTMSK_RTO field value from a register. */
1796 #define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
1797 /* Produces a ALT_SDMMC_INTMSK_RTO register field value suitable for setting the register. */
1798 #define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
1799 
1800 /*
1801  * Field : Data Read Timeout - drt
1802  *
1803  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1804  * enables interrupt.
1805  *
1806  * Field Enumeration Values:
1807  *
1808  * Enum | Value | Description
1809  * :-----------------------------|:------|:--------------------------
1810  * ALT_SDMMC_INTMSK_DRT_E_MSK | 0x0 | Data read timeout Mask
1811  * ALT_SDMMC_INTMSK_DRT_E_NOMSK | 0x1 | Data read timeout No Mask
1812  *
1813  * Field Access Macros:
1814  *
1815  */
1816 /*
1817  * Enumerated value for register field ALT_SDMMC_INTMSK_DRT
1818  *
1819  * Data read timeout Mask
1820  */
1821 #define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
1822 /*
1823  * Enumerated value for register field ALT_SDMMC_INTMSK_DRT
1824  *
1825  * Data read timeout No Mask
1826  */
1827 #define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
1828 
1829 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DRT register field. */
1830 #define ALT_SDMMC_INTMSK_DRT_LSB 9
1831 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DRT register field. */
1832 #define ALT_SDMMC_INTMSK_DRT_MSB 9
1833 /* The width in bits of the ALT_SDMMC_INTMSK_DRT register field. */
1834 #define ALT_SDMMC_INTMSK_DRT_WIDTH 1
1835 /* The mask used to set the ALT_SDMMC_INTMSK_DRT register field value. */
1836 #define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
1837 /* The mask used to clear the ALT_SDMMC_INTMSK_DRT register field value. */
1838 #define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
1839 /* The reset value of the ALT_SDMMC_INTMSK_DRT register field. */
1840 #define ALT_SDMMC_INTMSK_DRT_RESET 0x0
1841 /* Extracts the ALT_SDMMC_INTMSK_DRT field value from a register. */
1842 #define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
1843 /* Produces a ALT_SDMMC_INTMSK_DRT register field value suitable for setting the register. */
1844 #define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
1845 
1846 /*
1847  * Field : Data Starvation Host Timeout - hto
1848  *
1849  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1850  * enables interrupt.
1851  *
1852  * Field Enumeration Values:
1853  *
1854  * Enum | Value | Description
1855  * :-----------------------------|:------|:----------------------------------------
1856  * ALT_SDMMC_INTMSK_HTO_E_MSK | 0x0 | Data starvation by host timeout Mask
1857  * ALT_SDMMC_INTMSK_HTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask
1858  *
1859  * Field Access Macros:
1860  *
1861  */
1862 /*
1863  * Enumerated value for register field ALT_SDMMC_INTMSK_HTO
1864  *
1865  * Data starvation by host timeout Mask
1866  */
1867 #define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
1868 /*
1869  * Enumerated value for register field ALT_SDMMC_INTMSK_HTO
1870  *
1871  * Data starvation by host timeout No Mask
1872  */
1873 #define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
1874 
1875 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HTO register field. */
1876 #define ALT_SDMMC_INTMSK_HTO_LSB 10
1877 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HTO register field. */
1878 #define ALT_SDMMC_INTMSK_HTO_MSB 10
1879 /* The width in bits of the ALT_SDMMC_INTMSK_HTO register field. */
1880 #define ALT_SDMMC_INTMSK_HTO_WIDTH 1
1881 /* The mask used to set the ALT_SDMMC_INTMSK_HTO register field value. */
1882 #define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
1883 /* The mask used to clear the ALT_SDMMC_INTMSK_HTO register field value. */
1884 #define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
1885 /* The reset value of the ALT_SDMMC_INTMSK_HTO register field. */
1886 #define ALT_SDMMC_INTMSK_HTO_RESET 0x0
1887 /* Extracts the ALT_SDMMC_INTMSK_HTO field value from a register. */
1888 #define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
1889 /* Produces a ALT_SDMMC_INTMSK_HTO register field value suitable for setting the register. */
1890 #define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
1891 
1892 /*
1893  * Field : FIFO Underrun Overrun Error - frun
1894  *
1895  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1896  * enables interrupt.
1897  *
1898  * Field Enumeration Values:
1899  *
1900  * Enum | Value | Description
1901  * :------------------------------|:------|:------------------------------------
1902  * ALT_SDMMC_INTMSK_FRUN_E_MSK | 0x0 | FIFO underrun/overrun error Mask
1903  * ALT_SDMMC_INTMSK_FRUN_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask
1904  *
1905  * Field Access Macros:
1906  *
1907  */
1908 /*
1909  * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN
1910  *
1911  * FIFO underrun/overrun error Mask
1912  */
1913 #define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
1914 /*
1915  * Enumerated value for register field ALT_SDMMC_INTMSK_FRUN
1916  *
1917  * FIFO underrun/overrun error No Mask
1918  */
1919 #define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
1920 
1921 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */
1922 #define ALT_SDMMC_INTMSK_FRUN_LSB 11
1923 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_FRUN register field. */
1924 #define ALT_SDMMC_INTMSK_FRUN_MSB 11
1925 /* The width in bits of the ALT_SDMMC_INTMSK_FRUN register field. */
1926 #define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
1927 /* The mask used to set the ALT_SDMMC_INTMSK_FRUN register field value. */
1928 #define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
1929 /* The mask used to clear the ALT_SDMMC_INTMSK_FRUN register field value. */
1930 #define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
1931 /* The reset value of the ALT_SDMMC_INTMSK_FRUN register field. */
1932 #define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
1933 /* Extracts the ALT_SDMMC_INTMSK_FRUN field value from a register. */
1934 #define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
1935 /* Produces a ALT_SDMMC_INTMSK_FRUN register field value suitable for setting the register. */
1936 #define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
1937 
1938 /*
1939  * Field : Hardware Locked Write Error - hle
1940  *
1941  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1942  * enables interrupt.
1943  *
1944  * Field Enumeration Values:
1945  *
1946  * Enum | Value | Description
1947  * :-----------------------------|:------|:------------------------------------
1948  * ALT_SDMMC_INTMSK_HLE_E_MSK | 0x0 | Hardware locked write error Mask
1949  * ALT_SDMMC_INTMSK_HLE_E_NOMSK | 0x1 | Hardware locked write error No Mask
1950  *
1951  * Field Access Macros:
1952  *
1953  */
1954 /*
1955  * Enumerated value for register field ALT_SDMMC_INTMSK_HLE
1956  *
1957  * Hardware locked write error Mask
1958  */
1959 #define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
1960 /*
1961  * Enumerated value for register field ALT_SDMMC_INTMSK_HLE
1962  *
1963  * Hardware locked write error No Mask
1964  */
1965 #define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
1966 
1967 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HLE register field. */
1968 #define ALT_SDMMC_INTMSK_HLE_LSB 12
1969 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HLE register field. */
1970 #define ALT_SDMMC_INTMSK_HLE_MSB 12
1971 /* The width in bits of the ALT_SDMMC_INTMSK_HLE register field. */
1972 #define ALT_SDMMC_INTMSK_HLE_WIDTH 1
1973 /* The mask used to set the ALT_SDMMC_INTMSK_HLE register field value. */
1974 #define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
1975 /* The mask used to clear the ALT_SDMMC_INTMSK_HLE register field value. */
1976 #define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
1977 /* The reset value of the ALT_SDMMC_INTMSK_HLE register field. */
1978 #define ALT_SDMMC_INTMSK_HLE_RESET 0x0
1979 /* Extracts the ALT_SDMMC_INTMSK_HLE field value from a register. */
1980 #define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
1981 /* Produces a ALT_SDMMC_INTMSK_HLE register field value suitable for setting the register. */
1982 #define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
1983 
1984 /*
1985  * Field : Start-bit Error - sbe
1986  *
1987  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
1988  * enables interrupt.
1989  *
1990  * Field Enumeration Values:
1991  *
1992  * Enum | Value | Description
1993  * :-----------------------------|:------|:------------------------
1994  * ALT_SDMMC_INTMSK_SBE_E_MSK | 0x0 | Start-bit error Mask
1995  * ALT_SDMMC_INTMSK_SBE_E_NOMSK | 0x1 | Start-bit error No Mask
1996  *
1997  * Field Access Macros:
1998  *
1999  */
2000 /*
2001  * Enumerated value for register field ALT_SDMMC_INTMSK_SBE
2002  *
2003  * Start-bit error Mask
2004  */
2005 #define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2006 /*
2007  * Enumerated value for register field ALT_SDMMC_INTMSK_SBE
2008  *
2009  * Start-bit error No Mask
2010  */
2011 #define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2012 
2013 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SBE register field. */
2014 #define ALT_SDMMC_INTMSK_SBE_LSB 13
2015 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SBE register field. */
2016 #define ALT_SDMMC_INTMSK_SBE_MSB 13
2017 /* The width in bits of the ALT_SDMMC_INTMSK_SBE register field. */
2018 #define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2019 /* The mask used to set the ALT_SDMMC_INTMSK_SBE register field value. */
2020 #define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2021 /* The mask used to clear the ALT_SDMMC_INTMSK_SBE register field value. */
2022 #define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2023 /* The reset value of the ALT_SDMMC_INTMSK_SBE register field. */
2024 #define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2025 /* Extracts the ALT_SDMMC_INTMSK_SBE field value from a register. */
2026 #define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2027 /* Produces a ALT_SDMMC_INTMSK_SBE register field value suitable for setting the register. */
2028 #define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2029 
2030 /*
2031  * Field : Auto Command Done - acd
2032  *
2033  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2034  * enables interrupt.
2035  *
2036  * Field Enumeration Values:
2037  *
2038  * Enum | Value | Description
2039  * :-----------------------------|:------|:--------------------------
2040  * ALT_SDMMC_INTMSK_ACD_E_MSK | 0x0 | Auto command done Mask
2041  * ALT_SDMMC_INTMSK_ACD_E_NOMSK | 0x1 | Auto command done No Mask
2042  *
2043  * Field Access Macros:
2044  *
2045  */
2046 /*
2047  * Enumerated value for register field ALT_SDMMC_INTMSK_ACD
2048  *
2049  * Auto command done Mask
2050  */
2051 #define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2052 /*
2053  * Enumerated value for register field ALT_SDMMC_INTMSK_ACD
2054  *
2055  * Auto command done No Mask
2056  */
2057 #define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2058 
2059 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_ACD register field. */
2060 #define ALT_SDMMC_INTMSK_ACD_LSB 14
2061 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_ACD register field. */
2062 #define ALT_SDMMC_INTMSK_ACD_MSB 14
2063 /* The width in bits of the ALT_SDMMC_INTMSK_ACD register field. */
2064 #define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2065 /* The mask used to set the ALT_SDMMC_INTMSK_ACD register field value. */
2066 #define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2067 /* The mask used to clear the ALT_SDMMC_INTMSK_ACD register field value. */
2068 #define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2069 /* The reset value of the ALT_SDMMC_INTMSK_ACD register field. */
2070 #define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2071 /* Extracts the ALT_SDMMC_INTMSK_ACD field value from a register. */
2072 #define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2073 /* Produces a ALT_SDMMC_INTMSK_ACD register field value suitable for setting the register. */
2074 #define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2075 
2076 /*
2077  * Field : End-bit Error Read Write no CRC - ebe
2078  *
2079  * Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1
2080  * enables interrupt.
2081  *
2082  * Field Enumeration Values:
2083  *
2084  * Enum | Value | Description
2085  * :-----------------------------|:------|:----------------------
2086  * ALT_SDMMC_INTMSK_EBE_E_MSK | 0x0 | End-bit error Mask
2087  * ALT_SDMMC_INTMSK_EBE_E_NOMSK | 0x1 | End-bit error No Mask
2088  *
2089  * Field Access Macros:
2090  *
2091  */
2092 /*
2093  * Enumerated value for register field ALT_SDMMC_INTMSK_EBE
2094  *
2095  * End-bit error Mask
2096  */
2097 #define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2098 /*
2099  * Enumerated value for register field ALT_SDMMC_INTMSK_EBE
2100  *
2101  * End-bit error No Mask
2102  */
2103 #define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2104 
2105 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_EBE register field. */
2106 #define ALT_SDMMC_INTMSK_EBE_LSB 15
2107 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_EBE register field. */
2108 #define ALT_SDMMC_INTMSK_EBE_MSB 15
2109 /* The width in bits of the ALT_SDMMC_INTMSK_EBE register field. */
2110 #define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2111 /* The mask used to set the ALT_SDMMC_INTMSK_EBE register field value. */
2112 #define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2113 /* The mask used to clear the ALT_SDMMC_INTMSK_EBE register field value. */
2114 #define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2115 /* The reset value of the ALT_SDMMC_INTMSK_EBE register field. */
2116 #define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2117 /* Extracts the ALT_SDMMC_INTMSK_EBE field value from a register. */
2118 #define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2119 /* Produces a ALT_SDMMC_INTMSK_EBE register field value suitable for setting the register. */
2120 #define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2121 
2122 /*
2123  * Field : SDIO Interrupt Mask - sdio_int_mask
2124  *
2125  * In current application, MMC-Ver3.3 only Bit 16 of this field is used. Bits 17 to
2126  * 31 are unused and return 0
2127  *
2128  * Field Enumeration Values:
2129  *
2130  * Enum | Value | Description
2131  * :-------------------------------------|:------|:-----------------------------
2132  * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD | 0x0 | SDIO Mask Interrupt Disabled
2133  * ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END | 0x1 | SDIO Interrupt Enabled
2134  *
2135  * Field Access Macros:
2136  *
2137  */
2138 /*
2139  * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK
2140  *
2141  * SDIO Mask Interrupt Disabled
2142  */
2143 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2144 /*
2145  * Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK
2146  *
2147  * SDIO Interrupt Enabled
2148  */
2149 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2150 
2151 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2152 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2153 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2154 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 16
2155 /* The width in bits of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2156 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 1
2157 /* The mask used to set the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */
2158 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0x00010000
2159 /* The mask used to clear the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value. */
2160 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0xfffeffff
2161 /* The reset value of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field. */
2162 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2163 /* Extracts the ALT_SDMMC_INTMSK_SDIO_INT_MSK field value from a register. */
2164 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0x00010000) >> 16)
2165 /* Produces a ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value suitable for setting the register. */
2166 #define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0x00010000)
2167 
2168 #ifndef __ASSEMBLY__
2169 /*
2170  * WARNING: The C register and register group struct declarations are provided for
2171  * convenience and illustrative purposes. They should, however, be used with
2172  * caution as the C language standard provides no guarantees about the alignment or
2173  * atomicity of device memory accesses. The recommended practice for writing
2174  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2175  * alt_write_word() functions.
2176  *
2177  * The struct declaration for register ALT_SDMMC_INTMSK.
2178  */
2179 struct ALT_SDMMC_INTMSK_s
2180 {
2181  uint32_t cd : 1; /* Card Detected */
2182  uint32_t re : 1; /* Response Error */
2183  uint32_t cmd : 1; /* Command Done */
2184  uint32_t dto : 1; /* Data Transfer Over */
2185  uint32_t txdr : 1; /* Transmit FIFO Data Request */
2186  uint32_t rxdr : 1; /* Receive FIFO Data Request ( */
2187  uint32_t rcrc : 1; /* Response CRC Error */
2188  uint32_t dcrc : 1; /* Data CRC Error */
2189  uint32_t rto : 1; /* Response Timeout */
2190  uint32_t drt : 1; /* Data Read Timeout */
2191  uint32_t hto : 1; /* Data Starvation Host Timeout */
2192  uint32_t frun : 1; /* FIFO Underrun Overrun Error */
2193  uint32_t hle : 1; /* Hardware Locked Write Error */
2194  uint32_t sbe : 1; /* Start-bit Error */
2195  uint32_t acd : 1; /* Auto Command Done */
2196  uint32_t ebe : 1; /* End-bit Error Read Write no CRC */
2197  uint32_t sdio_int_mask : 1; /* SDIO Interrupt Mask */
2198  uint32_t : 15; /* *UNDEFINED* */
2199 };
2200 
2201 /* The typedef declaration for register ALT_SDMMC_INTMSK. */
2202 typedef volatile struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t;
2203 #endif /* __ASSEMBLY__ */
2204 
2205 /* The byte offset of the ALT_SDMMC_INTMSK register from the beginning of the component. */
2206 #define ALT_SDMMC_INTMSK_OFST 0x24
2207 
2208 /*
2209  * Register : Command Argument Register - cmdarg
2210  *
2211  * See Field Description.
2212  *
2213  * Register Layout
2214  *
2215  * Bits | Access | Reset | Description
2216  * :-------|:-------|:------|:------------
2217  * [31:0] | RW | 0x0 | Cmd Arg
2218  *
2219  */
2220 /*
2221  * Field : Cmd Arg - cmd_arg
2222  *
2223  * Values indicates command argument to be passed to card.
2224  *
2225  * Field Access Macros:
2226  *
2227  */
2228 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2229 #define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2230 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2231 #define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2232 /* The width in bits of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2233 #define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2234 /* The mask used to set the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
2235 #define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2236 /* The mask used to clear the ALT_SDMMC_CMDARG_CMD_ARG register field value. */
2237 #define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2238 /* The reset value of the ALT_SDMMC_CMDARG_CMD_ARG register field. */
2239 #define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2240 /* Extracts the ALT_SDMMC_CMDARG_CMD_ARG field value from a register. */
2241 #define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2242 /* Produces a ALT_SDMMC_CMDARG_CMD_ARG register field value suitable for setting the register. */
2243 #define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2244 
2245 #ifndef __ASSEMBLY__
2246 /*
2247  * WARNING: The C register and register group struct declarations are provided for
2248  * convenience and illustrative purposes. They should, however, be used with
2249  * caution as the C language standard provides no guarantees about the alignment or
2250  * atomicity of device memory accesses. The recommended practice for writing
2251  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2252  * alt_write_word() functions.
2253  *
2254  * The struct declaration for register ALT_SDMMC_CMDARG.
2255  */
2256 struct ALT_SDMMC_CMDARG_s
2257 {
2258  uint32_t cmd_arg : 32; /* Cmd Arg */
2259 };
2260 
2261 /* The typedef declaration for register ALT_SDMMC_CMDARG. */
2262 typedef volatile struct ALT_SDMMC_CMDARG_s ALT_SDMMC_CMDARG_t;
2263 #endif /* __ASSEMBLY__ */
2264 
2265 /* The byte offset of the ALT_SDMMC_CMDARG register from the beginning of the component. */
2266 #define ALT_SDMMC_CMDARG_OFST 0x28
2267 
2268 /*
2269  * Register : Command Register - cmd
2270  *
2271  * This register issues various commands.
2272  *
2273  * Register Layout
2274  *
2275  * Bits | Access | Reset | Description
2276  * :--------|:-------|:------|:-----------------------------------
2277  * [5:0] | RW | 0x0 | Cmd Index
2278  * [6] | RW | 0x0 | Response Expect
2279  * [7] | RW | 0x0 | Response Length
2280  * [8] | RW | 0x0 | Check Response Crc
2281  * [9] | RW | 0x0 | Data Transfer Expected
2282  * [10] | RW | 0x0 | Read Write
2283  * [11] | RW | 0x0 | Transfer Mode
2284  * [12] | RW | 0x0 | Send Auto Stop
2285  * [13] | RW | 0x0 | Wait Previous Data Complete
2286  * [14] | RW | 0x0 | Stop Abort Cmd
2287  * [15] | RW | 0x0 | Send Initialization
2288  * [20:16] | RW | 0x0 | Card Number
2289  * [21] | RW | 0x0 | Update Clock Registers Only
2290  * [22] | RW | 0x0 | Read CE-ATA Device
2291  * [23] | RW | 0x0 | Command Completion Signal Expected
2292  * [24] | RW | 0x0 | Enable Boot
2293  * [25] | RW | 0x0 | Expect Boot Ack
2294  * [26] | RW | 0x0 | Disable Boot
2295  * [27] | RW | 0x0 | Boot Mode
2296  * [28] | RW | 0x0 | Volt Switch
2297  * [29] | RW | 0x1 | Use Hold Reg
2298  * [30] | ??? | 0x0 | *UNDEFINED*
2299  * [31] | RW | 0x0 | Start Cmd
2300  *
2301  */
2302 /*
2303  * Field : Cmd Index - cmd_index
2304  *
2305  * Tracks the command index number. Values from 0-31.
2306  *
2307  * Field Access Macros:
2308  *
2309  */
2310 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2311 #define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2312 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2313 #define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2314 /* The width in bits of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2315 #define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2316 /* The mask used to set the ALT_SDMMC_CMD_CMD_INDEX register field value. */
2317 #define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2318 /* The mask used to clear the ALT_SDMMC_CMD_CMD_INDEX register field value. */
2319 #define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2320 /* The reset value of the ALT_SDMMC_CMD_CMD_INDEX register field. */
2321 #define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2322 /* Extracts the ALT_SDMMC_CMD_CMD_INDEX field value from a register. */
2323 #define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2324 /* Produces a ALT_SDMMC_CMD_CMD_INDEX register field value suitable for setting the register. */
2325 #define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2326 
2327 /*
2328  * Field : Response Expect - response_expect
2329  *
2330  * Response expected from card.
2331  *
2332  * Field Enumeration Values:
2333  *
2334  * Enum | Value | Description
2335  * :---------------------------------------|:------|:-------------------------------
2336  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP | 0x0 | No response expected from card
2337  * ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP | 0x1 | Response expected from card
2338  *
2339  * Field Access Macros:
2340  *
2341  */
2342 /*
2343  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
2344  *
2345  * No response expected from card
2346  */
2347 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x0
2348 /*
2349  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
2350  *
2351  * Response expected from card
2352  */
2353 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x1
2354 
2355 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2356 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2357 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2358 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2359 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2360 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2361 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
2362 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2363 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value. */
2364 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2365 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field. */
2366 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2367 /* Extracts the ALT_SDMMC_CMD_RESPONSE_EXPECT field value from a register. */
2368 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2369 /* Produces a ALT_SDMMC_CMD_RESPONSE_EXPECT register field value suitable for setting the register. */
2370 #define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2371 
2372 /*
2373  * Field : Response Length - response_length
2374  *
2375  * Provides long and short response
2376  *
2377  * Field Enumeration Values:
2378  *
2379  * Enum | Value | Description
2380  * :-----------------------------------|:------|:----------------------------------
2381  * ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT | 0x0 | Short response expected from card
2382  * ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG | 0x1 | Long response expected from card
2383  *
2384  * Field Access Macros:
2385  *
2386  */
2387 /*
2388  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
2389  *
2390  * Short response expected from card
2391  */
2392 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2393 /*
2394  * Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
2395  *
2396  * Long response expected from card
2397  */
2398 #define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2399 
2400 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2401 #define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2402 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2403 #define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2404 /* The width in bits of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2405 #define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2406 /* The mask used to set the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */
2407 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2408 /* The mask used to clear the ALT_SDMMC_CMD_RESPONSE_LEN register field value. */
2409 #define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2410 /* The reset value of the ALT_SDMMC_CMD_RESPONSE_LEN register field. */
2411 #define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2412 /* Extracts the ALT_SDMMC_CMD_RESPONSE_LEN field value from a register. */
2413 #define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2414 /* Produces a ALT_SDMMC_CMD_RESPONSE_LEN register field value suitable for setting the register. */
2415 #define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2416 
2417 /*
2418  * Field : Check Response Crc - check_response_crc
2419  *
2420  * Some of command responses do not return valid CRC bits. Software should disable
2421  * CRC checks for those commands in order to disable CRC checking by controller.
2422  *
2423  * Field Enumeration Values:
2424  *
2425  * Enum | Value | Description
2426  * :-----------------------------------------|:------|:--------------------------
2427  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK | 0x0 | Do not check response CRC
2428  * ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK | 0x1 | Check Response CRC
2429  *
2430  * Field Access Macros:
2431  *
2432  */
2433 /*
2434  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
2435  *
2436  * Do not check response CRC
2437  */
2438 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2439 /*
2440  * Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
2441  *
2442  * Check Response CRC
2443  */
2444 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2445 
2446 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2447 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2448 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2449 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2450 /* The width in bits of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2451 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2452 /* The mask used to set the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
2453 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2454 /* The mask used to clear the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value. */
2455 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2456 /* The reset value of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field. */
2457 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2458 /* Extracts the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC field value from a register. */
2459 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2460 /* Produces a ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value suitable for setting the register. */
2461 #define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2462 
2463 /*
2464  * Field : Data Transfer Expected - data_expected
2465  *
2466  * Set decision on data transfer expecetd or not.
2467  *
2468  * Field Enumeration Values:
2469  *
2470  * Enum | Value | Description
2471  * :-------------------------------------------|:------|:---------------------------------------
2472  * ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP | 0x0 | No data transfer expected (read/write)
2473  * ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP | 0x1 | Data transfer expected (read/write)
2474  *
2475  * Field Access Macros:
2476  *
2477  */
2478 /*
2479  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
2480  *
2481  * No data transfer expected (read/write)
2482  */
2483 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2484 /*
2485  * Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
2486  *
2487  * Data transfer expected (read/write)
2488  */
2489 #define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2490 
2491 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2492 #define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2493 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2494 #define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2495 /* The width in bits of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2496 #define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2497 /* The mask used to set the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
2498 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2499 /* The mask used to clear the ALT_SDMMC_CMD_DATA_EXPECTED register field value. */
2500 #define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2501 /* The reset value of the ALT_SDMMC_CMD_DATA_EXPECTED register field. */
2502 #define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2503 /* Extracts the ALT_SDMMC_CMD_DATA_EXPECTED field value from a register. */
2504 #define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2505 /* Produces a ALT_SDMMC_CMD_DATA_EXPECTED register field value suitable for setting the register. */
2506 #define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2507 
2508 /*
2509  * Field : Read Write - read_write
2510  *
2511  * Read/Write from card. Don't care if no data transfer expected.
2512  *
2513  * Field Enumeration Values:
2514  *
2515  * Enum | Value | Description
2516  * :-------------------------|:------|:---------------
2517  * ALT_SDMMC_CMD_RD_WR_E_RD | 0x0 | Read from card
2518  * ALT_SDMMC_CMD_RD_WR_E_WR | 0x1 | Write to card
2519  *
2520  * Field Access Macros:
2521  *
2522  */
2523 /*
2524  * Enumerated value for register field ALT_SDMMC_CMD_RD_WR
2525  *
2526  * Read from card
2527  */
2528 #define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2529 /*
2530  * Enumerated value for register field ALT_SDMMC_CMD_RD_WR
2531  *
2532  * Write to card
2533  */
2534 #define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2535 
2536 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_WR register field. */
2537 #define ALT_SDMMC_CMD_RD_WR_LSB 10
2538 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_WR register field. */
2539 #define ALT_SDMMC_CMD_RD_WR_MSB 10
2540 /* The width in bits of the ALT_SDMMC_CMD_RD_WR register field. */
2541 #define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2542 /* The mask used to set the ALT_SDMMC_CMD_RD_WR register field value. */
2543 #define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2544 /* The mask used to clear the ALT_SDMMC_CMD_RD_WR register field value. */
2545 #define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2546 /* The reset value of the ALT_SDMMC_CMD_RD_WR register field. */
2547 #define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2548 /* Extracts the ALT_SDMMC_CMD_RD_WR field value from a register. */
2549 #define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2550 /* Produces a ALT_SDMMC_CMD_RD_WR register field value suitable for setting the register. */
2551 #define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2552 
2553 /*
2554  * Field : Transfer Mode - transfer_mode
2555  *
2556  * Block transfer command. Don't care if no data expected
2557  *
2558  * Field Enumeration Values:
2559  *
2560  * Enum | Value | Description
2561  * :----------------------------|:------|:-----------------------------
2562  * ALT_SDMMC_CMD_TFR_MOD_E_BLK | 0x0 | Block data transfer command
2563  * ALT_SDMMC_CMD_TFR_MOD_E_STR | 0x1 | Stream data transfer command
2564  *
2565  * Field Access Macros:
2566  *
2567  */
2568 /*
2569  * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
2570  *
2571  * Block data transfer command
2572  */
2573 #define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2574 /*
2575  * Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
2576  *
2577  * Stream data transfer command
2578  */
2579 #define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2580 
2581 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */
2582 #define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2583 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_TFR_MOD register field. */
2584 #define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2585 /* The width in bits of the ALT_SDMMC_CMD_TFR_MOD register field. */
2586 #define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2587 /* The mask used to set the ALT_SDMMC_CMD_TFR_MOD register field value. */
2588 #define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2589 /* The mask used to clear the ALT_SDMMC_CMD_TFR_MOD register field value. */
2590 #define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2591 /* The reset value of the ALT_SDMMC_CMD_TFR_MOD register field. */
2592 #define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2593 /* Extracts the ALT_SDMMC_CMD_TFR_MOD field value from a register. */
2594 #define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2595 /* Produces a ALT_SDMMC_CMD_TFR_MOD register field value suitable for setting the register. */
2596 #define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2597 
2598 /*
2599  * Field : Send Auto Stop - send_auto_stop
2600  *
2601  * When set, SD/MMC sends stop command to SD_MMC_CEATA cards at end of data
2602  * transfer. Determine the following:
2603  *
2604  * * -when send_auto_stop bit should be set, since some data transfers do not
2605  * need explicit stop commands. *-open-ended transfers that software should
2606  * explicitly send to stop command.
2607  *
2608  * Additionally, when resume is sent to resume- suspended memory access of SD-Combo
2609  * card, bit should be set correctly if suspended data transfer needs
2610  * send_auto_stop. Don't care if no data expected from card.
2611  *
2612  * Field Enumeration Values:
2613  *
2614  * Enum | Value | Description
2615  * :--------------------------------------|:------|:---------------------------------------------
2616  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND | 0x0 | No stop command sent at end of data transfer
2617  * ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND | 0x1 | Send stop command at end of data transfer
2618  *
2619  * Field Access Macros:
2620  *
2621  */
2622 /*
2623  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
2624  *
2625  * No stop command sent at end of data transfer
2626  */
2627 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2628 /*
2629  * Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
2630  *
2631  * Send stop command at end of data transfer
2632  */
2633 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2634 
2635 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2636 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2637 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2638 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2639 /* The width in bits of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2640 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2641 /* The mask used to set the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
2642 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2643 /* The mask used to clear the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value. */
2644 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2645 /* The reset value of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field. */
2646 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2647 /* Extracts the ALT_SDMMC_CMD_SEND_AUTO_STOP field value from a register. */
2648 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2649 /* Produces a ALT_SDMMC_CMD_SEND_AUTO_STOP register field value suitable for setting the register. */
2650 #define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
2651 
2652 /*
2653  * Field : Wait Previous Data Complete - wait_prvdata_complete
2654  *
2655  * Determines when command is sent. The send command at once option is typically
2656  * used to query status of card during data transfer or to stop current data
2657  * transfer.
2658  *
2659  * Field Enumeration Values:
2660  *
2661  * Enum | Value | Description
2662  * :---------------------------------------------|:------|:-------------------------------------------
2663  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT | 0x0 | Send command at once
2664  * ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT | 0x1 | Wait for previous data transfer completion
2665  *
2666  * Field Access Macros:
2667  *
2668  */
2669 /*
2670  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
2671  *
2672  * Send command at once
2673  */
2674 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
2675 /*
2676  * Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
2677  *
2678  * Wait for previous data transfer completion
2679  */
2680 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
2681 
2682 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
2683 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
2684 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
2685 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
2686 /* The width in bits of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
2687 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
2688 /* The mask used to set the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
2689 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
2690 /* The mask used to clear the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value. */
2691 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
2692 /* The reset value of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field. */
2693 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
2694 /* Extracts the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE field value from a register. */
2695 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
2696 /* Produces a ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value suitable for setting the register. */
2697 #define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
2698 
2699 /*
2700  * Field : Stop Abort Cmd - stop_abort_cmd
2701  *
2702  * When open-ended or predefined data transfer is in progress, and host issues stop
2703  * or abort command to stop data transfer, bit should be set so that command/data
2704  * state-machines of CIU can return correctly to idle state. This is also
2705  * applicable for Boot mode transfers. To Abort boot mode, this bit should be set
2706  * along with CMD[26] = disable_boot.
2707  *
2708  * Note: If abort is sent to function-number currently selected or not in data-
2709  * transfer mode, then bit should be set to 0.
2710  *
2711  * Field Enumeration Values:
2712  *
2713  * Enum | Value | Description
2714  * :----------------------------------------|:------|:-------------------------------------------------
2715  * ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT | 0x0 | Don't stop or abort command to stop current data
2716  * : | | transfer in progress
2717  * ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT | 0x1 | Stop or Abort command, intended to stop current
2718  * : | | data transfer in progress
2719  *
2720  * Field Access Macros:
2721  *
2722  */
2723 /*
2724  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
2725  *
2726  * Don't stop or abort command to stop current data transfer in progress
2727  */
2728 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
2729 /*
2730  * Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
2731  *
2732  * Stop or Abort command, intended to stop current data transfer in progress
2733  */
2734 #define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
2735 
2736 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
2737 #define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
2738 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
2739 #define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
2740 /* The width in bits of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
2741 #define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
2742 /* The mask used to set the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */
2743 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
2744 /* The mask used to clear the ALT_SDMMC_CMD_STOP_ABT_CMD register field value. */
2745 #define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
2746 /* The reset value of the ALT_SDMMC_CMD_STOP_ABT_CMD register field. */
2747 #define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
2748 /* Extracts the ALT_SDMMC_CMD_STOP_ABT_CMD field value from a register. */
2749 #define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
2750 /* Produces a ALT_SDMMC_CMD_STOP_ABT_CMD register field value suitable for setting the register. */
2751 #define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
2752 
2753 /*
2754  * Field : Send Initialization - send_initialization
2755  *
2756  * After power on, 80 clocks must be sent to the card for initialization before
2757  * sending any commands to card. Bit should be set while sending first command to
2758  * card so that controller will initialize clocks before sending command to card.
2759  * This bit should not be set for either of the boot modes (alternate or
2760  * mandatory).
2761  *
2762  * Field Enumeration Values:
2763  *
2764  * Enum | Value | Description
2765  * :-------------------------------------------|:------|:-------------------------------------------------
2766  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT | 0x0 | Do not send initialization sequence (80 clocks
2767  * : | | of 1) before sending this command
2768  * ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT | 0x1 | Send initialization sequence before sending this
2769  * : | | command
2770  *
2771  * Field Access Macros:
2772  *
2773  */
2774 /*
2775  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
2776  *
2777  * Do not send initialization sequence (80 clocks of 1) before sending this command
2778  */
2779 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
2780 /*
2781  * Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
2782  *
2783  * Send initialization sequence before sending this command
2784  */
2785 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
2786 
2787 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
2788 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
2789 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
2790 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
2791 /* The width in bits of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
2792 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
2793 /* The mask used to set the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
2794 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
2795 /* The mask used to clear the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value. */
2796 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
2797 /* The reset value of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field. */
2798 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
2799 /* Extracts the ALT_SDMMC_CMD_SEND_INITIALIZATION field value from a register. */
2800 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
2801 /* Produces a ALT_SDMMC_CMD_SEND_INITIALIZATION register field value suitable for setting the register. */
2802 #define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
2803 
2804 /*
2805  * Field : Card Number - card_number
2806  *
2807  * Card number in use must always be 0.
2808  *
2809  * Field Access Macros:
2810  *
2811  */
2812 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
2813 #define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
2814 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
2815 #define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
2816 /* The width in bits of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
2817 #define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
2818 /* The mask used to set the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
2819 #define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
2820 /* The mask used to clear the ALT_SDMMC_CMD_CARD_NUMBER register field value. */
2821 #define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
2822 /* The reset value of the ALT_SDMMC_CMD_CARD_NUMBER register field. */
2823 #define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
2824 /* Extracts the ALT_SDMMC_CMD_CARD_NUMBER field value from a register. */
2825 #define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
2826 /* Produces a ALT_SDMMC_CMD_CARD_NUMBER register field value suitable for setting the register. */
2827 #define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
2828 
2829 /*
2830  * Field : Update Clock Registers Only - update_clock_registers_only
2831  *
2832  * Following register values transferred into card clock domain: CLKDIV, CLRSRC,
2833  * CLKENA.
2834  *
2835  * Changes card clocks (change frequency, truncate off or on, and set low-frequency
2836  * mode); provided in order to change clock frequency or stop clock without having
2837  * to send command to cards. During normal command sequence, when
2838  * update_clock_registers_only = 0, following control registers are transferred
2839  * from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new
2840  * register values for new command sequence to card(s). When bit is set, there are
2841  * no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
2842  *
2843  * Field Enumeration Values:
2844  *
2845  * Enum | Value | Description
2846  * :-------------------------------------------------|:------|:-------------------------------------------------
2847  * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD | 0x0 | Normal command sequence
2848  * ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG | 0x1 | Do not send commands, just update clock register
2849  * : | | value into card clock domain
2850  *
2851  * Field Access Macros:
2852  *
2853  */
2854 /*
2855  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
2856  *
2857  * Normal command sequence
2858  */
2859 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
2860 /*
2861  * Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
2862  *
2863  * Do not send commands, just update clock register value into card clock domain
2864  */
2865 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
2866 
2867 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
2868 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
2869 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
2870 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
2871 /* The width in bits of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
2872 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
2873 /* The mask used to set the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */
2874 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
2875 /* The mask used to clear the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value. */
2876 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
2877 /* The reset value of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field. */
2878 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
2879 /* Extracts the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY field value from a register. */
2880 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
2881 /* Produces a ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value suitable for setting the register. */
2882 #define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
2883 
2884 /*
2885  * Field : Read CE-ATA Device - read_ceata_device
2886  *
2887  * Software should set this bit to indicate that CE-ATA device is being accessed
2888  * for read transfer. This bit is used to disable read data timeout indication
2889  * while performing CE-ATA read transfers. Maximum value of I/O transmission delay
2890  * can be no less than 10 seconds. SD/MMC should not indicate read data timeout
2891  * while waiting for data from CE-ATA device.
2892  *
2893  * Field Enumeration Values:
2894  *
2895  * Enum | Value | Description
2896  * :-------------------------------------|:------|:----------------------------------------------
2897  * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD | 0x0 | Host is not performing read access (RW_REG or
2898  * : | | RW_BLK) towards CE-ATA device
2899  * ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD | 0x1 | Host is performing read access (RW_REG or
2900  * : | | RW_BLK) towards CE-ATA device
2901  *
2902  * Field Access Macros:
2903  *
2904  */
2905 /*
2906  * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
2907  *
2908  * Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device
2909  */
2910 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
2911 /*
2912  * Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
2913  *
2914  * Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device
2915  */
2916 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
2917 
2918 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
2919 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
2920 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
2921 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
2922 /* The width in bits of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
2923 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
2924 /* The mask used to set the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */
2925 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
2926 /* The mask used to clear the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value. */
2927 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
2928 /* The reset value of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field. */
2929 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
2930 /* Extracts the ALT_SDMMC_CMD_RD_CEATA_DEVICE field value from a register. */
2931 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
2932 /* Produces a ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value suitable for setting the register. */
2933 #define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
2934 
2935 /*
2936  * Field : Command Completion Signal Expected - ccs_expected
2937  *
2938  * If the command expects Command Completion Signal (CCS) from the CE-ATA device,
2939  * the software should set this control bit. SD/MMC sets Data Transfer Over (DTO)
2940  * bit in RINTSTS register and generates interrupt to host if Data Transfer Over
2941  * interrupt is not masked.
2942  *
2943  * Field Enumeration Values:
2944  *
2945  * Enum | Value | Description
2946  * :----------------------------------|:------|:------------------------------------------------
2947  * ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD | 0x0 | Interrupts are not enabled in CE-ATA device
2948  * : | | (nIEN = 1 in ATA control register), or command
2949  * : | | does not expect CCS from device
2950  * ALT_SDMMC_CMD_CCS_EXPECTED_E_END | 0x1 | Interrupts are enabled in CE-ATA device (nIEN =
2951  * : | | 0), and RW_BLK command expects command
2952  * : | | completion signal from CE-ATA device
2953  *
2954  * Field Access Macros:
2955  *
2956  */
2957 /*
2958  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
2959  *
2960  * Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
2961  * or command does not expect CCS from device
2962  */
2963 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
2964 /*
2965  * Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
2966  *
2967  * Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
2968  * command completion signal from CE-ATA device
2969  */
2970 #define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
2971 
2972 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
2973 #define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
2974 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
2975 #define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
2976 /* The width in bits of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
2977 #define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
2978 /* The mask used to set the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
2979 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
2980 /* The mask used to clear the ALT_SDMMC_CMD_CCS_EXPECTED register field value. */
2981 #define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
2982 /* The reset value of the ALT_SDMMC_CMD_CCS_EXPECTED register field. */
2983 #define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
2984 /* Extracts the ALT_SDMMC_CMD_CCS_EXPECTED field value from a register. */
2985 #define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
2986 /* Produces a ALT_SDMMC_CMD_CCS_EXPECTED register field value suitable for setting the register. */
2987 #define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
2988 
2989 /*
2990  * Field : Enable Boot - enable_boot
2991  *
2992  * This bit should be set only for mandatory boot mode. When Software sets this bit
2993  * along with start_cmd, CIU starts the boot sequence for the corresponding card by
2994  * asserting the CMD line low. Do NOT set disable_boot and enable_boot together
2995  *
2996  * Field Enumeration Values:
2997  *
2998  * Enum | Value | Description
2999  * :-----------------------------|:------|:-------------
3000  * ALT_SDMMC_CMD_EN_BOOT_E_DISD | 0x0 | Disable Boot
3001  * ALT_SDMMC_CMD_EN_BOOT_E_END | 0x1 | Enable Boot
3002  *
3003  * Field Access Macros:
3004  *
3005  */
3006 /*
3007  * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
3008  *
3009  * Disable Boot
3010  */
3011 #define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3012 /*
3013  * Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
3014  *
3015  * Enable Boot
3016  */
3017 #define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3018 
3019 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */
3020 #define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3021 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EN_BOOT register field. */
3022 #define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3023 /* The width in bits of the ALT_SDMMC_CMD_EN_BOOT register field. */
3024 #define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3025 /* The mask used to set the ALT_SDMMC_CMD_EN_BOOT register field value. */
3026 #define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3027 /* The mask used to clear the ALT_SDMMC_CMD_EN_BOOT register field value. */
3028 #define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3029 /* The reset value of the ALT_SDMMC_CMD_EN_BOOT register field. */
3030 #define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3031 /* Extracts the ALT_SDMMC_CMD_EN_BOOT field value from a register. */
3032 #define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3033 /* Produces a ALT_SDMMC_CMD_EN_BOOT register field value suitable for setting the register. */
3034 #define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3035 
3036 /*
3037  * Field : Expect Boot Ack - expect_boot_ack
3038  *
3039  * When Software sets this bit along with enable_boot, CIU expects a boot
3040  * acknowledge start pattern of 0-1-0 from the selected card.
3041  *
3042  * Field Enumeration Values:
3043  *
3044  * Enum | Value | Description
3045  * :------------------------------------------|:------|:----------------
3046  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK | 0x0 | No Boot ACK
3047  * ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK | 0x1 | Expect Boot ACK
3048  *
3049  * Field Access Macros:
3050  *
3051  */
3052 /*
3053  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
3054  *
3055  * No Boot ACK
3056  */
3057 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3058 /*
3059  * Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
3060  *
3061  * Expect Boot ACK
3062  */
3063 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3064 
3065 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3066 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3067 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3068 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3069 /* The width in bits of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3070 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3071 /* The mask used to set the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
3072 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3073 /* The mask used to clear the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value. */
3074 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3075 /* The reset value of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field. */
3076 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3077 /* Extracts the ALT_SDMMC_CMD_EXPECT_BOOT_ACK field value from a register. */
3078 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3079 /* Produces a ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value suitable for setting the register. */
3080 #define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3081 
3082 /*
3083  * Field : Disable Boot - disable_boot
3084  *
3085  * When software sets this bit along with start_cmd, CIU terminates the boot
3086  * operation. Do NOT set disable_boot and enable_boot together.
3087  *
3088  * Field Enumeration Values:
3089  *
3090  * Enum | Value | Description
3091  * :------------------------------------|:------|:--------------------
3092  * ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT | 0x0 | Boot not Terminated
3093  * ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT | 0x1 | Terminate Boot
3094  *
3095  * Field Access Macros:
3096  *
3097  */
3098 /*
3099  * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
3100  *
3101  * Boot not Terminated
3102  */
3103 #define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3104 /*
3105  * Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
3106  *
3107  * Terminate Boot
3108  */
3109 #define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3110 
3111 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3112 #define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3113 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3114 #define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3115 /* The width in bits of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3116 #define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3117 /* The mask used to set the ALT_SDMMC_CMD_DIS_BOOT register field value. */
3118 #define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3119 /* The mask used to clear the ALT_SDMMC_CMD_DIS_BOOT register field value. */
3120 #define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3121 /* The reset value of the ALT_SDMMC_CMD_DIS_BOOT register field. */
3122 #define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3123 /* Extracts the ALT_SDMMC_CMD_DIS_BOOT field value from a register. */
3124 #define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3125 /* Produces a ALT_SDMMC_CMD_DIS_BOOT register field value suitable for setting the register. */
3126 #define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3127 
3128 /*
3129  * Field : Boot Mode - boot_mode
3130  *
3131  * Type of Boot Mode.
3132  *
3133  * Field Enumeration Values:
3134  *
3135  * Enum | Value | Description
3136  * :-----------------------------------|:------|:-------------------------
3137  * ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY | 0x0 | Mandatory Boot Operation
3138  * ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE | 0x1 | Alternate Boot Operation
3139  *
3140  * Field Access Macros:
3141  *
3142  */
3143 /*
3144  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
3145  *
3146  * Mandatory Boot Operation
3147  */
3148 #define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3149 /*
3150  * Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
3151  *
3152  * Alternate Boot Operation
3153  */
3154 #define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3155 
3156 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3157 #define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3158 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3159 #define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3160 /* The width in bits of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3161 #define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3162 /* The mask used to set the ALT_SDMMC_CMD_BOOT_MOD register field value. */
3163 #define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3164 /* The mask used to clear the ALT_SDMMC_CMD_BOOT_MOD register field value. */
3165 #define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3166 /* The reset value of the ALT_SDMMC_CMD_BOOT_MOD register field. */
3167 #define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3168 /* Extracts the ALT_SDMMC_CMD_BOOT_MOD field value from a register. */
3169 #define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3170 /* Produces a ALT_SDMMC_CMD_BOOT_MOD register field value suitable for setting the register. */
3171 #define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3172 
3173 /*
3174  * Field : Volt Switch - volt_switch
3175  *
3176  * Voltage switch bit. When set must be set for CMD11 only.
3177  *
3178  * Field Enumeration Values:
3179  *
3180  * Enum | Value | Description
3181  * :-------------------------------------|:------|:-------------------------------
3182  * ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW | 0x0 | No voltage switching - default
3183  * ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW | 0x1 | Voltage switching enabled
3184  *
3185  * Field Access Macros:
3186  *
3187  */
3188 /*
3189  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
3190  *
3191  * No voltage switching - default
3192  */
3193 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3194 /*
3195  * Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
3196  *
3197  * Voltage switching enabled
3198  */
3199 #define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3200 
3201 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3202 #define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3203 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3204 #define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3205 /* The width in bits of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3206 #define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3207 /* The mask used to set the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
3208 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3209 /* The mask used to clear the ALT_SDMMC_CMD_VOLT_SWITCH register field value. */
3210 #define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3211 /* The reset value of the ALT_SDMMC_CMD_VOLT_SWITCH register field. */
3212 #define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3213 /* Extracts the ALT_SDMMC_CMD_VOLT_SWITCH field value from a register. */
3214 #define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3215 /* Produces a ALT_SDMMC_CMD_VOLT_SWITCH register field value suitable for setting the register. */
3216 #define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3217 
3218 /*
3219  * Field : Use Hold Reg - use_hold_reg
3220  *
3221  * Set to one for SDR12 and SDR25 (with non-zero phase-shifted cclk_in_drv); zero
3222  * phase shift is not allowed in these modes.
3223  *
3224  * * Set to 1'b0 for SDR50, SDR104, and DDR50 (with zero phase-shifted
3225  * cclk_in_drv).
3226  *
3227  * * Set to 1'b1 for SDR50, SDR104, and DDR50 (with non-zero phase-shifted
3228  * cclk_in_drv).
3229  *
3230  * Field Enumeration Values:
3231  *
3232  * Enum | Value | Description
3233  * :--------------------------------------|:------|:-------------------------------------------
3234  * ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS | 0x0 | CMD and DATA sent to card bypassing HOLD
3235  * : | | Register
3236  * ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS | 0x1 | CMD and DATA sent to card through the HOLD
3237  * : | | Register
3238  *
3239  * Field Access Macros:
3240  *
3241  */
3242 /*
3243  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
3244  *
3245  * CMD and DATA sent to card bypassing HOLD Register
3246  */
3247 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3248 /*
3249  * Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
3250  *
3251  * CMD and DATA sent to card through the HOLD Register
3252  */
3253 #define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3254 
3255 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3256 #define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3257 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3258 #define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3259 /* The width in bits of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3260 #define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3261 /* The mask used to set the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
3262 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3263 /* The mask used to clear the ALT_SDMMC_CMD_USE_HOLD_REG register field value. */
3264 #define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3265 /* The reset value of the ALT_SDMMC_CMD_USE_HOLD_REG register field. */
3266 #define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3267 /* Extracts the ALT_SDMMC_CMD_USE_HOLD_REG field value from a register. */
3268 #define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3269 /* Produces a ALT_SDMMC_CMD_USE_HOLD_REG register field value suitable for setting the register. */
3270 #define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3271 
3272 /*
3273  * Field : Start Cmd - start_cmd
3274  *
3275  * Once command is taken by CIU, bit is cleared. If Start Cmd issued host should
3276  * not attempt to write to any command registers. If write is attempted, hardware
3277  * lock error is set in raw interrupt register. Once command is sent and response
3278  * is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt
3279  * register.
3280  *
3281  * Field Enumeration Values:
3282  *
3283  * Enum | Value | Description
3284  * :----------------------------------|:------|:-----------------
3285  * ALT_SDMMC_CMD_START_CMD_E_NOSTART | 0x0 | No Start Cmd
3286  * ALT_SDMMC_CMD_START_CMD_E_START | 0x1 | Start Cmd Issued
3287  *
3288  * Field Access Macros:
3289  *
3290  */
3291 /*
3292  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
3293  *
3294  * No Start Cmd
3295  */
3296 #define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3297 /*
3298  * Enumerated value for register field ALT_SDMMC_CMD_START_CMD
3299  *
3300  * Start Cmd Issued
3301  */
3302 #define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3303 
3304 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
3305 #define ALT_SDMMC_CMD_START_CMD_LSB 31
3306 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_START_CMD register field. */
3307 #define ALT_SDMMC_CMD_START_CMD_MSB 31
3308 /* The width in bits of the ALT_SDMMC_CMD_START_CMD register field. */
3309 #define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3310 /* The mask used to set the ALT_SDMMC_CMD_START_CMD register field value. */
3311 #define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3312 /* The mask used to clear the ALT_SDMMC_CMD_START_CMD register field value. */
3313 #define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3314 /* The reset value of the ALT_SDMMC_CMD_START_CMD register field. */
3315 #define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3316 /* Extracts the ALT_SDMMC_CMD_START_CMD field value from a register. */
3317 #define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3318 /* Produces a ALT_SDMMC_CMD_START_CMD register field value suitable for setting the register. */
3319 #define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3320 
3321 #ifndef __ASSEMBLY__
3322 /*
3323  * WARNING: The C register and register group struct declarations are provided for
3324  * convenience and illustrative purposes. They should, however, be used with
3325  * caution as the C language standard provides no guarantees about the alignment or
3326  * atomicity of device memory accesses. The recommended practice for writing
3327  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3328  * alt_write_word() functions.
3329  *
3330  * The struct declaration for register ALT_SDMMC_CMD.
3331  */
3332 struct ALT_SDMMC_CMD_s
3333 {
3334  uint32_t cmd_index : 6; /* Cmd Index */
3335  uint32_t response_expect : 1; /* Response Expect */
3336  uint32_t response_length : 1; /* Response Length */
3337  uint32_t check_response_crc : 1; /* Check Response Crc */
3338  uint32_t data_expected : 1; /* Data Transfer Expected */
3339  uint32_t read_write : 1; /* Read Write */
3340  uint32_t transfer_mode : 1; /* Transfer Mode */
3341  uint32_t send_auto_stop : 1; /* Send Auto Stop */
3342  uint32_t wait_prvdata_complete : 1; /* Wait Previous Data Complete */
3343  uint32_t stop_abort_cmd : 1; /* Stop Abort Cmd */
3344  uint32_t send_initialization : 1; /* Send Initialization */
3345  uint32_t card_number : 5; /* Card Number */
3346  uint32_t update_clock_registers_only : 1; /* Update Clock Registers Only */
3347  uint32_t read_ceata_device : 1; /* Read CE-ATA Device */
3348  uint32_t ccs_expected : 1; /* Command Completion Signal Expected */
3349  uint32_t enable_boot : 1; /* Enable Boot */
3350  uint32_t expect_boot_ack : 1; /* Expect Boot Ack */
3351  uint32_t disable_boot : 1; /* Disable Boot */
3352  uint32_t boot_mode : 1; /* Boot Mode */
3353  uint32_t volt_switch : 1; /* Volt Switch */
3354  uint32_t use_hold_reg : 1; /* Use Hold Reg */
3355  uint32_t : 1; /* *UNDEFINED* */
3356  uint32_t start_cmd : 1; /* Start Cmd */
3357 };
3358 
3359 /* The typedef declaration for register ALT_SDMMC_CMD. */
3360 typedef volatile struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t;
3361 #endif /* __ASSEMBLY__ */
3362 
3363 /* The byte offset of the ALT_SDMMC_CMD register from the beginning of the component. */
3364 #define ALT_SDMMC_CMD_OFST 0x2c
3365 
3366 /*
3367  * Register : Response Register 0 - resp0
3368  *
3369  * Preserves previous command.
3370  *
3371  * Register Layout
3372  *
3373  * Bits | Access | Reset | Description
3374  * :-------|:-------|:------|:------------
3375  * [31:0] | R | 0x0 | Response 0
3376  *
3377  */
3378 /*
3379  * Field : Response 0 - response0
3380  *
3381  * Bit[31:0] of response.
3382  *
3383  * Field Access Macros:
3384  *
3385  */
3386 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3387 #define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3388 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3389 #define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3390 /* The width in bits of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3391 #define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3392 /* The mask used to set the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
3393 #define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3394 /* The mask used to clear the ALT_SDMMC_RESP0_RESPONSE0 register field value. */
3395 #define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3396 /* The reset value of the ALT_SDMMC_RESP0_RESPONSE0 register field. */
3397 #define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3398 /* Extracts the ALT_SDMMC_RESP0_RESPONSE0 field value from a register. */
3399 #define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3400 /* Produces a ALT_SDMMC_RESP0_RESPONSE0 register field value suitable for setting the register. */
3401 #define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3402 
3403 #ifndef __ASSEMBLY__
3404 /*
3405  * WARNING: The C register and register group struct declarations are provided for
3406  * convenience and illustrative purposes. They should, however, be used with
3407  * caution as the C language standard provides no guarantees about the alignment or
3408  * atomicity of device memory accesses. The recommended practice for writing
3409  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3410  * alt_write_word() functions.
3411  *
3412  * The struct declaration for register ALT_SDMMC_RESP0.
3413  */
3414 struct ALT_SDMMC_RESP0_s
3415 {
3416  const uint32_t response0 : 32; /* Response 0 */
3417 };
3418 
3419 /* The typedef declaration for register ALT_SDMMC_RESP0. */
3420 typedef volatile struct ALT_SDMMC_RESP0_s ALT_SDMMC_RESP0_t;
3421 #endif /* __ASSEMBLY__ */
3422 
3423 /* The byte offset of the ALT_SDMMC_RESP0 register from the beginning of the component. */
3424 #define ALT_SDMMC_RESP0_OFST 0x30
3425 
3426 /*
3427  * Register : Response Register 1 - resp1
3428  *
3429  * Register Layout
3430  *
3431  * Bits | Access | Reset | Description
3432  * :-------|:-------|:------|:------------
3433  * [31:0] | R | 0x0 | Response 1
3434  *
3435  */
3436 /*
3437  * Field : Response 1 - response1
3438  *
3439  * Register represents bit[63:32] of long response. When CIU sends auto-stop
3440  * command, then response is saved in register. Response for previous command sent
3441  * by host is still preserved in Response 0 register. Additional auto-stop issued
3442  * only for data transfer commands, and response type is always short for them.
3443  *
3444  * Field Access Macros:
3445  *
3446  */
3447 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3448 #define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3449 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3450 #define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3451 /* The width in bits of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3452 #define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3453 /* The mask used to set the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
3454 #define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3455 /* The mask used to clear the ALT_SDMMC_RESP1_RESPONSE1 register field value. */
3456 #define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3457 /* The reset value of the ALT_SDMMC_RESP1_RESPONSE1 register field. */
3458 #define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3459 /* Extracts the ALT_SDMMC_RESP1_RESPONSE1 field value from a register. */
3460 #define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3461 /* Produces a ALT_SDMMC_RESP1_RESPONSE1 register field value suitable for setting the register. */
3462 #define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3463 
3464 #ifndef __ASSEMBLY__
3465 /*
3466  * WARNING: The C register and register group struct declarations are provided for
3467  * convenience and illustrative purposes. They should, however, be used with
3468  * caution as the C language standard provides no guarantees about the alignment or
3469  * atomicity of device memory accesses. The recommended practice for writing
3470  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3471  * alt_write_word() functions.
3472  *
3473  * The struct declaration for register ALT_SDMMC_RESP1.
3474  */
3475 struct ALT_SDMMC_RESP1_s
3476 {
3477  const uint32_t response1 : 32; /* Response 1 */
3478 };
3479 
3480 /* The typedef declaration for register ALT_SDMMC_RESP1. */
3481 typedef volatile struct ALT_SDMMC_RESP1_s ALT_SDMMC_RESP1_t;
3482 #endif /* __ASSEMBLY__ */
3483 
3484 /* The byte offset of the ALT_SDMMC_RESP1 register from the beginning of the component. */
3485 #define ALT_SDMMC_RESP1_OFST 0x34
3486 
3487 /*
3488  * Register : Response Register 2 - resp2
3489  *
3490  * Register Layout
3491  *
3492  * Bits | Access | Reset | Description
3493  * :-------|:-------|:------|:------------
3494  * [31:0] | R | 0x0 | Response 2
3495  *
3496  */
3497 /*
3498  * Field : Response 2 - response2
3499  *
3500  * Bit[95:64] of long response
3501  *
3502  * Field Access Macros:
3503  *
3504  */
3505 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3506 #define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3507 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3508 #define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3509 /* The width in bits of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3510 #define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3511 /* The mask used to set the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
3512 #define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3513 /* The mask used to clear the ALT_SDMMC_RESP2_RESPONSE2 register field value. */
3514 #define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3515 /* The reset value of the ALT_SDMMC_RESP2_RESPONSE2 register field. */
3516 #define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3517 /* Extracts the ALT_SDMMC_RESP2_RESPONSE2 field value from a register. */
3518 #define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3519 /* Produces a ALT_SDMMC_RESP2_RESPONSE2 register field value suitable for setting the register. */
3520 #define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3521 
3522 #ifndef __ASSEMBLY__
3523 /*
3524  * WARNING: The C register and register group struct declarations are provided for
3525  * convenience and illustrative purposes. They should, however, be used with
3526  * caution as the C language standard provides no guarantees about the alignment or
3527  * atomicity of device memory accesses. The recommended practice for writing
3528  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3529  * alt_write_word() functions.
3530  *
3531  * The struct declaration for register ALT_SDMMC_RESP2.
3532  */
3533 struct ALT_SDMMC_RESP2_s
3534 {
3535  const uint32_t response2 : 32; /* Response 2 */
3536 };
3537 
3538 /* The typedef declaration for register ALT_SDMMC_RESP2. */
3539 typedef volatile struct ALT_SDMMC_RESP2_s ALT_SDMMC_RESP2_t;
3540 #endif /* __ASSEMBLY__ */
3541 
3542 /* The byte offset of the ALT_SDMMC_RESP2 register from the beginning of the component. */
3543 #define ALT_SDMMC_RESP2_OFST 0x38
3544 
3545 /*
3546  * Register : Response Register 3 - resp3
3547  *
3548  * Register Layout
3549  *
3550  * Bits | Access | Reset | Description
3551  * :-------|:-------|:------|:------------
3552  * [31:0] | R | 0x0 | Response 3
3553  *
3554  */
3555 /*
3556  * Field : Response 3 - response3
3557  *
3558  * Bit[127:96] of long response
3559  *
3560  * Field Access Macros:
3561  *
3562  */
3563 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
3564 #define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
3565 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
3566 #define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
3567 /* The width in bits of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
3568 #define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
3569 /* The mask used to set the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
3570 #define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
3571 /* The mask used to clear the ALT_SDMMC_RESP3_RESPONSE3 register field value. */
3572 #define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
3573 /* The reset value of the ALT_SDMMC_RESP3_RESPONSE3 register field. */
3574 #define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
3575 /* Extracts the ALT_SDMMC_RESP3_RESPONSE3 field value from a register. */
3576 #define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
3577 /* Produces a ALT_SDMMC_RESP3_RESPONSE3 register field value suitable for setting the register. */
3578 #define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
3579 
3580 #ifndef __ASSEMBLY__
3581 /*
3582  * WARNING: The C register and register group struct declarations are provided for
3583  * convenience and illustrative purposes. They should, however, be used with
3584  * caution as the C language standard provides no guarantees about the alignment or
3585  * atomicity of device memory accesses. The recommended practice for writing
3586  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3587  * alt_write_word() functions.
3588  *
3589  * The struct declaration for register ALT_SDMMC_RESP3.
3590  */
3591 struct ALT_SDMMC_RESP3_s
3592 {
3593  const uint32_t response3 : 32; /* Response 3 */
3594 };
3595 
3596 /* The typedef declaration for register ALT_SDMMC_RESP3. */
3597 typedef volatile struct ALT_SDMMC_RESP3_s ALT_SDMMC_RESP3_t;
3598 #endif /* __ASSEMBLY__ */
3599 
3600 /* The byte offset of the ALT_SDMMC_RESP3 register from the beginning of the component. */
3601 #define ALT_SDMMC_RESP3_OFST 0x3c
3602 
3603 /*
3604  * Register : Masked Interrupt Status Register - mintsts
3605  *
3606  * Describes state of Masked Interrupt Register.
3607  *
3608  * Register Layout
3609  *
3610  * Bits | Access | Reset | Description
3611  * :--------|:-------|:------|:-----------------------------
3612  * [0] | R | 0x0 | Card Detect
3613  * [1] | R | 0x0 | Response Error
3614  * [2] | R | 0x0 | Command Done
3615  * [3] | R | 0x0 | Data Transfer Over
3616  * [4] | R | 0x0 | Data TX FIFO Data Request
3617  * [5] | R | 0x0 | Receive FIFO Data Request
3618  * [6] | R | 0x0 | Response CRC Error
3619  * [7] | R | 0x0 | Data CRC Error
3620  * [8] | R | 0x0 | Response Timeout
3621  * [9] | R | 0x0 | Data Read Timeout
3622  * [10] | R | 0x0 | Data Starvation Host Timeout
3623  * [11] | R | 0x0 | FIFO Underrun Overrun Error
3624  * [12] | R | 0x0 | Hardware Locked Write Error
3625  * [13] | R | 0x0 | Start-bit Error
3626  * [14] | R | 0x0 | Auto Command Done
3627  * [15] | R | 0x0 | End-bit Error
3628  * [16] | R | 0x0 | SDIO Interrupts
3629  * [31:17] | ??? | 0x0 | *UNDEFINED*
3630  *
3631  */
3632 /*
3633  * Field : Card Detect - cd
3634  *
3635  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3636  *
3637  * Field Enumeration Values:
3638  *
3639  * Enum | Value | Description
3640  * :-----------------------------|:------|:----------------------
3641  * ALT_SDMMC_MINTSTS_CD_E_MSK | 0x0 | Card Detected Mask
3642  * ALT_SDMMC_MINTSTS_CD_E_NOMSK | 0x1 | Card Detected No Mask
3643  *
3644  * Field Access Macros:
3645  *
3646  */
3647 /*
3648  * Enumerated value for register field ALT_SDMMC_MINTSTS_CD
3649  *
3650  * Card Detected Mask
3651  */
3652 #define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
3653 /*
3654  * Enumerated value for register field ALT_SDMMC_MINTSTS_CD
3655  *
3656  * Card Detected No Mask
3657  */
3658 #define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
3659 
3660 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CD register field. */
3661 #define ALT_SDMMC_MINTSTS_CD_LSB 0
3662 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CD register field. */
3663 #define ALT_SDMMC_MINTSTS_CD_MSB 0
3664 /* The width in bits of the ALT_SDMMC_MINTSTS_CD register field. */
3665 #define ALT_SDMMC_MINTSTS_CD_WIDTH 1
3666 /* The mask used to set the ALT_SDMMC_MINTSTS_CD register field value. */
3667 #define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
3668 /* The mask used to clear the ALT_SDMMC_MINTSTS_CD register field value. */
3669 #define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
3670 /* The reset value of the ALT_SDMMC_MINTSTS_CD register field. */
3671 #define ALT_SDMMC_MINTSTS_CD_RESET 0x0
3672 /* Extracts the ALT_SDMMC_MINTSTS_CD field value from a register. */
3673 #define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
3674 /* Produces a ALT_SDMMC_MINTSTS_CD register field value suitable for setting the register. */
3675 #define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
3676 
3677 /*
3678  * Field : Response Error - resp
3679  *
3680  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3681  *
3682  * Field Enumeration Values:
3683  *
3684  * Enum | Value | Description
3685  * :-------------------------------|:------|:-----------------------
3686  * ALT_SDMMC_MINTSTS_RESP_E_MSK | 0x0 | Response error Mask
3687  * ALT_SDMMC_MINTSTS_RESP_E_NOMSK | 0x1 | Response error No Mask
3688  *
3689  * Field Access Macros:
3690  *
3691  */
3692 /*
3693  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP
3694  *
3695  * Response error Mask
3696  */
3697 #define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
3698 /*
3699  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESP
3700  *
3701  * Response error No Mask
3702  */
3703 #define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
3704 
3705 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */
3706 #define ALT_SDMMC_MINTSTS_RESP_LSB 1
3707 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESP register field. */
3708 #define ALT_SDMMC_MINTSTS_RESP_MSB 1
3709 /* The width in bits of the ALT_SDMMC_MINTSTS_RESP register field. */
3710 #define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
3711 /* The mask used to set the ALT_SDMMC_MINTSTS_RESP register field value. */
3712 #define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
3713 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESP register field value. */
3714 #define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
3715 /* The reset value of the ALT_SDMMC_MINTSTS_RESP register field. */
3716 #define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
3717 /* Extracts the ALT_SDMMC_MINTSTS_RESP field value from a register. */
3718 #define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
3719 /* Produces a ALT_SDMMC_MINTSTS_RESP register field value suitable for setting the register. */
3720 #define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
3721 
3722 /*
3723  * Field : Command Done - cmd_done
3724  *
3725  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3726  *
3727  * Field Enumeration Values:
3728  *
3729  * Enum | Value | Description
3730  * :-----------------------------------|:------|:---------------------
3731  * ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK | 0x0 | Command Done Mask
3732  * ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK | 0x1 | Command Done No Mask
3733  *
3734  * Field Access Macros:
3735  *
3736  */
3737 /*
3738  * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE
3739  *
3740  * Command Done Mask
3741  */
3742 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
3743 /*
3744  * Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE
3745  *
3746  * Command Done No Mask
3747  */
3748 #define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
3749 
3750 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
3751 #define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
3752 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
3753 #define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
3754 /* The width in bits of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
3755 #define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
3756 /* The mask used to set the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */
3757 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
3758 /* The mask used to clear the ALT_SDMMC_MINTSTS_CMD_DONE register field value. */
3759 #define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
3760 /* The reset value of the ALT_SDMMC_MINTSTS_CMD_DONE register field. */
3761 #define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
3762 /* Extracts the ALT_SDMMC_MINTSTS_CMD_DONE field value from a register. */
3763 #define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
3764 /* Produces a ALT_SDMMC_MINTSTS_CMD_DONE register field value suitable for setting the register. */
3765 #define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
3766 
3767 /*
3768  * Field : Data Transfer Over - dt
3769  *
3770  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3771  *
3772  * Field Enumeration Values:
3773  *
3774  * Enum | Value | Description
3775  * :-----------------------------|:------|:---------------------------
3776  * ALT_SDMMC_MINTSTS_DT_E_MSK | 0x0 | Data transfer over Mask
3777  * ALT_SDMMC_MINTSTS_DT_E_NOMSK | 0x1 | Data transfer over No Mask
3778  *
3779  * Field Access Macros:
3780  *
3781  */
3782 /*
3783  * Enumerated value for register field ALT_SDMMC_MINTSTS_DT
3784  *
3785  * Data transfer over Mask
3786  */
3787 #define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
3788 /*
3789  * Enumerated value for register field ALT_SDMMC_MINTSTS_DT
3790  *
3791  * Data transfer over No Mask
3792  */
3793 #define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
3794 
3795 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DT register field. */
3796 #define ALT_SDMMC_MINTSTS_DT_LSB 3
3797 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DT register field. */
3798 #define ALT_SDMMC_MINTSTS_DT_MSB 3
3799 /* The width in bits of the ALT_SDMMC_MINTSTS_DT register field. */
3800 #define ALT_SDMMC_MINTSTS_DT_WIDTH 1
3801 /* The mask used to set the ALT_SDMMC_MINTSTS_DT register field value. */
3802 #define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
3803 /* The mask used to clear the ALT_SDMMC_MINTSTS_DT register field value. */
3804 #define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
3805 /* The reset value of the ALT_SDMMC_MINTSTS_DT register field. */
3806 #define ALT_SDMMC_MINTSTS_DT_RESET 0x0
3807 /* Extracts the ALT_SDMMC_MINTSTS_DT field value from a register. */
3808 #define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
3809 /* Produces a ALT_SDMMC_MINTSTS_DT register field value suitable for setting the register. */
3810 #define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
3811 
3812 /*
3813  * Field : Data TX FIFO Data Request - dttxfifodr
3814  *
3815  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3816  *
3817  * Field Enumeration Values:
3818  *
3819  * Enum | Value | Description
3820  * :-------------------------------------|:------|:-----------------------------------
3821  * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK | 0x0 | Transmit FIFO data request Mask
3822  * ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK | 0x1 | Transmit FIFO data request No Mask
3823  *
3824  * Field Access Macros:
3825  *
3826  */
3827 /*
3828  * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR
3829  *
3830  * Transmit FIFO data request Mask
3831  */
3832 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
3833 /*
3834  * Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR
3835  *
3836  * Transmit FIFO data request No Mask
3837  */
3838 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
3839 
3840 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
3841 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
3842 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
3843 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
3844 /* The width in bits of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
3845 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
3846 /* The mask used to set the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */
3847 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
3848 /* The mask used to clear the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value. */
3849 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
3850 /* The reset value of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field. */
3851 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
3852 /* Extracts the ALT_SDMMC_MINTSTS_DTTXFIFODR field value from a register. */
3853 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
3854 /* Produces a ALT_SDMMC_MINTSTS_DTTXFIFODR register field value suitable for setting the register. */
3855 #define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
3856 
3857 /*
3858  * Field : Receive FIFO Data Request - rxfifodr
3859  *
3860  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3861  *
3862  * Field Enumeration Values:
3863  *
3864  * Enum | Value | Description
3865  * :-----------------------------------|:------|:----------------------------------
3866  * ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK | 0x0 | Receive FIFO data request Mask
3867  * ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK | 0x1 | Receive FIFO data request No Mask
3868  *
3869  * Field Access Macros:
3870  *
3871  */
3872 /*
3873  * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR
3874  *
3875  * Receive FIFO data request Mask
3876  */
3877 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
3878 /*
3879  * Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR
3880  *
3881  * Receive FIFO data request No Mask
3882  */
3883 #define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
3884 
3885 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
3886 #define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
3887 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
3888 #define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
3889 /* The width in bits of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
3890 #define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
3891 /* The mask used to set the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */
3892 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
3893 /* The mask used to clear the ALT_SDMMC_MINTSTS_RXFIFODR register field value. */
3894 #define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
3895 /* The reset value of the ALT_SDMMC_MINTSTS_RXFIFODR register field. */
3896 #define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
3897 /* Extracts the ALT_SDMMC_MINTSTS_RXFIFODR field value from a register. */
3898 #define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
3899 /* Produces a ALT_SDMMC_MINTSTS_RXFIFODR register field value suitable for setting the register. */
3900 #define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
3901 
3902 /*
3903  * Field : Response CRC Error - respcrcerr
3904  *
3905  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3906  *
3907  * Field Enumeration Values:
3908  *
3909  * Enum | Value | Description
3910  * :-------------------------------------|:------|:---------------------------
3911  * ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK | 0x0 | Response CRC error Mask
3912  * ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK | 0x1 | Response CRC error No Mask
3913  *
3914  * Field Access Macros:
3915  *
3916  */
3917 /*
3918  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR
3919  *
3920  * Response CRC error Mask
3921  */
3922 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
3923 /*
3924  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR
3925  *
3926  * Response CRC error No Mask
3927  */
3928 #define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
3929 
3930 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
3931 #define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
3932 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
3933 #define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
3934 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
3935 #define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
3936 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */
3937 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
3938 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPCRCERR register field value. */
3939 #define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
3940 /* The reset value of the ALT_SDMMC_MINTSTS_RESPCRCERR register field. */
3941 #define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
3942 /* Extracts the ALT_SDMMC_MINTSTS_RESPCRCERR field value from a register. */
3943 #define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
3944 /* Produces a ALT_SDMMC_MINTSTS_RESPCRCERR register field value suitable for setting the register. */
3945 #define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
3946 
3947 /*
3948  * Field : Data CRC Error - datacrcerr
3949  *
3950  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3951  *
3952  * Field Enumeration Values:
3953  *
3954  * Enum | Value | Description
3955  * :-------------------------------------|:------|:-----------------------
3956  * ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK | 0x0 | Data CRC error Mask
3957  * ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK | 0x1 | Data CRC error No Mask
3958  *
3959  * Field Access Macros:
3960  *
3961  */
3962 /*
3963  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR
3964  *
3965  * Data CRC error Mask
3966  */
3967 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
3968 /*
3969  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR
3970  *
3971  * Data CRC error No Mask
3972  */
3973 #define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
3974 
3975 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
3976 #define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
3977 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
3978 #define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
3979 /* The width in bits of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
3980 #define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
3981 /* The mask used to set the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */
3982 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
3983 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATACRCERR register field value. */
3984 #define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
3985 /* The reset value of the ALT_SDMMC_MINTSTS_DATACRCERR register field. */
3986 #define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
3987 /* Extracts the ALT_SDMMC_MINTSTS_DATACRCERR field value from a register. */
3988 #define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
3989 /* Produces a ALT_SDMMC_MINTSTS_DATACRCERR register field value suitable for setting the register. */
3990 #define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
3991 
3992 /*
3993  * Field : Response Timeout - respto
3994  *
3995  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
3996  *
3997  * Field Enumeration Values:
3998  *
3999  * Enum | Value | Description
4000  * :---------------------------------|:------|:-------------------------
4001  * ALT_SDMMC_MINTSTS_RESPTO_E_MSK | 0x0 | Response timeout Mask
4002  * ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK | 0x1 | Response timeout No Mask
4003  *
4004  * Field Access Macros:
4005  *
4006  */
4007 /*
4008  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO
4009  *
4010  * Response timeout Mask
4011  */
4012 #define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4013 /*
4014  * Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO
4015  *
4016  * Response timeout No Mask
4017  */
4018 #define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4019 
4020 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4021 #define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4022 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4023 #define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4024 /* The width in bits of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4025 #define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4026 /* The mask used to set the ALT_SDMMC_MINTSTS_RESPTO register field value. */
4027 #define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4028 /* The mask used to clear the ALT_SDMMC_MINTSTS_RESPTO register field value. */
4029 #define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4030 /* The reset value of the ALT_SDMMC_MINTSTS_RESPTO register field. */
4031 #define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4032 /* Extracts the ALT_SDMMC_MINTSTS_RESPTO field value from a register. */
4033 #define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4034 /* Produces a ALT_SDMMC_MINTSTS_RESPTO register field value suitable for setting the register. */
4035 #define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4036 
4037 /*
4038  * Field : Data Read Timeout - datardto
4039  *
4040  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4041  *
4042  * Field Enumeration Values:
4043  *
4044  * Enum | Value | Description
4045  * :-----------------------------------|:------|:--------------------------
4046  * ALT_SDMMC_MINTSTS_DATARDTO_E_MSK | 0x0 | Data read timeout Mask
4047  * ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK | 0x1 | Data read timeout No Mask
4048  *
4049  * Field Access Macros:
4050  *
4051  */
4052 /*
4053  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO
4054  *
4055  * Data read timeout Mask
4056  */
4057 #define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4058 /*
4059  * Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO
4060  *
4061  * Data read timeout No Mask
4062  */
4063 #define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4064 
4065 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4066 #define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4067 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4068 #define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4069 /* The width in bits of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4070 #define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4071 /* The mask used to set the ALT_SDMMC_MINTSTS_DATARDTO register field value. */
4072 #define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4073 /* The mask used to clear the ALT_SDMMC_MINTSTS_DATARDTO register field value. */
4074 #define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4075 /* The reset value of the ALT_SDMMC_MINTSTS_DATARDTO register field. */
4076 #define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4077 /* Extracts the ALT_SDMMC_MINTSTS_DATARDTO field value from a register. */
4078 #define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4079 /* Produces a ALT_SDMMC_MINTSTS_DATARDTO register field value suitable for setting the register. */
4080 #define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4081 
4082 /*
4083  * Field : Data Starvation Host Timeout - dshto
4084  *
4085  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4086  *
4087  * Field Enumeration Values:
4088  *
4089  * Enum | Value | Description
4090  * :--------------------------------|:------|:----------------------------------------
4091  * ALT_SDMMC_MINTSTS_DSHTO_E_MSK | 0x0 | Data starvation by host timeout Mask
4092  * ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK | 0x1 | Data starvation by host timeout No Mask
4093  *
4094  * Field Access Macros:
4095  *
4096  */
4097 /*
4098  * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO
4099  *
4100  * Data starvation by host timeout Mask
4101  */
4102 #define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4103 /*
4104  * Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO
4105  *
4106  * Data starvation by host timeout No Mask
4107  */
4108 #define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4109 
4110 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4111 #define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4112 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4113 #define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4114 /* The width in bits of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4115 #define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4116 /* The mask used to set the ALT_SDMMC_MINTSTS_DSHTO register field value. */
4117 #define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4118 /* The mask used to clear the ALT_SDMMC_MINTSTS_DSHTO register field value. */
4119 #define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4120 /* The reset value of the ALT_SDMMC_MINTSTS_DSHTO register field. */
4121 #define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4122 /* Extracts the ALT_SDMMC_MINTSTS_DSHTO field value from a register. */
4123 #define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4124 /* Produces a ALT_SDMMC_MINTSTS_DSHTO register field value suitable for setting the register. */
4125 #define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4126 
4127 /*
4128  * Field : FIFO Underrun Overrun Error - fifoovunerr
4129  *
4130  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4131  *
4132  * Field Enumeration Values:
4133  *
4134  * Enum | Value | Description
4135  * :--------------------------------------|:------|:------------------------------------
4136  * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK | 0x0 | FIFO underrun/overrun error Mask
4137  * ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK | 0x1 | FIFO underrun/overrun error No Mask
4138  *
4139  * Field Access Macros:
4140  *
4141  */
4142 /*
4143  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR
4144  *
4145  * FIFO underrun/overrun error Mask
4146  */
4147 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4148 /*
4149  * Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR
4150  *
4151  * FIFO underrun/overrun error No Mask
4152  */
4153 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4154 
4155 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4156 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4157 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4158 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4159 /* The width in bits of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4160 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4161 /* The mask used to set the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */
4162 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4163 /* The mask used to clear the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value. */
4164 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4165 /* The reset value of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field. */
4166 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4167 /* Extracts the ALT_SDMMC_MINTSTS_FIFOOVUNERR field value from a register. */
4168 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4169 /* Produces a ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value suitable for setting the register. */
4170 #define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4171 
4172 /*
4173  * Field : Hardware Locked Write Error - hlwerr
4174  *
4175  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4176  *
4177  * Field Enumeration Values:
4178  *
4179  * Enum | Value | Description
4180  * :---------------------------------|:------|:------------------------------------
4181  * ALT_SDMMC_MINTSTS_HLWERR_E_MSK | 0x0 | Hardware locked write error Mask
4182  * ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK | 0x1 | Hardware locked write error No Mask
4183  *
4184  * Field Access Macros:
4185  *
4186  */
4187 /*
4188  * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR
4189  *
4190  * Hardware locked write error Mask
4191  */
4192 #define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4193 /*
4194  * Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR
4195  *
4196  * Hardware locked write error No Mask
4197  */
4198 #define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4199 
4200 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4201 #define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4202 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4203 #define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4204 /* The width in bits of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4205 #define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4206 /* The mask used to set the ALT_SDMMC_MINTSTS_HLWERR register field value. */
4207 #define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4208 /* The mask used to clear the ALT_SDMMC_MINTSTS_HLWERR register field value. */
4209 #define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4210 /* The reset value of the ALT_SDMMC_MINTSTS_HLWERR register field. */
4211 #define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4212 /* Extracts the ALT_SDMMC_MINTSTS_HLWERR field value from a register. */
4213 #define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4214 /* Produces a ALT_SDMMC_MINTSTS_HLWERR register field value suitable for setting the register. */
4215 #define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4216 
4217 /*
4218  * Field : Start-bit Error - strerr
4219  *
4220  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4221  *
4222  * Field Enumeration Values:
4223  *
4224  * Enum | Value | Description
4225  * :---------------------------------|:------|:------------------------
4226  * ALT_SDMMC_MINTSTS_STRERR_E_MSK | 0x0 | Start-bit error Mask
4227  * ALT_SDMMC_MINTSTS_STRERR_E_NOMSK | 0x1 | Start-bit error No Mask
4228  *
4229  * Field Access Macros:
4230  *
4231  */
4232 /*
4233  * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR
4234  *
4235  * Start-bit error Mask
4236  */
4237 #define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4238 /*
4239  * Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR
4240  *
4241  * Start-bit error No Mask
4242  */
4243 #define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4244 
4245 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */
4246 #define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4247 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_STRERR register field. */
4248 #define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4249 /* The width in bits of the ALT_SDMMC_MINTSTS_STRERR register field. */
4250 #define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4251 /* The mask used to set the ALT_SDMMC_MINTSTS_STRERR register field value. */
4252 #define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4253 /* The mask used to clear the ALT_SDMMC_MINTSTS_STRERR register field value. */
4254 #define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4255 /* The reset value of the ALT_SDMMC_MINTSTS_STRERR register field. */
4256 #define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4257 /* Extracts the ALT_SDMMC_MINTSTS_STRERR field value from a register. */
4258 #define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4259 /* Produces a ALT_SDMMC_MINTSTS_STRERR register field value suitable for setting the register. */
4260 #define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4261 
4262 /*
4263  * Field : Auto Command Done - acd
4264  *
4265  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4266  *
4267  * Field Enumeration Values:
4268  *
4269  * Enum | Value | Description
4270  * :------------------------------|:------|:--------------------------
4271  * ALT_SDMMC_MINTSTS_ACD_E_MSK | 0x0 | Auto command done Mask
4272  * ALT_SDMMC_MINTSTS_ACD_E_NOMSK | 0x1 | Auto command done No Mask
4273  *
4274  * Field Access Macros:
4275  *
4276  */
4277 /*
4278  * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD
4279  *
4280  * Auto command done Mask
4281  */
4282 #define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4283 /*
4284  * Enumerated value for register field ALT_SDMMC_MINTSTS_ACD
4285  *
4286  * Auto command done No Mask
4287  */
4288 #define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4289 
4290 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */
4291 #define ALT_SDMMC_MINTSTS_ACD_LSB 14
4292 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_ACD register field. */
4293 #define ALT_SDMMC_MINTSTS_ACD_MSB 14
4294 /* The width in bits of the ALT_SDMMC_MINTSTS_ACD register field. */
4295 #define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4296 /* The mask used to set the ALT_SDMMC_MINTSTS_ACD register field value. */
4297 #define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4298 /* The mask used to clear the ALT_SDMMC_MINTSTS_ACD register field value. */
4299 #define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4300 /* The reset value of the ALT_SDMMC_MINTSTS_ACD register field. */
4301 #define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4302 /* Extracts the ALT_SDMMC_MINTSTS_ACD field value from a register. */
4303 #define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4304 /* Produces a ALT_SDMMC_MINTSTS_ACD register field value suitable for setting the register. */
4305 #define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4306 
4307 /*
4308  * Field : End-bit Error - ebe
4309  *
4310  * Interrupt enabled only if corresponding bit in interrupt mask register is set.
4311  *
4312  * Field Enumeration Values:
4313  *
4314  * Enum | Value | Description
4315  * :------------------------------|:------|:----------------------
4316  * ALT_SDMMC_MINTSTS_EBE_E_MSK | 0x0 | End-bit error Mask
4317  * ALT_SDMMC_MINTSTS_EBE_E_NOMSK | 0x1 | End-bit error No Mask
4318  *
4319  * Field Access Macros:
4320  *
4321  */
4322 /*
4323  * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE
4324  *
4325  * End-bit error Mask
4326  */
4327 #define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4328 /*
4329  * Enumerated value for register field ALT_SDMMC_MINTSTS_EBE
4330  *
4331  * End-bit error No Mask
4332  */
4333 #define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4334 
4335 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */
4336 #define ALT_SDMMC_MINTSTS_EBE_LSB 15
4337 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_EBE register field. */
4338 #define ALT_SDMMC_MINTSTS_EBE_MSB 15
4339 /* The width in bits of the ALT_SDMMC_MINTSTS_EBE register field. */
4340 #define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4341 /* The mask used to set the ALT_SDMMC_MINTSTS_EBE register field value. */
4342 #define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4343 /* The mask used to clear the ALT_SDMMC_MINTSTS_EBE register field value. */
4344 #define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4345 /* The reset value of the ALT_SDMMC_MINTSTS_EBE register field. */
4346 #define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4347 /* Extracts the ALT_SDMMC_MINTSTS_EBE field value from a register. */
4348 #define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4349 /* Produces a ALT_SDMMC_MINTSTS_EBE register field value suitable for setting the register. */
4350 #define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4351 
4352 /*
4353  * Field : SDIO Interrupts - sdio_interrupt
4354  *
4355  * Interrupt from SDIO card: one bit for each card. Bit[16] is for Card[0]. SDIO
4356  * interrupt for card enabled only if corresponding sdio_int_mask bit is set in
4357  * Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). In
4358  * MMC-Ver3.3-only mode, bits always 0.
4359  *
4360  * Field Enumeration Values:
4361  *
4362  * Enum | Value | Description
4363  * :-----------------------------------|:------|:----------------------------
4364  * ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card
4365  * ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card
4366  *
4367  * Field Access Macros:
4368  *
4369  */
4370 /*
4371  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT
4372  *
4373  * SDIO interrupt from card
4374  */
4375 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4376 /*
4377  * Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT
4378  *
4379  * No SDIO interrupt from card
4380  */
4381 #define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4382 
4383 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4384 #define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4385 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4386 #define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 16
4387 /* The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4388 #define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 1
4389 /* The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */
4390 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0x00010000
4391 /* The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INT register field value. */
4392 #define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
4393 /* The reset value of the ALT_SDMMC_MINTSTS_SDIO_INT register field. */
4394 #define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4395 /* Extracts the ALT_SDMMC_MINTSTS_SDIO_INT field value from a register. */
4396 #define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
4397 /* Produces a ALT_SDMMC_MINTSTS_SDIO_INT register field value suitable for setting the register. */
4398 #define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
4399 
4400 #ifndef __ASSEMBLY__
4401 /*
4402  * WARNING: The C register and register group struct declarations are provided for
4403  * convenience and illustrative purposes. They should, however, be used with
4404  * caution as the C language standard provides no guarantees about the alignment or
4405  * atomicity of device memory accesses. The recommended practice for writing
4406  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4407  * alt_write_word() functions.
4408  *
4409  * The struct declaration for register ALT_SDMMC_MINTSTS.
4410  */
4411 struct ALT_SDMMC_MINTSTS_s
4412 {
4413  const uint32_t cd : 1; /* Card Detect */
4414  const uint32_t resp : 1; /* Response Error */
4415  const uint32_t cmd_done : 1; /* Command Done */
4416  const uint32_t dt : 1; /* Data Transfer Over */
4417  const uint32_t dttxfifodr : 1; /* Data TX FIFO Data Request */
4418  const uint32_t rxfifodr : 1; /* Receive FIFO Data Request */
4419  const uint32_t respcrcerr : 1; /* Response CRC Error */
4420  const uint32_t datacrcerr : 1; /* Data CRC Error */
4421  const uint32_t respto : 1; /* Response Timeout */
4422  const uint32_t datardto : 1; /* Data Read Timeout */
4423  const uint32_t dshto : 1; /* Data Starvation Host Timeout */
4424  const uint32_t fifoovunerr : 1; /* FIFO Underrun Overrun Error */
4425  const uint32_t hlwerr : 1; /* Hardware Locked Write Error */
4426  const uint32_t strerr : 1; /* Start-bit Error */
4427  const uint32_t acd : 1; /* Auto Command Done */
4428  const uint32_t ebe : 1; /* End-bit Error */
4429  const uint32_t sdio_interrupt : 1; /* SDIO Interrupts */
4430  uint32_t : 15; /* *UNDEFINED* */
4431 };
4432 
4433 /* The typedef declaration for register ALT_SDMMC_MINTSTS. */
4434 typedef volatile struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t;
4435 #endif /* __ASSEMBLY__ */
4436 
4437 /* The byte offset of the ALT_SDMMC_MINTSTS register from the beginning of the component. */
4438 #define ALT_SDMMC_MINTSTS_OFST 0x40
4439 
4440 /*
4441  * Register : Raw Interrupt Status Register - rintsts
4442  *
4443  * Interrupt Status Before Masking.
4444  *
4445  * Register Layout
4446  *
4447  * Bits | Access | Reset | Description
4448  * :--------|:-------|:------|:---------------------------------------------
4449  * [0] | RW | 0x0 | Card Detect
4450  * [1] | RW | 0x0 | Response Error
4451  * [2] | RW | 0x0 | Command Done
4452  * [3] | RW | 0x0 | Data Transfer Over
4453  * [4] | RW | 0x0 | Transmit FIFO Data Request
4454  * [5] | RW | 0x0 | Receive FIFO Data Request
4455  * [6] | RW | 0x0 | Response CRC Error
4456  * [7] | RW | 0x0 | Data CRC Error
4457  * [8] | RW | 0x0 | Response Timeout Boot Ack Received
4458  * [9] | RW | 0x0 | Data Read Timeout Boot Data Start
4459  * [10] | RW | 0x0 | Data Starvation Host Timeout Volt Switch_int
4460  * [11] | RW | 0x0 | FIFO Underrun Overrun Error
4461  * [12] | RW | 0x0 | Hardware Locked Write Error
4462  * [13] | RW | 0x0 | Start-bit error (SBE)
4463  * [14] | RW | 0x0 | Auto Cmommand Done
4464  * [15] | RW | 0x0 | End-bit Error
4465  * [16] | RW | 0x0 | SDIO Interrupt
4466  * [31:17] | ??? | 0x0 | *UNDEFINED*
4467  *
4468  */
4469 /*
4470  * Field : Card Detect - cd
4471  *
4472  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4473  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4474  *
4475  * Field Enumeration Values:
4476  *
4477  * Enum | Value | Description
4478  * :-----------------------------|:------|:------------------------
4479  * ALT_SDMMC_RINTSTS_CD_E_INACT | 0x0 | Card detect (CD)
4480  * ALT_SDMMC_RINTSTS_CD_E_ACT | 0x1 | Clears Card detect (CD)
4481  *
4482  * Field Access Macros:
4483  *
4484  */
4485 /*
4486  * Enumerated value for register field ALT_SDMMC_RINTSTS_CD
4487  *
4488  * Card detect (CD)
4489  */
4490 #define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4491 /*
4492  * Enumerated value for register field ALT_SDMMC_RINTSTS_CD
4493  *
4494  * Clears Card detect (CD)
4495  */
4496 #define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4497 
4498 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CD register field. */
4499 #define ALT_SDMMC_RINTSTS_CD_LSB 0
4500 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CD register field. */
4501 #define ALT_SDMMC_RINTSTS_CD_MSB 0
4502 /* The width in bits of the ALT_SDMMC_RINTSTS_CD register field. */
4503 #define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4504 /* The mask used to set the ALT_SDMMC_RINTSTS_CD register field value. */
4505 #define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4506 /* The mask used to clear the ALT_SDMMC_RINTSTS_CD register field value. */
4507 #define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4508 /* The reset value of the ALT_SDMMC_RINTSTS_CD register field. */
4509 #define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4510 /* Extracts the ALT_SDMMC_RINTSTS_CD field value from a register. */
4511 #define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4512 /* Produces a ALT_SDMMC_RINTSTS_CD register field value suitable for setting the register. */
4513 #define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4514 
4515 /*
4516  * Field : Response Error - re
4517  *
4518  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4519  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4520  *
4521  * Field Enumeration Values:
4522  *
4523  * Enum | Value | Description
4524  * :-----------------------------|:------|:---------------------------
4525  * ALT_SDMMC_RINTSTS_RE_E_INACT | 0x0 | Response error (RE)
4526  * ALT_SDMMC_RINTSTS_RE_E_ACT | 0x1 | Clears Response error (RE)
4527  *
4528  * Field Access Macros:
4529  *
4530  */
4531 /*
4532  * Enumerated value for register field ALT_SDMMC_RINTSTS_RE
4533  *
4534  * Response error (RE)
4535  */
4536 #define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4537 /*
4538  * Enumerated value for register field ALT_SDMMC_RINTSTS_RE
4539  *
4540  * Clears Response error (RE)
4541  */
4542 #define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4543 
4544 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RE register field. */
4545 #define ALT_SDMMC_RINTSTS_RE_LSB 1
4546 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RE register field. */
4547 #define ALT_SDMMC_RINTSTS_RE_MSB 1
4548 /* The width in bits of the ALT_SDMMC_RINTSTS_RE register field. */
4549 #define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4550 /* The mask used to set the ALT_SDMMC_RINTSTS_RE register field value. */
4551 #define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4552 /* The mask used to clear the ALT_SDMMC_RINTSTS_RE register field value. */
4553 #define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4554 /* The reset value of the ALT_SDMMC_RINTSTS_RE register field. */
4555 #define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4556 /* Extracts the ALT_SDMMC_RINTSTS_RE field value from a register. */
4557 #define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
4558 /* Produces a ALT_SDMMC_RINTSTS_RE register field value suitable for setting the register. */
4559 #define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
4560 
4561 /*
4562  * Field : Command Done - cmd
4563  *
4564  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4565  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4566  *
4567  * Field Enumeration Values:
4568  *
4569  * Enum | Value | Description
4570  * :------------------------------|:------|:-------------------------
4571  * ALT_SDMMC_RINTSTS_CMD_E_INACT | 0x0 | Command done (CD)
4572  * ALT_SDMMC_RINTSTS_CMD_E_ACT | 0x1 | Clears Command done (CD)
4573  *
4574  * Field Access Macros:
4575  *
4576  */
4577 /*
4578  * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD
4579  *
4580  * Command done (CD)
4581  */
4582 #define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
4583 /*
4584  * Enumerated value for register field ALT_SDMMC_RINTSTS_CMD
4585  *
4586  * Clears Command done (CD)
4587  */
4588 #define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
4589 
4590 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */
4591 #define ALT_SDMMC_RINTSTS_CMD_LSB 2
4592 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_CMD register field. */
4593 #define ALT_SDMMC_RINTSTS_CMD_MSB 2
4594 /* The width in bits of the ALT_SDMMC_RINTSTS_CMD register field. */
4595 #define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
4596 /* The mask used to set the ALT_SDMMC_RINTSTS_CMD register field value. */
4597 #define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
4598 /* The mask used to clear the ALT_SDMMC_RINTSTS_CMD register field value. */
4599 #define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
4600 /* The reset value of the ALT_SDMMC_RINTSTS_CMD register field. */
4601 #define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
4602 /* Extracts the ALT_SDMMC_RINTSTS_CMD field value from a register. */
4603 #define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
4604 /* Produces a ALT_SDMMC_RINTSTS_CMD register field value suitable for setting the register. */
4605 #define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
4606 
4607 /*
4608  * Field : Data Transfer Over - dto
4609  *
4610  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4611  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4612  *
4613  * Field Enumeration Values:
4614  *
4615  * Enum | Value | Description
4616  * :------------------------------|:------|:--------------------------------
4617  * ALT_SDMMC_RINTSTS_DTO_E_INACT | 0x0 | Data transfer over (DTO)
4618  * ALT_SDMMC_RINTSTS_DTO_E_ACT | 0x1 | Clears Data transfer over (DTO)
4619  *
4620  * Field Access Macros:
4621  *
4622  */
4623 /*
4624  * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO
4625  *
4626  * Data transfer over (DTO)
4627  */
4628 #define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
4629 /*
4630  * Enumerated value for register field ALT_SDMMC_RINTSTS_DTO
4631  *
4632  * Clears Data transfer over (DTO)
4633  */
4634 #define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
4635 
4636 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */
4637 #define ALT_SDMMC_RINTSTS_DTO_LSB 3
4638 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DTO register field. */
4639 #define ALT_SDMMC_RINTSTS_DTO_MSB 3
4640 /* The width in bits of the ALT_SDMMC_RINTSTS_DTO register field. */
4641 #define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
4642 /* The mask used to set the ALT_SDMMC_RINTSTS_DTO register field value. */
4643 #define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
4644 /* The mask used to clear the ALT_SDMMC_RINTSTS_DTO register field value. */
4645 #define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
4646 /* The reset value of the ALT_SDMMC_RINTSTS_DTO register field. */
4647 #define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
4648 /* Extracts the ALT_SDMMC_RINTSTS_DTO field value from a register. */
4649 #define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
4650 /* Produces a ALT_SDMMC_RINTSTS_DTO register field value suitable for setting the register. */
4651 #define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
4652 
4653 /*
4654  * Field : Transmit FIFO Data Request - txdr
4655  *
4656  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4657  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4658  *
4659  * Field Enumeration Values:
4660  *
4661  * Enum | Value | Description
4662  * :-------------------------------|:------|:-----------------------------------------
4663  * ALT_SDMMC_RINTSTS_TXDR_E_INACT | 0x0 | Transmit FIFO data request (TXDR)
4664  * ALT_SDMMC_RINTSTS_TXDR_E_ACT | 0x1 | Clears Transmit FIFO data request (TXDR)
4665  *
4666  * Field Access Macros:
4667  *
4668  */
4669 /*
4670  * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR
4671  *
4672  * Transmit FIFO data request (TXDR)
4673  */
4674 #define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
4675 /*
4676  * Enumerated value for register field ALT_SDMMC_RINTSTS_TXDR
4677  *
4678  * Clears Transmit FIFO data request (TXDR)
4679  */
4680 #define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
4681 
4682 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */
4683 #define ALT_SDMMC_RINTSTS_TXDR_LSB 4
4684 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_TXDR register field. */
4685 #define ALT_SDMMC_RINTSTS_TXDR_MSB 4
4686 /* The width in bits of the ALT_SDMMC_RINTSTS_TXDR register field. */
4687 #define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
4688 /* The mask used to set the ALT_SDMMC_RINTSTS_TXDR register field value. */
4689 #define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
4690 /* The mask used to clear the ALT_SDMMC_RINTSTS_TXDR register field value. */
4691 #define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
4692 /* The reset value of the ALT_SDMMC_RINTSTS_TXDR register field. */
4693 #define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
4694 /* Extracts the ALT_SDMMC_RINTSTS_TXDR field value from a register. */
4695 #define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
4696 /* Produces a ALT_SDMMC_RINTSTS_TXDR register field value suitable for setting the register. */
4697 #define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
4698 
4699 /*
4700  * Field : Receive FIFO Data Request - rxdr
4701  *
4702  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4703  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4704  *
4705  * Field Enumeration Values:
4706  *
4707  * Enum | Value | Description
4708  * :-------------------------------|:------|:----------------------------------------
4709  * ALT_SDMMC_RINTSTS_RXDR_E_INACT | 0x0 | Receive FIFO data request (RXDR)
4710  * ALT_SDMMC_RINTSTS_RXDR_E_ACT | 0x1 | Clears Receive FIFO data request (RXDR)
4711  *
4712  * Field Access Macros:
4713  *
4714  */
4715 /*
4716  * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR
4717  *
4718  * Receive FIFO data request (RXDR)
4719  */
4720 #define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
4721 /*
4722  * Enumerated value for register field ALT_SDMMC_RINTSTS_RXDR
4723  *
4724  * Clears Receive FIFO data request (RXDR)
4725  */
4726 #define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
4727 
4728 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */
4729 #define ALT_SDMMC_RINTSTS_RXDR_LSB 5
4730 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RXDR register field. */
4731 #define ALT_SDMMC_RINTSTS_RXDR_MSB 5
4732 /* The width in bits of the ALT_SDMMC_RINTSTS_RXDR register field. */
4733 #define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
4734 /* The mask used to set the ALT_SDMMC_RINTSTS_RXDR register field value. */
4735 #define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
4736 /* The mask used to clear the ALT_SDMMC_RINTSTS_RXDR register field value. */
4737 #define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
4738 /* The reset value of the ALT_SDMMC_RINTSTS_RXDR register field. */
4739 #define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
4740 /* Extracts the ALT_SDMMC_RINTSTS_RXDR field value from a register. */
4741 #define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
4742 /* Produces a ALT_SDMMC_RINTSTS_RXDR register field value suitable for setting the register. */
4743 #define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
4744 
4745 /*
4746  * Field : Response CRC Error - rcrc
4747  *
4748  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4749  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4750  *
4751  * Field Enumeration Values:
4752  *
4753  * Enum | Value | Description
4754  * :-------------------------------|:------|:---------------------------------
4755  * ALT_SDMMC_RINTSTS_RCRC_E_INACT | 0x0 | Response CRC error (RCRC)
4756  * ALT_SDMMC_RINTSTS_RCRC_E_ACT | 0x1 | Clears Response CRC error (RCRC)
4757  *
4758  * Field Access Macros:
4759  *
4760  */
4761 /*
4762  * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC
4763  *
4764  * Response CRC error (RCRC)
4765  */
4766 #define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
4767 /*
4768  * Enumerated value for register field ALT_SDMMC_RINTSTS_RCRC
4769  *
4770  * Clears Response CRC error (RCRC)
4771  */
4772 #define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
4773 
4774 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */
4775 #define ALT_SDMMC_RINTSTS_RCRC_LSB 6
4776 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_RCRC register field. */
4777 #define ALT_SDMMC_RINTSTS_RCRC_MSB 6
4778 /* The width in bits of the ALT_SDMMC_RINTSTS_RCRC register field. */
4779 #define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
4780 /* The mask used to set the ALT_SDMMC_RINTSTS_RCRC register field value. */
4781 #define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
4782 /* The mask used to clear the ALT_SDMMC_RINTSTS_RCRC register field value. */
4783 #define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
4784 /* The reset value of the ALT_SDMMC_RINTSTS_RCRC register field. */
4785 #define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
4786 /* Extracts the ALT_SDMMC_RINTSTS_RCRC field value from a register. */
4787 #define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
4788 /* Produces a ALT_SDMMC_RINTSTS_RCRC register field value suitable for setting the register. */
4789 #define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
4790 
4791 /*
4792  * Field : Data CRC Error - dcrc
4793  *
4794  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4795  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4796  *
4797  * Field Enumeration Values:
4798  *
4799  * Enum | Value | Description
4800  * :-------------------------------|:------|:-----------------------------
4801  * ALT_SDMMC_RINTSTS_DCRC_E_INACT | 0x0 | Data CRC error (DCRC)
4802  * ALT_SDMMC_RINTSTS_DCRC_E_ACT | 0x1 | Clears Data CRC error (DCRC)
4803  *
4804  * Field Access Macros:
4805  *
4806  */
4807 /*
4808  * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC
4809  *
4810  * Data CRC error (DCRC)
4811  */
4812 #define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
4813 /*
4814  * Enumerated value for register field ALT_SDMMC_RINTSTS_DCRC
4815  *
4816  * Clears Data CRC error (DCRC)
4817  */
4818 #define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
4819 
4820 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */
4821 #define ALT_SDMMC_RINTSTS_DCRC_LSB 7
4822 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_DCRC register field. */
4823 #define ALT_SDMMC_RINTSTS_DCRC_MSB 7
4824 /* The width in bits of the ALT_SDMMC_RINTSTS_DCRC register field. */
4825 #define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
4826 /* The mask used to set the ALT_SDMMC_RINTSTS_DCRC register field value. */
4827 #define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
4828 /* The mask used to clear the ALT_SDMMC_RINTSTS_DCRC register field value. */
4829 #define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
4830 /* The reset value of the ALT_SDMMC_RINTSTS_DCRC register field. */
4831 #define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
4832 /* Extracts the ALT_SDMMC_RINTSTS_DCRC field value from a register. */
4833 #define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
4834 /* Produces a ALT_SDMMC_RINTSTS_DCRC register field value suitable for setting the register. */
4835 #define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
4836 
4837 /*
4838  * Field : Response Timeout Boot Ack Received - bar
4839  *
4840  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4841  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4842  *
4843  * Field Enumeration Values:
4844  *
4845  * Enum | Value | Description
4846  * :------------------------------|:------|:------------------------------------------------
4847  * ALT_SDMMC_RINTSTS_BAR_E_INACT | 0x0 | Response timeout (RTO)/Boot Ack Received (BAR)
4848  * ALT_SDMMC_RINTSTS_BAR_E_ACT | 0x1 | Clears Response timeout (RTO)/Boot Ack Received
4849  * : | | (BAR)
4850  *
4851  * Field Access Macros:
4852  *
4853  */
4854 /*
4855  * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR
4856  *
4857  * Response timeout (RTO)/Boot Ack Received (BAR)
4858  */
4859 #define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
4860 /*
4861  * Enumerated value for register field ALT_SDMMC_RINTSTS_BAR
4862  *
4863  * Clears Response timeout (RTO)/Boot Ack Received (BAR)
4864  */
4865 #define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
4866 
4867 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */
4868 #define ALT_SDMMC_RINTSTS_BAR_LSB 8
4869 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BAR register field. */
4870 #define ALT_SDMMC_RINTSTS_BAR_MSB 8
4871 /* The width in bits of the ALT_SDMMC_RINTSTS_BAR register field. */
4872 #define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
4873 /* The mask used to set the ALT_SDMMC_RINTSTS_BAR register field value. */
4874 #define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
4875 /* The mask used to clear the ALT_SDMMC_RINTSTS_BAR register field value. */
4876 #define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
4877 /* The reset value of the ALT_SDMMC_RINTSTS_BAR register field. */
4878 #define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
4879 /* Extracts the ALT_SDMMC_RINTSTS_BAR field value from a register. */
4880 #define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
4881 /* Produces a ALT_SDMMC_RINTSTS_BAR register field value suitable for setting the register. */
4882 #define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
4883 
4884 /*
4885  * Field : Data Read Timeout Boot Data Start - bds
4886  *
4887  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4888  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4889  *
4890  * Field Enumeration Values:
4891  *
4892  * Enum | Value | Description
4893  * :------------------------------|:------|:------------------------------------------------
4894  * ALT_SDMMC_RINTSTS_BDS_E_INACT | 0x0 | Data read timeout (DRTO)/Boot Data Start (BDS)
4895  * ALT_SDMMC_RINTSTS_BDS_E_ACT | 0x1 | Clears Data read timeout (DRTO)/Boot Data Start
4896  * : | | (BDS)
4897  *
4898  * Field Access Macros:
4899  *
4900  */
4901 /*
4902  * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS
4903  *
4904  * Data read timeout (DRTO)/Boot Data Start (BDS)
4905  */
4906 #define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
4907 /*
4908  * Enumerated value for register field ALT_SDMMC_RINTSTS_BDS
4909  *
4910  * Clears Data read timeout (DRTO)/Boot Data Start (BDS)
4911  */
4912 #define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
4913 
4914 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */
4915 #define ALT_SDMMC_RINTSTS_BDS_LSB 9
4916 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_BDS register field. */
4917 #define ALT_SDMMC_RINTSTS_BDS_MSB 9
4918 /* The width in bits of the ALT_SDMMC_RINTSTS_BDS register field. */
4919 #define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
4920 /* The mask used to set the ALT_SDMMC_RINTSTS_BDS register field value. */
4921 #define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
4922 /* The mask used to clear the ALT_SDMMC_RINTSTS_BDS register field value. */
4923 #define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
4924 /* The reset value of the ALT_SDMMC_RINTSTS_BDS register field. */
4925 #define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
4926 /* Extracts the ALT_SDMMC_RINTSTS_BDS field value from a register. */
4927 #define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
4928 /* Produces a ALT_SDMMC_RINTSTS_BDS register field value suitable for setting the register. */
4929 #define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
4930 
4931 /*
4932  * Field : Data Starvation Host Timeout Volt Switch_int - hto
4933  *
4934  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4935  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4936  *
4937  * Field Enumeration Values:
4938  *
4939  * Enum | Value | Description
4940  * :------------------------------|:------|:---------------------------------------------
4941  * ALT_SDMMC_RINTSTS_HTO_E_INACT | 0x0 | Data starvation-by-host timeout (HTO)
4942  * : | | /Volt_switch_int
4943  * ALT_SDMMC_RINTSTS_HTO_E_ACT | 0x1 | Clears Data starvation-by-host timeout (HTO)
4944  * : | | /Volt_switch_int
4945  *
4946  * Field Access Macros:
4947  *
4948  */
4949 /*
4950  * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO
4951  *
4952  * Data starvation-by-host timeout (HTO) /Volt_switch_int
4953  */
4954 #define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
4955 /*
4956  * Enumerated value for register field ALT_SDMMC_RINTSTS_HTO
4957  *
4958  * Clears Data starvation-by-host timeout (HTO) /Volt_switch_int
4959  */
4960 #define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
4961 
4962 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */
4963 #define ALT_SDMMC_RINTSTS_HTO_LSB 10
4964 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HTO register field. */
4965 #define ALT_SDMMC_RINTSTS_HTO_MSB 10
4966 /* The width in bits of the ALT_SDMMC_RINTSTS_HTO register field. */
4967 #define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
4968 /* The mask used to set the ALT_SDMMC_RINTSTS_HTO register field value. */
4969 #define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
4970 /* The mask used to clear the ALT_SDMMC_RINTSTS_HTO register field value. */
4971 #define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
4972 /* The reset value of the ALT_SDMMC_RINTSTS_HTO register field. */
4973 #define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
4974 /* Extracts the ALT_SDMMC_RINTSTS_HTO field value from a register. */
4975 #define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
4976 /* Produces a ALT_SDMMC_RINTSTS_HTO register field value suitable for setting the register. */
4977 #define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
4978 
4979 /*
4980  * Field : FIFO Underrun Overrun Error - frun
4981  *
4982  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
4983  * leaves bit intact. Bits are logged regardless of interrupt mask status.
4984  *
4985  * Field Enumeration Values:
4986  *
4987  * Enum | Value | Description
4988  * :-------------------------------|:------|:-----------------------------------------
4989  * ALT_SDMMC_RINTSTS_FRUN_E_INACT | 0x0 | FIFO underrun/overrun error (FRUN)
4990  * ALT_SDMMC_RINTSTS_FRUN_E_ACT | 0x1 | Clear FIFO underrun/overrun error (FRUN)
4991  *
4992  * Field Access Macros:
4993  *
4994  */
4995 /*
4996  * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN
4997  *
4998  * FIFO underrun/overrun error (FRUN)
4999  */
5000 #define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5001 /*
5002  * Enumerated value for register field ALT_SDMMC_RINTSTS_FRUN
5003  *
5004  * Clear FIFO underrun/overrun error (FRUN)
5005  */
5006 #define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5007 
5008 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */
5009 #define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5010 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_FRUN register field. */
5011 #define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5012 /* The width in bits of the ALT_SDMMC_RINTSTS_FRUN register field. */
5013 #define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5014 /* The mask used to set the ALT_SDMMC_RINTSTS_FRUN register field value. */
5015 #define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5016 /* The mask used to clear the ALT_SDMMC_RINTSTS_FRUN register field value. */
5017 #define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5018 /* The reset value of the ALT_SDMMC_RINTSTS_FRUN register field. */
5019 #define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5020 /* Extracts the ALT_SDMMC_RINTSTS_FRUN field value from a register. */
5021 #define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5022 /* Produces a ALT_SDMMC_RINTSTS_FRUN register field value suitable for setting the register. */
5023 #define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5024 
5025 /*
5026  * Field : Hardware Locked Write Error - hle
5027  *
5028  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5029  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5030  *
5031  * Field Enumeration Values:
5032  *
5033  * Enum | Value | Description
5034  * :------------------------------|:------|:-----------------------------------------
5035  * ALT_SDMMC_RINTSTS_HLE_E_INACT | 0x0 | Hardware locked write error (HLE)
5036  * ALT_SDMMC_RINTSTS_HLE_E_ACT | 0x1 | Clears Hardware locked write error (HLE)
5037  *
5038  * Field Access Macros:
5039  *
5040  */
5041 /*
5042  * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE
5043  *
5044  * Hardware locked write error (HLE)
5045  */
5046 #define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5047 /*
5048  * Enumerated value for register field ALT_SDMMC_RINTSTS_HLE
5049  *
5050  * Clears Hardware locked write error (HLE)
5051  */
5052 #define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5053 
5054 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */
5055 #define ALT_SDMMC_RINTSTS_HLE_LSB 12
5056 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_HLE register field. */
5057 #define ALT_SDMMC_RINTSTS_HLE_MSB 12
5058 /* The width in bits of the ALT_SDMMC_RINTSTS_HLE register field. */
5059 #define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5060 /* The mask used to set the ALT_SDMMC_RINTSTS_HLE register field value. */
5061 #define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5062 /* The mask used to clear the ALT_SDMMC_RINTSTS_HLE register field value. */
5063 #define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5064 /* The reset value of the ALT_SDMMC_RINTSTS_HLE register field. */
5065 #define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5066 /* Extracts the ALT_SDMMC_RINTSTS_HLE field value from a register. */
5067 #define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5068 /* Produces a ALT_SDMMC_RINTSTS_HLE register field value suitable for setting the register. */
5069 #define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5070 
5071 /*
5072  * Field : Start-bit error (SBE) - sbe
5073  *
5074  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5075  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5076  *
5077  * Field Enumeration Values:
5078  *
5079  * Enum | Value | Description
5080  * :------------------------------|:------|:-----------------------------
5081  * ALT_SDMMC_RINTSTS_SBE_E_INACT | 0x0 | Start-bit error (SBE)
5082  * ALT_SDMMC_RINTSTS_SBE_E_ACT | 0x1 | Clears Start-bit error (SBE)
5083  *
5084  * Field Access Macros:
5085  *
5086  */
5087 /*
5088  * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE
5089  *
5090  * Start-bit error (SBE)
5091  */
5092 #define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5093 /*
5094  * Enumerated value for register field ALT_SDMMC_RINTSTS_SBE
5095  *
5096  * Clears Start-bit error (SBE)
5097  */
5098 #define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5099 
5100 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */
5101 #define ALT_SDMMC_RINTSTS_SBE_LSB 13
5102 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SBE register field. */
5103 #define ALT_SDMMC_RINTSTS_SBE_MSB 13
5104 /* The width in bits of the ALT_SDMMC_RINTSTS_SBE register field. */
5105 #define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5106 /* The mask used to set the ALT_SDMMC_RINTSTS_SBE register field value. */
5107 #define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5108 /* The mask used to clear the ALT_SDMMC_RINTSTS_SBE register field value. */
5109 #define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5110 /* The reset value of the ALT_SDMMC_RINTSTS_SBE register field. */
5111 #define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5112 /* Extracts the ALT_SDMMC_RINTSTS_SBE field value from a register. */
5113 #define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5114 /* Produces a ALT_SDMMC_RINTSTS_SBE register field value suitable for setting the register. */
5115 #define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5116 
5117 /*
5118  * Field : Auto Cmommand Done - acd
5119  *
5120  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5121  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5122  *
5123  * Field Enumeration Values:
5124  *
5125  * Enum | Value | Description
5126  * :------------------------------|:------|:-----------------------------
5127  * ALT_SDMMC_RINTSTS_ACD_E_INACT | 0x0 | Auto command done (ACD)
5128  * ALT_SDMMC_RINTSTS_ACD_E_ACT | 0x1 | Clear Auto command done (ACD
5129  *
5130  * Field Access Macros:
5131  *
5132  */
5133 /*
5134  * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD
5135  *
5136  * Auto command done (ACD)
5137  */
5138 #define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5139 /*
5140  * Enumerated value for register field ALT_SDMMC_RINTSTS_ACD
5141  *
5142  * Clear Auto command done (ACD
5143  */
5144 #define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5145 
5146 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */
5147 #define ALT_SDMMC_RINTSTS_ACD_LSB 14
5148 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_ACD register field. */
5149 #define ALT_SDMMC_RINTSTS_ACD_MSB 14
5150 /* The width in bits of the ALT_SDMMC_RINTSTS_ACD register field. */
5151 #define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5152 /* The mask used to set the ALT_SDMMC_RINTSTS_ACD register field value. */
5153 #define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5154 /* The mask used to clear the ALT_SDMMC_RINTSTS_ACD register field value. */
5155 #define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5156 /* The reset value of the ALT_SDMMC_RINTSTS_ACD register field. */
5157 #define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5158 /* Extracts the ALT_SDMMC_RINTSTS_ACD field value from a register. */
5159 #define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5160 /* Produces a ALT_SDMMC_RINTSTS_ACD register field value suitable for setting the register. */
5161 #define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5162 
5163 /*
5164  * Field : End-bit Error - ebe
5165  *
5166  * Writes to bits clear status bit. Value of 1 clears status bit, and value of 0
5167  * leaves bit intact. Bits are logged regardless of interrupt mask status.
5168  *
5169  * Field Enumeration Values:
5170  *
5171  * Enum | Value | Description
5172  * :------------------------------|:------|:-----------------------------------------------
5173  * ALT_SDMMC_RINTSTS_EBE_E_INACT | 0x0 | End-bit error (read)/write no CRC (EBE)
5174  * ALT_SDMMC_RINTSTS_EBE_E_ACT | 0x1 | Clears End-bit error (read)/write no CRC (EBE)
5175  *
5176  * Field Access Macros:
5177  *
5178  */
5179 /*
5180  * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE
5181  *
5182  * End-bit error (read)/write no CRC (EBE)
5183  */
5184 #define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5185 /*
5186  * Enumerated value for register field ALT_SDMMC_RINTSTS_EBE
5187  *
5188  * Clears End-bit error (read)/write no CRC (EBE)
5189  */
5190 #define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5191 
5192 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */
5193 #define ALT_SDMMC_RINTSTS_EBE_LSB 15
5194 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_EBE register field. */
5195 #define ALT_SDMMC_RINTSTS_EBE_MSB 15
5196 /* The width in bits of the ALT_SDMMC_RINTSTS_EBE register field. */
5197 #define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5198 /* The mask used to set the ALT_SDMMC_RINTSTS_EBE register field value. */
5199 #define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5200 /* The mask used to clear the ALT_SDMMC_RINTSTS_EBE register field value. */
5201 #define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5202 /* The reset value of the ALT_SDMMC_RINTSTS_EBE register field. */
5203 #define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5204 /* Extracts the ALT_SDMMC_RINTSTS_EBE field value from a register. */
5205 #define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5206 /* Produces a ALT_SDMMC_RINTSTS_EBE register field value suitable for setting the register. */
5207 #define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5208 
5209 /*
5210  * Field : SDIO Interrupt - sdio_interrupt
5211  *
5212  * Interrupt from SDIO card.
5213  *
5214  * Field Enumeration Values:
5215  *
5216  * Enum | Value | Description
5217  * :-----------------------------------|:------|:-------------------------------
5218  * ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT | 0x1 | SDIO interrupt from card bit
5219  * ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT | 0x0 | No SDIO interrupt from card bi
5220  *
5221  * Field Access Macros:
5222  *
5223  */
5224 /*
5225  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT
5226  *
5227  * SDIO interrupt from card bit
5228  */
5229 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5230 /*
5231  * Enumerated value for register field ALT_SDMMC_RINTSTS_SDIO_INT
5232  *
5233  * No SDIO interrupt from card bi
5234  */
5235 #define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5236 
5237 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5238 #define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5239 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5240 #define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 16
5241 /* The width in bits of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5242 #define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 1
5243 /* The mask used to set the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */
5244 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0x00010000
5245 /* The mask used to clear the ALT_SDMMC_RINTSTS_SDIO_INT register field value. */
5246 #define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
5247 /* The reset value of the ALT_SDMMC_RINTSTS_SDIO_INT register field. */
5248 #define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5249 /* Extracts the ALT_SDMMC_RINTSTS_SDIO_INT field value from a register. */
5250 #define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
5251 /* Produces a ALT_SDMMC_RINTSTS_SDIO_INT register field value suitable for setting the register. */
5252 #define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
5253 
5254 #ifndef __ASSEMBLY__
5255 /*
5256  * WARNING: The C register and register group struct declarations are provided for
5257  * convenience and illustrative purposes. They should, however, be used with
5258  * caution as the C language standard provides no guarantees about the alignment or
5259  * atomicity of device memory accesses. The recommended practice for writing
5260  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5261  * alt_write_word() functions.
5262  *
5263  * The struct declaration for register ALT_SDMMC_RINTSTS.
5264  */
5265 struct ALT_SDMMC_RINTSTS_s
5266 {
5267  uint32_t cd : 1; /* Card Detect */
5268  uint32_t re : 1; /* Response Error */
5269  uint32_t cmd : 1; /* Command Done */
5270  uint32_t dto : 1; /* Data Transfer Over */
5271  uint32_t txdr : 1; /* Transmit FIFO Data Request */
5272  uint32_t rxdr : 1; /* Receive FIFO Data Request */
5273  uint32_t rcrc : 1; /* Response CRC Error */
5274  uint32_t dcrc : 1; /* Data CRC Error */
5275  uint32_t bar : 1; /* Response Timeout Boot Ack Received */
5276  uint32_t bds : 1; /* Data Read Timeout Boot Data Start */
5277  uint32_t hto : 1; /* Data Starvation Host Timeout Volt Switch_int */
5278  uint32_t frun : 1; /* FIFO Underrun Overrun Error */
5279  uint32_t hle : 1; /* Hardware Locked Write Error */
5280  uint32_t sbe : 1; /* Start-bit error (SBE) */
5281  uint32_t acd : 1; /* Auto Cmommand Done */
5282  uint32_t ebe : 1; /* End-bit Error */
5283  uint32_t sdio_interrupt : 1; /* SDIO Interrupt */
5284  uint32_t : 15; /* *UNDEFINED* */
5285 };
5286 
5287 /* The typedef declaration for register ALT_SDMMC_RINTSTS. */
5288 typedef volatile struct ALT_SDMMC_RINTSTS_s ALT_SDMMC_RINTSTS_t;
5289 #endif /* __ASSEMBLY__ */
5290 
5291 /* The byte offset of the ALT_SDMMC_RINTSTS register from the beginning of the component. */
5292 #define ALT_SDMMC_RINTSTS_OFST 0x44
5293 
5294 /*
5295  * Register : Status Register - status
5296  *
5297  * Reports various operting status conditions.
5298  *
5299  * Register Layout
5300  *
5301  * Bits | Access | Reset | Description
5302  * :--------|:-------|:------|:-------------------
5303  * [0] | R | 0x0 | FIFO Rx Watermark
5304  * [1] | R | 0x1 | FIFO Tx Watermark
5305  * [2] | R | 0x1 | FIFO Empty
5306  * [3] | R | 0x0 | FIFO Full
5307  * [7:4] | R | 0x0 | Command FSM States
5308  * [8] | R | 0x1 | Data 3 Status
5309  * [9] | R | 0x0 | Data Busy
5310  * [10] | R | 0x0 | Data State MC Busy
5311  * [16:11] | R | 0x0 | Response Index
5312  * [29:17] | R | 0x0 | FIFO Count
5313  * [31:30] | ??? | 0x0 | *UNDEFINED*
5314  *
5315  */
5316 /*
5317  * Field : FIFO Rx Watermark - fifo_rx_watermark
5318  *
5319  * FIFO reached Receive watermark level; not qualified with data transfer
5320  *
5321  * Field Enumeration Values:
5322  *
5323  * Enum | Value | Description
5324  * :-------------------------------------------------|:------|:-------------------------------------------------
5325  * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK | 0x0 | FIFO reached watermark level; not qualified with
5326  * : | | data transfer.
5327  * ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK | 0x1 | FIFO not at watermark Level
5328  *
5329  * Field Access Macros:
5330  *
5331  */
5332 /*
5333  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK
5334  *
5335  * FIFO reached watermark level; not qualified with data transfer.
5336  */
5337 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5338 /*
5339  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_RX_WATERMARK
5340  *
5341  * FIFO not at watermark Level
5342  */
5343 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5344 
5345 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5346 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5347 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5348 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5349 /* The width in bits of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5350 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5351 /* The mask used to set the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */
5352 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5353 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value. */
5354 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5355 /* The reset value of the ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field. */
5356 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5357 /* Extracts the ALT_SDMMC_STAT_FIFO_RX_WATERMARK field value from a register. */
5358 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5359 /* Produces a ALT_SDMMC_STAT_FIFO_RX_WATERMARK register field value suitable for setting the register. */
5360 #define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5361 
5362 /*
5363  * Field : FIFO Tx Watermark - fifo_tx_watermark
5364  *
5365  * FIFO reached Transmit watermark level; not qualified with data transfer.
5366  *
5367  * Field Enumeration Values:
5368  *
5369  * Enum | Value | Description
5370  * :-------------------------------------------------|:------|:-------------------------------------------
5371  * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK | 0x1 | FIFO reached transmit watermark level: not
5372  * : | | qualified with data transfer.
5373  * ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK | 0x0 | FIFO not at transmit watermark Level
5374  *
5375  * Field Access Macros:
5376  *
5377  */
5378 /*
5379  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK
5380  *
5381  * FIFO reached transmit watermark level: not qualified with data transfer.
5382  */
5383 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5384 /*
5385  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_TX_WATERMARK
5386  *
5387  * FIFO not at transmit watermark Level
5388  */
5389 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5390 
5391 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5392 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5393 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5394 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5395 /* The width in bits of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5396 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5397 /* The mask used to set the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */
5398 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5399 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value. */
5400 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5401 /* The reset value of the ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field. */
5402 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5403 /* Extracts the ALT_SDMMC_STAT_FIFO_TX_WATERMARK field value from a register. */
5404 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5405 /* Produces a ALT_SDMMC_STAT_FIFO_TX_WATERMARK register field value suitable for setting the register. */
5406 #define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5407 
5408 /*
5409  * Field : FIFO Empty - fifo_empty
5410  *
5411  * FIFO is empty status.
5412  *
5413  * Field Enumeration Values:
5414  *
5415  * Enum | Value | Description
5416  * :-----------------------------------------|:------|:---------------
5417  * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY | 0x1 | FIFO is empty
5418  * ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY | 0x0 | FIFO not empty
5419  *
5420  * Field Access Macros:
5421  *
5422  */
5423 /*
5424  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY
5425  *
5426  * FIFO is empty
5427  */
5428 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5429 /*
5430  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_EMPTY
5431  *
5432  * FIFO not empty
5433  */
5434 #define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5435 
5436 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5437 #define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5438 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5439 #define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5440 /* The width in bits of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5441 #define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5442 /* The mask used to set the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */
5443 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5444 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_EMPTY register field value. */
5445 #define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5446 /* The reset value of the ALT_SDMMC_STAT_FIFO_EMPTY register field. */
5447 #define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5448 /* Extracts the ALT_SDMMC_STAT_FIFO_EMPTY field value from a register. */
5449 #define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5450 /* Produces a ALT_SDMMC_STAT_FIFO_EMPTY register field value suitable for setting the register. */
5451 #define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5452 
5453 /*
5454  * Field : FIFO Full - fifo_full
5455  *
5456  * FIFO is full status.
5457  *
5458  * Field Enumeration Values:
5459  *
5460  * Enum | Value | Description
5461  * :---------------------------------------|:------|:-----------------
5462  * ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL | 0x0 | FIFO is full
5463  * ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL | 0x1 | FIFO is not full
5464  *
5465  * Field Access Macros:
5466  *
5467  */
5468 /*
5469  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL
5470  *
5471  * FIFO is full
5472  */
5473 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x0
5474 /*
5475  * Enumerated value for register field ALT_SDMMC_STAT_FIFO_FULL
5476  *
5477  * FIFO is not full
5478  */
5479 #define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x1
5480 
5481 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5482 #define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5483 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5484 #define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5485 /* The width in bits of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5486 #define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5487 /* The mask used to set the ALT_SDMMC_STAT_FIFO_FULL register field value. */
5488 #define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5489 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_FULL register field value. */
5490 #define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5491 /* The reset value of the ALT_SDMMC_STAT_FIFO_FULL register field. */
5492 #define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5493 /* Extracts the ALT_SDMMC_STAT_FIFO_FULL field value from a register. */
5494 #define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5495 /* Produces a ALT_SDMMC_STAT_FIFO_FULL register field value suitable for setting the register. */
5496 #define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
5497 
5498 /*
5499  * Field : Command FSM States - command_fsm_states
5500  *
5501  * The command FSM state.
5502  *
5503  * Field Enumeration Values:
5504  *
5505  * Enum | Value | Description
5506  * :----------------------------------------------|:------|:--------------------------------------------
5507  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS | 0x0 | Idle, Wait for CCS, Send CCSD, or Boot Mode
5508  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ | 0x1 | Send init sequence
5509  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART | 0x2 | Tx cmd start bit
5510  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT | 0x3 | Tx cmd tx bit
5511  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG | 0x4 | Tx cmd index + arg
5512  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 | 0x5 | Tx cmd crc7
5513  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND | 0x6 | Tx cmd end bit
5514  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART | 0x7 | Rx resp start bit
5515  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ | 0x8 | Rx resp IRQ response
5516  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX | 0x9 | Rx resp tx bit
5517  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX | 0xa | Rx resp cmd idx
5518  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA | 0xb | Rx resp data
5519  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 | 0xc | Rx resp crc7
5520  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND | 0xd | Rx resp end bit
5521  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT | 0xe | Cmd path wait NCC
5522  * ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN | 0xf | Wait: CMD-to-reponse turnaround
5523  *
5524  * Field Access Macros:
5525  *
5526  */
5527 /*
5528  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5529  *
5530  * Idle, Wait for CCS, Send CCSD, or Boot Mode
5531  */
5532 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
5533 /*
5534  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5535  *
5536  * Send init sequence
5537  */
5538 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
5539 /*
5540  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5541  *
5542  * Tx cmd start bit
5543  */
5544 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
5545 /*
5546  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5547  *
5548  * Tx cmd tx bit
5549  */
5550 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
5551 /*
5552  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5553  *
5554  * Tx cmd index + arg
5555  */
5556 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
5557 /*
5558  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5559  *
5560  * Tx cmd crc7
5561  */
5562 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
5563 /*
5564  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5565  *
5566  * Tx cmd end bit
5567  */
5568 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
5569 /*
5570  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5571  *
5572  * Rx resp start bit
5573  */
5574 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
5575 /*
5576  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5577  *
5578  * Rx resp IRQ response
5579  */
5580 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
5581 /*
5582  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5583  *
5584  * Rx resp tx bit
5585  */
5586 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
5587 /*
5588  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5589  *
5590  * Rx resp cmd idx
5591  */
5592 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
5593 /*
5594  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5595  *
5596  * Rx resp data
5597  */
5598 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
5599 /*
5600  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5601  *
5602  * Rx resp crc7
5603  */
5604 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
5605 /*
5606  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5607  *
5608  * Rx resp end bit
5609  */
5610 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
5611 /*
5612  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5613  *
5614  * Cmd path wait NCC
5615  */
5616 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
5617 /*
5618  * Enumerated value for register field ALT_SDMMC_STAT_CMD_FSM_STATES
5619  *
5620  * Wait: CMD-to-reponse turnaround
5621  */
5622 #define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
5623 
5624 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
5625 #define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
5626 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
5627 #define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
5628 /* The width in bits of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
5629 #define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
5630 /* The mask used to set the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */
5631 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
5632 /* The mask used to clear the ALT_SDMMC_STAT_CMD_FSM_STATES register field value. */
5633 #define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
5634 /* The reset value of the ALT_SDMMC_STAT_CMD_FSM_STATES register field. */
5635 #define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
5636 /* Extracts the ALT_SDMMC_STAT_CMD_FSM_STATES field value from a register. */
5637 #define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
5638 /* Produces a ALT_SDMMC_STAT_CMD_FSM_STATES register field value suitable for setting the register. */
5639 #define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
5640 
5641 /*
5642  * Field : Data 3 Status - data_3_status
5643  *
5644  * Raw selected card_data[3]; checks whether card is present. The default can be
5645  * cardpresent or not present depend on cdata_in.
5646  *
5647  * Field Enumeration Values:
5648  *
5649  * Enum | Value | Description
5650  * :--------------------------------------------|:------|:-----------------
5651  * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT | 0x1 | Card Present
5652  * ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT | 0x0 | Card Not Present
5653  *
5654  * Field Access Macros:
5655  *
5656  */
5657 /*
5658  * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT
5659  *
5660  * Card Present
5661  */
5662 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
5663 /*
5664  * Enumerated value for register field ALT_SDMMC_STAT_DATA_3_STAT
5665  *
5666  * Card Not Present
5667  */
5668 #define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
5669 
5670 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
5671 #define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
5672 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
5673 #define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
5674 /* The width in bits of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
5675 #define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
5676 /* The mask used to set the ALT_SDMMC_STAT_DATA_3_STAT register field value. */
5677 #define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
5678 /* The mask used to clear the ALT_SDMMC_STAT_DATA_3_STAT register field value. */
5679 #define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
5680 /* The reset value of the ALT_SDMMC_STAT_DATA_3_STAT register field. */
5681 #define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
5682 /* Extracts the ALT_SDMMC_STAT_DATA_3_STAT field value from a register. */
5683 #define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
5684 /* Produces a ALT_SDMMC_STAT_DATA_3_STAT register field value suitable for setting the register. */
5685 #define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
5686 
5687 /*
5688  * Field : Data Busy - data_busy
5689  *
5690  * Inverted version of raw selected card_data[0]. The default can be cardpresent or
5691  * not present depend on cdata_in.
5692  *
5693  * Field Enumeration Values:
5694  *
5695  * Enum | Value | Description
5696  * :---------------------------------------|:------|:-------------------
5697  * ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY | 0x1 | card data busy
5698  * ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY | 0x0 | card data not busy
5699  *
5700  * Field Access Macros:
5701  *
5702  */
5703 /*
5704  * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY
5705  *
5706  * card data busy
5707  */
5708 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
5709 /*
5710  * Enumerated value for register field ALT_SDMMC_STAT_DATA_BUSY
5711  *
5712  * card data not busy
5713  */
5714 #define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
5715 
5716 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */
5717 #define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
5718 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_BUSY register field. */
5719 #define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
5720 /* The width in bits of the ALT_SDMMC_STAT_DATA_BUSY register field. */
5721 #define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
5722 /* The mask used to set the ALT_SDMMC_STAT_DATA_BUSY register field value. */
5723 #define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
5724 /* The mask used to clear the ALT_SDMMC_STAT_DATA_BUSY register field value. */
5725 #define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
5726 /* The reset value of the ALT_SDMMC_STAT_DATA_BUSY register field. */
5727 #define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
5728 /* Extracts the ALT_SDMMC_STAT_DATA_BUSY field value from a register. */
5729 #define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
5730 /* Produces a ALT_SDMMC_STAT_DATA_BUSY register field value suitable for setting the register. */
5731 #define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
5732 
5733 /*
5734  * Field : Data State MC Busy - data_state_mc_busy
5735  *
5736  * Data transmit or receive state-machine is busy.
5737  *
5738  * Field Enumeration Values:
5739  *
5740  * Enum | Value | Description
5741  * :----------------------------------------------------|:------|:-----------------------
5742  * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY | 0x1 | Data State MC busy
5743  * ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY | 0x0 | Data State MC not busy
5744  *
5745  * Field Access Macros:
5746  *
5747  */
5748 /*
5749  * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY
5750  *
5751  * Data State MC busy
5752  */
5753 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
5754 /*
5755  * Enumerated value for register field ALT_SDMMC_STAT_DATA_STATE_MC_BUSY
5756  *
5757  * Data State MC not busy
5758  */
5759 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
5760 
5761 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
5762 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
5763 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
5764 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
5765 /* The width in bits of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
5766 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
5767 /* The mask used to set the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */
5768 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
5769 /* The mask used to clear the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value. */
5770 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
5771 /* The reset value of the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field. */
5772 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
5773 /* Extracts the ALT_SDMMC_STAT_DATA_STATE_MC_BUSY field value from a register. */
5774 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
5775 /* Produces a ALT_SDMMC_STAT_DATA_STATE_MC_BUSY register field value suitable for setting the register. */
5776 #define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
5777 
5778 /*
5779  * Field : Response Index - response_index
5780  *
5781  * Index of previous response, including any auto-stop sent by core
5782  *
5783  * Field Access Macros:
5784  *
5785  */
5786 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
5787 #define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
5788 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
5789 #define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
5790 /* The width in bits of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
5791 #define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
5792 /* The mask used to set the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */
5793 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
5794 /* The mask used to clear the ALT_SDMMC_STAT_RESPONSE_INDEX register field value. */
5795 #define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
5796 /* The reset value of the ALT_SDMMC_STAT_RESPONSE_INDEX register field. */
5797 #define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
5798 /* Extracts the ALT_SDMMC_STAT_RESPONSE_INDEX field value from a register. */
5799 #define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
5800 /* Produces a ALT_SDMMC_STAT_RESPONSE_INDEX register field value suitable for setting the register. */
5801 #define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
5802 
5803 /*
5804  * Field : FIFO Count - fifo_count
5805  *
5806  * FIFO count - Number of filled locations in FIFO
5807  *
5808  * Field Access Macros:
5809  *
5810  */
5811 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
5812 #define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
5813 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
5814 #define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
5815 /* The width in bits of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
5816 #define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
5817 /* The mask used to set the ALT_SDMMC_STAT_FIFO_COUNT register field value. */
5818 #define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
5819 /* The mask used to clear the ALT_SDMMC_STAT_FIFO_COUNT register field value. */
5820 #define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
5821 /* The reset value of the ALT_SDMMC_STAT_FIFO_COUNT register field. */
5822 #define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
5823 /* Extracts the ALT_SDMMC_STAT_FIFO_COUNT field value from a register. */
5824 #define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
5825 /* Produces a ALT_SDMMC_STAT_FIFO_COUNT register field value suitable for setting the register. */
5826 #define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
5827 
5828 #ifndef __ASSEMBLY__
5829 /*
5830  * WARNING: The C register and register group struct declarations are provided for
5831  * convenience and illustrative purposes. They should, however, be used with
5832  * caution as the C language standard provides no guarantees about the alignment or
5833  * atomicity of device memory accesses. The recommended practice for writing
5834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5835  * alt_write_word() functions.
5836  *
5837  * The struct declaration for register ALT_SDMMC_STAT.
5838  */
5839 struct ALT_SDMMC_STAT_s
5840 {
5841  const uint32_t fifo_rx_watermark : 1; /* FIFO Rx Watermark */
5842  const uint32_t fifo_tx_watermark : 1; /* FIFO Tx Watermark */
5843  const uint32_t fifo_empty : 1; /* FIFO Empty */
5844  const uint32_t fifo_full : 1; /* FIFO Full */
5845  const uint32_t command_fsm_states : 4; /* Command FSM States */
5846  const uint32_t data_3_status : 1; /* Data 3 Status */
5847  const uint32_t data_busy : 1; /* Data Busy */
5848  const uint32_t data_state_mc_busy : 1; /* Data State MC Busy */
5849  const uint32_t response_index : 6; /* Response Index */
5850  const uint32_t fifo_count : 13; /* FIFO Count */
5851  uint32_t : 2; /* *UNDEFINED* */
5852 };
5853 
5854 /* The typedef declaration for register ALT_SDMMC_STAT. */
5855 typedef volatile struct ALT_SDMMC_STAT_s ALT_SDMMC_STAT_t;
5856 #endif /* __ASSEMBLY__ */
5857 
5858 /* The byte offset of the ALT_SDMMC_STAT register from the beginning of the component. */
5859 #define ALT_SDMMC_STAT_OFST 0x48
5860 
5861 /*
5862  * Register : FIFO Threshold Watermark Register - fifoth
5863  *
5864  * DMA and FIFO Control Fields.
5865  *
5866  * Register Layout
5867  *
5868  * Bits | Access | Reset | Description
5869  * :--------|:-------|:------|:------------------------------
5870  * [11:0] | RW | 0x0 | Tx WMark
5871  * [15:12] | ??? | 0x0 | *UNDEFINED*
5872  * [27:16] | RW | 0x3ff | Rx WMark
5873  * [30:28] | RW | 0x0 | DMA Multiple Transaction Size
5874  * [31] | ??? | 0x0 | *UNDEFINED*
5875  *
5876  */
5877 /*
5878  * Field : Tx WMark - tx_wmark
5879  *
5880  * FIFO threshold watermark level when transmitting data to card. When FIFO data
5881  * count is less than or equal to this number, DMA/FIFO request is raised. If
5882  * Interrupt is enabled, then interrupt occurs. During end of packet, request or
5883  * interrupt is generated, regardless of threshold programming. In non-DMA mode,
5884  * when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is
5885  * generated instead of DMA request. During end of packet, on last interrupt, host
5886  * is responsible for filling FIFO with only required remaining bytes (not before
5887  * FIFO is full or after CIU completes data transfers, because FIFO may not be
5888  * empty). In DMA mode, at end of packet, if last transfer is less than burst size,
5889  * DMA controller does single cycles until required bytes are transferred. 12 bits
5890  * - 1 bit less than FIFO-count of status register, which is 13 bits.
5891  *
5892  * Limitation: TX_WMark >= 1;
5893  *
5894  * Recommended: FIFO_DEPTH/2 = 512; (means less than or equal to 512)
5895  *
5896  * Field Access Macros:
5897  *
5898  */
5899 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
5900 #define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
5901 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
5902 #define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
5903 /* The width in bits of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
5904 #define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
5905 /* The mask used to set the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
5906 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
5907 /* The mask used to clear the ALT_SDMMC_FIFOTH_TX_WMARK register field value. */
5908 #define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
5909 /* The reset value of the ALT_SDMMC_FIFOTH_TX_WMARK register field. */
5910 #define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
5911 /* Extracts the ALT_SDMMC_FIFOTH_TX_WMARK field value from a register. */
5912 #define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
5913 /* Produces a ALT_SDMMC_FIFOTH_TX_WMARK register field value suitable for setting the register. */
5914 #define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
5915 
5916 /*
5917  * Field : Rx WMark - rx_wmark
5918  *
5919  * FIFO threshold watermark level when receiving data to card. When FIFO data count
5920  * reaches greater than this number, DMA/FIFO request is raised. During end of
5921  * packet, request is generated regardless of threshold programming in order to
5922  * complete any remaining data. In non-DMA mode, when receiver FIFO threshold
5923  * (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.
5924  * During end of packet, interrupt is not generated if threshold programming is
5925  * larger than any remaining data. It is responsibility of host to read remaining
5926  * bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet,
5927  * even if remaining bytes are less than threshold, DMA request does single
5928  * transfers to flush out any remaining bytes before Data Transfer Done interrupt
5929  * is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13
5930  * bits.
5931  *
5932  * Limitation: RX_WMark <= 1022
5933  *
5934  * Recommended: 511; means greater than (FIFO_DEPTH/2) - 1)
5935  *
5936  * NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at
5937  * the end of packet, even if remaining bytes are less than threshold. In this
5938  * case, there will be some data left in the FIFO. It is the responsibility of the
5939  * application to reset the FIFO after the CCS timeout.
5940  *
5941  * Field Access Macros:
5942  *
5943  */
5944 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
5945 #define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
5946 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
5947 #define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
5948 /* The width in bits of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
5949 #define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
5950 /* The mask used to set the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
5951 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
5952 /* The mask used to clear the ALT_SDMMC_FIFOTH_RX_WMARK register field value. */
5953 #define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
5954 /* The reset value of the ALT_SDMMC_FIFOTH_RX_WMARK register field. */
5955 #define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
5956 /* Extracts the ALT_SDMMC_FIFOTH_RX_WMARK field value from a register. */
5957 #define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
5958 /* Produces a ALT_SDMMC_FIFOTH_RX_WMARK register field value suitable for setting the register. */
5959 #define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
5960 
5961 /*
5962  * Field : DMA Multiple Transaction Size - dw_dma_multiple_transaction_size
5963  *
5964  * Burst size of multiple transaction; should be programmed same as DMA controller
5965  * multiple-transaction-size SRC/DEST_MSIZE.
5966  *
5967  * The units for transfers is 32 bits. A single transfer would be signalled based
5968  * on this value. Value should be sub-multiple of 512. Allowed combinations for
5969  * MSize and TX_WMark.
5970  *
5971  * Field Enumeration Values:
5972  *
5973  * Enum | Value | Description
5974  * :-----------------------------------------------------------|:------|:----------------------------
5975  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 | 0x0 | Msize 1 and TX_WMARK 1-1023
5976  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 | 0x1 | Msize 4 and TX_WMARK 256
5977  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 | 0x2 | Msize 8 and TX_WMARK 128
5978  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 | 0x3 | Msize 16 and TX_WMARK 64
5979  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 | 0x5 | Msize 1 and RX_WMARK 512
5980  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 | 0x6 | Msize 4 and RX_WMARK 128
5981  * ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 | 0x7 | Msize 8 and RX_WMARK 64
5982  *
5983  * Field Access Macros:
5984  *
5985  */
5986 /*
5987  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
5988  *
5989  * Msize 1 and TX_WMARK 1-1023
5990  */
5991 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
5992 /*
5993  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
5994  *
5995  * Msize 4 and TX_WMARK 256
5996  */
5997 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
5998 /*
5999  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6000  *
6001  * Msize 8 and TX_WMARK 128
6002  */
6003 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6004 /*
6005  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6006  *
6007  * Msize 16 and TX_WMARK 64
6008  */
6009 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6010 /*
6011  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6012  *
6013  * Msize 1 and RX_WMARK 512
6014  */
6015 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6016 /*
6017  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6018  *
6019  * Msize 4 and RX_WMARK 128
6020  */
6021 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6022 /*
6023  * Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
6024  *
6025  * Msize 8 and RX_WMARK 64
6026  */
6027 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6028 
6029 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6030 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6031 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6032 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6033 /* The width in bits of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6034 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6035 /* The mask used to set the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */
6036 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6037 /* The mask used to clear the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value. */
6038 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6039 /* The reset value of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field. */
6040 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6041 /* Extracts the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE field value from a register. */
6042 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6043 /* Produces a ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value suitable for setting the register. */
6044 #define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6045 
6046 #ifndef __ASSEMBLY__
6047 /*
6048  * WARNING: The C register and register group struct declarations are provided for
6049  * convenience and illustrative purposes. They should, however, be used with
6050  * caution as the C language standard provides no guarantees about the alignment or
6051  * atomicity of device memory accesses. The recommended practice for writing
6052  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6053  * alt_write_word() functions.
6054  *
6055  * The struct declaration for register ALT_SDMMC_FIFOTH.
6056  */
6057 struct ALT_SDMMC_FIFOTH_s
6058 {
6059  uint32_t tx_wmark : 12; /* Tx WMark */
6060  uint32_t : 4; /* *UNDEFINED* */
6061  uint32_t rx_wmark : 12; /* Rx WMark */
6062  uint32_t dw_dma_multiple_transaction_size : 3; /* DMA Multiple Transaction Size */
6063  uint32_t : 1; /* *UNDEFINED* */
6064 };
6065 
6066 /* The typedef declaration for register ALT_SDMMC_FIFOTH. */
6067 typedef volatile struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t;
6068 #endif /* __ASSEMBLY__ */
6069 
6070 /* The byte offset of the ALT_SDMMC_FIFOTH register from the beginning of the component. */
6071 #define ALT_SDMMC_FIFOTH_OFST 0x4c
6072 
6073 /*
6074  * Register : Card Detect Register - cdetect
6075  *
6076  * Determines if card is present.
6077  *
6078  * Register Layout
6079  *
6080  * Bits | Access | Reset | Description
6081  * :-------|:-------|:------|:------------
6082  * [0] | R | 0x1 | Card Detect
6083  * [31:1] | ??? | 0x0 | *UNDEFINED*
6084  *
6085  */
6086 /*
6087  * Field : Card Detect - card_detect_n
6088  *
6089  * Value on sdmmc_cd_i input port.
6090  *
6091  * Field Enumeration Values:
6092  *
6093  * Enum | Value | Description
6094  * :----------------------------------------------|:------|:------------------
6095  * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED | 0x1 | Card not Detected
6096  * ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED | 0x0 | Card Detected
6097  *
6098  * Field Access Macros:
6099  *
6100  */
6101 /*
6102  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N
6103  *
6104  * Card not Detected
6105  */
6106 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6107 /*
6108  * Enumerated value for register field ALT_SDMMC_CDETECT_CARD_DETECT_N
6109  *
6110  * Card Detected
6111  */
6112 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6113 
6114 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6115 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6116 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6117 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6118 /* The width in bits of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6119 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6120 /* The mask used to set the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */
6121 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6122 /* The mask used to clear the ALT_SDMMC_CDETECT_CARD_DETECT_N register field value. */
6123 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6124 /* The reset value of the ALT_SDMMC_CDETECT_CARD_DETECT_N register field. */
6125 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6126 /* Extracts the ALT_SDMMC_CDETECT_CARD_DETECT_N field value from a register. */
6127 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6128 /* Produces a ALT_SDMMC_CDETECT_CARD_DETECT_N register field value suitable for setting the register. */
6129 #define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6130 
6131 #ifndef __ASSEMBLY__
6132 /*
6133  * WARNING: The C register and register group struct declarations are provided for
6134  * convenience and illustrative purposes. They should, however, be used with
6135  * caution as the C language standard provides no guarantees about the alignment or
6136  * atomicity of device memory accesses. The recommended practice for writing
6137  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6138  * alt_write_word() functions.
6139  *
6140  * The struct declaration for register ALT_SDMMC_CDETECT.
6141  */
6142 struct ALT_SDMMC_CDETECT_s
6143 {
6144  const uint32_t card_detect_n : 1; /* Card Detect */
6145  uint32_t : 31; /* *UNDEFINED* */
6146 };
6147 
6148 /* The typedef declaration for register ALT_SDMMC_CDETECT. */
6149 typedef volatile struct ALT_SDMMC_CDETECT_s ALT_SDMMC_CDETECT_t;
6150 #endif /* __ASSEMBLY__ */
6151 
6152 /* The byte offset of the ALT_SDMMC_CDETECT register from the beginning of the component. */
6153 #define ALT_SDMMC_CDETECT_OFST 0x50
6154 
6155 /*
6156  * Register : Write Protect Register - wrtprt
6157  *
6158  * See Field Description.
6159  *
6160  * Register Layout
6161  *
6162  * Bits | Access | Reset | Description
6163  * :-------|:-------|:------|:--------------
6164  * [0] | R | 0x1 | Write Protect
6165  * [31:1] | ??? | 0x0 | *UNDEFINED*
6166  *
6167  */
6168 /*
6169  * Field : Write Protect - write_protect
6170  *
6171  * Value on sdmmc_wp_i input port.
6172  *
6173  * Field Enumeration Values:
6174  *
6175  * Enum | Value | Description
6176  * :-----------------------------------|:------|:-----------------------
6177  * ALT_SDMMC_WRTPRT_WR_PROTECT_E_END | 0x1 | Write Protect Enabled
6178  * ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD | 0x0 | Write Protect Disabled
6179  *
6180  * Field Access Macros:
6181  *
6182  */
6183 /*
6184  * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT
6185  *
6186  * Write Protect Enabled
6187  */
6188 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6189 /*
6190  * Enumerated value for register field ALT_SDMMC_WRTPRT_WR_PROTECT
6191  *
6192  * Write Protect Disabled
6193  */
6194 #define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6195 
6196 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6197 #define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6198 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6199 #define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6200 /* The width in bits of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6201 #define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6202 /* The mask used to set the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */
6203 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6204 /* The mask used to clear the ALT_SDMMC_WRTPRT_WR_PROTECT register field value. */
6205 #define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6206 /* The reset value of the ALT_SDMMC_WRTPRT_WR_PROTECT register field. */
6207 #define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6208 /* Extracts the ALT_SDMMC_WRTPRT_WR_PROTECT field value from a register. */
6209 #define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6210 /* Produces a ALT_SDMMC_WRTPRT_WR_PROTECT register field value suitable for setting the register. */
6211 #define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6212 
6213 #ifndef __ASSEMBLY__
6214 /*
6215  * WARNING: The C register and register group struct declarations are provided for
6216  * convenience and illustrative purposes. They should, however, be used with
6217  * caution as the C language standard provides no guarantees about the alignment or
6218  * atomicity of device memory accesses. The recommended practice for writing
6219  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6220  * alt_write_word() functions.
6221  *
6222  * The struct declaration for register ALT_SDMMC_WRTPRT.
6223  */
6224 struct ALT_SDMMC_WRTPRT_s
6225 {
6226  const uint32_t write_protect : 1; /* Write Protect */
6227  uint32_t : 31; /* *UNDEFINED* */
6228 };
6229 
6230 /* The typedef declaration for register ALT_SDMMC_WRTPRT. */
6231 typedef volatile struct ALT_SDMMC_WRTPRT_s ALT_SDMMC_WRTPRT_t;
6232 #endif /* __ASSEMBLY__ */
6233 
6234 /* The byte offset of the ALT_SDMMC_WRTPRT register from the beginning of the component. */
6235 #define ALT_SDMMC_WRTPRT_OFST 0x54
6236 
6237 /*
6238  * Register : Transferred CIU Card Byte Count Register - tcbcnt
6239  *
6240  * Register Layout
6241  *
6242  * Bits | Access | Reset | Description
6243  * :-------|:-------|:------|:----------------------
6244  * [31:0] | R | 0x0 | Trans Card Byte Count
6245  *
6246  */
6247 /*
6248  * Field : Trans Card Byte Count - trans_card_byte_count
6249  *
6250  * Number of bytes transferred by CIU unit to card.
6251  *
6252  * Field Access Macros:
6253  *
6254  */
6255 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
6256 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
6257 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
6258 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
6259 /* The width in bits of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
6260 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
6261 /* The mask used to set the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
6262 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
6263 /* The mask used to clear the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value. */
6264 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
6265 /* The reset value of the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field. */
6266 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
6267 /* Extracts the ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT field value from a register. */
6268 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6269 /* Produces a ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT register field value suitable for setting the register. */
6270 #define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6271 
6272 #ifndef __ASSEMBLY__
6273 /*
6274  * WARNING: The C register and register group struct declarations are provided for
6275  * convenience and illustrative purposes. They should, however, be used with
6276  * caution as the C language standard provides no guarantees about the alignment or
6277  * atomicity of device memory accesses. The recommended practice for writing
6278  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6279  * alt_write_word() functions.
6280  *
6281  * The struct declaration for register ALT_SDMMC_TCBCNT.
6282  */
6283 struct ALT_SDMMC_TCBCNT_s
6284 {
6285  const uint32_t trans_card_byte_count : 32; /* Trans Card Byte Count */
6286 };
6287 
6288 /* The typedef declaration for register ALT_SDMMC_TCBCNT. */
6289 typedef volatile struct ALT_SDMMC_TCBCNT_s ALT_SDMMC_TCBCNT_t;
6290 #endif /* __ASSEMBLY__ */
6291 
6292 /* The byte offset of the ALT_SDMMC_TCBCNT register from the beginning of the component. */
6293 #define ALT_SDMMC_TCBCNT_OFST 0x5c
6294 
6295 /*
6296  * Register : Transferred Host to BIU-FIFO Byte Count Register - tbbcnt
6297  *
6298  * Tracks number of bytes transferred between Host and FIFO.
6299  *
6300  * Register Layout
6301  *
6302  * Bits | Access | Reset | Description
6303  * :-------|:-------|:------|:----------------------
6304  * [31:0] | R | 0x0 | Trans FIFO Byte Count
6305  *
6306  */
6307 /*
6308  * Field : Trans FIFO Byte Count - trans_fifo_byte_count
6309  *
6310  * Number of bytes transferred between Host/DMA memory and BIU FIFO. In 32-bit AMBA
6311  * data-bus-width modes, register should be accessed in full to avoid read-
6312  * coherency problems. Both TCBCNT and TBBCNT share same coherency register.
6313  *
6314  * Field Access Macros:
6315  *
6316  */
6317 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
6318 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
6319 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
6320 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
6321 /* The width in bits of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
6322 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
6323 /* The mask used to set the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
6324 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
6325 /* The mask used to clear the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value. */
6326 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
6327 /* The reset value of the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field. */
6328 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
6329 /* Extracts the ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT field value from a register. */
6330 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6331 /* Produces a ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT register field value suitable for setting the register. */
6332 #define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6333 
6334 #ifndef __ASSEMBLY__
6335 /*
6336  * WARNING: The C register and register group struct declarations are provided for
6337  * convenience and illustrative purposes. They should, however, be used with
6338  * caution as the C language standard provides no guarantees about the alignment or
6339  * atomicity of device memory accesses. The recommended practice for writing
6340  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6341  * alt_write_word() functions.
6342  *
6343  * The struct declaration for register ALT_SDMMC_TBBCNT.
6344  */
6345 struct ALT_SDMMC_TBBCNT_s
6346 {
6347  const uint32_t trans_fifo_byte_count : 32; /* Trans FIFO Byte Count */
6348 };
6349 
6350 /* The typedef declaration for register ALT_SDMMC_TBBCNT. */
6351 typedef volatile struct ALT_SDMMC_TBBCNT_s ALT_SDMMC_TBBCNT_t;
6352 #endif /* __ASSEMBLY__ */
6353 
6354 /* The byte offset of the ALT_SDMMC_TBBCNT register from the beginning of the component. */
6355 #define ALT_SDMMC_TBBCNT_OFST 0x60
6356 
6357 /*
6358  * Register : Debounce Count Register - debnce
6359  *
6360  * Register Layout
6361  *
6362  * Bits | Access | Reset | Description
6363  * :--------|:-------|:---------|:---------------
6364  * [23:0] | RW | 0xffffff | Debounce Count
6365  * [31:24] | ??? | 0x0 | *UNDEFINED*
6366  *
6367  */
6368 /*
6369  * Field : Debounce Count - debounce_count
6370  *
6371  * Number of host clocks l4_mp_clk used by debounce filter logic; typical debounce
6372  * time is 5-25 ms.
6373  *
6374  * Field Access Macros:
6375  *
6376  */
6377 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
6378 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
6379 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
6380 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
6381 /* The width in bits of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
6382 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
6383 /* The mask used to set the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
6384 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
6385 /* The mask used to clear the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value. */
6386 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
6387 /* The reset value of the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field. */
6388 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
6389 /* Extracts the ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT field value from a register. */
6390 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
6391 /* Produces a ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT register field value suitable for setting the register. */
6392 #define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
6393 
6394 #ifndef __ASSEMBLY__
6395 /*
6396  * WARNING: The C register and register group struct declarations are provided for
6397  * convenience and illustrative purposes. They should, however, be used with
6398  * caution as the C language standard provides no guarantees about the alignment or
6399  * atomicity of device memory accesses. The recommended practice for writing
6400  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6401  * alt_write_word() functions.
6402  *
6403  * The struct declaration for register ALT_SDMMC_DEBNCE.
6404  */
6405 struct ALT_SDMMC_DEBNCE_s
6406 {
6407  uint32_t debounce_count : 24; /* Debounce Count */
6408  uint32_t : 8; /* *UNDEFINED* */
6409 };
6410 
6411 /* The typedef declaration for register ALT_SDMMC_DEBNCE. */
6412 typedef volatile struct ALT_SDMMC_DEBNCE_s ALT_SDMMC_DEBNCE_t;
6413 #endif /* __ASSEMBLY__ */
6414 
6415 /* The byte offset of the ALT_SDMMC_DEBNCE register from the beginning of the component. */
6416 #define ALT_SDMMC_DEBNCE_OFST 0x64
6417 
6418 /*
6419  * Register : User ID Register - usrid
6420  *
6421  * Register Layout
6422  *
6423  * Bits | Access | Reset | Description
6424  * :-------|:-------|:----------|:------------
6425  * [31:0] | RW | 0x7967797 | User ID
6426  *
6427  */
6428 /*
6429  * Field : User ID - usr_id
6430  *
6431  * User identification field; Value is 0x7967797.
6432  *
6433  * Field Access Macros:
6434  *
6435  */
6436 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
6437 #define ALT_SDMMC_USRID_USR_ID_LSB 0
6438 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_USRID_USR_ID register field. */
6439 #define ALT_SDMMC_USRID_USR_ID_MSB 31
6440 /* The width in bits of the ALT_SDMMC_USRID_USR_ID register field. */
6441 #define ALT_SDMMC_USRID_USR_ID_WIDTH 32
6442 /* The mask used to set the ALT_SDMMC_USRID_USR_ID register field value. */
6443 #define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
6444 /* The mask used to clear the ALT_SDMMC_USRID_USR_ID register field value. */
6445 #define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
6446 /* The reset value of the ALT_SDMMC_USRID_USR_ID register field. */
6447 #define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
6448 /* Extracts the ALT_SDMMC_USRID_USR_ID field value from a register. */
6449 #define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
6450 /* Produces a ALT_SDMMC_USRID_USR_ID register field value suitable for setting the register. */
6451 #define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
6452 
6453 #ifndef __ASSEMBLY__
6454 /*
6455  * WARNING: The C register and register group struct declarations are provided for
6456  * convenience and illustrative purposes. They should, however, be used with
6457  * caution as the C language standard provides no guarantees about the alignment or
6458  * atomicity of device memory accesses. The recommended practice for writing
6459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6460  * alt_write_word() functions.
6461  *
6462  * The struct declaration for register ALT_SDMMC_USRID.
6463  */
6464 struct ALT_SDMMC_USRID_s
6465 {
6466  uint32_t usr_id : 32; /* User ID */
6467 };
6468 
6469 /* The typedef declaration for register ALT_SDMMC_USRID. */
6470 typedef volatile struct ALT_SDMMC_USRID_s ALT_SDMMC_USRID_t;
6471 #endif /* __ASSEMBLY__ */
6472 
6473 /* The byte offset of the ALT_SDMMC_USRID register from the beginning of the component. */
6474 #define ALT_SDMMC_USRID_OFST 0x68
6475 
6476 /*
6477  * Register : Version ID Register - verid
6478  *
6479  * Register Layout
6480  *
6481  * Bits | Access | Reset | Description
6482  * :-------|:-------|:-----------|:------------
6483  * [31:0] | R | 0x5342240a | Version ID
6484  *
6485  */
6486 /*
6487  * Field : Version ID - ver_id
6488  *
6489  * Synopsys version id. Current value is 32'h5342240a
6490  *
6491  * Field Access Macros:
6492  *
6493  */
6494 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
6495 #define ALT_SDMMC_VERID_VER_ID_LSB 0
6496 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_VERID_VER_ID register field. */
6497 #define ALT_SDMMC_VERID_VER_ID_MSB 31
6498 /* The width in bits of the ALT_SDMMC_VERID_VER_ID register field. */
6499 #define ALT_SDMMC_VERID_VER_ID_WIDTH 32
6500 /* The mask used to set the ALT_SDMMC_VERID_VER_ID register field value. */
6501 #define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
6502 /* The mask used to clear the ALT_SDMMC_VERID_VER_ID register field value. */
6503 #define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
6504 /* The reset value of the ALT_SDMMC_VERID_VER_ID register field. */
6505 #define ALT_SDMMC_VERID_VER_ID_RESET 0x5342240a
6506 /* Extracts the ALT_SDMMC_VERID_VER_ID field value from a register. */
6507 #define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
6508 /* Produces a ALT_SDMMC_VERID_VER_ID register field value suitable for setting the register. */
6509 #define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
6510 
6511 #ifndef __ASSEMBLY__
6512 /*
6513  * WARNING: The C register and register group struct declarations are provided for
6514  * convenience and illustrative purposes. They should, however, be used with
6515  * caution as the C language standard provides no guarantees about the alignment or
6516  * atomicity of device memory accesses. The recommended practice for writing
6517  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6518  * alt_write_word() functions.
6519  *
6520  * The struct declaration for register ALT_SDMMC_VERID.
6521  */
6522 struct ALT_SDMMC_VERID_s
6523 {
6524  const uint32_t ver_id : 32; /* Version ID */
6525 };
6526 
6527 /* The typedef declaration for register ALT_SDMMC_VERID. */
6528 typedef volatile struct ALT_SDMMC_VERID_s ALT_SDMMC_VERID_t;
6529 #endif /* __ASSEMBLY__ */
6530 
6531 /* The byte offset of the ALT_SDMMC_VERID register from the beginning of the component. */
6532 #define ALT_SDMMC_VERID_OFST 0x6c
6533 
6534 /*
6535  * Register : Hardware Configuration Register - hcon
6536  *
6537  * Hardware configurations registers. Register can be used to develop
6538  * configuration-independent software drivers.
6539  *
6540  * Register Layout
6541  *
6542  * Bits | Access | Reset | Description
6543  * :--------|:-------|:------|:-------------------------
6544  * [0] | R | 0x1 | Card Type
6545  * [5:1] | R | 0x0 | Number of Cards
6546  * [6] | R | 0x0 | Slave Bus Type
6547  * [9:7] | R | 0x1 | Slave Bus Data Width
6548  * [15:10] | R | 0xc | Slave Bus Address Width
6549  * [17:16] | R | 0x0 | DMA Interface Type
6550  * [20:18] | R | 0x1 | Generic DMA Data Width
6551  * [21] | R | 0x0 | FIFO RAM Location
6552  * [22] | R | 0x1 | Implement Hold Register
6553  * [23] | R | 0x1 | Clock False Path
6554  * [25:24] | R | 0x0 | Number of Clock Dividers
6555  * [26] | R | 0x0 | Area Optimized
6556  * [31:27] | ??? | 0x0 | *UNDEFINED*
6557  *
6558  */
6559 /*
6560  * Field : Card Type - ct
6561  *
6562  * Supported card types
6563  *
6564  * Field Enumeration Values:
6565  *
6566  * Enum | Value | Description
6567  * :--------------------------|:------|:-----------------
6568  * ALT_SDMMC_HCON_CT_E_SDMMC | 0x1 | Card Type SD/MMC
6569  *
6570  * Field Access Macros:
6571  *
6572  */
6573 /*
6574  * Enumerated value for register field ALT_SDMMC_HCON_CT
6575  *
6576  * Card Type SD/MMC
6577  */
6578 #define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
6579 
6580 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_CT register field. */
6581 #define ALT_SDMMC_HCON_CT_LSB 0
6582 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_CT register field. */
6583 #define ALT_SDMMC_HCON_CT_MSB 0
6584 /* The width in bits of the ALT_SDMMC_HCON_CT register field. */
6585 #define ALT_SDMMC_HCON_CT_WIDTH 1
6586 /* The mask used to set the ALT_SDMMC_HCON_CT register field value. */
6587 #define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
6588 /* The mask used to clear the ALT_SDMMC_HCON_CT register field value. */
6589 #define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
6590 /* The reset value of the ALT_SDMMC_HCON_CT register field. */
6591 #define ALT_SDMMC_HCON_CT_RESET 0x1
6592 /* Extracts the ALT_SDMMC_HCON_CT field value from a register. */
6593 #define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
6594 /* Produces a ALT_SDMMC_HCON_CT register field value suitable for setting the register. */
6595 #define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
6596 
6597 /*
6598  * Field : Number of Cards - nc
6599  *
6600  * Maximum number of cards less one
6601  *
6602  * Field Enumeration Values:
6603  *
6604  * Enum | Value | Description
6605  * :----------------------------|:------|:------------
6606  * ALT_SDMMC_HCON_NC_E_NUMCARD | 0x0 | 1 Card
6607  *
6608  * Field Access Macros:
6609  *
6610  */
6611 /*
6612  * Enumerated value for register field ALT_SDMMC_HCON_NC
6613  *
6614  * 1 Card
6615  */
6616 #define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
6617 
6618 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NC register field. */
6619 #define ALT_SDMMC_HCON_NC_LSB 1
6620 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NC register field. */
6621 #define ALT_SDMMC_HCON_NC_MSB 5
6622 /* The width in bits of the ALT_SDMMC_HCON_NC register field. */
6623 #define ALT_SDMMC_HCON_NC_WIDTH 5
6624 /* The mask used to set the ALT_SDMMC_HCON_NC register field value. */
6625 #define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
6626 /* The mask used to clear the ALT_SDMMC_HCON_NC register field value. */
6627 #define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
6628 /* The reset value of the ALT_SDMMC_HCON_NC register field. */
6629 #define ALT_SDMMC_HCON_NC_RESET 0x0
6630 /* Extracts the ALT_SDMMC_HCON_NC field value from a register. */
6631 #define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
6632 /* Produces a ALT_SDMMC_HCON_NC register field value suitable for setting the register. */
6633 #define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
6634 
6635 /*
6636  * Field : Slave Bus Type - hbus
6637  *
6638  * Slave bus type.
6639  *
6640  * Field Enumeration Values:
6641  *
6642  * Enum | Value | Description
6643  * :--------------------------|:------|:------------
6644  * ALT_SDMMC_HCON_HBUS_E_APB | 0x0 | APB Bus
6645  *
6646  * Field Access Macros:
6647  *
6648  */
6649 /*
6650  * Enumerated value for register field ALT_SDMMC_HCON_HBUS
6651  *
6652  * APB Bus
6653  */
6654 #define ALT_SDMMC_HCON_HBUS_E_APB 0x0
6655 
6656 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HBUS register field. */
6657 #define ALT_SDMMC_HCON_HBUS_LSB 6
6658 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HBUS register field. */
6659 #define ALT_SDMMC_HCON_HBUS_MSB 6
6660 /* The width in bits of the ALT_SDMMC_HCON_HBUS register field. */
6661 #define ALT_SDMMC_HCON_HBUS_WIDTH 1
6662 /* The mask used to set the ALT_SDMMC_HCON_HBUS register field value. */
6663 #define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
6664 /* The mask used to clear the ALT_SDMMC_HCON_HBUS register field value. */
6665 #define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
6666 /* The reset value of the ALT_SDMMC_HCON_HBUS register field. */
6667 #define ALT_SDMMC_HCON_HBUS_RESET 0x0
6668 /* Extracts the ALT_SDMMC_HCON_HBUS field value from a register. */
6669 #define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
6670 /* Produces a ALT_SDMMC_HCON_HBUS register field value suitable for setting the register. */
6671 #define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
6672 
6673 /*
6674  * Field : Slave Bus Data Width - hdatawidth
6675  *
6676  * Slave bus data width
6677  *
6678  * Field Enumeration Values:
6679  *
6680  * Enum | Value | Description
6681  * :----------------------------------------|:------|:--------------
6682  * ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS | 0x1 | Width 32 Bits
6683  *
6684  * Field Access Macros:
6685  *
6686  */
6687 /*
6688  * Enumerated value for register field ALT_SDMMC_HCON_HDATAWIDTH
6689  *
6690  * Width 32 Bits
6691  */
6692 #define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
6693 
6694 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
6695 #define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
6696 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
6697 #define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
6698 /* The width in bits of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
6699 #define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
6700 /* The mask used to set the ALT_SDMMC_HCON_HDATAWIDTH register field value. */
6701 #define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
6702 /* The mask used to clear the ALT_SDMMC_HCON_HDATAWIDTH register field value. */
6703 #define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
6704 /* The reset value of the ALT_SDMMC_HCON_HDATAWIDTH register field. */
6705 #define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
6706 /* Extracts the ALT_SDMMC_HCON_HDATAWIDTH field value from a register. */
6707 #define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
6708 /* Produces a ALT_SDMMC_HCON_HDATAWIDTH register field value suitable for setting the register. */
6709 #define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
6710 
6711 /*
6712  * Field : Slave Bus Address Width - haddrwidth
6713  *
6714  * Slave bus address width less one
6715  *
6716  * Field Enumeration Values:
6717  *
6718  * Enum | Value | Description
6719  * :----------------------------------------|:------|:--------------
6720  * ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS | 0xc | Width 13 Bits
6721  *
6722  * Field Access Macros:
6723  *
6724  */
6725 /*
6726  * Enumerated value for register field ALT_SDMMC_HCON_HADDRWIDTH
6727  *
6728  * Width 13 Bits
6729  */
6730 #define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
6731 
6732 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
6733 #define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
6734 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
6735 #define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
6736 /* The width in bits of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
6737 #define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
6738 /* The mask used to set the ALT_SDMMC_HCON_HADDRWIDTH register field value. */
6739 #define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
6740 /* The mask used to clear the ALT_SDMMC_HCON_HADDRWIDTH register field value. */
6741 #define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
6742 /* The reset value of the ALT_SDMMC_HCON_HADDRWIDTH register field. */
6743 #define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
6744 /* Extracts the ALT_SDMMC_HCON_HADDRWIDTH field value from a register. */
6745 #define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
6746 /* Produces a ALT_SDMMC_HCON_HADDRWIDTH register field value suitable for setting the register. */
6747 #define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
6748 
6749 /*
6750  * Field : DMA Interface Type - dmaintf
6751  *
6752  * DMA interface type
6753  *
6754  * Field Enumeration Values:
6755  *
6756  * Enum | Value | Description
6757  * :------------------------------|:------|:-------------------------------------------------
6758  * ALT_SDMMC_HCON_DMAINTF_E_NONE | 0x0 | No External DMA Controller Interface (SD/MMC has
6759  * : | | its own internal DMA Controller
6760  *
6761  * Field Access Macros:
6762  *
6763  */
6764 /*
6765  * Enumerated value for register field ALT_SDMMC_HCON_DMAINTF
6766  *
6767  * No External DMA Controller Interface (SD/MMC has its own internal DMA Controller
6768  */
6769 #define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
6770 
6771 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */
6772 #define ALT_SDMMC_HCON_DMAINTF_LSB 16
6773 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMAINTF register field. */
6774 #define ALT_SDMMC_HCON_DMAINTF_MSB 17
6775 /* The width in bits of the ALT_SDMMC_HCON_DMAINTF register field. */
6776 #define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
6777 /* The mask used to set the ALT_SDMMC_HCON_DMAINTF register field value. */
6778 #define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
6779 /* The mask used to clear the ALT_SDMMC_HCON_DMAINTF register field value. */
6780 #define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
6781 /* The reset value of the ALT_SDMMC_HCON_DMAINTF register field. */
6782 #define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
6783 /* Extracts the ALT_SDMMC_HCON_DMAINTF field value from a register. */
6784 #define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
6785 /* Produces a ALT_SDMMC_HCON_DMAINTF register field value suitable for setting the register. */
6786 #define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
6787 
6788 /*
6789  * Field : Generic DMA Data Width - dmadatawidth
6790  *
6791  * Encodes bit width of external DMA controller interface. Doesn't apply to the
6792  * SD/MMC because it has no external DMA controller interface.
6793  *
6794  * Field Enumeration Values:
6795  *
6796  * Enum | Value | Description
6797  * :------------------------------------------|:------|:-------------
6798  * ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS | 0x1 | 32-bits wide
6799  *
6800  * Field Access Macros:
6801  *
6802  */
6803 /*
6804  * Enumerated value for register field ALT_SDMMC_HCON_DMADATAWIDTH
6805  *
6806  * 32-bits wide
6807  */
6808 #define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
6809 
6810 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
6811 #define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
6812 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
6813 #define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
6814 /* The width in bits of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
6815 #define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
6816 /* The mask used to set the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */
6817 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
6818 /* The mask used to clear the ALT_SDMMC_HCON_DMADATAWIDTH register field value. */
6819 #define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
6820 /* The reset value of the ALT_SDMMC_HCON_DMADATAWIDTH register field. */
6821 #define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
6822 /* Extracts the ALT_SDMMC_HCON_DMADATAWIDTH field value from a register. */
6823 #define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
6824 /* Produces a ALT_SDMMC_HCON_DMADATAWIDTH register field value suitable for setting the register. */
6825 #define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
6826 
6827 /*
6828  * Field : FIFO RAM Location - rios
6829  *
6830  * FIFO RAM location
6831  *
6832  * Field Enumeration Values:
6833  *
6834  * Enum | Value | Description
6835  * :------------------------------|:------|:-------------------------
6836  * ALT_SDMMC_HCON_RIOS_E_OUTSIDE | 0x0 | FIFO RAM Outside IP Core
6837  *
6838  * Field Access Macros:
6839  *
6840  */
6841 /*
6842  * Enumerated value for register field ALT_SDMMC_HCON_RIOS
6843  *
6844  * FIFO RAM Outside IP Core
6845  */
6846 #define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
6847 
6848 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_RIOS register field. */
6849 #define ALT_SDMMC_HCON_RIOS_LSB 21
6850 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_RIOS register field. */
6851 #define ALT_SDMMC_HCON_RIOS_MSB 21
6852 /* The width in bits of the ALT_SDMMC_HCON_RIOS register field. */
6853 #define ALT_SDMMC_HCON_RIOS_WIDTH 1
6854 /* The mask used to set the ALT_SDMMC_HCON_RIOS register field value. */
6855 #define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
6856 /* The mask used to clear the ALT_SDMMC_HCON_RIOS register field value. */
6857 #define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
6858 /* The reset value of the ALT_SDMMC_HCON_RIOS register field. */
6859 #define ALT_SDMMC_HCON_RIOS_RESET 0x0
6860 /* Extracts the ALT_SDMMC_HCON_RIOS field value from a register. */
6861 #define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
6862 /* Produces a ALT_SDMMC_HCON_RIOS register field value suitable for setting the register. */
6863 #define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
6864 
6865 /*
6866  * Field : Implement Hold Register - ihr
6867  *
6868  * Implement hold register
6869  *
6870  * Field Enumeration Values:
6871  *
6872  * Enum | Value | Description
6873  * :---------------------------------|:------|:-------------------------
6874  * ALT_SDMMC_HCON_IHR_E_IMPLEMENTED | 0x1 | Implements Hold Register
6875  *
6876  * Field Access Macros:
6877  *
6878  */
6879 /*
6880  * Enumerated value for register field ALT_SDMMC_HCON_IHR
6881  *
6882  * Implements Hold Register
6883  */
6884 #define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
6885 
6886 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_IHR register field. */
6887 #define ALT_SDMMC_HCON_IHR_LSB 22
6888 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_IHR register field. */
6889 #define ALT_SDMMC_HCON_IHR_MSB 22
6890 /* The width in bits of the ALT_SDMMC_HCON_IHR register field. */
6891 #define ALT_SDMMC_HCON_IHR_WIDTH 1
6892 /* The mask used to set the ALT_SDMMC_HCON_IHR register field value. */
6893 #define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
6894 /* The mask used to clear the ALT_SDMMC_HCON_IHR register field value. */
6895 #define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
6896 /* The reset value of the ALT_SDMMC_HCON_IHR register field. */
6897 #define ALT_SDMMC_HCON_IHR_RESET 0x1
6898 /* Extracts the ALT_SDMMC_HCON_IHR field value from a register. */
6899 #define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
6900 /* Produces a ALT_SDMMC_HCON_IHR register field value suitable for setting the register. */
6901 #define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
6902 
6903 /*
6904  * Field : Clock False Path - scfp
6905  *
6906  * Clock False Path
6907  *
6908  * Field Enumeration Values:
6909  *
6910  * Enum | Value | Description
6911  * :--------------------------|:------|:---------------------
6912  * ALT_SDMMC_HCON_SCFP_E_SET | 0x1 | Clock False Path Set
6913  *
6914  * Field Access Macros:
6915  *
6916  */
6917 /*
6918  * Enumerated value for register field ALT_SDMMC_HCON_SCFP
6919  *
6920  * Clock False Path Set
6921  */
6922 #define ALT_SDMMC_HCON_SCFP_E_SET 0x1
6923 
6924 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_SCFP register field. */
6925 #define ALT_SDMMC_HCON_SCFP_LSB 23
6926 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_SCFP register field. */
6927 #define ALT_SDMMC_HCON_SCFP_MSB 23
6928 /* The width in bits of the ALT_SDMMC_HCON_SCFP register field. */
6929 #define ALT_SDMMC_HCON_SCFP_WIDTH 1
6930 /* The mask used to set the ALT_SDMMC_HCON_SCFP register field value. */
6931 #define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
6932 /* The mask used to clear the ALT_SDMMC_HCON_SCFP register field value. */
6933 #define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
6934 /* The reset value of the ALT_SDMMC_HCON_SCFP register field. */
6935 #define ALT_SDMMC_HCON_SCFP_RESET 0x1
6936 /* Extracts the ALT_SDMMC_HCON_SCFP field value from a register. */
6937 #define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
6938 /* Produces a ALT_SDMMC_HCON_SCFP register field value suitable for setting the register. */
6939 #define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
6940 
6941 /*
6942  * Field : Number of Clock Dividers - ncd
6943  *
6944  * Number of clock dividers less one
6945  *
6946  * Field Enumeration Values:
6947  *
6948  * Enum | Value | Description
6949  * :----------------------------|:------|:------------------
6950  * ALT_SDMMC_HCON_NCD_E_ONEDIV | 0x0 | One Clock Divider
6951  *
6952  * Field Access Macros:
6953  *
6954  */
6955 /*
6956  * Enumerated value for register field ALT_SDMMC_HCON_NCD
6957  *
6958  * One Clock Divider
6959  */
6960 #define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
6961 
6962 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NCD register field. */
6963 #define ALT_SDMMC_HCON_NCD_LSB 24
6964 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NCD register field. */
6965 #define ALT_SDMMC_HCON_NCD_MSB 25
6966 /* The width in bits of the ALT_SDMMC_HCON_NCD register field. */
6967 #define ALT_SDMMC_HCON_NCD_WIDTH 2
6968 /* The mask used to set the ALT_SDMMC_HCON_NCD register field value. */
6969 #define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
6970 /* The mask used to clear the ALT_SDMMC_HCON_NCD register field value. */
6971 #define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
6972 /* The reset value of the ALT_SDMMC_HCON_NCD register field. */
6973 #define ALT_SDMMC_HCON_NCD_RESET 0x0
6974 /* Extracts the ALT_SDMMC_HCON_NCD field value from a register. */
6975 #define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
6976 /* Produces a ALT_SDMMC_HCON_NCD register field value suitable for setting the register. */
6977 #define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
6978 
6979 /*
6980  * Field : Area Optimized - aro
6981  *
6982  * Area optimized
6983  *
6984  * Field Enumeration Values:
6985  *
6986  * Enum | Value | Description
6987  * :-----------------------------------|:------|:-----------------------
6988  * ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA | 0x0 | Not Optimized For Area
6989  *
6990  * Field Access Macros:
6991  *
6992  */
6993 /*
6994  * Enumerated value for register field ALT_SDMMC_HCON_ARO
6995  *
6996  * Not Optimized For Area
6997  */
6998 #define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
6999 
7000 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_ARO register field. */
7001 #define ALT_SDMMC_HCON_ARO_LSB 26
7002 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_ARO register field. */
7003 #define ALT_SDMMC_HCON_ARO_MSB 26
7004 /* The width in bits of the ALT_SDMMC_HCON_ARO register field. */
7005 #define ALT_SDMMC_HCON_ARO_WIDTH 1
7006 /* The mask used to set the ALT_SDMMC_HCON_ARO register field value. */
7007 #define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7008 /* The mask used to clear the ALT_SDMMC_HCON_ARO register field value. */
7009 #define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7010 /* The reset value of the ALT_SDMMC_HCON_ARO register field. */
7011 #define ALT_SDMMC_HCON_ARO_RESET 0x0
7012 /* Extracts the ALT_SDMMC_HCON_ARO field value from a register. */
7013 #define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7014 /* Produces a ALT_SDMMC_HCON_ARO register field value suitable for setting the register. */
7015 #define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7016 
7017 #ifndef __ASSEMBLY__
7018 /*
7019  * WARNING: The C register and register group struct declarations are provided for
7020  * convenience and illustrative purposes. They should, however, be used with
7021  * caution as the C language standard provides no guarantees about the alignment or
7022  * atomicity of device memory accesses. The recommended practice for writing
7023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7024  * alt_write_word() functions.
7025  *
7026  * The struct declaration for register ALT_SDMMC_HCON.
7027  */
7028 struct ALT_SDMMC_HCON_s
7029 {
7030  const uint32_t ct : 1; /* Card Type */
7031  const uint32_t nc : 5; /* Number of Cards */
7032  const uint32_t hbus : 1; /* Slave Bus Type */
7033  const uint32_t hdatawidth : 3; /* Slave Bus Data Width */
7034  const uint32_t haddrwidth : 6; /* Slave Bus Address Width */
7035  const uint32_t dmaintf : 2; /* DMA Interface Type */
7036  const uint32_t dmadatawidth : 3; /* Generic DMA Data Width */
7037  const uint32_t rios : 1; /* FIFO RAM Location */
7038  const uint32_t ihr : 1; /* Implement Hold Register */
7039  const uint32_t scfp : 1; /* Clock False Path */
7040  const uint32_t ncd : 2; /* Number of Clock Dividers */
7041  const uint32_t aro : 1; /* Area Optimized */
7042  uint32_t : 5; /* *UNDEFINED* */
7043 };
7044 
7045 /* The typedef declaration for register ALT_SDMMC_HCON. */
7046 typedef volatile struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t;
7047 #endif /* __ASSEMBLY__ */
7048 
7049 /* The byte offset of the ALT_SDMMC_HCON register from the beginning of the component. */
7050 #define ALT_SDMMC_HCON_OFST 0x70
7051 
7052 /*
7053  * Register : UHS-1 Register - uhs_reg
7054  *
7055  * UHS-1 Register
7056  *
7057  * Register Layout
7058  *
7059  * Bits | Access | Reset | Description
7060  * :--------|:-------|:------|:------------------
7061  * [0] | RW | 0x0 | High Voltage Mode
7062  * [15:1] | ??? | 0x0 | *UNDEFINED*
7063  * [16] | RW | 0x0 | DDR Mode
7064  * [31:17] | ??? | 0x0 | *UNDEFINED*
7065  *
7066  */
7067 /*
7068  * Field : High Voltage Mode - volt_reg
7069  *
7070  * Determines the voltage fed to the buffers by an external voltage regulator.
7071  * These bits function as the output of the host controller and are fed to an
7072  * external voltage regulator. The voltage regulator must switch the voltage of the
7073  * buffers of a particular card to either 3.3V or 1.8V, depending on the value
7074  * programmed in the register.
7075  *
7076  * Field Enumeration Values:
7077  *
7078  * Enum | Value | Description
7079  * :------------------------------------|:------|:-------------------------------
7080  * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V | 0x0 | Buffers supplied with 3.3V Vdd
7081  * ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V | 0x1 | Buffers supplied with 1.8V Vdd
7082  *
7083  * Field Access Macros:
7084  *
7085  */
7086 /*
7087  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG
7088  *
7089  * Buffers supplied with 3.3V Vdd
7090  */
7091 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7092 /*
7093  * Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG
7094  *
7095  * Buffers supplied with 1.8V Vdd
7096  */
7097 #define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7098 
7099 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7100 #define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7101 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7102 #define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 0
7103 /* The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7104 #define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 1
7105 /* The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */
7106 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x00000001
7107 /* The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG register field value. */
7108 #define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xfffffffe
7109 /* The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG register field. */
7110 #define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7111 /* Extracts the ALT_SDMMC_UHS_REG_VOLT_REG field value from a register. */
7112 #define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x00000001) >> 0)
7113 /* Produces a ALT_SDMMC_UHS_REG_VOLT_REG register field value suitable for setting the register. */
7114 #define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x00000001)
7115 
7116 /*
7117  * Field : DDR Mode - ddr_reg
7118  *
7119  * Determines the voltage fed to the buffers by an external voltage regulator.
7120  *
7121  * Field Enumeration Values:
7122  *
7123  * Enum | Value | Description
7124  * :-----------------------------------|:------|:-------------
7125  * ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR | 0x0 | Non-DDR mode
7126  * ALT_SDMMC_UHS_REG_DDR_REG_E_DDR | 0x1 | DDR mode
7127  *
7128  * Field Access Macros:
7129  *
7130  */
7131 /*
7132  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG
7133  *
7134  * Non-DDR mode
7135  */
7136 #define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7137 /*
7138  * Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG
7139  *
7140  * DDR mode
7141  */
7142 #define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7143 
7144 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7145 #define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7146 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7147 #define ALT_SDMMC_UHS_REG_DDR_REG_MSB 16
7148 /* The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7149 #define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 1
7150 /* The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG register field value. */
7151 #define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0x00010000
7152 /* The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG register field value. */
7153 #define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0xfffeffff
7154 /* The reset value of the ALT_SDMMC_UHS_REG_DDR_REG register field. */
7155 #define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7156 /* Extracts the ALT_SDMMC_UHS_REG_DDR_REG field value from a register. */
7157 #define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0x00010000) >> 16)
7158 /* Produces a ALT_SDMMC_UHS_REG_DDR_REG register field value suitable for setting the register. */
7159 #define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0x00010000)
7160 
7161 #ifndef __ASSEMBLY__
7162 /*
7163  * WARNING: The C register and register group struct declarations are provided for
7164  * convenience and illustrative purposes. They should, however, be used with
7165  * caution as the C language standard provides no guarantees about the alignment or
7166  * atomicity of device memory accesses. The recommended practice for writing
7167  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7168  * alt_write_word() functions.
7169  *
7170  * The struct declaration for register ALT_SDMMC_UHS_REG.
7171  */
7172 struct ALT_SDMMC_UHS_REG_s
7173 {
7174  uint32_t volt_reg : 1; /* High Voltage Mode */
7175  uint32_t : 15; /* *UNDEFINED* */
7176  uint32_t ddr_reg : 1; /* DDR Mode */
7177  uint32_t : 15; /* *UNDEFINED* */
7178 };
7179 
7180 /* The typedef declaration for register ALT_SDMMC_UHS_REG. */
7181 typedef volatile struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t;
7182 #endif /* __ASSEMBLY__ */
7183 
7184 /* The byte offset of the ALT_SDMMC_UHS_REG register from the beginning of the component. */
7185 #define ALT_SDMMC_UHS_REG_OFST 0x74
7186 
7187 /*
7188  * Register : Hardware Reset Register - rst_n
7189  *
7190  * Register Layout
7191  *
7192  * Bits | Access | Reset | Description
7193  * :-------|:-------|:------|:------------
7194  * [0] | RW | 0x1 | Card Reset
7195  * [31:1] | ??? | 0x0 | *UNDEFINED*
7196  *
7197  */
7198 /*
7199  * Field : Card Reset - card_reset
7200  *
7201  * This bit causes the cards to enter pre-idle state, which requires it to be re-
7202  * initialized.
7203  *
7204  * Field Enumeration Values:
7205  *
7206  * Enum | Value | Description
7207  * :------------------------------------|:------|:----------------
7208  * ALT_SDMMC_RST_N_CARD_RST_E_ASSERT | 0x1 | Active Mode
7209  * ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT | 0x0 | Not Active Mode
7210  *
7211  * Field Access Macros:
7212  *
7213  */
7214 /*
7215  * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST
7216  *
7217  * Active Mode
7218  */
7219 #define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
7220 /*
7221  * Enumerated value for register field ALT_SDMMC_RST_N_CARD_RST
7222  *
7223  * Not Active Mode
7224  */
7225 #define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
7226 
7227 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */
7228 #define ALT_SDMMC_RST_N_CARD_RST_LSB 0
7229 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_RST_N_CARD_RST register field. */
7230 #define ALT_SDMMC_RST_N_CARD_RST_MSB 0
7231 /* The width in bits of the ALT_SDMMC_RST_N_CARD_RST register field. */
7232 #define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
7233 /* The mask used to set the ALT_SDMMC_RST_N_CARD_RST register field value. */
7234 #define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
7235 /* The mask used to clear the ALT_SDMMC_RST_N_CARD_RST register field value. */
7236 #define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
7237 /* The reset value of the ALT_SDMMC_RST_N_CARD_RST register field. */
7238 #define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
7239 /* Extracts the ALT_SDMMC_RST_N_CARD_RST field value from a register. */
7240 #define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
7241 /* Produces a ALT_SDMMC_RST_N_CARD_RST register field value suitable for setting the register. */
7242 #define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
7243 
7244 #ifndef __ASSEMBLY__
7245 /*
7246  * WARNING: The C register and register group struct declarations are provided for
7247  * convenience and illustrative purposes. They should, however, be used with
7248  * caution as the C language standard provides no guarantees about the alignment or
7249  * atomicity of device memory accesses. The recommended practice for writing
7250  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7251  * alt_write_word() functions.
7252  *
7253  * The struct declaration for register ALT_SDMMC_RST_N.
7254  */
7255 struct ALT_SDMMC_RST_N_s
7256 {
7257  uint32_t card_reset : 1; /* Card Reset */
7258  uint32_t : 31; /* *UNDEFINED* */
7259 };
7260 
7261 /* The typedef declaration for register ALT_SDMMC_RST_N. */
7262 typedef volatile struct ALT_SDMMC_RST_N_s ALT_SDMMC_RST_N_t;
7263 #endif /* __ASSEMBLY__ */
7264 
7265 /* The byte offset of the ALT_SDMMC_RST_N register from the beginning of the component. */
7266 #define ALT_SDMMC_RST_N_OFST 0x78
7267 
7268 /*
7269  * Register : Bus Mode Register - bmod
7270  *
7271  * Details different bus operating modes.
7272  *
7273  * Register Layout
7274  *
7275  * Bits | Access | Reset | Description
7276  * :--------|:-------|:------|:--------------------------
7277  * [0] | RW | 0x0 | Software Reset
7278  * [1] | RW | 0x0 | Fixed Burst
7279  * [6:2] | RW | 0x0 | Descriptor Skip Length
7280  * [7] | RW | 0x0 | IDMAC Enable
7281  * [10:8] | R | 0x0 | Programmable Burst Length
7282  * [31:11] | ??? | 0x0 | *UNDEFINED*
7283  *
7284  */
7285 /*
7286  * Field : Software Reset - swr
7287  *
7288  * This bit resets all internal registers of the DMA Controller. It is
7289  * automatically cleared after 1 clock cycle.
7290  *
7291  * Field Enumeration Values:
7292  *
7293  * Enum | Value | Description
7294  * :------------------------------|:------|:------------------------------
7295  * ALT_SDMMC_BMOD_SWR_E_SFTRST | 0x1 | Resets DMA Internal Registers
7296  * ALT_SDMMC_BMOD_SWR_E_NOSFTRST | 0x0 | No reset - default
7297  *
7298  * Field Access Macros:
7299  *
7300  */
7301 /*
7302  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
7303  *
7304  * Resets DMA Internal Registers
7305  */
7306 #define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
7307 /*
7308  * Enumerated value for register field ALT_SDMMC_BMOD_SWR
7309  *
7310  * No reset - default
7311  */
7312 #define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
7313 
7314 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_SWR register field. */
7315 #define ALT_SDMMC_BMOD_SWR_LSB 0
7316 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_SWR register field. */
7317 #define ALT_SDMMC_BMOD_SWR_MSB 0
7318 /* The width in bits of the ALT_SDMMC_BMOD_SWR register field. */
7319 #define ALT_SDMMC_BMOD_SWR_WIDTH 1
7320 /* The mask used to set the ALT_SDMMC_BMOD_SWR register field value. */
7321 #define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
7322 /* The mask used to clear the ALT_SDMMC_BMOD_SWR register field value. */
7323 #define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
7324 /* The reset value of the ALT_SDMMC_BMOD_SWR register field. */
7325 #define ALT_SDMMC_BMOD_SWR_RESET 0x0
7326 /* Extracts the ALT_SDMMC_BMOD_SWR field value from a register. */
7327 #define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
7328 /* Produces a ALT_SDMMC_BMOD_SWR register field value suitable for setting the register. */
7329 #define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
7330 
7331 /*
7332  * Field : Fixed Burst - fb
7333  *
7334  * Controls whether the AHB Master interface performs fixed burst transfers or not.
7335  * Will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst
7336  * transfers.
7337  *
7338  * Field Enumeration Values:
7339  *
7340  * Enum | Value | Description
7341  * :--------------------------------|:------|:--------------------------
7342  * ALT_SDMMC_BMOD_FB_E_FIXEDBRST | 0x1 | AHB Master Fixed Burst
7343  * ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST | 0x0 | Non Fixed Burst - default
7344  *
7345  * Field Access Macros:
7346  *
7347  */
7348 /*
7349  * Enumerated value for register field ALT_SDMMC_BMOD_FB
7350  *
7351  * AHB Master Fixed Burst
7352  */
7353 #define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
7354 /*
7355  * Enumerated value for register field ALT_SDMMC_BMOD_FB
7356  *
7357  * Non Fixed Burst - default
7358  */
7359 #define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
7360 
7361 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_FB register field. */
7362 #define ALT_SDMMC_BMOD_FB_LSB 1
7363 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_FB register field. */
7364 #define ALT_SDMMC_BMOD_FB_MSB 1
7365 /* The width in bits of the ALT_SDMMC_BMOD_FB register field. */
7366 #define ALT_SDMMC_BMOD_FB_WIDTH 1
7367 /* The mask used to set the ALT_SDMMC_BMOD_FB register field value. */
7368 #define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
7369 /* The mask used to clear the ALT_SDMMC_BMOD_FB register field value. */
7370 #define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
7371 /* The reset value of the ALT_SDMMC_BMOD_FB register field. */
7372 #define ALT_SDMMC_BMOD_FB_RESET 0x0
7373 /* Extracts the ALT_SDMMC_BMOD_FB field value from a register. */
7374 #define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
7375 /* Produces a ALT_SDMMC_BMOD_FB register field value suitable for setting the register. */
7376 #define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
7377 
7378 /*
7379  * Field : Descriptor Skip Length - dsl
7380  *
7381  * Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip
7382  * between two unchained descriptors.
7383  *
7384  * Field Access Macros:
7385  *
7386  */
7387 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DSL register field. */
7388 #define ALT_SDMMC_BMOD_DSL_LSB 2
7389 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DSL register field. */
7390 #define ALT_SDMMC_BMOD_DSL_MSB 6
7391 /* The width in bits of the ALT_SDMMC_BMOD_DSL register field. */
7392 #define ALT_SDMMC_BMOD_DSL_WIDTH 5
7393 /* The mask used to set the ALT_SDMMC_BMOD_DSL register field value. */
7394 #define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
7395 /* The mask used to clear the ALT_SDMMC_BMOD_DSL register field value. */
7396 #define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
7397 /* The reset value of the ALT_SDMMC_BMOD_DSL register field. */
7398 #define ALT_SDMMC_BMOD_DSL_RESET 0x0
7399 /* Extracts the ALT_SDMMC_BMOD_DSL field value from a register. */
7400 #define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
7401 /* Produces a ALT_SDMMC_BMOD_DSL register field value suitable for setting the register. */
7402 #define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
7403 
7404 /*
7405  * Field : IDMAC Enable - de
7406  *
7407  * Enables and Disables Internal DMA.
7408  *
7409  * Field Enumeration Values:
7410  *
7411  * Enum | Value | Description
7412  * :-------------------------|:------|:--------------
7413  * ALT_SDMMC_BMOD_DE_E_END | 0x1 | IDMAC Enable
7414  * ALT_SDMMC_BMOD_DE_E_DISD | 0x0 | IDMAC Disable
7415  *
7416  * Field Access Macros:
7417  *
7418  */
7419 /*
7420  * Enumerated value for register field ALT_SDMMC_BMOD_DE
7421  *
7422  * IDMAC Enable
7423  */
7424 #define ALT_SDMMC_BMOD_DE_E_END 0x1
7425 /*
7426  * Enumerated value for register field ALT_SDMMC_BMOD_DE
7427  *
7428  * IDMAC Disable
7429  */
7430 #define ALT_SDMMC_BMOD_DE_E_DISD 0x0
7431 
7432 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DE register field. */
7433 #define ALT_SDMMC_BMOD_DE_LSB 7
7434 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DE register field. */
7435 #define ALT_SDMMC_BMOD_DE_MSB 7
7436 /* The width in bits of the ALT_SDMMC_BMOD_DE register field. */
7437 #define ALT_SDMMC_BMOD_DE_WIDTH 1
7438 /* The mask used to set the ALT_SDMMC_BMOD_DE register field value. */
7439 #define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
7440 /* The mask used to clear the ALT_SDMMC_BMOD_DE register field value. */
7441 #define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
7442 /* The reset value of the ALT_SDMMC_BMOD_DE register field. */
7443 #define ALT_SDMMC_BMOD_DE_RESET 0x0
7444 /* Extracts the ALT_SDMMC_BMOD_DE field value from a register. */
7445 #define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
7446 /* Produces a ALT_SDMMC_BMOD_DE register field value suitable for setting the register. */
7447 #define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
7448 
7449 /*
7450  * Field : Programmable Burst Length - pbl
7451  *
7452  * These bits indicate the maximum number of beats to be performed in one IDMAC
7453  * transaction. The IDMAC will always attempt to burst as specified in PBL each
7454  * time it starts a Burst transfer on the host bus. This value is the mirror of
7455  * MSIZE of FIFOTH register. In order to change this value, write the required
7456  * value to FIFOTH register. This is an encode value as follows.
7457  *
7458  * Field Enumeration Values:
7459  *
7460  * Enum | Value | Description
7461  * :------------------------------|:------|:-------------
7462  * ALT_SDMMC_BMOD_PBL_E_TRANS1 | 0x0 | Transfer 1
7463  * ALT_SDMMC_BMOD_PBL_E_TRANS4 | 0x1 | Transfer 4
7464  * ALT_SDMMC_BMOD_PBL_E_TRANS8 | 0x2 | Transfer 8
7465  * ALT_SDMMC_BMOD_PBL_E_TRANS16 | 0x3 | Transfer 16
7466  * ALT_SDMMC_BMOD_PBL_E_TRANS32 | 0x4 | Transfer 32
7467  * ALT_SDMMC_BMOD_PBL_E_TRANS64 | 0x5 | Transfer 64
7468  * ALT_SDMMC_BMOD_PBL_E_TRANS128 | 0x6 | Transfer 128
7469  * ALT_SDMMC_BMOD_PBL_E_TRANS256 | 0x7 | Transfer 256
7470  *
7471  * Field Access Macros:
7472  *
7473  */
7474 /*
7475  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7476  *
7477  * Transfer 1
7478  */
7479 #define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
7480 /*
7481  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7482  *
7483  * Transfer 4
7484  */
7485 #define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
7486 /*
7487  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7488  *
7489  * Transfer 8
7490  */
7491 #define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
7492 /*
7493  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7494  *
7495  * Transfer 16
7496  */
7497 #define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
7498 /*
7499  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7500  *
7501  * Transfer 32
7502  */
7503 #define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
7504 /*
7505  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7506  *
7507  * Transfer 64
7508  */
7509 #define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
7510 /*
7511  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7512  *
7513  * Transfer 128
7514  */
7515 #define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
7516 /*
7517  * Enumerated value for register field ALT_SDMMC_BMOD_PBL
7518  *
7519  * Transfer 256
7520  */
7521 #define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
7522 
7523 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_PBL register field. */
7524 #define ALT_SDMMC_BMOD_PBL_LSB 8
7525 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_PBL register field. */
7526 #define ALT_SDMMC_BMOD_PBL_MSB 10
7527 /* The width in bits of the ALT_SDMMC_BMOD_PBL register field. */
7528 #define ALT_SDMMC_BMOD_PBL_WIDTH 3
7529 /* The mask used to set the ALT_SDMMC_BMOD_PBL register field value. */
7530 #define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
7531 /* The mask used to clear the ALT_SDMMC_BMOD_PBL register field value. */
7532 #define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
7533 /* The reset value of the ALT_SDMMC_BMOD_PBL register field. */
7534 #define ALT_SDMMC_BMOD_PBL_RESET 0x0
7535 /* Extracts the ALT_SDMMC_BMOD_PBL field value from a register. */
7536 #define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
7537 /* Produces a ALT_SDMMC_BMOD_PBL register field value suitable for setting the register. */
7538 #define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
7539 
7540 #ifndef __ASSEMBLY__
7541 /*
7542  * WARNING: The C register and register group struct declarations are provided for
7543  * convenience and illustrative purposes. They should, however, be used with
7544  * caution as the C language standard provides no guarantees about the alignment or
7545  * atomicity of device memory accesses. The recommended practice for writing
7546  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7547  * alt_write_word() functions.
7548  *
7549  * The struct declaration for register ALT_SDMMC_BMOD.
7550  */
7551 struct ALT_SDMMC_BMOD_s
7552 {
7553  uint32_t swr : 1; /* Software Reset */
7554  uint32_t fb : 1; /* Fixed Burst */
7555  uint32_t dsl : 5; /* Descriptor Skip Length */
7556  uint32_t de : 1; /* IDMAC Enable */
7557  const uint32_t pbl : 3; /* Programmable Burst Length */
7558  uint32_t : 21; /* *UNDEFINED* */
7559 };
7560 
7561 /* The typedef declaration for register ALT_SDMMC_BMOD. */
7562 typedef volatile struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t;
7563 #endif /* __ASSEMBLY__ */
7564 
7565 /* The byte offset of the ALT_SDMMC_BMOD register from the beginning of the component. */
7566 #define ALT_SDMMC_BMOD_OFST 0x80
7567 
7568 /*
7569  * Register : Poll Demand Register - pldmnd
7570  *
7571  * See Field Description.
7572  *
7573  * Register Layout
7574  *
7575  * Bits | Access | Reset | Description
7576  * :-------|:-------|:------|:------------
7577  * [31:0] | W | 0x0 | Poll Demand
7578  *
7579  */
7580 /*
7581  * Field : Poll Demand - pd
7582  *
7583  * If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state.
7584  * The host needs to write any value into this register for the IDMAC FSM to resume
7585  * normal descriptor fetch operation.
7586  *
7587  * Field Access Macros:
7588  *
7589  */
7590 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_PLDMND_PD register field. */
7591 #define ALT_SDMMC_PLDMND_PD_LSB 0
7592 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_PLDMND_PD register field. */
7593 #define ALT_SDMMC_PLDMND_PD_MSB 31
7594 /* The width in bits of the ALT_SDMMC_PLDMND_PD register field. */
7595 #define ALT_SDMMC_PLDMND_PD_WIDTH 32
7596 /* The mask used to set the ALT_SDMMC_PLDMND_PD register field value. */
7597 #define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
7598 /* The mask used to clear the ALT_SDMMC_PLDMND_PD register field value. */
7599 #define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
7600 /* The reset value of the ALT_SDMMC_PLDMND_PD register field. */
7601 #define ALT_SDMMC_PLDMND_PD_RESET 0x0
7602 /* Extracts the ALT_SDMMC_PLDMND_PD field value from a register. */
7603 #define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
7604 /* Produces a ALT_SDMMC_PLDMND_PD register field value suitable for setting the register. */
7605 #define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
7606 
7607 #ifndef __ASSEMBLY__
7608 /*
7609  * WARNING: The C register and register group struct declarations are provided for
7610  * convenience and illustrative purposes. They should, however, be used with
7611  * caution as the C language standard provides no guarantees about the alignment or
7612  * atomicity of device memory accesses. The recommended practice for writing
7613  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7614  * alt_write_word() functions.
7615  *
7616  * The struct declaration for register ALT_SDMMC_PLDMND.
7617  */
7618 struct ALT_SDMMC_PLDMND_s
7619 {
7620  uint32_t pd : 32; /* Poll Demand */
7621 };
7622 
7623 /* The typedef declaration for register ALT_SDMMC_PLDMND. */
7624 typedef volatile struct ALT_SDMMC_PLDMND_s ALT_SDMMC_PLDMND_t;
7625 #endif /* __ASSEMBLY__ */
7626 
7627 /* The byte offset of the ALT_SDMMC_PLDMND register from the beginning of the component. */
7628 #define ALT_SDMMC_PLDMND_OFST 0x84
7629 
7630 /*
7631  * Register : Descriptor List Base Address Register - dbaddr
7632  *
7633  * See Field Descriptor
7634  *
7635  * Register Layout
7636  *
7637  * Bits | Access | Reset | Description
7638  * :-------|:-------|:------|:-------------------------
7639  * [1:0] | ??? | 0x0 | *UNDEFINED*
7640  * [31:2] | RW | 0x0 | Start of Descriptor List
7641  *
7642  */
7643 /*
7644  * Field : Start of Descriptor List - sdl
7645  *
7646  * Contains the base address of the First Descriptor. This is the byte address
7647  * divided by 4.
7648  *
7649  * Field Access Macros:
7650  *
7651  */
7652 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
7653 #define ALT_SDMMC_DBADDR_SDL_LSB 2
7654 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DBADDR_SDL register field. */
7655 #define ALT_SDMMC_DBADDR_SDL_MSB 31
7656 /* The width in bits of the ALT_SDMMC_DBADDR_SDL register field. */
7657 #define ALT_SDMMC_DBADDR_SDL_WIDTH 30
7658 /* The mask used to set the ALT_SDMMC_DBADDR_SDL register field value. */
7659 #define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xfffffffc
7660 /* The mask used to clear the ALT_SDMMC_DBADDR_SDL register field value. */
7661 #define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000003
7662 /* The reset value of the ALT_SDMMC_DBADDR_SDL register field. */
7663 #define ALT_SDMMC_DBADDR_SDL_RESET 0x0
7664 /* Extracts the ALT_SDMMC_DBADDR_SDL field value from a register. */
7665 #define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xfffffffc) >> 2)
7666 /* Produces a ALT_SDMMC_DBADDR_SDL register field value suitable for setting the register. */
7667 #define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 2) & 0xfffffffc)
7668 
7669 #ifndef __ASSEMBLY__
7670 /*
7671  * WARNING: The C register and register group struct declarations are provided for
7672  * convenience and illustrative purposes. They should, however, be used with
7673  * caution as the C language standard provides no guarantees about the alignment or
7674  * atomicity of device memory accesses. The recommended practice for writing
7675  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7676  * alt_write_word() functions.
7677  *
7678  * The struct declaration for register ALT_SDMMC_DBADDR.
7679  */
7680 struct ALT_SDMMC_DBADDR_s
7681 {
7682  uint32_t : 2; /* *UNDEFINED* */
7683  uint32_t sdl : 30; /* Start of Descriptor List */
7684 };
7685 
7686 /* The typedef declaration for register ALT_SDMMC_DBADDR. */
7687 typedef volatile struct ALT_SDMMC_DBADDR_s ALT_SDMMC_DBADDR_t;
7688 #endif /* __ASSEMBLY__ */
7689 
7690 /* The byte offset of the ALT_SDMMC_DBADDR register from the beginning of the component. */
7691 #define ALT_SDMMC_DBADDR_OFST 0x88
7692 
7693 /*
7694  * Register : Internal DMAC Status Register - idsts
7695  *
7696  * Sets Internal DMAC Status Fields
7697  *
7698  * Register Layout
7699  *
7700  * Bits | Access | Reset | Description
7701  * :--------|:-------|:------|:---------------------------------
7702  * [0] | RW | 0x0 | Transmit Interrupt
7703  * [1] | RW | 0x0 | Receive Interrupt
7704  * [2] | RW | 0x0 | Fatal Bus Error Interrupt
7705  * [3] | ??? | 0x0 | *UNDEFINED*
7706  * [4] | RW | 0x0 | Descriptor Unavailable Interrupt
7707  * [5] | RW | 0x0 | Card Error Summary
7708  * [7:6] | ??? | 0x0 | *UNDEFINED*
7709  * [8] | RW | 0x0 | Normal Interrupt Summary
7710  * [9] | RW | 0x0 | Abnormal Interrupt Summary
7711  * [12:10] | R | 0x0 | Error Bits
7712  * [16:13] | R | 0x0 | Finite State Machine
7713  * [31:17] | ??? | 0x0 | *UNDEFINED*
7714  *
7715  */
7716 /*
7717  * Field : Transmit Interrupt - ti
7718  *
7719  * Indicates that data transmission is finished for a descriptor.
7720  *
7721  * Field Enumeration Values:
7722  *
7723  * Enum | Value | Description
7724  * :---------------------------|:------|:------------------------------------------
7725  * ALT_SDMMC_IDSTS_TI_E_CLR | 0x1 | Clears Transmit Interrupt Status Bit
7726  * ALT_SDMMC_IDSTS_TI_E_NOCLR | 0x0 | No Clear of Transmit Interrupt Status Bit
7727  *
7728  * Field Access Macros:
7729  *
7730  */
7731 /*
7732  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
7733  *
7734  * Clears Transmit Interrupt Status Bit
7735  */
7736 #define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
7737 /*
7738  * Enumerated value for register field ALT_SDMMC_IDSTS_TI
7739  *
7740  * No Clear of Transmit Interrupt Status Bit
7741  */
7742 #define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
7743 
7744 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_TI register field. */
7745 #define ALT_SDMMC_IDSTS_TI_LSB 0
7746 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_TI register field. */
7747 #define ALT_SDMMC_IDSTS_TI_MSB 0
7748 /* The width in bits of the ALT_SDMMC_IDSTS_TI register field. */
7749 #define ALT_SDMMC_IDSTS_TI_WIDTH 1
7750 /* The mask used to set the ALT_SDMMC_IDSTS_TI register field value. */
7751 #define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
7752 /* The mask used to clear the ALT_SDMMC_IDSTS_TI register field value. */
7753 #define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
7754 /* The reset value of the ALT_SDMMC_IDSTS_TI register field. */
7755 #define ALT_SDMMC_IDSTS_TI_RESET 0x0
7756 /* Extracts the ALT_SDMMC_IDSTS_TI field value from a register. */
7757 #define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
7758 /* Produces a ALT_SDMMC_IDSTS_TI register field value suitable for setting the register. */
7759 #define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
7760 
7761 /*
7762  * Field : Receive Interrupt - ri
7763  *
7764  * Indicates the completion of data reception for a descriptor
7765  *
7766  * Field Enumeration Values:
7767  *
7768  * Enum | Value | Description
7769  * :---------------------------|:------|:-----------------------------------------
7770  * ALT_SDMMC_IDSTS_RI_E_CLR | 0x1 | Clears Receive Interrupt Status Bit
7771  * ALT_SDMMC_IDSTS_RI_E_NOCLR | 0x0 | No Clear of Receive Interrupt Status Bit
7772  *
7773  * Field Access Macros:
7774  *
7775  */
7776 /*
7777  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
7778  *
7779  * Clears Receive Interrupt Status Bit
7780  */
7781 #define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
7782 /*
7783  * Enumerated value for register field ALT_SDMMC_IDSTS_RI
7784  *
7785  * No Clear of Receive Interrupt Status Bit
7786  */
7787 #define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
7788 
7789 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_RI register field. */
7790 #define ALT_SDMMC_IDSTS_RI_LSB 1
7791 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_RI register field. */
7792 #define ALT_SDMMC_IDSTS_RI_MSB 1
7793 /* The width in bits of the ALT_SDMMC_IDSTS_RI register field. */
7794 #define ALT_SDMMC_IDSTS_RI_WIDTH 1
7795 /* The mask used to set the ALT_SDMMC_IDSTS_RI register field value. */
7796 #define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
7797 /* The mask used to clear the ALT_SDMMC_IDSTS_RI register field value. */
7798 #define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
7799 /* The reset value of the ALT_SDMMC_IDSTS_RI register field. */
7800 #define ALT_SDMMC_IDSTS_RI_RESET 0x0
7801 /* Extracts the ALT_SDMMC_IDSTS_RI field value from a register. */
7802 #define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
7803 /* Produces a ALT_SDMMC_IDSTS_RI register field value suitable for setting the register. */
7804 #define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
7805 
7806 /*
7807  * Field : Fatal Bus Error Interrupt - fbe
7808  *
7809  * Indicates that a Bus Error occurred (IDSTS[12:10]). When setthe DMA disables all
7810  * its bus accesses.
7811  *
7812  * Field Enumeration Values:
7813  *
7814  * Enum | Value | Description
7815  * :----------------------------|:------|:-------------------------------------------------
7816  * ALT_SDMMC_IDSTS_FBE_E_CLR | 0x1 | Clears Fatal Bus Error Interrupt Status Bit
7817  * ALT_SDMMC_IDSTS_FBE_E_NOCLR | 0x0 | No Clear of Fatal Bus Error Interrupt Status Bit
7818  *
7819  * Field Access Macros:
7820  *
7821  */
7822 /*
7823  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
7824  *
7825  * Clears Fatal Bus Error Interrupt Status Bit
7826  */
7827 #define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
7828 /*
7829  * Enumerated value for register field ALT_SDMMC_IDSTS_FBE
7830  *
7831  * No Clear of Fatal Bus Error Interrupt Status Bit
7832  */
7833 #define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
7834 
7835 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
7836 #define ALT_SDMMC_IDSTS_FBE_LSB 2
7837 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FBE register field. */
7838 #define ALT_SDMMC_IDSTS_FBE_MSB 2
7839 /* The width in bits of the ALT_SDMMC_IDSTS_FBE register field. */
7840 #define ALT_SDMMC_IDSTS_FBE_WIDTH 1
7841 /* The mask used to set the ALT_SDMMC_IDSTS_FBE register field value. */
7842 #define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
7843 /* The mask used to clear the ALT_SDMMC_IDSTS_FBE register field value. */
7844 #define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
7845 /* The reset value of the ALT_SDMMC_IDSTS_FBE register field. */
7846 #define ALT_SDMMC_IDSTS_FBE_RESET 0x0
7847 /* Extracts the ALT_SDMMC_IDSTS_FBE field value from a register. */
7848 #define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
7849 /* Produces a ALT_SDMMC_IDSTS_FBE register field value suitable for setting the register. */
7850 #define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
7851 
7852 /*
7853  * Field : Descriptor Unavailable Interrupt - du
7854  *
7855  * This status bit is set when the descriptor is unavailable due to OWN bit = 0
7856  * (DES0[31] =0).
7857  *
7858  * Field Enumeration Values:
7859  *
7860  * Enum | Value | Description
7861  * :---------------------------|:------|:-----------------------------------------------
7862  * ALT_SDMMC_IDSTS_DU_E_CLR | 0x1 | Clears Descriptor Unavailable Interrupt Status
7863  * : | | Bit
7864  * ALT_SDMMC_IDSTS_DU_E_NOCLR | 0x0 | No Clear of Descriptor Unavailable Interrupt
7865  * : | | Status Bit
7866  *
7867  * Field Access Macros:
7868  *
7869  */
7870 /*
7871  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
7872  *
7873  * Clears Descriptor Unavailable Interrupt Status Bit
7874  */
7875 #define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
7876 /*
7877  * Enumerated value for register field ALT_SDMMC_IDSTS_DU
7878  *
7879  * No Clear of Descriptor Unavailable Interrupt Status Bit
7880  */
7881 #define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
7882 
7883 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_DU register field. */
7884 #define ALT_SDMMC_IDSTS_DU_LSB 4
7885 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_DU register field. */
7886 #define ALT_SDMMC_IDSTS_DU_MSB 4
7887 /* The width in bits of the ALT_SDMMC_IDSTS_DU register field. */
7888 #define ALT_SDMMC_IDSTS_DU_WIDTH 1
7889 /* The mask used to set the ALT_SDMMC_IDSTS_DU register field value. */
7890 #define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
7891 /* The mask used to clear the ALT_SDMMC_IDSTS_DU register field value. */
7892 #define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
7893 /* The reset value of the ALT_SDMMC_IDSTS_DU register field. */
7894 #define ALT_SDMMC_IDSTS_DU_RESET 0x0
7895 /* Extracts the ALT_SDMMC_IDSTS_DU field value from a register. */
7896 #define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
7897 /* Produces a ALT_SDMMC_IDSTS_DU register field value suitable for setting the register. */
7898 #define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
7899 
7900 /*
7901  * Field : Card Error Summary - ces
7902  *
7903  * Indicates the status of the transaction to/from the card; also present in
7904  * RINTSTS. Indicates the logical OR of the following bits:
7905  *
7906  * EBE - End Bit Error
7907  *
7908  * RTO - Response Timeout/Boot Ack Timeout
7909  *
7910  * RCRC - Response CRC
7911  *
7912  * SBE - Start Bit Error
7913  *
7914  * DRTO - Data Read Timeout/BDS timeout
7915  *
7916  * DCRC - Data CRC for Receive
7917  *
7918  * RE - Response Error
7919  *
7920  * Field Enumeration Values:
7921  *
7922  * Enum | Value | Description
7923  * :----------------------------|:------|:-------------------------------------------------
7924  * ALT_SDMMC_IDSTS_CES_E_CLR | 0x1 | Clears Card Error Summary Interrupt Status Bit
7925  * ALT_SDMMC_IDSTS_CES_E_NOCLR | 0x0 | No Clear Card Error Summary Interrupt Status Bit
7926  *
7927  * Field Access Macros:
7928  *
7929  */
7930 /*
7931  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
7932  *
7933  * Clears Card Error Summary Interrupt Status Bit
7934  */
7935 #define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
7936 /*
7937  * Enumerated value for register field ALT_SDMMC_IDSTS_CES
7938  *
7939  * No Clear Card Error Summary Interrupt Status Bit
7940  */
7941 #define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
7942 
7943 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_CES register field. */
7944 #define ALT_SDMMC_IDSTS_CES_LSB 5
7945 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_CES register field. */
7946 #define ALT_SDMMC_IDSTS_CES_MSB 5
7947 /* The width in bits of the ALT_SDMMC_IDSTS_CES register field. */
7948 #define ALT_SDMMC_IDSTS_CES_WIDTH 1
7949 /* The mask used to set the ALT_SDMMC_IDSTS_CES register field value. */
7950 #define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
7951 /* The mask used to clear the ALT_SDMMC_IDSTS_CES register field value. */
7952 #define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
7953 /* The reset value of the ALT_SDMMC_IDSTS_CES register field. */
7954 #define ALT_SDMMC_IDSTS_CES_RESET 0x0
7955 /* Extracts the ALT_SDMMC_IDSTS_CES field value from a register. */
7956 #define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
7957 /* Produces a ALT_SDMMC_IDSTS_CES register field value suitable for setting the register. */
7958 #define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
7959 
7960 /*
7961  * Field : Normal Interrupt Summary - nis
7962  *
7963  * Logical OR of the following:
7964  *
7965  * IDSTS[0] - Transmit Interrupt
7966  *
7967  * IDSTS[1] - Receive Interrupt
7968  *
7969  * Only unmasked bits affect this bit. This is a sticky bit and must be cleared
7970  * each time a corresponding bit that causes NIS to be set is cleared.
7971  *
7972  * Field Enumeration Values:
7973  *
7974  * Enum | Value | Description
7975  * :----------------------------|:------|:----------------------------------------------
7976  * ALT_SDMMC_IDSTS_NIS_E_CLR | 0x1 | Clears Normal Interrupt Summary Status Bit
7977  * ALT_SDMMC_IDSTS_NIS_E_NOCLR | 0x0 | No Clear Normal Interrupt Summary Status Bit
7978  *
7979  * Field Access Macros:
7980  *
7981  */
7982 /*
7983  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
7984  *
7985  * Clears Normal Interrupt Summary Status Bit
7986  */
7987 #define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
7988 /*
7989  * Enumerated value for register field ALT_SDMMC_IDSTS_NIS
7990  *
7991  * No Clear Normal Interrupt Summary Status Bit
7992  */
7993 #define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
7994 
7995 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
7996 #define ALT_SDMMC_IDSTS_NIS_LSB 8
7997 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_NIS register field. */
7998 #define ALT_SDMMC_IDSTS_NIS_MSB 8
7999 /* The width in bits of the ALT_SDMMC_IDSTS_NIS register field. */
8000 #define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8001 /* The mask used to set the ALT_SDMMC_IDSTS_NIS register field value. */
8002 #define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8003 /* The mask used to clear the ALT_SDMMC_IDSTS_NIS register field value. */
8004 #define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8005 /* The reset value of the ALT_SDMMC_IDSTS_NIS register field. */
8006 #define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8007 /* Extracts the ALT_SDMMC_IDSTS_NIS field value from a register. */
8008 #define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8009 /* Produces a ALT_SDMMC_IDSTS_NIS register field value suitable for setting the register. */
8010 #define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8011 
8012 /*
8013  * Field : Abnormal Interrupt Summary - ais
8014  *
8015  * Logical OR of the following:
8016  *
8017  * IDSTS[2] - Fatal Bus Interrupt
8018  *
8019  * IDSTS[4] - DU bit Interrupt
8020  *
8021  * IDSTS[5] - Card Error Summary Interrupt
8022  *
8023  * Only unmasked bits affect this bit. This is a sticky bit and must be cleared
8024  * each time a corresponding bit that causes AIS to be set is cleared.
8025  *
8026  * Field Enumeration Values:
8027  *
8028  * Enum | Value | Description
8029  * :----------------------------|:------|:-----------------------------------------------
8030  * ALT_SDMMC_IDSTS_AIS_E_CLR | 0x1 | Clears Abnormal Summary Interrupt Status Bit
8031  * ALT_SDMMC_IDSTS_AIS_E_NOCLR | 0x0 | No Clear Abnormal Summary Interrupt Status Bit
8032  *
8033  * Field Access Macros:
8034  *
8035  */
8036 /*
8037  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
8038  *
8039  * Clears Abnormal Summary Interrupt Status Bit
8040  */
8041 #define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8042 /*
8043  * Enumerated value for register field ALT_SDMMC_IDSTS_AIS
8044  *
8045  * No Clear Abnormal Summary Interrupt Status Bit
8046  */
8047 #define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8048 
8049 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
8050 #define ALT_SDMMC_IDSTS_AIS_LSB 9
8051 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_AIS register field. */
8052 #define ALT_SDMMC_IDSTS_AIS_MSB 9
8053 /* The width in bits of the ALT_SDMMC_IDSTS_AIS register field. */
8054 #define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8055 /* The mask used to set the ALT_SDMMC_IDSTS_AIS register field value. */
8056 #define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8057 /* The mask used to clear the ALT_SDMMC_IDSTS_AIS register field value. */
8058 #define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8059 /* The reset value of the ALT_SDMMC_IDSTS_AIS register field. */
8060 #define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8061 /* Extracts the ALT_SDMMC_IDSTS_AIS field value from a register. */
8062 #define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8063 /* Produces a ALT_SDMMC_IDSTS_AIS register field value suitable for setting the register. */
8064 #define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
8065 
8066 /*
8067  * Field : Error Bits - eb
8068  *
8069  * Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus
8070  * Error bit (IDSTS[2]) set. This field does not generate an interrupt.
8071  *
8072  * Field Enumeration Values:
8073  *
8074  * Enum | Value | Description
8075  * :--------------------------------|:------|:------------------------------------------------
8076  * ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX | 0x1 | Host Abort during transmission Status Bit
8077  * ALT_SDMMC_IDSTS_EB_E_HOSTARBRX | 0x2 | Host Abort received during reception Status Bit
8078  *
8079  * Field Access Macros:
8080  *
8081  */
8082 /*
8083  * Enumerated value for register field ALT_SDMMC_IDSTS_EB
8084  *
8085  * Host Abort during transmission Status Bit
8086  */
8087 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
8088 /*
8089  * Enumerated value for register field ALT_SDMMC_IDSTS_EB
8090  *
8091  * Host Abort received during reception Status Bit
8092  */
8093 #define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
8094 
8095 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_EB register field. */
8096 #define ALT_SDMMC_IDSTS_EB_LSB 10
8097 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_EB register field. */
8098 #define ALT_SDMMC_IDSTS_EB_MSB 12
8099 /* The width in bits of the ALT_SDMMC_IDSTS_EB register field. */
8100 #define ALT_SDMMC_IDSTS_EB_WIDTH 3
8101 /* The mask used to set the ALT_SDMMC_IDSTS_EB register field value. */
8102 #define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
8103 /* The mask used to clear the ALT_SDMMC_IDSTS_EB register field value. */
8104 #define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
8105 /* The reset value of the ALT_SDMMC_IDSTS_EB register field. */
8106 #define ALT_SDMMC_IDSTS_EB_RESET 0x0
8107 /* Extracts the ALT_SDMMC_IDSTS_EB field value from a register. */
8108 #define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
8109 /* Produces a ALT_SDMMC_IDSTS_EB register field value suitable for setting the register. */
8110 #define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
8111 
8112 /*
8113  * Field : Finite State Machine - fsm
8114  *
8115  * DMAC FSM present state.
8116  *
8117  * Field Enumeration Values:
8118  *
8119  * Enum | Value | Description
8120  * :-----------------------------------|:------|:----------------
8121  * ALT_SDMMC_IDSTS_FSM_E_DMAIDLE | 0x0 | DMA IDLE
8122  * ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND | 0x1 | DMA SUSPEND
8123  * ALT_SDMMC_IDSTS_FSM_E_DESCRD | 0x2 | DESC_RD
8124  * ALT_SDMMC_IDSTS_FSM_E_DESCCHK | 0x3 | DESC_CHK
8125  * ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT | 0x4 | DMA RD REQ WAIT
8126  * ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT | 0x5 | DMA WR REQ WAIT
8127  * ALT_SDMMC_IDSTS_FSM_E_DMARD | 0x6 | DMA RD
8128  * ALT_SDMMC_IDSTS_FSM_E_DMAWR | 0x7 | DMA WR
8129  * ALT_SDMMC_IDSTS_FSM_E_DECCLOSE | 0x8 | DESC CLOSE
8130  *
8131  * Field Access Macros:
8132  *
8133  */
8134 /*
8135  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8136  *
8137  * DMA IDLE
8138  */
8139 #define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
8140 /*
8141  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8142  *
8143  * DMA SUSPEND
8144  */
8145 #define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
8146 /*
8147  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8148  *
8149  * DESC_RD
8150  */
8151 #define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
8152 /*
8153  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8154  *
8155  * DESC_CHK
8156  */
8157 #define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
8158 /*
8159  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8160  *
8161  * DMA RD REQ WAIT
8162  */
8163 #define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
8164 /*
8165  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8166  *
8167  * DMA WR REQ WAIT
8168  */
8169 #define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
8170 /*
8171  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8172  *
8173  * DMA RD
8174  */
8175 #define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
8176 /*
8177  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8178  *
8179  * DMA WR
8180  */
8181 #define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
8182 /*
8183  * Enumerated value for register field ALT_SDMMC_IDSTS_FSM
8184  *
8185  * DESC CLOSE
8186  */
8187 #define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
8188 
8189 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
8190 #define ALT_SDMMC_IDSTS_FSM_LSB 13
8191 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FSM register field. */
8192 #define ALT_SDMMC_IDSTS_FSM_MSB 16
8193 /* The width in bits of the ALT_SDMMC_IDSTS_FSM register field. */
8194 #define ALT_SDMMC_IDSTS_FSM_WIDTH 4
8195 /* The mask used to set the ALT_SDMMC_IDSTS_FSM register field value. */
8196 #define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
8197 /* The mask used to clear the ALT_SDMMC_IDSTS_FSM register field value. */
8198 #define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
8199 /* The reset value of the ALT_SDMMC_IDSTS_FSM register field. */
8200 #define ALT_SDMMC_IDSTS_FSM_RESET 0x0
8201 /* Extracts the ALT_SDMMC_IDSTS_FSM field value from a register. */
8202 #define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
8203 /* Produces a ALT_SDMMC_IDSTS_FSM register field value suitable for setting the register. */
8204 #define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
8205 
8206 #ifndef __ASSEMBLY__
8207 /*
8208  * WARNING: The C register and register group struct declarations are provided for
8209  * convenience and illustrative purposes. They should, however, be used with
8210  * caution as the C language standard provides no guarantees about the alignment or
8211  * atomicity of device memory accesses. The recommended practice for writing
8212  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8213  * alt_write_word() functions.
8214  *
8215  * The struct declaration for register ALT_SDMMC_IDSTS.
8216  */
8217 struct ALT_SDMMC_IDSTS_s
8218 {
8219  uint32_t ti : 1; /* Transmit Interrupt */
8220  uint32_t ri : 1; /* Receive Interrupt */
8221  uint32_t fbe : 1; /* Fatal Bus Error Interrupt */
8222  uint32_t : 1; /* *UNDEFINED* */
8223  uint32_t du : 1; /* Descriptor Unavailable Interrupt */
8224  uint32_t ces : 1; /* Card Error Summary */
8225  uint32_t : 2; /* *UNDEFINED* */
8226  uint32_t nis : 1; /* Normal Interrupt Summary */
8227  uint32_t ais : 1; /* Abnormal Interrupt Summary */
8228  const uint32_t eb : 3; /* Error Bits */
8229  const uint32_t fsm : 4; /* Finite State Machine */
8230  uint32_t : 15; /* *UNDEFINED* */
8231 };
8232 
8233 /* The typedef declaration for register ALT_SDMMC_IDSTS. */
8234 typedef volatile struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t;
8235 #endif /* __ASSEMBLY__ */
8236 
8237 /* The byte offset of the ALT_SDMMC_IDSTS register from the beginning of the component. */
8238 #define ALT_SDMMC_IDSTS_OFST 0x8c
8239 
8240 /*
8241  * Register : Internal DMAC Interrupt Enable Register - idinten
8242  *
8243  * Various DMA Interrupt Enable Status
8244  *
8245  * Register Layout
8246  *
8247  * Bits | Access | Reset | Description
8248  * :--------|:-------|:------|:------------------------------------
8249  * [0] | RW | 0x0 | Transmit Interrupt Enable
8250  * [1] | RW | 0x0 | Receive Interrupt Enable
8251  * [2] | RW | 0x0 | Fatal Bus Error
8252  * [3] | ??? | 0x0 | *UNDEFINED*
8253  * [4] | RW | 0x0 | Descriptor Unavailable Interrupt
8254  * [5] | RW | 0x0 | Card Error Summary Interrupt Enable
8255  * [7:6] | ??? | 0x0 | *UNDEFINED*
8256  * [8] | RW | 0x0 | Normal Interrupt Summary Enable
8257  * [9] | RW | 0x0 | Abnormal Interrupt Summary Enable.
8258  * [31:10] | ??? | 0x0 | *UNDEFINED*
8259  *
8260  */
8261 /*
8262  * Field : Transmit Interrupt Enable - ti
8263  *
8264  * Enables and Disables Transmit Interrupt when Normal Interrupt Summary Enable is
8265  * set.
8266  *
8267  * Field Enumeration Values:
8268  *
8269  * Enum | Value | Description
8270  * :----------------------------|:------|:-------------------------------
8271  * ALT_SDMMC_IDINTEN_TI_E_END | 0x1 | Transmit Interrupt is enabled
8272  * ALT_SDMMC_IDINTEN_TI_E_DISD | 0x0 | Transmit Interrupt is disabled
8273  *
8274  * Field Access Macros:
8275  *
8276  */
8277 /*
8278  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
8279  *
8280  * Transmit Interrupt is enabled
8281  */
8282 #define ALT_SDMMC_IDINTEN_TI_E_END 0x1
8283 /*
8284  * Enumerated value for register field ALT_SDMMC_IDINTEN_TI
8285  *
8286  * Transmit Interrupt is disabled
8287  */
8288 #define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
8289 
8290 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
8291 #define ALT_SDMMC_IDINTEN_TI_LSB 0
8292 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_TI register field. */
8293 #define ALT_SDMMC_IDINTEN_TI_MSB 0
8294 /* The width in bits of the ALT_SDMMC_IDINTEN_TI register field. */
8295 #define ALT_SDMMC_IDINTEN_TI_WIDTH 1
8296 /* The mask used to set the ALT_SDMMC_IDINTEN_TI register field value. */
8297 #define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
8298 /* The mask used to clear the ALT_SDMMC_IDINTEN_TI register field value. */
8299 #define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
8300 /* The reset value of the ALT_SDMMC_IDINTEN_TI register field. */
8301 #define ALT_SDMMC_IDINTEN_TI_RESET 0x0
8302 /* Extracts the ALT_SDMMC_IDINTEN_TI field value from a register. */
8303 #define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
8304 /* Produces a ALT_SDMMC_IDINTEN_TI register field value suitable for setting the register. */
8305 #define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
8306 
8307 /*
8308  * Field : Receive Interrupt Enable - ri
8309  *
8310  * Enables and Disables Receive Interrupt when Normal Interrupt Summary Enable is
8311  * set.
8312  *
8313  * Field Enumeration Values:
8314  *
8315  * Enum | Value | Description
8316  * :----------------------------|:------|:------------------------------
8317  * ALT_SDMMC_IDINTEN_RI_E_END | 0x1 | Receive Interrupt is enabled
8318  * ALT_SDMMC_IDINTEN_RI_E_DISD | 0x0 | Receive Interrupt is disabled
8319  *
8320  * Field Access Macros:
8321  *
8322  */
8323 /*
8324  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
8325  *
8326  * Receive Interrupt is enabled
8327  */
8328 #define ALT_SDMMC_IDINTEN_RI_E_END 0x1
8329 /*
8330  * Enumerated value for register field ALT_SDMMC_IDINTEN_RI
8331  *
8332  * Receive Interrupt is disabled
8333  */
8334 #define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
8335 
8336 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
8337 #define ALT_SDMMC_IDINTEN_RI_LSB 1
8338 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_RI register field. */
8339 #define ALT_SDMMC_IDINTEN_RI_MSB 1
8340 /* The width in bits of the ALT_SDMMC_IDINTEN_RI register field. */
8341 #define ALT_SDMMC_IDINTEN_RI_WIDTH 1
8342 /* The mask used to set the ALT_SDMMC_IDINTEN_RI register field value. */
8343 #define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
8344 /* The mask used to clear the ALT_SDMMC_IDINTEN_RI register field value. */
8345 #define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
8346 /* The reset value of the ALT_SDMMC_IDINTEN_RI register field. */
8347 #define ALT_SDMMC_IDINTEN_RI_RESET 0x0
8348 /* Extracts the ALT_SDMMC_IDINTEN_RI field value from a register. */
8349 #define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
8350 /* Produces a ALT_SDMMC_IDINTEN_RI register field value suitable for setting the register. */
8351 #define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
8352 
8353 /*
8354  * Field : Fatal Bus Error - fbe
8355  *
8356  * When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt
8357  * is enabled.
8358  *
8359  * Field Enumeration Values:
8360  *
8361  * Enum | Value | Description
8362  * :-----------------------------|:------|:--------------------------------------
8363  * ALT_SDMMC_IDINTEN_FBE_E_END | 0x1 | Fatal Bus Error Interrupt is enabled
8364  * ALT_SDMMC_IDINTEN_FBE_E_DISD | 0x0 | Fatal Bus Error Interrupt is disabled
8365  *
8366  * Field Access Macros:
8367  *
8368  */
8369 /*
8370  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
8371  *
8372  * Fatal Bus Error Interrupt is enabled
8373  */
8374 #define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
8375 /*
8376  * Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
8377  *
8378  * Fatal Bus Error Interrupt is disabled
8379  */
8380 #define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
8381 
8382 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
8383 #define ALT_SDMMC_IDINTEN_FBE_LSB 2
8384 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_FBE register field. */
8385 #define ALT_SDMMC_IDINTEN_FBE_MSB 2
8386 /* The width in bits of the ALT_SDMMC_IDINTEN_FBE register field. */
8387 #define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
8388 /* The mask used to set the ALT_SDMMC_IDINTEN_FBE register field value. */
8389 #define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
8390 /* The mask used to clear the ALT_SDMMC_IDINTEN_FBE register field value. */
8391 #define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
8392 /* The reset value of the ALT_SDMMC_IDINTEN_FBE register field. */
8393 #define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
8394 /* Extracts the ALT_SDMMC_IDINTEN_FBE field value from a register. */
8395 #define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
8396 /* Produces a ALT_SDMMC_IDINTEN_FBE register field value suitable for setting the register. */
8397 #define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
8398 
8399 /*
8400  * Field : Descriptor Unavailable Interrupt - du
8401  *
8402  * When set along with Abnormal Interrupt Summary Enable, the DU interrupt is
8403  * enabled.
8404  *
8405  * Field Enumeration Values:
8406  *
8407  * Enum | Value | Description
8408  * :----------------------------|:------|:---------------------------------------------
8409  * ALT_SDMMC_IDINTEN_DU_E_END | 0x1 | Descriptor Unavailable Interrupt is enabled
8410  * ALT_SDMMC_IDINTEN_DU_E_DISD | 0x0 | Descriptor Unavailable Interrupt is disabled
8411  *
8412  * Field Access Macros:
8413  *
8414  */
8415 /*
8416  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
8417  *
8418  * Descriptor Unavailable Interrupt is enabled
8419  */
8420 #define ALT_SDMMC_IDINTEN_DU_E_END 0x1
8421 /*
8422  * Enumerated value for register field ALT_SDMMC_IDINTEN_DU
8423  *
8424  * Descriptor Unavailable Interrupt is disabled
8425  */
8426 #define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
8427 
8428 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
8429 #define ALT_SDMMC_IDINTEN_DU_LSB 4
8430 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_DU register field. */
8431 #define ALT_SDMMC_IDINTEN_DU_MSB 4
8432 /* The width in bits of the ALT_SDMMC_IDINTEN_DU register field. */
8433 #define ALT_SDMMC_IDINTEN_DU_WIDTH 1
8434 /* The mask used to set the ALT_SDMMC_IDINTEN_DU register field value. */
8435 #define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
8436 /* The mask used to clear the ALT_SDMMC_IDINTEN_DU register field value. */
8437 #define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
8438 /* The reset value of the ALT_SDMMC_IDINTEN_DU register field. */
8439 #define ALT_SDMMC_IDINTEN_DU_RESET 0x0
8440 /* Extracts the ALT_SDMMC_IDINTEN_DU field value from a register. */
8441 #define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
8442 /* Produces a ALT_SDMMC_IDINTEN_DU register field value suitable for setting the register. */
8443 #define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
8444 
8445 /*
8446  * Field : Card Error Summary Interrupt Enable - ces
8447  *
8448  * Enable and disable Card Error Interrupt Summary
8449  *
8450  * Field Enumeration Values:
8451  *
8452  * Enum | Value | Description
8453  * :-----------------------------|:------|:-----------------------------------------
8454  * ALT_SDMMC_IDINTEN_CES_E_END | 0x1 | Card Error Summary Interrupt is enabled
8455  * ALT_SDMMC_IDINTEN_CES_E_DISD | 0x0 | Card Error Summary Interrupt is disabled
8456  *
8457  * Field Access Macros:
8458  *
8459  */
8460 /*
8461  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
8462  *
8463  * Card Error Summary Interrupt is enabled
8464  */
8465 #define ALT_SDMMC_IDINTEN_CES_E_END 0x1
8466 /*
8467  * Enumerated value for register field ALT_SDMMC_IDINTEN_CES
8468  *
8469  * Card Error Summary Interrupt is disabled
8470  */
8471 #define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
8472 
8473 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
8474 #define ALT_SDMMC_IDINTEN_CES_LSB 5
8475 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_CES register field. */
8476 #define ALT_SDMMC_IDINTEN_CES_MSB 5
8477 /* The width in bits of the ALT_SDMMC_IDINTEN_CES register field. */
8478 #define ALT_SDMMC_IDINTEN_CES_WIDTH 1
8479 /* The mask used to set the ALT_SDMMC_IDINTEN_CES register field value. */
8480 #define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
8481 /* The mask used to clear the ALT_SDMMC_IDINTEN_CES register field value. */
8482 #define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
8483 /* The reset value of the ALT_SDMMC_IDINTEN_CES register field. */
8484 #define ALT_SDMMC_IDINTEN_CES_RESET 0x0
8485 /* Extracts the ALT_SDMMC_IDINTEN_CES field value from a register. */
8486 #define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
8487 /* Produces a ALT_SDMMC_IDINTEN_CES register field value suitable for setting the register. */
8488 #define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
8489 
8490 /*
8491  * Field : Normal Interrupt Summary Enable - ni
8492  *
8493  * Enable and Disable Normal Interrupt Summary
8494  *
8495  * Field Enumeration Values:
8496  *
8497  * Enum | Value | Description
8498  * :----------------------------|:------|:-------------------------------------
8499  * ALT_SDMMC_IDINTEN_NI_E_END | 0x1 | Normal Interrupt Summary is enabled
8500  * ALT_SDMMC_IDINTEN_NI_E_DISD | 0x0 | Normal Interrupt Summary is disabled
8501  *
8502  * Field Access Macros:
8503  *
8504  */
8505 /*
8506  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
8507  *
8508  * Normal Interrupt Summary is enabled
8509  */
8510 #define ALT_SDMMC_IDINTEN_NI_E_END 0x1
8511 /*
8512  * Enumerated value for register field ALT_SDMMC_IDINTEN_NI
8513  *
8514  * Normal Interrupt Summary is disabled
8515  */
8516 #define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
8517 
8518 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
8519 #define ALT_SDMMC_IDINTEN_NI_LSB 8
8520 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_NI register field. */
8521 #define ALT_SDMMC_IDINTEN_NI_MSB 8
8522 /* The width in bits of the ALT_SDMMC_IDINTEN_NI register field. */
8523 #define ALT_SDMMC_IDINTEN_NI_WIDTH 1
8524 /* The mask used to set the ALT_SDMMC_IDINTEN_NI register field value. */
8525 #define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
8526 /* The mask used to clear the ALT_SDMMC_IDINTEN_NI register field value. */
8527 #define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
8528 /* The reset value of the ALT_SDMMC_IDINTEN_NI register field. */
8529 #define ALT_SDMMC_IDINTEN_NI_RESET 0x0
8530 /* Extracts the ALT_SDMMC_IDINTEN_NI field value from a register. */
8531 #define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
8532 /* Produces a ALT_SDMMC_IDINTEN_NI register field value suitable for setting the register. */
8533 #define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
8534 
8535 /*
8536  * Field : Abnormal Interrupt Summary Enable. - ai
8537  *
8538  * This bit enables the following bits:
8539  *
8540  * IDINTEN[2] - Fatal Bus Error Interrupt
8541  *
8542  * IDINTEN[4] - DU Interrupt
8543  *
8544  * IDINTEN[5] - Card Error Summary Interrupt
8545  *
8546  * Field Enumeration Values:
8547  *
8548  * Enum | Value | Description
8549  * :----------------------------|:------|:---------------------------------------
8550  * ALT_SDMMC_IDINTEN_AI_E_END | 0x1 | Abnormal Interrupt Summary is enabled
8551  * ALT_SDMMC_IDINTEN_AI_E_DISD | 0x0 | Abnormal Interrupt Summary is disabled
8552  *
8553  * Field Access Macros:
8554  *
8555  */
8556 /*
8557  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
8558  *
8559  * Abnormal Interrupt Summary is enabled
8560  */
8561 #define ALT_SDMMC_IDINTEN_AI_E_END 0x1
8562 /*
8563  * Enumerated value for register field ALT_SDMMC_IDINTEN_AI
8564  *
8565  * Abnormal Interrupt Summary is disabled
8566  */
8567 #define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
8568 
8569 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
8570 #define ALT_SDMMC_IDINTEN_AI_LSB 9
8571 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_AI register field. */
8572 #define ALT_SDMMC_IDINTEN_AI_MSB 9
8573 /* The width in bits of the ALT_SDMMC_IDINTEN_AI register field. */
8574 #define ALT_SDMMC_IDINTEN_AI_WIDTH 1
8575 /* The mask used to set the ALT_SDMMC_IDINTEN_AI register field value. */
8576 #define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
8577 /* The mask used to clear the ALT_SDMMC_IDINTEN_AI register field value. */
8578 #define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
8579 /* The reset value of the ALT_SDMMC_IDINTEN_AI register field. */
8580 #define ALT_SDMMC_IDINTEN_AI_RESET 0x0
8581 /* Extracts the ALT_SDMMC_IDINTEN_AI field value from a register. */
8582 #define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
8583 /* Produces a ALT_SDMMC_IDINTEN_AI register field value suitable for setting the register. */
8584 #define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
8585 
8586 #ifndef __ASSEMBLY__
8587 /*
8588  * WARNING: The C register and register group struct declarations are provided for
8589  * convenience and illustrative purposes. They should, however, be used with
8590  * caution as the C language standard provides no guarantees about the alignment or
8591  * atomicity of device memory accesses. The recommended practice for writing
8592  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8593  * alt_write_word() functions.
8594  *
8595  * The struct declaration for register ALT_SDMMC_IDINTEN.
8596  */
8597 struct ALT_SDMMC_IDINTEN_s
8598 {
8599  uint32_t ti : 1; /* Transmit Interrupt Enable */
8600  uint32_t ri : 1; /* Receive Interrupt Enable */
8601  uint32_t fbe : 1; /* Fatal Bus Error */
8602  uint32_t : 1; /* *UNDEFINED* */
8603  uint32_t du : 1; /* Descriptor Unavailable Interrupt */
8604  uint32_t ces : 1; /* Card Error Summary Interrupt Enable */
8605  uint32_t : 2; /* *UNDEFINED* */
8606  uint32_t ni : 1; /* Normal Interrupt Summary Enable */
8607  uint32_t ai : 1; /* Abnormal Interrupt Summary Enable. */
8608  uint32_t : 22; /* *UNDEFINED* */
8609 };
8610 
8611 /* The typedef declaration for register ALT_SDMMC_IDINTEN. */
8612 typedef volatile struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t;
8613 #endif /* __ASSEMBLY__ */
8614 
8615 /* The byte offset of the ALT_SDMMC_IDINTEN register from the beginning of the component. */
8616 #define ALT_SDMMC_IDINTEN_OFST 0x90
8617 
8618 /*
8619  * Register : Current Host Descriptor Address Register - dscaddr
8620  *
8621  * See Field Description.
8622  *
8623  * Register Layout
8624  *
8625  * Bits | Access | Reset | Description
8626  * :-------|:-------|:------|:-----------------------------------------
8627  * [31:0] | R | 0x0 | Current Host Descriptor Address Register
8628  *
8629  */
8630 /*
8631  * Field : Current Host Descriptor Address Register - hda
8632  *
8633  * Cleared on reset. Pointer updated by IDMAC during operation. This register
8634  * points to the start address of the current descriptor read by the IDMAC.
8635  *
8636  * Field Access Macros:
8637  *
8638  */
8639 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
8640 #define ALT_SDMMC_DSCADDR_HDA_LSB 0
8641 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DSCADDR_HDA register field. */
8642 #define ALT_SDMMC_DSCADDR_HDA_MSB 31
8643 /* The width in bits of the ALT_SDMMC_DSCADDR_HDA register field. */
8644 #define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
8645 /* The mask used to set the ALT_SDMMC_DSCADDR_HDA register field value. */
8646 #define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
8647 /* The mask used to clear the ALT_SDMMC_DSCADDR_HDA register field value. */
8648 #define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
8649 /* The reset value of the ALT_SDMMC_DSCADDR_HDA register field. */
8650 #define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
8651 /* Extracts the ALT_SDMMC_DSCADDR_HDA field value from a register. */
8652 #define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
8653 /* Produces a ALT_SDMMC_DSCADDR_HDA register field value suitable for setting the register. */
8654 #define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
8655 
8656 #ifndef __ASSEMBLY__
8657 /*
8658  * WARNING: The C register and register group struct declarations are provided for
8659  * convenience and illustrative purposes. They should, however, be used with
8660  * caution as the C language standard provides no guarantees about the alignment or
8661  * atomicity of device memory accesses. The recommended practice for writing
8662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8663  * alt_write_word() functions.
8664  *
8665  * The struct declaration for register ALT_SDMMC_DSCADDR.
8666  */
8667 struct ALT_SDMMC_DSCADDR_s
8668 {
8669  const uint32_t hda : 32; /* Current Host Descriptor Address Register */
8670 };
8671 
8672 /* The typedef declaration for register ALT_SDMMC_DSCADDR. */
8673 typedef volatile struct ALT_SDMMC_DSCADDR_s ALT_SDMMC_DSCADDR_t;
8674 #endif /* __ASSEMBLY__ */
8675 
8676 /* The byte offset of the ALT_SDMMC_DSCADDR register from the beginning of the component. */
8677 #define ALT_SDMMC_DSCADDR_OFST 0x94
8678 
8679 /*
8680  * Register : Current Buffer Descriptor Address Register - bufaddr
8681  *
8682  * See Field Description.
8683  *
8684  * Register Layout
8685  *
8686  * Bits | Access | Reset | Description
8687  * :-------|:-------|:------|:----------------------------
8688  * [31:0] | R | 0x0 | Host Buffer Address Pointer
8689  *
8690  */
8691 /*
8692  * Field : Host Buffer Address Pointer - hba
8693  *
8694  * Cleared on Reset. Pointer updated by IDMAC during operation. This register
8695  * points to the current Data Buffer Address being accessed by the IDMAC.
8696  *
8697  * Field Access Macros:
8698  *
8699  */
8700 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
8701 #define ALT_SDMMC_BUFADDR_HBA_LSB 0
8702 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BUFADDR_HBA register field. */
8703 #define ALT_SDMMC_BUFADDR_HBA_MSB 31
8704 /* The width in bits of the ALT_SDMMC_BUFADDR_HBA register field. */
8705 #define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
8706 /* The mask used to set the ALT_SDMMC_BUFADDR_HBA register field value. */
8707 #define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
8708 /* The mask used to clear the ALT_SDMMC_BUFADDR_HBA register field value. */
8709 #define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
8710 /* The reset value of the ALT_SDMMC_BUFADDR_HBA register field. */
8711 #define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
8712 /* Extracts the ALT_SDMMC_BUFADDR_HBA field value from a register. */
8713 #define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
8714 /* Produces a ALT_SDMMC_BUFADDR_HBA register field value suitable for setting the register. */
8715 #define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
8716 
8717 #ifndef __ASSEMBLY__
8718 /*
8719  * WARNING: The C register and register group struct declarations are provided for
8720  * convenience and illustrative purposes. They should, however, be used with
8721  * caution as the C language standard provides no guarantees about the alignment or
8722  * atomicity of device memory accesses. The recommended practice for writing
8723  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8724  * alt_write_word() functions.
8725  *
8726  * The struct declaration for register ALT_SDMMC_BUFADDR.
8727  */
8728 struct ALT_SDMMC_BUFADDR_s
8729 {
8730  const uint32_t hba : 32; /* Host Buffer Address Pointer */
8731 };
8732 
8733 /* The typedef declaration for register ALT_SDMMC_BUFADDR. */
8734 typedef volatile struct ALT_SDMMC_BUFADDR_s ALT_SDMMC_BUFADDR_t;
8735 #endif /* __ASSEMBLY__ */
8736 
8737 /* The byte offset of the ALT_SDMMC_BUFADDR register from the beginning of the component. */
8738 #define ALT_SDMMC_BUFADDR_OFST 0x98
8739 
8740 /*
8741  * Register : Card Threshold Control Register - cardthrctl
8742  *
8743  * See Field descriptions
8744  *
8745  * Register Layout
8746  *
8747  * Bits | Access | Reset | Description
8748  * :--------|:-------|:------|:---------------------------
8749  * [0] | RW | 0x0 | Card Read Threshold Enable
8750  * [15:1] | ??? | 0x0 | *UNDEFINED*
8751  * [27:16] | RW | 0x0 | Card Read Threshold
8752  * [31:28] | ??? | 0x0 | *UNDEFINED*
8753  *
8754  */
8755 /*
8756  * Field : Card Read Threshold Enable - cardrdthren
8757  *
8758  * Host Controller initiates Read Transfer only if CardRdThreshold amount of space
8759  * is available in receive FIFO.
8760  *
8761  * Field Enumeration Values:
8762  *
8763  * Enum | Value | Description
8764  * :----------------------------------------|:------|:--------------------------------
8765  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END | 0x1 | Card Read Threshold is enabled
8766  * ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD | 0x0 | Card Read Threshold is disabled
8767  *
8768  * Field Access Macros:
8769  *
8770  */
8771 /*
8772  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
8773  *
8774  * Card Read Threshold is enabled
8775  */
8776 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
8777 /*
8778  * Enumerated value for register field ALT_SDMMC_CARDTHRCTL_CARDRDTHREN
8779  *
8780  * Card Read Threshold is disabled
8781  */
8782 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
8783 
8784 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
8785 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
8786 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
8787 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
8788 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
8789 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
8790 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
8791 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
8792 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value. */
8793 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
8794 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field. */
8795 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
8796 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHREN field value from a register. */
8797 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
8798 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHREN register field value suitable for setting the register. */
8799 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
8800 
8801 /*
8802  * Field : Card Read Threshold - cardrdthreshold
8803  *
8804  * Card Read Threshold size
8805  *
8806  * Field Access Macros:
8807  *
8808  */
8809 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
8810 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
8811 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
8812 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 27
8813 /* The width in bits of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
8814 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 12
8815 /* The mask used to set the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
8816 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x0fff0000
8817 /* The mask used to clear the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value. */
8818 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xf000ffff
8819 /* The reset value of the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field. */
8820 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
8821 /* Extracts the ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD field value from a register. */
8822 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x0fff0000) >> 16)
8823 /* Produces a ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD register field value suitable for setting the register. */
8824 #define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x0fff0000)
8825 
8826 #ifndef __ASSEMBLY__
8827 /*
8828  * WARNING: The C register and register group struct declarations are provided for
8829  * convenience and illustrative purposes. They should, however, be used with
8830  * caution as the C language standard provides no guarantees about the alignment or
8831  * atomicity of device memory accesses. The recommended practice for writing
8832  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8833  * alt_write_word() functions.
8834  *
8835  * The struct declaration for register ALT_SDMMC_CARDTHRCTL.
8836  */
8837 struct ALT_SDMMC_CARDTHRCTL_s
8838 {
8839  uint32_t cardrdthren : 1; /* Card Read Threshold Enable */
8840  uint32_t : 15; /* *UNDEFINED* */
8841  uint32_t cardrdthreshold : 12; /* Card Read Threshold */
8842  uint32_t : 4; /* *UNDEFINED* */
8843 };
8844 
8845 /* The typedef declaration for register ALT_SDMMC_CARDTHRCTL. */
8846 typedef volatile struct ALT_SDMMC_CARDTHRCTL_s ALT_SDMMC_CARDTHRCTL_t;
8847 #endif /* __ASSEMBLY__ */
8848 
8849 /* The byte offset of the ALT_SDMMC_CARDTHRCTL register from the beginning of the component. */
8850 #define ALT_SDMMC_CARDTHRCTL_OFST 0x100
8851 
8852 /*
8853  * Register : Back End Power Register - back_end_power_r
8854  *
8855  * See Field Description
8856  *
8857  * Register Layout
8858  *
8859  * Bits | Access | Reset | Description
8860  * :--------|:-------|:------|:---------------
8861  * [15:0] | RW | 0x0 | Back End Power
8862  * [31:16] | ??? | 0x0 | *UNDEFINED*
8863  *
8864  */
8865 /*
8866  * Field : Back End Power - back_end_power
8867  *
8868  * Back end power operation.
8869  *
8870  * Field Enumeration Values:
8871  *
8872  * Enum | Value | Description
8873  * :-----------------------------------------------------|:------|:--------------------------------------------
8874  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 | 0x1 | Back-end Power supplied to card only 1 card
8875  * ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 | 0x0 | Off Reset
8876  *
8877  * Field Access Macros:
8878  *
8879  */
8880 /*
8881  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER
8882  *
8883  * Back-end Power supplied to card only 1 card
8884  */
8885 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
8886 /*
8887  * Enumerated value for register field ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER
8888  *
8889  * Off Reset
8890  */
8891 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
8892 
8893 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
8894 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
8895 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
8896 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
8897 /* The width in bits of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
8898 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
8899 /* The mask used to set the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */
8900 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
8901 /* The mask used to clear the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value. */
8902 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
8903 /* The reset value of the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field. */
8904 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
8905 /* Extracts the ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER field value from a register. */
8906 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
8907 /* Produces a ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER register field value suitable for setting the register. */
8908 #define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
8909 
8910 #ifndef __ASSEMBLY__
8911 /*
8912  * WARNING: The C register and register group struct declarations are provided for
8913  * convenience and illustrative purposes. They should, however, be used with
8914  * caution as the C language standard provides no guarantees about the alignment or
8915  * atomicity of device memory accesses. The recommended practice for writing
8916  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8917  * alt_write_word() functions.
8918  *
8919  * The struct declaration for register ALT_SDMMC_BACK_END_POWER_R.
8920  */
8921 struct ALT_SDMMC_BACK_END_POWER_R_s
8922 {
8923  uint32_t back_end_power : 16; /* Back End Power */
8924  uint32_t : 16; /* *UNDEFINED* */
8925 };
8926 
8927 /* The typedef declaration for register ALT_SDMMC_BACK_END_POWER_R. */
8928 typedef volatile struct ALT_SDMMC_BACK_END_POWER_R_s ALT_SDMMC_BACK_END_POWER_R_t;
8929 #endif /* __ASSEMBLY__ */
8930 
8931 /* The byte offset of the ALT_SDMMC_BACK_END_POWER_R register from the beginning of the component. */
8932 #define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
8933 
8934 /*
8935  * Register : Data FIFO Access - data
8936  *
8937  * Provides read/write access to data FIFO. Addresses 0x200 and above are mapped to
8938  * the data FIFO. More than one address is mapped to data FIFO so that FIFO can be
8939  * accessed using bursts.
8940  *
8941  * Register Layout
8942  *
8943  * Bits | Access | Reset | Description
8944  * :-------|:-------|:--------|:------------
8945  * [31:0] | RW | Unknown | FIFO Data
8946  *
8947  */
8948 /*
8949  * Field : FIFO Data - value
8950  *
8951  * Provides read/write access to data FIFO.
8952  *
8953  * Field Access Macros:
8954  *
8955  */
8956 /* The Least Significant Bit (LSB) position of the ALT_SDMMC_DATA_VALUE register field. */
8957 #define ALT_SDMMC_DATA_VALUE_LSB 0
8958 /* The Most Significant Bit (MSB) position of the ALT_SDMMC_DATA_VALUE register field. */
8959 #define ALT_SDMMC_DATA_VALUE_MSB 31
8960 /* The width in bits of the ALT_SDMMC_DATA_VALUE register field. */
8961 #define ALT_SDMMC_DATA_VALUE_WIDTH 32
8962 /* The mask used to set the ALT_SDMMC_DATA_VALUE register field value. */
8963 #define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
8964 /* The mask used to clear the ALT_SDMMC_DATA_VALUE register field value. */
8965 #define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
8966 /* The reset value of the ALT_SDMMC_DATA_VALUE register field is UNKNOWN. */
8967 #define ALT_SDMMC_DATA_VALUE_RESET 0x0
8968 /* Extracts the ALT_SDMMC_DATA_VALUE field value from a register. */
8969 #define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
8970 /* Produces a ALT_SDMMC_DATA_VALUE register field value suitable for setting the register. */
8971 #define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
8972 
8973 #ifndef __ASSEMBLY__
8974 /*
8975  * WARNING: The C register and register group struct declarations are provided for
8976  * convenience and illustrative purposes. They should, however, be used with
8977  * caution as the C language standard provides no guarantees about the alignment or
8978  * atomicity of device memory accesses. The recommended practice for writing
8979  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8980  * alt_write_word() functions.
8981  *
8982  * The struct declaration for register ALT_SDMMC_DATA.
8983  */
8984 struct ALT_SDMMC_DATA_s
8985 {
8986  uint32_t value : 32; /* FIFO Data */
8987 };
8988 
8989 /* The typedef declaration for register ALT_SDMMC_DATA. */
8990 typedef volatile struct ALT_SDMMC_DATA_s ALT_SDMMC_DATA_t;
8991 #endif /* __ASSEMBLY__ */
8992 
8993 /* The byte offset of the ALT_SDMMC_DATA register from the beginning of the component. */
8994 #define ALT_SDMMC_DATA_OFST 0x200
8995 
8996 #ifndef __ASSEMBLY__
8997 /*
8998  * WARNING: The C register and register group struct declarations are provided for
8999  * convenience and illustrative purposes. They should, however, be used with
9000  * caution as the C language standard provides no guarantees about the alignment or
9001  * atomicity of device memory accesses. The recommended practice for writing
9002  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9003  * alt_write_word() functions.
9004  *
9005  * The struct declaration for register group ALT_SDMMC.
9006  */
9007 struct ALT_SDMMC_s
9008 {
9009  ALT_SDMMC_CTL_t ctrl; /* ALT_SDMMC_CTL */
9010  ALT_SDMMC_PWREN_t pwren; /* ALT_SDMMC_PWREN */
9011  ALT_SDMMC_CLKDIV_t clkdiv; /* ALT_SDMMC_CLKDIV */
9012  ALT_SDMMC_CLKSRC_t clksrc; /* ALT_SDMMC_CLKSRC */
9013  ALT_SDMMC_CLKENA_t clkena; /* ALT_SDMMC_CLKENA */
9014  ALT_SDMMC_TMOUT_t tmout; /* ALT_SDMMC_TMOUT */
9015  ALT_SDMMC_CTYPE_t ctype; /* ALT_SDMMC_CTYPE */
9016  ALT_SDMMC_BLKSIZ_t blksiz; /* ALT_SDMMC_BLKSIZ */
9017  ALT_SDMMC_BYTCNT_t bytcnt; /* ALT_SDMMC_BYTCNT */
9018  ALT_SDMMC_INTMSK_t intmask; /* ALT_SDMMC_INTMSK */
9019  ALT_SDMMC_CMDARG_t cmdarg; /* ALT_SDMMC_CMDARG */
9020  ALT_SDMMC_CMD_t cmd; /* ALT_SDMMC_CMD */
9021  ALT_SDMMC_RESP0_t resp0; /* ALT_SDMMC_RESP0 */
9022  ALT_SDMMC_RESP1_t resp1; /* ALT_SDMMC_RESP1 */
9023  ALT_SDMMC_RESP2_t resp2; /* ALT_SDMMC_RESP2 */
9024  ALT_SDMMC_RESP3_t resp3; /* ALT_SDMMC_RESP3 */
9025  ALT_SDMMC_MINTSTS_t mintsts; /* ALT_SDMMC_MINTSTS */
9026  ALT_SDMMC_RINTSTS_t rintsts; /* ALT_SDMMC_RINTSTS */
9027  ALT_SDMMC_STAT_t status; /* ALT_SDMMC_STAT */
9028  ALT_SDMMC_FIFOTH_t fifoth; /* ALT_SDMMC_FIFOTH */
9029  ALT_SDMMC_CDETECT_t cdetect; /* ALT_SDMMC_CDETECT */
9030  ALT_SDMMC_WRTPRT_t wrtprt; /* ALT_SDMMC_WRTPRT */
9031  volatile uint32_t _pad_0x58_0x5b; /* *UNDEFINED* */
9032  ALT_SDMMC_TCBCNT_t tcbcnt; /* ALT_SDMMC_TCBCNT */
9033  ALT_SDMMC_TBBCNT_t tbbcnt; /* ALT_SDMMC_TBBCNT */
9034  ALT_SDMMC_DEBNCE_t debnce; /* ALT_SDMMC_DEBNCE */
9035  ALT_SDMMC_USRID_t usrid; /* ALT_SDMMC_USRID */
9036  ALT_SDMMC_VERID_t verid; /* ALT_SDMMC_VERID */
9037  ALT_SDMMC_HCON_t hcon; /* ALT_SDMMC_HCON */
9038  ALT_SDMMC_UHS_REG_t uhs_reg; /* ALT_SDMMC_UHS_REG */
9039  ALT_SDMMC_RST_N_t rst_n; /* ALT_SDMMC_RST_N */
9040  volatile uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
9041  ALT_SDMMC_BMOD_t bmod; /* ALT_SDMMC_BMOD */
9042  ALT_SDMMC_PLDMND_t pldmnd; /* ALT_SDMMC_PLDMND */
9043  ALT_SDMMC_DBADDR_t dbaddr; /* ALT_SDMMC_DBADDR */
9044  ALT_SDMMC_IDSTS_t idsts; /* ALT_SDMMC_IDSTS */
9045  ALT_SDMMC_IDINTEN_t idinten; /* ALT_SDMMC_IDINTEN */
9046  ALT_SDMMC_DSCADDR_t dscaddr; /* ALT_SDMMC_DSCADDR */
9047  ALT_SDMMC_BUFADDR_t bufaddr; /* ALT_SDMMC_BUFADDR */
9048  volatile uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
9049  ALT_SDMMC_CARDTHRCTL_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */
9050  ALT_SDMMC_BACK_END_POWER_R_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */
9051  volatile uint32_t _pad_0x108_0x1ff[62]; /* *UNDEFINED* */
9052  ALT_SDMMC_DATA_t data; /* ALT_SDMMC_DATA */
9053  volatile uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
9054 };
9055 
9056 /* The typedef declaration for register group ALT_SDMMC. */
9057 typedef volatile struct ALT_SDMMC_s ALT_SDMMC_t;
9058 /* The struct declaration for the raw register contents of register group ALT_SDMMC. */
9059 struct ALT_SDMMC_raw_s
9060 {
9061  volatile uint32_t ctrl; /* ALT_SDMMC_CTL */
9062  volatile uint32_t pwren; /* ALT_SDMMC_PWREN */
9063  volatile uint32_t clkdiv; /* ALT_SDMMC_CLKDIV */
9064  volatile uint32_t clksrc; /* ALT_SDMMC_CLKSRC */
9065  volatile uint32_t clkena; /* ALT_SDMMC_CLKENA */
9066  volatile uint32_t tmout; /* ALT_SDMMC_TMOUT */
9067  volatile uint32_t ctype; /* ALT_SDMMC_CTYPE */
9068  volatile uint32_t blksiz; /* ALT_SDMMC_BLKSIZ */
9069  volatile uint32_t bytcnt; /* ALT_SDMMC_BYTCNT */
9070  volatile uint32_t intmask; /* ALT_SDMMC_INTMSK */
9071  volatile uint32_t cmdarg; /* ALT_SDMMC_CMDARG */
9072  volatile uint32_t cmd; /* ALT_SDMMC_CMD */
9073  volatile uint32_t resp0; /* ALT_SDMMC_RESP0 */
9074  volatile uint32_t resp1; /* ALT_SDMMC_RESP1 */
9075  volatile uint32_t resp2; /* ALT_SDMMC_RESP2 */
9076  volatile uint32_t resp3; /* ALT_SDMMC_RESP3 */
9077  volatile uint32_t mintsts; /* ALT_SDMMC_MINTSTS */
9078  volatile uint32_t rintsts; /* ALT_SDMMC_RINTSTS */
9079  volatile uint32_t status; /* ALT_SDMMC_STAT */
9080  volatile uint32_t fifoth; /* ALT_SDMMC_FIFOTH */
9081  volatile uint32_t cdetect; /* ALT_SDMMC_CDETECT */
9082  volatile uint32_t wrtprt; /* ALT_SDMMC_WRTPRT */
9083  uint32_t _pad_0x58_0x5b; /* *UNDEFINED* */
9084  volatile uint32_t tcbcnt; /* ALT_SDMMC_TCBCNT */
9085  volatile uint32_t tbbcnt; /* ALT_SDMMC_TBBCNT */
9086  volatile uint32_t debnce; /* ALT_SDMMC_DEBNCE */
9087  volatile uint32_t usrid; /* ALT_SDMMC_USRID */
9088  volatile uint32_t verid; /* ALT_SDMMC_VERID */
9089  volatile uint32_t hcon; /* ALT_SDMMC_HCON */
9090  volatile uint32_t uhs_reg; /* ALT_SDMMC_UHS_REG */
9091  volatile uint32_t rst_n; /* ALT_SDMMC_RST_N */
9092  uint32_t _pad_0x7c_0x7f; /* *UNDEFINED* */
9093  volatile uint32_t bmod; /* ALT_SDMMC_BMOD */
9094  volatile uint32_t pldmnd; /* ALT_SDMMC_PLDMND */
9095  volatile uint32_t dbaddr; /* ALT_SDMMC_DBADDR */
9096  volatile uint32_t idsts; /* ALT_SDMMC_IDSTS */
9097  volatile uint32_t idinten; /* ALT_SDMMC_IDINTEN */
9098  volatile uint32_t dscaddr; /* ALT_SDMMC_DSCADDR */
9099  volatile uint32_t bufaddr; /* ALT_SDMMC_BUFADDR */
9100  uint32_t _pad_0x9c_0xff[25]; /* *UNDEFINED* */
9101  volatile uint32_t cardthrctl; /* ALT_SDMMC_CARDTHRCTL */
9102  volatile uint32_t back_end_power_r; /* ALT_SDMMC_BACK_END_POWER_R */
9103  uint32_t _pad_0x108_0x1ff[62]; /* *UNDEFINED* */
9104  volatile uint32_t data; /* ALT_SDMMC_DATA */
9105  uint32_t _pad_0x204_0x400[127]; /* *UNDEFINED* */
9106 };
9107 
9108 /* The typedef declaration for the raw register contents of register group ALT_SDMMC. */
9109 typedef volatile struct ALT_SDMMC_raw_s ALT_SDMMC_raw_t;
9110 #endif /* __ASSEMBLY__ */
9111 
9112 
9113 #ifdef __cplusplus
9114 }
9115 #endif /* __cplusplus */
9116 #endif /* __ALTERA_ALT_SDMMC_H__ */
9117