Hardware Libraries  20.1
Arria 10 SoC Hardware Manager
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alt_sysmgr.h
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32 
33 /* Altera - ALT_SYSMGR */
34 
35 #ifndef __ALTERA_ALT_SYSMGR_H__
36 #define __ALTERA_ALT_SYSMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
43 /*
44  * Component : System Manager Module - ALT_SYSMGR
45  * System Manager Module
46  *
47  * Registers in the System Manager module
48  *
49  */
50 /*
51  * Register : Silicon ID1 Register - siliconid1
52  *
53  * Specifies Silicon ID and revision number.
54  *
55  * Register Layout
56  *
57  * Bits | Access | Reset | Description
58  * :--------|:-------|:------|:-----------------
59  * [15:0] | R | 0x1 | Silicon Revision
60  * [31:16] | R | 0x0 | Silicon ID
61  *
62  */
63 /*
64  * Field : Silicon Revision - rev
65  *
66  * Silicon revision number.
67  *
68  * Field Enumeration Values:
69  *
70  * Enum | Value | Description
71  * :---------------------------------|:------|:------------
72  * ALT_SYSMGR_SILICONID1_REV_E_REV1 | 0x1 | Revision 1
73  *
74  * Field Access Macros:
75  *
76  */
77 /*
78  * Enumerated value for register field ALT_SYSMGR_SILICONID1_REV
79  *
80  * Revision 1
81  */
82 #define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1
83 
84 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
85 #define ALT_SYSMGR_SILICONID1_REV_LSB 0
86 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_REV register field. */
87 #define ALT_SYSMGR_SILICONID1_REV_MSB 15
88 /* The width in bits of the ALT_SYSMGR_SILICONID1_REV register field. */
89 #define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
90 /* The mask used to set the ALT_SYSMGR_SILICONID1_REV register field value. */
91 #define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
92 /* The mask used to clear the ALT_SYSMGR_SILICONID1_REV register field value. */
93 #define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
94 /* The reset value of the ALT_SYSMGR_SILICONID1_REV register field. */
95 #define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
96 /* Extracts the ALT_SYSMGR_SILICONID1_REV field value from a register. */
97 #define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
98 /* Produces a ALT_SYSMGR_SILICONID1_REV register field value suitable for setting the register. */
99 #define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
100 
101 /*
102  * Field : Silicon ID - id
103  *
104  * Silicon ID
105  *
106  * Field Enumeration Values:
107  *
108  * Enum | Value | Description
109  * :-------------------------------------------|:------|:----------------------------------------------
110  * ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV | 0x0 | HPS in Cyclone V and Arria V SoC FPGA devices
111  *
112  * Field Access Macros:
113  *
114  */
115 /*
116  * Enumerated value for register field ALT_SYSMGR_SILICONID1_ID
117  *
118  * HPS in Cyclone V and Arria V SoC FPGA devices
119  */
120 #define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0
121 
122 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
123 #define ALT_SYSMGR_SILICONID1_ID_LSB 16
124 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID1_ID register field. */
125 #define ALT_SYSMGR_SILICONID1_ID_MSB 31
126 /* The width in bits of the ALT_SYSMGR_SILICONID1_ID register field. */
127 #define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
128 /* The mask used to set the ALT_SYSMGR_SILICONID1_ID register field value. */
129 #define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
130 /* The mask used to clear the ALT_SYSMGR_SILICONID1_ID register field value. */
131 #define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
132 /* The reset value of the ALT_SYSMGR_SILICONID1_ID register field. */
133 #define ALT_SYSMGR_SILICONID1_ID_RESET 0x0
134 /* Extracts the ALT_SYSMGR_SILICONID1_ID field value from a register. */
135 #define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
136 /* Produces a ALT_SYSMGR_SILICONID1_ID register field value suitable for setting the register. */
137 #define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
138 
139 #ifndef __ASSEMBLY__
140 /*
141  * WARNING: The C register and register group struct declarations are provided for
142  * convenience and illustrative purposes. They should, however, be used with
143  * caution as the C language standard provides no guarantees about the alignment or
144  * atomicity of device memory accesses. The recommended practice for writing
145  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
146  * alt_write_word() functions.
147  *
148  * The struct declaration for register ALT_SYSMGR_SILICONID1.
149  */
150 struct ALT_SYSMGR_SILICONID1_s
151 {
152  const uint32_t rev : 16; /* Silicon Revision */
153  const uint32_t id : 16; /* Silicon ID */
154 };
155 
156 /* The typedef declaration for register ALT_SYSMGR_SILICONID1. */
157 typedef volatile struct ALT_SYSMGR_SILICONID1_s ALT_SYSMGR_SILICONID1_t;
158 #endif /* __ASSEMBLY__ */
159 
160 /* The byte offset of the ALT_SYSMGR_SILICONID1 register from the beginning of the component. */
161 #define ALT_SYSMGR_SILICONID1_OFST 0x0
162 
163 /*
164  * Register : Silicon ID2 Register - siliconid2
165  *
166  * Reserved for future use.
167  *
168  * Register Layout
169  *
170  * Bits | Access | Reset | Description
171  * :-------|:-------|:------|:------------
172  * [31:0] | R | 0x0 | Reserved
173  *
174  */
175 /*
176  * Field : Reserved - rsv
177  *
178  * Reserved for future use.
179  *
180  * Field Access Macros:
181  *
182  */
183 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
184 #define ALT_SYSMGR_SILICONID2_RSV_LSB 0
185 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SILICONID2_RSV register field. */
186 #define ALT_SYSMGR_SILICONID2_RSV_MSB 31
187 /* The width in bits of the ALT_SYSMGR_SILICONID2_RSV register field. */
188 #define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
189 /* The mask used to set the ALT_SYSMGR_SILICONID2_RSV register field value. */
190 #define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
191 /* The mask used to clear the ALT_SYSMGR_SILICONID2_RSV register field value. */
192 #define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
193 /* The reset value of the ALT_SYSMGR_SILICONID2_RSV register field. */
194 #define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
195 /* Extracts the ALT_SYSMGR_SILICONID2_RSV field value from a register. */
196 #define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
197 /* Produces a ALT_SYSMGR_SILICONID2_RSV register field value suitable for setting the register. */
198 #define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
199 
200 #ifndef __ASSEMBLY__
201 /*
202  * WARNING: The C register and register group struct declarations are provided for
203  * convenience and illustrative purposes. They should, however, be used with
204  * caution as the C language standard provides no guarantees about the alignment or
205  * atomicity of device memory accesses. The recommended practice for writing
206  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
207  * alt_write_word() functions.
208  *
209  * The struct declaration for register ALT_SYSMGR_SILICONID2.
210  */
211 struct ALT_SYSMGR_SILICONID2_s
212 {
213  const uint32_t rsv : 32; /* Reserved */
214 };
215 
216 /* The typedef declaration for register ALT_SYSMGR_SILICONID2. */
217 typedef volatile struct ALT_SYSMGR_SILICONID2_s ALT_SYSMGR_SILICONID2_t;
218 #endif /* __ASSEMBLY__ */
219 
220 /* The byte offset of the ALT_SYSMGR_SILICONID2 register from the beginning of the component. */
221 #define ALT_SYSMGR_SILICONID2_OFST 0x4
222 
223 /*
224  * Register : L4 Watchdog Debug Register - wddbg
225  *
226  * Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These
227  * control registers are used to drive the pause input signal of the L4 watchdogs.
228  * Note that the watchdogs built into the MPU automatically are paused when their
229  * associated CPU enters debug mode. Only reset by a cold reset.
230  *
231  * Register Layout
232  *
233  * Bits | Access | Reset | Description
234  * :-------|:-------|:------|:------------
235  * [1:0] | RW | 0x3 | Debug Mode
236  * [3:2] | RW | 0x3 | Debug Mode
237  * [31:4] | ??? | 0x0 | *UNDEFINED*
238  *
239  */
240 /*
241  * Field : Debug Mode - mode_0
242  *
243  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
244  * matches L4 watchdog index.
245  *
246  * Field Enumeration Values:
247  *
248  * Enum | Value | Description
249  * :-------------------------------------|:------|:-------------------------------------------------
250  * ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of
251  * : | | CPUs
252  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug
253  * : | | mode
254  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug
255  * : | | mode
256  * ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in
257  * : | | debug mode
258  *
259  * Field Access Macros:
260  *
261  */
262 /*
263  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
264  *
265  * Continue normal operation ignoring debug mode of CPUs
266  */
267 #define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
268 /*
269  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
270  *
271  * Pause normal operation only if CPU0 is in debug mode
272  */
273 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
274 /*
275  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
276  *
277  * Pause normal operation only if CPU1 is in debug mode
278  */
279 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
280 /*
281  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0
282  *
283  * Pause normal operation if CPU0 or CPU1 is in debug mode
284  */
285 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
286 
287 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
288 #define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
289 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
290 #define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
291 /* The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
292 #define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
293 /* The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
294 #define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
295 /* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value. */
296 #define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
297 /* The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field. */
298 #define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
299 /* Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register. */
300 #define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
301 /* Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register. */
302 #define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
303 
304 /*
305  * Field : Debug Mode - mode_1
306  *
307  * Controls behavior of L4 watchdog when CPUs in debug mode. Field array index
308  * matches L4 watchdog index.
309  *
310  * Field Enumeration Values:
311  *
312  * Enum | Value | Description
313  * :-------------------------------------|:------|:-------------------------------------------------
314  * ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE | 0x0 | Continue normal operation ignoring debug mode of
315  * : | | CPUs
316  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 | 0x1 | Pause normal operation only if CPU0 is in debug
317  * : | | mode
318  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 | 0x2 | Pause normal operation only if CPU1 is in debug
319  * : | | mode
320  * ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER | 0x3 | Pause normal operation if CPU0 or CPU1 is in
321  * : | | debug mode
322  *
323  * Field Access Macros:
324  *
325  */
326 /*
327  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
328  *
329  * Continue normal operation ignoring debug mode of CPUs
330  */
331 #define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
332 /*
333  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
334  *
335  * Pause normal operation only if CPU0 is in debug mode
336  */
337 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
338 /*
339  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
340  *
341  * Pause normal operation only if CPU1 is in debug mode
342  */
343 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
344 /*
345  * Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1
346  *
347  * Pause normal operation if CPU0 or CPU1 is in debug mode
348  */
349 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
350 
351 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
352 #define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
353 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
354 #define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
355 /* The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
356 #define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
357 /* The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
358 #define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
359 /* The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value. */
360 #define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
361 /* The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field. */
362 #define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
363 /* Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register. */
364 #define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
365 /* Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register. */
366 #define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
367 
368 #ifndef __ASSEMBLY__
369 /*
370  * WARNING: The C register and register group struct declarations are provided for
371  * convenience and illustrative purposes. They should, however, be used with
372  * caution as the C language standard provides no guarantees about the alignment or
373  * atomicity of device memory accesses. The recommended practice for writing
374  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
375  * alt_write_word() functions.
376  *
377  * The struct declaration for register ALT_SYSMGR_WDDBG.
378  */
379 struct ALT_SYSMGR_WDDBG_s
380 {
381  uint32_t mode_0 : 2; /* Debug Mode */
382  uint32_t mode_1 : 2; /* Debug Mode */
383  uint32_t : 28; /* *UNDEFINED* */
384 };
385 
386 /* The typedef declaration for register ALT_SYSMGR_WDDBG. */
387 typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
388 #endif /* __ASSEMBLY__ */
389 
390 /* The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component. */
391 #define ALT_SYSMGR_WDDBG_OFST 0x10
392 
393 /*
394  * Register : Boot Info Register - bootinfo
395  *
396  * Provides access to boot configuration information.
397  *
398  * Register Layout
399  *
400  * Bits | Access | Reset | Description
401  * :--------|:-------|:--------|:---------------------
402  * [2:0] | R | Unknown | Boot Select
403  * [4:3] | R | Unknown | Clock Select
404  * [7:5] | R | Unknown | HPS Pin Boot Select
405  * [9:8] | R | Unknown | HPS Pin Clock Select
406  * [31:10] | ??? | Unknown | *UNDEFINED*
407  *
408  */
409 /*
410  * Field : Boot Select - bsel
411  *
412  * The boot select field specifies the boot source. It is read by the Boot ROM code
413  * on a cold or warm reset to determine the boot source.
414  *
415  * The HPS BSEL pins value are sampled upon deassertion of cold reset.
416  *
417  * Field Enumeration Values:
418  *
419  * Enum | Value | Description
420  * :--------------------------------------------------------|:------|:-----------------------------------
421  * ALT_SYSMGR_BOOT_BSEL_E_RSVD | 0x0 | Reserved
422  * ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | FPGA (HPS2FPGA Bridge)
423  * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | NAND Flash (1.8v)
424  * ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | NAND Flash (3.0v)
425  * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | SD/MMC External Transceiver (1.8v)
426  * ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | SD/MMC Internal Transceiver (3.0v)
427  * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | QSPI Flash (1.8v)
428  * ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 | QSPI Flash (3.0v)
429  *
430  * Field Access Macros:
431  *
432  */
433 /*
434  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
435  *
436  * Reserved
437  */
438 #define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0
439 /*
440  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
441  *
442  * FPGA (HPS2FPGA Bridge)
443  */
444 #define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
445 /*
446  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
447  *
448  * NAND Flash (1.8v)
449  */
450 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
451 /*
452  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
453  *
454  * NAND Flash (3.0v)
455  */
456 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
457 /*
458  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
459  *
460  * SD/MMC External Transceiver (1.8v)
461  */
462 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
463 /*
464  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
465  *
466  * SD/MMC Internal Transceiver (3.0v)
467  */
468 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
469 /*
470  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
471  *
472  * QSPI Flash (1.8v)
473  */
474 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
475 /*
476  * Enumerated value for register field ALT_SYSMGR_BOOT_BSEL
477  *
478  * QSPI Flash (3.0v)
479  */
480 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
481 
482 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
483 #define ALT_SYSMGR_BOOT_BSEL_LSB 0
484 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field. */
485 #define ALT_SYSMGR_BOOT_BSEL_MSB 2
486 /* The width in bits of the ALT_SYSMGR_BOOT_BSEL register field. */
487 #define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
488 /* The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value. */
489 #define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007
490 /* The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value. */
491 #define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8
492 /* The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN. */
493 #define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
494 /* Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register. */
495 #define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0)
496 /* Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register. */
497 #define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007)
498 
499 /*
500  * Field : Clock Select - csel
501  *
502  * The clock select field specifies clock information for booting. The clock select
503  * encoding is a function of the CSEL value. The clock select field is read by the
504  * Boot ROM code on a cold or warm reset when booting from a flash device to get
505  * information about how to setup the HPS clocking to boot from the specified clock
506  * device.
507  *
508  * The encoding of the clock select field is specified by the enum associated with
509  * this field.
510  *
511  * The HPS CSEL pins value are sampled upon deassertion of cold reset.
512  *
513  * Field Enumeration Values:
514  *
515  * Enum | Value | Description
516  * :------------------------------|:------|:------------------------------------------------
517  * ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 | 0x0 | QSPI device clock is osc1_clk divided by 4,
518  * : | | SD/MMC device clock is osc1_clk divided by 4,
519  * : | | NAND device operation is osc1_clk divided by 25
520  * ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 | 0x1 | QSPI device clock is osc1_clk divided by 2,
521  * : | | SD/MMC device clock is osc1_clk divided by 1,
522  * : | | NAND device operation is osc1_clk multiplied by
523  * : | | 20/25
524  * ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 | 0x2 | QSPI device clock is osc1_clk divided by 1,
525  * : | | SD/MMC device clock is osc1_clk divided by 2,
526  * : | | NAND device operation is osc1_clk multiplied by
527  * : | | 10/25
528  * ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 | 0x3 | QSPI device clock is osc1_clk multiplied by 2,
529  * : | | SD/MMC device clock is osc1_clk divided by 4,
530  * : | | NAND device operation is osc1_clk multiplied by
531  * : | | 5/25
532  *
533  * Field Access Macros:
534  *
535  */
536 /*
537  * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
538  *
539  * QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk
540  * divided by 4, NAND device operation is osc1_clk divided by 25
541  */
542 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0
543 /*
544  * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
545  *
546  * QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk
547  * divided by 1, NAND device operation is osc1_clk multiplied by 20/25
548  */
549 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1
550 /*
551  * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
552  *
553  * QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk
554  * divided by 2, NAND device operation is osc1_clk multiplied by 10/25
555  */
556 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2
557 /*
558  * Enumerated value for register field ALT_SYSMGR_BOOT_CSEL
559  *
560  * QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk
561  * divided by 4, NAND device operation is osc1_clk multiplied by 5/25
562  */
563 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3
564 
565 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */
566 #define ALT_SYSMGR_BOOT_CSEL_LSB 3
567 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field. */
568 #define ALT_SYSMGR_BOOT_CSEL_MSB 4
569 /* The width in bits of the ALT_SYSMGR_BOOT_CSEL register field. */
570 #define ALT_SYSMGR_BOOT_CSEL_WIDTH 2
571 /* The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value. */
572 #define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018
573 /* The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value. */
574 #define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7
575 /* The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN. */
576 #define ALT_SYSMGR_BOOT_CSEL_RESET 0x0
577 /* Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register. */
578 #define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3)
579 /* Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register. */
580 #define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018)
581 
582 /*
583  * Field : HPS Pin Boot Select - pinbsel
584  *
585  * Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are
586  * sampled upon deassertion of cold reset.
587  *
588  * Field Access Macros:
589  *
590  */
591 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */
592 #define ALT_SYSMGR_BOOT_PINBSEL_LSB 5
593 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field. */
594 #define ALT_SYSMGR_BOOT_PINBSEL_MSB 7
595 /* The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field. */
596 #define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3
597 /* The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value. */
598 #define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0
599 /* The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value. */
600 #define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f
601 /* The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN. */
602 #define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0
603 /* Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register. */
604 #define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5)
605 /* Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register. */
606 #define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0)
607 
608 /*
609  * Field : HPS Pin Clock Select - pincsel
610  *
611  * Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are
612  * sampled upon deassertion of cold reset.
613  *
614  * Field Access Macros:
615  *
616  */
617 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */
618 #define ALT_SYSMGR_BOOT_PINCSEL_LSB 8
619 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field. */
620 #define ALT_SYSMGR_BOOT_PINCSEL_MSB 9
621 /* The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field. */
622 #define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2
623 /* The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value. */
624 #define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300
625 /* The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value. */
626 #define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff
627 /* The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN. */
628 #define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0
629 /* Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register. */
630 #define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8)
631 /* Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register. */
632 #define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300)
633 
634 #ifndef __ASSEMBLY__
635 /*
636  * WARNING: The C register and register group struct declarations are provided for
637  * convenience and illustrative purposes. They should, however, be used with
638  * caution as the C language standard provides no guarantees about the alignment or
639  * atomicity of device memory accesses. The recommended practice for writing
640  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
641  * alt_write_word() functions.
642  *
643  * The struct declaration for register ALT_SYSMGR_BOOT.
644  */
645 struct ALT_SYSMGR_BOOT_s
646 {
647  const uint32_t bsel : 3; /* Boot Select */
648  const uint32_t csel : 2; /* Clock Select */
649  const uint32_t pinbsel : 3; /* HPS Pin Boot Select */
650  const uint32_t pincsel : 2; /* HPS Pin Clock Select */
651  uint32_t : 22; /* *UNDEFINED* */
652 };
653 
654 /* The typedef declaration for register ALT_SYSMGR_BOOT. */
655 typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
656 #endif /* __ASSEMBLY__ */
657 
658 /* The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component. */
659 #define ALT_SYSMGR_BOOT_OFST 0x14
660 
661 /*
662  * Register : HPS Info Register - hpsinfo
663  *
664  * Provides information about the HPS capabilities.
665  *
666  * Register Layout
667  *
668  * Bits | Access | Reset | Description
669  * :-------|:-------|:--------|:------------
670  * [0] | R | Unknown | Dual Core
671  * [1] | R | Unknown | CAN
672  * [31:2] | ??? | 0x0 | *UNDEFINED*
673  *
674  */
675 /*
676  * Field : Dual Core - dualcore
677  *
678  * Indicates if CPU1 is available in MPU or not.
679  *
680  * Field Enumeration Values:
681  *
682  * Enum | Value | Description
683  * :-----------------------------------------|:------|:---------------------------------------------
684  * ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE | 0x0 | Not dual-core (only CPU0 available).
685  * ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE | 0x1 | Is dual-core (CPU0 and CPU1 both available).
686  *
687  * Field Access Macros:
688  *
689  */
690 /*
691  * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE
692  *
693  * Not dual-core (only CPU0 available).
694  */
695 #define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0
696 /*
697  * Enumerated value for register field ALT_SYSMGR_HPSINFO_DUALCORE
698  *
699  * Is dual-core (CPU0 and CPU1 both available).
700  */
701 #define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1
702 
703 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
704 #define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0
705 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
706 #define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0
707 /* The width in bits of the ALT_SYSMGR_HPSINFO_DUALCORE register field. */
708 #define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1
709 /* The mask used to set the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */
710 #define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001
711 /* The mask used to clear the ALT_SYSMGR_HPSINFO_DUALCORE register field value. */
712 #define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe
713 /* The reset value of the ALT_SYSMGR_HPSINFO_DUALCORE register field is UNKNOWN. */
714 #define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0
715 /* Extracts the ALT_SYSMGR_HPSINFO_DUALCORE field value from a register. */
716 #define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0)
717 /* Produces a ALT_SYSMGR_HPSINFO_DUALCORE register field value suitable for setting the register. */
718 #define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001)
719 
720 /*
721  * Field : CAN - can
722  *
723  * Indicates if CAN0 and CAN1 controllers are available or not.
724  *
725  * Field Enumeration Values:
726  *
727  * Enum | Value | Description
728  * :-----------------------------------------|:------|:---------------------------------
729  * ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE | 0x0 | CAN0 and CAN1 are not available.
730  * ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE | 0x1 | CAN0 and CAN1 are available.
731  *
732  * Field Access Macros:
733  *
734  */
735 /*
736  * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN
737  *
738  * CAN0 and CAN1 are not available.
739  */
740 #define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0
741 /*
742  * Enumerated value for register field ALT_SYSMGR_HPSINFO_CAN
743  *
744  * CAN0 and CAN1 are available.
745  */
746 #define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1
747 
748 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */
749 #define ALT_SYSMGR_HPSINFO_CAN_LSB 1
750 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_HPSINFO_CAN register field. */
751 #define ALT_SYSMGR_HPSINFO_CAN_MSB 1
752 /* The width in bits of the ALT_SYSMGR_HPSINFO_CAN register field. */
753 #define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1
754 /* The mask used to set the ALT_SYSMGR_HPSINFO_CAN register field value. */
755 #define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002
756 /* The mask used to clear the ALT_SYSMGR_HPSINFO_CAN register field value. */
757 #define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd
758 /* The reset value of the ALT_SYSMGR_HPSINFO_CAN register field is UNKNOWN. */
759 #define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0
760 /* Extracts the ALT_SYSMGR_HPSINFO_CAN field value from a register. */
761 #define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1)
762 /* Produces a ALT_SYSMGR_HPSINFO_CAN register field value suitable for setting the register. */
763 #define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002)
764 
765 #ifndef __ASSEMBLY__
766 /*
767  * WARNING: The C register and register group struct declarations are provided for
768  * convenience and illustrative purposes. They should, however, be used with
769  * caution as the C language standard provides no guarantees about the alignment or
770  * atomicity of device memory accesses. The recommended practice for writing
771  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
772  * alt_write_word() functions.
773  *
774  * The struct declaration for register ALT_SYSMGR_HPSINFO.
775  */
776 struct ALT_SYSMGR_HPSINFO_s
777 {
778  const uint32_t dualcore : 1; /* Dual Core */
779  const uint32_t can : 1; /* CAN */
780  uint32_t : 30; /* *UNDEFINED* */
781 };
782 
783 /* The typedef declaration for register ALT_SYSMGR_HPSINFO. */
784 typedef volatile struct ALT_SYSMGR_HPSINFO_s ALT_SYSMGR_HPSINFO_t;
785 #endif /* __ASSEMBLY__ */
786 
787 /* The byte offset of the ALT_SYSMGR_HPSINFO register from the beginning of the component. */
788 #define ALT_SYSMGR_HPSINFO_OFST 0x18
789 
790 /*
791  * Register : Parity Fail Injection Register - parityinj
792  *
793  * Inject parity failures into the parity-protected RAMs in the MPU. Allows
794  * software to test the parity failure interrupt handler. The field array index
795  * corresponds to the CPU index.
796  *
797  * All fields are reset by a cold or warm reset.
798  *
799  * Register Layout
800  *
801  * Bits | Access | Reset | Description
802  * :--------|:-------|:------|:-----------------------------------------------------
803  * [0] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM
804  * [1] | RW | 0x0 | Parity Fail Injection for Data Cache Data RAM
805  * [2] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM
806  * [3] | RW | 0x0 | Parity Fail Injection for Data Cache Tag RAM
807  * [4] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM
808  * [5] | RW | 0x0 | Parity Fail Injection for Data Cache Outer RAM
809  * [6] | RW | 0x0 | Parity Fail Injection for Main TLB RAM
810  * [7] | RW | 0x0 | Parity Fail Injection for Main TLB RAM
811  * [8] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM
812  * [9] | RW | 0x0 | Parity Fail Injection for Instruction Cache Data RAM
813  * [10] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM
814  * [11] | RW | 0x0 | Parity Fail Injection for Instruction Cache Tag RAM
815  * [12] | RW | 0x0 | Parity Fail Injection for GHB RAM
816  * [13] | RW | 0x0 | Parity Fail Injection for GHB RAM
817  * [14] | RW | 0x0 | Parity Fail Injection for BTAC RAM
818  * [15] | RW | 0x0 | Parity Fail Injection for BTAC RAM
819  * [31:16] | ??? | 0x0 | *UNDEFINED*
820  *
821  */
822 /*
823  * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_0
824  *
825  * If 1, injecting parity error to Data Cache Data RAM.The field array index
826  * corresponds to the CPU index.
827  *
828  * Field Access Macros:
829  *
830  */
831 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
832 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0
833 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
834 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0
835 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
836 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1
837 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */
838 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001
839 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value. */
840 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe
841 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_0 register field. */
842 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0
843 /* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_0 field value from a register. */
844 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0)
845 /* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_0 register field value suitable for setting the register. */
846 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001)
847 
848 /*
849  * Field : Parity Fail Injection for Data Cache Data RAM - dcdata_1
850  *
851  * If 1, injecting parity error to Data Cache Data RAM.The field array index
852  * corresponds to the CPU index.
853  *
854  * Field Access Macros:
855  *
856  */
857 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
858 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1
859 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
860 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1
861 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
862 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1
863 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */
864 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002
865 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value. */
866 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd
867 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCDATA_1 register field. */
868 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0
869 /* Extracts the ALT_SYSMGR_PARITYINJ_DCDATA_1 field value from a register. */
870 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1)
871 /* Produces a ALT_SYSMGR_PARITYINJ_DCDATA_1 register field value suitable for setting the register. */
872 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002)
873 
874 /*
875  * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_0
876  *
877  * If 1, injecting parity error to Data Cache Tag RAM.The field array index
878  * corresponds to the CPU index.
879  *
880  * Field Access Macros:
881  *
882  */
883 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
884 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2
885 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
886 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2
887 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
888 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1
889 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */
890 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004
891 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value. */
892 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb
893 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_0 register field. */
894 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0
895 /* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_0 field value from a register. */
896 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2)
897 /* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_0 register field value suitable for setting the register. */
898 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004)
899 
900 /*
901  * Field : Parity Fail Injection for Data Cache Tag RAM - dctag_1
902  *
903  * If 1, injecting parity error to Data Cache Tag RAM.The field array index
904  * corresponds to the CPU index.
905  *
906  * Field Access Macros:
907  *
908  */
909 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
910 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3
911 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
912 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3
913 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
914 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1
915 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */
916 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008
917 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value. */
918 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7
919 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCTAG_1 register field. */
920 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0
921 /* Extracts the ALT_SYSMGR_PARITYINJ_DCTAG_1 field value from a register. */
922 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3)
923 /* Produces a ALT_SYSMGR_PARITYINJ_DCTAG_1 register field value suitable for setting the register. */
924 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008)
925 
926 /*
927  * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_0
928  *
929  * If 1, injecting parity error to Data Cache Outer RAM.The field array index
930  * corresponds to the CPU index.
931  *
932  * Field Access Macros:
933  *
934  */
935 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
936 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4
937 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
938 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4
939 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
940 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1
941 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */
942 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010
943 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value. */
944 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef
945 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field. */
946 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0
947 /* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_0 field value from a register. */
948 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4)
949 /* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_0 register field value suitable for setting the register. */
950 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010)
951 
952 /*
953  * Field : Parity Fail Injection for Data Cache Outer RAM - dcouter_1
954  *
955  * If 1, injecting parity error to Data Cache Outer RAM.The field array index
956  * corresponds to the CPU index.
957  *
958  * Field Access Macros:
959  *
960  */
961 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
962 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5
963 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
964 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5
965 /* The width in bits of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
966 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1
967 /* The mask used to set the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */
968 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020
969 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value. */
970 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf
971 /* The reset value of the ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field. */
972 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0
973 /* Extracts the ALT_SYSMGR_PARITYINJ_DCOUTER_1 field value from a register. */
974 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5)
975 /* Produces a ALT_SYSMGR_PARITYINJ_DCOUTER_1 register field value suitable for setting the register. */
976 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020)
977 
978 /*
979  * Field : Parity Fail Injection for Main TLB RAM - maintlb_0
980  *
981  * If 1, injecting parity error to Main TLB RAM.The field array index corresponds
982  * to the CPU index.
983  *
984  * Field Access Macros:
985  *
986  */
987 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
988 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6
989 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
990 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6
991 /* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
992 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1
993 /* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */
994 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040
995 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value. */
996 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf
997 /* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field. */
998 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0
999 /* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_0 field value from a register. */
1000 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6)
1001 /* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_0 register field value suitable for setting the register. */
1002 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040)
1003 
1004 /*
1005  * Field : Parity Fail Injection for Main TLB RAM - maintlb_1
1006  *
1007  * If 1, injecting parity error to Main TLB RAM.The field array index corresponds
1008  * to the CPU index.
1009  *
1010  * Field Access Macros:
1011  *
1012  */
1013 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1014 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7
1015 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1016 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7
1017 /* The width in bits of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1018 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1
1019 /* The mask used to set the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */
1020 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080
1021 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value. */
1022 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f
1023 /* The reset value of the ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field. */
1024 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0
1025 /* Extracts the ALT_SYSMGR_PARITYINJ_MAINTLB_1 field value from a register. */
1026 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7)
1027 /* Produces a ALT_SYSMGR_PARITYINJ_MAINTLB_1 register field value suitable for setting the register. */
1028 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080)
1029 
1030 /*
1031  * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_0
1032  *
1033  * If 1, injecting parity error to Instruction Cache Data RAM.The field array index
1034  * corresponds to the CPU index.
1035  *
1036  * Field Access Macros:
1037  *
1038  */
1039 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1040 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8
1041 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1042 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8
1043 /* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1044 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1
1045 /* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */
1046 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100
1047 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value. */
1048 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff
1049 /* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_0 register field. */
1050 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0
1051 /* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_0 field value from a register. */
1052 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8)
1053 /* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_0 register field value suitable for setting the register. */
1054 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100)
1055 
1056 /*
1057  * Field : Parity Fail Injection for Instruction Cache Data RAM - icdata_1
1058  *
1059  * If 1, injecting parity error to Instruction Cache Data RAM.The field array index
1060  * corresponds to the CPU index.
1061  *
1062  * Field Access Macros:
1063  *
1064  */
1065 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1066 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9
1067 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1068 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9
1069 /* The width in bits of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1070 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1
1071 /* The mask used to set the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */
1072 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200
1073 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value. */
1074 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff
1075 /* The reset value of the ALT_SYSMGR_PARITYINJ_ICDATA_1 register field. */
1076 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0
1077 /* Extracts the ALT_SYSMGR_PARITYINJ_ICDATA_1 field value from a register. */
1078 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9)
1079 /* Produces a ALT_SYSMGR_PARITYINJ_ICDATA_1 register field value suitable for setting the register. */
1080 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200)
1081 
1082 /*
1083  * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_0
1084  *
1085  * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index
1086  * corresponds to the CPU index.
1087  *
1088  * Field Access Macros:
1089  *
1090  */
1091 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1092 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10
1093 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1094 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10
1095 /* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1096 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1
1097 /* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */
1098 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400
1099 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value. */
1100 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff
1101 /* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_0 register field. */
1102 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0
1103 /* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_0 field value from a register. */
1104 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10)
1105 /* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_0 register field value suitable for setting the register. */
1106 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400)
1107 
1108 /*
1109  * Field : Parity Fail Injection for Instruction Cache Tag RAM - ictag_1
1110  *
1111  * If 1, injecting parity error to Instruction Cache Tag RAM.The field array index
1112  * corresponds to the CPU index.
1113  *
1114  * Field Access Macros:
1115  *
1116  */
1117 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1118 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11
1119 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1120 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11
1121 /* The width in bits of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1122 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1
1123 /* The mask used to set the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */
1124 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800
1125 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value. */
1126 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff
1127 /* The reset value of the ALT_SYSMGR_PARITYINJ_ICTAG_1 register field. */
1128 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0
1129 /* Extracts the ALT_SYSMGR_PARITYINJ_ICTAG_1 field value from a register. */
1130 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11)
1131 /* Produces a ALT_SYSMGR_PARITYINJ_ICTAG_1 register field value suitable for setting the register. */
1132 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800)
1133 
1134 /*
1135  * Field : Parity Fail Injection for GHB RAM - ghb_0
1136  *
1137  * If 1, injecting parity error to GHB RAM.The field array index corresponds to the
1138  * CPU index.
1139  *
1140  * Field Access Macros:
1141  *
1142  */
1143 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1144 #define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12
1145 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1146 #define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12
1147 /* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1148 #define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1
1149 /* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */
1150 #define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000
1151 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_0 register field value. */
1152 #define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff
1153 /* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_0 register field. */
1154 #define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0
1155 /* Extracts the ALT_SYSMGR_PARITYINJ_GHB_0 field value from a register. */
1156 #define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12)
1157 /* Produces a ALT_SYSMGR_PARITYINJ_GHB_0 register field value suitable for setting the register. */
1158 #define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000)
1159 
1160 /*
1161  * Field : Parity Fail Injection for GHB RAM - ghb_1
1162  *
1163  * If 1, injecting parity error to GHB RAM.The field array index corresponds to the
1164  * CPU index.
1165  *
1166  * Field Access Macros:
1167  *
1168  */
1169 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1170 #define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13
1171 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1172 #define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13
1173 /* The width in bits of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1174 #define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1
1175 /* The mask used to set the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */
1176 #define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000
1177 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_GHB_1 register field value. */
1178 #define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff
1179 /* The reset value of the ALT_SYSMGR_PARITYINJ_GHB_1 register field. */
1180 #define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0
1181 /* Extracts the ALT_SYSMGR_PARITYINJ_GHB_1 field value from a register. */
1182 #define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13)
1183 /* Produces a ALT_SYSMGR_PARITYINJ_GHB_1 register field value suitable for setting the register. */
1184 #define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000)
1185 
1186 /*
1187  * Field : Parity Fail Injection for BTAC RAM - btac_0
1188  *
1189  * If 1, injecting parity error to BTAC RAM.The field array index corresponds to
1190  * the CPU index.
1191  *
1192  * Field Access Macros:
1193  *
1194  */
1195 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1196 #define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14
1197 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1198 #define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14
1199 /* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1200 #define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1
1201 /* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */
1202 #define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000
1203 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_0 register field value. */
1204 #define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff
1205 /* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_0 register field. */
1206 #define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0
1207 /* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_0 field value from a register. */
1208 #define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14)
1209 /* Produces a ALT_SYSMGR_PARITYINJ_BTAC_0 register field value suitable for setting the register. */
1210 #define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000)
1211 
1212 /*
1213  * Field : Parity Fail Injection for BTAC RAM - btac_1
1214  *
1215  * If 1, injecting parity error to BTAC RAM.The field array index corresponds to
1216  * the CPU index.
1217  *
1218  * Field Access Macros:
1219  *
1220  */
1221 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1222 #define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15
1223 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1224 #define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15
1225 /* The width in bits of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1226 #define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1
1227 /* The mask used to set the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */
1228 #define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000
1229 /* The mask used to clear the ALT_SYSMGR_PARITYINJ_BTAC_1 register field value. */
1230 #define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff
1231 /* The reset value of the ALT_SYSMGR_PARITYINJ_BTAC_1 register field. */
1232 #define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0
1233 /* Extracts the ALT_SYSMGR_PARITYINJ_BTAC_1 field value from a register. */
1234 #define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15)
1235 /* Produces a ALT_SYSMGR_PARITYINJ_BTAC_1 register field value suitable for setting the register. */
1236 #define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000)
1237 
1238 #ifndef __ASSEMBLY__
1239 /*
1240  * WARNING: The C register and register group struct declarations are provided for
1241  * convenience and illustrative purposes. They should, however, be used with
1242  * caution as the C language standard provides no guarantees about the alignment or
1243  * atomicity of device memory accesses. The recommended practice for writing
1244  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1245  * alt_write_word() functions.
1246  *
1247  * The struct declaration for register ALT_SYSMGR_PARITYINJ.
1248  */
1249 struct ALT_SYSMGR_PARITYINJ_s
1250 {
1251  uint32_t dcdata_0 : 1; /* Parity Fail Injection for Data Cache Data RAM */
1252  uint32_t dcdata_1 : 1; /* Parity Fail Injection for Data Cache Data RAM */
1253  uint32_t dctag_0 : 1; /* Parity Fail Injection for Data Cache Tag RAM */
1254  uint32_t dctag_1 : 1; /* Parity Fail Injection for Data Cache Tag RAM */
1255  uint32_t dcouter_0 : 1; /* Parity Fail Injection for Data Cache Outer RAM */
1256  uint32_t dcouter_1 : 1; /* Parity Fail Injection for Data Cache Outer RAM */
1257  uint32_t maintlb_0 : 1; /* Parity Fail Injection for Main TLB RAM */
1258  uint32_t maintlb_1 : 1; /* Parity Fail Injection for Main TLB RAM */
1259  uint32_t icdata_0 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */
1260  uint32_t icdata_1 : 1; /* Parity Fail Injection for Instruction Cache Data RAM */
1261  uint32_t ictag_0 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */
1262  uint32_t ictag_1 : 1; /* Parity Fail Injection for Instruction Cache Tag RAM */
1263  uint32_t ghb_0 : 1; /* Parity Fail Injection for GHB RAM */
1264  uint32_t ghb_1 : 1; /* Parity Fail Injection for GHB RAM */
1265  uint32_t btac_0 : 1; /* Parity Fail Injection for BTAC RAM */
1266  uint32_t btac_1 : 1; /* Parity Fail Injection for BTAC RAM */
1267  uint32_t : 16; /* *UNDEFINED* */
1268 };
1269 
1270 /* The typedef declaration for register ALT_SYSMGR_PARITYINJ. */
1271 typedef volatile struct ALT_SYSMGR_PARITYINJ_s ALT_SYSMGR_PARITYINJ_t;
1272 #endif /* __ASSEMBLY__ */
1273 
1274 /* The byte offset of the ALT_SYSMGR_PARITYINJ register from the beginning of the component. */
1275 #define ALT_SYSMGR_PARITYINJ_OFST 0x1c
1276 
1277 /*
1278  * Register Group : FPGA Interface Group - ALT_SYSMGR_FPGAINTF
1279  * FPGA Interface Group
1280  *
1281  * Registers used to enable/disable interfaces between the FPGA and HPS. Required
1282  * for either of the following situations:[list][*]Interfaces that cannot be
1283  * disabled by putting an HPS module associated with the interface into
1284  * reset.[*]HPS modules that accept signals from the FPGA fabric and those signals
1285  * might interfere with the normal operation of the module.[/list].
1286  *
1287  * All registers are only reset by a cold reset (ignore warm reset).
1288  *
1289  */
1290 /*
1291  * Register : Global Disable Register - gbl
1292  *
1293  * Used to disable all interfaces between the FPGA and HPS.
1294  *
1295  * Register Layout
1296  *
1297  * Bits | Access | Reset | Description
1298  * :-------|:-------|:------|:-----------------
1299  * [0] | RW | 0x1 | Global Interface
1300  * [31:1] | ??? | 0x0 | *UNDEFINED*
1301  *
1302  */
1303 /*
1304  * Field : Global Interface - intf
1305  *
1306  * Used to disable all interfaces between the FPGA and HPS. Software must ensure
1307  * that all interfaces between the FPGA and HPS are inactive before disabling them.
1308  *
1309  * Field Enumeration Values:
1310  *
1311  * Enum | Value | Description
1312  * :-----------------------------------|:------|:-------------------------------------------------
1313  * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS | 0x0 | All interfaces between FPGA and HPS are
1314  * : | | disabled.
1315  * ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN | 0x1 | Interfaces between FPGA and HPS are not all
1316  * : | | disabled. Interfaces can be indivdually disabled
1317  * : | | by putting the HPS module associated with the
1318  * : | | interface in reset using registers in the Reset
1319  * : | | Manager or by using registers in this register
1320  * : | | group of the System Manager for interfaces
1321  * : | | without an associated module.
1322  *
1323  * Field Access Macros:
1324  *
1325  */
1326 /*
1327  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF
1328  *
1329  * All interfaces between FPGA and HPS are disabled.
1330  */
1331 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0
1332 /*
1333  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF
1334  *
1335  * Interfaces between FPGA and HPS are not all disabled. Interfaces can be
1336  * indivdually disabled by putting the HPS module associated with the interface in
1337  * reset using registers in the Reset Manager or by using registers in this
1338  * register group of the System Manager for interfaces without an associated
1339  * module.
1340  */
1341 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1
1342 
1343 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1344 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0
1345 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1346 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0
1347 /* The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1348 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1
1349 /* The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */
1350 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001
1351 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value. */
1352 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe
1353 /* The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field. */
1354 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1
1355 /* Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register. */
1356 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0)
1357 /* Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register. */
1358 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001)
1359 
1360 #ifndef __ASSEMBLY__
1361 /*
1362  * WARNING: The C register and register group struct declarations are provided for
1363  * convenience and illustrative purposes. They should, however, be used with
1364  * caution as the C language standard provides no guarantees about the alignment or
1365  * atomicity of device memory accesses. The recommended practice for writing
1366  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1367  * alt_write_word() functions.
1368  *
1369  * The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL.
1370  */
1371 struct ALT_SYSMGR_FPGAINTF_GBL_s
1372 {
1373  uint32_t intf : 1; /* Global Interface */
1374  uint32_t : 31; /* *UNDEFINED* */
1375 };
1376 
1377 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL. */
1378 typedef volatile struct ALT_SYSMGR_FPGAINTF_GBL_s ALT_SYSMGR_FPGAINTF_GBL_t;
1379 #endif /* __ASSEMBLY__ */
1380 
1381 /* The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component. */
1382 #define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0
1383 
1384 /*
1385  * Register : Individual Disable Register - indiv
1386  *
1387  * Used to disable individual interfaces between the FPGA and HPS.
1388  *
1389  * Register Layout
1390  *
1391  * Bits | Access | Reset | Description
1392  * :-------|:-------|:------|:------------------------------
1393  * [0] | RW | 0x1 | Reset Request Interface
1394  * [1] | RW | 0x1 | JTAG Enable Interface
1395  * [2] | RW | 0x1 | CONFIG_IO Interface
1396  * [3] | RW | 0x1 | Boundary-Scan Interface
1397  * [4] | RW | 0x1 | Trace Interface
1398  * [5] | ??? | 0x1 | *UNDEFINED*
1399  * [6] | RW | 0x1 | STM Event Interface
1400  * [7] | RW | 0x1 | Cross Trigger Interface (CTI)
1401  * [31:8] | ??? | 0x0 | *UNDEFINED*
1402  *
1403  */
1404 /*
1405  * Field : Reset Request Interface - rstreqintf
1406  *
1407  * Used to disable the reset request interface. This interface allows logic in the
1408  * FPGA fabric to request HPS resets. This field disables the following reset
1409  * request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n -
1410  * Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of
1411  * the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list]
1412  *
1413  * Field Enumeration Values:
1414  *
1415  * Enum | Value | Description
1416  * :-------------------------------------------|:------|:-------------------------------------------------
1417  * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS | 0x0 | Reset request interface is disabled. Logic in
1418  * : | | the FPGA fabric cannot reset the HPS.
1419  * ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN | 0x1 | Reset request interface is enabled. Logic in the
1420  * : | | FPGA fabric can reset the HPS.
1421  *
1422  * Field Access Macros:
1423  *
1424  */
1425 /*
1426  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF
1427  *
1428  * Reset request interface is disabled. Logic in the FPGA fabric cannot reset the
1429  * HPS.
1430  */
1431 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0
1432 /*
1433  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF
1434  *
1435  * Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS.
1436  */
1437 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1
1438 
1439 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1440 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0
1441 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1442 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0
1443 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1444 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1
1445 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */
1446 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001
1447 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value. */
1448 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe
1449 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field. */
1450 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1
1451 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register. */
1452 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0)
1453 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register. */
1454 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001)
1455 
1456 /*
1457  * Field : JTAG Enable Interface - jtagenintf
1458  *
1459  * Used to disable the JTAG enable interface. This interface allows logic in the
1460  * FPGA fabric to disable the HPS JTAG operation.
1461  *
1462  * Field Enumeration Values:
1463  *
1464  * Enum | Value | Description
1465  * :-------------------------------------------|:------|:------------------------------------------------
1466  * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS | 0x0 | JTAG enable interface is disabled. Logic in the
1467  * : | | FPGA fabric cannot disable the HPS JTAG.
1468  * ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN | 0x1 | JTAG enable interface is enabled. Logic in the
1469  * : | | FPGA fabric can disable the HPS JTAG.
1470  *
1471  * Field Access Macros:
1472  *
1473  */
1474 /*
1475  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF
1476  *
1477  * JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the
1478  * HPS JTAG.
1479  */
1480 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0
1481 /*
1482  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF
1483  *
1484  * JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS
1485  * JTAG.
1486  */
1487 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1
1488 
1489 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1490 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1
1491 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1492 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1
1493 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1494 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1
1495 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */
1496 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002
1497 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value. */
1498 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd
1499 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field. */
1500 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1
1501 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register. */
1502 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1)
1503 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register. */
1504 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002)
1505 
1506 /*
1507  * Field : CONFIG_IO Interface - configiointf
1508  *
1509  * Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP
1510  * controller to execute the CONFIG_IO instruction and configure all device I/Os
1511  * (FPGA and HPS). This is typically done before executing boundary-scan
1512  * instructions. The CONFIG_IO interface must be enabled before attempting to send
1513  * the CONFIG_IO instruction to the FPGA JTAG TAP controller.
1514  *
1515  * Field Enumeration Values:
1516  *
1517  * Enum | Value | Description
1518  * :------------------------------------------|:------|:-------------------------------------------------
1519  * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS | 0x0 | CONFIG_IO interface is disabled. Execution of
1520  * : | | the CONFIG_IO instruction in the FPGA JTAG TAP
1521  * : | | controller is unsupported and produces undefined
1522  * : | | results.
1523  * ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN | 0x1 | CONFIG_IO interface is enabled. Execution of the
1524  * : | | CONFIG_IO instruction in the FPGA JTAG TAP
1525  * : | | controller is supported.
1526  *
1527  * Field Access Macros:
1528  *
1529  */
1530 /*
1531  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF
1532  *
1533  * CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the
1534  * FPGA JTAG TAP controller is unsupported and produces undefined results.
1535  */
1536 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0
1537 /*
1538  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF
1539  *
1540  * CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the
1541  * FPGA JTAG TAP controller is supported.
1542  */
1543 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1
1544 
1545 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1546 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2
1547 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1548 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2
1549 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1550 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1
1551 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */
1552 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004
1553 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value. */
1554 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb
1555 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field. */
1556 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1
1557 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register. */
1558 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2)
1559 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register. */
1560 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004)
1561 
1562 /*
1563  * Field : Boundary-Scan Interface - bscanintf
1564  *
1565  * Used to disable the boundary-scan interface. This interface allows the FPGA JTAG
1566  * TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD,
1567  * EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting
1568  * to send the boundary-scan instructions to the FPGA JTAG TAP controller.
1569  *
1570  * Field Enumeration Values:
1571  *
1572  * Enum | Value | Description
1573  * :------------------------------------------|:------|:-------------------------------------------------
1574  * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS | 0x0 | Boundary-scan interface is disabled. Execution
1575  * : | | of boundary-scan instructions in the FPGA JTAG
1576  * : | | TAP controller is unsupported and produces
1577  * : | | undefined results.
1578  * ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN | 0x1 | Boundary-scan interface is enabled. Execution of
1579  * : | | the boundary-scan instructions in the FPGA JTAG
1580  * : | | TAP controller is supported.
1581  *
1582  * Field Access Macros:
1583  *
1584  */
1585 /*
1586  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF
1587  *
1588  * Boundary-scan interface is disabled. Execution of boundary-scan instructions in
1589  * the FPGA JTAG TAP controller is unsupported and produces undefined results.
1590  */
1591 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0
1592 /*
1593  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF
1594  *
1595  * Boundary-scan interface is enabled. Execution of the boundary-scan instructions
1596  * in the FPGA JTAG TAP controller is supported.
1597  */
1598 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1
1599 
1600 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1601 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3
1602 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1603 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3
1604 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1605 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1
1606 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */
1607 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008
1608 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value. */
1609 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7
1610 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field. */
1611 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1
1612 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register. */
1613 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3)
1614 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register. */
1615 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008)
1616 
1617 /*
1618  * Field : Trace Interface - traceintf
1619  *
1620  * Used to disable the trace interface. This interface allows the HPS debug logic
1621  * to send trace data to logic in the FPGA fabric.
1622  *
1623  * Field Enumeration Values:
1624  *
1625  * Enum | Value | Description
1626  * :------------------------------------------|:------|:-----------------------------------------------
1627  * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS | 0x0 | Trace interface is disabled. HPS debug logic
1628  * : | | cannot send trace data to the FPGA fabric.
1629  * ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN | 0x1 | Trace interface is enabled. Other registers in
1630  * : | | the HPS debug logic must be programmmed to
1631  * : | | actually send trace data to the FPGA fabric.
1632  *
1633  * Field Access Macros:
1634  *
1635  */
1636 /*
1637  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF
1638  *
1639  * Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA
1640  * fabric.
1641  */
1642 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0
1643 /*
1644  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF
1645  *
1646  * Trace interface is enabled. Other registers in the HPS debug logic must be
1647  * programmmed to actually send trace data to the FPGA fabric.
1648  */
1649 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1
1650 
1651 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1652 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4
1653 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1654 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4
1655 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1656 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1
1657 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */
1658 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010
1659 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value. */
1660 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef
1661 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field. */
1662 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1
1663 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register. */
1664 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4)
1665 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register. */
1666 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010)
1667 
1668 /*
1669  * Field : STM Event Interface - stmeventintf
1670  *
1671  * Used to disable the STM event interface. This interface allows logic in the FPGA
1672  * fabric to trigger events to the STM debug module in the HPS.
1673  *
1674  * Field Enumeration Values:
1675  *
1676  * Enum | Value | Description
1677  * :---------------------------------------------|:------|:-----------------------------------------------
1678  * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS | 0x0 | STM event interface is disabled. Logic in the
1679  * : | | FPGA fabric cannot trigger STM events.
1680  * ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN | 0x1 | STM event interface is enabled. Logic in the
1681  * : | | FPGA fabric can trigger STM events.
1682  *
1683  * Field Access Macros:
1684  *
1685  */
1686 /*
1687  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF
1688  *
1689  * STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM
1690  * events.
1691  */
1692 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0
1693 /*
1694  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF
1695  *
1696  * STM event interface is enabled. Logic in the FPGA fabric can trigger STM
1697  * events.
1698  */
1699 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1
1700 
1701 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1702 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6
1703 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1704 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6
1705 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1706 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1
1707 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */
1708 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040
1709 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value. */
1710 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf
1711 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field. */
1712 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1
1713 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register. */
1714 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6)
1715 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register. */
1716 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040)
1717 
1718 /*
1719  * Field : Cross Trigger Interface (CTI) - crosstrigintf
1720  *
1721  * Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note
1722  * that this doesn't prevent the HPS debug logic from sending triggers to the FPGA
1723  * Fabric.
1724  *
1725  * Field Enumeration Values:
1726  *
1727  * Enum | Value | Description
1728  * :----------------------------------------------|:------|:----------------------------------
1729  * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS | 0x0 | FPGA Fabric cannot send triggers.
1730  * ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN | 0x1 | FPGA Fabric can send triggers.
1731  *
1732  * Field Access Macros:
1733  *
1734  */
1735 /*
1736  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF
1737  *
1738  * FPGA Fabric cannot send triggers.
1739  */
1740 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0
1741 /*
1742  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF
1743  *
1744  * FPGA Fabric can send triggers.
1745  */
1746 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1
1747 
1748 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1749 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7
1750 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1751 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7
1752 /* The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1753 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1
1754 /* The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */
1755 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080
1756 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value. */
1757 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f
1758 /* The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field. */
1759 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1
1760 /* Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register. */
1761 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7)
1762 /* Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register. */
1763 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080)
1764 
1765 #ifndef __ASSEMBLY__
1766 /*
1767  * WARNING: The C register and register group struct declarations are provided for
1768  * convenience and illustrative purposes. They should, however, be used with
1769  * caution as the C language standard provides no guarantees about the alignment or
1770  * atomicity of device memory accesses. The recommended practice for writing
1771  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1772  * alt_write_word() functions.
1773  *
1774  * The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV.
1775  */
1776 struct ALT_SYSMGR_FPGAINTF_INDIV_s
1777 {
1778  uint32_t rstreqintf : 1; /* Reset Request Interface */
1779  uint32_t jtagenintf : 1; /* JTAG Enable Interface */
1780  uint32_t configiointf : 1; /* CONFIG_IO Interface */
1781  uint32_t bscanintf : 1; /* Boundary-Scan Interface */
1782  uint32_t traceintf : 1; /* Trace Interface */
1783  uint32_t : 1; /* *UNDEFINED* */
1784  uint32_t stmeventintf : 1; /* STM Event Interface */
1785  uint32_t crosstrigintf : 1; /* Cross Trigger Interface (CTI) */
1786  uint32_t : 24; /* *UNDEFINED* */
1787 };
1788 
1789 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV. */
1790 typedef volatile struct ALT_SYSMGR_FPGAINTF_INDIV_s ALT_SYSMGR_FPGAINTF_INDIV_t;
1791 #endif /* __ASSEMBLY__ */
1792 
1793 /* The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component. */
1794 #define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4
1795 
1796 /*
1797  * Register : Module Disable Register - module
1798  *
1799  * Used to disable signals from the FPGA fabric to individual HPS modules.
1800  *
1801  * Register Layout
1802  *
1803  * Bits | Access | Reset | Description
1804  * :-------|:-------|:------|:------------
1805  * [1:0] | ??? | 0x0 | *UNDEFINED*
1806  * [2] | RW | 0x0 | EMAC Module
1807  * [3] | RW | 0x0 | EMAC Module
1808  * [31:4] | ??? | 0x0 | *UNDEFINED*
1809  *
1810  */
1811 /*
1812  * Field : EMAC Module - emac_0
1813  *
1814  * Used to disable signals from the FPGA fabric to the EMAC modules that could
1815  * potentially interfere with their normal operation.
1816  *
1817  * The array index corresponds to the EMAC module instance.
1818  *
1819  * Field Enumeration Values:
1820  *
1821  * Enum | Value | Description
1822  * :----------------------------------------|:------|:-------------------------------------------------
1823  * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation
1824  * : | | of the EMAC module.
1825  * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN | 0x1 | Signals from FPGA fabric can potentially affect
1826  * : | | operation of the EMAC module.
1827  *
1828  * Field Access Macros:
1829  *
1830  */
1831 /*
1832  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0
1833  *
1834  * Signals from FPGA fabric cannot affect operation of the EMAC module.
1835  */
1836 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0
1837 /*
1838  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0
1839  *
1840  * Signals from FPGA fabric can potentially affect operation of the EMAC module.
1841  */
1842 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1
1843 
1844 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1845 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2
1846 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1847 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2
1848 /* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1849 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1
1850 /* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */
1851 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004
1852 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value. */
1853 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb
1854 /* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field. */
1855 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0
1856 /* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 field value from a register. */
1857 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2)
1858 /* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field value suitable for setting the register. */
1859 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004)
1860 
1861 /*
1862  * Field : EMAC Module - emac_1
1863  *
1864  * Used to disable signals from the FPGA fabric to the EMAC modules that could
1865  * potentially interfere with their normal operation.
1866  *
1867  * The array index corresponds to the EMAC module instance.
1868  *
1869  * Field Enumeration Values:
1870  *
1871  * Enum | Value | Description
1872  * :----------------------------------------|:------|:-------------------------------------------------
1873  * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS | 0x0 | Signals from FPGA fabric cannot affect operation
1874  * : | | of the EMAC module.
1875  * ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN | 0x1 | Signals from FPGA fabric can potentially affect
1876  * : | | operation of the EMAC module.
1877  *
1878  * Field Access Macros:
1879  *
1880  */
1881 /*
1882  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1
1883  *
1884  * Signals from FPGA fabric cannot affect operation of the EMAC module.
1885  */
1886 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0
1887 /*
1888  * Enumerated value for register field ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1
1889  *
1890  * Signals from FPGA fabric can potentially affect operation of the EMAC module.
1891  */
1892 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1
1893 
1894 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1895 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3
1896 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1897 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3
1898 /* The width in bits of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1899 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1
1900 /* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */
1901 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008
1902 /* The mask used to clear the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value. */
1903 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7
1904 /* The reset value of the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field. */
1905 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0
1906 /* Extracts the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 field value from a register. */
1907 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3)
1908 /* Produces a ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field value suitable for setting the register. */
1909 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008)
1910 
1911 #ifndef __ASSEMBLY__
1912 /*
1913  * WARNING: The C register and register group struct declarations are provided for
1914  * convenience and illustrative purposes. They should, however, be used with
1915  * caution as the C language standard provides no guarantees about the alignment or
1916  * atomicity of device memory accesses. The recommended practice for writing
1917  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1918  * alt_write_word() functions.
1919  *
1920  * The struct declaration for register ALT_SYSMGR_FPGAINTF_MODULE.
1921  */
1922 struct ALT_SYSMGR_FPGAINTF_MODULE_s
1923 {
1924  uint32_t : 2; /* *UNDEFINED* */
1925  uint32_t emac_0 : 1; /* EMAC Module */
1926  uint32_t emac_1 : 1; /* EMAC Module */
1927  uint32_t : 28; /* *UNDEFINED* */
1928 };
1929 
1930 /* The typedef declaration for register ALT_SYSMGR_FPGAINTF_MODULE. */
1931 typedef volatile struct ALT_SYSMGR_FPGAINTF_MODULE_s ALT_SYSMGR_FPGAINTF_MODULE_t;
1932 #endif /* __ASSEMBLY__ */
1933 
1934 /* The byte offset of the ALT_SYSMGR_FPGAINTF_MODULE register from the beginning of the component. */
1935 #define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8
1936 
1937 #ifndef __ASSEMBLY__
1938 /*
1939  * WARNING: The C register and register group struct declarations are provided for
1940  * convenience and illustrative purposes. They should, however, be used with
1941  * caution as the C language standard provides no guarantees about the alignment or
1942  * atomicity of device memory accesses. The recommended practice for writing
1943  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1944  * alt_write_word() functions.
1945  *
1946  * The struct declaration for register group ALT_SYSMGR_FPGAINTF.
1947  */
1948 struct ALT_SYSMGR_FPGAINTF_s
1949 {
1950  ALT_SYSMGR_FPGAINTF_GBL_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */
1951  ALT_SYSMGR_FPGAINTF_INDIV_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */
1952  ALT_SYSMGR_FPGAINTF_MODULE_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */
1953  volatile uint32_t _pad_0xc_0x10; /* *UNDEFINED* */
1954 };
1955 
1956 /* The typedef declaration for register group ALT_SYSMGR_FPGAINTF. */
1957 typedef volatile struct ALT_SYSMGR_FPGAINTF_s ALT_SYSMGR_FPGAINTF_t;
1958 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */
1959 struct ALT_SYSMGR_FPGAINTF_raw_s
1960 {
1961  volatile uint32_t gbl; /* ALT_SYSMGR_FPGAINTF_GBL */
1962  volatile uint32_t indiv; /* ALT_SYSMGR_FPGAINTF_INDIV */
1963  volatile uint32_t module; /* ALT_SYSMGR_FPGAINTF_MODULE */
1964  uint32_t _pad_0xc_0x10; /* *UNDEFINED* */
1965 };
1966 
1967 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FPGAINTF. */
1968 typedef volatile struct ALT_SYSMGR_FPGAINTF_raw_s ALT_SYSMGR_FPGAINTF_raw_t;
1969 #endif /* __ASSEMBLY__ */
1970 
1971 
1972 /*
1973  * Register Group : Scan Manager Group - ALT_SYSMGR_SCANMGR
1974  * Scan Manager Group
1975  *
1976  * Registers related to the Scan Manager that aren't located inside the Scan
1977  * Manager itself.
1978  *
1979  */
1980 /*
1981  * Register : Scan Manager Control Register - ctrl
1982  *
1983  * Controls behaviors of Scan Manager not controlled by registers in the Scan
1984  * Manager itself.
1985  *
1986  * Register Layout
1987  *
1988  * Bits | Access | Reset | Description
1989  * :-------|:-------|:------|:-----------------
1990  * [0] | RW | 0x0 | FPGA JTAG Enable
1991  * [31:1] | ??? | 0x0 | *UNDEFINED*
1992  *
1993  */
1994 /*
1995  * Field : FPGA JTAG Enable - fpgajtagen
1996  *
1997  * Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA.
1998  *
1999  * Only reset by a cold reset (ignores warm reset).
2000  *
2001  * Field Enumeration Values:
2002  *
2003  * Enum | Value | Description
2004  * :---------------------------------------------|:------|:------------------------------------------
2005  * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS | 0x0 | FPGA JTAG pins drive JTAG signals to FPGA
2006  * ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR | 0x1 | Scan Manager drives JTAG signals to FPGA
2007  *
2008  * Field Access Macros:
2009  *
2010  */
2011 /*
2012  * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN
2013  *
2014  * FPGA JTAG pins drive JTAG signals to FPGA
2015  */
2016 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0
2017 /*
2018  * Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN
2019  *
2020  * Scan Manager drives JTAG signals to FPGA
2021  */
2022 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1
2023 
2024 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2025 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0
2026 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2027 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0
2028 /* The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2029 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1
2030 /* The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */
2031 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001
2032 /* The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value. */
2033 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe
2034 /* The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field. */
2035 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0
2036 /* Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register. */
2037 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0)
2038 /* Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register. */
2039 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001)
2040 
2041 #ifndef __ASSEMBLY__
2042 /*
2043  * WARNING: The C register and register group struct declarations are provided for
2044  * convenience and illustrative purposes. They should, however, be used with
2045  * caution as the C language standard provides no guarantees about the alignment or
2046  * atomicity of device memory accesses. The recommended practice for writing
2047  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2048  * alt_write_word() functions.
2049  *
2050  * The struct declaration for register ALT_SYSMGR_SCANMGR_CTL.
2051  */
2052 struct ALT_SYSMGR_SCANMGR_CTL_s
2053 {
2054  uint32_t fpgajtagen : 1; /* FPGA JTAG Enable */
2055  uint32_t : 31; /* *UNDEFINED* */
2056 };
2057 
2058 /* The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL. */
2059 typedef volatile struct ALT_SYSMGR_SCANMGR_CTL_s ALT_SYSMGR_SCANMGR_CTL_t;
2060 #endif /* __ASSEMBLY__ */
2061 
2062 /* The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component. */
2063 #define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0
2064 
2065 #ifndef __ASSEMBLY__
2066 /*
2067  * WARNING: The C register and register group struct declarations are provided for
2068  * convenience and illustrative purposes. They should, however, be used with
2069  * caution as the C language standard provides no guarantees about the alignment or
2070  * atomicity of device memory accesses. The recommended practice for writing
2071  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2072  * alt_write_word() functions.
2073  *
2074  * The struct declaration for register group ALT_SYSMGR_SCANMGR.
2075  */
2076 struct ALT_SYSMGR_SCANMGR_s
2077 {
2078  ALT_SYSMGR_SCANMGR_CTL_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */
2079 };
2080 
2081 /* The typedef declaration for register group ALT_SYSMGR_SCANMGR. */
2082 typedef volatile struct ALT_SYSMGR_SCANMGR_s ALT_SYSMGR_SCANMGR_t;
2083 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */
2084 struct ALT_SYSMGR_SCANMGR_raw_s
2085 {
2086  volatile uint32_t ctrl; /* ALT_SYSMGR_SCANMGR_CTL */
2087 };
2088 
2089 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SCANMGR. */
2090 typedef volatile struct ALT_SYSMGR_SCANMGR_raw_s ALT_SYSMGR_SCANMGR_raw_t;
2091 #endif /* __ASSEMBLY__ */
2092 
2093 
2094 /*
2095  * Register Group : Freeze Control Group - ALT_SYSMGR_FRZCTL
2096  * Freeze Control Group
2097  *
2098  * Registers used to generate HPS IO freeze signals.
2099  *
2100  * All registers are only reset by a cold reset (ignore warm reset).
2101  *
2102  */
2103 /*
2104  * Register : VIO Control Register - vioctrl
2105  *
2106  * Used to drive freeze signals to HPS VIO banks.
2107  *
2108  * The register array index corresponds to the freeze channel.
2109  *
2110  * Freeze channel 0 provides freeze signals to VIO bank 0 and 1.
2111  *
2112  * Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze
2113  * signals when SRC.VIO1 is set to SW.
2114  *
2115  * Freeze channel 2 provides freeze signals to VIO bank 4.
2116  *
2117  * All fields are only reset by a cold reset (ignore warm reset).
2118  *
2119  * The following equation determines when the weak pullup resistor is enabled:
2120  *
2121  * enabled = ~wkpullup | (CFF & cfg & tristate)
2122  *
2123  * where CFF is the value of weak pullup as set by IO configuration
2124  *
2125  * Register Layout
2126  *
2127  * Bits | Access | Reset | Description
2128  * :-------|:-------|:------|:-----------------
2129  * [0] | RW | 0x0 | IO Configuration
2130  * [1] | RW | 0x0 | IO Bus Hold
2131  * [2] | RW | 0x0 | IO Tri-State
2132  * [3] | RW | 0x0 | IO Weak Pullup
2133  * [4] | RW | 0x0 | IO Slew-rate
2134  * [31:5] | ??? | 0x0 | *UNDEFINED*
2135  *
2136  */
2137 /*
2138  * Field : IO Configuration - cfg
2139  *
2140  * Controls IO configuration
2141  *
2142  * Field Enumeration Values:
2143  *
2144  * Enum | Value | Description
2145  * :-----------------------------------|:------|:-----------------------------------------------
2146  * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe
2147  * : | | value).
2148  * ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously
2149  * : | | configured by software using the Scan Manager.
2150  *
2151  * Field Access Macros:
2152  *
2153  */
2154 /*
2155  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
2156  *
2157  * Disable IO configuration (forced to a safe value).
2158  */
2159 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0
2160 /*
2161  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
2162  *
2163  * Enables IO configuration as previously configured by software using the Scan
2164  * Manager.
2165  */
2166 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1
2167 
2168 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2169 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0
2170 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2171 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0
2172 /* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2173 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1
2174 /* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */
2175 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001
2176 /* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value. */
2177 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe
2178 /* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field. */
2179 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0
2180 /* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register. */
2181 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2182 /* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register. */
2183 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2184 
2185 /*
2186  * Field : IO Bus Hold - bushold
2187  *
2188  * Controls bus hold circuit
2189  *
2190  * Field Enumeration Values:
2191  *
2192  * Enum | Value | Description
2193  * :---------------------------------------|:------|:-------------------------------------------------
2194  * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit.
2195  * ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration.
2196  *
2197  * Field Access Macros:
2198  *
2199  */
2200 /*
2201  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
2202  *
2203  * Disable bus hold circuit.
2204  */
2205 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0
2206 /*
2207  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
2208  *
2209  * Bus hold circuit controlled by IO configuration.
2210  */
2211 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1
2212 
2213 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2214 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1
2215 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2216 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1
2217 /* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2218 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1
2219 /* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */
2220 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002
2221 /* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value. */
2222 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2223 /* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field. */
2224 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0
2225 /* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register. */
2226 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2227 /* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register. */
2228 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2229 
2230 /*
2231  * Field : IO Tri-State - tristate
2232  *
2233  * Controls IO tri-state
2234  *
2235  * Field Enumeration Values:
2236  *
2237  * Enum | Value | Description
2238  * :----------------------------------------|:------|:---------------------------------------------
2239  * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled.
2240  * ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration.
2241  *
2242  * Field Access Macros:
2243  *
2244  */
2245 /*
2246  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
2247  *
2248  * IO tri-state enabled.
2249  */
2250 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0
2251 /*
2252  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
2253  *
2254  * IO tri-state controlled by IO configuration.
2255  */
2256 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1
2257 
2258 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2259 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2
2260 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2261 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2
2262 /* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2263 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1
2264 /* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */
2265 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004
2266 /* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value. */
2267 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2268 /* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field. */
2269 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0
2270 /* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register. */
2271 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2272 /* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register. */
2273 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2274 
2275 /*
2276  * Field : IO Weak Pullup - wkpullup
2277  *
2278  * Controls weak pullup resistor
2279  *
2280  * Field Enumeration Values:
2281  *
2282  * Enum | Value | Description
2283  * :----------------------------------------|:------|:---------------------------------------------
2284  * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled.
2285  * ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO
2286  * : | | configuration.
2287  *
2288  * Field Access Macros:
2289  *
2290  */
2291 /*
2292  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
2293  *
2294  * Weak pullup resistor enabled.
2295  */
2296 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0
2297 /*
2298  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
2299  *
2300  * Weak pullup resistor enable controlled by IO configuration.
2301  */
2302 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1
2303 
2304 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2305 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3
2306 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2307 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3
2308 /* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2309 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1
2310 /* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */
2311 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008
2312 /* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value. */
2313 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2314 /* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field. */
2315 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0
2316 /* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register. */
2317 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2318 /* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register. */
2319 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2320 
2321 /*
2322  * Field : IO Slew-rate - slew
2323  *
2324  * Controls IO slew-rate
2325  *
2326  * Field Enumeration Values:
2327  *
2328  * Enum | Value | Description
2329  * :-------------------------------------|:------|:------------------------------------------
2330  * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow.
2331  * ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration.
2332  *
2333  * Field Access Macros:
2334  *
2335  */
2336 /*
2337  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
2338  *
2339  * Slew-rate forced to slow.
2340  */
2341 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0
2342 /*
2343  * Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
2344  *
2345  * Slew-rate controlled by IO configuration.
2346  */
2347 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1
2348 
2349 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2350 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4
2351 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2352 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4
2353 /* The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2354 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1
2355 /* The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */
2356 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010
2357 /* The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value. */
2358 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef
2359 /* The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field. */
2360 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0
2361 /* Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register. */
2362 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2363 /* Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register. */
2364 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2365 
2366 #ifndef __ASSEMBLY__
2367 /*
2368  * WARNING: The C register and register group struct declarations are provided for
2369  * convenience and illustrative purposes. They should, however, be used with
2370  * caution as the C language standard provides no guarantees about the alignment or
2371  * atomicity of device memory accesses. The recommended practice for writing
2372  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2373  * alt_write_word() functions.
2374  *
2375  * The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL.
2376  */
2377 struct ALT_SYSMGR_FRZCTL_VIOCTL_s
2378 {
2379  uint32_t cfg : 1; /* IO Configuration */
2380  uint32_t bushold : 1; /* IO Bus Hold */
2381  uint32_t tristate : 1; /* IO Tri-State */
2382  uint32_t wkpullup : 1; /* IO Weak Pullup */
2383  uint32_t slew : 1; /* IO Slew-rate */
2384  uint32_t : 27; /* *UNDEFINED* */
2385 };
2386 
2387 /* The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL. */
2388 typedef volatile struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t;
2389 #endif /* __ASSEMBLY__ */
2390 
2391 /* The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component. */
2392 #define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0
2393 
2394 /*
2395  * Register : HIO Control Register - hioctrl
2396  *
2397  * Used to drive freeze signals to HPS HIO bank (DDR SDRAM).
2398  *
2399  * All fields are only reset by a cold reset (ignore warm reset).
2400  *
2401  * The following equation determines when the weak pullup resistor is enabled:
2402  *
2403  * enabled = ~wkpullup | (CFF & cfg & tristate)
2404  *
2405  * where CFF is the value of weak pullup as set by IO configuration
2406  *
2407  * Register Layout
2408  *
2409  * Bits | Access | Reset | Description
2410  * :-------|:-------|:------|:-----------------------------------------
2411  * [0] | RW | 0x0 | IO Configuration
2412  * [1] | RW | 0x0 | IO Bus Hold
2413  * [2] | RW | 0x0 | IO Tri-State
2414  * [3] | RW | 0x0 | IO Weak Pullup
2415  * [4] | RW | 0x0 | IO Slew-rate
2416  * [5] | RW | 0x1 | DLL Reset
2417  * [6] | RW | 0x1 | OCT Reset
2418  * [7] | RW | 0x1 | IO and DQS Reset
2419  * [8] | RW | 0x0 | OCT Calibration and Configuration Enable
2420  * [31:9] | ??? | 0x0 | *UNDEFINED*
2421  *
2422  */
2423 /*
2424  * Field : IO Configuration - cfg
2425  *
2426  * Controls IO configuration
2427  *
2428  * Field Enumeration Values:
2429  *
2430  * Enum | Value | Description
2431  * :-----------------------------------|:------|:-----------------------------------------------
2432  * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS | 0x0 | Disable IO configuration (forced to a safe
2433  * : | | value).
2434  * ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG | 0x1 | Enables IO configuration as previously
2435  * : | | configured by software using the Scan Manager.
2436  *
2437  * Field Access Macros:
2438  *
2439  */
2440 /*
2441  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
2442  *
2443  * Disable IO configuration (forced to a safe value).
2444  */
2445 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0
2446 /*
2447  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
2448  *
2449  * Enables IO configuration as previously configured by software using the Scan
2450  * Manager.
2451  */
2452 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1
2453 
2454 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2455 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0
2456 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2457 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0
2458 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2459 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1
2460 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */
2461 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001
2462 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value. */
2463 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe
2464 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field. */
2465 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0
2466 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register. */
2467 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2468 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register. */
2469 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2470 
2471 /*
2472  * Field : IO Bus Hold - bushold
2473  *
2474  * Controls bus hold circuit
2475  *
2476  * Field Enumeration Values:
2477  *
2478  * Enum | Value | Description
2479  * :---------------------------------------|:------|:-------------------------------------------------
2480  * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS | 0x0 | Disable bus hold circuit.
2481  * ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG | 0x1 | Bus hold circuit controlled by IO configuration.
2482  *
2483  * Field Access Macros:
2484  *
2485  */
2486 /*
2487  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
2488  *
2489  * Disable bus hold circuit.
2490  */
2491 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0
2492 /*
2493  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
2494  *
2495  * Bus hold circuit controlled by IO configuration.
2496  */
2497 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1
2498 
2499 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2500 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1
2501 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2502 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1
2503 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2504 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1
2505 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */
2506 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002
2507 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value. */
2508 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2509 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field. */
2510 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0
2511 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register. */
2512 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2513 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register. */
2514 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2515 
2516 /*
2517  * Field : IO Tri-State - tristate
2518  *
2519  * Controls IO tri-state
2520  *
2521  * Field Enumeration Values:
2522  *
2523  * Enum | Value | Description
2524  * :----------------------------------------|:------|:---------------------------------------------
2525  * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN | 0x0 | IO tri-state enabled.
2526  * ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG | 0x1 | IO tri-state controlled by IO configuration.
2527  *
2528  * Field Access Macros:
2529  *
2530  */
2531 /*
2532  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
2533  *
2534  * IO tri-state enabled.
2535  */
2536 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0
2537 /*
2538  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
2539  *
2540  * IO tri-state controlled by IO configuration.
2541  */
2542 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1
2543 
2544 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2545 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2
2546 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2547 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2
2548 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2549 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1
2550 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */
2551 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004
2552 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value. */
2553 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2554 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field. */
2555 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0
2556 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register. */
2557 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2558 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register. */
2559 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2560 
2561 /*
2562  * Field : IO Weak Pullup - wkpullup
2563  *
2564  * Controls weak pullup resistor
2565  *
2566  * Field Enumeration Values:
2567  *
2568  * Enum | Value | Description
2569  * :----------------------------------------|:------|:---------------------------------------------
2570  * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN | 0x0 | Weak pullup resistor enabled.
2571  * ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG | 0x1 | Weak pullup resistor enable controlled by IO
2572  * : | | configuration.
2573  *
2574  * Field Access Macros:
2575  *
2576  */
2577 /*
2578  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
2579  *
2580  * Weak pullup resistor enabled.
2581  */
2582 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0
2583 /*
2584  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
2585  *
2586  * Weak pullup resistor enable controlled by IO configuration.
2587  */
2588 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1
2589 
2590 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2591 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3
2592 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2593 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3
2594 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2595 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1
2596 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */
2597 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008
2598 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value. */
2599 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2600 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field. */
2601 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0
2602 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register. */
2603 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2604 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register. */
2605 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2606 
2607 /*
2608  * Field : IO Slew-rate - slew
2609  *
2610  * Controls IO slew-rate
2611  *
2612  * Field Enumeration Values:
2613  *
2614  * Enum | Value | Description
2615  * :-------------------------------------|:------|:------------------------------------------
2616  * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW | 0x0 | Slew-rate forced to slow.
2617  * ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG | 0x1 | Slew-rate controlled by IO configuration.
2618  *
2619  * Field Access Macros:
2620  *
2621  */
2622 /*
2623  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
2624  *
2625  * Slew-rate forced to slow.
2626  */
2627 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0
2628 /*
2629  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
2630  *
2631  * Slew-rate controlled by IO configuration.
2632  */
2633 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1
2634 
2635 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2636 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4
2637 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2638 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4
2639 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2640 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1
2641 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */
2642 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010
2643 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value. */
2644 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef
2645 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field. */
2646 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0
2647 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register. */
2648 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2649 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register. */
2650 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2651 
2652 /*
2653  * Field : DLL Reset - dllrst
2654  *
2655  * Controls DLL (Delay-Locked Loop) reset.
2656  *
2657  * Field Enumeration Values:
2658  *
2659  * Enum | Value | Description
2660  * :--------------------------------------|:------|:----------------------------------------------
2661  * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS | 0x0 | No reset or clock gating.
2662  * ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN | 0x1 | Resets registers in the DLL and gates off DLL
2663  * : | | clock.
2664  *
2665  * Field Access Macros:
2666  *
2667  */
2668 /*
2669  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
2670  *
2671  * No reset or clock gating.
2672  */
2673 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0
2674 /*
2675  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
2676  *
2677  * Resets registers in the DLL and gates off DLL clock.
2678  */
2679 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1
2680 
2681 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2682 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5
2683 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2684 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5
2685 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2686 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1
2687 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */
2688 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020
2689 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value. */
2690 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf
2691 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field. */
2692 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1
2693 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register. */
2694 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5)
2695 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register. */
2696 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020)
2697 
2698 /*
2699  * Field : OCT Reset - octrst
2700  *
2701  * Controls OCT reset.
2702  *
2703  * Field Enumeration Values:
2704  *
2705  * Enum | Value | Description
2706  * :--------------------------------------|:------|:-----------------------------
2707  * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS | 0x0 | No reset.
2708  * ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN | 0x1 | Resets registers in the OCT.
2709  *
2710  * Field Access Macros:
2711  *
2712  */
2713 /*
2714  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
2715  *
2716  * No reset.
2717  */
2718 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0
2719 /*
2720  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
2721  *
2722  * Resets registers in the OCT.
2723  */
2724 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1
2725 
2726 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2727 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6
2728 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2729 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6
2730 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2731 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1
2732 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */
2733 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040
2734 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value. */
2735 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf
2736 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field. */
2737 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1
2738 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register. */
2739 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6)
2740 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register. */
2741 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040)
2742 
2743 /*
2744  * Field : IO and DQS Reset - regrst
2745  *
2746  * Controls IO and DQS reset.
2747  *
2748  * Field Enumeration Values:
2749  *
2750  * Enum | Value | Description
2751  * :--------------------------------------|:------|:-------------------------------------------
2752  * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS | 0x0 | No reset.
2753  * ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN | 0x1 | Resets all IO registers and DQS registers.
2754  *
2755  * Field Access Macros:
2756  *
2757  */
2758 /*
2759  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
2760  *
2761  * No reset.
2762  */
2763 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0
2764 /*
2765  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
2766  *
2767  * Resets all IO registers and DQS registers.
2768  */
2769 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1
2770 
2771 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2772 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7
2773 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2774 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7
2775 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2776 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1
2777 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */
2778 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080
2779 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value. */
2780 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f
2781 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field. */
2782 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1
2783 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register. */
2784 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7)
2785 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register. */
2786 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080)
2787 
2788 /*
2789  * Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart
2790  *
2791  * Controls OCT calibration and OCT IO configuration enable.
2792  *
2793  * Field Enumeration Values:
2794  *
2795  * Enum | Value | Description
2796  * :--------------------------------------------------|:------|:-------------------------------------------------
2797  * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS | 0x0 | Disables IO configuration (forced to a safe
2798  * : | | value) in OCT calibration block.
2799  * ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN | 0x1 | Starts OCT calibration state machine and enables
2800  * : | | IO configuration in OCT calibration block.
2801  *
2802  * Field Access Macros:
2803  *
2804  */
2805 /*
2806  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
2807  *
2808  * Disables IO configuration (forced to a safe value) in OCT calibration block.
2809  */
2810 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0
2811 /*
2812  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
2813  *
2814  * Starts OCT calibration state machine and enables IO configuration in OCT
2815  * calibration block.
2816  */
2817 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1
2818 
2819 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2820 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8
2821 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2822 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8
2823 /* The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2824 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1
2825 /* The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */
2826 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100
2827 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value. */
2828 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff
2829 /* The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field. */
2830 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0
2831 /* Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register. */
2832 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8)
2833 /* Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register. */
2834 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100)
2835 
2836 #ifndef __ASSEMBLY__
2837 /*
2838  * WARNING: The C register and register group struct declarations are provided for
2839  * convenience and illustrative purposes. They should, however, be used with
2840  * caution as the C language standard provides no guarantees about the alignment or
2841  * atomicity of device memory accesses. The recommended practice for writing
2842  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2843  * alt_write_word() functions.
2844  *
2845  * The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL.
2846  */
2847 struct ALT_SYSMGR_FRZCTL_HIOCTL_s
2848 {
2849  uint32_t cfg : 1; /* IO Configuration */
2850  uint32_t bushold : 1; /* IO Bus Hold */
2851  uint32_t tristate : 1; /* IO Tri-State */
2852  uint32_t wkpullup : 1; /* IO Weak Pullup */
2853  uint32_t slew : 1; /* IO Slew-rate */
2854  uint32_t dllrst : 1; /* DLL Reset */
2855  uint32_t octrst : 1; /* OCT Reset */
2856  uint32_t regrst : 1; /* IO and DQS Reset */
2857  uint32_t oct_cfgen_calstart : 1; /* OCT Calibration and Configuration Enable */
2858  uint32_t : 23; /* *UNDEFINED* */
2859 };
2860 
2861 /* The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL. */
2862 typedef volatile struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t;
2863 #endif /* __ASSEMBLY__ */
2864 
2865 /* The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component. */
2866 #define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10
2867 
2868 /*
2869  * Register : Source Register - src
2870  *
2871  * Contains register field to choose between software state machine (vioctrl array
2872  * index [1] register) or hardware state machine in the Freeze Controller as the
2873  * freeze signal source for VIO channel 1.
2874  *
2875  * All fields are only reset by a cold reset (ignore warm reset).
2876  *
2877  * Register Layout
2878  *
2879  * Bits | Access | Reset | Description
2880  * :-------|:-------|:------|:--------------------------
2881  * [0] | RW | 0x0 | VIO1 Freeze Signal Source
2882  * [31:1] | ??? | 0x0 | *UNDEFINED*
2883  *
2884  */
2885 /*
2886  * Field : VIO1 Freeze Signal Source - vio1
2887  *
2888  * The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3).
2889  *
2890  * Field Enumeration Values:
2891  *
2892  * Enum | Value | Description
2893  * :--------------------------------|:------|:-------------------------------------------------
2894  * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW | 0x0 | VIO1 freeze signals are driven by software
2895  * : | | writing to the VIOCTRL[1] register. The
2896  * : | | VIO1-related fields in the hwctrl register are
2897  * : | | active but don't effect the VIO1 freeze signals.
2898  * ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW | 0x1 | VIO1 freeze signals are driven by the hardware
2899  * : | | state machine in the Freeze Controller. The
2900  * : | | VIO1-related fields in the hwctrl register are
2901  * : | | active and effect the VIO1 freeze signals.
2902  *
2903  * Field Access Macros:
2904  *
2905  */
2906 /*
2907  * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1
2908  *
2909  * VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register.
2910  * The VIO1-related fields in the hwctrl register are active but don't effect the
2911  * VIO1 freeze signals.
2912  */
2913 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0
2914 /*
2915  * Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1
2916  *
2917  * VIO1 freeze signals are driven by the hardware state machine in the Freeze
2918  * Controller. The VIO1-related fields in the hwctrl register are active and effect
2919  * the VIO1 freeze signals.
2920  */
2921 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1
2922 
2923 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2924 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0
2925 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2926 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0
2927 /* The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2928 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1
2929 /* The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */
2930 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001
2931 /* The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value. */
2932 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe
2933 /* The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field. */
2934 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0
2935 /* Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register. */
2936 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0)
2937 /* Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register. */
2938 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001)
2939 
2940 #ifndef __ASSEMBLY__
2941 /*
2942  * WARNING: The C register and register group struct declarations are provided for
2943  * convenience and illustrative purposes. They should, however, be used with
2944  * caution as the C language standard provides no guarantees about the alignment or
2945  * atomicity of device memory accesses. The recommended practice for writing
2946  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
2947  * alt_write_word() functions.
2948  *
2949  * The struct declaration for register ALT_SYSMGR_FRZCTL_SRC.
2950  */
2951 struct ALT_SYSMGR_FRZCTL_SRC_s
2952 {
2953  uint32_t vio1 : 1; /* VIO1 Freeze Signal Source */
2954  uint32_t : 31; /* *UNDEFINED* */
2955 };
2956 
2957 /* The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC. */
2958 typedef volatile struct ALT_SYSMGR_FRZCTL_SRC_s ALT_SYSMGR_FRZCTL_SRC_t;
2959 #endif /* __ASSEMBLY__ */
2960 
2961 /* The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component. */
2962 #define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14
2963 
2964 /*
2965  * Register : Hardware Control Register - hwctrl
2966  *
2967  * Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3)
2968  * and monitor for completeness and the current state.
2969  *
2970  * These fields interact with the hardware state machine in the Freeze Controller.
2971  * These fields can be accessed independent of the value of SRC1.VIO1 although they
2972  * only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup
2973  * to have the hardware state machine be the freeze signal source.
2974  *
2975  * All fields are only reset by a cold reset (ignore warm reset).
2976  *
2977  * Register Layout
2978  *
2979  * Bits | Access | Reset | Description
2980  * :-------|:-------|:------|:----------------------------------
2981  * [0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request
2982  * [2:1] | R | 0x2 | VIO channel 1 State
2983  * [31:3] | ??? | 0x0 | *UNDEFINED*
2984  *
2985  */
2986 /*
2987  * Field : VIO channel 1 Freeze/Thaw request - vio1req
2988  *
2989  * Requests hardware state machine to generate freeze signal sequence to transition
2990  * between frozen and thawed states.
2991  *
2992  * If this field is read by software, it contains the value previously written by
2993  * software (i.e. this field is not written by hardware).
2994  *
2995  * Field Enumeration Values:
2996  *
2997  * Enum | Value | Description
2998  * :------------------------------------------|:------|:--------------------------------------
2999  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW | 0x0 | Requests a thaw (unfreeze) operation.
3000  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ | 0x1 | Requests a freeze operation.
3001  *
3002  * Field Access Macros:
3003  *
3004  */
3005 /*
3006  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
3007  *
3008  * Requests a thaw (unfreeze) operation.
3009  */
3010 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0
3011 /*
3012  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
3013  *
3014  * Requests a freeze operation.
3015  */
3016 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1
3017 
3018 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3019 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0
3020 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3021 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0
3022 /* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3023 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1
3024 /* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */
3025 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001
3026 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value. */
3027 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe
3028 /* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field. */
3029 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1
3030 /* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register. */
3031 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0)
3032 /* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register. */
3033 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001)
3034 
3035 /*
3036  * Field : VIO channel 1 State - vio1state
3037  *
3038  * Software reads this field to determine the current frozen/thawed state of the
3039  * VIO channel 1 or to determine when a freeze/thaw request is made by writing the
3040  * corresponding *REQ field in this register has completed.
3041  *
3042  * Reset by a cold reset (ignores warm reset).
3043  *
3044  * Field Enumeration Values:
3045  *
3046  * Enum | Value | Description
3047  * :--------------------------------------------------|:------|:-------------------------------------------------
3048  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN | 0x0 | Transitioning from thawed state to frozen state.
3049  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED | 0x1 | Thawed state. I/Os behave as configured. I/Os
3050  * : | | must be configured by the Scan Manager before
3051  * : | | entering this state.
3052  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN | 0x2 | Frozen state. I/O configuration is ignored.
3053  * : | | Instead, I/Os are in tri-state mode with a weak
3054  * : | | pull-up. Scan Manager can be used to configure
3055  * : | | the I/Os while they are frozen.
3056  * ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED | 0x3 | Transitioning from frozen state to thawed state.
3057  *
3058  * Field Access Macros:
3059  *
3060  */
3061 /*
3062  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3063  *
3064  * Transitioning from thawed state to frozen state.
3065  */
3066 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0
3067 /*
3068  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3069  *
3070  * Thawed state. I/Os behave as configured. I/Os must be configured by the Scan
3071  * Manager before entering this state.
3072  */
3073 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1
3074 /*
3075  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3076  *
3077  * Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode
3078  * with a weak pull-up. Scan Manager can be used to configure the I/Os while they
3079  * are frozen.
3080  */
3081 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2
3082 /*
3083  * Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
3084  *
3085  * Transitioning from frozen state to thawed state.
3086  */
3087 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3
3088 
3089 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3090 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1
3091 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3092 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2
3093 /* The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3094 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2
3095 /* The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */
3096 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006
3097 /* The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value. */
3098 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9
3099 /* The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field. */
3100 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2
3101 /* Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register. */
3102 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1)
3103 /* Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register. */
3104 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006)
3105 
3106 #ifndef __ASSEMBLY__
3107 /*
3108  * WARNING: The C register and register group struct declarations are provided for
3109  * convenience and illustrative purposes. They should, however, be used with
3110  * caution as the C language standard provides no guarantees about the alignment or
3111  * atomicity of device memory accesses. The recommended practice for writing
3112  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3113  * alt_write_word() functions.
3114  *
3115  * The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL.
3116  */
3117 struct ALT_SYSMGR_FRZCTL_HWCTL_s
3118 {
3119  uint32_t vio1req : 1; /* VIO channel 1 Freeze/Thaw request */
3120  const uint32_t vio1state : 2; /* VIO channel 1 State */
3121  uint32_t : 29; /* *UNDEFINED* */
3122 };
3123 
3124 /* The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL. */
3125 typedef volatile struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t;
3126 #endif /* __ASSEMBLY__ */
3127 
3128 /* The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component. */
3129 #define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18
3130 
3131 #ifndef __ASSEMBLY__
3132 /*
3133  * WARNING: The C register and register group struct declarations are provided for
3134  * convenience and illustrative purposes. They should, however, be used with
3135  * caution as the C language standard provides no guarantees about the alignment or
3136  * atomicity of device memory accesses. The recommended practice for writing
3137  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3138  * alt_write_word() functions.
3139  *
3140  * The struct declaration for register group ALT_SYSMGR_FRZCTL.
3141  */
3142 struct ALT_SYSMGR_FRZCTL_s
3143 {
3144  ALT_SYSMGR_FRZCTL_VIOCTL_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */
3145  volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3146  ALT_SYSMGR_FRZCTL_HIOCTL_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */
3147  ALT_SYSMGR_FRZCTL_SRC_t src; /* ALT_SYSMGR_FRZCTL_SRC */
3148  ALT_SYSMGR_FRZCTL_HWCTL_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */
3149  volatile uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */
3150 };
3151 
3152 /* The typedef declaration for register group ALT_SYSMGR_FRZCTL. */
3153 typedef volatile struct ALT_SYSMGR_FRZCTL_s ALT_SYSMGR_FRZCTL_t;
3154 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */
3155 struct ALT_SYSMGR_FRZCTL_raw_s
3156 {
3157  volatile uint32_t vioctrl[3]; /* ALT_SYSMGR_FRZCTL_VIOCTL */
3158  uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
3159  volatile uint32_t hioctrl; /* ALT_SYSMGR_FRZCTL_HIOCTL */
3160  volatile uint32_t src; /* ALT_SYSMGR_FRZCTL_SRC */
3161  volatile uint32_t hwctrl; /* ALT_SYSMGR_FRZCTL_HWCTL */
3162  uint32_t _pad_0x1c_0x20; /* *UNDEFINED* */
3163 };
3164 
3165 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_FRZCTL. */
3166 typedef volatile struct ALT_SYSMGR_FRZCTL_raw_s ALT_SYSMGR_FRZCTL_raw_t;
3167 #endif /* __ASSEMBLY__ */
3168 
3169 
3170 /*
3171  * Register Group : EMAC Group - ALT_SYSMGR_EMAC
3172  * EMAC Group
3173  *
3174  * External control registers for the EMACs
3175  *
3176  */
3177 /*
3178  * Register : Control Register - ctrl
3179  *
3180  * Registers used by the EMACs. All fields are reset by a cold or warm reset.
3181  *
3182  * Register Layout
3183  *
3184  * Bits | Access | Reset | Description
3185  * :-------|:-------|:------|:---------------------
3186  * [1:0] | RW | 0x2 | PHY Interface Select
3187  * [3:2] | RW | 0x2 | PHY Interface Select
3188  * [4] | RW | 0x0 | PTP Clock Select
3189  * [5] | RW | 0x0 | PTP Clock Select
3190  * [31:6] | ??? | 0x0 | *UNDEFINED*
3191  *
3192  */
3193 /*
3194  * Field : PHY Interface Select - physel_0
3195  *
3196  * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC
3197  * module when it exits from reset. The associated enum defines the allowed values.
3198  * The field array index corresponds to the EMAC index.
3199  *
3200  * Field Enumeration Values:
3201  *
3202  * Enum | Value | Description
3203  * :----------------------------------------|:------|:------------------------------
3204  * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII | 0x0 | Select GMII/MII PHY interface
3205  * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII | 0x1 | Select RGMII PHY interface
3206  * ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII | 0x2 | Select RMII PHY interface
3207  *
3208  * Field Access Macros:
3209  *
3210  */
3211 /*
3212  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3213  *
3214  * Select GMII/MII PHY interface
3215  */
3216 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0
3217 /*
3218  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3219  *
3220  * Select RGMII PHY interface
3221  */
3222 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1
3223 /*
3224  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
3225  *
3226  * Select RMII PHY interface
3227  */
3228 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2
3229 
3230 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3231 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0
3232 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3233 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1
3234 /* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3235 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2
3236 /* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */
3237 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003
3238 /* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value. */
3239 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc
3240 /* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field. */
3241 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2
3242 /* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register. */
3243 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0)
3244 /* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register. */
3245 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003)
3246 
3247 /*
3248  * Field : PHY Interface Select - physel_1
3249  *
3250  * Controls the PHY interface selection of the EMACs. This is sampled by an EMAC
3251  * module when it exits from reset. The associated enum defines the allowed values.
3252  * The field array index corresponds to the EMAC index.
3253  *
3254  * Field Enumeration Values:
3255  *
3256  * Enum | Value | Description
3257  * :----------------------------------------|:------|:------------------------------
3258  * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII | 0x0 | Select GMII/MII PHY interface
3259  * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII | 0x1 | Select RGMII PHY interface
3260  * ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII | 0x2 | Select RMII PHY interface
3261  *
3262  * Field Access Macros:
3263  *
3264  */
3265 /*
3266  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3267  *
3268  * Select GMII/MII PHY interface
3269  */
3270 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0
3271 /*
3272  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3273  *
3274  * Select RGMII PHY interface
3275  */
3276 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1
3277 /*
3278  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
3279  *
3280  * Select RMII PHY interface
3281  */
3282 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2
3283 
3284 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3285 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2
3286 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3287 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3
3288 /* The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3289 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2
3290 /* The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */
3291 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c
3292 /* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value. */
3293 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3
3294 /* The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field. */
3295 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2
3296 /* Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register. */
3297 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2)
3298 /* Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register. */
3299 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c)
3300 
3301 /*
3302  * Field : PTP Clock Select - ptpclksel_0
3303  *
3304  * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC
3305  * module when it exits from reset. The field array index corresponds to the EMAC
3306  * index.
3307  *
3308  * Field Enumeration Values:
3309  *
3310  * Enum | Value | Description
3311  * :---------------------------------------------------|:------|:-------------------------
3312  * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK | 0x0 | Selects osc1_clk
3313  * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk
3314  *
3315  * Field Access Macros:
3316  *
3317  */
3318 /*
3319  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
3320  *
3321  * Selects osc1_clk
3322  */
3323 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0
3324 /*
3325  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
3326  *
3327  * Selects fpga_ptp_ref_clk
3328  */
3329 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1
3330 
3331 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3332 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4
3333 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3334 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4
3335 /* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3336 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1
3337 /* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */
3338 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010
3339 /* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value. */
3340 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef
3341 /* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field. */
3342 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0
3343 /* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register. */
3344 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4)
3345 /* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register. */
3346 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010)
3347 
3348 /*
3349  * Field : PTP Clock Select - ptpclksel_1
3350  *
3351  * Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC
3352  * module when it exits from reset. The field array index corresponds to the EMAC
3353  * index.
3354  *
3355  * Field Enumeration Values:
3356  *
3357  * Enum | Value | Description
3358  * :---------------------------------------------------|:------|:-------------------------
3359  * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK | 0x0 | Selects osc1_clk
3360  * ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK | 0x1 | Selects fpga_ptp_ref_clk
3361  *
3362  * Field Access Macros:
3363  *
3364  */
3365 /*
3366  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
3367  *
3368  * Selects osc1_clk
3369  */
3370 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0
3371 /*
3372  * Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
3373  *
3374  * Selects fpga_ptp_ref_clk
3375  */
3376 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1
3377 
3378 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3379 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5
3380 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3381 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5
3382 /* The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3383 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1
3384 /* The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */
3385 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020
3386 /* The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value. */
3387 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf
3388 /* The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field. */
3389 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0
3390 /* Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register. */
3391 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5)
3392 /* Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register. */
3393 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020)
3394 
3395 #ifndef __ASSEMBLY__
3396 /*
3397  * WARNING: The C register and register group struct declarations are provided for
3398  * convenience and illustrative purposes. They should, however, be used with
3399  * caution as the C language standard provides no guarantees about the alignment or
3400  * atomicity of device memory accesses. The recommended practice for writing
3401  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
3402  * alt_write_word() functions.
3403  *
3404  * The struct declaration for register ALT_SYSMGR_EMAC_CTL.
3405  */
3406 struct ALT_SYSMGR_EMAC_CTL_s
3407 {
3408  uint32_t physel_0 : 2; /* PHY Interface Select */
3409  uint32_t physel_1 : 2; /* PHY Interface Select */
3410  uint32_t ptpclksel_0 : 1; /* PTP Clock Select */
3411  uint32_t ptpclksel_1 : 1; /* PTP Clock Select */
3412  uint32_t : 26; /* *UNDEFINED* */
3413 };
3414 
3415 /* The typedef declaration for register ALT_SYSMGR_EMAC_CTL. */
3416 typedef volatile struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t;
3417 #endif /* __ASSEMBLY__ */
3418 
3419 /* The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component. */
3420 #define ALT_SYSMGR_EMAC_CTL_OFST 0x0
3421 
3422 /*
3423  * Register : EMAC L3 Master AxCACHE Register - l3master
3424  *
3425  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
3426  *
3427  * These register bits should be updated only during system initialization prior to
3428  * removing the peripheral from reset. They may not be changed dynamically during
3429  * peripheral operation
3430  *
3431  * All fields are reset by a cold or warm reset.
3432  *
3433  * Register Layout
3434  *
3435  * Bits | Access | Reset | Description
3436  * :--------|:-------|:------|:-------------
3437  * [3:0] | RW | 0x0 | EMAC ARCACHE
3438  * [7:4] | RW | 0x0 | EMAC ARCACHE
3439  * [11:8] | RW | 0x0 | EMAC AWCACHE
3440  * [15:12] | RW | 0x0 | EMAC AWCACHE
3441  * [31:16] | ??? | 0x0 | *UNDEFINED*
3442  *
3443  */
3444 /*
3445  * Field : EMAC ARCACHE - arcache_0
3446  *
3447  * Specifies the values of the 2 EMAC ARCACHE signals.
3448  *
3449  * The field array index corresponds to the EMAC index.
3450  *
3451  * Field Enumeration Values:
3452  *
3453  * Enum | Value | Description
3454  * :-------------------------------------------------------|:------|:-------------------------------------------------
3455  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3456  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only.
3457  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3458  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3459  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved.
3460  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved.
3461  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3462  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3463  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved.
3464  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved.
3465  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3466  * : | | only.
3467  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3468  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved.
3469  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved.
3470  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3471  * : | | and writes.
3472  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3473  * : | | writes.
3474  *
3475  * Field Access Macros:
3476  *
3477  */
3478 /*
3479  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3480  *
3481  * Noncacheable and nonbufferable.
3482  */
3483 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
3484 /*
3485  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3486  *
3487  * Bufferable only.
3488  */
3489 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1
3490 /*
3491  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3492  *
3493  * Cacheable, but do not allocate.
3494  */
3495 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
3496 /*
3497  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3498  *
3499  * Cacheable and bufferable, but do not allocate.
3500  */
3501 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3502 /*
3503  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3504  *
3505  * Reserved.
3506  */
3507 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4
3508 /*
3509  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3510  *
3511  * Reserved.
3512  */
3513 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5
3514 /*
3515  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3516  *
3517  * Cacheable write-through, allocate on reads only.
3518  */
3519 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3520 /*
3521  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3522  *
3523  * Cacheable write-back, allocate on reads only.
3524  */
3525 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3526 /*
3527  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3528  *
3529  * Reserved.
3530  */
3531 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8
3532 /*
3533  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3534  *
3535  * Reserved.
3536  */
3537 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9
3538 /*
3539  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3540  *
3541  * Cacheable write-through, allocate on writes only.
3542  */
3543 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3544 /*
3545  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3546  *
3547  * Cacheable write-back, allocate on writes only.
3548  */
3549 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3550 /*
3551  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3552  *
3553  * Reserved.
3554  */
3555 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc
3556 /*
3557  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3558  *
3559  * Reserved.
3560  */
3561 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd
3562 /*
3563  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3564  *
3565  * Cacheable write-through, allocate on both reads and writes.
3566  */
3567 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3568 /*
3569  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0
3570  *
3571  * Cacheable write-back, allocate on both reads and writes.
3572  */
3573 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3574 
3575 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3576 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0
3577 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3578 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3
3579 /* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3580 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4
3581 /* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */
3582 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f
3583 /* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value. */
3584 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
3585 /* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field. */
3586 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0
3587 /* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register. */
3588 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
3589 /* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register. */
3590 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
3591 
3592 /*
3593  * Field : EMAC ARCACHE - arcache_1
3594  *
3595  * Specifies the values of the 2 EMAC ARCACHE signals.
3596  *
3597  * The field array index corresponds to the EMAC index.
3598  *
3599  * Field Enumeration Values:
3600  *
3601  * Enum | Value | Description
3602  * :-------------------------------------------------------|:------|:-------------------------------------------------
3603  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3604  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF | 0x1 | Bufferable only.
3605  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3606  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3607  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 | 0x4 | Reserved.
3608  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 | 0x5 | Reserved.
3609  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3610  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3611  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 | 0x8 | Reserved.
3612  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 | 0x9 | Reserved.
3613  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3614  * : | | only.
3615  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3616  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 | 0xc | Reserved.
3617  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 | 0xd | Reserved.
3618  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3619  * : | | and writes.
3620  * ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3621  * : | | writes.
3622  *
3623  * Field Access Macros:
3624  *
3625  */
3626 /*
3627  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3628  *
3629  * Noncacheable and nonbufferable.
3630  */
3631 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0
3632 /*
3633  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3634  *
3635  * Bufferable only.
3636  */
3637 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1
3638 /*
3639  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3640  *
3641  * Cacheable, but do not allocate.
3642  */
3643 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2
3644 /*
3645  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3646  *
3647  * Cacheable and bufferable, but do not allocate.
3648  */
3649 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3650 /*
3651  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3652  *
3653  * Reserved.
3654  */
3655 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4
3656 /*
3657  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3658  *
3659  * Reserved.
3660  */
3661 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5
3662 /*
3663  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3664  *
3665  * Cacheable write-through, allocate on reads only.
3666  */
3667 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3668 /*
3669  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3670  *
3671  * Cacheable write-back, allocate on reads only.
3672  */
3673 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3674 /*
3675  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3676  *
3677  * Reserved.
3678  */
3679 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8
3680 /*
3681  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3682  *
3683  * Reserved.
3684  */
3685 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9
3686 /*
3687  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3688  *
3689  * Cacheable write-through, allocate on writes only.
3690  */
3691 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3692 /*
3693  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3694  *
3695  * Cacheable write-back, allocate on writes only.
3696  */
3697 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3698 /*
3699  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3700  *
3701  * Reserved.
3702  */
3703 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc
3704 /*
3705  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3706  *
3707  * Reserved.
3708  */
3709 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd
3710 /*
3711  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3712  *
3713  * Cacheable write-through, allocate on both reads and writes.
3714  */
3715 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
3716 /*
3717  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1
3718  *
3719  * Cacheable write-back, allocate on both reads and writes.
3720  */
3721 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
3722 
3723 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3724 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4
3725 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3726 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7
3727 /* The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3728 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4
3729 /* The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */
3730 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0
3731 /* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value. */
3732 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f
3733 /* The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field. */
3734 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0
3735 /* Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register. */
3736 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4)
3737 /* Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register. */
3738 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0)
3739 
3740 /*
3741  * Field : EMAC AWCACHE - awcache_0
3742  *
3743  * Specifies the values of the 2 EMAC AWCACHE signals.
3744  *
3745  * The field array index corresponds to the EMAC index.
3746  *
3747  * Field Enumeration Values:
3748  *
3749  * Enum | Value | Description
3750  * :-------------------------------------------------------|:------|:-------------------------------------------------
3751  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3752  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only.
3753  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3754  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3755  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved.
3756  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved.
3757  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3758  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3759  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved.
3760  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved.
3761  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3762  * : | | only.
3763  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3764  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved.
3765  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved.
3766  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3767  * : | | and writes.
3768  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3769  * : | | writes.
3770  *
3771  * Field Access Macros:
3772  *
3773  */
3774 /*
3775  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3776  *
3777  * Noncacheable and nonbufferable.
3778  */
3779 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
3780 /*
3781  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3782  *
3783  * Bufferable only.
3784  */
3785 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1
3786 /*
3787  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3788  *
3789  * Cacheable, but do not allocate.
3790  */
3791 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
3792 /*
3793  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3794  *
3795  * Cacheable and bufferable, but do not allocate.
3796  */
3797 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3798 /*
3799  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3800  *
3801  * Reserved.
3802  */
3803 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4
3804 /*
3805  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3806  *
3807  * Reserved.
3808  */
3809 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5
3810 /*
3811  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3812  *
3813  * Cacheable write-through, allocate on reads only.
3814  */
3815 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3816 /*
3817  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3818  *
3819  * Cacheable write-back, allocate on reads only.
3820  */
3821 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3822 /*
3823  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3824  *
3825  * Reserved.
3826  */
3827 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8
3828 /*
3829  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3830  *
3831  * Reserved.
3832  */
3833 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9
3834 /*
3835  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3836  *
3837  * Cacheable write-through, allocate on writes only.
3838  */
3839 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3840 /*
3841  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3842  *
3843  * Cacheable write-back, allocate on writes only.
3844  */
3845 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3846 /*
3847  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3848  *
3849  * Reserved.
3850  */
3851 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc
3852 /*
3853  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3854  *
3855  * Reserved.
3856  */
3857 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd
3858 /*
3859  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3860  *
3861  * Cacheable write-through, allocate on both reads and writes.
3862  */
3863 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3864 /*
3865  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0
3866  *
3867  * Cacheable write-back, allocate on both reads and writes.
3868  */
3869 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3870 
3871 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3872 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8
3873 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3874 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11
3875 /* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3876 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4
3877 /* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */
3878 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00
3879 /* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value. */
3880 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff
3881 /* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field. */
3882 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0
3883 /* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register. */
3884 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8)
3885 /* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register. */
3886 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00)
3887 
3888 /*
3889  * Field : EMAC AWCACHE - awcache_1
3890  *
3891  * Specifies the values of the 2 EMAC AWCACHE signals.
3892  *
3893  * The field array index corresponds to the EMAC index.
3894  *
3895  * Field Enumeration Values:
3896  *
3897  * Enum | Value | Description
3898  * :-------------------------------------------------------|:------|:-------------------------------------------------
3899  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
3900  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF | 0x1 | Bufferable only.
3901  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
3902  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
3903  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 | 0x4 | Reserved.
3904  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 | 0x5 | Reserved.
3905  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
3906  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
3907  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 | 0x8 | Reserved.
3908  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 | 0x9 | Reserved.
3909  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
3910  * : | | only.
3911  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
3912  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 | 0xc | Reserved.
3913  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 | 0xd | Reserved.
3914  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
3915  * : | | and writes.
3916  * ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
3917  * : | | writes.
3918  *
3919  * Field Access Macros:
3920  *
3921  */
3922 /*
3923  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3924  *
3925  * Noncacheable and nonbufferable.
3926  */
3927 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0
3928 /*
3929  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3930  *
3931  * Bufferable only.
3932  */
3933 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1
3934 /*
3935  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3936  *
3937  * Cacheable, but do not allocate.
3938  */
3939 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2
3940 /*
3941  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3942  *
3943  * Cacheable and bufferable, but do not allocate.
3944  */
3945 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3946 /*
3947  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3948  *
3949  * Reserved.
3950  */
3951 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4
3952 /*
3953  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3954  *
3955  * Reserved.
3956  */
3957 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5
3958 /*
3959  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3960  *
3961  * Cacheable write-through, allocate on reads only.
3962  */
3963 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3964 /*
3965  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3966  *
3967  * Cacheable write-back, allocate on reads only.
3968  */
3969 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3970 /*
3971  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3972  *
3973  * Reserved.
3974  */
3975 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8
3976 /*
3977  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3978  *
3979  * Reserved.
3980  */
3981 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9
3982 /*
3983  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3984  *
3985  * Cacheable write-through, allocate on writes only.
3986  */
3987 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3988 /*
3989  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3990  *
3991  * Cacheable write-back, allocate on writes only.
3992  */
3993 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3994 /*
3995  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
3996  *
3997  * Reserved.
3998  */
3999 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc
4000 /*
4001  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4002  *
4003  * Reserved.
4004  */
4005 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd
4006 /*
4007  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4008  *
4009  * Cacheable write-through, allocate on both reads and writes.
4010  */
4011 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
4012 /*
4013  * Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1
4014  *
4015  * Cacheable write-back, allocate on both reads and writes.
4016  */
4017 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
4018 
4019 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4020 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12
4021 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4022 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15
4023 /* The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4024 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4
4025 /* The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */
4026 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000
4027 /* The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value. */
4028 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff
4029 /* The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field. */
4030 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0
4031 /* Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register. */
4032 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12)
4033 /* Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register. */
4034 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000)
4035 
4036 #ifndef __ASSEMBLY__
4037 /*
4038  * WARNING: The C register and register group struct declarations are provided for
4039  * convenience and illustrative purposes. They should, however, be used with
4040  * caution as the C language standard provides no guarantees about the alignment or
4041  * atomicity of device memory accesses. The recommended practice for writing
4042  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4043  * alt_write_word() functions.
4044  *
4045  * The struct declaration for register ALT_SYSMGR_EMAC_L3MST.
4046  */
4047 struct ALT_SYSMGR_EMAC_L3MST_s
4048 {
4049  uint32_t arcache_0 : 4; /* EMAC ARCACHE */
4050  uint32_t arcache_1 : 4; /* EMAC ARCACHE */
4051  uint32_t awcache_0 : 4; /* EMAC AWCACHE */
4052  uint32_t awcache_1 : 4; /* EMAC AWCACHE */
4053  uint32_t : 16; /* *UNDEFINED* */
4054 };
4055 
4056 /* The typedef declaration for register ALT_SYSMGR_EMAC_L3MST. */
4057 typedef volatile struct ALT_SYSMGR_EMAC_L3MST_s ALT_SYSMGR_EMAC_L3MST_t;
4058 #endif /* __ASSEMBLY__ */
4059 
4060 /* The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component. */
4061 #define ALT_SYSMGR_EMAC_L3MST_OFST 0x4
4062 
4063 #ifndef __ASSEMBLY__
4064 /*
4065  * WARNING: The C register and register group struct declarations are provided for
4066  * convenience and illustrative purposes. They should, however, be used with
4067  * caution as the C language standard provides no guarantees about the alignment or
4068  * atomicity of device memory accesses. The recommended practice for writing
4069  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4070  * alt_write_word() functions.
4071  *
4072  * The struct declaration for register group ALT_SYSMGR_EMAC.
4073  */
4074 struct ALT_SYSMGR_EMAC_s
4075 {
4076  ALT_SYSMGR_EMAC_CTL_t ctrl; /* ALT_SYSMGR_EMAC_CTL */
4077  ALT_SYSMGR_EMAC_L3MST_t l3master; /* ALT_SYSMGR_EMAC_L3MST */
4078  volatile uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */
4079 };
4080 
4081 /* The typedef declaration for register group ALT_SYSMGR_EMAC. */
4082 typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t;
4083 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */
4084 struct ALT_SYSMGR_EMAC_raw_s
4085 {
4086  volatile uint32_t ctrl; /* ALT_SYSMGR_EMAC_CTL */
4087  volatile uint32_t l3master; /* ALT_SYSMGR_EMAC_L3MST */
4088  uint32_t _pad_0x8_0x10[2]; /* *UNDEFINED* */
4089 };
4090 
4091 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_EMAC. */
4092 typedef volatile struct ALT_SYSMGR_EMAC_raw_s ALT_SYSMGR_EMAC_raw_t;
4093 #endif /* __ASSEMBLY__ */
4094 
4095 
4096 /*
4097  * Register Group : DMA Controller Group - ALT_SYSMGR_DMA
4098  * DMA Controller Group
4099  *
4100  * Registers used by the DMA Controller to enable secured system support and select
4101  * DMA channels.
4102  *
4103  */
4104 /*
4105  * Register : Control Register - ctrl
4106  *
4107  * Registers used by the DMA Controller. All fields are reset by a cold or warm
4108  * reset.
4109  *
4110  * These register bits should be updated during system initialization prior to
4111  * removing the DMA controller from reset. They may not be changed dynamically
4112  * during DMA operation.
4113  *
4114  * Register Layout
4115  *
4116  * Bits | Access | Reset | Description
4117  * :--------|:-------|:------|:------------------------
4118  * [0] | RW | 0x0 | Channel Select
4119  * [1] | RW | 0x0 | Channel Select
4120  * [2] | RW | 0x0 | Channel Select
4121  * [3] | RW | 0x0 | Channel Select
4122  * [4] | RW | 0x0 | Manager Thread Security
4123  * [12:5] | RW | 0x0 | IRQ Security
4124  * [31:13] | ??? | 0x0 | *UNDEFINED*
4125  *
4126  */
4127 /*
4128  * Field : Channel Select - chansel_0
4129  *
4130  * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4131  * peripheral request interfaces.The peripheral request interface index equals the
4132  * array index + 4. For example, array index 0 is for peripheral request index 4.
4133  *
4134  * Field Enumeration Values:
4135  *
4136  * Enum | Value | Description
4137  * :------------------------------------|:------|:-----------------------------------------
4138  * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA | 0x0 | FPGA drives peripheral request interface
4139  * ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN | 0x1 | CAN drives peripheral request interface
4140  *
4141  * Field Access Macros:
4142  *
4143  */
4144 /*
4145  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
4146  *
4147  * FPGA drives peripheral request interface
4148  */
4149 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0
4150 /*
4151  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
4152  *
4153  * CAN drives peripheral request interface
4154  */
4155 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1
4156 
4157 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4158 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0
4159 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4160 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0
4161 /* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4162 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1
4163 /* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */
4164 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001
4165 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value. */
4166 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe
4167 /* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field. */
4168 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0
4169 /* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register. */
4170 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
4171 /* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register. */
4172 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
4173 
4174 /*
4175  * Field : Channel Select - chansel_1
4176  *
4177  * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4178  * peripheral request interfaces.The peripheral request interface index equals the
4179  * array index + 4. For example, array index 0 is for peripheral request index 4.
4180  *
4181  * Field Enumeration Values:
4182  *
4183  * Enum | Value | Description
4184  * :------------------------------------|:------|:-----------------------------------------
4185  * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA | 0x0 | FPGA drives peripheral request interface
4186  * ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN | 0x1 | CAN drives peripheral request interface
4187  *
4188  * Field Access Macros:
4189  *
4190  */
4191 /*
4192  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
4193  *
4194  * FPGA drives peripheral request interface
4195  */
4196 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0
4197 /*
4198  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
4199  *
4200  * CAN drives peripheral request interface
4201  */
4202 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1
4203 
4204 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4205 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1
4206 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4207 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1
4208 /* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4209 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1
4210 /* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */
4211 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002
4212 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value. */
4213 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd
4214 /* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field. */
4215 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0
4216 /* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register. */
4217 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1)
4218 /* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register. */
4219 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002)
4220 
4221 /*
4222  * Field : Channel Select - chansel_2
4223  *
4224  * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4225  * peripheral request interfaces.The peripheral request interface index equals the
4226  * array index + 4. For example, array index 0 is for peripheral request index 4.
4227  *
4228  * Field Enumeration Values:
4229  *
4230  * Enum | Value | Description
4231  * :------------------------------------|:------|:-----------------------------------------
4232  * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA | 0x0 | FPGA drives peripheral request interface
4233  * ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN | 0x1 | CAN drives peripheral request interface
4234  *
4235  * Field Access Macros:
4236  *
4237  */
4238 /*
4239  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
4240  *
4241  * FPGA drives peripheral request interface
4242  */
4243 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0
4244 /*
4245  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
4246  *
4247  * CAN drives peripheral request interface
4248  */
4249 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1
4250 
4251 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4252 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2
4253 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4254 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2
4255 /* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4256 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1
4257 /* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */
4258 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004
4259 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value. */
4260 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb
4261 /* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field. */
4262 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0
4263 /* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register. */
4264 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2)
4265 /* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register. */
4266 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004)
4267 
4268 /*
4269  * Field : Channel Select - chansel_3
4270  *
4271  * Controls mux that selects whether FPGA or CAN connects to one of the DMA
4272  * peripheral request interfaces.The peripheral request interface index equals the
4273  * array index + 4. For example, array index 0 is for peripheral request index 4.
4274  *
4275  * Field Enumeration Values:
4276  *
4277  * Enum | Value | Description
4278  * :------------------------------------|:------|:-----------------------------------------
4279  * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA | 0x0 | FPGA drives peripheral request interface
4280  * ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN | 0x1 | CAN drives peripheral request interface
4281  *
4282  * Field Access Macros:
4283  *
4284  */
4285 /*
4286  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
4287  *
4288  * FPGA drives peripheral request interface
4289  */
4290 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0
4291 /*
4292  * Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
4293  *
4294  * CAN drives peripheral request interface
4295  */
4296 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1
4297 
4298 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4299 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3
4300 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4301 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3
4302 /* The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4303 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1
4304 /* The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */
4305 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008
4306 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value. */
4307 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7
4308 /* The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field. */
4309 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0
4310 /* Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register. */
4311 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3)
4312 /* Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register. */
4313 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008)
4314 
4315 /*
4316  * Field : Manager Thread Security - mgrnonsecure
4317  *
4318  * Specifies the security state of the DMA manager thread.
4319  *
4320  * 0 = assigns DMA manager to the Secure state.
4321  *
4322  * 1 = assigns DMA manager to the Non-secure state.
4323  *
4324  * Sampled by the DMA controller when it exits from reset.
4325  *
4326  * Field Access Macros:
4327  *
4328  */
4329 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4330 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4
4331 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4332 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4
4333 /* The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4334 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1
4335 /* The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */
4336 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010
4337 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value. */
4338 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef
4339 /* The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field. */
4340 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0
4341 /* Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register. */
4342 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4)
4343 /* Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register. */
4344 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010)
4345 
4346 /*
4347  * Field : IRQ Security - irqnonsecure
4348  *
4349  * Specifies the security state of an event-interrupt resource.
4350  *
4351  * If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state.
4352  *
4353  * If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure
4354  * state.
4355  *
4356  * Field Access Macros:
4357  *
4358  */
4359 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4360 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5
4361 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4362 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12
4363 /* The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4364 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8
4365 /* The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */
4366 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0
4367 /* The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value. */
4368 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f
4369 /* The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field. */
4370 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0
4371 /* Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register. */
4372 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5)
4373 /* Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register. */
4374 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0)
4375 
4376 #ifndef __ASSEMBLY__
4377 /*
4378  * WARNING: The C register and register group struct declarations are provided for
4379  * convenience and illustrative purposes. They should, however, be used with
4380  * caution as the C language standard provides no guarantees about the alignment or
4381  * atomicity of device memory accesses. The recommended practice for writing
4382  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4383  * alt_write_word() functions.
4384  *
4385  * The struct declaration for register ALT_SYSMGR_DMA_CTL.
4386  */
4387 struct ALT_SYSMGR_DMA_CTL_s
4388 {
4389  uint32_t chansel_0 : 1; /* Channel Select */
4390  uint32_t chansel_1 : 1; /* Channel Select */
4391  uint32_t chansel_2 : 1; /* Channel Select */
4392  uint32_t chansel_3 : 1; /* Channel Select */
4393  uint32_t mgrnonsecure : 1; /* Manager Thread Security */
4394  uint32_t irqnonsecure : 8; /* IRQ Security */
4395  uint32_t : 19; /* *UNDEFINED* */
4396 };
4397 
4398 /* The typedef declaration for register ALT_SYSMGR_DMA_CTL. */
4399 typedef volatile struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t;
4400 #endif /* __ASSEMBLY__ */
4401 
4402 /* The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component. */
4403 #define ALT_SYSMGR_DMA_CTL_OFST 0x0
4404 
4405 /*
4406  * Register : Peripheral Security Register - persecurity
4407  *
4408  * Controls the security state of a peripheral request interface. Sampled by the
4409  * DMA controller when it exits from reset.
4410  *
4411  * These register bits should be updated during system initialization prior to
4412  * removing the DMA controller from reset. They may not be changed dynamically
4413  * during DMA operation.
4414  *
4415  * Register Layout
4416  *
4417  * Bits | Access | Reset | Description
4418  * :-------|:-------|:------|:----------------------
4419  * [31:0] | RW | 0x0 | Peripheral Non-Secure
4420  *
4421  */
4422 /*
4423  * Field : Peripheral Non-Secure - nonsecure
4424  *
4425  * If bit index [x] is 0, the DMA controller assigns peripheral request interface x
4426  * to the Secure state.
4427  *
4428  * If bit index [x] is 1, the DMA controller assigns peripheral request interface x
4429  * to the Non-secure state.
4430  *
4431  * Reset by a cold or warm reset.
4432  *
4433  * Field Access Macros:
4434  *
4435  */
4436 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4437 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0
4438 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4439 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31
4440 /* The width in bits of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4441 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32
4442 /* The mask used to set the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */
4443 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff
4444 /* The mask used to clear the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value. */
4445 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000
4446 /* The reset value of the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field. */
4447 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0
4448 /* Extracts the ALT_SYSMGR_DMA_PERSECURITY_NONSECURE field value from a register. */
4449 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0)
4450 /* Produces a ALT_SYSMGR_DMA_PERSECURITY_NONSECURE register field value suitable for setting the register. */
4451 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff)
4452 
4453 #ifndef __ASSEMBLY__
4454 /*
4455  * WARNING: The C register and register group struct declarations are provided for
4456  * convenience and illustrative purposes. They should, however, be used with
4457  * caution as the C language standard provides no guarantees about the alignment or
4458  * atomicity of device memory accesses. The recommended practice for writing
4459  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4460  * alt_write_word() functions.
4461  *
4462  * The struct declaration for register ALT_SYSMGR_DMA_PERSECURITY.
4463  */
4464 struct ALT_SYSMGR_DMA_PERSECURITY_s
4465 {
4466  uint32_t nonsecure : 32; /* Peripheral Non-Secure */
4467 };
4468 
4469 /* The typedef declaration for register ALT_SYSMGR_DMA_PERSECURITY. */
4470 typedef volatile struct ALT_SYSMGR_DMA_PERSECURITY_s ALT_SYSMGR_DMA_PERSECURITY_t;
4471 #endif /* __ASSEMBLY__ */
4472 
4473 /* The byte offset of the ALT_SYSMGR_DMA_PERSECURITY register from the beginning of the component. */
4474 #define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4
4475 
4476 #ifndef __ASSEMBLY__
4477 /*
4478  * WARNING: The C register and register group struct declarations are provided for
4479  * convenience and illustrative purposes. They should, however, be used with
4480  * caution as the C language standard provides no guarantees about the alignment or
4481  * atomicity of device memory accesses. The recommended practice for writing
4482  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4483  * alt_write_word() functions.
4484  *
4485  * The struct declaration for register group ALT_SYSMGR_DMA.
4486  */
4487 struct ALT_SYSMGR_DMA_s
4488 {
4489  ALT_SYSMGR_DMA_CTL_t ctrl; /* ALT_SYSMGR_DMA_CTL */
4490  ALT_SYSMGR_DMA_PERSECURITY_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */
4491 };
4492 
4493 /* The typedef declaration for register group ALT_SYSMGR_DMA. */
4494 typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
4495 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_DMA. */
4496 struct ALT_SYSMGR_DMA_raw_s
4497 {
4498  volatile uint32_t ctrl; /* ALT_SYSMGR_DMA_CTL */
4499  volatile uint32_t persecurity; /* ALT_SYSMGR_DMA_PERSECURITY */
4500 };
4501 
4502 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_DMA. */
4503 typedef volatile struct ALT_SYSMGR_DMA_raw_s ALT_SYSMGR_DMA_raw_t;
4504 #endif /* __ASSEMBLY__ */
4505 
4506 
4507 /*
4508  * Register Group : Preloader (initial software) Group - ALT_SYSMGR_ISW
4509  * Preloader (initial software) Group
4510  *
4511  * Registers used by preloader code and the OS.
4512  *
4513  * All registers are only reset by a cold reset (ignore warm reset).
4514  *
4515  */
4516 /*
4517  * Register : Preloader to OS Handoff Information - handoff
4518  *
4519  * These registers are used to store handoff infomation between the preloader and
4520  * the OS. These 8 registers can be used to store any information. The contents of
4521  * these registers have no impact on the state of the HPS hardware.
4522  *
4523  * Register Layout
4524  *
4525  * Bits | Access | Reset | Description
4526  * :-------|:-------|:------|:------------------------------
4527  * [31:0] | RW | 0x0 | Preloader Handoff Information
4528  *
4529  */
4530 /*
4531  * Field : Preloader Handoff Information - value
4532  *
4533  * Preloader Handoff Information.
4534  *
4535  * Field Access Macros:
4536  *
4537  */
4538 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4539 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0
4540 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4541 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31
4542 /* The width in bits of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4543 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32
4544 /* The mask used to set the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */
4545 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff
4546 /* The mask used to clear the ALT_SYSMGR_ISW_HANDOFF_VALUE register field value. */
4547 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000
4548 /* The reset value of the ALT_SYSMGR_ISW_HANDOFF_VALUE register field. */
4549 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0
4550 /* Extracts the ALT_SYSMGR_ISW_HANDOFF_VALUE field value from a register. */
4551 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4552 /* Produces a ALT_SYSMGR_ISW_HANDOFF_VALUE register field value suitable for setting the register. */
4553 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4554 
4555 #ifndef __ASSEMBLY__
4556 /*
4557  * WARNING: The C register and register group struct declarations are provided for
4558  * convenience and illustrative purposes. They should, however, be used with
4559  * caution as the C language standard provides no guarantees about the alignment or
4560  * atomicity of device memory accesses. The recommended practice for writing
4561  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4562  * alt_write_word() functions.
4563  *
4564  * The struct declaration for register ALT_SYSMGR_ISW_HANDOFF.
4565  */
4566 struct ALT_SYSMGR_ISW_HANDOFF_s
4567 {
4568  uint32_t value : 32; /* Preloader Handoff Information */
4569 };
4570 
4571 /* The typedef declaration for register ALT_SYSMGR_ISW_HANDOFF. */
4572 typedef volatile struct ALT_SYSMGR_ISW_HANDOFF_s ALT_SYSMGR_ISW_HANDOFF_t;
4573 #endif /* __ASSEMBLY__ */
4574 
4575 /* The byte offset of the ALT_SYSMGR_ISW_HANDOFF register from the beginning of the component. */
4576 #define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0
4577 
4578 #ifndef __ASSEMBLY__
4579 /*
4580  * WARNING: The C register and register group struct declarations are provided for
4581  * convenience and illustrative purposes. They should, however, be used with
4582  * caution as the C language standard provides no guarantees about the alignment or
4583  * atomicity of device memory accesses. The recommended practice for writing
4584  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4585  * alt_write_word() functions.
4586  *
4587  * The struct declaration for register group ALT_SYSMGR_ISW.
4588  */
4589 struct ALT_SYSMGR_ISW_s
4590 {
4591  ALT_SYSMGR_ISW_HANDOFF_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */
4592 };
4593 
4594 /* The typedef declaration for register group ALT_SYSMGR_ISW. */
4595 typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t;
4596 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ISW. */
4597 struct ALT_SYSMGR_ISW_raw_s
4598 {
4599  volatile uint32_t handoff[8]; /* ALT_SYSMGR_ISW_HANDOFF */
4600 };
4601 
4602 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ISW. */
4603 typedef volatile struct ALT_SYSMGR_ISW_raw_s ALT_SYSMGR_ISW_raw_t;
4604 #endif /* __ASSEMBLY__ */
4605 
4606 
4607 /*
4608  * Register Group : Boot ROM Code Register Group - ALT_SYSMGR_ROMCODE
4609  * Boot ROM Code Register Group
4610  *
4611  * Registers used by the Boot ROM code. All fields are only reset by a cold reset
4612  * (ignore warm reset).
4613  *
4614  */
4615 /*
4616  * Register : Control Register - ctrl
4617  *
4618  * Contains information used to control Boot ROM code.
4619  *
4620  * Register Layout
4621  *
4622  * Bits | Access | Reset | Description
4623  * :-------|:-------|:------|:-------------------------------------------
4624  * [0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins
4625  * [1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins
4626  * [31:2] | ??? | 0x0 | *UNDEFINED*
4627  *
4628  */
4629 /*
4630  * Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux
4631  *
4632  * Specifies whether the Boot ROM code configures the pin mux for boot pins after a
4633  * warm reset. Note that the Boot ROM code always configures the pin mux for boot
4634  * pins after a cold reset. After the Boot ROM code configures the pin mux for boot
4635  * pins, it always disables this field. It is up to user software to enable this
4636  * field if it wants a different behavior.
4637  *
4638  * Field Enumeration Values:
4639  *
4640  * Enum | Value | Description
4641  * :-----------------------------------------------|:------|:----------------------------------------------
4642  * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | Boot ROM code will not configure pin mux for
4643  * : | | boot pins after a warm reset
4644  * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Boot ROM code will configure pin mux for boot
4645  * : | | pins after a warm reset
4646  *
4647  * Field Access Macros:
4648  *
4649  */
4650 /*
4651  * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX
4652  *
4653  * Boot ROM code will not configure pin mux for boot pins after a warm reset
4654  */
4655 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
4656 /*
4657  * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX
4658  *
4659  * Boot ROM code will configure pin mux for boot pins after a warm reset
4660  */
4661 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
4662 
4663 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4664 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
4665 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4666 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
4667 /* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4668 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
4669 /* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
4670 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
4671 /* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value. */
4672 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
4673 /* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field. */
4674 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
4675 /* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register. */
4676 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
4677 /* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register. */
4678 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
4679 
4680 /*
4681  * Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio
4682  *
4683  * Specifies whether the Boot ROM code configures the IOs used by boot after a warm
4684  * reset. Note that the Boot ROM code always configures the IOs used by boot after
4685  * a cold reset. After the Boot ROM code configures the IOs used by boot, it always
4686  * disables this field. It is up to user software to enable this field if it wants
4687  * a different behavior.
4688  *
4689  * Field Enumeration Values:
4690  *
4691  * Enum | Value | Description
4692  * :-------------------------------------------|:------|:----------------------------------------------
4693  * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | Boot ROM code will not configure IOs used by
4694  * : | | boot after a warm reset
4695  * ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Boot ROM code will configure IOs used by boot
4696  * : | | after a warm reset
4697  *
4698  * Field Access Macros:
4699  *
4700  */
4701 /*
4702  * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO
4703  *
4704  * Boot ROM code will not configure IOs used by boot after a warm reset
4705  */
4706 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
4707 /*
4708  * Enumerated value for register field ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO
4709  *
4710  * Boot ROM code will configure IOs used by boot after a warm reset
4711  */
4712 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
4713 
4714 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4715 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
4716 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4717 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
4718 /* The width in bits of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4719 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
4720 /* The mask used to set the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */
4721 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
4722 /* The mask used to clear the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value. */
4723 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
4724 /* The reset value of the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field. */
4725 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
4726 /* Extracts the ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO field value from a register. */
4727 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
4728 /* Produces a ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register. */
4729 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
4730 
4731 #ifndef __ASSEMBLY__
4732 /*
4733  * WARNING: The C register and register group struct declarations are provided for
4734  * convenience and illustrative purposes. They should, however, be used with
4735  * caution as the C language standard provides no guarantees about the alignment or
4736  * atomicity of device memory accesses. The recommended practice for writing
4737  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4738  * alt_write_word() functions.
4739  *
4740  * The struct declaration for register ALT_SYSMGR_ROMCODE_CTL.
4741  */
4742 struct ALT_SYSMGR_ROMCODE_CTL_s
4743 {
4744  uint32_t warmrstcfgpinmux : 1; /* Warm Reset Configure Pin Mux for Boot Pins */
4745  uint32_t warmrstcfgio : 1; /* Warm Reset Configure IOs for Boot Pins */
4746  uint32_t : 30; /* *UNDEFINED* */
4747 };
4748 
4749 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_CTL. */
4750 typedef volatile struct ALT_SYSMGR_ROMCODE_CTL_s ALT_SYSMGR_ROMCODE_CTL_t;
4751 #endif /* __ASSEMBLY__ */
4752 
4753 /* The byte offset of the ALT_SYSMGR_ROMCODE_CTL register from the beginning of the component. */
4754 #define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0
4755 
4756 /*
4757  * Register : CPU1 Start Address Register - cpu1startaddr
4758  *
4759  * When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset
4760  * exception address (the typical case), the Boot ROM reset handler code reads the
4761  * address stored in this register and jumps it to hand off execution to user
4762  * software.
4763  *
4764  * Register Layout
4765  *
4766  * Bits | Access | Reset | Description
4767  * :-------|:-------|:------|:------------
4768  * [31:0] | RW | 0x0 | Address
4769  *
4770  */
4771 /*
4772  * Field : Address - value
4773  *
4774  * Address for CPU1 to start executing at after coming out of reset.
4775  *
4776  * Field Access Macros:
4777  *
4778  */
4779 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4780 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0
4781 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4782 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31
4783 /* The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4784 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32
4785 /* The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */
4786 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff
4787 /* The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value. */
4788 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000
4789 /* The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field. */
4790 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0
4791 /* Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register. */
4792 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4793 /* Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register. */
4794 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4795 
4796 #ifndef __ASSEMBLY__
4797 /*
4798  * WARNING: The C register and register group struct declarations are provided for
4799  * convenience and illustrative purposes. They should, however, be used with
4800  * caution as the C language standard provides no guarantees about the alignment or
4801  * atomicity of device memory accesses. The recommended practice for writing
4802  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4803  * alt_write_word() functions.
4804  *
4805  * The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR.
4806  */
4807 struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s
4808 {
4809  uint32_t value : 32; /* Address */
4810 };
4811 
4812 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR. */
4813 typedef volatile struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t;
4814 #endif /* __ASSEMBLY__ */
4815 
4816 /* The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component. */
4817 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4
4818 
4819 /*
4820  * Register : Preloader (initial software) State Register - initswstate
4821  *
4822  * The preloader software (loaded by the Boot ROM) writes the magic value
4823  * 0x49535756 (ISWV in ASCII) to this register when it has reached a valid state.
4824  *
4825  * Register Layout
4826  *
4827  * Bits | Access | Reset | Description
4828  * :-------|:-------|:------|:------------
4829  * [31:0] | RW | 0x0 | Value
4830  *
4831  */
4832 /*
4833  * Field : Value - value
4834  *
4835  * Written with magic value.
4836  *
4837  * Field Enumeration Values:
4838  *
4839  * Enum | Value | Description
4840  * :-----------------------------------------------|:-----------|:------------
4841  * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID | 0x0 |
4842  * ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID | 0x49535756 |
4843  *
4844  * Field Access Macros:
4845  *
4846  */
4847 /*
4848  * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE
4849  *
4850  */
4851 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
4852 /*
4853  * Enumerated value for register field ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE
4854  *
4855  */
4856 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
4857 
4858 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4859 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0
4860 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4861 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31
4862 /* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4863 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
4864 /* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */
4865 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
4866 /* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value. */
4867 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
4868 /* The reset value of the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field. */
4869 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
4870 /* Extracts the ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE field value from a register. */
4871 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4872 /* Produces a ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE register field value suitable for setting the register. */
4873 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4874 
4875 #ifndef __ASSEMBLY__
4876 /*
4877  * WARNING: The C register and register group struct declarations are provided for
4878  * convenience and illustrative purposes. They should, however, be used with
4879  * caution as the C language standard provides no guarantees about the alignment or
4880  * atomicity of device memory accesses. The recommended practice for writing
4881  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4882  * alt_write_word() functions.
4883  *
4884  * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE.
4885  */
4886 struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s
4887 {
4888  uint32_t value : 32; /* Value */
4889 };
4890 
4891 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWSTATE. */
4892 typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWSTATE_s ALT_SYSMGR_ROMCODE_INITSWSTATE_t;
4893 #endif /* __ASSEMBLY__ */
4894 
4895 /* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWSTATE register from the beginning of the component. */
4896 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8
4897 
4898 /*
4899  * Register : Preloader (initial software) Last Image Loaded Register - initswlastld
4900  *
4901  * Contains the index of the last preloader software image loaded by the Boot ROM
4902  * from the boot device.
4903  *
4904  * Register Layout
4905  *
4906  * Bits | Access | Reset | Description
4907  * :-------|:-------|:------|:------------
4908  * [1:0] | RW | 0x0 | Index
4909  * [31:2] | ??? | 0x0 | *UNDEFINED*
4910  *
4911  */
4912 /*
4913  * Field : Index - index
4914  *
4915  * Index of last image loaded.
4916  *
4917  * Field Access Macros:
4918  *
4919  */
4920 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4921 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0
4922 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4923 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1
4924 /* The width in bits of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4925 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
4926 /* The mask used to set the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */
4927 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
4928 /* The mask used to clear the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value. */
4929 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
4930 /* The reset value of the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field. */
4931 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
4932 /* Extracts the ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX field value from a register. */
4933 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
4934 /* Produces a ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX register field value suitable for setting the register. */
4935 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
4936 
4937 #ifndef __ASSEMBLY__
4938 /*
4939  * WARNING: The C register and register group struct declarations are provided for
4940  * convenience and illustrative purposes. They should, however, be used with
4941  * caution as the C language standard provides no guarantees about the alignment or
4942  * atomicity of device memory accesses. The recommended practice for writing
4943  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
4944  * alt_write_word() functions.
4945  *
4946  * The struct declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD.
4947  */
4948 struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s
4949 {
4950  uint32_t index : 2; /* Index */
4951  uint32_t : 30; /* *UNDEFINED* */
4952 };
4953 
4954 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_INITSWLASTLD. */
4955 typedef volatile struct ALT_SYSMGR_ROMCODE_INITSWLASTLD_s ALT_SYSMGR_ROMCODE_INITSWLASTLD_t;
4956 #endif /* __ASSEMBLY__ */
4957 
4958 /* The byte offset of the ALT_SYSMGR_ROMCODE_INITSWLASTLD register from the beginning of the component. */
4959 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc
4960 
4961 /*
4962  * Register : Boot ROM Software State Register - bootromswstate
4963  *
4964  * 32-bits general purpose register used by the Boot ROM code. Actual usage is
4965  * defined in the Boot ROM source code.
4966  *
4967  * Register Layout
4968  *
4969  * Bits | Access | Reset | Description
4970  * :-------|:-------|:------|:------------------------
4971  * [31:0] | RW | 0x0 | Boot ROM Software State
4972  *
4973  */
4974 /*
4975  * Field : Boot ROM Software State - value
4976  *
4977  * Reserved for Boot ROM use.
4978  *
4979  * Field Access Macros:
4980  *
4981  */
4982 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4983 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
4984 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4985 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
4986 /* The width in bits of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4987 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
4988 /* The mask used to set the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
4989 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
4990 /* The mask used to clear the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value. */
4991 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
4992 /* The reset value of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field. */
4993 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
4994 /* Extracts the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE field value from a register. */
4995 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4996 /* Produces a ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE register field value suitable for setting the register. */
4997 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4998 
4999 #ifndef __ASSEMBLY__
5000 /*
5001  * WARNING: The C register and register group struct declarations are provided for
5002  * convenience and illustrative purposes. They should, however, be used with
5003  * caution as the C language standard provides no guarantees about the alignment or
5004  * atomicity of device memory accesses. The recommended practice for writing
5005  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5006  * alt_write_word() functions.
5007  *
5008  * The struct declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE.
5009  */
5010 struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s
5011 {
5012  uint32_t value : 32; /* Boot ROM Software State */
5013 };
5014 
5015 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE. */
5016 typedef volatile struct ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_s ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t;
5017 #endif /* __ASSEMBLY__ */
5018 
5019 /* The byte offset of the ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE register from the beginning of the component. */
5020 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10
5021 
5022 /*
5023  * Register Group : Warm Boot from On-Chip RAM Group - ALT_SYSMGR_ROMCODE_WARMRAM
5024  * Warm Boot from On-Chip RAM Group
5025  *
5026  * Registers used by the Boot ROM code to support booting from the On-chip RAM on a
5027  * warm reset. All these registers must be written by user software before a warm
5028  * reset occurs to make use of this feature.
5029  *
5030  */
5031 /*
5032  * Register : Enable Register - enable
5033  *
5034  * Enables or disables the warm reset from On-chip RAM feature.
5035  *
5036  * Register Layout
5037  *
5038  * Bits | Access | Reset | Description
5039  * :-------|:-------|:------|:----------------------------
5040  * [31:0] | RW | 0x0 | Warm Reset from On-chip RAM
5041  *
5042  */
5043 /*
5044  * Field : Warm Reset from On-chip RAM - magic
5045  *
5046  * Controls whether Boot ROM will attempt to boot from the contents of the On-chip
5047  * RAM on a warm reset. When this feature is enabled, the Boot ROM code will not
5048  * configure boot IOs, the pin mux, or clocks.
5049  *
5050  * Note that the enable value is a 32-bit magic value (provided by the enum).
5051  *
5052  * Field Enumeration Values:
5053  *
5054  * Enum | Value | Description
5055  * :-------------------------------------------|:-----------|:------------------------------------------------
5056  * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD | 0x0 | Boot ROM code will not attempt to boot from On-
5057  * : | | chip RAM on a warm reset
5058  * ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END | 0xae9efebc | Boot ROM code will attempt to boot from On-chip
5059  * : | | RAM on a warm reset
5060  *
5061  * Field Access Macros:
5062  *
5063  */
5064 /*
5065  * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC
5066  *
5067  * Boot ROM code will not attempt to boot from On-chip RAM on a warm reset
5068  */
5069 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0
5070 /*
5071  * Enumerated value for register field ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC
5072  *
5073  * Boot ROM code will attempt to boot from On-chip RAM on a warm reset
5074  */
5075 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc
5076 
5077 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5078 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0
5079 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5080 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31
5081 /* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5082 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32
5083 /* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */
5084 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
5085 /* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value. */
5086 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
5087 /* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field. */
5088 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0
5089 /* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC field value from a register. */
5090 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
5091 /* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC register field value suitable for setting the register. */
5092 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
5093 
5094 #ifndef __ASSEMBLY__
5095 /*
5096  * WARNING: The C register and register group struct declarations are provided for
5097  * convenience and illustrative purposes. They should, however, be used with
5098  * caution as the C language standard provides no guarantees about the alignment or
5099  * atomicity of device memory accesses. The recommended practice for writing
5100  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5101  * alt_write_word() functions.
5102  *
5103  * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN.
5104  */
5105 struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s
5106 {
5107  uint32_t magic : 32; /* Warm Reset from On-chip RAM */
5108 };
5109 
5110 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EN. */
5111 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EN_s ALT_SYSMGR_ROMCODE_WARMRAM_EN_t;
5112 #endif /* __ASSEMBLY__ */
5113 
5114 /* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register from the beginning of the component. */
5115 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0
5116 /* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EN register. */
5117 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST))
5118 
5119 /*
5120  * Register : Data Start Register - datastart
5121  *
5122  * Offset into On-chip RAM of the start of the region for CRC validation
5123  *
5124  * Register Layout
5125  *
5126  * Bits | Access | Reset | Description
5127  * :--------|:-------|:------|:------------------
5128  * [15:0] | RW | 0x0 | Data Start Offset
5129  * [31:16] | ??? | 0x0 | *UNDEFINED*
5130  *
5131  */
5132 /*
5133  * Field : Data Start Offset - offset
5134  *
5135  * Contains the byte offset into the On-chip RAM of the start of the On-chip RAM
5136  * region for the warm boot CRC validation. The offset must be an integer multiple
5137  * of 4 (i.e. aligned to a word). The Boot ROM code will set the top 16 bits to
5138  * 0xFFFF and clear the bottom 2 bits.
5139  *
5140  * Field Access Macros:
5141  *
5142  */
5143 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5144 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0
5145 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5146 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15
5147 /* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5148 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16
5149 /* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */
5150 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff
5151 /* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value. */
5152 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000
5153 /* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field. */
5154 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0
5155 /* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET field value from a register. */
5156 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5157 /* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET register field value suitable for setting the register. */
5158 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5159 
5160 #ifndef __ASSEMBLY__
5161 /*
5162  * WARNING: The C register and register group struct declarations are provided for
5163  * convenience and illustrative purposes. They should, however, be used with
5164  * caution as the C language standard provides no guarantees about the alignment or
5165  * atomicity of device memory accesses. The recommended practice for writing
5166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5167  * alt_write_word() functions.
5168  *
5169  * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART.
5170  */
5171 struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s
5172 {
5173  uint32_t offset : 16; /* Data Start Offset */
5174  uint32_t : 16; /* *UNDEFINED* */
5175 };
5176 
5177 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART. */
5178 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_s ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t;
5179 #endif /* __ASSEMBLY__ */
5180 
5181 /* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register from the beginning of the component. */
5182 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4
5183 /* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART register. */
5184 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST))
5185 
5186 /*
5187  * Register : Length Register - length
5188  *
5189  * Length of region in On-chip RAM for CRC validation.
5190  *
5191  * Register Layout
5192  *
5193  * Bits | Access | Reset | Description
5194  * :--------|:-------|:------|:------------
5195  * [15:0] | RW | 0x0 | Size
5196  * [31:16] | ??? | 0x0 | *UNDEFINED*
5197  *
5198  */
5199 /*
5200  * Field : Size - size
5201  *
5202  * Contains the length (in bytes) of the region in the On-chip RAM for the warm
5203  * boot CRC validation.
5204  *
5205  * If the length is 0, the Boot ROM won't perform CRC calculation and CRC check to
5206  * avoid overhead caused by CRC validation.
5207  *
5208  * If the START + LENGTH exceeds the maximum offset into the On-chip RAM, the Boot
5209  * ROM won't boot from the On-chip RAM.
5210  *
5211  * The length must be an integer multiple of 4.
5212  *
5213  * The Boot ROM code will clear the top 16 bits and the bottom 2 bits.
5214  *
5215  * Field Access Macros:
5216  *
5217  */
5218 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5219 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0
5220 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5221 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15
5222 /* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5223 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16
5224 /* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */
5225 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff
5226 /* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value. */
5227 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000
5228 /* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field. */
5229 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0
5230 /* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE field value from a register. */
5231 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
5232 /* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE register field value suitable for setting the register. */
5233 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
5234 
5235 #ifndef __ASSEMBLY__
5236 /*
5237  * WARNING: The C register and register group struct declarations are provided for
5238  * convenience and illustrative purposes. They should, however, be used with
5239  * caution as the C language standard provides no guarantees about the alignment or
5240  * atomicity of device memory accesses. The recommended practice for writing
5241  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5242  * alt_write_word() functions.
5243  *
5244  * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN.
5245  */
5246 struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s
5247 {
5248  uint32_t size : 16; /* Size */
5249  uint32_t : 16; /* *UNDEFINED* */
5250 };
5251 
5252 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_LEN. */
5253 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_LEN_s ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t;
5254 #endif /* __ASSEMBLY__ */
5255 
5256 /* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register from the beginning of the component. */
5257 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8
5258 /* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_LEN register. */
5259 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST))
5260 
5261 /*
5262  * Register : Execution Register - execution
5263  *
5264  * Offset into On-chip RAM to enter to on a warm boot.
5265  *
5266  * Register Layout
5267  *
5268  * Bits | Access | Reset | Description
5269  * :--------|:-------|:------|:-----------------
5270  * [15:0] | RW | 0x0 | Execution Offset
5271  * [31:16] | ??? | 0x0 | *UNDEFINED*
5272  *
5273  */
5274 /*
5275  * Field : Execution Offset - offset
5276  *
5277  * Contains the byte offset into the On-chip RAM that the Boot ROM will jump to if
5278  * the CRC validation succeeds.
5279  *
5280  * The Boot ROM code will set the top 16 bits to 0xFFFF.
5281  *
5282  * Field Access Macros:
5283  *
5284  */
5285 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5286 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0
5287 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5288 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15
5289 /* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5290 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16
5291 /* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */
5292 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff
5293 /* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value. */
5294 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000
5295 /* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field. */
5296 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0
5297 /* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET field value from a register. */
5298 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5299 /* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET register field value suitable for setting the register. */
5300 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5301 
5302 #ifndef __ASSEMBLY__
5303 /*
5304  * WARNING: The C register and register group struct declarations are provided for
5305  * convenience and illustrative purposes. They should, however, be used with
5306  * caution as the C language standard provides no guarantees about the alignment or
5307  * atomicity of device memory accesses. The recommended practice for writing
5308  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5309  * alt_write_word() functions.
5310  *
5311  * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION.
5312  */
5313 struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s
5314 {
5315  uint32_t offset : 16; /* Execution Offset */
5316  uint32_t : 16; /* *UNDEFINED* */
5317 };
5318 
5319 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION. */
5320 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_s ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t;
5321 #endif /* __ASSEMBLY__ */
5322 
5323 /* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register from the beginning of the component. */
5324 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc
5325 /* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION register. */
5326 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST))
5327 
5328 /*
5329  * Register : Expected CRC Register - crc
5330  *
5331  * Length of region in On-chip RAM for CRC validation.
5332  *
5333  * Register Layout
5334  *
5335  * Bits | Access | Reset | Description
5336  * :-------|:-------|:-----------|:-------------
5337  * [31:0] | RW | 0xe763552a | Expected CRC
5338  *
5339  */
5340 /*
5341  * Field : Expected CRC - expected
5342  *
5343  * Contains the expected CRC of the region in the On-chip RAM.The Boot ROM code
5344  * calculates the actual CRC for all bytes in the region specified by the DATA
5345  * START an LENGTH registers. The contents of the EXECUTION register (after it has
5346  * been read and modified by the Boot ROM code) is also included in the CRC
5347  * calculation. The contents of the EXECUTION register is added to the CRC
5348  * accumulator a byte at a time starting with the least significant byte. If the
5349  * actual CRC doesn't match the expected CRC value in this register, the Boot ROM
5350  * won't boot from the On-chip RAM.
5351  *
5352  * The CRC is a standard CRC32 with the polynomial:
5353  *
5354  * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 +
5355  * x^2 + x + 1
5356  *
5357  * There is no reflection of the bits and the initial value of the remainder is
5358  * 0xFFFFFFFF and the final value is exclusive ORed with 0xFFFFFFFF.
5359  *
5360  * Field Access Macros:
5361  *
5362  */
5363 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5364 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0
5365 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5366 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31
5367 /* The width in bits of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5368 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32
5369 /* The mask used to set the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */
5370 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
5371 /* The mask used to clear the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value. */
5372 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
5373 /* The reset value of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field. */
5374 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a
5375 /* Extracts the ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED field value from a register. */
5376 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
5377 /* Produces a ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED register field value suitable for setting the register. */
5378 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
5379 
5380 #ifndef __ASSEMBLY__
5381 /*
5382  * WARNING: The C register and register group struct declarations are provided for
5383  * convenience and illustrative purposes. They should, however, be used with
5384  * caution as the C language standard provides no guarantees about the alignment or
5385  * atomicity of device memory accesses. The recommended practice for writing
5386  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5387  * alt_write_word() functions.
5388  *
5389  * The struct declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC.
5390  */
5391 struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s
5392 {
5393  uint32_t expected : 32; /* Expected CRC */
5394 };
5395 
5396 /* The typedef declaration for register ALT_SYSMGR_ROMCODE_WARMRAM_CRC. */
5397 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_CRC_s ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t;
5398 #endif /* __ASSEMBLY__ */
5399 
5400 /* The byte offset of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register from the beginning of the component. */
5401 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10
5402 /* The address of the ALT_SYSMGR_ROMCODE_WARMRAM_CRC register. */
5403 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST))
5404 
5405 #ifndef __ASSEMBLY__
5406 /*
5407  * WARNING: The C register and register group struct declarations are provided for
5408  * convenience and illustrative purposes. They should, however, be used with
5409  * caution as the C language standard provides no guarantees about the alignment or
5410  * atomicity of device memory accesses. The recommended practice for writing
5411  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5412  * alt_write_word() functions.
5413  *
5414  * The struct declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM.
5415  */
5416 struct ALT_SYSMGR_ROMCODE_WARMRAM_s
5417 {
5418  ALT_SYSMGR_ROMCODE_WARMRAM_EN_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */
5419  ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */
5420  ALT_SYSMGR_ROMCODE_WARMRAM_LEN_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */
5421  ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */
5422  ALT_SYSMGR_ROMCODE_WARMRAM_CRC_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */
5423  volatile uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */
5424 };
5425 
5426 /* The typedef declaration for register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5427 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_s ALT_SYSMGR_ROMCODE_WARMRAM_t;
5428 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5429 struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s
5430 {
5431  volatile uint32_t enable; /* ALT_SYSMGR_ROMCODE_WARMRAM_EN */
5432  volatile uint32_t datastart; /* ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART */
5433  volatile uint32_t length; /* ALT_SYSMGR_ROMCODE_WARMRAM_LEN */
5434  volatile uint32_t execution; /* ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION */
5435  volatile uint32_t crc; /* ALT_SYSMGR_ROMCODE_WARMRAM_CRC */
5436  uint32_t _pad_0x14_0x20[3]; /* *UNDEFINED* */
5437 };
5438 
5439 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE_WARMRAM. */
5440 typedef volatile struct ALT_SYSMGR_ROMCODE_WARMRAM_raw_s ALT_SYSMGR_ROMCODE_WARMRAM_raw_t;
5441 #endif /* __ASSEMBLY__ */
5442 
5443 
5444 #ifndef __ASSEMBLY__
5445 /*
5446  * WARNING: The C register and register group struct declarations are provided for
5447  * convenience and illustrative purposes. They should, however, be used with
5448  * caution as the C language standard provides no guarantees about the alignment or
5449  * atomicity of device memory accesses. The recommended practice for writing
5450  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5451  * alt_write_word() functions.
5452  *
5453  * The struct declaration for register group ALT_SYSMGR_ROMCODE.
5454  */
5455 struct ALT_SYSMGR_ROMCODE_s
5456 {
5457  ALT_SYSMGR_ROMCODE_CTL_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */
5458  ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */
5459  ALT_SYSMGR_ROMCODE_INITSWSTATE_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */
5460  ALT_SYSMGR_ROMCODE_INITSWLASTLD_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */
5461  ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */
5462  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5463  ALT_SYSMGR_ROMCODE_WARMRAM_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */
5464 };
5465 
5466 /* The typedef declaration for register group ALT_SYSMGR_ROMCODE. */
5467 typedef volatile struct ALT_SYSMGR_ROMCODE_s ALT_SYSMGR_ROMCODE_t;
5468 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */
5469 struct ALT_SYSMGR_ROMCODE_raw_s
5470 {
5471  volatile uint32_t ctrl; /* ALT_SYSMGR_ROMCODE_CTL */
5472  volatile uint32_t cpu1startaddr; /* ALT_SYSMGR_ROMCODE_CPU1STARTADDR */
5473  volatile uint32_t initswstate; /* ALT_SYSMGR_ROMCODE_INITSWSTATE */
5474  volatile uint32_t initswlastld; /* ALT_SYSMGR_ROMCODE_INITSWLASTLD */
5475  volatile uint32_t bootromswstate; /* ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE */
5476  uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5477  ALT_SYSMGR_ROMCODE_WARMRAM_raw_t romcodegrp_warmramgrp; /* ALT_SYSMGR_ROMCODE_WARMRAM */
5478 };
5479 
5480 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMCODE. */
5481 typedef volatile struct ALT_SYSMGR_ROMCODE_raw_s ALT_SYSMGR_ROMCODE_raw_t;
5482 #endif /* __ASSEMBLY__ */
5483 
5484 
5485 /*
5486  * Register Group : Boot ROM Hardware Register Group - ALT_SYSMGR_ROMHW
5487  * Boot ROM Hardware Register Group
5488  *
5489  * Registers used by the Boot ROM hardware, not the code within it.
5490  *
5491  */
5492 /*
5493  * Register : Boot ROM Hardware Control Register - ctrl
5494  *
5495  * Controls behavior of Boot ROM hardware.
5496  *
5497  * All fields are only reset by a cold reset (ignore warm reset).
5498  *
5499  * Register Layout
5500  *
5501  * Bits | Access | Reset | Description
5502  * :-------|:-------|:------|:-----------------------------------
5503  * [0] | RW | 0x0 | Wait State
5504  * [1] | RW | 0x1 | Enable Safe Mode Warm Reset Update
5505  * [31:2] | ??? | 0x0 | *UNDEFINED*
5506  *
5507  */
5508 /*
5509  * Field : Wait State - waitstate
5510  *
5511  * Controls the number of wait states applied to the Boot ROM's read operation.
5512  *
5513  * This field is cleared on a cold reset and optionally updated by hardware upon
5514  * deassertion of warm reset.
5515  *
5516  * Field Enumeration Values:
5517  *
5518  * Enum | Value | Description
5519  * :-------------------------------------|:------|:-------------------------------------------------
5520  * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS | 0x0 | No wait states are applied to the Boom ROM's
5521  * : | | read operation.
5522  * ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN | 0x1 | A single wait state is applied to the Boot ROM's
5523  * : | | read operation.
5524  *
5525  * Field Access Macros:
5526  *
5527  */
5528 /*
5529  * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
5530  *
5531  * No wait states are applied to the Boom ROM's read operation.
5532  */
5533 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0
5534 /*
5535  * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
5536  *
5537  * A single wait state is applied to the Boot ROM's read operation.
5538  */
5539 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1
5540 
5541 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5542 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0
5543 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5544 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0
5545 /* The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5546 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1
5547 /* The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */
5548 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
5549 /* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value. */
5550 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
5551 /* The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field. */
5552 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0
5553 /* Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register. */
5554 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
5555 /* Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register. */
5556 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
5557 
5558 /*
5559  * Field : Enable Safe Mode Warm Reset Update - ensfmdwru
5560  *
5561  * Controls whether the wait state bit is updated upon deassertion of warm reset.
5562  *
5563  * This field is set on a cold reset.
5564  *
5565  * Field Enumeration Values:
5566  *
5567  * Enum | Value | Description
5568  * :-------------------------------------|:------|:-----------------------------------------------
5569  * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS | 0x0 | Wait state bit is not updated upon deassertion
5570  * : | | of warm reset.
5571  * ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN | 0x1 | Wait state bit is updated upon deassertion of
5572  * : | | warm reset. It's value is updated based on the
5573  * : | | control bit from clock manager which specifies
5574  * : | | whether clock manager will be in safe mode or
5575  * : | | not after warm reset.
5576  *
5577  * Field Access Macros:
5578  *
5579  */
5580 /*
5581  * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
5582  *
5583  * Wait state bit is not updated upon deassertion of warm reset.
5584  */
5585 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0
5586 /*
5587  * Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
5588  *
5589  * Wait state bit is updated upon deassertion of warm reset.
5590  *
5591  * It's value is updated based on the control bit from clock manager which
5592  * specifies whether clock manager will be in safe mode or not after warm reset.
5593  */
5594 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1
5595 
5596 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5597 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1
5598 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5599 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1
5600 /* The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5601 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1
5602 /* The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */
5603 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002
5604 /* The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value. */
5605 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd
5606 /* The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field. */
5607 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1
5608 /* Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register. */
5609 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1)
5610 /* Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register. */
5611 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002)
5612 
5613 #ifndef __ASSEMBLY__
5614 /*
5615  * WARNING: The C register and register group struct declarations are provided for
5616  * convenience and illustrative purposes. They should, however, be used with
5617  * caution as the C language standard provides no guarantees about the alignment or
5618  * atomicity of device memory accesses. The recommended practice for writing
5619  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5620  * alt_write_word() functions.
5621  *
5622  * The struct declaration for register ALT_SYSMGR_ROMHW_CTL.
5623  */
5624 struct ALT_SYSMGR_ROMHW_CTL_s
5625 {
5626  uint32_t waitstate : 1; /* Wait State */
5627  uint32_t ensfmdwru : 1; /* Enable Safe Mode Warm Reset Update */
5628  uint32_t : 30; /* *UNDEFINED* */
5629 };
5630 
5631 /* The typedef declaration for register ALT_SYSMGR_ROMHW_CTL. */
5632 typedef volatile struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t;
5633 #endif /* __ASSEMBLY__ */
5634 
5635 /* The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component. */
5636 #define ALT_SYSMGR_ROMHW_CTL_OFST 0x0
5637 
5638 #ifndef __ASSEMBLY__
5639 /*
5640  * WARNING: The C register and register group struct declarations are provided for
5641  * convenience and illustrative purposes. They should, however, be used with
5642  * caution as the C language standard provides no guarantees about the alignment or
5643  * atomicity of device memory accesses. The recommended practice for writing
5644  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5645  * alt_write_word() functions.
5646  *
5647  * The struct declaration for register group ALT_SYSMGR_ROMHW.
5648  */
5649 struct ALT_SYSMGR_ROMHW_s
5650 {
5651  ALT_SYSMGR_ROMHW_CTL_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */
5652 };
5653 
5654 /* The typedef declaration for register group ALT_SYSMGR_ROMHW. */
5655 typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t;
5656 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */
5657 struct ALT_SYSMGR_ROMHW_raw_s
5658 {
5659  volatile uint32_t ctrl; /* ALT_SYSMGR_ROMHW_CTL */
5660 };
5661 
5662 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ROMHW. */
5663 typedef volatile struct ALT_SYSMGR_ROMHW_raw_s ALT_SYSMGR_ROMHW_raw_t;
5664 #endif /* __ASSEMBLY__ */
5665 
5666 
5667 /*
5668  * Register Group : SDMMC Controller Group - ALT_SYSMGR_SDMMC
5669  * SDMMC Controller Group
5670  *
5671  * Registers related to SDMMC Controller which aren't located inside the SDMMC
5672  * itself.
5673  *
5674  */
5675 /*
5676  * Register : Control Register - ctrl
5677  *
5678  * Registers used by the SDMMC Controller. All fields are reset by a cold or warm
5679  * reset.
5680  *
5681  * Register Layout
5682  *
5683  * Bits | Access | Reset | Description
5684  * :-------|:-------|:------|:--------------------------------
5685  * [2:0] | RW | 0x0 | Drive Clock Phase Shift Select
5686  * [5:3] | RW | 0x0 | Sample Clock Phase Shift Select
5687  * [6] | RW | 0x0 | Feedback Clock Select
5688  * [31:7] | ??? | 0x0 | *UNDEFINED*
5689  *
5690  */
5691 /*
5692  * Field : Drive Clock Phase Shift Select - drvsel
5693  *
5694  * Select which phase shift of the clock for cclk_in_drv.
5695  *
5696  * Field Enumeration Values:
5697  *
5698  * Enum | Value | Description
5699  * :-----------------------------------------|:------|:--------------------------------------------
5700  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected
5701  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected
5702  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected
5703  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected
5704  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected
5705  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected
5706  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected
5707  * ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected
5708  *
5709  * Field Access Macros:
5710  *
5711  */
5712 /*
5713  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5714  *
5715  * 0 degrees phase shifted clock is selected
5716  */
5717 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0
5718 /*
5719  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5720  *
5721  * 45 degrees phase shifted clock is selected
5722  */
5723 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1
5724 /*
5725  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5726  *
5727  * 90 degrees phase shifted clock is selected
5728  */
5729 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2
5730 /*
5731  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5732  *
5733  * 135 degrees phase shifted clock is selected
5734  */
5735 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3
5736 /*
5737  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5738  *
5739  * 180 degrees phase shifted clock is selected
5740  */
5741 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4
5742 /*
5743  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5744  *
5745  * 225 degrees phase shifted clock is selected
5746  */
5747 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5
5748 /*
5749  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5750  *
5751  * 270 degrees phase shifted clock is selected
5752  */
5753 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6
5754 /*
5755  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL
5756  *
5757  * 315 degrees phase shifted clock is selected
5758  */
5759 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7
5760 
5761 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5762 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0
5763 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5764 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2
5765 /* The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5766 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3
5767 /* The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */
5768 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007
5769 /* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value. */
5770 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8
5771 /* The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field. */
5772 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0
5773 /* Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register. */
5774 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
5775 /* Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register. */
5776 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
5777 
5778 /*
5779  * Field : Sample Clock Phase Shift Select - smplsel
5780  *
5781  * Select which phase shift of the clock for cclk_in_sample.
5782  *
5783  * Field Enumeration Values:
5784  *
5785  * Enum | Value | Description
5786  * :------------------------------------------|:------|:--------------------------------------------
5787  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 | 0x0 | 0 degrees phase shifted clock is selected
5788  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 | 0x1 | 45 degrees phase shifted clock is selected
5789  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 | 0x2 | 90 degrees phase shifted clock is selected
5790  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 | 0x3 | 135 degrees phase shifted clock is selected
5791  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 | 0x4 | 180 degrees phase shifted clock is selected
5792  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 | 0x5 | 225 degrees phase shifted clock is selected
5793  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 | 0x6 | 270 degrees phase shifted clock is selected
5794  * ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 | 0x7 | 315 degrees phase shifted clock is selected
5795  *
5796  * Field Access Macros:
5797  *
5798  */
5799 /*
5800  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5801  *
5802  * 0 degrees phase shifted clock is selected
5803  */
5804 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0
5805 /*
5806  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5807  *
5808  * 45 degrees phase shifted clock is selected
5809  */
5810 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1
5811 /*
5812  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5813  *
5814  * 90 degrees phase shifted clock is selected
5815  */
5816 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2
5817 /*
5818  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5819  *
5820  * 135 degrees phase shifted clock is selected
5821  */
5822 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3
5823 /*
5824  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5825  *
5826  * 180 degrees phase shifted clock is selected
5827  */
5828 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4
5829 /*
5830  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5831  *
5832  * 225 degrees phase shifted clock is selected
5833  */
5834 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5
5835 /*
5836  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5837  *
5838  * 270 degrees phase shifted clock is selected
5839  */
5840 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6
5841 /*
5842  * Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL
5843  *
5844  * 315 degrees phase shifted clock is selected
5845  */
5846 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7
5847 
5848 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5849 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3
5850 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5851 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5
5852 /* The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5853 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3
5854 /* The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */
5855 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038
5856 /* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value. */
5857 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7
5858 /* The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field. */
5859 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0
5860 /* Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register. */
5861 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3)
5862 /* Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register. */
5863 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038)
5864 
5865 /*
5866  * Field : Feedback Clock Select - fbclksel
5867  *
5868  * Select which fb_clk to be used as cclk_in_sample.
5869  *
5870  * If 0, cclk_in_sample is driven by internal phase shifted cclk_in.
5871  *
5872  * If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided
5873  * internally on cclk_in_sample.
5874  *
5875  * Note: Using the feedback clock (setting this bit to 1) is not a supported use
5876  * model.
5877  *
5878  * Field Access Macros:
5879  *
5880  */
5881 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5882 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6
5883 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5884 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6
5885 /* The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5886 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1
5887 /* The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */
5888 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040
5889 /* The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value. */
5890 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf
5891 /* The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field. */
5892 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0
5893 /* Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register. */
5894 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6)
5895 /* Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register. */
5896 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040)
5897 
5898 #ifndef __ASSEMBLY__
5899 /*
5900  * WARNING: The C register and register group struct declarations are provided for
5901  * convenience and illustrative purposes. They should, however, be used with
5902  * caution as the C language standard provides no guarantees about the alignment or
5903  * atomicity of device memory accesses. The recommended practice for writing
5904  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
5905  * alt_write_word() functions.
5906  *
5907  * The struct declaration for register ALT_SYSMGR_SDMMC_CTL.
5908  */
5909 struct ALT_SYSMGR_SDMMC_CTL_s
5910 {
5911  uint32_t drvsel : 3; /* Drive Clock Phase Shift Select */
5912  uint32_t smplsel : 3; /* Sample Clock Phase Shift Select */
5913  uint32_t fbclksel : 1; /* Feedback Clock Select */
5914  uint32_t : 25; /* *UNDEFINED* */
5915 };
5916 
5917 /* The typedef declaration for register ALT_SYSMGR_SDMMC_CTL. */
5918 typedef volatile struct ALT_SYSMGR_SDMMC_CTL_s ALT_SYSMGR_SDMMC_CTL_t;
5919 #endif /* __ASSEMBLY__ */
5920 
5921 /* The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component. */
5922 #define ALT_SYSMGR_SDMMC_CTL_OFST 0x0
5923 
5924 /*
5925  * Register : SD/MMC L3 Master HPROT Register - l3master
5926  *
5927  * Controls the L3 master HPROT AHB-Lite signal.
5928  *
5929  * These register bits should be updated only during system initialization prior to
5930  * removing the peripheral from reset. They may not be changed dynamically during
5931  * peripheral operation
5932  *
5933  * All fields are reset by a cold or warm reset.
5934  *
5935  * Register Layout
5936  *
5937  * Bits | Access | Reset | Description
5938  * :-------|:-------|:------|:-------------------------
5939  * [0] | RW | 0x1 | SD/MMC HPROT Data/Opcode
5940  * [1] | RW | 0x1 | SD/MMC HPROT Privileged
5941  * [2] | RW | 0x0 | SD/MMC HPROT Bufferable
5942  * [3] | RW | 0x0 | SD/MMC HPROT Cacheable
5943  * [31:4] | ??? | 0x0 | *UNDEFINED*
5944  *
5945  */
5946 /*
5947  * Field : SD/MMC HPROT Data/Opcode - hprotdata_0
5948  *
5949  * Specifies if the L3 master access is for data or opcode for the SD/MMC module.
5950  *
5951  * Field Enumeration Values:
5952  *
5953  * Enum | Value | Description
5954  * :--------------------------------------------|:------|:-------------
5955  * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch
5956  * ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access
5957  *
5958  * Field Access Macros:
5959  *
5960  */
5961 /*
5962  * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0
5963  *
5964  * Opcode fetch
5965  */
5966 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0
5967 /*
5968  * Enumerated value for register field ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0
5969  *
5970  * Data access
5971  */
5972 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1
5973 
5974 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5975 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0
5976 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5977 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0
5978 /* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5979 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1
5980 /* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */
5981 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001
5982 /* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value. */
5983 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
5984 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field. */
5985 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1
5986 /* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 field value from a register. */
5987 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
5988 /* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0 register field value suitable for setting the register. */
5989 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
5990 
5991 /*
5992  * Field : SD/MMC HPROT Privileged - hprotpriv_0
5993  *
5994  * If 1, L3 master accesses for the SD/MMC module are privileged.
5995  *
5996  * Field Access Macros:
5997  *
5998  */
5999 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6000 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1
6001 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6002 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1
6003 /* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6004 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1
6005 /* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */
6006 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002
6007 /* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value. */
6008 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd
6009 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field. */
6010 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1
6011 /* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 field value from a register. */
6012 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1)
6013 /* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */
6014 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002)
6015 
6016 /*
6017  * Field : SD/MMC HPROT Bufferable - hprotbuff_0
6018  *
6019  * If 1, L3 master accesses for the SD/MMC module are bufferable.
6020  *
6021  * Field Access Macros:
6022  *
6023  */
6024 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6025 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2
6026 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6027 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2
6028 /* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6029 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1
6030 /* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */
6031 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004
6032 /* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value. */
6033 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb
6034 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field. */
6035 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0
6036 /* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 field value from a register. */
6037 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2)
6038 /* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */
6039 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004)
6040 
6041 /*
6042  * Field : SD/MMC HPROT Cacheable - hprotcache_0
6043  *
6044  * If 1, L3 master accesses for the SD/MMC module are cacheable.
6045  *
6046  * Field Access Macros:
6047  *
6048  */
6049 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6050 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3
6051 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6052 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3
6053 /* The width in bits of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6054 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1
6055 /* The mask used to set the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */
6056 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008
6057 /* The mask used to clear the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value. */
6058 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7
6059 /* The reset value of the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field. */
6060 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0
6061 /* Extracts the ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 field value from a register. */
6062 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3)
6063 /* Produces a ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */
6064 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008)
6065 
6066 #ifndef __ASSEMBLY__
6067 /*
6068  * WARNING: The C register and register group struct declarations are provided for
6069  * convenience and illustrative purposes. They should, however, be used with
6070  * caution as the C language standard provides no guarantees about the alignment or
6071  * atomicity of device memory accesses. The recommended practice for writing
6072  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6073  * alt_write_word() functions.
6074  *
6075  * The struct declaration for register ALT_SYSMGR_SDMMC_L3MST.
6076  */
6077 struct ALT_SYSMGR_SDMMC_L3MST_s
6078 {
6079  uint32_t hprotdata_0 : 1; /* SD/MMC HPROT Data/Opcode */
6080  uint32_t hprotpriv_0 : 1; /* SD/MMC HPROT Privileged */
6081  uint32_t hprotbuff_0 : 1; /* SD/MMC HPROT Bufferable */
6082  uint32_t hprotcache_0 : 1; /* SD/MMC HPROT Cacheable */
6083  uint32_t : 28; /* *UNDEFINED* */
6084 };
6085 
6086 /* The typedef declaration for register ALT_SYSMGR_SDMMC_L3MST. */
6087 typedef volatile struct ALT_SYSMGR_SDMMC_L3MST_s ALT_SYSMGR_SDMMC_L3MST_t;
6088 #endif /* __ASSEMBLY__ */
6089 
6090 /* The byte offset of the ALT_SYSMGR_SDMMC_L3MST register from the beginning of the component. */
6091 #define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4
6092 
6093 #ifndef __ASSEMBLY__
6094 /*
6095  * WARNING: The C register and register group struct declarations are provided for
6096  * convenience and illustrative purposes. They should, however, be used with
6097  * caution as the C language standard provides no guarantees about the alignment or
6098  * atomicity of device memory accesses. The recommended practice for writing
6099  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6100  * alt_write_word() functions.
6101  *
6102  * The struct declaration for register group ALT_SYSMGR_SDMMC.
6103  */
6104 struct ALT_SYSMGR_SDMMC_s
6105 {
6106  ALT_SYSMGR_SDMMC_CTL_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */
6107  ALT_SYSMGR_SDMMC_L3MST_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */
6108 };
6109 
6110 /* The typedef declaration for register group ALT_SYSMGR_SDMMC. */
6111 typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
6112 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */
6113 struct ALT_SYSMGR_SDMMC_raw_s
6114 {
6115  volatile uint32_t ctrl; /* ALT_SYSMGR_SDMMC_CTL */
6116  volatile uint32_t l3master; /* ALT_SYSMGR_SDMMC_L3MST */
6117 };
6118 
6119 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_SDMMC. */
6120 typedef volatile struct ALT_SYSMGR_SDMMC_raw_s ALT_SYSMGR_SDMMC_raw_t;
6121 #endif /* __ASSEMBLY__ */
6122 
6123 
6124 /*
6125  * Register Group : NAND Flash Controller Register Group - ALT_SYSMGR_NAND
6126  * NAND Flash Controller Register Group
6127  *
6128  * Registers related to NAND Flash Controller which aren't located in the NAND
6129  * Flash Controller itself.
6130  *
6131  */
6132 /*
6133  * Register : Bootstrap Control Register - bootstrap
6134  *
6135  * Bootstrap fields sampled by NAND Flash Controller when released from reset.
6136  *
6137  * All fields are reset by a cold or warm reset.
6138  *
6139  * Register Layout
6140  *
6141  * Bits | Access | Reset | Description
6142  * :-------|:-------|:------|:--------------------------------------
6143  * [0] | RW | 0x0 | Bootstrap Inhibit Initialization
6144  * [1] | RW | 0x0 | Bootstrap 512 Byte Device
6145  * [2] | RW | 0x0 | Bootstrap Inhibit Load Block 0 Page 0
6146  * [3] | RW | 0x0 | Bootstrap Two Row Address Cycles
6147  * [31:4] | ??? | 0x0 | *UNDEFINED*
6148  *
6149  */
6150 /*
6151  * Field : Bootstrap Inhibit Initialization - noinit
6152  *
6153  * If 1, inhibits NAND Flash Controller from performing initialization when coming
6154  * out of reset. Instead, software must program all registers pertaining to device
6155  * parameters like page size, width, etc.
6156  *
6157  * Field Access Macros:
6158  *
6159  */
6160 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6161 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
6162 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6163 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
6164 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6165 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
6166 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
6167 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
6168 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value. */
6169 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
6170 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field. */
6171 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
6172 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT field value from a register. */
6173 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
6174 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT register field value suitable for setting the register. */
6175 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
6176 
6177 /*
6178  * Field : Bootstrap 512 Byte Device - page512
6179  *
6180  * If 1, NAND device has a 512 byte page size.
6181  *
6182  * Field Access Macros:
6183  *
6184  */
6185 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6186 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1
6187 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6188 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1
6189 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6190 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
6191 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
6192 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002
6193 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value. */
6194 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd
6195 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field. */
6196 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
6197 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 field value from a register. */
6198 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1)
6199 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512 register field value suitable for setting the register. */
6200 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002)
6201 
6202 /*
6203  * Field : Bootstrap Inhibit Load Block 0 Page 0 - noloadb0p0
6204  *
6205  * If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND
6206  * device as part of the initialization procedure.
6207  *
6208  * Field Access Macros:
6209  *
6210  */
6211 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6212 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2
6213 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6214 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2
6215 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6216 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
6217 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
6218 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004
6219 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value. */
6220 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb
6221 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field. */
6222 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
6223 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 field value from a register. */
6224 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2)
6225 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0 register field value suitable for setting the register. */
6226 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004)
6227 
6228 /*
6229  * Field : Bootstrap Two Row Address Cycles - tworowaddr
6230  *
6231  * If 1, NAND device requires only 2 row address cycles instead of the normal 3 row
6232  * address cycles.
6233  *
6234  * Field Access Macros:
6235  *
6236  */
6237 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6238 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3
6239 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6240 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3
6241 /* The width in bits of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6242 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
6243 /* The mask used to set the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
6244 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008
6245 /* The mask used to clear the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value. */
6246 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7
6247 /* The reset value of the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field. */
6248 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
6249 /* Extracts the ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR field value from a register. */
6250 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3)
6251 /* Produces a ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR register field value suitable for setting the register. */
6252 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008)
6253 
6254 #ifndef __ASSEMBLY__
6255 /*
6256  * WARNING: The C register and register group struct declarations are provided for
6257  * convenience and illustrative purposes. They should, however, be used with
6258  * caution as the C language standard provides no guarantees about the alignment or
6259  * atomicity of device memory accesses. The recommended practice for writing
6260  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6261  * alt_write_word() functions.
6262  *
6263  * The struct declaration for register ALT_SYSMGR_NAND_BOOTSTRAP.
6264  */
6265 struct ALT_SYSMGR_NAND_BOOTSTRAP_s
6266 {
6267  uint32_t noinit : 1; /* Bootstrap Inhibit Initialization */
6268  uint32_t page512 : 1; /* Bootstrap 512 Byte Device */
6269  uint32_t noloadb0p0 : 1; /* Bootstrap Inhibit Load Block 0 Page 0 */
6270  uint32_t tworowaddr : 1; /* Bootstrap Two Row Address Cycles */
6271  uint32_t : 28; /* *UNDEFINED* */
6272 };
6273 
6274 /* The typedef declaration for register ALT_SYSMGR_NAND_BOOTSTRAP. */
6275 typedef volatile struct ALT_SYSMGR_NAND_BOOTSTRAP_s ALT_SYSMGR_NAND_BOOTSTRAP_t;
6276 #endif /* __ASSEMBLY__ */
6277 
6278 /* The byte offset of the ALT_SYSMGR_NAND_BOOTSTRAP register from the beginning of the component. */
6279 #define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0
6280 
6281 /*
6282  * Register : NAND L3 Master AxCACHE Register - l3master
6283  *
6284  * Controls the L3 master ARCACHE and AWCACHE AXI signals.
6285  *
6286  * These register bits should be updated only during system initialization prior to
6287  * removing the peripheral from reset. They may not be changed dynamically during
6288  * peripheral operation
6289  *
6290  * All fields are reset by a cold or warm reset.
6291  *
6292  * Register Layout
6293  *
6294  * Bits | Access | Reset | Description
6295  * :-------|:-------|:------|:-------------
6296  * [3:0] | RW | 0x0 | NAND ARCACHE
6297  * [7:4] | RW | 0x0 | NAND AWCACHE
6298  * [31:8] | ??? | 0x0 | *UNDEFINED*
6299  *
6300  */
6301 /*
6302  * Field : NAND ARCACHE - arcache_0
6303  *
6304  * Specifies the value of the module ARCACHE signal.
6305  *
6306  * Field Enumeration Values:
6307  *
6308  * Enum | Value | Description
6309  * :-------------------------------------------------------|:------|:-------------------------------------------------
6310  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
6311  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF | 0x1 | Bufferable only.
6312  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
6313  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
6314  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 | 0x4 | Reserved.
6315  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 | 0x5 | Reserved.
6316  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
6317  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
6318  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 | 0x8 | Reserved.
6319  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 | 0x9 | Reserved.
6320  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
6321  * : | | only.
6322  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
6323  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 | 0xc | Reserved.
6324  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 | 0xd | Reserved.
6325  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
6326  * : | | and writes.
6327  * ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
6328  * : | | writes.
6329  *
6330  * Field Access Macros:
6331  *
6332  */
6333 /*
6334  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6335  *
6336  * Noncacheable and nonbufferable.
6337  */
6338 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
6339 /*
6340  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6341  *
6342  * Bufferable only.
6343  */
6344 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
6345 /*
6346  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6347  *
6348  * Cacheable, but do not allocate.
6349  */
6350 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
6351 /*
6352  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6353  *
6354  * Cacheable and bufferable, but do not allocate.
6355  */
6356 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6357 /*
6358  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6359  *
6360  * Reserved.
6361  */
6362 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
6363 /*
6364  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6365  *
6366  * Reserved.
6367  */
6368 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
6369 /*
6370  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6371  *
6372  * Cacheable write-through, allocate on reads only.
6373  */
6374 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6375 /*
6376  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6377  *
6378  * Cacheable write-back, allocate on reads only.
6379  */
6380 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6381 /*
6382  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6383  *
6384  * Reserved.
6385  */
6386 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
6387 /*
6388  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6389  *
6390  * Reserved.
6391  */
6392 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
6393 /*
6394  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6395  *
6396  * Cacheable write-through, allocate on writes only.
6397  */
6398 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6399 /*
6400  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6401  *
6402  * Cacheable write-back, allocate on writes only.
6403  */
6404 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6405 /*
6406  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6407  *
6408  * Reserved.
6409  */
6410 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
6411 /*
6412  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6413  *
6414  * Reserved.
6415  */
6416 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
6417 /*
6418  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6419  *
6420  * Cacheable write-through, allocate on both reads and writes.
6421  */
6422 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6423 /*
6424  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_ARCACHE_0
6425  *
6426  * Cacheable write-back, allocate on both reads and writes.
6427  */
6428 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6429 
6430 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6431 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
6432 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6433 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
6434 /* The width in bits of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6435 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
6436 /* The mask used to set the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
6437 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
6438 /* The mask used to clear the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value. */
6439 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
6440 /* The reset value of the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field. */
6441 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
6442 /* Extracts the ALT_SYSMGR_NAND_L3MST_ARCACHE_0 field value from a register. */
6443 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
6444 /* Produces a ALT_SYSMGR_NAND_L3MST_ARCACHE_0 register field value suitable for setting the register. */
6445 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
6446 
6447 /*
6448  * Field : NAND AWCACHE - awcache_0
6449  *
6450  * Specifies the value of the module AWCACHE signal.
6451  *
6452  * Field Enumeration Values:
6453  *
6454  * Enum | Value | Description
6455  * :-------------------------------------------------------|:------|:-------------------------------------------------
6456  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF | 0x0 | Noncacheable and nonbufferable.
6457  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF | 0x1 | Bufferable only.
6458  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC | 0x2 | Cacheable, but do not allocate.
6459  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC | 0x3 | Cacheable and bufferable, but do not allocate.
6460  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 | 0x4 | Reserved.
6461  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 | 0x5 | Reserved.
6462  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC | 0x6 | Cacheable write-through, allocate on reads only.
6463  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC | 0x7 | Cacheable write-back, allocate on reads only.
6464  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 | 0x8 | Reserved.
6465  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 | 0x9 | Reserved.
6466  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC | 0xa | Cacheable write-through, allocate on writes
6467  * : | | only.
6468  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC | 0xb | Cacheable write-back, allocate on writes only.
6469  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 | 0xc | Reserved.
6470  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 | 0xd | Reserved.
6471  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC | 0xe | Cacheable write-through, allocate on both reads
6472  * : | | and writes.
6473  * ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC | 0xf | Cacheable write-back, allocate on both reads and
6474  * : | | writes.
6475  *
6476  * Field Access Macros:
6477  *
6478  */
6479 /*
6480  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6481  *
6482  * Noncacheable and nonbufferable.
6483  */
6484 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
6485 /*
6486  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6487  *
6488  * Bufferable only.
6489  */
6490 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
6491 /*
6492  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6493  *
6494  * Cacheable, but do not allocate.
6495  */
6496 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
6497 /*
6498  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6499  *
6500  * Cacheable and bufferable, but do not allocate.
6501  */
6502 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6503 /*
6504  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6505  *
6506  * Reserved.
6507  */
6508 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
6509 /*
6510  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6511  *
6512  * Reserved.
6513  */
6514 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
6515 /*
6516  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6517  *
6518  * Cacheable write-through, allocate on reads only.
6519  */
6520 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6521 /*
6522  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6523  *
6524  * Cacheable write-back, allocate on reads only.
6525  */
6526 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6527 /*
6528  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6529  *
6530  * Reserved.
6531  */
6532 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
6533 /*
6534  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6535  *
6536  * Reserved.
6537  */
6538 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
6539 /*
6540  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6541  *
6542  * Cacheable write-through, allocate on writes only.
6543  */
6544 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6545 /*
6546  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6547  *
6548  * Cacheable write-back, allocate on writes only.
6549  */
6550 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6551 /*
6552  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6553  *
6554  * Reserved.
6555  */
6556 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
6557 /*
6558  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6559  *
6560  * Reserved.
6561  */
6562 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
6563 /*
6564  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6565  *
6566  * Cacheable write-through, allocate on both reads and writes.
6567  */
6568 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6569 /*
6570  * Enumerated value for register field ALT_SYSMGR_NAND_L3MST_AWCACHE_0
6571  *
6572  * Cacheable write-back, allocate on both reads and writes.
6573  */
6574 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6575 
6576 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6577 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
6578 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6579 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
6580 /* The width in bits of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6581 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
6582 /* The mask used to set the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
6583 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
6584 /* The mask used to clear the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value. */
6585 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
6586 /* The reset value of the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field. */
6587 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
6588 /* Extracts the ALT_SYSMGR_NAND_L3MST_AWCACHE_0 field value from a register. */
6589 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
6590 /* Produces a ALT_SYSMGR_NAND_L3MST_AWCACHE_0 register field value suitable for setting the register. */
6591 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
6592 
6593 #ifndef __ASSEMBLY__
6594 /*
6595  * WARNING: The C register and register group struct declarations are provided for
6596  * convenience and illustrative purposes. They should, however, be used with
6597  * caution as the C language standard provides no guarantees about the alignment or
6598  * atomicity of device memory accesses. The recommended practice for writing
6599  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6600  * alt_write_word() functions.
6601  *
6602  * The struct declaration for register ALT_SYSMGR_NAND_L3MST.
6603  */
6604 struct ALT_SYSMGR_NAND_L3MST_s
6605 {
6606  uint32_t arcache_0 : 4; /* NAND ARCACHE */
6607  uint32_t awcache_0 : 4; /* NAND AWCACHE */
6608  uint32_t : 24; /* *UNDEFINED* */
6609 };
6610 
6611 /* The typedef declaration for register ALT_SYSMGR_NAND_L3MST. */
6612 typedef volatile struct ALT_SYSMGR_NAND_L3MST_s ALT_SYSMGR_NAND_L3MST_t;
6613 #endif /* __ASSEMBLY__ */
6614 
6615 /* The byte offset of the ALT_SYSMGR_NAND_L3MST register from the beginning of the component. */
6616 #define ALT_SYSMGR_NAND_L3MST_OFST 0x4
6617 
6618 #ifndef __ASSEMBLY__
6619 /*
6620  * WARNING: The C register and register group struct declarations are provided for
6621  * convenience and illustrative purposes. They should, however, be used with
6622  * caution as the C language standard provides no guarantees about the alignment or
6623  * atomicity of device memory accesses. The recommended practice for writing
6624  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6625  * alt_write_word() functions.
6626  *
6627  * The struct declaration for register group ALT_SYSMGR_NAND.
6628  */
6629 struct ALT_SYSMGR_NAND_s
6630 {
6631  ALT_SYSMGR_NAND_BOOTSTRAP_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
6632  ALT_SYSMGR_NAND_L3MST_t l3master; /* ALT_SYSMGR_NAND_L3MST */
6633 };
6634 
6635 /* The typedef declaration for register group ALT_SYSMGR_NAND. */
6636 typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t;
6637 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_NAND. */
6638 struct ALT_SYSMGR_NAND_raw_s
6639 {
6640  volatile uint32_t bootstrap; /* ALT_SYSMGR_NAND_BOOTSTRAP */
6641  volatile uint32_t l3master; /* ALT_SYSMGR_NAND_L3MST */
6642 };
6643 
6644 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_NAND. */
6645 typedef volatile struct ALT_SYSMGR_NAND_raw_s ALT_SYSMGR_NAND_raw_t;
6646 #endif /* __ASSEMBLY__ */
6647 
6648 
6649 /*
6650  * Register Group : USB Controller Group - ALT_SYSMGR_USB
6651  * USB Controller Group
6652  *
6653  * Registers related to USB Controllers which aren't located inside the USB
6654  * controllers themselves.
6655  *
6656  */
6657 /*
6658  * Register : USB L3 Master HPROT Register - l3master
6659  *
6660  * Controls the L3 master HPROT AHB-Lite signal.
6661  *
6662  * These register bits should be updated only during system initialization prior to
6663  * removing the peripheral from reset. They may not be changed dynamically during
6664  * peripheral operation
6665  *
6666  * All fields are reset by a cold or warm reset.
6667  *
6668  * Register Layout
6669  *
6670  * Bits | Access | Reset | Description
6671  * :-------|:-------|:------|:----------------------
6672  * [0] | RW | 0x1 | USB HPROT Data/Opcode
6673  * [1] | RW | 0x1 | USB HPROT Data/Opcode
6674  * [2] | RW | 0x1 | USB HPROT Privileged
6675  * [3] | RW | 0x1 | USB HPROT Privileged
6676  * [4] | RW | 0x0 | USB HPROT Bufferable
6677  * [5] | RW | 0x0 | USB HPROT Bufferable
6678  * [6] | RW | 0x0 | USB HPROT Cacheable
6679  * [7] | RW | 0x0 | USB HPROT Cacheable
6680  * [31:8] | ??? | 0x0 | *UNDEFINED*
6681  *
6682  */
6683 /*
6684  * Field : USB HPROT Data/Opcode - hprotdata_0
6685  *
6686  * Specifies if the L3 master access is for data or opcode for the USB modules.
6687  *
6688  * The field array index corresponds to the USB index.
6689  *
6690  * Field Enumeration Values:
6691  *
6692  * Enum | Value | Description
6693  * :------------------------------------------|:------|:-------------
6694  * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE | 0x0 | Opcode fetch
6695  * ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA | 0x1 | Data access
6696  *
6697  * Field Access Macros:
6698  *
6699  */
6700 /*
6701  * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0
6702  *
6703  * Opcode fetch
6704  */
6705 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0
6706 /*
6707  * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_0
6708  *
6709  * Data access
6710  */
6711 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1
6712 
6713 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6714 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0
6715 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6716 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0
6717 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6718 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1
6719 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */
6720 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001
6721 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value. */
6722 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
6723 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field. */
6724 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1
6725 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_0 field value from a register. */
6726 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
6727 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_0 register field value suitable for setting the register. */
6728 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
6729 
6730 /*
6731  * Field : USB HPROT Data/Opcode - hprotdata_1
6732  *
6733  * Specifies if the L3 master access is for data or opcode for the USB modules.
6734  *
6735  * The field array index corresponds to the USB index.
6736  *
6737  * Field Enumeration Values:
6738  *
6739  * Enum | Value | Description
6740  * :------------------------------------------|:------|:-------------
6741  * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE | 0x0 | Opcode fetch
6742  * ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA | 0x1 | Data access
6743  *
6744  * Field Access Macros:
6745  *
6746  */
6747 /*
6748  * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1
6749  *
6750  * Opcode fetch
6751  */
6752 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0
6753 /*
6754  * Enumerated value for register field ALT_SYSMGR_USB_L3MST_HPROTDATA_1
6755  *
6756  * Data access
6757  */
6758 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1
6759 
6760 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6761 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1
6762 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6763 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1
6764 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6765 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1
6766 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */
6767 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002
6768 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value. */
6769 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd
6770 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field. */
6771 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1
6772 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTDATA_1 field value from a register. */
6773 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1)
6774 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTDATA_1 register field value suitable for setting the register. */
6775 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002)
6776 
6777 /*
6778  * Field : USB HPROT Privileged - hprotpriv_0
6779  *
6780  * If 1, L3 master accesses for the USB modules are privileged.
6781  *
6782  * The field array index corresponds to the USB index.
6783  *
6784  * Field Access Macros:
6785  *
6786  */
6787 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6788 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2
6789 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6790 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2
6791 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6792 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1
6793 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */
6794 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004
6795 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value. */
6796 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb
6797 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field. */
6798 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1
6799 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 field value from a register. */
6800 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2)
6801 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_0 register field value suitable for setting the register. */
6802 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004)
6803 
6804 /*
6805  * Field : USB HPROT Privileged - hprotpriv_1
6806  *
6807  * If 1, L3 master accesses for the USB modules are privileged.
6808  *
6809  * The field array index corresponds to the USB index.
6810  *
6811  * Field Access Macros:
6812  *
6813  */
6814 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6815 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3
6816 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6817 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3
6818 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6819 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1
6820 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */
6821 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008
6822 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value. */
6823 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7
6824 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field. */
6825 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1
6826 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 field value from a register. */
6827 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3)
6828 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTPRIV_1 register field value suitable for setting the register. */
6829 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008)
6830 
6831 /*
6832  * Field : USB HPROT Bufferable - hprotbuff_0
6833  *
6834  * If 1, L3 master accesses for the USB modules are bufferable.
6835  *
6836  * The field array index corresponds to the USB index.
6837  *
6838  * Field Access Macros:
6839  *
6840  */
6841 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6842 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4
6843 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6844 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4
6845 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6846 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1
6847 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */
6848 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010
6849 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value. */
6850 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef
6851 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field. */
6852 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0
6853 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 field value from a register. */
6854 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4)
6855 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_0 register field value suitable for setting the register. */
6856 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010)
6857 
6858 /*
6859  * Field : USB HPROT Bufferable - hprotbuff_1
6860  *
6861  * If 1, L3 master accesses for the USB modules are bufferable.
6862  *
6863  * The field array index corresponds to the USB index.
6864  *
6865  * Field Access Macros:
6866  *
6867  */
6868 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6869 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5
6870 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6871 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5
6872 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6873 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1
6874 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */
6875 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020
6876 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value. */
6877 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf
6878 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field. */
6879 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0
6880 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 field value from a register. */
6881 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5)
6882 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTBUFF_1 register field value suitable for setting the register. */
6883 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020)
6884 
6885 /*
6886  * Field : USB HPROT Cacheable - hprotcache_0
6887  *
6888  * If 1, L3 master accesses for the USB modules are cacheable.
6889  *
6890  * The field array index corresponds to the USB index.
6891  *
6892  * Field Access Macros:
6893  *
6894  */
6895 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6896 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6
6897 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6898 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6
6899 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6900 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1
6901 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */
6902 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040
6903 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value. */
6904 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf
6905 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field. */
6906 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0
6907 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 field value from a register. */
6908 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6)
6909 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_0 register field value suitable for setting the register. */
6910 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040)
6911 
6912 /*
6913  * Field : USB HPROT Cacheable - hprotcache_1
6914  *
6915  * If 1, L3 master accesses for the USB modules are cacheable.
6916  *
6917  * The field array index corresponds to the USB index.
6918  *
6919  * Field Access Macros:
6920  *
6921  */
6922 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6923 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7
6924 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6925 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7
6926 /* The width in bits of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6927 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1
6928 /* The mask used to set the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */
6929 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080
6930 /* The mask used to clear the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value. */
6931 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f
6932 /* The reset value of the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field. */
6933 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0
6934 /* Extracts the ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 field value from a register. */
6935 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7)
6936 /* Produces a ALT_SYSMGR_USB_L3MST_HPROTCACHE_1 register field value suitable for setting the register. */
6937 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080)
6938 
6939 #ifndef __ASSEMBLY__
6940 /*
6941  * WARNING: The C register and register group struct declarations are provided for
6942  * convenience and illustrative purposes. They should, however, be used with
6943  * caution as the C language standard provides no guarantees about the alignment or
6944  * atomicity of device memory accesses. The recommended practice for writing
6945  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6946  * alt_write_word() functions.
6947  *
6948  * The struct declaration for register ALT_SYSMGR_USB_L3MST.
6949  */
6950 struct ALT_SYSMGR_USB_L3MST_s
6951 {
6952  uint32_t hprotdata_0 : 1; /* USB HPROT Data/Opcode */
6953  uint32_t hprotdata_1 : 1; /* USB HPROT Data/Opcode */
6954  uint32_t hprotpriv_0 : 1; /* USB HPROT Privileged */
6955  uint32_t hprotpriv_1 : 1; /* USB HPROT Privileged */
6956  uint32_t hprotbuff_0 : 1; /* USB HPROT Bufferable */
6957  uint32_t hprotbuff_1 : 1; /* USB HPROT Bufferable */
6958  uint32_t hprotcache_0 : 1; /* USB HPROT Cacheable */
6959  uint32_t hprotcache_1 : 1; /* USB HPROT Cacheable */
6960  uint32_t : 24; /* *UNDEFINED* */
6961 };
6962 
6963 /* The typedef declaration for register ALT_SYSMGR_USB_L3MST. */
6964 typedef volatile struct ALT_SYSMGR_USB_L3MST_s ALT_SYSMGR_USB_L3MST_t;
6965 #endif /* __ASSEMBLY__ */
6966 
6967 /* The byte offset of the ALT_SYSMGR_USB_L3MST register from the beginning of the component. */
6968 #define ALT_SYSMGR_USB_L3MST_OFST 0x0
6969 
6970 #ifndef __ASSEMBLY__
6971 /*
6972  * WARNING: The C register and register group struct declarations are provided for
6973  * convenience and illustrative purposes. They should, however, be used with
6974  * caution as the C language standard provides no guarantees about the alignment or
6975  * atomicity of device memory accesses. The recommended practice for writing
6976  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
6977  * alt_write_word() functions.
6978  *
6979  * The struct declaration for register group ALT_SYSMGR_USB.
6980  */
6981 struct ALT_SYSMGR_USB_s
6982 {
6983  ALT_SYSMGR_USB_L3MST_t l3master; /* ALT_SYSMGR_USB_L3MST */
6984 };
6985 
6986 /* The typedef declaration for register group ALT_SYSMGR_USB. */
6987 typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t;
6988 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_USB. */
6989 struct ALT_SYSMGR_USB_raw_s
6990 {
6991  volatile uint32_t l3master; /* ALT_SYSMGR_USB_L3MST */
6992 };
6993 
6994 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_USB. */
6995 typedef volatile struct ALT_SYSMGR_USB_raw_s ALT_SYSMGR_USB_raw_t;
6996 #endif /* __ASSEMBLY__ */
6997 
6998 
6999 /*
7000  * Register Group : ECC Management Register Group - ALT_SYSMGR_ECC
7001  * ECC Management Register Group
7002  *
7003  * ECC error status and control for all ECC-protected HPS RAM blocks.
7004  *
7005  */
7006 /*
7007  * Register : L2 Data RAM ECC Enable Register - l2
7008  *
7009  * This register is used to enable ECC on the L2 Data RAM. ECC errors can be
7010  * injected into the write path using bits in this register. This register contains
7011  * interrupt status of the ECC single/double bit error.
7012  *
7013  * Only reset by a cold reset (ignores warm reset).
7014  *
7015  * Register Layout
7016  *
7017  * Bits | Access | Reset | Description
7018  * :-------|:-------|:------|:---------------------------------------------------------
7019  * [0] | RW | 0x0 | L2 Data RAM ECC Enable
7020  * [1] | RW | 0x0 | L2 Data RAM ECC inject single, correctable Error
7021  * [2] | RW | 0x0 | L2 Data RAM ECC inject double bit, non-correctable error
7022  * [31:3] | ??? | 0x0 | *UNDEFINED*
7023  *
7024  */
7025 /*
7026  * Field : L2 Data RAM ECC Enable - en
7027  *
7028  * Enable ECC for L2 Data RAM
7029  *
7030  * Field Access Macros:
7031  *
7032  */
7033 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */
7034 #define ALT_SYSMGR_ECC_L2_EN_LSB 0
7035 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_EN register field. */
7036 #define ALT_SYSMGR_ECC_L2_EN_MSB 0
7037 /* The width in bits of the ALT_SYSMGR_ECC_L2_EN register field. */
7038 #define ALT_SYSMGR_ECC_L2_EN_WIDTH 1
7039 /* The mask used to set the ALT_SYSMGR_ECC_L2_EN register field value. */
7040 #define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001
7041 /* The mask used to clear the ALT_SYSMGR_ECC_L2_EN register field value. */
7042 #define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe
7043 /* The reset value of the ALT_SYSMGR_ECC_L2_EN register field. */
7044 #define ALT_SYSMGR_ECC_L2_EN_RESET 0x0
7045 /* Extracts the ALT_SYSMGR_ECC_L2_EN field value from a register. */
7046 #define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0)
7047 /* Produces a ALT_SYSMGR_ECC_L2_EN register field value suitable for setting the register. */
7048 #define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001)
7049 
7050 /*
7051  * Field : L2 Data RAM ECC inject single, correctable Error - injs
7052  *
7053  * Changing this bit from zero to one injects a single, correctable error into the
7054  * L2 Data RAM. This only injects one error into the L2 Data RAM.
7055  *
7056  * Field Access Macros:
7057  *
7058  */
7059 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */
7060 #define ALT_SYSMGR_ECC_L2_INJS_LSB 1
7061 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJS register field. */
7062 #define ALT_SYSMGR_ECC_L2_INJS_MSB 1
7063 /* The width in bits of the ALT_SYSMGR_ECC_L2_INJS register field. */
7064 #define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1
7065 /* The mask used to set the ALT_SYSMGR_ECC_L2_INJS register field value. */
7066 #define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002
7067 /* The mask used to clear the ALT_SYSMGR_ECC_L2_INJS register field value. */
7068 #define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd
7069 /* The reset value of the ALT_SYSMGR_ECC_L2_INJS register field. */
7070 #define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0
7071 /* Extracts the ALT_SYSMGR_ECC_L2_INJS field value from a register. */
7072 #define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1)
7073 /* Produces a ALT_SYSMGR_ECC_L2_INJS register field value suitable for setting the register. */
7074 #define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002)
7075 
7076 /*
7077  * Field : L2 Data RAM ECC inject double bit, non-correctable error - injd
7078  *
7079  * Changing this bit from zero to one injects a double, non-correctable error into
7080  * the L2 Data RAM. This only injects one double bit error into the L2 Data RAM.
7081  *
7082  * Field Access Macros:
7083  *
7084  */
7085 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */
7086 #define ALT_SYSMGR_ECC_L2_INJD_LSB 2
7087 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_L2_INJD register field. */
7088 #define ALT_SYSMGR_ECC_L2_INJD_MSB 2
7089 /* The width in bits of the ALT_SYSMGR_ECC_L2_INJD register field. */
7090 #define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1
7091 /* The mask used to set the ALT_SYSMGR_ECC_L2_INJD register field value. */
7092 #define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004
7093 /* The mask used to clear the ALT_SYSMGR_ECC_L2_INJD register field value. */
7094 #define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb
7095 /* The reset value of the ALT_SYSMGR_ECC_L2_INJD register field. */
7096 #define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0
7097 /* Extracts the ALT_SYSMGR_ECC_L2_INJD field value from a register. */
7098 #define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2)
7099 /* Produces a ALT_SYSMGR_ECC_L2_INJD register field value suitable for setting the register. */
7100 #define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004)
7101 
7102 #ifndef __ASSEMBLY__
7103 /*
7104  * WARNING: The C register and register group struct declarations are provided for
7105  * convenience and illustrative purposes. They should, however, be used with
7106  * caution as the C language standard provides no guarantees about the alignment or
7107  * atomicity of device memory accesses. The recommended practice for writing
7108  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7109  * alt_write_word() functions.
7110  *
7111  * The struct declaration for register ALT_SYSMGR_ECC_L2.
7112  */
7113 struct ALT_SYSMGR_ECC_L2_s
7114 {
7115  uint32_t en : 1; /* L2 Data RAM ECC Enable */
7116  uint32_t injs : 1; /* L2 Data RAM ECC inject single, correctable Error */
7117  uint32_t injd : 1; /* L2 Data RAM ECC inject double bit, non-correctable error */
7118  uint32_t : 29; /* *UNDEFINED* */
7119 };
7120 
7121 /* The typedef declaration for register ALT_SYSMGR_ECC_L2. */
7122 typedef volatile struct ALT_SYSMGR_ECC_L2_s ALT_SYSMGR_ECC_L2_t;
7123 #endif /* __ASSEMBLY__ */
7124 
7125 /* The byte offset of the ALT_SYSMGR_ECC_L2 register from the beginning of the component. */
7126 #define ALT_SYSMGR_ECC_L2_OFST 0x0
7127 
7128 /*
7129  * Register : On-chip RAM ECC Enable Register - ocram
7130  *
7131  * This register is used to enable ECC on the On-chip RAM. ECC errors can be
7132  * injected into the write path using bits in this register. This register contains
7133  * interrupt status of the ECC single/double bit error.
7134  *
7135  * Only reset by a cold reset (ignores warm reset).
7136  *
7137  * Register Layout
7138  *
7139  * Bits | Access | Reset | Description
7140  * :-------|:-------|:------|:-------------------------------------------------------------------
7141  * [0] | RW | 0x0 | On-chip RAM ECC Enable
7142  * [1] | RW | 0x0 | On-chip RAM ECC inject single, correctable Error
7143  * [2] | RW | 0x0 | On-chip RAM ECC inject double bit, non-correctable error
7144  * [3] | RW | 0x0 | On-chip RAM ECC single, correctable error interrupt status
7145  * [4] | RW | 0x0 | On-chip RAM ECC double bit, non-correctable error interrupt status
7146  * [31:5] | ??? | 0x0 | *UNDEFINED*
7147  *
7148  */
7149 /*
7150  * Field : On-chip RAM ECC Enable - en
7151  *
7152  * Enable ECC for On-chip RAM
7153  *
7154  * Field Access Macros:
7155  *
7156  */
7157 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7158 #define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0
7159 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7160 #define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0
7161 /* The width in bits of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7162 #define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1
7163 /* The mask used to set the ALT_SYSMGR_ECC_OCRAM_EN register field value. */
7164 #define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001
7165 /* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_EN register field value. */
7166 #define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe
7167 /* The reset value of the ALT_SYSMGR_ECC_OCRAM_EN register field. */
7168 #define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0
7169 /* Extracts the ALT_SYSMGR_ECC_OCRAM_EN field value from a register. */
7170 #define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0)
7171 /* Produces a ALT_SYSMGR_ECC_OCRAM_EN register field value suitable for setting the register. */
7172 #define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001)
7173 
7174 /*
7175  * Field : On-chip RAM ECC inject single, correctable Error - injs
7176  *
7177  * Changing this bit from zero to one injects a single, correctable error into the
7178  * On-chip RAM. This only injects one error into the On-chip RAM.
7179  *
7180  * Field Access Macros:
7181  *
7182  */
7183 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7184 #define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1
7185 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7186 #define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1
7187 /* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7188 #define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1
7189 /* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */
7190 #define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002
7191 /* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJS register field value. */
7192 #define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd
7193 /* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJS register field. */
7194 #define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0
7195 /* Extracts the ALT_SYSMGR_ECC_OCRAM_INJS field value from a register. */
7196 #define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1)
7197 /* Produces a ALT_SYSMGR_ECC_OCRAM_INJS register field value suitable for setting the register. */
7198 #define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002)
7199 
7200 /*
7201  * Field : On-chip RAM ECC inject double bit, non-correctable error - injd
7202  *
7203  * Changing this bit from zero to one injects a double, non-correctable error into
7204  * the On-chip RAM. This only injects one double bit error into the On-chip RAM.
7205  *
7206  * Field Access Macros:
7207  *
7208  */
7209 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7210 #define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2
7211 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7212 #define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2
7213 /* The width in bits of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7214 #define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1
7215 /* The mask used to set the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */
7216 #define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004
7217 /* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_INJD register field value. */
7218 #define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb
7219 /* The reset value of the ALT_SYSMGR_ECC_OCRAM_INJD register field. */
7220 #define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0
7221 /* Extracts the ALT_SYSMGR_ECC_OCRAM_INJD field value from a register. */
7222 #define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2)
7223 /* Produces a ALT_SYSMGR_ECC_OCRAM_INJD register field value suitable for setting the register. */
7224 #define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004)
7225 
7226 /*
7227  * Field : On-chip RAM ECC single, correctable error interrupt status - serr
7228  *
7229  * This bit is an interrupt status bit for On-chip RAM ECC single, correctable
7230  * error. It is set by hardware when single, correctable error occurs in On-chip
7231  * RAM. Software needs to write 1 into this bit to clear the interrupt status.
7232  *
7233  * Field Access Macros:
7234  *
7235  */
7236 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7237 #define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3
7238 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7239 #define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3
7240 /* The width in bits of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7241 #define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1
7242 /* The mask used to set the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */
7243 #define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008
7244 /* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_SERR register field value. */
7245 #define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7
7246 /* The reset value of the ALT_SYSMGR_ECC_OCRAM_SERR register field. */
7247 #define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0
7248 /* Extracts the ALT_SYSMGR_ECC_OCRAM_SERR field value from a register. */
7249 #define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3)
7250 /* Produces a ALT_SYSMGR_ECC_OCRAM_SERR register field value suitable for setting the register. */
7251 #define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008)
7252 
7253 /*
7254  * Field : On-chip RAM ECC double bit, non-correctable error interrupt status - derr
7255  *
7256  * This bit is an interrupt status bit for On-chip RAM ECC double bit, non-
7257  * correctable error. It is set by hardware when double bit, non-correctable error
7258  * occurs in On-chip RAM. Software needs to write 1 into this bit to clear the
7259  * interrupt status.
7260  *
7261  * Field Access Macros:
7262  *
7263  */
7264 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7265 #define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4
7266 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7267 #define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4
7268 /* The width in bits of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7269 #define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1
7270 /* The mask used to set the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */
7271 #define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010
7272 /* The mask used to clear the ALT_SYSMGR_ECC_OCRAM_DERR register field value. */
7273 #define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef
7274 /* The reset value of the ALT_SYSMGR_ECC_OCRAM_DERR register field. */
7275 #define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0
7276 /* Extracts the ALT_SYSMGR_ECC_OCRAM_DERR field value from a register. */
7277 #define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4)
7278 /* Produces a ALT_SYSMGR_ECC_OCRAM_DERR register field value suitable for setting the register. */
7279 #define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010)
7280 
7281 #ifndef __ASSEMBLY__
7282 /*
7283  * WARNING: The C register and register group struct declarations are provided for
7284  * convenience and illustrative purposes. They should, however, be used with
7285  * caution as the C language standard provides no guarantees about the alignment or
7286  * atomicity of device memory accesses. The recommended practice for writing
7287  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7288  * alt_write_word() functions.
7289  *
7290  * The struct declaration for register ALT_SYSMGR_ECC_OCRAM.
7291  */
7292 struct ALT_SYSMGR_ECC_OCRAM_s
7293 {
7294  uint32_t en : 1; /* On-chip RAM ECC Enable */
7295  uint32_t injs : 1; /* On-chip RAM ECC inject single, correctable Error */
7296  uint32_t injd : 1; /* On-chip RAM ECC inject double bit, non-correctable error */
7297  uint32_t serr : 1; /* On-chip RAM ECC single, correctable error interrupt status */
7298  uint32_t derr : 1; /* On-chip RAM ECC double bit, non-correctable error interrupt status */
7299  uint32_t : 27; /* *UNDEFINED* */
7300 };
7301 
7302 /* The typedef declaration for register ALT_SYSMGR_ECC_OCRAM. */
7303 typedef volatile struct ALT_SYSMGR_ECC_OCRAM_s ALT_SYSMGR_ECC_OCRAM_t;
7304 #endif /* __ASSEMBLY__ */
7305 
7306 /* The byte offset of the ALT_SYSMGR_ECC_OCRAM register from the beginning of the component. */
7307 #define ALT_SYSMGR_ECC_OCRAM_OFST 0x4
7308 
7309 /*
7310  * Register : USB0 RAM ECC Enable Register - usb0
7311  *
7312  * This register is used to enable ECC on the USB0 RAM. ECC errors can be injected
7313  * into the write path using bits in this register. This register contains
7314  * interrupt status of the ECC single/double bit error.
7315  *
7316  * Only reset by a cold reset (ignores warm reset).
7317  *
7318  * Register Layout
7319  *
7320  * Bits | Access | Reset | Description
7321  * :-------|:-------|:------|:----------------------------------------------------------------
7322  * [0] | RW | 0x0 | USB0 RAM ECC Enable
7323  * [1] | RW | 0x0 | USB0 RAM ECC inject single, correctable Error
7324  * [2] | RW | 0x0 | USB0 RAM ECC inject double bit, non-correctable error
7325  * [3] | RW | 0x0 | USB0 RAM ECC single, correctable error interrupt status
7326  * [4] | RW | 0x0 | USB0 RAM ECC double bit, non-correctable error interrupt status
7327  * [31:5] | ??? | 0x0 | *UNDEFINED*
7328  *
7329  */
7330 /*
7331  * Field : USB0 RAM ECC Enable - en
7332  *
7333  * Enable ECC for USB0 RAM
7334  *
7335  * Field Access Macros:
7336  *
7337  */
7338 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */
7339 #define ALT_SYSMGR_ECC_USB0_EN_LSB 0
7340 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_EN register field. */
7341 #define ALT_SYSMGR_ECC_USB0_EN_MSB 0
7342 /* The width in bits of the ALT_SYSMGR_ECC_USB0_EN register field. */
7343 #define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1
7344 /* The mask used to set the ALT_SYSMGR_ECC_USB0_EN register field value. */
7345 #define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001
7346 /* The mask used to clear the ALT_SYSMGR_ECC_USB0_EN register field value. */
7347 #define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe
7348 /* The reset value of the ALT_SYSMGR_ECC_USB0_EN register field. */
7349 #define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0
7350 /* Extracts the ALT_SYSMGR_ECC_USB0_EN field value from a register. */
7351 #define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0)
7352 /* Produces a ALT_SYSMGR_ECC_USB0_EN register field value suitable for setting the register. */
7353 #define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001)
7354 
7355 /*
7356  * Field : USB0 RAM ECC inject single, correctable Error - injs
7357  *
7358  * Changing this bit from zero to one injects a single, correctable error into the
7359  * USB0 RAM. This only injects one error into the USB0 RAM.
7360  *
7361  * Field Access Macros:
7362  *
7363  */
7364 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7365 #define ALT_SYSMGR_ECC_USB0_INJS_LSB 1
7366 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7367 #define ALT_SYSMGR_ECC_USB0_INJS_MSB 1
7368 /* The width in bits of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7369 #define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1
7370 /* The mask used to set the ALT_SYSMGR_ECC_USB0_INJS register field value. */
7371 #define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002
7372 /* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJS register field value. */
7373 #define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd
7374 /* The reset value of the ALT_SYSMGR_ECC_USB0_INJS register field. */
7375 #define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0
7376 /* Extracts the ALT_SYSMGR_ECC_USB0_INJS field value from a register. */
7377 #define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1)
7378 /* Produces a ALT_SYSMGR_ECC_USB0_INJS register field value suitable for setting the register. */
7379 #define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002)
7380 
7381 /*
7382  * Field : USB0 RAM ECC inject double bit, non-correctable error - injd
7383  *
7384  * Changing this bit from zero to one injects a double, non-correctable error into
7385  * the USB0 RAM. This only injects one double bit error into the USB0 RAM.
7386  *
7387  * Field Access Macros:
7388  *
7389  */
7390 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7391 #define ALT_SYSMGR_ECC_USB0_INJD_LSB 2
7392 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7393 #define ALT_SYSMGR_ECC_USB0_INJD_MSB 2
7394 /* The width in bits of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7395 #define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1
7396 /* The mask used to set the ALT_SYSMGR_ECC_USB0_INJD register field value. */
7397 #define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004
7398 /* The mask used to clear the ALT_SYSMGR_ECC_USB0_INJD register field value. */
7399 #define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb
7400 /* The reset value of the ALT_SYSMGR_ECC_USB0_INJD register field. */
7401 #define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0
7402 /* Extracts the ALT_SYSMGR_ECC_USB0_INJD field value from a register. */
7403 #define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2)
7404 /* Produces a ALT_SYSMGR_ECC_USB0_INJD register field value suitable for setting the register. */
7405 #define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004)
7406 
7407 /*
7408  * Field : USB0 RAM ECC single, correctable error interrupt status - serr
7409  *
7410  * This bit is an interrupt status bit for USB0 RAM ECC single, correctable error.
7411  * It is set by hardware when single, correctable error occurs in USB0 RAM.
7412  * Software needs to write 1 into this bit to clear the interrupt status.
7413  *
7414  * Field Access Macros:
7415  *
7416  */
7417 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7418 #define ALT_SYSMGR_ECC_USB0_SERR_LSB 3
7419 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7420 #define ALT_SYSMGR_ECC_USB0_SERR_MSB 3
7421 /* The width in bits of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7422 #define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1
7423 /* The mask used to set the ALT_SYSMGR_ECC_USB0_SERR register field value. */
7424 #define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008
7425 /* The mask used to clear the ALT_SYSMGR_ECC_USB0_SERR register field value. */
7426 #define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7
7427 /* The reset value of the ALT_SYSMGR_ECC_USB0_SERR register field. */
7428 #define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0
7429 /* Extracts the ALT_SYSMGR_ECC_USB0_SERR field value from a register. */
7430 #define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3)
7431 /* Produces a ALT_SYSMGR_ECC_USB0_SERR register field value suitable for setting the register. */
7432 #define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008)
7433 
7434 /*
7435  * Field : USB0 RAM ECC double bit, non-correctable error interrupt status - derr
7436  *
7437  * This bit is an interrupt status bit for USB0 RAM ECC double bit, non-correctable
7438  * error. It is set by hardware when double bit, non-correctable error occurs in
7439  * USB0 RAM. Software needs to write 1 into this bit to clear the interrupt status.
7440  *
7441  * Field Access Macros:
7442  *
7443  */
7444 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7445 #define ALT_SYSMGR_ECC_USB0_DERR_LSB 4
7446 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7447 #define ALT_SYSMGR_ECC_USB0_DERR_MSB 4
7448 /* The width in bits of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7449 #define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1
7450 /* The mask used to set the ALT_SYSMGR_ECC_USB0_DERR register field value. */
7451 #define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010
7452 /* The mask used to clear the ALT_SYSMGR_ECC_USB0_DERR register field value. */
7453 #define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef
7454 /* The reset value of the ALT_SYSMGR_ECC_USB0_DERR register field. */
7455 #define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0
7456 /* Extracts the ALT_SYSMGR_ECC_USB0_DERR field value from a register. */
7457 #define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4)
7458 /* Produces a ALT_SYSMGR_ECC_USB0_DERR register field value suitable for setting the register. */
7459 #define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010)
7460 
7461 #ifndef __ASSEMBLY__
7462 /*
7463  * WARNING: The C register and register group struct declarations are provided for
7464  * convenience and illustrative purposes. They should, however, be used with
7465  * caution as the C language standard provides no guarantees about the alignment or
7466  * atomicity of device memory accesses. The recommended practice for writing
7467  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7468  * alt_write_word() functions.
7469  *
7470  * The struct declaration for register ALT_SYSMGR_ECC_USB0.
7471  */
7472 struct ALT_SYSMGR_ECC_USB0_s
7473 {
7474  uint32_t en : 1; /* USB0 RAM ECC Enable */
7475  uint32_t injs : 1; /* USB0 RAM ECC inject single, correctable Error */
7476  uint32_t injd : 1; /* USB0 RAM ECC inject double bit, non-correctable error */
7477  uint32_t serr : 1; /* USB0 RAM ECC single, correctable error interrupt status */
7478  uint32_t derr : 1; /* USB0 RAM ECC double bit, non-correctable error interrupt status */
7479  uint32_t : 27; /* *UNDEFINED* */
7480 };
7481 
7482 /* The typedef declaration for register ALT_SYSMGR_ECC_USB0. */
7483 typedef volatile struct ALT_SYSMGR_ECC_USB0_s ALT_SYSMGR_ECC_USB0_t;
7484 #endif /* __ASSEMBLY__ */
7485 
7486 /* The byte offset of the ALT_SYSMGR_ECC_USB0 register from the beginning of the component. */
7487 #define ALT_SYSMGR_ECC_USB0_OFST 0x8
7488 
7489 /*
7490  * Register : USB1 RAM ECC Enable Register - usb1
7491  *
7492  * This register is used to enable ECC on the USB1 RAM. ECC errors can be injected
7493  * into the write path using bits in this register. This register contains
7494  * interrupt status of the ECC single/double bit error.
7495  *
7496  * Only reset by a cold reset (ignores warm reset).
7497  *
7498  * Register Layout
7499  *
7500  * Bits | Access | Reset | Description
7501  * :-------|:-------|:------|:----------------------------------------------------------------
7502  * [0] | RW | 0x0 | USB1 RAM ECC Enable
7503  * [1] | RW | 0x0 | USB1 RAM ECC inject single, correctable Error
7504  * [2] | RW | 0x0 | USB1 RAM ECC inject double bit, non-correctable error
7505  * [3] | RW | 0x0 | USB1 RAM ECC single, correctable error interrupt status
7506  * [4] | RW | 0x0 | USB1 RAM ECC double bit, non-correctable error interrupt status
7507  * [31:5] | ??? | 0x0 | *UNDEFINED*
7508  *
7509  */
7510 /*
7511  * Field : USB1 RAM ECC Enable - en
7512  *
7513  * Enable ECC for USB1 RAM
7514  *
7515  * Field Access Macros:
7516  *
7517  */
7518 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */
7519 #define ALT_SYSMGR_ECC_USB1_EN_LSB 0
7520 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_EN register field. */
7521 #define ALT_SYSMGR_ECC_USB1_EN_MSB 0
7522 /* The width in bits of the ALT_SYSMGR_ECC_USB1_EN register field. */
7523 #define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1
7524 /* The mask used to set the ALT_SYSMGR_ECC_USB1_EN register field value. */
7525 #define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001
7526 /* The mask used to clear the ALT_SYSMGR_ECC_USB1_EN register field value. */
7527 #define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe
7528 /* The reset value of the ALT_SYSMGR_ECC_USB1_EN register field. */
7529 #define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0
7530 /* Extracts the ALT_SYSMGR_ECC_USB1_EN field value from a register. */
7531 #define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0)
7532 /* Produces a ALT_SYSMGR_ECC_USB1_EN register field value suitable for setting the register. */
7533 #define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001)
7534 
7535 /*
7536  * Field : USB1 RAM ECC inject single, correctable Error - injs
7537  *
7538  * Changing this bit from zero to one injects a single, correctable error into the
7539  * USB1 RAM. This only injects one error into the USB1 RAM.
7540  *
7541  * Field Access Macros:
7542  *
7543  */
7544 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7545 #define ALT_SYSMGR_ECC_USB1_INJS_LSB 1
7546 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7547 #define ALT_SYSMGR_ECC_USB1_INJS_MSB 1
7548 /* The width in bits of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7549 #define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1
7550 /* The mask used to set the ALT_SYSMGR_ECC_USB1_INJS register field value. */
7551 #define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002
7552 /* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJS register field value. */
7553 #define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd
7554 /* The reset value of the ALT_SYSMGR_ECC_USB1_INJS register field. */
7555 #define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0
7556 /* Extracts the ALT_SYSMGR_ECC_USB1_INJS field value from a register. */
7557 #define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1)
7558 /* Produces a ALT_SYSMGR_ECC_USB1_INJS register field value suitable for setting the register. */
7559 #define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002)
7560 
7561 /*
7562  * Field : USB1 RAM ECC inject double bit, non-correctable error - injd
7563  *
7564  * Changing this bit from zero to one injects a double, non-correctable error into
7565  * the USB1 RAM. This only injects one double bit error into the USB1 RAM.
7566  *
7567  * Field Access Macros:
7568  *
7569  */
7570 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7571 #define ALT_SYSMGR_ECC_USB1_INJD_LSB 2
7572 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7573 #define ALT_SYSMGR_ECC_USB1_INJD_MSB 2
7574 /* The width in bits of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7575 #define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1
7576 /* The mask used to set the ALT_SYSMGR_ECC_USB1_INJD register field value. */
7577 #define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004
7578 /* The mask used to clear the ALT_SYSMGR_ECC_USB1_INJD register field value. */
7579 #define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb
7580 /* The reset value of the ALT_SYSMGR_ECC_USB1_INJD register field. */
7581 #define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0
7582 /* Extracts the ALT_SYSMGR_ECC_USB1_INJD field value from a register. */
7583 #define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2)
7584 /* Produces a ALT_SYSMGR_ECC_USB1_INJD register field value suitable for setting the register. */
7585 #define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004)
7586 
7587 /*
7588  * Field : USB1 RAM ECC single, correctable error interrupt status - serr
7589  *
7590  * This bit is an interrupt status bit for USB1 RAM ECC single, correctable error.
7591  * It is set by hardware when single, correctable error occurs in USB1 RAM.
7592  * Software needs to write 1 into this bit to clear the interrupt status.
7593  *
7594  * Field Access Macros:
7595  *
7596  */
7597 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7598 #define ALT_SYSMGR_ECC_USB1_SERR_LSB 3
7599 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7600 #define ALT_SYSMGR_ECC_USB1_SERR_MSB 3
7601 /* The width in bits of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7602 #define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1
7603 /* The mask used to set the ALT_SYSMGR_ECC_USB1_SERR register field value. */
7604 #define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008
7605 /* The mask used to clear the ALT_SYSMGR_ECC_USB1_SERR register field value. */
7606 #define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7
7607 /* The reset value of the ALT_SYSMGR_ECC_USB1_SERR register field. */
7608 #define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0
7609 /* Extracts the ALT_SYSMGR_ECC_USB1_SERR field value from a register. */
7610 #define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3)
7611 /* Produces a ALT_SYSMGR_ECC_USB1_SERR register field value suitable for setting the register. */
7612 #define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008)
7613 
7614 /*
7615  * Field : USB1 RAM ECC double bit, non-correctable error interrupt status - derr
7616  *
7617  * This bit is an interrupt status bit for USB1 RAM ECC double bit, non-correctable
7618  * error. It is set by hardware when double bit, non-correctable error occurs in
7619  * USB1 RAM. Software needs to write 1 into this bit to clear the interrupt status.
7620  *
7621  * Field Access Macros:
7622  *
7623  */
7624 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7625 #define ALT_SYSMGR_ECC_USB1_DERR_LSB 4
7626 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7627 #define ALT_SYSMGR_ECC_USB1_DERR_MSB 4
7628 /* The width in bits of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7629 #define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1
7630 /* The mask used to set the ALT_SYSMGR_ECC_USB1_DERR register field value. */
7631 #define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010
7632 /* The mask used to clear the ALT_SYSMGR_ECC_USB1_DERR register field value. */
7633 #define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef
7634 /* The reset value of the ALT_SYSMGR_ECC_USB1_DERR register field. */
7635 #define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0
7636 /* Extracts the ALT_SYSMGR_ECC_USB1_DERR field value from a register. */
7637 #define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4)
7638 /* Produces a ALT_SYSMGR_ECC_USB1_DERR register field value suitable for setting the register. */
7639 #define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010)
7640 
7641 #ifndef __ASSEMBLY__
7642 /*
7643  * WARNING: The C register and register group struct declarations are provided for
7644  * convenience and illustrative purposes. They should, however, be used with
7645  * caution as the C language standard provides no guarantees about the alignment or
7646  * atomicity of device memory accesses. The recommended practice for writing
7647  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7648  * alt_write_word() functions.
7649  *
7650  * The struct declaration for register ALT_SYSMGR_ECC_USB1.
7651  */
7652 struct ALT_SYSMGR_ECC_USB1_s
7653 {
7654  uint32_t en : 1; /* USB1 RAM ECC Enable */
7655  uint32_t injs : 1; /* USB1 RAM ECC inject single, correctable Error */
7656  uint32_t injd : 1; /* USB1 RAM ECC inject double bit, non-correctable error */
7657  uint32_t serr : 1; /* USB1 RAM ECC single, correctable error interrupt status */
7658  uint32_t derr : 1; /* USB1 RAM ECC double bit, non-correctable error interrupt status */
7659  uint32_t : 27; /* *UNDEFINED* */
7660 };
7661 
7662 /* The typedef declaration for register ALT_SYSMGR_ECC_USB1. */
7663 typedef volatile struct ALT_SYSMGR_ECC_USB1_s ALT_SYSMGR_ECC_USB1_t;
7664 #endif /* __ASSEMBLY__ */
7665 
7666 /* The byte offset of the ALT_SYSMGR_ECC_USB1 register from the beginning of the component. */
7667 #define ALT_SYSMGR_ECC_USB1_OFST 0xc
7668 
7669 /*
7670  * Register : EMAC0 RAM ECC Enable Register - emac0
7671  *
7672  * This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected
7673  * into the write path using bits in this register. This register contains
7674  * interrupt status of the ECC single/double bit error.
7675  *
7676  * Only reset by a cold reset (ignores warm reset).
7677  *
7678  * Register Layout
7679  *
7680  * Bits | Access | Reset | Description
7681  * :-------|:-------|:------|:------------------------------------------------------------------------
7682  * [0] | RW | 0x0 | EMAC0 RAM ECC Enable
7683  * [1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error
7684  * [2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error
7685  * [3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error
7686  * [4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error
7687  * [5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status
7688  * [6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status
7689  * [7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status
7690  * [8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status
7691  * [31:9] | ??? | 0x0 | *UNDEFINED*
7692  *
7693  */
7694 /*
7695  * Field : EMAC0 RAM ECC Enable - en
7696  *
7697  * Enable ECC for EMAC0 RAM
7698  *
7699  * Field Access Macros:
7700  *
7701  */
7702 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7703 #define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0
7704 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7705 #define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0
7706 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7707 #define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1
7708 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value. */
7709 #define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001
7710 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value. */
7711 #define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe
7712 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field. */
7713 #define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0
7714 /* Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register. */
7715 #define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0)
7716 /* Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register. */
7717 #define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001)
7718 
7719 /*
7720  * Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs
7721  *
7722  * Changing this bit from zero to one injects a single, correctable error into the
7723  * EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM.
7724  *
7725  * Field Access Macros:
7726  *
7727  */
7728 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7729 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1
7730 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7731 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1
7732 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7733 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1
7734 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */
7735 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002
7736 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value. */
7737 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd
7738 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field. */
7739 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0
7740 /* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register. */
7741 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
7742 /* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register. */
7743 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
7744 
7745 /*
7746  * Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd
7747  *
7748  * Changing this bit from zero to one injects a double, non-correctable error into
7749  * the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0
7750  * TXFIFO RAM.
7751  *
7752  * Field Access Macros:
7753  *
7754  */
7755 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7756 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2
7757 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7758 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2
7759 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7760 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1
7761 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */
7762 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004
7763 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value. */
7764 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb
7765 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field. */
7766 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0
7767 /* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register. */
7768 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
7769 /* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register. */
7770 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
7771 
7772 /*
7773  * Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs
7774  *
7775  * Changing this bit from zero to one injects a single, correctable error into the
7776  * EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM.
7777  *
7778  * Field Access Macros:
7779  *
7780  */
7781 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7782 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3
7783 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7784 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3
7785 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7786 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1
7787 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */
7788 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008
7789 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value. */
7790 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7
7791 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field. */
7792 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0
7793 /* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register. */
7794 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
7795 /* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register. */
7796 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
7797 
7798 /*
7799  * Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd
7800  *
7801  * Changing this bit from zero to one injects a double, non-correctable error into
7802  * the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0
7803  * RXFIFO RAM.
7804  *
7805  * Field Access Macros:
7806  *
7807  */
7808 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7809 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4
7810 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7811 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4
7812 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7813 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1
7814 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */
7815 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010
7816 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value. */
7817 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef
7818 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field. */
7819 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0
7820 /* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register. */
7821 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
7822 /* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register. */
7823 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
7824 
7825 /*
7826  * Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr
7827  *
7828  * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable
7829  * error. It is set by hardware when single, correctable error occurs in EMAC0
7830  * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
7831  * status.
7832  *
7833  * Field Access Macros:
7834  *
7835  */
7836 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7837 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5
7838 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7839 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5
7840 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7841 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1
7842 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */
7843 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020
7844 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value. */
7845 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf
7846 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field. */
7847 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0
7848 /* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register. */
7849 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
7850 /* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register. */
7851 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
7852 
7853 /*
7854  * Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr
7855  *
7856  * This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non-
7857  * correctable error. It is set by hardware when double bit, non-correctable error
7858  * occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the
7859  * interrupt status.
7860  *
7861  * Field Access Macros:
7862  *
7863  */
7864 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7865 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6
7866 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7867 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6
7868 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7869 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1
7870 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */
7871 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040
7872 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value. */
7873 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf
7874 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field. */
7875 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0
7876 /* Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register. */
7877 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
7878 /* Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register. */
7879 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
7880 
7881 /*
7882  * Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr
7883  *
7884  * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable
7885  * error. It is set by hardware when single, correctable error occurs in EMAC0
7886  * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
7887  * status.
7888  *
7889  * Field Access Macros:
7890  *
7891  */
7892 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7893 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7
7894 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7895 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7
7896 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7897 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1
7898 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */
7899 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080
7900 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value. */
7901 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f
7902 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field. */
7903 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0
7904 /* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register. */
7905 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
7906 /* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register. */
7907 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
7908 
7909 /*
7910  * Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr
7911  *
7912  * This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non-
7913  * correctable error. It is set by hardware when double bit, non-correctable error
7914  * occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the
7915  * interrupt status.
7916  *
7917  * Field Access Macros:
7918  *
7919  */
7920 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7921 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8
7922 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7923 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8
7924 /* The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7925 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1
7926 /* The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */
7927 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100
7928 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value. */
7929 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff
7930 /* The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field. */
7931 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0
7932 /* Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register. */
7933 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
7934 /* Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register. */
7935 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
7936 
7937 #ifndef __ASSEMBLY__
7938 /*
7939  * WARNING: The C register and register group struct declarations are provided for
7940  * convenience and illustrative purposes. They should, however, be used with
7941  * caution as the C language standard provides no guarantees about the alignment or
7942  * atomicity of device memory accesses. The recommended practice for writing
7943  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
7944  * alt_write_word() functions.
7945  *
7946  * The struct declaration for register ALT_SYSMGR_ECC_EMAC0.
7947  */
7948 struct ALT_SYSMGR_ECC_EMAC0_s
7949 {
7950  uint32_t en : 1; /* EMAC0 RAM ECC Enable */
7951  uint32_t txfifoinjs : 1; /* EMAC0 TXFIFO RAM ECC inject single, correctable Error */
7952  uint32_t txfifoinjd : 1; /* EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error */
7953  uint32_t rxfifoinjs : 1; /* EMAC0 RXFIFO RAM ECC inject single, correctable Error */
7954  uint32_t rxfifoinjd : 1; /* EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error */
7955  uint32_t txfifoserr : 1; /* EMAC0 TXFIFO RAM ECC single, correctable error interrupt status */
7956  uint32_t txfifoderr : 1; /* EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status */
7957  uint32_t rxfifoserr : 1; /* EMAC0 RXFIFO RAM ECC single, correctable error interrupt status */
7958  uint32_t rxfifoderr : 1; /* EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status */
7959  uint32_t : 23; /* *UNDEFINED* */
7960 };
7961 
7962 /* The typedef declaration for register ALT_SYSMGR_ECC_EMAC0. */
7963 typedef volatile struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t;
7964 #endif /* __ASSEMBLY__ */
7965 
7966 /* The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component. */
7967 #define ALT_SYSMGR_ECC_EMAC0_OFST 0x10
7968 
7969 /*
7970  * Register : EMAC1 RAM ECC Enable Register - emac1
7971  *
7972  * This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected
7973  * into the write path using bits in this register. This register contains
7974  * interrupt status of the ECC single/double bit error.
7975  *
7976  * Only reset by a cold reset (ignores warm reset).
7977  *
7978  * Register Layout
7979  *
7980  * Bits | Access | Reset | Description
7981  * :-------|:-------|:------|:------------------------------------------------------------------------
7982  * [0] | RW | 0x0 | EMAC1 RAM ECC Enable
7983  * [1] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject single, correctable Error
7984  * [2] | RW | 0x0 | EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error
7985  * [3] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject single, correctable Error
7986  * [4] | RW | 0x0 | EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error
7987  * [5] | RW | 0x0 | EMAC1 TXFIFO RAM ECC single, correctable error interrupt status
7988  * [6] | RW | 0x0 | EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status
7989  * [7] | RW | 0x0 | EMAC1 RXFIFO RAM ECC single, correctable error interrupt status
7990  * [8] | RW | 0x0 | EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status
7991  * [31:9] | ??? | 0x0 | *UNDEFINED*
7992  *
7993  */
7994 /*
7995  * Field : EMAC1 RAM ECC Enable - en
7996  *
7997  * Enable ECC for EMAC1 RAM
7998  *
7999  * Field Access Macros:
8000  *
8001  */
8002 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8003 #define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0
8004 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8005 #define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0
8006 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8007 #define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1
8008 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_EN register field value. */
8009 #define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001
8010 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_EN register field value. */
8011 #define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe
8012 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_EN register field. */
8013 #define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0
8014 /* Extracts the ALT_SYSMGR_ECC_EMAC1_EN field value from a register. */
8015 #define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0)
8016 /* Produces a ALT_SYSMGR_ECC_EMAC1_EN register field value suitable for setting the register. */
8017 #define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001)
8018 
8019 /*
8020  * Field : EMAC1 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs
8021  *
8022  * Changing this bit from zero to one injects a single, correctable error into the
8023  * EMAC1 TXFIFO RAM. This only injects one error into the EMAC1 TXFIFO RAM.
8024  *
8025  * Field Access Macros:
8026  *
8027  */
8028 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8029 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1
8030 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8031 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1
8032 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8033 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1
8034 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */
8035 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002
8036 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value. */
8037 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd
8038 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field. */
8039 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0
8040 /* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS field value from a register. */
8041 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
8042 /* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS register field value suitable for setting the register. */
8043 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
8044 
8045 /*
8046  * Field : EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd
8047  *
8048  * Changing this bit from zero to one injects a double, non-correctable error into
8049  * the EMAC1 TXFIFO RAM. This only injects one double bit error into the EMAC1
8050  * TXFIFO RAM.
8051  *
8052  * Field Access Macros:
8053  *
8054  */
8055 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8056 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2
8057 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8058 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2
8059 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8060 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1
8061 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */
8062 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004
8063 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value. */
8064 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb
8065 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field. */
8066 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0
8067 /* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD field value from a register. */
8068 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
8069 /* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD register field value suitable for setting the register. */
8070 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
8071 
8072 /*
8073  * Field : EMAC1 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs
8074  *
8075  * Changing this bit from zero to one injects a single, correctable error into the
8076  * EMAC1 RXFIFO RAM. This only injects one error into the EMAC1 RXFIFO RAM.
8077  *
8078  * Field Access Macros:
8079  *
8080  */
8081 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8082 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3
8083 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8084 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3
8085 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8086 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1
8087 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */
8088 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008
8089 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value. */
8090 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7
8091 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field. */
8092 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0
8093 /* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS field value from a register. */
8094 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8095 /* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS register field value suitable for setting the register. */
8096 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8097 
8098 /*
8099  * Field : EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd
8100  *
8101  * Changing this bit from zero to one injects a double, non-correctable error into
8102  * the EMAC1 RXFIFO RAM. This only injects one double bit error into the EMAC1
8103  * RXFIFO RAM.
8104  *
8105  * Field Access Macros:
8106  *
8107  */
8108 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8109 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4
8110 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8111 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4
8112 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8113 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1
8114 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */
8115 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010
8116 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value. */
8117 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef
8118 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field. */
8119 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0
8120 /* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD field value from a register. */
8121 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8122 /* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD register field value suitable for setting the register. */
8123 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8124 
8125 /*
8126  * Field : EMAC1 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr
8127  *
8128  * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC single, correctable
8129  * error. It is set by hardware when single, correctable error occurs in EMAC1
8130  * TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
8131  * status.
8132  *
8133  * Field Access Macros:
8134  *
8135  */
8136 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8137 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5
8138 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8139 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5
8140 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8141 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1
8142 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */
8143 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020
8144 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value. */
8145 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf
8146 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field. */
8147 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0
8148 /* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR field value from a register. */
8149 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
8150 /* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR register field value suitable for setting the register. */
8151 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
8152 
8153 /*
8154  * Field : EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr
8155  *
8156  * This bit is an interrupt status bit for EMAC1 TXFIFO RAM ECC double bit, non-
8157  * correctable error. It is set by hardware when double bit, non-correctable error
8158  * occurs in EMAC1 TXFIFO RAM. Software needs to write 1 into this bit to clear the
8159  * interrupt status.
8160  *
8161  * Field Access Macros:
8162  *
8163  */
8164 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8165 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6
8166 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8167 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6
8168 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8169 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1
8170 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */
8171 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040
8172 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value. */
8173 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf
8174 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field. */
8175 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0
8176 /* Extracts the ALT_SYSMGR_ECC_EMAC1_TXFIFODERR field value from a register. */
8177 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
8178 /* Produces a ALT_SYSMGR_ECC_EMAC1_TXFIFODERR register field value suitable for setting the register. */
8179 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
8180 
8181 /*
8182  * Field : EMAC1 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr
8183  *
8184  * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC single, correctable
8185  * error. It is set by hardware when single, correctable error occurs in EMAC1
8186  * RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
8187  * status.
8188  *
8189  * Field Access Macros:
8190  *
8191  */
8192 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8193 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7
8194 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8195 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7
8196 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8197 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1
8198 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */
8199 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080
8200 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value. */
8201 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f
8202 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field. */
8203 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0
8204 /* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR field value from a register. */
8205 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
8206 /* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR register field value suitable for setting the register. */
8207 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
8208 
8209 /*
8210  * Field : EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr
8211  *
8212  * This bit is an interrupt status bit for EMAC1 RXFIFO RAM ECC double bit, non-
8213  * correctable error. It is set by hardware when double bit, non-correctable error
8214  * occurs in EMAC1 RXFIFO RAM. Software needs to write 1 into this bit to clear the
8215  * interrupt status.
8216  *
8217  * Field Access Macros:
8218  *
8219  */
8220 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8221 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8
8222 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8223 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8
8224 /* The width in bits of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8225 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1
8226 /* The mask used to set the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */
8227 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100
8228 /* The mask used to clear the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value. */
8229 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff
8230 /* The reset value of the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field. */
8231 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0
8232 /* Extracts the ALT_SYSMGR_ECC_EMAC1_RXFIFODERR field value from a register. */
8233 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
8234 /* Produces a ALT_SYSMGR_ECC_EMAC1_RXFIFODERR register field value suitable for setting the register. */
8235 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
8236 
8237 #ifndef __ASSEMBLY__
8238 /*
8239  * WARNING: The C register and register group struct declarations are provided for
8240  * convenience and illustrative purposes. They should, however, be used with
8241  * caution as the C language standard provides no guarantees about the alignment or
8242  * atomicity of device memory accesses. The recommended practice for writing
8243  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8244  * alt_write_word() functions.
8245  *
8246  * The struct declaration for register ALT_SYSMGR_ECC_EMAC1.
8247  */
8248 struct ALT_SYSMGR_ECC_EMAC1_s
8249 {
8250  uint32_t en : 1; /* EMAC1 RAM ECC Enable */
8251  uint32_t txfifoinjs : 1; /* EMAC1 TXFIFO RAM ECC inject single, correctable Error */
8252  uint32_t txfifoinjd : 1; /* EMAC1 TXFIFO RAM ECC inject double bit, non-correctable error */
8253  uint32_t rxfifoinjs : 1; /* EMAC1 RXFIFO RAM ECC inject single, correctable Error */
8254  uint32_t rxfifoinjd : 1; /* EMAC1 RXFIFO RAM ECC inject double bit, non-correctable error */
8255  uint32_t txfifoserr : 1; /* EMAC1 TXFIFO RAM ECC single, correctable error interrupt status */
8256  uint32_t txfifoderr : 1; /* EMAC1 TXFIFO RAM ECC double bit, non-correctable error interrupt status */
8257  uint32_t rxfifoserr : 1; /* EMAC1 RXFIFO RAM ECC single, correctable error interrupt status */
8258  uint32_t rxfifoderr : 1; /* EMAC1 RXFIFO RAM ECC double bit, non-correctable error interrupt status */
8259  uint32_t : 23; /* *UNDEFINED* */
8260 };
8261 
8262 /* The typedef declaration for register ALT_SYSMGR_ECC_EMAC1. */
8263 typedef volatile struct ALT_SYSMGR_ECC_EMAC1_s ALT_SYSMGR_ECC_EMAC1_t;
8264 #endif /* __ASSEMBLY__ */
8265 
8266 /* The byte offset of the ALT_SYSMGR_ECC_EMAC1 register from the beginning of the component. */
8267 #define ALT_SYSMGR_ECC_EMAC1_OFST 0x14
8268 
8269 /*
8270  * Register : DMA RAM ECC Enable Register - dma
8271  *
8272  * This register is used to enable ECC on the DMA RAM. ECC errors can be injected
8273  * into the write path using bits in this register. This register contains
8274  * interrupt status of the ECC single/double bit error.
8275  *
8276  * Only reset by a cold reset (ignores warm reset).
8277  *
8278  * Register Layout
8279  *
8280  * Bits | Access | Reset | Description
8281  * :-------|:-------|:------|:---------------------------------------------------------------
8282  * [0] | RW | 0x0 | DMA RAM ECC Enable
8283  * [1] | RW | 0x0 | DMA RAM ECC inject single, correctable Error
8284  * [2] | RW | 0x0 | DMA RAM ECC inject double bit, non-correctable error
8285  * [3] | RW | 0x0 | DMA RAM ECC single, correctable error interrupt status
8286  * [4] | RW | 0x0 | DMA RAM ECC double bit, non-correctable error interrupt status
8287  * [31:5] | ??? | 0x0 | *UNDEFINED*
8288  *
8289  */
8290 /*
8291  * Field : DMA RAM ECC Enable - en
8292  *
8293  * Enable ECC for DMA RAM
8294  *
8295  * Field Access Macros:
8296  *
8297  */
8298 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */
8299 #define ALT_SYSMGR_ECC_DMA_EN_LSB 0
8300 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_EN register field. */
8301 #define ALT_SYSMGR_ECC_DMA_EN_MSB 0
8302 /* The width in bits of the ALT_SYSMGR_ECC_DMA_EN register field. */
8303 #define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1
8304 /* The mask used to set the ALT_SYSMGR_ECC_DMA_EN register field value. */
8305 #define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001
8306 /* The mask used to clear the ALT_SYSMGR_ECC_DMA_EN register field value. */
8307 #define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe
8308 /* The reset value of the ALT_SYSMGR_ECC_DMA_EN register field. */
8309 #define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0
8310 /* Extracts the ALT_SYSMGR_ECC_DMA_EN field value from a register. */
8311 #define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0)
8312 /* Produces a ALT_SYSMGR_ECC_DMA_EN register field value suitable for setting the register. */
8313 #define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001)
8314 
8315 /*
8316  * Field : DMA RAM ECC inject single, correctable Error - injs
8317  *
8318  * Changing this bit from zero to one injects a single, correctable error into the
8319  * DMA RAM. This only injects one error into the DMA RAM.
8320  *
8321  * Field Access Macros:
8322  *
8323  */
8324 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8325 #define ALT_SYSMGR_ECC_DMA_INJS_LSB 1
8326 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8327 #define ALT_SYSMGR_ECC_DMA_INJS_MSB 1
8328 /* The width in bits of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8329 #define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1
8330 /* The mask used to set the ALT_SYSMGR_ECC_DMA_INJS register field value. */
8331 #define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002
8332 /* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJS register field value. */
8333 #define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd
8334 /* The reset value of the ALT_SYSMGR_ECC_DMA_INJS register field. */
8335 #define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0
8336 /* Extracts the ALT_SYSMGR_ECC_DMA_INJS field value from a register. */
8337 #define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1)
8338 /* Produces a ALT_SYSMGR_ECC_DMA_INJS register field value suitable for setting the register. */
8339 #define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002)
8340 
8341 /*
8342  * Field : DMA RAM ECC inject double bit, non-correctable error - injd
8343  *
8344  * Changing this bit from zero to one injects a double, non-correctable error into
8345  * the DMA RAM. This only injects one double bit error into the DMA RAM.
8346  *
8347  * Field Access Macros:
8348  *
8349  */
8350 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8351 #define ALT_SYSMGR_ECC_DMA_INJD_LSB 2
8352 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8353 #define ALT_SYSMGR_ECC_DMA_INJD_MSB 2
8354 /* The width in bits of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8355 #define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1
8356 /* The mask used to set the ALT_SYSMGR_ECC_DMA_INJD register field value. */
8357 #define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004
8358 /* The mask used to clear the ALT_SYSMGR_ECC_DMA_INJD register field value. */
8359 #define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb
8360 /* The reset value of the ALT_SYSMGR_ECC_DMA_INJD register field. */
8361 #define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0
8362 /* Extracts the ALT_SYSMGR_ECC_DMA_INJD field value from a register. */
8363 #define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2)
8364 /* Produces a ALT_SYSMGR_ECC_DMA_INJD register field value suitable for setting the register. */
8365 #define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004)
8366 
8367 /*
8368  * Field : DMA RAM ECC single, correctable error interrupt status - serr
8369  *
8370  * This bit is an interrupt status bit for DMA RAM ECC single, correctable error.
8371  * It is set by hardware when single, correctable error occurs in DMA RAM. Software
8372  * needs to write 1 into this bit to clear the interrupt status.
8373  *
8374  * Field Access Macros:
8375  *
8376  */
8377 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8378 #define ALT_SYSMGR_ECC_DMA_SERR_LSB 3
8379 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8380 #define ALT_SYSMGR_ECC_DMA_SERR_MSB 3
8381 /* The width in bits of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8382 #define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1
8383 /* The mask used to set the ALT_SYSMGR_ECC_DMA_SERR register field value. */
8384 #define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008
8385 /* The mask used to clear the ALT_SYSMGR_ECC_DMA_SERR register field value. */
8386 #define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7
8387 /* The reset value of the ALT_SYSMGR_ECC_DMA_SERR register field. */
8388 #define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0
8389 /* Extracts the ALT_SYSMGR_ECC_DMA_SERR field value from a register. */
8390 #define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3)
8391 /* Produces a ALT_SYSMGR_ECC_DMA_SERR register field value suitable for setting the register. */
8392 #define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008)
8393 
8394 /*
8395  * Field : DMA RAM ECC double bit, non-correctable error interrupt status - derr
8396  *
8397  * This bit is an interrupt status bit for DMA RAM ECC double bit, non-correctable
8398  * error. It is set by hardware when double bit, non-correctable error occurs in
8399  * DMA RAM. Software needs to write 1 into this bit to clear the interrupt status.
8400  *
8401  * Field Access Macros:
8402  *
8403  */
8404 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8405 #define ALT_SYSMGR_ECC_DMA_DERR_LSB 4
8406 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8407 #define ALT_SYSMGR_ECC_DMA_DERR_MSB 4
8408 /* The width in bits of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8409 #define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1
8410 /* The mask used to set the ALT_SYSMGR_ECC_DMA_DERR register field value. */
8411 #define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010
8412 /* The mask used to clear the ALT_SYSMGR_ECC_DMA_DERR register field value. */
8413 #define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef
8414 /* The reset value of the ALT_SYSMGR_ECC_DMA_DERR register field. */
8415 #define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0
8416 /* Extracts the ALT_SYSMGR_ECC_DMA_DERR field value from a register. */
8417 #define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4)
8418 /* Produces a ALT_SYSMGR_ECC_DMA_DERR register field value suitable for setting the register. */
8419 #define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010)
8420 
8421 #ifndef __ASSEMBLY__
8422 /*
8423  * WARNING: The C register and register group struct declarations are provided for
8424  * convenience and illustrative purposes. They should, however, be used with
8425  * caution as the C language standard provides no guarantees about the alignment or
8426  * atomicity of device memory accesses. The recommended practice for writing
8427  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8428  * alt_write_word() functions.
8429  *
8430  * The struct declaration for register ALT_SYSMGR_ECC_DMA.
8431  */
8432 struct ALT_SYSMGR_ECC_DMA_s
8433 {
8434  uint32_t en : 1; /* DMA RAM ECC Enable */
8435  uint32_t injs : 1; /* DMA RAM ECC inject single, correctable Error */
8436  uint32_t injd : 1; /* DMA RAM ECC inject double bit, non-correctable error */
8437  uint32_t serr : 1; /* DMA RAM ECC single, correctable error interrupt status */
8438  uint32_t derr : 1; /* DMA RAM ECC double bit, non-correctable error interrupt status */
8439  uint32_t : 27; /* *UNDEFINED* */
8440 };
8441 
8442 /* The typedef declaration for register ALT_SYSMGR_ECC_DMA. */
8443 typedef volatile struct ALT_SYSMGR_ECC_DMA_s ALT_SYSMGR_ECC_DMA_t;
8444 #endif /* __ASSEMBLY__ */
8445 
8446 /* The byte offset of the ALT_SYSMGR_ECC_DMA register from the beginning of the component. */
8447 #define ALT_SYSMGR_ECC_DMA_OFST 0x18
8448 
8449 /*
8450  * Register : CAN0 RAM ECC Enable Register - can0
8451  *
8452  * This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected
8453  * into the write path using bits in this register. This register contains
8454  * interrupt status of the ECC single/double bit error.
8455  *
8456  * Only reset by a cold reset (ignores warm reset).
8457  *
8458  * Register Layout
8459  *
8460  * Bits | Access | Reset | Description
8461  * :-------|:-------|:------|:----------------------------------------------------------------
8462  * [0] | RW | 0x0 | CAN0 RAM ECC Enable
8463  * [1] | RW | 0x0 | CAN0 RAM ECC inject single, correctable Error
8464  * [2] | RW | 0x0 | CAN0 RAM ECC inject double bit, non-correctable error
8465  * [3] | RW | 0x0 | CAN0 RAM ECC single, correctable error interrupt status
8466  * [4] | RW | 0x0 | CAN0 RAM ECC double bit, non-correctable error interrupt status
8467  * [31:5] | ??? | 0x0 | *UNDEFINED*
8468  *
8469  */
8470 /*
8471  * Field : CAN0 RAM ECC Enable - en
8472  *
8473  * Enable ECC for CAN0 RAM
8474  *
8475  * Field Access Macros:
8476  *
8477  */
8478 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8479 #define ALT_SYSMGR_ECC_CAN0_EN_LSB 0
8480 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8481 #define ALT_SYSMGR_ECC_CAN0_EN_MSB 0
8482 /* The width in bits of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8483 #define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1
8484 /* The mask used to set the ALT_SYSMGR_ECC_CAN0_EN register field value. */
8485 #define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001
8486 /* The mask used to clear the ALT_SYSMGR_ECC_CAN0_EN register field value. */
8487 #define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe
8488 /* The reset value of the ALT_SYSMGR_ECC_CAN0_EN register field. */
8489 #define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0
8490 /* Extracts the ALT_SYSMGR_ECC_CAN0_EN field value from a register. */
8491 #define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0)
8492 /* Produces a ALT_SYSMGR_ECC_CAN0_EN register field value suitable for setting the register. */
8493 #define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001)
8494 
8495 /*
8496  * Field : CAN0 RAM ECC inject single, correctable Error - injs
8497  *
8498  * Changing this bit from zero to one injects a single, correctable error into the
8499  * CAN0 RAM. This only injects one error into the CAN0 RAM.
8500  *
8501  * Field Access Macros:
8502  *
8503  */
8504 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8505 #define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1
8506 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8507 #define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1
8508 /* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8509 #define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1
8510 /* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJS register field value. */
8511 #define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002
8512 /* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJS register field value. */
8513 #define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd
8514 /* The reset value of the ALT_SYSMGR_ECC_CAN0_INJS register field. */
8515 #define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0
8516 /* Extracts the ALT_SYSMGR_ECC_CAN0_INJS field value from a register. */
8517 #define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1)
8518 /* Produces a ALT_SYSMGR_ECC_CAN0_INJS register field value suitable for setting the register. */
8519 #define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002)
8520 
8521 /*
8522  * Field : CAN0 RAM ECC inject double bit, non-correctable error - injd
8523  *
8524  * Changing this bit from zero to one injects a double, non-correctable error into
8525  * the CAN0 RAM. This only injects one double bit error into the CAN0 RAM.
8526  *
8527  * Field Access Macros:
8528  *
8529  */
8530 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8531 #define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2
8532 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8533 #define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2
8534 /* The width in bits of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8535 #define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1
8536 /* The mask used to set the ALT_SYSMGR_ECC_CAN0_INJD register field value. */
8537 #define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004
8538 /* The mask used to clear the ALT_SYSMGR_ECC_CAN0_INJD register field value. */
8539 #define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb
8540 /* The reset value of the ALT_SYSMGR_ECC_CAN0_INJD register field. */
8541 #define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0
8542 /* Extracts the ALT_SYSMGR_ECC_CAN0_INJD field value from a register. */
8543 #define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2)
8544 /* Produces a ALT_SYSMGR_ECC_CAN0_INJD register field value suitable for setting the register. */
8545 #define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004)
8546 
8547 /*
8548  * Field : CAN0 RAM ECC single, correctable error interrupt status - serr
8549  *
8550  * This bit is an interrupt status bit for CAN0 RAM ECC single, correctable error.
8551  * It is set by hardware when single, correctable error occurs in CAN0 RAM.
8552  * Software needs to write 1 into this bit to clear the interrupt status.
8553  *
8554  * Field Access Macros:
8555  *
8556  */
8557 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8558 #define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3
8559 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8560 #define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3
8561 /* The width in bits of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8562 #define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1
8563 /* The mask used to set the ALT_SYSMGR_ECC_CAN0_SERR register field value. */
8564 #define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008
8565 /* The mask used to clear the ALT_SYSMGR_ECC_CAN0_SERR register field value. */
8566 #define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7
8567 /* The reset value of the ALT_SYSMGR_ECC_CAN0_SERR register field. */
8568 #define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0
8569 /* Extracts the ALT_SYSMGR_ECC_CAN0_SERR field value from a register. */
8570 #define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3)
8571 /* Produces a ALT_SYSMGR_ECC_CAN0_SERR register field value suitable for setting the register. */
8572 #define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008)
8573 
8574 /*
8575  * Field : CAN0 RAM ECC double bit, non-correctable error interrupt status - derr
8576  *
8577  * This bit is an interrupt status bit for CAN0 RAM ECC double bit, non-correctable
8578  * error. It is set by hardware when double bit, non-correctable error occurs in
8579  * CAN0 RAM. Software needs to write 1 into this bit to clear the interrupt status.
8580  *
8581  * Field Access Macros:
8582  *
8583  */
8584 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8585 #define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4
8586 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8587 #define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4
8588 /* The width in bits of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8589 #define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1
8590 /* The mask used to set the ALT_SYSMGR_ECC_CAN0_DERR register field value. */
8591 #define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010
8592 /* The mask used to clear the ALT_SYSMGR_ECC_CAN0_DERR register field value. */
8593 #define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef
8594 /* The reset value of the ALT_SYSMGR_ECC_CAN0_DERR register field. */
8595 #define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0
8596 /* Extracts the ALT_SYSMGR_ECC_CAN0_DERR field value from a register. */
8597 #define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4)
8598 /* Produces a ALT_SYSMGR_ECC_CAN0_DERR register field value suitable for setting the register. */
8599 #define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010)
8600 
8601 #ifndef __ASSEMBLY__
8602 /*
8603  * WARNING: The C register and register group struct declarations are provided for
8604  * convenience and illustrative purposes. They should, however, be used with
8605  * caution as the C language standard provides no guarantees about the alignment or
8606  * atomicity of device memory accesses. The recommended practice for writing
8607  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8608  * alt_write_word() functions.
8609  *
8610  * The struct declaration for register ALT_SYSMGR_ECC_CAN0.
8611  */
8612 struct ALT_SYSMGR_ECC_CAN0_s
8613 {
8614  uint32_t en : 1; /* CAN0 RAM ECC Enable */
8615  uint32_t injs : 1; /* CAN0 RAM ECC inject single, correctable Error */
8616  uint32_t injd : 1; /* CAN0 RAM ECC inject double bit, non-correctable error */
8617  uint32_t serr : 1; /* CAN0 RAM ECC single, correctable error interrupt status */
8618  uint32_t derr : 1; /* CAN0 RAM ECC double bit, non-correctable error interrupt status */
8619  uint32_t : 27; /* *UNDEFINED* */
8620 };
8621 
8622 /* The typedef declaration for register ALT_SYSMGR_ECC_CAN0. */
8623 typedef volatile struct ALT_SYSMGR_ECC_CAN0_s ALT_SYSMGR_ECC_CAN0_t;
8624 #endif /* __ASSEMBLY__ */
8625 
8626 /* The byte offset of the ALT_SYSMGR_ECC_CAN0 register from the beginning of the component. */
8627 #define ALT_SYSMGR_ECC_CAN0_OFST 0x1c
8628 
8629 /*
8630  * Register : CAN1 RAM ECC Enable Register - can1
8631  *
8632  * This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected
8633  * into the write path using bits in this register. This register contains
8634  * interrupt status of the ECC single/double bit error.
8635  *
8636  * Only reset by a cold reset (ignores warm reset).
8637  *
8638  * Register Layout
8639  *
8640  * Bits | Access | Reset | Description
8641  * :-------|:-------|:------|:----------------------------------------------------------------
8642  * [0] | RW | 0x0 | CAN1 RAM ECC Enable
8643  * [1] | RW | 0x0 | CAN1 RAM ECC inject single, correctable Error
8644  * [2] | RW | 0x0 | CAN1 RAM ECC inject double bit, non-correctable error
8645  * [3] | RW | 0x0 | CAN1 RAM ECC single, correctable error interrupt status
8646  * [4] | RW | 0x0 | CAN1 RAM ECC double bit, non-correctable error interrupt status
8647  * [31:5] | ??? | 0x0 | *UNDEFINED*
8648  *
8649  */
8650 /*
8651  * Field : CAN1 RAM ECC Enable - en
8652  *
8653  * Enable ECC for CAN1 RAM
8654  *
8655  * Field Access Macros:
8656  *
8657  */
8658 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8659 #define ALT_SYSMGR_ECC_CAN1_EN_LSB 0
8660 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8661 #define ALT_SYSMGR_ECC_CAN1_EN_MSB 0
8662 /* The width in bits of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8663 #define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1
8664 /* The mask used to set the ALT_SYSMGR_ECC_CAN1_EN register field value. */
8665 #define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001
8666 /* The mask used to clear the ALT_SYSMGR_ECC_CAN1_EN register field value. */
8667 #define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe
8668 /* The reset value of the ALT_SYSMGR_ECC_CAN1_EN register field. */
8669 #define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0
8670 /* Extracts the ALT_SYSMGR_ECC_CAN1_EN field value from a register. */
8671 #define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0)
8672 /* Produces a ALT_SYSMGR_ECC_CAN1_EN register field value suitable for setting the register. */
8673 #define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001)
8674 
8675 /*
8676  * Field : CAN1 RAM ECC inject single, correctable Error - injs
8677  *
8678  * Changing this bit from zero to one injects a single, correctable error into the
8679  * CAN1 RAM. This only injects one error into the CAN1 RAM.
8680  *
8681  * Field Access Macros:
8682  *
8683  */
8684 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8685 #define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1
8686 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8687 #define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1
8688 /* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8689 #define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1
8690 /* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJS register field value. */
8691 #define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002
8692 /* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJS register field value. */
8693 #define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd
8694 /* The reset value of the ALT_SYSMGR_ECC_CAN1_INJS register field. */
8695 #define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0
8696 /* Extracts the ALT_SYSMGR_ECC_CAN1_INJS field value from a register. */
8697 #define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1)
8698 /* Produces a ALT_SYSMGR_ECC_CAN1_INJS register field value suitable for setting the register. */
8699 #define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002)
8700 
8701 /*
8702  * Field : CAN1 RAM ECC inject double bit, non-correctable error - injd
8703  *
8704  * Changing this bit from zero to one injects a double, non-correctable error into
8705  * the CAN1 RAM. This only injects one double bit error into the CAN1 RAM.
8706  *
8707  * Field Access Macros:
8708  *
8709  */
8710 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8711 #define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2
8712 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8713 #define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2
8714 /* The width in bits of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8715 #define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1
8716 /* The mask used to set the ALT_SYSMGR_ECC_CAN1_INJD register field value. */
8717 #define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004
8718 /* The mask used to clear the ALT_SYSMGR_ECC_CAN1_INJD register field value. */
8719 #define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb
8720 /* The reset value of the ALT_SYSMGR_ECC_CAN1_INJD register field. */
8721 #define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0
8722 /* Extracts the ALT_SYSMGR_ECC_CAN1_INJD field value from a register. */
8723 #define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2)
8724 /* Produces a ALT_SYSMGR_ECC_CAN1_INJD register field value suitable for setting the register. */
8725 #define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004)
8726 
8727 /*
8728  * Field : CAN1 RAM ECC single, correctable error interrupt status - serr
8729  *
8730  * This bit is an interrupt status bit for CAN1 RAM ECC single, correctable error.
8731  * It is set by hardware when single, correctable error occurs in CAN1 RAM.
8732  * Software needs to write 1 into this bit to clear the interrupt status.
8733  *
8734  * Field Access Macros:
8735  *
8736  */
8737 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8738 #define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3
8739 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8740 #define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3
8741 /* The width in bits of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8742 #define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1
8743 /* The mask used to set the ALT_SYSMGR_ECC_CAN1_SERR register field value. */
8744 #define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008
8745 /* The mask used to clear the ALT_SYSMGR_ECC_CAN1_SERR register field value. */
8746 #define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7
8747 /* The reset value of the ALT_SYSMGR_ECC_CAN1_SERR register field. */
8748 #define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0
8749 /* Extracts the ALT_SYSMGR_ECC_CAN1_SERR field value from a register. */
8750 #define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3)
8751 /* Produces a ALT_SYSMGR_ECC_CAN1_SERR register field value suitable for setting the register. */
8752 #define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008)
8753 
8754 /*
8755  * Field : CAN1 RAM ECC double bit, non-correctable error interrupt status - derr
8756  *
8757  * This bit is an interrupt status bit for CAN1 RAM ECC double bit, non-correctable
8758  * error. It is set by hardware when double bit, non-correctable error occurs in
8759  * CAN1 RAM. Software needs to write 1 into this bit to clear the interrupt status.
8760  *
8761  * Field Access Macros:
8762  *
8763  */
8764 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8765 #define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4
8766 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8767 #define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4
8768 /* The width in bits of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8769 #define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1
8770 /* The mask used to set the ALT_SYSMGR_ECC_CAN1_DERR register field value. */
8771 #define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010
8772 /* The mask used to clear the ALT_SYSMGR_ECC_CAN1_DERR register field value. */
8773 #define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef
8774 /* The reset value of the ALT_SYSMGR_ECC_CAN1_DERR register field. */
8775 #define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0
8776 /* Extracts the ALT_SYSMGR_ECC_CAN1_DERR field value from a register. */
8777 #define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4)
8778 /* Produces a ALT_SYSMGR_ECC_CAN1_DERR register field value suitable for setting the register. */
8779 #define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010)
8780 
8781 #ifndef __ASSEMBLY__
8782 /*
8783  * WARNING: The C register and register group struct declarations are provided for
8784  * convenience and illustrative purposes. They should, however, be used with
8785  * caution as the C language standard provides no guarantees about the alignment or
8786  * atomicity of device memory accesses. The recommended practice for writing
8787  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
8788  * alt_write_word() functions.
8789  *
8790  * The struct declaration for register ALT_SYSMGR_ECC_CAN1.
8791  */
8792 struct ALT_SYSMGR_ECC_CAN1_s
8793 {
8794  uint32_t en : 1; /* CAN1 RAM ECC Enable */
8795  uint32_t injs : 1; /* CAN1 RAM ECC inject single, correctable Error */
8796  uint32_t injd : 1; /* CAN1 RAM ECC inject double bit, non-correctable error */
8797  uint32_t serr : 1; /* CAN1 RAM ECC single, correctable error interrupt status */
8798  uint32_t derr : 1; /* CAN1 RAM ECC double bit, non-correctable error interrupt status */
8799  uint32_t : 27; /* *UNDEFINED* */
8800 };
8801 
8802 /* The typedef declaration for register ALT_SYSMGR_ECC_CAN1. */
8803 typedef volatile struct ALT_SYSMGR_ECC_CAN1_s ALT_SYSMGR_ECC_CAN1_t;
8804 #endif /* __ASSEMBLY__ */
8805 
8806 /* The byte offset of the ALT_SYSMGR_ECC_CAN1 register from the beginning of the component. */
8807 #define ALT_SYSMGR_ECC_CAN1_OFST 0x20
8808 
8809 /*
8810  * Register : NAND RAM ECC Enable Register - nand
8811  *
8812  * This register is used to enable ECC on the NAND RAM. ECC errors can be injected
8813  * into the write path using bits in this register. This register contains
8814  * interrupt status of the ECC single/double bit error.
8815  *
8816  * Only reset by a cold reset (ignores warm reset).
8817  *
8818  * Register Layout
8819  *
8820  * Bits | Access | Reset | Description
8821  * :--------|:-------|:------|:--------------------------------------------------------------------------
8822  * [0] | RW | 0x0 | NAND RAM ECC Enable
8823  * [1] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject single, correctable Error
8824  * [2] | RW | 0x0 | NAND ECCBUFFER RAM ECC inject double bit, non-correctable error
8825  * [3] | RW | 0x0 | NAND WRFIFO RAM ECC inject single, correctable Error
8826  * [4] | RW | 0x0 | NAND WRFIFO RAM ECC inject double bit, non-correctable error
8827  * [5] | RW | 0x0 | NAND RDFIFO RAM ECC inject single, correctable Error
8828  * [6] | RW | 0x0 | NAND RDFIFO RAM ECC inject double bit, non-correctable error
8829  * [7] | RW | 0x0 | NAND ECCBUFFER RAM ECC single, correctable error interrupt status
8830  * [8] | RW | 0x0 | NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status
8831  * [9] | RW | 0x0 | NAND WRFIFO RAM ECC single, correctable error interrupt status
8832  * [10] | RW | 0x0 | NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status
8833  * [11] | RW | 0x0 | NAND RDFIFO RAM ECC single, correctable error interrupt status
8834  * [12] | RW | 0x0 | NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status
8835  * [31:13] | ??? | 0x0 | *UNDEFINED*
8836  *
8837  */
8838 /*
8839  * Field : NAND RAM ECC Enable - en
8840  *
8841  * Enable ECC for NAND RAM
8842  *
8843  * Field Access Macros:
8844  *
8845  */
8846 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */
8847 #define ALT_SYSMGR_ECC_NAND_EN_LSB 0
8848 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field. */
8849 #define ALT_SYSMGR_ECC_NAND_EN_MSB 0
8850 /* The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field. */
8851 #define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1
8852 /* The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value. */
8853 #define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001
8854 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value. */
8855 #define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe
8856 /* The reset value of the ALT_SYSMGR_ECC_NAND_EN register field. */
8857 #define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0
8858 /* Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register. */
8859 #define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0)
8860 /* Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register. */
8861 #define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001)
8862 
8863 /*
8864  * Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs
8865  *
8866  * Changing this bit from zero to one injects a single, correctable error into the
8867  * NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM.
8868  *
8869  * Field Access Macros:
8870  *
8871  */
8872 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8873 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1
8874 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8875 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1
8876 /* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8877 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1
8878 /* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */
8879 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002
8880 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value. */
8881 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd
8882 /* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field. */
8883 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0
8884 /* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register. */
8885 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1)
8886 /* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register. */
8887 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002)
8888 
8889 /*
8890  * Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd
8891  *
8892  * Changing this bit from zero to one injects a double, non-correctable error into
8893  * the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND
8894  * ECCBUFFER RAM.
8895  *
8896  * Field Access Macros:
8897  *
8898  */
8899 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8900 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2
8901 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8902 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2
8903 /* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8904 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1
8905 /* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */
8906 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004
8907 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value. */
8908 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb
8909 /* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field. */
8910 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0
8911 /* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register. */
8912 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2)
8913 /* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register. */
8914 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004)
8915 
8916 /*
8917  * Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs
8918  *
8919  * Changing this bit from zero to one injects a single, correctable error into the
8920  * NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM.
8921  *
8922  * Field Access Macros:
8923  *
8924  */
8925 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8926 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3
8927 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8928 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3
8929 /* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8930 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1
8931 /* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */
8932 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008
8933 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value. */
8934 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7
8935 /* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field. */
8936 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0
8937 /* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register. */
8938 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8939 /* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register. */
8940 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8941 
8942 /*
8943  * Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd
8944  *
8945  * Changing this bit from zero to one injects a double, non-correctable error into
8946  * the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO
8947  * RAM.
8948  *
8949  * Field Access Macros:
8950  *
8951  */
8952 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8953 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4
8954 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8955 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4
8956 /* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8957 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1
8958 /* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */
8959 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010
8960 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value. */
8961 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef
8962 /* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field. */
8963 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0
8964 /* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register. */
8965 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8966 /* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register. */
8967 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8968 
8969 /*
8970  * Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs
8971  *
8972  * Changing this bit from zero to one injects a single, correctable error into the
8973  * NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM.
8974  *
8975  * Field Access Macros:
8976  *
8977  */
8978 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8979 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5
8980 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8981 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5
8982 /* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8983 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1
8984 /* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */
8985 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020
8986 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value. */
8987 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf
8988 /* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field. */
8989 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0
8990 /* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register. */
8991 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5)
8992 /* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register. */
8993 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020)
8994 
8995 /*
8996  * Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd
8997  *
8998  * Changing this bit from zero to one injects a double, non-correctable error into
8999  * the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO
9000  * RAM.
9001  *
9002  * Field Access Macros:
9003  *
9004  */
9005 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9006 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6
9007 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9008 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6
9009 /* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9010 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1
9011 /* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */
9012 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040
9013 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value. */
9014 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf
9015 /* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field. */
9016 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0
9017 /* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register. */
9018 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6)
9019 /* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register. */
9020 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040)
9021 
9022 /*
9023  * Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr
9024  *
9025  * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single,
9026  * correctable error. It is set by hardware when single, correctable error occurs
9027  * in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the
9028  * interrupt status.
9029  *
9030  * Field Access Macros:
9031  *
9032  */
9033 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9034 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7
9035 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9036 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7
9037 /* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9038 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1
9039 /* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */
9040 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080
9041 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value. */
9042 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f
9043 /* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field. */
9044 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0
9045 /* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register. */
9046 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7)
9047 /* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register. */
9048 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080)
9049 
9050 /*
9051  * Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr
9052  *
9053  * This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non-
9054  * correctable error. It is set by hardware when double bit, non-correctable error
9055  * occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear
9056  * the interrupt status.
9057  *
9058  * Field Access Macros:
9059  *
9060  */
9061 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9062 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8
9063 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9064 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8
9065 /* The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9066 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1
9067 /* The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */
9068 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100
9069 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value. */
9070 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff
9071 /* The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field. */
9072 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0
9073 /* Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register. */
9074 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8)
9075 /* Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register. */
9076 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100)
9077 
9078 /*
9079  * Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr
9080  *
9081  * This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable
9082  * error. It is set by hardware when single, correctable error occurs in NAND
9083  * WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
9084  * status.
9085  *
9086  * Field Access Macros:
9087  *
9088  */
9089 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9090 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9
9091 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9092 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9
9093 /* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9094 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1
9095 /* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */
9096 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200
9097 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value. */
9098 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff
9099 /* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field. */
9100 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0
9101 /* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register. */
9102 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9)
9103 /* Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register. */
9104 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200)
9105 
9106 /*
9107  * Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr
9108  *
9109  * This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non-
9110  * correctable error. It is set by hardware when double bit, non-correctable error
9111  * occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the
9112  * interrupt status.
9113  *
9114  * Field Access Macros:
9115  *
9116  */
9117 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9118 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10
9119 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9120 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10
9121 /* The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9122 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1
9123 /* The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */
9124 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400
9125 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value. */
9126 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff
9127 /* The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field. */
9128 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0
9129 /* Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register. */
9130 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10)
9131 /* Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register. */
9132 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400)
9133 
9134 /*
9135  * Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr
9136  *
9137  * This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable
9138  * error. It is set by hardware when single, correctable error occurs in NAND
9139  * RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt
9140  * status.
9141  *
9142  * Field Access Macros:
9143  *
9144  */
9145 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9146 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11
9147 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9148 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11
9149 /* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9150 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1
9151 /* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */
9152 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800
9153 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value. */
9154 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff
9155 /* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field. */
9156 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0
9157 /* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register. */
9158 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11)
9159 /* Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register. */
9160 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800)
9161 
9162 /*
9163  * Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr
9164  *
9165  * This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non-
9166  * correctable error. It is set by hardware when double bit, non-correctable error
9167  * occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the
9168  * interrupt status.
9169  *
9170  * Field Access Macros:
9171  *
9172  */
9173 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9174 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12
9175 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9176 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12
9177 /* The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9178 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1
9179 /* The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */
9180 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000
9181 /* The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value. */
9182 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff
9183 /* The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field. */
9184 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0
9185 /* Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register. */
9186 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12)
9187 /* Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register. */
9188 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000)
9189 
9190 #ifndef __ASSEMBLY__
9191 /*
9192  * WARNING: The C register and register group struct declarations are provided for
9193  * convenience and illustrative purposes. They should, however, be used with
9194  * caution as the C language standard provides no guarantees about the alignment or
9195  * atomicity of device memory accesses. The recommended practice for writing
9196  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9197  * alt_write_word() functions.
9198  *
9199  * The struct declaration for register ALT_SYSMGR_ECC_NAND.
9200  */
9201 struct ALT_SYSMGR_ECC_NAND_s
9202 {
9203  uint32_t en : 1; /* NAND RAM ECC Enable */
9204  uint32_t eccbufinjs : 1; /* NAND ECCBUFFER RAM ECC inject single, correctable Error */
9205  uint32_t eccbufinjd : 1; /* NAND ECCBUFFER RAM ECC inject double bit, non-correctable error */
9206  uint32_t wrfifoinjs : 1; /* NAND WRFIFO RAM ECC inject single, correctable Error */
9207  uint32_t wrfifoinjd : 1; /* NAND WRFIFO RAM ECC inject double bit, non-correctable error */
9208  uint32_t rdfifoinjs : 1; /* NAND RDFIFO RAM ECC inject single, correctable Error */
9209  uint32_t rdfifoinjd : 1; /* NAND RDFIFO RAM ECC inject double bit, non-correctable error */
9210  uint32_t eccbufserr : 1; /* NAND ECCBUFFER RAM ECC single, correctable error interrupt status */
9211  uint32_t eccbufderr : 1; /* NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status */
9212  uint32_t wrfifoserr : 1; /* NAND WRFIFO RAM ECC single, correctable error interrupt status */
9213  uint32_t wrfifoderr : 1; /* NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status */
9214  uint32_t rdfifoserr : 1; /* NAND RDFIFO RAM ECC single, correctable error interrupt status */
9215  uint32_t rdfifoderr : 1; /* NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status */
9216  uint32_t : 19; /* *UNDEFINED* */
9217 };
9218 
9219 /* The typedef declaration for register ALT_SYSMGR_ECC_NAND. */
9220 typedef volatile struct ALT_SYSMGR_ECC_NAND_s ALT_SYSMGR_ECC_NAND_t;
9221 #endif /* __ASSEMBLY__ */
9222 
9223 /* The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component. */
9224 #define ALT_SYSMGR_ECC_NAND_OFST 0x24
9225 
9226 /*
9227  * Register : QSPI RAM ECC Enable Register - qspi
9228  *
9229  * This register is used to enable ECC on the QSPI RAM. ECC errors can be injected
9230  * into the write path using bits in this register. This register contains
9231  * interrupt status of the ECC single/double bit error.
9232  *
9233  * Only reset by a cold reset (ignores warm reset).
9234  *
9235  * Register Layout
9236  *
9237  * Bits | Access | Reset | Description
9238  * :-------|:-------|:------|:----------------------------------------------------------------
9239  * [0] | RW | 0x0 | QSPI RAM ECC Enable
9240  * [1] | RW | 0x0 | QSPI RAM ECC inject single, correctable Error
9241  * [2] | RW | 0x0 | QSPI RAM ECC inject double bit, non-correctable error
9242  * [3] | RW | 0x0 | QSPI RAM ECC single, correctable error interrupt status
9243  * [4] | RW | 0x0 | QSPI RAM ECC double bit, non-correctable error interrupt status
9244  * [31:5] | ??? | 0x0 | *UNDEFINED*
9245  *
9246  */
9247 /*
9248  * Field : QSPI RAM ECC Enable - en
9249  *
9250  * Enable ECC for QSPI RAM
9251  *
9252  * Field Access Macros:
9253  *
9254  */
9255 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9256 #define ALT_SYSMGR_ECC_QSPI_EN_LSB 0
9257 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9258 #define ALT_SYSMGR_ECC_QSPI_EN_MSB 0
9259 /* The width in bits of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9260 #define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1
9261 /* The mask used to set the ALT_SYSMGR_ECC_QSPI_EN register field value. */
9262 #define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001
9263 /* The mask used to clear the ALT_SYSMGR_ECC_QSPI_EN register field value. */
9264 #define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe
9265 /* The reset value of the ALT_SYSMGR_ECC_QSPI_EN register field. */
9266 #define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0
9267 /* Extracts the ALT_SYSMGR_ECC_QSPI_EN field value from a register. */
9268 #define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0)
9269 /* Produces a ALT_SYSMGR_ECC_QSPI_EN register field value suitable for setting the register. */
9270 #define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001)
9271 
9272 /*
9273  * Field : QSPI RAM ECC inject single, correctable Error - injs
9274  *
9275  * Changing this bit from zero to one injects a single, correctable error into the
9276  * QSPI RAM. This only injects one error into the QSPI RAM.
9277  *
9278  * Field Access Macros:
9279  *
9280  */
9281 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9282 #define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1
9283 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9284 #define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1
9285 /* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9286 #define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1
9287 /* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJS register field value. */
9288 #define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002
9289 /* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJS register field value. */
9290 #define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd
9291 /* The reset value of the ALT_SYSMGR_ECC_QSPI_INJS register field. */
9292 #define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0
9293 /* Extracts the ALT_SYSMGR_ECC_QSPI_INJS field value from a register. */
9294 #define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1)
9295 /* Produces a ALT_SYSMGR_ECC_QSPI_INJS register field value suitable for setting the register. */
9296 #define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002)
9297 
9298 /*
9299  * Field : QSPI RAM ECC inject double bit, non-correctable error - injd
9300  *
9301  * Changing this bit from zero to one injects a double, non-correctable error into
9302  * the QSPI RAM. This only injects one double bit error into the QSPI RAM.
9303  *
9304  * Field Access Macros:
9305  *
9306  */
9307 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9308 #define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2
9309 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9310 #define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2
9311 /* The width in bits of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9312 #define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1
9313 /* The mask used to set the ALT_SYSMGR_ECC_QSPI_INJD register field value. */
9314 #define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004
9315 /* The mask used to clear the ALT_SYSMGR_ECC_QSPI_INJD register field value. */
9316 #define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb
9317 /* The reset value of the ALT_SYSMGR_ECC_QSPI_INJD register field. */
9318 #define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0
9319 /* Extracts the ALT_SYSMGR_ECC_QSPI_INJD field value from a register. */
9320 #define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2)
9321 /* Produces a ALT_SYSMGR_ECC_QSPI_INJD register field value suitable for setting the register. */
9322 #define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004)
9323 
9324 /*
9325  * Field : QSPI RAM ECC single, correctable error interrupt status - serr
9326  *
9327  * This bit is an interrupt status bit for QSPI RAM ECC single, correctable error.
9328  * It is set by hardware when single, correctable error occurs in QSPI RAM.
9329  * Software needs to write 1 into this bit to clear the interrupt status.
9330  *
9331  * Field Access Macros:
9332  *
9333  */
9334 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9335 #define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3
9336 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9337 #define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3
9338 /* The width in bits of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9339 #define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1
9340 /* The mask used to set the ALT_SYSMGR_ECC_QSPI_SERR register field value. */
9341 #define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008
9342 /* The mask used to clear the ALT_SYSMGR_ECC_QSPI_SERR register field value. */
9343 #define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7
9344 /* The reset value of the ALT_SYSMGR_ECC_QSPI_SERR register field. */
9345 #define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0
9346 /* Extracts the ALT_SYSMGR_ECC_QSPI_SERR field value from a register. */
9347 #define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3)
9348 /* Produces a ALT_SYSMGR_ECC_QSPI_SERR register field value suitable for setting the register. */
9349 #define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008)
9350 
9351 /*
9352  * Field : QSPI RAM ECC double bit, non-correctable error interrupt status - derr
9353  *
9354  * This bit is an interrupt status bit for QSPI RAM ECC double bit, non-correctable
9355  * error. It is set by hardware when double bit, non-correctable error occurs in
9356  * QSPI RAM. Software needs to write 1 into this bit to clear the interrupt status.
9357  *
9358  * Field Access Macros:
9359  *
9360  */
9361 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9362 #define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4
9363 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9364 #define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4
9365 /* The width in bits of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9366 #define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1
9367 /* The mask used to set the ALT_SYSMGR_ECC_QSPI_DERR register field value. */
9368 #define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010
9369 /* The mask used to clear the ALT_SYSMGR_ECC_QSPI_DERR register field value. */
9370 #define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef
9371 /* The reset value of the ALT_SYSMGR_ECC_QSPI_DERR register field. */
9372 #define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0
9373 /* Extracts the ALT_SYSMGR_ECC_QSPI_DERR field value from a register. */
9374 #define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4)
9375 /* Produces a ALT_SYSMGR_ECC_QSPI_DERR register field value suitable for setting the register. */
9376 #define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010)
9377 
9378 #ifndef __ASSEMBLY__
9379 /*
9380  * WARNING: The C register and register group struct declarations are provided for
9381  * convenience and illustrative purposes. They should, however, be used with
9382  * caution as the C language standard provides no guarantees about the alignment or
9383  * atomicity of device memory accesses. The recommended practice for writing
9384  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9385  * alt_write_word() functions.
9386  *
9387  * The struct declaration for register ALT_SYSMGR_ECC_QSPI.
9388  */
9389 struct ALT_SYSMGR_ECC_QSPI_s
9390 {
9391  uint32_t en : 1; /* QSPI RAM ECC Enable */
9392  uint32_t injs : 1; /* QSPI RAM ECC inject single, correctable Error */
9393  uint32_t injd : 1; /* QSPI RAM ECC inject double bit, non-correctable error */
9394  uint32_t serr : 1; /* QSPI RAM ECC single, correctable error interrupt status */
9395  uint32_t derr : 1; /* QSPI RAM ECC double bit, non-correctable error interrupt status */
9396  uint32_t : 27; /* *UNDEFINED* */
9397 };
9398 
9399 /* The typedef declaration for register ALT_SYSMGR_ECC_QSPI. */
9400 typedef volatile struct ALT_SYSMGR_ECC_QSPI_s ALT_SYSMGR_ECC_QSPI_t;
9401 #endif /* __ASSEMBLY__ */
9402 
9403 /* The byte offset of the ALT_SYSMGR_ECC_QSPI register from the beginning of the component. */
9404 #define ALT_SYSMGR_ECC_QSPI_OFST 0x28
9405 
9406 /*
9407  * Register : SDMMC RAM ECC Enable Register - sdmmc
9408  *
9409  * This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected
9410  * into the write path using bits in this register.
9411  *
9412  * Only reset by a cold reset (ignores warm reset).
9413  *
9414  * Register Layout
9415  *
9416  * Bits | Access | Reset | Description
9417  * :-------|:-------|:------|:------------------------------------------------------------------------
9418  * [0] | RW | 0x0 | SDMMC RAM ECC Enable
9419  * [1] | RW | 0x0 | SDMMC Port A RAM ECC inject single, correctable Error at Port A
9420  * [2] | RW | 0x0 | SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A
9421  * [3] | RW | 0x0 | SDMMC Port B RAM ECC inject single, correctable Error at Port B
9422  * [4] | RW | 0x0 | SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B
9423  * [5] | RW | 0x0 | SDMMC Port A RAM ECC single, correctable error interrupt status
9424  * [6] | RW | 0x0 | SDMMC Port A RAM ECC double bit, non-correctable error interrupt status
9425  * [7] | RW | 0x0 | SDMMC Port B RAM ECC single, correctable error interrupt status
9426  * [8] | RW | 0x0 | SDMMC Port B RAM ECC double bit, non-correctable error interrupt status
9427  * [31:9] | ??? | 0x0 | *UNDEFINED*
9428  *
9429  */
9430 /*
9431  * Field : SDMMC RAM ECC Enable - en
9432  *
9433  * Enable ECC for SDMMC RAM
9434  *
9435  * Field Access Macros:
9436  *
9437  */
9438 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9439 #define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0
9440 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9441 #define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0
9442 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9443 #define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1
9444 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_EN register field value. */
9445 #define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001
9446 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_EN register field value. */
9447 #define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe
9448 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_EN register field. */
9449 #define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0
9450 /* Extracts the ALT_SYSMGR_ECC_SDMMC_EN field value from a register. */
9451 #define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0)
9452 /* Produces a ALT_SYSMGR_ECC_SDMMC_EN register field value suitable for setting the register. */
9453 #define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001)
9454 
9455 /*
9456  * Field : SDMMC Port A RAM ECC inject single, correctable Error at Port A - injsporta
9457  *
9458  * Changing this bit from zero to one injects a single, correctable error into the
9459  * SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A.
9460  *
9461  * Field Access Macros:
9462  *
9463  */
9464 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9465 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1
9466 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9467 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1
9468 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9469 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1
9470 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */
9471 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002
9472 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value. */
9473 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd
9474 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field. */
9475 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0
9476 /* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTA field value from a register. */
9477 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1)
9478 /* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTA register field value suitable for setting the register. */
9479 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002)
9480 
9481 /*
9482  * Field : SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A - injdporta
9483  *
9484  * Changing this bit from zero to one injects a double, non-correctable error into
9485  * the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC
9486  * RAM at Port A.
9487  *
9488  * Field Access Macros:
9489  *
9490  */
9491 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9492 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2
9493 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9494 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2
9495 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9496 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1
9497 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */
9498 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004
9499 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value. */
9500 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb
9501 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field. */
9502 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0
9503 /* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTA field value from a register. */
9504 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2)
9505 /* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTA register field value suitable for setting the register. */
9506 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004)
9507 
9508 /*
9509  * Field : SDMMC Port B RAM ECC inject single, correctable Error at Port B - injsportb
9510  *
9511  * Changing this bit from zero to one injects a single, correctable error into the
9512  * SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B.
9513  *
9514  * Field Access Macros:
9515  *
9516  */
9517 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9518 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3
9519 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9520 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3
9521 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9522 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1
9523 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */
9524 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008
9525 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value. */
9526 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7
9527 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field. */
9528 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0
9529 /* Extracts the ALT_SYSMGR_ECC_SDMMC_INJSPORTB field value from a register. */
9530 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3)
9531 /* Produces a ALT_SYSMGR_ECC_SDMMC_INJSPORTB register field value suitable for setting the register. */
9532 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008)
9533 
9534 /*
9535  * Field : SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B - injdportb
9536  *
9537  * Changing this bit from zero to one injects a double, non-correctable error into
9538  * the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC
9539  * RAM at Port B.
9540  *
9541  * Field Access Macros:
9542  *
9543  */
9544 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9545 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4
9546 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9547 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4
9548 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9549 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1
9550 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */
9551 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010
9552 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value. */
9553 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef
9554 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field. */
9555 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0
9556 /* Extracts the ALT_SYSMGR_ECC_SDMMC_INJDPORTB field value from a register. */
9557 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4)
9558 /* Produces a ALT_SYSMGR_ECC_SDMMC_INJDPORTB register field value suitable for setting the register. */
9559 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010)
9560 
9561 /*
9562  * Field : SDMMC Port A RAM ECC single, correctable error interrupt status - serrporta
9563  *
9564  * This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable
9565  * error. It is set by hardware when single, correctable error occurs in SDMMC Port
9566  * A RAM. Software needs to write 1 into this bit to clear the interrupt status.
9567  *
9568  * Field Access Macros:
9569  *
9570  */
9571 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9572 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5
9573 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9574 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5
9575 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9576 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1
9577 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */
9578 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020
9579 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value. */
9580 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf
9581 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field. */
9582 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0
9583 /* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTA field value from a register. */
9584 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5)
9585 /* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTA register field value suitable for setting the register. */
9586 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020)
9587 
9588 /*
9589  * Field : SDMMC Port A RAM ECC double bit, non-correctable error interrupt status - derrporta
9590  *
9591  * This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non-
9592  * correctable error. It is set by hardware when double bit, non-correctable error
9593  * occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the
9594  * interrupt status.
9595  *
9596  * Field Access Macros:
9597  *
9598  */
9599 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9600 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6
9601 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9602 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6
9603 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9604 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1
9605 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */
9606 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040
9607 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value. */
9608 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf
9609 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field. */
9610 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0
9611 /* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTA field value from a register. */
9612 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6)
9613 /* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTA register field value suitable for setting the register. */
9614 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040)
9615 
9616 /*
9617  * Field : SDMMC Port B RAM ECC single, correctable error interrupt status - serrportb
9618  *
9619  * This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable
9620  * error. It is set by hardware when single, correctable error occurs in SDMMC Port
9621  * B RAM. Software needs to write 1 into this bit to clear the interrupt status.
9622  *
9623  * Field Access Macros:
9624  *
9625  */
9626 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9627 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7
9628 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9629 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7
9630 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9631 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1
9632 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */
9633 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080
9634 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value. */
9635 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f
9636 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field. */
9637 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0
9638 /* Extracts the ALT_SYSMGR_ECC_SDMMC_SERRPORTB field value from a register. */
9639 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7)
9640 /* Produces a ALT_SYSMGR_ECC_SDMMC_SERRPORTB register field value suitable for setting the register. */
9641 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080)
9642 
9643 /*
9644  * Field : SDMMC Port B RAM ECC double bit, non-correctable error interrupt status - derrportb
9645  *
9646  * This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non-
9647  * correctable error. It is set by hardware when double bit, non-correctable error
9648  * occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the
9649  * interrupt status.
9650  *
9651  * Field Access Macros:
9652  *
9653  */
9654 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9655 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8
9656 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9657 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8
9658 /* The width in bits of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9659 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1
9660 /* The mask used to set the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */
9661 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100
9662 /* The mask used to clear the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value. */
9663 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff
9664 /* The reset value of the ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field. */
9665 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0
9666 /* Extracts the ALT_SYSMGR_ECC_SDMMC_DERRPORTB field value from a register. */
9667 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8)
9668 /* Produces a ALT_SYSMGR_ECC_SDMMC_DERRPORTB register field value suitable for setting the register. */
9669 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100)
9670 
9671 #ifndef __ASSEMBLY__
9672 /*
9673  * WARNING: The C register and register group struct declarations are provided for
9674  * convenience and illustrative purposes. They should, however, be used with
9675  * caution as the C language standard provides no guarantees about the alignment or
9676  * atomicity of device memory accesses. The recommended practice for writing
9677  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9678  * alt_write_word() functions.
9679  *
9680  * The struct declaration for register ALT_SYSMGR_ECC_SDMMC.
9681  */
9682 struct ALT_SYSMGR_ECC_SDMMC_s
9683 {
9684  uint32_t en : 1; /* SDMMC RAM ECC Enable */
9685  uint32_t injsporta : 1; /* SDMMC Port A RAM ECC inject single, correctable Error at Port A */
9686  uint32_t injdporta : 1; /* SDMMC Port A RAM ECC inject double bit, non-correctable error at Port A */
9687  uint32_t injsportb : 1; /* SDMMC Port B RAM ECC inject single, correctable Error at Port B */
9688  uint32_t injdportb : 1; /* SDMMC Port B RAM ECC inject double bit, non-correctable error at Port B */
9689  uint32_t serrporta : 1; /* SDMMC Port A RAM ECC single, correctable error interrupt status */
9690  uint32_t derrporta : 1; /* SDMMC Port A RAM ECC double bit, non-correctable error interrupt status */
9691  uint32_t serrportb : 1; /* SDMMC Port B RAM ECC single, correctable error interrupt status */
9692  uint32_t derrportb : 1; /* SDMMC Port B RAM ECC double bit, non-correctable error interrupt status */
9693  uint32_t : 23; /* *UNDEFINED* */
9694 };
9695 
9696 /* The typedef declaration for register ALT_SYSMGR_ECC_SDMMC. */
9697 typedef volatile struct ALT_SYSMGR_ECC_SDMMC_s ALT_SYSMGR_ECC_SDMMC_t;
9698 #endif /* __ASSEMBLY__ */
9699 
9700 /* The byte offset of the ALT_SYSMGR_ECC_SDMMC register from the beginning of the component. */
9701 #define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c
9702 
9703 #ifndef __ASSEMBLY__
9704 /*
9705  * WARNING: The C register and register group struct declarations are provided for
9706  * convenience and illustrative purposes. They should, however, be used with
9707  * caution as the C language standard provides no guarantees about the alignment or
9708  * atomicity of device memory accesses. The recommended practice for writing
9709  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9710  * alt_write_word() functions.
9711  *
9712  * The struct declaration for register group ALT_SYSMGR_ECC.
9713  */
9714 struct ALT_SYSMGR_ECC_s
9715 {
9716  ALT_SYSMGR_ECC_L2_t l2; /* ALT_SYSMGR_ECC_L2 */
9717  ALT_SYSMGR_ECC_OCRAM_t ocram; /* ALT_SYSMGR_ECC_OCRAM */
9718  ALT_SYSMGR_ECC_USB0_t usb0; /* ALT_SYSMGR_ECC_USB0 */
9719  ALT_SYSMGR_ECC_USB1_t usb1; /* ALT_SYSMGR_ECC_USB1 */
9720  ALT_SYSMGR_ECC_EMAC0_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */
9721  ALT_SYSMGR_ECC_EMAC1_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */
9722  ALT_SYSMGR_ECC_DMA_t dma; /* ALT_SYSMGR_ECC_DMA */
9723  ALT_SYSMGR_ECC_CAN0_t can0; /* ALT_SYSMGR_ECC_CAN0 */
9724  ALT_SYSMGR_ECC_CAN1_t can1; /* ALT_SYSMGR_ECC_CAN1 */
9725  ALT_SYSMGR_ECC_NAND_t nand; /* ALT_SYSMGR_ECC_NAND */
9726  ALT_SYSMGR_ECC_QSPI_t qspi; /* ALT_SYSMGR_ECC_QSPI */
9727  ALT_SYSMGR_ECC_SDMMC_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */
9728  volatile uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */
9729 };
9730 
9731 /* The typedef declaration for register group ALT_SYSMGR_ECC. */
9732 typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t;
9733 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_ECC. */
9734 struct ALT_SYSMGR_ECC_raw_s
9735 {
9736  volatile uint32_t l2; /* ALT_SYSMGR_ECC_L2 */
9737  volatile uint32_t ocram; /* ALT_SYSMGR_ECC_OCRAM */
9738  volatile uint32_t usb0; /* ALT_SYSMGR_ECC_USB0 */
9739  volatile uint32_t usb1; /* ALT_SYSMGR_ECC_USB1 */
9740  volatile uint32_t emac0; /* ALT_SYSMGR_ECC_EMAC0 */
9741  volatile uint32_t emac1; /* ALT_SYSMGR_ECC_EMAC1 */
9742  volatile uint32_t dma; /* ALT_SYSMGR_ECC_DMA */
9743  volatile uint32_t can0; /* ALT_SYSMGR_ECC_CAN0 */
9744  volatile uint32_t can1; /* ALT_SYSMGR_ECC_CAN1 */
9745  volatile uint32_t nand; /* ALT_SYSMGR_ECC_NAND */
9746  volatile uint32_t qspi; /* ALT_SYSMGR_ECC_QSPI */
9747  volatile uint32_t sdmmc; /* ALT_SYSMGR_ECC_SDMMC */
9748  uint32_t _pad_0x30_0x40[4]; /* *UNDEFINED* */
9749 };
9750 
9751 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_ECC. */
9752 typedef volatile struct ALT_SYSMGR_ECC_raw_s ALT_SYSMGR_ECC_raw_t;
9753 #endif /* __ASSEMBLY__ */
9754 
9755 
9756 /*
9757  * Register Group : Pin Mux Control Group - ALT_SYSMGR_PINMUX
9758  * Pin Mux Control Group
9759  *
9760  * Controls Pin Mux selections
9761  *
9762  * NOTE: These registers should not be modified after IO configuration.There is no
9763  * support for dynamically changing the Pin Mux selections.
9764  *
9765  */
9766 /*
9767  * Register : emac0_tx_clk Mux Selection Register - EMACIO0
9768  *
9769  * This register is used to control the peripherals connected to emac0_tx_clk
9770  *
9771  * Only reset by a cold reset (ignores warm reset).
9772  *
9773  * NOTE: These registers should not be modified after IO configuration.There is no
9774  * support for dynamically changing the Pin Mux selections.
9775  *
9776  * Register Layout
9777  *
9778  * Bits | Access | Reset | Description
9779  * :-------|:-------|:------|:---------------------------------
9780  * [1:0] | RW | 0x0 | emac0_tx_clk Mux Selection Field
9781  * [31:2] | ??? | 0x0 | *UNDEFINED*
9782  *
9783  */
9784 /*
9785  * Field : emac0_tx_clk Mux Selection Field - sel
9786  *
9787  * Select peripheral signals connected emac0_tx_clk.
9788  *
9789  * 0 : Pin is connected to GPIO/LoanIO number 0.
9790  *
9791  * 1 : Pin is connected to Peripheral signal not applicable.
9792  *
9793  * 2 : Pin is connected to Peripheral signal not applicable.
9794  *
9795  * 3 : Pin is connected to Peripheral signal RGMII0.TX_CLK.
9796  *
9797  * Field Access Macros:
9798  *
9799  */
9800 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9801 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0
9802 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9803 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1
9804 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9805 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2
9806 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */
9807 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003
9808 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value. */
9809 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc
9810 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO0_SEL register field. */
9811 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0
9812 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO0_SEL field value from a register. */
9813 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
9814 /* Produces a ALT_SYSMGR_PINMUX_EMACIO0_SEL register field value suitable for setting the register. */
9815 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
9816 
9817 #ifndef __ASSEMBLY__
9818 /*
9819  * WARNING: The C register and register group struct declarations are provided for
9820  * convenience and illustrative purposes. They should, however, be used with
9821  * caution as the C language standard provides no guarantees about the alignment or
9822  * atomicity of device memory accesses. The recommended practice for writing
9823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9824  * alt_write_word() functions.
9825  *
9826  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO0.
9827  */
9828 struct ALT_SYSMGR_PINMUX_EMACIO0_s
9829 {
9830  uint32_t sel : 2; /* emac0_tx_clk Mux Selection Field */
9831  uint32_t : 30; /* *UNDEFINED* */
9832 };
9833 
9834 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO0. */
9835 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO0_s ALT_SYSMGR_PINMUX_EMACIO0_t;
9836 #endif /* __ASSEMBLY__ */
9837 
9838 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO0 register from the beginning of the component. */
9839 #define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0
9840 
9841 /*
9842  * Register : emac0_tx_d0 Mux Selection Register - EMACIO1
9843  *
9844  * This register is used to control the peripherals connected to emac0_tx_d0
9845  *
9846  * Only reset by a cold reset (ignores warm reset).
9847  *
9848  * NOTE: These registers should not be modified after IO configuration.There is no
9849  * support for dynamically changing the Pin Mux selections.
9850  *
9851  * Register Layout
9852  *
9853  * Bits | Access | Reset | Description
9854  * :-------|:-------|:------|:--------------------------------
9855  * [1:0] | RW | 0x0 | emac0_tx_d0 Mux Selection Field
9856  * [31:2] | ??? | 0x0 | *UNDEFINED*
9857  *
9858  */
9859 /*
9860  * Field : emac0_tx_d0 Mux Selection Field - sel
9861  *
9862  * Select peripheral signals connected emac0_tx_d0.
9863  *
9864  * 0 : Pin is connected to GPIO/LoanIO number 1.
9865  *
9866  * 1 : Pin is connected to Peripheral signal not applicable.
9867  *
9868  * 2 : Pin is connected to Peripheral signal USB1.D0.
9869  *
9870  * 3 : Pin is connected to Peripheral signal RGMII0.TXD0.
9871  *
9872  * Field Access Macros:
9873  *
9874  */
9875 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9876 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0
9877 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9878 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1
9879 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9880 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2
9881 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */
9882 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003
9883 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value. */
9884 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc
9885 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO1_SEL register field. */
9886 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0
9887 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO1_SEL field value from a register. */
9888 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
9889 /* Produces a ALT_SYSMGR_PINMUX_EMACIO1_SEL register field value suitable for setting the register. */
9890 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
9891 
9892 #ifndef __ASSEMBLY__
9893 /*
9894  * WARNING: The C register and register group struct declarations are provided for
9895  * convenience and illustrative purposes. They should, however, be used with
9896  * caution as the C language standard provides no guarantees about the alignment or
9897  * atomicity of device memory accesses. The recommended practice for writing
9898  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9899  * alt_write_word() functions.
9900  *
9901  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO1.
9902  */
9903 struct ALT_SYSMGR_PINMUX_EMACIO1_s
9904 {
9905  uint32_t sel : 2; /* emac0_tx_d0 Mux Selection Field */
9906  uint32_t : 30; /* *UNDEFINED* */
9907 };
9908 
9909 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO1. */
9910 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO1_s ALT_SYSMGR_PINMUX_EMACIO1_t;
9911 #endif /* __ASSEMBLY__ */
9912 
9913 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO1 register from the beginning of the component. */
9914 #define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4
9915 
9916 /*
9917  * Register : emac0_tx_d1 Mux Selection Register - EMACIO2
9918  *
9919  * This register is used to control the peripherals connected to emac0_tx_d1
9920  *
9921  * Only reset by a cold reset (ignores warm reset).
9922  *
9923  * NOTE: These registers should not be modified after IO configuration.There is no
9924  * support for dynamically changing the Pin Mux selections.
9925  *
9926  * Register Layout
9927  *
9928  * Bits | Access | Reset | Description
9929  * :-------|:-------|:------|:--------------------------------
9930  * [1:0] | RW | 0x0 | emac0_tx_d1 Mux Selection Field
9931  * [31:2] | ??? | 0x0 | *UNDEFINED*
9932  *
9933  */
9934 /*
9935  * Field : emac0_tx_d1 Mux Selection Field - sel
9936  *
9937  * Select peripheral signals connected emac0_tx_d1.
9938  *
9939  * 0 : Pin is connected to GPIO/LoanIO number 2.
9940  *
9941  * 1 : Pin is connected to Peripheral signal not applicable.
9942  *
9943  * 2 : Pin is connected to Peripheral signal USB1.D1.
9944  *
9945  * 3 : Pin is connected to Peripheral signal RGMII0.TXD1.
9946  *
9947  * Field Access Macros:
9948  *
9949  */
9950 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9951 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0
9952 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9953 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1
9954 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9955 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2
9956 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */
9957 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003
9958 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value. */
9959 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc
9960 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO2_SEL register field. */
9961 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0
9962 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO2_SEL field value from a register. */
9963 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
9964 /* Produces a ALT_SYSMGR_PINMUX_EMACIO2_SEL register field value suitable for setting the register. */
9965 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
9966 
9967 #ifndef __ASSEMBLY__
9968 /*
9969  * WARNING: The C register and register group struct declarations are provided for
9970  * convenience and illustrative purposes. They should, however, be used with
9971  * caution as the C language standard provides no guarantees about the alignment or
9972  * atomicity of device memory accesses. The recommended practice for writing
9973  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
9974  * alt_write_word() functions.
9975  *
9976  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO2.
9977  */
9978 struct ALT_SYSMGR_PINMUX_EMACIO2_s
9979 {
9980  uint32_t sel : 2; /* emac0_tx_d1 Mux Selection Field */
9981  uint32_t : 30; /* *UNDEFINED* */
9982 };
9983 
9984 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO2. */
9985 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO2_s ALT_SYSMGR_PINMUX_EMACIO2_t;
9986 #endif /* __ASSEMBLY__ */
9987 
9988 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO2 register from the beginning of the component. */
9989 #define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8
9990 
9991 /*
9992  * Register : emac0_tx_d2 Mux Selection Register - EMACIO3
9993  *
9994  * This register is used to control the peripherals connected to emac0_tx_d2
9995  *
9996  * Only reset by a cold reset (ignores warm reset).
9997  *
9998  * NOTE: These registers should not be modified after IO configuration.There is no
9999  * support for dynamically changing the Pin Mux selections.
10000  *
10001  * Register Layout
10002  *
10003  * Bits | Access | Reset | Description
10004  * :-------|:-------|:------|:--------------------------------
10005  * [1:0] | RW | 0x0 | emac0_tx_d2 Mux Selection Field
10006  * [31:2] | ??? | 0x0 | *UNDEFINED*
10007  *
10008  */
10009 /*
10010  * Field : emac0_tx_d2 Mux Selection Field - sel
10011  *
10012  * Select peripheral signals connected emac0_tx_d2.
10013  *
10014  * 0 : Pin is connected to GPIO/LoanIO number 3.
10015  *
10016  * 1 : Pin is connected to Peripheral signal not applicable.
10017  *
10018  * 2 : Pin is connected to Peripheral signal USB1.D2.
10019  *
10020  * 3 : Pin is connected to Peripheral signal RGMII0.TXD2.
10021  *
10022  * Field Access Macros:
10023  *
10024  */
10025 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10026 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0
10027 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10028 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1
10029 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10030 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2
10031 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */
10032 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003
10033 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value. */
10034 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc
10035 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO3_SEL register field. */
10036 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0
10037 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO3_SEL field value from a register. */
10038 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
10039 /* Produces a ALT_SYSMGR_PINMUX_EMACIO3_SEL register field value suitable for setting the register. */
10040 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
10041 
10042 #ifndef __ASSEMBLY__
10043 /*
10044  * WARNING: The C register and register group struct declarations are provided for
10045  * convenience and illustrative purposes. They should, however, be used with
10046  * caution as the C language standard provides no guarantees about the alignment or
10047  * atomicity of device memory accesses. The recommended practice for writing
10048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10049  * alt_write_word() functions.
10050  *
10051  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO3.
10052  */
10053 struct ALT_SYSMGR_PINMUX_EMACIO3_s
10054 {
10055  uint32_t sel : 2; /* emac0_tx_d2 Mux Selection Field */
10056  uint32_t : 30; /* *UNDEFINED* */
10057 };
10058 
10059 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO3. */
10060 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO3_s ALT_SYSMGR_PINMUX_EMACIO3_t;
10061 #endif /* __ASSEMBLY__ */
10062 
10063 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO3 register from the beginning of the component. */
10064 #define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc
10065 
10066 /*
10067  * Register : emac0_tx_d3 Mux Selection Register - EMACIO4
10068  *
10069  * This register is used to control the peripherals connected to emac0_tx_d3
10070  *
10071  * Only reset by a cold reset (ignores warm reset).
10072  *
10073  * NOTE: These registers should not be modified after IO configuration.There is no
10074  * support for dynamically changing the Pin Mux selections.
10075  *
10076  * Register Layout
10077  *
10078  * Bits | Access | Reset | Description
10079  * :-------|:-------|:------|:--------------------------------
10080  * [1:0] | RW | 0x0 | emac0_tx_d3 Mux Selection Field
10081  * [31:2] | ??? | 0x0 | *UNDEFINED*
10082  *
10083  */
10084 /*
10085  * Field : emac0_tx_d3 Mux Selection Field - sel
10086  *
10087  * Select peripheral signals connected emac0_tx_d3.
10088  *
10089  * 0 : Pin is connected to GPIO/LoanIO number 4.
10090  *
10091  * 1 : Pin is connected to Peripheral signal not applicable.
10092  *
10093  * 2 : Pin is connected to Peripheral signal USB1.D3.
10094  *
10095  * 3 : Pin is connected to Peripheral signal RGMII0.TXD3.
10096  *
10097  * Field Access Macros:
10098  *
10099  */
10100 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10101 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0
10102 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10103 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1
10104 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10105 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2
10106 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */
10107 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003
10108 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value. */
10109 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc
10110 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO4_SEL register field. */
10111 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0
10112 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO4_SEL field value from a register. */
10113 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
10114 /* Produces a ALT_SYSMGR_PINMUX_EMACIO4_SEL register field value suitable for setting the register. */
10115 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
10116 
10117 #ifndef __ASSEMBLY__
10118 /*
10119  * WARNING: The C register and register group struct declarations are provided for
10120  * convenience and illustrative purposes. They should, however, be used with
10121  * caution as the C language standard provides no guarantees about the alignment or
10122  * atomicity of device memory accesses. The recommended practice for writing
10123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10124  * alt_write_word() functions.
10125  *
10126  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO4.
10127  */
10128 struct ALT_SYSMGR_PINMUX_EMACIO4_s
10129 {
10130  uint32_t sel : 2; /* emac0_tx_d3 Mux Selection Field */
10131  uint32_t : 30; /* *UNDEFINED* */
10132 };
10133 
10134 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO4. */
10135 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO4_s ALT_SYSMGR_PINMUX_EMACIO4_t;
10136 #endif /* __ASSEMBLY__ */
10137 
10138 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO4 register from the beginning of the component. */
10139 #define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10
10140 
10141 /*
10142  * Register : emac0_rx_d0 Mux Selection Register - EMACIO5
10143  *
10144  * This register is used to control the peripherals connected to emac0_rx_d0
10145  *
10146  * Only reset by a cold reset (ignores warm reset).
10147  *
10148  * NOTE: These registers should not be modified after IO configuration.There is no
10149  * support for dynamically changing the Pin Mux selections.
10150  *
10151  * Register Layout
10152  *
10153  * Bits | Access | Reset | Description
10154  * :-------|:-------|:------|:--------------------------------
10155  * [1:0] | RW | 0x0 | emac0_rx_d0 Mux Selection Field
10156  * [31:2] | ??? | 0x0 | *UNDEFINED*
10157  *
10158  */
10159 /*
10160  * Field : emac0_rx_d0 Mux Selection Field - sel
10161  *
10162  * Select peripheral signals connected emac0_rx_d0.
10163  *
10164  * 0 : Pin is connected to GPIO/LoanIO number 5.
10165  *
10166  * 1 : Pin is connected to Peripheral signal not applicable.
10167  *
10168  * 2 : Pin is connected to Peripheral signal USB1.D4.
10169  *
10170  * 3 : Pin is connected to Peripheral signal RGMII0.RXD0.
10171  *
10172  * Field Access Macros:
10173  *
10174  */
10175 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10176 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0
10177 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10178 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1
10179 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10180 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2
10181 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */
10182 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003
10183 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value. */
10184 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc
10185 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO5_SEL register field. */
10186 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0
10187 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO5_SEL field value from a register. */
10188 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
10189 /* Produces a ALT_SYSMGR_PINMUX_EMACIO5_SEL register field value suitable for setting the register. */
10190 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
10191 
10192 #ifndef __ASSEMBLY__
10193 /*
10194  * WARNING: The C register and register group struct declarations are provided for
10195  * convenience and illustrative purposes. They should, however, be used with
10196  * caution as the C language standard provides no guarantees about the alignment or
10197  * atomicity of device memory accesses. The recommended practice for writing
10198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10199  * alt_write_word() functions.
10200  *
10201  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO5.
10202  */
10203 struct ALT_SYSMGR_PINMUX_EMACIO5_s
10204 {
10205  uint32_t sel : 2; /* emac0_rx_d0 Mux Selection Field */
10206  uint32_t : 30; /* *UNDEFINED* */
10207 };
10208 
10209 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO5. */
10210 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO5_s ALT_SYSMGR_PINMUX_EMACIO5_t;
10211 #endif /* __ASSEMBLY__ */
10212 
10213 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO5 register from the beginning of the component. */
10214 #define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14
10215 
10216 /*
10217  * Register : emac0_mdio Mux Selection Register - EMACIO6
10218  *
10219  * This register is used to control the peripherals connected to emac0_mdio
10220  *
10221  * Only reset by a cold reset (ignores warm reset).
10222  *
10223  * NOTE: These registers should not be modified after IO configuration.There is no
10224  * support for dynamically changing the Pin Mux selections.
10225  *
10226  * Register Layout
10227  *
10228  * Bits | Access | Reset | Description
10229  * :-------|:-------|:------|:-------------------------------
10230  * [1:0] | RW | 0x0 | emac0_mdio Mux Selection Field
10231  * [31:2] | ??? | 0x0 | *UNDEFINED*
10232  *
10233  */
10234 /*
10235  * Field : emac0_mdio Mux Selection Field - sel
10236  *
10237  * Select peripheral signals connected emac0_mdio.
10238  *
10239  * 0 : Pin is connected to GPIO/LoanIO number 6.
10240  *
10241  * 1 : Pin is connected to Peripheral signal I2C2.SDA.
10242  *
10243  * 2 : Pin is connected to Peripheral signal USB1.D5.
10244  *
10245  * 3 : Pin is connected to Peripheral signal RGMII0.MDIO.
10246  *
10247  * Field Access Macros:
10248  *
10249  */
10250 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10251 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0
10252 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10253 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1
10254 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10255 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2
10256 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */
10257 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003
10258 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value. */
10259 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc
10260 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO6_SEL register field. */
10261 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0
10262 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO6_SEL field value from a register. */
10263 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
10264 /* Produces a ALT_SYSMGR_PINMUX_EMACIO6_SEL register field value suitable for setting the register. */
10265 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
10266 
10267 #ifndef __ASSEMBLY__
10268 /*
10269  * WARNING: The C register and register group struct declarations are provided for
10270  * convenience and illustrative purposes. They should, however, be used with
10271  * caution as the C language standard provides no guarantees about the alignment or
10272  * atomicity of device memory accesses. The recommended practice for writing
10273  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10274  * alt_write_word() functions.
10275  *
10276  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO6.
10277  */
10278 struct ALT_SYSMGR_PINMUX_EMACIO6_s
10279 {
10280  uint32_t sel : 2; /* emac0_mdio Mux Selection Field */
10281  uint32_t : 30; /* *UNDEFINED* */
10282 };
10283 
10284 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO6. */
10285 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO6_s ALT_SYSMGR_PINMUX_EMACIO6_t;
10286 #endif /* __ASSEMBLY__ */
10287 
10288 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO6 register from the beginning of the component. */
10289 #define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18
10290 
10291 /*
10292  * Register : emac0_mdc Mux Selection Register - EMACIO7
10293  *
10294  * This register is used to control the peripherals connected to emac0_mdc
10295  *
10296  * Only reset by a cold reset (ignores warm reset).
10297  *
10298  * NOTE: These registers should not be modified after IO configuration.There is no
10299  * support for dynamically changing the Pin Mux selections.
10300  *
10301  * Register Layout
10302  *
10303  * Bits | Access | Reset | Description
10304  * :-------|:-------|:------|:------------------------------
10305  * [1:0] | RW | 0x0 | emac0_mdc Mux Selection Field
10306  * [31:2] | ??? | 0x0 | *UNDEFINED*
10307  *
10308  */
10309 /*
10310  * Field : emac0_mdc Mux Selection Field - sel
10311  *
10312  * Select peripheral signals connected emac0_mdc.
10313  *
10314  * 0 : Pin is connected to GPIO/LoanIO number 7.
10315  *
10316  * 1 : Pin is connected to Peripheral signal I2C2.SCL.
10317  *
10318  * 2 : Pin is connected to Peripheral signal USB1.D6.
10319  *
10320  * 3 : Pin is connected to Peripheral signal RGMII0.MDC.
10321  *
10322  * Field Access Macros:
10323  *
10324  */
10325 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10326 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0
10327 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10328 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1
10329 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10330 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2
10331 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */
10332 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003
10333 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value. */
10334 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc
10335 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO7_SEL register field. */
10336 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0
10337 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO7_SEL field value from a register. */
10338 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
10339 /* Produces a ALT_SYSMGR_PINMUX_EMACIO7_SEL register field value suitable for setting the register. */
10340 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
10341 
10342 #ifndef __ASSEMBLY__
10343 /*
10344  * WARNING: The C register and register group struct declarations are provided for
10345  * convenience and illustrative purposes. They should, however, be used with
10346  * caution as the C language standard provides no guarantees about the alignment or
10347  * atomicity of device memory accesses. The recommended practice for writing
10348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10349  * alt_write_word() functions.
10350  *
10351  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO7.
10352  */
10353 struct ALT_SYSMGR_PINMUX_EMACIO7_s
10354 {
10355  uint32_t sel : 2; /* emac0_mdc Mux Selection Field */
10356  uint32_t : 30; /* *UNDEFINED* */
10357 };
10358 
10359 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO7. */
10360 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO7_s ALT_SYSMGR_PINMUX_EMACIO7_t;
10361 #endif /* __ASSEMBLY__ */
10362 
10363 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO7 register from the beginning of the component. */
10364 #define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c
10365 
10366 /*
10367  * Register : emac0_rx_ctl Mux Selection Register - EMACIO8
10368  *
10369  * This register is used to control the peripherals connected to emac0_rx_ctl
10370  *
10371  * Only reset by a cold reset (ignores warm reset).
10372  *
10373  * NOTE: These registers should not be modified after IO configuration.There is no
10374  * support for dynamically changing the Pin Mux selections.
10375  *
10376  * Register Layout
10377  *
10378  * Bits | Access | Reset | Description
10379  * :-------|:-------|:------|:---------------------------------
10380  * [1:0] | RW | 0x0 | emac0_rx_ctl Mux Selection Field
10381  * [31:2] | ??? | 0x0 | *UNDEFINED*
10382  *
10383  */
10384 /*
10385  * Field : emac0_rx_ctl Mux Selection Field - sel
10386  *
10387  * Select peripheral signals connected emac0_rx_ctl.
10388  *
10389  * 0 : Pin is connected to GPIO/LoanIO number 8.
10390  *
10391  * 1 : Pin is connected to Peripheral signal not applicable.
10392  *
10393  * 2 : Pin is connected to Peripheral signal USB1.D7.
10394  *
10395  * 3 : Pin is connected to Peripheral signal RGMII0.RX_CTL.
10396  *
10397  * Field Access Macros:
10398  *
10399  */
10400 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10401 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0
10402 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10403 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1
10404 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10405 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2
10406 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */
10407 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003
10408 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value. */
10409 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc
10410 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO8_SEL register field. */
10411 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0
10412 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO8_SEL field value from a register. */
10413 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
10414 /* Produces a ALT_SYSMGR_PINMUX_EMACIO8_SEL register field value suitable for setting the register. */
10415 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
10416 
10417 #ifndef __ASSEMBLY__
10418 /*
10419  * WARNING: The C register and register group struct declarations are provided for
10420  * convenience and illustrative purposes. They should, however, be used with
10421  * caution as the C language standard provides no guarantees about the alignment or
10422  * atomicity of device memory accesses. The recommended practice for writing
10423  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10424  * alt_write_word() functions.
10425  *
10426  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO8.
10427  */
10428 struct ALT_SYSMGR_PINMUX_EMACIO8_s
10429 {
10430  uint32_t sel : 2; /* emac0_rx_ctl Mux Selection Field */
10431  uint32_t : 30; /* *UNDEFINED* */
10432 };
10433 
10434 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO8. */
10435 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO8_s ALT_SYSMGR_PINMUX_EMACIO8_t;
10436 #endif /* __ASSEMBLY__ */
10437 
10438 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO8 register from the beginning of the component. */
10439 #define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20
10440 
10441 /*
10442  * Register : emac0_tx_ctl Mux Selection Register - EMACIO9
10443  *
10444  * This register is used to control the peripherals connected to emac0_tx_ctl
10445  *
10446  * Only reset by a cold reset (ignores warm reset).
10447  *
10448  * NOTE: These registers should not be modified after IO configuration.There is no
10449  * support for dynamically changing the Pin Mux selections.
10450  *
10451  * Register Layout
10452  *
10453  * Bits | Access | Reset | Description
10454  * :-------|:-------|:------|:---------------------------------
10455  * [1:0] | RW | 0x0 | emac0_tx_ctl Mux Selection Field
10456  * [31:2] | ??? | 0x0 | *UNDEFINED*
10457  *
10458  */
10459 /*
10460  * Field : emac0_tx_ctl Mux Selection Field - sel
10461  *
10462  * Select peripheral signals connected emac0_tx_ctl.
10463  *
10464  * 0 : Pin is connected to GPIO/LoanIO number 9.
10465  *
10466  * 1 : Pin is connected to Peripheral signal not applicable.
10467  *
10468  * 2 : Pin is connected to Peripheral signal not applicable.
10469  *
10470  * 3 : Pin is connected to Peripheral signal RGMII0.TX_CTL.
10471  *
10472  * Field Access Macros:
10473  *
10474  */
10475 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10476 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0
10477 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10478 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1
10479 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10480 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2
10481 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */
10482 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003
10483 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value. */
10484 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc
10485 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO9_SEL register field. */
10486 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0
10487 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO9_SEL field value from a register. */
10488 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
10489 /* Produces a ALT_SYSMGR_PINMUX_EMACIO9_SEL register field value suitable for setting the register. */
10490 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
10491 
10492 #ifndef __ASSEMBLY__
10493 /*
10494  * WARNING: The C register and register group struct declarations are provided for
10495  * convenience and illustrative purposes. They should, however, be used with
10496  * caution as the C language standard provides no guarantees about the alignment or
10497  * atomicity of device memory accesses. The recommended practice for writing
10498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10499  * alt_write_word() functions.
10500  *
10501  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO9.
10502  */
10503 struct ALT_SYSMGR_PINMUX_EMACIO9_s
10504 {
10505  uint32_t sel : 2; /* emac0_tx_ctl Mux Selection Field */
10506  uint32_t : 30; /* *UNDEFINED* */
10507 };
10508 
10509 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO9. */
10510 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO9_s ALT_SYSMGR_PINMUX_EMACIO9_t;
10511 #endif /* __ASSEMBLY__ */
10512 
10513 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO9 register from the beginning of the component. */
10514 #define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24
10515 
10516 /*
10517  * Register : emac0_rx_clk Mux Selection Register - EMACIO10
10518  *
10519  * This register is used to control the peripherals connected to emac0_rx_clk
10520  *
10521  * Only reset by a cold reset (ignores warm reset).
10522  *
10523  * NOTE: These registers should not be modified after IO configuration.There is no
10524  * support for dynamically changing the Pin Mux selections.
10525  *
10526  * Register Layout
10527  *
10528  * Bits | Access | Reset | Description
10529  * :-------|:-------|:------|:---------------------------------
10530  * [1:0] | RW | 0x0 | emac0_rx_clk Mux Selection Field
10531  * [31:2] | ??? | 0x0 | *UNDEFINED*
10532  *
10533  */
10534 /*
10535  * Field : emac0_rx_clk Mux Selection Field - sel
10536  *
10537  * Select peripheral signals connected emac0_rx_clk.
10538  *
10539  * 0 : Pin is connected to GPIO/LoanIO number 10.
10540  *
10541  * 1 : Pin is connected to Peripheral signal not applicable.
10542  *
10543  * 2 : Pin is connected to Peripheral signal USB1.CLK.
10544  *
10545  * 3 : Pin is connected to Peripheral signal RGMII0.RX_CLK.
10546  *
10547  * Field Access Macros:
10548  *
10549  */
10550 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10551 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0
10552 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10553 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1
10554 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10555 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2
10556 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */
10557 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003
10558 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value. */
10559 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc
10560 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO10_SEL register field. */
10561 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0
10562 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO10_SEL field value from a register. */
10563 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
10564 /* Produces a ALT_SYSMGR_PINMUX_EMACIO10_SEL register field value suitable for setting the register. */
10565 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
10566 
10567 #ifndef __ASSEMBLY__
10568 /*
10569  * WARNING: The C register and register group struct declarations are provided for
10570  * convenience and illustrative purposes. They should, however, be used with
10571  * caution as the C language standard provides no guarantees about the alignment or
10572  * atomicity of device memory accesses. The recommended practice for writing
10573  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10574  * alt_write_word() functions.
10575  *
10576  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO10.
10577  */
10578 struct ALT_SYSMGR_PINMUX_EMACIO10_s
10579 {
10580  uint32_t sel : 2; /* emac0_rx_clk Mux Selection Field */
10581  uint32_t : 30; /* *UNDEFINED* */
10582 };
10583 
10584 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO10. */
10585 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO10_s ALT_SYSMGR_PINMUX_EMACIO10_t;
10586 #endif /* __ASSEMBLY__ */
10587 
10588 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO10 register from the beginning of the component. */
10589 #define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28
10590 
10591 /*
10592  * Register : emac0_rx_d1 Mux Selection Register - EMACIO11
10593  *
10594  * This register is used to control the peripherals connected to emac0_rx_d1
10595  *
10596  * Only reset by a cold reset (ignores warm reset).
10597  *
10598  * NOTE: These registers should not be modified after IO configuration.There is no
10599  * support for dynamically changing the Pin Mux selections.
10600  *
10601  * Register Layout
10602  *
10603  * Bits | Access | Reset | Description
10604  * :-------|:-------|:------|:--------------------------------
10605  * [1:0] | RW | 0x0 | emac0_rx_d1 Mux Selection Field
10606  * [31:2] | ??? | 0x0 | *UNDEFINED*
10607  *
10608  */
10609 /*
10610  * Field : emac0_rx_d1 Mux Selection Field - sel
10611  *
10612  * Select peripheral signals connected emac0_rx_d1.
10613  *
10614  * 0 : Pin is connected to GPIO/LoanIO number 11.
10615  *
10616  * 1 : Pin is connected to Peripheral signal not applicable.
10617  *
10618  * 2 : Pin is connected to Peripheral signal USB1.STP.
10619  *
10620  * 3 : Pin is connected to Peripheral signal RGMII0.RXD1.
10621  *
10622  * Field Access Macros:
10623  *
10624  */
10625 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10626 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0
10627 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10628 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1
10629 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10630 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2
10631 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */
10632 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003
10633 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value. */
10634 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc
10635 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO11_SEL register field. */
10636 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0
10637 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO11_SEL field value from a register. */
10638 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
10639 /* Produces a ALT_SYSMGR_PINMUX_EMACIO11_SEL register field value suitable for setting the register. */
10640 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
10641 
10642 #ifndef __ASSEMBLY__
10643 /*
10644  * WARNING: The C register and register group struct declarations are provided for
10645  * convenience and illustrative purposes. They should, however, be used with
10646  * caution as the C language standard provides no guarantees about the alignment or
10647  * atomicity of device memory accesses. The recommended practice for writing
10648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10649  * alt_write_word() functions.
10650  *
10651  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO11.
10652  */
10653 struct ALT_SYSMGR_PINMUX_EMACIO11_s
10654 {
10655  uint32_t sel : 2; /* emac0_rx_d1 Mux Selection Field */
10656  uint32_t : 30; /* *UNDEFINED* */
10657 };
10658 
10659 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO11. */
10660 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO11_s ALT_SYSMGR_PINMUX_EMACIO11_t;
10661 #endif /* __ASSEMBLY__ */
10662 
10663 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO11 register from the beginning of the component. */
10664 #define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c
10665 
10666 /*
10667  * Register : emac0_rx_d2 Mux Selection Register - EMACIO12
10668  *
10669  * This register is used to control the peripherals connected to emac0_rx_d2
10670  *
10671  * Only reset by a cold reset (ignores warm reset).
10672  *
10673  * NOTE: These registers should not be modified after IO configuration.There is no
10674  * support for dynamically changing the Pin Mux selections.
10675  *
10676  * Register Layout
10677  *
10678  * Bits | Access | Reset | Description
10679  * :-------|:-------|:------|:--------------------------------
10680  * [1:0] | RW | 0x0 | emac0_rx_d2 Mux Selection Field
10681  * [31:2] | ??? | 0x0 | *UNDEFINED*
10682  *
10683  */
10684 /*
10685  * Field : emac0_rx_d2 Mux Selection Field - sel
10686  *
10687  * Select peripheral signals connected emac0_rx_d2.
10688  *
10689  * 0 : Pin is connected to GPIO/LoanIO number 12.
10690  *
10691  * 1 : Pin is connected to Peripheral signal not applicable.
10692  *
10693  * 2 : Pin is connected to Peripheral signal USB1.DIR.
10694  *
10695  * 3 : Pin is connected to Peripheral signal RGMII0.RXD2.
10696  *
10697  * Field Access Macros:
10698  *
10699  */
10700 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10701 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0
10702 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10703 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1
10704 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10705 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2
10706 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */
10707 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003
10708 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value. */
10709 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc
10710 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO12_SEL register field. */
10711 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0
10712 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO12_SEL field value from a register. */
10713 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
10714 /* Produces a ALT_SYSMGR_PINMUX_EMACIO12_SEL register field value suitable for setting the register. */
10715 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
10716 
10717 #ifndef __ASSEMBLY__
10718 /*
10719  * WARNING: The C register and register group struct declarations are provided for
10720  * convenience and illustrative purposes. They should, however, be used with
10721  * caution as the C language standard provides no guarantees about the alignment or
10722  * atomicity of device memory accesses. The recommended practice for writing
10723  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10724  * alt_write_word() functions.
10725  *
10726  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO12.
10727  */
10728 struct ALT_SYSMGR_PINMUX_EMACIO12_s
10729 {
10730  uint32_t sel : 2; /* emac0_rx_d2 Mux Selection Field */
10731  uint32_t : 30; /* *UNDEFINED* */
10732 };
10733 
10734 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO12. */
10735 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO12_s ALT_SYSMGR_PINMUX_EMACIO12_t;
10736 #endif /* __ASSEMBLY__ */
10737 
10738 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO12 register from the beginning of the component. */
10739 #define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30
10740 
10741 /*
10742  * Register : emac0_rx_d3 Mux Selection Register - EMACIO13
10743  *
10744  * This register is used to control the peripherals connected to emac0_rx_d3
10745  *
10746  * Only reset by a cold reset (ignores warm reset).
10747  *
10748  * NOTE: These registers should not be modified after IO configuration.There is no
10749  * support for dynamically changing the Pin Mux selections.
10750  *
10751  * Register Layout
10752  *
10753  * Bits | Access | Reset | Description
10754  * :-------|:-------|:------|:--------------------------------
10755  * [1:0] | RW | 0x0 | emac0_rx_d3 Mux Selection Field
10756  * [31:2] | ??? | 0x0 | *UNDEFINED*
10757  *
10758  */
10759 /*
10760  * Field : emac0_rx_d3 Mux Selection Field - sel
10761  *
10762  * Select peripheral signals connected emac0_rx_d3.
10763  *
10764  * 0 : Pin is connected to GPIO/LoanIO number 13.
10765  *
10766  * 1 : Pin is connected to Peripheral signal not applicable.
10767  *
10768  * 2 : Pin is connected to Peripheral signal USB1.NXT.
10769  *
10770  * 3 : Pin is connected to Peripheral signal RGMII0.RXD3.
10771  *
10772  * Field Access Macros:
10773  *
10774  */
10775 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10776 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0
10777 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10778 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1
10779 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10780 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2
10781 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */
10782 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003
10783 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value. */
10784 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc
10785 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO13_SEL register field. */
10786 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0
10787 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO13_SEL field value from a register. */
10788 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
10789 /* Produces a ALT_SYSMGR_PINMUX_EMACIO13_SEL register field value suitable for setting the register. */
10790 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
10791 
10792 #ifndef __ASSEMBLY__
10793 /*
10794  * WARNING: The C register and register group struct declarations are provided for
10795  * convenience and illustrative purposes. They should, however, be used with
10796  * caution as the C language standard provides no guarantees about the alignment or
10797  * atomicity of device memory accesses. The recommended practice for writing
10798  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10799  * alt_write_word() functions.
10800  *
10801  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO13.
10802  */
10803 struct ALT_SYSMGR_PINMUX_EMACIO13_s
10804 {
10805  uint32_t sel : 2; /* emac0_rx_d3 Mux Selection Field */
10806  uint32_t : 30; /* *UNDEFINED* */
10807 };
10808 
10809 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO13. */
10810 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO13_s ALT_SYSMGR_PINMUX_EMACIO13_t;
10811 #endif /* __ASSEMBLY__ */
10812 
10813 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO13 register from the beginning of the component. */
10814 #define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34
10815 
10816 /*
10817  * Register : emac1_tx_clk Mux Selection Register - EMACIO14
10818  *
10819  * This register is used to control the peripherals connected to emac1_tx_clk
10820  *
10821  * Only reset by a cold reset (ignores warm reset).
10822  *
10823  * NOTE: These registers should not be modified after IO configuration.There is no
10824  * support for dynamically changing the Pin Mux selections.
10825  *
10826  * Register Layout
10827  *
10828  * Bits | Access | Reset | Description
10829  * :-------|:-------|:------|:---------------------------------
10830  * [1:0] | RW | 0x0 | emac1_tx_clk Mux Selection Field
10831  * [31:2] | ??? | 0x0 | *UNDEFINED*
10832  *
10833  */
10834 /*
10835  * Field : emac1_tx_clk Mux Selection Field - sel
10836  *
10837  * Select peripheral signals connected emac1_tx_clk.
10838  *
10839  * 0 : Pin is connected to GPIO/LoanIO number 48.
10840  *
10841  * 1 : Pin is connected to Peripheral signal not applicable.
10842  *
10843  * 2 : Pin is connected to Peripheral signal not applicable.
10844  *
10845  * 3 : Pin is connected to Peripheral signal RGMII1.TX_CLK.
10846  *
10847  * Field Access Macros:
10848  *
10849  */
10850 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10851 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0
10852 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10853 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1
10854 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10855 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2
10856 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */
10857 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003
10858 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value. */
10859 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc
10860 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO14_SEL register field. */
10861 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0
10862 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO14_SEL field value from a register. */
10863 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
10864 /* Produces a ALT_SYSMGR_PINMUX_EMACIO14_SEL register field value suitable for setting the register. */
10865 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
10866 
10867 #ifndef __ASSEMBLY__
10868 /*
10869  * WARNING: The C register and register group struct declarations are provided for
10870  * convenience and illustrative purposes. They should, however, be used with
10871  * caution as the C language standard provides no guarantees about the alignment or
10872  * atomicity of device memory accesses. The recommended practice for writing
10873  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10874  * alt_write_word() functions.
10875  *
10876  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO14.
10877  */
10878 struct ALT_SYSMGR_PINMUX_EMACIO14_s
10879 {
10880  uint32_t sel : 2; /* emac1_tx_clk Mux Selection Field */
10881  uint32_t : 30; /* *UNDEFINED* */
10882 };
10883 
10884 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO14. */
10885 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO14_s ALT_SYSMGR_PINMUX_EMACIO14_t;
10886 #endif /* __ASSEMBLY__ */
10887 
10888 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO14 register from the beginning of the component. */
10889 #define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38
10890 
10891 /*
10892  * Register : emac1_tx_d0 Mux Selection Register - EMACIO15
10893  *
10894  * This register is used to control the peripherals connected to emac1_tx_d0
10895  *
10896  * Only reset by a cold reset (ignores warm reset).
10897  *
10898  * NOTE: These registers should not be modified after IO configuration.There is no
10899  * support for dynamically changing the Pin Mux selections.
10900  *
10901  * Register Layout
10902  *
10903  * Bits | Access | Reset | Description
10904  * :-------|:-------|:------|:--------------------------------
10905  * [1:0] | RW | 0x0 | emac1_tx_d0 Mux Selection Field
10906  * [31:2] | ??? | 0x0 | *UNDEFINED*
10907  *
10908  */
10909 /*
10910  * Field : emac1_tx_d0 Mux Selection Field - sel
10911  *
10912  * Select peripheral signals connected emac1_tx_d0.
10913  *
10914  * 0 : Pin is connected to GPIO/LoanIO number 49.
10915  *
10916  * 1 : Pin is connected to Peripheral signal not applicable.
10917  *
10918  * 2 : Pin is connected to Peripheral signal not applicable.
10919  *
10920  * 3 : Pin is connected to Peripheral signal RGMII1.TXD0.
10921  *
10922  * Field Access Macros:
10923  *
10924  */
10925 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10926 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0
10927 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10928 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1
10929 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10930 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2
10931 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */
10932 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003
10933 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value. */
10934 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc
10935 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO15_SEL register field. */
10936 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0
10937 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO15_SEL field value from a register. */
10938 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
10939 /* Produces a ALT_SYSMGR_PINMUX_EMACIO15_SEL register field value suitable for setting the register. */
10940 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
10941 
10942 #ifndef __ASSEMBLY__
10943 /*
10944  * WARNING: The C register and register group struct declarations are provided for
10945  * convenience and illustrative purposes. They should, however, be used with
10946  * caution as the C language standard provides no guarantees about the alignment or
10947  * atomicity of device memory accesses. The recommended practice for writing
10948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
10949  * alt_write_word() functions.
10950  *
10951  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO15.
10952  */
10953 struct ALT_SYSMGR_PINMUX_EMACIO15_s
10954 {
10955  uint32_t sel : 2; /* emac1_tx_d0 Mux Selection Field */
10956  uint32_t : 30; /* *UNDEFINED* */
10957 };
10958 
10959 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO15. */
10960 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO15_s ALT_SYSMGR_PINMUX_EMACIO15_t;
10961 #endif /* __ASSEMBLY__ */
10962 
10963 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO15 register from the beginning of the component. */
10964 #define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c
10965 
10966 /*
10967  * Register : emac1_tx_d1 Mux Selection Register - EMACIO16
10968  *
10969  * This register is used to control the peripherals connected to emac1_tx_d1
10970  *
10971  * Only reset by a cold reset (ignores warm reset).
10972  *
10973  * NOTE: These registers should not be modified after IO configuration.There is no
10974  * support for dynamically changing the Pin Mux selections.
10975  *
10976  * Register Layout
10977  *
10978  * Bits | Access | Reset | Description
10979  * :-------|:-------|:------|:--------------------------------
10980  * [1:0] | RW | 0x0 | emac1_tx_d1 Mux Selection Field
10981  * [31:2] | ??? | 0x0 | *UNDEFINED*
10982  *
10983  */
10984 /*
10985  * Field : emac1_tx_d1 Mux Selection Field - sel
10986  *
10987  * Select peripheral signals connected emac1_tx_d1.
10988  *
10989  * 0 : Pin is connected to GPIO/LoanIO number 50.
10990  *
10991  * 1 : Pin is connected to Peripheral signal not applicable.
10992  *
10993  * 2 : Pin is connected to Peripheral signal not applicable.
10994  *
10995  * 3 : Pin is connected to Peripheral signal RGMII1.TXD1.
10996  *
10997  * Field Access Macros:
10998  *
10999  */
11000 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11001 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0
11002 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11003 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1
11004 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11005 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2
11006 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */
11007 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003
11008 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value. */
11009 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc
11010 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO16_SEL register field. */
11011 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0
11012 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO16_SEL field value from a register. */
11013 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
11014 /* Produces a ALT_SYSMGR_PINMUX_EMACIO16_SEL register field value suitable for setting the register. */
11015 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
11016 
11017 #ifndef __ASSEMBLY__
11018 /*
11019  * WARNING: The C register and register group struct declarations are provided for
11020  * convenience and illustrative purposes. They should, however, be used with
11021  * caution as the C language standard provides no guarantees about the alignment or
11022  * atomicity of device memory accesses. The recommended practice for writing
11023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11024  * alt_write_word() functions.
11025  *
11026  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO16.
11027  */
11028 struct ALT_SYSMGR_PINMUX_EMACIO16_s
11029 {
11030  uint32_t sel : 2; /* emac1_tx_d1 Mux Selection Field */
11031  uint32_t : 30; /* *UNDEFINED* */
11032 };
11033 
11034 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO16. */
11035 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO16_s ALT_SYSMGR_PINMUX_EMACIO16_t;
11036 #endif /* __ASSEMBLY__ */
11037 
11038 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO16 register from the beginning of the component. */
11039 #define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40
11040 
11041 /*
11042  * Register : emac1_tx_ctl Mux Selection Register - EMACIO17
11043  *
11044  * This register is used to control the peripherals connected to emac1_tx_ctl
11045  *
11046  * Only reset by a cold reset (ignores warm reset).
11047  *
11048  * NOTE: These registers should not be modified after IO configuration.There is no
11049  * support for dynamically changing the Pin Mux selections.
11050  *
11051  * Register Layout
11052  *
11053  * Bits | Access | Reset | Description
11054  * :-------|:-------|:------|:---------------------------------
11055  * [1:0] | RW | 0x0 | emac1_tx_ctl Mux Selection Field
11056  * [31:2] | ??? | 0x0 | *UNDEFINED*
11057  *
11058  */
11059 /*
11060  * Field : emac1_tx_ctl Mux Selection Field - sel
11061  *
11062  * Select peripheral signals connected emac1_tx_ctl.
11063  *
11064  * 0 : Pin is connected to GPIO/LoanIO number 51.
11065  *
11066  * 1 : Pin is connected to Peripheral signal not applicable.
11067  *
11068  * 2 : Pin is connected to Peripheral signal not applicable.
11069  *
11070  * 3 : Pin is connected to Peripheral signal RGMII1.TX_CTL.
11071  *
11072  * Field Access Macros:
11073  *
11074  */
11075 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11076 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0
11077 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11078 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1
11079 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11080 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2
11081 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */
11082 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003
11083 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value. */
11084 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc
11085 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO17_SEL register field. */
11086 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0
11087 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO17_SEL field value from a register. */
11088 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
11089 /* Produces a ALT_SYSMGR_PINMUX_EMACIO17_SEL register field value suitable for setting the register. */
11090 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
11091 
11092 #ifndef __ASSEMBLY__
11093 /*
11094  * WARNING: The C register and register group struct declarations are provided for
11095  * convenience and illustrative purposes. They should, however, be used with
11096  * caution as the C language standard provides no guarantees about the alignment or
11097  * atomicity of device memory accesses. The recommended practice for writing
11098  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11099  * alt_write_word() functions.
11100  *
11101  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO17.
11102  */
11103 struct ALT_SYSMGR_PINMUX_EMACIO17_s
11104 {
11105  uint32_t sel : 2; /* emac1_tx_ctl Mux Selection Field */
11106  uint32_t : 30; /* *UNDEFINED* */
11107 };
11108 
11109 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO17. */
11110 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO17_s ALT_SYSMGR_PINMUX_EMACIO17_t;
11111 #endif /* __ASSEMBLY__ */
11112 
11113 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO17 register from the beginning of the component. */
11114 #define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44
11115 
11116 /*
11117  * Register : emac1_rx_d0 Mux Selection Register - EMACIO18
11118  *
11119  * This register is used to control the peripherals connected to emac1_rx_d0
11120  *
11121  * Only reset by a cold reset (ignores warm reset).
11122  *
11123  * NOTE: These registers should not be modified after IO configuration.There is no
11124  * support for dynamically changing the Pin Mux selections.
11125  *
11126  * Register Layout
11127  *
11128  * Bits | Access | Reset | Description
11129  * :-------|:-------|:------|:--------------------------------
11130  * [1:0] | RW | 0x0 | emac1_rx_d0 Mux Selection Field
11131  * [31:2] | ??? | 0x0 | *UNDEFINED*
11132  *
11133  */
11134 /*
11135  * Field : emac1_rx_d0 Mux Selection Field - sel
11136  *
11137  * Select peripheral signals connected emac1_rx_d0.
11138  *
11139  * 0 : Pin is connected to GPIO/LoanIO number 52.
11140  *
11141  * 1 : Pin is connected to Peripheral signal not applicable.
11142  *
11143  * 2 : Pin is connected to Peripheral signal not applicable.
11144  *
11145  * 3 : Pin is connected to Peripheral signal RGMII1.RXD0.
11146  *
11147  * Field Access Macros:
11148  *
11149  */
11150 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11151 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0
11152 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11153 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1
11154 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11155 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2
11156 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */
11157 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003
11158 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value. */
11159 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc
11160 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO18_SEL register field. */
11161 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0
11162 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO18_SEL field value from a register. */
11163 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
11164 /* Produces a ALT_SYSMGR_PINMUX_EMACIO18_SEL register field value suitable for setting the register. */
11165 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
11166 
11167 #ifndef __ASSEMBLY__
11168 /*
11169  * WARNING: The C register and register group struct declarations are provided for
11170  * convenience and illustrative purposes. They should, however, be used with
11171  * caution as the C language standard provides no guarantees about the alignment or
11172  * atomicity of device memory accesses. The recommended practice for writing
11173  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11174  * alt_write_word() functions.
11175  *
11176  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO18.
11177  */
11178 struct ALT_SYSMGR_PINMUX_EMACIO18_s
11179 {
11180  uint32_t sel : 2; /* emac1_rx_d0 Mux Selection Field */
11181  uint32_t : 30; /* *UNDEFINED* */
11182 };
11183 
11184 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO18. */
11185 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO18_s ALT_SYSMGR_PINMUX_EMACIO18_t;
11186 #endif /* __ASSEMBLY__ */
11187 
11188 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO18 register from the beginning of the component. */
11189 #define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48
11190 
11191 /*
11192  * Register : emac1_rx_d1 Mux Selection Register - EMACIO19
11193  *
11194  * This register is used to control the peripherals connected to emac1_rx_d1
11195  *
11196  * Only reset by a cold reset (ignores warm reset).
11197  *
11198  * NOTE: These registers should not be modified after IO configuration.There is no
11199  * support for dynamically changing the Pin Mux selections.
11200  *
11201  * Register Layout
11202  *
11203  * Bits | Access | Reset | Description
11204  * :-------|:-------|:------|:--------------------------------
11205  * [1:0] | RW | 0x0 | emac1_rx_d1 Mux Selection Field
11206  * [31:2] | ??? | 0x0 | *UNDEFINED*
11207  *
11208  */
11209 /*
11210  * Field : emac1_rx_d1 Mux Selection Field - sel
11211  *
11212  * Select peripheral signals connected emac1_rx_d1.
11213  *
11214  * 0 : Pin is connected to GPIO/LoanIO number 53.
11215  *
11216  * 1 : Pin is connected to Peripheral signal not applicable.
11217  *
11218  * 2 : Pin is connected to Peripheral signal not applicable.
11219  *
11220  * 3 : Pin is connected to Peripheral signal RGMII1.RXD1.
11221  *
11222  * Field Access Macros:
11223  *
11224  */
11225 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11226 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0
11227 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11228 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1
11229 /* The width in bits of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11230 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2
11231 /* The mask used to set the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */
11232 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003
11233 /* The mask used to clear the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value. */
11234 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc
11235 /* The reset value of the ALT_SYSMGR_PINMUX_EMACIO19_SEL register field. */
11236 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0
11237 /* Extracts the ALT_SYSMGR_PINMUX_EMACIO19_SEL field value from a register. */
11238 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
11239 /* Produces a ALT_SYSMGR_PINMUX_EMACIO19_SEL register field value suitable for setting the register. */
11240 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
11241 
11242 #ifndef __ASSEMBLY__
11243 /*
11244  * WARNING: The C register and register group struct declarations are provided for
11245  * convenience and illustrative purposes. They should, however, be used with
11246  * caution as the C language standard provides no guarantees about the alignment or
11247  * atomicity of device memory accesses. The recommended practice for writing
11248  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11249  * alt_write_word() functions.
11250  *
11251  * The struct declaration for register ALT_SYSMGR_PINMUX_EMACIO19.
11252  */
11253 struct ALT_SYSMGR_PINMUX_EMACIO19_s
11254 {
11255  uint32_t sel : 2; /* emac1_rx_d1 Mux Selection Field */
11256  uint32_t : 30; /* *UNDEFINED* */
11257 };
11258 
11259 /* The typedef declaration for register ALT_SYSMGR_PINMUX_EMACIO19. */
11260 typedef volatile struct ALT_SYSMGR_PINMUX_EMACIO19_s ALT_SYSMGR_PINMUX_EMACIO19_t;
11261 #endif /* __ASSEMBLY__ */
11262 
11263 /* The byte offset of the ALT_SYSMGR_PINMUX_EMACIO19 register from the beginning of the component. */
11264 #define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c
11265 
11266 /*
11267  * Register : sdmmc_cmd Mux Selection Register - FLASHIO0
11268  *
11269  * This register is used to control the peripherals connected to sdmmc_cmd
11270  *
11271  * Only reset by a cold reset (ignores warm reset).
11272  *
11273  * NOTE: These registers should not be modified after IO configuration.There is no
11274  * support for dynamically changing the Pin Mux selections.
11275  *
11276  * Register Layout
11277  *
11278  * Bits | Access | Reset | Description
11279  * :-------|:-------|:------|:------------------------------
11280  * [1:0] | RW | 0x0 | sdmmc_cmd Mux Selection Field
11281  * [31:2] | ??? | 0x0 | *UNDEFINED*
11282  *
11283  */
11284 /*
11285  * Field : sdmmc_cmd Mux Selection Field - sel
11286  *
11287  * Select peripheral signals connected sdmmc_cmd.
11288  *
11289  * 0 : Pin is connected to GPIO/LoanIO number 36.
11290  *
11291  * 1 : Pin is connected to Peripheral signal not applicable.
11292  *
11293  * 2 : Pin is connected to Peripheral signal USB0.D0.
11294  *
11295  * 3 : Pin is connected to Peripheral signal SDMMC.CMD.
11296  *
11297  * Field Access Macros:
11298  *
11299  */
11300 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11301 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0
11302 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11303 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1
11304 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11305 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2
11306 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */
11307 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003
11308 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value. */
11309 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc
11310 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field. */
11311 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0
11312 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO0_SEL field value from a register. */
11313 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
11314 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO0_SEL register field value suitable for setting the register. */
11315 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
11316 
11317 #ifndef __ASSEMBLY__
11318 /*
11319  * WARNING: The C register and register group struct declarations are provided for
11320  * convenience and illustrative purposes. They should, however, be used with
11321  * caution as the C language standard provides no guarantees about the alignment or
11322  * atomicity of device memory accesses. The recommended practice for writing
11323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11324  * alt_write_word() functions.
11325  *
11326  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO0.
11327  */
11328 struct ALT_SYSMGR_PINMUX_FLSHIO0_s
11329 {
11330  uint32_t sel : 2; /* sdmmc_cmd Mux Selection Field */
11331  uint32_t : 30; /* *UNDEFINED* */
11332 };
11333 
11334 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO0. */
11335 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO0_s ALT_SYSMGR_PINMUX_FLSHIO0_t;
11336 #endif /* __ASSEMBLY__ */
11337 
11338 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO0 register from the beginning of the component. */
11339 #define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50
11340 
11341 /*
11342  * Register : sdmmc_pwren Mux Selection Register - FLASHIO1
11343  *
11344  * This register is used to control the peripherals connected to sdmmc_pwren
11345  *
11346  * Only reset by a cold reset (ignores warm reset).
11347  *
11348  * NOTE: These registers should not be modified after IO configuration.There is no
11349  * support for dynamically changing the Pin Mux selections.
11350  *
11351  * Register Layout
11352  *
11353  * Bits | Access | Reset | Description
11354  * :-------|:-------|:------|:--------------------------------
11355  * [1:0] | RW | 0x0 | sdmmc_pwren Mux Selection Field
11356  * [31:2] | ??? | 0x0 | *UNDEFINED*
11357  *
11358  */
11359 /*
11360  * Field : sdmmc_pwren Mux Selection Field - sel
11361  *
11362  * Select peripheral signals connected sdmmc_pwren.
11363  *
11364  * 0 : Pin is connected to GPIO/LoanIO number 37.
11365  *
11366  * 1 : Pin is connected to Peripheral signal not applicable.
11367  *
11368  * 2 : Pin is connected to Peripheral signal USB0.D1.
11369  *
11370  * 3 : Pin is connected to Peripheral signal SDMMC.PWREN.
11371  *
11372  * Field Access Macros:
11373  *
11374  */
11375 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11376 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0
11377 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11378 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1
11379 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11380 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2
11381 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */
11382 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003
11383 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value. */
11384 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc
11385 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field. */
11386 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0
11387 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO1_SEL field value from a register. */
11388 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
11389 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO1_SEL register field value suitable for setting the register. */
11390 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
11391 
11392 #ifndef __ASSEMBLY__
11393 /*
11394  * WARNING: The C register and register group struct declarations are provided for
11395  * convenience and illustrative purposes. They should, however, be used with
11396  * caution as the C language standard provides no guarantees about the alignment or
11397  * atomicity of device memory accesses. The recommended practice for writing
11398  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11399  * alt_write_word() functions.
11400  *
11401  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO1.
11402  */
11403 struct ALT_SYSMGR_PINMUX_FLSHIO1_s
11404 {
11405  uint32_t sel : 2; /* sdmmc_pwren Mux Selection Field */
11406  uint32_t : 30; /* *UNDEFINED* */
11407 };
11408 
11409 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO1. */
11410 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO1_s ALT_SYSMGR_PINMUX_FLSHIO1_t;
11411 #endif /* __ASSEMBLY__ */
11412 
11413 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO1 register from the beginning of the component. */
11414 #define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54
11415 
11416 /*
11417  * Register : sdmmc_d0 Mux Selection Register - FLASHIO2
11418  *
11419  * This register is used to control the peripherals connected to sdmmc_d0
11420  *
11421  * Only reset by a cold reset (ignores warm reset).
11422  *
11423  * NOTE: These registers should not be modified after IO configuration.There is no
11424  * support for dynamically changing the Pin Mux selections.
11425  *
11426  * Register Layout
11427  *
11428  * Bits | Access | Reset | Description
11429  * :-------|:-------|:------|:-----------------------------
11430  * [1:0] | RW | 0x0 | sdmmc_d0 Mux Selection Field
11431  * [31:2] | ??? | 0x0 | *UNDEFINED*
11432  *
11433  */
11434 /*
11435  * Field : sdmmc_d0 Mux Selection Field - sel
11436  *
11437  * Select peripheral signals connected sdmmc_d0.
11438  *
11439  * 0 : Pin is connected to GPIO/LoanIO number 38.
11440  *
11441  * 1 : Pin is connected to Peripheral signal not applicable.
11442  *
11443  * 2 : Pin is connected to Peripheral signal USB0.D2.
11444  *
11445  * 3 : Pin is connected to Peripheral signal SDMMC.D0.
11446  *
11447  * Field Access Macros:
11448  *
11449  */
11450 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11451 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0
11452 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11453 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1
11454 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11455 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2
11456 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */
11457 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003
11458 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value. */
11459 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc
11460 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field. */
11461 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0
11462 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO2_SEL field value from a register. */
11463 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
11464 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO2_SEL register field value suitable for setting the register. */
11465 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
11466 
11467 #ifndef __ASSEMBLY__
11468 /*
11469  * WARNING: The C register and register group struct declarations are provided for
11470  * convenience and illustrative purposes. They should, however, be used with
11471  * caution as the C language standard provides no guarantees about the alignment or
11472  * atomicity of device memory accesses. The recommended practice for writing
11473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11474  * alt_write_word() functions.
11475  *
11476  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO2.
11477  */
11478 struct ALT_SYSMGR_PINMUX_FLSHIO2_s
11479 {
11480  uint32_t sel : 2; /* sdmmc_d0 Mux Selection Field */
11481  uint32_t : 30; /* *UNDEFINED* */
11482 };
11483 
11484 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO2. */
11485 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO2_s ALT_SYSMGR_PINMUX_FLSHIO2_t;
11486 #endif /* __ASSEMBLY__ */
11487 
11488 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO2 register from the beginning of the component. */
11489 #define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58
11490 
11491 /*
11492  * Register : sdmmc_d1 Mux Selection Register - FLASHIO3
11493  *
11494  * This register is used to control the peripherals connected to sdmmc_d1
11495  *
11496  * Only reset by a cold reset (ignores warm reset).
11497  *
11498  * NOTE: These registers should not be modified after IO configuration.There is no
11499  * support for dynamically changing the Pin Mux selections.
11500  *
11501  * Register Layout
11502  *
11503  * Bits | Access | Reset | Description
11504  * :-------|:-------|:------|:-----------------------------
11505  * [1:0] | RW | 0x0 | sdmmc_d1 Mux Selection Field
11506  * [31:2] | ??? | 0x0 | *UNDEFINED*
11507  *
11508  */
11509 /*
11510  * Field : sdmmc_d1 Mux Selection Field - sel
11511  *
11512  * Select peripheral signals connected sdmmc_d1.
11513  *
11514  * 0 : Pin is connected to GPIO/LoanIO number 39.
11515  *
11516  * 1 : Pin is connected to Peripheral signal not applicable.
11517  *
11518  * 2 : Pin is connected to Peripheral signal USB0.D3.
11519  *
11520  * 3 : Pin is connected to Peripheral signal SDMMC.D1.
11521  *
11522  * Field Access Macros:
11523  *
11524  */
11525 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11526 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0
11527 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11528 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1
11529 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11530 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2
11531 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */
11532 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003
11533 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value. */
11534 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc
11535 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field. */
11536 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0
11537 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO3_SEL field value from a register. */
11538 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
11539 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO3_SEL register field value suitable for setting the register. */
11540 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
11541 
11542 #ifndef __ASSEMBLY__
11543 /*
11544  * WARNING: The C register and register group struct declarations are provided for
11545  * convenience and illustrative purposes. They should, however, be used with
11546  * caution as the C language standard provides no guarantees about the alignment or
11547  * atomicity of device memory accesses. The recommended practice for writing
11548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11549  * alt_write_word() functions.
11550  *
11551  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO3.
11552  */
11553 struct ALT_SYSMGR_PINMUX_FLSHIO3_s
11554 {
11555  uint32_t sel : 2; /* sdmmc_d1 Mux Selection Field */
11556  uint32_t : 30; /* *UNDEFINED* */
11557 };
11558 
11559 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO3. */
11560 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO3_s ALT_SYSMGR_PINMUX_FLSHIO3_t;
11561 #endif /* __ASSEMBLY__ */
11562 
11563 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO3 register from the beginning of the component. */
11564 #define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c
11565 
11566 /*
11567  * Register : sdmmc_d4 Mux Selection Register - FLASHIO4
11568  *
11569  * This register is used to control the peripherals connected to sdmmc_d4
11570  *
11571  * Only reset by a cold reset (ignores warm reset).
11572  *
11573  * NOTE: These registers should not be modified after IO configuration.There is no
11574  * support for dynamically changing the Pin Mux selections.
11575  *
11576  * Register Layout
11577  *
11578  * Bits | Access | Reset | Description
11579  * :-------|:-------|:------|:-----------------------------
11580  * [1:0] | RW | 0x0 | sdmmc_d4 Mux Selection Field
11581  * [31:2] | ??? | 0x0 | *UNDEFINED*
11582  *
11583  */
11584 /*
11585  * Field : sdmmc_d4 Mux Selection Field - sel
11586  *
11587  * Select peripheral signals connected sdmmc_d4.
11588  *
11589  * 0 : Pin is connected to GPIO/LoanIO number 40.
11590  *
11591  * 1 : Pin is connected to Peripheral signal not applicable.
11592  *
11593  * 2 : Pin is connected to Peripheral signal USB0.D4.
11594  *
11595  * 3 : Pin is connected to Peripheral signal SDMMC.D4.
11596  *
11597  * Field Access Macros:
11598  *
11599  */
11600 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11601 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0
11602 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11603 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1
11604 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11605 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2
11606 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */
11607 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003
11608 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value. */
11609 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc
11610 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field. */
11611 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0
11612 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO4_SEL field value from a register. */
11613 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
11614 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO4_SEL register field value suitable for setting the register. */
11615 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
11616 
11617 #ifndef __ASSEMBLY__
11618 /*
11619  * WARNING: The C register and register group struct declarations are provided for
11620  * convenience and illustrative purposes. They should, however, be used with
11621  * caution as the C language standard provides no guarantees about the alignment or
11622  * atomicity of device memory accesses. The recommended practice for writing
11623  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11624  * alt_write_word() functions.
11625  *
11626  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO4.
11627  */
11628 struct ALT_SYSMGR_PINMUX_FLSHIO4_s
11629 {
11630  uint32_t sel : 2; /* sdmmc_d4 Mux Selection Field */
11631  uint32_t : 30; /* *UNDEFINED* */
11632 };
11633 
11634 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO4. */
11635 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO4_s ALT_SYSMGR_PINMUX_FLSHIO4_t;
11636 #endif /* __ASSEMBLY__ */
11637 
11638 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO4 register from the beginning of the component. */
11639 #define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60
11640 
11641 /*
11642  * Register : sdmmc_d5 Mux Selection Register - FLASHIO5
11643  *
11644  * This register is used to control the peripherals connected to sdmmc_d5
11645  *
11646  * Only reset by a cold reset (ignores warm reset).
11647  *
11648  * NOTE: These registers should not be modified after IO configuration.There is no
11649  * support for dynamically changing the Pin Mux selections.
11650  *
11651  * Register Layout
11652  *
11653  * Bits | Access | Reset | Description
11654  * :-------|:-------|:------|:-----------------------------
11655  * [1:0] | RW | 0x0 | sdmmc_d5 Mux Selection Field
11656  * [31:2] | ??? | 0x0 | *UNDEFINED*
11657  *
11658  */
11659 /*
11660  * Field : sdmmc_d5 Mux Selection Field - sel
11661  *
11662  * Select peripheral signals connected sdmmc_d5.
11663  *
11664  * 0 : Pin is connected to GPIO/LoanIO number 41.
11665  *
11666  * 1 : Pin is connected to Peripheral signal not applicable.
11667  *
11668  * 2 : Pin is connected to Peripheral signal USB0.D5.
11669  *
11670  * 3 : Pin is connected to Peripheral signal SDMMC.D5.
11671  *
11672  * Field Access Macros:
11673  *
11674  */
11675 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11676 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0
11677 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11678 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1
11679 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11680 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2
11681 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */
11682 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003
11683 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value. */
11684 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc
11685 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field. */
11686 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0
11687 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO5_SEL field value from a register. */
11688 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
11689 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO5_SEL register field value suitable for setting the register. */
11690 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
11691 
11692 #ifndef __ASSEMBLY__
11693 /*
11694  * WARNING: The C register and register group struct declarations are provided for
11695  * convenience and illustrative purposes. They should, however, be used with
11696  * caution as the C language standard provides no guarantees about the alignment or
11697  * atomicity of device memory accesses. The recommended practice for writing
11698  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11699  * alt_write_word() functions.
11700  *
11701  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO5.
11702  */
11703 struct ALT_SYSMGR_PINMUX_FLSHIO5_s
11704 {
11705  uint32_t sel : 2; /* sdmmc_d5 Mux Selection Field */
11706  uint32_t : 30; /* *UNDEFINED* */
11707 };
11708 
11709 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO5. */
11710 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO5_s ALT_SYSMGR_PINMUX_FLSHIO5_t;
11711 #endif /* __ASSEMBLY__ */
11712 
11713 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO5 register from the beginning of the component. */
11714 #define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64
11715 
11716 /*
11717  * Register : sdmmc_d6 Mux Selection Register - FLASHIO6
11718  *
11719  * This register is used to control the peripherals connected to sdmmc_d6
11720  *
11721  * Only reset by a cold reset (ignores warm reset).
11722  *
11723  * NOTE: These registers should not be modified after IO configuration.There is no
11724  * support for dynamically changing the Pin Mux selections.
11725  *
11726  * Register Layout
11727  *
11728  * Bits | Access | Reset | Description
11729  * :-------|:-------|:------|:-----------------------------
11730  * [1:0] | RW | 0x0 | sdmmc_d6 Mux Selection Field
11731  * [31:2] | ??? | 0x0 | *UNDEFINED*
11732  *
11733  */
11734 /*
11735  * Field : sdmmc_d6 Mux Selection Field - sel
11736  *
11737  * Select peripheral signals connected sdmmc_d6.
11738  *
11739  * 0 : Pin is connected to GPIO/LoanIO number 42.
11740  *
11741  * 1 : Pin is connected to Peripheral signal not applicable.
11742  *
11743  * 2 : Pin is connected to Peripheral signal USB0.D6.
11744  *
11745  * 3 : Pin is connected to Peripheral signal SDMMC.D6.
11746  *
11747  * Field Access Macros:
11748  *
11749  */
11750 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11751 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0
11752 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11753 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1
11754 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11755 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2
11756 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */
11757 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003
11758 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value. */
11759 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc
11760 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field. */
11761 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0
11762 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO6_SEL field value from a register. */
11763 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
11764 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO6_SEL register field value suitable for setting the register. */
11765 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
11766 
11767 #ifndef __ASSEMBLY__
11768 /*
11769  * WARNING: The C register and register group struct declarations are provided for
11770  * convenience and illustrative purposes. They should, however, be used with
11771  * caution as the C language standard provides no guarantees about the alignment or
11772  * atomicity of device memory accesses. The recommended practice for writing
11773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11774  * alt_write_word() functions.
11775  *
11776  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO6.
11777  */
11778 struct ALT_SYSMGR_PINMUX_FLSHIO6_s
11779 {
11780  uint32_t sel : 2; /* sdmmc_d6 Mux Selection Field */
11781  uint32_t : 30; /* *UNDEFINED* */
11782 };
11783 
11784 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO6. */
11785 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO6_s ALT_SYSMGR_PINMUX_FLSHIO6_t;
11786 #endif /* __ASSEMBLY__ */
11787 
11788 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO6 register from the beginning of the component. */
11789 #define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68
11790 
11791 /*
11792  * Register : sdmmc_d7 Mux Selection Register - FLASHIO7
11793  *
11794  * This register is used to control the peripherals connected to sdmmc_d7
11795  *
11796  * Only reset by a cold reset (ignores warm reset).
11797  *
11798  * NOTE: These registers should not be modified after IO configuration.There is no
11799  * support for dynamically changing the Pin Mux selections.
11800  *
11801  * Register Layout
11802  *
11803  * Bits | Access | Reset | Description
11804  * :-------|:-------|:------|:-----------------------------
11805  * [1:0] | RW | 0x0 | sdmmc_d7 Mux Selection Field
11806  * [31:2] | ??? | 0x0 | *UNDEFINED*
11807  *
11808  */
11809 /*
11810  * Field : sdmmc_d7 Mux Selection Field - sel
11811  *
11812  * Select peripheral signals connected sdmmc_d7.
11813  *
11814  * 0 : Pin is connected to GPIO/LoanIO number 43.
11815  *
11816  * 1 : Pin is connected to Peripheral signal not applicable.
11817  *
11818  * 2 : Pin is connected to Peripheral signal USB0.D7.
11819  *
11820  * 3 : Pin is connected to Peripheral signal SDMMC.D7.
11821  *
11822  * Field Access Macros:
11823  *
11824  */
11825 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11826 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0
11827 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11828 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1
11829 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11830 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2
11831 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */
11832 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003
11833 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value. */
11834 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc
11835 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field. */
11836 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0
11837 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO7_SEL field value from a register. */
11838 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
11839 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO7_SEL register field value suitable for setting the register. */
11840 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
11841 
11842 #ifndef __ASSEMBLY__
11843 /*
11844  * WARNING: The C register and register group struct declarations are provided for
11845  * convenience and illustrative purposes. They should, however, be used with
11846  * caution as the C language standard provides no guarantees about the alignment or
11847  * atomicity of device memory accesses. The recommended practice for writing
11848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11849  * alt_write_word() functions.
11850  *
11851  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO7.
11852  */
11853 struct ALT_SYSMGR_PINMUX_FLSHIO7_s
11854 {
11855  uint32_t sel : 2; /* sdmmc_d7 Mux Selection Field */
11856  uint32_t : 30; /* *UNDEFINED* */
11857 };
11858 
11859 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO7. */
11860 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO7_s ALT_SYSMGR_PINMUX_FLSHIO7_t;
11861 #endif /* __ASSEMBLY__ */
11862 
11863 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO7 register from the beginning of the component. */
11864 #define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c
11865 
11866 /*
11867  * Register : sdmmc_clk_in Mux Selection Register - FLASHIO8
11868  *
11869  * This register is used to control the peripherals connected to sdmmc_clk_in
11870  *
11871  * Only reset by a cold reset (ignores warm reset).
11872  *
11873  * NOTE: These registers should not be modified after IO configuration.There is no
11874  * support for dynamically changing the Pin Mux selections.
11875  *
11876  * Register Layout
11877  *
11878  * Bits | Access | Reset | Description
11879  * :-------|:-------|:------|:---------------------------------
11880  * [1:0] | RW | 0x0 | sdmmc_clk_in Mux Selection Field
11881  * [31:2] | ??? | 0x0 | *UNDEFINED*
11882  *
11883  */
11884 /*
11885  * Field : sdmmc_clk_in Mux Selection Field - sel
11886  *
11887  * Select peripheral signals connected sdmmc_clk_in.
11888  *
11889  * 0 : Pin is connected to GPIO/LoanIO number 44.
11890  *
11891  * 1 : Pin is connected to Peripheral signal not applicable.
11892  *
11893  * 2 : Pin is connected to Peripheral signal USB0.CLK.
11894  *
11895  * 3 : Pin is connected to Peripheral signal SDMMC.CLK_IN.
11896  *
11897  * Field Access Macros:
11898  *
11899  */
11900 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11901 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0
11902 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11903 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1
11904 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11905 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2
11906 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */
11907 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003
11908 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value. */
11909 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc
11910 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field. */
11911 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0
11912 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO8_SEL field value from a register. */
11913 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
11914 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO8_SEL register field value suitable for setting the register. */
11915 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
11916 
11917 #ifndef __ASSEMBLY__
11918 /*
11919  * WARNING: The C register and register group struct declarations are provided for
11920  * convenience and illustrative purposes. They should, however, be used with
11921  * caution as the C language standard provides no guarantees about the alignment or
11922  * atomicity of device memory accesses. The recommended practice for writing
11923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11924  * alt_write_word() functions.
11925  *
11926  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO8.
11927  */
11928 struct ALT_SYSMGR_PINMUX_FLSHIO8_s
11929 {
11930  uint32_t sel : 2; /* sdmmc_clk_in Mux Selection Field */
11931  uint32_t : 30; /* *UNDEFINED* */
11932 };
11933 
11934 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO8. */
11935 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO8_s ALT_SYSMGR_PINMUX_FLSHIO8_t;
11936 #endif /* __ASSEMBLY__ */
11937 
11938 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO8 register from the beginning of the component. */
11939 #define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70
11940 
11941 /*
11942  * Register : sdmmc_clk Mux Selection Register - FLASHIO9
11943  *
11944  * This register is used to control the peripherals connected to sdmmc_clk
11945  *
11946  * Only reset by a cold reset (ignores warm reset).
11947  *
11948  * NOTE: These registers should not be modified after IO configuration.There is no
11949  * support for dynamically changing the Pin Mux selections.
11950  *
11951  * Register Layout
11952  *
11953  * Bits | Access | Reset | Description
11954  * :-------|:-------|:------|:------------------------------
11955  * [1:0] | RW | 0x0 | sdmmc_clk Mux Selection Field
11956  * [31:2] | ??? | 0x0 | *UNDEFINED*
11957  *
11958  */
11959 /*
11960  * Field : sdmmc_clk Mux Selection Field - sel
11961  *
11962  * Select peripheral signals connected sdmmc_clk.
11963  *
11964  * 0 : Pin is connected to GPIO/LoanIO number 45.
11965  *
11966  * 1 : Pin is connected to Peripheral signal not applicable.
11967  *
11968  * 2 : Pin is connected to Peripheral signal USB0.STP.
11969  *
11970  * 3 : Pin is connected to Peripheral signal SDMMC.CLK.
11971  *
11972  * Field Access Macros:
11973  *
11974  */
11975 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11976 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0
11977 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11978 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1
11979 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11980 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2
11981 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */
11982 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003
11983 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value. */
11984 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc
11985 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field. */
11986 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0
11987 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO9_SEL field value from a register. */
11988 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
11989 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO9_SEL register field value suitable for setting the register. */
11990 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
11991 
11992 #ifndef __ASSEMBLY__
11993 /*
11994  * WARNING: The C register and register group struct declarations are provided for
11995  * convenience and illustrative purposes. They should, however, be used with
11996  * caution as the C language standard provides no guarantees about the alignment or
11997  * atomicity of device memory accesses. The recommended practice for writing
11998  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
11999  * alt_write_word() functions.
12000  *
12001  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO9.
12002  */
12003 struct ALT_SYSMGR_PINMUX_FLSHIO9_s
12004 {
12005  uint32_t sel : 2; /* sdmmc_clk Mux Selection Field */
12006  uint32_t : 30; /* *UNDEFINED* */
12007 };
12008 
12009 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO9. */
12010 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO9_s ALT_SYSMGR_PINMUX_FLSHIO9_t;
12011 #endif /* __ASSEMBLY__ */
12012 
12013 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO9 register from the beginning of the component. */
12014 #define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74
12015 
12016 /*
12017  * Register : sdmmc_d2 Mux Selection Register - FLASHIO10
12018  *
12019  * This register is used to control the peripherals connected to sdmmc_d2
12020  *
12021  * Only reset by a cold reset (ignores warm reset).
12022  *
12023  * NOTE: These registers should not be modified after IO configuration.There is no
12024  * support for dynamically changing the Pin Mux selections.
12025  *
12026  * Register Layout
12027  *
12028  * Bits | Access | Reset | Description
12029  * :-------|:-------|:------|:-----------------------------
12030  * [1:0] | RW | 0x0 | sdmmc_d2 Mux Selection Field
12031  * [31:2] | ??? | 0x0 | *UNDEFINED*
12032  *
12033  */
12034 /*
12035  * Field : sdmmc_d2 Mux Selection Field - sel
12036  *
12037  * Select peripheral signals connected sdmmc_d2.
12038  *
12039  * 0 : Pin is connected to GPIO/LoanIO number 46.
12040  *
12041  * 1 : Pin is connected to Peripheral signal not applicable.
12042  *
12043  * 2 : Pin is connected to Peripheral signal USB0.DIR.
12044  *
12045  * 3 : Pin is connected to Peripheral signal SDMMC.D2.
12046  *
12047  * Field Access Macros:
12048  *
12049  */
12050 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12051 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0
12052 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12053 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1
12054 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12055 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2
12056 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */
12057 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003
12058 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value. */
12059 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc
12060 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field. */
12061 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0
12062 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO10_SEL field value from a register. */
12063 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12064 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO10_SEL register field value suitable for setting the register. */
12065 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12066 
12067 #ifndef __ASSEMBLY__
12068 /*
12069  * WARNING: The C register and register group struct declarations are provided for
12070  * convenience and illustrative purposes. They should, however, be used with
12071  * caution as the C language standard provides no guarantees about the alignment or
12072  * atomicity of device memory accesses. The recommended practice for writing
12073  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12074  * alt_write_word() functions.
12075  *
12076  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO10.
12077  */
12078 struct ALT_SYSMGR_PINMUX_FLSHIO10_s
12079 {
12080  uint32_t sel : 2; /* sdmmc_d2 Mux Selection Field */
12081  uint32_t : 30; /* *UNDEFINED* */
12082 };
12083 
12084 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO10. */
12085 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO10_s ALT_SYSMGR_PINMUX_FLSHIO10_t;
12086 #endif /* __ASSEMBLY__ */
12087 
12088 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO10 register from the beginning of the component. */
12089 #define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78
12090 
12091 /*
12092  * Register : sdmmc_d3 Mux Selection Register - FLASHIO11
12093  *
12094  * This register is used to control the peripherals connected to sdmmc_d3
12095  *
12096  * Only reset by a cold reset (ignores warm reset).
12097  *
12098  * NOTE: These registers should not be modified after IO configuration.There is no
12099  * support for dynamically changing the Pin Mux selections.
12100  *
12101  * Register Layout
12102  *
12103  * Bits | Access | Reset | Description
12104  * :-------|:-------|:------|:-----------------------------
12105  * [1:0] | RW | 0x0 | sdmmc_d3 Mux Selection Field
12106  * [31:2] | ??? | 0x0 | *UNDEFINED*
12107  *
12108  */
12109 /*
12110  * Field : sdmmc_d3 Mux Selection Field - sel
12111  *
12112  * Select peripheral signals connected sdmmc_d3.
12113  *
12114  * 0 : Pin is connected to GPIO/LoanIO number 47.
12115  *
12116  * 1 : Pin is connected to Peripheral signal not applicable.
12117  *
12118  * 2 : Pin is connected to Peripheral signal USB0.NXT.
12119  *
12120  * 3 : Pin is connected to Peripheral signal SDMMC.D3.
12121  *
12122  * Field Access Macros:
12123  *
12124  */
12125 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12126 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0
12127 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12128 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1
12129 /* The width in bits of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12130 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2
12131 /* The mask used to set the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */
12132 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003
12133 /* The mask used to clear the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value. */
12134 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc
12135 /* The reset value of the ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field. */
12136 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0
12137 /* Extracts the ALT_SYSMGR_PINMUX_FLSHIO11_SEL field value from a register. */
12138 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
12139 /* Produces a ALT_SYSMGR_PINMUX_FLSHIO11_SEL register field value suitable for setting the register. */
12140 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
12141 
12142 #ifndef __ASSEMBLY__
12143 /*
12144  * WARNING: The C register and register group struct declarations are provided for
12145  * convenience and illustrative purposes. They should, however, be used with
12146  * caution as the C language standard provides no guarantees about the alignment or
12147  * atomicity of device memory accesses. The recommended practice for writing
12148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12149  * alt_write_word() functions.
12150  *
12151  * The struct declaration for register ALT_SYSMGR_PINMUX_FLSHIO11.
12152  */
12153 struct ALT_SYSMGR_PINMUX_FLSHIO11_s
12154 {
12155  uint32_t sel : 2; /* sdmmc_d3 Mux Selection Field */
12156  uint32_t : 30; /* *UNDEFINED* */
12157 };
12158 
12159 /* The typedef declaration for register ALT_SYSMGR_PINMUX_FLSHIO11. */
12160 typedef volatile struct ALT_SYSMGR_PINMUX_FLSHIO11_s ALT_SYSMGR_PINMUX_FLSHIO11_t;
12161 #endif /* __ASSEMBLY__ */
12162 
12163 /* The byte offset of the ALT_SYSMGR_PINMUX_FLSHIO11 register from the beginning of the component. */
12164 #define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c
12165 
12166 /*
12167  * Register : trace_clk Mux Selection Register - GENERALIO0
12168  *
12169  * This register is used to control the peripherals connected to trace_clk
12170  *
12171  * Only reset by a cold reset (ignores warm reset).
12172  *
12173  * NOTE: These registers should not be modified after IO configuration.There is no
12174  * support for dynamically changing the Pin Mux selections.
12175  *
12176  * Register Layout
12177  *
12178  * Bits | Access | Reset | Description
12179  * :-------|:-------|:------|:------------------------------
12180  * [1:0] | RW | 0x0 | trace_clk Mux Selection Field
12181  * [31:2] | ??? | 0x0 | *UNDEFINED*
12182  *
12183  */
12184 /*
12185  * Field : trace_clk Mux Selection Field - sel
12186  *
12187  * Select peripheral signals connected trace_clk.
12188  *
12189  * 0 : Pin is connected to GPIO/LoanIO number 48.
12190  *
12191  * 1 : Pin is connected to Peripheral signal not applicable.
12192  *
12193  * 2 : Pin is connected to Peripheral signal not applicable.
12194  *
12195  * 3 : Pin is connected to Peripheral signal TRACE.CLK.
12196  *
12197  * Field Access Macros:
12198  *
12199  */
12200 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12201 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0
12202 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12203 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1
12204 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12205 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2
12206 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */
12207 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003
12208 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value. */
12209 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc
12210 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field. */
12211 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0
12212 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO0_SEL field value from a register. */
12213 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
12214 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO0_SEL register field value suitable for setting the register. */
12215 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
12216 
12217 #ifndef __ASSEMBLY__
12218 /*
12219  * WARNING: The C register and register group struct declarations are provided for
12220  * convenience and illustrative purposes. They should, however, be used with
12221  * caution as the C language standard provides no guarantees about the alignment or
12222  * atomicity of device memory accesses. The recommended practice for writing
12223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12224  * alt_write_word() functions.
12225  *
12226  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO0.
12227  */
12228 struct ALT_SYSMGR_PINMUX_GENERALIO0_s
12229 {
12230  uint32_t sel : 2; /* trace_clk Mux Selection Field */
12231  uint32_t : 30; /* *UNDEFINED* */
12232 };
12233 
12234 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO0. */
12235 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO0_s ALT_SYSMGR_PINMUX_GENERALIO0_t;
12236 #endif /* __ASSEMBLY__ */
12237 
12238 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO0 register from the beginning of the component. */
12239 #define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80
12240 
12241 /*
12242  * Register : trace_d0 Mux Selection Register - GENERALIO1
12243  *
12244  * This register is used to control the peripherals connected to trace_d0
12245  *
12246  * Only reset by a cold reset (ignores warm reset).
12247  *
12248  * NOTE: These registers should not be modified after IO configuration.There is no
12249  * support for dynamically changing the Pin Mux selections.
12250  *
12251  * Register Layout
12252  *
12253  * Bits | Access | Reset | Description
12254  * :-------|:-------|:------|:-----------------------------
12255  * [1:0] | RW | 0x0 | trace_d0 Mux Selection Field
12256  * [31:2] | ??? | 0x0 | *UNDEFINED*
12257  *
12258  */
12259 /*
12260  * Field : trace_d0 Mux Selection Field - sel
12261  *
12262  * Select peripheral signals connected trace_d0.
12263  *
12264  * 0 : Pin is connected to GPIO/LoanIO number 49.
12265  *
12266  * 1 : Pin is connected to Peripheral signal UART0.RX.
12267  *
12268  * 2 : Pin is connected to Peripheral signal SPIS0.CLK.
12269  *
12270  * 3 : Pin is connected to Peripheral signal TRACE.D0.
12271  *
12272  * Field Access Macros:
12273  *
12274  */
12275 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12276 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0
12277 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12278 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1
12279 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12280 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2
12281 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */
12282 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003
12283 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value. */
12284 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc
12285 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field. */
12286 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0
12287 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO1_SEL field value from a register. */
12288 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
12289 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO1_SEL register field value suitable for setting the register. */
12290 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
12291 
12292 #ifndef __ASSEMBLY__
12293 /*
12294  * WARNING: The C register and register group struct declarations are provided for
12295  * convenience and illustrative purposes. They should, however, be used with
12296  * caution as the C language standard provides no guarantees about the alignment or
12297  * atomicity of device memory accesses. The recommended practice for writing
12298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12299  * alt_write_word() functions.
12300  *
12301  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO1.
12302  */
12303 struct ALT_SYSMGR_PINMUX_GENERALIO1_s
12304 {
12305  uint32_t sel : 2; /* trace_d0 Mux Selection Field */
12306  uint32_t : 30; /* *UNDEFINED* */
12307 };
12308 
12309 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO1. */
12310 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO1_s ALT_SYSMGR_PINMUX_GENERALIO1_t;
12311 #endif /* __ASSEMBLY__ */
12312 
12313 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO1 register from the beginning of the component. */
12314 #define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84
12315 
12316 /*
12317  * Register : trace_d1 Mux Selection Register - GENERALIO2
12318  *
12319  * This register is used to control the peripherals connected to trace_d1
12320  *
12321  * Only reset by a cold reset (ignores warm reset).
12322  *
12323  * NOTE: These registers should not be modified after IO configuration.There is no
12324  * support for dynamically changing the Pin Mux selections.
12325  *
12326  * Register Layout
12327  *
12328  * Bits | Access | Reset | Description
12329  * :-------|:-------|:------|:-----------------------------
12330  * [1:0] | RW | 0x0 | trace_d1 Mux Selection Field
12331  * [31:2] | ??? | 0x0 | *UNDEFINED*
12332  *
12333  */
12334 /*
12335  * Field : trace_d1 Mux Selection Field - sel
12336  *
12337  * Select peripheral signals connected trace_d1.
12338  *
12339  * 0 : Pin is connected to GPIO/LoanIO number 50.
12340  *
12341  * 1 : Pin is connected to Peripheral signal UART0.TX.
12342  *
12343  * 2 : Pin is connected to Peripheral signal SPIS0.MOSI.
12344  *
12345  * 3 : Pin is connected to Peripheral signal TRACE.D1.
12346  *
12347  * Field Access Macros:
12348  *
12349  */
12350 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12351 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0
12352 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12353 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1
12354 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12355 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2
12356 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */
12357 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003
12358 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value. */
12359 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc
12360 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field. */
12361 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0
12362 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO2_SEL field value from a register. */
12363 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
12364 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO2_SEL register field value suitable for setting the register. */
12365 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
12366 
12367 #ifndef __ASSEMBLY__
12368 /*
12369  * WARNING: The C register and register group struct declarations are provided for
12370  * convenience and illustrative purposes. They should, however, be used with
12371  * caution as the C language standard provides no guarantees about the alignment or
12372  * atomicity of device memory accesses. The recommended practice for writing
12373  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12374  * alt_write_word() functions.
12375  *
12376  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO2.
12377  */
12378 struct ALT_SYSMGR_PINMUX_GENERALIO2_s
12379 {
12380  uint32_t sel : 2; /* trace_d1 Mux Selection Field */
12381  uint32_t : 30; /* *UNDEFINED* */
12382 };
12383 
12384 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO2. */
12385 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO2_s ALT_SYSMGR_PINMUX_GENERALIO2_t;
12386 #endif /* __ASSEMBLY__ */
12387 
12388 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO2 register from the beginning of the component. */
12389 #define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88
12390 
12391 /*
12392  * Register : trace_d2 Mux Selection Register - GENERALIO3
12393  *
12394  * This register is used to control the peripherals connected to trace_d2
12395  *
12396  * Only reset by a cold reset (ignores warm reset).
12397  *
12398  * NOTE: These registers should not be modified after IO configuration.There is no
12399  * support for dynamically changing the Pin Mux selections.
12400  *
12401  * Register Layout
12402  *
12403  * Bits | Access | Reset | Description
12404  * :-------|:-------|:------|:-----------------------------
12405  * [1:0] | RW | 0x0 | trace_d2 Mux Selection Field
12406  * [31:2] | ??? | 0x0 | *UNDEFINED*
12407  *
12408  */
12409 /*
12410  * Field : trace_d2 Mux Selection Field - sel
12411  *
12412  * Select peripheral signals connected trace_d2.
12413  *
12414  * 0 : Pin is connected to GPIO/LoanIO number 51.
12415  *
12416  * 1 : Pin is connected to Peripheral signal I2C1.SDA.
12417  *
12418  * 2 : Pin is connected to Peripheral signal SPIS0.MISO.
12419  *
12420  * 3 : Pin is connected to Peripheral signal TRACE.D2.
12421  *
12422  * Field Access Macros:
12423  *
12424  */
12425 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12426 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0
12427 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12428 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1
12429 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12430 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2
12431 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */
12432 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003
12433 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value. */
12434 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc
12435 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field. */
12436 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0
12437 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO3_SEL field value from a register. */
12438 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
12439 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO3_SEL register field value suitable for setting the register. */
12440 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
12441 
12442 #ifndef __ASSEMBLY__
12443 /*
12444  * WARNING: The C register and register group struct declarations are provided for
12445  * convenience and illustrative purposes. They should, however, be used with
12446  * caution as the C language standard provides no guarantees about the alignment or
12447  * atomicity of device memory accesses. The recommended practice for writing
12448  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12449  * alt_write_word() functions.
12450  *
12451  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO3.
12452  */
12453 struct ALT_SYSMGR_PINMUX_GENERALIO3_s
12454 {
12455  uint32_t sel : 2; /* trace_d2 Mux Selection Field */
12456  uint32_t : 30; /* *UNDEFINED* */
12457 };
12458 
12459 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO3. */
12460 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO3_s ALT_SYSMGR_PINMUX_GENERALIO3_t;
12461 #endif /* __ASSEMBLY__ */
12462 
12463 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO3 register from the beginning of the component. */
12464 #define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c
12465 
12466 /*
12467  * Register : trace_d3 Mux Selection Register - GENERALIO4
12468  *
12469  * This register is used to control the peripherals connected to trace_d3
12470  *
12471  * Only reset by a cold reset (ignores warm reset).
12472  *
12473  * NOTE: These registers should not be modified after IO configuration.There is no
12474  * support for dynamically changing the Pin Mux selections.
12475  *
12476  * Register Layout
12477  *
12478  * Bits | Access | Reset | Description
12479  * :-------|:-------|:------|:-----------------------------
12480  * [1:0] | RW | 0x0 | trace_d3 Mux Selection Field
12481  * [31:2] | ??? | 0x0 | *UNDEFINED*
12482  *
12483  */
12484 /*
12485  * Field : trace_d3 Mux Selection Field - sel
12486  *
12487  * Select peripheral signals connected trace_d3.
12488  *
12489  * 0 : Pin is connected to GPIO/LoanIO number 52.
12490  *
12491  * 1 : Pin is connected to Peripheral signal I2C1.SCL.
12492  *
12493  * 2 : Pin is connected to Peripheral signal SPIS0.SS0.
12494  *
12495  * 3 : Pin is connected to Peripheral signal TRACE.D3.
12496  *
12497  * Field Access Macros:
12498  *
12499  */
12500 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12501 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0
12502 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12503 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1
12504 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12505 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2
12506 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */
12507 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003
12508 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value. */
12509 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc
12510 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field. */
12511 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0
12512 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO4_SEL field value from a register. */
12513 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
12514 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO4_SEL register field value suitable for setting the register. */
12515 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
12516 
12517 #ifndef __ASSEMBLY__
12518 /*
12519  * WARNING: The C register and register group struct declarations are provided for
12520  * convenience and illustrative purposes. They should, however, be used with
12521  * caution as the C language standard provides no guarantees about the alignment or
12522  * atomicity of device memory accesses. The recommended practice for writing
12523  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12524  * alt_write_word() functions.
12525  *
12526  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO4.
12527  */
12528 struct ALT_SYSMGR_PINMUX_GENERALIO4_s
12529 {
12530  uint32_t sel : 2; /* trace_d3 Mux Selection Field */
12531  uint32_t : 30; /* *UNDEFINED* */
12532 };
12533 
12534 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO4. */
12535 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO4_s ALT_SYSMGR_PINMUX_GENERALIO4_t;
12536 #endif /* __ASSEMBLY__ */
12537 
12538 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO4 register from the beginning of the component. */
12539 #define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90
12540 
12541 /*
12542  * Register : trace_d4 Mux Selection Register - GENERALIO5
12543  *
12544  * This register is used to control the peripherals connected to trace_d4
12545  *
12546  * Only reset by a cold reset (ignores warm reset).
12547  *
12548  * NOTE: These registers should not be modified after IO configuration.There is no
12549  * support for dynamically changing the Pin Mux selections.
12550  *
12551  * Register Layout
12552  *
12553  * Bits | Access | Reset | Description
12554  * :-------|:-------|:------|:-----------------------------
12555  * [1:0] | RW | 0x0 | trace_d4 Mux Selection Field
12556  * [31:2] | ??? | 0x0 | *UNDEFINED*
12557  *
12558  */
12559 /*
12560  * Field : trace_d4 Mux Selection Field - sel
12561  *
12562  * Select peripheral signals connected trace_d4.
12563  *
12564  * 0 : Pin is connected to GPIO/LoanIO number 53.
12565  *
12566  * 1 : Pin is connected to Peripheral signal CAN1.RX.
12567  *
12568  * 2 : Pin is connected to Peripheral signal SPIS1.CLK.
12569  *
12570  * 3 : Pin is connected to Peripheral signal TRACE.D4.
12571  *
12572  * Field Access Macros:
12573  *
12574  */
12575 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12576 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0
12577 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12578 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1
12579 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12580 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2
12581 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */
12582 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003
12583 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value. */
12584 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc
12585 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field. */
12586 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0
12587 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register. */
12588 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
12589 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register. */
12590 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
12591 
12592 #ifndef __ASSEMBLY__
12593 /*
12594  * WARNING: The C register and register group struct declarations are provided for
12595  * convenience and illustrative purposes. They should, however, be used with
12596  * caution as the C language standard provides no guarantees about the alignment or
12597  * atomicity of device memory accesses. The recommended practice for writing
12598  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12599  * alt_write_word() functions.
12600  *
12601  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5.
12602  */
12603 struct ALT_SYSMGR_PINMUX_GENERALIO5_s
12604 {
12605  uint32_t sel : 2; /* trace_d4 Mux Selection Field */
12606  uint32_t : 30; /* *UNDEFINED* */
12607 };
12608 
12609 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO5. */
12610 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO5_s ALT_SYSMGR_PINMUX_GENERALIO5_t;
12611 #endif /* __ASSEMBLY__ */
12612 
12613 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component. */
12614 #define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94
12615 
12616 /*
12617  * Register : trace_d5 Mux Selection Register - GENERALIO6
12618  *
12619  * This register is used to control the peripherals connected to trace_d5
12620  *
12621  * Only reset by a cold reset (ignores warm reset).
12622  *
12623  * NOTE: These registers should not be modified after IO configuration.There is no
12624  * support for dynamically changing the Pin Mux selections.
12625  *
12626  * Register Layout
12627  *
12628  * Bits | Access | Reset | Description
12629  * :-------|:-------|:------|:-----------------------------
12630  * [1:0] | RW | 0x0 | trace_d5 Mux Selection Field
12631  * [31:2] | ??? | 0x0 | *UNDEFINED*
12632  *
12633  */
12634 /*
12635  * Field : trace_d5 Mux Selection Field - sel
12636  *
12637  * Select peripheral signals connected trace_d5.
12638  *
12639  * 0 : Pin is connected to GPIO/LoanIO number 54.
12640  *
12641  * 1 : Pin is connected to Peripheral signal CAN1.TX.
12642  *
12643  * 2 : Pin is connected to Peripheral signal SPIS1.MOSI.
12644  *
12645  * 3 : Pin is connected to Peripheral signal TRACE.D5.
12646  *
12647  * Field Access Macros:
12648  *
12649  */
12650 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12651 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0
12652 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12653 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1
12654 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12655 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2
12656 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */
12657 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003
12658 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value. */
12659 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc
12660 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field. */
12661 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0
12662 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO6_SEL field value from a register. */
12663 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
12664 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO6_SEL register field value suitable for setting the register. */
12665 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
12666 
12667 #ifndef __ASSEMBLY__
12668 /*
12669  * WARNING: The C register and register group struct declarations are provided for
12670  * convenience and illustrative purposes. They should, however, be used with
12671  * caution as the C language standard provides no guarantees about the alignment or
12672  * atomicity of device memory accesses. The recommended practice for writing
12673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12674  * alt_write_word() functions.
12675  *
12676  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO6.
12677  */
12678 struct ALT_SYSMGR_PINMUX_GENERALIO6_s
12679 {
12680  uint32_t sel : 2; /* trace_d5 Mux Selection Field */
12681  uint32_t : 30; /* *UNDEFINED* */
12682 };
12683 
12684 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO6. */
12685 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO6_s ALT_SYSMGR_PINMUX_GENERALIO6_t;
12686 #endif /* __ASSEMBLY__ */
12687 
12688 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO6 register from the beginning of the component. */
12689 #define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98
12690 
12691 /*
12692  * Register : trace_d6 Mux Selection Register - GENERALIO7
12693  *
12694  * This register is used to control the peripherals connected to trace_d6
12695  *
12696  * Only reset by a cold reset (ignores warm reset).
12697  *
12698  * NOTE: These registers should not be modified after IO configuration.There is no
12699  * support for dynamically changing the Pin Mux selections.
12700  *
12701  * Register Layout
12702  *
12703  * Bits | Access | Reset | Description
12704  * :-------|:-------|:------|:-----------------------------
12705  * [1:0] | RW | 0x0 | trace_d6 Mux Selection Field
12706  * [31:2] | ??? | 0x0 | *UNDEFINED*
12707  *
12708  */
12709 /*
12710  * Field : trace_d6 Mux Selection Field - sel
12711  *
12712  * Select peripheral signals connected trace_d6.
12713  *
12714  * 0 : Pin is connected to GPIO/LoanIO number 55.
12715  *
12716  * 1 : Pin is connected to Peripheral signal I2C0.SDA.
12717  *
12718  * 2 : Pin is connected to Peripheral signal SPIS1.SS0.
12719  *
12720  * 3 : Pin is connected to Peripheral signal TRACE.D6.
12721  *
12722  * Field Access Macros:
12723  *
12724  */
12725 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12726 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0
12727 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12728 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1
12729 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12730 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2
12731 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */
12732 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003
12733 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value. */
12734 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc
12735 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field. */
12736 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0
12737 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO7_SEL field value from a register. */
12738 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
12739 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO7_SEL register field value suitable for setting the register. */
12740 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
12741 
12742 #ifndef __ASSEMBLY__
12743 /*
12744  * WARNING: The C register and register group struct declarations are provided for
12745  * convenience and illustrative purposes. They should, however, be used with
12746  * caution as the C language standard provides no guarantees about the alignment or
12747  * atomicity of device memory accesses. The recommended practice for writing
12748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12749  * alt_write_word() functions.
12750  *
12751  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO7.
12752  */
12753 struct ALT_SYSMGR_PINMUX_GENERALIO7_s
12754 {
12755  uint32_t sel : 2; /* trace_d6 Mux Selection Field */
12756  uint32_t : 30; /* *UNDEFINED* */
12757 };
12758 
12759 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO7. */
12760 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO7_s ALT_SYSMGR_PINMUX_GENERALIO7_t;
12761 #endif /* __ASSEMBLY__ */
12762 
12763 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO7 register from the beginning of the component. */
12764 #define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c
12765 
12766 /*
12767  * Register : trace_d7 Mux Selection Register - GENERALIO8
12768  *
12769  * This register is used to control the peripherals connected to trace_d7
12770  *
12771  * Only reset by a cold reset (ignores warm reset).
12772  *
12773  * NOTE: These registers should not be modified after IO configuration.There is no
12774  * support for dynamically changing the Pin Mux selections.
12775  *
12776  * Register Layout
12777  *
12778  * Bits | Access | Reset | Description
12779  * :-------|:-------|:------|:-----------------------------
12780  * [1:0] | RW | 0x0 | trace_d7 Mux Selection Field
12781  * [31:2] | ??? | 0x0 | *UNDEFINED*
12782  *
12783  */
12784 /*
12785  * Field : trace_d7 Mux Selection Field - sel
12786  *
12787  * Select peripheral signals connected trace_d7.
12788  *
12789  * 0 : Pin is connected to GPIO/LoanIO number 56.
12790  *
12791  * 1 : Pin is connected to Peripheral signal I2C0.SCL.
12792  *
12793  * 2 : Pin is connected to Peripheral signal SPIS1.MISO.
12794  *
12795  * 3 : Pin is connected to Peripheral signal TRACE.D7.
12796  *
12797  * Field Access Macros:
12798  *
12799  */
12800 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12801 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0
12802 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12803 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1
12804 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12805 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2
12806 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */
12807 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003
12808 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value. */
12809 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc
12810 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field. */
12811 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0
12812 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO8_SEL field value from a register. */
12813 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
12814 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO8_SEL register field value suitable for setting the register. */
12815 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
12816 
12817 #ifndef __ASSEMBLY__
12818 /*
12819  * WARNING: The C register and register group struct declarations are provided for
12820  * convenience and illustrative purposes. They should, however, be used with
12821  * caution as the C language standard provides no guarantees about the alignment or
12822  * atomicity of device memory accesses. The recommended practice for writing
12823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12824  * alt_write_word() functions.
12825  *
12826  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO8.
12827  */
12828 struct ALT_SYSMGR_PINMUX_GENERALIO8_s
12829 {
12830  uint32_t sel : 2; /* trace_d7 Mux Selection Field */
12831  uint32_t : 30; /* *UNDEFINED* */
12832 };
12833 
12834 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO8. */
12835 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO8_s ALT_SYSMGR_PINMUX_GENERALIO8_t;
12836 #endif /* __ASSEMBLY__ */
12837 
12838 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO8 register from the beginning of the component. */
12839 #define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0
12840 
12841 /*
12842  * Register : spim0_clk Mux Selection Register - GENERALIO9
12843  *
12844  * This register is used to control the peripherals connected to spim0_clk
12845  *
12846  * Only reset by a cold reset (ignores warm reset).
12847  *
12848  * NOTE: These registers should not be modified after IO configuration.There is no
12849  * support for dynamically changing the Pin Mux selections.
12850  *
12851  * Register Layout
12852  *
12853  * Bits | Access | Reset | Description
12854  * :-------|:-------|:------|:------------------------------
12855  * [1:0] | RW | 0x0 | spim0_clk Mux Selection Field
12856  * [31:2] | ??? | 0x0 | *UNDEFINED*
12857  *
12858  */
12859 /*
12860  * Field : spim0_clk Mux Selection Field - sel
12861  *
12862  * Select peripheral signals connected spim0_clk.
12863  *
12864  * 0 : Pin is connected to GPIO/LoanIO number 57.
12865  *
12866  * 1 : Pin is connected to Peripheral signal UART0.CTS.
12867  *
12868  * 2 : Pin is connected to Peripheral signal I2C1.SDA.
12869  *
12870  * 3 : Pin is connected to Peripheral signal SPIM0.CLK.
12871  *
12872  * Field Access Macros:
12873  *
12874  */
12875 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12876 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0
12877 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12878 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1
12879 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12880 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2
12881 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */
12882 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003
12883 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value. */
12884 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc
12885 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field. */
12886 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0
12887 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO9_SEL field value from a register. */
12888 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
12889 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO9_SEL register field value suitable for setting the register. */
12890 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
12891 
12892 #ifndef __ASSEMBLY__
12893 /*
12894  * WARNING: The C register and register group struct declarations are provided for
12895  * convenience and illustrative purposes. They should, however, be used with
12896  * caution as the C language standard provides no guarantees about the alignment or
12897  * atomicity of device memory accesses. The recommended practice for writing
12898  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12899  * alt_write_word() functions.
12900  *
12901  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO9.
12902  */
12903 struct ALT_SYSMGR_PINMUX_GENERALIO9_s
12904 {
12905  uint32_t sel : 2; /* spim0_clk Mux Selection Field */
12906  uint32_t : 30; /* *UNDEFINED* */
12907 };
12908 
12909 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO9. */
12910 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO9_s ALT_SYSMGR_PINMUX_GENERALIO9_t;
12911 #endif /* __ASSEMBLY__ */
12912 
12913 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO9 register from the beginning of the component. */
12914 #define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4
12915 
12916 /*
12917  * Register : spim0_mosi Mux Selection Register - GENERALIO10
12918  *
12919  * This register is used to control the peripherals connected to spim0_mosi
12920  *
12921  * Only reset by a cold reset (ignores warm reset).
12922  *
12923  * NOTE: These registers should not be modified after IO configuration.There is no
12924  * support for dynamically changing the Pin Mux selections.
12925  *
12926  * Register Layout
12927  *
12928  * Bits | Access | Reset | Description
12929  * :-------|:-------|:------|:-------------------------------
12930  * [1:0] | RW | 0x0 | spim0_mosi Mux Selection Field
12931  * [31:2] | ??? | 0x0 | *UNDEFINED*
12932  *
12933  */
12934 /*
12935  * Field : spim0_mosi Mux Selection Field - sel
12936  *
12937  * Select peripheral signals connected spim0_mosi.
12938  *
12939  * 0 : Pin is connected to GPIO/LoanIO number 58.
12940  *
12941  * 1 : Pin is connected to Peripheral signal UART0.RTS.
12942  *
12943  * 2 : Pin is connected to Peripheral signal I2C1.SCL.
12944  *
12945  * 3 : Pin is connected to Peripheral signal SPIM0.MOSI.
12946  *
12947  * Field Access Macros:
12948  *
12949  */
12950 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12951 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0
12952 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12953 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1
12954 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12955 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2
12956 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */
12957 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003
12958 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value. */
12959 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc
12960 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field. */
12961 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0
12962 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO10_SEL field value from a register. */
12963 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12964 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO10_SEL register field value suitable for setting the register. */
12965 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12966 
12967 #ifndef __ASSEMBLY__
12968 /*
12969  * WARNING: The C register and register group struct declarations are provided for
12970  * convenience and illustrative purposes. They should, however, be used with
12971  * caution as the C language standard provides no guarantees about the alignment or
12972  * atomicity of device memory accesses. The recommended practice for writing
12973  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
12974  * alt_write_word() functions.
12975  *
12976  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO10.
12977  */
12978 struct ALT_SYSMGR_PINMUX_GENERALIO10_s
12979 {
12980  uint32_t sel : 2; /* spim0_mosi Mux Selection Field */
12981  uint32_t : 30; /* *UNDEFINED* */
12982 };
12983 
12984 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO10. */
12985 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO10_s ALT_SYSMGR_PINMUX_GENERALIO10_t;
12986 #endif /* __ASSEMBLY__ */
12987 
12988 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO10 register from the beginning of the component. */
12989 #define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8
12990 
12991 /*
12992  * Register : spim0_miso Mux Selection Register - GENERALIO11
12993  *
12994  * This register is used to control the peripherals connected to spim0_miso
12995  *
12996  * Only reset by a cold reset (ignores warm reset).
12997  *
12998  * NOTE: These registers should not be modified after IO configuration.There is no
12999  * support for dynamically changing the Pin Mux selections.
13000  *
13001  * Register Layout
13002  *
13003  * Bits | Access | Reset | Description
13004  * :-------|:-------|:------|:-------------------------------
13005  * [1:0] | RW | 0x0 | spim0_miso Mux Selection Field
13006  * [31:2] | ??? | 0x0 | *UNDEFINED*
13007  *
13008  */
13009 /*
13010  * Field : spim0_miso Mux Selection Field - sel
13011  *
13012  * Select peripheral signals connected spim0_miso.
13013  *
13014  * 0 : Pin is connected to GPIO/LoanIO number 59.
13015  *
13016  * 1 : Pin is connected to Peripheral signal UART1.CTS.
13017  *
13018  * 2 : Pin is connected to Peripheral signal CAN1.RX.
13019  *
13020  * 3 : Pin is connected to Peripheral signal SPIM0.MISO.
13021  *
13022  * Field Access Macros:
13023  *
13024  */
13025 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13026 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0
13027 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13028 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1
13029 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13030 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2
13031 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */
13032 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003
13033 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value. */
13034 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc
13035 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field. */
13036 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0
13037 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO11_SEL field value from a register. */
13038 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
13039 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO11_SEL register field value suitable for setting the register. */
13040 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
13041 
13042 #ifndef __ASSEMBLY__
13043 /*
13044  * WARNING: The C register and register group struct declarations are provided for
13045  * convenience and illustrative purposes. They should, however, be used with
13046  * caution as the C language standard provides no guarantees about the alignment or
13047  * atomicity of device memory accesses. The recommended practice for writing
13048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13049  * alt_write_word() functions.
13050  *
13051  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO11.
13052  */
13053 struct ALT_SYSMGR_PINMUX_GENERALIO11_s
13054 {
13055  uint32_t sel : 2; /* spim0_miso Mux Selection Field */
13056  uint32_t : 30; /* *UNDEFINED* */
13057 };
13058 
13059 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO11. */
13060 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO11_s ALT_SYSMGR_PINMUX_GENERALIO11_t;
13061 #endif /* __ASSEMBLY__ */
13062 
13063 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO11 register from the beginning of the component. */
13064 #define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac
13065 
13066 /*
13067  * Register : spim0_ss0 Mux Selection Register - GENERALIO12
13068  *
13069  * This register is used to control the peripherals connected to spim0_ss0
13070  *
13071  * Only reset by a cold reset (ignores warm reset).
13072  *
13073  * NOTE: These registers should not be modified after IO configuration.There is no
13074  * support for dynamically changing the Pin Mux selections.
13075  *
13076  * Register Layout
13077  *
13078  * Bits | Access | Reset | Description
13079  * :-------|:-------|:------|:------------------------------
13080  * [1:0] | RW | 0x0 | spim0_ss0 Mux Selection Field
13081  * [31:2] | ??? | 0x0 | *UNDEFINED*
13082  *
13083  */
13084 /*
13085  * Field : spim0_ss0 Mux Selection Field - sel
13086  *
13087  * Select peripheral signals connected spim0_ss0.
13088  *
13089  * 0 : Pin is connected to GPIO/LoanIO number 60.
13090  *
13091  * 1 : Pin is connected to Peripheral signal UART1.RTS.
13092  *
13093  * 2 : Pin is connected to Peripheral signal CAN1.TX.
13094  *
13095  * 3 : Pin is connected to Peripheral signal SPIM0.SS0.
13096  *
13097  * Field Access Macros:
13098  *
13099  */
13100 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13101 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0
13102 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13103 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1
13104 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13105 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2
13106 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */
13107 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003
13108 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value. */
13109 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc
13110 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field. */
13111 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0
13112 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO12_SEL field value from a register. */
13113 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
13114 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO12_SEL register field value suitable for setting the register. */
13115 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
13116 
13117 #ifndef __ASSEMBLY__
13118 /*
13119  * WARNING: The C register and register group struct declarations are provided for
13120  * convenience and illustrative purposes. They should, however, be used with
13121  * caution as the C language standard provides no guarantees about the alignment or
13122  * atomicity of device memory accesses. The recommended practice for writing
13123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13124  * alt_write_word() functions.
13125  *
13126  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO12.
13127  */
13128 struct ALT_SYSMGR_PINMUX_GENERALIO12_s
13129 {
13130  uint32_t sel : 2; /* spim0_ss0 Mux Selection Field */
13131  uint32_t : 30; /* *UNDEFINED* */
13132 };
13133 
13134 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO12. */
13135 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO12_s ALT_SYSMGR_PINMUX_GENERALIO12_t;
13136 #endif /* __ASSEMBLY__ */
13137 
13138 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO12 register from the beginning of the component. */
13139 #define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0
13140 
13141 /*
13142  * Register : uart0_rx Mux Selection Register - GENERALIO13
13143  *
13144  * This register is used to control the peripherals connected to uart0_rx
13145  *
13146  * Only reset by a cold reset (ignores warm reset).
13147  *
13148  * NOTE: These registers should not be modified after IO configuration.There is no
13149  * support for dynamically changing the Pin Mux selections.
13150  *
13151  * Register Layout
13152  *
13153  * Bits | Access | Reset | Description
13154  * :-------|:-------|:------|:-----------------------------
13155  * [1:0] | RW | 0x0 | uart0_rx Mux Selection Field
13156  * [31:2] | ??? | 0x0 | *UNDEFINED*
13157  *
13158  */
13159 /*
13160  * Field : uart0_rx Mux Selection Field - sel
13161  *
13162  * Select peripheral signals connected uart0_rx.
13163  *
13164  * 0 : Pin is connected to GPIO/LoanIO number 61.
13165  *
13166  * 1 : Pin is connected to Peripheral signal SPIM0.SS1.
13167  *
13168  * 2 : Pin is connected to Peripheral signal CAN0.RX.
13169  *
13170  * 3 : Pin is connected to Peripheral signal UART0.RX.
13171  *
13172  * Field Access Macros:
13173  *
13174  */
13175 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13176 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0
13177 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13178 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1
13179 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13180 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2
13181 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */
13182 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003
13183 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value. */
13184 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc
13185 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field. */
13186 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0
13187 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO13_SEL field value from a register. */
13188 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
13189 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO13_SEL register field value suitable for setting the register. */
13190 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
13191 
13192 #ifndef __ASSEMBLY__
13193 /*
13194  * WARNING: The C register and register group struct declarations are provided for
13195  * convenience and illustrative purposes. They should, however, be used with
13196  * caution as the C language standard provides no guarantees about the alignment or
13197  * atomicity of device memory accesses. The recommended practice for writing
13198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13199  * alt_write_word() functions.
13200  *
13201  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO13.
13202  */
13203 struct ALT_SYSMGR_PINMUX_GENERALIO13_s
13204 {
13205  uint32_t sel : 2; /* uart0_rx Mux Selection Field */
13206  uint32_t : 30; /* *UNDEFINED* */
13207 };
13208 
13209 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO13. */
13210 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO13_s ALT_SYSMGR_PINMUX_GENERALIO13_t;
13211 #endif /* __ASSEMBLY__ */
13212 
13213 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO13 register from the beginning of the component. */
13214 #define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4
13215 
13216 /*
13217  * Register : uart0_tx Mux Selection Register - GENERALIO14
13218  *
13219  * This register is used to control the peripherals connected to uart0_tx
13220  *
13221  * Only reset by a cold reset (ignores warm reset).
13222  *
13223  * NOTE: These registers should not be modified after IO configuration.There is no
13224  * support for dynamically changing the Pin Mux selections.
13225  *
13226  * Register Layout
13227  *
13228  * Bits | Access | Reset | Description
13229  * :-------|:-------|:------|:-----------------------------
13230  * [1:0] | RW | 0x0 | uart0_tx Mux Selection Field
13231  * [31:2] | ??? | 0x0 | *UNDEFINED*
13232  *
13233  */
13234 /*
13235  * Field : uart0_tx Mux Selection Field - sel
13236  *
13237  * Select peripheral signals connected uart0_tx.
13238  *
13239  * 0 : Pin is connected to GPIO/LoanIO number 62.
13240  *
13241  * 1 : Pin is connected to Peripheral signal SPIM1.SS1.
13242  *
13243  * 2 : Pin is connected to Peripheral signal CAN0.TX.
13244  *
13245  * 3 : Pin is connected to Peripheral signal UART0.TX.
13246  *
13247  * Field Access Macros:
13248  *
13249  */
13250 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13251 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0
13252 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13253 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1
13254 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13255 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2
13256 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */
13257 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003
13258 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value. */
13259 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc
13260 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field. */
13261 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0
13262 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO14_SEL field value from a register. */
13263 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
13264 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO14_SEL register field value suitable for setting the register. */
13265 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
13266 
13267 #ifndef __ASSEMBLY__
13268 /*
13269  * WARNING: The C register and register group struct declarations are provided for
13270  * convenience and illustrative purposes. They should, however, be used with
13271  * caution as the C language standard provides no guarantees about the alignment or
13272  * atomicity of device memory accesses. The recommended practice for writing
13273  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13274  * alt_write_word() functions.
13275  *
13276  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO14.
13277  */
13278 struct ALT_SYSMGR_PINMUX_GENERALIO14_s
13279 {
13280  uint32_t sel : 2; /* uart0_tx Mux Selection Field */
13281  uint32_t : 30; /* *UNDEFINED* */
13282 };
13283 
13284 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO14. */
13285 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO14_s ALT_SYSMGR_PINMUX_GENERALIO14_t;
13286 #endif /* __ASSEMBLY__ */
13287 
13288 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO14 register from the beginning of the component. */
13289 #define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8
13290 
13291 /*
13292  * Register : i2c0_sda Mux Selection Register - GENERALIO15
13293  *
13294  * This register is used to control the peripherals connected to i2c0_sda
13295  *
13296  * Only reset by a cold reset (ignores warm reset).
13297  *
13298  * NOTE: These registers should not be modified after IO configuration.There is no
13299  * support for dynamically changing the Pin Mux selections.
13300  *
13301  * Register Layout
13302  *
13303  * Bits | Access | Reset | Description
13304  * :-------|:-------|:------|:-----------------------------
13305  * [1:0] | RW | 0x0 | i2c0_sda Mux Selection Field
13306  * [31:2] | ??? | 0x0 | *UNDEFINED*
13307  *
13308  */
13309 /*
13310  * Field : i2c0_sda Mux Selection Field - sel
13311  *
13312  * Select peripheral signals connected i2c0_sda.
13313  *
13314  * 0 : Pin is connected to GPIO/LoanIO number 63.
13315  *
13316  * 1 : Pin is connected to Peripheral signal SPIM1.CLK.
13317  *
13318  * 2 : Pin is connected to Peripheral signal UART1.RX.
13319  *
13320  * 3 : Pin is connected to Peripheral signal I2C0.SDA.
13321  *
13322  * Field Access Macros:
13323  *
13324  */
13325 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13326 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0
13327 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13328 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1
13329 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13330 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2
13331 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */
13332 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003
13333 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value. */
13334 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc
13335 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field. */
13336 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0
13337 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO15_SEL field value from a register. */
13338 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
13339 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO15_SEL register field value suitable for setting the register. */
13340 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
13341 
13342 #ifndef __ASSEMBLY__
13343 /*
13344  * WARNING: The C register and register group struct declarations are provided for
13345  * convenience and illustrative purposes. They should, however, be used with
13346  * caution as the C language standard provides no guarantees about the alignment or
13347  * atomicity of device memory accesses. The recommended practice for writing
13348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13349  * alt_write_word() functions.
13350  *
13351  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO15.
13352  */
13353 struct ALT_SYSMGR_PINMUX_GENERALIO15_s
13354 {
13355  uint32_t sel : 2; /* i2c0_sda Mux Selection Field */
13356  uint32_t : 30; /* *UNDEFINED* */
13357 };
13358 
13359 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO15. */
13360 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO15_s ALT_SYSMGR_PINMUX_GENERALIO15_t;
13361 #endif /* __ASSEMBLY__ */
13362 
13363 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO15 register from the beginning of the component. */
13364 #define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc
13365 
13366 /*
13367  * Register : i2c0_scl Mux Selection Register - GENERALIO16
13368  *
13369  * This register is used to control the peripherals connected to i2c0_scl
13370  *
13371  * Only reset by a cold reset (ignores warm reset).
13372  *
13373  * NOTE: These registers should not be modified after IO configuration.There is no
13374  * support for dynamically changing the Pin Mux selections.
13375  *
13376  * Register Layout
13377  *
13378  * Bits | Access | Reset | Description
13379  * :-------|:-------|:------|:-----------------------------
13380  * [1:0] | RW | 0x0 | i2c0_scl Mux Selection Field
13381  * [31:2] | ??? | 0x0 | *UNDEFINED*
13382  *
13383  */
13384 /*
13385  * Field : i2c0_scl Mux Selection Field - sel
13386  *
13387  * Select peripheral signals connected i2c0_scl.
13388  *
13389  * 0 : Pin is connected to GPIO/LoanIO number 64.
13390  *
13391  * 1 : Pin is connected to Peripheral signal SPIM1.MOSI.
13392  *
13393  * 2 : Pin is connected to Peripheral signal UART1.TX.
13394  *
13395  * 3 : Pin is connected to Peripheral signal I2C0.SCL.
13396  *
13397  * Field Access Macros:
13398  *
13399  */
13400 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13401 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0
13402 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13403 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1
13404 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13405 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2
13406 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */
13407 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003
13408 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value. */
13409 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc
13410 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field. */
13411 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0
13412 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO16_SEL field value from a register. */
13413 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
13414 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO16_SEL register field value suitable for setting the register. */
13415 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
13416 
13417 #ifndef __ASSEMBLY__
13418 /*
13419  * WARNING: The C register and register group struct declarations are provided for
13420  * convenience and illustrative purposes. They should, however, be used with
13421  * caution as the C language standard provides no guarantees about the alignment or
13422  * atomicity of device memory accesses. The recommended practice for writing
13423  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13424  * alt_write_word() functions.
13425  *
13426  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO16.
13427  */
13428 struct ALT_SYSMGR_PINMUX_GENERALIO16_s
13429 {
13430  uint32_t sel : 2; /* i2c0_scl Mux Selection Field */
13431  uint32_t : 30; /* *UNDEFINED* */
13432 };
13433 
13434 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO16. */
13435 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO16_s ALT_SYSMGR_PINMUX_GENERALIO16_t;
13436 #endif /* __ASSEMBLY__ */
13437 
13438 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO16 register from the beginning of the component. */
13439 #define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0
13440 
13441 /*
13442  * Register : can0_rx Mux Selection Register - GENERALIO17
13443  *
13444  * This register is used to control the peripherals connected to can0_rx
13445  *
13446  * Only reset by a cold reset (ignores warm reset).
13447  *
13448  * NOTE: These registers should not be modified after IO configuration.There is no
13449  * support for dynamically changing the Pin Mux selections.
13450  *
13451  * Register Layout
13452  *
13453  * Bits | Access | Reset | Description
13454  * :-------|:-------|:------|:----------------------------
13455  * [1:0] | RW | 0x0 | can0_rx Mux Selection Field
13456  * [31:2] | ??? | 0x0 | *UNDEFINED*
13457  *
13458  */
13459 /*
13460  * Field : can0_rx Mux Selection Field - sel
13461  *
13462  * Select peripheral signals connected can0_rx.
13463  *
13464  * 0 : Pin is connected to GPIO/LoanIO number 65.
13465  *
13466  * 1 : Pin is connected to Peripheral signal SPIM1.MISO.
13467  *
13468  * 2 : Pin is connected to Peripheral signal UART0.RX.
13469  *
13470  * 3 : Pin is connected to Peripheral signal CAN0.RX.
13471  *
13472  * Field Access Macros:
13473  *
13474  */
13475 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13476 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0
13477 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13478 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1
13479 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13480 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2
13481 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */
13482 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003
13483 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value. */
13484 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc
13485 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field. */
13486 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0
13487 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO17_SEL field value from a register. */
13488 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
13489 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO17_SEL register field value suitable for setting the register. */
13490 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
13491 
13492 #ifndef __ASSEMBLY__
13493 /*
13494  * WARNING: The C register and register group struct declarations are provided for
13495  * convenience and illustrative purposes. They should, however, be used with
13496  * caution as the C language standard provides no guarantees about the alignment or
13497  * atomicity of device memory accesses. The recommended practice for writing
13498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13499  * alt_write_word() functions.
13500  *
13501  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO17.
13502  */
13503 struct ALT_SYSMGR_PINMUX_GENERALIO17_s
13504 {
13505  uint32_t sel : 2; /* can0_rx Mux Selection Field */
13506  uint32_t : 30; /* *UNDEFINED* */
13507 };
13508 
13509 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO17. */
13510 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO17_s ALT_SYSMGR_PINMUX_GENERALIO17_t;
13511 #endif /* __ASSEMBLY__ */
13512 
13513 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO17 register from the beginning of the component. */
13514 #define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4
13515 
13516 /*
13517  * Register : can0_tx Mux Selection Register - GENERALIO18
13518  *
13519  * This register is used to control the peripherals connected to can0_tx
13520  *
13521  * Only reset by a cold reset (ignores warm reset).
13522  *
13523  * NOTE: These registers should not be modified after IO configuration.There is no
13524  * support for dynamically changing the Pin Mux selections.
13525  *
13526  * Register Layout
13527  *
13528  * Bits | Access | Reset | Description
13529  * :-------|:-------|:------|:----------------------------
13530  * [1:0] | RW | 0x0 | can0_tx Mux Selection Field
13531  * [31:2] | ??? | 0x0 | *UNDEFINED*
13532  *
13533  */
13534 /*
13535  * Field : can0_tx Mux Selection Field - sel
13536  *
13537  * Select peripheral signals connected can0_tx.
13538  *
13539  * 0 : Pin is connected to GPIO/LoanIO number 66.
13540  *
13541  * 1 : Pin is connected to Peripheral signal SPIM1.SS0.
13542  *
13543  * 2 : Pin is connected to Peripheral signal UART0.TX.
13544  *
13545  * 3 : Pin is connected to Peripheral signal CAN0.TX.
13546  *
13547  * Field Access Macros:
13548  *
13549  */
13550 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13551 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0
13552 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13553 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1
13554 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13555 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2
13556 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */
13557 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003
13558 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value. */
13559 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc
13560 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field. */
13561 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0
13562 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO18_SEL field value from a register. */
13563 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
13564 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO18_SEL register field value suitable for setting the register. */
13565 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
13566 
13567 #ifndef __ASSEMBLY__
13568 /*
13569  * WARNING: The C register and register group struct declarations are provided for
13570  * convenience and illustrative purposes. They should, however, be used with
13571  * caution as the C language standard provides no guarantees about the alignment or
13572  * atomicity of device memory accesses. The recommended practice for writing
13573  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13574  * alt_write_word() functions.
13575  *
13576  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO18.
13577  */
13578 struct ALT_SYSMGR_PINMUX_GENERALIO18_s
13579 {
13580  uint32_t sel : 2; /* can0_tx Mux Selection Field */
13581  uint32_t : 30; /* *UNDEFINED* */
13582 };
13583 
13584 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO18. */
13585 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO18_s ALT_SYSMGR_PINMUX_GENERALIO18_t;
13586 #endif /* __ASSEMBLY__ */
13587 
13588 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO18 register from the beginning of the component. */
13589 #define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8
13590 
13591 /*
13592  * Register : spis1_clk Mux Selection Register - GENERALIO19
13593  *
13594  * This register is used to control the peripherals connected to spis1_clk
13595  *
13596  * Only reset by a cold reset (ignores warm reset).
13597  *
13598  * NOTE: These registers should not be modified after IO configuration.There is no
13599  * support for dynamically changing the Pin Mux selections.
13600  *
13601  * Register Layout
13602  *
13603  * Bits | Access | Reset | Description
13604  * :-------|:-------|:------|:------------------------------
13605  * [1:0] | RW | 0x0 | spis1_clk Mux Selection Field
13606  * [31:2] | ??? | 0x0 | *UNDEFINED*
13607  *
13608  */
13609 /*
13610  * Field : spis1_clk Mux Selection Field - sel
13611  *
13612  * Select peripheral signals connected spis1_clk.
13613  *
13614  * 0 : Pin is connected to GPIO/LoanIO number 67.
13615  *
13616  * 1 : Pin is connected to Peripheral signal not applicable.
13617  *
13618  * 2 : Pin is connected to Peripheral signal SPIM1.CLK.
13619  *
13620  * 3 : Pin is connected to Peripheral signal SPIS1.CLK.
13621  *
13622  * Field Access Macros:
13623  *
13624  */
13625 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13626 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0
13627 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13628 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1
13629 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13630 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2
13631 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */
13632 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003
13633 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value. */
13634 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc
13635 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field. */
13636 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0
13637 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO19_SEL field value from a register. */
13638 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
13639 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO19_SEL register field value suitable for setting the register. */
13640 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
13641 
13642 #ifndef __ASSEMBLY__
13643 /*
13644  * WARNING: The C register and register group struct declarations are provided for
13645  * convenience and illustrative purposes. They should, however, be used with
13646  * caution as the C language standard provides no guarantees about the alignment or
13647  * atomicity of device memory accesses. The recommended practice for writing
13648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13649  * alt_write_word() functions.
13650  *
13651  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO19.
13652  */
13653 struct ALT_SYSMGR_PINMUX_GENERALIO19_s
13654 {
13655  uint32_t sel : 2; /* spis1_clk Mux Selection Field */
13656  uint32_t : 30; /* *UNDEFINED* */
13657 };
13658 
13659 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO19. */
13660 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO19_s ALT_SYSMGR_PINMUX_GENERALIO19_t;
13661 #endif /* __ASSEMBLY__ */
13662 
13663 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO19 register from the beginning of the component. */
13664 #define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc
13665 
13666 /*
13667  * Register : spis1_mosi Mux Selection Register - GENERALIO20
13668  *
13669  * This register is used to control the peripherals connected to spis1_mosi
13670  *
13671  * Only reset by a cold reset (ignores warm reset).
13672  *
13673  * NOTE: These registers should not be modified after IO configuration.There is no
13674  * support for dynamically changing the Pin Mux selections.
13675  *
13676  * Register Layout
13677  *
13678  * Bits | Access | Reset | Description
13679  * :-------|:-------|:------|:-------------------------------
13680  * [1:0] | RW | 0x0 | spis1_mosi Mux Selection Field
13681  * [31:2] | ??? | 0x0 | *UNDEFINED*
13682  *
13683  */
13684 /*
13685  * Field : spis1_mosi Mux Selection Field - sel
13686  *
13687  * Select peripheral signals connected spis1_mosi.
13688  *
13689  * 0 : Pin is connected to GPIO/LoanIO number 68.
13690  *
13691  * 1 : Pin is connected to Peripheral signal not applicable.
13692  *
13693  * 2 : Pin is connected to Peripheral signal SPIM1.MOSI.
13694  *
13695  * 3 : Pin is connected to Peripheral signal SPIS1.MOSI.
13696  *
13697  * Field Access Macros:
13698  *
13699  */
13700 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13701 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0
13702 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13703 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1
13704 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13705 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2
13706 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */
13707 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003
13708 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value. */
13709 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc
13710 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field. */
13711 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0
13712 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO20_SEL field value from a register. */
13713 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
13714 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO20_SEL register field value suitable for setting the register. */
13715 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003)
13716 
13717 #ifndef __ASSEMBLY__
13718 /*
13719  * WARNING: The C register and register group struct declarations are provided for
13720  * convenience and illustrative purposes. They should, however, be used with
13721  * caution as the C language standard provides no guarantees about the alignment or
13722  * atomicity of device memory accesses. The recommended practice for writing
13723  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13724  * alt_write_word() functions.
13725  *
13726  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO20.
13727  */
13728 struct ALT_SYSMGR_PINMUX_GENERALIO20_s
13729 {
13730  uint32_t sel : 2; /* spis1_mosi Mux Selection Field */
13731  uint32_t : 30; /* *UNDEFINED* */
13732 };
13733 
13734 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO20. */
13735 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO20_s ALT_SYSMGR_PINMUX_GENERALIO20_t;
13736 #endif /* __ASSEMBLY__ */
13737 
13738 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO20 register from the beginning of the component. */
13739 #define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0
13740 
13741 /*
13742  * Register : spis1_miso Mux Selection Register - GENERALIO21
13743  *
13744  * This register is used to control the peripherals connected to spis1_miso
13745  *
13746  * Only reset by a cold reset (ignores warm reset).
13747  *
13748  * NOTE: These registers should not be modified after IO configuration.There is no
13749  * support for dynamically changing the Pin Mux selections.
13750  *
13751  * Register Layout
13752  *
13753  * Bits | Access | Reset | Description
13754  * :-------|:-------|:------|:-------------------------------
13755  * [1:0] | RW | 0x0 | spis1_miso Mux Selection Field
13756  * [31:2] | ??? | 0x0 | *UNDEFINED*
13757  *
13758  */
13759 /*
13760  * Field : spis1_miso Mux Selection Field - sel
13761  *
13762  * Select peripheral signals connected spis1_miso.
13763  *
13764  * 0 : Pin is connected to GPIO/LoanIO number 69.
13765  *
13766  * 1 : Pin is connected to Peripheral signal not applicable.
13767  *
13768  * 2 : Pin is connected to Peripheral signal SPIM1.MISO.
13769  *
13770  * 3 : Pin is connected to Peripheral signal SPIS1.MISO.
13771  *
13772  * Field Access Macros:
13773  *
13774  */
13775 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13776 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0
13777 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13778 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1
13779 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13780 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2
13781 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */
13782 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003
13783 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value. */
13784 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc
13785 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field. */
13786 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0
13787 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO21_SEL field value from a register. */
13788 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
13789 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO21_SEL register field value suitable for setting the register. */
13790 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003)
13791 
13792 #ifndef __ASSEMBLY__
13793 /*
13794  * WARNING: The C register and register group struct declarations are provided for
13795  * convenience and illustrative purposes. They should, however, be used with
13796  * caution as the C language standard provides no guarantees about the alignment or
13797  * atomicity of device memory accesses. The recommended practice for writing
13798  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13799  * alt_write_word() functions.
13800  *
13801  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO21.
13802  */
13803 struct ALT_SYSMGR_PINMUX_GENERALIO21_s
13804 {
13805  uint32_t sel : 2; /* spis1_miso Mux Selection Field */
13806  uint32_t : 30; /* *UNDEFINED* */
13807 };
13808 
13809 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO21. */
13810 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO21_s ALT_SYSMGR_PINMUX_GENERALIO21_t;
13811 #endif /* __ASSEMBLY__ */
13812 
13813 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO21 register from the beginning of the component. */
13814 #define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4
13815 
13816 /*
13817  * Register : spis1_ss0 Mux Selection Register - GENERALIO22
13818  *
13819  * This register is used to control the peripherals connected to spis1_ss0
13820  *
13821  * Only reset by a cold reset (ignores warm reset).
13822  *
13823  * NOTE: These registers should not be modified after IO configuration.There is no
13824  * support for dynamically changing the Pin Mux selections.
13825  *
13826  * Register Layout
13827  *
13828  * Bits | Access | Reset | Description
13829  * :-------|:-------|:------|:------------------------------
13830  * [1:0] | RW | 0x0 | spis1_ss0 Mux Selection Field
13831  * [31:2] | ??? | 0x0 | *UNDEFINED*
13832  *
13833  */
13834 /*
13835  * Field : spis1_ss0 Mux Selection Field - sel
13836  *
13837  * Select peripheral signals connected spis1_ss0.
13838  *
13839  * 0 : Pin is connected to GPIO/LoanIO number 70.
13840  *
13841  * 1 : Pin is connected to Peripheral signal not applicable.
13842  *
13843  * 2 : Pin is connected to Peripheral signal SPIM1.SS0.
13844  *
13845  * 3 : Pin is connected to Peripheral signal SPIS1.SS0.
13846  *
13847  * Field Access Macros:
13848  *
13849  */
13850 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13851 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0
13852 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13853 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1
13854 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13855 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2
13856 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */
13857 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003
13858 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value. */
13859 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc
13860 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field. */
13861 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0
13862 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO22_SEL field value from a register. */
13863 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0)
13864 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO22_SEL register field value suitable for setting the register. */
13865 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003)
13866 
13867 #ifndef __ASSEMBLY__
13868 /*
13869  * WARNING: The C register and register group struct declarations are provided for
13870  * convenience and illustrative purposes. They should, however, be used with
13871  * caution as the C language standard provides no guarantees about the alignment or
13872  * atomicity of device memory accesses. The recommended practice for writing
13873  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13874  * alt_write_word() functions.
13875  *
13876  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO22.
13877  */
13878 struct ALT_SYSMGR_PINMUX_GENERALIO22_s
13879 {
13880  uint32_t sel : 2; /* spis1_ss0 Mux Selection Field */
13881  uint32_t : 30; /* *UNDEFINED* */
13882 };
13883 
13884 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO22. */
13885 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO22_s ALT_SYSMGR_PINMUX_GENERALIO22_t;
13886 #endif /* __ASSEMBLY__ */
13887 
13888 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO22 register from the beginning of the component. */
13889 #define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8
13890 
13891 /*
13892  * Register : uart1_rx Mux Selection Register - GENERALIO23
13893  *
13894  * This register is used to control the peripherals connected to uart1_rx
13895  *
13896  * Only reset by a cold reset (ignores warm reset).
13897  *
13898  * NOTE: These registers should not be modified after IO configuration.There is no
13899  * support for dynamically changing the Pin Mux selections.
13900  *
13901  * Register Layout
13902  *
13903  * Bits | Access | Reset | Description
13904  * :-------|:-------|:------|:-----------------------------
13905  * [1:0] | RW | 0x0 | uart1_rx Mux Selection Field
13906  * [31:2] | ??? | 0x0 | *UNDEFINED*
13907  *
13908  */
13909 /*
13910  * Field : uart1_rx Mux Selection Field - sel
13911  *
13912  * Select peripheral signals connected uart1_rx.
13913  *
13914  * 0 : Pin is connected to GPIO/LoanIO number 62.
13915  *
13916  * 1 : Pin is connected to Peripheral signal not applicable.
13917  *
13918  * 2 : Pin is connected to Peripheral signal SPIM1.SS1.
13919  *
13920  * 3 : Pin is connected to Peripheral signal UART1.RX.
13921  *
13922  * Field Access Macros:
13923  *
13924  */
13925 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13926 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0
13927 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13928 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1
13929 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13930 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2
13931 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */
13932 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003
13933 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value. */
13934 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc
13935 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field. */
13936 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0
13937 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO23_SEL field value from a register. */
13938 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0)
13939 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO23_SEL register field value suitable for setting the register. */
13940 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003)
13941 
13942 #ifndef __ASSEMBLY__
13943 /*
13944  * WARNING: The C register and register group struct declarations are provided for
13945  * convenience and illustrative purposes. They should, however, be used with
13946  * caution as the C language standard provides no guarantees about the alignment or
13947  * atomicity of device memory accesses. The recommended practice for writing
13948  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
13949  * alt_write_word() functions.
13950  *
13951  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO23.
13952  */
13953 struct ALT_SYSMGR_PINMUX_GENERALIO23_s
13954 {
13955  uint32_t sel : 2; /* uart1_rx Mux Selection Field */
13956  uint32_t : 30; /* *UNDEFINED* */
13957 };
13958 
13959 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO23. */
13960 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO23_s ALT_SYSMGR_PINMUX_GENERALIO23_t;
13961 #endif /* __ASSEMBLY__ */
13962 
13963 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO23 register from the beginning of the component. */
13964 #define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc
13965 
13966 /*
13967  * Register : uart1_tx Mux Selection Register - GENERALIO24
13968  *
13969  * This register is used to control the peripherals connected to uart1_tx
13970  *
13971  * Only reset by a cold reset (ignores warm reset).
13972  *
13973  * NOTE: These registers should not be modified after IO configuration.There is no
13974  * support for dynamically changing the Pin Mux selections.
13975  *
13976  * Register Layout
13977  *
13978  * Bits | Access | Reset | Description
13979  * :-------|:-------|:------|:-----------------------------
13980  * [1:0] | RW | 0x0 | uart1_tx Mux Selection Field
13981  * [31:2] | ??? | 0x0 | *UNDEFINED*
13982  *
13983  */
13984 /*
13985  * Field : uart1_tx Mux Selection Field - sel
13986  *
13987  * Select peripheral signals connected uart1_tx.
13988  *
13989  * 0 : Pin is connected to GPIO/LoanIO number 63.
13990  *
13991  * 1 : Pin is connected to Peripheral signal not applicable.
13992  *
13993  * 2 : Pin is connected to Peripheral signal SPIM0.CLK.
13994  *
13995  * 3 : Pin is connected to Peripheral signal UART1.TX.
13996  *
13997  * Field Access Macros:
13998  *
13999  */
14000 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14001 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0
14002 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14003 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1
14004 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14005 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2
14006 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */
14007 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003
14008 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value. */
14009 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc
14010 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field. */
14011 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0
14012 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO24_SEL field value from a register. */
14013 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0)
14014 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO24_SEL register field value suitable for setting the register. */
14015 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003)
14016 
14017 #ifndef __ASSEMBLY__
14018 /*
14019  * WARNING: The C register and register group struct declarations are provided for
14020  * convenience and illustrative purposes. They should, however, be used with
14021  * caution as the C language standard provides no guarantees about the alignment or
14022  * atomicity of device memory accesses. The recommended practice for writing
14023  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14024  * alt_write_word() functions.
14025  *
14026  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO24.
14027  */
14028 struct ALT_SYSMGR_PINMUX_GENERALIO24_s
14029 {
14030  uint32_t sel : 2; /* uart1_tx Mux Selection Field */
14031  uint32_t : 30; /* *UNDEFINED* */
14032 };
14033 
14034 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO24. */
14035 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO24_s ALT_SYSMGR_PINMUX_GENERALIO24_t;
14036 #endif /* __ASSEMBLY__ */
14037 
14038 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO24 register from the beginning of the component. */
14039 #define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0
14040 
14041 /*
14042  * Register : i2c1_sda Mux Selection Register - GENERALIO25
14043  *
14044  * This register is used to control the peripherals connected to i2c1_sda
14045  *
14046  * Only reset by a cold reset (ignores warm reset).
14047  *
14048  * NOTE: These registers should not be modified after IO configuration.There is no
14049  * support for dynamically changing the Pin Mux selections.
14050  *
14051  * Register Layout
14052  *
14053  * Bits | Access | Reset | Description
14054  * :-------|:-------|:------|:-----------------------------
14055  * [1:0] | RW | 0x0 | i2c1_sda Mux Selection Field
14056  * [31:2] | ??? | 0x0 | *UNDEFINED*
14057  *
14058  */
14059 /*
14060  * Field : i2c1_sda Mux Selection Field - sel
14061  *
14062  * Select peripheral signals connected i2c1_sda.
14063  *
14064  * 0 : Pin is connected to GPIO/LoanIO number 64.
14065  *
14066  * 1 : Pin is connected to Peripheral signal not applicable.
14067  *
14068  * 2 : Pin is connected to Peripheral signal SPIM0.MOSI.
14069  *
14070  * 3 : Pin is connected to Peripheral signal I2C1.SDA.
14071  *
14072  * Field Access Macros:
14073  *
14074  */
14075 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14076 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0
14077 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14078 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1
14079 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14080 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2
14081 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */
14082 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003
14083 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value. */
14084 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc
14085 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field. */
14086 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0
14087 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO25_SEL field value from a register. */
14088 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0)
14089 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO25_SEL register field value suitable for setting the register. */
14090 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003)
14091 
14092 #ifndef __ASSEMBLY__
14093 /*
14094  * WARNING: The C register and register group struct declarations are provided for
14095  * convenience and illustrative purposes. They should, however, be used with
14096  * caution as the C language standard provides no guarantees about the alignment or
14097  * atomicity of device memory accesses. The recommended practice for writing
14098  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14099  * alt_write_word() functions.
14100  *
14101  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO25.
14102  */
14103 struct ALT_SYSMGR_PINMUX_GENERALIO25_s
14104 {
14105  uint32_t sel : 2; /* i2c1_sda Mux Selection Field */
14106  uint32_t : 30; /* *UNDEFINED* */
14107 };
14108 
14109 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO25. */
14110 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO25_s ALT_SYSMGR_PINMUX_GENERALIO25_t;
14111 #endif /* __ASSEMBLY__ */
14112 
14113 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO25 register from the beginning of the component. */
14114 #define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4
14115 
14116 /*
14117  * Register : i2c1_scl Mux Selection Register - GENERALIO26
14118  *
14119  * This register is used to control the peripherals connected to i2c1_scl
14120  *
14121  * Only reset by a cold reset (ignores warm reset).
14122  *
14123  * NOTE: These registers should not be modified after IO configuration.There is no
14124  * support for dynamically changing the Pin Mux selections.
14125  *
14126  * Register Layout
14127  *
14128  * Bits | Access | Reset | Description
14129  * :-------|:-------|:------|:-----------------------------
14130  * [1:0] | RW | 0x0 | i2c1_scl Mux Selection Field
14131  * [31:2] | ??? | 0x0 | *UNDEFINED*
14132  *
14133  */
14134 /*
14135  * Field : i2c1_scl Mux Selection Field - sel
14136  *
14137  * Select peripheral signals connected i2c1_scl.
14138  *
14139  * 0 : Pin is connected to GPIO/LoanIO number 65.
14140  *
14141  * 1 : Pin is connected to Peripheral signal not applicable.
14142  *
14143  * 2 : Pin is connected to Peripheral signal SPIM0.MISO.
14144  *
14145  * 3 : Pin is connected to Peripheral signal I2C1.SCL.
14146  *
14147  * Field Access Macros:
14148  *
14149  */
14150 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14151 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0
14152 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14153 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1
14154 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14155 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2
14156 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */
14157 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003
14158 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value. */
14159 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc
14160 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field. */
14161 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0
14162 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO26_SEL field value from a register. */
14163 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0)
14164 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO26_SEL register field value suitable for setting the register. */
14165 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003)
14166 
14167 #ifndef __ASSEMBLY__
14168 /*
14169  * WARNING: The C register and register group struct declarations are provided for
14170  * convenience and illustrative purposes. They should, however, be used with
14171  * caution as the C language standard provides no guarantees about the alignment or
14172  * atomicity of device memory accesses. The recommended practice for writing
14173  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14174  * alt_write_word() functions.
14175  *
14176  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO26.
14177  */
14178 struct ALT_SYSMGR_PINMUX_GENERALIO26_s
14179 {
14180  uint32_t sel : 2; /* i2c1_scl Mux Selection Field */
14181  uint32_t : 30; /* *UNDEFINED* */
14182 };
14183 
14184 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO26. */
14185 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO26_s ALT_SYSMGR_PINMUX_GENERALIO26_t;
14186 #endif /* __ASSEMBLY__ */
14187 
14188 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO26 register from the beginning of the component. */
14189 #define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8
14190 
14191 /*
14192  * Register : spim0_ss0_alt Mux Selection Register - GENERALIO27
14193  *
14194  * This register is used to control the peripherals connected to spim0_ss0_alt
14195  *
14196  * Only reset by a cold reset (ignores warm reset).
14197  *
14198  * NOTE: These registers should not be modified after IO configuration.There is no
14199  * support for dynamically changing the Pin Mux selections.
14200  *
14201  * Register Layout
14202  *
14203  * Bits | Access | Reset | Description
14204  * :-------|:-------|:------|:----------------------------------
14205  * [1:0] | RW | 0x0 | spim0_ss0_alt Mux Selection Field
14206  * [31:2] | ??? | 0x0 | *UNDEFINED*
14207  *
14208  */
14209 /*
14210  * Field : spim0_ss0_alt Mux Selection Field - sel
14211  *
14212  * Select peripheral signals connected spim0_ss0_alt.
14213  *
14214  * 0 : Pin is connected to GPIO/LoanIO number 66.
14215  *
14216  * 1 : Pin is connected to Peripheral signal not applicable.
14217  *
14218  * 2 : Pin is connected to Peripheral signal SPIM0.SS0.
14219  *
14220  * 3 : Pin is connected to Peripheral signal not applicable.
14221  *
14222  * Field Access Macros:
14223  *
14224  */
14225 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14226 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0
14227 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14228 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1
14229 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14230 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2
14231 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */
14232 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003
14233 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value. */
14234 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc
14235 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field. */
14236 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0
14237 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO27_SEL field value from a register. */
14238 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0)
14239 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO27_SEL register field value suitable for setting the register. */
14240 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003)
14241 
14242 #ifndef __ASSEMBLY__
14243 /*
14244  * WARNING: The C register and register group struct declarations are provided for
14245  * convenience and illustrative purposes. They should, however, be used with
14246  * caution as the C language standard provides no guarantees about the alignment or
14247  * atomicity of device memory accesses. The recommended practice for writing
14248  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14249  * alt_write_word() functions.
14250  *
14251  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO27.
14252  */
14253 struct ALT_SYSMGR_PINMUX_GENERALIO27_s
14254 {
14255  uint32_t sel : 2; /* spim0_ss0_alt Mux Selection Field */
14256  uint32_t : 30; /* *UNDEFINED* */
14257 };
14258 
14259 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO27. */
14260 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO27_s ALT_SYSMGR_PINMUX_GENERALIO27_t;
14261 #endif /* __ASSEMBLY__ */
14262 
14263 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO27 register from the beginning of the component. */
14264 #define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec
14265 
14266 /*
14267  * Register : spis0_clk Mux Selection Register - GENERALIO28
14268  *
14269  * This register is used to control the peripherals connected to spis0_clk
14270  *
14271  * Only reset by a cold reset (ignores warm reset).
14272  *
14273  * NOTE: These registers should not be modified after IO configuration.There is no
14274  * support for dynamically changing the Pin Mux selections.
14275  *
14276  * Register Layout
14277  *
14278  * Bits | Access | Reset | Description
14279  * :-------|:-------|:------|:------------------------------
14280  * [1:0] | RW | 0x0 | spis0_clk Mux Selection Field
14281  * [31:2] | ??? | 0x0 | *UNDEFINED*
14282  *
14283  */
14284 /*
14285  * Field : spis0_clk Mux Selection Field - sel
14286  *
14287  * Select peripheral signals connected spis0_clk.
14288  *
14289  * 0 : Pin is connected to GPIO/LoanIO number 67.
14290  *
14291  * 1 : Pin is connected to Peripheral signal not applicable.
14292  *
14293  * 2 : Pin is connected to Peripheral signal SPIM0.SS1.
14294  *
14295  * 3 : Pin is connected to Peripheral signal SPIS0.CLK.
14296  *
14297  * Field Access Macros:
14298  *
14299  */
14300 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14301 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0
14302 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14303 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1
14304 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14305 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2
14306 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */
14307 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003
14308 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value. */
14309 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc
14310 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field. */
14311 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0
14312 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO28_SEL field value from a register. */
14313 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0)
14314 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO28_SEL register field value suitable for setting the register. */
14315 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003)
14316 
14317 #ifndef __ASSEMBLY__
14318 /*
14319  * WARNING: The C register and register group struct declarations are provided for
14320  * convenience and illustrative purposes. They should, however, be used with
14321  * caution as the C language standard provides no guarantees about the alignment or
14322  * atomicity of device memory accesses. The recommended practice for writing
14323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14324  * alt_write_word() functions.
14325  *
14326  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO28.
14327  */
14328 struct ALT_SYSMGR_PINMUX_GENERALIO28_s
14329 {
14330  uint32_t sel : 2; /* spis0_clk Mux Selection Field */
14331  uint32_t : 30; /* *UNDEFINED* */
14332 };
14333 
14334 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO28. */
14335 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO28_s ALT_SYSMGR_PINMUX_GENERALIO28_t;
14336 #endif /* __ASSEMBLY__ */
14337 
14338 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO28 register from the beginning of the component. */
14339 #define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0
14340 
14341 /*
14342  * Register : spis0_mosi Mux Selection Register - GENERALIO29
14343  *
14344  * This register is used to control the peripherals connected to spis0_mosi
14345  *
14346  * Only reset by a cold reset (ignores warm reset).
14347  *
14348  * NOTE: These registers should not be modified after IO configuration.There is no
14349  * support for dynamically changing the Pin Mux selections.
14350  *
14351  * Register Layout
14352  *
14353  * Bits | Access | Reset | Description
14354  * :-------|:-------|:------|:-------------------------------
14355  * [1:0] | RW | 0x0 | spis0_mosi Mux Selection Field
14356  * [31:2] | ??? | 0x0 | *UNDEFINED*
14357  *
14358  */
14359 /*
14360  * Field : spis0_mosi Mux Selection Field - sel
14361  *
14362  * Select peripheral signals connected spis0_mosi.
14363  *
14364  * 0 : Pin is connected to GPIO/LoanIO number 68.
14365  *
14366  * 1 : Pin is connected to Peripheral signal not applicable.
14367  *
14368  * 2 : Pin is connected to Peripheral signal not applicable.
14369  *
14370  * 3 : Pin is connected to Peripheral signal SPIS0.MOSI.
14371  *
14372  * Field Access Macros:
14373  *
14374  */
14375 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14376 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0
14377 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14378 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1
14379 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14380 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2
14381 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */
14382 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003
14383 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value. */
14384 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc
14385 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field. */
14386 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0
14387 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO29_SEL field value from a register. */
14388 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0)
14389 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO29_SEL register field value suitable for setting the register. */
14390 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003)
14391 
14392 #ifndef __ASSEMBLY__
14393 /*
14394  * WARNING: The C register and register group struct declarations are provided for
14395  * convenience and illustrative purposes. They should, however, be used with
14396  * caution as the C language standard provides no guarantees about the alignment or
14397  * atomicity of device memory accesses. The recommended practice for writing
14398  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14399  * alt_write_word() functions.
14400  *
14401  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO29.
14402  */
14403 struct ALT_SYSMGR_PINMUX_GENERALIO29_s
14404 {
14405  uint32_t sel : 2; /* spis0_mosi Mux Selection Field */
14406  uint32_t : 30; /* *UNDEFINED* */
14407 };
14408 
14409 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO29. */
14410 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO29_s ALT_SYSMGR_PINMUX_GENERALIO29_t;
14411 #endif /* __ASSEMBLY__ */
14412 
14413 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO29 register from the beginning of the component. */
14414 #define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4
14415 
14416 /*
14417  * Register : spis0_miso Mux Selection Register - GENERALIO30
14418  *
14419  * This register is used to control the peripherals connected to spis0_miso
14420  *
14421  * Only reset by a cold reset (ignores warm reset).
14422  *
14423  * NOTE: These registers should not be modified after IO configuration.There is no
14424  * support for dynamically changing the Pin Mux selections.
14425  *
14426  * Register Layout
14427  *
14428  * Bits | Access | Reset | Description
14429  * :-------|:-------|:------|:-------------------------------
14430  * [1:0] | RW | 0x0 | spis0_miso Mux Selection Field
14431  * [31:2] | ??? | 0x0 | *UNDEFINED*
14432  *
14433  */
14434 /*
14435  * Field : spis0_miso Mux Selection Field - sel
14436  *
14437  * Select peripheral signals connected spis0_miso.
14438  *
14439  * 0 : Pin is connected to GPIO/LoanIO number 69.
14440  *
14441  * 1 : Pin is connected to Peripheral signal not applicable.
14442  *
14443  * 2 : Pin is connected to Peripheral signal not applicable.
14444  *
14445  * 3 : Pin is connected to Peripheral signal SPIS0.MISO.
14446  *
14447  * Field Access Macros:
14448  *
14449  */
14450 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14451 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0
14452 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14453 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1
14454 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14455 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2
14456 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */
14457 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003
14458 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value. */
14459 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc
14460 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field. */
14461 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0
14462 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO30_SEL field value from a register. */
14463 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0)
14464 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO30_SEL register field value suitable for setting the register. */
14465 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003)
14466 
14467 #ifndef __ASSEMBLY__
14468 /*
14469  * WARNING: The C register and register group struct declarations are provided for
14470  * convenience and illustrative purposes. They should, however, be used with
14471  * caution as the C language standard provides no guarantees about the alignment or
14472  * atomicity of device memory accesses. The recommended practice for writing
14473  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14474  * alt_write_word() functions.
14475  *
14476  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO30.
14477  */
14478 struct ALT_SYSMGR_PINMUX_GENERALIO30_s
14479 {
14480  uint32_t sel : 2; /* spis0_miso Mux Selection Field */
14481  uint32_t : 30; /* *UNDEFINED* */
14482 };
14483 
14484 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO30. */
14485 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO30_s ALT_SYSMGR_PINMUX_GENERALIO30_t;
14486 #endif /* __ASSEMBLY__ */
14487 
14488 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO30 register from the beginning of the component. */
14489 #define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8
14490 
14491 /*
14492  * Register : spis0_ss0 Mux Selection Register - GENERALIO31
14493  *
14494  * This register is used to control the peripherals connected to spis0_ss0
14495  *
14496  * Only reset by a cold reset (ignores warm reset).
14497  *
14498  * NOTE: These registers should not be modified after IO configuration.There is no
14499  * support for dynamically changing the Pin Mux selections.
14500  *
14501  * Register Layout
14502  *
14503  * Bits | Access | Reset | Description
14504  * :-------|:-------|:------|:------------------------------
14505  * [1:0] | RW | 0x0 | spis0_ss0 Mux Selection Field
14506  * [31:2] | ??? | 0x0 | *UNDEFINED*
14507  *
14508  */
14509 /*
14510  * Field : spis0_ss0 Mux Selection Field - sel
14511  *
14512  * Select peripheral signals connected spis0_ss0.
14513  *
14514  * 0 : Pin is connected to GPIO/LoanIO number 70.
14515  *
14516  * 1 : Pin is connected to Peripheral signal not applicable.
14517  *
14518  * 2 : Pin is connected to Peripheral signal not applicable.
14519  *
14520  * 3 : Pin is connected to Peripheral signal SPIS0.SS0.
14521  *
14522  * Field Access Macros:
14523  *
14524  */
14525 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14526 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0
14527 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14528 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1
14529 /* The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14530 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2
14531 /* The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */
14532 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003
14533 /* The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value. */
14534 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc
14535 /* The reset value of the ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field. */
14536 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0
14537 /* Extracts the ALT_SYSMGR_PINMUX_GENERALIO31_SEL field value from a register. */
14538 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0)
14539 /* Produces a ALT_SYSMGR_PINMUX_GENERALIO31_SEL register field value suitable for setting the register. */
14540 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003)
14541 
14542 #ifndef __ASSEMBLY__
14543 /*
14544  * WARNING: The C register and register group struct declarations are provided for
14545  * convenience and illustrative purposes. They should, however, be used with
14546  * caution as the C language standard provides no guarantees about the alignment or
14547  * atomicity of device memory accesses. The recommended practice for writing
14548  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14549  * alt_write_word() functions.
14550  *
14551  * The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO31.
14552  */
14553 struct ALT_SYSMGR_PINMUX_GENERALIO31_s
14554 {
14555  uint32_t sel : 2; /* spis0_ss0 Mux Selection Field */
14556  uint32_t : 30; /* *UNDEFINED* */
14557 };
14558 
14559 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GENERALIO31. */
14560 typedef volatile struct ALT_SYSMGR_PINMUX_GENERALIO31_s ALT_SYSMGR_PINMUX_GENERALIO31_t;
14561 #endif /* __ASSEMBLY__ */
14562 
14563 /* The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO31 register from the beginning of the component. */
14564 #define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc
14565 
14566 /*
14567  * Register : nand_ale Mux Selection Register - MIXED1IO0
14568  *
14569  * This register is used to control the peripherals connected to nand_ale
14570  *
14571  * Only reset by a cold reset (ignores warm reset).
14572  *
14573  * NOTE: These registers should not be modified after IO configuration.There is no
14574  * support for dynamically changing the Pin Mux selections.
14575  *
14576  * Register Layout
14577  *
14578  * Bits | Access | Reset | Description
14579  * :-------|:-------|:------|:-----------------------------
14580  * [1:0] | RW | 0x0 | nand_ale Mux Selection Field
14581  * [31:2] | ??? | 0x0 | *UNDEFINED*
14582  *
14583  */
14584 /*
14585  * Field : nand_ale Mux Selection Field - sel
14586  *
14587  * Select peripheral signals connected nand_ale.
14588  *
14589  * 0 : Pin is connected to GPIO/LoanIO number 14.
14590  *
14591  * 1 : Pin is connected to Peripheral signal QSPI.SS3.
14592  *
14593  * 2 : Pin is connected to Peripheral signal RGMII1.TX_CLK.
14594  *
14595  * 3 : Pin is connected to Peripheral signal NAND.ale.
14596  *
14597  * Field Access Macros:
14598  *
14599  */
14600 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14601 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0
14602 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14603 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1
14604 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14605 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2
14606 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */
14607 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003
14608 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value. */
14609 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc
14610 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field. */
14611 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0
14612 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO0_SEL field value from a register. */
14613 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
14614 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO0_SEL register field value suitable for setting the register. */
14615 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
14616 
14617 #ifndef __ASSEMBLY__
14618 /*
14619  * WARNING: The C register and register group struct declarations are provided for
14620  * convenience and illustrative purposes. They should, however, be used with
14621  * caution as the C language standard provides no guarantees about the alignment or
14622  * atomicity of device memory accesses. The recommended practice for writing
14623  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14624  * alt_write_word() functions.
14625  *
14626  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0.
14627  */
14628 struct ALT_SYSMGR_PINMUX_MIXED1IO0_s
14629 {
14630  uint32_t sel : 2; /* nand_ale Mux Selection Field */
14631  uint32_t : 30; /* *UNDEFINED* */
14632 };
14633 
14634 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO0. */
14635 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO0_s ALT_SYSMGR_PINMUX_MIXED1IO0_t;
14636 #endif /* __ASSEMBLY__ */
14637 
14638 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO0 register from the beginning of the component. */
14639 #define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100
14640 
14641 /*
14642  * Register : nand_ce Mux Selection Register - MIXED1IO1
14643  *
14644  * This register is used to control the peripherals connected to nand_ce
14645  *
14646  * Only reset by a cold reset (ignores warm reset).
14647  *
14648  * NOTE: These registers should not be modified after IO configuration.There is no
14649  * support for dynamically changing the Pin Mux selections.
14650  *
14651  * Register Layout
14652  *
14653  * Bits | Access | Reset | Description
14654  * :-------|:-------|:------|:----------------------------
14655  * [1:0] | RW | 0x0 | nand_ce Mux Selection Field
14656  * [31:2] | ??? | 0x0 | *UNDEFINED*
14657  *
14658  */
14659 /*
14660  * Field : nand_ce Mux Selection Field - sel
14661  *
14662  * Select peripheral signals connected nand_ce.
14663  *
14664  * 0 : Pin is connected to GPIO/LoanIO number 15.
14665  *
14666  * 1 : Pin is connected to Peripheral signal USB1.D0.
14667  *
14668  * 2 : Pin is connected to Peripheral signal RGMII1.TXD0.
14669  *
14670  * 3 : Pin is connected to Peripheral signal NAND.ce.
14671  *
14672  * Field Access Macros:
14673  *
14674  */
14675 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14676 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0
14677 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14678 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1
14679 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14680 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2
14681 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */
14682 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003
14683 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value. */
14684 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc
14685 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field. */
14686 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0
14687 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO1_SEL field value from a register. */
14688 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
14689 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO1_SEL register field value suitable for setting the register. */
14690 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
14691 
14692 #ifndef __ASSEMBLY__
14693 /*
14694  * WARNING: The C register and register group struct declarations are provided for
14695  * convenience and illustrative purposes. They should, however, be used with
14696  * caution as the C language standard provides no guarantees about the alignment or
14697  * atomicity of device memory accesses. The recommended practice for writing
14698  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14699  * alt_write_word() functions.
14700  *
14701  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1.
14702  */
14703 struct ALT_SYSMGR_PINMUX_MIXED1IO1_s
14704 {
14705  uint32_t sel : 2; /* nand_ce Mux Selection Field */
14706  uint32_t : 30; /* *UNDEFINED* */
14707 };
14708 
14709 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO1. */
14710 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO1_s ALT_SYSMGR_PINMUX_MIXED1IO1_t;
14711 #endif /* __ASSEMBLY__ */
14712 
14713 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO1 register from the beginning of the component. */
14714 #define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104
14715 
14716 /*
14717  * Register : nand_cle Mux Selection Register - MIXED1IO2
14718  *
14719  * This register is used to control the peripherals connected to nand_cle
14720  *
14721  * Only reset by a cold reset (ignores warm reset).
14722  *
14723  * NOTE: These registers should not be modified after IO configuration.There is no
14724  * support for dynamically changing the Pin Mux selections.
14725  *
14726  * Register Layout
14727  *
14728  * Bits | Access | Reset | Description
14729  * :-------|:-------|:------|:-----------------------------
14730  * [1:0] | RW | 0x0 | nand_cle Mux Selection Field
14731  * [31:2] | ??? | 0x0 | *UNDEFINED*
14732  *
14733  */
14734 /*
14735  * Field : nand_cle Mux Selection Field - sel
14736  *
14737  * Select peripheral signals connected nand_cle.
14738  *
14739  * 0 : Pin is connected to GPIO/LoanIO number 16.
14740  *
14741  * 1 : Pin is connected to Peripheral signal USB1.D1.
14742  *
14743  * 2 : Pin is connected to Peripheral signal RGMII1.TXD1.
14744  *
14745  * 3 : Pin is connected to Peripheral signal NAND.cle.
14746  *
14747  * Field Access Macros:
14748  *
14749  */
14750 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14751 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0
14752 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14753 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1
14754 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14755 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2
14756 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */
14757 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003
14758 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value. */
14759 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc
14760 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field. */
14761 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0
14762 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO2_SEL field value from a register. */
14763 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
14764 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO2_SEL register field value suitable for setting the register. */
14765 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
14766 
14767 #ifndef __ASSEMBLY__
14768 /*
14769  * WARNING: The C register and register group struct declarations are provided for
14770  * convenience and illustrative purposes. They should, however, be used with
14771  * caution as the C language standard provides no guarantees about the alignment or
14772  * atomicity of device memory accesses. The recommended practice for writing
14773  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14774  * alt_write_word() functions.
14775  *
14776  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2.
14777  */
14778 struct ALT_SYSMGR_PINMUX_MIXED1IO2_s
14779 {
14780  uint32_t sel : 2; /* nand_cle Mux Selection Field */
14781  uint32_t : 30; /* *UNDEFINED* */
14782 };
14783 
14784 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO2. */
14785 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO2_s ALT_SYSMGR_PINMUX_MIXED1IO2_t;
14786 #endif /* __ASSEMBLY__ */
14787 
14788 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO2 register from the beginning of the component. */
14789 #define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108
14790 
14791 /*
14792  * Register : nand_re Mux Selection Register - MIXED1IO3
14793  *
14794  * This register is used to control the peripherals connected to nand_re
14795  *
14796  * Only reset by a cold reset (ignores warm reset).
14797  *
14798  * NOTE: These registers should not be modified after IO configuration.There is no
14799  * support for dynamically changing the Pin Mux selections.
14800  *
14801  * Register Layout
14802  *
14803  * Bits | Access | Reset | Description
14804  * :-------|:-------|:------|:----------------------------
14805  * [1:0] | RW | 0x0 | nand_re Mux Selection Field
14806  * [31:2] | ??? | 0x0 | *UNDEFINED*
14807  *
14808  */
14809 /*
14810  * Field : nand_re Mux Selection Field - sel
14811  *
14812  * Select peripheral signals connected nand_re.
14813  *
14814  * 0 : Pin is connected to GPIO/LoanIO number 17.
14815  *
14816  * 1 : Pin is connected to Peripheral signal USB1.D2.
14817  *
14818  * 2 : Pin is connected to Peripheral signal RGMII1.TXD2.
14819  *
14820  * 3 : Pin is connected to Peripheral signal NAND.re.
14821  *
14822  * Field Access Macros:
14823  *
14824  */
14825 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14826 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0
14827 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14828 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1
14829 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14830 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2
14831 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */
14832 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003
14833 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value. */
14834 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc
14835 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field. */
14836 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0
14837 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO3_SEL field value from a register. */
14838 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
14839 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO3_SEL register field value suitable for setting the register. */
14840 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
14841 
14842 #ifndef __ASSEMBLY__
14843 /*
14844  * WARNING: The C register and register group struct declarations are provided for
14845  * convenience and illustrative purposes. They should, however, be used with
14846  * caution as the C language standard provides no guarantees about the alignment or
14847  * atomicity of device memory accesses. The recommended practice for writing
14848  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14849  * alt_write_word() functions.
14850  *
14851  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3.
14852  */
14853 struct ALT_SYSMGR_PINMUX_MIXED1IO3_s
14854 {
14855  uint32_t sel : 2; /* nand_re Mux Selection Field */
14856  uint32_t : 30; /* *UNDEFINED* */
14857 };
14858 
14859 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO3. */
14860 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO3_s ALT_SYSMGR_PINMUX_MIXED1IO3_t;
14861 #endif /* __ASSEMBLY__ */
14862 
14863 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO3 register from the beginning of the component. */
14864 #define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c
14865 
14866 /*
14867  * Register : nand_rb Mux Selection Register - MIXED1IO4
14868  *
14869  * This register is used to control the peripherals connected to nand_rb
14870  *
14871  * Only reset by a cold reset (ignores warm reset).
14872  *
14873  * NOTE: These registers should not be modified after IO configuration.There is no
14874  * support for dynamically changing the Pin Mux selections.
14875  *
14876  * Register Layout
14877  *
14878  * Bits | Access | Reset | Description
14879  * :-------|:-------|:------|:----------------------------
14880  * [1:0] | RW | 0x0 | nand_rb Mux Selection Field
14881  * [31:2] | ??? | 0x0 | *UNDEFINED*
14882  *
14883  */
14884 /*
14885  * Field : nand_rb Mux Selection Field - sel
14886  *
14887  * Select peripheral signals connected nand_rb.
14888  *
14889  * 0 : Pin is connected to GPIO/LoanIO number 18.
14890  *
14891  * 1 : Pin is connected to Peripheral signal USB1.D3.
14892  *
14893  * 2 : Pin is connected to Peripheral signal RGMII1.TXD3.
14894  *
14895  * 3 : Pin is connected to Peripheral signal NAND.rb.
14896  *
14897  * Field Access Macros:
14898  *
14899  */
14900 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14901 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0
14902 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14903 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1
14904 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14905 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2
14906 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */
14907 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003
14908 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value. */
14909 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc
14910 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field. */
14911 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0
14912 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO4_SEL field value from a register. */
14913 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
14914 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO4_SEL register field value suitable for setting the register. */
14915 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
14916 
14917 #ifndef __ASSEMBLY__
14918 /*
14919  * WARNING: The C register and register group struct declarations are provided for
14920  * convenience and illustrative purposes. They should, however, be used with
14921  * caution as the C language standard provides no guarantees about the alignment or
14922  * atomicity of device memory accesses. The recommended practice for writing
14923  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14924  * alt_write_word() functions.
14925  *
14926  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4.
14927  */
14928 struct ALT_SYSMGR_PINMUX_MIXED1IO4_s
14929 {
14930  uint32_t sel : 2; /* nand_rb Mux Selection Field */
14931  uint32_t : 30; /* *UNDEFINED* */
14932 };
14933 
14934 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO4. */
14935 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO4_s ALT_SYSMGR_PINMUX_MIXED1IO4_t;
14936 #endif /* __ASSEMBLY__ */
14937 
14938 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO4 register from the beginning of the component. */
14939 #define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110
14940 
14941 /*
14942  * Register : nand_dq0 Mux Selection Register - MIXED1IO5
14943  *
14944  * This register is used to control the peripherals connected to nand_dq0
14945  *
14946  * Only reset by a cold reset (ignores warm reset).
14947  *
14948  * NOTE: These registers should not be modified after IO configuration.There is no
14949  * support for dynamically changing the Pin Mux selections.
14950  *
14951  * Register Layout
14952  *
14953  * Bits | Access | Reset | Description
14954  * :-------|:-------|:------|:-----------------------------
14955  * [1:0] | RW | 0x0 | nand_dq0 Mux Selection Field
14956  * [31:2] | ??? | 0x0 | *UNDEFINED*
14957  *
14958  */
14959 /*
14960  * Field : nand_dq0 Mux Selection Field - sel
14961  *
14962  * Select peripheral signals connected nand_dq0.
14963  *
14964  * 0 : Pin is connected to GPIO/LoanIO number 19.
14965  *
14966  * 1 : Pin is connected to Peripheral signal not applicable.
14967  *
14968  * 2 : Pin is connected to Peripheral signal RGMII1.RXD0.
14969  *
14970  * 3 : Pin is connected to Peripheral signal NAND.dq0.
14971  *
14972  * Field Access Macros:
14973  *
14974  */
14975 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14976 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0
14977 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14978 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1
14979 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14980 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2
14981 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */
14982 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003
14983 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value. */
14984 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc
14985 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field. */
14986 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0
14987 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO5_SEL field value from a register. */
14988 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
14989 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO5_SEL register field value suitable for setting the register. */
14990 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
14991 
14992 #ifndef __ASSEMBLY__
14993 /*
14994  * WARNING: The C register and register group struct declarations are provided for
14995  * convenience and illustrative purposes. They should, however, be used with
14996  * caution as the C language standard provides no guarantees about the alignment or
14997  * atomicity of device memory accesses. The recommended practice for writing
14998  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
14999  * alt_write_word() functions.
15000  *
15001  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5.
15002  */
15003 struct ALT_SYSMGR_PINMUX_MIXED1IO5_s
15004 {
15005  uint32_t sel : 2; /* nand_dq0 Mux Selection Field */
15006  uint32_t : 30; /* *UNDEFINED* */
15007 };
15008 
15009 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO5. */
15010 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO5_s ALT_SYSMGR_PINMUX_MIXED1IO5_t;
15011 #endif /* __ASSEMBLY__ */
15012 
15013 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO5 register from the beginning of the component. */
15014 #define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114
15015 
15016 /*
15017  * Register : nand_dq1 Mux Selection Register - MIXED1IO6
15018  *
15019  * This register is used to control the peripherals connected to nand_dq1
15020  *
15021  * Only reset by a cold reset (ignores warm reset).
15022  *
15023  * NOTE: These registers should not be modified after IO configuration.There is no
15024  * support for dynamically changing the Pin Mux selections.
15025  *
15026  * Register Layout
15027  *
15028  * Bits | Access | Reset | Description
15029  * :-------|:-------|:------|:-----------------------------
15030  * [1:0] | RW | 0x0 | nand_dq1 Mux Selection Field
15031  * [31:2] | ??? | 0x0 | *UNDEFINED*
15032  *
15033  */
15034 /*
15035  * Field : nand_dq1 Mux Selection Field - sel
15036  *
15037  * Select peripheral signals connected nand_dq1.
15038  *
15039  * 0 : Pin is connected to GPIO/LoanIO number 20.
15040  *
15041  * 1 : Pin is connected to Peripheral signal I2C3.SDA.
15042  *
15043  * 2 : Pin is connected to Peripheral signal RGMII1.MDIO.
15044  *
15045  * 3 : Pin is connected to Peripheral signal NAND.dq1.
15046  *
15047  * Field Access Macros:
15048  *
15049  */
15050 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15051 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0
15052 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15053 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1
15054 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15055 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2
15056 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */
15057 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003
15058 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value. */
15059 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc
15060 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field. */
15061 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0
15062 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO6_SEL field value from a register. */
15063 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
15064 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO6_SEL register field value suitable for setting the register. */
15065 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
15066 
15067 #ifndef __ASSEMBLY__
15068 /*
15069  * WARNING: The C register and register group struct declarations are provided for
15070  * convenience and illustrative purposes. They should, however, be used with
15071  * caution as the C language standard provides no guarantees about the alignment or
15072  * atomicity of device memory accesses. The recommended practice for writing
15073  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15074  * alt_write_word() functions.
15075  *
15076  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6.
15077  */
15078 struct ALT_SYSMGR_PINMUX_MIXED1IO6_s
15079 {
15080  uint32_t sel : 2; /* nand_dq1 Mux Selection Field */
15081  uint32_t : 30; /* *UNDEFINED* */
15082 };
15083 
15084 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO6. */
15085 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO6_s ALT_SYSMGR_PINMUX_MIXED1IO6_t;
15086 #endif /* __ASSEMBLY__ */
15087 
15088 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO6 register from the beginning of the component. */
15089 #define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118
15090 
15091 /*
15092  * Register : nand_dq2 Mux Selection Register - MIXED1IO7
15093  *
15094  * This register is used to control the peripherals connected to nand_dq2
15095  *
15096  * Only reset by a cold reset (ignores warm reset).
15097  *
15098  * NOTE: These registers should not be modified after IO configuration.There is no
15099  * support for dynamically changing the Pin Mux selections.
15100  *
15101  * Register Layout
15102  *
15103  * Bits | Access | Reset | Description
15104  * :-------|:-------|:------|:-----------------------------
15105  * [1:0] | RW | 0x0 | nand_dq2 Mux Selection Field
15106  * [31:2] | ??? | 0x0 | *UNDEFINED*
15107  *
15108  */
15109 /*
15110  * Field : nand_dq2 Mux Selection Field - sel
15111  *
15112  * Select peripheral signals connected nand_dq2.
15113  *
15114  * 0 : Pin is connected to GPIO/LoanIO number 21.
15115  *
15116  * 1 : Pin is connected to Peripheral signal I2C3.SCL.
15117  *
15118  * 2 : Pin is connected to Peripheral signal RGMII1.MDC.
15119  *
15120  * 3 : Pin is connected to Peripheral signal NAND.dq2.
15121  *
15122  * Field Access Macros:
15123  *
15124  */
15125 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15126 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0
15127 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15128 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1
15129 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15130 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2
15131 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */
15132 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003
15133 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value. */
15134 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc
15135 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field. */
15136 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0
15137 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO7_SEL field value from a register. */
15138 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
15139 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO7_SEL register field value suitable for setting the register. */
15140 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
15141 
15142 #ifndef __ASSEMBLY__
15143 /*
15144  * WARNING: The C register and register group struct declarations are provided for
15145  * convenience and illustrative purposes. They should, however, be used with
15146  * caution as the C language standard provides no guarantees about the alignment or
15147  * atomicity of device memory accesses. The recommended practice for writing
15148  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15149  * alt_write_word() functions.
15150  *
15151  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7.
15152  */
15153 struct ALT_SYSMGR_PINMUX_MIXED1IO7_s
15154 {
15155  uint32_t sel : 2; /* nand_dq2 Mux Selection Field */
15156  uint32_t : 30; /* *UNDEFINED* */
15157 };
15158 
15159 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO7. */
15160 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO7_s ALT_SYSMGR_PINMUX_MIXED1IO7_t;
15161 #endif /* __ASSEMBLY__ */
15162 
15163 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO7 register from the beginning of the component. */
15164 #define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c
15165 
15166 /*
15167  * Register : nand_dq3 Mux Selection Register - MIXED1IO8
15168  *
15169  * This register is used to control the peripherals connected to nand_dq3
15170  *
15171  * Only reset by a cold reset (ignores warm reset).
15172  *
15173  * NOTE: These registers should not be modified after IO configuration.There is no
15174  * support for dynamically changing the Pin Mux selections.
15175  *
15176  * Register Layout
15177  *
15178  * Bits | Access | Reset | Description
15179  * :-------|:-------|:------|:-----------------------------
15180  * [1:0] | RW | 0x0 | nand_dq3 Mux Selection Field
15181  * [31:2] | ??? | 0x0 | *UNDEFINED*
15182  *
15183  */
15184 /*
15185  * Field : nand_dq3 Mux Selection Field - sel
15186  *
15187  * Select peripheral signals connected nand_dq3.
15188  *
15189  * 0 : Pin is connected to GPIO/LoanIO number 22.
15190  *
15191  * 1 : Pin is connected to Peripheral signal USB1.D4.
15192  *
15193  * 2 : Pin is connected to Peripheral signal RGMII1.RX_CTL.
15194  *
15195  * 3 : Pin is connected to Peripheral signal NAND.dq3.
15196  *
15197  * Field Access Macros:
15198  *
15199  */
15200 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15201 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0
15202 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15203 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1
15204 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15205 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2
15206 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */
15207 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003
15208 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value. */
15209 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc
15210 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field. */
15211 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0
15212 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO8_SEL field value from a register. */
15213 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
15214 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO8_SEL register field value suitable for setting the register. */
15215 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003)
15216 
15217 #ifndef __ASSEMBLY__
15218 /*
15219  * WARNING: The C register and register group struct declarations are provided for
15220  * convenience and illustrative purposes. They should, however, be used with
15221  * caution as the C language standard provides no guarantees about the alignment or
15222  * atomicity of device memory accesses. The recommended practice for writing
15223  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15224  * alt_write_word() functions.
15225  *
15226  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8.
15227  */
15228 struct ALT_SYSMGR_PINMUX_MIXED1IO8_s
15229 {
15230  uint32_t sel : 2; /* nand_dq3 Mux Selection Field */
15231  uint32_t : 30; /* *UNDEFINED* */
15232 };
15233 
15234 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO8. */
15235 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO8_s ALT_SYSMGR_PINMUX_MIXED1IO8_t;
15236 #endif /* __ASSEMBLY__ */
15237 
15238 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO8 register from the beginning of the component. */
15239 #define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120
15240 
15241 /*
15242  * Register : nand_dq4 Mux Selection Register - MIXED1IO9
15243  *
15244  * This register is used to control the peripherals connected to nand_dq4
15245  *
15246  * Only reset by a cold reset (ignores warm reset).
15247  *
15248  * NOTE: These registers should not be modified after IO configuration.There is no
15249  * support for dynamically changing the Pin Mux selections.
15250  *
15251  * Register Layout
15252  *
15253  * Bits | Access | Reset | Description
15254  * :-------|:-------|:------|:-----------------------------
15255  * [1:0] | RW | 0x0 | nand_dq4 Mux Selection Field
15256  * [31:2] | ??? | 0x0 | *UNDEFINED*
15257  *
15258  */
15259 /*
15260  * Field : nand_dq4 Mux Selection Field - sel
15261  *
15262  * Select peripheral signals connected nand_dq4.
15263  *
15264  * 0 : Pin is connected to GPIO/LoanIO number 23.
15265  *
15266  * 1 : Pin is connected to Peripheral signal USB1.D5.
15267  *
15268  * 2 : Pin is connected to Peripheral signal RGMII1.TX_CTL.
15269  *
15270  * 3 : Pin is connected to Peripheral signal NAND.dq4.
15271  *
15272  * Field Access Macros:
15273  *
15274  */
15275 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15276 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0
15277 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15278 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1
15279 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15280 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2
15281 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */
15282 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003
15283 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value. */
15284 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc
15285 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field. */
15286 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0
15287 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO9_SEL field value from a register. */
15288 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
15289 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO9_SEL register field value suitable for setting the register. */
15290 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003)
15291 
15292 #ifndef __ASSEMBLY__
15293 /*
15294  * WARNING: The C register and register group struct declarations are provided for
15295  * convenience and illustrative purposes. They should, however, be used with
15296  * caution as the C language standard provides no guarantees about the alignment or
15297  * atomicity of device memory accesses. The recommended practice for writing
15298  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15299  * alt_write_word() functions.
15300  *
15301  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9.
15302  */
15303 struct ALT_SYSMGR_PINMUX_MIXED1IO9_s
15304 {
15305  uint32_t sel : 2; /* nand_dq4 Mux Selection Field */
15306  uint32_t : 30; /* *UNDEFINED* */
15307 };
15308 
15309 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO9. */
15310 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO9_s ALT_SYSMGR_PINMUX_MIXED1IO9_t;
15311 #endif /* __ASSEMBLY__ */
15312 
15313 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO9 register from the beginning of the component. */
15314 #define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124
15315 
15316 /*
15317  * Register : nand_dq5 Mux Selection Register - MIXED1IO10
15318  *
15319  * This register is used to control the peripherals connected to nand_dq5
15320  *
15321  * Only reset by a cold reset (ignores warm reset).
15322  *
15323  * NOTE: These registers should not be modified after IO configuration.There is no
15324  * support for dynamically changing the Pin Mux selections.
15325  *
15326  * Register Layout
15327  *
15328  * Bits | Access | Reset | Description
15329  * :-------|:-------|:------|:-----------------------------
15330  * [1:0] | RW | 0x0 | nand_dq5 Mux Selection Field
15331  * [31:2] | ??? | 0x0 | *UNDEFINED*
15332  *
15333  */
15334 /*
15335  * Field : nand_dq5 Mux Selection Field - sel
15336  *
15337  * Select peripheral signals connected nand_dq5.
15338  *
15339  * 0 : Pin is connected to GPIO/LoanIO number 24.
15340  *
15341  * 1 : Pin is connected to Peripheral signal USB1.D6.
15342  *
15343  * 2 : Pin is connected to Peripheral signal RGMII1.RX_CLK.
15344  *
15345  * 3 : Pin is connected to Peripheral signal NAND.dq5.
15346  *
15347  * Field Access Macros:
15348  *
15349  */
15350 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15351 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0
15352 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15353 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1
15354 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15355 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2
15356 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */
15357 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003
15358 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value. */
15359 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc
15360 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field. */
15361 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0
15362 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO10_SEL field value from a register. */
15363 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
15364 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO10_SEL register field value suitable for setting the register. */
15365 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003)
15366 
15367 #ifndef __ASSEMBLY__
15368 /*
15369  * WARNING: The C register and register group struct declarations are provided for
15370  * convenience and illustrative purposes. They should, however, be used with
15371  * caution as the C language standard provides no guarantees about the alignment or
15372  * atomicity of device memory accesses. The recommended practice for writing
15373  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15374  * alt_write_word() functions.
15375  *
15376  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10.
15377  */
15378 struct ALT_SYSMGR_PINMUX_MIXED1IO10_s
15379 {
15380  uint32_t sel : 2; /* nand_dq5 Mux Selection Field */
15381  uint32_t : 30; /* *UNDEFINED* */
15382 };
15383 
15384 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO10. */
15385 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO10_s ALT_SYSMGR_PINMUX_MIXED1IO10_t;
15386 #endif /* __ASSEMBLY__ */
15387 
15388 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO10 register from the beginning of the component. */
15389 #define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128
15390 
15391 /*
15392  * Register : nand_dq6 Mux Selection Register - MIXED1IO11
15393  *
15394  * This register is used to control the peripherals connected to nand_dq6
15395  *
15396  * Only reset by a cold reset (ignores warm reset).
15397  *
15398  * NOTE: These registers should not be modified after IO configuration.There is no
15399  * support for dynamically changing the Pin Mux selections.
15400  *
15401  * Register Layout
15402  *
15403  * Bits | Access | Reset | Description
15404  * :-------|:-------|:------|:-----------------------------
15405  * [1:0] | RW | 0x0 | nand_dq6 Mux Selection Field
15406  * [31:2] | ??? | 0x0 | *UNDEFINED*
15407  *
15408  */
15409 /*
15410  * Field : nand_dq6 Mux Selection Field - sel
15411  *
15412  * Select peripheral signals connected nand_dq6.
15413  *
15414  * 0 : Pin is connected to GPIO/LoanIO number 25.
15415  *
15416  * 1 : Pin is connected to Peripheral signal USB1.D7.
15417  *
15418  * 2 : Pin is connected to Peripheral signal RGMII1.RXD1.
15419  *
15420  * 3 : Pin is connected to Peripheral signal NAND.dq6.
15421  *
15422  * Field Access Macros:
15423  *
15424  */
15425 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15426 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0
15427 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15428 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1
15429 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15430 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2
15431 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */
15432 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003
15433 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value. */
15434 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc
15435 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field. */
15436 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0
15437 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO11_SEL field value from a register. */
15438 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
15439 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO11_SEL register field value suitable for setting the register. */
15440 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003)
15441 
15442 #ifndef __ASSEMBLY__
15443 /*
15444  * WARNING: The C register and register group struct declarations are provided for
15445  * convenience and illustrative purposes. They should, however, be used with
15446  * caution as the C language standard provides no guarantees about the alignment or
15447  * atomicity of device memory accesses. The recommended practice for writing
15448  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15449  * alt_write_word() functions.
15450  *
15451  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11.
15452  */
15453 struct ALT_SYSMGR_PINMUX_MIXED1IO11_s
15454 {
15455  uint32_t sel : 2; /* nand_dq6 Mux Selection Field */
15456  uint32_t : 30; /* *UNDEFINED* */
15457 };
15458 
15459 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO11. */
15460 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO11_s ALT_SYSMGR_PINMUX_MIXED1IO11_t;
15461 #endif /* __ASSEMBLY__ */
15462 
15463 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO11 register from the beginning of the component. */
15464 #define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c
15465 
15466 /*
15467  * Register : nand_dq7 Mux Selection Register - MIXED1IO12
15468  *
15469  * This register is used to control the peripherals connected to nand_dq7
15470  *
15471  * Only reset by a cold reset (ignores warm reset).
15472  *
15473  * NOTE: These registers should not be modified after IO configuration.There is no
15474  * support for dynamically changing the Pin Mux selections.
15475  *
15476  * Register Layout
15477  *
15478  * Bits | Access | Reset | Description
15479  * :-------|:-------|:------|:-----------------------------
15480  * [1:0] | RW | 0x0 | nand_dq7 Mux Selection Field
15481  * [31:2] | ??? | 0x0 | *UNDEFINED*
15482  *
15483  */
15484 /*
15485  * Field : nand_dq7 Mux Selection Field - sel
15486  *
15487  * Select peripheral signals connected nand_dq7.
15488  *
15489  * 0 : Pin is connected to GPIO/LoanIO number 26.
15490  *
15491  * 1 : Pin is connected to Peripheral signal not applicable.
15492  *
15493  * 2 : Pin is connected to Peripheral signal RGMII1.RXD2.
15494  *
15495  * 3 : Pin is connected to Peripheral signal NAND.dq7.
15496  *
15497  * Field Access Macros:
15498  *
15499  */
15500 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15501 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0
15502 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15503 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1
15504 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15505 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2
15506 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */
15507 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003
15508 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value. */
15509 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc
15510 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field. */
15511 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0
15512 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO12_SEL field value from a register. */
15513 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
15514 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO12_SEL register field value suitable for setting the register. */
15515 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003)
15516 
15517 #ifndef __ASSEMBLY__
15518 /*
15519  * WARNING: The C register and register group struct declarations are provided for
15520  * convenience and illustrative purposes. They should, however, be used with
15521  * caution as the C language standard provides no guarantees about the alignment or
15522  * atomicity of device memory accesses. The recommended practice for writing
15523  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15524  * alt_write_word() functions.
15525  *
15526  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12.
15527  */
15528 struct ALT_SYSMGR_PINMUX_MIXED1IO12_s
15529 {
15530  uint32_t sel : 2; /* nand_dq7 Mux Selection Field */
15531  uint32_t : 30; /* *UNDEFINED* */
15532 };
15533 
15534 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO12. */
15535 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO12_s ALT_SYSMGR_PINMUX_MIXED1IO12_t;
15536 #endif /* __ASSEMBLY__ */
15537 
15538 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO12 register from the beginning of the component. */
15539 #define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130
15540 
15541 /*
15542  * Register : nand_wp Mux Selection Register - MIXED1IO13
15543  *
15544  * This register is used to control the peripherals connected to nand_wp
15545  *
15546  * Only reset by a cold reset (ignores warm reset).
15547  *
15548  * NOTE: These registers should not be modified after IO configuration.There is no
15549  * support for dynamically changing the Pin Mux selections.
15550  *
15551  * Register Layout
15552  *
15553  * Bits | Access | Reset | Description
15554  * :-------|:-------|:------|:----------------------------
15555  * [1:0] | RW | 0x0 | nand_wp Mux Selection Field
15556  * [31:2] | ??? | 0x0 | *UNDEFINED*
15557  *
15558  */
15559 /*
15560  * Field : nand_wp Mux Selection Field - sel
15561  *
15562  * Select peripheral signals connected nand_wp.
15563  *
15564  * 0 : Pin is connected to GPIO/LoanIO number 27.
15565  *
15566  * 1 : Pin is connected to Peripheral signal QSPI.SS2.
15567  *
15568  * 2 : Pin is connected to Peripheral signal RGMII1.RXD3.
15569  *
15570  * 3 : Pin is connected to Peripheral signal NAND.wp.
15571  *
15572  * Field Access Macros:
15573  *
15574  */
15575 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15576 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0
15577 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15578 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1
15579 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15580 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2
15581 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */
15582 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003
15583 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value. */
15584 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc
15585 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field. */
15586 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0
15587 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO13_SEL field value from a register. */
15588 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
15589 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO13_SEL register field value suitable for setting the register. */
15590 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003)
15591 
15592 #ifndef __ASSEMBLY__
15593 /*
15594  * WARNING: The C register and register group struct declarations are provided for
15595  * convenience and illustrative purposes. They should, however, be used with
15596  * caution as the C language standard provides no guarantees about the alignment or
15597  * atomicity of device memory accesses. The recommended practice for writing
15598  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15599  * alt_write_word() functions.
15600  *
15601  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13.
15602  */
15603 struct ALT_SYSMGR_PINMUX_MIXED1IO13_s
15604 {
15605  uint32_t sel : 2; /* nand_wp Mux Selection Field */
15606  uint32_t : 30; /* *UNDEFINED* */
15607 };
15608 
15609 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO13. */
15610 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO13_s ALT_SYSMGR_PINMUX_MIXED1IO13_t;
15611 #endif /* __ASSEMBLY__ */
15612 
15613 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO13 register from the beginning of the component. */
15614 #define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134
15615 
15616 /*
15617  * Register : nand_we Mux Selection Register - MIXED1IO14
15618  *
15619  * This register is used to control the peripherals connected to nand_we
15620  *
15621  * Only reset by a cold reset (ignores warm reset).
15622  *
15623  * NOTE: These registers should not be modified after IO configuration.There is no
15624  * support for dynamically changing the Pin Mux selections.
15625  *
15626  * Register Layout
15627  *
15628  * Bits | Access | Reset | Description
15629  * :-------|:-------|:------|:----------------------------
15630  * [1:0] | RW | 0x0 | nand_we Mux Selection Field
15631  * [31:2] | ??? | 0x0 | *UNDEFINED*
15632  *
15633  */
15634 /*
15635  * Field : nand_we Mux Selection Field - sel
15636  *
15637  * Select peripheral signals connected nand_we.
15638  *
15639  * 0 : Pin is connected to GPIO/LoanIO number 28.
15640  *
15641  * 1 : Pin is connected to Peripheral signal not applicable.
15642  *
15643  * 2 : Pin is connected to Peripheral signal QSPI.SS1.
15644  *
15645  * 3 : Pin is connected to Peripheral signal NAND.we.
15646  *
15647  * Field Access Macros:
15648  *
15649  */
15650 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15651 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0
15652 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15653 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1
15654 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15655 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2
15656 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */
15657 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003
15658 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value. */
15659 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc
15660 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field. */
15661 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0
15662 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO14_SEL field value from a register. */
15663 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
15664 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO14_SEL register field value suitable for setting the register. */
15665 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003)
15666 
15667 #ifndef __ASSEMBLY__
15668 /*
15669  * WARNING: The C register and register group struct declarations are provided for
15670  * convenience and illustrative purposes. They should, however, be used with
15671  * caution as the C language standard provides no guarantees about the alignment or
15672  * atomicity of device memory accesses. The recommended practice for writing
15673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15674  * alt_write_word() functions.
15675  *
15676  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14.
15677  */
15678 struct ALT_SYSMGR_PINMUX_MIXED1IO14_s
15679 {
15680  uint32_t sel : 2; /* nand_we Mux Selection Field */
15681  uint32_t : 30; /* *UNDEFINED* */
15682 };
15683 
15684 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO14. */
15685 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO14_s ALT_SYSMGR_PINMUX_MIXED1IO14_t;
15686 #endif /* __ASSEMBLY__ */
15687 
15688 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO14 register from the beginning of the component. */
15689 #define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138
15690 
15691 /*
15692  * Register : qspi_io0 Mux Selection Register - MIXED1IO15
15693  *
15694  * This register is used to control the peripherals connected to qspi_io0
15695  *
15696  * Only reset by a cold reset (ignores warm reset).
15697  *
15698  * NOTE: These registers should not be modified after IO configuration.There is no
15699  * support for dynamically changing the Pin Mux selections.
15700  *
15701  * Register Layout
15702  *
15703  * Bits | Access | Reset | Description
15704  * :-------|:-------|:------|:-----------------------------
15705  * [1:0] | RW | 0x0 | qspi_io0 Mux Selection Field
15706  * [31:2] | ??? | 0x0 | *UNDEFINED*
15707  *
15708  */
15709 /*
15710  * Field : qspi_io0 Mux Selection Field - sel
15711  *
15712  * Select peripheral signals connected qspi_io0.
15713  *
15714  * 0 : Pin is connected to GPIO/LoanIO number 29.
15715  *
15716  * 1 : Pin is connected to Peripheral signal USB1.CLK.
15717  *
15718  * 2 : Pin is connected to Peripheral signal not applicable.
15719  *
15720  * 3 : Pin is connected to Peripheral signal QSPI.IO0.
15721  *
15722  * Field Access Macros:
15723  *
15724  */
15725 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15726 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0
15727 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15728 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1
15729 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15730 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2
15731 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */
15732 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003
15733 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value. */
15734 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc
15735 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field. */
15736 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0
15737 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO15_SEL field value from a register. */
15738 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
15739 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO15_SEL register field value suitable for setting the register. */
15740 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003)
15741 
15742 #ifndef __ASSEMBLY__
15743 /*
15744  * WARNING: The C register and register group struct declarations are provided for
15745  * convenience and illustrative purposes. They should, however, be used with
15746  * caution as the C language standard provides no guarantees about the alignment or
15747  * atomicity of device memory accesses. The recommended practice for writing
15748  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15749  * alt_write_word() functions.
15750  *
15751  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15.
15752  */
15753 struct ALT_SYSMGR_PINMUX_MIXED1IO15_s
15754 {
15755  uint32_t sel : 2; /* qspi_io0 Mux Selection Field */
15756  uint32_t : 30; /* *UNDEFINED* */
15757 };
15758 
15759 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO15. */
15760 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO15_s ALT_SYSMGR_PINMUX_MIXED1IO15_t;
15761 #endif /* __ASSEMBLY__ */
15762 
15763 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO15 register from the beginning of the component. */
15764 #define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c
15765 
15766 /*
15767  * Register : qspi_io1 Mux Selection Register - MIXED1IO16
15768  *
15769  * This register is used to control the peripherals connected to qspi_io1
15770  *
15771  * Only reset by a cold reset (ignores warm reset).
15772  *
15773  * NOTE: These registers should not be modified after IO configuration.There is no
15774  * support for dynamically changing the Pin Mux selections.
15775  *
15776  * Register Layout
15777  *
15778  * Bits | Access | Reset | Description
15779  * :-------|:-------|:------|:-----------------------------
15780  * [1:0] | RW | 0x0 | qspi_io1 Mux Selection Field
15781  * [31:2] | ??? | 0x0 | *UNDEFINED*
15782  *
15783  */
15784 /*
15785  * Field : qspi_io1 Mux Selection Field - sel
15786  *
15787  * Select peripheral signals connected qspi_io1.
15788  *
15789  * 0 : Pin is connected to GPIO/LoanIO number 30.
15790  *
15791  * 1 : Pin is connected to Peripheral signal USB1.STP.
15792  *
15793  * 2 : Pin is connected to Peripheral signal not applicable.
15794  *
15795  * 3 : Pin is connected to Peripheral signal QSPI.IO1.
15796  *
15797  * Field Access Macros:
15798  *
15799  */
15800 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15801 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0
15802 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15803 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1
15804 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15805 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2
15806 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */
15807 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003
15808 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value. */
15809 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc
15810 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field. */
15811 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0
15812 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO16_SEL field value from a register. */
15813 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
15814 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO16_SEL register field value suitable for setting the register. */
15815 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003)
15816 
15817 #ifndef __ASSEMBLY__
15818 /*
15819  * WARNING: The C register and register group struct declarations are provided for
15820  * convenience and illustrative purposes. They should, however, be used with
15821  * caution as the C language standard provides no guarantees about the alignment or
15822  * atomicity of device memory accesses. The recommended practice for writing
15823  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15824  * alt_write_word() functions.
15825  *
15826  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16.
15827  */
15828 struct ALT_SYSMGR_PINMUX_MIXED1IO16_s
15829 {
15830  uint32_t sel : 2; /* qspi_io1 Mux Selection Field */
15831  uint32_t : 30; /* *UNDEFINED* */
15832 };
15833 
15834 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO16. */
15835 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO16_s ALT_SYSMGR_PINMUX_MIXED1IO16_t;
15836 #endif /* __ASSEMBLY__ */
15837 
15838 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO16 register from the beginning of the component. */
15839 #define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140
15840 
15841 /*
15842  * Register : qspi_io2 Mux Selection Register - MIXED1IO17
15843  *
15844  * This register is used to control the peripherals connected to qspi_io2
15845  *
15846  * Only reset by a cold reset (ignores warm reset).
15847  *
15848  * NOTE: These registers should not be modified after IO configuration.There is no
15849  * support for dynamically changing the Pin Mux selections.
15850  *
15851  * Register Layout
15852  *
15853  * Bits | Access | Reset | Description
15854  * :-------|:-------|:------|:-----------------------------
15855  * [1:0] | RW | 0x0 | qspi_io2 Mux Selection Field
15856  * [31:2] | ??? | 0x0 | *UNDEFINED*
15857  *
15858  */
15859 /*
15860  * Field : qspi_io2 Mux Selection Field - sel
15861  *
15862  * Select peripheral signals connected qspi_io2.
15863  *
15864  * 0 : Pin is connected to GPIO/LoanIO number 31.
15865  *
15866  * 1 : Pin is connected to Peripheral signal USB1.DIR.
15867  *
15868  * 2 : Pin is connected to Peripheral signal not applicable.
15869  *
15870  * 3 : Pin is connected to Peripheral signal QSPI.IO2.
15871  *
15872  * Field Access Macros:
15873  *
15874  */
15875 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15876 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0
15877 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15878 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1
15879 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15880 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2
15881 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */
15882 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003
15883 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value. */
15884 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc
15885 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field. */
15886 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0
15887 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO17_SEL field value from a register. */
15888 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
15889 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO17_SEL register field value suitable for setting the register. */
15890 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003)
15891 
15892 #ifndef __ASSEMBLY__
15893 /*
15894  * WARNING: The C register and register group struct declarations are provided for
15895  * convenience and illustrative purposes. They should, however, be used with
15896  * caution as the C language standard provides no guarantees about the alignment or
15897  * atomicity of device memory accesses. The recommended practice for writing
15898  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15899  * alt_write_word() functions.
15900  *
15901  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17.
15902  */
15903 struct ALT_SYSMGR_PINMUX_MIXED1IO17_s
15904 {
15905  uint32_t sel : 2; /* qspi_io2 Mux Selection Field */
15906  uint32_t : 30; /* *UNDEFINED* */
15907 };
15908 
15909 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO17. */
15910 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO17_s ALT_SYSMGR_PINMUX_MIXED1IO17_t;
15911 #endif /* __ASSEMBLY__ */
15912 
15913 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO17 register from the beginning of the component. */
15914 #define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144
15915 
15916 /*
15917  * Register : qspi_io3 Mux Selection Register - MIXED1IO18
15918  *
15919  * This register is used to control the peripherals connected to qspi_io3
15920  *
15921  * Only reset by a cold reset (ignores warm reset).
15922  *
15923  * NOTE: These registers should not be modified after IO configuration.There is no
15924  * support for dynamically changing the Pin Mux selections.
15925  *
15926  * Register Layout
15927  *
15928  * Bits | Access | Reset | Description
15929  * :-------|:-------|:------|:-----------------------------
15930  * [1:0] | RW | 0x0 | qspi_io3 Mux Selection Field
15931  * [31:2] | ??? | 0x0 | *UNDEFINED*
15932  *
15933  */
15934 /*
15935  * Field : qspi_io3 Mux Selection Field - sel
15936  *
15937  * Select peripheral signals connected qspi_io3.
15938  *
15939  * 0 : Pin is connected to GPIO/LoanIO number 32.
15940  *
15941  * 1 : Pin is connected to Peripheral signal USB1.NXT.
15942  *
15943  * 2 : Pin is connected to Peripheral signal not applicable.
15944  *
15945  * 3 : Pin is connected to Peripheral signal QSPI.IO3.
15946  *
15947  * Field Access Macros:
15948  *
15949  */
15950 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15951 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0
15952 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15953 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1
15954 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15955 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2
15956 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */
15957 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003
15958 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value. */
15959 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc
15960 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field. */
15961 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0
15962 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO18_SEL field value from a register. */
15963 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
15964 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO18_SEL register field value suitable for setting the register. */
15965 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003)
15966 
15967 #ifndef __ASSEMBLY__
15968 /*
15969  * WARNING: The C register and register group struct declarations are provided for
15970  * convenience and illustrative purposes. They should, however, be used with
15971  * caution as the C language standard provides no guarantees about the alignment or
15972  * atomicity of device memory accesses. The recommended practice for writing
15973  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
15974  * alt_write_word() functions.
15975  *
15976  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18.
15977  */
15978 struct ALT_SYSMGR_PINMUX_MIXED1IO18_s
15979 {
15980  uint32_t sel : 2; /* qspi_io3 Mux Selection Field */
15981  uint32_t : 30; /* *UNDEFINED* */
15982 };
15983 
15984 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO18. */
15985 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO18_s ALT_SYSMGR_PINMUX_MIXED1IO18_t;
15986 #endif /* __ASSEMBLY__ */
15987 
15988 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO18 register from the beginning of the component. */
15989 #define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148
15990 
15991 /*
15992  * Register : qspi_ss0 Mux Selection Register - MIXED1IO19
15993  *
15994  * This register is used to control the peripherals connected to qspi_ss0
15995  *
15996  * Only reset by a cold reset (ignores warm reset).
15997  *
15998  * NOTE: These registers should not be modified after IO configuration.There is no
15999  * support for dynamically changing the Pin Mux selections.
16000  *
16001  * Register Layout
16002  *
16003  * Bits | Access | Reset | Description
16004  * :-------|:-------|:------|:-----------------------------
16005  * [1:0] | RW | 0x0 | qspi_ss0 Mux Selection Field
16006  * [31:2] | ??? | 0x0 | *UNDEFINED*
16007  *
16008  */
16009 /*
16010  * Field : qspi_ss0 Mux Selection Field - sel
16011  *
16012  * Select peripheral signals connected qspi_ss0.
16013  *
16014  * 0 : Pin is connected to GPIO/LoanIO number 33.
16015  *
16016  * 1 : Pin is connected to Peripheral signal not applicable.
16017  *
16018  * 2 : Pin is connected to Peripheral signal not applicable.
16019  *
16020  * 3 : Pin is connected to Peripheral signal QSPI.SS0.
16021  *
16022  * Field Access Macros:
16023  *
16024  */
16025 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16026 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0
16027 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16028 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1
16029 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16030 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2
16031 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */
16032 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003
16033 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value. */
16034 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc
16035 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field. */
16036 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0
16037 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO19_SEL field value from a register. */
16038 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
16039 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO19_SEL register field value suitable for setting the register. */
16040 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003)
16041 
16042 #ifndef __ASSEMBLY__
16043 /*
16044  * WARNING: The C register and register group struct declarations are provided for
16045  * convenience and illustrative purposes. They should, however, be used with
16046  * caution as the C language standard provides no guarantees about the alignment or
16047  * atomicity of device memory accesses. The recommended practice for writing
16048  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16049  * alt_write_word() functions.
16050  *
16051  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19.
16052  */
16053 struct ALT_SYSMGR_PINMUX_MIXED1IO19_s
16054 {
16055  uint32_t sel : 2; /* qspi_ss0 Mux Selection Field */
16056  uint32_t : 30; /* *UNDEFINED* */
16057 };
16058 
16059 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO19. */
16060 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO19_s ALT_SYSMGR_PINMUX_MIXED1IO19_t;
16061 #endif /* __ASSEMBLY__ */
16062 
16063 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO19 register from the beginning of the component. */
16064 #define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c
16065 
16066 /*
16067  * Register : qpsi_clk Mux Selection Register - MIXED1IO20
16068  *
16069  * This register is used to control the peripherals connected to qpsi_clk
16070  *
16071  * Only reset by a cold reset (ignores warm reset).
16072  *
16073  * NOTE: These registers should not be modified after IO configuration.There is no
16074  * support for dynamically changing the Pin Mux selections.
16075  *
16076  * Register Layout
16077  *
16078  * Bits | Access | Reset | Description
16079  * :-------|:-------|:------|:-----------------------------
16080  * [1:0] | RW | 0x0 | qpsi_clk Mux Selection Field
16081  * [31:2] | ??? | 0x0 | *UNDEFINED*
16082  *
16083  */
16084 /*
16085  * Field : qpsi_clk Mux Selection Field - sel
16086  *
16087  * Select peripheral signals connected qpsi_clk.
16088  *
16089  * 0 : Pin is connected to GPIO/LoanIO number 34.
16090  *
16091  * 1 : Pin is connected to Peripheral signal not applicable.
16092  *
16093  * 2 : Pin is connected to Peripheral signal not applicable.
16094  *
16095  * 3 : Pin is connected to Peripheral signal QSPI.CLK.
16096  *
16097  * Field Access Macros:
16098  *
16099  */
16100 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16101 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0
16102 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16103 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1
16104 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16105 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2
16106 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */
16107 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003
16108 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value. */
16109 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc
16110 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field. */
16111 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0
16112 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO20_SEL field value from a register. */
16113 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
16114 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO20_SEL register field value suitable for setting the register. */
16115 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003)
16116 
16117 #ifndef __ASSEMBLY__
16118 /*
16119  * WARNING: The C register and register group struct declarations are provided for
16120  * convenience and illustrative purposes. They should, however, be used with
16121  * caution as the C language standard provides no guarantees about the alignment or
16122  * atomicity of device memory accesses. The recommended practice for writing
16123  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16124  * alt_write_word() functions.
16125  *
16126  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20.
16127  */
16128 struct ALT_SYSMGR_PINMUX_MIXED1IO20_s
16129 {
16130  uint32_t sel : 2; /* qpsi_clk Mux Selection Field */
16131  uint32_t : 30; /* *UNDEFINED* */
16132 };
16133 
16134 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO20. */
16135 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO20_s ALT_SYSMGR_PINMUX_MIXED1IO20_t;
16136 #endif /* __ASSEMBLY__ */
16137 
16138 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO20 register from the beginning of the component. */
16139 #define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150
16140 
16141 /*
16142  * Register : qspi_ss1 Mux Selection Register - MIXED1IO21
16143  *
16144  * This register is used to control the peripherals connected to qspi_ss1
16145  *
16146  * Only reset by a cold reset (ignores warm reset).
16147  *
16148  * NOTE: These registers should not be modified after IO configuration.There is no
16149  * support for dynamically changing the Pin Mux selections.
16150  *
16151  * Register Layout
16152  *
16153  * Bits | Access | Reset | Description
16154  * :-------|:-------|:------|:-----------------------------
16155  * [1:0] | RW | 0x0 | qspi_ss1 Mux Selection Field
16156  * [31:2] | ??? | 0x0 | *UNDEFINED*
16157  *
16158  */
16159 /*
16160  * Field : qspi_ss1 Mux Selection Field - sel
16161  *
16162  * Select peripheral signals connected qspi_ss1.
16163  *
16164  * 0 : Pin is connected to GPIO/LoanIO number 35.
16165  *
16166  * 1 : Pin is connected to Peripheral signal not applicable.
16167  *
16168  * 2 : Pin is connected to Peripheral signal not applicable.
16169  *
16170  * 3 : Pin is connected to Peripheral signal QSPI.SS1.
16171  *
16172  * Field Access Macros:
16173  *
16174  */
16175 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16176 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0
16177 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16178 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1
16179 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16180 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2
16181 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */
16182 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003
16183 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value. */
16184 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc
16185 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field. */
16186 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0
16187 /* Extracts the ALT_SYSMGR_PINMUX_MIXED1IO21_SEL field value from a register. */
16188 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
16189 /* Produces a ALT_SYSMGR_PINMUX_MIXED1IO21_SEL register field value suitable for setting the register. */
16190 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003)
16191 
16192 #ifndef __ASSEMBLY__
16193 /*
16194  * WARNING: The C register and register group struct declarations are provided for
16195  * convenience and illustrative purposes. They should, however, be used with
16196  * caution as the C language standard provides no guarantees about the alignment or
16197  * atomicity of device memory accesses. The recommended practice for writing
16198  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16199  * alt_write_word() functions.
16200  *
16201  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21.
16202  */
16203 struct ALT_SYSMGR_PINMUX_MIXED1IO21_s
16204 {
16205  uint32_t sel : 2; /* qspi_ss1 Mux Selection Field */
16206  uint32_t : 30; /* *UNDEFINED* */
16207 };
16208 
16209 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED1IO21. */
16210 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED1IO21_s ALT_SYSMGR_PINMUX_MIXED1IO21_t;
16211 #endif /* __ASSEMBLY__ */
16212 
16213 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED1IO21 register from the beginning of the component. */
16214 #define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154
16215 
16216 /*
16217  * Register : emac1_mdio Mux Selection Register - MIXED2IO0
16218  *
16219  * This register is used to control the peripherals connected to emac1_mdio
16220  *
16221  * Only reset by a cold reset (ignores warm reset).
16222  *
16223  * NOTE: These registers should not be modified after IO configuration.There is no
16224  * support for dynamically changing the Pin Mux selections.
16225  *
16226  * Register Layout
16227  *
16228  * Bits | Access | Reset | Description
16229  * :-------|:-------|:------|:-------------------------------
16230  * [1:0] | RW | 0x0 | emac1_mdio Mux Selection Field
16231  * [31:2] | ??? | 0x0 | *UNDEFINED*
16232  *
16233  */
16234 /*
16235  * Field : emac1_mdio Mux Selection Field - sel
16236  *
16237  * Select peripheral signals connected emac1_mdio.
16238  *
16239  * 0 : Pin is connected to GPIO/LoanIO number 54.
16240  *
16241  * 1 : Pin is connected to Peripheral signal SPIS0.CLK.
16242  *
16243  * 2 : Pin is connected to Peripheral signal SPIM0.CLK.
16244  *
16245  * 3 : Pin is connected to Peripheral signal RGMII1.MDIO.
16246  *
16247  * Field Access Macros:
16248  *
16249  */
16250 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16251 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0
16252 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16253 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1
16254 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16255 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2
16256 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */
16257 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003
16258 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value. */
16259 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc
16260 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field. */
16261 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0
16262 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO0_SEL field value from a register. */
16263 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
16264 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO0_SEL register field value suitable for setting the register. */
16265 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
16266 
16267 #ifndef __ASSEMBLY__
16268 /*
16269  * WARNING: The C register and register group struct declarations are provided for
16270  * convenience and illustrative purposes. They should, however, be used with
16271  * caution as the C language standard provides no guarantees about the alignment or
16272  * atomicity of device memory accesses. The recommended practice for writing
16273  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16274  * alt_write_word() functions.
16275  *
16276  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0.
16277  */
16278 struct ALT_SYSMGR_PINMUX_MIXED2IO0_s
16279 {
16280  uint32_t sel : 2; /* emac1_mdio Mux Selection Field */
16281  uint32_t : 30; /* *UNDEFINED* */
16282 };
16283 
16284 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO0. */
16285 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO0_s ALT_SYSMGR_PINMUX_MIXED2IO0_t;
16286 #endif /* __ASSEMBLY__ */
16287 
16288 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO0 register from the beginning of the component. */
16289 #define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158
16290 
16291 /*
16292  * Register : emac1_mdc Mux Selection Register - MIXED2IO1
16293  *
16294  * This register is used to control the peripherals connected to emac1_mdc
16295  *
16296  * Only reset by a cold reset (ignores warm reset).
16297  *
16298  * NOTE: These registers should not be modified after IO configuration.There is no
16299  * support for dynamically changing the Pin Mux selections.
16300  *
16301  * Register Layout
16302  *
16303  * Bits | Access | Reset | Description
16304  * :-------|:-------|:------|:------------------------------
16305  * [1:0] | RW | 0x0 | emac1_mdc Mux Selection Field
16306  * [31:2] | ??? | 0x0 | *UNDEFINED*
16307  *
16308  */
16309 /*
16310  * Field : emac1_mdc Mux Selection Field - sel
16311  *
16312  * Select peripheral signals connected emac1_mdc.
16313  *
16314  * 0 : Pin is connected to GPIO/LoanIO number 55.
16315  *
16316  * 1 : Pin is connected to Peripheral signal SPIS0.MOSI.
16317  *
16318  * 2 : Pin is connected to Peripheral signal SPIM0.MOSI.
16319  *
16320  * 3 : Pin is connected to Peripheral signal RGMII1.MDC.
16321  *
16322  * Field Access Macros:
16323  *
16324  */
16325 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16326 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0
16327 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16328 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1
16329 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16330 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2
16331 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */
16332 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003
16333 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value. */
16334 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc
16335 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field. */
16336 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0
16337 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO1_SEL field value from a register. */
16338 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
16339 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO1_SEL register field value suitable for setting the register. */
16340 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
16341 
16342 #ifndef __ASSEMBLY__
16343 /*
16344  * WARNING: The C register and register group struct declarations are provided for
16345  * convenience and illustrative purposes. They should, however, be used with
16346  * caution as the C language standard provides no guarantees about the alignment or
16347  * atomicity of device memory accesses. The recommended practice for writing
16348  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16349  * alt_write_word() functions.
16350  *
16351  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1.
16352  */
16353 struct ALT_SYSMGR_PINMUX_MIXED2IO1_s
16354 {
16355  uint32_t sel : 2; /* emac1_mdc Mux Selection Field */
16356  uint32_t : 30; /* *UNDEFINED* */
16357 };
16358 
16359 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO1. */
16360 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO1_s ALT_SYSMGR_PINMUX_MIXED2IO1_t;
16361 #endif /* __ASSEMBLY__ */
16362 
16363 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO1 register from the beginning of the component. */
16364 #define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c
16365 
16366 /*
16367  * Register : emac1_tx_d2 Mux Selection Register - MIXED2IO2
16368  *
16369  * This register is used to control the peripherals connected to emac1_tx_d2
16370  *
16371  * Only reset by a cold reset (ignores warm reset).
16372  *
16373  * NOTE: These registers should not be modified after IO configuration.There is no
16374  * support for dynamically changing the Pin Mux selections.
16375  *
16376  * Register Layout
16377  *
16378  * Bits | Access | Reset | Description
16379  * :-------|:-------|:------|:--------------------------------
16380  * [1:0] | RW | 0x0 | emac1_tx_d2 Mux Selection Field
16381  * [31:2] | ??? | 0x0 | *UNDEFINED*
16382  *
16383  */
16384 /*
16385  * Field : emac1_tx_d2 Mux Selection Field - sel
16386  *
16387  * Select peripheral signals connected emac1_tx_d2.
16388  *
16389  * 0 : Pin is connected to GPIO/LoanIO number 56.
16390  *
16391  * 1 : Pin is connected to Peripheral signal SPIS0.MISO.
16392  *
16393  * 2 : Pin is connected to Peripheral signal SPIM0.MISO.
16394  *
16395  * 3 : Pin is connected to Peripheral signal RGMII1.TXD2.
16396  *
16397  * Field Access Macros:
16398  *
16399  */
16400 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16401 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0
16402 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16403 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1
16404 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16405 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2
16406 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */
16407 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003
16408 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value. */
16409 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc
16410 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field. */
16411 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0
16412 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO2_SEL field value from a register. */
16413 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
16414 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO2_SEL register field value suitable for setting the register. */
16415 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
16416 
16417 #ifndef __ASSEMBLY__
16418 /*
16419  * WARNING: The C register and register group struct declarations are provided for
16420  * convenience and illustrative purposes. They should, however, be used with
16421  * caution as the C language standard provides no guarantees about the alignment or
16422  * atomicity of device memory accesses. The recommended practice for writing
16423  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16424  * alt_write_word() functions.
16425  *
16426  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2.
16427  */
16428 struct ALT_SYSMGR_PINMUX_MIXED2IO2_s
16429 {
16430  uint32_t sel : 2; /* emac1_tx_d2 Mux Selection Field */
16431  uint32_t : 30; /* *UNDEFINED* */
16432 };
16433 
16434 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO2. */
16435 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO2_s ALT_SYSMGR_PINMUX_MIXED2IO2_t;
16436 #endif /* __ASSEMBLY__ */
16437 
16438 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO2 register from the beginning of the component. */
16439 #define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160
16440 
16441 /*
16442  * Register : emac1_tx_d3 Mux Selection Register - MIXED2IO3
16443  *
16444  * This register is used to control the peripherals connected to emac1_tx_d3
16445  *
16446  * Only reset by a cold reset (ignores warm reset).
16447  *
16448  * NOTE: These registers should not be modified after IO configuration.There is no
16449  * support for dynamically changing the Pin Mux selections.
16450  *
16451  * Register Layout
16452  *
16453  * Bits | Access | Reset | Description
16454  * :-------|:-------|:------|:--------------------------------
16455  * [1:0] | RW | 0x0 | emac1_tx_d3 Mux Selection Field
16456  * [31:2] | ??? | 0x0 | *UNDEFINED*
16457  *
16458  */
16459 /*
16460  * Field : emac1_tx_d3 Mux Selection Field - sel
16461  *
16462  * Select peripheral signals connected emac1_tx_d3.
16463  *
16464  * 0 : Pin is connected to GPIO/LoanIO number 57.
16465  *
16466  * 1 : Pin is connected to Peripheral signal SPIS0.SS0.
16467  *
16468  * 2 : Pin is connected to Peripheral signal SPIM0.SS0.
16469  *
16470  * 3 : Pin is connected to Peripheral signal RGMII1.TXD3.
16471  *
16472  * Field Access Macros:
16473  *
16474  */
16475 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16476 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0
16477 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16478 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1
16479 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16480 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2
16481 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */
16482 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003
16483 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value. */
16484 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc
16485 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field. */
16486 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0
16487 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO3_SEL field value from a register. */
16488 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
16489 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO3_SEL register field value suitable for setting the register. */
16490 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
16491 
16492 #ifndef __ASSEMBLY__
16493 /*
16494  * WARNING: The C register and register group struct declarations are provided for
16495  * convenience and illustrative purposes. They should, however, be used with
16496  * caution as the C language standard provides no guarantees about the alignment or
16497  * atomicity of device memory accesses. The recommended practice for writing
16498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16499  * alt_write_word() functions.
16500  *
16501  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3.
16502  */
16503 struct ALT_SYSMGR_PINMUX_MIXED2IO3_s
16504 {
16505  uint32_t sel : 2; /* emac1_tx_d3 Mux Selection Field */
16506  uint32_t : 30; /* *UNDEFINED* */
16507 };
16508 
16509 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO3. */
16510 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO3_s ALT_SYSMGR_PINMUX_MIXED2IO3_t;
16511 #endif /* __ASSEMBLY__ */
16512 
16513 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO3 register from the beginning of the component. */
16514 #define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164
16515 
16516 /*
16517  * Register : emac1_rx_clk Mux Selection Register - MIXED2IO4
16518  *
16519  * This register is used to control the peripherals connected to emac1_rx_clk
16520  *
16521  * Only reset by a cold reset (ignores warm reset).
16522  *
16523  * NOTE: These registers should not be modified after IO configuration.There is no
16524  * support for dynamically changing the Pin Mux selections.
16525  *
16526  * Register Layout
16527  *
16528  * Bits | Access | Reset | Description
16529  * :-------|:-------|:------|:---------------------------------
16530  * [1:0] | RW | 0x0 | emac1_rx_clk Mux Selection Field
16531  * [31:2] | ??? | 0x0 | *UNDEFINED*
16532  *
16533  */
16534 /*
16535  * Field : emac1_rx_clk Mux Selection Field - sel
16536  *
16537  * Select peripheral signals connected emac1_rx_clk.
16538  *
16539  * 0 : Pin is connected to GPIO/LoanIO number 58.
16540  *
16541  * 1 : Pin is connected to Peripheral signal SPIM1.CLK.
16542  *
16543  * 2 : Pin is connected to Peripheral signal SPIS1.CLK.
16544  *
16545  * 3 : Pin is connected to Peripheral signal RGMII1.RX_CLK.
16546  *
16547  * Field Access Macros:
16548  *
16549  */
16550 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16551 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0
16552 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16553 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1
16554 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16555 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2
16556 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */
16557 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003
16558 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value. */
16559 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc
16560 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field. */
16561 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0
16562 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO4_SEL field value from a register. */
16563 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
16564 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO4_SEL register field value suitable for setting the register. */
16565 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
16566 
16567 #ifndef __ASSEMBLY__
16568 /*
16569  * WARNING: The C register and register group struct declarations are provided for
16570  * convenience and illustrative purposes. They should, however, be used with
16571  * caution as the C language standard provides no guarantees about the alignment or
16572  * atomicity of device memory accesses. The recommended practice for writing
16573  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16574  * alt_write_word() functions.
16575  *
16576  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4.
16577  */
16578 struct ALT_SYSMGR_PINMUX_MIXED2IO4_s
16579 {
16580  uint32_t sel : 2; /* emac1_rx_clk Mux Selection Field */
16581  uint32_t : 30; /* *UNDEFINED* */
16582 };
16583 
16584 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO4. */
16585 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO4_s ALT_SYSMGR_PINMUX_MIXED2IO4_t;
16586 #endif /* __ASSEMBLY__ */
16587 
16588 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO4 register from the beginning of the component. */
16589 #define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168
16590 
16591 /*
16592  * Register : emac1_rx_ctl Mux Selection Register - MIXED2IO5
16593  *
16594  * This register is used to control the peripherals connected to emac1_rx_ctl
16595  *
16596  * Only reset by a cold reset (ignores warm reset).
16597  *
16598  * NOTE: These registers should not be modified after IO configuration.There is no
16599  * support for dynamically changing the Pin Mux selections.
16600  *
16601  * Register Layout
16602  *
16603  * Bits | Access | Reset | Description
16604  * :-------|:-------|:------|:---------------------------------
16605  * [1:0] | RW | 0x0 | emac1_rx_ctl Mux Selection Field
16606  * [31:2] | ??? | 0x0 | *UNDEFINED*
16607  *
16608  */
16609 /*
16610  * Field : emac1_rx_ctl Mux Selection Field - sel
16611  *
16612  * Select peripheral signals connected emac1_rx_ctl.
16613  *
16614  * 0 : Pin is connected to GPIO/LoanIO number 59.
16615  *
16616  * 1 : Pin is connected to Peripheral signal SPIM1.MOSI.
16617  *
16618  * 2 : Pin is connected to Peripheral signal SPIS1.MOSI.
16619  *
16620  * 3 : Pin is connected to Peripheral signal RGMII1.RX_CTL.
16621  *
16622  * Field Access Macros:
16623  *
16624  */
16625 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16626 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0
16627 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16628 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1
16629 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16630 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2
16631 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */
16632 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003
16633 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value. */
16634 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc
16635 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field. */
16636 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0
16637 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO5_SEL field value from a register. */
16638 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
16639 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO5_SEL register field value suitable for setting the register. */
16640 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
16641 
16642 #ifndef __ASSEMBLY__
16643 /*
16644  * WARNING: The C register and register group struct declarations are provided for
16645  * convenience and illustrative purposes. They should, however, be used with
16646  * caution as the C language standard provides no guarantees about the alignment or
16647  * atomicity of device memory accesses. The recommended practice for writing
16648  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16649  * alt_write_word() functions.
16650  *
16651  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5.
16652  */
16653 struct ALT_SYSMGR_PINMUX_MIXED2IO5_s
16654 {
16655  uint32_t sel : 2; /* emac1_rx_ctl Mux Selection Field */
16656  uint32_t : 30; /* *UNDEFINED* */
16657 };
16658 
16659 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO5. */
16660 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO5_s ALT_SYSMGR_PINMUX_MIXED2IO5_t;
16661 #endif /* __ASSEMBLY__ */
16662 
16663 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO5 register from the beginning of the component. */
16664 #define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c
16665 
16666 /*
16667  * Register : emac1_rx_d2 Mux Selection Register - MIXED2IO6
16668  *
16669  * This register is used to control the peripherals connected to emac1_rx_d2
16670  *
16671  * Only reset by a cold reset (ignores warm reset).
16672  *
16673  * NOTE: These registers should not be modified after IO configuration.There is no
16674  * support for dynamically changing the Pin Mux selections.
16675  *
16676  * Register Layout
16677  *
16678  * Bits | Access | Reset | Description
16679  * :-------|:-------|:------|:--------------------------------
16680  * [1:0] | RW | 0x0 | emac1_rx_d2 Mux Selection Field
16681  * [31:2] | ??? | 0x0 | *UNDEFINED*
16682  *
16683  */
16684 /*
16685  * Field : emac1_rx_d2 Mux Selection Field - sel
16686  *
16687  * Select peripheral signals connected emac1_rx_d2.
16688  *
16689  * 0 : Pin is connected to GPIO/LoanIO number 60.
16690  *
16691  * 1 : Pin is connected to Peripheral signal SPIM1.MISO.
16692  *
16693  * 2 : Pin is connected to Peripheral signal SPIS1.MISO.
16694  *
16695  * 3 : Pin is connected to Peripheral signal RGMII1.RXD2.
16696  *
16697  * Field Access Macros:
16698  *
16699  */
16700 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16701 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0
16702 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16703 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1
16704 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16705 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2
16706 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */
16707 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003
16708 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value. */
16709 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc
16710 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field. */
16711 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0
16712 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO6_SEL field value from a register. */
16713 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
16714 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO6_SEL register field value suitable for setting the register. */
16715 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
16716 
16717 #ifndef __ASSEMBLY__
16718 /*
16719  * WARNING: The C register and register group struct declarations are provided for
16720  * convenience and illustrative purposes. They should, however, be used with
16721  * caution as the C language standard provides no guarantees about the alignment or
16722  * atomicity of device memory accesses. The recommended practice for writing
16723  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16724  * alt_write_word() functions.
16725  *
16726  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6.
16727  */
16728 struct ALT_SYSMGR_PINMUX_MIXED2IO6_s
16729 {
16730  uint32_t sel : 2; /* emac1_rx_d2 Mux Selection Field */
16731  uint32_t : 30; /* *UNDEFINED* */
16732 };
16733 
16734 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO6. */
16735 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO6_s ALT_SYSMGR_PINMUX_MIXED2IO6_t;
16736 #endif /* __ASSEMBLY__ */
16737 
16738 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO6 register from the beginning of the component. */
16739 #define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170
16740 
16741 /*
16742  * Register : emac1_rx_d3 Mux Selection Register - MIXED2IO7
16743  *
16744  * This register is used to control the peripherals connected to emac1_rx_d3
16745  *
16746  * Only reset by a cold reset (ignores warm reset).
16747  *
16748  * NOTE: These registers should not be modified after IO configuration.There is no
16749  * support for dynamically changing the Pin Mux selections.
16750  *
16751  * Register Layout
16752  *
16753  * Bits | Access | Reset | Description
16754  * :-------|:-------|:------|:--------------------------------
16755  * [1:0] | RW | 0x0 | emac1_rx_d3 Mux Selection Field
16756  * [31:2] | ??? | 0x0 | *UNDEFINED*
16757  *
16758  */
16759 /*
16760  * Field : emac1_rx_d3 Mux Selection Field - sel
16761  *
16762  * Select peripheral signals connected emac1_rx_d3.
16763  *
16764  * 0 : Pin is connected to GPIO/LoanIO number 61.
16765  *
16766  * 1 : Pin is connected to Peripheral signal SPIM1.SS0.
16767  *
16768  * 2 : Pin is connected to Peripheral signal SPIS1.SS0.
16769  *
16770  * 3 : Pin is connected to Peripheral signal RGMII1.RXD3.
16771  *
16772  * Field Access Macros:
16773  *
16774  */
16775 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16776 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0
16777 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16778 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1
16779 /* The width in bits of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16780 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2
16781 /* The mask used to set the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */
16782 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003
16783 /* The mask used to clear the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value. */
16784 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc
16785 /* The reset value of the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field. */
16786 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0
16787 /* Extracts the ALT_SYSMGR_PINMUX_MIXED2IO7_SEL field value from a register. */
16788 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
16789 /* Produces a ALT_SYSMGR_PINMUX_MIXED2IO7_SEL register field value suitable for setting the register. */
16790 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
16791 
16792 #ifndef __ASSEMBLY__
16793 /*
16794  * WARNING: The C register and register group struct declarations are provided for
16795  * convenience and illustrative purposes. They should, however, be used with
16796  * caution as the C language standard provides no guarantees about the alignment or
16797  * atomicity of device memory accesses. The recommended practice for writing
16798  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16799  * alt_write_word() functions.
16800  *
16801  * The struct declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7.
16802  */
16803 struct ALT_SYSMGR_PINMUX_MIXED2IO7_s
16804 {
16805  uint32_t sel : 2; /* emac1_rx_d3 Mux Selection Field */
16806  uint32_t : 30; /* *UNDEFINED* */
16807 };
16808 
16809 /* The typedef declaration for register ALT_SYSMGR_PINMUX_MIXED2IO7. */
16810 typedef volatile struct ALT_SYSMGR_PINMUX_MIXED2IO7_s ALT_SYSMGR_PINMUX_MIXED2IO7_t;
16811 #endif /* __ASSEMBLY__ */
16812 
16813 /* The byte offset of the ALT_SYSMGR_PINMUX_MIXED2IO7 register from the beginning of the component. */
16814 #define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174
16815 
16816 /*
16817  * Register : GPIO/LoanIO 48 Input Mux Selection Register - GPLINMUX48
16818  *
16819  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16820  * the input signal for GPIO/LoanIO 48.
16821  *
16822  * Only reset by a cold reset (ignores warm reset).
16823  *
16824  * NOTE: These registers should not be modified after IO configuration.There is no
16825  * support for dynamically changing the Pin Mux selections.
16826  *
16827  * Register Layout
16828  *
16829  * Bits | Access | Reset | Description
16830  * :-------|:-------|:------|:----------------------------------------
16831  * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field
16832  * [31:1] | ??? | 0x0 | *UNDEFINED*
16833  *
16834  */
16835 /*
16836  * Field : GPIO/Loan IO48Input Mux Selection Field - sel
16837  *
16838  * Select source for GPIO/LoanIO 48.
16839  *
16840  * 0 : Source for GPIO/LoanIO 48 is GENERALIO0.
16841  *
16842  * 1 : Source for GPIO/LoanIO 48 is EMACIO14.
16843  *
16844  * Field Access Macros:
16845  *
16846  */
16847 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16848 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0
16849 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16850 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0
16851 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16852 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1
16853 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */
16854 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001
16855 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value. */
16856 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe
16857 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field. */
16858 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0
16859 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX48_SEL field value from a register. */
16860 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
16861 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX48_SEL register field value suitable for setting the register. */
16862 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
16863 
16864 #ifndef __ASSEMBLY__
16865 /*
16866  * WARNING: The C register and register group struct declarations are provided for
16867  * convenience and illustrative purposes. They should, however, be used with
16868  * caution as the C language standard provides no guarantees about the alignment or
16869  * atomicity of device memory accesses. The recommended practice for writing
16870  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16871  * alt_write_word() functions.
16872  *
16873  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48.
16874  */
16875 struct ALT_SYSMGR_PINMUX_GPLINMUX48_s
16876 {
16877  uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */
16878  uint32_t : 31; /* *UNDEFINED* */
16879 };
16880 
16881 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX48. */
16882 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX48_s ALT_SYSMGR_PINMUX_GPLINMUX48_t;
16883 #endif /* __ASSEMBLY__ */
16884 
16885 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX48 register from the beginning of the component. */
16886 #define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178
16887 
16888 /*
16889  * Register : GPIO/LoanIO 49 Input Mux Selection Register - GPLINMUX49
16890  *
16891  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16892  * the input signal for GPIO/LoanIO 49.
16893  *
16894  * Only reset by a cold reset (ignores warm reset).
16895  *
16896  * NOTE: These registers should not be modified after IO configuration.There is no
16897  * support for dynamically changing the Pin Mux selections.
16898  *
16899  * Register Layout
16900  *
16901  * Bits | Access | Reset | Description
16902  * :-------|:-------|:------|:----------------------------------------
16903  * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field
16904  * [31:1] | ??? | 0x0 | *UNDEFINED*
16905  *
16906  */
16907 /*
16908  * Field : GPIO/Loan IO49Input Mux Selection Field - sel
16909  *
16910  * Select source for GPIO/LoanIO 49.
16911  *
16912  * 0 : Source for GPIO/LoanIO 49 is GENERALIO1.
16913  *
16914  * 1 : Source for GPIO/LoanIO 49 is EMACIO15.
16915  *
16916  * Field Access Macros:
16917  *
16918  */
16919 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16920 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0
16921 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16922 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0
16923 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16924 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1
16925 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */
16926 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001
16927 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value. */
16928 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe
16929 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field. */
16930 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0
16931 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX49_SEL field value from a register. */
16932 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
16933 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX49_SEL register field value suitable for setting the register. */
16934 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
16935 
16936 #ifndef __ASSEMBLY__
16937 /*
16938  * WARNING: The C register and register group struct declarations are provided for
16939  * convenience and illustrative purposes. They should, however, be used with
16940  * caution as the C language standard provides no guarantees about the alignment or
16941  * atomicity of device memory accesses. The recommended practice for writing
16942  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
16943  * alt_write_word() functions.
16944  *
16945  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49.
16946  */
16947 struct ALT_SYSMGR_PINMUX_GPLINMUX49_s
16948 {
16949  uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */
16950  uint32_t : 31; /* *UNDEFINED* */
16951 };
16952 
16953 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX49. */
16954 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX49_s ALT_SYSMGR_PINMUX_GPLINMUX49_t;
16955 #endif /* __ASSEMBLY__ */
16956 
16957 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX49 register from the beginning of the component. */
16958 #define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c
16959 
16960 /*
16961  * Register : GPIO/LoanIO 50 Input Mux Selection Register - GPLINMUX50
16962  *
16963  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
16964  * the input signal for GPIO/LoanIO 50.
16965  *
16966  * Only reset by a cold reset (ignores warm reset).
16967  *
16968  * NOTE: These registers should not be modified after IO configuration.There is no
16969  * support for dynamically changing the Pin Mux selections.
16970  *
16971  * Register Layout
16972  *
16973  * Bits | Access | Reset | Description
16974  * :-------|:-------|:------|:----------------------------------------
16975  * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field
16976  * [31:1] | ??? | 0x0 | *UNDEFINED*
16977  *
16978  */
16979 /*
16980  * Field : GPIO/Loan IO50Input Mux Selection Field - sel
16981  *
16982  * Select source for GPIO/LoanIO 50.
16983  *
16984  * 0 : Source for GPIO/LoanIO 50 is GENERALIO2.
16985  *
16986  * 1 : Source for GPIO/LoanIO 50 is EMACIO16.
16987  *
16988  * Field Access Macros:
16989  *
16990  */
16991 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
16992 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0
16993 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
16994 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0
16995 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
16996 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1
16997 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */
16998 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001
16999 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value. */
17000 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe
17001 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field. */
17002 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0
17003 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX50_SEL field value from a register. */
17004 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
17005 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX50_SEL register field value suitable for setting the register. */
17006 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
17007 
17008 #ifndef __ASSEMBLY__
17009 /*
17010  * WARNING: The C register and register group struct declarations are provided for
17011  * convenience and illustrative purposes. They should, however, be used with
17012  * caution as the C language standard provides no guarantees about the alignment or
17013  * atomicity of device memory accesses. The recommended practice for writing
17014  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17015  * alt_write_word() functions.
17016  *
17017  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50.
17018  */
17019 struct ALT_SYSMGR_PINMUX_GPLINMUX50_s
17020 {
17021  uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */
17022  uint32_t : 31; /* *UNDEFINED* */
17023 };
17024 
17025 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX50. */
17026 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX50_s ALT_SYSMGR_PINMUX_GPLINMUX50_t;
17027 #endif /* __ASSEMBLY__ */
17028 
17029 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX50 register from the beginning of the component. */
17030 #define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180
17031 
17032 /*
17033  * Register : GPIO/LoanIO 51 Input Mux Selection Register - GPLINMUX51
17034  *
17035  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17036  * the input signal for GPIO/LoanIO 51.
17037  *
17038  * Only reset by a cold reset (ignores warm reset).
17039  *
17040  * NOTE: These registers should not be modified after IO configuration.There is no
17041  * support for dynamically changing the Pin Mux selections.
17042  *
17043  * Register Layout
17044  *
17045  * Bits | Access | Reset | Description
17046  * :-------|:-------|:------|:----------------------------------------
17047  * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field
17048  * [31:1] | ??? | 0x0 | *UNDEFINED*
17049  *
17050  */
17051 /*
17052  * Field : GPIO/Loan IO51Input Mux Selection Field - sel
17053  *
17054  * Select source for GPIO/LoanIO 51.
17055  *
17056  * 0 : Source for GPIO/LoanIO 51 is GENERALIO3.
17057  *
17058  * 1 : Source for GPIO/LoanIO 51 is EMACIO17.
17059  *
17060  * Field Access Macros:
17061  *
17062  */
17063 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17064 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0
17065 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17066 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0
17067 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17068 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1
17069 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */
17070 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001
17071 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value. */
17072 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe
17073 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field. */
17074 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0
17075 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX51_SEL field value from a register. */
17076 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
17077 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX51_SEL register field value suitable for setting the register. */
17078 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
17079 
17080 #ifndef __ASSEMBLY__
17081 /*
17082  * WARNING: The C register and register group struct declarations are provided for
17083  * convenience and illustrative purposes. They should, however, be used with
17084  * caution as the C language standard provides no guarantees about the alignment or
17085  * atomicity of device memory accesses. The recommended practice for writing
17086  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17087  * alt_write_word() functions.
17088  *
17089  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51.
17090  */
17091 struct ALT_SYSMGR_PINMUX_GPLINMUX51_s
17092 {
17093  uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */
17094  uint32_t : 31; /* *UNDEFINED* */
17095 };
17096 
17097 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX51. */
17098 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX51_s ALT_SYSMGR_PINMUX_GPLINMUX51_t;
17099 #endif /* __ASSEMBLY__ */
17100 
17101 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX51 register from the beginning of the component. */
17102 #define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184
17103 
17104 /*
17105  * Register : GPIO/LoanIO 52 Input Mux Selection Register - GPLINMUX52
17106  *
17107  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17108  * the input signal for GPIO/LoanIO 52.
17109  *
17110  * Only reset by a cold reset (ignores warm reset).
17111  *
17112  * NOTE: These registers should not be modified after IO configuration.There is no
17113  * support for dynamically changing the Pin Mux selections.
17114  *
17115  * Register Layout
17116  *
17117  * Bits | Access | Reset | Description
17118  * :-------|:-------|:------|:----------------------------------------
17119  * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field
17120  * [31:1] | ??? | 0x0 | *UNDEFINED*
17121  *
17122  */
17123 /*
17124  * Field : GPIO/Loan IO52Input Mux Selection Field - sel
17125  *
17126  * Select source for GPIO/LoanIO 52.
17127  *
17128  * 0 : Source for GPIO/LoanIO 52 is GENERALIO4.
17129  *
17130  * 1 : Source for GPIO/LoanIO 52 is EMACIO18.
17131  *
17132  * Field Access Macros:
17133  *
17134  */
17135 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17136 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0
17137 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17138 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0
17139 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17140 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1
17141 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */
17142 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001
17143 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value. */
17144 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe
17145 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field. */
17146 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0
17147 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX52_SEL field value from a register. */
17148 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
17149 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX52_SEL register field value suitable for setting the register. */
17150 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
17151 
17152 #ifndef __ASSEMBLY__
17153 /*
17154  * WARNING: The C register and register group struct declarations are provided for
17155  * convenience and illustrative purposes. They should, however, be used with
17156  * caution as the C language standard provides no guarantees about the alignment or
17157  * atomicity of device memory accesses. The recommended practice for writing
17158  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17159  * alt_write_word() functions.
17160  *
17161  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52.
17162  */
17163 struct ALT_SYSMGR_PINMUX_GPLINMUX52_s
17164 {
17165  uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */
17166  uint32_t : 31; /* *UNDEFINED* */
17167 };
17168 
17169 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX52. */
17170 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX52_s ALT_SYSMGR_PINMUX_GPLINMUX52_t;
17171 #endif /* __ASSEMBLY__ */
17172 
17173 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX52 register from the beginning of the component. */
17174 #define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188
17175 
17176 /*
17177  * Register : GPIO/LoanIO 53 Input Mux Selection Register - GPLINMUX53
17178  *
17179  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17180  * the input signal for GPIO/LoanIO 53.
17181  *
17182  * Only reset by a cold reset (ignores warm reset).
17183  *
17184  * NOTE: These registers should not be modified after IO configuration.There is no
17185  * support for dynamically changing the Pin Mux selections.
17186  *
17187  * Register Layout
17188  *
17189  * Bits | Access | Reset | Description
17190  * :-------|:-------|:------|:----------------------------------------
17191  * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field
17192  * [31:1] | ??? | 0x0 | *UNDEFINED*
17193  *
17194  */
17195 /*
17196  * Field : GPIO/Loan IO53Input Mux Selection Field - sel
17197  *
17198  * Select source for GPIO/LoanIO 53.
17199  *
17200  * 0 : Source for GPIO/LoanIO 53 is GENERALIO5.
17201  *
17202  * 1 : Source for GPIO/LoanIO 53 is EMACIO19.
17203  *
17204  * Field Access Macros:
17205  *
17206  */
17207 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17208 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0
17209 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17210 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0
17211 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17212 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1
17213 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */
17214 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001
17215 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value. */
17216 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe
17217 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field. */
17218 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0
17219 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX53_SEL field value from a register. */
17220 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
17221 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX53_SEL register field value suitable for setting the register. */
17222 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
17223 
17224 #ifndef __ASSEMBLY__
17225 /*
17226  * WARNING: The C register and register group struct declarations are provided for
17227  * convenience and illustrative purposes. They should, however, be used with
17228  * caution as the C language standard provides no guarantees about the alignment or
17229  * atomicity of device memory accesses. The recommended practice for writing
17230  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17231  * alt_write_word() functions.
17232  *
17233  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53.
17234  */
17235 struct ALT_SYSMGR_PINMUX_GPLINMUX53_s
17236 {
17237  uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */
17238  uint32_t : 31; /* *UNDEFINED* */
17239 };
17240 
17241 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX53. */
17242 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX53_s ALT_SYSMGR_PINMUX_GPLINMUX53_t;
17243 #endif /* __ASSEMBLY__ */
17244 
17245 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX53 register from the beginning of the component. */
17246 #define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c
17247 
17248 /*
17249  * Register : GPIO/LoanIO 54 Input Mux Selection Register - GPLINMUX54
17250  *
17251  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17252  * the input signal for GPIO/LoanIO 54.
17253  *
17254  * Only reset by a cold reset (ignores warm reset).
17255  *
17256  * NOTE: These registers should not be modified after IO configuration.There is no
17257  * support for dynamically changing the Pin Mux selections.
17258  *
17259  * Register Layout
17260  *
17261  * Bits | Access | Reset | Description
17262  * :-------|:-------|:------|:----------------------------------------
17263  * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field
17264  * [31:1] | ??? | 0x0 | *UNDEFINED*
17265  *
17266  */
17267 /*
17268  * Field : GPIO/Loan IO54Input Mux Selection Field - sel
17269  *
17270  * Select source for GPIO/LoanIO 54.
17271  *
17272  * 0 : Source for GPIO/LoanIO 54 is GENERALIO6.
17273  *
17274  * 1 : Source for GPIO/LoanIO 54 is MIXED2IO0.
17275  *
17276  * Field Access Macros:
17277  *
17278  */
17279 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17280 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0
17281 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17282 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0
17283 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17284 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1
17285 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */
17286 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001
17287 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value. */
17288 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe
17289 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field. */
17290 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0
17291 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX54_SEL field value from a register. */
17292 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
17293 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX54_SEL register field value suitable for setting the register. */
17294 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
17295 
17296 #ifndef __ASSEMBLY__
17297 /*
17298  * WARNING: The C register and register group struct declarations are provided for
17299  * convenience and illustrative purposes. They should, however, be used with
17300  * caution as the C language standard provides no guarantees about the alignment or
17301  * atomicity of device memory accesses. The recommended practice for writing
17302  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17303  * alt_write_word() functions.
17304  *
17305  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54.
17306  */
17307 struct ALT_SYSMGR_PINMUX_GPLINMUX54_s
17308 {
17309  uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */
17310  uint32_t : 31; /* *UNDEFINED* */
17311 };
17312 
17313 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX54. */
17314 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX54_s ALT_SYSMGR_PINMUX_GPLINMUX54_t;
17315 #endif /* __ASSEMBLY__ */
17316 
17317 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX54 register from the beginning of the component. */
17318 #define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190
17319 
17320 /*
17321  * Register : GPIO/LoanIO 55 Input Mux Selection Register - GPLINMUX55
17322  *
17323  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17324  * the input signal for GPIO/LoanIO 55.
17325  *
17326  * Only reset by a cold reset (ignores warm reset).
17327  *
17328  * NOTE: These registers should not be modified after IO configuration.There is no
17329  * support for dynamically changing the Pin Mux selections.
17330  *
17331  * Register Layout
17332  *
17333  * Bits | Access | Reset | Description
17334  * :-------|:-------|:------|:----------------------------------------
17335  * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field
17336  * [31:1] | ??? | 0x0 | *UNDEFINED*
17337  *
17338  */
17339 /*
17340  * Field : GPIO/Loan IO55Input Mux Selection Field - sel
17341  *
17342  * Select source for GPIO/LoanIO 55.
17343  *
17344  * 0 : Source for GPIO/LoanIO 55 is GENERALIO7.
17345  *
17346  * 1 : Source for GPIO/LoanIO 55 is MIXED2IO1.
17347  *
17348  * Field Access Macros:
17349  *
17350  */
17351 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17352 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0
17353 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17354 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0
17355 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17356 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1
17357 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */
17358 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001
17359 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value. */
17360 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe
17361 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field. */
17362 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0
17363 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX55_SEL field value from a register. */
17364 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
17365 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX55_SEL register field value suitable for setting the register. */
17366 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
17367 
17368 #ifndef __ASSEMBLY__
17369 /*
17370  * WARNING: The C register and register group struct declarations are provided for
17371  * convenience and illustrative purposes. They should, however, be used with
17372  * caution as the C language standard provides no guarantees about the alignment or
17373  * atomicity of device memory accesses. The recommended practice for writing
17374  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17375  * alt_write_word() functions.
17376  *
17377  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55.
17378  */
17379 struct ALT_SYSMGR_PINMUX_GPLINMUX55_s
17380 {
17381  uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */
17382  uint32_t : 31; /* *UNDEFINED* */
17383 };
17384 
17385 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX55. */
17386 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX55_s ALT_SYSMGR_PINMUX_GPLINMUX55_t;
17387 #endif /* __ASSEMBLY__ */
17388 
17389 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX55 register from the beginning of the component. */
17390 #define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194
17391 
17392 /*
17393  * Register : GPIO/LoanIO 56 Input Mux Selection Register - GPLINMUX56
17394  *
17395  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17396  * the input signal for GPIO/LoanIO 56.
17397  *
17398  * Only reset by a cold reset (ignores warm reset).
17399  *
17400  * NOTE: These registers should not be modified after IO configuration.There is no
17401  * support for dynamically changing the Pin Mux selections.
17402  *
17403  * Register Layout
17404  *
17405  * Bits | Access | Reset | Description
17406  * :-------|:-------|:------|:----------------------------------------
17407  * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field
17408  * [31:1] | ??? | 0x0 | *UNDEFINED*
17409  *
17410  */
17411 /*
17412  * Field : GPIO/Loan IO56Input Mux Selection Field - sel
17413  *
17414  * Select source for GPIO/LoanIO 56.
17415  *
17416  * 0 : Source for GPIO/LoanIO 56 is GENERALIO8.
17417  *
17418  * 1 : Source for GPIO/LoanIO 56 is MIXED2IO2.
17419  *
17420  * Field Access Macros:
17421  *
17422  */
17423 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17424 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0
17425 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17426 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0
17427 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17428 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1
17429 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */
17430 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001
17431 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value. */
17432 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe
17433 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field. */
17434 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0
17435 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX56_SEL field value from a register. */
17436 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
17437 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX56_SEL register field value suitable for setting the register. */
17438 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
17439 
17440 #ifndef __ASSEMBLY__
17441 /*
17442  * WARNING: The C register and register group struct declarations are provided for
17443  * convenience and illustrative purposes. They should, however, be used with
17444  * caution as the C language standard provides no guarantees about the alignment or
17445  * atomicity of device memory accesses. The recommended practice for writing
17446  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17447  * alt_write_word() functions.
17448  *
17449  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56.
17450  */
17451 struct ALT_SYSMGR_PINMUX_GPLINMUX56_s
17452 {
17453  uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */
17454  uint32_t : 31; /* *UNDEFINED* */
17455 };
17456 
17457 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX56. */
17458 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX56_s ALT_SYSMGR_PINMUX_GPLINMUX56_t;
17459 #endif /* __ASSEMBLY__ */
17460 
17461 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX56 register from the beginning of the component. */
17462 #define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198
17463 
17464 /*
17465  * Register : GPIO/LoanIO 57 Input Mux Selection Register - GPLINMUX57
17466  *
17467  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17468  * the input signal for GPIO/LoanIO 57.
17469  *
17470  * Only reset by a cold reset (ignores warm reset).
17471  *
17472  * NOTE: These registers should not be modified after IO configuration.There is no
17473  * support for dynamically changing the Pin Mux selections.
17474  *
17475  * Register Layout
17476  *
17477  * Bits | Access | Reset | Description
17478  * :-------|:-------|:------|:----------------------------------------
17479  * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field
17480  * [31:1] | ??? | 0x0 | *UNDEFINED*
17481  *
17482  */
17483 /*
17484  * Field : GPIO/Loan IO57Input Mux Selection Field - sel
17485  *
17486  * Select source for GPIO/LoanIO 57.
17487  *
17488  * 0 : Source for GPIO/LoanIO 57 is GENERALIO9.
17489  *
17490  * 1 : Source for GPIO/LoanIO 57 is MIXED2IO3.
17491  *
17492  * Field Access Macros:
17493  *
17494  */
17495 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17496 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0
17497 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17498 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0
17499 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17500 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1
17501 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */
17502 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001
17503 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value. */
17504 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe
17505 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field. */
17506 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0
17507 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX57_SEL field value from a register. */
17508 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
17509 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX57_SEL register field value suitable for setting the register. */
17510 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
17511 
17512 #ifndef __ASSEMBLY__
17513 /*
17514  * WARNING: The C register and register group struct declarations are provided for
17515  * convenience and illustrative purposes. They should, however, be used with
17516  * caution as the C language standard provides no guarantees about the alignment or
17517  * atomicity of device memory accesses. The recommended practice for writing
17518  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17519  * alt_write_word() functions.
17520  *
17521  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57.
17522  */
17523 struct ALT_SYSMGR_PINMUX_GPLINMUX57_s
17524 {
17525  uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */
17526  uint32_t : 31; /* *UNDEFINED* */
17527 };
17528 
17529 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX57. */
17530 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX57_s ALT_SYSMGR_PINMUX_GPLINMUX57_t;
17531 #endif /* __ASSEMBLY__ */
17532 
17533 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX57 register from the beginning of the component. */
17534 #define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c
17535 
17536 /*
17537  * Register : GPIO/LoanIO 58 Input Mux Selection Register - GPLINMUX58
17538  *
17539  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17540  * the input signal for GPIO/LoanIO 58.
17541  *
17542  * Only reset by a cold reset (ignores warm reset).
17543  *
17544  * NOTE: These registers should not be modified after IO configuration.There is no
17545  * support for dynamically changing the Pin Mux selections.
17546  *
17547  * Register Layout
17548  *
17549  * Bits | Access | Reset | Description
17550  * :-------|:-------|:------|:----------------------------------------
17551  * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field
17552  * [31:1] | ??? | 0x0 | *UNDEFINED*
17553  *
17554  */
17555 /*
17556  * Field : GPIO/Loan IO58Input Mux Selection Field - sel
17557  *
17558  * Select source for GPIO/LoanIO 58.
17559  *
17560  * 0 : Source for GPIO/LoanIO 58 is GENERALIO10.
17561  *
17562  * 1 : Source for GPIO/LoanIO 58 is MIXED2IO4.
17563  *
17564  * Field Access Macros:
17565  *
17566  */
17567 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17568 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0
17569 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17570 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0
17571 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17572 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1
17573 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */
17574 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001
17575 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value. */
17576 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe
17577 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field. */
17578 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0
17579 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX58_SEL field value from a register. */
17580 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
17581 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX58_SEL register field value suitable for setting the register. */
17582 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
17583 
17584 #ifndef __ASSEMBLY__
17585 /*
17586  * WARNING: The C register and register group struct declarations are provided for
17587  * convenience and illustrative purposes. They should, however, be used with
17588  * caution as the C language standard provides no guarantees about the alignment or
17589  * atomicity of device memory accesses. The recommended practice for writing
17590  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17591  * alt_write_word() functions.
17592  *
17593  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58.
17594  */
17595 struct ALT_SYSMGR_PINMUX_GPLINMUX58_s
17596 {
17597  uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */
17598  uint32_t : 31; /* *UNDEFINED* */
17599 };
17600 
17601 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX58. */
17602 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX58_s ALT_SYSMGR_PINMUX_GPLINMUX58_t;
17603 #endif /* __ASSEMBLY__ */
17604 
17605 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX58 register from the beginning of the component. */
17606 #define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0
17607 
17608 /*
17609  * Register : GPIO/LoanIO 59 Input Mux Selection Register - GPLINMUX59
17610  *
17611  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17612  * the input signal for GPIO/LoanIO 59.
17613  *
17614  * Only reset by a cold reset (ignores warm reset).
17615  *
17616  * NOTE: These registers should not be modified after IO configuration.There is no
17617  * support for dynamically changing the Pin Mux selections.
17618  *
17619  * Register Layout
17620  *
17621  * Bits | Access | Reset | Description
17622  * :-------|:-------|:------|:----------------------------------------
17623  * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field
17624  * [31:1] | ??? | 0x0 | *UNDEFINED*
17625  *
17626  */
17627 /*
17628  * Field : GPIO/Loan IO59Input Mux Selection Field - sel
17629  *
17630  * Select source for GPIO/LoanIO 59.
17631  *
17632  * 0 : Source for GPIO/LoanIO 59 is GENERALIO11.
17633  *
17634  * 1 : Source for GPIO/LoanIO 59 is MIXED2IO5.
17635  *
17636  * Field Access Macros:
17637  *
17638  */
17639 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17640 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0
17641 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17642 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0
17643 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17644 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1
17645 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */
17646 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001
17647 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value. */
17648 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe
17649 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field. */
17650 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0
17651 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX59_SEL field value from a register. */
17652 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
17653 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX59_SEL register field value suitable for setting the register. */
17654 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
17655 
17656 #ifndef __ASSEMBLY__
17657 /*
17658  * WARNING: The C register and register group struct declarations are provided for
17659  * convenience and illustrative purposes. They should, however, be used with
17660  * caution as the C language standard provides no guarantees about the alignment or
17661  * atomicity of device memory accesses. The recommended practice for writing
17662  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17663  * alt_write_word() functions.
17664  *
17665  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59.
17666  */
17667 struct ALT_SYSMGR_PINMUX_GPLINMUX59_s
17668 {
17669  uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */
17670  uint32_t : 31; /* *UNDEFINED* */
17671 };
17672 
17673 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX59. */
17674 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX59_s ALT_SYSMGR_PINMUX_GPLINMUX59_t;
17675 #endif /* __ASSEMBLY__ */
17676 
17677 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX59 register from the beginning of the component. */
17678 #define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4
17679 
17680 /*
17681  * Register : GPIO/LoanIO 60 Input Mux Selection Register - GPLINMUX60
17682  *
17683  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17684  * the input signal for GPIO/LoanIO 60.
17685  *
17686  * Only reset by a cold reset (ignores warm reset).
17687  *
17688  * NOTE: These registers should not be modified after IO configuration.There is no
17689  * support for dynamically changing the Pin Mux selections.
17690  *
17691  * Register Layout
17692  *
17693  * Bits | Access | Reset | Description
17694  * :-------|:-------|:------|:----------------------------------------
17695  * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field
17696  * [31:1] | ??? | 0x0 | *UNDEFINED*
17697  *
17698  */
17699 /*
17700  * Field : GPIO/Loan IO60Input Mux Selection Field - sel
17701  *
17702  * Select source for GPIO/LoanIO 60.
17703  *
17704  * 0 : Source for GPIO/LoanIO 60 is GENERALIO12.
17705  *
17706  * 1 : Source for GPIO/LoanIO 60 is MIXED2IO6.
17707  *
17708  * Field Access Macros:
17709  *
17710  */
17711 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17712 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0
17713 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17714 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0
17715 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17716 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1
17717 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */
17718 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001
17719 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value. */
17720 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe
17721 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field. */
17722 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0
17723 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX60_SEL field value from a register. */
17724 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
17725 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX60_SEL register field value suitable for setting the register. */
17726 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
17727 
17728 #ifndef __ASSEMBLY__
17729 /*
17730  * WARNING: The C register and register group struct declarations are provided for
17731  * convenience and illustrative purposes. They should, however, be used with
17732  * caution as the C language standard provides no guarantees about the alignment or
17733  * atomicity of device memory accesses. The recommended practice for writing
17734  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17735  * alt_write_word() functions.
17736  *
17737  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60.
17738  */
17739 struct ALT_SYSMGR_PINMUX_GPLINMUX60_s
17740 {
17741  uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */
17742  uint32_t : 31; /* *UNDEFINED* */
17743 };
17744 
17745 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX60. */
17746 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX60_s ALT_SYSMGR_PINMUX_GPLINMUX60_t;
17747 #endif /* __ASSEMBLY__ */
17748 
17749 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX60 register from the beginning of the component. */
17750 #define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8
17751 
17752 /*
17753  * Register : GPIO/LoanIO 61 Input Mux Selection Register - GPLINMUX61
17754  *
17755  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17756  * the input signal for GPIO/LoanIO 61.
17757  *
17758  * Only reset by a cold reset (ignores warm reset).
17759  *
17760  * NOTE: These registers should not be modified after IO configuration.There is no
17761  * support for dynamically changing the Pin Mux selections.
17762  *
17763  * Register Layout
17764  *
17765  * Bits | Access | Reset | Description
17766  * :-------|:-------|:------|:----------------------------------------
17767  * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field
17768  * [31:1] | ??? | 0x0 | *UNDEFINED*
17769  *
17770  */
17771 /*
17772  * Field : GPIO/Loan IO61Input Mux Selection Field - sel
17773  *
17774  * Select source for GPIO/LoanIO 61.
17775  *
17776  * 0 : Source for GPIO/LoanIO 61 is GENERALIO13.
17777  *
17778  * 1 : Source for GPIO/LoanIO 61 is MIXED2IO7.
17779  *
17780  * Field Access Macros:
17781  *
17782  */
17783 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17784 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0
17785 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17786 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0
17787 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17788 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1
17789 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */
17790 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001
17791 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value. */
17792 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe
17793 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field. */
17794 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0
17795 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX61_SEL field value from a register. */
17796 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
17797 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX61_SEL register field value suitable for setting the register. */
17798 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
17799 
17800 #ifndef __ASSEMBLY__
17801 /*
17802  * WARNING: The C register and register group struct declarations are provided for
17803  * convenience and illustrative purposes. They should, however, be used with
17804  * caution as the C language standard provides no guarantees about the alignment or
17805  * atomicity of device memory accesses. The recommended practice for writing
17806  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17807  * alt_write_word() functions.
17808  *
17809  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61.
17810  */
17811 struct ALT_SYSMGR_PINMUX_GPLINMUX61_s
17812 {
17813  uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */
17814  uint32_t : 31; /* *UNDEFINED* */
17815 };
17816 
17817 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX61. */
17818 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX61_s ALT_SYSMGR_PINMUX_GPLINMUX61_t;
17819 #endif /* __ASSEMBLY__ */
17820 
17821 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX61 register from the beginning of the component. */
17822 #define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac
17823 
17824 /*
17825  * Register : GPIO/LoanIO 62 Input Mux Selection Register - GPLINMUX62
17826  *
17827  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17828  * the input signal for GPIO/LoanIO 62.
17829  *
17830  * Only reset by a cold reset (ignores warm reset).
17831  *
17832  * NOTE: These registers should not be modified after IO configuration.There is no
17833  * support for dynamically changing the Pin Mux selections.
17834  *
17835  * Register Layout
17836  *
17837  * Bits | Access | Reset | Description
17838  * :-------|:-------|:------|:----------------------------------------
17839  * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field
17840  * [31:1] | ??? | 0x0 | *UNDEFINED*
17841  *
17842  */
17843 /*
17844  * Field : GPIO/Loan IO62Input Mux Selection Field - sel
17845  *
17846  * Select source for GPIO/LoanIO 62.
17847  *
17848  * 0 : Source for GPIO/LoanIO 62 is GENERALIO14.
17849  *
17850  * 1 : Source for GPIO/LoanIO 62 is GENERALIO23.
17851  *
17852  * Field Access Macros:
17853  *
17854  */
17855 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17856 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0
17857 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17858 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0
17859 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17860 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1
17861 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */
17862 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001
17863 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value. */
17864 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe
17865 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field. */
17866 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0
17867 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX62_SEL field value from a register. */
17868 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
17869 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX62_SEL register field value suitable for setting the register. */
17870 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
17871 
17872 #ifndef __ASSEMBLY__
17873 /*
17874  * WARNING: The C register and register group struct declarations are provided for
17875  * convenience and illustrative purposes. They should, however, be used with
17876  * caution as the C language standard provides no guarantees about the alignment or
17877  * atomicity of device memory accesses. The recommended practice for writing
17878  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17879  * alt_write_word() functions.
17880  *
17881  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62.
17882  */
17883 struct ALT_SYSMGR_PINMUX_GPLINMUX62_s
17884 {
17885  uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */
17886  uint32_t : 31; /* *UNDEFINED* */
17887 };
17888 
17889 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX62. */
17890 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX62_s ALT_SYSMGR_PINMUX_GPLINMUX62_t;
17891 #endif /* __ASSEMBLY__ */
17892 
17893 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX62 register from the beginning of the component. */
17894 #define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0
17895 
17896 /*
17897  * Register : GPIO/LoanIO 63 Input Mux Selection Register - GPLINMUX63
17898  *
17899  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17900  * the input signal for GPIO/LoanIO 63.
17901  *
17902  * Only reset by a cold reset (ignores warm reset).
17903  *
17904  * NOTE: These registers should not be modified after IO configuration.There is no
17905  * support for dynamically changing the Pin Mux selections.
17906  *
17907  * Register Layout
17908  *
17909  * Bits | Access | Reset | Description
17910  * :-------|:-------|:------|:----------------------------------------
17911  * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field
17912  * [31:1] | ??? | 0x0 | *UNDEFINED*
17913  *
17914  */
17915 /*
17916  * Field : GPIO/Loan IO63Input Mux Selection Field - sel
17917  *
17918  * Select source for GPIO/LoanIO 63.
17919  *
17920  * 0 : Source for GPIO/LoanIO 63 is GENERALIO15.
17921  *
17922  * 1 : Source for GPIO/LoanIO 63 is GENERALIO24.
17923  *
17924  * Field Access Macros:
17925  *
17926  */
17927 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17928 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0
17929 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17930 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0
17931 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17932 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1
17933 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */
17934 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001
17935 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value. */
17936 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe
17937 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field. */
17938 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0
17939 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX63_SEL field value from a register. */
17940 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
17941 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX63_SEL register field value suitable for setting the register. */
17942 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
17943 
17944 #ifndef __ASSEMBLY__
17945 /*
17946  * WARNING: The C register and register group struct declarations are provided for
17947  * convenience and illustrative purposes. They should, however, be used with
17948  * caution as the C language standard provides no guarantees about the alignment or
17949  * atomicity of device memory accesses. The recommended practice for writing
17950  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
17951  * alt_write_word() functions.
17952  *
17953  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63.
17954  */
17955 struct ALT_SYSMGR_PINMUX_GPLINMUX63_s
17956 {
17957  uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */
17958  uint32_t : 31; /* *UNDEFINED* */
17959 };
17960 
17961 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX63. */
17962 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX63_s ALT_SYSMGR_PINMUX_GPLINMUX63_t;
17963 #endif /* __ASSEMBLY__ */
17964 
17965 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX63 register from the beginning of the component. */
17966 #define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4
17967 
17968 /*
17969  * Register : GPIO/LoanIO 64 Input Mux Selection Register - GPLINMUX64
17970  *
17971  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
17972  * the input signal for GPIO/LoanIO 64.
17973  *
17974  * Only reset by a cold reset (ignores warm reset).
17975  *
17976  * NOTE: These registers should not be modified after IO configuration.There is no
17977  * support for dynamically changing the Pin Mux selections.
17978  *
17979  * Register Layout
17980  *
17981  * Bits | Access | Reset | Description
17982  * :-------|:-------|:------|:----------------------------------------
17983  * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field
17984  * [31:1] | ??? | 0x0 | *UNDEFINED*
17985  *
17986  */
17987 /*
17988  * Field : GPIO/Loan IO64Input Mux Selection Field - sel
17989  *
17990  * Select source for GPIO/LoanIO 64.
17991  *
17992  * 0 : Source for GPIO/LoanIO 64 is GENERALIO16.
17993  *
17994  * 1 : Source for GPIO/LoanIO 64 is GENERALIO25.
17995  *
17996  * Field Access Macros:
17997  *
17998  */
17999 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18000 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0
18001 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18002 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0
18003 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18004 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1
18005 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */
18006 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001
18007 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value. */
18008 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe
18009 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field. */
18010 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0
18011 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX64_SEL field value from a register. */
18012 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
18013 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX64_SEL register field value suitable for setting the register. */
18014 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
18015 
18016 #ifndef __ASSEMBLY__
18017 /*
18018  * WARNING: The C register and register group struct declarations are provided for
18019  * convenience and illustrative purposes. They should, however, be used with
18020  * caution as the C language standard provides no guarantees about the alignment or
18021  * atomicity of device memory accesses. The recommended practice for writing
18022  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18023  * alt_write_word() functions.
18024  *
18025  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64.
18026  */
18027 struct ALT_SYSMGR_PINMUX_GPLINMUX64_s
18028 {
18029  uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */
18030  uint32_t : 31; /* *UNDEFINED* */
18031 };
18032 
18033 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX64. */
18034 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX64_s ALT_SYSMGR_PINMUX_GPLINMUX64_t;
18035 #endif /* __ASSEMBLY__ */
18036 
18037 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX64 register from the beginning of the component. */
18038 #define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8
18039 
18040 /*
18041  * Register : GPIO/LoanIO 65 Input Mux Selection Register - GPLINMUX65
18042  *
18043  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18044  * the input signal for GPIO/LoanIO 65.
18045  *
18046  * Only reset by a cold reset (ignores warm reset).
18047  *
18048  * NOTE: These registers should not be modified after IO configuration.There is no
18049  * support for dynamically changing the Pin Mux selections.
18050  *
18051  * Register Layout
18052  *
18053  * Bits | Access | Reset | Description
18054  * :-------|:-------|:------|:----------------------------------------
18055  * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field
18056  * [31:1] | ??? | 0x0 | *UNDEFINED*
18057  *
18058  */
18059 /*
18060  * Field : GPIO/Loan IO65Input Mux Selection Field - sel
18061  *
18062  * Select source for GPIO/LoanIO 65.
18063  *
18064  * 0 : Source for GPIO/LoanIO 65 is GENERALIO17.
18065  *
18066  * 1 : Source for GPIO/LoanIO 65 is GENERALIO26.
18067  *
18068  * Field Access Macros:
18069  *
18070  */
18071 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18072 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0
18073 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18074 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0
18075 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18076 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1
18077 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */
18078 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001
18079 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value. */
18080 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe
18081 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field. */
18082 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0
18083 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX65_SEL field value from a register. */
18084 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
18085 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX65_SEL register field value suitable for setting the register. */
18086 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
18087 
18088 #ifndef __ASSEMBLY__
18089 /*
18090  * WARNING: The C register and register group struct declarations are provided for
18091  * convenience and illustrative purposes. They should, however, be used with
18092  * caution as the C language standard provides no guarantees about the alignment or
18093  * atomicity of device memory accesses. The recommended practice for writing
18094  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18095  * alt_write_word() functions.
18096  *
18097  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65.
18098  */
18099 struct ALT_SYSMGR_PINMUX_GPLINMUX65_s
18100 {
18101  uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */
18102  uint32_t : 31; /* *UNDEFINED* */
18103 };
18104 
18105 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX65. */
18106 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX65_s ALT_SYSMGR_PINMUX_GPLINMUX65_t;
18107 #endif /* __ASSEMBLY__ */
18108 
18109 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX65 register from the beginning of the component. */
18110 #define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc
18111 
18112 /*
18113  * Register : GPIO/LoanIO 66 Input Mux Selection Register - GPLINMUX66
18114  *
18115  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18116  * the input signal for GPIO/LoanIO 66.
18117  *
18118  * Only reset by a cold reset (ignores warm reset).
18119  *
18120  * NOTE: These registers should not be modified after IO configuration.There is no
18121  * support for dynamically changing the Pin Mux selections.
18122  *
18123  * Register Layout
18124  *
18125  * Bits | Access | Reset | Description
18126  * :-------|:-------|:------|:----------------------------------------
18127  * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field
18128  * [31:1] | ??? | 0x0 | *UNDEFINED*
18129  *
18130  */
18131 /*
18132  * Field : GPIO/Loan IO66Input Mux Selection Field - sel
18133  *
18134  * Select source for GPIO/LoanIO 66.
18135  *
18136  * 0 : Source for GPIO/LoanIO 66 is GENERALIO18.
18137  *
18138  * 1 : Source for GPIO/LoanIO 66 is GENERALIO27.
18139  *
18140  * Field Access Macros:
18141  *
18142  */
18143 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18144 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0
18145 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18146 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0
18147 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18148 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1
18149 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */
18150 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001
18151 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value. */
18152 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe
18153 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field. */
18154 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0
18155 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX66_SEL field value from a register. */
18156 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
18157 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX66_SEL register field value suitable for setting the register. */
18158 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
18159 
18160 #ifndef __ASSEMBLY__
18161 /*
18162  * WARNING: The C register and register group struct declarations are provided for
18163  * convenience and illustrative purposes. They should, however, be used with
18164  * caution as the C language standard provides no guarantees about the alignment or
18165  * atomicity of device memory accesses. The recommended practice for writing
18166  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18167  * alt_write_word() functions.
18168  *
18169  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66.
18170  */
18171 struct ALT_SYSMGR_PINMUX_GPLINMUX66_s
18172 {
18173  uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */
18174  uint32_t : 31; /* *UNDEFINED* */
18175 };
18176 
18177 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX66. */
18178 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX66_s ALT_SYSMGR_PINMUX_GPLINMUX66_t;
18179 #endif /* __ASSEMBLY__ */
18180 
18181 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX66 register from the beginning of the component. */
18182 #define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0
18183 
18184 /*
18185  * Register : GPIO/LoanIO 67 Input Mux Selection Register - GPLINMUX67
18186  *
18187  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18188  * the input signal for GPIO/LoanIO 67.
18189  *
18190  * Only reset by a cold reset (ignores warm reset).
18191  *
18192  * NOTE: These registers should not be modified after IO configuration.There is no
18193  * support for dynamically changing the Pin Mux selections.
18194  *
18195  * Register Layout
18196  *
18197  * Bits | Access | Reset | Description
18198  * :-------|:-------|:------|:----------------------------------------
18199  * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field
18200  * [31:1] | ??? | 0x0 | *UNDEFINED*
18201  *
18202  */
18203 /*
18204  * Field : GPIO/Loan IO67Input Mux Selection Field - sel
18205  *
18206  * Select source for GPIO/LoanIO 67.
18207  *
18208  * 0 : Source for GPIO/LoanIO 67 is GENERALIO19.
18209  *
18210  * 1 : Source for GPIO/LoanIO 67 is GENERALIO28.
18211  *
18212  * Field Access Macros:
18213  *
18214  */
18215 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18216 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0
18217 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18218 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0
18219 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18220 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1
18221 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */
18222 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001
18223 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value. */
18224 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe
18225 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field. */
18226 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0
18227 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX67_SEL field value from a register. */
18228 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
18229 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX67_SEL register field value suitable for setting the register. */
18230 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
18231 
18232 #ifndef __ASSEMBLY__
18233 /*
18234  * WARNING: The C register and register group struct declarations are provided for
18235  * convenience and illustrative purposes. They should, however, be used with
18236  * caution as the C language standard provides no guarantees about the alignment or
18237  * atomicity of device memory accesses. The recommended practice for writing
18238  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18239  * alt_write_word() functions.
18240  *
18241  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67.
18242  */
18243 struct ALT_SYSMGR_PINMUX_GPLINMUX67_s
18244 {
18245  uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */
18246  uint32_t : 31; /* *UNDEFINED* */
18247 };
18248 
18249 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX67. */
18250 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX67_s ALT_SYSMGR_PINMUX_GPLINMUX67_t;
18251 #endif /* __ASSEMBLY__ */
18252 
18253 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX67 register from the beginning of the component. */
18254 #define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4
18255 
18256 /*
18257  * Register : GPIO/LoanIO 68 Input Mux Selection Register - GPLINMUX68
18258  *
18259  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18260  * the input signal for GPIO/LoanIO 68.
18261  *
18262  * Only reset by a cold reset (ignores warm reset).
18263  *
18264  * NOTE: These registers should not be modified after IO configuration.There is no
18265  * support for dynamically changing the Pin Mux selections.
18266  *
18267  * Register Layout
18268  *
18269  * Bits | Access | Reset | Description
18270  * :-------|:-------|:------|:----------------------------------------
18271  * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field
18272  * [31:1] | ??? | 0x0 | *UNDEFINED*
18273  *
18274  */
18275 /*
18276  * Field : GPIO/Loan IO68Input Mux Selection Field - sel
18277  *
18278  * Select source for GPIO/LoanIO 68.
18279  *
18280  * 0 : Source for GPIO/LoanIO 68 is GENERALIO20.
18281  *
18282  * 1 : Source for GPIO/LoanIO 68 is GENERALIO29.
18283  *
18284  * Field Access Macros:
18285  *
18286  */
18287 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18288 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0
18289 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18290 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0
18291 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18292 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1
18293 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */
18294 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001
18295 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value. */
18296 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe
18297 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field. */
18298 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0
18299 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX68_SEL field value from a register. */
18300 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
18301 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX68_SEL register field value suitable for setting the register. */
18302 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
18303 
18304 #ifndef __ASSEMBLY__
18305 /*
18306  * WARNING: The C register and register group struct declarations are provided for
18307  * convenience and illustrative purposes. They should, however, be used with
18308  * caution as the C language standard provides no guarantees about the alignment or
18309  * atomicity of device memory accesses. The recommended practice for writing
18310  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18311  * alt_write_word() functions.
18312  *
18313  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68.
18314  */
18315 struct ALT_SYSMGR_PINMUX_GPLINMUX68_s
18316 {
18317  uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */
18318  uint32_t : 31; /* *UNDEFINED* */
18319 };
18320 
18321 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX68. */
18322 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX68_s ALT_SYSMGR_PINMUX_GPLINMUX68_t;
18323 #endif /* __ASSEMBLY__ */
18324 
18325 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX68 register from the beginning of the component. */
18326 #define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8
18327 
18328 /*
18329  * Register : GPIO/LoanIO 69 Input Mux Selection Register - GPLINMUX69
18330  *
18331  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18332  * the input signal for GPIO/LoanIO 69.
18333  *
18334  * Only reset by a cold reset (ignores warm reset).
18335  *
18336  * NOTE: These registers should not be modified after IO configuration.There is no
18337  * support for dynamically changing the Pin Mux selections.
18338  *
18339  * Register Layout
18340  *
18341  * Bits | Access | Reset | Description
18342  * :-------|:-------|:------|:----------------------------------------
18343  * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field
18344  * [31:1] | ??? | 0x0 | *UNDEFINED*
18345  *
18346  */
18347 /*
18348  * Field : GPIO/Loan IO69Input Mux Selection Field - sel
18349  *
18350  * Select source for GPIO/LoanIO 69.
18351  *
18352  * 0 : Source for GPIO/LoanIO 69 is GENERALIO21.
18353  *
18354  * 1 : Source for GPIO/LoanIO 69 is GENERALIO30.
18355  *
18356  * Field Access Macros:
18357  *
18358  */
18359 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18360 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0
18361 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18362 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0
18363 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18364 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1
18365 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */
18366 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001
18367 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value. */
18368 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe
18369 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field. */
18370 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0
18371 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX69_SEL field value from a register. */
18372 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
18373 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX69_SEL register field value suitable for setting the register. */
18374 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
18375 
18376 #ifndef __ASSEMBLY__
18377 /*
18378  * WARNING: The C register and register group struct declarations are provided for
18379  * convenience and illustrative purposes. They should, however, be used with
18380  * caution as the C language standard provides no guarantees about the alignment or
18381  * atomicity of device memory accesses. The recommended practice for writing
18382  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18383  * alt_write_word() functions.
18384  *
18385  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69.
18386  */
18387 struct ALT_SYSMGR_PINMUX_GPLINMUX69_s
18388 {
18389  uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */
18390  uint32_t : 31; /* *UNDEFINED* */
18391 };
18392 
18393 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX69. */
18394 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX69_s ALT_SYSMGR_PINMUX_GPLINMUX69_t;
18395 #endif /* __ASSEMBLY__ */
18396 
18397 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX69 register from the beginning of the component. */
18398 #define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc
18399 
18400 /*
18401  * Register : GPIO/LoanIO 70 Input Mux Selection Register - GPLINMUX70
18402  *
18403  * Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects
18404  * the input signal for GPIO/LoanIO 70.
18405  *
18406  * Only reset by a cold reset (ignores warm reset).
18407  *
18408  * NOTE: These registers should not be modified after IO configuration.There is no
18409  * support for dynamically changing the Pin Mux selections.
18410  *
18411  * Register Layout
18412  *
18413  * Bits | Access | Reset | Description
18414  * :-------|:-------|:------|:----------------------------------------
18415  * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field
18416  * [31:1] | ??? | 0x0 | *UNDEFINED*
18417  *
18418  */
18419 /*
18420  * Field : GPIO/Loan IO70Input Mux Selection Field - sel
18421  *
18422  * Select source for GPIO/LoanIO 70.
18423  *
18424  * 0 : Source for GPIO/LoanIO 70 is GENERALIO22.
18425  *
18426  * 1 : Source for GPIO/LoanIO 70 is GENERALIO31.
18427  *
18428  * Field Access Macros:
18429  *
18430  */
18431 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18432 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0
18433 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18434 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0
18435 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18436 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1
18437 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */
18438 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001
18439 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value. */
18440 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe
18441 /* The reset value of the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field. */
18442 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0
18443 /* Extracts the ALT_SYSMGR_PINMUX_GPLINMUX70_SEL field value from a register. */
18444 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
18445 /* Produces a ALT_SYSMGR_PINMUX_GPLINMUX70_SEL register field value suitable for setting the register. */
18446 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
18447 
18448 #ifndef __ASSEMBLY__
18449 /*
18450  * WARNING: The C register and register group struct declarations are provided for
18451  * convenience and illustrative purposes. They should, however, be used with
18452  * caution as the C language standard provides no guarantees about the alignment or
18453  * atomicity of device memory accesses. The recommended practice for writing
18454  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18455  * alt_write_word() functions.
18456  *
18457  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70.
18458  */
18459 struct ALT_SYSMGR_PINMUX_GPLINMUX70_s
18460 {
18461  uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */
18462  uint32_t : 31; /* *UNDEFINED* */
18463 };
18464 
18465 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLINMUX70. */
18466 typedef volatile struct ALT_SYSMGR_PINMUX_GPLINMUX70_s ALT_SYSMGR_PINMUX_GPLINMUX70_t;
18467 #endif /* __ASSEMBLY__ */
18468 
18469 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLINMUX70 register from the beginning of the component. */
18470 #define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0
18471 
18472 /*
18473  * Register : GPIO/LoanIO 0 Output/Output Enable Mux Selection Register - GPLMUX0
18474  *
18475  * Selection between GPIO and LoanIO output and output enable for GPIO0 and
18476  * LoanIO0. These signals drive the Pin Mux. The Pin Mux must be configured to use
18477  * GPIO/LoanIO in addition to these settings
18478  *
18479  * Only reset by a cold reset (ignores warm reset).
18480  *
18481  * NOTE: These registers should not be modified after IO configuration.There is no
18482  * support for dynamically changing the Pin Mux selections.
18483  *
18484  * Register Layout
18485  *
18486  * Bits | Access | Reset | Description
18487  * :-------|:-------|:------|:---------------------------------------
18488  * [0] | RW | 0x0 | GPIO/Loan IO0Input Mux Selection Field
18489  * [31:1] | ??? | 0x0 | *UNDEFINED*
18490  *
18491  */
18492 /*
18493  * Field : GPIO/Loan IO0Input Mux Selection Field - sel
18494  *
18495  * Select source for GPIO/LoanIO 0.
18496  *
18497  * 0 : LoanIO 0 controls GPIO/LOANIO[0] output and output enable signals.
18498  *
18499  * 1 : GPIO 0 controls GPIO/LOANI[0] output and output enable signals.
18500  *
18501  * Field Access Macros:
18502  *
18503  */
18504 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18505 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0
18506 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18507 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0
18508 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18509 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1
18510 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */
18511 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001
18512 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value. */
18513 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe
18514 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field. */
18515 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0
18516 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX0_SEL field value from a register. */
18517 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0)
18518 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX0_SEL register field value suitable for setting the register. */
18519 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001)
18520 
18521 #ifndef __ASSEMBLY__
18522 /*
18523  * WARNING: The C register and register group struct declarations are provided for
18524  * convenience and illustrative purposes. They should, however, be used with
18525  * caution as the C language standard provides no guarantees about the alignment or
18526  * atomicity of device memory accesses. The recommended practice for writing
18527  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18528  * alt_write_word() functions.
18529  *
18530  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX0.
18531  */
18532 struct ALT_SYSMGR_PINMUX_GPLMUX0_s
18533 {
18534  uint32_t sel : 1; /* GPIO/Loan IO0Input Mux Selection Field */
18535  uint32_t : 31; /* *UNDEFINED* */
18536 };
18537 
18538 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX0. */
18539 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX0_s ALT_SYSMGR_PINMUX_GPLMUX0_t;
18540 #endif /* __ASSEMBLY__ */
18541 
18542 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX0 register from the beginning of the component. */
18543 #define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4
18544 
18545 /*
18546  * Register : GPIO/LoanIO 1 Output/Output Enable Mux Selection Register - GPLMUX1
18547  *
18548  * Selection between GPIO and LoanIO output and output enable for GPIO1 and
18549  * LoanIO1. These signals drive the Pin Mux. The Pin Mux must be configured to use
18550  * GPIO/LoanIO in addition to these settings
18551  *
18552  * Only reset by a cold reset (ignores warm reset).
18553  *
18554  * NOTE: These registers should not be modified after IO configuration.There is no
18555  * support for dynamically changing the Pin Mux selections.
18556  *
18557  * Register Layout
18558  *
18559  * Bits | Access | Reset | Description
18560  * :-------|:-------|:------|:---------------------------------------
18561  * [0] | RW | 0x0 | GPIO/Loan IO1Input Mux Selection Field
18562  * [31:1] | ??? | 0x0 | *UNDEFINED*
18563  *
18564  */
18565 /*
18566  * Field : GPIO/Loan IO1Input Mux Selection Field - sel
18567  *
18568  * Select source for GPIO/LoanIO 1.
18569  *
18570  * 0 : LoanIO 1 controls GPIO/LOANIO[1] output and output enable signals.
18571  *
18572  * 1 : GPIO 1 controls GPIO/LOANI[1] output and output enable signals.
18573  *
18574  * Field Access Macros:
18575  *
18576  */
18577 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18578 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0
18579 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18580 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0
18581 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18582 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1
18583 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */
18584 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001
18585 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value. */
18586 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe
18587 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field. */
18588 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0
18589 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX1_SEL field value from a register. */
18590 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0)
18591 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX1_SEL register field value suitable for setting the register. */
18592 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001)
18593 
18594 #ifndef __ASSEMBLY__
18595 /*
18596  * WARNING: The C register and register group struct declarations are provided for
18597  * convenience and illustrative purposes. They should, however, be used with
18598  * caution as the C language standard provides no guarantees about the alignment or
18599  * atomicity of device memory accesses. The recommended practice for writing
18600  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18601  * alt_write_word() functions.
18602  *
18603  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX1.
18604  */
18605 struct ALT_SYSMGR_PINMUX_GPLMUX1_s
18606 {
18607  uint32_t sel : 1; /* GPIO/Loan IO1Input Mux Selection Field */
18608  uint32_t : 31; /* *UNDEFINED* */
18609 };
18610 
18611 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX1. */
18612 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX1_s ALT_SYSMGR_PINMUX_GPLMUX1_t;
18613 #endif /* __ASSEMBLY__ */
18614 
18615 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX1 register from the beginning of the component. */
18616 #define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8
18617 
18618 /*
18619  * Register : GPIO/LoanIO 2 Output/Output Enable Mux Selection Register - GPLMUX2
18620  *
18621  * Selection between GPIO and LoanIO output and output enable for GPIO2 and
18622  * LoanIO2. These signals drive the Pin Mux. The Pin Mux must be configured to use
18623  * GPIO/LoanIO in addition to these settings
18624  *
18625  * Only reset by a cold reset (ignores warm reset).
18626  *
18627  * NOTE: These registers should not be modified after IO configuration.There is no
18628  * support for dynamically changing the Pin Mux selections.
18629  *
18630  * Register Layout
18631  *
18632  * Bits | Access | Reset | Description
18633  * :-------|:-------|:------|:---------------------------------------
18634  * [0] | RW | 0x0 | GPIO/Loan IO2Input Mux Selection Field
18635  * [31:1] | ??? | 0x0 | *UNDEFINED*
18636  *
18637  */
18638 /*
18639  * Field : GPIO/Loan IO2Input Mux Selection Field - sel
18640  *
18641  * Select source for GPIO/LoanIO 2.
18642  *
18643  * 0 : LoanIO 2 controls GPIO/LOANIO[2] output and output enable signals.
18644  *
18645  * 1 : GPIO 2 controls GPIO/LOANI[2] output and output enable signals.
18646  *
18647  * Field Access Macros:
18648  *
18649  */
18650 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18651 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0
18652 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18653 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0
18654 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18655 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1
18656 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */
18657 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001
18658 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value. */
18659 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe
18660 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field. */
18661 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0
18662 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX2_SEL field value from a register. */
18663 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0)
18664 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX2_SEL register field value suitable for setting the register. */
18665 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001)
18666 
18667 #ifndef __ASSEMBLY__
18668 /*
18669  * WARNING: The C register and register group struct declarations are provided for
18670  * convenience and illustrative purposes. They should, however, be used with
18671  * caution as the C language standard provides no guarantees about the alignment or
18672  * atomicity of device memory accesses. The recommended practice for writing
18673  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18674  * alt_write_word() functions.
18675  *
18676  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX2.
18677  */
18678 struct ALT_SYSMGR_PINMUX_GPLMUX2_s
18679 {
18680  uint32_t sel : 1; /* GPIO/Loan IO2Input Mux Selection Field */
18681  uint32_t : 31; /* *UNDEFINED* */
18682 };
18683 
18684 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX2. */
18685 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX2_s ALT_SYSMGR_PINMUX_GPLMUX2_t;
18686 #endif /* __ASSEMBLY__ */
18687 
18688 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX2 register from the beginning of the component. */
18689 #define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc
18690 
18691 /*
18692  * Register : GPIO/LoanIO 3 Output/Output Enable Mux Selection Register - GPLMUX3
18693  *
18694  * Selection between GPIO and LoanIO output and output enable for GPIO3 and
18695  * LoanIO3. These signals drive the Pin Mux. The Pin Mux must be configured to use
18696  * GPIO/LoanIO in addition to these settings
18697  *
18698  * Only reset by a cold reset (ignores warm reset).
18699  *
18700  * NOTE: These registers should not be modified after IO configuration.There is no
18701  * support for dynamically changing the Pin Mux selections.
18702  *
18703  * Register Layout
18704  *
18705  * Bits | Access | Reset | Description
18706  * :-------|:-------|:------|:---------------------------------------
18707  * [0] | RW | 0x0 | GPIO/Loan IO3Input Mux Selection Field
18708  * [31:1] | ??? | 0x0 | *UNDEFINED*
18709  *
18710  */
18711 /*
18712  * Field : GPIO/Loan IO3Input Mux Selection Field - sel
18713  *
18714  * Select source for GPIO/LoanIO 3.
18715  *
18716  * 0 : LoanIO 3 controls GPIO/LOANIO[3] output and output enable signals.
18717  *
18718  * 1 : GPIO 3 controls GPIO/LOANI[3] output and output enable signals.
18719  *
18720  * Field Access Macros:
18721  *
18722  */
18723 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18724 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0
18725 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18726 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0
18727 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18728 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1
18729 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */
18730 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001
18731 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value. */
18732 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe
18733 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field. */
18734 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0
18735 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX3_SEL field value from a register. */
18736 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0)
18737 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX3_SEL register field value suitable for setting the register. */
18738 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001)
18739 
18740 #ifndef __ASSEMBLY__
18741 /*
18742  * WARNING: The C register and register group struct declarations are provided for
18743  * convenience and illustrative purposes. They should, however, be used with
18744  * caution as the C language standard provides no guarantees about the alignment or
18745  * atomicity of device memory accesses. The recommended practice for writing
18746  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18747  * alt_write_word() functions.
18748  *
18749  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX3.
18750  */
18751 struct ALT_SYSMGR_PINMUX_GPLMUX3_s
18752 {
18753  uint32_t sel : 1; /* GPIO/Loan IO3Input Mux Selection Field */
18754  uint32_t : 31; /* *UNDEFINED* */
18755 };
18756 
18757 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX3. */
18758 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX3_s ALT_SYSMGR_PINMUX_GPLMUX3_t;
18759 #endif /* __ASSEMBLY__ */
18760 
18761 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX3 register from the beginning of the component. */
18762 #define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0
18763 
18764 /*
18765  * Register : GPIO/LoanIO 4 Output/Output Enable Mux Selection Register - GPLMUX4
18766  *
18767  * Selection between GPIO and LoanIO output and output enable for GPIO4 and
18768  * LoanIO4. These signals drive the Pin Mux. The Pin Mux must be configured to use
18769  * GPIO/LoanIO in addition to these settings
18770  *
18771  * Only reset by a cold reset (ignores warm reset).
18772  *
18773  * NOTE: These registers should not be modified after IO configuration.There is no
18774  * support for dynamically changing the Pin Mux selections.
18775  *
18776  * Register Layout
18777  *
18778  * Bits | Access | Reset | Description
18779  * :-------|:-------|:------|:---------------------------------------
18780  * [0] | RW | 0x0 | GPIO/Loan IO4Input Mux Selection Field
18781  * [31:1] | ??? | 0x0 | *UNDEFINED*
18782  *
18783  */
18784 /*
18785  * Field : GPIO/Loan IO4Input Mux Selection Field - sel
18786  *
18787  * Select source for GPIO/LoanIO 4.
18788  *
18789  * 0 : LoanIO 4 controls GPIO/LOANIO[4] output and output enable signals.
18790  *
18791  * 1 : GPIO 4 controls GPIO/LOANI[4] output and output enable signals.
18792  *
18793  * Field Access Macros:
18794  *
18795  */
18796 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18797 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0
18798 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18799 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0
18800 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18801 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1
18802 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */
18803 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001
18804 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value. */
18805 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe
18806 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field. */
18807 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0
18808 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX4_SEL field value from a register. */
18809 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0)
18810 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX4_SEL register field value suitable for setting the register. */
18811 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001)
18812 
18813 #ifndef __ASSEMBLY__
18814 /*
18815  * WARNING: The C register and register group struct declarations are provided for
18816  * convenience and illustrative purposes. They should, however, be used with
18817  * caution as the C language standard provides no guarantees about the alignment or
18818  * atomicity of device memory accesses. The recommended practice for writing
18819  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18820  * alt_write_word() functions.
18821  *
18822  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX4.
18823  */
18824 struct ALT_SYSMGR_PINMUX_GPLMUX4_s
18825 {
18826  uint32_t sel : 1; /* GPIO/Loan IO4Input Mux Selection Field */
18827  uint32_t : 31; /* *UNDEFINED* */
18828 };
18829 
18830 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX4. */
18831 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX4_s ALT_SYSMGR_PINMUX_GPLMUX4_t;
18832 #endif /* __ASSEMBLY__ */
18833 
18834 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX4 register from the beginning of the component. */
18835 #define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4
18836 
18837 /*
18838  * Register : GPIO/LoanIO 5 Output/Output Enable Mux Selection Register - GPLMUX5
18839  *
18840  * Selection between GPIO and LoanIO output and output enable for GPIO5 and
18841  * LoanIO5. These signals drive the Pin Mux. The Pin Mux must be configured to use
18842  * GPIO/LoanIO in addition to these settings
18843  *
18844  * Only reset by a cold reset (ignores warm reset).
18845  *
18846  * NOTE: These registers should not be modified after IO configuration.There is no
18847  * support for dynamically changing the Pin Mux selections.
18848  *
18849  * Register Layout
18850  *
18851  * Bits | Access | Reset | Description
18852  * :-------|:-------|:------|:---------------------------------------
18853  * [0] | RW | 0x0 | GPIO/Loan IO5Input Mux Selection Field
18854  * [31:1] | ??? | 0x0 | *UNDEFINED*
18855  *
18856  */
18857 /*
18858  * Field : GPIO/Loan IO5Input Mux Selection Field - sel
18859  *
18860  * Select source for GPIO/LoanIO 5.
18861  *
18862  * 0 : LoanIO 5 controls GPIO/LOANIO[5] output and output enable signals.
18863  *
18864  * 1 : GPIO 5 controls GPIO/LOANI[5] output and output enable signals.
18865  *
18866  * Field Access Macros:
18867  *
18868  */
18869 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18870 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0
18871 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18872 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0
18873 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18874 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1
18875 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */
18876 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001
18877 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value. */
18878 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe
18879 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field. */
18880 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0
18881 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX5_SEL field value from a register. */
18882 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0)
18883 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX5_SEL register field value suitable for setting the register. */
18884 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001)
18885 
18886 #ifndef __ASSEMBLY__
18887 /*
18888  * WARNING: The C register and register group struct declarations are provided for
18889  * convenience and illustrative purposes. They should, however, be used with
18890  * caution as the C language standard provides no guarantees about the alignment or
18891  * atomicity of device memory accesses. The recommended practice for writing
18892  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18893  * alt_write_word() functions.
18894  *
18895  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX5.
18896  */
18897 struct ALT_SYSMGR_PINMUX_GPLMUX5_s
18898 {
18899  uint32_t sel : 1; /* GPIO/Loan IO5Input Mux Selection Field */
18900  uint32_t : 31; /* *UNDEFINED* */
18901 };
18902 
18903 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX5. */
18904 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX5_s ALT_SYSMGR_PINMUX_GPLMUX5_t;
18905 #endif /* __ASSEMBLY__ */
18906 
18907 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX5 register from the beginning of the component. */
18908 #define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8
18909 
18910 /*
18911  * Register : GPIO/LoanIO 6 Output/Output Enable Mux Selection Register - GPLMUX6
18912  *
18913  * Selection between GPIO and LoanIO output and output enable for GPIO6 and
18914  * LoanIO6. These signals drive the Pin Mux. The Pin Mux must be configured to use
18915  * GPIO/LoanIO in addition to these settings
18916  *
18917  * Only reset by a cold reset (ignores warm reset).
18918  *
18919  * NOTE: These registers should not be modified after IO configuration.There is no
18920  * support for dynamically changing the Pin Mux selections.
18921  *
18922  * Register Layout
18923  *
18924  * Bits | Access | Reset | Description
18925  * :-------|:-------|:------|:---------------------------------------
18926  * [0] | RW | 0x0 | GPIO/Loan IO6Input Mux Selection Field
18927  * [31:1] | ??? | 0x0 | *UNDEFINED*
18928  *
18929  */
18930 /*
18931  * Field : GPIO/Loan IO6Input Mux Selection Field - sel
18932  *
18933  * Select source for GPIO/LoanIO 6.
18934  *
18935  * 0 : LoanIO 6 controls GPIO/LOANIO[6] output and output enable signals.
18936  *
18937  * 1 : GPIO 6 controls GPIO/LOANI[6] output and output enable signals.
18938  *
18939  * Field Access Macros:
18940  *
18941  */
18942 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18943 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0
18944 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18945 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0
18946 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18947 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1
18948 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */
18949 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001
18950 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value. */
18951 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe
18952 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field. */
18953 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0
18954 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX6_SEL field value from a register. */
18955 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0)
18956 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX6_SEL register field value suitable for setting the register. */
18957 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001)
18958 
18959 #ifndef __ASSEMBLY__
18960 /*
18961  * WARNING: The C register and register group struct declarations are provided for
18962  * convenience and illustrative purposes. They should, however, be used with
18963  * caution as the C language standard provides no guarantees about the alignment or
18964  * atomicity of device memory accesses. The recommended practice for writing
18965  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
18966  * alt_write_word() functions.
18967  *
18968  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX6.
18969  */
18970 struct ALT_SYSMGR_PINMUX_GPLMUX6_s
18971 {
18972  uint32_t sel : 1; /* GPIO/Loan IO6Input Mux Selection Field */
18973  uint32_t : 31; /* *UNDEFINED* */
18974 };
18975 
18976 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX6. */
18977 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX6_s ALT_SYSMGR_PINMUX_GPLMUX6_t;
18978 #endif /* __ASSEMBLY__ */
18979 
18980 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX6 register from the beginning of the component. */
18981 #define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec
18982 
18983 /*
18984  * Register : GPIO/LoanIO 7 Output/Output Enable Mux Selection Register - GPLMUX7
18985  *
18986  * Selection between GPIO and LoanIO output and output enable for GPIO7 and
18987  * LoanIO7. These signals drive the Pin Mux. The Pin Mux must be configured to use
18988  * GPIO/LoanIO in addition to these settings
18989  *
18990  * Only reset by a cold reset (ignores warm reset).
18991  *
18992  * NOTE: These registers should not be modified after IO configuration.There is no
18993  * support for dynamically changing the Pin Mux selections.
18994  *
18995  * Register Layout
18996  *
18997  * Bits | Access | Reset | Description
18998  * :-------|:-------|:------|:---------------------------------------
18999  * [0] | RW | 0x0 | GPIO/Loan IO7Input Mux Selection Field
19000  * [31:1] | ??? | 0x0 | *UNDEFINED*
19001  *
19002  */
19003 /*
19004  * Field : GPIO/Loan IO7Input Mux Selection Field - sel
19005  *
19006  * Select source for GPIO/LoanIO 7.
19007  *
19008  * 0 : LoanIO 7 controls GPIO/LOANIO[7] output and output enable signals.
19009  *
19010  * 1 : GPIO 7 controls GPIO/LOANI[7] output and output enable signals.
19011  *
19012  * Field Access Macros:
19013  *
19014  */
19015 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19016 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0
19017 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19018 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0
19019 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19020 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1
19021 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */
19022 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001
19023 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value. */
19024 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe
19025 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field. */
19026 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0
19027 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX7_SEL field value from a register. */
19028 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0)
19029 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX7_SEL register field value suitable for setting the register. */
19030 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001)
19031 
19032 #ifndef __ASSEMBLY__
19033 /*
19034  * WARNING: The C register and register group struct declarations are provided for
19035  * convenience and illustrative purposes. They should, however, be used with
19036  * caution as the C language standard provides no guarantees about the alignment or
19037  * atomicity of device memory accesses. The recommended practice for writing
19038  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19039  * alt_write_word() functions.
19040  *
19041  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX7.
19042  */
19043 struct ALT_SYSMGR_PINMUX_GPLMUX7_s
19044 {
19045  uint32_t sel : 1; /* GPIO/Loan IO7Input Mux Selection Field */
19046  uint32_t : 31; /* *UNDEFINED* */
19047 };
19048 
19049 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX7. */
19050 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX7_s ALT_SYSMGR_PINMUX_GPLMUX7_t;
19051 #endif /* __ASSEMBLY__ */
19052 
19053 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX7 register from the beginning of the component. */
19054 #define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0
19055 
19056 /*
19057  * Register : GPIO/LoanIO 8 Output/Output Enable Mux Selection Register - GPLMUX8
19058  *
19059  * Selection between GPIO and LoanIO output and output enable for GPIO8 and
19060  * LoanIO8. These signals drive the Pin Mux. The Pin Mux must be configured to use
19061  * GPIO/LoanIO in addition to these settings
19062  *
19063  * Only reset by a cold reset (ignores warm reset).
19064  *
19065  * NOTE: These registers should not be modified after IO configuration.There is no
19066  * support for dynamically changing the Pin Mux selections.
19067  *
19068  * Register Layout
19069  *
19070  * Bits | Access | Reset | Description
19071  * :-------|:-------|:------|:---------------------------------------
19072  * [0] | RW | 0x0 | GPIO/Loan IO8Input Mux Selection Field
19073  * [31:1] | ??? | 0x0 | *UNDEFINED*
19074  *
19075  */
19076 /*
19077  * Field : GPIO/Loan IO8Input Mux Selection Field - sel
19078  *
19079  * Select source for GPIO/LoanIO 8.
19080  *
19081  * 0 : LoanIO 8 controls GPIO/LOANIO[8] output and output enable signals.
19082  *
19083  * 1 : GPIO 8 controls GPIO/LOANI[8] output and output enable signals.
19084  *
19085  * Field Access Macros:
19086  *
19087  */
19088 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19089 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0
19090 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19091 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0
19092 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19093 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1
19094 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */
19095 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001
19096 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value. */
19097 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe
19098 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field. */
19099 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0
19100 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX8_SEL field value from a register. */
19101 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0)
19102 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX8_SEL register field value suitable for setting the register. */
19103 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001)
19104 
19105 #ifndef __ASSEMBLY__
19106 /*
19107  * WARNING: The C register and register group struct declarations are provided for
19108  * convenience and illustrative purposes. They should, however, be used with
19109  * caution as the C language standard provides no guarantees about the alignment or
19110  * atomicity of device memory accesses. The recommended practice for writing
19111  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19112  * alt_write_word() functions.
19113  *
19114  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX8.
19115  */
19116 struct ALT_SYSMGR_PINMUX_GPLMUX8_s
19117 {
19118  uint32_t sel : 1; /* GPIO/Loan IO8Input Mux Selection Field */
19119  uint32_t : 31; /* *UNDEFINED* */
19120 };
19121 
19122 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX8. */
19123 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX8_s ALT_SYSMGR_PINMUX_GPLMUX8_t;
19124 #endif /* __ASSEMBLY__ */
19125 
19126 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX8 register from the beginning of the component. */
19127 #define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4
19128 
19129 /*
19130  * Register : GPIO/LoanIO 9 Output/Output Enable Mux Selection Register - GPLMUX9
19131  *
19132  * Selection between GPIO and LoanIO output and output enable for GPIO9 and
19133  * LoanIO9. These signals drive the Pin Mux. The Pin Mux must be configured to use
19134  * GPIO/LoanIO in addition to these settings
19135  *
19136  * Only reset by a cold reset (ignores warm reset).
19137  *
19138  * NOTE: These registers should not be modified after IO configuration.There is no
19139  * support for dynamically changing the Pin Mux selections.
19140  *
19141  * Register Layout
19142  *
19143  * Bits | Access | Reset | Description
19144  * :-------|:-------|:------|:---------------------------------------
19145  * [0] | RW | 0x0 | GPIO/Loan IO9Input Mux Selection Field
19146  * [31:1] | ??? | 0x0 | *UNDEFINED*
19147  *
19148  */
19149 /*
19150  * Field : GPIO/Loan IO9Input Mux Selection Field - sel
19151  *
19152  * Select source for GPIO/LoanIO 9.
19153  *
19154  * 0 : LoanIO 9 controls GPIO/LOANIO[9] output and output enable signals.
19155  *
19156  * 1 : GPIO 9 controls GPIO/LOANI[9] output and output enable signals.
19157  *
19158  * Field Access Macros:
19159  *
19160  */
19161 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19162 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0
19163 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19164 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0
19165 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19166 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1
19167 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */
19168 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001
19169 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value. */
19170 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe
19171 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field. */
19172 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0
19173 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX9_SEL field value from a register. */
19174 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0)
19175 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX9_SEL register field value suitable for setting the register. */
19176 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001)
19177 
19178 #ifndef __ASSEMBLY__
19179 /*
19180  * WARNING: The C register and register group struct declarations are provided for
19181  * convenience and illustrative purposes. They should, however, be used with
19182  * caution as the C language standard provides no guarantees about the alignment or
19183  * atomicity of device memory accesses. The recommended practice for writing
19184  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19185  * alt_write_word() functions.
19186  *
19187  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX9.
19188  */
19189 struct ALT_SYSMGR_PINMUX_GPLMUX9_s
19190 {
19191  uint32_t sel : 1; /* GPIO/Loan IO9Input Mux Selection Field */
19192  uint32_t : 31; /* *UNDEFINED* */
19193 };
19194 
19195 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX9. */
19196 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX9_s ALT_SYSMGR_PINMUX_GPLMUX9_t;
19197 #endif /* __ASSEMBLY__ */
19198 
19199 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX9 register from the beginning of the component. */
19200 #define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8
19201 
19202 /*
19203  * Register : GPIO/LoanIO 10 Output/Output Enable Mux Selection Register - GPLMUX10
19204  *
19205  * Selection between GPIO and LoanIO output and output enable for GPIO10 and
19206  * LoanIO10. These signals drive the Pin Mux. The Pin Mux must be configured to use
19207  * GPIO/LoanIO in addition to these settings
19208  *
19209  * Only reset by a cold reset (ignores warm reset).
19210  *
19211  * NOTE: These registers should not be modified after IO configuration.There is no
19212  * support for dynamically changing the Pin Mux selections.
19213  *
19214  * Register Layout
19215  *
19216  * Bits | Access | Reset | Description
19217  * :-------|:-------|:------|:----------------------------------------
19218  * [0] | RW | 0x0 | GPIO/Loan IO10Input Mux Selection Field
19219  * [31:1] | ??? | 0x0 | *UNDEFINED*
19220  *
19221  */
19222 /*
19223  * Field : GPIO/Loan IO10Input Mux Selection Field - sel
19224  *
19225  * Select source for GPIO/LoanIO 10.
19226  *
19227  * 0 : LoanIO 10 controls GPIO/LOANIO[10] output and output enable signals.
19228  *
19229  * 1 : GPIO 10 controls GPIO/LOANI[10] output and output enable signals.
19230  *
19231  * Field Access Macros:
19232  *
19233  */
19234 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19235 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0
19236 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19237 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0
19238 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19239 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1
19240 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */
19241 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001
19242 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value. */
19243 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe
19244 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field. */
19245 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0
19246 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX10_SEL field value from a register. */
19247 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0)
19248 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX10_SEL register field value suitable for setting the register. */
19249 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001)
19250 
19251 #ifndef __ASSEMBLY__
19252 /*
19253  * WARNING: The C register and register group struct declarations are provided for
19254  * convenience and illustrative purposes. They should, however, be used with
19255  * caution as the C language standard provides no guarantees about the alignment or
19256  * atomicity of device memory accesses. The recommended practice for writing
19257  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19258  * alt_write_word() functions.
19259  *
19260  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX10.
19261  */
19262 struct ALT_SYSMGR_PINMUX_GPLMUX10_s
19263 {
19264  uint32_t sel : 1; /* GPIO/Loan IO10Input Mux Selection Field */
19265  uint32_t : 31; /* *UNDEFINED* */
19266 };
19267 
19268 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX10. */
19269 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX10_s ALT_SYSMGR_PINMUX_GPLMUX10_t;
19270 #endif /* __ASSEMBLY__ */
19271 
19272 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX10 register from the beginning of the component. */
19273 #define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc
19274 
19275 /*
19276  * Register : GPIO/LoanIO 11 Output/Output Enable Mux Selection Register - GPLMUX11
19277  *
19278  * Selection between GPIO and LoanIO output and output enable for GPIO11 and
19279  * LoanIO11. These signals drive the Pin Mux. The Pin Mux must be configured to use
19280  * GPIO/LoanIO in addition to these settings
19281  *
19282  * Only reset by a cold reset (ignores warm reset).
19283  *
19284  * NOTE: These registers should not be modified after IO configuration.There is no
19285  * support for dynamically changing the Pin Mux selections.
19286  *
19287  * Register Layout
19288  *
19289  * Bits | Access | Reset | Description
19290  * :-------|:-------|:------|:----------------------------------------
19291  * [0] | RW | 0x0 | GPIO/Loan IO11Input Mux Selection Field
19292  * [31:1] | ??? | 0x0 | *UNDEFINED*
19293  *
19294  */
19295 /*
19296  * Field : GPIO/Loan IO11Input Mux Selection Field - sel
19297  *
19298  * Select source for GPIO/LoanIO 11.
19299  *
19300  * 0 : LoanIO 11 controls GPIO/LOANIO[11] output and output enable signals.
19301  *
19302  * 1 : GPIO 11 controls GPIO/LOANI[11] output and output enable signals.
19303  *
19304  * Field Access Macros:
19305  *
19306  */
19307 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19308 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0
19309 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19310 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0
19311 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19312 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1
19313 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */
19314 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001
19315 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value. */
19316 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe
19317 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field. */
19318 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0
19319 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX11_SEL field value from a register. */
19320 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0)
19321 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX11_SEL register field value suitable for setting the register. */
19322 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001)
19323 
19324 #ifndef __ASSEMBLY__
19325 /*
19326  * WARNING: The C register and register group struct declarations are provided for
19327  * convenience and illustrative purposes. They should, however, be used with
19328  * caution as the C language standard provides no guarantees about the alignment or
19329  * atomicity of device memory accesses. The recommended practice for writing
19330  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19331  * alt_write_word() functions.
19332  *
19333  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX11.
19334  */
19335 struct ALT_SYSMGR_PINMUX_GPLMUX11_s
19336 {
19337  uint32_t sel : 1; /* GPIO/Loan IO11Input Mux Selection Field */
19338  uint32_t : 31; /* *UNDEFINED* */
19339 };
19340 
19341 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX11. */
19342 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX11_s ALT_SYSMGR_PINMUX_GPLMUX11_t;
19343 #endif /* __ASSEMBLY__ */
19344 
19345 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX11 register from the beginning of the component. */
19346 #define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200
19347 
19348 /*
19349  * Register : GPIO/LoanIO 12 Output/Output Enable Mux Selection Register - GPLMUX12
19350  *
19351  * Selection between GPIO and LoanIO output and output enable for GPIO12 and
19352  * LoanIO12. These signals drive the Pin Mux. The Pin Mux must be configured to use
19353  * GPIO/LoanIO in addition to these settings
19354  *
19355  * Only reset by a cold reset (ignores warm reset).
19356  *
19357  * NOTE: These registers should not be modified after IO configuration.There is no
19358  * support for dynamically changing the Pin Mux selections.
19359  *
19360  * Register Layout
19361  *
19362  * Bits | Access | Reset | Description
19363  * :-------|:-------|:------|:----------------------------------------
19364  * [0] | RW | 0x0 | GPIO/Loan IO12Input Mux Selection Field
19365  * [31:1] | ??? | 0x0 | *UNDEFINED*
19366  *
19367  */
19368 /*
19369  * Field : GPIO/Loan IO12Input Mux Selection Field - sel
19370  *
19371  * Select source for GPIO/LoanIO 12.
19372  *
19373  * 0 : LoanIO 12 controls GPIO/LOANIO[12] output and output enable signals.
19374  *
19375  * 1 : GPIO 12 controls GPIO/LOANI[12] output and output enable signals.
19376  *
19377  * Field Access Macros:
19378  *
19379  */
19380 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19381 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0
19382 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19383 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0
19384 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19385 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1
19386 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */
19387 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001
19388 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value. */
19389 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe
19390 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field. */
19391 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0
19392 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX12_SEL field value from a register. */
19393 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0)
19394 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX12_SEL register field value suitable for setting the register. */
19395 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001)
19396 
19397 #ifndef __ASSEMBLY__
19398 /*
19399  * WARNING: The C register and register group struct declarations are provided for
19400  * convenience and illustrative purposes. They should, however, be used with
19401  * caution as the C language standard provides no guarantees about the alignment or
19402  * atomicity of device memory accesses. The recommended practice for writing
19403  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19404  * alt_write_word() functions.
19405  *
19406  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX12.
19407  */
19408 struct ALT_SYSMGR_PINMUX_GPLMUX12_s
19409 {
19410  uint32_t sel : 1; /* GPIO/Loan IO12Input Mux Selection Field */
19411  uint32_t : 31; /* *UNDEFINED* */
19412 };
19413 
19414 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX12. */
19415 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX12_s ALT_SYSMGR_PINMUX_GPLMUX12_t;
19416 #endif /* __ASSEMBLY__ */
19417 
19418 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX12 register from the beginning of the component. */
19419 #define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204
19420 
19421 /*
19422  * Register : GPIO/LoanIO 13 Output/Output Enable Mux Selection Register - GPLMUX13
19423  *
19424  * Selection between GPIO and LoanIO output and output enable for GPIO13 and
19425  * LoanIO13. These signals drive the Pin Mux. The Pin Mux must be configured to use
19426  * GPIO/LoanIO in addition to these settings
19427  *
19428  * Only reset by a cold reset (ignores warm reset).
19429  *
19430  * NOTE: These registers should not be modified after IO configuration.There is no
19431  * support for dynamically changing the Pin Mux selections.
19432  *
19433  * Register Layout
19434  *
19435  * Bits | Access | Reset | Description
19436  * :-------|:-------|:------|:----------------------------------------
19437  * [0] | RW | 0x0 | GPIO/Loan IO13Input Mux Selection Field
19438  * [31:1] | ??? | 0x0 | *UNDEFINED*
19439  *
19440  */
19441 /*
19442  * Field : GPIO/Loan IO13Input Mux Selection Field - sel
19443  *
19444  * Select source for GPIO/LoanIO 13.
19445  *
19446  * 0 : LoanIO 13 controls GPIO/LOANIO[13] output and output enable signals.
19447  *
19448  * 1 : GPIO 13 controls GPIO/LOANI[13] output and output enable signals.
19449  *
19450  * Field Access Macros:
19451  *
19452  */
19453 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19454 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0
19455 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19456 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0
19457 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19458 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1
19459 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */
19460 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001
19461 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value. */
19462 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe
19463 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field. */
19464 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0
19465 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX13_SEL field value from a register. */
19466 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0)
19467 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX13_SEL register field value suitable for setting the register. */
19468 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001)
19469 
19470 #ifndef __ASSEMBLY__
19471 /*
19472  * WARNING: The C register and register group struct declarations are provided for
19473  * convenience and illustrative purposes. They should, however, be used with
19474  * caution as the C language standard provides no guarantees about the alignment or
19475  * atomicity of device memory accesses. The recommended practice for writing
19476  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19477  * alt_write_word() functions.
19478  *
19479  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX13.
19480  */
19481 struct ALT_SYSMGR_PINMUX_GPLMUX13_s
19482 {
19483  uint32_t sel : 1; /* GPIO/Loan IO13Input Mux Selection Field */
19484  uint32_t : 31; /* *UNDEFINED* */
19485 };
19486 
19487 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX13. */
19488 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX13_s ALT_SYSMGR_PINMUX_GPLMUX13_t;
19489 #endif /* __ASSEMBLY__ */
19490 
19491 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX13 register from the beginning of the component. */
19492 #define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208
19493 
19494 /*
19495  * Register : GPIO/LoanIO 14 Output/Output Enable Mux Selection Register - GPLMUX14
19496  *
19497  * Selection between GPIO and LoanIO output and output enable for GPIO14 and
19498  * LoanIO14. These signals drive the Pin Mux. The Pin Mux must be configured to use
19499  * GPIO/LoanIO in addition to these settings
19500  *
19501  * Only reset by a cold reset (ignores warm reset).
19502  *
19503  * NOTE: These registers should not be modified after IO configuration.There is no
19504  * support for dynamically changing the Pin Mux selections.
19505  *
19506  * Register Layout
19507  *
19508  * Bits | Access | Reset | Description
19509  * :-------|:-------|:------|:----------------------------------------
19510  * [0] | RW | 0x0 | GPIO/Loan IO14Input Mux Selection Field
19511  * [31:1] | ??? | 0x0 | *UNDEFINED*
19512  *
19513  */
19514 /*
19515  * Field : GPIO/Loan IO14Input Mux Selection Field - sel
19516  *
19517  * Select source for GPIO/LoanIO 14.
19518  *
19519  * 0 : LoanIO 14 controls GPIO/LOANIO[14] output and output enable signals.
19520  *
19521  * 1 : GPIO 14 controls GPIO/LOANI[14] output and output enable signals.
19522  *
19523  * Field Access Macros:
19524  *
19525  */
19526 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19527 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0
19528 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19529 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0
19530 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19531 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1
19532 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */
19533 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001
19534 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value. */
19535 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe
19536 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field. */
19537 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0
19538 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX14_SEL field value from a register. */
19539 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0)
19540 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX14_SEL register field value suitable for setting the register. */
19541 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001)
19542 
19543 #ifndef __ASSEMBLY__
19544 /*
19545  * WARNING: The C register and register group struct declarations are provided for
19546  * convenience and illustrative purposes. They should, however, be used with
19547  * caution as the C language standard provides no guarantees about the alignment or
19548  * atomicity of device memory accesses. The recommended practice for writing
19549  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19550  * alt_write_word() functions.
19551  *
19552  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX14.
19553  */
19554 struct ALT_SYSMGR_PINMUX_GPLMUX14_s
19555 {
19556  uint32_t sel : 1; /* GPIO/Loan IO14Input Mux Selection Field */
19557  uint32_t : 31; /* *UNDEFINED* */
19558 };
19559 
19560 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX14. */
19561 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX14_s ALT_SYSMGR_PINMUX_GPLMUX14_t;
19562 #endif /* __ASSEMBLY__ */
19563 
19564 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX14 register from the beginning of the component. */
19565 #define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c
19566 
19567 /*
19568  * Register : GPIO/LoanIO 15 Output/Output Enable Mux Selection Register - GPLMUX15
19569  *
19570  * Selection between GPIO and LoanIO output and output enable for GPIO15 and
19571  * LoanIO15. These signals drive the Pin Mux. The Pin Mux must be configured to use
19572  * GPIO/LoanIO in addition to these settings
19573  *
19574  * Only reset by a cold reset (ignores warm reset).
19575  *
19576  * NOTE: These registers should not be modified after IO configuration.There is no
19577  * support for dynamically changing the Pin Mux selections.
19578  *
19579  * Register Layout
19580  *
19581  * Bits | Access | Reset | Description
19582  * :-------|:-------|:------|:----------------------------------------
19583  * [0] | RW | 0x0 | GPIO/Loan IO15Input Mux Selection Field
19584  * [31:1] | ??? | 0x0 | *UNDEFINED*
19585  *
19586  */
19587 /*
19588  * Field : GPIO/Loan IO15Input Mux Selection Field - sel
19589  *
19590  * Select source for GPIO/LoanIO 15.
19591  *
19592  * 0 : LoanIO 15 controls GPIO/LOANIO[15] output and output enable signals.
19593  *
19594  * 1 : GPIO 15 controls GPIO/LOANI[15] output and output enable signals.
19595  *
19596  * Field Access Macros:
19597  *
19598  */
19599 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19600 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0
19601 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19602 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0
19603 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19604 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1
19605 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */
19606 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001
19607 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value. */
19608 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe
19609 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field. */
19610 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0
19611 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX15_SEL field value from a register. */
19612 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0)
19613 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX15_SEL register field value suitable for setting the register. */
19614 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001)
19615 
19616 #ifndef __ASSEMBLY__
19617 /*
19618  * WARNING: The C register and register group struct declarations are provided for
19619  * convenience and illustrative purposes. They should, however, be used with
19620  * caution as the C language standard provides no guarantees about the alignment or
19621  * atomicity of device memory accesses. The recommended practice for writing
19622  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19623  * alt_write_word() functions.
19624  *
19625  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX15.
19626  */
19627 struct ALT_SYSMGR_PINMUX_GPLMUX15_s
19628 {
19629  uint32_t sel : 1; /* GPIO/Loan IO15Input Mux Selection Field */
19630  uint32_t : 31; /* *UNDEFINED* */
19631 };
19632 
19633 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX15. */
19634 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX15_s ALT_SYSMGR_PINMUX_GPLMUX15_t;
19635 #endif /* __ASSEMBLY__ */
19636 
19637 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX15 register from the beginning of the component. */
19638 #define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210
19639 
19640 /*
19641  * Register : GPIO/LoanIO 16 Output/Output Enable Mux Selection Register - GPLMUX16
19642  *
19643  * Selection between GPIO and LoanIO output and output enable for GPIO16 and
19644  * LoanIO16. These signals drive the Pin Mux. The Pin Mux must be configured to use
19645  * GPIO/LoanIO in addition to these settings
19646  *
19647  * Only reset by a cold reset (ignores warm reset).
19648  *
19649  * NOTE: These registers should not be modified after IO configuration.There is no
19650  * support for dynamically changing the Pin Mux selections.
19651  *
19652  * Register Layout
19653  *
19654  * Bits | Access | Reset | Description
19655  * :-------|:-------|:------|:----------------------------------------
19656  * [0] | RW | 0x0 | GPIO/Loan IO16Input Mux Selection Field
19657  * [31:1] | ??? | 0x0 | *UNDEFINED*
19658  *
19659  */
19660 /*
19661  * Field : GPIO/Loan IO16Input Mux Selection Field - sel
19662  *
19663  * Select source for GPIO/LoanIO 16.
19664  *
19665  * 0 : LoanIO 16 controls GPIO/LOANIO[16] output and output enable signals.
19666  *
19667  * 1 : GPIO 16 controls GPIO/LOANI[16] output and output enable signals.
19668  *
19669  * Field Access Macros:
19670  *
19671  */
19672 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19673 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0
19674 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19675 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0
19676 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19677 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1
19678 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */
19679 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001
19680 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value. */
19681 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe
19682 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field. */
19683 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0
19684 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX16_SEL field value from a register. */
19685 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0)
19686 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX16_SEL register field value suitable for setting the register. */
19687 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001)
19688 
19689 #ifndef __ASSEMBLY__
19690 /*
19691  * WARNING: The C register and register group struct declarations are provided for
19692  * convenience and illustrative purposes. They should, however, be used with
19693  * caution as the C language standard provides no guarantees about the alignment or
19694  * atomicity of device memory accesses. The recommended practice for writing
19695  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19696  * alt_write_word() functions.
19697  *
19698  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX16.
19699  */
19700 struct ALT_SYSMGR_PINMUX_GPLMUX16_s
19701 {
19702  uint32_t sel : 1; /* GPIO/Loan IO16Input Mux Selection Field */
19703  uint32_t : 31; /* *UNDEFINED* */
19704 };
19705 
19706 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX16. */
19707 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX16_s ALT_SYSMGR_PINMUX_GPLMUX16_t;
19708 #endif /* __ASSEMBLY__ */
19709 
19710 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX16 register from the beginning of the component. */
19711 #define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214
19712 
19713 /*
19714  * Register : GPIO/LoanIO 17 Output/Output Enable Mux Selection Register - GPLMUX17
19715  *
19716  * Selection between GPIO and LoanIO output and output enable for GPIO17 and
19717  * LoanIO17. These signals drive the Pin Mux. The Pin Mux must be configured to use
19718  * GPIO/LoanIO in addition to these settings
19719  *
19720  * Only reset by a cold reset (ignores warm reset).
19721  *
19722  * NOTE: These registers should not be modified after IO configuration.There is no
19723  * support for dynamically changing the Pin Mux selections.
19724  *
19725  * Register Layout
19726  *
19727  * Bits | Access | Reset | Description
19728  * :-------|:-------|:------|:----------------------------------------
19729  * [0] | RW | 0x0 | GPIO/Loan IO17Input Mux Selection Field
19730  * [31:1] | ??? | 0x0 | *UNDEFINED*
19731  *
19732  */
19733 /*
19734  * Field : GPIO/Loan IO17Input Mux Selection Field - sel
19735  *
19736  * Select source for GPIO/LoanIO 17.
19737  *
19738  * 0 : LoanIO 17 controls GPIO/LOANIO[17] output and output enable signals.
19739  *
19740  * 1 : GPIO 17 controls GPIO/LOANI[17] output and output enable signals.
19741  *
19742  * Field Access Macros:
19743  *
19744  */
19745 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19746 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0
19747 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19748 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0
19749 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19750 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1
19751 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */
19752 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001
19753 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value. */
19754 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe
19755 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field. */
19756 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0
19757 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX17_SEL field value from a register. */
19758 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0)
19759 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX17_SEL register field value suitable for setting the register. */
19760 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001)
19761 
19762 #ifndef __ASSEMBLY__
19763 /*
19764  * WARNING: The C register and register group struct declarations are provided for
19765  * convenience and illustrative purposes. They should, however, be used with
19766  * caution as the C language standard provides no guarantees about the alignment or
19767  * atomicity of device memory accesses. The recommended practice for writing
19768  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19769  * alt_write_word() functions.
19770  *
19771  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX17.
19772  */
19773 struct ALT_SYSMGR_PINMUX_GPLMUX17_s
19774 {
19775  uint32_t sel : 1; /* GPIO/Loan IO17Input Mux Selection Field */
19776  uint32_t : 31; /* *UNDEFINED* */
19777 };
19778 
19779 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX17. */
19780 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX17_s ALT_SYSMGR_PINMUX_GPLMUX17_t;
19781 #endif /* __ASSEMBLY__ */
19782 
19783 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX17 register from the beginning of the component. */
19784 #define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218
19785 
19786 /*
19787  * Register : GPIO/LoanIO 18 Output/Output Enable Mux Selection Register - GPLMUX18
19788  *
19789  * Selection between GPIO and LoanIO output and output enable for GPIO18 and
19790  * LoanIO18. These signals drive the Pin Mux. The Pin Mux must be configured to use
19791  * GPIO/LoanIO in addition to these settings
19792  *
19793  * Only reset by a cold reset (ignores warm reset).
19794  *
19795  * NOTE: These registers should not be modified after IO configuration.There is no
19796  * support for dynamically changing the Pin Mux selections.
19797  *
19798  * Register Layout
19799  *
19800  * Bits | Access | Reset | Description
19801  * :-------|:-------|:------|:----------------------------------------
19802  * [0] | RW | 0x0 | GPIO/Loan IO18Input Mux Selection Field
19803  * [31:1] | ??? | 0x0 | *UNDEFINED*
19804  *
19805  */
19806 /*
19807  * Field : GPIO/Loan IO18Input Mux Selection Field - sel
19808  *
19809  * Select source for GPIO/LoanIO 18.
19810  *
19811  * 0 : LoanIO 18 controls GPIO/LOANIO[18] output and output enable signals.
19812  *
19813  * 1 : GPIO 18 controls GPIO/LOANI[18] output and output enable signals.
19814  *
19815  * Field Access Macros:
19816  *
19817  */
19818 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19819 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0
19820 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19821 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0
19822 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19823 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1
19824 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */
19825 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001
19826 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value. */
19827 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe
19828 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field. */
19829 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0
19830 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX18_SEL field value from a register. */
19831 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0)
19832 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX18_SEL register field value suitable for setting the register. */
19833 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001)
19834 
19835 #ifndef __ASSEMBLY__
19836 /*
19837  * WARNING: The C register and register group struct declarations are provided for
19838  * convenience and illustrative purposes. They should, however, be used with
19839  * caution as the C language standard provides no guarantees about the alignment or
19840  * atomicity of device memory accesses. The recommended practice for writing
19841  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19842  * alt_write_word() functions.
19843  *
19844  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX18.
19845  */
19846 struct ALT_SYSMGR_PINMUX_GPLMUX18_s
19847 {
19848  uint32_t sel : 1; /* GPIO/Loan IO18Input Mux Selection Field */
19849  uint32_t : 31; /* *UNDEFINED* */
19850 };
19851 
19852 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX18. */
19853 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX18_s ALT_SYSMGR_PINMUX_GPLMUX18_t;
19854 #endif /* __ASSEMBLY__ */
19855 
19856 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX18 register from the beginning of the component. */
19857 #define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c
19858 
19859 /*
19860  * Register : GPIO/LoanIO 19 Output/Output Enable Mux Selection Register - GPLMUX19
19861  *
19862  * Selection between GPIO and LoanIO output and output enable for GPIO19 and
19863  * LoanIO19. These signals drive the Pin Mux. The Pin Mux must be configured to use
19864  * GPIO/LoanIO in addition to these settings
19865  *
19866  * Only reset by a cold reset (ignores warm reset).
19867  *
19868  * NOTE: These registers should not be modified after IO configuration.There is no
19869  * support for dynamically changing the Pin Mux selections.
19870  *
19871  * Register Layout
19872  *
19873  * Bits | Access | Reset | Description
19874  * :-------|:-------|:------|:----------------------------------------
19875  * [0] | RW | 0x0 | GPIO/Loan IO19Input Mux Selection Field
19876  * [31:1] | ??? | 0x0 | *UNDEFINED*
19877  *
19878  */
19879 /*
19880  * Field : GPIO/Loan IO19Input Mux Selection Field - sel
19881  *
19882  * Select source for GPIO/LoanIO 19.
19883  *
19884  * 0 : LoanIO 19 controls GPIO/LOANIO[19] output and output enable signals.
19885  *
19886  * 1 : GPIO 19 controls GPIO/LOANI[19] output and output enable signals.
19887  *
19888  * Field Access Macros:
19889  *
19890  */
19891 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19892 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0
19893 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19894 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0
19895 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19896 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1
19897 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */
19898 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001
19899 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value. */
19900 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe
19901 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field. */
19902 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0
19903 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX19_SEL field value from a register. */
19904 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0)
19905 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX19_SEL register field value suitable for setting the register. */
19906 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001)
19907 
19908 #ifndef __ASSEMBLY__
19909 /*
19910  * WARNING: The C register and register group struct declarations are provided for
19911  * convenience and illustrative purposes. They should, however, be used with
19912  * caution as the C language standard provides no guarantees about the alignment or
19913  * atomicity of device memory accesses. The recommended practice for writing
19914  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19915  * alt_write_word() functions.
19916  *
19917  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX19.
19918  */
19919 struct ALT_SYSMGR_PINMUX_GPLMUX19_s
19920 {
19921  uint32_t sel : 1; /* GPIO/Loan IO19Input Mux Selection Field */
19922  uint32_t : 31; /* *UNDEFINED* */
19923 };
19924 
19925 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX19. */
19926 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX19_s ALT_SYSMGR_PINMUX_GPLMUX19_t;
19927 #endif /* __ASSEMBLY__ */
19928 
19929 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX19 register from the beginning of the component. */
19930 #define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220
19931 
19932 /*
19933  * Register : GPIO/LoanIO 20 Output/Output Enable Mux Selection Register - GPLMUX20
19934  *
19935  * Selection between GPIO and LoanIO output and output enable for GPIO20 and
19936  * LoanIO20. These signals drive the Pin Mux. The Pin Mux must be configured to use
19937  * GPIO/LoanIO in addition to these settings
19938  *
19939  * Only reset by a cold reset (ignores warm reset).
19940  *
19941  * NOTE: These registers should not be modified after IO configuration.There is no
19942  * support for dynamically changing the Pin Mux selections.
19943  *
19944  * Register Layout
19945  *
19946  * Bits | Access | Reset | Description
19947  * :-------|:-------|:------|:----------------------------------------
19948  * [0] | RW | 0x0 | GPIO/Loan IO20Input Mux Selection Field
19949  * [31:1] | ??? | 0x0 | *UNDEFINED*
19950  *
19951  */
19952 /*
19953  * Field : GPIO/Loan IO20Input Mux Selection Field - sel
19954  *
19955  * Select source for GPIO/LoanIO 20.
19956  *
19957  * 0 : LoanIO 20 controls GPIO/LOANIO[20] output and output enable signals.
19958  *
19959  * 1 : GPIO 20 controls GPIO/LOANI[20] output and output enable signals.
19960  *
19961  * Field Access Macros:
19962  *
19963  */
19964 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19965 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0
19966 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19967 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0
19968 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19969 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1
19970 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */
19971 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001
19972 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value. */
19973 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe
19974 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field. */
19975 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0
19976 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX20_SEL field value from a register. */
19977 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0)
19978 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX20_SEL register field value suitable for setting the register. */
19979 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001)
19980 
19981 #ifndef __ASSEMBLY__
19982 /*
19983  * WARNING: The C register and register group struct declarations are provided for
19984  * convenience and illustrative purposes. They should, however, be used with
19985  * caution as the C language standard provides no guarantees about the alignment or
19986  * atomicity of device memory accesses. The recommended practice for writing
19987  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
19988  * alt_write_word() functions.
19989  *
19990  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX20.
19991  */
19992 struct ALT_SYSMGR_PINMUX_GPLMUX20_s
19993 {
19994  uint32_t sel : 1; /* GPIO/Loan IO20Input Mux Selection Field */
19995  uint32_t : 31; /* *UNDEFINED* */
19996 };
19997 
19998 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX20. */
19999 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX20_s ALT_SYSMGR_PINMUX_GPLMUX20_t;
20000 #endif /* __ASSEMBLY__ */
20001 
20002 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX20 register from the beginning of the component. */
20003 #define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224
20004 
20005 /*
20006  * Register : GPIO/LoanIO 21 Output/Output Enable Mux Selection Register - GPLMUX21
20007  *
20008  * Selection between GPIO and LoanIO output and output enable for GPIO21 and
20009  * LoanIO21. These signals drive the Pin Mux. The Pin Mux must be configured to use
20010  * GPIO/LoanIO in addition to these settings
20011  *
20012  * Only reset by a cold reset (ignores warm reset).
20013  *
20014  * NOTE: These registers should not be modified after IO configuration.There is no
20015  * support for dynamically changing the Pin Mux selections.
20016  *
20017  * Register Layout
20018  *
20019  * Bits | Access | Reset | Description
20020  * :-------|:-------|:------|:----------------------------------------
20021  * [0] | RW | 0x0 | GPIO/Loan IO21Input Mux Selection Field
20022  * [31:1] | ??? | 0x0 | *UNDEFINED*
20023  *
20024  */
20025 /*
20026  * Field : GPIO/Loan IO21Input Mux Selection Field - sel
20027  *
20028  * Select source for GPIO/LoanIO 21.
20029  *
20030  * 0 : LoanIO 21 controls GPIO/LOANIO[21] output and output enable signals.
20031  *
20032  * 1 : GPIO 21 controls GPIO/LOANI[21] output and output enable signals.
20033  *
20034  * Field Access Macros:
20035  *
20036  */
20037 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20038 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0
20039 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20040 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0
20041 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20042 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1
20043 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */
20044 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001
20045 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value. */
20046 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe
20047 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field. */
20048 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0
20049 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX21_SEL field value from a register. */
20050 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0)
20051 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX21_SEL register field value suitable for setting the register. */
20052 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001)
20053 
20054 #ifndef __ASSEMBLY__
20055 /*
20056  * WARNING: The C register and register group struct declarations are provided for
20057  * convenience and illustrative purposes. They should, however, be used with
20058  * caution as the C language standard provides no guarantees about the alignment or
20059  * atomicity of device memory accesses. The recommended practice for writing
20060  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20061  * alt_write_word() functions.
20062  *
20063  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX21.
20064  */
20065 struct ALT_SYSMGR_PINMUX_GPLMUX21_s
20066 {
20067  uint32_t sel : 1; /* GPIO/Loan IO21Input Mux Selection Field */
20068  uint32_t : 31; /* *UNDEFINED* */
20069 };
20070 
20071 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX21. */
20072 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX21_s ALT_SYSMGR_PINMUX_GPLMUX21_t;
20073 #endif /* __ASSEMBLY__ */
20074 
20075 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX21 register from the beginning of the component. */
20076 #define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228
20077 
20078 /*
20079  * Register : GPIO/LoanIO 22 Output/Output Enable Mux Selection Register - GPLMUX22
20080  *
20081  * Selection between GPIO and LoanIO output and output enable for GPIO22 and
20082  * LoanIO22. These signals drive the Pin Mux. The Pin Mux must be configured to use
20083  * GPIO/LoanIO in addition to these settings
20084  *
20085  * Only reset by a cold reset (ignores warm reset).
20086  *
20087  * NOTE: These registers should not be modified after IO configuration.There is no
20088  * support for dynamically changing the Pin Mux selections.
20089  *
20090  * Register Layout
20091  *
20092  * Bits | Access | Reset | Description
20093  * :-------|:-------|:------|:----------------------------------------
20094  * [0] | RW | 0x0 | GPIO/Loan IO22Input Mux Selection Field
20095  * [31:1] | ??? | 0x0 | *UNDEFINED*
20096  *
20097  */
20098 /*
20099  * Field : GPIO/Loan IO22Input Mux Selection Field - sel
20100  *
20101  * Select source for GPIO/LoanIO 22.
20102  *
20103  * 0 : LoanIO 22 controls GPIO/LOANIO[22] output and output enable signals.
20104  *
20105  * 1 : GPIO 22 controls GPIO/LOANI[22] output and output enable signals.
20106  *
20107  * Field Access Macros:
20108  *
20109  */
20110 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20111 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0
20112 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20113 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0
20114 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20115 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1
20116 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */
20117 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001
20118 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value. */
20119 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe
20120 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field. */
20121 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0
20122 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX22_SEL field value from a register. */
20123 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0)
20124 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX22_SEL register field value suitable for setting the register. */
20125 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001)
20126 
20127 #ifndef __ASSEMBLY__
20128 /*
20129  * WARNING: The C register and register group struct declarations are provided for
20130  * convenience and illustrative purposes. They should, however, be used with
20131  * caution as the C language standard provides no guarantees about the alignment or
20132  * atomicity of device memory accesses. The recommended practice for writing
20133  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20134  * alt_write_word() functions.
20135  *
20136  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX22.
20137  */
20138 struct ALT_SYSMGR_PINMUX_GPLMUX22_s
20139 {
20140  uint32_t sel : 1; /* GPIO/Loan IO22Input Mux Selection Field */
20141  uint32_t : 31; /* *UNDEFINED* */
20142 };
20143 
20144 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX22. */
20145 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX22_s ALT_SYSMGR_PINMUX_GPLMUX22_t;
20146 #endif /* __ASSEMBLY__ */
20147 
20148 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX22 register from the beginning of the component. */
20149 #define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c
20150 
20151 /*
20152  * Register : GPIO/LoanIO 23 Output/Output Enable Mux Selection Register - GPLMUX23
20153  *
20154  * Selection between GPIO and LoanIO output and output enable for GPIO23 and
20155  * LoanIO23. These signals drive the Pin Mux. The Pin Mux must be configured to use
20156  * GPIO/LoanIO in addition to these settings
20157  *
20158  * Only reset by a cold reset (ignores warm reset).
20159  *
20160  * NOTE: These registers should not be modified after IO configuration.There is no
20161  * support for dynamically changing the Pin Mux selections.
20162  *
20163  * Register Layout
20164  *
20165  * Bits | Access | Reset | Description
20166  * :-------|:-------|:------|:----------------------------------------
20167  * [0] | RW | 0x0 | GPIO/Loan IO23Input Mux Selection Field
20168  * [31:1] | ??? | 0x0 | *UNDEFINED*
20169  *
20170  */
20171 /*
20172  * Field : GPIO/Loan IO23Input Mux Selection Field - sel
20173  *
20174  * Select source for GPIO/LoanIO 23.
20175  *
20176  * 0 : LoanIO 23 controls GPIO/LOANIO[23] output and output enable signals.
20177  *
20178  * 1 : GPIO 23 controls GPIO/LOANI[23] output and output enable signals.
20179  *
20180  * Field Access Macros:
20181  *
20182  */
20183 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20184 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0
20185 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20186 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0
20187 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20188 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1
20189 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */
20190 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001
20191 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value. */
20192 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe
20193 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field. */
20194 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0
20195 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX23_SEL field value from a register. */
20196 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0)
20197 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX23_SEL register field value suitable for setting the register. */
20198 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001)
20199 
20200 #ifndef __ASSEMBLY__
20201 /*
20202  * WARNING: The C register and register group struct declarations are provided for
20203  * convenience and illustrative purposes. They should, however, be used with
20204  * caution as the C language standard provides no guarantees about the alignment or
20205  * atomicity of device memory accesses. The recommended practice for writing
20206  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20207  * alt_write_word() functions.
20208  *
20209  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX23.
20210  */
20211 struct ALT_SYSMGR_PINMUX_GPLMUX23_s
20212 {
20213  uint32_t sel : 1; /* GPIO/Loan IO23Input Mux Selection Field */
20214  uint32_t : 31; /* *UNDEFINED* */
20215 };
20216 
20217 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX23. */
20218 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX23_s ALT_SYSMGR_PINMUX_GPLMUX23_t;
20219 #endif /* __ASSEMBLY__ */
20220 
20221 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX23 register from the beginning of the component. */
20222 #define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230
20223 
20224 /*
20225  * Register : GPIO/LoanIO 24 Output/Output Enable Mux Selection Register - GPLMUX24
20226  *
20227  * Selection between GPIO and LoanIO output and output enable for GPIO24 and
20228  * LoanIO24. These signals drive the Pin Mux. The Pin Mux must be configured to use
20229  * GPIO/LoanIO in addition to these settings
20230  *
20231  * Only reset by a cold reset (ignores warm reset).
20232  *
20233  * NOTE: These registers should not be modified after IO configuration.There is no
20234  * support for dynamically changing the Pin Mux selections.
20235  *
20236  * Register Layout
20237  *
20238  * Bits | Access | Reset | Description
20239  * :-------|:-------|:------|:----------------------------------------
20240  * [0] | RW | 0x0 | GPIO/Loan IO24Input Mux Selection Field
20241  * [31:1] | ??? | 0x0 | *UNDEFINED*
20242  *
20243  */
20244 /*
20245  * Field : GPIO/Loan IO24Input Mux Selection Field - sel
20246  *
20247  * Select source for GPIO/LoanIO 24.
20248  *
20249  * 0 : LoanIO 24 controls GPIO/LOANIO[24] output and output enable signals.
20250  *
20251  * 1 : GPIO 24 controls GPIO/LOANI[24] output and output enable signals.
20252  *
20253  * Field Access Macros:
20254  *
20255  */
20256 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20257 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0
20258 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20259 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0
20260 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20261 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1
20262 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */
20263 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001
20264 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value. */
20265 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe
20266 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field. */
20267 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0
20268 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX24_SEL field value from a register. */
20269 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0)
20270 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX24_SEL register field value suitable for setting the register. */
20271 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001)
20272 
20273 #ifndef __ASSEMBLY__
20274 /*
20275  * WARNING: The C register and register group struct declarations are provided for
20276  * convenience and illustrative purposes. They should, however, be used with
20277  * caution as the C language standard provides no guarantees about the alignment or
20278  * atomicity of device memory accesses. The recommended practice for writing
20279  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20280  * alt_write_word() functions.
20281  *
20282  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX24.
20283  */
20284 struct ALT_SYSMGR_PINMUX_GPLMUX24_s
20285 {
20286  uint32_t sel : 1; /* GPIO/Loan IO24Input Mux Selection Field */
20287  uint32_t : 31; /* *UNDEFINED* */
20288 };
20289 
20290 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX24. */
20291 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX24_s ALT_SYSMGR_PINMUX_GPLMUX24_t;
20292 #endif /* __ASSEMBLY__ */
20293 
20294 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX24 register from the beginning of the component. */
20295 #define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234
20296 
20297 /*
20298  * Register : GPIO/LoanIO 25 Output/Output Enable Mux Selection Register - GPLMUX25
20299  *
20300  * Selection between GPIO and LoanIO output and output enable for GPIO25 and
20301  * LoanIO25. These signals drive the Pin Mux. The Pin Mux must be configured to use
20302  * GPIO/LoanIO in addition to these settings
20303  *
20304  * Only reset by a cold reset (ignores warm reset).
20305  *
20306  * NOTE: These registers should not be modified after IO configuration.There is no
20307  * support for dynamically changing the Pin Mux selections.
20308  *
20309  * Register Layout
20310  *
20311  * Bits | Access | Reset | Description
20312  * :-------|:-------|:------|:----------------------------------------
20313  * [0] | RW | 0x0 | GPIO/Loan IO25Input Mux Selection Field
20314  * [31:1] | ??? | 0x0 | *UNDEFINED*
20315  *
20316  */
20317 /*
20318  * Field : GPIO/Loan IO25Input Mux Selection Field - sel
20319  *
20320  * Select source for GPIO/LoanIO 25.
20321  *
20322  * 0 : LoanIO 25 controls GPIO/LOANIO[25] output and output enable signals.
20323  *
20324  * 1 : GPIO 25 controls GPIO/LOANI[25] output and output enable signals.
20325  *
20326  * Field Access Macros:
20327  *
20328  */
20329 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20330 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0
20331 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20332 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0
20333 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20334 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1
20335 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */
20336 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001
20337 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value. */
20338 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe
20339 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field. */
20340 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0
20341 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX25_SEL field value from a register. */
20342 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0)
20343 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX25_SEL register field value suitable for setting the register. */
20344 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001)
20345 
20346 #ifndef __ASSEMBLY__
20347 /*
20348  * WARNING: The C register and register group struct declarations are provided for
20349  * convenience and illustrative purposes. They should, however, be used with
20350  * caution as the C language standard provides no guarantees about the alignment or
20351  * atomicity of device memory accesses. The recommended practice for writing
20352  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20353  * alt_write_word() functions.
20354  *
20355  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX25.
20356  */
20357 struct ALT_SYSMGR_PINMUX_GPLMUX25_s
20358 {
20359  uint32_t sel : 1; /* GPIO/Loan IO25Input Mux Selection Field */
20360  uint32_t : 31; /* *UNDEFINED* */
20361 };
20362 
20363 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX25. */
20364 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX25_s ALT_SYSMGR_PINMUX_GPLMUX25_t;
20365 #endif /* __ASSEMBLY__ */
20366 
20367 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX25 register from the beginning of the component. */
20368 #define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238
20369 
20370 /*
20371  * Register : GPIO/LoanIO 26 Output/Output Enable Mux Selection Register - GPLMUX26
20372  *
20373  * Selection between GPIO and LoanIO output and output enable for GPIO26 and
20374  * LoanIO26. These signals drive the Pin Mux. The Pin Mux must be configured to use
20375  * GPIO/LoanIO in addition to these settings
20376  *
20377  * Only reset by a cold reset (ignores warm reset).
20378  *
20379  * NOTE: These registers should not be modified after IO configuration.There is no
20380  * support for dynamically changing the Pin Mux selections.
20381  *
20382  * Register Layout
20383  *
20384  * Bits | Access | Reset | Description
20385  * :-------|:-------|:------|:----------------------------------------
20386  * [0] | RW | 0x0 | GPIO/Loan IO26Input Mux Selection Field
20387  * [31:1] | ??? | 0x0 | *UNDEFINED*
20388  *
20389  */
20390 /*
20391  * Field : GPIO/Loan IO26Input Mux Selection Field - sel
20392  *
20393  * Select source for GPIO/LoanIO 26.
20394  *
20395  * 0 : LoanIO 26 controls GPIO/LOANIO[26] output and output enable signals.
20396  *
20397  * 1 : GPIO 26 controls GPIO/LOANI[26] output and output enable signals.
20398  *
20399  * Field Access Macros:
20400  *
20401  */
20402 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20403 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0
20404 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20405 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0
20406 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20407 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1
20408 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */
20409 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001
20410 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value. */
20411 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe
20412 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field. */
20413 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0
20414 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX26_SEL field value from a register. */
20415 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0)
20416 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX26_SEL register field value suitable for setting the register. */
20417 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001)
20418 
20419 #ifndef __ASSEMBLY__
20420 /*
20421  * WARNING: The C register and register group struct declarations are provided for
20422  * convenience and illustrative purposes. They should, however, be used with
20423  * caution as the C language standard provides no guarantees about the alignment or
20424  * atomicity of device memory accesses. The recommended practice for writing
20425  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20426  * alt_write_word() functions.
20427  *
20428  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX26.
20429  */
20430 struct ALT_SYSMGR_PINMUX_GPLMUX26_s
20431 {
20432  uint32_t sel : 1; /* GPIO/Loan IO26Input Mux Selection Field */
20433  uint32_t : 31; /* *UNDEFINED* */
20434 };
20435 
20436 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX26. */
20437 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX26_s ALT_SYSMGR_PINMUX_GPLMUX26_t;
20438 #endif /* __ASSEMBLY__ */
20439 
20440 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX26 register from the beginning of the component. */
20441 #define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c
20442 
20443 /*
20444  * Register : GPIO/LoanIO 27 Output/Output Enable Mux Selection Register - GPLMUX27
20445  *
20446  * Selection between GPIO and LoanIO output and output enable for GPIO27 and
20447  * LoanIO27. These signals drive the Pin Mux. The Pin Mux must be configured to use
20448  * GPIO/LoanIO in addition to these settings
20449  *
20450  * Only reset by a cold reset (ignores warm reset).
20451  *
20452  * NOTE: These registers should not be modified after IO configuration.There is no
20453  * support for dynamically changing the Pin Mux selections.
20454  *
20455  * Register Layout
20456  *
20457  * Bits | Access | Reset | Description
20458  * :-------|:-------|:------|:----------------------------------------
20459  * [0] | RW | 0x0 | GPIO/Loan IO27Input Mux Selection Field
20460  * [31:1] | ??? | 0x0 | *UNDEFINED*
20461  *
20462  */
20463 /*
20464  * Field : GPIO/Loan IO27Input Mux Selection Field - sel
20465  *
20466  * Select source for GPIO/LoanIO 27.
20467  *
20468  * 0 : LoanIO 27 controls GPIO/LOANIO[27] output and output enable signals.
20469  *
20470  * 1 : GPIO 27 controls GPIO/LOANI[27] output and output enable signals.
20471  *
20472  * Field Access Macros:
20473  *
20474  */
20475 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20476 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0
20477 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20478 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0
20479 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20480 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1
20481 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */
20482 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001
20483 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value. */
20484 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe
20485 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field. */
20486 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0
20487 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX27_SEL field value from a register. */
20488 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0)
20489 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX27_SEL register field value suitable for setting the register. */
20490 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001)
20491 
20492 #ifndef __ASSEMBLY__
20493 /*
20494  * WARNING: The C register and register group struct declarations are provided for
20495  * convenience and illustrative purposes. They should, however, be used with
20496  * caution as the C language standard provides no guarantees about the alignment or
20497  * atomicity of device memory accesses. The recommended practice for writing
20498  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20499  * alt_write_word() functions.
20500  *
20501  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX27.
20502  */
20503 struct ALT_SYSMGR_PINMUX_GPLMUX27_s
20504 {
20505  uint32_t sel : 1; /* GPIO/Loan IO27Input Mux Selection Field */
20506  uint32_t : 31; /* *UNDEFINED* */
20507 };
20508 
20509 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX27. */
20510 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX27_s ALT_SYSMGR_PINMUX_GPLMUX27_t;
20511 #endif /* __ASSEMBLY__ */
20512 
20513 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX27 register from the beginning of the component. */
20514 #define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240
20515 
20516 /*
20517  * Register : GPIO/LoanIO 28 Output/Output Enable Mux Selection Register - GPLMUX28
20518  *
20519  * Selection between GPIO and LoanIO output and output enable for GPIO28 and
20520  * LoanIO28. These signals drive the Pin Mux. The Pin Mux must be configured to use
20521  * GPIO/LoanIO in addition to these settings
20522  *
20523  * Only reset by a cold reset (ignores warm reset).
20524  *
20525  * NOTE: These registers should not be modified after IO configuration.There is no
20526  * support for dynamically changing the Pin Mux selections.
20527  *
20528  * Register Layout
20529  *
20530  * Bits | Access | Reset | Description
20531  * :-------|:-------|:------|:----------------------------------------
20532  * [0] | RW | 0x0 | GPIO/Loan IO28Input Mux Selection Field
20533  * [31:1] | ??? | 0x0 | *UNDEFINED*
20534  *
20535  */
20536 /*
20537  * Field : GPIO/Loan IO28Input Mux Selection Field - sel
20538  *
20539  * Select source for GPIO/LoanIO 28.
20540  *
20541  * 0 : LoanIO 28 controls GPIO/LOANIO[28] output and output enable signals.
20542  *
20543  * 1 : GPIO 28 controls GPIO/LOANI[28] output and output enable signals.
20544  *
20545  * Field Access Macros:
20546  *
20547  */
20548 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20549 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0
20550 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20551 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0
20552 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20553 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1
20554 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */
20555 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001
20556 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value. */
20557 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe
20558 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field. */
20559 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0
20560 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX28_SEL field value from a register. */
20561 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0)
20562 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX28_SEL register field value suitable for setting the register. */
20563 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001)
20564 
20565 #ifndef __ASSEMBLY__
20566 /*
20567  * WARNING: The C register and register group struct declarations are provided for
20568  * convenience and illustrative purposes. They should, however, be used with
20569  * caution as the C language standard provides no guarantees about the alignment or
20570  * atomicity of device memory accesses. The recommended practice for writing
20571  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20572  * alt_write_word() functions.
20573  *
20574  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX28.
20575  */
20576 struct ALT_SYSMGR_PINMUX_GPLMUX28_s
20577 {
20578  uint32_t sel : 1; /* GPIO/Loan IO28Input Mux Selection Field */
20579  uint32_t : 31; /* *UNDEFINED* */
20580 };
20581 
20582 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX28. */
20583 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX28_s ALT_SYSMGR_PINMUX_GPLMUX28_t;
20584 #endif /* __ASSEMBLY__ */
20585 
20586 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX28 register from the beginning of the component. */
20587 #define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244
20588 
20589 /*
20590  * Register : GPIO/LoanIO 29 Output/Output Enable Mux Selection Register - GPLMUX29
20591  *
20592  * Selection between GPIO and LoanIO output and output enable for GPIO29 and
20593  * LoanIO29. These signals drive the Pin Mux. The Pin Mux must be configured to use
20594  * GPIO/LoanIO in addition to these settings
20595  *
20596  * Only reset by a cold reset (ignores warm reset).
20597  *
20598  * NOTE: These registers should not be modified after IO configuration.There is no
20599  * support for dynamically changing the Pin Mux selections.
20600  *
20601  * Register Layout
20602  *
20603  * Bits | Access | Reset | Description
20604  * :-------|:-------|:------|:----------------------------------------
20605  * [0] | RW | 0x0 | GPIO/Loan IO29Input Mux Selection Field
20606  * [31:1] | ??? | 0x0 | *UNDEFINED*
20607  *
20608  */
20609 /*
20610  * Field : GPIO/Loan IO29Input Mux Selection Field - sel
20611  *
20612  * Select source for GPIO/LoanIO 29.
20613  *
20614  * 0 : LoanIO 29 controls GPIO/LOANIO[29] output and output enable signals.
20615  *
20616  * 1 : GPIO 29 controls GPIO/LOANI[29] output and output enable signals.
20617  *
20618  * Field Access Macros:
20619  *
20620  */
20621 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20622 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0
20623 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20624 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0
20625 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20626 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1
20627 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */
20628 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001
20629 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value. */
20630 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe
20631 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field. */
20632 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0
20633 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX29_SEL field value from a register. */
20634 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0)
20635 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX29_SEL register field value suitable for setting the register. */
20636 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001)
20637 
20638 #ifndef __ASSEMBLY__
20639 /*
20640  * WARNING: The C register and register group struct declarations are provided for
20641  * convenience and illustrative purposes. They should, however, be used with
20642  * caution as the C language standard provides no guarantees about the alignment or
20643  * atomicity of device memory accesses. The recommended practice for writing
20644  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20645  * alt_write_word() functions.
20646  *
20647  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX29.
20648  */
20649 struct ALT_SYSMGR_PINMUX_GPLMUX29_s
20650 {
20651  uint32_t sel : 1; /* GPIO/Loan IO29Input Mux Selection Field */
20652  uint32_t : 31; /* *UNDEFINED* */
20653 };
20654 
20655 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX29. */
20656 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX29_s ALT_SYSMGR_PINMUX_GPLMUX29_t;
20657 #endif /* __ASSEMBLY__ */
20658 
20659 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX29 register from the beginning of the component. */
20660 #define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248
20661 
20662 /*
20663  * Register : GPIO/LoanIO 30 Output/Output Enable Mux Selection Register - GPLMUX30
20664  *
20665  * Selection between GPIO and LoanIO output and output enable for GPIO30 and
20666  * LoanIO30. These signals drive the Pin Mux. The Pin Mux must be configured to use
20667  * GPIO/LoanIO in addition to these settings
20668  *
20669  * Only reset by a cold reset (ignores warm reset).
20670  *
20671  * NOTE: These registers should not be modified after IO configuration.There is no
20672  * support for dynamically changing the Pin Mux selections.
20673  *
20674  * Register Layout
20675  *
20676  * Bits | Access | Reset | Description
20677  * :-------|:-------|:------|:----------------------------------------
20678  * [0] | RW | 0x0 | GPIO/Loan IO30Input Mux Selection Field
20679  * [31:1] | ??? | 0x0 | *UNDEFINED*
20680  *
20681  */
20682 /*
20683  * Field : GPIO/Loan IO30Input Mux Selection Field - sel
20684  *
20685  * Select source for GPIO/LoanIO 30.
20686  *
20687  * 0 : LoanIO 30 controls GPIO/LOANIO[30] output and output enable signals.
20688  *
20689  * 1 : GPIO 30 controls GPIO/LOANI[30] output and output enable signals.
20690  *
20691  * Field Access Macros:
20692  *
20693  */
20694 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20695 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0
20696 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20697 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0
20698 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20699 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1
20700 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */
20701 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001
20702 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value. */
20703 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe
20704 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field. */
20705 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0
20706 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX30_SEL field value from a register. */
20707 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0)
20708 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX30_SEL register field value suitable for setting the register. */
20709 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001)
20710 
20711 #ifndef __ASSEMBLY__
20712 /*
20713  * WARNING: The C register and register group struct declarations are provided for
20714  * convenience and illustrative purposes. They should, however, be used with
20715  * caution as the C language standard provides no guarantees about the alignment or
20716  * atomicity of device memory accesses. The recommended practice for writing
20717  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20718  * alt_write_word() functions.
20719  *
20720  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX30.
20721  */
20722 struct ALT_SYSMGR_PINMUX_GPLMUX30_s
20723 {
20724  uint32_t sel : 1; /* GPIO/Loan IO30Input Mux Selection Field */
20725  uint32_t : 31; /* *UNDEFINED* */
20726 };
20727 
20728 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX30. */
20729 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX30_s ALT_SYSMGR_PINMUX_GPLMUX30_t;
20730 #endif /* __ASSEMBLY__ */
20731 
20732 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX30 register from the beginning of the component. */
20733 #define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c
20734 
20735 /*
20736  * Register : GPIO/LoanIO 31 Output/Output Enable Mux Selection Register - GPLMUX31
20737  *
20738  * Selection between GPIO and LoanIO output and output enable for GPIO31 and
20739  * LoanIO31. These signals drive the Pin Mux. The Pin Mux must be configured to use
20740  * GPIO/LoanIO in addition to these settings
20741  *
20742  * Only reset by a cold reset (ignores warm reset).
20743  *
20744  * NOTE: These registers should not be modified after IO configuration.There is no
20745  * support for dynamically changing the Pin Mux selections.
20746  *
20747  * Register Layout
20748  *
20749  * Bits | Access | Reset | Description
20750  * :-------|:-------|:------|:----------------------------------------
20751  * [0] | RW | 0x0 | GPIO/Loan IO31Input Mux Selection Field
20752  * [31:1] | ??? | 0x0 | *UNDEFINED*
20753  *
20754  */
20755 /*
20756  * Field : GPIO/Loan IO31Input Mux Selection Field - sel
20757  *
20758  * Select source for GPIO/LoanIO 31.
20759  *
20760  * 0 : LoanIO 31 controls GPIO/LOANIO[31] output and output enable signals.
20761  *
20762  * 1 : GPIO 31 controls GPIO/LOANI[31] output and output enable signals.
20763  *
20764  * Field Access Macros:
20765  *
20766  */
20767 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20768 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0
20769 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20770 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0
20771 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20772 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1
20773 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */
20774 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001
20775 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value. */
20776 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe
20777 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field. */
20778 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0
20779 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX31_SEL field value from a register. */
20780 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0)
20781 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX31_SEL register field value suitable for setting the register. */
20782 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001)
20783 
20784 #ifndef __ASSEMBLY__
20785 /*
20786  * WARNING: The C register and register group struct declarations are provided for
20787  * convenience and illustrative purposes. They should, however, be used with
20788  * caution as the C language standard provides no guarantees about the alignment or
20789  * atomicity of device memory accesses. The recommended practice for writing
20790  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20791  * alt_write_word() functions.
20792  *
20793  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX31.
20794  */
20795 struct ALT_SYSMGR_PINMUX_GPLMUX31_s
20796 {
20797  uint32_t sel : 1; /* GPIO/Loan IO31Input Mux Selection Field */
20798  uint32_t : 31; /* *UNDEFINED* */
20799 };
20800 
20801 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX31. */
20802 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX31_s ALT_SYSMGR_PINMUX_GPLMUX31_t;
20803 #endif /* __ASSEMBLY__ */
20804 
20805 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX31 register from the beginning of the component. */
20806 #define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250
20807 
20808 /*
20809  * Register : GPIO/LoanIO 32 Output/Output Enable Mux Selection Register - GPLMUX32
20810  *
20811  * Selection between GPIO and LoanIO output and output enable for GPIO32 and
20812  * LoanIO32. These signals drive the Pin Mux. The Pin Mux must be configured to use
20813  * GPIO/LoanIO in addition to these settings
20814  *
20815  * Only reset by a cold reset (ignores warm reset).
20816  *
20817  * NOTE: These registers should not be modified after IO configuration.There is no
20818  * support for dynamically changing the Pin Mux selections.
20819  *
20820  * Register Layout
20821  *
20822  * Bits | Access | Reset | Description
20823  * :-------|:-------|:------|:----------------------------------------
20824  * [0] | RW | 0x0 | GPIO/Loan IO32Input Mux Selection Field
20825  * [31:1] | ??? | 0x0 | *UNDEFINED*
20826  *
20827  */
20828 /*
20829  * Field : GPIO/Loan IO32Input Mux Selection Field - sel
20830  *
20831  * Select source for GPIO/LoanIO 32.
20832  *
20833  * 0 : LoanIO 32 controls GPIO/LOANIO[32] output and output enable signals.
20834  *
20835  * 1 : GPIO 32 controls GPIO/LOANI[32] output and output enable signals.
20836  *
20837  * Field Access Macros:
20838  *
20839  */
20840 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20841 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0
20842 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20843 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0
20844 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20845 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1
20846 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */
20847 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001
20848 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value. */
20849 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe
20850 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field. */
20851 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0
20852 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX32_SEL field value from a register. */
20853 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0)
20854 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX32_SEL register field value suitable for setting the register. */
20855 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001)
20856 
20857 #ifndef __ASSEMBLY__
20858 /*
20859  * WARNING: The C register and register group struct declarations are provided for
20860  * convenience and illustrative purposes. They should, however, be used with
20861  * caution as the C language standard provides no guarantees about the alignment or
20862  * atomicity of device memory accesses. The recommended practice for writing
20863  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20864  * alt_write_word() functions.
20865  *
20866  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX32.
20867  */
20868 struct ALT_SYSMGR_PINMUX_GPLMUX32_s
20869 {
20870  uint32_t sel : 1; /* GPIO/Loan IO32Input Mux Selection Field */
20871  uint32_t : 31; /* *UNDEFINED* */
20872 };
20873 
20874 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX32. */
20875 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX32_s ALT_SYSMGR_PINMUX_GPLMUX32_t;
20876 #endif /* __ASSEMBLY__ */
20877 
20878 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX32 register from the beginning of the component. */
20879 #define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254
20880 
20881 /*
20882  * Register : GPIO/LoanIO 33 Output/Output Enable Mux Selection Register - GPLMUX33
20883  *
20884  * Selection between GPIO and LoanIO output and output enable for GPIO33 and
20885  * LoanIO33. These signals drive the Pin Mux. The Pin Mux must be configured to use
20886  * GPIO/LoanIO in addition to these settings
20887  *
20888  * Only reset by a cold reset (ignores warm reset).
20889  *
20890  * NOTE: These registers should not be modified after IO configuration.There is no
20891  * support for dynamically changing the Pin Mux selections.
20892  *
20893  * Register Layout
20894  *
20895  * Bits | Access | Reset | Description
20896  * :-------|:-------|:------|:----------------------------------------
20897  * [0] | RW | 0x0 | GPIO/Loan IO33Input Mux Selection Field
20898  * [31:1] | ??? | 0x0 | *UNDEFINED*
20899  *
20900  */
20901 /*
20902  * Field : GPIO/Loan IO33Input Mux Selection Field - sel
20903  *
20904  * Select source for GPIO/LoanIO 33.
20905  *
20906  * 0 : LoanIO 33 controls GPIO/LOANIO[33] output and output enable signals.
20907  *
20908  * 1 : GPIO 33 controls GPIO/LOANI[33] output and output enable signals.
20909  *
20910  * Field Access Macros:
20911  *
20912  */
20913 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20914 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0
20915 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20916 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0
20917 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20918 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1
20919 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */
20920 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001
20921 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value. */
20922 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe
20923 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field. */
20924 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0
20925 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX33_SEL field value from a register. */
20926 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0)
20927 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX33_SEL register field value suitable for setting the register. */
20928 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001)
20929 
20930 #ifndef __ASSEMBLY__
20931 /*
20932  * WARNING: The C register and register group struct declarations are provided for
20933  * convenience and illustrative purposes. They should, however, be used with
20934  * caution as the C language standard provides no guarantees about the alignment or
20935  * atomicity of device memory accesses. The recommended practice for writing
20936  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
20937  * alt_write_word() functions.
20938  *
20939  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX33.
20940  */
20941 struct ALT_SYSMGR_PINMUX_GPLMUX33_s
20942 {
20943  uint32_t sel : 1; /* GPIO/Loan IO33Input Mux Selection Field */
20944  uint32_t : 31; /* *UNDEFINED* */
20945 };
20946 
20947 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX33. */
20948 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX33_s ALT_SYSMGR_PINMUX_GPLMUX33_t;
20949 #endif /* __ASSEMBLY__ */
20950 
20951 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX33 register from the beginning of the component. */
20952 #define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258
20953 
20954 /*
20955  * Register : GPIO/LoanIO 34 Output/Output Enable Mux Selection Register - GPLMUX34
20956  *
20957  * Selection between GPIO and LoanIO output and output enable for GPIO34 and
20958  * LoanIO34. These signals drive the Pin Mux. The Pin Mux must be configured to use
20959  * GPIO/LoanIO in addition to these settings
20960  *
20961  * Only reset by a cold reset (ignores warm reset).
20962  *
20963  * NOTE: These registers should not be modified after IO configuration.There is no
20964  * support for dynamically changing the Pin Mux selections.
20965  *
20966  * Register Layout
20967  *
20968  * Bits | Access | Reset | Description
20969  * :-------|:-------|:------|:----------------------------------------
20970  * [0] | RW | 0x0 | GPIO/Loan IO34Input Mux Selection Field
20971  * [31:1] | ??? | 0x0 | *UNDEFINED*
20972  *
20973  */
20974 /*
20975  * Field : GPIO/Loan IO34Input Mux Selection Field - sel
20976  *
20977  * Select source for GPIO/LoanIO 34.
20978  *
20979  * 0 : LoanIO 34 controls GPIO/LOANIO[34] output and output enable signals.
20980  *
20981  * 1 : GPIO 34 controls GPIO/LOANI[34] output and output enable signals.
20982  *
20983  * Field Access Macros:
20984  *
20985  */
20986 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20987 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0
20988 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20989 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0
20990 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20991 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1
20992 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */
20993 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001
20994 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value. */
20995 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe
20996 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field. */
20997 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0
20998 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX34_SEL field value from a register. */
20999 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0)
21000 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX34_SEL register field value suitable for setting the register. */
21001 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001)
21002 
21003 #ifndef __ASSEMBLY__
21004 /*
21005  * WARNING: The C register and register group struct declarations are provided for
21006  * convenience and illustrative purposes. They should, however, be used with
21007  * caution as the C language standard provides no guarantees about the alignment or
21008  * atomicity of device memory accesses. The recommended practice for writing
21009  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21010  * alt_write_word() functions.
21011  *
21012  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX34.
21013  */
21014 struct ALT_SYSMGR_PINMUX_GPLMUX34_s
21015 {
21016  uint32_t sel : 1; /* GPIO/Loan IO34Input Mux Selection Field */
21017  uint32_t : 31; /* *UNDEFINED* */
21018 };
21019 
21020 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX34. */
21021 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX34_s ALT_SYSMGR_PINMUX_GPLMUX34_t;
21022 #endif /* __ASSEMBLY__ */
21023 
21024 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX34 register from the beginning of the component. */
21025 #define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c
21026 
21027 /*
21028  * Register : GPIO/LoanIO 35 Output/Output Enable Mux Selection Register - GPLMUX35
21029  *
21030  * Selection between GPIO and LoanIO output and output enable for GPIO35 and
21031  * LoanIO35. These signals drive the Pin Mux. The Pin Mux must be configured to use
21032  * GPIO/LoanIO in addition to these settings
21033  *
21034  * Only reset by a cold reset (ignores warm reset).
21035  *
21036  * NOTE: These registers should not be modified after IO configuration.There is no
21037  * support for dynamically changing the Pin Mux selections.
21038  *
21039  * Register Layout
21040  *
21041  * Bits | Access | Reset | Description
21042  * :-------|:-------|:------|:----------------------------------------
21043  * [0] | RW | 0x0 | GPIO/Loan IO35Input Mux Selection Field
21044  * [31:1] | ??? | 0x0 | *UNDEFINED*
21045  *
21046  */
21047 /*
21048  * Field : GPIO/Loan IO35Input Mux Selection Field - sel
21049  *
21050  * Select source for GPIO/LoanIO 35.
21051  *
21052  * 0 : LoanIO 35 controls GPIO/LOANIO[35] output and output enable signals.
21053  *
21054  * 1 : GPIO 35 controls GPIO/LOANI[35] output and output enable signals.
21055  *
21056  * Field Access Macros:
21057  *
21058  */
21059 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21060 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0
21061 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21062 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0
21063 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21064 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1
21065 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */
21066 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001
21067 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value. */
21068 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe
21069 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field. */
21070 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0
21071 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX35_SEL field value from a register. */
21072 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0)
21073 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX35_SEL register field value suitable for setting the register. */
21074 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001)
21075 
21076 #ifndef __ASSEMBLY__
21077 /*
21078  * WARNING: The C register and register group struct declarations are provided for
21079  * convenience and illustrative purposes. They should, however, be used with
21080  * caution as the C language standard provides no guarantees about the alignment or
21081  * atomicity of device memory accesses. The recommended practice for writing
21082  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21083  * alt_write_word() functions.
21084  *
21085  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX35.
21086  */
21087 struct ALT_SYSMGR_PINMUX_GPLMUX35_s
21088 {
21089  uint32_t sel : 1; /* GPIO/Loan IO35Input Mux Selection Field */
21090  uint32_t : 31; /* *UNDEFINED* */
21091 };
21092 
21093 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX35. */
21094 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX35_s ALT_SYSMGR_PINMUX_GPLMUX35_t;
21095 #endif /* __ASSEMBLY__ */
21096 
21097 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX35 register from the beginning of the component. */
21098 #define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260
21099 
21100 /*
21101  * Register : GPIO/LoanIO 36 Output/Output Enable Mux Selection Register - GPLMUX36
21102  *
21103  * Selection between GPIO and LoanIO output and output enable for GPIO36 and
21104  * LoanIO36. These signals drive the Pin Mux. The Pin Mux must be configured to use
21105  * GPIO/LoanIO in addition to these settings
21106  *
21107  * Only reset by a cold reset (ignores warm reset).
21108  *
21109  * NOTE: These registers should not be modified after IO configuration.There is no
21110  * support for dynamically changing the Pin Mux selections.
21111  *
21112  * Register Layout
21113  *
21114  * Bits | Access | Reset | Description
21115  * :-------|:-------|:------|:----------------------------------------
21116  * [0] | RW | 0x0 | GPIO/Loan IO36Input Mux Selection Field
21117  * [31:1] | ??? | 0x0 | *UNDEFINED*
21118  *
21119  */
21120 /*
21121  * Field : GPIO/Loan IO36Input Mux Selection Field - sel
21122  *
21123  * Select source for GPIO/LoanIO 36.
21124  *
21125  * 0 : LoanIO 36 controls GPIO/LOANIO[36] output and output enable signals.
21126  *
21127  * 1 : GPIO 36 controls GPIO/LOANI[36] output and output enable signals.
21128  *
21129  * Field Access Macros:
21130  *
21131  */
21132 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21133 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0
21134 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21135 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0
21136 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21137 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1
21138 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */
21139 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001
21140 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value. */
21141 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe
21142 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field. */
21143 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0
21144 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX36_SEL field value from a register. */
21145 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0)
21146 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX36_SEL register field value suitable for setting the register. */
21147 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001)
21148 
21149 #ifndef __ASSEMBLY__
21150 /*
21151  * WARNING: The C register and register group struct declarations are provided for
21152  * convenience and illustrative purposes. They should, however, be used with
21153  * caution as the C language standard provides no guarantees about the alignment or
21154  * atomicity of device memory accesses. The recommended practice for writing
21155  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21156  * alt_write_word() functions.
21157  *
21158  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX36.
21159  */
21160 struct ALT_SYSMGR_PINMUX_GPLMUX36_s
21161 {
21162  uint32_t sel : 1; /* GPIO/Loan IO36Input Mux Selection Field */
21163  uint32_t : 31; /* *UNDEFINED* */
21164 };
21165 
21166 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX36. */
21167 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX36_s ALT_SYSMGR_PINMUX_GPLMUX36_t;
21168 #endif /* __ASSEMBLY__ */
21169 
21170 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX36 register from the beginning of the component. */
21171 #define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264
21172 
21173 /*
21174  * Register : GPIO/LoanIO 37 Output/Output Enable Mux Selection Register - GPLMUX37
21175  *
21176  * Selection between GPIO and LoanIO output and output enable for GPIO37 and
21177  * LoanIO37. These signals drive the Pin Mux. The Pin Mux must be configured to use
21178  * GPIO/LoanIO in addition to these settings
21179  *
21180  * Only reset by a cold reset (ignores warm reset).
21181  *
21182  * NOTE: These registers should not be modified after IO configuration.There is no
21183  * support for dynamically changing the Pin Mux selections.
21184  *
21185  * Register Layout
21186  *
21187  * Bits | Access | Reset | Description
21188  * :-------|:-------|:------|:----------------------------------------
21189  * [0] | RW | 0x0 | GPIO/Loan IO37Input Mux Selection Field
21190  * [31:1] | ??? | 0x0 | *UNDEFINED*
21191  *
21192  */
21193 /*
21194  * Field : GPIO/Loan IO37Input Mux Selection Field - sel
21195  *
21196  * Select source for GPIO/LoanIO 37.
21197  *
21198  * 0 : LoanIO 37 controls GPIO/LOANIO[37] output and output enable signals.
21199  *
21200  * 1 : GPIO 37 controls GPIO/LOANI[37] output and output enable signals.
21201  *
21202  * Field Access Macros:
21203  *
21204  */
21205 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21206 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0
21207 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21208 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0
21209 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21210 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1
21211 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */
21212 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001
21213 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value. */
21214 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe
21215 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field. */
21216 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0
21217 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX37_SEL field value from a register. */
21218 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0)
21219 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX37_SEL register field value suitable for setting the register. */
21220 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001)
21221 
21222 #ifndef __ASSEMBLY__
21223 /*
21224  * WARNING: The C register and register group struct declarations are provided for
21225  * convenience and illustrative purposes. They should, however, be used with
21226  * caution as the C language standard provides no guarantees about the alignment or
21227  * atomicity of device memory accesses. The recommended practice for writing
21228  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21229  * alt_write_word() functions.
21230  *
21231  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX37.
21232  */
21233 struct ALT_SYSMGR_PINMUX_GPLMUX37_s
21234 {
21235  uint32_t sel : 1; /* GPIO/Loan IO37Input Mux Selection Field */
21236  uint32_t : 31; /* *UNDEFINED* */
21237 };
21238 
21239 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX37. */
21240 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX37_s ALT_SYSMGR_PINMUX_GPLMUX37_t;
21241 #endif /* __ASSEMBLY__ */
21242 
21243 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX37 register from the beginning of the component. */
21244 #define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268
21245 
21246 /*
21247  * Register : GPIO/LoanIO 38 Output/Output Enable Mux Selection Register - GPLMUX38
21248  *
21249  * Selection between GPIO and LoanIO output and output enable for GPIO38 and
21250  * LoanIO38. These signals drive the Pin Mux. The Pin Mux must be configured to use
21251  * GPIO/LoanIO in addition to these settings
21252  *
21253  * Only reset by a cold reset (ignores warm reset).
21254  *
21255  * NOTE: These registers should not be modified after IO configuration.There is no
21256  * support for dynamically changing the Pin Mux selections.
21257  *
21258  * Register Layout
21259  *
21260  * Bits | Access | Reset | Description
21261  * :-------|:-------|:------|:----------------------------------------
21262  * [0] | RW | 0x0 | GPIO/Loan IO38Input Mux Selection Field
21263  * [31:1] | ??? | 0x0 | *UNDEFINED*
21264  *
21265  */
21266 /*
21267  * Field : GPIO/Loan IO38Input Mux Selection Field - sel
21268  *
21269  * Select source for GPIO/LoanIO 38.
21270  *
21271  * 0 : LoanIO 38 controls GPIO/LOANIO[38] output and output enable signals.
21272  *
21273  * 1 : GPIO 38 controls GPIO/LOANI[38] output and output enable signals.
21274  *
21275  * Field Access Macros:
21276  *
21277  */
21278 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21279 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0
21280 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21281 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0
21282 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21283 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1
21284 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */
21285 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001
21286 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value. */
21287 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe
21288 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field. */
21289 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0
21290 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX38_SEL field value from a register. */
21291 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0)
21292 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX38_SEL register field value suitable for setting the register. */
21293 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001)
21294 
21295 #ifndef __ASSEMBLY__
21296 /*
21297  * WARNING: The C register and register group struct declarations are provided for
21298  * convenience and illustrative purposes. They should, however, be used with
21299  * caution as the C language standard provides no guarantees about the alignment or
21300  * atomicity of device memory accesses. The recommended practice for writing
21301  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21302  * alt_write_word() functions.
21303  *
21304  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX38.
21305  */
21306 struct ALT_SYSMGR_PINMUX_GPLMUX38_s
21307 {
21308  uint32_t sel : 1; /* GPIO/Loan IO38Input Mux Selection Field */
21309  uint32_t : 31; /* *UNDEFINED* */
21310 };
21311 
21312 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX38. */
21313 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX38_s ALT_SYSMGR_PINMUX_GPLMUX38_t;
21314 #endif /* __ASSEMBLY__ */
21315 
21316 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX38 register from the beginning of the component. */
21317 #define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c
21318 
21319 /*
21320  * Register : GPIO/LoanIO 39 Output/Output Enable Mux Selection Register - GPLMUX39
21321  *
21322  * Selection between GPIO and LoanIO output and output enable for GPIO39 and
21323  * LoanIO39. These signals drive the Pin Mux. The Pin Mux must be configured to use
21324  * GPIO/LoanIO in addition to these settings
21325  *
21326  * Only reset by a cold reset (ignores warm reset).
21327  *
21328  * NOTE: These registers should not be modified after IO configuration.There is no
21329  * support for dynamically changing the Pin Mux selections.
21330  *
21331  * Register Layout
21332  *
21333  * Bits | Access | Reset | Description
21334  * :-------|:-------|:------|:----------------------------------------
21335  * [0] | RW | 0x0 | GPIO/Loan IO39Input Mux Selection Field
21336  * [31:1] | ??? | 0x0 | *UNDEFINED*
21337  *
21338  */
21339 /*
21340  * Field : GPIO/Loan IO39Input Mux Selection Field - sel
21341  *
21342  * Select source for GPIO/LoanIO 39.
21343  *
21344  * 0 : LoanIO 39 controls GPIO/LOANIO[39] output and output enable signals.
21345  *
21346  * 1 : GPIO 39 controls GPIO/LOANI[39] output and output enable signals.
21347  *
21348  * Field Access Macros:
21349  *
21350  */
21351 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21352 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0
21353 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21354 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0
21355 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21356 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1
21357 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */
21358 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001
21359 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value. */
21360 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe
21361 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field. */
21362 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0
21363 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX39_SEL field value from a register. */
21364 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0)
21365 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX39_SEL register field value suitable for setting the register. */
21366 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001)
21367 
21368 #ifndef __ASSEMBLY__
21369 /*
21370  * WARNING: The C register and register group struct declarations are provided for
21371  * convenience and illustrative purposes. They should, however, be used with
21372  * caution as the C language standard provides no guarantees about the alignment or
21373  * atomicity of device memory accesses. The recommended practice for writing
21374  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21375  * alt_write_word() functions.
21376  *
21377  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX39.
21378  */
21379 struct ALT_SYSMGR_PINMUX_GPLMUX39_s
21380 {
21381  uint32_t sel : 1; /* GPIO/Loan IO39Input Mux Selection Field */
21382  uint32_t : 31; /* *UNDEFINED* */
21383 };
21384 
21385 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX39. */
21386 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX39_s ALT_SYSMGR_PINMUX_GPLMUX39_t;
21387 #endif /* __ASSEMBLY__ */
21388 
21389 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX39 register from the beginning of the component. */
21390 #define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270
21391 
21392 /*
21393  * Register : GPIO/LoanIO 40 Output/Output Enable Mux Selection Register - GPLMUX40
21394  *
21395  * Selection between GPIO and LoanIO output and output enable for GPIO40 and
21396  * LoanIO40. These signals drive the Pin Mux. The Pin Mux must be configured to use
21397  * GPIO/LoanIO in addition to these settings
21398  *
21399  * Only reset by a cold reset (ignores warm reset).
21400  *
21401  * NOTE: These registers should not be modified after IO configuration.There is no
21402  * support for dynamically changing the Pin Mux selections.
21403  *
21404  * Register Layout
21405  *
21406  * Bits | Access | Reset | Description
21407  * :-------|:-------|:------|:----------------------------------------
21408  * [0] | RW | 0x0 | GPIO/Loan IO40Input Mux Selection Field
21409  * [31:1] | ??? | 0x0 | *UNDEFINED*
21410  *
21411  */
21412 /*
21413  * Field : GPIO/Loan IO40Input Mux Selection Field - sel
21414  *
21415  * Select source for GPIO/LoanIO 40.
21416  *
21417  * 0 : LoanIO 40 controls GPIO/LOANIO[40] output and output enable signals.
21418  *
21419  * 1 : GPIO 40 controls GPIO/LOANI[40] output and output enable signals.
21420  *
21421  * Field Access Macros:
21422  *
21423  */
21424 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21425 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0
21426 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21427 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0
21428 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21429 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1
21430 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */
21431 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001
21432 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value. */
21433 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe
21434 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field. */
21435 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0
21436 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX40_SEL field value from a register. */
21437 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0)
21438 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX40_SEL register field value suitable for setting the register. */
21439 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001)
21440 
21441 #ifndef __ASSEMBLY__
21442 /*
21443  * WARNING: The C register and register group struct declarations are provided for
21444  * convenience and illustrative purposes. They should, however, be used with
21445  * caution as the C language standard provides no guarantees about the alignment or
21446  * atomicity of device memory accesses. The recommended practice for writing
21447  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21448  * alt_write_word() functions.
21449  *
21450  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX40.
21451  */
21452 struct ALT_SYSMGR_PINMUX_GPLMUX40_s
21453 {
21454  uint32_t sel : 1; /* GPIO/Loan IO40Input Mux Selection Field */
21455  uint32_t : 31; /* *UNDEFINED* */
21456 };
21457 
21458 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX40. */
21459 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX40_s ALT_SYSMGR_PINMUX_GPLMUX40_t;
21460 #endif /* __ASSEMBLY__ */
21461 
21462 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX40 register from the beginning of the component. */
21463 #define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274
21464 
21465 /*
21466  * Register : GPIO/LoanIO 41 Output/Output Enable Mux Selection Register - GPLMUX41
21467  *
21468  * Selection between GPIO and LoanIO output and output enable for GPIO41 and
21469  * LoanIO41. These signals drive the Pin Mux. The Pin Mux must be configured to use
21470  * GPIO/LoanIO in addition to these settings
21471  *
21472  * Only reset by a cold reset (ignores warm reset).
21473  *
21474  * NOTE: These registers should not be modified after IO configuration.There is no
21475  * support for dynamically changing the Pin Mux selections.
21476  *
21477  * Register Layout
21478  *
21479  * Bits | Access | Reset | Description
21480  * :-------|:-------|:------|:----------------------------------------
21481  * [0] | RW | 0x0 | GPIO/Loan IO41Input Mux Selection Field
21482  * [31:1] | ??? | 0x0 | *UNDEFINED*
21483  *
21484  */
21485 /*
21486  * Field : GPIO/Loan IO41Input Mux Selection Field - sel
21487  *
21488  * Select source for GPIO/LoanIO 41.
21489  *
21490  * 0 : LoanIO 41 controls GPIO/LOANIO[41] output and output enable signals.
21491  *
21492  * 1 : GPIO 41 controls GPIO/LOANI[41] output and output enable signals.
21493  *
21494  * Field Access Macros:
21495  *
21496  */
21497 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21498 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0
21499 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21500 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0
21501 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21502 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1
21503 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */
21504 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001
21505 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value. */
21506 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe
21507 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field. */
21508 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0
21509 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX41_SEL field value from a register. */
21510 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0)
21511 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX41_SEL register field value suitable for setting the register. */
21512 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001)
21513 
21514 #ifndef __ASSEMBLY__
21515 /*
21516  * WARNING: The C register and register group struct declarations are provided for
21517  * convenience and illustrative purposes. They should, however, be used with
21518  * caution as the C language standard provides no guarantees about the alignment or
21519  * atomicity of device memory accesses. The recommended practice for writing
21520  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21521  * alt_write_word() functions.
21522  *
21523  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX41.
21524  */
21525 struct ALT_SYSMGR_PINMUX_GPLMUX41_s
21526 {
21527  uint32_t sel : 1; /* GPIO/Loan IO41Input Mux Selection Field */
21528  uint32_t : 31; /* *UNDEFINED* */
21529 };
21530 
21531 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX41. */
21532 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX41_s ALT_SYSMGR_PINMUX_GPLMUX41_t;
21533 #endif /* __ASSEMBLY__ */
21534 
21535 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX41 register from the beginning of the component. */
21536 #define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278
21537 
21538 /*
21539  * Register : GPIO/LoanIO 42 Output/Output Enable Mux Selection Register - GPLMUX42
21540  *
21541  * Selection between GPIO and LoanIO output and output enable for GPIO42 and
21542  * LoanIO42. These signals drive the Pin Mux. The Pin Mux must be configured to use
21543  * GPIO/LoanIO in addition to these settings
21544  *
21545  * Only reset by a cold reset (ignores warm reset).
21546  *
21547  * NOTE: These registers should not be modified after IO configuration.There is no
21548  * support for dynamically changing the Pin Mux selections.
21549  *
21550  * Register Layout
21551  *
21552  * Bits | Access | Reset | Description
21553  * :-------|:-------|:------|:----------------------------------------
21554  * [0] | RW | 0x0 | GPIO/Loan IO42Input Mux Selection Field
21555  * [31:1] | ??? | 0x0 | *UNDEFINED*
21556  *
21557  */
21558 /*
21559  * Field : GPIO/Loan IO42Input Mux Selection Field - sel
21560  *
21561  * Select source for GPIO/LoanIO 42.
21562  *
21563  * 0 : LoanIO 42 controls GPIO/LOANIO[42] output and output enable signals.
21564  *
21565  * 1 : GPIO 42 controls GPIO/LOANI[42] output and output enable signals.
21566  *
21567  * Field Access Macros:
21568  *
21569  */
21570 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21571 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0
21572 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21573 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0
21574 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21575 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1
21576 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */
21577 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001
21578 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value. */
21579 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe
21580 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field. */
21581 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0
21582 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX42_SEL field value from a register. */
21583 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0)
21584 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX42_SEL register field value suitable for setting the register. */
21585 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001)
21586 
21587 #ifndef __ASSEMBLY__
21588 /*
21589  * WARNING: The C register and register group struct declarations are provided for
21590  * convenience and illustrative purposes. They should, however, be used with
21591  * caution as the C language standard provides no guarantees about the alignment or
21592  * atomicity of device memory accesses. The recommended practice for writing
21593  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21594  * alt_write_word() functions.
21595  *
21596  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX42.
21597  */
21598 struct ALT_SYSMGR_PINMUX_GPLMUX42_s
21599 {
21600  uint32_t sel : 1; /* GPIO/Loan IO42Input Mux Selection Field */
21601  uint32_t : 31; /* *UNDEFINED* */
21602 };
21603 
21604 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX42. */
21605 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX42_s ALT_SYSMGR_PINMUX_GPLMUX42_t;
21606 #endif /* __ASSEMBLY__ */
21607 
21608 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX42 register from the beginning of the component. */
21609 #define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c
21610 
21611 /*
21612  * Register : GPIO/LoanIO 43 Output/Output Enable Mux Selection Register - GPLMUX43
21613  *
21614  * Selection between GPIO and LoanIO output and output enable for GPIO43 and
21615  * LoanIO43. These signals drive the Pin Mux. The Pin Mux must be configured to use
21616  * GPIO/LoanIO in addition to these settings
21617  *
21618  * Only reset by a cold reset (ignores warm reset).
21619  *
21620  * NOTE: These registers should not be modified after IO configuration.There is no
21621  * support for dynamically changing the Pin Mux selections.
21622  *
21623  * Register Layout
21624  *
21625  * Bits | Access | Reset | Description
21626  * :-------|:-------|:------|:----------------------------------------
21627  * [0] | RW | 0x0 | GPIO/Loan IO43Input Mux Selection Field
21628  * [31:1] | ??? | 0x0 | *UNDEFINED*
21629  *
21630  */
21631 /*
21632  * Field : GPIO/Loan IO43Input Mux Selection Field - sel
21633  *
21634  * Select source for GPIO/LoanIO 43.
21635  *
21636  * 0 : LoanIO 43 controls GPIO/LOANIO[43] output and output enable signals.
21637  *
21638  * 1 : GPIO 43 controls GPIO/LOANI[43] output and output enable signals.
21639  *
21640  * Field Access Macros:
21641  *
21642  */
21643 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21644 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0
21645 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21646 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0
21647 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21648 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1
21649 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */
21650 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001
21651 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value. */
21652 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe
21653 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field. */
21654 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0
21655 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX43_SEL field value from a register. */
21656 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0)
21657 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX43_SEL register field value suitable for setting the register. */
21658 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001)
21659 
21660 #ifndef __ASSEMBLY__
21661 /*
21662  * WARNING: The C register and register group struct declarations are provided for
21663  * convenience and illustrative purposes. They should, however, be used with
21664  * caution as the C language standard provides no guarantees about the alignment or
21665  * atomicity of device memory accesses. The recommended practice for writing
21666  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21667  * alt_write_word() functions.
21668  *
21669  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX43.
21670  */
21671 struct ALT_SYSMGR_PINMUX_GPLMUX43_s
21672 {
21673  uint32_t sel : 1; /* GPIO/Loan IO43Input Mux Selection Field */
21674  uint32_t : 31; /* *UNDEFINED* */
21675 };
21676 
21677 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX43. */
21678 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX43_s ALT_SYSMGR_PINMUX_GPLMUX43_t;
21679 #endif /* __ASSEMBLY__ */
21680 
21681 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX43 register from the beginning of the component. */
21682 #define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280
21683 
21684 /*
21685  * Register : GPIO/LoanIO 44 Output/Output Enable Mux Selection Register - GPLMUX44
21686  *
21687  * Selection between GPIO and LoanIO output and output enable for GPIO44 and
21688  * LoanIO44. These signals drive the Pin Mux. The Pin Mux must be configured to use
21689  * GPIO/LoanIO in addition to these settings
21690  *
21691  * Only reset by a cold reset (ignores warm reset).
21692  *
21693  * NOTE: These registers should not be modified after IO configuration.There is no
21694  * support for dynamically changing the Pin Mux selections.
21695  *
21696  * Register Layout
21697  *
21698  * Bits | Access | Reset | Description
21699  * :-------|:-------|:------|:----------------------------------------
21700  * [0] | RW | 0x0 | GPIO/Loan IO44Input Mux Selection Field
21701  * [31:1] | ??? | 0x0 | *UNDEFINED*
21702  *
21703  */
21704 /*
21705  * Field : GPIO/Loan IO44Input Mux Selection Field - sel
21706  *
21707  * Select source for GPIO/LoanIO 44.
21708  *
21709  * 0 : LoanIO 44 controls GPIO/LOANIO[44] output and output enable signals.
21710  *
21711  * 1 : GPIO 44 controls GPIO/LOANI[44] output and output enable signals.
21712  *
21713  * Field Access Macros:
21714  *
21715  */
21716 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21717 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0
21718 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21719 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0
21720 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21721 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1
21722 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */
21723 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001
21724 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value. */
21725 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe
21726 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field. */
21727 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0
21728 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX44_SEL field value from a register. */
21729 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0)
21730 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX44_SEL register field value suitable for setting the register. */
21731 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001)
21732 
21733 #ifndef __ASSEMBLY__
21734 /*
21735  * WARNING: The C register and register group struct declarations are provided for
21736  * convenience and illustrative purposes. They should, however, be used with
21737  * caution as the C language standard provides no guarantees about the alignment or
21738  * atomicity of device memory accesses. The recommended practice for writing
21739  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21740  * alt_write_word() functions.
21741  *
21742  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX44.
21743  */
21744 struct ALT_SYSMGR_PINMUX_GPLMUX44_s
21745 {
21746  uint32_t sel : 1; /* GPIO/Loan IO44Input Mux Selection Field */
21747  uint32_t : 31; /* *UNDEFINED* */
21748 };
21749 
21750 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX44. */
21751 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX44_s ALT_SYSMGR_PINMUX_GPLMUX44_t;
21752 #endif /* __ASSEMBLY__ */
21753 
21754 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX44 register from the beginning of the component. */
21755 #define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284
21756 
21757 /*
21758  * Register : GPIO/LoanIO 45 Output/Output Enable Mux Selection Register - GPLMUX45
21759  *
21760  * Selection between GPIO and LoanIO output and output enable for GPIO45 and
21761  * LoanIO45. These signals drive the Pin Mux. The Pin Mux must be configured to use
21762  * GPIO/LoanIO in addition to these settings
21763  *
21764  * Only reset by a cold reset (ignores warm reset).
21765  *
21766  * NOTE: These registers should not be modified after IO configuration.There is no
21767  * support for dynamically changing the Pin Mux selections.
21768  *
21769  * Register Layout
21770  *
21771  * Bits | Access | Reset | Description
21772  * :-------|:-------|:------|:----------------------------------------
21773  * [0] | RW | 0x0 | GPIO/Loan IO45Input Mux Selection Field
21774  * [31:1] | ??? | 0x0 | *UNDEFINED*
21775  *
21776  */
21777 /*
21778  * Field : GPIO/Loan IO45Input Mux Selection Field - sel
21779  *
21780  * Select source for GPIO/LoanIO 45.
21781  *
21782  * 0 : LoanIO 45 controls GPIO/LOANIO[45] output and output enable signals.
21783  *
21784  * 1 : GPIO 45 controls GPIO/LOANI[45] output and output enable signals.
21785  *
21786  * Field Access Macros:
21787  *
21788  */
21789 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21790 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0
21791 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21792 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0
21793 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21794 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1
21795 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */
21796 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001
21797 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value. */
21798 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe
21799 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field. */
21800 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0
21801 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX45_SEL field value from a register. */
21802 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0)
21803 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX45_SEL register field value suitable for setting the register. */
21804 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001)
21805 
21806 #ifndef __ASSEMBLY__
21807 /*
21808  * WARNING: The C register and register group struct declarations are provided for
21809  * convenience and illustrative purposes. They should, however, be used with
21810  * caution as the C language standard provides no guarantees about the alignment or
21811  * atomicity of device memory accesses. The recommended practice for writing
21812  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21813  * alt_write_word() functions.
21814  *
21815  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX45.
21816  */
21817 struct ALT_SYSMGR_PINMUX_GPLMUX45_s
21818 {
21819  uint32_t sel : 1; /* GPIO/Loan IO45Input Mux Selection Field */
21820  uint32_t : 31; /* *UNDEFINED* */
21821 };
21822 
21823 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX45. */
21824 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX45_s ALT_SYSMGR_PINMUX_GPLMUX45_t;
21825 #endif /* __ASSEMBLY__ */
21826 
21827 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX45 register from the beginning of the component. */
21828 #define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288
21829 
21830 /*
21831  * Register : GPIO/LoanIO 46 Output/Output Enable Mux Selection Register - GPLMUX46
21832  *
21833  * Selection between GPIO and LoanIO output and output enable for GPIO46 and
21834  * LoanIO46. These signals drive the Pin Mux. The Pin Mux must be configured to use
21835  * GPIO/LoanIO in addition to these settings
21836  *
21837  * Only reset by a cold reset (ignores warm reset).
21838  *
21839  * NOTE: These registers should not be modified after IO configuration.There is no
21840  * support for dynamically changing the Pin Mux selections.
21841  *
21842  * Register Layout
21843  *
21844  * Bits | Access | Reset | Description
21845  * :-------|:-------|:------|:----------------------------------------
21846  * [0] | RW | 0x0 | GPIO/Loan IO46Input Mux Selection Field
21847  * [31:1] | ??? | 0x0 | *UNDEFINED*
21848  *
21849  */
21850 /*
21851  * Field : GPIO/Loan IO46Input Mux Selection Field - sel
21852  *
21853  * Select source for GPIO/LoanIO 46.
21854  *
21855  * 0 : LoanIO 46 controls GPIO/LOANIO[46] output and output enable signals.
21856  *
21857  * 1 : GPIO 46 controls GPIO/LOANI[46] output and output enable signals.
21858  *
21859  * Field Access Macros:
21860  *
21861  */
21862 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21863 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0
21864 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21865 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0
21866 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21867 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1
21868 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */
21869 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001
21870 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value. */
21871 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe
21872 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field. */
21873 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0
21874 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX46_SEL field value from a register. */
21875 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0)
21876 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX46_SEL register field value suitable for setting the register. */
21877 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001)
21878 
21879 #ifndef __ASSEMBLY__
21880 /*
21881  * WARNING: The C register and register group struct declarations are provided for
21882  * convenience and illustrative purposes. They should, however, be used with
21883  * caution as the C language standard provides no guarantees about the alignment or
21884  * atomicity of device memory accesses. The recommended practice for writing
21885  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21886  * alt_write_word() functions.
21887  *
21888  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX46.
21889  */
21890 struct ALT_SYSMGR_PINMUX_GPLMUX46_s
21891 {
21892  uint32_t sel : 1; /* GPIO/Loan IO46Input Mux Selection Field */
21893  uint32_t : 31; /* *UNDEFINED* */
21894 };
21895 
21896 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX46. */
21897 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX46_s ALT_SYSMGR_PINMUX_GPLMUX46_t;
21898 #endif /* __ASSEMBLY__ */
21899 
21900 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX46 register from the beginning of the component. */
21901 #define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c
21902 
21903 /*
21904  * Register : GPIO/LoanIO 47 Output/Output Enable Mux Selection Register - GPLMUX47
21905  *
21906  * Selection between GPIO and LoanIO output and output enable for GPIO47 and
21907  * LoanIO47. These signals drive the Pin Mux. The Pin Mux must be configured to use
21908  * GPIO/LoanIO in addition to these settings
21909  *
21910  * Only reset by a cold reset (ignores warm reset).
21911  *
21912  * NOTE: These registers should not be modified after IO configuration.There is no
21913  * support for dynamically changing the Pin Mux selections.
21914  *
21915  * Register Layout
21916  *
21917  * Bits | Access | Reset | Description
21918  * :-------|:-------|:------|:----------------------------------------
21919  * [0] | RW | 0x0 | GPIO/Loan IO47Input Mux Selection Field
21920  * [31:1] | ??? | 0x0 | *UNDEFINED*
21921  *
21922  */
21923 /*
21924  * Field : GPIO/Loan IO47Input Mux Selection Field - sel
21925  *
21926  * Select source for GPIO/LoanIO 47.
21927  *
21928  * 0 : LoanIO 47 controls GPIO/LOANIO[47] output and output enable signals.
21929  *
21930  * 1 : GPIO 47 controls GPIO/LOANI[47] output and output enable signals.
21931  *
21932  * Field Access Macros:
21933  *
21934  */
21935 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21936 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0
21937 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21938 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0
21939 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21940 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1
21941 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */
21942 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001
21943 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value. */
21944 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe
21945 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field. */
21946 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0
21947 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX47_SEL field value from a register. */
21948 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0)
21949 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX47_SEL register field value suitable for setting the register. */
21950 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001)
21951 
21952 #ifndef __ASSEMBLY__
21953 /*
21954  * WARNING: The C register and register group struct declarations are provided for
21955  * convenience and illustrative purposes. They should, however, be used with
21956  * caution as the C language standard provides no guarantees about the alignment or
21957  * atomicity of device memory accesses. The recommended practice for writing
21958  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
21959  * alt_write_word() functions.
21960  *
21961  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX47.
21962  */
21963 struct ALT_SYSMGR_PINMUX_GPLMUX47_s
21964 {
21965  uint32_t sel : 1; /* GPIO/Loan IO47Input Mux Selection Field */
21966  uint32_t : 31; /* *UNDEFINED* */
21967 };
21968 
21969 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX47. */
21970 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX47_s ALT_SYSMGR_PINMUX_GPLMUX47_t;
21971 #endif /* __ASSEMBLY__ */
21972 
21973 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX47 register from the beginning of the component. */
21974 #define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290
21975 
21976 /*
21977  * Register : GPIO/LoanIO 48 Output/Output Enable Mux Selection Register - GPLMUX48
21978  *
21979  * Selection between GPIO and LoanIO output and output enable for GPIO48 and
21980  * LoanIO48. These signals drive the Pin Mux. The Pin Mux must be configured to use
21981  * GPIO/LoanIO in addition to these settings
21982  *
21983  * Only reset by a cold reset (ignores warm reset).
21984  *
21985  * NOTE: These registers should not be modified after IO configuration.There is no
21986  * support for dynamically changing the Pin Mux selections.
21987  *
21988  * Register Layout
21989  *
21990  * Bits | Access | Reset | Description
21991  * :-------|:-------|:------|:----------------------------------------
21992  * [0] | RW | 0x0 | GPIO/Loan IO48Input Mux Selection Field
21993  * [31:1] | ??? | 0x0 | *UNDEFINED*
21994  *
21995  */
21996 /*
21997  * Field : GPIO/Loan IO48Input Mux Selection Field - sel
21998  *
21999  * Select source for GPIO/LoanIO 48.
22000  *
22001  * 0 : LoanIO 48 controls GPIO/LOANIO[48] output and output enable signals.
22002  *
22003  * 1 : GPIO 48 controls GPIO/LOANI[48] output and output enable signals.
22004  *
22005  * Field Access Macros:
22006  *
22007  */
22008 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22009 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0
22010 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22011 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0
22012 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22013 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1
22014 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */
22015 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001
22016 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value. */
22017 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe
22018 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field. */
22019 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0
22020 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX48_SEL field value from a register. */
22021 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
22022 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX48_SEL register field value suitable for setting the register. */
22023 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
22024 
22025 #ifndef __ASSEMBLY__
22026 /*
22027  * WARNING: The C register and register group struct declarations are provided for
22028  * convenience and illustrative purposes. They should, however, be used with
22029  * caution as the C language standard provides no guarantees about the alignment or
22030  * atomicity of device memory accesses. The recommended practice for writing
22031  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22032  * alt_write_word() functions.
22033  *
22034  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX48.
22035  */
22036 struct ALT_SYSMGR_PINMUX_GPLMUX48_s
22037 {
22038  uint32_t sel : 1; /* GPIO/Loan IO48Input Mux Selection Field */
22039  uint32_t : 31; /* *UNDEFINED* */
22040 };
22041 
22042 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX48. */
22043 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX48_s ALT_SYSMGR_PINMUX_GPLMUX48_t;
22044 #endif /* __ASSEMBLY__ */
22045 
22046 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX48 register from the beginning of the component. */
22047 #define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294
22048 
22049 /*
22050  * Register : GPIO/LoanIO 49 Output/Output Enable Mux Selection Register - GPLMUX49
22051  *
22052  * Selection between GPIO and LoanIO output and output enable for GPIO49 and
22053  * LoanIO49. These signals drive the Pin Mux. The Pin Mux must be configured to use
22054  * GPIO/LoanIO in addition to these settings
22055  *
22056  * Only reset by a cold reset (ignores warm reset).
22057  *
22058  * NOTE: These registers should not be modified after IO configuration.There is no
22059  * support for dynamically changing the Pin Mux selections.
22060  *
22061  * Register Layout
22062  *
22063  * Bits | Access | Reset | Description
22064  * :-------|:-------|:------|:----------------------------------------
22065  * [0] | RW | 0x0 | GPIO/Loan IO49Input Mux Selection Field
22066  * [31:1] | ??? | 0x0 | *UNDEFINED*
22067  *
22068  */
22069 /*
22070  * Field : GPIO/Loan IO49Input Mux Selection Field - sel
22071  *
22072  * Select source for GPIO/LoanIO 49.
22073  *
22074  * 0 : LoanIO 49 controls GPIO/LOANIO[49] output and output enable signals.
22075  *
22076  * 1 : GPIO 49 controls GPIO/LOANI[49] output and output enable signals.
22077  *
22078  * Field Access Macros:
22079  *
22080  */
22081 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22082 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0
22083 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22084 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0
22085 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22086 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1
22087 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */
22088 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001
22089 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value. */
22090 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe
22091 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field. */
22092 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0
22093 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX49_SEL field value from a register. */
22094 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
22095 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX49_SEL register field value suitable for setting the register. */
22096 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
22097 
22098 #ifndef __ASSEMBLY__
22099 /*
22100  * WARNING: The C register and register group struct declarations are provided for
22101  * convenience and illustrative purposes. They should, however, be used with
22102  * caution as the C language standard provides no guarantees about the alignment or
22103  * atomicity of device memory accesses. The recommended practice for writing
22104  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22105  * alt_write_word() functions.
22106  *
22107  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX49.
22108  */
22109 struct ALT_SYSMGR_PINMUX_GPLMUX49_s
22110 {
22111  uint32_t sel : 1; /* GPIO/Loan IO49Input Mux Selection Field */
22112  uint32_t : 31; /* *UNDEFINED* */
22113 };
22114 
22115 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX49. */
22116 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX49_s ALT_SYSMGR_PINMUX_GPLMUX49_t;
22117 #endif /* __ASSEMBLY__ */
22118 
22119 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX49 register from the beginning of the component. */
22120 #define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298
22121 
22122 /*
22123  * Register : GPIO/LoanIO 50 Output/Output Enable Mux Selection Register - GPLMUX50
22124  *
22125  * Selection between GPIO and LoanIO output and output enable for GPIO50 and
22126  * LoanIO50. These signals drive the Pin Mux. The Pin Mux must be configured to use
22127  * GPIO/LoanIO in addition to these settings
22128  *
22129  * Only reset by a cold reset (ignores warm reset).
22130  *
22131  * NOTE: These registers should not be modified after IO configuration.There is no
22132  * support for dynamically changing the Pin Mux selections.
22133  *
22134  * Register Layout
22135  *
22136  * Bits | Access | Reset | Description
22137  * :-------|:-------|:------|:----------------------------------------
22138  * [0] | RW | 0x0 | GPIO/Loan IO50Input Mux Selection Field
22139  * [31:1] | ??? | 0x0 | *UNDEFINED*
22140  *
22141  */
22142 /*
22143  * Field : GPIO/Loan IO50Input Mux Selection Field - sel
22144  *
22145  * Select source for GPIO/LoanIO 50.
22146  *
22147  * 0 : LoanIO 50 controls GPIO/LOANIO[50] output and output enable signals.
22148  *
22149  * 1 : GPIO 50 controls GPIO/LOANI[50] output and output enable signals.
22150  *
22151  * Field Access Macros:
22152  *
22153  */
22154 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22155 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0
22156 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22157 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0
22158 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22159 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1
22160 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */
22161 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001
22162 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value. */
22163 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe
22164 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field. */
22165 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0
22166 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX50_SEL field value from a register. */
22167 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
22168 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX50_SEL register field value suitable for setting the register. */
22169 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
22170 
22171 #ifndef __ASSEMBLY__
22172 /*
22173  * WARNING: The C register and register group struct declarations are provided for
22174  * convenience and illustrative purposes. They should, however, be used with
22175  * caution as the C language standard provides no guarantees about the alignment or
22176  * atomicity of device memory accesses. The recommended practice for writing
22177  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22178  * alt_write_word() functions.
22179  *
22180  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX50.
22181  */
22182 struct ALT_SYSMGR_PINMUX_GPLMUX50_s
22183 {
22184  uint32_t sel : 1; /* GPIO/Loan IO50Input Mux Selection Field */
22185  uint32_t : 31; /* *UNDEFINED* */
22186 };
22187 
22188 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX50. */
22189 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX50_s ALT_SYSMGR_PINMUX_GPLMUX50_t;
22190 #endif /* __ASSEMBLY__ */
22191 
22192 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX50 register from the beginning of the component. */
22193 #define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c
22194 
22195 /*
22196  * Register : GPIO/LoanIO 51 Output/Output Enable Mux Selection Register - GPLMUX51
22197  *
22198  * Selection between GPIO and LoanIO output and output enable for GPIO51 and
22199  * LoanIO51. These signals drive the Pin Mux. The Pin Mux must be configured to use
22200  * GPIO/LoanIO in addition to these settings
22201  *
22202  * Only reset by a cold reset (ignores warm reset).
22203  *
22204  * NOTE: These registers should not be modified after IO configuration.There is no
22205  * support for dynamically changing the Pin Mux selections.
22206  *
22207  * Register Layout
22208  *
22209  * Bits | Access | Reset | Description
22210  * :-------|:-------|:------|:----------------------------------------
22211  * [0] | RW | 0x0 | GPIO/Loan IO51Input Mux Selection Field
22212  * [31:1] | ??? | 0x0 | *UNDEFINED*
22213  *
22214  */
22215 /*
22216  * Field : GPIO/Loan IO51Input Mux Selection Field - sel
22217  *
22218  * Select source for GPIO/LoanIO 51.
22219  *
22220  * 0 : LoanIO 51 controls GPIO/LOANIO[51] output and output enable signals.
22221  *
22222  * 1 : GPIO 51 controls GPIO/LOANI[51] output and output enable signals.
22223  *
22224  * Field Access Macros:
22225  *
22226  */
22227 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22228 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0
22229 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22230 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0
22231 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22232 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1
22233 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */
22234 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001
22235 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value. */
22236 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe
22237 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field. */
22238 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0
22239 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX51_SEL field value from a register. */
22240 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
22241 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX51_SEL register field value suitable for setting the register. */
22242 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
22243 
22244 #ifndef __ASSEMBLY__
22245 /*
22246  * WARNING: The C register and register group struct declarations are provided for
22247  * convenience and illustrative purposes. They should, however, be used with
22248  * caution as the C language standard provides no guarantees about the alignment or
22249  * atomicity of device memory accesses. The recommended practice for writing
22250  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22251  * alt_write_word() functions.
22252  *
22253  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX51.
22254  */
22255 struct ALT_SYSMGR_PINMUX_GPLMUX51_s
22256 {
22257  uint32_t sel : 1; /* GPIO/Loan IO51Input Mux Selection Field */
22258  uint32_t : 31; /* *UNDEFINED* */
22259 };
22260 
22261 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX51. */
22262 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX51_s ALT_SYSMGR_PINMUX_GPLMUX51_t;
22263 #endif /* __ASSEMBLY__ */
22264 
22265 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX51 register from the beginning of the component. */
22266 #define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0
22267 
22268 /*
22269  * Register : GPIO/LoanIO 52 Output/Output Enable Mux Selection Register - GPLMUX52
22270  *
22271  * Selection between GPIO and LoanIO output and output enable for GPIO52 and
22272  * LoanIO52. These signals drive the Pin Mux. The Pin Mux must be configured to use
22273  * GPIO/LoanIO in addition to these settings
22274  *
22275  * Only reset by a cold reset (ignores warm reset).
22276  *
22277  * NOTE: These registers should not be modified after IO configuration.There is no
22278  * support for dynamically changing the Pin Mux selections.
22279  *
22280  * Register Layout
22281  *
22282  * Bits | Access | Reset | Description
22283  * :-------|:-------|:------|:----------------------------------------
22284  * [0] | RW | 0x0 | GPIO/Loan IO52Input Mux Selection Field
22285  * [31:1] | ??? | 0x0 | *UNDEFINED*
22286  *
22287  */
22288 /*
22289  * Field : GPIO/Loan IO52Input Mux Selection Field - sel
22290  *
22291  * Select source for GPIO/LoanIO 52.
22292  *
22293  * 0 : LoanIO 52 controls GPIO/LOANIO[52] output and output enable signals.
22294  *
22295  * 1 : GPIO 52 controls GPIO/LOANI[52] output and output enable signals.
22296  *
22297  * Field Access Macros:
22298  *
22299  */
22300 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22301 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0
22302 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22303 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0
22304 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22305 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1
22306 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */
22307 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001
22308 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value. */
22309 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe
22310 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field. */
22311 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0
22312 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX52_SEL field value from a register. */
22313 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
22314 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX52_SEL register field value suitable for setting the register. */
22315 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
22316 
22317 #ifndef __ASSEMBLY__
22318 /*
22319  * WARNING: The C register and register group struct declarations are provided for
22320  * convenience and illustrative purposes. They should, however, be used with
22321  * caution as the C language standard provides no guarantees about the alignment or
22322  * atomicity of device memory accesses. The recommended practice for writing
22323  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22324  * alt_write_word() functions.
22325  *
22326  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX52.
22327  */
22328 struct ALT_SYSMGR_PINMUX_GPLMUX52_s
22329 {
22330  uint32_t sel : 1; /* GPIO/Loan IO52Input Mux Selection Field */
22331  uint32_t : 31; /* *UNDEFINED* */
22332 };
22333 
22334 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX52. */
22335 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX52_s ALT_SYSMGR_PINMUX_GPLMUX52_t;
22336 #endif /* __ASSEMBLY__ */
22337 
22338 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX52 register from the beginning of the component. */
22339 #define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4
22340 
22341 /*
22342  * Register : GPIO/LoanIO 53 Output/Output Enable Mux Selection Register - GPLMUX53
22343  *
22344  * Selection between GPIO and LoanIO output and output enable for GPIO53 and
22345  * LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use
22346  * GPIO/LoanIO in addition to these settings
22347  *
22348  * Only reset by a cold reset (ignores warm reset).
22349  *
22350  * NOTE: These registers should not be modified after IO configuration.There is no
22351  * support for dynamically changing the Pin Mux selections.
22352  *
22353  * Register Layout
22354  *
22355  * Bits | Access | Reset | Description
22356  * :-------|:-------|:------|:----------------------------------------
22357  * [0] | RW | 0x0 | GPIO/Loan IO53Input Mux Selection Field
22358  * [31:1] | ??? | 0x0 | *UNDEFINED*
22359  *
22360  */
22361 /*
22362  * Field : GPIO/Loan IO53Input Mux Selection Field - sel
22363  *
22364  * Select source for GPIO/LoanIO 53.
22365  *
22366  * 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals.
22367  *
22368  * 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals.
22369  *
22370  * Field Access Macros:
22371  *
22372  */
22373 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22374 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0
22375 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22376 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0
22377 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22378 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1
22379 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */
22380 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001
22381 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value. */
22382 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe
22383 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field. */
22384 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0
22385 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX53_SEL field value from a register. */
22386 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
22387 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX53_SEL register field value suitable for setting the register. */
22388 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
22389 
22390 #ifndef __ASSEMBLY__
22391 /*
22392  * WARNING: The C register and register group struct declarations are provided for
22393  * convenience and illustrative purposes. They should, however, be used with
22394  * caution as the C language standard provides no guarantees about the alignment or
22395  * atomicity of device memory accesses. The recommended practice for writing
22396  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22397  * alt_write_word() functions.
22398  *
22399  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX53.
22400  */
22401 struct ALT_SYSMGR_PINMUX_GPLMUX53_s
22402 {
22403  uint32_t sel : 1; /* GPIO/Loan IO53Input Mux Selection Field */
22404  uint32_t : 31; /* *UNDEFINED* */
22405 };
22406 
22407 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX53. */
22408 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX53_s ALT_SYSMGR_PINMUX_GPLMUX53_t;
22409 #endif /* __ASSEMBLY__ */
22410 
22411 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX53 register from the beginning of the component. */
22412 #define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8
22413 
22414 /*
22415  * Register : GPIO/LoanIO 54 Output/Output Enable Mux Selection Register - GPLMUX54
22416  *
22417  * Selection between GPIO and LoanIO output and output enable for GPIO54 and
22418  * LoanIO54. These signals drive the Pin Mux. The Pin Mux must be configured to use
22419  * GPIO/LoanIO in addition to these settings
22420  *
22421  * Only reset by a cold reset (ignores warm reset).
22422  *
22423  * NOTE: These registers should not be modified after IO configuration.There is no
22424  * support for dynamically changing the Pin Mux selections.
22425  *
22426  * Register Layout
22427  *
22428  * Bits | Access | Reset | Description
22429  * :-------|:-------|:------|:----------------------------------------
22430  * [0] | RW | 0x0 | GPIO/Loan IO54Input Mux Selection Field
22431  * [31:1] | ??? | 0x0 | *UNDEFINED*
22432  *
22433  */
22434 /*
22435  * Field : GPIO/Loan IO54Input Mux Selection Field - sel
22436  *
22437  * Select source for GPIO/LoanIO 54.
22438  *
22439  * 0 : LoanIO 54 controls GPIO/LOANIO[54] output and output enable signals.
22440  *
22441  * 1 : GPIO 54 controls GPIO/LOANI[54] output and output enable signals.
22442  *
22443  * Field Access Macros:
22444  *
22445  */
22446 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22447 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0
22448 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22449 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0
22450 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22451 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1
22452 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */
22453 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001
22454 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value. */
22455 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe
22456 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field. */
22457 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0
22458 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX54_SEL field value from a register. */
22459 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
22460 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX54_SEL register field value suitable for setting the register. */
22461 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
22462 
22463 #ifndef __ASSEMBLY__
22464 /*
22465  * WARNING: The C register and register group struct declarations are provided for
22466  * convenience and illustrative purposes. They should, however, be used with
22467  * caution as the C language standard provides no guarantees about the alignment or
22468  * atomicity of device memory accesses. The recommended practice for writing
22469  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22470  * alt_write_word() functions.
22471  *
22472  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX54.
22473  */
22474 struct ALT_SYSMGR_PINMUX_GPLMUX54_s
22475 {
22476  uint32_t sel : 1; /* GPIO/Loan IO54Input Mux Selection Field */
22477  uint32_t : 31; /* *UNDEFINED* */
22478 };
22479 
22480 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX54. */
22481 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX54_s ALT_SYSMGR_PINMUX_GPLMUX54_t;
22482 #endif /* __ASSEMBLY__ */
22483 
22484 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX54 register from the beginning of the component. */
22485 #define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac
22486 
22487 /*
22488  * Register : GPIO/LoanIO 55 Output/Output Enable Mux Selection Register - GPLMUX55
22489  *
22490  * Selection between GPIO and LoanIO output and output enable for GPIO55 and
22491  * LoanIO55. These signals drive the Pin Mux. The Pin Mux must be configured to use
22492  * GPIO/LoanIO in addition to these settings
22493  *
22494  * Only reset by a cold reset (ignores warm reset).
22495  *
22496  * NOTE: These registers should not be modified after IO configuration.There is no
22497  * support for dynamically changing the Pin Mux selections.
22498  *
22499  * Register Layout
22500  *
22501  * Bits | Access | Reset | Description
22502  * :-------|:-------|:------|:----------------------------------------
22503  * [0] | RW | 0x0 | GPIO/Loan IO55Input Mux Selection Field
22504  * [31:1] | ??? | 0x0 | *UNDEFINED*
22505  *
22506  */
22507 /*
22508  * Field : GPIO/Loan IO55Input Mux Selection Field - sel
22509  *
22510  * Select source for GPIO/LoanIO 55.
22511  *
22512  * 0 : LoanIO 55 controls GPIO/LOANIO[55] output and output enable signals.
22513  *
22514  * 1 : GPIO 55 controls GPIO/LOANI[55] output and output enable signals.
22515  *
22516  * Field Access Macros:
22517  *
22518  */
22519 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22520 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0
22521 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22522 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0
22523 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22524 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1
22525 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */
22526 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001
22527 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value. */
22528 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe
22529 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field. */
22530 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0
22531 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX55_SEL field value from a register. */
22532 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
22533 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX55_SEL register field value suitable for setting the register. */
22534 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
22535 
22536 #ifndef __ASSEMBLY__
22537 /*
22538  * WARNING: The C register and register group struct declarations are provided for
22539  * convenience and illustrative purposes. They should, however, be used with
22540  * caution as the C language standard provides no guarantees about the alignment or
22541  * atomicity of device memory accesses. The recommended practice for writing
22542  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22543  * alt_write_word() functions.
22544  *
22545  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX55.
22546  */
22547 struct ALT_SYSMGR_PINMUX_GPLMUX55_s
22548 {
22549  uint32_t sel : 1; /* GPIO/Loan IO55Input Mux Selection Field */
22550  uint32_t : 31; /* *UNDEFINED* */
22551 };
22552 
22553 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX55. */
22554 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX55_s ALT_SYSMGR_PINMUX_GPLMUX55_t;
22555 #endif /* __ASSEMBLY__ */
22556 
22557 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX55 register from the beginning of the component. */
22558 #define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0
22559 
22560 /*
22561  * Register : GPIO/LoanIO 56 Output/Output Enable Mux Selection Register - GPLMUX56
22562  *
22563  * Selection between GPIO and LoanIO output and output enable for GPIO56 and
22564  * LoanIO56. These signals drive the Pin Mux. The Pin Mux must be configured to use
22565  * GPIO/LoanIO in addition to these settings
22566  *
22567  * Only reset by a cold reset (ignores warm reset).
22568  *
22569  * NOTE: These registers should not be modified after IO configuration.There is no
22570  * support for dynamically changing the Pin Mux selections.
22571  *
22572  * Register Layout
22573  *
22574  * Bits | Access | Reset | Description
22575  * :-------|:-------|:------|:----------------------------------------
22576  * [0] | RW | 0x0 | GPIO/Loan IO56Input Mux Selection Field
22577  * [31:1] | ??? | 0x0 | *UNDEFINED*
22578  *
22579  */
22580 /*
22581  * Field : GPIO/Loan IO56Input Mux Selection Field - sel
22582  *
22583  * Select source for GPIO/LoanIO 56.
22584  *
22585  * 0 : LoanIO 56 controls GPIO/LOANIO[56] output and output enable signals.
22586  *
22587  * 1 : GPIO 56 controls GPIO/LOANI[56] output and output enable signals.
22588  *
22589  * Field Access Macros:
22590  *
22591  */
22592 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22593 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0
22594 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22595 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0
22596 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22597 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1
22598 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */
22599 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001
22600 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value. */
22601 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe
22602 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field. */
22603 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0
22604 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX56_SEL field value from a register. */
22605 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
22606 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX56_SEL register field value suitable for setting the register. */
22607 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
22608 
22609 #ifndef __ASSEMBLY__
22610 /*
22611  * WARNING: The C register and register group struct declarations are provided for
22612  * convenience and illustrative purposes. They should, however, be used with
22613  * caution as the C language standard provides no guarantees about the alignment or
22614  * atomicity of device memory accesses. The recommended practice for writing
22615  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22616  * alt_write_word() functions.
22617  *
22618  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX56.
22619  */
22620 struct ALT_SYSMGR_PINMUX_GPLMUX56_s
22621 {
22622  uint32_t sel : 1; /* GPIO/Loan IO56Input Mux Selection Field */
22623  uint32_t : 31; /* *UNDEFINED* */
22624 };
22625 
22626 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX56. */
22627 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX56_s ALT_SYSMGR_PINMUX_GPLMUX56_t;
22628 #endif /* __ASSEMBLY__ */
22629 
22630 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX56 register from the beginning of the component. */
22631 #define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4
22632 
22633 /*
22634  * Register : GPIO/LoanIO 57 Output/Output Enable Mux Selection Register - GPLMUX57
22635  *
22636  * Selection between GPIO and LoanIO output and output enable for GPIO57 and
22637  * LoanIO57. These signals drive the Pin Mux. The Pin Mux must be configured to use
22638  * GPIO/LoanIO in addition to these settings
22639  *
22640  * Only reset by a cold reset (ignores warm reset).
22641  *
22642  * NOTE: These registers should not be modified after IO configuration.There is no
22643  * support for dynamically changing the Pin Mux selections.
22644  *
22645  * Register Layout
22646  *
22647  * Bits | Access | Reset | Description
22648  * :-------|:-------|:------|:----------------------------------------
22649  * [0] | RW | 0x0 | GPIO/Loan IO57Input Mux Selection Field
22650  * [31:1] | ??? | 0x0 | *UNDEFINED*
22651  *
22652  */
22653 /*
22654  * Field : GPIO/Loan IO57Input Mux Selection Field - sel
22655  *
22656  * Select source for GPIO/LoanIO 57.
22657  *
22658  * 0 : LoanIO 57 controls GPIO/LOANIO[57] output and output enable signals.
22659  *
22660  * 1 : GPIO 57 controls GPIO/LOANI[57] output and output enable signals.
22661  *
22662  * Field Access Macros:
22663  *
22664  */
22665 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22666 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0
22667 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22668 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0
22669 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22670 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1
22671 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */
22672 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001
22673 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value. */
22674 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe
22675 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field. */
22676 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0
22677 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX57_SEL field value from a register. */
22678 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
22679 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX57_SEL register field value suitable for setting the register. */
22680 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
22681 
22682 #ifndef __ASSEMBLY__
22683 /*
22684  * WARNING: The C register and register group struct declarations are provided for
22685  * convenience and illustrative purposes. They should, however, be used with
22686  * caution as the C language standard provides no guarantees about the alignment or
22687  * atomicity of device memory accesses. The recommended practice for writing
22688  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22689  * alt_write_word() functions.
22690  *
22691  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX57.
22692  */
22693 struct ALT_SYSMGR_PINMUX_GPLMUX57_s
22694 {
22695  uint32_t sel : 1; /* GPIO/Loan IO57Input Mux Selection Field */
22696  uint32_t : 31; /* *UNDEFINED* */
22697 };
22698 
22699 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX57. */
22700 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX57_s ALT_SYSMGR_PINMUX_GPLMUX57_t;
22701 #endif /* __ASSEMBLY__ */
22702 
22703 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX57 register from the beginning of the component. */
22704 #define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8
22705 
22706 /*
22707  * Register : GPIO/LoanIO 58 Output/Output Enable Mux Selection Register - GPLMUX58
22708  *
22709  * Selection between GPIO and LoanIO output and output enable for GPIO58 and
22710  * LoanIO58. These signals drive the Pin Mux. The Pin Mux must be configured to use
22711  * GPIO/LoanIO in addition to these settings
22712  *
22713  * Only reset by a cold reset (ignores warm reset).
22714  *
22715  * NOTE: These registers should not be modified after IO configuration.There is no
22716  * support for dynamically changing the Pin Mux selections.
22717  *
22718  * Register Layout
22719  *
22720  * Bits | Access | Reset | Description
22721  * :-------|:-------|:------|:----------------------------------------
22722  * [0] | RW | 0x0 | GPIO/Loan IO58Input Mux Selection Field
22723  * [31:1] | ??? | 0x0 | *UNDEFINED*
22724  *
22725  */
22726 /*
22727  * Field : GPIO/Loan IO58Input Mux Selection Field - sel
22728  *
22729  * Select source for GPIO/LoanIO 58.
22730  *
22731  * 0 : LoanIO 58 controls GPIO/LOANIO[58] output and output enable signals.
22732  *
22733  * 1 : GPIO 58 controls GPIO/LOANI[58] output and output enable signals.
22734  *
22735  * Field Access Macros:
22736  *
22737  */
22738 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22739 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0
22740 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22741 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0
22742 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22743 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1
22744 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */
22745 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001
22746 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value. */
22747 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe
22748 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field. */
22749 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0
22750 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX58_SEL field value from a register. */
22751 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
22752 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX58_SEL register field value suitable for setting the register. */
22753 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
22754 
22755 #ifndef __ASSEMBLY__
22756 /*
22757  * WARNING: The C register and register group struct declarations are provided for
22758  * convenience and illustrative purposes. They should, however, be used with
22759  * caution as the C language standard provides no guarantees about the alignment or
22760  * atomicity of device memory accesses. The recommended practice for writing
22761  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22762  * alt_write_word() functions.
22763  *
22764  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX58.
22765  */
22766 struct ALT_SYSMGR_PINMUX_GPLMUX58_s
22767 {
22768  uint32_t sel : 1; /* GPIO/Loan IO58Input Mux Selection Field */
22769  uint32_t : 31; /* *UNDEFINED* */
22770 };
22771 
22772 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX58. */
22773 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX58_s ALT_SYSMGR_PINMUX_GPLMUX58_t;
22774 #endif /* __ASSEMBLY__ */
22775 
22776 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX58 register from the beginning of the component. */
22777 #define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc
22778 
22779 /*
22780  * Register : GPIO/LoanIO 59 Output/Output Enable Mux Selection Register - GPLMUX59
22781  *
22782  * Selection between GPIO and LoanIO output and output enable for GPIO59 and
22783  * LoanIO59. These signals drive the Pin Mux. The Pin Mux must be configured to use
22784  * GPIO/LoanIO in addition to these settings
22785  *
22786  * Only reset by a cold reset (ignores warm reset).
22787  *
22788  * NOTE: These registers should not be modified after IO configuration.There is no
22789  * support for dynamically changing the Pin Mux selections.
22790  *
22791  * Register Layout
22792  *
22793  * Bits | Access | Reset | Description
22794  * :-------|:-------|:------|:----------------------------------------
22795  * [0] | RW | 0x0 | GPIO/Loan IO59Input Mux Selection Field
22796  * [31:1] | ??? | 0x0 | *UNDEFINED*
22797  *
22798  */
22799 /*
22800  * Field : GPIO/Loan IO59Input Mux Selection Field - sel
22801  *
22802  * Select source for GPIO/LoanIO 59.
22803  *
22804  * 0 : LoanIO 59 controls GPIO/LOANIO[59] output and output enable signals.
22805  *
22806  * 1 : GPIO 59 controls GPIO/LOANI[59] output and output enable signals.
22807  *
22808  * Field Access Macros:
22809  *
22810  */
22811 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22812 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0
22813 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22814 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0
22815 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22816 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1
22817 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */
22818 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001
22819 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value. */
22820 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe
22821 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field. */
22822 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0
22823 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX59_SEL field value from a register. */
22824 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
22825 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX59_SEL register field value suitable for setting the register. */
22826 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
22827 
22828 #ifndef __ASSEMBLY__
22829 /*
22830  * WARNING: The C register and register group struct declarations are provided for
22831  * convenience and illustrative purposes. They should, however, be used with
22832  * caution as the C language standard provides no guarantees about the alignment or
22833  * atomicity of device memory accesses. The recommended practice for writing
22834  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22835  * alt_write_word() functions.
22836  *
22837  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX59.
22838  */
22839 struct ALT_SYSMGR_PINMUX_GPLMUX59_s
22840 {
22841  uint32_t sel : 1; /* GPIO/Loan IO59Input Mux Selection Field */
22842  uint32_t : 31; /* *UNDEFINED* */
22843 };
22844 
22845 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX59. */
22846 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX59_s ALT_SYSMGR_PINMUX_GPLMUX59_t;
22847 #endif /* __ASSEMBLY__ */
22848 
22849 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX59 register from the beginning of the component. */
22850 #define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0
22851 
22852 /*
22853  * Register : GPIO/LoanIO 60 Output/Output Enable Mux Selection Register - GPLMUX60
22854  *
22855  * Selection between GPIO and LoanIO output and output enable for GPIO60 and
22856  * LoanIO60. These signals drive the Pin Mux. The Pin Mux must be configured to use
22857  * GPIO/LoanIO in addition to these settings
22858  *
22859  * Only reset by a cold reset (ignores warm reset).
22860  *
22861  * NOTE: These registers should not be modified after IO configuration.There is no
22862  * support for dynamically changing the Pin Mux selections.
22863  *
22864  * Register Layout
22865  *
22866  * Bits | Access | Reset | Description
22867  * :-------|:-------|:------|:----------------------------------------
22868  * [0] | RW | 0x0 | GPIO/Loan IO60Input Mux Selection Field
22869  * [31:1] | ??? | 0x0 | *UNDEFINED*
22870  *
22871  */
22872 /*
22873  * Field : GPIO/Loan IO60Input Mux Selection Field - sel
22874  *
22875  * Select source for GPIO/LoanIO 60.
22876  *
22877  * 0 : LoanIO 60 controls GPIO/LOANIO[60] output and output enable signals.
22878  *
22879  * 1 : GPIO 60 controls GPIO/LOANI[60] output and output enable signals.
22880  *
22881  * Field Access Macros:
22882  *
22883  */
22884 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22885 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0
22886 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22887 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0
22888 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22889 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1
22890 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */
22891 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001
22892 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value. */
22893 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe
22894 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field. */
22895 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0
22896 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX60_SEL field value from a register. */
22897 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
22898 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX60_SEL register field value suitable for setting the register. */
22899 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
22900 
22901 #ifndef __ASSEMBLY__
22902 /*
22903  * WARNING: The C register and register group struct declarations are provided for
22904  * convenience and illustrative purposes. They should, however, be used with
22905  * caution as the C language standard provides no guarantees about the alignment or
22906  * atomicity of device memory accesses. The recommended practice for writing
22907  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22908  * alt_write_word() functions.
22909  *
22910  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX60.
22911  */
22912 struct ALT_SYSMGR_PINMUX_GPLMUX60_s
22913 {
22914  uint32_t sel : 1; /* GPIO/Loan IO60Input Mux Selection Field */
22915  uint32_t : 31; /* *UNDEFINED* */
22916 };
22917 
22918 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX60. */
22919 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX60_s ALT_SYSMGR_PINMUX_GPLMUX60_t;
22920 #endif /* __ASSEMBLY__ */
22921 
22922 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX60 register from the beginning of the component. */
22923 #define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4
22924 
22925 /*
22926  * Register : GPIO/LoanIO 61 Output/Output Enable Mux Selection Register - GPLMUX61
22927  *
22928  * Selection between GPIO and LoanIO output and output enable for GPIO61 and
22929  * LoanIO61. These signals drive the Pin Mux. The Pin Mux must be configured to use
22930  * GPIO/LoanIO in addition to these settings
22931  *
22932  * Only reset by a cold reset (ignores warm reset).
22933  *
22934  * NOTE: These registers should not be modified after IO configuration.There is no
22935  * support for dynamically changing the Pin Mux selections.
22936  *
22937  * Register Layout
22938  *
22939  * Bits | Access | Reset | Description
22940  * :-------|:-------|:------|:----------------------------------------
22941  * [0] | RW | 0x0 | GPIO/Loan IO61Input Mux Selection Field
22942  * [31:1] | ??? | 0x0 | *UNDEFINED*
22943  *
22944  */
22945 /*
22946  * Field : GPIO/Loan IO61Input Mux Selection Field - sel
22947  *
22948  * Select source for GPIO/LoanIO 61.
22949  *
22950  * 0 : LoanIO 61 controls GPIO/LOANIO[61] output and output enable signals.
22951  *
22952  * 1 : GPIO 61 controls GPIO/LOANI[61] output and output enable signals.
22953  *
22954  * Field Access Macros:
22955  *
22956  */
22957 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22958 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0
22959 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22960 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0
22961 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22962 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1
22963 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */
22964 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001
22965 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value. */
22966 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe
22967 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field. */
22968 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0
22969 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX61_SEL field value from a register. */
22970 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
22971 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX61_SEL register field value suitable for setting the register. */
22972 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
22973 
22974 #ifndef __ASSEMBLY__
22975 /*
22976  * WARNING: The C register and register group struct declarations are provided for
22977  * convenience and illustrative purposes. They should, however, be used with
22978  * caution as the C language standard provides no guarantees about the alignment or
22979  * atomicity of device memory accesses. The recommended practice for writing
22980  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
22981  * alt_write_word() functions.
22982  *
22983  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX61.
22984  */
22985 struct ALT_SYSMGR_PINMUX_GPLMUX61_s
22986 {
22987  uint32_t sel : 1; /* GPIO/Loan IO61Input Mux Selection Field */
22988  uint32_t : 31; /* *UNDEFINED* */
22989 };
22990 
22991 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX61. */
22992 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX61_s ALT_SYSMGR_PINMUX_GPLMUX61_t;
22993 #endif /* __ASSEMBLY__ */
22994 
22995 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX61 register from the beginning of the component. */
22996 #define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8
22997 
22998 /*
22999  * Register : GPIO/LoanIO 62 Output/Output Enable Mux Selection Register - GPLMUX62
23000  *
23001  * Selection between GPIO and LoanIO output and output enable for GPIO62 and
23002  * LoanIO62. These signals drive the Pin Mux. The Pin Mux must be configured to use
23003  * GPIO/LoanIO in addition to these settings
23004  *
23005  * Only reset by a cold reset (ignores warm reset).
23006  *
23007  * NOTE: These registers should not be modified after IO configuration.There is no
23008  * support for dynamically changing the Pin Mux selections.
23009  *
23010  * Register Layout
23011  *
23012  * Bits | Access | Reset | Description
23013  * :-------|:-------|:------|:----------------------------------------
23014  * [0] | RW | 0x0 | GPIO/Loan IO62Input Mux Selection Field
23015  * [31:1] | ??? | 0x0 | *UNDEFINED*
23016  *
23017  */
23018 /*
23019  * Field : GPIO/Loan IO62Input Mux Selection Field - sel
23020  *
23021  * Select source for GPIO/LoanIO 62.
23022  *
23023  * 0 : LoanIO 62 controls GPIO/LOANIO[62] output and output enable signals.
23024  *
23025  * 1 : GPIO 62 controls GPIO/LOANI[62] output and output enable signals.
23026  *
23027  * Field Access Macros:
23028  *
23029  */
23030 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23031 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0
23032 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23033 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0
23034 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23035 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1
23036 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */
23037 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001
23038 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value. */
23039 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe
23040 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field. */
23041 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0
23042 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX62_SEL field value from a register. */
23043 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
23044 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX62_SEL register field value suitable for setting the register. */
23045 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
23046 
23047 #ifndef __ASSEMBLY__
23048 /*
23049  * WARNING: The C register and register group struct declarations are provided for
23050  * convenience and illustrative purposes. They should, however, be used with
23051  * caution as the C language standard provides no guarantees about the alignment or
23052  * atomicity of device memory accesses. The recommended practice for writing
23053  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23054  * alt_write_word() functions.
23055  *
23056  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX62.
23057  */
23058 struct ALT_SYSMGR_PINMUX_GPLMUX62_s
23059 {
23060  uint32_t sel : 1; /* GPIO/Loan IO62Input Mux Selection Field */
23061  uint32_t : 31; /* *UNDEFINED* */
23062 };
23063 
23064 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX62. */
23065 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX62_s ALT_SYSMGR_PINMUX_GPLMUX62_t;
23066 #endif /* __ASSEMBLY__ */
23067 
23068 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX62 register from the beginning of the component. */
23069 #define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc
23070 
23071 /*
23072  * Register : GPIO/LoanIO 63 Output/Output Enable Mux Selection Register - GPLMUX63
23073  *
23074  * Selection between GPIO and LoanIO output and output enable for GPIO63 and
23075  * LoanIO63. These signals drive the Pin Mux. The Pin Mux must be configured to use
23076  * GPIO/LoanIO in addition to these settings
23077  *
23078  * Only reset by a cold reset (ignores warm reset).
23079  *
23080  * NOTE: These registers should not be modified after IO configuration.There is no
23081  * support for dynamically changing the Pin Mux selections.
23082  *
23083  * Register Layout
23084  *
23085  * Bits | Access | Reset | Description
23086  * :-------|:-------|:------|:----------------------------------------
23087  * [0] | RW | 0x0 | GPIO/Loan IO63Input Mux Selection Field
23088  * [31:1] | ??? | 0x0 | *UNDEFINED*
23089  *
23090  */
23091 /*
23092  * Field : GPIO/Loan IO63Input Mux Selection Field - sel
23093  *
23094  * Select source for GPIO/LoanIO 63.
23095  *
23096  * 0 : LoanIO 63 controls GPIO/LOANIO[63] output and output enable signals.
23097  *
23098  * 1 : GPIO 63 controls GPIO/LOANI[63] output and output enable signals.
23099  *
23100  * Field Access Macros:
23101  *
23102  */
23103 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23104 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0
23105 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23106 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0
23107 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23108 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1
23109 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */
23110 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001
23111 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value. */
23112 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe
23113 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field. */
23114 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0
23115 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX63_SEL field value from a register. */
23116 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
23117 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX63_SEL register field value suitable for setting the register. */
23118 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
23119 
23120 #ifndef __ASSEMBLY__
23121 /*
23122  * WARNING: The C register and register group struct declarations are provided for
23123  * convenience and illustrative purposes. They should, however, be used with
23124  * caution as the C language standard provides no guarantees about the alignment or
23125  * atomicity of device memory accesses. The recommended practice for writing
23126  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23127  * alt_write_word() functions.
23128  *
23129  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX63.
23130  */
23131 struct ALT_SYSMGR_PINMUX_GPLMUX63_s
23132 {
23133  uint32_t sel : 1; /* GPIO/Loan IO63Input Mux Selection Field */
23134  uint32_t : 31; /* *UNDEFINED* */
23135 };
23136 
23137 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX63. */
23138 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX63_s ALT_SYSMGR_PINMUX_GPLMUX63_t;
23139 #endif /* __ASSEMBLY__ */
23140 
23141 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX63 register from the beginning of the component. */
23142 #define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0
23143 
23144 /*
23145  * Register : GPIO/LoanIO 64 Output/Output Enable Mux Selection Register - GPLMUX64
23146  *
23147  * Selection between GPIO and LoanIO output and output enable for GPIO64 and
23148  * LoanIO64. These signals drive the Pin Mux. The Pin Mux must be configured to use
23149  * GPIO/LoanIO in addition to these settings
23150  *
23151  * Only reset by a cold reset (ignores warm reset).
23152  *
23153  * NOTE: These registers should not be modified after IO configuration.There is no
23154  * support for dynamically changing the Pin Mux selections.
23155  *
23156  * Register Layout
23157  *
23158  * Bits | Access | Reset | Description
23159  * :-------|:-------|:------|:----------------------------------------
23160  * [0] | RW | 0x0 | GPIO/Loan IO64Input Mux Selection Field
23161  * [31:1] | ??? | 0x0 | *UNDEFINED*
23162  *
23163  */
23164 /*
23165  * Field : GPIO/Loan IO64Input Mux Selection Field - sel
23166  *
23167  * Select source for GPIO/LoanIO 64.
23168  *
23169  * 0 : LoanIO 64 controls GPIO/LOANIO[64] output and output enable signals.
23170  *
23171  * 1 : GPIO 64 controls GPIO/LOANI[64] output and output enable signals.
23172  *
23173  * Field Access Macros:
23174  *
23175  */
23176 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23177 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0
23178 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23179 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0
23180 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23181 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1
23182 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */
23183 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001
23184 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value. */
23185 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe
23186 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field. */
23187 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0
23188 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX64_SEL field value from a register. */
23189 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
23190 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX64_SEL register field value suitable for setting the register. */
23191 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
23192 
23193 #ifndef __ASSEMBLY__
23194 /*
23195  * WARNING: The C register and register group struct declarations are provided for
23196  * convenience and illustrative purposes. They should, however, be used with
23197  * caution as the C language standard provides no guarantees about the alignment or
23198  * atomicity of device memory accesses. The recommended practice for writing
23199  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23200  * alt_write_word() functions.
23201  *
23202  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX64.
23203  */
23204 struct ALT_SYSMGR_PINMUX_GPLMUX64_s
23205 {
23206  uint32_t sel : 1; /* GPIO/Loan IO64Input Mux Selection Field */
23207  uint32_t : 31; /* *UNDEFINED* */
23208 };
23209 
23210 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX64. */
23211 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX64_s ALT_SYSMGR_PINMUX_GPLMUX64_t;
23212 #endif /* __ASSEMBLY__ */
23213 
23214 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX64 register from the beginning of the component. */
23215 #define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4
23216 
23217 /*
23218  * Register : GPIO/LoanIO 65 Output/Output Enable Mux Selection Register - GPLMUX65
23219  *
23220  * Selection between GPIO and LoanIO output and output enable for GPIO65 and
23221  * LoanIO65. These signals drive the Pin Mux. The Pin Mux must be configured to use
23222  * GPIO/LoanIO in addition to these settings
23223  *
23224  * Only reset by a cold reset (ignores warm reset).
23225  *
23226  * NOTE: These registers should not be modified after IO configuration.There is no
23227  * support for dynamically changing the Pin Mux selections.
23228  *
23229  * Register Layout
23230  *
23231  * Bits | Access | Reset | Description
23232  * :-------|:-------|:------|:----------------------------------------
23233  * [0] | RW | 0x0 | GPIO/Loan IO65Input Mux Selection Field
23234  * [31:1] | ??? | 0x0 | *UNDEFINED*
23235  *
23236  */
23237 /*
23238  * Field : GPIO/Loan IO65Input Mux Selection Field - sel
23239  *
23240  * Select source for GPIO/LoanIO 65.
23241  *
23242  * 0 : LoanIO 65 controls GPIO/LOANIO[65] output and output enable signals.
23243  *
23244  * 1 : GPIO 65 controls GPIO/LOANI[65] output and output enable signals.
23245  *
23246  * Field Access Macros:
23247  *
23248  */
23249 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23250 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0
23251 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23252 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0
23253 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23254 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1
23255 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */
23256 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001
23257 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value. */
23258 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe
23259 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field. */
23260 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0
23261 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX65_SEL field value from a register. */
23262 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
23263 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX65_SEL register field value suitable for setting the register. */
23264 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
23265 
23266 #ifndef __ASSEMBLY__
23267 /*
23268  * WARNING: The C register and register group struct declarations are provided for
23269  * convenience and illustrative purposes. They should, however, be used with
23270  * caution as the C language standard provides no guarantees about the alignment or
23271  * atomicity of device memory accesses. The recommended practice for writing
23272  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23273  * alt_write_word() functions.
23274  *
23275  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX65.
23276  */
23277 struct ALT_SYSMGR_PINMUX_GPLMUX65_s
23278 {
23279  uint32_t sel : 1; /* GPIO/Loan IO65Input Mux Selection Field */
23280  uint32_t : 31; /* *UNDEFINED* */
23281 };
23282 
23283 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX65. */
23284 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX65_s ALT_SYSMGR_PINMUX_GPLMUX65_t;
23285 #endif /* __ASSEMBLY__ */
23286 
23287 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX65 register from the beginning of the component. */
23288 #define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8
23289 
23290 /*
23291  * Register : GPIO/LoanIO 66 Output/Output Enable Mux Selection Register - GPLMUX66
23292  *
23293  * Selection between GPIO and LoanIO output and output enable for GPIO66 and
23294  * LoanIO66. These signals drive the Pin Mux. The Pin Mux must be configured to use
23295  * GPIO/LoanIO in addition to these settings
23296  *
23297  * Only reset by a cold reset (ignores warm reset).
23298  *
23299  * NOTE: These registers should not be modified after IO configuration.There is no
23300  * support for dynamically changing the Pin Mux selections.
23301  *
23302  * Register Layout
23303  *
23304  * Bits | Access | Reset | Description
23305  * :-------|:-------|:------|:----------------------------------------
23306  * [0] | RW | 0x0 | GPIO/Loan IO66Input Mux Selection Field
23307  * [31:1] | ??? | 0x0 | *UNDEFINED*
23308  *
23309  */
23310 /*
23311  * Field : GPIO/Loan IO66Input Mux Selection Field - sel
23312  *
23313  * Select source for GPIO/LoanIO 66.
23314  *
23315  * 0 : LoanIO 66 controls GPIO/LOANIO[66] output and output enable signals.
23316  *
23317  * 1 : GPIO 66 controls GPIO/LOANI[66] output and output enable signals.
23318  *
23319  * Field Access Macros:
23320  *
23321  */
23322 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23323 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0
23324 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23325 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0
23326 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23327 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1
23328 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */
23329 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001
23330 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value. */
23331 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe
23332 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field. */
23333 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0
23334 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX66_SEL field value from a register. */
23335 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
23336 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX66_SEL register field value suitable for setting the register. */
23337 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
23338 
23339 #ifndef __ASSEMBLY__
23340 /*
23341  * WARNING: The C register and register group struct declarations are provided for
23342  * convenience and illustrative purposes. They should, however, be used with
23343  * caution as the C language standard provides no guarantees about the alignment or
23344  * atomicity of device memory accesses. The recommended practice for writing
23345  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23346  * alt_write_word() functions.
23347  *
23348  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX66.
23349  */
23350 struct ALT_SYSMGR_PINMUX_GPLMUX66_s
23351 {
23352  uint32_t sel : 1; /* GPIO/Loan IO66Input Mux Selection Field */
23353  uint32_t : 31; /* *UNDEFINED* */
23354 };
23355 
23356 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX66. */
23357 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX66_s ALT_SYSMGR_PINMUX_GPLMUX66_t;
23358 #endif /* __ASSEMBLY__ */
23359 
23360 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX66 register from the beginning of the component. */
23361 #define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc
23362 
23363 /*
23364  * Register : GPIO/LoanIO 67 Output/Output Enable Mux Selection Register - GPLMUX67
23365  *
23366  * Selection between GPIO and LoanIO output and output enable for GPIO67 and
23367  * LoanIO67. These signals drive the Pin Mux. The Pin Mux must be configured to use
23368  * GPIO/LoanIO in addition to these settings
23369  *
23370  * Only reset by a cold reset (ignores warm reset).
23371  *
23372  * NOTE: These registers should not be modified after IO configuration.There is no
23373  * support for dynamically changing the Pin Mux selections.
23374  *
23375  * Register Layout
23376  *
23377  * Bits | Access | Reset | Description
23378  * :-------|:-------|:------|:----------------------------------------
23379  * [0] | RW | 0x0 | GPIO/Loan IO67Input Mux Selection Field
23380  * [31:1] | ??? | 0x0 | *UNDEFINED*
23381  *
23382  */
23383 /*
23384  * Field : GPIO/Loan IO67Input Mux Selection Field - sel
23385  *
23386  * Select source for GPIO/LoanIO 67.
23387  *
23388  * 0 : LoanIO 67 controls GPIO/LOANIO[67] output and output enable signals.
23389  *
23390  * 1 : GPIO 67 controls GPIO/LOANI[67] output and output enable signals.
23391  *
23392  * Field Access Macros:
23393  *
23394  */
23395 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23396 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0
23397 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23398 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0
23399 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23400 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1
23401 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */
23402 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001
23403 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value. */
23404 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe
23405 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field. */
23406 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0
23407 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX67_SEL field value from a register. */
23408 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
23409 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX67_SEL register field value suitable for setting the register. */
23410 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
23411 
23412 #ifndef __ASSEMBLY__
23413 /*
23414  * WARNING: The C register and register group struct declarations are provided for
23415  * convenience and illustrative purposes. They should, however, be used with
23416  * caution as the C language standard provides no guarantees about the alignment or
23417  * atomicity of device memory accesses. The recommended practice for writing
23418  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23419  * alt_write_word() functions.
23420  *
23421  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX67.
23422  */
23423 struct ALT_SYSMGR_PINMUX_GPLMUX67_s
23424 {
23425  uint32_t sel : 1; /* GPIO/Loan IO67Input Mux Selection Field */
23426  uint32_t : 31; /* *UNDEFINED* */
23427 };
23428 
23429 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX67. */
23430 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX67_s ALT_SYSMGR_PINMUX_GPLMUX67_t;
23431 #endif /* __ASSEMBLY__ */
23432 
23433 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX67 register from the beginning of the component. */
23434 #define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0
23435 
23436 /*
23437  * Register : GPIO/LoanIO 68 Output/Output Enable Mux Selection Register - GPLMUX68
23438  *
23439  * Selection between GPIO and LoanIO output and output enable for GPIO68 and
23440  * LoanIO68. These signals drive the Pin Mux. The Pin Mux must be configured to use
23441  * GPIO/LoanIO in addition to these settings
23442  *
23443  * Only reset by a cold reset (ignores warm reset).
23444  *
23445  * NOTE: These registers should not be modified after IO configuration.There is no
23446  * support for dynamically changing the Pin Mux selections.
23447  *
23448  * Register Layout
23449  *
23450  * Bits | Access | Reset | Description
23451  * :-------|:-------|:------|:----------------------------------------
23452  * [0] | RW | 0x0 | GPIO/Loan IO68Input Mux Selection Field
23453  * [31:1] | ??? | 0x0 | *UNDEFINED*
23454  *
23455  */
23456 /*
23457  * Field : GPIO/Loan IO68Input Mux Selection Field - sel
23458  *
23459  * Select source for GPIO/LoanIO 68.
23460  *
23461  * 0 : LoanIO 68 controls GPIO/LOANIO[68] output and output enable signals.
23462  *
23463  * 1 : GPIO 68 controls GPIO/LOANI[68] output and output enable signals.
23464  *
23465  * Field Access Macros:
23466  *
23467  */
23468 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23469 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0
23470 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23471 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0
23472 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23473 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1
23474 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */
23475 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001
23476 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value. */
23477 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe
23478 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field. */
23479 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0
23480 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX68_SEL field value from a register. */
23481 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
23482 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX68_SEL register field value suitable for setting the register. */
23483 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
23484 
23485 #ifndef __ASSEMBLY__
23486 /*
23487  * WARNING: The C register and register group struct declarations are provided for
23488  * convenience and illustrative purposes. They should, however, be used with
23489  * caution as the C language standard provides no guarantees about the alignment or
23490  * atomicity of device memory accesses. The recommended practice for writing
23491  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23492  * alt_write_word() functions.
23493  *
23494  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX68.
23495  */
23496 struct ALT_SYSMGR_PINMUX_GPLMUX68_s
23497 {
23498  uint32_t sel : 1; /* GPIO/Loan IO68Input Mux Selection Field */
23499  uint32_t : 31; /* *UNDEFINED* */
23500 };
23501 
23502 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX68. */
23503 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX68_s ALT_SYSMGR_PINMUX_GPLMUX68_t;
23504 #endif /* __ASSEMBLY__ */
23505 
23506 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX68 register from the beginning of the component. */
23507 #define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4
23508 
23509 /*
23510  * Register : GPIO/LoanIO 69 Output/Output Enable Mux Selection Register - GPLMUX69
23511  *
23512  * Selection between GPIO and LoanIO output and output enable for GPIO69 and
23513  * LoanIO69. These signals drive the Pin Mux. The Pin Mux must be configured to use
23514  * GPIO/LoanIO in addition to these settings
23515  *
23516  * Only reset by a cold reset (ignores warm reset).
23517  *
23518  * NOTE: These registers should not be modified after IO configuration.There is no
23519  * support for dynamically changing the Pin Mux selections.
23520  *
23521  * Register Layout
23522  *
23523  * Bits | Access | Reset | Description
23524  * :-------|:-------|:------|:----------------------------------------
23525  * [0] | RW | 0x0 | GPIO/Loan IO69Input Mux Selection Field
23526  * [31:1] | ??? | 0x0 | *UNDEFINED*
23527  *
23528  */
23529 /*
23530  * Field : GPIO/Loan IO69Input Mux Selection Field - sel
23531  *
23532  * Select source for GPIO/LoanIO 69.
23533  *
23534  * 0 : LoanIO 69 controls GPIO/LOANIO[69] output and output enable signals.
23535  *
23536  * 1 : GPIO 69 controls GPIO/LOANI[69] output and output enable signals.
23537  *
23538  * Field Access Macros:
23539  *
23540  */
23541 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23542 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0
23543 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23544 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0
23545 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23546 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1
23547 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */
23548 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001
23549 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value. */
23550 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe
23551 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field. */
23552 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0
23553 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX69_SEL field value from a register. */
23554 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
23555 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX69_SEL register field value suitable for setting the register. */
23556 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
23557 
23558 #ifndef __ASSEMBLY__
23559 /*
23560  * WARNING: The C register and register group struct declarations are provided for
23561  * convenience and illustrative purposes. They should, however, be used with
23562  * caution as the C language standard provides no guarantees about the alignment or
23563  * atomicity of device memory accesses. The recommended practice for writing
23564  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23565  * alt_write_word() functions.
23566  *
23567  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX69.
23568  */
23569 struct ALT_SYSMGR_PINMUX_GPLMUX69_s
23570 {
23571  uint32_t sel : 1; /* GPIO/Loan IO69Input Mux Selection Field */
23572  uint32_t : 31; /* *UNDEFINED* */
23573 };
23574 
23575 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX69. */
23576 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX69_s ALT_SYSMGR_PINMUX_GPLMUX69_t;
23577 #endif /* __ASSEMBLY__ */
23578 
23579 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX69 register from the beginning of the component. */
23580 #define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8
23581 
23582 /*
23583  * Register : GPIO/LoanIO 70 Output/Output Enable Mux Selection Register - GPLMUX70
23584  *
23585  * Selection between GPIO and LoanIO output and output enable for GPIO70 and
23586  * LoanIO70. These signals drive the Pin Mux. The Pin Mux must be configured to use
23587  * GPIO/LoanIO in addition to these settings
23588  *
23589  * Only reset by a cold reset (ignores warm reset).
23590  *
23591  * NOTE: These registers should not be modified after IO configuration.There is no
23592  * support for dynamically changing the Pin Mux selections.
23593  *
23594  * Register Layout
23595  *
23596  * Bits | Access | Reset | Description
23597  * :-------|:-------|:------|:----------------------------------------
23598  * [0] | RW | 0x0 | GPIO/Loan IO70Input Mux Selection Field
23599  * [31:1] | ??? | 0x0 | *UNDEFINED*
23600  *
23601  */
23602 /*
23603  * Field : GPIO/Loan IO70Input Mux Selection Field - sel
23604  *
23605  * Select source for GPIO/LoanIO 70.
23606  *
23607  * 0 : LoanIO 70 controls GPIO/LOANIO[70] output and output enable signals.
23608  *
23609  * 1 : GPIO 70 controls GPIO/LOANI[70] output and output enable signals.
23610  *
23611  * Field Access Macros:
23612  *
23613  */
23614 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23615 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0
23616 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23617 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0
23618 /* The width in bits of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23619 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1
23620 /* The mask used to set the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */
23621 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001
23622 /* The mask used to clear the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value. */
23623 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe
23624 /* The reset value of the ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field. */
23625 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0
23626 /* Extracts the ALT_SYSMGR_PINMUX_GPLMUX70_SEL field value from a register. */
23627 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
23628 /* Produces a ALT_SYSMGR_PINMUX_GPLMUX70_SEL register field value suitable for setting the register. */
23629 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
23630 
23631 #ifndef __ASSEMBLY__
23632 /*
23633  * WARNING: The C register and register group struct declarations are provided for
23634  * convenience and illustrative purposes. They should, however, be used with
23635  * caution as the C language standard provides no guarantees about the alignment or
23636  * atomicity of device memory accesses. The recommended practice for writing
23637  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23638  * alt_write_word() functions.
23639  *
23640  * The struct declaration for register ALT_SYSMGR_PINMUX_GPLMUX70.
23641  */
23642 struct ALT_SYSMGR_PINMUX_GPLMUX70_s
23643 {
23644  uint32_t sel : 1; /* GPIO/Loan IO70Input Mux Selection Field */
23645  uint32_t : 31; /* *UNDEFINED* */
23646 };
23647 
23648 /* The typedef declaration for register ALT_SYSMGR_PINMUX_GPLMUX70. */
23649 typedef volatile struct ALT_SYSMGR_PINMUX_GPLMUX70_s ALT_SYSMGR_PINMUX_GPLMUX70_t;
23650 #endif /* __ASSEMBLY__ */
23651 
23652 /* The byte offset of the ALT_SYSMGR_PINMUX_GPLMUX70 register from the beginning of the component. */
23653 #define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec
23654 
23655 /*
23656  * Register : Select source for NAND signals (HPS Pins or FPGA Interface) - NANDUSEFPGA
23657  *
23658  * Selection between HPS Pins and FPGA Interface for NAND signals.
23659  *
23660  * Only reset by a cold reset (ignores warm reset).
23661  *
23662  * NOTE: These registers should not be modified after IO configuration.There is no
23663  * support for dynamically changing the Pin Mux selections.
23664  *
23665  * Register Layout
23666  *
23667  * Bits | Access | Reset | Description
23668  * :-------|:-------|:------|:---------------------------
23669  * [0] | RW | 0x0 | Selection for NAND signals
23670  * [31:1] | ??? | 0x0 | *UNDEFINED*
23671  *
23672  */
23673 /*
23674  * Field : Selection for NAND signals - sel
23675  *
23676  * Select connection for NAND.
23677  *
23678  * 0 : NAND uses HPS Pins.
23679  *
23680  * 1 : NAND uses the FPGA Inteface.
23681  *
23682  * Field Access Macros:
23683  *
23684  */
23685 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23686 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0
23687 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23688 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0
23689 /* The width in bits of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23690 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1
23691 /* The mask used to set the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */
23692 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001
23693 /* The mask used to clear the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value. */
23694 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe
23695 /* The reset value of the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field. */
23696 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0
23697 /* Extracts the ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL field value from a register. */
23698 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23699 /* Produces a ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL register field value suitable for setting the register. */
23700 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23701 
23702 #ifndef __ASSEMBLY__
23703 /*
23704  * WARNING: The C register and register group struct declarations are provided for
23705  * convenience and illustrative purposes. They should, however, be used with
23706  * caution as the C language standard provides no guarantees about the alignment or
23707  * atomicity of device memory accesses. The recommended practice for writing
23708  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23709  * alt_write_word() functions.
23710  *
23711  * The struct declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA.
23712  */
23713 struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s
23714 {
23715  uint32_t sel : 1; /* Selection for NAND signals */
23716  uint32_t : 31; /* *UNDEFINED* */
23717 };
23718 
23719 /* The typedef declaration for register ALT_SYSMGR_PINMUX_NANDUSEFPGA. */
23720 typedef volatile struct ALT_SYSMGR_PINMUX_NANDUSEFPGA_s ALT_SYSMGR_PINMUX_NANDUSEFPGA_t;
23721 #endif /* __ASSEMBLY__ */
23722 
23723 /* The byte offset of the ALT_SYSMGR_PINMUX_NANDUSEFPGA register from the beginning of the component. */
23724 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0
23725 
23726 /*
23727  * Register : Select source for RGMII1 signals (HPS Pins or FPGA Interface) - RGMII1USEFPGA
23728  *
23729  * Selection between HPS Pins and FPGA Interface for RGMII1 signals.
23730  *
23731  * Only reset by a cold reset (ignores warm reset).
23732  *
23733  * NOTE: These registers should not be modified after IO configuration.There is no
23734  * support for dynamically changing the Pin Mux selections.
23735  *
23736  * Register Layout
23737  *
23738  * Bits | Access | Reset | Description
23739  * :-------|:-------|:------|:-----------------------------
23740  * [0] | RW | 0x0 | Selection for RGMII1 signals
23741  * [31:1] | ??? | 0x0 | *UNDEFINED*
23742  *
23743  */
23744 /*
23745  * Field : Selection for RGMII1 signals - sel
23746  *
23747  * Select connection for RGMII1.
23748  *
23749  * 0 : RGMII1 uses HPS Pins.
23750  *
23751  * 1 : RGMII1 uses the FPGA Inteface.
23752  *
23753  * Field Access Macros:
23754  *
23755  */
23756 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23757 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0
23758 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23759 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0
23760 /* The width in bits of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23761 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1
23762 /* The mask used to set the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */
23763 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001
23764 /* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value. */
23765 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe
23766 /* The reset value of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field. */
23767 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0
23768 /* Extracts the ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL field value from a register. */
23769 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23770 /* Produces a ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL register field value suitable for setting the register. */
23771 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23772 
23773 #ifndef __ASSEMBLY__
23774 /*
23775  * WARNING: The C register and register group struct declarations are provided for
23776  * convenience and illustrative purposes. They should, however, be used with
23777  * caution as the C language standard provides no guarantees about the alignment or
23778  * atomicity of device memory accesses. The recommended practice for writing
23779  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23780  * alt_write_word() functions.
23781  *
23782  * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA.
23783  */
23784 struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s
23785 {
23786  uint32_t sel : 1; /* Selection for RGMII1 signals */
23787  uint32_t : 31; /* *UNDEFINED* */
23788 };
23789 
23790 /* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII1USEFPGA. */
23791 typedef volatile struct ALT_SYSMGR_PINMUX_RGMII1USEFPGA_s ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t;
23792 #endif /* __ASSEMBLY__ */
23793 
23794 /* The byte offset of the ALT_SYSMGR_PINMUX_RGMII1USEFPGA register from the beginning of the component. */
23795 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8
23796 
23797 /*
23798  * Register : Select source for I2C0 signals (HPS Pins or FPGA Interface) - I2C0USEFPGA
23799  *
23800  * Selection between HPS Pins and FPGA Interface for I2C0 signals.
23801  *
23802  * Only reset by a cold reset (ignores warm reset).
23803  *
23804  * NOTE: These registers should not be modified after IO configuration.There is no
23805  * support for dynamically changing the Pin Mux selections.
23806  *
23807  * Register Layout
23808  *
23809  * Bits | Access | Reset | Description
23810  * :-------|:-------|:------|:---------------------------
23811  * [0] | RW | 0x0 | Selection for I2C0 signals
23812  * [31:1] | ??? | 0x0 | *UNDEFINED*
23813  *
23814  */
23815 /*
23816  * Field : Selection for I2C0 signals - sel
23817  *
23818  * Select connection for I2C0.
23819  *
23820  * 0 : I2C0 uses HPS Pins.
23821  *
23822  * 1 : I2C0 uses the FPGA Inteface.
23823  *
23824  * Field Access Macros:
23825  *
23826  */
23827 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23828 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0
23829 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23830 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0
23831 /* The width in bits of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23832 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1
23833 /* The mask used to set the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */
23834 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001
23835 /* The mask used to clear the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value. */
23836 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe
23837 /* The reset value of the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field. */
23838 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0
23839 /* Extracts the ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL field value from a register. */
23840 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23841 /* Produces a ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL register field value suitable for setting the register. */
23842 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23843 
23844 #ifndef __ASSEMBLY__
23845 /*
23846  * WARNING: The C register and register group struct declarations are provided for
23847  * convenience and illustrative purposes. They should, however, be used with
23848  * caution as the C language standard provides no guarantees about the alignment or
23849  * atomicity of device memory accesses. The recommended practice for writing
23850  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23851  * alt_write_word() functions.
23852  *
23853  * The struct declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA.
23854  */
23855 struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s
23856 {
23857  uint32_t sel : 1; /* Selection for I2C0 signals */
23858  uint32_t : 31; /* *UNDEFINED* */
23859 };
23860 
23861 /* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C0USEFPGA. */
23862 typedef volatile struct ALT_SYSMGR_PINMUX_I2C0USEFPGA_s ALT_SYSMGR_PINMUX_I2C0USEFPGA_t;
23863 #endif /* __ASSEMBLY__ */
23864 
23865 /* The byte offset of the ALT_SYSMGR_PINMUX_I2C0USEFPGA register from the beginning of the component. */
23866 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304
23867 
23868 /*
23869  * Register : Select source for RGMII0 signals (HPS Pins or FPGA Interface) - RGMII0USEFPGA
23870  *
23871  * Selection between HPS Pins and FPGA Interface for RGMII0 signals.
23872  *
23873  * Only reset by a cold reset (ignores warm reset).
23874  *
23875  * NOTE: These registers should not be modified after IO configuration.There is no
23876  * support for dynamically changing the Pin Mux selections.
23877  *
23878  * Register Layout
23879  *
23880  * Bits | Access | Reset | Description
23881  * :-------|:-------|:------|:-----------------------------
23882  * [0] | RW | 0x0 | Selection for RGMII0 signals
23883  * [31:1] | ??? | 0x0 | *UNDEFINED*
23884  *
23885  */
23886 /*
23887  * Field : Selection for RGMII0 signals - sel
23888  *
23889  * Select connection for RGMII0.
23890  *
23891  * 0 : RGMII0 uses HPS Pins.
23892  *
23893  * 1 : RGMII0 uses the FPGA Inteface.
23894  *
23895  * Field Access Macros:
23896  *
23897  */
23898 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23899 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0
23900 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23901 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0
23902 /* The width in bits of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23903 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1
23904 /* The mask used to set the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */
23905 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001
23906 /* The mask used to clear the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value. */
23907 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe
23908 /* The reset value of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field. */
23909 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0
23910 /* Extracts the ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL field value from a register. */
23911 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23912 /* Produces a ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL register field value suitable for setting the register. */
23913 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23914 
23915 #ifndef __ASSEMBLY__
23916 /*
23917  * WARNING: The C register and register group struct declarations are provided for
23918  * convenience and illustrative purposes. They should, however, be used with
23919  * caution as the C language standard provides no guarantees about the alignment or
23920  * atomicity of device memory accesses. The recommended practice for writing
23921  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23922  * alt_write_word() functions.
23923  *
23924  * The struct declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA.
23925  */
23926 struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s
23927 {
23928  uint32_t sel : 1; /* Selection for RGMII0 signals */
23929  uint32_t : 31; /* *UNDEFINED* */
23930 };
23931 
23932 /* The typedef declaration for register ALT_SYSMGR_PINMUX_RGMII0USEFPGA. */
23933 typedef volatile struct ALT_SYSMGR_PINMUX_RGMII0USEFPGA_s ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t;
23934 #endif /* __ASSEMBLY__ */
23935 
23936 /* The byte offset of the ALT_SYSMGR_PINMUX_RGMII0USEFPGA register from the beginning of the component. */
23937 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314
23938 
23939 /*
23940  * Register : Select source for I2C3 signals (HPS Pins or FPGA Interface) - I2C3USEFPGA
23941  *
23942  * Selection between HPS Pins and FPGA Interface for I2C3 signals.
23943  *
23944  * Only reset by a cold reset (ignores warm reset).
23945  *
23946  * NOTE: These registers should not be modified after IO configuration.There is no
23947  * support for dynamically changing the Pin Mux selections.
23948  *
23949  * Register Layout
23950  *
23951  * Bits | Access | Reset | Description
23952  * :-------|:-------|:------|:---------------------------
23953  * [0] | RW | 0x0 | Selection for I2C3 signals
23954  * [31:1] | ??? | 0x0 | *UNDEFINED*
23955  *
23956  */
23957 /*
23958  * Field : Selection for I2C3 signals - sel
23959  *
23960  * Select connection for I2C3.
23961  *
23962  * 0 : I2C3 uses HPS Pins.
23963  *
23964  * 1 : I2C3 uses the FPGA Inteface.
23965  *
23966  * Field Access Macros:
23967  *
23968  */
23969 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23970 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0
23971 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23972 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0
23973 /* The width in bits of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23974 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1
23975 /* The mask used to set the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */
23976 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001
23977 /* The mask used to clear the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value. */
23978 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe
23979 /* The reset value of the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field. */
23980 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0
23981 /* Extracts the ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL field value from a register. */
23982 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23983 /* Produces a ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL register field value suitable for setting the register. */
23984 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23985 
23986 #ifndef __ASSEMBLY__
23987 /*
23988  * WARNING: The C register and register group struct declarations are provided for
23989  * convenience and illustrative purposes. They should, however, be used with
23990  * caution as the C language standard provides no guarantees about the alignment or
23991  * atomicity of device memory accesses. The recommended practice for writing
23992  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
23993  * alt_write_word() functions.
23994  *
23995  * The struct declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA.
23996  */
23997 struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s
23998 {
23999  uint32_t sel : 1; /* Selection for I2C3 signals */
24000  uint32_t : 31; /* *UNDEFINED* */
24001 };
24002 
24003 /* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C3USEFPGA. */
24004 typedef volatile struct ALT_SYSMGR_PINMUX_I2C3USEFPGA_s ALT_SYSMGR_PINMUX_I2C3USEFPGA_t;
24005 #endif /* __ASSEMBLY__ */
24006 
24007 /* The byte offset of the ALT_SYSMGR_PINMUX_I2C3USEFPGA register from the beginning of the component. */
24008 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324
24009 
24010 /*
24011  * Register : Select source for I2C2 signals (HPS Pins or FPGA Interface) - I2C2USEFPGA
24012  *
24013  * Selection between HPS Pins and FPGA Interface for I2C2 signals.
24014  *
24015  * Only reset by a cold reset (ignores warm reset).
24016  *
24017  * NOTE: These registers should not be modified after IO configuration.There is no
24018  * support for dynamically changing the Pin Mux selections.
24019  *
24020  * Register Layout
24021  *
24022  * Bits | Access | Reset | Description
24023  * :-------|:-------|:------|:---------------------------
24024  * [0] | RW | 0x0 | Selection for I2C2 signals
24025  * [31:1] | ??? | 0x0 | *UNDEFINED*
24026  *
24027  */
24028 /*
24029  * Field : Selection for I2C2 signals - sel
24030  *
24031  * Select connection for I2C2.
24032  *
24033  * 0 : I2C2 uses HPS Pins.
24034  *
24035  * 1 : I2C2 uses the FPGA Inteface.
24036  *
24037  * Field Access Macros:
24038  *
24039  */
24040 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24041 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0
24042 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24043 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0
24044 /* The width in bits of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24045 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1
24046 /* The mask used to set the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */
24047 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001
24048 /* The mask used to clear the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value. */
24049 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe
24050 /* The reset value of the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field. */
24051 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0
24052 /* Extracts the ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL field value from a register. */
24053 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24054 /* Produces a ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL register field value suitable for setting the register. */
24055 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24056 
24057 #ifndef __ASSEMBLY__
24058 /*
24059  * WARNING: The C register and register group struct declarations are provided for
24060  * convenience and illustrative purposes. They should, however, be used with
24061  * caution as the C language standard provides no guarantees about the alignment or
24062  * atomicity of device memory accesses. The recommended practice for writing
24063  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24064  * alt_write_word() functions.
24065  *
24066  * The struct declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA.
24067  */
24068 struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s
24069 {
24070  uint32_t sel : 1; /* Selection for I2C2 signals */
24071  uint32_t : 31; /* *UNDEFINED* */
24072 };
24073 
24074 /* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C2USEFPGA. */
24075 typedef volatile struct ALT_SYSMGR_PINMUX_I2C2USEFPGA_s ALT_SYSMGR_PINMUX_I2C2USEFPGA_t;
24076 #endif /* __ASSEMBLY__ */
24077 
24078 /* The byte offset of the ALT_SYSMGR_PINMUX_I2C2USEFPGA register from the beginning of the component. */
24079 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328
24080 
24081 /*
24082  * Register : Select source for I2C1 signals (HPS Pins or FPGA Interface) - I2C1USEFPGA
24083  *
24084  * Selection between HPS Pins and FPGA Interface for I2C1 signals.
24085  *
24086  * Only reset by a cold reset (ignores warm reset).
24087  *
24088  * NOTE: These registers should not be modified after IO configuration.There is no
24089  * support for dynamically changing the Pin Mux selections.
24090  *
24091  * Register Layout
24092  *
24093  * Bits | Access | Reset | Description
24094  * :-------|:-------|:------|:---------------------------
24095  * [0] | RW | 0x0 | Selection for I2C1 signals
24096  * [31:1] | ??? | 0x0 | *UNDEFINED*
24097  *
24098  */
24099 /*
24100  * Field : Selection for I2C1 signals - sel
24101  *
24102  * Select connection for I2C1.
24103  *
24104  * 0 : I2C1 uses HPS Pins.
24105  *
24106  * 1 : I2C1 uses the FPGA Inteface.
24107  *
24108  * Field Access Macros:
24109  *
24110  */
24111 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24112 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0
24113 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24114 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0
24115 /* The width in bits of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24116 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1
24117 /* The mask used to set the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */
24118 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001
24119 /* The mask used to clear the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value. */
24120 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe
24121 /* The reset value of the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field. */
24122 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0
24123 /* Extracts the ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL field value from a register. */
24124 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24125 /* Produces a ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL register field value suitable for setting the register. */
24126 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24127 
24128 #ifndef __ASSEMBLY__
24129 /*
24130  * WARNING: The C register and register group struct declarations are provided for
24131  * convenience and illustrative purposes. They should, however, be used with
24132  * caution as the C language standard provides no guarantees about the alignment or
24133  * atomicity of device memory accesses. The recommended practice for writing
24134  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24135  * alt_write_word() functions.
24136  *
24137  * The struct declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA.
24138  */
24139 struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s
24140 {
24141  uint32_t sel : 1; /* Selection for I2C1 signals */
24142  uint32_t : 31; /* *UNDEFINED* */
24143 };
24144 
24145 /* The typedef declaration for register ALT_SYSMGR_PINMUX_I2C1USEFPGA. */
24146 typedef volatile struct ALT_SYSMGR_PINMUX_I2C1USEFPGA_s ALT_SYSMGR_PINMUX_I2C1USEFPGA_t;
24147 #endif /* __ASSEMBLY__ */
24148 
24149 /* The byte offset of the ALT_SYSMGR_PINMUX_I2C1USEFPGA register from the beginning of the component. */
24150 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c
24151 
24152 /*
24153  * Register : Select source for SPIM1 signals (HPS Pins or FPGA Interface) - SPIM1USEFPGA
24154  *
24155  * Selection between HPS Pins and FPGA Interface for SPIM1 signals.
24156  *
24157  * Only reset by a cold reset (ignores warm reset).
24158  *
24159  * NOTE: These registers should not be modified after IO configuration.There is no
24160  * support for dynamically changing the Pin Mux selections.
24161  *
24162  * Register Layout
24163  *
24164  * Bits | Access | Reset | Description
24165  * :-------|:-------|:------|:----------------------------
24166  * [0] | RW | 0x0 | Selection for SPIM1 signals
24167  * [31:1] | ??? | 0x0 | *UNDEFINED*
24168  *
24169  */
24170 /*
24171  * Field : Selection for SPIM1 signals - sel
24172  *
24173  * Select connection for SPIM1.
24174  *
24175  * 0 : SPIM1 uses HPS Pins.
24176  *
24177  * 1 : SPIM1 uses the FPGA Inteface.
24178  *
24179  * Field Access Macros:
24180  *
24181  */
24182 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24183 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0
24184 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24185 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0
24186 /* The width in bits of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24187 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1
24188 /* The mask used to set the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */
24189 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001
24190 /* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value. */
24191 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe
24192 /* The reset value of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field. */
24193 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0
24194 /* Extracts the ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL field value from a register. */
24195 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24196 /* Produces a ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL register field value suitable for setting the register. */
24197 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24198 
24199 #ifndef __ASSEMBLY__
24200 /*
24201  * WARNING: The C register and register group struct declarations are provided for
24202  * convenience and illustrative purposes. They should, however, be used with
24203  * caution as the C language standard provides no guarantees about the alignment or
24204  * atomicity of device memory accesses. The recommended practice for writing
24205  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24206  * alt_write_word() functions.
24207  *
24208  * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA.
24209  */
24210 struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s
24211 {
24212  uint32_t sel : 1; /* Selection for SPIM1 signals */
24213  uint32_t : 31; /* *UNDEFINED* */
24214 };
24215 
24216 /* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM1USEFPGA. */
24217 typedef volatile struct ALT_SYSMGR_PINMUX_SPIM1USEFPGA_s ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t;
24218 #endif /* __ASSEMBLY__ */
24219 
24220 /* The byte offset of the ALT_SYSMGR_PINMUX_SPIM1USEFPGA register from the beginning of the component. */
24221 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330
24222 
24223 /*
24224  * Register : Select source for SPIM0 signals (HPS Pins or FPGA Interface) - SPIM0USEFPGA
24225  *
24226  * Selection between HPS Pins and FPGA Interface for SPIM0 signals.
24227  *
24228  * Only reset by a cold reset (ignores warm reset).
24229  *
24230  * NOTE: These registers should not be modified after IO configuration.There is no
24231  * support for dynamically changing the Pin Mux selections.
24232  *
24233  * Register Layout
24234  *
24235  * Bits | Access | Reset | Description
24236  * :-------|:-------|:------|:----------------------------
24237  * [0] | RW | 0x0 | Selection for SPIM0 signals
24238  * [31:1] | ??? | 0x0 | *UNDEFINED*
24239  *
24240  */
24241 /*
24242  * Field : Selection for SPIM0 signals - sel
24243  *
24244  * Select connection for SPIM0.
24245  *
24246  * 0 : SPIM0 uses HPS Pins.
24247  *
24248  * 1 : SPIM0 uses the FPGA Inteface.
24249  *
24250  * Field Access Macros:
24251  *
24252  */
24253 /* The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24254 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0
24255 /* The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24256 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0
24257 /* The width in bits of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24258 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1
24259 /* The mask used to set the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */
24260 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001
24261 /* The mask used to clear the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value. */
24262 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe
24263 /* The reset value of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field. */
24264 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0
24265 /* Extracts the ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL field value from a register. */
24266 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24267 /* Produces a ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL register field value suitable for setting the register. */
24268 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24269 
24270 #ifndef __ASSEMBLY__
24271 /*
24272  * WARNING: The C register and register group struct declarations are provided for
24273  * convenience and illustrative purposes. They should, however, be used with
24274  * caution as the C language standard provides no guarantees about the alignment or
24275  * atomicity of device memory accesses. The recommended practice for writing
24276  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24277  * alt_write_word() functions.
24278  *
24279  * The struct declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA.
24280  */
24281 struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s
24282 {
24283  uint32_t sel : 1; /* Selection for SPIM0 signals */
24284  uint32_t : 31; /* *UNDEFINED* */
24285 };
24286 
24287 /* The typedef declaration for register ALT_SYSMGR_PINMUX_SPIM0USEFPGA. */
24288 typedef volatile struct ALT_SYSMGR_PINMUX_SPIM0USEFPGA_s ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t;
24289 #endif /* __ASSEMBLY__ */
24290 
24291 /* The byte offset of the ALT_SYSMGR_PINMUX_SPIM0USEFPGA register from the beginning of the component. */
24292 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338
24293 
24294 #ifndef __ASSEMBLY__
24295 /*
24296  * WARNING: The C register and register group struct declarations are provided for
24297  * convenience and illustrative purposes. They should, however, be used with
24298  * caution as the C language standard provides no guarantees about the alignment or
24299  * atomicity of device memory accesses. The recommended practice for writing
24300  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24301  * alt_write_word() functions.
24302  *
24303  * The struct declaration for register group ALT_SYSMGR_PINMUX.
24304  */
24305 struct ALT_SYSMGR_PINMUX_s
24306 {
24307  ALT_SYSMGR_PINMUX_EMACIO0_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */
24308  ALT_SYSMGR_PINMUX_EMACIO1_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */
24309  ALT_SYSMGR_PINMUX_EMACIO2_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */
24310  ALT_SYSMGR_PINMUX_EMACIO3_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */
24311  ALT_SYSMGR_PINMUX_EMACIO4_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */
24312  ALT_SYSMGR_PINMUX_EMACIO5_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */
24313  ALT_SYSMGR_PINMUX_EMACIO6_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */
24314  ALT_SYSMGR_PINMUX_EMACIO7_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */
24315  ALT_SYSMGR_PINMUX_EMACIO8_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */
24316  ALT_SYSMGR_PINMUX_EMACIO9_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */
24317  ALT_SYSMGR_PINMUX_EMACIO10_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */
24318  ALT_SYSMGR_PINMUX_EMACIO11_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */
24319  ALT_SYSMGR_PINMUX_EMACIO12_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */
24320  ALT_SYSMGR_PINMUX_EMACIO13_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */
24321  ALT_SYSMGR_PINMUX_EMACIO14_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */
24322  ALT_SYSMGR_PINMUX_EMACIO15_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */
24323  ALT_SYSMGR_PINMUX_EMACIO16_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */
24324  ALT_SYSMGR_PINMUX_EMACIO17_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */
24325  ALT_SYSMGR_PINMUX_EMACIO18_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */
24326  ALT_SYSMGR_PINMUX_EMACIO19_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */
24327  ALT_SYSMGR_PINMUX_FLSHIO0_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */
24328  ALT_SYSMGR_PINMUX_FLSHIO1_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */
24329  ALT_SYSMGR_PINMUX_FLSHIO2_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */
24330  ALT_SYSMGR_PINMUX_FLSHIO3_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */
24331  ALT_SYSMGR_PINMUX_FLSHIO4_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */
24332  ALT_SYSMGR_PINMUX_FLSHIO5_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */
24333  ALT_SYSMGR_PINMUX_FLSHIO6_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */
24334  ALT_SYSMGR_PINMUX_FLSHIO7_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */
24335  ALT_SYSMGR_PINMUX_FLSHIO8_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */
24336  ALT_SYSMGR_PINMUX_FLSHIO9_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */
24337  ALT_SYSMGR_PINMUX_FLSHIO10_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */
24338  ALT_SYSMGR_PINMUX_FLSHIO11_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */
24339  ALT_SYSMGR_PINMUX_GENERALIO0_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */
24340  ALT_SYSMGR_PINMUX_GENERALIO1_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */
24341  ALT_SYSMGR_PINMUX_GENERALIO2_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */
24342  ALT_SYSMGR_PINMUX_GENERALIO3_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */
24343  ALT_SYSMGR_PINMUX_GENERALIO4_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */
24344  ALT_SYSMGR_PINMUX_GENERALIO5_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */
24345  ALT_SYSMGR_PINMUX_GENERALIO6_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */
24346  ALT_SYSMGR_PINMUX_GENERALIO7_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */
24347  ALT_SYSMGR_PINMUX_GENERALIO8_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */
24348  ALT_SYSMGR_PINMUX_GENERALIO9_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */
24349  ALT_SYSMGR_PINMUX_GENERALIO10_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */
24350  ALT_SYSMGR_PINMUX_GENERALIO11_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */
24351  ALT_SYSMGR_PINMUX_GENERALIO12_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */
24352  ALT_SYSMGR_PINMUX_GENERALIO13_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */
24353  ALT_SYSMGR_PINMUX_GENERALIO14_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */
24354  ALT_SYSMGR_PINMUX_GENERALIO15_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */
24355  ALT_SYSMGR_PINMUX_GENERALIO16_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */
24356  ALT_SYSMGR_PINMUX_GENERALIO17_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */
24357  ALT_SYSMGR_PINMUX_GENERALIO18_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */
24358  ALT_SYSMGR_PINMUX_GENERALIO19_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */
24359  ALT_SYSMGR_PINMUX_GENERALIO20_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */
24360  ALT_SYSMGR_PINMUX_GENERALIO21_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */
24361  ALT_SYSMGR_PINMUX_GENERALIO22_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */
24362  ALT_SYSMGR_PINMUX_GENERALIO23_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */
24363  ALT_SYSMGR_PINMUX_GENERALIO24_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */
24364  ALT_SYSMGR_PINMUX_GENERALIO25_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */
24365  ALT_SYSMGR_PINMUX_GENERALIO26_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */
24366  ALT_SYSMGR_PINMUX_GENERALIO27_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */
24367  ALT_SYSMGR_PINMUX_GENERALIO28_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */
24368  ALT_SYSMGR_PINMUX_GENERALIO29_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */
24369  ALT_SYSMGR_PINMUX_GENERALIO30_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */
24370  ALT_SYSMGR_PINMUX_GENERALIO31_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */
24371  ALT_SYSMGR_PINMUX_MIXED1IO0_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */
24372  ALT_SYSMGR_PINMUX_MIXED1IO1_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */
24373  ALT_SYSMGR_PINMUX_MIXED1IO2_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */
24374  ALT_SYSMGR_PINMUX_MIXED1IO3_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */
24375  ALT_SYSMGR_PINMUX_MIXED1IO4_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */
24376  ALT_SYSMGR_PINMUX_MIXED1IO5_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */
24377  ALT_SYSMGR_PINMUX_MIXED1IO6_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */
24378  ALT_SYSMGR_PINMUX_MIXED1IO7_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */
24379  ALT_SYSMGR_PINMUX_MIXED1IO8_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */
24380  ALT_SYSMGR_PINMUX_MIXED1IO9_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */
24381  ALT_SYSMGR_PINMUX_MIXED1IO10_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */
24382  ALT_SYSMGR_PINMUX_MIXED1IO11_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */
24383  ALT_SYSMGR_PINMUX_MIXED1IO12_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */
24384  ALT_SYSMGR_PINMUX_MIXED1IO13_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */
24385  ALT_SYSMGR_PINMUX_MIXED1IO14_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */
24386  ALT_SYSMGR_PINMUX_MIXED1IO15_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */
24387  ALT_SYSMGR_PINMUX_MIXED1IO16_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */
24388  ALT_SYSMGR_PINMUX_MIXED1IO17_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */
24389  ALT_SYSMGR_PINMUX_MIXED1IO18_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */
24390  ALT_SYSMGR_PINMUX_MIXED1IO19_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */
24391  ALT_SYSMGR_PINMUX_MIXED1IO20_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */
24392  ALT_SYSMGR_PINMUX_MIXED1IO21_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */
24393  ALT_SYSMGR_PINMUX_MIXED2IO0_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */
24394  ALT_SYSMGR_PINMUX_MIXED2IO1_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */
24395  ALT_SYSMGR_PINMUX_MIXED2IO2_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */
24396  ALT_SYSMGR_PINMUX_MIXED2IO3_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */
24397  ALT_SYSMGR_PINMUX_MIXED2IO4_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */
24398  ALT_SYSMGR_PINMUX_MIXED2IO5_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */
24399  ALT_SYSMGR_PINMUX_MIXED2IO6_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */
24400  ALT_SYSMGR_PINMUX_MIXED2IO7_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */
24401  ALT_SYSMGR_PINMUX_GPLINMUX48_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */
24402  ALT_SYSMGR_PINMUX_GPLINMUX49_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */
24403  ALT_SYSMGR_PINMUX_GPLINMUX50_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */
24404  ALT_SYSMGR_PINMUX_GPLINMUX51_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */
24405  ALT_SYSMGR_PINMUX_GPLINMUX52_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */
24406  ALT_SYSMGR_PINMUX_GPLINMUX53_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */
24407  ALT_SYSMGR_PINMUX_GPLINMUX54_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */
24408  ALT_SYSMGR_PINMUX_GPLINMUX55_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */
24409  ALT_SYSMGR_PINMUX_GPLINMUX56_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */
24410  ALT_SYSMGR_PINMUX_GPLINMUX57_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */
24411  ALT_SYSMGR_PINMUX_GPLINMUX58_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */
24412  ALT_SYSMGR_PINMUX_GPLINMUX59_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */
24413  ALT_SYSMGR_PINMUX_GPLINMUX60_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */
24414  ALT_SYSMGR_PINMUX_GPLINMUX61_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */
24415  ALT_SYSMGR_PINMUX_GPLINMUX62_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */
24416  ALT_SYSMGR_PINMUX_GPLINMUX63_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */
24417  ALT_SYSMGR_PINMUX_GPLINMUX64_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */
24418  ALT_SYSMGR_PINMUX_GPLINMUX65_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */
24419  ALT_SYSMGR_PINMUX_GPLINMUX66_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */
24420  ALT_SYSMGR_PINMUX_GPLINMUX67_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */
24421  ALT_SYSMGR_PINMUX_GPLINMUX68_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */
24422  ALT_SYSMGR_PINMUX_GPLINMUX69_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */
24423  ALT_SYSMGR_PINMUX_GPLINMUX70_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */
24424  ALT_SYSMGR_PINMUX_GPLMUX0_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */
24425  ALT_SYSMGR_PINMUX_GPLMUX1_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */
24426  ALT_SYSMGR_PINMUX_GPLMUX2_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */
24427  ALT_SYSMGR_PINMUX_GPLMUX3_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */
24428  ALT_SYSMGR_PINMUX_GPLMUX4_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */
24429  ALT_SYSMGR_PINMUX_GPLMUX5_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */
24430  ALT_SYSMGR_PINMUX_GPLMUX6_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */
24431  ALT_SYSMGR_PINMUX_GPLMUX7_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */
24432  ALT_SYSMGR_PINMUX_GPLMUX8_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */
24433  ALT_SYSMGR_PINMUX_GPLMUX9_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */
24434  ALT_SYSMGR_PINMUX_GPLMUX10_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */
24435  ALT_SYSMGR_PINMUX_GPLMUX11_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */
24436  ALT_SYSMGR_PINMUX_GPLMUX12_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */
24437  ALT_SYSMGR_PINMUX_GPLMUX13_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */
24438  ALT_SYSMGR_PINMUX_GPLMUX14_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */
24439  ALT_SYSMGR_PINMUX_GPLMUX15_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */
24440  ALT_SYSMGR_PINMUX_GPLMUX16_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */
24441  ALT_SYSMGR_PINMUX_GPLMUX17_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */
24442  ALT_SYSMGR_PINMUX_GPLMUX18_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */
24443  ALT_SYSMGR_PINMUX_GPLMUX19_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */
24444  ALT_SYSMGR_PINMUX_GPLMUX20_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */
24445  ALT_SYSMGR_PINMUX_GPLMUX21_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */
24446  ALT_SYSMGR_PINMUX_GPLMUX22_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */
24447  ALT_SYSMGR_PINMUX_GPLMUX23_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */
24448  ALT_SYSMGR_PINMUX_GPLMUX24_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */
24449  ALT_SYSMGR_PINMUX_GPLMUX25_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */
24450  ALT_SYSMGR_PINMUX_GPLMUX26_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */
24451  ALT_SYSMGR_PINMUX_GPLMUX27_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */
24452  ALT_SYSMGR_PINMUX_GPLMUX28_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */
24453  ALT_SYSMGR_PINMUX_GPLMUX29_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */
24454  ALT_SYSMGR_PINMUX_GPLMUX30_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */
24455  ALT_SYSMGR_PINMUX_GPLMUX31_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */
24456  ALT_SYSMGR_PINMUX_GPLMUX32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */
24457  ALT_SYSMGR_PINMUX_GPLMUX33_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */
24458  ALT_SYSMGR_PINMUX_GPLMUX34_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */
24459  ALT_SYSMGR_PINMUX_GPLMUX35_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */
24460  ALT_SYSMGR_PINMUX_GPLMUX36_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */
24461  ALT_SYSMGR_PINMUX_GPLMUX37_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */
24462  ALT_SYSMGR_PINMUX_GPLMUX38_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */
24463  ALT_SYSMGR_PINMUX_GPLMUX39_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */
24464  ALT_SYSMGR_PINMUX_GPLMUX40_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */
24465  ALT_SYSMGR_PINMUX_GPLMUX41_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */
24466  ALT_SYSMGR_PINMUX_GPLMUX42_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */
24467  ALT_SYSMGR_PINMUX_GPLMUX43_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */
24468  ALT_SYSMGR_PINMUX_GPLMUX44_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */
24469  ALT_SYSMGR_PINMUX_GPLMUX45_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */
24470  ALT_SYSMGR_PINMUX_GPLMUX46_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */
24471  ALT_SYSMGR_PINMUX_GPLMUX47_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */
24472  ALT_SYSMGR_PINMUX_GPLMUX48_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */
24473  ALT_SYSMGR_PINMUX_GPLMUX49_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */
24474  ALT_SYSMGR_PINMUX_GPLMUX50_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */
24475  ALT_SYSMGR_PINMUX_GPLMUX51_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */
24476  ALT_SYSMGR_PINMUX_GPLMUX52_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */
24477  ALT_SYSMGR_PINMUX_GPLMUX53_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */
24478  ALT_SYSMGR_PINMUX_GPLMUX54_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */
24479  ALT_SYSMGR_PINMUX_GPLMUX55_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */
24480  ALT_SYSMGR_PINMUX_GPLMUX56_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */
24481  ALT_SYSMGR_PINMUX_GPLMUX57_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */
24482  ALT_SYSMGR_PINMUX_GPLMUX58_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */
24483  ALT_SYSMGR_PINMUX_GPLMUX59_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */
24484  ALT_SYSMGR_PINMUX_GPLMUX60_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */
24485  ALT_SYSMGR_PINMUX_GPLMUX61_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */
24486  ALT_SYSMGR_PINMUX_GPLMUX62_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */
24487  ALT_SYSMGR_PINMUX_GPLMUX63_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */
24488  ALT_SYSMGR_PINMUX_GPLMUX64_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */
24489  ALT_SYSMGR_PINMUX_GPLMUX65_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */
24490  ALT_SYSMGR_PINMUX_GPLMUX66_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */
24491  ALT_SYSMGR_PINMUX_GPLMUX67_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */
24492  ALT_SYSMGR_PINMUX_GPLMUX68_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */
24493  ALT_SYSMGR_PINMUX_GPLMUX69_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */
24494  ALT_SYSMGR_PINMUX_GPLMUX70_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */
24495  ALT_SYSMGR_PINMUX_NANDUSEFPGA_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */
24496  volatile uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */
24497  ALT_SYSMGR_PINMUX_RGMII1USEFPGA_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */
24498  volatile uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */
24499  ALT_SYSMGR_PINMUX_I2C0USEFPGA_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */
24500  volatile uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */
24501  ALT_SYSMGR_PINMUX_RGMII0USEFPGA_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */
24502  volatile uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */
24503  ALT_SYSMGR_PINMUX_I2C3USEFPGA_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */
24504  ALT_SYSMGR_PINMUX_I2C2USEFPGA_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */
24505  ALT_SYSMGR_PINMUX_I2C1USEFPGA_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */
24506  ALT_SYSMGR_PINMUX_SPIM1USEFPGA_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */
24507  volatile uint32_t _pad_0x334_0x337; /* *UNDEFINED* */
24508  ALT_SYSMGR_PINMUX_SPIM0USEFPGA_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */
24509  volatile uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */
24510 };
24511 
24512 /* The typedef declaration for register group ALT_SYSMGR_PINMUX. */
24513 typedef volatile struct ALT_SYSMGR_PINMUX_s ALT_SYSMGR_PINMUX_t;
24514 /* The struct declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */
24515 struct ALT_SYSMGR_PINMUX_raw_s
24516 {
24517  volatile uint32_t EMACIO0; /* ALT_SYSMGR_PINMUX_EMACIO0 */
24518  volatile uint32_t EMACIO1; /* ALT_SYSMGR_PINMUX_EMACIO1 */
24519  volatile uint32_t EMACIO2; /* ALT_SYSMGR_PINMUX_EMACIO2 */
24520  volatile uint32_t EMACIO3; /* ALT_SYSMGR_PINMUX_EMACIO3 */
24521  volatile uint32_t EMACIO4; /* ALT_SYSMGR_PINMUX_EMACIO4 */
24522  volatile uint32_t EMACIO5; /* ALT_SYSMGR_PINMUX_EMACIO5 */
24523  volatile uint32_t EMACIO6; /* ALT_SYSMGR_PINMUX_EMACIO6 */
24524  volatile uint32_t EMACIO7; /* ALT_SYSMGR_PINMUX_EMACIO7 */
24525  volatile uint32_t EMACIO8; /* ALT_SYSMGR_PINMUX_EMACIO8 */
24526  volatile uint32_t EMACIO9; /* ALT_SYSMGR_PINMUX_EMACIO9 */
24527  volatile uint32_t EMACIO10; /* ALT_SYSMGR_PINMUX_EMACIO10 */
24528  volatile uint32_t EMACIO11; /* ALT_SYSMGR_PINMUX_EMACIO11 */
24529  volatile uint32_t EMACIO12; /* ALT_SYSMGR_PINMUX_EMACIO12 */
24530  volatile uint32_t EMACIO13; /* ALT_SYSMGR_PINMUX_EMACIO13 */
24531  volatile uint32_t EMACIO14; /* ALT_SYSMGR_PINMUX_EMACIO14 */
24532  volatile uint32_t EMACIO15; /* ALT_SYSMGR_PINMUX_EMACIO15 */
24533  volatile uint32_t EMACIO16; /* ALT_SYSMGR_PINMUX_EMACIO16 */
24534  volatile uint32_t EMACIO17; /* ALT_SYSMGR_PINMUX_EMACIO17 */
24535  volatile uint32_t EMACIO18; /* ALT_SYSMGR_PINMUX_EMACIO18 */
24536  volatile uint32_t EMACIO19; /* ALT_SYSMGR_PINMUX_EMACIO19 */
24537  volatile uint32_t FLASHIO0; /* ALT_SYSMGR_PINMUX_FLSHIO0 */
24538  volatile uint32_t FLASHIO1; /* ALT_SYSMGR_PINMUX_FLSHIO1 */
24539  volatile uint32_t FLASHIO2; /* ALT_SYSMGR_PINMUX_FLSHIO2 */
24540  volatile uint32_t FLASHIO3; /* ALT_SYSMGR_PINMUX_FLSHIO3 */
24541  volatile uint32_t FLASHIO4; /* ALT_SYSMGR_PINMUX_FLSHIO4 */
24542  volatile uint32_t FLASHIO5; /* ALT_SYSMGR_PINMUX_FLSHIO5 */
24543  volatile uint32_t FLASHIO6; /* ALT_SYSMGR_PINMUX_FLSHIO6 */
24544  volatile uint32_t FLASHIO7; /* ALT_SYSMGR_PINMUX_FLSHIO7 */
24545  volatile uint32_t FLASHIO8; /* ALT_SYSMGR_PINMUX_FLSHIO8 */
24546  volatile uint32_t FLASHIO9; /* ALT_SYSMGR_PINMUX_FLSHIO9 */
24547  volatile uint32_t FLASHIO10; /* ALT_SYSMGR_PINMUX_FLSHIO10 */
24548  volatile uint32_t FLASHIO11; /* ALT_SYSMGR_PINMUX_FLSHIO11 */
24549  volatile uint32_t GENERALIO0; /* ALT_SYSMGR_PINMUX_GENERALIO0 */
24550  volatile uint32_t GENERALIO1; /* ALT_SYSMGR_PINMUX_GENERALIO1 */
24551  volatile uint32_t GENERALIO2; /* ALT_SYSMGR_PINMUX_GENERALIO2 */
24552  volatile uint32_t GENERALIO3; /* ALT_SYSMGR_PINMUX_GENERALIO3 */
24553  volatile uint32_t GENERALIO4; /* ALT_SYSMGR_PINMUX_GENERALIO4 */
24554  volatile uint32_t GENERALIO5; /* ALT_SYSMGR_PINMUX_GENERALIO5 */
24555  volatile uint32_t GENERALIO6; /* ALT_SYSMGR_PINMUX_GENERALIO6 */
24556  volatile uint32_t GENERALIO7; /* ALT_SYSMGR_PINMUX_GENERALIO7 */
24557  volatile uint32_t GENERALIO8; /* ALT_SYSMGR_PINMUX_GENERALIO8 */
24558  volatile uint32_t GENERALIO9; /* ALT_SYSMGR_PINMUX_GENERALIO9 */
24559  volatile uint32_t GENERALIO10; /* ALT_SYSMGR_PINMUX_GENERALIO10 */
24560  volatile uint32_t GENERALIO11; /* ALT_SYSMGR_PINMUX_GENERALIO11 */
24561  volatile uint32_t GENERALIO12; /* ALT_SYSMGR_PINMUX_GENERALIO12 */
24562  volatile uint32_t GENERALIO13; /* ALT_SYSMGR_PINMUX_GENERALIO13 */
24563  volatile uint32_t GENERALIO14; /* ALT_SYSMGR_PINMUX_GENERALIO14 */
24564  volatile uint32_t GENERALIO15; /* ALT_SYSMGR_PINMUX_GENERALIO15 */
24565  volatile uint32_t GENERALIO16; /* ALT_SYSMGR_PINMUX_GENERALIO16 */
24566  volatile uint32_t GENERALIO17; /* ALT_SYSMGR_PINMUX_GENERALIO17 */
24567  volatile uint32_t GENERALIO18; /* ALT_SYSMGR_PINMUX_GENERALIO18 */
24568  volatile uint32_t GENERALIO19; /* ALT_SYSMGR_PINMUX_GENERALIO19 */
24569  volatile uint32_t GENERALIO20; /* ALT_SYSMGR_PINMUX_GENERALIO20 */
24570  volatile uint32_t GENERALIO21; /* ALT_SYSMGR_PINMUX_GENERALIO21 */
24571  volatile uint32_t GENERALIO22; /* ALT_SYSMGR_PINMUX_GENERALIO22 */
24572  volatile uint32_t GENERALIO23; /* ALT_SYSMGR_PINMUX_GENERALIO23 */
24573  volatile uint32_t GENERALIO24; /* ALT_SYSMGR_PINMUX_GENERALIO24 */
24574  volatile uint32_t GENERALIO25; /* ALT_SYSMGR_PINMUX_GENERALIO25 */
24575  volatile uint32_t GENERALIO26; /* ALT_SYSMGR_PINMUX_GENERALIO26 */
24576  volatile uint32_t GENERALIO27; /* ALT_SYSMGR_PINMUX_GENERALIO27 */
24577  volatile uint32_t GENERALIO28; /* ALT_SYSMGR_PINMUX_GENERALIO28 */
24578  volatile uint32_t GENERALIO29; /* ALT_SYSMGR_PINMUX_GENERALIO29 */
24579  volatile uint32_t GENERALIO30; /* ALT_SYSMGR_PINMUX_GENERALIO30 */
24580  volatile uint32_t GENERALIO31; /* ALT_SYSMGR_PINMUX_GENERALIO31 */
24581  volatile uint32_t MIXED1IO0; /* ALT_SYSMGR_PINMUX_MIXED1IO0 */
24582  volatile uint32_t MIXED1IO1; /* ALT_SYSMGR_PINMUX_MIXED1IO1 */
24583  volatile uint32_t MIXED1IO2; /* ALT_SYSMGR_PINMUX_MIXED1IO2 */
24584  volatile uint32_t MIXED1IO3; /* ALT_SYSMGR_PINMUX_MIXED1IO3 */
24585  volatile uint32_t MIXED1IO4; /* ALT_SYSMGR_PINMUX_MIXED1IO4 */
24586  volatile uint32_t MIXED1IO5; /* ALT_SYSMGR_PINMUX_MIXED1IO5 */
24587  volatile uint32_t MIXED1IO6; /* ALT_SYSMGR_PINMUX_MIXED1IO6 */
24588  volatile uint32_t MIXED1IO7; /* ALT_SYSMGR_PINMUX_MIXED1IO7 */
24589  volatile uint32_t MIXED1IO8; /* ALT_SYSMGR_PINMUX_MIXED1IO8 */
24590  volatile uint32_t MIXED1IO9; /* ALT_SYSMGR_PINMUX_MIXED1IO9 */
24591  volatile uint32_t MIXED1IO10; /* ALT_SYSMGR_PINMUX_MIXED1IO10 */
24592  volatile uint32_t MIXED1IO11; /* ALT_SYSMGR_PINMUX_MIXED1IO11 */
24593  volatile uint32_t MIXED1IO12; /* ALT_SYSMGR_PINMUX_MIXED1IO12 */
24594  volatile uint32_t MIXED1IO13; /* ALT_SYSMGR_PINMUX_MIXED1IO13 */
24595  volatile uint32_t MIXED1IO14; /* ALT_SYSMGR_PINMUX_MIXED1IO14 */
24596  volatile uint32_t MIXED1IO15; /* ALT_SYSMGR_PINMUX_MIXED1IO15 */
24597  volatile uint32_t MIXED1IO16; /* ALT_SYSMGR_PINMUX_MIXED1IO16 */
24598  volatile uint32_t MIXED1IO17; /* ALT_SYSMGR_PINMUX_MIXED1IO17 */
24599  volatile uint32_t MIXED1IO18; /* ALT_SYSMGR_PINMUX_MIXED1IO18 */
24600  volatile uint32_t MIXED1IO19; /* ALT_SYSMGR_PINMUX_MIXED1IO19 */
24601  volatile uint32_t MIXED1IO20; /* ALT_SYSMGR_PINMUX_MIXED1IO20 */
24602  volatile uint32_t MIXED1IO21; /* ALT_SYSMGR_PINMUX_MIXED1IO21 */
24603  volatile uint32_t MIXED2IO0; /* ALT_SYSMGR_PINMUX_MIXED2IO0 */
24604  volatile uint32_t MIXED2IO1; /* ALT_SYSMGR_PINMUX_MIXED2IO1 */
24605  volatile uint32_t MIXED2IO2; /* ALT_SYSMGR_PINMUX_MIXED2IO2 */
24606  volatile uint32_t MIXED2IO3; /* ALT_SYSMGR_PINMUX_MIXED2IO3 */
24607  volatile uint32_t MIXED2IO4; /* ALT_SYSMGR_PINMUX_MIXED2IO4 */
24608  volatile uint32_t MIXED2IO5; /* ALT_SYSMGR_PINMUX_MIXED2IO5 */
24609  volatile uint32_t MIXED2IO6; /* ALT_SYSMGR_PINMUX_MIXED2IO6 */
24610  volatile uint32_t MIXED2IO7; /* ALT_SYSMGR_PINMUX_MIXED2IO7 */
24611  volatile uint32_t GPLINMUX48; /* ALT_SYSMGR_PINMUX_GPLINMUX48 */
24612  volatile uint32_t GPLINMUX49; /* ALT_SYSMGR_PINMUX_GPLINMUX49 */
24613  volatile uint32_t GPLINMUX50; /* ALT_SYSMGR_PINMUX_GPLINMUX50 */
24614  volatile uint32_t GPLINMUX51; /* ALT_SYSMGR_PINMUX_GPLINMUX51 */
24615  volatile uint32_t GPLINMUX52; /* ALT_SYSMGR_PINMUX_GPLINMUX52 */
24616  volatile uint32_t GPLINMUX53; /* ALT_SYSMGR_PINMUX_GPLINMUX53 */
24617  volatile uint32_t GPLINMUX54; /* ALT_SYSMGR_PINMUX_GPLINMUX54 */
24618  volatile uint32_t GPLINMUX55; /* ALT_SYSMGR_PINMUX_GPLINMUX55 */
24619  volatile uint32_t GPLINMUX56; /* ALT_SYSMGR_PINMUX_GPLINMUX56 */
24620  volatile uint32_t GPLINMUX57; /* ALT_SYSMGR_PINMUX_GPLINMUX57 */
24621  volatile uint32_t GPLINMUX58; /* ALT_SYSMGR_PINMUX_GPLINMUX58 */
24622  volatile uint32_t GPLINMUX59; /* ALT_SYSMGR_PINMUX_GPLINMUX59 */
24623  volatile uint32_t GPLINMUX60; /* ALT_SYSMGR_PINMUX_GPLINMUX60 */
24624  volatile uint32_t GPLINMUX61; /* ALT_SYSMGR_PINMUX_GPLINMUX61 */
24625  volatile uint32_t GPLINMUX62; /* ALT_SYSMGR_PINMUX_GPLINMUX62 */
24626  volatile uint32_t GPLINMUX63; /* ALT_SYSMGR_PINMUX_GPLINMUX63 */
24627  volatile uint32_t GPLINMUX64; /* ALT_SYSMGR_PINMUX_GPLINMUX64 */
24628  volatile uint32_t GPLINMUX65; /* ALT_SYSMGR_PINMUX_GPLINMUX65 */
24629  volatile uint32_t GPLINMUX66; /* ALT_SYSMGR_PINMUX_GPLINMUX66 */
24630  volatile uint32_t GPLINMUX67; /* ALT_SYSMGR_PINMUX_GPLINMUX67 */
24631  volatile uint32_t GPLINMUX68; /* ALT_SYSMGR_PINMUX_GPLINMUX68 */
24632  volatile uint32_t GPLINMUX69; /* ALT_SYSMGR_PINMUX_GPLINMUX69 */
24633  volatile uint32_t GPLINMUX70; /* ALT_SYSMGR_PINMUX_GPLINMUX70 */
24634  volatile uint32_t GPLMUX0; /* ALT_SYSMGR_PINMUX_GPLMUX0 */
24635  volatile uint32_t GPLMUX1; /* ALT_SYSMGR_PINMUX_GPLMUX1 */
24636  volatile uint32_t GPLMUX2; /* ALT_SYSMGR_PINMUX_GPLMUX2 */
24637  volatile uint32_t GPLMUX3; /* ALT_SYSMGR_PINMUX_GPLMUX3 */
24638  volatile uint32_t GPLMUX4; /* ALT_SYSMGR_PINMUX_GPLMUX4 */
24639  volatile uint32_t GPLMUX5; /* ALT_SYSMGR_PINMUX_GPLMUX5 */
24640  volatile uint32_t GPLMUX6; /* ALT_SYSMGR_PINMUX_GPLMUX6 */
24641  volatile uint32_t GPLMUX7; /* ALT_SYSMGR_PINMUX_GPLMUX7 */
24642  volatile uint32_t GPLMUX8; /* ALT_SYSMGR_PINMUX_GPLMUX8 */
24643  volatile uint32_t GPLMUX9; /* ALT_SYSMGR_PINMUX_GPLMUX9 */
24644  volatile uint32_t GPLMUX10; /* ALT_SYSMGR_PINMUX_GPLMUX10 */
24645  volatile uint32_t GPLMUX11; /* ALT_SYSMGR_PINMUX_GPLMUX11 */
24646  volatile uint32_t GPLMUX12; /* ALT_SYSMGR_PINMUX_GPLMUX12 */
24647  volatile uint32_t GPLMUX13; /* ALT_SYSMGR_PINMUX_GPLMUX13 */
24648  volatile uint32_t GPLMUX14; /* ALT_SYSMGR_PINMUX_GPLMUX14 */
24649  volatile uint32_t GPLMUX15; /* ALT_SYSMGR_PINMUX_GPLMUX15 */
24650  volatile uint32_t GPLMUX16; /* ALT_SYSMGR_PINMUX_GPLMUX16 */
24651  volatile uint32_t GPLMUX17; /* ALT_SYSMGR_PINMUX_GPLMUX17 */
24652  volatile uint32_t GPLMUX18; /* ALT_SYSMGR_PINMUX_GPLMUX18 */
24653  volatile uint32_t GPLMUX19; /* ALT_SYSMGR_PINMUX_GPLMUX19 */
24654  volatile uint32_t GPLMUX20; /* ALT_SYSMGR_PINMUX_GPLMUX20 */
24655  volatile uint32_t GPLMUX21; /* ALT_SYSMGR_PINMUX_GPLMUX21 */
24656  volatile uint32_t GPLMUX22; /* ALT_SYSMGR_PINMUX_GPLMUX22 */
24657  volatile uint32_t GPLMUX23; /* ALT_SYSMGR_PINMUX_GPLMUX23 */
24658  volatile uint32_t GPLMUX24; /* ALT_SYSMGR_PINMUX_GPLMUX24 */
24659  volatile uint32_t GPLMUX25; /* ALT_SYSMGR_PINMUX_GPLMUX25 */
24660  volatile uint32_t GPLMUX26; /* ALT_SYSMGR_PINMUX_GPLMUX26 */
24661  volatile uint32_t GPLMUX27; /* ALT_SYSMGR_PINMUX_GPLMUX27 */
24662  volatile uint32_t GPLMUX28; /* ALT_SYSMGR_PINMUX_GPLMUX28 */
24663  volatile uint32_t GPLMUX29; /* ALT_SYSMGR_PINMUX_GPLMUX29 */
24664  volatile uint32_t GPLMUX30; /* ALT_SYSMGR_PINMUX_GPLMUX30 */
24665  volatile uint32_t GPLMUX31; /* ALT_SYSMGR_PINMUX_GPLMUX31 */
24666  volatile uint32_t GPLMUX32; /* ALT_SYSMGR_PINMUX_GPLMUX32 */
24667  volatile uint32_t GPLMUX33; /* ALT_SYSMGR_PINMUX_GPLMUX33 */
24668  volatile uint32_t GPLMUX34; /* ALT_SYSMGR_PINMUX_GPLMUX34 */
24669  volatile uint32_t GPLMUX35; /* ALT_SYSMGR_PINMUX_GPLMUX35 */
24670  volatile uint32_t GPLMUX36; /* ALT_SYSMGR_PINMUX_GPLMUX36 */
24671  volatile uint32_t GPLMUX37; /* ALT_SYSMGR_PINMUX_GPLMUX37 */
24672  volatile uint32_t GPLMUX38; /* ALT_SYSMGR_PINMUX_GPLMUX38 */
24673  volatile uint32_t GPLMUX39; /* ALT_SYSMGR_PINMUX_GPLMUX39 */
24674  volatile uint32_t GPLMUX40; /* ALT_SYSMGR_PINMUX_GPLMUX40 */
24675  volatile uint32_t GPLMUX41; /* ALT_SYSMGR_PINMUX_GPLMUX41 */
24676  volatile uint32_t GPLMUX42; /* ALT_SYSMGR_PINMUX_GPLMUX42 */
24677  volatile uint32_t GPLMUX43; /* ALT_SYSMGR_PINMUX_GPLMUX43 */
24678  volatile uint32_t GPLMUX44; /* ALT_SYSMGR_PINMUX_GPLMUX44 */
24679  volatile uint32_t GPLMUX45; /* ALT_SYSMGR_PINMUX_GPLMUX45 */
24680  volatile uint32_t GPLMUX46; /* ALT_SYSMGR_PINMUX_GPLMUX46 */
24681  volatile uint32_t GPLMUX47; /* ALT_SYSMGR_PINMUX_GPLMUX47 */
24682  volatile uint32_t GPLMUX48; /* ALT_SYSMGR_PINMUX_GPLMUX48 */
24683  volatile uint32_t GPLMUX49; /* ALT_SYSMGR_PINMUX_GPLMUX49 */
24684  volatile uint32_t GPLMUX50; /* ALT_SYSMGR_PINMUX_GPLMUX50 */
24685  volatile uint32_t GPLMUX51; /* ALT_SYSMGR_PINMUX_GPLMUX51 */
24686  volatile uint32_t GPLMUX52; /* ALT_SYSMGR_PINMUX_GPLMUX52 */
24687  volatile uint32_t GPLMUX53; /* ALT_SYSMGR_PINMUX_GPLMUX53 */
24688  volatile uint32_t GPLMUX54; /* ALT_SYSMGR_PINMUX_GPLMUX54 */
24689  volatile uint32_t GPLMUX55; /* ALT_SYSMGR_PINMUX_GPLMUX55 */
24690  volatile uint32_t GPLMUX56; /* ALT_SYSMGR_PINMUX_GPLMUX56 */
24691  volatile uint32_t GPLMUX57; /* ALT_SYSMGR_PINMUX_GPLMUX57 */
24692  volatile uint32_t GPLMUX58; /* ALT_SYSMGR_PINMUX_GPLMUX58 */
24693  volatile uint32_t GPLMUX59; /* ALT_SYSMGR_PINMUX_GPLMUX59 */
24694  volatile uint32_t GPLMUX60; /* ALT_SYSMGR_PINMUX_GPLMUX60 */
24695  volatile uint32_t GPLMUX61; /* ALT_SYSMGR_PINMUX_GPLMUX61 */
24696  volatile uint32_t GPLMUX62; /* ALT_SYSMGR_PINMUX_GPLMUX62 */
24697  volatile uint32_t GPLMUX63; /* ALT_SYSMGR_PINMUX_GPLMUX63 */
24698  volatile uint32_t GPLMUX64; /* ALT_SYSMGR_PINMUX_GPLMUX64 */
24699  volatile uint32_t GPLMUX65; /* ALT_SYSMGR_PINMUX_GPLMUX65 */
24700  volatile uint32_t GPLMUX66; /* ALT_SYSMGR_PINMUX_GPLMUX66 */
24701  volatile uint32_t GPLMUX67; /* ALT_SYSMGR_PINMUX_GPLMUX67 */
24702  volatile uint32_t GPLMUX68; /* ALT_SYSMGR_PINMUX_GPLMUX68 */
24703  volatile uint32_t GPLMUX69; /* ALT_SYSMGR_PINMUX_GPLMUX69 */
24704  volatile uint32_t GPLMUX70; /* ALT_SYSMGR_PINMUX_GPLMUX70 */
24705  volatile uint32_t NANDUSEFPGA; /* ALT_SYSMGR_PINMUX_NANDUSEFPGA */
24706  uint32_t _pad_0x2f4_0x2f7; /* *UNDEFINED* */
24707  volatile uint32_t RGMII1USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII1USEFPGA */
24708  uint32_t _pad_0x2fc_0x303[2]; /* *UNDEFINED* */
24709  volatile uint32_t I2C0USEFPGA; /* ALT_SYSMGR_PINMUX_I2C0USEFPGA */
24710  uint32_t _pad_0x308_0x313[3]; /* *UNDEFINED* */
24711  volatile uint32_t RGMII0USEFPGA; /* ALT_SYSMGR_PINMUX_RGMII0USEFPGA */
24712  uint32_t _pad_0x318_0x323[3]; /* *UNDEFINED* */
24713  volatile uint32_t I2C3USEFPGA; /* ALT_SYSMGR_PINMUX_I2C3USEFPGA */
24714  volatile uint32_t I2C2USEFPGA; /* ALT_SYSMGR_PINMUX_I2C2USEFPGA */
24715  volatile uint32_t I2C1USEFPGA; /* ALT_SYSMGR_PINMUX_I2C1USEFPGA */
24716  volatile uint32_t SPIM1USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM1USEFPGA */
24717  uint32_t _pad_0x334_0x337; /* *UNDEFINED* */
24718  volatile uint32_t SPIM0USEFPGA; /* ALT_SYSMGR_PINMUX_SPIM0USEFPGA */
24719  uint32_t _pad_0x33c_0x400[49]; /* *UNDEFINED* */
24720 };
24721 
24722 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR_PINMUX. */
24723 typedef volatile struct ALT_SYSMGR_PINMUX_raw_s ALT_SYSMGR_PINMUX_raw_t;
24724 #endif /* __ASSEMBLY__ */
24725 
24726 
24727 #ifndef __ASSEMBLY__
24728 /*
24729  * WARNING: The C register and register group struct declarations are provided for
24730  * convenience and illustrative purposes. They should, however, be used with
24731  * caution as the C language standard provides no guarantees about the alignment or
24732  * atomicity of device memory accesses. The recommended practice for writing
24733  * hardware drivers is to use the SoCAL access macros and alt_read_word() and
24734  * alt_write_word() functions.
24735  *
24736  * The struct declaration for register group ALT_SYSMGR.
24737  */
24738 struct ALT_SYSMGR_s
24739 {
24740  ALT_SYSMGR_SILICONID1_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
24741  ALT_SYSMGR_SILICONID2_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
24742  volatile uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
24743  ALT_SYSMGR_WDDBG_t wddbg; /* ALT_SYSMGR_WDDBG */
24744  ALT_SYSMGR_BOOT_t bootinfo; /* ALT_SYSMGR_BOOT */
24745  ALT_SYSMGR_HPSINFO_t hpsinfo; /* ALT_SYSMGR_HPSINFO */
24746  ALT_SYSMGR_PARITYINJ_t parityinj; /* ALT_SYSMGR_PARITYINJ */
24747  ALT_SYSMGR_FPGAINTF_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */
24748  ALT_SYSMGR_SCANMGR_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */
24749  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
24750  ALT_SYSMGR_FRZCTL_t frzctrl; /* ALT_SYSMGR_FRZCTL */
24751  ALT_SYSMGR_EMAC_t emacgrp; /* ALT_SYSMGR_EMAC */
24752  ALT_SYSMGR_DMA_t dmagrp; /* ALT_SYSMGR_DMA */
24753  volatile uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */
24754  ALT_SYSMGR_ISW_t iswgrp; /* ALT_SYSMGR_ISW */
24755  volatile uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */
24756  ALT_SYSMGR_ROMCODE_t romcodegrp; /* ALT_SYSMGR_ROMCODE */
24757  ALT_SYSMGR_ROMHW_t romhwgrp; /* ALT_SYSMGR_ROMHW */
24758  volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
24759  ALT_SYSMGR_SDMMC_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */
24760  ALT_SYSMGR_NAND_t nandgrp; /* ALT_SYSMGR_NAND */
24761  ALT_SYSMGR_USB_t usbgrp; /* ALT_SYSMGR_USB */
24762  volatile uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */
24763  ALT_SYSMGR_ECC_t eccgrp; /* ALT_SYSMGR_ECC */
24764  volatile uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */
24765  ALT_SYSMGR_PINMUX_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */
24766  volatile uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */
24767 };
24768 
24769 /* The typedef declaration for register group ALT_SYSMGR. */
24770 typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
24771 /* The struct declaration for the raw register contents of register group ALT_SYSMGR. */
24772 struct ALT_SYSMGR_raw_s
24773 {
24774  volatile uint32_t siliconid1; /* ALT_SYSMGR_SILICONID1 */
24775  volatile uint32_t siliconid2; /* ALT_SYSMGR_SILICONID2 */
24776  uint32_t _pad_0x8_0xf[2]; /* *UNDEFINED* */
24777  volatile uint32_t wddbg; /* ALT_SYSMGR_WDDBG */
24778  volatile uint32_t bootinfo; /* ALT_SYSMGR_BOOT */
24779  volatile uint32_t hpsinfo; /* ALT_SYSMGR_HPSINFO */
24780  volatile uint32_t parityinj; /* ALT_SYSMGR_PARITYINJ */
24781  ALT_SYSMGR_FPGAINTF_raw_t fpgaintfgrp; /* ALT_SYSMGR_FPGAINTF */
24782  ALT_SYSMGR_SCANMGR_raw_t scanmgrgrp; /* ALT_SYSMGR_SCANMGR */
24783  uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
24784  ALT_SYSMGR_FRZCTL_raw_t frzctrl; /* ALT_SYSMGR_FRZCTL */
24785  ALT_SYSMGR_EMAC_raw_t emacgrp; /* ALT_SYSMGR_EMAC */
24786  ALT_SYSMGR_DMA_raw_t dmagrp; /* ALT_SYSMGR_DMA */
24787  uint32_t _pad_0x78_0x7f[2]; /* *UNDEFINED* */
24788  ALT_SYSMGR_ISW_raw_t iswgrp; /* ALT_SYSMGR_ISW */
24789  uint32_t _pad_0xa0_0xbf[8]; /* *UNDEFINED* */
24790  ALT_SYSMGR_ROMCODE_raw_t romcodegrp; /* ALT_SYSMGR_ROMCODE */
24791  ALT_SYSMGR_ROMHW_raw_t romhwgrp; /* ALT_SYSMGR_ROMHW */
24792  uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
24793  ALT_SYSMGR_SDMMC_raw_t sdmmcgrp; /* ALT_SYSMGR_SDMMC */
24794  ALT_SYSMGR_NAND_raw_t nandgrp; /* ALT_SYSMGR_NAND */
24795  ALT_SYSMGR_USB_raw_t usbgrp; /* ALT_SYSMGR_USB */
24796  uint32_t _pad_0x11c_0x13f[9]; /* *UNDEFINED* */
24797  ALT_SYSMGR_ECC_raw_t eccgrp; /* ALT_SYSMGR_ECC */
24798  uint32_t _pad_0x180_0x3ff[160]; /* *UNDEFINED* */
24799  ALT_SYSMGR_PINMUX_raw_t pinmuxgrp; /* ALT_SYSMGR_PINMUX */
24800  uint32_t _pad_0x800_0x4000[3584]; /* *UNDEFINED* */
24801 };
24802 
24803 /* The typedef declaration for the raw register contents of register group ALT_SYSMGR. */
24804 typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
24805 #endif /* __ASSEMBLY__ */
24806 
24807 
24808 #ifdef __cplusplus
24809 }
24810 #endif /* __cplusplus */
24811 #endif /* __ALTERA_ALT_SYSMGR_H__ */
24812