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alt_nand.h
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32 
33 /* Altera - ALT_NAND_CFG */
34 
35 #ifndef __ALT_SOCAL_NAND_H__
36 #define __ALT_SOCAL_NAND_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
48 /*
49  * Component : Configuration registers - NAND_CFG
50  * Configuration registers
51  *
52  * Common across all types of flash devices, configuration registers
53  *
54  * setup the basic operating modes of the controller
55  *
56  */
57 /*
58  * Register : device_reset
59  *
60  * Device reset. Controller sends a RESET command to device.
61  *
62  * Controller resets bit after sending command to device
63  *
64  * Register Layout
65  *
66  * Bits | Access | Reset | Description
67  * :-------|:-------|:--------|:--------------------------------
68  * [0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RESET_BANK0
69  * [1] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RESET_BANK1
70  * [2] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RESET_BANK2
71  * [3] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RESET_BANK3
72  * [31:4] | ??? | Unknown | *UNDEFINED*
73  *
74  */
75 /*
76  * Field : bank0
77  *
78  * Issues reset to bank 0. Controller resets the bit after
79  *
80  * reset command is issued to device.
81  *
82  * Field Access Macros:
83  *
84  */
85 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field. */
86 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_LSB 0
87 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field. */
88 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_MSB 0
89 /* The width in bits of the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field. */
90 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_WIDTH 1
91 /* The mask used to set the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field value. */
92 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_SET_MSK 0x00000001
93 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field value. */
94 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_CLR_MSK 0xfffffffe
95 /* The reset value of the ALT_NAND_CFG_DEVICE_RESET_BANK0 register field. */
96 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_RESET 0x0
97 /* Extracts the ALT_NAND_CFG_DEVICE_RESET_BANK0 field value from a register. */
98 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_GET(value) (((value) & 0x00000001) >> 0)
99 /* Produces a ALT_NAND_CFG_DEVICE_RESET_BANK0 register field value suitable for setting the register. */
100 #define ALT_NAND_CFG_DEVICE_RESET_BANK0_SET(value) (((value) << 0) & 0x00000001)
101 
102 /*
103  * Field : bank1
104  *
105  * Issues reset to bank 1. Controller resets the bit after
106  *
107  * reset command is issued to device.
108  *
109  * Field Access Macros:
110  *
111  */
112 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field. */
113 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_LSB 1
114 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field. */
115 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_MSB 1
116 /* The width in bits of the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field. */
117 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_WIDTH 1
118 /* The mask used to set the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field value. */
119 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_SET_MSK 0x00000002
120 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field value. */
121 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_CLR_MSK 0xfffffffd
122 /* The reset value of the ALT_NAND_CFG_DEVICE_RESET_BANK1 register field. */
123 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_RESET 0x0
124 /* Extracts the ALT_NAND_CFG_DEVICE_RESET_BANK1 field value from a register. */
125 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_GET(value) (((value) & 0x00000002) >> 1)
126 /* Produces a ALT_NAND_CFG_DEVICE_RESET_BANK1 register field value suitable for setting the register. */
127 #define ALT_NAND_CFG_DEVICE_RESET_BANK1_SET(value) (((value) << 1) & 0x00000002)
128 
129 /*
130  * Field : bank2
131  *
132  * Issues reset to bank 2. Controller resets the bit after
133  *
134  * reset command is issued to device.
135  *
136  * Field Access Macros:
137  *
138  */
139 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field. */
140 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_LSB 2
141 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field. */
142 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_MSB 2
143 /* The width in bits of the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field. */
144 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_WIDTH 1
145 /* The mask used to set the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field value. */
146 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_SET_MSK 0x00000004
147 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field value. */
148 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_CLR_MSK 0xfffffffb
149 /* The reset value of the ALT_NAND_CFG_DEVICE_RESET_BANK2 register field. */
150 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_RESET 0x0
151 /* Extracts the ALT_NAND_CFG_DEVICE_RESET_BANK2 field value from a register. */
152 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_GET(value) (((value) & 0x00000004) >> 2)
153 /* Produces a ALT_NAND_CFG_DEVICE_RESET_BANK2 register field value suitable for setting the register. */
154 #define ALT_NAND_CFG_DEVICE_RESET_BANK2_SET(value) (((value) << 2) & 0x00000004)
155 
156 /*
157  * Field : bank3
158  *
159  * Issues reset to bank 3. Controller resets the bit after
160  *
161  * reset command is issued to device.
162  *
163  * Field Access Macros:
164  *
165  */
166 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field. */
167 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_LSB 3
168 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field. */
169 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_MSB 3
170 /* The width in bits of the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field. */
171 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_WIDTH 1
172 /* The mask used to set the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field value. */
173 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_SET_MSK 0x00000008
174 /* The mask used to clear the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field value. */
175 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_CLR_MSK 0xfffffff7
176 /* The reset value of the ALT_NAND_CFG_DEVICE_RESET_BANK3 register field. */
177 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_RESET 0x0
178 /* Extracts the ALT_NAND_CFG_DEVICE_RESET_BANK3 field value from a register. */
179 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_GET(value) (((value) & 0x00000008) >> 3)
180 /* Produces a ALT_NAND_CFG_DEVICE_RESET_BANK3 register field value suitable for setting the register. */
181 #define ALT_NAND_CFG_DEVICE_RESET_BANK3_SET(value) (((value) << 3) & 0x00000008)
182 
183 #ifndef __ASSEMBLY__
184 /*
185  * WARNING: The C register and register group struct declarations are provided for
186  * convenience and illustrative purposes. They should, however, be used with
187  * caution as the C language standard provides no guarantees about the alignment or
188  * atomicity of device memory accesses. The recommended practice for coding device
189  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
190  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
191  * alt_write_dword() functions for 64 bit registers.
192  *
193  * The struct declaration for register ALT_NAND_CFG_DEVICE_RESET.
194  */
195 struct ALT_NAND_CFG_DEVICE_RESET_s
196 {
197  volatile uint32_t bank0 : 1; /* ALT_NAND_CFG_DEVICE_RESET_BANK0 */
198  volatile uint32_t bank1 : 1; /* ALT_NAND_CFG_DEVICE_RESET_BANK1 */
199  volatile uint32_t bank2 : 1; /* ALT_NAND_CFG_DEVICE_RESET_BANK2 */
200  volatile uint32_t bank3 : 1; /* ALT_NAND_CFG_DEVICE_RESET_BANK3 */
201  uint32_t : 28; /* *UNDEFINED* */
202 };
203 
204 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_RESET. */
205 typedef struct ALT_NAND_CFG_DEVICE_RESET_s ALT_NAND_CFG_DEVICE_RESET_t;
206 #endif /* __ASSEMBLY__ */
207 
208 /* The reset value of the ALT_NAND_CFG_DEVICE_RESET register. */
209 #define ALT_NAND_CFG_DEVICE_RESET_RESET 0x00000000
210 /* The byte offset of the ALT_NAND_CFG_DEVICE_RESET register from the beginning of the component. */
211 #define ALT_NAND_CFG_DEVICE_RESET_OFST 0x0
212 /* The address of the ALT_NAND_CFG_DEVICE_RESET register. */
213 #define ALT_NAND_CFG_DEVICE_RESET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_RESET_OFST))
214 
215 /*
216  * Register : transfer_spare_reg
217  *
218  * Default data transfer mode. (Ignored during Spare only mode)
219  *
220  * Register Layout
221  *
222  * Bits | Access | Reset | Description
223  * :-------|:-------|:--------|:-------------------------------------
224  * [0] | RW | 0x0 | ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG
225  * [31:1] | ??? | Unknown | *UNDEFINED*
226  *
227  */
228 /*
229  * Field : flag
230  *
231  * On all read or write commands through Map 01, if this bit is set,
232  *
233  * data in spare area of memory will be transfered to host along with
234  *
235  * main area of data. The main area will be transfered followed by
236  *
237  * spare area.[list][*]1 - MAIN+SPARE [*]0 - MAIN[/list]
238  *
239  * Field Access Macros:
240  *
241  */
242 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field. */
243 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_LSB 0
244 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field. */
245 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_MSB 0
246 /* The width in bits of the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field. */
247 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_WIDTH 1
248 /* The mask used to set the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field value. */
249 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_SET_MSK 0x00000001
250 /* The mask used to clear the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field value. */
251 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
252 /* The reset value of the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field. */
253 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_RESET 0x0
254 /* Extracts the ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG field value from a register. */
255 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
256 /* Produces a ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG register field value suitable for setting the register. */
257 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
258 
259 #ifndef __ASSEMBLY__
260 /*
261  * WARNING: The C register and register group struct declarations are provided for
262  * convenience and illustrative purposes. They should, however, be used with
263  * caution as the C language standard provides no guarantees about the alignment or
264  * atomicity of device memory accesses. The recommended practice for coding device
265  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
266  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
267  * alt_write_dword() functions for 64 bit registers.
268  *
269  * The struct declaration for register ALT_NAND_CFG_TRANSFER_SPARE_REG.
270  */
271 struct ALT_NAND_CFG_TRANSFER_SPARE_REG_s
272 {
273  volatile uint32_t flag : 1; /* ALT_NAND_CFG_TRANSFER_SPARE_REG_FLAG */
274  uint32_t : 31; /* *UNDEFINED* */
275 };
276 
277 /* The typedef declaration for register ALT_NAND_CFG_TRANSFER_SPARE_REG. */
278 typedef struct ALT_NAND_CFG_TRANSFER_SPARE_REG_s ALT_NAND_CFG_TRANSFER_SPARE_REG_t;
279 #endif /* __ASSEMBLY__ */
280 
281 /* The reset value of the ALT_NAND_CFG_TRANSFER_SPARE_REG register. */
282 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_RESET 0x00000000
283 /* The byte offset of the ALT_NAND_CFG_TRANSFER_SPARE_REG register from the beginning of the component. */
284 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_OFST 0x10
285 /* The address of the ALT_NAND_CFG_TRANSFER_SPARE_REG register. */
286 #define ALT_NAND_CFG_TRANSFER_SPARE_REG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TRANSFER_SPARE_REG_OFST))
287 
288 /*
289  * Register : load_wait_cnt
290  *
291  * Wait count value for Load operation
292  *
293  * Register Layout
294  *
295  * Bits | Access | Reset | Description
296  * :--------|:-------|:--------|:---------------------------------
297  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE
298  * [31:16] | ??? | Unknown | *UNDEFINED*
299  *
300  */
301 /*
302  * Field : value
303  *
304  * Number of clock cycles after issue of load operation before
305  *
306  * Cadence NAND Flash Controller polls for status. This values is of
307  *
308  * relevance for status polling mode of operation and has been
309  *
310  * provided to minimize redundant polling after issuing a command.
311  *
312  * After a load command, the first polling will happen after this many
313  *
314  * number of cycles have elapsed and then on polling will happen every
315  *
316  * intmon_cyc_cnt cycles.
317  *
318  * The default values is equal to the
319  *
320  * default value of intmon_cyc_cnt.
321  *
322  * Field Access Macros:
323  *
324  */
325 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field. */
326 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_LSB 0
327 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field. */
328 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_MSB 15
329 /* The width in bits of the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field. */
330 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_WIDTH 16
331 /* The mask used to set the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field value. */
332 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
333 /* The mask used to clear the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field value. */
334 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
335 /* The reset value of the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field. */
336 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_RESET 0x1f4
337 /* Extracts the ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE field value from a register. */
338 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
339 /* Produces a ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE register field value suitable for setting the register. */
340 #define ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
341 
342 #ifndef __ASSEMBLY__
343 /*
344  * WARNING: The C register and register group struct declarations are provided for
345  * convenience and illustrative purposes. They should, however, be used with
346  * caution as the C language standard provides no guarantees about the alignment or
347  * atomicity of device memory accesses. The recommended practice for coding device
348  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
349  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
350  * alt_write_dword() functions for 64 bit registers.
351  *
352  * The struct declaration for register ALT_NAND_CFG_LOAD_WAIT_CNT.
353  */
354 struct ALT_NAND_CFG_LOAD_WAIT_CNT_s
355 {
356  volatile uint32_t value : 16; /* ALT_NAND_CFG_LOAD_WAIT_CNT_VALUE */
357  uint32_t : 16; /* *UNDEFINED* */
358 };
359 
360 /* The typedef declaration for register ALT_NAND_CFG_LOAD_WAIT_CNT. */
361 typedef struct ALT_NAND_CFG_LOAD_WAIT_CNT_s ALT_NAND_CFG_LOAD_WAIT_CNT_t;
362 #endif /* __ASSEMBLY__ */
363 
364 /* The reset value of the ALT_NAND_CFG_LOAD_WAIT_CNT register. */
365 #define ALT_NAND_CFG_LOAD_WAIT_CNT_RESET 0x000001f4
366 /* The byte offset of the ALT_NAND_CFG_LOAD_WAIT_CNT register from the beginning of the component. */
367 #define ALT_NAND_CFG_LOAD_WAIT_CNT_OFST 0x20
368 /* The address of the ALT_NAND_CFG_LOAD_WAIT_CNT register. */
369 #define ALT_NAND_CFG_LOAD_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_LOAD_WAIT_CNT_OFST))
370 
371 /*
372  * Register : program_wait_cnt
373  *
374  * Wait count value for Program operation
375  *
376  * Register Layout
377  *
378  * Bits | Access | Reset | Description
379  * :--------|:-------|:--------|:------------------------------------
380  * [15:0] | RW | 0x1f40 | ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE
381  * [31:16] | ??? | Unknown | *UNDEFINED*
382  *
383  */
384 /*
385  * Field : value
386  *
387  * Number of clock cycles after issue of program operation before
388  *
389  * Cadence NAND Flash Controller polls for status. This values is of
390  *
391  * relevance for status polling mode of operation and has been
392  *
393  * provided to minimize redundant polling after issuing a command.
394  *
395  * After a program command, the first polling will happen after this many
396  *
397  * number of cycles have elapsed and then on polling will happen every
398  *
399  * intmon_cyc_cnt cycles.
400  *
401  * The default values is equal to the
402  *
403  * default value of intmon_cyc_cnt. The controller internally multiplies
404  *
405  * the value programmed into this register by 16 to provide a wider
406  *
407  * range for polling.
408  *
409  * Field Access Macros:
410  *
411  */
412 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
413 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
414 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
415 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
416 /* The width in bits of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
417 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
418 /* The mask used to set the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
419 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
420 /* The mask used to clear the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value. */
421 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
422 /* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field. */
423 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f40
424 /* Extracts the ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE field value from a register. */
425 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
426 /* Produces a ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE register field value suitable for setting the register. */
427 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
428 
429 #ifndef __ASSEMBLY__
430 /*
431  * WARNING: The C register and register group struct declarations are provided for
432  * convenience and illustrative purposes. They should, however, be used with
433  * caution as the C language standard provides no guarantees about the alignment or
434  * atomicity of device memory accesses. The recommended practice for coding device
435  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
436  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
437  * alt_write_dword() functions for 64 bit registers.
438  *
439  * The struct declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT.
440  */
441 struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
442 {
443  volatile uint32_t value : 16; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE */
444  uint32_t : 16; /* *UNDEFINED* */
445 };
446 
447 /* The typedef declaration for register ALT_NAND_CFG_PROGRAM_WAIT_CNT. */
448 typedef struct ALT_NAND_CFG_PROGRAM_WAIT_CNT_s ALT_NAND_CFG_PROGRAM_WAIT_CNT_t;
449 #endif /* __ASSEMBLY__ */
450 
451 /* The reset value of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register. */
452 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_RESET 0x00001f40
453 /* The byte offset of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register from the beginning of the component. */
454 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
455 /* The address of the ALT_NAND_CFG_PROGRAM_WAIT_CNT register. */
456 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST))
457 
458 /*
459  * Register : erase_wait_cnt
460  *
461  * Wait count value for Erase operation
462  *
463  * Register Layout
464  *
465  * Bits | Access | Reset | Description
466  * :--------|:-------|:--------|:----------------------------------
467  * [15:0] | RW | 0x1f40 | ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE
468  * [31:16] | ??? | Unknown | *UNDEFINED*
469  *
470  */
471 /*
472  * Field : value
473  *
474  * Number of clock cycles after issue of erase operation before
475  *
476  * Cadence NAND Flash Controller polls for status. This values is of
477  *
478  * relevance for status polling mode of operation and has been
479  *
480  * provided to minimize redundant polling after issuing a command.
481  *
482  * After a erase command, the first polling will happen after this many
483  *
484  * number of cycles have elapsed and then on polling will happen every
485  *
486  * intmon_cyc_cnt cycles.
487  *
488  * The default values is equal to the
489  *
490  * default value of intmon_cyc_cnt. The controller internally multiplies
491  *
492  * the value programmed into this register by 16 to provide a wider
493  *
494  * range for polling.
495  *
496  * Field Access Macros:
497  *
498  */
499 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
500 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
501 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
502 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
503 /* The width in bits of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
504 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
505 /* The mask used to set the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
506 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
507 /* The mask used to clear the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value. */
508 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
509 /* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field. */
510 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f40
511 /* Extracts the ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE field value from a register. */
512 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
513 /* Produces a ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE register field value suitable for setting the register. */
514 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
515 
516 #ifndef __ASSEMBLY__
517 /*
518  * WARNING: The C register and register group struct declarations are provided for
519  * convenience and illustrative purposes. They should, however, be used with
520  * caution as the C language standard provides no guarantees about the alignment or
521  * atomicity of device memory accesses. The recommended practice for coding device
522  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
523  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
524  * alt_write_dword() functions for 64 bit registers.
525  *
526  * The struct declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT.
527  */
528 struct ALT_NAND_CFG_ERASE_WAIT_CNT_s
529 {
530  volatile uint32_t value : 16; /* ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE */
531  uint32_t : 16; /* *UNDEFINED* */
532 };
533 
534 /* The typedef declaration for register ALT_NAND_CFG_ERASE_WAIT_CNT. */
535 typedef struct ALT_NAND_CFG_ERASE_WAIT_CNT_s ALT_NAND_CFG_ERASE_WAIT_CNT_t;
536 #endif /* __ASSEMBLY__ */
537 
538 /* The reset value of the ALT_NAND_CFG_ERASE_WAIT_CNT register. */
539 #define ALT_NAND_CFG_ERASE_WAIT_CNT_RESET 0x00001f40
540 /* The byte offset of the ALT_NAND_CFG_ERASE_WAIT_CNT register from the beginning of the component. */
541 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
542 /* The address of the ALT_NAND_CFG_ERASE_WAIT_CNT register. */
543 #define ALT_NAND_CFG_ERASE_WAIT_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ERASE_WAIT_CNT_OFST))
544 
545 /*
546  * Register : int_mon_cyccnt
547  *
548  * Interrupt monitor cycle count value
549  *
550  * Register Layout
551  *
552  * Bits | Access | Reset | Description
553  * :--------|:-------|:--------|:----------------------------------
554  * [15:0] | RW | 0x1f4 | ALT_NAND_CFG_INT_MON_CYCCNT_VALUE
555  * [31:16] | ??? | Unknown | *UNDEFINED*
556  *
557  */
558 /*
559  * Field : value
560  *
561  * In polling mode, sets the number of cycles Cadence Flash Controller
562  *
563  * must wait before checking the status register. This register is
564  *
565  * only used when R/B pins are not available to Cadence NAND Flash
566  *
567  * Controller.
568  *
569  * Field Access Macros:
570  *
571  */
572 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
573 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
574 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
575 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
576 /* The width in bits of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
577 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
578 /* The mask used to set the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
579 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
580 /* The mask used to clear the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value. */
581 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
582 /* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field. */
583 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
584 /* Extracts the ALT_NAND_CFG_INT_MON_CYCCNT_VALUE field value from a register. */
585 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
586 /* Produces a ALT_NAND_CFG_INT_MON_CYCCNT_VALUE register field value suitable for setting the register. */
587 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
588 
589 #ifndef __ASSEMBLY__
590 /*
591  * WARNING: The C register and register group struct declarations are provided for
592  * convenience and illustrative purposes. They should, however, be used with
593  * caution as the C language standard provides no guarantees about the alignment or
594  * atomicity of device memory accesses. The recommended practice for coding device
595  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
596  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
597  * alt_write_dword() functions for 64 bit registers.
598  *
599  * The struct declaration for register ALT_NAND_CFG_INT_MON_CYCCNT.
600  */
601 struct ALT_NAND_CFG_INT_MON_CYCCNT_s
602 {
603  volatile uint32_t value : 16; /* ALT_NAND_CFG_INT_MON_CYCCNT_VALUE */
604  uint32_t : 16; /* *UNDEFINED* */
605 };
606 
607 /* The typedef declaration for register ALT_NAND_CFG_INT_MON_CYCCNT. */
608 typedef struct ALT_NAND_CFG_INT_MON_CYCCNT_s ALT_NAND_CFG_INT_MON_CYCCNT_t;
609 #endif /* __ASSEMBLY__ */
610 
611 /* The reset value of the ALT_NAND_CFG_INT_MON_CYCCNT register. */
612 #define ALT_NAND_CFG_INT_MON_CYCCNT_RESET 0x000001f4
613 /* The byte offset of the ALT_NAND_CFG_INT_MON_CYCCNT register from the beginning of the component. */
614 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
615 /* The address of the ALT_NAND_CFG_INT_MON_CYCCNT register. */
616 #define ALT_NAND_CFG_INT_MON_CYCCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_INT_MON_CYCCNT_OFST))
617 
618 /*
619  * Register : rb_pin_enabled
620  *
621  * Interrupt or polling mode. Ready/Busy pin is enabled from device.
622  *
623  * Register Layout
624  *
625  * Bits | Access | Reset | Description
626  * :-------|:-------|:--------|:----------------------------------
627  * [0] | RW | 0x1 | ALT_NAND_CFG_RB_PIN_ENABLED_BANK0
628  * [1] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_ENABLED_BANK1
629  * [2] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_ENABLED_BANK2
630  * [3] | RW | 0x0 | ALT_NAND_CFG_RB_PIN_ENABLED_BANK3
631  * [31:4] | ??? | Unknown | *UNDEFINED*
632  *
633  */
634 /*
635  * Field : bank0
636  *
637  * Sets Cadence Flash Controller in interrupt pin or polling mode
638  *
639  * [list][*]1 - R/B pin enabled for bank 0. Interrupt pin mode.
640  *
641  * [*]0 - R/B pin disabled for bank 0. Polling mode.[/list]
642  *
643  * Field Access Macros:
644  *
645  */
646 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field. */
647 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_LSB 0
648 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field. */
649 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_MSB 0
650 /* The width in bits of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field. */
651 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_WIDTH 1
652 /* The mask used to set the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field value. */
653 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_SET_MSK 0x00000001
654 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field value. */
655 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_CLR_MSK 0xfffffffe
656 /* The reset value of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field. */
657 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_RESET 0x1
658 /* Extracts the ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 field value from a register. */
659 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_GET(value) (((value) & 0x00000001) >> 0)
660 /* Produces a ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 register field value suitable for setting the register. */
661 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK0_SET(value) (((value) << 0) & 0x00000001)
662 
663 /*
664  * Field : bank1
665  *
666  * Sets Cadence Flash Controller in interrupt pin or polling mode
667  *
668  * [list][*]1 - R/B pin enabled for bank 1. Interrupt pin mode.
669  *
670  * [*]0 - R/B pin disabled for bank 1. Polling mode.[/list]
671  *
672  * Field Access Macros:
673  *
674  */
675 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field. */
676 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_LSB 1
677 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field. */
678 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_MSB 1
679 /* The width in bits of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field. */
680 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_WIDTH 1
681 /* The mask used to set the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field value. */
682 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_SET_MSK 0x00000002
683 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field value. */
684 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_CLR_MSK 0xfffffffd
685 /* The reset value of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field. */
686 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_RESET 0x0
687 /* Extracts the ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 field value from a register. */
688 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_GET(value) (((value) & 0x00000002) >> 1)
689 /* Produces a ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 register field value suitable for setting the register. */
690 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK1_SET(value) (((value) << 1) & 0x00000002)
691 
692 /*
693  * Field : bank2
694  *
695  * Sets Cadence Flash Controller in interrupt pin or polling mode
696  *
697  * [list][*]1 - R/B pin enabled for bank 2. Interrupt pin mode.
698  *
699  * [*]0 - R/B pin disabled for bank 2. Polling mode.[/list]
700  *
701  * Field Access Macros:
702  *
703  */
704 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field. */
705 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_LSB 2
706 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field. */
707 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_MSB 2
708 /* The width in bits of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field. */
709 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_WIDTH 1
710 /* The mask used to set the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field value. */
711 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_SET_MSK 0x00000004
712 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field value. */
713 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_CLR_MSK 0xfffffffb
714 /* The reset value of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field. */
715 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_RESET 0x0
716 /* Extracts the ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 field value from a register. */
717 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_GET(value) (((value) & 0x00000004) >> 2)
718 /* Produces a ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 register field value suitable for setting the register. */
719 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK2_SET(value) (((value) << 2) & 0x00000004)
720 
721 /*
722  * Field : bank3
723  *
724  * Sets Cadence Flash Controller in interrupt pin or polling mode
725  *
726  * [list][*]1 - R/B pin enabled for bank 3. Interrupt pin mode.
727  *
728  * [*]0 - R/B pin disabled for bank 3. Polling mode.[/list]
729  *
730  * Field Access Macros:
731  *
732  */
733 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field. */
734 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_LSB 3
735 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field. */
736 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_MSB 3
737 /* The width in bits of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field. */
738 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_WIDTH 1
739 /* The mask used to set the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field value. */
740 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_SET_MSK 0x00000008
741 /* The mask used to clear the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field value. */
742 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_CLR_MSK 0xfffffff7
743 /* The reset value of the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field. */
744 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_RESET 0x0
745 /* Extracts the ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 field value from a register. */
746 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_GET(value) (((value) & 0x00000008) >> 3)
747 /* Produces a ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 register field value suitable for setting the register. */
748 #define ALT_NAND_CFG_RB_PIN_ENABLED_BANK3_SET(value) (((value) << 3) & 0x00000008)
749 
750 #ifndef __ASSEMBLY__
751 /*
752  * WARNING: The C register and register group struct declarations are provided for
753  * convenience and illustrative purposes. They should, however, be used with
754  * caution as the C language standard provides no guarantees about the alignment or
755  * atomicity of device memory accesses. The recommended practice for coding device
756  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
757  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
758  * alt_write_dword() functions for 64 bit registers.
759  *
760  * The struct declaration for register ALT_NAND_CFG_RB_PIN_ENABLED.
761  */
762 struct ALT_NAND_CFG_RB_PIN_ENABLED_s
763 {
764  volatile uint32_t bank0 : 1; /* ALT_NAND_CFG_RB_PIN_ENABLED_BANK0 */
765  volatile uint32_t bank1 : 1; /* ALT_NAND_CFG_RB_PIN_ENABLED_BANK1 */
766  volatile uint32_t bank2 : 1; /* ALT_NAND_CFG_RB_PIN_ENABLED_BANK2 */
767  volatile uint32_t bank3 : 1; /* ALT_NAND_CFG_RB_PIN_ENABLED_BANK3 */
768  uint32_t : 28; /* *UNDEFINED* */
769 };
770 
771 /* The typedef declaration for register ALT_NAND_CFG_RB_PIN_ENABLED. */
772 typedef struct ALT_NAND_CFG_RB_PIN_ENABLED_s ALT_NAND_CFG_RB_PIN_ENABLED_t;
773 #endif /* __ASSEMBLY__ */
774 
775 /* The reset value of the ALT_NAND_CFG_RB_PIN_ENABLED register. */
776 #define ALT_NAND_CFG_RB_PIN_ENABLED_RESET 0x00000001
777 /* The byte offset of the ALT_NAND_CFG_RB_PIN_ENABLED register from the beginning of the component. */
778 #define ALT_NAND_CFG_RB_PIN_ENABLED_OFST 0x60
779 /* The address of the ALT_NAND_CFG_RB_PIN_ENABLED register. */
780 #define ALT_NAND_CFG_RB_PIN_ENABLED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RB_PIN_ENABLED_OFST))
781 
782 /*
783  * Register : multiplane_operation
784  *
785  * Multiplane transfer mode. Pipelined read, copyback, erase
786  *
787  * and program commands are transfered in multiplane mode
788  *
789  * Register Layout
790  *
791  * Bits | Access | Reset | Description
792  * :-------|:-------|:--------|:---------------------------------------
793  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG
794  * [31:1] | ??? | Unknown | *UNDEFINED*
795  *
796  */
797 /*
798  * Field : flag
799  *
800  * [list][*]1 - Multiplane operation enabled
801  *
802  * [*]0 - Multiplane operation disabled[/list]
803  *
804  * Field Access Macros:
805  *
806  */
807 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field. */
808 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_LSB 0
809 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field. */
810 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_MSB 0
811 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field. */
812 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_WIDTH 1
813 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field value. */
814 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_SET_MSK 0x00000001
815 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field value. */
816 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_CLR_MSK 0xfffffffe
817 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field. */
818 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_RESET 0x0
819 /* Extracts the ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG field value from a register. */
820 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_GET(value) (((value) & 0x00000001) >> 0)
821 /* Produces a ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG register field value suitable for setting the register. */
822 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG_SET(value) (((value) << 0) & 0x00000001)
823 
824 #ifndef __ASSEMBLY__
825 /*
826  * WARNING: The C register and register group struct declarations are provided for
827  * convenience and illustrative purposes. They should, however, be used with
828  * caution as the C language standard provides no guarantees about the alignment or
829  * atomicity of device memory accesses. The recommended practice for coding device
830  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
831  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
832  * alt_write_dword() functions for 64 bit registers.
833  *
834  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_OPERATION.
835  */
836 struct ALT_NAND_CFG_MULTIPLANE_OPERATION_s
837 {
838  volatile uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_OPERATION_FLAG */
839  uint32_t : 31; /* *UNDEFINED* */
840 };
841 
842 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_OPERATION. */
843 typedef struct ALT_NAND_CFG_MULTIPLANE_OPERATION_s ALT_NAND_CFG_MULTIPLANE_OPERATION_t;
844 #endif /* __ASSEMBLY__ */
845 
846 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_OPERATION register. */
847 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_RESET 0x00000000
848 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_OPERATION register from the beginning of the component. */
849 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_OFST 0x70
850 /* The address of the ALT_NAND_CFG_MULTIPLANE_OPERATION register. */
851 #define ALT_NAND_CFG_MULTIPLANE_OPERATION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_OPERATION_OFST))
852 
853 /*
854  * Register : multiplane_read_enable
855  *
856  * Device supports multiplane read command sequence
857  *
858  * Register Layout
859  *
860  * Bits | Access | Reset | Description
861  * :-------|:-------|:--------|:-----------------------------------------
862  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG
863  * [31:1] | ??? | Unknown | *UNDEFINED*
864  *
865  */
866 /*
867  * Field : flag
868  *
869  * Certain devices support dedicated multiplane read command sequences
870  *
871  * to read data in the same fashion as is written with multiplane program
872  *
873  * commands. This bit set should be set for the above devices. When not set,
874  *
875  * pipeline reads in multiplane mode will still happen in the order of multiplane
876  *
877  * writes, though normal read command sequences will be issued to the device.
878  *
879  * [list][*]1 - Device supports multiplane read sequence
880  *
881  * [*]0 - Device does not support multiplane read sequence[/list]
882  *
883  * Field Access Macros:
884  *
885  */
886 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field. */
887 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_LSB 0
888 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field. */
889 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_MSB 0
890 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field. */
891 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_WIDTH 1
892 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field value. */
893 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_SET_MSK 0x00000001
894 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field value. */
895 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_CLR_MSK 0xfffffffe
896 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field. */
897 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_RESET 0x0
898 /* Extracts the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG field value from a register. */
899 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
900 /* Produces a ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG register field value suitable for setting the register. */
901 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
902 
903 #ifndef __ASSEMBLY__
904 /*
905  * WARNING: The C register and register group struct declarations are provided for
906  * convenience and illustrative purposes. They should, however, be used with
907  * caution as the C language standard provides no guarantees about the alignment or
908  * atomicity of device memory accesses. The recommended practice for coding device
909  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
910  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
911  * alt_write_dword() functions for 64 bit registers.
912  *
913  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_READ_ENABLE.
914  */
915 struct ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_s
916 {
917  volatile uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_FLAG */
918  uint32_t : 31; /* *UNDEFINED* */
919 };
920 
921 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_READ_ENABLE. */
922 typedef struct ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_s ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_t;
923 #endif /* __ASSEMBLY__ */
924 
925 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE register. */
926 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_RESET 0x00000000
927 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE register from the beginning of the component. */
928 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_OFST 0x80
929 /* The address of the ALT_NAND_CFG_MULTIPLANE_READ_ENABLE register. */
930 #define ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_OFST))
931 
932 /*
933  * Register : copyback_disable
934  *
935  * Device does not support copyback command sequence
936  *
937  * Register Layout
938  *
939  * Bits | Access | Reset | Description
940  * :-------|:-------|:--------|:-----------------------------------
941  * [0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_DISABLE_FLAG
942  * [31:1] | ??? | Unknown | *UNDEFINED*
943  *
944  */
945 /*
946  * Field : flag
947  *
948  * [list][*]1 - Copyback disabled [*]0 - Copyback enabled[/list]
949  *
950  * Field Access Macros:
951  *
952  */
953 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field. */
954 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_LSB 0
955 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field. */
956 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_MSB 0
957 /* The width in bits of the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field. */
958 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_WIDTH 1
959 /* The mask used to set the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field value. */
960 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_SET_MSK 0x00000001
961 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field value. */
962 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_CLR_MSK 0xfffffffe
963 /* The reset value of the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field. */
964 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_RESET 0x0
965 /* Extracts the ALT_NAND_CFG_COPYBACK_DISABLE_FLAG field value from a register. */
966 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
967 /* Produces a ALT_NAND_CFG_COPYBACK_DISABLE_FLAG register field value suitable for setting the register. */
968 #define ALT_NAND_CFG_COPYBACK_DISABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
969 
970 #ifndef __ASSEMBLY__
971 /*
972  * WARNING: The C register and register group struct declarations are provided for
973  * convenience and illustrative purposes. They should, however, be used with
974  * caution as the C language standard provides no guarantees about the alignment or
975  * atomicity of device memory accesses. The recommended practice for coding device
976  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
977  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
978  * alt_write_dword() functions for 64 bit registers.
979  *
980  * The struct declaration for register ALT_NAND_CFG_COPYBACK_DISABLE.
981  */
982 struct ALT_NAND_CFG_COPYBACK_DISABLE_s
983 {
984  volatile uint32_t flag : 1; /* ALT_NAND_CFG_COPYBACK_DISABLE_FLAG */
985  uint32_t : 31; /* *UNDEFINED* */
986 };
987 
988 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_DISABLE. */
989 typedef struct ALT_NAND_CFG_COPYBACK_DISABLE_s ALT_NAND_CFG_COPYBACK_DISABLE_t;
990 #endif /* __ASSEMBLY__ */
991 
992 /* The reset value of the ALT_NAND_CFG_COPYBACK_DISABLE register. */
993 #define ALT_NAND_CFG_COPYBACK_DISABLE_RESET 0x00000000
994 /* The byte offset of the ALT_NAND_CFG_COPYBACK_DISABLE register from the beginning of the component. */
995 #define ALT_NAND_CFG_COPYBACK_DISABLE_OFST 0x90
996 /* The address of the ALT_NAND_CFG_COPYBACK_DISABLE register. */
997 #define ALT_NAND_CFG_COPYBACK_DISABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_COPYBACK_DISABLE_OFST))
998 
999 /*
1000  * Register : cache_write_enable
1001  *
1002  * Device supports cache write command sequence
1003  *
1004  * Register Layout
1005  *
1006  * Bits | Access | Reset | Description
1007  * :-------|:-------|:--------|:-------------------------------------
1008  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG
1009  * [31:1] | ??? | Unknown | *UNDEFINED*
1010  *
1011  */
1012 /*
1013  * Field : flag
1014  *
1015  * [list][*]1 - Cache write supported [*]0 - Cache write not supported[/list]
1016  *
1017  * Field Access Macros:
1018  *
1019  */
1020 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field. */
1021 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_LSB 0
1022 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field. */
1023 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_MSB 0
1024 /* The width in bits of the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field. */
1025 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_WIDTH 1
1026 /* The mask used to set the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field value. */
1027 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_SET_MSK 0x00000001
1028 /* The mask used to clear the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field value. */
1029 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_CLR_MSK 0xfffffffe
1030 /* The reset value of the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field. */
1031 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_RESET 0x0
1032 /* Extracts the ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG field value from a register. */
1033 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1034 /* Produces a ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG register field value suitable for setting the register. */
1035 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1036 
1037 #ifndef __ASSEMBLY__
1038 /*
1039  * WARNING: The C register and register group struct declarations are provided for
1040  * convenience and illustrative purposes. They should, however, be used with
1041  * caution as the C language standard provides no guarantees about the alignment or
1042  * atomicity of device memory accesses. The recommended practice for coding device
1043  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1044  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1045  * alt_write_dword() functions for 64 bit registers.
1046  *
1047  * The struct declaration for register ALT_NAND_CFG_CACHE_WRITE_ENABLE.
1048  */
1049 struct ALT_NAND_CFG_CACHE_WRITE_ENABLE_s
1050 {
1051  volatile uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_WRITE_ENABLE_FLAG */
1052  uint32_t : 31; /* *UNDEFINED* */
1053 };
1054 
1055 /* The typedef declaration for register ALT_NAND_CFG_CACHE_WRITE_ENABLE. */
1056 typedef struct ALT_NAND_CFG_CACHE_WRITE_ENABLE_s ALT_NAND_CFG_CACHE_WRITE_ENABLE_t;
1057 #endif /* __ASSEMBLY__ */
1058 
1059 /* The reset value of the ALT_NAND_CFG_CACHE_WRITE_ENABLE register. */
1060 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_RESET 0x00000000
1061 /* The byte offset of the ALT_NAND_CFG_CACHE_WRITE_ENABLE register from the beginning of the component. */
1062 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_OFST 0xa0
1063 /* The address of the ALT_NAND_CFG_CACHE_WRITE_ENABLE register. */
1064 #define ALT_NAND_CFG_CACHE_WRITE_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CACHE_WRITE_ENABLE_OFST))
1065 
1066 /*
1067  * Register : cache_read_enable
1068  *
1069  * Device supports cache read command sequence
1070  *
1071  * Register Layout
1072  *
1073  * Bits | Access | Reset | Description
1074  * :-------|:-------|:--------|:------------------------------------
1075  * [0] | RW | 0x0 | ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG
1076  * [31:1] | ??? | Unknown | *UNDEFINED*
1077  *
1078  */
1079 /*
1080  * Field : flag
1081  *
1082  * [list][*]1 - Cache read supported [*]0 - Cache read not supported[/list]
1083  *
1084  * Field Access Macros:
1085  *
1086  */
1087 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field. */
1088 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_LSB 0
1089 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field. */
1090 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_MSB 0
1091 /* The width in bits of the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field. */
1092 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_WIDTH 1
1093 /* The mask used to set the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field value. */
1094 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_SET_MSK 0x00000001
1095 /* The mask used to clear the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field value. */
1096 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_CLR_MSK 0xfffffffe
1097 /* The reset value of the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field. */
1098 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_RESET 0x0
1099 /* Extracts the ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG field value from a register. */
1100 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1101 /* Produces a ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG register field value suitable for setting the register. */
1102 #define ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1103 
1104 #ifndef __ASSEMBLY__
1105 /*
1106  * WARNING: The C register and register group struct declarations are provided for
1107  * convenience and illustrative purposes. They should, however, be used with
1108  * caution as the C language standard provides no guarantees about the alignment or
1109  * atomicity of device memory accesses. The recommended practice for coding device
1110  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1111  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1112  * alt_write_dword() functions for 64 bit registers.
1113  *
1114  * The struct declaration for register ALT_NAND_CFG_CACHE_READ_ENABLE.
1115  */
1116 struct ALT_NAND_CFG_CACHE_READ_ENABLE_s
1117 {
1118  volatile uint32_t flag : 1; /* ALT_NAND_CFG_CACHE_READ_ENABLE_FLAG */
1119  uint32_t : 31; /* *UNDEFINED* */
1120 };
1121 
1122 /* The typedef declaration for register ALT_NAND_CFG_CACHE_READ_ENABLE. */
1123 typedef struct ALT_NAND_CFG_CACHE_READ_ENABLE_s ALT_NAND_CFG_CACHE_READ_ENABLE_t;
1124 #endif /* __ASSEMBLY__ */
1125 
1126 /* The reset value of the ALT_NAND_CFG_CACHE_READ_ENABLE register. */
1127 #define ALT_NAND_CFG_CACHE_READ_ENABLE_RESET 0x00000000
1128 /* The byte offset of the ALT_NAND_CFG_CACHE_READ_ENABLE register from the beginning of the component. */
1129 #define ALT_NAND_CFG_CACHE_READ_ENABLE_OFST 0xb0
1130 /* The address of the ALT_NAND_CFG_CACHE_READ_ENABLE register. */
1131 #define ALT_NAND_CFG_CACHE_READ_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CACHE_READ_ENABLE_OFST))
1132 
1133 /*
1134  * Register : prefetch_mode
1135  *
1136  * Enables read data prefetching to faster performance
1137  *
1138  * Register Layout
1139  *
1140  * Bits | Access | Reset | Description
1141  * :--------|:-------|:--------|:-------------------------------------------------
1142  * [0] | RW | 0x1 | ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN
1143  * [3:1] | ??? | Unknown | *UNDEFINED*
1144  * [15:4] | RW | 0x0 | ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH
1145  * [31:16] | ??? | Unknown | *UNDEFINED*
1146  *
1147  */
1148 /*
1149  * Field : prefetch_en
1150  *
1151  * Enable prefetch of Data
1152  *
1153  * Field Access Macros:
1154  *
1155  */
1156 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field. */
1157 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_LSB 0
1158 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field. */
1159 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_MSB 0
1160 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field. */
1161 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_WIDTH 1
1162 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field value. */
1163 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_SET_MSK 0x00000001
1164 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field value. */
1165 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_CLR_MSK 0xfffffffe
1166 /* The reset value of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field. */
1167 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_RESET 0x1
1168 /* Extracts the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN field value from a register. */
1169 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1170 /* Produces a ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN register field value suitable for setting the register. */
1171 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1172 
1173 /*
1174  * Field : prefetch_burst_length
1175  *
1176  * If prefetch_en is set and prefetch_burst_length is set to ZERO, the controller
1177  * will
1178  *
1179  * start prefetching data only after the receiving the first Map01 read command for
1180  * the page.
1181  *
1182  * If prefetch_en is set and prefetch_burst_length is set to a non-ZERO, valid
1183  * value,
1184  *
1185  * the controller will start prefetching data corresponding to this value even
1186  * before
1187  *
1188  * the first Map01 for the current page has been received.
1189  *
1190  * The value written here should be in bytes.
1191  *
1192  * Field Access Macros:
1193  *
1194  */
1195 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field. */
1196 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_LSB 4
1197 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field. */
1198 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_MSB 15
1199 /* The width in bits of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field. */
1200 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_WIDTH 12
1201 /* The mask used to set the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field value. */
1202 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_SET_MSK 0x0000fff0
1203 /* The mask used to clear the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field value. */
1204 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_CLR_MSK 0xffff000f
1205 /* The reset value of the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field. */
1206 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_RESET 0x0
1207 /* Extracts the ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH field value from a register. */
1208 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_GET(value) (((value) & 0x0000fff0) >> 4)
1209 /* Produces a ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH register field value suitable for setting the register. */
1210 #define ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH_SET(value) (((value) << 4) & 0x0000fff0)
1211 
1212 #ifndef __ASSEMBLY__
1213 /*
1214  * WARNING: The C register and register group struct declarations are provided for
1215  * convenience and illustrative purposes. They should, however, be used with
1216  * caution as the C language standard provides no guarantees about the alignment or
1217  * atomicity of device memory accesses. The recommended practice for coding device
1218  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1219  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1220  * alt_write_dword() functions for 64 bit registers.
1221  *
1222  * The struct declaration for register ALT_NAND_CFG_PREFETCH_MODE.
1223  */
1224 struct ALT_NAND_CFG_PREFETCH_MODE_s
1225 {
1226  volatile uint32_t prefetch_en : 1; /* ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_EN */
1227  uint32_t : 3; /* *UNDEFINED* */
1228  volatile uint32_t prefetch_burst_length : 12; /* ALT_NAND_CFG_PREFETCH_MODE_PREFETCH_BURST_LENGTH */
1229  uint32_t : 16; /* *UNDEFINED* */
1230 };
1231 
1232 /* The typedef declaration for register ALT_NAND_CFG_PREFETCH_MODE. */
1233 typedef struct ALT_NAND_CFG_PREFETCH_MODE_s ALT_NAND_CFG_PREFETCH_MODE_t;
1234 #endif /* __ASSEMBLY__ */
1235 
1236 /* The reset value of the ALT_NAND_CFG_PREFETCH_MODE register. */
1237 #define ALT_NAND_CFG_PREFETCH_MODE_RESET 0x00000001
1238 /* The byte offset of the ALT_NAND_CFG_PREFETCH_MODE register from the beginning of the component. */
1239 #define ALT_NAND_CFG_PREFETCH_MODE_OFST 0xc0
1240 /* The address of the ALT_NAND_CFG_PREFETCH_MODE register. */
1241 #define ALT_NAND_CFG_PREFETCH_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PREFETCH_MODE_OFST))
1242 
1243 /*
1244  * Register : chip_enable_dont_care
1245  *
1246  * Device can work in the chip enable dont care mode
1247  *
1248  * Register Layout
1249  *
1250  * Bits | Access | Reset | Description
1251  * :-------|:-------|:--------|:----------------------------------------
1252  * [0] | RW | 0x0 | ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG
1253  * [31:1] | ??? | Unknown | *UNDEFINED*
1254  *
1255  */
1256 /*
1257  * Field : flag
1258  *
1259  * Controller can interleave commands between banks when this feature is enabled.
1260  *
1261  * [list][*]1 - Device in dont care mode
1262  *
1263  * [*]0 - Device cares for chip enable[/list]
1264  *
1265  * Field Access Macros:
1266  *
1267  */
1268 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field. */
1269 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_LSB 0
1270 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field. */
1271 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_MSB 0
1272 /* The width in bits of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field. */
1273 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_WIDTH 1
1274 /* The mask used to set the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field value. */
1275 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_SET_MSK 0x00000001
1276 /* The mask used to clear the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field value. */
1277 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1278 /* The reset value of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field. */
1279 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_RESET 0x0
1280 /* Extracts the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG field value from a register. */
1281 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1282 /* Produces a ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG register field value suitable for setting the register. */
1283 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1284 
1285 #ifndef __ASSEMBLY__
1286 /*
1287  * WARNING: The C register and register group struct declarations are provided for
1288  * convenience and illustrative purposes. They should, however, be used with
1289  * caution as the C language standard provides no guarantees about the alignment or
1290  * atomicity of device memory accesses. The recommended practice for coding device
1291  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1292  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1293  * alt_write_dword() functions for 64 bit registers.
1294  *
1295  * The struct declaration for register ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE.
1296  */
1297 struct ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_s
1298 {
1299  volatile uint32_t flag : 1; /* ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_FLAG */
1300  uint32_t : 31; /* *UNDEFINED* */
1301 };
1302 
1303 /* The typedef declaration for register ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE. */
1304 typedef struct ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_s ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_t;
1305 #endif /* __ASSEMBLY__ */
1306 
1307 /* The reset value of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE register. */
1308 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_RESET 0x00000000
1309 /* The byte offset of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE register from the beginning of the component. */
1310 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_OFST 0xd0
1311 /* The address of the ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE register. */
1312 #define ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_OFST))
1313 
1314 /*
1315  * Register : ecc_enable
1316  *
1317  * Enable controller ECC check bit generation and correction
1318  *
1319  * Register Layout
1320  *
1321  * Bits | Access | Reset | Description
1322  * :-------|:-------|:--------|:-----------------------------
1323  * [0] | RW | 0x1 | ALT_NAND_CFG_ECC_ENABLE_FLAG
1324  * [31:1] | ??? | Unknown | *UNDEFINED*
1325  *
1326  */
1327 /*
1328  * Field : flag
1329  *
1330  * Enables or disables controller ECC capabilities. When enabled, controller
1331  * calculates
1332  *
1333  * ECC check-bits and writes them onto device on program operation. On page reads,
1334  *
1335  * check-bits are recomputed and errors reported, if any, after comparing with
1336  * stored
1337  *
1338  * check-bits. When disabled, controller does not compute check-bits.
1339  *
1340  * [list][*]1 - ECC Enabled [*]0 - ECC disabled[/list]
1341  *
1342  * Field Access Macros:
1343  *
1344  */
1345 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_ENABLE_FLAG register field. */
1346 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_LSB 0
1347 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_ENABLE_FLAG register field. */
1348 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_MSB 0
1349 /* The width in bits of the ALT_NAND_CFG_ECC_ENABLE_FLAG register field. */
1350 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_WIDTH 1
1351 /* The mask used to set the ALT_NAND_CFG_ECC_ENABLE_FLAG register field value. */
1352 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_SET_MSK 0x00000001
1353 /* The mask used to clear the ALT_NAND_CFG_ECC_ENABLE_FLAG register field value. */
1354 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_CLR_MSK 0xfffffffe
1355 /* The reset value of the ALT_NAND_CFG_ECC_ENABLE_FLAG register field. */
1356 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_RESET 0x1
1357 /* Extracts the ALT_NAND_CFG_ECC_ENABLE_FLAG field value from a register. */
1358 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1359 /* Produces a ALT_NAND_CFG_ECC_ENABLE_FLAG register field value suitable for setting the register. */
1360 #define ALT_NAND_CFG_ECC_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1361 
1362 #ifndef __ASSEMBLY__
1363 /*
1364  * WARNING: The C register and register group struct declarations are provided for
1365  * convenience and illustrative purposes. They should, however, be used with
1366  * caution as the C language standard provides no guarantees about the alignment or
1367  * atomicity of device memory accesses. The recommended practice for coding device
1368  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1369  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1370  * alt_write_dword() functions for 64 bit registers.
1371  *
1372  * The struct declaration for register ALT_NAND_CFG_ECC_ENABLE.
1373  */
1374 struct ALT_NAND_CFG_ECC_ENABLE_s
1375 {
1376  volatile uint32_t flag : 1; /* ALT_NAND_CFG_ECC_ENABLE_FLAG */
1377  uint32_t : 31; /* *UNDEFINED* */
1378 };
1379 
1380 /* The typedef declaration for register ALT_NAND_CFG_ECC_ENABLE. */
1381 typedef struct ALT_NAND_CFG_ECC_ENABLE_s ALT_NAND_CFG_ECC_ENABLE_t;
1382 #endif /* __ASSEMBLY__ */
1383 
1384 /* The reset value of the ALT_NAND_CFG_ECC_ENABLE register. */
1385 #define ALT_NAND_CFG_ECC_ENABLE_RESET 0x00000001
1386 /* The byte offset of the ALT_NAND_CFG_ECC_ENABLE register from the beginning of the component. */
1387 #define ALT_NAND_CFG_ECC_ENABLE_OFST 0xe0
1388 /* The address of the ALT_NAND_CFG_ECC_ENABLE register. */
1389 #define ALT_NAND_CFG_ECC_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ECC_ENABLE_OFST))
1390 
1391 /*
1392  * Register : global_int_enable
1393  *
1394  * Global Interrupt enable and Error/Timeout disable.
1395  *
1396  * Register Layout
1397  *
1398  * Bits | Access | Reset | Description
1399  * :-------|:-------|:--------|:-------------------------------------------------
1400  * [0] | RW | 0x0 | ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG
1401  * [3:1] | ??? | Unknown | *UNDEFINED*
1402  * [4] | RW | 0x0 | ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE
1403  * [7:5] | ??? | Unknown | *UNDEFINED*
1404  * [8] | RW | 0x0 | ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE
1405  * [31:9] | ??? | Unknown | *UNDEFINED*
1406  *
1407  */
1408 /*
1409  * Field : flag
1410  *
1411  * Host will receive an interrupt only when this bit is set.
1412  *
1413  * Field Access Macros:
1414  *
1415  */
1416 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field. */
1417 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_LSB 0
1418 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field. */
1419 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_MSB 0
1420 /* The width in bits of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field. */
1421 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_WIDTH 1
1422 /* The mask used to set the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field value. */
1423 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_SET_MSK 0x00000001
1424 /* The mask used to clear the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field value. */
1425 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_CLR_MSK 0xfffffffe
1426 /* The reset value of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field. */
1427 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_RESET 0x0
1428 /* Extracts the ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG field value from a register. */
1429 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1430 /* Produces a ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG register field value suitable for setting the register. */
1431 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1432 
1433 /*
1434  * Field : timeout_disable
1435  *
1436  * Watchdog timer logic will be de-activated when
1437  *
1438  * this bit is set.
1439  *
1440  * Field Access Macros:
1441  *
1442  */
1443 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field. */
1444 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_LSB 4
1445 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field. */
1446 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_MSB 4
1447 /* The width in bits of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field. */
1448 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_WIDTH 1
1449 /* The mask used to set the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field value. */
1450 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_SET_MSK 0x00000010
1451 /* The mask used to clear the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field value. */
1452 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_CLR_MSK 0xffffffef
1453 /* The reset value of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field. */
1454 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_RESET 0x0
1455 /* Extracts the ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE field value from a register. */
1456 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_GET(value) (((value) & 0x00000010) >> 4)
1457 /* Produces a ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE register field value suitable for setting the register. */
1458 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE_SET(value) (((value) << 4) & 0x00000010)
1459 
1460 /*
1461  * Field : error_rpt_disable
1462  *
1463  * Command and ECC uncorrectable failures will not be
1464  *
1465  * reported when this bit is set
1466  *
1467  * Field Access Macros:
1468  *
1469  */
1470 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field. */
1471 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_LSB 8
1472 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field. */
1473 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_MSB 8
1474 /* The width in bits of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field. */
1475 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_WIDTH 1
1476 /* The mask used to set the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field value. */
1477 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_SET_MSK 0x00000100
1478 /* The mask used to clear the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field value. */
1479 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_CLR_MSK 0xfffffeff
1480 /* The reset value of the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field. */
1481 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_RESET 0x0
1482 /* Extracts the ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE field value from a register. */
1483 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_GET(value) (((value) & 0x00000100) >> 8)
1484 /* Produces a ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE register field value suitable for setting the register. */
1485 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE_SET(value) (((value) << 8) & 0x00000100)
1486 
1487 #ifndef __ASSEMBLY__
1488 /*
1489  * WARNING: The C register and register group struct declarations are provided for
1490  * convenience and illustrative purposes. They should, however, be used with
1491  * caution as the C language standard provides no guarantees about the alignment or
1492  * atomicity of device memory accesses. The recommended practice for coding device
1493  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1494  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1495  * alt_write_dword() functions for 64 bit registers.
1496  *
1497  * The struct declaration for register ALT_NAND_CFG_GLOBAL_INT_ENABLE.
1498  */
1499 struct ALT_NAND_CFG_GLOBAL_INT_ENABLE_s
1500 {
1501  volatile uint32_t flag : 1; /* ALT_NAND_CFG_GLOBAL_INT_ENABLE_FLAG */
1502  uint32_t : 3; /* *UNDEFINED* */
1503  volatile uint32_t timeout_disable : 1; /* ALT_NAND_CFG_GLOBAL_INT_ENABLE_TIMEOUT_DISABLE */
1504  uint32_t : 3; /* *UNDEFINED* */
1505  volatile uint32_t error_rpt_disable : 1; /* ALT_NAND_CFG_GLOBAL_INT_ENABLE_ERROR_RPT_DISABLE */
1506  uint32_t : 23; /* *UNDEFINED* */
1507 };
1508 
1509 /* The typedef declaration for register ALT_NAND_CFG_GLOBAL_INT_ENABLE. */
1510 typedef struct ALT_NAND_CFG_GLOBAL_INT_ENABLE_s ALT_NAND_CFG_GLOBAL_INT_ENABLE_t;
1511 #endif /* __ASSEMBLY__ */
1512 
1513 /* The reset value of the ALT_NAND_CFG_GLOBAL_INT_ENABLE register. */
1514 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_RESET 0x00000000
1515 /* The byte offset of the ALT_NAND_CFG_GLOBAL_INT_ENABLE register from the beginning of the component. */
1516 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_OFST 0xf0
1517 /* The address of the ALT_NAND_CFG_GLOBAL_INT_ENABLE register. */
1518 #define ALT_NAND_CFG_GLOBAL_INT_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_GLOBAL_INT_ENABLE_OFST))
1519 
1520 /*
1521  * Register : twhr2_and_we_2_re
1522  *
1523  * Register Layout
1524  *
1525  * Bits | Access | Reset | Description
1526  * :--------|:-------|:--------|:---------------------------------------
1527  * [5:0] | RW | 0x32 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE
1528  * [7:6] | ??? | Unknown | *UNDEFINED*
1529  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2
1530  * [31:14] | ??? | Unknown | *UNDEFINED*
1531  *
1532  */
1533 /*
1534  * Field : we_2_re
1535  *
1536  * Signifies the number of bus interface clk_x clocks that should be introduced
1537  * between
1538  *
1539  * write enable going high to read enable going low. The number of clocks is the
1540  *
1541  * function of device parameter Twhr and controller clock frequency.
1542  *
1543  * Field Access Macros:
1544  *
1545  */
1546 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1547 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1548 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1549 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1550 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1551 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1552 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1553 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1554 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value. */
1555 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1556 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field. */
1557 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1558 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE field value from a register. */
1559 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1560 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value suitable for setting the register. */
1561 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1562 
1563 /*
1564  * Field : twhr2
1565  *
1566  * Signifies the number of controller clocks that should be introduced between
1567  *
1568  * the last command of a random data output command to the start of the data
1569  * transfer.
1570  *
1571  * Field Access Macros:
1572  *
1573  */
1574 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1575 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1576 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1577 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1578 /* The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1579 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1580 /* The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1581 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1582 /* The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value. */
1583 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1584 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field. */
1585 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1586 /* Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 field value from a register. */
1587 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1588 /* Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value suitable for setting the register. */
1589 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1590 
1591 #ifndef __ASSEMBLY__
1592 /*
1593  * WARNING: The C register and register group struct declarations are provided for
1594  * convenience and illustrative purposes. They should, however, be used with
1595  * caution as the C language standard provides no guarantees about the alignment or
1596  * atomicity of device memory accesses. The recommended practice for coding device
1597  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1598  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1599  * alt_write_dword() functions for 64 bit registers.
1600  *
1601  * The struct declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE.
1602  */
1603 struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1604 {
1605  volatile uint32_t we_2_re : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE */
1606  uint32_t : 2; /* *UNDEFINED* */
1607  volatile uint32_t twhr2 : 6; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 */
1608  uint32_t : 18; /* *UNDEFINED* */
1609 };
1610 
1611 /* The typedef declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE. */
1612 typedef struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t;
1613 #endif /* __ASSEMBLY__ */
1614 
1615 /* The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register. */
1616 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_RESET 0x00001432
1617 /* The byte offset of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register from the beginning of the component. */
1618 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1619 /* The address of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register. */
1620 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST))
1621 
1622 /*
1623  * Register : tcwaw_and_addr_2_data
1624  *
1625  * Register Layout
1626  *
1627  * Bits | Access | Reset | Description
1628  * :--------|:-------|:--------|:-----------------------------------------------
1629  * [6:0] | RW | 0x32 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA
1630  * [7] | ??? | Unknown | *UNDEFINED*
1631  * [13:8] | RW | 0x14 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW
1632  * [31:14] | ??? | Unknown | *UNDEFINED*
1633  *
1634  */
1635 /*
1636  * Field : addr_2_data
1637  *
1638  * Signifies the number of bus interface clk_x clocks that should be introduced
1639  *
1640  * between an address to a data input cycle. The number of clocks is the function
1641  * of device
1642  *
1643  * parameter Tadl and controller clock frequency.
1644  *
1645  * Field Access Macros:
1646  *
1647  */
1648 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1649 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1650 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1651 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 6
1652 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1653 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 7
1654 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1655 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000007f
1656 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value. */
1657 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffff80
1658 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field. */
1659 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1660 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA field value from a register. */
1661 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000007f) >> 0)
1662 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value suitable for setting the register. */
1663 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000007f)
1664 
1665 /*
1666  * Field : tcwaw
1667  *
1668  * Signifies the number of controller clocks that should be introduced between
1669  *
1670  * the command cycle of a random data input command to the address cycle of the
1671  * random
1672  *
1673  * data input command.
1674  *
1675  * Field Access Macros:
1676  *
1677  */
1678 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1679 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1680 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1681 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1682 /* The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1683 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1684 /* The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1685 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1686 /* The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value. */
1687 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1688 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field. */
1689 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1690 /* Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW field value from a register. */
1691 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1692 /* Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value suitable for setting the register. */
1693 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1694 
1695 #ifndef __ASSEMBLY__
1696 /*
1697  * WARNING: The C register and register group struct declarations are provided for
1698  * convenience and illustrative purposes. They should, however, be used with
1699  * caution as the C language standard provides no guarantees about the alignment or
1700  * atomicity of device memory accesses. The recommended practice for coding device
1701  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1702  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1703  * alt_write_dword() functions for 64 bit registers.
1704  *
1705  * The struct declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA.
1706  */
1707 struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1708 {
1709  volatile uint32_t addr_2_data : 7; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA */
1710  uint32_t : 1; /* *UNDEFINED* */
1711  volatile uint32_t tcwaw : 6; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW */
1712  uint32_t : 18; /* *UNDEFINED* */
1713 };
1714 
1715 /* The typedef declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA. */
1716 typedef struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t;
1717 #endif /* __ASSEMBLY__ */
1718 
1719 /* The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register. */
1720 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_RESET 0x00001432
1721 /* The byte offset of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register from the beginning of the component. */
1722 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1723 /* The address of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register. */
1724 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST))
1725 
1726 /*
1727  * Register : re_2_we
1728  *
1729  * Timing parameter between re high to we low (Trhw)
1730  *
1731  * Register Layout
1732  *
1733  * Bits | Access | Reset | Description
1734  * :-------|:-------|:--------|:---------------------------
1735  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_WE_VALUE
1736  * [31:6] | ??? | Unknown | *UNDEFINED*
1737  *
1738  */
1739 /*
1740  * Field : value
1741  *
1742  * Signifies the number of bus interface clk_x clocks that should be introduced
1743  * between
1744  *
1745  * read enable going high to write enable going low. The number of clocks is the
1746  *
1747  * function of device parameter Trhw and controller clock frequency.
1748  *
1749  * Field Access Macros:
1750  *
1751  */
1752 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1753 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1754 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1755 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1756 /* The width in bits of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1757 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1758 /* The mask used to set the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1759 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1760 /* The mask used to clear the ALT_NAND_CFG_RE_2_WE_VALUE register field value. */
1761 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1762 /* The reset value of the ALT_NAND_CFG_RE_2_WE_VALUE register field. */
1763 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1764 /* Extracts the ALT_NAND_CFG_RE_2_WE_VALUE field value from a register. */
1765 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1766 /* Produces a ALT_NAND_CFG_RE_2_WE_VALUE register field value suitable for setting the register. */
1767 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1768 
1769 #ifndef __ASSEMBLY__
1770 /*
1771  * WARNING: The C register and register group struct declarations are provided for
1772  * convenience and illustrative purposes. They should, however, be used with
1773  * caution as the C language standard provides no guarantees about the alignment or
1774  * atomicity of device memory accesses. The recommended practice for coding device
1775  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1776  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1777  * alt_write_dword() functions for 64 bit registers.
1778  *
1779  * The struct declaration for register ALT_NAND_CFG_RE_2_WE.
1780  */
1781 struct ALT_NAND_CFG_RE_2_WE_s
1782 {
1783  volatile uint32_t value : 6; /* ALT_NAND_CFG_RE_2_WE_VALUE */
1784  uint32_t : 26; /* *UNDEFINED* */
1785 };
1786 
1787 /* The typedef declaration for register ALT_NAND_CFG_RE_2_WE. */
1788 typedef struct ALT_NAND_CFG_RE_2_WE_s ALT_NAND_CFG_RE_2_WE_t;
1789 #endif /* __ASSEMBLY__ */
1790 
1791 /* The reset value of the ALT_NAND_CFG_RE_2_WE register. */
1792 #define ALT_NAND_CFG_RE_2_WE_RESET 0x00000032
1793 /* The byte offset of the ALT_NAND_CFG_RE_2_WE register from the beginning of the component. */
1794 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1795 /* The address of the ALT_NAND_CFG_RE_2_WE register. */
1796 #define ALT_NAND_CFG_RE_2_WE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RE_2_WE_OFST))
1797 
1798 /*
1799  * Register : acc_clks
1800  *
1801  * Timing parameter from read enable going low to capture read data
1802  *
1803  * Register Layout
1804  *
1805  * Bits | Access | Reset | Description
1806  * :-------|:-------|:--------|:----------------------------
1807  * [3:0] | RW | 0x0 | ALT_NAND_CFG_ACC_CLKS_VALUE
1808  * [31:4] | ??? | Unknown | *UNDEFINED*
1809  *
1810  */
1811 /*
1812  * Field : value
1813  *
1814  * Signifies the number of bus interface clk_x clock cycles, controller
1815  *
1816  * should wait from read enable going low to sending out a strobe of clk_x for
1817  *
1818  * capturing of incoming data.
1819  *
1820  * Field Access Macros:
1821  *
1822  */
1823 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1824 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1825 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1826 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1827 /* The width in bits of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1828 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1829 /* The mask used to set the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1830 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1831 /* The mask used to clear the ALT_NAND_CFG_ACC_CLKS_VALUE register field value. */
1832 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1833 /* The reset value of the ALT_NAND_CFG_ACC_CLKS_VALUE register field. */
1834 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1835 /* Extracts the ALT_NAND_CFG_ACC_CLKS_VALUE field value from a register. */
1836 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1837 /* Produces a ALT_NAND_CFG_ACC_CLKS_VALUE register field value suitable for setting the register. */
1838 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1839 
1840 #ifndef __ASSEMBLY__
1841 /*
1842  * WARNING: The C register and register group struct declarations are provided for
1843  * convenience and illustrative purposes. They should, however, be used with
1844  * caution as the C language standard provides no guarantees about the alignment or
1845  * atomicity of device memory accesses. The recommended practice for coding device
1846  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1847  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1848  * alt_write_dword() functions for 64 bit registers.
1849  *
1850  * The struct declaration for register ALT_NAND_CFG_ACC_CLKS.
1851  */
1852 struct ALT_NAND_CFG_ACC_CLKS_s
1853 {
1854  volatile uint32_t value : 4; /* ALT_NAND_CFG_ACC_CLKS_VALUE */
1855  uint32_t : 28; /* *UNDEFINED* */
1856 };
1857 
1858 /* The typedef declaration for register ALT_NAND_CFG_ACC_CLKS. */
1859 typedef struct ALT_NAND_CFG_ACC_CLKS_s ALT_NAND_CFG_ACC_CLKS_t;
1860 #endif /* __ASSEMBLY__ */
1861 
1862 /* The reset value of the ALT_NAND_CFG_ACC_CLKS register. */
1863 #define ALT_NAND_CFG_ACC_CLKS_RESET 0x00000000
1864 /* The byte offset of the ALT_NAND_CFG_ACC_CLKS register from the beginning of the component. */
1865 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1866 /* The address of the ALT_NAND_CFG_ACC_CLKS register. */
1867 #define ALT_NAND_CFG_ACC_CLKS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ACC_CLKS_OFST))
1868 
1869 /*
1870  * Register : number_of_planes
1871  *
1872  * Number of planes in the device
1873  *
1874  * Register Layout
1875  *
1876  * Bits | Access | Reset | Description
1877  * :-------|:-------|:--------|:------------------------------------
1878  * [2:0] | RW | 0x0 | ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE
1879  * [31:3] | ??? | Unknown | *UNDEFINED*
1880  *
1881  */
1882 /*
1883  * Field : value
1884  *
1885  * Controller will read Electronic Signature of devices and populate
1886  *
1887  * this field as the number of planes information is present in the signature.
1888  *
1889  * For 512B device, this information needs to be programmed by software.
1890  *
1891  * Software could also choose to override the populated value.
1892  *
1893  * The values in the fields should be as follows[list]
1894  *
1895  * [*]3'h0 - Monoplane device
1896  *
1897  * [*]3'h1 - Two plane device
1898  *
1899  * [*]3'h3 - 4 plane device
1900  *
1901  * [*]3'h7 - 8 plane device
1902  *
1903  * [*]All other values - Reserved[/list]
1904  *
1905  * Field Access Macros:
1906  *
1907  */
1908 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1909 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1910 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1911 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1912 /* The width in bits of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1913 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1914 /* The mask used to set the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1915 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1916 /* The mask used to clear the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value. */
1917 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1918 /* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field. */
1919 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1920 /* Extracts the ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE field value from a register. */
1921 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1922 /* Produces a ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE register field value suitable for setting the register. */
1923 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1924 
1925 #ifndef __ASSEMBLY__
1926 /*
1927  * WARNING: The C register and register group struct declarations are provided for
1928  * convenience and illustrative purposes. They should, however, be used with
1929  * caution as the C language standard provides no guarantees about the alignment or
1930  * atomicity of device memory accesses. The recommended practice for coding device
1931  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
1932  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
1933  * alt_write_dword() functions for 64 bit registers.
1934  *
1935  * The struct declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES.
1936  */
1937 struct ALT_NAND_CFG_NUMBER_OF_PLANES_s
1938 {
1939  volatile uint32_t value : 3; /* ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE */
1940  uint32_t : 29; /* *UNDEFINED* */
1941 };
1942 
1943 /* The typedef declaration for register ALT_NAND_CFG_NUMBER_OF_PLANES. */
1944 typedef struct ALT_NAND_CFG_NUMBER_OF_PLANES_s ALT_NAND_CFG_NUMBER_OF_PLANES_t;
1945 #endif /* __ASSEMBLY__ */
1946 
1947 /* The reset value of the ALT_NAND_CFG_NUMBER_OF_PLANES register. */
1948 #define ALT_NAND_CFG_NUMBER_OF_PLANES_RESET 0x00000000
1949 /* The byte offset of the ALT_NAND_CFG_NUMBER_OF_PLANES register from the beginning of the component. */
1950 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1951 /* The address of the ALT_NAND_CFG_NUMBER_OF_PLANES register. */
1952 #define ALT_NAND_CFG_NUMBER_OF_PLANES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_NUMBER_OF_PLANES_OFST))
1953 
1954 /*
1955  * Register : pages_per_block
1956  *
1957  * Number of pages in a block
1958  *
1959  * Register Layout
1960  *
1961  * Bits | Access | Reset | Description
1962  * :--------|:-------|:--------|:-----------------------------------
1963  * [15:0] | RW | 0x0 | ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE
1964  * [31:16] | ??? | Unknown | *UNDEFINED*
1965  *
1966  */
1967 /*
1968  * Field : value
1969  *
1970  * Controller will read Electronic Signature of devices and populate
1971  *
1972  * this field. For 512B devices, bootstrap_512B_device will determine the value of
1973  *
1974  * this field to be of 32. Software could also choose to override the populated
1975  *
1976  * value.
1977  *
1978  * Field Access Macros:
1979  *
1980  */
1981 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1982 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1983 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1984 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1985 /* The width in bits of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1986 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1987 /* The mask used to set the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1988 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1989 /* The mask used to clear the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value. */
1990 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1991 /* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field. */
1992 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1993 /* Extracts the ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE field value from a register. */
1994 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1995 /* Produces a ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE register field value suitable for setting the register. */
1996 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1997 
1998 #ifndef __ASSEMBLY__
1999 /*
2000  * WARNING: The C register and register group struct declarations are provided for
2001  * convenience and illustrative purposes. They should, however, be used with
2002  * caution as the C language standard provides no guarantees about the alignment or
2003  * atomicity of device memory accesses. The recommended practice for coding device
2004  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2005  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2006  * alt_write_dword() functions for 64 bit registers.
2007  *
2008  * The struct declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK.
2009  */
2010 struct ALT_NAND_CFG_PAGES_PER_BLOCK_s
2011 {
2012  volatile uint32_t value : 16; /* ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE */
2013  uint32_t : 16; /* *UNDEFINED* */
2014 };
2015 
2016 /* The typedef declaration for register ALT_NAND_CFG_PAGES_PER_BLOCK. */
2017 typedef struct ALT_NAND_CFG_PAGES_PER_BLOCK_s ALT_NAND_CFG_PAGES_PER_BLOCK_t;
2018 #endif /* __ASSEMBLY__ */
2019 
2020 /* The reset value of the ALT_NAND_CFG_PAGES_PER_BLOCK register. */
2021 #define ALT_NAND_CFG_PAGES_PER_BLOCK_RESET 0x00000000
2022 /* The byte offset of the ALT_NAND_CFG_PAGES_PER_BLOCK register from the beginning of the component. */
2023 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
2024 /* The address of the ALT_NAND_CFG_PAGES_PER_BLOCK register. */
2025 #define ALT_NAND_CFG_PAGES_PER_BLOCK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_PAGES_PER_BLOCK_OFST))
2026 
2027 /*
2028  * Register : device_width
2029  *
2030  * I/O width of attached devices
2031  *
2032  * Register Layout
2033  *
2034  * Bits | Access | Reset | Description
2035  * :-------|:-------|:--------|:--------------------------------
2036  * [1:0] | RW | 0x3 | ALT_NAND_CFG_DEVICE_WIDTH_VALUE
2037  * [31:2] | ??? | Unknown | *UNDEFINED*
2038  *
2039  */
2040 /*
2041  * Field : value
2042  *
2043  * Controller will read Electronic Signature of devices and populate
2044  *
2045  * this field. For 512B devices, bootstrap_x16_device will determine the value of
2046  *
2047  * this field. Software could also choose to override the populated value.
2048  *
2049  * The values in this field should be as follows[list][*]2'h00 - 8bit device[*]
2050  *
2051  * 2'h01 - 16bit device[*]All other values - Reserved[/list]
2052  *
2053  * Field Access Macros:
2054  *
2055  */
2056 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
2057 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
2058 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
2059 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
2060 /* The width in bits of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
2061 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
2062 /* The mask used to set the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
2063 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
2064 /* The mask used to clear the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value. */
2065 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
2066 /* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field. */
2067 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
2068 /* Extracts the ALT_NAND_CFG_DEVICE_WIDTH_VALUE field value from a register. */
2069 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
2070 /* Produces a ALT_NAND_CFG_DEVICE_WIDTH_VALUE register field value suitable for setting the register. */
2071 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
2072 
2073 #ifndef __ASSEMBLY__
2074 /*
2075  * WARNING: The C register and register group struct declarations are provided for
2076  * convenience and illustrative purposes. They should, however, be used with
2077  * caution as the C language standard provides no guarantees about the alignment or
2078  * atomicity of device memory accesses. The recommended practice for coding device
2079  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2080  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2081  * alt_write_dword() functions for 64 bit registers.
2082  *
2083  * The struct declaration for register ALT_NAND_CFG_DEVICE_WIDTH.
2084  */
2085 struct ALT_NAND_CFG_DEVICE_WIDTH_s
2086 {
2087  volatile uint32_t value : 2; /* ALT_NAND_CFG_DEVICE_WIDTH_VALUE */
2088  uint32_t : 30; /* *UNDEFINED* */
2089 };
2090 
2091 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_WIDTH. */
2092 typedef struct ALT_NAND_CFG_DEVICE_WIDTH_s ALT_NAND_CFG_DEVICE_WIDTH_t;
2093 #endif /* __ASSEMBLY__ */
2094 
2095 /* The reset value of the ALT_NAND_CFG_DEVICE_WIDTH register. */
2096 #define ALT_NAND_CFG_DEVICE_WIDTH_RESET 0x00000003
2097 /* The byte offset of the ALT_NAND_CFG_DEVICE_WIDTH register from the beginning of the component. */
2098 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
2099 /* The address of the ALT_NAND_CFG_DEVICE_WIDTH register. */
2100 #define ALT_NAND_CFG_DEVICE_WIDTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_WIDTH_OFST))
2101 
2102 /*
2103  * Register : device_main_area_size
2104  *
2105  * Page main area size of device in bytes
2106  *
2107  * Register Layout
2108  *
2109  * Bits | Access | Reset | Description
2110  * :--------|:-------|:--------|:-----------------------------------------
2111  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE
2112  * [31:16] | ??? | Unknown | *UNDEFINED*
2113  *
2114  */
2115 /*
2116  * Field : value
2117  *
2118  * Controller will read Electronic Signature of devices and populate
2119  *
2120  * this field. For 512B devices, bootstrap_512B_device will determine the value
2121  *
2122  * of this field to be 512. Software could also choose to override the populated
2123  *
2124  * value.
2125  *
2126  * Field Access Macros:
2127  *
2128  */
2129 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2130 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
2131 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2132 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
2133 /* The width in bits of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2134 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
2135 /* The mask used to set the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
2136 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2137 /* The mask used to clear the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value. */
2138 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2139 /* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field. */
2140 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
2141 /* Extracts the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE field value from a register. */
2142 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2143 /* Produces a ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE register field value suitable for setting the register. */
2144 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2145 
2146 #ifndef __ASSEMBLY__
2147 /*
2148  * WARNING: The C register and register group struct declarations are provided for
2149  * convenience and illustrative purposes. They should, however, be used with
2150  * caution as the C language standard provides no guarantees about the alignment or
2151  * atomicity of device memory accesses. The recommended practice for coding device
2152  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2153  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2154  * alt_write_dword() functions for 64 bit registers.
2155  *
2156  * The struct declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE.
2157  */
2158 struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
2159 {
2160  volatile uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE */
2161  uint32_t : 16; /* *UNDEFINED* */
2162 };
2163 
2164 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE. */
2165 typedef struct ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t;
2166 #endif /* __ASSEMBLY__ */
2167 
2168 /* The reset value of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register. */
2169 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_RESET 0x00000000
2170 /* The byte offset of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register from the beginning of the component. */
2171 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
2172 /* The address of the ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE register. */
2173 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST))
2174 
2175 /*
2176  * Register : device_spare_area_size
2177  *
2178  * Page spare area size of device in bytes
2179  *
2180  * Register Layout
2181  *
2182  * Bits | Access | Reset | Description
2183  * :--------|:-------|:--------|:------------------------------------------
2184  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE
2185  * [31:16] | ??? | Unknown | *UNDEFINED*
2186  *
2187  */
2188 /*
2189  * Field : value
2190  *
2191  * Controller will read Electronic Signature of devices and populate
2192  *
2193  * this field. For 512B devices, bootstrap_512B_device will determine the value
2194  *
2195  * of this field to be 16. Software could also choose to override the populated
2196  *
2197  * value.
2198  *
2199  * Field Access Macros:
2200  *
2201  */
2202 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2203 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
2204 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2205 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
2206 /* The width in bits of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2207 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
2208 /* The mask used to set the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
2209 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2210 /* The mask used to clear the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value. */
2211 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2212 /* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field. */
2213 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
2214 /* Extracts the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE field value from a register. */
2215 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2216 /* Produces a ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE register field value suitable for setting the register. */
2217 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2218 
2219 #ifndef __ASSEMBLY__
2220 /*
2221  * WARNING: The C register and register group struct declarations are provided for
2222  * convenience and illustrative purposes. They should, however, be used with
2223  * caution as the C language standard provides no guarantees about the alignment or
2224  * atomicity of device memory accesses. The recommended practice for coding device
2225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2227  * alt_write_dword() functions for 64 bit registers.
2228  *
2229  * The struct declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE.
2230  */
2231 struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
2232 {
2233  volatile uint32_t value : 16; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE */
2234  uint32_t : 16; /* *UNDEFINED* */
2235 };
2236 
2237 /* The typedef declaration for register ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE. */
2238 typedef struct ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t;
2239 #endif /* __ASSEMBLY__ */
2240 
2241 /* The reset value of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register. */
2242 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_RESET 0x00000000
2243 /* The byte offset of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register from the beginning of the component. */
2244 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2245 /* The address of the ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE register. */
2246 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST))
2247 
2248 /*
2249  * Register : two_row_addr_cycles
2250  *
2251  * Attached device has only 2 ROW address cycles
2252  *
2253  * Register Layout
2254  *
2255  * Bits | Access | Reset | Description
2256  * :-------|:-------|:--------|:--------------------------------------
2257  * [0] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG
2258  * [3:1] | ??? | Unknown | *UNDEFINED*
2259  * [4] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR
2260  * [31:5] | ??? | Unknown | *UNDEFINED*
2261  *
2262  */
2263 /*
2264  * Field : flag
2265  *
2266  * This flag must be set for devices which allow for 2 ROW address cycles instead
2267  *
2268  * of the usual 3. Alternatively, bootstrap_two_row_addr_cycles when asserted will
2269  *
2270  * set this flag.
2271  *
2272  * Field Access Macros:
2273  *
2274  */
2275 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2276 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2277 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2278 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2279 /* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2280 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2281 /* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2282 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2283 /* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value. */
2284 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2285 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field. */
2286 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2287 /* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG field value from a register. */
2288 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2289 /* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value suitable for setting the register. */
2290 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2291 
2292 /*
2293  * Field : four
2294  *
2295  * This flag must be set for devices which allow for 4 ROW address cycles instead
2296  *
2297  * of the usual 3.
2298  *
2299  * Field Access Macros:
2300  *
2301  */
2302 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2303 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4
2304 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2305 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4
2306 /* The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2307 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1
2308 /* The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value. */
2309 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010
2310 /* The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value. */
2311 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef
2312 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field. */
2313 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0
2314 /* Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR field value from a register. */
2315 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4)
2316 /* Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value suitable for setting the register. */
2317 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010)
2318 
2319 #ifndef __ASSEMBLY__
2320 /*
2321  * WARNING: The C register and register group struct declarations are provided for
2322  * convenience and illustrative purposes. They should, however, be used with
2323  * caution as the C language standard provides no guarantees about the alignment or
2324  * atomicity of device memory accesses. The recommended practice for coding device
2325  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2326  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2327  * alt_write_dword() functions for 64 bit registers.
2328  *
2329  * The struct declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES.
2330  */
2331 struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2332 {
2333  volatile uint32_t flag : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG */
2334  uint32_t : 3; /* *UNDEFINED* */
2335  volatile uint32_t four : 1; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR */
2336  uint32_t : 27; /* *UNDEFINED* */
2337 };
2338 
2339 /* The typedef declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES. */
2340 typedef struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t;
2341 #endif /* __ASSEMBLY__ */
2342 
2343 /* The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register. */
2344 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000
2345 /* The byte offset of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register from the beginning of the component. */
2346 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2347 /* The address of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register. */
2348 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST))
2349 
2350 /*
2351  * Register : multiplane_addr_restrict
2352  *
2353  * Address restriction for multiplane commands
2354  *
2355  * Register Layout
2356  *
2357  * Bits | Access | Reset | Description
2358  * :-------|:-------|:--------|:-------------------------------------------
2359  * [0] | RW | 0x0 | ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG
2360  * [31:1] | ??? | Unknown | *UNDEFINED*
2361  *
2362  */
2363 /*
2364  * Field : flag
2365  *
2366  * This flag must be set for devices which require that during multiplane
2367  *
2368  * operations all but the address for the last plane should have their address
2369  *
2370  * cycles tied low. The last plane address cycles has proper values. This
2371  *
2372  * ensures multiplane address restrictions in the device.
2373  *
2374  * Field Access Macros:
2375  *
2376  */
2377 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2378 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2379 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2380 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2381 /* The width in bits of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2382 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2383 /* The mask used to set the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2384 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2385 /* The mask used to clear the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value. */
2386 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2387 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field. */
2388 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2389 /* Extracts the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG field value from a register. */
2390 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2391 /* Produces a ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG register field value suitable for setting the register. */
2392 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2393 
2394 #ifndef __ASSEMBLY__
2395 /*
2396  * WARNING: The C register and register group struct declarations are provided for
2397  * convenience and illustrative purposes. They should, however, be used with
2398  * caution as the C language standard provides no guarantees about the alignment or
2399  * atomicity of device memory accesses. The recommended practice for coding device
2400  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2401  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2402  * alt_write_dword() functions for 64 bit registers.
2403  *
2404  * The struct declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT.
2405  */
2406 struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2407 {
2408  volatile uint32_t flag : 1; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG */
2409  uint32_t : 31; /* *UNDEFINED* */
2410 };
2411 
2412 /* The typedef declaration for register ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT. */
2413 typedef struct ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t;
2414 #endif /* __ASSEMBLY__ */
2415 
2416 /* The reset value of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register. */
2417 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_RESET 0x00000000
2418 /* The byte offset of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register from the beginning of the component. */
2419 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2420 /* The address of the ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT register. */
2421 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST))
2422 
2423 /*
2424  * Register : ecc_correction
2425  *
2426  * Correction capability required and the Erase threshold value.
2427  *
2428  * Register Layout
2429  *
2430  * Bits | Access | Reset | Description
2431  * :--------|:-------|:--------|:--------------------------------------------
2432  * [7:0] | RW | 0x8 | ALT_NAND_CFG_ECC_CORRECTION_VALUE
2433  * [15:8] | ??? | Unknown | *UNDEFINED*
2434  * [31:16] | RW | 0x0 | ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD
2435  *
2436  */
2437 /*
2438  * Field : value
2439  *
2440  * The required correction capability. A smaller correction capability will
2441  *
2442  * lead to lesser number of ECC check-bits being written per ECC sector.
2443  *
2444  * The supported ECC correction levels are -
2445  *
2446  * [list]
2447  *
2448  * [*] 16,8,4 over 512 bytes.
2449  *
2450  * [*] 24 over 1024 bytes.
2451  *
2452  * [*] All other values will cause the correction value in the controller
2453  *
2454  * to fall back to the previously selected value.
2455  *
2456  * [/list]
2457  *
2458  * Field Access Macros:
2459  *
2460  */
2461 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2462 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2463 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2464 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2465 /* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2466 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2467 /* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2468 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2469 /* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value. */
2470 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2471 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field. */
2472 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2473 /* Extracts the ALT_NAND_CFG_ECC_CORRECTION_VALUE field value from a register. */
2474 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2475 /* Produces a ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value suitable for setting the register. */
2476 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2477 
2478 /*
2479  * Field : erase_threshold
2480  *
2481  * This value informs the ECC logic of the number of 0's to count
2482  *
2483  * in a page before considering it as Erased. If the number of 0's in
2484  *
2485  * the page being read is less than the value in this register,
2486  *
2487  * an erased page is inferred and no un-correctable error will be flagged
2488  *
2489  * for that page. If ECC is disabled, the erased_page interrupt shall be
2490  *
2491  * set as explained above. If ECC is enabled, in addition to the above
2492  *
2493  * condition, only when the ECC logic detects an un-correctable error for
2494  *
2495  * that page will the erased_page interrupt be flagged. If the ECC logic
2496  *
2497  * detects a no-error or correctable error page, this erased page interrupt
2498  *
2499  * will not be set. A value of ZERO in this register will disabled checking for
2500  *
2501  * erased pages. Erased page detection logic will be activated only in MAIN or
2502  *
2503  * MAIN+SPARE or META-DATA(if available) modes of operation.
2504  *
2505  * Field Access Macros:
2506  *
2507  */
2508 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2509 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB 16
2510 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2511 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB 31
2512 /* The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2513 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH 16
2514 /* The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value. */
2515 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK 0xffff0000
2516 /* The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value. */
2517 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK 0x0000ffff
2518 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field. */
2519 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET 0x0
2520 /* Extracts the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD field value from a register. */
2521 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value) (((value) & 0xffff0000) >> 16)
2522 /* Produces a ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value suitable for setting the register. */
2523 #define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value) (((value) << 16) & 0xffff0000)
2524 
2525 #ifndef __ASSEMBLY__
2526 /*
2527  * WARNING: The C register and register group struct declarations are provided for
2528  * convenience and illustrative purposes. They should, however, be used with
2529  * caution as the C language standard provides no guarantees about the alignment or
2530  * atomicity of device memory accesses. The recommended practice for coding device
2531  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2532  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2533  * alt_write_dword() functions for 64 bit registers.
2534  *
2535  * The struct declaration for register ALT_NAND_CFG_ECC_CORRECTION.
2536  */
2537 struct ALT_NAND_CFG_ECC_CORRECTION_s
2538 {
2539  volatile uint32_t value : 8; /* ALT_NAND_CFG_ECC_CORRECTION_VALUE */
2540  uint32_t : 8; /* *UNDEFINED* */
2541  volatile uint32_t erase_threshold : 16; /* ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD */
2542 };
2543 
2544 /* The typedef declaration for register ALT_NAND_CFG_ECC_CORRECTION. */
2545 typedef struct ALT_NAND_CFG_ECC_CORRECTION_s ALT_NAND_CFG_ECC_CORRECTION_t;
2546 #endif /* __ASSEMBLY__ */
2547 
2548 /* The reset value of the ALT_NAND_CFG_ECC_CORRECTION register. */
2549 #define ALT_NAND_CFG_ECC_CORRECTION_RESET 0x00000008
2550 /* The byte offset of the ALT_NAND_CFG_ECC_CORRECTION register from the beginning of the component. */
2551 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2552 /* The address of the ALT_NAND_CFG_ECC_CORRECTION register. */
2553 #define ALT_NAND_CFG_ECC_CORRECTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_ECC_CORRECTION_OFST))
2554 
2555 /*
2556  * Register : read_mode
2557  *
2558  * The type of read sequence that the controller will follow for pipe read
2559  * commands.
2560  *
2561  * Register Layout
2562  *
2563  * Bits | Access | Reset | Description
2564  * :-------|:-------|:--------|:-----------------------------
2565  * [3:0] | RW | 0x0 | ALT_NAND_CFG_READ_MODE_VALUE
2566  * [31:4] | ??? | Unknown | *UNDEFINED*
2567  *
2568  */
2569 /*
2570  * Field : value
2571  *
2572  * The values in the field should be as follows[list]
2573  *
2574  * [*]4'h0 - This value informs the controller that the pipe read sequence to
2575  * follow is of
2576  *
2577  * a normal read.
2578  *
2579  * For 512 byte page devices, Normal read sequence is,
2580  *
2581  * C00, Address, Data, .....
2582  *
2583  * For devices with page size greater that 512 bytes, the sequence is,
2584  *
2585  * C00, Address, C30, Data.....
2586  *
2587  * [*]4'h1 - This value informs the controller that the pipe read sequence to
2588  * follow is of
2589  *
2590  * a Cache Read with the following sequence,
2591  *
2592  * C00, Address, C30, C31, Data, C31, Data, ....., C3F, Data.
2593  *
2594  * [*]4'h2 - This value informs the controller that the pipe read sequence to
2595  * follow is of
2596  *
2597  * a Cache Read with the following sequence,
2598  *
2599  * C00, Address, C31, Data, Data, ....., C34.
2600  *
2601  * [*]4'h3 - This value informs the controller that the pipe read sequence to
2602  * follow is of
2603  *
2604  * a 'N' Plane Read with the following sequence,
2605  *
2606  * C00, Address, C00, Address, C30, Data, C06, Address, CE0, Data.....
2607  *
2608  * [*]4'h4 - This value informs the controller that the pipe read sequence to
2609  * follow is of
2610  *
2611  * a 'N' Plane Read with the following sequence,
2612  *
2613  * C60, Address, C60, Address, C30, C00, Address, C05, Address, CE0, Data, C00,
2614  *
2615  * Address, C05, Address, CE0, Data.....
2616  *
2617  * [*]4'h5 - This value informs the controller that the pipe read sequence to
2618  * follow is of
2619  *
2620  * a 'N' Plane Cache Read with the following sequence,
2621  *
2622  * C60, Address, C60, Address, C30, C31, C00, Address, C05, Address, CE0, Data,
2623  *
2624  * C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,
2625  *
2626  * CE0, Data, C00, Address, C05, Address, CE0, Data
2627  *
2628  * [*]4'h6 - This value informs the controller that the pipe read sequence to
2629  * follow is of
2630  *
2631  * a 'N' Plane Read with the following sequence,
2632  *
2633  * C00, Address, C32, .., C00, Address, C30, C06, Address, CE0, Data,
2634  *
2635  * C06, Address, CE0, Data,....
2636  *
2637  * [*]4'h7 - This value informs the controller that the pipe read sequence to
2638  * follow is of
2639  *
2640  * a 'N' Plane Cache Read with the following sequence,
2641  *
2642  * C00, Address, C32,..., C00, Address, C30, C31,C06, Address, CE0, Data,
2643  *
2644  * C31, C06, Address, CE0, Data, C3F, C06, Address, CE0, Data....
2645  *
2646  * [*]4'h8 - This value informs the controller that the pipe read sequence to
2647  * follow is of
2648  *
2649  * a 'N' Plane Cache Read with the following sequence,
2650  *
2651  * C60, Address, C60, Address, C33, C31, C00, Address, C05, Address, CE0, Data,
2652  *
2653  * C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,
2654  *
2655  * CE0, Data, C00, Address, C05, Address, CE0, Data
2656  *
2657  * [*]4'h9 - 4'h15 - Reserved.
2658  *
2659  * [/list]
2660  *
2661  * ..... indicates that the previous sequence is repeated till the last page.
2662  *
2663  * Field Access Macros:
2664  *
2665  */
2666 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_READ_MODE_VALUE register field. */
2667 #define ALT_NAND_CFG_READ_MODE_VALUE_LSB 0
2668 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_READ_MODE_VALUE register field. */
2669 #define ALT_NAND_CFG_READ_MODE_VALUE_MSB 3
2670 /* The width in bits of the ALT_NAND_CFG_READ_MODE_VALUE register field. */
2671 #define ALT_NAND_CFG_READ_MODE_VALUE_WIDTH 4
2672 /* The mask used to set the ALT_NAND_CFG_READ_MODE_VALUE register field value. */
2673 #define ALT_NAND_CFG_READ_MODE_VALUE_SET_MSK 0x0000000f
2674 /* The mask used to clear the ALT_NAND_CFG_READ_MODE_VALUE register field value. */
2675 #define ALT_NAND_CFG_READ_MODE_VALUE_CLR_MSK 0xfffffff0
2676 /* The reset value of the ALT_NAND_CFG_READ_MODE_VALUE register field. */
2677 #define ALT_NAND_CFG_READ_MODE_VALUE_RESET 0x0
2678 /* Extracts the ALT_NAND_CFG_READ_MODE_VALUE field value from a register. */
2679 #define ALT_NAND_CFG_READ_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2680 /* Produces a ALT_NAND_CFG_READ_MODE_VALUE register field value suitable for setting the register. */
2681 #define ALT_NAND_CFG_READ_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2682 
2683 #ifndef __ASSEMBLY__
2684 /*
2685  * WARNING: The C register and register group struct declarations are provided for
2686  * convenience and illustrative purposes. They should, however, be used with
2687  * caution as the C language standard provides no guarantees about the alignment or
2688  * atomicity of device memory accesses. The recommended practice for coding device
2689  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2690  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2691  * alt_write_dword() functions for 64 bit registers.
2692  *
2693  * The struct declaration for register ALT_NAND_CFG_READ_MODE.
2694  */
2695 struct ALT_NAND_CFG_READ_MODE_s
2696 {
2697  volatile uint32_t value : 4; /* ALT_NAND_CFG_READ_MODE_VALUE */
2698  uint32_t : 28; /* *UNDEFINED* */
2699 };
2700 
2701 /* The typedef declaration for register ALT_NAND_CFG_READ_MODE. */
2702 typedef struct ALT_NAND_CFG_READ_MODE_s ALT_NAND_CFG_READ_MODE_t;
2703 #endif /* __ASSEMBLY__ */
2704 
2705 /* The reset value of the ALT_NAND_CFG_READ_MODE register. */
2706 #define ALT_NAND_CFG_READ_MODE_RESET 0x00000000
2707 /* The byte offset of the ALT_NAND_CFG_READ_MODE register from the beginning of the component. */
2708 #define ALT_NAND_CFG_READ_MODE_OFST 0x1c0
2709 /* The address of the ALT_NAND_CFG_READ_MODE register. */
2710 #define ALT_NAND_CFG_READ_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_READ_MODE_OFST))
2711 
2712 /*
2713  * Register : write_mode
2714  *
2715  * The type of write sequence that the controller will follow for pipe write
2716  * commands.
2717  *
2718  * Register Layout
2719  *
2720  * Bits | Access | Reset | Description
2721  * :-------|:-------|:--------|:------------------------------
2722  * [3:0] | RW | 0x0 | ALT_NAND_CFG_WRITE_MODE_VALUE
2723  * [31:4] | ??? | Unknown | *UNDEFINED*
2724  *
2725  */
2726 /*
2727  * Field : value
2728  *
2729  * The values in the field should be as follows[list]
2730  *
2731  * [*]4'h0 - This value informs the controller that the pipe write sequence to
2732  * follow is of
2733  *
2734  * a normal write with the following sequence,
2735  *
2736  * C80, Address, Data, C10.....
2737  *
2738  * [*]4'h1 - This value informs the controller that the pipe write sequence to
2739  * follow is of
2740  *
2741  * a Cache Program with the following sequence,
2742  *
2743  * C80, Address, Data, C15, ....., C80, Address, Data, C10.
2744  *
2745  * [*]4'h2 - This value informs the controller that the pipe write sequence to
2746  * follow is of
2747  *
2748  * a Two/Four Plane Program with the following sequence,
2749  *
2750  * C80, Address, Data, C11, C81, Address, Data, C10.....
2751  *
2752  * [*]4'h3 - This value informs the controller that the pipe write sequence to
2753  * follow is of
2754  *
2755  * a 'N' Plane Program with the following sequence,
2756  *
2757  * C80, Address, Data, C11, C80, Address, Data, C10.....
2758  *
2759  * [*]4'h4 - This value informs the controller that the pipe write sequence to
2760  * follow is of
2761  *
2762  * a 'N' Plane Cache Program with the following sequence,
2763  *
2764  * C80, Address, Data, C11, C80, Address, Data, C15.....C80, Address, Data, C11,
2765  *
2766  * C80, Address, Data, C10.
2767  *
2768  * [*]4'h5 - This value informs the controller that the pipe write sequence to
2769  * follow is of
2770  *
2771  * a 'N' Plane Cache Program with the following sequence,
2772  *
2773  * C80, Address, Data, C11, C81, Address, Data, C15.....C80, Address, Data, C11,
2774  *
2775  * C81, Address, Data, C10.
2776  *
2777  * [*]4'h6 - 4'h15 - Reserved.
2778  *
2779  * [/list]
2780  *
2781  * ..... indicates that the previous sequence is repeated till the last page.
2782  *
2783  * Field Access Macros:
2784  *
2785  */
2786 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WRITE_MODE_VALUE register field. */
2787 #define ALT_NAND_CFG_WRITE_MODE_VALUE_LSB 0
2788 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WRITE_MODE_VALUE register field. */
2789 #define ALT_NAND_CFG_WRITE_MODE_VALUE_MSB 3
2790 /* The width in bits of the ALT_NAND_CFG_WRITE_MODE_VALUE register field. */
2791 #define ALT_NAND_CFG_WRITE_MODE_VALUE_WIDTH 4
2792 /* The mask used to set the ALT_NAND_CFG_WRITE_MODE_VALUE register field value. */
2793 #define ALT_NAND_CFG_WRITE_MODE_VALUE_SET_MSK 0x0000000f
2794 /* The mask used to clear the ALT_NAND_CFG_WRITE_MODE_VALUE register field value. */
2795 #define ALT_NAND_CFG_WRITE_MODE_VALUE_CLR_MSK 0xfffffff0
2796 /* The reset value of the ALT_NAND_CFG_WRITE_MODE_VALUE register field. */
2797 #define ALT_NAND_CFG_WRITE_MODE_VALUE_RESET 0x0
2798 /* Extracts the ALT_NAND_CFG_WRITE_MODE_VALUE field value from a register. */
2799 #define ALT_NAND_CFG_WRITE_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2800 /* Produces a ALT_NAND_CFG_WRITE_MODE_VALUE register field value suitable for setting the register. */
2801 #define ALT_NAND_CFG_WRITE_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2802 
2803 #ifndef __ASSEMBLY__
2804 /*
2805  * WARNING: The C register and register group struct declarations are provided for
2806  * convenience and illustrative purposes. They should, however, be used with
2807  * caution as the C language standard provides no guarantees about the alignment or
2808  * atomicity of device memory accesses. The recommended practice for coding device
2809  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2810  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2811  * alt_write_dword() functions for 64 bit registers.
2812  *
2813  * The struct declaration for register ALT_NAND_CFG_WRITE_MODE.
2814  */
2815 struct ALT_NAND_CFG_WRITE_MODE_s
2816 {
2817  volatile uint32_t value : 4; /* ALT_NAND_CFG_WRITE_MODE_VALUE */
2818  uint32_t : 28; /* *UNDEFINED* */
2819 };
2820 
2821 /* The typedef declaration for register ALT_NAND_CFG_WRITE_MODE. */
2822 typedef struct ALT_NAND_CFG_WRITE_MODE_s ALT_NAND_CFG_WRITE_MODE_t;
2823 #endif /* __ASSEMBLY__ */
2824 
2825 /* The reset value of the ALT_NAND_CFG_WRITE_MODE register. */
2826 #define ALT_NAND_CFG_WRITE_MODE_RESET 0x00000000
2827 /* The byte offset of the ALT_NAND_CFG_WRITE_MODE register from the beginning of the component. */
2828 #define ALT_NAND_CFG_WRITE_MODE_OFST 0x1d0
2829 /* The address of the ALT_NAND_CFG_WRITE_MODE register. */
2830 #define ALT_NAND_CFG_WRITE_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WRITE_MODE_OFST))
2831 
2832 /*
2833  * Register : copyback_mode
2834  *
2835  * The type of copyback sequence that the controller will follow.
2836  *
2837  * Register Layout
2838  *
2839  * Bits | Access | Reset | Description
2840  * :-------|:-------|:--------|:---------------------------------
2841  * [3:0] | RW | 0x0 | ALT_NAND_CFG_COPYBACK_MODE_VALUE
2842  * [31:4] | ??? | Unknown | *UNDEFINED*
2843  *
2844  */
2845 /*
2846  * Field : value
2847  *
2848  * The values in the field should be as follows[list]
2849  *
2850  * [*]4'h0 - This value informs the controller that the copyback sequence to follow
2851  * is,
2852  *
2853  * C00, Address, C35, C85, Address, C10
2854  *
2855  * [*]4'h1 - This value informs the controller that the copyback sequence to follow
2856  * is,
2857  *
2858  * C00, Address, C30, C8C, Address, C10
2859  *
2860  * [*]4'h2 - This value informs the controller that the copyback sequence to follow
2861  * is,
2862  *
2863  * C00, Address, C8A, Address, C10
2864  *
2865  * [*]4'h3 - This value informs the controller that the copyback sequence to follow
2866  * is of
2867  *
2868  * a four plane copyback sequence,
2869  *
2870  * C00, Address, C03, Address, C03, Address, C03, Address, C8A, Address, C11,
2871  *
2872  * C8A, Address, C11, C8A, Address, C11, C8A, Address, C10.
2873  *
2874  * [*]4'h4 - This value informs the controller that the copyback sequence to follow
2875  * is of
2876  *
2877  * a two plane copyback sequence,
2878  *
2879  * C00, Address, C35, C00, Address, C35, C85, Address, C11, C81, Address, C10.
2880  *
2881  * [*]4'h5 - This value informs the controller that the copyback sequence to follow
2882  * is of
2883  *
2884  * a two plane copyback sequence,
2885  *
2886  * C60, Address, C60, Address, C35, C85, Address, C11, C81, Address, C10.
2887  *
2888  * [*]4'h6 - This value informs the controller that the copyback sequence to follow
2889  * is of
2890  *
2891  * a two plane copyback sequence,
2892  *
2893  * C00, Address, C00, Address, C35, C85, Address, C11, C80, Address, C10.
2894  *
2895  * [*]4'h7 - This value informs the controller that the copyback sequence to follow
2896  * is of
2897  *
2898  * a two plane copyback sequence,
2899  *
2900  * C60, Address, C60, Address, C30, C8C, Address, C11, C8C, Address, C10.
2901  *
2902  * [*]4'h8 - 4'h15 - Reserved.[/list]
2903  *
2904  * Field Access Macros:
2905  *
2906  */
2907 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field. */
2908 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_LSB 0
2909 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field. */
2910 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_MSB 3
2911 /* The width in bits of the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field. */
2912 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_WIDTH 4
2913 /* The mask used to set the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field value. */
2914 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_SET_MSK 0x0000000f
2915 /* The mask used to clear the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field value. */
2916 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_CLR_MSK 0xfffffff0
2917 /* The reset value of the ALT_NAND_CFG_COPYBACK_MODE_VALUE register field. */
2918 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_RESET 0x0
2919 /* Extracts the ALT_NAND_CFG_COPYBACK_MODE_VALUE field value from a register. */
2920 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2921 /* Produces a ALT_NAND_CFG_COPYBACK_MODE_VALUE register field value suitable for setting the register. */
2922 #define ALT_NAND_CFG_COPYBACK_MODE_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2923 
2924 #ifndef __ASSEMBLY__
2925 /*
2926  * WARNING: The C register and register group struct declarations are provided for
2927  * convenience and illustrative purposes. They should, however, be used with
2928  * caution as the C language standard provides no guarantees about the alignment or
2929  * atomicity of device memory accesses. The recommended practice for coding device
2930  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
2931  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
2932  * alt_write_dword() functions for 64 bit registers.
2933  *
2934  * The struct declaration for register ALT_NAND_CFG_COPYBACK_MODE.
2935  */
2936 struct ALT_NAND_CFG_COPYBACK_MODE_s
2937 {
2938  volatile uint32_t value : 4; /* ALT_NAND_CFG_COPYBACK_MODE_VALUE */
2939  uint32_t : 28; /* *UNDEFINED* */
2940 };
2941 
2942 /* The typedef declaration for register ALT_NAND_CFG_COPYBACK_MODE. */
2943 typedef struct ALT_NAND_CFG_COPYBACK_MODE_s ALT_NAND_CFG_COPYBACK_MODE_t;
2944 #endif /* __ASSEMBLY__ */
2945 
2946 /* The reset value of the ALT_NAND_CFG_COPYBACK_MODE register. */
2947 #define ALT_NAND_CFG_COPYBACK_MODE_RESET 0x00000000
2948 /* The byte offset of the ALT_NAND_CFG_COPYBACK_MODE register from the beginning of the component. */
2949 #define ALT_NAND_CFG_COPYBACK_MODE_OFST 0x1e0
2950 /* The address of the ALT_NAND_CFG_COPYBACK_MODE register. */
2951 #define ALT_NAND_CFG_COPYBACK_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_COPYBACK_MODE_OFST))
2952 
2953 /*
2954  * Register : rdwr_en_lo_cnt
2955  *
2956  * Read/Write Enable low pulse width
2957  *
2958  * Register Layout
2959  *
2960  * Bits | Access | Reset | Description
2961  * :-------|:-------|:--------|:----------------------------------
2962  * [4:0] | RW | 0x12 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE
2963  * [31:5] | ??? | Unknown | *UNDEFINED*
2964  *
2965  */
2966 /*
2967  * Field : value
2968  *
2969  * Number of clk_x cycles that read or write enable will kept low to meet the min
2970  *
2971  * Trp/Twp parameter of the device. The value in this register plus rdwr_en_hi_cnt
2972  *
2973  * register value should meet the min cycle time of the device connected. The
2974  * default
2975  *
2976  * value is calculated assuming the max clk_x time period of 4ns to work with ONFI
2977  *
2978  * Mode 0 mode of 100ns device cycle time. This assumes a 1x/5x clocking scheme.
2979  *
2980  * Field Access Macros:
2981  *
2982  */
2983 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2984 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2985 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2986 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2987 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2988 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2989 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2990 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2991 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value. */
2992 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2993 /* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field. */
2994 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2995 /* Extracts the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE field value from a register. */
2996 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2997 /* Produces a ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value suitable for setting the register. */
2998 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2999 
3000 #ifndef __ASSEMBLY__
3001 /*
3002  * WARNING: The C register and register group struct declarations are provided for
3003  * convenience and illustrative purposes. They should, however, be used with
3004  * caution as the C language standard provides no guarantees about the alignment or
3005  * atomicity of device memory accesses. The recommended practice for coding device
3006  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3007  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3008  * alt_write_dword() functions for 64 bit registers.
3009  *
3010  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT.
3011  */
3012 struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s
3013 {
3014  volatile uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE */
3015  uint32_t : 27; /* *UNDEFINED* */
3016 };
3017 
3018 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT. */
3019 typedef struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t;
3020 #endif /* __ASSEMBLY__ */
3021 
3022 /* The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT register. */
3023 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_RESET 0x00000012
3024 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_LO_CNT register from the beginning of the component. */
3025 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
3026 /* The address of the ALT_NAND_CFG_RDWR_EN_LO_CNT register. */
3027 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST))
3028 
3029 /*
3030  * Register : rdwr_en_hi_cnt
3031  *
3032  * Read/Write Enable high pulse width
3033  *
3034  * Register Layout
3035  *
3036  * Bits | Access | Reset | Description
3037  * :-------|:-------|:--------|:----------------------------------
3038  * [4:0] | RW | 0xc | ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE
3039  * [31:5] | ??? | Unknown | *UNDEFINED*
3040  *
3041  */
3042 /*
3043  * Field : value
3044  *
3045  * Number of clk_x cycles that read or write enable will kept high to meet the min
3046  *
3047  * Treh/Tweh parameter of the device. The value in this register plus
3048  * rdwr_en_lo_cnt
3049  *
3050  * register value should meet the min cycle time of the device connected. The
3051  * default
3052  *
3053  * value is calculated assuming the max clk_x time period of 4ns to work with ONFI
3054  *
3055  * Mode 0 mode of 100ns device cycle time. This assumes a 1x/5x clocking scheme.
3056  *
3057  * Field Access Macros:
3058  *
3059  */
3060 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
3061 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
3062 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
3063 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
3064 /* The width in bits of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
3065 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
3066 /* The mask used to set the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
3067 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
3068 /* The mask used to clear the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value. */
3069 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
3070 /* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field. */
3071 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
3072 /* Extracts the ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE field value from a register. */
3073 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3074 /* Produces a ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE register field value suitable for setting the register. */
3075 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3076 
3077 #ifndef __ASSEMBLY__
3078 /*
3079  * WARNING: The C register and register group struct declarations are provided for
3080  * convenience and illustrative purposes. They should, however, be used with
3081  * caution as the C language standard provides no guarantees about the alignment or
3082  * atomicity of device memory accesses. The recommended practice for coding device
3083  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3084  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3085  * alt_write_dword() functions for 64 bit registers.
3086  *
3087  * The struct declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT.
3088  */
3089 struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s
3090 {
3091  volatile uint32_t value : 5; /* ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE */
3092  uint32_t : 27; /* *UNDEFINED* */
3093 };
3094 
3095 /* The typedef declaration for register ALT_NAND_CFG_RDWR_EN_HI_CNT. */
3096 typedef struct ALT_NAND_CFG_RDWR_EN_HI_CNT_s ALT_NAND_CFG_RDWR_EN_HI_CNT_t;
3097 #endif /* __ASSEMBLY__ */
3098 
3099 /* The reset value of the ALT_NAND_CFG_RDWR_EN_HI_CNT register. */
3100 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_RESET 0x0000000c
3101 /* The byte offset of the ALT_NAND_CFG_RDWR_EN_HI_CNT register from the beginning of the component. */
3102 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
3103 /* The address of the ALT_NAND_CFG_RDWR_EN_HI_CNT register. */
3104 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST))
3105 
3106 /*
3107  * Register : max_rd_delay
3108  *
3109  * Max round trip read data delay for data capture
3110  *
3111  * Register Layout
3112  *
3113  * Bits | Access | Reset | Description
3114  * :-------|:-------|:--------|:--------------------------------
3115  * [3:0] | RW | 0x0 | ALT_NAND_CFG_MAX_RD_DELAY_VALUE
3116  * [31:4] | ??? | Unknown | *UNDEFINED*
3117  *
3118  */
3119 /*
3120  * Field : value
3121  *
3122  * Number of clk_x cycles after generation of feedback clk_x_out pulse when it is
3123  * safe
3124  *
3125  * to synchronize received data to clk_x domain. Data should have been registered
3126  * with
3127  *
3128  * clk_x_in and stable by the time max_rd_delay cycles has elapsed. Please see
3129  * timing
3130  *
3131  * diagram in bus interface timing section of this guide for further elaboration. A
3132  *
3133  * default value of zero will mean a value of clk_x multiple minus one.
3134  *
3135  * Field Access Macros:
3136  *
3137  */
3138 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3139 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
3140 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3141 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
3142 /* The width in bits of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3143 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
3144 /* The mask used to set the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
3145 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
3146 /* The mask used to clear the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value. */
3147 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
3148 /* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field. */
3149 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
3150 /* Extracts the ALT_NAND_CFG_MAX_RD_DELAY_VALUE field value from a register. */
3151 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
3152 /* Produces a ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value suitable for setting the register. */
3153 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
3154 
3155 #ifndef __ASSEMBLY__
3156 /*
3157  * WARNING: The C register and register group struct declarations are provided for
3158  * convenience and illustrative purposes. They should, however, be used with
3159  * caution as the C language standard provides no guarantees about the alignment or
3160  * atomicity of device memory accesses. The recommended practice for coding device
3161  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3162  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3163  * alt_write_dword() functions for 64 bit registers.
3164  *
3165  * The struct declaration for register ALT_NAND_CFG_MAX_RD_DELAY.
3166  */
3167 struct ALT_NAND_CFG_MAX_RD_DELAY_s
3168 {
3169  volatile uint32_t value : 4; /* ALT_NAND_CFG_MAX_RD_DELAY_VALUE */
3170  uint32_t : 28; /* *UNDEFINED* */
3171 };
3172 
3173 /* The typedef declaration for register ALT_NAND_CFG_MAX_RD_DELAY. */
3174 typedef struct ALT_NAND_CFG_MAX_RD_DELAY_s ALT_NAND_CFG_MAX_RD_DELAY_t;
3175 #endif /* __ASSEMBLY__ */
3176 
3177 /* The reset value of the ALT_NAND_CFG_MAX_RD_DELAY register. */
3178 #define ALT_NAND_CFG_MAX_RD_DELAY_RESET 0x00000000
3179 /* The byte offset of the ALT_NAND_CFG_MAX_RD_DELAY register from the beginning of the component. */
3180 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
3181 /* The address of the ALT_NAND_CFG_MAX_RD_DELAY register. */
3182 #define ALT_NAND_CFG_MAX_RD_DELAY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_MAX_RD_DELAY_OFST))
3183 
3184 /*
3185  * Register : cs_setup_cnt
3186  *
3187  * Chip select setup/tWB time
3188  *
3189  * Register Layout
3190  *
3191  * Bits | Access | Reset | Description
3192  * :--------|:-------|:--------|:--------------------------------
3193  * [4:0] | RW | 0x3 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE
3194  * [11:5] | ??? | Unknown | *UNDEFINED*
3195  * [17:12] | RW | 0xa | ALT_NAND_CFG_CS_SETUP_CNT_TWB
3196  * [31:18] | ??? | Unknown | *UNDEFINED*
3197  *
3198  */
3199 /*
3200  * Field : value
3201  *
3202  * Number of clk_x cycles required for meeting chip select setup time. This
3203  * register
3204  *
3205  * refers to device timing parameter Tcs. The value in this registers reflects the
3206  * extra
3207  *
3208  * setup cycles for chip select before read/write enable signal is set low. The
3209  * default value
3210  *
3211  * is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum clk_x period of 4ns
3212  * for
3213  *
3214  * 1x/5x clock multiple for 20ns cycle time device.
3215  *
3216  * Please refer to Figure 3.3 for the relationship between the cs_setup_cnt and
3217  * rdwr_en_lo_cnt values.
3218  *
3219  * Field Access Macros:
3220  *
3221  */
3222 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3223 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
3224 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3225 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
3226 /* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3227 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
3228 /* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
3229 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
3230 /* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value. */
3231 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
3232 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field. */
3233 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
3234 /* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_VALUE field value from a register. */
3235 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3236 /* Produces a ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value suitable for setting the register. */
3237 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3238 
3239 /*
3240  * Field : twb
3241  *
3242  * Number of clk_x cycles required for meeting the tWB time. This register
3243  *
3244  * refers to device timing parameter TWB.
3245  *
3246  * Field Access Macros:
3247  *
3248  */
3249 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3250 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12
3251 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3252 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17
3253 /* The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3254 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6
3255 /* The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value. */
3256 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000
3257 /* The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value. */
3258 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff
3259 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field. */
3260 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa
3261 /* Extracts the ALT_NAND_CFG_CS_SETUP_CNT_TWB field value from a register. */
3262 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12)
3263 /* Produces a ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value suitable for setting the register. */
3264 #define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000)
3265 
3266 #ifndef __ASSEMBLY__
3267 /*
3268  * WARNING: The C register and register group struct declarations are provided for
3269  * convenience and illustrative purposes. They should, however, be used with
3270  * caution as the C language standard provides no guarantees about the alignment or
3271  * atomicity of device memory accesses. The recommended practice for coding device
3272  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3273  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3274  * alt_write_dword() functions for 64 bit registers.
3275  *
3276  * The struct declaration for register ALT_NAND_CFG_CS_SETUP_CNT.
3277  */
3278 struct ALT_NAND_CFG_CS_SETUP_CNT_s
3279 {
3280  volatile uint32_t value : 5; /* ALT_NAND_CFG_CS_SETUP_CNT_VALUE */
3281  uint32_t : 7; /* *UNDEFINED* */
3282  volatile uint32_t twb : 6; /* ALT_NAND_CFG_CS_SETUP_CNT_TWB */
3283  uint32_t : 14; /* *UNDEFINED* */
3284 };
3285 
3286 /* The typedef declaration for register ALT_NAND_CFG_CS_SETUP_CNT. */
3287 typedef struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t;
3288 #endif /* __ASSEMBLY__ */
3289 
3290 /* The reset value of the ALT_NAND_CFG_CS_SETUP_CNT register. */
3291 #define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003
3292 /* The byte offset of the ALT_NAND_CFG_CS_SETUP_CNT register from the beginning of the component. */
3293 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
3294 /* The address of the ALT_NAND_CFG_CS_SETUP_CNT register. */
3295 #define ALT_NAND_CFG_CS_SETUP_CNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_CS_SETUP_CNT_OFST))
3296 
3297 /*
3298  * Register : spare_area_skip_bytes
3299  *
3300  * Spare area skip bytes
3301  *
3302  * Register Layout
3303  *
3304  * Bits | Access | Reset | Description
3305  * :-------|:-------|:--------|:-----------------------------------------
3306  * [5:0] | RW | 0x0 | ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE
3307  * [31:6] | ??? | Unknown | *UNDEFINED*
3308  *
3309  */
3310 /*
3311  * Field : value
3312  *
3313  * Number of bytes to skip from start of spare area before last ECC sector
3314  *
3315  * data starts. The bytes will be written with the value programmed in the
3316  *
3317  * spare_area_marker register. This register could be potentially used to
3318  *
3319  * preserve the bad block marker in the spare area by marking it good.
3320  *
3321  * The default value is zero which means no bytes will be skipped and
3322  *
3323  * last ECC sector will start from the beginning of spare area. This value
3324  *
3325  * should be an even number.
3326  *
3327  * Field Access Macros:
3328  *
3329  */
3330 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3331 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
3332 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3333 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
3334 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3335 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
3336 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
3337 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
3338 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value. */
3339 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
3340 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field. */
3341 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
3342 /* Extracts the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE field value from a register. */
3343 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3344 /* Produces a ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE register field value suitable for setting the register. */
3345 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3346 
3347 #ifndef __ASSEMBLY__
3348 /*
3349  * WARNING: The C register and register group struct declarations are provided for
3350  * convenience and illustrative purposes. They should, however, be used with
3351  * caution as the C language standard provides no guarantees about the alignment or
3352  * atomicity of device memory accesses. The recommended practice for coding device
3353  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3354  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3355  * alt_write_dword() functions for 64 bit registers.
3356  *
3357  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES.
3358  */
3359 struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
3360 {
3361  volatile uint32_t value : 6; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE */
3362  uint32_t : 26; /* *UNDEFINED* */
3363 };
3364 
3365 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES. */
3366 typedef struct ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t;
3367 #endif /* __ASSEMBLY__ */
3368 
3369 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register. */
3370 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_RESET 0x00000000
3371 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register from the beginning of the component. */
3372 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
3373 /* The address of the ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES register. */
3374 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST))
3375 
3376 /*
3377  * Register : spare_area_marker
3378  *
3379  * Spare area marker value
3380  *
3381  * Register Layout
3382  *
3383  * Bits | Access | Reset | Description
3384  * :--------|:-------|:--------|:-------------------------------------
3385  * [15:0] | RW | 0xffff | ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE
3386  * [31:16] | ??? | Unknown | *UNDEFINED*
3387  *
3388  */
3389 /*
3390  * Field : value
3391  *
3392  * A 16bit value that will be written in the spare area skip bytes. This value
3393  *
3394  * will be used by controller while in the MAIN mode of data transfer.
3395  *
3396  * Field Access Macros:
3397  *
3398  */
3399 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3400 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
3401 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3402 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
3403 /* The width in bits of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3404 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
3405 /* The mask used to set the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
3406 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
3407 /* The mask used to clear the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value. */
3408 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
3409 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field. */
3410 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
3411 /* Extracts the ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE field value from a register. */
3412 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3413 /* Produces a ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE register field value suitable for setting the register. */
3414 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3415 
3416 #ifndef __ASSEMBLY__
3417 /*
3418  * WARNING: The C register and register group struct declarations are provided for
3419  * convenience and illustrative purposes. They should, however, be used with
3420  * caution as the C language standard provides no guarantees about the alignment or
3421  * atomicity of device memory accesses. The recommended practice for coding device
3422  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3423  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3424  * alt_write_dword() functions for 64 bit registers.
3425  *
3426  * The struct declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER.
3427  */
3428 struct ALT_NAND_CFG_SPARE_AREA_MARKER_s
3429 {
3430  volatile uint32_t value : 16; /* ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE */
3431  uint32_t : 16; /* *UNDEFINED* */
3432 };
3433 
3434 /* The typedef declaration for register ALT_NAND_CFG_SPARE_AREA_MARKER. */
3435 typedef struct ALT_NAND_CFG_SPARE_AREA_MARKER_s ALT_NAND_CFG_SPARE_AREA_MARKER_t;
3436 #endif /* __ASSEMBLY__ */
3437 
3438 /* The reset value of the ALT_NAND_CFG_SPARE_AREA_MARKER register. */
3439 #define ALT_NAND_CFG_SPARE_AREA_MARKER_RESET 0x0000ffff
3440 /* The byte offset of the ALT_NAND_CFG_SPARE_AREA_MARKER register from the beginning of the component. */
3441 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
3442 /* The address of the ALT_NAND_CFG_SPARE_AREA_MARKER register. */
3443 #define ALT_NAND_CFG_SPARE_AREA_MARKER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_SPARE_AREA_MARKER_OFST))
3444 
3445 /*
3446  * Register : devices_connected
3447  *
3448  * Number of Devices connected on one bank
3449  *
3450  * Register Layout
3451  *
3452  * Bits | Access | Reset | Description
3453  * :-------|:-------|:--------|:-------------------------------------
3454  * [2:0] | RW | 0x0 | ALT_NAND_CFG_DEVICES_CONNECTED_VALUE
3455  * [31:3] | ??? | Unknown | *UNDEFINED*
3456  *
3457  */
3458 /*
3459  * Field : value
3460  *
3461  * Indicates the number of devices connected to a bank. At POR, the value loaded
3462  *
3463  * is the maximum possible devices that could be connected in this configuration.
3464  *
3465  * Field Access Macros:
3466  *
3467  */
3468 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3469 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
3470 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3471 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
3472 /* The width in bits of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3473 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
3474 /* The mask used to set the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
3475 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
3476 /* The mask used to clear the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value. */
3477 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
3478 /* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field. */
3479 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
3480 /* Extracts the ALT_NAND_CFG_DEVICES_CONNECTED_VALUE field value from a register. */
3481 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
3482 /* Produces a ALT_NAND_CFG_DEVICES_CONNECTED_VALUE register field value suitable for setting the register. */
3483 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
3484 
3485 #ifndef __ASSEMBLY__
3486 /*
3487  * WARNING: The C register and register group struct declarations are provided for
3488  * convenience and illustrative purposes. They should, however, be used with
3489  * caution as the C language standard provides no guarantees about the alignment or
3490  * atomicity of device memory accesses. The recommended practice for coding device
3491  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3492  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3493  * alt_write_dword() functions for 64 bit registers.
3494  *
3495  * The struct declaration for register ALT_NAND_CFG_DEVICES_CONNECTED.
3496  */
3497 struct ALT_NAND_CFG_DEVICES_CONNECTED_s
3498 {
3499  volatile uint32_t value : 3; /* ALT_NAND_CFG_DEVICES_CONNECTED_VALUE */
3500  uint32_t : 29; /* *UNDEFINED* */
3501 };
3502 
3503 /* The typedef declaration for register ALT_NAND_CFG_DEVICES_CONNECTED. */
3504 typedef struct ALT_NAND_CFG_DEVICES_CONNECTED_s ALT_NAND_CFG_DEVICES_CONNECTED_t;
3505 #endif /* __ASSEMBLY__ */
3506 
3507 /* The reset value of the ALT_NAND_CFG_DEVICES_CONNECTED register. */
3508 #define ALT_NAND_CFG_DEVICES_CONNECTED_RESET 0x00000000
3509 /* The byte offset of the ALT_NAND_CFG_DEVICES_CONNECTED register from the beginning of the component. */
3510 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
3511 /* The address of the ALT_NAND_CFG_DEVICES_CONNECTED register. */
3512 #define ALT_NAND_CFG_DEVICES_CONNECTED_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DEVICES_CONNECTED_OFST))
3513 
3514 /*
3515  * Register : die_mask
3516  *
3517  * Indicates the die differentiator in case of NAND devices with stacked dies.
3518  *
3519  * Register Layout
3520  *
3521  * Bits | Access | Reset | Description
3522  * :--------|:-------|:--------|:----------------------------
3523  * [15:0] | RW | 0x0 | ALT_NAND_CFG_DIE_MASK_VALUE
3524  * [31:16] | ??? | Unknown | *UNDEFINED*
3525  *
3526  */
3527 /*
3528  * Field : value
3529  *
3530  * The die_mask register information will be used for devices having address
3531  * restrictions.
3532  *
3533  * For example, in certain Samsung devices, when the first address in a two-plane
3534  * command
3535  *
3536  * is being sent, it is expected that the address is all zeros. But if the NAND
3537  * device
3538  *
3539  * internally has multiple dies stacked, the die information (MSB of final row
3540  * address) has
3541  *
3542  * to be sent.
3543  *
3544  * The value programmed in this register will be used to mask the address while
3545  * sending
3546  *
3547  * out the last row address.
3548  *
3549  * Field Access Macros:
3550  *
3551  */
3552 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DIE_MASK_VALUE register field. */
3553 #define ALT_NAND_CFG_DIE_MASK_VALUE_LSB 0
3554 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DIE_MASK_VALUE register field. */
3555 #define ALT_NAND_CFG_DIE_MASK_VALUE_MSB 15
3556 /* The width in bits of the ALT_NAND_CFG_DIE_MASK_VALUE register field. */
3557 #define ALT_NAND_CFG_DIE_MASK_VALUE_WIDTH 16
3558 /* The mask used to set the ALT_NAND_CFG_DIE_MASK_VALUE register field value. */
3559 #define ALT_NAND_CFG_DIE_MASK_VALUE_SET_MSK 0x0000ffff
3560 /* The mask used to clear the ALT_NAND_CFG_DIE_MASK_VALUE register field value. */
3561 #define ALT_NAND_CFG_DIE_MASK_VALUE_CLR_MSK 0xffff0000
3562 /* The reset value of the ALT_NAND_CFG_DIE_MASK_VALUE register field. */
3563 #define ALT_NAND_CFG_DIE_MASK_VALUE_RESET 0x0
3564 /* Extracts the ALT_NAND_CFG_DIE_MASK_VALUE field value from a register. */
3565 #define ALT_NAND_CFG_DIE_MASK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3566 /* Produces a ALT_NAND_CFG_DIE_MASK_VALUE register field value suitable for setting the register. */
3567 #define ALT_NAND_CFG_DIE_MASK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3568 
3569 #ifndef __ASSEMBLY__
3570 /*
3571  * WARNING: The C register and register group struct declarations are provided for
3572  * convenience and illustrative purposes. They should, however, be used with
3573  * caution as the C language standard provides no guarantees about the alignment or
3574  * atomicity of device memory accesses. The recommended practice for coding device
3575  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3576  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3577  * alt_write_dword() functions for 64 bit registers.
3578  *
3579  * The struct declaration for register ALT_NAND_CFG_DIE_MASK.
3580  */
3581 struct ALT_NAND_CFG_DIE_MASK_s
3582 {
3583  volatile uint32_t value : 16; /* ALT_NAND_CFG_DIE_MASK_VALUE */
3584  uint32_t : 16; /* *UNDEFINED* */
3585 };
3586 
3587 /* The typedef declaration for register ALT_NAND_CFG_DIE_MASK. */
3588 typedef struct ALT_NAND_CFG_DIE_MASK_s ALT_NAND_CFG_DIE_MASK_t;
3589 #endif /* __ASSEMBLY__ */
3590 
3591 /* The reset value of the ALT_NAND_CFG_DIE_MASK register. */
3592 #define ALT_NAND_CFG_DIE_MASK_RESET 0x00000000
3593 /* The byte offset of the ALT_NAND_CFG_DIE_MASK register from the beginning of the component. */
3594 #define ALT_NAND_CFG_DIE_MASK_OFST 0x260
3595 /* The address of the ALT_NAND_CFG_DIE_MASK register. */
3596 #define ALT_NAND_CFG_DIE_MASK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_DIE_MASK_OFST))
3597 
3598 /*
3599  * Register : first_block_of_next_plane
3600  *
3601  * The starting block address of the next plane in a multi plane device.
3602  *
3603  * Register Layout
3604  *
3605  * Bits | Access | Reset | Description
3606  * :--------|:-------|:--------|:---------------------------------------------
3607  * [15:0] | RW | 0x1 | ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE
3608  * [31:16] | ??? | Unknown | *UNDEFINED*
3609  *
3610  */
3611 /*
3612  * Field : value
3613  *
3614  * This values informs the controller of the plane structure of the device.
3615  *
3616  * In case the device is a multi plane device and the value here is 1, the
3617  *
3618  * controller understands that the next plane starts from Block number 1
3619  *
3620  * and in conjunction with the number of planes parameter can decide upon the
3621  *
3622  * distribution of blocks in a plane in the device.
3623  *
3624  * Field Access Macros:
3625  *
3626  */
3627 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3628 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3629 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3630 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3631 /* The width in bits of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3632 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3633 /* The mask used to set the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3634 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3635 /* The mask used to clear the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value. */
3636 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3637 /* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field. */
3638 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3639 /* Extracts the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE field value from a register. */
3640 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3641 /* Produces a ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE register field value suitable for setting the register. */
3642 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3643 
3644 #ifndef __ASSEMBLY__
3645 /*
3646  * WARNING: The C register and register group struct declarations are provided for
3647  * convenience and illustrative purposes. They should, however, be used with
3648  * caution as the C language standard provides no guarantees about the alignment or
3649  * atomicity of device memory accesses. The recommended practice for coding device
3650  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3651  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3652  * alt_write_dword() functions for 64 bit registers.
3653  *
3654  * The struct declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE.
3655  */
3656 struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3657 {
3658  volatile uint32_t value : 16; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE */
3659  uint32_t : 16; /* *UNDEFINED* */
3660 };
3661 
3662 /* The typedef declaration for register ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE. */
3663 typedef struct ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t;
3664 #endif /* __ASSEMBLY__ */
3665 
3666 /* The reset value of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register. */
3667 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_RESET 0x00000001
3668 /* The byte offset of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register from the beginning of the component. */
3669 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3670 /* The address of the ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE register. */
3671 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST))
3672 
3673 /*
3674  * Register : write_protect
3675  *
3676  * This register is used to control the assertion/de-assertion of the WP# pin to
3677  * the device.
3678  *
3679  * Register Layout
3680  *
3681  * Bits | Access | Reset | Description
3682  * :-------|:-------|:--------|:--------------------------------
3683  * [0] | RW | 0x1 | ALT_NAND_CFG_WRITE_PROTECT_FLAG
3684  * [31:1] | ??? | Unknown | *UNDEFINED*
3685  *
3686  */
3687 /*
3688  * Field : flag
3689  *
3690  * When the controller is in reset, the WP# pin is always asserted to the device.
3691  * Once the
3692  *
3693  * reset is removed, the WP# is de-asserted. The software will then have to come
3694  * and program
3695  *
3696  * this bit to assert/de-assert the same.
3697  *
3698  * [list][*]1 - Write protect de-assert [*]0 - Write protect assert[/list]
3699  *
3700  * Field Access Macros:
3701  *
3702  */
3703 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field. */
3704 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_LSB 0
3705 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field. */
3706 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_MSB 0
3707 /* The width in bits of the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field. */
3708 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_WIDTH 1
3709 /* The mask used to set the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field value. */
3710 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_SET_MSK 0x00000001
3711 /* The mask used to clear the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field value. */
3712 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_CLR_MSK 0xfffffffe
3713 /* The reset value of the ALT_NAND_CFG_WRITE_PROTECT_FLAG register field. */
3714 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_RESET 0x1
3715 /* Extracts the ALT_NAND_CFG_WRITE_PROTECT_FLAG field value from a register. */
3716 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3717 /* Produces a ALT_NAND_CFG_WRITE_PROTECT_FLAG register field value suitable for setting the register. */
3718 #define ALT_NAND_CFG_WRITE_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3719 
3720 #ifndef __ASSEMBLY__
3721 /*
3722  * WARNING: The C register and register group struct declarations are provided for
3723  * convenience and illustrative purposes. They should, however, be used with
3724  * caution as the C language standard provides no guarantees about the alignment or
3725  * atomicity of device memory accesses. The recommended practice for coding device
3726  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3727  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3728  * alt_write_dword() functions for 64 bit registers.
3729  *
3730  * The struct declaration for register ALT_NAND_CFG_WRITE_PROTECT.
3731  */
3732 struct ALT_NAND_CFG_WRITE_PROTECT_s
3733 {
3734  volatile uint32_t flag : 1; /* ALT_NAND_CFG_WRITE_PROTECT_FLAG */
3735  uint32_t : 31; /* *UNDEFINED* */
3736 };
3737 
3738 /* The typedef declaration for register ALT_NAND_CFG_WRITE_PROTECT. */
3739 typedef struct ALT_NAND_CFG_WRITE_PROTECT_s ALT_NAND_CFG_WRITE_PROTECT_t;
3740 #endif /* __ASSEMBLY__ */
3741 
3742 /* The reset value of the ALT_NAND_CFG_WRITE_PROTECT register. */
3743 #define ALT_NAND_CFG_WRITE_PROTECT_RESET 0x00000001
3744 /* The byte offset of the ALT_NAND_CFG_WRITE_PROTECT register from the beginning of the component. */
3745 #define ALT_NAND_CFG_WRITE_PROTECT_OFST 0x280
3746 /* The address of the ALT_NAND_CFG_WRITE_PROTECT register. */
3747 #define ALT_NAND_CFG_WRITE_PROTECT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WRITE_PROTECT_OFST))
3748 
3749 /*
3750  * Register : re_2_re
3751  *
3752  * Timing parameter between re high to re low (Trhz) for the next bank
3753  *
3754  * Register Layout
3755  *
3756  * Bits | Access | Reset | Description
3757  * :-------|:-------|:--------|:---------------------------
3758  * [5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_RE_VALUE
3759  * [31:6] | ??? | Unknown | *UNDEFINED*
3760  *
3761  */
3762 /*
3763  * Field : value
3764  *
3765  * Signifies the number of bus interface clk_x clocks that should be introduced
3766  * between
3767  *
3768  * read enable going high to a bank to the read enable going low to the next bank.
3769  * The number
3770  *
3771  * of clocks is the function of device parameter Trhz and controller clock
3772  * frequency.
3773  *
3774  * Field Access Macros:
3775  *
3776  */
3777 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3778 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3779 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3780 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3781 /* The width in bits of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3782 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3783 /* The mask used to set the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3784 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3785 /* The mask used to clear the ALT_NAND_CFG_RE_2_RE_VALUE register field value. */
3786 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3787 /* The reset value of the ALT_NAND_CFG_RE_2_RE_VALUE register field. */
3788 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3789 /* Extracts the ALT_NAND_CFG_RE_2_RE_VALUE field value from a register. */
3790 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3791 /* Produces a ALT_NAND_CFG_RE_2_RE_VALUE register field value suitable for setting the register. */
3792 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3793 
3794 #ifndef __ASSEMBLY__
3795 /*
3796  * WARNING: The C register and register group struct declarations are provided for
3797  * convenience and illustrative purposes. They should, however, be used with
3798  * caution as the C language standard provides no guarantees about the alignment or
3799  * atomicity of device memory accesses. The recommended practice for coding device
3800  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3801  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3802  * alt_write_dword() functions for 64 bit registers.
3803  *
3804  * The struct declaration for register ALT_NAND_CFG_RE_2_RE.
3805  */
3806 struct ALT_NAND_CFG_RE_2_RE_s
3807 {
3808  volatile uint32_t value : 6; /* ALT_NAND_CFG_RE_2_RE_VALUE */
3809  uint32_t : 26; /* *UNDEFINED* */
3810 };
3811 
3812 /* The typedef declaration for register ALT_NAND_CFG_RE_2_RE. */
3813 typedef struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t;
3814 #endif /* __ASSEMBLY__ */
3815 
3816 /* The reset value of the ALT_NAND_CFG_RE_2_RE register. */
3817 #define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032
3818 /* The byte offset of the ALT_NAND_CFG_RE_2_RE register from the beginning of the component. */
3819 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3820 /* The address of the ALT_NAND_CFG_RE_2_RE register. */
3821 #define ALT_NAND_CFG_RE_2_RE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_RE_2_RE_OFST))
3822 
3823 /*
3824  * Register : por_reset_count
3825  *
3826  * The number of cycles the controller waits after POR to issue the first RESET
3827  * command
3828  *
3829  * to the device.
3830  *
3831  * Register Layout
3832  *
3833  * Bits | Access | Reset | Description
3834  * :--------|:-------|:--------|:-----------------------------------
3835  * [15:0] | RW | 0x13b | ALT_NAND_CFG_POR_RESET_COUNT_VALUE
3836  * [31:16] | ??? | Unknown | *UNDEFINED*
3837  *
3838  */
3839 /*
3840  * Field : value
3841  *
3842  * The controller waits for this number of cycles before issuing the first
3843  *
3844  * RESET command to the device. The number in this register is multiplied
3845  *
3846  * internally by 16 in the controller to form the final reset wait count.
3847  *
3848  * Field Access Macros:
3849  *
3850  */
3851 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field. */
3852 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_LSB 0
3853 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field. */
3854 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_MSB 15
3855 /* The width in bits of the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field. */
3856 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_WIDTH 16
3857 /* The mask used to set the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field value. */
3858 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_SET_MSK 0x0000ffff
3859 /* The mask used to clear the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field value. */
3860 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_CLR_MSK 0xffff0000
3861 /* The reset value of the ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field. */
3862 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_RESET 0x13b
3863 /* Extracts the ALT_NAND_CFG_POR_RESET_COUNT_VALUE field value from a register. */
3864 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3865 /* Produces a ALT_NAND_CFG_POR_RESET_COUNT_VALUE register field value suitable for setting the register. */
3866 #define ALT_NAND_CFG_POR_RESET_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3867 
3868 #ifndef __ASSEMBLY__
3869 /*
3870  * WARNING: The C register and register group struct declarations are provided for
3871  * convenience and illustrative purposes. They should, however, be used with
3872  * caution as the C language standard provides no guarantees about the alignment or
3873  * atomicity of device memory accesses. The recommended practice for coding device
3874  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3875  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3876  * alt_write_dword() functions for 64 bit registers.
3877  *
3878  * The struct declaration for register ALT_NAND_CFG_POR_RESET_COUNT.
3879  */
3880 struct ALT_NAND_CFG_POR_RESET_COUNT_s
3881 {
3882  volatile uint32_t value : 16; /* ALT_NAND_CFG_POR_RESET_COUNT_VALUE */
3883  uint32_t : 16; /* *UNDEFINED* */
3884 };
3885 
3886 /* The typedef declaration for register ALT_NAND_CFG_POR_RESET_COUNT. */
3887 typedef struct ALT_NAND_CFG_POR_RESET_COUNT_s ALT_NAND_CFG_POR_RESET_COUNT_t;
3888 #endif /* __ASSEMBLY__ */
3889 
3890 /* The reset value of the ALT_NAND_CFG_POR_RESET_COUNT register. */
3891 #define ALT_NAND_CFG_POR_RESET_COUNT_RESET 0x0000013b
3892 /* The byte offset of the ALT_NAND_CFG_POR_RESET_COUNT register from the beginning of the component. */
3893 #define ALT_NAND_CFG_POR_RESET_COUNT_OFST 0x2a0
3894 /* The address of the ALT_NAND_CFG_POR_RESET_COUNT register. */
3895 #define ALT_NAND_CFG_POR_RESET_COUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_POR_RESET_COUNT_OFST))
3896 
3897 /*
3898  * Register : watchdog_reset_count
3899  *
3900  * The number of cycles the controller waits before flagging a
3901  *
3902  * watchdog timeout interrupt.
3903  *
3904  * Register Layout
3905  *
3906  * Bits | Access | Reset | Description
3907  * :--------|:-------|:--------|:----------------------------------------
3908  * [15:0] | RW | 0x5b9a | ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE
3909  * [31:16] | ??? | Unknown | *UNDEFINED*
3910  *
3911  */
3912 /*
3913  * Field : value
3914  *
3915  * The controller waits for this number of cycles before issuing
3916  *
3917  * a watchdog timeout interrupt. The value in this register is
3918  *
3919  * multiplied internally by 32 in the controller to form the final
3920  *
3921  * watchdog counter.
3922  *
3923  * Field Access Macros:
3924  *
3925  */
3926 /* The Least Significant Bit (LSB) position of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field. */
3927 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_LSB 0
3928 /* The Most Significant Bit (MSB) position of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field. */
3929 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_MSB 15
3930 /* The width in bits of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field. */
3931 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_WIDTH 16
3932 /* The mask used to set the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field value. */
3933 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_SET_MSK 0x0000ffff
3934 /* The mask used to clear the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field value. */
3935 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_CLR_MSK 0xffff0000
3936 /* The reset value of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field. */
3937 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_RESET 0x5b9a
3938 /* Extracts the ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE field value from a register. */
3939 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3940 /* Produces a ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE register field value suitable for setting the register. */
3941 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3942 
3943 #ifndef __ASSEMBLY__
3944 /*
3945  * WARNING: The C register and register group struct declarations are provided for
3946  * convenience and illustrative purposes. They should, however, be used with
3947  * caution as the C language standard provides no guarantees about the alignment or
3948  * atomicity of device memory accesses. The recommended practice for coding device
3949  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3950  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3951  * alt_write_dword() functions for 64 bit registers.
3952  *
3953  * The struct declaration for register ALT_NAND_CFG_WATCHDOG_RESET_COUNT.
3954  */
3955 struct ALT_NAND_CFG_WATCHDOG_RESET_COUNT_s
3956 {
3957  volatile uint32_t value : 16; /* ALT_NAND_CFG_WATCHDOG_RESET_COUNT_VALUE */
3958  uint32_t : 16; /* *UNDEFINED* */
3959 };
3960 
3961 /* The typedef declaration for register ALT_NAND_CFG_WATCHDOG_RESET_COUNT. */
3962 typedef struct ALT_NAND_CFG_WATCHDOG_RESET_COUNT_s ALT_NAND_CFG_WATCHDOG_RESET_COUNT_t;
3963 #endif /* __ASSEMBLY__ */
3964 
3965 /* The reset value of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT register. */
3966 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_RESET 0x00005b9a
3967 /* The byte offset of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT register from the beginning of the component. */
3968 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_OFST 0x2b0
3969 /* The address of the ALT_NAND_CFG_WATCHDOG_RESET_COUNT register. */
3970 #define ALT_NAND_CFG_WATCHDOG_RESET_COUNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_CFG_WATCHDOG_RESET_COUNT_OFST))
3971 
3972 #ifndef __ASSEMBLY__
3973 /*
3974  * WARNING: The C register and register group struct declarations are provided for
3975  * convenience and illustrative purposes. They should, however, be used with
3976  * caution as the C language standard provides no guarantees about the alignment or
3977  * atomicity of device memory accesses. The recommended practice for coding device
3978  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
3979  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
3980  * alt_write_dword() functions for 64 bit registers.
3981  *
3982  * The struct declaration for register group ALT_NAND_CFG.
3983  */
3984 struct ALT_NAND_CFG_s
3985 {
3986  volatile ALT_NAND_CFG_DEVICE_RESET_t device_reset; /* ALT_NAND_CFG_DEVICE_RESET */
3987  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
3988  volatile ALT_NAND_CFG_TRANSFER_SPARE_REG_t transfer_spare_reg; /* ALT_NAND_CFG_TRANSFER_SPARE_REG */
3989  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
3990  volatile ALT_NAND_CFG_LOAD_WAIT_CNT_t load_wait_cnt; /* ALT_NAND_CFG_LOAD_WAIT_CNT */
3991  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
3992  volatile ALT_NAND_CFG_PROGRAM_WAIT_CNT_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
3993  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
3994  volatile ALT_NAND_CFG_ERASE_WAIT_CNT_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
3995  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
3996  volatile ALT_NAND_CFG_INT_MON_CYCCNT_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
3997  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
3998  volatile ALT_NAND_CFG_RB_PIN_ENABLED_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_ENABLED */
3999  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
4000  volatile ALT_NAND_CFG_MULTIPLANE_OPERATION_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OPERATION */
4001  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
4002  volatile ALT_NAND_CFG_MULTIPLANE_READ_ENABLE_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_READ_ENABLE */
4003  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
4004  volatile ALT_NAND_CFG_COPYBACK_DISABLE_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DISABLE */
4005  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
4006  volatile ALT_NAND_CFG_CACHE_WRITE_ENABLE_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WRITE_ENABLE */
4007  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
4008  volatile ALT_NAND_CFG_CACHE_READ_ENABLE_t cache_read_enable; /* ALT_NAND_CFG_CACHE_READ_ENABLE */
4009  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
4010  volatile ALT_NAND_CFG_PREFETCH_MODE_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MODE */
4011  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
4012  volatile ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE */
4013  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
4014  volatile ALT_NAND_CFG_ECC_ENABLE_t ecc_enable; /* ALT_NAND_CFG_ECC_ENABLE */
4015  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
4016  volatile ALT_NAND_CFG_GLOBAL_INT_ENABLE_t global_int_enable; /* ALT_NAND_CFG_GLOBAL_INT_ENABLE */
4017  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
4018  volatile ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
4019  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
4020  volatile ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
4021  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
4022  volatile ALT_NAND_CFG_RE_2_WE_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
4023  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
4024  volatile ALT_NAND_CFG_ACC_CLKS_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
4025  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
4026  volatile ALT_NAND_CFG_NUMBER_OF_PLANES_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
4027  volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
4028  volatile ALT_NAND_CFG_PAGES_PER_BLOCK_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
4029  volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
4030  volatile ALT_NAND_CFG_DEVICE_WIDTH_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
4031  volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
4032  volatile ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
4033  volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
4034  volatile ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
4035  volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
4036  volatile ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
4037  volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
4038  volatile ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
4039  volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
4040  volatile ALT_NAND_CFG_ECC_CORRECTION_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
4041  volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
4042  volatile ALT_NAND_CFG_READ_MODE_t read_mode; /* ALT_NAND_CFG_READ_MODE */
4043  volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
4044  volatile ALT_NAND_CFG_WRITE_MODE_t write_mode; /* ALT_NAND_CFG_WRITE_MODE */
4045  volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
4046  volatile ALT_NAND_CFG_COPYBACK_MODE_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MODE */
4047  volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
4048  volatile ALT_NAND_CFG_RDWR_EN_LO_CNT_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
4049  volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
4050  volatile ALT_NAND_CFG_RDWR_EN_HI_CNT_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
4051  volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
4052  volatile ALT_NAND_CFG_MAX_RD_DELAY_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
4053  volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
4054  volatile ALT_NAND_CFG_CS_SETUP_CNT_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
4055  volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
4056  volatile ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
4057  volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
4058  volatile ALT_NAND_CFG_SPARE_AREA_MARKER_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
4059  volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
4060  volatile ALT_NAND_CFG_DEVICES_CONNECTED_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
4061  volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
4062  volatile ALT_NAND_CFG_DIE_MASK_t die_mask; /* ALT_NAND_CFG_DIE_MASK */
4063  volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
4064  volatile ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
4065  volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
4066  volatile ALT_NAND_CFG_WRITE_PROTECT_t write_protect; /* ALT_NAND_CFG_WRITE_PROTECT */
4067  volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
4068  volatile ALT_NAND_CFG_RE_2_RE_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
4069  volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
4070  volatile ALT_NAND_CFG_POR_RESET_COUNT_t por_reset_count; /* ALT_NAND_CFG_POR_RESET_COUNT */
4071  volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
4072  volatile ALT_NAND_CFG_WATCHDOG_RESET_COUNT_t watchdog_reset_count; /* ALT_NAND_CFG_WATCHDOG_RESET_COUNT */
4073 };
4074 
4075 /* The typedef declaration for register group ALT_NAND_CFG. */
4076 typedef struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
4077 /* The struct declaration for the raw register contents of register group ALT_NAND_CFG. */
4078 struct ALT_NAND_CFG_raw_s
4079 {
4080  volatile uint32_t device_reset; /* ALT_NAND_CFG_DEVICE_RESET */
4081  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
4082  volatile uint32_t transfer_spare_reg; /* ALT_NAND_CFG_TRANSFER_SPARE_REG */
4083  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
4084  volatile uint32_t load_wait_cnt; /* ALT_NAND_CFG_LOAD_WAIT_CNT */
4085  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
4086  volatile uint32_t program_wait_cnt; /* ALT_NAND_CFG_PROGRAM_WAIT_CNT */
4087  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
4088  volatile uint32_t erase_wait_cnt; /* ALT_NAND_CFG_ERASE_WAIT_CNT */
4089  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
4090  volatile uint32_t int_mon_cyccnt; /* ALT_NAND_CFG_INT_MON_CYCCNT */
4091  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
4092  volatile uint32_t rb_pin_enabled; /* ALT_NAND_CFG_RB_PIN_ENABLED */
4093  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
4094  volatile uint32_t multiplane_operation; /* ALT_NAND_CFG_MULTIPLANE_OPERATION */
4095  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
4096  volatile uint32_t multiplane_read_enable; /* ALT_NAND_CFG_MULTIPLANE_READ_ENABLE */
4097  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
4098  volatile uint32_t copyback_disable; /* ALT_NAND_CFG_COPYBACK_DISABLE */
4099  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
4100  volatile uint32_t cache_write_enable; /* ALT_NAND_CFG_CACHE_WRITE_ENABLE */
4101  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
4102  volatile uint32_t cache_read_enable; /* ALT_NAND_CFG_CACHE_READ_ENABLE */
4103  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
4104  volatile uint32_t prefetch_mode; /* ALT_NAND_CFG_PREFETCH_MODE */
4105  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
4106  volatile uint32_t chip_enable_dont_care; /* ALT_NAND_CFG_CHIP_ENABLE_DONT_CARE */
4107  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
4108  volatile uint32_t ecc_enable; /* ALT_NAND_CFG_ECC_ENABLE */
4109  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
4110  volatile uint32_t global_int_enable; /* ALT_NAND_CFG_GLOBAL_INT_ENABLE */
4111  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
4112  volatile uint32_t twhr2_and_we_2_re; /* ALT_NAND_CFG_TWHR2_AND_WE_2_RE */
4113  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
4114  volatile uint32_t tcwaw_and_addr_2_data; /* ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA */
4115  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
4116  volatile uint32_t re_2_we; /* ALT_NAND_CFG_RE_2_WE */
4117  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
4118  volatile uint32_t acc_clks; /* ALT_NAND_CFG_ACC_CLKS */
4119  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
4120  volatile uint32_t number_of_planes; /* ALT_NAND_CFG_NUMBER_OF_PLANES */
4121  volatile uint32_t _pad_0x144_0x14f[3]; /* *UNDEFINED* */
4122  volatile uint32_t pages_per_block; /* ALT_NAND_CFG_PAGES_PER_BLOCK */
4123  volatile uint32_t _pad_0x154_0x15f[3]; /* *UNDEFINED* */
4124  volatile uint32_t device_width; /* ALT_NAND_CFG_DEVICE_WIDTH */
4125  volatile uint32_t _pad_0x164_0x16f[3]; /* *UNDEFINED* */
4126  volatile uint32_t device_main_area_size; /* ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE */
4127  volatile uint32_t _pad_0x174_0x17f[3]; /* *UNDEFINED* */
4128  volatile uint32_t device_spare_area_size; /* ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE */
4129  volatile uint32_t _pad_0x184_0x18f[3]; /* *UNDEFINED* */
4130  volatile uint32_t two_row_addr_cycles; /* ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES */
4131  volatile uint32_t _pad_0x194_0x19f[3]; /* *UNDEFINED* */
4132  volatile uint32_t multiplane_addr_restrict; /* ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT */
4133  volatile uint32_t _pad_0x1a4_0x1af[3]; /* *UNDEFINED* */
4134  volatile uint32_t ecc_correction; /* ALT_NAND_CFG_ECC_CORRECTION */
4135  volatile uint32_t _pad_0x1b4_0x1bf[3]; /* *UNDEFINED* */
4136  volatile uint32_t read_mode; /* ALT_NAND_CFG_READ_MODE */
4137  volatile uint32_t _pad_0x1c4_0x1cf[3]; /* *UNDEFINED* */
4138  volatile uint32_t write_mode; /* ALT_NAND_CFG_WRITE_MODE */
4139  volatile uint32_t _pad_0x1d4_0x1df[3]; /* *UNDEFINED* */
4140  volatile uint32_t copyback_mode; /* ALT_NAND_CFG_COPYBACK_MODE */
4141  volatile uint32_t _pad_0x1e4_0x1ef[3]; /* *UNDEFINED* */
4142  volatile uint32_t rdwr_en_lo_cnt; /* ALT_NAND_CFG_RDWR_EN_LO_CNT */
4143  volatile uint32_t _pad_0x1f4_0x1ff[3]; /* *UNDEFINED* */
4144  volatile uint32_t rdwr_en_hi_cnt; /* ALT_NAND_CFG_RDWR_EN_HI_CNT */
4145  volatile uint32_t _pad_0x204_0x20f[3]; /* *UNDEFINED* */
4146  volatile uint32_t max_rd_delay; /* ALT_NAND_CFG_MAX_RD_DELAY */
4147  volatile uint32_t _pad_0x214_0x21f[3]; /* *UNDEFINED* */
4148  volatile uint32_t cs_setup_cnt; /* ALT_NAND_CFG_CS_SETUP_CNT */
4149  volatile uint32_t _pad_0x224_0x22f[3]; /* *UNDEFINED* */
4150  volatile uint32_t spare_area_skip_bytes; /* ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES */
4151  volatile uint32_t _pad_0x234_0x23f[3]; /* *UNDEFINED* */
4152  volatile uint32_t spare_area_marker; /* ALT_NAND_CFG_SPARE_AREA_MARKER */
4153  volatile uint32_t _pad_0x244_0x24f[3]; /* *UNDEFINED* */
4154  volatile uint32_t devices_connected; /* ALT_NAND_CFG_DEVICES_CONNECTED */
4155  volatile uint32_t _pad_0x254_0x25f[3]; /* *UNDEFINED* */
4156  volatile uint32_t die_mask; /* ALT_NAND_CFG_DIE_MASK */
4157  volatile uint32_t _pad_0x264_0x26f[3]; /* *UNDEFINED* */
4158  volatile uint32_t first_block_of_next_plane; /* ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE */
4159  volatile uint32_t _pad_0x274_0x27f[3]; /* *UNDEFINED* */
4160  volatile uint32_t write_protect; /* ALT_NAND_CFG_WRITE_PROTECT */
4161  volatile uint32_t _pad_0x284_0x28f[3]; /* *UNDEFINED* */
4162  volatile uint32_t re_2_re; /* ALT_NAND_CFG_RE_2_RE */
4163  volatile uint32_t _pad_0x294_0x29f[3]; /* *UNDEFINED* */
4164  volatile uint32_t por_reset_count; /* ALT_NAND_CFG_POR_RESET_COUNT */
4165  volatile uint32_t _pad_0x2a4_0x2af[3]; /* *UNDEFINED* */
4166  volatile uint32_t watchdog_reset_count; /* ALT_NAND_CFG_WATCHDOG_RESET_COUNT */
4167 };
4168 
4169 /* The typedef declaration for the raw register contents of register group ALT_NAND_CFG. */
4170 typedef struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
4171 #endif /* __ASSEMBLY__ */
4172 
4173 
4174 /*
4175  * Component : Device parameters - NAND_PARAM
4176  * Device parameters
4177  *
4178  * Controller reads device parameters after initialization and stores
4179  *
4180  * in the following registers for software
4181  *
4182  */
4183 /*
4184  * Register : manufacturer_id
4185  *
4186  * Register Layout
4187  *
4188  * Bits | Access | Reset | Description
4189  * :-------|:-------|:--------|:-------------------------------------
4190  * [7:0] | RW | 0x0 | ALT_NAND_PARAM_MANUFACTURER_ID_VALUE
4191  * [31:8] | ??? | Unknown | *UNDEFINED*
4192  *
4193  */
4194 /*
4195  * Field : value
4196  *
4197  * Manufacturer ID
4198  *
4199  * Field Access Macros:
4200  *
4201  */
4202 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4203 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
4204 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4205 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
4206 /* The width in bits of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4207 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
4208 /* The mask used to set the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
4209 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
4210 /* The mask used to clear the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value. */
4211 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
4212 /* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field. */
4213 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
4214 /* Extracts the ALT_NAND_PARAM_MANUFACTURER_ID_VALUE field value from a register. */
4215 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4216 /* Produces a ALT_NAND_PARAM_MANUFACTURER_ID_VALUE register field value suitable for setting the register. */
4217 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4218 
4219 #ifndef __ASSEMBLY__
4220 /*
4221  * WARNING: The C register and register group struct declarations are provided for
4222  * convenience and illustrative purposes. They should, however, be used with
4223  * caution as the C language standard provides no guarantees about the alignment or
4224  * atomicity of device memory accesses. The recommended practice for coding device
4225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4227  * alt_write_dword() functions for 64 bit registers.
4228  *
4229  * The struct declaration for register ALT_NAND_PARAM_MANUFACTURER_ID.
4230  */
4231 struct ALT_NAND_PARAM_MANUFACTURER_ID_s
4232 {
4233  volatile uint32_t value : 8; /* ALT_NAND_PARAM_MANUFACTURER_ID_VALUE */
4234  uint32_t : 24; /* *UNDEFINED* */
4235 };
4236 
4237 /* The typedef declaration for register ALT_NAND_PARAM_MANUFACTURER_ID. */
4238 typedef struct ALT_NAND_PARAM_MANUFACTURER_ID_s ALT_NAND_PARAM_MANUFACTURER_ID_t;
4239 #endif /* __ASSEMBLY__ */
4240 
4241 /* The reset value of the ALT_NAND_PARAM_MANUFACTURER_ID register. */
4242 #define ALT_NAND_PARAM_MANUFACTURER_ID_RESET 0x00000000
4243 /* The byte offset of the ALT_NAND_PARAM_MANUFACTURER_ID register from the beginning of the component. */
4244 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
4245 /* The address of the ALT_NAND_PARAM_MANUFACTURER_ID register. */
4246 #define ALT_NAND_PARAM_MANUFACTURER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_MANUFACTURER_ID_OFST))
4247 
4248 /*
4249  * Register : device_id
4250  *
4251  * Register Layout
4252  *
4253  * Bits | Access | Reset | Description
4254  * :-------|:-------|:--------|:-------------------------------
4255  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_ID_VALUE
4256  * [31:8] | ??? | Unknown | *UNDEFINED*
4257  *
4258  */
4259 /*
4260  * Field : value
4261  *
4262  * Device ID
4263  *
4264  * Field Access Macros:
4265  *
4266  */
4267 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4268 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
4269 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4270 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
4271 /* The width in bits of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4272 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
4273 /* The mask used to set the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
4274 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
4275 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_ID_VALUE register field value. */
4276 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
4277 /* The reset value of the ALT_NAND_PARAM_DEVICE_ID_VALUE register field. */
4278 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
4279 /* Extracts the ALT_NAND_PARAM_DEVICE_ID_VALUE field value from a register. */
4280 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4281 /* Produces a ALT_NAND_PARAM_DEVICE_ID_VALUE register field value suitable for setting the register. */
4282 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4283 
4284 #ifndef __ASSEMBLY__
4285 /*
4286  * WARNING: The C register and register group struct declarations are provided for
4287  * convenience and illustrative purposes. They should, however, be used with
4288  * caution as the C language standard provides no guarantees about the alignment or
4289  * atomicity of device memory accesses. The recommended practice for coding device
4290  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4291  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4292  * alt_write_dword() functions for 64 bit registers.
4293  *
4294  * The struct declaration for register ALT_NAND_PARAM_DEVICE_ID.
4295  */
4296 struct ALT_NAND_PARAM_DEVICE_ID_s
4297 {
4298  const volatile uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_ID_VALUE */
4299  uint32_t : 24; /* *UNDEFINED* */
4300 };
4301 
4302 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_ID. */
4303 typedef struct ALT_NAND_PARAM_DEVICE_ID_s ALT_NAND_PARAM_DEVICE_ID_t;
4304 #endif /* __ASSEMBLY__ */
4305 
4306 /* The reset value of the ALT_NAND_PARAM_DEVICE_ID register. */
4307 #define ALT_NAND_PARAM_DEVICE_ID_RESET 0x00000000
4308 /* The byte offset of the ALT_NAND_PARAM_DEVICE_ID register from the beginning of the component. */
4309 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
4310 /* The address of the ALT_NAND_PARAM_DEVICE_ID register. */
4311 #define ALT_NAND_PARAM_DEVICE_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_ID_OFST))
4312 
4313 /*
4314  * Register : device_param_0
4315  *
4316  * Register Layout
4317  *
4318  * Bits | Access | Reset | Description
4319  * :-------|:-------|:--------|:------------------------------------
4320  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE
4321  * [31:8] | ??? | Unknown | *UNDEFINED*
4322  *
4323  */
4324 /*
4325  * Field : value
4326  *
4327  * 3rd byte relating to Device Signature. This register is
4328  *
4329  * updated only for Legacy NAND devices.
4330  *
4331  * Field Access Macros:
4332  *
4333  */
4334 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4335 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
4336 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4337 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
4338 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4339 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
4340 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
4341 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
4342 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value. */
4343 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
4344 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field. */
4345 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
4346 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE field value from a register. */
4347 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4348 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE register field value suitable for setting the register. */
4349 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4350 
4351 #ifndef __ASSEMBLY__
4352 /*
4353  * WARNING: The C register and register group struct declarations are provided for
4354  * convenience and illustrative purposes. They should, however, be used with
4355  * caution as the C language standard provides no guarantees about the alignment or
4356  * atomicity of device memory accesses. The recommended practice for coding device
4357  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4358  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4359  * alt_write_dword() functions for 64 bit registers.
4360  *
4361  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0.
4362  */
4363 struct ALT_NAND_PARAM_DEVICE_PARAM_0_s
4364 {
4365  const volatile uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE */
4366  uint32_t : 24; /* *UNDEFINED* */
4367 };
4368 
4369 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_0. */
4370 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_0_s ALT_NAND_PARAM_DEVICE_PARAM_0_t;
4371 #endif /* __ASSEMBLY__ */
4372 
4373 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_0 register. */
4374 #define ALT_NAND_PARAM_DEVICE_PARAM_0_RESET 0x00000000
4375 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_0 register from the beginning of the component. */
4376 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
4377 /* The address of the ALT_NAND_PARAM_DEVICE_PARAM_0 register. */
4378 #define ALT_NAND_PARAM_DEVICE_PARAM_0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_0_OFST))
4379 
4380 /*
4381  * Register : device_param_1
4382  *
4383  * Register Layout
4384  *
4385  * Bits | Access | Reset | Description
4386  * :-------|:-------|:--------|:------------------------------------
4387  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE
4388  * [31:8] | ??? | Unknown | *UNDEFINED*
4389  *
4390  */
4391 /*
4392  * Field : value
4393  *
4394  * 4th byte relating to Device Signature. This register is
4395  *
4396  * updated only for Legacy NAND devices.
4397  *
4398  * Field Access Macros:
4399  *
4400  */
4401 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4402 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
4403 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4404 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
4405 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4406 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
4407 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
4408 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
4409 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value. */
4410 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
4411 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field. */
4412 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
4413 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE field value from a register. */
4414 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4415 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE register field value suitable for setting the register. */
4416 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4417 
4418 #ifndef __ASSEMBLY__
4419 /*
4420  * WARNING: The C register and register group struct declarations are provided for
4421  * convenience and illustrative purposes. They should, however, be used with
4422  * caution as the C language standard provides no guarantees about the alignment or
4423  * atomicity of device memory accesses. The recommended practice for coding device
4424  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4425  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4426  * alt_write_dword() functions for 64 bit registers.
4427  *
4428  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1.
4429  */
4430 struct ALT_NAND_PARAM_DEVICE_PARAM_1_s
4431 {
4432  const volatile uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE */
4433  uint32_t : 24; /* *UNDEFINED* */
4434 };
4435 
4436 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_1. */
4437 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_1_s ALT_NAND_PARAM_DEVICE_PARAM_1_t;
4438 #endif /* __ASSEMBLY__ */
4439 
4440 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_1 register. */
4441 #define ALT_NAND_PARAM_DEVICE_PARAM_1_RESET 0x00000000
4442 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_1 register from the beginning of the component. */
4443 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
4444 /* The address of the ALT_NAND_PARAM_DEVICE_PARAM_1 register. */
4445 #define ALT_NAND_PARAM_DEVICE_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_1_OFST))
4446 
4447 /*
4448  * Register : device_param_2
4449  *
4450  * Register Layout
4451  *
4452  * Bits | Access | Reset | Description
4453  * :-------|:-------|:--------|:------------------------------------
4454  * [7:0] | R | 0x0 | ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE
4455  * [31:8] | ??? | Unknown | *UNDEFINED*
4456  *
4457  */
4458 /*
4459  * Field : value
4460  *
4461  * Reserved.
4462  *
4463  * Field Access Macros:
4464  *
4465  */
4466 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4467 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
4468 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4469 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
4470 /* The width in bits of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4471 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
4472 /* The mask used to set the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
4473 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
4474 /* The mask used to clear the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value. */
4475 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
4476 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field. */
4477 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
4478 /* Extracts the ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE field value from a register. */
4479 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4480 /* Produces a ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE register field value suitable for setting the register. */
4481 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4482 
4483 #ifndef __ASSEMBLY__
4484 /*
4485  * WARNING: The C register and register group struct declarations are provided for
4486  * convenience and illustrative purposes. They should, however, be used with
4487  * caution as the C language standard provides no guarantees about the alignment or
4488  * atomicity of device memory accesses. The recommended practice for coding device
4489  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4490  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4491  * alt_write_dword() functions for 64 bit registers.
4492  *
4493  * The struct declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2.
4494  */
4495 struct ALT_NAND_PARAM_DEVICE_PARAM_2_s
4496 {
4497  const volatile uint32_t value : 8; /* ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE */
4498  uint32_t : 24; /* *UNDEFINED* */
4499 };
4500 
4501 /* The typedef declaration for register ALT_NAND_PARAM_DEVICE_PARAM_2. */
4502 typedef struct ALT_NAND_PARAM_DEVICE_PARAM_2_s ALT_NAND_PARAM_DEVICE_PARAM_2_t;
4503 #endif /* __ASSEMBLY__ */
4504 
4505 /* The reset value of the ALT_NAND_PARAM_DEVICE_PARAM_2 register. */
4506 #define ALT_NAND_PARAM_DEVICE_PARAM_2_RESET 0x00000000
4507 /* The byte offset of the ALT_NAND_PARAM_DEVICE_PARAM_2 register from the beginning of the component. */
4508 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
4509 /* The address of the ALT_NAND_PARAM_DEVICE_PARAM_2 register. */
4510 #define ALT_NAND_PARAM_DEVICE_PARAM_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_DEVICE_PARAM_2_OFST))
4511 
4512 /*
4513  * Register : logical_page_data_size
4514  *
4515  * Logical page data area size in bytes
4516  *
4517  * Register Layout
4518  *
4519  * Bits | Access | Reset | Description
4520  * :--------|:-------|:--------|:--------------------------------------------
4521  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE
4522  * [31:16] | ??? | Unknown | *UNDEFINED*
4523  *
4524  */
4525 /*
4526  * Field : value
4527  *
4528  * Logical page spare area size in bytes. If multiple devices are
4529  *
4530  * connected on a single chip select, physical page data size will be
4531  *
4532  * multiplied by the number of devices to arrive at logical page size.
4533  *
4534  * Field Access Macros:
4535  *
4536  */
4537 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4538 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
4539 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4540 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
4541 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4542 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
4543 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
4544 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
4545 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value. */
4546 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
4547 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field. */
4548 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
4549 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE field value from a register. */
4550 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4551 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE register field value suitable for setting the register. */
4552 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4553 
4554 #ifndef __ASSEMBLY__
4555 /*
4556  * WARNING: The C register and register group struct declarations are provided for
4557  * convenience and illustrative purposes. They should, however, be used with
4558  * caution as the C language standard provides no guarantees about the alignment or
4559  * atomicity of device memory accesses. The recommended practice for coding device
4560  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4561  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4562  * alt_write_dword() functions for 64 bit registers.
4563  *
4564  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE.
4565  */
4566 struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
4567 {
4568  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE */
4569  uint32_t : 16; /* *UNDEFINED* */
4570 };
4571 
4572 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE. */
4573 typedef struct ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t;
4574 #endif /* __ASSEMBLY__ */
4575 
4576 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register. */
4577 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_RESET 0x00000000
4578 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register from the beginning of the component. */
4579 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
4580 /* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE register. */
4581 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST))
4582 
4583 /*
4584  * Register : logical_page_spare_size
4585  *
4586  * Logical page data area size in bytes
4587  *
4588  * Register Layout
4589  *
4590  * Bits | Access | Reset | Description
4591  * :--------|:-------|:--------|:---------------------------------------------
4592  * [15:0] | R | 0x0 | ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE
4593  * [31:16] | ??? | Unknown | *UNDEFINED*
4594  *
4595  */
4596 /*
4597  * Field : value
4598  *
4599  * Logical page spare area size in bytes. If multiple devices are
4600  *
4601  * connected on a single chip select, physical page spare size will be
4602  *
4603  * multiplied by the number of devices to arrive at logical page size.
4604  *
4605  * Field Access Macros:
4606  *
4607  */
4608 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4609 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
4610 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4611 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
4612 /* The width in bits of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4613 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
4614 /* The mask used to set the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
4615 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
4616 /* The mask used to clear the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value. */
4617 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
4618 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field. */
4619 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
4620 /* Extracts the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE field value from a register. */
4621 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4622 /* Produces a ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE register field value suitable for setting the register. */
4623 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4624 
4625 #ifndef __ASSEMBLY__
4626 /*
4627  * WARNING: The C register and register group struct declarations are provided for
4628  * convenience and illustrative purposes. They should, however, be used with
4629  * caution as the C language standard provides no guarantees about the alignment or
4630  * atomicity of device memory accesses. The recommended practice for coding device
4631  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4632  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4633  * alt_write_dword() functions for 64 bit registers.
4634  *
4635  * The struct declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE.
4636  */
4637 struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
4638 {
4639  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE */
4640  uint32_t : 16; /* *UNDEFINED* */
4641 };
4642 
4643 /* The typedef declaration for register ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE. */
4644 typedef struct ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t;
4645 #endif /* __ASSEMBLY__ */
4646 
4647 /* The reset value of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register. */
4648 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_RESET 0x00000000
4649 /* The byte offset of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register from the beginning of the component. */
4650 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
4651 /* The address of the ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE register. */
4652 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST))
4653 
4654 /*
4655  * Register : revision
4656  *
4657  * Controller Revision
4658  *
4659  * Register Layout
4660  *
4661  * Bits | Access | Reset | Description
4662  * :--------|:-------|:--------|:------------------------------
4663  * [7:0] | R | 0x5 | ALT_NAND_PARAM_REVISION_VALUE
4664  * [15:8] | R | 0x1 | ALT_NAND_PARAM_REVISION_MINOR
4665  * [31:16] | ??? | Unknown | *UNDEFINED*
4666  *
4667  */
4668 /*
4669  * Field : value
4670  *
4671  * The Major revision number of the controller
4672  *
4673  * Field Access Macros:
4674  *
4675  */
4676 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4677 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
4678 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4679 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 7
4680 /* The width in bits of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4681 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 8
4682 /* The mask used to set the ALT_NAND_PARAM_REVISION_VALUE register field value. */
4683 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x000000ff
4684 /* The mask used to clear the ALT_NAND_PARAM_REVISION_VALUE register field value. */
4685 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffffff00
4686 /* The reset value of the ALT_NAND_PARAM_REVISION_VALUE register field. */
4687 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
4688 /* Extracts the ALT_NAND_PARAM_REVISION_VALUE field value from a register. */
4689 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4690 /* Produces a ALT_NAND_PARAM_REVISION_VALUE register field value suitable for setting the register. */
4691 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4692 
4693 /*
4694  * Field : minor
4695  *
4696  * The Minor revision number of the controller
4697  *
4698  * Field Access Macros:
4699  *
4700  */
4701 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4702 #define ALT_NAND_PARAM_REVISION_MINOR_LSB 8
4703 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4704 #define ALT_NAND_PARAM_REVISION_MINOR_MSB 15
4705 /* The width in bits of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4706 #define ALT_NAND_PARAM_REVISION_MINOR_WIDTH 8
4707 /* The mask used to set the ALT_NAND_PARAM_REVISION_MINOR register field value. */
4708 #define ALT_NAND_PARAM_REVISION_MINOR_SET_MSK 0x0000ff00
4709 /* The mask used to clear the ALT_NAND_PARAM_REVISION_MINOR register field value. */
4710 #define ALT_NAND_PARAM_REVISION_MINOR_CLR_MSK 0xffff00ff
4711 /* The reset value of the ALT_NAND_PARAM_REVISION_MINOR register field. */
4712 #define ALT_NAND_PARAM_REVISION_MINOR_RESET 0x1
4713 /* Extracts the ALT_NAND_PARAM_REVISION_MINOR field value from a register. */
4714 #define ALT_NAND_PARAM_REVISION_MINOR_GET(value) (((value) & 0x0000ff00) >> 8)
4715 /* Produces a ALT_NAND_PARAM_REVISION_MINOR register field value suitable for setting the register. */
4716 #define ALT_NAND_PARAM_REVISION_MINOR_SET(value) (((value) << 8) & 0x0000ff00)
4717 
4718 #ifndef __ASSEMBLY__
4719 /*
4720  * WARNING: The C register and register group struct declarations are provided for
4721  * convenience and illustrative purposes. They should, however, be used with
4722  * caution as the C language standard provides no guarantees about the alignment or
4723  * atomicity of device memory accesses. The recommended practice for coding device
4724  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4725  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4726  * alt_write_dword() functions for 64 bit registers.
4727  *
4728  * The struct declaration for register ALT_NAND_PARAM_REVISION.
4729  */
4730 struct ALT_NAND_PARAM_REVISION_s
4731 {
4732  const volatile uint32_t value : 8; /* ALT_NAND_PARAM_REVISION_VALUE */
4733  const volatile uint32_t minor : 8; /* ALT_NAND_PARAM_REVISION_MINOR */
4734  uint32_t : 16; /* *UNDEFINED* */
4735 };
4736 
4737 /* The typedef declaration for register ALT_NAND_PARAM_REVISION. */
4738 typedef struct ALT_NAND_PARAM_REVISION_s ALT_NAND_PARAM_REVISION_t;
4739 #endif /* __ASSEMBLY__ */
4740 
4741 /* The reset value of the ALT_NAND_PARAM_REVISION register. */
4742 #define ALT_NAND_PARAM_REVISION_RESET 0x00000105
4743 /* The byte offset of the ALT_NAND_PARAM_REVISION register from the beginning of the component. */
4744 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4745 /* The address of the ALT_NAND_PARAM_REVISION register. */
4746 #define ALT_NAND_PARAM_REVISION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_REVISION_OFST))
4747 
4748 /*
4749  * Register : onfi_device_features
4750  *
4751  * Features supported by the connected ONFI device
4752  *
4753  * Register Layout
4754  *
4755  * Bits | Access | Reset | Description
4756  * :--------|:-------|:--------|:------------------------------------------
4757  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE
4758  * [31:16] | ??? | Unknown | *UNDEFINED*
4759  *
4760  */
4761 /*
4762  * Field : value
4763  *
4764  * The values in the field should be interpreted as follows[list]
4765  *
4766  * [*]Bit 0 - Supports 16 bit data bus width.
4767  *
4768  * [*]Bit 1 - Supports multiple LUN operations.
4769  *
4770  * [*]Bit 2 - Supports non-sequential page programming.
4771  *
4772  * [*]Bit 3 - Supports interleaved program and erase operations.
4773  *
4774  * [*]Bit 4 - Supports odd to even page copyback.
4775  *
4776  * [*]Bit 5 - Supports source synchronous.
4777  *
4778  * [*]Bit 6 - Supports interleaved read operations.
4779  *
4780  * [*]Bit 7 - Supports extended parameter page.
4781  *
4782  * [*]Bit 8 - Supports program page register clear enhancement.
4783  *
4784  * [*]Bit 9 - Supports EZNAND.
4785  *
4786  * [*]Bit 10 - Supports NV-DDR2.
4787  *
4788  * [*]Bit 11 - Supports Volume Addressing.
4789  *
4790  * [*]Bit 12 - Supports External Vpp.
4791  *
4792  * [*]Bit 13-15 - Reserved.[/list]
4793  *
4794  * Field Access Macros:
4795  *
4796  */
4797 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field. */
4798 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_LSB 0
4799 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field. */
4800 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_MSB 15
4801 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field. */
4802 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_WIDTH 16
4803 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field value. */
4804 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_SET_MSK 0x0000ffff
4805 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field value. */
4806 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_CLR_MSK 0xffff0000
4807 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field. */
4808 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_RESET 0x0
4809 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE field value from a register. */
4810 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4811 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE register field value suitable for setting the register. */
4812 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4813 
4814 #ifndef __ASSEMBLY__
4815 /*
4816  * WARNING: The C register and register group struct declarations are provided for
4817  * convenience and illustrative purposes. They should, however, be used with
4818  * caution as the C language standard provides no guarantees about the alignment or
4819  * atomicity of device memory accesses. The recommended practice for coding device
4820  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4821  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4822  * alt_write_dword() functions for 64 bit registers.
4823  *
4824  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEVICE_FEATURES.
4825  */
4826 struct ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_s
4827 {
4828  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_VALUE */
4829  uint32_t : 16; /* *UNDEFINED* */
4830 };
4831 
4832 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEVICE_FEATURES. */
4833 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_s ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_t;
4834 #endif /* __ASSEMBLY__ */
4835 
4836 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES register. */
4837 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_RESET 0x00000000
4838 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES register from the beginning of the component. */
4839 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_OFST 0x80
4840 /* The address of the ALT_NAND_PARAM_ONFI_DEVICE_FEATURES register. */
4841 #define ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_OFST))
4842 
4843 /*
4844  * Register : onfi_optional_commands
4845  *
4846  * Optional commands supported by the connected ONFI device
4847  *
4848  * Register Layout
4849  *
4850  * Bits | Access | Reset | Description
4851  * :--------|:-------|:--------|:--------------------------------------------
4852  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE
4853  * [31:16] | ??? | Unknown | *UNDEFINED*
4854  *
4855  */
4856 /*
4857  * Field : value
4858  *
4859  * The values in the field should be interpreted as follows[list]
4860  *
4861  * [*]Bit 0 - Supports page cache program command.
4862  *
4863  * [*]Bit 1 - Supports read cache commands.
4864  *
4865  * [*]Bit 2 - Supports get and set features.
4866  *
4867  * [*]Bit 3 - Supports read status enhanced commands.
4868  *
4869  * [*]Bit 4 - Supports copyback.
4870  *
4871  * [*]Bit 5 - Supports Read Unique Id.
4872  *
4873  * [*]Bit 6 - Supports Change Read Column Enhanced.
4874  *
4875  * [*]Bit 7 - Supports change row address.
4876  *
4877  * [*]Bit 8 - Supports Change small data move.
4878  *
4879  * [*]Bit 9 - Supports RESET LUN.
4880  *
4881  * [*]Bit 10 - Supports Volume Select.
4882  *
4883  * [*]Bit 11 - Supports ODT Configure.
4884  *
4885  * [*]Bit 12-15 - Reserved.[/list]
4886  *
4887  * Field Access Macros:
4888  *
4889  */
4890 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field. */
4891 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_LSB 0
4892 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field. */
4893 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_MSB 15
4894 /* The width in bits of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field. */
4895 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_WIDTH 16
4896 /* The mask used to set the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field value. */
4897 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_SET_MSK 0x0000ffff
4898 /* The mask used to clear the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field value. */
4899 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_CLR_MSK 0xffff0000
4900 /* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field. */
4901 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_RESET 0x0
4902 /* Extracts the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE field value from a register. */
4903 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4904 /* Produces a ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE register field value suitable for setting the register. */
4905 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4906 
4907 #ifndef __ASSEMBLY__
4908 /*
4909  * WARNING: The C register and register group struct declarations are provided for
4910  * convenience and illustrative purposes. They should, however, be used with
4911  * caution as the C language standard provides no guarantees about the alignment or
4912  * atomicity of device memory accesses. The recommended practice for coding device
4913  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4914  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4915  * alt_write_dword() functions for 64 bit registers.
4916  *
4917  * The struct declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS.
4918  */
4919 struct ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_s
4920 {
4921  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_VALUE */
4922  uint32_t : 16; /* *UNDEFINED* */
4923 };
4924 
4925 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS. */
4926 typedef struct ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_s ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_t;
4927 #endif /* __ASSEMBLY__ */
4928 
4929 /* The reset value of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS register. */
4930 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_RESET 0x00000000
4931 /* The byte offset of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS register from the beginning of the component. */
4932 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_OFST 0x90
4933 /* The address of the ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS register. */
4934 #define ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_OFST))
4935 
4936 /*
4937  * Register : onfi_timing_mode
4938  *
4939  * Asynchronous Timing modes supported by the connected ONFI device
4940  *
4941  * Register Layout
4942  *
4943  * Bits | Access | Reset | Description
4944  * :-------|:-------|:--------|:--------------------------------------
4945  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE
4946  * [31:6] | ??? | Unknown | *UNDEFINED*
4947  *
4948  */
4949 /*
4950  * Field : value
4951  *
4952  * The values in the field should be interpreted as follows[list]
4953  *
4954  * [*]Bit 0 - Supports Timing mode 0.
4955  *
4956  * [*]Bit 1 - Supports Timing mode 1.
4957  *
4958  * [*]Bit 2 - Supports Timing mode 2.
4959  *
4960  * [*]Bit 3 - Supports Timing mode 3.
4961  *
4962  * [*]Bit 4 - Supports Timing mode 4.
4963  *
4964  * [*]Bit 5 - Supports Timing mode 5.[/list]
4965  *
4966  * Field Access Macros:
4967  *
4968  */
4969 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field. */
4970 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_LSB 0
4971 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field. */
4972 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_MSB 5
4973 /* The width in bits of the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field. */
4974 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_WIDTH 6
4975 /* The mask used to set the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field value. */
4976 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_SET_MSK 0x0000003f
4977 /* The mask used to clear the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field value. */
4978 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_CLR_MSK 0xffffffc0
4979 /* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field. */
4980 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_RESET 0x0
4981 /* Extracts the ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE field value from a register. */
4982 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4983 /* Produces a ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE register field value suitable for setting the register. */
4984 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4985 
4986 #ifndef __ASSEMBLY__
4987 /*
4988  * WARNING: The C register and register group struct declarations are provided for
4989  * convenience and illustrative purposes. They should, however, be used with
4990  * caution as the C language standard provides no guarantees about the alignment or
4991  * atomicity of device memory accesses. The recommended practice for coding device
4992  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
4993  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
4994  * alt_write_dword() functions for 64 bit registers.
4995  *
4996  * The struct declaration for register ALT_NAND_PARAM_ONFI_TIMING_MODE.
4997  */
4998 struct ALT_NAND_PARAM_ONFI_TIMING_MODE_s
4999 {
5000  const volatile uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_TIMING_MODE_VALUE */
5001  uint32_t : 26; /* *UNDEFINED* */
5002 };
5003 
5004 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_TIMING_MODE. */
5005 typedef struct ALT_NAND_PARAM_ONFI_TIMING_MODE_s ALT_NAND_PARAM_ONFI_TIMING_MODE_t;
5006 #endif /* __ASSEMBLY__ */
5007 
5008 /* The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MODE register. */
5009 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_RESET 0x00000000
5010 /* The byte offset of the ALT_NAND_PARAM_ONFI_TIMING_MODE register from the beginning of the component. */
5011 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_OFST 0xa0
5012 /* The address of the ALT_NAND_PARAM_ONFI_TIMING_MODE register. */
5013 #define ALT_NAND_PARAM_ONFI_TIMING_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_TIMING_MODE_OFST))
5014 
5015 /*
5016  * Register : onfi_pgm_cache_timing_mode
5017  *
5018  * Asynchronous Program Cache Timing modes supported by the connected ONFI device
5019  *
5020  * Register Layout
5021  *
5022  * Bits | Access | Reset | Description
5023  * :-------|:-------|:--------|:------------------------------------------------
5024  * [5:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE
5025  * [31:6] | ??? | Unknown | *UNDEFINED*
5026  *
5027  */
5028 /*
5029  * Field : value
5030  *
5031  * The values in the field should be interpreted as follows[list]
5032  *
5033  * [*]Bit 0 - Supports Timing mode 0.
5034  *
5035  * [*]Bit 1 - Supports Timing mode 1.
5036  *
5037  * [*]Bit 2 - Supports Timing mode 2.
5038  *
5039  * [*]Bit 3 - Supports Timing mode 3.
5040  *
5041  * [*]Bit 4 - Supports Timing mode 4.
5042  *
5043  * [*]Bit 5 - Supports Timing mode 5.[/list]
5044  *
5045  * Field Access Macros:
5046  *
5047  */
5048 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field. */
5049 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_LSB 0
5050 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field. */
5051 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_MSB 5
5052 /* The width in bits of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field. */
5053 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_WIDTH 6
5054 /* The mask used to set the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field value. */
5055 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_SET_MSK 0x0000003f
5056 /* The mask used to clear the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field value. */
5057 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_CLR_MSK 0xffffffc0
5058 /* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field. */
5059 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_RESET 0x0
5060 /* Extracts the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE field value from a register. */
5061 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
5062 /* Produces a ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE register field value suitable for setting the register. */
5063 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
5064 
5065 #ifndef __ASSEMBLY__
5066 /*
5067  * WARNING: The C register and register group struct declarations are provided for
5068  * convenience and illustrative purposes. They should, however, be used with
5069  * caution as the C language standard provides no guarantees about the alignment or
5070  * atomicity of device memory accesses. The recommended practice for coding device
5071  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5072  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5073  * alt_write_dword() functions for 64 bit registers.
5074  *
5075  * The struct declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE.
5076  */
5077 struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_s
5078 {
5079  const volatile uint32_t value : 6; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_VALUE */
5080  uint32_t : 26; /* *UNDEFINED* */
5081 };
5082 
5083 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE. */
5084 typedef struct ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_s ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_t;
5085 #endif /* __ASSEMBLY__ */
5086 
5087 /* The reset value of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE register. */
5088 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_RESET 0x00000000
5089 /* The byte offset of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE register from the beginning of the component. */
5090 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_OFST 0xb0
5091 /* The address of the ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE register. */
5092 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_OFST))
5093 
5094 /*
5095  * Register : onfi_device_no_of_luns
5096  *
5097  * Indicates if the device is an ONFI compliant device and the number
5098  *
5099  * of LUNS present in the device
5100  *
5101  * Register Layout
5102  *
5103  * Bits | Access | Reset | Description
5104  * :--------|:-------|:--------|:--------------------------------------------------------------------------
5105  * [7:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS
5106  * [8] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE
5107  * [11:9] | ??? | Unknown | *UNDEFINED*
5108  * [12] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT
5109  * [15:13] | ??? | Unknown | *UNDEFINED*
5110  * [16] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ
5111  * [19:17] | ??? | Unknown | *UNDEFINED*
5112  * [20] | RW | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE
5113  * [31:21] | ??? | Unknown | *UNDEFINED*
5114  *
5115  */
5116 /*
5117  * Field : no_of_luns
5118  *
5119  * Indicates the number of LUNS present in the device
5120  *
5121  * Field Access Macros:
5122  *
5123  */
5124 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field. */
5125 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_LSB 0
5126 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field. */
5127 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_MSB 7
5128 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field. */
5129 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
5130 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field value. */
5131 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
5132 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field value. */
5133 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
5134 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field. */
5135 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
5136 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS field value from a register. */
5137 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
5138 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS register field value suitable for setting the register. */
5139 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
5140 
5141 /*
5142  * Field : onfi_device
5143  *
5144  * Indicates if the device is an ONFI compliant device.[list]
5145  *
5146  * [*]0 - Non-ONFI compliant device
5147  *
5148  * [*]1 - ONFI compliant device[/list]
5149  *
5150  * Field Access Macros:
5151  *
5152  */
5153 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field. */
5154 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_LSB 8
5155 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field. */
5156 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_MSB 8
5157 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field. */
5158 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
5159 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field value. */
5160 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
5161 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field value. */
5162 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
5163 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field. */
5164 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
5165 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE field value from a register. */
5166 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
5167 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE register field value suitable for setting the register. */
5168 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
5169 
5170 /*
5171  * Field : prog_page_reg_clear_enhancement
5172  *
5173  * Device supports program page register clear enhancement.In such a device,
5174  *
5175  * a program can be initiated in a LUN even if a read command is ongoing in
5176  *
5177  * another LUN in the device.
5178  *
5179  * [list][*]1 - Program page register clear enhancement supported
5180  *
5181  * [*]0 - Program page register clear enhancement not supported[/list]
5182  *
5183  * Field Access Macros:
5184  *
5185  */
5186 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field. */
5187 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_LSB 12
5188 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field. */
5189 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_MSB 12
5190 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field. */
5191 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_WIDTH 1
5192 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field value. */
5193 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_SET_MSK 0x00001000
5194 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field value. */
5195 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_CLR_MSK 0xffffefff
5196 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field. */
5197 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_RESET 0x0
5198 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT field value from a register. */
5199 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_GET(value) (((value) & 0x00001000) >> 12)
5200 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT register field value suitable for setting the register. */
5201 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT_SET(value) (((value) << 12) & 0x00001000)
5202 
5203 /*
5204  * Field : onfi_jedec_multiplane_erase_seq
5205  *
5206  * Device supports ONFI JEDEC Multiplane erase sequence.(Only valid for Onfi
5207  * devices)
5208  *
5209  * [list][*]1 - ONFI JEDEC Multiplane erase sequence supported
5210  *
5211  * [*]0 - ONFI JEDEC Multiplane erase sequence not supported[/list]
5212  *
5213  * Field Access Macros:
5214  *
5215  */
5216 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5217 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_LSB 16
5218 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5219 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_MSB 16
5220 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5221 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_WIDTH 1
5222 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value. */
5223 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET_MSK 0x00010000
5224 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value. */
5225 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_CLR_MSK 0xfffeffff
5226 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field. */
5227 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_RESET 0x0
5228 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ field value from a register. */
5229 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_GET(value) (((value) & 0x00010000) >> 16)
5230 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ register field value suitable for setting the register. */
5231 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET(value) (((value) << 16) & 0x00010000)
5232 
5233 /*
5234  * Field : ce_reduction_volume_addr_and_change
5235  *
5236  * Device supports CE pin reduction with volume assignments,volume addressing
5237  *
5238  * and volume change command sequence.For any device configured by host to be used
5239  * in
5240  *
5241  * volume addressing mode, this bit must be set to 1.
5242  *
5243  * [list][*]1 - supported [*]0 - Not supported[/list]
5244  *
5245  * Field Access Macros:
5246  *
5247  */
5248 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5249 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_LSB 20
5250 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5251 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_MSB 20
5252 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5253 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_WIDTH 1
5254 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value. */
5255 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET_MSK 0x00100000
5256 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value. */
5257 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_CLR_MSK 0xffefffff
5258 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field. */
5259 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_RESET 0x0
5260 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE field value from a register. */
5261 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_GET(value) (((value) & 0x00100000) >> 20)
5262 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE register field value suitable for setting the register. */
5263 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET(value) (((value) << 20) & 0x00100000)
5264 
5265 #ifndef __ASSEMBLY__
5266 /*
5267  * WARNING: The C register and register group struct declarations are provided for
5268  * convenience and illustrative purposes. They should, however, be used with
5269  * caution as the C language standard provides no guarantees about the alignment or
5270  * atomicity of device memory accesses. The recommended practice for coding device
5271  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5272  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5273  * alt_write_dword() functions for 64 bit registers.
5274  *
5275  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS.
5276  */
5277 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_s
5278 {
5279  const volatile uint32_t no_of_luns : 8; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_NO_OF_LUNS */
5280  volatile uint32_t onfi_device : 1; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_DEVICE */
5281  uint32_t : 3; /* *UNDEFINED* */
5282  volatile uint32_t prog_page_reg_clear_enhancement : 1; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_PROG_PAGE_REG_CLEAR_ENHANCEMENT */
5283  uint32_t : 3; /* *UNDEFINED* */
5284  volatile uint32_t onfi_jedec_multiplane_erase_seq : 1; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ */
5285  uint32_t : 3; /* *UNDEFINED* */
5286  volatile uint32_t ce_reduction_volume_addr_and_change : 1; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE */
5287  uint32_t : 11; /* *UNDEFINED* */
5288 };
5289 
5290 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS. */
5291 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_t;
5292 #endif /* __ASSEMBLY__ */
5293 
5294 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS register. */
5295 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_RESET 0x00000000
5296 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS register from the beginning of the component. */
5297 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_OFST 0xc0
5298 /* The address of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS register. */
5299 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_OFST))
5300 
5301 /*
5302  * Register : onfi_device_no_of_blocks_per_lun_l
5303  *
5304  * Lower bits of number of blocks per LUN present in
5305  *
5306  * the ONFI complaint device.
5307  *
5308  * Register Layout
5309  *
5310  * Bits | Access | Reset | Description
5311  * :--------|:-------|:--------|:--------------------------------------------------------
5312  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE
5313  * [31:16] | ??? | Unknown | *UNDEFINED*
5314  *
5315  */
5316 /*
5317  * Field : value
5318  *
5319  * Indicates the lower bits of number of blocks per
5320  *
5321  * LUN present in the ONFI complaint device.
5322  *
5323  * Field Access Macros:
5324  *
5325  */
5326 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field. */
5327 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_LSB 0
5328 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field. */
5329 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_MSB 15
5330 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field. */
5331 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_WIDTH 16
5332 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field value. */
5333 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
5334 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field value. */
5335 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
5336 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field. */
5337 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_RESET 0x0
5338 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE field value from a register. */
5339 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5340 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE register field value suitable for setting the register. */
5341 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5342 
5343 #ifndef __ASSEMBLY__
5344 /*
5345  * WARNING: The C register and register group struct declarations are provided for
5346  * convenience and illustrative purposes. They should, however, be used with
5347  * caution as the C language standard provides no guarantees about the alignment or
5348  * atomicity of device memory accesses. The recommended practice for coding device
5349  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5350  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5351  * alt_write_dword() functions for 64 bit registers.
5352  *
5353  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L.
5354  */
5355 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_s
5356 {
5357  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_VALUE */
5358  uint32_t : 16; /* *UNDEFINED* */
5359 };
5360 
5361 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L. */
5362 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_t;
5363 #endif /* __ASSEMBLY__ */
5364 
5365 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L register. */
5366 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_RESET 0x00000000
5367 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L register from the beginning of the component. */
5368 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_OFST 0xd0
5369 /* The address of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L register. */
5370 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_OFST))
5371 
5372 /*
5373  * Register : onfi_device_no_of_blocks_per_lun_u
5374  *
5375  * Upper bits of number of blocks per LUN present in
5376  *
5377  * the ONFI complaint device.
5378  *
5379  * Register Layout
5380  *
5381  * Bits | Access | Reset | Description
5382  * :--------|:-------|:--------|:--------------------------------------------------------
5383  * [15:0] | R | 0x0 | ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE
5384  * [31:16] | ??? | Unknown | *UNDEFINED*
5385  *
5386  */
5387 /*
5388  * Field : value
5389  *
5390  * Indicates the upper bits of number of blocks per
5391  *
5392  * LUN present in the ONFI complaint device.
5393  *
5394  * Field Access Macros:
5395  *
5396  */
5397 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field. */
5398 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_LSB 0
5399 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field. */
5400 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_MSB 15
5401 /* The width in bits of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field. */
5402 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_WIDTH 16
5403 /* The mask used to set the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field value. */
5404 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
5405 /* The mask used to clear the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field value. */
5406 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
5407 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field. */
5408 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_RESET 0x0
5409 /* Extracts the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE field value from a register. */
5410 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5411 /* Produces a ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE register field value suitable for setting the register. */
5412 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5413 
5414 #ifndef __ASSEMBLY__
5415 /*
5416  * WARNING: The C register and register group struct declarations are provided for
5417  * convenience and illustrative purposes. They should, however, be used with
5418  * caution as the C language standard provides no guarantees about the alignment or
5419  * atomicity of device memory accesses. The recommended practice for coding device
5420  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5421  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5422  * alt_write_dword() functions for 64 bit registers.
5423  *
5424  * The struct declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U.
5425  */
5426 struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_s
5427 {
5428  const volatile uint32_t value : 16; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_VALUE */
5429  uint32_t : 16; /* *UNDEFINED* */
5430 };
5431 
5432 /* The typedef declaration for register ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U. */
5433 typedef struct ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_s ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_t;
5434 #endif /* __ASSEMBLY__ */
5435 
5436 /* The reset value of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U register. */
5437 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_RESET 0x00000000
5438 /* The byte offset of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U register from the beginning of the component. */
5439 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_OFST 0xe0
5440 /* The address of the ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U register. */
5441 #define ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_OFST))
5442 
5443 /*
5444  * Register : features
5445  *
5446  * Shows Available hardware features or attributes
5447  *
5448  * Register Layout
5449  *
5450  * Bits | Access | Reset | Description
5451  * :--------|:-------|:--------|:--------------------------------------
5452  * [1:0] | R | 0x2 | ALT_NAND_PARAM_FEATURES_N_BANKS
5453  * [5:2] | ??? | Unknown | *UNDEFINED*
5454  * [6] | R | 0x1 | ALT_NAND_PARAM_FEATURES_DMA
5455  * [7] | R | 0x1 | ALT_NAND_PARAM_FEATURES_CMD_DMA
5456  * [8] | R | 0x0 | ALT_NAND_PARAM_FEATURES_PARTITION
5457  * [9] | R | 0x0 | ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND
5458  * [10] | R | 0x0 | ALT_NAND_PARAM_FEATURES_GPREG
5459  * [11] | R | 0x1 | ALT_NAND_PARAM_FEATURES_INDEX_ADDR
5460  * [12] | R | 0x0 | ALT_NAND_PARAM_FEATURES_DFI_INTF
5461  * [13] | R | 0x0 | ALT_NAND_PARAM_FEATURES_LBA
5462  * [31:14] | ??? | Unknown | *UNDEFINED*
5463  *
5464  */
5465 /*
5466  * Field : n_banks
5467  *
5468  * Maximum number of banks supported by hardware. This is an
5469  *
5470  * encoded value.
5471  *
5472  * [list][*]0 - One bank
5473  *
5474  * [*]1 - Two banks
5475  *
5476  * [*]2 - Four banks
5477  *
5478  * [*]3 - Eight banks[/list]
5479  *
5480  * Field Access Macros:
5481  *
5482  */
5483 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5484 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
5485 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5486 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
5487 /* The width in bits of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5488 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
5489 /* The mask used to set the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
5490 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
5491 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_N_BANKS register field value. */
5492 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
5493 /* The reset value of the ALT_NAND_PARAM_FEATURES_N_BANKS register field. */
5494 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x2
5495 /* Extracts the ALT_NAND_PARAM_FEATURES_N_BANKS field value from a register. */
5496 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
5497 /* Produces a ALT_NAND_PARAM_FEATURES_N_BANKS register field value suitable for setting the register. */
5498 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
5499 
5500 /*
5501  * Field : dma
5502  *
5503  * if set, DATA-DMA is present in hardware.
5504  *
5505  * Field Access Macros:
5506  *
5507  */
5508 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5509 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
5510 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5511 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
5512 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5513 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
5514 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DMA register field value. */
5515 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
5516 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DMA register field value. */
5517 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
5518 /* The reset value of the ALT_NAND_PARAM_FEATURES_DMA register field. */
5519 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
5520 /* Extracts the ALT_NAND_PARAM_FEATURES_DMA field value from a register. */
5521 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
5522 /* Produces a ALT_NAND_PARAM_FEATURES_DMA register field value suitable for setting the register. */
5523 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
5524 
5525 /*
5526  * Field : cmd_dma
5527  *
5528  * if set, CMD-DMA is present in hardware.
5529  *
5530  * Field Access Macros:
5531  *
5532  */
5533 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5534 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
5535 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5536 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
5537 /* The width in bits of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5538 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
5539 /* The mask used to set the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
5540 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
5541 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_CMD_DMA register field value. */
5542 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
5543 /* The reset value of the ALT_NAND_PARAM_FEATURES_CMD_DMA register field. */
5544 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x1
5545 /* Extracts the ALT_NAND_PARAM_FEATURES_CMD_DMA field value from a register. */
5546 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
5547 /* Produces a ALT_NAND_PARAM_FEATURES_CMD_DMA register field value suitable for setting the register. */
5548 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
5549 
5550 /*
5551  * Field : partition
5552  *
5553  * if set, Partition logic is present in hardware.
5554  *
5555  * Field Access Macros:
5556  *
5557  */
5558 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5559 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
5560 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5561 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
5562 /* The width in bits of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5563 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
5564 /* The mask used to set the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
5565 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
5566 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_PARTITION register field value. */
5567 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
5568 /* The reset value of the ALT_NAND_PARAM_FEATURES_PARTITION register field. */
5569 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
5570 /* Extracts the ALT_NAND_PARAM_FEATURES_PARTITION field value from a register. */
5571 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
5572 /* Produces a ALT_NAND_PARAM_FEATURES_PARTITION register field value suitable for setting the register. */
5573 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
5574 
5575 /*
5576  * Field : xdma_sideband
5577  *
5578  * if set, Side band DMA signals are present in hardware.
5579  *
5580  * Field Access Macros:
5581  *
5582  */
5583 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5584 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
5585 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5586 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
5587 /* The width in bits of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5588 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
5589 /* The mask used to set the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
5590 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
5591 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value. */
5592 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
5593 /* The reset value of the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field. */
5594 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
5595 /* Extracts the ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND field value from a register. */
5596 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
5597 /* Produces a ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND register field value suitable for setting the register. */
5598 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
5599 
5600 /*
5601  * Field : gpreg
5602  *
5603  * if set, General purpose registers are is present in hardware.
5604  *
5605  * Field Access Macros:
5606  *
5607  */
5608 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5609 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
5610 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5611 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
5612 /* The width in bits of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5613 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
5614 /* The mask used to set the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
5615 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
5616 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_GPREG register field value. */
5617 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
5618 /* The reset value of the ALT_NAND_PARAM_FEATURES_GPREG register field. */
5619 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
5620 /* Extracts the ALT_NAND_PARAM_FEATURES_GPREG field value from a register. */
5621 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
5622 /* Produces a ALT_NAND_PARAM_FEATURES_GPREG register field value suitable for setting the register. */
5623 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
5624 
5625 /*
5626  * Field : index_addr
5627  *
5628  * if set, hardware support only Indexed addressing.
5629  *
5630  * Field Access Macros:
5631  *
5632  */
5633 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5634 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
5635 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5636 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
5637 /* The width in bits of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5638 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
5639 /* The mask used to set the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
5640 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
5641 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value. */
5642 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
5643 /* The reset value of the ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field. */
5644 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
5645 /* Extracts the ALT_NAND_PARAM_FEATURES_INDEX_ADDR field value from a register. */
5646 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
5647 /* Produces a ALT_NAND_PARAM_FEATURES_INDEX_ADDR register field value suitable for setting the register. */
5648 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
5649 
5650 /*
5651  * Field : dfi_intf
5652  *
5653  * if set, hardware supports ONFI2.x synchronous interface.
5654  *
5655  * Field Access Macros:
5656  *
5657  */
5658 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5659 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
5660 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5661 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
5662 /* The width in bits of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5663 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
5664 /* The mask used to set the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
5665 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
5666 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_DFI_INTF register field value. */
5667 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
5668 /* The reset value of the ALT_NAND_PARAM_FEATURES_DFI_INTF register field. */
5669 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
5670 /* Extracts the ALT_NAND_PARAM_FEATURES_DFI_INTF field value from a register. */
5671 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
5672 /* Produces a ALT_NAND_PARAM_FEATURES_DFI_INTF register field value suitable for setting the register. */
5673 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
5674 
5675 /*
5676  * Field : lba
5677  *
5678  * if set, hardware supports Toshiba LBA devices.
5679  *
5680  * Field Access Macros:
5681  *
5682  */
5683 /* The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5684 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
5685 /* The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5686 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
5687 /* The width in bits of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5688 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
5689 /* The mask used to set the ALT_NAND_PARAM_FEATURES_LBA register field value. */
5690 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
5691 /* The mask used to clear the ALT_NAND_PARAM_FEATURES_LBA register field value. */
5692 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
5693 /* The reset value of the ALT_NAND_PARAM_FEATURES_LBA register field. */
5694 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
5695 /* Extracts the ALT_NAND_PARAM_FEATURES_LBA field value from a register. */
5696 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
5697 /* Produces a ALT_NAND_PARAM_FEATURES_LBA register field value suitable for setting the register. */
5698 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
5699 
5700 #ifndef __ASSEMBLY__
5701 /*
5702  * WARNING: The C register and register group struct declarations are provided for
5703  * convenience and illustrative purposes. They should, however, be used with
5704  * caution as the C language standard provides no guarantees about the alignment or
5705  * atomicity of device memory accesses. The recommended practice for coding device
5706  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5707  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5708  * alt_write_dword() functions for 64 bit registers.
5709  *
5710  * The struct declaration for register ALT_NAND_PARAM_FEATURES.
5711  */
5712 struct ALT_NAND_PARAM_FEATURES_s
5713 {
5714  const volatile uint32_t n_banks : 2; /* ALT_NAND_PARAM_FEATURES_N_BANKS */
5715  uint32_t : 4; /* *UNDEFINED* */
5716  const volatile uint32_t dma : 1; /* ALT_NAND_PARAM_FEATURES_DMA */
5717  const volatile uint32_t cmd_dma : 1; /* ALT_NAND_PARAM_FEATURES_CMD_DMA */
5718  const volatile uint32_t partition : 1; /* ALT_NAND_PARAM_FEATURES_PARTITION */
5719  const volatile uint32_t xdma_sideband : 1; /* ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND */
5720  const volatile uint32_t gpreg : 1; /* ALT_NAND_PARAM_FEATURES_GPREG */
5721  const volatile uint32_t index_addr : 1; /* ALT_NAND_PARAM_FEATURES_INDEX_ADDR */
5722  const volatile uint32_t dfi_intf : 1; /* ALT_NAND_PARAM_FEATURES_DFI_INTF */
5723  const volatile uint32_t lba : 1; /* ALT_NAND_PARAM_FEATURES_LBA */
5724  uint32_t : 18; /* *UNDEFINED* */
5725 };
5726 
5727 /* The typedef declaration for register ALT_NAND_PARAM_FEATURES. */
5728 typedef struct ALT_NAND_PARAM_FEATURES_s ALT_NAND_PARAM_FEATURES_t;
5729 #endif /* __ASSEMBLY__ */
5730 
5731 /* The reset value of the ALT_NAND_PARAM_FEATURES register. */
5732 #define ALT_NAND_PARAM_FEATURES_RESET 0x000008c2
5733 /* The byte offset of the ALT_NAND_PARAM_FEATURES register from the beginning of the component. */
5734 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
5735 /* The address of the ALT_NAND_PARAM_FEATURES register. */
5736 #define ALT_NAND_PARAM_FEATURES_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_PARAM_FEATURES_OFST))
5737 
5738 #ifndef __ASSEMBLY__
5739 /*
5740  * WARNING: The C register and register group struct declarations are provided for
5741  * convenience and illustrative purposes. They should, however, be used with
5742  * caution as the C language standard provides no guarantees about the alignment or
5743  * atomicity of device memory accesses. The recommended practice for coding device
5744  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5745  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5746  * alt_write_dword() functions for 64 bit registers.
5747  *
5748  * The struct declaration for register group ALT_NAND_PARAM.
5749  */
5750 struct ALT_NAND_PARAM_s
5751 {
5752  volatile ALT_NAND_PARAM_MANUFACTURER_ID_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
5753  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
5754  volatile ALT_NAND_PARAM_DEVICE_ID_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
5755  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5756  volatile ALT_NAND_PARAM_DEVICE_PARAM_0_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
5757  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
5758  volatile ALT_NAND_PARAM_DEVICE_PARAM_1_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
5759  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
5760  volatile ALT_NAND_PARAM_DEVICE_PARAM_2_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
5761  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
5762  volatile ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
5763  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
5764  volatile ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
5765  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
5766  volatile ALT_NAND_PARAM_REVISION_t revision; /* ALT_NAND_PARAM_REVISION */
5767  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
5768  volatile ALT_NAND_PARAM_ONFI_DEVICE_FEATURES_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEVICE_FEATURES */
5769  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
5770  volatile ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS */
5771  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
5772  volatile ALT_NAND_PARAM_ONFI_TIMING_MODE_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MODE */
5773  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
5774  volatile ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE */
5775  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
5776  volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS */
5777  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
5778  volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L */
5779  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
5780  volatile ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U */
5781  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
5782  volatile ALT_NAND_PARAM_FEATURES_t features; /* ALT_NAND_PARAM_FEATURES */
5783 };
5784 
5785 /* The typedef declaration for register group ALT_NAND_PARAM. */
5786 typedef struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
5787 /* The struct declaration for the raw register contents of register group ALT_NAND_PARAM. */
5788 struct ALT_NAND_PARAM_raw_s
5789 {
5790  volatile uint32_t manufacturer_id; /* ALT_NAND_PARAM_MANUFACTURER_ID */
5791  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
5792  volatile uint32_t device_id; /* ALT_NAND_PARAM_DEVICE_ID */
5793  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
5794  volatile uint32_t device_param_0; /* ALT_NAND_PARAM_DEVICE_PARAM_0 */
5795  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
5796  volatile uint32_t device_param_1; /* ALT_NAND_PARAM_DEVICE_PARAM_1 */
5797  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
5798  volatile uint32_t device_param_2; /* ALT_NAND_PARAM_DEVICE_PARAM_2 */
5799  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
5800  volatile uint32_t logical_page_data_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE */
5801  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
5802  volatile uint32_t logical_page_spare_size; /* ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE */
5803  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
5804  volatile uint32_t revision; /* ALT_NAND_PARAM_REVISION */
5805  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
5806  volatile uint32_t onfi_device_features; /* ALT_NAND_PARAM_ONFI_DEVICE_FEATURES */
5807  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
5808  volatile uint32_t onfi_optional_commands; /* ALT_NAND_PARAM_ONFI_OPTIONAL_COMMANDS */
5809  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
5810  volatile uint32_t onfi_timing_mode; /* ALT_NAND_PARAM_ONFI_TIMING_MODE */
5811  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
5812  volatile uint32_t onfi_pgm_cache_timing_mode; /* ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MODE */
5813  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
5814  volatile uint32_t onfi_device_no_of_luns; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_LUNS */
5815  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
5816  volatile uint32_t onfi_device_no_of_blocks_per_lun_l; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L */
5817  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
5818  volatile uint32_t onfi_device_no_of_blocks_per_lun_u; /* ALT_NAND_PARAM_ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U */
5819  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
5820  volatile uint32_t features; /* ALT_NAND_PARAM_FEATURES */
5821 };
5822 
5823 /* The typedef declaration for the raw register contents of register group ALT_NAND_PARAM. */
5824 typedef struct ALT_NAND_PARAM_raw_s ALT_NAND_PARAM_raw_t;
5825 #endif /* __ASSEMBLY__ */
5826 
5827 
5828 /*
5829  * Component : Interrupt and Status registers - NAND_STAT
5830  * Interrupt and Status registers
5831  *
5832  * Contains interrupt and status registers of controller accessible
5833  *
5834  * by software.
5835  *
5836  */
5837 /*
5838  * Register : transfer_mode
5839  *
5840  * Current data transfer mode is Main only, Spare only or Main+Spare.
5841  *
5842  * This information is per bank.
5843  *
5844  * Register Layout
5845  *
5846  * Bits | Access | Reset | Description
5847  * :-------|:-------|:--------|:-----------------------------------
5848  * [1:0] | R | 0x0 | ALT_NAND_STAT_TRANSFER_MODE_VALUE0
5849  * [3:2] | R | 0x0 | ALT_NAND_STAT_TRANSFER_MODE_VALUE1
5850  * [5:4] | R | 0x0 | ALT_NAND_STAT_TRANSFER_MODE_VALUE2
5851  * [7:6] | R | 0x0 | ALT_NAND_STAT_TRANSFER_MODE_VALUE3
5852  * [31:8] | ??? | Unknown | *UNDEFINED*
5853  *
5854  */
5855 /*
5856  * Field : value0
5857  *
5858  * [list][*]00 - Bank 0 is in Main mode [*]01 - Bank 0 is in Spare mode [*]10 -
5859  * Bank 0 is in Main+Spare mode[/list]
5860  *
5861  * Field Access Macros:
5862  *
5863  */
5864 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field. */
5865 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_LSB 0
5866 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field. */
5867 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_MSB 1
5868 /* The width in bits of the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field. */
5869 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_WIDTH 2
5870 /* The mask used to set the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field value. */
5871 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_SET_MSK 0x00000003
5872 /* The mask used to clear the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field value. */
5873 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_CLR_MSK 0xfffffffc
5874 /* The reset value of the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field. */
5875 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_RESET 0x0
5876 /* Extracts the ALT_NAND_STAT_TRANSFER_MODE_VALUE0 field value from a register. */
5877 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
5878 /* Produces a ALT_NAND_STAT_TRANSFER_MODE_VALUE0 register field value suitable for setting the register. */
5879 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE0_SET(value) (((value) << 0) & 0x00000003)
5880 
5881 /*
5882  * Field : value1
5883  *
5884  * [list][*]00 - Bank 1 is in Main mode [*]01 - Bank 1 is in Spare mode [*]10 -
5885  * Bank 1 is in Main+Spare mode[/list]
5886  *
5887  * Field Access Macros:
5888  *
5889  */
5890 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field. */
5891 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_LSB 2
5892 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field. */
5893 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_MSB 3
5894 /* The width in bits of the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field. */
5895 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_WIDTH 2
5896 /* The mask used to set the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field value. */
5897 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_SET_MSK 0x0000000c
5898 /* The mask used to clear the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field value. */
5899 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_CLR_MSK 0xfffffff3
5900 /* The reset value of the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field. */
5901 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_RESET 0x0
5902 /* Extracts the ALT_NAND_STAT_TRANSFER_MODE_VALUE1 field value from a register. */
5903 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
5904 /* Produces a ALT_NAND_STAT_TRANSFER_MODE_VALUE1 register field value suitable for setting the register. */
5905 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
5906 
5907 /*
5908  * Field : value2
5909  *
5910  * [list][*]00 - Bank 2 is in Main mode [*]01 - Bank 2 is in Spare mode [*]10 -
5911  * Bank 2 is in Main+Spare mode[/list]
5912  *
5913  * Field Access Macros:
5914  *
5915  */
5916 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field. */
5917 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_LSB 4
5918 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field. */
5919 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_MSB 5
5920 /* The width in bits of the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field. */
5921 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_WIDTH 2
5922 /* The mask used to set the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field value. */
5923 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_SET_MSK 0x00000030
5924 /* The mask used to clear the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field value. */
5925 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_CLR_MSK 0xffffffcf
5926 /* The reset value of the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field. */
5927 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_RESET 0x0
5928 /* Extracts the ALT_NAND_STAT_TRANSFER_MODE_VALUE2 field value from a register. */
5929 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
5930 /* Produces a ALT_NAND_STAT_TRANSFER_MODE_VALUE2 register field value suitable for setting the register. */
5931 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE2_SET(value) (((value) << 4) & 0x00000030)
5932 
5933 /*
5934  * Field : value3
5935  *
5936  * [list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is in Spare mode [*]10 -
5937  * Bank 3 is in Main+Spare mode[/list]
5938  *
5939  * Field Access Macros:
5940  *
5941  */
5942 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field. */
5943 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_LSB 6
5944 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field. */
5945 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_MSB 7
5946 /* The width in bits of the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field. */
5947 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_WIDTH 2
5948 /* The mask used to set the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field value. */
5949 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_SET_MSK 0x000000c0
5950 /* The mask used to clear the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field value. */
5951 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_CLR_MSK 0xffffff3f
5952 /* The reset value of the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field. */
5953 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_RESET 0x0
5954 /* Extracts the ALT_NAND_STAT_TRANSFER_MODE_VALUE3 field value from a register. */
5955 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
5956 /* Produces a ALT_NAND_STAT_TRANSFER_MODE_VALUE3 register field value suitable for setting the register. */
5957 #define ALT_NAND_STAT_TRANSFER_MODE_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
5958 
5959 #ifndef __ASSEMBLY__
5960 /*
5961  * WARNING: The C register and register group struct declarations are provided for
5962  * convenience and illustrative purposes. They should, however, be used with
5963  * caution as the C language standard provides no guarantees about the alignment or
5964  * atomicity of device memory accesses. The recommended practice for coding device
5965  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
5966  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
5967  * alt_write_dword() functions for 64 bit registers.
5968  *
5969  * The struct declaration for register ALT_NAND_STAT_TRANSFER_MODE.
5970  */
5971 struct ALT_NAND_STAT_TRANSFER_MODE_s
5972 {
5973  const volatile uint32_t value0 : 2; /* ALT_NAND_STAT_TRANSFER_MODE_VALUE0 */
5974  const volatile uint32_t value1 : 2; /* ALT_NAND_STAT_TRANSFER_MODE_VALUE1 */
5975  const volatile uint32_t value2 : 2; /* ALT_NAND_STAT_TRANSFER_MODE_VALUE2 */
5976  const volatile uint32_t value3 : 2; /* ALT_NAND_STAT_TRANSFER_MODE_VALUE3 */
5977  uint32_t : 24; /* *UNDEFINED* */
5978 };
5979 
5980 /* The typedef declaration for register ALT_NAND_STAT_TRANSFER_MODE. */
5981 typedef struct ALT_NAND_STAT_TRANSFER_MODE_s ALT_NAND_STAT_TRANSFER_MODE_t;
5982 #endif /* __ASSEMBLY__ */
5983 
5984 /* The reset value of the ALT_NAND_STAT_TRANSFER_MODE register. */
5985 #define ALT_NAND_STAT_TRANSFER_MODE_RESET 0x00000000
5986 /* The byte offset of the ALT_NAND_STAT_TRANSFER_MODE register from the beginning of the component. */
5987 #define ALT_NAND_STAT_TRANSFER_MODE_OFST 0x0
5988 /* The address of the ALT_NAND_STAT_TRANSFER_MODE register. */
5989 #define ALT_NAND_STAT_TRANSFER_MODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_TRANSFER_MODE_OFST))
5990 
5991 /*
5992  * Register : intr_status0
5993  *
5994  * Interrupt status register for bank 0
5995  *
5996  * Register Layout
5997  *
5998  * Bits | Access | Reset | Description
5999  * :--------|:-------|:--------|:------------------------------------------------
6000  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR
6001  * [1] | ??? | Unknown | *UNDEFINED*
6002  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP
6003  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_TIME_OUT
6004  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL
6005  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL
6006  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP
6007  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP
6008  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP
6009  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP
6010  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK
6011  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD
6012  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_INT_ACT
6013  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_RST_COMP
6014  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR
6015  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC
6016  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE
6017  * [31:17] | ??? | Unknown | *UNDEFINED*
6018  *
6019  */
6020 /*
6021  * Field : ecc_uncor_err
6022  *
6023  * Ecc logic detected uncorrectable error while reading data from flash device.
6024  *
6025  * Field Access Macros:
6026  *
6027  */
6028 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field. */
6029 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_LSB 0
6030 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field. */
6031 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_MSB 0
6032 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field. */
6033 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_WIDTH 1
6034 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field value. */
6035 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6036 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field value. */
6037 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6038 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field. */
6039 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_RESET 0x0
6040 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR field value from a register. */
6041 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6042 /* Produces a ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR register field value suitable for setting the register. */
6043 #define ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6044 
6045 /*
6046  * Field : dma_cmd_comp
6047  *
6048  * A data DMA command has completed on this bank
6049  *
6050  * Field Access Macros:
6051  *
6052  */
6053 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field. */
6054 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_LSB 2
6055 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field. */
6056 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_MSB 2
6057 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field. */
6058 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_WIDTH 1
6059 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field value. */
6060 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_SET_MSK 0x00000004
6061 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field value. */
6062 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6063 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field. */
6064 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_RESET 0x0
6065 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP field value from a register. */
6066 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6067 /* Produces a ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP register field value suitable for setting the register. */
6068 #define ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6069 
6070 /*
6071  * Field : time_out
6072  *
6073  * Watchdog timer has triggered in the controller due to one of the reasons like
6074  * device
6075  *
6076  * not responding or controller state machine did not get back to idle
6077  *
6078  * Field Access Macros:
6079  *
6080  */
6081 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field. */
6082 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_LSB 3
6083 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field. */
6084 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_MSB 3
6085 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field. */
6086 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_WIDTH 1
6087 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field value. */
6088 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_SET_MSK 0x00000008
6089 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field value. */
6090 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_CLR_MSK 0xfffffff7
6091 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field. */
6092 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_RESET 0x0
6093 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_TIME_OUT field value from a register. */
6094 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6095 /* Produces a ALT_NAND_STAT_INTR_STATUS0_TIME_OUT register field value suitable for setting the register. */
6096 #define ALT_NAND_STAT_INTR_STATUS0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6097 
6098 /*
6099  * Field : program_fail
6100  *
6101  * Program failure occurred in the device on issuance of a program command.
6102  * err_block_addr
6103  *
6104  * and err_page_addr contain the block address and page address that failed program
6105  * operation.
6106  *
6107  * Field Access Macros:
6108  *
6109  */
6110 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field. */
6111 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_LSB 4
6112 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field. */
6113 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_MSB 4
6114 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field. */
6115 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_WIDTH 1
6116 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field value. */
6117 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_SET_MSK 0x00000010
6118 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field value. */
6119 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6120 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field. */
6121 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_RESET 0x0
6122 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL field value from a register. */
6123 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6124 /* Produces a ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL register field value suitable for setting the register. */
6125 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6126 
6127 /*
6128  * Field : erase_fail
6129  *
6130  * Erase failure occurred in the device on issuance of a erase command.
6131  * err_block_addr
6132  *
6133  * and err_page_addr contain the block address and page address that failed erase
6134  * operation.
6135  *
6136  * Field Access Macros:
6137  *
6138  */
6139 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field. */
6140 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_LSB 5
6141 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field. */
6142 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_MSB 5
6143 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field. */
6144 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_WIDTH 1
6145 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field value. */
6146 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_SET_MSK 0x00000020
6147 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field value. */
6148 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_CLR_MSK 0xffffffdf
6149 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field. */
6150 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_RESET 0x0
6151 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL field value from a register. */
6152 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6153 /* Produces a ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL register field value suitable for setting the register. */
6154 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6155 
6156 /*
6157  * Field : load_comp
6158  *
6159  * Device finished the last issued load command.
6160  *
6161  * Field Access Macros:
6162  *
6163  */
6164 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field. */
6165 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_LSB 6
6166 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field. */
6167 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_MSB 6
6168 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field. */
6169 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_WIDTH 1
6170 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field value. */
6171 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_SET_MSK 0x00000040
6172 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field value. */
6173 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_CLR_MSK 0xffffffbf
6174 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field. */
6175 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_RESET 0x0
6176 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP field value from a register. */
6177 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6178 /* Produces a ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP register field value suitable for setting the register. */
6179 #define ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
6180 
6181 /*
6182  * Field : program_comp
6183  *
6184  * Device finished the last issued program command.
6185  *
6186  * Field Access Macros:
6187  *
6188  */
6189 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field. */
6190 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_LSB 7
6191 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field. */
6192 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_MSB 7
6193 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field. */
6194 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_WIDTH 1
6195 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field value. */
6196 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_SET_MSK 0x00000080
6197 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field value. */
6198 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6199 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field. */
6200 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_RESET 0x0
6201 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP field value from a register. */
6202 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6203 /* Produces a ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP register field value suitable for setting the register. */
6204 #define ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6205 
6206 /*
6207  * Field : erase_comp
6208  *
6209  * Device erase operation complete
6210  *
6211  * Field Access Macros:
6212  *
6213  */
6214 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field. */
6215 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_LSB 8
6216 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field. */
6217 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_MSB 8
6218 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field. */
6219 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_WIDTH 1
6220 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field value. */
6221 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_SET_MSK 0x00000100
6222 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field value. */
6223 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_CLR_MSK 0xfffffeff
6224 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field. */
6225 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_RESET 0x0
6226 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP field value from a register. */
6227 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6228 /* Produces a ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP register field value suitable for setting the register. */
6229 #define ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6230 
6231 /*
6232  * Field : pipe_cpybck_cmd_comp
6233  *
6234  * A pipeline command or a copyback bank command has completed on this particular
6235  * bank
6236  *
6237  * Field Access Macros:
6238  *
6239  */
6240 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field. */
6241 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_LSB 9
6242 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field. */
6243 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_MSB 9
6244 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field. */
6245 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6246 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field value. */
6247 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6248 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field value. */
6249 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6250 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field. */
6251 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6252 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP field value from a register. */
6253 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6254 /* Produces a ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6255 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6256 
6257 /*
6258  * Field : locked_blk
6259  *
6260  * The address to program or erase operation is to a locked block and the operation
6261  * failed
6262  *
6263  * due to this reason
6264  *
6265  * Field Access Macros:
6266  *
6267  */
6268 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field. */
6269 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_LSB 10
6270 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field. */
6271 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_MSB 10
6272 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field. */
6273 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_WIDTH 1
6274 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field value. */
6275 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_SET_MSK 0x00000400
6276 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field value. */
6277 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_CLR_MSK 0xfffffbff
6278 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field. */
6279 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_RESET 0x0
6280 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK field value from a register. */
6281 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6282 /* Produces a ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK register field value suitable for setting the register. */
6283 #define ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6284 
6285 /*
6286  * Field : unsup_cmd
6287  *
6288  * An unsupported command was received. This interrupt is set when an invalid
6289  * command is
6290  *
6291  * received, or when a command sequence is broken.
6292  *
6293  * Field Access Macros:
6294  *
6295  */
6296 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field. */
6297 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_LSB 11
6298 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field. */
6299 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_MSB 11
6300 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field. */
6301 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_WIDTH 1
6302 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field value. */
6303 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_SET_MSK 0x00000800
6304 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field value. */
6305 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6306 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field. */
6307 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_RESET 0x0
6308 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD field value from a register. */
6309 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6310 /* Produces a ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD register field value suitable for setting the register. */
6311 #define ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6312 
6313 /*
6314  * Field : int_act
6315  *
6316  * R/B pin of device transitioned from low to high
6317  *
6318  * Field Access Macros:
6319  *
6320  */
6321 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field. */
6322 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_LSB 12
6323 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field. */
6324 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_MSB 12
6325 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field. */
6326 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_WIDTH 1
6327 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field value. */
6328 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_SET_MSK 0x00001000
6329 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field value. */
6330 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_CLR_MSK 0xffffefff
6331 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field. */
6332 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_RESET 0x0
6333 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_INT_ACT field value from a register. */
6334 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6335 /* Produces a ALT_NAND_STAT_INTR_STATUS0_INT_ACT register field value suitable for setting the register. */
6336 #define ALT_NAND_STAT_INTR_STATUS0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6337 
6338 /*
6339  * Field : rst_comp
6340  *
6341  * Controller has finished reset and initialization process
6342  *
6343  * Field Access Macros:
6344  *
6345  */
6346 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field. */
6347 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_LSB 13
6348 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field. */
6349 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_MSB 13
6350 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field. */
6351 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_WIDTH 1
6352 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field value. */
6353 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_SET_MSK 0x00002000
6354 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field value. */
6355 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_CLR_MSK 0xffffdfff
6356 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field. */
6357 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_RESET 0x0
6358 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_RST_COMP field value from a register. */
6359 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6360 /* Produces a ALT_NAND_STAT_INTR_STATUS0_RST_COMP register field value suitable for setting the register. */
6361 #define ALT_NAND_STAT_INTR_STATUS0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6362 
6363 /*
6364  * Field : pipe_cmd_err
6365  *
6366  * A pipeline command sequence has been violated. This occurs when Map 01 page
6367  * read/write
6368  *
6369  * address does not match the corresponding expected address from the pipeline
6370  * commands issued
6371  *
6372  * earlier.
6373  *
6374  * Field Access Macros:
6375  *
6376  */
6377 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field. */
6378 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_LSB 14
6379 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field. */
6380 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_MSB 14
6381 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field. */
6382 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_WIDTH 1
6383 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field value. */
6384 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_SET_MSK 0x00004000
6385 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field value. */
6386 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6387 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field. */
6388 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_RESET 0x0
6389 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR field value from a register. */
6390 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6391 /* Produces a ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR register field value suitable for setting the register. */
6392 #define ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6393 
6394 /*
6395  * Field : page_xfer_inc
6396  *
6397  * For every page of data transfer to or from the device, this bit will be set.
6398  *
6399  * Field Access Macros:
6400  *
6401  */
6402 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field. */
6403 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_LSB 15
6404 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field. */
6405 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_MSB 15
6406 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field. */
6407 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_WIDTH 1
6408 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field value. */
6409 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_SET_MSK 0x00008000
6410 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field value. */
6411 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6412 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field. */
6413 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_RESET 0x0
6414 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC field value from a register. */
6415 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6416 /* Produces a ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC register field value suitable for setting the register. */
6417 #define ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6418 
6419 /*
6420  * Field : erased_page
6421  *
6422  * If an erased page is detected on reads, this bit will be set. The detection of
6423  * erased
6424  *
6425  * page is based on the number of 0's in the page. If the number of 0's in the page
6426  * being
6427  *
6428  * read is less than the value in the erase_threshold (programmable register),
6429  *
6430  * an erased page is inferred and no un-correctable error will be flagged for that
6431  * page.
6432  *
6433  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
6434  * If ECC is
6435  *
6436  * enabled, in addition to the above condition, only when the ECC logic detects an
6437  *
6438  * un-correctable error for that page will the erased_page interrupt be flagged. If
6439  * the ECC
6440  *
6441  * logic detects a no-error or correctable error page, this erased page interrupt
6442  * will not
6443  *
6444  * be set.
6445  *
6446  * Field Access Macros:
6447  *
6448  */
6449 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field. */
6450 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_LSB 16
6451 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field. */
6452 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_MSB 16
6453 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field. */
6454 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_WIDTH 1
6455 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field value. */
6456 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_SET_MSK 0x00010000
6457 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field value. */
6458 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_CLR_MSK 0xfffeffff
6459 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field. */
6460 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_RESET 0x0
6461 /* Extracts the ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE field value from a register. */
6462 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6463 /* Produces a ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE register field value suitable for setting the register. */
6464 #define ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6465 
6466 #ifndef __ASSEMBLY__
6467 /*
6468  * WARNING: The C register and register group struct declarations are provided for
6469  * convenience and illustrative purposes. They should, however, be used with
6470  * caution as the C language standard provides no guarantees about the alignment or
6471  * atomicity of device memory accesses. The recommended practice for coding device
6472  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6473  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6474  * alt_write_dword() functions for 64 bit registers.
6475  *
6476  * The struct declaration for register ALT_NAND_STAT_INTR_STATUS0.
6477  */
6478 struct ALT_NAND_STAT_INTR_STATUS0_s
6479 {
6480  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STATUS0_ECC_UNCOR_ERR */
6481  uint32_t : 1; /* *UNDEFINED* */
6482  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_DMA_CMD_COMP */
6483  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STATUS0_TIME_OUT */
6484  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STATUS0_PROGRAM_FAIL */
6485  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STATUS0_ERASE_FAIL */
6486  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_LOAD_COMP */
6487  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_PROGRAM_COMP */
6488  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_ERASE_COMP */
6489  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_PIPE_CPYBCK_CMD_COMP */
6490  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STATUS0_LOCKED_BLK */
6491  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STATUS0_UNSUP_CMD */
6492  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STATUS0_INT_ACT */
6493  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STATUS0_RST_COMP */
6494  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STATUS0_PIPE_CMD_ERR */
6495  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STATUS0_PAGE_XFER_INC */
6496  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STATUS0_ERASED_PAGE */
6497  uint32_t : 15; /* *UNDEFINED* */
6498 };
6499 
6500 /* The typedef declaration for register ALT_NAND_STAT_INTR_STATUS0. */
6501 typedef struct ALT_NAND_STAT_INTR_STATUS0_s ALT_NAND_STAT_INTR_STATUS0_t;
6502 #endif /* __ASSEMBLY__ */
6503 
6504 /* The reset value of the ALT_NAND_STAT_INTR_STATUS0 register. */
6505 #define ALT_NAND_STAT_INTR_STATUS0_RESET 0x00000000
6506 /* The byte offset of the ALT_NAND_STAT_INTR_STATUS0 register from the beginning of the component. */
6507 #define ALT_NAND_STAT_INTR_STATUS0_OFST 0x10
6508 /* The address of the ALT_NAND_STAT_INTR_STATUS0 register. */
6509 #define ALT_NAND_STAT_INTR_STATUS0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS0_OFST))
6510 
6511 /*
6512  * Register : intr_en0
6513  *
6514  * Enables corresponding interrupt bit in interrupt register
6515  *
6516  * for bank 0
6517  *
6518  * Register Layout
6519  *
6520  * Bits | Access | Reset | Description
6521  * :--------|:-------|:--------|:--------------------------------------------
6522  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR
6523  * [1] | ??? | Unknown | *UNDEFINED*
6524  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP
6525  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_TIME_OUT
6526  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL
6527  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_FAIL
6528  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LOAD_COMP
6529  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP
6530  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASE_COMP
6531  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP
6532  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_LOCKED_BLK
6533  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_UNSUP_CMD
6534  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_INT_ACT
6535  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN0_RST_COMP
6536  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR
6537  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC
6538  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN0_ERASED_PAGE
6539  * [31:17] | ??? | Unknown | *UNDEFINED*
6540  *
6541  */
6542 /*
6543  * Field : ecc_uncor_err
6544  *
6545  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
6546  * error.
6547  *
6548  * Field Access Macros:
6549  *
6550  */
6551 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6552 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
6553 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6554 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
6555 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6556 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
6557 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
6558 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6559 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value. */
6560 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6561 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field. */
6562 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
6563 /* Extracts the ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR field value from a register. */
6564 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6565 /* Produces a ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR register field value suitable for setting the register. */
6566 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6567 
6568 /*
6569  * Field : dma_cmd_comp
6570  *
6571  * A data DMA command has completed on this bank
6572  *
6573  * Field Access Macros:
6574  *
6575  */
6576 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6577 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
6578 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6579 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
6580 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6581 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
6582 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
6583 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
6584 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value. */
6585 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6586 /* The reset value of the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field. */
6587 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
6588 /* Extracts the ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP field value from a register. */
6589 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6590 /* Produces a ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP register field value suitable for setting the register. */
6591 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6592 
6593 /*
6594  * Field : time_out
6595  *
6596  * Watchdog timer has triggered in the controller due to one of the reasons like
6597  * device
6598  *
6599  * not responding or controller state machine did not get back to idle
6600  *
6601  * Field Access Macros:
6602  *
6603  */
6604 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6605 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
6606 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6607 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
6608 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6609 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
6610 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
6611 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
6612 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value. */
6613 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
6614 /* The reset value of the ALT_NAND_STAT_INTR_EN0_TIME_OUT register field. */
6615 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
6616 /* Extracts the ALT_NAND_STAT_INTR_EN0_TIME_OUT field value from a register. */
6617 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6618 /* Produces a ALT_NAND_STAT_INTR_EN0_TIME_OUT register field value suitable for setting the register. */
6619 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6620 
6621 /*
6622  * Field : program_fail
6623  *
6624  * Program failure occurred in the device on issuance of a program command.
6625  * err_block_addr
6626  *
6627  * and err_page_addr contain the block address and page address that failed program
6628  * operation.
6629  *
6630  * Field Access Macros:
6631  *
6632  */
6633 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6634 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
6635 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6636 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
6637 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6638 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
6639 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
6640 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
6641 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value. */
6642 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6643 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field. */
6644 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
6645 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL field value from a register. */
6646 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6647 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL register field value suitable for setting the register. */
6648 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6649 
6650 /*
6651  * Field : erase_fail
6652  *
6653  * Erase failure occurred in the device on issuance of a erase command.
6654  * err_block_addr
6655  *
6656  * and err_page_addr contain the block address and page address that failed erase
6657  * operation.
6658  *
6659  * Field Access Macros:
6660  *
6661  */
6662 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6663 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
6664 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6665 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
6666 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6667 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
6668 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
6669 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
6670 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value. */
6671 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
6672 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field. */
6673 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
6674 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_FAIL field value from a register. */
6675 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6676 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_FAIL register field value suitable for setting the register. */
6677 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6678 
6679 /*
6680  * Field : load_comp
6681  *
6682  * Device finished the last issued load command.
6683  *
6684  * Field Access Macros:
6685  *
6686  */
6687 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field. */
6688 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_LSB 6
6689 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field. */
6690 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_MSB 6
6691 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field. */
6692 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_WIDTH 1
6693 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field value. */
6694 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_SET_MSK 0x00000040
6695 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field value. */
6696 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_CLR_MSK 0xffffffbf
6697 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field. */
6698 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_RESET 0x0
6699 /* Extracts the ALT_NAND_STAT_INTR_EN0_LOAD_COMP field value from a register. */
6700 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6701 /* Produces a ALT_NAND_STAT_INTR_EN0_LOAD_COMP register field value suitable for setting the register. */
6702 #define ALT_NAND_STAT_INTR_EN0_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
6703 
6704 /*
6705  * Field : program_comp
6706  *
6707  * Device finished the last issued program command.
6708  *
6709  * Field Access Macros:
6710  *
6711  */
6712 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6713 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
6714 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6715 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
6716 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6717 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
6718 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
6719 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
6720 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value. */
6721 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6722 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field. */
6723 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
6724 /* Extracts the ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP field value from a register. */
6725 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6726 /* Produces a ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP register field value suitable for setting the register. */
6727 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6728 
6729 /*
6730  * Field : erase_comp
6731  *
6732  * Device erase operation complete
6733  *
6734  * Field Access Macros:
6735  *
6736  */
6737 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6738 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
6739 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6740 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
6741 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6742 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
6743 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
6744 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
6745 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value. */
6746 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
6747 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field. */
6748 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
6749 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASE_COMP field value from a register. */
6750 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6751 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASE_COMP register field value suitable for setting the register. */
6752 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6753 
6754 /*
6755  * Field : pipe_cpybck_cmd_comp
6756  *
6757  * A pipeline command or a copyback bank command has completed on this particular
6758  * bank
6759  *
6760  * Field Access Macros:
6761  *
6762  */
6763 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6764 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
6765 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6766 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
6767 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6768 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6769 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
6770 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6771 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value. */
6772 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6773 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field. */
6774 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6775 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP field value from a register. */
6776 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6777 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
6778 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6779 
6780 /*
6781  * Field : locked_blk
6782  *
6783  * The address to program or erase operation is to a locked block and the operation
6784  * failed
6785  *
6786  * due to this reason
6787  *
6788  * Field Access Macros:
6789  *
6790  */
6791 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6792 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
6793 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6794 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
6795 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6796 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
6797 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
6798 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
6799 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value. */
6800 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
6801 /* The reset value of the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field. */
6802 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
6803 /* Extracts the ALT_NAND_STAT_INTR_EN0_LOCKED_BLK field value from a register. */
6804 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6805 /* Produces a ALT_NAND_STAT_INTR_EN0_LOCKED_BLK register field value suitable for setting the register. */
6806 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6807 
6808 /*
6809  * Field : unsup_cmd
6810  *
6811  * An unsupported command was received. This interrupt is set when an invalid
6812  * command is
6813  *
6814  * received, or when a command sequence is broken.
6815  *
6816  * Field Access Macros:
6817  *
6818  */
6819 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6820 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
6821 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6822 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
6823 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6824 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
6825 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
6826 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
6827 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value. */
6828 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6829 /* The reset value of the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field. */
6830 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
6831 /* Extracts the ALT_NAND_STAT_INTR_EN0_UNSUP_CMD field value from a register. */
6832 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6833 /* Produces a ALT_NAND_STAT_INTR_EN0_UNSUP_CMD register field value suitable for setting the register. */
6834 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6835 
6836 /*
6837  * Field : int_act
6838  *
6839  * R/B pin of device transitioned from low to high
6840  *
6841  * Field Access Macros:
6842  *
6843  */
6844 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6845 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
6846 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6847 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
6848 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6849 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
6850 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
6851 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
6852 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_INT_ACT register field value. */
6853 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
6854 /* The reset value of the ALT_NAND_STAT_INTR_EN0_INT_ACT register field. */
6855 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
6856 /* Extracts the ALT_NAND_STAT_INTR_EN0_INT_ACT field value from a register. */
6857 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6858 /* Produces a ALT_NAND_STAT_INTR_EN0_INT_ACT register field value suitable for setting the register. */
6859 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6860 
6861 /*
6862  * Field : rst_comp
6863  *
6864  * A reset command has completed on this bank
6865  *
6866  * Field Access Macros:
6867  *
6868  */
6869 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6870 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
6871 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6872 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
6873 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6874 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
6875 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
6876 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
6877 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_RST_COMP register field value. */
6878 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
6879 /* The reset value of the ALT_NAND_STAT_INTR_EN0_RST_COMP register field. */
6880 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
6881 /* Extracts the ALT_NAND_STAT_INTR_EN0_RST_COMP field value from a register. */
6882 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6883 /* Produces a ALT_NAND_STAT_INTR_EN0_RST_COMP register field value suitable for setting the register. */
6884 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6885 
6886 /*
6887  * Field : pipe_cmd_err
6888  *
6889  * A pipeline command sequence has been violated. This occurs when Map 01 page
6890  * read/write
6891  *
6892  * address does not match the corresponding expected address from the pipeline
6893  * commands issued
6894  *
6895  * earlier.
6896  *
6897  * Field Access Macros:
6898  *
6899  */
6900 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6901 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
6902 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6903 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
6904 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6905 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
6906 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
6907 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
6908 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value. */
6909 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6910 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field. */
6911 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
6912 /* Extracts the ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR field value from a register. */
6913 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6914 /* Produces a ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR register field value suitable for setting the register. */
6915 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6916 
6917 /*
6918  * Field : page_xfer_inc
6919  *
6920  * For every page of data transfer to or from the device, this bit will be set.
6921  *
6922  * Field Access Macros:
6923  *
6924  */
6925 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6926 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
6927 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6928 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
6929 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6930 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
6931 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
6932 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
6933 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value. */
6934 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6935 /* The reset value of the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field. */
6936 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
6937 /* Extracts the ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC field value from a register. */
6938 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6939 /* Produces a ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC register field value suitable for setting the register. */
6940 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6941 
6942 /*
6943  * Field : erased_page
6944  *
6945  * If an erased page is detected on reads, this bit will be set. The detection of
6946  * erased
6947  *
6948  * page is based on the number of 0's in the page. If the number of 0's in the page
6949  * being
6950  *
6951  * read is less than the value in the erase_threshold (programmable register),
6952  *
6953  * an erased page is inferred and no un-correctable error will be flagged for that
6954  * page.
6955  *
6956  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
6957  * If ECC is
6958  *
6959  * enabled, in addition to the above condition, only when the ECC logic detects an
6960  *
6961  * un-correctable error for that page will the erased_page interrupt be flagged. If
6962  * the ECC
6963  *
6964  * logic detects a no-error or correctable error page, this erased page interrupt
6965  * will not
6966  *
6967  * be set.
6968  *
6969  * Field Access Macros:
6970  *
6971  */
6972 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6973 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_LSB 16
6974 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6975 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_MSB 16
6976 /* The width in bits of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6977 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_WIDTH 1
6978 /* The mask used to set the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value. */
6979 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET_MSK 0x00010000
6980 /* The mask used to clear the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value. */
6981 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_CLR_MSK 0xfffeffff
6982 /* The reset value of the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field. */
6983 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_RESET 0x0
6984 /* Extracts the ALT_NAND_STAT_INTR_EN0_ERASED_PAGE field value from a register. */
6985 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6986 /* Produces a ALT_NAND_STAT_INTR_EN0_ERASED_PAGE register field value suitable for setting the register. */
6987 #define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6988 
6989 #ifndef __ASSEMBLY__
6990 /*
6991  * WARNING: The C register and register group struct declarations are provided for
6992  * convenience and illustrative purposes. They should, however, be used with
6993  * caution as the C language standard provides no guarantees about the alignment or
6994  * atomicity of device memory accesses. The recommended practice for coding device
6995  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
6996  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
6997  * alt_write_dword() functions for 64 bit registers.
6998  *
6999  * The struct declaration for register ALT_NAND_STAT_INTR_EN0.
7000  */
7001 struct ALT_NAND_STAT_INTR_EN0_s
7002 {
7003  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR */
7004  uint32_t : 1; /* *UNDEFINED* */
7005  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP */
7006  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN0_TIME_OUT */
7007  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL */
7008  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_FAIL */
7009  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN0_LOAD_COMP */
7010  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP */
7011  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN0_ERASE_COMP */
7012  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP */
7013  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN0_LOCKED_BLK */
7014  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN0_UNSUP_CMD */
7015  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN0_INT_ACT */
7016  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN0_RST_COMP */
7017  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR */
7018  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC */
7019  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN0_ERASED_PAGE */
7020  uint32_t : 15; /* *UNDEFINED* */
7021 };
7022 
7023 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN0. */
7024 typedef struct ALT_NAND_STAT_INTR_EN0_s ALT_NAND_STAT_INTR_EN0_t;
7025 #endif /* __ASSEMBLY__ */
7026 
7027 /* The reset value of the ALT_NAND_STAT_INTR_EN0 register. */
7028 #define ALT_NAND_STAT_INTR_EN0_RESET 0x00002000
7029 /* The byte offset of the ALT_NAND_STAT_INTR_EN0 register from the beginning of the component. */
7030 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
7031 /* The address of the ALT_NAND_STAT_INTR_EN0 register. */
7032 #define ALT_NAND_STAT_INTR_EN0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN0_OFST))
7033 
7034 /*
7035  * Register : page_cnt0
7036  *
7037  * Decrementing page count bank 0
7038  *
7039  * Register Layout
7040  *
7041  * Bits | Access | Reset | Description
7042  * :-------|:-------|:--------|:------------------------------
7043  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT0_VALUE
7044  * [31:8] | ??? | Unknown | *UNDEFINED*
7045  *
7046  */
7047 /*
7048  * Field : value
7049  *
7050  * Maintains a decrementing count of the number of pages in
7051  *
7052  * the multi-page (pipeline and copyback) command being executed.
7053  *
7054  * Field Access Macros:
7055  *
7056  */
7057 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
7058 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
7059 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
7060 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
7061 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
7062 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
7063 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
7064 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
7065 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT0_VALUE register field value. */
7066 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
7067 /* The reset value of the ALT_NAND_STAT_PAGE_CNT0_VALUE register field. */
7068 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
7069 /* Extracts the ALT_NAND_STAT_PAGE_CNT0_VALUE field value from a register. */
7070 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
7071 /* Produces a ALT_NAND_STAT_PAGE_CNT0_VALUE register field value suitable for setting the register. */
7072 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
7073 
7074 #ifndef __ASSEMBLY__
7075 /*
7076  * WARNING: The C register and register group struct declarations are provided for
7077  * convenience and illustrative purposes. They should, however, be used with
7078  * caution as the C language standard provides no guarantees about the alignment or
7079  * atomicity of device memory accesses. The recommended practice for coding device
7080  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7081  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7082  * alt_write_dword() functions for 64 bit registers.
7083  *
7084  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT0.
7085  */
7086 struct ALT_NAND_STAT_PAGE_CNT0_s
7087 {
7088  const volatile uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT0_VALUE */
7089  uint32_t : 24; /* *UNDEFINED* */
7090 };
7091 
7092 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT0. */
7093 typedef struct ALT_NAND_STAT_PAGE_CNT0_s ALT_NAND_STAT_PAGE_CNT0_t;
7094 #endif /* __ASSEMBLY__ */
7095 
7096 /* The reset value of the ALT_NAND_STAT_PAGE_CNT0 register. */
7097 #define ALT_NAND_STAT_PAGE_CNT0_RESET 0x00000000
7098 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT0 register from the beginning of the component. */
7099 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
7100 /* The address of the ALT_NAND_STAT_PAGE_CNT0 register. */
7101 #define ALT_NAND_STAT_PAGE_CNT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT0_OFST))
7102 
7103 /*
7104  * Register : err_page_addr0
7105  *
7106  * Erred page address bank 0
7107  *
7108  * Register Layout
7109  *
7110  * Bits | Access | Reset | Description
7111  * :--------|:-------|:--------|:-----------------------------------
7112  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE
7113  * [31:16] | ??? | Unknown | *UNDEFINED*
7114  *
7115  */
7116 /*
7117  * Field : value
7118  *
7119  * Holds the page address that resulted in a failure on program
7120  *
7121  * or erase operation.
7122  *
7123  * Field Access Macros:
7124  *
7125  */
7126 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
7127 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
7128 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
7129 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
7130 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
7131 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
7132 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
7133 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
7134 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value. */
7135 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
7136 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field. */
7137 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
7138 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE field value from a register. */
7139 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7140 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE register field value suitable for setting the register. */
7141 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7142 
7143 #ifndef __ASSEMBLY__
7144 /*
7145  * WARNING: The C register and register group struct declarations are provided for
7146  * convenience and illustrative purposes. They should, however, be used with
7147  * caution as the C language standard provides no guarantees about the alignment or
7148  * atomicity of device memory accesses. The recommended practice for coding device
7149  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7150  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7151  * alt_write_dword() functions for 64 bit registers.
7152  *
7153  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0.
7154  */
7155 struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s
7156 {
7157  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE */
7158  uint32_t : 16; /* *UNDEFINED* */
7159 };
7160 
7161 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR0. */
7162 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR0_s ALT_NAND_STAT_ERR_PAGE_ADDR0_t;
7163 #endif /* __ASSEMBLY__ */
7164 
7165 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register. */
7166 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_RESET 0x00000000
7167 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register from the beginning of the component. */
7168 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
7169 /* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR0 register. */
7170 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST))
7171 
7172 /*
7173  * Register : err_block_addr0
7174  *
7175  * Erred block address bank 0
7176  *
7177  * Register Layout
7178  *
7179  * Bits | Access | Reset | Description
7180  * :--------|:-------|:--------|:------------------------------------
7181  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE
7182  * [31:16] | ??? | Unknown | *UNDEFINED*
7183  *
7184  */
7185 /*
7186  * Field : value
7187  *
7188  * Holds the block address that resulted in a failure on program
7189  *
7190  * or erase operation.
7191  *
7192  * Field Access Macros:
7193  *
7194  */
7195 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
7196 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
7197 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
7198 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
7199 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
7200 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
7201 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
7202 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
7203 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value. */
7204 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
7205 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field. */
7206 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
7207 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE field value from a register. */
7208 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7209 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE register field value suitable for setting the register. */
7210 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7211 
7212 #ifndef __ASSEMBLY__
7213 /*
7214  * WARNING: The C register and register group struct declarations are provided for
7215  * convenience and illustrative purposes. They should, however, be used with
7216  * caution as the C language standard provides no guarantees about the alignment or
7217  * atomicity of device memory accesses. The recommended practice for coding device
7218  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7219  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7220  * alt_write_dword() functions for 64 bit registers.
7221  *
7222  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0.
7223  */
7224 struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
7225 {
7226  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE */
7227  uint32_t : 16; /* *UNDEFINED* */
7228 };
7229 
7230 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR0. */
7231 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR0_s ALT_NAND_STAT_ERR_BLOCK_ADDR0_t;
7232 #endif /* __ASSEMBLY__ */
7233 
7234 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register. */
7235 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_RESET 0x00000000
7236 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register from the beginning of the component. */
7237 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
7238 /* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR0 register. */
7239 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST))
7240 
7241 /*
7242  * Register : intr_status1
7243  *
7244  * Interrupt status register for bank 1
7245  *
7246  * Register Layout
7247  *
7248  * Bits | Access | Reset | Description
7249  * :--------|:-------|:--------|:------------------------------------------------
7250  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR
7251  * [1] | ??? | Unknown | *UNDEFINED*
7252  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP
7253  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_TIME_OUT
7254  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL
7255  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL
7256  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP
7257  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP
7258  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP
7259  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP
7260  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK
7261  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD
7262  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_INT_ACT
7263  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_RST_COMP
7264  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR
7265  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC
7266  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE
7267  * [31:17] | ??? | Unknown | *UNDEFINED*
7268  *
7269  */
7270 /*
7271  * Field : ecc_uncor_err
7272  *
7273  * Ecc logic detected uncorrectable error while reading data from flash device.
7274  *
7275  * Field Access Macros:
7276  *
7277  */
7278 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field. */
7279 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_LSB 0
7280 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field. */
7281 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_MSB 0
7282 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field. */
7283 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_WIDTH 1
7284 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field value. */
7285 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7286 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field value. */
7287 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7288 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field. */
7289 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_RESET 0x0
7290 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR field value from a register. */
7291 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7292 /* Produces a ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR register field value suitable for setting the register. */
7293 #define ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7294 
7295 /*
7296  * Field : dma_cmd_comp
7297  *
7298  * A data DMA command has completed on this bank
7299  *
7300  * Field Access Macros:
7301  *
7302  */
7303 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field. */
7304 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_LSB 2
7305 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field. */
7306 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_MSB 2
7307 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field. */
7308 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_WIDTH 1
7309 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field value. */
7310 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_SET_MSK 0x00000004
7311 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field value. */
7312 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7313 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field. */
7314 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_RESET 0x0
7315 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP field value from a register. */
7316 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7317 /* Produces a ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP register field value suitable for setting the register. */
7318 #define ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7319 
7320 /*
7321  * Field : time_out
7322  *
7323  * Watchdog timer has triggered in the controller due to one of the reasons like
7324  * device
7325  *
7326  * not responding or controller state machine did not get back to idle
7327  *
7328  * Field Access Macros:
7329  *
7330  */
7331 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field. */
7332 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_LSB 3
7333 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field. */
7334 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_MSB 3
7335 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field. */
7336 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_WIDTH 1
7337 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field value. */
7338 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_SET_MSK 0x00000008
7339 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field value. */
7340 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_CLR_MSK 0xfffffff7
7341 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field. */
7342 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_RESET 0x0
7343 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_TIME_OUT field value from a register. */
7344 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7345 /* Produces a ALT_NAND_STAT_INTR_STATUS1_TIME_OUT register field value suitable for setting the register. */
7346 #define ALT_NAND_STAT_INTR_STATUS1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7347 
7348 /*
7349  * Field : program_fail
7350  *
7351  * Program failure occurred in the device on issuance of a program command.
7352  * err_block_addr
7353  *
7354  * and err_page_addr contain the block address and page address that failed program
7355  * operation.
7356  *
7357  * Field Access Macros:
7358  *
7359  */
7360 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field. */
7361 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_LSB 4
7362 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field. */
7363 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_MSB 4
7364 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field. */
7365 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_WIDTH 1
7366 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field value. */
7367 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_SET_MSK 0x00000010
7368 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field value. */
7369 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7370 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field. */
7371 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_RESET 0x0
7372 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL field value from a register. */
7373 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7374 /* Produces a ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL register field value suitable for setting the register. */
7375 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7376 
7377 /*
7378  * Field : erase_fail
7379  *
7380  * Erase failure occurred in the device on issuance of a erase command.
7381  * err_block_addr
7382  *
7383  * and err_page_addr contain the block address and page address that failed erase
7384  * operation.
7385  *
7386  * Field Access Macros:
7387  *
7388  */
7389 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field. */
7390 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_LSB 5
7391 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field. */
7392 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_MSB 5
7393 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field. */
7394 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_WIDTH 1
7395 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field value. */
7396 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_SET_MSK 0x00000020
7397 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field value. */
7398 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_CLR_MSK 0xffffffdf
7399 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field. */
7400 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_RESET 0x0
7401 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL field value from a register. */
7402 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7403 /* Produces a ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL register field value suitable for setting the register. */
7404 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7405 
7406 /*
7407  * Field : load_comp
7408  *
7409  * Device finished the last issued load command.
7410  *
7411  * Field Access Macros:
7412  *
7413  */
7414 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field. */
7415 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_LSB 6
7416 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field. */
7417 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_MSB 6
7418 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field. */
7419 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_WIDTH 1
7420 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field value. */
7421 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_SET_MSK 0x00000040
7422 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field value. */
7423 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_CLR_MSK 0xffffffbf
7424 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field. */
7425 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_RESET 0x0
7426 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP field value from a register. */
7427 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7428 /* Produces a ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP register field value suitable for setting the register. */
7429 #define ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
7430 
7431 /*
7432  * Field : program_comp
7433  *
7434  * Device finished the last issued program command.
7435  *
7436  * Field Access Macros:
7437  *
7438  */
7439 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field. */
7440 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_LSB 7
7441 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field. */
7442 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_MSB 7
7443 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field. */
7444 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_WIDTH 1
7445 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field value. */
7446 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_SET_MSK 0x00000080
7447 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field value. */
7448 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7449 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field. */
7450 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_RESET 0x0
7451 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP field value from a register. */
7452 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7453 /* Produces a ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP register field value suitable for setting the register. */
7454 #define ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7455 
7456 /*
7457  * Field : erase_comp
7458  *
7459  * Device erase operation complete
7460  *
7461  * Field Access Macros:
7462  *
7463  */
7464 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field. */
7465 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_LSB 8
7466 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field. */
7467 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_MSB 8
7468 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field. */
7469 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_WIDTH 1
7470 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field value. */
7471 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_SET_MSK 0x00000100
7472 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field value. */
7473 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_CLR_MSK 0xfffffeff
7474 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field. */
7475 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_RESET 0x0
7476 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP field value from a register. */
7477 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7478 /* Produces a ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP register field value suitable for setting the register. */
7479 #define ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7480 
7481 /*
7482  * Field : pipe_cpybck_cmd_comp
7483  *
7484  * A pipeline command or a copyback bank command has completed on this particular
7485  * bank
7486  *
7487  * Field Access Macros:
7488  *
7489  */
7490 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field. */
7491 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_LSB 9
7492 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field. */
7493 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_MSB 9
7494 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field. */
7495 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7496 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field value. */
7497 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7498 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field value. */
7499 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7500 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field. */
7501 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7502 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP field value from a register. */
7503 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7504 /* Produces a ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
7505 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7506 
7507 /*
7508  * Field : locked_blk
7509  *
7510  * The address to program or erase operation is to a locked block and the operation
7511  * failed
7512  *
7513  * due to this reason
7514  *
7515  * Field Access Macros:
7516  *
7517  */
7518 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field. */
7519 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_LSB 10
7520 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field. */
7521 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_MSB 10
7522 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field. */
7523 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_WIDTH 1
7524 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field value. */
7525 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_SET_MSK 0x00000400
7526 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field value. */
7527 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_CLR_MSK 0xfffffbff
7528 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field. */
7529 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_RESET 0x0
7530 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK field value from a register. */
7531 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7532 /* Produces a ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK register field value suitable for setting the register. */
7533 #define ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7534 
7535 /*
7536  * Field : unsup_cmd
7537  *
7538  * An unsupported command was received. This interrupt is set when an invalid
7539  * command is
7540  *
7541  * received, or when a command sequence is broken.
7542  *
7543  * Field Access Macros:
7544  *
7545  */
7546 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field. */
7547 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_LSB 11
7548 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field. */
7549 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_MSB 11
7550 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field. */
7551 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_WIDTH 1
7552 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field value. */
7553 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_SET_MSK 0x00000800
7554 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field value. */
7555 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7556 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field. */
7557 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_RESET 0x0
7558 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD field value from a register. */
7559 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7560 /* Produces a ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD register field value suitable for setting the register. */
7561 #define ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7562 
7563 /*
7564  * Field : int_act
7565  *
7566  * R/B pin of device transitioned from low to high
7567  *
7568  * Field Access Macros:
7569  *
7570  */
7571 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field. */
7572 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_LSB 12
7573 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field. */
7574 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_MSB 12
7575 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field. */
7576 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_WIDTH 1
7577 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field value. */
7578 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_SET_MSK 0x00001000
7579 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field value. */
7580 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_CLR_MSK 0xffffefff
7581 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field. */
7582 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_RESET 0x0
7583 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_INT_ACT field value from a register. */
7584 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7585 /* Produces a ALT_NAND_STAT_INTR_STATUS1_INT_ACT register field value suitable for setting the register. */
7586 #define ALT_NAND_STAT_INTR_STATUS1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7587 
7588 /*
7589  * Field : rst_comp
7590  *
7591  * The Cadence NAND Flash Memory Controller has completed its reset and
7592  * initialization process
7593  *
7594  * Field Access Macros:
7595  *
7596  */
7597 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field. */
7598 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_LSB 13
7599 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field. */
7600 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_MSB 13
7601 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field. */
7602 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_WIDTH 1
7603 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field value. */
7604 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_SET_MSK 0x00002000
7605 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field value. */
7606 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_CLR_MSK 0xffffdfff
7607 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field. */
7608 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_RESET 0x0
7609 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_RST_COMP field value from a register. */
7610 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7611 /* Produces a ALT_NAND_STAT_INTR_STATUS1_RST_COMP register field value suitable for setting the register. */
7612 #define ALT_NAND_STAT_INTR_STATUS1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7613 
7614 /*
7615  * Field : pipe_cmd_err
7616  *
7617  * A pipeline command sequence has been violated. This occurs when Map 01 page
7618  * read/write
7619  *
7620  * address does not match the corresponding expected address from the pipeline
7621  * commands issued
7622  *
7623  * earlier.
7624  *
7625  * Field Access Macros:
7626  *
7627  */
7628 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field. */
7629 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_LSB 14
7630 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field. */
7631 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_MSB 14
7632 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field. */
7633 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_WIDTH 1
7634 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field value. */
7635 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_SET_MSK 0x00004000
7636 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field value. */
7637 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7638 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field. */
7639 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_RESET 0x0
7640 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR field value from a register. */
7641 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7642 /* Produces a ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR register field value suitable for setting the register. */
7643 #define ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7644 
7645 /*
7646  * Field : page_xfer_inc
7647  *
7648  * For every page of data transfer to or from the device, this bit will be set.
7649  *
7650  * Field Access Macros:
7651  *
7652  */
7653 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field. */
7654 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_LSB 15
7655 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field. */
7656 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_MSB 15
7657 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field. */
7658 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_WIDTH 1
7659 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field value. */
7660 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_SET_MSK 0x00008000
7661 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field value. */
7662 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7663 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field. */
7664 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_RESET 0x0
7665 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC field value from a register. */
7666 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7667 /* Produces a ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC register field value suitable for setting the register. */
7668 #define ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7669 
7670 /*
7671  * Field : erased_page
7672  *
7673  * If an erased page is detected on reads, this bit will be set. The detection of
7674  * erased
7675  *
7676  * page is based on the number of 0's in the page. If the number of 0's in the page
7677  * being
7678  *
7679  * read is less than the value in the erase_threshold (programmable register),
7680  *
7681  * an erased page is inferred and no un-correctable error will be flagged for that
7682  * page.
7683  *
7684  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
7685  * If ECC is
7686  *
7687  * enabled, in addition to the above condition, only when the ECC logic detects an
7688  *
7689  * un-correctable error for that page will the erased_page interrupt be flagged. If
7690  * the ECC
7691  *
7692  * logic detects a no-error or correctable error page, this erased page interrupt
7693  * will not
7694  *
7695  * be set.
7696  *
7697  * Field Access Macros:
7698  *
7699  */
7700 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field. */
7701 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_LSB 16
7702 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field. */
7703 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_MSB 16
7704 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field. */
7705 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_WIDTH 1
7706 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field value. */
7707 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_SET_MSK 0x00010000
7708 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field value. */
7709 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_CLR_MSK 0xfffeffff
7710 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field. */
7711 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_RESET 0x0
7712 /* Extracts the ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE field value from a register. */
7713 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
7714 /* Produces a ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE register field value suitable for setting the register. */
7715 #define ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
7716 
7717 #ifndef __ASSEMBLY__
7718 /*
7719  * WARNING: The C register and register group struct declarations are provided for
7720  * convenience and illustrative purposes. They should, however, be used with
7721  * caution as the C language standard provides no guarantees about the alignment or
7722  * atomicity of device memory accesses. The recommended practice for coding device
7723  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
7724  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
7725  * alt_write_dword() functions for 64 bit registers.
7726  *
7727  * The struct declaration for register ALT_NAND_STAT_INTR_STATUS1.
7728  */
7729 struct ALT_NAND_STAT_INTR_STATUS1_s
7730 {
7731  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STATUS1_ECC_UNCOR_ERR */
7732  uint32_t : 1; /* *UNDEFINED* */
7733  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_DMA_CMD_COMP */
7734  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STATUS1_TIME_OUT */
7735  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STATUS1_PROGRAM_FAIL */
7736  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STATUS1_ERASE_FAIL */
7737  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_LOAD_COMP */
7738  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_PROGRAM_COMP */
7739  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_ERASE_COMP */
7740  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_PIPE_CPYBCK_CMD_COMP */
7741  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STATUS1_LOCKED_BLK */
7742  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STATUS1_UNSUP_CMD */
7743  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STATUS1_INT_ACT */
7744  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STATUS1_RST_COMP */
7745  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STATUS1_PIPE_CMD_ERR */
7746  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STATUS1_PAGE_XFER_INC */
7747  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STATUS1_ERASED_PAGE */
7748  uint32_t : 15; /* *UNDEFINED* */
7749 };
7750 
7751 /* The typedef declaration for register ALT_NAND_STAT_INTR_STATUS1. */
7752 typedef struct ALT_NAND_STAT_INTR_STATUS1_s ALT_NAND_STAT_INTR_STATUS1_t;
7753 #endif /* __ASSEMBLY__ */
7754 
7755 /* The reset value of the ALT_NAND_STAT_INTR_STATUS1 register. */
7756 #define ALT_NAND_STAT_INTR_STATUS1_RESET 0x00000000
7757 /* The byte offset of the ALT_NAND_STAT_INTR_STATUS1 register from the beginning of the component. */
7758 #define ALT_NAND_STAT_INTR_STATUS1_OFST 0x60
7759 /* The address of the ALT_NAND_STAT_INTR_STATUS1 register. */
7760 #define ALT_NAND_STAT_INTR_STATUS1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS1_OFST))
7761 
7762 /*
7763  * Register : intr_en1
7764  *
7765  * Enables corresponding interrupt bit in interrupt register
7766  *
7767  * for bank 1
7768  *
7769  * Register Layout
7770  *
7771  * Bits | Access | Reset | Description
7772  * :--------|:-------|:--------|:--------------------------------------------
7773  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR
7774  * [1] | ??? | Unknown | *UNDEFINED*
7775  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP
7776  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_TIME_OUT
7777  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL
7778  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_FAIL
7779  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LOAD_COMP
7780  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP
7781  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASE_COMP
7782  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP
7783  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_LOCKED_BLK
7784  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_UNSUP_CMD
7785  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_INT_ACT
7786  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN1_RST_COMP
7787  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR
7788  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC
7789  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN1_ERASED_PAGE
7790  * [31:17] | ??? | Unknown | *UNDEFINED*
7791  *
7792  */
7793 /*
7794  * Field : ecc_uncor_err
7795  *
7796  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
7797  * error.
7798  *
7799  * Field Access Macros:
7800  *
7801  */
7802 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7803 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
7804 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7805 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
7806 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7807 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
7808 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
7809 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7810 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value. */
7811 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7812 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field. */
7813 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
7814 /* Extracts the ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR field value from a register. */
7815 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7816 /* Produces a ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR register field value suitable for setting the register. */
7817 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7818 
7819 /*
7820  * Field : dma_cmd_comp
7821  *
7822  * A data DMA command has completed on this bank
7823  *
7824  * Field Access Macros:
7825  *
7826  */
7827 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7828 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
7829 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7830 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
7831 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7832 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
7833 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
7834 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
7835 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value. */
7836 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7837 /* The reset value of the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field. */
7838 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
7839 /* Extracts the ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP field value from a register. */
7840 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7841 /* Produces a ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP register field value suitable for setting the register. */
7842 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7843 
7844 /*
7845  * Field : time_out
7846  *
7847  * Watchdog timer has triggered in the controller due to one of the reasons like
7848  * device
7849  *
7850  * not responding or controller state machine did not get back to idle
7851  *
7852  * Field Access Macros:
7853  *
7854  */
7855 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7856 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
7857 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7858 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
7859 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7860 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
7861 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
7862 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
7863 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value. */
7864 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
7865 /* The reset value of the ALT_NAND_STAT_INTR_EN1_TIME_OUT register field. */
7866 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
7867 /* Extracts the ALT_NAND_STAT_INTR_EN1_TIME_OUT field value from a register. */
7868 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7869 /* Produces a ALT_NAND_STAT_INTR_EN1_TIME_OUT register field value suitable for setting the register. */
7870 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7871 
7872 /*
7873  * Field : program_fail
7874  *
7875  * Program failure occurred in the device on issuance of a program command.
7876  * err_block_addr
7877  *
7878  * and err_page_addr contain the block address and page address that failed program
7879  * operation.
7880  *
7881  * Field Access Macros:
7882  *
7883  */
7884 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7885 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
7886 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7887 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
7888 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7889 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
7890 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
7891 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
7892 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value. */
7893 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7894 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field. */
7895 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
7896 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL field value from a register. */
7897 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7898 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL register field value suitable for setting the register. */
7899 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7900 
7901 /*
7902  * Field : erase_fail
7903  *
7904  * Erase failure occurred in the device on issuance of a erase command.
7905  * err_block_addr
7906  *
7907  * and err_page_addr contain the block address and page address that failed erase
7908  * operation.
7909  *
7910  * Field Access Macros:
7911  *
7912  */
7913 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7914 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
7915 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7916 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
7917 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7918 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
7919 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
7920 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
7921 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value. */
7922 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
7923 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field. */
7924 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
7925 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_FAIL field value from a register. */
7926 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7927 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_FAIL register field value suitable for setting the register. */
7928 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7929 
7930 /*
7931  * Field : load_comp
7932  *
7933  * Device finished the last issued load command.
7934  *
7935  * Field Access Macros:
7936  *
7937  */
7938 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field. */
7939 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_LSB 6
7940 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field. */
7941 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_MSB 6
7942 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field. */
7943 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_WIDTH 1
7944 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field value. */
7945 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_SET_MSK 0x00000040
7946 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field value. */
7947 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_CLR_MSK 0xffffffbf
7948 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field. */
7949 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_RESET 0x0
7950 /* Extracts the ALT_NAND_STAT_INTR_EN1_LOAD_COMP field value from a register. */
7951 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7952 /* Produces a ALT_NAND_STAT_INTR_EN1_LOAD_COMP register field value suitable for setting the register. */
7953 #define ALT_NAND_STAT_INTR_EN1_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
7954 
7955 /*
7956  * Field : program_comp
7957  *
7958  * Device finished the last issued program command.
7959  *
7960  * Field Access Macros:
7961  *
7962  */
7963 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7964 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
7965 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7966 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
7967 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7968 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
7969 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
7970 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
7971 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value. */
7972 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7973 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field. */
7974 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
7975 /* Extracts the ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP field value from a register. */
7976 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7977 /* Produces a ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP register field value suitable for setting the register. */
7978 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7979 
7980 /*
7981  * Field : erase_comp
7982  *
7983  * Device erase operation complete
7984  *
7985  * Field Access Macros:
7986  *
7987  */
7988 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7989 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
7990 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7991 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
7992 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7993 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
7994 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
7995 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
7996 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value. */
7997 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
7998 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field. */
7999 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
8000 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASE_COMP field value from a register. */
8001 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8002 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASE_COMP register field value suitable for setting the register. */
8003 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8004 
8005 /*
8006  * Field : pipe_cpybck_cmd_comp
8007  *
8008  * A pipeline command or a copyback bank command has completed on this particular
8009  * bank
8010  *
8011  * Field Access Macros:
8012  *
8013  */
8014 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
8015 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
8016 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
8017 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
8018 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
8019 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8020 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
8021 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8022 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value. */
8023 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8024 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field. */
8025 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8026 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP field value from a register. */
8027 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8028 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
8029 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8030 
8031 /*
8032  * Field : locked_blk
8033  *
8034  * The address to program or erase operation is to a locked block and the operation
8035  * failed
8036  *
8037  * due to this reason
8038  *
8039  * Field Access Macros:
8040  *
8041  */
8042 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
8043 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
8044 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
8045 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
8046 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
8047 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
8048 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
8049 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
8050 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value. */
8051 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
8052 /* The reset value of the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field. */
8053 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
8054 /* Extracts the ALT_NAND_STAT_INTR_EN1_LOCKED_BLK field value from a register. */
8055 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8056 /* Produces a ALT_NAND_STAT_INTR_EN1_LOCKED_BLK register field value suitable for setting the register. */
8057 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8058 
8059 /*
8060  * Field : unsup_cmd
8061  *
8062  * An unsupported command was received. This interrupt is set when an invalid
8063  * command is
8064  *
8065  * received, or when a command sequence is broken.
8066  *
8067  * Field Access Macros:
8068  *
8069  */
8070 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
8071 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
8072 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
8073 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
8074 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
8075 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
8076 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
8077 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
8078 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value. */
8079 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
8080 /* The reset value of the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field. */
8081 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
8082 /* Extracts the ALT_NAND_STAT_INTR_EN1_UNSUP_CMD field value from a register. */
8083 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8084 /* Produces a ALT_NAND_STAT_INTR_EN1_UNSUP_CMD register field value suitable for setting the register. */
8085 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8086 
8087 /*
8088  * Field : int_act
8089  *
8090  * R/B pin of device transitioned from low to high
8091  *
8092  * Field Access Macros:
8093  *
8094  */
8095 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
8096 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
8097 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
8098 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
8099 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
8100 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
8101 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
8102 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
8103 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_INT_ACT register field value. */
8104 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
8105 /* The reset value of the ALT_NAND_STAT_INTR_EN1_INT_ACT register field. */
8106 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
8107 /* Extracts the ALT_NAND_STAT_INTR_EN1_INT_ACT field value from a register. */
8108 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8109 /* Produces a ALT_NAND_STAT_INTR_EN1_INT_ACT register field value suitable for setting the register. */
8110 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8111 
8112 /*
8113  * Field : rst_comp
8114  *
8115  * A reset command has completed on this bank
8116  *
8117  * Field Access Macros:
8118  *
8119  */
8120 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
8121 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
8122 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
8123 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
8124 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
8125 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
8126 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
8127 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
8128 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_RST_COMP register field value. */
8129 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
8130 /* The reset value of the ALT_NAND_STAT_INTR_EN1_RST_COMP register field. */
8131 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
8132 /* Extracts the ALT_NAND_STAT_INTR_EN1_RST_COMP field value from a register. */
8133 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8134 /* Produces a ALT_NAND_STAT_INTR_EN1_RST_COMP register field value suitable for setting the register. */
8135 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8136 
8137 /*
8138  * Field : pipe_cmd_err
8139  *
8140  * A pipeline command sequence has been violated. This occurs when Map 01 page
8141  * read/write
8142  *
8143  * address does not match the corresponding expected address from the pipeline
8144  * commands issued
8145  *
8146  * earlier.
8147  *
8148  * Field Access Macros:
8149  *
8150  */
8151 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
8152 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
8153 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
8154 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
8155 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
8156 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
8157 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
8158 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
8159 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value. */
8160 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8161 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field. */
8162 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
8163 /* Extracts the ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR field value from a register. */
8164 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8165 /* Produces a ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR register field value suitable for setting the register. */
8166 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8167 
8168 /*
8169  * Field : page_xfer_inc
8170  *
8171  * For every page of data transfer to or from the device, this bit will be set.
8172  *
8173  * Field Access Macros:
8174  *
8175  */
8176 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
8177 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
8178 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
8179 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
8180 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
8181 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
8182 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
8183 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
8184 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value. */
8185 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8186 /* The reset value of the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field. */
8187 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
8188 /* Extracts the ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC field value from a register. */
8189 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8190 /* Produces a ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC register field value suitable for setting the register. */
8191 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8192 
8193 /*
8194  * Field : erased_page
8195  *
8196  * If an erased page is detected on reads, this bit will be set. The detection of
8197  * erased
8198  *
8199  * page is based on the number of 0's in the page. If the number of 0's in the page
8200  * being
8201  *
8202  * read is less than the value in the erase_threshold (programmable register),
8203  *
8204  * an erased page is inferred and no un-correctable error will be flagged for that
8205  * page.
8206  *
8207  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
8208  * If ECC is
8209  *
8210  * enabled, in addition to the above condition, only when the ECC logic detects an
8211  *
8212  * un-correctable error for that page will the erased_page interrupt be flagged. If
8213  * the ECC
8214  *
8215  * logic detects a no-error or correctable error page, this erased page interrupt
8216  * will not
8217  *
8218  * be set.
8219  *
8220  * Field Access Macros:
8221  *
8222  */
8223 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8224 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_LSB 16
8225 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8226 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_MSB 16
8227 /* The width in bits of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8228 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_WIDTH 1
8229 /* The mask used to set the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value. */
8230 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET_MSK 0x00010000
8231 /* The mask used to clear the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value. */
8232 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_CLR_MSK 0xfffeffff
8233 /* The reset value of the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field. */
8234 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_RESET 0x0
8235 /* Extracts the ALT_NAND_STAT_INTR_EN1_ERASED_PAGE field value from a register. */
8236 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8237 /* Produces a ALT_NAND_STAT_INTR_EN1_ERASED_PAGE register field value suitable for setting the register. */
8238 #define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8239 
8240 #ifndef __ASSEMBLY__
8241 /*
8242  * WARNING: The C register and register group struct declarations are provided for
8243  * convenience and illustrative purposes. They should, however, be used with
8244  * caution as the C language standard provides no guarantees about the alignment or
8245  * atomicity of device memory accesses. The recommended practice for coding device
8246  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8247  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8248  * alt_write_dword() functions for 64 bit registers.
8249  *
8250  * The struct declaration for register ALT_NAND_STAT_INTR_EN1.
8251  */
8252 struct ALT_NAND_STAT_INTR_EN1_s
8253 {
8254  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR */
8255  uint32_t : 1; /* *UNDEFINED* */
8256  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP */
8257  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN1_TIME_OUT */
8258  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL */
8259  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_FAIL */
8260  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN1_LOAD_COMP */
8261  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP */
8262  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN1_ERASE_COMP */
8263  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP */
8264  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN1_LOCKED_BLK */
8265  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN1_UNSUP_CMD */
8266  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN1_INT_ACT */
8267  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN1_RST_COMP */
8268  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR */
8269  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC */
8270  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN1_ERASED_PAGE */
8271  uint32_t : 15; /* *UNDEFINED* */
8272 };
8273 
8274 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN1. */
8275 typedef struct ALT_NAND_STAT_INTR_EN1_s ALT_NAND_STAT_INTR_EN1_t;
8276 #endif /* __ASSEMBLY__ */
8277 
8278 /* The reset value of the ALT_NAND_STAT_INTR_EN1 register. */
8279 #define ALT_NAND_STAT_INTR_EN1_RESET 0x00002000
8280 /* The byte offset of the ALT_NAND_STAT_INTR_EN1 register from the beginning of the component. */
8281 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
8282 /* The address of the ALT_NAND_STAT_INTR_EN1 register. */
8283 #define ALT_NAND_STAT_INTR_EN1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN1_OFST))
8284 
8285 /*
8286  * Register : page_cnt1
8287  *
8288  * Decrementing page count bank 1
8289  *
8290  * Register Layout
8291  *
8292  * Bits | Access | Reset | Description
8293  * :-------|:-------|:--------|:------------------------------
8294  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT1_VALUE
8295  * [31:8] | ??? | Unknown | *UNDEFINED*
8296  *
8297  */
8298 /*
8299  * Field : value
8300  *
8301  * Maintains a decrementing count of the number of pages in
8302  *
8303  * the multi-page (pipeline and copyback) command being executed.
8304  *
8305  * Field Access Macros:
8306  *
8307  */
8308 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8309 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
8310 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8311 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
8312 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8313 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
8314 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
8315 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
8316 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT1_VALUE register field value. */
8317 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
8318 /* The reset value of the ALT_NAND_STAT_PAGE_CNT1_VALUE register field. */
8319 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
8320 /* Extracts the ALT_NAND_STAT_PAGE_CNT1_VALUE field value from a register. */
8321 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8322 /* Produces a ALT_NAND_STAT_PAGE_CNT1_VALUE register field value suitable for setting the register. */
8323 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8324 
8325 #ifndef __ASSEMBLY__
8326 /*
8327  * WARNING: The C register and register group struct declarations are provided for
8328  * convenience and illustrative purposes. They should, however, be used with
8329  * caution as the C language standard provides no guarantees about the alignment or
8330  * atomicity of device memory accesses. The recommended practice for coding device
8331  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8332  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8333  * alt_write_dword() functions for 64 bit registers.
8334  *
8335  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT1.
8336  */
8337 struct ALT_NAND_STAT_PAGE_CNT1_s
8338 {
8339  const volatile uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT1_VALUE */
8340  uint32_t : 24; /* *UNDEFINED* */
8341 };
8342 
8343 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT1. */
8344 typedef struct ALT_NAND_STAT_PAGE_CNT1_s ALT_NAND_STAT_PAGE_CNT1_t;
8345 #endif /* __ASSEMBLY__ */
8346 
8347 /* The reset value of the ALT_NAND_STAT_PAGE_CNT1 register. */
8348 #define ALT_NAND_STAT_PAGE_CNT1_RESET 0x00000000
8349 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT1 register from the beginning of the component. */
8350 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
8351 /* The address of the ALT_NAND_STAT_PAGE_CNT1 register. */
8352 #define ALT_NAND_STAT_PAGE_CNT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT1_OFST))
8353 
8354 /*
8355  * Register : err_page_addr1
8356  *
8357  * Erred page address bank 1
8358  *
8359  * Register Layout
8360  *
8361  * Bits | Access | Reset | Description
8362  * :--------|:-------|:--------|:-----------------------------------
8363  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE
8364  * [31:16] | ??? | Unknown | *UNDEFINED*
8365  *
8366  */
8367 /*
8368  * Field : value
8369  *
8370  * Holds the page address that resulted in a failure on program
8371  *
8372  * or erase operation.
8373  *
8374  * Field Access Macros:
8375  *
8376  */
8377 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8378 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
8379 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8380 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
8381 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8382 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
8383 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
8384 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
8385 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value. */
8386 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
8387 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field. */
8388 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
8389 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE field value from a register. */
8390 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8391 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE register field value suitable for setting the register. */
8392 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8393 
8394 #ifndef __ASSEMBLY__
8395 /*
8396  * WARNING: The C register and register group struct declarations are provided for
8397  * convenience and illustrative purposes. They should, however, be used with
8398  * caution as the C language standard provides no guarantees about the alignment or
8399  * atomicity of device memory accesses. The recommended practice for coding device
8400  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8401  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8402  * alt_write_dword() functions for 64 bit registers.
8403  *
8404  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1.
8405  */
8406 struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s
8407 {
8408  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE */
8409  uint32_t : 16; /* *UNDEFINED* */
8410 };
8411 
8412 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR1. */
8413 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR1_s ALT_NAND_STAT_ERR_PAGE_ADDR1_t;
8414 #endif /* __ASSEMBLY__ */
8415 
8416 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register. */
8417 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_RESET 0x00000000
8418 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register from the beginning of the component. */
8419 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
8420 /* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR1 register. */
8421 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST))
8422 
8423 /*
8424  * Register : err_block_addr1
8425  *
8426  * Erred block address bank 1
8427  *
8428  * Register Layout
8429  *
8430  * Bits | Access | Reset | Description
8431  * :--------|:-------|:--------|:------------------------------------
8432  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE
8433  * [31:16] | ??? | Unknown | *UNDEFINED*
8434  *
8435  */
8436 /*
8437  * Field : value
8438  *
8439  * Holds the block address that resulted in a failure on program
8440  *
8441  * or erase operation.
8442  *
8443  * Field Access Macros:
8444  *
8445  */
8446 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8447 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
8448 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8449 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
8450 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8451 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
8452 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
8453 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
8454 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value. */
8455 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
8456 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field. */
8457 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
8458 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE field value from a register. */
8459 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8460 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE register field value suitable for setting the register. */
8461 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8462 
8463 #ifndef __ASSEMBLY__
8464 /*
8465  * WARNING: The C register and register group struct declarations are provided for
8466  * convenience and illustrative purposes. They should, however, be used with
8467  * caution as the C language standard provides no guarantees about the alignment or
8468  * atomicity of device memory accesses. The recommended practice for coding device
8469  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8470  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8471  * alt_write_dword() functions for 64 bit registers.
8472  *
8473  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1.
8474  */
8475 struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
8476 {
8477  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE */
8478  uint32_t : 16; /* *UNDEFINED* */
8479 };
8480 
8481 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR1. */
8482 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR1_s ALT_NAND_STAT_ERR_BLOCK_ADDR1_t;
8483 #endif /* __ASSEMBLY__ */
8484 
8485 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register. */
8486 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_RESET 0x00000000
8487 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register from the beginning of the component. */
8488 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
8489 /* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR1 register. */
8490 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST))
8491 
8492 /*
8493  * Register : intr_status2
8494  *
8495  * Interrupt status register for bank 2
8496  *
8497  * Register Layout
8498  *
8499  * Bits | Access | Reset | Description
8500  * :--------|:-------|:--------|:------------------------------------------------
8501  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR
8502  * [1] | ??? | Unknown | *UNDEFINED*
8503  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP
8504  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_TIME_OUT
8505  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL
8506  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL
8507  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP
8508  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP
8509  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP
8510  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP
8511  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK
8512  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD
8513  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_INT_ACT
8514  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_RST_COMP
8515  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR
8516  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC
8517  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE
8518  * [31:17] | ??? | Unknown | *UNDEFINED*
8519  *
8520  */
8521 /*
8522  * Field : ecc_uncor_err
8523  *
8524  * Ecc logic detected uncorrectable error while reading data from flash device.
8525  *
8526  * Field Access Macros:
8527  *
8528  */
8529 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field. */
8530 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_LSB 0
8531 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field. */
8532 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_MSB 0
8533 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field. */
8534 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_WIDTH 1
8535 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field value. */
8536 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8537 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field value. */
8538 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8539 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field. */
8540 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_RESET 0x0
8541 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR field value from a register. */
8542 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8543 /* Produces a ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR register field value suitable for setting the register. */
8544 #define ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8545 
8546 /*
8547  * Field : dma_cmd_comp
8548  *
8549  * A data DMA command has completed on this bank
8550  *
8551  * Field Access Macros:
8552  *
8553  */
8554 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field. */
8555 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_LSB 2
8556 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field. */
8557 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_MSB 2
8558 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field. */
8559 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_WIDTH 1
8560 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field value. */
8561 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_SET_MSK 0x00000004
8562 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field value. */
8563 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8564 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field. */
8565 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_RESET 0x0
8566 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP field value from a register. */
8567 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8568 /* Produces a ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP register field value suitable for setting the register. */
8569 #define ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8570 
8571 /*
8572  * Field : time_out
8573  *
8574  * Watchdog timer has triggered in the controller due to one of the reasons like
8575  * device
8576  *
8577  * not responding or controller state machine did not get back to idle
8578  *
8579  * Field Access Macros:
8580  *
8581  */
8582 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field. */
8583 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_LSB 3
8584 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field. */
8585 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_MSB 3
8586 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field. */
8587 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_WIDTH 1
8588 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field value. */
8589 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_SET_MSK 0x00000008
8590 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field value. */
8591 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_CLR_MSK 0xfffffff7
8592 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field. */
8593 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_RESET 0x0
8594 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_TIME_OUT field value from a register. */
8595 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8596 /* Produces a ALT_NAND_STAT_INTR_STATUS2_TIME_OUT register field value suitable for setting the register. */
8597 #define ALT_NAND_STAT_INTR_STATUS2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8598 
8599 /*
8600  * Field : program_fail
8601  *
8602  * Program failure occurred in the device on issuance of a program command.
8603  * err_block_addr
8604  *
8605  * and err_page_addr contain the block address and page address that failed program
8606  * operation.
8607  *
8608  * Field Access Macros:
8609  *
8610  */
8611 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field. */
8612 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_LSB 4
8613 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field. */
8614 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_MSB 4
8615 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field. */
8616 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_WIDTH 1
8617 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field value. */
8618 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_SET_MSK 0x00000010
8619 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field value. */
8620 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8621 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field. */
8622 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_RESET 0x0
8623 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL field value from a register. */
8624 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8625 /* Produces a ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL register field value suitable for setting the register. */
8626 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8627 
8628 /*
8629  * Field : erase_fail
8630  *
8631  * Erase failure occurred in the device on issuance of a erase command.
8632  * err_block_addr
8633  *
8634  * and err_page_addr contain the block address and page address that failed erase
8635  * operation.
8636  *
8637  * Field Access Macros:
8638  *
8639  */
8640 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field. */
8641 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_LSB 5
8642 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field. */
8643 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_MSB 5
8644 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field. */
8645 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_WIDTH 1
8646 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field value. */
8647 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_SET_MSK 0x00000020
8648 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field value. */
8649 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_CLR_MSK 0xffffffdf
8650 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field. */
8651 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_RESET 0x0
8652 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL field value from a register. */
8653 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8654 /* Produces a ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL register field value suitable for setting the register. */
8655 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8656 
8657 /*
8658  * Field : load_comp
8659  *
8660  * Device finished the last issued load command.
8661  *
8662  * Field Access Macros:
8663  *
8664  */
8665 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field. */
8666 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_LSB 6
8667 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field. */
8668 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_MSB 6
8669 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field. */
8670 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_WIDTH 1
8671 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field value. */
8672 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_SET_MSK 0x00000040
8673 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field value. */
8674 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_CLR_MSK 0xffffffbf
8675 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field. */
8676 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_RESET 0x0
8677 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP field value from a register. */
8678 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8679 /* Produces a ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP register field value suitable for setting the register. */
8680 #define ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
8681 
8682 /*
8683  * Field : program_comp
8684  *
8685  * Device finished the last issued program command.
8686  *
8687  * Field Access Macros:
8688  *
8689  */
8690 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field. */
8691 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_LSB 7
8692 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field. */
8693 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_MSB 7
8694 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field. */
8695 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_WIDTH 1
8696 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field value. */
8697 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_SET_MSK 0x00000080
8698 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field value. */
8699 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8700 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field. */
8701 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_RESET 0x0
8702 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP field value from a register. */
8703 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8704 /* Produces a ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP register field value suitable for setting the register. */
8705 #define ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8706 
8707 /*
8708  * Field : erase_comp
8709  *
8710  * Device erase operation complete
8711  *
8712  * Field Access Macros:
8713  *
8714  */
8715 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field. */
8716 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_LSB 8
8717 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field. */
8718 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_MSB 8
8719 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field. */
8720 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_WIDTH 1
8721 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field value. */
8722 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_SET_MSK 0x00000100
8723 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field value. */
8724 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_CLR_MSK 0xfffffeff
8725 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field. */
8726 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_RESET 0x0
8727 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP field value from a register. */
8728 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8729 /* Produces a ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP register field value suitable for setting the register. */
8730 #define ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8731 
8732 /*
8733  * Field : pipe_cpybck_cmd_comp
8734  *
8735  * A pipeline command or a copyback bank command has completed on this particular
8736  * bank
8737  *
8738  * Field Access Macros:
8739  *
8740  */
8741 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field. */
8742 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_LSB 9
8743 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field. */
8744 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_MSB 9
8745 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field. */
8746 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8747 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field value. */
8748 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8749 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field value. */
8750 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8751 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field. */
8752 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8753 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP field value from a register. */
8754 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8755 /* Produces a ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
8756 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8757 
8758 /*
8759  * Field : locked_blk
8760  *
8761  * The address to program or erase operation is to a locked block and the operation
8762  * failed
8763  *
8764  * due to this reason
8765  *
8766  * Field Access Macros:
8767  *
8768  */
8769 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field. */
8770 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_LSB 10
8771 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field. */
8772 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_MSB 10
8773 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field. */
8774 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_WIDTH 1
8775 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field value. */
8776 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_SET_MSK 0x00000400
8777 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field value. */
8778 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_CLR_MSK 0xfffffbff
8779 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field. */
8780 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_RESET 0x0
8781 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK field value from a register. */
8782 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8783 /* Produces a ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK register field value suitable for setting the register. */
8784 #define ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8785 
8786 /*
8787  * Field : unsup_cmd
8788  *
8789  * An unsupported command was received. This interrupt is set when an invalid
8790  * command is
8791  *
8792  * received, or when a command sequence is broken.
8793  *
8794  * Field Access Macros:
8795  *
8796  */
8797 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field. */
8798 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_LSB 11
8799 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field. */
8800 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_MSB 11
8801 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field. */
8802 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_WIDTH 1
8803 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field value. */
8804 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_SET_MSK 0x00000800
8805 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field value. */
8806 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_CLR_MSK 0xfffff7ff
8807 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field. */
8808 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_RESET 0x0
8809 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD field value from a register. */
8810 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8811 /* Produces a ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD register field value suitable for setting the register. */
8812 #define ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8813 
8814 /*
8815  * Field : int_act
8816  *
8817  * R/B pin of device transitioned from low to high
8818  *
8819  * Field Access Macros:
8820  *
8821  */
8822 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field. */
8823 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_LSB 12
8824 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field. */
8825 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_MSB 12
8826 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field. */
8827 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_WIDTH 1
8828 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field value. */
8829 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_SET_MSK 0x00001000
8830 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field value. */
8831 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_CLR_MSK 0xffffefff
8832 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field. */
8833 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_RESET 0x0
8834 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_INT_ACT field value from a register. */
8835 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8836 /* Produces a ALT_NAND_STAT_INTR_STATUS2_INT_ACT register field value suitable for setting the register. */
8837 #define ALT_NAND_STAT_INTR_STATUS2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8838 
8839 /*
8840  * Field : rst_comp
8841  *
8842  * The Cadence NAND Flash Memory Controller has completed its reset and
8843  * initialization process
8844  *
8845  * Field Access Macros:
8846  *
8847  */
8848 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field. */
8849 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_LSB 13
8850 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field. */
8851 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_MSB 13
8852 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field. */
8853 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_WIDTH 1
8854 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field value. */
8855 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_SET_MSK 0x00002000
8856 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field value. */
8857 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_CLR_MSK 0xffffdfff
8858 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field. */
8859 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_RESET 0x0
8860 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_RST_COMP field value from a register. */
8861 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8862 /* Produces a ALT_NAND_STAT_INTR_STATUS2_RST_COMP register field value suitable for setting the register. */
8863 #define ALT_NAND_STAT_INTR_STATUS2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8864 
8865 /*
8866  * Field : pipe_cmd_err
8867  *
8868  * A pipeline command sequence has been violated. This occurs when Map 01 page
8869  * read/write
8870  *
8871  * address does not match the corresponding expected address from the pipeline
8872  * commands issued
8873  *
8874  * earlier.
8875  *
8876  * Field Access Macros:
8877  *
8878  */
8879 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field. */
8880 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_LSB 14
8881 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field. */
8882 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_MSB 14
8883 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field. */
8884 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_WIDTH 1
8885 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field value. */
8886 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_SET_MSK 0x00004000
8887 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field value. */
8888 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8889 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field. */
8890 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_RESET 0x0
8891 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR field value from a register. */
8892 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8893 /* Produces a ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR register field value suitable for setting the register. */
8894 #define ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8895 
8896 /*
8897  * Field : page_xfer_inc
8898  *
8899  * For every page of data transfer to or from the device, this bit will be set.
8900  *
8901  * Field Access Macros:
8902  *
8903  */
8904 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field. */
8905 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_LSB 15
8906 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field. */
8907 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_MSB 15
8908 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field. */
8909 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_WIDTH 1
8910 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field value. */
8911 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_SET_MSK 0x00008000
8912 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field value. */
8913 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8914 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field. */
8915 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_RESET 0x0
8916 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC field value from a register. */
8917 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8918 /* Produces a ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC register field value suitable for setting the register. */
8919 #define ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8920 
8921 /*
8922  * Field : erased_page
8923  *
8924  * If an erased page is detected on reads, this bit will be set. The detection of
8925  * erased
8926  *
8927  * page is based on the number of 0's in the page. If the number of 0's in the page
8928  * being
8929  *
8930  * read is less than the value in the erase_threshold (programmable register),
8931  *
8932  * an erased page is inferred and no un-correctable error will be flagged for that
8933  * page.
8934  *
8935  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
8936  * If ECC is
8937  *
8938  * enabled, in addition to the above condition, only when the ECC logic detects an
8939  *
8940  * un-correctable error for that page will the erased_page interrupt be flagged. If
8941  * the ECC
8942  *
8943  * logic detects a no-error or correctable error page, this erased page interrupt
8944  * will not
8945  *
8946  * be set.
8947  *
8948  * Field Access Macros:
8949  *
8950  */
8951 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field. */
8952 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_LSB 16
8953 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field. */
8954 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_MSB 16
8955 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field. */
8956 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_WIDTH 1
8957 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field value. */
8958 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_SET_MSK 0x00010000
8959 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field value. */
8960 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_CLR_MSK 0xfffeffff
8961 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field. */
8962 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_RESET 0x0
8963 /* Extracts the ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE field value from a register. */
8964 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8965 /* Produces a ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE register field value suitable for setting the register. */
8966 #define ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8967 
8968 #ifndef __ASSEMBLY__
8969 /*
8970  * WARNING: The C register and register group struct declarations are provided for
8971  * convenience and illustrative purposes. They should, however, be used with
8972  * caution as the C language standard provides no guarantees about the alignment or
8973  * atomicity of device memory accesses. The recommended practice for coding device
8974  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
8975  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
8976  * alt_write_dword() functions for 64 bit registers.
8977  *
8978  * The struct declaration for register ALT_NAND_STAT_INTR_STATUS2.
8979  */
8980 struct ALT_NAND_STAT_INTR_STATUS2_s
8981 {
8982  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STATUS2_ECC_UNCOR_ERR */
8983  uint32_t : 1; /* *UNDEFINED* */
8984  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_DMA_CMD_COMP */
8985  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STATUS2_TIME_OUT */
8986  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STATUS2_PROGRAM_FAIL */
8987  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STATUS2_ERASE_FAIL */
8988  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_LOAD_COMP */
8989  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_PROGRAM_COMP */
8990  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_ERASE_COMP */
8991  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_PIPE_CPYBCK_CMD_COMP */
8992  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STATUS2_LOCKED_BLK */
8993  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STATUS2_UNSUP_CMD */
8994  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STATUS2_INT_ACT */
8995  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STATUS2_RST_COMP */
8996  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STATUS2_PIPE_CMD_ERR */
8997  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STATUS2_PAGE_XFER_INC */
8998  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STATUS2_ERASED_PAGE */
8999  uint32_t : 15; /* *UNDEFINED* */
9000 };
9001 
9002 /* The typedef declaration for register ALT_NAND_STAT_INTR_STATUS2. */
9003 typedef struct ALT_NAND_STAT_INTR_STATUS2_s ALT_NAND_STAT_INTR_STATUS2_t;
9004 #endif /* __ASSEMBLY__ */
9005 
9006 /* The reset value of the ALT_NAND_STAT_INTR_STATUS2 register. */
9007 #define ALT_NAND_STAT_INTR_STATUS2_RESET 0x00000000
9008 /* The byte offset of the ALT_NAND_STAT_INTR_STATUS2 register from the beginning of the component. */
9009 #define ALT_NAND_STAT_INTR_STATUS2_OFST 0xb0
9010 /* The address of the ALT_NAND_STAT_INTR_STATUS2 register. */
9011 #define ALT_NAND_STAT_INTR_STATUS2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS2_OFST))
9012 
9013 /*
9014  * Register : intr_en2
9015  *
9016  * Enables corresponding interrupt bit in interrupt register
9017  *
9018  * for bank 2
9019  *
9020  * Register Layout
9021  *
9022  * Bits | Access | Reset | Description
9023  * :--------|:-------|:--------|:--------------------------------------------
9024  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR
9025  * [1] | ??? | Unknown | *UNDEFINED*
9026  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP
9027  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_TIME_OUT
9028  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL
9029  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_FAIL
9030  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LOAD_COMP
9031  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP
9032  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASE_COMP
9033  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP
9034  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_LOCKED_BLK
9035  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_UNSUP_CMD
9036  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_INT_ACT
9037  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN2_RST_COMP
9038  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR
9039  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC
9040  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN2_ERASED_PAGE
9041  * [31:17] | ??? | Unknown | *UNDEFINED*
9042  *
9043  */
9044 /*
9045  * Field : ecc_uncor_err
9046  *
9047  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
9048  * error.
9049  *
9050  * Field Access Macros:
9051  *
9052  */
9053 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
9054 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
9055 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
9056 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
9057 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
9058 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
9059 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
9060 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
9061 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value. */
9062 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9063 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field. */
9064 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
9065 /* Extracts the ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR field value from a register. */
9066 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9067 /* Produces a ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR register field value suitable for setting the register. */
9068 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9069 
9070 /*
9071  * Field : dma_cmd_comp
9072  *
9073  * A data DMA command has completed on this bank
9074  *
9075  * Field Access Macros:
9076  *
9077  */
9078 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
9079 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
9080 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
9081 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
9082 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
9083 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
9084 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
9085 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
9086 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value. */
9087 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9088 /* The reset value of the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field. */
9089 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
9090 /* Extracts the ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP field value from a register. */
9091 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9092 /* Produces a ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP register field value suitable for setting the register. */
9093 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9094 
9095 /*
9096  * Field : time_out
9097  *
9098  * Watchdog timer has triggered in the controller due to one of the reasons like
9099  * device
9100  *
9101  * not responding or controller state machine did not get back to idle
9102  *
9103  * Field Access Macros:
9104  *
9105  */
9106 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
9107 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
9108 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
9109 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
9110 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
9111 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
9112 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
9113 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
9114 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value. */
9115 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
9116 /* The reset value of the ALT_NAND_STAT_INTR_EN2_TIME_OUT register field. */
9117 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
9118 /* Extracts the ALT_NAND_STAT_INTR_EN2_TIME_OUT field value from a register. */
9119 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9120 /* Produces a ALT_NAND_STAT_INTR_EN2_TIME_OUT register field value suitable for setting the register. */
9121 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9122 
9123 /*
9124  * Field : program_fail
9125  *
9126  * Program failure occurred in the device on issuance of a program command.
9127  * err_block_addr
9128  *
9129  * and err_page_addr contain the block address and page address that failed program
9130  * operation.
9131  *
9132  * Field Access Macros:
9133  *
9134  */
9135 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
9136 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
9137 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
9138 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
9139 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
9140 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
9141 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
9142 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
9143 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value. */
9144 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
9145 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field. */
9146 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
9147 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL field value from a register. */
9148 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9149 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL register field value suitable for setting the register. */
9150 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9151 
9152 /*
9153  * Field : erase_fail
9154  *
9155  * Erase failure occurred in the device on issuance of a erase command.
9156  * err_block_addr
9157  *
9158  * and err_page_addr contain the block address and page address that failed erase
9159  * operation.
9160  *
9161  * Field Access Macros:
9162  *
9163  */
9164 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
9165 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
9166 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
9167 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
9168 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
9169 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
9170 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
9171 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
9172 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value. */
9173 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
9174 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field. */
9175 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
9176 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_FAIL field value from a register. */
9177 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9178 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_FAIL register field value suitable for setting the register. */
9179 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9180 
9181 /*
9182  * Field : load_comp
9183  *
9184  * Device finished the last issued load command.
9185  *
9186  * Field Access Macros:
9187  *
9188  */
9189 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field. */
9190 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_LSB 6
9191 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field. */
9192 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_MSB 6
9193 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field. */
9194 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_WIDTH 1
9195 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field value. */
9196 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_SET_MSK 0x00000040
9197 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field value. */
9198 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_CLR_MSK 0xffffffbf
9199 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field. */
9200 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_RESET 0x0
9201 /* Extracts the ALT_NAND_STAT_INTR_EN2_LOAD_COMP field value from a register. */
9202 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9203 /* Produces a ALT_NAND_STAT_INTR_EN2_LOAD_COMP register field value suitable for setting the register. */
9204 #define ALT_NAND_STAT_INTR_EN2_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
9205 
9206 /*
9207  * Field : program_comp
9208  *
9209  * Device finished the last issued program command.
9210  *
9211  * Field Access Macros:
9212  *
9213  */
9214 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
9215 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
9216 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
9217 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
9218 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
9219 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
9220 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
9221 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
9222 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value. */
9223 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
9224 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field. */
9225 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
9226 /* Extracts the ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP field value from a register. */
9227 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9228 /* Produces a ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP register field value suitable for setting the register. */
9229 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9230 
9231 /*
9232  * Field : erase_comp
9233  *
9234  * Device erase operation complete
9235  *
9236  * Field Access Macros:
9237  *
9238  */
9239 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9240 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
9241 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9242 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
9243 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9244 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
9245 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
9246 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
9247 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value. */
9248 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
9249 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field. */
9250 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
9251 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASE_COMP field value from a register. */
9252 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9253 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASE_COMP register field value suitable for setting the register. */
9254 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9255 
9256 /*
9257  * Field : pipe_cpybck_cmd_comp
9258  *
9259  * A pipeline command or a copyback bank command has completed on this particular
9260  * bank
9261  *
9262  * Field Access Macros:
9263  *
9264  */
9265 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9266 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
9267 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9268 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
9269 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9270 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9271 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
9272 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9273 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value. */
9274 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9275 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field. */
9276 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9277 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP field value from a register. */
9278 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9279 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
9280 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9281 
9282 /*
9283  * Field : locked_blk
9284  *
9285  * The address to program or erase operation is to a locked block and the operation
9286  * failed
9287  *
9288  * due to this reason
9289  *
9290  * Field Access Macros:
9291  *
9292  */
9293 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9294 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
9295 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9296 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
9297 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9298 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
9299 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
9300 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
9301 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value. */
9302 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
9303 /* The reset value of the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field. */
9304 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
9305 /* Extracts the ALT_NAND_STAT_INTR_EN2_LOCKED_BLK field value from a register. */
9306 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9307 /* Produces a ALT_NAND_STAT_INTR_EN2_LOCKED_BLK register field value suitable for setting the register. */
9308 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9309 
9310 /*
9311  * Field : unsup_cmd
9312  *
9313  * An unsupported command was received. This interrupt is set when an invalid
9314  * command is
9315  *
9316  * received, or when a command sequence is broken.
9317  *
9318  * Field Access Macros:
9319  *
9320  */
9321 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9322 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
9323 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9324 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
9325 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9326 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
9327 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
9328 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
9329 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value. */
9330 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
9331 /* The reset value of the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field. */
9332 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
9333 /* Extracts the ALT_NAND_STAT_INTR_EN2_UNSUP_CMD field value from a register. */
9334 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9335 /* Produces a ALT_NAND_STAT_INTR_EN2_UNSUP_CMD register field value suitable for setting the register. */
9336 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9337 
9338 /*
9339  * Field : int_act
9340  *
9341  * R/B pin of device transitioned from low to high
9342  *
9343  * Field Access Macros:
9344  *
9345  */
9346 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9347 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
9348 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9349 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
9350 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9351 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
9352 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
9353 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
9354 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_INT_ACT register field value. */
9355 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
9356 /* The reset value of the ALT_NAND_STAT_INTR_EN2_INT_ACT register field. */
9357 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
9358 /* Extracts the ALT_NAND_STAT_INTR_EN2_INT_ACT field value from a register. */
9359 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9360 /* Produces a ALT_NAND_STAT_INTR_EN2_INT_ACT register field value suitable for setting the register. */
9361 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9362 
9363 /*
9364  * Field : rst_comp
9365  *
9366  * A reset command has completed on this bank
9367  *
9368  * Field Access Macros:
9369  *
9370  */
9371 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9372 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
9373 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9374 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
9375 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9376 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
9377 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
9378 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
9379 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_RST_COMP register field value. */
9380 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
9381 /* The reset value of the ALT_NAND_STAT_INTR_EN2_RST_COMP register field. */
9382 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
9383 /* Extracts the ALT_NAND_STAT_INTR_EN2_RST_COMP field value from a register. */
9384 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9385 /* Produces a ALT_NAND_STAT_INTR_EN2_RST_COMP register field value suitable for setting the register. */
9386 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9387 
9388 /*
9389  * Field : pipe_cmd_err
9390  *
9391  * A pipeline command sequence has been violated. This occurs when Map 01 page
9392  * read/write
9393  *
9394  * address does not match the corresponding expected address from the pipeline
9395  * commands issued
9396  *
9397  * earlier.
9398  *
9399  * Field Access Macros:
9400  *
9401  */
9402 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9403 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
9404 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9405 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
9406 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9407 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
9408 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
9409 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
9410 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value. */
9411 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9412 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field. */
9413 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
9414 /* Extracts the ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR field value from a register. */
9415 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9416 /* Produces a ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR register field value suitable for setting the register. */
9417 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9418 
9419 /*
9420  * Field : page_xfer_inc
9421  *
9422  * For every page of data transfer to or from the device, this bit will be set.
9423  *
9424  * Field Access Macros:
9425  *
9426  */
9427 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9428 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
9429 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9430 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
9431 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9432 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
9433 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
9434 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
9435 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value. */
9436 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9437 /* The reset value of the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field. */
9438 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
9439 /* Extracts the ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC field value from a register. */
9440 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9441 /* Produces a ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC register field value suitable for setting the register. */
9442 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9443 
9444 /*
9445  * Field : erased_page
9446  *
9447  * If an erased page is detected on reads, this bit will be set. The detection of
9448  * erased
9449  *
9450  * page is based on the number of 0's in the page. If the number of 0's in the page
9451  * being
9452  *
9453  * read is less than the value in the erase_threshold (programmable register),
9454  *
9455  * an erased page is inferred and no un-correctable error will be flagged for that
9456  * page.
9457  *
9458  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
9459  * If ECC is
9460  *
9461  * enabled, in addition to the above condition, only when the ECC logic detects an
9462  *
9463  * un-correctable error for that page will the erased_page interrupt be flagged. If
9464  * the ECC
9465  *
9466  * logic detects a no-error or correctable error page, this erased page interrupt
9467  * will not
9468  *
9469  * be set.
9470  *
9471  * Field Access Macros:
9472  *
9473  */
9474 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9475 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_LSB 16
9476 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9477 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_MSB 16
9478 /* The width in bits of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9479 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_WIDTH 1
9480 /* The mask used to set the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value. */
9481 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET_MSK 0x00010000
9482 /* The mask used to clear the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value. */
9483 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_CLR_MSK 0xfffeffff
9484 /* The reset value of the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field. */
9485 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_RESET 0x0
9486 /* Extracts the ALT_NAND_STAT_INTR_EN2_ERASED_PAGE field value from a register. */
9487 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9488 /* Produces a ALT_NAND_STAT_INTR_EN2_ERASED_PAGE register field value suitable for setting the register. */
9489 #define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9490 
9491 #ifndef __ASSEMBLY__
9492 /*
9493  * WARNING: The C register and register group struct declarations are provided for
9494  * convenience and illustrative purposes. They should, however, be used with
9495  * caution as the C language standard provides no guarantees about the alignment or
9496  * atomicity of device memory accesses. The recommended practice for coding device
9497  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9498  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9499  * alt_write_dword() functions for 64 bit registers.
9500  *
9501  * The struct declaration for register ALT_NAND_STAT_INTR_EN2.
9502  */
9503 struct ALT_NAND_STAT_INTR_EN2_s
9504 {
9505  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR */
9506  uint32_t : 1; /* *UNDEFINED* */
9507  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP */
9508  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN2_TIME_OUT */
9509  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL */
9510  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_FAIL */
9511  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN2_LOAD_COMP */
9512  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP */
9513  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN2_ERASE_COMP */
9514  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP */
9515  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN2_LOCKED_BLK */
9516  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN2_UNSUP_CMD */
9517  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN2_INT_ACT */
9518  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN2_RST_COMP */
9519  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR */
9520  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC */
9521  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN2_ERASED_PAGE */
9522  uint32_t : 15; /* *UNDEFINED* */
9523 };
9524 
9525 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN2. */
9526 typedef struct ALT_NAND_STAT_INTR_EN2_s ALT_NAND_STAT_INTR_EN2_t;
9527 #endif /* __ASSEMBLY__ */
9528 
9529 /* The reset value of the ALT_NAND_STAT_INTR_EN2 register. */
9530 #define ALT_NAND_STAT_INTR_EN2_RESET 0x00002000
9531 /* The byte offset of the ALT_NAND_STAT_INTR_EN2 register from the beginning of the component. */
9532 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
9533 /* The address of the ALT_NAND_STAT_INTR_EN2 register. */
9534 #define ALT_NAND_STAT_INTR_EN2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN2_OFST))
9535 
9536 /*
9537  * Register : page_cnt2
9538  *
9539  * Decrementing page count bank 2
9540  *
9541  * Register Layout
9542  *
9543  * Bits | Access | Reset | Description
9544  * :-------|:-------|:--------|:------------------------------
9545  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT2_VALUE
9546  * [31:8] | ??? | Unknown | *UNDEFINED*
9547  *
9548  */
9549 /*
9550  * Field : value
9551  *
9552  * Maintains a decrementing count of the number of pages in
9553  *
9554  * the multi-page (pipeline and copyback) command being executed.
9555  *
9556  * Field Access Macros:
9557  *
9558  */
9559 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9560 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
9561 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9562 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
9563 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9564 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
9565 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
9566 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
9567 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT2_VALUE register field value. */
9568 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
9569 /* The reset value of the ALT_NAND_STAT_PAGE_CNT2_VALUE register field. */
9570 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
9571 /* Extracts the ALT_NAND_STAT_PAGE_CNT2_VALUE field value from a register. */
9572 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9573 /* Produces a ALT_NAND_STAT_PAGE_CNT2_VALUE register field value suitable for setting the register. */
9574 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9575 
9576 #ifndef __ASSEMBLY__
9577 /*
9578  * WARNING: The C register and register group struct declarations are provided for
9579  * convenience and illustrative purposes. They should, however, be used with
9580  * caution as the C language standard provides no guarantees about the alignment or
9581  * atomicity of device memory accesses. The recommended practice for coding device
9582  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9583  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9584  * alt_write_dword() functions for 64 bit registers.
9585  *
9586  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT2.
9587  */
9588 struct ALT_NAND_STAT_PAGE_CNT2_s
9589 {
9590  const volatile uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT2_VALUE */
9591  uint32_t : 24; /* *UNDEFINED* */
9592 };
9593 
9594 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT2. */
9595 typedef struct ALT_NAND_STAT_PAGE_CNT2_s ALT_NAND_STAT_PAGE_CNT2_t;
9596 #endif /* __ASSEMBLY__ */
9597 
9598 /* The reset value of the ALT_NAND_STAT_PAGE_CNT2 register. */
9599 #define ALT_NAND_STAT_PAGE_CNT2_RESET 0x00000000
9600 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT2 register from the beginning of the component. */
9601 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
9602 /* The address of the ALT_NAND_STAT_PAGE_CNT2 register. */
9603 #define ALT_NAND_STAT_PAGE_CNT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT2_OFST))
9604 
9605 /*
9606  * Register : err_page_addr2
9607  *
9608  * Erred page address bank 2
9609  *
9610  * Register Layout
9611  *
9612  * Bits | Access | Reset | Description
9613  * :--------|:-------|:--------|:-----------------------------------
9614  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE
9615  * [31:16] | ??? | Unknown | *UNDEFINED*
9616  *
9617  */
9618 /*
9619  * Field : value
9620  *
9621  * Holds the page address that resulted in a failure on program
9622  *
9623  * or erase operation.
9624  *
9625  * Field Access Macros:
9626  *
9627  */
9628 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9629 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
9630 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9631 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
9632 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9633 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
9634 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
9635 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
9636 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value. */
9637 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
9638 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field. */
9639 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
9640 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE field value from a register. */
9641 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9642 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE register field value suitable for setting the register. */
9643 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9644 
9645 #ifndef __ASSEMBLY__
9646 /*
9647  * WARNING: The C register and register group struct declarations are provided for
9648  * convenience and illustrative purposes. They should, however, be used with
9649  * caution as the C language standard provides no guarantees about the alignment or
9650  * atomicity of device memory accesses. The recommended practice for coding device
9651  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9652  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9653  * alt_write_dword() functions for 64 bit registers.
9654  *
9655  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2.
9656  */
9657 struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s
9658 {
9659  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE */
9660  uint32_t : 16; /* *UNDEFINED* */
9661 };
9662 
9663 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR2. */
9664 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR2_s ALT_NAND_STAT_ERR_PAGE_ADDR2_t;
9665 #endif /* __ASSEMBLY__ */
9666 
9667 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register. */
9668 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_RESET 0x00000000
9669 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register from the beginning of the component. */
9670 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
9671 /* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR2 register. */
9672 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST))
9673 
9674 /*
9675  * Register : err_block_addr2
9676  *
9677  * Erred block address bank 2
9678  *
9679  * Register Layout
9680  *
9681  * Bits | Access | Reset | Description
9682  * :--------|:-------|:--------|:------------------------------------
9683  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE
9684  * [31:16] | ??? | Unknown | *UNDEFINED*
9685  *
9686  */
9687 /*
9688  * Field : value
9689  *
9690  * Holds the block address that resulted in a failure on program
9691  *
9692  * or erase operation.
9693  *
9694  * Field Access Macros:
9695  *
9696  */
9697 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9698 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
9699 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9700 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
9701 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9702 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
9703 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
9704 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
9705 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value. */
9706 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
9707 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field. */
9708 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
9709 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE field value from a register. */
9710 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9711 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE register field value suitable for setting the register. */
9712 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9713 
9714 #ifndef __ASSEMBLY__
9715 /*
9716  * WARNING: The C register and register group struct declarations are provided for
9717  * convenience and illustrative purposes. They should, however, be used with
9718  * caution as the C language standard provides no guarantees about the alignment or
9719  * atomicity of device memory accesses. The recommended practice for coding device
9720  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
9721  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
9722  * alt_write_dword() functions for 64 bit registers.
9723  *
9724  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2.
9725  */
9726 struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
9727 {
9728  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE */
9729  uint32_t : 16; /* *UNDEFINED* */
9730 };
9731 
9732 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR2. */
9733 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR2_s ALT_NAND_STAT_ERR_BLOCK_ADDR2_t;
9734 #endif /* __ASSEMBLY__ */
9735 
9736 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register. */
9737 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_RESET 0x00000000
9738 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register from the beginning of the component. */
9739 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
9740 /* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR2 register. */
9741 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST))
9742 
9743 /*
9744  * Register : intr_status3
9745  *
9746  * Interrupt status register for bank 3
9747  *
9748  * Register Layout
9749  *
9750  * Bits | Access | Reset | Description
9751  * :--------|:-------|:--------|:------------------------------------------------
9752  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR
9753  * [1] | ??? | Unknown | *UNDEFINED*
9754  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP
9755  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_TIME_OUT
9756  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL
9757  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL
9758  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP
9759  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP
9760  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP
9761  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP
9762  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK
9763  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD
9764  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_INT_ACT
9765  * [13] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_RST_COMP
9766  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR
9767  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC
9768  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE
9769  * [31:17] | ??? | Unknown | *UNDEFINED*
9770  *
9771  */
9772 /*
9773  * Field : ecc_uncor_err
9774  *
9775  * Ecc logic detected uncorrectable error while reading data from flash device.
9776  *
9777  * Field Access Macros:
9778  *
9779  */
9780 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field. */
9781 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_LSB 0
9782 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field. */
9783 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_MSB 0
9784 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field. */
9785 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_WIDTH 1
9786 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field value. */
9787 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_SET_MSK 0x00000001
9788 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field value. */
9789 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9790 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field. */
9791 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_RESET 0x0
9792 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR field value from a register. */
9793 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9794 /* Produces a ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR register field value suitable for setting the register. */
9795 #define ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9796 
9797 /*
9798  * Field : dma_cmd_comp
9799  *
9800  * A data DMA command has completed on this bank
9801  *
9802  * Field Access Macros:
9803  *
9804  */
9805 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field. */
9806 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_LSB 2
9807 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field. */
9808 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_MSB 2
9809 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field. */
9810 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_WIDTH 1
9811 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field value. */
9812 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_SET_MSK 0x00000004
9813 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field value. */
9814 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9815 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field. */
9816 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_RESET 0x0
9817 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP field value from a register. */
9818 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9819 /* Produces a ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP register field value suitable for setting the register. */
9820 #define ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9821 
9822 /*
9823  * Field : time_out
9824  *
9825  * Watchdog timer has triggered in the controller due to one of the reasons like
9826  * device
9827  *
9828  * not responding or controller state machine did not get back to idle
9829  *
9830  * Field Access Macros:
9831  *
9832  */
9833 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field. */
9834 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_LSB 3
9835 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field. */
9836 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_MSB 3
9837 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field. */
9838 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_WIDTH 1
9839 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field value. */
9840 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_SET_MSK 0x00000008
9841 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field value. */
9842 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_CLR_MSK 0xfffffff7
9843 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field. */
9844 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_RESET 0x0
9845 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_TIME_OUT field value from a register. */
9846 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9847 /* Produces a ALT_NAND_STAT_INTR_STATUS3_TIME_OUT register field value suitable for setting the register. */
9848 #define ALT_NAND_STAT_INTR_STATUS3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9849 
9850 /*
9851  * Field : program_fail
9852  *
9853  * Program failure occurred in the device on issuance of a program command.
9854  * err_block_addr
9855  *
9856  * and err_page_addr contain the block address and page address that failed program
9857  * operation.
9858  *
9859  * Field Access Macros:
9860  *
9861  */
9862 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field. */
9863 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_LSB 4
9864 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field. */
9865 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_MSB 4
9866 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field. */
9867 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_WIDTH 1
9868 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field value. */
9869 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_SET_MSK 0x00000010
9870 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field value. */
9871 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_CLR_MSK 0xffffffef
9872 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field. */
9873 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_RESET 0x0
9874 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL field value from a register. */
9875 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9876 /* Produces a ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL register field value suitable for setting the register. */
9877 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9878 
9879 /*
9880  * Field : erase_fail
9881  *
9882  * Erase failure occurred in the device on issuance of a erase command.
9883  * err_block_addr
9884  *
9885  * and err_page_addr contain the block address and page address that failed erase
9886  * operation.
9887  *
9888  * Field Access Macros:
9889  *
9890  */
9891 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field. */
9892 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_LSB 5
9893 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field. */
9894 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_MSB 5
9895 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field. */
9896 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_WIDTH 1
9897 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field value. */
9898 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_SET_MSK 0x00000020
9899 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field value. */
9900 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_CLR_MSK 0xffffffdf
9901 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field. */
9902 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_RESET 0x0
9903 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL field value from a register. */
9904 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9905 /* Produces a ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL register field value suitable for setting the register. */
9906 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9907 
9908 /*
9909  * Field : load_comp
9910  *
9911  * Device finished the last issued load command.
9912  *
9913  * Field Access Macros:
9914  *
9915  */
9916 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field. */
9917 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_LSB 6
9918 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field. */
9919 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_MSB 6
9920 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field. */
9921 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_WIDTH 1
9922 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field value. */
9923 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_SET_MSK 0x00000040
9924 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field value. */
9925 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_CLR_MSK 0xffffffbf
9926 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field. */
9927 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_RESET 0x0
9928 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP field value from a register. */
9929 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9930 /* Produces a ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP register field value suitable for setting the register. */
9931 #define ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
9932 
9933 /*
9934  * Field : program_comp
9935  *
9936  * Device finished the last issued program command.
9937  *
9938  * Field Access Macros:
9939  *
9940  */
9941 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field. */
9942 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_LSB 7
9943 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field. */
9944 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_MSB 7
9945 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field. */
9946 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_WIDTH 1
9947 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field value. */
9948 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_SET_MSK 0x00000080
9949 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field value. */
9950 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_CLR_MSK 0xffffff7f
9951 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field. */
9952 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_RESET 0x0
9953 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP field value from a register. */
9954 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9955 /* Produces a ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP register field value suitable for setting the register. */
9956 #define ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9957 
9958 /*
9959  * Field : erase_comp
9960  *
9961  * Device erase operation complete
9962  *
9963  * Field Access Macros:
9964  *
9965  */
9966 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field. */
9967 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_LSB 8
9968 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field. */
9969 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_MSB 8
9970 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field. */
9971 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_WIDTH 1
9972 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field value. */
9973 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_SET_MSK 0x00000100
9974 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field value. */
9975 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_CLR_MSK 0xfffffeff
9976 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field. */
9977 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_RESET 0x0
9978 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP field value from a register. */
9979 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9980 /* Produces a ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP register field value suitable for setting the register. */
9981 #define ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9982 
9983 /*
9984  * Field : pipe_cpybck_cmd_comp
9985  *
9986  * A pipeline command or a copyback bank command has completed on this particular
9987  * bank
9988  *
9989  * Field Access Macros:
9990  *
9991  */
9992 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field. */
9993 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_LSB 9
9994 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field. */
9995 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_MSB 9
9996 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field. */
9997 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9998 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field value. */
9999 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10000 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field value. */
10001 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10002 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field. */
10003 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10004 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP field value from a register. */
10005 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10006 /* Produces a ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
10007 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10008 
10009 /*
10010  * Field : locked_blk
10011  *
10012  * The address to program or erase operation is to a locked block and the operation
10013  * failed
10014  *
10015  * due to this reason
10016  *
10017  * Field Access Macros:
10018  *
10019  */
10020 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field. */
10021 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_LSB 10
10022 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field. */
10023 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_MSB 10
10024 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field. */
10025 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_WIDTH 1
10026 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field value. */
10027 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_SET_MSK 0x00000400
10028 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field value. */
10029 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_CLR_MSK 0xfffffbff
10030 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field. */
10031 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_RESET 0x0
10032 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK field value from a register. */
10033 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10034 /* Produces a ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK register field value suitable for setting the register. */
10035 #define ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10036 
10037 /*
10038  * Field : unsup_cmd
10039  *
10040  * An unsupported command was received. This interrupt is set when an invalid
10041  * command is
10042  *
10043  * received, or when a command sequence is broken.
10044  *
10045  * Field Access Macros:
10046  *
10047  */
10048 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field. */
10049 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_LSB 11
10050 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field. */
10051 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_MSB 11
10052 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field. */
10053 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_WIDTH 1
10054 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field value. */
10055 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_SET_MSK 0x00000800
10056 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field value. */
10057 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10058 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field. */
10059 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_RESET 0x0
10060 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD field value from a register. */
10061 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10062 /* Produces a ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD register field value suitable for setting the register. */
10063 #define ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10064 
10065 /*
10066  * Field : int_act
10067  *
10068  * R/B pin of device transitioned from low to high
10069  *
10070  * Field Access Macros:
10071  *
10072  */
10073 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field. */
10074 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_LSB 12
10075 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field. */
10076 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_MSB 12
10077 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field. */
10078 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_WIDTH 1
10079 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field value. */
10080 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_SET_MSK 0x00001000
10081 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field value. */
10082 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_CLR_MSK 0xffffefff
10083 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field. */
10084 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_RESET 0x0
10085 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_INT_ACT field value from a register. */
10086 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10087 /* Produces a ALT_NAND_STAT_INTR_STATUS3_INT_ACT register field value suitable for setting the register. */
10088 #define ALT_NAND_STAT_INTR_STATUS3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10089 
10090 /*
10091  * Field : rst_comp
10092  *
10093  * The Cadence NAND Flash Memory Controller has completed its reset and
10094  * initialization process
10095  *
10096  * Field Access Macros:
10097  *
10098  */
10099 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field. */
10100 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_LSB 13
10101 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field. */
10102 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_MSB 13
10103 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field. */
10104 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_WIDTH 1
10105 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field value. */
10106 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_SET_MSK 0x00002000
10107 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field value. */
10108 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_CLR_MSK 0xffffdfff
10109 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field. */
10110 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_RESET 0x0
10111 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_RST_COMP field value from a register. */
10112 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10113 /* Produces a ALT_NAND_STAT_INTR_STATUS3_RST_COMP register field value suitable for setting the register. */
10114 #define ALT_NAND_STAT_INTR_STATUS3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10115 
10116 /*
10117  * Field : pipe_cmd_err
10118  *
10119  * A pipeline command sequence has been violated. This occurs when Map 01 page
10120  * read/write
10121  *
10122  * address does not match the corresponding expected address from the pipeline
10123  * commands issued
10124  *
10125  * earlier.
10126  *
10127  * Field Access Macros:
10128  *
10129  */
10130 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field. */
10131 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_LSB 14
10132 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field. */
10133 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_MSB 14
10134 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field. */
10135 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_WIDTH 1
10136 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field value. */
10137 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_SET_MSK 0x00004000
10138 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field value. */
10139 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10140 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field. */
10141 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_RESET 0x0
10142 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR field value from a register. */
10143 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10144 /* Produces a ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR register field value suitable for setting the register. */
10145 #define ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10146 
10147 /*
10148  * Field : page_xfer_inc
10149  *
10150  * For every page of data transfer to or from the device, this bit will be set.
10151  *
10152  * Field Access Macros:
10153  *
10154  */
10155 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field. */
10156 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_LSB 15
10157 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field. */
10158 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_MSB 15
10159 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field. */
10160 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_WIDTH 1
10161 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field value. */
10162 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_SET_MSK 0x00008000
10163 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field value. */
10164 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10165 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field. */
10166 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_RESET 0x0
10167 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC field value from a register. */
10168 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10169 /* Produces a ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC register field value suitable for setting the register. */
10170 #define ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10171 
10172 /*
10173  * Field : erased_page
10174  *
10175  * If an erased page is detected on reads, this bit will be set. The detection of
10176  * erased
10177  *
10178  * page is based on the number of 0's in the page. If the number of 0's in the page
10179  * being
10180  *
10181  * read is less than the value in the erase_threshold (programmable register),
10182  *
10183  * an erased page is inferred and no un-correctable error will be flagged for that
10184  * page.
10185  *
10186  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
10187  * If ECC is
10188  *
10189  * enabled, in addition to the above condition, only when the ECC logic detects an
10190  *
10191  * un-correctable error for that page will the erased_page interrupt be flagged. If
10192  * the ECC
10193  *
10194  * logic detects a no-error or correctable error page, this erased page interrupt
10195  * will not
10196  *
10197  * be set.
10198  *
10199  * Field Access Macros:
10200  *
10201  */
10202 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field. */
10203 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_LSB 16
10204 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field. */
10205 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_MSB 16
10206 /* The width in bits of the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field. */
10207 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_WIDTH 1
10208 /* The mask used to set the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field value. */
10209 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_SET_MSK 0x00010000
10210 /* The mask used to clear the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field value. */
10211 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_CLR_MSK 0xfffeffff
10212 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field. */
10213 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_RESET 0x0
10214 /* Extracts the ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE field value from a register. */
10215 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10216 /* Produces a ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE register field value suitable for setting the register. */
10217 #define ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10218 
10219 #ifndef __ASSEMBLY__
10220 /*
10221  * WARNING: The C register and register group struct declarations are provided for
10222  * convenience and illustrative purposes. They should, however, be used with
10223  * caution as the C language standard provides no guarantees about the alignment or
10224  * atomicity of device memory accesses. The recommended practice for coding device
10225  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10226  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10227  * alt_write_dword() functions for 64 bit registers.
10228  *
10229  * The struct declaration for register ALT_NAND_STAT_INTR_STATUS3.
10230  */
10231 struct ALT_NAND_STAT_INTR_STATUS3_s
10232 {
10233  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_STATUS3_ECC_UNCOR_ERR */
10234  uint32_t : 1; /* *UNDEFINED* */
10235  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_DMA_CMD_COMP */
10236  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_STATUS3_TIME_OUT */
10237  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_STATUS3_PROGRAM_FAIL */
10238  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_STATUS3_ERASE_FAIL */
10239  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_LOAD_COMP */
10240  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_PROGRAM_COMP */
10241  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_ERASE_COMP */
10242  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_PIPE_CPYBCK_CMD_COMP */
10243  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_STATUS3_LOCKED_BLK */
10244  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_STATUS3_UNSUP_CMD */
10245  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_STATUS3_INT_ACT */
10246  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_STATUS3_RST_COMP */
10247  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_STATUS3_PIPE_CMD_ERR */
10248  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_STATUS3_PAGE_XFER_INC */
10249  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_STATUS3_ERASED_PAGE */
10250  uint32_t : 15; /* *UNDEFINED* */
10251 };
10252 
10253 /* The typedef declaration for register ALT_NAND_STAT_INTR_STATUS3. */
10254 typedef struct ALT_NAND_STAT_INTR_STATUS3_s ALT_NAND_STAT_INTR_STATUS3_t;
10255 #endif /* __ASSEMBLY__ */
10256 
10257 /* The reset value of the ALT_NAND_STAT_INTR_STATUS3 register. */
10258 #define ALT_NAND_STAT_INTR_STATUS3_RESET 0x00000000
10259 /* The byte offset of the ALT_NAND_STAT_INTR_STATUS3 register from the beginning of the component. */
10260 #define ALT_NAND_STAT_INTR_STATUS3_OFST 0x100
10261 /* The address of the ALT_NAND_STAT_INTR_STATUS3 register. */
10262 #define ALT_NAND_STAT_INTR_STATUS3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_STATUS3_OFST))
10263 
10264 /*
10265  * Register : intr_en3
10266  *
10267  * Enables corresponding interrupt bit in interrupt register
10268  *
10269  * for bank 3
10270  *
10271  * Register Layout
10272  *
10273  * Bits | Access | Reset | Description
10274  * :--------|:-------|:--------|:--------------------------------------------
10275  * [0] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR
10276  * [1] | ??? | Unknown | *UNDEFINED*
10277  * [2] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP
10278  * [3] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_TIME_OUT
10279  * [4] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL
10280  * [5] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_FAIL
10281  * [6] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LOAD_COMP
10282  * [7] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP
10283  * [8] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASE_COMP
10284  * [9] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP
10285  * [10] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_LOCKED_BLK
10286  * [11] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_UNSUP_CMD
10287  * [12] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_INT_ACT
10288  * [13] | RW | 0x1 | ALT_NAND_STAT_INTR_EN3_RST_COMP
10289  * [14] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR
10290  * [15] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC
10291  * [16] | RW | 0x0 | ALT_NAND_STAT_INTR_EN3_ERASED_PAGE
10292  * [31:17] | ??? | Unknown | *UNDEFINED*
10293  *
10294  */
10295 /*
10296  * Field : ecc_uncor_err
10297  *
10298  * If set, Controller will interrupt processor when Ecc logic detects uncorrectable
10299  * error.
10300  *
10301  * Field Access Macros:
10302  *
10303  */
10304 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10305 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
10306 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10307 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
10308 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10309 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
10310 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
10311 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
10312 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value. */
10313 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
10314 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field. */
10315 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
10316 /* Extracts the ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR field value from a register. */
10317 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
10318 /* Produces a ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR register field value suitable for setting the register. */
10319 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
10320 
10321 /*
10322  * Field : dma_cmd_comp
10323  *
10324  * A data DMA command has completed on this bank
10325  *
10326  * Field Access Macros:
10327  *
10328  */
10329 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10330 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
10331 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10332 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
10333 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10334 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
10335 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
10336 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
10337 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value. */
10338 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
10339 /* The reset value of the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field. */
10340 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
10341 /* Extracts the ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP field value from a register. */
10342 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
10343 /* Produces a ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP register field value suitable for setting the register. */
10344 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
10345 
10346 /*
10347  * Field : time_out
10348  *
10349  * Watchdog timer has triggered in the controller due to one of the reasons like
10350  * device
10351  *
10352  * not responding or controller state machine did not get back to idle
10353  *
10354  * Field Access Macros:
10355  *
10356  */
10357 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10358 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
10359 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10360 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
10361 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10362 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
10363 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
10364 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
10365 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value. */
10366 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
10367 /* The reset value of the ALT_NAND_STAT_INTR_EN3_TIME_OUT register field. */
10368 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
10369 /* Extracts the ALT_NAND_STAT_INTR_EN3_TIME_OUT field value from a register. */
10370 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
10371 /* Produces a ALT_NAND_STAT_INTR_EN3_TIME_OUT register field value suitable for setting the register. */
10372 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
10373 
10374 /*
10375  * Field : program_fail
10376  *
10377  * Program failure occurred in the device on issuance of a program command.
10378  * err_block_addr
10379  *
10380  * and err_page_addr contain the block address and page address that failed program
10381  * operation.
10382  *
10383  * Field Access Macros:
10384  *
10385  */
10386 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10387 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
10388 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10389 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
10390 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10391 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
10392 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
10393 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
10394 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value. */
10395 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
10396 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field. */
10397 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
10398 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL field value from a register. */
10399 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
10400 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL register field value suitable for setting the register. */
10401 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
10402 
10403 /*
10404  * Field : erase_fail
10405  *
10406  * Erase failure occurred in the device on issuance of a erase command.
10407  * err_block_addr
10408  *
10409  * and err_page_addr contain the block address and page address that failed erase
10410  * operation.
10411  *
10412  * Field Access Macros:
10413  *
10414  */
10415 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10416 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
10417 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10418 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
10419 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10420 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
10421 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
10422 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
10423 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value. */
10424 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
10425 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field. */
10426 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
10427 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_FAIL field value from a register. */
10428 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
10429 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_FAIL register field value suitable for setting the register. */
10430 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
10431 
10432 /*
10433  * Field : load_comp
10434  *
10435  * Device finished the last issued load command.
10436  *
10437  * Field Access Macros:
10438  *
10439  */
10440 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field. */
10441 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_LSB 6
10442 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field. */
10443 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_MSB 6
10444 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field. */
10445 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_WIDTH 1
10446 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field value. */
10447 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_SET_MSK 0x00000040
10448 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field value. */
10449 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_CLR_MSK 0xffffffbf
10450 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field. */
10451 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_RESET 0x0
10452 /* Extracts the ALT_NAND_STAT_INTR_EN3_LOAD_COMP field value from a register. */
10453 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_GET(value) (((value) & 0x00000040) >> 6)
10454 /* Produces a ALT_NAND_STAT_INTR_EN3_LOAD_COMP register field value suitable for setting the register. */
10455 #define ALT_NAND_STAT_INTR_EN3_LOAD_COMP_SET(value) (((value) << 6) & 0x00000040)
10456 
10457 /*
10458  * Field : program_comp
10459  *
10460  * Device finished the last issued program command.
10461  *
10462  * Field Access Macros:
10463  *
10464  */
10465 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10466 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
10467 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10468 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
10469 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10470 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
10471 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
10472 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
10473 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value. */
10474 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
10475 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field. */
10476 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
10477 /* Extracts the ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP field value from a register. */
10478 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
10479 /* Produces a ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP register field value suitable for setting the register. */
10480 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
10481 
10482 /*
10483  * Field : erase_comp
10484  *
10485  * Device erase operation complete
10486  *
10487  * Field Access Macros:
10488  *
10489  */
10490 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10491 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
10492 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10493 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
10494 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10495 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
10496 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
10497 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
10498 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value. */
10499 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
10500 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field. */
10501 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
10502 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASE_COMP field value from a register. */
10503 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
10504 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASE_COMP register field value suitable for setting the register. */
10505 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
10506 
10507 /*
10508  * Field : pipe_cpybck_cmd_comp
10509  *
10510  * A pipeline command or a copyback bank command has completed on this particular
10511  * bank
10512  *
10513  * Field Access Macros:
10514  *
10515  */
10516 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10517 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
10518 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10519 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
10520 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10521 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
10522 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
10523 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10524 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value. */
10525 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10526 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field. */
10527 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10528 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP field value from a register. */
10529 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10530 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register. */
10531 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10532 
10533 /*
10534  * Field : locked_blk
10535  *
10536  * The address to program or erase operation is to a locked block and the operation
10537  * failed
10538  *
10539  * due to this reason
10540  *
10541  * Field Access Macros:
10542  *
10543  */
10544 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10545 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
10546 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10547 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
10548 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10549 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
10550 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
10551 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
10552 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value. */
10553 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
10554 /* The reset value of the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field. */
10555 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
10556 /* Extracts the ALT_NAND_STAT_INTR_EN3_LOCKED_BLK field value from a register. */
10557 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10558 /* Produces a ALT_NAND_STAT_INTR_EN3_LOCKED_BLK register field value suitable for setting the register. */
10559 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10560 
10561 /*
10562  * Field : unsup_cmd
10563  *
10564  * An unsupported command was received. This interrupt is set when an invalid
10565  * command is
10566  *
10567  * received, or when a command sequence is broken.
10568  *
10569  * Field Access Macros:
10570  *
10571  */
10572 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10573 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
10574 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10575 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
10576 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10577 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
10578 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
10579 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
10580 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value. */
10581 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10582 /* The reset value of the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field. */
10583 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
10584 /* Extracts the ALT_NAND_STAT_INTR_EN3_UNSUP_CMD field value from a register. */
10585 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10586 /* Produces a ALT_NAND_STAT_INTR_EN3_UNSUP_CMD register field value suitable for setting the register. */
10587 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10588 
10589 /*
10590  * Field : int_act
10591  *
10592  * R/B pin of device transitioned from low to high
10593  *
10594  * Field Access Macros:
10595  *
10596  */
10597 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10598 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
10599 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10600 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
10601 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10602 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
10603 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
10604 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
10605 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_INT_ACT register field value. */
10606 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
10607 /* The reset value of the ALT_NAND_STAT_INTR_EN3_INT_ACT register field. */
10608 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
10609 /* Extracts the ALT_NAND_STAT_INTR_EN3_INT_ACT field value from a register. */
10610 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10611 /* Produces a ALT_NAND_STAT_INTR_EN3_INT_ACT register field value suitable for setting the register. */
10612 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10613 
10614 /*
10615  * Field : rst_comp
10616  *
10617  * A reset command has completed on this bank
10618  *
10619  * Field Access Macros:
10620  *
10621  */
10622 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10623 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
10624 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10625 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
10626 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10627 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
10628 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
10629 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
10630 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_RST_COMP register field value. */
10631 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
10632 /* The reset value of the ALT_NAND_STAT_INTR_EN3_RST_COMP register field. */
10633 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
10634 /* Extracts the ALT_NAND_STAT_INTR_EN3_RST_COMP field value from a register. */
10635 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10636 /* Produces a ALT_NAND_STAT_INTR_EN3_RST_COMP register field value suitable for setting the register. */
10637 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10638 
10639 /*
10640  * Field : pipe_cmd_err
10641  *
10642  * A pipeline command sequence has been violated. This occurs when Map 01 page
10643  * read/write
10644  *
10645  * address does not match the corresponding expected address from the pipeline
10646  * commands issued
10647  *
10648  * earlier.
10649  *
10650  * Field Access Macros:
10651  *
10652  */
10653 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10654 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
10655 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10656 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
10657 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10658 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
10659 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
10660 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
10661 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value. */
10662 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10663 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field. */
10664 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
10665 /* Extracts the ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR field value from a register. */
10666 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10667 /* Produces a ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR register field value suitable for setting the register. */
10668 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10669 
10670 /*
10671  * Field : page_xfer_inc
10672  *
10673  * For every page of data transfer to or from the device, this bit will be set.
10674  *
10675  * Field Access Macros:
10676  *
10677  */
10678 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10679 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
10680 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10681 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
10682 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10683 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
10684 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
10685 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
10686 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value. */
10687 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10688 /* The reset value of the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field. */
10689 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
10690 /* Extracts the ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC field value from a register. */
10691 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10692 /* Produces a ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC register field value suitable for setting the register. */
10693 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10694 
10695 /*
10696  * Field : erased_page
10697  *
10698  * If an erased page is detected on reads, this bit will be set. The detection of
10699  * erased
10700  *
10701  * page is based on the number of 0's in the page. If the number of 0's in the page
10702  * being
10703  *
10704  * read is less than the value in the erase_threshold (programmable register),
10705  *
10706  * an erased page is inferred and no un-correctable error will be flagged for that
10707  * page.
10708  *
10709  * If ECC is disabled, the erased_page interrupt shall be set as explained above.
10710  * If ECC is
10711  *
10712  * enabled, in addition to the above condition, only when the ECC logic detects an
10713  *
10714  * un-correctable error for that page will the erased_page interrupt be flagged. If
10715  * the ECC
10716  *
10717  * logic detects a no-error or correctable error page, this erased page interrupt
10718  * will not
10719  *
10720  * be set.
10721  *
10722  * Field Access Macros:
10723  *
10724  */
10725 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10726 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_LSB 16
10727 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10728 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_MSB 16
10729 /* The width in bits of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10730 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_WIDTH 1
10731 /* The mask used to set the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value. */
10732 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET_MSK 0x00010000
10733 /* The mask used to clear the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value. */
10734 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_CLR_MSK 0xfffeffff
10735 /* The reset value of the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field. */
10736 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_RESET 0x0
10737 /* Extracts the ALT_NAND_STAT_INTR_EN3_ERASED_PAGE field value from a register. */
10738 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10739 /* Produces a ALT_NAND_STAT_INTR_EN3_ERASED_PAGE register field value suitable for setting the register. */
10740 #define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10741 
10742 #ifndef __ASSEMBLY__
10743 /*
10744  * WARNING: The C register and register group struct declarations are provided for
10745  * convenience and illustrative purposes. They should, however, be used with
10746  * caution as the C language standard provides no guarantees about the alignment or
10747  * atomicity of device memory accesses. The recommended practice for coding device
10748  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10749  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10750  * alt_write_dword() functions for 64 bit registers.
10751  *
10752  * The struct declaration for register ALT_NAND_STAT_INTR_EN3.
10753  */
10754 struct ALT_NAND_STAT_INTR_EN3_s
10755 {
10756  volatile uint32_t ecc_uncor_err : 1; /* ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR */
10757  uint32_t : 1; /* *UNDEFINED* */
10758  volatile uint32_t dma_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP */
10759  volatile uint32_t time_out : 1; /* ALT_NAND_STAT_INTR_EN3_TIME_OUT */
10760  volatile uint32_t program_fail : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL */
10761  volatile uint32_t erase_fail : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_FAIL */
10762  volatile uint32_t load_comp : 1; /* ALT_NAND_STAT_INTR_EN3_LOAD_COMP */
10763  volatile uint32_t program_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP */
10764  volatile uint32_t erase_comp : 1; /* ALT_NAND_STAT_INTR_EN3_ERASE_COMP */
10765  volatile uint32_t pipe_cpybck_cmd_comp : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP */
10766  volatile uint32_t locked_blk : 1; /* ALT_NAND_STAT_INTR_EN3_LOCKED_BLK */
10767  volatile uint32_t unsup_cmd : 1; /* ALT_NAND_STAT_INTR_EN3_UNSUP_CMD */
10768  volatile uint32_t int_act : 1; /* ALT_NAND_STAT_INTR_EN3_INT_ACT */
10769  volatile uint32_t rst_comp : 1; /* ALT_NAND_STAT_INTR_EN3_RST_COMP */
10770  volatile uint32_t pipe_cmd_err : 1; /* ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR */
10771  volatile uint32_t page_xfer_inc : 1; /* ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC */
10772  volatile uint32_t erased_page : 1; /* ALT_NAND_STAT_INTR_EN3_ERASED_PAGE */
10773  uint32_t : 15; /* *UNDEFINED* */
10774 };
10775 
10776 /* The typedef declaration for register ALT_NAND_STAT_INTR_EN3. */
10777 typedef struct ALT_NAND_STAT_INTR_EN3_s ALT_NAND_STAT_INTR_EN3_t;
10778 #endif /* __ASSEMBLY__ */
10779 
10780 /* The reset value of the ALT_NAND_STAT_INTR_EN3 register. */
10781 #define ALT_NAND_STAT_INTR_EN3_RESET 0x00002000
10782 /* The byte offset of the ALT_NAND_STAT_INTR_EN3 register from the beginning of the component. */
10783 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
10784 /* The address of the ALT_NAND_STAT_INTR_EN3 register. */
10785 #define ALT_NAND_STAT_INTR_EN3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_INTR_EN3_OFST))
10786 
10787 /*
10788  * Register : page_cnt3
10789  *
10790  * Decrementing page count bank 3
10791  *
10792  * Register Layout
10793  *
10794  * Bits | Access | Reset | Description
10795  * :-------|:-------|:--------|:------------------------------
10796  * [7:0] | R | 0x0 | ALT_NAND_STAT_PAGE_CNT3_VALUE
10797  * [31:8] | ??? | Unknown | *UNDEFINED*
10798  *
10799  */
10800 /*
10801  * Field : value
10802  *
10803  * Maintains a decrementing count of the number of pages in
10804  *
10805  * the multi-page (pipeline and copyback) command being executed.
10806  *
10807  * Field Access Macros:
10808  *
10809  */
10810 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10811 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
10812 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10813 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
10814 /* The width in bits of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10815 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
10816 /* The mask used to set the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
10817 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
10818 /* The mask used to clear the ALT_NAND_STAT_PAGE_CNT3_VALUE register field value. */
10819 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
10820 /* The reset value of the ALT_NAND_STAT_PAGE_CNT3_VALUE register field. */
10821 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
10822 /* Extracts the ALT_NAND_STAT_PAGE_CNT3_VALUE field value from a register. */
10823 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
10824 /* Produces a ALT_NAND_STAT_PAGE_CNT3_VALUE register field value suitable for setting the register. */
10825 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
10826 
10827 #ifndef __ASSEMBLY__
10828 /*
10829  * WARNING: The C register and register group struct declarations are provided for
10830  * convenience and illustrative purposes. They should, however, be used with
10831  * caution as the C language standard provides no guarantees about the alignment or
10832  * atomicity of device memory accesses. The recommended practice for coding device
10833  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10834  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10835  * alt_write_dword() functions for 64 bit registers.
10836  *
10837  * The struct declaration for register ALT_NAND_STAT_PAGE_CNT3.
10838  */
10839 struct ALT_NAND_STAT_PAGE_CNT3_s
10840 {
10841  const volatile uint32_t value : 8; /* ALT_NAND_STAT_PAGE_CNT3_VALUE */
10842  uint32_t : 24; /* *UNDEFINED* */
10843 };
10844 
10845 /* The typedef declaration for register ALT_NAND_STAT_PAGE_CNT3. */
10846 typedef struct ALT_NAND_STAT_PAGE_CNT3_s ALT_NAND_STAT_PAGE_CNT3_t;
10847 #endif /* __ASSEMBLY__ */
10848 
10849 /* The reset value of the ALT_NAND_STAT_PAGE_CNT3 register. */
10850 #define ALT_NAND_STAT_PAGE_CNT3_RESET 0x00000000
10851 /* The byte offset of the ALT_NAND_STAT_PAGE_CNT3 register from the beginning of the component. */
10852 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
10853 /* The address of the ALT_NAND_STAT_PAGE_CNT3 register. */
10854 #define ALT_NAND_STAT_PAGE_CNT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_PAGE_CNT3_OFST))
10855 
10856 /*
10857  * Register : err_page_addr3
10858  *
10859  * Erred page address bank 3
10860  *
10861  * Register Layout
10862  *
10863  * Bits | Access | Reset | Description
10864  * :--------|:-------|:--------|:-----------------------------------
10865  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE
10866  * [31:16] | ??? | Unknown | *UNDEFINED*
10867  *
10868  */
10869 /*
10870  * Field : value
10871  *
10872  * Holds the page address that resulted in a failure on program
10873  *
10874  * or erase operation.
10875  *
10876  * Field Access Macros:
10877  *
10878  */
10879 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10880 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
10881 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10882 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
10883 /* The width in bits of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10884 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
10885 /* The mask used to set the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
10886 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
10887 /* The mask used to clear the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value. */
10888 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
10889 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field. */
10890 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
10891 /* Extracts the ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE field value from a register. */
10892 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10893 /* Produces a ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE register field value suitable for setting the register. */
10894 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10895 
10896 #ifndef __ASSEMBLY__
10897 /*
10898  * WARNING: The C register and register group struct declarations are provided for
10899  * convenience and illustrative purposes. They should, however, be used with
10900  * caution as the C language standard provides no guarantees about the alignment or
10901  * atomicity of device memory accesses. The recommended practice for coding device
10902  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10903  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10904  * alt_write_dword() functions for 64 bit registers.
10905  *
10906  * The struct declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3.
10907  */
10908 struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s
10909 {
10910  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE */
10911  uint32_t : 16; /* *UNDEFINED* */
10912 };
10913 
10914 /* The typedef declaration for register ALT_NAND_STAT_ERR_PAGE_ADDR3. */
10915 typedef struct ALT_NAND_STAT_ERR_PAGE_ADDR3_s ALT_NAND_STAT_ERR_PAGE_ADDR3_t;
10916 #endif /* __ASSEMBLY__ */
10917 
10918 /* The reset value of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register. */
10919 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_RESET 0x00000000
10920 /* The byte offset of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register from the beginning of the component. */
10921 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
10922 /* The address of the ALT_NAND_STAT_ERR_PAGE_ADDR3 register. */
10923 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST))
10924 
10925 /*
10926  * Register : err_block_addr3
10927  *
10928  * Erred block address bank 3
10929  *
10930  * Register Layout
10931  *
10932  * Bits | Access | Reset | Description
10933  * :--------|:-------|:--------|:------------------------------------
10934  * [15:0] | R | 0x0 | ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE
10935  * [31:16] | ??? | Unknown | *UNDEFINED*
10936  *
10937  */
10938 /*
10939  * Field : value
10940  *
10941  * Holds the block address that resulted in a failure on program
10942  *
10943  * or erase operation.
10944  *
10945  * Field Access Macros:
10946  *
10947  */
10948 /* The Least Significant Bit (LSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10949 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
10950 /* The Most Significant Bit (MSB) position of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10951 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
10952 /* The width in bits of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10953 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
10954 /* The mask used to set the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
10955 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
10956 /* The mask used to clear the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value. */
10957 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
10958 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field. */
10959 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
10960 /* Extracts the ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE field value from a register. */
10961 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10962 /* Produces a ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE register field value suitable for setting the register. */
10963 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10964 
10965 #ifndef __ASSEMBLY__
10966 /*
10967  * WARNING: The C register and register group struct declarations are provided for
10968  * convenience and illustrative purposes. They should, however, be used with
10969  * caution as the C language standard provides no guarantees about the alignment or
10970  * atomicity of device memory accesses. The recommended practice for coding device
10971  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
10972  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
10973  * alt_write_dword() functions for 64 bit registers.
10974  *
10975  * The struct declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3.
10976  */
10977 struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
10978 {
10979  const volatile uint32_t value : 16; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE */
10980  uint32_t : 16; /* *UNDEFINED* */
10981 };
10982 
10983 /* The typedef declaration for register ALT_NAND_STAT_ERR_BLOCK_ADDR3. */
10984 typedef struct ALT_NAND_STAT_ERR_BLOCK_ADDR3_s ALT_NAND_STAT_ERR_BLOCK_ADDR3_t;
10985 #endif /* __ASSEMBLY__ */
10986 
10987 /* The reset value of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register. */
10988 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_RESET 0x00000000
10989 /* The byte offset of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register from the beginning of the component. */
10990 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
10991 /* The address of the ALT_NAND_STAT_ERR_BLOCK_ADDR3 register. */
10992 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST))
10993 
10994 #ifndef __ASSEMBLY__
10995 /*
10996  * WARNING: The C register and register group struct declarations are provided for
10997  * convenience and illustrative purposes. They should, however, be used with
10998  * caution as the C language standard provides no guarantees about the alignment or
10999  * atomicity of device memory accesses. The recommended practice for coding device
11000  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11001  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11002  * alt_write_dword() functions for 64 bit registers.
11003  *
11004  * The struct declaration for register group ALT_NAND_STAT.
11005  */
11006 struct ALT_NAND_STAT_s
11007 {
11008  volatile ALT_NAND_STAT_TRANSFER_MODE_t transfer_mode; /* ALT_NAND_STAT_TRANSFER_MODE */
11009  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11010  volatile ALT_NAND_STAT_INTR_STATUS0_t intr_status0; /* ALT_NAND_STAT_INTR_STATUS0 */
11011  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
11012  volatile ALT_NAND_STAT_INTR_EN0_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
11013  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
11014  volatile ALT_NAND_STAT_PAGE_CNT0_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
11015  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
11016  volatile ALT_NAND_STAT_ERR_PAGE_ADDR0_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
11017  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
11018  volatile ALT_NAND_STAT_ERR_BLOCK_ADDR0_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
11019  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
11020  volatile ALT_NAND_STAT_INTR_STATUS1_t intr_status1; /* ALT_NAND_STAT_INTR_STATUS1 */
11021  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
11022  volatile ALT_NAND_STAT_INTR_EN1_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
11023  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
11024  volatile ALT_NAND_STAT_PAGE_CNT1_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
11025  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
11026  volatile ALT_NAND_STAT_ERR_PAGE_ADDR1_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
11027  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
11028  volatile ALT_NAND_STAT_ERR_BLOCK_ADDR1_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
11029  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
11030  volatile ALT_NAND_STAT_INTR_STATUS2_t intr_status2; /* ALT_NAND_STAT_INTR_STATUS2 */
11031  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
11032  volatile ALT_NAND_STAT_INTR_EN2_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
11033  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
11034  volatile ALT_NAND_STAT_PAGE_CNT2_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
11035  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
11036  volatile ALT_NAND_STAT_ERR_PAGE_ADDR2_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
11037  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
11038  volatile ALT_NAND_STAT_ERR_BLOCK_ADDR2_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
11039  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
11040  volatile ALT_NAND_STAT_INTR_STATUS3_t intr_status3; /* ALT_NAND_STAT_INTR_STATUS3 */
11041  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
11042  volatile ALT_NAND_STAT_INTR_EN3_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
11043  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
11044  volatile ALT_NAND_STAT_PAGE_CNT3_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
11045  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
11046  volatile ALT_NAND_STAT_ERR_PAGE_ADDR3_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
11047  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
11048  volatile ALT_NAND_STAT_ERR_BLOCK_ADDR3_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
11049 };
11050 
11051 /* The typedef declaration for register group ALT_NAND_STAT. */
11052 typedef struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
11053 /* The struct declaration for the raw register contents of register group ALT_NAND_STAT. */
11054 struct ALT_NAND_STAT_raw_s
11055 {
11056  volatile uint32_t transfer_mode; /* ALT_NAND_STAT_TRANSFER_MODE */
11057  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11058  volatile uint32_t intr_status0; /* ALT_NAND_STAT_INTR_STATUS0 */
11059  volatile uint32_t _pad_0x14_0x1f[3]; /* *UNDEFINED* */
11060  volatile uint32_t intr_en0; /* ALT_NAND_STAT_INTR_EN0 */
11061  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
11062  volatile uint32_t page_cnt0; /* ALT_NAND_STAT_PAGE_CNT0 */
11063  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
11064  volatile uint32_t err_page_addr0; /* ALT_NAND_STAT_ERR_PAGE_ADDR0 */
11065  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
11066  volatile uint32_t err_block_addr0; /* ALT_NAND_STAT_ERR_BLOCK_ADDR0 */
11067  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
11068  volatile uint32_t intr_status1; /* ALT_NAND_STAT_INTR_STATUS1 */
11069  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
11070  volatile uint32_t intr_en1; /* ALT_NAND_STAT_INTR_EN1 */
11071  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
11072  volatile uint32_t page_cnt1; /* ALT_NAND_STAT_PAGE_CNT1 */
11073  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
11074  volatile uint32_t err_page_addr1; /* ALT_NAND_STAT_ERR_PAGE_ADDR1 */
11075  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
11076  volatile uint32_t err_block_addr1; /* ALT_NAND_STAT_ERR_BLOCK_ADDR1 */
11077  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
11078  volatile uint32_t intr_status2; /* ALT_NAND_STAT_INTR_STATUS2 */
11079  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
11080  volatile uint32_t intr_en2; /* ALT_NAND_STAT_INTR_EN2 */
11081  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
11082  volatile uint32_t page_cnt2; /* ALT_NAND_STAT_PAGE_CNT2 */
11083  volatile uint32_t _pad_0xd4_0xdf[3]; /* *UNDEFINED* */
11084  volatile uint32_t err_page_addr2; /* ALT_NAND_STAT_ERR_PAGE_ADDR2 */
11085  volatile uint32_t _pad_0xe4_0xef[3]; /* *UNDEFINED* */
11086  volatile uint32_t err_block_addr2; /* ALT_NAND_STAT_ERR_BLOCK_ADDR2 */
11087  volatile uint32_t _pad_0xf4_0xff[3]; /* *UNDEFINED* */
11088  volatile uint32_t intr_status3; /* ALT_NAND_STAT_INTR_STATUS3 */
11089  volatile uint32_t _pad_0x104_0x10f[3]; /* *UNDEFINED* */
11090  volatile uint32_t intr_en3; /* ALT_NAND_STAT_INTR_EN3 */
11091  volatile uint32_t _pad_0x114_0x11f[3]; /* *UNDEFINED* */
11092  volatile uint32_t page_cnt3; /* ALT_NAND_STAT_PAGE_CNT3 */
11093  volatile uint32_t _pad_0x124_0x12f[3]; /* *UNDEFINED* */
11094  volatile uint32_t err_page_addr3; /* ALT_NAND_STAT_ERR_PAGE_ADDR3 */
11095  volatile uint32_t _pad_0x134_0x13f[3]; /* *UNDEFINED* */
11096  volatile uint32_t err_block_addr3; /* ALT_NAND_STAT_ERR_BLOCK_ADDR3 */
11097 };
11098 
11099 /* The typedef declaration for the raw register contents of register group ALT_NAND_STAT. */
11100 typedef struct ALT_NAND_STAT_raw_s ALT_NAND_STAT_raw_t;
11101 #endif /* __ASSEMBLY__ */
11102 
11103 
11104 /*
11105  * Component : ECC registers - NAND_ECC
11106  * ECC registers
11107  *
11108  *
11109  */
11110 /*
11111  * Register : ecccorinfo_b01
11112  *
11113  * ECC Error correction Information register. Controller updates this register when
11114  * it completes
11115  *
11116  * a transaction. The values are held in this register till a new transaction
11117  * completes.
11118  *
11119  * Register Layout
11120  *
11121  * Bits | Access | Reset | Description
11122  * :--------|:-------|:--------|:------------------------------------------
11123  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0
11124  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0
11125  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1
11126  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1
11127  * [31:16] | ??? | Unknown | *UNDEFINED*
11128  *
11129  */
11130 /*
11131  * Field : max_errors_b0
11132  *
11133  * Maximum of number of errors corrected per sector in Bank0. This field is not
11134  * valid for
11135  *
11136  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11137  * last completed
11138  *
11139  * transaction.
11140  *
11141  * Field Access Macros:
11142  *
11143  */
11144 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
11145 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
11146 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
11147 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
11148 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
11149 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
11150 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
11151 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
11152 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value. */
11153 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
11154 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field. */
11155 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
11156 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 field value from a register. */
11157 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
11158 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 register field value suitable for setting the register. */
11159 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
11160 
11161 /*
11162  * Field : uncor_err_b0
11163  *
11164  * Uncorrectable error occurred while reading pages for last transaction in Bank0.
11165  * Uncorrectable
11166  *
11167  * errors also generate interrupts in intr_statusx register.
11168  *
11169  * Field Access Macros:
11170  *
11171  */
11172 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
11173 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
11174 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
11175 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
11176 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
11177 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
11178 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
11179 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
11180 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value. */
11181 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
11182 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field. */
11183 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
11184 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 field value from a register. */
11185 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
11186 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 register field value suitable for setting the register. */
11187 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
11188 
11189 /*
11190  * Field : max_errors_b1
11191  *
11192  * Maximum of number of errors corrected per sector in Bank1. This field is not
11193  * valid for
11194  *
11195  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11196  * last
11197  *
11198  * completed transaction.
11199  *
11200  * Field Access Macros:
11201  *
11202  */
11203 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
11204 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
11205 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
11206 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
11207 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
11208 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
11209 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
11210 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
11211 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value. */
11212 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
11213 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field. */
11214 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
11215 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 field value from a register. */
11216 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
11217 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 register field value suitable for setting the register. */
11218 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
11219 
11220 /*
11221  * Field : uncor_err_b1
11222  *
11223  * Uncorrectable error occurred while reading pages for last transaction in Bank1.
11224  * Uncorrectable
11225  *
11226  * errors also generate interrupts in intr_statusx register.
11227  *
11228  * Field Access Macros:
11229  *
11230  */
11231 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
11232 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
11233 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
11234 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
11235 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
11236 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
11237 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
11238 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
11239 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value. */
11240 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
11241 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field. */
11242 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
11243 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 field value from a register. */
11244 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
11245 /* Produces a ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 register field value suitable for setting the register. */
11246 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
11247 
11248 #ifndef __ASSEMBLY__
11249 /*
11250  * WARNING: The C register and register group struct declarations are provided for
11251  * convenience and illustrative purposes. They should, however, be used with
11252  * caution as the C language standard provides no guarantees about the alignment or
11253  * atomicity of device memory accesses. The recommended practice for coding device
11254  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11255  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11256  * alt_write_dword() functions for 64 bit registers.
11257  *
11258  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B01.
11259  */
11260 struct ALT_NAND_ECC_ECCCORINFO_B01_s
11261 {
11262  const volatile uint32_t max_errors_b0 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0 */
11263  const volatile uint32_t uncor_err_b0 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0 */
11264  const volatile uint32_t max_errors_b1 : 7; /* ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1 */
11265  const volatile uint32_t uncor_err_b1 : 1; /* ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1 */
11266  uint32_t : 16; /* *UNDEFINED* */
11267 };
11268 
11269 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B01. */
11270 typedef struct ALT_NAND_ECC_ECCCORINFO_B01_s ALT_NAND_ECC_ECCCORINFO_B01_t;
11271 #endif /* __ASSEMBLY__ */
11272 
11273 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B01 register. */
11274 #define ALT_NAND_ECC_ECCCORINFO_B01_RESET 0x00000000
11275 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B01 register from the beginning of the component. */
11276 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
11277 /* The address of the ALT_NAND_ECC_ECCCORINFO_B01 register. */
11278 #define ALT_NAND_ECC_ECCCORINFO_B01_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_ECC_ECCCORINFO_B01_OFST))
11279 
11280 /*
11281  * Register : ecccorinfo_b23
11282  *
11283  * ECC Error correction Information register. Controller updates this register when
11284  * it completes
11285  *
11286  * a transaction. The values are held in this register till a new transaction
11287  * completes.
11288  *
11289  * Register Layout
11290  *
11291  * Bits | Access | Reset | Description
11292  * :--------|:-------|:--------|:------------------------------------------
11293  * [6:0] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2
11294  * [7] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2
11295  * [14:8] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3
11296  * [15] | R | 0x0 | ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3
11297  * [31:16] | ??? | Unknown | *UNDEFINED*
11298  *
11299  */
11300 /*
11301  * Field : max_errors_b2
11302  *
11303  * Maximum of number of errors corrected per sector in Bank2. This field is not
11304  * valid for
11305  *
11306  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11307  * last completed
11308  *
11309  * transaction.
11310  *
11311  * Field Access Macros:
11312  *
11313  */
11314 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11315 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
11316 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11317 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
11318 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11319 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
11320 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
11321 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
11322 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value. */
11323 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
11324 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field. */
11325 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
11326 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 field value from a register. */
11327 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
11328 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 register field value suitable for setting the register. */
11329 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
11330 
11331 /*
11332  * Field : uncor_err_b2
11333  *
11334  * Uncorrectable error occurred while reading pages for last transaction in Bank2.
11335  * Uncorrectable
11336  *
11337  * errors also generate interrupts in intr_statusx register.
11338  *
11339  * Field Access Macros:
11340  *
11341  */
11342 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11343 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
11344 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11345 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
11346 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11347 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
11348 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
11349 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
11350 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value. */
11351 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
11352 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field. */
11353 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
11354 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 field value from a register. */
11355 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
11356 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 register field value suitable for setting the register. */
11357 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
11358 
11359 /*
11360  * Field : max_errors_b3
11361  *
11362  * Maximum of number of errors corrected per sector in Bank3. This field is not
11363  * valid for
11364  *
11365  * uncorrectable errors. A value of zero indicates that no ECC error occurred in
11366  * last
11367  *
11368  * completed transaction.
11369  *
11370  * Field Access Macros:
11371  *
11372  */
11373 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11374 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
11375 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11376 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
11377 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11378 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
11379 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
11380 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
11381 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value. */
11382 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
11383 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field. */
11384 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
11385 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 field value from a register. */
11386 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
11387 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 register field value suitable for setting the register. */
11388 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
11389 
11390 /*
11391  * Field : uncor_err_b3
11392  *
11393  * Uncorrectable error occurred while reading pages for last transaction in Bank3.
11394  * Uncorrectable
11395  *
11396  * errors also generate interrupts in intr_statusx register.
11397  *
11398  * Field Access Macros:
11399  *
11400  */
11401 /* The Least Significant Bit (LSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11402 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
11403 /* The Most Significant Bit (MSB) position of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11404 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
11405 /* The width in bits of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11406 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
11407 /* The mask used to set the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
11408 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
11409 /* The mask used to clear the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value. */
11410 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
11411 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field. */
11412 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
11413 /* Extracts the ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 field value from a register. */
11414 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
11415 /* Produces a ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 register field value suitable for setting the register. */
11416 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
11417 
11418 #ifndef __ASSEMBLY__
11419 /*
11420  * WARNING: The C register and register group struct declarations are provided for
11421  * convenience and illustrative purposes. They should, however, be used with
11422  * caution as the C language standard provides no guarantees about the alignment or
11423  * atomicity of device memory accesses. The recommended practice for coding device
11424  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11425  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11426  * alt_write_dword() functions for 64 bit registers.
11427  *
11428  * The struct declaration for register ALT_NAND_ECC_ECCCORINFO_B23.
11429  */
11430 struct ALT_NAND_ECC_ECCCORINFO_B23_s
11431 {
11432  const volatile uint32_t max_errors_b2 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2 */
11433  const volatile uint32_t uncor_err_b2 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2 */
11434  const volatile uint32_t max_errors_b3 : 7; /* ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3 */
11435  const volatile uint32_t uncor_err_b3 : 1; /* ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3 */
11436  uint32_t : 16; /* *UNDEFINED* */
11437 };
11438 
11439 /* The typedef declaration for register ALT_NAND_ECC_ECCCORINFO_B23. */
11440 typedef struct ALT_NAND_ECC_ECCCORINFO_B23_s ALT_NAND_ECC_ECCCORINFO_B23_t;
11441 #endif /* __ASSEMBLY__ */
11442 
11443 /* The reset value of the ALT_NAND_ECC_ECCCORINFO_B23 register. */
11444 #define ALT_NAND_ECC_ECCCORINFO_B23_RESET 0x00000000
11445 /* The byte offset of the ALT_NAND_ECC_ECCCORINFO_B23 register from the beginning of the component. */
11446 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
11447 /* The address of the ALT_NAND_ECC_ECCCORINFO_B23 register. */
11448 #define ALT_NAND_ECC_ECCCORINFO_B23_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_ECC_ECCCORINFO_B23_OFST))
11449 
11450 #ifndef __ASSEMBLY__
11451 /*
11452  * WARNING: The C register and register group struct declarations are provided for
11453  * convenience and illustrative purposes. They should, however, be used with
11454  * caution as the C language standard provides no guarantees about the alignment or
11455  * atomicity of device memory accesses. The recommended practice for coding device
11456  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11457  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11458  * alt_write_dword() functions for 64 bit registers.
11459  *
11460  * The struct declaration for register group ALT_NAND_ECC.
11461  */
11462 struct ALT_NAND_ECC_s
11463 {
11464  volatile ALT_NAND_ECC_ECCCORINFO_B01_t ecccorinfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
11465  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11466  volatile ALT_NAND_ECC_ECCCORINFO_B23_t ecccorinfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
11467 };
11468 
11469 /* The typedef declaration for register group ALT_NAND_ECC. */
11470 typedef struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
11471 /* The struct declaration for the raw register contents of register group ALT_NAND_ECC. */
11472 struct ALT_NAND_ECC_raw_s
11473 {
11474  volatile uint32_t ecccorinfo_b01; /* ALT_NAND_ECC_ECCCORINFO_B01 */
11475  volatile uint32_t _pad_0x4_0xf[3]; /* *UNDEFINED* */
11476  volatile uint32_t ecccorinfo_b23; /* ALT_NAND_ECC_ECCCORINFO_B23 */
11477 };
11478 
11479 /* The typedef declaration for the raw register contents of register group ALT_NAND_ECC. */
11480 typedef struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
11481 #endif /* __ASSEMBLY__ */
11482 
11483 
11484 /*
11485  * Component : DMA registers - NAND_DMA
11486  * DMA registers
11487  *
11488  *
11489  */
11490 /*
11491  * Register : dma_enable
11492  *
11493  * Register Layout
11494  *
11495  * Bits | Access | Reset | Description
11496  * :-------|:-------|:--------|:-----------------------------
11497  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_ENABLE_FLAG
11498  * [31:1] | ??? | Unknown | *UNDEFINED*
11499  *
11500  */
11501 /*
11502  * Field : flag
11503  *
11504  * Enables data DMA operation in the controller
11505  *
11506  * 1 - Enable DMA 0 - Disable DMA
11507  *
11508  * Field Access Macros:
11509  *
11510  */
11511 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_ENABLE_FLAG register field. */
11512 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_LSB 0
11513 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_ENABLE_FLAG register field. */
11514 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_MSB 0
11515 /* The width in bits of the ALT_NAND_DMA_DMA_ENABLE_FLAG register field. */
11516 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_WIDTH 1
11517 /* The mask used to set the ALT_NAND_DMA_DMA_ENABLE_FLAG register field value. */
11518 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_SET_MSK 0x00000001
11519 /* The mask used to clear the ALT_NAND_DMA_DMA_ENABLE_FLAG register field value. */
11520 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_CLR_MSK 0xfffffffe
11521 /* The reset value of the ALT_NAND_DMA_DMA_ENABLE_FLAG register field. */
11522 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_RESET 0x0
11523 /* Extracts the ALT_NAND_DMA_DMA_ENABLE_FLAG field value from a register. */
11524 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
11525 /* Produces a ALT_NAND_DMA_DMA_ENABLE_FLAG register field value suitable for setting the register. */
11526 #define ALT_NAND_DMA_DMA_ENABLE_FLAG_SET(value) (((value) << 0) & 0x00000001)
11527 
11528 #ifndef __ASSEMBLY__
11529 /*
11530  * WARNING: The C register and register group struct declarations are provided for
11531  * convenience and illustrative purposes. They should, however, be used with
11532  * caution as the C language standard provides no guarantees about the alignment or
11533  * atomicity of device memory accesses. The recommended practice for coding device
11534  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11535  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11536  * alt_write_dword() functions for 64 bit registers.
11537  *
11538  * The struct declaration for register ALT_NAND_DMA_DMA_ENABLE.
11539  */
11540 struct ALT_NAND_DMA_DMA_ENABLE_s
11541 {
11542  volatile uint32_t flag : 1; /* ALT_NAND_DMA_DMA_ENABLE_FLAG */
11543  uint32_t : 31; /* *UNDEFINED* */
11544 };
11545 
11546 /* The typedef declaration for register ALT_NAND_DMA_DMA_ENABLE. */
11547 typedef struct ALT_NAND_DMA_DMA_ENABLE_s ALT_NAND_DMA_DMA_ENABLE_t;
11548 #endif /* __ASSEMBLY__ */
11549 
11550 /* The reset value of the ALT_NAND_DMA_DMA_ENABLE register. */
11551 #define ALT_NAND_DMA_DMA_ENABLE_RESET 0x00000000
11552 /* The byte offset of the ALT_NAND_DMA_DMA_ENABLE register from the beginning of the component. */
11553 #define ALT_NAND_DMA_DMA_ENABLE_OFST 0x0
11554 /* The address of the ALT_NAND_DMA_DMA_ENABLE register. */
11555 #define ALT_NAND_DMA_DMA_ENABLE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_ENABLE_OFST))
11556 
11557 /*
11558  * Register : dma_intr
11559  *
11560  * DMA interrupt register
11561  *
11562  * Register Layout
11563  *
11564  * Bits | Access | Reset | Description
11565  * :-------|:-------|:--------|:-----------------------------------------
11566  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_TARGET_ERROR
11567  * [1] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0
11568  * [2] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1
11569  * [3] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2
11570  * [4] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3
11571  * [5] | ??? | Unknown | *UNDEFINED*
11572  * [6] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE
11573  * [31:7] | ??? | Unknown | *UNDEFINED*
11574  *
11575  */
11576 /*
11577  * Field : target_error
11578  *
11579  * Controller initiator interface received an ERROR target response for a
11580  * transaction.
11581  *
11582  * Field Access Macros:
11583  *
11584  */
11585 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field. */
11586 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_LSB 0
11587 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field. */
11588 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_MSB 0
11589 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field. */
11590 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_WIDTH 1
11591 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field value. */
11592 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_SET_MSK 0x00000001
11593 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field value. */
11594 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_CLR_MSK 0xfffffffe
11595 /* The reset value of the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field. */
11596 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_RESET 0x0
11597 /* Extracts the ALT_NAND_DMA_DMA_INTR_TARGET_ERROR field value from a register. */
11598 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11599 /* Produces a ALT_NAND_DMA_DMA_INTR_TARGET_ERROR register field value suitable for setting the register. */
11600 #define ALT_NAND_DMA_DMA_INTR_TARGET_ERROR_SET(value) (((value) << 0) & 0x00000001)
11601 
11602 /*
11603  * Field : desc_comp_channel0
11604  *
11605  * Indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt
11606  * bit in cmd flags set).
11607  *
11608  * Field Access Macros:
11609  *
11610  */
11611 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11612 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_LSB 1
11613 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11614 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_MSB 1
11615 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11616 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_WIDTH 1
11617 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value. */
11618 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11619 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value. */
11620 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11621 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field. */
11622 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_RESET 0x0
11623 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 field value from a register. */
11624 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11625 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 register field value suitable for setting the register. */
11626 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11627 
11628 /*
11629  * Field : desc_comp_channel1
11630  *
11631  * Indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt
11632  * bit in cmd flags set).
11633  *
11634  * Field Access Macros:
11635  *
11636  */
11637 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11638 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_LSB 2
11639 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11640 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_MSB 2
11641 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11642 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_WIDTH 1
11643 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value. */
11644 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11645 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value. */
11646 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11647 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field. */
11648 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_RESET 0x0
11649 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 field value from a register. */
11650 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11651 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 register field value suitable for setting the register. */
11652 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11653 
11654 /*
11655  * Field : desc_comp_channel2
11656  *
11657  * Indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt
11658  * bit in cmd flags set).
11659  *
11660  * Field Access Macros:
11661  *
11662  */
11663 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11664 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_LSB 3
11665 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11666 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_MSB 3
11667 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11668 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_WIDTH 1
11669 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value. */
11670 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11671 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value. */
11672 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11673 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field. */
11674 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_RESET 0x0
11675 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 field value from a register. */
11676 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11677 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 register field value suitable for setting the register. */
11678 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11679 
11680 /*
11681  * Field : desc_comp_channel3
11682  *
11683  * Indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt
11684  * bit in cmd flags set).
11685  *
11686  * Field Access Macros:
11687  *
11688  */
11689 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11690 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_LSB 4
11691 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11692 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_MSB 4
11693 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11694 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_WIDTH 1
11695 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value. */
11696 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11697 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value. */
11698 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11699 /* The reset value of the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field. */
11700 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_RESET 0x0
11701 /* Extracts the ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 field value from a register. */
11702 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11703 /* Produces a ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 register field value suitable for setting the register. */
11704 #define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11705 
11706 /*
11707  * Field : cmddma_idle
11708  *
11709  * Command DMA became IDLE after completing all descriptors
11710  *
11711  * Field Access Macros:
11712  *
11713  */
11714 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11715 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_LSB 6
11716 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11717 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_MSB 6
11718 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11719 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_WIDTH 1
11720 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value. */
11721 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET_MSK 0x00000040
11722 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value. */
11723 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11724 /* The reset value of the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field. */
11725 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_RESET 0x0
11726 /* Extracts the ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE field value from a register. */
11727 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11728 /* Produces a ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE register field value suitable for setting the register. */
11729 #define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11730 
11731 #ifndef __ASSEMBLY__
11732 /*
11733  * WARNING: The C register and register group struct declarations are provided for
11734  * convenience and illustrative purposes. They should, however, be used with
11735  * caution as the C language standard provides no guarantees about the alignment or
11736  * atomicity of device memory accesses. The recommended practice for coding device
11737  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11738  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11739  * alt_write_dword() functions for 64 bit registers.
11740  *
11741  * The struct declaration for register ALT_NAND_DMA_DMA_INTR.
11742  */
11743 struct ALT_NAND_DMA_DMA_INTR_s
11744 {
11745  volatile uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_TARGET_ERROR */
11746  volatile uint32_t desc_comp_channel0 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0 */
11747  volatile uint32_t desc_comp_channel1 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1 */
11748  volatile uint32_t desc_comp_channel2 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2 */
11749  volatile uint32_t desc_comp_channel3 : 1; /* ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3 */
11750  uint32_t : 1; /* *UNDEFINED* */
11751  volatile uint32_t cmddma_idle : 1; /* ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE */
11752  uint32_t : 25; /* *UNDEFINED* */
11753 };
11754 
11755 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR. */
11756 typedef struct ALT_NAND_DMA_DMA_INTR_s ALT_NAND_DMA_DMA_INTR_t;
11757 #endif /* __ASSEMBLY__ */
11758 
11759 /* The reset value of the ALT_NAND_DMA_DMA_INTR register. */
11760 #define ALT_NAND_DMA_DMA_INTR_RESET 0x00000000
11761 /* The byte offset of the ALT_NAND_DMA_DMA_INTR register from the beginning of the component. */
11762 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
11763 /* The address of the ALT_NAND_DMA_DMA_INTR register. */
11764 #define ALT_NAND_DMA_DMA_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_INTR_OFST))
11765 
11766 /*
11767  * Register : dma_intr_en
11768  *
11769  * Enables corresponding interrupt bit in dma interrupt register
11770  *
11771  * Register Layout
11772  *
11773  * Bits | Access | Reset | Description
11774  * :-------|:-------|:--------|:--------------------------------------------
11775  * [0] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR
11776  * [1] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0
11777  * [2] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1
11778  * [3] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2
11779  * [4] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3
11780  * [5] | ??? | Unknown | *UNDEFINED*
11781  * [6] | RW | 0x0 | ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE
11782  * [31:7] | ??? | Unknown | *UNDEFINED*
11783  *
11784  */
11785 /*
11786  * Field : target_error
11787  *
11788  * Controller initiator interface received an ERROR target response for a
11789  * transaction.
11790  *
11791  * Field Access Macros:
11792  *
11793  */
11794 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field. */
11795 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_LSB 0
11796 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field. */
11797 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_MSB 0
11798 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field. */
11799 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_WIDTH 1
11800 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field value. */
11801 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_SET_MSK 0x00000001
11802 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field value. */
11803 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_CLR_MSK 0xfffffffe
11804 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field. */
11805 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_RESET 0x0
11806 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR field value from a register. */
11807 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11808 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR register field value suitable for setting the register. */
11809 #define ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR_SET(value) (((value) << 0) & 0x00000001)
11810 
11811 /*
11812  * Field : desc_comp_channel0
11813  *
11814  * Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated
11815  * when interrupt bit in cmd flags set).
11816  *
11817  * Field Access Macros:
11818  *
11819  */
11820 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11821 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB 1
11822 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11823 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB 1
11824 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11825 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH 1
11826 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value. */
11827 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11828 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value. */
11829 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11830 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field. */
11831 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET 0x0
11832 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 field value from a register. */
11833 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11834 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value suitable for setting the register. */
11835 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11836 
11837 /*
11838  * Field : desc_comp_channel1
11839  *
11840  * Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated
11841  * when interrupt bit in cmd flags set).
11842  *
11843  * Field Access Macros:
11844  *
11845  */
11846 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11847 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB 2
11848 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11849 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB 2
11850 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11851 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH 1
11852 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value. */
11853 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11854 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value. */
11855 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11856 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field. */
11857 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET 0x0
11858 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 field value from a register. */
11859 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11860 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value suitable for setting the register. */
11861 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11862 
11863 /*
11864  * Field : desc_comp_channel2
11865  *
11866  * Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated
11867  * when interrupt bit in cmd flags set).
11868  *
11869  * Field Access Macros:
11870  *
11871  */
11872 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11873 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB 3
11874 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11875 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB 3
11876 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11877 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH 1
11878 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value. */
11879 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11880 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value. */
11881 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11882 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field. */
11883 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET 0x0
11884 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 field value from a register. */
11885 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11886 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value suitable for setting the register. */
11887 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11888 
11889 /*
11890  * Field : desc_comp_channel3
11891  *
11892  * Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated
11893  * when interrupt bit in cmd flags set).
11894  *
11895  * Field Access Macros:
11896  *
11897  */
11898 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11899 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB 4
11900 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11901 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB 4
11902 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11903 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH 1
11904 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value. */
11905 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11906 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value. */
11907 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11908 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field. */
11909 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET 0x0
11910 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 field value from a register. */
11911 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11912 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value suitable for setting the register. */
11913 #define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11914 
11915 /*
11916  * Field : cmddma_idle
11917  *
11918  * Interrupt processor when command DMA becomes IDLE after completing all
11919  *
11920  * descriptors.
11921  *
11922  * Field Access Macros:
11923  *
11924  */
11925 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11926 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB 6
11927 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11928 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB 6
11929 /* The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11930 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH 1
11931 /* The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value. */
11932 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK 0x00000040
11933 /* The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value. */
11934 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11935 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field. */
11936 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET 0x0
11937 /* Extracts the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE field value from a register. */
11938 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11939 /* Produces a ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value suitable for setting the register. */
11940 #define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11941 
11942 #ifndef __ASSEMBLY__
11943 /*
11944  * WARNING: The C register and register group struct declarations are provided for
11945  * convenience and illustrative purposes. They should, however, be used with
11946  * caution as the C language standard provides no guarantees about the alignment or
11947  * atomicity of device memory accesses. The recommended practice for coding device
11948  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
11949  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
11950  * alt_write_dword() functions for 64 bit registers.
11951  *
11952  * The struct declaration for register ALT_NAND_DMA_DMA_INTR_EN.
11953  */
11954 struct ALT_NAND_DMA_DMA_INTR_EN_s
11955 {
11956  volatile uint32_t target_error : 1; /* ALT_NAND_DMA_DMA_INTR_EN_TARGET_ERROR */
11957  volatile uint32_t desc_comp_channel0 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 */
11958  volatile uint32_t desc_comp_channel1 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 */
11959  volatile uint32_t desc_comp_channel2 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 */
11960  volatile uint32_t desc_comp_channel3 : 1; /* ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 */
11961  uint32_t : 1; /* *UNDEFINED* */
11962  volatile uint32_t cmddma_idle : 1; /* ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE */
11963  uint32_t : 25; /* *UNDEFINED* */
11964 };
11965 
11966 /* The typedef declaration for register ALT_NAND_DMA_DMA_INTR_EN. */
11967 typedef struct ALT_NAND_DMA_DMA_INTR_EN_s ALT_NAND_DMA_DMA_INTR_EN_t;
11968 #endif /* __ASSEMBLY__ */
11969 
11970 /* The reset value of the ALT_NAND_DMA_DMA_INTR_EN register. */
11971 #define ALT_NAND_DMA_DMA_INTR_EN_RESET 0x00000000
11972 /* The byte offset of the ALT_NAND_DMA_DMA_INTR_EN register from the beginning of the component. */
11973 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
11974 /* The address of the ALT_NAND_DMA_DMA_INTR_EN register. */
11975 #define ALT_NAND_DMA_DMA_INTR_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_DMA_INTR_EN_OFST))
11976 
11977 /*
11978  * Register : target_err_addr_lo
11979  *
11980  * Transaction address for which controller initiator interface received an ERROR
11981  * target response.
11982  *
11983  * Register Layout
11984  *
11985  * Bits | Access | Reset | Description
11986  * :--------|:-------|:--------|:--------------------------------------
11987  * [15:0] | R | 0x0 | ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE
11988  * [31:16] | ??? | Unknown | *UNDEFINED*
11989  *
11990  */
11991 /*
11992  * Field : value
11993  *
11994  * Least significant 16 bits
11995  *
11996  * Field Access Macros:
11997  *
11998  */
11999 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field. */
12000 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_LSB 0
12001 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field. */
12002 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_MSB 15
12003 /* The width in bits of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field. */
12004 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_WIDTH 16
12005 /* The mask used to set the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field value. */
12006 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
12007 /* The mask used to clear the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field value. */
12008 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
12009 /* The reset value of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field. */
12010 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_RESET 0x0
12011 /* Extracts the ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE field value from a register. */
12012 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12013 /* Produces a ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE register field value suitable for setting the register. */
12014 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12015 
12016 #ifndef __ASSEMBLY__
12017 /*
12018  * WARNING: The C register and register group struct declarations are provided for
12019  * convenience and illustrative purposes. They should, however, be used with
12020  * caution as the C language standard provides no guarantees about the alignment or
12021  * atomicity of device memory accesses. The recommended practice for coding device
12022  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12023  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12024  * alt_write_dword() functions for 64 bit registers.
12025  *
12026  * The struct declaration for register ALT_NAND_DMA_TARGET_ERR_ADDR_LO.
12027  */
12028 struct ALT_NAND_DMA_TARGET_ERR_ADDR_LO_s
12029 {
12030  const volatile uint32_t value : 16; /* ALT_NAND_DMA_TARGET_ERR_ADDR_LO_VALUE */
12031  uint32_t : 16; /* *UNDEFINED* */
12032 };
12033 
12034 /* The typedef declaration for register ALT_NAND_DMA_TARGET_ERR_ADDR_LO. */
12035 typedef struct ALT_NAND_DMA_TARGET_ERR_ADDR_LO_s ALT_NAND_DMA_TARGET_ERR_ADDR_LO_t;
12036 #endif /* __ASSEMBLY__ */
12037 
12038 /* The reset value of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO register. */
12039 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_RESET 0x00000000
12040 /* The byte offset of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO register from the beginning of the component. */
12041 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_OFST 0x40
12042 /* The address of the ALT_NAND_DMA_TARGET_ERR_ADDR_LO register. */
12043 #define ALT_NAND_DMA_TARGET_ERR_ADDR_LO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_TARGET_ERR_ADDR_LO_OFST))
12044 
12045 /*
12046  * Register : target_err_addr_hi
12047  *
12048  * Transaction address for which controller initiator interface received an ERROR
12049  * target response.
12050  *
12051  * Register Layout
12052  *
12053  * Bits | Access | Reset | Description
12054  * :--------|:-------|:--------|:--------------------------------------
12055  * [15:0] | R | 0x0 | ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE
12056  * [31:16] | ??? | Unknown | *UNDEFINED*
12057  *
12058  */
12059 /*
12060  * Field : value
12061  *
12062  * Most significant 16 bits
12063  *
12064  * Field Access Macros:
12065  *
12066  */
12067 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field. */
12068 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_LSB 0
12069 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field. */
12070 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_MSB 15
12071 /* The width in bits of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field. */
12072 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_WIDTH 16
12073 /* The mask used to set the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field value. */
12074 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
12075 /* The mask used to clear the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field value. */
12076 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
12077 /* The reset value of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field. */
12078 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_RESET 0x0
12079 /* Extracts the ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE field value from a register. */
12080 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12081 /* Produces a ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE register field value suitable for setting the register. */
12082 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12083 
12084 #ifndef __ASSEMBLY__
12085 /*
12086  * WARNING: The C register and register group struct declarations are provided for
12087  * convenience and illustrative purposes. They should, however, be used with
12088  * caution as the C language standard provides no guarantees about the alignment or
12089  * atomicity of device memory accesses. The recommended practice for coding device
12090  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12091  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12092  * alt_write_dword() functions for 64 bit registers.
12093  *
12094  * The struct declaration for register ALT_NAND_DMA_TARGET_ERR_ADDR_HI.
12095  */
12096 struct ALT_NAND_DMA_TARGET_ERR_ADDR_HI_s
12097 {
12098  const volatile uint32_t value : 16; /* ALT_NAND_DMA_TARGET_ERR_ADDR_HI_VALUE */
12099  uint32_t : 16; /* *UNDEFINED* */
12100 };
12101 
12102 /* The typedef declaration for register ALT_NAND_DMA_TARGET_ERR_ADDR_HI. */
12103 typedef struct ALT_NAND_DMA_TARGET_ERR_ADDR_HI_s ALT_NAND_DMA_TARGET_ERR_ADDR_HI_t;
12104 #endif /* __ASSEMBLY__ */
12105 
12106 /* The reset value of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI register. */
12107 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_RESET 0x00000000
12108 /* The byte offset of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI register from the beginning of the component. */
12109 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_OFST 0x50
12110 /* The address of the ALT_NAND_DMA_TARGET_ERR_ADDR_HI register. */
12111 #define ALT_NAND_DMA_TARGET_ERR_ADDR_HI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_TARGET_ERR_ADDR_HI_OFST))
12112 
12113 /*
12114  * Register : chnl_active
12115  *
12116  * Indicates CMD-DMA channel activity status
12117  *
12118  * Register Layout
12119  *
12120  * Bits | Access | Reset | Description
12121  * :-------|:-------|:--------|:----------------------------------
12122  * [0] | R | 0x0 | ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0
12123  * [1] | R | 0x0 | ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1
12124  * [2] | R | 0x0 | ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2
12125  * [3] | R | 0x0 | ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3
12126  * [31:4] | ??? | Unknown | *UNDEFINED*
12127  *
12128  */
12129 /*
12130  * Field : channel0
12131  *
12132  * CMD-DMA channel 0 is active
12133  *
12134  * Field Access Macros:
12135  *
12136  */
12137 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field. */
12138 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_LSB 0
12139 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field. */
12140 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_MSB 0
12141 /* The width in bits of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field. */
12142 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_WIDTH 1
12143 /* The mask used to set the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field value. */
12144 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_SET_MSK 0x00000001
12145 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field value. */
12146 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_CLR_MSK 0xfffffffe
12147 /* The reset value of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field. */
12148 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_RESET 0x0
12149 /* Extracts the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 field value from a register. */
12150 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12151 /* Produces a ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 register field value suitable for setting the register. */
12152 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12153 
12154 /*
12155  * Field : channel1
12156  *
12157  * CMD-DMA channel 1 is active
12158  *
12159  * Field Access Macros:
12160  *
12161  */
12162 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field. */
12163 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_LSB 1
12164 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field. */
12165 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_MSB 1
12166 /* The width in bits of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field. */
12167 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_WIDTH 1
12168 /* The mask used to set the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field value. */
12169 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_SET_MSK 0x00000002
12170 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field value. */
12171 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_CLR_MSK 0xfffffffd
12172 /* The reset value of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field. */
12173 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_RESET 0x0
12174 /* Extracts the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 field value from a register. */
12175 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12176 /* Produces a ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 register field value suitable for setting the register. */
12177 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12178 
12179 /*
12180  * Field : channel2
12181  *
12182  * CMD-DMA channel 2 is active
12183  *
12184  * Field Access Macros:
12185  *
12186  */
12187 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field. */
12188 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_LSB 2
12189 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field. */
12190 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_MSB 2
12191 /* The width in bits of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field. */
12192 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_WIDTH 1
12193 /* The mask used to set the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field value. */
12194 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_SET_MSK 0x00000004
12195 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field value. */
12196 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_CLR_MSK 0xfffffffb
12197 /* The reset value of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field. */
12198 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_RESET 0x0
12199 /* Extracts the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 field value from a register. */
12200 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12201 /* Produces a ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 register field value suitable for setting the register. */
12202 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12203 
12204 /*
12205  * Field : channel3
12206  *
12207  * CMD-DMA channel 3 is active
12208  *
12209  * Field Access Macros:
12210  *
12211  */
12212 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field. */
12213 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_LSB 3
12214 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field. */
12215 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_MSB 3
12216 /* The width in bits of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field. */
12217 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_WIDTH 1
12218 /* The mask used to set the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field value. */
12219 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_SET_MSK 0x00000008
12220 /* The mask used to clear the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field value. */
12221 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_CLR_MSK 0xfffffff7
12222 /* The reset value of the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field. */
12223 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_RESET 0x0
12224 /* Extracts the ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 field value from a register. */
12225 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12226 /* Produces a ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 register field value suitable for setting the register. */
12227 #define ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12228 
12229 #ifndef __ASSEMBLY__
12230 /*
12231  * WARNING: The C register and register group struct declarations are provided for
12232  * convenience and illustrative purposes. They should, however, be used with
12233  * caution as the C language standard provides no guarantees about the alignment or
12234  * atomicity of device memory accesses. The recommended practice for coding device
12235  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12236  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12237  * alt_write_dword() functions for 64 bit registers.
12238  *
12239  * The struct declaration for register ALT_NAND_DMA_CHNL_ACTIVE.
12240  */
12241 struct ALT_NAND_DMA_CHNL_ACTIVE_s
12242 {
12243  const volatile uint32_t channel0 : 1; /* ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL0 */
12244  const volatile uint32_t channel1 : 1; /* ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL1 */
12245  const volatile uint32_t channel2 : 1; /* ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL2 */
12246  const volatile uint32_t channel3 : 1; /* ALT_NAND_DMA_CHNL_ACTIVE_CHANNEL3 */
12247  uint32_t : 28; /* *UNDEFINED* */
12248 };
12249 
12250 /* The typedef declaration for register ALT_NAND_DMA_CHNL_ACTIVE. */
12251 typedef struct ALT_NAND_DMA_CHNL_ACTIVE_s ALT_NAND_DMA_CHNL_ACTIVE_t;
12252 #endif /* __ASSEMBLY__ */
12253 
12254 /* The reset value of the ALT_NAND_DMA_CHNL_ACTIVE register. */
12255 #define ALT_NAND_DMA_CHNL_ACTIVE_RESET 0x00000000
12256 /* The byte offset of the ALT_NAND_DMA_CHNL_ACTIVE register from the beginning of the component. */
12257 #define ALT_NAND_DMA_CHNL_ACTIVE_OFST 0x60
12258 /* The address of the ALT_NAND_DMA_CHNL_ACTIVE register. */
12259 #define ALT_NAND_DMA_CHNL_ACTIVE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CHNL_ACTIVE_OFST))
12260 
12261 /*
12262  * Register : flash_burst_length
12263  *
12264  * Register Layout
12265  *
12266  * Bits | Access | Reset | Description
12267  * :-------|:-------|:--------|:-----------------------------------------------------------
12268  * [1:0] | RW | 0x1 | ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE
12269  * [3:2] | ??? | Unknown | *UNDEFINED*
12270  * [4] | RW | 0x0 | ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST
12271  * [7:5] | ??? | Unknown | *UNDEFINED*
12272  * [31:8] | RW | 0x0 | ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE
12273  *
12274  */
12275 /*
12276  * Field : value
12277  *
12278  * Sets the burst used by data dma for transferring data to/from flash device.
12279  *
12280  * This burst length is different and is larger than the burst length on the
12281  *
12282  * host bus so that larger amount of data can be transferred to/from device,
12283  *
12284  * descreasing controller data transfer overhead in the process.
12285  *
12286  * 00 - 64 bytes, 01 - 128 bytes, 10 - 256 bytes, 11 - 512 bytes.
12287  *
12288  * The host burst size multiplied by the number of outstanding requests on the
12289  *
12290  * host side should be greater than equal to this value. If not, the device side
12291  *
12292  * burst length will be equal to host side burst length.
12293  *
12294  * Field Access Macros:
12295  *
12296  */
12297 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field. */
12298 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_LSB 0
12299 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field. */
12300 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_MSB 1
12301 /* The width in bits of the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field. */
12302 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_WIDTH 2
12303 /* The mask used to set the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field value. */
12304 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_SET_MSK 0x00000003
12305 /* The mask used to clear the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field value. */
12306 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_CLR_MSK 0xfffffffc
12307 /* The reset value of the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field. */
12308 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_RESET 0x1
12309 /* Extracts the ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE field value from a register. */
12310 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
12311 /* Produces a ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE register field value suitable for setting the register. */
12312 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
12313 
12314 /*
12315  * Field : continous_burst
12316  *
12317  * When this bit is set, the Data DMA will burst the entire page from/to the
12318  *
12319  * flash device. Please make sure that the host system can provide/sink data
12320  *
12321  * at a fast pace to avoid unnecessary pausing of data on the device interface.
12322  *
12323  * Field Access Macros:
12324  *
12325  */
12326 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field. */
12327 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_LSB 4
12328 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field. */
12329 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_MSB 4
12330 /* The width in bits of the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field. */
12331 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_WIDTH 1
12332 /* The mask used to set the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field value. */
12333 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_SET_MSK 0x00000010
12334 /* The mask used to clear the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field value. */
12335 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_CLR_MSK 0xffffffef
12336 /* The reset value of the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field. */
12337 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_RESET 0x0
12338 /* Extracts the ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST field value from a register. */
12339 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
12340 /* Produces a ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST register field value suitable for setting the register. */
12341 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
12342 
12343 /*
12344  * Field : polling_sync_counter_value
12345  *
12346  * Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer
12347  * again.
12348  *
12349  * If this counter value is 0, no polling is done.
12350  *
12351  * Field Access Macros:
12352  *
12353  */
12354 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field. */
12355 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_LSB 8
12356 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field. */
12357 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_MSB 31
12358 /* The width in bits of the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field. */
12359 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_WIDTH 24
12360 /* The mask used to set the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field value. */
12361 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_SET_MSK 0xffffff00
12362 /* The mask used to clear the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field value. */
12363 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_CLR_MSK 0x000000ff
12364 /* The reset value of the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field. */
12365 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_RESET 0x0
12366 /* Extracts the ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE field value from a register. */
12367 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_GET(value) (((value) & 0xffffff00) >> 8)
12368 /* Produces a ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE register field value suitable for setting the register. */
12369 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE_SET(value) (((value) << 8) & 0xffffff00)
12370 
12371 #ifndef __ASSEMBLY__
12372 /*
12373  * WARNING: The C register and register group struct declarations are provided for
12374  * convenience and illustrative purposes. They should, however, be used with
12375  * caution as the C language standard provides no guarantees about the alignment or
12376  * atomicity of device memory accesses. The recommended practice for coding device
12377  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12378  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12379  * alt_write_dword() functions for 64 bit registers.
12380  *
12381  * The struct declaration for register ALT_NAND_DMA_FLASH_BURST_LENGTH.
12382  */
12383 struct ALT_NAND_DMA_FLASH_BURST_LENGTH_s
12384 {
12385  volatile uint32_t value : 2; /* ALT_NAND_DMA_FLASH_BURST_LENGTH_VALUE */
12386  uint32_t : 2; /* *UNDEFINED* */
12387  volatile uint32_t continous_burst : 1; /* ALT_NAND_DMA_FLASH_BURST_LENGTH_CONTINOUS_BURST */
12388  uint32_t : 3; /* *UNDEFINED* */
12389  volatile uint32_t polling_sync_counter_value : 24; /* ALT_NAND_DMA_FLASH_BURST_LENGTH_POLLING_SYNC_COUNTER_VALUE */
12390 };
12391 
12392 /* The typedef declaration for register ALT_NAND_DMA_FLASH_BURST_LENGTH. */
12393 typedef struct ALT_NAND_DMA_FLASH_BURST_LENGTH_s ALT_NAND_DMA_FLASH_BURST_LENGTH_t;
12394 #endif /* __ASSEMBLY__ */
12395 
12396 /* The reset value of the ALT_NAND_DMA_FLASH_BURST_LENGTH register. */
12397 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_RESET 0x00000001
12398 /* The byte offset of the ALT_NAND_DMA_FLASH_BURST_LENGTH register from the beginning of the component. */
12399 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_OFST 0x70
12400 /* The address of the ALT_NAND_DMA_FLASH_BURST_LENGTH register. */
12401 #define ALT_NAND_DMA_FLASH_BURST_LENGTH_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_FLASH_BURST_LENGTH_OFST))
12402 
12403 /*
12404  * Register : chip_interleave_enable_and_allow_int_reads
12405  *
12406  * Register Layout
12407  *
12408  * Bits | Access | Reset | Description
12409  * :-------|:-------|:--------|:------------------------------------------------------------------------------------
12410  * [0] | RW | 0x0 | ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE
12411  * [3:1] | ??? | Unknown | *UNDEFINED*
12412  * [4] | RW | 0x1 | ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS
12413  * [7:5] | ??? | Unknown | *UNDEFINED*
12414  * [8] | RW | 0x1 | ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE
12415  * [31:9] | ??? | Unknown | *UNDEFINED*
12416  *
12417  */
12418 /*
12419  * Field : chip_interleave_enable
12420  *
12421  * This bit informs the controller to enable or disable interleaving
12422  *
12423  * among banks/LUNS to increase the net performance of the controller.
12424  *
12425  * [list][*]1 - Enable interleaving [*]0 - Disable Interleaving[/list]
12426  *
12427  * Field Access Macros:
12428  *
12429  */
12430 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field. */
12431 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_LSB 0
12432 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field. */
12433 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_MSB 0
12434 /* The width in bits of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field. */
12435 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_WIDTH 1
12436 /* The mask used to set the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field value. */
12437 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_SET_MSK 0x00000001
12438 /* The mask used to clear the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field value. */
12439 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_CLR_MSK 0xfffffffe
12440 /* The reset value of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field. */
12441 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_RESET 0x0
12442 /* Extracts the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE field value from a register. */
12443 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_GET(value) (((value) & 0x00000001) >> 0)
12444 /* Produces a ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE register field value suitable for setting the register. */
12445 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE_SET(value) (((value) << 0) & 0x00000001)
12446 
12447 /*
12448  * Field : allow_int_reads_within_luns
12449  *
12450  * This bit informs the controller to enable or disable simultaneous read accesses
12451  *
12452  * to different LUNS in the same bank. This bit is of importance only if the
12453  * controller
12454  *
12455  * supports interleaved operations among LUNs and if the device has multiple LUNS.
12456  *
12457  * If the bit is disabled, the controller will send read commands to different LUNS
12458  * of
12459  *
12460  * of the same bank only sequentially and if enabled, the controller will issue
12461  * simultaneous
12462  *
12463  * read accesses to LUNS of same bank if required.
12464  *
12465  * [list][*]1 - Enable [*]0 - Disable[/list]
12466  *
12467  * Field Access Macros:
12468  *
12469  */
12470 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field. */
12471 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_LSB 4
12472 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field. */
12473 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_MSB 4
12474 /* The width in bits of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field. */
12475 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_WIDTH 1
12476 /* The mask used to set the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field value. */
12477 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_SET_MSK 0x00000010
12478 /* The mask used to clear the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field value. */
12479 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_CLR_MSK 0xffffffef
12480 /* The reset value of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field. */
12481 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_RESET 0x1
12482 /* Extracts the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS field value from a register. */
12483 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
12484 /* Produces a ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS register field value suitable for setting the register. */
12485 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
12486 
12487 /*
12488  * Field : cmd_dma_error_enable
12489  *
12490  * This bit informs the CDMA channels to stop working on any new MAP10 Command
12491  * DMAcommands from the host after encountering an
12492  *
12493  * error situation till the error bit for that corresponding channel is cleared in
12494  * the cmd_dma_channel_error register by f/w.
12495  *
12496  * When the CDMA channel encounters an error, it will set the corresponding error
12497  * bit in cmd_dma_channel_error register
12498  *
12499  * If this bit is set, the channel will stop executing any further commands
12500  *
12501  * till f/w comes and clears the error bit in the cmd_dma_channel_error_register.
12502  *
12503  * If this bit is not set, controller will still keep on executing new commands
12504  * issued from f/w.
12505  *
12506  * Field Access Macros:
12507  *
12508  */
12509 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field. */
12510 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_LSB 8
12511 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field. */
12512 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_MSB 8
12513 /* The width in bits of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field. */
12514 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_WIDTH 1
12515 /* The mask used to set the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field value. */
12516 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_SET_MSK 0x00000100
12517 /* The mask used to clear the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field value. */
12518 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_CLR_MSK 0xfffffeff
12519 /* The reset value of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field. */
12520 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_RESET 0x1
12521 /* Extracts the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE field value from a register. */
12522 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_GET(value) (((value) & 0x00000100) >> 8)
12523 /* Produces a ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE register field value suitable for setting the register. */
12524 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE_SET(value) (((value) << 8) & 0x00000100)
12525 
12526 #ifndef __ASSEMBLY__
12527 /*
12528  * WARNING: The C register and register group struct declarations are provided for
12529  * convenience and illustrative purposes. They should, however, be used with
12530  * caution as the C language standard provides no guarantees about the alignment or
12531  * atomicity of device memory accesses. The recommended practice for coding device
12532  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12533  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12534  * alt_write_dword() functions for 64 bit registers.
12535  *
12536  * The struct declaration for register ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS.
12537  */
12538 struct ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_s
12539 {
12540  volatile uint32_t chip_interleave_enable : 1; /* ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CHIP_INTERLEAVE_ENABLE */
12541  uint32_t : 3; /* *UNDEFINED* */
12542  volatile uint32_t allow_int_reads_within_luns : 1; /* ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ALLOW_INT_READS_WITHIN_LUNS */
12543  uint32_t : 3; /* *UNDEFINED* */
12544  volatile uint32_t cmd_dma_error_enable : 1; /* ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_CMD_DMA_ERROR_ENABLE */
12545  uint32_t : 23; /* *UNDEFINED* */
12546 };
12547 
12548 /* The typedef declaration for register ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS. */
12549 typedef struct ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_s ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_t;
12550 #endif /* __ASSEMBLY__ */
12551 
12552 /* The reset value of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS register. */
12553 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_RESET 0x00000110
12554 /* The byte offset of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS register from the beginning of the component. */
12555 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_OFST 0x80
12556 /* The address of the ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS register. */
12557 #define ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_OFST))
12558 
12559 /*
12560  * Register : rescan_buffer_flag
12561  *
12562  * Rescan buffer flag.
12563  *
12564  * Register Layout
12565  *
12566  * Bits | Access | Reset | Description
12567  * :-------|:-------|:--------|:-------------------------------------
12568  * [3:0] | RW | 0x0 | ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG
12569  * [31:4] | ??? | Unknown | *UNDEFINED*
12570  *
12571  */
12572 /*
12573  * Field : flag
12574  *
12575  * This register can be used to force rescan of buffer flags in any of the cmd-dma
12576  * channels.
12577  *
12578  * The bit index decides the Channel number. Cmd-dma would rescan the buffer flag
12579  * for matching
12580  *
12581  * condition and it executes the descriptor if it is ready. Hardware clears this
12582  * register after
12583  *
12584  * generating the trigger event.
12585  *
12586  * Field Access Macros:
12587  *
12588  */
12589 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field. */
12590 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_LSB 0
12591 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field. */
12592 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_MSB 3
12593 /* The width in bits of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field. */
12594 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_WIDTH 4
12595 /* The mask used to set the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field value. */
12596 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_SET_MSK 0x0000000f
12597 /* The mask used to clear the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field value. */
12598 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_CLR_MSK 0xfffffff0
12599 /* The reset value of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field. */
12600 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_RESET 0x0
12601 /* Extracts the ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG field value from a register. */
12602 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_GET(value) (((value) & 0x0000000f) >> 0)
12603 /* Produces a ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG register field value suitable for setting the register. */
12604 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG_SET(value) (((value) << 0) & 0x0000000f)
12605 
12606 #ifndef __ASSEMBLY__
12607 /*
12608  * WARNING: The C register and register group struct declarations are provided for
12609  * convenience and illustrative purposes. They should, however, be used with
12610  * caution as the C language standard provides no guarantees about the alignment or
12611  * atomicity of device memory accesses. The recommended practice for coding device
12612  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12613  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12614  * alt_write_dword() functions for 64 bit registers.
12615  *
12616  * The struct declaration for register ALT_NAND_DMA_RESCAN_BUFFER_FLAG.
12617  */
12618 struct ALT_NAND_DMA_RESCAN_BUFFER_FLAG_s
12619 {
12620  volatile uint32_t flag : 4; /* ALT_NAND_DMA_RESCAN_BUFFER_FLAG_FLAG */
12621  uint32_t : 28; /* *UNDEFINED* */
12622 };
12623 
12624 /* The typedef declaration for register ALT_NAND_DMA_RESCAN_BUFFER_FLAG. */
12625 typedef struct ALT_NAND_DMA_RESCAN_BUFFER_FLAG_s ALT_NAND_DMA_RESCAN_BUFFER_FLAG_t;
12626 #endif /* __ASSEMBLY__ */
12627 
12628 /* The reset value of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG register. */
12629 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_RESET 0x00000000
12630 /* The byte offset of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG register from the beginning of the component. */
12631 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_OFST 0x90
12632 /* The address of the ALT_NAND_DMA_RESCAN_BUFFER_FLAG register. */
12633 #define ALT_NAND_DMA_RESCAN_BUFFER_FLAG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_RESCAN_BUFFER_FLAG_OFST))
12634 
12635 /*
12636  * Register : no_of_blocks_per_lun
12637  *
12638  * Register Layout
12639  *
12640  * Bits | Access | Reset | Description
12641  * :--------|:-------|:--------|:---------------------------------------------------------------
12642  * [3:0] | RW | 0xf | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE
12643  * [23:4] | ??? | Unknown | *UNDEFINED*
12644  * [24] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP
12645  * [27:25] | ??? | Unknown | *UNDEFINED*
12646  * [28] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC
12647  * [31:29] | ??? | Unknown | *UNDEFINED*
12648  *
12649  */
12650 /*
12651  * Field : value
12652  *
12653  * Indicates the first block of next LUN. This information is used for extracting
12654  * the target LUN during LUN interleaving.
12655  *
12656  * After Initialization, if the controller detects an ONFi device,
12657  *
12658  * this field is automatically updated by the controller.
12659  *
12660  * For other devices, software will need to write to this register
12661  *
12662  * for proper interleaving.
12663  *
12664  * The value in this register is interpreted as follows-
12665  *
12666  * [list][*]0 - Next LUN starts from 1024.
12667  *
12668  * [*]1 - Next LUN starts from 2048.
12669  *
12670  * [*]2 - Next LUN starts from 4096 and so on...
12671  *
12672  * [/list]
12673  *
12674  * Field Access Macros:
12675  *
12676  */
12677 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12678 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
12679 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12680 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
12681 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12682 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
12683 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
12684 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
12685 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value. */
12686 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
12687 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field. */
12688 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
12689 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE field value from a register. */
12690 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
12691 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value suitable for setting the register. */
12692 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
12693 
12694 /*
12695  * Field : update_sync_before_prog_comp
12696  *
12697  * Update SYNC Pointer after the data is written to flash and dont wait for program
12698  *
12699  * to complete. If this value is 0, CMD DMA waits for page program to get over
12700  *
12701  * before updating the sync pointer. This bit should be set to 0 if the controller
12702  *
12703  * is being accessed in non-Command DMA mode.
12704  *
12705  * Field Access Macros:
12706  *
12707  */
12708 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12709 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24
12710 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12711 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24
12712 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12713 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1
12714 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value. */
12715 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000
12716 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value. */
12717 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff
12718 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field. */
12719 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0
12720 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP field value from a register. */
12721 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET(value) (((value) & 0x01000000) >> 24)
12722 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value suitable for setting the register. */
12723 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET(value) (((value) << 24) & 0x01000000)
12724 
12725 /*
12726  * Field : issue_read_before_sync
12727  *
12728  * Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the
12729  * data is read
12730  *
12731  * from the device (for this load) only after the SYNC condition has been
12732  * satisfied.
12733  *
12734  * If this value is 0, CMD DMA waits for SYNC before issuing a READ command.
12735  *
12736  * This bit should be set to 0 if the controller is being accessed in non-Command
12737  * DMA mode.
12738  *
12739  * Field Access Macros:
12740  *
12741  */
12742 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field. */
12743 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_LSB 28
12744 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field. */
12745 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_MSB 28
12746 /* The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field. */
12747 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_WIDTH 1
12748 /* The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field value. */
12749 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_SET_MSK 0x10000000
12750 /* The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field value. */
12751 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_CLR_MSK 0xefffffff
12752 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field. */
12753 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_RESET 0x0
12754 /* Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC field value from a register. */
12755 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28)
12756 /* Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC register field value suitable for setting the register. */
12757 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000)
12758 
12759 #ifndef __ASSEMBLY__
12760 /*
12761  * WARNING: The C register and register group struct declarations are provided for
12762  * convenience and illustrative purposes. They should, however, be used with
12763  * caution as the C language standard provides no guarantees about the alignment or
12764  * atomicity of device memory accesses. The recommended practice for coding device
12765  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12766  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12767  * alt_write_dword() functions for 64 bit registers.
12768  *
12769  * The struct declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN.
12770  */
12771 struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
12772 {
12773  volatile uint32_t value : 4; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE */
12774  uint32_t : 20; /* *UNDEFINED* */
12775  volatile uint32_t update_sync_before_prog_comp : 1; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP */
12776  uint32_t : 3; /* *UNDEFINED* */
12777  volatile uint32_t issue_read_before_sync : 1; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_READ_BEFORE_SYNC */
12778  uint32_t : 3; /* *UNDEFINED* */
12779 };
12780 
12781 /* The typedef declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN. */
12782 typedef struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t;
12783 #endif /* __ASSEMBLY__ */
12784 
12785 /* The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register. */
12786 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f
12787 /* The byte offset of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register from the beginning of the component. */
12788 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0
12789 /* The address of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register. */
12790 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST))
12791 
12792 /*
12793  * Register : lun_status_cmd
12794  *
12795  * Indicates the command to be sent while checking status of the next LUN.
12796  *
12797  * Register Layout
12798  *
12799  * Bits | Access | Reset | Description
12800  * :--------|:-------|:--------|:----------------------------------
12801  * [15:0] | RW | 0x7878 | ALT_NAND_DMA_LUN_STATUS_CMD_VALUE
12802  * [31:16] | ??? | Unknown | *UNDEFINED*
12803  *
12804  */
12805 /*
12806  * Field : value
12807  *
12808  * [list][*]7:0 - Indicates the command to check the
12809  *
12810  * status of the first LUN/Die.
12811  *
12812  * [*]15:8 - Indicates the command to check the
12813  *
12814  * status of the other LUN/Die.[/list]
12815  *
12816  * Field Access Macros:
12817  *
12818  */
12819 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field. */
12820 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_LSB 0
12821 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field. */
12822 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_MSB 15
12823 /* The width in bits of the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field. */
12824 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_WIDTH 16
12825 /* The mask used to set the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field value. */
12826 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_SET_MSK 0x0000ffff
12827 /* The mask used to clear the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field value. */
12828 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_CLR_MSK 0xffff0000
12829 /* The reset value of the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field. */
12830 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_RESET 0x7878
12831 /* Extracts the ALT_NAND_DMA_LUN_STATUS_CMD_VALUE field value from a register. */
12832 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12833 /* Produces a ALT_NAND_DMA_LUN_STATUS_CMD_VALUE register field value suitable for setting the register. */
12834 #define ALT_NAND_DMA_LUN_STATUS_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12835 
12836 #ifndef __ASSEMBLY__
12837 /*
12838  * WARNING: The C register and register group struct declarations are provided for
12839  * convenience and illustrative purposes. They should, however, be used with
12840  * caution as the C language standard provides no guarantees about the alignment or
12841  * atomicity of device memory accesses. The recommended practice for coding device
12842  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12843  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12844  * alt_write_dword() functions for 64 bit registers.
12845  *
12846  * The struct declaration for register ALT_NAND_DMA_LUN_STATUS_CMD.
12847  */
12848 struct ALT_NAND_DMA_LUN_STATUS_CMD_s
12849 {
12850  volatile uint32_t value : 16; /* ALT_NAND_DMA_LUN_STATUS_CMD_VALUE */
12851  uint32_t : 16; /* *UNDEFINED* */
12852 };
12853 
12854 /* The typedef declaration for register ALT_NAND_DMA_LUN_STATUS_CMD. */
12855 typedef struct ALT_NAND_DMA_LUN_STATUS_CMD_s ALT_NAND_DMA_LUN_STATUS_CMD_t;
12856 #endif /* __ASSEMBLY__ */
12857 
12858 /* The reset value of the ALT_NAND_DMA_LUN_STATUS_CMD register. */
12859 #define ALT_NAND_DMA_LUN_STATUS_CMD_RESET 0x00007878
12860 /* The byte offset of the ALT_NAND_DMA_LUN_STATUS_CMD register from the beginning of the component. */
12861 #define ALT_NAND_DMA_LUN_STATUS_CMD_OFST 0xb0
12862 /* The address of the ALT_NAND_DMA_LUN_STATUS_CMD register. */
12863 #define ALT_NAND_DMA_LUN_STATUS_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_LUN_STATUS_CMD_OFST))
12864 
12865 /*
12866  * Register : cmd_dma_channel_error
12867  *
12868  * Bits indicating CMD-DMA channel receiving an error condition. To get more
12869  * information on the error, s/w needs to read the status field of the descriptor.
12870  *
12871  * Register Layout
12872  *
12873  * Bits | Access | Reset | Description
12874  * :-------|:-------|:--------|:--------------------------------------------
12875  * [0] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0
12876  * [1] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1
12877  * [2] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2
12878  * [3] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3
12879  * [31:4] | ??? | Unknown | *UNDEFINED*
12880  *
12881  */
12882 /*
12883  * Field : channel0
12884  *
12885  * CMD-DMA channel 0 received an error.
12886  *
12887  * Field Access Macros:
12888  *
12889  */
12890 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12891 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0
12892 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12893 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0
12894 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12895 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1
12896 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value. */
12897 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001
12898 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value. */
12899 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe
12900 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field. */
12901 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0
12902 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 field value from a register. */
12903 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12904 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value suitable for setting the register. */
12905 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12906 
12907 /*
12908  * Field : channel1
12909  *
12910  * CMD-DMA channel 1 received an error.
12911  *
12912  * Field Access Macros:
12913  *
12914  */
12915 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12916 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1
12917 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12918 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1
12919 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12920 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1
12921 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value. */
12922 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002
12923 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value. */
12924 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd
12925 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field. */
12926 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0
12927 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 field value from a register. */
12928 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12929 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value suitable for setting the register. */
12930 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12931 
12932 /*
12933  * Field : channel2
12934  *
12935  * CMD-DMA channel 2 received an error.
12936  *
12937  * Field Access Macros:
12938  *
12939  */
12940 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12941 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2
12942 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12943 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2
12944 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12945 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1
12946 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value. */
12947 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004
12948 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value. */
12949 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb
12950 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field. */
12951 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0
12952 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 field value from a register. */
12953 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12954 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value suitable for setting the register. */
12955 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12956 
12957 /*
12958  * Field : channel3
12959  *
12960  * CMD-DMA channel 3 received an error.
12961  *
12962  * Field Access Macros:
12963  *
12964  */
12965 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12966 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3
12967 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12968 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3
12969 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12970 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1
12971 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value. */
12972 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008
12973 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value. */
12974 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7
12975 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field. */
12976 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0
12977 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 field value from a register. */
12978 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12979 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value suitable for setting the register. */
12980 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12981 
12982 #ifndef __ASSEMBLY__
12983 /*
12984  * WARNING: The C register and register group struct declarations are provided for
12985  * convenience and illustrative purposes. They should, however, be used with
12986  * caution as the C language standard provides no guarantees about the alignment or
12987  * atomicity of device memory accesses. The recommended practice for coding device
12988  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
12989  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
12990  * alt_write_dword() functions for 64 bit registers.
12991  *
12992  * The struct declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR.
12993  */
12994 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
12995 {
12996  volatile uint32_t channel0 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 */
12997  volatile uint32_t channel1 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 */
12998  volatile uint32_t channel2 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 */
12999  volatile uint32_t channel3 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 */
13000  uint32_t : 28; /* *UNDEFINED* */
13001 };
13002 
13003 /* The typedef declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR. */
13004 typedef struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t;
13005 #endif /* __ASSEMBLY__ */
13006 
13007 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register. */
13008 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000
13009 /* The byte offset of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register from the beginning of the component. */
13010 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0
13011 /* The address of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register. */
13012 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST))
13013 
13014 /*
13015  * Register : cmd_dma_channel_error_en
13016  *
13017  * Enable bits indicating CMD-DMA channel receiving an error condition. To get more
13018  * information on the error, s/w needs to read the status field of the descriptor.
13019  *
13020  * Register Layout
13021  *
13022  * Bits | Access | Reset | Description
13023  * :-------|:-------|:--------|:-----------------------------------------------
13024  * [0] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0
13025  * [1] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1
13026  * [2] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2
13027  * [3] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3
13028  * [31:4] | ??? | Unknown | *UNDEFINED*
13029  *
13030  */
13031 /*
13032  * Field : channel0
13033  *
13034  * enable bit for CMD-DMA channel 0 receiving an error
13035  *
13036  * Field Access Macros:
13037  *
13038  */
13039 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
13040 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_LSB 0
13041 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
13042 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_MSB 0
13043 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
13044 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_WIDTH 1
13045 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value. */
13046 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET_MSK 0x00000001
13047 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value. */
13048 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_CLR_MSK 0xfffffffe
13049 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field. */
13050 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_RESET 0x0
13051 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 field value from a register. */
13052 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
13053 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 register field value suitable for setting the register. */
13054 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
13055 
13056 /*
13057  * Field : channel1
13058  *
13059  * enable bit for CMD-DMA channel 1 receiving an error
13060  *
13061  * Field Access Macros:
13062  *
13063  */
13064 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
13065 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_LSB 1
13066 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
13067 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_MSB 1
13068 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
13069 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_WIDTH 1
13070 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value. */
13071 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET_MSK 0x00000002
13072 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value. */
13073 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_CLR_MSK 0xfffffffd
13074 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field. */
13075 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_RESET 0x0
13076 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 field value from a register. */
13077 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
13078 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 register field value suitable for setting the register. */
13079 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
13080 
13081 /*
13082  * Field : channel2
13083  *
13084  * enable bit for CMD-DMA channel 2 receiving an error
13085  *
13086  * Field Access Macros:
13087  *
13088  */
13089 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
13090 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_LSB 2
13091 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
13092 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_MSB 2
13093 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
13094 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_WIDTH 1
13095 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value. */
13096 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET_MSK 0x00000004
13097 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value. */
13098 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_CLR_MSK 0xfffffffb
13099 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field. */
13100 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_RESET 0x0
13101 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 field value from a register. */
13102 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
13103 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 register field value suitable for setting the register. */
13104 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
13105 
13106 /*
13107  * Field : channel3
13108  *
13109  * enable bit for CMD-DMA channel 3 receiving an error
13110  *
13111  * Field Access Macros:
13112  *
13113  */
13114 /* The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
13115 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_LSB 3
13116 /* The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
13117 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_MSB 3
13118 /* The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
13119 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_WIDTH 1
13120 /* The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value. */
13121 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET_MSK 0x00000008
13122 /* The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value. */
13123 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_CLR_MSK 0xfffffff7
13124 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field. */
13125 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_RESET 0x0
13126 /* Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 field value from a register. */
13127 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
13128 /* Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 register field value suitable for setting the register. */
13129 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
13130 
13131 #ifndef __ASSEMBLY__
13132 /*
13133  * WARNING: The C register and register group struct declarations are provided for
13134  * convenience and illustrative purposes. They should, however, be used with
13135  * caution as the C language standard provides no guarantees about the alignment or
13136  * atomicity of device memory accesses. The recommended practice for coding device
13137  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13138  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13139  * alt_write_dword() functions for 64 bit registers.
13140  *
13141  * The struct declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN.
13142  */
13143 struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
13144 {
13145  volatile uint32_t channel0 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0 */
13146  volatile uint32_t channel1 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1 */
13147  volatile uint32_t channel2 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2 */
13148  volatile uint32_t channel3 : 1; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3 */
13149  uint32_t : 28; /* *UNDEFINED* */
13150 };
13151 
13152 /* The typedef declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN. */
13153 typedef struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t;
13154 #endif /* __ASSEMBLY__ */
13155 
13156 /* The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN register. */
13157 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_RESET 0x00000000
13158 /* The byte offset of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN register from the beginning of the component. */
13159 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST 0xd0
13160 /* The address of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN register. */
13161 #define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST))
13162 
13163 #ifndef __ASSEMBLY__
13164 /*
13165  * WARNING: The C register and register group struct declarations are provided for
13166  * convenience and illustrative purposes. They should, however, be used with
13167  * caution as the C language standard provides no guarantees about the alignment or
13168  * atomicity of device memory accesses. The recommended practice for coding device
13169  * drivers is to use the SoCAL access macros in conjunction with alt_read_word()
13170  * and alt_write_word() functions for 32 bit registers and alt_read_dword() and
13171  * alt_write_dword() functions for 64 bit registers.
13172  *
13173  * The struct declaration for register group ALT_NAND_DMA.
13174  */
13175 struct ALT_NAND_DMA_s
13176 {
13177  volatile ALT_NAND_DMA_DMA_ENABLE_t dma_enable; /* ALT_NAND_DMA_DMA_ENABLE */
13178  volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
13179  volatile ALT_NAND_DMA_DMA_INTR_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
13180  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
13181  volatile ALT_NAND_DMA_DMA_INTR_EN_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
13182  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
13183  volatile ALT_NAND_DMA_TARGET_ERR_ADDR_LO_t target_err_addr_lo; /* ALT_NAND_DMA_TARGET_ERR_ADDR_LO */
13184  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
13185  volatile ALT_NAND_DMA_TARGET_ERR_ADDR_HI_t target_err_addr_hi; /* ALT_NAND_DMA_TARGET_ERR_ADDR_HI */
13186  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
13187  volatile ALT_NAND_DMA_CHNL_ACTIVE_t chnl_active; /* ALT_NAND_DMA_CHNL_ACTIVE */
13188  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
13189  volatile ALT_NAND_DMA_FLASH_BURST_LENGTH_t flash_burst_length; /* ALT_NAND_DMA_FLASH_BURST_LENGTH */
13190  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
13191  volatile ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS */
13192  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
13193  volatile ALT_NAND_DMA_RESCAN_BUFFER_FLAG_t rescan_buffer_flag; /* ALT_NAND_DMA_RESCAN_BUFFER_FLAG */
13194  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
13195  volatile ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
13196  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
13197  volatile ALT_NAND_DMA_LUN_STATUS_CMD_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STATUS_CMD */
13198  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
13199  volatile ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t cmd_dma_channel_error; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR */
13200  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
13201  volatile ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t cmd_dma_channel_error_en; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN */
13202 };
13203 
13204 /* The typedef declaration for register group ALT_NAND_DMA. */
13205 typedef struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
13206 /* The struct declaration for the raw register contents of register group ALT_NAND_DMA. */
13207 struct ALT_NAND_DMA_raw_s
13208 {
13209  volatile uint32_t dma_enable; /* ALT_NAND_DMA_DMA_ENABLE */
13210  volatile uint32_t _pad_0x4_0x1f[7]; /* *UNDEFINED* */
13211  volatile uint32_t dma_intr; /* ALT_NAND_DMA_DMA_INTR */
13212  volatile uint32_t _pad_0x24_0x2f[3]; /* *UNDEFINED* */
13213  volatile uint32_t dma_intr_en; /* ALT_NAND_DMA_DMA_INTR_EN */
13214  volatile uint32_t _pad_0x34_0x3f[3]; /* *UNDEFINED* */
13215  volatile uint32_t target_err_addr_lo; /* ALT_NAND_DMA_TARGET_ERR_ADDR_LO */
13216  volatile uint32_t _pad_0x44_0x4f[3]; /* *UNDEFINED* */
13217  volatile uint32_t target_err_addr_hi; /* ALT_NAND_DMA_TARGET_ERR_ADDR_HI */
13218  volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
13219  volatile uint32_t chnl_active; /* ALT_NAND_DMA_CHNL_ACTIVE */
13220  volatile uint32_t _pad_0x64_0x6f[3]; /* *UNDEFINED* */
13221  volatile uint32_t flash_burst_length; /* ALT_NAND_DMA_FLASH_BURST_LENGTH */
13222  volatile uint32_t _pad_0x74_0x7f[3]; /* *UNDEFINED* */
13223  volatile uint32_t chip_interleave_enable_and_allow_int_reads; /* ALT_NAND_DMA_CHIP_INTERLEAVE_ENABLE_AND_ALLOW_INT_READS */
13224  volatile uint32_t _pad_0x84_0x8f[3]; /* *UNDEFINED* */
13225  volatile uint32_t rescan_buffer_flag; /* ALT_NAND_DMA_RESCAN_BUFFER_FLAG */
13226  volatile uint32_t _pad_0x94_0x9f[3]; /* *UNDEFINED* */
13227  volatile uint32_t no_of_blocks_per_lun; /* ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN */
13228  volatile uint32_t _pad_0xa4_0xaf[3]; /* *UNDEFINED* */
13229  volatile uint32_t lun_status_cmd; /* ALT_NAND_DMA_LUN_STATUS_CMD */
13230  volatile uint32_t _pad_0xb4_0xbf[3]; /* *UNDEFINED* */
13231  volatile uint32_t cmd_dma_channel_error; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR */
13232  volatile uint32_t _pad_0xc4_0xcf[3]; /* *UNDEFINED* */
13233  volatile uint32_t cmd_dma_channel_error_en; /* ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN */
13234 };
13235 
13236 /* The typedef declaration for the raw register contents of register group ALT_NAND_DMA. */
13237 typedef struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;
13238 #endif /* __ASSEMBLY__ */
13239 
13240 
13241 #ifdef __cplusplus
13242 }
13243 #endif /* __cplusplus */
13244 #endif /* __ALT_SOCAL_NAND_H__ */
13245